CY9A340NB Series 32-bit ARM Cortex -M3 FM3 Microcontroller

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The products which are described in this data sheet are placed into TYPE6 product categories in FM3 Family Peripheral Manual. Features 32-bit ARM Cortex -M3 Core Processor version: r2p1 Up to 40 MHz Frequency Operation Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as "Cypress" document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY9A340NB Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller The CY9A340NB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, and Communication Interfaces (USB, UART, CSIO, I2C). The products which are described in this data sheet are placed into TYPE6 product categories in FM3 Family Peripheral Manual. Features 32-bit ARM® Cortex®-M3 Core Processor version: r2p1 Up to 40 MHz Frequency Operation Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] Dual operation Flash memory Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously. Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank) Work area: 32 Kbytes (lower bank) Read cycle: 0 wait-cycle Security function for code protection [SRAM] This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. SRAM0: Up to 16 Kbytes SRAM1: Up to 16 Kbytes External Bus Interface* Supports SRAM, NOR Flash memory device Up to 8 chip selects 8-/16-bit Data width Up to 25-bit Address bit Maximum area size: Up to 256 Mbytes Supports Address/Data multiplex Supports external RDY function *: CY9AF341LB, F342LB and F344LB do not support External Bus Interface. USB Interface The USB interface is composed of Device and Host. PLL for USB is built-in, USB clock can be generated by multiplication of Main clock. [USB device] USB2.0 Full-Speed supported Max 6 EndPoint supported EndPoint 0 is control transfer EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or Isochronous-transfer EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer EndPoint 1 to 5 is comprised of Double Buffers. The size of each endpoint is according to the follows. - Endpoint 0, 2 to 5: 64 bytes - Endpoint 1: 256 bytes [USB host] USB2.0 Full/Low-speed supported Bulk-transfer, interrupt-transfer and Isochronous-transfer support Automatic detection of connected/disconnected USB Device Automatic processing of the IN/OUT token handshake packet Max 256-byte packet-length supported Wake-up function supported Cypress Semiconductor Corporation · Document Number: 002-05635 Rev. *C 198 Champion Court · San Jose, CA 95134-1709 · 408-943-2600 Revised May 16, 2019 CY9A340NB Series Multi-function Serial Interface (Max 8 channels) 4 channels with 16steps×9-bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3) Operation mode is selectable from the followings for each channel. UART CSIO I2C [UART] Full-duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator External clock available as a serial clock Hardware Flow control* : Automatically control the transmission by CTS/RTS (only ch.4) Various error detection functions available (parity errors, framing errors, and overrun errors) *: CY9AF341LB, F342LB and F344LB do not support Hardware Flow control. [CSIO] Full-duplex double buffer Built-in dedicated baud rate generator Overrun error detection function available [I2C] Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported DMA Controller (8 channels) The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously. 8 independently configured and operated channels Transfer can be started by software or request from the built-in peripherals Transfer address area: 32-bit (4 Gbytes) Transfer mode: Block transfer/Burst transfer/Demand transfer Transfer data type: byte/half-word/word Transfer block count: 1 to 16 Number of transfers: 1 to 65536 A/D Converter (Max 24 channels) [12-bit A/D Converter] Successive Approximation type Built-in 2 units Conversion time: 2.0 s @ 2.7 V to 3.6 V Priority conversion available (priority at 2 levels) Scanning conversion mode Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps) Base Timer (Max 8 channels) Operation mode is selectable from the followings for each channel. 16-bit PWM timer 16-bit PPG timer 16-/32-bit reload timer 16-/32-bit PWC timer General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to. Capable of pull-up control per pin Capable of reading pin level directly Built-in the port relocate function Up to 83 fast general-purpose I/O Ports@100 pin Package Some ports are 5V tolerant I/O. See Pin Description to confirm the corresponding pins. Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel. Free-running Periodic (=Reload) One-shot Document Number: 002-05635 Rev. *C Page 2 of 126 CY9A340NB Series HDMI-CEC/Remote Control Receiver (Up to 2 channels) HDMI-CEC transmitter Header block automatic transmission by judging Signal free Generating status interrupt by detecting Arbitration lost Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK) HDMI-CEC receiver Automatic ACK reply function available Line error detection function available Remote control receiver 4 bytes reception buffer Repeat code detection function available Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99. The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. Timer interrupt function after set time or each set time. Capable of rewriting the time with continuing the time count. Leap year automatic count is available. Watch Counter The Watch counter is used for wake up from sleep and timer mode. Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz External Interrupt Controller Unit Up to 16 external interrupt input pins Include one non-maskable interrupt (NMI) input pin Watchdog Timer (2 channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog. The Hardware watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the Hardware watchdog is active in any low-power consumption modes except RTC, Stop, Deep Standby RTC, Deep Standby Stop modes. CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. CCITT CRC16 and IEEE-802.3 CRC32 are supported. CCITT CRC16 Generator Polynomial: 0x1021 IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 Clock and Reset [Clocks] Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL). Main Clock: 4 MHz to 48 MHz Sub Clock: 32.768 kHz Built-in high-speed CR Clock:4 MHz Built-in low-speed CR Clock: 100 kHz Main PLL Clock [Resets] Reset requests from INITX pin Power-on reset Software reset Watchdog timers reset Low-voltage detection reset Clock Super Visor reset Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks. External clock failure (clock stop) is detected, reset is asserted. External frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset. LVD1: error reporting via interrupt LVD2: auto-reset operation Document Number: 002-05635 Rev. *C Page 3 of 126 CY9A340NB Series Low-Power Consumption Mode Six low-power consumption modes supported. Sleep Timer RTC Stop Deep Standby RTC (selectable between keeping the value of RAM and not) Deep Standby Stop (selectable between keeping the value of RAM and not) Debug Serial Wire JTAG Debug Port (SWJ-DP) Embedded Trace Macrocells (ETM).* *: CY9AF341LB/MB, F342LB/MB and F344LB/MB support only SWJ-DP. Unique ID Unique value of the device (41-bit) is set. Power Supply Wide range voltage: VCC = 1.65 V to 3.6 V VCC = 3.0 V to 3.6 V (when USB is used) Document Number: 002-05635 Rev. *C Page 4 of 126 CY9A340NB Series Contents 1. Product Lineup.................................................................................................................................................................. 7 2. Packages ........................................................................................................................................................................... 8 3. Pin Assignment ................................................................................................................................................................. 9 4. List of Pin Functions....................................................................................................................................................... 16 5. I/O Circuit Type ............................................................................................................................................................... 40 6. Handling Precautions ..................................................................................................................................................... 44 7. Handling Devices ............................................................................................................................................................ 47 8. Block Diagram ................................................................................................................................................................. 49 9. Memory Size .................................................................................................................................................................... 50 10. Memory Map .................................................................................................................................................................... 50 11. Pin Status in Each CPU State ........................................................................................................................................ 53 12. Electrical Characteristics ............................................................................................................................................... 61 12.1 Absolute Maximum Ratings ......................................................................................................................................... 61 12.2 Recommended Operating Conditions ......................................................................................................................... 62 12.3 DC Characteristics ...................................................................................................................................................... 63 12.3.1 Current rating ............................................................................................................................................................... 63 12.3.2 Pin Characteristics ....................................................................................................................................................... 66 12.4 AC Characteristics....................................................................................................................................................... 67 12.4.1 Main Clock Input Characteristics.................................................................................................................................. 67 12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 68 12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 68 12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL)................................... 69 12.4.5 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock of the Main PLL)........................................................................................................................................................... 69 12.4.6 Reset Input Characteristics .......................................................................................................................................... 71 12.4.7 Power-on Reset Timing................................................................................................................................................ 71 12.4.8 External Bus Timing ..................................................................................................................................................... 72 12.4.9 Base Timer Input Timing .............................................................................................................................................. 79 12.4.10 CSIO/UART Timing .................................................................................................................................................. 80 12.4.11 External Input Timing................................................................................................................................................ 89 12.4.12 I2C Timing ................................................................................................................................................................. 90 12.4.13 ETM Timing .............................................................................................................................................................. 91 12.4.14 JTAG Timing............................................................................................................................................................. 92 12.5 12-bit A/D Converter.................................................................................................................................................... 93 12.6 USB Characteristics .................................................................................................................................................... 96 12.7 Low-Voltage Detection Characteristics...................................................................................................................... 100 12.7.1 Low-Voltage Detection Reset..................................................................................................................................... 100 12.7.2 Interrupt of Low-Voltage Detection............................................................................................................................. 101 12.8 Flash Memory Write/Erase Characteristics ............................................................................................................... 102 12.8.1 Write / Erase time....................................................................................................................................................... 102 12.8.2 Write cycles and data hold time ................................................................................................................................. 102 12.9 Return Time from Low-Power Consumption Mode.................................................................................................... 103 12.9.1 Return Factor: Interrupt/WKUP .................................................................................................................................. 103 12.9.2 Return Factor: Reset .................................................................................................................................................. 105 13. Ordering Information .................................................................................................................................................... 107 14. Package Dimensions .................................................................................................................................................... 109 15. Errata.............................................................................................................................................................................. 118 Document Number: 002-05635 Rev. *C Page 5 of 126 CY9A340NB Series 16. Major Changes .............................................................................................................................................................. 122 Document History............................................................................................................................................................... 125 Sales, Solutions, and Legal Information........................................................................................................................... 126 Document Number: 002-05635 Rev. *C Page 6 of 126 CY9A340NB Series 1. Product Lineup Memory size Product name CY9AF341LB/MB/NB CY9AF342LB/MB/NB CY9AF344LB/MB/NB On-chip Flash memory On-chip SRAM Main area Work area SRAM0 SRAM1 Total 64 Kbytes 32 Kbytes 8 Kbytes 8 Kbytes 16 Kbytes 128 Kbytes 32 Kbytes 8 Kbytes 8 Kbytes 16 Kbytes 256 Kbytes 32 Kbytes 16 Kbytes 16 Kbytes 32 Kbytes Function Product name CY9AF341LB CY9AF342LB CY9AF344LB CY9AF341MB CY9AF342MB CY9AF344MB CY9AF341NB CY9AF342NB CY9AF344NB Pin count 64 80/96 100/112 CPU Freq. Cortex-M3 40 MHz Power supply voltage range 1.65 V to 3.6 V USB2.0 (Device/Host) 1 ch. DMAC 8 ch. External Bus Interface Addr: 21-bit (Max) Addr: 25-bit (Max) R/W Data: 8-bit (Max) R/W Data: 8-/16-bit (Max) - CS: 4 (Max) CS: 8 (Max) Support: SRAM, NOR Support: SRAM, Flash memory NOR Flash memory Multi-function Serial Interface (UART/CSIO/I2C) 8 ch. (Max) ch.4 to ch.7: FIFO (16steps × 9-bit) ch.0 to ch.3: No FIFO Base Timer (PWC/Reload timer/PWM/PPG) 8 ch. (Max) Dual Timer 1 unit HDMI-CEC/ Remote Control Receiver 2 ch. (Max) Real-Time Clock 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog timer 1ch. (SW) + 1ch. (HW) External Interrupts 8 pins (Max) + NMI × 1 11 pins (Max) + NMI × 1 16 pins (Max) + NMI × 1 I/O ports 51 pins (Max) 66 pins (Max) 83 pins (Max) 12-bit A/D converter 12 ch. (2 units) 17 ch. (2 units) 24 ch. (2 units) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2 ch. High-speed Built-in CR Low-speed 4 MHz 100 kHz Debug Function SWJ-DP SWJ-DP/ETM Unique ID Yes Note: - All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See Electrical Characteristics 12.4 AC Characteristics (12.4.3)Built-in CR Oscillation Characteristics for accuracy of built-in CR. Document Number: 002-05635 Rev. *C Page 7 of 126 CY9A340NB Series 2. Packages Package Product name LQFP: LQD064 (0.5 mm pitch) LQFP: LQG064 (0.65 mm pitch) QFN: VNC064 (0.5 mm pitch) LQFP: LQH080 (0.5 mm pitch) LQFP: LQJ080 (0.65 mm pitch) BGA: FDG096 (0.5 mm pitch) LQFP: LQI100 (0.5 mm pitch) QFP: PQH100 (0.65 mm pitch) BGA: LBC112 (0.8 mm pitch) : Supported CY9AF341LB CY9AF342LB CY9AF344LB - - - - - CY9AF341MB CY9AF342MB CY9AF344MB - - - Note: - See Package Dimensions for detailed information on each package. CY9AF341NB CY9AF342NB CY9AF344NB - - - - Document Number: 002-05635 Rev. *C Page 8 of 126 3. Pin Assignment LQI100 (TOP VIEW) CY9A340NB Series 100 VSS 99 P81/UDP0 98 P80/UDM0 97 VCC 96 P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1/MRDY_1 95 P61/SOT5_0/TIOB2_2/UHCONX 94 P62/SCK5_0/ADTG_3/MOEX_1 93 P63/INT03_0/MWEX_1 92 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 91 P0E/CTS4_0/TIOB3_2/MDQM1_1 90 P0D/RTS4_0/TIOA3_2/MDQM0_1 89 P0C/SCK4_0/TIOA6_1/MALE_1 88 P0B/SOT4_0/TIOB6_1/MCSX0_1 87 P0A/SIN4_0/INT00_2/MCSX1_1 86 P09/TRACECLK/TIOB0_2/RTS4_2/MCSX2_1 85 P08/AN23/TRACED3/TIOA0_2/CTS4_2/MCSX3_1 84 P07/AN22/TRACED2/ADTG_0/SCK4_2/MCLKOUT_1 83 P06/AN21/TRACED1/TIOB5_2/SOT4_2/INT01_1/MCSX4_1 82 P05/AN20/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_1 81 P04/TDO/SWO 80 P03/TMS/SWDIO 79 P02/TDI/MCSX6_1 78 P01/TCK/SWCLK 77 P00/TRSTX/MCSX7_1 76 VCC VCC 1 P50/INT00_0/SIN3_1/MADATA00_1 2 P51/INT01_0/SOT3_1/MADATA01_1 3 P52/INT02_0/SCK3_1/MADATA02_1 4 P53/SIN6_0/TIOA1_2/INT07_2/MADATA03_1 5 P54/SOT6_0/TIOB1_2/MADATA04_1 6 P55/SCK6_0/ADTG_1/MADATA05_1 7 P56/INT08_2/MADATA06_1 8 P30/TIOB0_1/INT03_2/MADATA07_1 9 P31/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 10 P32/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 11 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 12 P34/TIOB4_1/MADATA11_1 13 P35/TIOB5_1/INT08_1/MADATA12_1 14 P36/SIN5_2/INT09_1/MADATA13_1 15 P37/SOT5_2/INT10_1/MADATA14_1 16 P38/SCK5_2/INT11_1/MADATA15_1 17 P39/ADTG_2 18 P3A/TIOA0_1/RTCCO_2/SUBOUT_2 19 P3B/TIOA1_1 20 P3C/TIOA2_1 21 P3D/TIOA3_1 22 P3E/TIOA4_1 23 P3F/TIOA5_1 24 VSS 25 LQFP - 100 75 VSS 74 P20/AN19/INT05_0/CROUT_0/MAD24_1 73 P21/AN18/SIN0_0/INT06_1/WKUP2 72 P22/AN17/SOT0_0/TIOB7_1 71 P23/AN16/SCK0_0/TIOA7_1 70 P1F/AN15/ADTG_5/MAD23_1 69 P1E/AN14/RTS4_1/MAD22_1 68 P1D/AN13/CTS4_1/MAD21_1 67 P1C/AN12/SCK4_1/MAD20_1 66 P1B/AN11/SOT4_1/MAD19_1 65 P1A/AN10/SIN4_1/INT05_1/MAD18_1 64 P19/AN09/SCK2_2/MAD17_1 63 P18/AN08/SOT2_2/MAD16_1 62 AVSS 61 AVRH 60 AVCC 59 P17/AN07/SIN2_2/INT04_1/MAD15_1 58 P16/AN06/SCK0_1/MAD14_1 57 P15/AN05/SOT0_1/MAD13_1 56 P14/AN04/SIN0_1/INT03_1/MAD12_1 55 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/MAD11_1 54 P12/AN02/SOT1_1/MAD10_1 53 P11/AN01/SIN1_1/INT02_1/WKUP1/MAD09_1 52 P10/AN00 51 VCC VCC 26 P40/TIOA0_0/INT12_1 27 P41/TIOA1_0/INT13_1 28 P42/TIOA2_0 29 P43/TIOA3_0/ADTG_7 30 P44/TIOA4_0/MAD00_1 31 P45/TIOA5_0/MAD01_1 32 C 33 VSS 34 VCC 35 P46/X0A 36 P47/X1A 37 INITX 38 P48/INT14_1/SIN3_2/MAD02_1 39 P49/TIOB0_0/SOT3_2/MAD03_1 40 P4A/TIOB1_0/SCK3_2/MAD04_1 41 P4B/TIOB2_0/MAD05_1 42 P4C/TIOB3_0/SCK7_1/CEC0/MAD06_1 43 P4D/TIOB4_0/SOT7_1/MAD07_1 44 P4E/TIOB5_0/INT06_2/SIN7_1/MAD08_1 45 PE0/MD1 46 MD0 47 PE2/X0 48 PE3/X1 49 VSS 50 Note: - The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05635 Rev. *C Page 9 of 126 PQH100 (TOP VIEW) CY9A340NB Series 80 P50/INT00_0/SIN3_1/MADATA00_1 79 VCC 78 VSS 77 P81/UDP0 76 P80/UDM0 75 VCC 74 P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1/MRDY_1 73 P61/SOT5_0/TIOB2_2/UHCONX 72 P62/SCK5_0/ADTG_3/MOEX_1 71 P63/INT03_0/MWEX_1 70 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 69 P0E/CTS4_0/TIOB3_2/MDQM1_1 68 P0D/RTS4_0/TIOA3_2/MDQM0_1 67 P0C/SCK4_0/TIOA6_1/MALE_1 66 P0B/SOT4_0/TIOB6_1/MCSX0_1 65 P0A/SIN4_0/INT00_2/MCSX1_1 64 P09/TRACECLK/TIOB0_2/RTS4_2/MCSX2_1 63 P08/AN23/TRACED3/TIOA0_2/CTS4_2/MCSX3_1 62 P07/AN22/TRACED2/ADTG_0/SCK4_2/MCLKOUT_1 61 P06/AN21/TRACED1/TIOB5_2/SOT4_2/INT01_1/MCSX4_1 60 P05/AN20/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_1 59 P04/TDO/SWO 58 P03/TMS/SWDIO 57 P02/TDI/MCSX6_1 56 P01/TCK/SWCLK 55 P00/TRSTX/MCSX7_1 54 VCC 53 VSS 52 P20/AN19/INT05_0/CROUT_0/MAD24_1 51 P21/AN18/SIN0_0/INT06_1/WKUP2 P51/INT01_0/SOT3_1/MADATA01_1 81 P52/INT02_0/SCK3_1/MADATA02_1 82 P53/SIN6_0/TIOA1_2/INT07_2/MADATA03_1 83 P54/SOT6_0/TIOB1_2/MADATA04_1 84 P55/SCK6_0/ADTG_1/MADATA05_1 85 P56/INT08_2/MADATA06_1 86 P30/TIOB0_1/INT03_2/MADATA07_1 87 P31/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 88 P32/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 89 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 90 P34/TIOB4_1/MADATA11_1 91 P35/TIOB5_1/INT08_1/MADATA12_1 92 P36/SIN5_2/INT09_1/MADATA13_1 93 P37/SOT5_2/INT10_1/MADATA14_1 94 P38/SCK5_2/INT11_1/MADATA15_1 95 P39/ADTG_2 96 P3A/TIOA0_1/RTCCO_2/SUBOUT_2 97 P3B/TIOA1_1 98 P3C/TIOA2_1 99 P3D/TIOA3_1 100 QFP - 100 50 P22/AN17/SOT0_0/TIOB7_1 49 P23/AN16/SCK0_0/TIOA7_1 48 P1F/AN15/ADTG_5/MAD23_1 47 P1E/AN14/RTS4_1/MAD22_1 46 P1D/AN13/CTS4_1/MAD21_1 45 P1C/AN12/SCK4_1/MAD20_1 44 P1B/AN11/SOT4_1/MAD19_1 43 P1A/AN10/SIN4_1/INT05_1/MAD18_1 42 P19/AN09/SCK2_2/MAD17_1 41 P18/AN08/SOT2_2/MAD16_1 40 AVSS 39 AVRH 38 AVCC 37 P17/AN07/SIN2_2/INT04_1/MAD15_1 36 P16/AN06/SCK0_1/MAD14_1 35 P15/AN05/SOT0_1/MAD13_1 34 P14/AN04/SIN0_1/INT03_1/MAD12_1 33 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/MAD11_1 32 P12/AN02/SOT1_1/MAD10_1 31 P11/AN01/SIN1_1/INT02_1/WKUP1/MAD09_1 P3E/TIOA4_1 1 P3F/TIOA5_1 2 VSS 3 VCC 4 P40/TIOA0_0/INT12_1 5 P41/TIOA1_0/INT13_1 6 P42/TIOA2_0 7 P43/TIOA3_0/ADTG_7 8 P44/TIOA4_0/MAD00_1 9 P45/TIOA5_0/MAD01_1 10 C 11 VSS 12 VCC 13 P46/X0A 14 P47/X1A 15 INITX 16 P48/INT14_1/SIN3_2/MAD02_1 17 P49/TIOB0_0/SOT3_2/MAD03_1 18 P4A/TIOB1_0/SCK3_2/MAD04_1 19 P4B/TIOB2_0/MAD05_1 20 P4C/TIOB3_0/SCK7_1/CEC0/MAD06_1 21 P4D/TIOB4_0/SOT7_1/MAD07_1 22 P4E/TIOB5_0/INT06_2/SIN7_1/MAD08_1 23 PE0/MD1 24 MD0 25 PE2/X0 26 PE3/X1 27 VSS 28 VCC 29 P10/AN00 30 Note: - The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05635 Rev. *C Page 10 of 126 LQH080/ LQJ080 (TOP VIEW) CY9A340NB Series 80 VSS 79 P81/UDP0 78 P80/UDM0 77 VCC 76 P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1/MRDY_1 75 P61/SOT5_0/TIOB2_2/UHCONX 74 P62/SCK5_0/ADTG_3/MOEX_1 73 P63/INT03_0/MWEX_1 72 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 71 P0E/CTS4_0/TIOB3_2/MDQM1_1 70 P0D/RTS4_0/TIOA3_2/MDQM0_1 69 P0C/SCK4_0/TIOA6_1/MALE_1 68 P0B/SOT4_0/TIOB6_1/MCSX0_1 67 P0A/SIN4_0/INT00_2/MCSX1_1 66 P07/AN22/ADTG_0/MCLKOUT_1 65 P04/TDO/SWO 64 P03/TMS/SWDIO 63 P02/TDI/MCSX6_1 62 P01/TCK/SWCLK 61 P00/TRSTX/MCSX7_1 VCC 1 P50/INT00_0/SIN3_1/MADATA00_1 2 P51/INT01_0/SOT3_1/MADATA01_1 3 P52/INT02_0/SCK3_1/MADATA02_1 4 P53/SIN6_0/TIOA1_2/INT07_2/MADATA03_1 5 P54/SOT6_0/TIOB1_2/MADATA04_1 6 P55/SCK6_0/ADTG_1/MADATA05_1 7 P56/INT08_2/MADATA06_1 8 P30/TIOB0_1/INT03_2/MADATA07_1 9 P31/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 10 P32/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 11 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 12 P39/ADTG_2 13 P3A/TIOA0_1/RTCCO_2/SUBOUT_2 14 P3B/TIOA1_1 15 P3C/TIOA2_1 16 P3D/TIOA3_1 17 P3E/TIOA4_1 18 P3F/TIOA5_1 19 VSS 20 LQFP - 80 60 P20/AN19/INT05_0/CROUT_0/MAD24_1 59 P21/AN18/SIN0_0/INT06_1/WKUP2 58 P22/AN17/SOT0_0/TIOB7_1 57 P23/AN16/SCK0_0/TIOA7_1 56 P1B/AN11/SOT4_1/MAD19_1 55 P1A/AN10/SIN4_1/INT05_1/MAD18_1 54 P19/AN09/SCK2_2/MAD17_1 53 P18/AN08/SOT2_2/MAD16_1 52 AVSS 51 AVRH 50 AVCC 49 P17/AN07/SIN2_2/INT04_1/MAD15_1 48 P16/AN06/SCK0_1/MAD14_1 47 P15/AN05/SOT0_1/MAD13_1 46 P14/AN04/SIN0_1/INT03_1/MAD12_1 45 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/MAD11_1 44 P12/AN02/SOT1_1/MAD10_1 43 P11/AN01/SIN1_1/INT02_1/WKUP1/MAD09_1 42 P10/AN00 41 VCC P44/TIOA4_0/MAD00_1 21 P45/TIOA5_0/MAD01_1 22 C 23 VSS 24 VCC 25 P46/X0A 26 P47/X1A 27 INITX 28 P48/INT14_1/SIN3_2/MAD02_1 29 P49/TIOB0_0/SOT3_2/MAD03_1 30 P4A/TIOB1_0/SCK3_2/MAD04_1 31 P4B/TIOB2_0/MAD05_1 32 P4C/TIOB3_0/SCK7_1/CEC0/MAD06_1 33 P4D/TIOB4_0/SOT7_1/MAD07_1 34 P4E/TIOB5_0/INT06_2/SIN7_1/MAD08_1 35 PE0/MD1 36 MD0 37 PE2/X0 38 PE3/X1 39 VSS 40 Note: - The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05635 Rev. *C Page 11 of 126 LQD064/ LQG064 (TOP VIEW) CY9A340NB Series 64 VSS 63 P81/UDP0 62 P80/UDM0 61 VCC 60 P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1 59 P61/SOT5_0/TIOB2_2/UHCONX 58 P62/SCK5_0/ADTG_3 57 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 56 P0C/SCK4_0/TIOA6_1 55 P0B/SOT4_0/TIOB6_1 54 P0A/SIN4_0/INT00_2 53 P04/TDO/SWO 52 P03/TMS/SWDIO 51 P02/TDI 50 P01/TCK/SWCLK 49 P00/TRSTX VCC 1 P50/INT00_0/SIN3_1 2 P51/INT01_0/SOT3_1 3 P52/INT02_0/SCK3_1 4 P30/TIOB0_1/INT03_2 5 P31/TIOB1_1/SCK6_1/INT04_2 6 P32/TIOB2_1/SOT6_1/INT05_2 7 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6 8 P39/ADTG_2 9 P3A/TIOA0_1/RTCCO_2/SUBOUT_2 10 P3B/TIOA1_1 11 P3C/TIOA2_1 12 P3D/TIOA3_1 13 P3E/TIOA4_1 14 P3F/TIOA5_1 15 VSS 16 LQFP - 64 48 P21/AN18/SIN0_0/INT06_1/WKUP2 47 P22/AN17/SOT0_0/TIOB7_1 46 P23/AN16/SCK0_0/TIOA7_1 45 P19/AN09/SCK2_2 44 P18/AN08/SOT2_2 43 AVSS 42 AVRH 41 AVCC 40 P17/AN07/SIN2_2/INT04_1 39 P15/AN05 38 P14/AN04/INT03_1 37 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1 36 P12/AN02/SOT1_1 35 P11/AN01/SIN1_1/INT02_1/WKUP1 34 P10/AN00 33 VCC C 17 VCC 18 P46/X0A 19 P47/X1A 20 INITX 21 P49/TIOB0_0 22 P4A/TIOB1_0 23 P4B/TIOB2_0 24 P4C/TIOB3_0/SCK7_1/CEC0 25 P4D/TIOB4_0/SOT7_1 26 P4E/TIOB5_0/INT06_2/SIN7_1 27 PE0/MD1 28 MD0 29 PE2/X0 30 PE3/X1 31 VSS 32 Note: - The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05635 Rev. *C Page 12 of 126 VNC064 (TOP VIEW) CY9A340NB Series 64 VSS 63 P81/UDP0 62 P80/UDM0 61 VCC 60 P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1 59 P61/SOT5_0/TIOB2_2/UHCONX 58 P62/SCK5_0/ADTG_3 57 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 56 P0C/SCK4_0/TIOA6_1 55 P0B/SOT4_0/TIOB6_1 54 P0A/SIN4_0/INT00_2 53 P04/TDO/SWO 52 P03/TMS/SWDIO 51 P02/TDI 50 P01/TCK/SWCLK 49 P00/TRSTX VCC 1 P50/INT00_0/SIN3_1 2 P51/INT01_0/SOT3_1 3 P52/INT02_0/SCK3_1 4 P30/TIOB0_1/INT03_2 5 P31/TIOB1_1/SCK6_1/INT04_2 6 P32/TIOB2_1/SOT6_1/INT05_2 7 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6 8 P39/ADTG_2 9 P3A/TIOA0_1/RTCCO_2/SUBOUT_2 10 P3B/TIOA1_1 11 P3C/TIOA2_1 12 P3D/TIOA3_1 13 P3E/TIOA4_1 14 P3F/TIOA5_1 15 VSS 16 QFN - 64 48 P21/AN18/SIN0_0/INT06_1/WKUP2 47 P22/AN17/SOT0_0/TIOB7_1 46 P23/AN16/SCK0_0/TIOA7_1 45 P19/AN09/SCK2_2 44 P18/AN08/SOT2_2 43 AVSS 42 AVRH 41 AVCC 40 P17/AN07/SIN2_2/INT04_1 39 P15/AN05 38 P14/AN04/INT03_1 37 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1 36 P12/AN02/SOT1_1 35 P11/AN01/SIN1_1/INT02_1/WKUP1 34 P10/AN00 33 VCC C 17 VCC 18 P46/X0A 19 P47/X1A 20 INITX 21 P49/TIOB0_0 22 P4A/TIOB1_0 23 P4B/TIOB2_0 24 P4C/TIOB3_0/SCK7_1/CEC0 25 P4D/TIOB4_0/SOT7_1 26 P4E/TIOB5_0/INT06_2/SIN7_1 27 PE0/MD1 28 MD0 29 PE2/X0 30 PE3/X1 31 VSS 32 Note: - The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05635 Rev. *C Page 13 of 126 CY9A340NB Series LBC112 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A VSS UDP0 UDM0 VCC P0E P0B TMS/ AN22 SWDIO TRSTX VCC VSS B VCC VSS P52 P61 P0F P0C AN23 TDO/ SWO TCK/ SWCLK VSS TDI C P50 P51 VSS P60 P62 P0D P09 AN20 VSS AN19 AN18 D P53 P54 P55 VSS P56 P63 P0A VSS AN21 AN16 AN15 E P30 P31 P32 P33 Index AN17 AN14 AN12 AN11 F P34 P35 P36 P39 AN13 AN10 AN09 AVRH G P37 P38 P3A P3D AN08 AN07 AN06 AVSS H P3B P3C P3E VSS P44 P4C AN05 VSS AN04 AN03 AVCC J VCC P3F VSS P40 P43 P49 P4D AN02 VSS AN01 AN00 K VCC VSS X1A INITX P42 P48 P4B P4E MD1 VSS VCC L VSS C X0A VSS P41 P45 P4A MD0 X0 X1 VSS PFBGA - 112 Note: - The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05635 Rev. *C Page 14 of 126 CY9A340NB Series FDG096 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A TMS/ VSS UDP0 UDM0 VCC VSS P0F VSS AN22 SWDIO TRSTX VSS B VCC VSS P52 P61 P63 P0D P0C TDO/ SWO TCK/ SWCLK VSS TDI C P50 P51 VSS P60 P62 P0E P0B P0A VSS AN19 AN18 D P53 P54 P55 Index AN17 AN16 VSS E P56 P30 P31 AN11 AN10 AN09 F VSS VSS VSS AN08 AN07 AVRH G P32 P33 P39 AN06 AN05 AVSS H P3A P3B P3C AN04 AN03 AVCC J P3D P3E VSS P3F P48 P4A P4D AN02 VSS AN01 AN00 K VCC VSS X1A INITX P45 P49 P4C P4E MD1 VSS VCC L VSS C X0A VSS P44 VSS P4B MD0 X0 X1 VSS Note: PFBGA - 96 - The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05635 Rev. *C Page 15 of 126 CY9A340NB Series 4. List of Pin Functions List of Pin Numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 LQFP-64 QFN-64 Pin Name I/O Circuit Type Pin State Type 1 79 B1 1 B1 1 VCC - P50 2 INT00_0 2 80 C1 2 C1 E L SIN3_1 - MADATA00_1 P51 3 INT01_0 3 81 C2 3 C2 SOT3_1 E L (SDA3_1) - MADATA01_1 P52 4 INT02_0 4 82 B3 4 B3 SCK3_1 E L (SCL3_1) - MADATA02_1 P53 SIN6_0 5 83 D1 5 D1 - TIOA1_2 E L INT07_2 MADATA03_1 P54 6 84 D2 6 D2 - SOT6_0 (SDA6_0) E K TIOB1_2 MADATA04_1 Document Number: 002-05635 Rev. *C Page 16 of 126 CY9A340NB Series Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 7 85 D3 7 D3 8 86 D5 8 E1 9 87 E1 9 E2 10 88 E2 10 E3 11 89 E3 11 G1 12 90 E4 12 G2 13 91 F1 - - 14 92 F2 - - LQFP-64 QFN-64 - 5 6 7 8 - - Pin Name P55 SCK6_0 (SCL6_0) ADTG_1 MADATA05_1 P56 INT08_2 MADATA06_1 P30 TIOB0_1 INT03_2 MADATA07_1 P31 TIOB1_1 SCK6_1 (SCL6_1) INT04_2 MADATA08_1 P32 TIOB2_1 SOT6_1 (SDA6_1) INT05_2 MADATA09_1 P33 INT04_0 TIOB3_1 SIN6_1 ADTG_6 MADATA10_1 P34 TIOB4_1 MADATA11_1 P35 TIOB5_1 INT08_1 MADATA12_1 I/O Circuit Type Pin State Type E K E L E L E L E L E L E K E L Document Number: 002-05635 Rev. *C Page 17 of 126 CY9A340NB Series LQFP-100 15 - 16 17 18 19 20 21 22 23 24 25 26 QFP-100 93 - 94 95 96 97 98 99 100 1 2 3 4 Pin No BGA-112 LQFP-80 F3 - - - - - - - G1 - G2 - F4 13 G3 14 H1 15 H2 16 G4 17 B2 - H3 18 J2 19 L1 20 J1 - BGA-96 F1 F2 F3 - - G3 H1 H2 H3 J1 B2 J2 J4 L1 - LQFP-64 QFN-64 - - - 9 10 11 12 13 14 15 16 - Pin Name P36 SIN5_2 INT09_1 MADATA13_1 VSS VSS VSS P37 SOT5_2 (SDA5_2) INT10_1 MADATA14_1 P38 SCK5_2 (SCL5_2) INT11_1 MADATA15_1 P39 ADTG_2 P3A TIOA0_1 RTCCO_2 SUBOUT_2 P3B TIOA1_1 P3C TIOA2_1 P3D TIOA3_1 VSS P3E TIOA4_1 P3F TIOA5_1 VSS VCC I/O Circuit Type E - E E E E E E E E E - Pin State Type L L L K K K K K K K Document Number: 002-05635 Rev. *C Page 18 of 126 CY9A340NB Series LQFP-100 27 28 29 30 31 32 33 34 35 36 37 38 39 40 QFP-100 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Pin No BGA-112 LQFP-80 BGA-96 J4 - - L5 - - K5 - - J5 - - H5 21 L5 L6 22 K5 K2 - K2 J3 - J3 H4 - - - - L6 L2 23 L2 L4 24 L4 K1 25 K1 L3 26 L3 K3 27 K3 K4 28 K4 K6 29 J5 J6 30 K6 LQFP-64 QFN-64 - - - - - 17 18 19 20 21 - 22 - Pin Name P40 TIOA0_0 INT12_1 P41 TIOA1_0 INT13_1 P42 TIOA2_0 P43 TIOA3_0 ADTG_7 P44 TIOA4_0 MAD00_1 P45 TIOA5_0 MAD01_1 VSS VSS VSS VSS C VSS VCC P46 X0A P47 X1A INITX P48 INT14_1 SIN3_2 MAD02_1 P49 TIOB0_0 SOT3_2 (SDA3_2) MAD03_1 I/O Circuit Type E E E E E E D D B E E Pin State Type L L K K K K F G C L K Document Number: 002-05635 Rev. *C Page 19 of 126 CY9A340NB Series Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96 41 19 L7 31 J6 42 20 K7 32 L7 43 21 H6 33 K7 44 22 J7 34 J7 45 23 K8 35 K8 46 24 K9 36 K9 47 25 L8 37 L8 48 26 L9 38 L9 49 27 L10 39 L10 50 28 L11 40 L11 51 29 K11 41 K11 52 30 J11 42 J11 53 31 J10 43 J10 LQFP-64 QFN-64 23 24 - 25 26 - 27 28 29 30 31 32 33 34 35 - Pin Name P4A TIOB1_0 SCK3_2 (SCL3_2) MAD04_1 P4B TIOB2_0 MAD05_1 P4C TIOB3_0 SCK7_1 (SCL7_1) CEC0 MAD06_1 P4D TIOB4_0 SOT7_1 (SDA7_1) MAD07_1 P4E TIOB5_0 INT06_2 SIN7_1 MAD08_1 MD1 PE0 MD0 X0 PE2 X1 PE3 VSS VCC P10 AN00 P11 AN01 SIN1_1 INT02_1 WKUP1 MAD09_1 I/O Circuit Type E E I I I C G A A F F Pin State Type K K S K L E D A B M R Document Number: 002-05635 Rev. *C Page 20 of 126 CY9A340NB Series LQFP-100 54 55 56 57 58 59 60 61 62 QFP-100 32 33 34 35 36 37 38 39 40 Pin No BGA-112 LQFP-80 BGA-96 J8 44 J8 K10 - K10 J9 - J9 H10 45 H10 H9 46 H9 H7 47 G10 G10 48 G9 G9 49 F10 H11 50 H11 F11 51 F11 G11 52 G11 LQFP-64 QFN-64 36 - 37 38 39 - - 40 41 42 43 Pin Name P12 AN02 SOT1_1 (SDA1_1) MAD10_1 VSS VSS P13 AN03 SCK1_1 (SCL1_1) RTCCO_1 SUBOUT_1 MAD11_1 P14 AN04 INT03_1 SIN0_1 MAD12_1 P15 AN05 SOT0_1 (SDA0_1) MAD13_1 P16 AN06 SCK0_1 (SCL0_1) MAD14_1 P17 AN07 SIN2_2 INT04_1 MAD15_1 AVCC AVRH AVSS I/O Circuit Type F - F F F F F - Pin State Type M M N M M N Document Number: 002-05635 Rev. *C Page 21 of 126 CY9A340NB Series LQFP-100 63 64 65 66 67 68 69 70 Pin No QFP-100 BGA-112 LQFP-80 BGA-96 41 G8 53 F9 42 F10 54 E11 - H8 - - 43 F9 55 E10 44 E11 56 E9 45 E10 - - 46 F8 - - 47 E9 - - 48 D11 - - LQFP-64 QFN-64 44 45 - - - - - - Pin Name P18 AN08 SOT2_2 (SDA2_2) MAD16_1 P19 AN09 SCK2_2 (SCL2_2) MAD17_1 VSS P1A AN10 SIN4_1 INT05_1 MAD18_1 P1B AN11 SOT4_1 (SDA4_1) MAD19_1 P1C AN12 SCK4_1 (SCL4_1) MAD20_1 P1D AN13 CTS4_1 MAD21_1 P1E AN14 RTS4_1 MAD22_1 P1F AN15 ADTG_5 MAD23_1 I/O Circuit Type F F F F F F F F Pin State Type M M N M M M M M Document Number: 002-05635 Rev. *C Page 22 of 126 CY9A340NB Series LQFP-100 71 72 73 74 75 76 77 78 79 80 81 Pin No QFP-100 BGA-112 LQFP-80 BGA-96 - B10 - B10 - C9 - C9 - - - D11 49 D10 57 D10 50 E8 58 D9 51 C11 59 C11 52 C10 60 C10 53 A11 - A11 54 A10 - - 55 A9 61 A10 56 B9 62 B9 57 B11 63 B11 58 A8 64 A9 59 B8 65 B8 LQFP-64 QFN-64 - 46 47 48 - 49 50 51 52 53 Pin Name VSS VSS VSS P23 AN16 SCK0_0 (SCL0_0) TIOA7_1 P22 AN17 SOT0_0 (SDA0_0) TIOB7_1 P21 AN18 SIN0_0 INT06_1 WKUP2 P20 AN19 INT05_0 CROUT_0 MAD24_1 VSS VCC P00 TRSTX MCSX7_1 P01 TCK SWCLK P02 TDI MCSX6_1 P03 TMS SWDIO P04 TDO SWO I/O Circuit Type F F F F E E E E E Pin State Type M M R N J J J J J Document Number: 002-05635 Rev. *C Page 23 of 126 CY9A340NB Series LQFP-100 82 83 84 85 86 87 QFP-100 60 61 62 63 64 65 Pin No BGA-112 LQFP-80 C8 - D8 - D9 - 66 A7 - - - B7 - C7 - D7 67 BGA-96 - A8 A7 - C8 LQFP-64 QFN-64 - - 54 - Pin Name P05 AN20 TRACED0 TIOA5_2 SIN4_2 INT00_1 MCSX5_1 VSS P06 AN21 TRACED1 TIOB5_2 SOT4_2 (SDA4_2) INT01_1 MCSX4_1 P07 AN22 ADTG_0 MCLKOUT_ 1 TRACED2 SCK4_2 (SCL4_2) VSS P08 AN23 TRACED3 TIOA0_2 CTS4_2 MCSX3_1 P09 TRACECLK TIOB0_2 RTS4_2 MCSX2_1 P0A SIN4_0 INT00_2 MCSX1_1 I/O Circuit Type F F F F E I Pin State Type Q Q P P O L Document Number: 002-05635 Rev. *C Page 24 of 126 CY9A340NB Series Pin No LQFP-100 QFP-100 BGA-112 LQFP-80 88 66 A6 68 89 67 B6 69 - - D4 - - - C3 - 90 68 C6 70 91 69 A5 71 - - - - 92 70 B5 72 93 71 D6 73 94 72 C5 74 95 73 B4 75 BGA-96 LQFP-64 QFN-64 55 C7 - 56 B7 - - - C3 - B6 - C6 - A5 - A6 57 B5 - 58 C5 - B4 59 Pin Name P0B SOT4_0 (SDA4_0) TIOB6_1 MCSX0_1 P0C SCK4_0 (SCL4_0) TIOA6_1 MALE_1 VSS VSS P0D RTS4_0 TIOA3_2 MDQM0_1 P0E CTS4_0 TIOB3_2 MDQM1_1 VSS P0F NMIX CROUT_1 RTCCO_0 SUBOUT_0 WKUP0 P63 INT03_0 MWEX_1 P62 SCK5_0 (SCL5_0) ADTG_3 MOEX_1 P61 SOT5_0 (SDA5_0) TIOB2_2 UHCONX I/O Circuit Type Pin State Type I K I K - E K E K - E I E L E K E K Document Number: 002-05635 Rev. *C Page 25 of 126 CY9A340NB Series LQFP-100 96 97 98 99 100 Pin No QFP-100 BGA-112 LQFP-80 BGA-96 74 C4 76 C4 75 A4 77 A4 76 A3 78 A3 77 A2 79 A2 78 A1 80 A1 LQFP-64 QFN-64 60 61 62 63 64 Pin Name P60 SIN5_0 TIOA2_2 INT15_1 WKUP3 CEC1 MRDY_1 VCC P80 UDM0 P81 UDP0 VSS I/O Circuit Type Pin State Type I T - H H H H - Document Number: 002-05635 Rev. *C Page 26 of 126 CY9A340NB Series List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin Function Pin Name ADC ADTG_0 ADTG_1 Function Description LQFP100 84 7 QFP100 62 85 Pin No BGA- LQFP- BGA- 112 80 96 A7 66 A8 D3 7 D3 LQFP/ QFN- 64 - - ADTG_2 18 96 F4 13 G3 9 ADTG_3 94 72 C5 74 C5 58 ADTG_4 A/D converter external trigger input pin - - - - - - ADTG_5 70 48 D11 - - - ADTG_6 ADTG_7 ADTG_8 AN00 AN01 12 90 E4 12 G2 8 30 8 J5 - - - - - - - - - 52 30 J11 42 J11 34 53 31 J10 43 J10 35 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 54 32 J8 44 J8 36 55 33 H10 45 H10 37 56 34 H9 46 H9 38 57 35 H7 47 G10 39 58 36 G10 48 G9 - 59 37 G9 49 F10 40 63 41 G8 53 F9 44 64 42 F10 54 E11 45 65 43 F9 55 E10 - AN11 AN12 AN13 AN14 AN15 A/D converter analog input pin. 66 44 E11 56 E9 - ANxx describes ADC ch.xx. 67 45 E10 - - - 68 46 F8 - - - 69 47 E9 - - - 70 48 D11 - - - AN16 AN17 AN18 AN19 71 49 D10 57 D10 46 72 50 E8 58 D9 47 73 51 C11 59 C11 48 74 52 C10 60 C10 - AN20 AN21 AN22 AN23 82 60 C8 - - - 83 61 D9 - - - 84 62 A7 66 A8 - 85 63 B7 - - - Document Number: 002-05635 Rev. *C Page 27 of 126 CY9A340NB Series Pin Function Pin Name Function Description Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 TIOA0_0 TIOA0_1 TIOA0_2 TIOB0_0 TIOB0_1 TIOB0_2 TIOA1_0 TIOA1_1 TIOA1_2 TIOB1_0 TIOB1_1 TIOB1_2 TIOA2_0 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 TIOA3_0 TIOA3_1 TIOA3_2 TIOB3_0 TIOB3_1 TIOB3_2 TIOA4_0 TIOA4_1 TIOA4_2 TIOB4_0 TIOB4_1 TIOB4_2 TIOA5_0 TIOA5_1 TIOA5_2 TIOB5_0 TIOB5_1 TIOB5_2 TIOA6_1 TIOB6_1 TIOA7_0 TIOA7_1 TIOA7_2 TIOB7_0 TIOB7_1 TIOB7_2 Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin Base timer ch.6 TIOA pin Base timer ch.6 TIOB pin Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin Document Number: 002-05635 Rev. *C LQFP100 27 19 85 40 9 86 28 20 5 41 10 6 29 21 96 42 11 95 30 22 90 43 12 91 31 23 44 13 32 24 82 45 14 83 89 88 71 72 - QFP100 5 97 63 18 87 64 6 98 83 19 88 84 7 99 74 20 89 73 8 100 68 21 90 69 9 1 22 91 10 2 60 23 92 61 67 66 49 50 - Pin No BGA- LQFP- 112 80 J4 - G3 14 B7 - J6 30 E1 9 C7 - L5 - H1 15 D1 5 L7 31 E2 10 D2 6 K5 - H2 16 C4 76 K7 32 E3 11 B4 75 J5 - G4 17 C6 70 H6 33 E4 12 A5 71 H5 21 H3 18 - - J7 34 F1 - - - L6 22 J2 19 C8 - K8 35 F2 - D9 - B6 69 A6 68 - - D10 57 - - - - E8 58 - - BGA96 H1 K6 E2 H2 D1 J6 E3 D2 H3 C4 L7 G1 B4 J1 B6 K7 G2 C6 L5 J2 J7 K5 J4 K8 B7 C7 D10 D9 - LQFP/ QFN- 64 10 22 5 11 23 6 12 60 24 7 59 13 25 8 14 26 15 27 56 55 46 47 - Page 28 of 126 CY9A340NB Series Pin Function Debugger External Bus Pin Name SWCLK SWDIO SWO TCK TDI TDO TMS TRACECLK TRACED0 TRACED1 TRACED2 TRACED3 TRSTX MAD00_1 MAD01_1 MAD02_1 MAD03_1 MAD04_1 MAD05_1 MAD06_1 MAD07_1 MAD08_1 MAD09_1 MAD10_1 MAD11_1 MAD12_1 MAD13_1 MAD14_1 MAD15_1 MAD16_1 MAD17_1 MAD18_1 MAD19_1 MAD20_1 MAD21_1 MAD22_1 MAD23_1 MAD24_1 Function Description Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin JTAG test clock input pin JTAG test data input pin JTAG debug data output pin JTAG test mode state input/output pin Trace CLK output pin of ETM Trace data output pins of ETM JTAG test reset input pin External bus interface address bus LQFP100 78 80 81 78 79 81 80 86 82 83 84 85 77 31 32 39 40 41 42 43 44 45 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 74 QFP100 56 58 59 56 57 59 58 64 60 61 62 63 55 9 10 17 18 19 20 21 22 23 31 32 33 34 35 36 37 41 42 43 44 45 46 47 48 52 Pin No BGA- LQFP- 112 80 BGA96 B9 62 B9 A8 64 A9 B8 65 B8 B9 62 B9 B11 63 B11 B8 65 B8 A8 64 A9 C7 - - C8 - - D9 - - A7 - - B7 - - A9 61 A10 H5 21 L5 L6 22 K5 K6 29 J5 J6 30 K6 L7 31 J6 K7 32 L7 H6 33 K7 J7 34 J7 K8 35 K8 J10 43 J10 J8 44 J8 H10 45 H10 H9 46 H9 H7 47 G10 G10 48 G9 G9 49 F10 G8 53 F9 F10 54 E11 F9 55 E10 E11 56 E9 E10 - - F8 - - E9 - - D11 - - C10 60 C10 LQFP/ QFN- 64 50 52 53 50 51 53 52 49 - Document Number: 002-05635 Rev. *C Page 29 of 126 CY9A340NB Series Pin Function Pin Name External Bus MCSX0_1 MCSX1_1 MCSX2_1 MCSX3_1 MCSX4_1 MCSX5_1 MCSX6_1 MCSX7_1 MDQM0_1 MDQM1_1 MOEX_1 MWEX_1 MADATA00_1 MADATA01_1 MADATA02_1 MADATA03_1 MADATA04_1 MADATA05_1 MADATA06_1 MADATA07_1 MADATA08_1 MADATA09_1 MADATA10_1 MADATA11_1 MADATA12_1 MADATA13_1 MADATA14_1 MADATA15_1 MALE_1 MRDY_1 MCLKOUT_1 Function Description External bus interface chip select output pin External bus interface byte mask signal output pin External bus interface read enable signal for SRAM External bus interface write enable signal for SRAM External bus interface data bus Address Latch enable signal for multiplex External RDY input signal External bus clock output pin LQFP100 88 87 86 85 83 82 79 77 90 91 94 93 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 89 96 84 QFP100 66 65 64 63 61 60 57 55 68 69 72 71 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 67 74 62 Pin No BGA- LQFP- 112 80 BGA96 A6 68 C7 D7 67 C8 C7 - - B7 - - D9 - - C8 - - B11 63 B11 A9 61 A10 C6 70 B6 A5 71 C6 C5 74 C5 D6 73 B5 C1 2 C1 C2 3 C2 B3 4 B3 D1 5 D1 D2 6 D2 D3 7 D3 D5 8 E1 E1 9 E2 E2 10 E3 E3 11 G1 E4 12 G2 F1 - - F2 - - F3 - - G1 - - G2 - - B6 69 B7 C4 76 C4 A7 66 A8 LQFP/ QFN- 64 - - - - - - - Document Number: 002-05635 Rev. *C Page 30 of 126 CY9A340NB Series Pin Function Pin Name Function Description External Interrupt INT00_0 INT00_1 INT00_2 INT01_0 INT01_1 INT02_0 INT02_1 INT03_0 INT03_1 INT03_2 INT04_0 INT04_1 INT04_2 INT05_0 INT05_1 INT05_2 INT06_1 INT06_2 INT07_2 INT08_1 INT08_2 INT09_1 INT10_1 INT11_1 INT12_1 INT13_1 INT14_1 INT15_1 NMIX External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin External interrupt request 06 input pin External interrupt request 07 input pin External interrupt request 08 input pin External interrupt request 09 input pin External interrupt request 10 input pin External interrupt request 11 input pin External interrupt request 12 input pin External interrupt request 13 input pin External interrupt request 14 input pin External interrupt request 15 input pin Non-Maskable Interrupt input pin LQFP100 2 82 87 3 83 4 53 93 56 9 12 59 10 74 65 11 73 45 QFP100 80 60 65 81 61 82 31 71 34 87 90 37 88 52 43 89 51 23 5 83 14 92 8 86 15 93 Pin No BGA- LQFP- 112 80 C1 2 C8 - D7 67 C2 3 D9 - B3 4 J10 43 D6 73 H9 46 E1 9 E4 12 G9 49 E2 10 C10 60 F9 55 E3 11 C11 59 K8 35 BGA96 C1 C8 C2 B3 J10 B5 H9 E2 G2 F10 E3 C10 E10 G1 C11 K8 D1 5 D1 F2 - - D5 8 E1 F3 - - LQFP/ QFN- 64 2 54 3 4 35 38 5 8 40 6 7 48 27 - - - 16 94 G1 - - - 17 95 G2 - - - 27 5 J4 - - - 28 6 L5 - - - 39 17 K6 29 J5 - 96 74 C4 76 C4 60 92 70 B5 72 A6 57 Document Number: 002-05635 Rev. *C Page 31 of 126 CY9A340NB Series Pin Function Pin Name Function Description GPIO P00 P01 P02 P03 P04 P05 P06 P07 P08 P09 P0A P0B P0C P0D P0E P0F P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P1A P1B P1C P1D P1E P1F P20 P21 P22 P23 General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 LQFP100 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 52 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 74 73 72 71 QFP100 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 30 31 32 33 34 35 36 37 41 42 43 44 45 46 47 48 52 51 50 49 Pin No BGA- LQFP- 112 80 A9 61 B9 62 B11 63 A8 64 B8 65 C8 - D9 - A7 66 B7 - C7 - D7 67 A6 68 B6 69 C6 70 A5 71 B5 72 J11 42 J10 43 J8 44 H10 45 H9 46 H7 47 G10 48 G9 49 G8 53 F10 54 F9 55 E11 56 E10 - F8 - E9 - D11 - C10 60 C11 59 E8 58 D10 57 BGA96 A10 B9 B11 A9 B8 A8 C8 C7 B7 B6 C6 A6 J11 J10 J8 H10 H9 G10 G9 F10 F9 E11 E10 E9 C10 C11 D9 D10 LQFP/ QFN- 64 49 50 51 52 53 54 55 56 57 34 35 36 37 38 39 40 44 45 48 47 46 Document Number: 002-05635 Rev. *C Page 32 of 126 CY9A340NB Series Pin Function Pin Name Function Description GPIO P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P3A P3B P3C P3D P3E P3F P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P4A P4B P4C P4D P4E P50 P51 P52 P53 P54 P55 P56 P60 P61 P62 P63 P80 P81 PE0 PE2 PE3 General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 General-purpose I/O port 8 General-purpose I/O port E LQFP100 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 29 30 31 32 36 37 39 40 41 42 43 44 45 2 3 4 5 6 7 8 96 95 94 93 98 99 46 48 49 QFP100 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 5 6 7 8 9 10 14 15 17 18 19 20 21 22 23 80 81 82 83 84 85 86 74 73 72 71 76 77 24 26 27 Pin No BGA- LQFP- 112 80 E1 9 E2 10 E3 11 E4 12 F1 - F2 - F3 - G1 - G2 - F4 13 G3 14 H1 15 H2 16 G4 17 H3 18 J2 19 J4 - L5 - K5 - J5 - H5 21 L6 22 L3 26 K3 27 K6 29 J6 30 L7 31 K7 32 H6 33 J7 34 K8 35 C1 2 C2 3 B3 4 D1 5 D2 6 D3 7 D5 8 C4 76 B4 75 C5 74 D6 73 A3 78 A2 79 K9 36 L9 38 L10 39 BGA96 E2 E3 G1 G2 G3 H1 H2 H3 J1 J2 J4 L5 K5 L3 K3 J5 K6 J6 L7 K7 J7 K8 C1 C2 B3 D1 D2 D3 E1 C4 B4 C5 B5 A3 A2 K9 L9 L10 LQFP/ QFN- 64 5 6 7 8 9 10 11 12 13 14 15 19 20 22 23 24 25 26 27 2 3 4 60 59 58 62 63 28 30 31 Document Number: 002-05635 Rev. *C Page 33 of 126 CY9A340NB Series Pin Function Pin Name Multifunction Serial 0 SIN0_0 SIN0_1 SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) Multifunction Serial 1 SCK0_1 (SCL0_1) SIN1_1 SOT1_1 (SDA1_1) SCK1_1 (SCL1_1) Function Description LQFP100 Multi-function serial interface 73 ch.0 input pin 56 Multi-function serial interface ch.0 output pin. This pin operates as SOT0 72 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA0 when it is used in an I2C (operation mode 57 4). Multi-function serial interface ch.0 clock I/O pin. 71 This pin operates as SCK0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL0 when it is used in an I2C (operation mode 58 4). Multi-function serial interface ch.1 input pin 53 Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO (operation modes 54 0 to 2) and as SDA1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/ 55 CSIO (operation modes 0 to 2) and as SCL1 when it is used in an I2C (operation mode 4). QFP100 51 34 50 35 49 36 31 32 33 Pin No BGA- LQFP- 112 80 C11 59 H9 46 BGA96 C11 H9 E8 58 D9 H7 47 G10 D10 57 D10 G10 48 G9 J10 43 J10 J8 44 J8 H10 45 H10 LQFP/ QFN- 64 48 47 - 46 35 36 37 Document Number: 002-05635 Rev. *C Page 34 of 126 CY9A340NB Series Pin Function Pin Name Multifunction Serial 2 SIN2_2 SOT2_2 (SDA2_2) SCK2_2 (SCL2_2) Multifunction Serial 3 SIN3_1 SIN3_2 SOT3_1 (SDA3_1) SOT3_2 (SDA3_2) Function Description LQFP100 Multi-function serial interface ch.2 input pin 59 Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO (operation modes 63 0 to 2) and as SDA2 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a UART/ 64 CSIO (operation modes 0 to 2) and as SCL2 when it is used in an I2C (operation mode 4). Multi-function serial interface 2 ch.3 input pin 39 QFP100 37 41 42 80 17 Multi-function serial interface ch.3 output pin. 3 81 This pin operates as SOT3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA3 when it is used in an I2C (operation mode 40 18 4). Pin No BGA- LQFP- 112 80 BGA96 G9 49 F10 G8 53 F9 F10 54 E11 C1 2 C1 K6 29 J5 C2 3 C2 J6 30 K6 LQFP/ QFN- 64 40 44 45 2 3 - SCK3_1 (SCL3_1) Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 4 82 B3 4 B3 4 when it is used in a UART/ SCK3_2 (SCL3_2) CSIO (operation modes 0 to 2) and as SCL3 when it is used in 41 an I2C (operation mode 4). 19 L7 31 J6 - Document Number: 002-05635 Rev. *C Page 35 of 126 CY9A340NB Series Pin Function Pin Name Multifunction Serial 4 SIN4_0 SIN4_1 SIN4_2 SOT4_0 (SDA4_0) SOT4_1 (SDA4_1) Multifunction Serial 5 SOT4_2 (SDA4_2) SCK4_0 (SCL4_0) SCK4_1 (SCL4_1) SCK4_2 (SCL4_2) RTS4_0 RTS4_1 RTS4_2 CTS4_0 CTS4_1 CTS4_2 SIN5_0 SIN5_2 SOT5_0 (SDA5_0) SOT5_2 (SDA5_2) Function Description Multi-function serial interface ch.4 input pin LQFP100 87 65 82 QFP100 65 43 60 Multi-function serial interface 88 66 ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO (operation modes 66 44 0 to 2) and as SDA4 when it is used in an I2C (operation mode 4). 83 61 Multi-function serial interface 89 67 ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a UART/ 67 45 CSIO (operation modes 0 to 2) and as SCL4 when it is used in an I2C (operation mode 4). 84 62 90 68 Multi-function serial interface ch.4 RTS output pin 69 47 86 64 91 69 Multi-function serial interface ch.4 CTS input pin 68 46 85 63 Multi-function serial interface 96 74 ch.5 input pin 15 93 Multi-function serial interface ch.5 output pin. 95 73 This pin operates as SOT5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA5 when it is used in an I2C (operation mode 16 94 4). Pin No BGA- LQFP- 112 80 D7 67 F9 55 C8 - BGA96 C8 E10 - A6 68 C7 E11 56 E9 D9 - - B6 69 B7 E10 - - A7 - - C6 70 B6 E9 - - C7 - - A5 71 C6 F8 - - B7 - - C4 76 C4 F3 - - B4 75 B4 G1 - - LQFP/ QFN- 64 54 55 - - 56 - 60 - 59 - SCK5_0 (SCL5_0) Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 94 72 C5 74 C5 58 when it is used in a UART/ SCK5_2 (SCL5_2) CSIO (operation modes 0 to 2) and as SCL5 when it is used in 17 an I2C (operation mode 4). 95 G2 - - - Document Number: 002-05635 Rev. *C Page 36 of 126 CY9A340NB Series Pin Function Pin Name Multifunction Serial 6 SIN6_0 SIN6_1 SOT6_0 (SDA6_0) SOT6_1 (SDA6_1) Function Description Multi-function serial interface ch.6 input pin LQFP100 5 12 QFP100 83 90 Multi-function serial interface ch.6 output pin. 6 84 This pin operates as SOT6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA6 when it is used in an I2C (operation mode 11 89 4). Pin No BGA- LQFP- 112 80 D1 5 E4 12 BGA96 D1 G2 D2 6 D2 E3 11 G1 LQFP/ QFN- 64 8 - 7 SCK6_0 (SCL6_0) Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 7 85 D3 7 D3 - when it is used in a UART/ SCK6_1 (SCL6_1) CSIO (operation modes 0 to 2) and as SCL6 when it is used in 10 an I2C (operation mode 4). 88 E2 10 E3 6 Multifunction SIN7_1 Multi-function serial interface ch.7 input pin 45 23 K8 35 K8 27 Serial 7 Multi-function serial interface ch.7 output pin. This pin operates as SOT7 SOT7_1 (SDA7_1) when it is used in a UART/CSIO (operation modes 44 22 J7 34 J7 26 0 to 2) and as SDA7 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 clock I/O pin. SCK7_1 (SCL7_1) This pin operates as SCK7 when it is used in a UART/ 43 CSIO (operation modes 0 to 2) 21 H6 33 K7 25 and as SCL7 when it is used in an I2C (operation mode 4). Document Number: 002-05635 Rev. *C Page 37 of 126 CY9A340NB Series Pin Function Pin Name USB UDM0 UDP0 UHCONX Real-time clock RTCCO_0 RTCCO_1 RTCCO_2 SUBOUT_0 SUBOUT_1 SUBOUT_2 Low-Power Consumption WKUP0 Mode WKUP1 WKUP2 HDMICEC/ Remote Control Reception Reset Mode WKUP3 CEC0 CEC1 INITX MD0 Power MD1 VCC Function Description LQFP100 USB device/host D pin 98 USB device/host D + pin 99 USB external pull-up control pin 95 92 0.5 seconds pulse output pin of Real-time clock 55 19 92 Sub clock output pin 55 19 Deep standby mode return signal input pin 0 92 Deep standby mode return signal input pin 1 53 Deep standby mode return signal input pin 2 73 Deep standby mode return signal input pin 3 96 HDMI-CEC/Remote Control Reception ch.0 input/output pin 43 HDMI-CEC/Remote Control Reception ch.1 input/output pin 96 External Reset Input pin. A reset is valid when INITX=L. 38 Mode 0 pin. During normal operation, MD0=L must be input. During serial programming to Flash 47 memory, MD0=H must be input. Mode 1 pin. During serial programming to Flash memory, MD1=L must 46 be input. 1 26 35 Power supply Pin 51 76 97 QFP100 76 77 73 70 33 97 70 33 97 70 31 51 74 21 74 16 25 24 79 4 13 29 54 75 Pin No BGA- LQFP- 112 80 A3 78 A2 79 BGA96 A3 A2 B4 75 B4 B5 72 A6 H10 45 H10 G3 14 H1 B5 72 A6 H10 45 H10 G3 14 H1 B5 72 A6 J10 43 J10 C11 59 C11 C4 76 C4 H6 33 K7 C4 76 C4 K4 28 K4 L8 37 L8 K9 36 K9 B1 1 B1 J1 - - K1 25 K1 K11 41 K11 A10 - - A4 77 A4 LQFP/ QFN- 64 62 63 59 57 37 10 57 37 10 57 35 48 60 25 60 21 29 28 1 18 33 61 Document Number: 002-05635 Rev. *C Page 38 of 126 CY9A340NB Series Pin Function GND Pin Name Function Description LQFP100 - QFP100 - Pin No BGA- LQFP- 112 80 - - BGA96 F1 LQFP/ QFN- 64 - - - - - F2 - - - - - F3 - - - B2 - B2 - 25 3 L1 20 L1 16 - - K2 - K2 - - - J3 - J3 - - - H4 - - - - - - - L6 - 34 12 L4 24 L4 - 50 28 L11 40 L11 32 VSS GND Pin - - K10 - K10 - - - J9 - J9 - - - H8 - - - - - B10 - B10 - - - C9 - C9 - - - - - D11 - 75 53 A11 - A11 - - - D8 - - - - - - - A7 - - - D4 - - - - - C3 - C3 - - - - - A5 - 100 78 A1 80 A1 64 Clock X0 Main clock (oscillation) input pin 48 26 L9 38 L9 30 X0A Sub clock (oscillation) input pin 36 14 L3 26 L3 19 X1 Main clock (oscillation) I/O pin 49 27 L10 39 L10 31 X1A Sub clock (oscillation) I/O pin 37 15 K3 27 K3 20 CROUT_0 Built-in high-speed CR-osc 74 52 C10 60 C10 - CROUT_1 clock output port 92 70 B5 72 A6 57 ADC power AVCC A/D converter analog power supply pin 60 38 H11 50 H11 41 AVRH A/D converter analog reference voltage input pin 61 39 F11 51 F11 42 ADC GND AVSS A/D converter GND pin 62 40 G11 52 G11 43 C pin C Power supply stabilization capacity pin 33 11 L2 23 L2 17 Note: - While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: 002-05635 Rev. *C Page 39 of 126 CY9A340NB Series 5. I/O Circuit Type Type A X1 R Circuit Pull-up resistor P-ch P-ch N-ch Feedback resistor Digital output Remarks It is possible to select the main oscillation / GPIO function When the main oscillation is selected. - Oscillation feedback resistor : Approximately 1M - With Standby mode control Digital output - When the GPIO is selected. - CMOS level output. - CMOS level hysteresis input - With pull-up resistor control Pull-up resistor control - With standby mode control Digital input - Pull-up resistor : Approximately 33 k Standby mode control - IOH= -4 mA, IOL= 4 mA Clock input Pull-up resistor R P-ch P-ch X0 Standby mode control Digital input Standby mode control Digital output N-ch Digital output B Pull-up resistor Pull-up resistor control - CMOS level hysteresis input - Pull-up resistor : Approximately 33 k Digital input Document Number: 002-05635 Rev. *C Page 40 of 126 Type C N-ch Circuit CY9A340NB Series Digital input Digital output Remarks - Open drain output - CMOS level hysteresis input D X1A X0A Pull-up resistor P-ch P-ch Digital output It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected. - Oscillation feedback resistor : Approximately 5 M - With Standby mode control - When the GPIO is selected. N-ch Digital output - CMOS level output. R - CMOS level hysteresis input - With pull-up resistor control - With Standby mode control Pull-up resistor control - Digital input - Pull-up resistor : Approximately 33 k IOH= -4 mA, IOL= 4 mA Standby mode control Feedback resistor Clock input Pull-up resistor R P-ch P-ch Standby mode control Digital input Standby mode control Digital output N-ch Digital output Pull-up resistor control Document Number: 002-05635 Rev. *C Page 41 of 126 Type E F CY9A340NB Series Circuit P-ch P-ch Digital output N-ch Digital output R Remarks - CMOS level output - CMOS level hysteresis input - With pull-up resistor control - With Standby mode control - Pull-up resistor : Approximately 33 k - IOH= -4 mA, IOL= 4 mA - When this pin is used as an I2C pin, the digital output P-ch transistor is always off P-ch Pull-up resistor control Digital input Standby mode control P-ch Digital output N-ch Digital output - CMOS level output - CMOS level hysteresis input - With input control - Analog input - With pull-up resistor control - With Standby mode control - Pull-up resistor : Approximately 33 k - IOH= -4 mA, IOL= 4 mA - When this pin is used as an I2C pin, the digital output P-ch transistor is always off R Pull-up resistor control Digital input Standby mode control Analog input Input control Document Number: 002-05635 Rev. *C Page 42 of 126 Type G Circuit Mode input CY9A340NB Series Remarks CMOS level hysteresis input H UDP0/P81 Differential UDM0/P80 I P-ch R GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control It is possible to select the USB I/O / GPIO function. When the USB I/O is selected. - Full-speed, Low-speed control UDP output USB Full-speed/Low-speed control UDP input When the GPIO is selected. - CMOS level output - CMOS level hysteresis input - With Standby mode control Differential input USB/GPIO select UDM input UDM output USB Digital input/output direction GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control P-ch Digital output N-ch Digital output - CMOS level output - CMOS level hysteresis input - 5 V tolerant - With pull-up resistor control - With Standby mode control - Pull-up resistor : Approximately 33 k - IOH= -4 mA, IOL= 4 mA - Available to control PZR registers. - When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode control Document Number: 002-05635 Rev. *C Page 43 of 126 CY9A340NB Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Document Number: 002-05635 Rev. *C Page 44 of 126 CY9A340NB Series Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress Inc. recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress Inc. packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Document Number: 002-05635 Rev. *C Page 45 of 126 CY9A340NB Series Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 M). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-05635 Rev. *C Page 46 of 126 CY9A340NB Series 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin near this device. Stabilizing supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/s when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub crystal oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. Surface mount type Size: More than 3.2 mm × 1.5 mm Load capacitance: Approximately 6 pF to 7 pF Lead type Load capacitance: Approximately 6 pF to 7 pF Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. Example of Using an External Clock Device Can be used as general-purpose I/O ports. X0(X0A) X1(PE3), X1A (P47) Set as External clock input Document Number: 002-05635 Rev. *C Page 47 of 126 CY9A340NB Series Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7F would be recommended for this series. Device C CS VSS GND Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC = VCC and AVSS = VSS. Turning on : VCC AVCC AVRH Turning off : AVRH AVCC VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up function of 5 V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. Document Number: 002-05635 Rev. *C Page 48 of 126 8. Block Diagram CY9A340NB Series TRSTX,TCK, TDI,TMS TDO TRACEDx, TRACECLK INITX X0 X1 X0A X1A CROUT AVCC, AVSS, AVRH ANxx ADTGx TIOAx TIOBx SWJ-DP ETM*1 TPIU*1 ROM Table Cortex-M3Core I @40 MHz(Max) D NVIC Sys Dual-Timer WatchDog Timer (Software) Clock Reset Generator WatchDog Timer (Hardware) CSV CLK Main Osc Sub Osc PLL CR 4 MHz Source Clock CR 100 kHz 12-bit A/D Converter Unit 0 Unit 1 Base Timer 16-bit 8ch./ 32-bit 4ch. CEC0,CEC1 RTCCO, SUBOUT WKUPx HDMI-CEC/ Remote Reciver Control Real-Time Clock Deep Standby Ctrl AHB-APB Bridge : APB1 (Max 40 MHz) AHB-APB Bridge : APB2 (Max 40 MHz) AHB-APB Bridge: APB0(Max 40 MHz) Multi-layer AHB (Max 40 MHz) Flash I/F Security SRAM0 8/16 Kbyte SRAM1 8/16 Kbyte On-Chip Flash 64+32 Kbyte/ 128+32 Kbyte/ 256+32 Kbyte USB2.0 (Host/ PHY Device) DMAC 8ch. UDP0/UDM0 UHCONX AHB-AHB Bridge External Bus I/F*2 USB Clock Ctrl PLL LVD Ctrl IRQ-Monitor CRC Accelerator Watch Counter External Interrupt Controller 16-pin + NMI MODE-Ctrl Power-On Reset LVD Regulator GPIO PIN-Function-Ctrl Multi-Function Serial I/F 8ch. (with FIFO ch.4 to ch.7) HW flow control(ch.4)*2 MADx MADATAx MCSXx, MOEX, MWEX, MALE, MRDY, MCLKOUT, MDQMx C INTx NMIX MD0, MD1 P0x, P1x, . . . PEx SCKx SINx SOTx CTS4 RTS4 *1: For the CY9AF341LB/MB, CY9AF342LB/MB, and CY9AF344LB/MB, ETM is not available. *2: For the CY9AF341LB, CY9AF342LB and CY9AF344LB, the External Bus Interface is not available. And the Multi-function Serial Interface does not support hardware flow control in these products. Document Number: 002-05635 Rev. *C Page 49 of 126 9. Memory Size See Memory size in Product Lineup to confirm the memory size. 10. Memory Map Memory Map (1) 0xFFFF_FFFF 0xE010_0000 0xE000_0000 Reserved Cortex-M3 Private Peripherals See the next page "lMemory Map (2)" for the memory size details. Reserved 0x7000_0000 0x6000_0000 0x4400_0000 0x4200_0000 0x4000_0000 0x2400_0000 0x2200_0000 0x2008_0000 0x2000_0000 0x1FFF_0000 0x0020_8000 0x0020_0000 0x0010_4000 0x0010_0000 External Device Area Reserved 32Mbytes Bit band alias Peripherals Reserved 32Mbytes Bit band alias Reserved SRAM1 SRAM0 Reserved Flash(Work area) Reserved Security/CR Trim Flash(Main area) 0x0000_0000 Document Number: 002-05635 Rev. *C CY9A340NB Series 0x41FF_FFFF Peripherals Area Reserved 0x4006_1000 0x4006_0000 0x4005_0000 0x4004_0000 0x4003_F000 0x4003_C000 0x4003_B000 0x4003_A000 0x4003_9000 0x4003_8000 0x4003_7000 0x4003_6000 0x4003_5000 0x4003_4000 0x4003_3000 0x4003_2000 0x4003_1000 0x4003_0000 0x4002_F000 0x4002_E000 DMAC Reserved USB ch.0 EXT-bus I/F Reserved RTC Watch Counter CRC MFS Reserved USB Clock Ctrl LVD/DS mode HDMI-CEC/ Remote Control Receiver GPIO Reserved Int-Req.Read EXTI Reserved CR Trim 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 Reserved A/DC Reserved Base Timer Reserved 0x4001_6000 0x4001_5000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved Flash I/F Page 50 of 126 Memory Map (2) CY9A340NB Series Refer to the programming manual for the detail of Flash main area. CY9AB40N/A40N/340N/140N/150R, CY9B520M/320M/120M Series Flash Programming Manual Document Number: 002-05635 Rev. *C Page 51 of 126 CY9A340NB Series Peripheral Address Map Start address End address 0x4000_0000 0x4000_1000 0x4001_0000 0x4001_1000 0x4001_2000 0x4001_3000 0x4001_5000 0x4001_6000 0x4002_0000 0x4002_5000 0x4002_6000 0x4002_7000 0x4002_8000 0x4002_E000 0x4002_F000 0x4003_0000 0x4003_1000 0x4003_2000 0x4003_3000 0x4003_4000 0x4003_5000 0x4003_5800 0x4003_6000 0x4003_7000 0x4003_8000 0x4003_9000 0x4003_A000 0x4003_B000 0x4003_C000 0x4003_F000 0x4004_0000 0x4005_0000 0x4006_0000 0x4006_1000 0x4000_0FFF 0x4000_FFFF 0x4001_0FFF 0x4001_1FFF 0x4001_2FFF 0x4001_4FFF 0x4001_5FFF 0x4001_FFFF 0x4002_4FFF 0x4002_5FFF 0x4002_6FFF 0x4002_7FFF 0x4002_DFFF 0x4002_EFFF 0x4002_FFFF 0x4003_0FFF 0x4003_1FFF 0x4003_2FFF 0x4003_3FFF 0x4003_4FFF 0x4003_57FF 0x4003_5FFF 0x4003_6FFF 0x4003_7FFF 0x4003_8FFF 0x4003_9FFF 0x4003_AFFF 0x4003_BFFF 0x4003_EFFF 0x4003_FFFF 0x4004_FFFF 0x4005_FFFF 0x4006_0FFF 0x41FF_FFFF Bus AHB APB0 APB1 APB2 AHB Peripherals Flash memory I/F register Reserved Clock/Reset Control Hardware Watchdog timer Software Watchdog timer Reserved Dual Timer Reserved Reserved Base Timer Reserved A/D Converter Reserved Built-in CR trimming Reserved External Interrupt Interrupt Source Check Register Reserved GPIO HDMI-CEC/Remote control Receiver Low-Voltage Detector Deep standby mode Controller USB clock generator Reserved Multi-function serial CRC Watch Counter Real-time clock Reserved External Bus interface USB ch.0 Reserved DMAC register Reserved Document Number: 002-05635 Rev. *C Page 52 of 126 CY9A340NB Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings. INITX=0 This is the period when the INITX pin is the L level. INITX=1 This is the period when the INITX pin is the H level. SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0. SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1. Input enabled Indicates that the input function can be used. Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L. Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state. Setting disabled Indicates that the setting is disabled. Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. Analog input is enabled Indicates that the analog input is enabled. Trace output Indicates that the trace function can be used. GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port. Document Number: 002-05635 Rev. *C Page 53 of 126 CY9A340NB Series List of Pin Status Pin status type Function group Power-on reset or low-volta ge detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep standby RTC mode or Deep standby Stop mode state Return from Deep standby mode state GPIO selected Power supply unstable - Setting disabled Power supply stable INITX = 0 INITX = 1 - - Setting disabled Setting disabled Power supply stable INITX = 1 - Maintain previous state Power supply stable INITX = 1 SPL = 0 SPL = 1 Maintain previous state Hi-Z / Internal input fixed at 0 A Main crystal oscillator input pin/ External main clock input Input enabled selected Input enabled Input enabled Input enabled Input enabled Input enabled Power supply stable INITX = 1 SPL = 0 SPL = 1 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Power supply stable INITX = 1 - GPIO selected Input enabled Input enabled Input enabled GPIO selected External main clock input selected B Main crystal oscillator output pin C INITX input pin Setting disabled Setting disabled Hi-Z / Internal input fixed at 0/ or Input enabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state/Wh en oscillatio n stops*1, Hi-Z / Internal input fixed at 0 Maintain previous state/Whe n oscillation stops*1, Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Maintain previous state Maintain previous state/Wh en oscillatio n stops*1, Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state/Wh en oscillatio n stops*1, Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state Maintain previous state/Wh en oscillatio n stops*1, Hi-Z / Internal input fixed at 0 Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Mode input pin E GPIO selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled GPIO selected Hi-Z / Input enabled GPIO selected Document Number: 002-05635 Rev. *C Page 54 of 126 CY9A340NB Series Pin status type Function group Power-on reset or low-volta ge detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep standby RTC mode or Deep standby Stop mode state Return from Deep standby mode state GPIO selected Power supply unstable - Setting disabled Power supply stable INITX = 0 INITX = 1 - - Setting disabled Setting disabled Power supply stable INITX = 1 - Power supply stable INITX = 1 SPL = 0 SPL = 1 Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 F Sub crystal oscillator input pin / Input External sub clock enabled input selected Input enabled Input enabled Input enabled Input enabled Input enabled Power supply stable INITX = 1 SPL = 0 SPL = 1 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Power supply stable INITX = 1 - GPIO selected Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected External sub clock Setting input selected disabled G Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z/ Internal input fixed at 0 Maintain previous state Sub crystal oscillator output pin Hi-Z / Internal input fixed at 0/ or Input enable Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state/Whe n oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state/When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state/Wh en oscillatio n stops*2, Hi-Z/ Internal input fixed at 0 Maintain previous state/Wh en oscillatio n stops*2, Hi-Z/ Internal input fixed at 0 Maintain previous state/Wh en oscillatio n stops*2, Hi-Z/ Internal input fixed at 0 Document Number: 002-05635 Rev. *C Page 55 of 126 CY9A340NB Series Pin status type Function group Power-on reset or low-volta ge detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Power supply unstable - Power supply stable INITX = 0 INITX = 1 - - Power supply stable INITX = 1 - Power supply stable INITX = 1 SPL = 0 SPL = 1 Deep standby RTC mode or Deep standby Stop mode state Return from Deep standby mode state Power supply stable INITX = 1 SPL = 0 SPL = 1 Power supply stable INITX = 1 - GPIO selected GPIO Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected H USB I/O pin Setting disabled NMIX selected I Resource other than above selected GPIO selected JTAG selected J GPIO selected Setting disabled Hi-Z Hi-Z Setting disabled Resource selected Setting disabled Setting disabled Hi-Z / Input enabled Pull-up / Input enabled Setting disabled Setting disabled Setting disabled Hi-Z / Input enabled Pull-up / Input enabled Setting disabled Maintain previous state Maintain previous state Hi-Z at transmission/ Input enabled/ Internal input fixed at 0 at reception Maintain previous state Hi-Z at transmission/ Input enabled/ Internal input fixed at 0 at reception Maintain previous state Hi-Z / Internal input fixed at 0 Hi-Z / Input enabled WKUP input enabled Hi-Z / Input enabled Hi-Z / WKUP input enabled Hi-Z / Input enabled GPIO selected Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state GPIO selected Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state GPIO selected GPIO selected K GPIO selected GPIO Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 selected Internal input Hi-Z / Internal input fixed at 0 fixed at 0 Document Number: 002-05635 Rev. *C Page 56 of 126 CY9A340NB Series Pin status type Function group Power-on reset or low-volta ge detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep standby RTC mode or Deep standby Stop mode state Return from Deep standby mode state External interrupt enabled selected Resource other L than above selected GPIO selected Analog input selected M Resource other than above selected GPIO selected Power supply unstable - Setting disabled Hi-Z Power supply stable INITX = 0 INITX = 1 - - Setting disabled Setting disabled Hi-Z / Input enabled Hi-Z / Input enabled Power supply stable INITX = 1 - Maintain previous state Power supply stable INITX = 1 SPL = 0 SPL = 1 Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Power supply stable INITX = 1 SPL = 0 SPL = 1 Power supply stable INITX = 1 - GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Analog input selected Hi-Z N External interrupt enabled selected Resource other than above selected Setting disabled GPIO selected Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Document Number: 002-05635 Rev. *C Page 57 of 126 CY9A340NB Series Pin status type Function group Power-on reset or low-volta ge detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep standby RTC mode or Deep standby Stop mode state Return from Deep standby mode state Power supply unstable - Power supply stable INITX = 0 INITX = 1 - - Power supply stable INITX = 1 - Power supply stable INITX = 1 SPL = 0 SPL = 1 Power supply stable INITX = 1 SPL = 0 SPL = 1 Power supply stable INITX = 1 - Trace selected O Resource other than above selected GPIO selected Setting disabled Hi-Z Setting disabled Hi-Z / Input enabled Setting disabled Hi-Z / Input enabled Maintain previous state Maintain previous state Trace output Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Analog input selected P Trace selected Resource other than above selected GPIO selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Analog input selected Q Trace selected External interrupt enabled selected Resource other than above selected GPIO selected Hi-Z Setting disabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Trace output Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Document Number: 002-05635 Rev. *C Page 58 of 126 CY9A340NB Series Pin status type Function group Power-on reset or low-volta ge detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep standby RTC mode or Deep standby Stop mode state Return from Deep standby mode state Analog input selected WKUP R enabled External interrupt enabled selected Resource other than above selected GPIO selected CEC enabled Resource other than above S selected GPIO selected Power supply unstable - Hi-Z Power supply stable INITX = 0 INITX = 1 - - Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Power supply stable INITX = 1 - Hi-Z / Internal input fixed at 0 / Analog input enabled Power supply stable INITX = 1 SPL = 0 SPL = 1 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Power supply stable INITX = 1 SPL = 0 SPL = 1 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled WKUP input enabled Hi-Z / WKUP input enabled Power supply stable INITX = 1 - Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Document Number: 002-05635 Rev. *C Page 59 of 126 CY9A340NB Series Pin status type Function group Power-on reset or low-volta ge detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep standby RTC mode or Deep standby Stop mode state Return from Deep standby mode state CEC enabled WKUP enabled T External interrupt enabled selected Resource other than above selected GPIO selected Power supply unstable - Setting disabled Power supply stable INITX = 0 - Setting disabled INITX = 1 - Setting disabled Power supply stable INITX = 1 - Maintain previous state Power supply stable INITX = 1 SPL = 0 SPL = 1 Maintain Maintain previous previous state state Setting disabled Hi-Z Setting disabled Hi-Z / Input enabled Setting disabled Hi-Z / Input enabled Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Power supply stable INITX = 1 SPL = 0 SPL = 1 Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled Power supply stable INITX = 1 - Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected *1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: Oscillation is stopped at Stop mode and Deep Standby Stop mode. Document Number: 002-05635 Rev. *C Page 60 of 126 CY9A340NB Series 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter Power supply voltage*1, *2 Analog power supply voltage*1, *3 Analog reference voltage*1, *3 Input voltage*1 Analog pin input voltage*1 Output voltage*1 L level maximum output current*4 L level average output current*5 L level total maximum output current L level total average output current*6 H level maximum output current*4 H level average output current*5 H level total maximum output current H level total average output current*6 Power consumption Storage temperature Symbol VCC AVCC AVRH VI VIA VO IOL Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 - Rating Max VSS + 4.6 VSS + 4.6 VSS + 4.6 VCC + 0.5 ( 4.6 V) VSS + 6.5 AVCC + 0.5 ( 4.6 V) VCC + 0.5 ( 4.6 V) 10 39 IOLAV - IOL - IOLAV - IOH - 4 10.5 27 100 50 - 10 39 IOHAV - IOH IOHAV PD TSTG - 55 - 4 12 27 - 100 - 50 300 + 150 Unit V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW °C Remarks 5 V tolerant P81/UDP0 , P80/UDM0 pins *7 *8 P81/UDP0 , P80/UDM0 pins *7 *8 *1: These parameters are based on the condition that VSS = AVSS = 0 V. *2: VCC must not drop below VSS - 0.5 V. *3: Ensure that the voltage does not to exceed VCC + 0.5 V, for example, when the power is turned on. *4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. *7: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80). *8: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0). WARNING: - Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 002-05635 Rev. *C Page 61 of 126 CY9A340NB Series 12.2 Recommended Operating Conditions Parameter Power supply voltage Analog power supply voltage Analog reference voltage Smoothing capacitor Operating temperature Symbol Conditions VCC - AVCC - AVRH - AVRL - CS -- TA - Value Min Max 1.65*4 3.6 3.0*4 3.6 1.65 3.6 2.7 AVCC AVSS 1 - 40 AVCC AVCC AVSS 10 + 85 Unit V V V V V µF °C (VSS = AVSS = 0.0V) Remarks *1 *2 AVCC = VCC AVCC 2.7 V AVCC< 2.7 V For Regulator*3 *1: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80). *2: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0). *3: See C Pin in Handling Devices for the connection of the smoothing capacitor. *4: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. WARNING: - The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 002-05635 Rev. *C Page 62 of 126 CY9A340NB Series 12.3 DC Characteristics 12.3.1 Current rating Parameter Symbol Pin name PLL Run mode High-speed ICC CR Run mode Power supply current VCC Sub Run mode Low-speed CR Run mode PLL Sleep mode High-speed CR Sleep mode ICCS Sub Sleep mode Low-speed CR Sleep mode (VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Conditions CPU: 40 MHz, Peripheral: 40 MHz CPU: 40 MHz, Peripheral: the clock stops NOP operation Value Typ*3 Max*4 15.5 21 8.7 12 Unit mA mA Remarks *1, *5 *1, *5 CPU/ Peripheral: 4 MHz*2 1.8 2.9 mA *1 CPU/ Peripheral: 32 kHz 110 CPU/ Peripheral: 100 kHz 125 Peripheral: 40 MHz 9 Peripheral: 4 MHz*2 0.8 Peripheral: 32 kHz 96 Peripheral: 100 kHz 110 680 A 700 A 12.5 mA 1.6 mA 670 A 680 A *1, *6 *1 *1, *5 *1 *1, *6 *1 *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3: TA=+25°C, VCC=3.6 V *4: TA=+85°C, VCC=3.6 V *5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) Document Number: 002-05635 Rev. *C Page 63 of 126 CY9A340NB Series Parameter Symbol Pin name Conditions ICCT ICCR ICCH Power supply current ICCHD ICCRD Main Timer mode Sub Timer mode RTC mode Stop mode VCC Deep Standby Stop mode Deep Standby RTC mode TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off, When RAM is off TA = + 25°C, When LVD is off, When RAM is on TA = + 85°C, When LVD is off, When RAM is off TA = + 85°C, When LVD is off, When RAM is on TA = + 25°C, When LVD is off, When RAM is off TA = + 25°C, When LVD is off, When RAM is on TA = + 85°C, When LVD is off, When RAM is off TA = + 85°C, When LVD is off, When RAM is on Value Typ*2 Max*2 Unit Remarks mA *1, *3 - mA *1, *3 12 35 A *1, *4 - 330 A *1, *4 9.8 29 A *1, *4 - 280 A *1, *4 9 28 A *1 - 270 A *1 1.25 7 A *1, *4, *5 5.3 18 A *1, *4, *5 70 - 100 1.9 9 A *1, *4, *5 A *1, *4, *5 A *1, *5 5.9 20 A *1, *5 75 A *1, *5 - 105 A *1, *5 *1: When all ports are fixed. *2: VCC=3.6 V *3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) *5: RAM on/off setting is on-chip SRAM only. Document Number: 002-05635 Rev. *C Page 64 of 126 CY9A340NB Series Low-Voltage Detection Current Parameter Symbol Pin name (VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C) Conditions Value Unit Typ Max Remarks At operation for reset 0.13 0.3 Low-voltage VCC = 3.6 V detection circuit (LVD) power ICCLVD VCC supply current At operation for interrupt 0.13 0.3 VCC = 3.6 V A At not detect A At not detect Flash Memory Current Parameter Symbol Pin name (VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C) Conditions Value Unit Typ Max Remarks Flash memory write/erase current ICCFLASH VCC At Write/Erase 9.5 11.2 mA * *: The current at which to write or erase Flash memory, ICCFLASH is added to ICC. A/D Converter Current Parameter Power supply current Symbol ICCAD (VCC = VCC28 = AVCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = AVSS = 0V, TA = - 40°C to +85°C) Pin name Conditions Value Typ Max Unit Remarks AVCC At 1unit operation At stop 0.27 0.42 mA 0.03 10 A At 1unit operation 0.72 1.29 mA Reference power supply current ICCAVRH AVRH AVRH=3.6 V At stop 0.02 2.6 A Document Number: 002-05635 Rev. *C Page 65 of 126 CY9A340NB Series 12.3.2 Pin Characteristics Parameter H level input voltage (hysteresis input) Symbol Pin name Conditions CMOS hysteresis VCC 2.7 V input pin, MD0, MD1 VCC < 2.7 V VIHS VCC 2.7 V 5V tolerant input pin VCC < 2.7 V (VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Value Min Typ Unit Max Remarks VCC × 0.8 - VCC × 0.7 VCC + 0.3 V VCC × 0.8 - VCC × 0.7 VSS + 5.5 V L level input voltage (hysteresis VILS input) CMOS hysteresis input pin, MD0, MD1 VCC 2.7 V VCC < 2.7 V 5V tolerant input pin VCC 2.7 V VCC < 2.7 V VSS - 0.3 - VSS - 0.3 - VCC × 0.2 V VCC × 0.3 VCC × 0.2 V VCC × 0.3 4 mA type VCC 2.7 V, IOH = - 4 mA VCC - 0.5 - VCC V H level output voltage VOH VCC < 2.7 V, IOH = - 2 mA VCC 2.7 V, VCC - 0.45 The pin IOH = - 12 mA doubled as VCC - 0.4 - VCC V USB I/O VCC < 2.7 V, IOH = - 6.5 mA L level output voltage VOL Input leak current IIL VCC 2.7 V, IOL = 4 mA 4 mA type VSS VCC < 2.7 V, IOL = 2 mA VCC 2.7 V, The pin IOL = 10.5 mA doubled as VSS USB I/O VCC < 2.7 V, IOL = 5 mA - CEC0, CEC1 - - 5 VCC = AVCC = AVRH = VSS = AVSS = 0.0 V - 0.4 V - 0.4 V - + 5 A - +1.8 A VCC 2.7 V 21 Pull-up resistor value RPU Pull-up pin VCC < 2.7 V - 33 66 k - 134 Input capacitance CIN Other than VCC, VSS, AVCC, - AVSS, AVRH - 5 15 pF Document Number: 002-05635 Rev. *C Page 66 of 126 CY9A340NB Series 12.4 AC Characteristics 12.4.1 Main Clock Input Characteristics Parameter Input frequency Input clock cycle Input clock pulse width Input clock rising time and falling time Internal operating clock*1 frequency Internal operating clock*1 cycle time Symbol Pin name fCH tCYLH X0, X1 - tCF, tCR fCM - fCC - fCP0 - fCP1 - fCP2 - tCYCC - tCYCP0 - tCYCP1 - tCYCP2 - Conditions VCC 2.7 V VCC < 2.7 V - - PWH/tCYLH, PWL/tCYLH - - (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Unit Min Max Remarks 4 48 4 20 4 48 MHz MHz When crystal oscillator is connected When using external clock 20.83 250 ns When using external clock 45 55 % When using external clock - 5 ns When using external clock - 40 - 40 - 40 - 40 - 40 25 - 25 - 25 - 25 - MHz MHz MHz MHz MHz ns ns ns ns Master clock Base clock (HCLK/FCLK) APB0 bus clock*2 APB1 bus clock*2 APB2 bus clock*2 Base clock (HCLK/FCLK) APB0 bus clock*2 APB1 bus clock*2 APB2 bus clock*2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual. *2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet. X0 Document Number: 002-05635 Rev. *C Page 67 of 126 CY9A340NB Series 12.4.2 Sub Clock Input Characteristics Parameter Input frequency Input clock cycle Input clock pulse width Symbol Pin name Conditions fCL tCYLL - X0A, X1A - PWH/tCYLL, PWL/tCYLL Min 32 10 45 (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Unit Typ Max Remarks 32.768 - - 100 kHz When crystal oscillator is connected kHz When using external clock - 31.25 s When using external clock - 55 % When using external clock X0A 12.4.3 Built-in CR Oscillation Characteristics Built-in High-speed CR Parameter Clock frequency Frequency stabilization time Symbol Conditions TA = + 25°C VCC 2.7 V TA = + 25°C fCRH VCC < 2.7 V (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Unit Min Typ Max Remarks 3.96 4 4.04 3.9 4 4.1 When trimming*1 MHz TA = - 40°C to + 85°C 3.84 4 4.16 TA = - 40°C to + 85°C 2.8 - tCRWT - - - 5.2 When not trimming 30 s *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value. This period is able to use High-speed CR clock as source clock. Built-in Low-speed CR Parameter Symbol Conditions (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Unit Min Typ Max Remarks Clock frequency fCRL - 50 100 150 kHz Document Number: 002-05635 Rev. *C Page 68 of 126 CY9A340NB Series 12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL) Parameter PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiple rate PLL macro oscillation clock frequency Main PLL clock frequency*2 USB clock frequency*3 (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Symbol Unit Min Typ Max Remarks tLOCK 100 - fPLLI 4 - - 5 - fPLLO 75 - fCLKPLL - - fCLKSPLL - - - s 16 MHz 37 multip le 150 MHz 40 MHz 48 MHz After the M frequency division *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. *3: For more information about USB clock, see Chapter 2-2: USB Clock Generation in FM3 Family Peripheral Manual Communication Macro Part. 12.4.5 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock of the Main PLL) Parameter PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiple rate PLL macro oscillation clock frequency Main PLL clock frequency*2 Symbol Min Value Typ (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Unit Max Remarks tLOCK 100 - - fPLLI 3.8 4 4.2 - 19 - 35 fPLLO 72 - 150 fCLKPLL - - 40 s MHz multiple MHz MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. Note: - Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency/temperature has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. Document Number: 002-05635 Rev. *C Page 69 of 126 CY9A340NB Series Main PLL connection Main clock (CLKMO) High-speed CR clock (CLKHC) PLL input K clock divider Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider USB PLL connection Main clock (CLKMO) PLL input K clock divider USB PLL PLL macro oscillation clock M divider USB clock N divider Document Number: 002-05635 Rev. *C Page 70 of 126 CY9A340NB Series 12.4.6 Reset Input Characteristics Parameter Reset input time Symbol Pin name tINITX INITX Conditions - (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Unit Min Max Remarks 500 - ns 12.4.7 Power-on Reset Timing Parameter Symbol Pin name (VSS = 0V, TA = - 40°C to + 85°C) Conditions Value Min Typ Max Unit Remarks Power supply shut down time Power ramp rate Time until releasing Power-on reset tOFF dV/dt tPRT VCC - 1 Vcc:0.2 V to 1.65 V 0.2 - 1.34 - - ms *1 - 1000 mV/s *2 - 16.09 ms *1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met. *2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1 ms). Note: - If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per "12. 4. 6.Reset Input Characteristics". VCC Internal RST CPU Operation 1.65V VDH 0.2V dV/dt 0.2V 0.2V tPRT tOFF RST Active release start Glossary: VDH: detection voltage of Low Voltage detection reset. See "12.7 Low-Voltage Detection Characteristics" Document Number: 002-05635 Rev. *C Page 71 of 126 CY9A340NB Series 12.4.8 External Bus Timing External bus clock output characteristics Parameter Output frequency Symbol Pin name tCYCLE MCLKOUT* (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Conditions Unit Min Max VCC 2.7 V - VCC < 2.7 V - 40 MHz 20 MHz *: The external bus clock output (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see Chapter 12: External Bus Interface in FM3 Family Peripheral Manual. When external bus clock is not output, this characteristic does not give any effect on external bus operation. MCLKOUT External bus signal input/output characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks VIH Signal input characteristics VIL VOH Signal output characteristics VOL 0.8 × VCC V 0.2 × VCC V 0.8 × VCC V 0.2 × VCC V Input signal Output signal VIH VIL VOH VOL VIH VIL VOH VOL Document Number: 002-05635 Rev. *C Page 72 of 126 CY9A340NB Series Separate Bus Access Asynchronous SRAM Mode Parameter MOEX Min pulse width MCSX Address output delay time MOEX Address hold time MCSX MOEX delay time MOEX MCSX time MCSX MDQM delay time Data set up MOEX time MOEX Data hold time MWEX Min pulse width MWEX Address output delay time MCSX MWEX delay time MWEX MCSX delay time MCSX MDQM delay time MWEX Data output time MWEX Data hold time Symbol Pin name tOEW MOEX tCSL AV tOEH - AX MCSX[7:0], MAD[24:0] MOEX, MAD[24:0] tCSL - OEL tOEH - CSH MOEX, MCSX[7:0] tCSL - RDQML MCSX, MDQM[1:0] tDS - OE MOEX, MADATA[15:0] tDH - OE MOEX, MADATA[15:0] tWEW MWEX tWEH - AX MWEX, MAD[24:0] tCSL - WEL tWEH - CSH MWEX, MCSX[7:0] tCSL-WDQML tCSL - DV tWEH - DX MCSX, MDQM[1:0] MCSX, MADATA[15:0] MWEX, MADATA[15:0] Conditions VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Min Max Unit MCLK×n-3 - ns -9 -12 0 MCLK×m-9 MCLK×m-12 0 MCLK×m-9 MCLK×m-12 30 38 +9 ns +12 MCLK×m+9 ns MCLK×m+12 MCLK×m+9 ns MCLK×m+12 MCLK×m+9 ns MCLK×m+12 MCLK×m+9 ns MCLK×m+12 - ns - 0 - ns MCLK×n-3 0 MCLK×n-9 MCLK×n-12 0 MCLK×n-9 MCLK×n-12 MCLK-9 MCLK-12 0 - ns MCLK×m+9 ns MCLK×m+12 MCLK×n+9 ns MCLK×n+12 MCLK×m+9 ns MCLK×m+12 MCLK×n+9 ns MCLK×n+12 MCLK+9 ns MCLK+12 MCLK×m+9 ns MCLK×m+12 Note: - When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16). Document Number: 002-05635 Rev. *C Page 73 of 126 MCLK MCSX[7:0] MAD[24:0] MOEX MDQM[1:0] MWEX MADATA[15:0] CY9A340NB Series Document Number: 002-05635 Rev. *C Page 74 of 126 CY9A340NB Series Separate Bus Access Synchronous SRAM Mode Parameter Address delay time MCSX delay time Symbol Pin name tAV MCLK, MAD[24:0] tCSL MCLK, tCSH MCSX[7:0] tREL MOEX delay time tREH Data set up MCLK time tDS MCLK Data hold time tDH MWEX delay time tWEL tWEH MCLK, MOEX MCLK, MADATA[15:0] MCLK, MADATA[15:0] MCLK, MWEX MDQM[1:0] delay time tDQML tDQMH MCLK, MDQM[1:0] MCLK Data output time tODS MCLK, MADATA[15:0] MCLK Data hold time tOD MCLK, MADATA[15:0] Note: - When the external load capacitance CL = 30 pF. Conditions VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC <2.7 V VCC 2.7 V VCC <2.7 V (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Min Max Unit 1 12 13 ns 1 12 ns 1 1 1 24 37 0 1 1 1 1 MCLK + 1 1 12 ns 9 12 ns 9 12 ns - ns - ns 9 12 ns 9 12 ns 9 12 ns 9 12 ns MCLK + 18 MCLK + 24 ns 18 24 ns MCLK MCSX[7:0] MAD[24:0] MOEX MDQM[1:0] MWEX MADATA[15:0] Document Number: 002-05635 Rev. *C Page 75 of 126 CY9A340NB Series Multiplexed Bus Access Asynchronous SRAM Mode Parameter Multiplexed address delay time Multiplexed address hold time Symbol Pin name tALE-CHMADV tCHMADH MALE, MADATA[15:0] Conditions VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Min Max Unit +10 -2 ns +20 MCLK×n+0 MCLK×n+0 MCLK×n+10 ns MCLK×n+20 Note: - When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16). MCLK MCSX[7:0] MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: 002-05635 Rev. *C Page 76 of 126 CY9A340NB Series Multiplexed Bus Access Synchronous SRAM Mode Parameter MALE delay time MCLK Multiplexed Address delay time MCLK Multiplexed Data output time Symbol Pin name tCHAL tCHAH MCLK, ALE tCHMADV tCHMADX MCLK, MADATA[15:0] Conditions VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Min Max Unit Remarks 9 ns 1 12 ns 9 ns 1 12 ns VCC 2.7 V 1 VCC < 2.7 V tOD ns VCC 2.7 V 1 VCC < 2.7 V tOD ns Note: - When the external load capacitance CL = 30 pF. MCLK MCSX[7:0] MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: 002-05635 Rev. *C Page 77 of 126 CY9A340NB Series External Ready Input Timing Parameter MCLK MRDY input setup time Symbol tRDYI (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Pin name Conditions Unit Min Max Remarks MCLK, MRDY VCC 2.7 V 23 VCC < 2.7 V 37 - ns When RDY is input MCLK ··· Original MOEX MWEX Over 2cycles tRDYI MRDY When RDY is released MCLK Extended MOEX MWEX MRDY ··· ··· 2 cycles tRDYI 0.5×VCC Document Number: 002-05635 Rev. *C Page 78 of 126 CY9A340NB Series 12.4.9 Base Timer Input Timing Timer input timing Parameter Input pulse width Symbol Pin name tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) Conditions (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Unit Min Max Remarks - 2tCYCP - ns ECK TIN tTIWH tTIWL VIHS VIHS VILS VILS Trigger input timing Parameter Input pulse width Symbol Pin name tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) Conditions (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Unit Min Max Remarks - 2tCYCP - ns TGIN tTRGH tTRGL VIHS VIHS VILS VILS Note: - tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet. Document Number: 002-05635 Rev. *C Page 79 of 126 CY9A340NB Series 12.4.10 CSIO/UART Timing CSIO (SPI = 0, SCINV = 0) Parameter Baud rate Serial clock cycle time SCK SOT delay time SIN SCK setup time SCK SIN hold time Serial clock L pulse width Serial clock H pulse width SCK SOT delay time SIN SCK setup time SCK SIN hold time SCK falling time SCK rising time Symbol tSCYC tSLOVI tIVSHI tSHIXI tSLSH tSHSL tSLOVE tIVSHE tSHIXE tF tR Pin name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions Master mode Slave mode (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) VCC < 2.7 V Min Max VCC 2.7 V Min Max Unit - 8 - 8 Mbps 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 36 - ns 0 - 2tCYCP - 10 - tCYCP + 10 - - 50 0 - ns 2tCYCP - 10 - ns tCYCP + 10 - ns - 33 ns 10 - 10 - ns 20 - 20 - ns - 5 - 5 ns - 5 - 5 ns Notes: - The above characteristics apply to clock synchronous mode. - tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. - These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. - When the external load capacitance CL = 30 pF. Document Number: 002-05635 Rev. *C Page 80 of 126 CY9A340NB Series SCK SOT SIN VOH tSHOVI VOH VOL tSCYC VOL tIVSLI VIH VIL tSLIXI VIH VIL Master mode VOH tSHSL tSLSH SCK VIH VIH VIL tF VIL VIL tR tSHOVE SOT VOH VOL SIN tIVSLE VIH VIL tSLIXE VIH VIL Slave mode Document Number: 002-05635 Rev. *C Page 81 of 126 CY9A340NB Series CSIO (SPI = 0, SCINV = 1) Parameter Baud rate Serial clock cycle time SCK SOT delay time SIN SCK setup time SCK SIN hold time Serial clock L pulse width Serial clock H pulse width SCK SOT delay time SIN SCK setup time SCK SIN hold time SCK falling time SCK rising time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSLSH tSHSL tSHOVE tIVSLE tSLIXE tF tR Pin name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions - (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) VCC < 2.7 V Min Max VCC 2.7 V Min Max Unit - 8 - 8 Mbps 4tCYCP - 4tCYCP - ns - 30 Master mode 50 + 30 - 20 - 36 + 20 ns - ns 0 - 0 - ns 2tCYCP - 10 - 2tCYCP - 10 - ns tCYCP + 10 - tCYCP + 10 - ns - 50 - 33 ns Slave mode 10 - 10 - ns 20 - 20 - ns - 5 - 5 ns - 5 - 5 ns Notes: - The above characteristics apply to clock synchronous mode. - tCYCP indicates the APB bus clock cycle time. - About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. - These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. - When the external load capacitance CL = 30 pF. Document Number: 002-05635 Rev. *C Page 82 of 126 CY9A340NB Series SCK SOT SIN VOH tSHOVI VOH VOL tSCYC VOL tIVSLI VIH VIL tSLIXI VIH VIL Master mode VOH tSHSL tSLSH SCK VIH VIH VIL tF VIL VIL tR tSHOVE SOT VOH VOL SIN tIVSLE VIH VIL tSLIXE VIH VIL Slave mode Document Number: 002-05635 Rev. *C Page 83 of 126 CY9A340NB Series CSIO (SPI = 1, SCINV = 0) Parameter Baud rate Serial clock cycle time SCK SOT delay time SIN SCK setup time SCK SIN hold time SOT SCK delay time Serial clock L pulse width Serial clock H pulse width SCK SOT delay time SIN SCK setup time SCK SIN hold time SCK falling time SCK rising time Symbol Pin name tSCYC tSHOVI tIVSLI tSLIXI tSOVLI tSLSH tSHSL tSHOVE tIVSLE tSLIXE tF tR SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions - (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) VCC < 2.7 V Min Max VCC 2.7 V Min Max Unit - 8 - 8 Mbps 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns Master 50 mode 0 - 36 - ns - 0 - ns 2tCYCP - 34 - 2tCYCP - 10 - tCYCP + 10 - - 50 2tCYCP - 34 - ns 2tCYCP - 10 - ns tCYCP + 10 - ns - 33 ns Slave mode 10 - 10 - ns 20 - 20 - ns - 5 - 5 ns - 5 - 5 ns Notes: - The above characteristics apply to clock synchronous mode. - tCYCP indicates the APB bus clock cycle time. - About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. - These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. - When the external load capacitance CL = 30 pF. Document Number: 002-05635 Rev. *C Page 84 of 126 CY9A340NB Series SCK SOT SIN tSOVLI VOH VOL VIH VIL tIVSLI VOL tSCYC VOH tSHOVI tSLIXI VOH VOL VIH VIL VOL Master mode SCK SOT SIN tSLSH tSHSL VIH VIL * tF VOH VOL tIVSLE VIH VIL VIL VIH VIH tR tSLIXE tSHOVE VOH VOL VIH VIL *: Changes when writing to TDR register Slave mode Document Number: 002-05635 Rev. *C Page 85 of 126 CY9A340NB Series CSIO (SPI = 1, SCINV = 1) Parameter Baud rate Serial clock cycle time SCK SOT delay time SIN SCK setup time SCK SIN hold time SOT SCK delay time Serial clock L pulse width Serial clock H pulse width SCK SOT delay time SIN SCK setup time SCK SIN hold time SCK falling time SCK rising time Symbol tSCYC tSLOVI tIVSHI tSHIXI tSOVHI tSLSH tSHSL tSLOVE tIVSHE tSHIXE tF tR Pin name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Conditions - (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) VCC < 2.7 V Min Max VCC 2.7 V Min Max Unit - 8 4tCYCP - - 8 Mbps 4tCYCP - ns - 30 + 30 - 20 + 20 ns Master mode 50 - 0 - 2tCYCP - 34 - 2tCYCP - 10 - tCYCP + 10 - - 50 Slave mode 10 - 20 - - 5 - 5 36 - ns 0 - ns 2tCYCP - 34 - ns 2tCYCP - 10 - ns tCYCP + 10 - ns - 33 ns 10 - ns 20 - ns - 5 ns - 5 ns Notes: - The above characteristics apply to clock synchronous mode. - tCYCP indicates the APB bus clock cycle time. - About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. - These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. - When the external load capacitance CL = 30 pF. Document Number: 002-05635 Rev. *C Page 86 of 126 SCK SOT SIN SCK SOT SIN CY9A340NB Series VOH VOL tSOVHI tIVSHI VIH VIL VOH tSCYC tSLOVI tSHIXI VOL VOH VOL VIH VIL Master mode VOH tR VIL VIH VOH VOL VIH VIL tIVSHE tF tSHSL VIH VIL tSLSH VIL tSLOVE tSHIXE VOH VOL VIH VIL Slave mode Document Number: 002-05635 Rev. *C Page 87 of 126 CY9A340NB Series UART external clock input (EXT = 1) Parameter Serial clock L pulse width Serial clock H pulse width SCK falling time SCK rising time Symbol tSLSH tSHSL tF tR Conditions CL = 30 pF Min tCYCP + 10 tCYCP + 10 - (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Unit Max Remarks - ns - ns 5 ns 5 ns SCK tR t SHSL tF t SLSH V V IL IH V IH V IL V V I L IH Document Number: 002-05635 Rev. *C Page 88 of 126 CY9A340NB Series 12.4.11 External Input Timing Parameter Symbol Pin name Conditions (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Unit Min Max Remarks Input pulse width tINH, tINL ADTG - INTxx, *2 NMIX *3 WKUPx *4 2tCYCP*1 - 2tCYCP + 100*1 - 500 - 600 - ns A/D converter trigger input ns External interrupt ns NMI ns Deep standby wake up *1: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Multi-function Timer is connected to, see Block Diagram in this data sheet. *2: When in Run mode, in Sleep mode. *3: When in Timer mode, in RTC mode, in Stop mode. *4: When in Deep Standby RTC mode, in Deep Standby Stop mode. Document Number: 002-05635 Rev. *C Page 89 of 126 CY9A340NB Series 12.4.12 I2C Timing Parameter Symbol Conditions SCL clock frequency (Repeated) START condition hold time SDA SCL SCL clock L width SCL clock H width (Repeated) START condition setup time SCL SDA Data hold time SCL SDA Data setup time SDA SCL STOP condition setup time SCL SDA Bus free time between STOP condition and START condition Noise filter FSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tSUSTO tBUF tSP CL = 30 pF, R = (Vp/IOL)*1 - (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Standard-mode Min Max Fast-mode Min Max Unit Remarks 0 100 0 400 kHz 4.0 - 0.6 - s 4.7 - 1.3 - s 4.0 - 0.6 - s 4.7 - 0.6 - s 0 3.45*2 0 0.9*3 s 250 - 100 - ns 4.0 - 0.6 - s 4.7 - 1.3 - s 2 tCYCP*4 - 2 tCYCP*4 - ns *1: R and C represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. *3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see Block Diagram in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL Document Number: 002-05635 Rev. *C Page 90 of 126 CY9A340NB Series 12.4.13 ETM Timing Parameter Data hold TRACECLK frequency TRACECLK clock cycle Symbol Pin name tETMH TRACECLK, TRACED[3:0] 1/ tTRACE tTRACE TRACECLK Conditions VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Unit Min Max Remarks 2 11 ns 2 15 - 40 MHz - 20 MHz 25 - ns 50 - ns Note: - When the external load capacitance CL = 30 pF. HCLK TRACECLK TRACED[3:0] Document Number: 002-05635 Rev. *C Page 91 of 126 CY9A340NB Series 12.4.14 JTAG Timing Parameter Symbol Pin name TMS, TDI setup time tJTAGS TMS, TDI hold time tJTAGH TCK, TMS, TDI TCK, TMS, TDI TDO delay time tJTAGD TCK, TDO Conditions VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V VCC 2.7 V VCC < 2.7 V (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Min Max Unit Remarks 15 - ns 15 - ns - 25 ns - 45 Note: - When the external load capacitance CL = 30 pF. TCK TMS/TDI TDO Document Number: 002-05635 Rev. *C Page 92 of 126 CY9A340NB Series 12.5 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Pin name Min Typ Max Unit Remarks Resolution - - - - 12 bit Integral Nonlinearity - - Differential Nonlinearity - - - ± 2 ± 4.5 LSB - ± 2.2 ± 2.5 LSB Zero transition voltage VZT ANxx - ± 6 ± 15 mV Full-scale transition voltage VFST ANxx - AVRH ± 6 AVRH ± 15 mV 2.0*1 - - Conversion time - - 4.0*1 - - s 10*1 - - 0.6 - Sampling time*2 tS - 1.2 - 10 us 3.0 - Compare clock cycle*3 tCCK - 100 200 - 500 1000 ns State transition time to operation tSTT - - - 1.0 s permission Power supply current (analog + digital) - AVCC - 0.27 0.42 0.03 10 mA A Reference power supply current (between AVRH to - AVSS) AVRH - 0.72 1.29 0.02 2.6 mA A Analog input capacity CAIN - - - 9.4 pF 2.2 Analog input resistor RAIN - - - 5.5 k 10.5 Interchannel disparity - - - - 4 LSB Analog port input leak current - ANxx - - 5 A Analog input voltage - ANxx AVSS - AVRH V Reference voltage 2.7 AVRH - AVCC AVCC V - AVRL AVSS - AVSS V *1: The conversion time is the value of sampling time (tS) + compare time (tC). AVCC 2.7 V 1.8 V< AVCC < 2.7 V 1.65 V< AVCC < 1.8 V AVCC 2.7 V 1.8 V< AVCC < 2.7 V 1.65 V< AVCC < 1.8 V AVCC 2.7 V 1.8 V< AVCC < 2.7 V 1.65 V< AVCC < 1.8 V A/D 1unit operation When A/D stops A/D 1unit operation AVRH=3.6 V When A/D stops AVCC 2.7 V 1.8 V< AVCC < 2.7 V 1.65 V< AVCC < 1.8 V AVCC 2.7 V AVCC < 2.7 V The condition of the minimum conversion time is the following. AVCC 2.7 V, HCLK=40 MHz sampling time: 0.6 s, compare time: 1.4 s 1.8 V < AVCC < 2.7 V, HCLK=40 MHz sampling time: 1.2 s, compare time: 2.8 s 1.65 V < AVCC < 1.8 V, HCLK=40 MHz sampling time: 3 s, compare time: 7 s Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK). For setting of the sampling time and the compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual Analog Macro Port. The register setting of the A/D Converter are reflected in the operation according to the APB bus clock timing. The sampling clock and compare clock is generated from the Base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see Block Diagram in this data sheet. *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1). Document Number: 002-05635 Rev. *C Page 93 of 126 *3: The compare time (tC) is the value of (Equation 2). Analog signal source REXT ANxx Analog input pin RAIN CY9A340NB Series Comparator CAIN (Equation 1) tS ( RAIN + REXT ) × CAIN × 9 tS: RAIN: CAIN: REXT: Sampling time[ns] Input resistor of A/D[k] = 2.2 k at 2.7 V < AVCC < 3.6 V Input resistor of A/D[k] = 5.5 k at 1.8 V < AVCC < 2.7 V Input resistor of A/D[k] = 10.5 k at 1.65 V < AVCC < 1.8 V Input capacity of A/D[pF] = 9.4 pF at 1.65 V < AVCC < 3.6 V Output impedance of external circuit[k] (Equation 2) tC = tCCK × 14 tC: Compare time tCCK: Compare clock cycle Document Number: 002-05635 Rev. *C Page 94 of 126 CY9A340NB Series Definition of 12-bit A/D Converter Terms · Resolution: · Integral Nonlinearity: · Differential Nonlinearity: Analog variation that is recognized by an A/D converter. Deviation of the line between the zero-transition point (0b000000000000 0b000000000001) and the full-scale transition point (0b111111111110 0b111111111111) from the actual conversion characteristics. Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Digital output Digital output Integral Nonlinearity 0xFFF Actual conversion 0xFFE characteristics {1 LSB(N-1) + VZT} 0xFFD VFST (Actually- measured 0x004 value) VNT (Actually-measured 0x003 value) Actual conversion 0x002 characteristics Ideal characteristics 0x001 VZT (Actually-measured value) Differential Nonlinearity 0x(N+1) Actual conversion characteristics Ideal characteristics 0xN 0x(N-1) 0x(N-2) V(N+1)T (Actually-measured value) VNT (Actually-measured value) Actual conversion characteristics AVSS Analog input AVRH AVSS Analog input AVRH Linearity error of digital output N = VNT - {1LSB × (N - 1) + VZT} 1LSB [LSB] Differential linearity error of digital output N = V(N + 1) T - VNT 1LSB - 1 [LSB] 1LSB = VFST - VZT 4094 N: VZT: VFST: VNT: A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N - 1) to 0xN. Document Number: 002-05635 Rev. *C Page 95 of 126 CY9A340NB Series 12.6 USB Characteristics Parameter Input characteristics Input H level voltage Input L level voltage Differential input sensitivity Different common mode range Output H level voltage Output L level voltage Output characteristics Crossover voltage Rising time Falling time Rising/falling time matching Output impedance Rising time Falling time Rising/falling time matching Symbol VIH VIL Pin name (VCC = 3.0V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Conditions Value Min Max Unit Remarks - 2.0 VCC + 0.3 V *1 - VSS - 0.3 0.8 V *1 VDI - 0.2 - V *2 VCM VOH VOL VCRS tFR tFF tFRFM ZDRV tLR tLF tLRFM - 0.8 UDP0, UDM0 External pull-down resistor = 15 2.8 k External pull-up resistor = 1.5 0 k - 1.3 Full-Speed 4 Full-Speed 4 Full-Speed 90 Full-Speed 28 Low-Speed 75 Low-Speed 75 Low-Speed 80 2.5 3.6 0.3 2.0 20 20 111.11 44 300 300 125 V *2 V *3 V *3 V *4 ns *5 ns *5 % *5 *6 ns *7 ns *7 % *7 *1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V, VIH (Min) = 2.0 V (TTL input standard). There are some hysteresis to lower noise sensitivity. *2: Use the differential-Receiver to receive the USB differential data signal. The Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local ground reference level. Above voltage range is the common mode input voltage range. Minimum differential input sensitivity [V] Common mode input voltage [V] Document Number: 002-05635 Rev. *C Page 96 of 126 CY9A340NB Series *3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 k load), and 2.8 V or above (to ground and 15 k load) at High-State (VOH). *4: The cross voltage of the external differential output signal (D + /D -) of USB I/O buffer is within 1.3 V to 2.0 V. VCRS specified range *5: They indicate the rising time (Trise) and falling time (Tfall) of the full-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission. Rising time Falling time Document Number: 002-05635 Rev. *C Page 97 of 126 CY9A340NB Series *6: USB Full-speed connection is performed via twist pair cable shield with 90 ± 15% characteristic impedance (Differential Mode). USB standard defines that output impedance of USB driver must be in range from 28 to 44 . So, discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB I/O, use it with 25 to 30 (recommendation value 27 ) Series resistor Rs. 28 to 44 Equiv. Imped. 28 to 44 Equiv. Imped. Mount it as external resistor. Rs series resistor 25 to 30 Series resistor of 27 (recommendation value) must be added. And, use resistance with an uncertainty of 5% by E24 sequence. *7: They indicate the rising time (Trise) and falling time (Tfall) of the low-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. Rising time Falling time See Figure Low-Speed Load (Compliance Load) for conditions of the external load. Document Number: 002-05635 Rev. *C Page 98 of 126 Low-Speed Load (Upstream Port Load) - Reference 1 Low-Speed Load (Downstream Port Load) - Reference 2 CY9A340NB Series CL = 50pF to 150pF CL = 50pF to 150pF Low-Speed Load (Compliance Load) CL = 200pF to 600pF CL = 200pF to 600pF CL = 200pF to 450pF CL = 200pF to 450pF Document Number: 002-05635 Rev. *C Page 99 of 126 CY9A340NB Series 12.7 Low-Voltage Detection Characteristics 12.7.1 Low-Voltage Detection Reset Parameter Symbol Conditions Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage LVD stabilization wait time LVD detection delay time VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH tLVDW tLVDDL SVHR*1 = 00000 SVHR*1 = 00001 SVHR*1 = 00010 SVHR*1 = 00011 SVHR*1 = 00100 SVHR*1 = 00101 SVHR*1 = 00110 SVHR*1 = 00111 SVHR*1 = 01000 SVHR*1 = 01001 SVHR*1 = 01010 SVHR*1 = 01011 SVHR*1 = 01100 SVHR*1 = 01101 SVHR*1 = 01110 SVHR*1 = 01111 SVHR*1 = 10000 SVHR*1 = 10001 SVHR*1 = 10010 SVHR*1 = 10011 - (TA = - 40°C to + 85°C) Value Min Typ Max 1.38 1.50 1.60 1.43 1.55 1.65 1.43 1.55 1.65 Same as SVHR = 00000 value 1.47 1.60 1.73 Same as SVHR = 00000 value 1.52 1.65 1.78 Same as SVHR = 00000 value 1.56 1.70 1.84 Same as SVHR = 00000 value 1.61 1.75 1.89 Same as SVHR = 00000 value 1.66 1.80 1.94 Same as SVHR = 00000 value 1.70 1.85 2.00 Same as SVHR = 00000 value 1.75 1.90 2.05 Same as SVHR = 00000 value 1.79 1.95 2.11 Same as SVHR = 00000 value 1.84 2.00 2.16 Same as SVHR = 00000 value 1.89 2.05 2.21 Same as SVHR = 00000 value 2.30 2.50 2.70 Same as SVHR = 00000 value 2.39 2.60 2.81 Same as SVHR = 00000 value 2.48 2.70 2.92 Same as SVHR = 00000 value 2.58 2.80 3.02 Same as SVHR = 00000 value 2.67 2.90 3.13 Same as SVHR = 00000 value 2.76 3.00 3.24 Same as SVHR = 00000 value 2.85 3.10 3.35 Same as SVHR = 00000 value 2.94 3.20 3.46 Same as SVHR = 00000 value Unit Remarks V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises - - 5200 × tCYCP*2 s - - 200 s *1: The SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is initialized to 00000 by Low-Voltage Detection Reset. *2: tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-05635 Rev. *C Page 100 of 126 CY9A340NB Series 12.7.2 Interrupt of Low-Voltage Detection Parameter Symbol Conditions Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage LVD stabilization wait time LVD detection delay time VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH tLVDW tLVDDL SVHI = 00100 SVHI = 00101 SVHI = 00110 SVHI = 00111 SVHI = 01000 SVHI = 01001 SVHI = 01010 SVHI = 01011 SVHI = 01100 SVHI = 01101 SVHI = 01110 SVHI = 01111 SVHI = 10000 SVHI = 10001 SVHI = 10010 SVHI = 10011 - *: tCYCP indicates the APB2 bus clock cycle time. Min 1.56 1.61 1.61 1.66 1.66 1.70 1.70 1.75 1.75 1.79 1.79 1.84 1.84 1.89 1.89 1.93 2.30 2.39 2.39 2.48 2.48 2.58 2.58 2.67 2.67 2.76 2.76 2.85 2.85 2.94 2.94 3.04 - Value Typ Max 1.70 1.84 1.75 1.89 1.75 1.89 1.80 1.94 1.80 1.94 1.85 2.00 1.85 2.00 1.90 2.05 1.90 2.05 1.95 2.11 1.95 2.11 2.00 2.16 2.00 2.16 2.05 2.21 2.05 2.21 2.10 2.27 2.50 2.70 2.60 2.81 2.60 2.81 2.70 2.92 2.70 2.92 2.80 3.02 2.80 3.02 2.90 3.13 2.90 3.13 3.00 3.24 3.00 3.24 3.10 3.35 3.10 3.35 3.20 3.46 3.20 3.46 3.30 3.56 - 5200 × tCYCP* (TA = - 40°C to + 85°C) Unit Remarks V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises V When voltage drops V When voltage rises s - - 200 s Document Number: 002-05635 Rev. *C Page 101 of 126 CY9A340NB Series 12.8 Flash Memory Write/Erase Characteristics 12.8.1 Write / Erase time Parameter Sector erase time Large Sector Small Sector Half word (16-bit) write time Chip erase time Value Typ* Max* 1.1 2.7 0.3 0.9 30 528 6.8 18 (VCC = 1.65V to 3.6V, TA = - 40°C to + 85°C) Unit Remarks s Includes write time prior to internal erase s Not including system-level overhead time s Includes write time prior to internal erase *: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write. 12.8.2 Write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) 1,000 20* 10,000 10* *: At average + 85C Remarks Document Number: 002-05635 Rev. *C Page 102 of 126 CY9A340NB Series 12.9 Return Time from Low-Power Consumption Mode 12.9.1 Return Factor: Interrupt/WKUP The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time Parameter Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Low-speed CR Timer mode Sub Timer mode RTC mode, Stop mode Deep Standby RTC mode Deep Standby Stop mode Symbol (VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C) Value Typ Max* Unit Remarks tCYCC s 40 80 s 350 tICNT 690 278 318 278 700 s 880 s 523 s 603 s When RAM is off 523 s When RAM is on *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by external interrupt*) External interrupt Interrupt factor accept Active tICNT CPU Operation *: External interrupt is set to detecting fall edge. Interrupt factor clear by CPU Start Document Number: 002-05635 Rev. *C Page 103 of 126 CY9A340NB Series Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal resource interrupt Interrupt factor accept Active tICNT Interrupt factor clear by CPU CPU Operation Start *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: - The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. - When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. Document Number: 002-05635 Rev. *C Page 104 of 126 CY9A340NB Series 12.9.2 Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time Parameter Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Low-speed CR Timer mode Sub Timer mode RTC/Stop mode Deep Standby RTC mode Deep Standby Stop mode Symbol (VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C) Value Typ Max* Unit Remarks 148 263 s 148 263 s 258 483 s tRCNT 322 516 s 278 523 s 318 603 s When RAM is off 278 523 s When RAM is on *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by INITX) INITX Internal reset Reset active tRCNT Release CPU Operation Start Document Number: 002-05635 Rev. *C Page 105 of 126 CY9A340NB Series Operation example of return from low power consumption mode (by internal resource reset*) Internal resource reset Internal reset Reset active tRCNT Release CPU Operation Start *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: - The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. - When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. - The time during the power-on reset/low-voltage detection reset is excluded. See (6) Power-on Reset Timing in 4. AC Characteristics in Electrical Characteristics for the detail on the time during the power-on reset/low-voltage detection reset. - When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time. - The internal resource reset means the watchdog reset and the CSV reset. Document Number: 002-05635 Rev. *C Page 106 of 126 CY9A340NB Series 13. Ordering Information Part number On-chip Flash memory CY9AF341LBPMC1-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte CY9AF342LBPMC1-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte Main: 256 Kbyte CY9AF344LBPMC1-G-JNE2 Work: 32 Kbyte CY9AF341LBPMC-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte CY9AF342LBPMC-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte CY9AF344LBPMC-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte CY9AF341LBQN-G-AVE2 Main: 64 Kbyte Work: 32 Kbyte CY9AF342LBQN-G-AVE2 Main: 128 Kbyte Work: 32 Kbyte CY9AF344LBQN-G-AVE2 Main: 256 Kbyte Work: 32 Kbyte CY9AF341MBPMC-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte CY9AF342MBPMC-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte Main: 256 Kbyte CY9AF344MBPMC-G-JNE2 Work: 32 Kbyte CY9AF341MBPMC1-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte CY9AF342MBPMC1-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte CY9AF344MBPMC1-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte CY9AF341MBBGL-GE1 Main: 64 Kbyte Work: 32 Kbyte CY9AF342MBBGL-GE1 Main: 128 Kbyte Work: 32 Kbyte CY9AF344MBBGL-GE1 Main: 256 Kbyte Work: 32 Kbyte CY9AF341NBPMC-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte CY9AF342NBPMC-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte Main: 256 Kbyte CY9AF344NBPMC-G-JNE2 Work: 32 Kbyte On-chip SRAM 16 Kbyte 16 Kbyte 32 Kbyte 16 Kbyte 16 Kbyte 32 Kbyte 16 Kbyte 16 Kbyte 32 Kbyte 16 Kbyte 16 Kbyte 32 Kbyte 16 Kbyte 16 Kbyte 32 Kbyte 16 Kbyte 16 Kbyte 32 Kbyte 16 Kbyte 16 Kbyte 32 Kbyte Package Plastic LQFP 64-pin (0.5mm pitch), (LQD064) Plastic LQFP 64-pin (0.65mm pitch), (LQG064) Plastic QFN 64-pin (0.5mm pitch), (VNC064) Plastic LQFP 80-pin (0.5mm pitch), (LQH080) Plastic LQFP 80-pin (0.65mm pitch), (LQJ080) Plastic PFBGA 96-pin (0.5mm pitch), (FDG096) Plastic LQFP 100-pin (0.5mm pitch), (LQI100) Packing Tray Document Number: 002-05635 Rev. *C Page 107 of 126 CY9A340NB Series Part number CY9AF341NBPQC-G-JNE2 CY9AF342NBPQC-G-JNE2 CY9AF344NBPQC-G-JNE2 CY9AF341NBBGL-GE1 CY9AF342NBBGL-GE1 CY9AF344NBBGL-GE1 On-chip Flash memory Main: 64 Kbyte Work: 32 Kbyte Main: 128 Kbyte Work: 32 Kbyte Main: 256 Kbyte Work: 32 Kbyte Main: 64 Kbyte Work: 32 Kbyte Main: 128 Kbyte Work: 32 Kbyte Main: 256 Kbyte Work: 32 Kbyte On-chip SRAM 16 Kbyte 16 Kbyte 32 Kbyte 16 Kbyte 16 Kbyte 32 Kbyte Package Packing Plastic QFP 100-pin (0.65mm pitch), (PQH100) Tray Plastic PFBGA 112-pin (0.8mm pitch), (LBC112) Document Number: 002-05635 Rev. *C Page 108 of 126 14. Package Dimensions Package Type LQFP 100 Package Code LQI100 75 76 D4 57 D1 51 50 CY9A340NB Series 51 50 D4 57 D1 75 76 3 6 100 1 e 3 0.2 0 C A-B D TOP VIEW 2 E1 E 54 7 26 25 257 0.1 0 C A-B D b 8 0.0 8 C A-B D 0.0 8 C SIDE VIEW A SEATIN G A' PLA N E E1 E 54 7 26 25 100 1 BOTTOM VIEW A L1 0.25 A1 10 L DETAIL A 9 c b SECTIO N A-A ' SYM BOL A A1 b c D D1 e E E1 L L1 DIM ENSIONS M IN. NOM . M AX. 1.70 0.05 0.15 0.15 0.27 0.09 0.20 16.00 BSC 14.00 BSC 0.50 BSC 16.00 BSC 14.00 BSC 0.45 0.60 0.75 0.30 0.50 0.70 NOTES : 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. 2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE M OLD PARTING LINE COINCIDENT W ITH W HERE THE LEAD EXITS THE BODY. 3. DATUM S A-B AND D TO BE DETERM INED AT DATUM PLANE H. 4. TO BE DETERM INED AT SEATING PLANE C. 5. DIM ENSIONS D1 AND E1 DO NOT INCLUDE M OLD PROTRUSION. ALLOW ABLEPROTRUSION IS 0.25m m PRE SIDE. DIM ENSIONS D1 AND E1 INCLUDE M OLD M ISM ATCH AND ARE DETERM INED AT DATUM PLANE H. 6. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT M UST BE LOCATED W ITHIN THE ZONE INDICATED. 7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOW ER BODY SECTIONS. DIM ENSIONS D1 AND E1 ARE DETERM INED AT THE LARGEST FEATURE OF THE BODY EXCLUSIVE OF M OLD FLASH AND GATE BURRS. BUT INCLUDING ANY M ISM ATCH BETW EEN THE UPPER AND LOW ER SECTIONS OF THE M OLDER BODY. 8. DIM ENSION b DOES NOT INCLUDE DAM BAR PROTRUSION. THE DAM BAR PROTRUSION (S) SHALL NOT CAUSE THE LEAD W IDTH TO EXCEED b M AXIM UM BY M ORE THAN 0.08m m . DAM BAR CANNOT BE LOCATED ON THE LOW ER RADIUS OR THE LEAD FOOT. 9. THESE DIM ENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETW EEN 0.10m m AND 0.25m m FROM THE LEAD TIP. 10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOW EST POINT OF THE PACKAGE BODY. 002-11500 *A PACKAGE OUTLINE, 100 LEAD LQFP 14.0X14.0X1.7 M M LQI100 REV*A Document Number: 002-05635 Rev. *C Page 109 of 126 CY9A340NB Series Package Type QFP 100 80 81 Package Code PQH100 D 4 D1 57 51 50 51 50 80 81 6 3 100 1 e 3 0.40 C A-B D TOP VIEW E1 E 54 7 31 30 b 0.13 257 0.20 C A-B D C A-B D 8 31 30 BOTTOM VIEW 2 SID E VIEW 0.10 C A SEATING A' PLANE L2 10 D ETAIL A 100 1 9c b SECTION A-A' SYM BOL A A1 b c D D1 e E E1 L L1 L2 DIM ENSIONS M IN. NOM . M AX. 3.35 0.05 0.45 0.27 0.32 0.37 0.11 0.23 23.90 BSC 20.00 BSC 0.65 BSC 17.90 BSC 14.00 BSC 0° 8° 0.73 0.88 1.03 1.95 REF 0.2 5 BSC Document Number: 002-05635 Rev. *C PACKAGE OUTLINE, 100 LEAD QFP 20.00X14.00X3 .35 M M PQH100 REV** 002-15156 ** Page 110 of 126 CY9A340NB Series Package Type LQFP 80 Package Code LQH080 D4 60 D1 5 7 41 41 60 61 40 40 61 5 7 E1 E 4 3 6 80 21 21 80 1 D e 3 0.20 C A-B D TOP VIEW 20 257 0.10 C A-B D b 0.08 C A-B D 8 20 1 BOTTOM VIEW 2 A SIDE VIEW 0.08 C A SEATIN G 9c A' PLAN E L1 L 0.25 A1 10 b SECTION A-A' SYM BOL A A1 b c D D1 e E E1 L L1 DIM ENSIONS M IN. NOM . M AX. 1.70 0.05 0.15 0.15 0.27 0.09 0.20 14.00 BSC. 12.00 BSC. 0.50 BSC 14.00 BSC. 12.00 BSC. 0.45 0.60 0.75 0.30 0.50 0.70 Document Number: 002-05635 Rev. *C PACKAGE OUTLINE, 80 LEAD LQFP 12.0X12.0X1.7 M M LQH080 Rev ** 002-11501 ** Page 111 of 126 CY9A340NB Series Package Type LQFP 80 Package Code LQJ080 60 61 D4 57 D1 41 40 41 40 60 61 3 6 80 1 e 0.2 0 C A-B D E1 E 54 7 21 20 257 3 0.1 0 C A-B D b d d d C A-B D 8 2 0.1 0 C A SEA TIN G A' PLAN E 21 20 A L1 0.2 5 L 80 1 A1 10 9 c b SECTION A-A' SYM BOL A A1 b c D D1 e E E1 L L1 DIM ENSIONS M IN. NOM . M AX. 1.70 0.00 0.20 0.16 0.32 0.38 0.09 0.20 16.00 BSC 14.00 BSC 0.65 BSC 16.00 BSC 14.00 BSC 0.45 0.60 0.75 0.30 0.50 0.70 0° 8° Document Number: 002-05635 Rev. *C PACKAGE OUTLINE, 80 LEAD LQFP 14.0X14.0X1.7 M M LQJ080 REV** 002-14043 ** Page 112 of 126 CY9A340NB Series Package Type LQFP 64 Package Code LQD064 D4 D1 5 7 48 33 49 3 6 64 32 5 7 E1 E 4 17 33 32 17 48 49 64 1 e 3 0.2 0 C A-B D TOP VIEW 16 b 257 0.1 0 C A-B D 0.0 8 C A-B D 8 16 1 BOTTOM VIEW 2 A 9c A SEA TIN G 0.0 8 C A' PLAN E L1 SIDE VIEW 0.25 A1 L 10 b SECTION A-A' SYM BOL A A1 b c D D1 e E E1 L L1 DIM ENSIONS M IN. NOM . M AX. 1.70 0.00 0.20 0.15 0.2 0.09 0.20 12.00 BSC. 10.00 BSC. 0.50 BSC 12.00 BSC. 10.00 BSC. 0.45 0.60 0.75 0.30 0.50 0.70 Document Number: 002-05635 Rev. *C PACKAGE OUTLINE, 64 LEAD LQFP 10.0X10.0X1.7 M M LQD064 Rev** 002-11499 ** Page 113 of 126 CY9A340NB Series Package Type LQFP 64 Package Code LQG064 48 49 4 D 57 D1 33 32 33 32 48 49 E1 E 54 7 3 64 17 17 64 1 e 3 0.20 C A-B D TOP VIEW 16 b 257 0.10 C A-B D 0.13 C A-B D 8 16 1 BOTTOM VIEW 2 A A SEATI N G A' PLA N E L1 0.10 C SIDE VIEW 0.2 5 L A1 10 9 c b SECTION A -A' SYM BOL A A1 b c D D1 e E E1 L L1 DIM ENSION M IN. NOM . M AX. 1.70 0.00 0.20 0.27 0.32 0.37 0.09 0.20 14.00 BSC 12.00 BSC 0.65 BSC 14.00 BSC 12.00 BSC 0.45 0.60 0.75 0.30 0.50 0.70 0° 8° Document Number: 002-05635 Rev. *C PACKAGE OUTLINE, 64 LEAD LQFP 12.0X12.0X1.7 M M LQG064 REV** 002-13881 ** Page 114 of 126 Package Type QFN 64 48 0.10 C 49 2X Package Code VNC064 D A 33 32 33 32 5 E (ND-1)× e CY9A340NB Series 0.10 C A B D2 48 49 0.10 C A B E2 64 1 IN D EX M ARK 8 TOP VIEW A A1 SIDE VIEW 17 16 B 0.10 C 2X 17 16 9e L BOTTOM VIEW 64 1 b4 0.10 0.05 CAB C 0.10 C 0.05 C SEATINGPLANE C DIM ENSIONS SYMBOL M IN. NOM . M AX. A 0.90 A1 0.00 0.05 D 9.00 BSC E 9.00 BSC b 0.20 0.25 0.30 D2 6.00 BSC E2 6.00 BSC e 0.50 BSC R 0.20 REF L 0.35 0.40 0.45 N 64 ND 16 NOTES: 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. 2. DIM ENSIONING AND TOLERANCING CONFORM S TO ASM E Y14.5M -1994. 3. N IS THE TOTAL NUM BER OF TERM INALS. 4 DIM ENSION "b "APPLIES TO M ETALLIZED TERM INAL AND IS M EASURED BETW EEN 0.15 AND 0.30m m FROM TERM INAL TIP. IF THE TERM INAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERM INAL, THE DIM ENSION "b "SHOULD NOT BE M EASURED IN THAT RADIUS AREA. 5 ND REFERS TO THE NUM BER OF TERM INALS ON D SIDE OR E SIDE. 6. M AX. PACKAGE W ARPAGE IS 0.05m m . 7. M AXIM UM ALLOW ABLE BURR IS 0.076m m IN ALL DIRECTIONS. 8 PIN #1 ID ON TOP W ILL BE LOCATED W ITHIN THE INDICATED ZONE. 9 BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS W ELL AS THE TERM INALS. Document Number: 002-05635 Rev. *C PACKAGE OUTLINE, 64 LEAD QFN 9.0X9.0X0.9 M M VNC064 6.0X6.0 M M EPAD (SAW N) Rev*.* 002-13234 ** Page 115 of 126 CY9A340NB Series Package Type FBGA 112 Package Code LBC112 0.20 C 2X PIN A1 CO RN E R IN D EX M A RK 7 TOP VIEW A B 0.20 C 2X 11 10 9 6 8 7 6 5 4 3 2 1 LK JHGF EDCBA 6 BOTTOM VIEW DETAIL A 0.10 C C D ETAIL A 5 11 2xb 0.08 CAB SID E VIEW SYM BOL A A1 D E D1 E1 MD ME N b eD eE SD SE M IN. - 0.25 0.35 DIM ENSIONS NOM . 0.35 10.00 BSC 10.00 BSC 8.00 BSC 8.00 BSC 11 11 112 0.45 0.80 BSC 0.80 BSC 0.00 0.00 M AX. 1.45 0.45 0.55 N OTES: 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. 2. SOLDER BALL POSITION DESIGNATIO N PER JEP95, SECTION 3, SPP-020. 3. "e"REPRESENTSTHE SOLDER BALL GRID PITCH. 4. SYM BOL "M D"IS THE BALL M ATRIX SIZE IN THE "D"DIRECTION. SYM BOL "M E"IS THE BALL M ATRIX SIZE IN THE "E"DIRECTION. N IS THE NUM BER OF POPULATED SOLDER BALL POSITIONS FOR M ATRIX SIZE M D X M E. 5. DIM ENSION "b"IS M EASURED AT THE MAXIM UM BALL DIAM ETER IN A PLANE PARALLEL TO DATUM C. 6. "SD"AND "SE"ARE M EASURED W ITH RESPECT TO DATUM S A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW . W HEN THERE IS AN ODD NUM BEROF SOLDER BALLS IN THE OUTER ROW , "SD"OR "SE"= 0. W HEN THERE IS AN EVEN NUM BEROF SOLDER BALLS IN THE OUTER ROW , "SD"= eD/2 AND "SE"= eE/2. 7. A1 CORNER TO BE IDENTIFIED BY CHAM FER, LASER OR INK M ARK M ETALIZED M ARK, INDENTATION OR OTHER M EANS. 8. "+ " INDICATESTHE THEORETICAL CENTER OF DEPOPULATED SOLDER BALLS. Document Number: 002-05635 Rev. *C PACKAGE OUTLINE, 112 BALL FBGA 10.00X10.00X1.45 M M LBC112 REV** 002-13225 ** Page 116 of 126 CY9A340NB Series Package Type FBGA 96 Package Code FDG096 A 0.20 C 2X PIN A1 CO RN ER INDEX M ARK 7 TOP VIEW 0.08 C C DETAIL A B 0.20 C 2X 0.20 C 5 96xb 0.0 5 CAB 11 10 9 6 8 7 6 5 4 3 2 1 LK JHGF EDCBA 6 BOTTOM VIEW DETAIL A SIDE VIEW SYM BOL A A1 D E D1 E1 MD ME N b eD eE SD SE M IN. - 0.15 0.20 DIM ENSIONS NOM . 0.25 6.00 BSC 6.00 BSC 5.00 BSC 5.00 BSC 11 11 96 0.30 0.50 BSC 0.50 BSC 0.00 0.00 M AX. 1.30 0.35 0.40 N OTES: 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. 2. SOLDER BALL POSITION DESIGNATIO N PER JEP95, SECTION 3, SPP-020. 3. "e"REPRESENTSTHE SOLDER BALL GRID PITCH. 4. SYM BOL "M D"IS THE BALL M ATRIX SIZE IN THE "D"DIRECTION. SYM BOL "M E"IS THE BALL M ATRIX SIZE IN THE "E"DIRECTION. N IS THE NUM BER OF POPULATED SOLDER BALL POSITIONS FOR M ATRIX SIZE M D X M E. 5. DIM ENSION "b"IS MEASURED AT THE M AXIM UM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 6. "SD"AND "SE"ARE M EASURED W ITH RESPECT TO DATUM S A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW . W HEN THERE IS AN ODD NUM BEROF SOLDER BALLS IN THE OUTER ROW , "SD"OR "SE"= 0. W HEN THERE IS AN EVEN NUM BEROF SOLDER BALLS IN THE OUTER ROW , "SD"= eD/2 AND "SE"= eE/2. 7. A1 CORNER TO BE IDENTIFIED BY CHAM FER, LASER OR INK M ARK M ETALIZED M ARK, INDENTATION OR OTHER M EANS. 8. "+ " INDICATESTHE THEORETICAL CENTER OF DEPOPULATED SOLDER BALLS. PACKAGE OUTLINE, 96 BALL FBGA 6.0X6.0X1.3 M M FDG096 REV** 002-13224 ** Document Number: 002-05635 Rev. *C Page 117 of 126 CY9A340NB Series 15. Errata This chapter describes the errata for CY9A340N, CY9A340NA and CY9A340MB series. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. 15.1 Part Numbers Affected Part Number Initial Revision CY9AF341NPMC-G-JNE2, CY9AF342NPMC-G-JNE2, CY9AF344NPMC-G-JNE2, CY9AF341NPQC-G-JNE2, CY9AF342NPQC-G-JNE2, CY9AF344NPQC-G-JNE2, CY9AF341NBGL-GE1, CY9AF342NBGL-GE1, CY9AF344NBGL-GE1, CY9AF341MPMC-G-JNE2, CY9AF342MPMC-G-JNE2, CY9AF344MPMC-G-JNE2, CY9AF341MPMC1-G-JNE2, CY9AF342MPMC1-G-JNE2, CY9AF344MPMC1-G-JNE2, CY9AF341MBGL-GE1, CY9AF342MBGL-GE1, CY9AF344MBGL-GE1, CY9AF341LPMC1-G-JNE2, CY9AF342LPMC1-G-JNE2, CY9AF344LPMC1-G-JNE2, CY9AF341LPMC-G-JNE2, CY9AF342LPMC-G-JNE2, CY9AF344LPMC-G-JNE2, CY9AF341LQN-G-AVE2, CY9AF342LQN-G-AVE2, CY9AF344LQN-G-AVE2 Rev. A CY9AF341NAPMC-G-JNE2, CY9AF342NAPMC-G-JNE2, CY9AF344NAPMC-G-JNE2, CY9AF341NAPQC-G-JNE2, CY9AF342NAPQC-G-JNE2, CY9AF344NAPQC-G-JNE2, CY9AF341NABGL-GE1, CY9AF342NABGL-GE1, CY9AF344NABGL-GE1, CY9AF341MAPMC-G-JNE2, CY9AF342MAPMC-G-JNE2, CY9AF344MAPMC-G-JNE2, CY9AF341MAPMC1-G-JNE2, CY9AF342MAPMC1-G-JNE2, CY9AF344MAPMC1-G-JNE2, CY9AF341MABGL-GE1, CY9AF342MABGL-GE1, CY9AF344MABGL-GE1, CY9AF341LAPMC1-G-JNE2, CY9AF342LAPMC1-G-JNE2, CY9AF344LAPMC1-G-JNE2, CY9AF341LAPMC-G-JNE2, CY9AF342LAPMC-G-JNE2, CY9AF344LAPMC-G-JNE2, CY9AF341LAQN-G-AVE2, CY9AF342LAQN-G-AVE2, CY9AF344LAQN-G-AVE2 Rev. B CY9AF341NBPMC-G-JNE2, CY9AF342NBPMC-G-JNE2, CY9AF344NBPMC-G-JNE2, CY9AF341NBPQC-G-JNE2, CY9AF342NBPQC-G-JNE2, CY9AF344NBPQC-G-JNE2, CY9AF341NBBGL-GE1, CY9AF342NBBGL-GE1, CY9AF344NBBGL-GE1, CY9AF341MBPMC-G-JNE2, CY9AF342MBPMC-G-JNE2, CY9AF344MBPMC-G-JNE2, CY9AF341MBPMC1-G-JNE2, CY9AF342MBPMC1-G-JNE2, CY9AF344MBPMC1-G-JNE2, CY9AF341MBBGL-GE1, CY9AF342MBBGL-GE1, CY9AF344MBBGL-GE1, CY9AF341LBPMC1-G-JNE2, CY9AF342LBPMC1-G-JNE2, CY9AF344LBPMC1-G-JNE2, CY9AF341LBPMC-G-JNE2, CY9AF342LBPMC-G-JNE2, CY9AF344LBPMC-G-JNE2, CY9AF341LBQN-G-AVE2, CY9AF342LBQN-G-AVE2, CY9AF344LBQN-G-AVE2 15.2 Qualification Status Product Status: In Production - Qual. Document Number: 002-05635 Rev. *C Page 118 of 126 CY9A340NB Series 15.3 Errata Summary This table defines the errata applicability to available devices. Items [1] FLASH lower bank read during write [2] FLASH read during write & erase suspend [3] Regulator issue [4] HDMI-CEC arbitration lost issue [5] HDMI-CEC polling message issue Part Number Refer to 15.1 Refer to 15.1 Refer to 15.1 Refer to 15.1 Refer to 15.1 Silicon Revision Initial rev. Initial rev. Initial rev., Rev. A Initial rev., Rev. A Initial rev., Rev. A , Rev. B Fix Status Fixed in Rev. A Fixed in Rev. A Fixed in Rev. B Fixed in Rev. B Next silicon is not planned 1. FLASH lower bank read during write PROBLEM DEFINITION During writing (programming) to FLASH memory of an upper bank, FLASH memory of a lower bank could not be read at a specific timing in some operation combinations. PARAMETERS AFFECTED N/A TRIGGER CONDITION(S) This issue may happen when read data or fetch instruction from the FLASH memory lower bank (smaller sector), while a write (program) operation to the FLASH memory upper bank (larger sector) is in progress. SCOPE OF IMPACT Instructions could not be fetched (read) correctly from the lower bank, and then execution of the (corrupted) instructions may cause a hard fault or run-away. If an instruction in RAM reads a data from the lower bank while writing to the upper bank, an incorrect value might be read. WORKAROUND To rewrite the upper bank of FLASH memory, put the write instruction in RAM instead of the lower bank and execute it from the RAM. Do not access the lower bank until the write operation is completed (RDY=1). Especially to avoid a vector fetch from the lower bank of the FLASH memory by an interrupt occurred, the interrupt should be prohibited or the vector address should be set to RAM by the vector table offset register. FIX STATUS This issue was fixed in Rev. A. 2. FLASH Read during Write & Sector Erase Suspend PROBLEM DEFINITION When writing is executed during sector erase suspend, FLASH memory could not be read correctly at a specific timing. PARAMETERS AFFECTED N/A TRIGGER CONDITION(S) This issue may happen when read data or fetch instruction from the FLASH memory bank (higher or lower), while a write (program) operation is in progress to the opposite bank which has a sector erase suspended. The following flow could not be executed correctly. (a) Erase a sector of a bank (b) Suspend the sector erase operation (c) Write to a different sector of the bank (d) Execute an instruction or read data in the opposite bank SCOPE OF IMPACT Document Number: 002-05635 Rev. *C Page 119 of 126 CY9A340NB Series Instructions could not be fetched (read) correctly, and then execution of the (corrupted) instructions may cause a hard fault or run-away. If an instruction in RAM reads a data from the bank, an incorrect value might be read. WORKAROUND Do not execute the write operation to a different sector in the same bank at sector erase suspend. FIX STATUS This issue was fixed in Rev. A. 3. Regulator issue PROBLEM DEFINITION The regulator does not get initialized while internal power-up sequence. PARAMETERS AFFECTED N/A TRIGGER CONDITION(S) This issue rarely happens depending on states of internal circuits which the user cannot control. SCOPE OF IMPACT MCU does not start operation if this issue occurs. WORKAROUND This error cannot be avoided by any software. FIX STATUS This issue was fixed in Rev. B. 4. HDMI-CEC arbitration lost issue PROBLEM DEFINITION Large external load on CEC bus may cause arbitration lost. PARAMETERS AFFECTED N/A TRIGGER CONDITION(S) The arbitration lost detection mechanism samples outputting signals and determines that arbitration lost occurs if sampled signals do not match the outputting signals. The large external load on the CEC bus increases slew rate of the signals. The increased slew rate makes the mismatch between outputting signals and sampled signals and the mismatch misleads MCU that arbitration lost occurs. SCOPE OF IMPACT Once the arbitration lost is detected, the CEC aborts the transmission. Any transmission cannot be completed. WORKAROUND This error cannot be avoided by any software. Reduce the external load. FIX STATUS This issue was fixed in Rev. B. 5. HDMI-CEC polling message issue PROBLEM DEFINITION Error#1) While MCU sends a Polling Message, it always returns a NACK to a message coming to the MCU from another node. Error#2) MCU always waits for 7-bit signal free on CEC line before it drives the line even when the last line initiator was another node. PARAMETERS AFFECTED N/A TRIGGER CONDITION(S) This error always happens. SCOPE OF IMPACT MCU does not reply properly to another node. Document Number: 002-05635 Rev. *C Page 120 of 126 CY9A340NB Series WORKAROUND The software workaround is applied to Error #1. 1. Store 0x0 to SFREE register. 2. Monitor CEC line with GPIO and wait until 1 lasts for the signal free time. 3. Store frame data to TXDATA register and store 0x0F to RCADR1 or RCADR2 register. It sends a message after 3~4 clocks of 32.768 kHz clock when TXDATA is stored 0x0F. If the device receives a frame from another node within 2~3 clocks after storing TXDATA, the bus error occurs and if the device receives a frame from another node within 3~4 clocks after storing TXDATA, the arbitration lost occurs. In these cases: 4-A-1. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK 4-A-2. Return back to step 2 above If the device receives a frame from another node within 1~2 clocks after storing TXDATA, take these steps. 4-B-1. Monitor CEC line with GPIO after 50us from storing TXDATA 4-B-2. Set TXEN to 1 -> 0 -> 1 immediately when GPIO finds state low on the CEC line 4-B-3. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK 4-B-4. Return back to step 2 above For Error #2, there is no software workaround, but signal free time of fixed 7-bit does not violate HDMI-CEC specification. The specification says signal free time must be more than and equals to 5-bit. FIX STATUS The user uses the workaround to avoid the issue. The next silicon fixing the issue is not planned. Document Number: 002-05635 Rev. *C Page 121 of 126 CY9A340NB Series 16. Major Changes Spansion Publication Number: DS706-00039 Page Section Revision 2.0 FEATURE 2 · On-chip Memories · USB Interface 6 · Unique ID 7 PRODUCT LINEUP · Function 48 HANDLING DEVICES 53 MEMORY MAP · Memory Map (2) 58 PIN STATUS IN EACH CPU STATE · List of Pin Status ELECTRICAL CHARACTERISTICS 65 3.DC Characteristics (1) Current rating 4.AC Characteristics 68 (3) Built-in CR Oscillation Characteristics · Built-in high-speed CR 72, 73 (7) External Bus Timing · Separate Bus Access Asynchronous SRAM Mode 74 · Separate Bus Access Synchronous SRAM Mode 79, 81, 83, 85 88 (9) CSIO Timing (11) I2C Timing 5. 12-bit A/D Converter 91 · Electrical characteristics for the A/D converter (Preliminary value) 93 · Definition of 12-bit A/D Converter Terms 7. Low-Voltage Detection 98 Characteristics (1) Low-Voltage Detection Reset 99 (2) Interrupt of Low-Voltage Detection Revision 2.1 - - Revision 3.0 - - - - 2 FEATURES ·External Bus Interface 3 ·Multi-function Serial Interface Change Results Revised the descriptions of [Flash memory]. Revised the descriptions of [USB function]. Added the descriptions of "Unique ID". Added the descriptions. Revised the Pin status type of "I". Revised the descriptions of Power supply current. Added the "Flash memory write/erase current". Added the footnote. Revised the table and the footnote. Revised the table and the figure. Revised the title to "CSIO Timing". Revised the note. Revised the footnote. · Revised the parameter. · Revised the symbol. · Corrected the value. · Revised the parameter. · Revised the symbol. · Corrected "Conditions" and "Value" in the table. · Added the Item. · Added the footnote. Added the Item. Company name and layout design change Corrected the Series name. MB9A340NA Series MB9A340NB Series Corrected the Product name as follows. MB9AF344LB, MB9AF342LB, MB9AF341LB MB9AF344MB, MB9AF342MB, MB9AF341MB MB9AF344NB, MB9AF342NB, MB9AF341NB Added the Item. · Maximum area size : Up to 256 Mbytes Corrected the description of "I2C" Document Number: 002-05635 Rev. *C Page 122 of 126 CY9A340NB Series Page Section Change Results 7 51 52 63 64,65 PRODUCT LINEUP ·Function BLOCK DIAGRAM MEMORY MAP ·Memory Map (1) ELECTRICAL CHARACTERISTICS 2.Recommended Operating Conditions 3.DC Characteristics (1)Current rating (9)CSIO Timing ·Synchronous serial (SPI=1, SCINV=1) 86 (9) CSIO Timing · External clock(EXT=1): asynchronous only (12)I2C Timing 88 5.12-bit A/D Converter ·Electrical Characteristics for the A/D Converter 91 101 ORDERING INFORMATON Revision 4.0 2 Features USB Interface 53 Memory Map · Memory map(2) Electrical Characteristics 64 - 66 3. DC Characteristics (1) Current rating Electrical Characteristics 67 3. DC Characteristics (2) Pin Characteristics Electrical Characteristics 4. AC Characteristics 70 (4-1) Operating Conditions of Main and USB PLL (4-2) Operating Conditions of Main PLL Electrical Characteristics 71 4. AC Characteristics (6) Power-on Reset Timing Electrical Characteristics 80 - 87 4. AC Characteristics (9) CSIO/UART Timing Added the footnote Corrected the figure Corrected the address "External Device Area" Add the footnote ·Corrected the Condition ·Delete the minimum value ·Corrected the remarks ·Add the footnote Corrected the figure of "MS bit=1" Corrected the figure Corrected the description as follows. ·Typical mode Standard-mode ·High-speed mode Fast-mode ·Corrected the terminal name AN00 ~ AN23 ANxx ·Corrected the minimum value of "Sampling time" ·Corrected the max and min value of "State transition time to operation permission" ·Corrected the footnote Corrected the "Part number" Added the description of PLL for USB Added the summary of Flash memory sector and the note · Changed the table format · Added Main Timer mode current · Moved A/D Converter Current Added input leak current of CEC pin at power off. Added the figure of Main PLL connection and USB PLL connection · Added Time until releasing Power-on reset · Changed the figure of timing · Modified from UART Timing to CSIO/UART Timing · Changed from Internal shift clock operation to Master mode · Changed from External shift clock operation to Slave mode Document Number: 002-05635 Rev. *C Page 123 of 126 CY9A340NB Series Page Section Change Results 92 Electrical Characteristics 5. 12bit A/D Converter 102 105 106, 107 Electrical Characteristics 9. Return Time from Low-Power Consumption Mode Ordering Information · Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage · Added Conversion time at AVcc < 2.7V Added Return Time from Low-Power Consumption Mode Changed notation of part number NOTE: Please see "Document History" about later revised information. Document Number: 002-05635 Rev. *C Page 124 of 126 CY9A340NB Series Document History Document Title: CY9A340NB Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller Document Number: 002-05635 Revision ECN Orig. of Change Submission Date Description of Change ** - AKIH 06/10/2015 Migrated to Cypress and assigned document number 002-05635. No change to document contents. *A 5199288 AKIH 04/01/2016 Updated to Cypress template. *B 5534251 YSKA 07/26/2017 Updated "12.4.7 Power-On Reset Timing". Changed parameter from "Power Supply rise time(Tr)[ms]" to "Power ramp rate(dV/dt)[mV/s]" and added some comments (Page 71) Modified RTC description in "Features, Real-Time Clock(RTC)" as below Changed starting count value from 01 to 00. Deleted "second , or day of the week" in the Interrupt function (Page 3) Added Notes for JTAG (Page 39), Changed "J-TAG" to" JTAG" in "4 List of Pin Functions" (Page 29) Updated Package code and dimensions as follows (Page 8-15, 107-117) FPT-64P-M38 -> LQD064, FPT-64P-M39 -> LQG064, LCC-64P-M24 -> VNC064, FPT-80P-M37 -> LQH080, FPT-80P-M40 -> LQJ080, BGA-96P-M07 -> FDG096, FPT-100P-M23 -> LQI100, FPT-100P-M36 -> PQH100 BGA-112P-M04 -> LBC112 Added "15. Errata" (Page 118) Change the name from "USB Function" to "USB Device" (Page 1, 7, 38) Add "Analog reference voltage(AVRL)" in "12.2 Recommended Operating Conditions" and "12.6 12-bit A/D Converter"(Page 62, 93) Corrected the following statement Analog port input current Analog port input leak current in chapter 12.6. 12-bit A/D Converter (Page 93) Added the Baud rate spec in "12.5.10 CSIO/UART Timing"(Page 80, 82, 84, 86) *C 6574940 HUAL 05/16/2019 Updated Document Title to read as "CY9A340NB Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller". Replaced "MB9A340NB Series" with "CY9A340NB Series" in all instances across the document. Updated Ordering Information: Updated part numbers. Updated to new template. Completing Sunset Review. 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You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-05635 Rev. *C May 16, 2019 Page 126 of 126

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CY9A340NB Series 32-bit ARM Cortex -M3 FM3 Microcontroller

Datasheet

MB9A340NB DS706-00039, MB9A340NB, MB9AF341LB, MB9AF34MB, MB9AF341NB , MB9AF342LB, MB9AF342MB, MB9AF342NB, MB9AF344LB, MB9AF344MB, MB9AF344NB, 32-bit microcontroller, FM3

HUAL

when appropriate, and any changes will be set out on the ...