LTM4678 (Rev. A)

50A µModule Regulator, Digital Power System Management, Digitally Adjustable, I2C, 250A, power module, DC/DC, PMBus

Analog Devices, Inc.

LTM4678 (Rev. A) - Analog Devices

Oct 18, 2018 — n Wide Input Voltage Range: 4.5V to 16V n Output Voltage Range: 0.5V to 3.4V n ±0.5% Maximum DC Output Error Over Temperature.

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LTM4678
Dual 25A or Single 50A µModule Regulator with Digital Power System Management

FEATURES
nn Dual Digitally Adjustable Analog Loops with Digital Interface forControl and Monitoring
nn Wide Input Voltage Range: 4.5V to 16V nn Output Voltage Range: 0.5V to 3.4V nn ±0.5% Maximum DC Output Error Over Temperature nn ±3.5% Current Readback Accuracy, 20°C to 125°C nn Sub-Milliohm DCR Current Sensing nn Integrated Input Current Sense Amplifier nn 400kHz PMBus-Compliant I2C Serial Interface nn Supports Telemetry Polling Rates up to 125Hz
nn Integrated 16-Bit ADC
nn Constant Frequency Current Mode Control nn Parallel and Current Share Up to 250A nn 16mm × 16mm × 5.86mm CoP-BGA Package Readable Data nn Input and Output Voltages, Currents, and Temperatures nn Running Peak Values, Uptime, Faults and Warnings nn Onboard EEPROM Fault Log Record Writable Data and Configurable Parameters nn Output Voltage, Voltage Sequencing and Margining nn Digital Soft-Start/Stop Ramp, Program Analog Loop nn OV/UV/OT, UVLO, Frequency and Phasing
APPLICATIONS
nn System Optimization, Characterization and Data Mining in Prototype, Production and Field Environments

DESCRIPTION
The LTM®4678 is a dual 25A or single 50A step-down µModule® (power module) DC/DC regulator featuring remote configurability and telemetry-monitoring of power management parameters over PMBus--an open standard I2C-based digital interface protocol . The LTM4678 is comprised of digitally programmable analog control loops, precision mixed-signal circuitry, EEPROM, power MOSFETs, inductors and supporting components.
The LTM4678's 2-wire serial interface allows outputs to be margined, tuned and ramped up and down at programmable slew rates with sequencing delay times. True input current sense, output currents and voltages, output power, temperatures, uptime and peak values are readable. Custom configuration of the EEPROM contents is not required. At start-up, output voltages, switching frequency, and channel phase angle assignments can be set by pin-strapping resistors. The LTpowerPlay® GUI and DC1613 USB-to-PMBus converter and demo kits are available.
The LTM4678 is offered in a 16mm × 16mm × 5.86mm CoP-BGA package available with SnPb or RoHS compliant terminal finish.
All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 7420359, 8163643. Licensed under U.S. Patent 7000125 and other related patents worldwide.

TYPICAL APPLICATION

Dual 25A µModule Regulator with Digital Interface for Control and Monitoring*

Using PMBus and LTpowerPlay to Monitor Telemetry and Margin VOUT0/VOUT1 During Load Pattern Tests, 10Hz Polling Rate, 12VIN

(FROM

4.5V to 16V

IN+

VOUT0

4.5V TO 5.75V,
CONNECT
VIN, SVIN AND INTVCC

22µF ×5

RSENSE IN VIN1

VOSNS0+ VOSNS0

TOGETHER) ON/OFF CONTROL

VIN0 SVIN RUN1
RUN0 FAULT0

LTM4678

VOUT1 VOSNS1+
VOSNS1

FAULT INTERRUPTS

FAULT1

SCL

SYNCHRONIZATION TIME-BASE REGISTER WRITE PROTECTION

SYNC SHARE_CLK

SDA ALERT

SGND GND

VOUT0 ADJUSTABLE
UP TO 25A

Output Voltage Readback, VOUT Margined 7.5% Low

1.1

1.9

VOUT0 (V)

VOUT1 (V)

LOAD0 LOAD1

100µF ×8
VOUT1 ADJUSTABLE UP TO 25A
100µF ×8

I2C/SMBus I/F WITH PMBus COMMAND SET TO/FROM IPMI OR OTHER BOARD MANAGEMENT CONTROLLER

IOUT0 (A)

1.0

1.8

0.9

1.7

0.8 0

1.6

TIME (SEC)

4678 TA01b

Output Current Readback, Varying Load Pattern

IOUT1 (A)

*FOR COMPLETE CIRCUIT, SEE FIGURE 46

4678 TA01a

TIME (SEC)

4678 TA01c

CHANNEL 0 TEMP (°C)

IIN0 (A)

Input Current Readback

2.6

4.3

IIN1 (A)

1.0

1.6

0.5

0.8

TIME (SEC)

4678 TA01d

Power Stage Temperature Readback

CHANNEL 1 TEMP (°C)

TIME (SEC)

4678 TA01e

Rev. A

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LTM4678

TABLE OF CONTENTS
Features...................................................... 1 Applications................................................. 1 Typical Application ......................................... 1 Description.................................................. 1 Table of Contents........................................... 2 Absolute Maximum Ratings............................... 4 Order Information........................................... 4 Pin Configuration........................................... 4 Electrical Characteristics.................................. 5 Typical Performance Characteristics................... 12 Pin Functions............................................... 15 Simplified Block Diagram................................ 19 Decoupling Requirements................................ 19 Functional Diagram....................................... 20 Test Circuits................................................ 21 Operation................................................... 22 Power Module Introduction ......................................22 Power Module Overview, Major Features...................22 EEPROM with ECC ....................................................23 Power-Up and Initialization ....................................... 24 Soft-Start ..................................................................25 Time-Based Sequencing ...........................................25 Voltage-Based Sequencing .......................................25 Shutdown .................................................................26 Light-Load Current Operation ...................................26 Switching Frequency and Phase................................ 27 PWM Loop Compensation ........................................ 27 Output Voltage Sensing ............................................ 27 INTVCC/EXTVCC Power ............................................. 27 Output Current Sensing and Sub Milliohm DCR
Current Sensing ...................................................... 28 Input Current Sensing ............................................... 28 PolyPhase Load Sharing ........................................... 28 External/Internal Temperature Sense ........................29 RCONFIG (Resistor Configuration) Pins ....................29 VOUTn _CFG Pin Strapping Look-Up Table for the LTM4678's Output Voltage, Coarse Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b)................29 VTRIMn_CFG Pin Strapping Look-Up Table for the LTM4678's Output Voltage, Fine Adjustment Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b) .......30

FSWPH_CFG Pin Strapping Look-Up Table to Set the LTM4678's Switching Frequency and Channel Phase-Interleaving Angle (Not Applicable if MFR_CONFIG_ALL[6] = 1b) ................................... 31 ASEL Pin Strapping Look-Up Table to Set the LTM4678's Slave Address (Applicable Regardless of MFR_CONFIG_ALL[6] Setting) ........................... 32 LTM4678 MFR_ADDRESS Command Examples Expressed in 7- and 8-Bit Addressing ..................... 32 Fault Detection and Handling .................................... 32 Status Registers and ALERT Masking .....................33 Mapping Faults to FAULT Pins ................................35 Power Good Pins ....................................................35 CRC Protection .......................................................35 Serial Interface ..........................................................35 Communication Protection .....................................35 Device Addressing ....................................................35 Responses to VOUT and IIN/IOUT Faults .....................36 Output Overvoltage Fault Response ........................36 Output Undervoltage Response .............................. 37 Peak Output Overcurrent Fault Response ............... 37 Responses to Timing Faults ...................................... 37 Responses to VIN OV Faults ...................................... 37 Responses to OT/UT Faults ....................................... 37 Internal Overtemperature Fault Response ............... 37 External Overtemperature and Undertemperature Fault Response .....................................................38 Responses to Input Overcurrent and Output Undercurrent Faults ................................................38 Responses to External Faults ....................................38 Fault Logging ............................................................38 Bus Timeout Protection ............................................38 Similarity Between PMBus, SMBus and I2C 2-Wire Interface ...................................................... 39 PMBus Serial Digital Interface .................................. 39 Abbreviations of Supported Data Formats ................40 Figure 7 to Figure 24 PMBus Protocols................... 41 PMBus Command Summary............................. 44 PMBus Commands ...................................................44 PMBus Commands Summary (Note: The Data Format Abbreviations are Detailed in Table 8) .........44 Data Format Abbreviations ....................................... 49

Rev. A

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LTM4678

TABLE OF CONTENTS

Applications Information................................. 50 VIN to VOUT Step-Down Ratios ..................................50 Input Capacitors .......................................................50 Output Capacitors .....................................................50 Light Load Current Operation....................................50 Switching Frequency and Phase ............................... 51 Recommended Switching Frequency for Various VIN-to-VOUT Step-Down Scenarios ......................... 52 Output Current Limit Programming .......................... 52 Minimum On-Time Considerations ............................53 Variable Delay Time, Soft-Start and Output Voltage Ramping ....................................................53 Digital Servo Mode ...................................................53 Soft Off (Sequenced Off) ..........................................54 Undervoltage Lockout ...............................................55 Fault Detection and Handling ....................................55 Open-Drain Pins ........................................................55 Phase-Locked Loop and Frequency Synchronization ......................................................56 Input Current Sense Amplifier ................................... 57 Programmable Loop Compensation ......................... 57 Checking Transient Response ...................................58
PolyPhase Configuration ........................................ 59 Connecting The USB to I2C/SMBus/PMBus Controller to the LTM4678 In System ..................... 59 LTpowerPlay: An Interactive GUI for Digital Power.......... 60 PMBus Communication and Command Processing ...... 60 Thermal Considerations and Output Current Derating ... 62 Table 10 thru Table 11: Output Current Derating........65 0.9V Output.............................................................65 1.8V Output..............................................................65 Channel Output Voltage vs Component Selection, 0A to 12.5A/s Load Step Output CapacitorGRM32ER60G337ME05L, 330F, 4V, X5R, Murata..... 66 Channel Output Voltage vs Component Selection, 0A to 12.5A/s Load Step........................................ 67
Dual Phase Single Output Ceramic and Poscap
Output Capacitors.................................................. 67
Applications Information-Derating Curves............. 68 EMI Performance ......................................................69 Safety Considerations ...............................................69 Layout Checklist/Example .........................................69
Typical Applications....................................... 71
PMBus Command Details................................ 76 Addressing and Write Protect.................................... 76

General Configuration Commands............................. 78 On/Off/Margin............................................................ 79 PWM Configuration................................................... 81 Voltage....................................................................... 84 Input Voltage and Limits..........................................84 Output Voltage and Limits.......................................85 Output Current and Limits.........................................88 Input Current and Limits .........................................90 Temperature............................................................... 91 Power Stage DCR Temperature Calibration.............. 91 Timing........................................................................ 92 Timing--On Sequence/Ramp..................................92
Timing--Off Sequence/Ramp.................................93 Precondition for Restart..........................................94 Fault Response..........................................................94 Fault Responses All Faults.......................................94 Fault Responses Input Voltage................................95 Fault Responses Output Voltage..............................95 VOUT_OV_FAULT_RESPONSE Data Byte Contents..... 96 VOUT_UV_FAULT_RESPONSE Data Byte Contents......97 Fault Responses Output Current..............................98 OUT_OC_FAULT_RESPONSE Data Byte Contents......99 Fault Responses IC Temperature.............................99 Data Byte Contents MFR_OT_FAULT_RESPONSE......100 Fault Responses External Temperature.................. 100 Fault Sharing............................................................ 101 Fault Sharing Propagation..................................... 101 FAULTn Propagate Fault Configuration..................... 102 Fault Sharing Response......................................... 103 Scratchpad............................................................... 103 Identification............................................................ 104 Fault Warning and Status......................................... 105 Telemetry..................................................................111 NVM Memory Commands....................................... 115 Store/Restore........................................................ 115 Fault Logging......................................................... 116 Fault Logging........................................................... 117 Explanation of Position_Fault Values....................... 119 Block Memory Write/Read..................................... 120 Package Description.................................... 121 LTM4678 BGA Pinout.............................................. 121 Revision History......................................... 123 Package Photograph.................................... 124 Design Resources....................................... 124 Related Parts............................................. 124

Rev. A

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LTM4678

ABSOLUTE MAXIMUM RATINGS

(Note 1)

Terminal Voltages: VINn (Note 4), SVIN, IIN+, IIN-....................... 0.3V to 18V (SVIN IIN+), (IIN+ IIN-)............................ 0.3V to 0.3V SW0, SW1................... -1V to 18V, -5V to 18V Transient

VVOOUSNTnS,0I+N, TVVOSCNC,S1E+X...T..V..C..C.................................................................

0.3V 0.3V

to to

6V 6V

VOSNS0-, VOSNS1-....................................... 0.3V to 0.3V

RUNn, SDA, SCL, ALERT............................ 0.3V to 5.5V

FSWPH_CFG, VOUT0,1_CFG,

VTRIM0,1_CFG, ASEL.......................... 0.3V to 2.75V

FAULTn, SYNC, SHARE_CLK, WP,

PGOOD0, PGOOD1................................ -0.3V to 3.6V

COMPna, COMPnb, ................................... 0.3V to 2.7V

TSNS0a, TSNS1a....................................... 0.3V to 2.2V

TSNS0b, TSNS1b....................................... 0.3V to 0.8V

Temperatures Internal Operating Temperature Range (Notes 2, 13, 17, 18)................................ 40°C to 125°C Storage Temperature Range................... 55°C to 125°C Peak Solder Reflow Package Body Temperature.... 245°C (Not Recommended for Upside Down Reflow)

PIN CONFIGURATION

A SW1
B

SVIN

GND

E
VIN1 F

G
H IIN+
J IIN
K

VIN0 GND

L SW0
M

TOP VIEW
GND

VOSNS1+ VOSNS1 VOUT1

VOUT1

COMP1b

VTRIM0_ CFG

SHARE_ TSNS1b PGOOD1 COMP1a CLK

VDD25

GND

INTVCC

VDD33

FSWPH_ VTRIM1_ VOUT0_ VOUT1_

CFG CFG

EXTVCC

RUN1 ASEL

GND

SGND

FAULT1 RUN0

COMP0b SDA ALERT FAULT0

PGOOD0 TSNS0b COMP0a TSNS1a TSNS0a SCL

GND

VOUT0

SYNC

VOSNS0+ VOSNS0

BGA PACKAGE 144-LEAD (16mm × 16mm × 5.86mm) TJMAX = 125°C, JCtop = 2.5°C/W, JCbottom = 2°C/W, BA = 7°C/W, JA = 9°C/W VALUES DETERMINED PER DEMOBOARD
WEIGHT = 3.2 GRAMS

ORDER INFORMATION

PART NUMBER LTM4678EY#PBF LTM4678IY#PBF LTM4678IY

PAD OR BALL FINISH SAC305 (RoHS) SnPb (63/37)

PART MARKING*

DEVICE

FINISH CODE

LTM4678Y e1
LTM4678Y

LTM4678Y

PACKAGE TYPE
BGA

MSL RATING

TEMPERATURE RANGE (See Note 2)

40°C to 125°C

Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container. Pad or ball finish code is per IPC/JEDEC J-STD-609.

Rev. A

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LTM4678

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). n is specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V, EXTVCC = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

VINn, SVIN VOUTn
VOUTn(DC)

Input DC Voltage

Test Circuit 1 Test Circuit 2; VIN_OFF < VIN_ON = 4V

l 5.75 l 4.5

Range of Output Voltage Regulation

VOUT0 VOUT1

Differentially Differentially

Sensed Sensed

on on

VVOOSSNNSS10++//VVOOSSNNSS01

Pin-Pair; Pin-Pair;

l 0.5 l 0.5

Commanded by Serial Bus or with Resistors Present at Start-

Up on VOUTn_CFG (Note 19)

Output Voltage, Total Variation with Line and Load

(Note 5)
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b) Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b) VOUTn Commanded to 1.000V, VOUTn Low Range (MFR_PWM_MODEn[1] = 1b)

0.995 l 0.985

VUVLO

Undervoltage Lockout Threshold, When VIN < 4.3V

Input Specifications

VINTVCC Falling VINTVCC Rising

IINRUSH(VIN) IQ(SVIN)

Input Inrush Current at Start-Up
Input Supply Bias Current

Test Circuit 1, VOUTn =1V, VIN = 12V; No Load Besides Capacitors; TON_RISEn = 3ms
Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b RUNn = 3.3V Shutdown, RUN0 = RUN1 = 0V (Note 16)

IS(VINn,PSM) IS(VINn,FCM)

Input Supply Current in PulseSkipping Mode Operation
Input Supply Current in ForcedContinuous Mode Operation

Output Specifications

Pulse-Skipping Mode, MFR_PWM_MODEn[0] = 0b, IOUTn = 100mA
Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b IOUTn = 100mA IOUTn = 25A

IOUTn
VOUTn(LINE) VOUTn

Output Continuous Current Range Line Regulation Accuracy

(Note 6) Utilizing MFR_PWM_MODE[7] = 1 and Using ~IOUT = 36A for IOUT_OC_FAULT_LIMIT, Page 89
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b) Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b) SVIN and VINn Electrically Shorted Together and INTVCC Open Circuit; IOUTn = 0A, 5.75V VIN 16V, VOUT Low Range (MFR_PWM_MODEn[1] = 1b), FREQUENCY_SWITCH = 350kHz (Note 5)

0 l

VOUTn(LOAD) Load Regulation Accuracy VOUTn

Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)

Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)

0A IOUTn 25A, VOUT Low Range, (MFR_PWM_MODEn[1] = 1b) (Note 5)

VOUTn(AC) fS (Each Channel)

Output Voltage Ripple VOUTn Ripple Frequency

FREQUENCY_SWITCH Set to 350kHz (0xFABC)

l 325

VOUTn(START) Turn-On Overshoot

tSTART

Turn-On Start-Up Time

TON_RISEn = 3ms (Note 12)

Time from VIN Toggling from 0V to 12V to Rising Edge

PGOODn. TON_DELAYn = 0ms, TON_RISEn = 3ms

tDELAY(0ms) VOUTn (LS)

Turn-On Delay Time
Peak Output Voltage Deviation for Dynamic Load Step

Time from First Rising Edge of RUNn to Rising Edge of PGOODn . TON_DELAYn = 0ms, TON_RISEn = 3ms, VIN Having Been Established for at Least 70ms
Load: 0A to 12.5A and 12.5A to 0A at 12.5A/µs, VOUTn = 1V, VIN = 12V (Note 12) See Load Transient Graphs

l 2.95

TYP
1.000 1.000
3.55 3.90 400
25 23 20
50 2.4
0.03 0.03
0.03 0.2
10 350 8 30 3.3
50

MAX 16 5.75 3.4 3.4 1.005 1.015
25 ±0.2
0.5 375
3.7

UNITS V V V V
V V
V V
mA
mA mA mA
mA A
A %/V %/V
% %
mVP-P kHz mV ms ms
mV

Rev. A

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LTM4678

SYMBOL

PARAMETER

CONDITIONS

MIN TYP MAX UNITS

tSETTLE

Settling Time for Dynamic Load Step

Load: 0A to 12.5A and 12.5A to 0A at 12.5A/µs, VOUTn = 1V, VIN = 12V (Note 12) See Load Transient Graphs

IOUTn(OCL_AVG) Output Current Limit, Time Averaged

Time-Averaged Output Inductor Current Limit Inception Threshold, Commanded by IOUT_OC_FAULT_LIMITn (Note 12) Utilizing MFR_PWM_MODE[7] = 1, Using ~IOUT = 36A, Page 89

Control Section

VFBCM0 VFBCM1

Channel 0 Feedback Input Common Mode Range

VVOOSSNNSS00+

Valid Valid

Input Input

Range Range

(Referred (Referred

to to

SGND) SGND)

Channel 1 Feedback Input Common Mode Range

VVOOSSNNSS11+

Valid Valid

Input Input

Range Range

(Referred (Referred

to to

SGND) SGND)

VOUT-RNGL

Full-Scale Command Voltage, Range Low (0.5V to 2.75V)
Set Point Accuracy Resolution LSB Step Size

VOUTn Commanded to 2.75V, MFR_PWM_MODEn[1] = 1b (Note 15)

µs

30A; See IO-RB-ACC Specification (Output Current
Readback Accuracy)

l 0.1 l

0.3

3.6

l 0.1 l

0.3

3.6

2.75

-0.5

-0.5 Bits

0.688

VOUT-RNGH
RVSNS0+ RVSNS1+ tON(MIN) RCOMP0,1
gm0,1

Full-Scale Command Voltage, Range High (0.5V to 3.6V)
Set Point Accuracy Resolution LSB Step Size
VOSNS0+ Impedance to SGND
VOSNS1 Impedance to SGND
Minimum On-Time
Resolution Compensation Resistor RTH(MAX) Compensation Resistor RTH(MIN)
Resolution Error Amplifier gm(MAX) Error Amplifier gm(MIN) LSB Step Size

VOUTn Commanded to 3.6V, MFR_PWM_MODEn[1] = 0b (Notes 7, 15)
0.05V VVOSNS0+ VSGND 3.3V 0.05V VVOSNS1 VSGND 3.3V (Note 8 ) MFR_PWM_CONFIG[4:0] = 0 to 31 (See Figure 1, Note Section) (Note 15)
COMP0,1 = 1.35V, MFR_PWM_CONFIG[7:5] = 0 to 7 (Note 15)

3.6

-0.5

0.5

Bits

1.375

Bits

5.76

mmho

0.68

mmho

Analog OV/UV (Overvoltage/Undervoltage) Output Voltage Supervisor Comparators (VOUT_OV/UV_FAULT_LIMIT and VOUT_OV/UV_WARN_LIMIT Monitors)

NOV/UV_COMP Resolution, Output Voltage Supervisors

(Notes 14, 15)

Bits

VOV-RNG

Output OV Comparator Threshold Detection Range

(Notes 14, 15) High Range Scale, MFR_PWM_MODEn[1] = 0b Low Range Scale, MFR_PWM_MODEn[1] = 1b

3.6

0.5

2.7

VOUSTP

Output OV and UV Comparator

(Note 15)

Threshold Programming LSB Step

High Range Scale, MFR_PWM_MODEn[1] = 0b

Size

Low Range Scale, MFR_PWM_MODEn[1] = 1b

11.2

5.6

VOV-ACC-0,1 VUV-RNG

Output OV Comparator Threshold Accuracy Channel 0 and 1
Output UV Comparator Threshold Detection Range

(See Note 14)

1V 0.5V 2.0V

VVVVOVVSOONSSSNNnSS+nn++

VVVVOVVSOONSSSNNnSSnn2.371.VV6V,, MM, MFFRRFR___PPPWWWMMM___MMMOOODDDEEE[[11[1]]]===110bbb

l l l

(Note 15)

High Range Scale, MFR_PWM_MODEn[1] = 0b

Low Range Scale, MFR_PWM_MODEn[1] = 1b

0.5

±1.5

±40

±1.5

3.6

2.7

Rev. A

For more information www.analog.com

LTM4678

SYMBOL

PARAMETER

CONDITIONS

VUV-ACC tPROP-OV

Output UV Comparator Threshold Accuracy
Output OV Comparator Response Times

(See Note 14)

1V 0.5V 2.0V

VVVVOVVSOONSSSNNnSS+nn++

VVVVOVVSOONSSSNNnSSnn

2.7V, MFR_PWM_MODE[1] = 1V, MFR_PWM_MODE[1] = 3.6V, MFR_PWM_MODE[1]

1b 1b = 0b

l l l

Overdrive to 10% Above Programmed Threshold

tPROP-UV

Output UV Comparator Response Under Drive to 10% Below Programmed Threshold Times

Analog OV/UV SVIN Input Voltage Supervisor Comparators (Threshold Detectors for VIN_ON and VIN_OFF) NSVIN-OV/UV-COMP SVIN OV/UV Comparator Threshold- (Note 15)
Programming Resolution

SVIN-OU-RANGE SVIN OV/UV Comparator Threshold-

Programming Range

SVIN-OU-STP

SVIN OV/UV Comparator Threshold- (Note 15) Programming LSB Step Size

SVIN-OU-ACC SVIN OV/UV Comparator Threshold 4.5V SVIN 16V

Accuracy

tPROP-SVIN-HIGH-VIN SVIN OV/UV Comparator Response Test Circuit 1, and:

Time, High VIN Operating

VIN_ON = 9V; SVIN Driven from 8.775V to 9.225V

Configuration

VIN_OFF = 9V; SVIN Driven from 9.225V to 8.775V

tPROP-SVIN-LOW-VIN SVIN OV/UV Comparator Response Test Circuit 2, and:

Time, Low VIN Operating

VIN_ON = 4.5V; SVIN Driven from 4.225V to 4.725V

Configuration

VIN_OFF = 4.5V; SVIN Driven from 4.725V to 4.225V

Channels 0 and 1 Output Voltage Readback (READ_VOUTn)

NVO-RB

Output Voltage Readback Resolution and LSB Step Size

(Note 15)

VO-F/S

Output Voltage Full-Scale Digitizable Range

VRUNn = 0V (Note 15)

VO-RB-ACC

Output Voltage Readback Accuracy

Channel Channel

0, 0,

1: 1:

1V 0.5V

VVVOVSONSSN+S+

VVVOVSONSSNS

3.6V < 1V

l l

tCONVERT-VO-RB Output Voltage Readback Update Rate

MFR_ADC_CONTROL = 0x00 (Notes 9, 15) MFR_ADC_CONTROL = 0x01 through 0x0C (Notes 9, 15) MFR_ADC_CONTROL Section

Input Voltage (SVIN) Readback (READ_VIN)

NSVIN-RB

Input Voltage Readback Resolution (Notes 10, 15) Limited to Abs Max = 18V for

and LSB Step Size

LTM4678 Module

SVIN-F/S

Input Voltage Full-Scale Digitizable (Notes 11, 15) Range

SVIN-RB-ACC Input Voltage Readback Accuracy READ_VIN, 4.5V SVIN 16V

tCONVERT-SVIN-RB Input Voltage Readback Update Rate

MFR_ADC_CONTROL = 0x00 (Notes 9, 15) MFR_ADC_CONTROL = 0x01 (Notes 9, 15)

Channels 0 and 1 Output Current (READ_IOUTn)

NIO-RB

Output Current Readback Resolution and LSB Step Size

(Notes 10, 12)

IO-F/S

Output Current Full-Scale Digitizable Range

(Note 12) Utilizing MFR_PWM_MODE[7] = 1, Using IOUT_OC_FAULT_ LIMIT = 34A, Page 89

MIN TYP MAX UNITS

±1.5

±40

±1.5

100

µs

100

µs

Bits

4.5

±350 mV

100

µs

100

µs

100

µs

100

µs

Bits

244

µV

Within ±0.5% of Reading Within ±5mV of Reading

Bits

15.625

Within ±2% of Reading

Bits

34.1

Rev. A

For more information www.analog.com

LTM4678

SYMBOL

PARAMETER

CONDITIONS

IO-RB-ACC

Output Current, Readback Accuracy READ_IOUTn, Channels 0 and 1, 0 IOUTn 25A, (Note 12), 20°C to 125°C Forced-Continuous Mode, MFR_PWM_MODEn[1:0] = 1b, 40°C to 125°C

IO-RB(25A)

Full Load Output Current Readback IOUTn = 25A (Note 12). See Histograms in Typical Performance Characteristics (Note 12)

tCONVERT-IO-RB Output Current Readback Update Rate

MFR_ADC_CONTROL = 0x00 (Notes 9, 15) MFR_ADC_CONTROL = 0x06 (CH0 IOUT) or 0x01 (CH1 IOUT) (Notes 9, 15) See MFR_ADC_CONTROL Section

Input Current Readback

N VIINSTP
IIN_TUE VOS tCONVERT

Resolution LSB Step Size Full-Scale Range = 16mV LSB Step Size Full-Scale Range = 32mV LSB Step Size Full-Scale Range = 64mV Total Unadjusted Error
Zero-Code Offset Voltage Update Rate

(Note 10)

Gain = 8, 0V |VIIN+ VIIN| 5mV

Gain Gain

= =

4, 2,

0V 0V

||VVIIIINN++

VVIIIINN||

20mV 50mV

(Note 15)

Gain Gain Gain

= = =

8, 4, 2,

2.5mV 4mV 6mV

||VV|IIVIINNI++IN+

VVIIVIINNIIN|| |

(Note 15)

(Notes 9,15) See MFR_ADC_CONTROL Section for Faster Update Rates

Supply Current Readback

Resolution

(Note 10)

VICHIPSTP

LSB Step Size Full-Scale Range = Onboard 1 Resistor (Note 15) 256mV

ICHIP-RB tCONVERT

ICHIP Readback Update Rate

SVIN Curent
(Notes 9,15) See MFR_ADC_CONTROL Section for Faster Update Rates

Temperature Readback (T0, T1)

TRES-RB T0_TUE

Temperature Readback Resolution
External Temperature Total Unadjusted Readback Error

Channel 0, Channel 1, and Controller (Note 15) Supporting Only VBE Sensing

T1_TUE tCONVERT

Internal TSNS TUE Update Rate

INTVCC Regulator/EXTVCC

VINTVCC

Internal VCC Voltage No Load

VLDO_INT

INTVCC Load Regulation

VEXTVCC

EXTVCC Switchover Voltage

VLDO_HYS

EXTVCC Hysteresis

VLDO_EXT

EXTVCC Voltage Drop

VRUN0,1 = 0.0, fSYNC = 0kHz (Note 15) (Note 9) MFR_ADC_CONTROL = 0x04 or 0x0C (Notes 9, 15)
6V VIN 16V ICC = 0mA to 20mA, 6V VIN 16V VIN 7V, EXTVCC Rising
ICC = 20mA, VEXTVCC = 5.5V

MIN TYP MAX UNITS Within ±0.875A of Reading
l Within ±1.50A of Reading

Bits

15.26

µV

30.52

µV

±2

±1.3

±1.2

±50

µV

Bits

244

µV

±50

0.25

°C

±5

°C

±1

°C

l 5.25 5.5 5.75

0.5 ±2

l 4.5 4.7 4.95

290

80 120

Rev. A

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LTM4678

SYMBOL

PARAMETER

VIN_THR

VIN Threshold to Enable EXTVCC Switchover

VIN_THF

VIN Hysteresis to Disable EXTVCC Switchover

VDD33 Regulator

VVDD33

Internal VDD33 Voltage

ILIM

VDD33 Current Limit

VVDD33_OV

VDD33 Overvoltage Threshold

VVDD33_UV

VDD33 Undervoltage Threshold

VDD25 Regulator

VVDD25

Internal VDD25 Voltage

ILIM

VDD25 Current Limit

Oscillator and Phase-Locked Loop (PLL)

fRANGE fOSC VTH(SYNC)

PLL SYNC Range Oscillator Frequency Accuracy SYNC Input Threshold

VOL(SYNC) ILEAK(SYNC)
SYNC-0

SYNC Low Output Voltage
SYNC Leakage Current in Slave Mode
SYNC to Ch0 Phase Relationship Based on the Falling Edge of Sync and Rising Edge of TG0 (Note 15)

SYNC-1

SYNC to Ch1 Phase Relationship Based on the Falling Edge of Sync and Rising Edge of TG1 (Note 15)

EEPROM Characteristics

Endurance (Notes 13 and 17)

Retention

(Notes 13 and 17)

Mass_Write Mass Write Operation Time (Notes 13 and 17)

Leakage Current SDA, SCL, ALERT, RUN

IOL

Input Leakage Current

Leakage Current FAULTn, PGOODn

IGL

Input Leakage Current

Digital Inputs SCL, SDA, RUNn, GPI0n (Note 15)

VIH VIL VHYST CPIN

Input High Threshold Voltage Input Low Threshold Voltage Input Hysteresis Input Capacitance

CONDITIONS VIN Rising
VIN Falling
4.5V < VINTVCC or 4.8V < VEXTVCC VDD33 = GND (Note 15) (Note 15)
VDD25 = GND
Synchronized with Falling Edge of SYNC Frequency Switch = 350.0kHz to 1000.0kHz (Note 15) VSYNC Falling VSYNC Rising (Note 15) ILOAD = 3mA 0V VPIN 3.6V
MFR_PWM_CONFIG[2:0] = 0,2,3 MFR_PWM_CONFIG[2:0] = 5 MFR_PWM_CONFIG[2:0] = 1 MFR_PWM_CONFIG[2:0]= 4,6 MFR_PWM_CONFIG[2:0] = 3 MFR_PWM_CONFIG[2:0] = 0 MFR_PWM_CONFIG[2:0] = 2,4,5 MFR_PWM_CONFIG[2:0] = 1 MFR_PWM_CONFIG[2:0] = 6
0°C TJ 85°C During EEPROM Write Operations TJ < 125°C STORE_USER_ALL, 0°C < TJ < 85°C During EEPROM Write Operation
OV VPIN 5.5V
OV VPIN 3.6V
SCL, SDA

MIN TYP MAX UNITS

7.5

600

3.2 3.3 3.4

100

3.5

3.1

2.5

l 300

1000 kHz

±7.5

1.5

0.2 0.4

±5

µA

Deg

120

Deg

120

Deg

180

Deg

240

Deg

270

Deg

300

Deg

l 10,000 l 10
440

Cycles

Years

4100

±5

µA

±2

µA

1.35

l 0.8

0.08

Rev. A

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LTM4678

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). n is specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V, EXTVCC = 0, FREQUENCY_SWITCH = 575kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

Digital Input WP (Note 15)

IPUWP

Input Pull-Up Current

Open-Drain Outputs SCL, SDA, FAULTn, ALERT, RUNn, SHARE_CLK, PGOODn (Note 15)

VOL

Output Low Voltage

Digital Inputs SHARE_CLK, WP (Note 15)

ISINK = 3mA

VIH

Input High Threshold Voltage

VIL

Input Low Threshold Voltage

Digital Filtering of FAULTn (Note 15)

IFLTG

Input Digital Filtering FAULTn

Digital Filtering of PGOODn (Note 15)

IFLTG

Output Digital Filtering PGOODn

Digital Filtering of RUNn (Note 15)

IFLTG

Input Digital Filtering RUN

PMBus Interface Timing Characteristics (Note 15)

fSCL

Serial Bus Operating Frequency

tBUF

Bus Free Time Between Stop and

Start

tHD(STA)

Hold Time After Repeated Start Condition After This Period, the First Clock is Generated

tSU(STA)

Repeated Start Condition Setup Time

tSU(ST0) tHD(DAT)

Stop Condition Setup Time
Date Hold Time Receiving Data Transmitting Data

tSU(DAT)

Data Setup Time Receiving Data

tTIMEOUT_SMB Stuck PMBus Timer Non-Block Reads Measured from the Last PMBus Start Event Stuck PMBus Timer Block Reads

tLOW

Serial Clock Low Period

tHIGH

Serial Clock High Period

MIN TYP MAX UNITS

µA

0.4

1.5 1.8

l 0.6 1

µs

l 10 l 1.3
l 0.6

400

kHz

µs

l 0.6

10000

µs

l 0.6

µs

l 0 l 0.3

µs

0.9

µs

0.1

µs

255

l 1.3

10000

µs

l 0.6

µs

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
Note 2: The LTM4678 is tested under pulsed-load conditions such that TJ TA. The LTM4678E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the 40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4678I is guaranteed to meet specifications over the full 40°C to 125°C internal operating temperature range. TJ is calculated from

the ambient temperature TA and the power dissipation PD according the formula:
TJ = TA + (PD · JA)
Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified

Rev. A

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LTM4678

ELECTRICAL CHARACTERISTICS

Note 4: The two power inputs--VIN0 and VIN1--and their respective power outputs--VOUT0 and VOUT1--are tested independently in production. A shorthand notation is used in this document that allows these parameters to be referred to by "VINn" and "VOUTn", where n is permitted to take on a value of 0 or 1. This italicized, subscripted "n " notation and convention is extended to encompass all such pin names, as well as register names with channel-specific, i.e., paged data. For example, VOUT_COMMANDn refers to the VOUT_COMMAND command code data located in Pages 0 and 1, which in turn relate to channel 0 (VOUT0) and channel 1 (VOUT1). Registers containing non-page-specific data, i.e., whose data is "global" to the module or applies to both of the module's channels lack the italicized, subscripted "n ", e.g., FREQUENCY_SWITCH.
Note 5: VOUTn (DC) and line and load regulation tests are performed in production with digital servo disengaged (MFR_PWM_MODEn[6] = 0b) and low VOUTn range selected MFR_PWM_MODEn[1] = 1b. The digital servo control loop is exercised in production (setting MFR_PWM_ MODEn[6] = 1b), but convergence of the output voltage to its final settling value is not necessarily observed in final test--due to potentially long time constants involved--and is instead guaranteed by the output voltage readback accuracy specification. Evaluation in application demonstrates capability; see the Typical Performance Characteristics section.
Note 6: See output current derating curves for different VIN, VOUT, and TA, located in the Applications Information section.
Note 7: Even though VOUT0 and VOUT1 are specified for 6V absolute maximum, the maximum recommended command voltage to regulate output channels 0 and 1 is 3.6V with VOUT range-setting bit set using MFR_PWM_MODE[1] = 0b.
Note 8: Minimum on-time is tested at wafer sort.
Note 9: The data conversion is done by default in round robin fashion. All inputs signals are continuously converted for a typical latency of 90ms. Setting MFR_ADC_CONTRL value to be 0 to 12, LTM4678 can do fast data conversion with only 8ms to 10ms. See section PMBus Command for details.
Note 10: The following telemetry parameters are formatted in PMBusdefined "Linear Data Format", in which each register contains a word comprised of 5 most significant bits--representing a signed exponent, to be raised to the power of 2--and 11 least significant bits--representing a signed mantissa: input voltage (on SVIN), accessed via the READ_VIN command code; output currents (IOUTn), accessed via the READ_IOUTn command codes; module input current (IVIN0 + IVIN1 + ISVIN), accessed via the READ_IIN command code; channel input currents (IVINn + 1/2 · ISVIN), accessed via the MFR_READ_IINn command codes;and duty cycles of channel 0 and channel 1 switching power stages, accessed via the READ_DUTY_CYCLEn command codes. This data format limits the resolution of telemetry readback data to 10 bits even though the internal ADC is 16 bits and the LTM4678's internal calculations use 32-bit words.
Note 11: The absolute maximum rating for the SVIN pin is 18V. Input voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled down from the SVIN pin.
Note 12: These typical parameters are based on bench measurements and are not production tested. Improved output current readback can be achieved by evaluating the system using the LTM4678. Measurements of the ambient temperature and the module inductor temperature for each channel with airflow can be compared with the GUI readback temperature. Once this temperature difference is known, then MFR_TEMP_1_GAIN and

the MFR_TEMP_1_OFFSET parameters can be adjusted to further improve output current readback accuracy.
Note 13: EEPROM endurance and retention are guaranteed by wafer-level testing for data retention. The minimum retention specification applies for devices whose EEPROM has been cycled less than the minimum endurance specification, and whose EEPROM data was written to at 0°C TJ 85°C. The RESTORE_USER_ALL or MFR_RESET is valid over the entire operating temperature range and does not influence EEPROM characteristics.
Note 14: Channel 0 OV/UV comparator threshold accuracy for MFR_PWM_MODEn[1] = 1b tested in ATE at VVOSNS0+ VVOSNS0 = 0.5V and 3.6V. 1V condition tested at IC-Level, only. Channel 1 OV/UV comparator threshold accuracy for MFR_PWM_MODEn[1] = 1b tested in ATE with VVOSNS1+ VVOSNS1 = 0.5V and 3.6V. 1.5V condition tested at IC-level, only. MFR_PWM_MODEn[1] = 1b is the Low Range.
Note 15: Tested at IC-level ATE.
Note 16: The LTM4678 quiescent current (IQ) equals the IQ of VIN plus the IQ of INTVCC. Note 17: The LTM4678's EEPROM temperature range for valid write commands is 0°C to 85°C. To achieve guaranteed EEPROM data retention, execution of the "STORE_USER_ALL" command--i.e., uploading RAM contents to NVM--outside this temperature range is not recommended. However, as long as the LTM4678's EEPROM temperature is less than 130°C, the LTM4678 will obey the STORE_USER_ALL command. Only when EEPROM temperature exceeds 130°C, the LTM4678 will not act on any STORE_USER_ALL transactions: instead, the LTM4678 NACKs the serial command and asserts its relevant CML (communications, memory, logic) fault bits. EEPROM temperature can be queried prior to commanding STORE_USER_ALL; see the Applications Information section.
Note 18: The LTM4678 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
Note 19: The maximum programmable output voltage is 3.6V, therefore, any of the overvoltage margining commands will be limited as the output voltage is programmed up to 3.6V.

RTH(k)

0 0 5 10 15 20 25 30 35

CODE

4678 F01

Figure 1. Programmable RCOMP

Rev. A

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LTM4678 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C.

EFFICIENCY (%)

Single Output Efficiency, 5VIN, VIN = SVIN = EXTVCC = 5V CCM Mode
100

0.9V, 350kHz

1.0V, 350kHz

1.2V, 350kHz

1.5V, 500kHz

1.8V, 575kHz

2.5V, 575kHz

3.3V, 500kHz

LOAD CURRENT (A)

4678 G01

EFFICIENCY (%)

Single Output Efficiency, 8VIN, VIN = SVIN = 8V, EXTVCC = 5V, CCM Mode
100

0.9V, 350kHz

1.0V, 350kHz

1.2V, 350kHz

1.5V, 500kHz

1.8V, 575kHz

2.5V, 575kHz

3.3V, 750kHz

LOAD CURRENT (A)

4678 G02

EFFICIENCY (%)

Single Output Efficiency, VIN = SVIN = 12V, EXTVCC = 5V
100

0.9V, 350kHz

1.0V, 350kHz

1.2V, 350kHz

1.5V, 500kHz

1.8V, 575kHz

2.5V, 575kHz

3.3V, 750kHz

LOAD CURRENT (A)

4678 G03

EFFICIENCY (%)

Dual Phase Single Output Efficiency, 12VIN, VIN = SVIN = 12V, EXTVCC = 5V, VOUT0 and VOUT1 Paralleled CCM Mode
100

1.0V, 350kHz

1.5V, 500kHz

2.5V, 574kHz

3.3V, 750kHz

75 0 5 10 15 20 25 30 35 40 45 50

LOAD CURRENT (A)

4678 G04

Rev. A

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LTM4678

TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Single Channel Load Transient Response 50% to 100% Load Step, 12A/µs 12VIN to 0.9VOUT

Single Channel Load Transient Response 50% to 100% Load Step, 12A/µs 12VIN to 1.2VOUT

Single Channel Load Transient Response 50% to 100% Load Step, 12A/µs 12VIN to 1.5VOUT

OUTPUT TRANSIENT
50mV/DIV

LOAD STEP 5A/DIV

100µs/DIV

4678 G05

FIGURE 46 CIRCUIT, 12V TO 0.9V, FREQ = 350kHz

COUT = 470µF ×2 POSCAP, 100µF ×2 CERAMIC RCOMP = 11k, EA-GM = 3.69ms, COMPna = 1500pF, COMPnb = 150pF

LOW VOUT RANGE FOR VOUT 2.5V HIGH VOUT RANGE FOR 2.5V VOUT ILIMIT RANGE = HIGH

100µs/DIV

4678 G06

FIGURE 46 CIRCUIT, 12V TO 1.2V, FREQ = 350kHz

COUT = 470µF ×2 POSCAP, 100µF ×2 CERAMIC RCOMP = 7k, EA-GM = 3.62ms, COMPna = 1500pF, COMPnb = 150pF

LOW VOUT RANGE FOR VOUT 2.5V HIGH VOUT RANGE FOR 2.5V VOUT ILIMIT RANGE = HIGH

100µs/DIV

4678 G07

FIGURE 46 CIRCUIT, 12V TO 1.5V, FREQ = 500kHz

COUT = 470µF ×2 POSCAP, 100µF ×2 CERAMIC RCOMP = 7k, EA-GM = 3.62ms, COMPna = 1500pF, COMPnb = 150pF

LOW VOUT RANGE FOR VOUT 2.5V HIGH VOUT RANGE FOR 2.5V VOUT ILIMIT RANGE = HIGH

Single Channel Load Transient Response 50% to 100% Load Step, 12A/µs 12VIN to 1.8VOUT

Dual Output Concurrent Rail, Start-Up/Shut Down

Dual Output Concurrent Rail, Start-Up/Shut Down, Pre-Bias

50mV/DIV

VOUT1, 1.8V 500mV/DIV

LOAD STEP 5A/DIV

50µs/DIV

4678 G08

FIGURE 46 CIRCUIT, 12V TO 1.8V, FREQ = 575kHz

COUT = 470µF ×2 POSCAP, 100µF ×2 CERAMIC RCOMP = 11k, EA-GM = 1ms, COMPna = 1500pF, COMPnb = 150pF

VOUT0, 1V 500mV/DIV

IOUT0, 18A 5A/DIV

RUN0, RUN1

5V/DIV

2ms/DIV

4678 G09

FIGURE 46 CIRCUIT, 12VIN, 18A LOAD VOUT0,

NO LOAD VOUT1

TON_RISE0 = 3ms

TON_RISE1 = 5.297ms

TON_DELAY0 = 2.43ms TOFF_DELAY1 = 0ms

TON_FALL0 = 3ms

TON_FALL1 = 5.328ms

ON_OFF CONFIGN = 0X1F

VOUT0, 1V 500mV/DIV

IOUT0, 25A 10A/DIV

RUN0, RUN1

5V/DIV

2ms/DIV

4678 G10

FIGURE 46 CIRCUIT, 12VIN, 25A LOAD VOUT0, NO LOAD VOUT1, VOUT1 PRE-BIASED TO 500mV THROUGH A DIODE (PRE-BIAS DISCONNECTED

AT SHUT-DOWN)

TON_RISE0 = 3ms

TON_RISE1 = 5.297ms

TON_DELAY0 = 2.43ms TOFF_DELAY1 = 0ms

TON_FALL0 = 3ms

TON_FALL1 = 5.328ms

ON_OFF CONFIGn = 0X1F

Dual Output Concurrent Rail, Start-Up/Shut Down, Pre-Bias

Single Phase Single Output Short-Circuit Protection, No Load

Single Phase Single Output Short-Circuit Protection, 18A Load

VOUT1, 1.8V 500mV/DIV

VOUT0 500mV/DIV

VOUT0, 1V 500mV/DIV

IOUT0, 25A 10A/DIV

RUN0, RUN1

5V/DIV

2ms/DIV

4678 G11

FIGURE 46 CIRCUIT, 12VIN, 25A LOAD VOUT0, NO LOAD VOUT1, VOUT1 PRE-BIASED TO 500mV THROUGH A DIODE

(PRE-BIAS DISCONNECTED AT SHUT-DOWN)

TON_RISE0 = 3ms

TON_RISE0 = 5.297ms

TON_DELAY0 = 2.43ms TOFF_DELAY1 = 0ms

TON_FALL0 = 3ms

TON_FALL1 = 5.328ms

ON_OFF CONFIGn = 0X1F

IIN 2A/DIV

20µs/DIV

4678 G12

FIGURE 46 CIRCUIT, 12VIN, NO LOAD VOUT0, PRIOR TO APPLICATION OF SHORT-CIRCUIT

USE HIGH RANGE OF I LIMIT SYSTEM

SHORT-CIRCUIT USING 50N04-8M

MOSFET ACROSS OUTPUT

VOUT0 500mV/DIV

IIN 2A/DIV

20µs/DIV

4678 G13

FIGURE 46 CIRCUIT, 12VIN, 18A LOAD VOUT0, PRIOR TO APPLICATION OF SHORT-CIRCUIT

USE HIGH RANGE OF I LIMIT SYSTEM

SHORT-CIRCUIT USING 50N04-8M

MOSFET ACROSS OUTPUT

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Rev. A
13

LTM4678

TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, 12VIN to 1VOUT, unless otherwise noted.

INPUT CURRENT (A) INPUT CURRENT (A) INPUT CURRENT (A)

Supply Current vs Load Current Comparison, RSENSE = 4m, 12V to 1.0VOUT, 350kHz

5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
0 0

RSENSE GUI READ

10 20 30 40 50 60

LOAD CURRENT (A)

4678 G14

Supply Current vs Load Current Comparison, RSENSE = 4m, 12V to 1.5VOUT,500kHz

8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
0 0

RSENSE GUI

10 20 30 40 50 60

LOAD CURRENT (A)

4678 G15

Supply Current vs Load Current Comparison, RSENSE = 4m, 12V to 2.5VOUT, 575kHz
14

RSENSE

GUI

0 0 10 20 30 40 50 60

LOAD CURRENT (A)

4678 G16

READ_IOUT of 10 LTM4678 Channels 12VIN, 1VOUT, TJ = 40°C, IOUTn = 25A, System Having Reached Thermally Steady-State Condition, No Airflow
4

READ_IOUT of 10 LTM4678 Channels 12VIN, 1VOUT, TJ = 25°C, IOUTn = 25A, System Having Reached Thermally Steady-State Condition, No Airflow
4

READ_IOUT of 10 LTM4678 Channels 12VIN, 1VOUT, TJ = 125°C, IOUTn = 25A, System Having Reached Thermally Steady-State Condition, No Airflow
4

NUMBER OF CHANNELS NUMBER OF CHANNELS NUMBER OF CHANNELS

0 25.5 25.7 25.9 26.1 26.2 26.3 26.3 READ_IOUT CHANNEL READBACK (A)
4678 G17

0 25.3 25.4 25.5 25.8 25.8 25.9 READ_IOUT CHANNEL READBACK (A)
4678 G18

0 24.3 24.4 24.7 24.7 24.9 24.9 25.2 25.8 READ_IOUT CHANNEL READBACK (A)
4678 G19

Rev. A

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LTM4678

PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.
GND (A3-A6, B1, B3-B6, C1-C6, D2-D6, E5-E6, F5-F7, G5-G8, H5-H8, J2-J6, K2-6, L1, L3-L6, M3-M6): Power Ground of the LTM4678. Power return for VOUT0 and VOUT1. Return input and output capacitors to this point .
VOUT0 (K7-K11, L7-L12, M7-M10): Channel 0 Output Voltage. Place recommended output capacitors from this shape to GND. See recommended layout.
VOSNS0+ (M11): Channel 0 Positive Differential Voltage Sense Input. Together, VOSNS0+ and VOSNS0 serve to kelvin-sense the VOUT0 output voltage at VOUT0's point of load (POL) and provide the differential feedback signal directly to channel 0's feedback loop. Command VOUT0's target regulation voltage by serial bus. Its initial command value at SVIN power-up is dictated by NVM (non-volatile memory) contents (factory default: 1.000V)--or, optionally, may be set by configuration resistors; see VOUT0_CFG and the Applications Information section.
VOSNS0 (M12): Channel 0 Negative Differential Voltage Sense Input. See VOSNS0+.
VOUT1 (A7-A10, B7-B12, C7-C9, D7): Channel 1 Output Voltage. Place recommended output capacitors from this shape to GND See recommended layout.
VOSNS1+ (A11): Channel 1 Positive Differential Voltage Sense Input. Together, VOSNS1+ and VOSNS1 serve to kelvin-sense the VOUT1 output voltage at VOUT1's point of load (POL) and provide the differential feedback signal directly to channel 1's feedback loop. Command VOUT1's target regulation voltage by serial bus. Its initial command value at SVIN power-up is dictated by NVM (non-volatile memory) contents (factory default: 1.000V)--or, optionally, may be set by configuration resistors; see VOUT1_CFG and the Applications Information section.
VOSNS1 (A12): Channel 1 Negative Differential Voltage Sense Input. See VOSNS1+.

SGND (F9-10, G9-10): SGND is the signal ground return path of the LTM4678. SGND is not internally connected to GND. Connect SGND to GND local to the LTM4678. See recommended layout.
VIN0 (G1-G4, H1-H4): Positive Power Input to Channel 0 Switching Stage. Provide sufficient decoupling capacitance in the form of multilayer ceramic capacitors (MLCCs) and low ESR electrolytic (or equivalent) to handle reflected input current ripple from the step-down switching stage. MLCCs should be placed as close to the LTM4678 as physically possible. See Layout Recommendations in the Applications Information section.
VIN1 (E1-E4, F1-F4): Positive Power Input to Channel 1 Switching Stage. Provide sufficient decoupling capacitance in the form of MLCCs and low ESR electrolytic (or equivalent) to handle reflected input current ripple from the step-down switching stage. MLCCs should be placed as close to the LTM4678 as physically possible. See Layout Recommendations in the Applications Information section.
SW0 (L2, M1-M2): Switching Node of Channel 0 StepDown Converter Stage. Used for test purposes or EMIsnubbing. May be routed a short distance to a local test point to monitor switching action of channel 0, if desired, but do not route near any sensitive signals; otherwise, leave electrically isolated (open).
SW1 (A1-A2, B2): Switching Node of Channel 1 Step-Down Converter Stage. Used for test purposes or EMI-snubbing. May be routed a short distance to a local test point to monitor switching action of channel 1, if desired, but do not route near any sensitive signals; otherwise, leave open.
SVIN (D1): Input Supply for LTM4678's Internal Control IC. In most applications, SVIN connects to VIN0 and/or VIN1. SVIN can be operated from an auxiliary supply separate from VIN0/VIN1 for powering the VIN0/VIN1 from a lower supply like 3.3V. The SVIN pin has an onboard 1 and 1µF decoupling capacitor. The 1 resistor is used to measure the actual control chip current. See MFR_READ_ICHIP and MFR_ADC_CONTROL Section. When operating from 4.5V to 5.75V with no auxiliary bias supply, then the main input

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Rev. A
15

LTM4678

PIN FUNCTIONS
supply should connect to SVIN and INTVCC. See Test Circuit 2 for an example. In this configuration, the ICHIP current will not be relevant since INTVCC is connected to SVIN.
IIN+ (J1): Positive Current Sense Amplifier Input. If the input current sense amplifier is not used, this pin must be shorted to the IIN and SVIN pin. See Applications section for detail about the input current sensing.
IIN (K1): Negative Current Sense Amplifier Input. If the input current sense amplifier is not used, this pin must be shorted to the IIN+ and SVIN pin. See Applications section for detail about the input current sensing.
EXTVCC (F8): External Power Input to an Internal Switch Connected to INTVCC. This switch closes and supplies the IC power, bypassing the internal regulator whenever EXTVCC is higher than 4.7V and VIN is higher than 7V. EXTVCC also powers up VDD33 when EXTVCC is higher than 4.7V and INTVCC is lower than 3.8V. Do not exceed 6V on this pin. Decouple this pin to PGND with a minimum of 4.7µF low ESR tantalum or ceramic capacitor. If the EXTVCC pin is not used to power INTVCC, the EXTVCC pin must be tied to GND.
INTVCC (E7) : Internal Regulator, 5.5V Output. When operating the LTM4678 from 5.75V SVIN 16V, an LDO generates INTVCC from SVIN to bias internal control circuits and the MOSFET drivers of the LTM4678. An external 2.2µF ceramic decoupling is required. INTVCC is regulated regardless of the RUNn pin state. When operating the LTM4678 with 4.5V SVIN < 5.75V, INTVCC must be electrically shorted to SVIN.
VDD33 (E8): Internally Generated 3.3V Power Supply Output Pin. This pin should only be used to provide external current for the pull-up resistors required for FAULTn, SHARE_CLK, and SYNC, and may be used to provide external current for pull-up resistors on RUNn, SDA, SCL, ALERT and PGOODn. No external decoupling is required.
VDD25 (D12): Internally Generated 2.5V Power Supply Output Pin. Do not load this pin with external current; it is used strictly to bias internal logic and provides current for the

internal pull-up resistors connected to the configurationprogramming pins. No external decoupling is required.
ASEL (F12): Serial Bus Address Configuration Pin. On any given I2C/SMBus serial bus segment, every device must have its own unique slave address. If this pin is left open, the LTM4678 powers up to its default slave address of 0x4F (hexadecimal), i.e., 1001111b (industry-standard convention is used throughout this document: 7-bit slave addressing). The lower four bits of the LTM4678's slave address can be altered from this default value by connecting a resistor from this pin to SGND. Minimize capacitance-- especially when the pin is left open--to assure accurate detection of the pin state.
FSWPH_CFG (E9): Switching Frequency, Channel PhaseInterleaving Angle and Phase Relationship to SYNC Configuration Pin. If this pin is left open--or, if the LTM4678 is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] = 1b--then LTM4678's switching frequency (FREQUENCY_SWITCH) and channel phase relationships (with respect to the SYNC clock; MFR_PWM_CONFIG[2:0]) are dictated at SVIN power-up according to the LTM4678's NVM contents. Default factory values are: 350kHz operation; channel 0 at 0°; and channel 1 at 180°C (convention throughout this document: a phase angle of 0° means the channel's switch node rises coincident with the falling edge of the SYNC pulse). Connecting a resistor from this pin to SGND (and using the factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b) allows a convenient way to configure multiple LTM4678s with identical NVM contents for different switching frequencies of operation and phase interleaving angle settings of intra- and extra-module-paralleled channels--all, without GUI intervention or the need to "custom pre-program" module NVM contents. (See the Applications Information section.) Minimize capacitance--especially when the pin is left open--to assure accurate detection of the pin state.
VOUT0_CFG (E11): Output Voltage Select Pin for VOUT0, Coarse Setting. If the VOUT0_CFG and VTRIM0_CFG pins are both left open--or, if the LTM4678 is configured to ignore pin-strap (RCONFIG) resistors, i.e.,

Rev. A

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LTM4678

PIN FUNCTIONS
MFR_CONFIG_ALL[6] = 1b--then the LTM4678s target VOUT0 output voltage setting (VOUT_COMMAND0) and associated power-good and OV/UV warning and fault thresholds are dictated at SVIN power-up according to the LTM4678's NVM contents. A resistor connected from this pin to SGND--in combination with resistor pin settings on VTRIM0_CFG, and using the factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b--can be used to configure the LTM4678's channel 0 output to power-up to a VOUT_COMMAND value (and associated output voltage monitoring and protection/fault-detection thresholds) different from those of NVM contents. (See the Applications Information section.) Connecting resistor(s) from VOUT0_CFG to SGND and/or VTRIM0_CFG to SGND in this manner allows a convenient way to configure multiple LTM4678s with identical NVM contents for different output voltage settings all without GUI intervention or the need to "custom-preprogram" module NVM contents. Minimize capacitance especially when the pin is left open to assure accurate detection of the pin state. Note that use of RCONFIGs on VOUT0_CFG/VTRIM0_CFG can affect the VOUT0 range setting (MFR_PWM_MODE0[1]) and loop gain.
VTRIM1_CFG (E10): Output Voltage Select Pin for VOUT1, Fine Setting. Works in combination with VOUT1_CFG to affect the VOUT_COMMAND (and associated output voltage monitoring and protection/fault-detection thresholds) of channel 1, at SVIN power-up. (See VOUT1_CFG and the Applications Information section.) Minimize capacitance especially when the pin is left open to assure accurate detection of the pin state. Note that use of RCONFIGs on VOUT1_CFG/VTRIM1_CFG can affect the VOUT1 range setting (MFR_PWM_MODE1[1]) and loop gain.
VOUT1_CFG (E12): Output Voltage Select Pin for VOUT1, Coarse Setting. If the VOUT1_CFG and VTRIM1_CFG pins are both left open or, if the LTM4678 is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ ALL[6] = 1b then the LTM4678's target VOUT1 output voltage setting (VOUT_COMMAND1) and associated OV/UV warning and fault thresholds are dictated at SVIN power-up according to the LTM4678's NVM contents, in precisely the same fashion that the VOUT1_CFG and

VTRIM1_CFG pins affect the respective settings of VOUT1/ channel 1. (See VOUT1_CFG, VTRIM1_CFG and the Applications Information section.) Minimize capacitance-- especially when the pin is left open--to assure accurate detection of the pin state. Note that use of RCONFIGs on VOUT1_CFG/VTRIM1_CFG can affect the VOUT1 range setting (MFR_PWM_MODE1[1]) and loop gain.
VTRIM0_CFG (C12): Output Voltage Select Pin for VOUT0, Fine Setting. Works in combination with VOUT0_CFG to affect the VOUT_COMMAND (and associated output voltage monitoring and protection/fault-detection thresholds) of channel 0, at SVIN power-up. (See VOUT0_CFG and the Applications Information section.) Minimize capacitance-- especially when the pin is left open--to assure accurate detection of the pin state. Note that use of RCONFIGs on VOUT0_CFG/ VTRIM0_CFG can affect the VOUT0 range setting (MFR_PWM_MODE0[1]) and loop gain.
RUN0, RUN1 (G12, F11 Respectively): Enable Run Input for Channels 0 and 1, Respectively. Open-drain input and output. Logic high on these pins enables the respective outputs of the LTM4678. These open-drain output pins hold the pin low until the LTM4678 is out of reset and SVIN is detected to exceed VIN_ON. A pull-up resistor to 3.3V is required in the application. The LTM4678 pulls RUN0 and/or RUN1 low, as appropriate, when a global fault and/ or channel-specific fault occurs whose fault response is configured to latch off and cease regulation; issuing a CLEAR_FAULTS command via I2C or power-cycling SVIN is necessary to restart the module, in such cases. Do not pull RUN logic high with a low impedance source.
PGOOD0/PGOOD1 (J7/D9): Power Good Indicator Outputs. Open-drain logic output that is pulled to ground when the output exceeds the UV and OV regulation window. The output is deglitch by an internal 100µs filter. A pull-up resistor to 3.3V is required in the application.
FAULT0/FAULT1 (H12/G11): Digital Programmable FAULT Inputs and Outputs. Open-drain output. A pull-up resistor to 3.3V is required in the application.

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Rev. A
17

LTM4678

PIN FUNCTIONS
COMP0b/COMP1b (H9/C10): Current Control Threshold and Error Amplifier Compensation Nodes. Each associated channel's current comparator tripping threshold increases with its compensation voltage. Each channel has a 22pF to SGND.
COMP0a/COMP1a (J9/D10): Loop Compensation Nodes. The internal PWM loop compensation resistors RCOMPn of the LTM4678 can be adjusted using bit[4:0] of the MFR_PWM_COMP command. The transconductance of the LTM4678 PWM error amplifier can be adjusted using bit[7:5] of the MFR_PWM_COMP command. These two loop compensation parameters can be programmed when device is in operation. Refer to the Programmable Loop Compensation subsection in the Applications Information section for further details. See Figure 1.
SYNC (K12): External Clock Synchronization Input and Open-Drain Output Pin. If an external clock is present at this pin, the switching frequency will be synchronized to the external clock. If clock master mode is enabled, this pin will pull low at the switching frequency with a 500ns pulse to ground. A resistor pull-up to 3.3V is required in the application if the LTM4678 is the master.
SCL (J12): Serial Bus Clock Open-Drain Input (Can Be an Input and Output, if Clock Stretching is Enabled). A pull-up resistor to 3.3V is required in the application for digital communication to the SMBus master(s) that nominally drive this clock. The LTM4678 will never encounter scenarios where it would need to engage clock stretching unless SCL communication speeds exceed 100kHz--and even then, LTM4678 will not clock stretch unless clock stretching is enabled by means of setting MFR_CONFIG_ALL[1] = 1b. The factory-default NVM configuration setting has MFR_CONFIG_ALL[1] = 0b: clock stretching disabled. If communication on the bus at clock speeds above 100kHz is required, the user's SMBus master(s) needs to implement clock stretching support to assure solid serial bus communications, and only then should MFR_CONFIG_ALL[1] be set to 1b. When clock

stretching is enabled, SCL becomes a bidirectional, opendrain output pin on LTM4678.
SDA (H10): Serial Bus Data Open-Drain Input and Output. A pull-up resistor to 3.3V is required in the application.
ALERT (H11): Open-Drain Digital Output. A pull-up resistor to 3.3V is required in the application only if SMBALERT interrupt detection is implemented in one's SMBus system.
SHARE_CLK (D11): Share Clock, Bidirectional Open-Drain Clock Sharing Pin. Nominally 100kHz. Used for synchronizing the time base between multiple LTM4678s (and any other Analog Devices devices with a SHARE_ CLK pin)--to realize well-defined rail sequencing and rail tracking. Tie the SHARE_CLK pins of all such devices together; all devices with a SHARE_CLK pin will synchronize to the fastest clock. A pull-up resistor to 3.3V is only required when synchronizing the time base between devices.
TSNS0a, TSNS0b (J11 and J8, Respectively): Channel 0 Temperature Excitation/Measurement and Thermal Sensor Pins, Respectively. Connect TSNS0a to TSNS0b. This allows the LTM4678 to monitor the power stage temperature of channel 0.
TSNS1a, TSNS1b (J10 and D8, Respectively): Channel 1 Temperature Excitation/Measurement and Thermal Sensor Pins, Respectively. In most applications, connect TSNS1a to TSNS1b. This allows the LTM4678 to monitor the power stage temperature of channel 1. See the Applications section for information on how to use TSNS1a to monitor an external temperature sensor.
WP (C11): Write Protect Pin, Active High. An internal 10µA current source pulls this pin to VDD33. If WP is open circuit or logic high, only I2C writes to PAGE, OPERATION, CLEAR_FAULTS, MFR_CLEAR_PEAKS and MFR_EE_UNLOCK are supported. Additionally, Individual faults can be cleared by writing 1b's to bits of interest in registers prefixed with "STATUS". If WP is low, I2C writes are unrestricted.

Rev. A

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LTM4678

SIMPLIFIED BLOCK DIAGRAM

+
CIN1

RSENSE CIN2

IIN+

IIN

SVIN 1

2.2µF

VIN0

INTVCC

1µF

2.2µF

EXTVCC

VDD33

2.2µF

VIN1 1µF

1µF A = N

INPUT CURRENT/ICHIP (READ_IIN,

MFR_READ_IIN_PEAK TO ANALOG

SW0

READBACK)

SW1

VOUT1 ADJ TO 3.4V
UP TO 25A
COUT2

VOUT0 COUT1 GND

2.2µF

MT0 220nH
MB0

POWER CONTROL ANALOG SECTION

LOAD0

CLOAD0

CCOMPH CCOMPL

TSNS0b TSNS0a

0.01µF TSNS0

IOUT0 CURRENT SENSE

VOSNS0+

REMOTE SENSE

VOSNS0

COMP0b

PROG GM EA0

22pF COMP0a

PROG RCOMP

PGOOD0

5.5V-TOLERANT PULL-UP NOT SHOWN
3.3V-TOLERANT PULL-UP NOT SHOWN

SCL SDA ALERT WP

POWER CONTROL DIGITAL SECTION ROM

RUN0

RAM

RUN1

FAULT0

FAULT1 SHARE_CLK

DIE TEMP SENSE

TO ANALOG READBACK

TEMP MUX

ALL ANALOG READBACK SIGNALS
10:1 MUX

ADC

SPI SLAVE

SPI MASTER DIGITAL ENGINE
EEPROM

+
+

MT1

220nH MB1

VOUT1
2.2µF GND

0.01µF TSNS1

SGND

IOUT0 CURRENT SENSE

TSNS1b TSNS1a

+ EA1

VOSNS1+

X1 PROG GM

REMOTE SENSE VOSNS1 COMP1b

PROG RCOMP

22pF COMP1a

PGOOD1

SYNC

2.5V

VDD25

2.2µF

VOUT1 ADJ TO 3.4V
UP TO 25A

COUT3

COUT4

CLOAD1

LOAD1

CCOMPH
CCOMPL
3.3V TOLERANT PULL-UP NOT SHOWN

SYNC DRIVER 32MHz OSC

ASEL FSWPH_CFG VTRIM0_CFG
VTRIM01_CFG VOUT0_CFG VOUT1_CFG

CONFIG RESISTORS TO 2.5V SGND NOT SHOWN

4678 F02
Figure 2. Simplified LTM4678 Block Diagram

DECOUPLING REQUIREMENTS TA = 25°C. Using Figure 1 configuration.

SYMBOL PARAMETER

CONDITIONS

MIN

CINH COUTn

External High Frequency Input Capacitor Requirement (5.75V VIN 16V, VOUTn Commanded to 1.000V)
External High Frequency Output Capacitor Requirement (5.75V VIN 16V, VOUTn Commanded to 1.000V)

IOUT0 = 25A IOUT1 = 25A IOUT0 = 25A IOUT1 = 25A

TYP MAX
66 66
400 400

UNITS
µF µF
µF µF

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Rev. A
19

LTM4678 FUNCTIONAL DIAGRAM

+
CIN1

RSENSE

IIN+

IIN

CIN2

SVIN 1

VIN0 1µF

2.2µF

INTVCC

EXTVCC VDD33

VIN1

2.2µF

1µF

Figure 3. Functional LTM4678 Block Diagram
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A = N

1µF SVIN TELEMETRY: (MFR_READ_ICHIP,
READ_VIN, READ_VIN_PEAK)

INPUT CURRENT/ICHIP (READIIN, MFRREADIINPEAK TO ANALOG READBACK)

OPTIONAL SNUBBER

(MFR_PWM_MODE, MFR_PWM_CONFIG, SW0 FREQUENCY_SWITCH)

VOUT1 ADJ
TO 3.4V
UP TO
25A

RSNUB0 CSNUB0

COUT2

COUT1

(VOUT0 TELEMETRY: READ_VOUT0,
MFR_VOUT_PEAK,
READ_POUT0)

VOUT0 GND
TSNS0b TSNS0a

(IOUT0 TELEMETRY: READ_IOUT0, MFR_IOUT_PEAK)
2.2µF READ_TEMPERATURE1
CHANNEL 0 TEMP
0.01µF TSNS0

MT0 220nH
MB0
IOUT0 SENSE DCR SENSE Z
CCM CH0 I SIGNAL

VOSNS0+

LOAD0

CLOAD0

REMOTE SENSE VOSNS0

COMPb0

CCOMPH

CCOMPL

COMPa0 PGOOD0

22pF

X1 PROG GM
MFR_PWM_COMP EA0
PROG RCOMP

+
+

PWM1
PWM0 TEMP IOUT2 IOUT1 VOUT2 VOUT1
VIN ICHIP
IIN

(CURRENT MODE PWM CNTL LOOPS, POWER CONTROL ANALOG SECTION LINEAR REGULATORS, DACs, ADC,

(MFR_PWM_MODE, MFR_PWM_CONFIG,

FREQUENCY_SWITCH)

SW1

UV/OV MONITORS, VCO/PLL, MOSFET

DRIVERS AND POWER CNTL LOGIC)

MT1

(IOUT1 TELEMETRY: READ_IOUT1,

VBE SENSING

220nH

MFR_IOUT_PEAK)

VOUT1

2µA 32µA

MB1

READ_TEMPERATURE0

DIE TEMP SENSE

IOUT1 SENSE

READ_TEMPERATURE1 CHANNEL 1 TEMP

2.2µF GND

0.01µF TSNS1

SGND

TEMP MUX

DCR SENSE Z CCM CH1 I SIGNAL

TSNS1b TSNS1a VOSNS1+

10:1 MUX
SETPOINT, ADC UV, OV, ILIM
DACs

+ EA1

X1
PROG GM MFR_PWM_COMP

REMOTE SENSE VOSNS1 COMP1b

PROG RCOMP

22pF COMP1a

PGOOD1

POWER MANAGEMENT DIGITAL SECTION

SPI SLAVE

SYNC

5.5V-TOLERANT PULL-UP NOT SHOWN
3.3V-TOLERANT PULL-UP NOT SHOWN

SCL SDA ALERT WP

I2C-BASED SMBus INTERFACE WITH PMBus
COMMANDS (10kHZ TO 400kHz COMPATIBLE)

10µA RUN0

VDD33

RUN1

FAULT0 FAULT1

CHANNEL TIMING MANAGEMENT

SHARE_CLK

VDD33 COMPARE

UVLO

ROM PROGRAM

DIGITAL ENGINE, MAIN CONTROL

SPI MASTER SINC3

RAM

EEPROM

SYNC DRIVER

VDD33 2.5V

32MHz OSC

CONFIG DETECT

VDD25

14.3k ×6

2.2µF ASEL

FSWPH_CFG

VTRIM0_CFG

VTRIM1_CFG VOUT0_CFG VOUT1_CFG

OPTIONAL SNUBBER
RSNUB1 CSNUB1

COUT3

VOUT1 ADJ COUT4 TO 3.4V
UP TO
25A

(VOUT0 TELEMETRY: READ_VOUT0,
MFR_VOUT_PEAK,
READ_POUT1)

CLOAD1

LOAD1

CCOMPL

CCOMPH

3.3V TOLERANT PULL-UP NOT SHOWN

CONFIG RESISTORS TO SGND NOT SHOWN

4678 F03

Rev. A

LTM4678 TEST CIRCUITS
Test Circuit 1. LTM4678 ATE High VIN Operating Range Configuration, 5.75V VIN 16V
2.2µF

VDD33 VDD25 INTVCC EXTVCC PGOOD0 PGOOD1 TSNS0a TSNS0b TSNS1a TSNS1b

COMP1a COMP1b COMP0a COMP0b VTRIM1_CFG VTRIM0_CFG VOUT0_CFG VOUT1_CFG FSWPH_CFG ASEL

VIN 150µF

5.75V TO 16V

IIN+

RSENSE

IIN

22µF

×5

VIN1

VIN0 SVIN SVIN

ON/OFF CONTROL

RUN1 RUN0

FAULT INTERRUPTS

FAULT0 FAULT1

SYNCHRONIZATION TIME-BASE
REGISTER WRITE PROTECTION

SYNC SHARE_CLK WP

LTM4678

2200pF 100pF

SW0 VOUT0 VOSNS0+
VOSNS0 SW1
VOUT1 VOSNS1+
VOSNS1

LOAD0 LOAD1

100µF ×4

VOUT0 1V, ADJUSTABLE UP TO 3.4V AT 25A
COUT0* BULK

100µF ×4

VOUT1 1V, ADJUSTABLE UP TO 3.4V AT 25A
COUT1* BULK

SCL SDA ALERT GND SGND
4678 TC01

I2C/SMBus I/F WITH PMBus COMMAND SET TO/FROM IPMI OR OTHER BOARD MANAGEMENT CONTROLLER
*COUT0 AND COUT1 ARE OPTIONAL FOR ATE TEST
(PULL-UP RESISTORS ON DIGITAL I/O PINS NOT SHOWN)

Test Circuit 2. LTM4678 ATE Low VIN Operating Range Configuration, 4.5V VIN 5.75V

1 SVIN

2.2µF

VDD33 VDD25 INTVCC EXTVCC PGOOD0 PGOOD1 TSNS0a TSNS0b TSNS1a TSNS1b

COMP1a COMP1b COMP0a COMP0b VTRIM1_CFG VTRIM0_CFG VOUT0_CFG VOUT1_CFG FSWPH_CFG ASEL

VIN

4.5V TO 5.75V

IIN+

150µF

RSENSE

IIN

22µF

×5

VIN1

VIN0 SVIN SVIN

ON/OFF CONTROL

RUN1 RUN0

FAULT INTERRUPTS

FAULT0 FAULT1

SYNCHRONIZATION TIME-BASE
REGISTER WRITE PROTECTION

SYNC SHARE_CLK WP

LTM4678

2200pF 100pF

SW0 VOUT0 VOSNS0+
VOSNS0 SW1
VOUT1 VOSNS1+
VOSNS1

LOAD0 LOAD1

100µF ×4

VOUT0 1V, ADJUSTABLE UP TO 3.4V AT 25A
COUT0* BULK

100µF ×4

VOUT1 1V, ADJUSTABLE UP TO 3.4V AT 25A
COUT1* BULK

SCL SDA ALERT GND SGND
4678 TC02

I2C/SMBus I/F WITH PMBus COMMAND SET TO/FROM IPMI OR OTHER BOARD MANAGEMENT CONTROLLER
*COUT0 AND COUT1 ARE OPTIONAL FOR ATE TEST
(PULL-UP RESISTORS ON DIGITAL I/O PINS NOT SHOWN)

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Rev. A
21

LTM4678

OPERATION

POWER MODULE INTRODUCTION

n Programmable Output Voltage

The LTM4678 is a highly configurable dual 25A output standalone nonisolated switching mode step-down DC/DC power supply with built-in EEPROM NVM (nonvolatile memory) with ECC and I2C-based PMBus/ SMBus 2-wire serial communication interface capable of 400kHz SCL bus speed. Two output voltages can be regulated (VOUT0, VOUT1--collectively, VOUTn) with a few external input and output capacitors and pull-up resistors. Readback telemetry data of input and output voltages and input and output currents, and module temperatures are continually digitized cyclically by an integrated 16-bit ADC (analog-todigital converter). Many fault thresholds and responses are customizable. Data can be autonomously saved to EEPROM when a fault occurs, and the resulting fault log can be retrieved over I2C at a later time, for analysis. See Figure 2 and Figure 3 for Block Diagrams.
POWER MODULE OVERVIEW, MAJOR FEATURES
Major Features Include:
n Dedicated Power Good Indicators
n Direct Input and Chip Current Sensing
n Programmable Loop Compensation Parameters
n TINIT Start-Up Time: 30ms
n PWM Synchronization Circuit, (See Frequency and Phasing Section for Details)
n MFR_ADC_CONTROL for Fast ADC Sampling of One Parameter (as Fast as 8ms) (See PMBus Command for Details)
n Fully Differential Output Sensing for Both Channels; VOUT0/VOUT1 Both Programmable Up to 3.6V
n Power-Up and Program EEPROM with EXTVCC
n Input Voltage Up to 16V
n VBE Temperature Sensing
n SYNC Contention Circuit (Refer to Frequency and Phase Section for Details)
n Fault Logging

n Programmable Input Voltage On and Off Threshold Voltage
n Programmable Current Limit
n Programmable Switching Frequency
n Programmable OV and UV Threshold voltage
n Programmable ON and Off Delay Times
n Programmable Output Rise/Fall Times
n Phase-Locked Loop for Synchronous PolyPhase Operation (2, 3, 4 or 6 Phases)
n Nonvolatile Configuration Memory with ECC
n Optional External Configuration Resistors for Key Operating Parameters
n Optional Time Base Interconnect for Synchronization Between Multiple Controllers
n WP Pin to Protect Internal Configuration
n Stand Along Operation After User Factory Configuration
n PMBus, Version 1.2, 400kHz Compliant Interface
The PMBus interface provides access to important power management data during system operation including:
n Internal Controller Temperature
n Internal Power Channel Temperature Average Output Current
n Average Output Voltage
n Average Input Voltage
n Average Input Current
n Average Chip Input Current from VIN n Configurable, Latched and Unlatched Individual Fault
and Warning Status
Individual channels are accessed through the PMBus using the PAGE command, i.e., PAGE 0 or 1.
Fault reporting and shutdown behavior are fully configurable. Two individual FAULT0, FAULT1 outputs are provided, both of which can be masked independently.
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LTM4678

OPERATION

Three dedicated pins for ALERT, PGOOD0/PGOOD1 functions are provided. The shutdown operation also allows all faults to be individually masked and can be operated in either unlatched (hiccup) or latched modes.
Individual status commands enable fault reporting over the serial bus to identify the specific fault event. Fault or warning detection includes the following:

The degradation in EEPROM retention for temperatures >125°C can be approximated by calculating the dimensionless acceleration factor using the following equation:

Ea k

TUSE

1 +273

1 TSTRESS

+273

where:

n Output Undervoltage/Overvoltage
n Input Undervoltage/Overvoltage
n Input and Output Overcurrent
n Internal Overtemperature
n Communication, Memory or Logic (CML) Fault
EEPROM WITH ECC
The LTM4678 contains internal EEPROM with ECC (Error Correction Coding) to store user configuration settings and fault log information. EEPROM endurance retention and mass write operation time are specified in the Electrical Characteristics and Absolute Maximum Ratings sections. Write operations above TJ = 85°C are possible although the Electrical Characteristics are not guaranteed and the EEPROM will be degraded. Read operations performed at temperatures between 40°C and 125°C will not degrade the EEPROM. Writing to the EEPROM above 85°C will result in a degradation of retention characteristics. The fault logging function, which is useful in debugging system problems that may occur at high temperatures, only writes to fault log EEPROM locations. If occasional writes to these registers occur above 85°C, the slight degradation in the data retention characteristics of the fault log will not take away from the usefulness of the function.
It is recommended that the EEPROM not be written when the die temperature is greater than 85°C. If the die temperature exceeds 130°C, the LTM4678 will disable all EEPROM write operations. All EEPROM write operations will be re-enabled when the die temperature drops below 125°C. (The controller will also disable all the switching when the die temperature exceeds the internal overtemperature fault limit 160°C with a 10°C hysteresis).

AF = acceleration factor
Ea = activation energy = 1.4eV K = 8.617 · 105 eV/°K
TUSE = 125°C specified junction temperature TSTRESS = actual junction temperature in °C
Example: Calculate the effect on retention when operating at a junction temperature of 135°C for 10 hours.
TSTRESS = 130°C
TUSE = 125°C, AF = e([(1.4/8.617 · 105) · (1/398 1/403)] ) = 16.6
The equivalent operating time at 125°C = 16.6 hours.
Thus the overall retention of the EEPROM was degraded by 16.6 hours as a result of operating at a junction temperature of 130°C for 10 hours. The effect of the overstress is negligible when compared to the overall EEPROM retention rating of 87,600 hours at a maximum junction temperature of 125°C.
The integrity of the entire onboard EEPROM is checked with a CRC calculation each time its data is to be read, such as after a power-on reset or execution of a RESTORE_USER_ ALL command. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC command is set, and the ALERT and RUN pins pulled low (PWM channels off). At that point the device will only respond at special address 0x7C, which is activated only after an invalid CRC has been detected. The chip will also respond at the global addresses 0x5A and 0x5B, but use of these addresses when attempting to recover from a CRC issue is not recommended. All power supply rails associated with either PWM channel of a device reporting an invalid CRC should remain disabled until the issue is resolved. See the Applications Information section or contact the factory
Rev. A

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LTM4678

OPERATION

for details on efficient in-system EEPROM programming, including bulk EEPROM Programming, which the LTM4678 also supports.

able for transient and stability analysis, and experienced users who prefer to adjust the module's feedback loop compensation parameters can use this tool.

The LTM4678 contains dual integrated constant frequency current mode control buck regulators (channel 0 and channel 1) whose built-in power MOSFETs are capable of fast switching speed. The factory NVM-default switching frequency clocks SYNC at 575kHz, to which the regulators synchronize their switching frequency. The default phase-interleaving angle between the channels is 180°. A pin-strapping resistor on FSWPH_CFG configures the frequency of the SYNC clock (switching frequency) and the channel phase relationship of the channels to each other and with respect to the falling edge of the SYNC signal. (Most possible combinations of switching frequency and phase-angle assignments are settleable by resistor pin programming; see Table 3. Configure the LTM4678's NVM to implement settings not available by resistor-pin strapping.) When a FSWPH_CFG pin-strap resistor sets the channel phase relationship of the LTM4678's channels, the SYNC clock is not driven by the module; instead, SYNC becomes strictly a high impedance input and channel switching frequency is then synchronized to SYNC provided by an externally-generated clock or sibling LTM4678 with pull-up resistor to VDD33. Switching frequency and phase relationship can be altered via the I2C interface, but only when switching action is off, i.e., when the module is not regulating either output. See the Applications Information section for details.
Programmable analog feedback loop compensation for channel 0 and channel 1 is accomplished with a capacitor connection from COMP0,1a to SGND, and a capacitor from COMP0,1b to SGND.) The COMP01b pin is for the high frequency gain roll off and is the gm amplifier output that has a programmable range, and the COMP0,1a pin has the programmable resistor range along with a capacitor to SGND that sets the frequency compensation. See Programmable Loop Compensation section. The LTM4678 module has sufficient stability margins and good transient performance with a wide range of output capacitors--even all-ceramic MLCCs. Table 13 provides guidance on input and output capacitors recommended for many common operating conditions along with the programmable compensation settings. The Analog Devices LTpowerCAD tool is avail-

POWER-UP AND INITIALIZATION
The LTM4678 is designed to provide standalone supply sequencing and controlled turn-on and turn-off operation. It operates from a single input supply (4.5V to 16V) while three on-chip linear regulators generate internal 2.5V, 3.3V and 5.5V. If VIN does not exceed 6V, and the EXTVCC pin is not driven by an external supply, the INTVCC and VIN pins must be tied together. The controller configuration is initialized by an internal threshold based UVLO where VIN must be approximately 4V and the 5.5V, 3.3V and 2.5V linear regulators must be within approximately 20% of the regulated values. In addition to the power supply, a PMBus RESTORE_USER_ALL or MFR_RESET command can initialize the part too.
The EXTVCC pin is driven by an external regulator to improve efficiency of the circuit and minimize power loss on the LTM4678 when VIN is high. The EXTVCC pin must exceed approximately 4.7V, and VIN must exceed approximately 7V before the INTVCC LDO operates from the EXTVCC pin. To minimize application power, the EXTVCC pin can be supplied by a switching regulator.
During initialization, the external configuration resistors are identified and/or contents of the NVM are read into the controller's commands and the power train is held off. The RUNn and FAULTn and PGOODn are held low. The LTM4678 will use the contents of Table 1 thru Table 5 to determine the resistor defined parameters. See the RCONFIG (Resistor Configuration) Pins section for more details. The resistor configuration pins only control some of the preset values of the controller. The remaining values are programmed in NVM either at the factory or by the user.
If the configuration resistors are not inserted or if the ignore RCONFIG bit is asserted (bit 6 of the MFR_CONFIG_ALL configuration command), the LTM4678 will use only the contents of NVM to determine the DC/DC characteristics. The ASEL value read at power-up or reset is always respected unless the pin is open. The ASEL will set the bottom 4LSBs and the MSBs are set by NVM. See the Applications Information section for more details.
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LTM4678

OPERATION

After the part has initialized, an additional comparator monitors VIN. The VIN_ON threshold must be exceeded before the output power sequencing can begin. After VIN is initially applied, the part will typically require 30ms to initialize and begin the TON_DELAY timer. The readback of voltages and currents may require an additional 0ms to 90ms.
SOFT-START
The method of start-up sequencing described below is time-based. The part must enter the run state prior to soft-start. The run pins are released by the LTM4678 after the part is initialized and VIN is greater than the VIN_ON threshold. If multiple LTM4678s are used in an application, they all hold their respective run pins low until all devices are initialized and VIN exceeds the VIN_ON threshold for every device. The SHARE_CLK pin assures all the devices connected to the signal use the same time base. The SHARE_CLK pin is held low until the part has been initialized after VIN is applied. The LTM4678 can be set to turn-off (or remain off) if SHARE_CLK is low (set bit 2 of MFR_CHAN_CONFIG to 1). This allows the user to assure synchronization across numerous LTC® devices even if the RUN pins cannot be connected together due to board constraints. In general, if the user cares about synchronization between chips it is best not only to connect all the respective RUN pins together but also to connect all the respective SHARE_CLK pins together and pulled up to VDD33 with a 10k resistor. This assures all chips begin sequencing at the same time and use the same time base.
After the RUN pins release and prior to entering a constant output voltage regulation state, the LTM4678 performs a monotonic initial ramp or "soft-start". Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0V to the commanded voltage set-point. Once the LTM4678 is commanded to turn on (after power up and initialization), the controller waits for the user specified turn-on delay (TON_DELAY) prior to initiating this output voltage ramp. The rise time of the voltage ramp can be programmed using the TON_RISE command to minimize inrush currents associated with the start-up voltage ramp. The soft-start feature is disabled by setting the value of TON_RISE to any value less than 0.25ms. The

LTM4678 PWM always uses discontinuous mode during the TON_RISE operation. In discontinuous mode, the bottom MOSFET is turned off as soon as reverse current is detected in the inductor. This will allow the regulator to start up into a pre-biased load. When the TON_MAX_FAULT_LIMIT is reached, the part transitions to continuous mode, if so programmed. If TON_MAX_FAULT_LIMIT is set to zero, there is no time limit and the part transitions to the desired conduction mode after TON_RISE completes and VOUT has exceeded the VOUT_UV_FAULT_LIMIT and IOUT_OC is not present. However, setting TON_MAX_FAULT_LIMIT to a value of 0 is not recommended.
TIME-BASED SEQUENCING
The default mode for sequencing the outputs on and off is time-based. Each output is enabled after waiting TON_DELAY amount of time following either a RUN pin going high, a PMBus command to turn on or the VIN rising above a preprogrammed voltage. Off sequencing is handled in a similar way. To assure proper sequencing, make sure all ICs connect the SHARE_CLK pin together and RUN pins together. If the RUN pins cannot be connected together for some reasons, set bit 2 of MFR_CHAN_ CONFIG to 1. This bit requires the SHARE_CLK pin to be clocking before the power supply output can start. When the RUN pin is pulled low, the LTM4678 will hold the pin low for the MFR_ RESTART_DELAY. The minimum MFR_RESTART_ DELAY is TOFF_DELAY + TOFF_FALL + 136ms. This delay assures proper sequencing of all rails. The LTM4678 calculates this delay internally and will not process a shorter delay. However, a longer commanded MFR_RESTART_DELAY can be used by the part. The maximum allowed value is 65.52 seconds.
VOLTAGE-BASED SEQUENCING
The sequence can also be voltage-based. As shown in Figure 4, The PGOODn pin is asserted when the UV threshold is exceeded for each output. It is possible to feed the PGOOD pin from one LTM4678 into the RUN pin of the next LTM4678 in the sequence, especially across multiple LTM4678s. The PGOODn has a 60µs filter. If the VOUT voltage bounces around the UV threshold for a long period of time it is possible for the PGOODn output

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LTM4678

OPERATION

START

RUN0 RUN1

LTM4678

PGOOD0 PGOOD1

RUN0 RUN1

LTM4678
4678 F04

PGOOD0 PGOOD1

TO NEXT CHANNEL IN THE SEQUENCE
Figure 4. Event (Voltage) Based Sequencing

to toggle more than once. To minimize this problem, set the TON_RISE time under 100ms.
If a fault in the string of rails is detected, only the faulted rail and downstream rails will fault off. The rails in the string of devices in front of the faulted rail will remain on unless commanded off.

SHUTDOWN
The LTM4678 supports two shutdown modes. The first mode is closed-loop shutdown response, with user defined turn-off delay (TOFF_DELAY) and ramp down rate (TOFF_FALL). The controller will maintain the mode of operation for TOFF_FALL. The second mode is discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current, instead of TOFF_FALL.
The shutdown occurs in response to a fault condition or loss of SHARE_CLK (if bit 2 of MFR_CHAN_ CONFIG is set to a 1) or VIN falling below the VIN_OFF threshold or FAULT pulled low externally (if the MFR_FAULT_ RESPONSE is set to inhibit). Under these conditions, the power stage is disabled in order to stop the transfer of energy to the load as quickly as possible. The shutdown state can be entered from the soft-start or active regulation states or through user intervention.
There are two ways to respond to faults; which are retry mode and latched off mode. In retry mode, the controller responds to a fault by shutting down and entering the inactive state for a programmable delay time (MFR_RETRY_ DELAY). This delay minimizes the duty cycle associated with autonomous retries if the fault that causes the shutdown disappears once the output is disabled. The retry delay

time is determined by the longer of the MFR_RETRY_ DELAY command or the time required for the regulated output to decay below 12.5% of the programmed value. If multiple outputs are controlled by the same FAULTn pin, the decay time of the faulted output determines the retry delay. If the natural decay time of the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of MFR_CHAN_CONFIG. Alternatively, latched off mode means the controller remains latched-off following a fault and clearing requires user intervention such as toggling RUNn or commanding the part OFF then ON.
LIGHT-LOAD CURRENT OPERATION
The LTM4678 has two modes of operation: high efficiency discontinuous conduction mode or forced continuous conduction mode. Mode selection is done using the MFR_PWM _MODE command (discontinuous conduction is always the start-up mode, forced continuous is the default running mode).
If a controller is enabled for discontinuous operation, the inductor current is not allowed to reverse. The reverse current comparator's output turns off the bottom MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative.
In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined solely by the voltage on the COMPn pins. In this mode, the efficiency at light loads is lower than in discontinuous mode operation. However, continuous mode exhibits lower output ripple and less interference with audio circuitry, but may result in reverse inductor current, which can cause the input supply to boost. The VIN_OV_FAULT_LIMIT can detect this and turn off the offending channel. However, this fault is based on an ADC read and can take up to tCONVERT to detect. If there is a concern about the input supply boosting, keep the part in discontinuous conduction mode.
If the part is set to discontinuous mode operation, as the inductor average current increases, the controller will automatically modify the operation from discontinuous mode to continuous mode.

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LTM4678

OPERATION

SWITCHING FREQUENCY AND PHASE

PWM LOOP COMPENSATION

The switching frequency of the PWM can be established with an internal oscillator or an external time base. The internal phase-locked loop (PLL) synchronizes the PWM control to this timing reference with proper phase relation, whether the clock is provided internally or externally. The device can also be configured to provide the master clock to other devices through PMBus command, NVM setting, or external configuration resistors as outlined in Table 3.
As clock master, the LTM4678 will drive its open-drain SYNC pin at the selected rate with a pulse width of 500ns. An external pull-up resistor between SYNC and VDD33 is required in this case. Only one device connected to SYNC should be designated to drive the pin. The LTM4678 will automatically revert to an external SYNC input, disabling its own SYNC, as long as the external SYNC frequency is greater than 80% of the programmed SYNC frequency. The external SYNC input shall have a duty cycle between 20% and 80%.
Whether configured to drive SYNC or not, the LTM4678 can continue PWM operation using its own internal oscillator if an external clock signal is subsequently lost.
The device can also be programmed to always require an external oscillator for PWM operation by setting bit 4 of MFR_CONFIG_ALL. The status of the SYNC driver circuit is indicated by bit 10 of MFR_PADS.
The MFR_PWM_CONFIG command can be used to configure the phase of each channel. Desired phase can also be set from EEPROM or external configuration resistors as outlined in Table 3. Designated phase is the relationship between the falling edge of SYNC and the internal clock edge that sets the PWM latch to turn on the top power switch. Additional small propagation delays to the PWM control pins will also apply. Both channels must be off before the FREQUENCY_SWITCH and MFR_PWM_CONFIG commands can be written to the LTM4678.
The phase relationships and frequency options provide for numerous application options. Multiple LTM4678 modules can be synchronized to realize a PolyPhase array. In this case the phases should be separated by 360/n degrees, where n is the number of phases driving the output voltage rail.

The internal PWM loop compensation resistors RCOMPna of the LTM4678 can be adjusted using bit[4:0] of the MFR_PWM_COMP command.
The transconductance (gm) of the LTM4678 PWM error amplifier can be adjusted using bit[7:5] of the MFR_PWM_ COMP command. These two loop compensation parameters can be programmed when device is in operation. Refer to the Programmable Loop Compensation subsection in the Applications Information section for further details.
OUTPUT VOLTAGE SENSING
Both channels in LTM4678 have differential amplifiers, which allow the remote sensing of the load voltage between V+ and V pins. The telemetry ADC is also fully differential and makes measurements between VOSNSn+ and VOSNSn-voltages for both channels at the V+ and V pins, respectively. The maximum allowed 3.6V, but the LTM4678 design is limited to 3.4V output.
INTVCC/EXTVCC POWER
Power for the internal top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is shorted to GND or tied to a voltage less than 4.7V, an internal 5.5V linear regulator supplies INTVCC power from VIN. If EXTVCC is taken above 4.7V and VIN is higher than 7.0V, the 5.5V regulator is turned off and an internal switch is turned on, connecting EXTVCC to INTVCC. Using the EXTVCC allows the INTVCC power to be derived from a high efficiency external source such as a switching regulator output. EXTVCC can provide power to the internal 3.3V linear regulator even when VIN is not present, which allows the LTM4678 to be initialized and programmed even without main power being applied.
The INTVCC regulator is powered from the SVIN pin, the power through the IC is equal to SVIN · IINTVCC. The gate charge current is dependent on operating frequency. The INTVCC regulator can supply up to 100mA, and the typical INTVCC current for the LTM4678 is ~50mA. A 12V input voltage would equate to a difference of 7V drop across the internal controller, when multiplied by 50mA equals a

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LTM4678

OPERATION

350mW power loss. This loss can be eliminated by providing an external 5V bias on the EXTVCC pin.
Do not tie INTVCC on the LTM4678 to an external supply because INTVCC will attempt to pull the external supply high and hit current limit, significantly increasing the die temperature.
For applications where VIN is 5V, tie the VIN and INTVCC pins together to the 5V input through a 1 or 2.2 resistor as shown in Test Circuit 2.
OUTPUT CURRENT SENSING AND SUB MILLIOHM DCR CURRENT SENSING
The LTM4678 use a unique sub-milliohm inductor current sensing technique that provides a high level signal to noise ratio while sensing very low signals in current mode operation. This enables higher conversion efficiencies with the use of the internal sub-milliohm inductors in heavy load applications. The current limit threshold can be accurately set with the MFR_PWM_MODE[7] for High and Low range (see page 89).
The internal DCR sensing network, thus current limit are calculated based on the DCR of the inductor at room temperature. The DCR of the inductor has a large temperature coefficient, approximately 3900ppm/°C. The temperature coefficient of the inductor is written to the MFR_IOUT_ CAL_GAIN_TC register. The external temperature is sensed near the inductor and used to modify the internal current limit circuit to maintain an essentially constant current limit with temperature. The current sensed is then digitized by the LTM4678's telemetry ADC with an input range of ±128mV, a noise floor of 7µVRMS, and a peak-peak noise of approximately 46.5µV. The LTM4678 computes the inductor current using the DCR value stored in the IOUT_CAL_GAIN command and the temperature coefficient stored in command MFR_IOUT_CAL_GAIN_TC. The resulting current value is returned by the READ_IOUT command.

to ±5% over temperature. This readback accuracy can be improved by evaluation the LTM4678 in the end system. Evaluating the ambient temperature, airflow, and the difference of the temperature between the GUI and the inductors on top can provide an offset value that can be programmed to improve the output current readback using the MFR_TEMP_1_OFFSET command.
INPUT CURRENT SENSING
To sense the total input current consumed by the LTM4678's power stages , a sense resistor is placed between the supply voltage and the drain of the top N-channel MOSFET. The IIN+ and IIN pins are connected to the sense resistor. The filtered voltage is amplified by the internal high side current sense amplifier and digitized by the LTM4678's telemetry ADC. The input current sense amplifier has three gain settings of 2x, 4x, and 8x set by the bit[3:2] of the MFR_PWM_MODE command. The maximum input sense voltage for the three gain settings is 50mV, 20mV, and 5mV respectively. The LTM4678 computes the input current using the internal RSENSE value stored in the IIN_CAL_GAIN command. The resulting measured power stage current is returned by the READ_IIN command.
The LTM4678 uses a 1 resistor to measure the SVIN pin supply current being consumed by the LTM4678. This value is returned by the MFR_READ_ICHIP command. The chip current is calculated by using the 1 value stored in the MFR_ICHIP_CAL_GAIN command. Refer to the subsection titled Input Current Sense Amplifier in the Applications Information section for further details.
PolyPhase LOAD SHARING
Multiple LTM4678s can be arrayed in order to provide a balanced load-share solution by bussing the necessary pins. Figure 47 illustrates a 4-Phase design sharing connections required for load sharing.

The LTM4678 power inductors for each channel are on top of the module and the temperature sensors for each channel are down on the substrate near the power stages and the inductor clip. They are about a 12°C difference at maximum load between the inductors and temperature sensor. This has degraded the output current readback

If an external oscillator is not provided, the SYNC pin should only be enabled on one of the LTM4678s. The other(s) should be programmed to disable SYNC using bit 4 of MFR_CONFIG_ALL. If an external oscillator is present, the chip with the SYNC pin enabled will detect the presence of the external clock and disable its output.

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LTM4678

OPERATION
Multiple channels need to tie all the VOSNSn+ pins together, and all the VOSNSn pins together, COMPna and COMPnb pins together as well. Do not assert bit[4] of MFR_CONFIG_ALL except in a PolyPhase application.
The user must share the SYNC, SHARE_CLK, FAULT, and ALERT pins of these parts. Be sure to use pull-up resistors on SYNC, FAULT, SHARE_CLK and ALERT.
EXTERNAL/INTERNAL TEMPERATURE SENSE
Temperature is measured using the internal diode-connected PNP transistors on either of the TSNS0b or TSNS1b pins corresponding to channel 0 or 1. TSNSnb pins should be connected to their respective TSNSna pins, and these returns are directly connected to the LTM4678 SGND pin. Two different currents are applied to the diode (nominally 2µA and 32µA) and the temperature is calculated from a VBE measurement made with the internal 16-bit monitor ADC (see Figure 2 Block Diagram).
The LTM4678 will only implement VBE temperature sensing, therefore MFR_PWM_MODE bit[5] is reserved.
CH0 and CH1 temperatures can be linked to CH0 only for adjusting the temperature compensated variables, and internal temperature monitoring. This frees up TSNS1a for an external/temperature sensing.
RCONFIG (RESISTOR CONFIGURATION) PINS
There are six input pins utilizing 1% resistors between these pins and SGND to select key operating parameters. The pins are ASEL, FSWPH_CFG, VOUT0_CFG, VOUT1_CFG, VTRIM0_CFG, VTRIM1_CFG. If pins are floated, the value stored in the corresponding NVM command is used. If bit 6 of the MFR_CONFIG_ALL configuration command is asserted in NVM, the resistor input is ignored upon power-up except for ASEL which is always respected. The resistor configuration pins are only measured during a power-up reset or after a MFR_RESET or after a RESTORE_USER_ALL command is executed.

The VOUTn_CFG pin settings are described in Table 1. These pins set the LTM4678 VOUT0 and VOUT1 output voltage coarse settings. If the pin is open, the VOUT_COMMAND command is loaded from NVM to determine the output voltage. The default setting is to have the switcher off unless the voltage configuration pins are installed. The VTRIMn_CFG pins in Table 2 are used to set the output voltage fine adjustment setting. Both combine to offer several distinct output voltages.

Table 1. VOUTn _CFG Pin Strapping Look-Up Table for the LTM4678's Output Voltage, Coarse Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b)

RVOUTn_CFG* (k)

VOUTn (V) SETTING COARSE

MFR_PWM_ MODEn[1] BIT

Open

NVM

32.4

NVM

22.6

3.3

18.0

3.1

15.4

2.9

12.7

2.7

10.7

2.5

0, if VTRIMn > 0mV

1, if VTRIMn 0mV

9.09

2.3

7.68

2.1

6.34

1.9

5.23

1.7

4.22

1.5

3.24

1.3

2.43

1.1

1.65

0.9

0.787

0.7

0.5

*RVOUTn_CFG value indicated is nominal. Select RVOUTn_CFG from a resistor vendor such that its value is always within 3% of the value
indicated in the table. Take into account resistor initial tolerance, T.C.R.
and resistor operating temperatures, soldering heat/IR reflow, and
endurance of the resistor over its lifetime. Thermal shock/cycling,
moisture (humidity) and other effects (depending on one's specific
application) could also affect RVOUTn_CFG's value over time. All such effects must be taken into account in order for resistor pin strapping to
yield the expected result at every SVIN power-up and/or every execution of MFR_RESET or RESTORE_ USER_ALL, over the lifetime of one's
product.

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LTM4678

OPERATION

Table 2. VTRIMn_CFG Pin Strapping Look-Up Table for the LTM4678's Output Voltage, Fine Adjustment Setting (Not Applicable if MFR_CONFIG_ALL[6] = 1b)

RVTRIMn_CFG* (k)

VTRIM (mV) FINE ADJUSTMENT TO VOUTn SETTING WHEN RESPECTIVE

Open

32.4

22.6

86.625

18.0

74.25

15.4

61.875

12.7

49.5

10.7

37.125

9.09

24.75

7.68

12.375

6.34

12.375

5.23

24.75

4.22

37.125

3.24

49.5

2.43

61.875

1.65

74.25

0.787

86.625

*RVTRIMn_CFG value indicated is nominal. Select RVTRIMn_CFG from a resistor vendor such that its value is always within 3% of the value
indicated in the table. Take into account resistor initial tolerance, T.C.R.
and resistor operating temperatures, soldering heat/IR reflow, and
endurance of the resistor over its lifetime. Thermal shock/cycling,
moisture (humidity) and other effects (depending on one's specific
application) could also affect RVTRIMn_CFG's value over time. All such effects must be taken into account in order for resistor pin strapping to
yield the expected result at every SVIN power-up and/or every execution of MFR_RESET, or RESTORE_USER_ALL over the lifetime of one's
product.

The following parameters are set as a percentage of the output voltage if the RCONFIG pins are used to determine the output voltage:
n VOUT_OV_FAULT_LIMIT.....................................+10% n VOUT_OV_WARN_LIMIT.....................................+7.5% n VOUT_MAX..........................................................+7.5% n VOUT_MARGIN_HIGH.........................................+5% n VOUT_MARGIN_LOW..........................................5% n VOUT_UV_FAULT_LIMIT.....................................7%
The FSWPH_CFG pin settings are described in Table 3. This pin selects the switching frequency and phase of each channel. The phase relationships between the two channels and SYNC pin are determined in Table 3. To synchronize to an external clock, the part should be put into external clock mode (SYNC output disabled but frequency set to the nominal value). If no external clock is supplied, the part will clock at the programmed frequency. If the application is multiphase and the SYNC signal between chips is lost, the parts will not operate at the designed phase even if they are programmed and trimmed to the same frequency.
This may increase the ripple voltage on the output, possibly produce undesirable operation. If the external SYNC signal is being generated internally and external SYNC is not selected, bit 10 of MFR_PADS will be asserted. If no frequency is selected and the external SYNC frequency is not present, a PLL_FAULT will occur. If the user does not wish to see the ALERT from a PLL_FAULT even if there is not a valid synchronization signal at power-up, the ALERT mask for PLL_FAULT must be written. See the description on SMBALERT_MASK for more details. If the SYNC pin is connected between multiple ICs only one of the ICs should have the SYNC pin enabled using the MFR_CONFIG_ALL[4] =1, and all other ICs should be configured to have the SYNC pin disabled with MFR_CONFIG_ALL[4] =0.
The ASEL pin settings are described in Table 4. ASEL selects slave address for the LTM4678. For more detail, refer to Table 5.
NOTE: Per the PMBus specification, pin programmed parameters can be overridden by commands from the digital interface with the exception of ASEL which is always honored. Do not set any part address to 0x5A or 0x5B because these are global addresses and all parts will respond to them.

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LTM4678

OPERATION

Table 3. FSWPH_CFG Pin Strapping Look-Up Table to Set the LTM4678's Switching Frequency and Channel Phase-Interleaving Angle (Not Applicable if MFR_CONFIG_ALL[6] = 1b)

RFSWPH_CFG* (k)

SWITCHING FREQUENCY (kHz)

SYNC TO 0

SYNC TO 1

bits [2:0] of MFR_ PWM_CONFIG

bit [4] of MFR_ CONFIG_ALL

NVM; LTM4678

Open

Default = 350

Default = 0°

Default = 180°

Default = 000b

Default = 0b

32.4

250

0°

180°

000b

22.6

350

0°

180°

000b

18.0

425

0°

180°

000b

15.4

575

0°

180°

000b

12.7

650

0°

180°

000b

10.7

750

0°

180°

000b

7.68

500

120°

240°

100b

6.34

500

90°

270°

001b

5.23

External**

0°

240°

010b

4.22

External**

0°

120°

011b

3.24

External**

60°

240°

101b

2.43

External**

120°

300°

110b

1.65

External**

90°

270°

001b

0.787

External**

0°

180°

000b

External**

120°

240°

100b

*RFSWPH_CFG value indicated is nominal. Select RFSWPH_CFG from a resistor vendor such that its value is always within 3% of the value indicated in the table. Take into account resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over
its lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending on one's specific application) could also affect RFSWPH_CFG's value over time. All such effects must be taken into account in order for resistor pin-strapping to yield the expected result at every SVIN power-up and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one's product.

**External setting corresponds to FREQUENCY_SWITCH (Register 0x33) value set to 0x0000; the device synchronizes its switching frequency to that of the clock provided on the SYNC pin, provided MFR_CONFIG_ALL[4] = 1b.

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Rev. A
31

LTM4678

OPERATION

Table 4. ASEL Pin Strapping Look-Up Table to Set the LTM4678's Slave Address (Applicable Regardless of MFR_CONFIG_ALL[6] Setting)

RASEL* (k) Open

SLAVE ADDRESS 100_1111_R/W

32.4

100_1111_R/W

22.6

100_1110_R/W

18.0

100_1101_R/W

15.4

100_1100_R/W

12.7

100_1011_R/W

10.7

100_1010_R/W

9.09

100_1001_R/W

7.68

100_1000_R/W

6.34

100_0111_R/W

5.23

100_0110_R/W

4.22

100_0101_R/W

3.24

100_0100_R/W

2.43

100_0011_R/W

1.65

100_0010_R/W

0.787

100_0001_R/W

100_0000_R/W

Where:

R/W = Read/Write bit in control byte

All PMBus device addresses listed in the specification are 7 bits wide unless otherwise noted.

Note: The LTM4678 will always respond to slave address 0x5A and 0x5B regardless of the NVM or ASEL resistor configuration values.

*RCFG value indicated is nominal. Select RCFG from a resistor vendor such that its value is always within 3% of the value indicated in the table.
Take into account resistor initial tolerance, T.C.R. and resistor operating
temperatures, soldering heat/IR reflow, and endurance of the resistor
over its lifetime. Thermal shock cycling, moisture (humidity) and other
effects (depending on one's specific application) could also affect RCFG's value over time. All such effects must be taken into account in order for
resistor pin-strapping to yield the expected result at every SVIN power-up and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the
lifetime of one's product.

Table 5. LTM4678 MFR_ADDRESS Command Examples Expressed in 7- and 8-Bit Addressing

HEX DEVICE

ADDRESS

BIT

DESCRIPTION 7-BIT

Rail4

0x5A

8-BIT 7 6 5 4 3 2 1 0 R/W 0xB4 0 1 0 1 1 0 1 0 0

Global4

0x5B 0xB6 0 1 0 1 1 0 1 1 0

Default

0x4F 0x9E 0 1 0 0 1 1 1 1 0

Example 1

0x40 0x80 0 1 0 0 0 0 0 0 0

Example 2

0x41 0x82 0 1 0 0 0 0 0 1 0

Disabled2,3

10000000 0

Note 1: This table can be applied to the MFR_RAIL_ADDRESSn commands, but not the MFR_ADDRESS command.

Note 2: A disabled value in one command does not disable the device, nor does it disable the global address.

Note 3: A disabled value in one command does not inhibit the device from responding to device addresses specified in other commands.

Note 4: It is not recommended to write the value 0x00, 0x0C (7-bit), 0x5A (7-bit), 0x5B (7-bit) or 0x7C(7-bit) to the MFR_CHANNEL_ADDRESSn or the MFR_RAIL_ADDRESSn commands.

FAULT DETECTION AND HANDLING
A variety of fault and warning reporting and handling mechanisms are available. Fault and warning detection capabilities include:
n Input OV FAULT Protection and UV Warning
n Average Input OC Warn
n Output OV/UV Fault and Warn Protection
n Output OC Fault and Warn Protection
n Internal control Die and Internal Module Overtemperature Fault and Warn Protection
n Internal Undertemperature Fault and Warn Protection
n CML Fault (Communication, Memory or Logic)
n External Fault Detection via the Bidirectional FAULTn Pins
In addition, the LTM4678 can map any combination of fault indicators to their respective FAULTn pin using the propagate FAULTn response commands, MFR_FAULT_ PROPAGATE. Typical usage of a FAULTn pin is as a driver

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LTM4678

OPERATION
for an external crowbar device, overtemperature alert, overvoltage alert or as an interrupt to cause a microcontroller to poll the fault commands. Alternatively, the FAULTn pins can be used as inputs to detect external faults downstream of the controller that require an immediate response.
Any fault or warning event will always cause the ALERT pin to assert low unless the fault or warning is masked by the SMBALERT_MASK. The pin will remain asserted low until the CLEAR_FAULTS command is issued, the fault bit is written to a 1 or bias power is cycled or a MFR_RESET command is issued, or the RUN pins are toggled OFF/ON or the part is commanded OFF/ON via PMBus or an ARA command operation is performed. The MFR_FAULT_ PROPAGATE command determines if the FAULT pins are pulled low when a fault is detected.
Output and input fault event handling is controlled by the corresponding fault response byte as specified in Table 14 thru Table 18. Shutdown recovery from these types of faults can either be autonomous or latched. For autonomous recovery, the faults are not latched, so if the fault conditions not present after the retry interval has elapsed, a new soft-start is attempted.
If the fault persists, the controller will continue to retry. The retry interval is specified by the MFR_RETRY_DELAY command and prevents damage to the regulator components by repetitive power cycling, assuming the fault condition itself is not immediately destructive. The MFR_RETRY_DELAY must be greater than 120ms. It can not exceed 83.88 seconds.
Status Registers and ALERT Masking
Figure 5 summarizes the internal LTM4678 status registers accessible by PMBus command. These contain indication of various faults, warnings and other important operating conditions. As shown, the STATUS_BYTE and STATUS_WORD commands also summarize contents of other status registers. Refer to PMBus Command Details for specific information.

NONE OF THE ABOVE in the STATUS_BYTE indicates that one or more of the bits in the most-significant nibble of STATUS_WORD are also set.
In general, any asserted bit in a STATUS_x register also pulls the ALERT pin low. Once set, ALERT will remain low until one of the following occurs.
n A CLEAR_FAULTS or MFR_RESET Command Is Issued
n The Related Status Bit Is Written to a One
n The Faulted Channel Is Properly Commanded Off and Back On
n The LTM4678 Successfully Transmits Its Address During a PMBus ARA
n Bias Power Is Cycled
With some exceptions, the SMBALERT_MASK command can be used to prevent the LTM4678 from asserting ALERT for bits in these registers on a bit-by-bit basis. These mask settings are promoted to STATUS_WORD and STATUS_BYTE in the same fashion as the status bits themselves. For example, if ALERT is masked for all bits in channel 0 STATUS_VOUT, then ALERT is effectively masked for the VOUT bit in STATUS_WORD for PAGE 0. The BUSY bit in STATUS_BYTE also asserts ALERT low and cannot be masked. This bit can be set as a result of various internal interactions with PMBus communication. This fault occurs when a command is received that cannot be safely executed with one or both channels enabled. As discussed in the Applications Information, BUSY faults can be avoided by polling MFR_COMMON before executing some commands.
If masked faults occur immediately after power up, ALERT may still be pulled low because there has not been time to retrieve all of the programmed masking information from EEPROM.
Status information contained in MFR_COMMON and MFR_PADS can be used to further debug or clarify the contents of STATUS_BYTE or STATUS_WORD as shown, but the contents of these registers do not affect the state of the ALERT pin and may not directly influence bits in STATUS_BYTE or STATUS_WORD.

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33

LTM4678 OPERATION

STATUS_VOUT*
7 VOUT_OV Fault 6 VOUT_OV Warning 5 VOUT_UV Warning 4 VOUT_UV Fault 3 VOUT_MAX Warning 2 TON_MAX Fault 1 TOFF_MAX Warning 0 (reads 0)

(PAGED)

STATUS_IOUT
7 IOUT_OC Fault 6 (reads 0) 5 IOUT_OC Warning 4 (reads 0) 3 (reads 0) 2 (reads 0) 1 (reads 0) 0 (reads 0)

(PAGED)

STATUS_TEMPERATURE

7 OT Fault 6 OT Warning 5 (reads 0) 4 UT Fault 3 (reads 0) 2 (reads 0) 1 (reads 0) 0 (reads 0)

(PAGED)

STATUS_CML
7 Invalid/Unsupported Command 6 Invalid/Unsupported Data 5 Packet Error Check Failed 4 Memory Fault Detected 3 Processor Fault Detected 2 (reads 0) 1 Other Communication Fault 0 Other Memory or Logic Fault

STATUS_WORD
15 VOUT 14 IOUT 13 INPUT 12 MFR_SPECIFIC 11 POWER_GOOD# 10 (reads 0) 9 (reads 0) 8 (reads 0)
STATUS_BYTE
7 BUSY 6 OFF 5 VOUT_OV 4 IOUT_OC 3 (reads 0) 2 TEMPERATURE 1 CML 0 NONE OF THE ABOVE

(PAGED)

MFR_COMMON
7 Chip Not Driving ALERT Low 6 Chip Not Busy 5 Internal Calculations Not Pending 4 Output Not In Transition 3 EEPROM Initialized 2 (reads 0) 1 SHARE_CLK_LOW 0 WP Pin High

MFR_INFO
15 Reserved 14 Reserved 13 Reserved 12 Reserved 11 Reserved 10 Reserved 9 Reserved 8 Reserved 7 Reserved 6 Reserved 5 Reserved 4 EEPROM ECC Status 3 Reserved 2 Reserved 1 Reserved 0 Reserved

STATUS_INPUT 7 VIN_OV Fault 6 (reads 0) 5 VIN_UV Warning 4 (reads 0) 3 Unit Off for Insuffcient VIN 2 (reads 0) 1 IIN_OC Warning 0 (reads 0)
STATUS_MFR_SPECIFIC 7 Internal Temperature Fault 6 Internal Temperature Warning 5 EEPROM CRC Error 4 Internal PLL Unlocked 3 Fault Log Present 2 VDD33 UV or OV Fault 1 VOUT Short Cycled 0 FAULT Pulled Low By External Device
(PAGED)
MFR_PADS 15 VDD33 OV Fault 14 VDD33 UV Fault 13 (reads 0) 12 (reads 0) 11 Invalid ADC Result(s) 10 SYNC Clocked by External Source 9 Channel 1 is POWER_GOOD 8 Channel 0 is POWER_GOOD 7 LTM4678 Forcing RUN1 Low 6 LTM4678 Forcing RUN0 Low 5 RUN1 Pin State 4 RUN0 Pin State 3 LTM4678 Forcing FAULT1 Low 2 LTM4678 Forcing FAULT0 Low 1 FAULT1 Pin State 0 FAULT0 Pin State
4678 F05

DESCRIPTION

MASKABLE GENERATES ALERT BIT CLEARABLE

General Fault or Warning Event Yes

Yes

General Non-Maskable Event

Yes

Dynamic

Status Derived from Other Bits

Not Directly

Figure 5. LTM4678 Status Register Summary

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LTM4678

OPERATION
Mapping Faults to FAULT Pins
Channel-to-channel fault (including channels from multiple LTM4678s) dependencies can be created by connecting FAULTn pins together. In the event of an internal fault, one or more of the channels is configured to pull the bussed FAULTn pins low. The other channels are then configured to shut down when the FAULTn pins are pulled low. For autonomous group retry, the faulted channel is configured to let go of the FAULTn pin(s) after a retry interval, assuming the original fault has cleared. All the channels in the group then begin a soft-start sequence. If the fault response is LATCH_OFF, the FAULTn pin remains asserted low until either the RUN pin is toggled OFF/ON or the part is commanded OFF/ON. The toggling of the RUN either by the pin or OFF/ON command will clear faults associated with the channel. If it is desired to have all faults cleared when either RUN pin is toggled or, set bit 0 of MFR_CONFIG_ALL to a 1.
The status of all faults and warnings is summarized in the STATUS_WORD and STATUS_BYTE commands.
Additional fault detection and handling capabilities are:
Power Good Pins
The PGOODn pins of the LTM4678 are connected to the open drains of internal MOSFETs. The MOSFETs turn on and pull the PGOODn pins low when the channel output voltage is not within the channel's UV and OV voltage thresholds. During TON_DELAY and TON_RISE sequencing, the PGOODn pin is held low. The PGOODn pin is also pulled low when the respective RUNn pin is low. The PGOODn pin response is deglitched by an internal 60µs digital filter. The PGOODn pin and PGOOD status may be different at times due to communication latency of up to 10µs.
CRC Protection
The integrity of the NVM memory is checked after a power on reset. A CRC error will prevent the controller from leaving the inactive state. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_MFR_SPECIFIC command, and the ALERT pin will be pulled low. NVM

repair can be attempted by writing the desired configuration to the controller and executing a STORE_USER_ALL command followed by a CLEAR_FAULTS command.
The LTM4678 manufacturing section of the NVM is mirrored. If both copies are corrupted, the "NVM CRC Fault" in the STATUS_MFR_SPECIFIC command is set. If this bit remains set after being cleared by issuing a CLEAR_FAULTS or writing a 1 to this bit, an irrecoverable internal fault has occurred. The user is cautioned to disable both output power supply rails associated with this specific part. There are no provisions for field repair of NVM faults in the manufacturing section.
SERIAL INTERFACE
The LTM4678 serial interface is a PMBus compliant slave device and can operate at any frequency between 10kHz and 400kHz. The address is configurable using either the NVM or an external resistor. In addition the LTM4678 always responds to the global broadcast address of 0x5A (7-bit) or 0x5B (7-bit).
The serial interface supports the following protocols defined in the PMBus specifications: 1) send command, 2) write byte, 3) write word, 4) group, 5) read byte, 6) read word and 7) read block. 8) write block. All read operations will return a valid PEC if the PMBus master requests it. If the PEC_REQUIRED bit is set in the MFR_CONFIG_ALL command, the PMBus write operations will not be acted upon until a valid PEC has been received by the LTM4678.
Communication Protection
PEC write errors (if PEC_REQUIRED is active), attempts to access unsupported commands, or writing invalid data to supported commands will result in a CML fault. The CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_CML command, and the ALERT pin is pulled low.
DEVICE ADDRESSING
The LTM4678 offers five different types of addressing over the PMBus interface, specifically: 1) global, 2) device, 3) rail addressing and 4) alert response address (ARA).

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LTM4678

OPERATION
Global addressing provides a means of the PMBus master to address all LTM4678 devices on the bus. The LTM4678 global address is fixed 0x5A (7-bit) or 0xB4 (8-bit) and cannot be disabled. Commands sent to the global address act the same as if PAGE is set to a value of 0xFF. Commands sent are written to both channels simultaneously. Global command 0x5B (7-bit) or 0xB6 (8-bit) is paged and allows channel specific command of all LTM4678 devices on the bus. Other ADI device types may respond at one or both of these global addresses. Reading from global addresses is strongly discouraged.
Device addressing provides the standard means of the PMBus master communicating with a single instance of an LTM4678. The value of the device address is set by a combination of the ASEL configuration pin and the MFR_ ADDRESS command. When this addressing means is used, the PAGE command determines the channel being acted upon. Device addressing can be disabled by writing a value of 0x80 to the MFR_ADDRESS.
Rail addressing provides a means for the bus master to simultaneously communicate with all channels connected together to produce a single output voltage (PolyPhase). While similar to global addressing, the rail address can be dynamically assigned with the paged MFR_RAIL_ ADDRESS command, allowing for any logical grouping of channels that might be required for reliable system control. Reading from rail addresses is also strongly discouraged.
All four means of PMBus addressing require the user to employ disciplined planning to avoid addressing conflicts. Communication to LTM4678 devices at global and rail addresses should be limited to command write operations.
RESPONSES TO VOUT AND IIN/IOUT FAULTS
VOUT OV and UV conditions are monitored by comparators. The OV and UV limits are set in three ways:
n As a Percentage of the VOUT if Using the Resistor Configuration Pins
n In NVM if Either Programmed at the Factory or Through the GUI
n By PMBus Command

The IIN and IOUT overcurrent monitors are performed by ADC readings and calculations. Thus these values are based on average currents and can have a time latency of up to tCONVERT. The IOUT calculation accounts for the DCR and their temperature coefficient. The input current is equal to the voltage measured across the RSENSE resistor divided by the resistors value as set with the MFR_RVIN command. If this calculated input current exceeds the IN_OC_WARN_LIMIT the ALERT pin is pulled low and the IIN_OC_WARN bit is asserted in the STATUS_INPUT command.
The digital processor within the LTM4678 provides the ability to ignore the fault, shut down and latch off or shut down and retry indefinitely (hiccup). The retry interval is set in MFR_RETRY_ DELAY and can be from 120ms to 83.88 seconds in 1ms increments. The shutdown for OV/UV and OC can be done immediately or after a user selectable deglitch time.
Output Overvoltage Fault Response
A programmable overvoltage comparator (OV) guards against transient overshoots as well as long-term overvoltages at the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on. However, the reverse output current is monitored while device is in OV fault. When it reaches the limit, both top and bottom MOSFETs are turned off. The top and bottom MOSFETs will keep their state until the overvoltage condition is cleared regardless of the PMBus VOUT_OV_FAULT_RESPONSE command byte value. This hardware level fault response delay is typically 2µs from the overvoltage condition to BG asserted high. Using the VOUT_OV_FAULT_RESPONSE command, the user can select any of the following behaviors:
n OV Pull-Down Only (OV Cannot Be Ignored)
n Shut Down (Stop Switching) Immediately--Latch Off
n Shut Down Immediately--Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY
Either the Latch Off or Retry fault responses can be deglitched in increments of (0-7) · 10µs. See Table 14.

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LTM4678

OPERATION

Output Undervoltage Response
The response to an undervoltage comparator output can be the following:
n Ignore
n Shut Down Immediately--Latch Off
n Shut Down Immediately--Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY.
The UV responses can be deglitched. See Table 15.
Peak Output Overcurrent Fault Response
Due to the current mode control algorithm, peak output current across the inductor is always limited on a cycle-bycycle basis. The value of the peak current limit is specified in Electrical Characteristics table. The current limit circuit operates by limiting the COMPn maximum voltage. Since internal DCR sensing is used, the COMPn maximum voltage has a temperature dependency directly proportional to the TC of the DCR of the inductor. The LTM4678 automatically monitors the external temperature sensors and modifies the maximum allowed COMPn to compensate for this term. The IOUT_OC_FAULT_LIMIT section provides data points for IOUT Limiting on page 89.
The overcurrent fault processing circuitry can execute the following behaviors:
n Current Limit Indefinitely
n Shut Down Immediately--Latch Off
n Shut Down Immediately--Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY.
The overcurrent responses can be deglitched in increments of (0-7) · 16ms. See Table 16.
RESPONSES TO TIMING FAULTS
TON_MAX_FAULT_LIMIT is the time allowed for VOUT to rise and settle at start-up. The TON_MAX_FAULT_LIMIT condition is predicated upon detection of the VOUT_UV_ FAULT_LIMIT as the output is undergoing a SOFT_START sequence. The TON_MAX_ FAULT_LIMIT time is started after TON_DELAY has been reached and a SOFT_START

sequence is started. The resolution of the TON_MAX_ FAULT_LIMIT is 10µs. If the VOUT_UV_FAULT _LIMIT is not reached within the TON_MAX_FAULT_LIMIT time, the response of this fault is determined by the value of the TON_MAX_FAULT_RESPONSE command value. This response may be one of the following:
n Ignore
n Shut Down (Stop Switching) Immediately--Latch Off
n Shut Down Immediately--Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY.
This fault response is not deglitched. A value of 0 in TON_MAX_FAULT_LIMIT means the fault is ignored. The TON_MAX_FAULT_LIMIT should be set longer than the TON_RISE time. It is recommended TON_MAX_FAULT_ LIMIT always be set to a non-zero value, otherwise the output may never come up and no flag will be set to the user. See Table 18.
RESPONSES TO VIN OV FAULTS
VIN overvoltage is measured with the ADC. The response is naturally deglitched by the 100ms typical response time of the ADC. The fault responses are:
n Ignore
n Shut Down Immediately--Latch Off
n Shut Down Immediately--Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. See Table 18.
RESPONSES TO OT/UT FAULTS
Internal Overtemperature Fault Response
An internal temperature sensor protects against NVM damage. Above 85°C, no writes to NVM are recommended. Above 130°C, the internal overtemperature warn threshold is exceeded and the part disables the NVM and does not reenable until the temperature has dropped to 125°C. When the die temperature exceed 160°C the internal temperature fault response is enabled and the PWM is disabled until the die temperature drops below 150°C. Temperature is measured by the ADC. Internal temperature faults cannot

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LTM4678

OPERATION
be ignored. Internal temperature limits cannot be adjusted by the user. See Table 17.
External Overtemperature and Undertemperature Fault Response
Two internal temperature sensors are used to sense the temperature of critical circuit elements like inductors and power MOSFETs on each channel. The OT_FAULT_ RESPONSE and UT_FAULT_ RESPONSE commands are used to determine the appropriate response to an overtemperature and under temperature condition, respectively. If no external sense elements are used (not recommended) set the UT_FAULT_ RESPONSE to ignore--and set the UT_FAULT_LIMIT to 275°C. The fault responses are:
n Ignore
n Shut Down Immediately--Latch Off
n Shut Down Immediately--Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY. See Table 18.
RESPONSES TO INPUT OVERCURRENT AND OUTPUT UNDERCURRENT FAULTS Input overcurrent and output undercurrent are measured with the ADC. The fault responses are:
n Ignore
n Shut Down Immediately--Latch Off
n Shut Down Immediately--Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY.
RESPONSES TO EXTERNAL FAULTS
When either FAULTn pin is pulled low, the OTHER bit is set in the STATUS_WORD command, the appropriate bit is set in the STATUS_MFR_SPECIFIC command, and the ALERT pin is pulled low. Responses are not deglitched. Each channel can be configured to ignore or shut down then retry in response to its FAULTn pin going low by modifying the MFR_FAULT_RESPONSE command. To avoid the ALERT pin asserting low when FAULT is pulled low, assert bit 1 of MFR_CHAN_CONFIG, or mask the ALERT using the SMBALERT_MASK command.

FAULT LOGGING
The LTM4678 has fault logging capability. Data is logged into memory in the order shown in Table 19. The data is stored in a continuously updated buffer in RAM. When a fault event occurs, the fault log buffer is copied from the RAM buffer into NVM. Fault logging is allowed at temperatures above 85°C; however, retention of 10 years is not guaranteed. When the die temperature exceeds 130°C the fault logging is delayed until the die temperature drops below 125°C. The fault log data remains in NVM until a MFR_FAULT _LOG_CLEAR command is issued. Issuing this command re-enables the fault log feature. Before re-enabling fault log, be sure no faults are present and a CLEAR_FAULTS command has been issued.
When the LTM4678 powers-up or exits its reset state, it checks the NVM for a valid fault log. If a valid fault log exists in NVM, the "Valid Fault Log" bit in the STATUS_ MFR_SPECIFIC command will be set and an ALERT event will be generated. Also, fault logging will be blocked until the LTM4678 has received a MFR_FAULT_LOG_CLEAR command before fault logging will be re-enabled.
The information is stored in EEPROM in the event of any fault that disables the controller on either channel. A FAULTn being externally pulled low will not trigger a fault logging event.
BUS TIMEOUT PROTECTION
The LTM4678 implements a timeout feature to avoid persistent faults on the serial interface. The data packet timer begins at the first START event before the device address write byte. Data packet information must be completed within 30ms or the LTM4678 will three-state the bus and ignore the given data packet. If more time is required, assert bit 3 of MFR_CONFIG_ALL to allow typical bus timeouts of 255ms. Data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read (if a read operation), all data bytes and the PEC byte if applicable.
The LTM4678 allows longer PMBus timeouts for block read data packets. This timeout is proportional to the length of the block read. The additional block read timeout applies

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LTM4678

OPERATION
primarily to the MFR_FAULT_LOG command. The timeout period defaults to 32ms.
The user is encouraged to use as high a clock rate as possible to maintain efficient data packet transfer between all devices sharing the serial bus interface. The LTM4678 supports the full PMBus frequency range from 10kHz to 400kHz.
SIMILARITY BETWEEN PMBus, SMBus AND I2C 2-WIRE INTERFACE
The PMBus 2-wire interface is an incremental extension of the SMBus. SMBus is built upon I2C with some minor differences in timing, DC parameters and protocol. The PMBus/SMBus protocols are more robust than simple I2C byte commands because PMBus/SMBus provide timeouts to prevent persistent bus errors and optional packet error checking (PEC) to ensure data integrity. In general, a master device that can be configured for I2C communication can be used for PMBus communication with little or no change to hardware or firmware. Repeat start (restart) is not supported by all I2C controllers but is required for SMBus/PMBus reads. If a general purpose I2C controller is used, check that repeat start is supported.
The LTM4678 supports the maximum SMBus clock speed of 100kHz and is compatible with the higher speed PMBus specification (between 100kHz and 400kHz) if MFR_ COMMON polling or clock stretching is enabled. For robust communication and operation refer to the Note section in the PMBus Command Summary. Clock stretching is enabled by asserting bit 1 of MFR_CONFIG_ALL.
For a description of the minor extensions and exceptions PMBus makes to SMBus, refer to PMBus Specification Part 1 Revision 1.2: Paragraph 5: Transport.
For a description of the differences between SMBus and I2C, refer to System Management Bus (SMBus) Specification Version 2.0: Appendix B--Differences Between SMBus and I2C.

PMBus SERIAL DIGITAL INTERFACE
The LTM4678 communicates with a host (master) using the standard PMBus serial bus interface. The Timing Diagram, Figure 6, shows the timing relationship of the signals on the bus. The two-bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The LTM4678 is a slave device. The master can communicate with the LTM4678 using the following formats:
n Master Transmitter, Slave Receiver
n Master Receiver, Slave Transmitter
The following PMBus protocols are supported:
n Write Byte, Write Word, Send Byte
n Read Byte, Read Word, Block Read, Block Write
n Alert Response Address
Figure 7 to Figure 24 illustrate the aforementioned PMBus protocols. All transactions support PEC and GCP (group command protocol). The Block Read supports 255 bytes of returned data. For this reason, the PMBus timeout may be extended when reading the fault log.
Figure 7 is a key to the protocol diagrams in this section. PEC is optional.
A value shown below a field in the following figures is mandatory value for that field.
The data formats implemented by PMBus are:
n Master transmitter transmits to slave receiver. The transfer direction in this case is not changed.
n Master reads slave immediately after the first byte. At the moment of the first acknowledgment (provided by the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter.
n Combined format. During a change of direction within a transfer, the master repeats both a start condition and the slave address but with the R/W bit reversed. In this case, the master receiver terminates the transfer by generating a NACK on the last byte of the transfer and a STOP condition.

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LTM4678
OPERATION
Refer to Figure 7 for a legend. Handshaking features are included to ensure robust system communication. Please refer to the PMBus Communication and Command Processing subsection of the Applications Information section for further details.

SDA

tLOW

SCL
tHD(STA)
START CONDITION

tSU(DAT)

tHD(SDA)

tHD(DAT)

tHIGH

tSU(STA)
REPEATED START CONDITION

Figure 6. PMBus Timing Diagram

tSP

tBUF

tSU(STO)

STOP CONDITION

4678 F06
START CONDITION

Table 6. Abbreviations of Supported Data Formats

PMBus

SPECIFICATION

ADI

TERMINOLOGY REFERENCE TERMINOLOGY

L11 Linear

Part II ¶7.1 Linear_5s_11s

L16 Linear VOUT_ MODE
CF DIRECT

Part II ¶8.2 Part II ¶7.2

Linear_16u Varies

Reg Register Bits

Part II ¶10.3

Reg

ASC Text Characters Part II ¶22.2.1

ASCII

DEFINITION
Floating point 16-bit data: value = Y · 2N, where N = b[15:11] and Y = b[10:0], both two's compliment binary integers
Floating point 16-bit data: value = Y · 212, where Y = b[15:0], an unsigned integer
16-bit data with a custom format defined in the detailed PMBus command description
Per-bit meaning defined in detailed PMBus command description
ISO/IEC 8859-1 [A05]

EXAMPLE b[15:0] = 0x9807 = 10011_000_0000_0111 value = 7 · 213 = 854E-6
b[15:0] = 0x4C00 = 0100_1100_0000_0000 value = 19456 · 212 = 4.75 Often an unsigned or two's compliment integer PMBus STATUS_BYTE command
ADI (0x4C5443)

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Figure 7 to Figure 24 PMBus Protocols

S START CONDITION Sr REPEATED START CONDITION Rd READ (BIT VALUE OF 1) Wr WRITE (BIT VALUE OF 0) A ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK) P STOP CONDITION PEC PACKET ERROR CODE
MASTER TO SLAVE

SLAVE TO MASTER ... CONTINUATION OF PROTOCOL

4678 F07

Figure 7. PMBus Packet Protocol Diagram Element Key

1 11

S SLAVE ADDRESS Rd/Wr A P
4678 F08

Figure 8. Quick Command Protocol

S SLAVE ADDRESS Wr A COMMAND CODE A P
4678 F09

Figure 9. Send Byte Protocol

S SLAVE ADDRESS Wr A COMMAND CODE A

PEC

Figure 10. Send Byte Protocol with PEC

11 AP
4678 F10

S SLAVE ADDRESS Wr A COMMAND CODE A

8 DATA BYTE

Figure 11. Write Byte Protocol

11 AP
4678 F11

S SLAVE ADDRESS Wr A COMMAND CODE A DATA BYTE A

PEC

Figure 12. Write Byte Protocol with PEC

11 AP
4678 F12

LTM4678

S SLAVE ADDRESS Wr A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A P

4678 F13
Figure 13. Write Word Protocol

S SLAVE ADDRESS Wr A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A

PEC

4678 F14
Figure 14. Write Word Protocol with PEC

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LTM4678

OPERATION

S SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A

Figure 15. Read Byte Protocol

8 DATA BYTE

11 AP
4678 F15

S SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A DATA BYTE A

Figure 16. Read Byte Protocol with PEC

PEC

11 AP
4678 F16

S SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A DATA BYTE LOW A DATA BYTE HIGH A P

4678 F17

Figure 17. Read Word Protocol

S SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A DATA BYTE LOW A DATA BYTE HIGH A

PEC

4678 F18

Figure 18. Read Word Protocol with PEC

S SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A BYTE COUNT = N A ...

1...

DATA BYTE 1 A DATA BYTE 2 A ... DATA BYTE N A P

4678 F19

Figure 19. Block Read Protocol

S SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A BYTE COUNT = N A ...

1...

DATA BYTE 1 A DATA BYTE 2 A ... DATA BYTE N A

PEC

Figure 20. Block Read Protocol with PEC

11 AP
4678 F20

Rev. A

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OPERATION

S SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A

8 DATA BYTE 1

1 A...

8 DATA BYTE 2

A ... DATA BYTE M

1 A...

Sr SLAVE ADDRESS Rd A BYTE COUNT = N A

8 DATA BYTE 1

11 A...

8 DATA BYTE 2

1... A...

8 DATA BYTE N

11 AP
4678 F21

Figure 21. Block Write Block Read Process Call

LTM4678

S SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A

8 DATA BYTE 1

1 A...

8 DATA BYTE 2

1 A...

DATA BYTE M A ...

Sr SLAVE ADDRESS Rd A BYTE COUNT = N A

8 DATA BYTE 1

11 A...

1...

DATA BYTE 2 A ... DATA BYTE N A

8 PEC

11 AP
4678 F22

Figure 22. Block Write Block Read Process Call with PEC

ALERT RESPONSE ADDRESS

DEVICE ADDRESS

4678 F23

Figure 23. Alert Response Address Protocol

ALERT RESPONSE ADDRESS

DEVICE ADDRESS

PEC

4678 F24

Figure 24. Alert Response Address Protocol with PEC

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Rev. A
43

LTM4678

PMBus COMMAND SUMMARY
PMBus COMMANDS
Table 7 lists supported PMBus commands and manufacturer specific commands. A complete description of these commands can be found in the "PMBus Power System Mgt Protocol Specification Part II Revision 1.2". Users are encouraged to reference this specification. Exceptions or manufacturer specific implementations are listed in Table 7. Floating point values listed in the "DEFAULT VALUE" column are either Linear 16-bit Signed (PMBus Section 8.3.1) or Linear_5s_11s (PMBus Section 7.1) format, whichever is appropriate for the command. All commands from 0xD0 through 0xFF not listed in Table 7 are implicitly reserved by the manufacturer. Users should avoid blind writes within this range of commands to avoid undesired operation of the part. All commands from 0x00 through 0xCF not listed in Table 7 are implicitly not supported by

the manufacturer. Attempting to access non-supported or reserved commands may result in a CML command fault event. All output voltage settings and measurements are based on the VOUT_MODE setting of 0x14. This translates to an exponent of 212.
If PMBus commands are received faster than they are being processed, the part may become too busy to handle new commands. In these circumstances the part follows the protocols defined in the PMBus Specification v1.2, Part II, Section 10.8.7, to communicate that it is busy. The part includes handshaking features to eliminate busy errors and simplify error handling software while ensuring robust communication and system behavior. Please refer to the subsection titled PMBus Communication and Command Processing in the Applications Information section for further details.

Table 7. PMBus Commands Summary (Note: The Data Format Abbreviations are Detailed in Table 8)

COMMAND NAME PAGE OPERATION ON_OFF_CONFIG CLEAR_FAULTS PAGE_PLUS_WRITE PAGE_PLUS_READ WRITE_PROTECT STORE_USER_ALL RESTORE_USER_ALL CAPABILITY SMBALERT_MASK VOUT_MODE VOUT_COMMAND VOUT_MAX

CMD CODE DESCRIPTION

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE PAGE

0x00 Provides integration with multi-page PMBus devices.

R/W Byte N

Reg

0x00

0x01 Operating mode control. On/off, margin R/W Byte Y

Reg

high and margin low.

0x80

0x02 RUN pin and PMBus bus on/off command R/W Byte Y

Reg

configuration.

0x1E

0x03 Clear any fault bits that have been set.

Send Byte N

105

0x05 Write a command directly to a

W Block N

specified page.

0x06 Read a command directly from a

Block R/W N

specified page.

0x10 Level of protection provided by the device R/W Byte N

Reg

against accidental changes.

0x00

0x15 Store user operating memory to EEPROM. Send Byte N

115

0x16 Restore user operating memory from EEPROM.

Send Byte N

116

0x19 Summary of PMBus optional communication R Byte

Reg

protocols supported by this device.

0xB0 104

0x1B Mask ALERT activity

Block R/W Y

Reg

0x20 Output voltage format and exponent (212). R Byte

Reg

Y See CMD 105

212

0x14

0x21 Nominal output voltage set point.

R/W Word Y

L16

1.0

0x1000

0x24 Upper limit on the commanded output

R/W Word Y

L16

3.6

voltage including VOUT_MARGIN_HI.

0x399A

Rev. A

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LTM4678

PMBus COMMAND SUMMARY

COMMAND NAME

CMD CODE DESCRIPTION

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE PAGE

VOUT_MARGIN_HIGH

0x25 Margin high output voltage set point. Must R/W Word Y

L16

1.05

be greater than VOUT_COMMAND.

0x10CD

VOUT_MARGIN_LOW

0x26 Margin low output voltage set point. Must R/W Word Y

L16

0.95

be less than VOUT_COMMAND.

0x0F33

VOUT_TRANSITION_ RATE 0X27 Rate the output changes when VOUT commanded to a new value.

R/W Word Y

L11 V/ms Y 0.001 93 0x8042

FREQUENCY_SWITCH

0x33 Switching frequency of the controller.

R/W Word N

L11 kHz Y 350kHz 84 0xFABC

VIN_ON

0x35 Input voltage at which the unit should start R/W Word N

L11

4.75

power conversion.

0xD130

VIN_OFF

0x36 Input voltage at which the unit should stop R/W Word N

L11

4.5

power conversion.

0xD120

VOUT_OV_FAULT_LIMIT

0x40 Output overvoltage fault limit.

R/W Word Y

L16

1.1

0x119A

VOUT_OV_FAULT_ RESPONSE

0x41 Action to be taken by the device when an R/W Byte Y

Reg

output overvoltage fault is detected.

0xB8

VOUT_OV_WARN_LIMIT

0x42 Output overvoltage warning limit.

R/W Word Y

L16

Y 1.075

0x1133

VOUT_UV_WARN_LIMIT

0x43 Output undervoltage warning limit.

R/W Word Y

L16

Y 0.925

0x0ECD

VOUT_UV_FAULT_LIMIT

0x44 Output undervoltage fault limit.

R/W Word Y

L16

0.9

0x0E66

VOUT_UV_FAULT_ RESPONSE

0x45 Action to be taken by the device when an R/W Byte Y

Reg

output undervoltage fault is detected.

0xB8

IOUT_OC_FAULT_LIMIT

0x46 Output overcurrent fault limit.

R/W Word Y

L11

Y 40.00

0xE280

IOUT_OC_FAULT_ RESPONSE 0x47 Action to be taken by the device when an R/W Byte Y

Reg

output overcurrent fault is detected.

0x00

IOUT_OC_WARN_LIMIT

0x4A Output overcurrent warning limit.

R/W Word Y

L11

30.0

0xDBC0

OT_FAULT_LIMIT

0x4F External overtemperature fault limit.

R/W Word Y

L11

Y 128.0

0xF200

OT_FAULT_RESPONSE

0x50 Action to be taken by the device when an R/W Byte Y

Reg

external overtemperature fault is detected,

Y 0xB8 100

OT_WARN_LIMIT

0x51 External overtemperature warning limit. R/W Word Y

L11

Y 125.0

0xEBE8

UT_FAULT_LIMIT

0x53 External undertemperature fault limit.

R/W Word Y

L11

Y 45.0

0xE530

UT_FAULT_RESPONSE

0x54 Action to be taken by the device when an external undertemperature fault is detected.

R/W Byte Y

Reg

Y 0xB8 100

VIN_OV_FAULT_LIMIT

0x55 Input supply overvoltage fault limit.

R/W Word N

L11

15.5

0xD3E0

VIN_OV_FAULT_ RESPONSE 0x56 Action to be taken by the device when an R/W Byte Y

Reg

input overvoltage fault is detected.

0x80

VIN_UV_WARN_LIMIT

0x58 Input supply undervoltage warning limit. R/W Word N

L11

4.65

0xD12A

IIN_OC_WARN_LIMIT

0x5D Input supply overcurrent warning limit. R/W Word N

L11

10.0

0xD280

Rev. A

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LTM4678

PMBus COMMAND SUMMARY

COMMAND NAME TON_DELAY TON_RISE
TON_MAX_FAULT_LIMIT
TON_MAX_FAULT_ RESPONSE TOFF_DELAY TOFF_FALL TOFF_MAX_WARN_ LIMIT
STATUS_BYTE STATUS_WORD STATUS_VOUT STATUS_IOUT STATUS_INPUT STATUS_TEMPERATURE STATUS_CML STATUS_MFR_SPECIFIC READ_VIN READ_IIN READ_VOUT READ_IOUT READ_TEMPERATURE_1
READ_TEMPERATURE_2 READ_FREQUENCY READ_POUT READ_PIN PMBus_REVISION MFR_ID MFR_MODEL
46

CMD CODE DESCRIPTION

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE PAGE

0x60 Time from RUN and/or Operation on to output rail turn-on.

R/W Word Y

L11 ms Y

0.0

0x8000

0x61 Time from when the output starts to rise R/W Word Y until the output voltage reaches the VOUT commanded value.

L11 ms Y

3.0

0xC300

0x62 Maximum time from the start of TON_ RISE for VOUT to cross the VOUT_UV_ FAULT_LIMIT.

R/W Word Y

L11 ms Y

5.0

0xCA80

0x63 Action to be taken by the device when a R/W Byte Y

Reg

TON_ MAX_FAULT event is detected.

0xB8

0x64 Time from RUN and/or Operation off to the R/W Word Y start of TOFF_FALL ramp.

L11 ms Y

0.0

0x8000

0x65 Time from when the output starts to fall R/W Word Y until the output reaches zero volts.

L11 ms Y

3.0

0xC300

0x66 Maximum allowed time, after TOFF_FALL R/W Word Y completed, for the unit to decay below 12.5%.

L11 ms Y

0x8000

0x78 One byte summary of the unit's fault condition.

R/W Byte Y

Reg

106

0x79 Two byte summary of the unit's fault condition.

R/W Word Y

Reg

107

0x7A Output voltage fault and warning status. R/W Byte Y

Reg

107

0x7B Output current fault and warning status. R/W Byte Y

Reg

108

0x7C Input supply fault and warning status.

R/W Byte N

Reg

108

0x7D External temperature fault and warning

R/W Byte Y

Reg

status for READ_TEMERATURE_1.

109

0x7E Communication and memory fault and

R/W Byte N

Reg

warning status.

109

0x80 Manufacturer specific fault and state information.

R/W Byte Y

Reg

110

0x88 Measured input supply voltage.

R Word

L11

112

0x89 Measured input supply current.

R Word

L11

112

0x8B Measured output voltage.

R Word

L16

112

0x8C Measured output current.

R Word

L11

112

0x8D External temperature sensor temperature. R Word

L11

This is the value used for all temperature

related processing, including IOUT_CAL_

GAIN.

112

0x8E Internal die junction temperature. Does

R Word

L11

not affect any other commands.

113

0x95 Measured PWM switching frequency.

R Word

L11

113

0x96 Measured output power

R Word

L11

N/A

113

0x97 Calculated input power

R Word

L11

N/A

113

0x98 PMBus revision supported by this device. R Byte

Reg

Current revision is 1.2.

0x22 104

0x99 The manufacturer ID of the LTM4678 in

R String

ASC

ASCII.

LTC

104

0x9A Manufacturer part number in ASCII.

R String N

ASC

104
Rev. A

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LTM4678

PMBus COMMAND SUMMARY

COMMAND NAME MFR_VOUT_MAX
MFR_PIN_ACCURACY
USER_DATA_00
USER_DATA_01 USER_DATA_02
USER_DATA_03 USER_DATA_04 MFR_EE_UNLOCK MFR_EE_ERASE MFR_EE_DATA MFR_CHAN_CONFIG
MFR_CONFIG_ALL MFR_FAULT_ PROPAGATE
MFR_PWM_COMP MFR_PWM_MODE MFR_FAULT_RESPONSE
MFR_OT_FAULT_ RESPONSE
MFR_IOUT_PEAK
MFR_ADC_CONTROL
MFR_RETRY_DELAY

CMD CODE DESCRIPTION
0xA5 Maximum allowed output voltage including VOUT_OV_FAULT_LIMIT.
0xAC Returns the accuracy of the READ_PIN command
0xB0 OEM RESERVED. Typically used for part serialization.
0xB1 Manufacturer reserved for LTpowerPlay.
0xB2 OEM RESERVED. Typically used for part serialization
0xB3 An NVM word available for the user.
0xB4 An NVM word available for the user.
0xBD Contact factory.
0xBE Contact factory.
0xBF Contact factory.
0xD0 Configuration bits that are channel specific.
0xD1 General configuration bits.
0xD2 Configuration that determines which faults are propagated to the FAULT pin.
0xD3 PWM loop compensation configuration
0xD4 Configuration for the PWM engine.
0xD5 Action to be taken by the device when the FAULT pin is externally asserted low.
0xD6 Action to be taken by the device when an internal overtemperature fault is detected.
0xD7 Report the maximum measured value of READ_ IOUT since last MFR_CLEAR_ PEAKS.
0xD8 ADC telemetry parameter selected for repeated fast ADC read back
0xDB Retry interval during FAULT retry mode.

MFR_RESTART_DELAY

0xDC Minimum time the RUN pin is held low by the LTM4678.

MFR_VOUT_PEAK

0xDD Maximum measured value of READ_VOUT since last MFR_CLEAR_PEAKS.

MFR_VIN_PEAK

0xDE Maximum measured value of READ_VIN since last MFR_CLEAR_PEAKS.

MFR_TEMPERATURE_1_ PEAK 0xDF Maximum measured value of external Temperature (READ_TEMPERATURE_1) since last MFR_CLEAR_PEAKS.

MFR_READ_IIN_PEAK

0xE1 Maximum measured value of READ_IIN command since last MFR_CLEAR_PEAKS

MFR_CLEAR_PEAKS

0xE3 Clears all peak values.

MFR_READ_ICHIP MFR_PADS

0xE4 Measured supply current of the SVIN pin 0xE5 Digital status of the I/O pads.

TYPE R Word R Byte R/W Word R/W Word R/W Word R/W Word R/W Word
R/W Byte R/W Byte R/W Word R/W Byte R/W Byte R/W Byte
R Byte R Word
R/W Byte R/W Word R/W Word
R Word R Word R Word
R Word Send Byte R Word R Word

PAGED Y N N Y N Y N
Y N Y Y Y Y N Y
N Y Y Y N Y
N N N N

DATA FORMAT UNITS NVM

L16

Reg

L11

Reg

L11 ms Y

L16

L11

Reg

DEFAULT VALUE
3.6 0x399A 5.0%
NA
NA NA
0x0000 0x0000
0x1D
0x21 0x6993
0x28 0xC7 0xC0
0xC0
NA
0x00
250.0 0xF3E8 150.0 0xF258
NA
NA
NA
NA
NA NA NA

PAGE 88
113
103
103 103
103 103 120 120 120 78
79 101
82 81 99
99
113
114
94
94
113
113
114
114
106 114 110

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Rev. A
47

LTM4678

PMBus COMMAND SUMMARY

COMMAND NAME MFR_ADDRESS

CMD CODE DESCRIPTION
0xE6 Sets the 7-bit I2C address byte.

TYPE R/W Byte

DATA PAGED FORMAT UNITS NVM

Reg

DEFAULT VALUE
0x4F

PAGE 78

MFR_SPECIAL_ID

0xE7 Manufacturer code representing the LTM4678 and revision

R Word

Reg

0x4100 104

MFR_IIN_CAL_GAIN

0xE8 The resistance value of the input current R/W Word N sense element in m.

L11 m Y

2.0

0xC200

MFR_FAULT_LOG_ STORE 0xEA Command a transfer of the fault log from Send Byte N RAM to EEPROM.

117

MFR_INFO

0x Contact factory.

119

MFR_IOUT_CAL_GAIN

0x SET AT FACTORY

MFR_FAULT_LOG_ CLEAR 0xEC Initialize the EEPROM block reserved for Send Byte N fault logging.

120

MFR_FAULT_LOG

0xEE Fault log data bytes.

R Block

Reg

116

MFR_COMMON

0xEF Manufacturer status bits that are common R Byte

Reg

across multiple ADI chips.

111

MFR_COMPARE_USER_ ALL 0xF0 Compares current command contents with NVM.

Send Byte N

116

MFR_TEMPERATURE_2_ PEAK 0xF4 Peak internal die temperature since last

R Word

L11

MFR_ CLEAR_PEAKS.

114

MFR_PWM_CONFIG

0xF5 Set numerous parameters for the DC/DC R/W Byte N

Reg

controller including phasing.

0x10

MFR_IOUT_CAL_GAIN_ TC 0xF6 Temperature coefficient of the current sensing element.

R/W Word Y

CF ppm/ Y

3800

°C

0x0ED8

MFR_ICHIP_CAL_GAIN

0xF7 The resistance value of the VIN pin filter R/W Word N element in m.

L11 m Y

1000

0x03E8

MFR_TEMP_1_GAIN

0xF8 Sets the slope of the external temperature R/W Word Y

sensor.

Y 0.995 91 0x3FAE

MFR_TEMP_1_OFFSET

0xF9 Sets the offset of the external temperature R/W Word Y

L11

0.0

sensor with respect to 273.1°C

0x8000

MFR_RAIL_ADDRESS

0xFA Common address for PolyPhase outputs R/W Byte Y

Reg

to adjust common parameters.

0x80

MFR_REAL_TIME

0xFB 48-bit share-clock counter value.

R Block

104

MFR_RESET

0xFD Commanded reset without requiring a power down.

Send Byte N

Note 1: Commands indicated with Y in the NVM column indicate that these commands are stored and restored using the STORE_USER_ALL and RESTORE_USER_ALL commands, respectively.

Note 2: Commands with a default value of NA indicate "not applicable". Commands with a default value of FS indicate "factory set on a per part basis".

Note 3: The LTM4678 contains additional commands not listed in Table 7. Reading these commands is harmless to the operation of the IC; however, the contents and meaning of these commands can change without notice.

Note 4: Some of the unpublished commands are read-only and will generate a CML bit 6 fault if written.

Note 5: Writing to commands not published in Table 7 is not permitted.

Note 6: The user should not assume compatibility of commands between different parts based upon command names. Always refer to the manufacturer's data sheet for each part for a complete definition of a command's function. ADI strives to keep command functionality compatible between all ADI devices. Differences may occur to address specific product requirements.

Rev. A

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LTM4678

PMBus COMMAND SUMMARY

Table 8. Data Format Abbreviations

L11

Linear_5s_11s PMBus data field b[15:0]

Value = Y · 2N

where N = b[15:11] is a 5-bit two's complement integer and Y = b[10:0] is an 11-bit two's complement integer

Example:

For b[15:0] = 0x9807 = `b10011_000_0000_0111 Value = 7 · 213 = 854 · 106

From "PMBus Spec Part II: Paragraph 7.1"

L16

Linear_16u

PMBus data field b[15:0] Value = Y · 2N where Y = b[15:0] is an unsigned integer and N = VOUT_MODE_PARAMETER is a 5-bit two's complement exponent that is hardwired to 12 decimal Example: For b[15:0] = 0x9800 = `b1001_1000_0000_0000 Value = 19456 · 212 = 4.75 From "PMBus Spec Part II: Paragraph 8.2"

Reg

PMBus data field b[15:0] or b[7:0]. Bit field meaning is defined in detailed PMBus Command Description.

L16

Integer Word

PMBus data field b[15:0]

Value = Y

where Y = b[15:0] is a 16-bit unsigned integer

Example:

For b[15:0] = 0x9807 = `b1001_1000_0000_0111

Value = 38919 (decimal)

Custom Format Value is defined in detailed PMBus Command Description.

This is often an unsigned or two's complement integer scaled by an MFR specific constant.

ASC

ASCII Format

A variable length string of text characters conforming to ISO/IEC 8859-1 standard.

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49

LTM4678

APPLICATIONS INFORMATION
VIN TO VOUT STEP-DOWN RATIOS
There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage. Each output of the LTM4678 is capable of 95% duty cycle at 500kHz, but the VIN to VOUT minimum dropout is still a function of its load current and will limit output current capability related to high duty cycle on the topside switch.
Minimum on-time tON(MIN) is another consideration in operating at a specified duty cycle while operating at a certain frequency due to the fact that tON(MIN) < D/fSW, where D is duty cycle and fSW is the switching frequency. tON(MIN) is specified in the electrical parameters as 50ns. See Note 6 in the Electrical Characteristics section for output current guideline.

INPUT CAPACITORS

The LTM4678 module should be connected to a low AC impedance DC source. For the regulator input, four 22µF input ceramic capacitors are used to handle the RMS ripple current. A 47µF to 150µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed.

For a buck converter, the switching duty-cycle can be estimated as:

VOUTn VINn

Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as:

( ) ICINn

(RMS)

IOUTn(MAX) %

Dn · 1- Dn

In the above equation, % is the estimated efficiency of the
power module. The bulk capacitor can be a switcher-rated electrolytic aluminum capacitor, or a polymer capacitor.

OUTPUT CAPACITORS
The LTM4678 is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, a low ESR polymer capacitor or ceramic capacitor. The typical output capacitance range for each output is from 400µF to 1000µF. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spikes is required. Table 13 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 0A to 12.5A step, 12A/µs transient each channel. Table 13 optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 13 matrix, and the LTPowerCAD Design Tool will be provided for stability analysis. Multiphase operation reduces effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The LTPowerCAD Design Tool can calculate the output ripple reduction as the number of implemented phases increases by N times. A small value 10 resistor can be placed in series from VOUTn to the VOSNS0+ pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. The LTM4678's stability compensation can be adjusted using two external capacitors, and the MFR_PWM_COMP commands.
LIGHT LOAD CURRENT OPERATION
The LTM4678 has two modes of operation including high efficiency, discontinuous conduction mode or forced continuous conduction mode. The mode of operation is configured by bit 0 of the MFR_PWM_MODEn command (discontinuous conduction is always the start-up mode, forced continuous is the default running mode).
If a channel is enabled for discontinuous mode operation, the inductor current is not allowed to reverse. The

Rev. A

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LTM4678

APPLICATIONS INFORMATION

reverse current comparator, IREV, turns off the bottom MOSFET (MBn) just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller can operate in discontinuous (pulseskipping) operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined solely by the voltage on the COMPnb pin. In this mode, the efficiency at light loads is lower than in discontinuous mode operation. However, continuous mode exhibits lower output ripple and less interference with audio circuitry. Forced continuous conduction mode may result in reverse inductor current, which can cause the input supply to boost. The VIN_OV_FAULT_LIMIT can detect this (if SVIN is connected to VIN0 and/or VIN1) and turn off the offending channel. However, this fault is based on an ADC read and can nominally take up to 100ms to detect. If there is a concern about the input supply boosting, keep the part in discontinuous conduction operation.
SWITCHING FREQUENCY AND PHASE
The switching frequency of the LTM4678's channels is established by its analog phase-locked-loop (PLL) locking on to the clock present at the module's SYNC pin. The clock waveform on the SYNC pin can be generated by the LTM4678's internal circuitry when an external pull-up resistor to 3.3V (e.g., VDD33) is provided, in combination with the LTM4678 control IC's FREQUENCY_SWITCH command being set to one of the following supported values: 250kHz, 350kHz, 425kHz, 500kHz, 575kHz, 650kHz, 750kHz. In this configuration, the module is called a "sync master": (using the factory-default setting of MFR_ CONFIG_ALL[4] = 0b), SYNC becomes a bidirectional open-drain pin, and the LTM4678 pulls SYNC logic low for nominally 500ns at a time, at the prescribed clock rate. The SYNC signal can be bused to other LTM4678 modules (configured as "sync slaves"), for purposes of synchronizing switching frequencies of multiple modules within a system--but only one LTM4678 should be configured as a "sync master"; the other LTM4678(s) should be configured as "sync slaves".
The most straightforward way is to set its FREQUENCY_ SWITCH command to 0x0000 and MFR_CONFIG_ ALL[4] = 1b. This can be easily implemented with resis-

tor pin-strap settings on the FSWPH_CFG pin (see Table 3). Using MFR_CONFIG_ALL[4] = 1b, the LTM4678s SYNC pin becomes a high impedance input, only--i.e., it does not drive SYNC low. The module synchronizes its frequency to that of the clock applied to its SYNC pin. The only shortcoming of this approach is: in the absence of an externally applied clock, the switching frequency of the module will default to the low end of its frequencysynchronization capture range (~225kHz).
If fault-tolerance to the loss of an externally applied SYNC clock is desired, the FREQUENCY_SWITCH command of a "sync slave" can be left at the nominal target switching frequency of the application, and not 0x0000. However, it is then still necessary to configure MFR_CONFIG_ ALL[4] = 1b. With this combination of configurations, the LTM4678's SYNC pin becomes a high impedance input and the module synchronizes its frequency to that of the externally applied clock, provided that the frequency of the externally applied clock exceeds ~½ of the target frequency (FREQUENCY_SWITCH). If the SYNC clock is absent, the module responds by operating at its target frequency, indefinitely. If and when the SYNC clock is restored, the module automatically phase-locks to the SYNC clock as normal. The only shortcoming of this approach is: the EEPROM must be configured per above guidance; resistor pin-strapping options on the FSWPH_CFG pin alone cannot provide fault-tolerance to the absence of the SYNC clock.
The FREQUENCY_SWITCH register can be altered via I2C commands, but only when switching action is disengaged, i.e., the module's outputs are turned off. The FREQUENCY_ SWITCH command takes on the value stored in NVM at SVIN power-up, but is overridden according to a resistor pin-strap applied between the FSWPH_CFG pin and SGND only if the module is configured to respect resistor pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 3 highlights available resistor pin-strap and corresponding FREQUENCY_SWITCH settings.
The relative phasing of all active channels in a PolyPhase rail should be optimally phased. The relative phasing of each rail is 360°/n, where n is the number of phases in the rail. MFR_PWM_CONFIG[2:0] configures channel relative phasing with respect to the SYNC pin. Phase relationship

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values are indicated with 0° corresponding to the falling edge of SYNC being coincident with the turn-on of the top MOSFETs, (MTn).
The MFR_PWM_CONFIG command can be altered via I2C commands, but only when switching action is disengaged, i.e., the module's outputs are turned off. The MFR_PWM_CONFIG command takes on the value stored in NVM at SVIN power-up, but is overridden according to a resistor pin-strap applied between the FSWPH_CFG pin and SGND only if the module is configured to respect resistor pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 3 highlights available resistor pin-strap and corresponding MFR_PWM_CONFIG[2:0] settings.
Some combinations of FREQUENCY_SWITCH and MFR_PWM_CONFIG[2:0] are not available by resistor pin-strapping the FSWPH_CFG pin. All combinations of supported values for FREQUENCY_SWITCH and MFR_PWM_CONFIG[2:0] can be configured by NVM programming--or, I2C transactions, provided switching action is disengaged, i.e., the module's outputs are turned off.
Care must be taken to minimize capacitance on SYNC to assure that the pull-up resistor versus the capacitor load has a low enough time constant for the application to form a "clean" clock. (See "Open-Drain Pins", later in this section.)
When a LTM4678 is configured as a sync slave, it is permissible for external circuitry to drive the SYNC pin from a current-limited source (less than 10mA), rather than using a pull-up resistor. Any external circuitry must not drive high with arbitrarily low impedance at SVIN powerup, because the SYNC output can be low impedance until NVM contents have been downloaded to RAM.
Recommended LTM4678 switching frequencies of operation for many common VIN-to-VOUT applications are indicated below. When the two channels of an LTM4678 are stepping input voltage(s) down to output voltages whose recommended switching frequencies below are significantly different, operation at the higher of the two recommended switching frequencies is preferable, but minimum on-time must be considered. (See Minimum On-Time Considerations section.)

Table 9. Recommended Switching Frequency for Various VINto-VOUT Step-Down Scenarios

5VIN

8VIN

12VIN

0.9VOUT

1.0VOUT

350kHz to 400kHz

1.2VOUT

1.5VOUT 1.8VOUT

450kHz to 550kHz

2.5VOUT 3.3VOUT

650kHz to 750kHz

OUTPUT CURRENT LIMIT PROGRAMMING
The cycle-by-cycle current limit threshold voltage, VIL limit is proportional to VCOMPnb, which can be programmed from 1.45V to 2.2V using the PMBus command IOUT_OC_ FAULT_LIMIT. The LTM4678 uses only the sub-milliohm sensing to detect current levels. See page 89. The LTM4678 has two ranges of current limit programming. The value of MFR_PWM_MODE[2] is reserved and the MFR_PWM_MODE[7], and IOUT_OC_FAULT_LIMIT are used to set the current limit level, see the section of the PMBus commands, the device can regulate output voltage with the peak current under the value of IOUT_OC_FAULT_LIMIT in normal operation. In case of output current exceeding that current limit, an OC fault will be issued. Each of the IOUT_OC_FAULT_LIMIT ranges will effects the loop gain, and subsequently effects the loop stability, so setting the range of current limiting is a part of loop design.
The LTPowerCAD Design Tool can be used to look at the loop stability changes if current limit is adjusted. The LTM4678 will automatically update the current limit as the inductor temperature changes. Keep in mind this operation is on a cycle-by-cycle basis and is only a function of the peak inductor current. The average inductor current is monitored by the ADC converter and can provide a warning if too much average output current is detected. The overcurrent fault is detected when the COMPnb voltage hits the maximum value. The digital processor within the LTM4678 provides the ability to either ignore the fault, shut down and latch off or shut down and retry indefinitely (hiccup). Refer to the overcurrent portion of the Operation section for more detail. The Read_POUT can be used to readback calculated output power.
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MINIMUM ON-TIME CONSIDERATIONS

Minimum on-time, tON(MIN), is the smallest time duration that the LTM4678 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that:

tON(MIN)

VOUTn VINn · fOSC

If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase.

Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0V to the commanded voltage set point. The rise time of the voltage ramp can be programmed using the TON_RISEn command to minimize inrush currents associated with the start-up voltage ramp. The soft-start feature is disabled by setting TON_RISEn to any value less than 0.250ms. The LTM4678 performs the necessary math internally to assure the voltage ramp is controlled to the desired slope. However, the voltage slope can not be any faster than the VOUTn fundamental limits of the power stage. The number of tON(MIN) steps in the ramp is proportional to TON_RISE/0.1ms.Therefore, the shorter the TON_RISEn time setting, the more discrete steps in the soft-start ramp appear.

The minimum on-time for the LTM4678 is 50ns.
VARIABLE DELAY TIME, SOFT-START AND OUTPUT VOLTAGE RAMPING
The LTM4678 must enter its run state prior to soft-start. The RUNn pins are released after the part initializes and SVIN is greater than the VIN_ON threshold. If multiple LTM4678s are used in an application, they should be configured to share the same RUNn pins. They all hold their respective RUNn pins low until all devices initialize and SVIN exceeds the VIN_ON threshold for all devices. The SHARE_CLK pin assures all the devices connected to the signal use the same time base.
After the RUNn pin releases, the controller waits for the user-specified turn-on delay (TON_DELAYn) prior to initiating an output voltage ramp. Multiple LTM4678s and other ADI parts can be configured to start with variable delay times. To work correctly, all devices use the same timing clock (SHARE_CLK) and all devices must share the RUNn pin.
This allows the relative delay of all parts to be synchronized. The actual variation in the delay will be dependent on the highest clock rate of the devices connected to the SHARE_CLK pin (all Analog Devices ICs are configured to allow the fastest SHARE_CLK signal to control the timing of all devices). The SHARE_CLK signal can be ±10% in frequency, thus the actual time delays will have some variance.

The LTM4678 PWM always operates in discontinuous mode during the TON_RISEn operation. In discontinuous mode, the bottom MOSFET (MBn) is turned off as soon as reverse current is detected in the inductor. This allows the regulator to start up into a pre-biased load.
There is no analog tracking feature in the LTM4678; however, two outputs can be given the same TON_RISEn and TON_DELAYn times to achieve ratiometric rail tracking. Because the RUNn pins are released at the same time and both units use the same time base (SHARE_CLK), the outputs track very closely. If the circuit is in a PolyPhase configuration, all timing parameters must be the same.
DIGITAL SERVO MODE
For maximum accuracy in the regulated output voltage, enable the digital servo loop by asserting bit 6 of the MFR_PWM_MODE command. In digital servo mode, the LTM4678 will adjust the regulated output voltage based on the ADC voltage reading. Every 90ms the digital servo loop will step the LSB of the DAC (nominally 1.375mV or 0.688mV depending on the voltage range bit) until the output is at the correct ADC reading. At power-up this mode engages after TON_MAX_FAULT_LIMIT unless the limit is set to 0 (infinite). If the TON_MAX_FAULT_LIMIT is set to 0 (infinite), the servo begins after TON_RISE is complete and VOUT has exceeded the VOUT_UV_FAULT_LIMIT. This same point in time is when the output changes from
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discontinuous to the programmed mode as indicated in MFR_PWM_MODE bit 0. Refer to Figure 25 for details on the VOUT waveform under time-based sequencing. If the TON_MAX_FAULT_LIMIT is set to a value greater than 0 and the TON_MAX_FAULT_RESPONSE is set to ignore 0x00, the servo begins:
1. After the TON_RISE sequence is complete
2. After the TON_MAX_FAULT_LIMIT time is reached; and
3. After the VOUT_UV_FAULT_LIMIT has been exceed or the IOUT_OC_FAULT_LIMIT is no longer active.
If the TON_MAX_FAULT_LIMIT is set to a value greater than 0 and the TON_MAX_FAULT_RESPONSE is not set to ignore 0x00, the servo begins:
1. After the TON_RISE sequence is complete
2. After the TON_MAX_FAULT_LIMIT time has expired and both VOUT_UV_FAULT and IOUT_OC_FAULT are not present.
The maximum rise time is limited to 1.3 seconds.
In a PolyPhase configuration it is recommended only one of the control loops have the digital servo mode enabled. This will assure the various loops do not work against each other due to slight differences in the reference circuits.

SOFT OFF (SEQUENCED OFF)
In addition to a controlled start-up, the LTM4678 also supports controlled turn-off. The TOFF_DELAY and TOFF_FALL functions are shown in Figure 26. TOFF_FALL is processed when the RUN pin goes low or if the part is commanded off. If the part faults off or FAULTn is pulled low externally and the part is programmed to respond to this, the output will three-state rather than exhibiting a controlled ramp. The output will decay as a function of the load. The output voltage will operate as shown in Figure 26 as long as the part is in forced continuous mode and the TOFF_FALL time is sufficiently slow that the power stage can achieve the desired slope. The TOFF_FALL time can only be met if the power stage and controller can sink sufficient current to assure the output is at zero volts by the end of the fall time interval. If the TOFF_FALL time is set shorter than the time required to discharge the load capacitance, the output will not reach the desired zero volt state. At the end of TOFF_FALL, the controller will cease to sink current and VOUT will decay at the natural rate determined by the load impedance. If the controller is in discontinuous mode, the controller will not pull negative current and the output will be pulled low by the load, not the power stage. The maximum fall time is limited to 1.3 seconds. The shorter TOFF_FALL time is set, the larger the discrete steps in the TOFF_FALL ramp will appear. The number of steps in the ramp is equal to TOFF_FALL/0.1ms.

DIGITAL SERVO

MODE ENABLED FINAL OUTPUT

TON_MAX_FAULT_LIMIT

VOLTAGE REACHED

VOUT

DAC VOLTAGE ERROR (NOT TO SCALE)

TIME DELAY OF 200-400ms

VOUT

TON_DELAY

TON_RISE

TIME

4678 F25

Figure 25. Timing Controlled VOUT Rise

TOFF_DELAY

TOFF_FALL

TIME

4678 F26

Figure 26. TOFF_DELAY and TOFF_FALL

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UNDERVOLTAGE LOCKOUT
The LTM4678 is initialized by an internal threshold-based UVLO where VIN must be approximately 4V and INTVCC, VDD33, and VDD25 must be within approximately 20% of their regulated values. In addition, VDD33 must be within approximately 7% of the targeted value before the RUN pin is released. After the part has initialized, an additional comparator monitors VIN. The VIN_ON threshold must be exceeded before the power sequencing can begin. When VIN drops below the VIN_OFF threshold, the SHARE_CLK pin will be pulled low and VIN must increase above the VIN_ON threshold before the controller will restart. The normal start-up sequence will be allowed after the VIN_ON threshold is crossed. If FAULTn is held low when VIN is applied, ALERT will be asserted low even if the part is programmed to not assert ALERT when FAULTn is held low. If I2C communication occurs before the LTM4678 is out of reset and only a portion of the command is seen by the part, this can be interpreted as a CML fault. If a CML fault is detected, ALERT is asserted low.
It is possible to program the contents of the NVM in the application if the VDD33 supply is externally driven directly to VDD33 or through EXTVCC. This will activate the digital portion of the LTM4678 without engaging the high voltage sections. PMBus communications are valid in this supply configuration. If VIN has not been applied to the LTM4678, bit 3 (NVM Not Initialized) in MFR_COMMON will be asserted low. If this condition is detected, the part will only respond to addresses 5A and 5B. To initialize the part issue the following set of commands: global address 0x5B command 0xBD data 0x2B followed by global address 5B command 0xBD and data 0xC4. The part will now respond to the correct address. Configure the part as desired then issue a STORE_USER_ALL. When VIN is applied a MFR_RESET command must be issued to allow the PWM to be enabled and valid ADC conversions to be read.
FAULT DETECTION AND HANDLING
The LTM4678 FAULT pins are configurable to indicate a variety of faults including OV, UV, OC, OT, timing faults, and peak over current faults. In addition, the FAULT pins

can be pulled low by external sources indicating a fault in some other portion of the system. The fault response is configurable and allows the following options:
n Ignore
n Shut Down Immediately--Latch Off
n Shut Down Immediately--Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY
Refer to the PMBus section of the data sheet and the PMBus specification for more details.
The OV response is automatic. If an OV condition is detected, TGn goes low and BGn is asserted.
Fault logging is available on the LTM4678. The fault logging is configurable to automatically store data when a fault occurs that causes the unit to fault off. The header portion of the fault logging table contains peak values. It is possible to read these values at any time. This data will be useful while troubleshooting the fault.
If the LTM4678 internal temperature is in excess of 85°C, writes into the NVM (other than fault logging) are not recommended. The data will still be held in RAM, unless the 3.3V supply UVLO threshold is reached. If the die temperature exceeds 130°C all NVM communication is disabled until the die temperature drops below 120°C.
OPEN-DRAIN PINS
The LTM4678 has the following open-drain pins:
3.3V Pins
1. FAULTn
2. SYNC
3. SHARE_CLK
4. PGOODn
5V Pins (5V pins operate correctly when pulled to 3.3V.)
1. RUNn
2. ALERT
3. SCL
4. SDA

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All the above pins have on-chip pull-down transistors that can sink 3mA at 0.4V. The low threshold on the pins is 0.8V; thus, there is plenty of margin on the digital signals with 3mA of current. For 3.3V pins, 3mA of current is a 1.1k resistor. Unless there are transient speed issues associated with the RC time constant of the resistor pullup and parasitic capacitance to ground, a 10k resistor or larger is generally recommended.

For high speed signals such as the SDA, SCL and SYNC, a lower value resistor may be required. The RC time constant should be set to 1/3 to 1/5 the required rise time to avoid timing issues. For a 100pF load and a 400kHz PMBus communication rate, the rise time must be less than 300ns. The resistor pull-up on the SDA and SCL pins with the time constant set to 1/3 the rise time is:

RPULLUP

tRISE 3 ·100pF

The closest 1% resistor value is 1k. Be careful to minimize parasitic capacitance on the SDA and SCL pins to avoid communication problems. To estimate the loading capacitance, monitor the signal in question and measure how long it takes for the desired signal to reach approximately 63% of the output value. This is a one time constant. The SYNC pin has an on-chip pull-down transistor with the output held low for nominally 500ns. If the internal oscillator is set for 500kHz and the load is 100pF and a 3x time constant is required, the resistor calculation is as follows:

RPULLUP

2µs 3·

500ns 100pF

The closest 1% resistor is 4.99k.
If timing errors are occurring or if the SYNC frequency is not as fast as desired, monitor the waveform and determine if the RC time constant is too long for the application. If possible reduce the parasitic capacitance. If not, reduce the pull-up resistor sufficiently to assure proper timing. The SHARE_CLK pull-up resistor has a similar equation with a period of 10µs and a pull-down time of 1µs. The RC time constant should be approximately 3µs or faster.

PHASE-LOCKED LOOP AND FREQUENCY SYNCHRONIZATION
The LTM4678 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. The PLL is locked to the falling edge of the SYNC pin. The phase relationship between the PWM controller and the falling edge of SYNC is controlled by the lower 3 bits of the MFR_PWM_ CONFIG command. For PolyPhase applications, it is recommended that all the phases be spaced evenly. Thus for a 2-phase system the signals should be 180° out of phase and a 4-phase system should be spaced 90°.
The phase detector is an edge-sensitive digital type that provides a known phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complementary current sources that charge or discharge the internal filter network. The PLL lock range is guaranteed between 200kHz and 1MHz. Nominal parts will have a range beyond this; however, operation to a wider frequency range is not guaranteed.
The PLL has a lock detection circuit. If the PLL should lose lock during operation, bit 4 of the STATUS_MFR_SPECIFIC command is asserted and the ALERT pin is pulled low. The fault can be cleared by writing a 1 to the bit. If the user does not wish to see the ALERT pin assert if a PLL_FAULT occurs, the SMBALERT_MASK command can be used to prevent the alert.
If the SYNC signal is not clocking in the application, the nominal programmed frequency will control the PWM circuitry. However, if multiple parts share the SYNC pins and the signal is not clocking, the parts will not be synchronized and excess voltage ripple on the output may be present. Bit 10 of MFR_PADS will be asserted low if this condition exists.
If the PWM signal appears to be running at too high a frequency, monitor the SYNC pin. Extra transitions on the falling edge will result in the PLL trying to lock on to noise versus the intended signal. Review routing of digital control signals and minimize crosstalk to the SYNC signal

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to avoid this problem. Multiple LTM4678s are required to share one SYNC pin in PolyPhase configurations. For other configurations, connecting the SYNC pins to form a single SYNC signal is optional. If the SYNC pin is shared between LTM4678s, only one LTM4678 can be programmed with a frequency output. All the other LTM4678s should be programmed to disable the SYNC output. However their frequency should be programmed to the nominal desired value.
INPUT CURRENT SENSE AMPLIFIER
The LTM4678 input current sense amplifier can sense the supply current into the VIN0 and VIN1 power stages pins using an external sense resistor as shown in the Figure 2 Block Diagram. The RSENSE value can be programmed using the MFR_IIN_CAL_GAIN command. Kelvin sensing is recommended across the RSENSE resistor to eliminate errors. The MFR_PWM_CONFIG [6:5] sets the input current sense amplifier gain. See the MFR_PWM_CONFIG section. The IIN_OC_WARN_LIMIT command sets the value of the input current measured by the ADC, in amperes, that causes a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has been exceeded. The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor.
There is an IR voltage drop from the supply to the SVIN pin due to the current flowing into the SVIN pin. To compensate for this voltage drop, the MFR_RVIN will be automatically set to the 1 internal sense resistor in the Figure 2 Block Diagram. The LTM4678 will multiply the MFR_READ_ICHIP measurement value by this 1 resistor and add this voltage to the measured voltage at the SVIN pin. Therefore, READ_VIN = VSVIN_PIN + (MFR_READ_ICHIP · 1) The MFR_READ_ICHIP command is used to measure the internal controller current. Using the READ_PIN command allows for reading calculated input power.
PROGRAMMABLE LOOP COMPENSATION
The LTM4678 offers programmable loop compensation to optimize the transient response without any hardware change. The error amplifier gain gm varies from 1.0mmho to

5.73mmho, and the compensation resistor RCOMPn varies from 0k to 62k inside the controller. Two compensation capacitors, COMPna and COMPnb, are required in the design and the typical ratio between COMPna and COMPnb is 10. Also see Figure 2 Block Diagram and Figure 27.
By adjusting the gm and RCOMPn only, the LTM4678 can provide a flexible Type II compensation network to optimize the loop over a wide range of output capacitors. Adjusting the gm will change the gain of the compensation over the whole frequency range without moving the pole and zero location, as shown in Figure 28.
Adjusting the RCOMP will change the pole and zero location, as shown in Figure 29. It is recommended that the user determines the appropriate value for the gm and RCOMPn using the LTPowerCAD tool.

RCOMPn COMPna
CCOMPL

22pF COMPnb CCOMPH

VREF FB
4678 F27

Figure 27. Programmable Loop Compensation

GAIN

TYPE II COMPENSATION

INCREASE gm
FREQUENCY
4678 F28
Figure 28. Error Amp gm Adjust

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GAIN

TYPE II COMPENSATION

INCREASE RCOMPn
FREQUENCY
4678 F29
Figure 29. RCOMP Adjust
CHECKING TRANSIENT RESPONSE
The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ILOAD(ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the COMP pin not only allows optimization of control loop behavior but also provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The COMPna external capacitor shown in the Typical Application circuit will provide an adequate starting point for most applications. The programmable parameters that affect loop gain are the voltage range, bit[1] of the MFR_PWM_CONFIG command, the current range bit[7] of the MFR_PWM_MODE command, the gm of the PWM channel amplifier bits [7:5] of MFR_PWM_COMP, and the internal RCOMP compensation resistor, bits[4:0] of MFR_PWM_COMP. Be sure to establish these settings prior to compensation calculation.

The COMPna series internal RCOMPn and external CCOMPna filter sets the dominant pole-zero loop compensation. The internal RCOMPn value can be modified (from 0 to 62k) using bits[4:0] of the MFR_PWM_ COMP command. Adjust the value of RCOMPn to optimize transient response once the final PCB layout is done and the particular CCOMPbn filter capacitor and output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1µs to 10µs will produce output voltage and COMP pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET with a resistor to ground directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce to a load step. The MOSFET + RSERIES will produce output currents approximately equal to VOUT/RSERIES. RSERIES values from 0.1 to 2 are valid depending on the current limit settings and the programmed output voltage. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the COMP pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RCOMP and the bandwidth of the loop will be increased by decreasing CCOMPna. If RCOMP is increased by the same factor that CCOMPL is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The gain of the loop will be proportional to the transconductance of the error amplifier which is set using bits[7:5] of the MFR_PWM_COMP command. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change

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in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 · CLOAD. Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA.
PolyPhase Configuration
When configuring a PolyPhase rail with multiple LTM4678s, the user must share the SYNC, COMP, SHARE_CLK, FAULT, and ALERT pins of these parts. Be sure to use pull-up resistors on FAULT, SHARE_CLK and ALERT. One of the part's SYNC pins must be set to the desired switching frequency, and all other FREQUENCY_SWITCH commands must be set to External Clock. If an external oscillator is provided, set the FREQUENCY_SWITCH command to External Clock for all parts. The relative phasing of all the channels should be spaced equally. The MFR_RAIL_ ADDRESS of all the devices should be set to the same value.
Multiple channels need to tie all the VSENSEn+ pins together, and all the VSENSEn pins together, COMPna and COMPnb pins together as well. Do not assert bit[4] of MFR_CONFIG_ALL except in a PolyPhase application. See application example Figure 47.

CONNECTING THE USB TO I2C/SMBUS/PMBUS CONTROLLER TO THE LTM4678 IN SYSTEM
The ADI USB-to-I2C/SMBus/PMBus adapter (DC1613A or equivalent) can be interfaced to the LTM4678 on the user's board for programming, telemetry and system debug. The adapter, when used in conjunction with LTpowerPlay, provides a powerful way to debug an entire power system. Faults are quickly diagnosed using telemetry, fault status commands and the fault log. The final configuration can be quickly developed and stored to the LTM4678 EEPROM. Figure 30 illustrates the application schematic for powering, programming and communication with one or more LTM4678s via the ADI I2C/SMBus/PMBus adapter regardless of whether or not system power is present. If system power is not present, the dongle will power the LTM4678 through the VDD33 supply pin. To initialize the part when VIN is not applied and the VDD33 pin is powered, use global address 0x5B command 0xBD data 0x2B followed by address 0x5B command 0xBD data 0xC4.The LTM4678 can now communicate with the internal EEPROM and read the project file utilizing Figure 30. Controller Connection can be updated. To write the updated project file to the NVM issue a STORE_USER _ALL command. When VIN is applied, a MFR_RESET must be issued to allow the PWM POWER to be enabled and valid ADCs to be read.

LTC CONTROLLER
HEADER ISOLATED 3.3V
SDA
SCL

100k

VIN 100k

TP0101K 10k 10k

TO LTC DC1613 USB TO I2C/SMBus/PMBus
CONTROLLER

VIN

VDD33

VDD25

1µF

LTM4678

SDA

SCL WP PGND/SGND

VIN

TP0101K

1µF

VGS MAX ON THE TP0101K IS 8V IF VIN > 16V CHANGE THE RESISTOR DIVIDER ON THE PFET GATE

VDD33

VDD25

LTM4678 SDA

SCL WP PGND/SGND
4678 F30

Figure 30. Controller Connection
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LTM4678

APPLICATIONS INFORMATION
Because of the adapter's limited current sourcing capability, only the LTM4678s, their associated pull-up resistors and the I2C pull-up resistors should be powered from the VDD33 3.3V supply. In addition any device sharing the I2C bus connections with the LTM4678 should not have body diodes between the SDA/SCL pins and their respective VDD node because this will interfere with bus communication in the absence of system power. If VIN is applied, the DC1613A will not supply the power to the LTM4678s on the board. It is recommended the RUNn pins be held low or no voltage configuration resistors inserted to avoid providing power to the load until the part is fully configured.
The LTM4678 is fully isolated from the host PC's ground by the DC1613A.The 3.3V from the adapter and the LTM4678 VDD33 pin must be driven to each LTM4678 with a separate PFET. If both VIN and EXTVCC are not applied, the VDD33 pins can be in parallel because the on-chip LDO is off. The controller 3.3V current limit is 100mA but typical VDD33 currents are under 15mA. The VDD33 does back drive the INTVCC/EXTVCC pin. Normally this is not an issue if VIN is open.
LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL POWER
LTpowerPlay (Figure 31) is a powerful Windows-based development environment that supports Analog Devices digital power system management ICs including the LTM4678. The software supports a variety of different tasks. LTpowerPlay can be used to evaluate Analog Devices ICs by connecting to a demo board or the user application. LTpowerPlay can also be used in an offline mode (with no hardware present) in order to build multiple IC configuration files that can be saved and reloaded at a later time. LTpowerPlay provides unprecedented diagnostic and debug features. It becomes a valuable diagnostic tool during board bring-up to program or tweak the power system or to diagnose power issues when bring up rails. LTpowerPlay utilizes Analog Devices' USB-to-I2C/SMBus/ PMBus adapter to communication with one of the many potential targets including the DC2165A demo board, the

DC2298A socketed programming board, or a customer target system. The software also provides an automatic update feature to keep the revisions current with the latest set of device drivers and documentation.
A great deal of context sensitive help is available with LTpower Play along with several tutorial demos. Complete information is available at: LTpowerPlay.
PMBus COMMUNICATION AND COMMAND PROCESSING
The LTM4678 has a one deep buffer to hold the last data written for each supported command prior to processing as shown in Figure 32, Write Command Data Processing. When the part receives a new command from the bus, it copies the data into the Write Command Data Buffer, indicates to the internal processor that this command data needs to be fetched, and converts the command to its internal format so that it can be executed. Two distinct parallel blocks manage command buffering and command processing (fetch, convert, and execute) to ensure the last data written to any command is never lost. Command data buffering handles incoming PMBus writes by storing the command data to the Write Command Data Buffer and marking these commands for future processing. The internal processor runs in parallel and handles the sometimes slower task of fetching, converting and executing commands marked for processing. Some computationally intensive commands (e.g., timing parameters, temperatures, voltages and currents) have internal processor execution times that may be long relative to PMBus timing. If the part is busy processing a command, and new command(s) arrive, execution may be delayed or processed in a different order than received. The part indicates when internal calculations are in process via bit 5 of MFR_COMMON ("calculations not pending"). When the part is busy calculating, bit 5 is cleared. When this bit is set, the part is ready for another command. An example polling loop is provided in Figure 33 which ensures that commands are processed in order while simplifying error handling routines.

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LTM4678

Figure 31. LTpowerPlay Screen Shot

PMBus WRITE

CMD DECODER

DATA MUX

CALCULATIONS

PENDING

CMDS

WRITE COMMAND DATA BUFFER
PAGE ·· ·
VOUT_COMMAND ···

0x00 0x21

INTERNAL PROCESSOR
FETCH, CONVERT
DATA AND EXECUTE

MFR_RESET 0xFD

x1
4678 F32

Figure 32. Write Command Data Processing

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61

LTM4678

APPLICATIONS INFORMATION
When the part receives a new command while it is busy, it will communicate this condition using standard PMBus protocol. Depending on part configuration it may either NACK the command or return all ones (0xFF) for reads. It may also generate a BUSY fault and ALERT notification, or stretch the SCL clock low. For more information refer to PMBus Specification v1.1, Part II, Section 10.8.7 and SMBus v2.0 section 4.3.3. Clock stretching can be enabled by asserting bit 1 of MFR_CONFIG_ ALL. Clock stretching will only occur if enabled and the bus communication speed exceeds 100kHz.
// wait until chip is not busy do { mfrCommonValue = PMBUS_READ_BYTE(0xEF); partReady = (mfrCommonValue & 0x68) == 0x68; }while(!partReady)
// now the part is ready to receive the next command PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_COMMAND to 2V
Figure 33. Example of a Command Write of VOUT_COMMAND
PMBus busy protocols are well accepted standards, but can make writing system level software somewhat complex. The part provides three `hand shaking' status bits which reduce complexity while enabling robust system level communication.
The three hand shaking status bits are in the MFR_ COMMON register. When the part is busy executing an internal operation, it will clear bit 6 of MFR_COMMON (`chip not busy'). When the part is busy specifically because it is in a transitional VOUT state (margining hi/lo, power off/ on, moving to a new output voltage set point, etc.) it will clear bit 4 of MFR_COMMON (`output not in transition'). When internal calculations are in process, the part will clear bit 5 of MFR_COMMON (`calculations not pending'). These three status bits can be polled with a PMBus read byte of the MFR_COMMON register until all three bits are set. A command immediately following the status bits being set will be accepted without NACKing or generating a BUSY fault/ALERT notification. The part can NACK commands for other reasons, however, as required by the PMBus spec (for instance, an invalid command or data).

An example of a robust command write algorithm for the VOUT_COMMAND register is provided in Figure 33.
It is recommended that all command writes (write byte, write word, etc.) be preceded with a polling loop to avoid the extra complexity of dealing with busy behavior and unwanted ALERT notification. A simple way to achieve this is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_ WORD() subroutine. The above polling mechanism allows your software to remain clean and simple while robustly communicating with the part. For a detailed discussion of these topics and other special cases please refer to Analog Devices application notes.
When communicating using bus speeds at or below 100kHz, the polling mechanism shown here provides a simple solution that ensures robust communication without clock stretching. At bus speeds in excess of 100kHz, it is strongly recommended that the part be configured to enable clock stretching. This requires a PMBus master that supports clock stretching. System software that detects and properly recovers from the standard PMBus NACK/ BUSY faults as described in the PMBus Specification v1.1, Par II, Section 10.8.7 is required to communicate The LTM4678 is not recommended in applications with bus speeds in excess of 400kHz.
THERMAL CONSIDERATIONS AND OUTPUT CURRENT DERATING
The thermal resistances reported in the Pin Configuration section of this data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board defined by JESD51-9 ("Test Boards for Area Array Surface Mount Package Thermal Measurements"). The motivation for providing these thermal coefficients is found in JESD51-12 ("Guidelines for Reporting and Using Electronic Package Thermal Information").
Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the µModule regulator's thermal performance in their appli-

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APPLICATIONS INFORMATION
cation at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided later in this data sheet can be used in a manner that yields insight and guidance pertaining to one's application-usage, and can be adapted to correlate thermal performance to one's own application.
The Pin Configuration section gives four thermal coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below:
1. JA, the thermal resistance from junction to ambi-
ent, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as "still air" although natural convection causes the air to move. This value is determined with the part mounted to a JESD51-9 defined test board, which does not reflect an actual application or viable operating condition.
2. JCbottom, the thermal resistance from junction to the
bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing pack-

ages but the test conditions don't generally match the user's application.
3. JCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the
top of the part. As in the case of JCbottom, this value
may be useful for comparing packages but the test conditions don't generally match the user's application.
4 JB, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule regulator and into the board,
and is really the sum of the JCbottom and the thermal
resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD51-9.
A graphical representation of the aforementioned thermal resistances is given in Figure 34; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in the

JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS

JUNCTION-TO-CASE (TOP) RESISTANCE

CASE (TOP)-TO-AMBIENT RESISTANCE

JUNCTION

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD

(BOTTOM) RESISTANCE

RESISTANCE

BOARD-TO-AMBIENT RESISTANCE

AMBIENT

µModule DEVICE

4678 F33

Figure 34. Graphical Representation of JESD51-12 Thermal Coefficients

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63

LTM4678

APPLICATIONS INFORMATION
Pin Configuration section replicates or conveys normal operating conditions of a µModule regulator. For example, in normal board-mounted applications, never does 100% of the device's total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the µModule package--as the standard defines
for JCtop and JCbottom, respectively. In practice, power
loss is thermally dissipated in both directions away from the package--granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board.
Within the LTM4678, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity--but also, not ignoring practical realities--an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4678 and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JESD51-9 and JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4678 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves provided in later sections of this data sheet, along with

well-correlated JESD51-12-defined values provided in
the Pin Configuration section of this data sheet.
The 5V, 8V and 12V power loss curves in Figure 35, Figure 36 and Figure 37 respectively can be used in coordination with the load current derating curves in Figure 38 to Figure
43 for calculating an approximate JA thermal resistance
for the LTM4678 with airflow conditions. These thermal resistances represent demonstrated performance of the LTM4678 on hardware; a 6-layer FR4 PCB measuring 99mm × 130mm × 1.6mm using 2oz copper on all layers. The power loss curves are taken at room temperature, and are increased with multiplicative factors of 1.35 when the junction temperature reaches 125°C. The derating curves are plotted with the LTM4678's paralleled outputs initially sourcing up to 50A and the ambient temperature at 25°C. The output voltages are 0.9V and 1.8V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow.
The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 125°C maximum while lowering output current or power while increasing ambient temperature. The decreased output current decreases the internal module loss as ambient temperature is increased. The monitored junction temperature of 125°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 40, the load current is derated to ~35A at ~73°C ambient with no air or heat sink and the room temperature (25°C) power loss for this 12VIN to 0.9VOUT at 35AOUT condition is ~4W. A 5.4W loss is calculated by multiplying the ~4W room temperature loss from the 12VIN to 0.9VOUT power loss curve at 35A (Figure 35), with the 1.35 multiplying factor. If the 73°C ambient temperature is subtracted from the 125°C junction temperature, then the difference of

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52°C divided by 5.4W yields a thermal resistance, JA, of
9.6°C/W--in good agreement with Table 10. Table 10 and Table 11 provide equivalent thermal resistances for 0.9V and 1.8V outputs with and without airflow. The derived thermal resistances in Table 10 and Table 11 for the various conditions can be multiplied by the calculated power loss

as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with the above ambient temperature multiplicative factors.

TABLE 10 THRU TABLE 11: OUTPUT CURRENT DERATING

Table 10. 0.9V Output
DERATING CURVE
Figure 38, Figure 39, Figure 40
Figure 38, Figure 39, Figure 40
Figure 38, Figure 39, Figure 40

VIN (V) 5, 8, 12
5, 8, 12
5, 8, 12

POWER LOSS CURVE
Figure 35, Figure 36, Figure 37
Figure 35, Figure 36, Figure 37
Figure 35, Figure 36, Figure 37

AIRFLOW (LFM) 0
200
400

Table 11. 1.8V Output
DERATING CURVE
Figure 41, Figure 42, Figure 43
Figure 41, Figure 42, Figure 43
Figure 41, Figure 42, Figure 43

VIN (V) 5, 8, 12
5, 8, 12
5, 8, 12

POWER LOSS CURVE
Figure 35, Figure 36, Figure 37
Figure 35, Figure 36, Figure 37
Figure 35, Figure 36, Figure 37

AIRFLOW (LFM) 0
200
400

HEAT SINK None None None
HEAT SINK None None None

JA (°C/W)
9 8 6.5
JA (°C/W)
9 8 6.5

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Table 12. Channel Output Voltage vs Component Selection, 0A to 12.5A/s Load Step Output Capacitor-GRM32ER60G337ME05L, 330F, 4V, X5R, Murata Low VOUT Range for VOUT 2.5V High VOUT Range for 2.5V VOUT ILIMIT Range = High

VIN

VOUT

COUT

CCOMP B CCOMP A

EA-GM

(V)

(CER CAP)

(pF)

(nF) R_ITH (k) (ms)

0.9

330Fx5

150

3.3

2.35

0.9

330Fx5

150

3.3

2.35

0.9

330Fx5

150

3.3

2.35

0.9

330Fx7

150

3.3

3.69

0.9

330Fx7

150

3.3

3.69

0.9

330Fx7

150

3.3

3.69

330Fx7

150

3.3

3.69

330Fx7

150

3.3

3.69

330Fx7

150

3.3

3.69

1.2

330Fx5

150

3.3

2.35

1.2

330Fx5

150

3.3

2.35

1.2

330Fx5

150

3.3

2.35

1.5

330Fx5

150

3.3

2.35

1.5

330Fx5

150

3.3

2.35

1.5

330Fx5

150

3.3

2.35

1.8

330Fx5

150

3.3

2.35

1.8

330Fx5

150

3.3

2.35

1.8

330Fx5

150

3.3

2.35

2.5

330Fx5

150

3.3

2.35

2.5

330Fx5

150

3.3

2.35

2.5

330Fx5

150

3.3

2.35

3.3

330Fx5

150

3.3

3.69

3.3

330Fx5

150

3.3

3.69

3.3

330Fx5

150

3.3

3.69

FSW (kHz) 350 350 350 350 350 350 350 350 350 350 350 350 500 500 500 575 575 575 575 575 575 750 750 750

LOAD STEP (A) 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5

PK-PK DEVIATION
(mV) 140 150 150 100 100 100 100 100 100 140 150 150 145 145 145 150 150 150 170 160 160 200 190 190

RECOVERY TIME (s) 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25

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Table 13. Channel Output Voltage vs Component Selection, 0A to 12.5A/s Load Step Low VOUT Range for VOUT 2.5V High VOUT Range for 2.5V VOUT ILIMIT Range = High
*GRM32ER60J107M 100F, 6.3V, 1210 X5R
**2R5TPF 470M6L, 470F, 2.5V 6m, Used on Up to 1.8V Output
***4TPF470ML, 470F, 4V, 10m, Used on 2.5V and 3.3V Output

VIN (V)

VOUT (V)

0.9

1.2

1.5

1.8

2.5

3.3

COUT (CER CAP) *100Fx3 *100Fx3 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2 *100Fx2

COUT (BULK CAP) **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 ***470Fx2 ***470Fx2 ***470Fx2 ***470Fx1 ***470Fx1 ***470Fx1 ***470Fx2 ***470Fx2 ***470Fx2

CCOMP B (pF) 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150

CCOMP A (nF) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5

RCOMPn (k) 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 15 15 15

EA-GM (ms) 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69 3.69

Dual Phase Single Output Ceramic and Poscap Output Capacitors

VIN (V)

VOUT (V)

5.5

1.5

1.8

COUT (CER CAP) *100Fx6 *100Fx6 *100Fx6 *100Fx6 *100Fx6 *100Fx6 *100Fx6 *100Fx6 *100Fx6

COUT (BULK CAP) **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2 **470Fx2

CCOMP B (pF) 150 150 150 150 150 150 150 150 150

CCOMP A (nF) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5

RCOMPn (k) 6 6 6 6 6 6 6 6 6

EA-GM (ms) 2.35 2.35 2.35 2.35 2.35 2.35 2.35 2.35 2.35

FSW (kHz) 350 350 350 350 350 350 350 350 350 350 350 500 500 500 575 575 575 575 575 575 750 750 750 750 750 750

LOAD STEP (A)
0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-12.5 0-10 0-12.5 0-12.5 0-10 0-12.5 0-12.5

PK-PK DEVIATION
(mV) 80 80 75 80 80 75 80 80 75 75 75 70 70 70 70 70 70 80 80 80 160 135 135 125 110 110

FSW (kHz) 500 500 500 500 500 500 575 575 575

LOAD STEP (A)
25-50 25-50 25-50 25-50 25-50 25-50 25-50 25-50 25-50

PK-PK DEVIATION
(mV) 90 90 90 95 95 95 100 100 100

RECOVERY TIME (s)
20 20 20 20 20 20 20 20 25 25 25 25 25 25 20 20 20 40 40 40 40 40 40 40 40 40
RECOVERY TIME (s)
15 15 15 15 15 15 15 15 15

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LTM4678

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12 0.9V, 350kHz

1.0V, 350kHz

1.2V, 350kHz

1.5V, 575kHz

1.8V, 575kHz

2.5V, 575kHz

3.3V, 750kHz

12 0.9V, 350kHz

1.0V, 350kHz

1.2V, 350kHz

1.5V, 575kHz

1.8V, 575kHz

2.5V, 575kHz

3.3V, 750kHz

12 0.9V, 350kHz

1.0V, 350kHz

1.2V, 350kHz

1.5V, 575kHz

1.8V, 575kHz

2.5V, 575kHz

3.3V, 750kHz

POWER LOSS (W) POWER LOSS (W) POWER LOSS (W)

OUTPUT CURRENT (A)

4678 F35

Figure 35. 5VIN Power Loss Curve

OUTPUT CURRENT (A)

4678 F36

Figure 36. 8VIN Power Loss Curve

OUTPUT CURRENT (A)

4678 F37

Figure 37. 12VIN Power Loss Curve

IOUT (A) IOUT (A) IOUT (A)

0LFM

200LFM

400LFM

75 100 125

AMBIENT TEMPERATURE (°C)
4678 F38

Figure 38. 5V to 0.9V Derating Curve, No Heat Sink

0LFM

200LFM

400LFM

75 100 125

AMBIENT TEMPERATURE (°C)
4678 F39

Figure 39. 8V to 0.9V Derating Curve, No Heat Sink

0LFM

200LFM

400LFM

100 125

AMBIENT TEMPERATURE (°C)
4678 F40

Figure 40. 12V to 0.9V Derating Curve, No Heat Sink

IOUT (A) IOUT (A) IOUT (A)

0LFM

200LFM

400LFM

75 100 125

AMBIENT TEMPERATURE (°C)
4678 F41

Figure 41. 5V to 1.8V Derating Curve, BGA No Heat Sink

0LFM

200LFM

400LFM

75 100 125

AMBIENT TEMPERATURE (°C)
4678 F42

Figure 42. 8V to 1.8V Derating Curve, No Heat Sink

0LFM

200LFM

400LFM

75 100 125

AMBIENT TEMPERATURE (°C)
4678 F43

Figure 43. 12V to 1.8V Derating Curve, No Heat Sink
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EMI PERFORMANCE

The SWn pin provides access to the midpoint of the power MOSFETs in LTM4678's power stages.

Connecting an optional series RC network from SWn to GND can dampen high frequency (~30MHz+) switch node ringing caused by parasitic inductances and capacitances in the switched-current paths. The RC network is called a snubber circuit because it dampens (or "snubs") the resonance of the parasitics, at the expense of higher power loss. To use a snubber, choose first how much power to allocate to the task and how much PCB real estate is available to implement the snubber. For example, if PCB space allows a low inductance 0.5W resistor to be used then the capacitor in the snubber network (CSW) is computed by:

CSW

PSNUB VINn(MAX)2 ·

fSW

where VINn(MAX) is the maximum input voltage that the input to the power stage (VINn) will see in the application, and fSW is the DC/DC converter's switching frequency of operation. CSW should be NPO, C0G or X7R-type (or better) material.

The snubber resistor (RSW) value is then given by:

RSW =

5nH CSW

The snubber resistor should be low ESL and capable of withstanding the pulsed currents present in snubber circuits. A value between 0.7 and 4.2 is normal.
A 2.2nF snubber capacitor is a good value to start with in series with the snubber resistor to ground. The no load input quiescent current can be monitored while selecting different RC series snubber components to get a increased power loss versus switch node ringing attenuation.

SAFETY CONSIDERATIONS
The LTM4678 modules do not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure.
The fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top MOSFET fault. If the internal top MOSFET fails, then turning it off will not resolve the overvoltage, thus the internal bottom MOSFET will turn on indefinitely trying to protect the load. Under this fault condition, the input voltage will source very large currents to ground through the failed internal top MOSFET and enabled internal bottom MOSFET. This can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. A fuse or circuit breaker can be used as a secondary fault protector in this situation. The device does support over current and overtemperature protection.
LAYOUT CHECKLIST/EXAMPLE
The high integration of LTM4678 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary.
n Use large PCB copper areas for high current paths, including VINn, GND and VOUTn. It helps to minimize the PCB conduction loss and thermal stress.
n Place high frequency ceramic input and output capacitors next to the VINn, GND and VOUTn pins to minimize high frequency noise.
n Place a dedicated power ground layer underneath the module.
n To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.

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n Do not put vias directly on pads, unless they are capped or plated over.
n Use a separate SGND copper plane for components connected to signal pins. Connect SGND to GND local to the LTM4678.
n Use Kelvin sense connections across the input RSENSE resistor if input current monitoring is used.

For parallel modules, tie the VOUTn, VOSNSn+/VOSNSn voltage-sense differential pair lines, RUNn, COMPna, COMPnb pin together.
n The user must share the SYNC, SHARE_CLK, FAULT, and ALERT pins of these parts. Be sure to use pull-up resistors on FAULT, SHARE_CLK and ALERT.
n Bring out test points on the signal pins for monitoring.
Figure 44 gives a good example of the recommended layout.

VOUT1 GND

GND

VOUT0 GND

VOUT1 GND

VOUT0 GND

OPTIONAL INPUT CURRENT SENSE

GND VIN

GND

4678 F44a

(a) TOP LAYER

GND

VIN

(b) BOTTOM LAYER

Figure 44. Recommended PCB Layout Package Top View

4678 F44b

Rev. A

For more information www.analog.com

TYPICAL APPLICATIONS
VDD33

2.2µF

VDD33 10k

PGOOD

LTM4678

VDD33 VDD25 INTVCC EXTVCC PGOOD0 PGOOD1 TSNS0a TSNS0b TSNS1a TSNS1b

VIN 5.75V TO 16V 150µF

VDD33

22µF ×5

IIN+ 1m
IIN VIN1 VIN0
SVIN

10k 4.99k 10k 10k
RUN1 ON/OFFCONFIG
RUN0 FAULT INTERRUPTS FAULT0
FAULT1 SYNC SHARE_CLK
WP

LTM4678

SW0 VOUT0
VOSNS0+ VOSNS0
SW1 VOUT1
VOSNS1+ VOSNS1
SCL SDA ALERT GND SGND

100µF ×3
0.9V AT 50A

100µF ×3

+ 470µF
×2

LOAD

VVOOSSNNSS01

AND AT

REMOTE GND

POINT

10k 10k 10k VDD33

COMP1a COMP1b COMP0a COMP0b VTRIM1_CFG VTRIM0_CFG VOUT0_CFG VOUT1_CFG FSWPH_CFG ASEL

3300pF

150pF

825

4678 F45
22.6k 22.6k

I2C/SMBus INTERFACE WITH PMBus COMMAND SET TO/FROM IPMI OR OTHER BOARD MANAGEMENT CONTROLLER
CONFIG RESISTORS ARE TO BE 1%, 50PPM

· SLAVE ADDRESS = 1001110_R/W (0X4E) · 350kHz SWITCHING FREQUENCY · NO GUI CONFIGURATION AND NO PART-SPECIFIC PROGRAMMING REQUIRED · IN MULTI-MODULE SYSTEMS, CONFIGURING RAIL_ADDRESS IS RECOMMENDED · RCOMP = 6k · GM = 2.35ms · VOUT RANGE = LOW · ILIMIT RANGE = HIGH
Figure 45. 50A, 0.9V Output DC/DC µModule Regulator with I2C/SMBus/PMBus Serial Interface

For more information www.analog.com

Rev. A
71

LTM4678 TYPICAL APPLICATIONS
VDD33

2.2µF 10k

VDD33 PGOOD0

10k

PGOOD1

VDD33 VDD25 INTVCC EXTVCC PGOOD0 PGOOD1 TSNS0a TSNS0b TSNS1a TSNS1b

VDD33

VIN 5.75V TO 16V

IIN+

150µF

1m IIN

22µF

VIN1

×5

VIN0

SVIN

10k 4.99k 10k 10k 10k 10k
RUN1 ON/OFFCONFIG RUN0 FAULT INTERRUPTS FAULT0
FAULT1 SYNC SHARE_CLK
WP

LTM4678

1500pF

150pF

1500pF 150pF

· SLAVE ADDRESS = 1001110_R/W (0X4E) · 425kHz SWITCHING FREQUENCY · NO GUI CONFIGURATION AND NO PART-SPECIFIC PROGRAMMING REQUIRED · IN MULTI-MODULE SYSTEMS, CONFIGURING RAIL_ADDRESS IS RECOMMENDED · VOUT1 AND VOUT0 = RCOMP = 11k, GM = 3.69ms, VOUT RANGE = LOW AND ILIMIT RANGE = HIGH

COMP1a COMP1b COMP0a COMP0b VTRIM1_CFG VTRIM0_CFG VOUT0_CFG VOUT1_CFG FSWPH_CFG ASEL

RSNUB0 SW0

CSNUB0

VOUT0 VOSNS0+
VOSNS0
SW1 VOUT1 VOSNS1+
VOSNS1

LOAD0 LOAD1

VOUT0 1V, 25A

100µF ×3

470µF ×2

RSNUB1

VOUT1 1.5V, 25A

CSNUB1

100µF ×2

470µF ×2

SCL SDA ALERT GND SGND

10k 10k 10k VDD33

2.43k

4678 F46
4.22k 18k 22.6k

I2C/SMBus INTERFACE WITH PMBus COMMAND SET TO/FROM IPMI OR OTHER BOARD MANAGEMENT CONTROLLER
CONFIG RESISTORS ARE TO BE 1%, 50PPM

Figure 46. 1.0V and 1.5V Outputs at 25A With Providing I2C/SMBus/PMBus Serial Interface

Rev. A

For more information www.analog.com

TYPICAL APPLICATIONS

VDD33 U1

5.75V TO 16V VIN

IIN+

150µF

IIN

VDD33 U1

VIN1 22µF

×4

VIN0

10k 4.99k 10k 10k

SVIN

RUN1 ON/OFF CONTROL RUN0

FAULT INTERRUPTS FAULT0

SYNC CLOCK SHARE CLOCK

FAULT1 SYNC SHARE_CLK

VDD33 2.2µF 4.99k
PGOOD
LTM4678

VDD33 VDD25 INTVCC *EXTVCC PGOOD0 PGOOD1 TSNS0a TSNS0b TSNS1a TSNS1b

U1
SW0 VOUT0 VOSNS0+ VOSNS0
SW1
VOUT1 VOSNS1+ VOSNS1
SCL SDA ALERT GND SGND

SCL SDA ALERT
10k 10k 10k
VDD33 U1

LTM4678

100µF ×3

470µF ×2

100µF ×3

470µF ×2

COMP1a COMP1b COMP0a COMP0b VTRIM1_CFG VTRIM0_CFG VOUT0_CFG VOUT1_CFG FSWPH_CFG ASEL

COMPa 10nF

VIN 22µF ×4

VDD33 U2
IIN+
IIN
VIN1 VIN0
SVIN RUN1 RUN0 FAULT0 FAULT1 SYNC SHARE_CLK WP

*OPTIONAL 5.5V BIAS 100mA TOTAL FOR EFFICIENCY AND THERMAL IMPROVEMENT

COMPa

COMP1a COMP1b COMP0a COMP0b VTRIM1_CFG VTRIM0_CFG VOUT0_CFG VOUT1_CFG FSWPH_CFG ASEL

VDD33 VDD25 INTVCC *EXTVCC PGOOD0 PGOOD1 TSNS0a TSNS0b TSNS1a TSNS1b

220pF

1.21k

COMPb

PGOOD 2.2µF

22.6k

CONFIG RESISTORS ARE TO BE 1%, 50PPM

I2C/SMBus I/F WITH PMBus COMMAND SET TO/FROM IPMI OR OTHER BOARD MANAGEMENT CONTROLLER

LTM4678 COMPb

1.21k

SW0 VOUT0 VOSNS0+ VOSNS0
SW1 VOUT1 VOSNS1+ VOSNS1
SCL SDA ALERT GND SGND
4678 F47
1.65k 787

100µF ×3

470µF ×2

SCL SDA ALERT

100µF ×3

470µF ×2

LOAD1

1V AT 100A

CONFIG RESISTORS ARE TO BE 1%, 50PPM
· U1: SLAVE ADDRESS = 1000000_R/W (0X40) · U2: SLAVE ADDRESS = 1000001_R/W (0X41) · 350kHz SWITCHING FREQUENCY WITH INTERLEAVING · NO GUI CONFIGURATION AND NO PART-
SPECIFIC PROGRAMMING REQUIRED · IN MULTI-MODULE SYSTEMS, CONFIGURING
RAIL_ADDRESS IS RECOMMENDED

FOivgeurre2-4W7i.reTwI2oCP/SaMraBlluesle/PdMLBTuMs4S6e7r8iaPlrIondtuecrfiancge1,VNOoUTInaptu1t 0C0uArr.eInntteRgeraadtebdacPkower System Management Features Accessible

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Rev. A
73

LTM4678
TYPICAL APPLICATIONS
5V BIAS 50mA
VDD33

2.2µF

VDD33
10k PGOOD

VDD33 VDD25 INTVCC EXTVCC PGOOD0 PGOOD1 TSNS0a TSNS0b TSNS1a TSNS1b

VIN 3.3V 220µF
TC75H09F4 5V BIAS
VDD33

IIN+

22µF ×5

IIN

VIN1

VIN0

5V BIAS SVIN

10k 4.99k 10k 10k

RUN1

ON/OFFCONFIG RUN0

FAULT INTERRUPTS FAULT0

FAULT1 SYNC

SHARE_CLK WP

LTM4678

SW0 VOUT0
VOSNS0+
VOSNS0 SW1
VOUT1
VOSNS1+ VOSNS1
SCL SDA ALERT GND SGND

100µF ×3
1V AT 25A
+
LOAD

330µF

100µF ×3
1.2V AT 25A
+
LOAD

330µF

10k 10k 10k VDD33

COMP1a COMP1b COMP0a COMP0b VTRIM1_CFG VTRIM0_CFG VOUT0_CFG VOUT1_CFG FSWPH_CFG ASEL

2200pF

100pF

2200pF 100pF

2.43k

4678 F48
3.24k 22.6k 22.6k
350kHz

I2C/SMBus I/F WITH PMBus COMMAND SET TO/FROM IPMI OR OTHER BOARD MANAGEMENT CONTROLLER
SLAVE ADDRESS:100 1110R/W
CONFIG RESISTORS ARE TO BE 1%, 50PPM

· VOUT0 AND VOUT1 = RCOMP = 11k, GM = 3.69ms, VOUT RANGE = LOW AND ILIMIT RANGE = HIGH
Figure 48. 1V and 1.2V Outputs Generated from 3.3V Power Input and Providing I2C/SMBus/PMBus Serial Interface

Rev. A

For more information www.analog.com

LTM4678

TYPICAL APPLICATIONS

VDD33 U1

5.75V TO 16V VIN

150µF

22µF

×4

VDD33 U1 10k 4.99k 10k 10k
ON/OFF FAULTS
SYNC SHARE CLK

IIN+
IIN
VIN1 VIN0 SVIN
RUN1 RUN0 FAULT0 FAULT1 SYNC SHARE_CLK WP

VDD33 U1 2.2µF 4.99k
PGOOD
LTM4678

VDD33 VDD25 INTVCC *EXTVCC PGOOD0 PGOOD1 TSNS0a TSNS0b TSNS1a TSNS1b

U1
SW0 VOUT0 VOSNS0+ VOSNS0
SW1
VOUT1 VOSNS1+ VOSNS1
SCL SDA ALERT GND SGND

100µF ×6

470µF ×4

100µF ×6

470µF ×4

SCL SDA ALERT
10k 10k 10k

VDD33 U1

SW0 VOUT0 VOSNS0+ VOSNS0

SW1

SCL SDA ALERT

VOUT1 VOSNS1+ VOSNS1 SCL SDA ALERT

GND SGND

TSNS1b TSNS1a TSNS0b TSNS0a PGOOD1 PGOOD0 *EXTVCC INTVCC
VDD25 VDD33

PGOOD

2.2µF

VDD33 U3

LTM4678

IIN+

VIN

22µF

IIN

×4

VIN1 VIN0 SVIN

RUN1 RUN0

ON/OFF

FAULT0

FAULT1

FAULTS

SYNC SYNC

SHARE_CLK SHARE_CLK

ASEL FSWPH_CFG VOUT1_CFG VOUT0_CFG VTRIM0_CFG VTRIM1_CFG COMP0b COMP0a COMP1b COMP1a

COMP1a COMP1b COMP0a COMP0b VTRIM1_CFG VTRIM0_CFG VOUT0_CFG VOUT1_CFG FSWPH_CFG ASEL

COMPa 18nF

VDD33 U2

VIN

IIN+

22µF ×4

IIN

VIN1 VIN0

ON/OFF FAULTS
SYNC SHARE_CLK

SVIN
RUN1 RUN0
FAULT0 FAULT1 SYNC SHARE_CLK WP

VDD33 VDD25 INTVCC *EXTVCC PGOOD0 PGOOD1 TSNS0a TSNS0b TSNS1a TSNS1b

220pF COMPb

1.21k

2.2µF

PGOOD

LTM4678

22.6k 787 CONFIG RESISTORS ARE TO BE 1%, 50PPM

2.43k 3.24k

I2C/SMBus I/F WITH PMBus COMMAND SET TO/FROM IPMI OR OTHER BOARD MANAGEMENT CONTROLLER

SW0
VOUT0 VOSNS0+ VOSNS0

100µF ×6

SW1

VOUT1

VOSNS1+

VOSNS1
SCL SDA ALERT

SCL SDA ALERT

GND SGND

100µF ×6

470µF ×4

SW0 VOUT0 VOSNS0+ VOSNS0

SW1

VOUT1

470µF ×4
1V AT 200A

SCL SDA ALERT

VOSNS1+ VOSNS1 SCL SDA ALERT

GND SGND

TSNS1b TSNS1a TSNS0b TSNS0a PGOOD1 PGOOD0 *EXTVCC INTVCC
VDD25 VDD33

1.21k

COMPb

COMPa

PGOOD

2.2µF

VDD33 U4

LTM4678

IIN+
IIN VIN1 VIN0 SVIN

VIN
22µF ×4

RUN1 RUN0

ON/OFF

FAULT0

FAULT1

FAULTS

SYNC SYNC

SHARE_CLK SHARE_CLK

ASEL FSWPH_CFG VOUT1_CFG VOUT0_CFG VTRIM0_CFG VTRIM1_CFG COMP0b COMP0a COMP1b COMP1a

COMP1a COMP1b COMP0a COMP0b VTRIM1_CFG VTRIM0_CFG VOUT0_CFG VOUT1_CFG FSWPH_CFG ASEL

*OPTIONAL 5.5V BIAS 200mA TOTAL FOR EFFICIENCY AND THERMAL IMPROVEMENT

COMPa

COMPb

1.21k 1.6k 1.65k

CONFIG RESISTORS ARE TO BE 1%, 50PPM

3.24k 2.43k

1.21k

COMPb

4678 F49
COMPa

Figure 49. 8-Phase Operation with Four LTM4678 Producing 1V at 200A. Power System Management Features Accessible Through the LTM4678 2-Wire I2C/SMBus/PMBus Serial Interface

For more information www.analog.com

Rev. A
75

LTM4678

PMBus COMMAND DETAILS

ADDRESSING AND WRITE PROTECT

COMMAND NAME PAGE PAGE_PLUS_WRITE PAGE_PLUS_READ
WRITE_PROTECT
MFR_ADDRESS MFR_RAIL_ADDRESS

CMD CODE DESCRIPTION

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE

0x00 Provides integration with multi-page PMBus devices. R/W Byte N

Reg

0x00

0x05 Write a supported command directly to a PWM channel. W Block N

0x06 Read a supported command directly from a PWM channel.

Block

R/W

0x10 Level of protection provided by the device against accidental changes.
0xE6 Sets the 7-bit I2C address byte.

R/W Byte N

Reg

R/W Byte N

Reg

Y 0x00 Y 0x4F

0xFA Common address for PolyPhase outputs to adjust common parameters.

R/W Byte Y

Reg

Y 0x80

PAGE
The PAGE command provides the ability to configure, control and monitor both PWM channels through only one physical address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating commands for one PWM channel.
Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device.
Setting PAGE to 0xFF applies any following paged commands to both outputs. With PAGE set to 0xFF the LTM4678 will respond to read commands as if PAGE were set to 0x00 (Channel 0 results).
This command has one data byte.

PAGE_PLUS_WRITE

The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command, and then send the data for the command, all in one communication packet. Commands allowed by the present write protection level may be sent with PAGE_PLUS_WRITE.

The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send a non-paged command, the Page Number byte is ignored.

This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a command that has two data bytes is shown in Figure 50.

SLAVE ADDRESS

PAGE_PLUS COMMAND CODE

BLOCK COUNT (= 4)

8
PAGE NUMBER

COMMAND CODE

A...

LOWER DATA BYTE

UPPER DATA BYTE

8 PEC BYTE

11 AP
4678 F50

Figure 50. Example of PAGE_PLUS_WRITE
PAGE_PLUS_READ
The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command, and then read the data returned by the command, all in one communication packet .

Rev. A

For more information www.analog.com

LTM4678

PMBus COMMAND DETAILS
The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access data from a non-paged command, the Page Number byte is ignored.
This command uses the Process Call protocol. An example of the PAGE_PLUS_READ command with PEC is shown in Figure 51.

SLAVE ADDRESS

PAGE_PLUS COMMAND CODE

BLOCK COUNT (= 2)

8
PAGE NUMBER

COMMAND CODE

A...

SLAVE ADDRESS

BLOCK COUNT (= 2)

LOWER DATA BYTE

UPPER DATA BYTE

8 PEC BYTE

11 NA P
4678 F51

Figure 51. Example of PAGE_PLUS_READ
Note: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another PAGE_PLUS command. If this is attempted, the LTM4678 will NACK the entire PAGE_PLUS packet and issue a CML fault for Invalid/Unsupported Data.
WRITE_PROTECT
The WRITE_PROTECT command is used to control writing to the LTM4678 device. This command does not indicate the status of the WP pin which is defined in the MFR_COMMON command. The WP pin takes precedence over the value of this command.
BYTE MEANING
0x80 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_ EE_UNLOCK, and STORE_USER_ALL commands.
0x40 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL, OPERATION and CLEAR_FAULTS command. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS commands.
0x20 Disable all writes except to the WRITE_PROTECT, OPERATION, MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS, PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_ ALL. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS commands.
0x10 Reserved, must be 0
0x08 Reserved, must be 0
0x04 Reserved, must be 0
0x02 Reserved, must be 0
0x01 Reserved, must be 0
Enable writes to all commands when WRITE_PROTECT is set to 0x00.
If WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK, WRITE_PROTECT and CLEAR_FAULTS commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS commands.

For more information www.analog.com

Rev. A
77

LTM4678

PMBus COMMAND DETAILS
MFR_ADDRESS
The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device.
Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B, cannot be deactivated. If RCONFIG is set to ignore, the ASEL pin is still used to determine the LSB of the channel address. If the ASEL pin is open, the LTM4678 will use the lower 4 bits of the MFR_ADDRESS value stored in NVM to construct the effective address of the part.
This command has one data byte.
MFR_RAIL_ADDRESS The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value of this command should be common to all devices attached to a single power supply rail.
The user should only perform command writes to this address. If a read is performed from this address and the rail devices do not respond with EXACTLY the same value, the LTM4678 will detect bus contention and may set a CML communications fault.
Setting this command to a value of 0x80 disables rail device addressing for the channel.
This command has one data byte.

GENERAL CONFIGURATION COMMANDS

COMMAND NAME

CMD CODE DESCRIPTION

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE

MFR_CHAN_CONFIG

0xD0 Configuration bits that are channel specific. R/W Byte Y

Reg

Y 0x1D

MFR_CONFIG_ALL

0xD1 General configuration bits.

R/W Byte N

Reg

0x21

MFR_CHAN_CONFIG General purpose configuration command common to multiple ADI products.
BIT MEANING 7 Reserved 6 Reserved 5 Reserved 4 Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF. 3 Enable Short Cycle recognition if this bit is set to a 1. 2 SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled. 1 No FAULT ALERT, ALERT is not pulled low if FAULT is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are
propagated on FAULT. 0 Disables the VOUT decay value requirement for MFR_RETRY_TIME and tOFF(MIN) processing. When this bit is set to a 0, the output must decay to
less than 12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from high to low to high.
This command has one data byte.

Rev. A

For more information www.analog.com

LTM4678

PMBus COMMAND DETAILS
A ShortCycle event occurs whenever the PWM channel is commanded back ON, or reactivated, after the part has been commanded OFF and is processing either the TOFF_DELAY or the TOFF_FALL states. The PWM channel can be turned ON and OFF through either the RUN pin and or the PMBus OPERATION command. If the PWM channel is reactivated during the TOFF_DELAY, the part will perform the following:
1. Immediately tri-state the PWM channel output;
2. Start the retry delay timer as specified by the tOFF(MIN). 3. After the tOFF(MIN) value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_ MFR_SPECIFIC bit #1 will assert.
If the PWM channel is reactivated during the TOFF_FALL, the part will perform the following:
1. Stop ramping down the PWM channel output;
2. Immediately tri-state the PWM channel output;
3. Start the retry delay timer as specified by the tOFF(MIN). 4. After the tOFF(MIN) value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_ MFR_SPEFIFIC bit #1 will assert.
If the ShortCycle event occurs and the ShortCycle MFR_CHAN_CONFIG bit is not set, the PWM channel state machine will complete its TOFF_DELAY and TOFF_FALL operations as previously commanded by the user.
MFR_CONFIG_ALL General purpose configuration command common to multiple ADI products.
BIT MEANING 7 Enable Fault Logging 6 Ignore Resistor Configuration Pins 5 Mask PMBus, Part II, Section 10.9.1 Violations 4 Disable SYNC output 3 Enable 255ms PMBus timeout 2 A valid PEC required for PMBus writes to be accepted. If this bit is not
set, the part will accept commands with invalid PEC. 1 Enable the use of PMBus clock stretching 0 Execute CLEAR_FAULTS on rising edge of either RUN pin.
This command has one data byte.

ON/OFF/MARGIN

COMMAND NAME ON_OFF_CONFIG OPERATION
MFR_RESET

CMD CODE DESCRIPTION

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE

0x02 RUN pin and PMBus bus on/off command configuration. R/W Byte Y

Reg

0x1E

0x01 Operating mode control. On/off, margin high and margin R/W Byte Y

Reg

low.

0x80

0xFD Commanded reset without requiring a power-down.

Send Byte N

For more information www.analog.com

Rev. A
79

LTM4678

PMBus COMMAND DETAILS
ON_OFF_CONFIG
The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to turn the PWM channel on and off.
Supported Values:
VALUE MEANING 0x1F OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off. 0x1E OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when commanded off. 0x17 RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored. 0x16 RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored.

Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored. This command has one data byte.

OPERATION

The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in the commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation command is sequence off. If VIN is applied to a part with factory default programming and the VOUT_CONFIG resistor configuration pins are not installed, the outputs will be commanded off.

The part defaults to the Sequence Off state.

This command has one data byte.

Supported Values:

VALUE MEANING

0xA8 Margin high.

0x98 Margin low.

0x80 0x40*

On (VOUT back to nominal even if bit 3 of ON_OFF_CONFIG is not set). Soft off (with sequencing).

0x00* Immediate off (no sequencing).

*Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set.

Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored. This command has one data byte.

MFR_RESET

This command provides a means to reset the LTM4678 from the serial bus. This forces the LTM4678 to turn off both PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start of both PWM channels, if enabled.

This write-only command has no data bytes.
Rev. A

For more information www.analog.com

LTM4678

PMBus COMMAND DETAILS
PWM CONFIGURATION

COMMAND NAME MFR_PWM_COMP MFR_PWM_MODE MFR_PWM_CONFIG
FREQUENCY_SWITCH

CMD CODE DESCRIPTION 0xD3 PWM loop compensation configuration 0xD4 Configuration for the PWM engine. 0xF5 Set numerous parameters for the DC/DC controller including phasing. 0x33 Switching frequency of the controller.

TYPE R/W Byte R/W Byte R/W Byte

PAGED Y Y N

DATA

DEFAULT

FORMAT UNITS NVM VALUE

Reg

Y 0x28

Reg

Y 0xC7

Reg

Y 0x10

R/W

L11 kHz Y 350

Word

0xFABC

MFR_PWM_MODE
The MFR_PWM_MODE command sets important PWM controls for each channel.
The MFR_PWM_MODE command allows the user to program the PWM controller to use discontinuous (pulse-skipping mode), or forced continuous conduction mode.

BIT MEANING
7 Use High Range of ILIMIT 0b Low Current Range 1b High Current Range
6 Enable Servo Mode
5 External temperature sense:
0: VBE measurement. Now reserved, VBE only supported. 4 Page 0 Only: Use of TSNS1a-Sensed Temperature Telemetry 0 - Temperature sensed via TSNS1a is used to temperature-correct the current-sense information digitized by Channel 1's current sense input, ISNS1a+/ISNS1a. 1 - Temperature sensed via TSNS0a is used to temperature-correct the current-sense information digitized by Channel 1's current sense input, ISNS1a+/ISNS1a. Telemetry obtained from the thermal sensor connected to TSNS1a can be external to the module, if desired. 3 Reserved

2 1 1b 0b Bit[0] 0b 1b

Reserved, always low DCR current sense VOUT Range The maximum output voltage is 2.75V The maximum output voltage is 3.6V Mode Discontinuous Forced Continuous

Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command. Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing this bit when the channel is active will generate a CML fault.

Bit [6] The LTM4678 will not servo while the part is OFF, ramping on or ramping off. When set to a one, the output servo is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC and the VOUT_COMMAND (or the appropriate margined value).

The LTM4678 computes temperature in °C from VBE measured by the ADC at the TSNSn pin as T = (G · VBE · q/(K · ln(16))) 273.15 + O

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Rev. A
81

LTM4678

PMBus COMMAND DETAILS
For both equations, G = MFR_TEMP_1_GAIN · 214, and O = MFR_TEMP_1_OFFSET

Bit[2] is now reserved, and Ultra Low DCR mode is default.
Bit[1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing this bit when the channel is active will generate a CML fault.
Bit[0] determines if the PWM mode of operation is discontinuous (pulse-skipping mode), or forced continuous conduction mode. Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of this bit. This command has one data byte.

MFR_PWM_COMP The MFR_PWM_COMP command sets the gm of the PWM channel error amplifiers and the value of the internal RITHn compensation resistors. This command affects the loop gain of the PWM output which may require modifications to the external compensation network.

BIT BIT [7:5]
000b 001b 010b 011b 100b 101b 110b 111b BIT [4:0] 00000b 00001b 00010b 00011b 00100b 00101b 00110b 00111b 01000b 01001b 01010b 01011b 01100b 01101b 01110b 01111b

MEANING Error Amplifier GM Adjust (ms) 1.00 1.68 2.35 3.02 3.69 4.36 5.04 5.73 RITH (k) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.5 3 3.5 4 4.5 5 5.5

Rev. A

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LTM4678

PMBus COMMAND DETAILS

10000b

10001b

10010b

10011b

10100b

10101b

10110b

10111b

11000b

11001b

11010b

11011b

11100b

11101b

11110b

11111b

This command has one data byte.

MFR_PWM_CONFIG

The MFR_PWM_CONFIG command sets the switching frequency phase offset with respect to the falling edge of the SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the channels must be commanded off. If either channel is in the RUN state and this command is written, the command will be NACK'd and a BUSY fault will be asserted.

BIT 7 [6:5] 00b 01b 10b 11b 4
3 BIT [2:0]
000b 001b 010b 011b 100b 101b 110b

MEANING

Reserved

Input current sense gain. 2x gain. 0mV to 50mV range.

4x gain. 0mV to 20mV range.

8x gain. 0mV to 5mV range.

Reserved

Share Clock Enable : If this bit is 1, the SHARE_CLK pin will not be released until VIN > VIN_ON. The SHARE_CLK pin will be pulled low when VIN < VIN_OFF. If this bit is 0, the SHARE_ CLK pin will not be pulled low when VIN < VIN_OFF except for the initial application of VIN.

Reserved

CHANNEL 0 (DEGREES) CHANNEL 1 (DEGREES)

180

270

240

120

240

120

300

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Rev. A
83

LTM4678

PMBus COMMAND DETAILS

FREQUENCY_SWITCH The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of the LTM4678.

Supported Frequencies:

VALUE [15:0]

RESULTING FREQUENCY (TYP)

0x0000

External Oscillator

0xF3E8

250kHz

0xFABC

350kHz

0xFB52

425kHz

0xFBE8

500kHz

0x023F

575kHz

0x028A

650kHz

0x02EE

750kHz

0x03E8

1000kHz

The part must be in the OFF state to process this command. The RUN pin must be low or both channels must be commanded off. If the part is in the RUN state and this command is written, the command will be NACK'd and a BUSY fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be detected as the PLL locks onto the new frequency.

This command has two data bytes and is formatted in Linear_5s_11s format.

VOLTAGE

Input Voltage and Limits

COMMAND NAME VIN_OV_FAULT_LIMIT

CMD CODE DESCRIPTION 0x55 Input supply overvoltage fault limit.

VIN_UV_WARN_LIMIT

0x58 Input supply undervoltage warning limit.

VIN_ON VIN_OFF MFR_ICHIP_CAL_GAIN

0x35 Input voltage at which the unit should start power conversion.
0x36 Input voltage at which the unit should stop power conversion.
0xF7 The resistance value of the VIN pin filter element in milliohms

TYPE
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word

PAGED N

DATA FORMAT
L11

L11

UNITS V V V V m

DEFAULT NVM VALUE

15.5

0xD3E0

4.65

D12A

4.75

D130

4.5

D120

1000

0x03E8

VIN_OV_FAULT_LIMIT
The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes an input overvoltage fault. This command has two data bytes in Linear_5s_11s format.

Rev. A

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LTM4678

PMBus COMMAND DETAILS

VIN_UV_WARN_LIMIT
The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC that causes an input undervoltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON command and the unit has been enabled. If the VIN Voltage drops below the VIN_OV_WARN_LIMIT the device:
· Sets the INPUT Bit Is the STATUS_WORD · Sets the VIN Undervoltage Warning Bit in the STATUS_INPUT Command · Notifies the Host by Asserting ALERT, unless Masked

VIN_ON The VIN_ON command sets the input voltage, in Volts, at which the unit starts power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.

VIN_OFF The VIN_OFF command sets the input voltage, in Volts, at which the unit stops power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.

MFR_ICHIP_CAL_GAIN
The MFR_ICHIP_CAL_GAIN command is used to set the resistance value of the VIN pin filter element in milliohms. (See also READ_VIN). Set MFR_RVIN equal to 0 if no filter element is used.
This command has two data bytes and is formatted in Linear_5s_11s format.

Output Voltage and Limits

COMMAND NAME VOUT_MODE VOUT_MAX
VOUT_OV_FAULT_ LIMIT

CMD CODE 0x20 0x24
0x40

DESCRIPTION
Output voltage format and exponent (212).
Upper limit on the output voltage the unit can command regardless of any other commands.
Output overvoltage fault limit.

VOUT_OV_WARN_ LIMIT

0x42 Output overvoltage warning limit.

VOUT_MARGIN_HIGH
VOUT_COMMAND VOUT_MARGIN_LOW
VOUT_UV_WARN_ LIMIT VOUT_UV_FAULT_ LIMIT MFR_VOUT_MAX

0x25 Margin high output voltage set point. Must be greater than VOUT_ COMMAND.
0x21 Nominal output voltage set point.
0x26 Margin low output voltage set point. Must be less than VOUT_ COMMAND.
0x43 Output undervoltage warning limit.
0x44 Output undervoltage fault limit.
0xA5 Maximum allowed output voltage.

TYPE R Byte
R/W Word
R/W Word R/W Word R/W Word
R/W Word R/W Word
R/W Word R/W Word R Word

PAGED Y Y
Y Y Y
Y Y
Y Y Y

DATA FORMAT
Reg L16
L16 L16 L16
L16 L16
L16 L16 L16

UNITS
V
V V V
V V
V V V

DEFAULT

NVM

VALUE

212

0x14

3.6

0x399A

1.1

0x119A

1.075

0x1133

1.05

0x10CD

1.0

0x1000

0.95

0x0F33

0.925

0x0ECD

0.9

0x0E66

3.6 0x0399

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Rev. A
85

LTM4678
PMBus COMMAND DETAILS
VOUT_MODE The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode (only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write commands.
This read-only command has one data byte.
VOUT_MAX The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can command regardless of any other commands or combinations. The maximum allowed value of this command is 3.6V. The maximum output voltage the LTM4678 can produce is 3.4V including VOUT_MARGIN_HIGH. However, the VOUT_OV_FAULT_LIMIT can be commanded as high as 3.6V.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_OV_FAULT_LIMIT The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured by the OV supervisor comparator at the sense pins, in volts, which causes an output overvoltage fault.
If the VOUT_OV_FAULT_LIMIT is modified and the part is in the RUN state, allow 10ms after the command is modified to assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and 6 of MFR_COMMON. Either bit is low if the part is busy. If this wait time is not honored and the VOUT_COMMAND is modified above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable behavior and possible damage to the switcher.
If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN or 0x00, the FAULT pin will not assert if VOUT_OV_FAULT is propagated. The LTM4678 will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_OV_WARN_LIMIT The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured by the ADC at the sense pins, in volts, which causes an output voltage high warning. The MFR_VOUT_PEAK value can be used to determine if this limit has been exceeded.
In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:
· Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
· Sets the VOUT bit in the STATUS_WORD
· Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command
· Notifies the host by asserting ALERT pin, unless masked
This condition is detected by the ADC so the response time may be up to tCONVERT. This command has two data bytes and is formatted in Linear_16u format.

Rev. A

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LTM4678
PMBus COMMAND DETAILS
VOUT_MARGIN_HIGH The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in Volts, when the OPERATION command is set to "Margin High". The value should be greater than VOUT_COMMAND. The maximum guaranteed value on VOUT_MARGIN_HIGH is 3.7V. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format.
VOUT_COMMAND The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed value on VOUT is 3.6V. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format.
VOUT_MARGIN_LOW The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts, when the OPERATION command is set to "Margin Low". The value must be less than VOUT_COMMAND. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_WARN_LIMIT The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured by the ADC at the sense pins, in volts, which causes an output voltage low warning. In response to the VOUT_UV_WARN_LIMIT being exceeded, the device: · Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE · Sets the VOUT bit in the STATUS_WORD · Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command · Notifies the host by asserting ALERT pin, unless masked This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_FAULT_LIMIT The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured by the UV supervisor comparator at the sense pins, in volts, which causes an output undervoltage fault. This command has two data bytes and is formatted in Linear_16u format.

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Rev. A
87

LTM4678

PMBus COMMAND DETAILS
MFR_VOUT_MAX
The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel, including VOUT_OV_FAULT_ LIMIT. If the output voltages are set to high range (Bit 6 of MFR_PWM_CONFIG set to a 0) MFR_VOUT_MAX is 3.6V. If the output voltage is set to low range (Bit 6 of MFR_PWM_CONFIG set to a 1) the MFR_VOUT_MAX is 2.75V. Entering a VOUT_COMMAND value greater than this will result in a CML fault and the output voltage setting will be clamped to the maximum level. This will also result in Bit 3 VOUT_MAX_Warning in the STATUS_VOUT command being set.
This read only command has 2 data bytes and is formatted in Linear_16u format.

OUTPUT CURRENT AND LIMITS

COMMAND NAME MFR_IOUT_CAL_GAIN
MFR_IOUT_CAL_GAIN_TC IOUT_OC_FAULT_LIMIT

CMD CODE DESCRIPTION

TYPE

0xDA

The ratio of the voltage at the current sense pins to the sensed current. For devices using a fixed current sense resistor, it is the resistance value in m.

R Word

0xF6 Temperature coefficient of the current R/W Word sensing element.

0x46 Output overcurrent fault limit.

R/W Word

PAGED Y
Y Y

DATA FORMAT
L11
CF L11

UNITS m
A

IOUT_OC_WARN_LIMIT

0x4A Output overcurrent warning limit. R/W Word Y

L11

NVM
Factory Only NVM

DEFAULT VALUE
0.68 Typical 0xD02C

3800

0x0ED8

40.0

0xE280

30.0

0xDBC0

MFR_IOUT_CAL_GAIN
The MFR_IOUT_CAL_GAIN command is used to set the resistance value of the current sense resistor in milliohms. (see also MFR_IOUT_CAL_GAIN_TC).
This command has two data bytes and is formatted in Linear_5s_11s format.

MFR_IOUT_CAL_GAIN_TC The MFR_IOUT_CAL_GAIN_TC command allows the user to program the temperature coefficient of the MFR_IOUT_ CAL_GAIN sense resistor or inductor DCR in ppm/°C. This command has two data bytes and is formatted in 16-bit 2's complement integer ppm. N = 32768 to 32767 · 106. Nominal temperature is 27°C. The MFR_IOUT_CAL_GAIN is multiplied by:
[1.0 + MFR_IOUT_CAL_GAIN_TC · (READ_TEMPERATURE_127)]. DCR sensing will have a typical value of 3900.

The MFR_IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT, MFR_IOUT_PEAK, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT.

Rev. A

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LTM4678

PMBus COMMAND DETAILS

IOUT_OC_FAULT_LIMIT

The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in Amperes. When the controller is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The following table lists the progammable peak output current limit value in mV between ISENSE+ and ISENSE. The actual value of current limit is (ISENSE+ ISENSE)/MFR_IOUT_CAL_GAIN in Amperes.

BASED ON INDUCTOR CURRENT = 50% OF MAX LOAD OF 25A FOR WORSE CASE, THESE ARE APPROXIMATES, SO USE GUARDBAND AND CHECK

MFR_PWM_MODE[7] = 1 High Current Range (mV)

~ILPeak (A)

~IOUT (A)

MFR_PWM_MODE[7] = 0 Low Current Range (mV)

~ ILPeak (A)

~ IOUT (A)

17.73

26.07

20.07

9.85

14.49

8.49

18.86

27.35

21.35

10.48

15.41

9.41

20.42

30.03

24.03

11.34

16.68

10.68

21.14

31.09

25.09

11.74

17.26

11.26

22.27

32.75

26.75

12.37

18.19

12.19

23.41

34.43

28.43

13.01

19.13

13.13

24.55

36.10

30.10

13.64

20.06

14.06

Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation:

Peak Current Limit = MFR_IOUT_CAL_GAIN · (1 + MFR_IOUT_CAL_GAIN_TC · (READ_TEMPERTURE_1-27.0)). MFR_IOUT_CAL_GAIN is Set at Production Test.

The LTM4678 automatically convert currents to the appropriate internal bit value.

The IOUT range is set with bit 7 of the MFR_PWM_MODE command. The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.

If the IOUT_OC_FAULT_LIMIT is exceeded, the device:

· Sets the IOUT bit in the STATUS word

· Sets the IOUT Overcurrent fault bit in the STATUS_IOUT · Notifies the host by asserting ALERT, unless masked This command has two data bytes and is formatted in Linear_5s_11s format.

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Rev. A
89

LTM4678

PMBus COMMAND DETAILS
IOUT_OC_WARN_LIMIT This command sets the value of the output current measured by the ADC that causes an output overcurrent warning in Amperes. The READ_IOUT value will be used to determine if this limit has been exceeded. In response to the IOUT_OC_WARN_LIMIT being exceeded, the device: · Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE · Sets the IOUT bit in the STATUS_WORD · Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and · Notifies the host by asserting ALERT pin, unless masked The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL. This command has two data bytes and is formatted in Linear_5s_11s format

Input Current and Limits

COMMAND NAME

CMD CODE DESCRIPTION

MFR_IIN_CAL_GAIN

0xE8 The resistance value of the input current sense element in m.

TYPE R/W Word

DATA FORMAT
L11

UNITS m

DEFAULT

NVM

VALUE

2.000

0xC200

MFR_IIN_CAL_GAIN
The MFR_IIN_CAL_GAIN command is used to set the resistance value of the input current sense resistor in milliohms. (see also READ_IIN).
This command has two data bytes and is formatted in Linear_5s_11s format.

COMMAND NAME IIN_OC_WARN_LIMIT

CMD CODE DESCRIPTION
0x5D Input overcurrent warning limit.

TYPE PAGED R/W Word N

DATA FORMAT
L11

UNITS A

DEFAULT NVM VALUE

10.0

0xD280

IIN_OC_WARN_LIMIT The IIN_OC_WARN_LIMIT command sets the value of the input current measured by the ADC, in amperes, that causes a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has been exceeded. In response to the IIN_OC_WARN_LIMIT being exceeded, the device: · Sets the OTHER bit in the STATUS_BYTE · Sets the INPUT bit in the upper byte of the STATUS_WORD · Sets the IIN Overcurrent Warning bit[1] in the STATUS_INPUT command, and · Notifies the host by asserting ALERT pin This command has two data bytes and is formatted in Linear_5s_11s format.

Rev. A

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LTM4678

PMBus COMMAND DETAILS
TEMPERATURE

Power Stage DCR Temperature Calibration

COMMAND NAME MFR_TEMP_1_GAIN
MFR_TEMP_1_OFFSET

CMD CODE DESCRIPTION
0xF8 Sets the slope of the external temperature sensor.
0xF9 Sets the offset of the external temperature sensor.

TYPE R/W Word
R/W Word

PAGED Y
Y

DATA

DEFAULT

FORMAT UNITS NVM VALUE

Y 0.995

0x3FAE

L11

0.0

0x8000

MFR_TEMP_1_GAIN
The MFR_TEMP_1_GAIN command will modify the slope of the power stage sensor to account for non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in 16-bit 2's complement integer. The effective gain adjustment is N · 214. The nominal value is 1. N = 8192 to 32767

MFR_TEMP_1_OFFSET
The MFR_TEMP_1_OFFSET command will modify the offset of the power stage temperature sensor to account for non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor due to location.
This command has two data bytes and is formatted in Linear_5s_11s format. The part starts the calibration with a 273.15 so the default adjustment is zero.
Power Stage Temperature Limits

COMMAND NAME OT_FAULT_LIMIT
OT_WARN_LIMIT
UT_FAULT_LIMIT

CMD CODE DESCRIPTION

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM

VALUE

0x4F Power stage overtemperature fault R/W Word Y

L11

limit.

128.0

0xF200

0x51 Power stage overtemperature warning limit.

R/W Word Y

L11

125.0

0xEBE8

0x53 Power stage undertemperature fault R/W Word Y

L11

limit.

45.0

0xE530

OT_FAULT_LIMIT
The OT_FAULT_LIMIT command sets the value of the power stage temperature measured by the ADC, in degrees Celsius, which causes an overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.
This command has two data bytes and is formatted in Linear_5s_11s format.

OT_WARN_LIMIT
The OT_WARN_LIMIT command sets the value of the power stage temperature measured by the ADC, in degrees Celsius, which causes an overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.

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Rev. A
91

LTM4678
PMBus COMMAND DETAILS
In response to the OT_WARN_LIMIT being exceeded, the device: · Sets the TEMPERATURE bit in the STATUS_BYTE · Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and · Notifies the host by asserting ALERT pin, unless masked This command has two data bytes and is formatted in Linear_5s_11s format.
UT_FAULT_LIMIT The UT_FAULT_LIMIT command sets the value of the power stage temperature measured by the ADC, in degrees Celsius, which causes an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. Note: If the temp sensors are not installed, the UT_FAULT_LIMIT can be set to 275°C and UT_FAULT_LIMIT response set to ignore to avoid ALERT being asserted. This command has two data bytes and is formatted in Linear_5s_11s format.

TIMING

Timing--On Sequence/Ramp

COMMAND NAME

CMD CODE DESCRIPTION

TON_DELAY

0x60 Time from RUN and/or Operation on to output rail turn-on.

TON_RISE

0x61 Time from when the output starts to rise until the output voltage reaches the VOUT commanded value.

TON_MAX_FAULT_LIMIT

0x62 Maximum time from the start of TON_ RISE for VOUT to cross the VOUT_UV_ FAULT_LIMIT.

VOUT_TRANSITION_RATE 0x27 Rate the output changes when VOUT commanded to a new value.

DATA TYPE PAGED FORMAT UNITS

R/W Word Y

L11

R/W Word Y

L11

R/W Word Y

L11

R/W Word Y

L11 V/ms

NVM Y Y
Y
Y

DEFAULT VALUE
0.0 0x8000
3.0 0xC300
5.0 0xCA80
0.001 0x8042

TON_DELAY
The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output voltage starts to rise. Values from 0ms to 83 seconds are valid. The resulting turn-on delay will have a typical delay of 270µs for TON_DELAY = 0 and an uncertainty of ±50µs for all values of TON_DELAY.
This command has two data bytes and is formatted in Linear_5s_11s format.

TON_RISE

The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during TON_RISE events. If TON_RISE is less than 0.25ms, the LTM4678 digital slope will be bypassed and the output voltage transition will only be controlled by the analog performance of the PWM switcher. The number of steps in TON_RISE is equal to TON_RISE (in ms)/0.1ms with an uncertainty of ±0.1ms.

This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. A

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LTM4678

PMBus COMMAND DETAILS
TON_MAX_FAULT_LIMIT
The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit.
A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely. The maximum limit is 83 seconds.
This command has two data bytes and is formatted in Linear_5s_11s format.
VOUT_TRANSITION_RATE
When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the output voltage to change this command set the rate in V/ms at which the output voltage changes. The commanded rate of change does not apply when the unit is commanded on or off. The maximum allowed slope is 4V/ms.
This command has two data bytes and is formatted in Linear_5s_11s format.

Timing--Off Sequence/Ramp

COMMAND NAME TOFF_DELAY
TOFF_FALL
TOFF_MAX_WARN_LIMIT

CMD CODE DESCRIPTION

TYPE

0x64 Time from RUN and/or Operation off to R/W Word the start of TOFF_FALL ramp.

0x65 Time from when the output starts to fall R/W Word until the output reaches zero volts.

0x66 Maximum allowed time, after TOFF_FALL R/W Word completed, for the unit to decay below 12.5%.

PAGED Y
Y
Y

DATA FORMAT
L11
L11
L11

UNITS ms
ms
ms

DEFAULT NVM VALUE

0.0

0x8000

3.0

0xC300

0x8000

TOFF_DELAY

The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output voltage starts to fall. Values from 0 to 83 seconds are valid. The resulting turn off delay will have a typical delay of 270µs for TOFF_DELAY = 0 and an uncertainty of ±50µs for all values of TOFF_DELAY. TOFF_DELAY is not applied when a fault event occurs

This command has two data bytes and is formatted in Linear_5s_11s format.

TOFF_FALL
The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output voltage is commanded to zero. It is the ramp time of the VOUT DAC. When the VOUT DAC is zero, the PWM output will be set to high impedance state.

The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate. The minimum supported fall time is 0.25ms. A value less than 0.25ms will result in a 0.25ms ramp. The maximum fall time is 1.3 seconds. The number of steps in TOFF_FALL is equal to TOFF_FALL (in ms)/0.1ms with an uncertainty of ±0.1ms.

In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current.

This command has two data bytes and is formatted in Linear_5s_11s format.

Rev. A

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LTM4678

PMBus COMMAND DETAILS
TOFF_MAX_WARN_LIMIT
The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the output voltage exceeds 12.5% of the programmed voltage before a warning is asserted. The output is considered off when the VOUT voltage is less than 12.5% of the programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete.
A data value of 0ms means that there is no limit and that the output voltage exceeds 12.5% of the programmed voltage indefinitely. Other than 0, values from 120ms to 524 seconds are valid.
This command has two data bytes and is formatted in Linear_5s_11s format.

Precondition for Restart

COMMAND NAME MFR_RESTART_ DELAY

CMD CODE DESCRIPTION
0xDC Minimum time the RUN pin is held low by the LTM4678.

TYPE PAGED R/W Word Y

DATA FORMAT
L11

UNITS ms

DEFAULT NVM VALUE

150

0xF258

MFR_RESTART_DELAY
This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms.
Note: The restart delay is different than the retry delay. The restart delay pulls RUN low for the specified time, after which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_ FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time, set the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_ RESTART_DELAY after the RUN pin is pulled high if the output decay bit 0 is enabled in MFR_CHAN_CONFIG and the output takes a long time to decay below 12.5% of the programmed value.
This command has two data bytes and is formatted in Linear_5s_11s format.

FAULT RESPONSE

Fault Responses All Faults

COMMAND NAME MFR_RETRY_ DELAY

CMD CODE DESCRIPTION

TYPE

0xDB Retry interval during FAULT retry R/W Word mode.

PAGED Y

DATA FORMAT
L11

UNITS ms

DEFAULT

NVM

VALUE

250

0xF3E8

MFR_RETRY_DELAY
This command sets the time in milliseconds between retries if the fault response is to retry the controller at specified intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 10µs increments.
Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of MFR_CHAN_CONFIG.
This command has two data bytes and is formatted in Linear_5s_11s format.

Rev. A

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LTM4678

PMBus COMMAND DETAILS

Fault Responses Input Voltage

COMMAND NAME

CMD CODE DESCRIPTION

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE

VIN_OV_FAULT_RESPONSE 0x56 Action to be taken by the device when an R/W Byte Y

Reg

input supply overvoltage fault is detected.

0x80

VIN_OV_FAULT_RESPONSE The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input overvoltage fault. The data byte is in the format given in Table 18. The device also: · Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE · Set the INPUT bit in the upper byte of the STATUS_WORD · Sets the VIN Overvoltage Fault bit in the STATUS_INPUT command, and · Notifies the host by asserting ALERT pin, unless masked This command has one data byte.

Fault Responses Output Voltage

COMMAND NAME

CMD CODE DESCRIPTION

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE

VOUT_OV_FAULT_RESPONSE 0x41 Action to be taken by the device when an R/W Byte Y

Reg

output overvoltage fault is detected.

0xB8

VOUT_UV_FAULT_RESPONSE 0x45 Action to be taken by the device when an R/W Byte Y

Reg

output undervoltage fault is detected.

0xB8

TON_MAX_FAULT_ RESPONSE

0x63 Action to be taken by the device when a R/W Byte Y

Reg

TON_MAX_FAULT event is detected.

0xB8

VOUT_OV_FAULT_RESPONSE The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output overvoltage fault. The data byte is in the format given in Table 14. The device also: · Sets the VOUT_OV bit in the STATUS_BYTE · Sets the VOUT bit in the STATUS_WORD · Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command · Notifies the host by asserting ALERT pin, unless masked The only values recognized for this command are: 0x00Part performs OV pull down only, or OV_PULLDOWN. 0x80The device shuts down (disables the output) and the unit does not attempt to retry. (PMBus, Part II, Section 10.7).

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Rev. A
95

LTM4678

PMBus COMMAND DETAILS

0xB8The device shuts down (disables the output) and device attempts to retry continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down.
0x4n The device shuts down and the unit does not attempt to retry. The output remains disabled until the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN. The OV fault must remain active for a period of n · 10µs, where n is a value from 0 to 7.
0x78+n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared or the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN. The OV fault must remain active for a period of n · 10µs, where n is a value from 0 to 7.
Any other value will result in a CML fault and the write will be ignored.
This command has one data byte.

Table 14. VOUT_OV_FAULT_RESPONSE Data Byte Contents BITS DESCRIPTION 7:6 Response For all values of bits [7:6], the LTM4678: · Sets the corresponding fault bit in the status commands and · Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs: · The device receives a CLEAR_FAULTS command. · The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or · Bias power is removed and reapplied to the LTM4678. 5:3 Retry Setting
2:0 Delay Time

VALUE 00 01
10 11

MEANING
Part performs OV pull down only or OV_PULLDOWN (i.e., turns off the top MOSFET and turns on lower MOSFET while VOUT is > VOUT_OV_FAULT).
The PMBus device continues operation for the delay time specified by bits [2:0] and the delay time unit specified for that particular fault. If the fault condition is still present at the end of the delay time, the unit responds as programmed in the Retry Setting (bits [5:3]).
The device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3].
Not supported. Writing this value will generate a CML fault.

000 The unit does not attempt to restart. The output remains disabled until the fault is cleared until the device is commanded OFF bias power is removed.
111 The PMBus device attempts to restart continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. Note: The retry interval is set by the MFR_RETRY_DELAY command.
000-111 The delay time in 10µs increments. This delay time determines how long the controller continues operating after a fault is detected. Only valid for deglitched off state.

VOUT_UV_FAULT_RESPONSE

The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output undervoltage fault. The data byte is in the format given in Table 8.

The device also:

· Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

· Sets the VOUT bit in the STATUS_WORD

· Sets the VOUT undervoltage fault bit in the STATUS_VOUT command

· Notifies the host by asserting ALERT pin, unless masked
Rev. A

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LTM4678

PMBus COMMAND DETAILS

The UV fault and warn are masked until the following criteria are achieved: 1) The TON_MAX_FAULT_LIMIT has been reached 2) The TON_DELAY sequence has completed 3) The TON_RISE sequence has completed 4) The VOUT_UV_FAULT_LIMIT threshold has been reached 5) The IOUT_OC_FAULT_LIMIT is not present
The UV fault and warn are masked whenever the channel is not active. The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing. This command has one data byte.

Table 15. VOUT_UV_FAULT_RESPONSE Data Byte Contents BITS DESCRIPTION 7:6 Response For all values of bits [7:6], the LTM4678: · Sets the corresponding fault bit in the status commands and · Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs: · The device receives a CLEAR_FAULTS command. · The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or · The device receives a RESTORE_USER_ALL command. · The device receives a MFR_RESET command. · The device supply power is cycled. 5:3 Retry Setting
2:0 Delay Time

VALUE 00 01
10 11
000 111
000-111

MEANING The PMBus device continues operation without interruption. (Ignores the fault functionally) The PMBus device continues operation for the delay time specified by bits [2:0] and the delay time unit specified for that particular fault. If the fault condition is still present at the end of the delay time, the unit responds as programmed in the Retry Setting (bits [5:3]). The device shuts down (disables the output) and responds according to the retry setting in bits [5:3]. Not supported. Writing this value will generate a CML fault.
The unit does not attempt to restart. The output remains disabled until the fault is cleared until the device is commanded OFF bias power is removed. The PMBus device attempts to restart continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. Note: The retry interval is set by the MFR_RETRY_DELAY command. The delay time in 10µs increments. This delay time determines how long the controller continues operating after a fault is detected. Only valid for deglitched off state.

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Rev. A
97

LTM4678

PMBus COMMAND DETAILS
TON_MAX_FAULT_RESPONSE The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX fault. The data byte is in the format given in Table 13. The device also: · Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE · Sets the VOUT bit in the STATUS_WORD · Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and · Notifies the host by asserting ALERT pin, unless masked A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0. Note: The PWM channel remains in discontinues mode until the TON_MAX_FAULT_LIMIT has been exceeded. This command has one data byte.

Fault Responses Output Current

COMMAND NAME

CMD CODE DESCRIPTION

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE

IOUT_OC_FAULT_RESPONSE 0x47 Action to be taken by the device when an R/W Byte Y

Reg

output overcurrent fault is detected.

0x00

IOUT_OC_FAULT_RESPONSE The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output overcurrent fault. The data byte is in the format given in Table 9. The device also: · Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE · Sets the IOUT_OC bit in the STATUS_BYTE · Sets the IOUT bit in the STATUS_WORD · Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and · Notifies the host by asserting ALERT pin, unless masked This command has one data byte.

Rev. A

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LTM4678

PMBus COMMAND DETAILS

Table 16. OUT_OC_FAULT_RESPONSE Data Byte Contents

BITS DESCRIPTION

VALUE MEANING

7:6 Response

00 The LTM4678 continues to operate indefinitely while

For all values of bits [7:6], the LTM4678: · Sets the corresponding fault bit in the status commands and

maintaining the output current at the value set by IOUT_OC_FAULT_LIMIT without regard to the output voltage (known as constant-current or brick-wall limiting).

· Notifies the host by asserting ALERT pin, unless masked.

01 Not supported.

The fault bit, once set, is cleared only when one or more of the following events occurs:
· The device receives a CLEAR_FAULTS command.

10 The LTM4678 continues to operate, maintaining the output current at the value set by IOUT_OC_FAULT_LIMIT without regard to the output voltage, for the delay time set by bits [2:0].

· The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or

If the device is still operating in current limit at the end of the delay time, the device responds as programmed by the Retry Setting in bits [5:3].

· The device receives a RESTORE_USER_ALL command. · The device receives a MFR_RESET command.

11 The LTM4678 shuts down immediately and responds as programmed by the Retry Setting in bits [5:3].

· The device supply power is cycled.

5:3 Retry Setting

000 The unit does not attempt to restart. The output remains disabled until the fault is cleared by cycling the RUN pin or removing bias power.

111 The device attempts to restart continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. Note: The retry interval is set by the MFR_RETRY_DELAY command.

2:0 Delay Time

000-111 The number of delay time units in 16ms increments. This delay time is used to determine the amount of time a unit is to continue operating after a fault is detected before shutting down. Only valid for deglitched off response.

Fault Responses IC Temperature

COMMAND NAME

CMD CODE DESCRIPTION

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE

MFR_OT_FAULT_

0xD6 Action to be taken by the device when an R Byte

Reg

0xC0

RESPONSE

internal overtemperature fault is detected.

MFR_OT_FAULT_RESPONSE The MFR_OT_FAULT_RESPONSE command byte instructs the device on what action to take in response to an internal overtemperature fault. The data byte is in the format given in Table 12. The LTM4678 also: · Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE · Sets the MFR bit in the STATUS_WORD, and · Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command · Notifies the host by asserting ALERT pin, unless masked This command has one data byte.

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Rev. A
99

LTM4678

PMBus COMMAND DETAILS

Table 17. Data Byte Contents MFR_OT_FAULT_RESPONSE BITS DESCRIPTION 7:6 Response For all values of bits [7:6], the LTM4678: · Sets the corresponding fault bit in the status commands and · Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs: · The device receives a CLEAR_FAULTS command. · The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or · Bias power is removed and reapplied to the LTM4678. 5:3 Retry Setting
2:0 Delay Time

VALUE 00 01 10 11
000 001-111
XXX

MEANING Not supported. Writing this value will generate a CML fault. Not supported. Writing this value will generate a CML fault The device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. The device's output is disabled while the fault is present. Operation resumes and the output is enabled when the fault condition no longer exists.
The unit does not attempt to restart. The output remains disabled until the fault is cleared. Not supported. Writing this value will generate CML fault. Not supported. Value ignored

Fault Responses External Temperature

COMMAND NAME OT_FAULT_ RESPONSE
UT_FAULT_ RESPONSE

CMD CODE DESCRIPTION
0x50 Action to be taken by the device when an external overtemperature fault is detected,
0x54 Action to be taken by the device when an external undertemperature fault is detected.

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE

R/W Byte Y

Reg

0xB8

R/W Byte Y

Reg

0xB8

OT_FAULT_RESPONSE The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an external overtemperature fault on the external temp sensors. The data byte is in the format given in Table 13. The device also: · Sets the TEMPERATURE bit in the STATUS_BYTE · Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and · Notifies the host by asserting ALERT pin, unless masked This command has one data byte.

UT_FAULT_RESPONSE

The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an external undertemperature fault on the external temp sensors. The data byte is in the format given in Table 13.

The device also:

· Sets the TEMPERATURE bit in the STATUS_BYTE

· Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and

· Notifies the host by asserting ALERT pin, unless masked

Rev. A

100

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LTM4678

PMBus COMMAND DETAILS

This condition is detected by the ADC so the response time may be up to tCONVERT. This command has one data byte.

Table 18. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE, OT_FAULT_RESPONSE, UT_FAULT_RESPONSE

BITS DESCRIPTION

VALUE MEANING

7:6 Response

00 The PMBus device continues operation without interruption.

For all values of bits [7:6], the LTM4678:

01 Not supported. Writing this value will generate a CML fault.

· Sets the corresponding fault bit in the status commands, and · Notifies the host by asserting ALERT pin, unless masked.

10 The device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3].

The fault bit, once set, is cleared only when one or more of the following events occurs:

11 Not supported. Writing this value will generate a CML fault.

· The device receives a CLEAR_FAULTS command.

· The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or

· The device receives a RESTORE_USER_ALL command.

· The device receives a MFR_RESET command.

· The device supply power is cycled.

5:3 Retry Setting

000 The unit does not attempt to restart. The output remains disabled until the fault is cleared until the device is commanded OFF bias power is removed.

111 The PMBus device attempts to restart continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. Note: The retry interval is set by the MFR_RETRY_DELAY command.

2:0 Delay Time

XXX Not supported. Values ignored

FAULT SHARING

Fault Sharing Propagation

COMMAND NAME
MFR_FAULT_ PROPAGATE

CMD CODE DESCRIPTION
0xD2 Configuration that determines which faults are propagated to the FAULT pins.

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE

R/W Word Y

Reg

Y 0x6993

MFR_FAULT_PROPAGATE
The MFR_FAULT_PROPAGATE command enables the faults that can cause the FAULTn pin to assert low. The command is formatted as shown in Table 19. Faults can only be propagated to the FAULTn pin if they are programmed to respond to faults.
This command has two data bytes.

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Rev. A
101

LTM4678

PMBus COMMAND DETAILS

Table 19. FAULTn Propagate Fault Configuration The FAULT0 and FAULT1 pins are designed to provide electrical notification of selected events to the user. Some of these events are common to both output
channels. Others are specific to an output channel. They can also be used to share faults between channels.

BIT(S) B[15]
B[14] b[13]
b[12] b[11] b[10] b[9] b[8]
b[7]
b[6] b[5] b[4] b[3] b[2]
b[1]
b[0]

SYMBOL VOUT disabled while not decayed.
Mfr_fault_propagate_short_CMD_cycle
Mfr_fault_propagate_ton_max_fault
Reserved Mfr_fault0_propagate_int_ot, Mfr_fault1_propagate_int_ot Reserved Reserved Mfr_fault0_propagate_ut, Mfr_fault1_propagate_ut
Mfr_fault0_propagate_ot, Mfr_fault1_propagate_ot
Reserved Reserved Mfr_fault0_propagate_input_ov, Mfr_fault1_propagate_input_ov Reserved Mfr_fault0_propagate_iout_oc, Mfr_fault1_propagate_iout_oc
Mfr_fault0_propagate_vout_uv, Mfr_fault1_propagate_vout_uv
Mfr_fault0_propagate_vout_ov, Mfr_fault1_propagate_vout_ov

OPERATION This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG_LTM4678 is a zero. If the channel is turned off, by toggling the RUN pin or commanding the part OFF, and then the RUN is reasserted or the part is commanded back on before the output has decayed, VOUT will not restart until the 12.5% decay is honored. The FAULT pin is asserted during this condition if bit 15 is asserted. 0: No action 1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high tOFF(MIN) after sequence off. 0: No action if a TON_MAX_FAULT fault is asserted 1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted FAULT0 is associated with page 0 TON_MAX_FAULT faults FAULT1 is associated with page 1 TON_MAX_FAULT faults
0: No action if the MFR_OT_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted
0: No action if the UT_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 UT faults FAULT1 is associated with page 1 UT faults 0: No action if the OT_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 OT faults FAULT1 is associated with page 1 OT faults
0: No action if the VIN_OV_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted
0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 OC faults FAULT1 is associated with page 1 OC faults 0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 UV faults FAULT1 is associated with page 1 UV faults 0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted FAULT0 is associated with page 0 OV faults FAULT1 is associated with page 1 OV faults

Rev. A

102

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LTM4678

PMBus COMMAND DETAILS

Fault Sharing Response

COMMAND NAME

CMD CODE DESCRIPTION

MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the FAULT pin is asserted low.

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE

R/W Byte Y

Reg

0xC0

MFR_FAULT_RESPONSE
The MFR_FAULT_RESPONSE command instructs the device on what action to take in response to the FAULTn pin being pulled low by an external source.

Supported Values:
VALUE MEANING 0xC0 FAULT_INHIBIT The LTM4678 will three-state the output in response to the FAULT pin pulled low. 0x00 FAULT_IGNORE The LTM4678 continues operation without interruption.

The device also: · Sets the MFR Bit in the STATUS_WORD. · Sets Bit 0 in the STATUS_MFR_SPECIFIC Command to Indicate FAULTn Is Being Pulled Low · Notifies the Host by Asserting ALERT, Unless Masked This command has one data byte.

SCRATCHPAD

COMMAND NAME USER_DATA_00
USER_DATA_01 USER_DATA_02
USER_DATA_03 USER_DATA_04

CMD CODE DESCRIPTION
0xB0 OEM reserved. Typically used for part serialization.
0xB1 Manufacturer reserved for LTpowerPlay.
0xB2 OEM reserved. Typically used for part serialization.
0xB3 A NVM word available for the user.
0xB4 A NVM word available for the user.

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE

R/W Word N

Reg

R/W Word Y

Reg

R/W Word N

Reg

R/W Word Y

Reg

R/W Word N

Reg

0x0000

USER_DATA_00 through USER_DATA_04
These commands are non-volatile memory locations for customer storage. The customer has the option to write any value to the USER_DATA_nn at any time. However, the LTpowerPlay software and contract manufacturers use some of these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable inventory control and incompatibility with these products.
These commands have 2 data bytes and are in register format.

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Rev. A
103

LTM4678

PMBus COMMAND DETAILS

IDENTIFICATION

COMMAND NAME PMBus_REVISION
CAPABILITY
MFR_ID MFR_MODEL MFR_SPECIAL_ID

CMD CODE DESCRIPTION
0x98 PMBus revision supported by this device. Current revision is 1.2.
0x19 Summary of PMBus optional communication protocols supported by this device.
0x99 The manufacturer ID of the LTM4678 in ASCII.
0x9A Manufacturer part number in ASCII.
0xE7 Manufacturer code representing the LTM4678.

TYPE R Byte

PAGED N

DATA FORMAT
Reg

UNITS

R Byte

Reg

R String

ASC

R String

ASC

R Word

Reg

DEFAULT NVM VALUE

0x22

0xB0

LTC LTM4678
0x410x

PMBus_REVISION
The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTM4678 is PMBus Version 1.2 compliant in both Part I and Part II.
This read-only command has one data byte.

CAPABILITY This command provides a way for a host system to determine some key capabilities of a PMBus device. The LTM4678 supports packet error checking, 400kHz bus speeds, and ALERT pin. This read-only command has one data byte.

MFR_ID The MFR_ID command indicates the manufacturer ID of the LTM4678 using ASCII characters. This read-only command is in block format.

MFR_MODEL The MFR_MODEL command indicates the manufacturer's part number of the LTM4678 using ASCII characters. This read-only command is in block format.

MFR_SPECIAL_ID
The 16-bit word representing the part name and revision. 0x41 denotes the part is an LTM4678, XX is adjustable by the manufacturer.
This read-only command has two data bytes.

Rev. A

104

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LTM4678

PMBus COMMAND DETAILS

FAULT WARNING AND STATUS

COMMAND NAME CLEAR_FAULTS SMBALERT_MASK

CMD CODE DESCRIPTION 0x03 Clear any fault bits that have been set. 0x1B Mask activity.

TYPE Send Byte Block R/W

PAGED N Y

FORMAT UNITS Reg

MFR_CLEAR_PEAKS

0xE3 Clears all peak values.

Send Byte

STATUS_BYTE

0x78 One byte summary of the unit's fault R/W Byte

Reg

condition.

STATUS_WORD

0x79 Two byte summary of the unit's fault R/W Word

Reg

condition.

STATUS_VOUT

0x7A Output voltage fault and warning

R/W Byte

Reg

status.

STATUS_IOUT

0x7B Output current fault and warning

R/W Byte

Reg

status.

STATUS_INPUT

0x7C Input supply fault and warning status. R/W Byte

Reg

STATUS_ TEMPERATURE

0x7D External temperature fault and warning R/W Byte

Reg

status for READ_TEMERATURE_1.

STATUS_CML

0x7E Communication and memory fault and R/W Byte

Reg

warning status.

STATUS_MFR_ SPECIFIC

0x80 Manufacturer specific fault and state R/W Byte

Reg

information.

MFR_PADS

0xE5 Digital status of the I/O pads.

R Word

Reg

MFR_COMMON

0xEF Manufacturer status bits that are

R Byte

Reg

common across multiple ADI chips.

DEFAULT NVM VALUE
NA Y See CMD
Details NA NA
NA
NA
NA
NA NA
NA
NA
NA NA

CLEAR_FAULTS
The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault occurs within that time frame it may be cleared before the status register is set.
This write-only command has no data bytes.
The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut down for a fault condition are restarted when:
· The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
· MFR_RESET command is issued.
· Bias power is removed and reapplied to the integrated circuit

SMBALERT_MASK

The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they are asserted.

Figure 33 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits in the mask byte align with bits in the specified status register. For example, if the STATUS_TEMPERATURE command code is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning

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LTM4678

PMBus COMMAND DETAILS

would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE bits would continue to assert ALERT if set.
Figure 50 shows an example of the Block Write Block Read Process Call protocol used to read back the present state of any supported status register, again without PEC.
SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS_LTM4678. Factory default masking for applicable status registers is shown below. Providing an unsupported command code to SMBALERT_MASK will generate a CML for Invalid/Unsupported Data.

SMBALERT_MASK Default Setting: (Refer Also to Figure 2)

STATUS RESISTER ALERT Mask Value MASKED BITS

STATUS_VOUT

0x00

None

STATUS_IOUT

0x00

None

STATUS_TEMPERATURE

0x00

None

STATUS_CML

0x00

None

STATUS_INPUT

0x00

None

STATUS_MFR_SPECIFIC

0x11

Bit 4 (internal PLL unlocked), bit 0 (FAULT pulled low by external device)

SLAVE ADDRESS

SMBALERT_MASK COMMAND CODE

STATUS_x COMMAND CODE

MASK BYTE

4678 F52

Figure 52. Example of Writing SMBALERT_MASK

SLAVE ADDRESS

SMBALERT_MASK COMMAND CODE

BLOCK COUNT (= 1)

STATUS_x COMMAND CODE

...

SLAVE ADDRESS

BLOCK COUNT (= 1)

MASK BYTE NA P

4678 F53

Figure 53. Example of Reading SMBALERT_MASK

MFR_CLEAR_PEAKS
The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A MFR_RESET command will also clear the MFR_*_PEAK data values.
This write-only command has no data bytes.

STATUS_BYTE
The STATUS_BYTE command returns one byte of information with a summary of the most critical faults. This is the lower byte of the status word.

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LTM4678

PMBus COMMAND DETAILS

STATUS_BYTE Message Contents:

BIT STATUS BIT NAME MEANING

BUSY

A fault was declared because the LTM4678 was unable to respond.

OFF

This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not being enabled.

VOUT_OV

An output overvoltage fault has occurred.

IOUT_OC

An output overcurrent fault has occurred.

VIN_UV

Not supported (LTM4678 returns 0).

TEMPERATURE A temperature fault or warning has occurred.

CML

A communications, memory or logic fault has occurred.

0* NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred.

*ALERT can be asserted if either of these bits is set. They may be cleared by writing a 1 to their bit position in the STATUS_BYTE, in lieu of a CLEAR_ FAULTS command.

This command has one data byte.

STATUS_WORD
The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the STATUS_WORD is the same as the STATUS_BYTE command.

STATUS_WORD High Byte Message Contents:

BIT

STATUS BIT NAME MEANING

VOUT

An output voltage fault or warning has occurred.

IOUT

An output current fault or warning has occurred.

INPUT

An input voltage fault or warning has occurred.

MFR_SPECIFIC A fault or warning specific to the LTM4678 has occurred.

POWER_GOOD# The POWER_GOOD state is false if this bit is set.

FANS

Not supported (LTM4678 returns 0).

OTHER

Not supported (LTM4678 returns 0).

UNKNOWN

Not supported (LTM4678 returns 0).

If any of the bits in the upper byte are set, NONE_OF_THE_ABOVE is asserted. This command has two data bytes.

STATUS_VOUT

The STATUS_VOUT command returns one byte of VOUT status information.

STATUS_VOUT Message Contents:

BIT MEANING

VOUT overvoltage fault.

VOUT overvoltage warning.

VOUT undervoltage warning.

VOUT undervoltage fault.

VOUT max warning.

TON max fault.

TOFF max fault.

Not supported (LTM4678 returns 0).

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107

LTM4678

PMBus COMMAND DETAILS
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event. This command has one data byte.

STATUS_IOUT

The STATUS_IOUT command returns one byte of IOUT status information.

STATUS_IOUT Message Contents:

BIT MEANING

IOUT overcurrent fault.

Not supported (LTM4678 returns 0).

IOUT overcurrent warning.

4:0 Not supported (LTM4678 returns 0).

The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event. This command has one data byte.

STATUS_INPUT

The STATUS_INPUT command returns one byte of VIN (VINSNS) status information.

STATUS_INPUT Message Contents:

BIT MEANING

VIN overvoltage fault.

Not supported (LTM4678 returns 0).

VIN undervoltage warning.

Not supported (LTM4678 returns 0).

Unit off for insufficient VIN.

Not supported (LTM4678 returns 0).

IIN overcurrent warning.

Not supported (LTM4678 returns 0).

The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command.

Any supported fault bit in this command will initiate an ALERT event. Bit 3 of this command is not latched and will not generate an ALERT even if it is set. This command has one data byte.

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LTM4678

PMBus COMMAND DETAILS

STATUS_TEMPERATURE
The STATUS_TEMPERATURE commands returns one byte with status information on temperature. This is a paged command and is related to the respective READ_TEMPERATURE_1 value.

STATUS_TEMPERATURE Message Contents:

BIT MEANING

External overtemperature fault.

External overtemperature warning.

Not supported (LTM4678 returns 0).

External undertemperature fault.

3:0 Not supported (LTM4678 returns 0).

.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command.

This command has one data byte.

STATUS_CML The STATUS_CML command returns one byte of status information on received commands, internal memory and logic.

STATUS_CML Message Contents:

BIT MEANING

Invalid or unsupported command received.

Invalid or unsupported data received.

Packet error check failed.

Memory fault detected.

Processor fault detected.

Reserved (LTM4678 returns 0).

Other communication fault.

Other memory or logic fault.

If either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. Continued operation of the part is not recommended if these bits are continuously set.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte.

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LTM4678

PMBus COMMAND DETAILS
STATUS_MFR_SPECIFIC The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information. The format for this byte is:
BIT MEANING 7 Internal Temperature Fault Limit Exceeded. 6 Internal Temperature Warn Limit Exceeded. 5 Factory Trim Area NVM CRC Fault. 4 PLL is Unlocked 3 Fault Log Present 2 VDD33 UV or OV Fault 1 ShortCycle Event Detected 0 FAULT Pin Asserted Low by External Device
If any of these bits are set, the MFR bit in the STATUS_WORD will be set, and ALERT may be asserted. The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. However, the fault log present bit can only be cleared by issuing the MFR_FAULT_LOG_CLEAR command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte.

MFR_PADS
This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit assignments of this command are as follows:

BIT ASSIGNED DIGITAL PIN 15 VDD33 OV Fault 14 VDD33 UV Fault 13 Reserved 12 Reserved 11 ADC Values Invalid, Occurs During Start-Up. May Occur Briefly on Current Measurement Channels During Normal Operation 10 SYNC clocked by external device (when LTM4678 configured to drive SYNC pin) 9 Channel 1 Power Good 8 Channel 0 Power Good 7 LTM4678 Driving RUN1 Low 6 LTM4678 Driving RUN0 Low 5 RUN1 Pin State 4 RUN0 Pin State 3 LTM4678 Driving FAULT1 Low 2 LTM4678 Driving FAULT0 Low 1 FAULT1 Pin State 0 FAULT0 Pin State

A 1 indicates the condition is true.

This read-only command has two data bytes.

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LTM4678

PMBus COMMAND DETAILS
MFR_COMMON The MFR_COMMON command contains bits that are common to all ADI digital power and telemetry products.
BIT MEANING 7 Module Not Driving ALERT Low 6 LTM4678 Not Busy 5 Calculations Not Pending 4 LTM4678 Outputs Not in Transition 3 NVM Initialized 2 Reserved 1 SHARE_CLK Timeout 0 WP Pin Status
This read-only command has one data byte.

MFR_INFO
The MFR_INFO command contains additional status bits that are LTC3884-specific and may be common to multiple ADI PSM products.

MFR_INFO Data Contents:

BIT MEANING

15:5 Reserved.

EEPROM ECC status.

0: Corrections made in the EEPROM user space.

1: No corrections made in the EEPROM user space.

3:0 Reserved

EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or an EEPROM bulk read operation. This read-only command has two data bytes.

TELEMETRY
COMMAND NAME READ_VIN READ_IIN READ_VOUT READ_IOUT READ_TEMPERATURE_1
READ_TEMPERATURE_2
READ_FREQUENCY READ_POUT READ_PIN MFR_PIN_ACCURACY

CMD CODE DESCRIPTION

DEFAULT TYPE PAGED FORMAT UNITS NVM VALUE

0x88 Measured input supply voltage.

R Word N

L11

0x89 Measured input supply current.

R Word N

L11

0x8B Measured output voltage.

R Word Y

L16

0x8C Measured output current.

R Word Y

L11

0x8D Power stage temperature sensor. This is

R Word Y

L11

the value used for all temperature related

processing, including MFR_IOUT_CAL_GAIN.

0x8E Internal junction temperature. Does not affect R Word N

L11

any other controller commands.

0x95 Measured PWM switching frequency.

R Word Y

L11

0x96 Calculated output power.

R Word Y

L11

0x97 Calculated input power.

R Word N

L11

0xAC Returns the accuracy of the READ_PIN command R Byte N

5.0%

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LTM4678

PMBus COMMAND DETAILS

MFR_IOUT_PEAK

0xD7 Report the maximum measured value of

R Word Y

L11

READ_IOUT since last MFR_CLEAR_PEAKS.

MFR_VOUT_PEAK

0xDD Maximum measured value of READ_VOUT

R Word Y

L16

since last MFR_CLEAR_PEAKS.

MFR_VIN_PEAK

0xDE Maximum measured value of READ_VIN since R Word N

L11

last MFR_CLEAR_PEAKS.

MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of external

R Word Y

L11

Temperature (READ_TEMPERATURE_1) since

last MFR_CLEAR_PEAKS.

MFR_READ_IIN_PEAK

0xE1 Maximum measured value of READ_IIN

R Word N

L11

command since last MFR_CLEAR_PEAKS.

MFR_READ_ICHIP

0xE4 Measured current used by the LTM4678.

R Word N

L11

MFR_TEMPERATURE_2_PEAK 0xF4 Peak internal die temperature since last

R Word N

L11

MFR_CLEAR_PEAKS.

MFR_ADC_CONTROL

0xD8 ADC telemetry parameter selected for repeated R/W Byte N

Reg

fast ADC read back.

READ_VIN The READ_VIN command returns the measured VIN pin voltage, in volts added to READ_ICHIP · MFR_RVIN. This compensates for the IR voltage drop across the VIN filter element due to the supply current of the LTM4678. This read-only command has two data bytes and is formatted in Linear_5s_11s format.

READ_VOUT The READ_VOUT command returns the measured output voltage by the VOUT_MODE command. This read-only command has two data bytes and is formatted in Linear_16u format.

READ_IIN
The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor (see also MFR_IIN_CAL_GAIN).
This read-only command has two data bytes and is formatted in Linear_5s_11s format.

READ_IOUT The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of: a) the differential voltage measured across the ISENSE pins b) the IOUT_CAL_GAIN value c) the MFR_IOUT_CAL_GAIN_TC value, and d) READ_TEMPERATURE_1 value e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET This read-only command has two data bytes and is formatted in Linear_5s_11s format.

READ_TEMPERATURE_1 The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the power stage sense element. This read-only command has two data bytes and is formatted in Linear_5s_11s format.

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LTM4678
PMBus COMMAND DETAILS
READ_TEMPERATURE_2 The READ_TEMPERATURE_2 command returns the LTM4678's die temperature, in degrees Celsius, of the internal sense element. This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_FREQUENCY The READ_FREQUENCY command is a reading of the PWM switching frequency in kHz. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
READ_POUT The READ_POUT command is a reading of the DC/DC converter output power in Watts. POUT is calculated based on the most recent correlated output voltage and current reading. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
READ_PIN The READ_PIN command is a reading of the DC/DC converter input power in Watts. PIN is calculated based on the most recent input voltage and current reading. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
MFR_PIN_ACCURACY The MFR_PIN_ACCURACY command returns the accuracy, in percent, of the value returned by the READ_PIN command. There is one data byte. The value is 0.1% per bit which gives a range of ±0.0% to ±25.5%. This read-only command has one data byte and is formatted as an unsigned integer.
MFR_IOUT_PEAK The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_VOUT_PEAK The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_16u format.
MFR_VIN_PEAK The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement.

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LTM4678
PMBus COMMAND DETAILS
This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_1_PEAK The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_1 measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_READ_IIN_PEAK The MFR_READ_IIN_PEAK command reports the highest current, in Amperes, reported by the READ_IIN measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_READ_ICHIP The MFR_READ_ICHIP command returns the measured input current, in Amperes, used by the LTM4678. This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_2_PEAK The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_2 measurement. This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_ADC_CONTROL The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command runs the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of tCONVERT. The user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms. This command has a latency of up to 2 ADC conversions or approximately 16ms (external temperature conversions may have a latency of up to 3 ADC conversion or approximately 24ms). It is recommended the part remain in standard telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be commanded to monitor the desired parameter for a limited period of time (less then 1 second) then set the command back to standard round robin mode. If this command is set to any value except standard round robin telemetry (0) all warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled.

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LTM4678

PMBus COMMAND DETAILS

COMMANDED VALUE 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02
0x01 0x00

TELEMETRY COMMAND NAME
READ_TEMPERATURE_1
READ_IOUT READ_VOUT READ_TEMPERATURE_1
READ_IOUT READ_VOUT READ_TEMPERATURE_2
READ_IIN MFR_READ_ICHIP
READ_VIN

DESCRIPTION Reserved Reserved Reserved Channel 1 external temperature Reserved Channel 1 measured output current Channel 1 measured output voltage Channel 0 external temperature Reserved Channel 0 measured output current Channel 0 measured output voltage Internal junction temperature Measured input supply current Measured supply current of the LTM4678 Measured input supply voltage Standard ADC Round Robin Telemetry

If a reserved command value is entered, the telemetry will default to Internal IC Temperature and issue a CML fault. CML faults will continue to be issued by the LTM4678 until a valid command value is entered. The accuracy of the measured input supply voltage is only guaranteed if the MFR_ADC_CONTROL command is set to standard round robin telemetry.
This write-only command has 1 data byte and is formatted in register format.

NVM MEMORY COMMANDS

Store/Restore

COMMAND NAME STORE_USER_ALL
RESTORE_USER_ALL
MFR_COMPARE_USER_ALL

CMD CODE 0x15
0x16
0xF0

DESCRIPTION

TYPE

Store user operating memory to EEPROM.

Send Byte

Restore user operating memory from Send Byte EEPROM.

Compares current command contents Send Byte with NVM.

PAGED N
N
N

FORMAT

UNITS

DEFAULT NVM VALUE
NA
NA
NA

STORE_USER_ALL
The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating Memory to the matching locations in the non-volatile User NVM memory.
Executing this command if the die temperature exceeds 85°C or is below 0°C is not recommended and the data retention of 10 years cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is disabled. The command is re-enabled when the IC temperature drops below 125°C.
Communication with the LTM4678 and programming of the NVM can be initiated when EXTVCC or VDD33 is available and VIN is not applied. To enable the part in this state, using global address 0x5B write MFR_EE_UNLOCK to 0x2B followed by 0xC4. The LTM4678 will now communicate normally, and the project file can be updated. To write the

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115

LTM4678

PMBus COMMAND DETAILS
updated project file to the NVM issue a STORE_USER_ALL command. When VIN is applied, a MFR_RESET must be issued to allow the PWM to be enabled and valid ADCs to be read. This write-only command has no data bytes.

RESTORE_USER_ALL
The RESTORE_USER_ALL command instructs the LTM4678 to copy the contents of the non-volatile User memory to the matching locations in the Operating Memory. The values in the Operating Memory are overwritten by the value retrieved from the User commands. The LTM4678 ensures both channels are off, loads the operating memory from the internal EEPROM, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both PWM channels if applicable.
STORE_USER_ALL, MFR_COMPARE_USER_ALL and RESTORE_USER_ALL commands are disabled if the die exceeds 130°C and are not re-enabled until the die temperature drops below 125°C.
This write-only command has no data bytes.

MFR_COMPARE_USER_ALL
The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated.
This write-only command has no data bytes.

Fault Logging

COMMAND NAME MFR_FAULT_LOG MFR_FAULT_LOG_ STORE
MFR_FAULT_LOG_CLEAR

CMD CODE 0xEE 0xEA
0xEC

DESCRIPTION
Fault log data bytes.
Command a transfer of the fault log from RAM to EEPROM.
Initialize the EEPROM block reserved for fault logging.

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE

R Block N

Send Byte N

MFR_FAULT_LOG
The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occurrence since the last MFR_FAULT_LOG_CLEAR command was written. The contents of this command are stored in non-volatile memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this command are listed in Table 15. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the command will return a data length of 0. If a fault log is present, the MFR_FAULT_LOG will return a block of data 147 bytes long. If a fault occurs within the first second of applying power, some of the earlier pages in the fault log may not contain valid data.
NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock.
This read-only command is in block format.

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LTM4678

PMBus COMMAND DETAILS

MFR_FAULT_LOG_STORE

The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to NVM just as if a fault event occurred. This command will set bit 3 of the STATUS_MFR_SPECIFIC fault if bit 7 "Enable Fault Logging" is set in the MFR_CONFIG_ALL command.

If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature drops below 125°C.

This write-only command has no data bytes.

Table 20. Fault Logging This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.

Data Format Definitions
DATA Block Length HEADER INFORMATION Fault Log Preface
Fault Source MFR_REAL_TIME
MFR_VOUT_PEAK (PAGE 0) MFR_VOUT_PEAK (PAGE 1) MFR_IOUT_PEAK (PAGE 0) MFR_IOUT_PEAK (PAGE 1) MFR_VIN_PEAK READ_TEMPERATURE1 (PAGE 0) READ_TEMPERATURE1 (PAGE 1) READ_TEMPERATURE2

LIN 11 = PMBus = Rev 1.2, Part 2, section 7.1

LIN 16 = PMBus Rev 1.2, Part 2, section 8. Mantissa portion only

BYTE = 8 bits interpreted per definition of this command

DATA BITS FORMAT BYTE NUM BLOCK READ COMMAND

BYTE

147 The MFR_FAULT_LOG command is a fixed length of 147 bytes

The block length will be zero if a data log event has not been captured

[7:0] [7:0] [15:8] [7:0] [7:0] [7:0] [15:8] [23:16] [31:24] [39:32] [47:40] [15:8]
[7:0] [15:8]
[7:0] [15:8]
[7:0] [15:8]
[7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0]

ASC

Returns LTxx beginning at byte 0 if a partial or complete fault log exists.

Word xx is a factory identifier that may vary part to part.

Reg

Refer to Table 16.

Reg

48 bit share-clock counter value when fault occurred (200µs resolution).

L16

11 Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS

command.

L16

13 Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS

command.

L11

15 Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS

command.

L11

17 Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS

command.

L11

19 Peak READ_VIN since last power-on or CLEAR_PEAKS command.

L11

21 Power stage temperature sensor 0 during last event.

L11

23 Power stage temperature sensor 1 during last event.

L11

25 LTM4678 die temperature sensor during last event.

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LTM4678

PMBus COMMAND DETAILS
CYCLICAL DATA EVENT n (Data at Which Fault Occurred; Most Recent Data)

READ_VOUT (PAGE 0)

[15:8]

[7:0]

READ_VOUT (PAGE 1)

[15:8]

[7:0]

READ_IOUT (PAGE 0)

[15:8]

[7:0]

READ_IOUT (PAGE 1)

[15:8]

[7:0]

READ_VIN

[15:8]

[7:0]

READ_IIN

[15:8]

[7:0]

STATUS_VOUT (PAGE 0)

STATUS_VOUT (PAGE 1)

STATUS_WORD (PAGE 0)

[15:8]

[7:0]

STATUS_WORD (PAGE 1)

[15:8]

[7:0]

STATUS_MFR_SPECIFIC (PAGE 0)

STATUS_MFR_SPECIFIC (PAGE 1)

EVENT n-1 (data measured before fault was detected)

READ_VOUT (PAGE 0)

[15:8]

[7:0]

READ_VOUT (PAGE 1)

[15:8]

[7:0]

READ_IOUT (PAGE 0)

[15:8]

[7:0]

READ_IOUT (PAGE 1)

[15:8]

[7:0]

READ_VIN

[15:8]

[7:0]

READ_IIN

[15:8]

[7:0]

STATUS_VOUT (PAGE 0)

STATUS_VOUT (PAGE 1)

STATUS_WORD (PAGE 0)

[15:8]

[7:0]

STATUS_WORD (PAGE 1)

[15:8]

[7:0]

STATUS_MFR_SPECIFIC (PAGE 0)

STATUS_MFR_SPECIFIC (PAGE 1)

LIN 16 LIN 16 LIN 16 LIN 16 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 BYTE BYTE WORD WORD WORD WORD BYTE BYTE
LIN 16 LIN 16 LIN 16 LIN 16 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 LIN 11 BYTE BYTE WORD WORD WORD WORD BYTE BYTE

Event "n" represents one complete cycle of ADC reads through the MUX at time of fault. Example: If the fault occurs when the ADC is processing step 15, it will continue to take readings through step 25 and then store the header and all 6 event pages to EEPROM 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Rev. A

118

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PMBus COMMAND DETAILS

EVENT n-5 (Oldest Recorded Data) READ_VOUT (PAGE 0)
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
READ_IIN
STATUS_VOUT (PAGE 0) STATUS_VOUT (PAGE 1) STATUS_WORD (PAGE 0)
STATUS_WORD (PAGE 1)
STATUS_MFR_SPECIFIC (PAGE 0) STATUS_MFR_SPECIFIC (PAGE 1)

[15:8] LIN 16

127

[7:0]

LIN 16

128

[15:8] LIN 16

129

[7:0]

LIN 16

130

[15:8] LIN 11

131

[7:0]

LIN 11

132

[15:8] LIN 11

133

[7:0]

LIN 11

134

[15:8] LIN 11

135

[7:0]

LIN 11

136

[15:8] LIN 11

137

[7:0]

LIN 11

138

BYTE

139

BYTE

140

[15:8] WORD

141

[7:0]

WORD

142

[15:8] WORD

143

[7:0]

WORD

144

BYTE

145

BYTE

146

Table 21. Explanation of Position_Fault Values

POSITION_FAULT VALUE

SOURCE OF FAULT LOG

0xFF

MFR_FAULT_LOG_STORE

0x00

TON_MAX_FAULT

0x01

VOUT_OV_FAULT

0x02

VOUT_UV_FAULT

0x03

IOUT_OC_FAULT

0x05

TEMP_OT_FAULT

0x06

TEMP_UT_FAULT

0x07

VIN_OV_FAULT

0x0A

MFR_TEMP_2_OT_FAULT

MFR_INFO Contact the factory for details.

MFR_IOUT_CAL_GAIN Contact the factory for details.

For more information www.analog.com

LTM4678
Rev. A
119

LTM4678

PMBus COMMAND DETAILS
MFR_FAULT_LOG_CLEAR The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear. This write-only command is send bytes.

Block Memory Write/Read

COMMAND NAME CMD CODE DESCRIPTION

DATA

DEFAULT

TYPE PAGED FORMAT UNITS NVM VALUE

MFR_EE_UNLOCK

0xBD Unlock user EEPROM for access by MFR_EE_ERASE R/W Byte N

Reg

and MFR_EE_DATA commands.

MFR_EE_ERASE

0xBE Initialize user EEPROM for bulk programming by

R/W Byte N

Reg

MFR_EE_DATA.

MFR_EE_DATA

0xBF Data transferred to and from EEPROM using

R/W

Reg

sequential PMBus word reads or writes. Supports bulk Word

programming.

All the NVM commands are disabled if the die temperature exceeds 130°C. NVM commands are re-enabled when the die temperature drops below 125°C.

MFR_EE_xxxx
The MFR_EE_xxxx commands facilitate bulk programming of the LTM4678 internal EEPROM. Contact the factory for details.

Rev. A

120

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LTM4678

PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.

Table 22. LTM4678 BGA Pinout

PIN ID FUNCTION PIN ID FUNCTION

SW1

GND

SW1

GND

VOUT1

A10

VOUT1

B10

A11

VOSNS1+

B11

A12

VOSNS1

B12

VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1

PIN ID C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12

FUNCTION GND GND GND GND GND GND VOUT1 VOUT1 VOUT1
COMP1b WP
VTRIM0_CFG

PIN ID D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12

FUNCTION SVIN GND GND GND GND GND VOUT1
TSNS1b PGOOD1 COMP1a SHARE_CLK
VDD25

PIN ID E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12

FUNCTION VIN1 VIN1 VIN1 VIN1 GND GND
INTVCC VDD33 FSWPH_CFG VTRIM1_CFG VOUT0_CFG VOUT1_CFG

PIN ID F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12

FUNCTION VIN1 VIN1 VIN1 VIN1 GND GND GND
EXTVCC SGND SGND RUN1 ASEL

PIN ID G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12

FUNCTION VIN0 VIN0 VIN0 VIN0 GND GND GND GND SGND SGND
FAULT1 RUN0

PIN ID H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12

FUNCTION VIN0 VIN0 VIN0 VIN0 GND GND GND GND
COMP0b SDA ALERT
FAULT0

PIN ID J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12

FUNCTION IIN+ GND GND GND GND GND
PGOOD0 TSNS0b COMP0a TSNS1a TSNS0a
SCL

PIN ID K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12

FUNCTION IIN GND GND GND GND GND VOUT0 VOUT0 VOUT0 VOUT0 VOUT0 SYNC

PIN ID L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12

FUNCTION GND SW0 GND GND GND GND VOUT0 VOUT0 VOUT0 VOUT0 VOUT0 VOUT0

PIN ID M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12

FUNCTION SW0 SW0 GND GND GND GND VOUT0 VOUT0 VOUT0 VOUT0
VOSNS0+ VOSNS0

For more information www.analog.com

Rev. A
121

For more information www.analog.com

122

Rev. A

PIN "A1" CORNER 4
(7.3) aaa Z
(1.0)

(6.6)
E (4.35)
(6.6)

(4.35)

(1.0) Y
X

D
PACKAGE TOP VIEW

BGA Package 144-Lead (16mm × 16mm × 5.86mm) (Reference LTC DWG # 05-08-1540 Rev C)
A A2
A1 ccc Z

b1 MOLD CAP
SUBSTRATE H3
H1 H2
DETAIL B

// bbb Z Z

Øb (144 PLACES)

ddd M Z X Y eee M Z

DETAIL B
EPOXY/SOLDER
PACKAGE SIDE VIEW

aaa Z

6.9850 5.7150 4.4450 3.1750 1.9050 0.6350
0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850

0.630 ±0.025 Ø 144x
SUGGESTED PCB LAYOUT TOP VIEW

6.9850 5.7150 4.4450 3.1750 1.9050 0.6350
0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850

DETAIL A

SYMBOL A A1 A2 b b1 D E e F G H1 H2 H3 aaa bbb ccc ddd eee

DIMENSIONS

MIN

NOM

MAX NOTES

5.46

5.86

6.26

0.50

0.60

0.70 BALL HT

2.23

2.32

2.41

0.60

0.75

0.90 BALL DIMENSION

0.60

0.63

0.66 PAD DIMENSION

16.00

1.27

13.97

0.28

0.32

0.36 SUBSTRATE THK

1.95

2.00

2.05 MOLD CAP HT

2.73

2.94

3.15 INDUCTOR HT

0.15

0.10

0.20

0.30

0.15

TOTAL NUMBER OF BALLS: 144

Z Z

b F
e

12 11 10 9 8 7 6 5 4

PACKAGE BOTTOM VIEW

DETAIL A
321

SEE NOTES 7

A B PIN 1

SEE NOTES 3

NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994

2. ALL DIMENSIONS ARE IN MILLIMETERS

3 BALL DESIGNATION PER JESD MS-028 AND JEP95

4 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE

5. PRIMARY DATUM -Z- IS SEATING PLANE

PACKAGE ROW AND COLUMN LABELING MAY VARY

! AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY

COMPONENT PIN "A1"
TRAY PIN 1 BEVEL

LTMXXXXXX µModule
PACKAGE IN TRAY LOADING ORIENTATION BGA 144 0118 REV C

LTM4678 PACKAGE DESCRIPTION

REVISION HISTORY
REV DATE DESCRIPTION
A 03/19 Changed Current Readback Accuracy from ±5% to ±3.5% and added temperature condition Changed IOUT condition on IOUTn and IOUTn(OCL_AVG) from 34A to 36A Changed IOUTn(OCL_AVG) from 35A to 30A, deleted IOUTn(OCL_PK) Changed default value of MFR_IOUT_CAL_GAIN_TC to 3800 0x0ED8 Changed default value of MFR_IOUT_CAL_GAIN to 0.68 typical 0xD02C Updated IOUT_OC_FAULT_LIMIT table Updated READ_IOUT graphs Changed EA_GM to 3.69ms from 1ms on Load Transient Response for 0.9VOUT Changed maximum VOUT voltage from 3.3V to 3.4V Changed default value of MFR_VOUT_MAX to 0x399A Changed minimum VOUT from 0.6V to 0.5V on VOUT-RNGL, VOUT-RNGH, VO-RB-ACC Added description Not Recommended for Upside Down Reflow, updated Pin Configuration information Changed minimum VIN conditions from 5.0V to 5.75V for Line Regulation Changed SVIN-OU-ACC to 350mV, changed maximum value of VIN_THR to 7.5V Changed maximum frequency range to 1000kHz, changed default Switching Frequency to 350 in Table 3 Changed tON(MIN) from 50ns to 60ns Added Note 15 to VOUT-RNGH, RCOMP0,1, gm0,1, VINSTP, VICHIPSTP, VVDD33_OV, VDD33_UV, VTH(SYNC) Corrected typo on VOV-ACC-0,1 and VUV-ACC Corrected typo on Note 14 and Note 16, added Note 19 Tied SVIN to VIN directly on Test Circuit 1 and Test Circuit 2 Update Figure 29, Figure 45 thru Figure 49

LTM4678
PAGE NUMBER
1, 8 5, 6 6 48, 88 88 89 14 13 1,5,1921,27,86 47 6, 7 4 5 7, 8 9, 31 6 6, 7, 8, 9 6, 7 11 21 58, 7175

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license Fisogrrmanoterdebiny fiomrpmlicaattiion owrwotwhe.arwniasleougn.cdeormany patent or patent rights of Analog Devices.

Rev. A
123

LTM4678 PACKAGE PHOTOGRAPH

DESIGN RESOURCES

SUBJECT µModule Design and Manufacturing Resources
µModule Regulator Products Search

DESCRIPTION

Design: · Selector Guides · Demo Boards and Gerber Files · Free Simulation Tools

Manufacturing: · Quick Start Guide · PCB Design, Assembly and Manufacturing Guidelines · Package and Board Level Reliability

1. Sort table of products by parameters and download the result as a spread sheet.

2. Search using the Quick Power Search parametric table.

Digital Power System Management

Analog Devices' family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging.

RELATED PARTS

PART NUMBER LTM4676A LTM4630
LTM4620/LTM4620A
LTM4633 LTM4634 LTM4675 LTM4650/LTM4650-1 LTM4677

DESCRIPTION
Lower Power Than the LTM4677, Pin Compatible
Same Power as the LTM4677 but without Digital Power System Management
Lower Power Than the LTM4677 but without Digital Power System Management
Triple Output 16VIN, 5.5VOUT Triple Output 28VIN, 12VOUT Lower Power Than the LTM4677, Smaller Package
More Current Up to 50A µModule Regulator
Dual 18A or Single 36A with PSM

COMMENTS Dual 13A or Single 26A Dual 18A or Single 36A
Dual 13A or Single 26A, Pin Compatible with the LTM4630
10A, 10A, 10A 5A, 5A, 4A Dual 9A or Single 18A, 11.9mm × 16mm × 3.5mm Dual 25A or Single 50A 4.5V VIN 16V, 0.5V VOUT 1.8V

124

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