Scanned
1987 Digital Semiconductor Databook Vol 1 1987
Semiconductor
Databook
Volume 1
U.SA I SRA EL SCOTLAND
Confidential and Proprietary
·Foreword
We at Semiconductor Operations (SCO) are committed to provide excellence in integrated circuit technologies, products, and services to support our customers, the Digital Systems Groups.
Our primary objective is to optimize Digital's competitive market position by developing leadership system performance at the lowest possible cost and within the appropriate time constraints.
The execution of programs designed to achieve this <?hiective has resulted in the technologies
and products described in the 1987 Semiconductor Databook Volumes 1and2. While the basic
sea charter of
is to provide strategic and tactical management of all integrated circuit
requirements, the VLSI design and manufacturing function of SCO has become the focal point
for unique and complex circuits that have contributed significantly to the success of many new
Digital products. A strategic investment has been made in CMOS technology and in the design
tools necessary to take advantage of this technology. Increased circuit densities and perform-
ance have resulted, and capabilities have been extended from full-custom design for maximum
performance to semi-custom design for fast time-to-market application. CAD tools are
continually being developed to further enhance design and design methodology.
sea is continually expanding its facilities to provide you with better service. While Hudson
and Andover, Massachusetts are the nucleus of the engineering and manufacturing operations,
supplemental design facilities are available in Israel and Japan and additional manufacturing
capacity is being planned in Scotland. In addition, a new 6-inch wafer pilot fabrication Iine has
been approved for construction in Hudson to aid in the state-of-the-art development of the
advanced CMOS devices.
During the past year, many new integrated circuits have been developed and released. Although some are application-specific, the circuits that are suitable for general use are described in Volumes 1 and 2 of this databook. Volume 1 is a revision to the 1986 Databook and includes the latest revisions and changes. Volume 2 contains information related to the new CMOS products that have been recently developed for general use. We encourage you to become familiar with these products and to use them in the design of Digital's systems products when possible. We are ready to assist you in your design process and in support of your production needs.
Our ultimate goal is to ensure that Digital's systems continue to maintain significant competitive advantage through the use of SCO services and products.
Confidential and Proprietary
iii
· Functional Product Oassification
Name
Number
Microprocessors
78032 78132 78532 78516 78584 ADVICE
21-20887-01 21-22797-01 21-24 329-01 . 21-24330-01
21-23864-01
Description
MicroVAX 32-bit CPU MicroVAX Floating-point Unit · MicroVAX Ditei=tMemory Access MicroVAX:Vectoredlnterrupt Controller MicroVAX DynamkRAM Controller MicroVAX Indrcuit Emulation Unit
DC327 DC328 DC329 DC330
DCJll FPJll
DCTll
21-20852-AA 21-20851-AA 21-20850-AA 21-20849-AA
21-21858-00 21-17311-01
V-11 ROM/RAM
.V-11 Insttyction/Executio~ Logic
'V~ll
V-h
MFleomatolrnyg-Mpo~in~tknt~etratloor~cL.ogic
DCJll 16-bit Microprocessor
PPJli0Flt1ating.;poiet Aclt<!ierater
OCTU 16.bit Microptpcessor
Video Controllers
78610
21-24941-01
78680
21-25011-01
78690
21-21553-01
Programma~le SpdteCtirsor Video Processor (VIPER) Vkitt0 Control (ADDER)
Communications
78808 DC319
21-23458-01 21-17312-00
Octal ART ni.p.i;rr
Bus Support
78701 78702 78732 78733 78743 DC003 DC004 DC005 DC006 DCOlO DC013 DC021
19-22110-01 19-22111-01 21-21689-00 21-23839-01 21-23838-01 19-12730-00 19-12729-00 19-13040-00 19-14035-00 19-14038·00 19-14438-00 19-19015-00
General Purpose
DC022 DC102 DC301
19-17871-00 19-13888-00 21-12623-00
Mass Storage Support
DC018 DC024 DC309
19-19015-00 19-20116-01 21-15102-00
. ,VAXBI Clock Driver
VAXBI Gloek Receiver
VAXBlBIIC VA:x:BIBCl)
VAXBI~CAI
'Dual~~pt Circuit , Register Selector (Protbcol Chip) · .4-Bit Ttansceiver Word Count/BusAddress Logic Direct Memory Acces!'·Lbgic . UNIBUS'Request Logic Octal Bns Transceiver
16-word by 4-bit Register File Equals Checker Dual Baud Rate Geornitor
Serializer/Deserializer Logic Encoder/Decoder Logic Reed Solomon Generator
·Confidential and Proprietary
v
· Part Identification Codes
The following identification codes are used with the devices in this databo.ok.
780 Series
78xyz - xx
l _0 = Processors
1 = Coprocessor .
2 =Memories
3 = 1/0 devices.. 4 =Reserved
5 = Controllers 6 = Graphic devices
7 = Bus interfaces 8 = Communications devices
9 =Reserved
- xx
GA = Gullwing
FA= Straight
PA = Pin grid array
DC Series
DCxyz
.
t 0 = Custom bipolar devices
--1 = Custom bipolar devices
3 = MOS devices
.5 = MOS devices
· Cross-referencing of Semiconductor Products
Part
Name
DC003 DC004 DC005 DC006 DCOlO DC013 DC018 DC021 DC022 DC024 DC028
DC029 DC102 DC301 DC309 DC310 DC319 DC321 DC502 DC323
DC324 DC327 DC328 DC329 DC330 DC333 DC335 DC337 DC343
Part
Purchase
Number Number
Description
DC003 DC004 DC005 DC006 DC010 DC013
DC021
78701
19-12730-00 .Dual-interrupt Circuit 19-12729-00 Register Selector (Protocol) Logic
19-13040-00 4-bit Transceiver
19-14035-00 Word Count/Bus Address Logic 19-14038-00 Direct Memory Access 19-14438-00 UNIBUS Request Logic 19-17043-00/1 Serializer/Deserializer 19-19015-00 Octal Bus Transceiver 19-17871-00 16·Word by 4-bit Register File 19-20116-01 Eneoder/Decoder Logic 19-22110-01 VAXBI Clock Driver
78702
DCTll DC319 FPJU 78680-GA 78690-GA
19-22111-01 19-13888-00 21-12623-00 21-15102-00 21-17311-01 21-17312-00 21-21858-00 21-25011-01 21-21553-01
VAXBI Clock Receiver Equals Checker DualBimd Rate Generator Reed Solomon Generator DCTll 16-bit Microprocessor DLART FPJll Floating-point Accelerator Video Processor (VIPER) Video Control (ADDER)
78732-PA
78032-GA DCJll 78132-GA 78743-PA
21-21689-00 21-20852-AA
21-20851~AA
21-20850-AA 21-20849-AA 21-20887-01 2U7679-00 21-22797-01 21-23838-01
VAXBIBIIC V-11 ROM/RAM
V-11 Inst~u.;:tion/Execution L9gic V-11 Memory Management Logic V-11 Floating-point Accelerator Logic
MicroVAX 32-bit CPU
DCJll 16-bit Microprocessor MicroVAX Floating-point Unit
VAXBIBCAI
vi
Confidential and Proprietary
Part Name
DC344 DC349 DC357 DC358 DC503 DC506 ADVICE
Part
Purchase
Number Number
78733-PA 21-23839-01 78808-GA 21-23458-01 78584-GA 21-23864-01 78532-GA 21-24329-01 78610-GA 21-24941-01 78516-GA 21-24330-01 ADVICE
Description
VAXBIBCI3 Octal ART Dynamic RAM Controller (DYRC) MicroVAX Direct Memory Access (DMA) Programmable Sprite Cursor MicroVAX Vectored Interrupt Controller (VIC) MicroVAX Incircuit Evaluation/Emulation Unit
Confidential and Proprietary
vii
Contents
MicrcNAX 78032 32-bit C~ntral Processing Unit . . . . . . . . . . ... r ............... .
MictovAX 78132 Floating-point Unit .......................................... ,. ; :+· . 1-59
MicnNAX 78516 Vectored Interrupt Controller ..................... ; ......... '.. · 1-79
MicrcNAX 785J2 Direct Memory Access ... : ............................ : . ; . ,,.1-109
MicrcNAX 78584 l)ynamicRAMController ....... , ......... ,,, ..........., ...... :'l"J.75
MicrcNAX Incircuit EniulatorUnit . ·.;. ··... .,.:.; .y. ,, , .·.·1·., ,,; ·. p·;:. 1 ··.·· ,. , ····.· , · , .Jcl5>9
I:ntroductiQn to the V-11 Chipset . ; ·.'· ... , ·... 4 ·· ·· ··· , ..... , · ·:; ·. ''·· ···· , · ···· ,. ··· , · 1-207
DC327 V-11 Processor ROM/RAM Logic ................ 9;.;., ...... , ,, ..., .....,l-209
OC.328 V-11 l?tocessor Instruction/Executi®-4->gic ....·. , . . . -.r, ·' ... ,.·. , ......· t: , 1"217
DC329 V-11 l?tocessor Memory Management Logic ...... 1..""'
, ······· ; .· , ''·'. 1-227
DC330 V-11 Processor Floating-point Accelerator Logic ........................... 1-241
DCJll 16-bit Microprocessor ............................................... 1-249
FPJU Floating-point Accelerator ............................................ 1-323
DCTll 16-bit Microprocessor .............................................. 1-349
Section 2 · Vadeo Processors and Controllers
78680 Video Processor (VIPER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 78690 Video Control (ADDER) ............................................. 2-31 DC503 Progranunable Sprite Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75
Section 3 · Communications Devices
78808 Eight-channel Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 DC319 DLll Compatible Asynchronous Receiverflhnsmitter . . . . . . . . . . . . . . . . . . . . . . 3-27
Section 4 · Bus Support Devices
VAXBI 78732 General Purpose Bus Interconnect Interface . . . . . . . . . . . . . . . . . . . . . . . . 4-1
VAXBI 78743 BCI Adapter Interface ..........·.............................. 4-135 VAXBI 78733 BCI Bus to MicroVAX II Bus Interface ............................. 4-159 VAXBI 78701 Clock Driver ................................................. 4-191 VAXBI 78072 Clock Receiver ............................................... 4-203 DC003 Dual-interrupt Logic ............................................... 4-213 DC004 Register Select (Protocol) Logic ....................................... 4-223 DC005 4-Bit Transceiver .................................................. 4-233 DC006 Word Count/Bus Address Logic ....................................... 4-243 DCOlO Direct Memory Access Logic ......................................... 4-255 DC013 UNIBUS Request and Control Logic .................................... 4-269 DC021 Octal Bus Transceiver .............................................. 4-283
Section 5 · Mass-storage Devices
DC018 Serializer/Deserializer Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 DC024 Encoder/Decoder Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 DC309 Reed Solomon Generator for ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49
SeCtion 6 · General Purpose Devices
DC022 16-Word by 4-bit Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . .· . . . . . . . . . . . 6-1
DC102 Eight-channel Equals Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . · . . . . . . . . 6-23 DC301 Dual Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
Appendixes
Appendix A· MicroVAX 78032 CPU and MicroVAX 78132 FPU Instruction Set .......... A·l Appendix B · DCTll and DCJll Microprocessors Instruction Set ...................... B-1 Appendix C · de Specification Test Circuits . . . . . . . . . . . · . . . . . . . . . . . . . . . . . . . . . .... C-1 Appendix D · Input/Output Voltage Waveform Parameters ....·. , ...... , ............ D-1 Appendix E · Mechanical Specifications . . . . . . . . . . . . . ... : , , . . . . . . . . . . . . . . . . . . . . . E-1
x
Confidential and Proprietary
·Section 1-Microprocessor and Support Devices
The microprqcessors ~d support devices provide a low-cost ~s to implement the power and
versatility of the PDP"ll and VAX. comp~ters into system designs.
MicroVAX 32-bit Mic:roproeeSSol' ·.
.·'
.·. . ...· . .. .. . .. . . .
.
MicroVAX 78032 Central Processing Unit-The MicroVAX. CPD is a )~-bit ltjgh-perfo~pce
microprocessor that .contains the architecture. and functions of .a . VAX minkomp1.1ter. The
MicroVAX.·78032 implements a subset of the VKX insttuctlon set· and full VAX.,lf memory
management. It is fabricated in ZMOS (double-metal NMOS)and hi c~htafued iri £single 68-piii
package.
MicroVAX 78132 Floating-point Unit-The MicroVAX FPU is a high-performance cooperative processor used to accelerate the floating-point instructions of the MicroVAX. 78032 CPU. It supports floating-point add, subtract, multiply, divide, and convert and other VAX.-11 floatingpoint operations. The FPU is fabricated in ZMOS and is contained in a 68-pin package.
MicroVAX 78516 Vectored Interrupt Controller-The VIC is a programmable interrupt controller that is fully compatible with the MicroVAX 78032 CPU. The 78516 VIC services up to 16 interrupt sources, resolves interrupt priorities, drives the IRQ line!> of the CPU, and provides a programmable 16-bit interrupt to the CPU. It is fabricated in high-speed CMOS and is contained in a 68-pin package.
MicroVAX 78532 Direct Memory Access Controller-The 78532 DMA is a high-performance dualported four channel virtual memory DMA controller that enables high-speed data transfers between I/O subsytems and peripheral devices and the MicroVAX 78032 CPU bus. It contains dual ports and four channels that are independently programmable. The 132-pin device is fabricated in CMOS.
MicroVAX 78584 Dynamic RAM Controller-The MicroVAX. DYRC provides an interface between the MicroVAX CPU and up to 4 Mbytes of dynamic random access memory (DRAM). The 78584 DYRC operates at two speeds to support 256K by 1-bit DRAMs that operate at different speeds. It is contained in an 84-pin package and is fabricated in CMOS.
Advanced Development VAX Incircuit Emulator-The ADVICE is contained on a single module and provides a full-speed incircuit emulator of the MicroVAX 78032 CPU and MicroVAX 78132 FPU. It is used for the development of hardware and software products using the MicroVAX CPU and FPU.
V-1132-bit VAX Processor The V-11 processor chip set consists of four custom VLSI chips that were developed for use with the
Scorpio CPU module which is a single module VAX system.
DC327 ROM/RAM Logic-The ROM/RAM chip is a 44-pin cerquad device that provides the microcode control store function for the V-11 processor.
DC328 Instruction/Execution Logic-The I/E chip is a 132-pin PGA device that functions as the main data path and contains the microsequencer, minitranslation buffer, and instruction buffer.
DC329 Memory Management Logic-The M chip is a 132-pin PGA device that provides most of the memory management logic and includes a tag store for cache memory, four UARTS, and a 512-entry backup translation buffer.
DC330 Floating-point Accelerator Logic-The F chip is a 132-pin PGA device used to decrease the execution time of F, D, and G floating-point instructions and some integer multiply and divide instructions.
Cottfidenfulland Proprietary
PDP-11 16-bit Processors DC]ll Microprocessor....:.:.The DCJll microprocessor is a 60-pin CMOS DIP de\"ice that implements the full PDP-11 instruction set and has Ei pe:tformance comparable to the PDP111/44 mihiprocessof.
# FPJ11 Floating-point Accelerator-The FPJll FPA is a 40-pin DIP thatimplc;:ments in llatdware
the floating-point instructions of the DCJll thereby significantly improving the performance of
fl6!iting-point instructions.
·
Dern Microprocessor-The DCTll microprocessor is a 40-pin DIP device that contains the
essential el(!:ments of the PDP-11 architecture.
xii
Confidential and Proprietary
· High performance - 32-bit internal and external data path - Pipelined ru:cltltecture
- Insirtictidn prefetch
· 4 gigabyte virtual address space
· 1 gigabyte physical address space - 512 Mbyte physical memory space - 512 Mbyte 1/0 space
· VAX memory management - Ful'.l memory protection
- Four privilege modes - Process and system space mapped
· Subset of the VAX instruction set
--22145adindsrtens:stc~t~ioondes~ ~ 9 datibtypes · ·.
: Siite~ 3~·klf$~tiCral Putp()s~ registers
· 22 interrupt levels - 15 software - 7 hardware
·. Veetored spftware and hardware interrupts
~ Industr,y i;:ompatible external interface
· Single 5 V~·.~er.supply
· Description
The MicroVAX 73082 is a high-performal}ce single-chip mic;ropt9F~sor that provides the architecture and functions of:i;he VAX minicomput.er in a single·68-p.~ package. Fabricated in
ZMOS (double-metal MOS),· the MicroVAX 780:32 implements a ·£Ull· 32"bit architecture that can
directly access 4 Gbytes ?f vif1;Ual m~mory and 1 Gbyte of physic# mepiory. Figure 1 is a block
diagram of the MicroVAX 78o'32 microprocessor,
GENERAL REGISTERS ANO INTERNIAL REGl$T£~&
HID
PWm iN'mM
~
MICAOSEOUENCtR ANO CONTROL Si'OAe
DAL JNTEAFACE
MEMORY MANAGEMENT UNiT
CLKO ~
CLKI
CLOCl<S
RESET .__ _ ____.
Figure 1 · MicroVAX 78032 Microprocessor Block Diagram
Confidel)tial ~ Pipprietary
1-1
.''
'
'
'
,
·.·~y:/il:
TheMi#r~7afH.4tuses $single $Vdc··~·~ s~ppl~~;~~uires'no ~pec~suppottloiiic, . and is
easily interfaced with industry standard peripheral chlps. It is ideal for use as a single-board
computer, personal computer and workstation, and as a low-end system.
· Pin and Signal Descriptions
.\
This section provides a brief description of the input and output signals and po,,ver and gi:oµnd connections of the MicroVAX 78032 68-pin package. The pin assignments are id~ntified in Figure
2 iind the signals are summarized iri Table 1.
Voo
DAL06
DAL05
DAL04 DAL03
DAL02
DAL01 DA LOO
Vss Vbb iRi'.:i3
illQ2
TEST
im:ff
ifl()5
PWRIT Vas
r---------1
I
I
I
I
I
I
1
MieroVAX 78032
1
I 1
PROCESSOR CHIP
I 1
I
TOP VIEW
I
I
I
IL _ _ _ _ _ _ _ _ _ _;I
Vss
DAL22 .
DAL23
DAL24
DAL25 DAL26 DAL27 DAL28
DAL29
DAL30
DAL31
Voo
Vss ~
00 i5Bt
CLKO
Figure 2 ·MicroVAX 78032 Pin Assignments
1-2
Confidential and Proprietary
Preliminary
MicroVAX 18032
Table l · MicroVAX 78032 Pin and Signal Summary
~t/Outpu,t* Definition/Funetion
33-42 DAL<:31:00:>>·.·. input/output 45-59 62-68
Data/Address lines-Time multiplexed, ·. bidi:reetional data and address bus.
30 AS
29 OS· 12-15 BM<3:0>
output output input/output
Address
"
'
. ..
s
t
r
o
be-
'·
··-
S
··
y
-
$·..,t,.e.
m
"
address
'
"
'
"·'
st"r' obe,
·,_,,
. :(:la,tjl.st~~-Sys~~ ~o~m\,~..,
. Byte ifut~kfi;.....]dentifi~ t:he bytes of the DAL bus that
containfvatid data. · · · · · ·
21 WR 28 DBE
19 ID5Y
20 ERR
16 RESET
11 mtT
24-26 CS<2:0>
output output input input
transceivers.
Ready-J?rovidc;s.s~~ ~f~ ~~ ~rduring ~
memory or interrupt bus cycle. · · · · ·
input/output
Halt:~Halts .·the uebitiort of··· tnacroinstructions tnonmaskabl~ ll\l.rer,~). ··
": . -- -·> - ' - - ~ ',
... Control sta.tus-'fudtc~tes the type of bus cycle.
3,4, IRQ<J:O> input/output 6,7
Interrupt request-Interrupt lines for device interrupts.
8
input
10
input
Interval timer-Indicate~~ ;xter~afinte~ timer
condition.
18
input
DMA request-~~sts the bus for DMA transfetS.
22
output
DMA grant-Grants bus fot·DMA transfers.
23
output
External processor strobe..:.....Coordinates exrehmt
processor transactions.
2,32, VDD
44,61
input
Supply voltage-5 Vdcsupply.
1,31, Vss 43,60
input
Ground-Ground refe.rence.
17 CLKI
input
Clock in-Clock input for chip timing.
27 CLI<O
9 v ··
input output
Clock out-Clock output at half the frequency of CKLI.
Back-bias-For manufacturing use.
5
TEST
input
Test-For manufacturing use.
*All signals are TTL levels except for ~in 23(;EPS) \\'Wchis CMOS.
Confidential and Proprietary
1-3
Dataancl.A.ddressBus <.
·..,
, . . . ...t.'c.'c·.·, '· .· ·k''''·
.Data and address bus (DAL< 31:00>)-:-~heda~a a9dad<lress ~us is atime"multiplexed bidirec-
tional bus that transfors. address, dat~, and'dth~r irlforml!tioif'a{lrtrighuscycles. Fdf':a'detaife~
desc-tiption ofOAL <.31:00 :> bus, refer to dwMicraVAX 7803232~BitGentral~ctssing)JnitJJser'$
Guide. (Document No. EK-78032-UG}
Bus Control .· , , ...· ..
. .....
. .
Address· strobe· (i\S)-This signal indicates that valid address information is available on the
DAL<29:02> busand'validstatus informationis on the BM<3:0>, GS<2:0>, and WR lines.
~ le~dipg edi?;e of tJ;is si~nal c~n be used to latc:.h the address.
External processor strobe (EPS)-This signal\sused by the CPU to coordinate external processor transactions,.It is usedwith thefollowing transactio11s:
·.Transaction.between an extefP.al processor fontrolled by the CPU, such as· the MicroVAX 78132
Floating~Foint Unit.
·
.. ,
· ·
· Transactk:ms betweenlogic that implements a register or registers that are defined as apart ofthe
Mi'cr0VAX irlterl'ial pr&:essot 'register set.
· ·
·
· ·
Data strobe (QS)--:This signal indicates that the DAI,, bus is free to re.ceive data.during a CPU read
cycle or that valid data is.on the DAL bus during a CPU write cycle... · .
Byte maskS (BM <3:0> )-..These signals ate used to indicate which. bytes of the DAibus contain
valid data as lis:te<.l in Table 2. F9r a read cycle, they indicate which by~es. pf the DAL bus must have
data driven onto them. For a wri~ cycle, tl1ey i9dicate which bytes of the DAL bus contain valid data; Bhs BM< 3:() > aJ:t< valid when the AS ~ignal is asserted.
~ble 2 · MicroVAX 78~32 ~yte Mask Data Selection
Byte Mask . Valid Data Byte
BID'
DAL<31:24>
BM2.
D.AL<23:16>
BMl
,.QAL<15:08>
·.m;ro. ·PAL<07:00>
1-4
Confidential and Proprief~
Preliminary
Write tfi~..-'Fhis signal specifies the directionof datatransfor on the DA.11. bus fo:f,thecurrent bus cycle;:,When a~ted,:the CPU is performing a write operatl.on. When·noideassertkcl, the tPtJ
is performing a read operation. The WR signal is valid when the AS or EPS signal is asserte<:b
Data buffer enable (DBE)-This signal is used with the WR signal to the control transceivers that
may be between the GPU and the J)AL. bus.
bus . Ready (RDY)-This sigiiil'ishssdte&by'extemar:l(lgk to ·in.di~ the edm.pletion of the cu.rrent cycle. When not· asserted, it extends the current bus cyde i~~ ~ s19wer ,m~mo1¥0:r·peripbe@l
device. The RDY or ERR signal must be asserted to end the current bus cycle. ·:
Error {ERR)-This signal is asilerted by external logic to indicate t~t ~ri.~rror; assocfat~ ;With t~e current bus cycle, has occurred (e.g.' bus timeout or parity error} andto end the bus.cycle. Them
or RDY signal must be asserted to end the bus cycle.
. ··
System Control
Re~t (RESE!)-This input signal_is used to irutiaJW: tlie G!>'ti~.~fkdowt1 state,
Control status (CS < 2:0 > )-These lines areused with ~ithertlie'AS of the EPS and WRsignals to
the define the type of operation in progress for current btis cyc~]J.ije~,.µnes CS< 2:0 > ?re vali9
when the AS or the BPS signalis asserted.
.
During a read,.write, orinterrupt-acknowledge cycl~ (AS asserted},. it~ Wiland CS<l:O> lines
select the bus cycles indicated in Table 3.
·
Write Control Status Bas: Cycle
WR CS<2:0>
H LLL
reserved
·,;fescrved
·l:eiJei'ved'···
H LHH
interrupt acknowledge
H HLL
read (instruction)
H
HLH
H
HHL
H HHH
read (data, no modify intent)
L
LLL
reserved
L
LLH
L
LI{L
L ... LIDI
reserved reserved reserved
L HLL
reserved
L HLH
write unlock
L
HHL
reserved
L HHH
write (data)
Cobfidential and Proprietary
At the beginning of an:,external processor .read; Write:,:. or respo~ eycle. (m as~ted), the
CS2 sigllal is .high,. and the \\7R and C:S< l:():> signals select the bll5 cycles inclifated in
Table4.
~ble 4 · l\.iicroVAX 78032 Extemal Rtgista lJus Cycle
Write; Contl'OJ Status Bull Cycle
WR CS<l:O>
a LL
rest!rved
H LH
read data
H HL
reserved
H HH
response enaple
L
LL
write cqmniand (FPU)
L LH
write data
L HL
. write command (non-fPU)
L HH
reserved
During a response enable Cycle the ts <2 > signal maybe pulled lo\V bythe external logic. Refer to
the External Processor Cycle section for a description of a response enable cycle..
Interrupt Contl'Ol Interrupt request (..,,IR"'"Q...-<...,.3"""':0,....>-)'-These lines are used by the external logic to generate interrupt requests to the CPU. The lines are sampled by the CPU every microcy:cle. Table 5 lists the ip.terrupt level assignments.
Table 5 · MicroVAX 78032 Interrupt Request Assignments
IRQ Line . Interrupt Level IRQ 3 IPL 17
IPL 16 IPL 15 IPL 14
1-6
Ccmfidential and Proprietary
Preliminary. ··
MicroVAX 71l92
Powerfail (PWRFL)-This line allows the external logic to notify the CPU of a powerfail
condition. It i.s sampled by the CPU every microcycle. The PWRFL signal generates aninterrupt at
IPL 1E (hl!)Qld~imal}. This interrupt is internally acknowledged by the CPU and does qoi use an
interrupt ac,kn9wle~g~ bus cycle.
.
·
Interval timer (INt'fI&f)-Thisline provides systeintiming in£,<:rt".J,Uation of th~ interva,ltimel" and is
sampled every microcycle. The INTrtM signal generates an interrupt at IPL 16 (hexadecimal), This in· terrupt is internally acknowledged by the CPU and does not use an interrupt acknowledge bus cycle.
Halt (HACT)-This signal results in an interrupt used to halt the execution of macroinstructions,
and is sampled every microcycle. At the conclusion of the current macroinstruction the CPU
executes an external processor write cycle (CS< 1:0 > = 10 and DAL< 05 :00 > =111111) and then
enters the restart process. The restart proce$s sets !Qe CPU to a known state and then passes control to user code beginning at physical ad<lress 20040000 (hexadecim~). Fgr a description of the restart
process, refer to the MicroVAX 78032 User's Guide.
DMAControl
DMA request (DMR)..;;..;.This signal is usedby the external logic ·IP take control of the DAL bus and
its related control signals.
. ··
DMA grant (DMG)-This signalindicates that the CPU has gran;~d the use of the DAL bus and its
related control signals.
Clock Signals Clock in (CLKI)-A TTI. input that provides the basic clock timing to the clock generator on the MicroVAX 78032.
Clock out (CLKO)-A timing signal output at half the frequeneyo,fb(!si~dock (CLKI) to be used for system timing.
Miscellaneous Signals
Test (TEST)-Reserv(f,d. This pin must be connected to ground. ·
Power Supply Connections. Power (V00)-5 Vde suppl)r. ·
Ground (V85)-Ground reference.
Back-bias generator (Vu8 )-Reserved. This pin must notbe.contlected..
Confidential and Proprietary
1·7
-
· Ai'chitectme Summary. The MiciUVAX 78032··~hitecture show~ in Pigure 3is. group~ foto two ,main areas. One'area is usecfhy the' application programmer and contains general registers, pointer re~isters, and the
processor status word. The remainfug area is used by the system programme!: and contains process control registers, memory management registers, interrupt registers, and the processor status longw0rd.
APPLICATIONS PROGRAMMING GENERAL REGISTER$
RO
R1
FP
R2
A3
KSP
R4
ESP
A5
SSP
A6
USP
A7
RB.
R9
R10
PROCESSOR STATUS WORD
R11
PSW
SYSTEM . PROGRAMMING
PROCESS CONTROL REGISTERS
INTERRUPT REGISTERS
SCBB
SlRR
PCBB
MEMORY MANAGEMENT REGISTERS
POBR POLR
PIBR PILA
SISR
__,I . .___ _ _..;..,s_ r _ _
. i>.STLVL
PROCESSOR STATUS LONGWOfl D
l1PLI PSW
SBR SLR
MAPEN
Figure 3 ·MicroVAX 78032 Programming Model
1-8
Confidential and Proprietary
Preliminary.
MicroVAx 1sn;2
General Registers Sixteen ?2~bit g~~. registers are included and can be used for temporary. storage, as accumu-
lators, as ~ ~isters, and index registers. The registers used for specific functions are the stack
pointer (SP), argument pointer (AP), frame pointer (FP), and program counter (PC).
Stack pointer-The stack pointer (S;?) rontains tbe. address of the.pl,'OCesSQr defined stack: There are five stack pointers, onefor each 0£ the four opera.ting ntode.s of· theprocesl!or and.onefor use by
the system for handling interrupts. The stack pointer in use is determined by theoperating mode of the processor. Arlumeotpoin1-·-'The Vl\Xptocedure call<:onvention.uses.an·~ntlist data.structure. The argument pointer (AP) contains the address of the base of this structure.
&ame pointer-The VAX procedurecallconveo.tion·builds adata structu,fe on the stack&ame. The frame pointer contains the address of the base Qfthis structure. Program counter-The pl'ogtani oounter (PC) contairis the addte8s of the next byte oHhe program.
Therefore, the PC is not used as an accumulator, in~, ortemporaryfogister.
Ptocessor StatUs Word The proebssor status word (PSW), the lo\ver 16: bits of the PSL~ con~s the condition Codes and trap enable flags, The PSW is the user l:lceessible portio!lofthe proelesSOtstatus lohgwurd (PSI;} and is shown in Figure 4 anddescribed in 'lable 6.
: : +· : : I I I I I I I 15 14 13 12 11 10 ·® Oii Q7 I)!;. 05 04. ;. ~ o.~ 01 OQ DV FU ] IV T N z v c 1.:Pl!W
Figure 4 · MicroVAX 78032 Processor Status Word Format
Bit Description
15:08 MBZ (Must be zero).
07:04 'Ii:ap Enable Flags-,..,These bituause tlll.pSto occur under the following conditions. DV (Decimal overflow)-Used by the emulation software in the emulation of decimal instructions. FU (Floating underflow)-When set, this bit causes a floating underflow fault after the execution of any instruction which produced a floating result too small in magnitude to be represented. IV (Integer overflow)-When set, this bit causes an integer overflow trap after an instruction that produced an integer result that could not be correctly represented in the space provided. T (Trace)-When set, this bit causes a trace trap to occur after the execution of the next instruction.
03:00 Condition Codes-These bits contain information related to the result of the last CPU arithmetic or logical operation. The bits are defined as follows: N = 1 if the result was negative.
Z = 1 if the result was zero. V = 1 if the operation resulted in an arithmetic overflow.
C = 1 if the operand resulted in a carry-out-of or borrow-into the MSB (Most$ignificant Bit).
Confidenti.al.and. PtQprietary
1-9
Preliminary
System Registers The system .registers are privileged registers that are accessed by the operating system. These registers ·are used in context switching, memory: management, exception and· interrupt· handling, and processor control.
System control block base :register--The system control block base register (SCBB} contains the base address of the system control block (SCB). The SCB contains the vectors used for servicing interrupts and exceptions.
Process control block base register-The processor control block base register (PCBB) contains the baSe address of the process control block (PCB). The PCB contains the hardware oon~ext of the current process.
Memory management registers-These registers are used by the system to control the memory management unit of the MicroVAX 78032 and to access the page-rnble entdes in memory used to translate virtual addresses into physical addresses. The function, of each of these registers .is described in the memory management section.
Interrupt registers-These registers are used to control the interrupt system o.f !he proceSS()l,' by storing interrupt requests, current interrupt priority level, and· the internipt stack pointer. The function of eaCh of these registers is described in the Exception and Interrupt section,..
Processor status longword-The processor status longword· (PSL) contains the processor status information. The lower 16 bits of the PSL are the user accessible processor status word. The upper 16 bits of the PSL are privileged and accessed by the system. The PSL format is shown in Figure 5 and described in Table 7.
313029282726252423222120
1615
IPL
PROCESSOR STJ\TUS WORD
00
'PSL
TP
Figure 5 · MicroVAX 78032 Processor Status Longword Format
1-10
Confidential and Proprietary
·-
Preliminary
MicroVAX:~B0.32
'Jable 7 · MicroVAX 78032 Processor Status Longword Descriptions
31 MBZ(~~t:~zero),
30 TP (Trace pending)-Forces a trace trap when set at the beginning of any instruction. Set by the processor if the T bit in the PSW is set at the beginning of an instruction.
29:28 MBZ (Must be zero).
27 FPD (First part done)-Set when an exception or:fat~l)rllpt ()CCUfS during an instruction
that can be suspended. If FPD is set when the procesSor returnsfrom an exception or
interrupt, it resumes the interrupted operation where it left off, rather than restarting the
instruction.
26 IS (Interrupt stack)-Set when the processor is executing on the :ipterrupt stack.
25:24 CUR MOD (Current access mode)-The access mode ofthecurrebtly executing process as follows: 0 =Kernel
1 = Executive
2 = Supervisor 3 =User
23:22 PRV MOD (Previous access mode)~Loaded from CUR;M{.lD by exceptions and Change Mode instructions, cleared by interrupts, and restored by REI.
21 MBZ (Must be zero).
20:16 IPL (Interrupt pri9tjty level)~S:91ltaios the ~1ltP~sor prigrity in the range 0 to lF
hexadecimal. The processor will accept interrupts ottly on l~ gre~~ than its current IPL.
15:00 PSW (Processor statusword)-Contafns the processor status accessible by the user.
Confidentlalarid Pnlprietary
-·---~----------·-----------
1-11
· Data 'l}rpes
The architecture of the MicroVAX 78032 supports nine data types: by,i~! \VAJ:d.Jongw(}td,
quadword, character string, variable-length bit field and, through the option~lfl~~ti~-roint ~nit, F_floating, D_floating, and G_floating. Figures 6 and 7 show the organizatihn ufthe ci'ata types.
I;::::::I ' '
t;f/
' SYTE
.
00 '
:A '
WORD
f: ::::::::::::::001 :A
LONGWORD
r: .: ::::,::::::::::::.:::.::::::.::::001 :A
OUAOWDRD
CHARACTER STRING
Cc07 :J::JAA+00 1
l
I:::::::I 07
:
00
A+L-L
VARIABLE LENGTH BIT FIELD
I I P+S P+S-1
P P-1
FFFFFFFFFFFFFFFFFFFFFFFFFFFFF
S.1
00
I00 :A
Figure 6 · MicroVAX 78032 Integer, Character-string, and Bit-field Data Types
'1-12
Confidential and Propi'ietary
Preliminary .·. ·'·
F _FLOATING 15 14
07 06
00
31 D_FLOATING
15 14
s]
63 G_FLOATING
15 14
EXPONENT
07 06
1
FRACTION
FRACTION
.Ff!ACTION
;~ACTl~N
. l
-1
00
:A+4
_J_
48
:A+6
EXPONENT FRACTION
FRACTION
:A :11.+~'
63
48
Figure 7 · MicroVAX 78032 Floating-point Data Types
· Instruction Formats
The VAX instruction set has a variable length instruction format that may be one byte or more
depending on the type of instruction. The general format of a VAX instruction is shown in Figure 8.
Each instruction consists of an opcode followed by as many as six operand specifiers. The number
and type of operand specifiers depends ..on.the opcode.·Allop,erandspecifiers are of the same
format: an address mode plus additional information used to locate the operand. This additional
to and information contafos up f\Vo register designat6rs ad::Jresse$, data, or displacements. The use
of the operand is determined from the opcode and is called the operand type. It includes both the
access type and the data type,
·
Confidential and,P:roprietary
-.-- .. . ·~..
~ ....._.,..,..~ ......-~--·--·-~·-·-..,---·-·-·-----~-~·····-·---·------------~
Preliminaty.
. OPCODE 0 OR 2 BYTESI
.l OPERANO SPECIFIER 1
OPERAND SPECIFIER 2
OPERAND SPECIFIER 3
I
I
I
J...
I
.,,_
OPERAND SPECtftER 6
MfM190!
Figure 8 ·MicroVAX 78032 Instruction Format
Opcode Formats
.. . .
.. .
The opcode specifies the desired operation to be performed and may be one or. two bytes,
depending on the contents of the byte at address A. The opcode consists of two bytes if the value of
the byte at address A is FD (hexadecimal). Figure 9.shows th(! opcode formats.
ONE BYTE OPCODE:
TWO BYTE OpQODE:
Figure 9 · MicroVAX 78032 Opcode Formats
1-14
Confidential and Proprietary
Preliminary
· Addressing Mqdes
A summary of the addressing modes used by the MicroVAX 78032 is listed in Table .8 with a brief
description of each mode.
. ·
Table 8 · MicroVAX 78032 Register Addressing Modes
General Register Addressing Mode
Hexadecimal
0-3 4 5 6
7 8 9
A ll
c
D
E F
Name
Assembler r
literal index
s· #literal y
i (Rx)
y
register
Rn
y
register deferred
{Rn)
y
autodecrement
-(Rn)
y
autoincrement
(Rn)+
y
autoinctement
@(Rn)
y
deferred
byte displac;ement
byte displacement
B' q(}\n) y
@J?) d(R.~)
deferred
word displacement word displacement
W'd(Rn) y
@W~d(ltn)·y
deferred longwotd displacement .. L'd(~n). y
longwci.rd diwlacement @L'd(:(ln) y
deferred
Aecen
mwa v
f f
y y y y
yyf y
y y y y
y y
y
y yyy
y y y y
y yy y y yy
y y y y y y y y
y y y
y y y .Y
PC SP Indexable?
f
u
f
u y
y
u .y
ux
p y
ux
p y
ux
p y
y
p y
y
p y
y
p y
p y.
y
p y
y
·Program Counter Addressing Mooe
Hexadecimal Name
···· Assembler ..ii
W··. 8:· ...\'·
8
immediate
r #consi:nnt y ·u u y y
9
absolute
@#addregs· y · y·· y 1 y
y
A
byte relative
B' address y y y y y
y
B
byte relative defet;i:ed @~· addressy y y y y
y
G
word relative
W'. addrei;s. y y y,
y
y
D
word t"elative deferred W'a~C$S y y y .Y Yi
y
E
longword relative
L' ad4ress y y y y y
y
F
longword tdative
L·address y y y y y
y
deferred ·
Confideritial and;Hropiietary
1·15
Table 8 · MicroVAX 78032 Regist.er Addressing Modes (C6rtt:J1··
Access:
r =read m =modify w =write a =address v ""fidd
Syntax:
i = any indexable address mode d = displacement
Rn = general register, n = 0 to 15 Rx = general register, x = 0 to 14
Results:
y = yes, always valid address mode
f = reserved address mode fault
- = logically impossible p = program counter addressing u = unpredictable
uq = unpredictable for quad, D_/G_floating, or field if pos + size > 32 ·
ux = unpredictable if index reg = base reg
General Register Addressing
The general register address modes use one or more general registers, depending on the instruction
and data type, or information required to locate the operand(s) to be lised by the specifi<:!d
instruction.
Register mode-:-.The operand is contained in one of the general registers (Rn).
Register deferred mode-Register Rn contains the address of the operand.
Autoincrement mode........Register Rn contains the address of the operand. After the operand address is determined, the size of the operand in bytes is determined by its dafa type and is added to the contents of register Rn and the result is placed in register Rn.
Autoinct"ement deferred mode-Register Rn contains a longword address that points to the operand address. After the operand address has been determined, the number four is added to the contents of Rn and the result is so tred in Rn.
Autodecrement mode-The size of the operand .in· bytes is determined by its data type and is subtracted from the contents of Rn and the result is stored in Rn. The updated. content of register Rn is the address of the operand.
Literal mode-Literal mode addressing provides an efficient means of specifyinginteger constants
in thetange of from 0 to 63 (decimal). In addition to short integer literals, this mode can be used to
specify floating-point literals. The value is contained in the operand specifier.
Displacement mode-The displacement contaitled in' the operatid specifier, after being sign-
extended to .32 bits if it is a byte or word, is added fo the contents ofregister Rn, and the result is
the operand address.
·
Displacement deferred mode-The displacement contained in the operand specifier, after being sign-extended to 32 bits if it is a byte or word, is added to the contents of register Rn, and the result is the operand address.
Confidential and Proprietary
n...-1!......:.!_ _ _
rre.umuuu:y
Index mode-The operand specifier consistfof two bytes or more, a primary operand specifier and
a base eperand specifier. The primaryoperand specifier, contained in bits 0 thro-ugh 7, iucludes the ·index register (Rx) and a mode specifier of 4. The address of the primary operand is determined by multiplying the contents of index ~ter Rx by the size of the primary operand in bytes which is
determir,led by c>pe!mn.d type~ Thisyalue is then adde<l !)) the ~gress spet;ified by the b~ operand specifier (bits 15 through 8), and the n;sµlt 'is the pij~ry qpeliand addtess.
Program Counter Addressing Register 15 is used as the program counter (PC). It can also be used int}+~ a~ing;rqo<les, lhe processor increments the program counter as the opcode, operand speclfie~ ~nd immeruat~ data or
addresses of the instruction are e:Valuated/fhe atl1f)U!lt thatthe·PC isincremented is deterritlnedby the opcode, number of openind specifiers artaother values. The PC can be used with allofthe:VAX addressing modes, ex&pt regiSter; index, rtjµs'ter defetred; or autodecrement.
Immediate mode-This mode is an autoincrement mooe.andthf! PC is~.as the general register. The contents of the location followingthe~ddres8lngmdde corltainiminediaie data.
Absohlte mocle-Thls mod~ i~ . ~· ~ufofu~rerilerit d~.fer~~. @de using the .J?C. as the general
registe.c The contents of the location following the addi!essing·mode··are takeh as the operand
address. This is interpreted as an absolute address that is an address that n;~ ~t~µ1;jn .th,e
memory locaticmwhei;e .~ ~seml?led.ipstruajo.114~~t&;L
Relative mode--Thismode is a displaeement mode and the PC JS' uSed as1hecgeneral tegister. The
displacement that follows the operand specifier is added to thePC lltld thesum is1the address of the
operand.
ReJative deferred mode-This mode is similar to the relative mode except that the displacement, which follows the addressing mode, is added to the PC and the sum is the longword address of the operand.
Branch Addressing
During branc.h displa<;ement adcire,ssing, the byte 9r word displacement is sign-extended to 32 bits
and added to the updated content of the PC. The'updated content of the PC is the address of the
first byte beyond the operand specifier.
.
.
· Instruction S~t
A summary of the VAX instructions implemented by the MicroVAX 78032, the floating-point instructions supported by the Sooting-point unit, and the emulated instrQctions that are assisted by the microcode are listed in Appendix A..
Operand Type The operand type specifies the use of the operand that is associated with an instruction. The opcode includes the data type of each eperand and the method of acce::;s as follows: 1. Read-The specified operand is ready-only. 2. Write-The specified operand is write-only. 3. Modify-The specified operand is read, may be modified, and is written. 4. Address-Address ddculation occrns Utitil tHe address of the . operand is obtained. In this
mode, the data type indicates the operand size to be used in address calculation. The specified operand is not accessed directly; however, the instruction may use the address to access that operand.
1-17
Preliminary
5. Variable bitfield base address"'-If only .register REnl is spedfied; the fie4lis ii1 generalregister R(nJ or in R[n +' l}'R[n] (i.e., R[n + 1] concatenated with R[n]); If R{rl]is not specified, an
address calculation occurs until the actual address of rbe operand is obtained; This address
specifies the base to which the field position (offset) is applied.
6. Brancfl.--No operand is accessed. The operand specifier is the branch disptacernent and the
data type indicates the size of the brarich displacement.
.
· Memory Management
The mem9ry management. unit provides. a. flexible and efficient virtual memory programming
environment. Memory management and the operating systempr.ovide paging with user control
and swapping. It also provides four hierarchical modes-:-kernel1 executive, superyiso,r, and user, with ~ad/write.access control for each mode.
The VMS Virtual Merriory System provides a large address space and allows programs to tun with
small memory configurations. Programs are executed in a process environment. Each process can
operate with. an address space of 4-billion bytes.
·
V'trtual Address Space·
Memory management divides the virtual address space into two spaces of.equal size-the system space and the process space. The process space is divided into PO and Pl regions. Figure 10 shows 'the virtual address space assignments.
00000000
PO REGION
3FFFFFFF 40000000
1 FF f'f FF F
80000000
P1 REGION
SYSTEM REGION
BFFFFFFF
caooqooo
l
l
1
LENGTH OF PO REGION IN PAGES· IPOLRI
PO R:EGION GROWTH DIRECTION
P1 REGION GROWTH DIRECTION
LENGTH OF Pl REGION IN PAGES 12..21-P1 LAI
LENGTH OF SYSTEM R~GION IN PAGllS (SLR)
SYSTEM REGION GROWTH DIRECTION
RESERVED REGION
FFFFFFFF
Figure 10 · MicroVAX 78032 VirtualAddress Space Assignments
1-18
Confidential and Proprietaty
-··.
Preliminary
MicroVAX 780J2
V'artual adchess format-A 32-bit virroal address is generated fur each instruction ancl operand in
memory. As the process is executed, the processor translates each virutal address into a physical ~s; The4>rmat q£.~ ~irtual address is shown in Figure 11 a® describ~d in Table 9.
Page pl.'Ot.ed'ion-Independent of its location in virtual address space, a page of5U bytes may be
protected according to its use. A Pl'9gWXl ~y,g~teany ~ss;.hQWe\'~. Plet>~Jll may be
prevented prevented
from from
macocdesifsyininggoorriDacocdCi$fYSiilnlggppoorr~tioonnssoof!t}pireoseheassn:s9pasxcse,.te;n·space.
A··progi;·am
ma·y·.
also
be
V'irtual address $p8ce l~t....:~sstO thePti,P1, and Sys~eni 1-e,iions·is Cohtrolled by the {PDLR,
PltR, ancl SLR)length registers; Within: the limits set bftlie leilgth regiSte&; ·tlie' 'acce8S; is
controlled by a page table that specifies the validity, access requirements, and location of each page
inthe region.
Figure 11. · Mi~VAX 780)2 Virtt14l~.Format
Bit 31:09
08:00
Tahle 9 · MboVAX 780)2 V'ittuai ~ ~s ·
Descriptions
VPN (Virtual Page Number)-This field specifies the virtual page. to be referenced.
Virtual.address ~e cont~ 8;3~8.608 pages of~U bftes eacli.
Bits <31:30> of the ,VPN select the region of virtual ad~ss space being
referenced as follows: ·
·
.
Value of
Region
Bits <.31:30> Referefl(:ed
d
PO ...
1
Pl
2
Sys~ni
3
. · Reser\?¢d
Byte number-This field speclfiesthe number of~hC byte within the page.
Access Control The access control fon<;tiori detei;tnines whether a read or wri~.~ory ref~ will be all~ to a memory page. Every pagein tnemory is assigned a protectiOnicc.xk to preVent illegal access to
memory information.
Confidential and ProprietarY"
1-19
,MIKJe,..,...'ifhcdourhimucliical tiIWdes.'tlsed··h¥ theMitroVAX:780321n.the'!QtCJer of,most :.toJeast
privileged are
o Ker1ietili..ti~ed tiy theketiiel·of ·the operating sgsrerti for~age·mariagem~nt!,· schedlilirig; and
' · l/O:drivers. ·
· f''E.'Keouti\reLused for matfy ofthe operating syistem service ~alls:
2 .Sui}ei:visbr:::used £6r services;s~clf~scommand interpremibn:
~·.. Us,t;r-;:µsep for user level code', u'tiHties, co~pilers?Aehugg~rs, ~t,c:
, .
~-' '
,. ,' ,;
' : ' · ;- '
·
·
-·
''
· '
--_ -
;
,'
· - ' '- ; < i : -.; : ·' _,' - ' '
,. - ·. >,,-
'" t: : -_;
'fhe curre~t p~c~9r rm;ie,e is ~tared in the current mo<fl'= .field o,f the prqcess.orstatµs lpngV!Qrd
.(,PSL);
. . .,
·.
Protection code-A protection code, located in the page table entry for that page, defines the accessibility of the page for each mode. These codes are described in Table 10.
Table 10 · MicroVAX 78032 Protection Code Assignments
Decimal
Code
Binary Code
Mnemonic K
Currebt MOde
E
s
u
Comment
0
0000
NA
no access
1
0001
2
0010
3
4
0100
··uw
'Rw· RW
~
0101
EW
RW :RW
all access
6
0110
ERKW
R
7
0111
ER
R ..
R
~
8
1000
SW
RW 'RW RW
9
1001
SREW
RW RW R
10
1010
SRKW
RW
11
·roll
SR>
R
R
R.
'....;-+c!
12
1100
URSW
RW RW RW R
13
14' u·
1101
UREW
····1no} · :-;(· ·u.R:rc=w·
RW RW R
R
RW R:
R'·' i ..RP.I·
15
1111
UR
R
R
R
R
.. ' ', ).~ - . .!
Legend:
- = noaccess
* = unpredictable
R =read only
RW= read/write
K =Kernel
E =Executive
s = Supervisor u =User
W =write
Confidential and)Proprietllry
-
MicroVAX78032
· Memory Management Control
Three registers are used to control memory management .. One register is used to enable and disable
memory management and the other two are used to control the address translation buffer.
Memoey Management.Enable
The map enable register (MAPEN) determines whether ·the .l1lemory management functions is
disabled or enablecL The fqrrnat of the map enable: regi1Jter is. shewn in Figure 12 :ind described in
Table 11.
·
'·
·
·
31
. .
.
...
. .
. 0100
I::::::::::::::~: ·; :::::.::'. '. :::11 :MAPEN
I
MME
Figure 12 · MicroVAX 78032 M.ap Ena[J/q Register Format , '>, ,. c·."> . '
Table 11 · MicroVAX 78032 Map Enable ~Ster Description
Bit Descriptions
31:01 MBZ (Must be zero).
00 MME (Memory management enable)-used to enable and disable memory management as follows:
1 =M M E1enabled
0 =MME disabled
Translation Buffer
The translation bUffer stores frequently used fl.lemory page references. The translation buffer
stores eight entries that contain page table entries(P'FE) iorsu<:eessful:virtUal address translations.
py It is cont.rolled the.~ti0n.bi.¢fc;r iilvali~te s~ (Tl31$)j;egister and the translation buffer
invalidate all (TBIA) register. ·
· · · ·. . ·
. ·
The TBIS register invalidates single PTE entries in the translation buffei: This is accomJ.5lished by the system software by writing a v.irtuaL address into the .TBlS register shown in Figure 13. The MicroVAX 78032 will invalidate the translation buffer entry that maps 'to the page in virtual
memory accessed by the virtual address written into the register.
The TBIA register clears the.translation buff~ by invalidating all .t1le PTEs.inthe trans}atjon buffet
This is accomplished when the system: s0ftWt.re writes a ointo the TBIA register shown in Figure
13. When a 0 is written into the TBIA register, all the PTEs in the translation bUffer will be invalidated.
~
00
I::::::::::::+~+:A~oHss: :::::::::::I :TBIS
r: ::::::::::::::+: ::::::::::::::001 :TBIA
Figure 13 · MicroVAX 78032 Translation Buffer Registers
·Confic:Lmtial amlProprietary
1-21
- __________ ... ................ .. -~~·----- -·---------·---~-----~
·------·-~·'"""'""
MicroVAX 78032
Address Translation
Translating a virtual address into a physical address by the memory management unit is controlled
by the memory mapping enable (MME) bit fo the MAPEN register. When MME=O, the memory
mapping is disabled, bits < 29:00 > of the virtual address become the phy~ical address, and access
is allowed in all modes. When MME= 1, the memory mapping is enabled and the virtual address is mapped to a physical address by the memory management. The address translation process when memory management is enabled is as follows. Page table entry-All virtual addresses are translated to physical addresses by a page table entry (PTE) shown in Figure 14 and described in Table 12. Protection check before valid check-The page table entry contains a valid bit that controls the validity of the modify bit and page frame number field. The protection field is always valid and is checked first.
OWN
Figure 14 · MicroVAX 78032 Page-table Entry Format
Table 12 · MicroVAX 78032 Page Table Entry Descriptions Bit Descriptions 31 V (Valid bit)-Governs the validity of the M modify bit and the page frame number (PFN)
field. V =1 for valid; V =0 for not valid.
30:27 PROT. (Proteetion field)-Describes the protection for the page. This field is always valid
and is used by the hardware even when V=0. 26 M (Modify)-This bit is set (=1) if the page has already been recorded as modified. M =0
if the page has not been recorded as modified. Used only if V = 1.
25 0 (Zero)-reserved. 24:23 OWN (Owner)-reserved. 22:21 0 (Zero)-reserved. 20:00 PFN (Page frame number)-The upper 21 bits of the physical address of the base of the
page. Used if V = 1.
1-22
Confidential and Proprietary
-
Preliminary
MicroVAX 180.32
System Space Address ltanslation A virtual address with bits 31 at1d 30 equal to 2 is an address in the system virtual address space
that is mapped by.the system page table (SPT). Tue·sPT is located in physical memory and its
location and length ime defined by the system base register (SBR) and the system length register (SLR), Figure 15.The SBR contains the phys~cal ~.$of the system page t11.ble. The SLRCQ~s
the size of the SPT in longwords that is the.n'lJRlb« of page table entries. The page table entry
pointed to by the S~R llljlps to the first P · ofsystem virnW: ~ spa!'.:C .that is virtual~byte ad~ss 80000000 (hexadecimal);.
Figure 16 shows the translation of a system virtual addresHo a physical address;
The algorithm used to generate a physical ad.chess from a system rCgi.on virtual address is
SYS_PA =(SBR+ 4*SVA < 29:9>) < 20:00 > SVA <08:00 >
Figure 15 · MWIVVAX 78032 System Mapping P.egister Formats
SVk !SYSTEM VIRTUAL, ADDRESS)
31 0
E.~JRAC"f ANO
CHECt< LENGTH
ADD
0:2 0100 0
PTE:
CHECK ACCESS
PHYSICAL AOR OF CATA:
2120
FeTCH
PFN THIS ACCESS.q.tECK tN CU'JIP:ENT· MODE
09 08
Figure 16 · MicroVAX 78032 System Virtual-to-Physical Address Translation
Confidential"and Proprietary
1-23
Preliminary
MicroVAX 78032
Process Space Address Translation
. ,
A virtual acldress with bitJ 1 s.et to 0 is an adpress in the process vil'tl,lal address space. The process
space is divided into two equal sized, sepaqitely mapped regions. If virtual address bit 30 is set to 0,
the address is in region PO. If virtual address bit 30 is set to 1, the address is in region PL
PO region addreSs translation;_ The PO region of process address space is specified by the PO page
table (POPT). The.POPT is located in system virtual address and its location and length are defined
by the PO base register (POBR) and the PO length register (POLR), Figure 17. The POBR contains the
system virtual address of the PO page table. The POLR contains the size of the POPT in longwords,
that is, the number of page table entries. The page table entry pointed to by the PO base register
maps
the
first
page
of
the
],JO
region
of
the
v i r t. u a l
address
space,
that
is·, ,
virtual
byte
address
O. .
Figure 18 shows the translation of a PO virtual address into a physical address.
The algorithm used to generate a physical address from a PO region virtual address is
PVAYTE =POBR + 4*PVA < 29:09 > PTE_PA= (SBR +4*PVA_PTE < 29:09 >) < 20:00 > 'PVAYTE < 08:00 >
PROC_PA = (PTE_PA) < 20:00 > 'PVA < 08:00 >
:POBR
Figure 17 ·MicroVAX 78032 PO Region Mapping Register Formats
(PROCESS PVA:
VIRTUAL
ADDRESS I
31
23 22
EXTRACT AND CHECK LENGTH
02 0100 0
AOD
31
0100
POBR:
I:::::::: :+:+~+H0H+~::::::::: If I
VISLOS
31
0100
I:::::::::s(s:+f+:AHO~P~E: : : : : : : : : : Ii I
3130
FETCH BY SYSTEM SPACE TRANSLATION ALGORITHM, INCLUDING LENGTH AND -KERNEL MODE ACCESS CHECKS
2120
()()
PFN
CHECK ACCESS
TH IS ACCESS CHECK tN CURRENT M()DE
29
09 Oil
00
PHYSICALAOR OF DATA:
Figure 18 ·MicroVAX 78032 PO Virtual-to-physical Address Translation
1-24
Confidential and Proprietary
MicroVAX 780.32
Pl region address translation-The Pl region of the address space is specified by thePl page table
(PlPT). 'The PlPT is located in the system virtual address space and its location and length are
defined :by the Pl base register (PlBR) and the Pl length register (PlLR), shown in Figure 19. Because the Pt space eXpands toward smaller addresses, and a consistent hardware interpretation of the base andlength registers is desirable, the Pl:BR and Pl LR contain the portion ofthe P1i:!!pace
that is nbt accessible. Note tharPlLR containstlletitimber of nonexistent PTEs. PlBR connilns the system virtual address of what would be the PTE for the first page of Pl, which is the virmal byte address 40000000 (hexadecimal). The address in the PlBR may not be a valid system virtual
address; however, all the addresses of PTEs must be valid system vit:tval ~~. J?igµre 20 sl;i.ows
the Pl virtual address to physical address translation. The.algc)rithm used to gen~rate ~ physi~aladctre~sfroJl1 aPl'~onyirtualaddress fa
PV.AJTE =PlBR +4*PVA <29:09 > PTE_FA =(SBR +4*PVA_l"fE < 29:09 .~) < 20:00 >'PV.AJTE <08:00 >
. . PROCYA =(YfEYA) ~20:00 >'WA< 08:00 > . .
I::: ::I: :; l 31
2221
00
~:: ' ., . ' ' '- ··- ", :+~'~_,?1+--H. +-. ~-· ~'+..+"+:''":' .:-:, 'PILR
Figure 19 · MicroVAX 78032 Pl Reyj~Mapping Register Formats
PVA: (PROCESS VIRTUAL ADDRESS)
EXTRACT ANO <:-HECK -LENGTH
090if
00
llYTE
020100
ADO
~
moo
PlBR, I:::::::::+:vH+H+1+~: :::L;:::Ifl
I~ :::::::::
VIEL.OS
H~++~+~+H::
:,:
:::::Im?ooI
3130 PTE:
FETCH BY SYSTEM SPACE TRANSLAilON ALGORITHM, INCLUDING LENGTH ANO ~ERNELJllOOli ACCESS CHECK$
2120
00
PFN
CHECK ACCESS
nus ACCE;SS C;tiECK
tN CURRENT MOOE
29
00
PHYSICAL AOR OF DATA:
Figure 20 ·MicroVAX 78032 Pl Virtual-to-physica/Address Translation
Confidential 1md Proprietary
1-25
MicroVAX 78032
Memory Management Faults
The two types of fal.llts ~sociated with memory mapping and.protection are translation not valid and access control violation. An access con;trol violation fault exists when the protection field of the PTE indicates that .the intended page reference in the specified access mode is illegal. A tran$lation not-valid fault exists when a read .or write reference is attempted through an invalid
PTE. If an access control violation and a translation not-valid faults occur, the access control takes
precedence.
· Exceptions and Interrupts
During system operation, events that are not related to the current process can require service. These events cause the processor to interrupt the process being executed and transfer control to a
program that will service the event.
An exception is the notification of an event that is relevant to the currently executing process and
normally invokes a program in the context of the executing process. An interrupt is the notification of an event that is relevant to other processes or to the system and is serviced in a system wide context. The system wide context is defined as executing on the interrupt stack. The priority associated with the interrupt is the interrupt priority level. (IPL).
Interrupt Priority Leve1s The VAX architecture includes 31 priority interrupt levels. Fifteen levels (1 through F hexadecimal) are software related and 16 levels (10 through lF hexadecimal) are hardware related. Table 13 lists the interrupt priority level assignments for the MicroVAX 78032.
Table U · MicroVAX 78032 lnterrupt Priority Levd Assignments
IPLLevd Interrupt Condition (hexadecimal)
lF
unused
1E
PWRFL asserted
18-lD
unused
17
iRQJ asserted
16
INTTIM asserted
16
IRQ2 asserted
15
nm-r asserted
14
IRQO asserted
10-13 01-0F
unused software interrupt request
1-26
Confidential and Proprietary
-
MicroVAX 78032
Interrupt Requests Interrupt requests are serviced during the execution of long interactive instructions such as string instructions and at the completion of an instruction.
Urgent interrupts.......lnterrupt level 1E (hexadecimal) indicates a powerfail condition and requires
immediate service in the MicroVAX 78032.
Device internipts-Interrupts 14 through 17 (hexadecimal) are assigned to the peripheral devices operating with the MicroVAX 78032.
So£tware interrupts-Interrupts 1 through Fare used by the MicroVAX 78032 system to generate
software controlled interrupts.
· ·
Interrupt Registers
The interrupt system is controlled by the int~pt pri¢rity level register (IPL), the software
interrupt request register (SIRR), and the soft~ interrupt ·~ary register (SISR).
~-~ -
' " ----
Software interrupt summary iegister-The sof~ inUU'rupt summary register (SISR), shown in
Figure 21, is a privileged register that records1:11:e~.so(~ interrupts. A 1 is set in the bit
position corresponding to levels on which so{twt11'¢ in~pts:~ pending.
PENOINGSOfTWAAE·INTEFt·llUPTS F E J) ~ 8 A 9 8 18 S .4 3 2 1
:SISR
MBZ
Figure 21 · MicroVAX 78032 Software Intemtp,tSummary Register Format
Software interrupt request register-The software interrupt request register (SIRR),. shown in Figure 22, is a write-only, 4-bit privileged register used for maldng. a software lliterrupt request. The software requests an interrupt by writing the appropriate interrupt levelto the SIRR. Once a
software interrupt request is made, the corresponding bitin the SISR is set. The processor will clear the bit in the SISR when the interrupt has been acknowl~.
31
I:::::::::::::l~+H
::::::::::04H00 +H00
SIAR
Figure22 ·MicroVAX 78032JntemtptRequest Regis~ Format
Interrupt priority level register-Writing to the IPL register, shown in Figure 23, loads the
processor priority field in the processor status longwood (PSL).
++H 31
05 04
00
I:::::::::::+iRf~ 0:::::::I::::I:IPL
'---v---'
PSL<211: 18>
Figure 23 · MicroVAX 78032 Interrupt Priority Level Register Format
Confidential and Proprietary
1-27
mDllDID
MicroVAX 78032
· Exceptions
An exception is an event that is the direct result ofexecuting a specific instruction. Exceptions also
include errors automatically detected by the proeessor, such as improperly formed instructions. The MicroVAX 78032 recognizes the six classes of exceptions summarized in Table 14.
1Bble 14 · MicroVAX 78032 Classe.s of Exceptions
Exception Class
Condition
arithmetic traps/faults
integer overflow trap integer divide by zero trap subscript range trap floating overflow fault floating diVide by zero fault
floating underflow fault
memory management exceptions access control violation fault translation not valid fault
operand reference exceptions
reserved addressing mode fault reserved operand fault or abort
instruction execution exceptions
reserved/privileged instruction fault emulated instruction fault extended function fault breakpoint fault
tracing exceptiori
trace trap
·system failure exceptions
memory read error abort memory write error abort kernel stack not valid abort interrupt stack not valid abort machine check abort
System Control Block
The system control block (SCB) is a page in physical memory that contains the vectors for servicing interrupts and exceptions. Table 15 shows the type and location of the vectors. The SCB is pointed to by the system control block base register (SCBB), Figure 24.
3130 29
MBZ
PHYSICAL LONGWORD ADDRESS OF SCB
0908
MBZ
:SCBB
Figure 24 ·MicroVAX 78032 System Control Block Base Register Format
1-28
Confidential and Proprietary
Pt-eliminary
Table 15 · MiaoVAX 78032 System Control Block Vectors
Vector
Vector
Type
Address
Name
(hexadecimal)
00
unused
abort
04
machine check
abort
08
kernel stack not valid
interrupt
oc
powerfail
fault
10
reserved/privileged
fault
instruction
14
extended instruction
farilt/aboi-t
18
reserved operand
fault
lC
reserved addressing mode
fault
20
access control violation
farilt
24
translation not valid
fault
28
trace pending(TP)
f~t
2C
breakpoint instruction
30
unused
trap/fault
34
arithmetic
38-3C
unused
trap
40
CHMK
trap
44
CHME
trap
48
CHMS
·trap
4C
CHMU
50-80
unused
interrupt
84
software level 1
in~rrupt
88
software level 2
SC
sofnyare level 3
interrupt int;errupt
90-BC
co
s0ftware levels 4-15
interval timer
1nterrupt
C4
unused
fault
CB
emulation start
fault
Confidentialand Proprietary
1-29
...
MicroVAX.780.32
Table 15 · MicroVAX 78032 System Control Block Vectors (Cont.)
Vector
Vector
Type
Address
Name
(hexadecimal)
cc
emulation continue
DO-FC
unused
interrupt
100-lFC
adapter vectors*
interrupt
200-3FC device vectors*
*Used by the MicroVAX 78032 to directly vector interrupts from the external bus. The vector is
determined from bits < 9:2 > of the value supplied by external hardware. If bit < 0 > of the offset
is 1, then the new IPL is forced to 17 hexadecimal. Only device vectors in the range of 100 to 3FC hexadecimal should be used, except by devices emulating console storage and terminal devices.
·Process Structures
A process is .the basic entity scheduled by the system software. The context of the current process is contained in the process control block (PCB) shown in Figure 25. The PCB is located in physical memory and is pointed to by the process control block base register (PCBB) shown in Figure 26.
1-30
31
t5IJ MBZ I
MBZI
PM:I.
MBZ
l
NOTE: THE PME FIELD IS UNUSED.
KSP ESP SSP USP RO R1 R2 R3 R4 R6 R6 R7
RS
R9 R10 R11 AP {R121 FP{R13) PC PSL POBR
P1BR
POLA P1LR
00 :PCB +4 +B +12 +16 +20 +24 +28 +32 +36 +40 +44 +48 +52
-+66
+60
+68 +72 +76 +80 +84
+92
Figure 25 · MicroVAX 78032 Process Control Block Assignments
Confidential and Proprietary
-
MicroVAX 78032
Figure 26 ·MicroVAX 78032 Process Control Block Base Register Format
· Processor RegiSters The MicroVAX 78032 processor contains many registers ~t:~ acc;essible to the user. These
registers are listed in Table 16 and.~ groupsdc;~ribed by the following categories. 1=Registers implemented by the MicroVAX 78032 as specified ey the MicroVAx Architecture.
2=Registers implemented only by the MicroVAX 78032, 3 =Registers passed to the external logic ·via the .external processor .register· protocol. If not
implemented externally, they are read as ziero and result in no operation during a write cycle. 4 =Register access is not allowed (reserved opemrid fault).
Table 16 ·-
·
MiaoVAX, - .,
7.S..,o. 3--2---
Internal
'
Processor~
-.;:., . -_,
- -'
Number Register Name
:Mnemomc 'Fype ..·.~. initialif.e. Category*
0
Kernel Stack Pointer
KSP
RW PROC
1
1
Executive Stack Pointer
ESP
RW PROC
1
,, ..,-
2
Supervisor Stacie Pointer
SSP
RW PROC
1
3
User Stack Pointer
USP
RW PROC
l
4
Interrupt Stack Pointer
ISP
RW CPU
1
5
reserved
4
6
reserved
4
7
reserved
4
8
PO Base Register
9
PO L:ngth Register
POBR
RW PROC
1
POLR .Rw PROC
1
10
Pl Base Register
PlBR
RW PROC
1
11
Pl Length Register
PlLR
RW PROC
1
12
System Base Register
SBR
RW CPU
1
13
System Length Register
SLR
RW CPU
1
14
reserved
4
15
reserved
4
16
Process Control Block Base
PCBB
RW PROC
1
*Refer to Processor Register description.
Confidential and Pr,oprieta.ry
1-31
m1111ma·
Preliminaey.
MicroVAX 78032
Table 16 .. MicroVAX 78032 Internal Processor Registers (Cont.)
Number Register Name
Mnemonic Type Scope Initialize Category*
17
System Control .61ock Base
SCBB RW CPU
1
18
Interrupt Priority Level
IPL
RW CPU yes
1
19
AST Level
ASTLVL RW PROC yes
1
20
Software Interrupt Request
SIRR
w CPU
1
21
Software Interrupt Summary
SISR
RW CPU yes
1
22
Interprocessor Interrupt
IPIR
RW CPU
4
23
CMI Error Register
CMIERR R CPU
4
24
Interval Clock Control
25
Next Interval Count
ICCS
RW CPU yes
2
NICR w CPU
3
26
Interval Count
ICR
R CPU
3
27
Time Of Year
TODR RW CPU
3
28
Console Storage Receiver Status
CSRS
RW CPU
3
29
Console Storage Receiver Data
CSRD R CPU
3
30
Console Storage Transmitter Status CSTS
RW CPU
3
31
Console Storage Transmitter Data CSTD
w CPU
3
32
Console Receiver Status
RXCS RW CPU
3
33
Console Receiver Data
RXDB R CPU
3
34
Console Tunsmitter Status
TXCS RW CPU
3
35
Console Transmitter Data
TXDB w CPU
3
36
Translation Buffer Disable
TBDR RW CPU
3
37
Cache Disable
CADR RW CPU
3
38
Machine Check Error Summary
MCESR RW CPU
3
39
Cache Error
CAER RW CPU
3
40
Accelerator Control/Status
ACCS RW CPU
4
41
Console Saved Interrupt Stack Pointer SAVISP R CPU
2
42
Console Saved PC
SAVPC R CPU
2
43
Console Saved PSL
SAVPSL R CPU
2
44
WCSAddress
WCSA RW GPU
4
45
WCSData
WCSD RW CPU
4
46
reserved
4
47
reserved
4
*Refer to Processor Register description.
1-32
Confidential and Proprietary
-
MicroVAX 78032
Tablel6 ·MicroVAX 78032 Int.eroal Processor Registers (Cont.)
Number Register Namt
Mnemonic Type Scope Initialize Category*
48
SBI Fault/Status
SBIFS
RW CPU
3
49
SBI Silo
SBIS
R CPU
3
50
SBI Silo Comparator
SBISC RW CPU
3
51
SBI Maintenance
SBIMT RW CPU
3
52
SBI Error Register
SBIER RW CPU
3
53
SBI Timeout Address
SBITA R CPU
3
54
SBI Quadword Clear
SBIQC w CPU
3
55
IO Bus Reset
IORESET. w CPU
3
56
Memory Ma.rulge¢ent Enable
MA~EN: RW CPU yes
1
57
Trans. Buf. Invaliqate All
TBIA
'Sil CPU
1
58
Trans. Buf. Invalidate Single
TBIS
w CPU
1
59
Translation Buffer Data
TBDATA RW CPU
3
: ';.'~ ;, ',
60
Microprogram Break
M;6RK; RW·· CPU
3
61
Performance Monitor Enable ·
PMR· RW.· PROC ......
3
62
System Identification ·
SID
R CPU
1
6,3
Translation Buffer Check
TeCHK ?¥/ CPIJ
1
64:127 reserved
,,.,,_....,
4
*Refer to Processdr Register description.
· Interfacing Requirements
The MicroVAX 78032 connects to memory, to external circuits, and to the power &QQrce through
the connection pins on the package,. The following p~phs iJefine the power, reset, and bus connections and describe .the timing considerations for bus t}pe~tion.
Power Connections The MicroVAX 78032 requires a single 5 Vdc power supply. Eight pins are provided for power connections; four VDD pins and four Vss pins. The V0 Dpins connect to 5 V and the V55 pins connect to ground. The power decoupling and grounding is important. Decoupling the power supply is implemented by connecting a capacitor between each VDo pin and its associated V55 pin as shown in
Figure 27. The recommended capacitor type is 10 µf tantalum, + 1, -10%. The ground pins (V85)
should be connected to the common ground for the power supply at the chip.
The MicroVAX 78032 internally generates the required negative voltage that is externally available on the V88 pin. This voltage does not require filtering and the V88 pin must not be connected either to ground or to 5 V.
Confidential and· Proprietary
1-33
··ma
Preliminary
vssx
MicroVAX 78032
vccx
VSSI
MicroVAX 78032
16
ALL CAPACITORS 10 p.F TANTALUM, +1 -10%
Figure 27 ·MicroVAX 78032 Power and Reset Connections
Reset and Powerup Requirements The MicroVAX 78032 is reset by the following conditions. 1. When power is first applied, the RESET level must be held low for a minimum of 3.0 ms after
V00 has reached 4.75 V. To ensure that the internal voltages are stable before an operation begins. 2. The RESET level must be held low for a minimum of 3.0 µs if the RESET level is asserted after V00 has been at 4. 75 V for more than 3.0 ms. When RESET level is asserted, the MicroVAX 78032 stops executing instructions and enters the restart process. The restart process sets the CPU to a known state and then passes control to user code beginning at physical address 20040000 (hexadecimal). For a description of the restart process, refer to the MicroVAX 78032 Central Processing Unit User's Guide.
Bus Connections Figure 28 shows a typical interface configuration of the MicroVAX 78032 and includes control signals and bus connections. The directions of the input and output signal are indicated by the arrows on the lines.
1-34
Confidential and Proprietary
lf'ITERllUPT ·{, CONTROL
OMA
{
CONnOL
Preliminary
Hl.i.'I'
.PWRFL
iiffiiM
~
i5MR i5MG
m
R6V iiM<3:0>
55 A5
OAL<31'00>
M!cmV AX 78032 CENTRAL PROCESSING UNIT
MicroVAX 78032
ROY
--,,..-- REsET --i--.--.. CLKI
iPS 1-----..CS<2:0> _ __,r-f"_
CLKO
CS<2:0> CLKO
Figttre 28 ·MicroVAX 78032 Typical IntCrface Config,tJraR,on
·Bus Cycles
A bus cycle will be initiated by one of the following conditions:
A microcycle is the basic timing unit for abus~de. Ami~le·is shown in Figure 29 and is
defined as four cycles of CLKO·{Tl through T4}~
· ,
· Reading or writing inforltlationfrom or (:p ~~~ey or.a~~ device.
,,
,.
,. __ ,_,,,:('
_,
'
"'
'q
· Acknowledging an interrupt by reading the device interrupt vector.
· Transferring information from or to an external processor.
CLKO
Figure 29 ·MicroVAX 78032 Microcycle
Coafid~tial a~ ~prietary
1-35
....
Preliminary,
MicroVAX 18032
CPU Read Cycle
The CPU uses aCPtJ read cycle to input information from memory or an 'ijo device. A CPU read
cycle timing sequence is shown in Figure 30. A CPU read cycle requires a minimum of 2.0
microcycles and may be extended for slower memory or devices.
CLKO
MICROCYCLE
MICROCYCLE
Tl
Tl
< DAL.<:U:OO> ~~~...-~H~~·-oo_··-~~->r-~~-..,.~--~~-~--;: DATA
)-
I
I
A5
_
/
:I~---~"'~-----------/
I
! I
Figure 30 ·MicroVAX 78032 CPU Read Cycle Timing Sequence
1-36
Confidential and Proprietary
MicroVAX 78032
The first microcycle of a CPU read operation is used to transfer the address and control information and the data is latched into the CPU during the last microcyde.
The sequence of events for a CPU read operation follows: 1. The physical (longword) address is driven onto DAL < 29:02 > and the memory operand length
onto DAL<31:30> by tile CPU.
2. The WR signal is unasserted and CS <2:0> are asserted as required to indicate the type of bus
cycle being performed.
3. The BM< 3:0 > lines are asserted as requited.
4. The AS signaJ is asserted to indicate that the address is valid and can be latched for
demultiplexing and to qualify CS< 2:0 > and BM< 3:0 > information.
free 5. The i'5S signal is asserted to indicate that the bus is to receive the requested information.
The DBE signal is also asserted at this time and can be used to control the DAL bus transceivers.
this 6. If the requested data is valid, it can be placed on the bus duringT3 oft~~ ~t ~e, the
external logic asserts the RD? signal; and the miciocycle that rollaws is the last for bus cycle.
If the iIDY signal is not asserted by the end of the ctirrent micfueycle, the bus cycle will be
extended by one microcycle.
If a bus error occurs, externaI·togic resp<>nds by asserting.the EU signal..If·mul·is asserted
during a data read, the CPU ignores the data onDAL<31:00>,·extendsthe bus cycle by one
an microcycle, and initiates a niachlne ch~~k. If the EitR·signalis ~tetl dµr~ instruction
read with CS <2:tl~ ·..; 100, .the. CPU··.stpps. ·t>refetdling:. and. when the itist:ruction buffer is empty; the CPU will attempt to f~tch the nextinstructiori ·.~·~~ha data ~d cyqe., The mlR
signal takes precedence over thC'RDY signal; The as~ttitln ofeitlie:r RDV or the ERR signals
results in the completion of the current bus cycle. · .
· ·
7. The requested data is latched into the CPU and tile DS signal is deasserted.
8. The AS and DBE signals are deasserted to end tile. bus cycle.
CPU Write Cycle
The CPU uses a CPU write cycle to transfer Wormation to q:\emoi:y or .to an I/O. device..A CPU
write cycle, shown in Figwe 31, requires a minimum of 2 microcycles and may he extended for
slower memory or devices. . · .
.. ·
· -
ConfiQential and Propiietafy
1.37
MicroVAX 78032
CLKO
OAL~1:0IJ:.'
_"'-. __________/:
I
I I
SAMPi.JNG WINDOW
SAMPLING WINDOW
I
I
SAMPLING
WINDOW
Figure 31 · MicroVAX 78032 CPU Write Cycle Timing Sequence ·
The first microcycle of a CPU write operation is used to trans£er the address and control
information and the valid data is written during the second microcycle.
The sequence of events for a CPU write operation follows:
1. The physical (longword) address is driven onto DAL< 29:02 > and the memory operand length
is onto DAL<31:30> by the CPU.
.
2. The WR signal is asserted and CS <2:0> lines are asserted as required.
3. The BM< 3:0 > lines are asserted as required.
4. The AS signal is asserted to indicate that the address is valid and can be latched for demultiplexing and to qualify the CS<2:0> and BM<3:0> information.
5. The DBE signal is asserted and can be used to control the DAL bus transceivers.
6. The CPU drives data onto the DAL bus and asserts the DS signal to indicate that the data is valid.
7. If the data can be read during the next microcycle, the external logic asserts the RDY signal and the following microcycle is the last for this bus cycle. If the RDY signal is not asserted by the end of the current microcycle, the bus cycle will be extended by one microcyde.
If a bus error occurs, external logic responds by asserting the ERR signal and the CPU initiates a machine check. The ERR signal takes precedence over the RDY signal.
The assertion of either the RDY or ERR signals results in the completion of the current bus cycle.
1-38
Confidential and Proprietary
-
MicroVAX 18032
8. The DS sign,al is deasserted to indicate that the data will be removed from the DAL bus by the
CPU.
9.·The AS and DBE signals are deasserted to end the bus cycle.
Interrupt Acknowledge Cycle An interrupt acknowledge cycle is used to acknowledge an interrupt request from an 1/0 device,
and to read a vector. The structure of this cycle is the same as a CPU read cycle shown in Figure 30.
The first microcycle of an interrupt acknowledge cycle is used totransferthe interrupt prioritylevel (IPL) that is being acknowledged and the interrupt vector from the interrupting: device is latched
into the CPU during the last microcycle.
The sequence of events for an interrupt acknowledge cycle is as follows:
1. The CPU places the IPL of the interrupt being acknowledged on DAL<04:00>. DAL<29:05 >lines are zero and the DAL<31:30> lines are= 10.
2. Lines CS< 2:0 > are asserted to indicate an interrupt acknowledge cycle.
3. Lines BM< 3:0 > are all asserted and the WR signal is unasserted.
4. The AS signal is asserted to indicate that the IPL level on the DAL< 04:00 > lines is valid.
5. The DS is a.sserted to indicate that the bus can receive incoming data. The DBE signal is also asserted at this time and can be used to control the DAL bus transceivers.
6. If no error occurs, the· external logic responds by placing the interrupt vector on the DAL< 09:02 > lines the normal Q-bus processing flag on DAL< 00 > , and by asserting the RDY signal. The DAL< 15:10,01 > lines mustbe a high or low level in aceqrdance w,ith the setup
times specified in the timing diagrams.
7. If an error occurs, the external logic asserts the ~RR signal and the CPU cancels .the cycle and
ignores the data on the DAL bus.
·
8. The interrupt vector is latched into the CPU and the TIS signal is de~~erted.
9. The AS and DBE signals iire deasserted to en.d the l;>us cycle. .
DMACycle A DMA cycle shown in Figure 32, is used by the CPU to relinquish control of the DAL bus and
related control signals upon requesdro~ a DMA device or anot.h~ CPU.
The sequence of events for a DMA.cycle is
1. The DMA device requests use of the bus by asserting the QMR signal,
2. The CPU samples the DMR line for a DMA request during each microcycle unless the current bus
cycle is a read lock cycle.
3. The CPU causes theDAL<31:00>, AS, TIS, D}3E, \Xffi, B¥~3:0>,, a.00. CS<2:0> .lines to
become a high-impedance and asserts the 'f.5MG line to grant the DMA device use of the DAL
bus.
·
·
4. When the requesting device is finished using the bus, it deasserts the i5MR signal, and the CPU
takes control of the bus.
Confidential and Proprietary
1-39
MicroVAX 18032
I " I t4 ~
~ DMii
---\
ore
---\
0,..L<3l:oct·
----\
;;s
----\
OS
---\
ii1iE
----\ aM<J.O>, - - - \
Cfk1~,
----\
r-------~c:
Figure 32 ·MicroVAX 78032 DMA Cycle Timing Sequence
· External Processor Cycles
The CPU uses external processor cycles to communicate with external processors and external processor registers.
External Pmcessor Read Cycle The external processor read cycle shown in Figure 33 is used to transfer information from an external processor or external processor register to the CPU. An external processor read cycle requires one microcycle. The sequence of events for an external processor read cycle is:
1. The CS< 1:0 > lines are ~setted as required and the CS2 line is sustained at a high level.
2. The WR signal is not asserted for a read cycle. 3. The EPS signal is asserted to indicate that an external processor bus cycle is in process and to
qualify the CS< 2:0 > lines.
4. The external processor places the requested information on the DAL. 5. The requested information is latched into the CPU and the EPS line is deassei:ted. 6. The external processor removes its information from the DAL bus to end the bus cycle.
External Pmcessor Response Cycle The external processor response cycle shown in Figure 33 is used to transfer information and a completion or confirmation signal from an external processor or external processor register to the CPU. An external processor response cycle requires one microcycle.
.l-40
Confidential and Proprietary
Prelimm. acy.
MicroVAX l80~2
T4
I'. Tl .
CLKO
J\_
I
I
DAL<31:00>
--..--->---<-......,
,.
.,
.,
I.
~OATA~>-
j
I
I
I
I I
't
CS<1:0".>
cs 2
Figure 33 · MicroVAX 78032 External Processor Read/Response Cycle Timing Sequence
The sequence of events for an external processor response cycle is:
1. The cs< 1:0 > lines are asserted as required and the est~ i~'susajned at high level.
2. The WR signal is not asserted fo:r a read cycle.
.
.
3. The EPS signal is asserted to indicate that an external pmcessor bus cycle is in process and to
qualify the CS <2:0> lines.
·
4. The external processor places the requested information on the DAL bus and optionally drives the CS2 line low.
5. The requestedinfotmation is latched int0 the'CPU and the:E.PS signal is deasserted.
6. The external processor removes its information from the DAL bus and deasserts CS2, if asserted, to end the bus cycle.
Confidential and Proprietary
Preliminary
MicroVAX 78032
External Processor Write Cycle The external processor write cycle shown in Figure 34 is used to transfer information from the CPU
to an external processor or external processor register. An external processor write cyde requires one microcycle.
The sequence of events for an external processor write cycle is:
1. The CS< 1:0 > lines are asserted as required and the CS2 line is sustained at high level. 2. The WR signal is asserted.
.3. The EPS signal is asserted to indicate that an external processor bus cycle is in process and to qualify the CS< 2:0 > lines.
4. The CPU drives the information onto the DAL bus.
5. The EPS signal is deasserted and the external processor reads the infromation to the bus cycle.
MICROCYCLE
CLKO
--<____ DAL<31:00>
______.)------c(_ _DATA:.--->-
CS<2:0>
I
· I I
I
,..-~~~~~~~~~~~1
Figure 34 · MicroVAX 78032 External Processor Write Cycle Timing Sequence
· Memory Access Prorocol The 28-bit address provided by the MicroVAX 78032 on DAL< 29:02 > is a longword address that
uniquely identifies one of up to 268,435,456 32-bit memory locations. The chip provides four-byte masks, BM< 3:0 >, to select byte accesses within the 32-bit memory locations. No restrictions exist on data alignment. The data may start at any memory address except for the aligned operands of ADAWI instruction and the interlocked queue instructions. The memory consists of four parallel 8-bit banks, each of which receive the longword address on the DAL<29:02> lines in parallel. Each bank reads or writes one byte of the data bus (DAL<31:00> ), when its byte mask signal is asserted as shown in Figure 35.
1-42
Confidential and Proprietary
Preliminary
MicroVAX i8032
CPU read or write operations are grouped into one of the following categories-byte access, word access within a longword, word access across longwords, aligned longword acce$s, and unaligned longword access. Quadword accesses are treated as two successive longword accesses, with no
optimization. Byte accesses, word accesses within a longword, and aligned longword accesses
require one bus cycle. Unaligned longword aci:esses and word accesses that cross a longword
boundary require two bus cycles.
BBITS
..A:.
BBITS
~~
BBITS
8 BITS
....,..
T
:
I
DAL<29:02>-
: J-
OAL<31 ::M:>
DAL<23;16>
DAL <1.!i;OI>
DAL<07:00>
Figure 35 · MicroVAX 78032 Memory Organization
· External Processor Protocols
External processor protocols allow the MicroVAX 78032 to communicate efficiently with one or more external processors. Two external processor protocols exist-one for communicating with the optional floating-point unit and the second for communicating with processor register logic.
Floating-Point Unit Protocols The optional floating-point unit (FPU) is con.trolled by the CPU. When the CPU receives afloating-
point instruction, it passes the opcode and operands to the FPU for processing. The CPU waits for the FPU to complete the operation and then requests status information and the processing results. The FPU protocol is as follows:
1. Command transfer-The CPU performs an external processor write cycle to ttansmit a
command to the FPU. During this cycle, the CS< 1:0 > contains 00 indicating a FPU command
and the opcode of the floating-point instruction is placed on the DAL< 08:00 > lines.
2. Operand transfer-The VAX opcode determines the number and data type of operands to be transferred from the CPU to the FPU. The CPU performs one or more external processor write
cycles to transfer the operands. During these cycles, the CS< 1:0 > lines are equal to 01 (data
transfer), and the DAL<31:00> lines contain the data to be transferred.
Confidential and Proprietary
1-43
Preliminary
MicroVAX,78032
3. Operand processing-While the FPU .is processing the operands, the CPU checks to determine .where the operation is completed by executing ex~alprocessor response enable cycles.
4. Status transfer-When .the. FPU has finished processing the operands, it ·responds to the next ext.ernal processor response enable cycle by placing status information on the DAL<05:00>
lines and by driving the CS2 bus low. The CPU responds to the CS2 low signal by reading the
status information on the DAL< 05:00 > lines.
5. Result transfer-After reading the status code, the CPU may initiate one or more external processor read cycles to transfer the result operand(s). During these cycles, the CS< 1:0 > lines are equal to 01 (data transfer), and the DAL<31:00> lines contain the data to be transferred. The VAX opcode determines the number and data type of the operand(s) to be transferred from
the FPU to the CPU.
Register Protocols The external processor register protocol permits the external logic to implement processor register functions that are a part of the MicroVAX architecture but are not implemented in the hardware of the MicroVAX 78032. Refer to Table 16 for the processor registers implemented by the MicroVAX 78032. The following CPU protocols are used with a move from processor register (MFPR) or move to processor register (MTPR) instruction to access a register not contained in the CPU.
Read from processor register-The read from processor sequence is shown in Figure 36. This
sequence is performed when an MFPR instruction is used to read data from processor registers 25
through 39, 48 through 55, or 59 through 61. The protocol is as follows:
I
1. The CPU initiates an external processor write cycle to specify the register number. During this cycle, the CS< 1:0 > lines equal 10 to indicate to a non-FPU command, the DAL< 31 > lines equal 1 (read register), and the DAL<05:00> lines contain the register number specified by the MFPR instruction.
2. The CPU waits one cycle and then executes an external processor response cycle to read
the register data. If the CS2 line is driven low by the external logic, the data on the DAL<31:00> lines is the result of the MFPR instruction. If the CS2 line is high, the CPU returns zero as the result.
I ,,
m ' I I
WO~
i - I
I
:·I
1
-·., ~
~(«<1'.{(~{(<l(<q;«UJ>»J~>»»»>:t>~>~)>»~,__------.C
I
'--~~~~~~--:!.
.
'
I
I
~ CS<'>
1-1= ~%«<1<<1««<«<{~(<{))>J~J)»J$- \-----
UiHP.NAI. i"fl'.OC~SSQR NON·~f'll
I
COMl·O·/.ID (:'f(:U
IVl).0~ ,'
EICT&FOof·U 1"k0CES$0P 11£,t,Dlkl:SP(l~ cvcv
I
Figure 36 ·MicroVAX 78032 Read from Processor Register Timing Sequence
1-44
Confidential and Proprietary
-·.··
Preliminary
MicroVAX780J2
Write to processor tegjster.....The write to processor register sequence is shown in Figure 37. This sequence is performed when an MTPR instruction is used to write data to.processor registers 25 through 39, 48through 55, or 59 through 61. The protocol is as follows:
1. The CPU initiates an external processor write cycle to specify the register number. During this
cycle, the CS< 1:0> lines equal 10 indicating a non-FPU command, the DAL31 lines equal
0 (write register), and the DAL<0'.>:00> lines contain the register number specified by the MTPR instruction.
2. The CPU executes an external processor write cycle to writetheregister data. During ~cycle, the CS< l:O>linesequal01 (write data), and theDAL<3l:OO:> linescontainthedataspecified in the MTPR instruction.
3. The next cycle is not an external processor cycle.
MICROCYCLE
MfCROCYCLE
Tl
T2
T3
T4
Tl
CLKO
>-- I
OAL<l1;XJ> ~Il----------(:e;,!!,':~NUMBER)l----------1( WAITEOATA
I
Wna m I
""'
I
I
I
I
: . /Hi "--------'/_.:---I
I
. I
:
I
I
CS<1:0>
CS<2>
I
~ I
I
EXTERNAL PROCESSOR NON·FPU COMMAND CYCLE
E.XTEflNAL PROCESSOR WRITE CYCL£
Figure 37 ·MicroVAX 78032 Write to Processor Register Timing Sequence
de Eleet:rie,.I Characteristics The de electricafcharacteristics of the MicroVAX 78032 for the operating voltage and temperature ranges specified are listed in Table 17.
Confidential. and Proprietary
1-45
IJBDll
Preliminary
MicroVAX 78032
Table17 · MicroVAX 78032 de Input and Output Parameters
Parameter
High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Symbol
\{H
\{L VoH
VoL
Requirements min max 2.0
0.8 2.4
0.4
Units
v v
v
v
Test Condition
loH = -400 µA
loL = 2.0 rnA
High-level output voltage (EPS only)
Vomi
2.6
v
loH = -lQQ µA
Low-level output
voltage (EPS only)
VOLi!
0.2
v
lot = 1.0 rnA
Input leakage
current (CS2)1
I1LS
Input leakage current
IIL
3.2
mA
\{N = 0.4 V
-10 10
µA
0.4 < ~ < VDD
Output leakage current
IoL
-10 10
µA
0.4 < ~N < Vnn
Active supply current
Inn
700
mA
louT = 0, 't. = OC
Input capacitance
CIN
8.0
pF
Output capacitance
CouT
8.0
pF
Note: 'When CS2 is sustained high by the CPU the maximum sustainer current (11L) is 3.2 rnA.
ac Electrical Characteristics The input and output signal timing parameters for the MicroVAX 78032 is shown in Figures 38 through43.
The following notes apply to Figures 38 through 42 and their associated timing tables.
1. Formulas for the timing parameters are stated in terms of the CLKI period. CLKI
period= tar= P. 2. All times are in nanoseconds except where noted.
3. The ac characteristics are measured with a purely capacitive load of 100 pF. Times are valid for loads of up to 100 pF on all pins.
4. achighlevels are measured at 2.0 volts and aclow levels at 0.8 volts except for the BPS and TEST
signals. 5. An ac high level for the EPS and TEST signals are measured at2.2 volts and an ac low level at 0.6
volts.
6. S =the number of microcycles slipped during a bus cycle.
7. The sampling window is used to sample the following asynchronous signals: RDY, ERR, and DMR. The RDY and ERR signals are qualified when AS is asserted. The DMR signal is qualified by the AS signal being deasserted. The effect of these signals on the current bus cycle is as follows:
1-46
Confidential and Proprietary
Preliminary
MicroVAX 7W2
· The bus cycle will conclude at the end of the current mkrocycle if the RDY signal is asserted. and
the BAA signal is not asserted throughout the sampling window while the AS sigMI is asserted.
· If the ERR signal is asserted throughout the sampling window while the AS signal is asserted, the current microcycle becomes an extension cycle and the bus cycle ends after the .next microcycle.
· If the RDY or ERR signals go through a transl~.during the S4.lmpling wine.low while .the AS signal is asserted, the result is indeterminate,
· The DMR signal is sampled at every microcycle boundary.
· If the DMR signal is asserted throughout the sampling window and the AS signal is not asserted, and the CPU has not locked the bus, the next microcycle will be the beginning of a DMA cycle.
$'e . I?MA. · The first microcycle 11fter the end of the. current bl:'s cycle 'YPl pegin a
cycle if ~
signal is asserted throughout the sampling wfudow, the A'.S sigruµ is a~serted, and the CPUhas not
locked the bus.
.. · · · .·
· . ..
· .
· A DMA cycle concludes at the end of the current microcycle if the DMR signal, is deasserted
throughout the sampling window.
8. There are no internal pull-up circuits on theIRQ<J:O>, NfµiL, INTTIM, and HACT lines.
· Specifications The mechanical, electrical, and environmentaldlaracteristfos and specifications for the MicroVAX
78032 are described in the following paragraphs. The test conditions for the dectrical values are as follows unless specified otherwise. · Operating temperature (T...): 70°C · Ground reference (Vss): 0 V · Supply voltage (V00): 4. 75 V
Mechanical Coniiguration The physical dimensions of ~he MicroVAX 7803.2 68-pin cerquad package are contained in
AppendixE.
Absolute Maximum Ratings Stresses greater tl18n the absolute maximum rating5 may ¢ause. ~rmanent damage to the deviee. Exposure to the absolute maximum ratings for extended' periods may adversely affect the rdiability of the device. · Supply voltage (V00): -0.5 V to 7.0 V · Input or output voltage applied: -0.5 V to 7.0 V · Active temperature (T,J: 0°C to 70°C · Storage temperature ('I;): -55°C to 125°C · Power dissipation: 3.5 watts (maximum)
Confidential and .Proprietary
1-47
.... , ..
Preliminary
~omrnencfed Operating COnditions
· Supplyvoltage(Vou): 4.75Vto·5.25 V · Active supply cu~nt: (loo): 700 mA (maximum) · Tutnperafure (TA): 0°C to 60°C · Relative humidity: 10% to 95% (noncondensing)
· Minimum airflow over chip: 250 linear feet/minute
Clock Input Tuning
Figure:38 shows the timing specifications for the CLKI input clock signal andTable 18 lists the timing parameters indicated on the diagram. ·
rc1F
tc1L
Figure 38 · MicroVAX 78032 CLKl Timing Waveform
Timing Symbol
tclF
l:c1H
tc!L
tcIP tcra
Table 18 · MicroVAX 78032 CLKI Timing Parameters
Signal Definition
Requirements (ns)
min
max
Clock in fall time
4.5
Clock in high
8
Clock in low
8
Clock period
25
50
Clock in rise time
4.5
Confidential and Proprietary
Preliminary
CPU Read and Write Cycle Timing Figure 39 ·shows the timing sequence for the CPU read cycle and Figure 40 shows the timing
are sequence for the CPU write cycle. The parameters for the CPU read arid write cycles listed in
Table 19.
C!..KO
DAL<31:00>
CS<2:0>
Figure 39 · MicroVAX 78032 CPU Read Cycle Timing Sequence
SAMPLING WINDOW
Confidentml artEJ Propri~
-
Preliminary
MicroVAX 78032
Figure 40 · MicroVAX 78032 CPU Write Cycle Timing Sequence Confidential and Proprietary
-
MicroVAX 78DJZ
'liahle· 19 ~ MicroVAX 780l2 CPU arid Wri1e Cycle Patameten
Tuning Signal Defiaition Symbol
Requirements (as) ·
min
max
Address set up time to AS assertion
2P-28
Address hold time after AS assertion
tAmc As rising through 2.0 v to CLKO rising througho:sv P.i..'2J.
tASLC AS falling through 0.8 v to
CLKO rising through 0.8 V
P-20
AS·assertion to DBE and D'S (read) assertion
JP-15
.3P+20
tASnso
AS as!iertion to readdatavalid1 AS assertion to D'S assertion (write)
1.l,P-.30+8PS .5P+20
AS and DBE deassertion to data three-state t&mw AS deassertion Width tASLw AS assertigµ width
2P-20
JP . 121?:..1.5 +SJ?S
tASwa AS assertion to beginning of
R:DY, ERR, and DMR sampling window2
(6P.,.45) +BPS
tASwe AS assertion to end of ID5Y,
'ERR, and i5MR sampling window3
tASWll WR, BM< 3:0 >' cs <2:0> hold
time f;c,om AS deassertigµ
6P+10+8Ps ·P-20
.2P-25
tum CLKO rising through 2.0 Vto AS rising thro~ 0.8 \T P-7
P+15
tcASL CLKO rising through 2.0 V to AS falling through 2.0 V P-9
P+16
tco1
CLKO rising through 2.0 V to read data valid
P-5
tcoo Write data hold time from CLKO rising through 2.0 V P-15
tcr
CLKO fall time
12.5
trn
CLKO high
(2P-25) x .5
l:ct
CLKO low
(2P-25) x .5
ta
CLKO period
50
100
tea
CLKO rise time
12.5
tcw8 T4 CLKO rising through 2.0 V to beginning of RDY, ERR, and DMR sampling window2
.3P-45
l:cwE T4 CLKO rising through 0.8 V to end of RDY, ERR, and DMR sampling window3
.3P+ 15
1-51
Table 19 · MicroVAX i80:J2 'CPUand Write Gyde Parameters(Cont.)
Timing Signal Definition Symbol
Requirements (ns)
min
max
tDBLW tooc toons tDSAS tusu
DBE assertion width Write data set-up time to CLKO rising through 0.8 V
Write data set-up time to 00assertion DS deassertion to AS and DBE deassertion Read data hold time after l'.5S deassertion
9P-20+8PS .3P-42 .3P-30 P-15 0
tusm DS assertion to read data valid'
8P-35+8PS
tusoo tusoz tnsHW tusLWl
Write data hold time from DS deassertion
DS deassertion to read data high impedence D'S deassertion width DS assertion width (read)
3P-20
6P 8P-20+8PS
3p:20
tnsuvo twEDI
DS assertion width (write) Sampling window end to read data valid
6P-20+8PS 5P-25
twRAS
WR, CS< 2:0 >·set up time before AS assertion
3P-35
Notes:
' Read data is valid early enough if t,..801 or tusm or tcm is satisfied.
1 Requirements for the beginning of the sampling window are satisfied if either t.\swn or tcwn is satisfied.
3 Requirements for the end of the sampling window are satisfied if either tAswE or tcwE is satisfied.
1-52
Confidential and Proprietary
-
MicroVAx: 7$0l2
Ditect Memory ~ss CyclerlDling Figure 41 shows the timing ~uence for direct memory acces& (DMA) transfers and Table 20 lists
the timing parameters for the symbols referenced on the diagram. ·
,,,
l T4
T\
""" ~'oM·Gl'DMGRU
---\
OiiG
OAL<l1:00>
lS tnsz
iiS
DiE
iiii<3:i>.
QK2~
---\
Figure 41 · DMA Timing Seq~e
1-53
MicroVAX 78032
Timing
Symbol
Table 20 ~ ~croVAX 78032 DMA CycJ~ TOJ:ling Parametets ,,
'
,,,
'
'
;
'
'
"
'
i
Signal Definition
Requirements (ns)
min
max
tAsc
AS and DBE deassertion to DMG assertion
troH CLKO rising through 2.0 V to DMG rising th.rough 0.8 V
tcGL
CL.KO rising through 2.0 V to
DMG falling through 2.0v
4P-25 P-7
P-7
P+16 P+18
toMKG DMR to DMG latency
10P~25
60P + 20+16PS
toMacu DMR to DMG latency with bus unlocked
lOP-25
28P+20+8PS
toMllJt DMR hold with respect to
0
DMG assertion
tcoALZ DMG deassertion to external device three-state of DALS.
4P-20
tcoMit
DMG assertion to i5MR deassertion
such that no more DMA cycles are
requested
6P-45+ ((N-2) x 8P)1
!cHc DMG rising th.rough 2.0 V to CL.KO rising through 0.8 V
P-25
tGLC DMG falling through 0.8 V to CL.KO rising th.rough 0.8 V
P-23
tcLw DMG minimum assertion width
lOP-25+ ((N-2) x 8P)1
tcsz
DMG assertion to three-state
of AS, 'BS, i5iIB, WR. CS<2:0>
andBM <3:0>
-10
0
DMG deassertion to external device of three-state of AS, DS, DBE, WR,CS<2:0> <3:0>andBM <3:0>
3P-202
Notes: ' The number of microcyles that occur during a DMA grant. A DMA grant is issued for a minimum
of two microcycles. 2 At the conclusion of a DMA grant the external logic must deassert the AS, DS, and DBE signals
before the external bus drivers become a high impedance.
External Processor Cycle Timing Figure 42 shows the timing sequence for the external processor read and response timing and for the external processor write command timing. Table 21 lists the timing parameters for the symbols
referenced on the diagrams.
1-54
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CLKO· DAL<31:00>
CS<1:0>
MicroVAX.78032
CLKO
DAL<31:00>
Cs<2:Cl>
External Processor Write/Command Timing
Figure 42 · MicroVAX 78032 External Processor Cycle Timing Sequence
Confidential andfroprietary
. 1-55
-------------------------------··--··
MicroVAX 78032
. Table 21 · MicroVAX 78032 External Processor Cycl~ Timing Parameters
Tmting Signal DefinitioQ Symbol
Requirements Min. Max.
tcEP
CLKO falling through 0.8 V to EPS falling through 2.2 V
P-5 P+19
tooEPH tEPCSL tEPCSZ
Write data valid set up time to EPS deassertion
EPS assertion to eXternal processor assertion of CS< 2 > EPS deassertion to CS < 2 > three-stated by external processor
2P-35
0
3P-40
0
2P-20
tEPDl EPS assertion to read data valid
4P-40
tEPF
EPS fall time from 2.2 V to 0.6 V
0
10
tEPHOO Write data hold time from EPS deassertion
2P-25
tEPLC EPS falling through 0.6 V to CLKO falling through 2.0 V
P-25
tEPLWI EPS assertion width (read)
4P-20 4P+20
tEPL'\110 EPS assertion width (write)
5P-20 5P+20
tEPWJl WR and CS< 1:0 > hold time from EPS deassertion
P-20
tEPZ
EPS deassertion to read data three-state
tWJIEP WR and CS< 1:0 >. set up time beforeEi5!> assertion.
3P-20 2P-35
Reset Tuning
Figure 43 shows the timing sequence for the reset function of the processor and Table.22 lists the timing parameters for the symbols referenced on the diagram.
Figure 43 ·MicroVAX 78032Reset Timing Sequence
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MicroVAX 78032
18ble 22 · MicroVAX 78032 Reset Tuning Parameters
Tuning Signal Definition Symbol
Requirements (ns)
min
max
tRBs
RESET deassertion to first CL.KO pulse if RESET
is deasserted synchronously
3P+10 3P+85
taEsc Number of CL.KO periods from RESET deassertion until first DAL activity
32 periods
tREscn
taEsa tREsw
tRESWII
RESET assertion to DMG, EPS deassertion1
RESET assertion to AS, DS', IIBE, WR deassertion3 RESET assertion width after VDll = 4.75 V
RESET assertion width if VDll has already been at 4.75 V for 3 ms when RESET is asserted
3.0ms 3.0µs
150 1.0 µs
tal!S2! RESET assertion to DAL<31:00>, :BM<3:0>,
100
CS<2:0> .highimpedence'
Notes:
1 When the RESET level is asserted, the DMG and EPS signals become high and remain high.
2 When RESET is asserted, AS, DS', IIBE and f t outputs become a high impedance state and the
levels become high by low current internal pull-ups.
~When the mET level is asserted the BM<3:0> lines and CS<2:0> lines become high-
impedance.
· Mechanical Specl6cations
The dimensions of the MicroVAX 78032 68-pin cerquad surface and socket mount packages are shown Appendix E.
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1-57 ---------·-----------
· High performance -Accelerates by 50 times the execution of MicroVAX floating-point instructions
-Accelerates by two times the execution of MicroVAX integer multiply and divide
· Subset (70 instructions) of the VAX floating-point instruction set'
· Operates with standard VAX integer data t}Tpes · ·'
-byte, we.rd, longW<Jrd, and quadwortt
· Operates with standard VAX floating-point data types
-single-precision (F_floating) -double-precision (D_floatiµg) -extended range double-precision (G_flollting)
· Arithmetic error checki11&and reporting
· High-speed ZMOS technology
· Single 5 Vde power supply
· Description
The MicroVAX 78132Floating-Point Unit (FPU), contained in a ~-pin cerquadpackage, is a high-
performance cooperative processor that extends the data paths of the MicroVAX 78032 central
processing unit (CPU). Its primary functiot1 ·is to exeeute MicroVAX floating-point instructions to
eliminate the emulation of floating-pomt iristrUCfions in software. Figure 1 is a general block
diagram of the MicroVAX 78132 FPU.
''
..
EXPONENT OATA PATH
MULTlf>LEXER
FRACTION FRACTION DATA M'fH CONTIWL
13 MAIN SEQUENCER 121JOX35J
CS2 CS1 cso WA EPS
Figure 1 ·MicroVAX 78132 General Block Diagram
Conf~dellti1ll ~nd Proprietary
1-59
>§Fi' __ ll!IL11Ulll! _ ""llm'1l~z:"'"'
_.....,..._..-----·-~-............................,...,._ _ _~-----------
··~··
!he Mi~VAX FPU handles the FJloating (single-ptecision), D_floating (double-precision), ~d
G_floating (extended range double-precision) VAX floating-point data types. It supports several VAX floating-point operations, including floating-point add, subtract, multiply, divide, .and convert. The MicroVAX FPU also accelerates the execution of integer multiply and divide operations. The FPU supports sign~d integer ~ultiply and unsign~d integer divide operations.
· Pin and Signal Descriptions
This section provides a brief description of the input and m1tput signals and power and ground connections of the MicroVAX 78132 68-pin package. The pin assignments are identified in Figure 2 and the signals are summarized in Table 1.
DALOO ·CS2 cso EPs vss NC vcc vcc NC
NC CS1 Wii vss NC NC vcc VBB
DAL01 DAL02 OAL03
DAL04 DA LOS DAL06
OAL07
vcc vss vss
OALDB OAL09 OALlD DAL11 DAL12 OAL13 OAL14.
60 59 58 57 56 55 54 53 62 51 50 49 48 47 46 45 44
61
43
62
42
63 r------------, 41
64
I
65
I
66
40
I
39
I
I
311
61
I
37
68
MicroVAX 78132 FLOATING-POINT UNIT
L
36
(FPUI
I
35
2
I
34
3
I
33
4
I
32
5
I
6
I
31
I
30
'L - - - - - - - - - - - _J
29
8
28
9
27
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 26
vcc vcc NC vss NC NC vss DAL16 DAL16 vcc CLKI RESET vss NC NC vss DAL17
Figure 2 ·MicroVAX 78132 Pin Assignments
OAl.31 DAl30 DAL29 OAL28 DAL27 DAL26 DAL25 DAL24
VCC
vss vss.
DAL23 DAL22 DAL21 DAL20 DALIS DAL18
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-·
Preliminary .
MicroVAX 7852
,lable 1·MicroVAX78132 ~and Signal S~,
43-36, 32-25, 10-3, 67-61
57-56
'DAL<31:00> CS<l:O:>
58
CS2
55
54
16
14
CLKI
45
V1111
11-13,46-48, Vee 35,68
1,2,17,18, Vss 23,24,33,34, 52,53
15,19-22, NC 44,49-51,59
input/output Data/address lines-'Itansfers data, status, and
control information between the FPU and'CPU.
input
output
input
input
input input output
,.. ,
input input
Control stat~; <l:O > ~Indk:rteS the type of
· information ~ingtransferred to orfroni the PPU
(commarid$,·:dalt; or response enable). Valid
when EPS is asserted.
the Con~J.Vl stat!Js 2--A~~ qutil\g.an extern.al
processor ~ppnse. ·.~!)able b~s. cyCle ·. wh~n.
FNJ has cq~~~~e ~o~~q~ ()pt;ration. Wri.te.:.;....Iripilt from the MicroVAKCPU thafindi'.cates ·~ta fll:!W> ditection. ·~n ,as.setted,; cjndi~ cat:es·flmiJromdl~·CPU to the FPU. Valid .. when.mil.~~if.
Bxternal p~t stroqe ,Asserted· by the
MicroVAX' CPiJ to qualify aU. commuriication
between the FPU and CPU.
Reset--Asserted by external logic to resyndm:>~.~~ FPViwith.the CPU. Clock ita.plii,~J:4asi!; i;i9ck timing input. to' the FPU. Has the ~ame'£%equency as the MicroV~ CPU clock~CLKI)input.
BaCk-biasvoltage.
VOita'.ge-Powet! supply de voltage
GroundLCo:mrnon ground ref.f!rence
No connection-All unused pins should be left
~oaring
.-· -
and not pull~
··: '' .:-,\ _y::, ' -
up
.__ ;-
or,-,,g,_rp>t;µ..:l--<d"' ._e, d.
Data and Address Bus Data. and address bus (DAL< 31:00 >)-The data and address bus is a time-multip~sf bidirec-
tional bu,s that transfel'S address, data, status, and control ~nformation between the. FpU,~Jhe cyu. The MicroVAX CPU is always the bus master and communicates with the FPU ·according to
the protocol outlined in the "CPU/FPU General Protocol" discussion.
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,._.,_!'"""-_1.i!___,_, _ _ _ .$.1..l.'l.P.._ _ _ ,,_.,_ _ _
PHl_llffl.wl_R_Hll_ _ _,._U_!D-llli_il!I_,,...,,.......,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.,_,_,_.__... _,;
-
MicroVAX 78ll2
m to Bus Control
E:x:ternal processor strobe (EPs)-the
si~al iil used Wtfate 'all CPU/FPUbus cycles that are
external processor bus cycles. ft indicates to the FPU thatthe information on the CS< 1:0 > and
WR lines is valid. Refer to the "Bus Cycles Description" discussion for more information on CPU/
FPU bus cycles.
For reset operations, the FPU uses the first assertion of the EPS cycle following the assertion of the RESET signal to synchronize itself with the CPU.
Write (WR)-The WR signal is an input from the MicroVAX CPU that specifies the direction of
data flow between the CPU and FPU on the DAL<31:00> lines. When WR is asserted, data is
being transferred from the CPU to the FPU.
System Control Reset (RESi.IT)-External logic asserts the RESET signal to synchronize the FPU and the MicroVAX CPlJ. The assertion of RESET causes the CPU to perform a number of EPS cycles. The first external processor (EPS} cycle synchronizes the FPU and CPU. The remaining EPS cycles are used to verify the presence of the FPU in the system.
Control Status (CS< 2 :0 > )-The CS lines provide status information about the current bus cycle.
The CS< 1:0> lines are inputs to the FPU that specify the type of information being transferred. CS< 1:0 > are valid inputs only when the EPS signal is asserted. The WR signal further qualifies the type of bus cycle, as summarized in Table 2. Refer to the "Bus Cycle Descriptions" section for more information on the types of bus cycles.
CS line
1
0
0
0
0
0
0
1
1
0
1
1
1.8.ble 2 · MicroVAX 78132 Bus Cycle Types Write(Wi) Bus Cycle Type
0
External processor command write
1
External processor data read
0
External processor data write
0
Non-FPU command write
1
External processor response enable
CS2 is an open-drain output that is asserted when the current bus cycle is an external processor response enable cycle and the FPU.gas completed the current commanded operation.
OoekSignal
Oock In (CLKI)-This signal is the basic timing input provided to both the FPU and CPU from an
external clock Source.
.
Confidential and Proprietary
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Power Supply Connections Power (Vbc>....:.Tuese inputs are used tO supply 5 Vde power to the FPU. G~ (V;.8)-The~ inputs are used as a ground reference for the chip.
to Back-Bias Generator (V88)-This is a ~ck-bias voltage that is either bypassed ground with a
capacitor (typically 0.01 µF) or attached to a back-bias supply (typically -2.5 volt ± 10% at 10 mA).
· Architecture Summary
The MicroVAX 78132 FPU architecture, shown in Figure 3, consists of three separate processors-a
1-bit sign processor, a 13-bit <:JC~aj:9tJ1mc~r·. ~f!~a ?7-~lFJ~<:tipp, ~1;9Cessof. The extfu bits in the fraction data path acconunOdate ex~ precision ins,~io~ Such as EMO:OX. A lllicro-
sequencer containing 200 35-bit control words~COn.trtJh'i&~fioobf the three p~ssors/Data
enters and leaves the FPUJhrou~ ~ ~/Qbl;lf.£~ .Gonttolfufo~on passes to andfrol'll the FPU
through the interface control·logic.
are The following paragraphs descrille FPUarchitecture accessib~to the user.
Qr T I CL«YS '
" "
tNSTMuttlON
"'""""
Figure 3 ·MicroVAX 78132 Detailed Block Diagram
Confidentiithmd·.Proprietary
1.:.6:3
Preliminary
MicroVAX7i.32
Visible State The MicroVAX FPU does not contaip user-accessible interpal~gisters.or modebits. The M;ictoVAX .·
CPU contains the floating-point general registers al)d oon,dition codes. Commands sent from the
CPU to the FPU determine the operational modes (round or truncate) and the data types (for
example, F_floating or D.Jloating).
· ·
Exception Detection and Reporting Table 3 lists the exceptions that the MicroVAX FPU detects and reports.
Table 3 ·MicroVAX 781.32 Reported Exceptions
Condition
Result Returned to CPU
Reserved operand
UnpredictabJe;......cCPU unconditionally faults
Integer overflow
Low order 8, 16, or 32 bits of the true'result
Floating overflow
Unpredictable-CPU unconditionally faults
Floating underflow
Floating zero
Floating divide by zero
Original quotient
Unimplemented instruction . Qnpredictable-"comrnand not valid" exception
The exceptions associated with specific MicroVAX FPU instructions are described in the following paragraphs:
Data Types , .
. ,
The MicroVAX FPU handles seven data types-byte, word, longword, quadword, F_floating,
D_floating, and G_floating. Figure 4 illustrates the data type formats. For a summary of the data
types associated with specific MicroVAX FPU instructions, refer to appropriate instruction
discussions that follow.
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!lli.
BYTE
WORD
W!!il!:!. ~
8BITS
SIGNED()(! UNSIGNED INTEGER
16BITS
SIGNED DR UNSIGNED INTEGER
07
ob
r.____________o.o.I. :A
LONGWORD QUADWORD
-3~BIT~ 64 BITS
S)GNEl)QR ONSIG-NEC> INT~GER
SIGNED OR UNSIGNEO lNTeGER
----l: It--'.":-_._ ___._··.-.->·-;,.--
'· 32
F _FLOATING
3'2lllTS- F,LQATI~. POINT
:A :A+2
O_FLOATING 64e1rs FLOATING l>OIN'T
G_FLOAJll>IG
64BITS
F_LOATJ!l~pelNT
63
Figure 4 · MicroVAX 78112 Dl!lf4 Types
J..65
i
,- '
MicroVAX7&W
· MicroVAX 78132 FPU Instruction Set
The MicroVAX 78132 FPU instruction set consists of floating-point instructions, integer multiplication instructions, and integer division instructions. Refet to Appendix A for a summary listing of the FPU instruction set.
Floating-Point Instructions The FPU opcode is a nine-bit code for an FPU instruction derived from the opcode of the original instruction fetched by the MicroVAX CPU. The opcode for a G.Jloating instruction is the original instruction preeeded by a l. The opcode for an instruction that is not of extended range (G.Jloating) is the originalinstruction preceded by a 0.
The MOV, MNEG, and TST floating-point instructions are marked with an asterisk to indicate that they are implemented entirely within the MicroVAX CPU. In a system without an FPU, the CPU performsa reserved operand fault if an attempt is made to execute these instructions.
The MicroVAX FPU treats a two-operand instruction the same way it treats the corresponding three-operand instruction. The MicroVAX CPU handles the differences in processing these instructions.
The POLY instruction is implemented as a continuous, interruptible instruction. The MicroVAX FPU assists the CPU by performing floating-point addition and multiplication operations. After each step of the polynomial calculation, an intermediate result is returned to the MicroVAX CPU and a new coefficient is passed to the FPU. (No new command is issued to process this coefficient during normal operation.) A new intermediate result is then computed. If the CPU is interrupted, it can restart the POLY instruction by reissuing the POLY command and sending the most recent intermediate result, the argument, and the current coefficient.
Integer Multiplication Instructions The MicroVAX FPU can perform signed integer multiplication. The MicroVAX CPU uses this capability to accelerate the execution speed of the following instructions. Refer to Appendix A for the format and exceptions of the signed integer instructions executed by the MicroVAX FPU.
Opcode
7A
OA
C4
C5
Instruction EMUL {Extended multiply) INDEX (Index calculation) MULL2 (Multiply long 2-operand MULL3 (Multiply long 3-operand)
During MicroVAX FPU integer multiplication
· The FPU performs a 32 by 32-bit signed multiplication.
· The FPU in all cases returns a 64-bit result.
· The exception code is zero and the condition codes are unpredictable.
Integer Division Instructions The MicroVAX FPU can perform unsigned integer division. The MicroVAX CPU uses this capability to accelerate the execution speed of the following instructions. Refer to Appendix A for the format and exceptions of the unsigned integer division instructions executed by the MicroVAX CPU.
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Opcode C6 C7 7B
Jnstmction DIVL2 {Divide long 3-operand) DIVL3 (Divide long 3-operand) EDiv (Extended divide)
During MicroVAX FPU integer division·,
· A 64-bit dividend is divided by a 32-bit divisoi
· the operands are unsigned.
· The operands are guaranteed not to cause an integer overflow.,fFhe MicroVAX CPU checks this condition before activating the FPU.)
· The FPUreturns a 32-bit result anda J2,bfr remainder. . · The exception code is zero and the condition &des~ unp~ble..,·
· Interfacing Requirements
The MicroVAX 78132 FPU is designed. as a coproce$sor for th~ Midov.Ax 780J2 CPU. Therefore, all interfacing considetatio~ ~· macie witl;i ~t to .t}ua:..~rqVM .c~., The. JiPU/<;;:Pl.l
interface-indqding b11$ cydes, the FPUJC\PU Jil+'P~l; ~.a ty,pical f PU/CPU interoonnecti9n scheme-is described in the following ~hs;
Bus Cyde Descriptions
The MicroVAX FPU recognizes five types of bu~ ~~ ·¢i~t:Atil pn'.)C~sor com.tpa:l'ld write,
external processor data read, external processordata wnte; rioo·F:$Jceoit)mand writei and.external
processor response enable. The following paragraphs briefly describe these bus cycles. Refeft<l the
"MicroVAX 78032 32-bit.Central ~ilf:·lJ~it" ~fi?.!;l !o~ the corre:iponding MkroVA~ CPU
bus cycles. Figures 9 andlO are deilJiled bus~cYcieJllagroms; ···
··· · ·
an External Processor Command Write-An external processor command write. cycle is performed
when the CPU has a commarid (typically instruction o~e) for ~he FPB;~;teadMd ~xecute.
This type of cycle lasts four··clock(CLKOYPeriods oronemiCiocyde.Tl"iesequen~&f events is .
· The CPU drives cycle-status information ol1 Ifues CS~:i:p,;;1° '(Cs·~}.:O>;;,..pp_.fqr,,th~ty,pe of cycle), drives the cqmmand on theDAL<31:00> bus~ and asse,~iq:\ie ~l.5S an~'Witsignals.
· The FPU reads the opcode on the DAL.
· The CPU deasserts th~ BPS and \ft signals, and' the cyde ends? ·'
External processordouead-An C}(temal p~$.11Qr d~ta ~ ~te i§ ~OJ'i~ed when the FPU has data for the CPI:J to process. This t:ypeofcyde·lallts fcml:' .~peric4s, the seq~e 0£events.is.
· The CPU drives cycle-status information on lines CS< 1:0> (CS< 1:0> =01 for this type of cycle) and asserts the Ei5S signal. The WR signal is not asserted because this is not a write cycle.
· The FPU responds by driving the PAL< 31:00> bus wit;hdat~.
· The CPU reads the data.
· The CPU deasserts the EPS signal, and the cycle ends.
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Preliminary
External processor data write-An external processor data write cycle is performed when the CPU has data to write to the FPU. This type of cycle lasts £01.it·dotk periQd.s. The sequence of events is
·The CPU drives cycle-status information on lines cs<:t:O:> (CS<: 1:6:> =01 for this type of
cycle) and asserts the EPS and WR signals.
·
· The CPU drives the data on the DAL< 31:00> bus and deasserts th~'EPS and WR lines.
· The FPU responds to the deassertion of the EPS signal by reading the data on the DAL< 31:00 > bus, and the cycle ends.
N'on-FPU command write-A non-FPU command write cycle is perform,ed when the CPU has an
instruction or command for a processing unit other than the FPU. The sequence of events is
· The CPU drives cycle-status information on lines CS< 1:0 > (CS< 1:0>=10 for this type of cycle) and asserts the EPS and WR signals.
· The FPU initializes itself, suspends its operation, and disables its outputs so that it cannot respond to an external processor data read cycle or an external processor response enable cyde until an external processor command write cycle for the FPU has been initiated.
External processor iesportse enable-An external processor response enable cycle is performed
when the CPU is ready t:oaccept the result of :Someoperationfrom the CPU. The sequence of events is
· The CPU drives cycle-status information on lines CS< 1:0 > (CS< 1:0 > = 11 for this type of
cycle), asserts the EPS signal, and puts the CS2 line in the high-impedance state. T}:ie WR signal is
not asserted 1'ecause this is not a write cycle.
·
·
·
· When die FPU completesits current instruction, it drives status information on the DALbus and pulls line CS2 low.
· The CPU reads the information and deasserts the EPS ~ignal to end the cycle.
CPU/FPU.General Protocol
The communicaP,on protocol between the CPU and the FPU is grouped into Jive categories-
command transfer, operand transfer, operand processing, status transfer, and result transfer. The
following paragraphs describe each transfer. ·
.
.
Command transfer-The CPU initiates an interaction with the FPU by performing an external
processor command write cycle. The CPU drives a command (an instruction opcode) on the DAL·
bus, drives a status code on lines CS< 1:0 > , and asserts the BPS andWR signals.
Although the DAL<.31:00> bus is driven with a command (in this case an instruction opcode)
during the external processor command wri.te cyde, only DAL< 08:00 > is significant to the FPU.
Figure 5 shows the FPU command format and Tu.hie 4 describes the bit functions.
31
·· . . . . . .
0908
. 00
I:::::'. ::'. ::::::::'. :'. :'. I::?++, ;:I
Figure 5 ·MicroVAX 18132.Command Format
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Preliminary ...·.·..
DAL Line <31:09> <08:00>
Description
Not used Contahis the opcode of the in~trtiction that the FPU is th execute. or assist in executing.
Operand transfer-The instru~ion opcode specifies the operat~on(s) to be ~!'for~ by the FPU
and the number and data type of operands inVolved. The CPU f~tch:es thereqUired opehl:nd(sf~nd·
transfers them to the FPU by performing oneB.r)nore external processor d~ta write cycles. Dur1nt.
these cycles, lines CS< 1:0>.=01 and the DAt <:31:00 > nus ccintaihs. th~ trtinsfer:recl" ~ata'.
The opcode of the instruct:iol\ t~ be executed determines the number and dlitatype of the operands
transferred from the CPU toihe FPU. The followmgroles applyto the transfer of operanos from the
CPU to the FPU:
.
· Integer operand-An in~r operand is ~eff!lTed in one externalpro~sSQr data wri~ cycl~. lf
the integer is a byte, it ap.Pe~s on DAL<67:~6> with leading zeroes o1l l)AL<31:P8>. If the
integer is a word, it appe~ on DAL< 15:0().>. ~th leading ze):Oeson D~L<i 31:16 > .~.·
· .
· Floating-point operands~·An F_floating operand is transferred in one ~ternal pi:Ol:tessor ·dilta
write cycle. A D.J:ldllting or G_floating o~d is tntnsfefrecl in· two consecutive exrer.tifil
processor data write cycles; bits < 31:00> are transferred during the first cycle: and bits
< 63:32 > during the second.
·
·Multiple operands-Ihoperations requiringt® operands, the secondot)erand is transfer~
first. In operations ~uirillg three or more <>l'¢riJ.rids, the order of operand ttansfer iSdetermiried
by the instruction b¢1ng ~ted.
·'· ·
'.t ·,_':",',-',·,._. - "
·POLY instruction-Exe<:ution of the POLY·instructioninvolves an indeterminate ,m.imber,9£ operands and results. Duripg a POLY instruotl~n, the FPU need. only receive a coefficient;;to ·
calculate the next im;~ediate result. The FI::>P coptinuesto acceptcoe£fi¢i<mts and return results··
until the CPU sends theFPU another command.
Table 5 summarizes ~ order in which ope~ and results are transfe~red for all hlstructi.ons
recognized by the FJ>U. The ~hle uses the folloWiµg conventions:
· ..
.
·. .
'. --- ,,-
'
: ' -., '-., ,.
,,
\
· An "x" in a mnemonic·indkates that the FBUp:rocesses the two-operand and tliree-operand
versions of the instrtlction.in exactly the same way
· The "#" nIDCt to som.1? of the operands and reSults of a POLY instruction indicates that .the number of these operands and results depends on the size of the coefficient tal5le.
· A result may be roundedlR], truncated [TJ~ pf ~act[E]. ·
The MicroVAX FPU User's Guide prov~de~. co~plCte descriptio~ ~£ th~ operatjqn of these
instructions.
-
Preliminary
MicroVAX 78152
Table S · MicroVAX781.l2 Opetand Transfer .
VAX
FPU
Fll'St Second Third
Mnemonic Opcode Tumsfer lransfer Transfer Operation
Result 1
ACBD. 06F
ACBF 04F ACBG 14F
limit.cl add.cl index.cl (index+ add):limit (index.d[R]) limit.£ add.£ index.£ (index+ add):limit (index.f[R]) limit.g add.g index.g (index+ add):limit (index.g[R])
ADDDx 060,061 add2.d addl.d ADDFx 040,041 add2.f addl.f ADDGx 140, 141 add2.g addl.g
addl+add2 addl+add2 addl+add2
sum.d[R] sum.f[R] sum.g[R]
CMPD 071 CMPF 051
CMPG 151
src2.d srcl.d src2.f srcl.f src2.g srcl.g
srcl-src2 srcl,src2 srcl-src2
CVTBD 06C CVTBF 04C CVTBG 14C CVTDB 068 CVTDF 076 CVTDL 06A CVTDW 069 CVTFB 048 CVTFD 056 CVTFG 199 CVTFL 04A CVTFW 049 CVTGB 148 CVTGF 133 CVTGL 14A CVTGW 149 CVTLD 06E CvTLF 04E CVTLG 14E CVTWD 06D CVTWF 04D CVTWG 14D CVTRDL 06B CVTRFL 04B CVTRGL 14B
src.b src.b src.b src.d src.d src.d src.d src.f src.f src.£ src.f src.£ $rc.g src.g src.g src.g src.1 src.1
soc.I
src.w src.w src.w src.d src.f src.g
flt cvrt fltcvrt flt cvrt intcvrt flt change intcvrt intcvrt intcvrt
flt change
flt change intcvrt intcvrt int cvrt flt change int cvrt intcvrt
flt cvrt
flt cvrt
flt cvrt flt cvrt
flt cvrt flt cvrt mid int cvrt mid int cvrt mid int cvrt
d...Jloat[E] Lfloat[EJ g_float[E] byte[T] Lfloat[R] longword[T] word[T] byte[T] cLfloat[E] cLfloat[E] longword[T] word[T] byte[T] Lfloat[R] longword[T]
wordm cLfloat[EJ Lfloat[R] g_float[E] cLfloat[E] Lfloat[E] g_float[E] longword[R] longword[R] longword[R]
DIVDx DIVFx DIVGx
066, 067 divd.d divr.d 046, 047 divd.f divr.f 146, 147 divd.g divr.g
divd/divr divd/divr divd/divr
quo.d[R] quo.f[R] quo.g[R]
EMODD 074 EMODF 054 EMODG 154
muirx.b muir.d muld.d muir*(muir'muirx) int.I muirx.b muir.f muld.f muir*(muir'muirx) int.I muirx. w muir.g muld.g muir*(muir'muirx) int.I
Result2
fract.d[R] fract.f[R] fract.g(R]
1-70
Confidential and Proprietary
-
Preliminary
VAX FPU First Second Thinl
Mnemonic Opcode Transfer 1.iansfer 'Ihmsfer Operation
Result 1
MULDx 064, 065 muk.d muld.d MULFx 044, 045 muir.f muld.f MULGx 144, 145 muir.g muld.g
muir*muld muir*muld inuil:*muld
prod.cl[R] prod.f[R]
prod.g[l~J
POIYD 075 POLYP 055 POLYG 155
arg.d intl.d #coeff.d (ill'g*intl) +coeff #int2.dQlJ arg.£ intl.f ~~££.f (arg*intl)+coeff #int2.f[R] arg.g intl.g Ncoeff:i :(arg*mtll-+;co~ff #int2.g{RJ
#int3 .d[R] ...
#int3.f[R] ·... #int3.g[R] ...
SUBDx SUBFx SUBGx
062, 063 min.d sub.cl 042, 043 min.£ sub.£ 142, 143 min.g sub.g
min-sub
min-sub
fu.ih~suh
diff.d{Rl
diff,f[R] diftg[R]
EMUL INDEX MULLx
07A muir.ri muld.ri --
OOA
(muir-ri) size~ri
OC4, OC5 muiNi muld.ri _;.
,m:t;Ut~tnu14; .·
rnuir*size tnUir*mUld
pmCf.wq[E]
mcrei.ou~.wq[El-
prod:\vq[E]
DIVLx OC6, OC7 divr.rl divd.rq -
EDIV 07B
divr.rl divd.rq -
divd/divr
divd/divr
quo.w[E] quo.w[E]
rem.w(E] rem.w(E]
Note: The integer divide instructions require that th~lower 32:tnt:s of the dividend be transferred first, and then the upper 32-bits.
Operand pioc:euing-After the CPU ttamfel'$1ihe fast()perand, iteontinuously performs external
processor response enable cyde8 and waits for a response &om the FPu. For each of these cycles,
the CPU asserts the appropriate status code on lines CS< 1:0> (CS< 1:0> = 11) and asserts the
EPS signal.
.
... .
..
·
FPU operand processing is completely invisib~ ~·.the ~PU~ may no~~· a1t~d h}I. t;he user.
Status transfer-When the FPTt1 is ready to pass.;a result to theOP'IJ; it respondstri the next extci:nal processor response enable cycle by asserting the C82 Signal .!met $multaneouslydriving statlis
information onto the DAL·.bus. The CPU respondsto.th@iasserl;i~t1of the CS2 ~by.perfor~
one additional externalprocessor response enable~cle,,duringiWhich the CPU rei.\dsthe FPU status information again.
The format of the status infor~ion is shmvndn.figure6 and defined in '.Iable 6. When the }iPU
n asserts the CS2signal, it places bits of s~tus onto tl~fDiL< 31:00> bus. The CPU examines
bits <05:00>.
·
·
·
Figure 6 ·MicroVAX 7.81)2 Status Format 1-71
DAL Line
31:06
05
04
03
02:00
Tabie 6 · MicroVAX 78U2 Status Qesi;ription
Not used
FN (Furictfon negative)-Indicates the status as.follows:
FN = 1 if result LSS is 0
FN =0 if LSS not 0
FZ (Function zero)-Indicates the status as follows:
FZ= 1 if the result EQL is 0
FZ =0 if result EQL is not 0
BR (Branch)-Indicates the status as follows:
BR.., 1 if ABCx should branch
BR= 0 if ABCx should not branch
EXC CODE (Exception code)-Indicates that the following events have occurred:
Code
Description
0
reserved
1
floating divide by zero
2
integer oyerflow
3
floating overflow
4
floating underflow
5
reserved operand detected
6
operation completed normally
If the EXC CODE is not 7 after a floating-to-integer conversion instruction, the condition codes associated with the instruction are unpredictable and must be determined by the CPU. Integer multiply and divide instructions always return unpredictable condition codes (that is, in the FN, FZ, and BR fields) and set the EXC CODE field to 7.
Result ttansfe:r-The CPU performs one or more external processor data read cycles to read a result
from the FPU. During one of.these cycles, lines CS<l:O>=Ol and the DAL<31:00> bus contains the read data. After the result transfer, the CPU and FPU are free for the·next transaction.
The following rules apply to result transfers from the FPU to the CPU:
· Integer results-An integer result is transferred iri one external processor data read cyde. If the
integer is a byte, it appears on DAL< 07 :00 > with unpredictable data on DAL< 31:08 >. If the
integer is a word, it appears on DAL< 15:00 > with unpredictable data on DAL< 31:16 >. For
integer multiplication, two 32-bit transfers are necessary to return the entire result.
· Floating-point results-An F_floating operand is transferred in orieexternal processor data read
cycle. A D__floating or G_floating opemnd is transferred in two co.nsecutive external processor
data read cycles; bits < 31:00 > are transferred during the first cycle; and bits < 63:32 >,during
the second cycle.
'
· Overflow and underflow-In integer overflow cases, the FPU always returns the low-order bits of the true integer result; in floating underflow cases, the FPU always returns a zero result.
· CMPx instruction results-CMPD, CMPF, and CMPG do not cause a result to be generated by the FPU, hut the CPU will request one. The FPU returns a meaningless result that the CPU ignores.
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Confidential and Proprietary
-
Typical FPU/CPU Interconnection F:igure 7 illustrates atypical FPU/CPU hardware configuration. In the example, a DAL transceiver and latch is includedin the design for the benefit of the external logic that c0n1municates with the
FPU/CPU via the DAL. Also included for completeness are several MicroVAX 78032 CPU control signals that must be interpreted or generated by external logic. Refer to the "MicroVAX 78032
CPU" section for information on these control signals.
VCC
~
iNTfiM 5MR i5MG
BM<i:O>
OS
PWRFi: iiALi' ERFi
FiDY
Rim
CLKI . - - - - - GNCl, VBB
t-::-=. MicroVAX
7li032
CPU
_._uWDF_r..=..-c-,:_-,:,.-.t..-....,,._.,_--.-.-._-:,.'....".'....,'.:,,t,'....",.'.-..~.-..t.!.-..","."."_""_."__,_,...,..-·1W:;ini
---v~c ---GND,VBB
Figure 7·MicroVAX 78132 Typical F~tl/Micfe.i!IAX 78032 CPU Interconnection
',,
'
· Specifications
The mechanical, electrical, and envil'orunental characteristics and specificatfons for the MicroVAX
78132 are described in the following paragraphs. The test conditions for theelectrf<;dvalues are as
follows unless specified other\ll"ise.
· ··· ·
· Operating temperature range (TA): 0°C to 70°C
· Ground reference (V55) ·Supply voltage (Vee): 4.75 V
Mechanical Configuration The physical dimensions of the MicroVAX /8132 68-pin CERQUAD package are contained in AppendixE.
Confidential and Proprietary
1-73
-
Preliminary
MicroVAX'7Stl2
Absolute Maximum Ratings
Stresses greater than the absolute maximW,Q ratings may cause permanent' damage to the device. Exposure to the absolute maximum ratings for extended periods may adversely affect the reliability of the device.
· Supply voltage (Vcc): -.:o.5 V to 7.0 V
· Input or output voltage applied: -1.0 V to 10 V
· Operating temperature (TA): 0°C to 125°C
· Storage temperature range: -55°C to 125°C
· Power dissipation: 3 watts (maximum)
Recommended Operating Conditions · Supply voltage: 4. 75 V to 5.25 V
·Active supply current (led: 240 mA (maximum)
· Temperature range: 0°C to 70°C · Relative humidity: 10% to 95% (noncondensing)
de Electrical Characteristics The de electrical specifications of the MicroVAX 78132 FPU for the operating voltage and temperature ranges specified are listed in Table 7.
Symbol Vm Vn.
Vnm VILE Voa Voi
VOLS
Table 7 · MicroVAX 78132 de Input and Output Parameters
Parameter
High-level input voltage
Low-lever input voltage
High-level input EPS signal
Low-level input EPS signal High-level output voltage Low-level output voltage
Low-level output voltage CS2
Requirements
Min.
Max.
2.0
0.8
2.2
0.6
2.4
0.4
0.4
Units
v
v
v v
v
v v
Test Conditions
IoH=-400 µA Io1=2.0mA. 101=5.2 mA
1-74
Confidential and Proprietary
-
Symbol · Pannnetet
In.
lnputl~
'current
loL
Output leakage
curient
lee
Active supply
cilrrent
c ..
Input capacitance
(except EPS)
EPSinput capacitance
Requirements
Min.
Max.
-10
10
-10
10
700
10
30
Uqits µA
pF· pF
TestCondidons
ac Electrical Characteristics
Figures 8 is the timing waveform for the clock input (CL.Kl)·and Table 8 lists the clock timing
parameters. The formulas for the timing ~rs are stated it1 terms of clock periods where a
period P=tap.
.·
CLKI
Figure 8 ·MicroVAX 78132 CLKI Tittling W~eform
Table 8 ·.MicroVAX 78ll2 OtKI Timing Patameters
Symbol Definition
Requirements (ns)
Min.
Max.
ta, Clock in fall time
4.5
tau Clock in high
8.0
ten. Clock in low
8.0
ta, Clock in period
25
250
tCIR Clock in rise time
4.5
1-75
Preliminaty
MicroVAX ;18i.J2X
Figure 9 sh,oWs the:~~rial processe>rdata timing ~q,~Jl~~~or a read/respon~.t::n~ql~ fYde a.tld a
write/command write cycle. Table 9 lists the signa.biming Parameters. The following notes apply to
the signal measurements;
·
·
· ac characteristics are measured with a purely capacitive load of 100 pF and the parameters are
valid for loads up to 100 pF.
..
· ac high levels are measured at 2.0 V and low levels at 0.8 V except for the EPS signal.
· The achighlevelof the.BPS signal is measured at 2.2 V and the aclow levelis measured at 0.6 V. · p,.,.tcJp
T4
T1
T2
T3
T4
T1
tcEP 'EPLC
T4
Tl
T2
T3
T4
T1
lCEP IEPLC
CLKO 50
- - - -. .) I OAL<31:00>
( DATA
)-
1~ ..,.:.~~=~ ~
__/....-----..j d EP5
'wREP
[FS...__ .. . tePLWO (MAX)
~
t;·
tePWA
Wii \ \ \ \ \ \ \ \ \ \ \
I
l/7lJlZ
I
CS<1:0>
Wri1a/Command Write Cycle
· Figure 9 · MicroVAX 781J2 Extemal Processor Data Transacthw, Timing
1-76
Confidential and Proprietary
-
MicroVAX 78132
Table 9 · MicroVAX78U2 External Processor Data Transaction Tuning Parameters
Symbo1 Definition
Requirements (ns)
Min.
Max.
tCEP CLKO falling through 0.8 V to EPS falling through 2.2 V
P+l p + 19
tDOEPH
tEPCSL tEPCSZ
tEPDI
Write data valid setup time to EPS deassertion
EPS assertion to external processor assertion of CS < 2 >
EPS deassertion to CS < 2 > three-stated by external processor EPS assertion to read data valid
2P-35 0 0 4P-40
3P-40 2P-20
tEPHDO
tEPLc
tEPLWI tEPLWO
tEPWB. tEPZ twREP
Write data hold time from EPS deassertion EPS falling through 0.6 V to CLKO rising through 2.0 V EPS assertion width (read) EPS assertion width (write) WR and CS< 1:0 > hold time from EPS deassertion EPS deassertion to read data three-state WR and CS< 1:0> set up time before EPS assertion
2P-25 P-25 4P-20 5P-20 P-20 3P-20 2P- 35
4P + 20 5P + 20
Confidential and Proprietary
1-77
/
·Features
· Fully compatibile"with the MicroVAX 78032 CPU, CVAX 78034 CPU and rtVAX 78R32 CPU
· 16 Peripheral Interrupt Request (PIRQ) lines
· Edge or level triggering for each PIRQ line with individually selected priorities · 16 Programmable vector addresses ·,Optional external vector generation
· Fixed or round robin priority modes
·Uses a daisychain interrupt-enable scheme for cascading · High-sp~d, low-power CMOS technology
·Single 5-Vdc power supply
·Description
The MicroVAX 78516 Vectored Interrupt Controller (VIC)* is a low-cost, programmable interrupt controller that is fully compatible with the MicroVAX 78032 CPU, CVAX 78034 CPU, and rtVAX 78R32 CPU. The VIC manages as many as 16 interrupt sources, resolves interrupt priorities, drives the interrupt request (IRQ) lines of the CPU, and provides a programmable 13-bit interrupt vector to the CPU. Users can choose either the fixed or round robin interrupt priority mode. Using a daisychain scheme, the VIC is ~scadable. Figure 1 is a general block diagram of the MicroVAX 78516 VIC.
0At<15o00> J(1J
W1i 6ll
CS<2-:(I>
m5'1
~ ~
MicroVAX INTERFACE
CLK
illm
ClCCK GENERATION AMO RESET LOGIC
IAKEI
REGISTERS AND CONTROl LOGIC
PRIORITY ANO ARBITRATION LOGIC11
PER1_1*tEAAt. 1NttRFACE
PUI0.15 PiflJ14 l'IRU13 PtRQ112 AROH 'l'IRUtO PIA009 PIAtl08 PIR007 PIROOS PIROOS Plll004 P!ft0()3 PIR002 Pll!001 PIROOO
)MC iACK IAl<ECW IAl<EON
Figure 1 ·MicroVAX 78516 VIC General Block Diagram
*The MicroVAX 78516 VIC and the rtVAX 78516 VIC are physically and functionally identical and are assigned the same Digital part number.
Confidential and Propt;ietaty
1-79
·-
· Pin and Signal Descriptions
MicroVAX 78.516
The input and output signals and power and ground connections for the 68-pin device are shown in Figure 2. Table 1 contains a summary of the signals and describes their functions. Detailed descriptions of the signal functions are contained in paragraphs that follow.
VOD vss IAKEOP IROO IR02 ROY
vss
cso
VDD
vss IAKEON !ACK
IRQ1
IR03 VDD
AS
CS1
XVEC DALOO DAL01 DAL02 DAL03 DAL04 DAL05 DAL06
DAL08 DAL09 DAL10 DAL11 DAL12 DAL13 DAL14 DAL15
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
61·
43
62
42
63
41
64
40
65
39
66
38
67
37
68
36
MicroVAX 78516
VECTORED INTERRUPT
35
CONTROLLER
2
(CAVITY DOWN)
34
3
33
4
32
5
31
6
30
7
29
B
28
9
27
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
CS2
iAKEi
OS WR CSEL NC NC NC NC NC NC
vss
RESET CLK VDD PIR015 PIRQ14
VOD PIROOO PIRQ02 PIR004 PIR006 PIR008 PIR010 PIR012
VDD
VSS
PIR001 PIRQ03 PIR005 PIR007 PIRQ09 PIRQ11 PIR013
Figure 2 ·MicroVAX 78516 Pin Assignments
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Confidential and Proprietary
-
Pin 9-1,68-62 47 41
40
43,45,46 50 28-13 51-54 55
6t 42
56
MicroVAX 78516
Iable 1 ·MicroVAX 7&516 P"m and S'ignal Summary
Signal
Input/Output Definition/Function
DAL< 15:00 > input/output Data/address lines < 15:0 > - Time-multiplexed
lines used to transfer address, data, and interrupt information between the VIC and the CPU.
~nput input
Address strobe-Latches the state of the VIC into interrtal t'lhgisters.
Data Strobe.;;;;..When asserted during a CPU read .· .or interrupt acknowledge cycle:, it indicates that DAL< 15:00<> lines are available to receive data.
When asserted during a CPU write cycle, it
.·latches the. ff:ata on. the DAL< 15:M>. lines into
the internru: registers.
WR
CS<2:0>
input input
Write-Indicates the direction of data transfer on the DAL< 15:00> lines.
Control status-Used to decode the bus cycle type.
RDY
output
PIRQ< 15:00> inputs
·· Ready--..SyndOOnizes data transfers bertveen the VIC and theCPU.
peppheral i~f;f:J:J.Upt requests <:: 15:00>-Used by peripheralJlevi.ces to. request an internipt.
IRQ<J:O>· output
IACK
output
Interrupt teq'Uest <3:0>-Used to rtotify the CPU of any pending interrupts. These lines are maskable by the CPU.
Interrupt ackno..,,.ledge'."'.""lpdicat;~s that the Q.ir-
rent bus cycle edge is ap. interrupt acknowledge
cycle.
·
)WEC
output
IAKEI
input
IAKEOP
output
External vei::tor--Indicates that the interrupt
request is being acknowledged and the peripheral device mus.t s.upply a vector.to the CPU.
Interrupt· acknowledge enable in....:...Daisychain
control signal that indicates the V1C ean re5pond
to the curreht interrupt acknowledge cycle,
Interrupt.aCknowledge e,ns,tble out P-Anacdve
high pullup output .that connects together with
the with the 'tAJ{EON output to the iAK'EI input
of the next device in th(! daisychain.
·
Confidential and· Proprietary
1-81
-
Pin
Signal
57
IAK.EON
39
CSEL
31
RESET
30
CLK
10,11,29,44,60 Von U,32,48,58,59 Vss
Preliminary
MicroVAX 78S16
Input/Output· ,Definition/Funct.ion
output
Interrupt acknowledge enable out N-An active low pulldown output that connects together with the IAKEOP output to the IAKEI input of the next device in the daisychain or connects to the ERR input of the CPU.
input
Chip select-Enables read/write operations to .the internal registers.
input input
input input
Reset-Sets the VIC to a known initial state. Clock-Used to generate the internal time states of the VIC. Voltage-Power supply voltage. Ground-Ground reference
MicroVAX Bus Interface Signals
Data/Address lines (DAL< 1.5:00 > )-These lines are bidirectional and are. used to transfer
address and data between the VIC and the CPU. During internal VIC register access cycles, when the CSEL line is asserted, the DAL< 15:00 > lines transfer data to and from the internal registers. During interrupt acknowledge cycles, if the IAKEI input is asserted and the VIC has a pending interrupt at the level being acknowledged, the VIC places one of its interrupt vector registers on the DAL< 15:00 > lines or assert the external vector control signal (XVEC}. When the XVEC signal is asserted, the interrupting device must then supply a vector. During interrupt acknowledge cycles,
the DAL< 15:00 > lines are driven only when the IAKEI input is asserted, the IAKEON output is
deasserted, and the XVE bit in the interrupt vector register is cleared. The DAL< 15:00 > lines are otherwise in a high-impedance state.
Address strobe (AS)-When asserted, this signal latches the information on the DAL< 06:00 >,
CS< 2:0 >, and the WR lines into the VIC. This information is used internally to latch the PIRQ < 15:00 > line information for the duration of a read or interrupt acknowledge bus cycle that
accesses the VIC.
Data strobe {DS)-This signal is used by the VIC for data timing during internal register access cycles and interrupt acknowledge cycles. When writing to one of the internal registers, the assertion of this signal strobes the DAL< 15:00 > line data into the selected register. When reading an internal register, the assertion of this signal is used to transfer the contents of the selected register onto the DAL< 15:00> lines. When responding to an interrupt acknowledge cycle, the assertion of this signal is used to transfer the contents of the appropriate interrupt vector register ontotheDAL<l5:00> lines.
Write (WR)-This signal indicates whether the current bus cycle is a read or a write cycle. This
signal is used with the CS< 2:0 > inputs to decode the type of bus cycle in progress and to access
· internal registers to determine whether the operation is a read or write operation. The WR input is asserted for write cycles and is deasserted for read or interrupt acknowledge bus cycles.
Control status (CS < 2:0 >)-These lines and the WR input are decoded to determine the presence of a read, write, or interrupt acknowledge bus cycle. The bus cycle selections are listed in Table 2.
1-82
Confidential and Proprietary
....
Preliminary
MicroVAX 78S16
1ltble 2 · MicroVAX 78516 Bus Cycle Decoding*
.CSl..ine
CSEL Bus Cycle
2
1
0
H
x x H
L
Read
H
X
H
L
L
Write
L
H
H
H
X
lilterrupt aclqxowledge
*H =high level, L=low level, X=either high or low level.
Ready (RDV)-'Ihis signal is asserted by the VIC when its irttetnal registers are accessed during a
read or write cycle or during an interrupNlcknowledge (IACK)cyde whenthe VIC is providing an
interrupt vector. During IACK cycles, at le!Ultone re"'1y slip wilt be generated to al1ew an interrupt
acknowledge enable signal· (IAKEi, IAKEOP, :Or IAKEON) to ~!Opagate through ·the daigychain.
The total number of ready slips that occur depends onthe length of the daisychain. This is an open
drain (pulldown) output capable of sinking 16 mA.
Interrupt Int.er.face Signals
Peripheral interrupt request (PIRQ < lS:OO >)-These input lines are used by peripheral circuits
more to request an interrupt.· When one .or·
of these lines a!.'C asserted ~nd the interrupts are
enabled, .the VIC will assert the appropriatel!Qline(s). M;!.pping between each PIRQline and the
IRQ line is programmable by software thooghtheIRQ Map ~sters. The interrupt request can, be
sensed by a signal level or edge or by the signal polarity. The sensing is programmable by the user.
Unused PIRQ lines must. be connected to a.valid logic level.
Interrupt request (liQ<3:0> )-One or more of these lines will.be asserted by the.VIC when a
PIRQ line is asserted and the interrupts are enabled. The IRQ Map registers determine which IRQ
line is asserted for a particular PIRQ line. An IRQ line will be deassert¢d when all pending
interrupts mapped to that IRQ line have been serviced. T~se,~u'¢ open drain (pulldown} outputs
that require external pullup resistors.
Interrupt acknowledge {iACK)-This signal is a result of decoding the CS<2:0> and the WR
lines and will be asserted for all interrupt acknowledge cycles. The signal is not affected by the
interrupt acknowledge daisyc:hain !lignals. It allows the ~terna})ogic to disable the memory
transceivers during an interrupt acknowledge cycle. · ·
External vector enable <MCl-This signal is ass~ed Hthe XVE bifi.$ setin theinterrupt vector register for the PIRQ being acknowledged. The requesting device must s"l,lpply, its owh vector and the VICplaces thel.lAL< 15:00 > li!lles in the high-impedanqe, state. The hatdware supplying the
vector is required to assert the RDY signal at the correct time.
Daisychain Interface Signals Interrupt acknowledge enable in (IAKEI)-This input allows more than one VIC and other peripheral chips to be connected together in a daisychain. When this input is asserted, the VIC can respond to the current interrupt acknowledge bus cycle. This signal should be con.nected to a ground reference if the VIC is the highest priority device in the daisychain.
Confidential and Proprietary
1·83
-
MicroVAX18Sl6
Interrupt ackl'lawledge enable .QUt lUgh (L\KEOP)-This <;>utput and the IAKEON output are
connected to the IAKEI pin of the next lowest device in the interrupt daisychain. The IAKEOP output is normally an active high pullup. However, when the IAKEI signal is asserted and the VIC has no pending interrupts at the level being acknowledged, the IAKEOP output is a highimpedance. If the VIC is the lowest-priority device in the daisychafo, this line is not connected to
another device. This is an open drain, pullup output that cannot be pulled low. For daisychain
operation, the pulldown function is performed by the IAKEON line.
Interrupt ackl'lowledge enable out low/error low (IAKEON)-This is an open drain pulldown output that is used to either pull down the next IAKEI level in a daisychain application, or pull down the ERR input to the CPU if this VIC is the last (or only) device in the daisychain. The IAKEON line is normally in a high-impedance state. However, when the IAKEI signal is asserted and the VIC has no. pending interrupts at the level being acknowledged, the IAKEON signal is asserted. The VIC asserts this signal if PIRQ line is in level mode and the interrupting device removes its request before the interrupt is acknowledged. The level sensitive inputs are not stored
by'the VIC. Therefore, the PIRQ line that was asserted cannot .be used to determine the vector to
return to the CPU. This output is a high current open drain output.
Miscellaneous Signals Chip select (CSEL)-This signal, when asserted, enables read/write operations to the internal registers.
Reset (RESET)~This signal,· when asserted, sets all the internal registers to a known value except for the interrupt vector (IVEC) and IRQ map (IMAP) registers. The contents of the IVEC and IMAP
registers are unknown. The interrupts are disabled and the DAL<15:00> lines become a high
impedance.
Clock (CLK)-This signal is used to gene'rate the internal time states within the VIC. Any oscillator that meets the input requirements of CLK signal may be used.
Power and Ground COhnections Power supply voltage (VDD)-Power supply 5 Vdc. Ground (V58)-Ground reference.
·Functional De$Ctiption
The VIC may be connected directly to the CPU bus or to a buffered I/O bus. It accepts up to 16 priority interrupt requests (PIRQ < 15:00 >) from peripheral devices and it drives an associated
IRQ line to the CPU. The mapping between the VIC PIRQ lines and CPU IRQ lines is programmable. The VIC decodes the presence of a CPU interrupt acknowledge (IACK) cycle on the bus and monitors the interrupt priority level of the interrupt being acknowledged. It will respond
to the IACK cycle by transferring the appropriate user programmed vector on lines DAL< 15:00 > .
The CPU uses the vector as an offset into the system control block (SCB) to locate the starting address of the interrupt routine.
A daisychain wiring scheme enables the user to connect more than one VIC together so as to
expand the int~rriipt handling capability from that of a single VIC. This scheme is compatible with the daisychain scheme used by the other peripheral interfaces.
A peripheral device requests service by asserting one of the PIRQ lines. When the VIC detects the PIRQ line that has been enabled, it reflects the assertion of the line in the pending summary register (PSR) bit that corresponds to that PIRQ line. The IRQ output, programmed by the user for that PIRQ, will also be asserted to indicate to the CPU the interrupt condition at the specified IPL
1-&4
Confidential and Proprietary
levd. The CPU will respond with a!'l interrupt acknowledge cycle that contains the priority level of the interrupt being acknowledged; The VIC then decodes the IACK cycle and IPL line information and if the VIC ~eneratedthe interrupt and the IAKEl (daisychain input) signal is asserted, it selects
the vector of the next PIRQ to be serviced for that IPL level. It then places that vector on the DAL< 15:00> lines. If the VIC did not request the interrupt, it asserts the IAKEON (daisychain output) signal to allow the next devices in the daisy chain to be serviced. When the VIC is responding to an interrupt, it holds. the.IAKEON line from be~n& asserted to prevent devices in the
daisychain that have a lower priority from responding.
Regist.ers
The VIC contains 16 interrupt vector registers and..9' interrupt control registers that allow each
request to be individually configured by software·. The internalVIC registers, shown in Figure 3,
are accessible by the CPU and are used by software to collfigute the operation of the VIC. Each
register consists of 16-bits and is located on a longword boundary. The base address is determined
by external address decode logic. Direct access to the VIC registers is enabled when the CSEL signal
is asserted and the VIC decodes the address on the DAL< 06:09 > lines to sdect the register to be
accessed.
·
·
NOI'E: Only word access to the lower 16-bits of thelongword are allowed to transfer data between the CPU and the VIC. Byte accesses and longword accesses are not allowed. Longword
access may result in the CPU reading the incorrect data or lost data during a write cycle.
ADDRESS
15
00
BASE BASE+4 BASE+8 BASE+12 BASE+16 BASE+20 BASE+24 BASE+2B BASE+32 BASE+36
BASE+64 BASE.+t!B
POLARITY REGISTER'
. LEVEL/EDGE REGISTtR
PENDING Sl,JMIMR'I'. REGISTER
INTERRUPT ENASl..,E REGISTf!R
-"- I RO MAP REGISTER .0 .""""
I IAO MAP REGISTER 1
IRO MAP REGISTER 2
IRO MAP REGISTER 3
ROUND ROBl!·Hlt.EGISTER
..,.··· ";.:,
· ADDRESSES tBASE+361 ·. TO (8Ai$E~ ARIO
.0 .NOT 11',!TEFINALLV
· 'OECOOEt>S'Y 'l'HE VIC ...:...
.. INTERRUPT VECTOR REGISTER 0
BASE+124
INTERRUPTVECTOR R.EG.ISTER 15
Figure 3 ·MicroVAX 78516 Register Address and Descriptions
Confidential and Proprietary
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- - - - - - - - - - - - - - - - - - - ~·······-···-··-·---·-·--·~
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Preliminary·'
MicroVAX78516
Polarity register-The polarity (POL) register selects. the polarity of the input used to assert a
PIRQ < 15:00 > line. When a bit is set, the corresponding line is asserted by a low-to-high
transition or by a high level. When a bit is cleat, the corresponding line is asserted by a high-to-low
transition or by a low level. The register format is shown in Figure 4.
15
00
.I :
PIRO< 15:00>lEVEL/EDGE POLARITY
Figure 4 ·MicroVAX 78516 Polarity Register Format
The POL register is used with the level/edge (LE) register to configure each PIRQ input. A PIRQ input may be configured to respond to a rising edge, a falling edge, a high level, or a low level signal. Table 3 shows the bit selections of the POL and LE registers and the resulting state of a PIRQ line. When the RESET line is asserted, the POL register is cleared.
POL Bit 0 1 0 1
Table 3 · MicroVAX 78516 PIRQ Input Line Configurations
LE Bit
PIRQ Asserted State
0
Falling edge
0
Rising edge
1
Low level
l
High level
LeveJ/Edge register-The level/edge (LE) register is used to select the way in which a PIRQ
< 15:00 > line detects an interrupt request. It allows the user to select either level or edge sensitive
triggering. When a bit is set, the corresponding PIRQ line is level sensitive. When a bit is clear, the corresponding PIRQ line is edge sensitive. The polarity of the PIRQ line input is selected by the polarity register (POL). Figure 5 shows the register format.
15
00
PIRO< 15:00> LEVEL/EDGE TRIGGER
Figure 5 ·MicroVAX 78516 Level/Edge Register Fonnat
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Confidential and Proprietary
MicroVAX 18516
Level-sensitive inputs allow more than one device to be connected to a single PIRQ line by using a
wired NOR structure. Once the correct polarity level is detected by the VIC, the corresponding interrupt pending bit is setin the pending summary register (PSR). The interrupt pending bit will remain set until the PIRQ line is cleared. Therefore, an interrupt acknowledge cycle from the CPU will not clear the interrupt pending bit in the PSR register until the PIRQ line is deasserted. If a wired NOR structure is used, a external pullup resistors is required pn the PIRQ line.
Edge sensitive inputs detect either a high-to-low (falling edge) or low-to-high (rising edge)
transition. When the correct transition is detected, the corresponding bit in the PSR register will be
set..The VIC will clear the bit when the interrupt is seryiced 11n,d will not recognize an.other
interrupt request on this line un~ the proper tqmsition occurs. When the~ line is asserted,
the LE register is cleared.
·
Pending Summaey registef-'The pending summary register (f$R) pro¢.des a s,ummary of the
internal interrupt pending flags. When a bit is set, an interrupt request is pending for the
corresponding PIRQ line. Whep .a bit is clear, Po interrupt i.s pending.for the corre~pom:lir:% PIRQ
line. The contents of the PSR register are latc}l.ed during a read and !ACK cycle. The regi~ter format
is shown in Figure 6.
·
·
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PIRO< 15:00>INTERRUPT PENDING
Figure 6 ·MicroVAX 78518 Pending Summary Register Format
The VIC manages the setting and clearing the PSR register bits for level and edge sensitive PIRQ inputs as follows. When the RESET input is asserted, the PSR register is cleared. · For level sensitive PIRQ inputs, the ccirresponding .PSR bit will be set. when the PIRQ line is
asserted and cleared when line is deasserted.
· For edge sensitive PIRQ inputs, the corresponding PSR bit is set on the assertfug edge of the PtRQ input. The PSR bit for a PIRQ input will be cleared by an interrupt .acknowledge cycle that acknowledges the interrupt request of the corresponding PIRQline, whe.n .the software clears the PSR bit by writing a zero into the appropriate bit, or when information is written into the LE
register.
Interrupt Enable register-The interrupt enable (IEN) register is used to enable or disable the reporting of interrupts to the CPU by each PIRQ line. When a bit is set, it allows an interrupt request from the associated PIRQ line to generate an interrupt to the CPU. When a bitis clear, the associated PIRQ line is prevented from generating an interrupt to the CPU, The register format is shown in Figure 7..
Confidential and Proprietary
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Preliminary
MicroVAX 78516
15
:14 13
12 11 10
: :
09
08 07 I.
I.
06
05 04
03
02
01 ,QO
PIRO< 15:00>1NTERRUPT ENABLE/DISABLE
Figure 7 ·MicroVAX 78516 Interrupt Enable Register Format
nm The register enables or disables the generating of an interrupt to the CPU and does not affect
the detection of interrupts by the VIC. When a PIRQ line is asserted, the corresponding bit in the PSR register is set regardless of the state of the IEN bit for the PJRQ line. TheIEN register provides the support for a software interrupt polling scheme. The register is cleared when the RESET input is asserted.
IRQ Map registers (0-3)-The interrupt request map registers (IMAPO through IMAP3) are used to select the IRQ line to be asserted by the VIC when a PIRQ line is asserted. When a bit in one of the
IMAP registers is set, the corresponding PIRQ line is mapped to the associated IRQ line. The register format is shown in Figure 8. Each register corresponds to one of the IRQ outputs as defined in Table4.
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
I :
: :
: :
PIRO< 15:00>TO MicroVAX IRO LINE
Figure 8 ·MicroVAX 78516 IRQ Map Registers (0-3) Format
Register IMAP3 IMAP2 IMAPl IMAPO
Table 4 · MicroVAX 78516 IMAP Register to IRQ Mapping Line IRQ3 IRQ2 IRQl IRQO
Example: If bit 3 of the IMAPl register is set when the PIRQ3 line is asserted and the IEN register bit is set for thls line, line IRQl will be asserted.
The IMAP registers are not initialized when the RESET line is asserted and the contents will be undefined until programmed by software.
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MicroVAX'l8116
Round Robin ~The round robin (ROBIN) register is used to select either fixed or round
robin priority mode o.foperation fOr each IRQ level. More than one bit may be set in this register at
a time and the register controls only the PIRQ lines for the asscociated VIC. 'The register is cleared
when the WET input is asserted..The register for.µiat is shown in Figure 9. Table 5 describes the
function of each bit.
15
:
. '.
: I : 04 03
: :;
00
.. RAZ
RR17-RR14
Figure 9 ·MicroVAX 78516 Round Robin R:efjster Format
Bit 15:04 03:00
'Dible 5 · MicroVAX 78516 Round Robin Register Description
Description
RAZ (Read as zeros)-Not used
RR17-RR14 (ROUND ROBIN IPL17-IPL14)--.cTl:ieSe ~ selei;:t the priority m.t>defor.all
interrupts mapped to lines IRQ < 3:0>. RRl7 selects IRQ3 etc' When set, the mund robin mode is selected. When cleared,· the fixed mode·is selected.
Interrupt Vector registers .(0-15)-Each of the 16 interrupt vector. (tVECO through IV'EC15)
registers contains a fully programmable 16;bi_t vector. There isan IVECi:egiSterfor each PIRQ line.
The register format is shown in Figul'le 10 and Table 6 descri\Jes the fortdion of each bit.
~
· 1
'
·
·
' '
·
15
I :
: :
: ::
Pl.RO INTERRUPT VECTOR
: : : . ·.·
02 01 00
: II
I I
XVE
OFLG
Figure 10 ·MicroVAX. 78516 Intt:rrupt. Vector, Rcgistet;S (0-15) Format
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Bn
15:02 01
00
MicroVAX 7851.~
Table 6 ·MicroVAX 78516 lntettupt Ve(;t:Or Registers (0-15) Description · Description
VECTOR (PIRQ interrupt vector)-This vector is the offset into the system control block (SCB) for the location of the interrupt routine.
XVE (External vector enable)-When set, the DAL< 15:00> line drivers are disabled and the XVEC line is asserted during an IACK t-yde, indicating that an external vector is to be supplied. When clear, the VIC will drive the contents of the IVEC register onto the DAL< 15:00> lines during an IACK cycle.
QFLG (Normal/Q-bus processing flag)-When set, this bit forces the interrupt priority line of t:he CPp to priority IPL17 when servicing the interrupt. When clear, the CPU will service the interrupt normally.
These registers are not initialized when the RESET input is asserted and the contents of the register is undefined until programmed by software.
Interrupt Level 1iiggering and Edge Triggering The sensing of an interrupt condition by the VIC may be programmed for each PIRQ input by the LE register. Each PIRQ line can be set to respond to either a signal level or to a signal transition (edge}. The polarity of the sensed condition is also programmable.
In the edge-triggered mode, either a high-to-low or low-to-high transition on the PIRQ line will cause the VIC to latch the PIRQ line information. Further transitions on this PIRQ line will have no effect. After the acknowledgment of the latched assertion by the CPU, the VIC resets the latching mechanism allowing the U!ler to again assert the interruptwith a proper transition on the PIRQ line. A latched PIRQ assertion may be cleared by writing to the LE register or by writing a zero to the corresponding bit of the pending status register.
In the level mode, the interrupting device must deassert the PIRQ input before the interrupt
service routine ends to prevent the VIC from sensing the previous level and posting the same
interrupt twice. During edge- or level-triggering, a bit in the pending summary register corresponding to that PIRQ line indicates the pending interrupt and if the interrupt is enabled, the VIC will assert the appropriate IRQ line as programmed in the IMAP register.
If the CPU responds to an interrupt caused by a edge-triggered signal, the completion of the !ACK cycle will cause the VIC to clear the corresponding PSR register bit. If level-triggered mode was
selected, the PSR bit would continue to reflect the PIRQ status.
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MicroVAX 1'8.Sl6
Fixed and Round Robin Priority The two priority modes available to the user are fixed and round robin. Each PIRQ line has a fixed priority with respect to the other PIRQ lines with line PIRQ15 as the highest priority and line PIRQO as the lowest.
In fixed priority mode, the highest pending PIRQ for the IRQ level being recognized by the CPU will be serviced first. In round robin mode, the. highest pending PIRQ for the IRQ level being recognized by the CPU will be serviced and then prevented from requesting another interrupt until all other pending interrupts for that IRQ level have been serviced. When all pending interrupts assigned to an IRQ level have been serviced, the VIC will enable all the PIRQ lines assigned to that IRQ level and the round robin process will start again. The'round robin mode operates only within
the PIRQ lines of a specific VIC.
The VIC accepts as many as 16 interrupts from peripheral devices and drives an interrupt request (IRQ) line of the CPU, as determined by the user. The VIC decodes the presence of an interrupt
acknowledge cycle on the bus, monitors the interrupt priority line (IPL) being recognized, and sends a 13-bit vector to the CPU. Each of the 16 (IRQ) lines i~ configured by software as follows:
· triggering mode and polarity
· IRQ mapping to the CPU
· enabling/disabling of interrupt request
· an interrupt vector
External Vector Generation
External devices can generate their own vector under control of a bit in the IVEC register. The
vector generation sequence is as follows:
1. The VIC provides the external vector enable ~ signal to the external logic that generates
the vector.
;
2. The XVEC signal indicates that the interrupt requested is Reing acknowledged.
3. The external logic supplies a vector to the~ and assert~ an RDYto end the bus cycle.
Daisychain Configuration More than one VIC can be connected in a daisychain-enable configuration as shown in Figure 11. The three signals used are the ackrtowleclge eru:l?le in (i'AKEI}, interrupt acknowledge enable out high (IAKEOP), and interrupt acknowledge enable out low/error low (IAKEON). When the IAKEI signal is asserted, the VIC can respond to the current interrupt acknowledge cycle. If no pending interrupts exist for the IPL line being acknowledged, the VIC asserts the iAKEON and IAKEOP lines to allow the next device in the chain to respond to the interrupt acknowledge cycle.
Interrupt Operation
The VIC receives interrupt requests fro111 qevices and posts interrupts to the CPU by asserting the appropriate IRQ lines. It also provides a vector address to the CPU during an interrupt acknowledge cycle if the XVE bit in the interrupt register is not set. If it is set, the VIC notifies the device that a vector address is required from the device. ·
Posting interrupts-When the VIC detects an assertion on a PIRQ input from a device, it sets a bit in the in Pending Summary register that corre~onds to the PIRQ input. If the corresponding interrupt enable (IEN) bit in Interrupt Enable t(!gister is also set, an IRQ line is set to notify ~he CPU of the.interrupt request. The IRQ line that is set is selected by one of the four Interrupt Map registers. Figure 11 shows the sequence for posting an interrupt reqµest.
Confidential andJ'J.Pprieuu-y
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Preliminary. '
MicroVAX78:5t6
PIRQ ASSERTED
SET BIT INPSA
NO
ASSERT !AO <J:O> LINE SELECTED BY IMAP REG
END
Figure 11 ·MicroVAX· 78516 Interrupt Request Posting Sequence
Interrupt acknowledge response-After the IRQ line is asserted, The CPU responds with an interrupt acknowledge cycle that transfers the interrupt priority level (IPL) of the interrupt being acknowledged on the DAL< 04:00> lines. The VIC decodes this information to determine if it had requested the interrupt. If it had made the request, anchhe'IAKEI input is asserted, the VIC blocks the propagation of the IAKEI signal to another VIC, and sel~cf the vector address associated with the PIRQ line that requested the interrupt. The VIC then transfers the vector to the CPU
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MicroVAX 78516
through the DAL< 15:00 > lines. If an interrupt is not pending at the IPL being acknowledged, the
VIC passes control to the next device in the daisychain by asserting the IAKEON signal and by
placing the IAKEOP line in a high-impedance state. The interrupt acknowledge response sequence
is shown in Figure 12.
NO
DECODE IPL
ASSERTiAi£0N'
DEASSERT IAKEOP
SELECT HIGtfm'
PENDi~
·.
INTEMUPT fORIPl
YES
PLACEIVEC REG ON .Ml,,_ ASSERTADY
A
c
Figure 12 ·MicroVAX 78516 Interrnpt Acknowledge Response Sequence
Confidential and Proprietary
1-9.3
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A
NO
CLEAR PSR BIT RESET EDGE DETECT MECH
MicroVAX 78.516
c
NO
BLOCK PIRO JUST SERVICED FROM REOU EST ANOTHER INTERRUPT
YES
UNBLOCK ALL PIROs MAPPED TO IPL'
END
Figure 12 ·MicroVAX 78516 Interrupt Acknowledge Response Sequence (Continued)
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MiCl'OVAX 71516
· h\tedacing ~ments
The VIC can beusedmth the MkroVAX78031 CPU, CVAX 78034CPU, orthertVAX 78R32 CPU.
It can be. connected to either the CPU bus or to a bufferred 1/0 bus. A typical example of the VIC
connecteCI to a MicroVAX 78032 CPU is shown in Figure 13. The circuit includes separate address decode logic to assert the CSEt input that is used to select registers in the VIC.
~~g~s cs
LOGIC
RESET"*
CS<2:0> iR0.<3:0> 0 " CLKO
CLK*
PERIPHE""1i DEVICE ;·
.PERIPHl;RAL De\f/CE
PERIPHERAL DEVICE
·ANY CLOCK MEETING PC. SPECIFICATIONS ··SYSTEM-WIDE RESET SIGNAL ···THESE LINES NEED EXTERNAL PULLUPS.
Figure U ·MicroVAX 78516 Typical VIC and MicroVAX i80J2 CPU Inter.face Configpration
Daisychain Wiring Figure 14 is an example of~ ]\i{icroVAX 78032· CPUan4 th~ otl\!'.VIC and. wired in a daisychainenable configuration: The initalIAKEI input to the VIC is'held asserted by a ground connection to allow the VIC to respond to to the current interupt acknowledge cycle. If a pending interrupt does not exist for the IPL being acknowledged, the VIC asserts the !AREON and IAKEOP lines to allow the next device in the chain to respond to t~~interrupt ac~ledge cycle.
Confidential and Proprietary
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MicroVAX,\78Jt6
TO NEXT DEVICE IN DAISY CHAIN ·EXTERNAL PULLUP CIRCUITS 'REQUIRED
Figure 14 · MicroVAX785161AK Daisychain Wiring Configuration
Bus Cycles The VIC responds to read cycles, write cycles, and interrupt acknowledge cycles.
Register read cycle-A read cycle is performed by the CPU to read information from a VIC internal
register. The VIC responds to the read cycle when the CSEL input is asserted and when the address
on the DAL< 15:00 > lines corresponds to the address of a VIC internal register. The signal timing
and parameters for register read cycle are shown in the Specification section. The register read cycle sequence follows.
1. The CPU transfers an address on the DAL< 15:00 > lines, indicates a read cycle on control lines
CS<2:0>, and deasserts the WR input to the VIC.
2. The CPU asserts the AS signal to indicate that the information on the bus is valid.
3. The VIC latches the DAL<06:00>, CS<2:0>, and WR line information.
4. The external address decode logic, Figure 13, decodes the address on the DAL lines and asserts the CSEL input to the VIC.
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Prelim.inary
5. The VIC transfers the content of the selected register to the bus and asserts the RDY oritp'Ut'.
to 6.·The CPii latches the data and deasserts the i5S and AS outputs to.indicate the end of the bus
cycle. The VIC th~ deasserts the RDY output to the CPU end the read cycle.
·
Register write cycle-A write cycle is performed by the CPU' to write information into a V!C
internal register. The VIC responds to the write cycle when the CSEL input is asserted by the CPU
and the address on the DAL<06:00> lines corresponds to the address of a VIC internal register.
The signal· timing and parameters. fol' register write cycle are in the Sf><lCif~aclt;in section. The
register write cycle sequence f~. .
·.
. ·
1. The CPU tl'allSfers an address on the DAt <15:00 :> lines, iiidicafos a write cycle on oontrollines CS< 2:0 >, and asserts the WR input to the VIC.
2. The CPU assel'ts the AS signal to indicate that the infol'mation on the bus is valid.
3. The VIC latches the DAL< 06:00 > , CS< 2:0 >, and WR line information.
4. The exterrialaddress decode logic, Figure 13, decodes the address on the DAL lines and asserts the CSEL input to the VIC.
5. The VIC asserts the Ri5Y signal, latches the data on the DAL< 15:00 > lines into :the selected
register, and deasserts the RDY output when the CPU deasserts the DS input.
6. The CPU deasserts the AS output to indicate the end of the bus cycle which also ends the register
write cycle.
lnte:rrupJ ·~ledge cycle-The CPU performs ab interrupt acknowledge cycle in response to an
intem,tpt request (IRQ<3:0>) output from the VIC. The VIC responds to the interrupt
acknowledge bus cycle when its IAKEI input is asserted and when its pending interrupt is the same interrupt .~ recognized by the CPU. The signal timing and parameters fol' the interrupt acknowledge cycle are in the Specification section. The sequence of the interrupt acknowledge cycle sequence follows.
1. The CPU transfers a hexadecimal value of the IPL on the DAL< 15:00 > lines,. indicates an interrupt ~cknowledge cycle on control lines CS< 2:0 > , and deasserts the WR input to the VIC.
2. The CPU ass¢rts the AS signal to indicate that the information on the bus is valid.
3. The VIC latches the DAL< 06:00 >, CS< 2:0 >, and WR line information,
4. The IAKEI input is asserted. The timing of thl~ event depends on the.iocatl,on of the VIC in the daisychaim
5. The VIC transfers the vector address on the DAL< 15:00> lines and asserts the Ri5Y signal. If
the device is required· to supply the vector' address, the VIC !ISs'erls the XVEC output to the
device and the device asserts the Ri5Y signal.
6. The CPU latches the vector address and deasserts the DS and AS outputs to indicate the end of
the bus cycle. The VIC then deasserts the RDY output, if asserted, to end the cycll · · · ·
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MicroVAX 78516
Power Supply Decoupling
Figure 15 shows the power supply connections to the VIC. The V00 pins connect to 5 Vdc and the Vss pins connect to a common grourid. All the V00 pins shoUidbe connected together and all the Vss
pins should be connected together. Decoupling is provided by connecting 1.Ou f capacitors between the V00 and Vss pins as shown on the figure.
vss
VDO
49 48
44
MicroVAX 78516
VECTORED INTERRUPT CONTROLLER
vss
a2----.
ALL CAPACITORS 1 µ f ELECTROLYTIC
Figure 15 ·MicroVAX 78516 Power Supply Decoupling
· Specifications
The mechanical, electrical, and environmental specifications for the VIC are contained in the following paragraphs. The test conditions for the values specified are listed as follows unless specified otherwise.
· Temperature: 70°C · Power supply voltage (V00): 4. 75 V · Ground (V55): 0 V
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Preliminary.
Ah~.MaxillQun &tings Stresses grea~ than the absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may adversely affect the
reliability of the device.
·Storage temperature range: -55°C to 125°C
· Active temperature range: 0°C to 70°C
· Power supply voltage (V00 to Vss): 0 V to 6 V
·Input or output voltage applied: -0.3 V to CVnn +0.3 V)
· Temperature: 0°C to 70°C ·Power supply voltage: 4.75 V to 5.25 V · Power dissipation: 1.0 W (maximum)
de Electrical Characteristics The de input and output parameters for the VIC are listed in Tu.hie 7.
Symbol Vrn VIL
v 1,2 OH
VoL1 IILC
l.:i1c
ICCAc3
Vowm 4
Table 7 ·MicroVAX 1SS16 de Input dd'Obtptlt~tets
Parameter
Test Conditions
Requirements
Min. Max.
High-level
2.0
input voltage
Low-level
.0.8
input voltage
High-level
L:iH =-400 µA
2.4
output voltage
Low-level
loL=2.0 mA
0.4
output voltage
Input leakage
0 < V1~ < cVoo -0.6 V}
20
curren\
Output leakage
0 < V;. < (V00 -0.6 V)
100
current
Active supply
*
current
Open drain
101=6.0 mA
0.4
pulldown
low-level output
voltage
Units
v v v v
A µA mA
v
--
MicroVAX'i8Sl6
Symbol
Vo1002'
Open drain pulldown low-level output voltage
Test Conditions IoL=25 mA
Reqtlttemenf~ · Min. Max.
0.4
Units ·
v
Input capacitance
*
.pF
C..,
Output capacitance
*
pF
*To be determined. 10nly one output may be shorted to either supply rail at one time, and the duration of the short must be less than 2 seconds. 2Tiris specification also applies to the open drain output on IAKEOP 3All outputs floating, all inputs connected to either supply rail. The CLK input is fully swinging between both supply rails at 20 MHz.
·Applies only to the IRQ<3:0>outputs.
sApplies only to the RDY and IAKEON outputs.
ac Electrical Characteristics
Figure 16 shows the input signal and cloc.k signal waveforms arid the parameters are listed in Table 8.
tRIS .- nE·'FALL
90% t0%
CLOCK INPUT
CLK
INPUT SIGNAL
_Figure 16 ·MicroVAX 78516 Input and Clock Signal Timing
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Table 8· MicroVAX 78516 Input and Clock Signal T~ Puameten
Symbol Definition ;
Requirements
Min. Max.
tCPG Input clock high .
5.1 ns 500µs
tcPL Input clock low
,,, '
l:cw Input clock period
5.1 ns 500µs 50 tis·
tRISE Input signal ri5e tpJILL Input signal fall
15 ns2 15 nsz
1To be deterrllµied .
·· . . . .·
2Measured bet~ri 10%. llnd 90% levels.. Appli,~s to'lill input§ ext:ept PIRQ <.15:00>. Maximum
tlUSll and tFALL times for PIRQ < 15 :00 > isS001flS.
·
Figure 17 and 18 show the signal tip.iing and symbols for a regiSter read cycle and register write cycle, respectively, between the MicroVAX CPU and VIC. Figure 19 shows the signal timmg and symbols for an interrupt acknowledge cycle when the VIC responds.with a vector and when the
external device suppliis the vect0r.· F~ <lO' shSWS the t~· and 3y:rribols for a daisychain
configuration when the interrupt priority is not passed to the VIC .and when it is passed to the VIC.
Figure 21 shows the signal timing and symbols for the PIRQinput to IRQ output signal generation.
It also includes the RESET input signal timing. Table 9 lists and defines the symbols and parameters used on the figures. The following notes apply to the table; informati9n.
· (T) =input clQck period (few)
· All units are rtanosec'?nds (ns) except where indi<:;3;ted.
· All times are sp.eci.fiedWith a100-pFcapaeiti~ load on the 9utp~ts,
·
All
time5
are
measured
,,.
'
'
at
the
50
percent
levels
of <
the
wavefolttns
except
whgre
indicated.
-1·101
-····-···-·····-·-~·-----------------~,.---~.......,...,.._. _. . _ _ , . ....JI< O§
-· AS
MicroVAX78si6:
CS<2:0> DAL<15:00>
Figure 17 ·MicroVAX 78516 Register Read Cycle Timing
os.
CSEL
CS<2:0> OAL<15:00>
ADY
Figure 18 ·MicroVAX 78516 Register Write Cyck Timing
1-102
Confidential ~nd Proprietary
...... . · D-1:~~.-~,.,
WR CS<2:0> DAL <15:00>
ROY !AKEi !ACK
OS
VIC SUPPLIES VECTOA
CS<2:0> DAl<1$:00>
XVEC IAKEI IACK
---~__.,~\--~~~~~~~~~~
EXiEANAL m:vice SUPPLIESVEC'i'OA
Figure 19 ·MicroVAX 78516 Interrupt Acknowledge Cycle Timing
1-103
-·
WR
DAL<15:00> IAKEI
iAKEoN'
IAKEOH IAGK
DAISYCHAIN-NO PRIORITY PASSED TO VIC
WA
IAKEI
IAKEON IAKEOH
!ACK
IPL I
~
l!IOMAX
DAISYCHAIN-PRIORITY PASSED TO VIC
Figure 20 ·MicroVAX 78516Daisy9hain Priority Signal Timing
1-104
Con£identialand Proprietary
PWIO<.n>
RESET DAL<15:00;:.
AS
PIRO ASSERTEDIDEASSERTED TOIR'Q.A$SERTEDl06ASSERT·ED
AS _/ rlpRQS}....____ __
J _ _ _ PfRO·{h>
_.,..__._..,_.._~-
PIRO SETUP.
RESET TIMING
Figure 21 · MicroVAX18516PIRQand &sdSit,ti/JlTiming
Confid~ntial and Propri~tary
1-105
-
Prelimirulry
MicroVAX"78516
Table 9 ·MicroVAX 78516 Signal Timing Parameters
Symbol Definition
Requirements Min. Max.
tAJ\SH DAL< 06:00 > hold after AS assertion
0
tAAss DAL< 06:00 > setup to AS assertion
15
tASCS CSEL assertion after AS assertion
1 µs
tASDS DS assertion after AS assertion
0
tASH AS high after deassertion
1.5T
l:csLH CSEL hold after AS deassertion
0
tDRD RDY or XVEC deassertion from DS deassertion
1.5T +45
tDSAS AS deassertion after DS deassertion
0
tnss DS setup before RDY assertion
30
toz
Read data threecstate delay from DS deassertion
30
tENA1 RESET deassertion to VIC enabled internally
5T+250
tlAAS IACK assertion after AS assertion
1.5T+45
tlDAS IACK deassertion after AS deassertion
1.5T+45
tm1m IAKEO/IAKEOP deassertion from AS deassertion
40
tunn.u. IAKEON/IAKEOP delay from IAKEI assertion (IAKEI asserted 25 7.5T or more after AS
tno· .,. IAKEO/IAKEOP delay. from AS assertion (IAKEI asserted less
than 7.5T more after AS
8.5T+25
tllH
IAKEI hold after AS deassertion
0
tPIAD2 PIRQ assertion to IRQ assertion delay
0
100
tPIDD PIRQ deassertion to IRQ deassertion delay (applicable to level
100
triggering only)
t""'"' PIRQ minimum assertion width (applicable to edge triggering 90
only)
tPRQS3 PIRQ setup (proper level/edge) before AS assertion
50
tRDD
tRDDI·in
Read data delay from CSEL assertion
Read data or XVEC delay from iAKEi assertion (IAKEI asserts 7.5T or more after AS)
6.5T 6T
7.5T+25
txnm- Read data or XVEC delay from AS assertion (IAKEI asserted less than 7.5T after AS)
13.5T+25
tRDYD RDY delay from CSEL assertion
8.5T 9.5T +25
1-106
Confidential and Proprietary
-
MicroVAX 78S16
Requirements Min. Max.
tasTL 4 tan
tllYm..m
Minimum RESET low time
RESET assertion to DALs three-state RDY delay from IAKEi assertion (IAKEI asserted 7.5Tor m~re
after AS)
200 µs 8T
tavn1ma. RDY delay from AS assertion (IAKEI asserted less than 7.5T after AS)
100
15 .5T + 25
taros DS deassertion from RDY assertion
0
twcsu CS< 2:0 >, WR hold after AS assertion
0
twcss CS< 2:0 >,WR setup to AS assertion
15
twon Write data delay from CM assertion
3.5T-5
Write data hold after D'S deassertion
20
V1 DD must be greater than or equal to 4.75 V during th~ period.
2Maximum time is 100 ns unless a PIRQ line is asserted durins a register read or an IACK cycle. In these cases the IRQs will be asserted 100 ns after the end ohhe tegister read or IACK cycle.
1This ensures that the PIRQ signal will be recognized if the bus cycle started by the AS signal is a read or interrupt acknowledge cycle. Otherwise the VIC will hot recognize the PIRQ signal until the bus cycle has ended. 4The VIC requires 5T +250 ns after~ is deasserted to complete its internal reset. The AS signal should not be asserted until after this delay.
Mechanical Configuration The MicroVAX 78516 is available as a 68 pin cerquad surface mount package or socket mount package. The physical dimensions of each package is contained in Appendix E.
Confidential and Proprietary
1-107
~. Virtllafthemory DMA (direct memory access) controller, compatible witp VAX and' Mi6-t:>VAX
architectures
. .
.
· Full 32-bit architecture and implementation · Four independently programmable channels
· ),. ,,, ·
· Peak data transfer rate of 10 Mbytesfsec · Maximum DMA transfer length of 1 Gigabyte · Maximum I/O bus ~dress spa~epfl6~S:
· High-speed CMOS technology · Single 5-Vdc power.supply
·n~a.· ...y ..Ju -..o: n
The MicroVAX 78532 MicroDMA controller is a high-performance, dual-ported, four~el virtual memory DMA oontrollet. Figure 1 is a block diagram of the MicroDMA controller.
Figure 1 ·MicroVAX 78.5J2 MicroDMA B¥ick Diagram
It provides two buses, one for the MicroVAX interface and one for the I/O devices. It interfiq:s the 32-bit MicroVAX bus with high-speed peripheral devices or in~nt I/O subsystems on the 8-, 16-, or 32-bit I/O bus. The MicroJ?MA is used for the following applications:
· ForDMA transfers between memory (or devices) on the MicroVAX bus and memory (or devices)
are the J/O bus
· For DMA transfers.between nwll1<lry and'devi¢es -0nthe·I/O:bru11 ·
bus · As a window futo MicroVAX memory for devices on the.I/d
· As an access port to devke,s op the JfObus.fqrthe ¥J(;l'OYA4.
~/
'
- '·
The MicitSDMA is ..a .Virtual Ihemory DM4, .oon~ller with full l/i\f cqtt1patible memciry
management capabilities. It processes address translation for :t>MA transfers so that this function is
transparent to the user. Page table information is accessed from MicroVAX memory and used
directly without alteration. The MicroDMA. also performs data buffering and byte alignment for
transfers between the MicrovAx bus and the I/O bus.
· ·
· Pin and Signal Definitions
The input and output signals and power and ground connections of the Micl'oDMA controller 132pin package are shown in Figure 2. The signals are defined in the following paragraphs in two groups-signals that connect to the MicroVAX bus and signals that connect to the I/O bus. The power and ground connections are defined with the I/O bus signals.
VSSK4
iiM6 iiMi
iiM2 iiiM3 iiiS
iWii ffiii
iAS iDMG iOPiNT Kiili iDiiii iEiii iibV
T<STO
TEST!
Cir Dii
.liiii
iiiiO iiiii ;;;; iiiiii
..A.i
5Miii1
CS2
11$1·
cso iAKED
VSSXl
VODM iREG frRi ifiU iift1
"'
'"
H9 120
'"
"'
123
,,. ,,.
,,.
\IB3
CU{I
VSS!
l0.1.l.00 IDAl.02 tOAl,04': 10.11.1.06 10AL08 !DALIO IDAt12 1DA-U4 VODIQ
NC
\'DOI ID"l01 lbALOO: IO~l.05 !0AL07 IOAL09 1oA-t1 t '1riAL1~. IOALHs°
H)6 100 1Q.t 103 10}· H)I ·tOO- 99 98 97
9!i 94 ·93 9:l 91 90 89' Bi aJ. Sil. B5 84
83
",,'.
73
72
129
!JO
10
.69
MicroVAX 78'32 DMA
67
TOP VIEW
66
66
~
-62 61 60 59 58
54 .'~
l!).2 M ~ro~nnM·unan~mmn·H~nnn~~·u~~.uuu~~
Nii vaR iAW iftOO ROY 6iMi v$$1 DAL.OO -- DAl.02 _tM_U... :·DAula _':"'~- ~i10· ·~_L1l _oA.1..14 C!AL~e VODXl DMGi iiOi ~ ERA itOCi 'vssa VDDI DAI.bi_,' OAUl3. oAi.oto' Di.I.of bAl.09' 111.01" DAl-1'3 DALl6·. VODJQ
VSSll.3
104L25 IOAl.28 IOAUB IOAU9 IOAl.31 OAl..Jl DALJO 0AL29 OAt27 DAL2EI DAUS 0Al24 DAl.23
OAL19 0AL18 041.17 VSSX2
Figuw: 2 ·MicroVAX 78532 Pin Assignments
1-110
Confidential and·Proprietary
-
Preliminary
MicroVAX Bus Inte:rfaee Signals
~'f9llqwing ~s co~ctto the Mict()VAX bus and inclu4Ef. da~ and address lines, btJ.s conuvl
and stat.U$ lines, inte,rl'ljlpt control lines, andaclock input line. The bus signals are summarized in
Table L A more deciiled .deSctlption of the signal Junctions is contained in the following
paragraphs.
'
~52
49-33 10 5
2 9-6 4
Table l· MicroVAX 785,.l.l
Signal ' ' ' Input/Output
. . . .'
DAL< 31:0l);ri.·. input/output
~.·and address''lfueS <31:00>......'.Thne multi-
····~ lines uSed totransfer data and address infor.matfun.betweea,the MicroDMA and devices on the
~AX bus.
Input/output· J\dcb:ess strobe-Asserted to indicate a valid
.. , ,
, r'~sontheDAL<3l:OO> lines.
.'BS'
l)ata 11trobe~Ass~te:~ ~g a reap. ~e to indi~
catt.that the DAL:\t:'Jt:OO> lines are available ·io
·~i~ data and deassertedto indicate that data has
·~~·~v~, . .J\~~ii ·.®r~.. a wri~ . ~e . to
when in~te that data j,$,~ble on th~ tflW~ 31:00.~
' ~~$,and deasserted
the data is to be removed.
BM<3:0>
inpilt
; · -,AS!~d tt> i?di~te ~ refemice in the IfO bus range
·Q~·tc; a ··MicroDMA register define<} by t~e
DAt.< 31:00> lines' :
~' ._. {"-," q'·;. -~'
input/output Byt~ mask-Specifies the bytes of the
> that 31:00 lines co$in valid d11.tl, nAL<
'"'<...~:__·,._._ ~" -':<n.r-- ,-· :,·--· ,_.__. _,- ~--,.,,,;:; ·:<:._,/
inptit:/~tput '·10,atil .b~fr~t·~~i'i.t1'fa ·.·., ·~h~n.. as$~~tt:~·;'. th!!
.· riAX.<31:00 :>
'vets ~ildbdffers ~ enab~.
~-~-----..-.....-'----...-...-"---'--.........,."'"·'"'-.'"""'·......,.·..-....
·.r-··-·,;.·,-.,,,;.._:
..':.»,.-:,: -- _=::-,:··C",<;·:·-.-i'./t~
27
RatdyMVs:ta.~~r~·ta·t·?Sfets·~n
.'1¢¥~ 1~t~.:"l#f~m)~~ ~~op..~
~VJ\X bys. Th~ for the· ·rtion of
~);,us ~.~ust ~t
this signal before ,~~e,tlQg
the cycle and :removing data from the bus.
·
"' .-· }<-;:.· ,. ... ,, >
' ' -. '', ·'i·.'
_._., "' - ' ' ) '
,. --- -
--
26
input/output Error...,..Asserted tt> indicate. an trter condition in
the current MicroVAX cycle.
Confidential and Proprietary
i-111
Pre~···
Pin Signal
> 13-15 cs< 2:0
22-25 IRQ < 3:0 >
29
DMR
20 DMGI
19 iAKEi
16
104 CLKI
103 NC
Input/Output fuput/outpl1t output output input output
input output input
Delinitioo/Function ·
Control stathS-Indicatesthe type of cycl! !king
performed on the MicroVAXbus.
·
Interrupt request-Interrupt request lines for the devices on the MicroVAX bus that are maskahle.
DMA request-Asserted to indicate thata device on
the MkroVAX bus is. requesting control of the MicroVAX bus. · ·
DMA grant. input-Asserted to cause the MicroDMA controller to become bus master of the MicroVAX bus and perform a DMA transfei:
DMA grant output-Used only with systems having more than one MicroDMA controllers. Asserted when a DMA request· is to be granted to another contfuller in the daisychain.
Interrupt acknOW-ledge enable in-Asserted to allow the MicroDMA to respond to a MicroVAX interrupt acknowledge.
Interrupt acknowledge enable out-Asserted when an interrupt acknowledge is to be processed by another device in the interrupt daisychain.
Oock in-A TTL clock input used for timing.
No connection.
MicroVAX Bus Interface LiDes Data and Ad<kess (DAL<31:00>)-These are time-multiplexed bidirectional lines used to transfer data and address information between the MicroDMA controller and other MicroVAX bus
devices such as MicroVAX CPU and MicroVAX memory. The strobe signals AS and DS determine
whether data or address information is tran.sferred.
Address Suobe (AS)-The falling edge of the AS signal indicates that lines DAL< 31:00 > contain ~ valic;{ address. On the falling edge of AS, the MicroDMA controller latches the .address and inteqirets it as. a phy:sical address. If the CSL line is als6 asserted, the CPU is performing a MicroDMA access op~ration. This access could be to a MicroDMA register.or to a location in I/O bus memory space. Refer to the Access Operations section.
1£ theMicroDMA controller is bus rilastet; the AS line indicates that lines DAL< 29:02 >) contain a valid MicroVAX physidd memory address. Thb DAL<31:30> lines contain a 1 and a 0, respectiVc:ly.
The falling edge ofthe AS signal also mdicates that the information is valid on the BM< 3:0 > ,
CS<2:0>, and WR lines.
1-112
Confidential and Proprietarv
Preliminary
Data Sttolte (DS):.._This sigpal ~pes tinting ~ftl'lt#p~~· the ~tt\ tritnSfer portion of a read
or write cycle. ·~.a read cycle, the falling ·edge of DS signal indieates~hat.the DAL< 31;00.>:
lines are available'to receive data and the rising edge indicates that the data ill' about to be latd.1~.
During a write cycle, the falling edge of the D'S signal indica~ that~ta is pl'CSefi.t on the
DAL< 31:00 > lines and th.e: rising edge indkates that the data is about to be J!lemoved.
of Byte Masks (BM<J:IJ>.)...:..These sign8I!l spedly whicli Wf.eS the ~<31:00:> lines~ data validduring the curtcnt transfet During a wtite'C}'de,.litlts iW< 3:i}> specify which byres of
the DAL< 31:.00 :> Ur!.~~ co~ y~d data·' :PU#11g a re,-4 .stfl~· lines B.~,:<.J:ti.> specify which
bytes ofthe DAL.~.31;00> .lines must be supplied with ~ data by an eirternal device. Th,
information on lines.J3M<.3:0>··is valid 011the··fillling·~·.of the·AS'.sig1JaLThebyte mask
assignments are 'shownin Table 2.
· ·
Byte Mask line
>
,., ··,
DAL<31:24'>
DAL<23:16>
DAL<l.5:08>
DAL<07:0tb
Write {Wi)-This signal specifies the direction oif data tr$Sfer on lines DAL<.31:00> for the
current bus cycle. When a5serted, the cW.TefrtSUS ~ter ~~~.®.the~.<.3:~00,~..~ during the data transfer portion ofthe cycle. When \im'.is nousserted, an external deVice supplies the data during the data transfer pardon of the cycle or lines DAL< 31:00> do not contain data. The wtl signal may be used by external logic to control the ~j~9··of.I>M- ~u~.~~·· ~ WRipput4validonme~~eo~Jhe~si&tW· .· ··:·<'i·;:t· :· ' · · · ' · ·
J>ata,JJ· . ~t~E>~ThU ~,~.~,~~m.t~,~~.by ~rQal ~'to
control the DAL<:ll.;00> ~ ~~V!!'~..~-~M,l\isbus~ter,it~s
the DBE signal to enable the buffers or transceivers and deastie$ 'mm to disable them.
Ready (li}Y)-This signal is asserted by external logic to indicate that it will complete the current bus cycle. Whennot.asserted,.it e.xtends.the.~bus.cyplefox a slower memory.or peripheral device. The RDY otl!im:sPal rtmst;:be~'tb~-;tht'.MMtbus cyde'.
Bus Ertor <EiOO-Thls siPu is as~ l>y~.~;J logk to fudicate ~tan error~
withthecurrcntbuscycle,suchasbustimeout6rparityettc)J;'ilasoceuttedandtoe1'Jd.the~
bus cycle. The ERR or ROY signal must be assert:ed to endthe cun-ent bus cycle.If tJie Micro~ is bus master and detects the assertion of tIW ~ signal, it ends the bus cycle, interrupts ~~
MicroVAX CPU (ifenabled), and reoonilsthe error. The MicroDMA asserts the.ERi signal i£ an I/O
bus error (iElm) signal is detected during an lltcess transfer.
· ·
Control Status (CS< 2:0 >)-The IW~DMA ·uses these lines together with the WR ~;(to
· recognire and respond to the type·of bus cycle currently·inprogress. Table 3 lists the bus cycle
selections.
1-113
-
Preliminary·.
MicroVMf1s5J2
Write
ft
CS line
2
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
*Used by MicroDMA as bus master.
Bus C:xcJ.e Type ·
0
0
reserved
1
reserved
0
reserved
1
interrupt acknowledge
0
read instruction
1
read lock*
0
read data, modify intent
1
read data, no modify intent*
0
reserved
1
reserved
0
reserved
1
reserved
0
reserved
1
write unlock*
0
reserved
l
write*
MicroVAX Bus Interrupt Control
Interrupt Request (IRQ < 3:0 >)-These lines are used by the MicroDMA to interrupt the
MicroVAX CPU: The vectors associated with these interrupts are provided to the MicroDMA by · MicroVAX system software. The interrupt request assignments are listed fo Table 4.
IRQLine
Table 4' MicroVAX 78532 Interrupt Request A.signments Interrupt Level .IPL 17 . IPL 16 IPL 15 IPL 14
1-114
Confidential and Proprietary
·····
MicroVAX BasDMA~,
DMA·lteqaest<fiiil.).;....'.lliissigrial,iJcassertedbJ,tbeMkroDMA controller to initiate a DMA
the .to ttansfet over the Mi~VAX 'bus~ On t;he ~;ful,t;wing the assertion of the mil signal, the
MicroVAX CPU disables the bus and assert;s,dle:IM;eSignal. T1ii$ allows. ~crooMA take
c()ntrQf-0f th~ J.,us. Mer the ~DM:i\ h~ ~
th!! . · fet,it deasseH;~ the D1iJ
. ·. sMigincarol DtoMreAtuornnlyc.oifn~t@IJoMfAtheen~ausb~loe~beito~.f"~~;>~nvl· ~s·. .~~·.. h. e. ens..ecta.n.b.e
as~ .,..
by
the
.
Grant DMA..
Input {imGl)-Wberi ~,·'ijle '~I)M.N>¢t)~J1er takes control of the··
MiciOVAX bus for a.DMA ~ ~& J.irlti it'CW~ in·a d.ii~yehain.if more than one DMA
device isin a system. TheMici'<WJ\X'Dm~~·~~ to the···~ line ofthe highest priority
wfndi DMA device: If this MictoDMA ~ ~rnof ~ a DMA reqi.;teSt pending, it asserts its
~line,
coft1leets to the ll14ifl]ine!df.·$t·~tDMA device. A MicroDMA controller
cannot perforni·a DMA thUisfer rutthe Mi~~~tintlHt$ j)MGI line is asserted.
DMAGlantOaq,ut!JiMGO>-~~is~:~~~.~~~.:thanone n~·~~alld.
is asserted when a DMA request is to'be ~ toa·~ priority OMA device in the daisychain.
. .pn bOth the ~VAX bl.JS
CPU and MicroVAJtFPU. .
·I/0 Bas Inwf:ace Signals
The. lJO bus intc:rface lines con!lect to the.l/Q~ d~s !l:P9. co~st (lf data and ~s li.nces .alld
contmllines,Thi: bus.si,gnais.~.~i*l,~le2. A ~1~d descriptiol:)(~fthe sigul
functionds contained~ the f~~pht
·· '
<:onfidential and Proprietary
1-115
______________ . ,
'£~-----
67-82 85-101
lm~m
IDAL< 31:00> input/butput
rrR<3:o> input
· Data and address lihes < 31:00 >:....Time multiplexed lines ·used to tranSfer data and .. address. information
betweertthe MicroDMA and.devices an ·the f/Obus;
I/0 transfer reque~t ~3:0>-ASSertedto indi~ate
that a device on the J/O bu$ requires servke. :c.JneS
ITR<3:0>
respectively.
corresp..onds
to
cll.iinpel
3 VJOrigh . . ..
d,
.
106-109 IIR<J:O>
125
124 ·ii'>iIB 121-118 IBM<3:0>
123 ·m
131 130
input
J/O interrupt request-Interrupt request lines for l/0
bu1;idevices. ·Lines lIR < 3~0> corresponds to dta.nnel
3 throughO, respectively. Typically uSed to terminate a
DMA .transfer.
input/output I/O address strobe-Asserted to indicate that the
IDAL < 31:00 > lines contain .valid data...·
input/output
I/O data strobe'"""'."Asserted during. a re:acl. cyi;k to mdi~
cate that th(! IDAL<31:00> lines are availab_k to
receive data and deas~ to indicate that die d~t.l. has
been received. As~ed during a write cycle to indicate
that data is ~nt on the ll)AL<31:00> ll,nes at¥f
deasserted to indicate,thatdat1;1 is to be.J.1!m.o:ved..
input/output I/O data buffer enable.:....Assetted to .'enable the
IDAL< 31:00 > transceivers.
input/output input/output
I/O byte mask-Specifies the bytes on the
IDAL < 31:00 > lines that contain valid data.
cata 'I/O write-Specifies the direction of 'trttnSfer on
·. the IDAL< 31:00> lines. Asserted to indicate that the current bus master will be the source of the data. Can be used to control the directiop. of thelDAL<.31:00.:> lines.
inpllt/output
I/Oready..;..Used to synchronize datatransfers'between devices operating at different transfer rates onthe·I/O bus. The current bus master must wait for the assertion of this line before terminating the cycle and removing theoota.
input/output
1/0 error-Asserted to indicate an I/O bus error condition. In the window mode, it also may indicate a MicroVAX bus error.
129
input/output 1/0 DMA request-Asserted to indicate that a device
on the I/O bus is requesting mastership of the 1/0 bus.
The transfer cowd be 1/0 DMA, DMA, or I/O access.
1-116
Confidential and Proprietary
-
Pm.····~
21
VBR
11
VBG
Preliminary
ipput/output input output
1/0 DMA gtllD.t-Asserted to ~ tl:taf the JJO;bus
has been releru1ed by the currentJJO !;nq;. ~to allow
aDMAt~erto~
·
·
MicroVAXbus.~Causes:· the·· ·~c:roDMA ·to
request the·~ ·of the MktoVAX bus;·'l'ypically'used
wbet\pe~·~·~·tblt)·
114 nmG·
input
· ·lt().·~.~~~~~"by, t~LJfP.· p~es~·k,
~~Mi~l!IA~·
'
127 IOPIN't ; output
· 1/b' '~~~r·~~:Aisei~' ~Wn··~ny···nMA
channdiniua ·.·.······"····· t~a#,yar>~sot.
~~~~--.........--~--__,..~..,......-.,.------
28
'iil)Q{
input:
.·~·~·
,tra.~.;
·. ·: .~~il\)~~~}P
..J,n~ ~e. ~~·it,~~
·..
l15
10, lmT
input
Jjo ·~~As~·tt> enatik' ~'~fiMA ·t:o
· ~ t1ie mastut0{:.lhe ItDbus hy.&fau}t;:· · ·
· ., .· ' ,; ··. ,,;i;,:1*-~.:_,.,;._ ' )' -
' ' ' - ' ' ;,
1,132 Test<iltO:> input
U8 ICLKO
output
32,101 V00 18,50, 84,116
31,102 V58 17,51 83,117 30
input
~st+~· Wil·t5tirtg m.e,MiaQI)MA;oontn:i.Uer during~·. \'Ii0.i'.'
1/0 clock output---A clock pulse output s.t one-fourth of the CLKI frequency.
I/O Data aDd Address
.
J/O Dataand Address Bds (IDAL<~l~OO·>)-TheselinesiAre tlme-mult~andh~onal
and are used to tmn$i'er data and address ~matio.o betWeen the..~OMA controll~ ai:,id
m ms' ·devices or controllers on the IfO bus: The1lines can.~ pro~fot 8-, 16·, o.t-J2"bit data
widths'. 'fhe; strobe s~als and cdetermine wbli:ther the .bus cames data or ~
information.
1-117
-
PreliminBy
MicroVAX '185'.J2.
1/0 Address Strobe (ii\S)-1£ the l;v,li~.M4.is ~Ull·.tnast~;Jt USe$ ~e I.AS' signal ioin,dicate that
the IDAL<31:00> lines contain valid a:ddress informatioa and that the information on
IBM< 3:0 > and iWJ is also \Jalid. The iASline :ifose<lby exterrutl cirtuits to latch tfil~ address and
to qualify the control signals.
Ifthe MicroDMA is not bus mastei; the falling edge of the IAS signal causes the MicroDMA to latch the ·address and control. information to determine whether a window transfer is indicated. If a
window transfer is not specified, the MicroDMA does not participate in the cycle. If it is·specified,
the MicroDMA participates in the cycle by performing mapping (if required) and by asserting the
IRDY line when the transfer is complete.
an I/O Data Strobe (ii)J}-This signal provides timing information for the data transfer portion of
I/O bus read or write cycle. During a read cycle, the faJling edge of the IDS signal indicates that the
MictoDMA is ready to receive data andthe rising edge indicates that the data has been latched by
the MicroDMA and can be removed. During a write cycle, the falling edge of the IDS signal
mdi.cates that the MicroDMA h~ placed valid data on the IDAL lines and the rising edge indicate.s
that the data ~s. about to be retn6ved.
1/0 Byte Masks (lBM<):O>)--These signals indicate which bytes of the IDAL<31:00> lines
are \Jalid during the current data transfer: During a write cycle, the IBM< 3:0 > lines specify the
bytes that contain valid data fof writing: During a read cycle, the IBM< .3:0 > lines specify the
DAL< .31:00 > lines that must be supplied with valid data by an external device. The information
on the fflM < 3:0 < lines is valid on the falling edge ofthe iAS signal.
The validity of the bytes also depends on the width of the current data transfer. If the current
transfer isl byte }Vi.qe, the information on the IBM< 3:0 > lines is not significant because a byte is transferred orilf on the IDAL<07:00> lines. H the current transfer is 2 bytes wide, the
IBM<):O> lines specify whether lines IDAL< 15:08> and/or IDAL<07:00> contain valid
information. If the,cilrrent transfer is 4 bytes wide, the valid bytes are specified hy IBM< 3:0>. Table 6 lists the I/O bus byte mask assignments.
Table 6 ·MicroVAX 78.5)2 1/0 Bus Byte Mask Assignments
1/0 Byte Mask Line Valid Data
IBMJ
IDAL<31:24>
IDAL<2.3:16>
IDAL< 15:08>
IDAL<07:00>
1/0 Write (iWR)-This signal specifies the direction of data transfer on the IDAL < .31:00> lines
forthecilrreb.t·bus cycle. When the !WR signal is asserted, the current·bus masterdrives th~ lines
during the data trahsfet·portion of the cyele;·When the IWR signal is not asserted, an external .· device supplies the data during the data transfer portion of the cycle or the lines are idle. This signal
< maybe used by external logic td controlthe direction 0£ the IDAL 31:00> transceivers, The fWR
information is valid on the falling edge of the IA'S signal.
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-
I/ODataB1dfer.Bnahle (miE)_,This signal may beuad With the,:tWR s~ toamtrolextermd IDAL<'.'31:00> ~vers and buffers. When asserted, it enables a tnmsceiver ot buffer and when not userted, the O\ltputs of the transceiver or:buffer ate disabled.
'f/O Ready (ilil}Y)-During I/O bus cycle data transfer, the bus master must wBit fur the assertion
of this signalbefore tenili-.ting the.cuf'rent cycle. and:latclamg.(tifa.'.e:~daui·.from,the·nus.
VO····Ert:or ·(Mll)--This signal indica~ t·~bf15.el~ ci:mdltiOBtti the ~t1·bUs
~ter> If the MicroDMAdetedS·the.·a&serttonofWs 1Sipi!i~~ it '.OMA ttal1Sf~lt ·~tM
aBfluUelnst·i· bgusn'.·acylehde~·
mct·interruJ>t&'theMiclnv.AX1.~l:PU'(if~~):.'If
11 Windo\v transfer; it~Sedi mltR 50 that ~bus
·e·r~r·oMfiiestiblD~M:f.tAf·'·id:e&mtchi$e:ttH/be
processor.
1/0:Btls·lla1a 1iaosfet Control
~......&om·'f/O·Peftee·(iiJi< '.liO>)-~~iS~~atJ_·Jl)bus;~;that
~ DMAservice or by an ~d~1-t·,~~5r ~.~~;. ~Jitlb·is
~ed·to.~:cbannel. Sim~~~·.·~.~~~·to~·cbannel~
with rrRO' at higbest·priotity and Im· at ~t.;.~ ~~ ~ to:the aSsettiqnpi a
line by performing a DMA ttansfer if the channel is in DMA $'.Ide or a window transfot.if 'the
channel is in window mode. The MicroDMA does not admpw~ these sj~;.~ ~~
. performed auto~tkally. ~.~lnypl~diJl.t~ ~.~$$ ~~# fli.~~
device~ $\Nlclaipwlqpient)$~·
.
Interrupt Request from 1/0 Device (ttf<):6>)-These ~ are asserte4.by a:~~ on the
I/O:htts tointemtpl,thet&~~«O~.~etsa~.~.e~~~~lf a~l:~~
w}u,:nthe~o~. .ljtlciis~1 :the~t~i~~~Y~~~~
channel is disabled .~··.f<>r the~pt.~.\~;*.1:~-·~·~. ~a~. ·~
if;rterrupt. conditio11thatcausedtheline~be~~·fr1·J>e.'~~t~.~~.c:ian,he
enabled again.
I/O BusDMACOnttol
JfO OMA' ~t (16111)".'""'This signal is 8$serted bf a~ti'1} bus m~tet to requd$tl/0 bu8
ownership. When the MicrdDMl\is'l:He l:lefm!t7bus;·~~(~R mput·i8 ~· t~
IDMRisaninputsigrtalthatistyt>idUyaa~·~l/Op~s$0torfDMA~'ontheI/Obus:
When the MicroDMA is not the default lfus i::mtSter, it ass.eristhe ·im;m line to use the bus for a local memory transfer or a transfer to a peripheral register.
1/0 DMA Grant (1i)im}-This signal is asserted by the CW'tent bus·:master.in r¢$1)0rlse to the
IDMR signal. It indicates that the bus master has :released the l/Obusand that·ws ~bip.rnay
now be assumed by another device.
.JM/Oklo~ .V'AX BusCo~nti tolt.
. ...·..
(ftl)-This
.sigri.a.·.I·..~.....a·. sse. t·.'ted.··.P.Y·.
~·.
. . I(Q
p<l;fJcessor
to
¢0ntrol
the
the Micro\ri« blls when· ~ertniJJg a w~ ~ It 'l~ ~ t0 ~ S: &snflid:~
accesses the ~croVAX CPU
the 1/0 bus at ~ ~:l(Q l/C.f~~S()r ~ to. perfoptt a.~
transfer...When .userted, .the,MlcroDMf\. ~f$ ~rttrof<${·~ ·~~ bus;.and as.~~ the
~ sigiiat~n contt0I of theMii:roVAX ~·~;g1'1lft~··'rl:i~YO prot;ess~r ~Uldd~rt the
VBif signal as soon as windowttilri$£er is coinpl~ m~rdet ttfPresel'Ve the s~ t~pnt.
MicroVAX Bos Grant (V'im}-This ~nal is asserted by the MicroDMA in respopse to ~
assertion of the Vim signal. It informs an 1/0 processor that control of the MicroVAX bus has been
acquired and that the· 1/0 processor may proceed with a window transfer.
I/OBusB.epter.Access(iillG)...;.;.This signalis assertfed b,y anl./O pro&oorthaccess·aMk:roDMA
internal: regilltet ·It is asserted~uring the address portion of'an I/O bus cycle to indicate that t:he information on the IDAL < 08:00 > lines iiliould be interpreted as a register address; It should be
deasserted at the ~ of the cycle~
I/O Piocessor lntarupt (iOPINT)..,..Thi& signal is asserted when any of:the MicroDMA channels initiates an interrupt to an 1/0 pl'OCesso~ Because mo~ than on~.channel may interrupt atcthe same
time, t:h,e J/O processor .must poll .all the chrumels.to.determine the.highest priority intert1Jpt.·1'he I/O processor software deasserts this ~·by setting the -ENABLE bit pr clearing the.poNE bit
of the channel control register of t!:ie interrupting channel. or by redirecting the in.terrupt .to
the MicroVAX CPU.
MicroVAX Bus Lock (ILOCK)-'This signal is asserted by an I/O processor to create Jocked
MicroVAX bus cycles during a window reference. During window read and write aperaticins, asserting this signal·causes MicroVAX memor1 read ahd write operations to be.~d .with.·a
code of 101 on lines CS <2:0 > (read lock or write unlock). The MicroDMA continues to assert ·the
DMR linewhile the~ signal is asserted, but does l:lOt assert the read lock cc.Ide while accessing
the page table information required by the willdow access. Itci0es not check.the sequence ofreads
and writes.·
Miscellaneous Signals
i/O Btls ~ (IM:A,gfER)~When asserted, the MicroDMA becomes bus master ofthe 1/0 bus
by default and it responds to the assertion of the IDMR signal by asserting the IDMG line and by
releasing the 1/0 bus.
·
CbiP Select (Cfi;)-This signal is used by the external logic to allow.the MicroVAX CPU to access
the 1/0 btts or a MiciODMA faternal register. When· asserted, the information on the
DAI.< 23:00 > lines is interpreted as an I/Obus physical address if lines DAL< 23 :09 > are not all
ieros or the information on lines DAI.< 08:00 > are interpreted as an internal register 'address if
the DAl.<23:09> lines are all zeros.
Reset (RESET)-When asserted, this signal sets the MicroDMA to a specified.initial state.
Test (TEST <1:0>)-Reserved for ~ufacturing use. ,U Test01is asserted, all outputs will.~
forced to a high-impedance state. Test < 1:0 > contains an internal pull-down circuit:
·
1/0 Bus Oock Output (ICLKO)-Aclock output at one-fourth of the CLKifrequency.
Power and Ground Connections Voltage (V00)-5,Vde. power supply.
Gtmmd· CVss)-Ground reference.
· MicroDMA Controller Operation
The Micrp.QMA controller is a multipurpose interface that can be used ~ween .the MiqoVJJc
processor at;~ a compatible 32~bit J/O bus for peripheral devices Of controllers. The MicroDM.4 has
fou,r iodependently programmable. channels throitgh which DMA, wind9w, and I/O bus data
four trs.psfers can be per£orined..'I'lle chinuels. are ~!!Signed a Hxed priodty wi~h chan~ 0 having
the ~i;t prioP,ty. Devi~ .that ttl!Nfer.4~ta at th~ highest, ra~s or met:norr transfeq ~hottlci be
allow assign~(i the l~t priority chaµnels to
the slower deviq!s to ac<;ess,the bu,s. This ~on
of of bMriiecrfolyDMdeAsc.ribes the chara.cter.i. stics t,hese transfe.rs and the othe. r ma. .jor 'functio11s . the
1-120
Confidential and Proprietary
. MicrovAl<
d'IJ'
Figure 3 ·MicroVAX 78JJ2Mllfi,tfMAS:,sfeinin~acin:g
'fypef of DMATtansfets The primacy function of thet.MicraIDMAistopmfo~bto&.~·UMA.~~~arnwnts of dataclltl bettaruferad1between.a ~ce odntelligent l,lOSUbsys~mon theJ/0 bu-Sto aldeviee or memory on MicroVAX bus without CPU intervention. DMA transfers may als<>involve ~
~tj.on,.<lata~nt,ap.d4ata,bt!J~.
\'findow!T~l~ devices. on .theJJG busciut'~,,·:~iw:indows>:'.in the MiE1,liQVAX
memory. Window transfers allow the devices to access buffers a.pd to operate from work queuedri
~ofY· The !Qca® l!lllil.~of i\·wjaj<>'W;~q¢~·~,t~.~l'.;~~~~jo~HW~vi ~~~
~yinvolveaddres~~sh\tion~datl'J~g~~t1
· ·;::·,
· ·
T/O DM.t\ .1NMfers.;...'fheMroroDMA fontrollf:t'<:at111:~brm,tilocal J/O·.bus ~ .ttttnsfers ·
independe.ntlyof~het activities that· rnay~~.ihe~AXJ~ni. ::rlwifO DMA ~
allows the I/O bus memory to be used as a large bufferfordata tat'!: s~..Xhel/Qbttsmemmy
can be filled by a channel in 1/0DMA mode while another channelin DMA mode transfers the data to MicroVAX memory. 1/0 DMA transfers do not involve address translation or data realigrunent.
Access Operations The MicroDMA controller allows the MicroVAX CPU to access memory and devices on thel/0 bus similarly to devices directly connected to the MicroVAX bus. These access operations are performed by the user application and define a region of MicroVAX physical address space as an 1/0 bus access range. When a range is referenced, an access to one or more equivalent locations on the 1/0 bus is performed. Access operations may occur in parallel with channel operations such as DMA, window and 1/0 DMA transfers. During acce$S operations, data packing and unpacking is performed and address translation or realignment is not performed.
MicroVAX'.78512
Data Realignment.-:Data iii Mi<;roVAX memory: orT/O iriemofy can be accessed on arbitrary byte boundaries. The re#ignmentcanoccur as part of a lDMA or window transfer. During realignment a data byte, word, or longword on one bus. is .buffered by the MicroDMA and shifted for proper ~nment on the other bus.
Data Buffering-The MicioDMA provides a buffer oftwo longwords per channd to improve DMA transfer speed and efficiC,ncy. The data from a device on one bus can be read and buffered until the· device on the other bus is ready to accept the data, The buffer can also be tJSed to convert bytes and words from the J/O bus into longword data for the MicroVAX bus.. This improves the speed of MicroVAX bus transfers. During realignment, the buffer is used to hold data temporarily that is to be realigned.
Data Packing and Unpacking-Data packing and unpacking is used for byte and word DM:A transfers and access operations. It asembles or separates data between the MicroVAX and I/O bus. Data packing is performed to arrange byte or word data into longwords for the MicroVAX bus. Data unpacking separates longwords into bytes and words for the I/O bus.
Address Translation The MicroDMA performs virtual to physical address translation for DMA and window transfers if mapping is enabled for the channel involved i.n the transfer. The MicroDMA uses page table information stored in MicroVAX memory and maintained by MicroVAX system software. This information includes the system page table (a collection of page table entries contiguous in physical memory), the process page tables (a collection of page table entries contiguous in virtual memory), and the global page table used to describe shared pages.
Bus Interfacing The MicroDMA controller prevents different activities between the buses from interfering with each other. The controller appears as a DMA peripheral device on the MicroVAX bus. It requests and relinquishes the bus through the DMA request and grant logic. The bus interface. uses signals with the same timing characteristics as those used· for any· other MicroVAX bus device. such as MicroVAX.memory.
The controller appears as an I/O processor or CPU on the J/O ·bus. The I/O bus supports the simultaneous use of8.; 16-, and 32-bit devices and has an interfacing protocol simifar to :that of the MicroVAX bus.
The MicroDMA may operate as a master or a slave on either bus. Therefore, the bus controhignal AS (address strobe), for example, can be used as an input or output. Thble 7 summarizes the MicroDMA operations. It specifies operations for which the MicroDMA is bus master and shows the source and destinationbuses for each. MicroDMA internal registers can be accessed from either the MicroVAX bus or I/O bus.
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Preliminary
MicroVAX 78532
Table 7 ·MicroVAX 78S32 Opeation Summary
Bus Operation Master
Source Bus
Destination Address
Bus
Translation
DMA Transfer
MicroDMA MicroVAX/IO IO/MicroVAX Yes
Window Transfer IOP*
IO/MicroVAX MicroVAX/IO Tus
I/ODMA
Transfer MicroDMA IO
IO
No
Access Operation MicroVAX MicroVAX/IO IO/MicroVAX No
*!OP= Intelligent 1/0 device or I/O processor.
Data Alignment Yes Yes No No
Data Packing Yes No No ':res
Registers
The MicroDMA controller contains 63 byte addressable, user-accessible registers. The MicroDMA
controller contains ·one set of global registers that define$ the Overall. state of the MicroDMA controller and four sets of channel registers that define the stat~ ofeach channel. The registers rnay be accessed from either the MicroVAX bus or the I/O.bus.·
The registers occupy a 512-byte region in MicroVAX 1/0 address space. The base address of this region is defined by the user and must begin on a 16-MbYte boundary. The user's application decodes lines DAL< 31:00 > and.asserts the cSL line when an ~.ddress in the register region is referenced. When CSL is asserted, the information on the DAL< 08:00 > lines is interpreted as a register address if the DAL<23:09> lines are all zeros. HDAL<23:09> are not all zeros, the information on DAL < 23:00 > is interpreted as an I/O bus address and an 1/0 access cycle will be performed. (Refer to Access Operations.) The addresses associated with the global n:gisters are
listed in Table 8. Table 9 lists the addresses assigned to the channel registers.
Table 8 ·MicroVAX 78532.GJobaJ Registers .Addiess Assignments
Address* (hexadecimal)
Mnemonic
Read/Write
(R/W)
Description
000
DGCTL
RW
Global ControlRegister
004
DSBR
RW
System Base Register
008
DGBR
RW
Global Base Register
OOC-03C
Reserved
*Register addresses must appear on the DAL< 08 :00 > or IDAL <::: 08:00 > lines. References to reserved addresses will cause unpredictable results. Some registers have more than one function
depending on the current operational mode of the MicroDMA controller.
Confidentialand Proprietary
1-12.3
-
Preliminary
MicroVAX 78532
Table 9 · Mict0VAX 78532 Channel Regist;ef11 Address Assignments
Address*
Read/Write
CbO Cbt Cb2 Ch.3 Mnemonic+ R/W
Register:j:
040 080 oco 100 DCCTLx RW
DMA Channel Control
044 084 OC4 104
Reserved
048 088 OC8 108 DCINTx RW
04C 08C occ lOC DCIOBAx RW
04C 08C occ lOC DCIDSx RW
DMA Channel Interrupt Vector DMA 1/0 Base Address
DMA IfO Source Address
050 090 ODO 110 DCIBCx RW
DMA Initial Byte Count
050 090 ODO 110 DCWMx RW
Window Mask (window)
054 094 OD4 114 DCBOx RW
Byte Offset (mapping on)
054 094 OD4 114 DCUPAx RW
MicroVAX Physical Address (no map)
058 098 OD8 118 DCSPTEx RW
SVAPTE Register (DMA, window)
058 098 OD8 118 DCIDDx RW
I/O DMA Destination Address
060 OAO OEO 120 DCCSVx R
Current System Virtual Address of PTE
064 OA4 OE4 124 DCIOAx R
Current 1/0 Bus Address
068 OA8 OE8 128 DCBCx R
Current Byte Count
06C OAC OEC 12C DCPTEx R
Current Page Table Entry
070 OBO OFO 130 DCPAx R
Current Physical Address
074 OB4 OF4 134
Reserved
078 OBS OF8 138
Reserved
07C OBC OFC 13C
Reserved
*Hexadecimal notation. Register addresses must appear on the DAL< 08:00 > or IDAL < 08:00 ~
lines. References to reserved addresses will cause unpredictable results.
+x = Register designations 0, 1, 2, or 3, depending on channel number.
:j:Some registers have more than one function depeµding on the current operational mode of the MicroDMA controller.
To access a register from the 1/0 bus, the user's application decodes IDAL <23:00> and asserts the IREG signal to indicate a register access. The MicroDMA interprets the IDAL<08:00>
information as a register address. The I/O bus write access to the registersis controlled by bit 10 in
theDGCTL register, the value of which is usually determined by MicroVAX system software.
DMA Global Control Register-The DMA global control register (DGCTL) is used to control,
configure, and detern'line the global status for the MicroDMA controller. The format of the register information is shown in Figure 4 and defined in TableJO.
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Preliminary
MicroVAX 71:51'2
rr: ::::: n): I .. OEAO .
H:::: ++ ~mrn 1: : : :
I IOWE
I I' O!i'N RESET
MWE
EBLIM
Figure 4 ·MicroVAX 78532 DMA Global Control Register Format
Bit 31 30:24 23:12 11
10 9:5 4 :3
2 l 0
Table 10 · MicroVAX 78532 Global Control Register Descri1,>tion
Description
DEAD (Deadlock)-Aread~only bit that is set to indicate that a deadlock situation
existed in a previous I/O bus access operation. Oeared during a reset operation or
by writing a one to this bit.
Not used (read as zeros).
VID (Version identificatlon)-A read-only field that contains.the version number
9iiJ?. of the MicroDMA chip. For the initial \rersio11 ()f this the tiµttlbet is 00000001.
MWE (Mai.ntellance '1'11'ite en@le~:--Settlna ~s read/wri~ bit enables writing to any register including th~ read-only regis~rs.Jtis.itite~ for diagnostic and manufacturing test usage only. The status/error bits cannot .be set when this bit is set. Oeared during a reset operation.
IOWE (I/O bus register write enable)-A read/write bit set to enable an I/O device to write data to a channel register. When cleared, a write to external ~gisters will be ignored. Cl~ during a reset o~tion.
BUM (Burst limit)-Specifies the m~imum letigtQ (in.{)µs cycles) of a DMA bµrst
on the MicroVAX bus when EBLlM (bit l) is set·. Cleared d,µring a reset operation.
WID fWidth)-A read/write flt~fd tl'iat specifies the'data width of l/O bus access
operations as follows. These bits itte cleared. duting a re5et;o1'Jeradon.
WID Bits
04 03
Data Wldth
0
0
lbyte
0
1
lbyte
l
0
2 bytes
1
l
4 bytes
DEN (DMA enable)-A read/write bit that must be set to allow the MicroDMA
controller to perform DMA transfers on the MicroVAX bus. Clearing this bit prevents the MicroDMA ft?lll~Ss~~ting)'.5JVM. Cleared duringa ,reset operation.
EBLIM (Enable burst limit)-A read/write bit. When set~ BLJM (bits 9:5) defi11e
the maximum length of a DMA burst. When. clear, the DMA burst length is
unlimitec1. Cleared during a reset operation.
set to RESET-A read/write bit thatis
initiatea: reset operation that forces the
MicroDMA to a known foitial state. Settmg'th:is bit has the same effect as asserting
the RESET input.
. .
.
.
ConfJdential and Proprietary
1-125
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Preliminary1
MicroVAX '78.532
DMA System Ba$e Register...;.The DMA system base register (DSBR) is used in address translation and contains a copy of MicroVAX system base register which is the physical address of the base of the system page table. Refer to MicroVAX 78032 CPU in this databook for more detailed information on the MicroVAX system base register: The DSBR must be loaded by MicroVAX system software before any address translation occurs so that MicroVAX memory will not be corrupted. The format of the register information is shown in Figure 5 and defined in Table 11.
Bits
31:30 29:02
01:00
Figure 5 ·MicroVAX 78532 DMA System Base Register Format
Table 11 · MiCl'OVAX 78532 DMA System Base :fteaister Description
Description
Not used (read as zeros).
SBR (System base register)-Contains the physical longword address of the system page table. The same as bits 29:02 of the MicroVAX system base register. Not used (read as zeros).
DMA Global Base Register.......The DMA global base register (DGBR) contains a copy of the information in the MicroVAX global base register. It is used by the MicroDMA during virtual-tophysical address translation to locate the global page table that describes the shared pages in system virtual memory. The register must be loaded by MicroVAX system software before any virtual DMA activity so that MicroVAX memory will not be corrupted. The format of the register information is shown in Figure 6 and defined in Table 12.
Bits 31:30 29:02
01:00
1-126
Figure 6 ·MicroVAX 78532 DMA Global Base Register Format
Table 12 ·MicroVAX 78532 DMA Global Base Register Description Description Not used (read/write). GBR (Global pase register)-Used to locate. the global page table in the system virtualmemory. The~ as bits 29:02. on the MicroVAX global base register Not used (read as zeros).
Confidential and Proprietary
Preliminary
MicroVAX 78j32
DMA Channel Control Registers (0-J)-The four channel control (DCCTLO through DCCTL3)
registers, one for each ch.annel, are used to control, configure, and determine status for the four channels. Three translation error bits are used for system, process, and global tranSlation errors~
Translation errors can occur when a bus error is detected while fetching a page table entry, by an invalid.page table, and by a global page table entry that leach to another global page table entry.
The cause of errors is indicated only by the error bits that define the location in the translation
process in which. the error occurred. For ~mple, ~ ~he ern;>r occurred diµlng the global part of translation, then the global error bit will be·~··Theforll19,tof t~ register information is shown in
Figure 7 and defined in Table 13.
· ·
ISPTE
IPR CHAtl\I TOI , WIDTH DIR TE~M
Figure 7·MicroVAX 78.532 DMA Channel Cont?tJIRegisters (O-J) Format
Table 13 ·MicroVAX 78.S32 DMA C~ Conttf>l~ters {0-3) Deacription
Bits
Description
31
ERR (Error)-A read-only bit.seqo iQdicate that lln, error has pc;:curred in a channel
operatjop when any of bits ,30:26 are set. Cleared.during a. reset operation, by
writing a 1 to this location, or by setting the ENABLE (bit 00).
30
GTE (Global translatjqn error}'-A read-only.bit set to irid.icate that an error
ocCl,ll'red duri,ngan address transla,tion in,Vl)\ving global page t~bli;s'. The ISPTE and
IPTEhits indicate wh~ in the pi:ocess the t!trar occurred ~ared during a reset
ope~tion by writing a 1 to this location, or when. the ENABLE (bit 00) is set.
29
IPTE (Invalid process J?l1.ge table e~try)~A reoo:o,nl,Y, .bit ~t to indicate that an
invalid process page table entry has 1'een fetched. Cleared during a reset operation,
by writing a 1 to this location, or by setti~ the ENAB~E(bit 00).
28
ISPTE (Invalid system page table entry bit),,, .Al"(!a$l·<mlybit set to,indicate that an
invalid system.page table entry has qeen fet.cped..9eared QU,ring a.reset operation,
by writing a 1 to this location, or by setti~ the ~NA&LE (bit 00).
27
VBE (MicroVAX bus error)-A read-only b:it .set to indicate that a bus error
occurred on the MicroVAX bus during a PM'.t\: transfer on this channel. Cleared
during a reset operation, by writing a 1 to tbi~ ic;>cation, or by setting the ENABLE
(bit 00).
'
26
IBE (I/O bus error)-A read-only bit setto indicate that a bus erroF occurred on the
I/O bus during aDMA transfer on this channel. Cleared during a reset operation, by
writing a 1 to this location, or by setting the ENABLE (bit 00).
Confi.Qential and Proprietary
1-127
-
Bits 25:24 23 22 21:18 17 16:15
14:13 12 11
10 09:08
Preliminary
MicroVAX 785,2
Deicription
Not used (read as zeros).
OONE~A read-only bit set to indicate that the current channel operation has
terminated. Clea.red during a resetoperation when written to a 1 or whenENABLE (bit 00) is set.
IOI (I/O interrupt)-A read/write bit set to indicate that the UR line for this channel has been asserted. If the 'IOI (bit 10) is also set, the current tranSfer will terminate. Cleared during a reset operation or when ENABLE (bit 00) is set.
Not used (read as zeros).
PHYS (Physical)-A read/write bit set to disable the address translation for this channel. The contents of the DCSPTE;x: register are ignored and the contents of the
DCUPAx register are used as the first physical byte address of the transfer.
IPR (lntemipt priority}-Read/write bits that specify whichIRQ line is asserted if a channel error occurs or when a DMA operation terminates as follows:
IPR Bits IRQ Line
16
15
0
0 . iRQ(}
0
1
IRQl
1
0
IRQ2
1
1
IRQ3
NXTCH (Next channel)-Read/write bits that indicate the number of the next
channel to be enabled in a chaining operation when CHAIN (bit 12) is set.
CHAIN.;_A read/write bit set to start a transfer on the channel specified by
NXTCH channel number when the current transfer terminates without error.
IlOP (Interrupt 1/0 processor)-A read/write bit when set and IE (bit 02) is set, it
causes the channel interrupts to be directed to an I/O bus processor when the IOPINT signal is asserted: When cleared and IE (bit 02) is set, the channel
interrupts are directed to the MicroVAX CPU as determined by the IPR line.
'IOI (Termination on interrupt)-A read/write bit set to terminate DMA transfers on this channel upon the assertion of the IIRsignal for this channel.
CTM (Count mode)-Read/wri~e bits that determine whether addresses on the
MicroVAX bus and/or I/O bus will remain the same or be incremented for data transfers on this channel; MicroVAX bus addresses are incremented by 4. The I/O bus addresses· are incremented according to the data width of· the 1/0 device
involved in the transfer.
CTM Bits 09 · 08
MicroVAX Bus Address
I/O Bus Address
0
0
same
0
1
same
1
0
incremented
1
1
incremented
same incremented same ,incremented
1-128
Confidential and Proprietary
-
MicroVAX. 78512
07:06
05:04
03 02 01 oo
WID'l'H-:-Read/write bits that specify; the data width ofthe 1/0 device associated with the channel as follows:
wmm: Bits Data Width
07
06
0
0
1 byte
0
1
1 byte
1
0
2-~s
1
1
4 bytes
MODE (Mode field)--Read/'W'rite bits that specify the operational mode of the channel.
MODE Bits Operational Mode
OS
04
0
0
illegal
0
1
I/ODMA
1
0
DMA
1
l
wincilow
DIR (Direction)-A read/write bit that specifies the direction of a data transfer in DMA mode. Set to specify a transfer from the I/O bus to the MicroVAX bus. Cleared to specify a transfer from the:MkroVAKbu$to d1~H/G bus.
IE (lntettupt cmahle)~A ~~te bit setto e~bk ~e/~pts to devices on
the MicroVAX bus and1/0 bus.Must be set before or at the same time ENABLE (bit
00) ·is set. Cleared during a·reset operation··to ifumediately disable all channel
interrupts.
TERM (Tenninate)-A read/write bit, set to force the termination of the current channel operation, but allows buffered datato be mitten. Cleared during a reset operation .Of by setting ENABLE (bit 00).
ENABLE (Enable)--A ~writl! bit set to ~ial'Clydear !,lits 31:27 and 23:22 of this register and to co~ the chanMI tU;Cotding to bits l7:03. Cleared during a reset operation to immediately abort the ~nt channdoperation. Any buffeted
data is lost.
DMA Channel In~~ Register$ (0-J)-Thechannel interrupt vector/(DCINTO through
DCINT3) registers roritain the Vector value used by MicroVAX CPU to process:interrupts related to the operation of the channeL The priority .of t;b,,lf interrupt is: specified:h>r thf! IPR field of the
register. The format of the register information is shown in Figure 8.
.Figure 8·MicroVAX 78532 DMA Channel Interrupt Registers (0-3) Format · 1-129
Preliminary
MicroVAX 78532
DMA I/O Base Address Registers (0-3)-The DMA I/O base address (DCIOBAO through DCIOBA3) registers contain the base address of the device or memory on the I/O bus that will participate in a DMA transfer on this channel. When the DMA transfer is started, the register is
copied into the DCIOAx register which may be modified during the transfer. The DCIOBAx register information may be used in subsequent transfers or in chaining operations. The format of
the register information is shown in Figure 9.
Figure 9 ·MicroVAX 78532DMA1/0 B~e Address Registers (0-3) Format
DMA I/O Source Address Registers (0-3)-The DMA 1/0 source address (DCIDSO through
DCIDS3) registers contain a 24-bit physical 1/0 bus addressthat specifies the source of an I/O DMA
transfer. This address may be associated with a peripheral device or the start of a memory buffer in
I/O bus memory'. The format of the register information is shown in Figure 10.
Figure 10 ·MicroVAX 78532DMA1/0 Source Address Registers (0-3) Format
DMA Initial Byte Count Registers (0-3)-The initial byte count (DCIBCO through DCIBC3) registers contain the initial byte count for a DMA or I/O DMA transfer. When the transfer is started,
the register information is copied into the DCBCx register where it is decremented as the transfer proceeds. The maximum DMA transfer length is 1 Gbyte and the maximum I/0 DMA transfer length is 16 Mbytes. The format of the register information is shown in Figure 11.
Figure 11 ·MicroVAX 78532 DMA Initial Byte Count Registers (0-3)Format
DMA Wintlow Mask Registers (0-3)-The DMA window mask (DCWMO through DCWM3) registers are used during window mode data. transfers to help determine where in MicroVAX memory a window mode transfer will occur. Refer to the Window Transfers paragraph for more information. In window mode, the register information is logically ANDed with the address on the
VO bus to specify an offset within the window. The format of the register information is shown in
Figure 12.
1-130
Confidential and Proprietary
Preliminary
MicroVAX78532
F::~aJ: ::::::::Hs7 ::::::::::n
Figure 12 ·MicroVAX 78532 DMA Window Mask Registers (0-3) Format
DMA Byte Offset Registers (0-3)-The DMA byte offset (DCBOO through DCB03) ~gisters are used with the DMA system virtual PTE (OCSPTEO through DCSPTE'.3) registers to f;fetermine a memory location where a mapped DMA ··buffer or MicroVAX· window starts. The register information is used to find the physical address of thdirst (ba8e} page of the tranSfer. Each register
contains an offset (in bytes) that, when added to the base page address, specifies the physkal
address of the first byte of the buffer or window. Refer to the Address Translation paragraph for the use of these registers. The format of the register information is shown in Figure 13.
Figure 13 ·MicroVAX 78532 DMA Byte Offset Registers (0-3) Format
DMA MicroVAX Physical Address ·Registers (0·3)-The DMA MicroVAX physic& address (DCUPAO through DCUPA3) registers contain the basephysicaladdress in MicroVAX memory for unmapped transfers in DMA and window modes. For unmapped DMA mode transfers, this register specifies the physical address in MicroVAX memory at which a DMA transfer will begin. For unmapped window mode transfers, an offset is added to the contents of these registers to determine the startingaddress of thetransfer. The offsetis obtaiflCrl byANDing the address on the I/O bus with the DCWMx registei: The format ofthe·register information is shown in Figure 14.
Figure 14 ·MicroVAX 78532 DMA Physical Address Registers (0-3) format
DMA System V'trtual Address PTE Registers (0-3)-The system virtual address PTE (DCSPTEO through DCSPTE3) registers contain the system virtual address of a page table entry. The page table entry points to the base·add~ss of the page at which a mapped DMA buffer or window begins. An offset (expressed as a number of bytes) contained in the DCBOx register is added to the base address to specify the address of the first byte in the butfer or window. The format of the register information is shown in Figure 15.
Confidential and Proprietary
1-131
·-
MicroVAX 78532
313029
00
~ : : : : : :: : : : : Hofeis: : : : : : : : : : : : : : \
Figutr! 15 ·MicroVAX 78532 DMA System Virtual Address PTE Registers (0-3) Format
DMA I/O Destination Address Registers (0-3)-The DMA I/O destination address (DCIDDO through DCIDD3) registers contains a 24-bit physical I/O bus address that specifies the destination of an I/O DMA transfet This address may be associated with a peripheral device or the start of a memory buffer in J/O bus memory. The format of the register information is shown in Figure 16.
Figutr! 16 ·MicroVAX 78532DMA1/0 Destination Addtr!ss Registers(0-3) Format
DMA Current System Vtttual Address PTE Registers (0-3)-The current system virtual address PTE (DCCSVO through DCCSV3) registers contain the system virtual address of the page table entry currently being accessed. If a translation error occurs (for example, when a page table entry is invalid), the system virtual address of the erroneous page table entry is in this registet These registers are read only. The form.at of the register information is shown in Figure 17.
Figure 17 ·MicroVAX 78532 DMA Current System Virtual Address PTE Registers (0-3) Format
DMA Current I/O Bus Address Registers (0-.3)-If an 1/0 bus error occurs, the DMA current I/O bus addre~s (DCIOAO through DCIOA3) registers contain the I/O bus address associated with the error. These registers are read only. The format of the register information is shown in Figure 18.
Figure 18 ·MicroVAX 78532 DMA Current l/O Bus Address Registet! (0-3) Format
1-132
Confidential and Proprietary
-
Preliminary .
MicroVAX 785:12
DMA Current Byte Count Registers (0-3)-The current byte count (DCBCO through DC})C3) registers contain the byte count for the transfer currently in progress. It specifies the number of bytes remaining In the transfet. The$e registers are read only. The format of the register
information is shoWn in Figure 19.
Figure 1~ ·MicroVAX 785}2.t)MA C,urrent Byte CoujdR.et,isters(0-3)Format
DMA Current Page Table Entry Registers (0-3)-The DMA current page table ~try (QC]!I'EO
through DCPTE3) registers contain the page table entry currently being accessed. If a transla·
tion error occurs due to an invalid page table entry, the erroneous page table entry can be found in
these registers. These registers are read only. The format of the register information is shown in
Figure20.
.
Figure 20 ·MicroVAX 785)2 DMA CurrentPage TabkEnny &f,isfds (0-3)Format
'·
-
- -.-- ;"1 -,·
,,.,
. · . .,_._. ·- ' '
' '
DMA CunentPhysicd Address Registers (O·l}:-If:aMicroVAX bus errorcx:curs, the PMA CUJ"rent physical address (DPAO through DCPAJ) register&ciu1usually be decremented by 4 to obtainthe
MicroVAX longworo physical address l.\$se>ciated Withthe error. An exception is when bits 8:0 = 0
during a mapped transfer (Le., a page boundary.is crossed).and thelongworo that caused the Cfror is the last longword of the previous page. These registers are read only. The format of the register
informationis shown ip. Figure 21.
Figure 21 ·MicroVAX 78532 DMA Current Physical Address "Registers (0-3) Format
Confidential and l'roprietafy
1-133
. ------~-~-----·--·-·--------·--,--------------------~--.-lliill-·- - ·
-
Preliminary
MicroVAX 78532
· CLannel Operations
The type of operation performed by a channel is specified by MODE bits 05 and 04 of· the appropriate DMA configuration register (DCCTLO through DCCTL3).·· A channel operation is performed by the following:
· The configuration data is entered into the DMA global control register.
· The I/O device involved in the transfer must be appropriately configured and enabled. This is usually accomplished by an access operation that writes data to the I/O device.
· In the MicroDMA, the user registers that define the parameters of the channel operation are written (initialized) with appropriate data. If mapped transfers are to occw; the DMA global base register and D.MA system base register must also be initialized.
· The data that configures the channel and initiates the channel operation is written into the DMA channel control register.
DMA Transfers
A DMA transfer requires the user to specify the starting MicroVAX bus address, the starting 1/0 bus address of the transfer, and the number of data bytes to be transferred. The configuration parameters such as the direction and data width of the transfer are then written into the appropriate DMA channel control register.
For unmapped DMA transfers, the starting MicroVAX bus address of the transfer is completely
specified by the physical byte address of the beginning of the data buffer. This is contained in the
DMA MicroVAX physical address register. For mapped DMA transfers, the system virtual address of the page table entry that points to the first buffer page and the byte offset from the start of that page to the first data byte must be entered. These addresses specify the beginning of the buffer in virtual memory when the DMA .system base register and the DMA global base register are initialized. The system software computes these quantities from a virtual address and the process context, and loads them into the appropriate DCSPTEx· register and the DCBOx register to define the virtual buffer. The starting I/O bus address of a transfer is contained in the DMA 1/0 base address register.
The initial byte count is contained in the DMA initial byte count register (DCIBCx). At the beginning of the transfer, the DCIBCx register information is loaded into the current byte count register (DCBCx) and the reglster is decremented as the transfer progresses. When DCBCx reaches zero or becomes negative, the transfer is complete and is terminated.
Configuration information for the DMA transfer is contained in the DCCTLx register. In addition to specifying the data width and direction of the transfer, it also contains a "count mode" that specifies which addresses will be incremented !ind the value pf the increment as data is transferred from one bus to another. Addresses to or from the MicroVAX bus may be incremented by 0 or 4 because memory is always addressed in longworos on that bus. Addresses to or frorµ the I/O bus may be incremented by 0, 1, 2, or 4 depending on the programmed width of the I/O bus. I/0 bus addresses are not incremented for DMA transfers to or from a peripheral device through its data register. 1/0 bus addresses are incremented for I/O bus memory to MicroVAX memory transfers.
Table 14 lists the initial conditions of the registers involved with a DMA transfer. When these conditions have been established, a DMA transfer is initiated by the assertion of the ITR signal by the I/O device. A simplified flow diagram of the actions of an I/O device, the MicroDMA controller, the MicroVAX CPU, and MicroVAX memory during a typical DMA transfer is shown in Figure 22.
1-134
Confidential and Proprietary
-
Preliminary·
MicroVAX 78.Sl2
Table 14 lists the initial conditions of the registers involved with a OMA transfer:. When these conditions have been established, a OMA transfer is initiated by the assertion of the ITT signal by the 1/0 device. A simplified flow diagram ofthe actions of an 1/0 device, the MicroDMA controller, the MicroVAX CPU, and MicroVAX memory during a typical DMA transfer is shown in Figure 22.
18ble 14 · MiuoVAX 78.532 DMA '.liansfer Initial Conditions
Bit DGCTL
Content
= OC(16).(DEN 1, WID 03:02 (byte)
DCIOBA2
1001(16) (l/0 base address)
DCIBC2
OA(16) {Itµtial byte count)
DCB02
3316}(Byteoffset)
DCSPTE2
System virt:u8l address of base page table entry
DCCTI.02
03
~ (Transfer is to MicroVAX)
DCCTL2
05:04
10 (DMA:mode)
DCCTU
07:06
01 {Byte wide)
DCCTU
09:08
10 (HOLD IJO addre~a,nd INC MicroVAX address)
Data to be transferred is 01,02,03,04,05,06,07108,09, and OA.
Confidential and Proprietary
1-135
, MieroVAX ~l'lmory
MicroVAX CPU
MicroDMA Controller
,t
WAITING ·FOR. D~TA
MicroVAXi785'32
1/0 Bus.· Device ~
INITIATES 1/0 BUS READ CYCLE AT SOURCE 1/0 ADDRESS
ASSERTS iAS. ETC.
SUPPLIES DATA .
ASSERTS iR5V
LOADS DATA INTO
INTERNAL ITWO
LONGWORD) BUFFER AND DECREMENTS BVTE COUNT
iDC8Cxl ACCORDINGLY
COMPLETES CYCLE ANO GRAf\lTS OMA
ASSERTScOMGI
MAY PERFORM ADDRESS TRANSLATION
Figure 22 ·MicroVAX 78532 DMA Transfer Flow Diagram
1-136
Confidential and Proprietary
Preliminary
MicroVAX CPU
Mi<NOMA Controiler
MicroVAX 78'32
l/OSUS Device
ASSERTS A$; Wrf, ETC.
ACCEPTS IJl,TA
ASSEllTS Rl'W
GIVES UP MicroVAX). BUS
DEASSEATS i5'iiiR
ACCEPTS BUS
LOOP8ACK
TO WAIT FOR DATA
NO
TERMINATE TRANSFER
tfatis/er Figure 22 ·MicroVAX 78532DMA
,_
: -
.
Flow Diagram
'
'~--' ,. ; ' '
'
('Co' ntin. ued)
Confidential.and Proprietary
1·137
Preliminary
MicroVAX 785)2
An example of a DMA sequence to transfer 10 bytes of data from a bytewide I/O device at 1/0 bus address 1001 (hexadecimal) to a buffer in MicroVAX virtual memory at offset 33 (hexadecimal) from the base page is listed in Table 15. Channel 2 is used for the transfer.
Table 15 ·MicroVAX 78532 DMA Transfer Sequence
Byte MicroVAX
Bus
Count Operation Address* BM< 3:0 > Data
IfO
Bus
Operation Address mM < 3:0 > Data
10 write ---30
9 8 7 6
write ---34 5 4 3 2 1 write ---38 0
write ---3C Transfer terminates
0111
0000
0000
mo
read Olxxxxxx -
read read read read 05040302 read read read read 09080706 read xxxxxxOA-
1001 xxxO
1001 xxxO 1001 xxxO 1001 xxxO 1001 xxxO
1001 xxxO 1001 xxxO 1001 xxxO
1001 xxxO
1001 xxxO
xxxxxxOl
xxxxxx02 xxxxxx03 xxxxxx04 xxxxxx05
x-xxxxx06 xxxxxx07 xxxxxx08 xxxxxx09
xxxxxxOA
*The upper bits of the MicroVAX address depend on the page table information and are not shown. The lower two bits of the MicroVAX address are indeterminate and not necessarily zero.
Window 1iansfers To perform a window transfer, a window (i.e., a set of I/O bus addresses that correspond to locations in MicroVAX memory) must first be defined by the user. The user application decodes I/O
bus addresses (IDAL<23:00> such that the ITRx signal is asserted when an address in the window region is referenced.
When the 1/0 processor begins a window access, the MicroDMA uses the IBM< 3:0 > information, and the width of the JfO bus (byte, word, or longword) the effective byte count of the transfer
and to perform substitution for the low one or two bits of the incoming address, shown in Figure 23 and Table 16.
For unmapped window transfers, the base of the window region is completdy specified by the physical byte address of the window in MicroVAX memory. This must be loaded into the MicroDMA physical address register (DCUPAx), and is added to the window address derived from
the 1/0 bus device requesting the window access.
1-138
Confidential and Proprietary
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MicroVAX 78S32
IDAL<23:02>
TOOcBCx (BYTE COUNTf ._____,.....__..IOAL<01 :DO> DCWMx
31
24 23
00
WINDOW ADDRESS (WA)
O
Figure 23 ·MicroVAX 78532 Window Addressing Logic
This window address is derived by ANDing the effective 24-bit 'I/O address with the window· mask register DCWMx). Using the window mask to mask off the "don't care" bits from the address, simplifies the external hardware required to decode the iTRi signal. The sum of this window
address and the DCUPAx register forms the MicroVAX physical address of the window transfer. The
laocntugawlotrradnbsofuenrdw1lifl}lI'r.e.quire 1IlOfC than one access·'°· MiaoVAX ~. i . . .s the.ac:cessbytes cross of
&r mapped win<;low.transfers, both the syl);tem virtual ad~s of th~ p~~ table entry and byte
offset in the firsi window page must be s~ied ajmilarly.toaDM,4 t;ansfet Th~ incomingI/()bus address and byte tQaSb define a displacetn¢nt;£rom the base of.the~· Tuis is masked bythe contents of DMA window mask register and ~.to compute a new system.virtual address PTE and
byte offset.
For both mapped.and unmapped window transfers, the width qhhe channd is de&ed by DMA
channel contl.'61 register bits 7 and 6. ·
. ·
· .
.
Confidentialiand Proprietary
1-1.39
~...,..,....-..,.1.1-.&..0-,..Y.,.,._,,.,..,,..,_,n""<tlPf"..,.--c!.V,..aR.,.....,""''"'-''""'Hr,_..,,..._.,...,.......~.......·--~---. . --~---- ~-~
-
MicroVAX 785.12
Table 16 ·MicroVAX 7~.S.32 WiQdow Transfer Byte Count and Effective Displacement
Channel Width
IBM<..3:0>
Byte Count
Effective I/O
Bus Address < 01:00 >
Byte
xxxx
1
IDAL < 01:00 >
Word
xxOO
2
xxOl
1
xxlO
1
IDAL<Ol> 'O* IDAL<Ol>'l IDAL<Ol>'O
Longword
0000
4
00
0001
3
01
0011
2
10
0111
1
11
1000
3
00
1001
2
01
1011
1
10
1100
2
00
1101
1
01
1110
1
00
*(')indicates concatenation.
If the MicroVAX CPU performs an I/O bus access when' a windo"W access is being performed, a deadlock may occur as the MicroVAX and 1/0 processor each wait for the other's bus.
The 1/0 processor can ensure a unique access.to MicroVAX memory. Before beginning a window
access, the I/O processor must assert VBR and wait for VBG to be asserted. Because the MicroVAX pus is acquired by the ·MicroDMA before the window access, the possibility of deadlock is eliminated. Aftet the window access (or accesses), VER should be deailserted to allow the
MicroVAX processor to regain control of its bus.
The MicroDMA chip contains hardware that detects the presenee of a deadlock if it occurs. It
breaks the deadlock by causing a bus error on the MicroVAX bus by asserting the ERR·signal and
sets a bit in the DMA global control register to inform the MicroVAX CPU of the cause of the error.
Tuble 17 lists the initial conditions for an example of a window transfer. The sequence of events involved in this example is shown in Table 18. One byte is to be transferred from the I/O bus to the MicroVAX bus. The channel is configured in word mode. The user application decodes I/O bus addresses in the range xxxlOOOO-xxxlOlFF (hexadecimal) as window references. The I/O processor writes data word 55xx to location 10022 (hexadecimal).
Confidential and: Proprietary
DCWMx
DCCTLx DCCTLx DCCTLx DCUPAx
Preliminary.
MicroVAX 18532
Table 17 ·MicroVAX 78'32 Wmdow '.liansfer Initial Conditions
Bit
Content
04DEN=l
05:04
lFF (Mask high bits of 1/0 bus address) 11 (Windi>w mode)
17
1 (Physical addressing)
07:06
10 (Word width)
7341 (MicroVAX memory base physical address)
I/OBus Address
10022
.wmdow Table 18 ·MicroVAX 78.532
~er Sequence
IBM< 3:0 > Data
<MicroVAX.'
Qpeqa~ .,\.ddress JJ~ < 3:0 :> ~ta
Operation
xxOl
xxxx55xx Write 7364
1110
xxxxxx55 Write
The MicroDMA adjusts the value of the lower bits of the I/O bus address, as shown in Table 16. A
byte count of 1 is !lent to the DMA 'current byte c6tlnt :reiistet.
'
'
'
1
J/O DMA Transfer
An I/O OMA: transfer is an unmapped, unbciffered data transfer between an I/O bus source and an I/O bus destination. Because buffering arid datit liligrimeht are notperformed, the
source and destination addresses must be aligned on "nattl1'1lf' boundaries. i{f a channe1. is configured to 'perform word transfers; the addresses litU$tbe :a multiple of 2. If a channel is configured to perform longword transfers,. the addresses roust be a inultiple of 4. An. I/0 ·DMA operation has the following sequence:
1. The appropriate ITR < 3:0 > signal is asserted by an I/O device.
2. An 1/0 bus read cycle is performed at the address specified by the DMA 1/0 source address register (DCIDS).
3. H bit 8 of the D?vl.A channel cohtrol'register (DCC1L) is s~t, the DCIPS register is im:remented by the width of the channel specified by bits 7:6 of the DCCTL register. If cleared, d)e,DCIDS
register is not changed. 4. An I/O bus write cycle is performed at the ~dressspeci£iedby the PMA I/O destin,atiop. address
(DCIDD) register. The appropriate ITR< 3:0> line should be deasserted by the end of this
write cycle if the I/O device is not ready for another transfer. 5. If bit 9 of DCCTL register is set, the DMA destination address (DCIDD) register is incremented
by the width of the channel. If cleared, the DCIDD register is not changed.
6. The byte count initially contained in DCIBC register and subsequently contained in DCBC register is decremented by the width of the channel. If the byte count is zero or a negative value, the transfer terminates. If it is not, the transfer continues at step 1.
Confidential and Proprietary
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Preliminary
MicroVAX 78.S.32
· Access Operatio1,1s
Figure 24 shows the relationship between a user-defined "access region" in MicroVAX physical address space and its counterpart in I/O bus address space. The user application decodes MicroVAX
bus addresses such that csr; is asserted whenever a reference to the access region is made. The
access region always starts on a 16-Mbyte boundary and the lower 512 bytes of the region are
reserved for the MicroDMA internal registers.
XXFFFFFF XX000200
MicroVAX BUS
1/0 BUS ACCESS
MicroDMA
I
I I I I I
_j_
I I
XX0001FF
xxoooooo
MicroDMA REGISTER ACCESS
f--
MicroDMA
REGISTERS
J
1/0 BUS
1/0 BUS LOCATIONS
Figure 24 ·MicroVAX 78532 Access Operation
FFFFFF
000200 000000
When the CSL signal is asserted and the address on lines DAL<23:09> is equal to zero, a MicroDMA internal register is accessed by the address on lines DAL<08:00>. When the DAL<23:09> address is not zero, the I/O bus is accessed.
An access operation may require the transfer of a byte, word, or longword as determined by bits 4
and 3 of the DGCTL register and the infortµation on lines BM< 3:0 >. The following are. more
detailed examples of the access operation.
Example 1-Thble 19 lists the sequence required to perform an access operation to write a word in I/O bus· memory from the MicroVAX CPU. The number 1234 (hexadecimal) is to be written into location 2002 (hexadecimal) and the 1/0 bus width is 16 bits. The MicroDMA has an address of
21000000 (hexadecimal) in MicroVAX physical address space.
Table.19 ·MicroVAX 78532 Access Operation Sequence 1
MicroVAX Address BM<3:0> Data
I/O
Operation Address IBM<3:0> Data
21002000 0011
1234xx:xx Write- 2002
xxOO
1234
Operation Write
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MicroVAX 7S5l2.
Example 2-Table 20 lists the sequence required to perform access operation 2 from the MicroVAX
CPU. The number 332211 (hexadecimal) is read from location 2001 (hexadecimal). The I/O bus width is 8 blts: Tht MicroDMA has.an address 0£·21000000 (hexadecimal)in MicroVAX physical
address space. The initial condition of the DGCTL register is bits 4:3 =01 (I/O bus byte width).
18ble 20 ·MicroVAX 785.32 i\cce&s ()perationSequence 2
MicroVAX Address =BM,,..,,-<"""3'""":0"'"'>- Data
I/O
Operation Addtess mM<3:0> Data
21002000 0001
Read- 2001
x:~.~o
---11
.2002
x:xxO
---22
2003
xx:xO
---33
33221lxx
Operation
Read Read Read
· Address Translation
When bit 17 (PHYS) of a channelcontrol register is clear, mapping is enabled and virtual to physical address translationwill occur for DMA a.nd wind.o.w mode transfers on that channel. For mapped DMA transfers, the information requirements to completdy specify a buffer in virtual
memory after the DSBR an.cl DGBRregisters ~ b¢~n initialized are that the DCSPTEx register
must point to the page table entry that references the ph)rsical page in which the virtual buffer or window starts. The DCBOx register must c.ontliin the byte-,offset from the beginning of that physical page to where the virtual buffer or window starts: ·
Figure 25 shows the address translationfor DMAtrans£ers ~atq~ references to process (PO or Pl) or system page tables. Figure 26 shows a DMA transfer th~t use$ references to global (i.e., shared) page tables. Further information related to VAX memory mahagement is in Chapter 5 of the VAX-11 .Architecture Reference Manual (EK-VAXAR-RM).
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1-143
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Preliminary.
31
MicroV.AX1g,;:J2
0908
00
3130 29 DCSPTEx 10
31
23 22
0
VPN OF PTE EXTRACT
09 OB
00
BYTE
02 01 00 0
31 OSBR
ADD
00
PHYSICAL BASE ADORE$$ OF SYSTEM PAGE TABLE
31
YIELDS
00
PHYSICAL BASE ADDRESS OF SYSTEM PTE
PERFORM MEMORY REFERENCE TO FETCH SYSTEM PTE; CHECK VALID.
IF BUS ERROR, OR INVALID, OR GLOBAL,. DCCTLx<30: 28> · 001.
~
~~
00
SYSTEM PTE
PFN
29
09 08
00
PERFORM MEMORY REFERENCE TO FETCH PO. Pl, OR SYSTEM PTE. CHECK BITS< 31, 26, 22 >. IF BUS ERROR, OR INVALID, DCCTLx<30:28>= 010. iF VALID, THEN USE PFN TO FOAM PHYSICAL ADDRESS.
IF GLOBAL, TO TOP OF.FIGURE B.
00
PTE
PFN
29
PHYSICAL ADDRESS OF DATA OR INSTRUCTION
09 08
00
PTE <31, 26, 22> PTE TYPE
1XX 000 001 01X
VALID PFN VALID PFN GLOBAL PTE !SEE FIGURE 26) INVALID, 1/0 ABORT
Figure 25 ·MicroVAX 78532 DMA Address Translation for Process and PTE References
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Preliminary
31 PTE
26
22 21
31
24 23
0
GL-OBAl PAGE TABLE INDEX EXTRACT
MicmVAX7Bs~2
00
02 .01 00
o.
31 30 29
AOO
SYSTEM VIRTUAL BASE AOORESS OF GLOBAL PAGE TABLE
02 01 00 0
31 30 29
SYSTEM VIRTUAL ADDRESS OF GLOBAL PTE
31
23 22
0
YIELDS VPN OF PTI! . EXTRACT
09 08
00 BYTE
31
ADD
00
DSBA
PHYSICAL BASE ADDRESS OF SYSTEM PAGE TABLE
31
YIELDS
PHYSICAL BASE OF SYSTa.t f'TE ·
.
PER FORM MEMORY REFER ENl!:E'TO FE'TCK !l'l'Stl!l\il PTE; CHl!CK'.\fll.tto:
IF BUS ERROR, OR INVALID, OR.GLOBAl.,.OoeTL><<30:28>~10tV
'
21 20
00
PFN
PHYSICAL ADDRESS OF FINAL PTE
31
[
29
09 OB
00
PERFORM MEMORY REFERENCE TO FETCH GLOBAL PTE; CHECK VALID. IF BUS ERROR, OR INVALID, OR GLOBAL, DCCTLx<30:28>=101.
21 20
00
PFN
29
pHYSICAL ADDRESS OF DATA OR INSTRUCTION
09 08
00
]
LOW BYTE= DCBOx IF FIRST TRANSLATION = 0 OTHERWISE
.Figure 26 ·MicroVAX 78532 DMA Address Translation for Global References
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Preliminary
MicroVAX178532
For mapped window transfers, the actual transfer might not start in the page referenced by the DCSPTEx register. The window address, shown in Figure 23, is used to compute new values for the SVAPTE register and byte offset shown in Figure 27. The operation is transparent to the user.
A byte offset (BO') and system virtual address (PTE) are associated with point B in Figure 28 that must be calculated before address translation can occur. Figure 28 shows how these parameters are determined. Once BO' and DCSPTE' are found, they are used to perform address translation in the same way as for a DMA transfer (see Figures 25 and 26).
SYSTEM VIRTUAL ADDRESS SPACE
1 HAIDGDHREERSSES
DCSPTEx'
B BO'
WA WA1
BO DCSPTEx
A= BASE ADDRESS QF WINDOW B =ADDRESS WITHIN WINDOW THAT IS REFERENCED WA= WINDOW ADDRESS RELATIVE TO BASE WA'= WINDOW AD.DRESS RELATIVE TO.FIRST PAGE
DCSPTEx' AND BO' ARE THE DISPLACED SVAPTE ANO BYTE OFFSET DERIVED FROM DCSPTEx AND BO.
Figure 27·MicroVAX 78532 Address Translation for Window References
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-· 31 I WINDOW ADDRESS (WA)
Pre1iminary
24 23
I 0
ADD 31
DCBOx
0
31
WINDOW ADDRESS' (WA't
0
24 23
YIELDS
MicroVAX 71S32
i
0908
00
l I BO
0908 BO'
31 0
17 16
02 l 00 0
I I DCSPTEx
31 30 29 10
ADD
I31 30 29
f DCSPTEx' 10
YIELDS
1
Figure 28 ·MicroVAX 78532 Winflow Reference Parameters
· MicroDMA In~s
The MicroDMA can interrupt the MicroVAX CPU otan Ij() p~sor; ~pending onthe contents of
the interrupting channel's DCCTLx register.
· .·
·
·
The termination of. a lJMA tran$fer sets DONE (bit. 3) of the DMA channel control (I>CCTL)
regist~ resUlting in an interrupt if IE (bit 02) is ~t. The ·interrupt will be ·proces~d by the MicroVAX CPU if IIOP (bit 11) is cleared or by an I/0 processnt ifbit 11 is set.
For a MicroVAX CPU interrupt,
· The MicroDMA asserts an IRQ < 3:0 > line according to the level encoded by IPR (bits .16 and l5J
of the DCCTLx register...
· The MicroVAX CPU responds by initiating an inteuupt ai;;knowledge bus cycle.Th¢ MicroDMA provides an interrupt vector frOm the the DCINTx register.
· If the system coi:ita:ins more than.one MicroDMA controller, the MkroDMA closest to the CPU with respect to the interrupt daisychain that has posted an. interrupt at the current level will · participate in the interrupt acknowledge cycle.
to · If .more cl:ian one channel on the MicroOMA cp.ntl"()ller. has posted an. interrupt.at the current level, the channel with the highest priority willreturn the interiupt vector the CPU.
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MicroVAX 78ll2
· The system software dears.DONE(bit 23) of the DCCTLxregister after the interrupt has been acknowledged to prevent the same interrupt from being acknowledged ag~.
For an I/O processor interrupt,
· The MicroDMA asserts the IOPINT signal.
· The 1/0 processor polls all MicroDMA channels to determine which channel caused the interrupt.
· The I/O processor processes the interrupt according to some I/O processor dependent protocol. · The 1/0 processor software clears DONE (bit 23) of the DCCTLx register after the interrupt has
been acknowledged.
· Termination of DMA Transfers
DMA and 1/0 DMA transfers are normally terminated when the byte count associated with the transfer and contained in DCBC register becomes zero or a negative value. A transfer can also be terminated before the byte count reaches zero when the TERM {bit 01) of the DCCTL register is set or when the external hardware asserts the appropriate UR signal and TOI (bit 10) of a DCCTL register is set. The IOI (bit 22) of the DCCTL register is also set to indicate that termination was caused by an interrupt. The number of bytes remaining to be transferred can be read from the DCBCx register.
DMA transfers can also be terminated when the !ERR signal ls asserted during an 1/0 bus cycle,
when the ERR signal is asserted during a MicroVAX bus cycle, or when an invalid page table entry is referenced.A global page table entry reference that is either invalid or refers to another global page
table entry will also terminate the transfer. If the transfer is terminated by an error, a corresponding
bit in the DCCTL register is set to specify the error type.
The MicroDMA performs the following for all DMA transfer that are terminated.
· Sets DONE {bit 23) of the DCCTL register.
· Sets IOI (bit 22) of the DCCTL register if an IfO interrupt caused the termination.
· Clears ENABLE {bit 00) of the DCCTL register.
· Asserts the IOPINT signal if IE {bit 02) and IIOP (bit 11) of the DCCTL register are set.
· Initiates a MicroVAX interrupt at the level specified by IPR (bits 16 and 15) of the DCCTL register if IE (bit 02) is set and IIOP (bit 11) is cleared.
· Chaining
The MicroDMA includes logic to automatically switch channels after the data transfer has terminated. This is defined as chaining and is normally used by I/O subsystems that continuously transfer data at high data rates. To reduce the time required to service an interrupt and reconfigure a channel following the termiµation of .a DMA transfet; chaining is used to switch channels and the buffers associated with the channels to prevent data loss.
Chaining is enabled by setting CHAIN (bit 12) of the DCCTL register and the next channel in the
chain is specified by NXTCH {bits 14 and 13). If the current OMA transfer terminates without
errot; the channel specified by the NXTCH bits begins operation. Interrupts that were enabled for the first chanrielwill be serviced when the next channel in the chain is active.
The pins for the ITR < 3:0 > channels involved in a chain should be connected together to preserve
the transfer requests.
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Preliminary
MicroVA'X'iAS32
The pins for the ITR < 3:0 > channels involved in a chain should be ~nnectecl together t,(j .~
the transfer requests,
· MicroDMA Reset
When the RESET line is asserted, the RESET (bit 00) ofthe DGCTL register is set and the MicroDMA performs the following reset operation:
· DGCTLregist:er""".""Clears'theDEAD (bit 31), IOwE (bit 10), W$D.bit<04:03> and RESET (bit 00)
· All DCCJ'L registers~~ears the error condition (bits31:27),: :qpNE (bit 23). IOI (bit 22), IE
(bit 02), TERM (bit 01),.and ENABLE (bit QO)
·Bus Cycles
Operations such as DMA t1'lltl.Sfe111. window transf~s, and access ?peratio~s. requk the execution
of ~ne or more bus cy~s on the MiCroVAX bus and/or the I/O bw. A bus cycle is~ sequence of
events .that result~ in. a transfer of information between a bus ~aster a~ a bus ~ve. Bus cycles
usually involve read,' write, itl~nvpt acknowleclge, 'cir DMA opepitjons.
·
·
This section briefly describes the characteristics and prot~ok bf the various Mi~ bus
cycles. Bus cycles on the. I/Obusandthe:MkroVAXbus are similar. ~ailed:timing in£ormati9'n is
contained in the ac Characteristics section.
Mict'OVAX Bus Cycles
MiCl'OVAX Bus Read Cycle-A MicroVAX bus master performs a MiCT:QVAX b\.\13 ~cycle when, it
requires information from another MicroVAX bus.device, A~ss and control.information is sent to the bus slave during the fir$t part of a read .cycle and the ~o~ parvof tbe cycle is used to read
the data. The sequence of eventsfollpws:
L The bus master transfers the physical longword address of the locatiop tQ be read Of.\ dre
DAL<29:02> lines.
2. The WRline is unassert®. and the CS <2:0 >.lines a+e driveµ J:Jy the bus master to i,ndicate the
type of cycle being performed. 3.·The bus master drives the .B.M. ,,.,,...·:<_,.J..:.0. ,..,>-. lines.
4. The bus master asserts the AS signal to indicate that the address on the DAL lines is valid and can
be latched. When the· MicroDMA is be:\ns adckessed for n;gi:ster oli' ·. I/O bus '<¥'Cess, the CID:
signal must be asserted. The AS signal also qualifies the~nfor~iolil on ~ CS<2:0>, WR, and BM< 3:0 > lines.
5. The bus master asserts the DS signal to indicate that the bus is available to receive the required
information. The bus master also asserts the DBE signal lit ~ time whld,i. can be used to
control DAL line bus transceivers.
·
.· .·
6. If the slave can supply valid data within minimum access time1.i,t. asserts . the R'DY signal.at J;he
first sample window. after the assertion of AS and the master latches the data. If 41lta is, not
available at this time, the master waits.eight periods of the cuq·~ and samples the RDY
signal again. This sequence continues every eight clock peri~ unt:U the RDY signal is asserted.
I£ a bus error occurs, the external logic or the bus slave will respond by asserting the ERR signal.
The bus master must then process thee error. The current bl.ll! cyi:;lejs completed when the RDY or
ERR signals are asserted. The bus master latches the requested data and dea~rt;s theDS line. 7. The bus master deasserts the CSL line if it is asserted, and asserts the AS and DBE lines to end
the bus cycle.
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MicroVAX 78532
MicroVAX Bus Write Cycle
A MicroVAX bus master performs a MicroVAX bus write cycle to transfer information to another
MicroVAX bus device. During the first part of the bus cycle, address and control information is sent
to the bus slave. During the second part, the data to be written is transferred. The sequence of
events follows:
·
1. The bus master drives the physical longword address of .the location to be read onto the
DAL< 29:02 > lines.
2. The WR signal is asserted and the CS<2:0> lines are driven by the bus master as required. 3. The bus master drives the BM < 3:0 > lines and asserts the AS signal to indicate that the address
on the DAL lines is valid and can be latched. When the MicroDMA is being addressed for
register or 1/0 bus access, the CS'E signal must be asserted. The AS signal also qualifies the
information on the CS <2:0 >,WR, and BM< 3:0 > lines.
4. The bus master asserts the DBE signal, drives data onto the DAL lines, and asserts the DS line to
indicate that the data is valid.
5. If the slave can accept valid data within the minimum write cycle time, it asserts the RDY signal
at the first sample window after the assertion of the AS signal and latches the data when the DS
line is deasserted. If the data cannot be accepted at this time, the master waits eight periods of
the CLKI signal and samples the RDY signal again. This sequence continues every eight clock
periods until the RDY line is asserted. If a bus error occurs, the external logic or the bus slave
responds by asserting the ERR signal and the bus master must then process the error. The
current bus cycle is completed when the RDY or ERR signal is asserted.
6. The bus master deasserts the DS signal to indicate that it will remove the data from the DAL lines
and deasserts the AS and DBE lines to end the bus cycle.
MicroVAX Bus DMA Cycle
This cycle is used to force the bus master to release control of the DAL lines and related control signals to another MicroVAX bus device. The sequence of events follows: 1. A device requests the use of the MicroVAX bus from the bus master by asserting theDMR signal. 2. If the bus master is not performing a locked read cycle, it responds to the assertion of the DMR
by releasing the DAL<31:00>, AS, DS, DBE, WR, and BM<3:0>, lines. 3. The bus master asserts the DMG signal when it releases control of the bus and grants the use of
the bus to the requesting device. 4. One or more read and/or write cycles occur on the bus between the requesting device .(the new
bus master) and its slave. 5. When the requesting device is finished with the bus, it deasserts the DMR line to return control
of the bus to the original bus master. 6. The bus master deasserts the DMG signal and resumes operation on the bus.
MicroVAX Bus Interrupt Acknowledge Cycle A MicroVAX bus master performs an interrupt acknowledge cycle to acknowledge an interrupt request from a slave through the IRQ lines and to read a vector. The timing for this cycle is the same
as the MicroVAX bus read cycle shown in Figure 30. The sequence of events follows: 1. The bus master ttarisfers the priority of the interrupt being acknowledged onto lines
DAL<04:00>. The DAL<29:05> lines contain zeros and the DAL<31:30> lines contain
the value of 10.
2. ·The CS< 2:0 > lines are driven by the bus master to indicate an interrupt acknowledge cycle. 3. The bus master asserts all the BM <3:0> bits.· The WR signal is unasserted.
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MiCl'OVAX 185'2
4. The bus master asserts ~he AS signal to indicate that the interrupt.priority on the DAL lines is
valid and asserts t;he i5S signal to indicate that the bus is available to receive incoming data. The
bus master also asserts the DBE line, which can be used to control DAL line transceivers.
5, If no error occurs, the exter:nal logic or the bus slave transfers the iqterrupt vector on the
DAL<09:02> lines, thenormalprocessing/Q-buspJ:OCessiqg flagon theDAL<OO> line, and
asserts the RDY signal. Refer to the MicroVAX CPU User's Guide for a description of the normal
processing/Q-bus processing flag. The DAL< 15:10,01 > lines ~m;t be set to a valid high or low
level in accordance with the setup times shown in Figure 30.
.
6. If an error occurs, the external logic or the bus slave asserts the ERR signal. Thebus master
cancels the cycle !U)d ignores the data on .the DAL lines.
7. The bus master latches the interrupt vector, dea~erts the D'S signal, and deasserts the AS and
DBE signals to end the cycle.
.
I/OBusC~
1/0 Bus Read Cycle-:-""An J/O bus master performs an I/O .bus read: cycle when it requires information from another J/O bus device. During the first part ofa read cycle:. address and control information is sent to the bus slave, During the second pat;t of the cycle the data is read. The sequence of events follows:
1. The bus master drives the physical longword address of the location to be read: ont;o the
IDAL<23:00>. lines.
2. The i'WR signal is left unasserted. The bus master asiierts Jihe IBM <OH')> .as required.
4. The bus master as~rts the IAS signal to indicate. that the adqress on the,.ID.t\l, lines is valid and
ready ~be latched. The IAS signal also qualifjes the informatif!non t;he IBM< 3:0 > and iWR
lines.
. .
·
5. If the MicroDMA is not J./O bus master. and is performing ~ wjpdow ~ss, then the iTR signal
for the requested window channel should be asserted when the IA'S" signal is asserted. If a
MicroPMA register access is to be oorformed, the IREG sigmllshould. be asserted at this time.
6. The bus master asserts the IDS signal to indicate that the bus is available. t<;> receive the required
inforrrw,tion. At this time tP.e bus master also asserts IDBE which can be used to control IDAL
line transceivers. 7. If the slave can supply valid data within the mini.mum acces$ riirl.~. it assert.s the !].DY signal at
the first sample window after the assertion of the IAS signal and the master latches the data. If it
cannot supply valid data during this time, the master waits four periods of the CLKI signal and
samples the IRDY signal again. This sequence continues every f~ur clock periods until tlie umY'
line is asserted. If a bus error occurs, the external logic or th~ pus sl~ve responds by asserting the
IERR signal, and the bus master must then process the error. The current bus cycle is completed
when the iRi5Y or IERR signals are asserted. 8. The bus master latches the requested data, deasserts the IDS. signal, and deasserts the IA'S arid
IDBE signals to end the bus cycle.
1/0 Bus Write Cycle
An I/O bus master performs an "J/O bus write cycle to transfer information to another I/O bus device. During the first part of the cycle, address and control information is sent to the bus slave.
During the second part, the data is written. The sequence of events follows: 1. The bus master drives the physical longword address of the location to be read onto tlie
IDAL<23:00> lines.
2. The i'WR signal is asserted.
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Preliminary
MicroVAX 78S32
3. The bus master drives IBM<J:O> lines and asserts the iAS signal to indicate that the address on the IDAL lines is valid and should be latched, The IA'S signaI also qualifies IBM< 3:0 > and
IWR line information.
4. If the MicroDMA is not bus master and is performing a window access, the ITR signal for the
requested window channd should be asserted when the IAS signal is asserted. If :a MicroDMA
register access is to be performed, the IREG signal should be asserted at this time. 5. The bus master asserts the lDBE line which can be used to control the IDAL line transceivers,
transfers data onto the !DAL lines, and asserts the IDS signal to indicate that the data is valid. 6. If the slave can accept valid data within the minimum write cycletime, it asserts the IRDY signal
at the first sample window after the assertion of the IAS line and latches the data when the DS
signal is deasserted. If the slave cannot accept the data during this time, the master waits four dock periods and samples the IRDY line again. This sequence continues every four periods of the CLKI signal until the IRDY signal is asserted. If a bus error occurs, the external logic or the
bus slave responds by asserting the IERR signal and the bus master must then process the error.
The current bus cycle is completed when the IRDY or !ERR signal is asserted.
7. The bus master deasserts the ID'S signal to indicate that it will remove the data from the IDAL
lines and deasserts the IAS and IDBE signals to end the bus cycle.
'I/O Bus OMA Cycle This cycle is used to force the bus master to rdease control of the IDAL lines and control signals to
another I/O bus device. The sequence of eventsfollows:
1. A device requests the use of the 1/0 bus from the bus master by asserting the IDMR signal. 2. If the bus master is not performing a locked read cycle, it responds to the assertion of IDMR by
rdeasingthe IDAL<31:00>, IAS, IDS, IDBE, IWR, and IBM< 3:0> lines. 3. The bus master asserts the IDMG line to release control of the bus and to grant the use of the bus
to the requesting device.
4. One or more read or write cycles occur on the bus between the requesting device (the new bus
master) and its slave.
5. When the requesting device has finished with the bus, it deasserts the IDMR signal to return
control of the bus to the original bus master. 6. The bus master deasserts the IDMG signal and resumes operation on the bus.
· Specifications
The mechanical, electrical, and environmental characteristics and specifications for the MicroDMA are described in the following paragraphs. The test conditions for the dectrical values are as follows unless specified otherwise. · Temperature: 70°C · Vvo=4.75V, Vss=OV
Mechanical Configw:ation The physical dimensions of the 133-pin package are contained in Appendix E.
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Absolute Maximum Ratings Stresses ·greater tbm the absolute maximum ratings may cause permanent dam.age to the device.'. Exposure to the absolute ·maximum ratings for extended ··periods may adversely affect the reliability of the device. The functional operation of the device at these or other conditions greater than indicated is not defined.
· Power supply voltage (V00): -0.5 V to 5.5 V
· lnputoroutputv0ltageapplied: Vss-0.3 V toVoo0.3 V
· Storage temperature (T5): -55°C to 125°C
· Relative humidity: 10% to 95% (noncondensing)
Recommended Operating Conditions · Power supply voltage (V00): 5 V ± 5% · Supply current (lcc) : 500 mA (maximum)
de~ CfutraCter;sdcs
The de electrical characteriStics ofthe MicroVAX 78532 for the opetating voltage 1:1ndtemperature
ranges specified are listed in Tuble 21.
·
·. ··
Table 21 ·MicroVAX '7~.532 dc ~ ~ Ou,4mt.~
· · . ' ,",'·,·, ,_><,,.: .·--.
··,, '1 ,. _i'.-:,-' .
Hjgh-level
itlput voltage
Low-lCvel input voltage
High-level output voltage
.Low-le!lel output voltage
Low-level output open-drain voltage*
R'DY, ERR DMR, IRA<3:0>)
l';,a=4ooµA CL= lOOpF
~=2,0mA C~;=l.QOpF
JoL=U.5mA, CL=lOO pF
·2;0
v
0.8 v
v
0.4 v.
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----------------------------------~--~---"
manma
Preliminary
Symbol Paramet.et
Iu
Input leakage
current
~
Output leakage
current
Ia:
Active supply
current
C1o
Input capacitance
*Minimum pullup resistor=470
Test Condition
O<V1o<VDDI 0.4<Vu.<Vom
L...=O, TA=0°C
±5%.
MicroVAX 78532
Requiements
Mm.
Max.
-10
10
Units A
-10
10
A
500
mA
10
pF
ac Electrical Characteristics
The electrical characteristics for the signals used to control the information transfers to and from the MicroDMA are defined in the following paragraphs. The following notes apply to both the MicroVAX bus timing diagrams and the I/O bus timing diagrams and their associated tables.
· The timing parameters are specified in terms of the clock (CLKI) period, where CLKI = tCIP =P.
Pis nominally 25 ns.
· All times are in nanoseconds except where noted.
· ac characteristics are measured with a purely capacitive load of 100 pF. Times are valid for loads of up to 100 pF on all pins.
· ac high levels are measured at 2.0 V, and ac low levels at 0.8 V.
· S=the number of slipped microcycles during a bus cycle. A MicroVAX bus microcycle is nominally 8P or 200 ns and the I/O bus microcycle is normally 4P or 100 ns.
· N =the number of MicroVAX and I/O bus microcycles in a DMA transfer. N has a minimum value
of2.
The following notes apply to the MicroVAX bus timing diagrams and their associated tables.
· The sampling window is used to sample the RDY and ERR asynchronous signals. The RDY and ERR signals are qualified by the assertion of the AS signal. The effect of these signals on the current bus cycle is as follows:
1. The bus cycle concludes at the end of the current· microcyde if the RDY or ERR signal is asserted throughout the sampling window while the AS signal is asserted.
2. If a transition of the RDY or ERR signals occurs during the sampling window while the AS line
is asserted, the result is indeterminate. 3. PS= Clock period (P) times slipped microcydes (S).
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The following notes apply to I/O bus timing diagrams and their associated tables:
· The sampling windQW is used to sample the following asynchronous Signals-IRDY, 'iERR, and IDMR. Signals 'iRJ:)Y and mRR are qualified by the as5ertion ofthe iAS signal. The IDMRsignal
is qualified by the assertion of the IAS signal. The effect of these signals on the current bus cycle
is as follows:
1. The bus cycle concludes at the end of the current microcycle if the IRfi'Y or iERR signal is
asserted throughout the sampling window while them 'signal !s,,asseited.
2. If a transition of the ijU)Yor.IBRR sigrtals occurs duringt;hj!samplingwindow while the IAS
signal is asserted, the resultis indeterminate. · ·
· ,
.
3. The IDMR signal is sampled at every I/O bus microcycle.
Clock Input Timing Figure 29 shows the timing specifications for the clock input (CLKI) signal and Table 22 lists the
timing parameters indicated in the diagram.
tclF
tclL
Figure 29 · Mim>VAX 78J.J2 CLKI Timing Waveform
Clock input fall time Clock input high Clock input low Clock period Clock input rise time
4.5
8.0
8.0
25
50
4.5
....
Preliminary·.
MicroVAX;1s.s;2 .
MicroVAX Bus Reed arid Write Cycles
Figure 30 shC>Ws the MieroVAXbus master read cycletiming !111dFigµreJ1 showsthe MicroVAXb1.1s master write cycle timing, Tal:>le 23 defines the read and write cycle tillling parameters.
ICLKO DAL<31:0>
.x ADDRESS
.i:=: lAAS
!--- !ASA
t 1ASHW
1ASOI 1ASLW
~
I\
1oso1
tosHw
tosLWI
READ DATA VALID
~
I+- tosoz
J21
~ lASDZ
I~ f"t' tosAs
I\
.Jl
IASDB...J
toBLW
-
~ 1WRAS
CS<2:0> BM<3:0>
)3
1B M A S t :
'
~
IASWE .. ...1
IASWB
ltwEDI
J SA~PLE [
~
~
-.i t--tASWR
K
K.'.".., ...
..
Figure 30 ·MicroVAX 78532 MicroVAX Bus Master Read Cycle Timing
1~156
Confidential and Proprietary
-
Figure 3l.~ MjcroVAX 78512 MicttNAX Bus M.aster Write Cycle)'iming
tAAS tASA
t.UDll
t.um
tASDSO
t.um:
tAsmv tASl.111'
DAL< 31:0 > address setup time td AS lisaertfort'
2P~28
-
DAL< 31:0 > address hold time after AS assertion 2P-15
AS assertion to DBE' and DS (read) assertion
3P-15
3P+20
AS assertion to read data valid*
11P-30+8PS
AS assertion to OS assertion (write)
5P-15
5P+20
AS and DBE deassertion to busslave DAL<31:0>
three-state
2P-20
AS deassertion width
4P-25
AS assertion width
12P-15+8PS
Confidential and ·Proprietary
1-157
MicroVAX 785ll
Symbol . De£ioition
Requirements (ns)
Min.
Max.
tARa ~assertion to beginning of ltiSY and 'Ei:tR sample
window
6P-45+8PS
tAm AS assertion to end of RDY and ERR sample window · 6P+ 10 +8PS
tASWll
~/CS<l> holdtimefromAS deassertion
P-20
~ BM< 3:0 > setup time before AS assertion
2P- 25
toaLw DBE assertion width
9P-20+8PS
tDODS DAL< 31:0 > write data setup time to D'S assertion
mm DS 4eassertion to AS and deassertion
P-15
3P-30
DAL< 31:0 > read data hold time after DS
0
deassertion
t 05m fIB assertion to DAL<31:0 > read data valid
8P- 35 +8PS
t0 soo DAL<31:0> writedataholdtimefromDS deassertion
3P-20
tosoz DS deassertion to bus slave DAL<31:0> three-state
o n ¥ bUs cycles
3P-20
tosmiv tDSLWI
tDSLWO
DS deassertion width (read)
m assertion width (read)
DS assertion width (write)
8P- 50
SP- 20 + 8PS 6P- 20 +8PS
tWllDI RDY internal sample window end to DAL<31:0> read data valid
5P-:25
tftAS WR and CS< 1> setup time before AS assertion *Read data is valid if t.u01 Qt tnsm conditions are satisfied.
3P- 35
1-158
Confidential and Proprietary
Preliminary
MicroVAX 78.5)2
Figure 32 shows the MicroVAX bus slave read cycle timing and Figure 33 shows the MicroVAX bus slave write cycle timing. Tuble 24 lists the timing parameters.
Figure 32 ·MicroVAX 78532 MicroVAX Bus Slave Read Cycle Timing
Confidential arid Proprietary
1~159
...
Preliminar y
Figure 33 ·MicroVAX 78532 MicroVAX Bus Slave Write Cycle Timing
.Tuhle 24 ·MicroVAX 785.32 Bus Slave Read and Write Cycle Timin,g Parameters
Symbol Signal Definition
Requirements (ns)
Min..
Max.
tAllE
AS assertion to RDY/ERR assertion for MicroDMA "
*
bus-slave cycles
tASDSR
Required AS assertion to DS assertion delay (read 3P-20 cycles)
3P+25
tASDSW
Required AS assertion to DS assertion delay (write 5P-20
cycles)
5P+25
tASH
AS deassertion width
tASlll! AS deassertion to RDY/ERR deassertion
tBMs
BM< 31:00 > setup time before AS assertion
2P+25 100
2P-25
tnnHll
tmmw
DAL<31:00> data hold time after DS deassertion 0 (slave reads)
Required DAL< .31:00 > hold time after DS deasser- 35
tion on MicroDMA bus-slave writes
1-160
Confidential and.Proprietary
-
Preliminary
Symbol Signal DeSnition
Requirements (ns)
Min.
Max.
toosw Required DAL<31:00> setup time before OS deas- 20 sertion on MicroDMA bus-slave writes
tosASs Required OS" deassertio,n to A'S deassertion delay P-20
tosos OS deassertion to DAL< 31:00 > three-state
55
tHDA
Required DAL<31:00> hold timeafter.AS assertion 35
RDY assertion to DAL<31:00> data valid for -
35
MicroDMA bus-slave rCads
Required DAL<31:00> setup time before AS
15
assertion
t1111H WR/BM<31:00>/CS<2:0> hold time after AS P-25
deassertion
tftS WR/CS< 2:0 > setup time before A'S assertion
3P-50
(memory *tAIU.l time depends on the system conflgutation.
speed, number of cycle slips, type of
transfer, etc.)
·
Figure 34 shows the MicroVAX bus signal timing for the DMA cycle and Thble 25 lists the MicroVAX bus DMA cycle timin,g parameters..
ICLKO
·\.,s----ss·~--
____ _ _t-'OOOT
OAL<31:0>
}--1-------1J11--------"'lr---1-------<,__
Figure 34 ·MicroVAX 78532 MicroVAX Bus DMA Cycle Timing
Confidential and Proprietary
1-161
-
Preliminary
K:LKO
MicroVAX 785)2
Bus. l!lnd OMA Asserted bv Another Device
ICIJ(O
5iiiGi ----...
\"-+-L-,owe-o{.__...-___.----
MtcroDMA Not Using Bus
ICLKO
OMiii------::d ~00v----
OMGO
· MicroOMA Was Not Using Bus
~LKQ~~
~~-
No Interrupt Pending for MicroOMA
Figure 34 ·MicroVAX 78532 MicroVAX Bus DMA Cycle Timing (Continued)
1-162
Confidential and Proprietary
···
Preliminary
tASG
AS and DBE deassertion to DMGOJtssertion
2H'7"".25
End of DMGI s~e windo~ to AS ~~n ct>¥A. :;..
request pending fut MicroDMA)
tDCND Deassert DMR to 'AS/Ds/V/t[/cs<. 1 >/DBE(-BM <3:0> three-state
DeaSsel't DMR to DAL <3i:oo::J·three-state·.
End of DMGI sample window to.~8'~
·
,,_
_,
. i "",. - -- ,,. ,_ ·_;, '
End ofDMra sample wi.ri&w to ~u~tio~ (no -
OMA request ~JorMicroDMA)
Deassert DMGI to~ deassert
0
tWEro IAKEI sample window encl to IAK&5 asserts
*K=the number of microcycles (0, 1, 2, 3, 4) that the sequencer is busy.
10P+20+4PK"
3P+25
P+20 2P+33 :W+JO
60 2P+30
MicroVAX Bus Genentl Tuning Figure 35 shows the general signals for the MicroVAX bus timing and Table 26 lists the general
timing signal parameters.
-ICLKO
I
Figure 35 ·MicroVAX 78532 MicroVAX Bus General Signal Timing Confidential· and Proprietary
1-163
-
MicroVAX 785)2
Symbol SignatDe&nition:. '
Requitementt·(ns)
Min.
Max.
ICLKO to beginning of AS sample window
-35
ICLKO to end of AS sample window
3P+5
ICLKO to beginning ofliDCK sample window
-50
t1un ICLKO to end of IWCK sample window
5
tsws . ICLKO to beginning .of CSi::{V'jill/DMGI/IAKEI -
sample window
3P-50
tm ICLKO to end of CS'[/VBR/DMGi/iAKfil sample 3P+5
window
ICLKO to ER'R/R'i)Y assertion
3P-5
3P+26 ·
l-164
Col'lfidential and Proprietary
MicroVAX 18'32 1/0 Bus Maitet.~ and Write ~yctes Figures 36 and 37 are timing qiagrams for the 1/0 bus maste,r read and write cycles, respectively.
Table.27 lists the sytnP<,>ls and PQta111t:itc:rs for the timing sigrwls.
Figure 36 ·MicroVAX 78532 I/O Bus Master ~ad Cycle Timing
l-165 ------·---------··------·-----
Preliminary
MicroVAX.18l32'
llASDSO \IDBLW
t10SAS
1BM<3:0>
liASBM
t1ASWE t1ASWB .,.,.,.....,....,,,....,...,.,.,.....,.,.,...,.........,.,...........,.,.,.; SAMPLE ..,,...,......,..,......,,,.......,.....,.,.,........,..,.....,....,..,.,..,.....,.....,.. -WINDOW-
Figure37 ·MicroVAX 78532 I/O Bus Master Write C-y,cle Timing
Symbol Signal Definition
Requirements (ns)
Min.
Max.
IDAL < 31:00 > address setup time to IAS assertion 2P-28
tIASA
!DAL< 31:00 > address hold time after IA'S assertion 2P-15
tlASDB IA'S assertion to IDBE and IDS (read) assertion
3P-15
3P+20
I.AS assertion to read data valid
11P-30+4PS
tIAsD50 IAS assertion to IDS assertion (write)
5P-15
5P+20
'iAS and IDBE deassertion to bus slave IDA-
L< 31:00 >three-state
2P-20
t!ASH'IV IAS deassertion width
4P-25
IAS assertion width
12P-15+4PS -
IAS assertion to beginning of IERR/iRi5Y/IDMR sample window
6P-45+4PS
1-166
Confidential and Proprietary
Symbol Signal Definition
Preliminary
tiASWE
tlASBM
tmMAS
tlDBLW
tlOOns
IAS assertion to end of IRDY/IERR/IDMR sample window
m IBM< 3:0> hold time £tom assertion.
6P+ 10+4PS 3P-20
P-20
IBM< 3:6 > setup time. before iAS assertion
P'"'."25
!DBE.assertion width
9J>.,-20+4PS-
IDAL<31:00> writedatasetuptimetoIDSassertionf 3P-30
tJDSn tlDSor tJDSoo
tD>SDz tJDSHW
tIDSLWJ
IDAL < 31:00 > read data hold time after IDS
0
deassertion
IDS assertion toIDAL<31:00> teadditta valid
8P-.3;5+4PS
IDAL<.31:00> write data hold time £tom IDS deassertion
3P-20
IDS deassertion to bus slave IDAL~31:0Q> ~ state on read bus cycles
3P-20
IDS dea&sertion width (read)
8P- 50
IDS assertion width (read)
8P-20+4PS -
tIWEDI tIWllAs
IRDY internal sample window end to IDAL < 31:00 > read data valid
IWR setup time before iAS assertion
3P- 35
5P- 25
Confidential and Proprietary
· 1-167
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ,..u_..~---llli------------·
-~------·----
IF/iOguBreuss.3S8laavi;ied.R3e9aadr.eatnimd Wlntgj~~ Cmycslesfor
the
1/0
bus
slave
read
and
write
.
cycles,
..· ·... .
respectively.
.· .. .
'!able
28 lists the as~ated timing pal-ameters.
IDS
___ ~>
.,
ttARE
Figure 38 ·MicroVAX 78532 I/O Bus Slave Read Cycle Timing
1-168
Confidential and Proprietary
-
MicroVAX 1$jl2
IBM<J:O>
t1AAE
Figure 39 ·MicroVAX 78532 I/O Bus Slave Write Cycle Timing
Symbol Signal Definition
Requnements (ns)
Min.
Max.
tWDll· Required !AS assertion to IDS .assertion delay (tead 3P""20
cycles)
.
3P+25
tIASDSW Required iAS assertion to IDS assertion delay (write 5P- 20
cycles)
.
5P+25
IAS deassertion width
2P+25
100
tuws I'BM < 3:0 > setup time before IAS assertion
P- 25
troom trol>HW
IDAL<31:00> data hQld time aftertm' de~~rtion 0 (slave reads)
ms Required IDAL<31:00> hold time after deasc· 35
sertion on MicroDMA bus-slave writes
trol>SW
Required IDAL< 31:00 > setup time before IDS deas- 20
sertion on MicroDMA bus-slave writes
tll>SASS Required IDS deassertion to iAS deassertion delay P- 20
Confidential and Proprietary
1-169
-
MicroVAX 785}2
Symbol Signal Definition
Requirements (ns)
Min.
Max.
tmsos IDS deassertion to !DAL< 31:00 > three-state
55
tnmA Required !DAL< 31:00 > hold time after iAS assertion 35
tlRDR
IRDY assertion to IDAL< 31:00> data valid for
MicroDMA bus-slave reads
P+35
t1SDA
Required !DAL< 31:00 > setup time before iAS 15
assertion
tl'll'RH ~hold time after iAS deassertion P-25
tnl'RS IWR setup time before iAS assertion
3P-50
I/O Bus DMA Cycle Figure 40is a timing diagram for the I/O bus DMA cycle. Tu.ble 29 lists J./O bus.OMA cycle timing parameters.
ICLKO
J
!MASTER IS DEASSERTED
Figure 40 ·MicroVAX 78532 I/0 Bus DMA Cycle Timing
1-170
Confidential and Proprietary
Symbol SipalDefinition
Requirements (tu)
Min.
Max.
twx: Assert D'»l<i to IAS,IU5!~/IBM<3:0>
·.··40
three-state
IDAL< 31:00> three-state to assert~
Asserted IDMR (internal) sample wind?w. end tp ·~}?.
ii'.i&IG. assertion
. · ··
2P+5
·*
IA'S and IDBE deassertion to lf5MG assertion
4P-25
tIDAs Asserted rnMC:i (internal) sample window end tom -
assertion
mme tlDBM Asserted
(internal) sample wmdow end tO -
IBM< Jib> asreraori ·
.
10P+35+4P:rct 9P+ 4:5 +4PKT
tU>CNo
tlDDDT
Deassert IDMR tu L\S/IDS~IBM < 3:0>
three-state
Deassert li5m tu IDAL < 31~00 > three-state
3P+35 P+30
2P+40
*Maximum value determfue by latency spCdficatlollS. tK= The number of mkroc.ydes (0, 11 2,J, 4)4iat~~u~ ~busy.
J/OBus~Request. Figure41 shows the J/O 'bus
·. ,. ··
t®lsfer
~..u. ·.· est·. ~
t.j.pl.l.ng·.).~·n4
.· . v
$b&
l~l.·lt.i.it;;~
~ng
parameters.
ICLKO
.·~ rm<iii>-------
~
IAS _______):'=======-'-ITllA_JS___-_-:_-,...-:..-'-'---=--iit= -
Figure 41 ·MicroVAX 78532 1/0 Bus Tmttsfer.Rl!quest Timing
Confidential: and Proprietary
1-171
-
Preliminary ..
Symbol
Sign-1Definition
Requftments (tis)
Min.
Max.
torn ITR < 3:0 > assertion
assertionfor requesting
25P+30+4PK*
channel
IB assertion to ITR < 3:0 > deassertion to assure
present requested·bus cycle is last of ITR requested bus cycles (MicroDMA is bus master}
6P..;.35+4PS
*K= The number of microcycles (O, 1, 2, 3, 4) that the sequencer is busy.
J/O Bus General Signal Timing
.
Figure4;lshows the general timing for the I/O bus signals. Table 31 lists 1/0 bus general signal
timing parameters which include sample windows times for the asynchronoqs signals.
ICLKO--..J/
\.__·___,/
SAMPLE WINDOWS FOR ASYNC_H_RONOUS SIGNALS
ICLKO
I
llTER -eoj
~I
---""----~----->.------------\
IRO¥
iERR
----~~
DRIVE TIMES
Figure 42 ·MicroVAX 78532 I/O Bus General Signal Timing
1-172
Confidential and Proprietary
·-
Pl'eliminary
Table .Jl ·;MicroVAX 78S32 J/O Bus General Timing Parameters
Symbol Signal Definition
ReqUireinents (ns)
Min. ·
Max.
ICLKO to IR asserted.
P-12
P+25
ICLKO to begjn.njng ofIA:§ sample window
-35
ICLKO.!o.e~,?fjAS'.samplewind.my
3P+5
ICLKO tc>~~iitDY~ple w~dmv ~J}t'.5
end
..
,
,
'· '
tuwa
ICLKO to ~ ofi'.t'R<l:Oi>/tREG ~;
window
·
· ··
·
> ICLKO
to~of
iIR<J:O>
~
~ -
s- an-'l_..ple\·.r.indow
ICLKO to end of :mi< 3:0 sample wfudo\v
P + 5
ICLKO to iERRJtimY assertion
--50 P-50 3P+26
. Interfacing Requir¢!Jlellts
MicroDMA interface designs vary depending on the type of peripherals being interfaced. Figure·4i3 is a simplified example of a typical interface application. The MicroDMA is used as an interface between the MicroVAX CPU and an 8-bit peripheral chip similar to an Intel* device. *Intel is a trademark of Intel Corporation.
An address latch and decoder enables the MicroDMA and other devices on the MicroVAX bus. l£ more than one device on the MicroVAX bus can respond to a DMA or an interrupt acknowledge in cycle, the devices are connected as a daisychain as shown. The peripheral chip has separate read and
write controls. The assertion of the IWR and IDS lines indicates that a write operation is required.
The assertion of the IDS signal without the IWR being asserted indicates that a read operation is required. The peripheral interface includes buffers for the IDAL data and addresses, and a decoder for asserting signals such as DACK (a OMA data transfer acknowledgment signal), ~ (a peripheral chip select signal), and peripheral chip register addressing signals.·The !MASTER signal is asserted (MicroDMA is the default master of the I/O bus) and the IDMR signal is deasserted so that another
device cannot request control of the I/O bus.
Timing for the interfac.-e is from a common 40-MHz clock. The timing logic used depends on the type of peripheral chip(s) being interfaced and determines when an I/O bus cycle can be terminated and when IRDY line should be asserted. All the chips are reset by common reset circuit.
1-173
·-
TO OTHER DEVICES IN OAtSY Cl-IAIN
fiMGO iAKEi
DEVICE (DAISY CHAINED)
CHIP SELECT
CLKI
Preliminary
MICROVAX CPU
~
ilM1l cs<2> l5hfH:
------l ics<1I:0>m mwm
>-+--+'--<>--+-------~--
TO/FROM OTHER
MICROVAX aus
DEVICES
1---t--t--------~
.liMffii l .IAAll 1 !il.ll< · ··j mm DiIT ffi§
CU(! r..tran Diif,i IR0-0:0>
1 - - + - - - - . . , . . . . - l---+---...-~-----
I A< I DAL<31 :00:>
llmi'
Cs<TO>
BM<'fii>
MlCROOMA
iWR iOBe
I I
IOAL<31:00>
- 10Al<7"0> DOE
3·STATE BUFFER
AESEr
s.en PERIPHERAL CINTEll
cs
DEVICE INTERFACE SIGNALS
Figure 4,3 ·MicroVAX 78532 Typical MicroDMA Interfacing
1-174
Confidential and Proprietary
· FeatUl'es
· Compatible with the MicroVAX 78032 CPU
· 32-bit memory data organization · Controls operation of 4 Mbytes of 256K by
1-bit dynamic RAMs
· Generates multip.kxed address, RAS and CAS signals for as many as four banks of memory
· Two access speeds for use with different-
speed dynamic RAMs
· Four refresh modes
· Supports battery backup refresh · Suppo~ patjty etJ:Qr reporting with address
capture · Bus timeout error detection and reporting · Generates 100-Hz interval dock · nouhl~~~ CM()~ t~ology
· Minimum. parts count memory interface
· Description
The MicroVAX 78584 Dynamic Ram Controller (DYRC) provides a low cost interface between the MicroVAX 78032 CPU and 4 Mbytes of dynamic RAM (DRAM). The DYRC supports 256Kby 1-bit DRAMs and supplies mcltiplexed address, timing strobes, and refresh/access arbitration oontfQI.
Two operating speeds allow the designer to use different speed DRAMs. The choice 0£ speed
determines whether memory errors are reported during the same cycle or a following cycle. Error
address capture logic is implemented in the ,DYRC. to aid in the reporting of memory errors. The DYRC also provides battery backup refresh support.,;~ lOO-Hz interval timer, and bus timeQut logic
to report nonexistent addresses or no response to thee address strobe. Figure 1 is a block diagram of the MicroVAX 78584 DYRC.
~--+---+----+----+ WAmV
.---+--~+---+----+m
/~~~".--~~-'-..-.
~
OAl<ll):(l(I>
0v iNffiM
Figure 1 ·MicroVAX 78584 DYRC Block Diagram Confide11tW and Proprietary
1-175
Using the DYRC results in a nilnim4m part count 32-bit DRAM memory interface that requires a single 5-Vdc supply and is compatible with the MicroVAX 78032 CPU.
· Pin and Signal Description
This· section provides a description of the input and output signals and power and ground connections used by the MicroVAX78584DYRC. The signal pin assignments are shown in Figure 2 and summarized in Table 1.
EAS(! CAS1
CAS2
CAS3 SPARE
DALO DAll ADO DAL2
vss
VDD DAL3
ADl DAL4 DAL5
AD2 DAL6 DAL7
AD3 DAL8 DAL9
VPARITY ~ REFSELO RINPRG 20MHZ
vss
Rs
iiAs3
As
RASO
PARIN i'EST REFSELl RROST Si:OW VDD
m
PFAIL RAS2 RASl SfLECr
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
7&
53
76
52
77
51
78
50
79
49
ao
48
81
47
82
46
B3
45
84
44
MicroVAX 78584
DYNAMIC RAM
43
CONTROLLER
42
3
41
4
40
5
39
6
38
37
8
36
9
35
10
34
11
33
12 13 14 15 16 1 7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AD4
DALl 1 BMO
BM2
RESET
VDD
ADY
WR
CS2
cso
5v
DAL10 INTTIM BM1
BM3
vss
CLKI
ERR
EPS
CS1 ENBTMR
BSl
BSO
NC NC NC 0AU9 DALfB ADS DAL17 DAL16 VDD
vss
AD7 DAL15 DAL14 AD6 DAL13 DAL12 ADS OUTENB
DiiE
Figure 2 ·MicroVAX 78584 Pin Assignments
1-176
Confidentialand Proprietary
...
Preliminary
Pin
Signal·
48,47,45,44, 40,39 ,37,36, 14,13,11,10, 8, 7,5,4,2,83
DAL<l9:00>
Input/Output
input/output
66
SLOW
in:(lut
45
SELEC'f
input
61
~
input
62
CSR
input
57
AS
input
28-30
CS.<2:0>
input
19-16
BM<J:O>
input
53,52
BS<l:O>
input
46,41,38,35 AD<8:0> 12,9,6,3,82
59,58,56,55 RAS<3:6>
output output
78-75
CAS<3:0> output
24
output
34
OUTENB
input
Function/Definition
Data address lines < 19:00>-During the address pottion of a memory cycle, the address on DAL< 19:02 > is used to form the row and column addresses.
The D~j):l5:00> lines. are used for ~
transfer of information to and from the command status and fault address registers.
Slow-Matdies the operating speed of the
DYRC with the speed of slower memory chips.
Select-,Sel.ecis the· chip for.~ memory acce~s cycle. ·
Register ge:lect-Selects a(,:CCSS to the two internal registers.
Comma~d ..·status regis.t~ select-Selects which ohhe two internarfegi.sters is to be accessed.
Addres~ strdbe-A stro&; ~rom the CPU that latches. address and control information into the DYR<D and starts a RAM access cycle if the
SELECT signal is asserted or an internal register aq:ess,it,the RS·~ ~..~erted.
Control status-Determines the type of bus cycle to be performed.
Byte m,asks-Selects the,' byte(s) to b~ accessed.
Bank se~-""Selects the ·haa:lk of memory to
be accessed.
Address <8;0 >-Providesthe multiplexed memory~dress to theR.1\¥array.
Row address strobe-Strobe signals used to latch the row address into the men10ry bank
selected bv.,BS < 1:0> ..
Column address strobe-Strobe signals used to latch the column address into the byte(s) of
the memory array selected by BM< 3:0 > .
Ready-Synchronizes the data transfers.
Outputenable-"'-Enables the DYRC outputs.
Confidential and Proprietary «&QW_ik~!l!lllll1'7~-IRl!i-UJt............._.,...1----·-llliflo_PI....- - - - - · - - - · - · - - - - - - ·
1-177
-
Pin 26 33
70,69 27
68
67 31 74 25 73
32 23
65
71
15
Preliminary
MicroV.A¥;·1s.S$4
Signal
WR
DBE
I.nptat/Outp1:1t
input
input
REFSEL< 1:0 > input
EPS
input
RRQST RINPRG ENBTMR PARIN ERR VPARITY
input output input input output output
DV CLKI
output input
20MHZ
input
INCLKSEL
input
INTTIM
output
Function/Definition.
Writ;e..,...Indicates the direction of data trans·
fer on the DAL< 19:00 > lines.
Data buffer enable-Enables the three-state
DAL< 19:00 > lines drivers during an inter-
nal register read.
Refresh select-Select one of four refresh
modes.
External processor strobe-Provides a refresh request· synchronization for processors that use external processor cycles.
Refresh request-Used by external logic to request a refresh cycle.
Refresh in progress-Indicates that a refresh cycle is in progress.
Enable timeout timer-Enables the bus timeout function.
Parity in-Used by external logic to report a parity error to the DYRC.
Error-Indicates a parity error or bus timeout condition to the CPU.
Valid parity-For use by diagnostics to verify the operation of parity logic by forcing it to write a wrong parity.
Data valid-Indicates that the data being written to or read from memory is valid.
Clock input-A clock input that provides timing for the DYRC and synchronization with the CPU.
20 MHz-An optional clock input for generating 100-Hz internal timing and bus timeout timing.
Internal dock select-Selects the clock source to be used for generating internal timing and bus timeout timing.
Internal timer-A 100-Hz clock that can be used to support operating system timing functions.
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Confidential and Proprietary
Pin
Signal
60
input
20
1,22,43,64 Von 21,42,63,84 Vss
input
input input input
Powerfail-Continues memory refresh opera"' tion during a powerfail conditic>n when
refresh mode 0 or l is selected and memory . ~b~t~ry backup.
Reset"'"-'Sets the 'nYRC to a known initial state. ~l~g~--::-Power ~µpply voltage.
Ground......Grouncl reference.
Input and Output Signals
.....·...
Data address lines (DAL< 19:00 >)-These lines .~ ~sed .·~·form the multiprexed address for the
256K dynamic memory chips and to transfer in£orfI1atiO~;l)etwttn the CPU and the two internll!
and registers. During a memory read or write cycle, fui~s OAt;<I9:02 > are latched into the DYRC by
the assertion of the ~input. The multiplexed row mlum.n address is formed from this
information. Lines DAL< 19, 17, l5, l3, ll, 09, 07, 05, 03 > areusedtocfotmilie·9-bitroi!radd:ress
and lines DAL< 18, 16, 14, 12, 10, 08, 06, 04, 02> are used to form the9-bitcolumn address. The
DAL< 15:00 > lines are used to transfer information between the two internal registers and the
CPU. Access to the internal registers is controlled by the RS and CSR inpu!~:
Input Signals
. ..
Select (SELECT)-This signal, when a.Sserted by· e:Xternal adareSs decode logk, enables a memory
access cycle when the AS signa1.isasserted.TheCAS<3:0>·linesand theRi5Y ari,d J)Vsignals are
enabled when this input is asserted.
Register select (RS}-This signal, when asserted by external address decode logic, enables a read or
write access to the internal registers of the DYRC. The two int¢rnal registers can be positioned in
the 1/0 page or mapped into memory space by.the designer. The'RS: and SELECT inputs must be
mutually exclusive.
1 · ·: '
· .
Output enable (OUTENB)-This signal. is asserted to ~lc:ftm.following outputs: AD<$:!)>,
RAS<3:0>, CAS<3:0>, DAL< 15:00>, Rm, :0V, ill'&PRG, i!RR, IN"I'TIM, and VPARITY. lf the OUTENB input is not asserted, these outputs are ·~~nee. Address strobe {AS)-This signal, when asserted, latch~ t~ P~L < 19:02 > aed BS< 1:0 > line information into the DYRC. The assertion of the AS bJput ~s a memory ~ecess cycle if the SELECT input is asserted or an internal register access cycle if the RS input is asserted. The AS
inputis also used tointernally synchronize the refresh logic. ,
External processor stmbe (EPS)-This signal and the AS and SELECT signal.Sare used to
internally synchronize the refresh logic.
Contml status lines (CS< 2:0 >)-These signals are decoded by the DYRC with the WR input to monitor the type of bus cycle being performed. Table 2 lists the bus cycle assignments and indicates if a memory access is allowed for the cycle selected.
.Confidential. and Propr.ietary
1-179
···
Preliminary
MicroVAX78584
Ta&ie''2 · Mim>VAX~78'84 Bus Cjrcle Assignments
WR CSLine*
Bus C,de Type
2
1
0
H
L
L
L
reserved
H
L
L
H
reserved
H
L
H
L
reserved
H
L
H
H
interrupt acknowledge
H
H
L
L
read (instruction)
H
H
L
H
read lock
H
H
H
L
read (data, modify intent)
H
H
H
H
read (data, no modify intent)
L
L
L
L
reserved
L
L
L
H
reserved
L
L
H
L
reserved
L
L
H
H
reserved
L
H
L
L
reserved
t
H
L. H
write unlock
L
H
H
L
reserved
L
H
H
H
write (data)
*H =high level, L =low level.
Memory Access
No No No No Yes Yes Yes Yes
No No No No No Yes No Yes
Byte masks (BM< 3:0 >)-These signals are used to generate the information on the CAS < 3:0 >
outputs. During a memory read or write cycle, the byte mask BM< 3:0 > lines that are asserted
result in the corresponding CAS <J:O > line being asserted.
.
Bank select (BS< bO >)-These signals select one of the four banks of memory for access .by selecting the RAS line to be asserted as described in Table J.
Table 3 · MicroVAX 78584 Bank Select Decoding
BS Line*
1
0
RAS Line
L
L
RAS<O>
L
H
RAS<i>
H
L
RAS<2>
H
H
RAS<3>
*H =high .level, L =low level.
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...
Preliminary
Contrt>l iitatust"eglsttt (CSR)-This signalis used with the RS input to select the internal register to be·aCc:essed. When the~inputis a5serted, the control status register is selected. When the CSR input is riot asserted, the fauluddtess register is selected.
Write <fl)-This signal is used by the DYRC to detect a read or a Write bus cycle.
Data buffet enable (DBE)_:,Thls sigrtal is used With the RS signal to enable tl'ie three-state
DAL< 15:00> drivers when one of the interfiah~gistetii is beingrread,
Refresh select (REFSEL<l:O>)-These lines are~.to Rlect one ofthe iour ref~h lncldeS. The DYRC selects the refi:esh .mode wbeJJi th~:~ipput;..is a&se~. Th~ pins shoulc1.f,e
connected to the proper voltage level. Tuble 4 lists the refresh mode selections.
R,EFS~L J,ine
1
0
0
0
0
0
l
l
1.
0
2
l
l
J.
Refresh iequest.(RRQsT)~rbj$·sjgnal is ·.·~~.b)r.ext~~ic:~o,~t1~t ~·memo~ refresh
this cycle.when refte~ mode.2.i~ ~lecteP,. Ut~ ~YRC js.· ~~~llS·ili:~~~.~~eOi, l, Br}..lltld
will be signalis asseM:ed· an extra refresh cycle
pei;formed. ,f1oWever, this.&:ies. not have~ affect
the on refresh interValpec~~se ffic:int&rialc<>~ntersof~ ~9 arenqt·~· .. ,,,· .t.'
Slow (SLOW)-This sign~ is ~cl to mat~ th~ p~rai· . . . . ~f'the PY~C'with t&operi.ting
s~d of the DRAMshe1ng ti$ed. ~n assefte8; the . ·.. ·· .··.· . ~ ·Wi~tli ls'.i.ncre~ arid the
CAS<3:0> .and.RiJY signals aretldayed, alloWlng theDYKC'h5bius'edWiths1owerDllt\.Ms. This
pin showd be connected t0 Vun <>!Yu·
·
Enable. timeout.·.ti1net (ENlftMil) ... When. asserte4,··this ~~W.bl~~ ·the bus titneoot.timer.
When enabled and t:he XS irlpuf has been as8erted'for 25 µs,' th;e··~c will as'sert the 'mm o\itj:>ut
to notify the CPU of an error. The CPU is then required to examine the CSR to determine tlle cause of the error. This pii'l should be conrlei:ted:fO':V00 orV~s; ·. ·
Parity in (PARIN)-This signal is asserted by external parity checking logic wh~11. a parity erl:or has
occurred. If this signal is not·. used, it· should· be coonected.:to Vuo' throUgh ari e:x:temal pullup
resistor.
ClOck input (CLKI);...;.;This is the input dockthat provides thebWic timing'tfffereriCe for the·DYRC.
20 MHz (20MHZ)-Thls clock is used to generate the 100~Hz iNTrlM output and the 25 µs bus
timeout timer if selected by the INCLKSEL input.
..
Internal clock select (INCLKSEL)-This signal selects the clock source to be used to generate the 100-Hz INTIIM output and 25-IJI& bus timeout timer:. When the INCLKSEL signal is asserted, the CLKI divided by two is selected as the dock source. When the INCLKSEL signal is deasserted, the
20MHZ input is selected as the dock source. This pin should be connected to V00 or Vss·
Confid¢ntial and Proprietary
1-181
...
·Preliminary
MicroVAX 7es4
lom Powerfail (PF.i\iL)-This ©.gnalis asse~~ by external to notify t~ DYR<:;.pf a system power
failure and that the DYRC is to continue refreshing memt;iry frotll ab~ckup power source. This signal is functional in refresh modes 0 or 1 only. When thi: DYRC is used without a backup power source, the PFAIL input must 1:>e pulled up by an external resistor. Reset (RESET)-This line is asserted to set the DYRC to a known state.
Voltage (VDD)-Connects to the power supply voltage.
Ground (V55)-Connects to the ground refet¢nce.
Test (TEST)-Resetved for manufacturing use. This pin must be connected to VDD·
Output Signals
Address (AD< 8:0 >)-These are the multiplexed memory address outputs. When the selected
RAS< 3:0 > output is asserted, these lines contain the row address for the DRAMs. When the selected CAS < 3:0 > output.or outputs are aSlierted, lines AD <.8:0 > contain the column address
for the DRAMs. These outputs cannot drive the DRAMs directly. Therefore a memory driver is
required between these lines and the memory array. Each line is capable of driving up to four
memory driver inputs.
Row address strobe ('=RA..,...,,,S-<"""'3,....:0""">-)-These signals are used to latch the row address into the
selected bank of memory. The RAS<3:0> line or lines to be asserted are selected by the
BS< l:O > inputs or by the refresh logic. The RAZ< 3:0 > outputs cannot directly drive the
DRAMs. A memory driver is required between these lines and the memory array. Each line is
capable of driving up to four memory driver inputs.
.
Column address strobe (CAS < 3:0 >)-These signals are used to latch the column address into the selected byte(s) of the memory array. The lines to be asserted are selected by the BM< 3:0 > inputs.
'these outputs cannot drive the DRAMs directly. Therefore a memory driver is required between
these lin~s and the memory array. Each line is capable of driving up to foU:r memory driver inputs.
Ready (IIDY}-This signal is asserted to notify the controlling processor that the current memory
access bus cycle or internal register data transfer bus cycle can be completed.
.
Data valid (i}V)-This ·signal is asserted by the DYRC to notify the external error detection and correction logic that the data being read from or written to memory is stable.
Enor {ERR)-This signal is asserted by the DYRC to notify the CPU that the parity checkinglogic has reported a parity error to the DYRC by asserting the PARIN signal or that a bus .timeout condition has occurred. When there is more than one DYRC ina system, only one should report a bus timeout.
Refresh in progress (RINPRG)-This signal is asserted to notify the eitemal logic that a refresh cycle is in progress.
Interval timer (INT'tiM)-A 100-Hz timer for use by the operating system.
Valid parity (VPARITY)-This signal can be used by diagnostics to verify the operation of the external parity checking logic. This signal is controlled by the write wrong parity (WWP) bit in the comm.and status register. When VPARITY is asserted, the parity logic should function normally. When deasserted, the parity should be inverted.
1-182
Confidential and Proprietary
·-
. Funttional Description
MicroVAX,,78j84 ·
'This section describes the basic operation and organization of the MicroVAX 78584 DYRC.
Memory OrganiatM>n . The DYRC supports a .32"bit, byte oriented,memory data orga~tion.. Because of the byte orientation of the mern<>cy array, paritr, ~ecking shoqld be perform¢d on each by:tt:. This ~lllts in
a36-bit-wide memory W:ray with eisJu da~ bits pet byte. plU$ cme parity::bit. T~ P¥RC supports
up tofour banks of memory. Each~c.;ontains.1 Mbytewhep2~6J( dylWllic RAJ4s are u~for a
maximum memory array of 4 Mbytes pet DYRC.
JteaNWrite Operatioµ
For. a read/write operation, the DYRC provides the multiplexed memory address, row ad9ress strobe, and colum~ address strobe to the memory array. fr also genera~s the RJ:)Ysigmtl reqUired for bus cycle termination. The timing infortlU!.tionfor a read or ~ite\fycle is in the Specifictltiort
section.
A memory read or write cycle is initiated by the assertion ofthe SEL~C:T and AS signal~. If a
refresh request is not pending or in progress' the DYRC ~fers the row ad~ss on the memory
address bus and assert t~ RAS< H5 > otiqmt as selectedt;y~s< l:O >JipeS. After the sPecif~
row address hold time, the DYRC transfers the colilmn addtess· onto the' memory add:reSs bus and
asserts the CAS <3:0> outputs as selected by the BM <.3r-O >·lines. The DYRC asserts ·the RDY signal to notify the CPU that'the current bus cytle caribe tompleted. The assertion ofthe RDY line
is determined by the type of memory cycle (slow. odllSt) being performed. The data on the DAL <Jl:O > lines rs the data'to be written inliti!>r read from.the accessed DRAM chips~ The DV
signal is asserted to notify the external logic, such as parity or EDAC logic, that the data is valid. The AS signal is deasser.ted and the memoey access is compl~..The DYI\<i,: l;ISes the ''early write" mode of the DRAM for writing data into memory..
If a memory refresh is pending or in progress when the· D'ilRC iii selected and the AS signal is asserted, the·tnemoryaccess \Vill beddayed untilthe refresh cycle is oompleted. The MicroVAx bus
cycle is stretched by the delay of the as8ertion·t)f the R15'Y signal ft6'n:l the DYRC.
Refresh Operation The AS, SELECT, EPS, and PFAfL inputs are used by the DYRC to arbitrate a refresh cycle. The DYRC performs the arbitration and control for the refresh cycles that may be started by the following:
· Detecting thed~ssertion of the AS signal when clieSELECTSigrihl is asserted. The D$Cknows
when the p~t as:;ertion of the AS signal will ocCur. This allbws time for the DYRC to arbitra,te
between a refresh cycle and the next memory cycle. · ·
· Detecting the deassertion of RPS. TheDYI\Cwill perform the:necessary refresh cycles during the
execution of long floating-point instructions.
· Detecting the assertion of the AS sigQalwhen the SELECT or Ers are deas~ for an extended
period of time (62.5 µs maximum). Four consecutive rows will be refreshed during the refresh
cyde. This allows refresh cycles to be performed while the CPU'is. commuriicating with slo\V
peripheral devices.
··
Confidential and Proprietary
1-183
1111110
Preliminary
· At the assertion of the PFAIL signal. This condition inhibits memory accesses other thM refresh
source. . . . cycles. When the PFAIL signalis asserted, the aut~matic refresh occurs only when refresh mode 0
or 1 is selected and there is a badmp power
A refresh cycle consists of transferring the refresh address onto the memory address bus, asserting
the RAS< 3:0 > line information, and incrementing the refresh row address counter by 1 until four
rows have been refreshed. While a refresh cycle is in progress, the DYRC asserts the RINPRG signal.
The refresh cycle is completed when the RAS< 3:0 > lines and the RINPRG signal are deasserted.
Any· memory accesses attempted during ·a refresh operation· are deferred until the refresh is
completed.
DMA devices that access memory controlled by the DYRC must consider the latency time that may occur as a result of a refresh cycle. The DMA device can use RINPRG to detect a refresh cycle in
progress.
The four refresh modes that are selected by the REFSEL< 1:0> lines are listed in Table 2. The
refresh mode to be used is selected when the mE'i" line is asserted.
·
Mode 0-In this mode refresh operation is automatically controlled by the DYRC. The DYRC will ·refresh 256 consecutive locations in 4 ms when the clock input is. 40 MH,z. During the powerup
sequence, the memory anay is initialized with eight refresh cycles before any access is permitted.
The RINPRG output will be asserted during refresh cycles.
Mode 1.,.,-In this mode, refresh operation is automatically controlled by the DYRC. The DYRC will refresh 512 consecutive locations in 4 ms when the dock input is 40 MHz or 256 consecutive locations in 4 ms when it is 20 MHz. During powerup, the memory array is initialized with eight
refresh cycles before any access is permitted. The RINPRG output will be asserted during refresh
cycles.
Mode 2-ln this mode, refresh operation is controlled by external logic. The external logic
requests a refresh cycle by asserting the RRQST input. ·The DYRC arbitrates the refresh cycle, asserts the RINPRG output, performs the four refresh cycles, and increments the.refresh counter.
The RINPRG output can be used to dear the RRQST signal. During the powerup sequence, the
memory array is initialized with eight refresh cycles before any access is permitted. Automatic refresh is not performed after powerup.
Mode 3-In this mode the refresh operation is disabled and no refresh will occur during the
powerup sequence.
Internal Registers The. DYRC contains two 16-bit registers. The control and status register (CSR) is a read/write
register .that is used to transfer control and status information between the processor and the DYRC. The fault address register (FAR) is a read-only register that is .used to store the address of the page in memory being accessed at the time a parity error is reported. Access to the CSR and FAR is controlled bythe RS; CSR, and WR inputs. The RS input selects the DYRC for a register access, the
CSR input selects the register to be accessed, and the WR input determines whether a read or write transaction is to be performed. The addresses for the CSR and FAR registers must be on a longword boundary. Because these registers are 16 bits wide, they must be accessed using word instroct1ons.
Control Status Register-The control status register (~SR) enables parity erroi; support, reports parity a~d bus timeout status, and forces a wrong parity for diagnostic purposes. During the initiai powerup sequence or at the assertion of the RESET input, this register is cleared. Figure·J shows
the CSR register format and Table 5 describes the function of each bit.
1-184
Confidential and Proprietary
,READ AS.O':s
ERRSTAT 1- ENB I -
WWP
BTO
Figure J· MieroVAX 87584 Conoot Srams Ritfister Format··'
.00
I
1able 5 ·MicroVAX 81584 Control Status Register DescriP,~ .
15
is a ERRSTAT (Error statUs)~Trus bit used to report parity error afld is set when the ENR
(bit 13) is set and the PARiN input is asserted. When set, this bit indicates that a parity
erroi: has IJet!~ detf!<.:ted_by the external parity logic, This bit is cleared when the CSR is
read or tbe~inputis4ssertetl.
14 WWP (Write wrong parity)-This bit is set and cleared by software,;When set, it causes
:I.·:.-_;. the VPARttY buf:$>ut to be qea5setted; Whi:;n cleated~ the vPA:l(trY pµtput is lisserted.
lCoagnk. bbey.ufos..ercd.iwd..J.u..·r.w·i·n.r..godniga{pw~·t,_..·.o·ys.tieC..s..leopaenr;adtlqwn~S.·e..:.·n·_..t.to.h. e .. ,. , i(p)~~.u,.mt tisiOan~.·soerft.te.hd.e ext..ernal parity
13
ENB (I,:::~bl~h-·11itsbit.is,µsec1.to eAAhlethtj J,"epo~of~~~rs.:. set.ti? enable the
parity 'error reporqng fiiiiction of the'!m:itc; ~~ dearec1 to tliSable the parity error
aresspeortreti<nlg.
~cti~n
.J
·.·
in~
. ·. .
the E_~~:J:'AT
.
-
. - .. - · ·
fl\li.· "t:Je~
· ·· -· ···
when ,the
Imm
input
is
When repbrtiitg ~. pafitferrottb thil:;~, the I)YRC d&ables the' parityerror reporting
function by clearing·tlili 'i;,it. 'This is, cfu'~tC> keey'irt9,J,tiPJe parity ei;rors from·eorrupting
the fault address in.the FAR. After handling a parity; error software must reenable parity
error reporting by settingthishit.
12
BTO (BU$ tim,c:out)-Wh® set,Jrns bit indic~te~.tluit Jbe bu.$ has timed i:nit. This bit is
set enabled when the ENBTMR input is asserted. This bit is cleared when the CSR is read
or the RESET input is asserted.
11:00 RAZ (Read as zeros)-Not used.
Confid.ential and Proprietary
1-185
-
Preliminary
MicroVAX 78S84
Fault Address Register..,...The fault address register (FARUs ~~rily re~ter tha't is used to store
the address of the page in memory being accessed when a parity error is reported to the DYRC. This register is cleared wheh the RESET input is asserted. Figure 4 shows the FAR format and Table 6 describes the function of each bit.
15 14 13 12 11 10
00
II I I
I
'~'--~~-~~---J I ... ERRSTAT
RESERVED
DAL<19:09>
BS<1:0>
Figure 4 ·MicroVAX 78584 Fault Address Register Format
Table 6 · MicroVAX 78584 Fault Address Regist.er. Description
Bit Description
15
ERRSTAT (Parity error status)-This bit is set when external parity logic detects a parity
error and asserts the PARIN input. When set, register contents cannot be changed.
Cleared by a processor read transaction or when the .RESET input is asserted.
14:13
BS< 1:0 > (Bank select)-These bits contain the value of the BS< 1:0 > information at the time the PARIN input was asserted. This value can be used to determine the bank of memory with the parity error. Cleared when the RESET input is asserted.
12:11 RESERVED (Reserved)-These bits are cleared at powerup and set after the first memory operation. They remain set until the RESET input is asse.rted.
10:00 DAL< 19:09 > (Data/Address< 19:09 >)-These bits contain the address of the page in memory being accessed at the time the PARIN pin was asserted. Cleared when the RESET
. inpu,t is asserted.
Error Reporting The DYRC reports memory parity errors, bus timeout, and nonexistent memory address errors to the CPU. For a memory parity erroi; the DYRC provides the error reporting interface between external parity checking logic and the CPU. TI'le bus timeout logic monitors the MicroVAX bus activity and reports a timeout error when the addressed device does not respond by asserting the RDY signal. When an error has been reported to the CPU by the DYRC, the error handling routine must read the CSR to determine the type of error being reported.
Parity Error Reporting-The DYRC provides the interface between external parity checking logic and the MicroVAX 78032 CPU for reporting a parity error. Parity error reporting is enabled by setting the ENB bit in the CSR. When a parity error has been detected by external parity checking logic, it asserts the PARIN input of the DYRC. This causes the page address to be captured in the FAR, the ERRSTAT bit in the CSR to be set, the parity error logic to be disabled by the clearing of the ENB bit in the CSR, and the CPU to be notified of an error by asserting the ERR output. The
1-186
Confidential and Proprietary
-
Preliminary
MicroVAX ·!18'84
DYRC will hold the ERR signal asserted until the next data stream access to memory. This ensures
that the CPU will detect the error condition and respond. After responding to the parity error, the
software must reenable the parity error logic by setting the ENB bit in the CSR. Refer to the
MicroVAX 78032 Central Processing Unit User's Guide for information on error handling. The parity
error reporting logic also aids parity and error detection and correction (EDAC) designs by
providing a data valid strobe. The rN strobe can be used by external parity or EDAC logic as an
indicator that the cl-a.ta on the bus is valid.
· ·
Bus timeout error-The bus timeout logic provides a means to monitor the MicroVAX ~s activity
and to notify the CPU ofa nonexistent memory error or some other error that causes AS to be
asserted for more than 25 µs. Proper operation of this logic requires a 40·MHz clock input with the
INCLKSEL input asserted or a 20-MHz ini)ut with tbe if\tanEt input deassetted. The bus timeout logic is enabled or disabled by conn«ting the ENBTMl{inp\it toVilo or Vss. When the bus
timeout logic is enabled and the AS input has been asserted for more than 25 µs, the DYRC will set
the IITO bit in the CSR and assert the 'ERR signal.
Interval Timer The interval timer provides a 100-Hz output (IN'I'fiM) that can be used to support operating system timing functions. The clock source for this. outpl,lt is selected by the INCLKSEL input. When this input is asserted, the clock squrce (CLKi') is divided by two and the output is the dock
source for the timing circuit. When. not asserted, the 20.:Ml:Iz input is the clock source for the timing circuit. The IN'ITIM output will be lOOHz when the input is 40 MHz or the 20 MHz input
is20 MHz.
Powerfail Standby
Powerfail standby. is functional .only when ref.re.sh mode 0 Ol' 1. is selected. The powerfail logic
provides automatic memory refresh for powerfail conditions when memory and the DYRC have a
backup power source. Powerfail standby operation is enabled by the assertion of the PFAIL input.
This input must be asserted by external logic before the system power supply becomes unstable.
When asserted and refresh mode 0 or 1 is selected, any activity on :the MicroVAX bus is ipored,
and the DYRC continues to refresh memory until .the ~ :signal. is deasserted or the backup
power supply fails. The PFAIL signal should be deasserted a..mll.xh'llum of 10 µs before pprmal
operation is resumed.
·· . ·
· ·
Reset/Powerup
The DYRC will resetits internal counters and timing sequencers when .the lmSET input is asset:ted
for a minimum of 800 µsand the clock input is operating. When the RESET inputis deasserted, the DYRC will initialize theDAAMs with eight refresh cycles.Me!nory·ac.cess is delayed un~.il the
completion of the eight RAS-only refreshes. The DRAM data will belost when 'itESEi' is amted.
When power is first applied totheDYRC~ the RESET input must be asserted fot a minimum of 800 µs after the power supply voltages have stabilize&
· Interfacing Requttements
A typical MicroVAX CPU and DYRC interface configuration is shown in Figure 5. The external logic required to interface a dynamic memory system is also shown. The actual logic may vary according the requirements of the system. The typical external components consist of external address decode logic, data bus transceivers with parity, memory address bus drivers, RAS and CAS drivers, and a write buffer.
Confidential and Proprietary
1-187
----·~-··----·----------------------·----·-----·--·-----·--·
·-·
CKLI
Preliminary
MicroVAX 78584
l
1
BM<3:0>
- - - - - - 20 MHZ
M------ iNCLKSEL
I------- DV
14------ REFSEL<l:O>
~~~AOVAX t - - - : - E - - - - - - - - - - 9 ' 1
AS
DYRC
14------Pf!Ai[
M------ Si:OW M - - - - - - EiiiB'fiiiiR
SYSTEM CONTROL SIGNALS
CS<2:0>
I
11
.....,....__ _ _ _ _ OUTENB
1------...... RINAPG ------RiiQST
KA~<31~),.._
ADDRESS DECODE
SELECT
............__.........I ... I I .... LO\'JIC
"'""-1------- CSA
M .... ------ Rs
WR
DBE
OAL<19:00>
~...., ADDR<B:O>
BS<l:O> DBE
RAS<3:0> RAS<3:0>
r---"'\ CAS<3:0>
CAS<3:0>
RAM BANKS
WAT t---1
f"""V'.._01_N__D~o~u_ T _~
ENB
____j~
.._
_.
BUFFER
''\I ..___ _ _ _ _ _ DAL<31 :00>
~,./'!~
B
A ( BDAL<31:00>
Y
TRANSCEIVERS ~ READ/WRITE DATA
DIR
1
Figure 5 ·MicroVAX 78584 Typical MicroVAX CPU and DYRC Interface Configuration
Dynamic RAM Requit'ements The DYRC supports 256K dynamic RAMs that have the following characteristics. · Multiplexed row and column ad.dresses
· 9-bit memory ad.dress bus
· Data in and three-state data out to allow common input/output · RAS only refresh · 256 count or 512 count 4 ms refresh
The dynamic RAMs that meet the timing specifications in Table 7 will allow the MicroVAX 78032
CPU to access memory with no wait states or one cycle slip.
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...
Preliminary
MicroVJ\X.78$84
Table 7 ·MicroVAX 78584 Dynamic RAM Specificatiolls
Parameter
Access with
no cycle slip (ns)
Min.
Max.
Access with
one c:ydulip .(ns)
Min+
Max.
Access time from RAS
1.50
200
Access time from CAS
75
100
Row address hold time
20
25
Column address setup time
0
9
Column address hold time
45
5.5
RAS to CAS delay time
30
35
RAS precharge time
100
CAS precharge time
30
120
35
...,._
RAS pulse width
150
200·
DMA Interface
. . , . ·.. .. .. .
The DYRC performs DMA read and write cycles s4Jillar to CPUread and write cycles. The DMA
controller must control:~ DAL oe;= 19:0>, CS <2:0>, BS< l:O >, Wll, BM <3:0>; SELE<!r and
AS lines, and check di·state of the iIDY and DY.sigllals to transfer data to or from memory. It must
also check the state ofthe film line for error conditions.
When the DMA accesses a memory that is controlled by the DYRC, the DMA ·de.vi.ce must consider
the latency time that may occur as a result of a refre&h Cycle. The DMA device <:an use the RIN'.l?RG
signal to detect a refresh cycle in progress. The DYRC does not support refresh hold off. A DMA device must process a request without waiting or RAM data rould be lost.
· Specifications
The mechanical, electrical, and environmental characteriStics and specifications for the MicroVAX 78584 DYRC are describedin the following paragraphs. The test conditions for the electrical values are as follows unless specified otherwise.
· Power supply voltage (VDD): 5 V ±5%
· Ground (V55): 0 V
Mechanical Configuration The physical dimensions of the 78584 84-pin cerquad package are contained in Appendix E.
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Preliminary
MicroVAX 78S84
Absolute Maximum Ratings Stresses greater than the absolute maximum ratings may cause permanent damage to the device. Exposure to the abs<>Iute maximum ratings for extended periods may adversely affect the reliability of the device.
·Power supply voltage (V00): 5.0V ±5%
· Input and output voltage applied: -0.5 V V00 plus 0.5 V (5.5 V maximum)
· Storage temperature: -5°C to 125°C
Recommended Operating Conditions · Power supply voltage (V00): 5 V ± 5% · Temperature (TJ 0°C to 70°C
de Electrical Characteristics The de electrical parameters of the MicroVAX 78584 DYRC for the operating voltage and temperature ranges specified are listed in Th.hie 8.
Symbol Vrn Vu. VmE VILE Von VoL I,L IoL Im
Table 8 ·MicroVAX 78584 de Input and Output Parameters
Parameter
Test Conditions
Requirements
Min.
Max.
High-level input voltage
2.0
VDD
Low-level input voltage
0
0.8
High-level input voltage
(EPS only)
2.6
VDD
Low-level input voltage
(EPS only)
0
0.2
High-level output voltage
Ion =28 mA
2.4
VDD
Low-level output voltage
loL= 11 mA
0
0.4
Input leakage
V..,,*
current
0
-10
Output leakage
V...*
current
0
-10
High-level
100
input current
Units
v v v v v v
µA µA µA
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Symbol
Parameter
Preliminary
High-level output current
Active supply current
c ..
Input capacitance
c....
Output capacitance
*To be determined.
.. ··Requirements
Min.
Max.
-40
300 5.0 5.0
Units mA mA pF
ac Electrical Characteristics The ac riming parameters for the MicroVAX 78584 are grouped according to their functions. Figure 6 shows the clock input waveform and symbols and the parameters are defined lmle 9. Figure 7 shows the timing and symbols for the reset operation and the parameters arelisted in Table 10. The memory read signal timing is shown in Figure 8 and ~e Wr:ite signal timing in Figure 9. Table 11 lists the timing requirements for both memory read and write transactions. The refresh signal
timing is shown in Figure 10 andthe timing parameters are listed in Table 12. The register read and
write timing is shown in Figures 11 and 12, respectively, and the parameters are listed in Table 13. Figure 1.} shows the error reporting timing and Table 14 lists the timing requirements,
The"following notes apply to Figures 7 through 13 and to the associated timing parameter tables.
· All times are in nanoseci:mds except ~here ooted.
· The ac high levels are measured at 2.0 V and the low levels at 0.8 V.
· The ac characteristics are measured with a purely capacitive load at the output of 50 pF on
RAS <3:0 >, CAS<: 3z0>, AD<:8:0>, ROY, and DV.
tclR
Figure 6 ·MicroVAX 78584 Clock Input Timing
Confid~tial and Proprietary
1-191
- - - · l &_________ ·-·#1£4llll!i-Bt_m..,.._ll~-·-~-·---·-""-l!'!'ill'f""'.
J&-·---~---------~~--·~--"--"---·-----------
'Jltble 9 · MittoVAX 78;84 ··Cfbclt l:titmt Parameters
Symbol Definition
Requirements (ns)
Min.
Max.
tru
Clock in fall time
4.5
tau
Clock in high
tai.
Clock in low
1c1P
Clock in period
1ct1t
Clock in rise time
8
8
25
50
4.5
__ ___ ~
..,._
-----------------------------....\__----_-.
RiOWY _ ___,
Figure 7 ·MicroVAX 78584 Reset Input Signal Tirning
Table 10 ·MicroVAX 78584 Reset Input Timing Param.eters
Symbol Defmition*
Requirements (ns)
Min.
Max.
tllLW
RESET assertion width after V0 n=5.0 V
800 µs
tit HA
RESET deitssertion to AS assertion
100
tRLll
RESET assertion to RAS<3:0>, CAS<3:.0>, RDY, and DV
deassertion
50
tRHI
RESET deassertion to start of initial eight refresh cycles (lf
refresh enabled)
200
tlKEP
Time required to perform eight initial refresh cycles (if refresh
enabled)
3 µs
*Delay from assertion of RESET to deassertion of AS by the MicroVAX 78032 CPU is typically
1.5 µs. CLKI input must be applied while RESET is being asserted.
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Confidential and PrOprietary
DM<31:00> 85<1:0>
BM<3'°"
AtK8:0>
Preliminary
MicroVAX 78'84
DATA
Figure 8· MicroVAX 78JS4Memory Re~C:JW!e Timing
DAL<'3:1:00>
BS<1·0> - - - BM<:J·O>
A.l()ORESS' '
AD<.9:0> RAS<3:0> . CAS<3!0>
·DY
..------------tASLD\IL-----·
:I
-----'{
Figure 9 ·MicroVAX 78584 Memory Write Cycle Timing Confidential.and Proprietaty
H93
-
Pi:elimiruµ:y
MicroVAX 78584
Tahl4= 11 · MicroVAX 78S84 Memory Read/Write Cycle Timing Parameters
Symbol Definition
Requirements (ns)
Slow Cycle
Fast Cycle
Min. Max. Min. Max.
tARAV DAL< 19:02 > valid to tow address valid
20
10
20
tASHCASH AS deassertion to CAS < 3:ti> deassertion
50
50
tASHDVH AS deassertion to i5'V deassertion
50
50
tASHltDH AS deassertion to RDY deassertion tASLDVL AS assertion to DV assertion
50
50
425 450 225 250
tASLRDYL* AS assertion to RDY assertion
tASLRL* AS assertion to RAS assertion
260 300 20
60 100 20
tASLSH SELECT hold time after AS assertion
15
15
tuHASH Column address hold time after AS deassertion
20
20
tRAH Row address hold time after RAS< 3:0 > assertion 55 100
30
75
tRLRCL RAS< 3:0 > assertion to read CAS assertion
105 150
55 110
tttw
RAS< J:lj > pulse width
315 350 240 275
tRLWCL RAS <3:0> assertion to write CAS < 3:0>
assertion
115 140 115 140
tSA
DAL< 19:2 > and BS< 1:0 > setup time to AS
23
23
assertion
tsLASL SELECT setup time to AS assertion
8
8
tsRCA Cohunn address setup time before read CAS < 3:0 > 20
30
20
30
assertion
tswcA Column address setup time before write
CAS<3:0> assertion
RAS< 3:0 > precharge time
70
80
70
80
150
125
*The maximum times for tASLRDYL and tAsLRL assume there is no refresh cycle in progress.
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Confidential and Proprietary
.Table 12 · MicroVAX 78584 Rdiesh Timing Parameters
Symbol Definition
~ts(ns)'
Slow Cycle Fast Cycle Min. Max. Min. Max.
tADS Refresh address setup time..to RAS< 3:0 >
assertion
tADH Refresh address hold time-after RAS< 3:0 >
assertion
100
25 100
235 265 .135 165
tllEFPllJI RAS<3:0> precharge ·
,165 185 165 185
tnnr 'RAS<.1:0> pulse width
215 235 165 185
Figure 10 ·MicroVAX 78584 &fresh Signal Timing
DAL<1&:00> - - - <
AOOFllSS
DATA
'DBEDA~_::_------------'O-AOB_E_H~~========:r
Figure 11 ·MicroVAX 78584 Register Read Signal Timing
Confidential .and Proprietary
1-195
-----------------·-- ---------~----·-···· --·- -·---·- --····-----~--------··-·-------------·
-· OAL<15:00> - - - <
Preliminary
DATA ,
MicroV.AX.78.584
DBE
Figure 12 ·MicroVAX 78584 Register Write Signal Timing
Symbol
tASHllDH
tASLRDL
toADBEH
tDAH tDBEDA tRSASL
Table 13 · MicroVAX 78584 Regist.er Read/Writ.e Timing Parameters
Definition
Requirements (ns) Min. Max.
AS deassertion to RDY deassertion
35
AS assertion to RDY assertion
25
Data setup before i5lIB deassertion
50
Required data hold time after DBE assertion
10
DBE assertion to stable I/O data on DAL< 15:00 >
25
RS setup time before AS assertion
15
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Preliminary
MicroVAX 78584
CS<2:0> -<...____""_'_"_""_"'_M____,X.____'_"'-'""_CT_'·"_·_,,·_··_...____.X_____""_"_'"'_"_"_____,)-
~ \~~~~/\
··= _______.._.,_.,_)~"'_. _{___,/
r\~~~-f
·-·-~
0AL<31 :00>
BM<l:O>
Parity Error
Time·out Error
Figure 13 ·MicroVAX 78584 Error Reporting Signal Timing
Symbol
tPAEl!RL tPAEllKH tASLl!KL tASHEJl.H
Table 14 ·MicroVAX 78S84 Error Reporting Timing Parameters
Definition
Requirements (ns)
Min. Max.
PARIN to ERR assertion
50
ERR deassertion after data stream cycle
50
AS assertion to ERR assertion
25 µs
AS deassertion to ERR deassertion
50
Confidential and Proprietary
1-197
·Fea~
· Low~cost MicroVAX d~lopment system contairyed a single module · Full-speed incircuit emulation of MicroVAX 78032 microprocessor chip and MicroVAX 78132
floating-point unit chip · PROM-resident mortit6r with pO'IVerful eomtnand set · Han;iWare eve{lt d~orJpr Mlci<>VAX bus control sig~ anda<i~sses · 64 Khytes of relocatable memory simulation RAM for target applicatien ,
· Two RS-232-compatible serial lines for host and terminal connections, one with modem control
· Internal clock of 10-, 20-, or 40-MHz or external clock · Bus timing controllable by ADVICE and target or hy ftqet~ne (wait states only)
· Powerup diagnostic tests to verify its own oi>eration · Connectors for dock-in, trigger-in, trigget-~ut, power supply~ and R$-232 ports · Single 5-volt power supply
· Description
The ApplicationsDevelopment Micrt>VAX Irlcircuit E111ulator (ADVICE) is a low-cost, incircuit
emulator used for the development of ~ardware il:Qq, software products based on the MicroVAX
78032 32-bit microprocessor and the lvJiicroVAX 78~2 floating·point unit~ ~ostic or applica-
tion programs for the user's target may~ developed on a VAX/VMS h(,:st'aric!''.~nloaded to
ADVICE. ADVICE contains all the necess!U:Yhardw~ and S<?!!~ req~ to quicldY),and easily
debug the target.
· ·
.;>''"'' ·'' ,._ .L
'
The emulator is contained oti.a s~em0tk4e a~~lµ~ a PROM-1.Ji!side.rtt ~ 32Kbytes of monitor RAM; as matty as 64 Kb~ of.a ~mo.pr stt.nulatio~.~ for th<; uset"s.~etal:)plication,
a switch-selectable clcx;k1 a MicroVAX micioprocessor (CPU) f:f~~ating-poirit unit(FPU), and two serial lines-one for a corumle terminal and one for a host. An~~ detector is included to compare stored values to MicroVAX bus addresses or to the logic$1 l~of vatio'us MicroVAX bus control
signals.
,
Figure 1 ·ADVICE Bkx:k Diagram
1-199
· Sy81em Overview
The ADVICE enables the hardware emulation of the MicroVAX CPU and FPU at full-speed (40MHz) and provides the user with complete control over MicroVAX CPU operation. This includes the ability to start and stop the program operation and to single-step through a program. It contains hardware and software that can be used directly by the target application to simplify t_he development of the target hardware and software. Figure 2 shows the system interconnections to the ADVICE module. The host computer is used to
write, edit, and optionally debug the user programs that will eventually run on the target system.
These programs are converted to hexadecimal format by the DECPROM software and downloaded to the ADVICE over a serial line. A local console terminal is used to enter commands and control the entire development process.
HOST COMPUTER
POW.Ell ON LEO
CLOCK IN BNC
Figure 2 ·MicroVAX ADVICE System Interconnection
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Confidential and Proprietary
...
Module Connectors
Table I lists the connector types that are included on the ADVICE module and their function. .R.efur
to Figure 2 for the location of the connectors on the module and to the ADVICE User's Guide for the
connector applications and signals.
Connector
JI
]2
]3
J7 J8
]9
JlO Jll
.'Diltle 1 ·ADVICE Module: Connectors
Type.·.
Function
BNC
. 40-pin
40-pin . BNC.
BNC
4-pin 25-pin 25-pin
Clock in Target circuit Target circuit Tr.iggeri.µ Trigger out Power supply Host computer port (serial-line) Console port( serial-line)
SwiteheS and lndka1ots
The ADVICE mooule eohtains eight switches inll.4!1~-in:lj.rie p~~JDIP) tha~ a:i:e ~~.selea
various functions. a reset pushbutton switch, arid two LED indicit0rs~ Table2 lists the positions
and selections of the mtches on theDlP.·Theres~qrushbatton is'ustdto Wtiali!eithemodule.and
causes a series ofdiagnostic tests to be perlormed. The Power onlightindiC$~~ d1afthe clc.power is
applied and the ··Self-test indicator is used to verify the correct opention·of the diagnostic
programs.
.. ~· .
. 'l.ab.le...2. .··.A..·D.V·..IC·..I?.DI··P·· S. W')tchF..~.. c· ~.......
Switch
1
2
3
4
5
6
7
8
off off off on on off on on
External Clock
1o~M}ii Clock
20·MHzdoc:k
40-M~2; ~ock
off
; FPU dis~1e~
on
FPUenabled
off
Compreheflsive diagnostics
on
. Limited dilltriostks .
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1,201
-
Preliminary
MicroVAX Incttcuit &lutatm:
Switch
Selection
1
2
3
4
s
6
7
8
off off off on off off off on off on on off off off on on off on off on on on on on
110 baud rate 300 baud rate 600 baud rate UOO baud rate 2400 baud rate 4800 baud rate . 9600 baud rate 19200 baud rate
off Modem control disabled on Modem control enabled
PROM-resident Monitor The ADVICE monitor is contained in 64 Kbytes of EPROM and allows the user to load, execute, and debug application programs. The monitor is controlled by the ADVICE commands and allows the user to perform the following functions: · Upload/download programs to or from a host in Intel, Mostek, or Tektronix hexadecimal formats · Assemble MACR0-32 instructions from a terminal or host · Disassemble information stored.in memory to display MACR0-32 instructions · Start or stop program execution · Single-step through a program · Examine and deposit memory and the CPU registers · Set and dear up to 16 software breakpoint and/or tracepoints · Detect or ignore hardware events such as the assertion of variousMicroVAX bus control signals · Define or undefine symbols · Set or show current operational modes such as radix, word width, and hexadecimal data format · Maintain four command line buffers and allow repetitive execution of any buffer · Define up to 22 cursor control keys · Fill a memory range with any byte value · Evaluate expressions in binary, decimal, octal, or hexadecimal · Perform ADVICE hardware diagnostic tests · Use command abbreviations · Receive help in using ADVICE commands
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Confidential and Proprietary
.MicroVAX Incircuit Emulator
· Modes of Operation
The ADVICE operates in transparent and nontransparent mode. The selection of the mode depends on application to be developed.
In transparent mode, it acts as a full-speed (40 MHz) incircuit MicroVAX processor emulator and appears to be a MicroVAX 78032 chip to the target applicatiol*;.It provides complete control over the CPU operation by allowing the user to start, stop, and single-step through program operation. The ADVICE does not interfere with the operation of the tal'get application. This allows the debugging of user hardware and software that overlaps the ADVICE hardware and software.
Debugging a boot PROM for the target application W9Uld typically be performed in transparent
mode.
of In nontransparent mode, the internal circuits of ADVICE are r.tCCeSsible to the user. This allows the
use of ADVICE hardware and software as, an extension· the target hardware and software. Nontransparent mode allows 1tccess to serial-lineinterface rou,tines in the ADVICE monitoi:
Physical Address Space
The physical address space available depencfs on th,e mode o(o~tion. In transparent mode, the
entire MicroVAX physical ad~ space &Q,m ®000000 to.3FFFEFJW (hexadecimal) is available. In
nontransparent mode, a 256 Kbyte bl~9f lllf!InOry (addresses 20040000 through 2007FFFF) is
used by the ADVICE and is not available to the user. The tf.let.nory map for the nontransparent
mode is shown in Figure 3. ·
·
·
Confidential and Proprietary
-
MicroVAX Incircuit Emulator
00000000
2003FFFF 20040000
2004FFFF 20050000
20057FFF 20058000
2005FfFF
20060000
20061FFF 20062000
20063FFF 20064000
20064004
20064010 20064020 20064024 20064028.
2006402C
20064030 20064034 20064038 2006403C 20064040
20064070 20064071 2007FFFF 20080000
3FFFFFFF
A.VAILABLE TO
USER
AOVICE PROM \64 KG)
ADVICE RAM 132 KB)
RESERVED FOR FUTURE USE
RESERVED FOR ADVICE HARDWARE
RESERVED FOR FUTURE use
RESERVED FOR ADVICE HARDWARE
RESERVED FOR AOVICE HARDWARE STATUS REGISTER CONSOLE Ul>.RT. CONSOLE UART CONSOLE UART CONSOLE Ul>.RT HOST UART HOST Ul>.RT HOST Ul>.RT HOST UART RESERVED FOR ADVICE HARDWARE
RE SE RVEO FOR FUTURE USE
A.VAi LAS LE TO
USER
NOTE: ALL AODRESse's ARE AVAILABLE TO USER IN TRANSPARENT MODE
Figure 3 · ADVICE Nontransparent Mode Memory Map
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--
Pi-eliminary
MictoVAX lncircuit E~
Event Detector
The ADVICE contains an event detector that is primarily used during diagnostic operations to
analyze the interaction between the advice and target application. Depending on the states of its
inputs, the event detector provides a pulse output that can be used as a trigger to external circuits.
The event detector monitors the following signals:
··
· The logical levels of MicroVAX bus control sigruds including IWS', XS. WE, DMR, :tID:} < 3:0>,
andCS<2:0>
.
· The output of an address comparator that indicates whether a MicroVAX bus address is greater than, less than, or equal to a stored value
· The logical level of a BNC connector input
The ADVICE can be programmed.to igno~ eve.ntsQr halt ptQ.gJ:'8m ~tiotiwhen an event oceurs. In either case, a trigger output from ADVICE indicates the occu.r:rence ohm e\lent.
Memory Simulation The ADVICE contains 32-Kbytes or 64-Kbytes of memory simulation RAM (MSR) that can be
mapped anywh<:re in the UU"get address space. The en.abling of ¥S.R ensure(thht Users thllf\'alid
memory is available during the application developme0t.
Serial-line Ports One EIA RS-232 serial-line port is used to connect the host processor to the ADVICE and includes modem control. The remaining EIA RS-232 serial-line port connects to the console terminal. These ports are used in nontransparent mode and an internal subroutine is included to access these ports.
SeH-diagnostics Several diagnostic tests are performed in the ADVICE during the powerup sequence or when the Reset pushbutton on the ADVICE module is pressed. These programs verify the integrity of the information in PROM and RAM (including MSR) and the operation of serial-line ports, event detection logic, and MicroVAX CPU and FPU. The user can select a limited diagnostic routine to preserve RAM contents or a comprehensive diagnostic routine that tests RAM without regard for its original contents.
· User-supplied Equipment
The standard and optional equipment and software required for use with the ADVICE is listed· as follows. The optional listing depends on the type of application to be developed. · A VAX processor system with an available RS-232 serial-line port · VAX/VMS operating system, Version 3.4 or higher · DECPROM software, Version 1.0 or higher · 5-Volt power supply · Local VTlOO compatible terminal · Appropriate etch layout around target MicroVAX CPU surface mount pads to match ADVICE
connector (Refer to the ADVICE User~ Guide) · RS232-compatible modem for remote host or terminal (optional) · External clocks or triggering circuits including cables (optional)
Confidential and Proprietary
1·205
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· MicroVAX Incircuit Emttlaw
· Specifications
The physical and electrical specifications of the ADVICE are as follows:
Operating Environment
· Temperature: 15°Cto 32°C at 200 linear feet/minute air flow · Relative humidity: 20% to 80% (noncondensing)
Module Dimensions
· Height: 26.0 cm (10.25 inches) · Length: 40.6 cm(16.0 inches) · Width: 2.5 cm (l.O inches)
Power~ents
·Power supply: 5 V ±5 % at 6 A (maximum) 4.5 A (typical)
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Confidential and Proprietary
·Features
· Enitllates the VAXproce8sors·
· Cotlsists of the DC328 i1lstruction/ex;ecution lqgic {I/E: chip), t}w DC3.29 lll<!m£ll'Y management
logic (M chip). the DC.UO fk,a,ting-pointacceleratot logidF chip), aµd five DC327 ROM/RAM
memory chips
.
· ·
·
.
· Provides foll VAX ~SS0r functionality on a single module
· Description
The V-11 chipset is designed for µse on the Scorpio CPU modi.lie (KA820) that is a single module VAX processot: The V-11 chip set configmation for the Scorpio CPU is shown in the following
diagram and consists of the J/E. chip; M chip, Fchip, Jtn4 five rROM/RAMs.
._-------! VNI. Bl PORT
TO BllC
PORT CONTROLLER (3PORTS)
Figure 1 · V-11 Scorpio Microprocessor Block Diagram
Confidential and Proprietary
1-207
The five ROM/RAMs are connected in pamllel to provide a 16Kby 40-bit control store memory.
The CPU is positioned between the IfE chip and M chip that are controlled by microcode from the
ROM/RAM chips. The optional F chip contains high-speed logic and provides internal microcode for accelerating the operation of floating-point and other mathematical instructions.
The I/E chip consists of the instruction buffer (I box), executionunit (E box), and memory
interface logic which performs virtual-to-physical address translation through a five-entry address translation buffer (Mini-TB). It also contains the microsequencer and microinstruction prefetcher that mterfaces to the mictocontrol store. The microcontrol store is five ROM/RAM chips that form a combinational 16K by 40-bit ROM array and a lK by 40-bit RAM array. The RdM section contains the V-11 microcode that controls the .CPU chips, and . the RAM section ·is used for implementing microcode patches to the ROM locations. These chips also provide. 32 (total of 160) locations each of content addressable memory (CAM) that is used to store and compare the addresses of the patched ROM locations with the incoming microaddress.
The microcontrol store memory interfaces to the F chip, I/E chip, and M chip through the 40-bit, time multiplexed, microinstruction bus (MIB). The IfE chip drives the microaddress to the control
store during the first half of microcycle, and each ROM/RAM chip drives 8 hits of the microinstruction onto the MIB during the second half of the cycle. The MIB lines that are not used for the microaddress are used for interchip communication during the address portion of the cycle.
The M chip contains the tag store for the cache memory and the tag store for a 512-entry virtual to physical address translation buffer called the Backup TB (BTB). The BTB supplements a five-entry translation buffer (the Mini-TB) that is located in the I/E chip. The cache data and the BTB address translation entries are stored in external static RAM chips. The M chip also contains a variety of miscellaneous CPU functions such as CPU clock drivers, processor registers, the interval and timeof-day timer registers, interrupt hardware, clock generation circuits, and four serial-line units.
The main data flow between the processor chips, the cache, and the BTB is through the 32 bit data/ address lines (DAL< 31:0 >) that are also time multiplexed. The DAL line addresses are driven during the first half of each cycle, and DAL data is driven during the seeond half.
The V-11 chips :interface to main memory and 1/0 devices through three gate arrays that form the port controller. This logic provides three ports, one of which is the CPU port to the V-11 chips. The remaining two ports access main memory and I/O devices. Main memory and system I/O are on the VAXBI bus and are accessed through the VAXBI bus port and the VAXBI 78732 bus interconnect interface chip (BIIC). The third port is used for local I/O transfers to the control panel, floppy disk, etc.
Related Documents
Additional information on the V-11 chip set is contained in the following specifications.
· V-11 CPU Functional Specification
· DC327 ROM/RAM Chip Functional Specification
· DC328 I/E Chip Functional Specification
· DC329 M Chip Functional Specification
· DC330 F Chip Hardware Specification
· Scorpio Port Controller Specification
· KA820 CPU Modt& Specification
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Confidential.and Proprietary
· Featutes
· Custom deSigned VLSI ROM/RAM chip for the V.11 processor. · Contains 16K by 8-bit word ROM, lK by 8-bit word RAM and 32 by 14-bit word CAM.
· Description
The DC327 ROM/RAM, contai~ in a.~47pin.package,is ~VLSI chip designed for the V-11
of processor. It ~ontains 16K 8-bfrwords9f maskedpi;ogra~ROM (read-oru:r, memory), lK by 8-
bit words RAJv1. (rand()m ~iXess memory-) and.'.32 .i 4-bit' words of CAM (content addi-essable
memory). The PC.32ichip is de5igile<l t~ facilitatethe replacing (patching) of incorrect ROM data with RAM data. Figure 1 is a blb& diagram.of-the DC327 chip.
MSELB A<13:00>
ADDRESS AND . MSELB LATCH
WE
0<7:0>
Figure 1 · DCJ27 ROM/RAMB/ock0i4gram
Confidential and Proprietary
.1-209
DC327
·· Ym 8nd Signal Descriptions
The input and output signals and power and ground connections for the DC327 44-pin package are summarized in Table 1. The table also contains the physical pin locations that are shown on Figure 2. The following paragraphs provide more detailed descriptiops of the inputs and outputs of the Mchip.
Table 1 · DC327 Pin and Signal Summary
Pin
17-14,10~7
Signal D<7:00>
Input/output Description/Function ·
inputs/outputs· Data-Transfers data from the ROM and transfers data to and from t.he RAM and CAM.
3,4,30-33, A<13:00> inputs 36-43
Address-The ROM, RAM, and CAM address inputs.
5
CE
input
Chip enable-Clock signal to latch the A< 13:00 >
and MSELB inputs.
26
MATCH
output2
Match-Indicates the result of the CAM match
operatiori during a read cycle.
29
MSELB
input
M sdect B-Selects the ROM, RAM,· and CAM
arrays for data access.
19
OE
input
Output enable-Activates the output buffers dur-
ing a read operation.
6
. TRISTATE. input
Three state-Used only during manufacturing test.
20
WE
input
Write enable-Selects a. read or write operation for
the RAM or CAM.
28
Van
input
Voltage back-bias-Power supply back-bias voltage.
18
VH
input
Voltage high-Connects to VDD through an external
10-kn 5% resistor.
27
v
input
Voltage low-Connects to V55 ·
21
Not used.
35,34,22, Von 23,13,2
input
Voltage-Power supply voltage.
25,24,11, Vss 12,1,44
input
Ground-Common ground reference.
'Three-state output 20pen-drain
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DCl27
A03
A02 41
A01 42
AOO 43
vss 44
.,,.-- PIN 1.IDENTIFIER
vss
VDD 2
A13 3
A12 4
~ 5
'i'RiSi'Ai'E 6
TOP VIEW
VBB
VL
MAi'CH vss
vss
VDD VDD NOT USED WE
.OE'
VH
FigUnJ 2· DCJ27 Pin:Afsigtiments
Data (D < 7:0 > )-Bidh'ectional data lines used to transfer data from the ROM,, and to and from
the RAM and CAM.
.
'
Address (A< 13:00 >)-The address inptits to reference the ROM,'; RAM, and CA.¥. These inputs
are latched during read and write. cycles during .the high-to~loW tnJrisition of the C! input.
Chip Enable (Ci!)-A clock: signal that latches the A~ 13:()0 ;> ~ MSt:LB h1puts, and initiates
the internal .aca;ss cycle with 1l hlgh-tp..low transition. When de~ted. the ~ signal <;auses the
data output buffers to become a high iD)pedance.
Match .(MAmi)-An open.drain output that indicates the result 0f the CAM match opetation
during .a read cycle. The CA.Mmatch ~tion apd the MA1f;H 011:~put are active durirlg RAM read
cycles as well as ROM read cycles. The M1\'.I'C'H' output is disabled only when the ROM/RAM chip is in test mode. The state of the MA'IeH signal is not define4 duri~ p.AM/CAM write cycles.
MSelect B (MSEU~-An address input that ~crlects. the ROM or{:AM arrays and theRAM array
for data access. This &iiµlal is latchcc{ during read. or write cycks.
Output Enahle (OE)-Activ:ates the output buffets during a read operation.
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Prelitriinary
Three State (TRISTATE)-l}sed only for manufacturing test purposes and not used during normal operation. The input conntctS the power !flUpj:!}y voltage (Von) through a 10-kO ±5% external
resistor. When enabled, the D < 7:0> outputs 1Jte a high imped~.
Write Enable (WE).,...This input selects the read and write operations to the RAM or CAM. When asserted, the output lines of the buffer become a high impedance independently of the state of OE input.
Volt.age High (VH)-This input connects to the power supply voltage (V00) through a 10-kn ± 5%
resistor.
Voltage Low (VL)-This input connects the ground reference.
Voltage (V88)-Power stlpply-3 V (nominal) back-bias input voltage.
Voltage (V00)-Power supply 5 V (nominal) input voltage.
Ground (V.5 )....-Common ground references for the chip.
Functional Operation The patching of incorrect ROM data with RAM data is performed by the.following operation. The 14-bit ROM addresses of the incorrect ROM data are written into the CAM. The correct data is
written into RAM locations that have 10-bit addresses that are identical to the low-order 10-bits of
the incorrect ROM data. :E.aCh time the ROM is accessed, the incoming ROM address is automatically compared with the addresses stored in the CAM. If the addresses are the same, the MA'It:H output is asserted to inform the external logic that the ROM data currently being accessed is incorrect and that the correct data is in the RAM. The RAM is then accessed in the following
cyde(s) with the same address. tThe ten low-order address bits must be identical to access the
correct data.
The DC327 ROM[RAM chip contains an address/MSELB latch; a ROM, RAM, CAM,. a data
multiplexer, and an output buffer shown in Figure 1.
.
. .'
Address/MSELB · Latch-Thi.s latch. holds address inputs A< 13:00 > and the ·MSELB 'input.
When the CE input is deasserted, the address and the MSELB inputs pass through the latch to the
intetruil logicof the chip..A high-to-low transition of the CE input loads the state ofthe address and
MSELB H information into the latch, and any transitions on those inputs that follow are ignored.
Read-only Memory (ROM)-The 16K by 8-bit word ROM is accessed by the address information
on the A< 13:00 >lines froth the output ofthe address lat:Ch. The ROM is accessed during a high-
to:low transition of the CE input and the 8-bits of the ROM data are transferred to the data
mrl+iplexer.
.
Random Access Memory (RAM)-The lK. by 8-bit word RAM is accessed by the. address
lliformation on the A< 9:0> lines from the output of the address latch. A high-to-low transition
of the CE input when the WE input is deasserted will access the RAM and transfer 8-bits of the
RAM data to the data multiplexer. The RAM is written with the data on the D < 7:0 > lines when
the latched MSELB signal is asserted, the CE signal makes a high-to-low transition, and the WE
input is asserted with the proper timing.
Content Addressable Memory (CAM)-The CAM consists of 32 14-bit registers, 32 14-bit comparators, logic for detecting an address match, a CAM test address register, and logic for testing the CAM. When the CAM operates in the normal mode (not test mode), the latched address information on lines A< 13:00> is cqmpared with the addresses stored in the 32 14-bit CAM registers. If the latched address is the same as an address stored in the CAM registers, the MATCH output is asserted. The MATCH output is indeterminate during a RAM or CAM write cycle. In test mode, the MATCH output is disabled. The MATCH open drain output is internally disabled at the beginning of each cycle and must be pulled up to its inactive state by an external resistor.
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CAM Write Operations The mask progmmitaj:>le CAM write decoder enables up to eight ROM/RAM chips to be conn~
in parallel while main~ a unique write access to each CAM register on each of the eight ROM/
RAM chips.. AROM/RAM chip can access each of the 32·individual CAM registers. The CAM registers are writ~l'l ',1/hen the WE input is asserted, the ¥SELB input is Zero, the CE input is
asserted, and when the write decoder decodes one of the reserved addresses shown in Table 2.
Address A< 13:00 >
(bexadecimal)*
0000 0001 ·0002 0003
Internal Structure Accessed
CAM Register
Data
·o <07:00>
0 <13:08> 1 <07!00>
D<7:0>
I D<:5:0:>
0<:·1:0>
1 <U:08>
D<5:0>
(continued through)
003E 003F
31 <07:00>
31 <:13:08> ..
D<7:0>
D<5:b>.
*Assume mask p~ble bit!s A< 8:6 > 0£ ;th~ CAM write decoder are zett\s.
Data M11bip~
.
I
The data multiplexer selects the data to be..transferred to the output buffer and then to the
D<7:0> .lines. Eight bits of RONfdata, RAM data, or CAMregister match state are selected
depending on the state of the intenial CAMSEL signal and the latch MSELB signal listed in Table ,3.
CAMS EL
0 0 1
"X=l orO:
MSELB
0 1
x
D<7:0> output
ROM RAM CAM match state
OutptJt Buffer
The output bUffer dri'ves the output of the data multiplexer onto the D<7:0 > lines. When not
transferring data, ·the()utputs of the buffer are a high imped~ce. Tabl~ 4. lists the. state.of. the
outputs depending on the input signal conditions.
Confidential and Proprietary
1-213
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TRISTATE
CE
1
0
1
0
0
x
x
1
x
x
*X=l orO.
Preliminary
00;27
Table 4 · DC327 Output Buffer States*
WE
'OE
1
0
1
1
x
x
x
x
0
x
Output. Drive output high-impedance high-impedance high-impedance high-impedance
Summary of Read and Write Operations
Thble 5 lists the inputs required for read and write operations for each of the ROM/RAM chip sections.
Table .5 · DC327 Read and Write Operation Selection"'
CE TRISTATE WE OE MSELB A< 13:0> Operation
0
1
1
0
0
3FFB-0000 ROM read
0
1
1
0
1
3FFB-00001 RAM read
0
1
1
0
x
3FFF-3FFC CAM m~tch state read
0
1
0
1
0
1
0
x 0
0
x 0
0
x 1
003F-00002 0201-0200 3FFB-00001
CAM write CAM test address reg write RAM write
'The RAM is accessed by address bits A< 09:00>.BitsA<13:10 > are not used. 2Mask programmable bits A< 08:06 > of the CAM write decoder are zeros.
*X= 1orO.
· Specifications
The mechanical, electrical, and environmental specifications for the DC327 are contained in the following paragraphs. The test conditions for the parameters in these specifications, unless specified otherwise, are as follows:
· Ambient temperature (TA): 0°C to 70°C
· Power supply voltage (VDD): 5.0 V ± 5% (maximum ripple 200 mV peak-to-peak) · Power supply back-bias voltage (VBB): -3 .0 V ±15% (maximum ripple200 mV peak-to-peak)
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Confidential and Proprietary
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Preliminary
DC327
Mechanical Configuration
The mechanical dimensions for mounting the DC327 44-pin leadless package are shown in
AppendixE.
· Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to a device.
Exposure to the absolute maximum rating conditions for ex:tended periods may adversely affect the reliability of the device.
· Power supply voltages (VDD): -1.5 V to 7.0 V
· Power supply substate voltage (V88): -6.0 V to 0 V
.V · Input/output pin voltage: -1.0 V to 10
· Storage temperature range: -55°C to 125°C
· Ambient temperature operating range (TJ: 0°C to 70°C
Recommended Operating Conditions · Power supply voltage (V00): 5.0 V ± 5% · Power supply back-bias voltage (V88): - 3.0 V
· Ambient temperature {T,.): 25°C
ac and de Electrical Characteristics Refer to the DCJ27 ROM/RAM Chip Functional Specifo;ationfor the de input and output parameters
and ac ti.ming parameters.
Confidential and Proprietary
1-215
· Featdres
· Main processor element for the V-11 chipset · Used with the M-chip and F-chip to emulate VAX instruction set and memory management · Initiates memory references and contains add:'es~ translado~lagic
· Description
The DC328 InsttuCtiii>n/Execution(I/E) lOgic.is contained in a 132"pin PGA package and is the
main processing elem~ntof theV-11 processor chipset. It prefetches instnictions, parses opcodes
and specifiers, initiates all memory references, and contains the resister ille and arithmetic logic
unit (ALU) and most of the ad<hess translation hardware. Together with the F chip and M chip, it
emulates the VAX instruction set and memory architecture. The function:il block diagram of the
I/E chip is shown in F~re 1.
·
·
_:.:_
110
FBOXN
FBOXZ
_....
·1eox
oeus~)
.··. .::. ..t.:.
AWIWS<30.27.S.O~)
,eox .
1-f--
MEMORY lll!TE!IFACE
.....
. PHYS ADOR<5;0>
....... ..
> ; ·'~;
· l!M':St:OO>)
Aii5iii'
MTBMISS
° / . t~ l;)l\L
"' ·< .. ~.· INTERFACI' tlAt"S'l'IQl. K4" ,. t:::i H .ri LJ CMISS
ll;)l\L<31.:Ql{jl y
y
.. .."~"i
y
.·
i
{)..(
H H
I-
IDAl..<31:00>
'·.··.·
L~
171i-~
CAM MATCH
CPliFAUi.T MiRRiiW>
MICROSEQUENCER
~
r--..
H I-'
H
......
M18<39:~}
ri
CSWE
MIB INTERFACE
MAB<14:00>
.._,
MICRO TEST<3:0>
IM18<3a00>
CLK CLK BAR CLKSYNC
DCLO ~]!;TATE
CLOCKS
Figure 1 · DC328 I/E Chip Block Diagram
·Confidential and. Proprietary
1-217
OC328
Pin~ Sigrla) Descriptions
The input and output signals and power and ground connections to the DC328 I/E chip are shown in Figure 2 and summarized in Tu.hie 1. The paragraphs that follow provide a more detailed description of the signal functions listed in Table 1.
14 13 12·11 10 9 8 7 6 5 4 3 2
p 00000000000000
p
N 00000000 000 000
N
M 00000000000000
M
L 000
K 0 o· 0
J ·o 0 0
0 0 0
L
0 0 0
K
0 0 0
J
H 0 o· 0
G 000
DC328
0 0 0
H
0 0 0
G
F 000
0 0 0
F
E 000
0 0 0
E
0 000
0 00
D
c 00000000000000
c
B 0 0 0 _o 0 0 0 0 0 0 .o 0 0 0
B
o-. A 0 0 0 0 0 0 0 0 0 0 0 0 0
A
14 13 12 11 10 9 8 7 6 5 4 3 2
roPVIEW
PACKAGE . IDENTIFICATION
Figure 2 · DC328 Pin Assignments
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...
'lable l · DC328 Pin and Signal Summary
Pin
Signal
Input/output Descripdon/Function
P4,P3,N3,P2, M3,N2,M2,P1, L3,Nl,L2,Ml, K3,Ll,K2,Kl, J2,H1Jl,Gl, H2,Fl,E2,El, E3,Dl,D2,Cl, C2,Bl-B3
DAL<31:00> input/output Data/address lines-Transfer. data and
address information to and from the I/E chip.
C02
DAL BUSY input
Data/address lines busy---Indicates that the
port controller has control of the DAL lines.
A7
DAL STALL input
Data/address line stall--Indicates that the
data source cannot respond to a data request
during the same cycle.
B7
CMISS
input
Cae~mj.ss--Indica~s that the backup trans-
lation buffer miss has occurred.
Kl.3
CAMMA'itH input
Content .··addressable memory match-Indi-
cates that an improper address has been
detected by the ROM/MM logic.
;.·
''' ",·'
J12
CPU FAULT output
CPU fault-Indicates that a hardware error
has been detettcd.
Ll4
MERR TRAP input
Memory error trap-Indicates that the M
chip ha$. detected ari error condition.
M14,A9,Al0,B10, MIB<39:00> input/output Microinstruction bus-Transfers micro-
All,Cl0,A12,Bll,
address; microinstructions, anclinten::hipstatus.
Al3,B12,A14,B13,
C13,B14,D13,C14,
E13,D14,F12,El4,
F13,F14,H14,P8,
N9 ,P9,M9,Pll,
Pl0,P12,N12,M12,
P13,M13,Nl3,L12,
P14,Ll3,N14,K12
JU
output
Control store output enable-Controls the
state of the control store output buffers.
K14
output
Control store write enable-Controls the
writing of information into the RAM or CAM
of the control store memory.
M14
MIBPAR
input/output MIB parity-lndicates the odd parity of the
information on the MIB < 39:00 > lines.
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1-219
--- _ _ _ _ _ _ _ _ , -·-----------~---------------l'Hl!-·i0-"""-"illll'i-!illililli-!1115:!-·
-
Pin
Signal
P7
IID
P6
FBOX N
P5
FBOX Z
A2,B4,A3,B5, A4,B6,A5
AO
PAL<6:0> ABORT
A6
MT,B MISS
G3
CLK
F3
CLK BAR
G 14
·. CLK SYNC
N6
TRISTATE
]14
DCW
Al
Vuu
B9,C3,C6,C9,
V00
Cll,Cl2,D3,G2,
Hl2,H13J3,M5,
M7,Mll,N5,N7,
Nll
B8,C4,C5,C8,
Vss
Dl2,El2,F2,Gl2,
G13,H3,M4,M6,
M8,M10,N4,N8,
NlO
Input/output Description/Fqni;tion
QUtpUt
Initialinstruction decode-Indicates the start of a macroinstruction to an F chiJ?.
input
F chip sign N flag-Indicates that the result of an F chip computation is negative.
input
F chip sign Z flag-Indicates that the result of an F chip computation is zero.
output
Physical address lines-Transfer part of the DAL line address information to the M chip.
output
Abort-,--Indicates that the current microinstruction should be ignored.
outpµt input input input
Mini translation buffer miss-Indicates that a mini translation buffer lookup has failed.
Clock-A MOS clock signal from the M chip.
Complemented MOS clock-A complementary CLK signal.
Clock synchronization-Provides a phase 2 reference marker during a cycle.
input
Tristate-Causes the output buffers to
become a high impedance.
input input input
de low-Indicates that the de power is not within the required specifications.
Voltage back-bias-Power supply voltage for the substrate of the chip. (-3 .0 Vde nominally)
Voltage-Power supply voltage.
input
Ground-Common ground reference.
Data Address Lines (D.f\L < 31:00 >.-B.idirectiona1 lines used to transmit address and data to and
from the V.11 chipset, .the port controller, and the cache and backup translation buffer (BTB)
RAMS· The IfE. chip transfers address information during the first half of the the microcycle. Data
is transmittec;l and receiv7d by the DAL lines. The data is valid only during phase P7 when the data
is received from the cache or BTB )lAMs..When the data is received from other sources, it is valid
during phases P7 and P8.
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Confidential and Proprietary
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DAJ. Busy @AL BUS).')-This input is asserted when the port centroller has conu:ol of the DAL< 31:00> li~. When asserted, the DAL< 31:00 > outputs become a high i~ance. 'fhe
nl\I.!Jp$Y.sigtlal is a$Serted.dui:ing cache fill cycles . after the port controller bas accepted the
comm·nd sent. to it by the M chip. It is held·by the port contµ>ller until the. last loQgword of .the
cache fill has been received. The port contn>Jler also asser~ :the DAL lJUSY si,gnal during. I/O
invalidate cycles to hold the DAL lines while the controller transfers the invalid address to the
Mchip.
DAL Stall (DAL STALL)-This input is asserted when a data soun;e. cannot respond to a data transfer request during the same cycle; The 's0utt!e that reqnested the data' is stalleid' until the
responder can respotl<i, .The DAt stALL signal !JlUSthe de~~;by the end of Phase P4ifit is to
remain deasserted for the rest of the cycle.
Cache Miss <CiiBS).-This signal i~ a$serted by the M chi!,'>. quring memory req\iest write transactions, memory request read transactions that have each~ miSSC$, IB-fill trar1sactions th.at
have cache misses,. load PTE op'erations, and Mini-TB miss cycles that result in a miss in the BTB.
This input is used by the I/E chip only to indicate that a backup TB miss has occurred.
Content Addressable Memory Match (CAM MATCH)-Used to detect patched ROM locations duringaROMaccess·. This:signal is·assertedwhentheCAMin~the:DC3~7 cQ!itrolS10re&tects an
address with a patched mb:roinstructiotL. The execution 0f 1he faulty microinstruction is
suppressed by the AB6RT signal.
CPU Fault (CPU FAVL'f).-ThisJ.ine indicates. that a hatdware e1l1'Cir has d(tcurred andis ased for
driving an LED in the field. Refer to. Microseque:ru:ell.sect:ion fotdetailed in£0tmation.
M Error Trap (M £0 i'RAP}-~nili.line is asserted: by ~ Mchip to infurm the l/E chip of an
errot. The assertion of this signal causes the I/E chip to abort the microtrap operation. It is'asserted
when a paidty error~ on the&taread bperationfrom Ollie ofthe· tag~ys 'during a.memOl'y
request (MEMREQ),.m.fill, or Mini·TB mis& operation~ k is alsoassel!ted :When,tW: po.rt conttoller
asserts a port oontrolenor due ·to a data·~dtat:·haS ~.duringamemocy tead or write
operation·
C
Miaoinstruction Bus (MIB < 38:00 >)-This is the primary oohttdl buS. ·internal status bits and
mieroaddresses ar:e transferred on thisbm in pbasesP:liIDd P4 during.the address half of the cycle.
TheDC327controlstoredtlvesthemkroinst:nrotiomoritheM1B-<38:00>1inesirtphasesP7.and
P8 during the Iast half of the eycle.
Control Store Output Enable (~...;;'.A!lserted. to causethe-Outj;mt btiliefs;of the control store to
becoine.a:high impedance dwing,phases,P:6 .thtough.PS.
Control Store~ Bnahle (GSW£).;....Controhthe \Vritingoflilie'40~bl:t~rd to the RAM or CAM
in the control .store.
MIB Parity (MIB PAR)-This line indicates odd parity for the 39·bit control word during phasesP7 and P8,Jt. is.not·used during phase$PJ and P4·. When a pari;ty ~f!rror is detected; the. l/E .chip
forces a miaotrap.
Initial Instruction Decode (IID)-lndicates to the F chip that a new macroinstruction execution is
beginning and that the opcode on lines MIB < 22:15 > is valid.
F Chip N Bit (FBOX N)-lndicates that the reSult of an F chip computation is negative during
phases P7 and PS. When no F chip is present, a pullup resistor must be connected to thisinput. The
F chip also indicates an error by asserting the N bit during phases P3 and P4.
F Chip Z Bit (FBOX Z)-lndicates that the result of an F chip computation is zero during phases P7 andP8.
1·221
-
DC.328
Physical Address Lines (l>At < 6:0 >)-These lines provide the M chip with part of the address earlier than the address is available on the DAL< 38:00 > lines. When the :MTB MISS signal is asserted, the value on these lines is a virtual address. If the MTB MISS signal is not asserted,· the
address on the DAL<38:00> lines is a physical address. The mapping of the virtual and physical address of the DAL lines to thePAL<6:0> lines is shown in Table 2.
Table 2 · DC328 Physical Admess Line V'"tttual and Physical Addre~s Correlation
Virtual Address
DAL Line< 31 >
PAL Line
<30:17> <16:11> <10:00>
<0>
<6:1>
Physical Address
DAL Line PAL Line
<28:13> <12:06> <05:00> <6:0>
Abort (ABORT)-This signal indicates that the current microinstruction should be ignored. This
inhibits execution of the current microinstruction and forces the loading of the next microinstruc. tion.
Mini-TB Miss (MTB MISS)....,...This output is asserted during memory requests and IB·fill operations when a Mini-TB look.up fails. It indicates that a Back.up TB read cycle should be performed, a PTE should be passed from the BTB to the I/E chip, and the microinstruction or I .box request should be initiated again.
Clock (CLK)-This signal is driven by the M chip and is used by the I/E chip, M chip, F chip, and port controller chips. The CLK input makes a transition from a 0 to 1 at the beginning of every odd phase. The CLK frequencyis one half the frequency of the TTI.. CLK IN input to the M chip that is used to generate the CLK and CLK BAR signals. The nominal value for TTL CLK IN input is 40 MHz resuting in a 20-MHz CLK input.
Clock Bar (CLK BAR)-This signal is used by the l{E chip, M chip, F chip, and port controller
chips. The CLK BAR signal makes a transition from a 0 to 1·at the beginning of every even phase. The frequency of this signal is one·half the frequency of the TTL CLK IN signal. The nominal value for TTL CLK IN is 40 MHz, thus producing a 20·MHz CLK BARinput.
Clock Synchronize (CLK SYNC)-This signal is from the M chip and is used to synchronize the chip set and port controller by supplying the reference marker for phase 2 in the cycle.
de Low (DCW)-This signal is driven by the module to indicate that the de power is not within
specifications or is being restored.
Three State (TRISTATE)-This signal forces all of the output buffers to their high·irnpedance state. This feature is used only during parametric characterization, debugging operations, and for
module.test purposes.
Back-bias Voltage (V88)-A-3.0 V from an external supply used for substrate bias.
Voltage (V00) ......Power supply 5.0 V (nominal) voltage.
Ground (GND <)--:Ground reference.
1-222
Confidential and Proprietary
-
.·Preliminary
I/E Chip timing
The I/E chip.mictocycle is divided into eight: time slots Pl through PS shown in Figund. Two .
nonoverlapping docks and a. synchronization strobe ·are· reqWred to generate these phase~ The
eisht time slots can be .c;livided into five. ~ional time slots._-fetch, decode, drive the operands
onto the ipput buses, A:LU operation, and wtjte the results. The l/E chip is mpelin~ .such that the fetch and write cydeS, lill"e· overlapped. The overlap of mkI!Jiris~ructiorl5 Ularu.i U2 is shown.
MICRO Cl'CLE WRITE
Pl
P2
DECODE V1
P3
P4
DRIVE U1 OPERANDS :
P6 U1 >l-1.U OPEJllATION
Figure J · DCJ28 Miemcycle ~g
The IJE.chip is interiacedwith the system throl.l8h the time.mulijplexed microins.ttuction. bus
(MIB < 39:00>) and the data address lines (DAL<ThOO;;o),.I;head$ess istransfenedduring the
first halfof the cycle (P3
cycle (P7 ~d P8). F~
and P4) 4 shows
arid
the
the ~ta
lYUB apd
is t~fPittl!d
04 titUi~.
~r
~. .eived.
.in
the
SC.(l().nd,
h!llf
o. f
the
MlCROCYCLE
P8
Figure4·DC32SMffi<J9:ori> andD:tti..<31:00> Timm.·g
' ..,
'
'
'
'
Fwi~I>esct~ Flgul:e lshows the fµn,:.:tional elements, bus struc~, and·~ lines o;£· tht;.I/E chip. Refer ~
DC328 I/E Chip Funetional Speci!;iat<tionfor detailed pperaj:io~·of t~ clrlp. Abrie( deS'Ctiption of the l/E chipfollows:
lnstrtJctimt·~ and Decoder (I Bdrt)-.-The l box prefetches the instruction stream,
generates microprogram fork addresses, and provides instruction :data to the E box. The
instruction programmable l!)gic array (IPLA,)is l9Catedin theJ:®x.
Microsequencer-The microsequencer determines the address ofthe next microiasi;metion robe
fetched and executed from the external control store ROM/RAM. Its facilities included an eight-
entry stack, and two adders for fast next-address generation in conditional branches. It also has
special hardware used to enhance the power of microdiagnostics and handles microtrap generation.
Execution Box (E Box)-The E box contains facilities to implement the VAX instruction set. The
E box contains the general purpose registers (GPRs), temporary registerS,, (TEMPs), and working registers. It also includes a shifter, a 32-bit arithmetic logic unit (ALU), a constant generator
(KMUX), and the shift counter (SC) register.
-
Memory Interface-The memory interface converts program generated virtual·· ad<fyesses ·to
physical ac;ldresses and'governs all data requests of mijn memory or the cachedt also:has facilities
·to improve the performance of common memory management exceptions.
DAL Interface-The DAL interface connects the I/E chip to the external data path. Itperforms
byre rotation, buffering, and determines when the data on the DAL< 31:00 >.lines is valid.
MIB Interface-Th~ MIB interface connects the I/E chip to the external controfstore through the
MIB. It receives and checks the parity of the microcode words that are read from the external
control store, controls the sequencing of the ROM/RAM chips, and oversees the use of the MIB for
passing interchip status signals. It is also used for writing the patch RAM section of the DC327
ROM/RAM chips.
.
Interri.al Bus Structure
Five of the internal I/E chip buses are 32-hit data buses and the remaining two are used for control.
The f()llowing is a brief description of the major buses.
.
Internal Memory Information (IMIB < 38:00 >)-The IMIB < 38:00 > lines provide the main
control and are used to transfer the microinstruction to all other logic functions in the chip.
Because the I/E chip cannot stall the clocks, it must execute a microinstruction every cycle. The information on this bus is v:tlld every cycle. The memory interface logic inhibits write operations
that are associated with a stalled microinstniction. ·
·
Microtest <'.):0 >.;..;..The n:tlcrotest bus is used to transfer'the results ofa conditional branch test to
the microsequencer. The microsequeneer uses thls ·value and the branch cornmand field to
determine the next microaddress to be driven to the control store.
Internal Data/Address (IDAL < 31:00 >)-The IDAL bus connects the DAL< 31:00 > lines to the
internal register file. It is driven by the memory interface during the address portion ofthe microcycle and during the data hatf of the microcycle if the datais being written by the I/E chip. It
> is driven by the DAL <31:00 lines if thel/E chip is executing a read transactiori.
D-stteam Bus (DBOS < 31:00 > -This bus connects the E box registers to the IDAL bus and is
driven when the I/E chip reads D stream data or external registers. The microinstruction specifies
the E box register to be loaded from this bus.
AW Bus (AWBUS < 31:00 >-This is the main data bus between the I box, E box, and memory interface and is used as one of the input buses to the ALU. It also transfers the result of the
computation from the ALU. During a normal ALU operation, one of the operartds (inputs to the
ALU) is driven onto the AW bus by an E box register. After the ALU operation, the results are
transferred onto this bus and are then written into an E box register. Wheti data is befog written from the E box to the DAL lines, the AW bus is used to transfer the data to the memory interface that then drives' the DAL lines. It is also used to connect :registers located in the Ihemory.intetface and I box to the E box registers.
B Bus (B < 31:00 >)-This bus is located in the E box and is driven by E box registers to provide
the .remaiojng input to the ALU.
1-224
Confidential and Proprietary
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DC328
· Specifications
The mechanical, electrical, and environmental specifications for the DC328 are contained in the
following paragraphs. The test conditions for these specifications, unless specified otherwise, are
as follows:
· Ambient temperature (T.J: 0°C to 70°C
· Supply voltage (VDD): 5.0 V ±5% (maximum ripple ~00 mV peak-to-peak)
· Back-bias voltage (V98): -3.0 V ±15% (maximum ripple 200 mV peak-to-peak)
Mechanical Configuration
ThemechanicaldimensionsformountingtheDC328132-pinPGApackageareshowninAppendixE.
· Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may caus~ permanent damage to a device. Exposure to the absolute maximum rating conditions for extended periods may adversely affect
the reliability of the device.
· Supply voltage (VDiJ: -0.5 V to 7.0 V · Pin voltages: -LO V to 10 V · Power dissipation (TA= 0°C): 7.5 W · Power dissipation (TA= 70°C): 5.0 W · Ambient temperature operating range (T"): 0°C to 70°C · Storage temperature range: -55°C to U5°C
Recommended Operating Conditions · Supply voltage <Vee): 5.0 V ± 5% · Ambient temperature operating range (TA): 0°C to 70°C
ac and de Electrical Characteristics Refer to the DC328 J/E Chip Functional Specification for the de input and output parameters and
ac timing parameters.
Confidential and Proprietary
1-225
· Features
· Contains memory management logic · Provides tag store for cache memory and backup translation buffer · Provides functions for interrupts, communications, and timing
· Description
The DC329 V.11 processor memoeymanagement(l-f1drip} Jogic, ooritaineclin a 132-pin, pin,grid array (PGA) package, i.11cludes most of the tnemory management hardware and the tag store for the cache memory and for a 512-entry virtual·tp.physical address backup translation buffer (TB;BUJO). The BTB supplements the mini-TB that is located in the I/E chip. The cache data and the, .&TB address translation entries are stored in exremal static BAM chips. The M chip also contains miscellaneous CPU functions such as CPU clock drivers, processor registers, the intel'Wtand tirn.eof-day timer registers, interrupt hardware, clock-generation circuits, and four serial-line units, Figure 1 is a block diagram of the DC329 M chip.
CONTROL LOGIC
CASHECS OUTPUT EN
Peffn<3:0>
CLK CLKllAR mcLK
a.KDIS
CLOCK GENERATOR
PME
ADDRESS
OUT
TIWjlll,ATIOl'j
LOGIC
TIMER
R UA!fu:T
, IJNnr3
UAllT3T
Figure 1 · DC329Memory Management Logic Block Diagnam
1-227
-3·····
····~> ..
· Pin and Signal Descriptions
The input and output signals and power and ground connections for the 132-pin package are summarized in Table 1. The table also contains the physical pin locations that are shown in Figure 2. The following paragraphs provide a more detailed description of the inputs and outputs of the Mchip.
Table 1 · DC329 Pin and Signal Summary
Pin
Signal
Input/output* Description/Function
K13,Kl4,G13, DAL<.31:00> Jl4,G12,Hl4, F13,G 14,Fl2, F14,E13,El4, El2,D14,D13, · Cl4,C13,BlJ,
B14,Bl2,A14'
Bll,Al3,B10, Al2,C9,All,B9, A10,C8,A9,B8
input/output
Data/address lines-Transfers data and address information to and from the V-11 chipset.
D2
DAL BUSY
input
DAL busy-Indicates that the D~L < ?1:00 >
lines are controlled by the porfcontroller.
Al
DAL STALL input/output DAL stall-Indicates that the dat:ll ~urce can-
not respond to the data request in the same
.cycle.
Bl
input
Abort'-Asserted to ignore the last rnicro-
instruction.
N12,Nl3,M12, Pl4,M13,Nl4, L12,Ml4,L13,
L14,K12
MIB<.38:28>
input/output
Microinstruction bus-The primary control bus to transfer commands and status information.
B4,A4,C5,A5, B5,A6,C6,A7,
B6,A8,B7
CAL<10:00> outputs
Cache address lines-Provid.es physical
address to cache and virtual address to BTB
PTE.
Jl
BCIACLO
input
BCI ac low-Initiates an ac power low
interrupt.
H2
BIINTR4
inputs
BI interrupts (4-7)-BI bus interruptJeve,k14
L1
BIINTR5
through 17
L2
BIINTR6
17
BIINTR 7
A2
output
BTB chip select-Asserted to transfer data to
or from the BTB PTE RAMs.
1-228
Confidential and Proprietary
Pin
Sp
Input/output* Description/Function
B3
·mHEcs output
Cache chip select-Asserted to transfer data
to or from the cache data RAMs.
M9
CLK·
input/output Clock.;..,...A MOS clOck signal to the J/E chip; F
chip, and port controllers.
MlO
CLKBAR
input/output Clock bar-A comPiement MOS CLK sigllal
. to the I/E chip, Fflll~ a~~ part controllers.
NlO
cu: SYNC
input/output Clock synchronization-Provides Phase 2 ref-
erence for synchronization.
B2
input/output Cache miss---Asserted during cache misses,
load PTE operations, and cycles that miss in
theMtll.
]2
CNSLINTR input
Console .interrupt-Asserted to indicate an
· ~b1ein~pt.... · · ·
K3
CRDIN'I'R input
M5,N4,M4,N3 .WREN<3:0;> inputs
PlO
Btincr:o · input
Dl
MERR
output
P9
MTBMISS
input
K2 A.3 P3-Pl,N1 C2
NIINTR
input
OUTPUT EN output
PCMD<4:0> output
PCNTLERR input
<;:or~cyed read da,ta inter.rupt-Asserted to reqU£:St an intd:rupt anlPL 16.
.. B'.fB/c~he wr!te enable::-
BCicttl0w-lt1cUcatJs that the power supply
voltage will be .below.the specified minimum
value:
M chip error-lnforros the JJE chip of an
error. wtidition.
. Mini,TBmiss::-::-:lndicates.whether a cache or BTB·a<xzess iS ri:4uiredwhen a mini-TB miss has occurred.
an NI interrupt-Indicates that· unmaskable
interrupt is posted.
·
Otttput ~ble-Controls the outpilt enable of the~a'che and BTB.
Port controller command......Pr®ides; c~m
ma:ndS'to the port controller.
. ' '
~
Port controller error-Indicates an error has
~inthe portcontrollerduring a.data
ltarisfer. ' · ·
· ·· ·
Cl
PCNTLRDY input
P7,N6,P6,M6, PAL<6:0> input
Port controller ready-Indicates that a com-
mand can be sent to the port controller.
Physical add.fess< 6:0 >-Provides a physical or virtual address to the M chip.
ConfidcntW.andProprietal'y
1-229
-
Preliminary
DCJZ9
Pin
Signal
Input/output'* .Description/Function.
M2
PMEOUT
output
Performance monJ.tor enable-Indicates the
state of the PME bit in the PlLR.
N9
TTLCLKIN input
TTL clock-A TTL 20-MHz dock signal for
UARTs and timers.
PS
CLKDIS
input
Clock disable-Disables the clock outputs.
Ml
TRISTATE
input
Three state-Disables all outputs of the M
chip except for the CLK, CLK BAR, and CLK
SYNC.
GJ
UARTORCV input
UARTO receive-Serial-line input from
UARTO.
F2
UARTOXMIT output
UARTO transmit-Serial-line output to
UARTO.
Hl
UARTlRCV input
UARTl receive-Serial-line input from
UARTl.
Fl
UARTlXMIT input
UARTl transmit-Serial-line output to
UARTl.
G2
UART2RCV input
UART2 receive-Sedal-line input from
UART2.
E2
UART2XMIT input
UART2 transmit-Serial-line output to
UART2.
Gl
UARTJRCV· input
UART3 receive-Serial-line input from
UART3.
E2
UARTJXMIT input
UARTJ transmit-Serial-line output to
UART3.
C3,C4,Cl0,Cll, VDD H3,H12J12,M3, M7,M8,N8
input
Voltage-Power supply voltage.
C7,Cl2,D3,Dl2, Vss E3,H13J12J13, L3,Mll,N7,Nll
input
Ground-Common ground reference.
N2
Vaa
input
Back-bias voltage-Power supply back-bias
voltage ..
*All pfus have TTL compatible levels except CLK and CLK BAR.
1-230
Confidential and Proprietary
-
l4 13 12 11 10 9 . 8 1 '.6 5 4 3 2 1
p 0 0 0 0 0 0 0 .0 0 o. 0 .0 0 0 N 0 0 0 0 0 0 0 o· 0 0 0 0 0 Q
M 0000 0 0000 00 000
L 000
0 0 0
K 00 0
0 0 0
J 000
H 0 o·o
G 000
DC329
0 0 0 0 0 0 0 0 0
F 000
o>, Q 0
E 000
0 0 0
D 000
0 0 0
c 0000000 00 000 00
B 00000000
0 0
A 0 0 0 0 0 0 0 0 0 Q· Q 0 0 0
14 13 12 11 10 g 8 7 6 6 4 .f' 2 1
lOPVIEW
Figure 2 · 1JC329 Pin As#g?t~mts
Data/address Lines (DAL< 31:00 >)-These lines are used for transmitting addresses and data to
and from ~V-ltchipset, the PQ~t contro~,andtl1e:cacb(! RAM1~·'J;'he:Mchip ~eivesaddress and
data ipformation ~ transn;dts dataon, this:bus· The da~.iiivafid9my dtJ;ring pha8e 7~hen the ~ta
is &0111 the.cl!Che da~ RAMs. Whenthe qata is.Jl:'Om the M>c;hip, kis valid for.M~es P7 3Jltl.)?8.
DAL·B~.(DAL IUSY)-.This inpgt is·1\s.serted·when theport controller·has·cont:rolof··the
DAL< 31:0 > lines. When asserted, the PAL lines are ahighim.pedance and the DAL STALL'and
CMISS are released by the Mchip. It is'$5$erteddut~ tachefill:eycles after the po:i:t controller.·has
ac~pted the..com:mand s~t Ip it by .d;ie.·:M chi,,f>. )t is held .~ .the: .PQn controller until t:hel.l!lst
an longw:ord of the cache operation has bJren ~ivr;d. 'J;'he ~·controller .a1:1a .$sserts this ~t > during I/O invalidate cycles to ~nable it to drive theinv~~te~~onto the.04 < 31:0 lines..
DAL Stall (DAL.STA.LL);This signal.~.iwe*4whena~ta $0~.cannot ~P9ndJo a data
transfer requestit} the sapie cycle. Th~ resou~ ~trequ~sted the da'ta j.s stalled until d1t! source
can resPQnd. The M chip asserts this.signal when the cache or bac~p minslatU?n buffer is busy
command with a previOQs .command· and a new
is teet!ive<f ~hi~ i:equests the M chip~ It~ used
during the.first ready cycle ~£ an MREQ read transaction t~~tha~ a ca~he .miss, af!d when there is a
imd read miss or a cache write and the port controller is not re;ady. The M chip also asserts the I5XL
smI signal when the l/E chip :it~!Ilpts to read the P'fE adC1er the M chip is c~atin~ the
result. It is also used to stallthe 'I/E chi() during the first cycle of t~ two cycle MXPR read
operations and during the second cycle of the tWo cycle MXPR wrlte opet'iltions if the micr0code is
attempting to initiate another operation that requites the M chip. The M chip does not assert this
signal when the DAL BUSY input is asserted. The DAL STAll signal must be deasserted by the end
of phase P4 if it is to remain deasserted for the rest of the cycle.
Confidential and Proprietary
1-231
-- ·---------------·--------------..-··-··-------·-----·-.. -·--·-·-' ______ ..... ., .......
Microinstruction Bus (MIB < 38:28> )-This is the primary control bus and the M chip receives
U of the MIB<39:00> lines in the system. LlnesMIB<38:32:::> are used as input to the M chip and lines MIB < 31:28 > are bidirectional tfuee-state lines. During the first half of the cycle, the M chip transfers status information on lines MIB < 31:28 > and during the second half of the cycle it
receives status information. on. lines MIB < 38:32 >. The M chip receives commands on lines MIB < 38:32 > during the second half of the cycle. The status information received by the M chip
during the P3 and P4 phases is listed in Table 2. Table 3 lists the status transmitted by the M chip
during phases P3 and P4.
MIBLine 38-35
34 33 32
'Tuble 2 · DC329 MIB Line Status Received Description Write mask bits as follows:
Bit 38-Longword bits 31:24 (byte 3) Bit 37-Longword bits 23:16 (byte 2) Bit .36-Longword bits 15:8 (byte 1) Bit 35-Longword bits 31:14 (byte O)
IB Fill
Using DAL
Request second reference
The write mask (bits38:35) indicate to the Mchip which longword bytes are to be written into the cache and main memory or to the I/O device. The M chip uses these bits to enable the cache write enables if the cache hits on a MEM REQ write instruction. Each bit corresponds to the assodated cachewrite enable output. These bits are asserted to 1 and are supplied to the port controller on the PCMD4:0 outputs. These bits must be set whenever the microcycle is not a MREQ write instruction and low when asserted on the MlB asserted implies that the byteis to be written.
The IB Fill MIB34 'line is asserted low when the M chip is not completing a p~ious operation and initiates a read operation to read the requested VAX instructionlocated at the address present on the DAL lines during the address half of the DAL cycle.
The Using DAL MIB33 line is asserted high to indicate to the M chip that the current microinstPiction uses the DAL lines. This bit is used in determining when the current microinstruction has been completed.
The Request2nd reference MIB32 .is asserted Iow to indicate to the M chip that the reference is unaligned'~nd that two MJIBQ operations are required to transfer allofthe data. This applies to
urialigned read and unaligned.write transactions. It is asserted for the flrst unaligned data reference and pi:e~rits,tihe ~-chip £iom updating the microinstruction that ~<mld cause it to reexecute the memory ~uest (MREQ). The upd~ted address is supplied by the I/E chip'. .
1-232
Confidential and Proprietary
Prelimimtty
t>CJ29
31 .
Letigth violation
30
29
IID interrupt request
28
FPD intenuptrequest' ..
The length :violation MlB31 output reports the rompUiSQnof the:value$'fontairied in a selected
p~~·<>rsY5lemlengtl;iremte;Yfitl;i'qe.MVA~Ht.')/tft~MJA~in~cle(~},the·first
microcycle
that
can
branch
on
the
new
...is(n+ sta.~ , __ , __ , ,- - ___
i:, 4).'.
·
The systemsp~e M$.3.0 outp~t ~.~qyilllalent to th~;Valµtt~£~N'A~l,
The IID .interrupt request ·MIB29 .output is the intetnip1Jteq_uest generatedrhy the iiltettupt controller, It is asserted high · n there is"~·pending truiskable .interrupt inputthllt has 11: wlue
.above .the .current WL,. 'Vliet> ·1\h~ .ili. an. ~~bl~ int~iµJil!:: pen4ing, ort~ ~,;ISTATUS
H,t\Ll' ~it is set: Wrjting1.to t~ Sl~lt. the~. OF ~ I~Wt,T$ ¢an,,f~ a ~ein f;he intert;i,tpt
Status on,~.~; 'nris·.isin~tjpn to m~,in~~~Jnpµts ~.~caµseintertupts.
,There is a~ betweeti chqWgone af tlutSe re~):ers ~'~~~ o; that ~on t]:ie IID
input.
The FPD interrupt request MIB28 ·output'. is the.inmruPt:·.request generated by the interrupt
a controllet. It is asserted.high when there is pending muk~ inttiNpt 1np\tt that has a wlUe
above the current U'J;; 11>r when munmnkable ~l'1.lpti5:~ed. :The ~istheSaine ·.«s for
the IID ilitetrupt request status signal.
·
and The microinstruction formats that are recognized'tin theMIRduringphasesP7 PS ate shown
in Figi.:u:e 3; ·
·· ' "
MXPR:
MIS MEM REQ:
Figure 3 · DC329 MIB Microinstrnction Format
Confidential.and Pmprietary
'1-233
-
Preliminary
/OCJ29
Abort (ABORT)-This input i~ ~~rted whep th~,Wtinstructionon, the MIB in the previous P7 and PB phase is to be ignored. Because the ABORT signal is generated by the I/E chip, the M chip may not be executing the same microinstruction as the I/E chip and therefore it applies to the instruction that the I/E chip is executing. When this occurs, the M chip ignores the abort. If the M
chip asserts the MERR signal, the ABORT signal will be asserted by the I/E chip in a subsequent
cycle, causing a microtrap to occur. This ABORT signal must be deasserted by the end of phase 3 if
it is to remain deasserted for the rest of the cycle.
Micro Error (M ERR)-This signal is asserted by the M chip to inform the "f/E chip of an error
condition. It causes the I/E chip to abort and microtrap when there is a parity error on data read from one of the tag arrays in an MREQ, IB fill, or MTB miss operation and when the port controller asserts a port control error due to a data error on an MREQ read or write operation.
BCI ac Low (BCI ACLO)-This is an interrupt input to the M-chip. When asserted, an interrupt is
requested at IPL 16. This signal is sampled each cycle and is not latched by the M chip.
Port CobttoDer Error (PCNTL ERR)-This inputinforms the M chip that an error has occurred in
the port controller as a result of a data transfer operation.
Port Controller Ready (PCNTL READY)-This input informs the M chip that the port controller
is ready to accept a command. When deasserted and the current instruction requires the port
controller, the M chip will assert the DAL STALL signal until the port controller becomes ready.
Cache Address Lines (CAL< 10:00 >)-These outputs provide the physical address to the cache
during cache read and write cycles and the virtual address to the BTB during PTE ·read and write
cycles. The cache data array is organized into 2K longwords that require 11 address lines. The BTB contains 512 PTEs of one longword each. The CAL< 10:00 > outputs reflect the address sent to the M chip on the DAL<.31:00> lines during the first cycle of cache read operation and MTB miss cycles. The source of the CAL< 10:00> information is the MVA for the load PTE operation.
During cache fill operations, the M chip modifies the value of the CAL< 1:00 > lines by incrementing them by modulo four (starting from the value of these bits supplied on the DALlines)
each time one of the four longwords are received. The CAL line value is derived from the address
received on the DAL<31:00> lines or from the MVA.
Cache Chip Select (CACHE CS)-This signal is asserted when data is to be transferred to or from the cache data RAMs during read and write operations. The direction of transfer is specified by the WREN <3:0> lines. The RAMs address is on the CAL< 10:00> lines.
Write Enable (WREN< 3:0 >)-These lines specify the direction of the data to the cache and BTB data and parity RAMs. When active, the data for the associated byte in the cache or BTB RAM arrays is written. The chip selerct lines determine which bank of cache or BTB is to be written. The lines are asserted during the following:
· An MREQ write operation that has a cache hit. The write mask that is received by the M chip during the MIB line status transfer is used to determine which of the 4 bytes in the longword are to be written.
· When the cache is written with data on a cache fill. All 4 bytes are written and the write mask contains all ones.
· During an MREQ read operation of the PTE.-When the PTE returns from mei:µory, it is loaded into the PTE store and the write mask contains all ones.
· During an MXPR write operation to the PTE. All 4 bytes are written and the write mask contains all ones.
Confidential and Proprietary
...
Preliminary
BTB Chip Seleet {BTi CS)-This signal is .as$erted when data is to be transferred to or from the
BTB PTE.UMs dul:':il'lg read and write opel'.S.tions. The diteQtion of transfer is specified.by the WREN< 3:0 lines. The RAM address is on the CAL< 10:00> lines.
Output Enable (OUTPUT EN)-This output is used to enable the cache and BTB data chips. When asserted, the selected bank of data RAMs will drive the DAL lines.
Cache Miss(~)-.This signal is an 9u.~p,Ut.%>~.~ M cltjpw~en the """DA~L~B~.1J-S.~Y signal is not
asserted and is an input to the M.chlp when the '5At IftiSY' sign.SI iusserte<f It is asserted on
reswt MREQ write and read operations that result in .cache misses, IB fills transactions thllt ti:sult in
cache misses, load PTE operations, and MTB miss cycles dlit
in a miss in the BTB. When
asserted by the M chip and the MTB l;lliss is not true, this iii,sn'1#@.icates to the PQrt controller !hat
the command that was sent to it is to be executed. The ~;signal is deasserted by the end of
phase 4 if it is to remain deasserted for the rest of the cycle. During cache read misses and load PTE operations, the CMISS signal is asserted by the Mchip for each cycle up to and including the first
cycle in which the port controller is ready. The port controller then asserts the CMISS signal until
the completion of the fill operatiot?-· TheMF,hip $0 waits fort~e portCQaticlkr to ~JQ(1: ~Y
during. write cycks, The CM!SS ~put is.~ to .~cat:e ~tthe f.4·. chip igo perior~ an I/O
invali4te cycle.
DAL SfALL and
TDhAeLJB?QUl'St Y~n~tirgonlallesr~d~at$hseirstedb.y
deasS(!rting
thls.,S~
. .
a,;.the
sam.e
time.
t.h· .iit
the
Port Command (PCMD <4rtl>)--These outputs pl'QVide the comm.and to. the. port>controller
dur~ phases P3 and P4 and the write maslc d)JI~ pb~s.1'1 a11c.i pg. The co~and is ex.eoited
only by. the J?Qrt controller if the ~ is ~ted ~tet 4t Wat· cyde.. The wrl,te.·mask is used by
only by the port controller during write operations. .·
·· · · ·
.
The Cloclc (CLK)-The CLK signal isPM()S l~ input. ~FMP ~%~,thisputp1,1t back ~o its<;lf as
an input and it is used on the module by the I/¥ cpjp, F cllip,,~~ portcopµnJk:r chips, A transition
of this signalfrom a. 0 to 1occurs at the beginniug ofev!!ry ()(fd P,Qase· the·~~epcy ofthis ~is
one-half that of the TI'L CLK IN signal. It Cru1 be \lse<f asan llip\lt for test purposes by ass~rting the
CKL DIS signal and driving the CLK inpu~ from an ~nal s0~e. .. .. :. · . . ·
Clock (REF CLK)_:_The REF CLK input is. the 20-MHz clo~ reference for the time-of-day timer,
interval counter registers, and UARTs.
·
·
. ·
Bai Clock (CWcK BAR)~The CLK BAR sigOal is a MOS l~t iheut: The M chit? dri~s this
modUk output back to itself as an input and it is used on the
by the .Iff: chip, F chi~, and PQrt
frOsn· controller chips. A transition of this sigmll a 0 to :h'><:ct:lrs at the' begitlning ot every even
phase. The £requency'Of this clock is one"half that of the'I'iL CJ:.K lN si:gn!tl. It can·be used as an
input for test pU,.rposes py asserting the TRlf'l?AfE sighaland by·Ori'i'ing CLK BAR input from an
external source.
Clock S~ (CLKSYNC)~This s,ignal is tl'a!lsfe~ fO theV~ll chip set to synchronize the module by supp~ the reference for pliase 2. i.~the cycle. It CEµ)~ used for .test purposesby
asserting the CLK DIS input and by driving~s'input fr0in an external source. Clock Disable. (CLK I>IS)-When this inp~ is. assert~, all 1-4 .chip oqt:p~ts except for the CLK,
CLK BAR, and CLK SYNC outputs are enabled. This input i:pµtains an interna,l pullup resistor for
the normal operation state.
Three State (1'RISfAi'E)::-When asserted, this input cau$eS the outputdrivers t.o. become a high impedance. This input contains an internal pullup resistor to holdit deassertecl during normal operation.
1-235
-
P:teliminary
Physical Address Lines ·(PAL< 6:0> )-These inputs· provide part of the address that was previously referenced on the DAL lines. Table 4 lists the address bit correlation for a virtual address (MTB MISS asserted) and for a physical address (MTB MISS not asserted).
'Iable 4 · 0Cl29 PAL Line V1rtual and Physical Address Conelation
Virtual Address
DAL Line PAL Line
31
< 16:11 >
0
<6:1>
Physical Address
DAL Line PAL Line
< 11:6>
<6:0>
Mini-TB Miss (MTB MISS)-This input is asserted by the IfE chip when there is a mini-TB miss.
The M chip uses this signal to indicate whether the BTB or the cache is to be accessed during an MREQ operation. It is a qualifier on the address received on the DAL and PAL< 6:0 > lines that indicates whether the address is virtual or physical. When asserted, the M chip transfers the virtual address onto the CAL< 10:0 > lines and reexecutes the last microinstruction.
BI Interrupt (BI iNTR < 4:0 >)-These are interrupt inputs to the M chip. When a line is asserted,
an interrupt is requested on IPL 14 through IPL 17. These signals are sampled during each cy9e and are not latched by the M chip.
Console Interrupt (CNSL INTR)-When asserted, an unmaskable interrupt is posted. This signal is sampled each cycle and it is not latched by the M chip.
CRD Interrupt (CRD I'NfR)-When asserted, an interrupt is requested at IPL 16. This signal is
sampled each cycle and it is not latched by the M chip.
NI Intenupt (NI INTR)-When asserted, an unmaskable interrupt is posted. This input is sampled each cycle and is not latched by the M chip.
ac Low (BCI ACW)-This input is asserted when the ac voltage is below the specified limit and
initiates an interrupt request on IPL 16. This input is sampled each cycle.
de Low (BCI DCW)-This input signal is asserted by the power supply when its output voltage is about to be lower than the specified minimum value. When asserted, all.outputs of the M chip become a high impedance e;xcept for the CLK, CLKBAR, CLK SYNC, and OUTPUT EN outputs. The CLK and CLK BAR outputs are normal. The CLK SYNC signal and OUTPUT EN signals are deasserted. When the BCI DCW signal is deasserted and the CLK and CLK. BAR signals are
asserted, the first assertion of the CLK SYNC signal is within four or six TTL CLK IN cycles. After
this signal is deasserted, the M chip will remain in a reset state and the outputs will be a high impedance for the first three cycles of the CLK SYNC output. When the CLK SYNC signal has pulsed a minimum of four times, the M chip will respond to microinstructions on the MIB, and the high-impedance outputs will be enabled.
Voltage (V88)-This input is used to supply the back-bias voltage to the module.
Performance Monitor Enable Output (PME OUT)-This output has the same value as the PME bit in the P1 lengthregister (PlLR). Refer to the Register section for a description of the PlLR If the state of PME bit changes, the PME OUT signal will be valid during phase P4 of the following two cycles. If the PME bit does not change, the PME OUT signal will be stable for phase Pl through P8.
1-236
Confidential and Proprietary
-
TTL Clock Input (TTL CLK IN)-The TTL clock input is nominally 40 MHz and is used to generate alldock signals to the V-ll chip set. The M chip provides a 20-MHz MOS level dock pulse to the.~ther¥ll chips by dividing the input by two as the reference.
UART Receive and Transmit (UARTO R-UART3 Rand UARTO T-UART3 T)-These lines provide the serial line inputs from the four UARTS and serial·line outputs to the four UAR'IS. Each input is asynchronous to the"reference clock
Voltage (V00)-Power supply voltage 5 V (nominal)
Ground (V55)-Signal ground reference.
· Functional Description
The DC329 contains the functions shown in Figure l and is d¢5Cribed as follows. · Address translation logic · Backup translation buffer tags (BTB) · Cache tag array · Clock generator · Control logic · Priority interrupt/halt controller
· RAM temporary regis~rs · Timer logic · FourUARTS
Address 'lianslation Logi.c
The address translation logic (ATL) calculates a page-table entry address when the page~table entry:
necessary to translate a virtual address..isnot in the mini.o~.b~p ti;anslation buffet's. Thi;:. A'IL
contains the following registers;
·· ·
·
· PO base registi;:r (POBR)
· PO length register (POLR)
· Pl base register (PlBR)
· P1 length register (PlLR)
· SO base register (SOBR)
· SO length registet' ($0LR)
· PTE translated address (PTE ADR)
1-237
k¢.,....,.....,.'.W'.---·--"- - - _ -~·-··----~--·-----------..,--. _ _ _ _ _ _ _ _ _ ...,,..oe;..............!.§.r.1.tl.ll.d.!!.U.....
_~
...
Preliminary
Backup Translation Buffer
The backup translatitm buffer (BTB) is a direct mapped arraywith 128 entries, grouped into system and process spaces as determined by bit .31 of the virtual address. Each entry' contains a tag that corresponds to a group of four page-table entries (PTEs) and four valid bits, one for each PTE. The 512 PTEs are not included in the chip and are typically industry-standard RAMs. This array is used on MREQ or IB FILL operations when the MTB MISS signal is asserted and on the MREQ read PTE operations. It is also used in some MXPR instructions and contains the following registers.
· Memory address register (MAR)
· Missed virtual address register (MVA)
· Invalidate address register (INVAR)
· Refresh address register (REFR)
· BTB tag, valid bits, and parity bits register (BTB ENTRY)
· BTB invalidate register (BTB INV)
· PTE array register (BTB PTE)
· BTB status register (BTB STAT)
· Error status register (ERR STAT)
Cache Tag Array
This section contains 128 direct mapped cache tags each of which is mapped to a 64-byte block of contiguous physical data. Each tag has four valid bits to indicate the validity of each octaword (16
bytes) in the allocated block. The registers in this section are
· Cache tag, valid bits, and parity bits (CACHE ENTRY)
· Cache status register (CACHE STAT)
Control Logic The control logic is distributed throughout the chip. It receives the control inputs and generates the internal and external control and contains the following registers.
· Indirect MXPR register (INDIR)
· Indirect address value register (INDIR ADDR)
· No-Op diagnostic register (NO DRIVE)
Clock Generator The clock generator divides the 40-MHz TTL CLK IN input bytwo and generates the dock sources
(CLK, CLK BAR, and CLK SYNC). It also receives the CLK, CLK BAR, and CLK SYNC inputs so
that it can generate the M chip internal phases.
1-2.38
Confidential and Proprietary
Pre.Jim. m· aey
Priority Interrupt Contmller
. .
The ir).tefl'l1pt secti0,n .of. the .M chip receives the internal arid external intem.ipt requests and
reports an active interrupt if there is an interrupt whose priority is higher than that of. th~
processor's current priority. The software HALT request in the ISTATUS register is reported with
the interrupt requests during the MIB status transaction. It also containsh~ware logic to support
REI instruction. The registers contained in this section are
· · .
··
· Interrupt priontylevel (!PL)
· Interrupt status register (!STATUS)
· Asynchronous system trap level (ASTLVL)
· Processor status longword (PSL)
· Processor stafus longword temporary register (PSL TEMP)
· Software interrupt status register (SISR)
RAM 'lemporary Registers
... .
The RAM temporary registers are MTI::MPO thn:>ijgh MTJ;:MP17:;
TnnerLogic
cart The timer logic consists of the interval counter (IVC) and time-o~-<:!a~ ~s,t~('f()I)~). 'JJi~ IVC:is
used to provide a source of interrupts at a i:epeatable rate that be p~edby ~f~arein i
µs steps. The IDDR supplies the real-time clC>Ck function, teflecrlrigtheirela.~·timeJ~mitslast initialization. The TODR als<> is used to piov~ ~periridie ~ ?f~.~ka:ble.i,q~l?ts ··~ 1.28 seconds. This logic oontains thefollo\ving registers: ' ·· ·. · . · · ' · ·
· Interval counter.control and status register (ICCS} · lnterwl counter·valueregister (ICR)
· Next interval counter value register (NICR)
· Time-of-day register (TODR)
· Time-of-day prescaler register (TODPRE)
Universal Asynchronous Receivers and Transmitters Each of the four universal asynchronous receivers and transmitters (UARTO through UART3)
contain a status register and a data registet.
The mechanical, electrical, and environmental specifications for the DC329 are contained in the following paragraphs. The test conditions for the parameters specifications, unless specified otherwise, are as follows:
·Ambient temperature (T.J: 0°C to 125°C
· Supply voltage (V00): 5.0 V ± 5% (maximum ripple 200 mV peak-to-peak)
· Back-bias voltage (V88): -3.0 V ± 15% (maximum ripple 200 mV peak-to-peak)
Confidential and.Proprie~
1-239
DC329
Mechanical Configuration
The mechanical dimeruµotjs for moti.nting the DC329 132-pin CERQUAD package are shown in
AppendixE. · · · ··
·
· Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause per~anent damage .to a gevic~. Exposure to the absolue maximum rating conditions for extended periods may adversely affect the reliability of the device. · Power supply voltage (V00): -0.5 V to 7.0 V · Back-bias voltage (V88): - 7 V to 0 V · All other pin voltages: -1.0 V to 10 V
· Power dissipation (TA = 0°C): 5.25 W
· Power dissipation (TA= 70°C): 3.5 W · Ambient temperature operating range {TA): 0°~ to 70°C · Storage temperature range: -55°C to 125°C
·Power supplyvoltage(Vcc):5,0 V ±5% · Ariibient temperattire operating range (TA): o~c to 70°C
ac and de Electrlcal Cbara~tics
Refer to the DC329
timing parameters.
M
Chip
F.unctional
Specification
for
th
e
de
input
an
d
ou.tpu
t
parameters
and
ac .
1-240
Confidential ~nd Proprietary
·Features
· Contains a fraction processor and exponent and sign processor · Accelerates a subset of the VAX instructions
· Description
The DC330 V-11 processor flp~ting·pomt ,accelerator, contaiped in a 132~pin grid array {PGA)
package, receives opcodes ahd normalizeclfloating~peint operands from the I/E chip, and ex:ecµtes
the instructions fruiter than I{E chip ·microeode. It is optimized to accelerate a subset ohpe' VAX.'
instruction set. Figure 1 is a block diagram of the DC330 floating-point accelerator.
·
CLK CLKBAR CL.KSYNC
PH12
CLOCK LOGIC
FBOXN FBOXZ llD MTBMISS MIR TEST
DAL INTERFACE
MIBSVNC
Figure .1, DC330Floating-poim kceJerator Block Diagram
1-241
-·
· Pin and Signal Descriptions
DC330
The input and output signals and power and ground connections of the DC330 are shown in Figure 2 and are summarized in Table 1. Refer to the paragraphs that follow for a more detailed description of the signal functions.
Tuble 1 · DC330 Pin and Signal Summary
Pin
Signal
Input/output Description/Function
B3,A4,B6, DAL<31:00> B8,B9-Bll, C12,C4,C5, A6,A8,A3,A5, B7,C8-Cll, C13,B4,B5,A7, A9,All,A13, B13,C14
input/output
Data/address lines-Transfer data, status, and address information to and from the F chip.
}2
DAL BUSY input
DAL busy-Indicates that the DAL<31:0> lines
are controlled by the port controller.
Dl
DAL STALL input
DAL stall-Indicates that the data source cannot
respond to the data request in the same cycle.
N5,P4,M5, N4,M4,N3, M3,N2,K2, J1J3,Hl,L2, Ll,K3,Kl,
MIB<38:15>
input
Microinstruction bus-Transfers microinstnictions, synchronization control, and opcodes.
G3
MTBMISS input
Mini-TB miss-Indicates that the mini-TB in the
I{E chip has missed.
G2
IID
input
Input instruction-Indicates that the I{E chip is starting a new VAX instruction.
Fl.
ABORT
input
Abort-When asserted, the last instruction is
ignored.
El
TRISTATE input
Tristate-Disables all outputs of the F chip.
Gl
DCW
input
de low...,...Asserted for 70 ms after the power supply
voltage is within the specified value to initialize
theF chip.
F2
FBOXN
output
F box N code-Indicates a negative value or an
exception to the I/E chip at the completion of a
floating-point calculation.
C3
FBOXZ
output
Fbox Z code-Indicates a zero value to the I/E chip
at the completion of a floating-point calculation.
Confidetmal -.net Proprietary
-
Preliminary
ncno
Ym M6
P5
E14 Hl2,H13
Signal OPERVALID
DATA OUT
PH12 CLK
Input/output Description/Function
input
Operand valid-Indicates the successful assembly
of the operand.
output
Data out-Indicates that the F chip read result is pending.
output
Phase 12-Internal phase 12 output.
input
Clock-The MOS clock signal from the I/E chip.
Gl2,G13 CLKBAR
input
J14
CLKSYNC input
Kl4,L13, Ll4,M13, L12,M12
MIR 9-4
C6,D12,D13, Von E2,E3,F12Fl4,G14,M8, N8,P8
C7,D2,D3, Vss E12,E13,F3, H2,H3J12, J13,K12,K13, M9,N9,P9
outputs input input
Clockbar-A complement MOS CLK signal from
the I/E chip.
Clock synchroniza,tion-:-A synchronizing clock
signal that indica~ T, of the 200 ms microcycle.
Microcode test-Intet'1lal test bits MIR 9 through
MIR4.
Voltage-Power supply voltage.
Ground-Co.nunon ground reference.
Confidential and Proprietary
1-243
-
OC3JO
14 13 12 11 10 9 8 7 6 5 4 3 2
p 00000000000000
p
N 00000000000000
N
M 000000 00000000
M
L 000
0 0 0
l
K 000
J 0 0 .o
0 0 0
K
0 0 0
J
H 000 G 000
DC330
0 0 0
H
0 0 0
G
F 000
0 0 0
F
E 000
0 00
E
D 000
0 0 0
D
c 00000000000000
c
B 00000000000000
B
o..,. A 0 0 0 0 0 0 0 0 0 0 0 0 0
A
14 13 12 11 10 9 8 7 6 5 4 3 2
TOP VIEW
Figure 2 · DC330 Pin Assignments
PACKAGE IDENTIFICATION
Data/address Lines (DAL<31:00> )-These are bidirectional, three-state lines that are used for receiving operands, transmitting results, and for reading and writing the control/status register of the F chip. Addresses are received from the DAL lines for detecting unaligned memory references and to properly assemble the data.
DAL Busy (DAL BUSY)-This synchronization signal is driven by the port controller to indicate
that it is driving the DAL< 31:00 > lines. Any microcoded data that was transferred during the cycle is ignored and must be sent again. The DAL< 31:00 > lines are a high impedance when this
signal is asserted.
DAL Stall (DAL STALL)-This synchronization signal is driven by the V-11 chips to stall the microinstructions so that operations that require more than one cycle can be completed. It is used when the I/E chip reads a result of a calculation that is not completed.
Abort (ABORT)-When asserted, it indicates that the microword received during the last T150T200 phase is not valid and should not be executed.
de Low (DCW)-This signal is asserted for 70 ms after the 5-Vdc power is within the specified limits. It is used for initializing the control sequencers in the F chip.
F Box Negative (F BOX N)-This condition is transferred to the I/E chip to indicate a negative result upon completion of a floating-point calculation. It is also used to indicate exceptions.
F Box Zero (F BOX Z)-This condition is transferred to the I/E chip to indicate a zero result upon completion of a floating-point calculation.
1-244
Confidential and Proprietary
-
Initial Instruction ~e (DD)-This input indicates that the I/E chip is .sqirtihg ~·~ ..~
instruction and that a new opcode may be transferred to the F chip. If a calculation was in progress,
it must be aborted an<f the·n:ew instruction started.
·
· ·' · ·
< ~str1,1Wot1 Bqs (MIB 3$;1S > )-Theselin.<;s c9ntai11.~ microinstruction fl"Q.111 ·~.'.1'150 to
T200and provide sY~®~tion ~qptrol fro~..t~e·&50 tciT1<)0. .
.
Mini Translation Buffer Miss (MTB MISS)-this input is used for DAL line synchroniz.ation. I~ indicates that· the Mini~TB in the· I/E ·chip has missed data; and that· a page ta!;>le entry is l:iejng transferred from the BTB .on the DAL.lines. The .cm:tent miq:p4istructiof1 ~h~ld;b¢ stafi~.
Operation Valid (OPER VALID):--This is an input sequencer. test signal that indicates tbe
successful assembly of the operand. Control is gratited to the main sequencerdutj.ns d:lF:,~t, Q:ftER
VALID signal that is a function of the data type. ·
Dat.a Out (DATA OUT)-This is an output sequencer.test signal intlicating that the Fchip'resUlt is
ready and the read result is pending. An I/O sequence will take place as a result of this im:lication.
~t,ruction,,~.~~'J'BS'l'<;:o;> )"0'Tqe~~~'~es~,g'1tput~c~~.the,.Y~~.~£;the
inter~ microinsti;uction regist.¢r ;\M:!R<9:4?)..~. jlre ~~req.,!illd dri'?;by ~n~
devices and ~nal plll.lup .te$~tors of.1 k. ~,tequ~1 ;·.~in~rn~.~'" clla.nges·ev~
100 ns at PHU apdc}?lII.5.
Clock(CLK)-Thissignalis:the·MQS 0 clock.input~.the,·MLchip.andis.usedJO.·genet:a~.die
internaltiming.. The CLK input bas a~ of50 ,osand,is1high;dt:tting odd·phascs.
Clock Bar (Cl.K DAttJ..:...Tiiis signal is theoofuplemenl: ·6£ the MOS CLK sigmH!Om the M Chip arid is used·w generate the intetnal timing. Th¢ Cl.l·.BAR·input is the1Wnoweriappinginverse of
the CLK signal.
ClockSyncliroruze(ctKSYN~)-thissignalih'dictafuSt'ime~T~Ofthc!200nsmicrocycle; Ittisesat timeT175andfallSafT25. ' · ; ·
Pb8se 12 (PIJI2y.:;_This i:s the internal PHI2 sigrial·tftitt':is inverted andbttffered by an C>pen Soufce.
An external 1-k pulldown :resiiltCJr1s required.
· ·
1Httate ('MIS'fAtt)..-.Causes the DAL<31:00 >, FBOX Ni F BOX Z; and DA'LSTA'U.outputs to
beeome a high hrlpedance. · ·
' ··
, 1
\TQltage <Yoo)-The Pc>wer ~upply yq!~e t§ the llpg~~·fupu~ ~~-.·
'·
I _'. ; :. ·
' ~,,··
-' ' , '. ,, : «· · .·.·. "
)'_ .; .' ,
.·<. (.' , ":·'. · ··-~
,);~.- f · .,
~ (VsJ.-The pqwei;. supply ~turn and s,ignal»t'Ull!i tO ~ ~3, gfo,UJ;l,d input pini;r
~tina-PQint Jn~ Set
. . ..·. < ..,. .·
TheFchip is optiml.zed to.ac~ .~foll~~ ~~lil~of tW..VA.¥ ini;truttion~t. liefer to,:the
VAX· Sy11tem Ref'Crert,ce Manual. (S,.814) .foii··a. c1;1mp~ <,leso;ipt;ionqf thf.! o~tions. It .dqes not
execute the PDP-11 compatibility mode instruction set.
ADDF2,.AODP2,,J\DDG2, APDF3, ADQOJ, APDG}, ~UBFZi Stll}P~1 .S:PBG?, StJIJFl, SUBD3, SUBG3, MULF2,~um2, MULG2;·MT+l.LF3, ~f!JLD~;;¥UI.G3,,:i;;>:tVF.i~..QIV.02,D1V92, Dl~3. DIVD3; DIVG3, POLYF, J?O!XD,. POLYG, C¥Pl,1,. cM;ep, CMPO, CVTLF, QJTLD, CVTLG,
MULI2, MULL3, DIVL2,DIVL3, EMlJ.L, an,d EDIV.
It exetutes in a nonoptintlzedmanhet the £olldwing$ubset o£the VAX instuction set.
ADDF, AIJ:bb, ·ADDG, SUB'F, SUBb, SUBG, ·M'.ULF, MULD, MUtG, DIVF, DIVO,DIVG POLYF,
POI.YD, POLYG, CMPF, CMPD, CMPG, CVTI..F, CVTLD, CVTLG, EDIV, and EMUL. .
1111111
Preliminary
· Functitmal Operation
The F chip operates in the 200-ns cycle of the synchronous V-11 process0r system. It receives
microinstmctions from the V-U cont~l store that can initiate sequences in the F chip controlled by ·
the internal control store. The i.llternal opeJ:ations of the F chip cycle are performed at 100 ns.
Figure 1 shows the main logic elements described in the following paragraphs and includes the following:
· A.DAL and MIB interface
· A control store memory
· Afraction processor
· An exponent and sign processor
· Clock logic
DALinterface--The DAL interface corineets the F chip to the DAL< 31:00> lines. Together with the MIB interface, its conttollogic determines when data on the DAL is valid. It provides the
interfaces between the external DAL lines and the internal data paths, and it formats the data
internally in a standard floating-point form. It also detects unaligned data and latches and rotates the data to the proper format. It detects short literals and unpacks them into the standard floatingpoint formats. The DAL Interface also contains the F chip control and status register (CSR) that is used by the I/E chip microcode to determine the exceptional conditions that may occur.
MIB Interface-This interface connects the F chip control logic to the microinstruction bus (MIB)
and contains the currently executing external microinstruction, the current opcode and some of the
DA1 line synchronization bits. h contains logic that decodes the current external microinstruction
and opcode, sending control information to the DAL interface and control stpre.
Control Store-The control store is a 160·word by 36-bit ROM that provides the internal microinstruction for the F chip. It also contains the simple microsequencer.
Fraction Processor-The fraction proces59r contains the 67-bit. data path and control logic. It accelerates the execution of the VAX floating-point ADD, SUB, MUL, DIV, and POLY instructions on the Float, Double, and grand data types.It also accelerates the MULL and DIVLinstructions. The fraction data path contains a registerfile of two temporary and eight constant registers, a 67bit arithmetic logic unit (ALU), a 67-bit shifter, registers for storing the ALU information; shifter data and Q data, and a shift register able to shift up to 3 bits at a time. The operands are assembled
in the I/O register that forms the interface between the fraction data path and the DAL interface. The fraction control logic receives encoded control signals· from the control store (internal microinstruction) and MIB Interface (external microinstruction). It decodes these signals and
drives the data-path control lines.
Exponent and Sign P:rocessoio-The exponent processor is a 13-bit data path with control logic. It
allows calculations to be performed on exponents and signs of operands in parallel with operations
in the fraction processor. The data path consists of a four location dual-ported RAM with zero
detection on each output, an ALU, and latches for holding ALU data. A PLA is included to detect
certain cases .of exponent differences and a path for normalization data to get from the. fraction
data path to the exponent ALU. Literals can be transferred. to the exponent data path from a
dedicated. ROM.
. .
1-246
Confidential and Proprietary
-
DC330
Clock Logic-The dock logic receives the V-11 high-level, 50 ns cycle time clock signals and the TTL-compatible 200 ns cycle time phase signal. It generates docks that allow the DAL and MIB interfaces to synchronize to the 200 ns data transfers, and the internal data paths and control machines to cycle at 100 ns.
· Specifications
The mechanical, electrical, and environmental specifications for the DC330 are contained in the DC330 F Chip Hardware Specification. The test conditions for the parameters in these specifications, unless specified otherwise, are as follows:
· Ambient temperature (TA): 0°C to 70°C · Supply voltage (VDD): 5.0 V ±5% (maximum ripple 200 mV peak-to-peak) · Back-bias voltage (VBB): -3.0 V ± 15% (maximum ripple 200 mV peak-to-peak)
· Ground (Vs5): 0 V
Mechanical Configuration
ThemechanicaldimensionsformountingtheDC330132-pinPGApackageareshowninAppendixE.
Absolute Maxinnun Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to a device. Exposure to the absolute maximum rating conditions for extended periods may adversely affect the reliability of the device. · Power supply voltage (VDD): -5.0 V to 7.0 V · Power supply voltage (V55): -.3.0 V to-6.0 V · Pin voltages: -1.0 V to 10 V · Power dissipation (TA= 100°C) 3.5 W
· Power dissipation (TA= 0°C) 5.25 w
· Storage temperature range: -55°C to U5°C
Recommended Opemting Conditions
· Supplyvoltage(Vccl: 5.0V ±5% · Ambient temperature operating range (T11): 0°C to 70°C
ac and de Electrical Characteristics Refer t:O the DCJJO FChip Hardware Specification for the de input and output parameters and ac timing parameters.
____ Confidential and Proprietary
1-247
-- ___________________________________..,,_,..
·Features
· Wide-range functionallty iJi one package
and - High-performance P.tofessor ·.... ·
- Memory man~emeti.t protectfon
.'. 46 floating~point instructions
- Microdiagnostics
- Clock generation
- Console octal debugging technique (ODT)
- Direct melllOtY accC!>~ ar\?iP:ation
· Resideiit in~mofy ttiatlageirient ·
'- ·4-Mbyte addressing
..
·~ Direct addressmgo'f tasks up td 128 Kbytes
- Three levels of memory protection in
multiuser and multitask environments
· Comprehensive orthogonal itistruction set
- 140'ip.st~Ctiqns including floating-point
instructions · .· · ··· ··
· ·
- Coffipaubffify with PH~~llsystem software
· High-performance system-oriented
architecture - Pipeline ~chitecture
.:''.2-bit h~rialdatapath · ·· ~ $uppofts.~tfoimftllche fileriiory
·-' Supportsrh'lwtiprocessor o~tion · '-- Supp()rts ctipi'ocessor iritetf~
· Powerful vectored multilevel interrupt and trap structure with four external interrupts
· Description
The DCJll is an advanced 16-rutpUcroprocessor using v~ry large-scale integrated (VLSI) CMOS technology. The DCJll'.is a compl~e implementation of theJ~DP-11 proce~sor architecture and is compatible with PDP-'µ software and operating systems. Th~: DCJll consists of a data chip and
control chip that are contained irl a 60-pin dual-inline package (DIP). A blockdiagram of the DC]11
microprocessor is Shown in Figure 1.
- - -- r
·.- - - - - - ~. -..... '
I I PARiTV
.... I o;.;;; AiiiRT i.i:iitt~_ __,.--
- - .,
I
I
I- -
I I I L - ---
DATA CHIP
-;
CONTROL CHIP
- - - - - - - - __ '.- ,..,..._ ;,;.._ '"""""'
- - - - - - ...l
Figure 1 · DC]ll Microprocessor Block Diagram
1-249
~liminary
DCJU
Many system design requirements and options are included as integral parts of the chip. A highperformance processor using a four-level prefetch pipeline, resident memory management, floating-point arithmetic, console octal debugging technique (ODT), microdiagnostics, and dock generation provide efficient system functionality ina single package. The orthogonal instruction set allows fast and efficient programming to minimize development time and cost. The DCJll combines leadership system functionality with complete system software, a highly integrated
design, and low-power consumption to allow new classes of microprocessor applii::ations. A block diagram of theDCJ11 is shown in Figure 1.
· Signal and Pin Descriptions
The input and output signals and the power and ground connections for the DCJ 11 60-pin DIP are shown in Figure 2 and defined i.n Table 1. These signals are briefly described in the table and a more detailed description of the .signal functions is contained in the following paragraphs. The.system interface refers to the user's application of the DCJll and must be capable of providing or receiving these signals.
TEsfi
AI01 A102 Al03
PWR'F
FPE EVENT HALT IRQO IRQ 1 IAQ2 IRQ3 PARITY
GND
\Cc BSO BS 1
M'AP
ABORT DAL21
DAL20 DAL19 OAL18 DAL17 OAL16 DMR MISS
PRoC
NOT USED
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
DCJ11
16
46
45
17
44
18
43
19
42
20
41
21
40
22
39
23
38
24
37
25
36
26
35
27
34
28
33
29
32
30
31
TOP VIEW
Figure 2 ·DC/11 Pin Assignments
DAL06 DALO? DAL08 DALOO DAL09 DAI. 10 DAL 11 DAL12 DAL13 DAL14 DAL 15 DAL01 DAL02 DAL03
\f::c GND DAL04 DAL05 DV BOFCf[
ALE S:'fRB SCTL XTALO XTALI
CLK
CLK2 INIT
CoNr
TEST2
1-250
Confidential and Proprietary
···
··~
P'm
21-26, 43-44., 47"60 17-18
19 2-5
40 41
Signal
DAL<'.21:00$. ~t/olitpiit1 .
Data/address lines-Time-multiplexed data and ~$S.bl,1S.
BS< 1:0> output1
MAf5
output'
AI0<3:0> output'
ALE
BUFCTt
output1 output1
Ba:nk·select-These time-multiplexed signals define
the'type of physical address on the data/address bus,
and a ,il;'l~~~~te ifeither ciichi: memory~~s or a force
miss occurs.
Map:..:_:Thls time-mulitipl~ signal indicates if the . 1/0 ~p fs enabled <>r ifa DMAgtant ocC\lrs.
Ap~sfoput/output-These signals indicate the type
of· transac~ion ·currently being execu-ted.·. i.e.; read,
·· 'write/or·fACK.
., ··
Addreil~ U.tch enable-Lat-ches addresses, AIO codes, i mapetlll~l~ ~ignals~ and tJ:i~BS C()Otrolsignals.
BUffet 'ci:mtrol-InQicates.i:he ~cti¢,:i'6£ data on .the
· DAL bus. The line is active(low) when the DCJ llis not driVi~g i;o: i:he DAL bus.
38 SCTL
39 STRB
output'
.·' ~ '
O';ttput1
Stretc;~ Cff:>Otrol~Ideritifi~s ·the extended,poriiori of stretChedcycles. The edgescanbe used. to strobe data.
29 PRDC
output·
Predecode strobe-Indicates when the prefcetchbu,tfer is being decoded as the next macroinstructi<;)n,.
20 ABORT
input/output1
Abort-Indicates that an abort condition exists, i.e., a memory management or address error, bus timeout, nonexistent memory, or parity error.
28 MISS
input'
Miss-Reports the hit or miss status of the current cache memory entry lookup.
42
DV
input'
Data valid-Set to latch data into the DCJll.
32 CONT
input1
Continue-Used to terminate all extended cycles.
27
DMR
input1
10-13 IRQ<3:0> input1
Direct memory access request-Used to force a current cycle to be extended.
Interrupt Request < 3:0 >-Four maskable interrupt
request lines.
9
HACT
input1
Halt-A low-priority nonmaskable interrupt that forces the system into console mode.
8
EVENT
input'
Event-A maskable interrupt that forces a trap through vector location 100.
1·251
__ __ . ·-· -··-------·--------·-·-------------"""""'""""""'·,_,._._..........,.,,.,........,_......,....".'""'""''"'.·.,..,,,.._...,.,..
Pin Signal 6
7
input' input1
14 PXRITY'
35
CLK
34
CLK2
33
INIT
36
XTALI
37
XTALO
16,46. Vee
15,45 GND
1
TESTP
31
TEST22
'TTL levels 2MOS levels
input' output2
output2
input1
input output input input input input
·. Miminary
:Powerfiill2A high~priority nonmaskable.interrupt that forces a trap through vectodocation24:.
Floating·point enable-Reserved for a future FPA
coprocessor implementation. A high-priority notlmaskable interupt that. forces a trap through· vector location 244.
Used'to report parity errors.
·Clock-An output for intra-hybrid and diagnostic use only.
Clock 2-An output with identical frequency as CLK.
Can be used as system dock.
·
Initialize---Jnitializes or resets the system by forcing it through the powerup procedure.
_,.,..~..--~~~~~~~~~
Crystal input-External crystal input
Crystal output.:_External crystal output
Voltage....-Power supply voltage G1tmnd:._:_Ground reference.
Disables all outputs.
Disables the clock outputs. ·Permits external logic to drive the DC] 11 clock circuifry through CLK output.
. 1-252
Confidential and Proprietary
-
. 'Mliminary
Figure 3 shows the input and output signals grouped according to signal functi.oo.:
· INTERRUPTS
J DATA CONTRC;)L.
BUS ERROR OMA CONTROL CACHE CONTROL
INITIALIZE
CLOCK INPUT
DCJ11
i----~100
1----A.163
---aso
--- est
-----·A-CBEOfcT[
,. _. . ._. _ - -_··s.SnCrTeL
---M5C
---MAP
1 DATNADDRESS
l. ADDRESS 110
BANK SELECT
,figzt.re 3 · QC]p Signal F,u1!£ff,Ons .
'~. - -·-"
< ,,_,._ ,,. · - - · ·- -. ->1·.C- ~ -, --~:·-,,~
Data and Address Bus
Data Bct·~·tms (llAL<!hoO>;;.;.,The·dm and addi\::ss ··bUS consists·of 22 time·inultiplexed
datii'md address lirie~. The baskbuS d>mist!s ofDAL<15:00~ arid is bidirectiofull. The eitended
buS ootiSis~r bf' DAL< 21~16> .ana··is ···used·'for mittntts' ·only, ·Dt:lririg the first half of. lea&
transaction, the DCJll provides either a physical address, the acknowledged in~ level Or a
general purpose code. The physical address can use all 22 bits of the bus. The acknowledged
interrupt level uses DAL< 03:00> and the general purpose code uses DAL< 07:00 >. DuriJl8 the
second haH of the transaction, the DCJll . transmits. or receives data .ori;'the basic 1btis
(DAL< 15:00> ); The extended bUs lirl~ m&~·21t!6> J\tte' driveri' widi~t mfortruttioo when
the BtffiCTL Sigmll is asserted. Thejdafabeibg.ttafumittedor ~ived d~ on the type of bus
tram1actioq being perfo~ arid is H~ilie.:hmder bUs opetatioru.
. · ,. .
1-2)3
-
·'DCJU
Addiess Input/OutputLines Address input/output (AIO < 3:0 >)-The address input/output signals are latched at the start of
any bus transaction and are coded to indicate the type of transaction being performed. Table 2 lists the bus transactions selected by the AIO lines.
'Iable 2 · DCJtlBus 'liansaction SeleCdon
AIOLine1
3
2
1
0
Transaction
1
1
1
1
Non-1/0 operation (NOP)2
1
1
1
0
General purpose read
1
1
0
1
Interrupt acknowledge (read vector)
1
1
0
0
Instruction stream request read
1
0
1
1
Read-modify-write, no bus lock
1
0
1
0
Read-modify-write,: bus lock
1
0
0
i
Data stream read
1
0
0
0
0
1
1
x
0
1
0
x
0
0
1
x
0
0
0
x
Instruction stream demand read Reserved
General purpose word write
Bus byte write
Bus word write
1X=logic 1 orO 2A NOP transaction is an internal operation that does not require a bus transfer.
A bus transaction uses the DAL bus to access rp.emory, I/O devi~s, or addressable regi,s,ters. A
gel\eral purpose transaction is used to. access interface devices th~t are not directly addressable by the DAL bus. lnt¢rrupt acknowledge (JACK) transactions are in response to the DCJll granting an interrupt request.
B..hk Select Lines
Bank ~~t (BS< 1:0 >)-The bank select signals (BS 1 and.BSQ) are timecmultiplexed. During the first half of a bus tra~action, they are used to.qefine the type of aqdress that is .present on the
DAL< 21:00 > bus. During the second half of the ,read and write transa~tions, the~e liµes define the cache memory status. A cache memory bypass condition exists if the BSf signal is asserted high, and a force cache miss exists if the BSO signal is asserted high. Table 3 lists the address space
selected by the bank select signals.
Confidential and :Proprietary
-
BS~
1
0
0
0
0
l
l
0
1
l
Table 3 · DCJU Bank Select Line Assignments
Memory External !/O Internal register
DCJU
Table 4 lists the addresses assigned to the system registers and interr:ial reg,isters of the DCJU
microprocessor. Physical addresseslessthan 1776()000are inempry addresses: AddreSsesin the I/O · page (17760000-17771777) that ~o not ac~s a DCJll resister .are exrernal I/O addresses.
Addresses in the I/O page that access internal registeis; ·exeeJ?t for ·CCR, ·nre internal register addresses. Addresses in the range of 17777740 to 17777l'50 are classified as system registers,
Table 4.· DCJll Regisiet J\,~ss Space_A~ents
Address
Register
17 777 776 17 777 772 17 777 766 17 777752 17 777 740-17 777 750
Processodtattis word (PSW) Program interfupt't'equest (PIRQ)··· · CPU error Hit/Miss register
System register space
17 777 746 17 777 707-17 777 700
17 777 676-17 777 660
17777 656-17 777 640 17 777 636-17 777 620
Cache control CPU general registers User data PAR,, Reg. o~7 Usednstntcl:ion.PAR, Reg. 0-7
User data PDR, Reg. o:7
17 777 616-17 777 600 17 777 576 17 777 574 17 777 572 17 777 516
17 772 376-:-17 772 360 17 772 356-17 772 340 17 772 336-17 772 320 17772 316-17 772300 17 772276-17 772260
17 772 256-17 772 240 17 772 236-17 772220
User instI'll~tion PDR, Reg.. o-i
MM Status Register 2 (Mb4R2) MM StatusRe~i~ter l (Mi\IB1)
MM St:atl1s Register 0 (MMRO)
MM Status Register 3 (MMR3) · .
,·'
,·'
''
',·',
.. \_,;
Kernel data PAR, Reg. 0-7 Kernel instruction PAR, Reg. 0-7 Kernel data PDR, Reg. 0- 7 Kernel instruction PDR, Reg. 0-7 Supervisor data pAR,,. Reg. 0-7
Supervisor instrtldion PAR, Rei 0-7
Supervisor instruction PDR, Reg. 0-7
All other addresses in I/O Page 17 760 000-17 777 777 0-17 757 777 physical memory space memory
Register Ciassi6cation
Internal· Internal Internal lnterooL. System
System lriternal
Intetnal Interrial
Internal
Internal Internal Internal .Internal Internal
Internal Internal Internal lntc!rnal Internal
Internal Internal
External I/O
Confi~t;i.al and Proprietary
1-255
·1'.X:Jft.
Data Control Lines
Buffer control (""B""'U""FC"""Ti"""'"')-The BUFCTL lirie is asserted when i;h,e DAL< 15:00 > bus is not being
driven by the DC]ll when receiving data during read transactions and during the stretched portion
of any nonwrite transaction. The BUFCTL signal is negated when the DCJll is writing an address ordatatotheDAL<15:00> bus.
Address latch enable (ALE)-The ALE line is asserted atthe start ofa transaction and is used to latch the address, I/O bank, I/O map and AIO code infor!llation. During the second half of the transaction, the signalis negated and can be used to latch the cache memory data.
Strobe (STRB)-The STRB is negated at the end of every tfarisaction and asserted by the end of the second dock period of the next transaction. The STRB signal identifies the end of a transaction and
can be used for external bus control. Stretch control (SCTL)-Th~ SCTL line is asserted for the stret~hed portiqn of a bus transaction. During ~rite transactions, the leading or trailing edges of the SCTL signal may be used to latch
data. During read transactions, the trailing edge of SCTL max be used to latch <iata..
Precode strobe (PRDC)..,,-The PROC line is asserted for the first· two clock periods of. any transaction and indicates to the system that the DCJll is decoding the next macroinstruction.
I/O map enable (MAP)-The MAP output is time multiplexed. If it is asserted during the first half of a bus transaction, theI/O map is enabled and the MMR3 bit 5 is set to 1. During the second half of the bus transaction, the MAP signal acknowledges that the DMR signal was recognized and will mwer be asserted during write transactions. Data valid (DV)-The DV input is received from the system interface when the DC]ll 1;anlatch
valid data from the DAL bus. Thisinput is s~mpled.when the BUFCTL signal is asserted during nonwrite stretched traii.sactions.
Continue (CONT),:_The CONT input is received from the system interface to inform the DCJll that it is finished using the DAL bus and ends a· stretched transaction.
to Bus Error Lines
Parity etft?r (=PA""'R=1=T=Y)-Tbe PARITY input is used by the system interface to report parity errors
is the DCJli. A parity interrupt is generated when PARITY is asserted without ABORT being
asserted. A parity abort is generated when PARITY as;;erted with ABORT being asserted. Assertion of the ABORT signal is used to differentiate between a parity interrupt and a parity abort. An abort immediately traps without completing the current instruction. Memory cycle abort (ABORT)-If ABORf input is qssert~d during the first dock period, it indicates that the memory cycle should not be initiated. During a bus transaction, if an abort condition (register, timeout, parity errors, etc.) is detected by the system interface, the system interface asserts the ABORT signal with an open-collector device during the stretched part of the transaction. ·
Control Lines DMA request (DMR)-The DMR line is driven by the system interface tb gain control over the DAL< 15:00> bus. The DMR line status is sampled by the DCJllat the rising edge of TO and the
request is acknowledged by the DCJll by asserting tbe MAf5· 1ines. The I5MR signal is not
acknowledged during write transactions. Asserting DMR ensures that the next transaction will be stretched. All write transactions are stretched. ·
1-256
Confidential and Proprietary
...
Cache miss (MISS)-The MISS input is received from the system interface to indicate the status of
the current tai:!fle memory lookup entry. The DCJll samples the status of the ~ISS line at tb.e rising
edge of T3 during a read transaction. If the MISS signal is asserted to indicate the entry was not located in cache memory, the current read transaction will be stretched.
Initialize (INIT)-The INIT input is driven by the system interface to initialize the DCJ 11 by forcing it to go through a powerup routine.
Interrupt Lines
..... .
Interrupt request (IRQ < 3:0> )-IRQ < J:O > are foutmaskable in~rrupt request lines that allow
the system interface to interrupt DCJll operations. ~four j9puts represent four interrupt levels
and are synchronized and latched b)' theDCJit· '
·
The interrupt is acknowledged only if the current PSW bits 07:05 are set to a lower level than
requested by the system interface. Tu,ble 5 lists the intenuptlevel a~ents.
!nput LeVel PS\Vbits
o1 06 OS
IRQ3 7
1
1
1
IRQ2 6
1
1
0
IRQ.l 5
1
IRQO ,4
1
Powerfail (PWRF)-The PWRF input is a nonmaskable interrupt from the system interface. The
DCJll traps to vector address 24 for the powerfail routine.
Floa~"}pqint ~on (FfE)-The FPE. input is a nontl(lll$kab1e interrupt from .the systt!tn
interfa,ce that ca,uses d1e DCJ11 to .trap j;() ~ectoi: address 244Jor tbe servi6e rQUt:in~'
.
,.".. -
-
-
'
·' --<
'-. ''·''--' ··';
1 '
-· '
,, ,·.
·
L'
." >.'
Bus even~ (£VEN1~The. EVENT iuput. is ,a·hui> i11terrupt ·fi:om the systei;n interfaee a,nd .the
DC]ll traps to vector address 100 for the ~ervit:e 1'9:Utine.
Halt (HALT)-The HALT input is the lowest nonmaskable interrupt from the system interface and
it foi:ces the DC}ll into the console mode.
Confidential and Proprietary
1-257
DCJU
Clock Lines
.
.
.
Crystal input (XTAU and XTALO)-The XTALl anq XTALO inputs provide connections for an
externat crystal as shownil'l Figure 4.
·
68pF I----.---~-- XTALI
CRYSTAL c::::J
1 M
i-----~~-XTALO
68pF
Figure 4 · DC]ll Typical Crystal Connections
Clock (CLK)-The CLK signal is used for testing purposes and should not be used. Clock 2 (CLK2)-The CLK2 signal is the same as the CLK and can be used by the system interface
as the system dock. The frequency of this signal is the same as the crystal frequency.
Miscellaneous Lines Test 1 (TESTl)-The TEST1 input is asserted by the systeminterface and disables all the DCJll output signals. The input is pulled up internally. Test 2 (TEST2)-The TEST2 input is asserted by the system interface to disable the CLK and CLK2 outputs and to allow an external clock to drive the DC]ll. The input is pulled up internally.
Power Supply <Vccl-Vcc input provides the DCJll with 5-Vdc operating power.
Ground (GND)-The GND input connects the DC]ll to the system interface ground reference.
· Architecture Summary
The DCJll implements the PDP-11 processor architecture to achieve processing power equivalent to high-performance minicomputers. The primary internal data path is 32 bits to optimize performance of floating-point arithmetic. The combination of a four-level instruction prefetch pipeline and an efficient internal architecture enables the DCJ11 to execute many instructions in four clock periods. THe DCJU incorporates many system features not available with alternative 16-bit mie'roproces' sors. It includes a powerful and flexible set of control signals between the processor and the system interface allowing high-performance and high-reliability systems to be built. The processor provides support for cache memory, parity memory, multiprocessing, and coprocessing implementations. Reliability has been built into the processor. The CMOS technology provides reliability and includes error reporting registers and a firmware resident console monitor handler. The key features of the DC]ll's register set memory management and interrupt structure are described in the following paragraphs. More comprehensive descriptions are provided by the PDP-11 System Handbooks for the PDP-11/44 or /70. Figure 5 is a programming model of the DCJll and shows the registers and accumulators available to the user for programming and maintenance purposes.
Confidential and Proprietary
-
GENERAL PURPOSE REGISTERS
fl()
Ro·
A1
111 ·
.82 '""' ~
82°
R3
R3"
84
R4" ,'
fis
RS*
KSP ,, f
SPECIAL REGISTERS
MRQ
I FPS
SSP USP
I I CPU ERAOR
I I CACHE CTRL
FEC
L1. HIT/MISS "' ,,-; "
FEA'
FLOATING·POINT ACCUMULATORS (64·BIT)
A.CO
..:_
-'-'-
AC1
AC2
AC3
AC~. ' ...
'.:.·::'
..;::,.
_L. ..::. .:
ACS
'
,,,
,,
as General Purpose Regist:ers
Two groups of 16-bit general purpose registers are used' ,a~~ulators, index reference, autoincrement, autodecrement, and stack pointers for temponll)" ~t~rage of data. Registers RO through R5are selected when bit 11 of the processor status longword (PSW) is set to zero. Regi!iters RO through R5 group is selected when bit 11 i& set .to 0ne. Theseindependentregister banks can be used by software to minimize context switch delay. .
Stack Pointers
. .
. .. . ·. ..· , · .· ..··... . .
r
The DCJll operates in three processor modes-kernel, supeivisor,. and user. EaCh processor mode
has a stack pointer that is designated R6. The stack is usedto store the processor status and CU1'1'Cllt
prognun oou.nter ~ .when,~~t!i, ~p11, .or ~~t~\ ~ans .qccur. ·nie ~t. meld~ is
determined by bits 15:14 of the PSW. The current..~~ $ s th~ srack ~~ to~ ~ed for all
instructions except for MOVPM instructions that u'Se the previous mode, bits'i3:U of the PSW, to
select the stack pointer. The DCJll can access only the selected stack pointer.
Program Counter
The program counter (PC) contains the 16-bit address of the next instruction robe executed. It is
designated R7 and controls the sequencing of instructions. The PC is directly addressablehy singleand double-operand instructions and is a general purpose re~ister th~t is normally not used as an
accumulator.
·
·
·
Processor Status Register
The processor status register (PSR} contains the processor status. woix:I (P&W) that contains
information related to the current and previous processor mode. It includes :the priority levels,
condition codes, register sets,·and trap information: The fotti111t of the PSR is shown in Figure 6
and the functions of the register bits are described in Table 6.
1-259
··
.·.·~u··
"U~j"·.· ..
l ,~~~,,: ~lous,
PRIORITY
v c
f
PRIORITY LEVEL
TRAP 1BIT ·
f p
CONDITION CODES
GENERAL PURPOSE SUSPENDED REGISTER GROUP INFORMATION
Figure 6 · DC]ll Processor Status Register Format
Table 6 · DCJU .Processor Status Word Descriptions
Bits* Description
15,14
Current mode-Indicates the current operating mode as follows.
Bit 15 Bit 14 Mode
0
0
Kernel
0
1
Supervisor
1
0
Illegal
1
1
User
lJ:U Previous mode-Indicates the previous operating mode and is coded the same as bits 15:14.
11
GP Register-Selects the group of general purpose registers being used. When the bit is
set, the RO'-R5' group is selected and when cleared, the RO-R5 group is selected.
10:08 Not used.
07:0.5 Priority level-Indicates the current priority levelof the microprocessor as follows:
. Bit 07 Bit 06 Bit 05 Priority level
1
1
1
7
1
0
0
6
1
0
1
5
1
0
0
4 .
0
1
1
3
0
1
0
2
0
0
1
I
0
0
0
0
04
Trap-The trap bit is inactive when cleared. When set, the processor traps to location 14
at the end of the current instruction, It is used for debugging programs and setting
breakpoints.
i-260
Confidential and Proprietary
Bits* 03:00
Description
Condition codes-Theses bits contain information related to the~ et. the1ast GPU
arithmetical or logical operation as follows:
Bit 03 nega.tive(N)-Set whe.n the previous operation result was negative.
Bit02 zefu (Z)_.:.S~t when the previous ~l>efut:ion resulted as ~~· . . .
Bit 01 Overflow (V)--Set whenthe p~iousoperation resul~din an arithmetic overflow..
00 Bit Carry (C).:_Set when the previous. ~tion ~use9 .a c@,tt'.Y. oµt of its most
signi.ficant bit.
· ·· ·
·
·
*All bits can be read·or written except where indicated.
CPU Enw Register .·.
. .. . . .. ..
The CPU error register is a read-only register used by .th(!J>CJll to tepPrt: .<.:PU.errors detected by
the system software. Six separate error conditions c - the micropro(:eSsor ·to trap. through
are location 4. The format of CPU error register is shown in Figure 7 and the functions of the bits
described in Table 7. .
··
15 0
IL.LEGAL HP,LT _ _...._.....,...,,,,__,.._......,...,........_..,.._.., ADDRESS E R R O R - - - - - - - - . . . , . . . - - - - " NON-EXISTENT M E M O R Y - - - - - - - - - - - . . . . . _ . 1/0 BUS T I M E O U T - - - - - - - - - - - - - - - - - - ' YELLOW STACK V I O L A T I O N - - - - - - - - - - - - - - RED STACK V I O L A T I O N - - - - - - - - - - - - - - - - - - - -
l-261
-
Preliminary
"'DCJll
Table 7 · DCJll CPU Error Register Descriptions
Bit* Description
15:08 07
Not used
is Illegal Halt-Set when the execution of a HAil' instructin attempted in user or
supervisor mode.
06
Address Error-Set when a word access to an odd byte address or an instruction fetch
is from an internal register attempted.
05
Nonexistent Memory-Set when a reference to main memory times out.
04
IJO Bus Timeout-Set when a reference to the I/O page times out.
03
Yellow Stack Violation-Set on a yellow zone stack overflow trap. (Kernel mode stack
reference less than 400 octal.)
02
Red Stack Violation- Set on a red stack trap-a kernel stack push abort violation during
an interrupt, abort, or trap sequence.
01:00 Not used
*All bits are read-only.
Program Intem..pt Requ4,!St Register The program interrupt request (PIRQ) register provides seven levels of software, interrupts. An interrupt request is queued by setting one of the bits 15:09 that correspond tu interrupt priority levels 7 through 1. Bits 07:05 and 03:01 are set to the encoded value of the highest pending request. When an interrupt is acknowledged, the DCJll program transfers to address 240 for a service routine. The service routine must clear the interrupt request. The format of PIRQ register is shown in Figure 8 and the functions of the register bits are described in Table 8.
11 sI sl I I 15 14 13 12 11 10 09 08 01
IP1A PIA PIA PIA 41PIA3IP1R 2! PIA 1 0
06 05 04 03
I 0
02 01
00
~EOUEST 1 LEVELS:=J
l I
PRIORITY ENCODED VALUE OF BITS9-15
Figure 8 · DC] 11 Program Interrupt Request Register Format
Confidential and Proprietary
-
00}11
Bits* Function
15:09
Request levels-Indicates the interrupt leveLrequested as follows:
bit 15 (Level 7)--~t an intettupt priority pf levet7.
bit 14 <1-evd 6)-Requestan interruptpriori7o£ ~16.
bit 13 <LeVd. 5)--~est an interropt priority of ~l '.
bit 12 (Level 4)-Request an interrupt priority of level 4.
bit 11 (LeVel},h..Reqµ~{ an interrupt P,rlority of l~ ~(.
bit 10 (l..evel2)-Request an interrupt priority of 1~4. bit 09 (Level 1)...,.,..Request an interruptpriority oflevelt
07:05 Encoded Value- Read-only bits 07:05 tep1'CSCnt.encoded value ofhighesi priority level
set in bits 15:09.
··
03:01 Encoded Value Read-only bits 03:01 represent the encoded value of the highest priority
level set in bits 15:09. Same as bits 07:05.
*All bits can be read or written except where indicated.
Cache Control Register
The cache control register (CCR) controls the opetatio11of the cache subsystem.·Throughthe CCR, cache bypass and force miss signals can be controlled by software. The powerup microcode also sets
the flush cache bit 8 to enable the orderly start of a cached machine. The format of the CCR is
shown in Figure 9 and the functions of the bits are described in Table 9.
15
11
0 0
0 0
0
,
._
J UNINTERPRETED
!READ AS ZEROES)
UNINTERPRETED I READ/WRITE)
UNCONOITIONAL CACHE BYPASS
-"-
JI.
.·
UNINTERPRETED (READ AS ZERO)·
UNINTERPRETED I READ/WRITE)
FORCE CACHE MlSS
UNINTERPRETED I READ/WRITE)
Figure 9 · DC]11 Cache Control Register Format
1·263
-
Bits* Function
15 :11 RAZ {read as zero and uninterpreted}
09
Bypass Cache-Asserts BSl during the second half ·of read and write transactions.
08
Flush Cache-Causes the cache subsystem to fltJsh cache. Always read as a zero.
07:04 Uninterpreted.
03:02 Force miss-When either of these bits are set, BSO is asserted during the second half of
read and write transactions. ·
·
01:00 Uninterpreted.
*All bits can be read or written except where indicated.
Hit/Miss Register The hit/miss register (HMR) records the status of the miss input from the system interface. The HMR is a shift register that records a hit as a one and a miss as a zero for the most recent memory reads. A hit indicates that the data is located in the cache memory and a miss indicates that the data is located in the main memory. Bit 0 represents the most recent memory read and is shifted to the left on successive memory reads. The format of the HMRis shown in Figure 10.
15 14 13 1:.' 11 10 09 00 07 06 05
I I I I l I I I I 0
0
0
0
0
0
0
0
0
0
00 fLOW
Figure10· D(.:]11 Hit/Miss Regiiter Format
· Floating-point Register Set
The floating-point registers are used to store floating-point data and to control and report floating-
point information.
·
Floating-point Accumulator Six 64-bit accumulators (ACO through AC5) are used to store and manipulate 32-bit and 64-bit floating-point data types.
Confidential and Proprietary
-
Floating-point Status Register The floating-point status (FPS) register provides mode and interrupt control for the floaring"point
unit and conditions ,resulting from the execution of the previous instruction. ".{'he FPS regfater contains an. error flag and· ~our. condition codes-'-'i'Catcy,1.overflow, zero, and nt!@ative,..-that are equivalent to the CPU condition codes. The floating·poir~t prooessor (FPP) recognizesthe following
Hoating:-point exceptions.
· Detection oftheptesence of the undefined vrffiinble in ineri\t.ny
· Floating .overflow
· FlOa.ting underflow
· FailureoHloating to integer conversion
PY · Attempt to pivfde ~rp
· Illegal floating opcode
the For the first four. exceptions, .the bits in. FPS. fegist~ are available tp ef)able or disable
interrupts.An interrupt caused bjr the la~t t:Wb exceptiops,canfje dis~l>,led.onlyhysetting a bit that
disables.the inteqilpts of all. sevenofthe exrep~ons. the'erl:C!r'flag atlcf ~onditioil codes are set by
the FPP as Pllft of t~e output ofa. flw~ting"poi~~· instrudioll. Th,e pi.ode and interru~t control bits
may be set by usitlg the LDFS ~truc~Qh. ~i~ 11 shoWs t}ie format of the FPS register, and the
functions of the register bits are described fn Tal::ile 10. .· .
.
15
00
FER
FC
RESERVED
RESERVED
Figure 11 · DCJ11 Fkiating-point Statits Register Format
Bit Descriptioti
15
FER·(Floating error)-This bit is set during a floaiing-f,(,intiriStrilction\vhen a division
This by zero occurs, an illegal opcode is spe'Cifi~; or l:lny oHhe remainin.g errors are detected
when the corresponding error interrupt is enabled. hit is,.set.l)y the Fl9ating-point
Processor (FPP) and deared<mly an LDFPS instructi9fl. Th~ bit . status. is valid. only if the
mostrecent floating-point instruction produced a floating-point exception. This action is
independent of the FID bit status.
14
FID (Floating interrupt disable)-Wll,en set, al! flollting-point in.terrupts are disal::iled;
The FID bit i~ primarily a maintenance feature and should normally be clear to assure that
the storage of -0 by an FPP is always accompanied by an interrupt. This bit is assumed to
clearfor aJ1 descriptionsthat followthat involying overflow, underflow, and occµr:rence of
-0, and integer conversi9n errors.
f · . ·<. '
:;i'L · · _ '. .·
Confidential and ·Proprietary
-
Preliminary
OOJU
Bit 13:12 11
10
09
08
07 06
0.5 04 03 02 01
00
Description
Not used-Reserved.
FIUV (Floating interrupt on undefined variahle)-An interrupt occurs when this bit is set
and a -Ois obtained from memory as an operand of an ADD, SUB, MUL, DIV, CMP, MOD,
NEG, ABS, TST, or any WAD instruction. The interrupt occurs before execution except for a NEG, ABS, and TST instructions when it occurs after execut.ion. When FIUV is reset, -0 can be loaded and used in any PPP operation. The interrupt is not activated by the presence of -0 in any ac operand of an arithmetic instruction and trap on -0 does not occur in mode 0. The FPP will not store a result of -0 without a simultaneous interrupt.
FIU (Floating interrupt on underflow)-When set, a floating underflow will cause an interrupt. The fractional part of the result of the operation causing the interrupt will be correct. The biased exponent will be too large by 400 (octal) except for the special case of 0, which is correct. If the Fill bit is reset and if underflow occurs, no interrupt occurs artd
the result is set to exact 0.
FIV (Floating interrupt on overflow)-When set, a floating overflow will cause an interrupt; The fractional part of the result of the operation causing the overflow will be correct. The biased exponent will be smaller by a value of 400 (octal). No interrupt will
occur if the FIV is reset and overflow occurs. The PPP returns to exact 0. Special cases of an overflo"w condition are defined in the detailed descriptions of the MOD and LDEXP
instructions.
FIC (Floating interrupt on integer conversion)-When set and the conversion to an
integer instruction fails, an interrupt will occur. The destination is set to 0, and all other registers are not affected. If this bit is reset, the result of the operation will be the same as previously described but an interrupt will not occur. The conversion instruction fails if it generates an integer that is longer than the short or long integer word specified by the FL
bit.
FD (Floating double precision mode)-This bit determines the precision that is used for floating-point calculations. When set, double-precision is assumed; when reset, singleprecision is used.
FL (Floating long integer mode)-This bit is used in the conversion between integer and floating-point format. When set, the integer format assumed is double-precision two's complement (i;e., 32 bits). When reset, the integer format is assumed to be singleprecision two's complement (i.e., 16 bits).
FT (Floating chop mode)-When set, the result of any arithmetic operation is chopped (or truncated). When cleared, the result is rounded.
Not used-reserved.
FN (Floating negative)-this bit set when the result of the last floating-point operation
wasO.
·
FZ (Floating zero)-This pit is set if the result of the last floating-point operation was 0.
FZ (Floating overflow)-This bitis set if the last floating-pointing operation resulted in
an exponent.
carry FC (Floating ·carry)-This bit is set if the last operation resulted fo. a
of the most
significant bit. This can occur only in a floating or double-to-integer conversion.
1-266
Confidential and Proprietary
OFlnoeatiinngt-p~opinttvEexccteopdt~io~nsRigengeisdtetro
all
. .·. .. ... .
floating-point
. . . ..
excepti6n:s.
. .
The
.
six
~ssible
eri:ors
are
coded
in the 4-bithting exception<!Ode (FEC) register asf0llaws~
· 2 Floating-opcode error
· 4 Floating-divide by ·zero
· 6 Floating~ or double-to-integer conversion error
· 8 Floating-overflow
· 10 Floating~t1nderflow
· 12 Floating-undefined variable
The address of the instruction producing the exception is stored in the Floating Exception Address (FEA) register. The FEC and FEA registers are updated when one of the following occurs: · Divide by zero
· ffiegal opcode
If one of the five exceptions.~s w,ith. the~r~nding ,interrupt ,disabled, the FEC and FEA are not updated. Inhibition of .it;tterruptii..by ?,he. F.Jgatihg fatertup( DisableJFID) bit does not
w1': inhibit updating of the FEC and FEA if an -~on e><;cµrs. Th~Fl~:<:; ~n4 FI!:/\' are not updated if
no exception occurs. Therefore, the store statu!i (S':['ST) it)str~ction return cl.ltl"ent information only if the most recent floating-point instruetion.prQ4uc~ an exception..No instructions are provided for storage into the FEC and FJ:tA ieg!Siers. '
· Memory Management
The DCJll ·implements the complete PDP-11 memory management and protection architecture
with its extensions for extended direct addressing. This architecture provides a fully supported
protection model for the design of_ reliable maj_tiuser ()t multitasking systems. Address relocation
and protection logic is·iP~i;ed ~~thec!?i~~~e~~;so ~t]J&(Ormance penalty is not
incurred by using the memory management unit-(MMU).
The MMU provides .three sePllNte. address fPaces---kern.eI, s~penrisor, a~ ~~'modes-with
ana different.privilegesand independenisetsdf 16·hitmaPiJi~gand'.'p~1negister$;This structure
protects the operating s)i'stem frorirless priv'iiegeif progritrtl$ tni~zes system'O\Terhead from
mswoidtceh. ing.
The
execution
·o.·f·
some
o·· f
the
instructions
isMfeferit~ndibg · ··· ·
on
thecirre
n
t
·progr·a· m
1-267
-
Instruction
HALT WAIT, RESET, SPL Rf!, RTT, MPI'S
Stack references
KernelMode
Executes as specified
Executes as specified
Alter PSR priority level bits 07:05 freely Checked for overflow
· Supervisor/UserMC>de ·
Traps through 4
Execute as a NOP instruction Cannot alter PSR priority le'1el bits 07:05 Not chedwd for oVerfl~
INSTRUCTION SPACE
PDR
PAR
..
··.·
i
DATASPAd
PDR
PAR
..
i ii.
i
I MMRO I MMR2
I MMR3
I . ·MMR1
INDEPENDENT SET FOR EACH MODE: KERNEL SUPERVISOR, USER
Figure 12 · DC] 11 Memory Management Registers
Bits*
l5
14:08
07 06
Table 12 .. DCJll Page Descriptor Register De&criptions
Description
Bypass c~che,.....This bit impleme.ots a conditiopa} cache .bypass mechanism. If the ]>DR
.accessed during a .reloc41,tion operation has this hit set, the time-multiplexed signalBS1 is
asserted during the subsequent I/0 cycle.
. ·
PLF (Page length field)-This field specifies the block number that defines the page boundary. The block number of the virtual address is compared against the page length field to detect length errors. An error occurs when expanding upward if the block number is greater than the page length field, and when expanding downward if the block number is less than the page length field.
Not used.
W (Page written)-This bit indicates whether the page has been written into since it was loaded in memory. When this bit is set, it indicates a modified page. This bit is automatically cleared when the PAR or PDR of that page is written into.
1-268
Confidential and Proprietary
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.DCJU
03 02:01
ED (Expansion direction)......'.fhis bit specifiesdn whicltdirection the page~- If E:D'*-0, the page expands.upwind &om bh:k number 0 to in~ bbcl!.'.S.'With higher addresses;.If ED·l, thepage,ekpahds:~fmmblook numbert27 w'iticlUd~
blocks with lower ac:ldnesses.
.ACFCACc~s rontrol'lleldbirus'tida coniiiliis the.i&ess Coaef~r'tllis p~.page.
The access code specifies the manner in which a page may be accessed and whether a·
access giveff
should
result
in
an
abOrt
of
the
Cllirerit
oPei'a·' t,:io:>n·· .',
T']'. ·h-','e"
~~ ·fl ,},
ate
J\ccess·Code
Page·Atcess
Bit02 BitOl
0 0
o 1 1 o
1 l
Nonresident-abort all accesses
RE.Ad only--abOrt ~n \Vrites
Notused;;.;.:..11bortrul11CCesses ·
Read/write: acce8s.
00 Not used.
*All bits can be read or written except as indicated.
The MMU conta.iDs four memory managt~~t ~~t'~t~t ate ~ to Cl)ntrolar,idl'~cor4the
status of the memory m~agement functions. '!lie registers and a4dress ~~t,s'l~'asf6lt~: · Memory mana,gement reg.ister 0 (acldre~ 17 777 572) · Memory management register 1 (address 17 .777 574) · Memory management register 2 ~add.n?s 17 777 576) · Memory lll.Wagement register 3 (address 17777 516)
Page Address and Page Descriptor Registers Each operating.mode is &Ssignedl6 page-address registers (PAR) ~16 p~escriptor registers
(PDR) to control the instruction and data space.. These 96 registers ate address.able tothe external DAL bus. A PAR contains a 16-bit displacement that is added to bits 12:06 of the virtual PC or to
the address received from the execution section tC> create pari ofthe:~fo~~"~hysicat address. A
PDR contains information relative te page data such as expansion, length, and access cont.rot The format of the information in the PDR is shown in Figure 13 and the function of the register bits is
described in Table 12.
15 14
08
I I
f '-----------'
BYPASS CACHE
PAGE LENGTH FIELD
PA1 WRITTEN
EOIREXCTlPd~ALI ~ ACCESS CONTROL FIELD
Figure 13 · DC]ll Page Descriptor Register Format
Confidential and .Proprietary
...
oc}u
The OCJI1 can optionally implement instruction and data space (I/D Space) relqcation to expand
the direct addressing range of a DCJ11 programor to facilitate efficient code sharing in a multiuser environment. I/D space relocation can be separately enabled for each of the pr6cessor modes. When l/Dspace.relocationis.enabled, the DCJll Classifies memory referencesasinstruction stream or data stream·referepces and independently relocates them.through the corresponding PAR and PDR. The memory referem;e~ are classified by the DCJ11 as I space references. All other references are classified as D space references. If the I/D space relocation is disabled,. all memory references
are relocated via the instruction space for that mode that includes the following information:
~. Instt\lction fetches
· Immediate operands (mode 27)
· Absolute addresses (mode 37)
· Index words
· First references in modes 17, 47, and 57
The classifications of memory references by addressing roocles for the first, second, and third memory reference are listed in Table 13.
Address M()(.{e
0-6 0 1 2 3 4 5 6 7
~Ster
7
Table 13 · DCJll ID Space Relocation
D D D/D D
D/D
I/D 'I/D/D
I
I/D
I
I/D
I/D l/D/D
1-270
Confidential and Proprietary
Memory Management Register 0
The memocy management register 0 (MMRO) provides memory management register control and ·
records status. The formatof the information in the MMRO is shown in Figure 14 and the function
of the i!lformation is described in Table ·14.
15
03
-
ABORT PAGE ' - - - - LENGTH ERROR. ,___ _ _ _. ANCBlOJtR-TREI~IOENT
.. 1..,
PAGE ADPRESS
SPA:CE!ltf .
ENABLE RELOCATION
Figure 14 · DC]ll Memory ManagemenlRegist.er oFormat
Table 14 · DCJll Memory Management Reamer 0 Description
Bits* Description
15
Abort nonresident-Set by attempting to accesu p~ with an access control-field key
equal to 0 or 2..It is_also set by attempting to use 1lletn0ry relocation With':an illt!g~
process<>r.m«le· (PSR 15:14"l'il.
14
40:ess Abort page length'error-$et by ~tteirtpfitl:g t6
a' location in a ~ with _a block
nwnber(~ ~s:bits 12·:0<>) d;ia~ is outside th:~ @t.llO'.~by~,page lqth
field of.the page desmpto~ ~tet !~r ~atpage:
.·
13
m.a Abort read-only access violatien-·'5etby .attemptitig ~-Write ~4-only page. Read-
only pages~ access keys of 1. ..
12:7 Not used.
06:05 04
Processor mode-A read-only bit that indicates the processor mode kernel/supervisor/
user/illegal associated with the page causing the abort (kernel= 00, supervisor= 01, user= 11, illegal= 10). If the illegal mode is specified, an.abQrt.i~generat~,~ ~t;t,?is set ..
Page spac~A read-Only bit trult indicates the ad<Iress sPiice (! or D) associated With the page causing the abort (O =I space, 1= D space).
03:01 Page number-Read-only bits that contain the page number of the page causing the abort.
00
Enable relocation-When set, all addresses are relocated. When cleared, memory
management is inoperative and addresses are not relocated.
*All bits can be read or written except as indicated.
.
Confidential and Proprietary
1-271
Memory Management Register 1
.
Memory management register 1 (MMRl) records any autoincrement or autodecrement of ;i general
pqrpose register, including explicit reference~ through the ~C. The amount that the register was
incremented or decremented is stored in two's complement notation. This allows an effective
recovery from an error resulting in an abort. The lower byte is used for all source operand
instructions and the destination operand may be stored in either byte depending on the mode and
instruction type. The register is cleared at the beginning of each instruction fetch. The format of
the information in MMR1 is shown in Figure 15 and the function of the information is described in
Table 15.
15
OB 07
03 02
00
. I
AMOUNT CHANGED (2'S COMPLEMENT)
I
REGISTER NUMBER
AMOUNT CHANGED (2'5 COMPLEMENT)
REGISTER NUMBER
Figure 15 · DCf 11 Memory Management Register 1 Format
Table 15 · DCJll Memory Management Register 1 Description
Bits~ ~ption
15:11 Amount changed-Represents the amount of autoincrement or autodecrement in the
two's complement notation for the register defined in b~ts 10:08. 10:08 Register number-Indentifies one of the eight general purpose registers. 07:03 Amount changed-Represents the amount of autoincrement or autodecrement in the
twa's complement notation for the register defined in bits 02:00. 02:00 Register number-Indentifies one of the eight general purpose registers. *All bits are read-only.
Memory Management Register 2 Memory management register 2 (MMR2) is loaded with the program counter information of the current instruction and holds this information when an abort condition is recorded in MMRO.
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Confidential and Prgprietary
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Memory Management Register 3
Memory management register 3 (MMR3) enables th~ dataspace_ ~or tJie kernel, s~p~rvisoi; and.~set:
'also oi:erating tl)odes. It selects either 18-bit or 22~bit mapping and ena~ the I/O map apd the
is request for th~ supervisC>r macroinsti-uction (CSM). 'J'he nrgister .£ormat shown in Figure 16.·and
the function of the information is described ifi Table 16.. ..
. .
~ ;..
15 14
ENABLE 22-BIT MAPPING-----..,..,,...,_,._...,.,,._ _..,,._,,._,.,..,.,......,_. ENABLE CSM I N S T R U C T I O N - - - - - - - - - - - - - - - - '
'KERNEL......,.......__ _ _...,__..w-;---..-..;.,...;.....,,..._"""""-"""""..,,_,................--....._....._~.
SUPERViSOR-~........................~......................................~...............-..._..........,.~................. : . -............... USER
Figure 16 · DC] 11 Memory Management Register 3 Format
BitS'*.
Ttble 16 · DCJll Memory ~t~ 3 Description
15:06 05
04
Notused..
Enable I/Omapc-Thisbitisused.toenable the.~terna{JlO~ilJg.The state ofthlshit
is reflecteclin the ~'Scignal during dresecond·mlf'~f:~:~teI:
Enable 22-bit mapping'-'-This:bit enablesthe 22-bit ~ey:addressitlg. The'Clef'Mlh is
1s~oit addreSsfug.
·
··· ·· ·
· ·
·
03 Enable CSM'. instrupicQ:=-This bit enables the rec0gllitf9li ~f't:IJ.e Call· s\i~$or ;~e
instruction.
02
01
Supervisor-Enables the data space mapping for the supezyisOi'operatirig mode.
00 User-Enables thedata,spacemapping for the user-operating mode,·
*All bits can be read or wi;itten except as indicated. '
Confidential.~ ~ppietary
1·273
__________ ·-"'-"' -----------~~~·--·-------~---
-
·Interrupts
The PCjl1 prmfides a se.t of trap, hardware, and software interrupt facili.ties. Fotir interrupt request lines allow the external hardware to. interrupt the processor o.n four interrupt levels using an externally supplied vector. Eight levels of software.interrupt requests are supported through use of the PIRQ register. Internally vectored traps are provided to flag error conditions. Table 17 identifies the PCJU asynchronous interrupts. The synchronous interrupts are listed in Table 18. The execution of a HALT instruction may cause different operations depending on the halt options determined during powerup and onthe mode of operation.
In kernel mode, a halt option of 1 causes an illegal halt abort if the HALT instruction is executed. Bit 7.ohheCPU error register is set and a trap is forced through vector 4.·If the halt option is 0, execution of the HALT instruction places the system into console mode. Execution of the HALT instruction in user or supervisor mode causes an illegal halt abort.
The halt line usually has the lowest priority; however, it has highest priority during vector reads. This is to allow the user to break out of potential infinite loops. An infinite loop could occur if a vector has not been properly mapped during memory management operation.
Table 17 · DCJll Asynchronous Interrupts
Interrupt
Location
Red stack trap (CPU error register bit 02)
Internal
Address error (CPU error register bit 06)
Internal
Memory manageme11t violation (MMRO bits 13:l'.5)
Internal
Timeout/nonexistent memory (CPU error register bits 04,05) Internal
Parity error (PARITY, ABORT)
External
Trace (T bit) 'Jhp (PSW bit 04)
Internal
Yellow stack trap (CPU error register bit 03)
Internal4
Powerfail (PWRF)
External
FP exception (FPE)
External
PIR 7 (PIRQ bit 1'.5)
Internal
IRQ7
External
PIR 6 (PIRQ bit 14) EVENT IRQ6
Internal External External
PIR 5 (PIRQ bit 13)
Internal
Vector Address 4 4 250 4 114 14 NM 24 244 240 Userdefined 240 100 Userdefined 240
Priority Level*
NM NM NM NM NM NM
NM NM
7 7
7 6 6
5
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Confidential and Proprietary
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IRQ'5
PIR 5 (J?IRQ bit 12),
IRQ4
PIR 3 (PIRQbitll) PIR 2 (PIRQ bit 10)
PIR 1 (PIRQ bit;09} Halt Urie (HA.Il') ·, .
*NM= Nonmaskable
Veetot Location ~
Enernai. User-
5
defined
240
Memory Parity Error
114
TRAP (trap instruction)
34
EMT (emulatort.raP instt\lcti6~)
1ar (I/O trap instruction)
BPT (breakpoint trap instruction)
Timeout and reserved instruction
Confidential and Proprietary
1-275
...
· Bus ()peratiQP. ,.,,
The DCJll perform~ the bus''tmnsactions during the execution of the program instructions. Transaction requires a minimum of four clock perfods and a maximum of eight clock periods. A transaction may be extended or stretched beyond its normal clock timing in increments of two clock periods. A read transaction can be extended by a minimum of four clock periods. This allows
a transaction to be extended fodefinitely. The four address input/output signals (AIO <3: 0 >) are
latched at the DCJll output at the beginning of a transaction and indicate the type of transaction
being performed. The AIO < 3:0 > codes for the type of transaction are identified in Table 2.
The bank select (BSl and BSO) signals are used with bus and general purpose. read or write transactions. Thc~e signals provide ,coded information to define the type of physical address that is on the DAL<21:00> lines. Thebank select transactions are listed in Table 3.
Physical addresses that are less than 17760000 (octal) are memory references. Addresses in the I/0
p8.ge (17769000-17777777) that do not access a DCJll register are external l/O references.
Addresses in the I/O page access internal registers, except for CCR, are internal register references. Systemregister references are addresses 17777740 through 17777750.
No Operation Transaction During a no operation (NOP) transaction, the DCJll performs an internal operation and the bus is used for external data as shown in. F~gure .17. The assertion of ALE latches the AIO code that identifies the transaction as non-1/0. The ttansitction requires four periods to complete provided no DMA requests occur.
If DMR is asserted at the start of the cycle, the NOP transaction is stretched. A stretched transaction is shown in Figure 18. The DMA request stretches the transaction to a minimum of
eight periods. The DMA request is received on DMR and is granted by MAP line. The BUFCTL an'd SCTL signals are asserted during the stretchedportion.' the transaction continues to stretch in two-
period increments until the DCJll receives the CONT signal to end the transaction.
TO
T1
T2
T3
Figure 17 · DC]ll Nonstretched Non-I/O Cycle Timing Sequence
1-276
Confidential and Proprietary
CLK
DAL
m
AIO
Figure 18 ·&111 stritchCd. Non-110 Timin'f)equence
Bus Read Transaction
J?# rrom A bus read transacti~n s~pwf1 irt,Ftgure 19 ~~.es ~h~. ~its !Sl ~iW~orwati.o,n memory, I/O,
and other addressable rl!gisters. These transactfuns may be instructiOn stream read, data stream
read, or the read portions of read-modify-write. The type of read tnmsaction being (lerformed is
identifie4 by the Alqcode.J'he D.CJll reads wprds a~d if a l:>yte is,tequir¢, the complete word is
tead @d the eXce~s byft: isigrior¢1.''\
· ·
'··
·
T~ DCJll f<llorts. filetl:l;'?!Y rnllt1as,errient. gr a. .~~~·'.~'the :ABf!>t\j·,~~£tt.t.dlJt'ing the
n6ristretched portion of tht:! transaction. If the
·.signal is"~d,·t~frtroi:tnatiori on DAL;
m. BS< 1:0 >, andMAp lilies shoula be ignored an<!Tu~')jus transaction;~ooldnotbe started.
~·read transaction ~initiated .by the assertion of
This sign,id,#t. '
' i1ncode, the
physical address on'·DALbus, the B5'< J:iO >, <a;·and the"mli·{~~~J': . . . .gignal. Tiie
DCJll latches the data 61'1 the rising <Xigeofthe T31it:tting lt.~~etclil~ ~cti6n:1\ bus read.is co.m. p.l.e.t.e.d.fo.. f.ourJ?<·;·riO. .d.s..w. l. ie..i.i.a.l. .lo.f. t. he..fol.l..O.wi.!'!I"L'.c.on.d...ii.. l...a..n...i..~,. s. t... ·~· .....:.·.'.".'.',;':."..;.~..~. .. ...... .......·
· BS<l:O.> set to zeros(memory reference)
· No cache bypass
· No cache for<iemiss ··· ···
· No DMA grant
· Noab:ort during adetnand read
-
Ifany one of the these· conditi'Q'ns exist, the transac;tioµ *-etches to. a minimum of eight periods as
shown in Figure io. The BUFCTI.: andSCTt·Ifues "are asserted during the stretched portion. The
triti)$l.ction will continue to stretch' in two-period inc;tefaenis u:ni:ilthe fJCJllrei:eives the CONT
signal toend t!ie transaction. The data is read into the DCJll when the DV signal is recei~ed. If the cycle is stretched· because DMR was asserted, the DV signal should. not be asserted because it
overwrites the previous valid data.
·Figure 19 · DC]11 Nonstretched Bus Read Cycle Timing Sequence
CLK
ADORE~~ ~ ~T1
T2
TJ· T4
T4
T4 ~T6
T7
1 PHYSICAL
.. f
DAL
lll\\\\\I
y
DRIVES~
Ill DAL ~
SYSTEM INTERFACE .ORIVESDAL . .
tmr
~
\\~
l/l1lJ
OMA REOUEST"l
mxx · m:
l/O MAP ENABLE"l
J_
I
J_
..:J ..l.
mx
' ))X((l
1/0 BANK SE LEC1::::i.
HX~ OMA GRANT
·.
..l.
BS
::! }}X{~
))X{( CACHE STATUS
CACHE HIT
I
I }}X((
i\\\ J/JJJJ
CACHE !lllSS
MMU ABORT STATUS
]\\\.\\
\\\~
VIII! I\\\\\
I
..l. MMU AND SYSTEM ABORT STATUS
T
I
T
I
l/mr
!\\\.\\
I
Vll!T
CONTINUE
l \\\~
1l111J
DV
11/fJ
I\\\\\
Figure 20 · DC]ll Stretched Bus Read Cycle Timing
1-278
Confidential and Proprietary
-
.···~
! ~· ~;~U·
BDuusriWngraitebu1siawnrsia~di~oCnti.· ·o.· . ·n..,..'$b..Q. \v..n.in.·.
. ·... .. F'igll.re 21,
. . the
.D...AL·...bu~
is
Used
tQ
write information
into
memory, 1/0, and other addressable registers. The information can be a byteotia'Word~..~
bytheAIOcode.·Th.eOCJllreportsmemocymanll8Cntentor.ad.dre~~rrorson;rJw;~·~
the first part of the cycle. If the ABORT signal .is asserted, the information on'bAL < 21:00 > ,
BS< 1:0 >, and MAP lines should be ignored.
The write transaction is initiated by the assertion~£the00Jt.~.Thiuignallat~ the AIO ~;
the physical address on DAL< 21:00>, BS< 1:0>, andthe ~ (I/9 Mf1J> ·~)signals: A~
write requires a mimimum ofeight periods and canb.utretdled.iP.t · · d fuaements until the
OCJll receives the Ct>NT signal to end the transaction. The &t~slahal.is ~ during the
stretched portion and the write &tills valid oh leading ~d,~ ~Ii. 9f~ ~·Sig~.
Sixteen bits of the DAL bus ~ used for byte write with the ~cdata «l ale.low byte ifthe
address is evenand the correct data on the high byt;e if the ~s$ ·if OM.''The data on the
remaining byte is not defined. ·
· · · ·· ···· · ··
·
·
CLK DAL
AiOR'f. +-..................~.......;;;;.;;.;;,.;.;;;;;~;;;,;.;.~.......,.
BUFCTL +-...._+-_.,+"-.....,+-""-'+'-.......,o;..;........~.....,.-4'-..._.*"'"........""""-..."+'-..,._"+--.....,...__.o.+--_.
SCTL
~Purpose Writar Transactions
.'" ·.·.· . . .n, "'
.
The general purpose write tmMactk>n is used.~ ad~ noo-~DP-11 interface hardware through
the~purp<>Se·codeson:qAL<07:Qt}~: Either·bytcorword\'Vritescanbeirtitiated·asdefiQ.e,4
l;>y the A.IP ~,Zfbe ~~~ ot}tl)eJ>A.i,,~us ~H?9()~~.Th~ .XJPC bit~.re~tthe gen~nd
purpose write' ,code.. '.Bllle 19 lists the write code assignments for the ·general purpose teid·
transaction,
Confidentml arid P,nlprietary
1-279
-
Write Code Function ·
ooJ' ..
Writes FPA i6~bit data'.
014
Asserts bus reset signal
034
RdeilSes system frorn conoole ODT mode
o4o··
Rese~~d for future use '
100 J 214 '
Acknowledges EVENT
140
Ackno:wledges powerfail .
220
Microdiagnostic test 1 passed
224
Microdiagnostic test 2 passed
230
11.ficrodiagnostic test 3 pas~ed
234
Places _s,ystem irit0·console oDT'mode
The general pu~se ~rite trans~ction shown in Fig~re 22. is itji'tiat~d..i,y the ~s~rtion~fthe fil
line; This· signal latches the AIO code and the general,.purpase ct0de on ,~he DAL bus. The
transaction reql.lires a minimum of eight periods and is stretchect in two-period increments until the
DCJii recefoes the CONT sigrinl tQ endthe ~nin~11ctiqn. The SCTL sigrlal i~' asserted during: the
stretched portion and the.write data is valid on leading and trailh1g edges.of this signal.
CLK DAL
m
frcrt· '
'' ~'
DV
Figure 22 · DC]ll General Purpose Write Cycle Timing Sequence
1-280
Collfidentiltl and Prdpiietary
-
General Purpose Re..t Transaction
Tli¥ gen~Pur1lose'write tialisactio~ is USed to addre5s non-PDP~n·mterfacC"harti~ throu&lf
the~-:~ ~es pl$Ced ofrthe DAL< 07~00 > btls. 0hfy ®rds .re1'ead by the~
~--·~s··~11·i£1 a·.~.·is. reqUired, .the ·excess. byte is·~. 'The~··on tbeDAt:i's
1~~xxx: ~:'XU: bi1frepMent the sem~taf~ ~a code: Tab~ 20·&tS the re&& cede
assigtlinentHoithe ~ purp<)Se read ttaiimto.t:t ' .,.
.
000
Reads. Ule··~rup. m@de..:hftltJ~~·..fPA.9pt;i.~,~~.h~>~J?9~i~: ~'
.··boot ad~·td'uri.Pgiuj~j(tf~f.i®..··~.-~··.Jnld~t~n.section~
001
Reads FPA data.
, ,, I ,
002
and··fle'aas''th~ 'pOv,i~I>rribc?e, haJitiy,tlpn.; FPA,o?ti9ti; POK ~al>'a~bt;i0r:~clteiis,'.
cl~~· FPA's FPS. ' ., .·. ' " ' ·.'? '·· ''' ' ' ' '
I .·
The general pu~ re~ tmnsactioq, s~n in F,Jgure ~3, is ip#iataj. by th~assertion of the ALE
line. Th.ls ~g~·~tshe~.-~e 41q¥~~ an~""the's~n.e~.rµi.~~ t(adt!ton~th,~ 'f;>t\L ~. 'fh~
~~af~O.n, reci~a· nurumum of eight periods
t · J~Q:~{l,pci.!!;lttements until
the IDtJll rereives'.fnffCCfNT'sigfuilt~·en:a the'
·· .· . ·.·.··. ,t.y'ecei~t~DV~nal encl
latehestbedata.while·SGtL~.
'; :" ;-: ·. · ·
'
CLK DAL
Figure 23 · DC]ll General Purpose Read Cycle Timing Sequence -1·281
-
DMA Request and Grant '.lhmsaction
"· ·.
...
>. , ,.
When the extetnal'system req¥ests the use of the D~I,. bl,15 or want~. tp1stalfthe DCJli, ,if ~er.ts the
DM,R input. This disable&; t~ DCJil frqm the DAL bus. anq ,c;aµses a stJ;!':t<:hed.transaction:. The DMRinputis acknowledged·afte-nhe 1/0 map i!lf9i:mation ison!he.:\)11).l? cm~put; The l),¥R inpq~
is the P;.1.A request and the Mf\P output _is the DMA grant. These. signals should be recog,Qized
during NOP or read transactions. The write transactions stretch beyond four peri,ods l\lld the l).tµ.
bus may contain write data. The DMA transfer stretches the transaction beyond eight periods by
two period increments, until the DC]ll receives the CONT signal to end the transaction.
Interrupt Acknowledge
..,
The interrupt acknowledge transaction is used to acknowledge an interrui;>t request recehred .
through the IRQ<3:0> inputs. The.vector address specified can be an interrial predesignated"
address or an cbcternal address received on the DAL bus. The deooded interrupt level acknowledged'·
is sent on the DAL< 03:00 > lines at the beginning ofthe thutsaction. The DAL< 21:16 > lines are
set to one and DAL bits < 15:04> are set to zero.
Thdnterrupt ac~owledge trarisactionshown in Figure 24, is initiatedby the assertion of the ALf: line that latches the AIO code and the acknowledged interrupt level.' The trans~don requires eight periods to read the vector address and can be stretched in two"period increments until the CONT input is asserted'. 'The DV input is asserted to latch the interrupt vector address while the SCTL
signal is asserted.
Figure.24 ·Interrupt Acknowledge Cycle Timing Sequence
-
Initialization The DCJll starts
. the
. . . ·. · initialization
<
i. ..
process when\he
.~··.·. y. stem
....
interface
pro.~e,. s
5
volts.(Vcc)
and
asserts INIT for a minimum of 25 dock periods. The INIT signal can be assettedby the sys~
in~f~.hY us~ a.fi>OWet wakeup circui~, ~ ~nitWizati9n process can~ itilpfe~nted at ~Y
time the system interface asserts INiT as showq~lf~ 25. ~r
Figure 25 · DCJ11 InitialiZtltion Timing Sequence
Th~ inltiauzatlon piixess uses the powerup ii;iltiOe, t& ~·i<ajijrie: ~~~,~~ ~t
returns the DCJll from the console ODT mode. A 002 G'P'~ ~bn 1$~£01,;fil(:d d:tirilig'ariy routine, and the .system interface provides the configuration data through the DAL< 15:00 > .The system interface pl'QVides .tbi$. data byJwd,~, ~ft:w~, Ptf~. fjggre i6 ~c:nys, the forµiat of the information in the ~~tion>.ter;;aod;Waf,1"'.f21 lists the function ofthe
information.
UNUSED-----------------' HALTOPTION------------------POWER U P M O D E - - - - - - - - - - - - - - - - - - - - - - '
POK------------~--~--------~---'
Figure 26 · DC]ll Powerup Configuration Register Format
Confideritial.mJd PmptWaty
-
15:09
for &ot· address...;;:Provides the boot'addte8;; as the .PC:· the usets program whenthe
powerup option fl3 is used. The PSW is 340. · ·
' '
08
FPA available-Indicates the system interface is using a floating-point accelerator.
07:()4 Not used-Reserved.
03 02:01 00 ,
Haltoption-'-"'Selects action to be taken when ahalt is executed in kernel mode.
Powerup mode-Selects the powerup mode for the system mterfaq!..
POK~lndicates when the system ac power supply is OK.
*All bits are read-only
~., tnOde'.""'°':['able 22 Jists th,!1 fo~ pc>weru~ ortions available .to the user and selected by mode
bits 02 and. 01 ofthe configuration i;egis~r: . . ' .
. .
.
.
',
'
'"
... ;,
1.
Powerup Bit02 Bit01
0
0
0
1
1
0
1
1
Mode Description
PC at 24, PS at 26
Mlcro ODT, Ps =O
PC= 173000; PS;.. 340 User bootstrap, PS= 340
Confid.eritial and Proprietary
-
· Powerup option o~The procCslJor reads physkal meuiory locations 24 afiif26 and loads the data
into the PC and PSR, respectively. The processor services. pending interrupts or starts program
execution beginning at the memory locat~ P?#tted to by the PC.
· Powerup option 1-The processor uncon<J,itlqp~lly,,ent:er~ Micro..OIYI' and the PSR is cleared. The pending service conditions are igno.red.
· Powerup option 2-::;:1":111t!~!l$()r sets~ ~;,~~7~906 ~d the PSI}~l1P· The processor then
services pending infetrliPt~, QI:. starts JP~· ~tio1" ·bqinning at the memory location
defined by the PC. This option is used f6t ttif g~'bcsbtstrap procedure.
,·''.·Ji!! .. _' --
'
· ~werup optionri"""'~~~sor n;{ads'ffl'~*:'.S~ by th~,.~n bootstrap ~ss
JUmpers and loads the reSultibtci the PQ< 15:09 >. M<O&:OO > ate cleared and the PSRlS set to
340. The processor then services pendi981~~is:g!s~s the program execution beginning at
the memory location pointed to by thejPc~. :r· '' .,,, : . · .. ·1
"·
'
'' ;"\ -~'
;' ' \·
Power OK-The power OK (POK) inpuJisl:"ro\r~by t:h~Jrstem interface to indicate that the ac
! supply is operating at the<:<>~ voltag~: When,:~t~is,~, the voltage is correct; when bit 0 is
cleiu; the DCJlf ~~~'~is off. .·,. · ,.. ·
Boot Address-The boot address reads fhe·~~dms (15:09) of the starting address from
the system interface. The remaining bits (08:~.J.~,~as·~s. This ~the bootstrap address
to reside on any 2,048-word boundary. 'Fheboot.~s issele(:ted by powerup option 3.
FPA Available-The system interface s~thi~~1i~ffl;¥ IlO.ting-point ac~tor is in the system
and is cleared when a floating-point accdemtar i$,r.iot1Acl~.
Halt-The halt option is used by the s~ilf~~J\? ipdicate the interpretation of the halt instruction in kernel mode. When set, tl:!is bit ~1;~;~t)the processorWill trap through vector address 4. When cleared, it indicates thatt~willb!pla<::ed into console ODT mode.
'!iL
'< . .;' ' · Initiali:r.ation Sequence
The initialization sequences
are
shown
iin~'.toJl<>Wing
flOw
diagrams.
The
powerup
routine
is
described in Figure 27, sheets 1 throughA"Th!'.·~rout;ine is desc.ribed in Figure 28. The
return from the our routine is described:.inE~.z,; ~ 1 and 2. All t:Wese routines perform a
variety of GP read and write transactions that are~ed in the Bus Operation section.
!:
'
1-285
-
GP WRITE
.GP WRITE
NIP. GP WAITE NIO NIO 'NIO BUS WRITE NIO
oqg; EXTERN.A. L.. l!,,_ . M;.
ASSERTS !Nl'TFOR A MINIMUM OF. 25 CLK PERIODS
SYSlEM IS NOT IN CONSOLE OOT MODE.
SET SYSTEM RESET f.LIP·FLOP
GENE.RATE GP CODE OF 214
CL.URMMR3
CLEAR PIRQ REGISTER ILOC. 177777721 .
·CLEAR FPS
Figure 27 · DC]ll Powerup Sequence Flow Diagram (sheet 1of4)
1-286
ConfiClenruu and Proprietary
BUS CYCLE
GP READ NIO
GENERATE GP CODE OF
002
BUS WRITE N.10 BUS READ NIO
WRITE ZEROES TO . THEMSER
(LOC 11777744)
~T 80F THE CCR, WHICH rs
"ty
IMPLEMENTED BY
THE . R /11$· lHE FLUSH CACHE
B1'f;(J .. ACH!i<SYSTEMSI. CLEAR THE OTH.~JN:!CR BITS.
~~fAR THE MEMORY SYSTEM
...eRi:mA.$EGlil.E,R, WHICH MAV <rl1A'~'(.~T !!IE)IMPLEMENTED
BYrili)tt~,*fl. ·
Figure 27· DC]11 Powerup Sequence Flow Di·' a~ (sheet 2 of4)
BUSCVCLE
DC.I' 1'\)''' OPERATION
GP WRITE BUS READ
GENERATE GP CODE OF 220
READ MEMORY LOCATION 00000000
. T:EST u·J,\SSii.O. CPU ERROR REGISTER WRITTEN AND READ CORRECTLY.
DETERMINE IF EXTERNAL LOGIC THINKS LOCATIO'N (I IS IN NONEXISTEl\IT M'TMORY UT SHO!Jl.[) NOT). IF IT DOES, EXTERNAL LOGIC "tYPJCALLY GENERATES AN ABORT.
GP WRITE BUS READ
GENERATE GP CODE OF 224
READ MEMORY LOCATION 17777660
·Dift'ER;iilNE IF ~XTERNAL LOGIC THINKS
1-0,.CATIQN 17777700 IS IN NONEXISTENT MEMORY (IT SHOULD}. IF IT DOES, EXTERNAL LOGIC TYPICALLY GENERATES
.. A.N ABO!fT. ·
'fES:t ~PASSED. NXM ABORT NOT
GENERATED BY REFERENCE TO LOCATION:QBUT WAS GENERATED
mntoo. · BY.IU';fERENCE ll"O LOCATION
READ RECEIVER CONTROL ANO STATUS REGISTER (RCSRl
Figure 27 · DC]ll Powerup Sequence Flow Diagram (sheet 3 of4)
Confidential. anli Proprietary
BUS CYCLE GP WRITE
-... ~~:-
·A'i1-LLUUU.J
NOTES
~'
OeTElMtNE IF EXTERNAL LOGIC THIN!4S LOCATION. ll~:P,600 {THE .·, . ~CSRJ; IS tN NONEXl'STENT MEMORY '''.ftTSHPULO NOTI. IF IT DOES,
·tm,..NAt.. LOGIC TYPICALLY
GENSRATES AN ABORT;
o:,;'<7 :;-!'-<,;;;- ;N .-,
'":·TEST·$ PASSED. NXM ABORT NOT GENERATED BY Rl!FERENCE TO RCSR.
CODE
TRAP THROUGH LOCATION.24
~;:::--:*.·,-
Figure 27· DCJll Powert4P 'Sequence Flow Bjagram (sheet 4)
·'",' ', "~-~'
~
1-2.89
-
BCISCVCLE
GP WRITE 2BUS READS 2BUSWRITES
OCJ11 OPERATION
POWER DOWN
GENERATE . GP CODE OF
140
TRAP THROUGH LOCATION24
GP READ
EXECUTE NEXT POWER DOWN SERVICE
ROUTINE INSTRUCTION
SET!31T7 OF CPU ERROR REGISTER AND TRAP THROUGH LOC4
:ijTART INl"tlALIZATION SE QUE N C £
SETBIT7 OFCPUERAOR REGISTER AND T!'IApTHROUGH LOC4 .
ENTER CONSOLE ODT
Figure 28 · DC]ll Powerdown Sequence Flow Diagram
1·290
Confidentiil and Proprietary
-
BUS CYCLE
Gl'cWfUTE GP WRITE NIO GP WRITE .MIO
NIO BUS WRITE NIO
OCJ11 OPERATION TYPE ING WHILE IN CONSOLE OOT MODE
GEN&MTE G03P4CClbEOP.
GENERATEQP CODE OF 014 .
DELAY O(>ERATION FOR69 ) MICROCYel.ES
GENERATE GP CODE OF 214
CLEARMMRO
CLEAR MMR3
DELAY OPERATION, FOR 600 . :
MICROCYCLES i
NQTES
Figure 29 · DC]ll Console Start Sequence Flow Diagram ·
Confidential arid··Proprietaiy
1-291
BUS CYCLE
,Qc,111 'Ol'ERATION
NOTES
.','.""·'-.d~t.J,4',.lli'l.'.
READ POWER-UP CONFIGURATION DATA THAT IS DRIVEN ON DAL BY EXTERNAL LOGIC.
BUS WRITE BUS WRITE BUS WRITE
WRITE400TO
THE CCR
,
(LOC 17777746)
WRITE ZEROES TO THE MSER ( LOC 17777744)
WRITE ZEROES TO LOC 17777744 .
SET BIT 8 OF THE CCR, WHICH .." IS TYPICALLY IMPLEMENTED BY
THE USER AS THE FLUSH CACHE BIT (IN CACHE SYSTEMS). CLEAR THE OTHER CCR BITS.
CLEAR THE MEMORY SYSTEM ERROR REGISTER, WHICH MAY OR MAY NOT BE IMPLEMENTED BY THE USER.
NIO
CLEAR PS
BEGIN EXECUTING CODE
Figure 29 · DC]ll Console Start Sequence Flow Diagram (Continued)
· Instruction Timing
The execution time for an instruction depends on the type of instruction executed, the mode of addressing used, and the type of memory being referenced. In general, the total execution time is the sum of the base instruction fetch and execute time plus the operand(s) address calculation/fetch time.
Tables 23 through 30 and the source and destination tables Sl, Dl through D6, and Fl through F4 are used to determine the execution time of an instruction in microcydes. The execution times listed in the tables specify the number of microcycles required to fetch and execute the base instruction. The read/write (R/W) columns specify the number of read and write microcydes required. If the instruction involves a calculation or fetch operation of one or more operands, a source or destination table is referenced in the table. The source and destination tables specify the number of microcycles required to perform the calculation or fetch operation for the source or destination. It also lists the number of read and write microcycles required. During the remaining microcydes, no operations (NOP) are performed.
.Confidential and ProprietaJ:y
-
The fable Wfues aij;;~\llculated ~\llJm~ that:;\ i:ead froqUlJ<:tl10l)O~tiO~ requires a miniffiull1 of
four clock ~iods, a:write to memory operation requires a. fninimum of eight clOck periods, and a
NOP'rrt~tiUctionr&i~res fo~ cl&ffperiQ<ls wben a DMA transaction is not ~tiated. The time for
rukl:&l a wait stat caU8kdb)r a sfo-Q/'memory or 'resulting from a DMA transfer must\%
tO the total
execution time. The first wait state of a nonstretched read cycle or NOP cycle requires four,clocl<.
periods at)d can continue in. increments of tWQ·cb::k periods. Additional wait state$ for stretdled
cycles ocrur in increments of two clock peric>cl$i '·.
ryf>e The execution time for floating-point·'· instructions will vary depending on·. the
of &tit
operation.
InstrncdQD Tuning ~pl~$
The examples that follow Show how the information from the tables is used to ~mcthg·totld
time of an instruction.
Example l: Determine the execution time df a MOV R0,@#2044 instruction'.
1.
The
~tion
time
for,,'_~-.e
MOV
:. (,~<r:~_-'-,·;/_7
base; in¢qiietiq,'1
is
1 µc,
or
fou__r.;/?:>CI--L:·.·F.:.;~;_-~ ';_.. s ,_._r_-.;·(··;~-IJ_t- b.-l-e
26.)_--;·--,:~_!i1#~
consists°.~ one read miClt)cycle. The micl'9#fl~}~\ay be stretched 'dtj)enffi~HpOn.the fy~.9{
memory in.the system..If the microcycle is stretthed,it requires a.tleast eight CLk periods .and may
be stretched thereafter in increments of two CLK periods.
·
tB 2. To findthe operand caleulation and fetchtitfiefdr the source operand RO,·ref& Tabl~St A a{ic: mode 0, register 0calculate and fetch requires Note that the operand is alread~1lvailable1'.6.tJ:ie
DCJll in the register file. ·
' ..· '
/
; '
3. To find the operand caleulation and fetch time for the destination operand t.trul'~·to·At:s·M memory l6cation 2044), .refer to Table· D3: cA_'.fiio& '3· ~gi$r.ett7 ·ai.1~te·afid:fetcli opemlli.011
a requires 3µc. One is a readritlcrocycle and one 1~ Write microcyde. The·remai~:microcydeisilllh
NO:Pmicrocycle. The type df meinoryin the syste.mmust betaken irito aecourii:.If the readcyde is
stretched, the stretched cycle requires a minimum of eight CLK periods and may be stretched
thereafter in increments of two CLK periods. The duration of a write microcycle is a minimum of
eight·cLK·periooS aaj ~a~, he· i;n~~fi,,ini~~~~,.?£. ~<.l~~ ~fi.qq~··
4.. To, det;eJ;rµirle th~. tjiiriimum time.· raj~d~ fotal up the miqocyeles. In this example, it iS
1 +O+ 3, QfA µc (whii::\t is 16 C~ periog~ i{.~'rnict'OQ'~~ %£retching occursl..
.,
' ' ,,,,,
' "' ·.
: ' , ,,. \·"- ,, '.
''-~'' ' >f'>'>
'. >
Example2: The source ahd destirtatiotftables for floarinifpoi11t instructions show a· ~8~f!~~.·
shows number in .the microcy!=le colmpn for certain mode 2 reg~.ster: 7 operations. This example
~.
timing calCulation for qne of these.
·
· ··
Determine tne execution time (If a CLRD #2000 instrµcti<;>Q.· ,
1. The base lnstructidn time for the CLRD instruction isl41-'C.
2. From Tuble F2, th~ caJclliation and fetch time for the operand (a mode .2 register 7 referep~e) is
no -1. 1 µc is sµbtracted f1.'9m the bll$e instruction time. For.the if:P.emory wri~ qpeJl2tj9n J: µc mu~.~
added to thls value. There are memory read cycles to aq:cn;mt for.
.
3. The total of the microcycles is 14-1 + 1= 14 µc mirul:num. This value assumes the cycle iS not
stretched.
-
P.liminary
»C)U. r. 1,.::. '--:
Table 2) ·DCJll.Single CJtlerand ltlstruction Executidn.Tinles
Exeeu~
SoQree Destination
Mnemonic Instruction
Opcode nme (µc) aJW Tuhle Table
General
CLR(B) Clear
0050DD 1
1/0
D3
COM(B) Complement (one's)
0051DD 1
1/0
D4
Il\IC(B) Increment
0052DD 1
1/0
04
DEC(B) Decrement
0053DD 1
1/0
D4
NEG(B) Negate (two's complement)
0054DD 1
1/0
04
TST(B) Test
0057DD 1
1/0
04
Rotate and Shift
ROR(B) Rotate right
0060DD 1
1/0
04
ROL(B) Rotate left
0061DD 1
1/0
04
ASR(B) Arithmetic shift right
0062DD 1
1/0
D4
ASL(B) Arithmetic shift left
0063DD 1
1/0
D4
SWAB Swap bytes
0003DD 1
1/0
D4
Multiple-Precision ADC(B) Add carry sbC(B) Subtract carry SXT Sign extend
0055DD l
1/0
D4
0056DD 1
.. 1/0
04
0067DD 1
1/0
D3
Multiprocessing
TSTSET Test and set (low bit int!!rlocked) 0072DD 5
1/1
04
WRTLCK Write interlocked
0073DD 4
1/1
D4
Table 24 · DCJll Double Operand Instruction Execution Times
Mnemonic Instruction
Opcode
Execution Time (µc) R/W
Source Table
Generat
MOV(B) CMP(B)
ADD SUB
Move Compare Add Subtract
OlSSDD 1 02SSDD 1 06SSDD 1 16SSDD 1
1/0
Sl
1/0
Sl
1/0
Sl
1/0
Sl
Logical BIT(B) BIC(B) BIS(B)
Bit test (AND) Bit clear Bit set(OR)
03SSDD 1 04SSDD 1 05SSDD 1
1/0
Sl
1/0
Sl
1/0
Sl
Register MUL DIV ASH ASHC XOR
Multiply Divide Shift automatically Arith shift combined Exclusive (OR)
070RSS 22
071RSS 34
072RSS
4
073RSS
5
074RDD. 34
1/0'·11 1/0'·"12 1/0 1/011 1/0
Destination Table
D3 D2 04 04
D2 D4 D4
Dl Dl Dl Dl D4
1:294
Confidential and Proprietary
···
MnemoniC Instmclion ·
Qpcode
Branches
BR BNE BEQ BPL
. Branch unconditional
Br if not eqwtl to 0
· Brifequalto-0
. Br ifplµs . .
BMI Br if minus
BVC
Br if ov'erflo~iis clear
BVS
Br if overflQ.W is set -
BCC Br if carry 'is dear
BCS . Br if catty is set
.. 000400·
001000 001400 '
100000
1004(1();
· io,~~s-nr
102400 .
105000
i03400
Signed Conditional Branches
BGE Br if greater or equal to 0 020000
BLT
BrJ£.~~~Q-
. ,,}Q<!2f!Q(l·.
BGT Brif greater than 0
00:3000 .
BLE Br if less _OJ: equal td t:J ·
<};, ,, } '
,' " ' ' ' ,.
uo ·stgned ConditioMrI/B·;ranches
003400 ·~·
BHI
Br ifhigher'
101o&
BIDS Br if lower ot same
BHIS Br if highefror same
·101400 lQ}QQQ
BLO Brif lower· .
103499
SOB Sul?tract 1. a,rid bran~ if 077RNN
not equal to,O
Branch
Branch
Not'Daken
. ·iGflten;
T'nne(µc) R/W . .,-r~. <"4C/ . R/!f,· ·.
2
1/0
4
2
1/0
4
2
1/0 4
2
.1/Q 4
2
1/0
4
2 2
'. ' ljQ
· 110
...... 4 4
2
' 1/0<·· 4
2
1/0
4
2/0'..
2/0 2/0. .. 2JQ ,'
2/0
2/0
..2/0
2(6· 2/0'
2
1/0
4
2/0
~-·
l/q \l
. 2/b
2
1/0
2/0
2
1/0 .4
2/0
2
1/0
2
1/0
·2
1/0
2
1/0
3
1/0
Table 26 ~ DCJU JuuiP and'~tine InstructiQn Execution T'mies·. ,
MnetnoniC Instructio'1
JMP
Jump
Opcode · OOOlDD
E~tion
DestinatiOO
MC' ·
K{'f{; " , , l@J;Je :..1 .. n, ,., . ,, .:.,., . J' ;:!
JSR
Jump to subroutine
004RDD
D64
RTS
·Return from subroutine
00020R 5
3/0
14
MARK Stack cleanup
0064NN 10
3/0
·-
Mnemonic lnsttuetion
EMT' 'Emu1~tor tr!lP ·r
TRAP Trap
BPT ·.1- __
IOT·· .
RTi:
RT::f.··
Breakpoint trap Input/output trap Return from intet~pt Return from interrupt
Execution
Opcode Time (µc) R/W
104000-
) \.
104377 20
4/2
104400~
104777 20
4/2
000003 20
4/2
000004 20
4/2
00o002 9
4/0
000006 9
' 4/0
f'~\ --.:
Table'.28 · DCJ1t Con~tion Code Operators Instruction Execntibn 'Times
,''..,
Mnemonic Instruction
cu:: Cleare
Opcode 000241
Execution
Time (µc) RfYJ
3
CLV Clear V.
OQ0244 3
CLZ ClearZ
000.244 3
CLN Clear N. i
CCC Clear all CC bits
. Q00250 3
'1/0
000257 3
1/0
SEC SetC
000261 3
1/0
SEV SEZ
SetV Set Z \·"
000262 3
1/0
000264 3
1/0
SEN SetN
sec ' Set all cc \)its''
000270 3
1/0
000277 3
1/0
.Cnnfidentiahmd l?ropdetary
-
····~
Execution
()pcode Tane (µc) R/W..
NOP, (No operation)··· SPL · Set ptiqrity levelto N
MFPT MO\te&omp~sor (RO<'f't.1l0)'-
·· proccode
'
CSM' . Call to supervisor.mode
Mnemonic Instruction
. Timutg (µc};,c,·
MNo0n4eo.
Min. .Typ!
ABSD Make absolute
· 1'706fdst 23
ABSF · .Make absolute
ADDD Add
ADDF Add
.172.~):fsrc 31
CFCC. Copy floating condition eodes 170®tl\
5..,
CLRC Cleat
17-04 fdst
14
CLRF Clear CMPD Compare
1704·fdst
12
:tn{ac+ 4) 24
CMPF Compare
.-173tac+4) 18
DIVD DIVF
Divide Divide
174(ac+4) 160 174(ac+4) 59
167
Fl
63 Fl
Confidential and~aty
-
Pm1iminary
·.~iicj11:
Mnemorllc I.llstruction ·.
~~
·}.fimitlg (µc) ··Non
MocleO ·
Min. Typ. Max.
LDCDF Ld and Cfrom D to F
177(ac+4) 24
.26
LDCFD Ld.and C from F to D
117(ac+4) 20
21
LDCID Ld and C Integer to D
. 177(ac) src
31
42
LDCIF Ld and C Integer to F
l77(ac) src 26
36 .
LDCLD Ld and C Long Integer to D 177(ac) src 31
52
LDCLF Ldand C Long Integer to F . 177(ac) src 26
LDD Load
172(ac+4) 16
17
FDEXP Load exponent
LDF
Load
LDFPS 1..oad FPP program status MODD .Multiply and ~eparate
176(ac+4) .17
18
.-.... ·,;
172(ac+4l 12
l3
1701 src
6
6'
l71(ac+4) 202
217
268
MODF Integer and frf.!,ction
171(ac+4) 82
94
115
MULD Multiply
.17l(ac) fsrc 165
173
MULF Multiply
171(ac) fsrc 56
61
NEGD Negate
1707 fdst
22
23
NEGE Negate
1707 fdst
18
19
SETD Set floating double mode·
170011 .
6
6
SETF Set floating mode
170001
6
6
SETI Set integer moqe
170002
6
SETL' Set long integer mode
170012
6
STCDF St and C from D to F
176(ac) fdst 17
STCDl St and C from D to integer
176(ac) fdst 26
38
STCDL St and C fromD to long integer 176(ac)fdst 26
54.
STCFD St and C from F to D
176(l1C) fdst 19
20,
STCFI St and C from F to integer
175(ac+4) 23
35 ..
STCFL St and C from F to long integer 175(ac+4) 23
51
STD
Store
174(acc} fdst 12
12
STEXP Store exponent
175(ac) dst 16
,J6
STF· Store
174(ac) fdst
8
.... s.
.. 11\bt~
Fl
Fl
F4 F4 F4. F4
Fl
F4 Fl F4
Fl
Fl Fl Fl F3 F3
F2 F5 F5 F2 F5 F5 F2 F5
F2
Confidential and Proprietary
-
Mnemoniclnstruc~·. STFPD StoreFPPprogram status· STST Store PPP.status
SUBD Subtract SUBF Subtract . TSTD Test TSTF Test
r..-.w~>·r
NOfl
''M~eo
Min. ): r)j.
Mn;.
w~
1702 dst.
.170.l.dst
. F5
17J(ac) fstc
.Fl
173facHsn: 37.
4.l
104
Fl
uo5£dst .
12 Ft...
170:'.ffdst
10 .Fl '
The following notes refer to the sou.tee a1'ld destination tables that follow. '
and 1. Submct 2 micl'.ocy<iJ.es (J.IC) one read ~ if bOth the source and destination mOdes,
autodecrement the PC, or if write-only or read-modify-write mode 07 or 17 is used. ·
2. Read-only and read,,modify-writedestination1mode47idenmcesactually perform three REAri operations. One of the 1-tEAD opexations!s acconuted for in~ exet;:ute1;£etchtiming.
3. Read-only and read-modify-write destination mode 57 id~s actually perform four READ operations. One of the READ operations is accounted for in the execute, fetch timing.
4. Suhtl'act 1 µc if the link register is the PC.
5·. Add. l.~:i! tlie,~:~~·~i~~:~::,:
·" ~·
6. 7.
Subtrap;.~ Add 1 µc if
µtchief;~q!i~j~>nurtii:seemveond.eA'isddfl29·!~~~~;'~.
overflow
~~~;, 4.··...<. M.,.. µ.c
and
1
read.,,c,,y,cl.e....i.·,·.·f...~. ·~
PC is used as a destinationregister and!OUl'Ce Jll<?de 47 or·57 is l\~ used'.
8. Add 1 µc per shift·. ·
9. Add 1 µc if the source operand hits 15.:06 is not.zero..
10. Subtract 1 µc if one"Shiftonly.
U. Add 4 µc and 1 read cycle if the PC is used as adestination register anti source mode 47 or 57 is
not used.···
· ···
·
12. The ·diVide by zero executionti.me is 5 µc ( see Note 6).
13. Timing for no shift. Add 1 µc ih left shift.,(Notes 8; 9, 11apply;)·A,dd 2 µc for a right shift.
(Notes s.10. u apply.)
...
14. Add 1 µc if a register other than R7 is used.
15. Mode 27 references access single word operands only. The execution time listed has been adjusted to accurately reflect the total execution.till'le.
&
W:t u
1-299
...
..··.Prellininary
Source Mode 0 1
2
2 3 3 4 4 5 5 6 7
Table St· DCJUStmtce.Address Time (Double-operand) Cycle Time
:'~ ~Ster
Microcode Cr,~s
Read Memory c~.~!,'",.
2
1
0-6
2
1
7
1
l
4
2
7
3
2
0-6
3
1
7
6
21
,, 5
2··
8
f"
3'
0-7
4
2
3
',· ··1;
Table Dl · DCJll Destination Address (Read~onlfSingle~operand) Cycle Time
Destination
Destination
Mierocodb . '
Read Memory ·
Mride
Regiiiter
Cydes
''Cycles
0
0-7
0
0
1
0-7
2
1
2
0-6
2
1
2.
7
1
3
0-6
4
2
3
7
3
~ .\ ' ' :
2
4
0-6
3
1
4
7
7
5
0+6:
5
5
7
9
6
0-7
4
2
7
0-7
6
3
1-300
onfideritial and Proptietal.'y
-
Destination Mode 0 1 2 2 3 3 4 4 5 5 6 7
Destination Register 0-7 0-7 0-6 7 0-6 7 0-6 7 0-6 7 0-7 0-7
Microcode Cycles
0 3 3 2 5 4 4 8 6 10 5 7
·Bead·Memoey ;(]ydes 0 1 1 1 2 2 l 2i
2 31 2, 3
Destination Mode 0 0 1 1 2 2 3 3 4 4 5 5 6 7
Table D3 · DCJU Destination Address (Write-only) Cycle Time
Destination ~ ....... ~.. .0-6
7
Mictocode
Memory
Cy~s
~' ·--~
0
0
' '~"~ ·,' :. ~; ;,~.<
}-:·,,',
5
1
Cycles
Write
0
·O
0-6
2
0
1
7
6
1
'l
0-6
2
0
1
7
6
1
1
0-6
4
1
1
7
3
1
'1
0-6
3
0
1
7
7
1
1
0-6
5
1
1
7
9
2
1
0-7
4
1
1
0-7
6
2
1
Confidential an1.Hl:toptietafy
-
Preliminary
·Table D4 ~· OOJU Destirultion .AddreSs tR.!atl-modify·write} Cyde Titlie
Destination Mode
Destination Register
Microcode Cycles
Memory Read
Cycles Write
0
0-6
0
0
0
0
7
5
1
0
1
0-6
3
1
1
1
7
7
2
1
2
0-6
3
1
1
2
7
7
2
1
3
0-6
5
2
1
3
7
4
2
1
4
0-6
4
1
1
4
7
8
2
l2
5
0-6
6
2
1
5
7
10
3
1'
6
0-7
5
2
1
7
0-7
7
3
1
I>c}J1'
Destination Mode 1 2 3 4 5
6 6
7
Table 05 · DCJll Destination Address (Jump) CycleTtrne
Destination Register
Microcode Cycles
Memory Read
Cycles Write
0-7
4
2
0
0-7
6
2
0
0-7
5
3
0
0-7
5
2
0
0-7
6
3
0
0-6
6
3
0
7
5
3
0
0-7
7
4
0
1-3Q2
Confidential and Proprietary
...
~
OOJU
Table,1>4·· OCJll DestinationAddress.(JumP.to-subroutine) Cycle ]iaie
Destination Mode
Destination Register
Microcode Cycles
>Memory Read
Cycles 'Write
1
0-7
9
2
1
2
0-7
10
2
1
3
0-6
10
3
1
3
7
9
3
1
4
.0-7
10
2
1
5
.0-7
11
3
1
6
0-6
10
3
1
6
7
9
3
1
7
0-7
12
4
1
Tal>le Fl · OCJU Floating Source Modes 1 through 7 Cycle '(i,me
Microcode Mode
Memory .Register
,Memory Cycles
Read
.·Write
Single Precision
1
0-7
3
2
0
2
0-6
3
2
0
2
7
1
1
0
3
0-6
4
3
0
3
7
3
3
0
4
0-7
4
2
0
5
0-7
5
3
0
6
0-7
4
3
0
7
0-7
6
4
0
Double Precision
1
0-7
5
4
0
2
0-6
5
4
0
2
7
QI>
1
0
3
0-6
6
5
0
3
7
5
5
0
4
0-7
6
4
0
5
0-7
7
5
0
6
0-7
6
5
0
7
0-7
8
6
0
Confidential ~d Proprietary
1:303
-
li .. ·..Pleliminary
Table F2· OCJU Floating ~tinatiott Modes l. through 1 Cycdtt Tune..'
Microcode Mode
·Memory . Register
·Memory Cycles
Read
Write
Single Precision
1
0-7
3
0
2
2
0-6
.3
0
2
2
7
1
0
1
3
0-6
4
1
2
3
7
3
1
2
4
0-7
4
0
2
5
0-7
5
1
2
6
0-7
4
1
2
7
0-7
6
2
2
Double Precision
1
0-7
5
0
4
2
0-6
5
0
4
2
7
(-l)lj
0
1
3
0-6
6
1
4
3
7
5
1
4
4
0~7
6
0
4·
5
0-7
7
1
4
6
0-7
6
1
4
7
0-7
8
2
4
1-304
Confidential and Proprietary
-
...:n....U:...:-..... ~1...uJ.llll.UU-1
·.·imJU
Table F) d)CJ11 Flaat.inB Reaa~modify.write Modes htlUougli 1 yde ilDle
Microcode Mode
Memory .·Register
Memory Cycles
.. -Read
~:Write
Single Precision
1
0-7
5
2
2
2
:0-6
5
'2
2
2
·v
:. 1u
1
1
3
0-6
6
3
2
3
7
5
3
2
4
0-7
6
2
2
5
0-7
7
3
2
6
0-7
6
3
2
7
0-7
8
4
·2
Double Precision
1
0-7
9
4
4
2
0-6
9
4
.4
2
7
-211
1
1
3
0-6
10
5
4
3
7
9
5
4
4
0-7
10
(4
4
5
0-7
11
.5
,4
6
0-7
10
5
4
7
0-7
12
6
,4
Confidential and Proprietary
· 1·305
-
Microcode Mode
Integer
1 2 2 3 3 4 5 6
7
Long Integer
1 2 2 3 3 4 5 6 7
Preliminary
Tabt~ Jl'4co DGJ:llilnteger Sow:ee Modes.l:thtough 7 C:yde Time
Memory Register
Memory Cycles
Read
Write
0-7
2
1
0
0-6
2
1
0
7
Q15
1
0
0-6
3
2
0
7
2
2
0
0-7
3
1
0
0-7
4
2
0
0-7
3
2
0
0-7
5
3
0
'0-7
4
2
0
0-6
4
2
0
7
Q15
l
0
0-6
5
3
0
7
'4
3
0
0-7
5
2
0
0-7
6
3
0
0-7
5
3
0
0-7
7
4
0
f\''oc)U.·
1·306
Confidential and Proprietary
...
Preliminary
DCJU.
Table F5 · DCJll Integer Destination Modes 1 through 7 Cycle Time
Microcode
Memory
Memory
Mode
Register
Cycles
Read
Write
Integer
1
0-7
4
0
2
2
0-6
4
0
2
2
7
2
0
1
3
0-6
5
1
2
3
7
4
1
2
4
0-7
5
0
2
5
0-7
6
1
2
6
0-7
5
1
2
7
0-7
7
2
2
Long Integer
1
0-7
2
0
l
2
0-6
2
0
1
2
7
2
0
1
3
0-6
3
1
1
3
7
2
1
1
4
0-7
3
0
1
5
0-7
4
l
1
6
0-7
3
1
1
7
0-7
5
2
1
Confidential. and Proprietary
1-307
-
PmJiminary
· Instruction Se*·
Refer to Appendix B for a complete list of the DCJll rajo;oprocessor ins~ction set.
· Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DC319-AA are described in the following paragraphs. The test conditions used for the electrical values listed are as follows unless specified otherwise. Refer to Digital specification A-PS-2100002-GS for the general specifications for integrated circuits.
· Operating temperature (T.~): 70°C
· Power supply voltage N cc): 4. 75 V
· (V55):0V
Mechanical Configuration The physical dimensions of the DCJll 60-pin ceramic DIP are contained in Appendix E.
Absolute Maxllnum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device. Exposure to the absolute maximum ratings for extended periods may adversely affect the reliability of the device. These ratings are for stress conditions only and do not imply that the
device will function properly at these ratings or ratings above those indicated. · Power supply voltage Nee): 7.0 V · Input or output voltage applied N 55): -0.3 V, Neel: 0.3 V · Active temperature: -55°C to 125°C
· Storage temperature: -65°C to 150°C
Recommended Operating Conditions
· Temperature range: 0°C to 70°C ·Voltage range: 5 V ±5% · Relative humidity: 10% to 95% (noncondensing)
de Electrical Characteristics Table 31 contains the de electrical parameters for the input and outputs of the DCJll for the specified operating voltage and temperature ranges. Refer to Appendix C for test circuit configurations referenced in the tables and used to perform the tests. Table 32 lists the applicable de tests required for the input and outputs of the DCJll.
Co1:1fidential and Proprietary
- - - ----~--~--~--=----->'---~.~~~~
-
.·, Preliminary
·OOJU.
Symbol Vm Vn. VIHT Vu.r 11
Iui.
18ble )t ·· DCJll de Input and Output Parameters
,'.·
Pamneter
High·level
MOS input
Low-level ,'.',..
MOSmput
High-level
TTL input
Low-lel.'.'Cl
TTL input
Test
Condition
Requirements
Min.
Max.
70% Vee
Units
v
30%Vcc v
2.2
v
v
Input-leakage
OV!:!VI!:!Vee -10
10
µA
current
non-Test inputs Vcc=5.25V
Input current Test inputs
VIN=OV
0.1
5.0
mA
,,·;
Ion
Output cuttent Vour=Va:·-<MY
at high'le'llel
lox.
Output current Vam=0.4V
2.0
at low level
lom
Output cuttent VoUT=2.4V
athighTTt.
level
High level
su5tainer
current
VOUT= Vee -1.0 V -0.2 Vcc=5.25V
IoSL Low level
sustainer
current
Voor=l.OV
0.2
Vcc==5.25 V
loz
Output leakage 0 V !:!VO :!Vee ~10.-0
current'
Vcc=5.25V
lccsa Static power
supply current2 Vcc=5.25V
C.,
Input only
C'lpacitance'
mA mA mA
-0...P. mA -
0.8
mA
lQ;O
30.0 7.0
µA
mA ·pF
lfit Circuit Cl,C2 Cl,C2 Cl,C2
Cl~Gl
C3,C4
C5
Cl Cl,C2 C2
C6.
C6
CS'iC9
C7
Confidential and Ptoprletaty
J.309
-
::nr....R;.1J·lnu· naty
Symbol
Cxo c .... c ....
.P.Wneter
Input/output capacitance' Output capacitance' DCJll capacitance plus external capacitance
~t.
Condition
Units
15
pF
15
pF
100
pF
1Applies only in the high-impedance condition.
2With ~. 1fES1'2, and all outputs open circuit. All other inputs equal to Vee· 'Sampled and guaranteed, but not tested. Does not apply to TEffi. or fESfi.
Test Circuit
Table 32 · OCJll de Signal Test Summary
Type
Name
Applicable de Test
TILinput
IRQ<3:1>, HALT, PW'RF, EVENT, PARITY
DV, MISS, CONT, DMR, INIT and FPE
Vrm, V1Lr,I1
TTL output
DAL<21:16>, AI0<3:0>, ALE, BUFCTL, sc:rL, STRB, BS< 1:0 >' MAP, and PRDC
IoL> Io1m loiz
MOS input
TESTl and TEST2
Vm, TIL, IILL
MOS output
CLKandCLK2
Ion, lot,~
TTLI/0
AB'Oi'IT*
V,m IoL, lom, Ioiz, losn
TTLJ/O
DAL<15:00>
Vrnr, VILT· lot, loz loHT>
Power
Vee
leesa
*A'B'OR1.i' must be driven with lll1 open-collector driver because the DCJU has a. pullup device that supplies Iosn·
ac f:lectrical Chap.cteristics
The timing references and signal parameters of the DCJll are shown in the following figures and tables. Figure 3() shows the input and output voltage waveform characteristics. The test conditions used to perform the ac measurements follow: Figure 33 shows the output load circuits referenced on the tables and used to perform the output measurements.
Confidential and Proprietary
-
HIZ
CLK !MOS) OV (TTL)
MOS, TTL
REFERENCE
OUTPUT
MOS, TTL
(INPUT)
(INPUT)
(INPUT)
VoH =Vee -.04 VOL =0.4V td = DEL~Y TIM~
.tri =HOLD TIME
t, = SETUP TIME
ten= ENABLE TIME
tdii> = DlSAB~~ TiME .
Figure JO· DC]ll Input and Output Voltage Waveforms
Confidential and :Proprietary
1-311
-
Preliminary
vee
1K
- - - - - - - - - - - o OUTPUT
UNDER
TEST POINT
TEST
1K
SoPF
Load A-Three-state disable test circuit MA-9423
TEST POINT
Vee RL IS SELECTED TO PROVIDE
RL loLOF2MAAT0.4VOLTS
OUTPUT
UNDER o----+-_..1--_.
TEST
ALL DIODES ARE EITHER IN916 OR IN3064
-=
CLOAD = CMAx-J-11 PIN CAPACITANCE
~ B-TTL output test circuit
OUTPUT
o.o---Ii--+-----o TUENSDTER
CLOAD
TEST POINT
CLOAD = CMAX - J-11. Pl N CAPACITANCE Load C-MOS output test circuit
Figure 31 · DC]ll Output Loading Circuits
Clock Signal Timing Figure 32 shows the timing references for the dock pulses referenced in the following measurements. The reference edges are defined as·whole- and half-unit clock cycles. A whole unit is the
time between the rising edges of the clock cycles and a half unit dock pulse is defined as the time betwe~n the risi.ng and falling edge of a clock cycle. Figure 33 shows the timing references for the
clock outputs and Table 33 lists the.clock timing parameters.
1-312
~1tiVVL
T0.5 T1.6 T2.5 T3.5 T4.5
T-2.5 T-1.5 T-0.5
Figure 32 · DC]11 Clock Cycle R.eference Edges
Confidential and Proprietary
-
.rnl...'.C_tWf_!..l.l.l.l.lary
Figure 33 · DCJll Clock Output Timing Waveforms
Table~)~ DCJU Clock Output T°amng Parameters
Symbol Paiamder
·;··~1s·
Mm. . .Max.
Units
Load Refetoence Circuit1
tINITW
tSHTU.H
INIT pulse width.
Initialization interval
'"·;:··;
.. 225
dock N/A
periods
fig
N/A
fcvCLB 4:urn
ta.n
CLK cycle time . CLK high width CLK low width
67·
ns
28 ... ,............
ns
28
..,,....
ns
N/A
LoadC
N/A
LoadC
N/A
LoadC
ta
CLK rise time
tp
CLK fall time
7
~
·7
ns
N/A
LoadC
hs
N/A
LoadC
tpeyc
CLK2 cycle time
67
.ns
N/A
LoadB
tPCI.Ja)2 CLK to CLK2 high time
tPCLKH
CLK2 high width
28
ns
N/A
LoadB
tl'CLIU.
CLK2 low width
28.
tl'll
CLK2 rise time ·
tpp
CLK2 fall time
ns
N/A
LoadB
nS
N/A
LoadB
·ns
N/A
LoadB
1Refer to Figure 31 for output load circuits used for the timing measurements.
zDependent on output loading of CLK. and CLK2.
,·
'
;
)" ;<
'
'
\
Confidential and Proprietary
-
Preliminary
Signal Timing
.
The following figures show the timing references for the bus read and write transactions, general
purpose (GP) read and write transactions, and the interrupt acknowledge bus cycles. Figure 34
shows the nonstretched bus read timing sequence and Table 34 lists the timing.parameters. Figure
35 shows the stretched bus read timing sequence and Figure 36 shows the bus write. timing
sequence. Table 35 lists the timing parameters for both the stretched bus read arid bus write
transactions. Figure 37 shows the GP read timing sequence and Figure 38 show the GP write timing
sequence. Thble 36 lists the timing parameters for both the GP read and GP write transactions.
Figure 39 shows the interrupt acknowledge timing sequence and Figure 40 shows the interrupt
timing sequence. The timing parameters for the interrupt sequences are listed in Table 37. Refer to
Table 38 for the t50 and tsm parameter references in respect to the CLK signal timing shown in
Figure 39.
T2/T6 T3m TO
T1
T2
T3
TO
CLK
AIO
BS
DAL DV
Figure 34 · DCJ11 Nonstretched Bus Read TimingSequence
1-314
Confidential and Proprietary
-
Preliminary
1ible :l4. · DCJllNomttetcbed Bus Read Taming~
Symbol
"V".'.!.". tM ~-.~~ts
Min. Mu:.
Units
Load
tAJO))
AI0<3:0> delay.
DAL valid delay
T-L5 LoadB
DAL valid hold
5
tms
DAL O\iltputdisable
Load A
ns
DMiihold2
20
. n5
tos
.. DAL< 15:00 > seru,;_e 35
5·
30
MISS hold
10
.nS
PRDC valid delay
50
ns
TO
LoadB
tPm
PRDC.inactive delay
5(f .;\', ', ''illi' .
:12.
LoadB
tso
Strobe active 4elmt
35
ns
Table 38 LoadB
tsm
Strobe illactive dCiay ·
35
ns
Table3s LoadB
1Refer to Figure }1 for output load circuits used for the timing measurements. 2The serup and hold signal ~ts ensure the recognition of the nC1ci: sample point.
Confidentialand. Proprietary
1-.315
----..--------·.....------·--····--------·-------
CLK 85
·'~.~..... ~Jll
DAL DI/
Figure 35 · DCJ 11 Stretched Bus Read Timing Sequence
T2/T6 T3/T7 TO
T1 ' T2
T3
T4
T4
T4
T4
T4
T5
T6
T7
TO
CLK
AIO
PR1lc
DAL
m
STAB
BuFC'fL
,/
SCTL
- ·so
BS
BYP/FOACE
WJ'
AmmT CONT'
Figure 36 · DC]11 Bus Write Timing Sequence
1-316
.CGnfidentialand Propri¢tary
Chcuitl
tMO!I . Al0<3:0> dday
t-15 LoadB
~...
tanu .
t~
T:...J5
T:..:)5
\--··,''·''· ;
T:1,Tt:.1. LoadB
T 1.5,Tl LoadB
Tt5,T4 Load A
', ns
TO
ns
TO
-..:.
ns
MDV:L
Iis ft/. \4 -.MDV-L
15
·''·N}A
tnm
DV deassertion
0
·T65
tovs
DV deassertion
0
DV pulse width
. '35
ns
T4
ns
N/A
PROC" valid dday
50
ns
TO
LoadB
tl'fl)
PRDC inactive delay
ns
T2
LoadB
,·n&.
. . ns
''lable38J LoadB ';..: .. lable38. LoadB
1Refer t:O Figure.31 for output load dfcUits used tclr the ilitiliig·m~rne!lts: ··· · . · .· ·.·
2The setue,andhold signal~~ ensurew ~pihion~f..~.tl,~·samplt:. pcint.
C9nfideµdal and Proprietary
oc111
CLK AIO
BS
m
SCTl
A80ii'f CONT iiUF'CTI.
DAL DV
Figure 37 · DC]ll GP Read Timing Sequence
T21T6 TJ/T7 TO
Tl
T2
T3
T4
T4
T4,
T4
CLK
AIO
PiiOC
DAL
GP WRITE DATA
m
STRB
iiUFCTI
tslD SCTL
BS
M"AP
DMG
AiiORT
CONT
Figure 38 · DCJ11 GP Write Timing Sequence
1~318
Confidential and Proprietary
Preliminary
OO}ti
Tuble }6 · CJU GP Read and Write Timing Parameters
Symbol Pumleter
.. Requirements
Min.
Max.
Units
Load
Reference. Circuit'
tAllD
ABORT delay
0
>'
,. \···-- '
' ' ' ... ,,~
tABS
A.BPRT drive
30
ns
ns
T-25
tAllw
AJ30lQ' wi4~ ·
40+
tCLJtll
ns
tMOD
. A.I0<...3..:0::>' .de.lay.
Tr
ns
t.cNn
CONT setup'
30
ns
T-1:5
r:..35
LoadB
tcNm
CONT hold
ns
T'""'3.5.
tnALD
DAL \\'alid delay
65
ns
T-i,Tl.5 Load:B
tDALH
bAL valicl.hQ14 .
5
:ru!.
'.I',LtT3 LoadB
tDH
DAL<:~:()()> hOld
5
ns
T3
to1s
DAL.output disable
35
ns
·Tq~T4 Load A
tDMllS
DMRsetup'
30
tmlltH iJMRlii:M:t
iu.
ns
TO
,·
.ns
·.·ro.
tm;
PAL <15:00 > setup 35
'.P
tnvnH
DAL< 15:00 > hold
.}5
ns
MDV-L
tnvns
DAL< 15:00> setup
35
n.s
MDV.L
t o VP
DV fall time
15
ns
N/A
tnVH
DV deassertion
0
ns
T6.5
tnvs
DV deassertion
0
tmrw
DV pulse Width ·
35
ns
T4
n.s
N/A
tHMS
MISSsettip
30
., ns
T3
tmm
MISS hold
10
ns
T3
tpJ)
' PRDC ~ ck:lay
.50
ns
TO
LoadB
trm
PRDC inactive delay
50
ns
T2
LoadB
tso
Strobe active delay
0
35
ns
Tahle38 LoadB
tsm
Strobe inactive delay
0
35
ns
Table 38 LoadB
1Refer to Figure 31 for output load circuits used for the timing measurements. :rrhe setup and hold signal requirements ensure the recognition of the next sample point.
Confidential and Proprietary
1-319
,...,.,.,.......,.1'11;.it«""i(!i.S..............,,!ll!J:!.'l;.(.).1!-,!1..-..- , - ··-'lHll..........................,.!.&.Ji_~ .U.l.lJii..,,.. ....._
. . . . . ._ _ _ , __,_. _ _D_ _ _ _ _ _ _ _ _ _ _ _ _ _'~---~----- ····
CLK AIO
DAL
pv
Figure 39 · DC]11 Interrupt Acknowledge Timing Sequence
IR0<3:0> HALT,PWRF, FPE, EVENT
PARITY
Figure 40 · DC]11 Interrupt Timing Sequence
1·32.0
Confidential ariJ.Proprietary
-
Symbol
tAllD tAllS tABw
tAIOD
tcNrs l:cNm
toJ\LD
tn&w
tms tDMas tDllOIB tovoH
tDVl>S
tow toVH tovs tovw
tHMS
tHMH
tpAJlS tPAllH
tPD
tPID tso
tsm
~
DQtl
'lible 37 · DCJll Interrupt md Acknowledge Timing Parame1iers
Requirements
.· ,.,,, ~
~
Min.
Max.
Units
~ Circuit1
AlIDRT delay
0
nS
ABORT .drive ABORT width AIO < 3:0 > delay
30 40+ ta.rm
ns
T-2.;J
ns··.
.ns
T-lS LoadB
CONT setl1p2 .
30
ns
'T-3.5
C'.X5NT hold
20
ns
T-3.5
DAL valid delay DAL valid bQld
DAL output disa~,
65
ns
T-1
LoadB
-
~/
Tl.5,13 LoadB
35
Tl.5 '.1'4 Lo~d,A.
DMilsetup2
30
OS
TO
DMRhokP
20
ns
TO
DAL<15:00> hold
35
DAL< 15:00> setup 55
DVfall time
·ns 15
MDV-L MDV.L
N/A
DV deassertion
0
ns
T6.5
TN deassertion
o·
ns
T4
DV pulse width
. 35
ns·
N/A
MISS setup
30
ns
T3
MISS hold
10
ns
T3
PARI1Y setup
20
ns
Figure 39
PARITY hold'
20
ns
Figure 39
PRDC valid delay
50
ns
TO
LoadB
PRi5C inactive delay
50
ns
T2
LoadB
Strobe active delay
0
35
ns
Tuble38 LoadB
Strobe inactive delay
0
35
ns
Table 38 LoadB
Confidential and Proprietary
1-321
_.,...,,...,w__ ,..,--_:w_..,?@;,..gr""'"""'!!!1.l!.ll.el..,..1u""'\.1
i:Jl_._.,..,....,_\1miitf_,,..,,""""'"""'_,.......,.... · """"'..,,.,.-----~ -·"'_"""""_ _ _ _ _ _ _ _,__~~·------··--·-
Parameter
·Requirements
Min.
Max.
Units
Load Reference Cittuit'
tsvcs
IRQ<3:0>, HArf,
20
PWRF, FPE, EVENT
setup2
ns
Figure 41
. IRQ<3:0>, HAIT,
20
PWRF, FPE, EVENT
hold2
ns
Figure 41
1Refer to Figure 31 for output load circuits used for the timing measurements. 2The setup and hold signal requirements ensure the recognition of the next sample point.
Signal ALE STRB BUFCTL
SCTL
BS
MAP ABORT
Table 38 · DCJll tsn and tsm Parameter References
tsn Reference Edge tsm Reference Edge
T0.5
T3
Tl.5
TO
Tl.5, first T4
T3, T-1
Second T4 or T5
T-2
T-0.5, Tl
Tl.5
T-0.5
1-322
Confidential and Proprietary
· Accderates by five to eight times the DCJll floating-point instruction perfotmahce. · Improves by three to five times the system performance in floating-point applications. · Supports the complete FPll floating-pointins~onset;.
· Supports single- and double-precision :qoati'.ng-point, !lS ~II !lS 16.- and 32-bit integers.
· High-speed, double-metal ZMOS ttchnblogy. · Single 5-Vde power supply.
· Description
The FPJll, shown in Figure 1, isa very large ~cale integratiqf! (VLSI) floating-point coprocessor for
the DCJU microprocessor that implements the FPll floating-point instruction set on a single 40-
pin chip. The high performance ofthe FPJll.significantly Wpl'O\(eS the performance of computa-
tion-intensive applications.
.
·
The FPJll interface provides the al:,illty tp overlap instruction e1cCcution in a DCJll system. This ability allows the effective execution time· of floating-point ins~ons to be measured as the time required to execute the support microeooe· in the DCJll\ and .any time waiting for a previous floating-point instruction to complete.
I
I
I
I
I
I
FRAC110N COHTI'IOL
I
E;:PONENT COUTROL
I
I
I
I
I
I
_J
L__L_
1-------~-~
J----FPARDV.~
- - - A J 0 < 3 : 0 > , ADOt't<1:0> -~-Al.E:,STf'!&.Pif.iC.SCii.°
_.i----Aii'O'in'.Aci. ov
Figure 1 · FP]11 FPA Block Diagram
Confidential and Prop:t:~
1-323
This section provides a description of the input and output signals and power and ground connections of the FPJll package. The pin assignments are identified in Figure 2 and the''signa1s are summarized in Table 1.
VDD DAL08 DAL09 DAL 10 DAL 11 DAL 12 DAL 13 DAL 14 DAL 15
CLK
ffiT vss
A103 AI02 AI01 AIOO AOIJ'l 1 ADDRO INIT
SC'iI
1
40
2
39
3
38
4
31
5
36
6
35
7
34
a
33
9
32
10 FPJ 11 31
11
,30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
TOP VIEW
VSS DAL07 DALOO DAL05 DAL04 DAL03 DAL02 DAL01 ~ FPAFPE
FPAROY .~ ~
ALE PflDC STRB DV
ACK'
ABORT
.Figure 2 · FPJ11 Pin Assignments
P'm
2-9 32-39 13-16
17,18
19
Signal
DAL< 15:00 >
AI0<3:0> ADDR< 1:0>
INIT
Table 1 · FPJll Pin and Signal Summary
Input/Output Definition/Function
input/oi{tput
Data lines-Transfer data; control, and status information between the DC]ll and the FPJ11.
input
Address input/output-Transfers control signals to indic(:lte the type of DC]ll cycle being performed.
input
Address-The two least significant bits of the
DCJll address used to determine the FPJll function
during GPreaa and GP write cycles.
input
Initialize-Initializes the FPJll and clears the floating-point status register.
1-324
Coofidentialiand Proprietary
-
Pin Signal 20
21
22
23
DV
24
STRB
25
26 ALE
27
28 FPASTL
30
FPARDY
31
FPAFPE
10 11 1,29 12,40
CLK
TEST
Voo Vss
Input/Output
input
input input input input
input input
output
output
output
input input input input
~tion/FunctioQ.
Stretch control-Used to enable the samplingo~the abort condition and clear the initialization condition.
Abort_:fndieates a noncomplel:ion of the ctJtrent
cycle to the FPJUi
Acknowledge-Enables the transfer of the FPJ11
output data onto DAL< 15:00 >.
J\tl Data vaJid--: '}7~fi()u~ strobe from the sys·
teril · l:nterfa:te 1i,l~e(( to. l~tcti in,put data duri!ig stretched rea:ds and general purpose write~:
S~be-A timipg ~ign.al f~!ll tlic: DCJll used to
latch the 'PRilC input and to indicate the end of
~e.
Prec1ecQde--lndicates .that an instruction is being
decoded.
·
~ '·'' ~.
Address latch enable-A timing signal us~ to latch
the Al0<3;0> and ADDR<l:O> inputs at low-
to-higb transition and to read cache data at higb-to-
}QW .transition.
Floa~-point accelerator opexation-Asserted to
inforin the sy$tem intedaceJ:>f WJ:ite cycles that use
FPJll data.
Floating-point accelerator stall-Used to stall the
ope~tion ofthe I)CJll ~ugh tlie DMR input.
' ' ; .. ', ., ' . ~ ' ' ' .:·· .·, - .i ··..
' " '' '
'' - : d '
... ' ' ' ' -,,,
Fl~ting-point ..ai:cele~tor ~y-Indi~tes. the
FPJll output data isore\IJC,ly:for,t:m!J~r.
·
Floating-point accelerator floating-point excep-
tion-Asserted to inform the DCJll of a floating-
wU,,t ~ptio{l~tipn.
·
Test-:Used during manufacturing test only. Voltage-Power supply voltage.
Ground-Grol.lnd··reference:
Confidential and Proprietary
- - - - - -·-----·--·--------~---------------·------------~·----
l-325
-
DataLines
.
.
.. .
Data lines (DAL< 15:00 >)-These lines are bidirectional I/O lines used for data com'munication
with the DCJll.
System Control OOck (CLK)-Bask clock input to the FPJll.
Address input/output (AIO < J:O >)-The AIO < 3:0> lines indicate to the FPJll the type of 1/0
cycle as described in Table 2.
'.lkble 2 · FPJll Address Input/Output Code Assignments
AIOline
Cycle type
3
2
1
0
1
1
1
1
Non-1/0 mictocycle (Non IO)
1
1
1
0
General purpose read (GP Read)
1
1
0
1
Not used
1
1
0
0
Instruction stream read request (I Read request)
1
0
1
x
Read-modify-Write (RMW)
1
0
0
1
Data stream read (D Read)
1
0
0
0
Instruction stream read demand (I Read demand)
0
1
1
x
Not used
0
1
0
x
General purp0se word write (GP Write)
0
0
1
x
Not used
0
0
0
x
External word write (Write)
X=either 1or0
Address lines (ADDR < 1:0 >)-The ADDR < 1:0 > lines contain the two least significant bits of
the DCJll address. They are used by the FPJll to decode the type of general purpose (GP) read and write cycles as described in Table 3.
Table 3 · FPJll GP Read and Write Address Code Assignments
ADDRLine
1
0
Cycle Function
GP Read cycle
0
0
0
1
1
0
1
1
Read powerup options
Read data from the FPJll
Read powerup options and clear floating-point status register
Read floating-point exception code and dear floating-point exception signal
GP Write Cycle
1
1
Load data into the FPJll
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Confidential and Proprietary
-
Address latch enable (ALE)-The low-to-high transition of this signal is used. to latch the
information from thecA.I0<3:0> and ADDR< 1:0> lines. The high-to-low tritriSition is:usedto the latch cache-hit input data to the FPJll. The polarity of this signal is inverted from.the DCJll
output.
Strobe (STRB)-The high-to-low transition of this signal indicates the ,~d of a DCJl~ cycle.
During FPJll read cycles, the STRB signal indicates that data was loaded by either the ALE or DV
signal. The low-to-high transition is used to sample the PRDe' signal. ~ .po~rity ofthis sigfU!l is .
inverted from the DCJll output.
·
·
&edecode (Pii)C}-This signal indicates to the FPJ11 that tM: 'DCJU i{initiating ihstruction
decode. ·
·
· ,.
Stretch control {SCTt}-this signal enables.the sampling of $eAUOft'f Jme by tp.e FPJJJ.during a
DCJll stretched J/O cycle. The l0w-to-high transition of sen is'~so ~ed after the negationof the
INIT signal t6 de1tt the u}it:f~zation c0nditl6ti~ .. .... . ·· ~ , ·, .·. .·.·· .. .· .. '
Abort ·CAfi()it't)~This sigh~.if ass~ted with .tbe ~·.·siinJ!l,. Q;tffi~atJ. tO th,e FPJµ ·th,at the
current I/O cycle'will not be completed. · · ·· ·· ··..· ' ' ' ,, · ····· '. · · : · · .
Data valid (DV}-This signal is an asynchronous strobe from the system interface. The high-to-low
transition of the DV signal is used to indicate that valid data is on the DAL< 15:00> lines. The DV
signal is used by the FPJll to latch input data duringGP write or stretched FPJll read cycles.
Acknowledge (ACK)-This signal is used to enable the operation of the FPJµ output drivers. The low to high transition of ACK indicates that output data ha·s Oeen·latchecLTh~. FPA RDY signal is
then deasserted by the FPJU.
·
Initia1i7.e (INIT)-This signal initiali~ the FPJll and dear$ the~PS re~ster. ·The polarity of this
signal is inverted from the DCJll input.
· . '~
Output Signals . . . . .' .
' .'
FPA opemte (FPAOP)-This sigr)a} is asserted by the.FPJ11 t6 iQf9rm the systeminterface that data
for the next.write.cycle will be provided by ~he FPJ11. The:fl?A(jp sigtilll is valid by the assertion of
the ALE signal for DCJll bus write cydesi It is also asse~J;ed during GP read cycles that read the
system powerttp options.to indicate tp.e presence of an FPJll.iJ1.the system.
FPA s-11 (fiPA S'fC)-This signal is asserted by the FPJll to stall the DCJlt It should be OR gated
into the DCJll DMR input. The system interface must assert the CONT signal to the DCJll after
the negation of FPA STL to restart the DCJll..
FPA floating-point exception (PPA FPE)-This signal is asserted by the FPJll to indicate that the
last completed floating-point instruction had caused aq ext~.. The system interface must
assert the CONT signal to the DCJll without performing the bus write cycle. The FPA FPE signal is
cleared by a GP read operation of the floating-point exception code cycle. This cycle is described in
the architecture section.
FPA ready (FPA RDYl-:'l'his sigtl4ll is asserted.by the f PA to ~cate d1at.Putputda,~js ready. The ACK signal must be asserted from the systen:l;Q;lterface cfuring GP: read.cycles be~ore the :fPJ11 will
assert the FPA RDY signal·. l'he FPA:RDY signal may be ~ priQrto ACK fore write cy~es. The
low-to-high transition of AeK negates the FPA RDY ajgnal. It will not be reassei.-t~d until after
completion of the current write or GP read cycle.
Confidenti~ and Prop~
1-327
- - - - · ------·------·--~-----
-
Miscellaneous Ten (TEST)-....This signal is ~erved for use by the manufacturer;.·It is pulled up internally to the inactive state.
Power (V00)-The 5-Vde power supply.
Ground (V55)--Gr0und reference.
· Architecture Summary
;The FPJ11 architectural configuration, shown in Figure .3, contains six. user-addressable 64-bit
floating-point accumulators {ACO-AC05), a floating-point status (FPS) register and a floating-point
exceptioQ code (FEC). register. The FPll architecture also includes .a floatiQg-point: exception
address (FEA) registerthat is implemented in the DC]ll.
The FPJll opera~es on single-precision (F) a~d double-precisioq (D) floating-point, and 16- and 32-
bit integer data. Single-precision format uses the . 32 most sigriificant bits of the.floating-point
aceuniulators and produces ·. 8-decinial-digit precision. Double-pr&isiori format produces 17-
decinial-digit precision.
·
r------------------~~
I
·· 64.SIT ACCUMULATOR
.
... ·I
I
~
FPP
I I
32·BIT ACCUMULATOR
EXCEPTION CODE .
I
~
REGISTER
I
FPP STATUS
I I
I' REGISTER
I ACO
I
I AC1
I I I
AC2 1----t-----1
·I AC3
I AC4 I AC5
I
I
FLOAT'9NG POINT
. I
ARITHMETIC
j·
ANO CONVERSION
I
UNIT
I
I
I
I
I
L I
~o. ~~..,'..'.,O~T.!_R~e_::~
~ .J .
I
_ _ _ _ _ _ _ _ _ ;.... .
1/0 BUS
CENTRAL PROCESSOR ARITHMETIC AND LOGICAL UNIT
MEMORY
Figure J · FPJll Architectural Configuration
CPU PROC!;SSOR STATUS
CPU GENERAL REGISTER
PROGRAM POINTER
1"0 LAST
INSTRUCTION CAUSING EXCEPTION
Operational Units The FPJll consists of two main functional units. The execution unit {EB) consists'of the fraction, exponent, and sign processors, The bus interface unit (SIU} controls all interface functions between
the EUandDCJll system. Both units contain independent control sequencers that intetactto allow
possible performence impl'tivement throughparallel operationof the I/O operations in the BIU and
instruction execution in the EU.
The BIU receives all instruction stream data and decodes instructions in parallel with the DCJ11. Support microcode in the DCJll initiates all I/O cycles required by the FPJll. On completion of the support microcode, the DCJll proceeds to the next instruction. Subsequent integer instructions can proceed without FPJll intervention. For subsequent load class floating-point instructions, the
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.FPJ11
BID can support the overlap of operand data loading while the EU complet:es l!Xecuti.on of the previous instruction; For subsectuent store class floating-point instructior:t, the DQJ ll prbceeds to the bus write cycle and then waits for the FPJll to provide writ:e data or to signal an exception by the FPA FPE input.
Floating-point Data.Forrna~ . . .. .. .. .. .
.
.
.
A fioating-point number may be defined as haying the form (+ or - )(2K) x £, where K is an integer
and f is a fraction. For a nonzero numbet; K anM are determined by imposing.the condition 1h ±
< f 1. The fractional part (f) of the number is then normalized. For the number 0, f is assigned the
value 0 and the value of K is indeterminate.
The'FPJ11 floating"point data fo.rttUlts are derived from: this represenmtiort for floating-point
numbers. Two types of floating-pointd~ta are J?rovided. In s§Pe .precision, or fl~ting mOde, the
data is 32 bits long. In double precision, or double mode, the data is &ifbits long. Sign magnitude
notation is used.
·
Nonzero Floating-point Numbers
The &actional part (f) is assumed to be binary nortµ;Ji.zed, so that i~s ~t sigt:Uficai:¢.bit must be 1.
Uris 1 is the hiclcknP,it,Jt i$ J;J.Ot stored e:xpli<;:itlyjl) the cJllta V/9~, .but i.iiJ~toJ:ed:by the FPJll
before carrying out arithmetic operations. The~oating and double modes reserve 23 ~cl 55 bits,
respectively, for f.·These bits, with the ·hidden bit, imply effective fractions.of,24. bits and 56 bits.
Eight bits are reserved for storage of the exponent K in excess-128 (200 octal) notation [i.e.,
K +200], giving a biased exponent. Thus, exponents frotn -.128. to+ 127 are represented by 0 to
377 (octal), or 0to 255 (decimal). A bi~ed eXixment of 0 (thC ~ ex{,onent of-20Q octal), is
reserved for floating.point 0. Therefore, exi)onents are restricted to. the .range of .,.. 127 to + 127 inclusive (-177 to + 177 octal) or, in excess-200 notation, 1 to 377 octal.
The remaining bit of the floating-point word is the sign bit. The number is negative if the sign
bit is at · · ·
·· · · · ·
·· ·
··"
Floating-point Zero Because of the hidden bit, the fractional part is not sufficient to distinguish between 0 and nonzero numbers whosdractional part is exactly one-half. Therefore; the FPJll reserves abiased exponent
of 0 for this parpose and any floating-point number with Ii'biased exponent of 0 either traps or is treated aSif it were an exact 0 in arithmetic ()peratforis: Ari exact ofdean 0 is representeO by a word
whose bits are all zeros. A dirty 0 is a floating-point number with a hi~ expanerif of 0 and a
nonzero fractional part. An arithmetic.': operationtot which the~tingtrueexportent exceeds 177
(octal) is regarded as producing a floating overflow; if the true f!Xponent is less than -177 (octal), the operation is regard~ ~s pro#~ a;fl()~tj~µn({~~w.j\·b~,sedexpOJ'1?1t ofO can.Occur from
arithmetic operations as a special ca$e of oVerflow (true exponent=200 octal).
Undefined Variable The undefined variable is anybit pattern with a sign bit ofland a.biased exponent of 0. The term
"undefined variable" is used to indicate that these bit patterns are not assigned a corresponding floating-point arithmetic value. The undefined variable is also referred to as -0. The FPJll ensures that the undefined variable will not be stored as the result of any floating-point arithmetic instruction in a program that is run with the overflow and underflow interrupts disabled. This is achieved by storing an exact 0 on overflow and underflow if the corresponding interrupt is disabled.
Confidential and Proprietary
1-329
Floa'ting-point Data
The single- and double-precision floating~p0int data is stored in lMmocy a$ shown in Figure 4. ·
F FORMAT, FLOATING-POINT SINGLE PRECISION 15
15 14
07 06
00
l_s_.._ ·1 MEMORY+o ...
__.~-""'--"-~E~x-P___,___......___.___.......___..___~·-F_R~A-C_T_<2_2~;-16>-~--~--·....
Single-precision (F)
D FORMAT, FLOATING POINT DOUBLE PRECISION 15
00
I ··
15
00
+4 ~ .1.'.__ _ __....__..__..__,_...___~~F-R~A-CT--IO~N-<_3_1~:1~6->__..____~~~--_._--_.-'-_....:I--__,
15
00
+2 .1..·--~--~'---~--~--~--~~F-R·A-CT--IO~N-<_4_7-:3~2->--~___,____.___~--~--~---'
15
07 06
00
I_· MEMORY +0 ... _s__,,_ __...__...__.__e_.x_P_ _.__ _._~--~-...__..__F_R_.A._c_T_.<5~4-:4_B>__,,_ __._ __.
S ~SIGN OF FRACTION
EXP ~JiXPONENT IN EXCESS 200 NOTATION, RESTRICTED TO 1TO377 OCTAL FOR NONVANISHING NUMBERS.
FRACTION= 23 BITS IN F FORMAT, 56 BITS_ l_N 0 FORMAT PLUS ONE'. HIDDEN BIT (NORMALIZATION). THE BINARY RADIX POINT IS TO THE LEFT.
Double-precision (D)
Figure 4 · FP]ll Floating-point Data Formats
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·FPJn
The FPJll provides' £.c?r co~ion of &ating·po!nt t9 ~ger.format ~d integer format to
&ating.point format. The procCssot recognizes the 16-bit short integer {I), and the 32.bit long
integer (L) shown in rlglllC 5. The numbers are in two's complement format.
.
I FORMAT, SHORT-INTEGER SINGLE PRECISION
15 14
00
NUMBER <15:00>
I .
15
00
L F1O5 RMA1T4, LO...NG.-INTEGER DOU.BLE. PRECIS..IO..N.
I I MEMORHO s
I
{
.:
s D SIGN OF 1'4UMBEll NUMBllR · 15. 81.TS IN} FQRM,~J. 3t.811'UN 1. F~f\~AT.
Floating-point Status.~ ..· . .··
The &atirtg-poi.ritstatus ri!gister(PPS},
.. . . .
show!;thl
Fis.ur.e
6. ;. .C..... .d. ~. ..
. .
three
inodeci>flti'ol
bits,
five
interruptcontrol bits,· an etrt>rbit;'Md fdi.tt cB~C&dbs':'~PPS feji&ter'bitsrlitCde5cribed in
Table 4: this regiSter is cleated dUririg thJ ~p$equcnceot·fir-1t~Pread cycie: .
' ,., ·~
<
"" ' "·l -- ' ' :~ .
... ··..·...·:;·· ·. ·.·
·.MODES.·.
00 (}1. 00
F? FV:. FC
·t .
FLOATING., COOblTION cbbES
Figure G.· FPJ11 Floating-point Status. Regjstb Format.
1~331
- - - - - - - - - - - - - - - - - - - - · - - - - - - ' "--·-----------,-----·--------~--·-~--------.-...-,~-----·
-
Bit Function
15
FER (Floating error)-This bit is set if one of the following conditions occurs. The setting
of this bit is independent of the state of the FID (bit 14). Cleared only by the LDFPS
instruction from the DCJll.
1. a division·by zero
2. an illegal opcode
.
3. a £100.tlng overflow and FIV (bit 09) = 1
4. floating underflow occurs with FIU'=l\
5. an undefined variable is loaded and FIUV (bit 11) =1 6. a floating-to-integer conversion error and FIC (bit 08) = 1
14
FID (Floating interrupt disable)~\Vhen set, all floating-point interrupts are.disabled.
This occurs on .an attempt to divide by zero or by the detection of illegal opcode.
13,12 RAZ (Read as zeros)
11:08
Interrupts-Initiates interrupt requests as follows:
Bit 11 FI!JV (Floating in,tet'l'llpt ~~undefined ;variables)...,.-When set, an interrupt OCCurS if
FID (bit 09) is dear and a -0 is obtained from memory as an FIUV operand for an ADD, SUB, MUL, DIV, CMP, MOD, NEG, ABS, TST, or any WAD 'instruction. The FPJll performs an interrupt before the execution ori all instructions. Note: The FPJll instruction set is interrupted affer the ~t.ion of NEG, ABS, and TST instructions.
Bit 10 FIU (Floating interrupt on underflow)-When set and the FID (bit 14) is dear, a
floating underflow will cause an interrupt. The fractional part of the result of the
operation causing the interrupt will be cdrrect. The bi~ed exponent will be too large by a
value of 400 {octal), except for the special case of 0 in which it is correct. If cleared and an
underflow occurs, no interrupt occurs and the FPJll returns exact 0. .
Bit 09 FJV (Fl~ting itl1Xm'UPt 9n overflow)~Whenser and FID,Cbit i4) is. de:~> a
floating pverflow will cau.se an io,ten:u,pt;., :rhe f~qtioq~ part of the result of.the q)'.)~tion
causit}g t~overflow will be correct. The b~ed exponent will he ~mallel," by a value of 400
(octal).
Bit 08 FIC (Floating interrupt on integer conversion)-When set and FID is cleared, an
error in .the conversion to in,teger instruction will cause: ah interrupt. The FPJll .returns
zero exact zero. When cleared, the ecact is return~ on a conversion to integer error but
· n«Yinterrupt will occur. A floatinft"to·integer mode conkrsion error occurs when a result
is no!: representable in the integer format specified by the Ft (bit 06).
07:05
¥.ocl,es...;...Spec;:ifies the modes as follows:
Bit 07 FD (Floating double precision)-Determines the precision that is used for floatingpoint calculations. When set, the doubll\!·precision mode is used. When cleared, the
single-precision mode is used.
Bit 06 FL (Floating long integer)-When set, the long integer format is used (32 bits). When cleared, the integer format is used (16 bits).
Bit 05 FT (Floating chop)-When set, the result of an arithmetic operation is chopped
(truncated). When cleared, the result is rounded.
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Bit Fufictiotl
Bit qJ FN (Floating ~egative)-Set if the result ohhe last fioating-poiht openttlbh W'a$
negiit:ive;''
· · · '·'
: ,:,/'..,,,
. ,/': · · '
si1otJ?z·~~· ~)., ,setg th,~,~~i,'..of ~~~. ~~rt~~~~t<fe~ti~~u~.
Bit Ot ~0~~!~·~h-~t if ,~e.~t fi~t~--P9~.o~~i~Q,~µl~Jp,im
exponent uvenww.
Bit 00 FC (Floating carry)-Set if the last floating-point instruction was a conversion
rbe from double/floating to integer/long in w~, t~ ~£,:WM,:~J~>~~qJ~x~
integer forJl1at specified by FL {bit 09).
· '
· '''ii
'
' ·'"I
·
Floating-point E~Code·.ad·~·~· . One interrupt vector is assigned inDCJll systems for all floating-point exceptions (location 244). A code for the six possible error conditions is contained in the 4-hit floating exception code (FEC) i:egister shown in Figure 7. Tuble 5 lists the code and error conditions.
Q
- - - ERROR cONf:ilrtbNcooe Figure 7 · FPJ11 Floating Exception CoJe;·R:egmer.ft>mutt·
Table !'j · FPJU Floating EKeption Code Register Description
Bit
Description
3 :0
t;.n octal''?cJe
:~~·.
tha:t
: defines iHlb~i: ~oridiii&ti ~qm~i/'.
A:f':lci.t~:',
.
2 ·.
floatitigopepde¢ROr ·
4
Floating divide py~··
,
6
Fk>ating:.t<>;.integ~ m-·dPuble~to-lnteger. gmversi1;'m error.
8
Floilcitlg overfl~:'
10
Floating:unclerflow
12
Floating undefined variable
1-3.33
__________ __ ---· .,_,,,..,,_
. ~-·-~-~---,.~-
-----~~-
-
A copy of the FEC register, which is updated during exception servicing, is located in..the DCJJl.
The address of the instruction producing the exception is stored in the floating exception address (FEA) register. The :FEA register is located in the ocJll and updated by DC]ll microcode. Therefore, the store status (STST) instruction does not require an outpudrom the FPJll a.nd is
execu~ entirely by the DCJll. The FEC and FEA registers are updated under the same conditions that cause the FERbit to be set. No instruction isprovicled for. writing into the FEC and FEA regist~rs. The FPJll does not assert
the FPA FPE signal until after the next instruction deco'de. A store status (STST) instruction may
not renirn new values·of the FEC and FEA registers for the immediately preceding floating-point
instruction.
· Floatirlg-point Instruction Addressing
Floating-point instructions use the same type of addressing as integer instructions. For addressing modes 1 to 7, a source or destination operand is specified by designating one of eight addressing modes and one of eight general registers. For addressing mode 0, floating-point operands are located in the specified floating-point accumulator (ACO-AC5). Integer operands are located in the
general register file of the DCJll (RO-R7). Table 6 lists the ad~ing modes.
Mode
0 1 2 3 4 5 6 7
'Thble 6 · FPJll Adchessiog Modes
Description
FSRC/FDST: AC0-AC5; SRC/DST: RO-R7
Deferred Autoincrement Autoincrement-deferred Autoincrement Autoincrement-deferred Indexed Indexed-deferred
The autoincrement and autodecrement modes operate on increments and decrements of 4 for F
format and 10 (octal) for D format. In mode 0, users c~ make use of all six floating-point
accumulators (ACO-AC5) as their source or destination: Specifying floating-point accumulators
AC6 or AC7 will result in an illegal opcodetrap. Inall other modes that involve transfer of data to or
from memory or the general registers;· users are restricted to the first four floating-point
accilmulators (ACO-AC3). When reading or writing a floating-point number to or from memory, the
low memory word contains the most significant word of the floating-point number, and the high memory word contains the least significant word.
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Accuracy An instni~on or operation is ~arded as ''exact" ifthe result is identical to an infinite precision calculation involving the same operands. All arithmetic inStructions treat an operand, whose biased exponent is 0, as an ex:act.O unless FIUV (bit 10) of the FPS. is set and the opera.ndis .... 0. A zero operand implies that the result of an arithmetic instruction is exact except when the operand is the divisor for a DIV instruction. In division, if the divisor is 0, the reslllt is uridc!!fined and an interrupt occurs if FID (bit 14) is cleared;
For nonzero floatlng·pofut operands, the fractional part is binary normalized. lt1Z0ntains 24-bits
returtl for floatirig mOde and 56:.bits for double mode: For ADD, SUB, MUL, and DIVinstructions, two
guard bits are necessary and sufficient for the general case to assure the
Qf ii. chopped or
rounded result identical to the corresponding infinite p~iono tion cl:;ippped er rotilided to
the specified word least significant bit
length. Thus, with two guard (LSB); a rounded result has an
bits, error
a chQp
bound
o.·.·f·'on.e-.h. falhfaL1S1B·. aTnh~ersebe9~lrl1orldb6o£unodnes
are realized by the FPJll for a1Hnstructioris.
The occurrence ofa floaruig-~int o~fl0w and ~derflow causes an error condition; the result of
the calculation cannot be correctly stored because the exponent is larger than the eight bits
reserved for it. When an underflow occurs, replaq!ment of the correct answer by 0 can resolve the
problerq' for many applications. This is· l'erloriried ·by the FPJJll. if the underflow interruptis
disabled; The error ~&tred'bythis actio# ls an abs'Olute rathett~ a telati\ie error; it is bounded
(in absolute value) by 2~1u (decimal); For the ciise' of civerfloVI, 'if'~ ~rfl0w interrupt is disabled,
the FPJll returns exact zero.
J>!
The FIV (bit 10) and FIU (bit 9) of the FPS register provide users with an opportunity to implement
corrections of an overflow or underflow condition. The FPJll stores the .correct fractional part and
the low eight bits of the biased expolient'lft.er floating overffuw<lr underflow if the corresponding
interrupt is.enable,d. The cause of tlie interrupt c~ be id~~ifiedby exa1TM.A~tfon of thefk>ating
overflow FV {bit 1j of the FPS register or the floating exception register (FEC).
.·. ·
an The biased exponent returned by the instructiO~'is related tti1the correct exponent. On Q'ICrflow,
it is smaller by 400 (octal) and on an Wlderflow, ihhe Sfased exponent is O; it is correct. If the
bia8ed exponent is not 0, ids larger by ~,qq (oetal).
Users may rescale their variables using STEXP anc,l ~D.EXP instructions to continue a calculation.
FL>at:ing·pc)int ~s
... . , .
.·. , .
. . , .· · .,.
Floating-point instructions.operate on either single,, .or double-pre(:l.sion numbers, depending on
the status of the FD mode bit 7 in the FPS registe1::Simiiarly; the FL niooe bit determines whe~r
32-bit or 16-bit mtegers are used in co~rsions Pe~ integer an4fl.9at~i;ioint rep~entation.
The floating source (FSRC) .~,floating destinati~n (FDST) use floating-po!nt·addres~ modes,
while sRC and DST use CPU addressingfl!odes. Tfie FP instructioti.forrtiats for single- and double.i
operand addressing are shC!'Wn in Figure 8;
m The six floating-point accumulators are used in numeric cakµIations and int;eracc\lrim!atot da!=S are transfers. The first four accumulators (ACO-AC3) alsri used for alldata transfers between the
FPJ 11 and the general registers or memory. ·
. ·
·Confidential and Proprietaty
1-335
·----·---·~---~----·--'-
DOUBLE-OPERAND ADDRESSING
15
,- .
FOC
!'
08 07 00 ··os
AC
.FSRC,FDST,SRC,DST
00
t
SINGLE·OP~RAND ADDRESSING
15
12 11
FOC
QCzOPCODE=<17 FOC =FLOATING OPCODE , 'AC'= FLOAitNG POINT ACCUMULATOR (ACO.AC3) FSRC ANO FDST USE FPP ADDRESSING MODES
SRCAND DST u.sE CPU ADDRESSING MODES
06
05
FDS~ : FSRC, I
00
SAC, DST
I
Figure .8 · FP]ll Single- and Double-operand Addressing Instruction Formats
. .
.
-
The instruction set for the FPJU is listed in Table Y. A. detailed deso-iptfon of eachinstru~ion as
well as specific comments on aCClJt!lCY can be found in the DC]ll Microprocessor User's Guide.or the
PDP-11, Architecture Handbopk, The condition codeJormats for Table, 7 are: * = Coµditionany set/
cleared, - =Not affected, 0 =Cleared, 1=Set.
·
Table 7 · FPJU Instruction Set
Mnemonic
'Opcode
Instruction
ABSD,ABSF. 1706 fdst
Make absolute dbVfl
ADDD,ADDF 172(ac)fsrc
Add dbl/fl
CFCC
170000
Copy condition codes
CLRD,CLRF 1704 fdst
Clear dbl/fl
CMPD,CMPF 173(ac+4)fsrc Compare dbl/fl (to ac)
DIVD,DIVF 174(ac+ 4)fsrc Divide dPl/fl
LDCDF, LDCFD 177(!1.c+ 4)fsrc Load and convert dbl-fl/fl-dbl
IDCID, LDCIJ:" 177(ac)src
Load and convert integer to dbl/fl
LDCLD, LDCLF 177(ac)src
Load and convert long integer to dbl/fl
LDD,LDF ' 172(ac + 4)fsrc Load dbl/fl
LDEXP
176(ac+ 4)src Load exponent
LDFPS
1701 src
Load FPJll program status
MODD,MODF 171(ac+4)fsrc Multiply and integerize dbl/fl
MULD,MULF 17l(ac)fsrc
Multiply dbl/fl
FN FZ FV FC
0 *00 * **0
01 0 0
**0 0
* **0
* * * 0
* * 0 0 * *00 * *00 * **0
* **0 * * .* 0
1-336
Confidential ·and Proprietary
Pteliminary
'RPJll ',,i· ., ,. '.:
Mnemonic
Opcode
' .:lristruction·
FN FZ FV PC
NEGD,NEGF 170Vfdst
Negate dbl/:fl
* *00
SETD
110011
Set floating double mode
SETF
170001
Set floating mode
SETI
170002
Set integer mode
SETL
170012
Set long integer mode
STCDF, STCFD 176(ae)fdst
Store and convert.fromdbJIEl to£l/dbl * * *" 0
*' STCDI, STCDL .17S(ac+4)dst Storeandconvertfromdblt0int/longint * * .0
* STCFI, STCFL 175(ac +4}ds.t Store and cotll.Tett from fl tojnt/long.int * * 0
STD,STF
174(ac)fdst
Store dbl/fl
STEXP
175(ac)dst
Store exponent
* * Q. 0
S'J.'FPS S'tST SUBD,SUBF TSTD,TSTF
. 1702dst
1793 dst·
· 17'.;(~)fsrc
';F05fd' St
Si t~ore' F' P,,Si Store FEA andi"EC Subti:aci: d~fl
Tce'st.d..b)/£,,11,
.-· ·,·,,
* )k' '
~
0 ,,,,
* * (f 0
Perfumtance
The combination of a fast internal cycle and optimized arithmetic algorithms pfo\tidtes'. ~ent
performance for. the FPJ1k In addition; ~n pverlat) ·~es ~substantial performance
gain in floating-poindntensive oode: The bus interface unit (BJUl4'upportsthe Qlierlap .of operand data loading for the next·floating~point in~mction .wbile.,the.texetutic~pniit'~U) completes· the
processing of the current instruction. The effective execution time of a floating-point instruqion. in a DCJll s,y&tem.~ Qqly~~e~esreq~to{!X~ ~~:S\l~~ mi'!!gcpd<;.~d~tirJM;
waiting fo.- tli.e FPJ11 t() complete ap~~ flooti~,po.ir+t ~trµd;iQt\~ T4eref9fe, only a portion'9f
the FPJll instruction execution contributes tqf~ ov¢ttill't:>tb~~~tion:i~.
As acoproceys.o; .floa~g:poiµt instru¢ol'l ~e<;utiQti<;~@f~J1j411tdtan~ly,'W~~l,1)ntegercode.
This overlap Cat\:be U$ed e,ffe1;tively to reduc~ the ~ecur~n tjnle or,c94et~th,l~*IM;S fl9ating-
point and nonfloatj.ng~poin~ ~°*1-lctions.
.
.. . ·
, ...
Table 8 lists.·ecycle counts ~J~ rnqstfroouen,tFPJll ari~it<;>perations. Cycletin:lecan be
deterrniqed 11s twice the input dock ~iocL ,'·
·
·
Cenfidential;and Proprietary
1-337
1111111
Instruction ADDF/SUBF MULF DIVF ADDD/SUBD MULD DIVD
Preliminary
Table 8 · FPJll Instructioo.E~tion Times
Minimum Cycles
Typi<:al Cycles
7
9
15
15
2.0µs
19
26
3.5 µs
7
9
1.2 µs
26
26
3.5 µs
35
45
6.0µs
·Interface
The FPJ 11 supports a coprocessor jnterface with the DCJil. All bus cycles are initiated by the
DCJll. The AIO < 3:0 > and ADDR < 1:0 > lines fully identify the type of bus cycle to the FPJ 11.
The FPJ11 loads all instruction stream data into a prefetch buffer. The DCJH asserts the PRDC ;line
when decoding instructions. PRDC is never asserted unless the prefetch buffer is valid. Floating·
point instructions (opcode 15:12= 17) begin executi(jn in the FPJll in patallet with the DCJll.
For instructions requiring data from memory, the DCJll executes the bus cycles necessary to fetch
the operands. The DCJll then continues to the next instruction after checking for a FPE from a
previous FP instruction. For register mode instruction, the DCJll continues to the next instruction
immediately after, the FPE check.
. ..
The FPJll outputs data only during store type instructions. Otitput data is supplied by the FPJll
during write cycles and GP read cycles as required. The FPJll may cancel an output cycle by asserting the FPA FPE signal if the ·previous floating-point instruction caused a floating-point· exception.
The' FPJll asserts the FPASTh line when executing a floating-point instruction that does not output data if the execution unit is still busy with a previous instruction. Thi! FPA STL signal is
asserted before the DCJll test for the FPA FPE signal.
The timing and systeminterface requirements for read, write, GP read, GP write, and the FPA stalls are described in fhe follo\ving sections. Refer to timing diagtams Fig1.1res 11 through 15.
An STF/D, STFPS, CFCC, or STEXP to memory instruction should be executed as the firstfloating-
point store instruction after the powerup sequence to initialize the FPJll. This initialization is performed automatically by all Digital software operating systems except MicroPower/Pascal.
Instruction or Data Reads The FPJll inputs read data on all instruction read cycles and data read cycles that are fetching FPA operands. Data is loaded at the high-to-low transition of the ALE signal for cache hits and again at the high-to-low transition of the DV signal for main memory reads. The FPJll uses the high-to-low transition of the STRB input to determine the end of the read cycle. It does not require cache hit/ miss information. The system interface read sequence is not altered by the presence of the FPJll in the system. If the ABORT signal is asserted during a demand read cycle, the FPJll will abort the present instruction.
1-338
Confidential and Proprietary
...
FP.JitW·~ .
. .
. . ... ;
TheFPJ:\l assett'S ~e mc>P.lineprior to the low~to-high transition of the ALE signal for all DCJll
buswritecycles~datafrom.theFPJll.Thisinformsthesysteminterfa<;e-~t.the,~tedata
is to be supplied by the FPJll. The system interface can assert the ACK ~ ~tely ~pon
recogni;i:ing a :Ff>Jll write cycle. The. ~serti9n of ACK enables ~e FPJll Ol)W1Jt dri~·
The FPARDY signal is,~erted to indi~t~ that ~~~daO\is ~~~-to·~Qtj~ . .. L~ ~:OQ>.
The FPA ROY signal will not be asserted prior to ~~·1P""~·~~ponq~ .
sign~~pr a
FPJll write. The system interface is required to wait for the FPA RJJY signal before continuing the
bus write cycle. There is no required precedence between FPA ROY and~ signals £~.ht.1$: ~~
cycles. Outing GP n:ratJ~st,~ i:4e sy~i9ter£ase rn!:ISF ~···~~~!gnat bef~l:he
FPJll will ~sert the.FpAR01{.si8naL_.~ FRJ11.oµ~µt··data,~ya,lkl wi~.to111 ·.~_¢;~
assertion of.the,FP41UlY ~ ot '\1rlthiti t()J!,ti~·ut~ ~s~oJi of~~ ~~? w!Uch~ is
longe:c After recognizing the FPA RDY signal, the system interface lat~ t:pe JilPJ.l:+·<QUtput .~a
and then deas~s ~-A<'.!((1:i11C· Th,t; l1PJll ~o~,PC)~ !1s~.-~,h9ld.~e a~~t~·~tion pf · Ael{. l}pon deteci:i9n-~ ~ lmr·to~~ tpmsi~i9~ o,f~.jJ1e ~J1l~~ftft~·ilie F~AJIDY ~'.
to The system interface compfetes the bits write cycle with the latdkii FPJll qu~~t dalll: apd ~s
the CONT signal the,DCJU.Jf more thap on~ word of output data is ~quited, the sanie·sequence
repeats fore~ 16.hi!' word of outµut data. · ·
· ' · ·' · ·
·
·wm If the. previous Uis~on ~~ ~ floiitU,ig-point ~P~Qn·.t~'~ril;i as5ert tl,i~ F~A .FPE
signal and not FfA: $ di.uin8A1e FPJlJ bQs }Yrl~ .~l!··. t.£ :~ ~fit!~ l!i~ ~-~r1:tl<:i? the
system interfll(;e... m9st asSt<:rt o:mT tO·the l)GJU ~cl not'p~rfo~~~ wtj.~ o~Jon~ in,e._:!Xlory.·.
O-; - --
' .. ·
.. - .
-' . - ..: - - -: ' '.-· · ;~
' -; . ·'/: .' ~ ,-· ': .· ' · , L .'.· .
.''>ff- .- >"
' ')
GP Read Ttansac.tions
The general purpose (GP) read cycle is used by the DCJll to transfer data from a system interface
register or the FPJll,, The AD.QR< l;O> bits ~~es~ f9i:.~~JU fo~tinguish ~ ty~ ~f
Gp read cycle b~g ~ortnec!. -The fottt ~ypeso£ GJ? ·react ~st,?llt ~ ~~zed,?y.~h~fPJ.ll
are ~scrib~ in the follmving paragraphs..
GP~ad ~~.(~Q~<J,;0 > ."10)~J)µfa,ngthe.GP 1.~.dcyele.0£ .·~ pqw;e~}'optjons~
the. FPJU will ass~t :the· J?PA p;p ,sigrud,. indic!ltiµg t~ pre~rice, Q~; t4e FPJ11.· if) the system
configuration.
GP read floating-point condition code$ ot tt;..'bit·data: (ADDlt-<:hO>:i!i<t)._Dw!ing the;Gp read cycle of the floating.point oo.(ldition codes (FCG) or 16·bit -d.ata,11:lie·s.ystemcintcrfare~s both
the DV and ACK signals and waits for theFPJ1h.o assertthe FPA!U;)Y·signahACK·mt1$t be asserted
by the system interface before the FPJll will assert FPA RDY. Upon recognizing the FPA RDY
signal, the system interface de.asserts DV, strobing the FPJll output data in~~l)CllL. SetJ,!p and
tlit; hold requirements wi~h respect to FPARDY si~~ and M,=K. sig~l for ppJU output data. are
identical for GP reaa and bus write' eycles. After th~ 'ta is' la.tChed,' th¢ system int~~c~..inay
deassert AC:K, causing FPJ11 output drivers to beCotne.a ~ impe'&irice.. The FPfll'Wilrth~n
deassert FPA RDY. If FPA FPE is asserted instead of FPA ROY, indicating a floating-point exceptio!l~
the FPJ11 will transfer a floating-point exception code. The system interface must still complete the
bus cycle but the DCJll will not use the data. A subsequent GP read transaction to the FEC register
will occur to read the register again and clear the exception condition.
GP read powerup options and clear FPS register (ADDR < 1:0 > =2)-During the GP read cycle of
powerup options and to clear the FPS register, the FPJ 11 will assert the 1iPK01? signal, indicating
the presence of the FPJll in the system configuration. The FPJll will also dear the FPS register.
The G command in the ODT command language causes this cycle.
Confidential and: Proptie~
-
reaa GP J:ead floating-point exception code (ADDR < 1:0>= 3)--The GP rea#.cyele 6£. the £!°'~ting·
fioint eiception Code (FEC) operates fu the sam~ nianner as the GP of FCC or l6·hit data cycle.
to The FPJll deasscrts the FPAFPE signal aanowledge the servicing of the FPE at the I0w-to·hlgh
transition ofSttB input.
GP write (ADDlt'< 1:0 > =3)-The GP write cyde withADDR< 1:0 > =3is used by the DCJll to
write mode 0 integer source data to the FPJll. Setup ·and hold requirements for the data with respect to DV is identical to thafof a data read cycle.
DCJll Stall The FPJll asserts the Ff>A STL signal when exeo.iting a· floating-point instruction that· dbes·not
transfer data if the EU is still busy with a previous instruction. This signal is asserted prior to the
DCJU test for afloating-point exception. The FPA STL signal is also asserted to minimiz'e DMA
latency in a OCJU system.
stt The. FPA signal should be OR g~ted ii:Jto the DCJll DMA request (i.5MR) input. The sysrerrt
interface must assert the CONT input to the DCJ11 after the negation of FPASTL to restart program
execution in the DCJ11.
.
There are two cases when the FPJll will assert the FPA STL signal. The FPJll does not maintain a
copy of the virtual ad~ss of the executing instruction. Therefore, the DCJll maintains the floating-point exception address register. The DCJ1l microinstruction sequence determine~ the
extent to whkhfloating-poiniinstructions can be overlapped. The DCJll can be allowed to oVerlap
execution of a sribsequent instruction only up to a point of the floating-point exception check. The
FPJll monitors DCJll microinstructions and always stalls the DCJll while allowing .a maximum
overlap.
During· FPJll load class instructions, this overlap allows the DCJll to complete data fetch operatiohsfor a subsequent instruction before it: is stalled by the FPJll. The effect of load class overlap in floating-point intensive code is significant when much of the data is located in memofy.
The FPJlhlso asserts the FPA STL signal to limit the worst case DMA latency of the DCJll 'syscem:
within The system interface cannot service DMA requests while waiting for FP}ll data
a \vrite
cycle. The FPJll will assert this signal prior to the write cycle allowing the system interface to
serviceDMA requests if FPJll output data will not be ready within worst case DMA latency time.
This condition can occur only if the execution.unit is executing a previous MOD or DIVD
instruction when the store instruction is decoded by the DCJll.
· System Configuration
A typ,ical DC]11 system configuration with the FPJ11 and cache memory is shown in Figure 91 In a single,bus system confi~tion, the ADDR< 1:0> li,nes would be connected to DAl<Ol:OO> pins.
1-.340
Confidential and Proprietary
AIO < 3:0 >, PRDC, SCTL
DCJ11
INlT'
Ai!ORT,ov
FPJ11
FPA ROY f PA OP
Ac'K
<21:00>
. figure 9· FPf11 TypicalSystem Configura#on
· Specifications
The mechanical, electrica1, and environmental characteristics.and spec:i£i~atldfis£ortheFPJ11 . are descibed in the follm.ring paragraph~. Th~ t~t conditioriSJ~t the' electrlCal values:~ as follows
unless specified otherwise.
· Pcrwer supply vol~ (\700}: 5.0 V ±0.2 V
· Temperature range (TJ: 0°C to 70°C
· Ground (V55): 0 V
Mecbanica1 Configut'8tron The physical <limeri§ions of the FPJll 40-pin package. are'~()QWged i11 Al>J?C~ E.
Absolute Maximum Ratings
S~ssesgreater than ~absolute maximum rating~ ~c~u~e· permanent.~~ tc,> the device.·
Exp0sure to the absolute maximum ratings for exten&H periods ma}' adversely affect the
reliability of .the device.
.
· Power supply voltage Noo): 5 V ±5%
· Input voltage appliedW18): -1.0 V to 7.0 V · Power dissipation: 2.~. W
· O~ting temperature (TA): 0°C to 70°C
· Storage temperature: - 65°C to 150°C
H41
-
· .r::aOJ.....o..;·;.:·a,:·..·u..u.M&IA'nA-I.TJ'
Recommended Operating Conditions
· Power supply voltage (VDD): 5 V ± 5% ·
de Electrical Characteristics
The de dectrical parameters of the FPjll for the operating voltage and temperature ranges specified are listed in Tuble 9.
Symbol Vrn V1uc VIL Voa VoL
IIL liu
Ion
~
ITST
loo Ca1t"
c;,, * c_·
Cm*
Table 9 · FPJll de Input and Output Paramei:ers
Parameter
Test Conditions
Requireinents
Min.
Max.
High-level input voltage
2.0
7.0
CLK high"level inputvoltage
2.4
7.0
Low-level input voltage
-1.0
0.8
High-level
lou=-1.0mA
2.5
output voltage
Low-level
IoL=4.Q mA
0.40
output vqlt:a&e
Input-low
V.,=OV
±10
leakage current
Input-high
V;.=5.0V
±10
leakage current
Low three-state
leakage current
V,.=OV TEST=OV
±100
High three-state
leakage current
I
.
TEST short
circuit current
p~~pply
current
V.,=5.0V TEST=OV TEST=OV
VnD=5.25 V
±100
0.3
1.9
500
CLK capacitance
fc= 1 MHz. All
5.0
unmeasured pins
Input capacitance
returned to GND
5.0
Output capacitance
10
I/O capacitance
15 .
Units
v
v
v v
µA µA µA mA mA pF pF pF pF
1-342
Confidential·and Proprietary
-
fo aTchEe clloeckciAtArutiwacV~afolr~.~a~J).4 timing symbols are shown in Figure 10. Table contains the timing
signal definitions end parameters for the clock input. Thetcu:a width is measured at 2.0 volts.
Figure 10 · FP]11 Cltxk Input Timing ·
.,,(
·:r-
Figures U through 15 show the signal timing an&symbo~.f~'.the fOllowipg~Afloating-point
accelerator operation are shown in Figure ll. Figure ·12·~.the ~~~during FPA siall conditions. Figure 13 shows a t:!!ad and cache hit tranSli!~~;· F~ llhhO\vs a:genl!ral purpose
write and stretched read transaction. Figure 15 shows a write operation with the RDY signal asserted before the assertion of the stretch control (SCTE) signal and a write and general purpose read operation with the system interface waiting for the RDY signal from the FPJll.
The timing symbols and parameter definitions for the figures are listed in Table 10. The following
specifications.apply~
Symbol
Definition
Acknowledge response Cache data hold Clock fall time Clock high width Clock low width Clock rise time Clock cycle Delay time FPA STL, FP.AOi5 Assert time FPA FPE, FPA RDY DVfall time
Requirements (ns)
Min.
Max.
60 7
15
T/2-3 T/2-3
15 T
2T
50
20
Confidential and Proprietary
1-.343
...
,·Preliminary
Symbol Definition
toVH toVPW toVR tmPM tms tra t15 tuoL v
fooH
t6ov
DV data hold time DV pulse width DV rise time Input data strobeto STRBor PRDC Input data setup time Input hold time Input setup time
Last read delay to FPA STL Output data hold time ·output data valid from: FPA ROY
Output da~ valid from ACK
Re<(Uitement5 (11s)
Mm.'
· Mu.
25
50
20
4T/5 40
25
T/2
3T/2
0
90 75
CLK
DCJ1T MICRO INST
FPAOP
REAQ
STRB \ , __ ___,/
AODF\~SS RELOCATE. ,
,___/
Figure n ·FPJ11 FPA Operation Timing
READ
\._______,/
1·344
Confidential and Proprietary
CLK DCJ11 MICRO INST
STRB
CLK OCJll MICRO INST
STRB
LATCH PAOC
ENO CYCLE
STALL DCJ11
FPA Stall by Register Mode Instruction
ENO CYCLE
STAB ASSERTED
STALL OCJ11
FPA Stall after Overlap of Operand Fetch
Figure 12 · FP]11 FPA Stall Condition Timing
CLK
AI0<3:0>
AODR<l:O> --·,'---1~--','------------'"'-+--..J'----------
DAL< 15:00>
OATA
ALE
STRB
LATCH AI0<3:0> ADOR<1:0>
LATCH DAL DATA
ENO CYCLE
Figure 13 · FP]ll Read and Cache Hit Transaction Timing
Confidential and.Proprietary
1-345
- - - - - - - - - - - - - · · - ----------------·-·-----~--
-··-----
CLK
AI0<3:0> ADDA<l:O> DAL<15:00>
ALE
\···.Preliminary
DV
LATCH AI0<3:0>
AD'DA<l:D>
LATCH DATA
Figure 14 · FP]ll GP Write and Stretched Read Transaction Timing
END CYCLE
1·346
·Confidential and Proprietary
CLK
Al0<3:0> ADOR<1:0>
FPJU
tooH
ALE
STAB
,,..___... -
---+-----------------\"9---'o·
AC<
LATCH Al0<3:0> ADOA<1:0>
SAMPLE F'fiAOP
ENI.ABLE OUTPUT DRIVERS
VALIO l)ATA
Writes with FPA RDY Asserted before !Cfi::
\
tACK I'""",'-------
CLK
~ - AIO<J:O>
AODR<l'.0>
x
0Al<1!>:00>
ALE
\
STRB
J
J
LATCH Al0<3:0> "°°R<1:0> SAMPLE~
r }. DATA
F too·-
\
L
\
.t
ENABl..E OUTPUT
DRIVERS
'o·--jlv:!~:::. 1oov
'o·
- ,---
/
.\. ----
r L '..:·
r-
VAUO DATA
Writes and GP Read with Systetn Interface Waiting for FPA RDY
Figure 15 · FP/11 Write and GP Read Transaction Timing
Confidential and Proprietary
1-347
· Basic PDP-11 instruction set (except for the MARK instruction)
at · 16- or 8-bit data paths selected initi~,; ,1; tion
· Interrupts on four priority levels with 15 internally generated vectors
· Option of having the interrupt device wq~
vide the vector address
' ,·
· DMA arbitration
· Full dynamic memory support: -:-R~ dynamic addressing
-RA'S abd 00 sin:ibes -Refrelfh counter
-Au«>ii'atic ref~h cycles
· Progra~ble ~eregister featuring -8- ot lf,-bit ext~ data bus -Start ~d resw,rt~ss selection -Statidor dynamkJ1rem.ory support
-Stallldfatd or long·microcycles
.,-,.,Bus·s~hcluondtisor constant clock output
siw ·
Single ·'
,.
de powet~upply
'
"
·'·
· Description
a The DCTll microprocessor is PDP-11 pn:l!Cessor containedin1t 40-pin, dual-inline package (DIP).
It is available in two versions; dne"operate~ ~th a maximurl:tdhck freque'nty of 7.5 MH:t (part no.
#- 21-17311-00,01) and one operates;with a ~imum clock f~~ncy ofta:z..mz (part no. 21-17311-
02). Full dynamic memory suppi:lrc is p~iled for 4K/16f{ 64K.clji~,memory. This includes
timing strobes, dynamic ad~,51mltiple:iflng, automatic ·' cycles,'~ a refresh counter. The
interrupt is multilevel, using four priority levets·.Vectot
scan be supplied by the DCTll {15
internal vector addresses are available) or by the interrupting device. DMA arbitration is included
in the DCTll. The maximum clock freque.t\l:GY1is 10 Mlb:A~trs~are TTL-compatible. Figure 1
is a block diagram of the DCTll microprocessor.
Figure 1 · DCT11 Microprocessor Black Diagram
Confidential and Proprietary;
'
-_., , . , _ ' '
.
j
1-349
The DCTll is a 40-pin microprocessor that functions with the input and output signals described in the following paragraphs. The signal pin assignments are identified in Figure 2 and summarized in Table 1.
OAL15 · DAL14 DAL13
OAL12 OAL11 DAL1()
OAL09 BGND
DAL08 DAL07 ..·
DAL06
OALOS
DAL04
DAL03 DAL02 OAL01
DALOO l:ll\L07
.BCi:R PUP ·GNo
1
«I
2
~
3
3B
4
37
5
3B
6
36
7
34
8
33
"'to OCT11
32 31
11
3)
12
29
13
28
14
XI
15
28
16
:lfi
17
:!4
23
22
20
21
.Vee Al7 Al6
Al5 · Al4
Al3 AIZ All AIO
Pl CAS
RiiS
R/WLB
AIWHB AEAW
SELO
SELl XTLO XTL1 COUT
Figure2 ··DCT11 Pin Assignments
Pin 1-7,9-17
8
18 19 20 21
18ble l · DCTU Pin and Signal Summary .
Sign81
lriput/Output Definition/FWiction
DAL<l5:00> input/output Data/address lines_;Multiplexed, bidirectio~ data
and address lines.
BGND
. input
B Ground-A ground reference for all DCTll signals.
OCIJ.t ..
output
Bus clear-An initialization signal from the DCTll to reset th¢ system.
PUP
input
Powerup-A signalto the DCTll that starts the
initialization process.
G1'1D
input
Ground-A ground reference for all DCTll signals.
COUT
output
Clock'out-The clock output signal.
1-350
Confidential and.Proprietary
-
Pin
22 23 24
25
26 27 28 29 30 31 32-39
40
Signal . XTLl
XTLO
SELl SELO
READY
R/WHB
R/WLB
RAS
m
PI
Al<7:0>. A<17:10>
Input/Output Definition/Function
Crystal input 1-Exte+nal crystal connecticin to the
internal oscillator ··
Cijs~ jflput.Or-J;'.x~al crystal co~ection t 0 the .intern~ osc.illamr
output
Select .1-:-:-Ene<:id~ with··.the.· SELO line to indicate the,transactipl'l: bcltig pert<>:rmed.
output
Select 0-"-E'ru::o&ett:With the 5Eti' line to indicate ··the transaetiolt~ingtp'erfu:i:ined. · ·
input input output output butput output .input/output
input
Reao/write·· ~. ··~ .strobe~Provickis · read and
write contrQLto:the,$f$~' · ·
Read/write lbw. ''ffyte strobt;--Provides read and write control to the system.
Row address strobe-A system ad~~~ s~bt:·
Column address'strobe~Anaddress aricf chip St'lect
strobe.~
· ·
Priority in-The write~ in.tei:rul'i~ ~d DMA request
strobe.
·. .
·.
A.ddr~s/~ntei:rup~ ·Hi;ie~~ultipkxed, .. bidirectional lines that transfer the dynamic memory address and receive all system inter,11JPts..ani;l DMA
·requests..
Data Address and lttterrUPt 'Bhs
used . Data and address bus. (DAL< 15:00>)-:Thedata and address lines are time-mtutiplexed,
bidirectional lities
to' ttlllls{er ad~!J iftformation and i~ata:'During . read orwrite
transaction, the system addi:es's is ttiinsfehed first! followed by the dlita. The opemtiori of the bus
lines depends on the selection of the 8- or l<J-bi1tl'mode.
·
Address and interrupt lines (AI< 7:0 >)-The address and interrupt lines are biditectlorutl, time-
multiplexed lines used to address dynamic random access memory (RAM) and to r<:,eeive interrupt
and direct memory access requests. At the beginnir~g of the. bus ~le, the addte$g on ·JinCs
Al< 7:0 > is the same as the address on the DAL bus. The information on the AI lineS depends on the selection ofdynamic oi:'static RAM rtiode of operation. ·
Confidentialand Propi:ietary
l-3'51
· Bus Control
Row and ~~mn add.-ess strobe (JI.Ai !ll,ld CA~)-When dynamic RAM support is selected, the
row address strobe {RAS) and column ~ddress strqqe (CAS) signals are used to latch the row and
column address of lines AI< 7:0 > into dynamic ·memory. If static mode is selected, the RAS output is used as a system address strobe. The CA'S output can be used by the external logic in
either static or dynamic mode, as a chip select: enable signal.
During tead operations, the data on the data and address lines DAL< 15:00 > is read by the DCTll
when the CAS signal is negated. During write opeyations, the negation of RAS or CAS signals can be used to latc;h data into t:he system irlf;erface.
Read/wite high byte and low~hyte (R{WHB) and R/WIB)-The read and write high byte and read and write low byte outputs specify the direction of the information transfer on t:he DAL< 15:0 >
lines during the input or output portlpn of a read or write bus cycle. The function ~nd name of the ~ and write Unes depend on the selection of 8~ or 16-bit data bus mode.
Select 1 and 0 (SELl arulSELO)-These lines ate encoded by the DCTll to indicate the type of
is bus tnmsaction that being performed.
Ready (READY)-This line is as~rted by external logic to extend the current bus cycle.
System Control Bus clear (BCLR)-The bus clear line. is asserted by the proces~r. during the powerup sequence and during the PDP-11 RESET instru~tion. The DAL< 15:8> and DAL< 1:0> lines receive the
mode register information during the assertion of the BCLR signal and the selected bits are loaded
into the ncn1 ·mode register.
.
Powerup (PUP)-The powerup signal resets the processor. When this signal is asserted, the DCTll stops all operation and an initialization sequence isexecuted when the signal.is·negated.
Int.errujit Control Priority in (PI)-The priority in signal is used as the system priority enable strobe. When the PI
line is asserted, the AI<;: 7;O > 1~.s receive interrupt inputs and the direct memory access request
(DMR). This signal may also be used as a data strobe for read or write operations.
Clock Signals Clock out (COUT)-The clock-out line provides a clock signal that is controlled by the selection of the mode register. This output can be one-half of the DCTll oscillator frequency or a pulse asserted once during e~ch internal microcycle.
Crystal,inputs (XTALO and XTALl)-The crystal-inputlines a~ external crystal connections JI) t:he internal clqck generator. A crystal or an external TTL-level dock generator may be used as an input. When an external oscillator is used, it c.oonects to the :XTU input and the XTLO input connects ~o ground.
~~Supply C9oµectioos
·. . .
Supply voliag~ (Vcci-Connects to.,tbe.5 Vdc power supply.
Ground and B Ground (GND and BGND)~These groµnd pins cont1e;ct together,and to the system ground to provide ground references for all lines of the DCT 11.
1-352
Confidential and Proprietary
...
· Architecture·sumuwj..
The DCTll microprocessor contains eight 16-bit general purpose regis~, a ps:«;essor sta~
fhe register; .and a mode register._ These registers, except for ivode register; are accessible to the to system prograinmer,bi>t~oi)ing appli(:S.tion pro~ms and the user for cliecking the validity
ofprograms and foq1erforming mainteriimcelfunctions.
GenerillPutpc>se RegiSiers
...
The eight 16-bit general putpose registers are !iliown in figure" 3. 'l'bei;e registers operate as
accµmulators, ind~ ~gisters, .!l~iru,;remf!n;t ~Ii~. !m~~m~t· ~t$, or as .stack
pointers for temporary storage of data.
Registers R6 and R7 are dedicated. R6 opemtes as the ~.po~~:{SP) an<itst.ntesthe location (address) of the last entry in the hardware stack. Register R7 (l.peta~J~:t\le processor program counter (PC) and stores the addre~ of t~ n,eKt ~t:ruct;ionoi; ~ toQc used;
RO
Rl
R2 GE~~RAL. l'!Ell1STER$
STACK POINTER
R6
,~t PROGRAM COUNTER ·I...___..,..._,A_1....,.......-.·..·....
Figure} · DCT11 General Purf!ose Registers
Processor Status Register
:woro The processor status register CC)P.tain~. the Pto,(es~o~ status
(PS'W) consisting of condition
codes, trap bit, and current{i~so)>p#()Titf'.':t'he p[()CesSOt statu~"tegister f()rmat is shown in
Figure 4. Table 2 lists the functions of the register information,
Figure 4 · DCTll Processor Status Register format Confidential and ProPrietacy
1-153
Bit
07-05
04
03-00
Table 2 · DCTll Processor Status Register Descrii'tion · ·
·'Description ·
by Priority level bits used the.software to determine which interrupt will be serviced.·
'
·,' '
'
' ''
' ... , ·,''
'''
'
'
': . ' - '
'
-
, - ~·-''
The trace bit used in debugging programs.· During a trap or.interrupt operation, the
trace bit can be set or cleared when returning from the intem;ipt by using a Return
from Interrrupt (RTI) or Return from Trap (RTT) instruction.
.
The coRdition codes eontain information about the result of the last CPU arithmetic or logical instructions. The bits are as follows:
N= 1 The result was negative. Z=l·Theresult was 0. V = 1 The operation resulted in an arithmetic overflow.· C = 11 The operand resulted in a carry from the most significant bit or a 1 was shifted from the most significant bit or least significant bit.
Mode Register The 16-bit mode register (MR) is used to program mariy ofthe DCTll features. The mode register
bit format is shown in Figure 5. This register must be loaded by the external hardware during the powerup sequence. It may be reloaded when a RESET instruction is executed; however, changing
processor modes after the powerup sequence has occurred is not recommended. Table 3 lists the functions of the register information.
15 14 13 12 11 10 09 os·· 07
START/RESTART USER 8-BIT K/1tlK STAT DELAY TEST 16-BIT 64K DYN NORM
06 OS 04 03
02 01
Figure 5 · DCT11 Mode Register Format
Bit
15-13 12 11 10 09 08 07-02 01 00
l-354
. Table 3 · DCTll Mode Register De~tion
Description
Start or restart address. User or tester mode. .8cbitor.16-bit data bus.. 4K/l6K or 64K chip memory. Static or dynamic memory; Delay or normal read or write strobes. Nofused. Standard or long microcycle. Processor or constant mode clock.
Confidential and Proprietary
Table 4 · OCT 11 Mode Register Starting Address Assigrmtents
Start/Restart
(bits 15:D)
Start
Address
Restart
Address
7
172000
172004
6
173000
173-004
5
000000
000004
4
010000
010004
3
020000
020004
2
040000.
040004
1
100000·
1\10004
0
140000
140004
''l>t,
· Bus . Operatif)ll
The following;par~bs. describe..$e.~PetiltiQp of, ~:})~1Tll·~P~?$0r 9µ~ dw:ing, the
pf· execu®n of i(IStru®QS'~ E.ach. ~:OP-11 jnstl11llc;tio~·.consis~ .~e or p:iore .transaoiqns.. A.
transactionis the activiw on. the bus re~to ~~form:t,~JC:iqcwu,g p~tj?Os·
. .
·Read
·Write
· Refresh
· DMA (Direct memory access)
· !ACK (Interrupt acknowledge)
· ASPI (Assert priority in)
· NOP (No operation)
Each transaction consists of one or two microcycles·and a microcyc)e consists of three or four cycles of the basic oscillator. One internal rnicroinstrllction is executed for e~ch microcycle. The number of microcycles required for a read a$Cl writetransaction depe~ds·on the mode register selections.
an . The standard microcycle mode wes. three clock cycle$ for most transactions. The long microcycle
mode uses four microcycles for transactions. One nii.croinstructkifi is executed during each microcycle. During a microinstruction, addres~i.nforma.ti1:m is transferi:ed, data is transferred to and from the bus, and internal operations are performed. Four clock cycles are used during the REFRESH, IACK, DMA, and ASPI transactions.
Read and Write Transactions
During a read or write transaction, the microprocessor transfers address information, sends or receives data, and monitors interrupt and Dlvi.A reqµests. Read, write, and DMA operations are modified by the mode register during powerup. The use of control signals and the number of transactions requiredfor:each operation depend$ on the following selections.
Confidential and·Proprietary
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· Static or dynamic memory: .. , / · 4/16K or 64K chip memory · 8- or 16-bit data bus opefutiorf
A write transaction is prec¢ed by a read transaction except when writing to the stack during an
interrupt or trap operation.
.
Address Selection
.
.·.
The address information is.transferred on the DAL< 15:00> and AI<7:0> lines depending on
the type of operation.
Dynamic Operation;..;.;.The timing sequence for the· 16-bit read and write operation with dynamic
memory is shown in Figure 6. The timing sequence for the 8-bit read or write operation with
dynamic memory is shown in Figure 7. When dynamic RAM operation is selected, the address
present on lines DAL<15:00> is time-multiplexed through the AI<7:0> outputs. The row.
address and then the column address is transferred at the beginning of a read or write transaction.
The' IO\V address is valid before the assertion of the RAS signahlrid the column address is valid
m before the assertion of the
signal: The multiplexed a&lress is the same addtess th11t is
transferraj by the DAL bus before the Ili\S sigtia1 oceurs. I:.ilnes AI< 7:0 > are ruso used to transfer
the internal refresh counter as a row address during the REFRESH transaction.
+ - - - C P U READ TRANSACTION1---
l--·E·O ADDRESS
READ INPUT~
Pl
R1Wti' ·.Willi.
NOAMAL -
$[ LO.S~L'I ~~~~-+---+-----+----
Read Sequence
OAlASTR®E
Figure 6 · DCT11 16-bit DynamkRh.rdand Write Timing Sequence
Confidential and, Pmpriet:ary
-
----CPVWRl'fETA:ANSACTION
ii
J--WfllTE ADDfU;ss~~RITE Ou'TPUT---1
R.iWt.T
AiWHB
NORMAL---~
R.jjJ
RIWH6 OEl'..A'VEO
S£L{),SE LI
L..,,..--J ~
ADDRESS STROBi::S'
OATA STROBES
Write Sequence
Figure 6 · DCT11 Dynamic Read-and Write Timing Sequence (Continued)
Confidential and Proprietary
1-357
'-------------------------·---·-·--------., . ..-·--~-~·
~CPU R!AD TRANSAet1~'(lO o.~~~u READ TRANSACTION !HI BYTE~ J-REAOADDAfSS~EAD INPUT~t:'AO ADORE~EAO 1NPur4
COUT SAL<15:08> - - . . . - - - - - - - - - - - - . , - - - - - - - - - - - . . . . , , - DAL< 15:06>
~~~~~~~~~~..---'''-~~~~~~~~-'''-
A-:17:10>
DCTU
Pl
~
NORMAL 'Im
Rii"HB
DELAYED
wr
R/Wtll
SE LO.SEU
"---v--J
ADDRESS STROIH:s
"---v--J DATA STROBE
ADDRESS STROBES
DATA STROBE
Read Sequem:e
Figure 7 · DCT11 8-bit Dynanic Read and Write Timing Sequence
1-358
Confidential and Proprietary
COUT
SAl<11l08> OAl.<15:08>
....... A<. t1:10>
.,,.,_.__.na~
P!
NORMAL
'11'1' RiWiJi
'JELA'fEO
SEUl,SELI
Ly.-) '----.,.-J Ly.-) L........,,,..-
ADbRES$t'r'ROS:ES DATAST~OIES ... , A0Df'ES$STII08ES ~OA1':ti.$YROBES
·Wrii:ec~ce
Figure 7 · DCT11 8-bit Dyna~ic.,Read.11n4W,rite Timing~equence (Continued)
Static Operation-The timing sequence for the 16-bitread and wr~te operation with static memory
is shown in Figure 8. The timing sequence for the 8-bitread or write operation with static memory
is shown in Figure 9. When static :mode is selected, lines AI< 1~0> are used to receive interrupt
and DMA requests and the address for static memory is.on th~ DAL bus. The information on the AI
lines should be valid when the PI signal is asserted. If theAI inputs change during the assertion of
the Pl signal, the results are unpredictable.
· ·
Confidential and Proprietary
....
GOUT·
- - - - - C P U READ TRANSACT!ON-
J.--..Rt:·D ADDRESS
f·
READ tNPUr---f'
',DCTU,:
=~
NORMAt -
=-DELAVEO -
AOORESS STROSE
Read Sequence
OATA STROBE
-CPUWAJTE TFU\NSACTIO,N---t---wR·ITE AOOAEss--+-:---WRITE OUTPur--t
Pl
·1.1:!.l
RIWHB NORMAL - - - - '
·W
A/WHB DELAYED
SELO,SEU -------t------1----"ttt----
ADO RESS STROBE
~ DATA STROBES
Write Sequence
Figure 8 · DCTll 16-bit Static Read and Write Timing Sequence
1-360
Confidential and Proprietary
-
rD.n.:-u1!m...n...u.~u-~: y
DCTU.
Pl
~.
NOIAMAL
ADORE.SS STftOBE
tJATAST-R08E ADpRESS STROSE
CO~T
S'i.L<tS:OI> Dfll.<15.'98> -'--.J\~-l--~~~~~~~~~-""-"+'-'--.;;;.;..;.;,.~~~~~~-''~ 0Al<07:01>
A<t?:MJ>
WT' R..wri
NORMAL
WI' ·liVlll
DELAYED 1115
R/WHe -
ADDRESS STROBE
DATA:STROBIS
ADDRESSSTROBE
L_,,.-..J
DATASTROB£S
Write Sequence
Figure 9 · DCTn 8-bit Static Read and Write Timing Sequence
Confidential and Proprietary
1-361
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. Preliminary
Address and Data, 16-bit Data Bus-During the 16-bit mode, ·shown in Figures 6 and 8,
.DAL< 05:00 > contain the 16-bit address before the assertion of the RAS signal. During a read
cycle, the data must be valid during the assertion of the PI signal and remain valid until the
negation of the CA'S signal. During a write cycle, the data is transferred before the assertion of the
PI signal and is valid after the negation of the PI signal.
·
Address and Data, 8-bit Data Bus-During the 8-bit mode, shown in Figure 10, two consecutive memory locations are used for one PDP-11 word. Two bus transactions are needed to fetch a PDP-11
instruction or to read or write a 16-bit operand'. The DAL< 15:08 > are renamed to SAL< 15:08 >
(static address lines) and are used to transfer the upper byte of the current 16-bit address.
SAL< 15:08 > signal lines are latched and valid until the end of the transaction. The timing of data
relative to the CAS signal and to the PI signal lines is the same as for 16-bit mode read and write
transactions.
SAi.<15:08> !DAU
HI avTE OF ADDRESS
Of.t.<07:00>
..""""LO BYTE OF
A<\7:10>
HI BYTE OF ADDRESS
Pl
fi'5 tA/WHil
NORMAL
llll"IRA'i'H!l
DELAYED
SELO NOTE
ADDRESS STROBE
NOTE: 1. SELO ASSitFITEO DURING INSTRUCTION FETCH AND ONlY FOR THE LO BYTE
2. SEL 1 IS LOW DURING THIS TAANSACTION.
ADDRESS STROBE
Figure 10 · DCTll 8-bit Read Transaction for 16-bit Won.I Timing Sequence
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Confidential and Proprietary
...
For an 8-bit mode ibstruction fetch odor operations on 16-bit data, the SAL< 15:08> Jines cont$n the upper byte of the current 16--bit address and DAL< 07:00> contain the lower byte of the address. As in 16-bit mode, the address is valid before the assertion of the RAS signal Thelow
byte of the word is then transferred in or out during ..the data part of the tra,nsaction. The DAL< 07:00 > outputs then the low byte of the word address+ 1, and the high byte of the 16-bit
won:l is transferred. When dynamic RAM supPort is selected; the addl:ds on DAL< 15:00> is mllltiplexed through the AI< 7:0 >. l,ine$ fur~ bus. transactiol;l,
When a PDP-11 BYTE instriictiol1.is ~~~·.Q.M.ol)f bus ~~on is needed to ti:ansfel' die source or destination operands..To fetch any instri.ictlon a word operation is always used.
Read and Write Control
The DCTU specifies the current bus transaction by the signals on the R/W'iIB' and R/WLB (read/ write) lines which may be modified.W the mode s~ions.
Selection of normal read/write mode causes the~ and"~ signals to be asserted before
the MS signal and is valid throughe,~t the ~n·...
and·R/WilB Selecting delayed read/write mode ~"the ~·
signals to be asserted with the
same timing as them signal. Selecting the 8- or 16-bit data,bus.operation changes the function of
these lines.
.
Read/Write and 16-bit Data Bus-During lb-hi.tb'\lS mode wd~~actions, Figures 6 and 8, the
R/Wi1B and R/Wi.B signals indicate which byte of DAL< 15:00> will contain valid write data.
During a byte write transaction, all the DAL bus lines will contain information; however, the
unused byte will be undefined. The valid write data is indicated by the read/write signals that is asserted low. When only one output is asserted; the data is a bytt:'operand. When the R,IWiIB line
ane asserted, the valid data is on DAL <>15:08 > when the RIWLB line is asserted, the valid data
is on DAL<07:00>. When ndther read/write line is lo~, a read operation occurs and
DAL<05:00> are in a high-impedance condition during this operations. Byte swapping is
performed within DCTll during read transactions.
Read/Write and 8-bit Data Bus-Selecting 8-bit data bus mode, shown in Figure 7 and 9, changes
the functions of the sigpals on the ~d/~tii) ~· The R/WmHine, l:iecomes a read signal when
asserted low, and the R/'WLl3 signal becomes a write signal when asserted low. The signal functions
are as follows:
16-Bit Data Bus
R/'WiIB (L =write operation) RJWrn (L=write operation)
8-Bit Data Bus
R/WHB (L... read operation) R/WIB (L =write operation)
Rj'WiIB (H =read operation)
R/WIB {H = read operation)
The functions of RD and WT signals are also affected by selecting normal or delayed read/write
mode. Normal mode asserts the RD or WT signal before the leading edge of the RAS signal. These signals are valid for the complete transaction. In the delayed mode, theRD and WT signals have the same tinllng as the GAS signal.
Confidential and Propdetary
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R.efresh..;...The dynamic memory of the system is automatically refreshedevery 2<milliseconds by a:
256.bit counter in the DCTlL A refresh transaction, shown;in Figure.Jll, :adds ami~le t'() the
transaction in progress·
· Afo~r every other PDP-llinstruction fetch in 16-bit mode. · After every PDP-11 instruction fetch U:i 8-bit mode.
· When an additional refresh occurs for addressing modes 5; 6, or 7.
· When a refresh microcyde occuts twice during a trap instruction.
":~ ~11---.,._SH~OORE-$-~
·
Pl
s~E<,L;O~~- 1: _____ ·· --·--------1~ .
SELi-
Figure 11 · DCT11 Refresh Transaction Timing Sequence
1-364
Confidential and Proprietary
...
.PseliminarY
ExteridingBuli ~stet.ions-Bus transactions can be extended for slow deviGes by asserting the
READY· sigruil dtiring·the tranSaetions.· Figure· 12 shows the READY· signal· timing sequenre.' In ~dditionfureadandwrite·transactions. the IAGK·and DMA transactions may aiso·beextended. '
-mcrrmm[ ~NllCROCYCt,.E SLll" I
""-<'·""> _ _x~(m~m~{{((~(m~(m~m(~{(((~m{-m~((((~m{~\{((~0·m"--..
lllllCAOCYCLE SltPl~
~:~:~~,:~~JI
A f}:tO
,,,_.,··.. --'.~_-,:; '.~_:';·:<;,, ,.':__~~!-~-~~-:~!'2;%_.~. ·' -,~'-.i§~, MICROCYCLES\.tP2~
_ ...x..._xm{nm((!mmm~{ammum I~~~ XR«mmm~~t'"1·~~]JJI
-1 _-- j . '~MiCROCVCLE~lf~ ' ·~
\....____________...!_,-_,~..-.._-_-_.._-_.-_-_-_-._. _-..,.-,_-.....
wc,~~~-LESLtP2_____,
~-- ~ u
-
- -- -
~MICROCYCLE SLIP l
ICflOCYCL,~llP 2~
\
.'r---·:- --------~-.,:_- ·_ 1 ________·:.____ J 1
N{)l'E l 7 3
----~'
\_ .;.- --- ----_.;. __s-- -- ---_--- -- ---\ ~MICAOCYCLESLIPI
MlCAOCVC'l!_ S L I P ' 2 - - 1
WAVEFORMS AR£"0AA.WN FOR 1&-81T DVN.6.MIC READ. REAOY WAVEFORM_IS_VAllO FOA ANY C~E Rfwti R"M-18 AAE-,~S'sERTEV HI THAOUGHOUT THE TRANSACTION SH OSH t ARF ASSfRTED LO THROUGHOUT THE TRANSACTION
~~;~T '-:X::::X: :~:i;lO -:oom:IXI
~~~~~1~,JXmlmlr CONDITIONAL ~-x:·.~·~·~·.x:
TH!' READY PULSE f#f,Y 8E Ol'IT...INEO BY GATING OOU-T WHH A READY EM AB-LE SIGN~L
HOLDING REAOY"l>f:RMANENTI..,, LOW RESULTS !HONE MlCAOCYCl.E SLO' PER aus TRANSACTION
~~~;1c=:x:
Figut;e 12 · DCTll READY Timing Se.quence
Each assertion of the READY line causes the ptocessor to add one rnicrocycle to the current bus
operation. The length ofthe rokrocycle depends on the selection of standard microcycle mode or long 1I!krocycle mode operation, Th~ REAl)Y in~utmt1Stbe pulsed lowf~r each uw¢t" miqpcycle to be added. When more than one a-dded rnicrofyeli,~)s tie~ded £61: sl!YW cte\fites;'tHei>CTllrequires
tnen a READY signal transition from low to high and to low. If the ft:tib'Y line fs connected to
ground, one microcycle slip will occur for each bus transaction. The RAS signal must be asserted for
the READY signal to have any affect.
lntflrl'Upt ~D~~P.eat~ ·
.
When the DCTll as~s the Plline; interru~ts and PMA ~\!ests cim"be received by the DCTU
;through the AI <7:0 >Ji.nes. T!le AI< 7:0 > lines ~ normally ~et. to a.high leYCl byinternal puJJqp
circuits and must be dri~nlow to caJJ&C.an interrupt. Jf static ip<;lClt is s,elected; these lines ru.:e u~
only as inputs and a~;lrepthlgh.dqrlng the address p~rof theJ?U!i cycle, Tht;se lines provide PF,
HALT, CPO-CP3 int~fUpts an,d theDM.R request.
Confidential and Proprietary
1-365
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Diie¢t .Memory Request..-When the. processor <letects .a direct memoey ·~ce:s~ request .on line AI <0 >,it releases control Of the OMA bus to~ device that asscms the DMR line. The DMAbus
consist11 of the DAL< 15:00>,AI< 7:0 > and ~writelines. The DCTll m~ control of all
other signals.
Interrupt Request-When one or more of the CPO-CPJ lines (AI< 4:1 >) are asserted during the
assertion of the PI line, the processor detects an interrupt request. The CPO-CP3 inputs are encoded, allowing 15 interrupts divided among four maskahle priority levels as described. The
processor decodes these inputs and starts an interrupt acknowledge (IACK) bus transaction when the current instruction is completed. Each line is dedicated to a specific interrupt or DMA request
as shown in Table 5.
CPJ
(All)
1ld>le .5 · DCTll Interrupt Request Line Assignments
CP2
(All)
m
(Al3)
CPO
(AI4)
Priority Level
Vector Address
x
x
x
x
HAIT*
x
·x.
x
x
PF*
24
L
L
L
L
7
140
L
L
L
H
7
144
L
L
H
L
7
150
L
L
H
H
7
154
L
H
L
L
6
100
L
H
L
H
6
104
L
H
H
L
6
110
L
H
H
H
6
114
H
L
L
H
5
124
H
L
H
L
5
130
H
L
H
H
5
134
H
H
L
L
4
60
H
H
L
H
4
64
H
H
H
H
No action
*IiJJl' and·PF signals are norunaskable interrupts. The HALT interrupt loads the PC with the
restart address and the PSW with the value 340.
Vector Assignments-When the VEC line (AI5} is asserted during a priority interrupt and one or more of the CPO-CP3 lines are asserted, the processor will accept an external vector value during an
I.ACK transaction. If the VEC' line is not asserted atthe same timethllt an interrupt is requested, the
processor willprovide a vectofaddtess from an internal table. The >Vector value will be oneof the 15
assigned to each CP interrupt cooe. Four interruptvect:Ors are assigned ro each priority level 7, 6,
and 5 and three interrupt vectors are assigned to level 4 as indicated in Table 5.
Powerfail-A powerfail hardware interrupt that vectors through locittion 24 occurs if.the PF signal
is asserted on line AI6 when the PI signal is asserted. This interrupt is nonmaskable and is processed regardless of the current interrupt priority level.
1.366
Confidential and Proprietary
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.OCTU
Hatt....;.'l'he li'i\I!i'interrupt request, assigned to line AI7,,is a nonmaskable interrupt that has a
higher.priority.than PQWetfail. After saving the current program counter and processor status values, the processor will set the priority to 340 and jump tot~ restart address. The restart address is ~.during poweruP when the mode register is loaded. The HALT input is pseudo-edge
tri88,~ and must be read as a n~g11tionbefore another ~tion,.is accepted by the processor. .
Dttect Memory Accesa..,....The DGTll provides a direct memc;>ry access (DMA) in,teyfi\Ce that can be
connect¢ to singl,e-channel or multipl~-channd DM,A tjrcwts. Requests for DMA are th!l)ugh the
direct memQry request JJMR inimto;n li11e 1\10·. A c.Urect m,.em9ry grant (OMG) will.ciccurafter
internal arbitration. The processor completes the cliirent bus transaction and relinquishes bus
mastership. Figure 13 shows the timing sequence of the OMA transaction.
Ml..<15:00>
___ ..
;w;
I OW,CURAENT "Ut.t.. UPI
OMG (SElOI
DMG (SE.Lil ·pv'Ls£.MOD!: ClOCK (MODE REGtSTEA<:t.().'*'1
Fi1;t1re ·13 · DCT11 DMA Timing Setjuence
The new bus master gains control of the bus when the SELO and SELl signals are asserted. When a OMG (SELO and SELl are both high) is received, the bus master must take control of the OMA bus.
The OMA bus consists of the R/W'HB and R/WIB lines (RD and WT in 8-bit mode), the
AI< 7:0 >, and the DAL< 15:00 > lines. The AI< 7:0 > and read/write lines are asserted through low-current pullup circuits and DAL< 15:00 > are in a high-impedance condition during the DMA
transfer. The processor maintains control over RAS, GAS, PI, COUT, SELO, and SELl lines to provides the new bus master with convenient timing signals for interfacing to dynamic memories.
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The bus master must control the read 'and write functions, provide addresses, and be capable of
driving or receiving data. fo dynamic memory systems, an address'must be multiplexed on lines
AI< 7:0 > so that row and column addresses are provided at the correct times. When adata input or o~tput transfer occurs, the direction of the transfer is controlled by the state
of the read and write lines. TheDCTll continues to issue grants by asserting the DMG signal until the DMR signal is not asserted. The DCTll then continues its usual operation.
Becausethe DCT11 . controls refresh operations based on the number of transactions.needed to execute the PDP-11 instruction set, consecutive DMA operations are not recommended: '
Interrupt()peratlon The DCTll uses a vectored, multilevel interrupt structure. Four priority levels are masked by the upper three bits of the processor status register. The two types of interrupts are maskable and nonmaskable.
Maskable interrupts are requested by an external device on the coded priority inputs lines CPO-
CP3. These requests will interrupt the processor operation according to the priority level of
interrupt codes 0 through 15. The nonmaskable interrupts are HAIT and PF which are not masked by the processor priority.
Interrupts are received on the CPO-CP3 lines when the PI signal is asserted. The processor
completes all bus transactions in the current PDP-11 instruction before servicing the interrupt.
Interrupts are latched in the processor during read transactions. The DMR inputs are latched during read or write transactions. The PI line must be asserted to latch either DMR or interrupts.
Each CP code is connected with a vector address in the DCTU. A PDP-11 vector consists of two consecutive memory locations. Vector locations are in low memory (0-376) and must be assigned by
software. The first location must contain the address of the first instruction of the interrupt service routine. The second location contains the new processor status word. The device causing the interrupt may provide a vector address. When it asserts the interrupt request code, it also asserts
the VEC signal on line AI5 to indicate that an external vector is present. If the VEC signal is not
asserted, the DCTll provides a predetermined vector.
Interrupt Acknowledge Transaction The interrupt acknowledge (IACK) transaction, shown in Figure 14, starts when the current instruction has been completed. ·The priority is compared with the value in the processor status register PSR. If the interrupting device's code has a higher priority than the present PSR value, the interrupt request is serviced. The SELO and SELl lines indicate that the current bus transaction is an IACK. The RAS signal is the only timing strobe asserted during IACK. When it is asserted, DAL< 15:08> (SAL< 15:08> in 8-bit bus mode) transfer the priority interrupt code that is being
acknowledged as shown in Figure 15. The DAL< 07:02 > lines contain the vector input if the VEC
signal is asserted.
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D-J:,....!--...u
" &' t.;1W'IHIUl'HU.-J
OAl.:<12:08>
· INTERRUPT ACKNOWLEDGE DATA
DAL<07:01>
VECTOR DATA
·ocTn
Pl SELO
SELi
IACK DATA VALID
Figure 14 · DCTll IACK Transaction Timing Sequence
The current contents of the PSR ate then placed on the hardware stack. The program counter (PC)
value at the time of theinterrupt is then placed onto the stack: ThctPC isloadedwiththe address of
the interrupt service routine from the vector location·~nd the new PS is loaded into the PS. register
from the vector location+ 2. When completed, the service routine ends with an RTI (Return from
interrupt) instruction that causes the PC and PSW values to be recovered from the stack and the
processor will continue executing theinterrupted pro~m;
/'
.'. - "" · -.
,.: ---~--.--_
_1 .: ' ' ·;-:1,'. ,-. :>--; ,, " :'.' 3,~
INTERRUPT RE OU EST
VEC
37
(AIS)
CPO
36
(Al4)
CPI
35
(AIS)
CP2
34
,!Al2)
CP3
33
(Al1)
DCT11
.·. JNUR.Rl!PT ACKNQWLEDGE (IACI<) ·
DAl12
OAL11
OAL10
7
DAL09
9
PAtDB
Figure 15 · DCTll Intmupt Request/Acknowledge Lines
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-----·- - - · · --~-------·------------------·------·
~-·----·------
-
Assert Priority in ilansactjog
.
. ..
. .
During an assert priorityJn (ASPI) transactions shown in Figure lq, interrupts or DMA requests
that are pending are allowed to compete for the DCTlL Only the 00 and PI lines are asserted
during an ASPI transaction that occurs after a powerup sequence, HALT instruction, halt interrupt,
or WAIT instruction.
Figure 16 · DCT11 ASPI Transaction Timing Sequence
No Operation Bus 'liansaction During a no operation (NOP), a process does not occur at the outputs of the DCTll. The DAL<15:00> have previouslylatched data and the AI<7:0> lines are connected to pullup
circuits during the static mode. The AI< 7:0 > lines are undefined in the dynamic mode and all
controls signals are unasserted.
Status Flags The SELO and SEL1 lines are processor status indicators. The type of transaction in process can be detected by decoding these lines. The signal timing of the these li.nes depends on the type of transaction.Table 6 shows the·select line assignments.
Table 6 · DCTU Status Indicator Selection
SELl
SELl
Function
L
L
Read or write, ASPI,1 bus NOP, or FETCH'
L
H
Instruction FETCH or REFRESH1
H
L
IACK (Interrupt Acknowledge)
H
H
DMG (Direct Memory Grant)
1ASPI (Assert Priority In) bus transactions check for interrupts during p<>werup and the PDP-11 WAIT intructions. 2This code specifies a fetch operation when 4K/16K dynamic mode is selected and AIO is asserted low during the assertion of the RAS signal. >This code specifies a fetch operation when static or 64K and dynamic modes are selected, and a refresh bus cycle when 4K/16K and dymµnic modes are selected.
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In addition to the select line outputs, the AIO line indicates that an instruction fetch is in progress.
This occurs before the assertion of the RAS signal when the 4K/16K chip dynamic RAM .mode i$
selected. The AIO line may also be asserted during a refresh transaction. The AIO signal is
controlled by the most significant bit of the internal'refresh counter. The SELO and SELl signals
can be used to verify that a refl:esh operati.On is,.i.J\ proc~· ~ ~K chip dynamic RAMs are
used, AIO is the. t>i:ocessor address bit ·M5..
, .
'
'
':· , . . .'
Signal Line Swmnary
.
... ..
The following tables summarize the. ftmction of data and address bus control signal,. and miscel-
laneous signal itlfc;>rmation of the DCTlt
Bus Operation Summa:ey-'llible 7 is a swnmary of the function of the information ci:>ntained on
the lines DAL< 15:00 > and AI< 7:0 > during bus operations.
P'ui . 1-7,9
10-17
Table 7 · DCTll Data and AddrelsBus Summary
Line
DAL< 15:08:> ·· 16-bit mode SAL< 15:08> 8-bit mode. DAL.<07:00> 8-or 16-bitmode
DAL<l5:00> Three-sta~ d,ur~ PMA ~,·asset. Pdority. (#J?I) ~~()tlS
Contain pfeviously data durlDg a NOP or refresh. tr1lnsaction.
DAL<Ol:OO> DAL<15:08>
DAL<07:02>
Read into the mode register on powerup or during the RESET instruction.
input .a-0. ~nat: Ve:ctor ~ t,l)e in~t~AeVic" d\Jl;,ipg ~
interrupt acknowledge (IACK) transaction if the VEC sigiial was
asserted during PI.
DAL<U:08> Used to output information present on.AI.< 5:1 > during the IACK
~oo:;
..
AI<5:1> AIO AI<7:0> AI5
AI<7:0>
Used to transfer interrupt crequ~t to the proce5sor.
Used to.t.r. a. n-s.fer a.DMA request tO'. the processor. Used to trans£er ~e row and colultln addresses from the processor.
Provides a control signal to indicate when an external vector is to be used.
Receives inputs in static mode and contains previously latched data in dynamic mode during NOP and IACK transactions.
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Address/IntemiptLin~The interrupt and addressing information presented on the Al~ 7:0 >
lines is listed in Table 8.
·
· ·
'
'.lable 8 · OCTll Address Line FunctiOnS
Pin
Line
All Modes @Pl
4K/16K Dynamic
RAS
CAS
64KDynamic
RAS
CAS
32
AIO
i5MR
FET/REF* A14
A15 · A14
33
All
CP3
Al
A2
Al
A2
34
Al2
CP2
A3
A4
A3
A4
35
AI3
CPI
A5
A6
A5
A6
36
AI4
CPO
A7
A8
A7
A8
37
AI5
VEC
A9
AlO
A9
AlO
38
AI6
PF
AU . A12
All
A12
39
AI7
HAIJ'
A13
A14
A13
A14
*PET/REF AIO indicates a fetch or refresh operation in 4K/16K dynamic mode. The encoded SELO
and SELl lines determine which transaction is occUrring.
'
. ·~.
Line AIO specifies a fetch or refresh operation for a 4K/16K chip dynamic RAM mode~ The SELi and SJ;:LO litlesJndicate which operation is in protess as listed in Table 9.
SELl L L
'.lable 9 · DCTU Dynamic RAM Select Line Functions
SELO
Transaction
L
FETCH
H
REFRESH
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Control Signal Summary-A summary of the control signals is contained in Table 10.
Table 10 · DCT11Conttol Signal Summary
P'm
Signal
Function
24
SEU
Transaction select 1
25
SELO
'i'ran$1tci:io6 ·~~ ij
26
READY
Idle.s.tate select
29
RAS
Row address select
30
CAS
Column address select
31
PI
Priority Interrupt
27
R/WHB
Read/Write high byte (16·bit) select
RD
Read (8..bit]
28
R/WLB
Read/Write low byte (8-hit) select
WT
Write (8-bit)
Miscdlaneous Signal Summary-A summar)t of the inis<:ellanedw signals is listed in Table 11. ·
Pin
Signal
18
Bus clear
19
PUP
Powerup
21
COUT
Clock,qut
22
XTLl
Crystal inputl
23
XTLO
Crystal input 2
· Inititialization
The powerup (PUP) input has a Schmitt trigger that sen5es transitions from low to high and has a low-current internal pulldown device~tis alwap e~b~. WheMhe :flUJNnput is forced high, all DCTll operation stops. Figure 17 shows the signal timing for the powerup operation. The assertion
of the PUP line causes the OCDi signal to be asserted. The OCDi signal enables the mode register to be loaded with the configuration information. When the processor detects a high to low transition
on the PUPline, the powerup sequence starts. All information in the internal registers is undefined.
The information on DAL< 15:00 > and AI< 7:0> lines is also undefined. The control and
miscellaneous signals are not asserted. An external lk 1% resistor must be connected from BCLR input to ground to assure the correct operation.
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...
·~J . \\\\·
''---'' , l.... --'J
Figure 17 · DCTll Powerup Timing Sequence
Loading the Mode Register
The DAL< 15:00 > provide information to change the mode register settings. Figure 18 shows the
connections of the PUP line to allow the BCLR signal to load the DCTll mode register information.
During the assertion of BCLR, DAL< 02:00 > and DAL< 15:08 > are connected to internal pullup
circuits and are asserted unless driven low by the external signals. These lines contain the mode
register information and DAL< 07:03 > are in a high-impedance condition at this time. The BCLR
signal is asserted during the powerup sequence and when a RESET instruction is executed. The mode register will accept data during the assertion of the BCLR signal.
DAL<15:08>'
Vee
DAL<Ol.00>
.l
DCT11
PUP
1Kil 1%
LS244
Fikure 18·DCT11 Mode Regjster Loading Configuration
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Refresh and No Operation The DCTU mode information loded when the BCLR signal is negated. If dynamic RAM support has been selected; the refresh transactions will be executed to ensure the correct·start for the dynamic RAMs: Dl:lnng8-bit'data bus mode, 20 REFRESH transactiohswillbeexecuted and, during 16~bit mode, t.en refresh transactions will be executed. During static mode, 11 NOP (No operation) bus transaction will be executed. After the refresh or NOP transactions,· one ASPI
the transaction is performed to determine if interrupts are pendip.g: ASPI trimsaction asserts, CAS
and PI signals and the refresh· transaction asserts only· the RAS signal. No control signals ·are
asserted during a NOP transe,ction while performing internal operatfons. ·
Starting Address ·
. ......
A read transaction to the starting address follows the refresh or NOP transaction. The first
instruction fetch. St!il'ts the DCTll program operation. One, of eight $tarting addresses can be
selected by the three .most significant bi.ts of .the 01ode regi.stef. Eapl;:i,,adq.ress has an associ~ted
restal'.t location. The restart address is the first location to btr ~ted when a JiAU' it;istruction is
executed or a halt interrupt is asserted.
Oock Output
. .
.
.. .
The clockouput (COUT) is a square wave controlled by bit 0 ofth{mode register as shown in
Figure 19. Selecting constant clock mode produces a square-wave bUtput at· a one-half of the
internal oscillator or XTLl inf)Ut frequency. When processor clock mode (PCM) is selected, the
COUT output provides a pulSe once during eapli mi.crocycle. No c~pse ~ relatii;lrisl:Up Cf{ists
between the edges of the COUT ~goal andthe.int~nal oscillatoi: or XTLl clqck input.
XTl1
=:~~~{T,I._----,-·-_-1-_--_-_.__I___....,J,.....-----. _ ___,, ...___
Figure 19 · DCT11 Clock Output Timing Sequence
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···octn
· Performance Data
Thbles 12 tluough 17 list the executi~n times for rut DCTlLinstructions and are used to determine
the total program exection time. The tables list the minimum and :rpaximum execution time of an
instruction µi 16-bit and 8-bit mode of operation and with the memory refresh function active (on)
and not aP;ive (off). The possible system combinations are . .
·.
.
· 16-bit mode with memory refresh on
· 16-bit mode with memory refresh off .
· 8-bit mode with memory refresh on · 8-bit mode ~ith memory refresh off
With refresh on, the refresh cycle increases the execution time. The execution time of an instruction may also vary wfth memory refresh on. In 8-bit mode, refresh occurs every instruction cycll!. In 16~bit mode, refresh occurs every other cyde: Addressing modes 5, 6·, 7, 1/0, and Trap also increase the time for execution.
The program execution time (PET) is calculated by totaling the average execution time of the instruction used in the progr:am. The following information applies to Tables 12 thrdugh 17.
·. All times· are in microseconds. Add 0.4. µs for every READY pulse that occurs during a read or write transaction,
~ The operatµig frequency is 7.5 MHz. To compute the program execution time (PET) for frequencies other than 7.5 MHz, the following equation is used.
PET=(7.5 MHz +F0 p)XIET
where IET is instruction execution time in microseconds from the tables and F0 pis the operating
frequency in MHz.
.
Example: Calculate the program execution (PET) for a MOV, RO, Rl instruction when in the static, 16-bit mode with memory refresh off. The operating frequency is 6.0 MHz. The MOV instruction is a double-operand instruction. The IET for the source operand and the destination operand is listed in Table 13 and 14, respectively. IET=source mode time+destination mode time= f.2 µs+0.4µs=1.6 µs'(total). To calculate the program execution time: PET=(7.5 MHz+6.0 MHz)x(l.6µs)=1.25x1.6=2.0 µs
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Prelimioiiy
·nma.:
lable U · DCTll XORand Single-operand·Inskuetion Execution Time
REFRESH
Instrtactions*
CLR(B),COM(B): INC(B),DEC{B), . NEG(B),ROR(B), ROL(B),ASR{B), ASL(B),SWAB, ADC(B),SBC(B), SXT,MFPS, XOR
16-BitMode
ON ON OFF
Dest. Mode Min. Max.
0
1.60 1.7.3 t6
1
2.80 2.93 2.8
2
2.80 2.93 2.8
3
3.60 3.73 3.6
4
3.20 ·3.33 3.2
5
4.13 4.26 4.0
6
4.U 4.26 4.0
7
4.93 5.06 4.8
8·BitMode ON ON
Word Byte In.tr. Instr.
2:53 2.53 5;33 3.73
5.33 3.73
6.93 5.33 5.73 4.13 1.46 5.86 7.46 5.86 9,06 7.46
OFF
Word
Instr.
2.4 5.2 5.2 6.8 5.6 7.2 7.2
8.8
OFF Byte Instr.
2.4 3.6 1 3.6 5.2· 4.0 5.6 5.6 7.2
TST(B)
0
1.60 1.73 1.6
1
2.40 2.53' 2.4
2
2.40 2.53 2.4
3
3.20 3.33 3.2
4
2.80 2.93 2.8
5,1, 3.73,: 3.86; l.6
6
3.73 3.86 3.6
"7
4.53 .4.66 4.4
2.53 2.53 2.4 2.4
4.13 353 4.G;· 3.2·
4.13 3.33 4.0 3.2
5.73 4.93 5.6 4.8
5.33 3.73 5.2 3.6
·6.~6. 5.46 6.0
5.2
.,6.26 5.46 6.0 5.2
7.86 7.06 7.6 6.8
MTPS
0
3.20 3.33 3.2
4.13 4.13 4.0 4.0
1
4.00 4.13 4-0
14.9,l .. 4.93 4.8 4,8
2
4:00 4.13 4.0
4;93 4.93 4,8. 4.8
3
4.80 4.93 4.8
''6.53 6.53 6.4 6.4
4
4.40 4.?3 4.4
. 5.33 5.33 5.2 5.2
5
.5.33 5.46 5.2
7.06 7.06 6.8 6.8
.6
5.33 5..46 5.2
7.06 7.06 6.8 6.8
7
6.13 6:26 6.0
8.66 8.66 8.4 8.4
*TheXOR and single~operand instruction ¢xecution times inclµde instructions fetch, instruction decode, operand fetch, instru.ction operation, and result Output. In mode 0 and the TST(B) instl'Uction, there is no output..
____________ ___ _ --- ._. Confidential·and PrQprietary
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..-. · ,. ,_,,, _....,.,....... ....,...,,............. _,,........".."'"""'"""'
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PNliminary
DGT11
Table 13 · DCTll Double-operand Instruction Sow:c~ Mode Execution Tame
l6·BitMode
,,,
8-BitMode
REFRESH
ON ON ON ON OFF ON ON OFF OFF
Instructions ·
Dest.
Dest.
src·· Mode (0-4) Mode(5-7)
Mode* Min. Max. Min. Max.
Word Byte Word Byte Instr. Instr. .Instr. Instr.
MOV(B),CMP(B), 0
ADD,SUB,
1
BIT(B),BIC(B), 2
BIS(B)
3
4
5
6
7
1.20 1.33 1.33 l.33 1.2 2.00 2.13 2.13 2.13 2.0 2.00 2.13 2.13 2.13 2.0 2.80 2.93 2.93 2.93 2.8 2.40 2.53 2.53 2.53 2.4 3.33 3.33 3.33 3.46 .3.2 3.33 3.33 3.33 3.46 3.2 4.13 4.13 4.. 13 4.26 4.0
2.13 2.13 2.0 2.0. 3.73 2.93 3;6 2.8 3.73 2.93 3.6 2.8 . 5.33 4.53 5;2 . 4.4 4.13 3.33 4.0 3.2 5.86 5.06 5.6 . 4;8 5.86 5.06 5.6 4.8 7.46 6.66 7.2 6.4
*Source mode times include instruction fetch, instruction decode, and source operand fetch.
Table 14 · DCTll Double-operand Instruction Destination Mode Execution Time
REFRESH Instructions*
16-BitMode ON ON OFF Dest. Mode Min. Max.
8-BitMode ON ON Word Byte Instr. Instr.
OFF Word
Instr.
OFF Byte Instr.
MOV(B),ADD, SUB,BIC{B), BIS(B)
0
0.4 0.4 0.4
0.40 0.40 0.4 0.4
1
1.6 1.6 1.6
.2.40 1.6 2.4 1.6
2
1.6 1.6 1.6
2.40 1.6 2.4 1.6
3
2.4 2.4 2.4
4.00 3.20 4.0 3.2
4
2.0 2.0 2.0
2.80 2.00 2.8 2.0
5
2.8 2.8 2.8
4.53 3.73 4.4 3.6
6
2.8 2.8 2.8
4.53 . 3.73 4.4 3.6
7
3.6 3.6 5.6
6.13 5.33 6.0 5.2
CMP(B),BIT(B)
0
0.4 0.4 0.4
1
1.2 1.2 1.2
2
1.2 1.2 1.2
3
2.0 2.0 2.0
4
1.6 1.6 1.6
5
2.4 2.4 2.4
6
2.4 2.4 2.4
7
3.2 3.2 3.2
0.40' 0.40 0.4 0.4 2.00 1.20 2.0 1.2 2.00 1.20 2.0 1.2 3.60 2.80 3.6 2.8 2.40 1.60 2.4 1.6 4.13 3.33 4.0 3.2 4.13 3.33 4.0 3.2 5.73 4.93 5.6 4.8
*Destination mode times include destination operand fetch, instruction operation, and result output. In destination mode 0 and the CMP{B) and BIT(B) instructions, there are no outputs.
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Table 15 · DCTll Branch, Trap, and Interrupt Instruction Execution Time
REFRESH
ln$tructions*
16-Bit Mode .ON ON OFF Ile$t.
Mode Min. ·Max.
8-BitMode ON ON Word Byte Instr. Instr.
OFF Word Instr.
OFF
Byte
Ins~
BR,BNE,BEQ,BPL, NA
BMI,BVC,BVS;BCC~
BCS,Bf}E,BLT,BGT, BtE,BHi;BLOS,· BHIS,BLO
EMT,TRAP,BPT,IOT NA
1.60 1.73 1.6 6.53 6.66 ,· '6.4
2.53 NA 2.4 Nit 9:73 NA 9.6 NA
lU'I
NA 3.20 33.3 3.2
4.93 NA 4.8 NA.
RTT
NA 4.40 4.53 4.4
7.0 NA
*l Branch instrudfon execution times include in'struction fetch, instruction decoding, doubling theMfset, testing the conditions,\ind adding the offset to the PC if the conditions are met. The execution times are not affected whether or not a branch is taken.
2. Trap instruction execution times include instruction fetch, instruction decode, pushing the PSW and PC onto the stack, loading the PC with the contents of the vector location, and loading the PSW with the contents ofthe vector location pluuwo.
3. Return from Ib~pf'instfuctioQ: eiecti!idn ~imes inclU,:de instruction fetch; ;instruction
decode, and removing t~ 00 .information and PS:W. from th.eYStack.
,Table16 · DCT1l·Jump and SubroutkJe Instru~ E~¢ittion Time
REFRESH
InStructions*
16-BitMode ON .ON OFF Dest. Mode Min. ·Max.
8-Bit.Mode ON ON
Word. Byre
Instr. Instr.
OFF 9F,F. Word ]Jyte
Instr. Insu.
JMP
1
2.00 2.13 2.0
2.93 NA 2.8 ·NA
2
2.40 2.53 2.4
3.33 NA 3.2 NA
3
2.40 2.53 2.4
4.13 NA 4.0 NA
4
2.40 2.53 2.4
.'U3 NA 3.2 NA
5
2.93 2~93 2.8
4.53 NA 4.4 NA
6
2:93 2i9:3 2.8
7
3.73 . 3.73 3.6
453 NA 6.13 NA
4.4 NA· 6.0 . NA
JSR
1
3.60 3.73 3.6
5.33 NA 52 NA
2
4.00 4.1.3 4.0
5
4.00 4.13 4.0
5.73 NA 5.6 NA
6.53 NA 6.4 NA
4
4.00 4.13 4.0
5.73 NA 5.6 NA
5
4.53 4.53 4.4
6.93 NA 6.8 NA
6
4.53 4.53 4.4
6.93 NA 6:8 NA
7
5.33 5.33 5.2
8.53 NA 8.4 NA
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Preliminary
REFRESH
Instructions*
Dest.
Mode
16·Bit Mode ·
ON ON
Min. Max.
OFF ,:J
&-Bit Mode ON ON
.Word Byte Instr. Instr.
OFF OFF
Word Byte
Instr. Instr.
RTS
NA 2.80 2.93 2.8
4.53 NA 4.4 NA
SOB
NA 2.40 2.53 2.4
3.33 NA 3.2· NA
*1. JMPf.fSR destination mode 0 is an illegal instruction that traps to vector location 10.
2. JMP execution times include instruction fetch, instruction decode, operand fetch, anq loading
the PC.
...
3. JSR execution times include instruction decode, operand fetch, pushing the linkag~ register
onto the stack, and loading the PC.
4. RTS execution times inlude instruction fetch, instruction decode, loading the PC, popping the stack, and loading the linkage register.
5. SOB execution times include instruction fetch, instruction decode, decrementing the count
register, testing for zero, and branching, if necessary. The exeoition time is not.affected whether
or not a branch is taken.
·
Table 17 · DCTU MiscellaneoJJs and Conditi~n Code Instruction ~xecution Time
REFRESH
Instructions*
16-BitMode
ON ON OFF
Dest.
Mode Min. Max.
8-BitMode
ON ON
Word Byte Instr. Instr.
OFF
Word Instr.
OFF Byte Instr.
HALT
NA 5.73 5.86 5.6
8.4 NA 8.0 NA
WAIT
NA 1.60 1.73 1.6
2.43 NA 2.4 NA
RESET
NA. 14.60 14.73 14.6
16.53 NA 16.4 NA
NOP
NA 2.40 2.53 2.4
3.33 NA 3.2 NA
CLC,CLV,CLZ,CLN, NA CCC,SEC,SEV,SEZ, SEN,SCC
2.40 2.53 2.4
3.33 NA 3.2 NA
MFPT
NA 2.00 2.13 2.0
2.93 NA 2.8 NA
*1.. The HALT instruction execution time includes instruction fetch, instruction decode, writing
the PC information and PSW onto the stack, loading the PSW with 340, and loading the PC with
the. testaruddress.
2. The WAIT instruction execi.ltion time includes instruction fetch, instruction decode, pulsing Pl,to sample the interrupt lines, and doing a REFRE.SH cycle if refresh is on. If no interrupt lines
were sensed by the DCTU to be asserted during the PI pulse, the WAIT instruction will cycle in a 1,2µs looppulsing PI. If refresl) in on, the loop will be 1.33µs qiaximum. The looping will continue
until an interrupt line is asserted and sensed by the pCTll.
1-380
Confidential and Proprietary
-
3· ·The ~SET execlJtion time includes instruction fetch, instruction decode, the ~on of
Bbt&; and the w:titing of DAL< 15:00> into the mode register.
rune 4..The NOP ~ti.On includes instruction fetch, instructlO[l decode, and idlbtime.
5. Condi~tt~ (CC) ~tructionexeQJtion ~me.~.iris~i9n fetch, instructiond~e,
and the Setting or resetting of the appropriate stilfus ~ in the PSW.
·
·
Interrupt Latency
The interruptJ·tellC}' ~ tµeasured from the time t~·Wfet;lif!~t request {IRQ) is asserted on the AI
inputs until the time that the DCTll is ready to fetch the1ii'st instruction in the service routine.
Figure iQ sh9WS d¥; interrupt latency,paflilmet;er,s,
··
- - - -'-
- - c-'
- - ,-,-._
- <.'.-.' ._,,_.-
I
Ll\ST
t !ACK
INl;tRUCTtON' , ,. MICROCODE
I FlflST INsTRVCTION
II OF SERVICE ROUTINE
..
I I
__ ,.._.,..__
. . II 8-~--
c
- - : -.7.:...1..i
.
I
.I .
' .. ' t
--...
iRU I
t
I
I
. l
I I
I
I
;
I
. 'I
· 1
. fr
I
1
Pl
,..._.,·,.·.·
l
I I . ' r:·
I t
- - - · '-o.:.. ( .
IACK _____.,,._, ,._1'I...;~.· !
I· I
.. ,l.,;'
The proce11Sor i:ontin.u~ to. ~te ~c;t~s Jil!.ltil tl1e rc::querJ~ is.lawhe.;l, l?y tht:.,as~tipn ,of the
PI signal which c~ ~Pll\~ ti).e,iifs~~~ti,9,n t~µ~in~,~c~l;l~~t. ~ ~uri:en~ in,str,u~ti9n is
then completed and ~e IACK microcode is execut@ to aC'.knowle<.{ge the interrupt request and the
following operatfons are perforined.
. .
· .'
·
· Arbitrate priority.
· Issue t.he IACK signal.
· Store proces5otstatcis andprogramcountervalues..
·.·Load. new p.fucess9r ~J~t\.ls'~rid prognim counter values.
, <-,, .,,, ,.·. ·,''\,' ) ., ·' '_. - ". , ;/ , : ' ' ' ' -_ :' ' '''
, >'-··· ,_.
·, ''i:' ·' ' '-;
Con£idential·an.d·Proprietary
-
..', D, -1L.., :· -':' ·-. ·"~"·1 ".··
The. interrupt.~uest:.(IRQ} ·fa. asswned tQ 9C(:J.l;t di:Jdng:.~·~P,P-11,Ju~p ;t9Subro~t:ine. (JSR) instruction (mode 2 or 4) or during an·e~u.lat9rJrap;{EMT)se~µ~~ whichprovides ® ll).aximtim
delay for. an IRQ., '.The. mrutinwm latende:( times a&sqr.ne tha.t the PCTlljsin the standard
mkrocyde mode andthe READY signalis pot asserted during the transaction.Table 18 lists the
maximum latency tiriles for the 16- arid 8-bit modes, di.iring dynamic and static operation;
Active Inputs*
Table 18 · DCTll 8- and 16-bit Mode Latency Time (7.5 MHz)
·::;o;
16-BitMode
Dest. Mode
Dynamic Static
D}tnamic · Static
CPO-CPJ,PF,HA'i':T (Internal vector)
NA
15.47
15.20
22.13
21.60
VEC,CPO-CP3 (External vector)
NA
15.87
15.60
22.53
22.00
DMR
NA
3.66
3.52
4.46
4.32
WAIT Instruction Internal vector
External vector
NA
7.87
7,73
10.53
10.13
NA
8.27
8.13
10.93
10.53
DMR
NA
1.66
1.66
1.79
1.66
*1. The latency time is in microseconds and the clock frequency is..7.5MH2.
2. Interrupt latency is calculated from the time the Interrupt Request is asserted either on the AI lines (in static modes) or on the input of the AI tine driver (in dynamic modes) to the time the DCTll is ready to fetch th~ first.i11strm:tio11 in the interrupt's service routine.
3. DMG latency is calculated from the time the DMR signal is valid on the input of the AI line driver to the time the DCTU.as~rts. the DMG. sign.al.
4. The WAIT instruction latencies are the maximum encountered in the instruction's execution state and do not include the instruction fetch or the instruction decode.
5. ·The Worstcfase times refer td IRQ occurring dudti:g aJSR (mode 2 or 4) EMT sequence.
6'.' The worst-case times refer to DMR <:fcurrihg dtiring aMTPS (mod~ 0) insttuction. 7. The timings assume that the DCTll is not in long bus cycle.and no ready slips occur.. ·
DMALatency The maximum time between a DMA request and grant dep~nds on the DCTll mode.The.
o maximum time occurs during a Move byte w Proet:ssor StatmdM1PS) instruction ih rnode and
is measured from the time that the DMR signal is valid on line AIO until the DCTU asserts the
a DMG signal. The maximum latencies aSSU!'.llC thaft;he PC'.fll il!.i~ the :;~11dard µtlcrocycle. mode
and the READY signal is not asserted during transaction. The mamnum.bMR latencies are listed
in Table 18.
Confidential,.and Pn;>prietmr
-·
· Instruction Set Refer te;Appendix B for a corn11Iete list of the DCTll mi®processor instruction set.
· Spedficatioos
BC'f The mechanical, electrical, and enviromental characteristics and specification.sfor the 11 are
'as described in the foll<>wjngparagraphs. The t~t F<Jnditions fortbe electrical vii!u1!S are :follows
unless.specified differently,.ift the tables. Refer to Digital specification A-PS-2100002-GS tor
general information on the integrated circuits. · Powersiipplyvoltage(Vcc)! 5.0 ±5% · Temperature range (TA): 0°C to 70°C · Relative pumidity; 10% tQ' 90% (qo;icondensing)
M~ Configwation
.
.
The physieal dimen~ons of the DCTll 40-pinDIPare contained in Appendix E.
Absolute Maximum Ratings
..
Stresses greater than the absolute maximum ratings may cause ~manent dij:mage" t<i'thf! deviee.
Exposure to the absolute maximum ratings · foli extended periQ<iS may adversely affect the
reliability of this device.
· Pin voltage: -0.5 Y to 7..0V
· Power dissipation:' 1.1 W (maximum) at 0°G
· Ambient operating temperature: 0°C to 70?:C
· Storage temperature: -55°C to J::?5°~
· Rdativehumidity: 10% to 95% {nonrondeOsl±lg) ·:
· Supply voltage (Vcc): 5.0 volts ± 5% · Supply current (lcJ: 190 mA (maximum)
de Electrical Characteristics The de electrical characteristics of the DCT 11 for the operating :v<>ltage and temperature ranges specified and with V55 =0 V are listed in Table 19. Refer to <A'ppendix C;for tes~ circuit configurations referenced in the tables.
-....:..
Tuble 19 · DCTll de Input and Output Parameters
Parameter
·,: ,,
Test
Symbol C.Ondition
;j,~ellts
Min. Max.
High-level input
Vm
voltage oq.~ADY,
DAL<
15:00>
(
-; '
,AI ··_
<·.,.-7.
:
0 '
>.''
High-level input·
Vui
voltage for PUP
2.0
Vee
2.2 Vee
Low-level input
VrL
voltage on READY,
DAL< 15:00-> ,AI< 7:0 >
Low-level input
VrL
voltage for PUP
-0.5* 0.8
.. ..;.05*
o.6
High-level
Von lou =-700. µA 2.4
output voltage
for DAL< 15:00 >,
C01JT, PI, ~ELl, SEJ1)
High-level output voltage for
Al<7:0>
Vom loo=:-700µA 2.6
High-level output voltage for BCLR
Voue lou=-700µA 2.2 terminated with ·
lkn resistor tO ·
Vss
High-level output voltage for
Vouc lou=-700µ4 2.$ .
RAS, CAS, R/WLB, R/WHB
Low-level output vo!tage for
VoL
~=3.2mA
0
o.4
DAL< 15:00> ,AI<7:0>,
COUT, PI, SELl, SELO,
BCLR, RAS, 00, R,IWLB,R/WHB
Input capacitance
G;.
10
for READY,
DAL< 15:00>,AI<7:0>
Output capaci-
C.,.,
20
tance for three·
state load on
DAL< 15:00 >,AI< 7:0 >,
COUT, PI, SELl, SELO,
BCLR, RAS, 00, R/WHB,
R{WLB
Units ··circuit
v
Cl,C2
v ' ~< ' Cl,C2 v·
v
Cl,C2
v
Cl
v
Cl
v
Cl
v
Cl
v ·····c2···
pF pF
1-384
CoofldentW ~d Ji>ropri~~
....
PaNmeter
Test Symbol Condition
Low-~t~~
lit
si:ai:e,~~···. .. . ..
cUrrent® ~<; 15.:()()?;'
High-input three-' ~ 1 In. ··
state leakage
current on DAL< 15:00 >
V1a=0.4 V
.':1
. Vii,"" V(;~ max.
-50 .µA C.5
Minimum input
Im
current for
.internal pullups
on AI <7:0 >,READY
DAL<02:00>,DAL< 15:07>
Maximum input
Im
current for
inrernal pullups
on AI< 7:0 > ,""RE-.Xb='iY"'.
DAL< 02:00> ,DAL< 15:07 >
v..,-2.4 v v,., ... fi.4 v
-0.1 -1.0 mA C4 mA C4
Power supply current on Vcc
Ice
static
'190 mA C7
High-input
iD.111' 2,4 <Vi.SVCC>
_µA
current on XTLl
.,; Xn..Q,gt:Qunded·
Low-input current; on XTLl
-0.~<V.. < 0.6V,
XTLO~ded
-6.4 mA
*-0.5volts on input pinullows for ringing onunterminamd~!
ac·Electrical.CLaraeteristics
the ana· MHz of The inptl.t and otltput sisnal timing for the DCTll is shown in Fi~reS~f tfirough 25: Mostbfthe
timing parameters listed in tbe tables apply to both 7.fM.Hz IO versions the
DCT11. Parameters that apply only to the 10 MHz version are indicated in the tables. Table 20 lists the timing parameters for the clock-input waveform shown in Figure 21. Table 21 lists the parameters for the powerup and reset timing shown in Figure 2~, Table 22 lists the parameters for the refresh and int.errupt acknowledge timing shown in Figure 23. The DMA timing parameters
shown in Figure 24 are listed in Table 23. The timing parameters for the read, write, and ready
signal, shown in Figure 25, are listed in Table 24.
The following notes apply to Figures 22 through 25.
· Timings are measured at the following output voltages:
RAS,CAS,R/W[B,R/WHB Al<7:0> All others
V0L =0.8 V V01.=0.8 V VoL=0.8 V
V0a = 2.4 V V00 =2.2 V V0 H=2.0 V
· Output timings are measured using a purely capacitive load of 80 pF.
·1485
· Deffo\ .l.it,ons and abbrevia,,t,'i;_o· n·sii;·.'.·'
- J !'i'JncTA~ £rec;uency .
.
--.(Le.)=leadingedge, (t.e.)=trailingedge
.
-F0 p;,,. XTLl, XTLO internal oscillator operating frequency. If an external TTL clockis used, F~p
minimum is 0 Hz (i.e., de). Internal data will not be lost i£ the input clock is stopped at either a
high or low level. The leading (low-to-!Jigh) edge of the clock starts theinteinal tirhlngto produce an output signal (RAS, CAS, PI, etc.). The tr3iling (high-t~-low) edge causes the,~id
to be asserted at the pin of the DCT11. The delay from the edge of the input clock to the outp\Jt
signal is not defined.
.
tcH---1
Figure 21 · DCT11 ClockJnput Waveform
Symbol
(Fop)
(tcvc) l:cH and l:cL ~11and~
Table 20 · DCTU Clock Input Timing Parameters
Description
7.';MHz
lOMHz
Min·. Max. Min. Max.
Operating Freqt)ency
0.1
7.5. 0.1
10
Cycle Time
133
100
Pl.llse Width
20
20
Rise and Fall
10
Units MHz ns ns
l-386
Confidential and Proprietary
-
Figure 22 · DCT11 l'owerup and Reset Signal Timing
'FAlble 21 · DCTll Powerup and Beset T. . .~
Symbol Hst Conditions*
Mm.
Mu.
tl'fl'
PUP(t.e.)to first insttuction fetch
295T 315T
tp11u
PUP(t.e.)to BCi::R(t.e)
99T
lOOT
tUPI'
PUP with
lOOµs
tPMU
PUP{t.e.)to DAL, mode data, valid input
74T
tPllC
PUP(l.e.)to JRlll(l.e.)
lOOns
tllMa
B'Cm{l.e~) to DAL, mode data valid, PDP-11
74T
RESET instruction
tlCll
BCLR width during a PDP-11 RESET instruction
84T
tMHll
B'Cm(t.e.) to DAL, mode data hold
Ons
trur
PUP(l.e.).t.o DAL, input float
250ns
trco
PUP(t.e.) to COUT(l.e.)
T+60ns
*1. Low-current pullup circuits are provided by the DCTll on DAL< 02:00 >, DAL< 15:08 > and AI< 7:0 > lines white the m:IB line is&..serted. This occurs both during powerup and during the
execution of a RESET instruction. (DAU is reserved for use by Digital Equipment Corporation.)
are 2. During a pqwerupsequence, the DCTU provides refresh cycles after the negation of the BCLR
signal if dynamic RAM mode is selected. There 20 refresh cyeles in $-bit mode and 10 in 16-bit
mode, When in static mode, these cycles become NOP{no bus operation) cycles.·The SELO and
SELl lines may indicate the presence of refresh cycles, depending on the setting of the mode
register. No REFRESH or NOP cycles occur after aresetinstructiOn.. ·
· · ·
3. During a ~werup sequenc~, the first instruCfion fetch ()C(t.1!'S at trFF iifter the trailing edge of
the PUP siglllll
4. The DCTll executes an Assert Priority In cycle to. detect any interrupts following a powerup sequence and after execution of reset instruction.
5. ·The actlvity on the read, write and SELO fu.tes depends on the settihg of the mode register.
6. AfterPTJP (t.e.), the/DC'rffcontrol signals RAS, CA'S, PI, SELO-SEU, and R/WHB, R/WLB
are not defined. Qnly the mode register input buffer should be allowed to assert data on the DAL bus during the assertion of the BCLR signal:. This is true for both powetup and execution of
RESET instruction.
'
7. After the};iUP signal; th.:: COT]T signal is used, as flrocessor mode dock. ;J'he COUToperation
then depends onthe setting of 111ode register bit 0 during the assertion of the BCLR signal.
8. t.e. =tciillng edge, I.e. =leading edge .
i-388
Confidential and Proprietary
-
"l·!uii-·,.~.······.·...·:' ;~~p
H-.····-
__________.!
_______ ./
Pl - - - - - - ,
J.Nt£RAUfT ACKN~~~ HAC:JC!JC.!i;'s;~:''' ~
,V''.;i
-
Symbol
l:ocD
Test ConditiOns*
COUT period, pulse,mqge, refresh, ·
IACK, and DMA . . ..
.
Requirements
Min.
Max.
4T
tAsR
AI row ad~ss to RAStl.l!.); set up
tAHR
RAS(t.e.) to AI row address hold ·
tsHF
RAS(t.e.) to SELO(t,eJ
tmt
SELO(l.e.) to RAS(l.e.)
T-83ns T-:60ns
T-123 ns T-23 ns T-80 ns+
tFIU'
RAS width;·REFRESH, IACK
trsp
SELO width, REFRESH
2T+35ns 4T-20 ns
tuo
R'AS(l.e.) to COUT(he.)
tno
COUT(t.e.) to ready (I.e.),
multiple C:ytje exteusfons
tlCSP
SELl width, IACK 1
tsPR
SEL1~,l4CK
tms
SELl(t.e:) to RAl(t.e.}
tvn
RAS(l.e.) to READY~le.)
t11:n
SELl(l.e.) set up to Rt\,S(l.e.), IACK
tWHR
R'AS(t.e.) to DAL< 15:08 > hold
T-15 ns 2T-127 ns
3T-66ns T 45 ns
T-103 ns T-63 ns T-118 ns T~90 nst
tDSll
DAL< 15:08>,IACKdatavalid to RA$(1.e.)
T-48 ns
tKRD
RAS(l.e.) to vector, roll.st be valid
onDAL<07:02>
2T-148 ns T-25 ns+
tiais
SELi(t.e.) to DAL<Oi02> vector hold
Ons
*1. AsSertion of the SELO line depends on mode selection of 4K/16K.
2. Add T(ns) if in long microcycle mode. If READY slips are initiated, add H T(ns) where T= 1/Fop H ==number of READY pulses multiplied by 3 for standard microcycle mode, multiplied by 4 for long microcycle mode.
3. Violation of tYltR will cause unpredictable results.
4 t.e. =trailing edge, I.e.= leading edge
tlO MHz version only
...
Symbol Test Conditions*
COUT width when high
T-3}ns
W(l.e.) to COUT(l.e.)
10 ns; C.; ·
Onst
PI(l.e.) to AI as input, data must
be valid
2T-167ns
PI(t.e.) to AI, next adchess
T-40ns
SELl(l.e.) W(l.e.)
2T-63ns
DMA bus(DAL,AI,R/W) disable to Ons SELO(l.e.)
SELO width, DMA
ST-38 ns
tsss
SELO(l.e.) to SELl(l.e.)
Ons
SELl .recovery, IACK, DMA
T
SELl width, DMA
7T-68ns
COUT(t.e.) to CAS(l.e.)
T+lOns
1-391
Symhol
l:cnE
lest Conditienst CAS(t.e.) to DAL, next address
~ents
Min~: :
'
'\
f-lsru ·
Max.
tMllo
RAS(l.e.) to COUT(t.e.)
T-51 ns
tltl>ll .. ,'R'AS(t.e.) t0DAL, next address
T-118 ns
T.-90nst
tMll~ '
RAS(l.e.) to 00(1.e.), DMA
2T+10ns
tm
;i:tA] wi9th, DMA
5T+35ns ·
1:a.s
CA'S width
tmr
Pl(U.) to AI as input, hold
,' - "\
"
tcsp
CAS{l.eJ to PIO.e.)
3T-90ns Ons T-28ns
tPIP
PI width
2T-47 ns 2T-J7 nst
*1. Add T(ns) if in long mi~e mgde. ~ m~ ~ADY · where
slips are initiated, add H T(ns)
T= lfFor H =number of READY pulses multiplied by 3 for standard microcyde mode and multiplied by 4
for long microcyele moge ·
2. Add 4T for each READY pulst;. ~ ~
3. Add 8T for each additional consecutiveDMA cycle.
. 4. The DMAdevice wertstheDAL<l.5:00> line~.f\l<:7:Q(': lip.e~,and.readandWrite signals,
The DMA device is responsible for preventing three-state collructs andfor ali~,for prechatge
times required by their external circuits.
· · ·· '
5. t.e, ==trailing edge, I.e.= leading edge
tlO MHz version only"
\ >;l
··Pteli.tnioay
.'13. t'~'>i~~?"':t.'Q··.· .
Al
OAL <Wft'rfll' DAL ... .!AEAQI.
A/lit lOELAVEOI SELO
Figure 25 · DCTll Read, Write, and Ready Signal Timing
-
n....1:-;:.....u.. .
.&\"4...al.UUQUI)'
COUT width when high ;~
RAS(l.e.) ~~OUT(Le.)
COUT(t«e:) to READY(l.e.)
RAS(l.e.) to REAbY(te.}
60 l'lS·'
tYl'W
READY pulSe width.
RAS width
tMBO
RAS(Le.) to~OUT(t.e;) ...
T-51 ns
OO(t.e.) toRAS(t.e.)
50ns
R.AS(l.e.) to 'CA$(1.e.)
T+10n8
PI(t.e.) to RAS(t,e.) CA:Swidth
10ns 3T2'· 90ns
CAS{l.e.) PI(l.e.)
row Al addfess toitAS(i.e.), set up
T-28ns T-8Jns
t.\SC
AI column address to CAS(l.e.), set
up
'12ns ·
tlllP
PI(t.e.) to AI as input, hold
Ons
'Ri\S(l.e.) to AI row address hold
T-60ns
t.\HC
OO{l.e.) to AI column address hold T-53 ns
PI(l.e.) to AI as input, data must
be valid
tPIP
PI width
2T-47 ns 2T-37 ns t
PI(t.e.) to AI, next address
T-40ns
CAS(l.e.) to DAL data valid, write cycle
80ns
ConfidentialandPropneta.cy
lOns 2T-U7ns 3T-125 ns 3T-100 nst
2T-167 ns T-90nst
-
···~
m<t.e,) to PI(t.e.)
lOm
IAS(t.e.) to DAL, next address valid
T-118 ns
DAL as address to W(l.e.), set up T-48 ns
~···
PI(t.e.) to DAL, write data hold
T-88 ns
ti.ma
RA'S(~.:C;H:o~~cle.
mode, R/Whold
OO(t.e.) to DAL, read data hold
0 ns
R/W width, standati:l ~le
mode
' 6T-66ns
R/WO.e.) set up to 'RB(t;e.~; ·· standard mode
SELO(l.e.) to lt\S(l.e.), instruction FE'It:H
/ .1, ""1-78 ns
.T-23ns .~.·1 ::>::·~·./ ., J··~·.-+:".'<'<-<~-,,_,,.
RfW(l.e.) to 00(1.e.), standard
microcycle mode
tsse
-,t~X.JT~!J8<U$'- .-Ck_ t.-.,:._·
3T-50nst
*1 T' . :1.Ti£. d 4T 'f. . lllle 1:oa lS J
tn S~u-.--m1.--u.~l nll·.w.,....~.,y._'..-..·J C -ll_J.,U-1U-e an
l ln !1U-·i·'l·g Jl.U_y.,~.:..Q,;l,(.,_~'>s'"T..,1-r.;·t···..··.·v
'·2: AddT(ns¥ifhl'~~~~~; li'&
.·'.. ~·~~,jpJ~T w~
T.;,irjF~J. ::r~;:·i\ ,; :::rt,· z,X: ~;:,;;:.· ·.· ',~,,,; :Li,,, ·. ·. ;;.;·:{;;:±:°F'L. ,.;,;{;i;:·:~;;· ii
·p.r...:nu1nbef:qt:R.b\!''~tnuti1'liedey., W~~.·~ ~; mUl~~~1~ rot
'l(fug~~'Wl:JM:A;:·>V'.·'; ·ii:.
.: · ., ''''''rr:~c2bftxl'.~;h:;: /.iti'·. ···· ·· : .'.',
m 3. The READY signal is an edge-triggered input that is aetiva.~~ as~itffii i;l~'on.it,plli~
When the RitAD! signal is asserted before the leading edge 'of the signal, it is internally
activated by the leading edge of the IlAS signal.
4. A violation of tvo will cause unpredictable results.
5. This timing panuneter applies only to cases where multiple ready pulses are requited, i.e., multiple cycle slips.
6. !£ in delayed mode, the read and write lines have the same timing as the CXS s.ignal.
-
7. SELO is as~·'.t.Q'indicate'at'l .fustruct.~:fetch is in progress·: ~:'"$\l,(lf.,~:m;.o.trs the;£~@;;
indicatods affected· by OCTll mode"Sdection. · 8. *t.e.·trailingeclge,le.... Ieading edge ',,,
t 10 MHz version only
· Interfacing Techniques
to :
",', '.!·'
.')
This section describes typical circuit config\irations that .may be use'd interface the DCTlt
These examples should not be construed ai specifications a:hd reoomniendatiOns. '
Powerup Circuit
m The circuit and voltage waveform foo the powerup function shown in Figure .26. The capacitor
value must be greater than 0.04 µF and is determined by the following:
C=0.05 tll(ms) whel'\:lt11 .ill the rise timeofthe,;\f¢c $Upply v,oltage
Mode ~Lbtadiq
~~ 47:~ a typica,l ~µsed to~ die ;rt,ode ~~,l'heJ3~L~,]#te ~sAA~~uring
the execution of a RESET instruction and is used to transfer the information from the LS244 IC~
die ~e ~t.er on J,4les IM~<()l:oo > ~· PAf,,< ~;ct~.> .. '.fhe,41pu:t'l;nesp:~q~ aJ:\ jnp11t
only when a low is required l:iecause the DCTll provides pullup ,circuit~ Qn~e,. ljn~ whe~. th,e ~.~~,!:s,ass~~~~t,. :·.·
Figu:eii~ Dct11 T;itcal'Af00e Register ~-ClfcJ#
~
r· .' · ClockCircuits
The DCTll clock
cin.-uit
is
cont.:Oll..e..c..l...e...x··t..e..n.u.1..Jli.~.. ~·. ~~r..y..s· .t...a...1..·.~;;;.<~.~.!1'·-
oscillator~
shown
in
Figure 28.
<Y_ ·.
are <'''.!< .:\~-· .'.
For a crystal-controlled clock, the capacitors tm~ typewtth~~wm~c~itive tolerance of ±
10% and the v~~ ~.~e~~If~:1bytbe,.f~ . ·.··· . .. ...
.. . G"T;'.9~~~·r~f¥>:~(~200 pF+£MUz
The T1L input must conform tcitlledoekinprtt specifications shown in Figure 21. The TTL input
must conform to the signal specifications listed in Table 20 and sh.own in Figure 28.
'
~ -
- ':
-'
._ 0
' ' , " _,,~"':_'' -.,-.
-
Interrupt and DMA ~l.:.in~
1
'm The interrupt request ~ignals to th~ DC'."£11 lllUSt he s,t.a,b,le:Jo ~n~,the p~WJ5ation of undefined
states. The AI line'8 requue ex~naU.5KC~ullupresistor.,t9'ttsmstlible opera~~on. Figure 29
shows a flip-flop,used{?~~tl-i!~E~!JPse. The signal delay betw~~the CAS and PI sigpals (105 ns at
7.5 MHz) is sufficient to·assure~hat flip-flop outputs are stable. :
OCT11
CAS
'iiiiii' '_,,.--..... iACi(·-.....__., ·iAC'i( = (SEICi · SEL 1) + (RAs}
Figure 29 · DCT11 TypiCrJl Ipterrupt and BMA Request Circuit
IACK Information Decoding Figure 30 shows a typical circuit used to decode th,e information from 15 interrupt devices.
DAL11 DAL10 DAL09 DAL08
OCT11
i7iCR 1
IACK
~ig:\'c6·A~~s~bNrlS.foAu'. &.; Ass~Fifi:ri··
: ;·
AT IR9 T~f\I~: {J.E.·,JNJE;~N.f).L VECTOR 140).
IACK 15 CORAESPC!NOS TO ONLY CPO ASSERTED (I.~.., Jl'H.Eflf\U,TcV~g;O,R,70h ·
Confidential: and Propmtary
DCTll
BxtftDll Vectors Figure 31 shows a typical cin:uit that enables the DCTU to receive external vector information
from a device on lines DAL< 07:02 > during an IACK transaction. The information is transferred. when the VE'E signal on line Al5 is asserted.
~SULTING
VECTOR··
GNO
(34)
OEV31JCK
(S4i
OEV 2 1AC.K ·
(64)
DEV 1JA.CK
(70)
OEVO"iiCK
LS244
OAL.07 OAL06 OAL05 OAl.04 OA!.03 OALOI!
·iACK = (SELO · SEl.1) + IRAsl
**CAN BE HARDWIRED IF A SINGLE EXTERNAL. VECTOR INTERRUPT IS USED ...USED ONLY WITH BOTH EXTERNAL ANO HllTERNAL V!'iCTOR
(If EXTERNAL ONLY, use IACK)
Figure 31 · DCTll Typical IACK External Vector Circuit
DMA Request Interface DMA requests to the DCT11 can be generated by the circuit showl'I. in Figure 32. The flip.flop is set
by the peripheral OMA. request when the C'.JtS signal is assertef;i provided that the word count
overflow signal is not asserted. When the PI liue is asserted, the :request AlO isgated tQ the DCT11 on line AIO. With the 00 signal asserted, the assertion ol ~,tl'ansattion complete (Te) signal clears the flip-flop. The reset input during the powerup sequence will al$O clear the flip-flop.
TC PERIPHERAL REQ (1) H
RESET
Figure 32 · DCT11 Typical DMA Interface R.ettue:it Circuit
Confidential and Proprietary
1-399
· Section 2-Video Ptocessors and Cont.toilers
Digital's new generation of video chips can be used for terroinllls and display systems and include new display features for larger screen sizes, varable pitch fonts, ~ar screen region:;, and bit·
map graphics generation. 78680 Video Processor-The 78680 video processor (VIPER) is -~pin HMOS cerquaddevice that
is used with the 78690 video control to provide higf:M1p!*i ~el processing of video data including display refresh, window scrolling, and screen updates. ~t;mtnsfers data into and out of the
bit-map memory planes according to the instructions issued by,the 78690 video controller.
78690 Video Control-The 78690 video control (ADDER) is an 84-pin ZMOS cerquad device used
with the 78660 video processor to provide scan timing, systemstat1,1s generation, memory address generation for a video display refresh, and scroll and update opet@tions. DC503 ProF)'tJmmable Videodisplay Cursor Logic-The DC503is'.l.44-pin cerquaddevice used to display a cursor font on the CRT. The shape of the cursor isp~ainrned into the DC503 thereby
enabling the selection of various character shapes or icons to be used as the cursor.
Confidential and Proprietary
- -- ----------~--------------
· Background fill on scroll
· Barrel shifter to and scroll data
· Data transfer in either X- or Z-mode
-X-mode, one word= 16 pixels per plane
-Z mode, one word= \~.pla1}Cs pel;',pixd.
<.~·01_,
,,'\' '_-
,i;' ~
· Description t\.. . :· .i"';., _J·_:N~;:::_.:_,~<; \-. · ."..,_ The 78680 video p~sor (VIPER) is a data.path chip that is ~$ed with dte'7.8690 video control (Adder) chip 1:6 ittjpleroent a high-performance, bit-map 00\phks sy,s~em ,,using a color or monochrome display. Figure 1 is a block diagram of the video processor. .· "~
Figure 1 · 78680 Video Processor Block Diagram
Confidential and Proprietary
2-1
receives commands from the video control and performs the data manipulations required J91'
sc:reen refresh, scrolling of windows, and screenupdates. It provides the bandwidth necdsfil-Y to display up to 850,000 pixels on a high-resofofion ,CRT :at an, ao-Hz refresh ,ritte, It.qontains a
progra.ti1nlab1e bus-width structure and internal buffering for'°'se \Vith64K OJ:'256KRAMs.
· Pill and Signal Description
This section provides a brief description ofthe input '1!1.ild outptit signals and pawer and ground
connections for the 78680 video processor 68·pin Cl$quad package, The pin assignments are
identified in Figure 2 and the signals are sutntnarized in Table 1.
'' '
' "'i '
' '
-, ' ~ ' '
\' ' ' ) ' . '
' ' ' -,- ;
Vbb
Vdd
SYNC
RO/WJf
64
128/ffl
65
LTCLK
66
Vss2
67
Vss1
68
Vss1
01000
2
01001
3
01002
4
01003
5
01004
6
DI005
7
01006
8
Vdd
9
,-------------,
I
I
I
I
I I I
78660 VIDEO PROC:ESSOft jVIPERJ
I I I I
I
CHIP 1
I I
I
1
' I
TOP VIEW
I
(CA VITYOOWN)
I
LI ___..;_..;__._ _____ JI
Vss
Vss Vu
cs
1001
ID02
Vdd
1003
35
1004
34
Vss
33
1005
32 . 1006
31
1007
30
Vss
29
Vss
28
Vn3
27
Vn3
.
.
Fig~re 2 · 78680 Pin Assignthef'Jis
2-2
Confidential and Proprietary
' - - - - ..... ·-.~---~·~.-,,---"""'~----------~·~~-~-~~~-
-.~-~-~~~.......,.,,--""" ......_~--~----------
2.s, 1i~1<J
31-:3J,·
35,36~8
}9.46·:
Q~iP\1t. ·(!,· I.·· ··.··.I~~F~~~~l~~~~M~·.-~,~~. ~· ~~t,:~~
l ·.
. ··ii;~~~ ;!'il:C;l;)l/'i;·(: · .· ::ic;c.· ·
56-59
61* 63
VID<3:0> output SYNC
V~,_Video oo$Ut lines to refresh the
display.
·. [ :Jc"~;'.;'. I :l,;f' '\ ·' f
9,22,23, 26,37,47 48,53,54, 62
1,20,21,24 27-30,34 41-45,51,52 67,68
input
Ground-Ground :reference.
-
BBiittM-ampaIpnt~e~rfaIc!etpSuyig()nuatlsptit,(·L·.·.W. O:. <t>si, ln:;.i,.), ~·".··f.·.''', H.e,·,s. elf:.t'.ies;c,oii,.l. ·li, n.the bit:map data input and
output data to each bit ma:P me~r~en th~.:~;p/Wl,~"~al is high, ·t~ 1:1JO < 15:00 > output
drivers ~re ahigh-im~d~ce state. .
· ..,. .·....
Scroll (SCROLL)-This sig~~ determines which of th~ data words received on the DIO < 15:00 >
lines are to be scrolled.
· ·
~e Enable (PE)-fus signal determines if the bit-map memory may ptocess a write operation.
128~~ 16-1'itM6de(l28/16)-.Wnenhigh, this signal enables the processing6£ 128-bits for screen
refresh and 51.:l,'Olling operations. ~eh low, 16 bit. bit-map 11pdate operations are enabled.
'Bitlmiji Mtmorjr Read/Bit·rnap Mem0ry Write (RI)/WR)-When high/this signal allows the video processor to receive bit-map memory data and the DIO < 15:00 > are a high-irripedance
state.. When low, the falling edge of the RD/WR signal latches the bit-map memory data on the mo.<15:oo>·,u~sand enables'the:QJO< 15:00> 011~pµt drivers.
Latch Clock (LTCLK)-When the· RD/WR and 128/16 lines are high, the trailing edge of the r;rcucsigJ'lallatches itl.})it-m,ap memr.:>ty data on the.DlO< 15:00::-.Jines. When this line isfow
·.·and the 128/i6 line is high, the leadmg eqge of LTCLK causes valid scrolled data to be shifted ~mt on
the DIO< 15:00> lines.
·
Synchronize (SYNC)-Thls pulse init~es all internal control flip-fldps and latches and updates
some maste~slave registers.This signal does not perfol:'m the fµnction of a reset input.
V'ldeo Bus Interface Signals
Vldeci(YJ.P <):fl> )--:--The fi,Sfi:ig ~dge of the ALPHA· r signal shifts the !)Creep refresh data out on
these lines.
·
ALPHAi:_ThJ.s sig~~ ciiu~es the datato be shifted l;othkYID<3:0> lin(!s.
Instruction/Data Bus Interface Sigrul!s '
·PIUtse. J ~se ~
2. ,qC>Cks, {PH,Il and PHI2)-Thes~ . are nonoved~ppi,ng ·clock inpurs that
determ1ne the overall ti!nirig ~d cpn~rol of the video processor.
,
~P ~leet (~S)-.;.Wh~ µne ID<7 :;.,·· is high, thi~. signaHs assertep to allow the incoming 'fnstru,ction to be fatchedan? Cxec~ted. If line ID< 7 > is' low, the incoming instruction is ignored wh~n the CS signal is as~ert~Ci. Wlien receiving data on lines ID<7:0>, the polarity of CS and/or
ID7 is irrelevant.
· ·
' Jruit'ructi6n Dat.i (I0<.7:o> )'..i.;..These input and outPl.lt lines normally remains in a high-
impedance state duringfnput instructions and data. The output drivers are enabled by the internal
execution of 2-axis or controlstore RAM instructions, ..
.··confidential and;Proprietary
-
Preliminary
78680
Power and Ground Connections Power Supply (V00)-Supplies 5 Vdc power to the 78680 video processor.
Ground (V8s)-Ground reference for all internal logic.
Ground (V851)-Ground reference for the output drivers of lines DIO < 15:0> .
Grc>und (V552)-Ground reference for the 1:fCLK, RD~, U8/I6 and SYNC input signals.
Ground (V55,)~round reference for th~ ID< 7:0>, VID<3:0 >, lind PE signals.
Cavity-Chip substrate that connects to V8B pin60..
· Architecture Summary
A typical bit-map processor system, shown in Figure 3, consists ofhigh-speed timingJogic, a local processor or remote processor that performs DMA operations, the 78690 video eontrol, the 78680
video processor, bit-map memory planes, and the color map and shift register logic. The timing
logic generates the system clq1:k _p~e~..The locru p~cessor p~c¥7s the. co!llmands to uppa;t~'the
to video control memory. The video control performs functfons ·that are C9mmon all.!Ilemory
planes such as raster computation operations, scan til.)ling, system status generation, arid.memory
address generation. Each video processor transfers i~9r.tillltfon into and out oi its bit-map mernocy
plane. The output data is transferred through the shift register to a color map and digital-to-analog
converter to provide the composite video to a monitor.
PROCESSOR
MONITOR
·
> 7®90
VIDEO CONTROl...CHIP
!ADOEAl ,
UP TO 24 PLANES
Figure 3 · 78680 Typical Bit-map Graphics System Configuration
Confidential and Proprietary
2-5
...
···78680
The video processor communicates through the instruction/data (ID} bus, the bit-map memory address bus, and the display video bus,
The source, destination, barrel-shift constant; and edge mask data is transferred to the video processor registers through the ID bus whicl:i controls the operatiqn of the video pro{;essor. _The JD bus is used to load and.read registers and to execute direct or indirect instructions. D.ata cap als~ be
exchanged between the registers of other video processors through 'this bus. During a source
operation, the video processor receives the source information from the Video control and locates the source in the bit-map memory. During the destination operation, the video processor receives a
destination code and an edge mask to determine which hits of the data bus are to be written.
The display memory bus transfers the address required to automatically refresh the memory, the scrolling information, and the screen update information.
The display video bus connects the video processor to the display circuits including .the shift
registers,; color map, and digital-to-analog converters.
·
Hardware Description
The following paragraphs provide a brief description of the major hardware functions of the video
proeessor shownin Figure 1.
·
Input FIFO-The 8-bit by 17 word first,in/first-out (FIFO) buffer p~rmits uninterrupted data flow
between bit-mat;> memory and the external di.splay circuits for scree11 refreshing. The maximum
data rate into the input FIFO buffer is approximately 11.5 MHz.
Word-to-nibble Converter-This converter reads the input FIFO buffer, divides the word into 4bit nibbles, and transfers the nibbles to the video output bus. The maximum docking rate of the converter is approximately 17.2 MHz.
Output FIFO-Because of the timing constraints, the video processor stores the scrolled data in the dynamic 16-bit by 16-word output FIFO buffer before returning the data to the bit-map memory. The maximum data rate from the output FIFO is approximately ll.5MHz. Data should not remain in the FIFO buffer for more than 30 microseconds. Any test vector rate should therefore be greater than 1.25 MHz (less than 800 ns per vector),
Barrel Shifter-The 16-bit barrel shifter is used to provide horizontal motion on the screen. The
barrel shifter multiplexes the independent processes of scrolling and updating the bit-map
memories so they occur concurrently.
Fill Register-During horizontal scrolling, the video processor creates voids at the left and right edges of the scrolled regions. The fill register holds the data pattern to fill in the voids.
Left and Right ~otmdary Registers-These registers contain masks that determine the actual bit positions of the edges of the scrolling region.
Logic Unit, Source Register, and Mask Registers-During bit map updates, the logic unit performs logical operations between data in i:he source register and incoming bit-map memory data. The Mask 1 and Mask 2 registers determine those bits within a 16-bit field that the logic unit will modify. The {ogic unit performs 16 possible operations by selecting data in the foreground or
background register for output to the mo< 15 :00 > lines.
Switchyard Logic-This logic transfers 1-, 2-, or 4"bits that are received on the ID bus to the 16-bit internal TWID bus. The number of bits received depends on the selection of full-, half-, or quarterresolution mode. The bits on the TWID bus are transferred to. the squrce, fill, foreground, or background register. The switchyard logic is used for Z-axis bit-map memory update operations.
ID I/O Holding Registers-These registers provide buffering between the 8-bit ID bus and the 16bit internal TWID bus: 1·
2-6
Confidential and Proprietary
-
78680
Edge :M.sk,~The edge mask generator converts an 8-bit code into '.lt.16-bit mask, which· is a window of variable width and position for raster operations. It may be placed anywhere within a 16~bit field.
Scroll Constant Register-This register stores barrel shifter control data. The scroll constant provides.shift magnitude and direction. One register bitdetermines the up or down S<i:roll direction and one bit enables the memory plane when writing scroll data backto the bit~map memory.
Plane Address Register-This register stores the device address, The video control compares the
m; value in this register to the incoming address to determine if a Z-axis insh'tlb:iOn: shol:tld
executed.
the Resolutioo Mode and.Bus-width Mode Registers-1hese regist~ control opeiating modes of.
the video proces50r. ·· . · · ·· · · · . . · .. ·
. ·
~ U.utF~~ier-,f:our registers tbat co~trol the logi<: uni~ al\~ logic unit fUJ1Ctio,ps,,
Control Store RAM (CSR)-Six registers that provide indirect instruction execution woontrol the origin and destination of data transferred on the internal TWID bus and t~ ~ternal ID bus.
Programming Functions The following types of instructions are available to the applications programmer.
Register load-The n-.gister load instructions are used to Idad data iri orie of the 22 addressable
registers in the video processor:. Two registers are available' fdr mede seleet:ion,1four registers for direct address control, six registers for data storage, and ten registers for indirect control functions.
Z-dimension color codes-Color information is received from the address processor and is written
into one of the four data registers-source, fill, foreground, and background. Up to 16 video processor chips can be addressed in paral1elat t}ie same time. D~ng a Z·read cycle, all color data for a specific pixel can be accessed inparallel from.the memory p;l9-0es.
Active cycles-During an indirect data transfer between the·bit·map memory planes and the address processor, one video processor transmits the information; and·the remaining video processors can receive the data and store it in one of three data registers.
The video processor has a progranunoable in~t instructio!;l s.et, which allows the address
processor in a video subsystem to command dil'C3Ct memocy acc~s.{PM.A) operattons between any memory components of the video subsystem. This enables data to be translated, rotated, and scaled. The video processor performs the following data transfer cycles,
Screen refresh-During this cycle, the data in the video· fiiemory is sampled and transferred to the
video circuits.
Scroll-During this cycle, data in bit·map memory is read, barrel shifted, and Written.into the bit-
map memory resulting in a scroll operation within a defined wmCiow of the display.
Bit-map update-This cycle requires an instruction and data. The type of instruction determines
the source of data, indicates the destination of the data, and determines the dispositiQ:n 9£ the data
at the ne\V location.
. ·
Modes of Operation The 78680 video processor operates in the following modes.
Bus width mode-This mode allaws the user to select an effective bus width of 4, 8, or 16 bits to optimize the cost advantages from low-density, partial page displays to high-density RAMs.
Confidential·and Proprietary
2-7
·llD
Preliminary
78680
Resolution mode....;This mode enables the programming of color or intensity changes fuy 1, 2, or 4 bits. An increase in the intensity or color results in a decrease in the resolution on which those
changes can be made. The resolution mode can be used effectively with terminals with low plane counts.
Axis mode-;-;This mode provides a method of data transfer to a group of planes that overlap each other in the Z dimension, as opposed to the normal transfer betweenpixelsin the same plane.
Register Descriptions The video processor contains 22 user-loadable, static registers that combine data and control instructions. The width of the registers is 16 bits. However, many of the registers operate with less than 16 bits. The information written into the registers cannot be read. A register is accessed by the least significant 5 bits of ID< 7:0> lines. Figure 4 shows the register load transfer sequence. The IDbus instruction is a one-byte code and most instructions are followed by a 16·bit data transfer or subinstruction as listed:
Parameter IN
SI
LB HB
Meaning Instruction Shift constant Data source-low byte Data source-high byte
INST: 15
SUBINST:
LOW BYTE: 15
6
5
4
3
2
0
I I 0
0
REGISTER ADDRESS
8
NONE REQUIRED
0
REGISrER DATA BITS <07:00)
a
HIGH BYTE:.! ._ _ _ _R_E_G_1s_Te_R_D_A_T_A_s_1T_s_<1_s_:o_s)_ _ __,
PHl2A _fl'Nil
r;N'Tl,___ _ _ _ _ _ _ _ __
PHI lA
fSlil
rSiTl.________
PHl2B
fLBOl
fUiil._____
PHI 1B
fHBOl
fHii'11_
Figure 4 · 78680 Register Load Data Transfer Model
2-8
Confidential and Proprietary
-
18i80.
The video processor registers, type, and address assignments are listed in Table· 2. Three oftha
registers are reserved,
·
Address (hexadecimal)
0 1 2
3 4
5
6 7 8 9 A B
c
D E
F
10 11 12 13 14 15 16
17
18
Table 2 · 78680 Register Address Assignments
Register Name
Width
Resolution mode
Buswiath S~t;QU C.OJ1S~llt Plane address
Logic function 0 Logic fupct;ion l
Logic function 2
Logic function 3 Data mask 1
Datamask2
Source Fill Leftscroll boundary Right scroll boundary
Background Foreground
Control store RAM (CSROJ
Control store RAM (CSRl) Control store RAM (CSR2)z...
Reserved
Control store RAM(CSR4} · · Control store RAM (CSR5) Control store RAM (CSR6) Reserved Reserved
1:0
3:2 6:0
5:0 7:0
7:0
7:o
7:0 15:0 15:0
;:$;()
1.5:0 15:0 15:0 15:0
·d:o
'6:0
6:0 6:0
6:0 6:0 6:0
Type
Mode Mode
Direct control Direct control Indirect control Indirect control Indirect control Indirect control Data Data Data Data.
l)irect control
,,JDirect control
Data Data Indirect control Indirect control Indirect control
Indirect control Indirect control Indirect control
are Th,~ dat~ and direct c.ontrol rei#&te_rsA thtot,t~p·F (h~~{l~i~~~ ~)6-bi! regis~Fts.t}1at~foad~d
by the ID bus load register commands. The rilask arid source registers loaded by data transfers
during the rasterop cycles. The source and fill registers ~an be lo~ded witha data ~onstant to select a
solid cofot·durfug Z-axis register load commands: The least signffie:antbit of the word determmes
the left pixer aml the most significant bit determines thengfapix'el 011 the display.·
Confi~entialand Pra.prietaty
i-9
-
Resolution mo~The resolution moGleregister controls the action of the maskbhs(mask l, mask 2, and edge mask), the source register, the barrel shifter constant, and the Z-IV(is,-0:ommand. Ibis
mode allows the 78680 video processor to respond as 1, 2, or 4 planes. Figure 5 shows the format of the register and Table .3 lists the functions of the register information. Because each video processor can be programmed for a different resolution, the single barrel-shifter constant should be
truncated for low-resolution applications except when scrolling. Horizontal scrolling should he
used for the lowest-resolution plane to prevent errors caused by truncating to result in the scrolling of an undesired region.
15
:02
01
00
NOT USED
Figure 5 · 78680 Resolution Mode R.egister Format
PLANE
Bit 15:02 01:00
Table .3 · 78680 Resolution Mode Register Description
Description
Not used.
Planes-Defines the planes of response as follows: '
Bit 01 Bit 00 Plane Description
0
0
1
Full resolution
0
1
2
Half resolution
1
0
.3
Undefined
1
1
4
Quarter resolution
Plane I-When plane 1 is specified, each bit in the mask registers and source register controls its
respective mask multiplexer or logic unit bit independently of the remaining bits. The plane
address can be programmed to any value ,and all barrel shifter constants are significant. Dl}dng Z-
its ~x1s operations, the vid~ processor receives or transmits the bi:t that corresponds to ]Jlane
address.
,
'
pili,ne 2-When plane 2 is specified, the ~en' ~nd odd mask or source bits are OR gated, anq the
results are used to control. the corresponding mask multiplexer or logic unit bits. The)east
significant bits of the barrel shifter constant is truncated so that the data will move only by a
multiple of 2 bits. During Z-axis operations, the video processor receives or transmits 1 bit that
corresponds to its plane address and the next most significant bit. The plane address bit must be
programmed to an even value.
2.10
Confidential and Proprietary
-
Planei4-"""When plane4 is specified,.tlie.4maskerSQurcetbits~OR gated and the.results·ate>\lsed , to controltherorresp(lnding. mask multiplexer or logia unit hits. The two least.significant.bits of the barrel shifter'constant ·are ·truncated so that the data will mo~ only by a multiple Pi 4 bits.
During Z-axis operations, the video processor receives or transmits the four bits that c<ttresPQ~ to its plane address and the next most significant bit. The plane address bit must be programmed to a multiple of four.
Bus width_.;;.:The bus width register selects the number of vidoobus bits depending ori the ri1lip~r
of pixek ~uired for .tbe. ~taY, ~.]~.9~Qsi~ P!'9!1e§S9~0ll!lcl.?~§.9,,Qxicl.!'!2 co,n~ro,l in11st .1* set
to the same bus width; Fjgure 6 shows theiregister !Grmat.and Table 4lists thebit selections.and the
reduction in the videci'bus speed that resirlts.
15 {1]
NOT USED
04 03 02 01 00 BUS WIDTH NOT USED
Bit 15:04 03:02'
01:00
Description
Not used.
Bus width,.;.,.Selei:tn·he number.<>E·vidf!t> bm:bits usedfor.the display as follows:
Bit 03 Bit 02 Data'.ln$ \VicJth \Tid~'~utput
· 0
0
: A~bits
· · ·4,Bits ~Y fourth alpha pulse
o
1
~b'lts: ·
··4 hits'Werji:li'.Jthet alpha puts~··
1
0
undefined
1
1
16-bits
4bits every alpha pulse
--> ', .:~.:~-·- - : ,..,-.·,;['· "'·' _'i'\i
Not used.
-
Scroll constant......The Scroll constant register is double buffe:red and isused to select the Je£for right .· horizontaI scrolling and. vertica:fscrolling. operations.· The· data entered. in the.· register becomes active ori the following frame; Figure 1shows the registerformat and 'Thble 5 lists the .functions of ·
the register information.
15 [2]
07 00 05 04 03
00
NOT USED
VERTICAL SCROLL DIRECTION---------~ SCROLL E N A B L E - - - - - - - - - - - - - - - - ' HORIZONTAL SCROLL D I R E C T I O N - - - - - - - - - - - - - - '
Figure 7 · 78680 Scroll Constant Register Format
Bit 15:07 06
05 04
03:00
Table 5 · 78680 Scroll Constant Register Description
Description
Not used.
Vertical scroll direction-Seleets the direc;tion for the vertical scroll as follows. Used to compensate for the asymmetries between the up and down scrolling
directions. O=down, 1=up, left, or right
Scroll enable;_,_Set to enable the horizontal or vertical scrolling of the data accessed. Cleared to disable scrolling and the writing of mfi:mory planes.
Horizontal scroll direction,..-Control the direction of the X scroll constant specified by bits3:0 as follows: Cleared when using the Yscroll constant. O=left, l=right
X-scroll constant-Selects.the number of pixels per frame as follows:
For left scrolls: 0 value= 0 pixel and 15 =15 pixels
For right scrolls: 0 value= 1 pixel and 15 = 16 pixels
Confidential and Proprietary
...
Plane address-The p~e address · e r detern}i~ the Z-axis operation. The plane addresses
must be different for each 78680 video processor. Addresses cannot overlap. A permanent plane
address is set if the scrolling process loads the fill register in Z-mode. If the fill register is loaded
individually by the scrolling process, then different update regions can have di££erent plane ad.dress
arrangements. The register format is shown in Figure 8·and function of the register information is
described in Thble 6.
·
· ·
·
15
(3]
:
06 06 04 03
00
: : '.
--------N-O_TU_S-ED_ _ _ _ _ _ _._.....··.··.~ Bff ADDRESS IN Z-AXtS
z-.Axrs ilL6cK ADDRESS
Bit 15:06 05,04
03:00
'
·
'
'. ·,
'',)'·
e
Table 6 · 78680 Plane Address Register Description
Description
Not used.
Z-access block ad<.\t'ess 0 .to .l-'.".""'Defines the high-9rder bits .of a 6-bit plane address when using more than 16 plan~ or subplanes within a system.
Bit address in Z-axis btocktho 3-This address is set to the bit on which data will be exchanged on the ID b~s'dtiring Z-mode transfers. Fot low resolution applica-
tions, this bit is the low·o:rder bit and must be a multiple of 2 everything that is a
multiple of 4 is a 111Uldple of2.
·
Logic unit function (0-3)-Each of the'fotirl(;igic unit function registers (0 through 3) include 8-
bits of information. The registers combine the word read from destination (D) during a read-
modify-write cycle with the contents bf .the !.puree (S) register. The results are used to select the
color of the foreground and background of the display. The format of the registers are shown in
Figure 9 and described in Table 7.
(4-7]
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
NOT USED
FUNCTION
ENABLE RESOLUTION M O D E - - - - - - - - - - ' SOURCE-----------------'
MASK2----------------~
MASKI--------------------'
Figure 9 · 78680 Logic Unit Function Registers (0-3) Fonnat
Confidential and Proprietary
2-13
- - - - - - - - · -·----·---------------------~.
-
Bit 15:08 07
06 05 04 03:00
Table 7 · 78680 Logic Unit Function (O-l) Register DesCriptiOri ·
Description
Not used.
Enable resolution mode-Cleared to enable the resol~tion mode for the source register. Set to disable the resolution mode. When disabled, the bits are not combined with the adjacent bits and are transferred through the logic unit regardless of the resolution mode register selections.
Source::--Set to select the source register word and cleared to select the complement of the source register word.
Mask 2-Cleared to use the content of programmable mask register 2 and set to use the complement of mask register 2.
Mask 1-Cleared to use the content of programmable mask register 1 and set to use the complement of mask register 1.
Function-Specifies the contents of the register as follows:
Bits
03
02
01
00
Function
0
0
0
0
zeros
0
0
0
1
not (Dor S)
0
0
1
0
(not D) andS
0
0
1
l
notD
0
L
0
0,
D and (not S)
0
1
0
1
notS ·
0
1
1
0
DXORS
0
1
1
1
not (D andS)
1
0
0
0
DandS
1
0
0
1
not (D XOR S)
1
0
1
0
s
1
0
1
1
(not D) or S
1
1
0
0
D
1
1
0
1
Dor (not S)
1
1
.1
0
DorS
1
1
1
1
ones
2-14
Confidential and Proprietary
-
Mask land·..,k2....-Programrnable ma~ registers 1 ~µ2 areu~ to contwl the.l:tits .thi,tt a l'lTMl,
modify-write cycle wilLmqdify. Loading the dJlta mask regi1'Jter 1 also loeiis data mast< register 2 with.the same inf~rmation. The outpat of these reg~ters and the edge register determi~e the bi~s that will be modified by the 78680 video processor. Figure 10 shows the format of the daia m11Sk.
registers.
15 [8.9)
: : : : < ... :.
: I , : ···.··.
READ·MODIFY WRITE BITS
< ·:
Figure 10 · 78680 Data Mask 1 and 2 Register Format
00
: :
Source-The source register contains the SQU1'.'<:.e.W()rdfor the logkunit that is combirted with the destination information to select the foregro~nd and background color for each pixel. The Z-mode address for this register is 00. The register format ii; shown in Fi.Jure 11.
15
[A}
.:
'SOURCE W!:>RO. : ·...
· .·Figure 11 · 78680 Source !RegistenrFormat
Fill-The fill register is double buffered and determines the fill area or blank space in memory that is created when scrolling. Normally, the Z·axisload command is used to select a solid color. If the
are register is loaded directly, all bits that correspond to the same subplane set to the same value.
The data from the register becomes aCt:ive durin~the frame that folioWs.
Because the scroll region boundaries can be contained within one word, the leftmost and rightmost word can be programmed to any bit position. The scroll region boundaries of the 78690.video
control; hoWever, are limited to a multiple of fofil:.When thevide0eonttol is used; theboil.ndaries
must be selected with groups of 4 bits. Only the low 4or 8 bits o.f this register are significant when using the 4- or 8-bit video bus widths, respectively. 'rhefegister for.mat is shown in Figure 12.
15 [BJ
: ".
FILL AREA/BLANK SPACE
Figure 12 · 78680 Fill Register Format
C<:infit;lential and. Proptjeracy
00
2,15
- - ---·~·-------- ------·--·----~~-- -~--~~-~~--~-~~-------- ----~----------~-
~- """"-
-
Preliminary
'78680
Left and right scroU boundary-The left scroll boundary register defines the' boundary for the left
scroll. All bits corresponding to the pixels that contain the left edge of the region are cleared, and all other bits remain set. Normally, all bits from the pixel are cleared on the edge through the most significant bit of the word. If both of the edges are within one word, only the bits from the left edge
through the right edge are cleared.
The right scroll boundary register defines the boundary for the right scroll. All bits are cleared from the least significant bit (LSB) of the left edge through the bit corresponding to the rightmost pixel that are to scroll within the word that contains the right edge of the region. All other bits remain set. If the right boundary is between words (LSB not scrolled) or if both edges are within one word,
all bits are set. The format of the left and right scroll boundary register is shown in Figure 1.3.
I :15 14
(C,DI
13
12
11
10
09
08
07
06
05
04
03
02
01
00
CLEAR/SET BITS
Figure 13 · 78680 Left and Right Scroll Boundary Register Format
BackgrOund and foreground-The background and foreground registers are loaded by the ID bus
register or Z-axis register load commands. The least significant bit of a word specifies the leftmost pixel and the most significant hit specifies the rightmost pixel. The infotmation in these registers is
selected 1 bit at time by the logic unit that transfers the information to the mask multiplexer. The
multiplexer selects either this data or the previous destination data. The background register is
selected by a zero output and the foreground register by a one output from the logic unit. The register format is shown in Figure 14.
I :15
[E.F]
:
1
·OG>rr-Mrnrr me
00
l
LEFT-MOST PIXEL--------------------------~-
Figure 14 · 78680 Background and Foreground Register Format
2-16
Confidential and Proprietary
Control Store RAM (CSRO-CSR6)-The control store RAM registers are CSRO through CSR6-::
wi¥i Register CSR3 is resery~. Duri,ng raster operations, these registers control the .transfer of ciata
the 78680video·.I>rocessor and the cl~ta transfer to. or from othe.r ID bus qevi<;es. Dui:ing
each update memory cycle, the 78690 video control addresses ~he contentsof' the5e re~isters.
When bank J is selected by. the video control, CSRO controls the first read souree, CSRl controls
the second read source, and CSR3 controls the read-modify-write destination. When bank2 iS
selected, CSR4. controts.the first read source, CSR.5. controls th,e seconci read scrqrce, and CSR6
controls the read-modify-write destination. Figure 15 shaws the furmai of the control store RAM
registers and Table 8 lists the function of the register informatfon. ·
·
·
15
(10-12]
[14-16] "'---'-__.__ _.__ _,__ _,_,_,__--'"----'---'---'--r-""--z-"----'.__-i;_...&.._...I
····.N.OTUSEO
c ·f ·' ~;~~~~Ho~·.
BARREL SHIFTER DELAY C O N T R O L - - - - - - - - - - - '
INTERNAL.l,.OAP
ID BUS OUTPUT--_...;.__...;.__.....;...;......_.....;._.....;.--.....;.......;......;..'"'-"-'
Figure 15 · 78680 Control Store RAM Regisrers(cSR.O·CSR6) forlnat.
Bit 15:06 05
04
03:02
01:00
Description
Not used
Barrel shifter delay control-Set during a fast .~(I~ ra!itei ope~~tion' to hOlcl ·the
previous word in adelay register so the remairid:et of each souree 'Woraforrns the
next output word. This prevents excessive read operations tot~ sovrue ~~.j;1lis
bit controls delay register one for CSRO and CSR:4 (for source i} ancl del~&ister ·~
for CSRl and CSR5 (for source2).
.
· · · r· .. ,. · ·~ ·
ID bus output-When a CSR is addressed during a memory rea.ci cycle, thisbi~ ~ .s,t:t
to, enable (ope pfane at a timeis ~o,wed)the transfer of data orfth:e ID bus during a
. memory read cycle.
l
. .
·
.. .. .·. . . .
Internal Load-Select the register to receive the data thro~. the bar~l shifter from the local memory plane following a memory read operation as follows:
Bits
03
02
Register
0
0
none
0
1
source
1
0
mask 1 and mask 2
1
1
mask2
External load-Selects the register to receive the input data from the ID bus following a memory read operation.
Conndentialand Proprietary
-
Preliminary.
·Specifications
The meChanical, ;elec~ric;tl, and environmenta1 ·characteri~tics .and sPecifitations for the 78680
video process6r are &scribed in the following paragraphs. The test conditions for the electrical
values \
are -
as
'
follows
'
.·
unless '·
specified
'
oth~rwise.
. '
· Power supply voltage (V00): 5.0V
· Temperature range (TA): 0°C to 70°C
Mechanical Configuration The physical dimensions of the 78680 68-pin cerquad package are contained in Appendix E.
Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to' the device.
Exposure ·to the absolute maximum ratings for extended periods may adversely affect the reliability of the device.· · Power supply voltage (V00): -0.5 V to 5.25 V · Input voltage appl,ied (V1.): -0.5 V to 6.0 V · Output voltage applied (Vou,): -0.5 V to 6.0 V · Power dissipation {P0 ): 1.9 Wat 100°C, 2.8 Wat 0°C · Active temperature (TA): 0°C to 70°C · Storage temperature: -55°C to 125°C
Recommended Operating Conditions · Power supply voltage (V1>1>): 5 V ± 5%
· Typical operating voltage: 5.0 V
de Elecb'.ical Characteristics . The de electrical parameters of the 78680 video processor for the operatine voltage and tempe~ture ranges specified are listed in Table 9.
2-18
Confidential and Proprietary
-
Symbol Parameter
Test Condition
High-level
input voltage
DIO < 15:00> ,cs;SCROL,
ID<7:0>,SYNC,
RD/WR,l28/I6,
Llt::LK,ALPHAl,
PHI1,PHI2
Low-level
input voltage
DIO < 15:00 > ,CS,SCROL,
ID<7:0>,SYNC,
RD/WR,128/I6,
CTCL.K;AU'HM,,
PHI1,PHI2 '
High-level ,>
output voltage
(all pinsexcept ID,< 7:0 >)
ID<7:0>
Low-level \T6ti,;.,ov
output voltage
DIO < 15:00:> ,PE,
· VID<3:0~
v~~.;;lo. loa=-200µA
ID<7:0>
lo1.=5.0 rnA
Active supply current
Input leakage
current (high]
lnputl~·kage current tlow)
·\T))D=max
····y..,,;..Vo'u {ri:1ax.)
V00 =max. V.. =OV
Short~circuit
output current' DI0<15:00> ,PE, VIP<3:0>
ID<7:0>
\Too=max.
High-Z state output current
Voo=max.
v.... ==OA v
High-Z state output current'
Vn0 =max. V..,,=2.4 V
Requirements Min. Ma;ic:.
Units
v
0.8 v
110
rnA
30
µA
-15
.... 140
mA
30
µA
30
µA
-
Symbol Parameter
Requirements
Min.
Max.
Units
Input·capacitance
c ...
Output capacitance1
4.7
pF
6.6
pF
'These are computer simulated measurements and cannot be tested. In the test simulation, only one output at a time may be short circuited to ground. 2The outputs include the driver current and input leakage current. 3Capacitance loading is for the output drivers and input receivers.
ac Electrical Characteristics The ac timing parameters for the 78680 video processor are grouped according to major cycle timing, minor cycle timing ID bus and video bus timing, and synchronization cycle timing. The timing parameters in the tables are in microseconds unless listed otherwise.
Major Cycle Timing Table 10 lists the symbols, definitions, and specifications for the major cycle timing shown in
Figure 16. A major cycle begins on the rising edge of the PHU clock pulse and is equal to four PHI2 dock periods. A refresh read memory cycle has two major cycles-a read cycle and a screen refresh transfer cycle for editing or scrolling. Every second major cycle must be a read cycle. The video processor provides data to the display during the forward scan time of the screen refresh transfer cycle. During this cycle, a refresh read memory cycle transfers data from bit-map memory to the video hus.
Symbol
tcvc1 .
Table 10 · 78680 Major Cycle Timing Parameters Definition
Period of LTCLK Period of PI-Ill or PHI2 Period of major cycles Propagation delay of LTCLK rising to valid data on DI0<15:00> Propagation delay of 128(i6 switching to an updated value of PE.
Requirements (ns) Min. Max.
54.5 148 *
32
37
2-20
Confidential and Proprietary
78680
Symbol
tu01 tu02
Definition
Hold time of RD/WR or 128/16 switching to the falling edge of LTCLK. This parameter must be met relative to the last falling edge of LTCLK in a major cycle. Hold time of DIO< 15:00> or SCROLL to the ,falling edge of LTCLK ·
Propagation delay of RD/WR going high ta a higtr.:finpec
dance on DIO < 15:00 >
Nonoverlap time, PHU to PHI2
Pulse wjdth high of i.TcLK
Pulse width high of PHU or PHI2
Setup time of RD/WR switching to the falling ~ge of
LTCLK. This .parameter must be satisfie<l·relative·tothe
first falling edge of LTCLK in a major cycle.
Setup time of 128/16 rising to the rising edge of CTCLK.
This parameter !l)ust be satisfied rela~ive to the .first rising edge of ~LK in a major cycle 41Jd applies only to ·
transitions between minor and major write cycles (guaran-
teed by not exceeding tr01).
Setup time of 010<15:00> or SCROLL t<!hthe falling
.edge of LTCLK
.
Setup time of RD/WR.or 128/16 switching to the first
falling edge of PHil in any major cycle
Propagation delay of RD/WR going low to valid data on DIO<l5:00>
*Minimum tcYc} =4 PHI2 cycles or 16 ALPHA cycles
Requirements (ns) Min. Max.
10 13 3.0 18 15.5 18 55.5 36.5
13
6.5 0
26.5 3.5 30
Conficlential and Proprietary
2-21
lt::._ru·-·-·-·L
PHI 1
·-:1 L.-
l'HI 2
MAJOR CYCLE
RD/WR
J1.·. ". +-t-------1--tcvcJ--·--- ----+-i..i
t tsu10
128/ f6
DIO
PE
Figure 16 · 78680 Major Cycle Timing
Confideni:ialand Proprietary
-
Minor Cycle Signal Timing Table 11 lists the specifications for the minor cycle events including a memory cycle shown in Figure 14. A memory cycle starts at the beginning of a major cycle and must end by the beginning of the next major cycle. Only.one memory cycle must be in progress ~ta time.
Symbol
Definition
tD2
Propagation delay of· PHI2 rising to -valid- data on
DIO < 15:00 >. This pat!t.cleter applies oiily ~ Z-axis
write operations.
Propag~tion ~ayQf ID data~tup to f{)Jlowing edg~ qfthe.
second PHU in a ;minor cycle to valid data on
DI0<15:00::>.
tHo3
.. Hold time of aifasserted, C:S tQ···tlje falllrij'fedg~ ofPHIZ.
Hold time of DIO < 15~00 > to the second falling edge of
PHI2 in a minor read.Cy<;Ie:
Hold time of DIO < 15:00> to the falling edge of RD/WR.
Propagation delay of the ri~ing edge of, 128/1b t9
DIO < 15:00 > ri.Sing oi falling.··
Setup time of an asserted CS to the falling edge of PHI2.
Setup time of DIO < 15:00 > to the falling edge of the
second PHI2 in a minor cycle.
Setup time of DIO< 15:00> to the falling edge of RD/ WR.
Propagation delay of RD/WR going low to valid data on DIO< 15:00>.
Requirements (n~)
Min. Max.
63
79.5
13 0
0
38.5
40
50
13
3.5
30
Confidential md Prt,>prietary
78680'
PHI 2
PHI 1
RD/WR
1281 fij
tzH1, tzL 1
cs
j 'sus I';: tHo4
·isusj'
tHos
!;::;: tpo
.. ;,,M_j_.------ xu11110, DIO m...,..,...,,..,...,..111,...,..,..zv,....,...,..111.,..,..,.0!!810100000~ .DOUT ··
ID
··. . f-1D5j
Figure 17 · 78680 Minor Cycle Signal Timing
2-24
Confidential and Proprietary
-
PrelimibarJ. ··
ID Bus and Vtdeo Bus $igna1 Tuning
Table U lists the specifications for the ID bus and video bus timing shown in F~re 18. A major
cycle begins on the risi1'ig edge of the PHl2 dock pulse with 4 PHl2 dock periods. PHil and PB.12
tntist have the same"j::ierlod and must not oyerlap. Ute alpha clock has atiming period one~foorth of
· the PHI2 clock and has coincident: rising edges.,
Sytnhol
tn
tD4
tHZl
tPWm tPWu tIU tsu1 tzw
Time delay to valid data on VID <3:0> is 10 ALPHA
cycles plus tD4 after start of present major cycle. (Not
testable).
·
Propagatiqn . ·delay .of ·PIIP ., l'.ising to':valiel"d~~ ..on ...
VIP<3:'1>> while ALPHAli.S~. l : : .·· ' f . · .
' ,. ; ·, ·, '
'
'.
'
'·'
\
- ' ,,
Pericxfof ALPHA.
Pro11ag~~n.d~y qLal~.~ng·t9~Yali4.4@~ o~
VU::i< 3:~ >~ Tuerate?f.~~~~~~·?~~~'~qt,h;e
the bus width mode:
full page= once/f.LPJ/# .~ock.. · ,
half page= once/tWo ALPHA clo~ks
one-fourth page= once/four ALPHA clocks
Hold time of ID<7:0> to the falling edge of PHil or
PHI2.
Propagation delay of PHil or PH12 going low to a High-Z
condition on ID< 7:0 > .
Pulse width high of ALPHA.
Pulse width low of ALPHA.
Input rise time (fall time) ID < 7:0 >
Setup time of ID< 7:0 > to the falling edge of PHil or
PHI2.
Propagation delay of PHil or PHI2 rising to valid data on ID<7:0>.
R~ts(ns)
Min. Max.
36
3:o
29
15.5
3.0
40
18
18
26.5
13
3.5
40
2·25
· - - - - - · - ·~~---------·---------~--------·--·-·-··
-
PHJ 1
PH12
ID
n-1:-1-~,
.&I.~']"''
i ALPHA ! '
Y" dmmzmw.obllmmzmzik ._._ 1/4 PAGE
Figure 18 · 78680 ID Bus and Video Bus Signal Ttming
2-26
Confidential and Proprietary
··.mM
S~.Cyde.T'uning
Synchronizatioooccurs once per£wneduring theverticalretraceperiod. When the SYNCsigrtal is
asserted, all internal clocks halt in at= 0 +state. The video processor suspends all data processing
an9 and1resets the counters that are used to transfer data out to the video.bus QUt of and into the ID
and data bus. The ll'CLK has eight time periods within a major ¢ycle. These periods can occur
witbirithe cycle to aci::ommodate·differenffypes of JMmoties. Ta1'le 13 lists the syriclironization
timing parameters shown in Figure 19.
,
Sydibol
tH
Tabte·u ·7;8680 S~tion CYcle T~ Parameters
Ddinition
of Use th~ i;isit:lg ~ge Pf:!II2 as the iµajor cycle foundiiry
except aftet>:async~e. {Not:·testable). .
R~ents(ns)
Min. Max.
The number of AtPHA cycles tha'r must elapse before
or PfU2·gqeslc1,\r;f~r
9, Bi.. ' .
Vt~
' .
fjrst
' .
~e!lftei:a.
.. '
1syNecycleis1,5,
l:cvcJ
Period of major cycles. (Not testable).
*
302
Skew between PHI2 falling and ALPHA falling.
±5.0
tsus
Setup time of SYNC going low to the first falling edge of
ALPHA.
302
tsu,t
Setup time of CTCLK falling to the rising edge of PHI2.
,:.26~~ '.'*· ·,, ·· '.lf.
tin order for the t3f·specjficafii0n(Tuble lZll.P W.~d~ dat:ij fJ'll;ll~d:t~~loa~edint~ t~in:ternal .FIFO bu££en.·Therefore;: 'th~fits~ t~ ~J,TCLJ( ap4 its,,[~a.t~data. dm-iag a, lllliliQr·rea<i cycle must precede the third rising edge of PHI2. *MinimWA~vc}'."J4 PH12 cyc~sor lf>:ALt'I-li\ ~fll~,
2-27
-
Preliminary
~~~~: _ ......l....:. ::::::tc_vc_3:::::::......i:.l.,..:.:::::::::::::::_tc_v_c_3':·:·::::::::::::::;.:!__
SYNC
LTCLK
PHI 1
PHl2
ALPHA
Figure 19 · 78680 SynchronWltion Cycle Timing
· Interfacing Techniques
The· video processor communicates with the· video subsystem using. the three TTL-compatible
ihterfaces shown in Figure 3'-the system interface, the bit·niap interface, and the display interface.
The system interface lines consist of the chip select (CS), the systemclocks, and an 8-bit, bidirectional instruction/data bus. The system interface connects to the address processor memory planes and other memory planes.
The bit-map interface includes the 16-bit bidirectional data bus DIO < 15:00 > and the LTCLK,
128, RD, SCR, OL, PE, PHil, and PHI2 signals that control data flow on the bus. The bit-map interface connects to the bit-map memory planes.
The display interface includes the video bus and the signals that control it. The video bus
VID < 3:0 > connects to the display circuits. The control signals include the ALPHA clock pulses
and the PHil and PHI2 system clocks pulses. This bus is used during screen refresh cycles.
The instruction/data (ID) bus is used to transfer information between the video processor and controllers. It is used to load and read registers and to execute direct or indirect instructions.
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Preliminary
78680
Interface Connections
The following circuit and connections are recommended for the proper operation of the 78680 video processor.
Power-The 78680 video processor operates with a 5 Vdc power supply. Ten of the chip pins connect to VDD and one connects to V88 · No special filtering is required. The 5 Vdc connects to the VDD pins and the power supply ground connects to Vss. Pin 61 (Vim) is the voltage generator output and must be connected to the pin 60 (cavity) which is the substrate.
Powerup latch-The video processor includes a circuit to ensure that the ID bus is in a high-
impedence state during the powerup sequence. A latch is set during the powerup sequence to force the ID bus to this state. The deassertion of the CS signal clears the latch.
ID bus lines-Connecting a 50-pF capacitor to ground on each ID bus line compensates for component variations in the interface design. Multiplane single-module systems may not require these capacitors. However, the etch capacitance to ground and to other signals should be evaluated. The noise margin should be limited to 0.2. V to 0.3 V. The total ID bus load capacitance should be
less than 400 pF.
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· Programmable display resolution · Programmable screen synchronous interrupt · Displays up to 1024 by 864 pixels at 60 Hz noninterlaced · Supports video memory add~&:spa~e.up to 8.Khy 8J{ · Up to 24 bit planes ·
· Raster operation!! at rates of 0.5 to 8milli~n pixdS per sec<>nd
· Smooth scl'?lling:~:lrectangular windows · Hardware clipp~ m the window boundaries · Hardware: rotatjq-i and noninte~r scaling ofsource
· Hardware p0lygon fill with stipple pattern or solid color · Addressing of pixels in X- or Z-mode · DescripQon '
The 78690 video ~ntrol (Adder) is an 84-pin; ZMOS VLSI cltlp used with: the. "Z~80 video
processor (V~per)drlp when buil~ a high-per~0rn:iance, bit·m~p graphics syst6n with a color or
monochrome Jisplity system. The video ~l I*'torms fujictions cornill~n-re all bit-map
memory planes, such~ scan timing, system status generation, ru:P memory addtess generation for
screen refresh and·· sc:reen update$.. The video co.tttroLsends. cbmmands to ·one or Mote video
processoi;. which perform the data manipulation for each memory plane. Figill:¢ l: is a block
diagram of the video control.
' ·.· ' '' ·
Figure 1 · 78690 Video Control Block Diagram
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Preliminary
·78690
· Pin and Signal Description
This section provides a brief description of the input and output signals and power and ground connections for the 78690 Video Control 84-pin cerquad package. The pin assignments are
identified in Figure 2 and the signals are summarized in Table 1.
DAT DAT DAT
DAT DAT
DAT DAT
02 04 06 GND 08 10 Vdd 12 14 GND Vdd
DAT DAT DAT
DAT DAT
DAT DAT PHI
03 05 07 Vdd 09 11 · GND 13 15
2
DAT01 OATOO ADD5 ADD4 AD03 ADD2 AD01 ADDO
BS A8
AD
iNTf
Vdd GND VSYNC CMPSYN BLANK
S\iNCR
SYNC
iNT
AEO
Mnnnro~~ITT~~~~~~OOWWEW~~
H
D
76
52
77
51
78
79 80
,------- - --,
50
49
48
81
I
82
I
83
I
I
I I
47 46
84
I
I
45
I
78690 VIDEO
I
44
1 2 3 4
I
CONTROL (ADDER)
I
43
I
CHIP
I
42
I
I
TOP VIEW
II.
I
(CAVITY DOWN)
I
41 40
39
5 6
IL ____________ _JI
38
37
7
36
8 35
9
34
10
33
11
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND ID Vdd ID ID Vdd CAS PHI SAA. Vbb
1
4
6
4
IOCTL ID
ID ID
ID
ID GND PHI ADS SPARE WEO
0
23 5 7
3
Figure 2 · 78690 Pin Assignments
PHI 1 MAD10 MAD09 MAD08 MAD07 MADOO MAD05 MAD04 MAD03 MAD02 MADOl GND Vdd MADOO SCROL FORCE 128 MRD WE3 WE2 WE1
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Pin
1 2
10 11 57-60 63-66 69-76 77-82 83
s~ .
RD INIT
INT
rum
DAT< 15:00>
ADD<5:0>
Table 1· 18690 Pin 8Jtd Sigtml Summary
Input/(i)utput Definition/Function
input
Read-Indicates a t:elld or write processor bus cycle.
input
lnitiiilize-=Initializes thevideo.control .and process6rbtis.
output output input/output
·. I~rupt-Initiateuprocessor intenupt request.
,, :'" '; -_
'-·<·'-·.,
' -.:.
~est...,,.Indicatesa .])tdA access reque,st.
· Data <15:00 >~Data bm lines
input
Address < 5:0 >-Address bus lines
Patastrobe......:Enablesdata transfers on the in~
or external data bus.. '
.
84
AS
5
VSYNC
6
CMPSYN
7
BLANK
8
SYNEil
9
12
14-16, 18-22 25
SYNC IDCTL ID<7;()>
CAS
26 27
28 29,.30 32-35
PHI3 PHI4
ADS
Spare WE<3:0>
36
MRD
37
128~
input output
output
· . output ootput
ir\put
Addn!ss strobe-Initiates an interface transfer·
Vertical synchronize-A video vertical synchronization signal.
Composite synchronize-.A video composite hori-
zon~ syt:tcitr<)tli~~n sigtU117.· '
.
Syndlroni~ feilli'($t;_A' sy1iem s~on
'cYcile reqiie$t:
.SynchroniZC7$ypchronizes'the Vidl!O subsyste'm.
', . ----. :·,, ,.__ ,. ,. _;
/·-: -, "-rf::;;;, ,_.
··
"
_ ·- _ , --
input/®t;pUt
Jnstru~ioQ/I>".ta ·. <r;;: i ;O :> ......lnstruetj~9,ata, ..bus
.lines.
···.COlutM address· strobe,..+Bit-mitpmemc>tY·~
clock'~·
inpQ.t input ,
output output out;put
Write enable~Ertables the writing of the bit-~ap
memory:·
Map read-Specifies a read or write cycle o(the bit-
maprm:mocy.
128/16-Indicati::s a major or minor bit-inap memory cycle.
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-a
Pin Signal
38
FORCE
39
SCROL
output output
40, MAD<lO:OO> outputs 43-52
53 PHil
input
55
PHI2
input
31
VBB
3,62,67 Von 17,23, 41,54
input
4,61,68 GND 13,24, 42,56
input
.··.7&;96
Fortie.;_Enables:a down scrolling writi:: cyde. Scroll-Selects refrf;sh read memory cydes during scrolling . . Memory address < 10:00 >-Row and column address lines for bit-map memories. Phase input 1-Phase 1 clock signal. Phase input 2-Phase 2 clock signal. Not used. Voltage-Power supply 5 Vdc.
Ground-Ground reference for signals and voltage.
Processor Interface Signals Read/Write (RD)-This signal informs the video control that the processor access is a read or a write cycle. The processor access is initiated by the assertion of the AS signal.
lnitiaJi7.e (i'NIT)-This signal causes the video control to be initialized to a known state. The processor interface becomes inactive forcing the ID bus drivers to a high-impedance state until the neyt SYNC signal is asserted.
Direct Memory Access Request (REQ)-This signal provides a hardware flag for the bits that are
erfubledin the status register. The enabled bits are selected by the request register.
Interrupt {iNT)-This signal provides a hardware flag for the bits .that are enabled in the status register. The enabled bits are selected by the interrupt register.
Data (DAT <15:00>)-"'These are bidirectional,. parallel data lines, through which the video control interfaces to the processor. During a read operation, the bus master enables the ITS input and the DAT< 15;00 > information drives the external data bus. During a write operation when the DS signal is asserted, the DAT< 15:00 > signals drive the internal data bus.
Address (ADD< S:O> )-These inputs select the video control register to be accessed.
Data Suobe (DS)....;;Durii:tg a register read cyt:le, this signal transfers data to the external data bus.
During a register write cycle, it transfers da,ta to the internal data bus.
,~ss .Stro~ <:p)-This signal initiates a video control .interfacetransfer. It.performs a chip Sclect function and latches the information into the addressed register.
Monitor Timing Signals Vertical Syncluonization (VSYNC)-This signal in separate vertical SYNC signal for displays that
.do l'.).Ot ~e a ~mpos,ite SYNC signal.
Video Composite or Horizontal Syn~tion (CMPSYN)-This signal can be programmed as either composite SYNC or horizontal SYNC signal.
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78690
Video Composite Blank Signal (BLANK)-The video control uses this signal to blankthe monit()r.
System Synclu:onUation Request.(SYNCR)'"'.'""The video control asserts this signal to request. the external clock generation logic to.generate a SYNC cycle. The clock logic asserts the SYNC s~al and stops the Q:ocks for a predetermirl~ number ofserial cycles.
System Sytlchroruzation (SYNC),..,..The ~ternal clock generation logic sends this signal to the
video control and video processor to syq.chronize the video suhsystenh This signal coru:rols all of the timing generators on the chips.
In Interface Signals . .
.. . .
·.· ....·..·. .
Chip Select Control (IOCTI.)-The ID bus requires t'o/O chi(>.~ reW5ters to allow,i,nd~n<font
selection of a video controlfor ID transactions. Whe,n theincn.:·~ignal isalow level, itselects the
cliip update chip selection tegistet When this s1grial is,a hig}l !~~l.'it selects'the scroll select
register.
.. .
· ..
. .
..
Instruction/Data Bus (ID< 7:0 >)-This bus is a comaiunications pat,h betwee~ the vi<leQ control
and video processor.
·
.
·
Memory Interface Signals Address Disable (ADS)-This signal is normally a low level:to allow the video control to drive the memory interface. When this signal is high level, all update activity ii; stopped and all refresh and scroll activities continue. All update cycles on the bus are no operations (NOP}· 16-bit read cycles.
Bitmap Memory Write Enable (WE< 3:0 >)-These signids erutble writing to groups of four bit map memories.
Memory Read/Write (MRD)-This signal indlCates a read or a writecycle. A high level indicates a read cycle and a low level indicates a write cycle.
128/16 Bit-map Memory AccesS Width,._This signalinqicat~ the type of cycle that the memory interface is abou.t to initiate. A high level specifies· the start of a 128-bit major cycle. A low level
indicates the start ofa 16-bif cycle(Onsisting of two back-to-hack minor cycles.
Force Signal fut Down ScrolJing Write Enables (FORCE)......This signal must occur during a down scroll to cause the write enable sign:al!s: ofthe memory planes, with video processor chip plane enables, to write back the data during a scroll write-back cycle,
Scroll Enable (SCROL)-This signalindfoates which refresh read .memory cycles are to be written back for scrolling.
Bit-map Memory Address (MAD< 10:00>;.._'fhese lines provide the row and column addresses
for the bit-map memories that are multiplexed from the video controL An address is available for
each column address strobe(CAS) pulse.
·
Clock Signals
.
Phase Input 1to Phase Input 4(PHI1 to PHI4)-These clock inputs provide the timing control for
all operations of the video control.
·
Column Address Strobe (CAS)-This input is a bit-map memory access strobe,
Power and Ground ConnectiOns Power Supply (V00)-Supplies 5-Vde power to the 78690 video control.
Ground (GND)-Ground reference for all internal logic except for the output drivers.
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-·
· Architecture Summary
Preliminary
78690
A typical bit-map processor system, shown in.Figure3, consists of a local processor or remote processor that performs DMA operations, the 78690 video control, the 78680 video processor, bitmap memory planes, the color map and shift register logic, and high-speed timing logic. The video
control performs the functions that are common to memory planes which includes local processor
interactiort, raster operation computations, scan timing, system status generation, and memory address generation for screen refresh and updates.
The video control communicates with the microprocessor through the microprocessor bus and with the memory through a display memory address bus. It communicates with the video processors through the instruction/data bus.
The video control contains 64 registers that can be directly or indirectly loaded by the local processor to control the scan timing, refresh and scrolling operations. The registers are used to generate interrupts, report status, and to read and write data in the bit-map memory. They also communicate with the instruction/data bus.
PROCESSOR
ADDRESS/DATA BUS
78690 VIDEO CONTROL CHIP
!ADDER)
MONITOR
78660 DATA DATA CHIP
(VIPER)
MEMORY
UP TO 24 PLANES
Figure 3 · 78690 Typical Bit-map Graphics System Configuration
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Confidential and Proprietary
The 78690 video control communicates with the processor through the data and address bus, with
the bit map memory through the. bit-map memory address bus, and with the 78680 video
processors through the instruction/data (ID) bus. ·
The local processor sends the commands to the video control to update ~emory,, The video control performs furictions such as local ProcesSor inl=etll~on., ,raster computad?n ope:ra'~ions, 'scan timing,
system status generation, and memory addres$ generation to re&eSh afid update the display, that
are common to all memory planes. ·
,,
·
on disetilf, # The displaymemotjr ~~ss blls:ti:an,sfers th~ a~fiSesto µpd~te the
to a~tomatkally
refresh memory, and to scroll the information
display. . . . ' . . ·. ' . '
The instnictjonfdata bus loads theregisters ~ the '{ideQ proc~ss~t :With ~~r destinatio,n, barrel shift constant,and edge maskdata. Data is also ·~ci)alliled t~';lgh. tliis b11S'. ~if.18 ascreen
update, the new infor~tion is tran#erred to th~ vide() .Pic;iCess~; J)Ur.itlg a sqi,irce openitiofit the
video corttrol Sends acD<le s(,ecl£ymgs~~l ?,r ~e'? an~fabafu!l shift C:o~taqt tpatslilits the
source data to align with the destination;-nuring a desH.iiationo~nLt,io,n, thfvideo cont:rolse~s a
destination code and an edge mask instructing the video processer that si:)ecifies'whidi bits of the data bus are to be written.
Hardware Description The following parilgraphs provide a brief description of the roajar.ftardware. bloclufonctiens ofthe
video control. Refer to:Eigure 1.
Processor Interface-'.This logkreCeives the 1~iu;ameters and eoOUtlands from the. local. processor.
The processor interfaee handles registet accesses and controls tirxlmg and·all necessary bus $ignals
to allow the video control to act as a bus slave to the local processor ot :OMA deVice.
mControl-The ID ctmtrol selC¢ts ttle clup select regist<:S tJu\fc:fett:rmine whjch video processors
will update the bit-map memory md which ones will perrorirt scbjllirig. The:update process uses
the ID data first-in/first-out (FIFO) buffer and the scroll prb't(\s5 i:lses.· the IDS and lCS regrsterll;
mData FfilO-Dtiring the bit"map memory u~¥' process; the video control uses the ID fhta
FIFO buffer to transfer data to and from the bitmapithroughtheVideo processot:It isalsti used 1:o
load the video pn:ices$0r registers.
X and Y Scan Logic-The X-scan circuits generate the X components for the l'llonitol' display, the system synchroflization ~gnals, the ref~Sh and.$Cwll ~S$eS~.~Jif<: scroll e~able $i~. The Y:scan circuits generate theYromponents for themonfror displa~~Y'stem sy-nchroruzation signal, refresh and scroll addresses, and determities the ~ve times fot)ftollmg.
Sync Conttol~This airouit controls horizontal arid verticah1ynchroriization.
Serial Memories-The ~rial memory. contaitls holds. the con;unands and data · for update
operations.
Main BNsenham Cont1'01....:this logU;. CQ~trols d>,e1sei;ial loilc that coroput~i;; the ~s.§eC!uence
for raster operations; It reeeives eommand and mode fuformation from the serial memories and
generates status bits and control flags for the niain .control and address collecti~ subSections. A
raster operation copiesa contiguous section of bit"~ mem0ry(souxce) into a different locationof
bit-map memory (destination). The modes of raster operations supported are normal raster
operations (rasterops), linear patterns, and polygon fill.
for · source Source Generator-The. source generator produces a sequence of addresses the.
data
during ra8ter operations. In normal mode, i:t"traces arect:angWar section of bit-map me~ocy.I~
a linear pattern mode, it loops on a small rectangle to create. repeating pattern until the destiriaticiii
completes its operation. In fill mode, it computes the address sequence for one edge of a polygon.
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78690
Destination ~l'!ltot7'.""The destinationi0generator produces a sequeµ~e of adc1resses for the
destinatiqn data during raster opt;.t:ation~. Ip, the normal and linef1.t pattern modes, .it traces a
parallelogram by drawing a sequence of arbitrarily oriented parallel lines as the origins follow a
traiectory defined by another arbitrarily oriented line. Infill mode, one part of the generator
computes the address sequence ofthe second edge of the polygon and another part of t!Je generator
fills the polygon by dra~ lines between the two polygon edges.
·
Source 2 Logic-This logic generates a second sequence of addresses for source. data. The video processors may access data from two sources and combine it with the destination data, Source 2 data is generated by adcilng an offset value to the destination address. It can be used to generate a
tile pattern that repeats the modulo of ariy power of 2 between 16 and 512.
Index Logic-The index logic permits an offset value to be added to the source.and destination
addresses to support the scrolling process. Scrolling is performed by physically moving data in the
bit-map memory. When data is moved, the index may be changed so that the processor is not
required to recompute its display list. The index logic allows data to be written into the hit-map
memory during the scrolling process.
.
Clipping Logic-The dipping logic prevents the writing to the bit-map memory locations beyond a predefined rectangular window. Status is generated in the main control section to inform the host processor of the clipping action.
Barrel Shift Constant/Edge Mask Logic-This logic computes the data required by the video
processors. The barrel shift constant indicates to the video processor the amount of the source data
shift necessary to align it with the destination data. Each source operation generates. a barrel shift
constant. The edge masklogic defines the left and right edges of the destination. Each destination
operation generatesan edge mask.
·
Ad~ss FIFO Buffer-This buffer receives the ~rial logic signals for addresses and flags . for destination update ;.vrites, source 1 update re~s, and source 2 update reads. The FIFO multiplexes this data so it is available when needed.
.Address Control-This logic controls the sequence of memory cycles on the. memory interface
including the refresh (read), scroll (write), and update (read-modify-write) cycles.
Write Enable Control-This logic controls the interface to the bit-map memories. The write enable logic generates the following:
· The timing signals to pass addresses from the RAS/CAS multiplexer to the memories
· The low 3 bits of the CAS iiddresses during major cycles
· The write enable signals for the memories during both scroll and update read-modify-write
memory operations
· The SCROL, MRD and 128/16 signal for memory
· The memory interface clocks and timing from the CAS docks
RAS/CAS Multiplexer.......This logic combines the X and Y address togenerate the row and column address for the hit-map memories. This multiplexer also assures the refreshing of the :bit-map
memories.
~FW1Ctions
.
.
. ..
.
When the Joca.J processor .or DMA controller loads the com.J.p.and register, the video control
~s one of the following co.IUma.qds:
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78690
InstruCtion/Data-The inst,niction/data commands are used t.o configure and control the video
processor.
Rast.et-The raster commands are used to initiate raster operations as defined by the information previously loaded into registers.
Processor/Bit-map· 'Jiiuisfer-These. commands ate rised to to transfefdata between the local
processor or DMA controller and the video control:
·
Cancel-The cancel·.command terminates an ut>AA~ ·.operation in progress .and .clears all raster
operation status registers. ·
·.· ·. '
·· '
Modes of Operation
The 78690 video control operates in .the following,modes.
N~ ~ode'"'C"'.Thls. mpde i§ use4 for. :otstet Ofl<lrat~ons when sou~ :L ·.~ ~,~ngle and the
destination is a parallelogram, or SOll1'.Ce, 2 ill offset from the destination. Soui:Ce 1 may be scaled up
or down by a noni.9tege,t: scale faq:oi: WlieP pos~hle, the video control ope;~t:es pµ the entire
memory bus for operations. Q~~1 .it opei;ates pn one pixel at a time. This acti()n ~.u;ansparent
to theuset.
Pattern Mode-This mode is used to generate dashed lines and thick patterned lin~ on the display;
Scaling is possible in this mode because the source records its own size !J.lld i!! not dependent the
destinati9J},. In this mode, ~-yj4ep (;Q,~iri::>ioperatesfo slow tn9de, ·' ·. . ·· ·
,.-. -
'
- ,,
_,, .· ... ~· ~ ·''·"'' - ' -
--·
' ~
',.' _, - 1
..
··
Fdl Mode-This ~e..is used, tx;J,_fill an..IU'Eta be~n two ~s..J?o~ the slo\li( source and
destination create ~ vectors, The .fast destination draw:s ;~th,er hc?rim11tal or vertical lines
between the twoie~vectcm·· ;Hp.weyer, ~ yectoi;si ~Y inte,t'.'se;ct~t;b.<>tl;iet, ~ add,i.ti9n, the area
to a baseline may~ ~ille<lso d¥it one ed~ is,a fix.eclYvalue.ot;~{~.~ va,lµe.~ The vi.deo control
uses fast mode fot}rorizontalyeciPrsanq slow: mode.for vertical vectors and the mo4e$ am be used
together with the (ill\{Uqde·. , .
.
.
'ide Mode:.-This mode is usedto fill intersecting polygons so thafthetexture ofeachis continuous
across the intersection arid applies fo solirCe 2 orily.
Register Descriptions The 78690 video control
cont.a...i..·~
~,· 4.
.·· reiis4u's
.·· .· that
i;:an
commurii.c.a····~. e
~th
tl,}e
processor
data/
address bus. Three of these registe);s are ~e,i:ved foi: test purposes.·Theregis~s may be load~
directly or indirectly through the adc,lress Counter (register 0) using anautom.crementil}Ode. Thest:; registers contain the parameters £9r '1'~t~r ~rations, ~o set the system timi.t,ia; .~ to.control the
operation of the video contr()l..Jhe fo~~tlg rule~·<l!?l?ly: . , ...·. .. .. ,
· The registers are write-only: unless o~ specified.
· Local processor coordin!ttes lifer to image(before aciding inc{d~ue$. ··
-.
'
" -
'
;
'
' ' - - ,.
'.,
- '' · ' - '
w
' -- )' ,_
~
,,,
'"
· Device coordinates describe a physical P'>sition O[l the SC~n With'o', 0 beingJPe Upper-left
comer with X:increasing to the right and-¥ incre.asiflg downward.
·
· A DMA controller may load the registers so common combinations are adjacent thereby requiring a minimum of address register loads.
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2-39
-----··-----·------·---""---·
. ;frt..n.w.-u1!u-n!~a-:-ry
11lbte 2 · 78690 Register Address Assignments
Address* Name
Width Function
Control Registers
0
Address counter (ADCT)
1
Request enable (REQ)
2
Interrupt enable (INT)
3
Status (STAT)
4
Reserved for test
5
Spare
6
Reserved for test
7
ID data (IDD)
8
Command (CMD)
9
Mode(MDE)
A
Command (CMD)
15:00 13:00 13:00 13:00
DMA device interface to registers DMA status flag request enable Interrupt enable for status flags Video system status
15:00 14:00
07:00 14:00
ID bus data Command register (same as command register location A) Sets varioos raster operation execution modes Command register
Scroll Registers
B
Reserved for test
C
ID scroll data (IDS)
D
ID scroll command (ICS)
E
Scroll X Minimum (PXMN)
F
Scroll X Maximum (PXMX)
10
Scroll Y Minimum (PYMN)
ll
Scroll Y Maximum (PYMX)
12
Pause (PS)
13
Y offset (PYOF)
14
Y scroll constant (PYSC)
15:00 15:00 13:00 13:00 13:00 13:00 10:00 13:00 14:00
ID bus scroll data ID command register for scroll process
Left boundary of scroll region Right boundary of scroll region Top boundary of scroll region Bottom boundary of scroll region Screen coordinate to set pause status Screen to memory coordinate offset Vertical scroll distance in one frame
Update Control Registers
15
Pending X index (PXI)
16
Pending Y index (PYI)
17
NewX index (NXI)
18
New Yindex (NYI)
19
Old X index (OXI)
IA Old Y index (OYI)
1B
Clip X minimum (CXMN)
lC
Clip X maximum (CXMX)
lD
Clip Y minimum (CYMN)
1E
Clip Y maximum (CYMX)
lF
Spare
13:00 13:00 13:00 13:00 13:00 13:00 13:00 13:00 13:00 13:00
Pending X index Pending Y index NewXindex NewYindex OldXindex OldYindex Left clipping boundary Right clipping boundary Top dipping boundary Bottom clipping boundary
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78690
Address* Name
RasterCon~l~
20
Fast source l dX (FSDX)
21
Slow source 1 dY (SSDY)
22
Source 1 X origin (SXO)
23
Source 1 Y origin (SYO)
24
Destination X origin (DXO)
25
Destination Y origin (DYO)
26
Fastdestination dX (FDX)
27
Fast destination dY (FDY)
28
Slow destfuation dX (SDX)
29
Slow destination dY (SDY)
2A
Fast scale (FSC)
2B
Slow scale (SSC)
2C
Source 2 X origin (S2XO)
2D
Source 2Y origin (S2YO)
2E
Source 2 Height and
Width (S2HW)
2F
Error 1 (ERRl)
30
Error 2 (ERR2)
8cre@ Fo.rn.iat CcmtrPl Rqi$ters
31
Y scan count 0 (YCTO)
32
Y scan count l(YCTl)
33
Y scan coUnt: 2 (YCT2)
34
Y scan count 3 (YCT3)
35
X scan configuration (XCON)
36
X limit (XL)
3 7
Y limit (YL)
38
X scan oount 0 (XCTO)
39
X scan count 1 (XCTl)
3A
X scan count 2 (XCT2)
3B
X scan count 3 (XCT3)
3C
X scan count 4 (XCT4)
3D
X scan count 5 (XCT5}
3E
X scan count 6 (XCT6)
3F
Sync phase (SYNP)
*Hexadecimal notation
Width Function
13:00 13:00 13:00 13:00 13:00 13:00 13:00 13:00 13:00 13:00 13:00 13:00 13:00
13:00 07:00
Fast delta X for source 1 Slow delta Y for source 1
X coordinate of source 1
Y coordinate of source I
x coor.vJin~te. of destination origin
Y coordinate of destination origin X component of fast destination vector Y componentof fast destination vector X component of slow destination vector
Y component of slow destination vector
Fast vector scale factor Slow vector scale factor
xeoordfuate of source 2
Y ccx>1'diP$!.te of 5911rce 2 Size of source 2 tile
13:00 Error adjust for slow destination 13:00 Error adjust for fast destination
13:00 Vertical timing
ll:-00 Vertical timing 13:00 Vertical tilllfug
13:00 Vertical timing 08:00 Cycles, bus width, number of refresh rows 13:00 Width limit on refresh
13:00 Height limit on refresh
15:00 X sdm connt 0 15:00 X scan count 1
15:00 .x scan col.lnt 2
15:00 X scan count 3 15:00 X scan count 4 15:00 X scan rount 5 15:00 X scan count 6 14:50 Sync phase adjustment
Confidential and Proprietary
2-41
-
Preliminary
78690
Status and Control Registers
The video control logic contains status and control registers used to initiate requests and interrupts, report status, select modes of operation, and initiate command functions. These registers are described in the following paragraphs. The status and control register formats are shown in Figure 4.
15 14
: [ l [OJ
DATA. FUNCTION
15 14 13
I : [11
NOT USED
I :1& 14 13
12] NOT USED
6
5
0
= DATA (BIT15 0)
ADDRESS COUNTER
= ADDRESS (BIT1 5 1)
0
REQUEST ENABLE STATUS REQUEST ENABLE REGISTER
00
INTERRUPT ENABLE STATUS INTERRUPT ENABLE REGISTER
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
[ T
I
r
131
....__._i_. __...J,.. .J_
T _L
I
I
J..
_L
1 ..1_
r
J..
I
I
_L
..1_
'I
-1
I _L
I .1.
I ..1_
I ..1_
]
NOT USED
vERTICAL BLANK-' cLIPPING WINDOW DETECT cLIP AT RIGHT BOUNDARYcLIP AT LEFT BOUNDARY cLIP AT BOTTOM BOUNDARY cLIP AT TOP BOUNDARY
0 SCROLL DATA READ D DATA TRANSMIT READY ID DATA RECEIVE READY A DDRESS OUTPUT COMPLETE RASTEROP COMPLETE RASTEROP INITIALIZATION COMPLETE
s CROLL SERVICE
pAUSE COMPLETE
STATUS REGISTER
Figure 4 · 78690 Status and Control Register Formats
2-42
Confidential and Proprietary
Preliminary
l :15
171
ID BUS DATA ID DATA REGISTER
15 14 13 12 t 1 10 00, 08 0.7
00
!BJ
~ TEST
'---....----"~--~~---- ---------~
SELECT FUNCTION
.lD COMMAND
RESERVED SOURCE 2 ENABLE SOURCE 1. ENABl.E - - - - ' DESTINATION ENABLE-----'
COMMAND REGISTER
15
[9]
NOTl)SEO
PEN U P / D O W N - - - - - - - - - - - - - " ' DESTINATION INDEX ENABLE/OISABLE-..__.-....._.._.._ __ SOl)RCE 1 INDEX ENAllL.EIPISA8LE----.,..-....-----__. HOLE FILL. ENABLE/DISABL.E ..__·- - - - - - - - - - - - - - - - " FILL NORMAL/MSEUNE__,._.._______........,,.......,_,....._ _.....__..._""'---' FILL AREA SCAN XIY A X I S - - - - - - - - - - - - - - - - - - - - - '
MOOE REGISTER
15
: :
00
(SAMES AS (8} COMMAND RfGISTERI
COMMAND REGISTER
Figure 4 · 78690 Status and Control Register Formats (Continued)
Confidential and Proprietary
-
Preliminary
··1s69o
[OJ Address Counter-The address counter (ADCT) provides indirect access to the video control registers and is used with standard bMA controllers. The register information 1s described in Table 3.
Bit 15
14:00
Table 3 · 78690 Address Count.er Description
Description
Data Function-During write operations, this bit is set to cause the following:
Bit 15 = 0: The data in the counter is transferred to the register selected by the counter and the counter is incremented.
Bit 15 = 1: The low 6 bits of data replace the original contents of the address counter with
the following exception. If the address counter is pointing to either the ID data register (IDD) or to the ID scroll data register (IDS), the most significant bit of the data is ignored and all 16 bits are loaded into the appropriate ID register and the counter is incremented.
When reading the address counter, the register that the contents of the address counter points to is accessed and the counter is incremented. The INIT signal clears the counter.
Data/Address-Contains data in bits 14:00 if data function bit 15=0 and address
information in bits 06:00 if data function bit 15 = L
[1] Request Enable Register-The request enable (REQ) register is used to select any of the corresponding 13 bits of the status register to be enabled to assert a request. When a status condition sets a bit in the status register, a request will be generated if the corresponding request enable bit in this register is also set. The DMA controller normally sets a request bit one at a time as it waits for the specific event to occur. The register information is defined in Table 4.
Bit
15:14
13 : 0 0
Table 4 · 78690 Request Enable Register Description
.Description
Not used
Request enable-Each bit corresponds to a bit in the status register. When a request bit is set, a request (REQ) signal is generated when the corresponding bit in the status register is
set. The request register allows a DMA controller to control data and request status.
2-44
Confidential and Proprietary
-
[2] lnt.errupt Enable Register-The interrupt (INT}~ register is used by the local processor to select any of the corresponding 13 bits of the status register. When a status condition sets a bit in the status regater, lin interrupt will be generated if the corresponding interrupt enable bit in this register is also set. The register informatlonis defined in Table 5.
Bit 15:14 13:00
~, ' r
Not used
Interrupt enable (iN1')._EE!':h bit ~~pen~ to .a hit in.~. status register. When a
interrupt enable bit is set, an J.q~pt: request.(IN.'I'.) ~i~ is generated when the corres.poP4ing .statPS conditlqp. c~p~s t.he status hit. to be set.. The interrupt enable
~ter provides. the loqd p~of.;with interrupt con<J.it:ions·
[jJ Status :Register-The status (STAT) registet is a ~d-ohly re~ster.·that provides indications of the internal progress of the via~ control. 'J'he ~gistetinfQrrnati!)tlis 'deScri:bed in.Table 6.
Bit 15:14 13 12
11
10
09
08
07
'Description
Not used
at of Vertical blank'--This bit is set the start the·vertfdil blank interval and cleared by
writing 0 to this bit position.
' ·''
Clipping window' detect-Set during a destinaticfu write cycle to indicate that part of a
raster operation was inside the clipping tectailgle; e~ by writ~ a zero to this bit
position.
Clipped right boundaty-Sefduii.ng a destination w'rlte cycle to indieate that part of a
raster operation was clipped at the right boundary. Cleared by writing a zero to this
position.
Clipped left boundary-Set during a desti~tj9~ \Vdte cycle Jo indicate fhat ~tof a raster operation was clipped at the left boundry. Cleated by writing a zero to ills position.
Clipped bottom boundary-Set during a destil1lltipn ~te cyge to inqicate,.~t part of a
raster operation was clipped at the bottom boundary. ·Cleared by writing a zero to this
position.
Clipped top boundary-Set during a destination wrlte cycle to indicat;e that part of a
raster. operation was clipped at the top boundary. Cleared by writing a. zero to this
;' '
; ·~
'
·,
'
'
',
'
' ' ,· !'
- ' -, · ,.
position~ .
·
ID scroll data-Set by the video control when a new data word can be1oaded into the ID scroll data register. Cleared by the ID command to the ID scroll command register.
Confidential and Proprietary
2-4)
·-
;,.,.6:.i:tm:.·.'.;-
:;\L:J'OU7V
Table 6 · 78690 Status Register Delcription · ·.
06
ID data transmit ~acly-Set ~indicate that data,can beloadecl.Jnto the ID data register
during an ID command. Cleared when the .qew ;cb data command is loaded. This bit is
also set at the completion of a Cancel command to indicate that the ID FlFO buffer is ·
dear to load another command. The Cancel command initially clears this bit. When a
raster operation or PBT command is not in progress, loading the ID data register or
asserting the INIT signal will set this bit.
05
ID data receive ready-Set when the ID data FIFO buffer has a word to be read. This bit is
cleared when the FIFO buffer is empty; when a raster operation, PBT, or cancel command
is loaded into the command register; or when bus initialization occurs,
04
Address output complete-Set when all addresses calculated by pending raster operations
or PBT commands, have been used· indicating that update parameters such as clipping
boundaries, indexes, ID data, or other commands can be loaded. During a hi.t-map to
processor (BTP) commands, this bit is set when the !DD FIFO buffer is empty. Ids also set
by the cancel command or INIT signal. Cleared by loading any raster operation or PBT
command.
03
Raster operation complete-Set at the completion of raster operations or PlIT address
calculation when no further command is pending. It indicate that other raster opera.tions
can be loaded such as dX and dY pairs, source 2, or scale factor, that the mode register can
be loaded, or that a new but not different raster operation can be initiated. It is also set by
the Cancel command or INIT signal. Cleared by loading any raster operation or PBT
command.
02
Raster operation initialization complete-Set at the completion of the initialization of a
raster operation or a processor-to-bit-map transfer. It indicate that the source 1 origin, the
destination origin, or a new but not different raster operation command (except· PBT
command) can be loaded. It is also set by a Cancel command or theINIT signal. Cleared
by loading a raster operation or PBT command.
01
Scroll service (frame sync)-Set at the start of frame when new scroll parameters can be
loaded. Cleared by writing a Z«::to to thi!i bit.
00
Pause complete-Set when the screen refresh process reaches the Y address of device
coordinates in the pause register. Cleared by writing a zero to this bit.
[4] Test Register-Reserved for test purposes.
[5] Spare Register-Not used.
[6] Test Register-Reserved for test purp6ses.. [7] ID Data Register-The ID data (IDD) register is the ID data bus port from the s~x-word FIFO buffer. During PBI commands,.data is transferred between the processor and bit-map memory through this register.
[8] Comm8n:d Register-The command (CMD) register is used for all commands by the update process and c.an be accessed from either address [8] or [A] (hexadecimal). The register information is described in Table· 7.
2-46
Confidential.and Proprietary
18ble 7 · 78690 Command Register Description
15:13 U 11 10 09:80
07:00
NOP (No operation)-Reserved and test functions as follows:
Bit 1': Re8cnr(;d andn0l1"Dally ~ro
Bits 14:13: Tust and notmally zero
S2E (Source 2 erulble).:.2Secona'8ource enable
SlE (Source 1 enable)-First source enable
;,.,''
;:· i
(RJNC) Select Function-Selects the function of the corr,t~ as follows:
Bit
Function
09 08
0
0
Cancel all active and pending commands '
0
1
ID command'
1
0
Raster operation oo~
1
1 .·.Processor hlt-map (PBT) transfer 00,m~
[9] Mode Register"'-The mode (MJ)E) register setnhe rast~i! operation exeetiti6rl triodes. The
register information is described in Tuble 8.
,
Bit 15:08 07
06
05
04
'Description
Not used
Pen up/dn-Selects the pen position as follows:
Bit 7 =0: pen up to disable writing
Bit 7= 1: pen down to enable writing
Destination indexing-Controls the indexing of the destination as follows:
Bit 6 =0: disable Bit 6 = 1: enable
Source 1 indexing-Controls the indexing of source 1 as follows:
Bit 5 =0: disable Bit 5 = 1: enable
Hole fill-Controls the hole fill operation as follows:
Bit 4=0: disable (normal single pixel wide destination) Bit 4= 1: enable (all other destinations}
Confi&;ntialand Ptoprietatjr
2-47
-----·-·--·--·--· ~--·
-------·-----·~~---·--------------~~-·
...
Bit 03
02 01:00
Description
Fill area-Selects the fill area as follows:
Bit 3 =0: Normal two-edge fill
Bit 3 =1: Fill to a vertical or horizontal base line depending on the scan direction of the
previous bit.
. .
Fill area scan axis-Selects the fill area to be scanned as follows:
Bit 2=0: Scanned parallel to the X axis
Bit 2 = 1: Scanned parallel to the Y axis
Mode-Selects the operating mode as follows:
Bit
Mode
01
00
0
0
Normal: Source 1 is a scaled destination area.
0
1
Reserved
1
0
Linear pattern: Source 1 is from.the dX and dY registers.
1
1
Fill: Destination slow generator computes the 'W.' edge vector. Source
I .generator computes the "B" edge vector and the video control fills
the space between the vectors.
[A] Command Register-The functions of this command (CMD) register are the same as the.[8] Command (CMD) register.
Scroll Registers The scroll registers determine the scroll activity on the display. During active scrolling operations, the scroll registers must be loaded by the scroll process before the start of the vertical blanking. The video processor performs vatiousfonctions dtiring the vertical blanking depending on the type of scrcill activity pending for the next frame. The scroll register formats are shown in Figure 5.
2-48
Confidential and Proprietary
I :15
ICJ
I :15
{DJ
I :15 14 13
(E] NOT USED
Pieliminary
78690
00
SCROLL PROCESS DATA ID SCROLL OATA REGISTER
:
ID SCROl.l COMMAND
ID SCROLL COMMAND REGISTER
00
:
: ::
LEFT BOtfl'llOARY VALUE
SCROLL X MINIMUM 8EGIS1'.ER
: : : 00 "
15 14 13
NOT USED
:
RIGHT BOUNDARY VALUE
SCROLL X MAXIMUM REGISTER
00
: I
15 14 13
00
NOT USED
TOP BOUNDARY VALUE SCROLL Y M1NIMUM REGISTER
Figure 5 · 78690 ID Scroll Register Formats
Confidential and Proprietary
2-49
VIM...l.iB.L___iilllW-6-----------·-·-- ~.W.!.J.,W....,..,.,.._ ,._ ___....,___........., ..
-------~-.~-·--·-~------·-
.
[11
I
I_.15
..
.
._14...__13...__...___,__...__.
.
. _...__ .
.
.
___ _.
.:_ .
.
.
_..
.
.__.
____00-'
NOT USED
BOTTOM BOUNDARY VALUE
SCROLL Y MAXIMUM REGISTER
15
12 11 10
00
NOT USED
COORDINATE FOR PAUSE STATUS PAUSE REGISTER
15 14 13
00
[13] 1 :
NOT USED
SCREEN·TO·MEMORY OFFSET Y OFFSET REGISTER
15 14 13 12 11
00
{141
~· NOT USED
SCROLL MAGNITUDE
NORMAL/ERASE SCROLL DIRECTION
Y SCROLL CONSTANT REGISTER
Figure 5 · 78690 JD Scroll Register Formats (Continued)
[B] Test Register-Reserved for test.
[CJ ID Scroll Data Register-The ID scroll (IDS) data register contains the data to be transferred to the ID bus during the scroll process ID commands.
[D] ID Scroll Command Register-The ID scroll command (ICS) register is the ID command register for the scroll process. Commands are transferred through this register without interfering with uixlate activities.
2-50
Confidential and Proprietary
[E] Scroll X Minimum Register-The Scroll X minimum (PXMN) register information determines the left boundary of the scroll region and specifiesthe left-most pixel. The X boundary may only be specified to amultiple of four pixels. The scroll boundaries are not affected by indelc values and the registeris double buffered so that the values loaded become active at the start of the following frame.
[F] Scroll X Maximum Register-The Scroll X maximum (PXMX}register information determines the right boundary of the scroll region. The scroll boundaries are not affected by index values and the register is double buffered so that the values loaded become active at the start of the following frame.
[10] Scroll Y Minimum Register-The Scroll Yminimum (PYMN} register information determines
the the top boundatyof the scroll region. 'lq.c; §~ll boundaries. ~.not affected by index v=dues and
the registeris double buffered so that the valµesloaded becomeutive at the start of the;following
frame.
·
[11] Scroll Y Maximum Register-The &toll¥ maximum (PYMX) register infonnatiom determines the bottom boundary of the scroll region. The scroll boundaries are not affected by index values and the register is double buffered so that the values loaded become active at the start of the following frame.
[U] Pause Register-The pause (PSE) register contains a yaluchthat specifies which scan, when
displayed, will cause the pause complete (bit 0) of the status resister to be set or a second pause
event to be queued. This register is double buf£ered so that the 1ll:'Wvalue loaded begins at the start
of the following frame and continues through the frame. ·
[U] Y Offset Register-The Y Offse~ (PYOr) ~gister contains the value when added to the device
coordinates become the memory coordinate ranging from 0 to height of display portion of the bit-
map memory. This value is the same as the value storedin the X ~m.it register minus1. The register
is double buffered so that the values loaded become active at the start of the following frame.
[14] Y Scroll Constant Register-The Y Scroll Constant (PYSC) register specifies the magnitude
and direction of the vel'.'tical SQ'Ollin one frame time. The ve~tigd dista!lce specUied by tM. vlll.ue in
this register and the horizontal distance specified by the value in the scroll consta!lt register of the
78680 video processor will be sctt>lled. The register information.is described in '.fable 9.
Bit 15:14 U
12
11:00
'.Gible 9 · 78690 Y Scroll Constant Register Oescription
Description
Not used
Normal/Erase-Specifies the scroll condition as follows:
Bit 13 =O:Normal scrolling Bit 13 = 1: Erase mode
Scroll direction-Specifies the scrollingdirection as follows:
Bit 12 =0: Up, left, or right scrolling
Bit 12 = 1: Down scrolling.
Magnitude-Determines the unsigned vertical magnitude of the scroll.
Confidential and Proprietary
2-51
78690
Update ControlR.egisters The update control registers, shown in Figure 6,. contain index values that are added to the raster operation addresses to adjust the addresses for scrolling and to specify location of the regions on the
display. The pending values are automatically loaded into the new registers at the start of the next frame. If no scrolling takes place, the loading of the registers is not required. The pending register
values are loaded first, followed by the new values, and then the old values.
I :15 14 13
[15]
00
NOT USED
X-INDEX VALUE
PENDING X INDEX REGISTER
15 14 13
00
[16]1~-_._~...__..__..__..____....__...__..._ __,_ ~ _.._....... .....:..._·_...__..___,...__,
'----......----·~----------------.....--------------------------
NOT USED
Y-INDEX VALUE
PENDING Y INDEX REGISTER
15 14 13
. 00
(17)1.._ _.__...__....__...__....__ _ _....__.....___.....____._......_ _...._........_ _..._ _.___,
NOT USED
X·INDEX VALUE
NEW X INDEX REGISTER
15 14 13
00
(18]
-------------------------' ~'NO-T-US-E-D--------------------Y·-IN-DE...X.....V. ALUE
NEW Y INDEX REGISTER
Figure 6 · 78690 Update Control Register Format
2-52
Confidential and Proprietary
.15 14 13
[19]
: :r
........ ...._____,__.__..__~~'--~~'--~---'--~~~---~~~~ '--'--'--~--'~----"
NOT USED
X-USED VALUE
OLD X INDEX REGISTER
15 14 13
00
15 14 13
I[18]
q:
~
NOT USED
: :
x-M1N11\11uM ctiPPtNG eouNDAR·v v.0.Ll.!Ei
CUP X MINlf;iUM REGIStE;R
rn · 14 13.
I : [1 CJ
NOT USED
:
X-MAXIMUM CUPPING BOUNDARY VALUE
15 14 13
00
[10]
.._____,____...__~~~~~~~~~~~~--..,,,.-~.---...--~~~~~~~.-----'
NOT USED
Y-MINIMUM CLIPPING BOUNDARY VALUE
CLIP Y MINIMUM REGISTER
15 14 13 [1E]
NOT USED
Y·MAXIMUM CLIPPING BOUNDARY VALUE CLIP Y MAXIMUM REGISTER
Figure 6 · 78690 Update Control Register Format (Continued)
Confidential lltld PooPrietary
00
2-53
-
[15] ~ X IndexRegister..,,...The pending X index (PXI) register contains.the Xinde:x:.value for
the next frame.
[16] Pending X lndexRegiS~.;_..The pending Y i:hde:X (PYU register contains theY i:hdex value for the next frame.
[17] New X Index Register-The new X index (NXI) register contai:hs the new X index: value that applies to the data that has been moved during the current frame.
[18) New X Index Register-The new Y index (NYI) register contains the new Y index value that applies to the data that has been moved duri:hg the current frame.
[19] Old X Index Register-The old X index (OXI) register contains the old X index value that
applies to the data that not been moved.
·
[1A] Old YIndex Register-The old Y index (OYI) register contains the old X index that applies to the data that has been moved during the current frame.
[1B] Clip X Minimum Register-The dip X minimum (CXMN) register contains the X minimum
value of the left clipping boundary. The value is a device coordinate and not affected by the index:
values. ·
·
CllP [1C] X MaximuntRegister-The clip X maximum (CXMX) register contains the X ma~imum
value of the right clipping boundary. The value is a device coordinate and not affected by the index
values.
[lD] Clip Y Minimum Register-The clip Y minimum (CYMN) register contains the Y minimum value of the top clipping boundary. The value is a device coordinate and not affected by the index values.
[1E] Clip Y Maxbnwn Register-:The dip Y max.imum (CYMX) register ccmtzjns the Y fI\azj,mum value of the bottom clipping boundary. The value is a device coordinate and not affected by the index values.
Raster Operation Control Registers The raster control registers, shown in Figure 7, are used to control the raster by selecting fast and slow operations, the source anq destination origins, and scali:hg.
2-54
Confidential and Proprietary
-
l :. : : 15 ... 14 13
[:?OJ
: :
00
~ NOT USED
DELTA X VALUE
FAST SOURCE 1 DELTAX REGISTER
15 14 13
00
DELTA X VALUE SLOW.SOURCE 1 OElTA.X REG.ISfER:.
15 14 13
00
[22]
....... ~--~~~~~~~~ ~--~--.......--'--'-......;.....:.-_;......;._.;..;.;.......;;,;__;...;;.:..:;.;...~--'
NOT USED
X·CDORDINATIO VALIJ£
15 [23J
14
13
12
11 · 10
:
Cl!!. ;08
: :> : 07 ,,~ 05 04
03
02 01
:
00
NOT USED
Y~COQRPINATs\le.LY.IL.
.SOURCE 1 Y Q~IGIN REGISTER
15 · 14 13 NOT USED
: : : : : : :
: ..
.. ...
00
X-COORDJNATE VALUE
DESTINATION X ORIGIN REGISTER
Figure 7· 78690 Raster Operation Control Register Format
2~55
L·: : : 15 14 13
[25]
:
00
NOT USED
Y,COORDINATE VALUE
DESTINATION Y ORIGIN REGISTER
15 14 13
00
[26]
: :
....... ~'-:--~~~~~~~..,._~~~~ ~---,~~~~~~~~~~~
NOTU$ED
X-COMPONENT
FAST DESTINATION DELTA X REGISTER
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
[27]
: ..
NOT USED
Y·COMPONENT FAST DESTINATION DELTA Y REGISTER
15 14 13
00
[29]
NOT USED
X-COMPONENT SLOW DESTINATION DELTA X REGISTER
15 14 13
00
I : 1291
~ NOT USED
Y-COMPONENT
SLOW DESTINATION DELTA Y REGISTER
[ :15 14
[2A]
13
:
00
NOT USED
·VECTOR SCALE FACTOR
FAST SCALE REGISTER
Figure 7 · 78690 Raster Operation Control Register Format (Continued)
2·56
Confidential and Proprietary
...
I : : 15 1't 13
[2B] ~ NOT USED
15 14 13 [2C]
NOT USED
I : : 15 14 13
[201
._______.._..
NOT USED
Preliminary
:
.;
VECTOR SCALE FACTOR
SLOW SCALE REGISTER
78690
00
I
: : : : : o"l
:"',
/
. 00
:.-
X-COORDINATE
seurice 2 X00RIGIN REGISTER
: : : :; : ::· ti· Y'C0tl'.R.PINAT.£i
: : l00
·.
SCURCI; 2Y ORIGIN REGtSTSA
15 (2EJ
ENABLE/DISABLE _______...._ _ __._....._.......___..
....... . RESERVED~-------_,_.......__._.-....
_.___.~~..._
.
..
....._..__,,,_...,
15 14 13
00
ERROR 1 REGISTER
15 14 13
00
{30]
NOT USED
ERROR ADJUSTMENT VALUE ERROR 2 REGISTERS
Figure 7· 78690 Raster Operation Control &gister Format (Continued)
Co.nfidentialand.l?roprietary
..·.,.···.... ..,..__, _,,_,m...,._,..,.._ _ _ _ _ _ _ _ _ _ _ '~_.1Wfi!18ill)>?t:~"""'"'..,.."'"""-1!il!i""''""'m'"'illMil
..,~11..,
~-------~--~---·
··Preliminary
[20] FastSoutcel DeltaXRegister-Thefast source 1 deltaX.(FSDX) register cohtains the value for the fast+ or-delta X for source 1.
[21] Slow Source 1 l>eltaYRC!gi.st.er-The slow source 1 delta Y (SSDY) register contains the value
for the fast+ or-delta Y for source 1.
[22] Source 1 X Origin Register-The source 1 X origin (SXO) register contains the value for the X coordinate of source 1.
[23] Somce 1 Y Origin Register-The source 1 Y origin (SYO) register contains the value for the Y coordinate of source 1.
[24] Destination X Origin Register-The destination X origin (DXO) register contains the value for X coordinate of the de8tination origin.
[25] Destination Y Origin Register-The destination Y origin (DYO) register contains the value for Y coordinate of the destination origin. This value can be a device or world coordinate depending onthe destination selected for the index mode.
[26] Fast Destination Delta X Register-The fast destination delta X (FOX) register contains the value for the X component of the fast destination vector. [27] Fast Destination Delta Y Register-The fast destination delta Y (FDY) register contains the value for the Y component of the fast destination vector.
[28] Slow Destination Delta X Register...,..The slow destination delta X (SOX) register contains the
value for the X component of the slow destination vector.
[29] Slow Destination Delta Y Register-The slow destination delta Y (SDY) register contains the value for the Y component of the slow destination vector. [21~] Fast Scale Register-The fast scale (FSC) register contains the fast vector scale factor for source land destination innormal and linear pattern mode. Bit 13 =0 selects upscaling and bit
13 = 1 selects downscaling. The binary point precedes bit 12.
[2B] Slow Scale Register-The slow scale (SSC) register contains the slow vector scale factor for source 1 and destination in normal and linear pattern mode. Bit 13 = 0 selects up scaling and bit 13 = 1 selects down scaling. The binary point precedes bit 12.
[2C] Source 2 X Origin Register-The source 2 X origin (S2XO) register contains the X coordinate of the source 2 origin that is added to the unindexed destination origin. The source 2 X oi:igin is specified as an offset from the destination. No indexing is provided and it can be used to generate
objects that are not ?n the display.
[20] Source 2 Y Origin Register-The source 2 Y origin (S2YO) register contains the X coordinate of the source 2 origin. The source 2 Y origin is specified a& an .offset from the destination. No indexing is provided and it can be used to generate objects that are not on the display.
[2E] Somce 2 Height and Width Register-:-The source 2 height and width (S2HW) register determines the size of the source 2 tile. The register bits are defined in Table 10.
2-58
Confidentfaland Proprietary
-
Preliminary
15:08 07
06:04 03 02:00
Destination address bit function_,..,Selects the destination address bits as follows: ·
Bit 7...0: High bits of destination axetmn~ before.adding tosow:ce 2 origin.
Bit 7 =1: All destination address bits are added ro sowice 2 origin.
Tile height (H)-Selects the tile height. H=O to 7 whi¢h is 2<H+2· from 4 to 512.
Reserved
.. ,
'
~ :·
' '
;
the Tile width (W}"'-'Sdects tilewidth~W·Otti 7·~is 21"1H) from4to512~lfhe tile
width must not be set to less· than the bus width. · ·
(2F] Error 1 Register-The error_ l _(ERRl) registrr contains the. error adjustment vector added during raster initialization for the slow destination (B side) fill mOde. . .
[2F] Error 2 Register-The error 2 (ERR2) register contains the error adjustment vector added
during raster initialization for the fast destination in normal and linear pattern mode and for the
source 1 (l3 side) infill mode.
Screen Format ControlRegisters The screen formafoontrol ~isters, shown i:n Figtite 8, Select the Vtj"t;cil and horizontal timing events, number of read cycles, bus width, and refresh rows.
15 14 13 12 11 10
00
[31-34J
~
J ~;~T~~::EVENJ
RESERVED----~
.TiMe OF EVENT
Y SCAN COUNT 0 TH ROUGH 3 REGISTERS
15 [35J
09 08 07 06 05
00
NOT USED
BUS WIDTH
MEMORY CONFIGURATION------_..
NUMBER OF READ CYCLES
X SCAN CONFIGURATION R.EGISTER
Figure 8 · 78690 Screen Format Control Register Format
Confidential .and Proprietary
2-59
-
Preliminary
15 [36]
14
: : 13 12 11
10
: : .09 08 Oi
: : 06 05 04
:03 02 . 01 :,
00
~--~~~~~--""-....;_~~~~--...---"-~~--~~~~~~~"-'---'
NOT USED
WIDTH LIMIT
X LIMIT REGISTER
15 14 13
00
NOT USED
HEIGHT LIMIT Y LIMIT REGISTER
I15
[38·3E]
14
13
11 10
00
~f~J~~~~~~~~
RESERVED PROGRAM BIT
EVENT
TIME OF EVENT
X SCAN COUNT 0 THROUGH 6 REGISTERS
15 14 [3F]
t
NOT USEO
PHASE ADJUSTMENT VALUE
05 04
00
NOT USED
SYNCHRONIZATION PHASE REGISTER
Figure 8 · 78690 Screen Format Control Register Formct (Continued)
2-60
Confidential and Proprietary
-
[31-J4lY Sea& Countfltegisten (0·3)-TheY scan count (YCTO throughYCT3) registers,are:used
to p~ the vematl el.!ents. Each register detetmines ,the rime for one·~cal event, sucl:na:s
vertical blank time, in order of increasing time. If the horizontal period is an odd·humber of rruijor cycles, the vertical period must be set for tn even number of scans in a frame. Table 11 describes the
function of the. register information.
Bit ~.
15:i4 . NiK used
13:12 WrtiCal event-SClects the vbncal's~~ lihd li1~1eveni(iis £¢ll0\l/s:
"i!;<,l
Bit Event
13
12
0
0
End vertical period. Set vertical bbutk low in the £9llmving scan.
0
1
Set vertical blank high.
···· ··
· ·.
1
0
Set vertical sync low.
1
1
Set vertical sync high.
,., .
Example:YCTO ~s vet1ica1 hhuik hi~ YC1;1 sets ~rtia.GJ'Sfll9higl:l, ¥CT2 sets vertical
sync law, and YCtl s¢ts verdeii.l~1ank lmv mresta?ts:· ~~~ ~ The video
oonttol~ffes's§s;teni·sYrn:iequestm tlieSeahprPffib·~~~vertica.lblank. The
Xscatlregis~~e~.~ti@tig.
',. · .,, ··
·
11 10:00
Reserved (must be zero)
·Time of ~t, ~~~ i¥1~6ft'h~·eveutfto~¥ d~ti~1fot~fcal''bWdc
{In scans), ··~·for'veiit~~P.i:Xl~ w1µ¢is'~et't~ (be ~¢ildf'stamitfa fnime nnnlis
or.le.·'·'··'':···· ·.. ·· ,·: '·"f. ... / ..,· ·····.:':·····.·
.····
Confidential.and Proprietsty
. .1!,__,_ _ _ _ ·~------·-1Ht_n_,_,_a..,.
,_,11m-=---..-,.
""'
""--·- - ·
2-61
-
£35] X Scan C:onfiguration Register....;.,'fhe X seen oonfiguration (X<COJ'.'.Il 'tegist~ detetmines the bus widths, the number Qfread cycles, and the memory configuration. The register inform:;\tion is
described in Tuble 12.
Bit 15:09 08 07 :06
05:00
Table 12 · 78690 X Scan Configumtion Register Description
Description ·.·.
Notused
Memory configuration:_Controls the number of row addresses refreshed on each s,can.
;,
-',
Bus width-'.fhis mode is programmed in the vid~ control and video processor before a
bitmap memory access is performed as follows:
Bits
1
6
Bus width
0
0
4-bit
0
1
8-bit
1
0
undefined
1
1
16-bit
Number. of :readcycles_,The numl:>er of major readcycles used for each scan. normally set to the smallest il;iteger ~j\ter than or.equal to the numbe~. of pixels to be Q.isplayed on each scan divided by 128, 64, or 32 inthe.16-, 8-, or 4 bit bus width mode, !'efipectively.
(36] XLimit.Register-The X limit (XL) register selects the w.idth of the memory that willbe read during the t'l!fi:esh proces.s. This value must be the number of read cycles µi the X scan configuration register multiplied by 128, 64, or 32 in 16-, 8-, or 4-bit bus width modes, respectively.
(37] Y Limit Register.;;_The Y limit (YL) register selects the height of memory that will be read during the refresh process. This value is set to the memory height plus the number of extra scans required during down scrolling.
[38-3E] X Scan Count Registers (0-6)-The X scan count (XCTO through XCT6) registers are used to program most of the horizontal timing events such as horizontal blank time. Each register determines the time of one horizontal event and the events are stored in the order of increasing time. The information in the register is defined in Table 13.
2-62
Confidential and Proprietiiry
-
Bit. 15 14 13:11
10:00
Tel* U · 78690 X Scan Count Rqisten (0-6) qesci'iptioos'
Reserved-Reserved for test. (normally zero)
Program bit-Set to one in the X scan count iegister~ theXsean C®11t~ that C:ontains the sync request event (bits tl:1J)1.!N.s·~~·~ ctCanii;I:Pi,~ re~J(
scan count registers;
Event~Sdeenthehorizontalpanuneters :afollows:
Bits
13
l2
11
Event
0
0
0
Set horizontal blank JoW,.·
0
0
1
Set horizontal bbiiik high.
0
1
0
Set horizontal sync low ....... .
0
1
1
Set horizontal$.~ · . '
1
0
0
Set horizontal sync lo\\t ?
1
0
1
Set horiZOririil syncKhigh:
1
1
0
End hociv.(lntal period,
1
1
1
Set sync request event.
Time of event-Sdects the time of event, in increments of 1/16 of a major cycle, from 31/4
major cycles that precede tlJ.ie start of the first~ry <:ycie1i:!fi·1a~''fliie'sbtft:Mi
memorycyd~ is at' the·nsing :edgeidf' th~tPm:2' ili~~.~uf~l:Ke{RiAs·~ ~t
begins the cycle.
' ' .<::. ·
· ·'
·· · · · ·· ·
[3FJ S~ Phase ~~The sync phase (~~~~~t# cilht:aini the sy~ p~ adjust~t
value. Th.is is the valµe ~t the~ controlloads into the horizontal sync counter at each system sync time(c;mce pct frame).
· Specifications
The mechanical, electrical, and environmental characteristics and spetjf~sa~iopi'fur the 78690
video. control are describedin thefollowing paragmphs..The test condition${0fthe ek!ctrical wlues
are as follows unless specified otherwise.
1
)i '
· Power supply voltage (V00): 5.0 V ±5%
· Temperature range {T"): 70°C
Mechanical Configuration
. .
.. . .
The physical dimensions of the 78690 84-pin cerquad paGkatieareeontained in A,Ppendix E.
-
Absolute Maximu~ ltatitlgs1 .··. 1 ·
· ··
Stresses greater thanthe~bsolute maximum ratings may cause permanent damage tothe device.
Exposure to the absolute maximum ratings for extended periods may adveri;ely affect the
reliability of the device.
· ];'ow~ supply voltage (Vno): -0.5 V to 6.0 V
· Input voltage applied (V..): .:..05 V to 6.0 V
· Output voltage applied (V...,): -0.5 V to 6.0 V
· Power dissipation (P0 ): 3.5 Wat 0°C
· Active temperature (T,.,): 0°C to 70°C
· Storage temperature: -55°C to 125°C
Recommended Operating Conditions
· Power supply voltage (V00): 5 V ± 5%
·Temperature (TJ: 0°C to 70°C
de Elec,,nc:iJ. Characteristics The de elei;:trical parameters of the 78690 video control for the operating voltage and temperature ranges specified are listed in Tuble 14.
Syntbol Vm Vn. Von
Vo1.
VoL CLKm CLKn. InD
Table 14 · 78690 de Input and Output Parameters
Parameter
Test Condition
Requiremenui ··
Min.
Max.
High-level
2.0
input voltage
Low-level
0.8
input voltage
High-level output
lou=0.2 mA
2.7
voltage
Vnn=OV
Low~level output
loL=-5 mA
0.5
voltage DAT< 15:00 > Vnn=OV
Low-level output
loL==-5 mA
0.4
voltage all ot~er outputs
Clock input high
2.7
level
Clock input low
0.4
level
Active supply
Vnn=max
0.66
current
Units··
v v
v
v v v v
mA
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Confidential and Proprietary
-·
Symbol ~
liH
Input high leakage
current
In.
Input lmv leakage
current
IZH
Hi-impedance
input high leak.age
current
Izi.
Hi-impedance
input low leakage
current
c.
Input cai)acitance
Cm
Input/output
capacitance
Preliminary
Test Condition
Voo=max Vu.= V00(max) Vnn=max V.,=OV Vno=max
V"' =V00(~ax)
VDD=max V"'=OV
Requirements
~m.
Max.
20
-20
20
... .:.20
~
10
._;;.,.
10
'78&90 Units
µA µA µA
µA
pF pF
ac Elect:rical Chatacteiristics The ac ti.ming parameters for tbe,78620.video .cutttrol ate;gt'Puped according to clock input, processor interface, instruction/data bus, me:tnory interface, and monitor timing and synchronization request. 'Thble 15 lists the ac input specifications.
'Dlble 1' · 78690 ac Test Limits and Specifications Symbol. Definitio~
c.. Input capacitance c.. Input/outpµ.t capacitance
Inputs~ rise t;ime
Input signal fall time
10 pF
10 pF
'1()
ns
10
OS
The following conditions apply to the ac test conditions ubles~ 9therwise stated.
· The delay times extend from the 1.5 V level of the do& input to the Vcm or Voc level of the
measured signal.
from · The rise times are measured the 10% to 90% level 9f ~htl signal,ttansitions. Fall times are
measured from the 90% to 10% of the signal transitions.
· The measurements are with a 50 pF capacitive load on the outputs. Exceptions to this are outputs ID< 7:0 > that have a 500 pF load, and DAT< 15:00 > that have a varying load up to 500 pF.
2-65
-
Clock ~t Tuning . . ....
. . ..
. . .. .. .. .
The ac fuput parameters for the phase fuput clock signals PHil through PHI4 and the CAS signal
are shown in Figure 9. The parameters are deffued in Table 16.
---------tc12PR-----------tc12Pw --IM
PHI 1
__. .___lc12_NO_____.!:,=p= ·. tC12PW
PHl2
_h_r-
PHl4
Httec ePW CPR~
CAS
. tc:
-----------
Figure 9 · 78690 Clock Input Timing
Table 16 · 78690 Clock Input Taming Parameters
Symbol Definition
tc1:1PR
tomi
Period of PHil ··~ PHI2
Period of PHI3 and PHI4
Requirements (ns)
Min. Max.
228
684
114
342
tCCPR Period of CAS
85.5 257
tc12PW Pulse width of PHil and PHI2
85.5
tcJ4PW Pulse width of PHI3 and PHl4
28.5
~ Pulse width of CAS
28.5
tea* Rise time of PHU, PHI2, PHI3, PHI4, CAS
5.0
ta* Fall time. of PHU, PHI2, PHI3, PHI4, CAS
5.0
;temro Nonoverlap time of PHil and PHI2 .
23.5
tcJ4NO Nonoverlap time of PHI3, PHI4
23.5
teen Low time between CAS pulses
57
*Rise time is measured from 0.4 V to 2. 7 V; fall time, from 2.7 V to 0.4 V.
2-66
Confidential and Proprietary
r .· &Th0ecepsrscoicre1sns. o~jn. ter·f·a·t.e·t·im~ ing is .shown in Figure 10 and the parameters listed on the figure· are
d~ined in 'table 17.
_A0(05:00) RO
DATA (WRITE) DATA (READ)
Symbol Definition
tASAs
tASHLD tASos
The time that· the AS input must ~~be ·asserted
before being reasserted.
·
Setup time for valid input data on the
ADD< 5:0 > inputs relative to the falling edge of
the AS input.
Pulse width of the AS input if the OS input is not
asserted.
Hold time for valid input data on the ADD< 5:0 >
after the falling edge of the AS input.
The time from assertion of the DS input to deasser-
tion of the AS input.
···~tJ'fils.)'\"
..'~ Reamd. :Y·t.k.e..
~imnuun Itead· 'Write
to5 105
0
0
180 180
40
40
140 75
Confidential and Proptiemry
2-67
Symbol Oeanition
Requirements (ns)"' ·
Minimum
Maximum
Read Write Read Write
tDSSU Setup time for valid data on the DAT< 15:00>
inputs relative to the falling edge of the DS input
during bus write operations.
0
tnspw Pulse width of the DS input.
140
95
t!U>DS The time for valid input on the RD input before
the assertion of the DS input.
30
30
tnsm Hold time for the RD input after the falling edge of
the DS input until the deassertion of the DS input. · 40
40
tnm.n Hold time for valid data on the DAT< 15:00> inputs after the falling edge of DS input during bus
write operations.
40
tDVON Delay time for valid data on the DAT< 15:00 >
outputs relative to the falling edge of the DS input
during bus read operations with a 50-pF capacitive
load on the outputs.
140
tnvoNAt Delay time for valid data on the DAT< 15:00>
outputs relative to the falling edge of the DS input
during bus read operations with a 500-pF capaci-
tive load on the outputs.
410
tnvoF Hold time with previous data valid on the
DAT< 15:00 > outputs after the rising edge of DS
during bus read operations
0
50
tINAS The time from deassertion of the INIT input to the
assertion of the AS input.
100 100
tlNP'lll:t: Pulse width of the INIT input.
12xt 12Xt
tADOP The time from assertion of the AS input to deasser-
tion of the DS input.
180 135
tASDV Delay time for valid data on the DAT<15:00>
outputs relative to the falling edge of the AS during
bus read operations.
180
*Timing is measured at the VoH and VoL levels
ttDvoNA = tnvoN + 60 ns per 100-pF capacitance additional loading. (Intermediate values may be
calculated.)
:t:This para~r is 12 x t where t = PHil or PHI2 clock period.
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Confidential and Proprietary
-
Instruction/Data Bus Timing Flgurell sllb\Vs tneinsltttctldri/databus signal timing andthe timingpaf9meterserelistedii'lTable18.·
PHl2
INSTRUCTION
LOW BVTI: l)ATA
INSTRUCTION
I0(()7:()0) TRANSMIT
10<07:00) RECEIVE
DON'T CARE
IDBUS ~-;----~-~~~~~-+----.;..,---;..~-~~~ CYCLES - - - - - - - - - - - - . . . , . . . . . . . . , . _ ._ _ _ _.....__ _ _ __
IOCTL
Figure 11 · 78690 Instruction/Data Bus Sigt14l Timing
Symbol Delinitioo l.
~t.t(os)
Min. Max.
Maximumdelay~e fm:~9U~t?~~.~~~<·¥f~?~~s
relative to the rising edge of the PHU A and PHI2A input. .
60
Delay time from the falllng edge of the PHllA and PHUA input to
thehigh-~IUl~ levd Qt!Jqe IQ.~]:Q.> lin~s.
5.0 25
Minimum ~~~~·~~~ijt~~t¥tr~~·l~~·7~~,.r~~·
relat~to the falling edge of the PHU Band PHI2 Binput.
."20 ..:
tow Minim'.Gm.hold ·time fo~.~4 !µput ,c:la!!!.Qn. ·th~ID5.?:0?. Jines after the falling::~of.PPlllB:and,.~Ji:t·t, :+.; ~/ ·
With previ~ otifPUi'de.bi .Jiilld;·~~fs the ni~urii held iin:ie
on the IDCTL outi;>ut.~tjve to tl;te rising e4ge of the PH11 B ·
signal. (PHU'B is~ but time is(tefere0ced;to>~ Pffll signil.,.J .. .o:
Maximum delay tim.e for ~ da~ (iti ~ I.~1'L~!rit1t:'remt1Vf! ·
to the PHU B signabgoing·high; (PHU B i11 u$Cd ~t .tim.e ,i$-
re£erenced to the PH11 signal.)
75
*ta is meuured from.the deasl!Crted level of the 1.5-V clock inplit to the high:im~e level of
the ID bus.
2-69
-
Memory Interface Timing
.. . .·· .. . .· · . ,
Figure 12 i>hows the memory ;interface sign11ltiming anqthe t4xting paraJ,lleters are listed in Table 19-.
CAS
m:(03:00) SCROL
MAD<10:00)
, . tcAD14"-
I 1 I tcAH i...,. I
·¥At10
VALID
CASTIMING ¥A!.ID.
MEMORY CYCLES
PHI 2
128 FORCE
MAD
PHI 1 ADS
MAJOR CYCLE MINOR CYCLE
PHI inMING
MAJOR CYCLE
MINOR CYCLE
MINOR CYCLE
PHI 1 TIMING
B
A
B
A
Figure 12 · 78690 Memory Interface Signal Timing
~ 19 · 78690 Memory In~e liming Pimuneters
~.L '"· -
'
,
,
'
,
:
- - , }, ,·) ,'
·
'
,
·..· , ·,
Symbol Definition
Requirements (ns) Min. Max.
tCAH The delay time that the previous outpufof the MAD< 10:00 >, ··
WE<3:0>, and SCROL signals is valid after ihe rising edge of
the CAS input.
·
. 8.o
The delay timeforvalidoutputirof theMAD<lO:OO>, WE, and
. SCROL signals after the rising ~e qf t4e CA,S input.
55
The dday time that the previous.outp\lt tif the 128/16 ai:id FORGE
signals is valid after the rising edge of PHI2 A input.
5.0.
2-70
Confidentialand Proprietary
55
___ The time that the previous out~tm tbeMlUl ·i'.~·~jf~
the
rising
edge-Of~
··..
PNI~
.··· '
A..., .i.n.p.u.t.~....
······.
. .....,......,.··.......,,...,._..,.....,.......__..................
The delay tiinefp~yalid ~,tf tile~.~~·~~~~~.·.
edge Qf the PHI2 A input.
55
1ww Minim~ ti'1Cfoi.~"1-iilP\lt ~l,~lQS:~~~~ iq.·;
the falling edge ~~HU :JJ ·; ~ . , ,
· ,, · f;;';,31 >i · ;r .,. . . 27
Monitor Timing and Syncluoniution . . . .~ '.'f :,
Dtitjns the ·s~Miationintmat,·the'PHI 1; m12~rl'l'~'~ level,"andtheCASfaputis~tt.u1hlghleveL · . ti': ·.:. > ·....· ... ·m~~tiondook timing and the pararn~"arc·ti:!!*11in11aBW &.1'he 'SiW~iibjutrpa~rs.~ :vaiid for .t4e
SYNC request from thevi~ro~ orlfrijm~110wie:.o~lli:kfcks:¢.ofl.tinue~the SYNC in~.
... ~ PHI 1
~
PHI 2 ~..,.__....·~
~· PHI 3 'L.fLJLJl_Jl_
~.su····5·~ PHI 4
tsYR
tsYF
SYNC
tsYPW
Figure 13 · 78690 Monitor and Synchronization Request Sifflal Timing
2-71
-
i'.JAWe ft· 78690 Monitor and Synchronimtion Request Timing Paramet.ets
Symbol Defiriidon
Requirements (ns) Min. Max·.
tnm The delay time for valid output of the VSYNC orSYNCRsignal
relative to the rising edge of the'PHll or PHU! inf)Ut.
..,..
90
tVHH The delay time that the previous output ofthe VSYNC or SYNCR
signals is valid'felative to the rising edge of the PHU or PHI2
inputs.
0 ·
to.PD The delay time for valid outt>ut ofthe CMPSYN or BLANK signals
relative to the rising edge of the PHI3 or PHI4 input. ··
-'
45
tc-H The delay time that the previous output of the CMPSYN ot
BLANK signals is valid relative to the rising edge of PHI3 or PHI4
inputs.
5.0 ·
l:svsu
l:s'111"&1 * t8m*
Minimum delay from the assertion of the SYNC signal to the PHI2 input going high. This delay starts the clock freeze period that is a restriction of the external clock generation control.
the pulse'widtll of the SY't)l'C signal.
The delay time from the deassertion of SYNCto the ei:id of the clock freeze.time. This delay is·a restrict.km of the external clock
generation control.
. 0 ' 800
400
. 24 µs .24 µs
tsVB Input rise time of the SYNC pulse.
50
tsvP Input fall th,ne op the SYNC pulse. ·
50
*tsv.. + tsVPZ must be equal to (or be a multiple of) 16 periods of the PHI1 or PHI2 inputs.
2-72
Confidential and·Proprietary
..
~~~.Sipa!Tuning.
· ·
The ~,$UM fot:,dte; 4iterrupt and ~uest are listed and defined in Tu.hie 21.
Symbol Definition
The assertion _propagation delay for the INT or REQ signal in
response to a status bit being set when the correspondiqg bit of the
ru Interrupt or Request Enable register has been set :previously.
Delay tA is measured from the edge of the or system clock signal
that sets the status bit.
0
140
The deassertion ptop3gation delay for the INT or imQ signal in
response to a status bit being cleared when the corresponding bit
of the Interrupt or Request Enable register has been set'previously.
Delay t 0 is measured from the edge of the DS signal that clears the
status bit.
0
.140
The assertion propagation delay for the 00 or REQ signal in
response to setting a bit of the Interrupt or Request Enable
register when the corresponding status bit has been set previously.
Delay t.w is measured from the edge of the D'S signal that sets the
Interrupt or Request Enable register bit.
0
180
The deassertion propagation delay for the INT or REQ signal in
response to clearing a hit of the Interrupt or Request Enable
register when the corresponding status bit has been set_previously.
Delay tDJ4 is measured from the edge of the DS signal that initiates
the resetting of the Interrupt or Request register bit.
0
180
· Interfacing Tedmiques
Up to twenty-four 78680 video processors may be used with each video con.trol. The video control includes a system interface, a hit-map memory interface, and a display interface as shown in Figure 3. Refer to the Dragon Video System Hardware Specification for l:l· romplete description of a video system using the 78680 video processor and 78690 video control.
The system interface connects the video control to· the local p~ssor or DMA controller through the processor interface. The processor interface transfers 16 data bits, 6 address bits and 6 control bits and receives the parameters and commands from the local processor. The interface handles register accesses and controls timing and all necessary bus signals.to allow the video control to act as a bus slave to the local processor or DMA device. The system interface also connects the video control to the instruction/data bus through the ID interface.
The ID interface transfers information on the 8-hit bidirectional instruction/data bus and the chip select control line. The instruction/data (ID) bus is used to transfer information within the video processor and to controls its operation. It is used to load and read registers and to execute direct or indirect instructions.
2·73
The bit-map memory interface includes the bit-map memory address btl.Sand tHe'signals that
control it. It transfers address information on 11 lines, write enable iri.forniatiorion 4 lines, and control information on 5 lines.
The display interface connects to the monochrome or color monitor interface for video and riming. The interface signals include the four synchronization and blanking signals.
The video control requires a 5-Vde power supply.
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Confidential and Proprietary
·Features
· Programmable for videOOisj:days using a.maxitlrum of 4096 by.4096 phrel.Jocatioos;
· Compatible with Digital's DC322 video processor and DC323 videocontrol
rursor '·· ·.'·· series ·
Interfaces with the MicroVAX
78032 microprocessor and Motorola 68000 -' - "
-' ' - ' -
... ~ro~essors
" '., ·;·
-~ ; \
'
, ·- ·,
· Selectable cursor characters and single- or double-w,idth hairline
<
·· .. "· .·
· Description
The DC503 programmable cursor chip {PCC) is contained in a 44:-pin c:erquad package and is used to provide a programmable cursor for use with videodisplay terminals. Figure 1 is a simplified block diagram of the DC503.
8U$ INTERFACE LOGIC
SYNC 81.ANK NllCLK
~· i-----~~-'"-~~~~~~~~~_,.,..-!>-l"'-~~~~~~-~ro1 AN> REGION REGISTERS
Figure 1 · DC503 Simplified Block Didgram
Confidential and Proprietary
2-75
The DC.503 e11ables cursor charac.ter~ or icons to be prognimtned and poSitioned to the desired
location of a videodisplay. The DC503 contains two 16 by 16 memory arrays to store the cursor sprite. This enables the cursor to sdect up to three colors and display normal video in its transparent region. In addition, the DC503 can be programmed to display either a single· ot: a double-width fullscreen hairline cursor. Two programmable boundary i;egions on the display can be detected and the cursor can be clipped in either of the two regions on the screen.
· Pin and Signal Description
The input and output signals and power and ground connections are shown in Figure 2 and
summarized in Table 1.
· ·
· ·
~ ~ ~ ~ ~ ~ ~"' ~ ~ ~ ~
VDO DAT15 DAT14 DAT13 DAT12 DAT11 IJl'IT10
voo
GNO
DAT09 DAT08
. 39 3g 37 36 35 34 33 32 3130 29
40
28
27
26
PIN 1 IDENTIFIER
25
24
DC503
23
22
21
20
19
18 7 8 9 10 11 12 13 14 15 16 17
! § ~ ~ ~ 1~ ~ ~ 1~ 1~ ~ z
GND OAT07 OAT06 .DATD5 OAT04 OAT03 DAT02 VDD GND OAT1 DATO
TOPVIEW
Figure 2 · DC503 Pin Assignments
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Confidential and Proprietary
Table 1 · DC,03 Pin and Signal Summary
Pio
41-44
1~2,5,6,
27-22
19,18
DAT<l5:00> inputs
Dsoartbaulsi.nes<:· 15:00>-Da·ta· inp· u· ts &om the proce·s-
10-7 . AD< 3:0 > inputs
11
AS
input
14
DS
input
.·~·lines ·<.3:1);>...,...Address·inputs from. the p~bus;..·· ,,.
Address· strobe...2::St~b~s the address··.· inputs AD<:3:0> ··mwthebtisintt:rface.
·,-
~
Dl¢llstn)~S~.the ga~ inpµtsDA'.1'<15:00>
into i;kel;>us ~~·
15
. ~
input
Write enable.;_.Whett<asserted,· a write operation is
perfi:>rm.ecl·totheOOS03.
17
SYNC
input
16 .
. 13
BLANK
NIBCLK
input . iiipti.i:
Nibble C:IBdc-'3'fhe t1fiiihg sigllal ~to sYfldm:>ni?.e .
the output to the di~/
39-36 PIA<3:0> outputs
Plane information A <3:0>-Four-bits of the 16bit data word for cursor plane A.
29-32 PIB<3:0> outputs
35
PARDI
output
33
PARD2
output
34
TEST
3,21, VDD
40
output input.
P.lmeinformation B< 3:0 >-Four-bits of the 16-bit
'd!lta'~.ftiiciit~t~ B.
~ble. ~ctive regi9n 1 detect-Jndicares that aCtive region1Of the dispt\1has been d~..
· Pl!>graminable ~vere.gion.2 detect...:-Iili:licates ~t
·llefii-vc region 2 ofthe display has been detected.
~-UsCd for test ~cnly. 1Vo1t4e-Power Supply voltage
4,12, GND 20,28
input
Gtound~Ground reference.
Confidential and Proprietary
2-77
·Ptelifuinary
· Functional Description
The data (DAT< 15:00 >) and address (AD~l;O >).information frqni the bus is loaded into the bus interface by the data strobe ('BS) and address strobe (AS) input· respectively. The data determines the cursor font and specifies the coordinates for the cursor location. Address
AD < 3:0 > selects the register that will receive the data. The write signal (WRT) loads the
information into the command, position, and region registers. The data is transferred to the memory plane A or B under control .of the timing and control and memory decode logic. Information from each memory plane is transferred ta barrel shifter A and B, under control of the barrel shifter logic, to the output multiplexers. Each multiplexer output provides 4-bits of information (PIA<3:0> and PIB<3:0>) ewry 37.8 ns for the 16-bit by 16-bit cursor font. Timing and control is provided by the sync detector logic that receives the SYNC and BLANK signals from the controlling device and the NIBCLK clock pulses.· Information from the sync detector is transferred to the registers that detect one of the two active regions on the display. The regions are indicated by the PARDHmd PARD2 outputs. The. te$t logjc receives PARD1 and PARD2 signals and the output from each multiplexer. The TEST· output is used to self-test the cursor memories and active region detectors.
Register. Selections
They· Address bits AD<3:0> select: a command, position, or active region register to·be loaded.
also select the cursor memory by an indirect me~ry address to an internal address oo-qnter. Table 2 lists the address codes and register selections.
18ble 2 · DC.503 Address~~ Select Functions
Address Line
AD3
AD2
AD1
ADO
~ster·
0
0
0
0
Load command register (CMDR)
0
0
0
1
LOadX position register (XPOS)
0
0
1
0
Load Y position register (YPOS)
0
0
1
1
LoadXminl active region register
0
1
0
0
Load Xmaxl active region register
0
1
0
1
LciadYminl active region register
0
1
1
0
Load Ymaxl active region register
1
0
1
1
Load Xmin2 active region register
1
1
0
0
Load Xmax2 active region register
1
1
0
1
Load Ymin2 active region register
1
1
1
0
Load Ymax2 active region register
1
1
1
1
Cursor memory (indirect memory address via an
internal address counter)
*All registers are write only.
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Confidential and Proprietary
-
Comouuid Register DesCr:iption The command register (CMD) is a write-only register and is used for communication between the CPU and the programmable curs0r chip. Thecommand registerformat isshown in Figure3 md<the
functions are listed in Table 3.
15
00
COMMAND REGISTER
':1
l'
I :
I.·
i'· c I ,
CM015-CMDO
Figure 3 · DC503 Command Register Format
Bit
CMDO~CMDl
CMD2~CMD3
CMD4* CMD5* CMD6* CMD7*
Description
Enable/force cursor plane Aoutput as follows:
CMDO CMD 1 State
0
0
logkO
)..;
0
.o 1
etlllble logicl
1
1
logic 1
Enable/force cursor plane B output as follows:
CMD2 CMD3 State
0
0
logic 0
;.[,
1 O enable
O
1
logicl .
1
1
logic 1
··Command 4ll..Hairlirte)Cu.rsor enable·
1 =enable, O=disable
Command 5-Clip .cursor inside ~Yf! regi?n
1=clip cursor, d=don't clip cursor
.·
Command6-c-Clip hairUne cursodnside active regi<ml ot 2
1 =active region..l, 0 ==active region 2
Command 7-Double width hairline cursor
1 ;,., double width, ()"=single width
Confidential'and Proprietary
2-79
-
Bit
Description
CMD8:CMD9
El"Utble/force active region 1detector as follows:
CMD8 CMD9 State
0
0
logic 0
1
0
enable
0
1
logic 1
1
1·
logicl
CMDlO:CMDll
Enable/force active region 2 detector as follows:
CMDlO CMDll State
0
0
logic 0
1
0
enable
0
1
logicl
1
1
logic 1
CMD12
Command 12-Load cursor memories 1=enable load, 0 =inhibit load
CMD13 CMD14
Command 13 -Select Hi/Low active BLANK (vertical) 1 =active high blank, 0 =active low blank
Command 14-Select Hi/Low active SYNC (scan)
l= active high sync, 0 =active low sync
CMD15
Command 15-Reset signal TEST=O 1=Clear TEST to "O'', O=Enable the test hardware
*These bits are double buffered during vertical blanks and any new value loaded is not acted upon until the next frame. CMDO and/or CMD2 must be enabled for the hairline cursor to appear.
· Architectural Description
The DC503 operates with a videodisplay using 4K by 4K locations and having a maximum scan rate of 9.45 ns/pixel. It provides a single- or double-width hairline cursor in two independent
programmable active regions. Clipping of the cursor in scan occurs in either active region 1 or active region 2. The cursor resolution is to a pixel pCYSition. The active region resolution is to a nibble (4-bit) position in the X direction and to a pixel position in the Y direction. Memory plane A
and/or plane B output information can be selected and the planes can be forced to either 1 or 0.
The blank areas and synchronization are controlled by the programmable active Hi/Low Blank and SYNC inputs. The origin of the display screen is the upper-left corner of the screen and the display is not interlaced.
Data from the DC503 is provided as two 4-bit nibbles every 37.8 ns assuming 9.45 ns/pixel. The CPU data path to load the information is 16 bits wide, The input clock period (NIBCLK) is aligned with a nibble output. Therefore, it is four times the pixel rate. The initial display of the cursor is not important while CRT is blanking. The SYNC input accepts either horizontal or composite
monitor sync information. The BLANK input signal must be active for a minimum of two sync
. intervals and must include Gr coincide with SYNC signal. The SYNC input must be active for two
NIBCLK dock periods. Registers must not be loaded between the assertion of vertical blank input until three horizontal sync pulses occur. During the powerup initialize time, the CPU must allow the DC503 to become self-initialized by two video frames and with the NIBCLK dock operating
continuously.
2-80
Confidential and Proprietary
..·,
The OC503 provides two similar logic paths for controlling the X and Y of the videodisplay axes. Each path consists ofa set of registers, a random access memory (RAM}, and multiplexing logic. Most of the registers are double buffered to allow a full frame time for loading. Both the X and Y paths are pipelined and the information in each paths must be complete before the entire content is valid.
Figure 4 shows the coordinates for the t\1..'0 programmable active regions and the cursor position. These 18 coordinates are pivgrammed by the user and stored in registers. After the coo.rdinates and cursor position have been loaded, they become the holding registers.for a· comparison with the internal X and Y counters that are used to determine the pixel reference.
BLAHK
(0,0>
.------..,..----.*
xmin1'
xmax1· -t
ymin1'
ymt n1'
ACTIVE REGION 1
xmin2'
x....ax2' -1
B
xminl'
ymln2x'm..a.xr1'----1 ----...,......-·--ymln2'
B
L A H
,_Y_m_ax_t_'_-,_ _ ___,ymax 1 , - 1
'I I xpos' ·. ·
ypos cursor
L A H
K
K
ACTIVE REGIOH 2
xmln2'
xmax2' -1
y111ax2' - 1 - - - - - - - - - - y n 1 a x 2 ' -1
BL AHK
Figure 4 · DC503 Programmable Active Region Display
*The maximum values of the active regions 1 and 2 define the limit that is reached by the region. As an example, the upper right location of region 1 includes Xmax-1 and Ymin (not Xmax and
Ymin).
Y (pos max or min 1 and 2)' =Y (pos max or min 1_and 2) :t the number of SYNC siggals per
BLANK signals after the first assertion of BLANK and SYNC signal~.
X (pos max or min 1 and 2)' =X (pos max or min 1 and 2) +6 NIBCLKH signals after the last
assertion of the SYNC signal.
**Location where BLANK and SYNC are first asserted
Confidential and Proprietary
2-81
· --------------.,,_...-~-~-. -------·--·---------···--·----·-··----
Preliminary
DC.503
Because the counters may not wrap around to a known position, the content of the internal X counter will be cleared at the end of each scan line and the content of the Y counter will be cleared at vertical blank time.
The X counter is incremented every NIBCLK dock pulse and is synchronized with the video stream data. The Y counter is incremented every scan line at the scan sync time.
The X and Y coordinates may change during a frame. However, the new coordinates will not become active until the present frame has been completed. This prevents part of the cursor from being displayed at one position on the screen and the remaining part displayed at the newly assigned position. The active regions may also be changed during a frame. However, the values are stored in registers until the next frame occurs.
The memory planes A and B contain the binary values of the cursor font. The memories are identical and each contains sixteen 16-bit locations. Figure 5 shows the organization of the cursor memories A and B.
15
0
WORDO WORD 1 WORD2
·
15
0
WORD 16 WORD 17 WORD 18
WORD 13 WORD 14 WORD 15
CURSOR MEMORY A
·
WORD29 WORD30 WORD 31
CURSOR MEMORY B
Figure 5 · DC503 Cursor Memory Organization
The cursor memory locations are addressed by an internal address counter, and data is loaded into the selected location. The counter is autoincremented by each data load operation provided that command bit (CMD12) is asserted and the register address code (Table 2) selects the cursor memory. When CMD12 is deasserted, the internal address counter is cleared. The load sequence may be interrupted to load other registers provided that the internal address counter is not cleared by the negation of the CMD12 bit. The CMD12 bit must be deasserted after the information has been entered into cursor memories.
The 16-bit words are read from the memory once for each scan line and shifted by the barrel shifter to enable the exact pixel alignment. The words are shifted by pixel amounts (0-3) and multiplexed into five consecutive 4-bit nibbles. The shift constant is determined by the two least significant bits of the Xpos address, since the offset can be up to three pixels. A nibble is generated for each NIBCLK clock pulse that results in an offset value and a multiplexing of five groups of four nibbles.
Output PIA < 3:0 > is a nibble of cursor memory plane A, and PIB < 0: 3 > is a nibble of cursor
memory plane B.
The TEST output is used to selftest the cursor memories and active-region detectors. Writing a 0 to bit 15 of the Command register enables the test hardware. The assertion of any PIA<3:0>,
PIB < .3:0 >, or PARD < 2;1 > output will assert the TEST output. The TEST output is disabled by
writing a 1 to bit 15 of the Command register. During normal operation, the timing of the TEST output is unspecified unless bit 15 is cleared.
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Confidential and Proprietary
-
Preliminary
· Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DC503 are
described in the following paragraphs. The test conditions for the electrical values are as follows unless specified otherwise.
· Power supply voltage (VDD): 5.0 V ± 5%
· Temperature range (TA): 0°C to 70°C
Mechanical Configuration The physical dimensions of the DC503 44-pin cerquad package are contained in Appendix·E.
Absolute ~um Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may adversely affect the
reliability of the device.
· Power supply voltage (V00): -0.5 V to 5.5 V
· Pin voltage: -0.3 V to VDD+0.3 V
· Power dissipation (T1= 0°C): 0.3 W · Operating temperature (TA): 0°C to 70°C
· Storage temperature: -55°C to 125°C
· Power supply voltage (VDD): 5 V ± 5%
· Temperature (TA) 0°C to 70°C
de Electrical Cha:rac1eristics The de. electrical parameters of the DC503 for the operating voltage and temperature ranges specified are listed in Table 4.
Confidential andProprictary
2-83
-
Parameter
High-level input voltage Low-level input voltage High-level clock input voltage Low-level clock input voltage Input high leakage current Input low leakage current
High-level output voltage
Low-level output voltage
Preliminary
Table 4 · DC.503 de Input and Output Parameters
Symbol Test Condition
Requhements
Min.
Max.
Vm
2.0
Va
0.8
Vm
2.7
6.0
DC503
Units
v v v
Vu.
0
0.4 v
Im
V1.= VDD=5.25 v
20
µA
I1L
V.,=OV
Von=5.25 V
Vou
loH=0.2mA
VoL
IoL=-5.QmA
-20
µA
2.7
v
0.4 v
ac Electrical Clwacteristics The signal timing parameters for the NIBCLK clock input are shown in Figure 6 and defined in Table 5. The waveforms and propagation delays symbols for the input and output signals are shown in Figures 7 through 10. The parameters for the symbols on the figures are defined in Table 6. The specifications and conditions for the ac tests as as follows.
· Input capacitance: 10 pF
· Input signal rise and fall time: 10 ns
· All delay times extend from the l.5V level of the clock input to the Vou or V0L levels of the measured signal.
· The rise times are measured from 10% to 90% and fall times are from 90% to 10% of signal transition.
· All timing parameters assume a 100 pF capacitive load on the output.
2-84
Confidential and Proprietary
-
NIBCLK
----t-----
Figure 6 · DC503 Clock Input Parameters
Symbol
tRA
tpA
tPRD tl"ll'
Table .5 · DC.503 Clock Signal Tuning Parameters
Requirements (ns)
Min. Max.
Rising-~¢ time
5.0
Falling-edge time
5.0
Clock period
400
37.8
Pulse width 50% duty cycle ± 5ns
~ NIBCLK . I .·.·· .
- w _ I
PIA<3:0> PIB<3:0> PARD1
PARD2
I
I
I
I I
- t : r PIA<3:0>
PIB<3:0> PARD1 PARD2
NIBCLK
SYNC BLANK
I
VALID
I I
tsas __..,..._ tsBH
Figure 7· DC503 Clock to l1tput/Output Timing Delays
Confidential and Proprietary
2-85
· - - - - · - -..-··-·----------·------------~
OS
\-1.sv.
I I I
DAT<15:00>
I VALID DATA I
-+jI·-to-s----rJI'----to-H1Ii--
LOAD DATA
DC:5' 03
AS AD<3:0>
I VALID ADDRESS
I
I
I
I
IAS --I- IAH !--
I
I
I
I
f4---lASAS~
LOAD ADDRESS
Figure 8 · DC503 Load Da.ta/Address Strobe Timing Delays
AS
I
~
I I
lQVLP
OS
Figure 9 · DC503 Write and Data/Address Strobe Timing Delay
2-86
Confidetitial and Proprietary
NIBCLK
:-Tsroo--j ,____..,___
I
TEST --+I--"'
I
l .. t-T~TOl, I
I
\ : : ---~~-~---.· I I
Figure 10 · DC503 TEST Output Timing Delay
Symbol Definition
Requttements (ns)
Min.
Max.
tPOOL
Propagation delay output 1ow·. ·
26
troon
Propagation delay output hi~
26
tsas *
SYNC/BLANK setup time
10
tSBH *
SYNC/BLANK hold time
10
tDS
Data setup time
0
tDH
Data hold time
40
tAS
Address setup time
0
tAH
Address hold time
40
tASAS
Address strobe precharge time
105
toVLP
Overlap time
100
tsTOH
Propagation delay to TEST output high
40
tsTOL
Propagation delay to TEST output low
100
*The SYNC input signal must be active for a minimum of two NICBLK periods. The BLANK input signal must be active for a minimum of two SYNC signal intervals and must encompass or coincide with the SYNC signal.
· Interfacing Techniques
The DC503 programmable cursor chip can be interfaced to the DC323 adder and can operate with a full-page, half-page, and quarter-page display system. Figure 11 shows the full-page display interface configuration and associated signal timing. The DC323 generates the BLANK and
CMPSYN signals to drive the BLANK and SYNC inputs of the DC503. The BLANK and CMPSYN signals can be latched into the flip-flops by the PHI3 or PHI4 phase clock of the DC323 and may rise on one PHI3/4 clock and fall on the other. The latched BLANK and SYNC signals are received by the DC503 on the falling edge of NIBCLK pulse. Latches are 3'74 or the equivalent.
BLANK
ADDER DC323
CMPSYN PHl3 PH14
Preliminary
BLANK D
DC503 CK
SYNC
CK
DCSO:J
NIBCLKH PHl3
PH14
Figure 11 · DC503 Full-page Display Interface and Timing
Confidential and Proprietary
--
DC503
Figure 12 shows the half- and quarter-page interface configuration and signal timing. The BLANK and CMPSYN signals from the DC.323 are used directly as inputs to the DC50.3.
BLANK
ADDER DC323
CMPSYN
XBLANK
XSYNC
DC503
_J NIBCLK
___I
PHl3
PHl4 ___n...___n......______n___
FiguJ'e 12 · DC503 Half- and Quarter-page Display Interface and Timing
Confidential and Proprietary
2-89
· Section 3-Communication Devices
The asynchronous communication devices enable serial-line information transfers between local
remote systems and terminals. 78808 Eight-channel Asynchronous Receiver/Transmitter-The octal ART is a 68-pin cerquad device that is programmable and allows the simultaneous transmission and reception of eight serial-line channels. DCJ19 DLll Compatible Asynchronous Receiverffransmitter-The DLART is a 40-pin DIP device
that allows data communication between Digital's microprocessors and console terminals or communication devices.
Confidential and Proprietary
·Features
· Eight independent full dµplex serial data lines
· Programmable baud rates individually selectable for each line's transmitter/receiver (50 to 19,200
baud)
reoofo · Summary registers that allow asingle
detect·~ data 5et Ch1111ge or to determine the cause of
an interrupt on any line · ·
. ..
· Triple buffers for ~&,.receiver · Device saumer m~m that reports interrupt request due transmitter/~vet interfUpts · Independently p~ble lines for interrupt-driven operation · Modem stitus chaµge detection for Data Set ~y(DSR) andData Carrier Detect (OCD) signals · Programmable int~pts for modem status changes ~ Synchroiaizes critical read-only ~gisters
· Description
The 78808 Eight-Channel Asynchronous Req:iver/l'ransmitter (Octal ART) is .·a VLSI device for new generations of'asynchronou8 serial communication designs and for micro4omputer·systems.
This 68-pin devict: rperforms the basic operations necessary .for simultanedus reception and transmission ofasynduonous messages on eight independent lin~s. Figure 1 is a functional block
diagram ofthe 788()80ctal ART. ·
1·00
Rx DO DSRO DCOO Tx-01 R.11:01 DSR1 OC01 Tx02 R.ic02 DSR2 DCD2 Tx03 A>1:03 OSR3 DC03 Tx04 Rx04 OSR·
1 - - - - - r - - OCD4
Tx05 Rx05
......_ __ , - - DoScRo5s
TxOO Rx06 OSR6
1 - - - - - r - - DCOB
T·D7 Rx07 OSR7
'----....z-- 0C07
Figure 1 · 78808 Octal ART Functional Block Diagram
Confidential and Pl'Oprietary
-~~.,.,..,._.~.J@!~"'·"'-""-·"'""""'"."._.".'._,...................,._,.. .. ..,,_~.-.. - - - - - - - - - - - ·
..Pi,.~d ~~efinitions
The input and output pins and power and ground connections of the 78808 Octal ART are shown in Figure 2. 'Thble 1 provides a summary of the signals defined in the following paragraphs.
..uz
~
>
~
u..J
"' wI:arw:n;-:;
0 0 ,<l
....
a 0
<(
N
0
0
"'0
0
I§ <(
<(
aCi
<(
0
aa 1a0:
<C, .· .-r
"' "a:
~
z
..J
0 0
!:!: !:
z 0z
..J ..J
0 0
!:!: !:!:
>a0
Tx07 OSR7 DCD7 Rx07.
RxD6
5C56
DSRli TxD6 Tx05
DSR5 ocps
Rx05 RxD4
DcD4 i'iSR4
TxD4
VOD
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 61
63
63
41
64
,
_ __;_,..o:_.;__ _ ,
40
65
I
I
39
66
l
I
38
6i'
I
I
37
68
I
78808
I
36
2 .3
4 5
I I
CAVITY DOWN CONNECTIONS
II I lOPVIEW
II III I.___ . _ _ _ ..;.;. _ _ _ .JJ
35 34 33 32 31
6
30
29
8
28
9 10 11 . 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
VSS2 TxD3
. 'DSR§ ;·
OCiTh
·RxD3
RxD2 DCD2
5SR2
Tx02
TxD1
mi 5Ci51 RxD1:. Rx DO
ocoo
DsRO
TxDO
Figure 2 · 78808 Piti Assignments
Confidential and Proprietary
-
Pin
10·13~22-25
50-52,54.56
Table
1.· '
78808 Pin
- --
'
and
Signal -
Summary
' -
. "
.
~
ot<1:0:> ·
~D<5:0>
input/output Data liries < 7:0:>-Receiveli and trans-
. mi~s the'parallel data,;
17 21,53
input
18
WR
14
15 57
58 62,67,2;7,
41~36,33,28
63,66,3,6, 40,37,32,29 49
RDY.
~·
MRESET
input input
CLK
DSR<7:0>
inpUt
inputs
DCD<1:0> inp~ts
IRQ.
45-47
IRQLN<2:0> output
48
'IRQTxRx
output
61,68,1,8, 42,35,34,27
64,65,4,5, . 39,38,31,36
44,26,9
16,59,43
'fxD<:7:0>
RxD<7:0>
. Vnn
v"
outputs
outputs
input input
Chip ~l~""'°'.A.ctlv.ates the; @ct;al ~T. to receiN~1,and \tt·!lsmit d4*ta over the .DL <.7;Q~Jines.
m i nati 's~~ .· f' am{ .2-Re&iva ·timllig
inforniati6tt for 'data t!ahSfet'.s. The and DS2 inputs must he. connected
togetbei.:
Wri~Specifies ~rection !'.)f data transfer
.<lnthe .E>L< 7:0 > lines.
Ready-Indicates when the Octal ART is ready to p~icipate in data transfer cycles.
Reset-Initializes the internal logic.
Manufacttrring re~t-Fo~ manufactur~ use;.
Clock-Clock input for timing.
Data set ready-Monitor data set readt (DSR) signals from modenis.
Da~ set carrier de~ct-Monitor data s~ earner det~ (DCD) signals from inodems.
· lnteriupt ~uest..:..:.Requests a processor interrupt.
Interrupt ~uest line number-Indicates the line number of originating interrupt request.
Interrupt request ,transmit/receiv'e-Indi-
cates whether an interrupt request is for
transmitting or re¢eiving data.
Transmit data-Provides asynchronous bit-serial data.output streams. Receive data-~pts asyncbro'nous bitserial data input streams.
Voltage-Power supply voltage +) Vde.
Ground-Ground·reference
3-3
-
78S08
Data and Address
; .. . ·.
Data lines (DL < 7:0 >)-These Iirl~s are used for the p~~l 'transmission and reception of data
'are between the CPU and the Oci:~ ART,· The receivers active when the data strobe (DS 1, DS2)
signal is asserted. The outpu,t drivc:rs are active otily w~n the chip select (CS) signalis assertt!d,the
data strobe (DSl, DS2) signal is asserted, and the write (WR) signal is deasserted. The drivers will
become inactive (high-impedance) within 50 nanoseconds when one or more of the following occurs: the chip select (CS) signal is deasserted, the data strobe (DST, ~)signal is deasserted, or
the write (WR) signal is asserted.
Address (ADD< 5:0 >)-These lines select which Octal ART internal register is accessible through
thle data I/O lines (DL<7:0>) when the data strobe (DST, DS2) and chip select (CS) signals are
asserted. Table 2 lists the addresses corresponding to each register. The receiver buffer and
transmitter holding register for .each line have ·the same address. When the (\WiI) signal is
deasserted, the address .accesses the. receiver buffer register and when asserted, it accesses the
transmitter holding register.
·
'lable 2 · 78808 Registers Address Selection
ADD Line*
54 32
0 0 0 .0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0 0
1 0
o. 0
0 0
0
1
1 0
1 1
ReadjWrite
Read Write Read Read/Write Read/Write
Register
Line 0 Receiver Buffer Line 0 Transmitter Holding Line 0 Status Line 0 Mode Registers 1, 2 Line 0 ·Command
0
0
1
0
0
0
0
0
1
0, 0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
0
1
0
1
1
Read Write Read Read/Write Read/Write
Line l Receiver Buffer . Line 1 Transmitter Hol~ Line 1 Status Line 1 Mode Register 1, Z Line 1 Command
0 10 0 00
0
1
0
0
0
0
0 1 0 0 .o 1
0
1
0
0. 1
0
0 1 0 0 1 1
Read Write Read Read/Write Read/Write
Line 2 Receiver Buffer Line 2 Transmitter Holding Line 2 Status Line 2 Mode Register 1, 2 Line 2 Command
0
1
1
0
0
0
0
1
1. 0
0
0
0
1
1 0
0
1
0 1
1
0
1
0
0110 11
Read Write Read Read/Write Read/Write
Line 3 Receiver Buffer Line 3 Transmitter Holding Line 3 Status Line 3 Mode Register 1, 2 Line ;3 Command
100 00 0
1
0
0
0
0
0
1
0
0
0
0
1
1 0
0 ·O
1
0
1
0
0
0
1
1
Read Write Read Read/Write Read/Write
Line 4 Receiver Buffer · Line 4 Transmitter Holding Line 4 Status Line 4 Mode Register 1, 2 Line 4 Command
3-4
Confidential and Proprietary
' --~-~- -·~~-~- '
. ~-~-----~--~-·---_,_~~-""""'~~.~~~'°-~~~n-"·--~"1', ,oo,_,0J¢0·~N
-
~
ADDLine*
' 1
4 0
3 1
2 0
1 0
0 0
10 100 0
10 10 0 1
10 10 10
1
0
1
0
1
l
l
10 0 0 0
1100 00
11000 1
1100 10
1100 11
Read/Write
Read Write Read Read/Write H.e.ad/Write
:Read
.Write
Read Read Read/Write
1110 00
1 1 10 0 0
1110 0 1
1
1
l
0
1
0
1110 11
xxx1 0 0
xxx1 0 1
Read 'Write Read
Read/Write Read/Write
Read Read
*X =Either 0 or 1.
788'8
Register
Line 5 Receiver Buffer Line 5 lhulsmitter Hoklmg Line 5 Status Line 5 Mode Register 1, 2 Line 5 Command
Line 6 Recdver B~
Line 6 ~tter Holding Line 6 Status Line 6 Mode :Registe~ 1, 2 Line 6 Command
Line 7 Receiver Buffer
Line 7 Transmitter Holding Line 7 Status Line 7 Mode Register 1, 2 Line 7 Command .
Interrupt Summary Data Set Change Summary
Bus Transaction Contto1
Chip select {CS)-This signal is asserted to perm.it data transfers through DL < 7:0 > to or from
the internal registers. Data transfer is controlled by the data strobe (DSl, DS2) signal and write (WR) signal.
Data strobe (DSl, DS2)-The data strobe inputs (DS1 and DS2) must be connected toget:her..·This
input receives timing information for data transfers. During a write cycle; the CPUasserts the data strobe signal when valid output data is available and deasserts the data strobe signal before the data
is removed. During a read cycle, the CPU asserts the data strobe slgnaland the Octal. ART transfers the valid data. When the data strobe signal is d~rted, DL <7;0> bec:Qme a high impe4ance.
Write {ft)-.;.The write (WR) signal specifies thed~ion of data transfer on the DL < 7:0 >pins
by controlling the direction of their transceivers. It the WR signalis asserted during adata transfer
(the CS, DSl, and DS2 signals asserted), the Octal ART is receiving data from DL<7:0>. Uthe
WR signal is deasserted during a write data transfer, the Octal ART is driving data onto DL < 7:0> .
Interrupt Request
Interrupt request iiQ)-The iRQ pin is an open drain output. The integral interrupt scanner
asserts the IRQ signal when it has detected· an interrupt condition on one of the eight serial data
lines.
y:mfidl.':ntial and PtoprielmY
3-5
...
Preliminary
78808
Interrupt request ti'ansmit/receive (IRQl'xlb)-This signal indicates when the interrupt scanner in the Octal AKI' stops and asserts IRQ because of a transmitter interrupt condition (the IRQTxRx signal is asserted) or because of a receiver interrupt condition (the IRQTxRx signal is deasserted).
The signal is valid only while IRQ is asserted. The state of IRQTxRx signal also appears as bit 0 of
the interrupt summary register.
Interrupt request line number (IRQLN < 2:0 >)-These lines indicate the line number at which the Octal ART interrupt scanner stopped and asserted the interrupt request (IRQ) signal. The number on these lines is valid only while the IRQ signal is asserted. The IRQLN2 is the high-order
bit and IRQLNO is the low-order bit. The state of these signals also appears as bits in the interrupt
summary register: IRQLN2 as bit 3, IRQLNl as bit 2, and IRQLNO as bit 1. Table 3 shows the line numbers corresponding to settings of IRQLN <2:0 >.
IRQLine
2
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Table 3 · 78808 Interrupt Request Line Asignments
Line 0
0
0
0
1
0
2
1
3
0
4
1
5
0
6
1
7
Serial Data mnsmit data (TxD<7:0> )-These outputs transmit the asynchronous bit-serial data streams. They remain at a high level when no data is being transmitted and a low level when the TxBRK bit
in the associated line's command register is set.
Receive data (RxD < 7:0 >)-These lines accept asynchronous bit-serial data streams. The input signals must remain in the high state for at least one-half bit time before a high-to-low transition is
recognized. (A high-to-low transition is required to signal the beginning of a "start" bit and initiate
data reception:)
Modem Signals
Data set ready (DSR < 7:0 >)-These eight input pins, one for each serial data line on the 78808,
are typically connected via intervening level converters to the data set ready outputs of modems, A
TTL low at a DSR pin causes the DSR bit Chit 7) in the corresponding line's status register to be
asserted. A TTL high at a DSR pin causes the DSR bit in the corresponding line's status register to
be deasserted. A change of this input from high-to-low, or low-to-high, causes the assertion of the
data set change (DSCHNG) bit that corresponds to this line in the data set change summary
register. Changes from one state to the other and back again that occur within one microsecond
may not be detected.
·
3-6
Confidential and Proprietary
-
78808
Carrier detect (DCD < 7:0 >)-These eight input pins, one for each serial data line of the Octal
ART, are typicilly eonnected through intervening level converters to the received line signal detect (also called cattier detect) outputs of modems. A TTL low at a DCD pin causes the DCD bit of the
rorresponding line's status register to be deasserted. A change of this input from high-to-low, or low-to-high, causes the assertion of the data set change (DSCHNG)bit corresponding to this line in the data set change summary register. Changeidrom one st.ate to the .other and qa¢k again that occur within one microsecond may not be detected.
General Control S~s
.
.
Ready (RDY)-TheRDY pin is an open drain output. Upon detecting a negative transition of chip
select (CS), the Octal ART asserts the RDy signal to indicate ~diness to take part in data transfer
cycles. The·RDY signlll cleasserts after the trailing edge of CS. Reset (RESET)-Wht;:n th~ RE.$ET input is as~ted, the TxD <}:0 > lines are asserted and all
are internal status bits listed in the "Architecture Sutnmary"discu~si~n cleared.
Manufacturing reset (MRESET)-This sigrud is. for l.lllmufact~ use only and t~ input should
be connected to ground· for normal operation.
·
·
MisceOaneous Sigruds
Clock in (CLIC)-Allbaud rates and internal clocks are derived fJ.'()Jb this input. Normal operating
frequency is 4.9152 MHz ±0.1 percent and duty cycle is 50 percent ±5pen;:ent.
Power and Ground Voltage (V->-Power supply 5 Vde
Ground {V58)-Ground reference
· Architecture.Summary
The Octal ART functions as a serial-to-parallel, parallel-to--serial>converter/controllet:: It can be programmed by a microprocessor to provide different characteristics for each of its eight serial data lines (stop bits, parity, character length, split baud rates, etc.).
Each serial line functions the same as a one-line UART-type device thereby reducing the number of chips and conserving space on communication devices that require multiple communications lines.
An integral interrupt scanner checkS for device interrupt condidonson the eight lines. Its scanning algorithm gives priority to receivers over tra~rs. The s~er can also check for interrupts
resulting from changes in modem control signals DSR and OCI5.
Lioe·specific Registers Each of the eight serial data lines in the Octal ART has a set of registers for buffering data into and out of the line and for external control of the line's character.istics...These registers are selected for
access by setting the appropriate address on lines ADD< 5:0 >. Lines ADD< 5:3 > select one of the eight data lines. Lines ADD < 2:0 > select the specific register for that line. Refer to Table 2 for
the register address assignments.
Receiver buffer register-Each line's receiver consists of a character assembly register and a two· entry FIFO that is the receiver buffer register. When the RxEN bit in a line's command register is set, received characters are moved automatically into the line's receiver buffer as soon as they have been deserialized from the associated communications line. When there are characters in this FIFO, the RxRDY bit is set in the status register for the line.
Confidential and Proprietary
3-7
-
78808
The assertion of the RxRDYsigrial for a Une that already has the RxIE bit of iu command register set causes the interrupt scanner logic to stop and generate an interrupt condition (the IRQ signal is asserted). When the receiver buffer is read, the interrupt condition is cleared (the IRQ signal is deasserted) and the interrupt scanner resumes operation.
If there is another entry in a line's FIFO, the RxRDY bit remains asserted. When the interrupt scanner reaches this line again, the assertion of RxRDY causes the scanner to halt and assert the IRQ again.
Asserting the RESET signal or clearing the RxEN bit initializes the receiver logic of Octal ART. The RxRDY flag is cleared and the receiver buffer register outputs become undefined. Any data in the FIFO at that time is lost.
Transmitter holding register-Each line has a writable transmitter holding register. When the
TxEN bit in the line's command register is set, characters are moved automatically from the output of this register into the transmitter serialization logic whenever the serialization logic becomes idle.
When this register is empty, the TxRDY bit in the line's status register is set. If the transmitter interrupt enable (TxIE) bit in the line's command register is also set, the interrupt scanner logic halts and generates an interrupt condition. If a character is then loaded into the register, the interrupt is cleared and the scanner resumes operation.
Assertion of the RESET signal initializes the transmitter logic of the Octal ART. The TxRDY flag is cleared and the transmitter holding register's contents are lost. The transmitter enable (TxEN) bit in the line's command register is also cleared by RESET. If at the end of the reset process, the TxEN is reasserted and TxRDY bit is reasserted. Software clearing of TxEN alone produces results different from the full RESET in that the transmitter holding register's contents are not lost; they
are transmitted when TxEN is set again.
Status register-Each line has a read-only status register that provides information about the
current state of the given line. This register indicates a line's readiness for transmission or reception
of data and flags error conditions in its bit fields. Figure 3 shows the format of the status kgister. Table 4 lists the flag bits in each status register.
7 6
5
4
3
2
0
DSR--___,
DCD------'
FER~~~~~~--" ORR~~~~~~~~- PER~~~~~~~~~~--'
TxEMT-------------'
RxRDY~~~~~~~~~~~~~--' TxRDY~~~~~~~~---~~~~~~--'
Figure 3 · 78808 Status Registers (Line 0-7) Format
3-8
Confidential and Proprietary
-
Bit 7 6 5
4
3
2
1
0
1'.aWe 4 · 78808 S·tus Registers (Lines 0-7) Description
Description
DSR <Data set ready)-Tbis bitis the invertedstate ofthe DSRJ.ine.
DCD (Data set carrier detect)-This bit is the inverted state ohhe OO'i3' Urie.
FER (Frame error)-Set. wh~ the teeeiv~· ~~cter .<;urreiiif¥,.flisplayed ip the
re.ceivet buffer rem~teJ: Was OQtframed by. ~Stoll bi~. Qnly f;he(irst ,sl:Qp bitis .check,ed to det¢tntlne that ~. ~ng error ~ts~ Sµbseq~nt. ~a~. p~ the
is receiver buffer register that indicates all ze~s (j~uditig ~h~ parit}r ~it, if any) can
be interpreted as a Break condition: This hit d&r&i DY clearfug Rx£N (bit 2) of the command registei; by asserting the lIBSET input, or by setting the reset error
RERR (bit 4) of the command register.
ORR (Overrun error)-Set when the character in the receiver buffer register was
not read before another.character was receiveq·.Cle~ by clearing RxEN (bit 2) of
the corilmand register, by asserting the the m!T·input, or by setting reset error
RERR (bit'4)of.the command register.
'
'
' ' · · ',.,",i'''"-·'·'1,·",· "--·-,;' ,,._, __
PER (Parity error)-!£ parity is enabJed and th,is bit is set, the received character in
the receiver buffer register has an iii.correct: paricybit: Tllis bit is cleared by clearing
RxEN (bit 2) of the command register, by asserting the:~ input, by setting
reset error REim (bit 2) of the command register, or Wreading the current
character in the receiver buffer register.
· ·
TxEMT (Thmstnitter ei:npty)-;Set when the ttansmitter serialization logic for the
associated line has completed transmission of a character, and no new character has been loaded into the transmitter holding register. Cleared by loading the transmit· ter holding register, by clearing TxEN (O) of the command register, or by asserting the RESET input.
._,}, >f'"·
RxRDY·(Receiverhu£furready)~When set, a Character has beenloaded into the FIFO buffer from the ckser.ialii;ation logic,Cle~ by ~ding tnt receiver butfer
registe.tj by clearing :RxEN (bit ·2) in the command c1:qistez; or by asserting .the
RESET iriput..·
TxRDY (Transmitter holding register ready)-When set, this bitindicates that the
transmitter holding register is empty. Clea1'00 ·when the program has loaded a
character into the transmitter holding register, when thetransmitter for this line is disabled by clearing TxEN (bit O) in the q~and register, or. by asserting the RESET input. This bit is initially set when th~.transminer logic is enabled by the setting of TxEN (bit 0) and the transmitter holding register is empty. This bit is not
set when the automatic echo or remote loopb~ modes· are prognunmed. Data can be overwritten if a consecutive write is pmotrned while TxRDY is cleared.
Confidential and Proprietary
3-9
Preliminary
Mode registers 1 and 2;-These read/wtite registerivcontrol the ~ttributes (including parity,
·character length, and line speed) of the communications line.
Each of the eight communications lii:ies has two of these registers, both accessed by the same address on ADD<5:0>. Successive access operations (t>ither read or write, in any combination) alternate between the two registers at that address by use of an internal pointer. The first operation addresses modi:: register 1, the next address mode register 2, and another after that would recycle the pointer to mode register 1. The pointer is reset to point to mode register lby RESET or by a read of the command register for this line.· These registers should not be accessed by bit-oriented
instructions that do read/modify/write cycles such as the PDP-11 BIS, BIC, and BIT instructions.
Figure 4 shows the format of mode registers 1 and Table 5 describes the function of the register information.
7
6
5
4
3
2
0
STOP-
·1
PAR C T R L - - - - - - - '
CHAR L E N G T H - - - - - - - - . . ,
RSRV~-----,..---------'
MCIE - - - - - - - - - - - - - - - - '
Figure 4 · 78808Mode Registers 1(Line0-7) Fotmat
Bit 7,6
5,4
3-10
Table 5 · 78808 Mode Registers 1 (Lines 0-7) Description
Description
.·STOP.-...These bits determine the number of stop bits that are appended to the transmitted characters as foll~. These bits are cleared by asserting the RESET
input.
Bits
7
6
Stop Bits
0
0
Invalid
0
1
1.0
1
0
1.5
1
1
2.0
PAR CTRL (Parity control}-These bits determine parity as follows and are cleared by asserting the RESET input. X= either 1or0.
Bits
5
4
Parity Type
1
1
Even
0
1
Odd
x 0
Disabled
Confidential and Proprietary
....
.1ases
Bit
Descdption
.3,2
CHAR LENGTii (Character length)-These bits determine the length (excloomg
stllft blt, parity, and stop bits) of the. characters received IPid sent. Received
characters ofless tluln 8 bits are "right aligned"iq. the receiyer buffer with unused
Iell&th high-ordci: ~i~~,equal to zero. Patjty bits .are not shO\Vn in t}le ~~ver buffer. The
charaeter
bits are cleared by asserting tlie mm' foput. The character
length bits are defined as follows: ·
Bits
3
2
Bit Length
0
0
5
0
1
6
1
0
7
1
1
8
1
RS,RV (Rese~ ~nd d~d by asserting the R£m input.)
0
MCIE (Modem control inte;mipt enable)-When set and ,RxIE (bit 5) of the
command register is set, the moc:lem control in~pt,s are ,enabled. Refer to the
Interrupt Scanner and Interrupt Handling infoqnation. Cleared by asserting the
~input.
Figure 5 shows the fo~t of D19de ~ters 2. and ';f!lble 6indic~tes th' b'll4ra(e ~ectiC>ns of the
register. Bits 7 through 4 of~~ re~~ 2 conti-91 tpe ~ro,\~.~~,~~ bi~s 3 thfough 0
control the receiver baud rate. These registers are cleared by s.SsertingR'ES!Tinput.
7 6
6 4
3
2
0
I
XMIT RATE RECV RATE
I
Figµre 5 · 78808 Mode Registers 2 (Line 0-7) Format
'
-
. '
Confidential and ~prietary
3-11
-
Preli.miriary
78SQs
o. Tuble 6 · 78808 Mode Registers 2 (Lines 7) Description
Bit
Descriptior;t
7:0
XMIT RATE/RECV RATE (Transmitter/Recever Rate)-Selects the baud rate of the
transmitter (bits 7:4) and receiver (bits 3:0) as follows:
'llansmitter Bits
7 6 s4
Receiver Bits
Nominal Actual
3 2 1 0 Rate Rate
Error* (percent)
0 0 0 0 00 0 1 00 10 00l 1 0 100 0 10 1 0 110 0 1 1 1 10 0 0 10 0 1 10 10 10 1 1 1 100 110 1 1 1 10 1 1 1 1
0 0 0 0
50 same
000 1
75 same
00 10
110 109.09 0.826
0 0 11
134.5 133.33 0.867
0l 00
150 same
0 10 1
300 same
0 1 10
600 same
0 1 1 1 1200 same
1 0 0 0 1800 1745.45 3.03
1 0 0 1 2000 2021.05 1.05
1 0 1 0 2400 'Same
1 0 1 1 3600 3490.91 3.03
1 1 0 0 4800 same
1 1 0 1 7200 6981.81 3.03
1 1 1 0 9600 same
1 1 1 1 19200 same
*The frequency of the clock input (CLK) is 4.9152 MHz. The clock input may vary by 0.1 percent. This variance results in an error that must be added the error listed.
Command register-These read/write registers control various functions on the selected line. Figure 6 shows the format of the command registers and 'Table 6 describes the function of the register information.
7
6
5 4
3
2
0
RxlE - - - - - - - '
RERR~---~~~-TxBRK~---~---~~
Rx E N - - - - - - - - - - - - ' TxlE - - - - - - - - - - - - -
TxEN----~-~---~-----'
Figure 6 · 78808 Command Registers (Line 0-7) Format
3-12
Confidential and Proprietary
-
7,6
5 4 J
2 1 0
'Jlible 1· 78808 Command Regist.ers (Lines o.7) Descripdon
78808
OPER MODE (Operating mode}-These bits control the operating mode of the channel as follows. These bit!' ~cleared byasserting the RESET input.
Bit
7
6
Operating Mode
0
0
Normal operation
0
1
.Aµtomatie echo
1
0
Loe~ ioopb!llck
1
1
~motecloop~
IWE (Reeeiver interrupt enable}---When set, the RxRDYffag (bit 1) ofthe ~tatus
register for this linewill generate an interrupt.
this the RERR: (Reset error)~When set, bit clears tnmiing error, overrunerror, and
parity ettor ofthe status register associat;Cd With this line. This 1'it must be cleared
before errors that occur wil:lpe reccirded in the Stafuiregistet Th.is bit is cleared by
asserting the trnm"rinput (l10t self-clearing). ·
when r~RK ('lhmsmit break)-
set, this I* forces the a,ppropriate 1'J(b<7:O >
line to the. spacing stai;e at the :conclusion. of the character presently being
transmitted·.When, the .pragnw;i ~ thi~ bit, .norm.al operation is restored, ;µid
arul any character pending in the transmitter holding register is moved ipto the
serialization logic transmitted:.The minimum breaklength obtainable is twice
· the cllaradet length plus 1 bit d!lie. The maltimum break le~th depends on the
amo.unt of time between the pro~ settirig ariddearing dlis bit, buds anin~ral
number of brttimes. This bitis Cle!tted by asserting the·~ input.
RxEN (Receiver enable)-When set, this bit· emroles the receiver l~gic. When
cleared, it stops the assembling of the received character, clears all receiver error bits and the RxRDY (bit 1) of the status register; clears any receiver interl:upr conditions associated with this line, 'and initializes all recei'ver logic. This bit is cleared by
assemn~ the Imm input"
TxIE (Transmit il;lter~pt enab}e)-When set; the s~~ of ~e associated TxRDY flag (bit 0) Q~ the s~tus reg~ster i~ .made available to.~ interrupt scatll1er logic. When the interrupt scanner logic scans this llne, it deter'mines if the T'1'RPY flag is . asserted and generates an interrupt by asserting tl}e IRQ s~na.l.
T:i>EN, (Transmitter enable)-:-When set, this bit enablesi. the transmitter lo~c.
When. cleared,. it inhibits the :redaHzation of the. cha.meters that follow but .the
serialization of the current character is completed. It also clears the T:xRPY.flag (bit O) of the status register, clears any transmitter interrupt conditions associated with
this line, and initializes all transmitter logic except that associated with the
transmitter holding register. The character in the transmitter holding register is retained so that XON/XOFF situations can be properly processed. This bit is cleared by asserting the RESET input.
Confidenti~ and Pt'l:>pdetary
3-13
-·
7~08
Bits 5 through 0 enable theJ.i.ne's receiver and tral!lStn,i.tter, ep.able handling of interrupts, initiate the transmission of break characters, and ~set error bits fC>r the line. Refer to "Interrupt Scanner" and "Interrupt Handling" paragraphs for detailed interrupt information. Bits 7 and 6 control the operating mode of the line. The four modes that can be set are
· Normal operation-The serial data received is assembled in the receiver logic and transferred in parallel to the receiver buffer register. (The RxEN bit must be set.) Data to be transmitted is loaded in parallel into the transmitter holding register, then automatically transferred into the transmitter logic and serialized for transmission. (The TxEN bit must be set.)
· Automatic echo-The serial dat.a received is assembled into parallel in the receiver logic (the RxEN bit must be set) and transferred to the receiver buffer register. Arriving serial data is also routed to the line's TxD < n > pin for serial output. TxEN is ignored and the transmitter logic is disabled. TxRDY flags and TxEMT indications are cleared. No transmitter interrupts are generated.
· Local loopback-The serial data from the RxD<n> input is ignored and the receiver serial input receives data from the transmitter serial output. That data is assembled into parallel form in the receiver logic (the RxEN bit must be set) and transferred to the receiver buffer register where it can be read by the program. Data to be transmitted to the receiver is loaded in parallel form into the transmitter holding register from which it is automatically moved into the. transmitter logic and serialized for transmission. (The TxEN bit must be set.) The transmission goes only to the
receiver serial input; the TxD < n > output is held high. As in normal operation, transmission
and reception baud rates are controlled by the transmitter speed and receiver speed entries in
mode register 2.
· Remote loopback-The serial data received on the RxD < n > line is returned to the TxD < n >
line without further action. No data is received or transmitted. The RxRDY, TxRDY, and TxEMT
flags are disabled. The. TxEN and RxEN bits of the command register are held cleared, causing
the transmitter and receiver logic to be disabled.
·
Summary Registers The Octal ART contains two registers that summarize the current status of al,l. eight.serial data lines, making it possible to determine that a line's status has changed with a single read operation. These registers are selected for access by setting the appropriate address on pins ADD<2:0>. Because the registers are shared by eight serial lines, the line-selection bits (ADD< 5:3 >} are ignored when these registers are accessed. Refer to "Interrupt Scanner and Interrupt Handling" for detailed interrupt information.
Interrupt su~ register-This read-only register indicates that a transmitter or receiver interrupt condition has occurred, and indicates the line number that generated the interrupt. Figure 7 shows the format of the interrupt summary register and Thble 8 describes register information.
3-14
Confidential and Proprietary
-
7 6 5. 4 3 2
0
\ IRQ---'
l
RAZ------·
:i
TINx.T/RLxIN.E...N._O_-_-_ -.- ...._- ......- .._-_ -.- ..._- _ -__',_ __ .
Figure 7 · 78808 Interrupt Summary Register Format
Bit
Descdption
7
JRQ (Interrupt request)-When set, this bit indicates that the interrupt scanner
has found an interrupting c:;~tl $!!00ngJheftight se.rial lines 0£ the Octal ART.
These conditions also result in the Octal A;R'I'. allsertmg the lR.'O sigmtl.
6:4
RAZ (Read as zero)_:_Not: used
3:1 *
INT L!NENO (~nterruptiilg Jine Aµtnher)- 'I1iese bit.s. indicat~ the line .number
upon which an interroptitig c~~tion was fo\lnd. 'l'hesebits correspond to the
IRQLN<2:0> signals_;_(bit··3..,IRQLN<2>, bit 2;.,,IRQLN<l>, and bit
1=IRQLN<0>. Refer to 'fableJ:
O*
t!ie Tx/Ri. {Transµtlt/rece~ve)~this bit ~nd,icates.~~th.rt intern.lpting conditiqn
was.caused by a transmitter (T#Jieq'1als 1) ora~eiver (Tx/!iequalsO). this bjt
corresponds to the IRQTxRx signal of the Octal ART and is set when IRQTxRx is .
asserted.
·
· ·
and *Bits 3-0 above represent the outputs of a free-n,mning counter are valid only when bit 7 is set.
current Data set change summary register-When the DSR or OCi5 inputs that are associated.witha line
change state, the bit corresponding to that line in this read-only register is set. The
state of
the DSR and Da5 inputs can then be obtained from that line'utatunegi.s.ter. If the state ofa line
changes twice within one microsecond, The change instate·may not be detected. Figure 8 shows
the forlllllt of the data set change summary registet. ·
6
5
4
3 2
0
OSCHNG 7-0 _ _ _ _ _ __,
Figure 8 · 78808 Data Set Change Summary &gister Format
Confidential and Proprietary
3-15
78808
When the MCIE bit in a line's mode ~gister 1 is i;etand RxlE is also set, the modem control
interrupts are enabled for that line. If DSCHNG forthat line is then set, the interrupt scanner will halt and assert the IRQ signal. The data set change summary register bits are cleared by writing a 1 into the bit position. A program that uses this register should read and save a copy of its contents. The copy can then be written back to the register to clear the bits that were set. The system interrupts should be disabled and writeback should directly follow the read operation. Assertion of the RESET signal disables and initializes the data set change logic. When the RESET signal is deasserted, future changes in DSR and DCD are reported as they occur.
· Interrupt Scanner and Interrupt Handling
The interrupt scanner is a four-bit counter that sequentially checks lines 0 through 7 for a receiver interrupt (counter positions 0-7) and then checks the lines in the same order for a transmitter
interrupt (counter positions 8-15). If the scanner detects an interrupt condition, it stops and the IRQ signal is asserted. An interrupt must be serviced by software or no other interrupt request can
be posted.
The scanner determines that a line has a receiver interrupt if the line's receiver buffer is ready and receiver interrupts are enabled for that line (RxRDY and RxIE= 1) or either of the line's modem status signals has changed state and both receiver and modem control interrupts are enabled for that line (DSCHNG and RxIE and MCIE= 1).
The scanner determines that a line has a transmitter interrupt if the line's transmitter holding the
register is empty and transmitter interrupts are enabled for that line (TxRDY and TxIE = 1).
When the scanner detects an interrupt, it reports the line number on th~ IRQ < 2:0 > lines. The
· IRQTxRx signal is asserted for a transmitter interrupt and deasserted for a receiver interrupt. The appropriate bits are also updated in the intertupt summary register. The IRQ lineis deasserted and the scanner is restarted for each of the following three types of interrupt conditions.
· Reading the receiver buffer or resetting the RxIE bit of the interrupting line for the first type of receiver interrupt previously described.
· Resetting the MCIE, RxIE, or DSCHNG bit of the interrupting line for the second type of receiver interrupt previously described.
· Loading the transmitter holding register or resetting the TxIE bit of the interrupting line for transmitter interrupts.
If the scanner was originally stopped by a receiver interrupt condition, the scanner resumes sequential operation from where it stopped, thus providing receivers with equal priority. If the scanner was stopped by a transmitter condition, the scanner restarts from position 0 (line O's
receiver), thus giving receivers priority over transmitters.
· Edge-triggered and Level-triggered Interrupt Sys{f:ms
If the interrupt system of the Octal ART is used only for generating interrupts for thee RxRDY and/ or TxRDY flags, the IRQ line can be connected to a processor having either edge-triggered or leveltriggered interrupt capability. If the modem control interrupts are being used (MCIE in mode register 1=1), the IRQ line can be connected only to a processor that uses level-triggered interrupts.
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Confidential and Proprietary
·-
138o8
· Modem Handling
The TxEMT (transmitter empty) bit of the status register is typically used to indicate when a . program can disable the transmission medium, as when deasserting the request-to-send line of a modem. A typical program will load the last character for transmission and then. monitor the TxEMT bit of the status register.
The assertion of the TxEMT bit to indicate that transmission is complete may ~r ~ substantial
time after the loading of the last character. After the last character is loaded, oni~r is in the
transmitter holding register and one character is. in the serialization .lggic. Theref6~~ frwill be t.wo
character times before the transmission process is completed.i ~icing for theJf:xRDY signal tQ. ·
assert before monitoring the TxEMT status shortens this by Onetl:hatacter time because the TxRDY
status bit indicates that there are no characters in .the transmitter holding register. The times
involved are calculated by talcing the reciprocal ofthe baucirate being used, multiplying by the
number of bits per character (a start bit-5, 6, 7, or 8 data bits; p)b$.parity bit if enabled; and 1, 1.5,
or 2 ·stop bits), .and multiplying by either two characters or one, ·depending on wh~ TxEMT
monitoring begins.
·
··
·
·Specifications
The mechanical, electrical, and environmental characterislf..s ~;~cificatiqns ~,the Octal ART
are described in the following paragraphs. The test conditi~:ins for the electriclljh1:alues llt'e as follows unless specified otherwise.
· Temperature: 0°Cto 70°C
· Power supply voltage <Vnn): 4.75 V to 5.25 V
Mechanical Configuration The physical dimensions of the 68-pin package are contained in Appendix E.
Absolute Maximum Ratings Stresses greater than the absolute maximum ratings may cause permanent damage to the device. Exposure to the absolute maximum ratings for extended periods may iidversely affect the reliability :0£ the device.
· Power supply voltage (V00): 7.0 V
· Input or output \toltage applied: - 5 V to 7.0 V
· Storage temperature: -65~C to 125°C
Recommended Ope..ating Conditions · Power supply voltage (V00): 5 V ± 5% · Operating temperature (TA): 0°C to 75°C
de Electrical Characteristics
The de ele<:ttical characteristics of the Octal ART for the operating voltage and temperature ra~s
specified arelisted in Table 9.
· ·
·
Confidential and Proprietary
3-17
-
78808'.
Symbol
Table 9 · 78808 de Electrical Characteristics
Parameter
Test Condition
Requirements
Min. Mu.
High-level
2.0
input voltage
Low-level
0.8
input Y9ltage
High-level
output voltage
Vrm=Min.
2.4
loH=-3.5 mA for DL<7:0>.
loH=-2.0 mA for all
remaining output except
lRQandRDY
Low-level
Voo=Min.
0.4
output voltage
lot =5.5 mA for DL< 7:0>
lot= 3.5 mA for all
remaining outputs
Units
v v
v
v
Input current
at maximum
input voltage
Von""Max. V1= Vnn (Max.)
10 µA
Input current at minimum input voltage
V00 =Max. V1 = 0 . 0 V
-10 µA
Short-circuit output current forDL<7:0>
Von=Max.
all remaining
outputs except
IRQandRDY
lozi.l
Three-state
Vnn=Max.
output current
Vo=0.4 V
-50
-180 mA
-30
-110 . mA
10 µA
output current
Von=Max. V0 =2.4 V
100
Supply current
Vuo=Max.
T"=Oo
C.,
Input
capacitance
10 µA 240 mA
4.0 pF
C10'
Input/output
capacitance
5.0 pF
1No more than one output should be short circuited at a time and the duration of the sh?rt should
not exceed 1 $CCOod. .
.. . . . . .
.
. .
. .. ·
zAll three-state output drivers are wired in an I/O configuration. The paran:ieters include the driver
and input receiver leakage currents.
·
'The parameters include the capacitive loads of the output driver and the input receiver.
3-18
Confidential and Proprietary
--
·ac.Jilectrical ~
The device propag~n delays specified in the ac characteristics figures and tables asstinie the
loading ConditlOns sh()\vn in Figure 9.
. .
.
TEST POINT
vDD
vDD
2.7k0*
I k fl
1kn OFRUOTPMUT ,.__..__ _..._........-fll---t
·usED
ONLY
FOR
, '
IRQ "''
and
-
ifrj.f,..,
LOAD A- STANDARD OUTPUTS
FROM OUTPUT
TEST POINT
S1 CLOSED: PU:LL UP ....$2,.CLOSEO: PULL DOWN
S1 Ar.IQ ~2 CLOSED: DIVIDER
LOAD B - THREE-STATE OUTPUTS
Figure 9 · 78808 Output Load Circuits
3-.19
-
Preliminary
'1s8otr
r mu·ng Parameters
... ·
Figure 10 shows the signal timing for a read cycle! to tt:ansfednformation from the Oct.alART to the
processor. Figure 11 sh0ws the signal timing· for a write cycle. to transfer informatioii from the
processor to the Octal ART. Table 11 lists the timing parameters for the read and write cycles.
DS1/0S2 AOD<5:0> WR
-------toPWH-------i
VALID ADDRESS
1wsu
Figure 10 · 78808 Bus Read Cycle Timing
3-20
Confidential and Proprietary
DS1fDS2
Preliminary M > - - - - - -1D P W H - - - - -
ADD< 5:0'>
VALID ADORE$$
~~~·,...--++-~~~~--~
1Asu
78808
_ _.....+-tcsu
Ol<7:0> ------+-<I
Figure n · 78808 Bus Write Cycle Timing
Reguiremtrnts
(ns) ·
Load
Mm. ~· Circuit1
tAuo Hold time of a valid ADP-;:: 5:0 > to a valid high level of
DSlandDS2.
10
t.uu
Setup time of a valid ADD< 5:0 > to the falling edge of
DSiandm.
30
tcuo Hold time of a valid low level ofCS to a valid,high level of
DSiandm.
lo
tcsu Setup time of a valid low level of CS to thefalling edge of
DSl and DS'i.
30
Propagation delay of avalid low level on DST and,~ (if CS is low and WR is high) to valid high or low data on DL<7:0>.
165 CL=150pF
Confidential and Proprietary
3-21
-
Symbol Definition
tonLZ 2 toom:
tDDZL toDZH
m Propagation delay of a valid high level on and D'S}
(if CS is low and WR is high) to DL<7:0> output
drivers disabled. toou
tDDHZ
tonu
toouz
toDLZ
tDDHZ
Propagation delay of a valid low level on I5SI and~ (if
CS is low and WR is high) to DL<7:0> output driver enabled.
toDZL
tonm
Requirements
(ns)
Load
Min. Max. Citcuit1
50 CL=50 pF 50 CL=50 pF 60 CL= 100 pF 60 CL= lOOpF 65 CL=150pF 65 ~=150pF
0 165 CL=150pF 0 165 CL=150pF
top
Hold time provided during a read cycle by Octal ART of
valid high or low data on DL < 7:0 > after the rising edge
of DSl and DS2.
0
touo Hold time of a valid DL<7:0> to a valid high level of
DSi andDS2.
30
to!'WH Pulse width high of DSl and DS2.
450
toPWLR
tnPWLw tosu
Pulse width low of DSl and DS2 when WR is high (read operation). Refer to timing parameter tnPWLw also.
Pulse width low of DST and W when WR is low (write
operation). Refer to timing parameter tnPWLll also.
Setup time of a valid DL < 7:0 > to the falling edge of I5SI and DS2.
180 10,000 130 10,000 130
tm'
Propagation delay of a valid low level on DS1 and DS2 (if
CS is low) to a high level on IRQ.
635 Ct=50pF
tIIDH4 Propagation delay of a valid high level of CS to a valid high level on RDY.
210 CL=50 pF
tRDL
Propagation delay of a valid low level on CS to a valid low
level on RDY.
90 CL=50pF
twao
m Hold time of a valid high or low level of WR to a valid
high level of and~.
10
twsu Setup time of a valid high or low level of WR to the
falling edge of DST and DS2.
30
'Refer to Figure 9 for the load circuits used with these measurements.
3-22
Confidential and Proprietary
-
2The tiiDLZ and tDDHZ ~rs are meas\lred wi,th .Ci.= 150 pF. The values of tDDLZ and tnDHZ for CL"" 50 pF and Ci.· lQO pF have been derived for user convenience. ·
'Total rise time depe~'on internal delay plus the pullup delay introduced by the external resistot
used: being The tin Pu9metercan be calculatedby the foll~: tm == 500 +RCi. where R= value of
the resistor that connects to eapacitor Ci. in load A, Figure 9.
·Total rise time depends on internal delay plus thepullup delay introduced by the exte~ resistor
being used. The tima parameter Can be calculated by the following:l-= 75 +RCL where R· valµe
of the resisror that connects to capacitor CL in load A, Figure 9.
Figures 12 shows the signal timing for the clock inpll~' interrupt~. effectof the RESET input
on data strobe, data set carrier detect (DC'.D)'and data sef ~l (DSRlinput timing, and the transmit data output timing. Tuble 11 lists the timing parameters ~r Figures 12.
CLK ~tCPWL:r1·
IROLN <2:0> IRQTxRx IRQ
i \
tcP
;CPWHJ'
CLOCK
t.,,,;
/ :
\
l
~"~~
JNTl!RRUPT
AE8ET1. tRES
OS1/DS2
1.
to ASU
~. to RHO
.~
EFFECT OF RESET ON DATA STROBE
- OCO/DSR<7:0> - - - - "X:I1.:.:.:.:.-_-_V-A_L-tI_D0O5C_OPW/_O_S_R-O--A-T-A---------pf( ~~-----------
TxD< 7:0>
DCD/DSR IN PUT
'~i:=--t-Tx_s_K___..LtTxsKJ------r-
TRANSMIT DATA OUTPUT
Figure 12 · 78808 Miscellaneous Signal Timing
Confidential and Proprietary
.3-23
·-
.Preliminary
Table·u ·78808 MiscelJaneous W!ite Tnning Parameters
78808
Syinbol De6nition
Requirements (ns.)
Min. Max.
Load Circuit1
tcP
Period of CLK.
tc.wa Pulse width high of CLK.
tcPWL Pulse width low of CLK.
203.45 (4.9152 MHz) 95
95
tlWIO Hold time of a valid high level of DS1 and DS2 to
a valid high level of RESET.
1,000
t:oesu Setup time of avalid high level ofI5SI and DS2 to
the rising edge of RESET.
900
tllSPW Pulse width high or low of DCD < 7:0 > and
DSR<7:0>.
1,000
tmo
Hold time provided by Octal AlIT from !l valid
IRQLN<2:0> and IRQTxRx to a valid high
level of IRQ.
100 -
CL=50pF
t1su
Setup time provided by Octal AlIT from a valid
IRQLN <2:0 > and IRQTxRx to a valid low level
of'ffi"O.
100
CL=50pF
tllllS
Pulse width low of RESET.
1,000
tTXSK Pulse width high or low provided by Octal ART
on the TxD < 7:0 > lines. At each baud rate, the
actual pulse widths provided vary by tn:sx:· This
timing parameter should be used to determine
cumulative reception/transmission errors.
±250 -
CL=50pF
*Refer to Figure 9 for the load circuits used with these measurements.
:3-24
Confidential and Proprietary
-
Figure 13 shows the input and output voltage waveforms for the propagation delay and setup and hold measurements. Figure 14 shows the waveforms for the three-state outputs measurements.
V1H (2.4 V) - - 2.0V - - - - - - --~--~-·--
INPUT STROBE 0.8 V - - - - -
V1L (0.4 V)
INPUT DATA
SET·UP AND HOLD
,., ___ l________ . V1H (2.4 V) _____ ------..
INPUT
1 ~-0~~--- -~j r-t-H-t._1_,_
~ -1 IL·H
v0 12.ovi---- - - - - IN·PHASE OUTPUT
-1I ~ 1H·L
Vo(O.B V J - - - -
PROPAGATION DELAY
Figure 13 · 78008 Propagation Delay and Setup and Hold Voltage Waveforms
, . .:!B-~~""'fltt""IH:&M""""''""""".....,n""'""'.,.,..,Hil~--m-------------------·--··-------·--
3-25
-
78808
THREE-STATE OUTPUTS NOTES: 1. INTERNAL CONDmONS ARE SUCH THAT THE OUTPUT IS LOW EXCEPT WHEN DISABLED BY
THE OUTPUT CONTROL 2. INTERNAL CONDITIONS ARE SUCH THAT THE OUTPUT IS HIGH EXCEPT WHEN DISABLED BY
THE OUTPUT CONTROL. 3. REFER TO FIGURE 9. A z SI CLOSED, B · 52 CLOSED. C = S1 ANDS2 CLOSED.
Figure 14 · 78008 Three-state Output Voltage Waveforms
3-26
Confidential and Proprietary
·Featum
· Hardware rompatible with Digital's DLll sqies oflriterfates · Asyncly:o~ operation
· Internal baud rate generation &:oni 300 baud t'0 38Ak Paild' ·' · Four realtime clock interrupt outputs.
· One stop bit only · Common baud rate for both transmitter and recei\ler · Single 5-volt power supply · Single TTL dock
· Desciption
The DC319-AA is a Digital Link (DLll) compa:ti~le, asynchro11~mreceiver/transmitter (DLART) designed for data communication between Digfta}'s microproc¢Ssors and console terminals or communication devices. The DC319-AA,.faJ:>rii;a~ using N-channe~ MOS silicon technology, is
contained in a 40-pin dual-inline (QIP) ~~e. that can be W~vet'1etUIY installed on a micropro-
cessor module or interface moduler Figure l is a &lock diagralltbfth,e DC319-AA DLART.
DAL<15:0>
DATA
BUS
BUFFER
RCSR OR
FISUF
SHIFTAf:G (S .'..':,p)
_-.-1____ so
MAINTENANCE
REGISTER ACCESS CONTROL
1 - - - - - - + -.. RCV IRQ ,___ __,___ BAK IRO
~CSR
OR XBIJR
SHIFT REG (P-S)
1----~-s1
CLK
:. TRAkS'
! - - - - - ' - - - - - - - - - - MITTER 1 - - - - - - ~~IT
PBRI
CONTROL
BRS2 BRS1
BAUD
RATE CONTROL
! - - - - - - - - - - - - - - - - - - - - - - 76.BKHZ
1-----------------------SOOHZ
>---------------------60HZ
BRSO
1----------------------SOHZ
Figure 1 · DC319-AA DLART Block Diagram
DC319
The DLART is pro~mmed by the CPU too~ in either 8-bit or 16-bit mode with asynchronous baud rates Varying from 300 to 38.4k. The DLART accepts data characters from the CPlJ in
parallel format and converts them into an asynchronous serial-data stream for transmission. It can simultaneously receive serial-data streams and convert them into parallel data characters for the CPU. The DLART notifies the CPU when it is ready to accept new characters for transmission or when it has received a character from the serial line. The DLART contains an internal haudrate control to reduce support logic required to select baud rates. It also provides four realtime interrupt outputs. The CPU can read the complete status of the DL.t\RT at any time including the indication of data transmission errors and the status of control signals. Device address detection,
vector generation, and interrupt arbitration must he provided externally. The DLART provides
the DL-defined internal registers allowing it to operate with Digital software.
· Signal and Pin Descriptions
The input and output signals and the power and ground connections for the DC319-AA 40-pin
DIP are shown Figure 2 and defined in Table 1.
·
Ro Cs WtB
OALOO DAL01 OAL02 DAL03 DAL04 DAL05 DAL06 OAL07 OALOS DAL09 DAL10
DA11 DA12 DAL13 DAL 14 DAL15
Vss
TOP VIEW
Vee TEST
BRs2 8RSi
RTClK60 (60 Hz) RTCLK50 (50 Hz) RTCLK77 (76.8 KHz) BRK IRQ CLK BRSO
so (SERIAL DATA oun
XMIT IRQ PBRI SI (SERIAL DATA IN) RCV IRQ RTCLKSOO (800Hz) INIT A2 A1 AO
Figure 2 · DC319-AA Pin Assignments
:3-28
Confidential and Proprietary
...
Pin
1
iU.)
input
Read-When asserted while the CS signal is
assei;ted and the '\"iUi:Bsignal is unasserted, the content of the register selected by the A2, Al, and AO lines is transferred to the DAL.
2
CS
input
<'.;lljp~lect-When~sened whileAOu~serted,
. the SQPtents of the DAL< 15:00> lines are trans-
fe~ to the register selected the A2 and Al inputs.
3
~
input
19-4 DAL< l'l:OO > input/output
Write low byte-When asserted and the AO input is iinaSSerted, the data on the low byte DAL< 07:00 >
lines is written into the writable bits of the register
selected by the A2.~ Al lines.
O~ta address lineS ·'<: 15:00 >-Multiplexed bidi-
recticirial data lines.
21
AO
23 A2 22 Al
input inputs
Regist:er byte select-When asserted, the high byte of .the register selected by the A2 and A1 lines is
m,~tiplexed to the lowbyte DAL<07:00 > lines.
~ter address select-These inputs select the intertll,ll register that is accessible through the DAL
· lines when the CS line is asserted; A2 ,. . Al ilegister
0
0
RCSR
0
1
RBUF
1
0
XCSR
1
1
XBUF
24 INIT
input
It:dti.alize-This input is used to reset the RCV IE bit
in fhe RCSR register, and the XMIT IE, MAINT, and
'XMl't' BRK bits in the:XCSR register.:
25 RTCLK.800
output
~me clock interrupt (800 Hz)-This output pJ.'PVides an 800-Hz, 50% duty cycle signal.
26 RCVlRQ
·output
27 SI
input
Receiver interrupt request-This interrupt output is asserted when both the RCV DONE and RCV IE bits in.theRCSR are set..
Serlal input-This input accepts an asynchronous
bit serial data stream. The input signal must remain
in the high (marking) state for at least one-half bit time before a high-to-low (mark-to-space) transition
is recognized. A mark-to-space transition is required
to determine the beginrung of a start bit and to initiate data reception.
ConfidentW.and.Ptpp~
3-29
....
Pin Signal
28
PBRI
29
XMl:TIRQ
30 so
32
CLK
33
BRKIRQ
34
RTCLK77
35
RTCLK50
DCJ19
Input/Output!"
input output
output input output
output output
Definition/Function
Programmable baud rate inhibit-This input is
optionally held lowextermtlly by a jumper to ground
or held high internally. Holding this line low disables the software programmable baud rate selection (dears the PBR2-0 and PBRE bits) but makes the DLAR DL-software compatible.
Transmitter interrupt request-This interrupt request output is asserted only when both the XMIT RDY and XMIT IE bits in the XCSR are set. This
output can also be cleared externally by being forced low (clamped to ground) by an open-collector tran-
sistor for a minimum of 100 ns after being high for a minimum of 500 ns.
Serial output-This output provides an asynchronous. bit serial-data stream. This line remains high (marking) when no data is being transmitted. This
line will remain low when the XMIT BRK bit in the
XCSR is set.
Clock in-This input requires a 614.4-kHz, 0.1 %
square wave. All baud rates and clocks are derived
from this input.
Break detected interrupt request-This output is asserted when the RCV BRK bit is set and is unasserted by the TEST input or when the RBUF register
is read. This output can also be cleared externally by
being forced low (clamped to ground) by an opencollector transistor for a minimum of 100 ns after being high for a minimum of 500 ns.
Realtime clock interrupt (76.8 kHz)-This output provides a 76.8-kHz, 50% duty cycle signal. After being high for a minimum of 500 ns, this output can be cleared externally by being forced low (clamped to ground) with an open-collector transistor for a minimum of 100 ns.
Realtime clock interrupt (50 Hz)-This output provides a 50-Hz, 50% duty cycle signal. After being
high for a minimum of 500 ns, this output can be cleared externally by being forced low (clamped to ground) with an open-collector transistor for a minimum of 100 ns.
3-30
Confidentialand Proprietary
-
OC319
Pin Signal
Input/Output* Definition/Function
36
RTCLK60
output
38,37, BRS<2:0> 31
input
39
TEST
input
Realtime clock interrupt (60 Hz)-Thls output pro-
vides a 60-Hz, 50% duty cycle signal. After being high for minimum of 500 ns, this output can be cleared externally by being forced low (clamped to ~) w;ith an open-collector transistor for a minimilin of 100 ns.
Baud rate select-Th~ inputs.select the· receiver
and tl,'allSmittet l>aud rateswhen the PBRE bit is
cleaJ;ed as follows: The inputs are optionally asserted
l()W by' jumper io groillid or held high internally.
BRS Line
Baud rate
2
1
0
H
H
H
300
H
H
L
600
H
L
H
1,200
H
L
L
2,400
L
H
H
4,800
L
H
L
9,600
L
L
H
19,200
L
L
L
38,400
Test-This input is used during modnle assembly
and test to disable all DLART outputs. It is also used
in a system during powerup to reset all internal logic.
40 Vee
input
Voltage-Power supply voltage.
20
V55
input
*Input and output signals are TfL levels.
Ground reference
Confidential and Proprietary
3-31
DC.319
Read and Write Control Functions Table 2 lists the control signal levels and transitions required to select the read and write func-
tions of the DC319-AA.
Table 2 · DC.319-AA Read and Write Control Functions
Control Signals*
AO cs RD
Wi:B Function
L
L
L
H
Read-Register bits 15:00 to DAL< 15:00>
H
L
L
H
Read-Register bits 15:08 to DAL<07:00>
x
H
L
x
Read-no effect
x
x
L
L
Read-no effect
L
/\
x
L
Write-DAL< 15:00> to register bits 15:00
L
L
x
/\
Write-DAL< 07:00 > to register bits 07:00
x
H
x
/\
Write-no effect
L
x
x
/\
Write-no effect
*x=either high or low
A =low-to-high transition
· Register Assignments
The DLll-defined internal registers are described in the following paragraphs and are available to the user to program and monitor the operation of the DC319-AA.
Receiver Control and Status Regist.er
The receiver control and status register (RCSR) controls the operation of the receiver and indicates status. Figure 3 shows the format of register, and the register information is described in Table3.
3-32
Confidential and Proprietary
OCJ19
Figure 3 · DC319-AA 'Receiver Control and Status Register Format
Bir 15-12 11
10.08 07
06
05-00
Description
RAZ (Read as zero)
RCV ACT (Receiver active)-A read-Qnly bit set when .the receiver is active. This bit is set at the center of the start bit, which is the beginriliig ohhe input serial data and cleared
one bit at a time before the leading edge of RCV DONE or TEST. sign$.
RAZ (Read as zero)
RCV DONE (Receiver done)-A read-only bit set when an entire byte has been received and transferred to the RBUF register. This bit is cleared by reading the RBHF register or by the TEST signal.
RCV IE (Receiver Interrupt Enable)-A read/write bit set under program control. The RCV IRQ line follows the J{CV DONE bitand alJ.aws,an, ~t:erruptrequ.~t to be made when RCV DONE is set. This bit is cleared by :t;heINI'f sig~ .~by the TEST sigt;tal.
RAZ (Read as zero)
Receiver Buffer Register The receiver buffer (RBUF) register is a read-only register that stores the serial infotm.ation received from the device and indicates error status. Figtire4 Sho\:Vs the format <>f the information in the RBUF register and Table 4 contains a description of the register information.
15 14 13 12 ' 11 10 ' . .08' 07
00
A2 A1
0 1
Figure 4 · DcJ19-AA ReceitJer BufferRegjiter Format
Confidential and Proprietary
3-33
DC319
Bit 15 14
U
12 11
10:08 07:00
Table 4 · DC~19~AA Receiver Buffer Register Description
Description
ERR (Error)-A read-only bit set when the overrun or the framing-error bit is set. It is cleared by removing the error-producing condition.
OR ERR (Overrun error)-A read-only bit set when a received byte is transferred to the RBUF register before the RCV DONE bit is cleared. An overrun error indicates that reading of the previously received byte was not completed prior to receiving a new byte. This bit is updated when byte is transferred to the RBUF register and is cleared by the TEST signal.
FR ERR (Framing error)-A read-only bit set when a received byte without a valid stop bit is. transferred. to the RBUF register. This bit is cleared by the TEST signal or when a received byte with.a valid stop bit is transferred to the RBUF register.
RAZ-Read as zero.
RCV BRK (Received break)-A read-only bit set when the serial-in (SI) signal goes from a mark to a. space and stays in the space condition for 11 bit times after serial reception
starts. This bit is cleared when the SI signal returns to the mark condition or by the TEST
signal.
RAZ-Read as zero.
RCV DATA BUFFER (Received data buffer)-Read-only bits that store the most recent
byte received. When anew byte is transferred to the RCV DATA BUFFER, the RCV DONE
bit in the RCSR is set. These bits are cleared by the TEST signal.
'Ihmsmitter Control and Status Register The transmitter control and status register (XCSR) controls the operation of the transn;riHer in the DC319-AA. Figure 5 shows the format of the information in the register and Table 5 contains a description of the register information.
15
08 07 06 05 04 03
00
A2 Al XCSR --~-----u~-----'A~1~ xl~IT PBR2 PBRl 0
Figure J ·DCJ19-AA Transmitter Control and Status Register Format
5-34
Confidential and Proprietary
-
Table S · DC319-AA 'liansmitter Control and Status Registet DescriptiOO Bit l)eseription
15:08 RAZ (Read as zero)
07
XMIT RDY (Transmitter ready)-A read-only bit is set when the XBUF is ready to accept
a byte. This bit is cleared by writing to the XBUF and is set by TEST signal.
06 05:03
02 01 00
XMIT IE (Transmitter interrupt enable)-A read/write bit set under program control.
The XMIT IRQ tine fullows the XMi:T RDY. bit and allOWs an interriipt 1.reqµest to be
initiated when the XMIT RDY bit. is set. Thi.Shit is deaidby the lNIT and TEST signal.
the PBR2-PBRO(Progratnm4ble ~~d ~te ~).-J~~te~ transmitter baud rate sdected as follows: These bits are cleared by the TEST Ot- PfiRi· (programmable baud rate
inhibit) signal. These bits are read-only as zero when the PBiU input is asserted.
Bit
0.5 04 03 Baud rate
0 0 0
300
0 0 1
600
0 1 0 1,200
0 1 1 2,400
1 0 0 4,800
1 0 1 9,600
1 1 0 19,200
1 1 1 38,400
MAINT.(Majntenapceh-A read/write pit ~ed tof~tateamafutenapc!'! seJf-test. When
this bit .is set, the transmitter serial output,ill co~ to ijie ~il!F serial input. The
external serial input is disconnected. This bit is cle~ by the INIT or TEST signal.
PBRE (Programmable baud rate enable)-This bit selects the internal and external baud
rate. When set, the baud rate is determined by the PBR <:2:0 > bit in the registet. When
clear, the baud rate is determined by the BRS <2:0 > inputs. This bit is cleared by the
TEST or PBiU (programmable baud rate inhibit) signals. This bit is read-onlyas·2ero'\vhen
the Pm inpµt is asserte9. Otherwise it is reftd/!-Yrite.
·XMIT BRK (Transmit break)...._A read/write bit·Setwhen the.serial oi:itput (SO}line,is forced to a space condition. This0 bids dem:ed by the1tNIT.and TEST signals;,
Confidential and .Proprietary
3-35
-
DC319
Transmitter O.t.fl Bufi;er.~ster .·
. . .
. .
The transmitter data buffer (XBUF) register stores the data in the DC319-AA for serial transfer to
the device. Figure 6 shows the format of the information in the register and Table 6 contains a
description of the register information.
15
08 07
00
A2 A1 XBUF 1
Figure 6 · DC319-AA Transmitter Data Buffer Register Format
Bit 15-08 07-00
Table 6 · DC.319-AA Transmitter Buffer Register Description
Description
RAZ (Read as zero)
XMIT DATA BUFFER (Transmitter Data Buffer)-A read/write byte that stores a copy of
the most recent byte written into it. When a byte is written into this register, the XMIT RDY bit in the XCSR register is cleared. This byte is copied into the transmitter serialoutput register whenever the register is empty and the XMIT RDY bit is dear. The XMIT RDY bit is set when a byte is copied from the XBUF into the serial output register. This regiSter is cleared by the TEST signal.
· Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DC319-AA are described in the following paragraphs. The test conditions used for the electrical values listed
are as follows unless specified otherwise. Refer to Digital specification A-PS-2100002-GS for the general specifications for integrated circuits. · Operating temperature (TA): 0°C to 70°C
· Power supply voltage Neel: 5 V ±5%
Mechanical Configuration
The physical dimensions of the DC319-AA 40-pin DIP are contair1ed in Appendix E.
3-36
Confidential and Proprietary
-
00319
AStbrsoel~ustegMreaaxteitrntuhmanRtahteinagbssolute
maximum
ratings
may
cause
i
perman~nt
damage
to
the
device.
Exposure to the absolute maximum ratings for extended periods f11ay adversely affect the
reliability of the deV'ice. These ratings are for stress conditions only and do not imply that the
device will function properly at these ratings or ratings above those inditated.
· Power supply voltage (Vcc): -0.3 V to 7.0 V
· Ambient temperature under bias: 0°C to 70°C
· Voltage on any pin with respect to ground: -0.5 V to 7.0 V
· Storage temperature: -65°C to 150°C
· Relative humidity: 0 to 95% (noncondensing)
· Power dissipation: 1.0 W
Recotnmended Operating Conditions · Power supply voltage (Vcd: 5 V ±5% ·Ambient temperature (TA): 0°C to 70°C
de Electrical Characteristics The de electrical parameters of the DC319-AA for the operating voltage and temperature ranges specified are listed in Table 7. Refer to Appendix C for the test circuit configurations referenced in the table. All input and output signals are TTL levels.
Parameter
Low-level input voltage
High-level input voltage
Low-level output voltage
High-level output voltage voltage
Output float leakage current
Table 7 · DC319·AA de Ibpdt'4nd 0utput Characteristics
S:ymbol Test Condlnons l\equh-emen:ts Uni:ts Mm: ·Max.
VIL
-0.5
0.8 v
Vm
2.0
Ver.: v
VoL
lc1..=2.2mA
0.4 v
VoH IcL =-4-00 µA
2A
v
IoPL
V..,=Vccto0.4V
10 µA
Test Circuit
Cl,C2
C1,c2
C2
Cl
Confidential '1ld Proprietary
3-37
·------·------
-
Parameter
Input leakage current
Power supply current
Standard V1aoutput
current
DALVm output current
Standard Va output
current
DAL VIL output current
DC.319
Symbol Test Conditions
I1L
V1n== Vee to 0.4 V
Requirements
Min.. Max.
10
. Units µA
Test Circuit
C5
lee
All outputs= high
100 mA
C7
Ion
V..,= Vee to 0.4 V -40
µA
Cl
Ion
V...,=Vccto0.4V -700
µA
Cl
V..,= Vee to 0.4 V
1.6
mA
C2
IoL
V.... =Vcc to0.4 V
3.2
mA
C2
ac Electrical Characteristics The switching characteristics of the output signals are listed in Table 8. Refer to the input and output waveforms in Appendix D for the symbols referenced in the table. The signal timing for a read and write data and control cycle is shown in Figure 7. Thble 9 defines the timing parameters listed in Figure 7 for the operating temperature and voltage ratings specified.
Table 8 · DC319-AA Signal Switching Characteristics
Symbol
Description
Signal
Requirements (ns)
Min.
Max.
t./tp
Rise time/Fall time* Interrupt request outputs (IRQ)
250
Serial-data outputs (SI)
150
Baud-rate clock (BRCLK)
150
*Each DAL line drives 200 pF load. All other outputs drive 1 TTL unit load and 50 pF load. Timing measurements are made at 2.0 V on a low-to-high transition and at 0.8 V at a high-to-low transition.
3-38
Confidential and Proprietary
ADRS
CTRL
VALID ADDRESS
50
tAS ns min
i - - - - -tP-W-10-0-NS-M-IN- - - + t
tAH
0 ns min
READ
tTR .\5.0ns max
, ·:,. :10 Bs.min
__............. __ DATA---------------
VALIDOATA'
·..;,...,.,._.......,._.
._,....__..
.._ ,___...,..._,.
WRITE
·~ .:-) 100tnOss min
tc;vc40Q ns. min
T'une Description'
R:e:qUitementS (n8)
Min. Max.
!:eve Cycle time
400
trw Controlling pulse width
100
t.r.s
Address setup time
50
t.r.H
Address hold time
0
t.r.c
Access time
0
250
~
Three-state time2
10
50
tns
Data setup time
100
fnH Data hold time
0
1Read control: ~and RD signal asserted and WLB signal unasserted.
Write control: ~and WI:B signal asserted and AO unasserted. 2tra (off) is measured with DAL drive= 100 µA.
Confiilential and Proprietary
3-39
··
oc;19
Application Information Figure 8 is an exrunple of an interface using two DC319-AA serial-line units (SLUs). The SLUl
DLARTcommunicates with a console terminal through connector Jl. The SLU2 DLART interfaces
with a communication line through connectorJ2.
The SLUs transmit or receive 8-bit, byte-oriented data with no parity, one start bit, and one stop bit. SLUl provides the XDLl and RDLl interrupts for the transmit and receive data and the BREAK output. The BREAK output at M14 can be connected to M13 by a jumper lead to generate the HALT interrupt when SLUl is used with a system console. SLU2 provides the XDL2 and RDL2
signal interrupts for transmit and receive data, and three realtime clock interrupts at 50, 60, and
800 Hz. These interrupts are wired to pins M18, M19, and M20 respectively and can be connected by a jumper leadto pin 17 to generate the TEVNT interrupt.
When the serial-line units are addressed, the CSDLO line is asserted to select SLUl and the CSDLl
line is asserted to select SLU 2. These inputs connect to the CS inputs of each SLU. Address bits
AD2 and AD 1 are used to select an individual register within the DLART. The READ line connects
to the RD input and when it is asserted, the contents of the register selected will be transferred to
the TDAL bus, provided that the WLB input is not asserted. When the WLB input is asserted, the
low byte of TDAL bus will be written into the register selected. Only the register bits designated as read/write will be written. The DLCLK input is a crystal-controlled dock reference used by the SLU to generate baud rates and realtime dock outputs. If the BCLR input is asserted during a RESET
instruction, the RCV IE bit of the RCSR register and the XMIT IE, MAINT, andXMIT BRK bits of the XCSR register are reset. When the DC LO input is asserted during powerup, all SLU outputs will be disabled and the internal logic and registers will be reset. The baud rate is set at 300 after the SW is initialized by DC LO signal.
The RS232 and RS423 EIA standard signal levels for the interface connector are provided by E30 and E3 7 dual-line drivers and dual-line receivers. The slew rate for both ch.annels is controlled by resistor R6. The factory configuration uses a 22-ko resistor to provide a 2-µs slew rate for operating at a 38.4k baud rate.
3-40
Confidential and Proprietary
CSOLO
DC LO BCLR AD2 A01 WLB READ DLCLK
CSDL1
DLCLK
+5 voe
E44
DC319
BREAK OUT
J1
M14 M13 O--THALT +12F 10
BRCLK
1
SLU1 DLA RT
E65
3
ACVIRQ
7
8
RS
-12V
2
4
6
9
-=
0Al<15:00>
J2
BRCLK
SLU2 DLART
E66
RDL2 XOL2
+12F 10
3 7
M18
8
50HZ
R7
M19M17
60HZ
0--TEVNT -12V
2
M20
4
800HZ
5
9
-=
04
03
05 4.3V
-=
Figure 8 · Dual DC319-AA Serial-line Unit Configuration
Confidential and Proprietary
3-41
· Section 4-Bus Support Devices
The bus support devices are available for Q-bus, UNIBUS, and V~BI bu~ interface development:
VAXBI Bus Interfitces
.
. .. .. . . .
. .
The VAX bus interconnect (VAX.BI) is low-cost,high"bandwidth,.,j2-bitsyn~JlOUS bus,~ to
connect VAX processors to memories, I/O controllers, I/O bus adlap~rs, ~~ VJ\X1pt:P«ssors.
It provides a large addressing range and high data integrity and allows a. ihlgle V~ prpc~wr :to
communicate with up to 16 nodes on the VAX.BI bus.
VAXBI 78732 Bus Interconnect Interfiu:e;-the .nIIC is a 1M~pli\ 'Z:¥-Olki#p ~t serves< ~s the
primary interface between the VAXBI bus and a master or slave port:interface. ,.,._,·,·--:,,· .....·. : ,.,,. VAXBI 78743 BC! Adapter Inteeface-The BCAI is a 133-pin ZMQ§ chip: that functiori$ as 'fl buffer
file between user-designed processors, memories, and adapter niQd,,ules and the VAXJU bus.
VAXBI 78733 BCiwMicroVAX II Bus Inteeface-TheBCI.3ifa;Q~~ffenpackage'usedtoc0tmeclthe
integrated circuit interconnect bus of the MicroVAX processor ti:>·ffie VMmI bnstbmilgHtheVAXBI
7~32BllC.
-
- ..
. ..
VAXBI 78701 Clock Driver and VAXBI 78702 Clock Receiver-J'heqlodq;hiveriS a14.opmbipolar DIP that serves as the clock source for the VAXBI bus system. ·'outpUtofthe¢l&:kdJ:iivtrds received by the 16-pin bipolar clock receiver to generate the tim.tng signals1\JSedcby the VADJ,bus
system.
Q-bus Circuits and Kits
·.· ··... · . ..
.. .· , . .. ·.. ·. .· .
me Digital provides a series of integrated circuits (ICs) and kits useµJt1the ~PP!J).tint qfdevice
interfaces for the Q-bus. The Q-bus is the LSI-11 processor bus. JCs~avail~l~,;iemu:a~ypr
as part of the DCKll series of chipkits. The chipkits contain a~ of ~bi~*~'~ gC>u})l~·~eiMt wiJ:e·
wrappable module {W9512), and connecting cables that ~be.~to/d~~ ijn4.iin~c~ most
· · · ·.·., Q-bus interfaces. The chipkits minimize the number ofcfup~l:/:~~~ary tp di;yel~i1-5~~m.p~gram
control or direct memory access (DMA) interfac5s:,.il'.he wi~i~
¥!~P~vi# .a(tdit.ipllal
to and space for mounting the special interface logic req~. ,1'efel'.JQ
number EK-01387) for detailed information related DCKU setteso
' .Q'ser.s c .ipklts
~ttf~u/r.a(dppolciucm~teinont
information. The specifications for the following Q-bus interface chips are contained in this
reference ~ide.
DC003 Duat~inierrupt Logic-The bc003 ls an ~8~pffiDIPbi~r~evite ~at is ~setf ttrperform an
interrupt transaction in a computer system that uses a daisYcllhln type bf ai'bitraHi:ui '
DC004 RegisterSelectofLogic_;The DC()04 is af<l·pin DIP bip0l~d1~vfoe that bperates'as a·rqµster
from selector to control the transfer of data to and up to four \Vdrd registtcr~. '· '··
·
as DC005 4-Bit Transceiver~The DC005 is a20-pin DIP bipolar device that is used in interfaces' a
bidirectional buffer between the Q-bus and device dam bus.
DC006 Word Count/Bus Address Logic-The DC006 is a 20-pin DIP bipolar device that is used to control direct memory access (DMA) data transfers.
DC010 Direct Memory Access Logic-The DCOlO is a 20-pin DIP bipolar device that provides the logic to perform the protocol operations required to request and gain control of the Q-bus.
Chipkit Description-The following LSI-11 chipkits are available and contain the components listed.
· DCKll-AA Program Control Bus InterfaceChipkit 1 DC003 Dual-interrupt Logic 1 DC004 Register Selector Logic 4 DC005 4-bit Transceiver Logic
· DCKll"AB Designer's Program Control Bus Interface Chipkit 1 DC003 Dual-interrupt Logic 1 DC004 Register Selector Logic 4 DC005 4"bit Transceiver Logic 1 W95U Double-height, wire-wrappable module 1 BC07-D lO~foot, 40-conductot; plug-in cable
· DCKll-AC DMA Bus Interface Chipkit
l DC003 Dual-interrupt Logic 1 DC004 Register Selector Logic
4 DC005 4-bit Transceiver Logic 2 DC006 Word count/Bus Address Logic 1 DCOlO Direct Memory Access Logic · DCKll-AD Designer's DMA Bus Interface Chipkit 1 DC003 Dual-interrupt Logic 1 DC004 Register Selector Logic
4 DC005 4-bit Transci:iV'er Logic
2 DC006 Word Count/Bus Address Logic
1DCOlO Direct Memory Access Logic
1W95U Double"height, wire-wrappable module
1BC07-D10-foot, 40-conductor, plug-in cable
UNIBUS Devices
The UNIBUS is an asynchronous bus used with the PDP-11 and VAX processors. The UNIBUS devices facilitate the development of the bus interfaces. DC013 UNIBUS Request Logic-The DC013 is a 16-pin DIP device that contains the logic required to perform bus requests and to gain control of the UNIBUS. DC021 .Octal Bus Transceiver-The DC021 is a 20-pin DIP device that contains eight bus transceivers used to transfer information be,tween the UNIBUS and a user-developed interface.
Confidential and Proprietary
· Enables low interface cost · High-level integration reduces module atea required
· Complete VAXBI arbitration, address decoding and matching logic ·to reduce hardware and software protocol
-~tion
iTnhteegrVaAteXdB<I;ir7c8u7it.3.2andbusser- ves as~ the priimntaettyfacue m~hi~p (!~UI·(;)tish·e~V~AX·BIo.Mn baµsl,3~ ;3-pintheZMusOerS-
developed ~ o! a node·.~ Sll<:: isr~~.pqrpqse ~~e for P~SS(}t'S, me~ties,
and.adapters that opera~ with.the.YAXBlhut.Itpi:do~.bQt~r·1.~-®1,1S:~~ ~and
match.iqJ, and contrpls the user's interface signals..Figure 1 is a functional block d,iagra;n pf the
VAXBI 787):2 interface.
.. . . . ..
CONTROL SEQUENCE
I I < ioqu... ~Fibfrt··
~~.·:·····~··..······.·······.···~·····..'
PH4
. .
.
Figure 1 · VAXBI 78732 Bus Interconnect Interface Block Diagram
4-1
> ;";->~-- -~--;·-:; ,1,·, { 'f,
-,- / " ' '
. "'\'·
~~r~~,··
'·,'l-
The \TAXJ3I bus i$··.·~ '2"pit, gen~ ~ ~~~~~s·bus,~hat 1can effectively ~'~ ~th single-processor or multiprocessor systems that are'based on the VAX processor$ or other 32-bit
processors or compatible devices. The VAXBI bus can have a maximum length of 1.5 meters and
can connect with as many as 16 intelligent nodes contained on a maximum of 36 modules. The
aggregate throughput rate ofthe nodes is 13.3 Mbytes per second.
·
· Pin and Signal Description
The VAXBI 78732 is a 133-pin interface that functions with tlleioput and output signals de$1;tibed in the following paragraphs. Figure 2 shows the connection pins and signals of the.VAXBI Bus interface chip. The BIIC interface contains two grouini ·of signals. The Blsigrialssonne~ tQ the. VAXBI bus and are shown in shaded blocks. The remaining blocks are BCI signalphis that connect to the user's interface and to power and miscellaneous signal lines.
14
13
12
11
10
9
7
6
4
3
2
p
N PO
102
000
ACLO 101
002 003
103
001
006 007 005 008
010 011 009 012
014 01s 015 D11l
019 020 .vea P
.
022
o25 N
M NXT CLE 100
+5V GND 004 GNri Giiio . 013 017 0:!1 023 024 026 M
L
EV01 RAK GND
K EV03 EVOO GND
DCLO EV04 EV02
+5V 027 029 L GNO 028 031 K
GNO ,030 scoo J
H
G
F
E
0
c
B
A
Figure 2 · VAXBI 78732 Pin Assignments
4-2
Confidential and Propri~tary
·-; ..
~···
VAXBI Bus Line Functions Table l lists the sig~al aQd functions of the VAXBI bus lines,· power connections and ground lines
that connect t0 the Bll(:. Each signalline includes a pullup resist.or circuitand allBldciver lines are
open-collectofootputs: The BI bus signals are grouped by the ~tions shown in Figure 3. All
signal lines are synchronous except for the asynchronous control signals.
A02-Al0 B01-B09 C01,C02 C05,C06 E01-E03 F01,F02 G01,G02
BI D<Jl:OO'.> input/output1 Bi' Dat:a-.:Use(i'fu 1~fer data and address
information .and to perform arbitration.
BlO,Bll C09
BII<3:0>
input/output' BI Identification-'-Used to transfer com-
. ri:J.atK!s;:>entodedftnaster identification, read
status codes, attd write masks.
All
input/output· Bl Parity odd-Used to transfer odd parity for
the 1Uo<31:00> and Bl~.~Jij1~.,~.~ i'1t ii·~.w:hen i:m ~·.Qum~r l:lf bits
on the liitw;i1ias~·.
en
input/8ut:pittn ··' m·M<:1·~tij''1iii~~:il>'ihhib:it·.ai'J:t1~
tration onitli''i1<D1<r3!t!iO(j''> linesi It .·is~
asse.ttc~h.d~·~f~U.C;··~~·····;Q:·P~nt
,othet~~~titli~~·untilaU
···~att~Y~P~~te.
A14
A13,Bl2 Cll P14
Hl3
input/output' BI Busy-Asserted to indicate that a transaction is in progress.
BI CNf <l.1Qr,;?. ·iupu,~QIJ~~t\· ·~. ji:Q~T~ii.oµ;,:.u~,to trarufor responses
, , .·.
~. ~~:rntmtndan:ddata cycles;
BI ACID
BI DC LO
input2 input2
BI ac Iow.......Used;lW.ith the'. Bi DC tD line tQ
perform po\Ver~~quettces,
,,
- ,'"<'i.·
<·
·BI ac li;>w...;.ctJse&witll t~.flt nC'tb line to
perfo~~sCquences,'
·
10pen drain· 20peneollector
-----··-··~----~·--------------~~---"·-·---~g-~-----~~·~----~--------~-----~-------··-"--=~
DATA PATH SIGNALS
810<31:00>
[2] EJ
~ 11116
$YNCl:IRONOUS COf\ITR!)L SIGNALS
El
81 N6AA8
Bl CNF<2:6S
ASYNCHRONOUS CONTROL SIGNALS
Figure J ·· VAXBI 78732 BI Line Functions
Bl Data-path Signals The BI data-path signals are grouped into the following categories. All data, arbitration, commands, and address information is transferred through these lines. BI Data and Address (BID <li:OO> )-These lines transfer data and address information and are
used during the arbitration sequeqc~.
BI Identi6cation (BI I< 3:0>)-These lines transfer commands, encoded master identification, read status codes, and write masks. Commands can be directed to one or more nodes depending on the type of command. The command codes and types are listed in Table 2.
BI I Line
3
2
H
H
H
H
H
H
H
H
H
L
H· L
H
L
H
L
4-4
Confidential and Proprietary
Bll:tine
3
2
1
0
L
H
H
H
MR
INTR/Iritertupt
L
H
H
L
SR
IDENT/ld¢ntify
L
H
L
H
L
H
L
L
L
L
H H MR
Stop
L
L
H
L
MR
INVAL/!nvalidate ·
L
'L
L
H
MR.
L
L
L
L
*SR is·a single responder, MR is more than one resp0iiClet · .
Bl. Parity ·~>-~cate!i the parity of thCBI b< 31:00.:>fand. fir t<:ftl·> 'Jfue$. ··cRef~··tQ
Plirity Checkitig and 'Generatiprr.)
· · ·"
· ·· '· ·· ·· · ·
BI Syn.dmM:tous ConttolSipals The BI synchronous control lines provide coritrol :fuhi.±ions and r¢$p()ttse!to·cktfaand command
cycles.
BI No ArbitnttfatiOIJ <m N9Mm"r'~'~~FP9*~ ~·· ~:,!<>.dieY~I data lines for
arbitration. The nodes·momtorthi$signal$0tMt the data~ ~m:l/addtess·inforrmatioi;idoes not contend with the arbitration information. I£ theM~~ is ~serted ~ ~VAXBI cycl~. thenodesarepreven~!romarbitratine<l~t.11e ~\T~Icycle~Thiss~is asi;ertedby
· Nocles arbitrating for the bus~ the ~~op~e~
'
---.-~,..--~.,.---~~.._,..
· The pending bus master from die cycle af~Jt \Vins the ai-1.>it~tion until it becomeil hus mastet
· The bus master during the fo1lowma:
-Embedded ARB cycle of longwrud transaction -EmbeddedARB cycle and the following cycle ofa quad~transa~n -E~ded .ARB cycle through the cycle after the''~® ACK data cycle of an octawotd
transaction
· The slave for all data cycles except for the last cycle. ~ All potential slaves for the third cycle (decoded masterm):and for theIOENT arbitration of the
IDENT co:mtlland.
· Nodes performing loopback transactions.
· The bus master during its command/address cycle to prevent bus arbitration from occurring. This allows the bus master to start a bus transaction following the current bus transaction. (This mode is reserved for use by Digital.)
· Nodes performing self-test operations until the VAXBI registers can be accessed.
4-5
BI Busy (BI BSY)-This sig~. p~0des thc;,oi;derly transition of bus mastership from one node to .
another node. The nodes monitor this signal to determine the action to be performed dtlring the following cycle. The deasserted state of the BI BSY signal indicates that the current transaction has been completed. The node that. won the last arbitration may become bus master in the cycle following the cycle in which the deasserted state of the signal was detected. The signal is asserted by
· The bus master during the following cycl~s of its transaction -Command/address and embedded ARB cycle of a longword transaction -Command/address, embedded ARB, and the following cycle of a quadword transaction -Command/address, embedded ARB through the cycle following the second ACK data. cycle
of an octaword transaction
· A node to delay the start of. the next· bus transaction until it can respond to another bus
transaction. The maximum stall time by a node should not exceed 16 consecutive cycles 1111d is limited by a timeout circuit to 127 consecutive cycles.
· The slaves for all except the last data cycle. · Nodes performing loopback transactions.
BI ~tion (BI CNF< 2:0 >-)-These lines provide handshake functions bet-ween mas.ter~d·
slave nodes to reflect detected errors and to indicate the current state of the slave. Table 3 llSts the
response codes and information. During a transaction, the node must first respond to the
command. For read-type, write-type, and IDENT commands, the slav~ must respond during each
data cycle following the command confirmation cycle.
· ·
.
Table 3 · VAXBI 78732 BIConfilrnation Line Code Assignments
BI CNF Line
Description
2
1
0
,,:_:;,.,--,
H
H
H
no ~cknov.~ledge
H
H
L
illegal
H
L
H
illegal
H
L
L
acknowledge
L
H
H
illegal
L
H
L
stall
L
L
H
retry
L
L
L
illegal
Confidential and Proprietary
PTohwe BelI'AQ<m:: LtrOolaSnidgnBaIlsOC
.
LO
.s.ig.tl.al.o. r.e
used
. .
tO
co.·.l.;l·t.i:ol.the
. . ..·. ·.
powetl,lp
.~t.:*< >, ~wn
sequences
of
the nodes on the bus. These signalsenable the VAXBl ta stonnu1d retrieve tVe·~s requimdr
in the ~nt of a po\li¢rfailure or interruption. The.Ill Ac lb is asset;ted w"hdl *e line voltage is
an below the lninimum te;vttl '114,t~ 13,I~~C>rsignal is assertedto indicate 1inpendingloss 0£~. ~c
power and is also used for initlalizatiOn<turhlg the powerup sequence.
·
· BCI Line Functions
The BCI bus consists of 64 Jines used to trall8£er data, address· status, and control infoiJniltiOfi·
be~.theBJIC an,q;the·u~ill:~~t;e;'l)ble 4~~·~-~ful!'\ctiouO,fmeBCllines. Th;C.
BCI'ljnes aJ'C ~ped;l;iy Jh~ tu~~s ~~in Figure 4. . .
L.[Z] '-------.------.1M:-,-.IX3\-3'"·2.'. ".'.".··:· o-c!>------.-.-.,,-r,....__<..,.....,.....' ··1¢is.K3:0>
~..SIANALS TOe11c···.
0 El·
sa R0<1 :O> sm f.tAii
FROM BllC
El
Ht ·RAK
El
fC1 NXT
EJ
iilifiii·
SLAVEmNALS TOBllC
FROMJIHC
TOBllC 8.CI. INT;<7:4>
l·.·.s .r
F ROM'811C BCI ACLO
rLni ·
BCI DCLO
EL
BCITIMl:L
eci PHASE L
Figu~4 · VAXBI 78732 BCI Line Functir.ms
-·
Sipa1
Input/Outpnt1
]02 K01,K02 L01,L02 M01-M06 N01,N03-N10 P03-P12
BCI D < 31:00 >
input/outp?t
M12 Nll,Nl2 PU
BCII<J:O> input/output
N14
BCIPO
input/output
Dl4,Fll
BClRQ< 1:0> 2 input
FU
BCIMAB2
input
L13
BCI RAC< 1:0 > output
M14
BCINXT
output
G14
BCIMDE
output:
C14,E14
BCI RS< 1:0 > 2 input
MU
BCICLE
output
Definition/Functicm ··
BCI ':Data-Used to transfer data and address information.
BCI Information-Used to transfer come mands,tead status codes, and write masks.
BCI Parity-Used to transfer <Xldparity for
the BCI D < 31:00 > and BCII < 3:0 > lines. This line is asserted when an even number of
bits on the lines is asserted.
BCJ Request-Used by the master-port interface to instruct the BIIC to perform a specified transaction.
BCI Master abort-Used by the master-port interface to instruct the BIIC to abort the current master-port transaction.
BCI Reqqest acknowledged-Used by the BIIC to indicate that a transaction requested by the master-port interface has been initiated.
BCI Next-Used by BIIC during write trans-
to' actions request the next data word from
the master-port interface and during read transad:iorts to indicate to the master·f)Ott interface that the data on the BCI bus is valid.
BCI Master data enable-Informs the master-port interface to transfer the information to the .BI bu~.
BClResponse-Used by the slave-port interface to specify the code that will be transferred by the BIIC on theVM\:Blbus. BCI Cycleenable-Indicates the presence of a command or address cycle to the sl~ve-port interface.
4~8
Confidential and ProprietlU'y
-' s¥ial.
H14
output
H03
BCISEL
output
H01,H02, sdsc<2:o:> output
JOl
BCI Sl!Wtt···;em.blC--:.Indi~,tG .·the·.,
slave-port interface that the htformation w
be transferred on the VAXBI ·bqs should be
transferred. to th~Btl.data Jines.
BCI . Se~~~Wken assert¢d, the BCI'
sc <2:o;:J·~sc;~lect a slave-~rt interface
for a VAXB'J:~~on.
.
BCI Sl~·~~ntrol--Sel~t~ a ·.sla~e-port
interface when the l'ici sEL line is asserted.
E14,Fl4 Gl2,GU
nd11il~f!i~1~fequ~s~tt~~
the~'siii:Werfaee'''1\Jro ~widldre\ kt
ns<~r;~'littei·'tlf·~~ions ··.during the diagnost.k mode.
J12JB
K13,K14 L14
NU
BCIEV<4:0>. OUtpl,lt .. BCIACID.
~I.g'J,f:Ut~Jtllii~t~~ tb~. CICCt¥~CC! (){ sig-
t}ihlficant '~ ~,~the BtIC or on the
VAfCJ,i:l.Ju§; Not~d dutidg the:~:;~c
mod~:'·
..
..
" ' '·
·,:·;.
BCI.aclowZiridicates .tne . statusof .·the ac
powel1,t() the us,er's intet#ce..
J14
BCI d6low-Indicates ~he status·'Of the de
po~ito~:~'si!l,~~C,·
B14
BCI TIME L input·
BCI fitne--A ~-MHz 1"L ~·from the
VAXB, Cloczk reCeiver in tbe user'~ interlace.
Usedmthtbe~9IPHA$~Lline t;;y the BII<'.:
~,ncl 1.l~'s ~~dace to geilerab! ~ :req~
t~~ign~.
D13
BCI PHASE L input
BCI Phase--A' r·Mifz TTL si~nai, from the
VAXBI clock~eiver in'.tb.e user'sJntetface.
Used Wi~hthe l3CtnME:L line by:the :SUC
and ~r's 'interface to generate the required
ti.rn.Uij \signals. i
are IAll User IDtettaCe ~ig~ rrtltwelS ; · · ·
>
~ '
. ·
2These signals must be connect'bato a.hi.ibJ~ when notus,ed .in the Dooe deS:lgn.
BO Data 1'.thSignals
The BCI data path consists of bidirectional three-state data, information, and parity lines. The direction of transfer is controlled by the 13CI Mf.5E and BC:i SDE signals.
BCI Data and Adchess (BCID < 31:00 >)-These lines provide a 32-bit path between the BIIC and
user's interface to transfer data and address information. During command/address cycles, the
BCI D < 31:30 > lines contain the data length code and lines BCI D < 29:00 > provide the address.
Table 5. lists the data length code assignments.
BCID·~
31
30
L.
L
L
H
H
L
H
H
Da1'1 Length .
reserved longword quadwon:l octaword
BCI hlformation (BCI I< 3:0 >.),...,..These lines are used to transfer commands, encoded master ID,
read status, and write masks. Table 6. lists the BCI command code assignments, Table 7 lists the
read~status code assignments, and Table 8 lists the write-mask code assignments.
'Iit.ble 6 · VAXBI 78732 BCI Command Code Assignments
BCl'.I tilles'
'Type1
Command Description
3
2
1
0
L
L
L
L
L
L
L
H
SR
L
L
H
L
SR
L
L
H
H
SR
READ IRCI RCI
reserved read interlocked read with cache intent read with cache intent
L
H
L
L
SR
L
H
L
H
SR
L
H
H
L
SR
L
H
H
H
SR
WRITE WCI UWMCI WMCI
write write with cache intent unlock write mask with cache intent write mask with cache intent
H
L
L
L
MR
H
L
L
H
SR
H
L
H
L
H
L
H
H
INTR ID ENT
interrupt identify reserved reserved
H
H
L
L
MR
H
H
L
H
MR
H
H
H
H
MR
H
H
H
H
MR
S1DP INVAL BDCST IPINTR
stop invalidate broadcast' interprocessor interrupt
1SR =single respondet; MR= multiresponder. 2Refer to Broadcast Transactions (Appendix A) of the VAXBI System Reference Manual.
4-10
Confidential and Prot)rietary
BcIILines
3
2
1
0
L
*
L
L
reserved
L
*
L
H
readdaur
L
*
ff.
L
·ronectedteaddata
L
"
H
H
· ~ddata:sUbstiture
H H
. *
H
fl
. *
L
L
reserved
·
L
H
read daqi/do not cache
H
L
cor:rected ~datafdo not cache
J3 .
H ..... ~.~~9'b~~/dq,~cache
*Line < 2 > is reserved. The Slave must deas~rt (L) this litit:\J~i.~s.~s tYpes ~the tna!~s
must ignore the state of this line.
·
BCIILine asserted
Bel DcJ..iBe
Write Byte
<21:24>
<:23:1~>
<15:08> <0.7:00>
.. . ·. . , ..
BCI ·Parity (BCFPO)-Thh line ··.eoritiilil$·tht'J Piirity ~cdpr for·itbe .BGf·J<:3!0> and
BCI D< 31:00 > line signals. The parit)>sen8¢'iso&:tThel-tf~'tiCl'PEf'·lme~~ail~
during· user's interEate·genet'lated parity .mo~ wh,en·an ~··l'lilJtllber of OOlP<.311:00> arid
BCI I<J:O.> linesare ~.'
fiCl p The iotate.of tbr. sq
powerup when the
t>Q
tin~:
fSt
is,Os)ingfnl,all,i)s~dabssfe.t~t~e.duf~~eerB'lslJC~]!o/~..~11.·~tih~~~'~~.~',A~l,t~·µ~ps:~l,)wju~ r~~e
parity mode: Ifthi:U:ser's interface asserts t:Ke BCfPOlin~of'4eviS'ft·~~~.iJ~lfl~by
default when the BCIDC @ line is a,sserte<J~. ~h~ Btrc Will"~{~~.·~ ~aeJ:ilitl~the ~ty
when.the·B'Cl data is tobe~ransmit~91l,thi:: y~tµ: buS;.c~~g~fi~,~~Jh,if,~Jl\:·~~'1t~
patjty 11¥1de app aIon&~ s~i:µp time~ required~i;~~ ~P~'~;·PJ.l> ~~l"2 ~~Q > ~.to
allow ~.BIIC to generatet~pa~itr' 1f~.user'$i~~~~~~tco~~.Ja~,l ~ Mf:?.~~
POWl:J;Up, the BIIC,will g~Detate parity.by default. lt,l B,If~1~~d ~ty mode, the :BClRt'l·line
does not have to connect ro t:he BIIC.
Iftpeu~'sinterfacedeas~~e<lthe'BCIPO~.'Yhr.i#tbe»(:Hlclbllheis~!ed~theBIICwfil
be C:Opfigured ~or user~s ili~rfa(:e-ge~~a~ t'~it)'..'The u~er.'& iht~rfa~.tID;stp~ide the'proper
t¥· 3:97 parify on the BCI pij'Jine,w~·the Jmc s:>licits dat~.·.(I3C!~ o~ ~r.s.n~1~ as$erre<i.) Iii this
mode, a shorter set11ptimek permit~ed on BC!l) ~ 'rl:oo.~ ~d BClJ ~ ~s·for the data
to be trailsinitted oh the VAXBt bus. Ifthe us'er's lnt'exface geri~~iricomct parlt)'i the parley will
be transmitted on the bus, and a bus error will result.
4-11
When data received from tk~ ~I b¥,s .i~J~sf~t:hrough, the]3IlC ~~e BCI lines, the BC!
PO line reflects.the received.state of the Bl'POline. During loopbacktransactfon cycles, the parity
generated by the user's interface or b}l' the·I3IIC is transferred to the BCI.
BCI Master Signals The BCI master signals are used to request, execute, and ter~ate transactions. BCI Request (BCI RQ < 1:0 >)-These lines are used by the master-port interface to request that the BIIC perform a transaction, The lines ate also used to select the BIIC diagnostic mode. Table 9 lists the BCI request codes assigoments.
BCIRQLine
1
0
H
H
H
L
L
H
L
L
Table 9 · VAXBI 78732 BCI Request Code Assignments Description
no request VAXBI transaction request loopback.requ~t diagnostic mode
BCI Master Abort (BCI MAB)-This signal is asserted by the master-port interface to indicate to
is the BIIC that the present master-port transaction from this node to be aborted. It is also used to
clear the retry state of the BIIC entered after a retry confirmation is received. The assertion of the
BCI MAB signal does not affect BIIC-generated transactions.
The user's interface usually cannot abort a requested transaction without generating bus errors that
will be detected by other nodes. The BCI MAB line therefore Should be used to abort a transaction
request only following an error coJ;ldition. A pipeline-request master should abort a tran,saction
request only for the transactiqn subsequent to one that fails.
The user1s interface Should deassert the request lines in the same cycle that BCI MAB is asserted. The actions performed by the BIIC depend on when the BC! MAB signalis asserted as follows:
· If the BCI MAB signal is asserted before the BIIC arbitration cycle, no. transact'ion is iriitiated.
· If the BIIC has won.the arbitration cycle and has not transmitted the command/address, it will. deassert the BI NO ARB line in ~e next cycle.
· Ifthe BCI MAB signhl is asserted after a retry cOnfirmatfon or timeout event code isrecei\fed
(RCR or RTO)'. the.BIIC. aborts its retry ·.state so .that it can· accept a new request... The user's in~1;1Ce can abtlrdhe tetry state only by 'asserting the '.i3Ci MAB signal. Follawing the assertion
· of'BCI MAB, the user's iriterface should nm assert a new request for a minimum of three cycles.
froll1 · .~n a node that .'110\\TS pipeline regues~s. the ~sertion of the.BCI MAB signal may 9ccur during a
transaction
this riOde. If the BCI M;XB signal is asserted during a trans!lction,. tht; BIIC
the caborts the tnm~action. 'J'he user~s ktte~f.97e ~~y not receive !ill event code fpr a traQsactioti th.at js
~~rted.. A.minimum oft~ <;rc;ft;s ~p1lo~~ thea~~rtion of BCI Miil3111u.~t .be all9-.vedJ'Y
,,user's interyl!-ce ~f()re a lle\l{ requcrst is gene~ted. Th# use of this m.ode shoulg be aypi~d....
4cl2
Confideritial and .Proprietary
-·.,
BCi Request ~~ (8d ilt\k)~fbis)itle i11: u~ \>y the JUIC ffijndicate that the transttctionrequested},ythemaster-port interface has been initlatied. Thq BCI lilt line is a~ed
only during master f:)Ort· trar.sactions and is not asserted during BHCfgenerated intcttupt' tind
interprocessor interrtf>t transactions. The line is asserted during the'fustt:ye1e ofa VAXBI or
loopback transactwn anc;l ~~ jtsserted for the c:hna«Q~LQfthe ~action.. It i$ deasserted
during the cycle when the i!Y~t 1:9de is transferred .f~n'l ~n~!~ During wtjte-type and;
broadcast transactions, the BORAl' line remains asserted until the ~1!lCknowledgc; cycle of the;
slave is on the VAXBl l;>us, .'l'lW; OC'CW"S three cycles 1:1.fter the last da1;a. ~Je during W'1ite·type and,:
broadcast transactiomvDurlng read-type and identification t~nsactio13$.,,theline~as~rted
until two cycles after the last data cycle to allow time for an intemalparlty check. The tiCfi l l line
is deasserted during the sixth cycle for a stop, invalidate, and master-port interprocessor
mmsactions.
·
If'the user's interface reasserts die ~CJ RQ~1:6> im.elkfore ·.· ..· . .. .· ., .if.ottJ#l<::!;iAI< as· ducirig a pipeline re<iuest: the notm'fil'tiriliiig·¢f the ooHCJ~''~'it· . '1 intFtti~iiCI Mk
signalisdea$settedmdie cycleaftertbe~BCf a·'i!( Hl~ was\~~tet.tll'W!ill~nbie~at
the. statt of the newlylaj~~·~~atrilaster·pc;>rt;intett~$·Y1
OCI N~ ~ThiSline is~seneab1the~ttct0. ~sr.~.n~t .~~·~~·fi~m ~e master-port interface during VAXBI write-type co~~ aii:(i:,,w'in(i~te tb't~ inutet-P<lrt
interface that;theda~ond~e ~H~.~4d~~~~
.. ·., ~~tJ~·~~~
data.cyclesinwhicPthe~ool$,~eivP,g~~··~.·.··· ··.· .......···~~~!<~W~~·~··~~i
pr no.~ow~~ge gJnfit;~ati,ori.oode ~s ·~~wiili..me d1ttl:t:rof J.1,~·i1*~·.Pldty of ·tlre
received<lat:a ~·
Duringwrite.·cypetratiSacti&ris, th!i! ~.~ofthe8(411N~~~ is~'to~lihenem
write-data longward:Thenew data to be wntt:enmllSt:be ~P~~upipttth¢BbID<· ~:kOO>
linesbe(orethe~nmgof··dte nex.t eycl~;1Beta~theBll'~~buffe~~1'4e!tl\e Be'.imCT
line is asserted only> onee for.each. cl4ta \l.ijraj ~·lf the·mN~i:lnls re'tfi&iot··mlled for one or
mare times.
;.'? ;,
trei During read-fype transactions; the il5sertihg~of th~ Nl'jsignal.Jn~t& tl'tat.tilf! data ()n
the BCI D<3t:OO> linesiSwu&;ti\biixna1lieU$alwtlo&sth~l~ddiita'i~1~htmel"sintE!r&ee.
Bc1··~··J)gta·E.-me...~M~!)..;Zl'fhiS·sf$naf'isas~1bY·t~·st1c·a~·~~·cycie'ro
µldicate'. t61 i:hefu~tt;r-port .m~~t· ~ha~ tft~ ~o~~~ informatioilCir' $t}lfSllclul6be
ttimsferred to the.Bel D<31:00>', B(;!!<~:<l~i~d'BCl~·~es.....· .....·
Because of the buffer storage in the BIIC, thelJCI Mfiit. si~aH~ as~rted only on~ tci~~ the
·.· ·.'· ··. nns command/~dress information and once 19 tl:llpst~~ ~firs~
For siinplifiesthe deSign of nod~s thatpt!rtdrJri ~r·tftt.' ..J
·····
'df
lr~d~..itls
j
capab~n Mtly.
transactions greater tlianone·16~ora; the'~lI~~y·as~tti~:~~ltmanY tf!hestorthesarne
data rorlgword; '!'he BC! NXT line llowever is as~rt&l oru* ortd:'(o:r ~athdata h:ing'Wom, . '· '
I·
._ ·, :,Cy·",
,
· i; _, ,-·,,· <·'?
BClSlave Signals
The .BClslave signals,respond to transactions directed to a nooe·
BClResponse (Bt:iRS <f:'O>)--These lines areuseclby the slaVe-port interface to select the code
on the BI CNF<2:0> lines in response to command and data cycles. They are also usetlfur
diagnostic mode function selecti.On. The sl~pon interface rnllst. lilSpj:>nd :With the appropl'Utte codes whenever a transac.ttion that involves the slave~port intedae¢ OCCUl:s· Transacti(}ns to i.mc registers do not involve the slave-port interface. ,A..~sponse is~ for each cydetin which the
slave node transfers information to the BICNF<2:0> lines. Table 10 lists the slave response codes. .
Confidential and Proprietary
·4-13
-·
BCIRSLines
1
0
H
H
H
·L
L
H
L
· L
· · · Re.pqnse · · · ·· · · ··· · · ··· · ~lcN~ c~~
no acknowledge (NO ACK) acknowledge (ACK)
stall
retry
Result
no acknowledge (NO ACK) ACK or NOACK st.all, ACK, or NO ACK retry or NO ACK
Correlation does not always exist between the response code and the corresponding confirmation
code transferred on the VJ\XBI bus. When a code is not involved in a transaction, the BIIC
respo~ds with the NO ACK confirmation code regardles~ ofthe code on the BCI RS< 1:0 > lines.
Some confirmation codes are illegal during ·certain types of cycles. During multiresponder transactions, a retry is an illegal response. If the slave-pott interface sends an illegal code during a
cyde, the IllIC .will reply W;ith a NO ACK code on the BICNF<2:0> lines except when a stall
response occurs to a multiresponder command.
BCI CotlUIWld Latch Enable (BCI CLE)-This line is·monitored by the user's interface to detect the presence of a oommand/address cycle. The deasserting edge of the signal can be used to latch
the received command/address information from the BCI D < 31:00 > and BCI I< J:O > lrnes. The
BIIC asserts BCI CLE signal during the cycle after the BIIC recognizes that the BI NO ARB signal is asserted and the BI BSY signal is deasserteq.. This no arbitration/busy state corresponds to an arbitration cycle or the last data cycle of a transaction that has a pending niastet. The BIIC deasserts the BCI CLE signal during the cycle after. the command/address cycle when the command/3Cidress information is on the BCI D<31:00> and BCI I<3:0> lines. The command/address cycle is detected at the transition of the BI BSY signal from the deasserted to the asserted state, when the ];'II NO ARB signal was .asserted during the previous cycle.
The BCICLE signal may be asserted for more than one cycle following a powerup sequence :when
different RUC nodes complete the self-test operation at different times. This.can}>Ccur during the
burst modt: and following a pending ~bort by a master. During loopback transactions, the BIIC sequences the state of the BCI CLE line without regard to the state of the BI BSY and BI NO ARB
signals, however; the timing relative to BCI signals is the same as for a transaction on the VAXBibus.
The state of thi;: BCI CLE signal does not depi;:11d on the receipt of valid parity orwhether the node
is selected as a slave. A silo or cache-resiqent node that monitors the bus and examines all VAXBI
transactions can use the deassertion of the BCI CLE signal to latch the information during any command/address cycle on the VAXBibus.
The assertion of the BCI CLE line should be used to force the slave-port interface t<J a state from
which it can respond to an SC code during the following cycle. In addition, the slave-port interface shpuld ensure .that the stall response code is. removed during the cycle when the BCI q.~signal is
asserted.
BCI Slave Data Enable (BCI SDE)-This line is used by the BIIC to indicate to the slave·port interface that the data ·to be transmitted 011 the VAXBI bus should be transferred to the
BCI D< 31:00!>, BCI I <3:0>, and BCI PO lines.
4-14
Confidential and PMprietary
-·
BCI Select (BtI SEL)-~ ~ is~~er~.by ~e BIIC tP: in{otm the #e-port interface ~tit has been selected by ;a VAXBI transaci:ion. The BCI SEL line is ~ during the ell'!bedded arbitration cycle of a transaction if the slave was selected by the·to~dfaddress inf<>rnmtiOh
from the previous cycle. The assertion of the BCI SEL signal is dependent on the receipt of valid
parity.dunns the.conunandfaQdre$S cycle.
,
1
The. assertion of the }jC'ls~ ~·~ ~m~.g ~the se)j;Ct);O,d¢ onthe BCf SC< 2:Q> lines.
Tsuhbe$B~.CoIf~V?AlXrBoIl~linid. s\tas~ .~~tf·e·.r...J/l.·t .. cCt:~S~l~\~f~~?~<?~~ i~l~a·~~~:~;ntiejr~faecsetthoactraeatetenoatcruesqtuoimreidzetod
~~nd to J?Wtkast s~ce. ~~~.~~\Vtite·t#. ~m"(i.SJ~j:lear the MSEN bit in the
:~:~~::r·1 dec0&mfa~{~ JPWti.~t~~~<~5i~n!~ ~pt requited. (Refer the Bue
'i1M: actSfil:liiie ~ iSserted wheritbe. fOlloWibg eo~ havM:Y¢e4received:
·,
·,,, ,,, ' ' , ' ;.·····:;;..,_,'"; ..,._·,,·-~;-··,·r .; _.. ,._,·~·-.;.··.---- '\'.''r-~:- ·,,,·i~:t·"··:··-.·- ,.','' ._ ·,c.1·.,,, ;e· 1 ;c··,:·'.'
· A read- or wri~cype co~ 9l00~-~~ f~wi~. ~~defined by the starting and
ending address.regili~rs of the BUC.
··
,: : ..· · ·
r ."
. _ 1 - -,
,. , ~ .' ,, -"·
. " , ,( :"-- . ·- .<- ., ·i · . , -- ,
· A refld·o~w~cy~ coiwn~w~,a~~;f~~wi~,~ql~-.space an(! the MSEN bit is
set in the BCICSR.
· A.read-~ wrf~type~Qln~~t IJlll~aqesihC.~~~in~~<;slisl'ace ~f·the··~· an<lthe
UCSREN bit is set in the BCICSR.
· Area<kor \Vri~typr;: co~ncl that mat<;~~:.BllC cs~~ of·the noclt'l~ theJJ!ICSREN
.bit is set jn the BQ(;SR.
. .
. . . ' '
· A BDCST commanil cfu.e2ted att~.~~·~tiqc,;; ·;,,,,_..~in the BCICSR.
· AS;I'QJ?1;9~(f ~ i;lt tfte ij~~.
.l?f:N . .
ii;\Jhe BClC,SR.
· A RESERVED command;«'nd.theRESEt·U.Utoisseimcdte:ac1~~.i ;i,
· AnINVA.L rom~·ot.a Wri1:e-ty~ c~.dl~t1i:s·~~~to the range of addresses
defiuedbythe stardog.anclendirlg address·~ w~.fiRexlNY~~N or the WINVALEN bit is
set in the BCICSR.
BCI Select Code (BCI SC< 2:0 >)-These lines transfer detaile<;J selection information from the
BIIC to the slave-port interface. The presence of select code is indicated by the assertion of the BCI
SEL line. The assertion of the select code depends on the receipt
· , h~19g~d/
addrc~ informatio~ lf the µsey'.s.~~ flJ)lx ~Acles ~~,~ < . ,
SEL line is not J..eqUi~. The BCI select cOd¢s !.®Ji$iat iO !~ble lL , '·' ',., ·,,,,·<''·' 1:·--.' -- ,, '
, t~ ~.9£ ~X " ' · .·
-··
BCISCLine
2
1
H H
H
H
H
L
H
L
L
H
L
H
L
L
L
L
Table n · VAX!l1787:J2 ~t akte Assigntnents
0
H
A default state to indicate that a selection has not occurred.
L
A read- or write-type command clir&ted to the control/status register
of the user's interface has been received and the UCSREN bit in the
BCI control and status registe; (BCICSR) is set. A read- or write-type
eommand directed to the control/status register of the BIIC has beeri
received and the BICSREN bitin the BCICSR is set.
H
A read- or write-type command directed to the range of address space
defined by the starting and ending address registers of the BIIC has
been received and the MSEN bit in the BCICSR is set.
L
A read- or write-type command directed ·to the range of addresses
defined as multicast space has been received and the MSEN bit in the
BCICSR is set.
H
An identification transaction has been received and the IDENTEN bit
in the BCICSR is set.
L
An interrupt transaetion with a destination that matches the node
has been received and the INTREN bit in the BClSCR is set or an inter-
rupt transaction :with a destination that matches the node and a source
that matches the IPINTR mask register has been received and the
IPINTREN bit in the BCISCR is set. '
H
An invalid or write-type command that is not directed to the range of
addresses defined by the starting and ending address registers of the
BIIC has been received, the BCI D29 bit is not asserted indicating that
the address is not within I/O space and t:he INVALEN bit or the
WINVALEN bit in the BCISCR is set
L
A BDCST, STOP, or RESERVED command with a destination that
matches the node (except for the RESERVED command) hgs been
received and the BDCSTEN, STOPEN, or RESEN enable bit in the
BCICSR is set.
Bel Interrupt Request Signals the interrupt request lines are used to interrupt currtint processor operation and cause'the
processor to branch to a routine to service the interrupt.
BCI Interrupt Request (BCI INT< 7:4 >)-These lines are used by the user's interface to request
that interrupts be performed by the BIIC. The BCI INT<7:4> signals must be synchronously
asserted. Each INT line signal causes an interrupt at the level corresponding to its bit position. The
BCI INT< 7> initiates level 7 interrupts, BCI INT< 6> initiates level 6 interrupts, etc. Interrupts
can also be generated by writing to the interrupt control register of the user's interface to set one or
more of the force bits
4-16
Confidential and.Proprietary
-.-. .·. .~111.1::
the TheBCllNTlines are."pseudo-~.;,~. '.fh,e&iC samples the state of lines.~~~ received llne T150/0. The BIIC determines when' a transition has occurred on t~ lines by comparing the.
state of-~ ff()m the p~ioos cycle with the received s~ of the eurrenteyde. The
ttan!ition ftpm the~ ~tate to the asserted stilte specifies an ititettupt reciuest.
1)e w;:u:N1"<7:4> '!lnes 8.fC ~:wi~ with the. BCI RS<;l:O> illnes for diagnostjc mode
~p selection·. ' ' ' ' BCI 1.iansaction Status Sigolb.
T1re ttan$aetjon, ~~~pi'9Vicl,e ~~;informati,on ,related1,¢> the V.AXBI int,eyface, ~ VAXBI
bus, or diagnostic pl'Q81'am.
BCI Event c.ode ('i0-"'"',.'""'1-v".."i"c:-4-,4-.::>-·..~· 'fliese Jines indicate the ~ of':Significant events
within the BllCorotl'the'V.Ae!.~tduiingthe diagn<:>stic ~· The three clitsses of.SV coda. are as follo'\Vs~ 'lhble 12 lists. the event.code$.
BCIEVL.ine
4
.3
2
H, H H
H H H H H H :H'' Fi :R
H H L
H: H L
H H L H H L
H
· '··NEV .... The def~t deasserred state
H
'MCP' 'Master~pt}rt tranlsaction complete'
L
't'
AKRSD. 'B'IO
··
..··,:s¥uskntiomwe~ou~te
~vedf!Xftn
· ·. · ··
slave~
·
data
·
H
~J. p ' ·.·(:W..· 'r.·
, , .·· (~'.I_O1l£l·teSt passed ..
,
H,
RCR ·· · Retry· coPflrmation recefved fof master-
,ROrt OO~
L
It IRW
'lnternafic@ster written
t
t
~CR Advance4retry conf~tion received
' , ,·
,
.(~ ' ,
'
4-17
Preli~ ·
BCIEVLme
4 ;
2
1
0
lknemJnic.
Dillcription ..
'
·
H
L
H
H
H
NJ;CI
No ;acknowleci~e ,9.t:. ille:gal c;onfirmation
received for interrupt command
H
L
H
H
L
of NICIPS No acknowledge illegal confirmation
received for Force-bit interprocessor/~top
command
·
H
L
H
L
H ·AKRE Acknowledge ·.confirmation· received ·for
error vector
H L
H
L
L
IAL
Identification arbitration lost
H L
L
H
H
EV4,
External vector selected-level 4
H L
L
H
L
EV5
External vector selected~level5
H
L
L
L
H
EV6
H L
L
L
L
EV7
L H H H H sm
External vector selected-level 6
External vec~or selected--level 7 Stall timeout on slave transaction ·
L
H
H
H
L
BPS
}>11d parityreceived Cluring slave: ttansa1::tioq
L
H
H
L
H
ICRSD illegal confirmation received for slave data
L
H
H
L
L
BBE
Bus busy error
L
H
L
H
H
AKRNE4 Acknowledge confirmation received for
nonerror vector-level 4
L
H
L
H L
AKRNE5 . Acknbwledge · confirmation received for
'nonerror vector-level 5
L
H
L
L
H
AKRNE6 Acknowledge confirmation received for
nonerror vector....,..,level 6
L
H
L
L
L
AKRNE7 Acknowledge confirmation received for
nonerror vector-level 7
L
L
H
H
H
RDSR
Read data substitute or res~rved status c~~
received ·
L
L
H
H L
ICRMC illegal confirmation received for master-
port command
L
L
H
L
H
NCRMC No acknowledge confirmation received for
master-port command
L L H L L BPR
Bad parity received
L
L
L
H
H
ICRMD Illegal confirmation received by master-
port data cycle
L
L
L
H
L
RID
Retry timeout:
L
L
L
L
H BPM
Bad parity received during master-port
transaction
L
L
L
L
L
MTCE Master transmit error check
BCI Power Status Signals
The power status lines provide information to the user's interface relatedto the condition of the ac , and de power.
4-18
Confidential and P.t:oprietary
m BCI ac ·Power @CI At. LO)....This signal is a buffeted and s~hro~ BI AC··w signal to the
user's irtterface to~ the irtterfaC(!·~ mo~r the power status. The tjuc receives t~s~~ of
m ACIO sigp~ ~d~ a ~o;Ci74:¢delay to verify that the ~~v~dsi-a«t is st®le.It the9 ~smits
the state of the s p to·theotiCI AC line. The BIIC will not ch~gf!Jhe State of the BCI ik LO
_signal unless the state of the line is ~t frorrithe (>recedi[lg state for two cycles.
BCI de Power (BCI fil'.IJ.\j)..;,,.'fhis signal indicates·tJl:ie$Mils oftfje.dc~fothe user'~ interface.
The BIIC asyQ~~~. -~ ~ct; BCI DC LO line f9~-me a5seriion of the. BI l),C LO
signal. The maxi
· ,. ~is speclfietf,~~~ · · ·
· s. When t~ Bl DC
!" . LO is assertedfor . . l'la110$eCOndlir
... ·. ·. ··· The anc deii.5serts
the BCI .De Jjj;sy~fi6Utit·\\Jith11~iT~ ~· foll~'ll2filti deassertion·of M.oo·.LO. A
validdeassertionreq#,th,a~:theJll~fb · :· · ·····. ·· -
·. ·. · ~rtwol,!s>~tive
cycles. While
D < 31:00>'
the BCI
Bl<llJ1:Cof>fl~i$'-aWssBeCrtIePdO;thdel'iv~letls.
·.·....drivers includf~.t~e BCI
;,'. 'Q(the VAXBf tn'&IUle by
allowing the modules ·w be t¢stec:i independently o£ the>sa::o~ .-: .·:;l i ··.
' ~'
'" ,' '
'· - ,_. ,_,__ '"
,,
s
tf1e When the node reset bitof the VJ\XBil Ct1ntmt·~1~~~ is set, BIIC as~ertS'.thelCI DC
LO line regardless ofthe state of ~;:PJ.~gs,~~, ~~en the lat Ot WiS de~'··~. BIIC
The a initiates the self·test, J31IC m~nWns ~tow:leveloutpu11cveltage-on the\1Ci OC f15 when
w thrv the BI oc ts ~~~µgli cc ~ppl,y vol~e to t~e ~f,IC is.in.tt1tnfiltion,
The BIIC loads the nocJe identifkation,'the>~ce i:ype· an~ feVisi9n, and parity mode·identific:a-
tion during the cycle ~fore the BCI .DGi~1~&nal is deasser~. Normally, thtf usesr'sjn~rface transfers the this information to the BCt I f l:(}:>; BCI D< 3lt()O>, and IJCI pt} lin~~ while the
The BCI DC LO is asserted. BCID<.3l:OO>,andJ3ClJ?Olinesi;o.~n in~~pu.ijupsclretitts that
are enabled during as$erti~n'Of the B<:1nc i'.lO lfj~sana¢~ r~~'tb.~~by'default. The default ~ondition m&y be useful in designing a nOde. The outputcurrent characteris~of the
pullup devices should be verified.
·
BCI Clock Signals
The clock signals from the user's interface provide the basic timing information for .µie VAXBI interface and user's interface.
BCI TUne (BCI TIME L}-1hisi~ a2o:~z ttL thiiirlg signti supplied by the VAXB1 dock
receiver in the user's interf11ce. 'it·is u~d·:Wjth1:ne ~blPfiASEL signal by the ,sue attd'user's
interfa~ to generate all the r~4-:tiroi.og~n~.. BCI Phase (BCI PHASE L)-.:-~ is.,a. ~,,Mij~.,;tf.~;~ ·~al suJ,>plied by the v~i:clock receiver in the user's interface; It is used with the :BCl11ME VSignalby the BUC and the user's interlace to generate all required timing signals.
· VAXBI Interface Registers
imd The VAX,B.l interface contain~ a co~plete set of VAXB.J reg:~ters. four geJleral purpose registers
fi&t that~ availllble w.~~fdefihecfoode l~c.·Tf{~ Bile re~~t~<~~edifitfi~ 256 bites Of
wfilch the.JJIIC nodespace,·
is des~ted. lls tlte;~~e.csil. s~c~;·1'¥(¢st tbcations in ~'CS~ node
spa~'are ~use4'. Wtiena ~ad-tjpe ~ommand8,~s8es the un~~ 16cations, the ~tic tespt>nd~by
~.zeros..When .·~·.write,;fype
c§~M but ignori!fl:he data.
CAfi>~nd F~ 5
asilico~wsssesthteb~:umn#rcd'·'lk0gcis~trefrutflo$r,mtahte
line accept~ the
and the ~s
a8signments. ·
· ·
·. ·. · ··· ·. · · ·
·. ' · ··
· .
4-19
31
bt>+OO .
bb+04
24 23 AESEAVEb
.. 16 15 . ·. .C::.c:. I
OEVICE REGISTER
' . ·J_
00
---'-
1. I
~ ·
.... ·
VAXBI CONTAQL /STATUS REGISTER
bb+08
BUS ERROR REGISTER
bb+OC bb+10 bb+14 bb+18 bb+1C
ERROR INTERRUPT CONTROL
RESERVED
I
IP INTERRUPT MASKAEGISTER ..
·
r ·
RESERVED
IP INTERRUPT SOUACEREGISTER
_,. .... ERROR VECTOR
INTERRUPT DESTINATION
~ -cc .
RESERVED
FORGE IPINTRISTOP DESTINATION
I RESERVED
..
bb+20
STARTING ADDRESS ·
..::.:UNUSED
bb+24
ENDING ADDRESS
UNUSED
,.
bb+28' bb+2C L bb+30 bb+34 bb+38
SCI.CONTROL/ STATUS REGISTER
--
WRITE STATUS REGISTER
I
FORCE IPINTRl$TOP COMMAND
I
UNUSED '
-'-
UNUSED
bb+3C
UNUSED
bb+4Q
USER INTERFACE INTR CONTROL
VEqTOR
I bb+44
UNUSED
bb+EC bb+FO bb+F4 bb+F8 bb+FC
!----
-+·
GENERAL PURPOSE REGISTER 0 GENERAL PURPQSE REGISTER 1 GENERAL PURPOSE REGISTER 2 GENEFIAL PURPOSE REGISTER 3
Figure 5 · VAXBI 78732 BIIC Registers and Address Assignments
The I}IIC i,-egist~rs can be accessed by a VAXBI transaction from a node to its associaieq BI1C or to a
BUCassociate,4 with another node or by a loopl;iack trans~j()n from the·!llaster-P'?rt interface,of a
nod,c. When the registers are ;:\Ccessed by a loppba~kcoinmand frpma master-port int~rfaceorby a
VAXBI trans~ipn, ,the high-o~erhits BI I) <:'2<;):B> of theaddte~s d;tat select the rii;J~ ~dclress
spare are ignored huhe BIIC. The lciw-orderhits (D < 12:01 >) c!etc:rml.nc: whether an i~tc:rnal
are regist~r is selected. A register is selected when bits D < 12:0S :> equal to zero and the ~mainfr1g
bits D < 07:00 > specify the register to be accessed.
· · · ·· ··~
4-20
Confidentialand Proprietary
-
Preliminary
l
VAXBI 78732
The BIIC supports write-mask transactions but does not support t e lock functionality for the internal registers. The interlock-read with cache intent (IRCI) transac~ion is performed as a normal
read transaction and the unlock-write-mask with cache intent (UWMCI) transaction is performed
as a write-mask transaction.
I
I
BIIC Registers Description The register description tables contain a code in the "Type" column that defines the type of bits in the register. Tuble 13 lists the codes and definitions.
Table 13· VAXBI 78732 Regi.-TypeCodes
Type
Definition*
DCWC Cleared following a successful self-test when the BCf DC W signal from the BIIC is
deasserted.
DCWL Loaded on the last cycle in which BCI DC W is asserted. Set if the BCI signal lines are not driven during this cycle.
DCLOS Set following a successful self·test.
DMW Can be written during the BIIC diagnostic mode which is reserved for use by Digital.
RO
Read-only.
R/W
Normal read/write
SC
Special case. Defined in the VAXBISystem Reference Manual.
S'IOPC S'IOPS
Cleared by a S'IOPcommand to the node.
Set by a Stop commarid to the node.
WlC
Write-1-to-clear. Cannot be set by the user's interfa<:e:
NA
Not applicable.
DS
Disables selection.
*Set refers to high level and clear refers toa low level.
Device Register-The device (DTYPE) register contains information to identify the node. It
consists of a device revision and device type field that are loaded from the BCI D< 31:00 > lines during the last cycle in which the BCI DC ill line is asserted. The register will be set to all one bits if the information the BCI D < 31:00 > lines is not present when the BC! DC W line is asserted.
Figure 6 shows the format of the register information and Table 14 describes the bits.
C<>nfidential and. Proprietary
4-21
.. ··-·····-----------------·-------------
···
VAXBI 78'732
31
1615
()()
bb+O'-~~~~D-Ev_1_c_E_R_E_v_rs_1o_N~~~~..._~~~~D-E_v_1_cE~TY_P_E~~~~.......
Figure 6 · VAXBI 78732 Device Register Format
Bit 31:16
15:00
Tuble 14 · VAXBI 78732 Device Register Description
Type
Description
R/W, DMW,
DCWL
Identifies the revision level of the device
R/W, DMW,
DCWL
Identifies the type of node
Control and Status Register-The VAXBI control and status register (VAXBICSR) contains interface identification, error and control information. The register information is shown in Figure 7 and described in Table 15.
31
bb + 4 [
J VAXBI INTERFACE REVISION
VAXBI INTERFACE TYPE HARD ERROR SUMMARY SOFT ERROR SUMMARY INITIALIZE BROKE SELF-T!;STSTATUS NODE RES!;T UNLOCK WRITE PENDING HARD ERROR INTR ENABLE SOFT ERROR INTR ENABLE ARBITRATION CONTROL NODE ID
2423
I
16 15 14 13 1211 1009 0807 0605 0403
00
1111 IIJlIII I ]
J
Figure 7 · VAXBI 78732 Control andStatus Register Format
4-22
Confidential and Proprietary
VAXBI78732
Bit 31:24 23:16
15
14 13 12 11 10 09 08
07 06 05:04
03:00
Table 15 ,· VAXBI 78732 VAXBI Control and .status Regi¥er Descriptiotl
Type RO
Description
IREV (Interface revision)-Indicates t~ revision level of the BIIC. The content of this field is incremented for each major revision.
RO
ITYPE (Interface type)--Contains the following code (0000 0001).
RO
HES (Hard error summruj)-Set todndicate that one or more hard
errors bits in the bus error register are set.
RO
SES (Soft error summary)-Set to indicate that one or.more. soft etror
bits are set in the bus ~r register.
WlC,DCLOS INIT(lnitialize)_:_Implementation dependent. STOPS
WlC,DCLOS BROKE (Self-test fail)-Set to indicate that the BUG did not piaSs tpe self-test routine.
R/W,DCLOS
STS (Self-test status)-Set to indicate that the BIIC has passed the selftest.
SC
NRST (Node reset)_:_Set to initiate a complete node self-test. Reading
this bit returns a zero. The STS bit is automatically reset by the BIIC
when this bit is set to allow the recording of the new test results.
RO
Reserved and cleared to zero.
WlC, DCLOC, SC
UWP (Unlock write pending)-Set to indicate that an interlock read With cache iritent (IRCl} transaction ~as been completed by the master-
port interface at this node and ~ ~e 'has not issued a subsequent
unlock writemask w#h cache intent (UWMCI) command. Cleared by a
master-port U\'QMCl ttall.Sactio11 that !fas been successfully completed.
If a UWMCI transaction is attempted· by the roaster-port interface
when this bit is not set; the ISE bfrin the bus error register will be set.
R/W, DCLOC,
STOPC
R/W,DCLOC, STOPC
HEIE (Hard error interr:upt enable)-Set to enable the generation of error interrupt when HES (bit 15) is Set. ·.
SEIE (Soft error fnterrupt enable}--Set to enable an error interrupt to
be generated when SES Chit'14) is set.
R/W, DCLOC
A'RB (Arbitration cootrol)-Indicates. the mode of arbitration to be used as follows:
Bit
5
4
Description
0
0
Dual round robin ai;bitration
0
1
Fixed high priority (reserved)
1
0
Fixed low priotitY (rese;rved)
1
1
Disable arbitration (reserved)
RO, DMW, DCLOC
NODE ID (node identification)-An identification number assigned
to the node. This information is loaded from the BCI I< 3:0 > lines
during the last cycle in which the BCI DC W signal is asserted.
Confidentilll·and Proprietary
4-23
11111111
VAXBl787)2
Bus Error Register-The bus error regi~ter (BER) provides hard error and soft error indications, and parity gehefation control. All bits iii the error register can be set during the VAXBI and loopback transactions except where noted. The register information is shown in Figure 8 and
described in Table 16.
3130292827 262524 23 22 21201918171615
-"-
l11111 l11 ll l bb+B
NO ACK TO MULTl-RESPONDER COMMAND RECEIVED
JJj MASTER TRANSMIT CHECK ERROR
J
ll ll
O's
CONTROL TRANSMIT ERROR
0403020100
111 JJ
MASTER PARllY ERROR
INTERLOCK SEQUENCE ERROR
TRANSMITTER DURING FAULT
!DENT VECTOR ERROR
COMMAND PARITY ERROR
SLAVE PARllY ERROR
READ DATA SUBSTITUTE
RETRY TIMEOUT
STALL TIMEOUT
BUS TIMEOUT
NONEXISTENT ADDRESS
ILLEGAL CONFIRMATION ERROR
USER PARITY ENABLED
ID PARITY ERROR
CORRECTED READ DATA
NULL BUS PARITY ERROR
HARO ERROR BITS <30:16>
SOFT ERROR BITS <02:00>
Figure 8 · VAXBI 78732 Bus Error Register Format
Tuble 16 · VAXBI 78732 Bus Error Register Description
Bit Type
Description
31
RO
Reserved and cleared to zero.
30
WlC, DCWC NO ACK (No acknowledge)-Set when a master-port receives a no
acknowledge command in response to an INVAL, INTER, IPINTER,
BDCST, or RESERVED command.
29
WlC, DCWC MTCE (Master transmit check error)-Set when the data transmitted
is different from the data received. During the transaction cycles in
which the master is the only source of data on the BI data path, the
BIIC verifies that the data to be transferred from the master is the same
as the data that the master receives. If the data is different, this bit is
set. This check is not performed when the encoded ID is transferred
from the master during embedded ARB cycles.
·
28
WlC, DCWC CTE (Control transmit error)-Set to indicate that a node has detected
a deasserted state of the BI NO ARB BI BST or BI CNF< 2:0 > line
during a cycle when the node is attempting to assert the signal. No
check is performed during burst-mode transactions.
27
WlC, DCWC MPE (Master parity error)-Set if the master detects a parity error on
the bus during a read-type or vector acknowledge data cycle.
4-24
Confidential and Proprietary
-
\"
VAXBl.78'132
Bit Type
Description
. I
26
WlC, DCLOC ISE (Interlock sequence error)-Set wh~ the node SU(Cessfolly com·
pletes a unlock write-mask with cadre intent (UWMCI) command and
no corresponding interlacl<: read with ~e intent (IRCI) was previ-
ously iSSl.led. The unlock write pi;;nding bit in the VAXBI control and
status register is m:.>t!let.
25
WlC, DCIOC TDF {Transrnitt:er durfug:faµlthSef ·Wlwn the master or sla~ detects a
pi.ttity ettQr during the following cycl~:in.which the master or slave was
responsibk #;ir ~·the ptopc?C:Wity on the VAXBI bus. This
bit is not set by parity errors ~t oci;ur. during loopback transactions.
-Ccirninand/adQress ~set }:iitlje ~ter -,..Read-type ~~e da~Fwl~~>~t:·by the slave
-:-Write-cype9aui, cyck,:s..set by the ;nas~
-Broadcast ~.cycle$ set, by the. m~ter
-Vector acjmow~c;dge data cy~lc;:s.set.br. the slave
- Embedded arbitration cycles with ;theencoded mast:er identification
set by th'.e master
· ·· ' ·
24
WlC, DCLOC lVE (ldc;:ptification~t~t);Or}-.-!ffl:when an acknowledge response
is not receivedfrom the master to indicate that the interrupt vector was
not received correctly.
23
WlC, DCLOC CPE (Command parity error)-Set if a parity error is detected in a
corxitnatld/ad,dtj:ss cycl~ of a VA){Bl p~.lpopgack tn\n~qµ..
22
WlC; DCIOC SPE (Slave parity error);__Set wh'.enaparityerrorisdetected bya slave
duriµg a write·type il<:knowledge; i write-type st1.dli or hr®dcast
· acknowledge data cycle.
21
WlC, DCIOC RDS (Read data substitute)-Set when read data substitute of reserved
status code is received during a read-type or vector status identification
data cycle. Valid parity must be received during both transactions.
20 "WlC,DCIOC ' RTO (Retry timeoutJ-Set when tM mastefteceives 4096 consecutive
retry.respon.ses fQr the s~mi: ~h;i ~t~ traµ~c~ion.
19
WlC,DCLOC SID (Stall timeout)-:-Set when the slave port asserts the stall code
information on the BCI RS <'1:0 > Un,~~ f9ril28~onsecutive cycles.
18
WlC,DCIOC BIO (Bus timeout)-Set when the nodeJ~folriitiate one of several
transaction that are pending befcire 4JJ96 cycles ~e elapsed.
17
WlC,DCIOC NEX (nonexistent addiessJ..:::...Set when the node ~ceives a no acknowl-
edge response for a read-type or wri~·type command after a successful
parity check of the node and master plirity ch'.etkhas occurred.
16
RO
ICE (illegal confirmation error)-Set by the master or slave node when a reserved or illegal confirmation code is received by the BIIC.
15:04 RO
Reserved and cleared to zero
4-25
- - - - - - - - - - - - - - ·_. .n--.- - ·______., . , ____
·~-
w _ _ _ _ _ · _ _ _ _ ~ ... -~---·-"·-~""" - - · - - - · · - -
VAXB17S732
Bit Type
Description
3
RO, DCLOC UPEN (User parity enable)-lndicates the parity mode of the BIIC. Set
to indicate that the user's interface will generate parity. Cleared to
indicate that the BIIC will generate parity. The user's interface provides
parity on the BCI PO line when data is requested from the user's
interface. The levels are reversed from those on the BCI PO line.
2
WlC, DCLOC IPE (Identification parity error)-Set if a parity error is detected on
the BI I< J:O > lines when the encoded ID of the master is asserted
during embedded arbitration cycles. This bit is not set during loopback
transactions.
1
WlC, DCWC CRD (Corrected read data)-Set when the master receives a corrected
read data status code after valid parity has been received. Valid parity
must be received during the data cycle that contains the corrected read
data code. This bit is set although the transaction may be aborted after
the status code has been received.
0
WlC, DCLOC NPE (Null bus parity error)-Set when odd parity is detected on the
bus during the second cycle of a two-cycle sequence during which the
BIARB and BI1IBY signals were not asserted.
Error Intetmpt Control Register-The error interrupt control register (EINTRCSR) controls the operation of the interrupts initiated when the BIIC detects a bus error or when the force bit in this register is set. An error interrupt request can be initiated provided the appropriate interrupt enable bit in the BIIC control and status register was previously set. The register information is shown in
Figure 9 and described in Table 17.
31
bb+C
2524 23 ·22 21 2019
1615 14 ·13
O's
0 0
INTR ABORT INTR COMPLETE INTR SENT INTR FORCE LEVEL 7:4 VECTOR
Figure 9 · VAXBI 78732 Error Interrupt Control Register Format
0201 00
0 0
4-26
Confidential and Proprietary
...
Preliminary
Bit 31:25 24
23
22 21
20 19:16 15:14 13:2 01:00
Table t.7 · VAXBI 78732 Error Interrupt Control Regist'ef Descripdotl
Type
Description
RO
Reserved and cleared to zero
WlC,DCLOC, SC
INTRAB (Interrupt abort)-Set by the BIIC when an interrupt command initiated by this register is aborted. A command is aborted when no acknowledge or an illegal confirmation code is received. When set, the BIIC is not inhibited. from initiating or responding to subsequent interrupt or identification transactions. This bit is cleared by the user's
interface.
WlC,DCLOC, SC
INTRC (Interrupt complete)-Set when the vector for an error interrupt has been successfully transferred or when.an interrupt command
transferred undel' the con®L Clf' this register is abo~d. This bit is cleared when the error interrupt ~uest has been removed: When set,
no interrupts can be.generatedhfdii:s register. When this hitis set, this
register will not respand to identifkatID:n transactions.
RO
WlC,DCLOC, STOPC, SC
Reserved and cleared to zero.
lNtRS (Interrupt ;Sent}~Set. wher1#1 interrupt command has been sent, Removal of the ~rror interrupt ~~u~st will clear this bit during an identification tra~o~.£oU9w,ingd~e detection of a level match and a
loses master identif.ic;9,tkin ~atch. When ~' the interrupt can be sent
again if the node the identiEicatiOnarbitration odf the node wins the arbitration but the vector transmission fails.
R/W,DCLOC
STOPC
R/W, DCLOC
INTRF (Interrupt force)-When set, an error interrupt is posted the
same as in the bus error register except that the request is not qualified
by HEIE bit7 and SEIB bit 6 in the control and status regi:Ster.
LEVEL 7;4 (Interrupt coilunatidl~G~dicates the level(s) at which the interrupt commands under codtrol initiated by this register are transferred.
RO
Reserved .and cleared to zero
R/W,DCLOC
VECTOR (Error interrupt vector)-Contains the vector used during the error interrupt sequence. ·
RO
Reserved and cleared to zero
Confidential and Proprietary
4-27
VAXBl787)2
Interrupt Des:tinatic>n,..Regisbe?...,.The. interrupt destinati9n (lNTRDES) register identifies the nodes that have been selected by the interrupt commands. The destination is transferred during
the interrupt command and is monitored by all the nodes to determine which node is to respond: The register information is shown in Figure 10 and described in Table 18.
31
1615
00
bb+10'~~--~--~~-o-·s--~~~~~---~~~'N_T_R_._o_Es_T_1N_A_T_1_o_N~~~---
Figure 10 · VAXBI 78732 Interrupt Destination Register Format
Bit 31:16 15:00
Table 18 · VAXBI 78732 Interrupt Destination Register Description
Type
Description
RO
Reserved and cleared to zero.
R/W, DCWC
INTR DEST (Interrupt destination)-During an identification command, a node compares the decoded identification from the master with the coded information in this field. When the information code is
the same, this node responds to the identification sequence provided that the ·unserviced interrupt request is the same level as the level
transferred during the identification command.
Interprocessor Interrupt Maslt Register-The interprocessor (IP) interrupt mask (IPINTRMSK)
register identifies the nodes that are allowed to send interprocessor interrupts to the BIIC. The register information is shown in Figure 11 and described in Table 19.
31
1615
00
Figure 11 · VAXBI 78732 IP InterruptMask Register Format
Bit 31:16
15:00
Table 19 · VAXBI 78732 IP Interrupt Mask Register Description
Type
Description
R/W, DCWC
IPINTR MASK (Interprocessor Interrupt mask)-When a bit in this field is set, the interprocessor interrupts directed to the BIIC from the
corresponding node will allow selection provided that the IPINTREN (bit 5) of the BCI control and status register is set.
RO
Reserved and cleared to zero.
4-28
Confidential and Proprietary
-
VAXBI78732
'
Force-Lit IPINTR/S1'0P,Destinatiott Register-The force-bit interpnkessor interruptlgtop desti-
nation (FlPSDES) register identifies the nodes that will receive the fotte··hit. intd\):rt>ce!illor
interrupts or stop commands issued by the BIIC. The register inform!ltion is show~ in Figure 12
and described in Table 20.
·
/
,
31
1615
00
bb+18
O's
Figure 12 · VAXBI 78732 Force-bit IPINTR/SI'OP Destination Register Format
Bit 31:16
Table 20 · VAXBI 78732 F~e-hit IPINTIVSTOP °'5tinaoon ~ Oescription
'Fype
J.l.e,...;..~.r..·....'-.·.·.
RO
Reserved.and cle~d to zero. '
15:00 R/W, DCLOC
FORCE-BIT IPIN'nU§tOP OJ::St (Force-bit interprocessor interrupt/
stop destination)--".Cotrunat'ld/addres& informati0l1 prov'ides by the user's interface«f6r t!::ie ma&ter·pott interprocessor interrupt transactions.
Interprocessor Interrupt Source Register-The interprocessor interrupt source register (IPINTRS) stores the decoded identification of a node that sends an interprocessodnterrupt command to the
BIIC. The register informatfon is shown in Figure 13 and describedin Table 21.
31
1615
00
bb+ 1 c-'~~---l-P-IN-T~R-SO--uR_c_e____......,.__.l~.--~--------"'o·~s---~~------I
Figure 13, · VAXBI 78732 IP. Inte~pt Souw;e Refhter Format
Bit 31:16
15:00
Table 21 · VAXBI 78732 IP Intermpt Source Register Description
Type
Description
WlC,DCLOC, SC
IPINTR SOURCE (Interprocessor interrupt source)-Each bit in this field corresponds to one node and is set when the destination of an interprocessor command to the BIIC is the same as the identification in this field.
RO
Reserved and cleared to zero.
Confidential and Proprietary
4-29
...
VAXBI787J2
Starting Address Register-The starting address register (SADR). defines: the starting address a 256-Kbyte. block of storage in a memory space or··l{O space excluding ·node space or· multicast space. The end of the block is defined by the ending address register. If the value of this address is greater than the ending address value, the address will not be recognized. The register information
is shown in Figure 14 and described in Table 22.
313029
1817
00
bb+20~'0~1_0.1~~sT_A_R_T_1N_G~A-DD_R_E_ss~--''--~~~~~---~-s~~~~~~~
Figure 14 · VAXBI 78732 Starting Address Register Format
Bit 31:30 29:18
17:00
'lable 22 · VAXBI 78732 Starting Address Regis~r Description
Type
Description
RO
Reserved and cleared to zero.
R/W, DCWC
START ADDR (Starting address)-ldentifies the address of the first location of a 256-Kbyte block of storage to be recognized by the BIIC for selection of the slave port.
RO
Reserved and cleared to zero.
313029
1817 ENDING ADDRESS
00
O's
I
Figure 15 · VAXBI 78732 Ending Address Register Format
Ending Address Register-The ending address register (EADR) defines the last address of a 256-
Kbyte block of storage in a memory space or I/O space excluding node space or multicast space.
The starting address of the block is defined by the starting address register, If the starting address value of this address is greater than the ending address value, the address will not be recognized. The register information is shown in Figure 15 and described in Table 23.
4-30
Confidential·and Proprietary
VAXBI78732
Bit 31:30 29:18
Type
Description
RO
Reserved and cleared to zero.
R/W, DCLOC
END ADDR {Ending address)-Specifies an ad<;hess valu~ that is
.· greateir by one than the. highest a~~s recognized by the BIIC for
selection by the s~e.port. The ij<;ldte!is m\lSt be the first location of the 256·Kbyte block of addresses. If~ i;tartjng address register contains
the value 1C44 0000. ~declfiuV,):, ancl the ending address register
cqntains the v;due. 1.D68 .OQOQ. (~ePmal), then the BIIC will
recognize addresses 1C44000thr<>ug.h1067 FFFF for selection of the
slave port. ·
·
. ··
17:00 . RO
Reserved and cleared to .zero;
BCI. Contt:ol and ·. SU!.tus .Registet--The BCI conttql and sta~s. register (BCICSR) contains
command enable bits t<> control the opemtipn ofthe slave~wrt ~rface. The register information
is sh<;lwn in Figure 16 and describeci iq ':I'al?Je 24..Figure 16 shows ~e register format and Table 14
lists the function of the information.
31 bb+28
18 ~.7 16 1514 13 12 11 ii> 09 oil .07 06 05 04 03
·00
figure 16 ·VAXBI BCI Control and Status 'B,egisterFormat
Confidential and Propri~
4-31
...
Preliminary
VAXBI71732
Bit 31:18 17
16
15 14 13 12 11
10
Table 24 · VAXBlBOlControl and Status Register Description
Type
Description
RO
Reserved and cleared to zero.
R/W,DCLOC, NA
BURSTEN (Burst enable)-When set, the BIIC asserts the BI NO ARB signal after the next successful arbitration until this signal is reset or until the BCI MAB signal is asserted. The assertion of the BI MAB signal clears the burst-mode state of the BIIC but does not clear this bit. The BI NO ARB signal will remain asserted through the next successful arbitration unless it is cleared by a subsequent transaction.
R/W,DCLOC, SC,NA
IPINTR/S1DP FORCE (Interprocessor interrupt/stop force)-When set, the BIIC arbitrates for the bus and transfers an IPINTR or S1DP command. The command that is sent is stored in the force-bit interprocessor command register and the destination field is contained in the force-bit interprocessor/stop destination register. This bit is cleared by the BIIC after the interprocessor interrupt transaction. If the transmission fails, a no acknowledge' or illegal confirmation for force-bit for INTR/S1DP command (NICIPS) event code is sent and the no acknowledge to multiresponder command received (NMR) bit in the bus error register is set.
R/W,DCWC, DS
MSEN (Multicast space enable)-When set, the BIIC asserts the BCI SEL line and transfers the appropriafe slave code on lines BCI SC<2:b> after a read- or write-type command directed to the multicast space been received.
R/W,DCLOC, DS
BDCSTEN (Broadcast enable)-When set, the BIIC asserts the BCI SEL line and transfers the appropriatie slave code on lines BCI SC< 2:0 > after a BDCST command has been received.
R/W,DCWC
S1DPEN (Stop enable)-When set, the BIIC asserts the BCI SEL DS line and transfers the appropriate slave code on lines BCI SC<2:0>
a after S1DP command has been received.
R/W,DCWC
RESEN (Reserved enable)-When set, the BIIC asserts the BCI SEL
line and transfers the appropriate slave code on lines BCI SC < 2:0 >
after a RESERVED command has been received.
R/W,DCWC
!DENTEN (Identification enable)-When set, the BIIC asserts the BCI SEL line and transfers the appropriate slave code on lines BCI SC <2:b> after an identification command has been received. The BIIC will participate in an identificatiofrtransaction to this node when this bit is cleared.
R/W,DCLOC, DS
INVALEN (Invalidate enable)-When set, the BIIC asserts the
BCI SEL line and transfers the appropriate slave code on lines
BCI SC< 2:0 > after an INVAL command has been received.
4-32
Confidential and Proprietary
-
Bit Type
09 R/W, DCLOC,
SC
08
R/W, DCLOC,
SC
07
R/W, DCLOC,
SC
06
R/W, DCLOC,
DS
05
R/W, DCLOC,
SC
04
RjW, QCLOC,
NA
03
RjW, DCI.OC,
NA
02:00 RO
WINVALEN (Write invalid enab1e)-:-·:~1htn set, the BUC asserts the
BCI SEL line and transfers the appropriate slave code on Iines
BCI SC< 2:0 >. This occurs after the.!BIIC receives a write-type command with an address n9t within the .range of .the starting and
ending address register values and not within the I/O space.
UCSREN (User's interface CSR· s?ace enable)---When set, the BIIC
asserts the BCI SEt~ lllld ~~~~the appropriate slave code on
lines BCI SC<1:6.:> af~ ~ei~ ~- ~7 . or write-type command
directed to the rontrolanils~~ter in~ user's interface.
BICSREN (BIIC control/states register space enable)-When set, the
BIIC asSel'ts the imI SEL line antHr~nsre!'.'S'the appropriate slave code
on lines BCI SC <1:0 > after receiving a read- or write-type command
directed to the control and status register in the BIIC. The BIIC always
p~pa.U;~ 4i t.1:1,\ps~ct:ipns that ~s this s~-
INTREN (Intemtpt ~nable)-When s~.Jhe BIIC asserts. the BCI SEL
lii1e and transfers the appropriate slave code on lines BCI,SC<2:0 >
after receiving aread- or wnt¢:i:~ command directed to the BIIC..
,.,
,.
'
'
· · . , , ..,- ·'
''
·l' ·;;. · ·.. '
IPINTREN (lnt~~sol' ~pt;enable)-When set, the BIIC
asserts tile BCI SEL line and tra,Qsfers the approp~te slave code on
lines B.¢l s('!'<2:0> ~ receiv~g ail IPINTR comrriand from a node
that is included,in the itl.~ett>rocesS<>r~pt mask registet: The BIIC receives the lPINn c0:n)m~'rf;gafale$s of the s.tate of this bit.
PNXTEN (kiPffine ~f ellahle)--\YJhen set, the BIIC provides an
Vie additional next 4ata ,':"?rd ~e ~ last longword is transferred
during write-type ilnd Hroadeiist. t~a¢tlons, This cycle can be used to transfer pain·· tofirst~in/first~t'tF'IFO) buffers in the nmster port:
RTOEvEN {Retry timeout ·~ ~ble).:_When set, the BIIC trans-
fers a retry timeout (RTO) Wte'aa of~ cqµfirmation receivedfor
master-port conmumd.·fR.CR) event code"°n lines BCI EV <4:0 > after
a retry timeout has occurred. Ifthis bifis cleared, the RTO bit in the bus error register will be set and an error interrupt will be generated if
enabled.
Confidential and Proprietary
4-33
~---··-------·-·------·--~--~------·-----------··
·-
Preliminary
VAXBI78732
Write Status Register-The write status (WSTAT) register indicates which of the general purpose registers have received information during a write VAXBI transaction. The registerinformation is shown in Figure 17 and described in Table 25.
bb+2C
00 O's
GENERAL.PURPOSE REGISTER 0 GENERAL PURPOSE REGISTER 1 GENERAL PURPOSE REGISTER 2 GENERAL PURPOSE REGISTER 3
Figure 17 · VAXBI 78732 Write Status Register Format
Table 2.S · VAXBI 78732 Write Status Register Description
Bit Type
Description
31
WlC, DCWC GPR3 (General purpose register 3)-Set by a write VAXBI transaction
to general purpose register 3 if valid parity is received. This bit is not
· set by loopback transactions.
~~~~~~~~~~~~~
10
WlC, DCWC GPR2 (General purpose register 2)-Set by a write VAXBI transaction
to general purpose register 2 if valid parity is received. This bit is not
set by loopbacktransactions.
29
WlC, DCWC GPRl (General purpose register 1)-Set by a write VAXBI transaction
to general purpose register 1 if valid parity is received. This bit is not
setby loopback transactions.
28
WlC, DCWC GPRO (General purpose register 0)-Set by a write VAXBI transaction
to general purpose register 0 if valid parity is received. This bit is not
set by loopback transactions.
27:00 RO
Reserved and cleared to zero.
Force-bit Interprocessor Interrupt/Stop Command Register-The force-bit IPINTR/S1DP command (FIPSCMD) register allows an interprocessor interrupt or stop transaction to be initiated when one of the interrupt force-bits in the user interface interrupt control register is set. The register information is shown in Figure 18 and described in Table 26.
31
1615
1211 10
00
I bb+3o~l--------~~o-·s--~----~~~--r--~l.,....l______~o·_s________, COMMAND
MASTER ID ENABLE
Figure 18 · VAXBI 78732 Forr:e-bit lPINT/STOP Command Register Format
4-34
Confidential and Proprietary ,
... VAXBI78732
Bit
31:16
15 : t i
Type
RO
R/W, DClOC
11
R/W,DCWC
10:00 RO
Description
Reserved and cleared to zero.
the CMD (Cotximand)-lrtdkates 4-bit com1Iland rode used to initiate
an interpro&ssor interrupt or stop transaction when one of the
interrupt force"bits m the tiser interface hitettupt control register is set.
The oomtnaiid t:odeS are
Bit
~d
" 14 13 12
1 1 1 1 IPINTR (lnterptocessor interrupt)
1 . 1 0 0 STOP
..~
MID.EN (Mastet J&;:ntjfkati.Qn enal?l~h-Set to enable the master
identification tq h;e. t~eri.-¢d on the ~II>< 31:00> lines when the
commfl!ld field Cbits ;15:12) con~ .~tdnt.erprocessor command code
during the command/address cycle. When the command field contains
a STOP command, this hit should be cleared:
'~. '
'
-· ' '
.., ;,
' ',· '· - '.
<
'
' ·''
' '
-"
Reserved and clea~t:o zero,· ,
User Interface Interrupt Control Registet....:Tue user 'interface interrupt control register
(UNITRCSR)conttolsthe operation of theinterr\ipts imtlatcd hy&.e·user's interface. The register information iS shewnin Figure19 and descdb&l in Table 21; T~ interrupt request referred to in
Table 27 are illterrupts initiated hy the BCI INT< 7:0,>. lines 0r· by $C,tting the force,.bits in this
register.
2627
0201 00
0 0
Figure 19~ VAXBI 7~?J2Dser Inter,[Q,Ce ln~Pt Crmtro/Register Format
Confidential and Proprietary
--~----·--------·-·-··-·-----~-~~-~--------·-----
4-35
____,_________'
-
Preliminary
VAXBl78732
Bit 31:28 27:24
23:20
19:16
15
Table 27 ·VAXBI'78732·User Intetfaee.Interiupt Control Register Deseriptkm .
Type
Description
WlC,DCWC,
SC
INTRAB (Interrupt abort 7:4)-These bits correspond to interrupt l~Is 7 through 4. A bit is set when an interrupt command sent under control of this register is aborted causing a no acknowledge or illegal confirmation code to be received by the BIIC. Cleared by the user's interface. The state of this bit does not prevent the BIIC from
responding to other interrupt or identification transactions.
WlC, DCLOC, SC
INTRC (Interrupt complete 7:4)-These bits correspond to interrupt
levels 7 through 4. A bit is set when the vector for an interrupt has been successfully transmitted or when an interrupt command sent under
control of this register is aborted. When a bit is set, no additional
interrupt requests at the level specified will be generated. No response to identification transactions will occur when this bit is set at the IDENT level. A bit is cleared when the corresponding interrupt request is removed.
WlC,DCWC, SENT (Interrupt sent)-These bits correspond to the interrupt levels 7
SIDPC, SC
through 4. A bit is set when an interrupt command for the correspond-
ing level has been successfully transferred. This bit is cleared during an identification command that follows the detection of ~ level and a.
match of the master identification. This bit is cleared when the
interrupt request is deasserted. When cleared, an interrupt request can
be sent again if the BIIC has lost the identification arbitration or if the
.. BIIC has won the arbitration but the vector transmission failed.
R/W,DCLOC, S1DPC
FORCE (Interrupt force 7:4)-These bits correspond to interrupt levels 7 through 4. When set, the BIIC generates interrupts at the specified level. Setting a bit is equivalent to asserting the corresponding BCI INT<7:4> line. When multiple interrupt requests are asserted simultaneously, the BUG transmits the interrupt command for the request with the highest priority first. The BIIC responds with the highest pending priority when an identification command solicits
more than one level.
R/W,DCWC
EX VECTOR (External vector)-When set, the BHC solicits the
interrupt vector from the BCI D<31:00> lines in response to an
identification transaction to select this register. The slave port transfers
an external vector selected (EVS) level during the cycle preceding the
vector transfer on the BCI D < 31:00 > lines. A slave-port interface that ·is using the BIIC must st111 the vector by transferring a stall code on the BCI RS< 2:0 > lines for at least one cycle during the identification
arbitration cycle before transmitting an acknowledge (with vector) or a
retry response.
Confidential and Proprietary
-
VAXBl 78'732
Bit 14 13:02
01:00
Type
RO RfW,DCLOC
RO
Description
Reserved and cleared to zero.
·, VECTOR (Interrupt sequence vector)-C~ntains the vector used during the user's interface interrupt sequences except when the external
vector bit 15 is set. The vector is transferred when the BIIC wins the
identification arhitratkm that is the same as the conditions specified
by the user interfaee mterrupt control register.
Reserved and cleared to zero.
t'Jeneral Purpose Registers The BIIC contains four general purpose registers (GPRO through GPR3) that are available to the
user and are implemen~tion specific. The type of bits in thiese riegi~ters are RfW ai;id DCWC.
When information iswritten toa GPR, thewtite status i:e@Stet,'f:dentifies the·GPR that received
the information. Figure 20 shows the register format.
31 . bb+FO bb+F4
00
'
-'
GENERAL PURPOSE REGISTER 0
bb+FS bb+FC
--
GENERAL eu~~Oie REGISTER 3
!'..
1..;. -
Figure 20· VAXBI78732 G,eneralPurpose 'Register Format
Confidenti,a). i.md J?roprietary
· - - - -- -- -----
----~--------
4-37
-
Preliminary
VAXBI 739'J2'·
Slave-only Status Register
. .
The slave-only status register (SOSR) is located out of the BBIG CSR space and is used by slave
nodes that have a device-type code and contain zeros in bits 14:08. The register format is shown in
Figure 20A and the information is defined in Table 27A. The Broke bit and Memory Size (MSIZE)
field must contain valid information. This is a read-only register andnmst not be written into.
31 2928'
1Bl7
131211
0
bb+ 1001
I
I II
MEMORY SIZE BROKE
I
Figure 20A · VAXBI 78732 Slave-only Status Register Format
Bit 31:29 28:18 17:13 12
11:00
'Jable 27A · VAXBI 78732 Slave-only Status Register Description
Type
Description
Implementation dependent
RO
MSIZE (Memory size)-A binary number that indicates the size of
memory as a multiple of 256 Kbytes.
Implementation dependent
RO,SC
Broke-Set by the user's interface before BCI DC W from the BIIC is deasserted to indicate the failure of the node to pass the self-test. Must be cleared by the user's interface upon the successful completion of the self-test.
Implementation dependent
Receive Console Data Register The receive console data (RXCD) register, implemented by VAXBI nodes that have a console terminal on the VAXBI, is used to receive data from other consoles. Nodes without a console must issue a no acknowledge response to read commands to this register or return a longword with the Busy 1 (bit 15) set before the Broke bit of the slave-only register is cleared. The RXCD register responds to longword VAXBI bus transactions directed to this register. If the RXCD register is in a primary console node, a lock bit must be implemented in the interface. When the optional upper word of a unlock write with cache intent (UWMCI) command to this register is not used, the mask bits can be ignored (assumed to be all set).
The register format is shown in Figure 20B and the information is described in Table 27B.
4-38
Confidential and Proprietary
O's
BUSY2 NODE 102 CHARACTER:!
24 23
.. VAXBI 78732 .
12 11
si 1
0
O's
BUSY 1 NODE ID 1 CHARACTER 1
OPTIONAL <31:.16>
REQUIRED <tS:O>
Figure 20B · VAXBI 78732 &ceit!t Console Data Register Format
Bit 31
30:28 27:24 23:16 15
14:12 11:08 07:00
'&ble.27B · VAXBI 78732 Receive.~nsoJe 0.ta Register Description
Type
Description
R/W
Busy 2-Set to intli.8ltethat th~ character 2 (CHAR 2)field (bits 23:15)
has not been read by the remot;e node. This b~t rnust be cleated before
CHAR 2 is available for anOther' character. ·
RO
~am:Jc1e~fu zeros.'
R/W
NODE ID 2 (Nooe identification 2)-Contains the identification of
the local node that se9t information to the Character 2 field.
R/W
CHAR2.(Chara~ .~n-contains the console command character or
console message 8ent frorii the local to the remote node.
R/W
:aw:;y. 1-Set t:o'1ndicate that.the chara~r 1 (CHAR 1) field (bits
07:00) has not been read by the remote node. This bit must be cleared
before CHAR 1 is available for another character.
RO
R/W
NODE ID 1. (NOOt: idehtificarien 2);,..;;...Contains the identification of
the local node that: sent information· to tht'!·Character l field.
R/W
CHAR 1 ·(Character n-tontailis the consol~ command character or
consol~ message sent from the .lOcalto the remote notfe.
·
· VAXBIIntetface Node
.
.
th,at Figure 21 is a diagram of.a \T~l .node si)pws the copn~ng lines anc,I signa4 ~.tweeQ. th~
BIIC and master~port and slave-port user'sinterfaces, an4 b~n the BIIC and VAX.Bfbus. The
BUC t;l~es ar@ matches the addtes~s from .t~e VAJQ3I bus and ~rforms all arbitration fu~ns between the VAXBIbus andtheJ,UIC. It tnclude:s the primary receiver and protocol logic
required to. interface to..the VAXBI. hus .l,l,nd all.VAX.BI bus transceivers as89ciated with the .data
transfers and most 0£ the bus receivers. The master-port a.nd ,sh\ve-por.t interfaces communicate
with the BllC through the synchronous interface BCI bus. The BCI bus consists of 64 lines tha~
transfer data, address, and control information to and from the BIIC. The user's interface can
request transfers th.rough the BC! bus under control of the BIIC.
Confidential and Proprietary
4-39
-
USER INTERFACE·
MASTER
PORT INTERFACE
BCIBUS
Ir
j:! I
'·
~
t: I
SLAVE PORT INTERFACE
....
1-------1 INTERRUPT PORT INTERFACE
p
BCI 0<31:00> BCI 1<3:0>
B81 ~S~4:o>
:= REIAEE8
SCI RS<1:0>
~
~ BCISC<2:0>
BCI INT<7:4> BCI TIME L
BllC
'"'Bll.mY" 61 NO ARB
BICNF<2:"1i> BID<31:00;;. "115i3:0>
·8B1legLLg
BCI PHASE l
VAXBIB us
--.....
FROM VAXBI CLOCK RECEIVER
Figure 21 · VAXBI 78732 Int.etface Node Connections
The BIIC can detect and transfers commands from the VAXBI bus to the master-port or slave-port interface. In a multiprocessor environment, the addresses transmitted on the VAXBI bus are available to the user's interface for monitoring cache invalidate transactions. The BIIC supports the
transfer of information between the master and slave within a single node.
Data and address information is transferred between the user's interface and the BIIC through the
time multiplexed three-state BCI D < 31:00 > lines. Commands are transferred through the BCI
I< 3:0> lines. The direction control is provided by the BIIC. The master-port interface initiates
command sequences by transferring a code on the request BCI RQ < 1:0 > lines and the BIIC
responds by asserting the appropriate enable signal that transfers the command information to BCI
bus. Command and data confirmation is transferred from the user's interface to the BIIC through the response lines. Transaction status is transferred to the user's interface through the event BCI
EV <4:0> lines. Several registers in the BIIC control the operation of interrupt requests. Interrupts can be generated by a$serting one of the BCI INT< 7:4 > lines or by writing
information into one of the interrupt control registers. TheBIIC provides vector information froni an internal register in response to an identification command or it can solicit vector information from a user's interface. ·
4-40
Confidential and Proprietary
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VAXBl-7.8"132 . .·
Master-port Tran~dons The master-port BCI signals are used to generate internode and intranode transactions. Transac-
Port tions directed to other nodes are internocle transactions and are limit:Jd to longwords. Intranocle
transactions can be VAXBI transactions that are issued by the master through the VAXBI bus or loopback transactions that are not transferred through the VAXBI bU.S. These transactions can transfer longwords, octawords, or quadwords.
The master-port interface requests a transaction by transferring a code on the BCI RQ < 1:0 >
lines. The BIIC asserts the BCI MDE line to inform the user's interface that the command/address
information is required on lines BCI I <3:0 >. and BCI D <31:00 > . In sub5equent cycles the BIIC asserts the BCI NXT and BCI MDE lines to request the data &om the user's interface.
Slave-port Transacti9ns The slave-port interface responds to read and write requests to. memory locations in this node but not to transactions that access the BIIC registers. lt"aJsP.~l.ves commands directed to more than one responder such as interrupt commands. The slave port willrespond to all transactions directed to it including more.~ Qne transaction received sequentially. It can operate at the.sustained peak bandwidth of the VAXBI bus i£ the user's interface is capable of this transfer rate.
Nodes that generate interrupts can use the interrupt port of the slave to request the transfer of an
interrupt and to respond with an external vector tO an identification command.
· VAXBI Address Space
The VAXBI address spaee is grouped into memory address space kx:ations and ip.putfoutput (I/O) address space locatio~. During the first cycle of a read-tytJe, write-type, and invalid transaction, a
30-bit physical address A29:00 is transferred on the'.Btl)<29:00> lines. Lin~ BI D<31:30>
specify the length of the transfer in longwotds·. When bit ,AJ,9 .is zero, the 51.2-Mbyte memory space from 0000 0000 to IFFF FFFF (hexadecimal) is accessed. When address bit A29 is a one, the 512-Mbyte I/O address space from 2000 0000 to 3FFF Ff'FF (hexadecimal} is seltfcted. The address space allocations are s4own in :F~ 22.
Con£i<knti.al and. Proprietary
441
Node 0 Nodespace (8KB)
. . ·
Node 15 Nodespace (8KB)
Multicast Space (128KB)
VAXBI78732
Hex Address
20000000 20001FFF
2001 EOOO 2001 FFFF 20020000
2003FFFF 2o040000
Node Private Space (3.75MB)
Node O Window Space
(256KB)
. . .
Node 15 Window Space
(256KB)
203F FFFF 2040 0000 2043 FFFF
207COOOO 207F FFFF
RESERVED
RESERVED (for multiple VAXBI systems)
(480MB)
2200 0000 3FFFFFFF
Figure 22 · VAXBI 78732 Input/Output Address Space Allocations.
4-42
Confidential and Proptjetary
...
I
The VAXBI architecture defines the use of the I/O address space ,that contains node space,
multicast space, window space, and reserved space. Up to 16 VAXBI bi.Jes can be accessed. Address
bits A28:25 define the mapping mechanism used to access these buses. If the I/O space is selected
and an address bits A28:25 is ones, a reserved location of 2200 .0000 through 3:eFF FFFFF
(hexadecimal) is selected.
1
The I/O spaces are selected by the address configurations shown in Figure 23. Two blocks of I/O space are partitioned according to the identification of the node. The node space i&:Positioned at the low end of the I/O address spai::e and coiisiSts1of 16 address bkx'ks eacli rohtaining 8 Kbytes. One nodespace is assigned to each node that can be implemented on the VAXBI bus. The first 256 bytes of each space consists of BIIC control and status register space and the relllaining space is assigned to the user's interface control and status information. The wllidow'splk:e starts at address 2040 0000 (hexadecimal) and contains 16 blocks of 256 Kbytes each and can be used by adapters to
map VAXBI transactions onto the selected bus.
Confidential.and ProptktaJ:1
4.43
-
EJ29
. '
l/0°$1>A~
VAXBillS7J:2
28
25
'
LJsPEc1F1EswH1cH vAx01 aus
24.23
lo ~RO +F NOT
BITS 24: 23 JNDICATJ; RESERVED SPA<;E
El;12 WINDOW SPACE
21
18
D
SPECIFIES WHICH NODE'S WINDOW SPACE
17
00
WINDOW SPACE ADDRESS
G22 NON-WINDOW SPACE B21201918 IF NOT ZERO BITS 21: 18 INDICATE NODE PRIVATE SPACE
El17 NOOESPACE
16
13
DNOOEID
12
00
_.! IL._ _ _ _ _ _ _ _ _ _ NODESPACE ADDRESS
ti17 MULTICAST SPACE 16
00 MULTl CAST SPACE ADDRESS
Figure 23 · VAXBI 78732 I/O Space Addressing
4.44
Confidential and Proprietary
-
i
\
VAXBI78132
Node Space Assignments
Each node that irtterfaces to the VAXBI bus is assigned an identification number (node ID) of from 0 to 15. The ID code determines the bus and interrupt priority level as~ignments and the locations of the node's regis~rs. The ID is selected by jumP,er lead connections on the VAXBI baCkptane. Figure 24 sho"{sthe node space allocations.~ !\Ssignment of.the8-Khyte node space depends on
the type of node as defined by this ident1fic3tioQ·.The.startWg 1@d<:Jret;s for a nqcle is 2000, .0000 (hei.adecimal) plus 8K times the node Ip. The ba8e address is reterrCd to as "bb."
VAXBI. REGISTERS
NOOESPACE !8 KBYTESJ
Figure 24 · VAXBI 78732 Node Space Allocatian
The first 256 bytes ofa node space is re~erve4for t~ v~r~ters ;:ind the ~aiping space is assigned tci user's jnterface control and s~~~gi$~ (t::;S!ls). ~CSR space (bb+100) contains
slave-only status and is us.eel by m~ nodes that do not im;~ei)~ the. ~roke bit of the VAXBI
control and status register. Location bb +200 is reserved for the receive console data register (RXCD) and is implemented by nodes capable of perfoiming''ti'Msactions with the console
terminal. Nodes that do not have the console capability respond to read commands with a no
acknowledge or with a longword in which the RXCD busy (bit 15) is set.
Because the BIIC has one starting and one ending address register, a node canrtot,~po:nd with a window space and region of memory space. Responses oomulticast space and user CSR spate can be disabled by the BCI control and status register.
The BIIC can be configured to respond tbanycombinationof thef,ollOwffig:
'.
· ·-
- '-
-
-
-"
' £ ,_.
-
-
"
'
'
- ""
· The node space of t:he node
· The space defined by thestarting addressa'ndending ·addfess ofthe node ..
· The multicast space
4-45
------·---
Preliminary·
VAXBi 18112
· VAXBI Protocol and Cycle Types
The VAXBI nod~sccm~!lin arbitratioq~iogic. Eachl.lod~.t>rovide,s two arbi~ationlevels. To become
bus master, a node asserts one of the 32 data lines ·. i:luring .lll1 the arbii:ratio.n transact.ion and
monitors the remaining data lines to determine if a lower number line has been asserted. If no line is a~rted, the node becomes.bus master and transfers command/address information immediately
or when the Current bus transaction if has been completed.
.
The BI NO ARB line controls access to the bus data path for arbitration. Arbitration can occur
during a cycle or after a cycle following the deassertion of this line. Arbitration cycles can occur during a transaction or after a transaction. The command/address information from the bus master is decoded by the node during the next cycle.
Arbitration performed during a transaction cycle is defined as an embedded arbitration cycle.
During the embedded arbitration cycles, all nodes update their arbitration priority according to
the arbitration mode and the ID of the current master. During this cycle, the master of the current
transaction transfers its encoded ID on lines BI I< 3:0 > and parity for these lines. From this
information, the nodes check the parity and calculate the arbitration priority. A master cannot
of arbitrate during the embedded arbitration cycle its transaction.
.
The node priority is transferred on lines BI D < 31:00 > during the arbitration cycle. Figure 25 shows the node ID assignment and priority level assignment. Lines BID< 31:16> are assigned the lowest priorities of from 15 through 0, respectively, and lines BI D <16:00 > are assigned the
highest priorities of from 15 through 0, respectively. During powerup, the nodes default to the low-
priority word.
31
2423
1615
0807
00
2 10
v
Low-Priorify Word ·
v
High~Priority Word
Figµre 25 · VAXBI 78732 Node Identification and Priority Assignments
Arbitration MQCies The arbitration modes, defined by the VAXBI protocol, are dual round robin, fixed-high priority, and fixed-low priority. The dual round robin mode is the only user authorized mode. The remaining modes are reserved for use by Digital. The modes are selected by arbitration control (bits
5 and 4) of the VAXBI control and status register and can be changed by a node during system
operation. Any combination of arbitration modes can exist on the VAXBI bus, however; the fixed-
high and fixed-low modes are reserved for use by Digital. AUnodes default to the dual round-robin
mode during the powerup sequence.
Dual Round Robin Mode-During this mode; the node arbitrates on the low-priority word when
the ID of this node is less than or equal to the ID of the previous bus master. When the ID of the node is greater than the ID of the previous bus master, it arbitrates on the higher priority word. If this mode is selected by all nodes on the VAXBI bus, all nodes will have equal access to the bus after a period of time. In multiprocessor configurations, this mode prevents excessive bus latency time that may occur when a node is denied bus access because several processors are performing instruction loops.
4-46
Confidential and Proprietary
VAXBI~7lJ
Fmd Lcnv·pftority Mode-This :reserved mode can be assigned to nod~s that require access to the bus infrequently. Fixed High-priority Mode-This reserved mode can be assigned to podes where critical access time to the bus is required.
Transaction Cycles .
The VAXBI transactions are performed using the command/ad~.. embedded arbitration, and
data cycles shown in Figure26. The basis operation is.~troW by the,BI NO ARB and BI BSY lines.
COMMAND/ ADDRESS (CIA) CYCLE
IMBEDDED ARBITRATION
(IA) CYCLE
DATA
CYCLE
DATA
CYCLE
Command/Address Cycle-This iS the first cycle ofilt.l VAXBI transactions and is identified by a
node when the BI BSY signal is werted. following a cycle where the BI NO ARB sign?l was assefted..
During this cycle, the master transmits a 4-bit cd:tntnatid code in lines'BI'I <3:0 :::- and the information to select the appropril!.te slave on lines BI15 < 31:00 > . Each transaction type is
restricted to one of the formats listed in Table 28.
'.l.iansactlon
Table 28 · VAXBI 78732 Co:mman4/Addrfts Transaction Type
VAXBI Bus Lin~s BID<31:t6S ..
BlD<U;OO>
Read-type Write-type Invalid
Length code and 30·bit address Length code and 30-bit address Length code and 30-bit address
Interprocessor interrupt Interrupt Stop Broadcast Identification
Decoded master ID Level·.
Reserved Reserved Level
Destination ~k · Destination mask Destination mask Destination mask · ·· ReseJ:!VOO
Di.¢ng read-type, write-type, an,d invalid. tt:anlj~i::tio~, the sele<;tion infor.mation consists of a
length code and 30·bit address. The sele~km information can. al,sp be al6-bit dest4t.ation mask in which each bit corresponds to an~ m. This enabl~s :from ho 16, nodes to be involved in the same
transaction. The destination mask is used for all multiresponder transactions except for the invalid
transaction. The interprocessor interrupt transaction uses the decoded mask and destination mask
to select a slave. The level field selects the slave during a identification transaction.
Confidential and.Pmpr!etarY
4-47
...
VAXBii'i873Z
Embedded Arbitration Cycle-During the second cycle of a transaction, the enroded ID of the
master is transferred on lines BI I< 3:0 > and the VAXBI data path is available for arbitration of the
other nodes unless the burst mode is selected.
Data Cycles-One or more data cycles can follow the imbedded arbitration cycle. During these cycles, data is transferred between the master and slave node through the VAXBI data path. The number of da~ cycles required normally depends on the length of the transfers and the number of stall responses issued by the slave. During identification transactions, the number of data cycles depends only on the number of stall responses. Multiresponder transactions, except for broadcast, use one reserved transaction. During broadcast transactions, data cycles cannot be stalled. Therefore, the number of data cycles depends on the length of the transfer. Table 29 lists VAXBI bus information transferred during the data cycle for each transaction type.
Table 29 · VAXBI 78732 Data Cycle Information Transfer
Transaction
VAXBI Bus Lines BID<31:00>
BII<3:0>
Read-type Write Write with cache intent Write mask with cache intent Unlock write with cache intent Invalid Interprocessor interrupt Invalid Stop Broadcast Identification
read data write data write data write data write data reserved reserved reserved reserved reserved interrupt vector
read status reserved reserved write mask write mask reserved reserved reserved reserved reserved vector status
· VAXBI Bus Transactions
This section describes the types of transactions that are supported by the VAXBI bus and defines their use.
Single and Multiresponder Transactions Single-responder transactions are directed to one node and multiresponder transactions are directed to more than one responder. Table 6 lists the commands that can be used with these transactions. During single-responder transactions, data is transferred between a master and a slave node. The master requests that a node be a slave with a 30-bit address. The node receiving the address uses
this and other irtformation transmitted ditring the command/address cycle to determine its slave
status.
4-48
Confidential and Proprietary
VAXBl78132
l
Multiresponder t~ are :initiated by the INTR, IPINTR ! INVAL, S1QP, and BDCST
commands from a ma$ter. During these transactions, the master
of an address. Interrupts are generated by a master.when itissues
as:~li$s.na
destination mask instead coronutnd·messageto one
or more slaves capable of accepting interrupt requests or when it ~sues an IPINTR command to
other processors. The INVAL command is used to notify a node that the cache data in its memory is
invalid. The STOP command is used to diagnose errors. The BDCST command is reserved by
Digital and is u~ to sen{i illformation throU~h the ent4-e system.
·
Interlock Transactions The IRCI and UWMCI interlock cc>mmands and the IPINTR ~rproceS50r co~ds su}1port
interprocessor COtnmuruCatiOf\S,. ThCse Cl)ID~nc-Js allow Ptoi;es~to, ooffilll.urucateby exchanging
messages that ~ ~posited in a shared m~ory. T):ie. shared ~ry .access is synchrc>nized because the ·mem&ry access £rem one proeess'er may be inter~ with memory accesses frem anotherprocesso1'.- Software~level synduonizaponis·achievechhr~trgh the use of the VAX interlock and queue instructions, and impleme11ted by µie IRCI add UWMpltransactions.
During IPINTR transactions, one processor interrupts the operation of another processor. Both shared memory··!Uld. inierproc~~ ~p~s;can ~·.I>(:.. ~;~ pi:pcessor.gtn. deposit a message in a specific location of shared memory·and then Issue a IPINTR command to notify the
other processor.
Indivisible. operation$ are perfo~ qn piooe~or ~s ;\Pd ~ap~ by·~. :IllCI ~ UWMCI
interlock transactions. The interlock f~ature of these ~ns;must b,ejmplenmJ,ltedJor
wiil Retei to ffacmorsooremsmmoomoto~1hai1eyn,tardasiennptdtooed.srla/lsOo~ilCob.CsclkepkIaerb<cCoyeJ~lOad~q~cd~ra·.t·aWd.t· ..iS.D~.C,n.t.Is~o...~Ufil\Cn~lIkc~tetrJii~9mn~s·t~.t9~of·:iu~nn~s..t4.:~·h·t~lei~b.'lr:~(.t'.·t(>~..l.·~s.\..'~?..A."..,
·
xs~.,~s.s.~.lt.'JeftiPmtout·denRs.~le.tsu/s.t~w~;"fe~fi(aMllt)fiotllRc~clCau:~.lrI
.. ·
·
· ··
DDuartai'nIigatnhsefe.rc~ o~and~ /~cyc;}.c;:~f.·~;.t·.~·~.~~.·'Y. ·x..i..·ii:<·ty~·t<nu:..l. s~.(· )'OS..·f. ~.~..~ID<:31:30>"
specify the number of bytes to be transferred an.alin~s :SI15 < .21':Uf1> specify'ihe address.· Thble
30 lists the data length selections.
BIDLines
:n
30
H
H
H
L
L
H
L
L
Table 30 · VAXBI 78732 Data LengthCodes
Data Length
Bytes
Reserved
LW (longword)
4
QW (quadword)
8
OW (octaword)
16
The low address of the block of data transferred is a multiple of the size of the block of data in bytes. During read-type transactions, the address supplied during the command/address cycle may not contain the low address of the block of data transferred.
4-49
Preliminary
VAXBl1S732
Address Intet1treta1tion-The .intetpretation of the address duiing read~type and write-type· transactions depends on the transaction type, address space, data-length field, and low-order address bits. Figure 27 shows the longword and byte references in an octaword block.
31
I 01
B3
I 02
B7
I 03
B11
I 04
815
82
I En
B6
I B5
810
I
B9
814
I
.913
00
I BO
B4
I
B8
I
B12
I
Figure 27 ·VAXBI 78732 Longword and Byte References in an OctawordBlock
Address BO specifies the data length as follows: A <29:02> 'OO==longword, A <29:03 > '000= quadword, A<29:04>; 'OOO=octaword.
Read-type Transactions-:-Table .31 lists the interpretation values of the addresses during read-type
transactions. During this transaction, the slave first transfers i:he addressed longword of data and the remaining longwords depend on the implementation of the node. The address normally is datalength Wgfl.ed and the remaining longwords are transferred in ascending address order. If the initially addressed longword is not data-length aligned, the remaining longwords are transmitted in ascending order until the beginning of the data-length aligned block is reached. A wrap will then occur and the next longword transferred will be located at the base address' of the block. Longwords are then transfened in ascending order until the entire block has been transferred.
4-.50
Confidential and Proprietary
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'llilJle 31 · VAXBI 78732 Reid-t)'pe ':transaction kf;te;s Intetpretatioo
Data
length'
ow ow ow ow
Address
space2
NWS NWS NWS
ws
Address transmitted
A29:04'00XX A29:04'01XX A29:04'10XX A29:04'11XX
Address 11!Ceived
A29:04'00A29:04'011\..a9:04' 1 0 A.29:04'11-
Return data order
D1,D2, DJ, andD4 02, D3, D4, andDl D3,D4, Dl, and D2
D4, Dl, D2, and DJ
QW
NWS
A29:0J'OXX
QW
NWS
A29:0J'1XX
QW ws
Notused1
A29:03'0A29:03'1-
01 llndD.2
D2andD1
LW
NWS
A29:02'XX
LW
WS/L A29:02'XX
LW
WS/W .A29:02'0X
LW
WS/W A29:02'1X
LW
WS/B A29:02'00
LW
WS/B A29:02'01
LW
WS/B, A.29:02'10
LW
WS/B .· i\29:0.f'll
A.29:02'A.29:02 1A.29:02'0A..29:02'1A29:02'00 A29::(}2'01
A.29:02'19 . .A29:02.'ll
Di (BJ, B2, Bl, and BO) Dl (B3, B2, B4, and B5) D1 (XX, XX, Bl;and BO)
01 (B3, B2,'X:X, and XX)
D1 (XX, XX, XX, and BO)
D;L <x:X, xx. Bl, and:X:X)
,01 (XX:,,.82,XX, and XX) DllB3, ~.;xx, and XX)
'Refer to Tuble 30 for data length abbreviations.
2NWS =nonwindow space, WS =window space, B=byte accessible, W =word accessible,
L=longword accessible, X =any data, - ==ignored by slave,.' =concatenation
1Slave must respond with a no acknowledge; .
Write·type 'liansactiotts-Tuble 32 lists the inte;rptetation values of the. addre~es d1,1ring write·
type transactions. During VAXBI write transactions, data is transferred in ascending order.
Confidential and Proprietary
4-51
Preliminary.
l8We }2 · Y~t ;z:s:nz-Wriie.~.type.~cd,on AifdioeS$ln~i.uon
Data
length'
ow ow
~s space2
NWS
ws
Adcbess transmitted
A29:04'00XX notusecP
Address received
A29:04'00-
l{eturn data· order
Dl, D2, D3, and D4
QW
NWS
A29:03'0XX
QW ws
not used'
A29:03'0-
Dl andD2
LW
NWS
A29:02'XX
A29:02'-
Dl
LW
WS/L
A29:02'XX
LW
WS/W
A29:02'0X
A29:02'A29:02'0-
01 (B3, Bl, Bl, and BO) Dl (-, - , Bl, and BO)
LW
WS/W
A29:02'1X
A29:02'1-
01 (B3, B2, - , and-)
LW
WS/B . A29:02'00
A29:02'00
Dl (-, - , - , and BO)
LW
WS/B
i\.29:02'01
A29:02'01
Dl (-,-,Bl, and-)
LW
WS{B
A29:02'10
A29:02'10
Dl (-, B2, -, and-)
LW
WS{B
A29:02'11
A29:02'11
Dl (B3, - , - , and-)
for 1Refer to Table 30 data length abbreviatfons. · ·
2NWS =nonwirtdow space, WS =window space, B =byte accessible, W =word accessible,
L=longword accessible, X =any data, - =ignored by slave, '=concatenation
JSlave must respond with a no acknowledge.
Memory Cache Data-VAXBI nodes that contain data caches must monitor the VAXBI write-type transactions. If a cache location is accessed, the data must be marked as invalid. If the node cannot mark the data as invalid before the monitoring transaction is complete, the monitoring transaction
must be extended. Refer to the VAXBI Systems· Reference Manual for detailed information on
data caches.
Write Mask-During WMCI and UWMCI data cycles, the write mask is transferred on the BI I <3:0> lines. When a mask bit is set, the corresponding byte is modified by the information
on the data lines. These lines are not defined for write-type data cycles that do not use the mask. Table 33 shows the byte assignment for the write mask codes.
Asserted BI I line
3 2 1 0
'Iable 33 · VAXBI 78732 Writ.e-mask Code Assignments
Byte BID line
31:24 23:16 15:08
7:00
4-52
Confidential and Proprietary
-;
Preliminary
:
VAXBI 7'8732
Read Status-The BI l < 3:0> lines trans;fer a read-status code from !he slave to the master during
the acknowledge data cycle of a read-type or identification transactiqn. The code defines the type of data returned to the master. Table 34 shows the read status code a~signments.
BIIline
3
2
H
*
H
*
H
*
H
*
L
*
L
*
L
*
L
*
*Reserved
Table 34 · VAXBI 78732 Read Status Code _A~~ts
Status
1
0
H
H
Reserved
H
L
Read data
L
H
Corrected readda.ta
L
L
Read data sµhstitute
H
H
Reserved
H
L
Read data/do not cache
L
H
Corrected i;tiid ~ta/do not cache
L
L
Rl::ad data Sllhs.titute/do not cache
Write-type Transact.Wns The VAXBI bus supports four write-type tra,ri~~ol:ls that ¥~ u~~'to tra:psfer di,ita from a master node to a slave node. The followingpa.ragrap}isdesttibe the seq~ used during the transactions.
The abbreviations referenced on the write tri\maction tirtling diagrams are:
M =master node, S.,,; slave node, Ss= more than dpe slave, MN· all arbitrating nodes, AN= all
nodes, APS =all potential· slaves for identify· transactions' priqr ·to ·ide~tificatii;in arbitration
selection. A (>) before a response indicates the CNF code tt(mSferred ~ing the transaction.
WRITE Command_:The Write transaction tt(mSfersdata &om a truistet: to a slave when the master
does not store the data in;cache memory. Figurei2&sh~ the transaction timing.of a WRITE and
Write with Cache Intent (WCI) command for an ~aword.
.
Confidential and Pro~rietary
4-53
CYCLE
CIA
IA
Bl 0<31:00>
3.1 OATA
:30 LENGTH
27
2fi
25
24
~
22
21
~
1~: 1~ 1~ 30 BIT 1~ ADDA 14 I~ 1~
111q
.·~
··~
~
~
~
1
q
SOURCE
M .·
DECODED 10
LOW PRIORITY
DECODED ID
HIGH. PRIORITY
AAN
Bl 1<3:0>
COMMAND
MASTER 10
M
M
M
M
AN
AN
01
c:~ 02
DATA 1
DATA2
M
WRITE MASK
M
M
s
M
WRITE MASK
M
M
s
.. 03
DATA 3
M WRITE MASK
M M
s
OATA4
M WRITE MASK
M M
s
VAXBlt8'732
__ ...;..:.__,...._ .;_,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1 - - - iI
I
I
I
I
I
I
-t----1
I
I
BICNF<2:0> SOURC E
>ACK
NOACK STALL RETRY
s
>ACK NOACK STALL
s
>ACK NOACK STALL
s
>ACK NOACK STALL
s
>ACK NOACK
s
>ACK NOACK
s
~
M I
M
I M,S I M,S I M,S
I
M,AAN
M.S
M,S
t M,S
l
l
I I
~
I I
1 T I
Figure 28 · VAXBI 78732 WRITE and WCI (octaword) Transaction Timing
4-54
Confidential and Proprietary
Preli ~. '.
VAXB17S732
During the command/address cycle, the roaster specifies the ~ength of the d~ta on lines
BID< 31:30 >,the acldress on lines BID< 29:00>, and the comtrufudonlines BH-< J:O >. Parity
No is generated by the rrktster and checked by the nodes. The BI BSY line is asserted until the last
acknowledge data cyck. Duringthe command/address cycle, the BI ARB line isdeasserted and
then asserted with th!:! BI BSY line until the end of the cycle,. During the embedded arbitration cycle, all nodes except for the present master can at~itrate for· th~ ~11s, a:?ntrol.
The slave transfers a command confirmation code to the blaster duJ;ing cycle D 1. This code indicates the slave status and errors conditions. Subsequent crm~ti~m codes I?tpVide informa-
tion related to the data transfers.
·
The master sends data to be written during D 1and sj:icceedingdata cycles. Slaves that are unable to
command, receive the qata at the specified time can iSsue a stalhesponse for a maxilnum of U~ cycles to delay
the data transkr until it is ready. During the data cycles of WltJTE
the information on
the BI I< 3:0> lines is undefined. Durmg the data, cycleS, 'the~masta: generates the parley that is
checked by the slave.
'l'ltls Write with Cache lntejnt-Duriµg the Write with Cache In~t {WCI) trilnsaction;Shown in Figure
28, the data transfeqed may be written into cache memoq.. can occur 9nJy if the data
previously written into the same.location in the cacbr is valid. 'l'he4ave bode mustissue an INVAL
command fqr subsequent write ~ctions to the ~ame locatioriji;that ;are not performed with a
WCIVAXBI transaction.TheWCl transaction is alwa1s perfornied·if'the W,de'is unaf::>Ie todetermine
ifthe data transferred will bewritteninto<;ache.The:response ~o this command by the slave is the
same as a WRITE. command. During the: data cycles of WCI'.command, the information on the
Bh< 3:0> lines is undefined. ·
.
·
Write Mask with Cache Intent-The Write Mask With <Ache lntelilt cWMCI) command. is similar
to.the WCI commarid ~fCPt tha~ ~ ~~ g(tij.~~~fui.~®to1* ffiodffie(l are selected by
the master. The write maskis ~ oa.the MI:<:.3'1b>, lines during each data cycle. The
master genetates parity for the entire VAXl.U data path regatdless ofthe bytes to be modified. The
WMCI transaction timing is shown in Figure 29. . . .
.. .
Confidential and ]?;roprietary
4-55
VAXBl78732
CYCLE
CIA
IA
31
30
29
28
27
~
25
24
23
22j
21
~
1~
1~
1~
BID<31:00>
1~
14
1~ 1~
11
1~
~ ~
~
~
1
~
SOURCE
DATA LENGTH
30131T ADDA
M
DECODED ID
LOW PRIORITY
OECOOEO ID
HIGH PRIORITY
I AAN
01 DATA1
M
DATA2 M
D3 DATA 3
M
..
QATA4 M
COMMAND
MASTER ID
UNDEFINED UNtieFINED UNDEFINED UNDEFINED
FIELD
FIELD
FIELD
FIELD
SOU RC E
M
M
M
M
M
M
BiPO
GE N
M
M
M
M
M
M
CH K
AN
AN
s
s
s
s
T------1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
·· 1
I l I I I I I I I T - - 1I
I
J.
I
I
I
I
+---'--4
I
I
BICNF<2:0> SOURC E
>ACK
NO ACK STALL RETRY
s
>ACK NOACK STALL
s
>ACK NOACK STALL
s
>ACK NOACK STALL
s
>ACK NOACK
s
>ACK NOACK
s
~
M
M
l l l T
}-~ I M.AAN
M.S
M,S I
l M,S
M,S
T
M,S
I
I
I
I
I
I I
Figure 29 · VAXBI 78732 WMCI and UWMCI (octaword) Transaction Timing
4-56
Confidential and Proprietary
I
Unlpck W~ ~ with Cadle Intent-TheJJnJpck Write M;a;sJ} with Cllciie Intent (UWMCI)
command~ used to c~mplete a read-modify-write operation that ~an with an interlock read with
cache intent (IRCI) command. It is used to unlock a shared memory ~truct1..111:. Tiie slave should not
clear the lock bit if a Parlty error occurs duing this transaction. A nbde must issue this transaction
as soon as possible af¢r issuing an IRCI command. Awrite fil$sk is ~erred on:Jines BI I< 3:0>
during each data cycle. The UWMCI t:ramaction timing is shbwnm Fig\lrC 29.
Read-type Transactions The VAXBI bus supports three read-type transactions that areused to transfer data to a master node from a slave node. The followitlg paragraphs describe the s~uence used during·~he transactions. The abbreviations referenced on the write transaction timing diagnuns' are ··
M=master node, S=slave node, Ss=m<;ire ~one slave, M~:=:idlar~~~ nodes, AN=all
nodes, APS =all potential· slaves for identify tnJnsaerlilnsi .prior· to; identifi~tion arbitration
selection. A (>) bef~ a response indicates the CNF code ~erred during the transaction. READ Command-The read transactions transfer data from $lave to master when the data will not be stored in caChe memory. F~ure 30 shows. the ~ransactioo ~ ·of a READ command that transfers an octaword.
4-57
-
VAXBI7s712
~
IA
01
31 DATA' 30 LENGTH
:
:27
24 23 22
:21
' '
DECODl!:D ID
LOW PRIORITY
Bl D<31:00>
18 17 16 30BIT 15 ADDA 14 ,13 12 11
:1C
~ ~
~
DATA 1
DECODED ID
HIGH PRIORITY
1
SOUAC E~
M
MN
s
1iifiO
COMMAND
SOUAC E
M
GE N
M
CH K
AN
MASTER ID
M
M AN
STATUS
s s
M
DATA2
s
STATUS
s s
M
'
DATA3
s
STATUS
s s
M
~-2-~...;.+..:.."""-~,
I ... ,.
. .,
DATA4
s
STATUS·
s s
M
I
I
I·
I
I
I
I
I
I
I
I
I
l
I
I
I
I
I
I
. I
I
I
I
I
I
I
I
I'
1
I
I
1
I
I
I
I
I
I
- 1 - - 1I
I
I
I
I
I
I
---+----4
I
I
BICNF<2:0> SOU RC E
>ACK
NOACK STALL RETRY
s
>ACK NOACK STALL
s
>ACK NOACK STALL
s
>ACK NOACK STALL
s
>ACK NOACK
M
>ACK NOACK
M
, MI
l J l M
M,S
M,S
M,S
'
M,AAN
M,S
M,S
M,S
I 1 1 .,l_I
'T
I
j
I
j
T
I I
l
Figure 30· VAXBI 78732 READ, RCI, and IRCI (oc'taword) Transaction Timing
·Confidential and Proprietary
Prelqinmy·.·
VAXBI78732
During the command/address cycle, the master specifies the length of the data word on lines
BID< 31:30 >,the address on lines BID< 29:00 >, and the comma.Pd on lines BI I< 3:0 > . Parity
is generated by the master and checked by the nodes. The~ line is asserted until the last acknowledge data cycle. During the command/address cydetbe BI ~O ARB line is deasserted and
then asserted with the BI BSY line until the end of the cycle. Durilig the embedded arbitration cycle, all nodes except for the present master can arbi$,~ for the- bus control for the next
transaction.
The slave transfers a command CQnfirmatipn code to th~'.master during cycle Dl. This code indicates the status of the slave aqd any errors conditions tha~~'.maY exist. Subsequent confirmation codes provide information related to the data transfers. A oonfirmation code providing informa-
tion related to the last two data cycles is tran$ferred from the master to the slave.
The slave sends data to be written during Dl and succeediqg.datacycles. Slaves that are unable to send data at the specified time can issue a stall response fo!.""1: maximum of 127 cycles to delay the
all data transfer until it is ready. During data cycl~ ~£Read ¢(Jmmand, the ~ity generated by the
slave is checked by the master and the read status Ii:Om the slllve onJines Bfl < :H1 > provides the
master with status information.
Read with Cache Int.ent-The Read with Cache.Intent (RCI) transaction, shown in Figure .30, is
master used to read data that is intended to be storedin cache. If a "do not cache" read status is transferred
on lines BI I<3:0> from ttje sla.ye, t:he.
must not'~to~ the data in cache memory. The
response from the slave for this comraand is the same as forthe .Read command. This command is
used for cached multiprocessor systems to inform the slave .that the data read will be stored in the
cache memory of the master.
·
Interlock Read with Cache Intent-The Interlock Read Data with Cache Intent (IRCI) transaction
for supports read-modify-write operations and is used with the UWMCI command. The transaction
timing shown in Figure 30 is the same as the read ~ction. When the memory space of a ·
node has been successfully aceessed by this command, the l"I0<1e must set a lock bit that will cause
susequent IRCI transactions directed to the s,'ame locked add~!V#Jbe repeated. The lock bit must remain set until a DWMCI trapsactfon di~ tri die s~me ~ock¢d address range is successful. The
minimum size of an !l<klre5s range c-Qntrcill~by as~'lodc: bit in the window range is a byte, and
beyond the window range, the minimum size of the address r:lnge is an octa~rd.
If the slave transfers a read data substitute status code, the Ill()[ trtmsaction is unsuccessful and the
are lock bit should not be set and the master shocldno~ initiate the .HWMCI transaction. If an IRCI or
UWMCI command is received befoi,;e the errors ~~d'iiiJhe previous !RCI command, the
slave should issue a stafior retry con£irmati9p 1111til the ~bl:!:¢ of the lock is determined.
A multiport memory with a lock bit set by ariy port will issu~ a retty response to an IRCI command.
An IRCI command from the VAXBI bus tC! a UNIBUS aoopter is interpreted as a data-in-pause (DATA.IP) transaction to the UNIBUS and a DATAIP transaction from the UNIBUS to the VAXBI bus
must be translated as an IRCI command to the VAXBI bus..
Invalidate Transaction The invalidate (INVAL) comm.and is used by processors and intelligent nodes dur.ing write operations to local memory to inform.the nodes that their cached data may be invalid. Figure 31 shows the transaction timing of.i INVAL command. ·
Confidentilll and Proprietary
4-59
-------------------·----------'
CIA
IA
CYCLE
31
DATA
LENGTH
VAXBl787;2
01
DECODED
ID
LOW
PRIORITY
4"60
910<31:00>
16 30 Bl.T
·RESERVED
15
ADDA
1---~---1
FIELD
14
13
12
DECODED
ID
HIGH
6
PRIORITY
5
4
3
2
Bl 1<3:0>
BiPO
SOURCE
SOURCE GEN CHK
M COMMAND
M M AN
Bl CNF<2:0>
A~
MASTER ID
M
M AN
RESERVED FIELD
RESERVED FIELD >ACK
NOACK
SOURCE
Ss
BIBSY Bl NO ARB
r )
M
I
I
M
I
I
l M,AAN I
J
\
I
I
I
I
Figure 31·VAXBI78732 INVAL Transaction Timing
Confidential and Proprietary
-
I
During tlie· conimanq/ad~ss cycle, the. master specifies the ~pgth of the data word on lines
BI I>< 3l:30 >,.th~ ~ss on lines BID<29:00 >, and the.C(>~!Ilat:id on lines BII.< 3:0 >. The
data length cod~ specµies the numbet of consecutive addresses tp be invalidated. The low-ordet
address bits ~.~d. Parity is generated by the master and 9-iecked by the nodes.. Table 35
shows the address interp~ion during this tranw,:tion,. ··
. ·
Data length
Octaword Quadword Longword
Adclrest
transmitted
A28:04'0000 A28:03'000 A28:02'00
~"'
received
A29:04' - - - A29:(}3' --A29:02'--
The nodes, except for the present mastei;. can arbitrate for the bus control for the next transaction
during the IA cycle. The acknowledge and no acknowledge are the only valid responses from the
slaves to this command. A node can delay the start of the next transaction to allow time to invalidate its cache by asserting
the BI BSY signal through cycle Dl and until the data is invalidated.
· Interrupt Transactions
The VAXBI bus supports device interrupts consisting of INTR and INVAL transactions and interprocessor interrupt IPINTR transactions. During device interrupts, the interrupting device supplies an interrupt vector in response to the identify transactjon that is unique to the device.
During IPINTR transactions, the interrupt vector and level are the same for all interrupts and are
stored in the receiving node.
Device Interrupts Nodes that are capable of generating interrupt requests contain a vector that is used by the VAX processors to select one or more 512-byte locations in memory. These locations contain address pointers used to select interrupt service routines. During the command/address cycles of the interrupt transaction, each BI D< 19:16> line corresponds to an interrupt level. Line 19 is assigned the highest-priority interrupt (level 7) and line 16 the lowest priority interrupt (level 4). These levels correspond to the VAX processor interrupt priority levels (IPL17 through IPL14). An interrupt node issues an identify transaction when it is ready to service an interrupt request. The interrupt level field from the node must contain only one level of the interrupt it is ready to service. This level must be the highest priority for which the bus master has received an interrupt request and has not responded with a identify transaction. Nodes that have an interrupt pending at the Ident level respond by arbitrating for the bus during the identify arbitration cycle of the identify transaction. The winner of the arbitration transfers its interrupt vector during the next cycle. The VAXBI interrupt vector is different from the VAX system interrupt vector described in the VAX-11 Architecture Reference Manual.
4-61
,,-~-------·------,~----------·--------. ---·-·-··-----------------~-----·-··-------
...
Preliminary
VAXBli8732
are Interrupt v¢clor values of zero arid Vector values th~t are multiples of.200 (hexadecimal) null
interruptsthat ilidicate ho action is required to servic:e th~ l.nterrupt; Ifmore thiin one bitis set in
the destination field of a node, two or more processors will attempt to seNke this interrupt and
each processor will issue an identify transaction. If only one nride issues the interrupt, the first processor to issue the identify transaction willservicethe node. The remaining processors will issue
identify transactions, however; an interrupt vector will not be returned because no contenders exist during the interrupt arbitration cycle. The null interrupt indicates to the processor that no nodes
are waiting to be serviced.
Interrupt Command-The interrupt· (INTR) command is used to initiate an interrupt request to
one or more nodes on the bus. Figure 32 shows the transaction timing of a INTR command.
4-62
Confidential and Proprietary
-
Preliminary
CYCLE
CIA
31
' Bl 0<31:00>
29 28 27
26 RESERVED 25 AELD
24
23 ' '
22 21 20
INm ·LEVEL
15 14
13 12 11 tO 9 8
7 6 5 4 3 2 1
SOURCE
iNTR DEST MASK
M
Bl 1<3:0>
BiPO
SOURCE
GEN
CHK
COMMAND
M M AN
IA
DEcODED
ID HIGH PRIORITY
AAN
MASTER
ID M M
AN
BICNF<2:0>
) ' 01
VAXBl~87J2
RESERVED FIELD
RESERVED FIELD >ACK NOACK
SOURCE
Ss
BiBsY
Bl NO ARB
~ I
{
M
I
I
M
i
I
i ~ M,AAN
Figure 32 · VAXBI 78732 INTR Transaction Timing
4-63
....
During the command/address cycle, the master transfers the interrupt request level on lines
BID< 19:16 >,the interrupt destination maskon lines BID< 15:00 >,and the command on lines BI I< 3:0 > . Lines BI D < 31:20 > are reserved. Parity is generated by the master and checked by
the nodes.
The nodes, except for the present master, can arbitrate for the bus control for the next transaction
during the IA cycle. During the Dl cycle, the slaves transfer an acknowledge or no acknowledge
response to the master.
The node that received the interrupt tt~nsfers an !DENT command to the node that initiated the
request to solicit a vectot: Only one of the many nodes that may receive the IDENT command.will
transfer the vector.
·
During INTR commands, interrupts may occur at more than one interrupt priority level. Nodes respond to the commands if their decoded ID is the·same as the destination code transferred on the BID< 15:00> lines during the command/address cycle. Nodes that respond to INTR commands must store an interrupt pending bit for each of the four interrupt levels to permit them to solicit vectors with IDENT commands. The interrupt level field of a command/address cycle may contain zeros, however, the slave must respond with an ACK confirmation.
Identify Commands-The identify command (IDENT) is used by nodes to solicit interrupt vectors
in response to an INTR command. Figure 33 shows the transaction timing of a IDENT command.
Confidential and Proprietary
Preliminary
VAXBl787)2.
CYClE
CIA
31
IOENT
STALL
Aql( ....
IA
OMIO
AflB
VECToA .vecroa
. OECOOEO PECOl>ED o~ ~f'I~~ O's
IO
.MAEll'Etjl
··L()W··
ID'
ID ARl!lng
l'JETD·
Pfft9RlTY
SI.AVES
BID<31:0Q>
!DENT LEVEL
DECODEo
rd
HIGH
PRIOAfTY
FlESEl'lVJ:o ''FIELD
SOURCE M
MN
BikiQ;
GQMMANO
BIPO
SOURCE
M
GEN
Id.
CHI(
AN
_...._.,...,----,
I
I
I
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f
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I I I
" I
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. .
I I
-~.......,..,,.."'"!':",
f
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:_--t----1
. I
I
BICNF<2:0>
SOURCE
Bl lfSY
l
I
iiiNOARii
~
MI M
lI t ·t ' ,: M,AAN
+ M.APS
¥·~
I I M,APS
M,APS
I
I
s: ... ,
',.. \.
s
' Figure 33 · VAXBI 78732·1DENT Transaction Timing
M
M
I
I ',
t
Confidential and Propri~
-
During the command/address cycle, the master transfers the command on lines BI I< 3:0 > and the identification level' on lines fif D< 19:16>. The IbENT level field can contain only one
asserted bit. Lines BI D<31:20> and BI D<l5:00> are reseved. Parity is generated by the master and checked by the nodes. Line BI BSY is asserted until the vector is transferred.
During the IA cycle, all nodes except for the present master can arbitrate for bus control during the
next transaction. During this cycle, nodes cannot arbitrate for anintr tl-ansaction. The decoded ID is transferred from the master on lines BI 0<31:16> duringthe Dl cycle and the parity is generated by the master and checked by the slaves. Nodes that detect invalid parity must transfer a no acknowledge response and must not participate in the identify transaction.
Nodes participate in the Ident ARB cycle if all of the following conditions exist:
· The interrupt level pending corresponds to the level sent during the command/address cycle.
· A command parity error has not been detected.
· A master decoded ID parity error has not been detected.
· The decoded ID from the master is the same as the INTR destination mask.
The slaves arbitrate by asseiting a bit that correspon,ds to their node 11) on one of the BI D<31:16 > lines. Lines BID< 15:00>, BI I <3:0> and BI PO are reserved during this cycle. The slave with the highest sublevel priority wins the cycle andtransfers an acknowledge, no acknowledge, retry, or stall response in the next cycle. Figure 33 indicates a stall response in this
cycle. During the ACK Vector cycle the slave transfers the vector on lines BID< 13:02 > and status on lines BI I< .3:0 > . If the transfer is unsuccessful because of a parity error, the master transfers a
no acknowledge response two cycles after the slave attempts to transfer the information. The master issues an IDENT command at the same level again to obtainthe vector. Upon receiving the acknowledge response indicating no parity error, the master clears the internipt pending bit at the identify level. When the vector is transferred, lines BI D<31:14> artd BI D<Ol:OO> must be zero. The vector parity is generated by the slave and checked by the master.
Two cycles after the vector has been transferred, the master issues an acknowledge confirmation if a parity error was not detected. The responding slave_ assumes that thevector is correct when the final acknowledge is received from the master. If a no acknowledge confirmation is received, the slave issues theINTR, oommand again prepares to transfer the vector when the IDENT command is received.
Nodes .that participate but lose the identify arbitration must again initiate the interrupt transaction atthe same level to prevent the loss of previously posted identify levels. Nodes transfer a no acknowledge responce if the interrupt condition is removed or if the interrupt was serviced by another node.
4-66
Confidential and Proprietary
VAXBl'87'2
VAXBI lmenupt Vectors
. 'I
T\Vo types of mterrupt:' vectors are issued by VAXBI adapters an~ each adapter. is allocated· four
interrupt vectors. The vector formats are shown in Figure 34. ·
13
$418 07 06 1i5
·02 Ot()Q
O's FfslNooemfofol
13 . .. . Oii oe . . . .. o~j>JJio,
I AOAP'NO I TARGETVEC :J'()l(l+
Figure 34. VAXBI 78732 vAXBI Intetmpt Vecmr Formats
1'he node ID ~r isloqtted betvJ~ !1~~ lbca~ions 100,aQ~ J~F (h~edmal). The rie>de ID
vector field assignments are de:i~ iii Tab~e 36. · · ' · ··
·
Bits
13:09 08 07 :06 05:02 01:00
'&hie 36 · VAXBI 78732 VAXBI Node ID V~ Descriptions Description MBZ (must be zero) Set to one S (Interrupt vector number)-One of four interrupt vector values assigned to a node. NODE ID (Node identification)-A interrupting node value of from 0 through 15. MBZ (must be zero)
Confidentiahmd Plioprieta.ry
. -:Dlil.!lii-----·1&-l'.l'>li-·--ili___,,,,} 1'~----Y!l-_J-
~
;Jl!I' "S"'l<!o _ _ _ _ _ _ _ _ _ __
4.67
The target vector specifies one of up to 128 interrupt service routines. Each,llPapter t:b,!:'tiss.ues tlJ!s
vector ~s 3 .u,tl.jque adapter tt\illllbet; and the range of ~unibers dete~ tqe t3tlgq 9£ possible vectors. The target vector field assignments are describedin Table 37.
Bits 13:09
08:02 01:00
Table 37 · VAXBI 78732 VAXBI Target Vector Descriptions
Description ADAP NO (Adapter number)-A unique adapter number assigned by the operating system software and used in constructing the interrupt vectoi:
TARGET VEC (Target vector)-Specifies the range of possible vectors in a system. All zeros indicate a null interrupt.
MBZ (must be zero)
Interprocessor Interrupt-The interprocessor interrupt (IPINTR) is used by processors to interrupt
the operation of other processors. This command is similar to the INTR command except that the
level and vector are not transferred during the transaction but are stored in the node that receives
the command. Figure 35 shows the transaction timing of a IPINTR command.
·
Confidential and Proprietary
-
010<31!00>
Preliminary
CYCLE
CIA
31
30
29
28
27
2265·· DECODED
24 MASTER.,
23
ID
22
21
20
19
18
17
i'e
t5
r
I I I
IA
' I
VAXBl71q):1
D1
Bl 1<3:0>
BiPO
12 1t 10
B
6 5 4
3
2 1 0
SOURCE
IPINJ:!'l DESTIN-
ATION
MASK
M
COMMAND
SOURCE
M
GEN
M
CHK
AN
Bl CNF<2:0>
AAN
MASTER
IO
M
M AN
RESERVED FIELD
RESERVED FIELD >ACK
NOACK
SOURCE
Ss
BIBSY Bl NO ARB
M
'l.
I
M
y
I
I I M,AAN
{
'\
I
'i
Figure 35 · VAXBI 78732 lPINTR Transaction Timing
Confidential and Proprietary
4-69
'~'lli''-------------------------------~·~·--~·
Prelinu.nary
During the command/address cycle, the master transfers its deooded ID on lines BI D < 31:16 >, the command on lines BI f<3:6>; and the interprocessor destination mask on lines BID< 15:00 >. Parity is genentted by the master and checked by the nodes.
All nodes except for the present master can arbitrate for control of the bus for the next transaction during the IA cycle.
The nodes that receive the interrupt compare the decod¢d ID from the master with the corresponding bit position in the IPINTR mask register to determine if they have been selected. During the D 1cycle, the slaves transfer an acknowledge or no,acknowledge response to the master;
the information on lines BI D < 31:00>, BI I< 3:0 >, and Bfi50 is reserved; and parity is not
generated.
When an interprocessor interrupt request is received by a VAX processor node, a level 14
(hexadecimal) interrupt is generated with an interrupt vector system control block offset value of 80 (hexadecimal) The processor that receives the interrupt examines the IPINTR souce register to identify the processor that initiated the request. A bit is set in this register indicates that an interprocessor interrupt has been received from a processor with the corresponding node ID. These bit should be cleared after being read.
STOP Command-The STOP command selectively forces a node to the stopped state preventing them from initiating a VAXBI transaction. It causes the node to retain the available error information. Nodes, howevei; can respond to VAXBI transactions. This allows the node to be accessed and the error information examined during diagnostic tests. After a STOP command is received, a node can be initialized· by the powerclown/powerup sequence or restarted by the software from its present state. The lock bit of the node must remain after the STOP command is received. Figure 36 shows the transaction timing of a STOP command.
4.70
Confidential and Proprietary
-
VAXBI .ililf:
CYCLE
CIA
IA
01
.--~~~-.-~~~~....,-...._~~--.
31
30
29 28
2
26
25
24 RESlaR\IED
~ FIELD;
22
21
M
Bl 1<:3;0>
filPO
GEN
CHK
Bl CNF<:2:0>
M ,
M AN
M
RESERVED
AN
FIELD
>ACK NOACK
SOURCE
Ss
BIBSY Bl NO ARB
M
l 1 'i {
I M
I { M,AAN
Figure 36 · VAXBI 78732 SWP Transaction Timing
Confidential.and Proprietary
4-il
VAXBI7873i
The S'IDP transaction sequence is similar to the interrupt (IN1'R} sequence except that the interrupt level information is not required.
Nodes sdected by the S'IDP command must
· Stop issuing tran~actions as soon as possible.
· Remove posted interrupts by clearing the Sent ~nd Force bits in the user's interface and interrupt
control registers.
·
· Set the hard error interrupt enable bit in the VAXBI control and status register.
The Stop command should be assigned a low level of implementation to assure that the node
reaches the stopped state as soon as possible.
During the command/address cyde, the master transfers the foterrupt destination mask on lines BID< 15:00>, and the command on lines BII<3:0>. The information on lines BID<31:l6> is reserved. Parity is generated by the master and checked by the nodes.
The nodes, except for the present master, can arbitrate for the bus control for the next transaction
during the IA cycle. During the Dl cycle, the slaves transfer an acknowledge or no acknowledge
response to the master. A node must perform one of the following while proceeding to the stopped
state.
· Issue a retry response when it receives subsequent single-responder commands. · Issue a no acknowledge respons~ when it receives subsequent single-responder commands.
· Extend the S'IDP transaction by keeping thi;; BI BSY line asserted.
· BIIC Transaction Status Information
Significant events within the BUC or VAXBI bus are reported to the master-port and slave-port
interface through event code lines BCI EV< 4:0 >. These lines provide 32 event codes that are grouped into summary event codes that provide status at the end of a transaction, status event
codes that provide status during a transaction and special codes that indicate self-test status and bus timeout information. Table 38 lists the event codes class and type.
4-72
Confidential and Proprietary
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VAXBl787J2
Table 38 · VAXBI 78732 BCI Event Oode As~ts
Suauraary NEV MCP AKRSD RCR IRW
NICI
NICIPS
AKRE
sro
BPS
I CR SD
BBE
AKRNE4
AKRNE5
AKRNE6 AKRNE7 RDSR ICRMC NCRMC ICRMD RTO BPM MTCE
No event
M:info S:info M:info
Master-port transaction romplete
Admowledge ~ved,£9r slave ~<;l datlJ
Retry confirmatjon ~~~v~ £~ ~~~por~ coQllllanq
S:info M:error/utlo
!:error/info
I:info
Internal n.:3istef written Jc.·.
.;.· '
No acl.<nowledge or illeg?-1 confirmatjon .received for interru)?t
cNoom·anU~~lnodwk.i. d.g.e.o.f~<V·:~·.~·.·i·.· .·r· .ni.· a.·· t.l. .·.·~..·:.·~ived for Fo~-bit
·ro&siOr/stc:> .· in "p . . ...... . ............ tel')? ... ·.· ·.·.. ..·
co.m..·.·
t·n . t · n d .· . . · . ·
·
.
· · · . ·. . . . ·.·
·· ·.·
.
·
AckrioWtt.dge c0nfiimtltion tecei\red fur error vectOr
S:error
Stall timeout on slave transaction
S:error
Bad parity received during slave transaction
S:error
Illegal co¢irll!.8tion received for slave data
S:error
Bus busy error ·
·
I:info I:info
Acknowledge confuination receiVec1 for no~errorvector-level 4 Acknowleijge confli'~a1:ion recei*d for .nonerrorvept()r......:1eve1 5
I:info !:info M:error
Acknowledge confkmation recei.Jed for nonerror vedOr-level 6
rode Acknowledge eonfirmation received for notierror vectQt",..,.,.levd 7
Read data subStitute ot reserved status received'·
M:error
Illegal confirmation l'Cefived for iw.ster-port command
M:error/info No acknowledge con£A1nation received fQF master-port.Command
M:error · · Illegit ci>nfimtation.~ve&l)y t&a$ier:pc,rt: data cycle
M:error
Retry timeout
M:error M:error
Bad parity received during master-port transaction
Masteft~t etrorcheck
Status ARCR IAL EVS4 EVS5
EVS6
EVS7 BPR
M:info I:info !:info !:info l:info I:info M/S:error
Advanced retry confirmation received Error identification arbitration lost External vector selected-level 4 ;
External vector selected-level 5 · External Vector sqe~ed-level 6 · External vtK:tQr seleete4-level 7 Bad parity received
Special Case
B'rO
M:error
STP
info
Bus timeout
· Self~test J?assed
*M=master, S=slave, !=interrupt, info= information
Confidential and Proprietary
4-73
_____......__..,______,.____,_______.__""'"'__ u ±rmwwcrw
-~-1.!lli'_,_,-----~
1:
Preliminary .)
VAXBVi8132
Summary Event Code QpC~tioo_,.'iCQ,~. s.umn:iacy EVent. (EV) code indicates the successflll completion of a transaction ur an error condition resulting from a transaction with a node. The master-port interface receives one master summary EV codeJcir each transaction unless the transaction is aborted. The slave-port interface receives this code for transactions in which an error is detected and for successful read-type and identification transactions, and when information is written into the VAXBI registers from the VAXBI bus.
The summary EV code lines are shared·by the master and slave ports. The information is time· multiplexed with a transaction cycle dedicated to the master codes and a transaction cycle · dedicated to the slave codes to assure that there is no contention between ports for the information.
Figure 37 shows the summary event code timing for a successful write-type and broadcast
transaction of a longword. Figure 38 shows the event code iirlling for a successful read-type
transaction of a longword. When a bus error causes the transaction to abort, the event code may occur before the times indicated unless the transaction is intranode.
CYCLE
1
C/A
BICNFCODE SOURCE
. EVCODES
SOURCE
BCI RAK
2
3
4
5
6
IA
01
ACK Slave
ACK Slave
ACK Slave
SUM EV SUM EV
Slave
Master
Figure 37 · VAXBI 78732 Summary Event-WRITE and BDCST Longword Transaction Timing
CYCLE
1
C/A
Bl CNF CODE SOURCE
EV CODES SOURCE
BCIRAK -I!'...
2
3
4
IA
01
5
6
ACK Slave
ACK Master
ACK Master
SUM EV SUM EV Master Slave
v
Figure 38 · VAXBI 78732 Summary Event-READ Transaction Timing
4-74
Confidential and.!?roprietary
-
Figwe ~9 shows the summary event code timing for~ succe~sful S~P, INTR, !PIN.TR, andINVAL ~n from a $.ast¢r-pott. No ·event code IS ttansferredi by the slave port for these transactions. During the STOP, IPIWTR, and INVAL transactioosl fhe.atent code is tranSfetred during cycle 6. A no acknowledge or illegal confirmation received EV code is transferred during cycle 6 by unsuccessful IPINTR and INTR transactions generated by the BIIC.
CYCL.e
BICNfCODE
SOURCE
EV CODES SOUFICe
BCI RAK
Status Event Code Opeiation-Status event cod.es provide status information during a trmSac· tion. The bad parity received event codes (BPM and BPS) are transferred the cycle after a data cycle parity error has been detected by a slave or master node. This allows a write-type transaction to be terminated soon after the error has been detected. These event codes are also transferred at the end of the designated cycle. The INTR command results in two types of slave status codes-The external vector selected {EVS4 through EVS7) codes and the identification lost (IAL) code. The EVS codes are transferred during cycle 4 and the IAL code during cycle 5. Spedal Event Code Operation-The bus timeout (BTO) and selfoest passed (STP) codes are special event codes that are not related to a transaction. The BTO code .can be transferred during any transaction cycle except the data cycles of a master transaction from this node. Other event codes are transferred before the BID code. This code is then transferred continuously until the request(s) are removed or the transaction begins. The STP code is transferred after the BIIC has completed the self-test operation.
-
VAXBl'iS73i,'.
Event COde WinclaW$~The :interval of time that the, summary or status event codes can l?e
transferred is from cycle 4 of the transaction until cycle 3 of thefo~g transaction. The node is required to relate the transaction and associated event codes, Figure 40 shows thetransaction event
code windows.
CYCLE
1
2
3
4
5
6
7
8
9
10
CfA 1 IA
01 C/A2 IA
01
02 C/A3 IA
DI
Bl NO ARB
BiBSY
BCICLE
EV codes for ___ previous trans.
EV codes for-+t----ev COdes 1or---
transaction No. 1
transaction No. 2
Figure 40 · VAXB{78732 Transaction Event Code Windows Timing
Event Codes and Bus Error Register Most event codes that are transferred are dependent on the status of the bus error register (BER) bits. Figure 41 shows the relationship of the codes to the BER. The event codes are defined in
TableJ9.
4-16
Confidential lltld Proprietary
-
I
Preliminary
\
.l
Bus Error Register 81ts I
VAXBI787J2
Event Codes
BTO NICI NICIPS
STO
BPS ICRSO
N M
M
T c
c
T
A E E
J
J
j
M p
I s
E E
T 0
v I
F E
' -
c
p E
s
p
c
R A 01 T S' 0
,_, s
T 0
e
T 0
N e
x
c I
E
I
,.
I
.·
. '
'
:
J1
...:..
...:..
J1
,..J .
·'
:
..t ·,
.·r.·
.J
I
J
BBE ROSA
.""
F
ICRMC
·J NCRMC
BPA
-'
ICRMD
RTO BPM MTCE
J
..J1
' ·.
,J .. f '
t
, 1'
.
I . -J
~
J
"""
l
·.f·
L'
-"-
J
-J
J
KEY
Direct correlation between the output of the EV ci>de and the setting ol1'1e BUs Error ReQister bit
..J Same as for master pcilt interface transactiori$.ei1c11eneta{fd t~ons will n~Yfir C;a11$e !tie output of
Mtce cOde the
.i;,v
; ,: ', -
'
-
'
if the.
- <: '
error
''.
~l:-;).-Q:;.i:-t1iO;I'!
is:'Jletect·e:'d' .
'Th'.,e
MT',.,C·- E''
bit·~,
i'''
""----
' .
wilH1!!1
'
' ·,'
set.
.. Thi& EV
~~
code
re1>resent11
one
e.rror
GO!Jdl1ion, .
but.
not. the .
only
con.i. :U~.
111at
Will
result
ifl
'1fle
l!8fling
of
this
Same as Jtor illegal CNF respon~; however, this error bit will not be set if !he respofl$e Was NO ACK.
the This BER bit represents one error condition. but not the only condition. that will result In output tlf this EV
code,
Figure 41 · VAXBI 787J2 EventCodeand Bus Error RegisterCom!ldtion
Confidential and Proprietary
4-77
----.,.,,.------------------·--·--------·-rn··-----··----~--~·--·--···-~-·---
....
VAXBI'7S732
Table 39 · VA,XIU Event Code Descriptions
Event
Descriptlon
NEV:
No event reported (default deasserted state)
MCP
Indicates that the last master-port transaction on the VAXBI bus has been oompleted successfully. During nonpipeline requests, the MPC code is transferred
during the cycle in which the BIC RAK signal is asserted. If a master performs
pipeline requests, this code may appear during the C/A cycle or embedded ARB cycle. The master must associate this code with the related transaction. If a stop
transaction selects the slave-port interface of the master, no summary event code
will be sent.
AKRSD
Sent from a slave to indicate that the last read-type transaction was successfully · completed.
B1D
Indicates that a node was unable to start a transaction within 4096 cycles after a
request from the BIIC or a master-port interface had been posted. Sets the BTO bit
in the bus error register. After the bus timeout, the BTO event code is transferred
until all requests are completed or a transaction occurs.
STP
Indicates that the BIIC self-test has been successfully completed.
RCR
Indicates that the confirmation received from the slave during the C/Acycle from a
slave or master has occurred previously (retry).
IRW
Indicates the completion of a VAXBI write-type transaction that was directed to the
BIIC control and status register space of this node.
ARCR
Used by the master-port interface to support pipeline requests. This code is transferred by the BIIC during the the cycle that follows the receipt of the retry confirmation. Because this event code is transferred one or two cycles before the retry confirmation received event code, it is useful in support the master-port design of pipeline requests.
NICI
Transferred if the confirmation received for an Intr transaction is a no acknowledge code, reserved code, or an illegal response code.
NICIRS
Transferred for IPINTR or STOP c;ommands that are initiated by setting the IPINTR/STOP bit in the BCI control and status register.
AKRE
Transferred after the slave receives an acknowledge confirmation from the identifying master for the transmitted error vector information from the slave.
IAL
Transfei:red by the BUC two cycles after th.e identification arbitration was lost by
the slave.
.
·
EVS4-EVS7
Used to solicit an external vector from the user's interface when the BIIC participates in the identification arbitration, when the EV bit is set in the interrupt control register of the user's interface, and when no error interrupt is pending at this node at a level selected by the IDENT command.
STO
Transferred if the user's interface stalls a data cycle for more than 127 consecutive
cycles. A node that is not a slave will receive this code if it extends a VAXBI
transaction for more than 127 cycles.
4-78
<:;qnfidential and Proppetary
Event BPS BPR
ICRMD
BPM MTCE
rra1ls£¢rred if a slave detects a parity error during · write-type acknowledge or stall
cycle or during a broadcast acknowledge data cydd. This coitdition sets the SPE bit in the bus error regis~
Transferred by a master or slave during the cycle after the BllC dettx:l:s a parity error
during the following data cycle types:
· ·
'
-Rea.d-cype acknowledge,(for the master)
-Vector acknowledge (for the master)
-Write-type acknowledge or stall (for the slave)
-Broadcast.acknowledge.(for the slave)
ana Transferred by theBttC during read~type, \Vrite"type; broadcast transactionsif
the slave returns an illegal confirmation codeaftetthe command confirmationhlls
been received.
Transferred by the master for each retry resPQOSC: after 4095 retries from the sl~e when the RIDEVEN bit is set in the BCI co~l·~ status register.
Transferred when the master detects a parity error on theVAXBI bus during a read-
type or vector acknowl~e data cycle.
·
Transferred for master-port transactions when the data received ob the
BID< 31;0>, Bil <3:0> and~ lines is not the same as the data transmitted
from this node. This occurs during a. cycle in which the .master should be the only node to transfer information on these lines except when encode ID of the master is transferred during an embedded arbitrationcycle. The BITCalscfsets the MTCE bit
in the bus error register.
· BIIC Operation
The following describes the operation of the BIIC during powerup sequeri.ce and during VAXBI
transactions.
Powerup Sequence· During the powerup sequence, the BIIC disables the VAXBI driver circuits, loads the configqration information from the user'.s interface into the BijC registers, and per£orJU~ a self~test operation.
The BIIC asynchronously a~rts the BCl DC LO s.iggaLwhen BtPC 1,0 is ~setted< Infonqation from the BCI D < 31:00> lines isloaded into the dwipe register; the node 11) inft>rmation £rom the BCI I <:;:0 > lines is k:laded into the V~I,;control an& s~tus regi$ter, and the state of the BCI PO line is loaded into the user parity enable (UPEN) hit of die bus em>r register. The state ofthe BCI PO
line determines if the BIIC or user's interfacewill ge~te parityfor the data transferred from the
BIIC.
Confidential and .Proprietary
4-19
VAXBI 78732.
Self-test Operation The BCI DCW line must be asserted for a minimum of 72 cycles (14.4 microseconds) to allow the BIIC to initialize the registers associated with self-rest. When the BI DC LO line is deasserted, the
BIICdeasserts the BCI DC LO line and starts the self-test. The BI NO ARB line is asserted during
the self-test operation to prevent VAXBI bus activity. After the self-test has been successfully
completed, the BIIC transfers the EV code (STP) for one cycle during the cycle after the self-test completes. BI NO ARB is not asserted during the node reset sequence. The user's interface can monitor this code or can read the VAXBI control and status.register to determine the results of the self-test. Table 40 lists the status of of the BIIC and user's interface signals during the self-test operation.
BIIC asserted lines BCID<31:00> BCII<3:0>
BCIPO BI NO ARB**
Table 40 · VAXBI 78732 Self-test Signal Status
BIIC deasse:rted lines
User asserted
lines"
BCIMDE
BCIRQ<l:O>
BCISDE
BCINXT
BCIRS<l:O>
BCICLE
BCIMAB
BCISEL
BCISC<2:0>
BCIEV<4:0>
BID<Jl:OO>
*These lines are optionally asserted. During the self-test, the diagnostic mode code should not
appear on lines BCI RQ < 1:0> to prevent the termination of the self-test before completion.
**The BIIC asserts the BI NO ARB signal during powerup self-test but not during NODE reset self· test.
Retry State
The BIIC enters the retry state in response to a legal retry response code from a slave during readtype, write-type, and identification transactions. The BIIC transfers the RCR event code and stores the command/address information of the trahsaction and the first data longword in its buffers during write-type and broadcast transactions. When the user's interface deasserts and then reasserts the request, the BIIC reinitiates the transaction. This provides the node with a variable delay before the transaction is initiated again. Nodes can initiate a retry transaction by disabling the VAXBI transaction request with the RCR event code.
After the BIIC receives 4096 consecutive retry confirmation responses, it issues the RTO event code. The user's interface can then ~ontinue to retry the transaction and the BIIC will continue to transfer the RTO code each time it receives a RCR response for the recent transaction. The user's interface must assert the BCI MAB line to terminate the transaction.
4-80
Confidential and Proprietary
-·
Request Codes
i
The ,anc monitors· the state of the request lines to determine if a transition has occut:red. It
compares the received state of the line from the previous cycle with fhe received state of the current
cycle. The transitioD1of the request lines from the deasserted state. (po request) to the asserted state
(a request other than diagnostic mode) is interpreted as a request. The ·reqlleSt code .on the BCI RQ < 1:0 >.lines can b,c removed during any cycle after the assertion of the BqJL\I( sig~ by
the BIIC. A new request will not be recognized by the BllC until the request lines have been
deasserted for at least one cycle. Therefore a new request cannot be presented until l;he second cycle
after arequeSt has been removed.
When the BIIC receives' a VAXBI reqQest, it initiates theh~s arbifull:jo11forthe.new tni.nsaction as soon as posible. If the bus master simultaneously ipitiates a nevn:eque~t, the BIICwUJ arbitrate for the new request in the neit available cycle after the last cyd~of .~ prese~t ~n.
to Api~ne reqi.iest is a ~uest i>osted pd.or the cJnssertionpf~BCI Mk's~Jp.r the p~nt
master-port transaction. Figll11! 42 shows.the sig~ timing £9.r.thepi~e ~~11.ts tha.t ~ow the
ma,ster-port in:tetface to transfer data at a.tlm;iug,hput i:ate of 11.4.MhYtes.pc:r. second.
CYCLE BC! RAK
1
2
ARB
C/A
BClRQ 0
I Earliest cycle in which a new
reqtrt 'l"~Y be ~,~rted
Earliest cycle in which.a
.·
·.·
request may be deasserted
·
I
I
Figure 42. VAXBI 78732 Request Signa!Tiinmg
VAXBlhtsaction R.equest,..-The master-po,rtinterf11ee use~ theV~I transaction requ~s~ ccx:ie
dUected to request transactions on the VAXlU
bus or to the slave node on the same
bVuAsX. BTIhien'tterarfnascaec.tiOonnslycalnon~;i~f:.ds
to \)thl!r nodes
can be transferred
O~Jol
the the
slave port.
All VAXBI commands can be initiated by the user's interface except for the interrupt command. Interrupts are initiated by asserting a BCI INT<7:4> line or by setting a force-bit in the user's interface interrupt control register in the BIIC. The interprocessor interrupts can also be initiated by setting the IPINTR bit in the BCI control and status register.
Loopback Requests-The master-port interface uses the loopback request code to initiate
longword intranode read-type and write-type transactions to node spaces that do not require the use of the the VAXBI data lines. Loopback transactions permit fast access to the BIIC and slaveport registers regardless of the activity on the VAXBI bus and during some bus failures. A oode can access its node space registers without reference to the node ID. During loopback transactions, the
BIIC disables the VAXBI drivers except for the BI NO ARB and BIBSY lines, and the transaction
data is looped back to the VAXBI bus receive logic.
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Loopback transactions and VAXBI bus transactions can occur concurrently. A loopback transaction can occur at one node while two other nodes are performing a VAXBI transaction; To assure proper bus operation, however, the BIIC will not initiate a loopback transaction when another node is initiating a VAXBI transaction. Because loopback transactions extend the bus cycle, the system access latency may be degraded.
Loopback transactions are received by the BUC similarly to VAXBI transactions except for the following:
· High-order address bits on lines BI D < 29:13 > are ignored by the address selection logic of the
BIIC except for parity qualification. The BIIC completes the transfer the same as if these lines contained the value 10 0000 0000 OOOn nnn (hexadecimal): where n nnn is the ID of this node. The address transferred to the slave port interface will be the same as the address received by the BIIC from the master-port interface. Read-type and write-type loopback transactions have limited addressing capability because the node ID is not required. The user's interface can access only the node space within the node that connects to the user's interface. Addresses defined by the starting and ending address registers of the BIIC can be accessed only by VAXBI transaction requests.
· The BIIC does not arbitrate for the bus and VAXBI transactions are not generated. If the bus is idle, a loopback transaction begins two cycles after the loopback request is initiated. The BI NO ARB and BI BSY lines are asserted during the command/address cycle of the loopback request to assure that no other BIIC will interpret this request as a VAXBI bus transaction. Asserting these signals extends a current VAXBI transaction to allow the completion of the loopback transaction. If a VAXBI bus transaction has been initiated, the node with the pending loopback request waits to verify that it has not been selected for the VAXBI transaction before processing the loopback request.
· The dual round robin arbitration priority is not updated by the BIIC during the embedded arbitration cycle of the loopback transaction.
Diagnostic Mode-This mode is reserved for Digital and is used in the development of bus testers,
bus monitors, and other diagnostic equipment. It facilitates testing of the BIIC and provides access
to the VAXBI bus. Refer to the VAXBI Systems Reference Manual for detailed information on the
diagnostic mode.
The BIIC supports the BCI-to-BI and BI-to-BCI transparent mode operations where the BCI signals are reassigned to correspond with the VAXBI bus signals except for the BI AC LO and BI DCLO signals. The assignments and state of the signals are shown in Table 41.
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BCIJ.hte D<31:00> 1<3:0> PO EVO
EVl
EV2 EV3
EV4.
VAXBI 78~12
'.18ble 41 · Diagnostic Mode Bus Signal A~signments
State
BIUne
inverted
n.q:J1:00>
inverted
1<3:0>
inverted
PO
not inverted
CNFO
not inverted
c~i
not inverted
CNF2
not inverted
N04JlB
not inverted
BSY
. In the BCI-to-BI transparent mode, the user's ini:erface transfers <liilll on tlie BCl D <.lj:OO > , Bq I< 3:0 > , and .BCI PO lines with.. the norrnal setup tirne and th~'. qata is synchl'()nously
transferred to the VAXBI bus by the BllC.
In the BI·to-BCI transparent rnode, the data re<.:eived fn;>m,theVAXBI bus is Jatclied: duril;lg each cycle and transferred: to the BCI lines by the BIICduring each cycle:. Data is transferred: to the BCI
in the same timing ~uence as a nontransparent mode.
The diagnostic mode supports a command that allows the loadtitg of the device type, node ID, and parity mode ififormation at the end of the assertion of the BCl DC LO signal.
During the diagnostic mode, the BIIC examines the BCI interrupt and response lines
BCI RQ < 1:0> to determine the diagnostic mode operation: The code on these lines must'not be
transferted until the BIIC completes the self-test. The diagnostic mode control signals on lines
can BCI RQ< i:O >, BClRS < l:O>, and BCI INT< 7:4 > may be transferredduring the samecycldn
which the BIIC is set to transparent mode. The operatlng mode be changed by the
BCI RS< 1:0 > and BCI INT< 1:0 > lined without deasserting the BCI RQ < l:O > lines. The new
operation begins within three cycles after the mode change. Table 42 lists the response codes for
the diagnostic mode.
·
BCIRS Line
1
0
H H
H
H
H
L
L
L
18ble 42 · VAXBI 78732 DiagnosticMode.OpetatiogCodes
BCIINTLine
7 H
6 H
' 4
H ·H
~tion
NQ operation
L
L
L
L
BCI-to-Bltransparent mode
H
L
H
L
Load configui:ation data
L
L
H
H
BI~to,BCI transparent mode
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Read-type Transactions .·
During master-initiated read-type transaction; the master-port interface requests a VAXBI transac-
tion through the BCI RQ < 1:0 > lines. The BIIC responds tO this request by asserting the
BCI MDE signal to indicate to the master that a VAXBI command, address, and parity information (for user-generated parity) should be transferred on the BCI lines. When the BIIC wins control of the VAXBI bus, it transfers this information to the bus and asserts BCI RAK line. The asserting edge of the BCI NXT signal indicates when valid read data is on the BCI lines. If a STALL command is received from a slave, the assertion of the BCI NXT signal is delayed until an acknowledge is received. Following the last data cycle, the BIIC issues two acknowledge confirmations on the
VAXBI bus if the transfers were successful. The final acknowledge can be inhibited by the user's
interface if it asserts the BCI MAB signal. The MPC event code is transferred during the cycle that
the final acknowledge is on the VAXBI bus. The BCI RAK line is also asserted at this time unless the master port issues a pipeline request.
All BIIC nodes deassert the BCI CLE line during the embedded arbitration cycle to allow the data
from the BCI to be loaded into the BIIC. Each BIIC determines if the transmitted address is within the range of addresses that are allocated to its node. The BIIC in the selected node asserts the BCI SEL line and issues the appropriate select code on the BCI SC<2:0> lines. The command
response of the slave must be transferred on the BCI RS < 1:0 > lines before the end of the
embedded ARB cycle. An acknowledge response is a positive command confirmation and indicates to the masterthat the data cycle in process contains valid read data. During a read-type transaction, a stall response indicates that the data is not valid, a retry response indicates that the command
cannot presently be completed, and a no acknowledge response indicates that the node was not
selected by the transmitted address. The slave provides read data, data status, and responses continually until all data is transferred from slave to master. At the end of successful transactions, the BIIC of the master node transfers two acknowledge responses on the VAXBI bus.. The BIIC of the slave node responds with a AKRSD event code during the cycle following the final acknowledge
response of the BIIC.
The BIIC controls the read transactions with its internal registers. The user's interface, however, can monitor the read transactions of its node ~pace if the BCISREN bit in the BCI control and sqitus register was set. When a successful read-type transaction to an internal register of the BIIC has been performed, the BIIC issues an AKRSD event code.
Write-type Transactions
The master-port interface requests a VAXBI transaction on lines BCI RQ < 1:0 > . The BIIC
responds to this request by asserting the BCI MDE line to indicate to the master that a VAXBI
command, address, and parity information (for user-generated parity) should be transferred on the BCI lines. After the BIIC wins the VAXBI bus, it transfers this information to the bus and asserts
the BCI RAK line. During the embedded arbitration cycle,· the assertion edge of the BCI NXT
signal indicates that the first .data word should be ready for transfer to the bus. During the same cycle the BIIC asserts the BCI MDE line that transfers the first data longword from the user's buffer
to the BCI bus. The BCI NXT and BCI MDE signals transfer each data word during a cycle until the transfer is completed. An additional BCI NXT cycle occurs at the end of this transaction if the
pipeline NXT enable bit in the BCI control and status register is set. After the last write-data cycle,
the slave transfers two acknowledge responses. The BIIC then issues an MCP event code to the user's interface and in the same cycle the BCI RAK line is deasserted unless a pipeline request was issuedfrom the master-port interface.
All BIIC nodes deassert the BCI CLE line during the embedded arbitration cycle to allow the data from the BCI to be loaded into the BIIC. Each BIIC determines if the transmitted address is within
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I
the range of addresses that are allocated to its node. The BIIG in.the selected node asserts the BCI SEL line and issues the appropriate select code on the BC~ SC< 2:0> lines. The command
response of the slave must be transferred on the BCI RS < i:P > lines before the end of the
embedded ARB cycle. An acknowledge response is a positive comimandconfirmation and indicates
to the master that the data cycle in pi;ocess contains valid read cl,lita. .N,stall response indicates that
the data from the first data cycle should be rePeated in the second data cycle. A retry response
indicates that the command cannot presently be·completed.'A ho ackrlbwledgeresponse indicates
that the node was not selected by the address transferred.
The slave-port interface provides an acknoWf&ige br stall resp(>nse f¢ each data cycle until all the datais transferredfrom master to slave. At the ~d df succ~sful.transactioris, the BilC of the slave
nOde transfers two ackrtawledge responses on the bus and the :imc ohhe muter node. responds
With a MCPevent code d.iirihg the cycle foll0wing the firull acknowledge response of the slave.
The BIIC controls the write transactions with ,it$ internitl. regist~rs. !'he u~'s interface however
can monitor the write transactions if the BCISREN bit in the BCI ~011trol ani:l statu$ register is set.
A write transaction to an j,nterna.1 register or to !l. ~ is simila,r ~t that .the information on the
BCI RS< 1:0> lines has no effect on the ccmfiimation ~spons~ of the BIIC, When a successful
write-type transaction to an internal register of the l3llC has been performed, the BIIC issues an
IRW event code.
lnrerrupt and Ideritification Tmnsactions, The BIIC can generate a u~er's interface inten;upt bl," an error interrupt by transmitting an INTR command on the VAXBI.bus. Error interrupt requests have the, highest priority for transaction transmission and in response to.IDENT commands.
The user's interrupt is initiated bythe interface whenit asse~ts one of the BCIINT < 7:4 > lines or when it performs a write transaetion to set the appropdate ifiterrupt force-hit fo the.user's interface
interrupt control register.
The error interrupt is ~litomatically generated by the BIIC when ~bus error is detected and the hard
error interrupt enable (HER) bit of the VAXBl control and status !;li:gister is set. The user's interface
can also cause an error interrupt by setting the interruptforce(INTR force) bit in the errorinterrupt
control register.
Following an interrupt request, the BIIC arbitrates for the VAXBI bus and, after winning the bus, it initiates the interrupt transaction. The user's interrupt and error interrupt use ·.the INTR destination register to select a node. During the command/address cycle of the interrupt
transaction, the appropriate INTR Sent bit is set inthe user's interface interrupt control register or
the error interrupt control register.
If more than one interrupt level is pending for the user's interface, the BIIC will transfer an interrupt request with all interrupt levels indicated when the VAX.BI bus is availible. Because only
the INTR Sent bit of the highest pending level is set, the BIIG "Yill arbitrateforthe VAXBlbus again to send the remaining levels of the pending interrupts. The BIIC transmits the INTR command
without interrupt levels if the interrupt condition is removed and the user's interface deasserts BCI
INT< 7:4 > one or two cycles before the arbitration cycle has occurred.
Slave nodes capable of receiving interrupts should set the appropriate interrupt pending bit or its
> equivalent to recott! the in,terrupt level received. This information is transferred in the level field on
the BCI D < 19:16 lines during the identification command/address cycle. When the interrupt
command is not successfully received, ,the BIIC sets the INTRAB and INTRC bits in the user
interrupt control and status register at the levels received during the interrupt command. The INTRC bit prevents idditional interrupts at that level from being transferred. Therefore this bit
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VAXBl18732
must be cleared and reset by a node to again initiate an interrupt request. TheINTRC and INTRAB bits can be cleared by performing a write transaction to the interrupt control register.
The node that receives the interrupt request issues an IDENT command to obtain the vector
information from the node that initiates the interrupt. The !DENT command is initiated by the master-port interface to request a VAXBI transaction. The identification level information consisting of only one level bit is provided by the user's interface for transfer during the !DENT
command cycle.
· All slaves with interrupt requests pending at the same identification level will participate .in IDENT
commands by verifing that the decoded master ID transferred during the third cycle is the same as the bit set in their interrupt destination register: When both condition exist, the node participates
in the identification arbitration. User's interface data froqi the slave port is not required unless the
external vector bit of the user interface interrupt control register is set. The BIIC can transfer an
external vector selected event code (EVS7 through EVS4) during the identification arbitration
cycle if required.· The event arbitration lost (JAL) event code causes the slave-port interface to
return to the idle state. The use of this code is shown in Figure 43. Nodes that use external vectors
must stall the vector transfer for a minimum of one cycle.
VAXBI ACTIVITY
CYCLE
1
2
3
4
5
6
7
B
DECODED
MASTER !DENT STALL ACK
C/A
IA
ID
ARB VECTOR VECTOR
"'-I
BIBSY SOURCE. M3
M3
M3,S1, M3, 51, S1, 52
S2
S2
I/
52
v "- Bl NO SAORUBRC~ M3
M3
M3, S1, M3, $1,
...;1
$2
S2.
Bl CNF Code
SOU RC E
STALL SI
ACK $1
ACK M3
ACK M3
BCI ACTIVITY
ST-Slave that wi~s IDENT A~B
I
I
I
I I
SLAVEBCIRS <1:0> <NOACK><NOACK><NOACK><STALL><ACK><NOACK><NOACK><NOACK>
EV Sn
AKRNEn
S2-Slave that loses !DENT ARB SLAVEBCI RS <1:0>· <NOAC°K><NOACK><NOACK><STALL><STALL><NOACK><NOACK>
EV<4:0> L
EVSn
IAL
+S2 slave port
interface returns to an idle state
I
Figure 43 · VAXBI 78732 Identification Transaction Event Code Timing
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The winner of the identification arbitration transmits the interru~t vector. The .slave-port interface
can stall if the vector is not iinmediately available. After the masteti of the identification transaction
has acknowledged that.the vector was received, the BIIC transfers an evc:nt;eode (AKRNE7 through
AKRNE4) and the INTRC bit in the user's intetfa<:e interrupt control l'egister is set. The slave-port interface can decode the class of the event and use these ~· to deassert the appropriate
interrupt request. User's interfaces that gate multiple interrupt S®tees onto one interrupt request line can prevent the loss of a request when thf! request )ine isdea~ert!d by clearing the INTRC bit
after the interrupt is serviced. If a vector transfer to a master tails!and the master does not transfer
the final acknowledge, the slave-port interface t~fqrs~UJegi4 confirmation received (ICRSD) event code. The BIIC automatically resen(ls thein~'if'fh.e ~terrupt request is still pending and the master may request the same vectdr in sub$equent ident~ation transactions.
l
Interrupt Sequence Figure 44 shows the interaction of the BIIC and the user's interfaF to the INTR transaction. Refer
to the VAX.BI System Reference Manual for detailed transaction irlformation.
I
(
I
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4-87
i
I
. ----··----------·-·---,.,...j_____ ---·-····------~-·--·---:
.OSER INTERFACE REQUESTS AN INTR BYSETtlNG
INTR FORCE BIT
NODE 1
USER ll'fTERFACE flEQUESTS AN INTR BY ASSERTING AN . INTEFlFlUPT SIGNAL (INT 7:4)
DE 1
VAxBI787)2
BllC SENDS AN INTR AND SETS INTR SENT BIT
NODE 1
NO
YES
SLAVE USER
®
INTERFACE(S) SET
INTERRUPT PENDING
BITS AT THE
INTR LEVEL(S)
NOOE2
BllC SETS INTRAB BIT AND INTRC BIT
NODE 1
@
WAITS FOR IOENT
NODE 1
NODE 1 Node sending the INTR NODE 2 Node responding to !he INTR
Figure 44 · VAXBI 78732 BIIC and User's Interface INTR Sequence Flow Diagram
Identification Sequence Figure 45 shows the interaction of the BIIC and the user's interface to the IDENT transaction. Refer to the VAXBI System Reference Manual for detailed transaction information.
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SENDS IOENT.
U$ERIN'TERFACE
RESETS INTEAAUPf
PENDING BIT
AT THE IOENT
LEVEL
NODE2
VAXBl78~}2
WAIT FOR NEXT IDENT NODE 1 ·
@
enc RESETS
INTR SENT BIT
AT THE IDENT LEVEL
I
NODE1
YES
TRAN$MITS VECTOR
(ErrHl:ft INTERNAL
OR EXTERNAL) NODE 1
NO
BllC RESENDS
INTR
YES Ii .
@
BllC SETS INTRC BIT.
NODE 1 Node that sent the INTR
NODE1
NOOE 2 Node responding to the INTR
I
'
Figure 45 · VAXBI 78732 BIIC and User's Inteiface IDENT Sequence Flow Diagram
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Interprocessor Interrupt Thmsaction Interprocessor interrupt (IPINTR) transactions can be initiated by the master~poi-t; .interface by
requesting a VAXBI transaction and issuing an IPINTR command in response to the assertion of the BCI MDE line. The user's interface must then provide the decoded ID of its own node and the destination mask.
The IPINTR transaction are also initited by the BIIC when the user's interface sets the IPINTR/ SIDP force-bit in the BCI control and status register using the destination mask froQ:l the IPINTR destination register. The force bit is cleared by the BIIC after the transaction has been completed. If the transmission fails, the NICIPS event code is transferred and the NMR bit of the bus error
register is set.
A node is selected when an identification match occurs between the decoded master ID and the corresponding bit is set in the IPINTR mask register and between the nodes decoded ID and the
corresponding bit in the IPINTR destination field. A slave node that is selected will set the bit that
corresponds to the decoded ID of the master in the IPINTR source register,
Broadcast Thmsactions
Broadcast (BRCST) transactions are reserved for use by Digital Equipment Corporation. The BIIC responds to these transactions similar to read-type transactions. However, the stall and retry confirmations are not valid for this multiresponder transaction. The stall code can be transferred on the response BCI RS< 1:0 > lines to extend the time of the transaction by keeping the BCI BSY line asserted. The stall code produces an acknowledge on the BI CNF<2:0> lines during cycles where an acknowledge confirmation from a slave node is on the VAXBI bus. The BI BSY line is asserted during all cycles. If the stall code remains after the last confirmation cycle, no information remains on the confirmation lines and the BI BSY line remains asserted.
Stop Transaction The SIDP command is initiated by the master-port interface. The user's interface provides the
destination mask and SIDP command code to be transferred during the command/address cycle. A slave is selected when the ID decoded by the slave matches the destination information of the
INTR destination register. The slave-port interface provides the command confirmation· on the
BCI RS< 1:0 > response lines and the slave is .initialized.
Invalidate Tumsaction
Invalidate (INVAL) commands are initiated by a master-port interface. When the BCI MDE line is
asserted, the user's interface provides an address and data length code that indicates the number of
longwords to be invalidated. Slaves that have the INVALEN bit set in the BCI control and status
register are selected for this transaction.
.
Reserved Commands
Reserved commands are recognized by the BIIC as three cycle VAXBI transactions consisting of a
command/address cycle that contains user's interface data, an embedded arbitration cycle, and a
data cycle in which the data lines are deasserted. The master requires an MCP, NCRMC, or ICRMC
acknowledge event code from the slave. A slave can respond to a reserved code of (HLHL) or
(HLHH) on lines BCI I< 3:0 > if the reserved enable (RESEN) bit is set in BCI control and status
register. The slave responses to the reserved commands can be an acknowledge, no acknowledge or
stall on the BCI RS< l:O > lines. The event codes used are bus busy error (BBE) and stall timeout
on slave transaction (SID).
.
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VAXBI78732
Transaction Priority
The BIIC recognizes more than one pending request. A VAXBI t~saction request, an error
interrupt request, an interprocessor request, and a user's interfacb interrupt request may be pending simultaneously. The priority for processing multiple request~ is listed in Table 43.
'
Table 43 · VAXBI 78732 'l'rabsaePon Request Priority tssignments
LPervioerlity Request
I
.
I
1
Loopback from master-port interface
2
Interrupts (INTR) controlled by error interrupt control register
3
Interrupts (INTR) from user's interface' interrupt control regfsteror BCI INT l~ne (level 7)
4
Interrupts (INTR) from user's interface interrupt control reaister1or BCI INT line (level 6)
5
Interrupts (INTR) from user's interface interrupt control registeror BCI INT line (levd 5)
6
Interrupts (INTR) from user's interface interrupt control register or BCI INT line (levd 4)
7
VAXBI transaction from the master-port interface
8
Interprocessor interrupts (IPINTR) froi;n the BCI control a~ status register.
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-···-···-··-·-··--··-···--------·--·-------------------"""'
VAXBl78732
Figure 46 shows the types of requests and the timing relationship between th<( .Posting of die
request and the priority assignment by the BUC. The BIIC examines !lhe request and establishes its
priority during the prioritization cycle.
. .
·
IPINTR FORCE BIT SET
E1NTRCSR OR UINTRCSR FORCE BIT SET
INTUNE ASSERTED
LOOPBACK REQUEST
VAXBI TRANSACTION REQUEST (2)
PRIORITIZATION CYCLE
-
BllC PRIORITIZES REQUESTS
(1)
ARBITRATION CYCLE
NOTES: 1. Loopback transactions have a dummy ARB cycle at this point. 2. If the VAXBI transaction request is posted while other types of requests are present, the BllC
prioritizes the VAXBI transaction request along with the other requests during the prioritization cycle. However, if no other types of requests are present, the BllC attempts to arbitrate in the next cycle.
,Figure 46 · VAXBI 78732 BIIC Transaction Priority Sequence
When no requests are pending, the BIIC arbitrates the VAXBI transaction request in the cycle that follows the request to minimize the bus latency time. If a VAXBI transaction request is posted while other requests are present, the VAXBI transaction is assigned priority together with the other requests during the prioritization cycle.
· Transaction Timing Sequences
Figures 47 through 74 are functional diagrams that show the timing sequence of the signals used to perform VAXBI interface transactions. The signals that communicate with the VAXBI bus are prefixed with a BI designation and signals that communicate with the user's interface are prefixed with a BCI designation. Table 44 lists the figure numbers and captions that includes notes that define the transaction operation.
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Table 44 · VAXBI 787.32 Functional Timing Diagram Descriptions Condition
48
Loopback lorlgword
read-type
To BIIC CSR space with an idle bus and with BICSREN set.
49
Loopback longword
read-tyjJe with Stall
Occurs within node on top of a longword read with a stalled VAXBI tran§action between master-port interface and node 1 and the slave-p()rt.interface and node 2.
52
Quadword read-type
Ma.Ster quadwbrd read to same slave node.
with pipeline request
59
Force-bit requested
interrupt
An INTR transaction initiated by a force bit in the OINTRCSR·..
62
Force-bit requested
a An IP~N'l'R transaction initiated by foree bit in the
interprocessor interrupt· UINTRCSlt
66
Stop
.Indicate~· the..~ults ot one allowable response to a STOP
command. Although BIIC 2 wins the imbedded ARB in cycle
5, it asserts 'Bi NO Aim in cycle 6 because of the S1DP
com,rnand. Ifu&er .2 holds BC! REQ asserted, BIIC 2 would
arbitratelh cy'ele 7and continue the transaction.
67
Stop with extension
Slav~-port interlace illjtiates a stall response to assert BI BSY signal while node completes Stop operation.
69
Burst-mode write
Begins at first arbitration cycle won by this node after the
operations with pipeline BURSTEN bit of BCICSR was set by previous transaction. A
request
quadword write is follp~d .by a longword write to the
BCICSR_to clear BµRSTEN'bit.
70
Burst mode writes with BCI CLE is asserted in a cycle follo\1ling a cycle with
pipeline request and
BI NO ARB asserted and BI BSY deasserted and until T0 of
PNXTEN bit set
the command /address cycle.
71
Special case 1
1. Master 1 wins arbitr'.ttion and initiates a quadword WMCI transaction to slave.
2. Master 2 requests the bus, arbitrated in the embedded arbitration cycle, and becomes the pending master.
3. BIIC 2 receives command/address data from master 2 during the embedded arbitration cycle to avoid BCI bus contention.
4. Master 2 performs a longword WMCI intranode transfer to an internal register in slave 2 (intranode transfer).
72
Special case 2
Master 1 initiates a longword read-type transaction to its slave port interface (slave 2)
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Figure Title
73
Special case 3
74
Special case 4
Preliminary
VAXBl78732
Condition
1. Master 1 and master 2 arbitrate in cycle 3. 2. Master 1 wins the arbitration and initiates a quadword WMCI transaction to slave 2.
3. Master 2 arbitrates again in the embedded arbitration cycle of master 1 and becomes the pending master.
4. BIIC 2 receives the command/address data from master 2 during the embedded arbitration cycle to avoid BCI bus contention.
5. Master 2 performs a longword WMCI intranode transfer to an internal rewster in slave 2.
1. Master 2 win~ the arbitration and initiates a quadword read-type transaction to slave 1. 2. Master 1 requests the bus, arbitrates during its embedded arbitration cycle becomes the pending master.
3. BIIC 1.cannot receive the command/address data during the embedded arbitration cycle and waits until BCI SDE is deasserted in cycle 7 before asserting BCI MDE. 4. Master 1 performs a quadword read-type transaction to slave 3.
Table 45 lists the abbreviations used on the functional timing diagrams except for the event code abbreviations. The numbers that follow designations M, S, USER, and BIIC are node identifications (ID).
4-94
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VAXBI 787:J2 'f,abJe 4j · VADI 78732 Timing Diagram Abbreviations
AAN AAS ACK
ADR ARP CMD DAl DMI DSI DSM .
IDD ILV
INTR REQ
LB REQ LCD
M MID MKl NAK REC RES RET S STA STS USER UDF VAXBI REQ VEC VST WS *item*
all arbitrating nodes all arbitrating slaves ·
acknowiedge confirrriationtode
address including data lengfu,fie}d
ABRpattem (decoded ID from.ru,1 arbitratillg nodes)
command
data word 1
decoded mast.er ID
decoded slave ID on lines Dk 3l;t6> from all~tbit~tjng nodes destination mask indudingl~~eld1£t)r BQCS1' .~mand master ID a:nddestination code identify level(s) on lines D< 19:1~>
interrupt request . loopbai::k request leveland destination code master node master ID write mask l no acknowledge confirtrultion co9e retry confirmation received for master~port command
reserved
retry confirmation code
slave node
stall confitmation code read status code user's interface undefined data VAXBI request identify vector identify vector status winning slave the potential occurrence of an item that is not shown on the diagram
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Figure 53 · VAXBI 78732 Quadword Read-type (Pending master) Transaction Timing Sequence
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Figure 54 · VAXBl 78732 Quadword Write transaction Timing Sequence
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-···1'···- ···~ ...~t--·t·······t·--···l....... ···- IOUfct - ·······
81 H<2:0) l
Mllfct
.
I
I l'-~- I · 52
-··-1··-· -··· .......
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I ·: l
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la I
l ,' I 10 I 1l 1 112 I 13 I 14 I
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1 -·- _;--<! )·-<G .>···i >·-\ll S/.,..,\t······ l__ bl c2 bi c2 us 2 bl ca .
.....
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c2 bl
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-··
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----
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··---,-·t·--··-···
-----:~--.............
_-"8_-_t*-_r_
·····t~t··--···r······
............. . ..,.,......... _....... . ..._.................
!
... ..... _...
... .... -..
.......-··-- ..........-....
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.J- + ' lIClCI lNllCETLL
BC! ltl8 l
-
--·------
---·-------·-+--tt-r---·-··-----·-·-:·t-'----·-·-··--····-t·-tI-··.·'=·-=--={i r···-··-···-·--·--·~·i'-t.-·.·-.·.·-.·.-·.t-~I·;.--.·.·--.-.--.-·.tjl.--.-.·-.·-.--.--.-.Ll+·-··-.--.-·.·.·.ttI·-·········-·---~~.-----·-·--··-··-t··-·-----·---~---!-----------·--------+·I
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I ro 1·: I !2 **SUM:**
1 I
I
l
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II ~ I
·
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l
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I
I
I
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114 J
I 1
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m . . . . . , . \ b~c2 ~g;e IDUTC9 ··
· · · -' f · · - i'·f·--<
I ·
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r····b\Rl l(eit/-··\+····-·t'····-·t·······t' ·······1t·······1t······+-····t
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! BC!
~ ::
BC!
SC:!
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Figure 66 · VAXBI 78732 STOP Transaction Timing Sequence
Confidential and Proprietary
4-115
... VAXBl '187)2
REfEltDl'CE BCI Tltt: l
!Cl PM L
Bll«lMBL sourw
Bl llS'f L source
Bl 0(31:09> L source
Bl 1<318> L source
---RES \ iiid x-iiid i llES mi- -mi
/-------
12 --12 ----i2 ---ii-
Bl CNf'<210> L source
** ** HASrER 1 I 2 I 3 I 4 I 5 I
BC! D<3l 100>
source
12 I 13 I l4 I
BC! 1<3:0> ~
150UTl:I!
____ _.,._ 1£1 lQ<l:O>-L -- -- --- ------ ----- .....
... ....._...
--- __.,.___ ------ --- ------
1£1 INT<7:t) --- ---- no r111u st ---- ------- ------ ----- ---- ---- ----- ------- ----- -
9:1 RM L 8CI l«I' L 9:1 IU L llCI IWI L llCI EV<410>-L
_ ,___ .._...
______ ......
,.,.. ....
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---.
--
------
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--- ._.
'-+--+~- -----t---r
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**SIAIE** 1 I 2 I 3 I 4 I :5 I 6 I 7 I 8 I !I I 10 I 11 I 12 I 13 I 14, I
llCI 1)(31100> sourw
BC! 1<310> !!..
source
l!CI CLE H BCI SI)[ L BC! SEl L SCI SCt210> L
Bel £V<4:·>"i:
--- ""t!:!:_ - ·-+---+---- ---- ---- --- ------- --
Figure 67 · VAXBl 78732 STOP Transaction (Extension) Timing Sequence
4-116
Confidential and Proprietary
A£F091CE BCI Tiii£ L
BCI PIM: l
81 NO MB L
HUTct
BI 11SY L
BI I<3:0> l source
Bl atF<21a>"i: ···-·· ----
lit lftSltUt 1 I 2 I BCI D<31118L --··· _ _
1G I 11 I 12 I 13 I J:4 .1
llCI 1<318> H-
_ _ _ .,. _ _ ..':"'...!""
Mltrct
BCI RQ<110>-L.
'!"'---
llCI INT<1:4r --··
llCI W l BCl NXT l BC! ltlE L BC! l'N l
,__ --- -,__ \ __
--·or---.-,--- --
FCI EV<4:0>..L _.,.__ - - - -
tt SLM tt 1 I 2 I 3 I 4 I 5 I 6 I 7 I 8 I iJ I 10 I lj I 12 I ,13 " 14 J
BCI D<31100> source
11:1 1<310) ~
MUfct
BC! KS<110> L
BCI CLE H llCJ !IDE,L
· - - · -....:;:=--=·:i=::::::ii::::=t
11:1 SEl l
SCI !IC<218> l
-~-
llCI M4:8>.l ·-··
Figure 68 · VAXBI 78732 Quadword BDCST Transaction Timing Sequence
Confidential and Proprietary
4-117
Preliminary
VAXBl787l2
.REfEma SCI Tiii l
SCI PIM L
Bl NJ ARB L source
Bl 8SY L
,__
un
BI D<31100> l source
Bl I<3:0> L- -----
-rl!t'
BI CNF<210>"i:
SOUFCll
** tt msmt 1
2I 3I 4I
13 I 14 I
source
BC! 1<3:8> H source
SCI RQ<l:O>-L
SCI INH7:4)
SCI WL BCI N)(I' l
-
---- ------ ------ ____/ ___/
----- ---- ------- ----'- ------- ------ ------- -------
----
·=- -::-:: :-:-:-=-:-_- _-== :=:=: __:=:- llCI lllE L -- ------- -~==== -:~-=: :~:=:: -~=== ------- -~:::· ~~:::: :~::::-
SCI IN L
BCJ EV<4:D>0L ------ ---- --- ----- ------ ------ ------ ------ =~-
EL ::!£2:: ------
** SI.AV£ tt l I 2 I 3 I 4 I 5 I Ii I 7 I 8 I !J I 10 I 11 I 12 I 13 I 14 I
BC! 0<31:00_>-i-.---t-source
SCI 1<3:0> ~
SOUTCf!
BC! RS<! :O> L
BCI ClE H
BCI SOE L
BCJ
. ecr
:-iiK: ------ S£l l
SC<2:o>"t ------ ------ ------
------- ------- ----- _!._Hf{!: -M:y- r"ar·- -;-r· ------
BCI £V<4:0) L
-- ------ -----·+-·-+----- ----- - - -- -·-r·---t-
Figure 69 · VAXBI 78732 Burst-mode Write (Pipeline request) Transaction Timing Sequence
4-118
Confidential and Proprietary
. ~------~---~----~---.-.------~--~--· ...-~----~~~-~------,,.-_~~--~--·------~,--~~~~~·--~~---~----~~~----------
-
. REfBDICE
acr TIME L
llCI l'INEL
81 NO ARI L
81 BSI' l sour c t
Bl 1><31 :IO> [ sourct
BJ H311> l - ---sourct
Ill ll*"<2:0> L
** MSTEA it l
llCI D<3l:OQ,:...>.i:---1-· sourct
VAXBl.187J2
131 14 I
-, -, ---- ___ SCI RM L
llCI NICT L il;I ta: L
_... ----·-- ----- ------ ------ __,.____ ----
--__-__'
____! _____
--:-'
·--\
__.,._..;..._ .,..___
---
llCI IN l
BCI EV<4iO>l - - - -----
tt SlAllE ** 1 I 2 I
BCI 0(31188> HUTct
BCI 1<318> H
511Jfct
BC! llS<l:ll L
Bel a.E H -+---·
BC! SllE L
BCI SUL SCI SC<210>~l
BCI lV<411>",1,.
Figure 70 · VAXBI 78732}3urst-mode Write (Pipeline request and pipeline NXT Enable bit set) · Transaction Timing Sequence
Confidential and Proprietary
4-119
Preliminary
VAXBI78732
REfEllEtQ SCI TillE L
llCI Pfli'lSE l
BI Nil ARB l source
Bl BSY L source
Bl 0<31100> L
source
- - - Bl CNF<2:0> l
source
ttl!ASTEJtti 1 I i! I 3 I 4 I
llCI 0<31:00!
- - -.ct x-,;- x.,.. ad- rid x··id- rid- /
'2 --ii" -Ii ~ '"'Si- --s2
7 I 8 I 9 I 18 I 11 I 12 I 13 I 14 I
llCI 1<3:8> H source
llCI RQ<110>-l
BCI INT<7:4}
llCI RAK L llCI NXT L llCI HOEL BCI IWl l llCI E\1<410>-l
__ __ ----- ------ - .....--..... ______... ----
\
--------, -'
--- --- - - ---·-t---+---- ---- --- ------- ----- ------- ----
------- ------ ------ ------- ------ ------ ----- ------ ----- .:E~:: ::!£2=: -----~-
** ** St.#JE r
llCI D<31 :00~ source
2 I 3 I 4 I 5 I Ii I 7 I 8 I 9 I 10 I 11 I 12. I 13 I 14 I
l\CJsoIu<r3c:0e> ~- ------ --·-·
SCI° RSU1D>L -----
lltl CLE 11 BC! SOE L
- -_-_-_--..,-._ __·-...-_._..-_- - -
llCI SEL L
a:1 sc<210>-i: ---- ---- ----- ----- :Ii&L ------ ---- ----- =~~- ··c;a:v- r-ar· -;T- -- ___..__ ---- -·---- .._ __..,____ ----- --- ___ .. .,....
_!!!___~
Figure 71·VAXBI78732Special Case 1 Transaction Timing Sequence
4·120
Confidential and Proprietary
-
81 HO MB L
-rce
81 BSY L sourct
Bl 0(31:09> L seurtt
&I 1<310> l H11rce
Bl Df'<l!1I) l sourct
** ** Wl'.Ell 1 I 2 I
llCI 0<31111!
SOtlTClt
llCI 1<3111> ~- ------ --·--
llCI RQ<l :O>"i: -----
1£1 Wl ll:l NXT l 1£1 lfOE L BCI !Ml l llCI EV<418>"[
---- ----
'----
ttSl.AUEtt 1.1 2 I 3 I 4 I llCI 0<31108!._ _ _
seurce llCI 1<310> 11
wurce BC! RS<118> l
BCI ctE H _ ------- -----llCI SllE L llCI Sfl L BC! 9C<21t> l
llCI lV<4it>"t ---·- -----
12 I 13. l J4. I 13 I 14 .1
Figure72 · VAXBI 787n SPfcial (Ase 2 Transactjon:j'iming Sequence
Confideniiat and Proprietary
4-121
REFWHCE SCI TIME l
VAXBl78732
Bl BSY L
HUfCI!
BI 0<31100> L sevrc:.
/------
** ** IWISTER 1
llCI D<31 :08!
SMTCI!
BCI 1<310> !!.
HUTCI!
BC! RQ<l10>"t
2I 3I 4I
12 I 13 I 14 I
SCI INT<714>
BC! W L llCJ NXT l SCI HOE l
,_
·--1~-1~---1==- =,-_,_·_4_·--==-r-·=--r - ----
BCI !WI L
llCI EV<4:8>..L.,..+-·--+---- --·- ----- ----- ------- ------ ----- ------- ------ ------ _-!-!!-!-..-. .-..!-:!·· -------
ft SIM ti 1 I Z I 3 I 4 I 5 I 6 I 7 I 8 I it I 10 I 11 I 12 I 13 I 14 I
SCI 0(31108> source
SCI 1<3:0> ~ 511urce
BCJ RS<l 10>L
BCI CLE H BCI SOE L -4---l
llCI SEL L
------ ------ ---- -"ii:[:
BC! lV<4lO> L
- __!~- -- -__-!S· -L t - - - t
Figure 73 · VAXBI 78732 Special Case 3 Transaction Timing Sequence
4-122
Confidential and Proprietary
REfOBU
act' TUI: L
81 art l
Bl D<llllt> l
IHTct
Bl 1<319> l --
81 OF<218> L
·** .ti lflSTER. .1
llCI D<3h80l
IOllfct
2I 3I ·
SCI INH7:4fi>[-=t:=:::t
SCI llllK L llCI l«1" L BCI ltlE L BCl ltlB l
ti:SIJllEtt l I 2 I 3 I BCI D<31180L -----
1£1 IGill> .H
BC! RS<l:O> l BC! Cl£ ff
SCI SOE l -+--+--4-·
--- ---- SCI SE!. L
llCI SC<210> l
ECI E\1(418>-L ------- -----
__g__
Figure 74 · VAXBI 78732 Special Case 4 Transaction TimingSetjUenee
Confidential and Proprietary
-------~---~-----------·--------------·~{
· ,Applica~pinformation
The VitXBI Syste,ms Reference Man~l ~bntains d~talled information.of the (:)peration of the VAXBI
bus and appliciltion information of the BIIC. .
'· ·
·
·Specifications
The mechanical, electrical, and environmental specifications for the VAXBI interlace are as follows. The test conditions for the values specified ate asfollows unless specified otherwise. · Temperature range: 0°C to 125°C
· Supply voltage CVcd: 4. 75 V'to 5.25 V
Mechanical Configuration
.
The mechanical dimeruions for mounting the 133-pin VAX'.BI iritetlace package are shown in
AppendixE.
· Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to a device.
Exposure to the absolue maximum rating conditions for extended periods may adversely affect the
reliability of the device.
· Pin voltages: -1.5 V to 7.0 V
· Operating junction temperature range (T1): 0°C to 125°C
· Storage temperature range: -5°C to 125°C
· Ambient t~mperature operating range (T"): 0°C to 70°C
· Package dissipation: 4.25 W* *Pac~ge dissipation is approximately 0.575 watts higher than :the product of the maximum supply current and supply voltage because of the dissipation of the VAXBI drivers that s.ink the external . VAXBI pullup current.
Recommended Operating Conditions · Supply voltage (Vcc): 5.0 V ± 5%
· Inlet temperature: 5°C to 50°C · Humidity: 10% to 95% with maximum wet bulb 32°C and minimum dew point of 2°C
· Altitude: 0 to 2.4 kilometers
· Airflow: 200 linear feet per minute
de Electrical Characteristics Table 46 contains the de electrical parameters for the input and outputs pins of the VAXBI interface chip. Unless otherwise specified, all specifications are at T1=0to125 degrees C and Vcc=4.75 to
5.25V.
4-124
Confidential and Proprietary
-
Symbol
BCI 11
BCI Im
BCiloH
BClloHD
BCI loL BCilow
BCIVIL BCIVm
BCIV0 n BCIVoL BCilos
BCI C10 BI 11 Bl loL BIVoL BIV0 n
BIV111 BIVnav
BI VIL BIVLHY
Preliminary
VAXBI78732
Table 46 · VAXBI 78732 de Inpu~ and Ou.tput Parameters
Parametef
Min.
Max. Unit
Test Condition
Input current1
0 . .33
0.10 mA
0.2 < V,.. < 5.25V 0 <Vee< 5.25V
Input current while
BCI DC LO is asserted2
-Q.25 mA -1.0 mA
V.=2.4V V.,=OSV
Output high current. (except BCi DC W)
Output high current (only for BCI DC I,,())
-400 -5.4
µA
V0.,.=BCIV0 n
mA
V..,.=BCIVoH
Output low current
4.0
mA
V··,=BCI Voc
Output low current
100
(only for BCI DC W .
when Vee< Vee min.)
Input low voltage
-1.0
Input high voltage
2.0
(except BCI TIME)
BCITIME
2.4
Output high voltage
2.7
Output low voltage
µA
0.8 v v
v v 0.5 v
V_=BCIVoL . 0 <Vee< 4.75 V
I..,,=BCI loa l....=BCiloL
Short circuit output current
-150 mA
or Not rp<:>re than one at a
time > 1 second
Pin capacitance
10
pF
0 < V10 <Vee
Input current'
Output low current
Output low voltage Bus voltage high
Input high voltage
Input high voltage
(hysteresis voltage)'
Input low voltage Input low voltage
(hysteresis voltage)3
-270 21
2.3
1.95
1.45 -1.0
30
µA
mA
0.6 v
3.5
v
v v
1.1
v
1.4
v
0 < Vm <BI Von
v..,=BI VoL
l..,=BI loL
These are bus terminator specifications
Con#clential and Proprietary
4-125
-
Preliminary ii
VAXBliS732
Symbol Parameter
Min.
·Max. Unit
Test Condition
BI C10
Ice
Piri tapadtance4
Power supply current
6.0 pF
700 mA 530 mA
I.·. =O,T1=27°C' I··· =0,T1=85°C
1These I, specifications apply only when data is not being driven by the output under test.
2While BCI DC LO is asserted, the BCI D and P lines are internally pulled up. While pulled up, these
lines can source a minimum of 250 µA at .2. 4 V. The user interface logic must sink a minimum of 1.0 mA at 0.5 V to drive any of these lines low when BCI DC LO is asserted.
lThe hysteresis voltage is defined as follows: BI V1a-The BIIC wilI not detect a change in input
state if the input voltage drops to BI vHHY following the application of BI Brn. BI v,L- The BIIC
will not detect a change in i_nput state if the input voltage rises to BI Vrnv following the application of BI VIL.
"The device under test must be powered up during this test and BI DC LO should be asserted,
except when measuring C10 for BI DC LO. 5T1 is junction temperature with ambient temperature (TA) = 0°C.
· ac Timing Specifications
Unless otherwise specified, test conditions are at TA =0°C to 70°C, Vcc=4.75 V to5.25 V, and the BCI signal capacitance load= 50 pF.
Figure 75 shows the ac timing for the BIIC and Table 47 lists the timing parameters for the symbols on the figure. Figure 76 shows the waveforms and symbols used for the measurements of the VAXBI bus. Figure 77 shows the waveforms and symbols used for the measurements of the BCI bus. Figure 78 shows the load circuit for the VAXBI bus driver measurements. Figure 79 shows the load circuit for the BCI bus driver measurements.
4~126
Confidential and Proprietary
-
-L
Ti· nse re T5ll Jlee 111111 ,.. TS1) Tl9B nse
JIC[ ta:: L
Bel Silt L
....
I f ~~i:ft'H -><Xxxxxx,.___.....,)---<(rlllllj "'*":>t------(rlllllj
VAXBI 78'132
'8CJ oc; LO L
oct EV<4s9>L
~------------+--1~1-'~---'------f-J'----------·-------~
Bl !11.Gl'R.,S L
Figure 75 · VAXBI 78732 ac Timing Sequence
Confidential.and Proprietary
4-127
ml'IDID
Preliminary
VAXBl78732
Table 47 · VAXBI 787)2 ac Timing Parameters
Symbol Signal definition
Min. Max.
Unit Reference
T., TIME period'
49
1000 ns
T,p
TIME pulse width
15
ns
T ··
PHASE setup time to TIME
10
ns
Tpl
PHASE hold time for TIME
T,
BCI signal rise time2
T,
BCI signal fall time2
10
ns
10 ns Figure 77-C
10 ns Figure 77-C
Tp,
BCI signal propagation delay from TIME
(except for BCI MDE and BCI SDE)2
0
Tp2
BCI D < 31:00 >, BCI I< 3:0 > , and < BCI PO
line signal propagation delay from TIME2
0
30 ns Figure 77-A T,,+30 ns Figure 77-A
T.,
BCI MDE and BCI SDE signal propagation
delay from TIME'
40 ns Figure77-A
Tw.. BCI DC LO assertion delay from BI DC LO
assertion
0
150 ns
T.w. BCI DC LO deassertion delay from BI DC LO
deassertion
45
55 us
T..... BCI DC LO assertion width following the
setting of the NRST bit
45
55 us
T ··
BCI D< 31:00> and BCI 1<3:0> line setup
time with BIIC configured for BIIC-generated
parity
20
T,
BCI signal setup time with BIIC configured for
user interface to supply parity
0
ns Figure 77-B ns Figure 77-B
Th
BCI signal hold time from TIME
15
T,,.. BCI D<31:00> and BCI 1<3:0> release
time from TIME
0
T.,,. BCI D<31:00> and BCI I<3:0> release
time to BCI MDE or BCI SDE assertion
0
ns Figure 77-B 40 ns
ns
T..m BCI SDE (BCI MDE) deassertion setup time to
BCI MDE (BCI SDE) assertion'
T,,-15
ns
Tdp
BCI NXT, BCI MDE, and BCI SDE deassertion
pulse width
T,,-10
ns
Tdh
BCI D<31:00> and BCII<3:0> hold time
from BCI CLE and BCI NXT
r.,-25
ns
4-128
Confidential and Proprietary
- ·· · - -~~""!;"''-'=-~~---...,,---·~·~·---------~,~-------~--~.--__,_-_,_,~--·~-··--""~-------~~---------~----~~------------
-·
Symbol Signal definition
Min. Max. Unit Reference
T.i. BCID<31:00> andBCII<3:0> setup time
to BCI CLE and BCI NXT
T,,-25
ns
T..., Minimum assertion to assertion period for
BCI NXT, BClMl)E; 11nd '.B~i SI5E4
J90
ns
Ti..' BI signal setup time ~o. TIME
20
ns Figure76-B
TL. BI signal hold time froml'IME
2Q, ..
ns Figure76-B
T._ BI signal assertion delayfrom .Ti'Mfl
' 0
85
ns Figure76-A
T.., BI signal release time from TIME
0
85 ·.. ns Figure 76-A
Tw BI signal fall time (C.· 410 pF)
20
ns Figure76-C
1The minimum specification allows for proper BIIC operation in environments with up to ±1.0 ns
of clock period noise jitter.
·
2Parameters T., T,, Tpo T,z, and T., are for 50-pF loads. The following equations describe the
degradation in rise and fall time and propagation delays for a BCI line with between 50 and 100 pF
load.
T,(50pF < C, < 100pF)=T,(50pF)+CJ17.8::--2.8.
T1 (50 pF < C1 < 100 pF)=T1 C50 pF}:+CJ17.8-2.8.
Tp1 (50 pF <C1 < 100 pF)=T,. (50t,>F)+CJ5.5-9.1.
Tp.2 (50 pF < C1 < 109pf),=7'f,, (50,pF)+.CJ5.5-'-9.1.
Tpl (50 pF < C1< 100 pF)=T,, (50 pF)+CJ5.5-9.l. .
'T..,. applies only for equally loaded BC1MDE ad BCl ~ s~gnalr;.
T4 up applies only if the lq~ng on the BCI output is constiµlt over time.
'Only one transition is .Hawed <luring TlOO to Tl30 on a.DY ,BI signal.
4~129
-
BCI TIME
Bl f'UT
Preliminary
TO
VAXBl7873:Z
BIPUT
-----Tbas---....,..."" ·----
A. VAXBI Driver Output Waveforms
T150
BCITIME
BIPUT B. VAXBI Receiver Setup and Hold Time Waveforms
Rise and fall times= 20 ns
BIPUT
~~·
VO~.
Tbif
C. VAXBI Driver Minimum Fall Time Waveform
Figure 76 · VAXBI 78732 BI Bus Voltage Waveforms
4-130
Confidential and Proprietary
0011'1ME
BCIPUT Vol Voh BCIPUT
Preliminary
VAXBI18732
------vo1
BCITIME
~v } _ . . . . . . . . _ _ v
vot_ec_·_P_u_r__; : :
~ ' '~vo
NOTE:
BCI input signals should have rise and fall times ol < 5 ns (between 0.8 and 2.0 volt points}.
B. BCI Receiver Setup and Hold Time Wavefotm&
Voh
BCIPUT
vo1------
C. BCI Driver Rise and F.U Time Waveforms
---Vol
Figure 77 · VAXBI 78732 BCI Bus Voltage Waveforms Confidential it.nd Proprietary
-
.....,....._ (3) .047 uF ~ · per group
Bl l/OPIN UNDER TEST
CBI Pun
DEVICE UNDER TEST
Preliminary
+5.0V
Vbb GND Vee GEN REF REF
VAXBl'18732
To other clamp networks
Reference voltage lllter capacitor 0.1 uF
09 *Switch 51 is closed for AC tests and open for DC tests.
Figure 78· VAXBI 7B732 BI Bus LoadCirr:uit
4-132
Confidential and J;>roprietarY
-
VAXBI 787.32
!'-~- +5.0V
5-0.7- Vol lol
DEVICE
UNDER TEST
BCI 1/0 PIN UNDER TEST (BCI PUT)
Scope probe
T 15 pF
_
(with scope and jig)
1
-
-
-
-
-
-
"
'
A
.
A
·
-
-
-
-
-
-
-
1
Voh
6.75K ohms =
loh
BCI
Signal Change
S1
S2
o to 1 1 too Zto 0 Z to 1 OtoZor1 toZ
OPEN CLOSED CLOSED
OPEN CLOSED
CLOSED CLOSED OPEN
CLOSED CLOSED
NOTE: The SENTRY test fixture does not matclh this test configuration.
S3
CLOSED CLOSED CLOSED CLOSED OPEN
Figure 79· VAXBI 78732 BCI Bus Load Circuit
Confidential and Proprietary
4-13 3
· Features
· Supports VAXBI bus system features of low interface cost, less. than 800-naoosecond data access time, and high data iotegtity
· Supports the full range of data lines rittdedfol: ah effidentVAXBHnterface
· DMA master port alfuws data transfer at (Ull VAXBI speeds
· Page overflow detection features · Single 5-volt supply
. Descnption
The VAXBI 78143 BCI Adapter Int¢ace 'BCAI) is ia· ZMOS custom integrated circuit that functions as a buffer .file between usen.design~processors, memories; 41ld adapter modules and Digital's high-performance VAXBI (VAX bus interconnect) bus. A block diagram of the BCAI is shown in Figure 1.
llCLRVB
llM<3:0>
II P<3:0> II 0<31:00>
BCI A<3:0> ~
AllOR LATCH--------------,---lrel'\W--:-_,
RClMLS
ii<ITNAl.TI:S l!c1.eliinMWl
II OMA PGOVF
llA<6:0>
ADDA LATCH
Figure 1·VAXBl78743 BCAIB!ock Diagram
!!Cl PO
ec11.<:i:o> ·
!!Cl D.;31:00>
4-135
---
VAXBI7874}
The VAXBibus is a 32-bit general purpose synchronous bus that can be eff~ively used in single or
multiprocessing systems based on VAX computers, other 32-bit processors, and compatible
devices. The VAXBI bus has a maximum length of 1.5 meters and can contain up to 16 intelligent
nodes on as many as 36 modules with an aggregate throughput of 13.3 Mbytes per second. The
BCAI supports the full range of data lines needed to fulfill an efficient VAXBI interface.
The BCAI contains a dual-port register file and byte shifter that functions as a buffer file between
the VAXBI bus interconnec_t interface chip (BIIC) and a local adapter bus on a. VAXBI module.
Individual registers within the register file have been customized to support the following functions:
· A VAXBI master port used for high bandwidth data t:fansfers (DMA master port)
· A second master port used for lower bandwidth local processor access to the VAXBI (mapped
master port)
· A slave port used to transfer VAXBI transactions onto the local bus (slave port)
A typical VAXBI 78743 BCAI interface configuration is shown in Figure 2. The BCAiperforms data-path operations and requires external control logic to fully implement a BCI adapter interface. The data path and the registers of the DMA master port are designed to allow data transfer at full
VAXBI speeds.
LOCAL
MICRO I--
PROCESSOR
~
II BUS INTERFACE
CONTROL LINES
II ADDRESS AND CONTROL
BCI CONTROL
LOGIC
BCIBUS
BllC
CONTROL LINES
j.-ADDRESS AND CONTROL
1
-
-
VAXBI BUS
MEMORY !-'
J DATA
PATH
BCAI
l BCIBUS
_r
DATA/ INFORMATION
Figure 2 · VAXBI 78743 Typical BCAI System Configuration
The BCI control logic interfaces with the BIIC and is used to generate the control signals and addressing information on the BCI bus in realtime applications. It also decouples the local processor bus interface for realtime aspects of VAXBI transactions. The processor interface loads the BCAI interface registers as required, asserts a request signal, and is notified when the transaction is complete. The data path for the processor interface can be 8-, 16-, or 32-bits wide because of the byte alignment and masking capabilities of the BCAI.
The data/address and control information to and from the local processor is referred to as II (Integrated circuit Interconnect) bus information. However, the signals from the BCAI may not be
compatible with every specific II implementation. The II bus address and control functions can be
implemented by a ROM-based microsequencer or by other logic interfaced to the microprocessor
bus.
4-136
Confidential and Proprietary
VAXBI 78'74)
The BCAI contains a dual-port register file consisting of 15 registers, each ofwhk:his 41-bitsw.ide,
The file is accessed from the Ilbus interface as 2B2-bit registers and from theBCibus as 14 36-bit
registers: TheBCI bUs register infOmiation is transferred on 32 data lines and 4 if.lformation lines.
Associated with the II bus is a byte swapper and special address decdde logic that ?erinits the user
to access one to four contiguous bytes starting from any byte boundary. The registers must be
accessed along longword boundaries from the BC! bus. The register file and byte swapper logic
includes several ad~. arid data lat~es. ~.Bg i,nterfae¢.~ P@s rwo ou~t latches, one for·
the master poruncfone for theslaVe. port. Aparley secuonis also aWilable and Checks parity in the
register file.
· ·
ws, sts) Figure 1 shows the fu.nctionalblocks and the VO lines of the BCAkFoUrof the BCI bus control
lines (BC'fRS, BCI BCI MLS, and.Bel have enable lines that gate the information from.
the primary line into the BCAI. This simplifies external controller design by allowing external dock signals to generate the precise timing required.
· Pin and Signal Definitions
The VAXBI 78743 BC.AI, contained in a 133-pin ~· functions with.~ inpµt tmd output
signals and power and ground e<:>rtnectiom shown in fligt.tfe 3~ The inputs anCI outputs are described
in the following paragraphs, The signals are gi;ouped byJI bus ~terface signals and BCI bus interface signals.
14 13 12 11 10 s a 1 6 s 4 3 2 1
p · ', · · ... -.~.·. ·.
· P'
N ·
· ·
· N
M· · · · · ·
· · · · · ·M
l
· L
K· · · J ~
H · .G ·
F · ,E ·
BCAI
· K · .J
· H "· ·G
· F · E
c· ·
· ·
B· · · ·
· · · · D
. ..
· c
· B
A · · -·
····· ·A
14 13 12 n 10 9 a 1 s 5 ·4 3 2 1
(TOP VIEW)
R.EFER TO TABLE 1.FOR LI avs INURF.1>,C!' SIGNt.LS, POW:!'RAND GRO.UND
PIN ASSl(lNMENTS,. . .. ··
..· . .· ·
. .. . ,
REFER TO TABLE 4'FOR BCI BUS INTERFACE SIGNAL PIN ASSIGNMEITTS..
Figure3· VAXBI 78743 Pin Assignments
Confidential and 'Pn:)prietacy
4-137
...
Preliminary·
ll-BQs Interface Signals
Table. l is a summary of.the Il bus signals that connect the BCAI ~the microprocessor bus
interface. The signal functions are described in the paragraphs that follow. Table 1 alSo includes the
power and ground connections to the chip.
Table 1 · VAXBI 78743 II Bus Interface Pih ancl Signal Summary
Pin
Signal
Input/Output Definition/Function
M2,M4,M5,M6 IID<31:00> N7,N9,N 10,MIO M3,P2,P4,N6, N8,M9,Pl2,Ml2, N2,P3,N5,P6, P8,P10,Nll,N13, N3,N4,P5,P7, P9,Pll,P13,P14
input/output II Data <31:00>-Transfers data to and from the processor bus interface.
Nl,Ml,L2,K2. II.P<3:0>
input/output II Parity<3:0>-Parjty for each of the four bytes on lines II D < 31:00 >.
113
input
II Data strobe-Loads the II D< 31:00 > line
information into the BCIA.
M14
HOE
input
II Output enable-Controls the data output
to the processor bus interface.
LlJ2,Kl,H3 IIM<3:0> input
II Mask < 3:0 >-Controls the ability to perform a II processor interface operation to individual byte fields.
Hl,Gl;FI,G2, IIA<6:0> F2Jl,H2
input
II Address < 6:0 >-Controls the selection of the internal registers in the register file.
El
IIAS
input
II Address strobe-Loads the information on
the II A<6:0> and II M<3:0> lines into
theBCAI.
KU
IIWS
input
II Write strobe-Controls the write operation
of the internal i:egister file.
L14
IIRS
input
II Read strobe-Controls the read operation
for the II interface port of the register file.
]12
IICLRVB
input
II Clear byte valid-Clears all master port
byte valid bits.
Bl
IIPSEL
input
II Parity select-Selects the user supplied or
internally generated parity indication on the
BCI PO line during data output transfers to
the BIIC.
Confidential and Proprietary
Preliminary
VAXBl7874.l.·
Pin
Sp
.lnpat/Output ~on ·
D12
I1PIAD
input
II Parity bad-Indicates that the f*lrlty is not
valid during data transfers to and from the
BIIC.
J14
II DMA POOVF output
HDMApage overflow-Indicates that the
]))MA address register is full.
-·
,/' ''
,.,
J13
II MAP PGOFV output
. ~IM~p.,page o~.;.;...;Jndicates ·that the
MAP address register is foll~
N14
II DMA fNc ENA input
rr' 6.MA incremem enable-Allows the mas-
terpdff DMA ·addtesii ·register · tO be ihfire.
mented.
M13
II MAP INC ENA input
map ff~p i~~l+W~! eµ~~le""7AJloWS t~1llast(!r"
po~ a4~s rt:gis~.1:9.·~·.i~mented.
L3,Cl0,A14,Mll Vee
input
VoJ.tage..,....Power supply voltage.
Pl,Cl2
VBB
output
C4,C7,C8,F3 GND G3J3,K3,Kl2, Kl4,L12,M7,M8, N12
inpu~
II Data (II D<}l:OO> )-Bidirectional data lines that connect t:O a transparent input latch. The latch is controlled by the ~signal. The three-state drivers iire~nabledby the 'II15i!input.
II Parity (II P< 3:0> )-Parity bits associated with each of thefour bytes on the IID< 31:00 :>
lines. Valid byte parity must be generated by the user andloaded him the Ji3CAI on Unes II P <3:0>
when transferring data, addresses, or command/mask/status informationdnto the.BCAL When
·the loading 4-l;~it command/mask/status infor~tion, pari~y g~~~P piu11t be for the coniplete
byte, includlng the ieros in the µnimple~ented QOrtk>~ of the hYt<!~ jhe'sc:AI iUso ge~ates parity for c{ata lo~ed into the BCAI from the. ~m:~ an<:l,com~s th!!' )?~lo/ it.8en.erate.! to#le BCI PO bit.
< ThefI Pl\AD line is set. i.f anei.:r,or~de~ re,~ardl~~ofJlt~~pn ()£ da~fl9w: ~I.I ~ty
bits ~ latched .With the II D 31:00 > ~£onn11tionby ~ sjin~ arid enabledby II()~ sig~.
II Data Strobe (Ilii$)..,,...This sign;µco~s th¢tra~p~n.t4\tch~·for th!! II.D<:3l.:00> . input
data. The input latch js transparent when the rrns input is as~rted and tl}e in£orrpati9n is latched
when the signal is d~11erte,d. ·
'
'' - '
'
'
'
., '· ~'- -,
· . · · ·. ..
'
. .
'
IDJE II Output ENlble (II OE)-Con.tt:o41;heowJ>Ut drjvers,for,tlic;}I D>31:9f,t:;- arid ~IP,J~:O>
lines. When is asserted, the ~on~ent$o£ the I~ D<Jl:OO> 'output latdi are,'transferrCd tO the
II D < 31:()0 >. ~ta bus. \lqhen it.is deasserted, theJ(I) <}1:0,0 > lines become ahigh·im~ce
state. Line ~I OE has a 50-µA pullup ~.ircuit, so that if the pin is not C01UJected, it will remain
deasserted.
·
II Mask (II M< 3:0 >)-Controls the ability to perform an II operation to individual byte fidds.
When the sdected tI M <3:0 > lines~·deasserted, anII bus Write openttlori for the correspond-
ing byte fidd is suppressed and an II read operationremrns hll zeros including the pttt!tyBit; The rrlllsk information is latched'by the assertion oftheITAS'lirie. Tuble2 lists the lrbus interface mask
bit assignments.
______ _ _ _ _ Confidentialand Proptletary
4-1}9
....,..,
,
-
--·=-.:·. . . -.·.· .·' P·~·l.Uftl&'.]'·t< ':'"'
Table2 · VAXBI78743 D Btiis .Masldlit Assignments .
II Mask lines*
3
2
1
Valid data
0.
Valid parity
1
1
1
1
IID<31:00>
IIP<3:0>
0
0
0
1
IID<07:00>
IIPO
0
0
1
0
IID< 15:00>
II Pl
0
1
0
0
. I!b<23:16>
IIP2
1
0
0
0
II D<31:24>
IIP3
*All, other i..Qput combinations that specify the validity of the bytes on the II D<31:00> lines are allowed.
D Address (DA< 6:0 >)--Controls the selectionof the internal registers in the register file. Referto
Fi.gllre 4 for the hexadecimal address values assigned to the registers. The II A< 6:2 > signals pass
through'a transparent latchcontrolledbyiIASinputand may be used in alatched or unlatched mode.
Lines II A< 6:2 > are .used to select. the primary longword register being accessed and lines
IIA< 1:0 > control the byte offset multiplexers attached to the internal registers as listed in Table 3.
Table 3 ·VAXBI 78743 Byte Offset
DA line·
1
0
L
L
Byte offset none
L
H
1
H
L
2
H
H
3
*H=high level,. L=low level;
For registers within the dual octaword buffer, the bytes that extend beyond the primary longword
register are contained in the next adjacent register (A< 6:2 > + 1) except .whenII A < 6:2 > ::=OOIU. When the exception exists, the primary longword register is at the bottbtn of the
buffer andthe offset is transferred to the longword register'addressed by 00000. For regist'ers hot in
the dual octaword buffer, the bytes that are offset beyond the primary longword register are not written during write operations and are returned as all zeros on read oj>erations.
Il Address,Strobe (D AS)-Controls the transparent latehfor the II A<6:0 > data and mask bits
II M < 3:0 >. The input latch is transparent when II AS is asserted and latched when deasserted:.
D Write Strobe(Il WS)-Controls the writing ofthe internal register file: The input data from the
,transparent latches on lines n D < 31:00> is loaded into the selectedregister during assertion of the ifWR strobe. The deassertion of the selected II M< 3:0 > lines. wilfinhibit the wdte operation
for the oorresponding byte field. When acce:::sing the DMA octaword data buffers, th~ byte valid bit
for the addressed location is set when its byte is written.
D ~ S4'0be ~II ~)..,....Controls the read operatiorJS.for the I~ bus port of the register file,Jbe
.~doperat,km isinitlateq when the II.RS line.is .~tep. l\Aq the resajting oµtpt1tdata, is heJff ~.the
IID < 31:00> outpudatch when the II RS sigQal is de~~erteq. Dea$sl'.rtion of the selected, ll
M < 3:0 > lines will inhibit the read operation for the corresponding byte field.
.
Confidential and Proprietary
Preliminary
ri: Clear Valid Byte (II CLRVB)-This sign!).! is ~¢<;! .~.~.~ all the master port Byte Valid bits
associated with the dual octaword buffer.· .
·. .
Il Parity settd: '(Iit-SBL)..;...Selects which source of parity·(user supplied or intetnally generated) is
passed to BCI PO otltput when data is transferred to the BIIC. A low level selects user parity and makes the errors within the processor bus interface or the BCAI visible to the VAXBI bus. A high level selects the internal parity. that ahvaysprovides corre<;t .parity for the daµ, being passed to the
BCI bus. This signal is latched by the BCI AS line.
Il Parity Bad (II PBAD)-When set, it indiC!li\tes one of two conditions:
· When tnm.smitting data to the BIIC; the result of the internal :parity generation from the BCI D<31:00> and BCI 1<3:0> lbles.forthis cycle do not agree with the parity bits associated withthe.5 bytes beingtransmittecl.
·When receiving data fromthe BIIC, the BCI PO line from the BIIC does not agree with the internal parity generated from the 5 bytes being received on the BCI D<31:00> and BCI 1<3:0> lines.
Il DMA Page Overflow (ll'fiMA PGbVif)i.,;..Asserted to indicate that the DMA address register has
reached the bo\llldary of a ?12~~ pl(!ge·
·
Il MAP Page Overflow (D MAP PGGFV):--'.Asserted to indicate that the MAP address register has
reached the boundary of a 512-byte page.
aj Il DMA Increment Enable ,J>MA.~C ENA)-Enables the low-onler 9 bits of the master port
be DMA address register to irlcremented by avalue of 4, 8, or 16 as specified by the length field (bits
31:30of theDMA address regiSter) whenever the master port DMA address ttgtster is accessed by a
BCI read operation:
. .
Il Map Increment E~able ·. a:r=·. ,......M, AP~==JN,...,.·.c=~.=E"""N,...,..A)-Enables the low-order .9 bits of the master port map address register to be i.®remetit(;!9 by a.value of 4, 8, or 16 as specified by the length field (bits 31:30) of the map address register wh~~the roaster port map address register is accessed by a BCI
read operation.
BCI Bus Signals Table 4 is a summary of the BCI bus sign~s that connect the BCAI to the BIIC interface. The signal functions are described in the paragrap~ that fullow.
Table 4 · V.AXBI 78743 BC!Bus Interface Pin and Signal Summary
C2,D3,Al;C3, BCI D < 31:00> ·input/output BCI Data < 31:00 >-Data lines that transfer
B2,A2,C5,B3,
data between the BCIA and the BIIC interface.
A3,B4,A4,B5,
A5,C6,B6,A6,
A7,B7,B8,A8,
A9 ,B9 ;AlO,All,
C9,B10,A12,Bll,
Al3,B12,Cll,B13
E14,F13,Dl4, BCII<3:0> F12
input/®tput
BCI Information < 3:0>-lnfprmation lines
used to transfer command, mask, and status information between the BCAI and BIIC interface.
Confidential and Proprietary
4-141
-i
Preliminary . ·.<,
VAXBI'l1814l'
Piri'
Signal
E13
BCIPO
F14
Dl,E3,Cl,D2 BCIA<3:0>
E2
BCIAS
Hl2
BCIWS
H13
BCIENAWS
Hl4
BCIRS
Gl4
BCIENARS
cu
I BCIENAMLS
Bl4
BCIENBMLS
El2
BCIMLS
Cl4
BCISLS
DU
BCIENASLS
Gl2
BCIMDE
GU
BCISDE
lnput/Ou~t Delii1itioi1/Ituncticm
_'",,;
< '','.·C
I
input/output BCI Parity-:A p~ity i.pdkator from the B:IIC
when data .is received and to the BIIC when
data is transferred to the the BIIC.
·
input
theBCI Datil strobe-Loads the information on BCI D<31:00> and BCI 1<3:0> lines into the BCAL
input
BCI Address-,-Controls the selection of the internal registers in the register file.
input
BCI Address strobe-Controls. the loading of the A<3:0> input information· from· the BIIC.
input
BCI Write strobe-Controls the writfug or from the BIIC to the register file.
input
BCI Enable write strobe-Enables theBCiWS
input to the BCAI.
input
BCI Read strobe-Controls the read opera-
tion of the register file from the BUG. .
input
BCI Enable read strobe~Enables the operation of the BCI RS signal from the BIIC.
input
BCI Enable A master latch strobe-Enables the operation of the BCI RS signal input from theBIIC.
input
BCI Enable B master latch strobe-Enables the operation of the BCI RS signal input from theBIIC.
input
BCI Master latch strobe-Controls the opera-
tion of the transparent output register.
input
BCI Slave latch strobe.._Controls the transfer
.of information on the BCI D < 31100 > and
BCI I< 3:0 > lines to the BIIC.
input
BCI Enable slave latch strobe-Enables the operation of the BCI SLS input from the BITC.
input
BCI Master data enable-Controls the slave output data from the BCAI to the BIIC;
input
BCI Slave data enable-Controls the transfer of the $lave data from ihe BCAI to the BIIC.
4-142
Confidential and Proprietary
-·
VAXBl73741
BCl Data .(BCI D<ll:OO> )-Bidirectional data lines with·a transparent input latch andt\vo
output latches. ~. input latch is controlled by .the ·BCT'DS line. The. ~f!litters fpJ: the, qutput
latches are-~ntrolled by BCI MOE.for the master data output latch ari.d by t,he BCI st>'£ input for
the slave data output latch.
·· · ·
.
BCl !nformatiou. ()ICI I< l:O >).;.....These line$ are used to traosfer ~CMD, ~MD.and M<:;MD
commands, mask, and status information to and from the BIIC. The lines are latched and enabled by the same signals as the BCI D < )1:00 > lines..
to# BCI Parity (BCI PO).,...This bidire~ional linelecei~s the p~!Y:~~~c;>11,Wfi.~ ~~ng data
from theBI~C andit is.compared
Paritrfrom (he interhiil~tr ~¥t.1nteinal.~ity is
line generated when the BCI D< 31:0()>.and.~Cl I.<: 3,:0> Unes,·(#ed. When tµtns~ting qata,
this line supplies user parity or interruil p~rlty, as·selected by II PSEL. Ifmtern&_p~jty ~Jlpt
agree with externally.supplied parity m either directiofl, th~ n~bJine is.' ~serted. The~
information is latched and enabled the same sith'.e; ~er 0 <31:00> lines. · ·
mm BClD,.biSttobe(BCipS>'.""""Con~l~th,~~~~~tU];put~tch{9f J3<t~D.<:;3l:QO>, BClt<3:0>,
and BCI PO iilput data. The input latch is transparent when
is asserted and theinformation
is latched when it is deasserted.
· 1 ·
BCI Address (BCI A< 3:0 >)-Controls the selection of the }t;ternlll r¢g~t~ f* .~is~et~.' }'he
BCI A< 3:0 > lines transfer through a transparent latch controlled by the~ sighal and may be
used in a latched or unlatched mode.
BO Address Strobe (Ba'AS}-Con~ls the trahsparentlatchforBCI A<: 3iO > input data andfor
arid Il PSEL input: The latch is transparent whefr BCI AS is asserted' the fuforfuation is latched
when it is deasserted.
.
·
BCI Write Strobe (BCl WS)-Controls BCI bus write operations to the internal register file. The input data BCI D< 31:00> from the input latch is loaded into the selected BCAI register during assertion of this signal.
BCI Enable Wrire Strobe (BCI ENA WS)-Gates the BCI WS level into the BCAI.
BCI Read Strobe (BCI RS)-Controls BCI bus read operations of the internal register file. The operation is initiated when BCTRS is asserted and the resulting data is held in an internal register upon the deassertion of BCI RS. The byte valid bits for the addressed register are reset when a byte within the DMA data buffer is read. The BCI ENA RS signal must be asserted or this line will be
disabled.
BCI Enable Read Strobe (BCI ENA RS)-Gates the IiCiRS signal into the BCAI. BCI Master Latch Strobe (BCI MLS)-Controls the transparent output register for BCI D < 31:00 >
and BCI I< 3:0 > master output data. The latch is transparent when BCI MSL is asserted and the information is latched when it is deasserted. Either the BCI ENA MSL or BCI ENB MLS signal
must be asserted or this line will be disabled.
Confidential ii.nd Proprietary
···
VAXBI7874;
BCI Enable A Master Latch Strobe (BCI ENA MLS)....,.Gates the BCI MLS signal into the BCAI. BClEnable B Master Latch (Bet ENB MLS)--'Samefuncrion as the BCI MLS signal.
BCT Slave Latch Strobe (BCI SLs)-Controls the transparent output latch for BCI D<31:00> and BCI I< .3:0 > slave output data. The latch is transparent when the BCI SLS is asserted and the
·information is latched when it is deasserted. ·The BCI ENA SLS signal must be asserted or this line
is disabled.
BCI Enable Slave Latch Strobe (BCI ENA SLS)-Gates the BCI SLS signal into the BCAL
BCI Ma11ter Data Enable (BCI MOE)-Controls the transfer of the data in the master output latch
to the BCID < 31:00 > and BcII < 3:0> lines. This signal has an internal 50 µA pullup device so
that the BCI D<.31:00> and BCI 1<3:0> lines remain a high impedance when the BCI MDE input is not connected.
BCI Slave Data Enable (BCI SDE)-Controls the transfer of the data in the slave outpu~ latch to
the BCI D < 31:00 > and BCI I< 3:0 > lines. This signal has an internal 50 µA pullup device so that the BCI D < 31:00 > and BCI I< 3:0 > lines remain a high impedance when the BCI SDE input is
not con.tlected.
· General Registel' Addressing
Figures 5 shows the memory map configuration and information of the BCAI registers. when accessed by the BCI .bus interface. Figure 6 show register memory map configuration and information of the BCAI registers accessed from the BCI bus interface. The hexadecimal address · assignments and read/write capablities of each register are listed in the figures.
4-144
Confidential and Proprietary
-? llA<B:O> I 31 0 4 8 c 10 14 18 1C
20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58
Preliminary
II 0<31:00>
23
1615
·MASTER PORT" A OMAOA'l"A l MASTER PORT A OMA DATA 2 MASTER PORT A OMA DATA 3 MASTER PORT 8 DMADATA 0 MASTER PORT 8 OMA DATA f MASTER PORT B OMA OA:TA 2 MASTER PORT B OMA OATA3
MASTER PORT OM.A ADORES§ OCMD
MASTER PORT MAP DATA MASK
MASTER PORTlA'.'.'PAQPRESS
ZEROS SLAVE PORT DATA 1
SLAVE PORT DATA 2
MASK STATUS(SPD 2l
ZEROS
VAXBI7S.:9
I
00
RIW
R/W
R/W RIW
DATA WRAPAROUND
RIW
R/W
R/W
R/W R/W RIW RIW RIW R/W R!W
RIW R/W
R/W
R/W
fi)'W
R.iW R
Figure 4 · VAXBI 78743 JI Bus Inteeface Register Memory Map
.Confidential arid Proprietary
4-145
-·
Preliminary
vAXfi,¥s71J;,:
BCI A<3:0> I
31
0
:BCI D<31 :00> MASTER PORT A OMA DATA 0
MASTER PORT A OMA DATA 1
2
MASTER PORT A OMA DATA 2
3
MASTER PORT A OMA DATA 3
4
MASTER PORT B OMA DATA 0
5
MASTER PORT B OMA DATA 1
6
MASTER PORT B OMA DATA 2
7
MASTER PORT BOMA DATA 3
8
MASTER PORT OMA ADDRESS
9
MASTER PORT MAP DATA
A
MASTER PORT MAP ADDRESS
B
SLAVE PORT DATA 1
c
SLAVE PORT DATA 2
D
SLAVE PORT ADDRESS
E
ZEROS
F
R=READ ONLY R/W= READ OR WRITE
ZEROS
BCI 1<3:0>
R/W
R
R/W
B
R
y
T
R/W
E
R
v
R/W
A L
R
I
RIW
D
R
B
I
R/W
T
R
s
R/W
R
R/W
R
R
DCMD R
R/W MASK R/W
R
MCMD R
R/W MASK RIW
RIW MASK R/W
R/W SCMD R/W
R
O's R
R
O's R
Figure 5 · VAXBI 7874 3 BCI Bus Intet/ace Read Transaction Timing
The registers within the file are grouped according to their supparting function. Supi)ort for the DMA port consists of a two octaword DMA transaction buffer, a command/address register with increment capability, and a next page frame (NPF) registet. Support for the mapped master port consists of a command/address register with increment capability and a· single longword data register with a mask/status register. Support for the slave port consists of a command/address register and two longword data registers, each with a mask/status register. A more detailed functional description of the registers is described.
. 4-146
Confidential and Proprietary
--
PreJiminary'
Master 1:'ort ,&gistei:·.
The master port of.~~ B.CAI is ~ for II bus-jpitiated ttansfers to the VAXBl bus. The BCAI
provi~st:egis~.fpr ~mast~ :w,r~s"':"""a high-speed DMA master port tha~ is optimbed forb~k
~~·.and a 1:98.pJ;n~tel' port. This allows a local processor to perform longword aq:esses to the
VAx;Bl~ in the_ml~e Qf. a.blQ:CkDMA tran.s·ction without~ng the sta~:of thf! previq~
tra.Psaction to be~ The main difference between the tw() roaster ports is the size o£ their da~a
buffers. The DMA master port has two octaword buffers andcthe lt,lap master .port has a single
longwqt,tl data n:gistF. Both nia~ter,POrts have ~ c0mmanpt~.~ n!~is~ ~th autoinqeme~t
cap~ility and.page-croSS detectil)ri. tfie l)b;(A master port inclqdeS ant:n page frame ~Ster that
holds the iµap for:the ~t page. . . :
· · .· ' · · · .·
MastFtr~ 4 ancl~ :O:MA Data ~TpeDMA data bµf~ g;>nsi~;s Qf ei,s-Pt con~iguously ·a~ !.;>ngwords. of read/write ~mory org~d .~ twp1ocl11~.Pbuffer:s, 4 and B. These
buf,f~ fl,llow otie transaction buffey. to l)(:: accessed hy an U b~ tran8a¢on \lf~ the other is
~ed by a master V~l bus ~sactlon., 'fo s'.µpport all· pos~bic.~<kess alignments, the :SCAI
byte multiplexer directs an II ~us transfer tp ~ .follf sequentj.al~~ .in the t~ctiop buffers.
An overflow that occurs when reading or writinsfrom either octawg,rd is auto~tically directed to
octawotd. ... . the first bytes. of t~.other octaword,: The;ef?re· the.f()# lo~rd of an UM1ttmallY aligned
octaword transaction can extend into the £list i:hree.bytes qf the cith~ Each DMA <J~~ huffer ~te lC>Cation ~ a c~r~~g ~aU4 btt~'A k~.: 1 lridfcates that the byte is valid. All valid bits~· cleareq wh~ the ij CJ,RVB ~is ~.rtcd or w~n anJf bus ~ad
operati~n is [>erformed"with an address of 1F (hexadecimal). When a write' ope~tion frop:i th~n
bus to a byte Jocation within the DMA data buffer is performed,.the correspondin.g valid};>it. f9r
that location is set. Wliendata is .read by the BCih\lS, the wJj.d bits are supplied to the BCI
I<: 3:0 > lines and canbe u~ to support the VAXBI b~s mai;ked write e<;>lllll1ands._.Typidllly a user would clear the valid bits, load a portion of an octaword into the DMA data btiffet. arid then initiate
a VAXBI writemaskttallsfet.
· .
Master Po~ M81? Data. ~~-TPis, resii;ter -~~re~ the.data t() be read anlwritfe11 for map
master port transactions. The maskfs~tus ~ster~s50ciated,~tl1the ~~ ~ster is separately accessed from the II bus by bits 19:16· ·of the address imm~tely followirig the data register
address. When the data l:egister is accessed by the B<:::I bus, the.tnask/smtus regi'ster ttans£ers the
information on the :SCI l< 3:0 > lines.
·
~ Pprt COnt~Address ~j~~'J;he ~Ster port.Q~ adc,iress re!#ster artd the m~ster port map address re~ster are u~ed to pfc>,Vide the VA~Jc\~.a&,he~ forJhe com~an#Jad~ss.cycle of
fbe. a VAXBI master porttran~act~on. If Il'. _IjijA~ .~N:A ()f,tf.~JI\JC: itmJh1es. ~asserted
when the. com::sponding addre_ss. register: i.~ rea~1 from the :ac;l l;ius, the. low-order 9. bit~ of ~t
address are incrementedby the size of the transaction as indicated by thelength field {bits 3PO)of
the address register. This increment feature enhances block DMA transfers because'the user is not
required to reload the address for every VAXBI bus transaction during seg_uen.t~aJ. transfers. Parity
for the two bytes affected by the in~rement js ~utomat;ica"y rec!Y~ted., ·. .
· ·
The access time of the address registers is SlUl'le as the other re~ters. However, a minimum of 500
ns must be allowed between tW'o BCI read operations to the address register with the increment feature.enabled. If this. time is not allowed.;. the present address will be read correctly, but. the next reacloperation will result® an incorrect .address.. The INC ENA:signal.that h esseQ.tially the.carry
input to thelowest bitofthe incrementer must also be asserted 500 ns before a ilCI :read 0peration
of the ·associated address register.
Confidential and Proprietary
4-147
-
Preliminary·.
The master port DMA command and master.port map command registers a.teusaHo J.)rovidethe VAXBI command for the command/address cycle ofa VAX'BI master pott transaction: From the II
bus, the command register is located in the lbngWClrd immediittely above the address register and
the com.mmand information is contained in bits 19:16 of this register. For the BIbus, the command
and address registers are at the same location. When the command/address register is read fromthe
BCibus, the cdmmanddata is transferred ornhe BC1l<3:0> lines arid the address data is
trim.sferredon the BCI D < 31:00 > lines. .
Next Page Frame Register-The OMA master port has a Next Page Frame (NPFl register that can
be preloaded with the upper address bits for the page following the current page. \Vhen the OMA
address register reaches a page boundary and the II DMPGOVF signal is asserted, bits 31:09 of this register are autofuatically transferred to the DMA itddress re~ster bits 31:09:. This feature can
increase throughput during block DMA transactions. Instead of halting while waiting fora new
map, VAXBI transactions can continue for as long as a page while the adaptercontrollerfetches'and
loads the next map. If an update of the NPF register occurS eoncurrenf with the second'page
crossing, the value loaded into the DMA address register is unpredictable.
'
The low-order 9 bits of the D&{A address are not loaded from the NPF rc;;gistei; so the II DMA
PGOVF signal remains asserted tintil the next address increment or until an II bus.write tran~action
occurs to the DMA address register or the NPF register. When loading the NPF register from the II
bus, the lo'W-order 9 lSits are not stored. Therefore, parity for the second byte (II D < 15:08 >)must
be calculated as if the II DOS bit was zero. The NPF register cannot be directly accessed by the BCl
interface.
S1ave Port Registers
The BCAI provides a commmand/address register and two longword data registers with associated
mask/status registers for the slave port.
·
. ·
·
Slave Port Data Registers 1 and 2-Slave port data register 1 and slaye port data 2 registers are
read/write regil>ters used for slave read transactions and for slave write trans11-ctions. These registers.
allow a read response code to be written into the the slave read data status register from a II bus
device having to rewrite it following a slave write transaction.
· '.
.
SLwe Port Co:mtnand/Address Register~The slave port command/address registers are used to
store the command and address data for the command/address cycle of a VAXBI bus master port
transaction. From the II bus, the registers are addressed separately with the command register
located in the longword immediately above the address register. Thecommand information is
located in bits 19:16 of this register. From the VA:XBl b\ls, the command and address registers reside
in the same location. When the command/address register is written from the BCI interface, the
command datais loaded from the BCI I<3:0> lines and the address data is loaded from the BCI
D<31:oo:> Hlines.
Page Boundary Detection
VAX processor memory management functions require that memory addresses are mapped from
virtual to physical space on a per page basis. To facilitate the mapping process, the BCAI provides the II DMA PGOVF signal for theDMA master port and the II AP PGOVF signal for themap master
port. These signals indicate to the processor that an address register hasincremented beyond a page boundary. A ffag bit in each address register indicates that a carry signahvas produced when an
address increment occurred. During a BCI read operation, the UDMA PGOVF and Il MAP PGOVF
signals are updated with the contents of the respective carry signals when the BCI RS signal is
asserted. Therefore, when a BCI read operation of an address register causes the address to increment from all ones to all zeros, the overflow bit for that register will be a.sserted. The
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Confidential and Proprietary
frtn.;..u-11!u-v!-;~~- y
VAX.lll'18743
subsequent read and increment operation will deassert the PGOVFL bit. The II M}1~ PG.Q'VF bit is
also deasserted by II bus write operation to the map address register. The II DMA PGOVF bit is
deasserted by an nbus write operation to either theDMA address register or to the next page frame
register. If.a.BCI interface read operation results in a page crossing at the Sttme time an R bus write
operation occursto one of the registers that affect that II PGOVF·qit, the state <;if the IIPGOVF bit
is unpredictable.
· Parity Data Path
All parity gene~d or checked by the BCAI is oddparity, A paritybit is associated with~ byte of data in the BCAI register file, including bytes that contain command, mask, or status bits. For
the 4-bit command, mask, or status information, the parity is calculated and supplied based on the
complete byte that includes the four zeros above the register. B~e parity is sup~lied .l>y the l.l~r on
the II P< 3:0 > during II bus read operations. Nonexistent hyteS;t\dudingupper bytes\ofslilfted read to nonwraparound registers and register:> th~t are. de{ined as zero.~ ~ as all zeros. The
parity bits are read as ones, TheJ;efore nonex4t~ byte~ have good p~ity.
During master-write or slave-read transactions that result in data transfers from the BCAI t<l the BIIC, the BCAI compares the~ parity bitsfrom the user after the byte parity and data have been transferred through the BCAI, with the· resultsof its ownintert)al parity generator that operates on
the BCI D < 31:00> and B.CI I< 3:0 > lines of the register file, Ihhe parity bits do not llgree, the
II PBAD line is asserted. The II PSEL line sele(:ts w~of the two sourcesofp~ity is passed.to the BCI PO line. Hthe II PSELlineis alow level, the user supplied parityisgiventothe~IlCinterfare. Therefore if an error has occurred in the BCAI or in the II bus interfilce, the bad parity is passed to the VAXBI bus where it will stop the memory write operation and the transaction. If user parity is not required, the IT PSEL line can be connected to a. high level and the parity wfil match the data transferred to the BIIC regardless of the previous parity' conditlollS;
During master read and slave write transactions that transfer data from the BIIC to theBCAI, .the
BCAI generates parity based on the incoming Bel D < 31:00 > and aCI I< ):0> line information
and compares the result with the BCI PO line from the BIIC. Hparity is different, the II PBAb line is asserted. An internal parity generator also determines the parity for each byte of data that is then
transferred through the BCAI to the II bus interface. The byte parity is read on the II P< 3:0> lines when the register file is read.
The state of the II PSEL line is latched by the assertion of BCTA.S signal. The II PBAD signal is automatically deasserted when the BCfRS or BCi WS signal is asserted and is updated when the
BCI RS or BCI WS signal is deasserted.
· Initialization
All the valid bits of the BCAI are cleared by the assertion of the II CLRVB signal or by an II bus read
operation with lines II A< 6:0 > =1111111. The II bus read operation enables the microprocessor to
perform the initialization without the use of external logic. Other states within the BCAI are undefined during the powerup sequence.
Ha write mask is the first DMA master-port transaction to follow the powerup sequence, the valid bits may have been cleared by the II CLRVB signal but the data bytes and parity bits that are not loaded will be undefined. The mask bits for those bytes will be zero and the BCAI and the VAXBI interface will still be checking their parity. To prevent erroneous parity, the correct parity should be entered by the user, the II CRLVB line asserted, and the transaction started at a known state.
Confj~ntial and Proprietary
4-149
-
·Sp~tipns
The. mechanical, electrical, and environmeatal .specifications. for .the· VAXBl interface are. as follows. :fhe test conditions for the values specified are as follows unless specified otherwise. ·Junction temperature (T1): 0°C to 125°C · Supply voltage (Vcc): 4. 75 V to 5.25 V
Mechanical Configuration The mechanical dimensions for mounting the 133-pin VAXBI interface package are shown .in AppendixE:
··AbsOlut.e Maximum Ratings
Stresses greater than the absolute maximum. ratings may ·cause permanent damage to a device. Exposure to the absolute maximum rating conditions for extended periods may adversely affect the reliability of the dc;vice. · Pin voltages: -1.5 V to 7.0 V · Operating junction temperature range (!1): 0°c to U5°C. ·· Storage temperature range: -55°C to U5°C · · Package dissipation: 3.0 watts
Recommended Operating Conditions · Supply voltage <Vcd: 4. 75 V to 5.25 V · A~bient tempera1:Ure operating range (TA): 0°C to 70°C
'4-150
Confidential and Proprietary
de Electrical ~tics Table ) contai.115.the ~ electrical parameters for the input and outputs of the BeAI :interface cltlp.
'.Jilble? ·.vum 1s14' de lliPJt,'Pf Output~.,.
Symbol Parameter
'lesteonditicms ·· · ~ntS
'Mini· Mu.
Vrn
High-level
2.0 Vee
v
input voltage
Vn.
. Low-level
input voltage
-l.O.
0.8 v
Von
High-level
LFII lou
2;7
v
output voltage
VoL
Low-level
output voltage
I.... =Il loL
0.5 v
Ion
High-level
\T-=:'II Yon
-400
A
output current
101
Low-level
V""1 ~II·V·:.·o'i.
hlA
output current
I,
Input current1
±20
µA
Ilu
Input current
open latch1
-230.
25 PA.
Ios
Output current
shortd.rcuit3
-150
mA
Ion
EnableJine
current
BCtMDE, Bti SOE, 50
Illrn' inputs
200.
µA
Inn
Power supply
current
500
mA
VBB
Substrate bias
voltage
Generated internally
-3.6
-2.4 v
Cm
Input/pµ~wit ·
O<Y19.<.Vcc
10
pF
capacitance
>, <: 1Applies to the f~g three-state bidirectional signals: BCI D < 31:00 BCII 3:0 >, BCI Pei,
IID<31:00>, andIIP<3:0>;
IILA applies when the following inputs are open and I!whencfosoo: OCIA<t3:0;:,., II M<3:0>,
II A< 6:0 >, and II PSEL. . ...
. . . .
. . . .,
2Not more than one output must be short circuited at a time and the duration of theshort must not
exceed 1 second.
·
·
Confidential and Proprietary
4-151
-···
ac Electrical Characteristics Figure 6 shows the. signal timing for axead transaction from the BCI bus interfaceand Table 6 lists the timing parameters. Figure 7 shows the signal timing for a write transaction from the BCI bus interface and Table 7 lists the timing parameters. Figure 8 shows the signal timing for an address increment and Table 8 lists the timing parameters. The signal timing for a II bus interface read transactio:n is shown in Figµre 9 and the timing parameter~ are listed in Table 9. Table 10 lists. the timing parameters for a II bus interf~ce write transaction shown in Figure 10.
BCIA<3:0>
BCISLS BCIMLS
BCI 0<31:00> BCI 1<3:0> BCIPO
Figure 6 · VAXBI 78743 BCI Bus Interface Read Transaction Timing.
Symbol
tBSI
tsm tBASW tllASSt tBASI
Tuble 6 · VAXBI 78743 BCI Bus Interface Read Timing Parameters
Definition
Requirements (ns) Min. Max.
BCIA<3:0>.to BCIAS setup time
15
BCI A< 3:0 > to BCT"AS hold time
10
BCI address latch strobe width
15
BC! AS to BCI RS setup time
45
BCI A< 3:0 > to BCfRS setup time
45
4-152
Confidential and Proprietary
...
~from BCI'l{S hold time
tan
Read strobe width
tBPCH
OutJ)llt latch close time after read access Read access time
BCI output enable time
BCI QUtput disable time
error . Parit;y output delay
~ments(ns)
~. " M~, 15
100 110
60
BCIA<3:0>
BCI 0<31:00> BC11<3:0> BCIPO
llRS
Figure 7 · VAX.13178743 BCI Bus Interface Write Transaction Timing
4-153
-
Symbol
tns1
tam
ts.uw ts.us2
tBAS2
t11AH2 taASH2 tsns1 tllll» tllllw tsPCH tsnsw tas2
tBH2 tPJ!D
tmn
Table7 · VAXBI 78743 BCI Bus Interface Write Timing·~
Definition
Requirements (ns)
Min.. Max.
BCI A< 3:0 > to BCI As setup time
15
BCI A< 3:0 > to BC'iAS hold time
10
BCI address latch strobe width
15
BCI AS to BCI WS
45
BCI A< 3:0 > to BCI WS setup time
45
BCI A< 3:0 > from BCI WS hold time
15
BCI AS from BCI RS hold time
15
BCi15S to BCI WS setup time
0
BCI D < 31:00 > to BCI WS setup time
0
Write strobe width
90
Preset width (BCiRS and BCI WS unasserted)
40
BCI data strobe pulse width
15
BCI data strobe setup time
15
BCI data strobe hold time
Parity error output delay
10
60
BCI WS deasserts to II read (same register)
0
llA<6:0> II M<3:0>
II 0<31:00> II P<3:0>
Figure 8 · VAXBI 78743 II Bus Interface R.ead Transaction Timing
Confidential and Proprietary
-
Symbol
tIAa· tusm t 15a tIPCa
tlOE
II A< 3:0 > to II AS setup time II A< 3:0 > to II AS hold time
II address latch strobe time
ifAS to II RS setup time II A< 3:0 > to II RS setup time II A< 3:0 > to II RS hold time 'ifXS from If'E hold time
Read strobe width
. Preset width (iiRS and lfWS unasserted) Read access time
II output enable time II output disable time
11.A.<3:0> . llAS
Requhemenu (m) Min. Max.
15 10
. 6t) 60
90 40 40
II 0<31:00> 11.P<3:0>
Figure 9· VAXBI 7874311 Bus lnteiface Write Tmnsaction
Confidential and Proprietary
4-155
-·
Preliminaey
Symbol
t!St
trn1
tlASW tIASSl
tlASZ
t1AH2 tlASH2
tms1 tms2 t1sw
t1PCH
tmsw t1s2 tlH2
·Definition
ll A< .3:0 > to II AS setup time
II A< 3:0 > to 'ffi\S hold time
II address latch strobe time II AS to~ setup time
IIA<3:0> to IIWS setup time IIA<3:0> to IIWS hold time
II AS from II RS hold time
II DS to II WS setup time IID<31:00> toIIWS Write strobe width Preset width (II RS and II WS unasserted) II data strobe width
II D < 31:00 > and II P < 3:0 > to II DS setup time II D < 31:00 > and II P < 3:0 > from II DS hold time
Requirements .(ns) Min. Max. 15 10 15 60
60
15 15 0
0
45
40 15 15 10
BCI D< 3t:O::> (OMA/MAP ADDRESS ACCESS) - - - - - - - - - - (
)
.
( INCREMENTED
~ rtBRD
'\ .· . · ,-. ···-·- \ . I
- - f T A II DMAINCENA
II MAPINCENA
· F,:85~.tAiH 1
1~-tl:o.P.-o1;.o~·. ·
1
=1.~-·~--- -1.
·
.
-
-
llDMAPGOVF ~~-------
-----~
II MAPPGOVF
c:: IMIN __.j .
I
Figure 10 · VAXBI 78743 BCI DMA and MAP AdJ,ress Increment Timing
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VAXBI78743
Table 10 · VAXBI 78743 DMA and MAP Address Increment Timing Parameters
Symbol
Definition
Requirements (ns) Min. Max.
tBSlt
Read strobe width
90
tBllD
Read access time
troo
Page overflow delay from BCiRS asserted
110
0
70
t111s
II DMA INC ENA or II MAP INC ENA setup to
500
to BCI RS deassertion.
ti\JH
II DMA INC ENA or II MAP INC ENA hold time
10
from to BCI RS deassertion.
t1111N1
Minimum time between BCI reads with increment
500
ti.om
Minimum time between II writes and BCI reads
500
with increment
toro
Page overflow delay from II DMA INC ENA and
520
II MAP INC ENA
Confidential and Proprietary
4-157
· Operates as a memory-rruipped perip~ totlie MicroVAX CPU chip.
· Responds to VA;xBl~ ~+ns ·~sued by ot~ VJ\n~~ ij:iat 11!icess loolI mem~ry ?r
seek to interrupt the BCI3's MkroVAXCPU.
. .
.
.
· Automatically ttanslates any· Integrated Circuit Interconnect (II) bus transaction into the
equivalent VAXBI transaction whenever the II bus transactions references a nonlocal resource.
~ -',
. ,-
- - - r-: -
--
· Fast transfer of data blocks between local memory and VAXBf memory at the reCiuest: ofthe
MkroVAx CPU.
· Description
The VAXBI 78733 bus interface adapter (BCI3), contained in a 132-pin ceramic pin grid array (PGA) package, is used to connect tfi~ ~ Circuit Interconnect (II) bus of the MicroVAX 78032 processor to the VAXBI bus through the VAX.BI 78732 Bus Interface Interconnect (BIIC)
chip. The BCI3 is responsible for the low-level interface functions Of the II bus and the high-level
protocol translation necessary for interbus commtinieatiori. It assiSts in managing the exchange of
data and provides ttans~nt translations of read and write tlaris4ctions, error conditions, and
interrupt requests.. A block diagram of the BCI3 is shown in Figure i.
.--.........---. - - -. - -1
I
I
I
I
I
I
I
I
I
I
I
I
I
I I v - - - - - - - . , . . . - v "-:r<,_......_"-'---'--1/
I
I
lI _ _ _ _ _ _ _ _
_ _ _ _ _ _ JI
Figure l · VAXB178733 BCIJ Block Diagram COnfidential and Proprietary
:4-159
Prelimhwy
The BC13 translates protocol, l'QUtes transactions between bQses, and. detects and resolves bus
transactions that result in a deadlock condition. Read, write, and interrupt request transactions
from the processor are automatically translated into VAXBI transactions. This includes the transfer
of data and the exchanges of error information when necessary. Devices on the VAXBI bus can access the II bus resources and interrupt the operation of the processor.
In addition to supporting processor nodes, the BCI3 can also be used in intelligent MicroVAX-based peripheral devices. It contains a 5 Mbyte-per-second datamover for high bandwidth block d11ta
transfers used by JjO devices.
· Pin and Signal Descriptions
The VAXBI 78733 is a 132-pin interface that functions with the input and output/signals and voltage and ground connections described in the following paragraphs. The pin and signal
descriptions are grouped by II bus signals and by BCI bus signals. The pin assignments·are shown in
Figure2.
. . . . 14 13 12 11 10 e a 1 s 5 4 3 2 1
p ·
· · p
N ·
· N
M ·
· · · .· · · M
L
L
K ·
K
J ·
· J
H · G ·
BCl3
· H
· G
F ·
E ·
D ·
c ·
(TOPVIEW)
F
· E · D
· c
B · A ·
· · · · · B
··· ·A
14 13 12 11 10 9 8 7 6 5 4 3 2 1
Figure 2 · VAXBI 78733 Pin Assignments
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Prelimmary
II Bu& Signals
.
.
Table 1 is a summary ofthe input and output signals that connect to the U blJ,S. It also includes the
power and ~nd connections. The signal functions are described in thf following paragraphs.
Pin
N3,P3,MJ,P2 N2,Pl,M2,N1 K3,Ml,L2,L1 K2,KlJ2Jl Hl,G2,Gl,G3 F1,F2,El,E2 Dl,D2,Cl,E3 Bl,C2,Al,C3
lld>le l · VA;XBI 7$7Ull Bus Ym and Signal Summary
Signal
'J'.n. put/Output ~ -.
II DAL< 31:00 >. input/output II Data address lines < 31:00 >-Supplies
dabl and address information.
N4,N6,N5,M6 IIBM<3:0> input/output II Byte nWk <3:0> lines-Specifies the bytes to be read or written.
N7,P5,M7
M8
M9,N12,Pl4, M12 NS
N9 Nil
P4
IICS<2:0>
HERR IIIRQ<~:O:>
··iiRI:"S
UDMR IlRESET
IIWR
input
II Cycle status <2:0> lines-Used with the
µ.e 11 WR line, ~:!;,pedfy the,, o~ratj~n of.
current cycle.
input/output
oµ~put
ftt~~pt ~t, ~3:Q;;l> .·fuie~-In~ertupt
~quest ~PUo ~J{:!.14, . . . ., ·.
inp\lt
II Retry~~ sttobe~tin.tro~the lo~ of the J:e!;l:Y:ad~srefds~er.
. output
.input input
II Write.:...::~d'es iead'anchvtifu c6ritrol of
the·--hus~
,:-\'
P6
HAS
input/output I I Address ~tr~.-..-I,ri~ates, when valid
J
'
addre~~1 dycl~ :status, anCl write' and nia5k
infornuition' is available.
P7
inpu~/outpµt n Dahl ~~,.~.Jndica~ .wlin data, aan be
,tnmsf~ .onJ;he bµs. .
.
P8
IIRLOE·
II Retry latch ·output enable-.Enables the .transfer of the retry · address latch infor· mation.
P9
input/output II Dat~ buffer enable~Control~the Dl\L bls
transceivers.
PlO
input/output II Ready-Indicates the status ofadata transfer.
For In~.Us~ Only
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....
Pin
Pll
P12
PB
L13
Signal ·JI RETRY IIDMG IINLMR
'1DD
D3,D12,L3,L12, V00
C5,El2,E13,M4 Vss M5,M10,Mll,
Preliminary
Input/Output Definition/Function
input/output n.~~ry~Requests ,a change in.bus mastership and indicates a locked location.
input
II DMA grant-Indicates that the BCI3 has been granted the bus for a DMA transfer.
input
II Nonlocal memory reference-Indicates that the memory space is not local.
input
Test output disable-Causes the BCI3 outputs to become a high impedance. Used for test purposes.
input
Voltage-Power supply voltage
input
Ground-Common ground connection.
UData arid Address Lines (Il DAL< 31:00 >)-These lines transfer data and address information
between the BCI3 and II bus. Il Address Strobe (fi'AS)-The.II bus master asserts this signal to indicate that a valid address is available on the II DAL< 31:00 > lines and that valid status information is available on the
II CS< 2:0 >, 'IfWR, and !I BM< 3:0 > lines. The subsequent deassertion of this signal indicates the end of the bus cycle. This signal is synchronized internally by the BCI3.
D Data strobe (lfDS)......The II bus master asserts this signal during a read and interrupt acknowledge transaction to allow the slave to transfer data on the II DAL< 31:00 > lines. When the line is deasserted, it indicates th.at the selected slave may release the DAL<31:00> lines. During write cycles, this sig~al is asserted to indicate that valid data is available on the
DAL< 31:00 > lines and deasserted to indicate that the master will soon release the DAL< 31:00 > lines. This signal is sychronized internally by the BCI3.
ri Data Buffer Enable (II DBE)-This signal is used by the bus master to enable the DAL< 31:00 >
transceivers. II Byte Mask (Il BM< 3:0 >)-This signal is used by the bus master during a read or write transaction to indicate which bytes within the data longword are to be read or written. II Ready (II RDY)--This signal is asserted during a read transaction to indicate to the bus master that data is ·ready for transfer. During a write transaction; itis asserted to indicate to the bus master
that data has been latched. The sigrial is sychronized internally by the BCI3.
U Bus Error Indicator (II ERR)-Assertion of this signal by the BCI3 during a MicroVAX-initiatei;:l II bus transaction (other than an instruction prefetch or interrupt acknowledge) causes the processor to perform a machine-check exception. Other devices on the VAXBI may assert the
·n ERR signal when the BCI3 is II bus master to indicate that· the current II bus transaction has
failed.
Confidential and Proprietary
n R.O$et (i'i,ljSit'fhl1 at:iether devi~ on.the II bus asserts this signalfor at~ 2 miel'Qset:onds, the BC13 Will reinitialize itself. The signal is synchronized internally by the BCI3.
U \V~ 011.'t'Ib-:-Thjs sigpal specifies. the direction of a data trans£er on the Uhus... IlCycle Status (UCS.i:: 2t0>~Together with the f t sigflal, these lines indicate the curtellt.bus cycle type requested by the II bus master. Table 2 lists the bus cycle 5elections. ·
WR*
CS line*
2
1
H
L
L
H
L
L,
H
L
H
H
L
. H
H
H
L
H
H
L
H
H
L
H
H
L
L
L
L
L
L
L
L
L
H
L
L
H·
L
H
L
L
H
L
L
H
H
L
H:
H
*H =high level, L =low level
0
L'· · H L
, H
L L L L
L H L H L
Ii
L H
·· las~ ty,pe
notused
ootUSed
not used
mtertuPt~ledge ~(l stream)
Read lock
Read(D stream, modify iq~ent), .·Rea4ff:lst1'J!~: l}O moclify itltent)
·· not4ls&I ··
not used not used .~t~~.
.not used
Writ~ 11nlock not Used write {D stream)
Il Interrupt Requests (II IRQ < 3:0 >)-These lines are used by the BCI.3 to ~ue~t qu.s
mastership from the MicroVAX. Each line corresponds to an interrupt priority line IPLaS'listedjµ.
Tuble 3.
'·
Table 3 · VAXBJ787?.l~pt Requtst Line Assignments Requestlevel (hexitdecitnal)
IPL17
U'Ll6. lPL15
IPL 14
Confidentialand Proprietary
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II'.DMA Request (H DMR)"-This line is· asserted by tlie'BCB, tO request bus ~srership from the
MicroVAX CPU.
.
to II DMA Grant (ll DMG)-This line is asserted to indi<!ltte the BCIJ that it has been griinted
mastership of the n bus. After the UDMR line is negated, this line mus.t be negated before the
II DMR signal can be reasserted for the next II bus master transaction sequence.
II Nonlocal Memory Reference (ll NLMR)-The memory controller asserts this signal to indicate that the address of a memory-space II read or write cycle does not reside in local II bus memory.
II Retry (Il RETRY)-This signal is asserted by the BCI3 to request that the MicroVAX relinquish
bus mastership and reissue the current .II bus transaction at a latei: time. The memory controller asserts the II RETRY signal in response to an II blls read lock to indicate that a location is locked~
The BCI3 assumes that this signal will not be asserted when it is II bus master except in responseto
the II bus read-lock transaction.
II Retry Latch Strobe (IIRLS)-This signal is·asserted to latch the address information on the II DAL< 31:00 > into the retry 3ddress register. When negated, the retry address register is
transparent.
II Retry Latch Output Enable (Ii RLOE)-This signal is used to assert the contents of the retry
address register on the Il DAL <31:00 > lines.
BCI Bus Signals
Tuble 4 contains a summary ofthe input and output signals that connect to the BCI bus. The signal
functions are described in the follOwing paragraphs.
Tuble 4 · VAXBI 78733 BCI Pin and Signal Summary
Pin
Signal
Input/Output De6nition/Function
B2,A2,C4,A3, BCID<31:00> B3,A4,B4,A5, B5,A6,B6,A 7, C7,A8,B7,A9, A10,B9,AU,C9, A12,B10,A13,Bll, A14,Bl2,B13,Cll, Bl4,C12,Cl4,C13
input/output
BCI data <31:00>-Used to transfer data between the BCI3 and the BCII.
B8,C8
BCIPOWER input
BCI power-Monitors the de power of the
BIIC.
C6,C10
BC!GNP
input
l3CI ground..,-Common ground reference for the BUC signals.
E14,F13, D14,D13
F12
BCII<3:0> BCIMDE
input/output BCI Information < 3:0 >-Transfers command values read status and write masks.
input
BCI Master data enable~Indicates when data on lines BCI D<31:00> and BCI 1<3:0>
should be.transferred to the BIIC.
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Pin
F14
:SCI CLE
input
GU
BC!SDE
input
Gl3,G14
BCIRS<l:O> output
H12,K14J13, J12,L14
P14,K12
BCIBV<4:0> input BCIRQ<l:O> output
J14,Hl3,H14 BCISC<2:0> ineut
M13
BCITIME
input
M14
BCIRAK
input
N13
OCIPHA~E
input
N14
BCIMAB
output
VAXBI 78133
BCI Commapd la~h enable-.-Indicates when
BI command/address infurmatiOn is available
during slave-port operation.
BCI SlaV¢ d~ enable-.-Iridicates when the BCI3 should transfer data .on the B.cI
0<31:00>: andsq<.3:0> lines. BCI Slave response < 1:0> lines-Used by the BCU to acknowledge the slave-port
operaµon.
the BCI Event <4:0 > lineii-,Contains event
status information from the BIIC.
BCI Reqilest.;...:.InitiS.tes ·BUC master-port
operations.
code Bel sta;e <2:0> lines-U~ to trans-
fer status.information durlDg BllC slave-port
operation.
BCI tilTtC-A. 20-MHz TTL clock reference
signal from the BUC,
Bq ~uest acknowledge-P19vides transaction timing.
': , ,,',,
BCJ Phase--A !}~MHz clock reference signal fromthe BBC.
BCI M11$te~'abClrt-Used to halt current BIIC
master~{>Qrt,g~tion.
BCI Data (BCI D < 31:00 >)-These lines are used to exchange VAXBI data and address field values with the BIIC.
BCI Information (BCI I< 3:0 >)-These lines are used to exchange VAXBI command field values, write masks, and read status with the BIIC.
BCI Master Request (BCI RQ<LO>-These lines are used to initiate BIIC master-port operations.
BCI Request Acknowledge (BCI RAK)-This signal provides timing information for BIIC masterport operations.
BCI Next (BCI NXT)-This signal provides timing information for BIIC master-port operations. BCI Master Abort (BCI MAB)-This signal aborts current BIIC master-port operations. BCI Master Data Enable (BCI MDE)-This signal indicates when the BCI3 should transfer data on
the BCI D < 31:001 and BCI I< 3:0 > lines during a BIIC master-port operation.
Confidential and ,Proprietary
4-165
-
are BCI Slave Respe>nse (BCI !$ ;s;J;O>)-1}iese. s~pal~ µsed by the BCI3 tq. acknowledge BIIC
slave port action when it is aCt:ing as the selected VAXBI slave.
·
BCI Command I..atdi Enable (BCI CLE)-This signal ·indicates when VAXBI command/address information is available on the BCI D<31:00> and BCI I<3:0> lines during BTIC slave-port
operation.
BCI Slave Select Code (Bel SC<2i0> }-These signal provide status information during BIIC slave-port operations.
BCI Slave Data :Enable (BCI SDE)-This signal indicates when the BCI3 should transfer data onto
the BCI D < 31:00 > and BCII < 3:0 > lines during BIIC slave-port operations.
BCI Event Code Information (BCI EV< 4:0 >)-These signals provide status information during BIIC master-port and slave-port operations.
BCI Time (BCI TIME)-This signal is the local BI node's version of the 20-MHz VAXBI dock reference signal.
BC.I Phase ("""uc=1"""p"""HA....,..,.S""'E')-111.is signal is the local VAXBI node's version of the 5-MHz VAXBI dock reference signal.
Test Output Disable (TOD)-This signal forces all BCI3 outputs into a high-impedance state. It is intended to support board-level manufacturing tests andindudes an internal pullup circuit.
Power (V1>1.) and Ground (Vss)-V00 connects to the power supply positive voltage and Vss connects to the power supply and signal ground reference.
· Architectuml Summary
Figure 3 shows the internal· organization of the BCI3 interface that includes four major subsystems-an II bus controller that initiates and responds to microprocessor bus transactions, a VAXBI master controller that initiates system bus transactions, a VAXBI slave controller that responds to the bus transactions and a datamover controller that coordinates the high-level DMA operations. Each is individually controlled and the three bus management subsystems each contain a 36-bit (32-bit data and 4-bit tag) bidirectional data ·bus. These four subsystems operate independently and can sim&cineously service multiple transactions.
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Preliminary
CONTROL AND STATUS FOR cSRs
VAXB1787J3
REQUEST 'STATUS
REQUEST STATUS
REQUEST STATUS
REQUEST _ _ST_AT_u_.s_...,... CVOAXf\IBTIRSOLLALVERE
CONTROL ;il,l\ID STATUS FOR INTERNAL VAXBI MASTER
BUS AND BCI INTERFACE.
CONTROL ANo.srAT\JS .F.()R INTERNAL II BUS AND II
INTERFACE.
CQNTROt. AND STATUS FOR INTERNAL VAXBI SLAVE BUS
AND BCI INTERFACE
Figure 3 · VAXBI 78733 Internal Subsystem Otganhation
or In addition to performing requests fromthe MicroVAX .controll~i; the BSI3 autotnatically
translates thetransactions directly into VAXBI trans~ctions and ~~nc1s fu all interru~t ~cknow'l~.·
edge tran$actions. It interrupts the MicroVAX it aniriterrupt reqttest·is received from another VAXBI node. In response to DMA requests from the VA:XBrbus; the Bl:;!I3 accesses the Ilbus using
the standard DMA protocol:
Memory IWeftmf:es
When the MicroVAX processor references a memory space location, the memory controller or eqU:ivalent logic determines when the address space is within .the range al,leeated to the BGI.3 interface. The controller asserts the nonlocal memory (II NLMR} signal to indic"te·the reference is not a me.mOry.location, The BCI3 translates ihe reference ,into the .equivlitent VAX:SI·trailsaction, tm.nsfers it to theVAXBl bus,. and reports the. results ta the; M.ictioVAOC using the U bus read and write protocol. The response of the BCH t6 the MicroVAX 1/0sp«te reference~ dePendson .the address . range
specified. If the address of the MicroVAX is within the OOde privatt¥space, the response of the BCI.3 depends the location accessed. The address assigbments of. the Mlcri>VAX\md tM·allocated space
of the BCI3 interfacer.\re shown irJ. Figure 4.
Confidential and Proprietary
4-167
-
Preliminary
VAXBI187J3
20000000 20040000
NODE PRIVATE SPACE
20100000
T.________ 3FFF FFFF
J_.'
2o040000
2008 0000 2008 2000 2008 4000
IBOOT ROMSI
LOOPBACK SPACE BC13 (CSR)
USER'S CONTROL AND STATUS REGISTERS ICSRl
2010 0000
Figu7e 4 · VAXBI 78733 MicroVAX Node Private Space Address Assignments
The lowest 256 Kbytes of II bus address space is assigned to the ROMs that contain the bootstrap program. The next address range consists of an 8-Kbyte loopback space and the BCB will respond to addresses in this range by using the loopback feature of the BIIC to permit access to the BIIC and BCI3 nodespace registers without performing VAXBI transactions. ,
The BCI3 control and status registers (CSRs) are located in the next higher 8-Kbyte range. These registers are accessible through the II bus and are accessed by the BCI.3 without involving the BIIC or VAXBI bus. The user CSR space is ignored by the BCI3 and may be used by local II bus devices. If the address of a II bus transaction is not within the private nodespace, the BCI3 translates the transaction into a VAXBI bus transaction and reports the results to the processor usj,ng standard read or write protocol.
Intettupt Vector Requests-An II bus interrupt request can be initiated as a result of a transaction from the VAXBI, by the BCIJ interface, or by a device on the local VAXBI bus node other than the BCI3. When the MicroVAX acknowledges an interrupt request, the BCI3 serves as the local II bus interrupt arbitrator by determining which of the outstanding interrupt requests will be serviced by this transaction. If a VAXBI interrupt is being serviced, the BCB will solicit an interrupt vector from the interruptj,ng VAXBI node using the VAXBI IDENTtransaction. If the interrupt bej,ng serviced is a result of a VAXBI IPINTR (IPL 14 .only), the BCB returns a fixed .vector of 80 (hexadecimal).. If the interrupt is BCI3 initiated (IPL 16 only), the BCI3 will return a fixed vector of 58 (hexadecimal). If none of these conditions are pendj,ng, the BCI3 interface returns a vector on behalf of a local device-the value of which depends on the IPL of the interrupt vector as follows:
FO (IPL 14), F4 (IPL 15), F8 (IPL 16), or FC (IPL 17).
· Register Description
The BCI3 interface contains two groups of registers. The nodespace register file is accessible from the VAXBI bus and consists of 12 general purpose l'egisters and a two-ported toggle registers. The BCI3 private registers are accessible from the II bus and consist of 28 registers that are used to control the transfer of information, to report status, and to generate interrupt requests.
4·168
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VAXBI737l'J
Nodespace Registers
The BC13 '.:iruerface contains 14. nodespace registers used .to facilitate ·COm.tnWlieatiombetween
different JU nodes~ The nodespace regist.ers and address assignments are shown in Figure 5.
31 88+200
00 GENERAL PURPOSE REGISTER 0 181 RXCD ONLY)
BB+204
88+208 88+20C
GElllERAt.: PUPIPOOE REGISTER 3
BB+210
BB+214
GENERAL PURPOSE REGISTER 5
88+218
GENERAL PURPOSE REGISTER 6
88+21C 88+220 88+224
GENERAL PURPOSE REGISTER 7 GENERAL PURPOSE REGISTER·~ GENERAL PIJRl'()SE REGISTEfl ~
BB+228
GENERAL Pl>RPOSE Rl!tnsre1no
B8+22C
GENEflAL·PUfWOSE REGlSTER 11
88+230
TOGGLE REGISTER A SET PORT
-----------------------
88+234
TOGGLE REGISTER.~ CLEAR. PO.RT
88+238
B8+23C
Figure 5. · V4Xl.U 787)3 Node$paet: ~gjster File .
General purpose registers 1 through 11 and the two toggle registers are accessed by 16 VAXBI longword addresses; bb+200 through bb+23C (hexadecimal). The nodespace registers can be
locked by a read lock command issued to any one register. This command locks the entire set until a
write unlock command is issued.
Each of the toggle registers can be accessed from two addresses. Writing a 1 into a bit of the lower address register will set the corresponding bit in the register. Writing a 1 into the higher address register will clear the corresponding bit in the register.
Confidential and Proprietary
4-169
...
Preliminary
VAXBl781J3
Private Registers
The private registers are.accessible only from the Rbus; They may be referenced using longword
length transactions but do not support the masking of write operations. The register file and
assigned addresses are shown in Figure 6. Some BCI3 internal address registers in this address space can be used for diagnostic purposes. However, they must not be used during normal BCI3 operation.
31 . 00
00
BCl3 CONTROL AND STAT:US
04
. BCl3MASK
08
BllC EVENT STATUS REGISTER
oc
BllC EVENT INTERRUPT MASK REGISTER
10
DATAMOVE CONl'IGURATION REGISTER
14
Bl MASTER COMMAND/ADDRESS REGISTER(INTERNAL)
18
Bl.MASTER DATA REGISTER (INTERNAL!
1C
Bl SLAVE COMMAND/ADDRESS REGISTER (INTERNAL!
20
t-
1--
1-2C
Bl SLAVE DATA REGISTERS (INTERNAL)
-
-
-,.
30~
.IJNUSED
'V
40
.._~~~~~~~~~~~~~~~~~~~---i
44
INTERRUPT VECTOR CONSTANT GENERATOR (INTERNAL)
48
Bl ADDRESS REGISTER ·
4C
II ADDRESS REGISTER
50
DATAMOVE DATA REGISTER 0
54
DATAMOVE DATA REGISTER 1
58
DATAMOVE DATA REGISTER 2
SC
DATAMOVE DATA REGISTER 3
60
6{fv
UNUSED
,......
6C
II ADDRESS REGISTER (ALTERNATE ADDRESS,.INTERNALJ
0
DATAMOVE DATA REGISTER 4 (INTERNAL)
4
DATAMOVE DATA REGISTER 5 IJNTERNALI
7 a
DATAMOVE DATA RE.GISTER 6 (INTERNAL)
7 c
... DATAMOVE DATA REGISTER 7 UNTERNAL)
Figure 6 · VAX.13178733 Private Register Assignments
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Confidential and Proprietary
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BCD Control and Status Register-The BCI3 control and status register (BCI3 CSR) contains 16
nodespace write sense bits, one for each of the nodespace regi*r addresses shown in Figure 4.
These bits are set when the BCI.3 is accessed by another VAXBI bus node. When information is
written into a nodespa¢e register, an interrupt request (IPL 16) is generated and the corresponding
bit in this register is set. The interrupt can be masked by ~~ i~~ti()fl in the control and status mask register. The register also contains controlad<lstatus·bitsus$1by the datamover. The register
format is Shown in Figure 7 and the information is described ~n ':['able 5.
31
2423
1615
0807
00
x = IGNORED ON WRITE 6PER)l;T1ot.1$ AND RETURNS ZERO ON READ OPERATIONS.
Figure 7 · VAXBI 78733 BCIJ Control and Status Register Forlmif .
Bit 31:26 25
23 22:16 15:00
Table .S ·.VAXBI 78733 BCD Control and Status ~tet Deaeription
DescriptiOn ·
' '
Not used."
DMOVE DONE (Datamove done)...,...When set, .it ..indicates. that the datari:iove operation completed successfully.
DMOVE ERR (Datamove error)-When set, it indicates that the datamove operation was aborted due to an error. Cleared by writing a 1 to this bit.
Not used.
No4e~pacewrite sense bits~S<lt wl\en the.~~pon~~~pace,regjs~~
received data from other Blnodes. Cle°'red by \Yfi~ f\l l to t,his bi,t. ·
BCD Control and Status Mask Register-The BCI3 control and st.atus mask (BCI.3 CSMR) register
contains 16 nodespace write sense mask bits that are used to mask the sense bits in the BCI3 control
and status register to prevent the generation of an interrupt. The register also contains bits to
enable datarnover interrupts arid globill interrupt enable bits.· Figure 8 shoWs the register format
and register inforrnatioll is described in Table 6.
· ·
Confidential and Proprietary
4-171
INTEN.
X ~ IG OFfEO ONWRl.TE OPEFfATIONS AND RETU.RN$ ZERO ON .l'!EAO Ql'!ERAT.ION$,
Figure 8· VAXBI 78733 BCI3 Control and Status Mask Register Format
Bit
31
30:26
25
24 23
22:16 15:00
Table 6 · VAx:BI 78733 BCI3Cont!rol and Statils Mask Register De~tion Description INT EN (Interrupt enable)-Set by the processor to enable an interrupt request that originate in the BCI3.
NotJ,!.Sed.
DMOVE DONE M (Data move done mask)-Set by the processor to allow an
interrupt when the corresponding bit in the control and status register is set.
Notu~.
DMOVE ERROR M (Data move error mask)-Set by the proc¢ssor to allow .~ interrupt' when the corresponding bit in the control and status register is set. · Not used.
NODESPACE WRITE SENSE MASKS-Seuo enable interrµpts when the corres-
ponding bits of the control and status register are set.
BilC Event Status Register-The BIIC event status register (BIIC ESR) indicates the history of
events specified on theVAXBI event lines BCH~V < 4:0> , ekcept for the lnrel'lOck error indicator
(bit O). Bit 0 is set if the readlock fails after the BCI3has read data from the II bus resulting in a II bus memory lock condition. The bits in this register are set ·by the BCI3 and cleared by the processor by writing a 1into the required location. The BCI3 will interrupt the processor when a bit
is set provided that the corresponding mask bit in the event mask register is set. The register format
is shown in Figure 9 and the bits are defined in Table 7.
D · DIAGNOSTIC INFORMATION E = VAXBl/BllC ERROR INFORMATION
S = VAXBl/BllC STATUS
INTERLOCK ERROR
Figure 9 · VAXBI 78733 BIIC Event Status Register Format
· Confidential and Prol'Jtletafy
Bit 31:01 31 30
29 28
27 26 25 24
23 22 21 20
19 18 17
16
15 14 13 12 11 10 09
. 08 07 06 05 04
Table7 · VAXBI 78733 BllC Event Status Register Description
Event Code bits-Specifies the BIIC events as' follows:
MTCE (Master transmit error check)
RT<J <Retry timeout) .
'ci' ·
ICRMC (Illegal confirmation received for master-port command)
BPR (Bad parity received)
RDSR (Read data substitute or reserved status code received) AKRNE7 (Acknowledge confirmation received for non.error vector-level 7)
BPS (Bad patity received during slave tmnsacdon) STO (Stall timeout on slave transaction)
EV6 (External'vector selec~:.2.I~el6) ·
EV5 (External vector selected-level 5)
EV4 (External vector selected-level 4)
IAL (Identification arbitratiQnJo~)
AKRE (AcJmowledge corififmati<;m, reCtiived for ~r vector)
..--
_., - -· ---
., . . . · __ ,. -- ,
. . ' . . ,L . . . . ·, '-.
·-_ .
NICIPS (No acknowledge of illegal confirm11tion received for force-bit interprocessor/
stop command)
NICI (No acknowledge or illegal confirmation recei~Cd fo~ interrupt command)
ARCR (Advanced retry confirmation received)
IRW (Internal register written)
RCR (Retry confirmation received for master-port command)
STP (Self-test passed)
Confidential and Proprietary
4~11;
-·;
Bit Description
03 BTO (Bus timeout)
02 AKRSD (Acknowledge received £rom slave read data)
01
MCP (Master-port transaction complete)
00
INT ERR (interlock error).,.....Set to interrupt the Mi,croVAX during ·.al'!. ert"Qr conditior:i
provided that the corresponding mask bit is set in the BIIC "CVent mask register.
BilC Event lntqruptMa.k RegiJter-The BOC eventinterrupt lrulSkregister (BIIC EIMR) is used
to mask the event indications in the event status register to prevent the generation of an interrupt. The bit mask assignments are shown in Figure 10 and the event codes are defined in Table 7.
31
2423
1615
0907
00
···H M:M:M:M:M:M;MIM:M:M:M:M:M:M:3M:M:M:M:M:M:M:M1M;M,:M:M:M:M:M:Ml
\
I
. ·.. EVENT MASK BITS:=J
M = SET TO ENABLE EVENT INTERRUPT
Figure 10 · VAXBI 78733 BIICEvent Interrupt MiJ.sk Register Format
Datamover Configuration Regis~-The datamover·configuration register (DMCR) is used during datamove operations and to specify diagnostic mode operations. The register format is shown in Figure 11 and described in Table 8.
lb. 31 28
21
13.
00
Ir+r I::::: ~ii.:.: I:>F~+HHf: :I
. Figure 11 · VAXBI 78733 Datamover Configuration Register Format
Confidential and Proprietary
-
Bit 31:28 27:20 21 20:14 BiOO
Table 8 · VAXlU 78733 Datamove Configwation Register Description
Nottised.
.,
DIAG MODE (Diagnostic mode)~Set to irtltiatediagnostic inode operatiqn.
(
'
''
.,. '',: ' - ,' ... ;''' ,' ,'' ,'_,,. .--·/'·i-· ·( ., '· '' ' ' '
' '' '' ' ' '
Not\ISl?d.
Transaction couht.cL.Con&ihs'thtitW<)'s con1ple~ritofthe nu.inbet dfoctaW(it& to
be transferred (from 1 to 16K ooawotds) ~the datainove.
·
BIB\UI A~s Register-The .BI adrlress. tegis~ {~I ~)ict?n~;~~ ~~tiqgVAXBI ad~s~,alld
VAXBI ~psaction length code to he usoobr i}le~~tll~r·.~eonteritSof thiS,re$i~r ~ID,be
altered dliring datamover opf:rations. The regisie,r forj'nit iS &MW11in F~l.1! 12. ·
·
·.
'
1'
(
,·; '
,t," ._ ,'
'
..:> ·, .'
.'J: .:&."'-·
.,_, '.';.,· '
IlBusAddiedRegiSter-The Ubus IKtdresuegis~·(ll~}~ the.ttarµngnbuS a~~for ·
the datamovet: The contents ofthiS'~WU11~·ttlttteti ~~th~ofkratto~of the ~tum~
The register format is shown in Figure 13.
Figure 13. VAXBI 787JJ IIBus 'Address ~Ster F01'111!lt Datamove Data Registers (0-3)-The datamove data registers (DORO through DDR3) are used as
buffers to transfer octawords between the II bus and VAXBI bus during a datamove operation. Each register contains 32 bits.
-
Preliminaty ·.·.
VAXBI Tnmsactioos · ·' All transactions between the BCI3 andVAXBI bus arefacilita.ted through the l3IIC interface th;it
communicates directly with the BCI3. The BCI3 can bea master or a slave on the VAXBI bus. As a
mastei; it performs the transactions requested by the protessot: As a slave, it responds to the VAXBI transactions that are directed to it and translates the VAXBI bus transaction onto the II bus. When
the transaction has been completed, the BCI3 reports the transaction status to the VAXBI master.
The BCl3 responds to VAXBI bus addresses in the 8-Kbyte region of I/O space (nodespace) and to a
region specified by the starting and ending address register (configurable by the MicroVAX
software). This software defined region typically resiqes in memory space but during certain
conditions it may reside in the VAXBI I/O space.
·
The nodespace region starts at address 20000000 + 2000 (hexadecimal) node JD defined as the
nodespace base address (bb). Each of the 16 nodes than can be assigned to the VAXBI bus is
identified by a node ID. The nodespace contains some registers that are defined by the VAXBI and
some that are defined by the BIIC and BCI.3 interfaces.
The remaining region is defined by the starting and ending address registers of the BIIC interface.at
locationsbb + 20 and bb + 24, respectively. The BCI3 responds to addresses numerically greater
than or equal to the starting address but less than the ending address. The low-order 18 bits ofthese registers must contain zeros so that the addresses are located in multiples of 256 Kbytes. The
MicroVAX software should load these addresses during VAXBI node initialization.
Transaction Response-The BCI3 reponse to VAXBI transactions is as follows:
· VAXBI Interrupts-When a VAXBI bus interrupt (INTR or IPINTR) command is issued to a local node, the BCU. interrupts the. processor at. the level specified in the command. The request is cleared after the processor solicits the interrupt vector by a MicroVAX interrupt l,lCknowledge transaction.
· VAXBI Identification-The BUC interface responds directly to IDENT transactions and the BCI3
is not involved in this transfer.
· VAXBI Invalidate-The BCI3 ignores the VAXBI INVAL transactions.
· VAXBI Stop-The BCI3 acknowledges 81.QP trapsactions but performs no operations. External
user logic may decode this transaction for node. specific respo1lse$.
Il Bus to VAXBI Bus Translaµons All II bus transactions directed to the VAXBI are transparent to the processor software. The READ,
READ WCK, and WRITE (etc.) are translated directly to VAXBI transactions. A MicroVAX interrupt acknowledge is translated to an IDENTtransaction. The windowed II bus transaction is stalled until the corresponding VAXBI bus transaction has been completed.
When a VAXBI bus error is detected, the BIIC interface informs the BCI3 interface through the
BCI EV< 4:0 > lines. The BCI.3 sets a bit in the event status register that may result in a processor
interrupt. Critical errors su<:h as BI master transaction errors can terminate the corresponding BCI3 operation. The BCI3 notifies the processor oferrors detected during windowing operations using the II ERR signal. Errors detected during datamove operations cause the BCI3 to abort the operation and to set the datamove error bit in the datamove register.
4-176
Confidential and Proprietary
II Bus Read Thmslations-The II bus to VAX.BI bus read translations·are·
ll Ju· eOmtnarid·
~d{Is~)
VA.XlSI B~s ~
. READ
Read Lock Read (D stream, modify intent)
READ LOCK
REAP·
Read (D stream, no modify intent)
READ
The length of the VAX.BI-generated transaction is a longword with D < 31:30 > equal to 01 in the
command/address cycle..Bits D <29:00> are transferredto the. VAXBibus. VAXBirodesusually
ignore bits D < 01:00 :> ·
"
The BCI3 generates a II bus errot:~whett
· The VAX.BI transactioh.is.not ackoowledged or exceeds the time specifi~ for completion...
·.Invalid paritY is detected or an illegal confitm.ation.code is ~ived.
· A read data substitute or reserved read s~tus eode is receivedftomtheVAJmibas.
II Bus Write 'ltanslations-The Ifbristo VAXBI1bus w_rite tral1S~tions are
II Bus command
VfuI Bus commatiil
Write (D stream)
WI.UTE MASK
Write unlock
.WJUTE UNLOCK
and The write(!;> stream)traru;actio~ is trans}'ated intp aYAx:BI WJ.µ~~1\.SK a II ~riteu~ is.
\fAxai at<rlaw2na9sya:s0ctt0riao>nnsofisufttaehldweiilnlrtfbbs·u·.a~s··aVfdAdoi.X~-JerlsI sWdaRr.(eDttr<TaE.>Un1sN!.3Ll0Qe~JC.Kfiitbrb1ea?m'.J$tnaofethhteefVAoXnB.H~t~I~#~->~ph'm,b.)afft.,l.db..ea.cgfd~ie' St's.e~re·.J.·.VB~iI~
The II ERR signal is asserted by the BCI3 by the following:
· The VAX.BI transaction times out.
· Invalid. parity or VAX$l bus etrors are detecteil.'.rin'clilie YAXJ3l bµ$.
···· ·
n~s{Jltetnlpt~~~~.'...WP~~;~n~tW~~~.jlltit1~u~.~~w1<lqg~)the
BCI3 iss~ !l VAXBI IO:E;NT(:c,mmapd if!l V~l~!'UPt. (~Nnqis,~&¢~ at~priC!tjtyl~
specified by the acknowledge. The vector returned by the IDENTcommand completes tfu:;:Il !:ms
interrupt acknowledge t~f1Sactio~. TI:e VAX13l U1!1',~}>t ~~~~~~ill sl~~ ~~ ~~.c~f11:pleti09
of the transaction or When an erroris detected. 'flte BCI~ ~ne~te~~ n;hw ~r .~~:when ,. ·. ..
"
<-'
' ' ,· \ ' -
' '\ '
'-· _.. -·-:·:"'!·-- .. ; ',_, .. ')·"·"" . ,.,, :-.-,, ,.,, . .., .. ,,.. _, "' -'·- ..·"- - ,.,
· TheIPENTC0Q1maQdis ll<ltackrulwledgedprpc~~sthe,t~~f<:>r~mpl~ion. ,
· TheBCI3 receives an illegal'VAXB!confkirl~ion&ide. ·· ··
4177
VAXBI Bus to Il Bus Ttan$4cijP,1Js The VAXBI bus read and ~it~ commands d1at ~~e an adoo;~s between the starti11~. llJld ending address register values of the BIIC interface are trah~lated to II bus read or write coirunands. VAXBI bus quadword-length transactions are translated into two longword length transactions. VAXBlbus octaword transactions are translated into four ldhgword-length transactions. Table la lists the
translation between the VAXBI bus command and II bus transactions.
18ble 9 · VAXBI 78733 VAXBI Command to II Bus Command Transactions
VAXBI Bus commands
II Bus commands
READ
Read (D stream, no modify)
INTERWCK READ*
Read lock
READ WITH CACHE INTENT
Read (D stream, no modify)
WRITE
Write (D stream)
WRITE WITH CACHE INTENT
Write (D stream)
UNWCK WRITE MASK
Write unlock
WRITE MASK
Write (D-stream)
*Gommands of quadword length are translated into a II bus ~~d lock transaction followed by a Read (D stream, no 1Uodify) transaction. Commands of octaword length are translated into a II bus read lock transaction followed by three Read (D stream, no modify) transactions.
Read Translations-During read-type transactions from the VAXBI bus, the BCB, wiV. normally
stall the VAXBI node until the translated transaction has completed. When the II bus memory controller transfers the requested data signified by the assertion of the rI RDY 'signal, the BCI3
returns the data through the VAXBI bus with a "read data don't cache" status. If the memory
controller responds with an error (II ERR) or retry (II RETRY) signal, the BCU returns the
appropriate no acknowledge, or retry confirmation on the VAX.BI ·bus arid terminates the
transaction.
Write 'lhmslations--The BCI3 acknowledges aVAXBI write-type transar;tion when the data has been successfully received but before the completion of the actual· write operation. Write transactions that fail because of nonexistent memory·and other conditions are not reported to the VAXBL This disconnecting of write transactions. ~ows the VAXBI bus tc:> par,ticipate il) other transactions while the BCD completes the write (detached) transaction to the II bus. If the BCI3
receives another VAXBI read- or write-type transaction before the lastwrhe operation has been
completed, it will retry all subsequent VAXBl transactili'lns until the detached write transaction has
completed.
4-178
Confide~tial and Proprietary
Error Hamlling The following events occur during an error condition.
· When an error<>eCW"son the Ifbus side during a VAXBI bus to Ilhus window·.tead ~tio!l; the
BCI3 indicates an error by. issuing a no acknowledge reply during the comm!md/adtlress cycle of
.the..VAX. ·1.·3.I read All II bus ¢rrots by *e assertion gfthe .·.·· . ' - - ,;,.
trama~pn.
--
"" - ,_, -- - -
-' - ,._ -.
~· ~£>~i&d
- . , ·, -- - ', - ' ' ' - - _-
- "" . _, :-.-. '" ' :
~s~rial
-·-· ,. ·-·. ' -
·'' -· ',.·' - ~ {\ ',,., --- ,_
· When an error occurs on the Il bus side during a VAX8'1 btl$to Ubus winddw'Write·~tion,·the
~u
write
inhibit~ traQSfet
~dditiotliil µ~.us
No erro.1; wilt he
w.ir;ietpeort~tr:c~> ~tliPe ~ ~ ~l~t
~ n%m~~ bus. ··. . .
~~iii4J?!'~µltiio~~rd . , '· . ..
< '
''
' - : . · · ; ',: , ' ' - ' ,·--·.:·;.'"·'·- ·--<' '·' '-.-.,·,;-·' "
- \·· .,f;·,_;' ·' ·' ,' -··:
.,·.-
- _,,
·The II ERR signal is used to inform the MictoV.MC.that;!i Jl\;hus'W~I·bus·win~
< ....·. . .. tranliacdon pas been (;J;)Q1pl¢tedun.s1,1C£e~ll#.tJly.lfiS. ne>t ~sleije@~10j"1~<;3.te~.ef#~ resµliilrig
'trom an inrorrulig \Trot bus transacti~nl!: ·· . ·. . . . . . ··.
· lfari error ipdic;atjqq is ~veddurioganWCQ!!ijng,\iAX.Bl~U bu~wrii:e t:i;ansltj~on'"oo 't.V..U'ti..rig
will.occuro.n. the... h. .b.··.u..s... .·. ·.· · , · · · ··' · ·· ·.'.' ,,.,,, '· · ,, · ·.· '·' · ,.,
-; >' ::~d
' '
· If theWAXBI:readlookfaik.ahtttheBCIJ ~;teadcheditt'1£t0iti'h ;i;t;fausrthe;BCJ3 wilftnot
unlock the II bus memory.
· During <>ther YA,XfJI to II bus conditiops~i;:h,~,.119ru~~~~ ~sa,~~~n~,abit ln .~.~
status register wfilbe setto i,rlter:rµpt the p.ro¢¢s~r l(~S9l'.'~29Ql;li'18~retrupt mask l:litlm:s Jl,O~
been set.
·
· Special Operations
the The BlC3 ,Wte~ace ~,the capaRili#e~.~. peJ:forl,U·St>eqlllJ'~~ ,rp im~~ ef(igel1cyof
data ttansact;ions .~·~·. ~oF. !$agn~tii;,.te;S~ P'W~~~ ~:$~~:eqm~ .~· th~ B(;I3 to
transfer a sequence ofQct!tWords ~~nth~ II bus .and VAJ!;BI ~:. ·
· ·,
, ." _,_,''
' ' ,'
,, ''
'.·- -
_, ·,,'
'- -
\
0 -
\
--
o: ".. - - '·"'· ,--_.-· ' - - ,-_:,-;- ,' : : J .-,
DDUatiai!m;lgovdeatOampoervaetioopnestat.i.on.·s~
. . the
.M..icr.o.\t·.·A·· .X
~...~·. e·.·s.·'.i. .·l·.· i.e·.
]'·)·.·C·. .B...tO·."..·t..tafls[e~
a
~~uen<:e
of
(jCt~\'vQtds
bet:Ween the 11 bus and VAXBI bus; The ad' ioaas'tfifoternal~twitho.6m~r' ~ini>~~ns
and transfers them to the other bus. When completed, the BCl};ffiterrtipts the t)toe'essor. ~ati$e
the datamove operation uses the VAXBI octaword transfer, it is mote efficient than the MicroVAX
MOVx command iliat: transfers sequences of individual longVloi'cls. In addition, it allows ilie
processor to perform other operations wl::jeni:heda.~ovettansacti(lnisin ptc)Cess.
If a RETRY request from the VAXBI bus is receim dUl'ing the Bl t~action, the BCB will repeat
the transaction until it is successfully compl~ or until a timeout cOriQit:1on occurs. If the
transaction is not aclmowledged or times out, i:h~·Bell·WiJ:f s~t the p:Mo~E ·f;&RO:R bit in the
control and status register. The cause· of the fail\ire must be Gletermiried ~m the BCH and BIIC
interface status regis~s.
The datamove commapd uses the datamcive copfjgrtratjon register, control and status register, control and status mask .register, II bus address reliiste+· aqd ilie BI bus address register in the BCU. The data to be transferred must be aligned by octawo.rds and the source anddesdnation blocks may
not cross a 256-Kbyte address boundary.
Confidential andProprietar,y
4-179
Data is transferred from the II bus to the VAXBI bus by the following operations. The, data to be
transferred must be octaword aligned on the IIbus and.VAXBI bus. ·. The starting ad.chss.of theofUbus data (source) isloaded into the BCUII bus address register,by
the microproceSSCl)r, · The starting address of the VAXBI address (destination) is loaded int6 the VAXBlbus address
register in the BCU by the microproceSSOJ:..
· The BI WRITE command (oode 0100) is written into the BICMD field and the two's complement
of the the number of octawords to be moved is Written into the transfercount field ofthe datamove configuration register by the processor.
· The GO DMOV bit of the BCU control and status register is set bY the nlicrop:rottssor to initiate
the data move operation,
~. The BCI3 Sets theDMOV DONE bitin the control and status register at the e11d of the tran:sa¢tion
or sets the DMOV ERROR bit during the transaction if an error detected during the ttansactfon. These hits can' generate a microprocessor interrupt li enabled by the corresponding mask bits·in the controland status mask register.
The sequence required to transfer data from the VAXBI bw to the II bus is similar to the previous transfer exceptthat a BIREAD command code (0001) is Written into the BICMD field ofthe data configuration register by the microprocessor.
· Application Information Refer to the BCIJEngineetlng Specification (DC344)for more detailed i.nforriiation of the operation of theVAXBI 78733 interface, the VAXBI System Re/erenceManual(documetit number EK-\ffiISYRM) for information on the VAXBI bus operation, and the VAX.81 78732 Bus Interconnect Interfaee Chip (BIIC) information contained in this databook.
Figure 14 shows a. typical system implementati,on consisting of three 1.nicroproce~sors. Each
microprocessor COl'lltnunicates with memory and· devices through its ri bus and to the VAXBI bus through the BCI3 and BIIC interface.
MICA OVA)( CPU
4-180
Figure 14 · VAXBI 78733 Typical System Configuration Confidential and Proprietary
The II bus is a 10 Mbyte-per-second private bus that communicates with the !l~~te-peN~CiO~ VAXBl sy!ltem bus through the BCI3 and :anc intel;face suuctQre. Bo.th buses im~ a
common 1-Gbyte address space. All resources with the exception of certain nodespace locations can be accessed through the uniform addressing arrangement.
· Specifications
The mechanical, electrical, and envi.tonmental::'.speeificatlons £«: the VAXBI interface .are., as
follows. The test conditions for thevalues specified :are as follow$ unless specified otherwise.
· Temperature: 70°C
· Supply voltage <Vccl: 4.75 V
· Ground (V58): 0 V
Mechanical Configuration
The mechanical dimensions
for
mounting
the
132-pin
PGA . interface
package
are·.'.. .~<.>..Wn
. . in
AppendixE.
· Absolute Ma:ximuni Ratings
Stresses greater than the absolute maximu~. nit!n,g~ mity caµ~, perlll1lp.en,t dainag~ to a. d¢vice.
Exposure to the absolute maximum rating eonditiorisfotextended pqiods may ad~sely,~«t
the reliability of the device.
.
· InputJtncl output voltages applied: -1.0 V tp.\O V
· Power supply voltage: 0.5 V to 7.0 V
Recommended Operating Conditions · Power supply voltage range (VcJ: 4.75 V to 5.25 V · Temperature range: 0°C to 70°C
Confi®ntial.aod Proprietary
-
de Electtical~cs Tubleio:contains the de electcic:al parameterSfor the input and outputs of the BCI3 interface chip.
Tuble 10 · VAXBI 78733 de Input and Output Parameters
Parameter
Symbol 'lest Condition
Requirements
Min.
Max.
High-level
Vm
2.0
input voltage
Low-levd
Vu.
input voltage
-0.5
0.8
High-level
Von
lou=-400A
2.4
output voltage
Low-level
Vot
loL=2.4 mA
0.4
output voltage
lot=4.0mA*
Input leakage
cutrent
I1L
OV < V., < 5.25V -20
20
Output high-
lzo
OV < V., < 5.25V -20
20
impedance
leakage current
Supply current
Ice
500
Input
c ..
BCI MDE, BCI SDE
50
capacitance
all other signals
10
Output
c ...
10
capacitance
*Open-drain outputs
·Units
.V
v
v
v
A,
A
mA pF
pF
PP
4-182
Confidential and Proprietary
· ac Toning$~t;ions
The timing fcirthe ac parameters that follciw are measured with a 100-pF capacitive load on each of
the output~.
Figures 15and16 show the ac~i.m,i,~ foi: th~~M,ls \1:$~ during II bus transactiqµs whenthe BCU
is operating as a slave. Figure 15 is a read and interrupt aclcnb~~~ transaction diagram. Figure 16
is a write transaction diagram. Table 11 lists the tiining ~Meters for the symbols shown in the
figures.
.
Ji- ::::=:>---co ~<31:QO>
~ ADDRESS
~ :r]j·~r,· J '. :-z.. t4t.6.zo.i\
... 4 'O_ ATAfi :
1__
_;---.
.
rn
. r
OS
J
I tosHW
'·· 1
' , - -\:;;~ \
r..,
'NSO~
r .·1. to.···SAS··· t-. -·.J. j ··J-········~-1-
. ~~---------~'-/-\_·_·/{·___r_·_·~-·1·_._~~ -·~··.·~."2····\
l tAswR-l ~
CS<2:0>
__ rr·....i .· DAL<31:00>
_,>----ti ADDRESS I _ _......i_t.A._
··~··· ''~.I. J· 1..
tDsHw ;1
... ·1
_/
r·.o·sv·o,......~-.-....
tDSASr.·
I
I
11
CS<2:0>
B'M<3:'0>
Figure 16· VAXBI 78733 SIAve II Bus Write Transaction Timing
Symbol
tAAs tASA
tASSH
tASSZ 11 tASWR
tAZl>A tBMAS
toons
Table 11 · VAXBI 78733 Slave Il Bus Signal Timing Parameters
Definition
Requirements (ns)
Min.
Max ·
.Address setup time to AS assertion
20
Address holdtime after AS assertion
20
Status hold from AS negation
0
Status highiinpedance frOm AS negatidn
40
WR, BM<3:0>, CS<2:0> hold time from
0
AS negation
Address high impedance to ITS (read-only)
0
BM< 3:0 > setup time before AS asse;tion
20
Write data setup time before DS assertion
0
4"1184
Confidential and Proprietary
Symbol''
· . , ·r.., .;~~'!e.~ :··.·L'·'i""·
tDJl.A
Read'd4ta setup to IrnY assertion
tDSAs
15S negation to A'S negation
tDSHW
twus
> ~ \\IB, c~< 2:0 setup tim~ Eie£~re n·~;;rtj<;.l
·.,,. - ,. '.," ~" ' ' ,, _,,_,.,,,_. ",.,,.
',·,; ,,, ;
'
'
*Designed for but oot~sted.
10 0
55
,.o
.to
Confidential and Proprietm'y
·~185
---1111J)i
m.-ter. is' Figu.res. Rindl8 ~w the ac.timing for the sigllais used during II bus tra!;l~9o$\vhen th,e ~CI;
is operating as a
i;· Figure 17 is a read transaction diagram. Fig~
a ~rite transaction
diagram. Table 12 lists the timing parameters for the symbols shown in the figures.
OAL<31:00>
AS
CS<2:0>
I I ,:BMA~l 1
ROY ERR RETRY
Figure 17 · VAXBI 78733 Master II Bus Read Transaction Timing
4·186
Confidential and. Proprietary
WR
Figure 18· VAXBI 787JJMDSler1IBus Write 1'1iiisaction Timing
;y' ">j
-::
Symbol
tAAS
tASDZ
1able 12 · VAXBI 7873.l Master ll Bus SiaPal Tindng Parameters
Definition
~ts (ns)
Min. Mn.
Address setup time to AS assertion
20
Address hold time after AS assertion
20
AS assertion to read data valid (only if slave asserts
data lillY before data valid)
220
AS assertion to data valid
105
AS assertion to DS asse.rtion
120
AS negation to read data high impedance
5.0
AS negated width
75
AS asserted width
245
Symbol
tmmv
tl>SHlll' tnZDBE tlll'llAS
~
AS as,sertion to beginning of ROY, ERR, and RETR¥,, ·.·
·~mpµttg window
.
: RDY, ERR, and RETRYhold time from deassertion of AS
·WR, BM<: 3:0 >, CS<2:0> hold time from AS negation
BM c:;lo > setup time before AS asseition
DBE assertion width
Write data setbp time to ill assertion
...Read data s~p tt;jfr)y assertion when t 05moi: t~n1
parameters are not met
DS negation to AS negation
Read data hold.time after DS negation .
DSdeassertion to'f51IB deassertion
. l5S assert::iQn _to .re11d. data valid when sla~ as~tt~ Ki5Y
before data valid
. ,/
'
"""
· Write data hold time from DS negation
DS negation to read data high impedance
m negated width
~.assertion width
DAL< 31:00 > three-state to i5BE assertion
WR, CS< 2:0 > setup time before AS assertion
~erits(ns)
Min.
Max.
.,.._
70
0
5
2p
135
25
20. 5 0 5
50
10
:..-p;.;.
'' .10
150
80 0
20
4~188
Confidential and Ptoprietary
-
Preliminary
VAXBI787l3
Figure 19 sho\Vs t:he DMA request and grant signal timing when the BCI3 requests the use of the II
bus. Table 13 lists the timing parameters.
\----.11---'v
\..__I-
J;°""'"-1 H 1 1 - - - - - - - -
toRoz
- - - - < _ HIGH-Z
) i - - - - - - - - - (.-------//
II . . I
HIGH-Z
1
H tAsoRH
toRoz
//. I _H_IG_H_-z__~_,~-------..\__ ___/~--H~-IG_H_-z______~~---_ . toRDZ.
I ...!.. ----------- DS DBEL HIGH·Z
,,.-----.\_ ___/
-----
II . .
\:
HIGH-Z
Figure 19 · VAXBI 78733 DMA &quest and Gran~'Signal Timing
Symbol
tDGASO tDGDRO
Table 1.3 · VAXBI 78733 DMA 'fran884!-tion Tuning Parapleters
Definition
Requirements (ns)
Min.
Max.
DMR deassertion to .output high impedance
50
DMR hold time from ~·assertion ·
0
DMG assertion to AS assertion
210
DMG deassertion to DMR assertion
0
Confidential and Proprietary
4-189
d ----~~-,--~--------------·---~-Zi ""'"
---"'""'"L'lllillOlllblW~~~"OS'"'"''
VAXBI78733
Figure 20 shows the signal timing for data transfers to and from the retry address latch (register). Th.ble 14 lists the timing parameters.
r,,," l .,:l" --1X! DAL<31:_0>__
VALIO DATA ~'----
_v-- \...__ ___.!/
J...
..I" tRLSLw ·I
tRLSHW
DATA INPUT
----~ DAL<31:0>
VALID DATA
))..1- - - - -
~
l«oco)
~~l'tt~LUUU~__,p-i~~~-
DATA OUTPUT
Figure 20 · VAXBI 78732 Retry Address Latch Input/Output Signal Timing
Table 14 · VAXBI 78733 Retry Address Latch Input/Output Timing Parameters
Symbol
Definition
Requirements (ns)
Min.
Max.
tosns
Data setup to RLS assertion
20
tDHRLS
Data hold after RLS assertion
20
tRLSH'il'
RLS deassertion width
100
tRLSLW tRLODO
RLS assertion width RWE assertion to valid
100
60
tRLODZ
RWE assertion to data high impedance
50
4-190
Confidential and Proprietary
·Features
· Custom.l4·pin DIP bipolar integreted circuit
over · Drives 16 clock receivers distributed a maXirtmnil.524 meters ofetch
· Single 5-V. power supply · Differential ECL drive outputs to both BI TIME +/- andJ~lPBASE +/-:-
· Uses an externally applied 40-MHz crystal oscillator input · Provides TTL outputs and differential ECL outputs
· Description
The VAXBI 78701 clock driver is a custom-built 14-pin DIP bipolar integrated circuit (IC) that serves as the clock source in VAXBI systems. The clock driver is designed to drive 16 clock receivers distributed over a maximum 5 feet of etch. The device requires only a 5 Vdc operating voltage. Figure 1 is a functional diagram of the dock-driver. .
GND TTL Vee 2
40MHz TTL
20MHz 4 TTL
10MHz 5 TTL
5 MHz 6 TTL
GND
3-BIT SYNCH
ECL COUNTER
QI
14 ECL Vee
13 Bl TIME+ Bl TIME -
11 OUTPUT ENABLE Bl PHASE+ Bl PHASE -
a ECLVcc
Figure 1 · VAXBI 78701 Clock Driver Logic
Confidential and Proprietary
4-191
VAXBI78101'
The circuit provides diffe~ntialECL drive Qutputs and TTL outputs from an externally applied 40-
MHz crystal oscillator. The ECL outputs drive both VAXBI bus BI TIME +/- and BI PHASE +/-
inputs. The TTL outputs are not recommended for use in a VAXBI system.
The VAXBI 78702 clock receiver must be used with each VAXBI dock driver source to provide the proper VAXBI clock receive function if the driving source of theVAXBI clock is also a VAXBI node. The dock driver must be at the electrical beginning of the bused clock etch lines. An output enable included with the device must be used if more than one node can be installed into the drive slot of the VAXBI bus. Only one source of docks in VAXBI systems is allowed and the first
slot should be wired to enable this device.
Pin and Signal Descriptions
The input and output signals and the power and ground connections of the clock driver are shown
in Figure 2. Table 1 provides a summary of the input and output signals.
· ·
GND
ECL Vee
TTL Vee
2
Bl TIME+
TTL 4{) MHz TTL 20 MHz TTL 10 MHz
3
4
VAXBI 78701
5
Bl TIME-·· ECL OUT ENA Bl PHASE+
TTL 5 MHz
6
Bl PHASE-
GND
7
ECL Vee
TOP VIEW
Figure 2 · VAXBI 78701 Pin Assignments
Table 1 · VAXBI 78701 Pin and Signal Summary
Pin Signal
Input/Output Definition/Function
3
40MHzTTL input
40 MHz TTL-A 40-MHz square-wave input from the clock oscillator.
4
20MHzTTL output
20 MHz TTL-A 20-MHz square-wave output.
5
lOMHzTTL output
10 MHz TTL-A 10-MHz square-wave output.
6
5MHzTTL
output
5 MHz TTL-A 5-MHz square-wave output to logic functions.
11
ECLENA
input
ECL enable-Enables the ECL outputs when at a
high level. Can be connected to ECL Vcc·
4-192
Confidential and Proprietary
-·
VAXBI7870l
Pin
Input/Output Deffuition/FunctiOn
9
BI PHASE - outputs
10 BI PHASE+
12 BITIME- outPlit .
13
BITIME +
BI PHASE +/- (5 MHz)-Differential ECL out-
puts for the phase signal inputs to the VAXBI 78702
clock receiyer and VAXBI bus.
4-/:- TIME ' BI
(20'Ntifz)_;.Differential EC.L outputs
for the time signal inputs to·~ V'Ax-Bl787Q2 clock
tectivet' randVWI bus: ,
2
TTL Vee
8,14 ECL Vcc
TTL voltage-Pawer supply wltage to TTL logic. ECL voltilge-Pawer supply voltage to ECL l~gic.
1,7 GND*
input
Ground..:_Conun.<:in ground teference.
*The two GND pins are not connected internally.
· Application
A typicalVAXBI clock driver and clock receiver system configinatio~ is shown in Figure 3: The
clock dri~:r receives th~ 40 MHz Tit..input from an .extermtl dock oscillator. An internal 3~bit synchronous ECL counter provides. the differential 5~MHz. BI PHASE.+/- ECL outp11ts. ancl differential 20-MHz BI TIME +/ - outputs for the clock receiVer. It also supplies a 20-MHz, 10-
MHz a.tY;I·.· 5-Mlfa TTL·square-wave outrJut.· Refer to theVA,XBI 78702··cioek 1;e1:eiver for a
·descripti(:)n of the VAXRI 78702 clock receiver functions.
·
Figure 3 · VAXBI 78701 Clock Driver with VAXBI 78702 Clock &ceiver System Configuration
Confidendai ·and Propriemry
4-193
·----·~--~-~----------------·------.--·--·---·------------~·
VAXBI7870t
Table 2 lists the relationship of the input andoutppt levels ?.f .the VAXBI 78701 clock driver. The
states of the inputs and outputs at startup time are not defined. .
.
. Table 2 · VAXBI 78701 Input and Output Signal Levels
'ITL Input Tm Outputs
ECLOutputs
40MHz 20MHz lOMHz 5MH21 BIPHASE + BI PHASE- BITIME + BITIME-
L
L
L
L
H
L
H
L
H
L
L
L
H
L
H
L
L
H
L
L
H
L
L
H
H
H
L
L
H
L
L
H
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
H
L
L
H
H
H
H
L
H
L
L
H
L
L
L
H
L
H
H
t
H
L
L
H
L
H
H
L
L
H
L
H
L
H.
L
H
H
H
L
H
L
H
L
H
L
L
H
H
L
H
H
L
H
L
H
H
L
H
H
L
L
H
H
H
L
H
L
H
H
H
H
H
L
H
L
H
· Specifications
The mechanical, electrical, and environmental characteristics and specifications for the clock driver are described in the following paragraphs. The test conditions for the electrical values are as follows unless specified otherwise. ·
· Power supply voltage (Vcc): 5.0 V ±5%
· Temperature range (TA): 0°C to 70°C
4-194
Confidential and Proprietary
-
Mechanic:al ~ ...
The physical dimensions of the 78701 14-pin CERDIP package are contained in Appendix E.
Absol'!te Muhn~ ~tings Stresses greater than the absolute maximum rating~ may cause permanent damage to the device. Exposure to the absolute maximum ratings for exten<:leq periods may ltdverselY affect the reliability of the device;
· Power supply voltage {Vcc): 7.0 V
·Input voltage applied: -1.5 Vto 7.0V(40 MHz TTL)
· Output voltage applied: 3.0 V to 7.0 V (Differential :ECt.}.
· TTL output applied current: 40 mA (low state)
"
'
· Storage temperature: - 55°C to U5°C
Recommended Operating Conditions
" Power supply voltage CVcc): 5 V ±5%
· Ambient temperature (TA): 0°c to 70°C · Input frequency: 0 to 50 MHz · Power dissipation: approximataly 500 mW (no load)
de Ek!ctrical Characteristics The de electrical parameters of the clock driver for.the operating vo1tage41'.d·rempetature ranges
specified and when at thermal equilibrium are listed in Table 3 and 4. All de specifications,
including capacit:anCe values, pe:rtain tO·packaged par;a. J;'a~le 4 liSts the TTL,.input and out{lu~
to parameters and Table 5 liSts the ECL input and output p~eters. Fjgtm:A s~ the de t~st
circuits use for the measurements. The ECL output lOac! ~~tor values uSed test·this device are not the same as theVAXBiclock termination values..· · ·
Confidential and Proprietary
4·195
-----------------·------------·---~··-···--......... --·---~---·-·-·-···-~·-····-~-----~---~---------'
-
Preliminary
VAXBI781ot
Table 3 · VAXBI787Q1 de ITL Input and ()utput Parameters'
Symbol Parameter
Vm
High-level
input voltage
Vn
Low-level
input voltage
Test Cot'lditions
Vc:c=5.'25V Pin3 Vcc=5.25V Pin 3
Unit Max.·
v
0.8 v
Im
High-level
input current
Vm=2.7V Vcc=~.25V Pin3
20
µA
In.
Low-level
input current
Vic
Input clamp
voltage
V1L=0.5V Vcc=5.25V Pin3
l.,=-18 mA Vcc=5.25 V Pin3
-2
mA
-1.2 v
IINBV
High-level
input curtent
breadown
c..
Input
capacitance
VoH1
High-level
output voltage
Vo1,1
Low-level
output voltage
· Vm=7 V Vcc=5.25 V Pin3
Vm=4 V Pin3
Io=Ioa max. Vcc=4.75 V Pins 4-6
lo=20mA Vcc=4.7' V · ·Pins 4-6
100
µA
12
pF
2.4
v
0.5 v
loa'
High-level
output current
Vo=Voamin. Pins4-6 Vcc==4.75 V
-1000
µA
lot1
Low-level
V0 =0.5V
20
mA
output current
Vcc=4.75 V
Pins 4-6
Ios2
Short circuit
Vcc==5.25 V
-25
output current
Pins4-6
-150
mA
ix
Power supply
current
Vcc:=5.25V No load Pin2
100
mA
'Testing either (VoH and V0L) or (lou and loL) satisfies these requirements.
2TTL outputs shorted to GND, ECL outputs shorted to Vee, or eith1=r outputs open a maximum
duration of 5 minutes. los is current into the output pin when the input conditions cause the
outputs be a logic one before the application of the short.
4-196
Confidential and Propriewy
VAXBI78701
'Illble 4 · VAXBI 78701 de ECL Output Parameters
Symbol
vOD1,2
VoH VOL
Parameter
Differential output voltage High-level output voltage Low-level output voltage
Test Conditions1
Load A Load A Load A
Requirements
Unit
Mm. Max.
700
mV
3.5
4.3
v
2.8
3.5
v
Iol
Output disable
current
VOHS
High output
stress voltage
VOLS
Low output
stress voltage
Voz=4.5V
50
µA
LoadB
Load A
3.5
4.3
v
Replace 110 0 with 60 0
Load A
2.8
3.5
v
Replace 110 0 with 60 O
Coz·
Disabled output
capacitance
6
pF
1Pins 9 and 10, U and 1.3 for all measurements
V2 00 is 318 rnV as measured in Figure 4 across points A and A' of ECL load. )Perform with pin 11 grounded, pins 1 and 7=GND, and TTL clock input (pin 3) hi~. Also performed with pins 2,. 8, and 14 grounded and at 5 .0 V.
·Difference in output capacitance (C02 +minus Coz - )=2 pF
Confidential and Proprietary ·
4-197 ·
-----------··-- ·-- - ·--·---·---------·-----
mn·a
Vee
8 2 11 14
.,.___<>-_..,. 3
4 o-..a---f5
6
VAXBI 78701
VAXBI787ol
7
LOAD A
Vee
l
2,8,14
VAXBI 9,10,12 78701 OR 13 1-----1:r-.
1,7,11
Voz4.SV
LOAD B
Figure 4 · de Test Circuits
4-198
Confidential and Propri.eta.ry
-·
Preliminary
ac Electrical Characteristics
The timing symbols and waveforms for the propagation delays are shown in Figure 5. The timing
symbols and waveforms for the output signals are shown in Figure 6. Table 7 lists the symbols and
parameters. All measurements are made when the chip is at thermal equilibrium. All ac
specifications, including capacitance values, pertain to packaged parts and apply when all outputs
are loaded and switched simultaneously. The ac t~t circuit con.figuration is shown in Figure 7 and
TTL and ECL load circuits are shown in Figure 8.
PINS 9,12
PINS 10,13
tp01
PINS 4,5,6
tpo2
tpo2
NOTES: 1. LOAD OUTPUTS PER FIGURE 8 2. INPUT RISE AND FALL TIMES EQUAL 1.0ns
Figure)· VAXBI 787()1 Propagation ~lay Timing
Confidential ~Proprietary,
4-199
...
A PINS 9(121
Preliminary
VAXBI7S701
B PINS
10(131
tsKW1
tsKW1 =GREATER OF [A -Bl OR [B -A) ABSOLUTE VALUE
A PINS-----9(10)
B PINS -----~--' 12(13)
tsKW2
tsKW2
1SKW2 =GREATER OF [A - Bl OR [B -Al ABSOLUTE VALUE
Figure 6 · VAXBI 78701 Output Signal Timing
Tuble 5 · VAXBI 78701 ac Timing Parameters
Symbol Parameter
Requirements (ns)
Min.
Max.
Propagation delay
-------
10
TTL output rise time (V0L max. to V0H min.)
8.0
TTL output fall time (V08 min. to VOL max.)
8.0
Single differential output skew
1.0
Differential output to output skew
1.0
Propagation delay
12
ECL output rise time (30% to 70%)
0.5
2.5
ECL ouput fall time (30% to 70%)
0.5
2.5
4-200
Confidential and Proprietary
-
VAXBI78701
2 8 11 14
4
5
6
VAXBI
OUT
IN
78701
9
10
12
7
13
Figure 7 · VAXBI 78701 ac Test Circuit
500n
150 PINS o---vvv---· TO son SCOPE
4,5,6
F
JP
TTL LOAD
PINS <>
L· ! f~" 10,13
eon
Vl/'v
6 IN -I
A .,. TO 60il SCOPE
PINS
9,12
[
0
eon
'\IV\-
..,A TO son SCOPE
ECL LOAD
Figure 8 · VAXBI l8701 ac Load Circuits
Confidential and Proprietary
4-201
·-----·-------·----·-----·
·-----·-------------·------·--·
·Features
· Custom bipola.r 16-pin integrated circuit used by all VAXBI nodes
· Receives the differential ECL BI Time +f-: '!:°<!.BI PHASE +/ - signals
· Single 5-V power supply · Approved for use in the VAXBI corner application
· Description
The VAXBI 78702 clock receiver is a cust:Om-built hi~lar 16-pin:·integrated circuit (IC) that must
be used by all VAXBI nodes to receive the differential ECL BI TIM£ +/- and BI PHASE +/ -
signals. The device requires only a 5~V <>perating vol~:
· ·
The clock receiver provides bOth trW! and·complement.ITL levels of both received differential
VAXBI signals to the adapter. It is appro\Ted for use onIY l.n theNAXBI comer application. Figure 1
is a functional diagram of the clock drivei
BCITIMEH
ECL Vee
2
Bl TIME+·
Bl TIME-
81 PH.ASE t ~r---0---1--~-; Bl PHASE - ~i----+--o
4!"203 '~-·-------~!llU------------~1£->---·-·,.;'ll_H_ _ _ _,_ _ _--~----·-----·
The input and output signals and the power and ground connections of the clock receiver are shown in Figure 2. Table 1 provides a summary of the input and output signals.
BCI TIME H
TTL Vee
ECL Vee Bl TIME+
BCITlME L· UNUSED
Bl TIME -
UNUSED
Bl PHASE+
Bl PHASEGND
TTL Vee BCI PHASE L.
· BCI PHASE H
GND
TOP VIEW
Figure 2 · VAXBI 78702 Pin Assignments
Pin Signal
14hle.1 · VAXBI 78702 P"m and Signal Summary Jnput/Output Definition/Function
3
BI TIME+ inputs
4
BI TIME-
BI TIME+/"- (20 MHz)-Differential ECL inputs from the VAXBI 78701 clock driver.
5
BI PHASE+ inputs
6
BI PHASE-
1
BCI TIME H outputs
15
BCITIMEL
BI PHASE+/- (5 MHz)-Differential ECL inputs from the VAXBI 78701 dock driver.
BCI TIME and BCI TIME (20 MHz)-TTL square-wave
outputs to the BIIC and master and slave interfaces.
8
BCI PHASE H outputs.
10
BCIPHASEL
BCI PHASE and SCI PHASE (5 MHz)-TTL squarewave outputs to the BIIC and master and slave interlaces.
13,14 Not used
2
ECL Vee
input
ECL voltage-Power supply voltage to ECL logic.
16,11 TTL Vcc
input
TTL voltage-Power supply voltage to TTL logic.
7,9,12 GND*
input
Ground-Common ground reference.
*GND pins are connected internally.
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Confidential and Proprietary
-
· Application
VAXBl781t2
A typical clock ddver and clock receiver configuration is shown in -Figure 3. The dock driver
receives the 40 MHz TTL input from an external clock oscillator and supplies the differential '.ECL BI TIME +/ ± and BI PHASE +/ ± inputs to the clock receiver and to the VAXBI bus. Refer to the
VAXBI 78701 clock driver for a description of the clock driver function"l. The differential ECL
signals are received by an internal gate structure in the clock re<;eiver. The oup,uts are converted. to TTL levels and provide the BCI PHASE H and BCI PHASE L. and.BC! TIME H.and BCl TIME L signal timing information to the VAXBI 78732 Bus Intercon00ct Interface (BIIC) and master and
slave interfaces.
--
XTAL OSCILLATOR
VAXBI 78732
BllC
1
BCI PHASE H BCI PHASE L BCI TIME H BCI TIME L
VAXBI 78702
CLOCK
~
···- RECEIVER
["' ·--;
- --
40MHz
VAXBI 78701
Bl TIME+
Bl TIME - .....
CLOCK ORI VER
-;SI PHASE+ Bl PHASE:,,..
;__ :;__
""""""'
;.i..
"::J'
-'- :.c:J <ll a; x
<(
;;.
v
Figure 3 · VAXBI 78702 Clock Receiver with VAXBI 78701 Clock Driver Configuration
· Specifications
The mechanicaf, electrical, _ and environmental characteristics and specifications for the clock driver are described in the following paragraphs. The test conditions for the electrical values are as follows and are performed when the chip is at thermal equilibrium unless.-specilied otherwise. · Power supply voltage CVcJ: 5.0 V ±5% · Teniperature range (T..,): 0°C to 70°C
Mechanical Configuration The physical dimensions of the 16-pin dual-inline (DIP) package are contained in Appendix E.
Confidential ~nd Proprietary
4-205
111111111·
VAXBl78702
Absolute Maximum Ratings Stresses gi;eater than the absolute maximum ratings may cause permanent damage to the device. Exposure to ..the absolute maximum ratings .for extended periods may adversely affect the reliability of the device.
· Power supply voltage (Vee): 7.0 V
· Input voltage applied: -1.5 V to 7.0 V · TTL output applied current: 40 mA (low state)
· Operating junction temperature ('.I;): 125°C
· Storage temperature (T8): -55°C to 150°C
Recommended Operating Conditions · Power supply voltage (Vcc): 5 V ± 5% · Ambient temperature (TA}: 0°C to 70°C · Input frequency: Limited only by tPHL and tPLu (Table 5) · Power dissipation: approximataly 160 mW
de Electrical Characteristics The de electrical parameters of the clock receiver for the operating voltage and temperature ranges specified and when at thermal equilibrium are listed in Table 2 and. 3. All de specifications, including capacitance values, pertain to packaged parts. Tuble 2 lists the ECL input parameters and Tuble 3 lists the TTL output parameters. Figure 4 shows the de test circuits use for the measurements.
Table 2 · VAXBI 78702 de ECL Input Parameters
Symbol Parameter
Test Conditions
Requirements
Unit
Min.
Max.
ImL1
High-level
input current
Vcc=5.25 V Vu.+4.5 V Complementinput=4.3 V
150
µA
Im,
High-level
input current
Vcc=GND
v,n=4.5 v vd;!f=l, ov
3.0 mA
I1L1 v 2,1
.&If
Low-level
input current
Differential threshold voltage
Vcc=5.25 V Vu.=2.8V Complement input= 3.0 V
150
µA
Pins3 to4, 5 to6
200
mV
4-206
Confidential and Proprietary
-
Symbol
Parameter
vCM1,4
Common mode voltage
Preliminary·
Test Conditiocill
Requirements
Min.
Max.
2.8
4.5
, ....
Unit
v
CMu'
Common mode rejection ratio
'40
dB
Ice·
Power supply
current
c...1
Sins}e-ended
input
capacitance
Vec=;:5.25 V toGND
20
mA
6
pF
10ther gate at valid logic state.
1Tested at V.,=2.8 V, 3.55 V, and 4.3 V with the complement input at 3.0 V, 3.75 V, and 4.5 V, respectively.
10utputs are guaranteed to be within V0JV08 limits if both inputs a~ within common mode range
and if minimum differential input voltage is applied.
·cMJt is the range of total inptit voltm:. through which the·output will respond to the minimum
differential input voltage.
'C-R is the ability to reject the effect of voltage applied to both inputs simultaneously. A CMIIR of 40
dB means that a 2 V commo~ mode voltage is processed by the device as though it were an additive
differential input signal of 20 mV.
'lee is measured with the de\ilce iii a quiescent state and with no load applied.
'Difference in output capacitance (C., +minus c..- )=0.7 pF ·':'
1Ab1! ; · VAXBI 78702 de TTL Output Parameters
Symbol Parameter
'fpst Conditions
Requirearients
Unit
Min.
Max.
High-level
Vccr4.75 V
2.6
v
output voltage
Vdlff=200 mY
lo= las max.
Low-level
Vc.c=4.75V
05
v
output.voltage
Vt111=200 mV
lo=20mA
High-level output current
Vcc=4.75 V Vdlff=200 mV Vo=Voumin.
-1000
A
Confidential and Proprietary
----
4-207
mDrlllll
Preliminary
VAXBI78702
Symhol Parameter
Test Conditions
Requirements
Unit
Min.
Max.
loL1
Low-level
Vcc=4.75 V
20
mA
output current
Vdlff=200 mV
V...,=0.5V
los'
Output short-
circuit current
-25
-150
mA
1Testing either V0u and VoL or lou and IoL is sufficient to satisfy these requirements.
'TTL outputs shorted to GND or open do not affect the impedance of differential inputs. los is
defined as current into output pin when the input conditions cause a logic one at· the outputs
before application of the short.
Vee
-r
2 11 16 3
- Vd"I -4
-
-15
-5
-10
-6
7 9 12
-8
NOTES: 1. Vee= GND FOR llH2 TEST 2. PINS 13 AND 14 ARE UNUSED
Figure 4 · VAXBI 78702 de Test Circuits
4-208
Confidential and Proprietary
·-
ac Electrical Chmacteriatics The timing symbols and waveforms for theECL and TTL signalare shown inFipre 5. Table 4 lists the symbols and parameters. The ac te~* cirt:ui.t configuration is shown in Figure 6.
Table 4 · VAXBI 78702 ac T.rDing Parameters
Symbol Parameier
Requiteblents (ns)
Min.
Max.
tPLH
Delay ECL to TTL output leading edge
tPHL
1.5
6.0
. 1.5
6.0
5.0
Output fall time (VOH min. to Voc max.)
5.0
Single output skew on individual outputs
4.0
Output to output skew (ootput to1H!y-0ther)
4.0
Vcc noise immunitr' )
0.25V
PJpF
Propagationdelayw capacitance
40
over the 0 pF to 100 pF range
*Noise immunity is such that the ttI:.ootputlevels Ofeach receiver are not tdf~ due to additive
noise OD Vcc· The noisevoJtSge is specified over v~ .volts Of additive OOlSe;; "'
Confidentjal ~Proprietary
4-209
Preliminary
"-;c,
VAXBI78702
PINS 3(5), 41Sl
ECL
PINS 1(8), 15(10) TTL
'-------3.3V tpLH
1. ALSO MAKE MEASUREMENTS REVERSING A AND B.
2. tsKW1 =GREATER OF tpHL- tpLH MEASURED FOR PINS 1, 8, 10, AN.D 15.
3, THIS TEST GUARANTEES WAVEFORM SYMMETRY ATA GIVEN Vee ANO AMBIENT TEMPERATURE.
ONE OUTPUT
OTHER THREE
t:----+--' OUTPUTS
1. tsKW2 IS THE GREATER OF SIX ABSOLUTE VALUE MEASUREMENTS. 2. THIS TEST GUARANTEES MAXIMUM SKEWS ON A GIVEN BOARD {ONE
RECEIVER) AND IS FOR A GIVEN Vee ANO AMBIENT TEMPERATURE.
Figure 5!· VAXBI 78702 Timing Waveforms
4-210
Confidential and Proptietary
Preliminary
VAXBI 78702
VAXBI78702
RI= 450n
T050'1:
Figure 6 · VAXBI 78702 ac Test Circuit
Confidential and Proprietary
4-211
·Features
· Used with the DC004, and DC005 circu\ts to in)plement a program control device interface. · Used with the DC004, DC005, DC006, and DCOlO circuits to implement a direct memory access
interface. · Provides two device-interrupt channels. · Performs a pass-the-pulse interrupt transaction. · Includes Q-bus drivers and receivers.
· Description
The DC003 dual-interrupt circuit, contained in an 18-pin, dual-inlitle paekage (DIP), is used in the
development of. device interfaces for the Q-bus. The simpl~ied 19gi.c ~iagragi of theDC003 is
shown in Figure 1.
·
·
Vee
RQSTA--~---t--.
ENA DATA ENA CLK
BiAKi BiiiiiT BciiN
ENS DATA
RQSTB-'---1-----'
Vee
1K
Figure 1 · DCOOJ Simplified Logic Diagram
BiAK5 8iRQ
ENB ST VECTOR
VEC ROSTB
Confidential and Proprietary
4-213
DC603 1
It provides the circuits to perform an intertupt transaction in a computer system that tises a
daisychain type of arbitration. It includes two interrupt channels; channel A and B, each of which
can generate an interrupt request from a device that requires service. The A interrupt logic is
assigned a higher priority than the B interrupt logic. Input signals from the bus are received by
high-impedance receivers on the DC003 and signals from the DC003 to the bus are supplied by
high-current, open-collector driveroutputs. The signalslevels between the bus and the DC003 are
compatible. When a device connected to the interfaceis not requesting setvice, the signal from the
polling device or processor is passed through the DC003 logic to the next device on the bus. The
DC003 circuits includes enable logic and provides interrupt status information to the requesting
device.
·
· Pin and Signal Descriptions
This section provides a brief description of the input and output signals and power and ground connections of the DC003. The pin assignments are identified in Figure 2 and summarized in Table 1.
VECTOR VEC RQSTB 2
8iNi'f'
BIAKO
TOP VIEW
Vee ROST A ENA ST ENA DATA ENA CLK ENB ClK ENB DATA ENBST ROSTB
Figure 2 · DC003 Pin Assignments
4-214
Confidential a~d Proprietary
-
Pin Signal
1 VECTOR
Table 1 · DCOOJ Pin and Signal Summary
Input/Output Definition/Function
output·
Interrupt vector gating-Asserted by the DC003 logic to gate the appropriate vector address onto the bus. This signal forms the bus signal.BRPLY'.
2 VEC RQSTB output1
3 BDIN
input2
Yectot:nequest B.,-,-Asserted by the..Dc003 logic to indicate
that the RQSTB service vector is required and not asserted to
indie~te that the RQSTA service vector is required. This signal
is
normally
'
'
bit ",
2 "
oft.h....e.
vector
address.
Bus· data in-As$e!teci by the masti;r to indica.te that an interrupt ~pe,ra:tion is occurring and Jways precedes a BIAK signal.
4 INIID
output1
Initialize out...,...A. bµff~ BINIT signal from the bus used to initialize the DC003 fogic and user device logic
5 BINIT 6 BiAKO
inpue
Bus irtltiallze.....;.Asserted by the bus to initialize the DC003 logkand device in~rface logic to a known state.
· Bus in~miPt acknowkdge outpl.lt:-Asserted by the DC003 logic to pass control to the next device on the bus iftheditVice connected to the DC003 does not require .service. Once
asserted, it remains passed until the next BiAKI signal is
generated.
inpue
Bus interrupt acknowledge input-Asserted by the processor
in response to the BIA.KO signal. The first; requesting device
prevents the BIAKO signal from being transferred·te' other dev~ces on the bus ~d· noprequesting devices will pass the
BiAKO .signal to th<! next ;device. Th~ .leading edge of the
BIAKI signal dears the BIRQ signal from the DC003.
8 BIRQ
9 GND 10 RQSTB
outpue
input input'
Bus interrupt request-Asserted by the DC003 logic to
indicate thQ.t the associated device is. requesting ari interrupt.
This signaUs as~ertedwhent;l1e RQSTA s~g~ ancl the E:.NA
DATA signal from the device is asserted. It is cle~dwhet} ~J:ie reqµest signal is removed or on the leading edge of the B.IAKI signal after the acteptarice ofthe:BEHN signal.
Ground-Common ground referen~ .
Device interrupt request B-Asserted by a device requesting an interrupt when the device has asserted· the ENB DATA signal. It results in ani.riterrupt request on the BIRQ.line that normally remains asserted until the interrupt request is granted.
11 ENB ST
output·
Interruptenable B status-Indicates the status. of the interrupt enable 13 ffip~flop on the J:)Cd0:3.
Confidential and Proprietary
4-215
---·--·-----·---------
1111110
DC003
Pin Signal 12 ENB DATA 13 ENB CLK 14 ENA CLK 15 ENA DATA 16 ENA ST 17 RQSTA
18 Vee 1TTLlevel 2high-impedance 'open-collector
Input/Output Definition/Function
input'
Interrupt enable R data-Asserted by a device to enable the transfer of data.
input' input1
A clock pulse from a device that enables the interrupt enable B flip-flop to assume the state of the ENB DATA signal.
A dock pulse from a device that enables the interrupt enable A flip-flop to assume the state of the ENA DATA signal.
input1
Interrupt enable A data-Asserted by a device to enable the transfer of data.
output'
Interrupt enable A status-Indicates the status of the interrupt e.nable A flip-flop on the DC003.
input2 input
Device interrupt request A-Asserted by a device requesting an interrupt when the device has. asserted the ENA DATA signal. It results in an interrupt request on the BIRQ line that normally remains asserted until the interrupt request is granted.
Voltage-Power supply de voltage
· Application Information
Refer to the Chipkit UsersManualLSl-11 Bus Interface Chips (document no. E]-01387-92) for general application information. The Q-bus is an LSI-11 bus.
· Specifications
The mechanical, electrical, and environmental characteristics and si}ecifications for the DC003 are described in the following paragraphs. The test conditions for the electrical values are as follows unless specified otherwise. · Operating temperature (TA): 0°C to 70°C · Supply voltage (Vee): 5.0 V ±5%
Mechanical Configuration The physical dimensions.of the DC003 18-pin DIP package are contained in Appendix E. The materials and constructionof the molded DIP are defined in Digital SpecificationA-PS-1900002-GS.
Absolute Maximum Ratings Stresses greater than the absolute maximum ratings may cause permanent damage to the device. Exposure to the absolute maximum ratings for extended periods may adversely affect the reliability of the device.
4-216
Confidential and Proprietary
··
· Supply voltage Wed: 7.0 V
· Operating temperature (T"): 0°C to 70°C
· Supply voltage (Vee): 4.75 V (mini111um), 5.0 V foormalJ, 5.25 V ~µni)
· Supply current. (lee): 140 mA (maximum)
· Relative humidity: 10% to 95% (noncondensing)
de Electrical Characteristics
The de electrical charact.l.tristics o~ the DG003 for the operating voltage and.temperature ranges
specified are listed in T®les 2~· 4. lfable ;2:Jists thedt ~ncat1onttif the TTLinput and
output circuits tQat d~ not.c<:>.iinectl.9·the bi.ts. 'n.l;>~}·~~~iµie ~ s~ificatfons fot.t#e ~h
impedance receivers that co~ tot~ l;SI-11 bus. Tuble 4 lists the de specifications for the open·
collector driver outputs that connect to the bus. Refer tQ Appendix C for the test circuit
configurations referenced in the tables.·
·
·
· ·
Parameter
High-level input voltage
Low-level input voltage
Input clamp voltage
High-level output voltage
Low-level output voltage
Input current at maximum input voltage High-level input current
·- \">
Table; 0 ocoo3 TTLlnput ancf~ppf~e-.s (nonbus)
Symbol Test Condition VJH
·~ts
Min. Max.
2.0
Units
v
1.i:st Circuit
Cl, C2
Vu.
0.8
v
'C1,'C2
Vr
Vcc=4.75 V
I1=-l8mA
-1.2
v
03
VoH
Vcc=4.7 V
2.7
1o:..:...i.o mA
v
Cl
VoL
Vcc=4.75 V
lo=20mA
0.5
v·
C2···
Ii
Vcc=5.25 V
V1=5.5 V
1.0
mA
C4
Im
Vcc=5.25V
V1 =2.7 V1
50
µA
C4
Confidential and Proprietary
4-217
-
'DCoo3
Parameter
Symbol Test Condition
Requirements. Min. Max.
Units
Test Circuit
Low-level
!IL
input current
Vcc=5.25 V V1=0.5 V2
-055 mA
C5
Short-circuit
los
output current
Vcc=5.25 V'
-40 -100
mA
C6
Supply current
lee
Vcc=5.25V
140
mA
C7
1lm =100 µA at pins 12 and 15.
lJIL-2.0 mA at pins 12 and 15. 'Not more than one output shall be short circuited at a time and the duration of the short must not exceed 1 second. 4Does not apply to pin 4.
Table ; · DCOOJ High-impedance Bus ~iver Parameters
Parameter
High-level input voltage Low-level input voltage Input clamp voltage
Symbol Test Condition
VIH
Vcc=4.75 V
Vm
Vcc=5.25 V
VIL
Vcc=4.75 V
VIL
Vcc=5.25 V
V1
Vcc..i4.75 V
I1 =~l8mA
V1
Vcc==4.75 V
I 1 =l8mA1
·Requirements Min. Max.
1.53 1.70
1.30 1.47
-1.2
Units
v v v v v
6.25 v
High-level
Irn
input current
Im
Vcc=O V V,=3.8V2
Vcc=5.25V
40
µA
40
µA
Low-level
I1L
input current
l1L
Vcc=OV V1=0.5 V2
Vcc=5.25 V
-10
µA
-10
µA
1Pins 10 and 17 only.
2Exclude pins 10 and 17.
Test Circuit
Cl,C2 Cl,C2 Cl,C2 Cl,C2 C3
C3
C4
. C4 C5
C5
4-218
Confidential and Proprietary
Parameter
Output reverse current Low-level output voltage
18ble 4 · DC003 Open-collector Bus Driver Parameters
Symbol Test Condition
Requirements Min. Max.
Units
Io.
Vcc=4.75 V
Von=3.fV
VoL
Vcc=4.75V
l,1.k=70 mA
Vcc=·DV I..-=16mA
25
µA
0.8 v
0:5 v·
Test
Circuit Cl
C2
C2
ac Electrical CharacteristiCs The input/output signal timing for the interrupt logic A is shownin Figure 3. The input/output signal timing for interrupt logic A and interrupt logic Bis shown inFigute4. Refer to Appetrdix D
for the standarg input voltage waveforms and f()r the ~igi:#pr,opagation delay measurements. The
load circuit configurations used in measuring the TTL outputs and open-collector outputs are shown in Figure 5.
BINIT~=f
I
I
I 7-35 I
rmrn~i ·,.c.::.:..J..I1-.-------------------------------------------------
I
I
ENAOATA
' I
ENA CLK . 30 MIN__,.: Fl..-------------R""·---------.......-
1
ENAST
F I
7-30--l ,
I...__________....,_
ROSTA -------""!,
1=:: F I
15-65-l
-1
20-90
I
I
.
I I I
I I
l:::..J ~---------------';.....;'
BIAKI
35 MIN-j
I
l:::..J 35 MIN-JI
I
I
I
I
I
I
I
I
-+l--._:- - - - - - - VECTOR _ _ _ _ _ _ _1._Q-4_5_.....,_'_.R.._l-_1_G-4_S_ _ _ _
·
BIAKO
---------~---------------------+I-I . 12-55----i l::.
:
I :Il
.
}
=12-55
Figure 3 · DCOOJ Interrupt Logic A Signal Timing
Confidential.and Prpptietary
4-219
-
ENB DATA
bcoo}:
ENA DATA ENA CLK
ENA ST
I I
30MIN---! ~~~--------------------...;..--~--------~
LJ
I I
l=:J ------------------------~~---1...;I
BIAKI
35 MIN-:
I
LU
I I
I 35 MIN-j
lI:!::_J
I I
I
I
VECTOR~----------------------~1-0-_4_5_'""'!I__.!I =FI1~1-Q_-4_6_______1__0-_45I~~i~--1I0·-45
I
I
VECRQSTB----------------------------------------~~----15_~_6_5-~1--1-5' -65
Figure 4 · DC003 Interrupt Logic A and B Signal Timing
4-220
Confidential and Proprietary
TEST POINT
FROM OUTPUT
DC003
Vee
2800
ALL DIODES FD777
LOAD A OPEN-COLLECTOR CIRCUIT
LOAD 8 TTL CIRCUIT
Figure 5 · DCOOJ Output Load Circuits
Confidential and Proprietary
4-221
·Features
·Used with the DC003, DC005; and DC006 citcuits to implement a program control device
interface.
· Used with the DC003, DC005, DC006, and DCOlO circuits to implement a direct memory access interface.
· Controls data transfers to and from asinany as four 8-by~.~9rd registers. · Prov.ides variable-delay logic for device response to trans,ferrequests.
· Includes Q-bus drivers and receivers, .
· Description
The DC004 register selectot; containeq ~n a 20-pin d~-iqlipt:.package (DIP), provides the signals
to control the transfer of data to 11.nd·from as many as fout word registers (8-bytes). The Q-bus signals directly connect to high-impedanee r¢eeivers and to high-current drivers on the DC004. A
resistor and capacitor circuit (RC) is included ~ dday the response of the peripheral interface to the
data transfers. An external RC network qm .~.added to val( the delay time to conform to the
device requirements. Figure 1 is a siffiplifi~ .logic diagrafu Jf' the DC004 which includes bus
latching circuits, enable logic, and a decoder used to select the registers.
..------Yee
D3 02
OECOOER 01 DO
VECTOR-----------'
Figure 1 · DC004 Simplified Logic Diagram Confidential and Proprietary
Set1i m:4 ml
mo
&l'i'H1!
OUT LB AXCX
mmv
1llWfi
4-223
.DC004
· P-m and Signal Pescriptions
This section provides a brief description of the input and output signals and power and ground connections of the DC004 20-pin DIP. The pin assignments are identified in Figure 2. and the summarized in Table 1. The signal names shown in the diagram are for the condition where the DC004 is connected to the internal three-state bus of the DC005.
VECTOR
BfiAI2
BOAL 1
Eil'.5AIO lm'l'm'
~ 6 mJllil
i!ifiP[Y
imm:rr 9 GND
TOP VIEW
Vee
ENB RXCX
rn:6 !!IT4
rn2 SITO
OU'fTij
/JO'f"1rn
rmw
Figure 2 · DC004 Pin Assignments
. 4-224
Confidential and Proprietary
Table 1 · DC004 Pin and Signal SQ,nunary
1 VECTOR
inpur'
2-4 BDAL < 2:0 > inputl
5 BWTBT
inpuf
inpuf
7 BDIN
inpuf
8 .·'BR'PLY
9 BOOUT
10 GND 11 iNWi5
u OUT LB
13 OUTHB 14 SELO 15 SEL2 16 SEL4 17 SEL6 18 RXCX
outptit'
input2 input output1 outputs1 outputs1
output1
Interrupt· vector gating-Asserted by the interrupt logic
(DC003) to gate· the appropriate vector address onto the
bus... 'this ~nal generates thejJ'U>iY output signal to the
bus after a time delay select~ by. the RC net:Work con-
nected to pin 18 (RX:CX).
· ·
to Bus data/address lines-The information ontheseJines.is
latched by the ,JjS.YNC ·sigrulJ.. froiµ .the pus. .~nd ust;i;i
select one or mQre of the 8-bit registers connected to the
S'EI:1J, ~. S'EL4' and SELb lines.
Write/Byte-Selects a byte or ~rd o~tion wh®: the
npqyt ~.i~nal.,.is.... asserted: B"Tst:. asserted=byte, ir~ttt pega~d =word. Tlie'GtcheJ output of this signitl
is gated with BI5ouT ·to' select a tow:byte ·or high-byte
output.
Bus syn~hro,nize-Asser~by t.he bus master to indicate
tha(ah ililtirt;ss is~nthe ~{tS:'W'hen ~serted;it disables
all the ·ou~uts extepi· tJ.lei·\l"ecror ·gerrerated· output of
BRPIY.
. .
Bus datain..,.-,Asser~ bY'·the:bus.rnas~· to effect adata
input transaction when the BS"Y"NC signal is asserted.'. It genemteS themrPIY outpufthrough the delay circuit and the iN'Wi5 output.
Bus reply.c....Assertedby·:tbe·slil.ve device· to indicate that
data 1:&: availlible on the ·m.5At busor diat the device has
accepted output data from the bus.
Bus da~,o~'""".~~~rt~,py )the ~evice toJ~dicate ~hat device data~ ~r-railabl~ on ~~Jines. .·· . .. ,
Ground-Common ground connection
In word-Asserted to gate the data from a selected J:e8ister
. to the bus.
· Out l~-bYte. Out high"bYte+'u$Cd .tQ~@a.;1. tb,e ~-byte,
high-byte; or both bytes ofthe write data fromthe sdCcted
register cinto the bus.
..
.· . . ' ,
Select decoder 0, 2, 4, and 6 output lines-Selects a word register for a data transaction.
External RC node-The value of the resistor and capacitor
network connected to this pin determines the delay of the BRPLYsignal.
Confidential a,nd Prop~etary
4-225
-
PC004
Pin Signs]
Input/Output. ~tion/Functiolt
19 ENB
input···
Enabl~-Asserted to enable the SE'i::O, SEL 2, SEL 4, and
SEL 6 outputs. -0£ the decoder and the adQ.ress term of
BRPLY.
20 Vee
input
Voltage-Power supply de voltage
'TTL level 2high-impedence >open-collector 4connected to Vcc through an 8500 resistor
· Application Infortnation
Refer to the Chipkit Users ManualLSI-11 Bus Int:erface Chips (document no. EJ-01387-92) for general
application information. The Q-bus is an LSI-11 bus.
· Specifications The mechanical, electrkal, and environmental characteristics and specifications for the DC003 are
described in the following paragraphs. The test conditions for the electrical values are as follows unless specified otherwise. · Operating temperature (TA): 0°C to 70°C ·Supply voltage (Vee): 5.0 V ±5%
Mechanical Configuration
The physical dimensions of theDC004 20-pin DIP are contained in Appendix E. The materials and construction of the molded DIP are defined in Digital Specification A-PS-2100002-GS.
Absolute· Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may adversely affect the reliability of the device. · Supply voltage (Vee): 7.0 V · Input voltage (V1): 5.5 V · Operating temperature (TA): 0°C to 70°C · Storage temperature (T5): -65°C to 150°C
4·226
Confidential and Proprietary
...
Recommended Operating.Condidons
v v v · Supply w!~ Ned: 4.75 (minimum), 5:0 (normal), 5.25 (maxiinum)
· Supply current (lee): 120 ml\ (maximum)
· Free-air temperature: 0°C to 70°C
· Relative humidity: 10% to 95% (noncondensing)
de Electrical Characteristics The de elec~rical charac~ristic~ of the D<::@4 for the openit~ v9l~~ and temperature ranges
specified are listed in Tables 2 through 4. Tuble 2 lists the de ,spec+ficati91is £or the TTLinput and
outputs that do not connect to the Q-pus pus.. J?:l>Je .3 lii;~&. tll~ ;4'= ~~~ications fo! die highimpedance receiver inputs from the Q-bus bus. Table 4 li~ts thi de specifications for'the 0,pen-
collector driver ou~uts that connect to the Q-bus. Refer to Appendix C for test circuit configurations listed in the tables.
· Note: Pin 18 (RXCX}of the DC004must be connected to Vee through a 1-kn ±5% resistor for performing all the de tests· shown in th~ te5t ~tdiagtams in:A!ppendix C.
Pammeter
High-level input voltage
Low-level input voltage
Input clamp voltage High-level output voltage Low-level output voltage
Input current atmaxinmm input voltage
High-level input current
Table 2·· DC004 TTL Input and'OQtput. p;p..meters
Symbol Test Condition
Re~ts.
Min Max
Units
Vm
2.0
v
Va
0.8 v
V1
Vcc=4.75V
li=-18 mA
VoH
Vcc=4.75
2.7
Io=-1.0mA
VoL
Vcc=4.75V
Io=20mA
I1
Vcc=5.25 V
V1 =5.5 V1
-1.2 v
v 0.5 v
1.0 mA
...
Circuit C1,C2 Cl,C2 C3 Cl C2 C4
Im
Vcc=5.25V
V1 = 2 . 7 V1
50 µA
C4
Confidential and Ptoprietaty
-a
DC004
Parameter
Symbol Test Condition
Requirements Min . Max'
Units Test
Circuit
Low-level
111
Vcc=5.25 V
input current
V1 =0.5V
-0.70 mA
C5
Short-circuit
Ios
output current
Vcc=5.25V2
-40
-100 mA
C6
Supply current
Ice
Vcc= 5.25 V
120 mA
C7
'Limits for pin 19are:11=1.4mA, IH=-2.25 mA (minimum) and-3.85 mA (maximum), IIL =-4.5
mA (rninii:num) and ..:.a.o mA (maximum).
·
'Not more than one output shall be shorted at atime and the duration of the short shall not exceed
1 second.
·
·
Parameter
High-level input voltage
Low-level
input voltage
Input clamp
voltage High-level input current
Low-level input current
Table ; · DC004 High-impedance Bus &ceiver Parameters
Symbol Test Condition
VIH
Vcc=4.75V
Vcc=5.25V
VIL
Vcc=4.75 V
Vcc=5.25 V
v,
Vcc=4.75V
li=-18 mA
Requirements Min Max
' 1.53 1.70
1.30 1.47
-1.2
Units
v
v v
v v
Im
V1=3.8 V
Vcc=OV
Vcc=5.25 V
40
µA
40
µA
I,L
V1=0V
Vcc=OV
Vcc=5.25 V
-10
µA
-10
µA
Test Circuit Cl,C2 Cl,C2 C3
C4
C5 C5
4-228
Confidential and Propriet;ary
oc004·
Table 4 · DC004 Open-collector Bus Driver Pamtneters
Parameter
Symbol Test
Condition
Requiremen~
Min Max
Units
Output reverse
IoH
current
Vcc=4.75 V VoH=3.5 V
25'
µA
Low-level
VoL
Vcc=4.75 V
output voltage
L... = 7 0 r n N
.mk=16mA'
l...=15 mA3
0.6 v 0,5 v 0.5 v
165 µA for pin 18 (RXCX). 2Applies to pin 8 only (BRPLY). 1Applies to pin 18 only (RXCX).
Test Circuit Cl
C2
ac Electrical Clwacteristics
The input and· output signal tirriing for the DC004 ·is shown in Figure 3. Tuble 5 lists the specifications for the values referenced on Fi~ 3. The open-collector and TTL output load
circuits referenced in Thble 5 are sh0wn in Figure 4. Refer to Appendix D for the standard input
voltage waveforms and for the signal propagation delay measurements.
Confidential and Proprietary
4-229
BDAL<2:0> 2/%a25 Mlt+5 M l w #:1/%%:7;@'~
eNs0/M~rNIJrNWffiW7##~ ·
I I I
I
I
I
I
I
I
-l~F
~0007#~
I
immTf
15 MIN--:I
I
Wu#~
I I
=J111~ : j
Ii ·
~t12f
"~ ...._~~~
I
-1 -~~~~~~---~--~-'!---.
ITTWi:Y
t13I:-
I
1I tl~fr-=-2-.4~V~----~--~---~
I
'------""',--'
I
I
VECTOR
-
-
-
-
-
-
-
-
-
-
-
-
!
' I
I
RxCx H
-iI ,, 5F
b
I
/ _~ J
I
-!I t15 b...____________
.TIME REQUIRED TO DISCHARGE Rx CxFROM ANY CONDITION ASSERTED= 150 ns.
NOTE TIMES ARE IN NANOSECONDS.
Figure 3 · DC004 Signal Timing Sequence
4-230
Confidential and Proprietary
-
LOAD A OPEN-COLLECTOR CIRCUIT
DQ>04··.
FROM OUTPUT
TEST P()tNT
Vee
R2
ALL DIODES F0777
CONDITION 1
R2 = 2800
C2=15pf
CONDITION 2 R2= OPEN
C2 = 160 pf
LOAD B TIL CIRCUIT
Figure 4 · DC004 Output Load Circuits
Timing Reference
...,
T5,T6
T9, TlO
TU, T12
Table 5 · DC004 Signal Timing Specl&ations
Signal1
Signal1
Output Tuning {ns)
(Load/condition) (Load/condition) Asserted
Negated
Min Max Min Max
SELO (B/2) SEL2 (B/2) SEL4 (B/2) SEL6 (B/2)
BSY'NC
15
40
15
40
15
40
15
40
5 30 5 30 5 30 5 30
OUT LB (B/2) OUTHB (B/2)
BOO UT
5
30
5
30
5 30 5 30
iNWD(B/2)
BDIN
5
30
5 30
Confidential and Proprietary
4~231
-
Timing Reference
DC004
SignaP
Signal1
Output Tuning (ns)
(Load/condition) (Load/condition) Asserted
Negated
Min Max Min Max
Tl3, T14
BRPLY(A)2
OUT LB (B/1)
20
OUTHB (B/1)
20
INWD (B/1)
20
VECIDR
30
60 -10 45
60
-10
45
60 -10 45
70
0
45
OUT LB (B/1)
300
400
-10
45
OUTHB (B/1)
INWD (B/1}
VECTOR
330 430
0 45
T15, T16
RXCX (A) 2
OUT LB OUTHB INWD VECIDR
10
50
10 50
'Refer to Figure 4 for load circuit configurations. 'Pin 18 connections: Rx=3.30n 5%, Cx= 15 pF 5%. }Pin 18 connections: Rx=4.64 kn 5%, Cx=220 pF 5%.
4-232
Confidential and Proprietary
·Features
· Used with the DC003 and DC004 circuits to.implement a program control deviceinterfiace.
· Used with the DC003, DC004, DC006, and DCOlO chl::uits toimplementa direct QJ.emory access
interface.
· Functions as a bidirectional buffer between the device logic a_nd oomputerbus. · Includes comparison circuit f~r device address selection. · Includes constant generator for interrupt vector address generation.
· Includes Q-bus drivers and receivers.
· Description
The DC005 4-bit transceiver, contained in a 20-pin dual-inline package (DIP), implements lowpower Schottky technology and functions as a bidirectional buffer between a data bus and peripheral device logic bus. It includes a comparison circuit for device address selection and a constant generator for interrupt-vector address gerietatfun. ~tprovides high-impedance inputs and
high-drive, open-collector outputs to allow direct connecti09 t0 a computer data bus structure. The bidirectional device port includes TTL inputs and thr¢e-state driver outputs. Figure 1 is a
simplified logic diagram of the DC005. ·
Figure 1 · DC005 Simplified Logic Diagram Confjd~ntif¥ ~d Proptj.etary
4-233
·--·-·-·-·------------ ,.... .,......,--·----------·
-·
DCOOS
Three address select inptlts <:;an he configured by jumper leads to enable a comparison to be made
between the jumper connections and three bus inputs. An open-collector MATCH output allows several transceiver outputs to be gated to form a composite address match signal. The address jumpers can also be configured to disable the address match condition. The address match condition is controlled by an input line that can enable or disable the MATCH output.
Three vector inputs can also be configured by jumper leads to generate a constant vector value that
is transferred to the computer bus. The vector inputs directly drive three of the bus lines to override the function of the control lines.
Two control signals are decoded to select the receive data and transmit data operation and to disable the operation of the device.
· Pin and Signal Descriptions
This section provides a brief description of the input and output signals and power and ground connections of the DC005 20-pin DIP. The pin assignments are identified in Figure 2 and the summarized in Table 1.
JA1 JA2
MATCH
GND
Vee
JA3
DATO
DAT1
JV3
JV2 JV1
ME'NB BUsn
tms1
TOP VIEW
Figure 2 · DC005 Pin Assignments
4-234
Confidential and Proprietary
Table 1 · ncoo; Pin and Signal Summary
Pin
Signal · Input/Output Definition/Function
8-12
BUS< 3:0 > input1/output2 Bus 3-0 lines-These lines are bidirectional and con-
nect to the BDAL lines of the Q-bus. A low is equal to 1.
6,7,17,18 DAT< 3:0 > inputs/outputs3
Data 3-0 lines-These lines transfer the inverted data
from the bus tothe device in receive mode and from the
device· to the ·bus in transmit :tnode:·During· disable
mode, the outputs are ata highimpeditnce.
16-14 JV< 3:1 > inputs4
Vector jumpers '"3-1::...-The!Se · lines directly .drive the
BUS< 3:1 > lines. A grouQd connection or .an open
jumper pin causes·an open condition on the corres-
ponding bus pin if the ·XM.IT signal is asserted. A high
(5 V) connection to the jumperpirlwillcatise a one(low')
·on the'coriesp()nding bus piit TheBUS'<O> line is
not controlledbya jutrtper. ·
·
13
MENB
input1
Match enable-A low input wi)J e~hle the.MATCH
.Qutput when .a match O(;CUI:S .~n the.. level of
BU$< 3:1> signals ~ttd the address jumpers JA3
through JAl.
3
MATCH output'
Address match-This output.. is. open when a match
occurs between the level of the BUS;<3:l>.lines.and
the levels ~ by ~he address iUffipers JV3 through
JV1. The output islow when no match occurs.
19,2,1 JA < 3:1> inputs,
5
XMIT
inputs)
4
REC
20
Vee
input
10
GND
input
· Address jumpers-When connected to. ground, these
pins allow a match to occur with a one Gow) on the
corresponding BUS <Jff> ·lines, Whert these lines are
nof connected, a. ~teh. can occur with a. zero (high)
level on the corresponding bus lines. When connected
to
5
V,
t.h.
e -
c.orre'-s·p- o...rtdi.ng
addres5
bit
is
disconnected:
Transmit/Receive·control-Controls:the operation of
the transcCiver as. follom:.
REC XMIT Function
0
0
Disable(open): BUS and DAT lines
0
1
Transmit: DAT to.BUS lines
1
O Receive; BUS to DAT lines
1
1
Receive: BUS to DAT lines
Vol~ge-Powersupply de voltage
Ground~Common ground reference
1high-impedence 2open-collector 'TTL level 4TTL level with pull-down circuit
'three-state
Confidential anP:.Proprietary
4·23.5
· Application Information Refer to the Chipkit Users Manual LSM1 Btis lntet'/ace Chips (document no. EJ-01387-92) for general application infol'.mation. The Q-bus is an LSI-11 bus.
·Specifications
The mechanical, electrical, and .environmental characteristics and specifications for the DC005 are described in the following paragraphs. The test conditions for the electrical values are as follows unless specified otherwise. · Operating temperature (TA): 0°C to 70°C
· Supply voltage (Vee): 5.0 V ±5%
Mechanical Configw:ation . The physical dimensions of the DC005. 20~pin DIP are contained in Appendix E. The materials and construction of the molded DIP are defined in Digital Specification A-PS-2100002-GS.
Ab~lute.Maximum Ratings Stresses greater thari the absolute maximum ratings may cause permanent damage to the device. Exposure to the absolute maximum ratings for extended periods may adversely affect the reliability of the device.
· Supply voltage (Vcc): 7.0 V
· Input voltage (V1): 5.5 V · Operating te~perature (TA): 0°C to 70°C (32°F to 158°F) · Storage temperature (T5): -65°C to 150°C (-149°F to 302°F)
Recommended Operating Conditions · Supply voltage (Vccl: 4.75 V (minimum), 5.0 V (normal), 5.25 V (maximum) · Supplycu~ent (lee): 120 mA (maximum) · Free-air temperature: 0°C to 70°C (32°F to 158°F) · Relative humidity: 10% to 95% (noncondensing)
de Electrical Characteristics The de electrical characteristics of the DC005 for the operating voltage and temperature ranges specified are listed in Tables 2 through 6. Table 2 lists the de specifications for the TTL input and outputs that do not connect to the bus. Table 3 lists the de specifications for· the high-impedance receiver inputs from the bus. Table 4 lists the de specifications for the open-collector driver outputs that connect to the bus.. Table 5 lists the de specifications for the three-state jumper lead connectiOns inputs used for the address comparison logic. Table 6 lists the de specifications for the TTL jumper leads connections used to select a vector address. Refer to Appendix C for test circuit configurations listed in the tables.
Confidential l1ild Proprietary
···
Parameter
High-level input voltage Low-level input voltage Input clamp voltage High-level output voltage Low-level output voltage Input current at maximum input voltage High-level input current
Low-level
input current
18ble 2 ·DCOOS TTL Input amf·Output Ptmulleters (nonbus)
Symbol Test Condition
Vm
Requiretnents Min. Max.
2.0
Units
v
VIL
0.8 v
V1
Vcc=4.75 V
-1.2 v
li=-18 mA
Von
Vcc=4.7V
3;65
v
lo=-1.0mA
VoL
Vcc=4.75V
0.5 v
Io=20mA
Ix
Vcc=5.25 V
V1 =5.5V
1.0 mA
Im
Vcc=5.25 V
V1=2.7V
Receive:
Transmit:
lit
Vcc=5.25V
V1=0,5Y
Recei\te: ·
100 µA 50 µA
-2.2 mA
DCOO;
Test Circuit
Gl,C2 Cl,C2 C3 Cl C2 C4
C4
C5
Transmit:
-1.1 mA
Short-circuit
los
output current
Vcc=5.25V1
-40
.-100 mA
C6
Supply current
lee
Vcc=5.25V
120 mA
C7
High-impedance Io
state output
current.2
Vcc=5.25 V V1 =3.65 V V1=0.5 V
100 µA -0.36 mA
1Not more than one output shall be short circuited at a time and the duration ofthe short: shall not
exceed 1 second.
20ff state, DAT< 3:0 > pins only.
Confidential and Proprietary
4-237
-
Parametet
High-level input voltage Low-levd input voltage Input damp voltage
Tablt; l . · OCOOS. High·imp~e Bus Receive!'. Parame~
Syo1bol .Test .·Condition
Vm
Vcc=4.75 V
Vcc=5.25 V
VIL
Vcc=4.75 V
Vcc=5.25V
V1
I1 = - l 8 m A
Vcc=4.75 V
Requirements
Min. Max.
1.53 1.70
1.30 1.47
-1.2
Units
v
v
v
v
v
High-le'7el input current MENB
BUS
I,H*
V1 =3.8V 2
Vcc=OV Vcc=5.25 V Vcc=OV Vcc=5.5V
40
µA
40
µA
65
.µA
65
µA
Low-level
I,L
Vr=0.5 V
input current
Vcc=OV
Vcc=5.25 V
-10
µA
-10
µA
*Includes open-collector leakage current on bus
Test
Circuit Cl,C2 Cl,C2 C3 C4
C5
'.lable 4 · DC005 Open-collector Bus Driver Parameters
Parameter
Synabol Test Condition
Requirements
Min. Max.
Units
Output reverse
IoH
current*
Vcc=4.75 V VoH=5.25 V
25
µA
Low-level
VoL
Vcc=4.75 V
output voltage
MATCH
I.1nk=8 mA
BUS<3:0>
Is1.k=70 rnA Isink= 16 mA
0.5 v 0.8 v 0.5 v
*Pin 3 only (MAtCH). For BUS< 3:0> pins, refer to Im Table 2.
Test Circuit Cl
C2
4-238
Confidential and Proprietary
-
Parameter
High-level
input voltage
Low-level
input voltage Open-circuit input voltage
Table 5 · DC005 TTL Three-state Address Input Parameters
S~bol
Vrn
Test Condition
Requirements
Min. Max.
4.75
Units
v
VxL
0.3
v
VoP
4.75 <Vee> 5.25 1
2
v
DCOO'
Test Circuit Cl
Cl
. 18ble6 · DC005 TTL Vector Input Parameters
Parameter
Symbol Test Condition
· Requirements
Min. Max·.
High-level
V1H
2.0
input voltage
Low-level
VIL
0.8
input voltage
Input clamp
VI
Vcc=4.75V
-l.2
voltage
I1 = - l 8 m A
High-level
Im
Vcc=5.25 V
1.2
input current
V1=2.4 V
Low-level
Vu
Vcc=4.75V
0.8
input voltage
I1=0.1 mA
forcing current
Input current
IIL
Vcc=5V
at maximum
V1=0.4V
input voltage
50
200
*Remaining inputs open.
Units
v
v v v
v
Test
Circuit
Cl Cl C3 C4 C4*
C5
ac Electrical Characteristics
The input and output signal timing parameters for the DC005 are grouped by functions and shown in Figure J. Figure 4 shows the load Circuits used to meas\lre the sign.al timing for the open-collector and three-state outputs. Figilre 5 shows the three-state voltage waveform parameters. Refer to Appendix D for the standard input and output voltage waveforms parameters used to measure propagation delay.
Copfidential and Proprietary
4-239
-
XMIT
· TRANSMIT DATA TO BUS
DC005
j.--s TO 30 ns
BliS - OUTPUT DAT- INPUT
5 TO 25 ns----!
RECEIVE DATA FROM BUS (BUS INITIALLY HIGH)
______ REC
.....
DAT-OUTPUT
_- ..-.J;
--I i1-...-__-.o TO 30 1---o nsr,~~~~---~--~....;,j TO 30 ns
Hl-z--.
'--- - - - - H l - Z
....... ~~~~~
-;o.f.
..-~~~~--;
~8 TO 30 ns
BUS- INPUT------
RECEIVE DATA FROM BUS {BUS INITIALLY LOW) XMIT ( G R O U N D ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
REC
- - - - - - - i - DAT-OUTPUT
------ l=e BUS- INPUT
fe--o TO 30 ns
Hl-Z----''---!
TO 30 ns
--..j
j---o TO 30 ns
I
Hl-Z
VECTOR TRANSFER TO BUS
JV1-JV3 BUS-OUTPUT
BUS-INPUT MATCH
MEN8
XMIT
--1 loi- 20 ns MAX
J.-...20 ns MAX
ADDRESS DECODING
-I
j--10 TO 40 ns
- t 1-o-- 5 TO 40 ns
--!
'4--10 TO 40 ns
RECEIVE MODE LOGIC DELAY
!-----40 TO 90 ns
4-240
figure 3 · DC005 Sif!Jlal Timing Sequence Confidential and Proprietary
·-
TEST POINT
ocoo;
R1 = 2K
ALL DIODES= FD777
~S2
= R1 60 0 FOR PINS 8, 9. 11, 12. = R1 475 0 FOR PIN 3.
C1 = 15 pf AT PIN 3.
LOAD A OPEN-COLLECTOR CIRCUIT
LOAD B THREE·STATE CIRCUIT
Figure 4 · DC005 Output Load Circuits
----------- - - --
REC
1.5 v
1ZL OATX
$1 CLOSED
"1'.,, -1.5 v
S1 OPEN S2 CLOSED DATX
1.5 V
ov
$1 AND S2 CLOSED
THREE-STATE VOLTAGE WAVEFORMS
Figure 5 · DC005 Three-state Voltage Waveforms
Confidential and Proprietary
4-241
·Features
· Used with the DC00.3, DC004, DC005, and DC010 to irriplemerit a direct memory access
interface. · Contains two 8-bit binary up counters for word byte count and bus address. · Implements low-power Schottky circuits. · Includes readandwrite control logic.
· Includes comparison circuit for deviee address selection. · Two DC006s can be cascaded for 16-bit register implementation.
· Contains internal 8-line bus and three-state bus drivers.
· Description The DC006 word count/bus address logic, contained in lit ~Q-pin dual-inline (DIP) package, is
designed for use in a direct memory access. (DMA) dey~jn~erface. The DC006 is a low-power
Schottky device that connects to the th~·state'oi.ltputs ofthe DC005 transceiver. The DC006 is
controlled by the DC004 register sel~ the DCOlO dj.rect memory access, and ancillary logic.
Figure 1 is a simplified block diagram of the·DC006.
MAX·A CiJf.i:
MAX·C
READ CONTROL LOGIC
RD·A f l 4 - - - - - I
R6 t > - t - - - - 1
SEL MULTIPLEXER ENBL
Figure 1 · DC006 Simplified Block Diagram Confidential and Proprietary
4-24.3
...
DC006
It includes two separately controlled8-bitbioary up-counters, onefor word (byte) C9UDt and one
for bus address. Each counter can be separately loaded and cleared. The word counter (G counter)
is incremented by a count of one and the address counter (A counter) is incremented by a count of
one for byte addressing and by a count of two for word addressing. Each counter is read separately.
Data from the DC006 is transferred to the three-state bus through the internal drivers.
· Pin and Signal De~criptions
Tiris section provides a brief description of the input and output signals and power and ground
connections of the DC005 20-pin DIP. The pin assignments are identified in figure 2 and then
summarized in Table 1.
·
-
MAX-A S-A
CLK·A
RO-A
RB CiiiTIA
1 0/F 2 D/F 4 D/F
GNO
TOP VIEW
Vee
S·C
i1i
MAX·C CLK·C 128 0/F 64 .Q/F 32 D/F 16 D/F 8 0/F
Figure 2 · DC006 Pin Assignments
4·244
Confidential and Proprietary
-
Ym Signal
2 S-A
19 S-C
4 RD-A
5 RD
18 LD
7 lD/F 8 2D/F 9 4D/F 11 8D/F 12 16D/F 13 32D/F 14 64D/F
15 128D/F
1 MAX-A
DC006
Table 1 · DC006 Pin and Signal Summary
Inpt1t/Outpnt Definition/Function
input input·
Increment counter A-Controls the least significant bit of the A counter . Wheniow the A counter is incremented by one. When high, the least-sigajffoant bit ofthe A counter is disabled and the count is incremented by two. When two counters are cascaded,
this input shouktbe connect~ to ground.
Clock A counter~The nega'tive edge of this signal increments the A counter by one or two count~ depending on the CNTIA level. The CNTlA and LD signals must be stable while the CLKA signal is high.
input
Clock C counte,r-The negative ecige of this signal increments
the. C counter bY a coupt of one. The L:O signal. must be stable
while the ct'K-e_signal is high.
input
Select A counter-Selects the outputs and functions of the A counter during read and write operations as specified in Tables 2 and3.
input
~elect C counter.:-c-Sdects the outputs and functions of the· C
counter during read and write operations as specified in Tables 2
and3.
.
input
Read A counter~Selects the outputs and functions of the A
counter during read and write operations as specified in Tables 2 and3.
input
Read-Enables a read operation as specified in Tables 2 and 3.
input
Ll>ad_:_A high-to-low trar1sition of this signal enables a load operation tobe performed as specified in Table 3.
When ID is low, data changes will not occur.
outputs*
Data bus-Eight bidirectional lines used to transfer data into or out of the A counter or C counter.
output
Maximum A count-Indicates that the Acounter has reached a
maximum count. The maximum count is 376 when counting by two and 377 when counting by one. The signal is generated by gating CLK-A and the maximum count condition of the counter.
Confidential and Proprietary
4-245
t>C006
Pin Signal 17 MAX-C
Input/Output Definitiorl/Function
output
Maximum C count.:_Indicates that the C counter has ~ached a.
maximum count of 377.
This signal is generated by ·gating CLK-C and the maximum
count condition.
20 Vee
input
Voltage-Power supply de voltage
10 GND
input
Ground-Common ground connection
*TTL three-state
Functlo~ Description Figure 3 is a simplified logic diagram of the DC006 that shows the read and write control logic, the inputs and outputs of the A and C counters, and the multiplexer logic. Table 2 lists the read and select inputs required to read the counter outputs. Table 3 lists the write-control inputs required to load and clear the counters.
Table 2 · DC006 Read"contro) Functions
Input Levels*
Output Functions
RD-A
RD
S-A
S-C
D/F<7:0>
L
L
L
L
Clear A and C counters, read C counter
L
L
L
H
A<7:0>
L
L
H
H
C<7:0>
L
H
H
H
High-impedance
L
H
x
x
High-impedance
H
L
L
L
Clear A and C counters, read A counter
H
L
L
.H
A<7:0>
H
L
H
L
A<7:0>
H
L
H
H
A<7:0>
H
H
L
L
Clear A and C counters, read A counter
H
H
L
H
A<7:0>
H
H
H
L
A<7:0>
H
H
H
H
A<7:0>
"L =TTL low, H =TTL high, X =TTL low or high
4-246
Confidential and Proprietary
...- -----·.- · ____.,__ ~~-
----.--.---.=----~-~~..,.--
-·--~~~-~-~-~·-··
: DC006
Table 3 · DC006 Write-control Functions
Inputs Levels1 RD-A RD
Function
L
H
H-L
L
L
Illegal2
H-L
L
H
LoadA<7:0>
H~L
H
L
LOadA<::..7:0:>
x
H
H
Word count/Bus· address not selected
H
L
L
Clear A and B c6\:inters
H
L
H
Loilding ~Jed
H
H
L
Lo~ i:lil!abled .
1L=TTLlow, H=TTL high, X=TTLlow or high, H-L=high-to"lowtransition. 2Simultaneous load and clear operation results in a clear.
DIF 10'1> RO
RO·A
~. l CCOUNTER
Sllit;lll!llAJll';.
LUDPC .C.H.O··.VNlER ~. : C <?,O>
CiJ<'.C - - . - - - - - - - - - - - + - - - - U C L K C ;. L
g: I
'-----ICLR H
01 I .
. .
DIF<7:0>
Figure 3 · DC006 Simplified Logic Diagram
Confidential and Proprietary
~-·-·--·--·-·--·------·-----
4-247
-·
DC006
· Application Information
Refer to the Chipkit Users Manual LSI-11 Bus Intetface Chips (document no. EJc01387c92) for general
application information. The Q-bus is an LSI-11 bus.
· Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DC005 are described in the following paragraphs. The test conditions for the electrical values are as follows unless specified otherwise.
· Operating temperature (TA): 0°C to 70°C · Supply voltage (Vcc):5.0 V ±5%
Mechanical Configuration
The physical dimensions of the DC005 20-pin DIP are contained in Appendix E. The materials and construction of the molded DIP are defined in Digital Specification A-PS-1900002-GS.
Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device. Exposure to the absolute maximum ratings for extended periods may adversely affect the reliability of the device.
· Supply voltage (Voc): 7.0 V ~ Input voltage (V1): 5.5 V
· Operating temperature (TA); 0°C to 70°C (32°F to 158°F)
· Storage temperature (Ts): -65°C to 150°C (-149°F to 302°F)
Recommettded Operating Conditions · Supply voltage (Vee): 4.75 V (minimum), 5.0 V (normal), 5.25 V (maximum) · Supply current Ucc): 140 mA (maximum)
· Free-air temperature: 0°C to 70°C (32°F to 158°F) · Relative humidity: 10% to 95% (noncondensing)
de Electrical Characteristics
The de electrical characteristics of the DC006 for the operating voltage and temperature'ranges
specified are listed in Table 4. All input and outputs are TTL levels. Refer to Appendix C for test
circuit configurations referenced in the tables.
4-248
Confidential and Proprietary
-
00Co86
Table 4 · DC006 Tn Input and Output Parameters (nonbus) ·
Parameter
High-level input voltage
Low-level input voltage
Input clamp voltage
High-level output voltage
Low-le\lel output voltage
Input current at maximum· input voltage
Symbol Test Condition
Vru'
Vu.
V1
Vcc=4.75V
11=-18 mA
VoH
Vcc""4.75
lo=-l.OmA
v~L
. Vcc=4.75V'
Jo=!:20 tnA.
Ix
Vci=5.2;5 V
V1=5.5V1
Requimnent!I
;Min. Max.
2.0
-
Uni1'
v
0.8 v
Test
Circuit Cl,C2
Cl,C2
-1.2 v
C3
2.7
';:r-
v
Cl
--/,i-~
v
C2
lnA C4
High-level
Im
input curtent
Three-state ·
Not three-state
Vcc=5.25 V Vr=2.7V
,:;_
·~~-:
C4
50 µA µA
Low-level
In.
input current
CLK-A, CLK-C
CN'i'IA
D/F<0:7> LD,RD, S-C,
s:A
RD-A
ro· High-impedance
output current
Vcc=5.25 V V1=0.5 V
Vcc=5.f5V ·Vo=3.75V
C5
-1.1 mA -1.7' mA
lOO µA
. 200... .w\
100 µA
Cl
Short-circuit
Ios
output current
Vcc=5.25V2
-40
-100 mA
C6
Supply current
Ice
Vcc=5.25 V
170 mA
C7
1Three-state TTL output in off state. 2Not more than one output shall be short circuited at a time and the duration of the short must not exceed 1 second.
Confidential and Proprietart
4-249
·----------~---·-----------
-
DC006
ac mectrical Char&cteri$tics
The input and output signal timing for the DC006 ~'shown in Figure 4. Table 51ists the setup time
and pulse characteristics for the times specified in Figure 4. Table 6 lists the propagation delays for
the signal timing references in Figure 4. Refer to Appendix D for the standard input and output
voltage waveforms parameters used to measure propagation delay. The output loading circuit for
the open collectors and the three-state output loading circuit and voltage waveforms are shown in
Figure 5. These circuits are referenced in Thble 6.
. ·
10/F 20/F
CLEAR
LOAD
Figure 4 · DC006 Signal Timing Sequence
4-250
.. Confidential and Proprietary
-
'f"mii .
~( t) (pulse width) t, (setup)
~(setup)
t 7 (pulse width)
ta (setup) tu (pulse width)
t14 (setup) ta (setup).
ti, (pulse width)
tis (setup)·
~' {data ho.Id)
Signals
Reference·
D/F<7:0>HtoID
5-CtoRD
S-A to'.R.D
LD to dafa in 20
Minimum Durafton {o_.) 50 10 10 90 . 20
. 40'
20
10 40::. 45 ... 15
Confidential md·Proprietai-y
4-251
--------
-
Tuning Input Signal Reference ·~Transition)
i.bt. 6·DC()06 ~~pagatic,n DelaY
Output Signal (Ttansition)*.·
Test Condition
ti
S-C (H-L)
S-A (H-L)
t,
S-C (H-L)
S-A (H-L)
t.
RD (L-H)
t,
RD (H-L)
t10
CLK-C (H-L)
tu
CLK-C (L-H)
t.,
CLKcA(L-H)
tu
CLK-C (H-L)
t11
CLK,A(H-L)
t20
a:K-'A (H-L)
t12
RD-A (L-H)
tn
RD-A (H-L)
*Z =high impedance
D/F<7:0> (X-L)
D/F<7:0> (X-L) ·
D/F<7:0>-(Z) (Z)-D/F<7:0> MAX-C (L-H) MAX-C (L-H) MAX-A (L-H) MAX-C (L-H) · D/F2 (L-H) MAX-A(H-L) D/F<7:0> (Z-L)
(Z-H) D/F<7:0> (L-Z)
(H-Z)
Load A RD-A=0.4 V (C counter)
Load A RD-A=0.4 V (A counter)
Load A
Load A
Load A
LoadB
LoadB
LoadB
Load A
LoadB Load A Load A Load A Load A
00006' ~ '
' '"
Propagatioo Delay(ns) ,. Min. Max.
15 80
15 80
10 30 34 80 18 55 10 .35 10 35
10 35
18 55 10 ·35 10 30 10 30 8 25 8 25
4-252
Confidential and Propr~tary
TEST POINT
Vee
FROM OUTPUT
50 pf
ALL DIODES
F0700
DC006
TEST _POINT
FROM OUTPUT
Vee
f200 n
S1
50 pf
All
1K
DIODES
F0700
S2
LOAD A TTL OUTPUT CIRCUIT
OUTPUT CONTROL (LOW-LEVEL ENABLING)
LOAD B THREE STATE CIRCUIT
-----3V
-I~- 1
WAVEFORM 1 _ _....._ _z_L..... (SEE NOTE 1}
_ _ 4 _5 V
S1 CLOSED
Jo"~"
S1 OPEN
1.3V
WAVEFORM 2
S2 CLOSED
(SEE NOTE 2} _ _ _ _ __,_ - - - 0 V
'---1.sv
S1 AND S2 CLOSED
NOTE
1 WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW EXCEPT WHEN DISABLED BY THE OUTPUT CONTROL.
2. WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH EXCEPT WHEN DISABLED BY OUTPUT CONTROL
Figure 5 · DCOOJ Output Load Circuits
Confidential and Proprietary
4-253
· Used with the DC006 to implement a direct memory access interface.
· Contains logic to request and gain control of the Q-bus.
· Allows four-word or multiple-word transfers.
cUtect · Contains bus receivers and drivers for
connectio~ tothe computer bus.
· Uses external free-running clock an<lfaternally generafe'S.eooble and disable clock controls.
· Description
The DC010 direct memory access (D¥t\), 1=Qntained in a20.pl,p. dual-inline package (DIP), is a low-
power Schottky device used prilll;aJj].y .in a DMA .device i.ilterface to perform the handshake operations required to request and pin !control of the Q-b,us. Once bus mastership has been
established, the OCOlO generates the required signals to perform a data-in (DATI) transfer, data-out
(DA1D) transfer, or a data-in/data-out (DATIO) transfer as selected by the control lines to the DCOlO. Four words or multiple words ~n be trans:fened befo~ ·control of the bus is relinquished. Figure 1 is a simplified diagram of the logic contained on the DCOlO chip. The signals in
parenthesis connect internally.
!END C'f~~~~--:::--.i......:=..:=~::f
{INIT tlll-
Figure 1 · DC010Simplified fogic Diagram
4-255
00010
· Pin and Signal Deserlptions
This section provides a brief description of the input and output signals. and power and ground connections of the DCOlO 20-pin DIP. The pin assignments are identified in Figure 2 and the summarized in Table 1.
REQ
5ATiO i5Ariiii Ai:iREN
DOUT
DIN
TSYNC
B5MGO
MASTER
GND
Vee
iiiiii'
OATEN CLK
CNT4 RPLY TM OUT BDMGI
ASYNC
BDMR
TOP VIEW
Figure 2 · DC010 Pin Assignments
Pin Signal 1 REQ
13 BDMGI
16 CNT4
14 TMOUT
Table 1 · DCOlO Pin and Signal Summary
Input/Output Definition/Function
input1
Request-A high level initiates a bus request. A low level allows the termination of bus mastership to occur.
input2 input' input'·'
DMA grant input-A low level allows bus mastership to be established if a bus request on the REQ line is pending. This signal is delayed and becomes the BDMGO output if not a low level.
Count four input--A high level allows a maximum of four
transfers to occur before bus mastership is relinquished. A low level allows unlimited transfers to occur when the REQ line is a high level. If the input is not connected, it assumes a high state.
Timeout-A low when the MASTER ENA signal is high. A highimpedance when .the output MASTER ENB signal is low. When driven low, it prevents the assertion of the BDMR signal. When driven high, it allows the assertion of the BDMR signal if the BDMR signal has been negated because of a four-maximum transfer condition. A resistor and capacitor network can be connected to this pin to delay the assertion of the BDMR signal.
4-256
Confidential and Proprietary
-
· 1~ ..·".·...":.· .- · . ····.
InpQt/Output Definition/Function
Data-in-Used with the DATIO si~ tQ se;l~ the fype,:0£
transfer as specified in Table 3.
·· ·
,
2 DATIO input1 12 RSYNC input1
Dat.a-in/Dat.a-out-Used with the DATIN signal to select the
type of transfer as specified in Table 3. H the input is not connected. itassumes a W&h. state,
· Rece1~ syrl~n~~'¥&.®vi~e to become bus master
· lie~ to the relationsliip!Oi.thd<tllowing signals.
RSYNC+l,lPtY-f.NfASTER,,ENA..;MAsTER
17 CLK
15 RPLY
input, . input'
Rij>Jy--:-Enapl~s or ~all:l~ ~ clcx:k. signal and allows the
derici! to become bus master 11<:cording to the relationship of the
fRoSllY~N·lC· g+:sR.·P·n·Ui·rls+:MA· ST'ER ENA= MASTER
19 INIT
input1
Initialize-Used to initialize thelogic so that the REQ signal will start a bus request transaction. A low level negates the BDMR,
MASTER, i'5ATEf.l, ADREN,.RSYNC, DIN, aJ)d.DO\.!T si~nals.
DMA request~A low level indi4$tes that the de"Vice 1;·~~stlng
·bm·mastt;rsOiP:M~ybe·~~dJ.rectlyt'otheQ~ow,
9 MASTER output'
sequence is in progress.
8 BOMGO output'
7 TSYNC output1
18 i5ATEN output'
4 ADREN output'
n a :, P:M,A.sll!nt.H.J,IJP~.t;oo-1( qo,
, is,~~· rl:lis sigi;ialis .the
,r
<-i~e<iP9~~t,~ft}1e.: pending, this signal is not
·..·. , .~J>µ{JR~ 13)~
asserted. May~ C9nnected
#d~irq¥\UleYs:titos
... theQ.bus.
· ' ' ' · ·· "
Transmit.syru::hronize_,,assel'tC!a.bY: the device .tri.indii:it'e.that.·a
transferis .in progress.
Data enable-Asserted to indicate that data may be transferred
to the bus.
A~ss e~~.le;~,.As~rt# transferred'to.the bus. · ·
·to·
~~~ · ··
J:h,·ala·ii
ad· dr,Ci;s
~af ·.
be
6 DIN
5 ·nouT
output' output'
20 Vee
input
10 GND
input
'TTL level 2high-impedance >open-collector
Data in-Asserted to indicate ~;th.e bus.· mJIStel.'dev~ can aceeptdata;
Data' ti:Jit:..:_.A:iJSei:ted fd ilidita'te~lliat:ilie'bU& m11:ster device has
ttansfened data to.the bus,
Voltage-.Pow~ supply de volta.ge
Ground-Common ground connection
-
Functional Description TheDATIN and DATIO are TTL. input levels that select the type of DMA transfer that will occur. Table 2 lists the inpudevels and the transfer selected.
Table 2 · DC010 Transfer Selection
Inputs Levels* .
DATIN
DATIO
x
L
li:ans:fer Type DATIO
L
H
DATI
H
H
DATO
*L=TTLlow, H=TTLhigh, X=TTLlowor high
· Application Information
Refer to the Chipkit Users Manuall,$1-11 Bus Interface Chips (document no. EJ-01387-92) for general
application information. The Q-bus is an LSI-11 bus.
· Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DCOlO are
described in the following paragraphs.· The test conditions fot the electrical values are as follows
unless specified otherwise.
.
· Operating temperature (TA): 0°C to 70°C
· Supply voltage (Vcd: 5.0 V ± 5%
Mechanical Configuration The physical dimensions of the DCOlO 20-pin DIP are contained in Appendix E. The materials and construction of the DIP are defined in Digital Specification A-PS-1900002"GS.
Ahsolu~ Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may adversely affect the
reliability of the device.
·
· Supply voltage (Vee): 7.0 V
· Input voltage (V1): 5.5 V
· Operating temperature (TA): 0°C to 70°C (32°F to 158°F)
· Storage temperature (Ts): -65°C to 150°C (-149°F to 302°F)
4·258
Confidential and Proprietary
· Supply voltage (Vcc): 4.75 V (minimum),5.0 V (normal), 5,25 V (maximum) · Supply current (kc): 160 mA (maximum) · Free~air temperature: 0°C to 70°C. (32 F to 158°F) · Relative humidity: 10% to 95% (noncondensing)
de Electrical Cbaracteristks
The de electrical parameters of the OCOlO for the operating voltage and temperature nmges
specified are listed in Table 3. Refer to Appendix C for the test circuit configurations ref~ed in
the table.
Pmameter
High-level
input voltage
Low-level
input: voltage
Inputoamp voltage
HigMevel
outputvoltage
Law-level
output voltage
Input current at maximum input voltage
High-level
input current
Low-level
input current
Symbol Test Condition
Vcc=4.75 Vcc=5.25
V~=4.75
vcc==s.2:5
.
,[
V~"';'Optm
I1·~-l8ma.
vc;t ...4.75 .f-0... -1!0 mA
V~=4'.7'5v
Io=8mA Io=70mA
Vcc=5.25 V V1 =5.5 V
Requirements
Units
Min Max
2.0
v·
1.53 1.7()
·W-'
v1
. o.a V1' f
t3o· V?"
' iA1 . 'fo.i
-1.2 v·.2.>
Test
Circuit Cl,C2
t1,c2
C3
'6.5 y1
0:8 'V),4
1.0 mA' 1.5 mA·
·c2 :j
C4
Im
Vcc=5.25Vs
V1=2.7 V
V1 =2.7V'
V1=3.8 V
v.=3.s v
I1L
Vr=0.5 V'
Vcc=5.25 V
Vcc=5.25V
Vcc=0-5.25 V
Vcc=0-5.25 V
C4
50
µA
300
µA
40
µA2
65
µA'
C5
-1.4 mA
-2.0 mA
-10
µA2
-10
µA)
Confid~ ;m,d ProprietlW
4-,259
-
00010
Parameter Output leakage
Symbol
IoH
Test GOnditlon
Vcc==4.75 V Vo=5.25V
Requireln~I§ ··· ·
Min Max
25
lJnits·
µA4
Test
Circuit
Cl
Short-circuit
los
output current .
Vcc=5.25V7
-1.5
-60
mA1 C6
Supply current
lee
Vcc=5.25 V
125
160
mA
C7
1TILinput'·
2high-impedance input
>high-impedance (Schmidt) input, open-collector output
·open-collector output
'except pin 16 and pin 2
6pin 16 and pin 2
7Not more than one output shall be short circuited at a tim,~ a11d the duration of the short must not
exceed 1 serond.
·. '
ac Electrical Characteristics The input and output signal timing for the DCOlO is shown in Figures 3 through 7. The setup time, pul5e-widths, and switching characteristics referenced in the timing diagtatns are listed in Table 4. Tuble 5 lists the signal propagation delays also referenced in the, timing diagrams. Figure 8 shows
the load circuits used for measuring for the open-collector and TTL outputs. Refer to Appendix D for the input and output voltage waveforms used for measuring the signal propagation delays.
Figure 3 shows the signal timing required for the DMA bus-request and bus-grant logic. Figure 4
shows the signal timing required for one data-in (DIN)transfer to the DMA interface. The signal
timing required for one data-out transfer is shown in Figure 5. Figure 6 s.hows the signal timing
required for multiple-data transfers in and out of the DMA interface. The signal timing for the
timeout sequence is shown in Figure 7. The values of the resistor (Rx) and capacitor (Cx) used in
the timeout circuit shown in Figure 9 are selected for the proper delay for the next DMA request
from the interface. The delay circuit connects to pin 14 (TMOUT).
·
4-260
Confidential and Proprietary
CLK
RSYNC
RPLY
I
I
REO _ _ _ _ _,.;-_...__.._._~I t
I 1......-.-=ta~
I
BOMR ---,---,-------.1---tt1st"- I
I~1~1-~I_ _ _ _ _ __ II I
r - B
O
--......-....;~...... t2
M G · l....__
_, _
_ _.1
1
I
1+--ts-·--t1...._
_
_
I-,...___ _~ I 1_···_: ........
_
_
_ _
BDMGO
~l'."':"-t3...
.____!..I. . ..
t.--I.
I
t1-I : I
*TMOUT MASTER
II ,'.
I I
I I
l
14-- I
I
136 ..;;_;._;1.,..1'llil;:Ji-·"":"1- , - - - - -
ADREN ---,---~----------~l__....,.______......_...._!_-_-_i1...·..·.~f=-t1_1_____
- U --it1!_4_- ______________,_:_________~--~----~~-----~---
iNiT
I
., .- - - - - - - t 4
..,
*WITH NO RC NETWORK CONNECTED
Figure J ~ DCOlO DMA Bus Request and Grant Signal Timing Sequence
Confidential and Proprieta,ry
4-261
CLK REQ
I
I
I I
115-I-H-
I
I
I I
I
1 I
r-II
t20-:
TSYNC
I 1
I~i--.-l11~7 tI I-1I9,-,-i---~--,,I.____,..___
DIN
I
I
1
J"I
.
I
1'*1,...[·
-1_24_
_~,.~......,1.l..,.__
__._1- - - - I
APLY (END
I
I
.~~~~-IJ
-I l-11a
1-1 .---~~~1~~~--
-I l-124 I ,-,
CYGLEl--..:..1___,_ _,_I_ _ _ _ _+l------fl,___---+-'II !.__ __
---"''_::;i_, t22 f4.-
i
DATIN
I I
I
I
..,_~!~~~~~~-~~~~~~~~-..:.,~-~-~
I
I
I
I
PARENTHESES= INTERNAL SIGNAL FOR REFERENCE ONLY
Figure 4 · DC010 One Data-in Transfer Signal Timing Sequence
4-262
Confidential and Proprietary
CLK
D~TIN _JI
: f
, . -1, 1tt22
OAriO_JI
I» I
i I
-J -lrt1sj REQ
I
1-t11 1
APRE~I
l . ...
I - t,5...,
'
I
!" I
1 I
l
I.
I >j f
IH I
i
t
., t
» I
_..,: f--t33
~!1+.-.t..2110. 1-
! :
lI r
T::::
______'_·__!t_23_...,_:r.i
· .
.
.
L
t2~~c._J _
_
_
::'~~~~~~~~:-
_
i J . RPLY ·_ _ _ _ _ _ _ __._!____1,1 -i r;-t~4
l ~·1'".
i,.;.!......;.._ _ _ _ _ _ _ __
j - l r.-· -------""'t.26.....-.-1.-.--i.
t1a
DATEN
. _
ft
rt
CNT4
t1a-; t--.·.. ·-------!:": « l ( ..
IF-I . t27
j . ' . . ' ..
MASTER NOTE: t27 OCCURS ONi; CLOCK CYCLE AFTER NEGATION OF POUT
Figure 5 · DC010 Data-out Transfer Signal Timing Sequence
. Confid~ial and Proprietary '
'4~263
lBllll
DCoto
CLK ~Jl-Il-11{Ln0-11~
DATiO ::i 1- t22 1 ' · 1
I
l II
REQ
I
-J i- tn
I
I
I
trn--t
f.-
I I
ADREN·~ I
1 ~m I
I l I -I l-t29
I l II I I
I ~
, ff 1 . .
I ff I
I I
I I 1. I
, "' 1· , 1 It I · I I
I II I II I II
DATEN
I. I I I .. I I
I
1
~It31
I 1 >
1t27'--f I- I I ,,...-,--
t1s-jl- I» I
I >>-4
1,
1.,
I I
!; TSYNC _ _ _ ____,I I I t17j I
.. I I .
t19-jf-I
I
I
t20--1l:--
I
I
1
J DIN
------!~
-l f
j - t24 -t1s
RPLY
-------
~~
~
t.n
I f
lj
I
J ~ 1--1 1+-t24 1 I
I
I
-l~t215-- t24
DOUT ----~~~~---1;'"-----~--t--1.~·--~~~-3_-l~~
~,.._~---
NOTE: t27 OCCURS ONE CLOCK CYCLE AFTER NEGATION OF DOUT
Figure 6 · DCOlO Multiple Data-in/Data-out Transfers Signal Timing Sequence
4-264
Confidential and Proprietary
...
END OF 4TH TRANSFER
CLK
REQ
I
{END CYCLE~l--------·-'-·'·--"------------
F . {MASTERENAH) t21-t1
f
J i,,__t3-5~:--~-:+;,,:r=~· »
·
1,..·""'i~"-'.,..·_,,_,_ _ _ _ _ _ _ _ __
I_
...
TM OUT -------RcOELAY
' \ .l11H
..1...- - - - - - - - - - '(·c
CLK
REQ
CNT4 (ENO l) MAsTER
LJ
-- TM OUT -------RCOELAY
PARENTHESES· INTERNAL SIGNAL FOR REFERENCE ONLY
Figure 7 · DC010 Timeout Signal Timing Sequence
-·
Tune Refe~ce t1 (pulse width) t. (setup) t6 (setup) t 9 (setup) t 12 (pulse width) t 11 (pulse width) ti· (setup) t,8 (setup) t22 (setup)
t2s (setup) t,. (pulse width) t30 (setup) tu (pulse width)
DC010
Table 4 · DCOlO Pulse Widths and Setup Times
Signals
Reference
MDuinmimtiounni(ns)
35
INIT toREQ
25
. BDMR to J;3DMGI
35 .
BDMR to BDMGf
0
CLK (low)
60
CLK (high)
60
RE'.QtoCLK
35
DINtoRPLY
0
60
RPLY.tnCLK
30.
RPLY to DATIO
35
30(1 clock period maximum)
65
REQ
35
Confidential and Proprietary
...
Dr.Iii·
Tuning Input Signal Reference (TransitiOn)
Table'S · DC010 Signal Propagation Ddays
Output Signal (Transition)
Test Condition1·2
Propagation Delay (ns)
Min. Max.
t,
BDMGI (H;JX
BDMGO(H-L)
· Loru:FA:
95
220
;''· ·,
t,
BDMGI (L:H).
BDMGO(L-H)
Load1A·
15
60
t,
REQ(L-H)
BDMR(H-L)
Load Ai
25
70
~
t,
BDMGI(H-L)
TMOUT(H-L)
LoadA
85
230
ta
BDMGI (H-L)
tu2
CLK (H-L)
BDMR(L-H)
Load A
117
306
4-D~f\'4 (J,.;l;ll,.
~adB , .. · 15
60
tu
CLK (H-L)
t"
CLK (H-L)
t17
CLK (H-L)
ti.
CIJ{ (H-L)
TSYNC (L-H)
LoadB
18
601
ADREN(H-L)
LoadB
20
65l
DIN (L-H)
LoadB
18
6(}l
DiN (H-L)
LoadB
18
60
tao
CLK (H-L)
TSYNC (H-L)
LoadB
18
60
t21
CLK (H-L)
t2,
CLK (H-L)
t2,
CLK (H-L)
TMOUT(L-H)
LoadB
30
90
DOUT(L-H) ··
LoadB
60
175
...
DOUT(H-L)
LoadB
20
65'
t,6
CLK (H-L)
DATEN (H-L)
LoadB
20
65'
t21
CLK (H-L)
t31
RPLY (H-L)
tH2
CLK (H-L)
DA,TEN (L-H)
i.5A'fEN (H-L)
LoadB
20
65'
( '
LoadB
20
65
ADREN (L-H)
LoadB
18
60
t"
TMOUT(L-H)
BDMR (H-L)
LoadB
20
75
t}6
BDMGI (H-L)
MASTER (L-H)
LoadB
90.
242
tn
CLK(H-L)
MASTER (H-L)
LoadB
18
66
tn
RSYNC (HcL)
MASTER (L-H)
LoadB
10
58
1See Figure 8 for output load circuit configurations.
2t11 represents the first time ADREN is asserted. t,, represents the subsequent assertion of ADREN.
'These propagation delays meet the following requirements:
t 1s to t 16 ::::; 10 ns
tu to t 27 S 20 ns
t 1s to t 17 S 10 ns tn to t,6 S40 ns
t 16 to tu; :S 10 ns t, to t}6 S27 ns
4~267
. ._.- - - - - -~.---·----~---&_
-
<·:; ·:~
'"o"o"''~j' :··.·Vee
600
TEST
T15pf ·
· POINT
TEST POINT: Vee
ALL DIODES FD7!JD ·
LOAD A OPEN-COLLECTOR Cl RCUIT
LOAD B TTL CIRCUIT
Figure 8 · DCOlO Output Load Circuits
vcc
fRx
..t:TMOUT
rcx
Figure 9 · DCOlO Timeout Delay Circuit
4-268
· Provides the logic to request and gain control of the UNIBUS
· Used to arbitrate for DMA or interrupt mastership
· Bus receivers and drivers compatible with UNIBUS
· Used to devdop UNIBUS interfaces for ~riph~ devices
· Description
The DC013 is a 16-pin, dual-inline packagi;; (DIP) used in the~lopment of device interfaces for the UNIBUS. It contains the logic required to perform interrupt bus requests (BR) and nonproces-
sor direct memory access (DMA) requests to gain controlcof~UNIBUS.
are Input signals from the UNIBUS recei~ by high-impedan8e tectivers on the DC013 and signals
from the DC013 to the UNIBUS are supplied by high~~nt, open-collector driver outputs. The
signals levels between the UNIBUS and the DC0!.3 ak compatible. The input and output signals
between the device and DC013 are TTL levels. The DC013 circuits includes bus grant logic, bus busy logic, and slave acknowledge logic. The simplified logic diagram of the DC013 is shown in Figure 1.
Figure 1 ·DC013 Simplified Logic Diagram Confidential and Proprietary
4-269
·:Pin and Sp ~$11\S
The input and output pins and power and ground connections of the DC013 are shown in Figure 2. Table 1 provides a summary of the signals defined in the following paragraphs.
REQUEST BUSSSYN STEAL GRANT SUSNPR BUS BG/NPG IN BUS BG/NPG OUT 6 BUS SACK
GND
TOP VIEW
Vee
CLR SACK ENB MASTER CLR INIT SACK MASTER BUS BBSY BUS BA/NPR
Figure 2 · DC013 Pin Assignments
Pin Signal
Table 1 · DCOl.3 Pin and Signal Summary Input/Output Definition/Function
1 REQUEST
input'
Request-Asserted to request that the DC013 begin arbitrating for mastership ofthe UNIBUS.
2
BUS SSYN
input1
Bus slave synchronization-Asserted by the UNIBUS slave to indicate that it has completed the operation requested by the master device.
3 STEAL GRANT· input2
Steal grant-Used only when the DC013 is permitted to win bus mastership.
4 BUSNPR
inpue
5
BUS BG/NPG IN input>
Bus nonprocessor request-Used only when the DC013 is allowed to win bus mastership and the Steal G~nt feature is enabled.
Bus grant/nonprocessor grant in-Provides the appropriate UNIBUS grant signal to the DC013.
6
BUS BG/NPG OUT output'
Bus grant/nonprocessor grant out-Transfers the appropriate grant signal from the DC013 to the repi.aining devices on the UNIBUS.
7 BUS SACK
8
GND
output' input
Bus sele.ction acknowledge-Indicates to the UNIBUS arbitrator thllt the DC013 acknowledges its selection as the next master of thi; UNIBUS.
Ground-Common ground connection.
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Pin
9 .bus BR/Nl?R
10 BUS·BBSY
11 MASTER 12 SACK
13 INIT 14 MASTERCtR 15 CLRSACKENB
·.motJ
Input/Output outpue
Defmition/FunctiOn
~us request/nonprocessor reguest out~I~te;;
by . that the DC013 has. heen requestfd the
RE-Ofi1*~~ intnit signal ttj arbitrate for ml\Stershlp of
theul\a~ys. ·
·
· ·
input'/01.1-tput3
Bus busy1T1,f\.~ .an ipput1 it ifn£q~ms the DCOl,l~th~'
the gm:ertj;, ;mas~ has completed its use. t)f the UNIBU$..A,s. ~ Ol;l:tP\lt> it allows the D;C!lU,to
indicate that (t~ b«:c::nroe the cutrent hu,s 1113S~·
output1 output1
Master-Asserted when the DC013 is the current .~us ~ster an~.~~.l\Ssert~g th,e BU~ B~W'.~]f3L · .
Sdection acknowleclge-Asserted when,.t1le.neel3 js ~s~erting tliqi~f.~St{ signal to 11eknowl~ \ts selection as '·'· . ~~.of the bus.. . : ·
input1 input1 ··
input1
M~\'.er···ciear..::.:Asserted to alloW 'tlle susrssYN
input to clear the'DCon. ' '
['"
·'
·"
16 Vee
input
1P'Llevd
2Wgh~irnpedance UNIBUS input
3open<-0llector UNIBVS output
UNIBUS Signals
BUS SSYN-Asserted by the UNIBUS slave to indicate that it·ha& completed .the opetl\tion reqested by the master device. When the 0Cfll3ni$ used 'to win interrupt n1astershipj this input
signal indicates that the processor has accepted~ ~qterru{?ty.ectpr an&$1Q'>VS the p<:Qp to ~~aire
the bus. When the DC013 is used to win DMA mastership, this input may be directly connected to
the UNIBUS or to other logic within the master device.
STEAL GRANT-When the DC013 i.s used to win interrupt mastership, .ws:input:signfd :aliowsill
to steal and reply to an inte~p~ grant ip.tepdedfor !lnother devi~e, connecte.d to the UNIBUS. This
feature can reduce the civ~ DMAlatency. · ·
· · ··
· ·
BUS NPR7""'"When the steal gi:ant fea~ is enabled @d the pcp13 requests interrupt lllaster:ship,
thh> input informs the DC013 that a. DMA <Jevice is requestingus~ of the bus.
·. ·' .
BQ~ BG/ffalG JN.,...When the DC013. requ~ts i~tei:rupt ·~~~rship, this ~put connects to the
appropriate BUS BG7 through BUS BG4 input. When requestingDMA mastership, it coqn~s t;o
the BUS NPG input.
BUS BG/NPG OUT-When the DC031 requests interrupt mastership, this output connects to the appropriate BUS BG7 through BUS BG4 output. When the DC013 requests DMA mastership, it connects to BUS NPG output.
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0C013
BUS SACK-This output indicates ~P the. UN.BUS arbit~tO! that.the DC013 acknowledges its
selection as the next master of the UNIBUS.
BUS BR/NPlt-This output indicates that the DC013 has been requested by the REQUEST input
to arbitrate for mastership of the UNIBUS. If the DC013 is requesting interrupt mastership, this output connects to the appropriate UNIBUS line BOS BR7 through BUS BR4 output. If the DC013
requests DMA mastership, the output connects to the UNI.aUS BUS NPR line.
BUS BBSY-After the DC013 has been granted next bus mastership, it must wait for the current master to complete its data transfers. This input informs the DC013 that the current master has completed its use of the UNIBUS and provides an output from the DC013 to indicate that it has become the current master of the UNIBUS.
Device Signals
.. . .
REQUEST-An input from the device to request that the DC013 begin arbitrating for mastership
of the UNIBUS.
MASrtit-This output is asserted when the DC013 is asserting the BUS BBSY signal indicating that the PC013 is the C1,ll"rent master of the UNIBUS. If the DC013 is requesting interrupt mastership, this output indicates that the interrupt vector from the device should be transferred to the UNlf,mS data lines. If the DC013 is requesting DMA mastership, the output is used to trigger tha data transfer logic of the master device.
SACK-This output is asserted when the DC013 is asserting the BUS SACK output to acknowledge its selection as the next bus master.
INIT-This input initializes the logic in the DC013 to end the bus cycle initiated by the DC013.
MASTER CLR-This input allows the BUS SSYN input to clear the DC013 logic. The use of this input is optional when the DC013 is used for DMA transfers.
I
-:=C,,,.L""'R""'SA:-:-;,C""K""'E="N~B""'-This input causes the the DC013 to deassert the BUS SACK output if the DC013 is
also asserting the BUS BBSY output. It allows UNIBUS arbitration to resume when the. DC013 becomes bus master. When the DC013 is requesting DMA mastership, this output may be used to delay UNIBUS arbitration during multiple data cycles. During the last data cycle, the the master logic should assert the CLR SACK ENB input to the DC031 to allow the arbitration to be resumed.
Power and Ground Connections Supply voltage (Vee): Connects to the 5-Vdc power supply
Ground (GND): Common signal and voltage ground
· Functional Operation
The followmg descriptions assume that the reader has a knowledge of the operation of the
UNIBUS. Refer to the PDP-11 UNIBUS Processor Handbook PDP-11/84, PDP-11/44, and PDP-11/24 (Digital document no. EB 26077-41) for a more detailed description of the UNIBUS operation.
Typical UNIBUS interface implementation of the DC013 for interrupt and DMA data transfers is shown in Figure 3. Request and grant signals that are not used are wired through the interface and can be used by subsequent devices.
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-
UNIBUS
AflBtTRATOR
·TOOTtiER· DEVICES
Thesignalsdesignatioqs;~owninmeJX:91J~ntr#tlo~crigitf~1;~t:~~~ededbya''l3US"
qan d~signatiqn cor,in~ tn· d~e UNIBUS, lfu~./Ihe~~013 contilins ):'l;i~ 'co~ttol l9gk reqUired ~~t 'a
deVice to he!:on}~bus ~tef.. A. bus m~t~t feq~~t ahd gai~ c~nftbl of tlle.UNtBUS to tmri~er. ·
interrupt ·~ctors ~r datk. · " · ·
· . . ..·· · .. · · ·. ·· . · · ·· · :· ·
.
The two o/PCS :9f ~uests .~ba~ can.~ ~~~~ ~the .in~rru t~~s ~~u~t (B~),apd ~
memory ace~. (D~} no~pip~sQt requ~st .(~): ·/\. ~~. t .~s use ?r tfie bU$ .· to
a.· .· .·. transferdata
m BR results
Oa~p\rroeccteostsso+rhirnotelr1r~uap,tp'ainndtetrh1e:1rle?qt~uteisatj,CgS nai~nRt,
tainjc'l~c~lat~"t'taiWuifteirllc.aoCnsPtUirubttriciOinniltrittjelrleriurp.j\t
transaction. Only one interrupt transaction may be executed under a single grant.
The NPR is assigned the highest priority and solicits the use of the data section of the bus to
transfer data between a device and memory without active participation of tliif'processbt:A'.8f.iiVice
that.requests the use oft.be bus-sen~ an Nl?Roto the atl?itrator in.the CPU wben.the device is re.ady
to transfer data.
·
The assertion of the REQUEST input initiates a priority tran&fer sequence and is awJied to theD
input of the Take Grant flip-flop. This flip-flop ensures that only one priority transfer sequence is
initiated for each REQUEST input. If the requesting device is not presently bus °'aster, ~ BBSY
flip·ilip is .not ·set. For each request;the·'REQWS'f.signal'!7!li1Sl: be ·~ated and again asserted
before another cycle can begin;
The state ofthe Bm t3BSY signal determmes~~et the receiy~'b~s ~tsigiiaI (BUS BG/NPG
IN) is tran~ferresl to'the tiext'qe\ttce or is ~eep~'l>Sr the ~ix~ijng demee: ff BUS BBSY is not
asserted, the logic acrepts the gt'aht. Ifjms ~1fs:*J,.s5erted,' th'e:~t is pasiecho another device
of the same priority le\.el.
' ·
· .. .
"··'
.
The BUS BG/NPG IN signal clocks the Thke Grant and Steal Grant flip-flops. With the REQUEST input asserted, the Take Grant flip-flop is set or if another device is asserting the BUS NPR input and the STEAL GRANT input is asserted, the Steal Grant flip-flop is set. Either flip-flop when set disables the bus grant driver and negates the BUS BG/NPG OUT signal. When the grant is accepted, the SACK flip-flop is set after the 75 ns delay from D2. The delay D2 ensures that the Tuke Grant and Steal Grant flip-flops have time to respond to the BUS BG{NPG IN signal before
the SACK flip-flop is clocked. When the Sack flip-flop is set, the BUS SACK output is asserted and the arbitrator is allowed to negate the grant after aminimum of 75 ns and the bus request signal BUS BR/NPR is negated. The BBSY flip-flop is set when the clock input conditions have been satisfied. This occurs when the Tuke Grant and Sack flip-flops are set and the BUS BG/NPG IN, BUS SYNC, and BUS '$BSY signals are negated.
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data The BUS BBSY and MASTER sigrials are then a,sserted. The BUS BBS~(signal holds the bus for the
master to perform the and/or interrupt\lectortr:µisfers. The MASTER signal may be used by
the master to initiate a data transfer or an interrupt. sequence. It may also be used to enable the
appropriate data or interrupt lines.
When the requesting device completes the transfer; it asserts the MASTER CLR input. When the MASTER CLR and BUS SSYN signals are asserted to indicate that the transfer is complete, the BBSY flip-flop is reset. This negates theMASTERoutput and after a delay of 80 ns from D4, the BUS BBSY output is negated.
Delay D3 ensures that the external bus interrupt that is driven by the MASTER output is asserted
before the SACK flip"flop is cleared. The SACK flip-flop may be reset when the bus grant on the BUS BG/NPG IN input is negated.
Asserting the INIT input clears the BBSY flip-flop if the bus grant signal BUS BG/NPG input is negated.
A ·dt;!Vice not requesting the QUS may assert the STEAL GRANT input to improve NPR latency. It
then receives an BUS NPR input followed by a bus grant signal BUS NPG IN. It blocks the bus grant
intended fora another device and asserts the BUS SACK signal that causes the arbitrator to negate
the bus grant signal and stop the arbitration. The n~gation of the BUS BG/NPG IN signal resets the
SACK flip-flop.
.
A 9.eviceclose~ fo the arbitrator may assert a BUS NPR signal before a grant is issued to a device that
previously made a bus request. The arbitrator first honors the.NPR and issues an NPG. When the
NPR device has completed its transaction, the arbitrator issues a bus grant to the original device.
· Interfadng Techniques
The DC013 control logic is used to develop device ·interfaces .to generate bus interrupt and nonprocessor request. The following paragraphs describe the use of the DC013 and standard circuits for typical interface applications.
Bus Request Logic
A typical BR UNIBUS interface usingthe DC013.and standard ICs for the bus drivers and receivers
is shown in Figure 4. This circuit generates one interrupt vector address and transfers the address and data to the UNIBUS. The 8641 ICs can be repla,ced with two DC021 Octal Bus Transceivers. The interrupt vector from the 74157 ICs is multiplexed with the data lines from the device. The address is selected by inserting and. removing jumper leads (V2 through V8). Multipleiing the inputs before the bus drivers reduces the total UNIBUS loading of the device.
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SIU'f&
INTENI tGOUT
i\if""' m-
iiJi iNt
"""au ·UtStOll'S 10·
t ·· "UlllL£5'.S OT~llfllr1Sf IWQtU;:
...,..
""SAC·
O<:Oll lllUT
SENOOATA. ltl S£NOC·1A 1· stNO t>AlA. 13 Sl'fDO·tA 11
'·- '$Ei.Q~D.At.J. 11 stir.oDua.·to
( sewtfUA1AOI SUU)_~,"if~OO :-,
...
Figure 4 · DCQBTypicaUlitinteefac(I Cireuit
.... . .,.. ,,
tusc
.., , IUSD
..,.. .
" suse
'"''
11</$0 i~lil
DGtll
ii.i$OiS
~
ram
iU!DT!
iUSOiT
iiUiOiQ ~ iQSi)&;
~
....
MOii
iUiDii
MOOi
iiiiiiii
fN9J
... ,
;;;soo;
MOiO
~
... ,
M1ii:i
iuiSACK
IU~l'lfo ~
AbustequestisinitiatWbyadevicewhenan.interruptisrequired.TheINTENBsignal~norn;uilly
produced by a bit in the rontrol and status · of.the device;, ~ntbe INT ENB,and the ~NT
inputs from the detrice are asse~i:{the ·
· input ~<~l)e,~13 is. assert«! to irlitfate a
priority transfer sequence on the UNIBUS. When the device reeeives .the grant, the MASTER
output is ~serted a11d·hegin~ tbe iJ:lterruptsequence,.
The master device negates both the SELECT ancHN inputs to disable the UNIBUS tran$ceive£ll for
theD <01:00 > and D < 15:10 > lines.
,
When the SELECT input to the multiplexer is negated, the A· ihpilts ·are transferred to the bus.
When the SELECT input is asserted, the B inputs arettansferred to the bus.
The asSeJ:tion of the MA.STER "output driables the SEL inputs to' the mUl.tiplexers, enables the
outputs ofthe bus transceivers lines BUS D < 09:02> and, aft(!f. ~ay,Jtenables the remaining
input to the ga~e that generates the BUS. :iN'rR output; The intertapt vector is therefore available before the interrupt is :requested that compile$ wfththe·busspecifications. When the processor receives the BUS INTR signal, it reads the vector information on the bci and asserts the lJUS" im'SY
signal. The device receives this signal, deasserts the MASTER output to terminate the vector, and
deasserts the BUS INTR output. After a delay of 80 ns, it deasserts the BUS BBSY output.
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........__,_____,
-----~·!!!lrl
···
Nonprocessor Req~t Logic A typical DC013 UNIIfOS interf~~'circµit for use with a NPR device is shown in Figure 5.
+SV
DC013
UNIBUS
CONTROi,.
LOGIC
NPR
BUS SACK BUSBBSY NPR MASTER
Figure 5 · T>C013 Typical NPR InU:rface Circuit
When an NPR transfer is required, the requesting device asserts the NPR REQ input. The arbitrator recognizes this request and issues a nonprocessor grant by asserting the BUS NPG IN input. The
requesting device blocks the grant from being transferred to the next device interface and
acknowledges the grant by asserting the BUS SACK output. With this signal asserted, the arbitrator negates the grant' and stops the arbitration process. With BUS SACK: asserted, the arbitrator negates the grant and stops arbitrating. When the requesting device receives the negation of the BUS BBSY, BUS SSYN, and BUS NPGsignals, it assetts .the BUS BBSY output, becomes bus master, and initiates the data transfer.
The NPR MASTER output, asserted when the BUS BBSY signal was asserted, is used to drive the
external circuits. When the data transfer is complete, the device negates tlJ.e. NPR REQ input to
relinquish the bus mastership. The NPR REQ input connects to the INIT input (13). Once a request
is initiated, the NPR REQ input must remain asserted until the data transfer is complete to prevent
the premature termination of bus mastership.
~
The Stel!-1 Grani flip·flop is disabled by connecting the""ST=E"'"A'""L,....G=RA.,...,..,N""'.""'T (3) and :SUS NP~ (4) inputs
to 3 V. The BUS NPG inputjs held asserted by the resistor network. The CLR.SACK ENB (15) is
asseyted and the MASTER CLR input is. negater:! by the ground connectiqn that all~ only one bus
cycl~ for each requ~st. Foi: morethan one ~a,~ cycle, the.C~R SACKJ>:Na input c;anbe held negated
tintilthebeginning pf;the last .Qu$ cycle. ·
·
·-· ·
·
Confidential and Proprietary
-
DC013
An interrupt request cannot be performed by a device that has become bus master through an NPR. In most NPR applications, an interrupt request usually follows the completion of a set of NPR transfers. This interrupt may be used to notify the processor that the NPR transfers are complete or that an error has occurred during the data transfet:
Bus Loading Configuration A typical device interface that uses a DC013 for NPR control and a DC013 for BR transfersis shown in Figure 6. The UNIBUS loading for the BUS SACKand BUS BBSY outputs can be reduced by using the wired-OR configurations from theDC013 outputs as shown.
NPRREQUEST BUSNPG IN
DC013
NPR CONTROL LOGIC
BUSNPR BUSNPGOUT
BUS SACK
BUSBBSY NPRMASTER
+5V +5V
8641
BUS SACK
UNIBUS TRANSCEIVERS
BUSBBSY
ENS 1
ENB2
BR REQUEST BUS BG IN
DC013
BR CONTROL LOGIC
BUS BR BUS BR OUT
BUS SACK BUSBSSY
BR MASTER
Figure 6 · DC013 BR and NPR Wiring Configuration
· Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DC013 ~ described in the following paragraphs. The test conditions for the electrical values are as follows unless specified otherwise. · Ambient temperature (TA): 0°C to 70°C · Supply voltage (Vcd: 5.0 V ± 5%
Confidential and· Proprietary
4-277
···
00013
Absolute Maximum Ratings Stresses greater than the absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may adversely affect the
reliability of the device.
· Supply voltage (Vee): 7.0 V
· Input voltage (\'l): 5.5 V
· Ambient temperature rn): 0°C to 70°C
· Storage temperature ('fs): -65°C to 125°C
Recommended Operating Conditions
· Power supply voltage (Vee): 5.0 V ± 5%
· Supply current (led: 140 mA (maximum) · Ambient temperature (TA): 0°C to 70°C · Relative humidity: 10% to 95% (noncondensing)
de Electrical Characteristics The d~ electrical parameters of the DC013 for the operating voltage and temperature ranges specified are listed in Thbles 2 through 4. Thble 2 lists the specifications of the TTI.. input and
output circuits that do not connect to the bus. Table 3 lists the specificatiorts for the highimpedance receivers that connect to the UNIBUS. Thble 4 lists the de specifications for the open-
collector driver outputs that connect to the UNIBUS. Refer to Appendix C for the test circuit
configurations referenced in the tables.
Parameter
High-level input voltage
Low-level input voltage Input damp voltage High·IeveI output voltage Low-level output voltage
pin 11 pin 12
Thble 2 · DC013 TTL Input and Output Parameters (nonbus)
Symbol Vm
Test Condition
Requirements Min. Max.
2.0
Units
v
VIL
0.8 v
V1
Vcc=open
I,=-18 mA
-1.2 v
Von
Vcc=4.7 V
2.7
v
lo=-1.0 mA
VoL
Vcc=4.75 V
I0 =20mA1 !0 =2 mA
0.5 v
v 0.5
Test Circuit Cl,C2
Cl,C2
C3
Cl
C2
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DC013
Parameter
Symbol Test Condition
Requirements
Min. Max.
Units
Test
Circuit
Input current
I1
at maximum
input voltage
Vcc=5.25 V V1=5.5 V
1.0 mA
C3
High-level
Irn
Vcc=5.25 V
C4
input current
V1 =2.7V
pins 13,15 pins 1,14
Low-level
In.
input current
Vcc=5.25V V1=0.5V
50
µA
100
µA
C5
pin 15 pin 1,13,14
-0.55 mA -1.l mA
Short-circuit
los
Vi;c=5.25V2
C6
output current
pin ll pin 12
-40 -100 mA
-5.0
-45 mA
Supply current
Ice
Vcc=5.25 V
140 mA
C7
1Requires a load current of 70 mA at pin 10. 2Not more than one output shall be short circuited at a. time and the duration of the short shall not
exceed 1 second.
Parameter
High-level input voltage
Low-level
input voltage Input clamp voltage High-level input current*
pin 10 pin 10
lable 3 · DC013 High-impedance Bus Receiver Parameters
Symbol Vm
VIL
Vi
Test Condition
Vcc=4.75V Vcc=5.25V Vcc=4.75V
Vcc=5.25 V
Vcc=4.75V
l,=-18mA
Requirements
Min. Max.
Units
1.53
v
1.70
v
1.30 v
· 1.47 ·V
-1.2 v
Im
Vcc=OV
V1=3.8 V
Vcc=5.25 V
40
µA
40
µA
Vcc=OV Vcc=5.25 V
40
µA
65
µA
Test Circuit Cl,C2
Cl,C2
C3
C4
Confidential and Proprietary
4.279
---- ----·-----------·-----·-~·-"---------------------~!
·-
Parameter
Low-level
input current*
Symbol
IIL
pin 10 pin 10 *All pins except pin 10.
Test
Condition
Vcc=OV V,=0 Vcc=5.25 V V1=0
Vcc=OV V1=0.5 V Vcc=5.25 V Vr=0.5V
Requirements Min. Max.
-10 -10
-10 -10
Units µA µA
µA µA
DC013
Test Circuit
C5
Table 4 · DCOU Open-collector Bus Driver Parameters
Parameter
Symbol
Test Condition
Requirements Min. Max.
Units
Output reverse
Iott
current*
Vcc=4.75 V Von=3.5 V
25
µA
pin 10
Low-level
Vo1.
output voltage
Vcc=4.75 V
Link=70.mA I.u.k = 16 rnA
65
µA
v
0.8 v
0.5
*All pins except pin 10.
Test Circuit Cl
C2
ac Electrical Characteristics The input/output signal timing for the UNIBUS request logic is shown in Figure 7. The transient specifications for the signals are listed in Table 5. Refer to Figure 8 for the load circuits used in measuring the TTL outputs and open-collector outputs. Refer to Appendix D for the voltage waveforms used in measuring the propagation delays.
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-_ __,f BUS BG/NPG IN
i.5 v.
.
1.5 v
35nsj (MA)<)
BUS BR/NPFl
INIT BUSBBSY
~__;__.l_ou0_1_,f 1.-5 V
BUSBBSY
Figure 7 · DC013 Signal Timing Sequence
Signal
REQUEST CLRSACKENB MASTERCLR !NIT BUSNPR STEAL GRANT BUS BG/NPG IN B'OSSSYN BUSBBSY
Table 5 · DC013 ac Signal 'Jhmsient Specifications
Input Voltage
Parameters (ns) Rise Time
Fall Time
0 to 3
!11!15
!II! 6
Oto3
::1!!15
!II! 6
Oto3
:!! 15
:I!! 6
Oto3
::1!!15
:I!! 6
1 to2
:!!10
!II! 10
1 to2
:!10
!II! 10
1 to2
!II! 10
:!!10
1 to2
:!! 10
!11!10
1 to2
:!! 10
!II! 10
Confi~p~ .atid. Propriet:l!cy
4-281
Vee
~on FROM
OUTPUT TEST POINT
LOAD A-OPEN-COLLECTOR CIRCUIT
TEST POINT
Vee
R1*
FROM OUTPUT
1--·
ALL DIODES FD777 OR EQUIVALENT
LOAD B-TTL EQUIVALENT CIRCUIT *Rl IS 2aon FOR PIN 11 AND 2Ul FOR PIN 12
Figure 8 · DCOlJOutput Load Circuits
Mechanical Configuration
The physical dimensions of the DC013 20-pin DIP are shown in Appendix E. The materials and construction of tbe DIP are defined in Digital Specification A-PS-210002-GS.
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Confidential and Proprietary
·Features
· Bidirectional bus transceivers
· Incorporates receiver noise immunity
· Input and output levels compatible with UNIBUS and Q-bus
· Provides three-state TTL outputs to interface
· Open-collector bus drivers
· Description
The DC021 is an octal bus transceiver oontained in a 20-pin dual-inline package (DIP) and is compatible with both the UNIBUS and Q~bus. The DC021 provides eight bidirectional channels that transfer information between a wired-OR bus and a user interface. It provides high-impedance receiver inputs and high-current, open-collector dr;iver outputs. The DC021 transfers TTL-level signals between the device logic and the bus. The Sdect and Enable inputs to the DC021 are used to control the direction of information transfer. ·The simplified logic diagram of the DC021 is shown in Figure 1.
ITRANSC'Ei'VER..,.....,
I
--'
CHANNEl..1
ITRANscE'iVE'R 2....,
I
CHANNEl..2
·
· ·
r ···· l"'n~ANs'cEiVER 8" I
·
· ·
CHANNELS
Figure 1 · DC021 Simplified Logic Diagram Confidential ~d Proprietary
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DC021
· Pin and Signal Definitions
This section provides a brief description of the input and output signals and power and ground connections of the DC021 20-pin DIP. The pin assignments are shown in Figure 2 and the signals are summarized in Thble 1.
SELECT
BUS 1
Vee
EN ABIE GHANNEL1 CHANNEL 2 CHANNEL3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 11 CHANNELS
TOP VIEW
Figure 2 · DC021 Pin Assignments
Table 1 · DC021 P"m and Signal Summary
Pin Signal
Input/Output Definition/Function
1
SELECT
input'
Receiver/driver select-A low input enables the driver outputs to the bus wnen the ENABLE input is low. A high input enables the receiver inputs from the bus when the ENABLE input is low.
2-9
BUS 1 to BUS 8 input2/output3 UNIBUS lines-Eight bidirectional line receivers
that connect to the bus.
10
GND
input
Ground-Common ground connection.
11-18 CI-J,ANNEL 8 to input1/output1 Interface channel-Eight bidirectional lines that
CHANNEL I
connect to the device interface.
19 ENABLE
input'
Enable-A low enables the SELECT input to select
the drivers or receivers. A high disables the drivers
and the receiver outputs become high impedance.
20
input
Voltage-Power supply de voltage.
'TTL level
2high-impedance 3open-collector
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Confidential and Proprietary
DC021·
Enable and Select Function
Table 2 lists the function of the transceiver as related to the ENABLE and SELECT control inputs.
Table 2 · DC021 Control Signal Functions
Signal Inputs*
Function
Driver
ENABLE
SELECT
L
TTL-to-bus ·
ehabl¢d.
L
H
bus-to-TTL
··disabled
H
x
no transfer
disabled
*H=high level L=low level X =high or low level
Receiver
·high impedance
· enabled high impedance
· Specifications
The mechanical, electrical, and environmental ~haracteristics and ~pecifications for the DC021 are
described in the following paragraphs. 'nie test conditions f9r :the electrical values are as follows
unless specified otherwise.
. .
· Ambient temperature (TA): 0°C to 70°C · Supply voltage (Vee): 5.0 V ±5%
Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause:permanent damage to the device.
Exposure to the absolute maximum ratings for extended . periods may adversely affect the reliability of the device.
· Supply voltage CVcc): 7.0 V
· Input voltage (V;.) and output voltage (V..,): 5.5 V
· Ambient temperature (TA): 0°C to 70°C
· Storage temperature <Ts): -65°C to 150°C
Recommended Operating Conditions · Power supply voltage (Vccl: 5.QV ±5%
· Supply current Cfccl: 240 mA (maximum) · Ambient temperature (TA): 0°C to 70°C
· Relative humidity: 10% to 95% (noncondensing)
Confidential and Proprietary
4-285
-
DC021
de Electrical Characteristics The de electrical specifiC11tions of the DC021 for the operating voltage and temperature ranges specified are listed in Tables 3 through 5. Table 3 lists the de parameters for the bus-to-channel receiver input and outputs. Table 4 lists the de parameters for the channel-to-bus driver inputs and outputs. Table 5 lists the de parameters for the enable and select inputs. Refer to Appendix C for the test circuit configurationsteferenced in 'Thbles.
Table 3 · DC021 Receiver Input and Output de Parameters
Parameter
SymboJ Test Condition
Requlrements Min. Max.
Units
High·level
Vm
Enable/Select'
input voltage
Receiver out= 20 mA
Receiver out < 0.5 V
Vcc=4.75 V
1.72
v
Vcc=5.25 V
1.9
v
Low-level
VIL
input voltage
Enable/Select' Receiver out= -2.0 mA
Receiver out > 2.4 V
Vcc:.:4.75V
Vcc=5.25 V
1.50 v 1.66 v
High-level
Voa
Enable/Select2
output voltage
Receiver in= 0.4 mA
Receiver out= -2.0 mA
Vcc=4.75 V
2.4
v
Low-level
Vo1
output voltage
Enable/Selecf Receiverin=0.4 V Receiver out= 20 mA Vcc=4.75 V
0.5
v
Short-circuit Ios
output current
Enable/Selece Receiver in=0.5 V Receiver out= 0 V
Vcc=5.25 V
-40
-100 mA
Three-state
IoZL
output leakage
current
Enable/Select' Receiverin=0.8 V Receiver out= 0.4 V
50
µA
'Enable=0.8 V, Select=2.0 V 'Enable=0.8 V, Select=2.4 V )Enable=O V, Select=2.0 V 4Enable=2.0 V, Select=2.0 V
Test Circuit Cl,C2
Cl,C2
Cl
C2
C6
4-286
Confidential and Proprietary
...
00021
Pariuneter
18ble 4 · DC02l,Driver Input and Output de.Parameters
Symbol Test Condition
Requirements
Min. Max.
Units
High-level
~ZH
output leakage
current
High-level
liH
input current
and receiver
output leakage
current
~nt'
Enable/Select' Driver in=0.8 V Driverout=4.0 V Vcc=5.25V
Enable/Select2 Driver in=0.8 V Driver out=4.0 V Vcc=5.25 V
Enable/Select1 Driverin=0.8 V Driverout=0.4 V
V~c=OV
Enable/Sdect2 Driver in=0.8 V
v Driver out= 4.0
Vcc"'OV
.;Enable/Select> Driver in= 0.4 V Receiver in=5.5 V Vcc=5.25 V
Enable/Select· Driverin=2.0 V Receiver in=4.75 V
100
µA
100
µA
100
µA
100
µA
200
µA
. 60
µA
Low-level
Ion
output leakage
current
Enable/Select1 Driver in=0.8 V Driver out= 0.4 V Vcc=5.25 V
-85 mA
Low-level
VoL
output voltage
Low-level
111.
input current
Enable/Selects Dtiver in=2.0 V Dciverout=0.4 V Vcc=5.25 V
Enable/Select' Driver in=2.0 V Driver out= 100 mA Vcc=4.75V Driver out= 130 mA
Enable/Select" Driver in= 0.4 V Receiverin=0.8 V · Vcc=5.25 V
..... 85 mA
0.7
v
0.75 v
-1.6 mA
Test Circuit C9
C4 C9 C8
C9 C5
Confidential and Proprietary
_,....,.._~-----~-~~¥~
4-287
..·~- , ---%
-
Parameter
Symbol T~st Condition
High-level input voltage
Low-level input voltage
Requttements Min. Max. 2.0
0.8
Units
v
v
Test
Cin:uit
Cl,C2
Cl,C2
1Enable=0.8 V, Select=0.8 V 2Enable=2.0 V, Select=2.0 V )Enable=5.5 V, Select=5.5 V
·Enable=2.0 V, Select=2.4 V
~Enable=0.8 V, Select=2.0 V ·Enable=0.4 V, Select=0.4 V 'Im total consists of 40 µA (maximum) and loz 20 µA (maximum) leakage current in the highimpedance state.
'Applies to all possible combinations of Vrn and v,L at 0.8 v or 2.0 v
Table 5 · DC021 Enable and Select Input de Parameters
Parameter
Symbol Test Condition
High-1~1
Vm
input voltage
Low-level
VIL
input voltage
Enable or Select input·
Enable or Select input1
Requirements
Min. Max.
2.0
0.8
Units
v
v
High-level
Irn
input current
Vcc=5.25 V Enable=2.4 V Enable input
80
mA
Enable= 5.5 V Enable input
100
mA
Select=2.4 V Select Input
80
mA
Low-level
I,L
input current
Select = 5 .5 V Select input
Vcc=5.25 V Enable or Select input=0.4 V
100
mA
-0.4 mA
Input diode- Vr · clamp voltage
Vcc=5.0V ±5%2
Enable= - 18 mA Select= - 18 mA Driver in= - 18 mA
-1.2 v
1Applies to all possible combinations of Vm and V1L at 0.8 V or 2.0 V.
2Ambient temperature is 25°C. One input at a time.
Test Circuit Cl,C2 Cl,C2 C4
C5 C3
4-288
Confidential and Proprietary
-
DC021
ac Electrical Characteristics The propagation delays for the receiver input and output signals are listed in Table 6 and the waveforms referenced in the table are shown in Figures 3 and 4. The load circuits referenced in the table and used in the delay measurements are shown in Figure 8.
1 ;.is RECEIVER JN
- - - - - - - RECEIVER OUT
tR AND IF = 10 ns BETWEEN 10% AND 90% LEVELS.
REFER TO FIGURE 8. LOAD A FOR OUTPUT CIRCUIT.
Figure 3 · DC021 Receiver Input to Output Propagation Delays
ENABLE
TTL OUTPUT RECEIVER IN= 2.4 V
TILOUTPUT RECEIVER IN= 0.8 V
SlCLOSED
-1S20PEN tpzH
,.------3.0V
- --1.3 v
r ----..:----------ov tplz Sl & S2 CLOSED ----1.sv -------Vol +0.5V
tpHz
51 OPEN,
- - ~ - -VoH-0.5 V
I S2 CLOSED
'-----1.sv
- - - - - - - v ----------~-----,-o
S1 & S2 CLOSED
REFER TO FIGURE 8. LOAD B FOR OUTPUT CIRCUIT
Figure 4 · DC021 Receiver Enable and Disable Propagation Delays
Confidential lU1d Proprietary
4-289
-
DC021
The receiver inp4t waveforms for the noise immunity test are shown in Figure 5. 'fhe values indicated are for no response at the output. l'he load.circuit referenc~ in Figure 5 and used in the delay measurements is shown in Figure 8.
WAVEFORM A
= 1A AND IF 3.2 ns + 10% BETWEEN 10% AND 90% LEVELS.
RECEIVER OUTPUT> 2.2 V
16 ns WAVEFORM B
1R AND IF= 2.4 ns +10% BETWEEN 10% AND 90% LEVELS. RECEIVER OUTPUT> 2.2 V
9 ns--e.j WAVEFORM C
1R AND IF = 3.2 ns ±10% BETWEEN l 0% AND 90% LEVELS. RECEIVER OUTPUT > 0. 7 V
16 ns WAVEFORMD
± = 1R AND IF 2.4 ns 10% BETWEEN 10% AND 90% LEVELS.
RECEIVER OUTPUT ;). 0. 7 V
REFER TO FIGURE 9. LOAD 8 FOR OUTPUT CIRCUIT. (S 1 AND S2 CLOSED)
Figure 5 · DC021 Noise Immunity Input Waveforms
4-290
Confidential and Proprietary
-
Symbol
tRLH
tltHL
tPZL tnu
tl'LZ tPHZ
Table 6 · DC021 Receiver ac<Pl'dpagation Delays
Voltage.
Test Condition
Wavefurm
ReqWements Min. Max.
Figure 3
Vcc=4.75 V
Enable=0.8 V
Select=2.0 V
V1a=0.8 V to 2.6 V
35
V1n= 1.2V to2.2 V
39
Figure 3
Vcc=4.75 V
Enable=0.8 V
Select=2.0V
v.=o.s v to 2.6 v
35
v.= i.2 v to 2.2 v
39
Figure4
Vcc=4.75 V
Enab1e=O V to 3.0 V
Sdect=2.0V
Receiver in=2.2 V
37
Figure4
Vcc=4.75 V
Enable=O V to 3.0 V
Select=2.0 v
Receiver in=2.6 V
30
Figure4
Vcc=4.75 V
Enable=0Vto3.0V
Sdect=2.0V
Receiver in=2.2 V
30
Pigure4
Vcc=4.75V
Enable=O V to 3.0 V
Seleci:-=:2.0 V
Receiver in= 2.2 V
30
DC021
Units Load ·circuit
Figure8A
ns ns
Figure 8A
ns ns
Figure8B
ns Figure8B
ns Figure 8B
ns Figure SB
ns
The propagation delays for the input signals to output signals are listed in Table 7 and the delay waveforms referenced in the table are shown in. Figures 6 and 7, Th~ load circuit referenced in the
table and used in the delay measurements are shown in Figure 8.
...-.- · - - - · - - - - - - - - - - - · _,,.,.....,.....,.._~-w~~----·---·-·--·-h"-"'
-----------··~-··-·------···
-
Tabla 7 · DC021 Driver ac Propagation Delays:
Symbol Voltage
Test Condition
Waveform
Requirements.
Min. Max.
tPLH
Figure6
Vcc=4.75 V
Select=0.8 V
Receiver in=0.5 V
35
tPHL
Figure6
Vcc==4.75 V
Select=0.8 V
Receiver in=2.4 V
35
tum
Figure 7
Vcc=4.75 V
Enable=0.8 V
Select=0.8 V
25
tDHL
Figure 7
Vcc=4.75V
Enable=0.8 V
Select=0.8 V
25
t./tF
Figure 7
8.0
Coo,
OV ::!! V00 ::!! 4.0V
20
1CL = 15 pF including probe and jig capacitance.
2Driver output node capacitance.
:oco21
Units
Load Circuit
Figure 8C
ns Figure 8C
ns Figure 8C
ns Figure 8C
ns
ns
Figure SC
pF
---1µs
3.0 v-----1.5 v-----
DRIVER OUT
---Vol
IR AND IF= 2.5 ns BETWEEN 10% AND 90% LEVELS. REFER TO FIGURE 8. LOAD C OUTPUT CIRCUIT.
Figure 6 · DC021 Enable Input to Driver Output Propagation Delays
4-292
Confidential and Proprietary
---lµs
3.0 v----- ------....
DRIVER IN
DRIVEljOUT
DC02l
lR ANO IF= 2.5 ns BETWE!=N .~ 0% AND 90% LEVELS. REFER TO FIGURE 8, LOAD C FOR OUTPUT CIRCUIT.
Figure 7 · DC021 Driver Input-to-Output Propaf,(1ition Delays
Tuble 8 lists the current requirements of the {)C021, for various. ~put signal conditions.
lest Condition*
Select=0.8 V Enable=0.8 V Driver in=3.0 V
Select=0.8 V Enable=0.8 V Driver in= 0 V
Select=2.0 V Enable=0.8 V Receiver in=2.4 V
Select=2.0 V Enable=0.8 V Receiver in=0.5 V
Select=2.0 V Enabie=2.0 V Receiver in=2.4 V Driver in=0.8 V
*Vcc=5.25 V
Thble 8 · DC021 Current Requirements
Functipn
Re~ta
Mfu. . Max.
TTL-to-bus
240
mA
TTL-to-bus
150
mA
bus-to-TTL
165
mA
bus-to-TTL
110
mA
disabled
165
mA
Confidential and Proprietary
4-293
-
Vee
FROM
390ll TEST
OUTPUT;,-....--~....,..- POINT
1600!2
LOAD A-OPEN COLLECTOR CIRCUIT
Vee
TEST POINT
!2000
S1 FROM
OUTPUT>-...,..-'---.---lolm'--~
I ~'""'"' 120011
ALL DIODES
. 50pF ----<'i
"="
-=-
Vee
FROM
9Hl TEST
OUTPUT >--.--"--~-POINT
LOAD B-THREE-STATE TTL CIRCUIT
LOAD C-OPEN-COLLECTOR CIRCUIT
Figure 8 · DC021 Output Load Circuits
Mechanica,l Configuration The physical dimensions of the DC02120-pin DIP are shown in Appendix E.
4-294
· Section .5-Mass-storage devices
The mass-storage devices are used in the development of disk and tape drive interfaces. DC018 Serializer/Deserializer Logic-The DC018 is a 40-pin DIP bipolar device that converts serial data from a drive into parallel data and parallel data into serialdata. DC024 Encoder/Decoder Logic-The DC024 is a 28-pinDIP device that encodes and decodes the information between the head electronics of a mass-storage device and the logic of the DC016 serializerfdeserializer. DC309 Reed Solomon Generatorfor BCC-The DC309 is a 28-pin DIP dynamic NMOS device that implements a Reed Solomon error correction code (ECC).
Confidential and Proprietary
·Features
· Converts seriaI data into parallel data and pa.nijlel data into serial data.
',
'
'
'
'
'·:
, ' ' " '
-,_
'
~·--,
· Correlation \ogic provides autostim capabilities.
· Two speed variations aVllilable. '
· Selectabl~ word length of 8,10, -0r\6 bits. ·
· Description
The DC018 ~rializerJ,deseri~er, contained in a 40-J?ill dual-inli11e pac~e,,.(D~)r.ls,~ bipolar LSI
device developed for ~e in cl,js~-dpve co1't1'0llers. I~ Provides ,!he circuits !llld l~c req~ to
convert serial da~ itlto p~ data and panJ1efctata in~ ~~ial da~. )rie J:)C(ll8 performs the
conversion at a lninimuni $eriaI-bit time 0£ 36 nano5¢COnds. figµtt!, 1 !~ ii sitnpJi#ed, bIOck cliagram
ofDC018.
, ..
.
.. . .
CE
Pcm
POM WLSO WLS1 SDIO SDl1
SCI
p;;fi DR
m
!mm
SDtC
UPPl:R SHIFT REG. CONTROL
LOWER SHIFT REG. CONTROL
7 9 15.. UPPER SHIFT REG.
7 9 15
110<15>
' SYNCH BYTE DETECJORI'.",....l'""""-1--1--+--+-+--..
OUTPUT SHIFT REG.
TSSCO
TSSDO
soo
CHIP STATUS
Figurf? 1 · DC018 Simplified Block Diagram
O/UR PRDY
WRC
5-1
The DC018 is aVailable.in the following variations depending on t,he clock speed required.
Clock Frequency 14.3 Megahertz (maximum) 27.7 Megahertz (maximum)
Digital Part No. 19-17043-00 19-17043-01
The DC018 contains input logic that selects the serial data input line and parallel data word length, and controls the conversion process. An upper and lower 16-bit shift register and associated logic control the parallel I/O data transfers to and from the chip. The parallel data is available from threestate drivers circuits. The serial data outputs are available from the output shift register. One output provides TTL levels and is used for serially cascading two DC018 chips. The remaining output provides three-state driver output levels that are externally controlled for the parallelport and serial port operation. An autostart feature allows the serial-to-parallel conversion process to begin upon recognition of a serial-input bit pattern.
Autocorrelation logic detects 9 serial-input bits out of 12 bits at clock frequencies up to 14.3 Megahertz. At clock frequencies from 14.3 to 27. 7 Megahertz, the autocorrelation logic detects 10 serial-input bits out of 12 bits. During the shifting operations, the logic searches for a maximum of 5 bits that are in agreement. When the correlation is detected, the COnVersion process OCCUtS in any one of the selectable word lengths of 8 bits, 10 bits, or 12 bits.
· Pin and Signal Description
This section provides a brief description of the input and output signals and power and ground connections of the DC018 40-pin DIP. The pin assignments are identified in Figure 2 and summarized in Table 1.
TTLGND
ACl5
O/UR PRDY
1/007 7 1/006 1/005 11004
11002 1/001 11000 SDl1 SDIO SDIC ~
CE GND
Vee
TSSCO TSSDO
SDO WRC
som:
1/008 11009
1/010 11011 1/012 1/013 11014 1/015
m
POM
1/0 GND
,;m
WLS1 WLSO
TOP VIEW
Figure 2 · DC018 Pin Assignments
5-2
Confidential and Proprietary
-
ncmtr
Pin
Signal
1
TTLCND input
TTL ground-A TTL ground reference. Pin 1 con. nects to pin 20 in the shortest possible path.
2
A.CD
output1
Aotocorrelator detect-Asserted by the sync byte
detector when irsync byte is present. Used for test
P\U'l?~es only.
.
·.
3
SCI
input·
Seriaj.dock-Data is shifted into the shift register on the positive edge 9£ ~s signal.
,·, ·'·c,
4
O/UR
output1 .
Overrun/Underrun-Indicates that data has been
~d during ··a ttansf~r on the ~el port, as
foll~r Cleared by the master reset pt\lse (Mi).
1. P~ in mode-Asserted to indicate an overrun
· condition in the parallel out mode- when the POM
sigmtl and parallel reaifY (PRDY) signxtI· are asserted
' ··and the data ready (DR) signal is not asserted within
theword time.
. 2. Parallel out mode+Asserted to ihdicate an
underrun condition when POM signal is negated and PR.DY signal· is asserted, if the parallel input
strobea>LS) is not asserted within the word time.
5
PRDY
output'
, ']>~ready-Indicates that the DC018 is ready to
transfer or receive data as follows:
1. Asserted in the pamll.el out mode.(POH asserted)
wh&data is available on pins J/0< 15:00> and if
tlie~el out ~~iate enable.~ signal is
asserted. It is negated by the a.Ssertion of data
received (DR) if~ is asserted.
2; Asserted in the parallel in mode (POM negated)
when the DC018 is ready to receive parallel data and the master reset (MR) is negated. It is negated by the negative edge of the paralld input strobe (PLS).
?~ If.conditions l ap.d} do not OCQ).t. PR.DY will be
overrun negated before the parallel data becom~s invalid and
an.
or underrun .condition. (0/UR) .will be
·· indic.ated.
6
DR
Datareceived"'.'"""Asserte;d,by the ll!ICf to indicate that
the parallel data on pins I/0<15:00> has been received. In the parallel out mode (POM asserted) wh~n the data is available and the Pm'SE signal is
·asserted, the DC018 asserts the PRDY line. After the
data is received, the assertion edge of the DR signal
negates the PRDY signal.
Confidential and Proprietary
-
Pin 7-14
27~34
15 16 17 18
19
20 21
22 23
24
25
00018
Signal
Input/OutpUt
I/0<15:00> inputs1/outpu~
Deinitron/PL'lllWo(l
.Parallel data irlput/~utput-SiXteett pamllel datq lines that provide controllable thr~Ntate level outputs and include TTL level gates for the parallel
input signals. The PQM input selects the function of
the lines.
SDil
input1
· Serial data in 1-Serial data input channel 1 selected when the serial data input control (SDIC) signal is high.
SDIO
input1
Serial data in 0-Serial data input channel 0
selected when the the SDIC signal is low.
SDIC
input·
Serial data input control-When high, this input selects serial data input channel 1 (SDIO) and when
low it selects serial data input channel 0 (SDIO).
'POTSE
input'
CE
input1
Parallel output three-state enable-Asserted to enable.and negated to disable the parallel three-state outputs J./O < 15:00 >).
Counter enable-In the parallel-in, serial-out mode,
this line is asserted to allow the next positive edge of
the dock input (SCI) to enable the internal bit-rate
counter. In the serial-in, parallel-out mode, this line is asserted to permit the detection of a sync pattern
of the serial data to enable the bit-rate counter.
GND
input
Ground-A ground reference. Pin 20 connects to pin 1 in the shortest connection possible.
WLSO
input1
Word length select 0-Used with word length select 1 to select the length of the parallel data output word, as follows: WLSO WLSl Word length
H
H
16 bits
H
L
10 bits
L
H
8 bits
WLSl
input1
Word length select 1-Refer to word length select 0 description.
MR
input1
Master reset-Asserted to reset all internal registers
and counters in the DC018.
I/OGND- input
Input/Output ground-An isolated ground refer-
enee for parallel outputs 1/0 < 15:00 >.
PQM
input1
Parallel out mode-Asserted to select the serial-in,
parallel-out mode and negated to select the parallel-
i:n; serial-out mode.
5.4
Confidential and Proprietary
,
.. ,,~~-----~""",......,.._, ~---,----~~_....,_~~-~~.----~---
-
Pin
26
35
36
WRC
37
soo
38
TSSDO
39
TSSCO
40
1TTL levels. 2Three-state.
Input/Output Definition/Function
input1
Pai-allel strobe-In the parallel-in, ~ial-out mode,.
this signal is asserted after the parallel.ready(PRDY) ·
is asserted, to ·!bad the patallel data on lines
I/O< Ci:OO> into the p~el registets of the
DC018. The·PRDY signal fnegated when ~ signal
becornes law b¢fot:e. the.next j.fycle. can o«ut
'
'-,1 ·, - '" ' . ;, ""'"''
input1
Serial-out three-state enabie......Asserted to enable and negated to disable the outputs of three-state serial data out (TSSDO) and serial clock out (TSSCO) lines.
·output1 .. · Word rate clock'' .Adbek output with a·50 percent:
duty cycle that is decoded from the modulo n (n= 8 bit, 10bit, or 16 bit) counter with a clock period of n
bit times. The WRC sig~i~.~ser~;~W·'H!t e<:>t:WX o/f
. ~ $llld neg"-~ ~t t:I~ pi~t.jplet , . . . . ...
output
Serial data autpu~l!:Jsed to cas<!ad.E!:the serial data
from two DC018 chips operating withr t:he>same
serial clock input (SCI). It exhibits the same delay
characte.dstics Its the seiiiil.dil& l~t;,($Dl0 ~
SDil) and the,"I/0< 15:00;> ()Utputs as destttbed
for .the rssnq sigpal, .!lie m'inimum:·J!'topigation
delay fromwhen the $~id.~.scI sisn*'bi.nput
flte i? becomes {thighievet~a c~~e SD() level,
is greater than .the ~uni hold time oil the. SDIO or SDil inputs with respect to the SCI mput.
Th.tee,state ..seii~··':a'ata.·· riitt 'C6n~11~!:! '''f:&"'th~
SOTSE signal. ~ta txansiiions on this line are
ssiygnncahl.loni~g ¥. tfi,i.il.w. p. (ls.itive.ed.ges of ihe. 'rs.sco
output2
~state serial~ock out--A serial clOck output &at jg ad~ayed sa-i81 clock input'SCFsignak The
delay· conforms to the propagation time incurred by
the TSSDO output; ~~.i. t~J,posid~going .· e4Be ohhe~~P~ is,~yn~~ ~i.thT~sn.o
s9uotprustE.pisti.g~n.al'.!he do·pk o. utp.u.t ,· i·s· CQ··1· ltroll·e·d· pe d1e.
input
Voltage-Power supply de voltage
Confidential and Proprietary
5-5
-
· Specifications
The mechanical, electriaa{., and envirOnm<'.ntal ch~risHcs and specifications of t~ DC018 are
described in the following paragraphs. Th~ test ~onc}itions for the electrical values are as follows
unless specified otherwise.. Refer to Digital specification A-PS-2100002-GS for detailed specifica-
tions ofthe DC018". ·
·
· Operating temperature (TA); 0°C to 70°C · Supply voltage (V~J: 5.0 V ±5%
Mecbanical Configuration
The physical dimensions of the DC018 40-pin DIP are contained in Appendix E.
'
'
'
'
' '
Ahsalute Maxilnum Ratings
Stresses greater than the absolute lllaXimum ratings may cause permanent damage to the device. Exposure to the absolute maximum ratings for extended periods may adversely affect the reliability of the device.
· Supply voltage<Vcc): 7.0 V · Input voltage (V1): 5.5 V ··Operating temperature {TA): 0°C to 70°C · $toragetetnperature (T,):-65°C to 125°C
Re~mmended Operatlng Conditions
··.Supplyvoltage (Vee): 5.0 V ±5% · Supply current (L'.;c): 425 mA (maximum) · Free-air temperature (TA): O"C to 70°C · Relative. humidity: 10% to 95% (noncoqdensing)
ck Electrical Characteristics
The de electrical patameters ()f the DC018 for the operating voltage and temperature ranges
are specified listed in Table 2. Refer to Appendix C fur the test circuit configurations referenced in
the table.
·
5-6
Confidential and Proprietary
"'
' ,~ ?· Dc018 de InPut and()utput Par.meters
Parameter High-level input voltage Low-level input vriltiige Iriput clamp voltage High-level output voltage
Low-1~
outpµt Voltage
Input current
at maximum
input voltage
Test Symbol Condition
Vm
Table4
Vn.
Tab!e4
V1
Nee""' Open
lx=-U .ma
Voa
Vcc=4.7V
1o·
Table4
YoL
Vq;=4.75V
Jo2
Table4
I;
Va.=':5.~25V
V1,,5V
~t ' '' li1
Min. Max.
2.0
0.8
- -.1.5
2.4
Units
v
v
', , ,
''
v
~t
Chcuit
Cl
er
Cl
0.5 v
C2
f;O mA ; .-t C4
High-level
,llH
Vcc==5.25 V
input current
v1..;;z.4
Low-level
k
input ettrtent
Vcc=,,,n V1=0A
µA'
C4
'
.lllA./ C5
Short-circuit
las
ouq>ut cw:rent
High-lln.pe<ience Ion
state output
current
~
Vcc=5.25V'
Vcc=5.25 V V0 =0.4 V
Table4
Vcc=5,25V V0=2.4: V Thble4
-100·
-5.{)6 mA
C6
;..,
µA
cs
.C9
Supply current
lee
Vcc=5.25N
425 l}iA ,e1
Input
C.,
capacitance
8.0 pF
1lo=-1 mA for SDO, -6.5 mA for TSCCO and TSSDO, -400 mA for all other outputs.
'lo= 1 mA for ACD, 20 mA for TSSCO, TSSDO, and SDO, 5 mA for all other outputs.
1Im=20 µA for SDIO, SOU, MR, and~ 40 µA for SCI, SDIC, CE, POM, DR, PLS, WLSO, and
WLSl, 80 µA for POi"'SE, -140µAfor1<15:00>.
4l!L =-400 µA for SDIO, sen, SOTSE, I< 15:00 > , and DR, -800 µA for SCI, CE, POM, 'l?LS,
WLSO, WLSl, MR, and 'i5(')'fSE, -1.0 mA for SDIC.
'Not more than one output shall be short-circuited at a time and the duration of the short shall not exceed 1 second.
5-7
-
·(Ios for WRC) Failure to per£prr11~ ~stwhe:re .indi~ated on Tagle .lwm cause the WRC output to
change states. Ios for .ACI5,.. .,.2om:A. (nllriimwn) and-50 mA (maximum).
7lon=50µA, ~=-50 µA forT$SCO ahdTSSDO, lon=IIL, loZJI=lt for I< 15:00>.
ac Electrical Characteristics The input and output signal timing for the DC018 is shown ,in Figures 3 through 10. The· propagation delays and conditions for the symbols on the timing diagrams are described in Thbles 3
through 8. Refer to Appendix D for the input and output voltage waveform parameters used for
measuring the signal propagation delays. Figure 11 shows the load circuit for the TTL outputs and the load circuit and waveforms for the three-state outputs.
SCI
.......+ - DR~-+--+~_........_......._......,.........,.......,,._.........,__,,.._._........._......_......,...._........_ POTSE -+-r---.
_______f __ _
I
I
, I I l I I I I
SEE /"j
t - . _ NOTE 1 r- - -
WAC----'
FPM ASSERTED
NOTE: TWO ARROWS DEFINING AN EDGE IMPLY THE' EDGE OCCURSWHEN BOTH CONDITIONS ARE SATISFIED.,
Figure 3 · DC018 Signal Timing A
5-8
Confidential and Proprietfilj
' Taite 3 · DCOJ.8 SijW Tmiirig A ~s .
Symbol Conditions
Propagation r>eiay· (ns>
C..=1' pF
C..=SOpF
Min. Max.
Min. Max.
1
55
2
30
3
0
0
4
30
6
36
7
DR can be asserted up to
18
18
(m-l)(ta)....;t..... (nanosecobds)
after the negative-going edge of SCI
where;
m=8, 10, or 16 bits,
tcr =input clock period,
t....,,;.;18ns(ass~,
8
9
See Figure 11 ttra
18
tu
25
10
If DRis not asserted during the previous
70
word cycle, O/Ull will be asserted by the
DC018.
11
50
12 WRC will be negared by DC018·in the
50
middle of the 8 (4th bit), 10 (5th bit),
or 16 (8th bit) word cycle.
13 Pulse width low
40
40
14 Pulse width high
40
40
15 Valid data will be present on
5.0
I/O < 15:00> before PRDY is asserted.
Confidential and J1oprietary
-
Figure 4 · DC018 Signal Timing 8
Symbol Conditions
1
Setup time
2
3
Setup time
4
'liable 4 · DC018 Signal Tunmg B Parameters
Propagation Delay (ns)
Ci.= 15 pF
Ci.=50pF
Min. Max.
Min. Max.
25
25
-
30
40
4o
45
.5-10
Confidential and Proprietary
-
.sci
P R o v - -...
TfLS-+--...,...,,~...,..,.-=-==-=-=-=-=-=.;;-;::::::=+ti;::::::=::=~~~
. . . . . . . . . . . . . . . . . . . . . .__ EXPANDEDDIAGRAM
··~
"O<":-------·-;;--v~:::4,..~-,-A-};-
POM NEGATED
Figure 5 · DC018 Signal Timint C
Table S · DC018 Sipal Tuning C Pariubeters
Symbol C'.onditions
~Delay(ns)
CL=ISpF
Cr.=.SOpF
Min. Max.
M,in. Max.
1
55
2
35
3
50
4
WRC will be negated by DC018 in the
45
50
middle of the 4th bit, 5th bit, or 8th
bit word cycle depending on the 8, 10,
or 16 bit (respectively) word length
selected.
5
30
Confidential·and Proprietary
5-11
-
Symbql :oQditions ·
6
PLS·aan he asserted up to
(m-l)(tQ.)-~nanoseconds
after the negative-going edge of SCI
where:
m=8, 10, or 16 bits
ta- input clock period
tload =18 ns (as specified)
7
8
If PLS is not asserted during the
previous word cycle, O/UR will
be asserted by the DC018.
9
If PLS isa.ssereted, it must be
negated up to (m)(tcp)-t,.,.,
nanoseconds after the positive edge of
SCI where:
m=8, 10, or 16 bits
tep =input clock period
tsetup =5 ns (as specified)
10
Pulse-width low
11
Setup time
12
Hold time
oco'.fB··
Pl:o~tion l}et.y('8)J!
Ci.=15 pF Min. Md.
C~=50pF
M·' in. Max.
18
18
0
0
70
5.0
5.0
25
25
40
40
5.0
5.0
5-12
Confidential and Proprietary
SCI ___ r--~=::0-=-==r=.-®-=-=-@====
.SOIC
Figure 6 · DC018 Signal Timing D
Symbol DeSC1'ipticm, ·
1
SCll! pttl~·width low ·
2
SCIHpulse-wigth high
3
SDIO or SDI1 setup
time
4
SDIO or SDil
hold tjme
5
sci.high to TSSCO
high
5a
6
~tion~ay(ns) 1,..17041·00
Ct=tspF. 4=50pE
Min. Mu. Min. Max.
1'~17Q4)4ll
4.t\);J$pF Min. Max.
C.,=50pF Min. Max.
'lj
15
j()
17
17
30
30
5 ..>.~.,...
5
5
5
12
4cr 13 33 13
..'.fJ ..... '.fi' H 45
8
8
10
10
8
8
10
10
7
S5TSE low io
TSSCO (active)
20
25
20
25
C:Onfjpential and Pmptietary
5.13
: 0~r.
Symbol Description
Propagation delay (ns)
19-17043-00
CL=15pF CL=50pF Min. Max. Min. Maxi
19-17043-01 Ct=15pF Min. Max.
C1=50pF
Min. Max.
8
SOTSElowto
TSSDO (active) .
20
25
.20
25
9
Setup time
25
25
25
25
10
SCitoSDO*
13 33 13 40 13 37 13 45
11
SOTSE high to i ..
TSSCO (Hi-z)
18
18
12
SOTSE to TSSDO
18
18
13
Input clock period
36
36
70
70
(SCI)
14
SCl low to TSSCO low
13 33 13 40 13 37 13 45
14a
5
5
5
5
*Propagation delay controlled to allow cascading of two or more DC018 chips using a common clock.
Fl RST POSITIVE GOING CLOCK EDGE AFTER CE THAT IS RECOGNIZED BY
, . - - - - - - - - - - - . . CHIP
SCI
~
:~OR~~----....-....---~------~---1----1i~--1~
~
LAST NEGATIVE GOtNGCLOCK EDGE
, _ __ _,\ 1-1--.;.._.o_----
PRDY (WHEN POM IS.NEGATIVE!
PRDY .POM
5-14
Figure 7 · DC018 Signal Timing E Confidential and Proprietary
·-
Mfl !SEE.FIGURE 7'FOR
MORE DETAILED TIMING INFORMATION OF THE POM
SIGNALI
S D l 1 Q R - - - - - - - : - - - - - - - - - -.......-..
SDIO !SEE FIGUR!:6 FOR MORE
DETAILED 1'1MtNG INF1'1 INFORMATION
OF THE SOIO, SOIt SIGNAi.~ ·
'
NOTE:
FAILURE TO SATISFY THIS REQUIREMENT (161 MAY CAUSE A~YN<lH(tONIZJiR~'OBL,EM
; tN'[MHP<l TOT.f't'*~fl>.·· , .·
1
For initialization
~f(in'.Dehly (fit)
. Ci,·':':Ji5pF H
, Ci.=50 pF
Min.. Max. ·--_-,_';:\:_'_, -
Min. Max.
60
60
2
Pulse-width low
80
80
3
If POM is negated, PRDY becomes high
50
after MRL is negated. If POM is asserted,
PRDY remains negated until the sync
byte is detected.
4
75
75
5
Setup time
50
50
6
Setup time
25
25
7
Hold time
15
15
. 5-15
Symbol Conditions
Propagation Delay· (ns) ·. ·
C1 =l5p:F·
Min. Max.
Cr,=50pF Min. Max..
8
PRDY must~ negated before POM can
0
0
be negated to assure the validity of the
data.
9
85
85
10
0
0
11
Pulse-width low*
25
25
12
Figure 11
Ti.a
TLZ
34
40
41
50
13
55
14
Hold time
3.5
3.5
15
Hold time
30
30
*Refer to Figure 7 and notes for additional PLS signal information.
SCI SDIO or 1 5011 - - - . . ,
Figure 9 · DC018 Signal Timing F
Confidential and Proprietary
···..~
Table 8 · OC018 Signal Timing F Patam$H
Symbol Conditions
Propagation Delay (ns)
Ci.= 15 pF·
Ci.= 50 pF
Min. Mu:,
Min.. Max:.
1
Signal ACj) will he asserted after the
70
12th bit ofthe ~nc byte is shifted in.
2
70
3
The sync byte ~tor will nigger when
9
10
a minimum of 9, 10, 11, or 12;bits are in
agreement or wl;i.en 10, 11, or 12 are
in agreement for the specified clock rate.
figure 10 · DC018SignalJiming G
C(}.nfidential and Ptuprietary
5-17
...
TEST POINT
FROM OUTPUT
2KQ
ALL DIODES F07000R EQUIVALENT
TEST POINT
FROM OUTPUT
15 pf
ALL DIODES FD700 OR EQUIVALENT
LOAD A TTL OUTPUTS
R1·2K!2, R2=1K.!l FOR Pl NS 7- 14, 27-34
R1=260n, R2=1KS"! FOR PIN PINS38, 39.
LOAD B THREE-STATE OUTPUT
OUTPUT
CL O(NLOTRWOLLEVEL ~
·
f .-------3v
ENABLING)
V..T_(_N_O_T_E_3_)_ _ _ _ _ ~~--------ov
tLz [ · ~~ ~rigSED
0.5V
WAVEFORM 1
(NOTE 11
--'-t"--1.5V
WAVEFORM 2 (NOTE 2)
IrtzH
f ------.\---- S1 OPEN
VTINOTE 31
-----1---VoL
tHz tj-..--
o.s v
F ~0 V.O5HV
1 1.5 V
_ _ _S_2CL_OS_ED.,, ------ov
S1 AND S2CLOSED
NOTES: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW EXCEPT WHEN DISABLED BY THE OUTPUT CONTROL
2 WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH EXCEPT WHEN DISABLED BY THE OUTPUT CONTROL
3 Vt=1.3 V FOR ALL OUTPUT PINS EXCEPT 3B ANO 39 Vr 1.5 V FOR PINS 38 AND 39
THREE-STATE OUTPUT WAVEFORMS
Figure 11 · DC018 Output Load Circuits and Waveforms
5-18
Confidential and PtoJ?rietary
· ~-rate encoder/decoder algoithm for mass-storage devices · Compatible with the DC018 Serializer/Deserializer
· TTL and ECL inputs and outputs
· Phase detector and counter/divider · Diagnostic mode operation
· Description
The DC024 encoder/decoder, contail!led. in a .28-pin duahinline package (DIP), provides the
functions required to encode and decode.j:he data betweenthe head electronics of a mass-storage device and the logic of the DC018 serilti~/deserializet.'.ln,addition to the encoder and decoder logic, the DC024 contains phase deteetot~;dividers, and &attoUogic for a phased-locked loop. A
test mode is provided to allow the DB0~4 and DC018 SEfla1!zer/Deset:ializer to be operated in an
end-around configuration for diagnbSti:ef purposes. F~·l is a simplified block diagram of
DC024.
'
The DC024 performs the ~-rate encciaing/decoding ~od'fum for mass storage products. It
operates with TTL and ECL level inputs and outputs'and requires 8. 5 V and-5.2 V power supply.
9'0+/Efll·
Figure 1 · DC024 Simplified Block Diagram 5-19
This section provides a brief description of the input and output signals and power and ground connections of the DC024 28-pin DIP. The pin assignments are identified in 'Figure 2 and
summarized in Table 1.
VCK
owe
DIAG
ORC
DRO
Vet GND
GND CLR
DWD
EWC
ERO+ EROVCK+ VCKUP+ UPGND ON+ ON-
E,WD+
EWDVEE
A1
AO
TOP VIEW
Figure 2 · DC024 Pin Assignments
;.20
Confidential and Proprietary
-·
28 ERD+· inpU:ts1 27 ERD-
u DWD
Enooded read data---A signal from the read circuits. Each flux
reversal tO the read·cireuits results in a pulse input on this line.
During mOO'e<TI; t1l! asserti~~e of the l'ulse enables the phase
<.letector .of ~h~·~Q,.24. tQ. ~orm a pk,as,;i.~mprui.J9;n of the
;d~ng edst~ ~ ntl)~ A and B, the phase detector is
internally enabled and.a pba.:ie.compiu'isonis ~rfon,n~ on· the.
cleassertinge~ Qf theSC< .~is.
·· ·
·
· · .,.,,. ',.,_;· ,·- ··'·
,,_k., 'c>;· - ,
p~~?~;Wi.-i~.d~~ ..·TtUS:·~~ruu is an input from the deserial-
izer of the system and is u~,:~ng write operations. The data
is.in r-iR?: form«tandwill be~~dedby the DC024 befc>re being
Wrltterioij the media.
·
·
2
15 AO
16 Al
inpu~··
J)ecodc:a !Wri~ cl~k-An:~t with a clock frequency of one
cyo}e;Iat.¢P di;i~ writ~~ta bit. When writing, this signal
is .~ oftlre :inputS .m the phase detector. An internal loop signal
of ;tlre. sarot. ~~w;:y. and·piulse when locked clocks the
. decpd~ Wt'.ite, da~~ip.tQ ~ ~~ This :mput must be i:ptmected
~Y tc>JM'~#t'C4'ecl~.source orirtdirectly through the dt:~~. lt'~apnotoe mc@directly to clock the decoded write
data into the DC024'. .
'
·' ' ,,J ' , , ,
'
·
.-,·,. " \ '· '.-
·Ai ·'
,0
b 1'
1
Mtii:f~
. ·f.: (~1nnble)
B. (p~l\\ble-troneat:e).
.~<4~) ..
D{~)
11 CLEAR inpuf ..
Ckar-W\ben,asserted1i all 0~24 storage. elements are .cleared
and the logic is set to a known state.
26 VCK+ inputs' 25 VCK_:
1 VCK input2
Voltage control clock-The dift~ntial input from an external
voltage controlled oscillator, Pl"QVides a frequency of two cycles
·fot .~.encodeddata:bit (tbree~es,.pe:r decoded data bit).···
Voltage dock-Used during diagnostic mode as th~ pful~
locked loop feedback clock.
3 DIAG input2
24 UP+ 23 ·UP-
outputs'
Diagnostic mode-When asserted, the DC024.enters t,h~ 9iagnostic mode. The VCK clock signal is used as a substitute for the VCK+{VCK~ clock input as the feedbadc dockfur·the phaselocked loop.
Up freqtiencf-'The phase defeci:or output s~als that causes
the. voltage controlled oseilla.t<>r··!»· increase ~~frequency. The duration of the assertion of this signal is proportional to the magnitude of the phase error.
5·21
-
Pin .signal
21 DN+ 20 . DN-
outputs1
Down frequencyi.:..:'..The ph!!Se 7detecror '00.tput that· causes the.
The voltage controll~d oscillator to decrease its frequency. dura.
tion of the ~sserton of th~ signal is proportional to the magni-
tyde of the phase error,
14
EWC
output~
19 EWD + · outputs1
18 EWD-
Encoded write clock-A dock output from the phase-locked loopcircuit with one cyde for each encoded write data bit.
Encoded write dat~--Acorobined output of the NRZ encoded write data and the encode.cl write clock. Every "one" input of the NRZ encoded write data signal causes the· outputs· tb change states.
4
DRC:
output2
5
DRD oqtput2
· Decoded read clock-This sigoal is a clock output that is phase
locked to the external input of phase-locked loop (ERD +/ERDwhen decoding or·DWC when encoding} ·at xa frequetJ.cy of one
cycle for a decoded data bit. Used to clock the decoded read data from the DC024 during read operations and as a clock source into a deserializer during write operations.
Dec~ded read data-This signal is an NRZ serial output of the DC024 that is decoded f:roro the serial input to the when reading encoded 2/3 rate) data .from the peripheral. This signal is normally used as an input to a deserializer. While writing to the media, this signal is not disabled and shifts the decoded data (DWD) out delayed by 10.5 VCK+/VCK- cycles.
6,7 Vee 8,9 GND
input input
Voltage-Power supply 5 Vdc. .. Ground-Ground reference fo~ 5 Vde.
17 Vu
input
Voltage-Power supply-5.2 V,
1-,U, GND 22
input
·Ground,.....Ground reference for the -2.5 V. ·
'ECLlevels
2TTL levels
';r,
)The multiple power and ground pins of the'DC024 must he properly connected to assure proper
operation,
· Operation ··
The OC024 encooer/deroder consists of three main logic sections-a phase detector, a counter/ divider; and an encoder/decoder. It implements the .?().rate modtilation code shown in Table 2. In
the bit seqJ.Iel),<;¢~, t,he bits at the ,left are the first in time.
Note: Sign@> tefei;enc;ed in· the descriptions that. Ql,'e e,pclosed in brackets [ ] are internal signals
only.
5-22
Confidential and· Pn>prietary
'-
Table .2 · DC024 2/3-Rate Modulation ~
Data Bits
00
xoo
01
XOl
10
010
1100
xooooo
1101
XOOOOl
1110
010000
1111
010001
*X= The complement of the last bit of theprCviously encoded data.
Phase Detector ' The phase detectorpperatesin O~·of t~ fourm!)des ~~d·hy;the 1\0,andAlinputs. These inputs are decoded hyihe·countei/dividedogic to 'Select themadeirlisted iri 1ilhle 3'.·
Mode A
Mode:control
Al
AO
0
0
[VC~6]·······
B
0
c
l
l
ERD+/ERD-
[VCR/6]
1
.~Rq+/ERD-
D
1
0
[VCK/3]
*Signals enclosed in brackets []are internal to the DC024.
Preamble Pream'ffie-Truncate Read/decode Write/encode
~.J\ .·..This,wast~.·~··.aR<3~tlvelo~~·inru}~::·J:~'.P~-~~~.~~'~.f~.~,£~~is~iof
flip~flt)p~.Etq~ !\~ Et(\7, ~ffi>-~9p E,:lQ~ is~t~W~ ~isi~* ~~~~~~-l~.g'1~P~t divided by 6. Flip-flop E107 is set by t1Je trll~,~ ,9£~ ~~"\~9fi¥~~~cil:lp}lt [}!~~]~
Both flip-flops are cleared immediately after they are both set. The output of flip-flop E108
indicates that the VCK clock frequency is low and is used to increase the charge of a filter network. Flip-flop E 107 indicates that the VCK frequency is high and is used to decrease the charge on a
filter network. At the start of a read operation, a special data pattern designated as the "preamble" is decoded to establish a phase lock before the normal data is read. The decoded preamble consists of all zeros. When encoded, the bit pattern is 100, 100, 100 etc. A lower frequency clock from the counter/divider is used as feedback to the phase detector when the preamble is expected.
Confidential'Wl>nl~r~
.5-23
UP·
VCK+ EWC DRC
Figure 3 · Mode A Phase Detictor Operation
Mode B-Figure 4 shows the logic for mode B. When the phase of the loop is locked, a lost bit in
the preamble data, indicating an error condition, could cause the loop to differ by one or more bits.
A truncate function is provided 'so the phase'detector can be reset by a signal from the counter/ divider after on~-half cycle of the feedback signal. This function should not'be used until frequency
lock is established as it may extend rime to frequency lock.
' ·
5-24
Confidential and Proprietary
.,.
[TRUNC CLK HI!
EWC ORC [TRUNC CLR HJ
[TRUNC CKL HJ [PT1J~~--~~--.i-.....--~--~--~~~_,-,..,.,...,..,.,...--,...,_...... ~....,.,,.,.,,.-~~
[PT2J~~----~--~~--~--~~~--------~-...----*'"'~-----
(VCK/6] [EROL]
ON· UP-
Figure 4 ·Mode B Phase fJeteetor~vn
Confidet;ltial·an4 Proprietary
5-25
-
Mode C-During a decoding (read) operation, the data input to the phased locked loop contains ones (pulses) and zeros (missing.pulses). Figure 5 shows the logic circuit and signal timing for mode B. The leading edge of the encoded read data [ERDL] pulses are used by the phase detector to prevent missing pulses from being interpreted as late pulses. This is performed by allowing a phase comparison to take place on the trailing edge.
[HJ [ERDLl
[HI D
DN ·
[HJ D E107
Figure 5 · Mode C Phase Detector Operation
5-26
Confidential and Proprietary
-
Mode D-TI:ie operation of the phase detector during the encoding (write) operationis1s~ to
the decoding (Rad)~tion except that the encoded read data;{ERP +/ERD--) sig®l.~i; .replaced with the decoded writ¢ clock (l}WC) signal. Figure 6 shows the k>gic circuit and sign,al ti$i,ng for mode D.·Feedback to the phase detectorJs provided by afVCK/3] signal from the count~dividet
logic.
DRC
Figure 6 · Mode D Phase Detector Operation
Confidentia1·and:Proprietal'f
'5-21
Countet/Divider
The co1:utter/divider provides the timing and clock signals td control the operation of the DC024
and fe~ck to the phase detector. The logic receives a differential Input (VCK + and VCK-) from an external voltage ~ontrolled oscillator during normal modes of operation. The counter/divider · ·
provides divide-by-two [VCK/2], divide-by-three [VCK/3], and divide-by-six [VCK/6] clock pulse to the phase detector depending on the operating mode selected. During diagnostic mode, the internal VCK signal is used as the feedback clock to the phase detector and the external signals are inhibited.
Encoder/Decoder
The encoder/decoder logic implements the ¥.I-rate modulation code and consists of a 4-bit fast serial shift register (Fast SR), a 4-bit slow serial shift register (Slow SR), a decode logic matrix, and
an encode logic matrix. The encoded shift register (fast) is clocked by the clock [VCK/2] signal from
the counter/divider and transfers the encoded data stream corning from or going to the disk interface. The decoded shift register (slow) is clocked by the [VCK/3] signal from the counter/ divider and transfers the decoded data stream coming from or going to the DC024. The decoding function and signal timing is shown in Figure 7. During this fllllction, the serial data read from a disk is synchronized by the [VCK/2] clock pulses and serially loaded into the encoded shift register. Every three bits shifted into this register are decoded to two Qitsiby the decoder matrix. The
decoder matrix transfers the information in parallel to the decoded shift register. The data from
this register is serially shifted to the DC024 logic functions.
[ENCODED DATA IN]
[VCK/2]
5-28
(LOAD H) (DRC INT)
DECODER SHIFT REGISTER
ORD
SHIFT
I
[VCK/2} VCK+
SHIFT
'
SHIFT
I
SHIFT
I
SHIFT
I
SHIFT
I
[DRC INT]
[LOAD HJ - - - ,
I
LOAD
SHIFT
I
LOAD
I
SHIFT
Figure 7 · DC024 Decode Function and Signal Timing
Confidential. and.Proprietary
-
DC024
The encoding operation and signal tinii.ng are shown ip Figure 8. A serial data stream is transferred serially to the decoded shift register. Every two bits shiftedinto this register are encoded to three bits by the encode logic matrix. This information is then transferred in parallel to the encoded shift register that serially shifts the data to the disk interface.
[LOAD H] [VCK/2]
IEWDH]
SHIFT
l
JVCK/2]
[LOAD H]
VCK+ {DRC INT]---,.__ _ _ _ ____,
·1....._ _ ___.r
I
. 'SHIFT
1
SHIFT .
I
SHIFT
r
SHIFT
Figure 8 · DC024 Encode Function and Signal Timing
When the DIAG line is asserted, a special diagnostic function is enabled by connecting the encoded shift register in an end-around configuration as shown in Figrtre 9. This function may be used as an open-loop test of the DC024 by bypassing the VCO controlled phase-locked loop. By selecting the proper operating modes through AO and Al lines, two serial bits on the DWD input can be shifted into the decoded register, encoded through the encoded matrix, and loaded into the encoded shift register. The end-around connection reshifts the encoded write data into the encoded register which is then decoded through the decoded logic matrix. This information is then transferred in parallel to the decoded shift register that serially shifts the data to the DRD output.
Confidential and.Proprietary
5-29
[VCl<;/2) {LOAD HJ
001>24
ORO
Figure 9 · DC024 Diagnostic Mode Function
The timing for a typical diagnostic mode operation is shown in Figure 10. Table 4 contains the possible decoded write data input patterns and the expected decoded read data output patterns.
~ VCK
h CLR
A1 AO
DWO
DAD
DRC
~ R R ~ llM nR ~ ~ n n n ~
L
Al A2 A3 M1A5 A6 A7
ll I 1
Al A2 A3 A4 A5 a1 a2 a3
01I 02 I B3JB4 85 86 B7j
~
I Tl
81 82 83 84 85 bl
~
h t- ~ ~ ~ ~
~ H
~
"X - UNDEFINED
Figure 10 · DC024 Typical Diagnostic Mode Signal Timing
5.30
Confidential and Proprietary
ncoi4·
"Jllb)¢ lf ·l)C0l4 Typical ~.Mode Deooded Data Patterns
Write Data Input*
Al Al A3 A4 A.5 A6 A7
0
1
1
1
0
0
x
0
1
1
x 1
0
x
x 0
1
0
1
0
x
x 0
1
J
0
0
x
x 0
1
1
0
1
0
x 0
1
1
0
1
I
x 0
1
1
1
0
x
x 0
1
1
1
1
0
x 0
1
1' l ,._,
1
1
xx0 0 0 0 x
x x 0
0
0
1
0
x x 0 0 .o 1 1
xx 0
0
1
0
x
x
x 0
1
0
0
x
x x 0
1
0
1
0
x x 0
1
0
1
1
x x 0
1
1
0
x
x x
0
1
1
1
0
x x 0
1
1
1
1
x x
1
0
0
0
x
Read O.ta Output
al
a2
a3
1
1
0
1
1
1
1
1
1
o:
0
1
0
0
1
1
0
1
0
1
0
0
1
1
1
l
1
0 0 ,, .....
0
0
0
0
1
0
0
1
0
0
0
0
1
{)
0
1
1
0
1
0
1
0
0
1
1
1
l
1
1
1
0
1X represents either a 1 or 0 sta,~· ..
.. . . . . .
2Application of all input state~ lis~ will ~ercise 93 perce.nt Of the leg~ decode input sequences
and 92 percent of the legal encode input sequences. · ·
·
Read and Write Signal Timing .. Figure 11 showsthe timing relationship of the ~ignals-dllfing ~ad and write:..functions, During read operations, the encoded read data (ERD) foom the head ele¢ronics 0£ the storagedevice results in a
decoded read clock (DRC) signal and the decoded read data (DRD) output. This output is normally
transferred to a deserializer. During write operations, the decoded write data input from the
serializer results in an encoded write clock (EWC) signal and the encoded write data (EWD +/
EWD-) output to the storage device electronics. This output provides a nonretum-to-zero signal to
the head electronics of the storage device.
Confidential and. Proprietary
5-31
-
ncoi4
VCK+ TRIPLET
ERO-
A
B
C
D
E
+---..-~..---+-~.----.-~t---1r-"--r---t~...--...~+--...-....-r--+--
EWC
DRC
ORD PAI
R
-
-
-t
-
-
-
-.
X ,r-
--
-
-;
t
-
-
-.
-X1---1----.-A,--
-1
-
-
-
.
.B.
.1
-
-
+
-
-
.C.-
,
-
-
READ 1/0 TIMING
VCK+
OWD
PAIR
DRC
EWC
EWD+ x
x
x
A
B
c
TRIPLET
WRITE 1/0 TIMING
Figure 11 · DC024 Read and Write Operation Timing
Counter/Divider Functions The counter divider provides all the timing and clock signals, feedback to the phase detector and control for the encoding and decoding functions. The DC024 uses a ¥Hate modulation code described in Table 2.
'ltansition Detector During read/decode operation (Mode C), the encoded read data from the device is tranformed from a pulse format to a non-return-to-zero (NRZ) signal and synchronized with the voltage controlled oscillator feedback dock to allow loading and shifting into the encoded shift register. Figure 12 shows the logic and signal timing that performs this function.
5-32
Confidential and Proprietary
-·
IERO:PULSEJ
DC024
VCK+ ERO [ERO PULSE]
IVCl</2J
Figure 12 · DC024 Transition Detector and Signal Timing
Flip-flop E104 chariges state on the rising edge of the enoodecl'reacl data [ERD PULSE] input from
the multiplexer. This indicates that a logic one of the data read h~ been detected, Flip-fl()P E205 synchronizes the data.and, together with flip-flop E206 and t~ ~elusive OR gate, provides the
separation of the synchronized signal. To assure that transitions at E104 .are.· recognized and
clocked during the proper bit cell for correct decoding, the encodecfread data and VCO clockinput
must be near a "phase-locked" condition.
·
·
'
A read data capture window defines a period of time during whlcll a high~to-l<)w transition of the ERD signal can occur and be recognized in the proper bit ceY· artd therefore become correctly decoded. The probability ·that the data transition will. not,be· tec,Ognized in .the ·proper bit cell
increases as the phase lock between the data and the VCO signalis degraded. As the rising edge of
the ERD- signal passes the right or left window boundaries, the transition of flip-flop E 104 will be
recognized by E205 either a bit cell too late or a bit cell too early. Refer t6 Figure 15 and Tuble 7 for
the the parameters associated ·With this windaw. Thble 7 speeiifies the absolute limits for these
paramenters to assures the correct decoding of encoded read data.
·Confidential llndProprietaty
5-33
-·
· Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DC024 are described in the following paragraphs. The test conditions for the electrical values are as follows
unless specified otherwise. Refer to Digital specificationA-PS-2100002-GS for general information
on integrated circuits. · Operating temperature (TA): 0°Cto 70°C
· Positive supply voltage (Vcc): 5.0 V ± 5 %
· Negative supply voltage (VEE): - 5.2 V · Relative humidity: 0 to 95% (noncondensing) · Storage temperature (T5): -65°C to 150°C
Mechanical Configuration The physical dimensions of the DC024 28-pin DIP are contained in Appendix E.
Absolute Maximum Ratings Stresses greater than the absolute maximum ratings may cause permanent damage to the device. Exposure to the absolute maximum ratings for extended periods m,ay adversely affect the reliability of the device. These ratings are for stress 'conditions only and do not imply that the device will function properly at these ratings or ratings above those indicated. All voltages are specified with respect to ground. The device must survive any combination of voltages within the ratings indicated. The ECL input voltage must not be allowed to go more negative than VEB· · Power supply voltage (Veel: -0.3 V to 7.0 V · Power supply voltage (Vn): 0.3 V to -8.0 V · ECL input voltage (V10): 0.3 V to VEE · TTL input voltage (V..): -0.5 V to 7.0 V
Recommended Operating Conditions · Power supply voltage (Veel: 4. 75 V to 5.25 V
· Power supply voltage (VEE): -5.46 V to -4.94 V
· Positive power supply current (IqJ 213 mA (maximum)
· Negative power supply current (IEE): -37 mA (maximum)
· Linear air flow 500 feet/minute (minimum)
de ElectricaJ Characteristics The de electrical parameters of the DC024 for the operating voltage and tempe~ture ranges specified are listed in Table 5. Refer to Figures 13 and 14 for the te.st circuit configurations referenced in the table. The conditions listed in Thble 6 apply to the test circuits.
5-34
Confidential and Proprietary
...
00924
,,,.r-;
Panmeter High-voltage input levd
Low-level input voltage
High-level input current
Low-level input current
'l8ble' ~ ~~4 de IDPut and Output~
Symbol Test
Conditions1·U
ReqUkements Unit
Min. Max.
Vm
Vcc==5.25 V
2.0
5.25 v
Inputs: DWC, bWD; '7CK
AO, Al, DIAG, CLR;
Differential inputs: VEE=-4.92V ERD-=-3.0V ERD+=OV vcK..:.=-3V VCK+==OV
-2.8 -3.0' ..;2;1s
~3.0
0 v -0.2 v 0 v -0.2 v
Vu..
Vcc=4.75V
Inputs: DWC, DWD, VCK, ...o.r· 0.8 v
AO, At,r>i'.AG;CLR
Differential inputs:
VE11=-5.46 V ERD-=OV ERD+=-3V VCK--=OV VCK+=-3V
-3.0 ..:2.8.
""'-'.o
..:.2.8:
-0.2 v
0 v -0.2 v 0 v
Im
Vcc=5.25V
V.,,.=2.75V
Inputs: DWC, DWD, "1t:k, -·'...,;,J
50
µA
AO,Al,CLR Input: DIAG
-
150
µA
Differential inputs:
VEE=-5.46 v
V.. =O V1 ERD-=OV
0
,60 µA
ERD+=-3V VCK-=OV
0
60 µA
0
60 µA
VCK+=-3V
0
. 60 µA
In.
Vcc=5.25V
V;,,=0.5 V2
Inputs: DWC, DWD, VCK, ' 0 '":500 µA
AO,A,1,CLR
Input:DIAG
0
-1.5 mA
Differential inputs:
VEl!=-5.20V
v~;..-3,0V
ERD'...=OV ERD+=-JV VCK-=OV VCK+=-3V
:.:.5,0
5.0 .· µA
-5.0
5.0 µA
-5.0
5.0 µA
-5.0
5.0 µA
F-tp' r'e../Tes.t 13/A
13/A
13/EJ 13fD 14/.E
13/D
13/D
14/E
Confidential and Proprietary
5-35
....
Dco24
Parameter
Symbol '''felt
Conditions' ·2 ·J
~tmts Unit Figure/Test Min. Max,
High-level
Von
output voltage
Vcc=4.75 V I,,·· =-2.6 mA Outputs: EWC, DRD, DRC
2.4 v 13/B
Differential outputs:
VEE=-5.2V UP+, UP-, DN +, DN-, EWD+,EWD-
0°C 25°C 70°C
13/C
-1.0 -0.96 -0,905
-0.84 v -0.81 v. -0.73 v
Low-level
VOL
output voltage
Vcc=4.75 V
I....=8.0mA Outputs: EWC, DRD, DRC 0
0.5 v 13/B
Differential outputs:
v VEE=-5.2
UP+, UP-, DN +, DN-,
13/C
EWD+,EWD0°C 25°C 70°C
-1.87 ,-1.85 -1.832
-1.665 v -1.65 v -1.63 v
Short-circuit Ios
output current I
Vcc=5.25V' Output: EWC, DRD, DRC -15
-60 mA 13/B
Positive power lee
supply current
Vcc=5.25 V·
v VEE=-5.46
213 mA 14/F
Negative power IEE supply current
Vl!.E=-5.4 V' Vcc=5.25 V
-37 mA 14/G
Input clamp Vic diode voltage
Vcc=5.0 V
VEE=-5.2 v
L.=-18mA Inputs: DWC, DWD, VCK -1.5 AO, Al, CLR DIAG
v 14/H
Input leakage 11
current
Vcc=5.25 V
v YEE=-5.46
V1n=5.5 V Inputs: DWC, DWH, VCK,
AO, Al, CLR, DIAG
,-0.05
1.0 mA 14/H
'Voltages are specified with respect to ground. 2Positive values of current flow into the device and negative values flow out of the device.
'Not more than one output shall be short circuited to ground at a time and the duration of the short shall not exceed one secorid.
·This test is performed with vcc at 5.2 v.
'This test shall be perfor.r,ied with VsE at -4.2 V.
5-36
Confidential and Proprietary
Vee
NOTES 1TO3 {TABLE 6)
ERD+
ERD-
VCK+ VCK-
ISWC
i'.5i.llJ§
A1
AO VCK CLR DWI>
DC024 GND
CIRCIUT A
Vee
OC024
GNCl CIRCUIT B
Vee
Vee
Vee
Vee
UP+ ON+ EWD+
UPONEWD-
DC024 GNO
=
CIRCUIT C
i--2.0 v
~
A1
AO VCK CLR OWOH
DC024
GND.
CIRCUITD
Figure 13 · DC024 de Test Circuits'
Confidential and Proprietary
5.37
Vee
Vee
ERO+ VCK+
ERO-
VCK-
OC024 GND
CIRCUIT E
Vee
VeECMAI
tlEE
.. Vcc1MAXl ., Vee Ice~
DC024
GNO
CIRCUIT F Vee
OC024 GNO
CIRCUIT G
owe
~
"T{· A1 AO VCK
CLR
VtN DWOH
DC024
or VcL
GND
J
CIRCUIT H
Figure 14 · DC024 de Test Circuits
CQnfidentia! and, Proprietary
-
Condition ..
FilurefCireuit
Reference
v v 1. The IH and OI. for the TTL inputs.are determined by the test c;ircuit logic. 13/A
2. Refer to Table 5 for ECL input conditions. Vm and V1L applied as indkatedby
the test seqµence.
1~/A
3. Each input iS tested separately. All other inputs must ~~ ¢destrequire·
ments at the voltage specified in Table 5 forVu, andV1w · .
13/A
4. The ECL inputs are tested by differential pairs and the input voltages-are '.13/A,13/B,HC .
applied to· meet the Vm and VoL specifications of Tabl~ 5.
; ' · t3/D,14E,14/F
l4/G ..
are 5. The test conditions listed in Table5.
1.3/B
are 6.· The input conditions determined-by the test sequencec.aiat').yvµl~···
within the range specified for Vn1 and V{)L·
..· 1.J/B,13/C
7.· Theinputconditionsareindicatedin.Table 5: ····
13/0;14/E
8. Each input is tested separately with the remaining TTL inp?ts connected to
GND. . .
.' .. .
1~/D,14/:H
.. ·. 9. Each diffe~ntial i.rtput pair is Jested ~~telt
·Tue 10. !rt outputs ~ open.
·. lJ/D,14/E,14/F
11. The ~er supply current must not eiceed the limits spedlied in. Table 5 for
any combination.of input logic levels.
14/F,14/G
ac_Electrical Characteristics
.
. .. ,
. .
. .
. ..
The input and output signal timing fur the DC024 iS shown in Figures 15 through 19. The
propagatiOn delays and conditions for the symbols on the timmg!liagrams atedeSdlbed in Tables7
ands: Refer tO Appendix D for the si:ai¥Jaril m:: iriput and QU~Ut voJtag~ wa~pim'parameters
used for measuring the sigflalpropagationddays. Figure20 shoW8the TTL and ECL.~utputfoadlng
are circuits used for measuring the ac parameters. The time measurements of TTL at 1.5 V and the
ECL mea5u~ments·are from the voltage crossing ofthe diffeten.µat·signii!s.
Symbol Definition
Specilieiuon (ns)*
Nom.
tvcp
· VOltage control pulse
tEDM
Early data ~dow margfu
-tyep-2.0
tl.m(
Late dam window margin
tvcr-2.5
*Specifications are TA=30°C, Vcc.=5.0 V and VBE=-5.2 V
Confidential and. Proprietary
Max.
25 tvcr- 3.0
tvcp- 3.0
5.39
...
Symbol·
tosv
tnuv tASV tAHv
tASV
tAHV tnsn tnHD 1:cav
1:cav tCRH
~
tllPH
tEPL tVPH
tvn
tvun tVLD
tDWH
toPL
tnPR tVPC
tVPD tcnp
tepn
Table 8 · DC024 Signal Timing Petameters
Description
Requirements(ns)
Min.
Max.
DWD setup to VCK + (+)
5.0
DWDhold to VCK+(+)
20
Al, AO setup to VCK + (+)
1.0
Al, AO hold to VCK + (+)
15
Al, AO setup to VCK( +)
10
Al, AO hold to VCK( +)
15
DWD setup to VCK( +)
5.0
DWD hold to VCK( +)
20
CLR release to VCK + (+)
25
CLR release to VCK( +)
25
CLR release to ERD-( +)
25
CLR pulse width high level
20
ERD- pulSe width high (Mode C)1
.45
ERD- pulse width low1
20
VCK + pulse width high
12
VCK + pulse width low
8.0
VCK pulse width high in diagnostic mode 18
VCK pulse width low in diagnostic mode 18
DWC pulse width high
20
DWC pulse width low
20
DWCperiod
75
VCK+/VCK- period
25
VCK period in diagnostic mode
40
CLit t6 DRC(-) propagation delay:
CL=15 pF
5.0
CL=70 pF
32
CLR to DRD(-) propagation delay:
CL=15pF
5.0
CL=70pF
33
00024·'·
Figme/Mede
18/D 18/D 18/A 18/A 18/A 18/A 19/DIAG-B 19/DIAG-B 16/A 16/A 16/A 16/A 17/A,B,C 17/A,B,C 17/A,B,C 17/D 17/A,B,C 17/D 19/DIAG-A 19/DIAd-A , . 17/D 17/D 17/D · 17/A,B,C,D 17/D 19/DIAG-A 16/A
16/A
5-40
Confidential and Proprietary
Requirements(ris)
Min.
Max.
CLR to EWD+(-) propagation delay:
Ci.=15 pF
5.0
Ci.·70 pF
30
CLR to DN-( +)propagation delay:
CL=15 pF
5.0
CL=70pF
16/A .16/A
CLR to UP-(+) propagation delay
16/A
CL=15 pF
CL=70pF,
ERD-( +) to'UP-(-) propagation delay: CL=15pF CL=70pF
17/A,B,C
DWC(-) to-UP-(-) propagation delay:
CL=15 pF
5.0
CL=70pF
VCK +(+) to DN-(-) proagation delay:
CL=15 pF CL=70pF
VCK +(+) to -TRUNC UP-(+) propagation delay:
CL=15pF Ct=70pF
VCK + (+) to TRUNC DN-( +) propagation delay:
CL=15 pF. Ct=70 pF
VCK +(+) to DRC( +) propagatio:Q. delay:
CL=15pF
9.0
Ci.=70pF
VCK +(-) to DRC(-) propagation delay:
CL=15 pF
5.0
Ci.=70 pF
17/D i17/A,B,C 17/D I i17/B
16/C
30
16/C
VCK + (-) to DRD( +) propagation delay:
CL=15pF
{o'
CL=70 pF
VCK + (-) to DRD(-) propagation delay:
CL=15pF
5.0
CL=70pF
32
twu
VCK + (+) to EWD + (+) propagation
dday
5.0
25
16/C 16/C 16/D
ConfidentJa,l~~ ~prietacy
5-41
~~M!ifllll!!"1':ll!I ll.4!·~---·---------------------~-
...
Symbbl
tEDD
tvctt
tvep
tvna
tVDF
tvnN
tvru
tvm
tvn. tDNL
tnNL-tUPL tncu·tncn
Descriptioil.
Requirements(nsl ·
Min.
Max.
VCK+(+) to EWD+(-) prop!lg!ltion
delay
5.0
25
VCK( +) to DRC( +)propagation delay
in diagnostic mode:
CL=15 pF
5.0
CL=70pF
35
VCK(-) to DRC(-) propagation delay
in diagnostic mode:
Ci.=15pF
5.0
CL=70pF
30
VCK(-) to DRD( +)propagation delay
in diagnostic mode: CL=15pF
5.Q
-
C1 =70pF
33
VCK(-) to DN-(-) propagation delay
. in diagnostic mode:
CL=15pF
5.0
CL=70pF
33
VCK( +)to DN-(-) propagation delay
in diagnostic mode:
CL=15pF
5.0
CL=70pF
30
. VCK( +) to TRUNC UP-(+) propagation
delay:
CL=15pF
5.0
CL=70 pF
40
VCK( +) to TRUNC DN-( +) propagation
delay:
CL=15pF
5.0
CL=70pF
40
UP- pulse width low
5.0
25
DN- pulse width low
5.0
25
UP- pulse to DN- pulse skew
-2.5
2.5
VCK+(-) to DRC(-) to VCK+(+)
to DRC( +} skew:
CL=15pF
-5.0
12
CL=70pF
-5.0
10
titm"
Figure)MOde
16/D 19/DIAG-A
19/DIAG-A
19/DIAG-A
19/DIAG-A
19/DIAG-A.
17/B
17/B 17/D 17/A,B,C
5-42
Confideritial and Proprietary
Symbol
VCK+(-) toriRC(-) to VCK+(-)
to DRri( +) skew:
Ci=l5 pF
-5;6
12
CL=70pF
-5.0
12
VCK+(+) toDRC(-) to VCK+(-)
to DRD(-) skew:
CL== 15 pF
-5.0
12
Ci=70pF
-.5.0
12
VCK+(+) to E\vl)+( +)to VCK+(.f..) -1.0
i.o
VCK +(+) to EWC(.-),propagation delay:
CL=15 pF
5.0
C1=70 pF
27
VCK + (+)to EWC( +)propagation delay:
Ci=15pF
5.0
Ct=70pF
25
C:LR t0 :Ewe(+) propagation delay: CL= 15.PF
Ct=70pF
5 .o
.. 2:6, '/"''"
···:~;_
CLRto DN-( :+) to CLRto UP.::.(+ )Skew .::.2.0
1 Optimum ERD +/Em- pulse width is tvcp+3,5 ns,with,no~'.Vt;;; Xll!~;t;..
2 UP+, UP-, DN +, DN- must drive matched loads of 15 pF to 7fi:pF;
3 EWD + and EWD- mustdrive matched loads of15 pF to70pF'. ·
18/A;B,C,D
18/A,B,C,D
19/A,B,C,D
!"~ -
VCK+ ERD·
UP-
ON-
Figure 15 · DC024 Read Data Capture Window Signal Timing
Confidential and Proprietary
,...,.____M'J,.,MIJz_;tR_l!t ..... i!-i?i!--!i"!il... \Afl.,..A.~-· "ii.,;.-.._._..___
li!f8r!.ll . . ...,_dlli------~~ ''°"'---~--·------~--
5-43
-
·DC024
MOOEC
MOOED
CLR DRC EWD+ ONUPOF.ID VCK+ORVCK ERO--
tcPW
tcEP tcoN tCUP
tcPO
tcRv
tcRH
MOOE A
Figure 16 · DC024 Signal Timing A
5.44
Confidential and·Proprietary
ONMOO!:SA, 1;!,C
VCK+
_
_ _
,
14 ,
-
tv
P
L
I-+-
tvPH
:I-.-.f__
_
__.Ij+
--t
v
cPI...._
_ .·:l 1 -
-
-
,
L
J .,.-. .:-.·_-.; ----+------t----------.....
D:~ ----tL
~=---.,.-.~~~'"-~
~-·~-toPL_-_ tu...-......
-
------
-~ -·~'--
- ----
ON- -'--------"--.I,
~
MOOED
VCK+OR VCK UPON-
EWC DRC
j--tvro
MODES
Figure 17 · DC024 Signal Timing B
Confidential anql?fopriewy
VCK+ORVCK .,_...._....,...__.
l...._ __,
DRC
OWD ________.Xl:+V-AtLIoD DsAvTA±::Xt,..O__H_v_:,:..;:!..._j·_--_--_-....,-..;:-_.-_-_--_--
MOOED
___ VCK+
EWC
__,
-.j !-tecu
MODES A, B, C, D
VCK+OR VCK EWC
VALID STATE MODES A, B, C, D
Figure 18 · DC024 Signal Timing C
5-46
Corifidetitial and PrOprietary
...
MOOE:DIAGNOSTIC
- - - - - - CLR -1 l-tceu ~ODES A. B. c. 0
MOOE:DIAGNOSTIC
~. ' ' - . ,-
' '-
! '
Figure 19 · DC024 Signal Timing D
Cohfidential and PrOt)tl~
""''"'"""·......................,,.,.,.,................~.......,.,....,!!ill,.,..,"".J""'""'""'"""""""""'-"""""'"""_" _,...................,._ _ _ _ _ _ _ _ _ _ ...__,__...-------···
-
-2.0 v
son
3pf
FROM c>-_....__ _...._---o TEST
OUTPUT
POINT
LOAD A: ECL CIRCUIT
TEST VCCTTL POINT
DIODES IN916
OR IN3064
LOAD B: TTL CIRCUIT
Figure 20 · DC024 Output Load Circuit
5-48
Confidential and Prqprietary
·Features
· Implements error correction code (ECC) · Accepts up to 10,060 bits of data in a 10-bit parallel form · Corrects any number of errors contained in up to
any eight of the 10-bit symbols in the data field,
fltirp · Generates 170-bits of ECC informati~n parallel fop~{
· Compares 170-bits of calculated ECC wi'tbJ,70-bits of ~'.E'CC
· Description The DC309 Reed Solomon generator fa'(:fu~fu a 28¥t>iil'<lual-inline package (DIP) and is a
:a dynamic NMOS LSI chip that implernetits Reed Soldn:Jott'~r correction code (ECC). The
DC309 accepts up to 10060 bits of of ESC init5rmation in.1Q::bi!parallel form . It contains the logic
to compare 170-bits of calculated ECC ~tion with 17Q-bjts j;>f read ECC information. This is
performed by generating in 10-bit ~ f4!tm the excl~ve-<?i remit of the calculated ECC and
read ECC. This result permits externaI,.COh'«tlon of inWUd'<bta. The algorithm is capable of
correcting any number of errors con~d'.il?- up to any . o fthe 10-bit symbols in the data field. Figure 1 is a block diagram of the DC309. · · ·
FEEOBACK AND GATES
FBE --+--+---j
Figure 1 · DC309 Block Diagram
Confidential and Proprietary
5-49
.,·:,,:. >.L. ·-
.. _
'
-~au4'~~~'
This section provides a brief description of the input and output signals and power and ground
connections of the DC309 28-pin DIP. The pin assignments are identified in Figure 2, and,
summarized in Table 1.
·
004
vcc
.,
ooi
012
016
010
006
000
008
INE
018
FBE
CLK
001
Voo
011
019
0\)3
009
013
·007
a::R
017
005
Vss
015
TOP VIEW
Figure 2 · DCJ09 Pin Assignments
5-50
Confidential and Proprietary
Table. t · DC)09 Pin and Signal Summary
10,7,13, :rjj<:9:fi> 4;15,2,18 26,20,25'·.
11,6;12, · 00 < 9:riS.
5,16,,l, 19;21,21 24 :
input tiut~ut
22
FBE
input
Data in'.< 9~0 >-Dat:tt input lines th.at receive the data inpudn 10,bit parallelform,.
· f}ilta out < 9:0~--Da'fa.·outP,Ut Jines'tluit ~s~er
170'bi,tso£10 . . . ··. (1Uby17)ECCfollowi'ng
thecid8iiL\ ·. < . ",,putda~andwh~170bits
of 1u;bi('p~clltO'bY ft)· reltd~''ltre tmnsfetted
for '. cor~&t:{ 'H\ , .\ ····.. \ · '· '·
.
,
23
INE
17
CLR
8
CLK
3
ERR
28
Vee
9
Voo
14
Vss
input
input input
outpµt
input input input
~ enable,,...,&Se.rted whend·t1t is ~i~ .for
ECt~tion:and·w~.the.£CCis.~eived fP
genera~ the. out~t.te$ldµe. ·~.· sigp~iil ~ated -when theJ~C~®.WlPs~ t4i-e EC..0 qµt. ·
>, -- " ,, ' - '- · '· · · · 'e ' · --,>jJC/.·>'(,t-'··'·>' '·. · ·' '· .,, ' ,. ii~''· ,f · ) ' ' ·
Clear-Asserted fora fulldock time to initialize the DC309 before starting any ECC process.
Clock~The tx!Ain~·~·.s~t!~ tha,t controls the 00'69 optimtiok!~ n()rmal operation, the
input Sigri~s·· ·~~··s.dtheoutputssignals are a~!f~Jeoa' the ; :.· ~e of clock signal~ T~ variati0nsambe.implemCftted.provided the switch,
~tiines ~~ spec:j~~ are ~d.
Errpr out2.A,sta!'iqt~y ~t()~ sign~ that is negated
by the dear input for initialization purposes ~d
fout# ¥ aT8hSeeJratted~hwisl;tettnr athbttf¥rwehsein~tihse
~BE,
to
sigMJ.
~!lzel.'Q· :i~.n¢'gat¢d
ittid the:fNE s~is 'a!serted.
Voltage-Power supply 5 Vdc
Voltage-Power supply 12 Vdc
Ground-Ground reference
Confllieritiafhlid 'l>foprletary
'"~
"!!f ~.-.it~ .~WI! !11!1 "Jilli:>!'"'f!'f:ll'.llR' _!WI~*""- ----·---·---~-~---------------
5-51
-
Functional Operation The DC309 contains
17
.· ·10-bit
. . register
~. ·t. ages,
..· · . ) an alpha
generat:O..r.·.·.ilnd
feedback
logic,
an
error
detector latch, and a dock generator. The registef stages·and etror detector are deftttfd by the clear signal. Atwo-phase clock output from the cfock generator is distributed toeachof th~ registers.
To generate the ECC, 10 bits of parallel data on lines DI< 9:0 > are entered through the input ANP
gates when enabled by the input enable (INE} signal. The parallel data from the input gates is
transferred thi;ough the feedback gate to the alpha generator wh(!n enabled by the feedback enable (FBE) signal. The alpha generator produces eight 10-bit alpha-terms: 'Each bit of the alpha-t:<;:rll1 is
composed of an exclusive-QR gated combination of from three to seven input bits and is OR g11ted with the register ~tputs. The results are clocked into the next register stage. This process
continues until all data words are entered. The ECC is then stored at the outputs of the 17 register
stages. The INE and FBE signals to the error detector latch are negated to shift out the 17-word
ECC register data.
To compare the internally generated ECC with an external ECC, the INE signal is asserted and the FBE signal is. negated. The internally generated ECC is shifted through the register stages and exclusive-OR gated with the input ECC. The resulting comparisondata is transferred on the data
out lines DO< 9:0> and to the error detector. The error detector output (ERR) is asserted when
the input ECC does not equal the inrernally generated ECC.
Table 2 lists the lodft levels required to select the DC309 functions.
Table 2 · DC309 Logic Function Selection
Function
Interface Signals*
DI<9i0> 00<9:0> FBE
INE
Clear
X
L
X
X
L
H
Calculate ECC
M
X
H
H
H
H
OutputECC
X
M.
L
L
H
H
Output remainder M
M
L
H
H
M
*H =High logic level, L =Low logic level, X =High or low, M =Meaningful data.
· Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DC309 are described in the following paragraphs. The test conditions for the electrical values are as follows
unless specified otherwise. Refer to Digital specification A-PS-2100002-GS for the general
specifications for integrated circuits.
· Operating temperature (TJ: 0°C to 75°C
· Power supply voltage Ned: 5.0 V ± 5 %
· Power supply voltage (Vnn): 12.0 V ±5%
5-52
Confidential arid :Proprietary
Mechanical Configu.-atioQ ...
..y .
The physical dimensions of the DC309 28-pm DIP are contained in Appendix E.
Absotute ~.RatintJs
may ·stresses gteater thad the absolute maximum ratings may cause permanent· d~ to tb1!·d®~e.
Exposure to the absolute maximum ratings for extended periods
adversely aj!~.::t;he
reliability of the de\iice. Functional operation of·the device ar these or ~er conditions~ater
than indicated is not implied.
· · '·
· PowerNupplyvoltageW.:c): 7;0 V
· Power supply voltage (V00): 14 V
· Ail other pin vol~es <YJ: ~1.0 VtolO V
· Storage temperature (T51c)~L65°C td 150°C
· Relative humidity: 10% to 95% {noncondenMg)
Cobdirions Recommended~
',·'
' ·.,
·. ,.. '
· Power supply voltage (VcJ: 5 V ±5%
.5 · Power supply veltage (V00): ... .46 V iQ-4.94\1 .
· Supply Current ~c): 75 mk (maximum)
· Supply current (lmJ: 30 mA (maximum)
de Electrical Characteristics
The de electrical parameters of the DC309 for the operating vo}tagi';;ancLtempetat\lre ranges
specified are listed i,nThble 3. Refer t;oA~·G for:the~t&cnitconf~ refetencetfin
Table3.
,
Cohfidentiabmd·Pmprietary
5.53
Parameter
High: level fuput wltage
Low~fevel
input roltage High-level output voltage
Low-Input output wltage
High-level input current
· Low"level input current
Short-circuit output current
Supply current
OC309
Table 3 DC309 de lnJ>.Ut and ,.. '
~
'
·' ;
,. -,
'
' ' " ' -- ~ .; ' ' ' - -
Ou~t -· '
. '
"
Par.~a' m' ~
Symbol Test Condition Requirements
Min. Max·. ,
Vm
2.0
Units
v
Vu.
0.8 v
VoH
Vcc=4.75 V
Io=-50 µA
VoL
Vcc=4.75 V
lo=2mA
Im
Vcc=5.25 V
V1=5.25V
I1L
Vr=0.8V
Vcc=5.25 V
las
Vcc=5.25 V
2.4
v
0.45 v
--10
10
-10
10
µA
-25
.:..65
mA
Test Circuit Cl Cl Cl C.2 C4 C5 C6
lee
Vcc=5.25 V
Inn
Von=12.6 V
75
mA
C7
30
mA ., C7
K Electrical Characteristics Table 4 lists ac timing parameters for theinput and outputs signals shown in Figures 3 and 4. Figure 3 shows the setup and hold timing sequence and Figure 4 defines the propagation delays for the input and signals. The symbols referenced in the figures and tables are defined in Table 4. The output load circuit used for the ac measurements is shown in Figure 5. Refer to Appendix D for the input and output voltage waveform parameters used for measuring the signal propagation delays.
5-54
Confidential and Proprietary
CLOCK {CU<l _
----.-~-· __,Jll<f-k-=-----tcui--
_::-_--tCLL::::::.::}_______ :
I
I
.·.·_·________ ._,)E CLEAR (CLRl _______
~··:f ~K
lV
I
M· '
ov
INPUT ENABLE (INE}
3V I
I
·>E·bs::f:11:j(~..~-
---------·-·-····.··· . ·r· --------ov
I
)f I
FEEDBACK ENABLE (FBEJ_ _ _ _ _ _ _ _ ~sf:~j(-------- lV
'I, ,·· . --------OV
______:: t
I'
)tr~r~sr"""· OATAIN(Dl<9:0>) ________·..·...
Figure J · DCJ09 SetfJfiaizdHoul.Signa!Timing
,~..,_lllI'IJJ,....,..,._..,,.,_,...,.,,.._.,..,_....,......,..,..,,.,.u,,..19.,.na""'"'"""""""'_ _ _, - - - - - - - - ·
'5-55
-
CLOCK (CLKI
v.,.----,-------r-------- .IS. INPUT ENABLE
II
UNE) ---+-·_____
PIDO ---~.
3V
ov
DATA OUT (00<9:0>)
I
I
!
:
------~.~"'Ii ll"'.·f-------lPCLDO
.._________ :::
CLOCK AND INPUT ENABLE TO DATA OUT
3V
DATA IN (00<9:0>)
>K
ov
I
I
I
DATA OUT (01<9:0>)
I·
lPDIDQ
~
VoH Vol
Note: Input enable INE is high.
DATA IN TO DATA OUT
CLOCK (CLK)
-1 ~=R
o
u
r
-~...------VoH
_ . tPCLE
-·
·
---------------Vol
CLOCK TO ERROR OUT
Figure 4 · DC309 ac Signal Propagation Delays
Confide:htlal and Proprietary
-
Symbol
fcvc
tPCLDO
Tsble 4 · DC309 ac Signal T'miing Parameters
Definition*
~ts.(ns}
Min. Mn.·
c~ cycle time
100,000
Clock high time
Clock low time
75
Input enable setup time
30
Feedback enable setup time
40
Data input setup time
45
Clear setup time
··' 115
Input enable hold time
25
Feedback enable hold
35
Data input hold time
50
Clear hold time
Clock to output data propagation cielay
30
200
Input enab~ to otitput
125
data propagation delay
Data input to output
80
data propagation delay
Clock to error
160
propagation d~y
Clear to error
160
propagation delay
*All time measurements .shall be made from the. ~,5,Y~ of1~111JP~priate signals. Input rise
and fall times shall be 15 ns maximum meaSured at the 10% and 90% levels. Valid output data
prior to low-going transition must remain valid for a minimum of 30 ns after the clock transition.
FROM OUTPUT
T.!;ST
POINT
.I/Cc
ALL DIODES IN916 OR IN3064
Figure 5 · DC309 ac Load Circuit Confidential and Proprietary
· Typical Application Figure 6 shows a typici.tl appUcation of the DC309. During a media write sequence, data is read
from main memory, an ECC is calculated, and the data and ECC are written into the serial memory.
During the following read-back data sequence, the data and ECC are read from the serial memory, and an ECC is again calculated from the da.ta read. If the ECC that accompanies the data read is
different from the calculated ECC, an error condition is indicated.
PROCESSOR
MAIN MEMORY
DC018 SERI A LIZER/ DESERIALIZER
SERIAL MEMORY
MEDIA
DC309
ERROR OUT (ERR)
Figure 6 · DC309 Typical ECC Application Block Diagram
Figure 7 shows the timing sequence for clearing the DC309, for calculating the ECC, and for transferring the ECC output information during a write operation. Figure 8 shows the timing sequence for clearing the DC309, for calculating the ECC, and for transferring the ECC output information during a read operation.
5-58
Confidential and Proprietary
-
16,RES R1E7S ....__ __
r- tPClf.,
Figure 7 · DC309 Typical Read Operation Signal Timing
Confidential and Pr<>prietaty
-
DC.Jtl9
CLK
DATA IN VALID
INE
FBE
DATA OUT VALID 00<9:0>
Figure 8 · Typical Write Operation Signal Timing
During a media write sequence, 16 bits of parallel data read from main memory are transferred to the serializer. The data from memory can be transferred in blocks consisting of up to 10,060-bits. The serializer converts the parallel data to serial data and transfers it to the serial memory. The parallel data is also converted into 10-bit parallel symbol form and transferred to the DC309. The DC309 generates an ECC from the data received and transfers the ECC to the serializer where it is transferred to the media.
During a read-back operation following the write operation, the serial data and ECC from the media are read and transferred to the deserializer. The data read is changed into a 10-bit parallel symbol form and transferred with the ECC to the DC309. After all the data is read, if the data is the same as previously written, the 170 bits of ECC will be the same. The DC309 generates the exclusive-OR function of the 170 bits of read-back ECC and the 170 bits of recently calculated ECC and the results (residue) are transferred to the main memory.
The DC309 checks the 170 bits of residue 10 bits at a time for all zero content. If the residue is all zeros, the read-back ECC is equal to the calculated ECC and no data errors are indicated. If the residue is not all zeros, the read-back ECC was not equal to the calculated ECC and the 170-bits of nonzero residue allow external mathematical calculations to correct any errors contained in any 8 of the 10-bit data symbols. A resulting error indication is transferred to main memory where it can be used to correct certain types of errors if required.
,,._60
Confidential and Proprietary
· Section 6-Gene:ral Purpose. Devices
The general purpose devices facilitate the development of pux:essor interfaces for the control and transfer of information from processors to memory and other devices.
DC022 16-Wbnl by 4-Bit Register File-The DC0.22 is a 28-pin DIP device that provides two independent read/write ports to allow simultaneous asynchronous access to a register file from
either port. DC102 Eight Channel Equals Checker-The DC102 is a 20..pin DIP that provides eight dual-input channels used to compare data in pairs for equality. DC301 Dual Baud Rate Generator-The OC301 is an 18-pin DIP that provides program selectable baud rates (50 to 38,400) and separate transmit and receive frequency outputs to control the transfer of serial-line information.
Confidential and Proprietary
------------------·---·-------
· l\voindependent read/write ports
· lOk series, ECL compatible input/output port capable of dti~ins 15Q·l9~s · TU input/output port capable of sinking 20 mA in a low state · ECL and TIL address decoder and bidirectional data buffer
· Desctipti.00. .
The DC022 register file, contained in a 28-pin dual-inline package (DIP), provides storage for up to 16 4-bit words and two independent read/write ports that allow simultane<>Us asynchronous access to the register file information from either port. Figure 1 is a simplified block diagram of the DC022.
ITTm'n'
wmr.T
AO-E
SEl.O SELi
SELO Sf LI
AO-T
,"n..' SEL2
SEU :,.l.
A1-E
>
0
SEL3
0:u
)>
AH
SEl.3
0
,~,.,
m
A2·E
""m0'' 8 m,0,
· · ·
I
I I
' I
· ··
A3-E
· I I
·
I
· · · · · · · · ·
~
g ~
A2·T
· ,m,
· A3-T
SEL15
SEL15
~
li1'iEITT
Figure 1 · DC022 Simplified Block Diagram
Confidential and Proprietaty
6-1
----,.--·---~----~---·-~-----·----
'
:'->- >..- .
'
----
' -··-- ,,_,-,,
,
'~eldata is ~j\sf~<ho lltld from the filet~µshf6ur~s cifbidirectio~at,data lines, one set
for each port. Each port receives address inputs and read and Write enable lines. One port has ECL
lOk series macrocell arrays (MCA) compatible inputs and data outputs capable of driving}5 µA
loads. The remaining port has TTL compatible inputs and outputs and is capable of sinking 20
milliamperes in the low state. A location in the file can be written from either port by specifying the
address on the address inputs, negating the read enable input, transferring the data to the input/
output lines, and asserting the write enable input. A kx::atiori £tom the file is ~ad from either port
by specifying the address at the address inputs and by asserting the read enable input while the
write enable input is negated.
· Pin and Signal Description
This section provides a brief description of the' input and output signals and power and ground
connections of the DC022 28-pin DIP. The pin assignments are identified in Figure 2 and,
summarized in Tuble 1.
·
02-T 03-T
A2-T A3-T
GNO
VEE
WREN-£
Vee GNO 03-E GNO
TOP VIEW
Figure 2 · DC022 Pin Assignments
6-2
Confidential and Proprietary
1Able 1 · DC022 P'm and Signal Summary
Pin
22-19 9
13-18 6-3 24
A<3:0 >:-E
WIIBN-E
RDEN-E ti <3 :O >~E
inputs'
ECL address bits <.3:0> .,.,.,Bits·} ~.Oofihe ECL
wrt addrells·
ECt ~fit~ etiab~~Wben ll$sert&i;· fy<>fu the ECL
data liheS · <::~!Q;~( · ~tt1eh << .... ~~th file
· Uid', thli Ittt addtltS'~·Bits <3!'0>.
tile · µte~s· tli~~tt present.
1,, ,,.
.'_ ,,.,~ '
·'. ,\',·,_ ''·"' c;C-'·:,, 'i'·-·-~ _,/_,'!
·"
£CL :teadii.enable~·Cdntcnts . o£ ,th~ ·l'eRister file
·. lbcatic:u.'I.:spdiedhhy.~L a~~,<3:0>...is
tran&fened·t:o'the:ECJ::1da.t.lfu.e!..<J,o> ·
inp~ts1/output~.2 . EC:LJl~t~~s' ~ j1(y'j..' Bidi1'ectif)nai lip~ $ ~ugh
Ol>f t~ !CI::PP.tt aa~wi~ the'~tt;~~fdUb\vet driv'ets
etiabled{JYfmJ!~,'f!:~~n~L'
'
'< p
'
., '· , ' ;';_;' , , ; · ·, J· ' - ,. I ' . ' " "·; i · '. / , ·: , ,_ · ' ' ,
, ·
·· ~ . ' ''' . ' ' ·" '· · , ' '~· ,. " , :. o
t'J:l.~(f~s,b~t, ~~;q~,,_Bfi,~~ ~o 9fttre !TL
port ad<kess. ·
·
inpue ·
m ~i~ ~nableS'Wht?ii ·asserted, data. on the m..
data inputs<3:0> is written to the reg~ter file l&a: tlon specified by the TU address bits< 3:0 > . When
negated, the location retains the data p~m.
25 RDEN-T
.(f'lfL. ~!~\>le!"":'"~. ·~®teq;fs.:of :the,~ter.. file location specifim ~;j~ '.CT~1~s lines.<3:0 > is transferrced:rotf!fLdati'lines <a.:;O:? ·thro'!.Jlh.Uie tAA:e·
state drivers.
2,1, 27,26
23
8,11
D<3:0>-T
inputs3/outputs4 input"·' input"·1
TTLdatalines<3:0:>.~Bic,ll~j~l~}l:~O
oftheTILdata PPtt 'With t~-~~tt ~yers enabled by
RDEN,T signal.
.. . . . . . ..
out- Voltage..i.PCJ'.Wer supPlf voltage fo Ttt.fuput and.
put buffers.
Voltal!e-Pow~ si,ip~y vol~e trilhe~ f~t:t:h. ECt'' output buffers: afidassociated interb1:iflbgic~ .
7,14,28 GND
input'·1
1ECtlevels 2Emitter folfower drivers 'TIL levels
4'Turee-state 'Pins 7, 12, 14, 17, and 28 connect to networkgroun:d (GND).
6Pins 8.and 11 connect to VBE· Piri 23 connects toVcc. . · 1The power and ground pins must be connected externally to the specified ~and gt'OUI'ldplane.
Confidential and Proprietary
6-3
·-
·Operation
a: The DC022 consists of an ECL and. TJ'L ado/e~s decoder, an Ec;L jlnd TTL bidirec~ional data
buffer, and a 16 word by 4-bit array lai:ch. The TTL bidirectional'buff tWtsfers data between the.
three-state data bus and the arraylatch. When the read enable RDEN"T signal is asserted, the data
from the array latch is transferred to the three-state TTL data lines D < 3:0 > -T. When the read
enable signal is negated, the three-state output buffers are in a high impedance state. The ECL
bidirectional dat11;.buffer tra~fers data between the 25 µA emitter OR gate type data bus and the
array latch. When the read enable RDEN-E line is asserted, data from the array latch is transferred
to the ECL datl,l. lines D < 3:0 > ~E. Whe~ the ~ad enable signal is negated, the ECL data lines are a
high-impedance state. The TTL address decoder decodes the four TTL address bits A< 3:0 >-T to
select one of the 16 4-bit words in the address latch for a read or write transaction. The 16 words are
accessed through the 16 TTL address decoder and 16 ECL address decoder select lines. The TTL or
ECL input data from the bidirectional data buffer is written into the location selected by the TTL or
ECL .address bits when the write enable (WREN-Tor WREN-E) lines are asserted. Data is read
from the array lat'*1 and transferred to the TTL.or ECL bidirectional data buffer by selecting the
pi-oper word through the appropriate TTL or ECL ad(:iress bits. The dual select lines, data paths,
and read/write controls allow simultaneous and independent operation of the TTL and ECL ports
for any rombination of read/write transactions. Simultaneous write operations from the two ports
to the same word location, however, will result in undefined logic states for the addressed word.
Simultaneous read and write operations to the same. location will cause the data read to Pe the same
as the data written.
.
· Specifications
The mechanical, electrical, and environmental characteristics and specifications for the DC022 are' described in the following paragraphs. The test conditions for the electrical values are as follows unless specified otherwise. Refer to Digital specification A-PS-2100002-GS for the general specifications for integrated circuits.
· Operating temperature (TA): 0°C to 75°C
· Supplyvoltage(Vcd: 5.0V ±5%
· Relative humidity: 0 to .95% (noncondensing)
Mechanical G~nfiguration
The physical dimensions of the DC0.22 28-pin DIP are contained in Appendix E.
Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device. Exposure to the absolute maximum ratings for extended periods may adversely. affect the reliability of the device. · Positive supply voltage (Vcd: -0.3 V to 7.0 V · Negative supply voltage (VEE): -8.0 V to 0.3 V
· ECL input voltage (V1o): 0.3 V to VEE · · TTL input voltage (V,.):-0.5 V to 7.0 V · Relative humidity: 10% to 95% (noncondensing)
6-4
Confidential and Propri~tary
-
· Supply voltage <Vcd: 4.75 V to5.25 V<Vr.E): -5.46 V to -4.94 V
· Supply current (led: 425 mA (maximum)
· Operating temperature (TA): 0°C to 75°C · Linear air flow 500 feet/minute (minimum)
de Electrical Charaeteristics
The de electrical parameters of the DC022 for the operating 'voltage and temperature ranges specified are listed in Thble 2. Re{er to Figures 3 and 4 for the ~t cil'Cui~ configurations referenced in the Table 2. Table 3 lists the conditions that apply to the ti~t. cinii.tits.
Parameter High-level input voltage
Low-level input voltage
neon·· Table 2.
EledriCal·~
Symbol Test Conditionsl,S
~~~
VIH D<3:0>-T A<3:0>-T WREN-T RDEN-T D<3:0>-E A<3:0>-E WREN-E RDEN-E 0°C 25°C 75°C
VIL D<3:0>-T A<3:0>-T WREN-T RDEN-T
2.0
.5,25
-1.14,. -1.105 -1.405
-0.P
Units F~
v
3/A
3/B
v v v
v
3/A
3/B
D<3:0>-E A<3:0>-E WREN-E RDEN-E 0°C 25°C 75°C
3/A
-2.5 -1A9 v -2.5 -1.475 v -2.5 -1.45 v
Confidential and. Proprietary
6-5
-
i.:>ar.meter High-level
input current
Low-level input current
Input clamp voltage Input current at maximum input voltage
Symbol Test Conditions1"
Im
D<3:0>-T
V1a=2.7V
A<3:0>-T WREN-T V1n=2.7V
RDEN-T V1n=2.7V
D<.3:0>-E V.;,=V1Hmax
A<.3:0>-E WREN-E RDEN-E V..,,=V1Hmax
IIL
D<3:0>~T
A<.3:0>-T
WREN-T
V.,==0.5 V
RDEN-T V..,,=0.5 V
D<3:0>-E V.,=-2.0
A<3:0>-E WREN-E RDEN-T Vin=-2.0V
Vrc D<.3:0>-T A<.3:0>-T WREN-T RDEN-T l..,,=-18mN
JIM
D<3:0>-T
Vo.=7.0V
A<3:0>-T
WREN-T
RDEN-T
V1a""7.0V
Requttetrients · Min. Max.
0 . 100
0
20
l>co22
tJnits F~··
µA
3/C
µA
0
50
0
.300
0
200
µA
µA 3/D
µA
3/D
-500
0
µA
3/C
-400
0
µA
-200
0
µA
-800
20
µA
3/D
0
20
µA
-1.2
0
v
3{E
0
300
0
100
µA
3/C
µA
6-6
Confidential and Proprietary
...
Parameter
High-level
outpµt voltage
Symhol Test Conditions1·'
Voo D<3:0>-T
L..=-2,6mA
D<3:0>-E 1-=40mA L=50mA QPC 25°C 75°C
Low-level
Vo-..
output voltage
D<3:0>-T L=-20.0mA
Low-level IoL
output current
D<3:0>-E
V.,..=~2.-0V
Short circuit Ios
output current
D<3:0>T4
Positive power Ice
supply: current
Negative power I,!E supply: current
ooozz
ReqWreinents Min. Max.
2.4
Units Figure/Test
v
3/B
3/A
-1.0 -0.84 v v .,-0.96 -0.81 -0.9 -0.72 v
0
0.5 v 3/B
-800
.20 '.·
µA
3/A
-40 ..100
mA 4/F
0
45
mA 4/G
-400
0
mA 4/G
1All inputs .mustbe at the voltage levels ~pecjf~ed ¥1 achiey~ the,desired logic state. Open inputs will
result in undefined logic states being propagated through the device. All voltages are specified with respect to network ground.
20n a transient basis, Vn (min.) for TTL inputs is considered to have a value equal to the input clamp voltage (V1c) as measured for the device under test. The device must meet functional requirements when any combination of inputs is subjected to a V1c transient of up to 100 nanoseconds.
'The duration of the specified input current CL..) on a TTL input for the input clamp voltage (V,c)
test must not exceed 1.0 milliseconds.
4All TTL outputs must meet all de and ac characteristics after the application of ground for 1.0
seconds. Only one output may be shorted to ground at a time.
1The definitions of input and output voltage and current parameters apply to both TTL and ECL inputs and outputs unless stated otherwise.
Confidential and I>n:>prietary
6-7
-
DC022
Table 3 · Dc022 de Test Circuit Conditions
Figure/Test Condition
3/A,3/B
Each input is tested separately. The test requirement must be met with other inputs at
any voltage within the range specified and for any voltage within the range specified
for Vn, or Vm. Pins D<3:0>-E are terminated to -2.0 V through a 250 resistor ·for
input test.
3/C
Each input is tested separately. To test D < 3:0 > -T, RDEN-T must be driven by a high-
level voltage and the input currents specified must be met over the range of Vrn
specified fo~ RDEN-T.
3/D
Each input is tested separately. To test D<3:0>-E, RDEN-E must be driven by a
high-level voltage and the input currents specified must be met over the range of Vm
specified for RDEN-E.
3/E
Each inputis tested separately. To test D < 3:0 >-T, RDEN-T must be driven by a high-
level voltage and the input currents specified must be met over the range of Vm
specified for RDEN-T.
.
4/F
Each inpht is tested separately. To test D < 3:0 >-T, RDEN-T must be driven by a low-
level voltage. The short circuit currents (los) specified must be met over the range of
Vm specified for RDEN-T.
Each input is tested separately.
4/G
1. The power supply currents may not exceed the limits specified for any combination
of input logic levels.
2. The total power dissipatioh will increase when the outputs are connected to loads.
6-8
Confidential and Proprietary
Vee
Vee
Vee
VE£
VtH. V1L
00-T 01-T 02-T 03-T
AO-T A1-T A2-T A3-T
WRE;;;::T
00-E 01-E 02-E } VOH, V01., loi. 03-E
AO-E A1-E A2-E A3-E
V1H, Vil
V1H- RDEN-T
v.. - WREN-E
DC022
Vn.- Ri5EN-E
GNO
=
CIRCUIT A
l1L.liH. hM
Vee
Vee
l 1
00-T 01-T 02-T 03-T
AO-T
Al-T A2-T
A3-T
l7imN-T
~
OC022
GND
1
CIRCUIT C
V1H,V1L
00-E 01-E 02-E 03-E
Ao-e
AH!
A2-'E
A3-E
~.
t>o-r
01-T
[?2-T
00-T
VOHVCJI_
}···· AO-T
AH A2-T
A3-T
Vt1- RDENOE
Vt1- WREN-E
DC022
Vt.- fiN-T
GNCl
CIRCUITS
v
Vte
00-E 01-E
02-E 03.,E
AO-E
A1.S A2-E A3-E ~ ROEN'E
OC022
GND
CIRCUIT 0
Figure 3 · DC022 Test Circuits
Confidential and Proprietary
6-9
VeE
00-T 01-T 02-T 03-T
Vic AO-T llM A1-T
A2-T
A3-T
WREN-T ROEN-T
DC022
GND
CIRCUIT E
REFER TO TABLE 3 NOTE 1 FOR TEST CURCUIT GINPUTS
Vee
+Ice
Vee +lee
AO-T A1-T A2-T A3-T
00-T 01-T 02-T 03-T
AO-E A1-E A2-E
A3-E
00-E 01-E 02-E
03-E
WREN-T
imm:T
WREN-E
ADEN-E
OC022
GNO
OPEN
-=
CIRCUIT G
Figure 4 · DC022 Test Circuits
DC022
Vee
00-T 01-T 02-T 03-T
los
1
DC022 GNO
CIRCUIT F
ac Electrical Characteristics Table 4 lists ac timing parameters for the input and outputs signals shown in Figures 5 through 9. The symbols referenced in the figures and tables are defined in Table 5. The TTL and ECL output load circuits used to measure the ac signal parameters are shown in Figure 10. Refer to Appendix D for the input and output voltage waveform parameters used for measuring the signal propagation delays.
6-10
Confidential and Proprietary
DC022
Symbol
Table 4 · DC022 ac Parameter Definitions
Address access time-The time between the specified references on the address input
and data output voltage waveforms with the output changing (rom one defined level
(high or low) to the other defined level. (Read enable is asserted and write enable is
negated.)
Data access time-The time betweT11 the specified referepces on. the .data input
voltage waveforms of one port arld the data output 'Voltage waveforms of the other port
(high with the output changing from ~me defined level
or low) to .the other defined
i!ie level. The first mentioned port is set up to write array lat~ (Write enable is
asserted and read enable is negated.) The secondpOrt is set up to r,eadth,e array latch
(read.enable is asserted and write enable is negated), and l;>oth ports are set up to access
the same location in the arraylatch.
·· ··
Write access time-The tim~ between the specified reference poi.rlts on the write enable ioput voltage waveform'6f one port and the dataou~put voltage waveforms of
the other port with the output changing from one def~ned level :(high or low) to the other defined level. The first mentioned port is. set up· to write the array latch. (read
enable is negated and write enable is in the process of being asSert:ed). The second port
is set up to read the array latch (read eruibleis asserted aDcl write enable is negated), and both ports are set up to access thi;: sa,m~ location in the array latch,
Output enable time-The propagation delay tiniebetween the.~ified reference
points on the read enable input and the data output voltage waveforms \Vith the output
changing from the high-impedance (off) state to either of the defined active levels
(high or low). For the three-state TTL outputs, both the high aDcl low levels are active.
For the openc.emitter ECL outputs, only the high level is active.
·
Output disable time-The propagation delay time bet:\Veen the specified reference points on the read enable input aridthe data output voltage waveforms with the output changing from either of the active levek(high or low) to the high-impedance (off) state. For the three-state TTL outputs, both the high and low levels are active. For the
open-emitter ECL outputs, only the high level is active.
Address setup time-The time interval between the specified reference points on the address input and write enable input waveforms that defines the earliest point in time that the address inputs must assume stable logic states with respect to the write enable input pulse. The logic levels at tbe address inputs must remain stable between the points in time defined by the address setup and hold times to ensure proper transfer of logic levels at the data inputs into the array location specified by the address without affecting any other location in the array.
Address hold time-The time interval between the specified reference points on the write enable input and address input waveforms that defines the latest point in time that the address inputs must maintain stable logic states with respect to the write enable input pulse. The logic levels at the address inputs must remain stable between the points in time defined by the address setup and hold times to ensure proper transfer of logic levels at the data inputs into the array location specified by the address without affecting any other location in the array.
Confidential and Proprietary
6-11
-
oco22
Symbol Name/Definition*
t0s
Data setup time-The time interval between the specified reference points on the data
input and write enab]e input waveforms that defines the earliest point in time that the
data inputs must assume stable logic states with respect to the write enable input pulse.
The logic levels at the data inputs must remain stable between the points in time
defined by the data setup and hold times to ensure proper transfer of logic levels at the
data inputs into the array location specified by the address.
toH
Data hold time-The time intervalbetween the specified reference points on the write
enable input and data input waveforms that defines the latest point in time that the
data inputs must maintain stable logic states with respect to the write enable input
pulse. The logic levels at the data inputs must remain stable between the points in time
defined by the data setup and hold times to ensure proper transfer of logic levels at the
data inputs into the array location specified by the address.
tWP
Write pulse width-The time interval between the specified reference points on the
leading and trailing edges of the waveform that must be applied to the write enable
input to ensure proper transfer of logic levels at the data inputs into the array location
specified by the address.
tll
Rise-time-The time between a specified low-level voltage and a specified high-level
vol~e on a waveform that is changing from the low level to the high level.
tF
Fall-time-The time between a specified high-level voltage and a specified low-level
voltage on a waveform that is changing from the high level to the low level.
C.
Input capacitance-The capacitance measured at the specified pins with power
applied to the device.
R.
Real input impedance-The real portion of the input impedance measured at the
specified pins with power applied to the device.
*The definition of the input and output voltage and current parameters and the timing parameters apply to the TTL and ECL ports unless stated otherwise.
6-12
Confidential and Proprietary
....
Symbol t.v. to11 tw11 to11
t11s
Table 5 · DC022 ac Electrieal Characteristics
Definition
Load <C.J Requirements (ns)
Min.
Max.
Address access time1
A<3:0>-T input to
15pF
2.0
30
D<3:0>-Toutput
50pF
2.0
30
150pF
2.0
40
Address access time:
A<3:0>-E input to
30pF
2.0
30
D < 3:0 >-E output
90pF
2.0
30
Data access time'
D<3:0>-Einput
15pF
6.0
30
D<3:0>-T output
50pF
6.0
30
150pF
6.0
33
Data access time4
D<3:0>-T input
.30 pF
6.0
30
D<3:0>-E output
90pF
6.0
30
Write access time'
WREN-E input
15 pF
6.0
32
D<3:0>-T output
50pF
6.0
32
150pF
6.0
36
Write access time'
WREN-1' input
30pF
6.0
32
0<3:0>-E output
90pF
6.0
32
Output enable time
RDEN-Tinput
15 pF
5.0
22
D < 3:0 >-T output
50pF
5.0
22
150pF
5.0
28
RDEN-E input
3.5pF 5.0
22
0<3:0>-Eoutput
30pF
5.0
23
90pF
5.0
25
Output disable time
RDEN-1 input
15pF
3.0
20
D<3:0>-Toutput
50pF
3.0
20
150pF
3.0
40
RDEN-E input
3.5 pF 2.0
D<J:O>-E output
30pF
18
90pF
20
Address setup time7
A<J:O>-T input8
5.0
A<J:O>-E input'
8.0
DC022 Figure/Level
5/TTL 5/ECL 6/TTL 6/ECL 7/TTL 7/ECL 8/TTL 8/ECL 8/TTL
8/ECL
9/TTL 9/ECL
Confidential and Pniprietary
6-13
Symbol
C., R;.
Del'mition
Load (Ci_)
Address hold time' A< 3:0 >-T input8 A<3:0>-E input9
Data setup time' D<3:0>-Tinput8 D<3:0>-E input9
Data hold time7 D < 3:0>-T input8 D<3:0>-E input9
Write pulse width7 WREN-T input8 WREN-E input'
Rise time'0 D<3:0>-Toutput
D<3:0>-E output
15pF 50pF
3.5pF 90pF
Fall time" D<3:0>-Toutput
D<3:0>-T output
15pF 50pF
3.5 pF 90pF
Input capacitance D<3:0>-T= 10 pF (max)12
A< 3:0 >-T =10 pF (max)
WREN-T =10pF
RDEN-T = 10 pF (max)
D < 3:0>-E=10 pF (max)u
A<3:0>-E=8 pF WREN-E=8pF RDEN-E=8pF
Real input impedance'· D<3:0>-T=OO A<3:0>-T=OO
WREN-T=OO RDEN-T=OO D<3:0>-E=00 A<3:0>-E=00 WREN-E=OO RDEN-E=On
Requirements (ns)
Min.
Max.
8.0 9.0
11.0 3.0
12.0 18.0 19.0
18.0 15.0
3.0 8.0
1.0 5.0
1.0 8.0
0.5 4.0
DC022
Fagure/Level
9/TTL 9/ECL
9/TTL 9/ECL
9/TTL 9/ECL
9/TTL 9/ECL
6-14
Confidential and Proprietary
1WREN-T and WREN-E = Vm, RDEN-T =V1L, A< 3:0 >-E are stable. 2WREN-T and WREN-E =Vm, RDEN-E =V1L, A< 3:0 >-Tare stable.
3WREN-T and RDEN-E=Vm, RDEN-T ahd WREN-E=V1L, A<3:0>-T and A<3:0>-E are stable with the same address.
4WREN-T and RDEN-E=V1L, RDEN-T and WREN-E=Vm, A<3:0>-E and A<3:0>-T are stable with the same address.
'WREN-T and RDEN-E =Vm, RDEN-T= V1L, D< 3:0>-E are stable, A< 3:0 >-T and A< 3:0 > ·
E are stable with the same address.
'WREN-E and RDEN-T=Vm, RDEN-E=V1L, D<3:0>-T are stable and A<3:0>-T and A<3:0>-E are stable with the same address.·.
1Setup times, hold times, and input pulse widths are specified as minimum values and represent the
requirements imposed by the device oil the input signal timing re,lationships.
8RDEN-T= V111·
'RDEN-E =Vm.
10For D < 3:0>-T, the rise time is measured from 0.8 to 2.0 volts. For D< 3:0>-E, the rise time is measured from -1.5 to -1.1 volts.
11For D<3:0>-T, the fall time is measured from 2.0 to 0.8 volts. For D3:0-E, the fall time is measured from -1.1 to -1.:5volts.
"Capacitance is measured at the D <3:0> -T pins with· the three-state buffers disabled. The
requirement specified mu5t ,be mef for ah V1H applied to the RDEN-T input that meets the
requirements of Thble 2.
°Capacitance is measured at the D < 0:3 > -E pins with the emitter follower outputs in the off
state. The requirement specified roust be met for any Vm applied to the RDEN-E input that meets
the requirements of Table 2.
· ·
. ·
1·This parameter specifies the real portion of the input impedance to be positive for all frequencies
that will ensure that the device will not cause oscillations in a system environment.
Confidential and Proprietary
6-15
...
A<3:0> -T D<3:0> -T
A<3:0> - E D<3:0> - E
TTL OUTPUTS ECL OUTPUTS
0<3:0> - T. - E
0<3:0> - T. - E NONMONOTONIC INPUTS
Figure 5 · DC022 Address Access Timing
Dt.022
6-16
Confidential and Proprietary
---e. 0<3:0> _E
---1._3_V_tD_A_~-.-.--_-_-_-_-_:~
0<3:0> -T
--· 1.5 V TTJ...OUTPUTS
0<3:0> · T
0<3:0> -E
ECL 01JTP!JTS
0<3:0> - E. - T 0<3:0> - T. - E
~VV\/V\/VVV,..._,.......,...,....,...,..-----------~~~H
=~':.":~·" ·.·:'.·~" "·:·:·-·:· -··=to-·=A-·:·-·:· /V\A/\/V\A/\. ..:.".'"··=.·.·:.··."""·.:..·.:........ .
·-·=·.
.,.·
:·-V·=:A~=:U~:D_V:_A:_L-l:D:_-:-=_:
NONMONPTONtc INPUT$
Figure 6 · DC022 Data Access Timing
Confidetrtialand PropHetary
6-17
DC022
0<3:0>-T
TTL OUTPUTS
0<3:0> - E
----------vlH
I"- --1.5 -v
V1L
!----twA-J-
---1.3 v
ECL OUTPUTS
XXX WREN-E. - T
HIGH
LOW
...,xxx....,..,~-- H
0<3:0> - T, -E .x.x..x.x..x.x-.x.x..x-:~r~nr-x.x_...IW~VAA-L-ID1~~~~~~L
NONMONOiONIC INPUTS
Figure 7 · DC022 Write Access Timing
6-18
Confidential and Proprietary
-
0<3~<»-TK-·~s~v-~5jV·S>·Mv<l/S·-~ ~ ~- - -:~:~·~.~V
.S.1 CLOSED,
\
. .
. .. . .
.. Vex
S2 OPEN--
_t_·-1.S. S2 CLOSED. . ..
. _ S1 OPEN-
... V
0<3.0> T
v:. . . . y
\ _____________
0.5 V
\;
_ 1.5 v
SIANIJS2CLOSED ---0.0V
TTL OUTPUTS
0<3:0> - E
-1.3V
~~1
-----VJH --·1.3 V
t ..~·-· Vot
-1.3 v
---1.3 v
ECL OUTPUTS
RDEN-T, - E 0<3:0> - T, -E
HIGH IO£ (MAX)
tO£ {MIN
H l too (MAXI
too {MINI H
L
Figure 8 · DC022 Enable and Disable Signal Timing
Confidential and Proprietary
6-19
-
· DC022
0<3:0> · T _____~X·-t1os.5~Vt~~¥~:----1=.5=~========::
A<3:0> -T
---1.3 v
'------'----------------- ------- --------V1L ECL PORT
0<3:0> - T. - E A<3:0> - T, - E
WREN -T, - E
Figure 9 · DC022 Write Sequence Timing
6-20
' COnfidentialand Proprietary
-
TEST POINT
FROM OUTPUT
S1
DIODES IN916
OR IN3064
"Ct INCLUDES PROBE CAPACITANCE Load A TTL Circuit
FROM
TEST
OUTPUT > - - -.......---.--<>POINT
25 !l
- 2.0 v
·Ct INCLUDES PROBE CAPACITANCE Load B TTL Circuit
Figure 10 · DC022 ac Output Load Circuits
DC022
Confidential and Proprietary
6-21
·Features
· High-speed, 8-channel equals checker function · TTL compatible inputs and output
· Description
The DC 102 equals checker, contained in a 20-pin dual-inline package (DIP), provides eight dualinput channels to compare data in pairs for equality. The equals checker output is a low level when any one or mo~ input pairs are not at equal logic levels. Figure 1 is a simplified logic diagram of the DC102.
INOA(1l--'\ INOB (2) ___}. IN1A (3) --'\ IN18(4)--J
IN2A (5).--' IN2B (6)--J
IN3A (7}--'\
IN3B (8)--J IN4A {12)--'\ IN48 (13)--/ E IN5A (14)--'\ IN5B (15)--/ F
IN6A (16)---\
IN6B (17) ___J
IN78 (18)----\
IN7B (19) ___J
NOTE: Numbers in ( ) Denote Terminal Numbers.
(9) OUT
Figure 1 · DC102 Simplified Logic Diagram
Confidential and Propri~
6-23
·nc102
The DC102 is provided intbe follbwing two variations..Refer to Table 3 for the ac parameters for each variation. · DC102: Digital part no. 1913888-00 and 1913888-01
· Pin and Signal Description
The input and output signals and the power and ground connections for the DC 102 20-pin DIP are shown in Figure 2 and summarized in Table 1.
INOA INOB IN1A IN1B IN2A IN2B IN3A IN3B OUT GND
20
2
19
3
18
4
17
5
16
DC102
6
15
7
14
g
13
9
12
10
11
Vee IN7B IN7A IN6B IN6A IN5B IN5A IN4B IN4A NC
TOP VIEW
Figure 2 · DC102 Pin Assignments
Confidential and Proprietary
-
oc102
Pin 1,2 3,4 5,6 7,8 12,13 14,15 16,17
INOA,INOB INlA,INlB IN2A,IN2B IN3A,IN3B IN4A,IN4B IN5A,IN.5B IN6A,IN6B
Table 1 · DC102 Pin and Signal Summary
Input/Output* Definitiot1/FUnct.iori
input
Input, AO and BO-Dual data inputs toga~ A
input
Input Al and Bl-Dual dat~inputs togateB
input input
Inputs A2 andB2-Dual datit inputs topte C Inputs A3 and BJ~Dual data'iripi:lts to gate D
input
Inputs A4 and B4-Dua1 data inputs to gate E
inpu,t
input
Inputs A6 and B6-Dua1 data inputs to gate G
18,19 IN7A,IN7B
9
OUT
output**
11
NC
10
GND
input
20
V
input
*All signals are TTL levels **Open collector
No connection
G·-
r
o
u
''
n
d ,,
-
G
r
,,
o
u
n
d
,
,r..e, .f.erence
Voltage---Pdwer supply voltage
Functional Description Figure 3 is a functiorutl symbol of the DC102 that shows the input signa,l groups.
EIGHT A INPUTS
EIGHT B INPUTS
A7
AO
DC102 B7 OUT BO
OUTPUT
Figure 3 · DC102 Functional Symbol
Confidential ahd Proprietary
6-25
nc102
· Specifications ,
The mechanical,. electrical, and environmental characteristics and specifications for the DC 102 are described in the following pa'ragraphs. The test conditions for the electrical values are as follows unless specified otherwise. Refer to Digital specification A-PS-2100002-GS for the general specifications of integrated ci.t:cuits. ·Power supplyvoltage(Vcc): 5.0 V ±5% · Temperature range (TA): 0°C to 70°C
Mechanical Configuration The physical dimensions of the DC102 20-pin DIP are contained in Appendix E.
Absolute Maximum Ratings
Stresses greater than the absolute maximum ratings may cause permanent damage to the device.
Exposure to the absolute maximum ratings for extended periods may adversely affect the relia-
bility of the device.
.
· Supply voltage (Vcc): 7.0 V
· Operating temperature (T"): 0°C to 70°C
· Relative humidity: 0 to 95% (noncondensing)
Recommended Operating Conditions · Supply voltage (Veel: 5 V ± 5% · Supply current (lee): 160mA
de Electrical Characteristics , The de electrical parameters of the DC102 for the operating voltage and temperature ranges specified are listed in Table 2. Refer to Appendix C for the test circuits configurations referenced in the tables.
6-26
Confidential and Proprietary
-·
18ble 2 · DC102 de Input and Output Parameters
~
Low-level input voltage High-level input voltage Low-level input current
Symbol Test Condition
Vn.
Vm
In.
v V1L=0.4
·vcc==5.25V
. Requirements Min. Max.
0.8
2.0
Units
v v
0.1
-0.2 mA
High-level
Im
V18 ==2.7 V
-0.1
0.2 mA
input current
Vcc=5.25 V
Input current
11
at maximum
input voltage
Vm=7V Vcc=5.25V
Low-level
VoL
Vcc=4.75V
output voltage
IOL=150mA
Pin 1=0.8V
All other
inputs=2.0 V
10
mA
0.55 v
Vcc=4.75 V lm=l20mA Pin1=0.8V All other inputs=2.0 V
0.5 v
Output reverse Ion
current
Vcc=4.75 V VOH=J.75V All inputs=.
2.0V
0.1 mA
Input clamp voltage
VI
Vcc=4.75 V
l1=-l8mA
-1.2 v
Supply current lee
Vcc=5.25V Pin I=Vm, all other inputs
=Vu."!'
160
mA
*Connect 330 resistor from Vcc to OUT (Pin 9)
001D2
Test
Circuit
Cl,C2
Cl
C4 C4 C4 C2
C2
Cl
CJ C7
Confidential and Proprietary
6-27
-
. ·oc112
ac Electrical Characteristics
. '·-
.
The voltage waveforms and propagation ~days symbols for the input and output signals 11re .. .
shown in, Figure 4 and definect in Table}. Refer to Figure .5 for· the load·circuit used in meastirlng
the propagation delays. The following t~st conditions apply to the ac propagation delay measure-
ments.
· V1L=O V to0.8 V,Vra=2.0 V to 3.5 V for inputs not being tested.
· The DC102 must meet the speed requirements for the specified input voltage range and per-
formance must not be degraded by momentary negative voltage spikes on the inputs.
· The nominal test conditions are V., (O) =0 V, V., (1)=3.0 V, V,L =0.5 V and Vrn=2.7 V.
I-- ti>w-----1 3V - - - 00%I-v----....I
I
OV
I l
~ tR
Input Waveform
tR =IF= 0.5 V/ns tpw = 180 ns V;n:O V ~ (V;nO) ~0.8 V 2.0 V ~ (Von 1} ~ 3.5 V
INPUT (V;n)~V(O}
Output Out-Of-Phase
~.~., ! · \
v ~L ·.->Iv
Output In-Phase
IPLH --I
I-!-- --i
!*- IPLH
~
I I
I I
IPLH ---i
!--- -I
!---tPLH
Figure 4 · DC102 ac SignalTiming Delay
6-28
Confidential and Proprietary
Symbol
tPLH
Table 3 · DC102 ac Propagation Delay
Delinition
Requirements
1913888-00*
Min.
Max.
1913888-01 **
Min.
Max.
Low-to-high level
20
13
output
High-to-low level
20
13
output
*CL=150pF **CL=lOOpF
DC102
Units ns
ns
Figure 5 · DC102 ac Load Circuit
Confidential and Proprietary
6-29
·Features
· Separate transmit and receive frequency out{'uts · Program selectable baud rates from 50 to 38,400 · External TTL dock or crystal inputs · TTL compatible inputs and outputs
· Description
The DC301 dual baud-rate generator, contained in a 18-pin dual-inline package (DIP), provides a transmit and receive output to control the transfer of serial line information. Figure 1 is a simplified block diagram of the DC301 baud rate generator.
FREQUENCY
DECODE AND CONTROL
XTAL/EXT 1 {11
a:
0
I-
<(
...J
:!
'ill
XTAL/EXT 2 (lS) 0
rREC Re
ADDA Re Ro
u:r
I<(
a...J
(8) STA
DIVIDER
XMIT FREQ
DIVIDER
REC FREQ
FREQUENCY DECODE ANO CONTROL
REPROGRAMMABLE FREQUENCY SELECT
ROM
{2) (11) (9)
AAA
Vee GND Voo
Figure 1 · DC301 Simplified Block Diagram
Confidential and Proprietary
6-31
'···DC301
TheDC301 consistJ! of a crystal-controlled osciUato~, two programmable frequency dividers, and two divide-by-two counters. The input frequency to the oscillator can be supplied by an external TTL generator or controlled by a crystal connected direccly to the DC301. Separate programmable inputs are provided for both the transmit and receive channels. These inputs select their respective baud rates that may deviate depending on the frequencyof the crystal of TTL input. The frequency decode and control logic is ROM-based and controls the functions of the divider.
· Pin and Signal Description
The input and output signals and the power and ground connections for the DC30l 18-pin DIP are shown in Figure 2 and surrunadzed in Thble 1.
XTAL/EXT1 Vee
REC FREQ REC ADDA R11
REC ADDR Ra
REC ADDR Re
RECADDRrfl:' STR Voo
XTAL/EXT2 XMIT FREQ XMIT ADDRTA XMIT ADDA Ta XMIT ADDA Tc XMIT ADDA To STT GND
NC
TOP VIEW
Figure 2 · DC301 Pin Assignments
6-32
Confidential and Proprietary
-
Table 1 · DC301 Pin and Signal Summary
Pin Signal
Input/Output Definition/Function
1
XTAL/EXTl input1
Crystal/external 1-Connects to one lead of the crystal or to a TTL input.
18
XTAI./EXT2 · input1
Cryst~~terna1:2T:Cpnnects to· the other lead of
the Cry$ta'l; the 6t;>tldsiie polarity a TTL input, or not
connected.
17
XMITFREQ output'
Transmit . frequency .(fr)_...The fre9uentjt output selected by the trll.ns1I1itter address. .
3
REC FREQ
output'
Receive .frequency(£.)_...The frequency output
selected by t;l}i: ~iven1cldrCss.
. .
4~7 RECADDRRA, input'
R..Rc,Ro
8
STR
input2
16-13 XMIT ADDR TA> input2 Ta,Tc,Tn
12 SIT
input2
. 10
NC
11
GND
. input
2
9
V00
input
1TTL levels or crystal input 2TTLlevel
Receiver address-Four receiver address inputs that select the output freq\lency of the receiver. (RECV OUT). Strobe receiver addliss-Asserted ·to !()ad the receiver address into the receiver address register.
Trinsnut address--Fol.lr. transmit ad~ it:lputs
that select the output frequency of the transmitter (XMITOUT). Strobe transmitter address-Asserted to load the transmitter address into the transmitter ~s register. No connection
Voltage-Power supply 'i2'V connection ·
Confidential and Proprietary
...
DC301
Frequency Selection
. .
The DC301 is available in several variations depending on the baud rates required and the external .
clock connections as listed in Table 2.
·
Digital Part Number 2112623-00
2112623-01
2112623-02
2112623-03
2112623-04
2112623-05
Table 2 · DC.301 Electrical Variations
External Oock
Baud Rates
TI'L TTL or crystal TTL TI'L TTL .TTL
50to19,200 (Table 3)
50to19,200 (Thble 3)
50to19,200 (Tuble 4)
50 to 10,200 (Table 5)
100 to 38,400 (Thble 6)
50to19,200 (Table 3)
Power Supplies
12V,5V or.5 Vonly
12V,5V or 5 Vonly
12V,5V or 5 Vonly
12V,5V or 5 Vonly
12V,5V or 5 V only
5Vonly
Tubles 3 through 6 list the transmit and receive addresses required to select the desired baud rates for the crystal frequency specified. The tables also contain the characteristics of the DC301 signals for the selected baud rates.
6-34
Confidential and Proprietary
DCJOi·
Table Y· DC301 B$td.lbne Selection and Cbal'ileteristics (Crystal Frequency S.0688 MHt)
'liansmit/Receive
Tbeoretica1
Actual
Duty
Address
Baud Frequency
Frequency · Percent Cycle
D c B A Rates 16X Clock (kl&) 16XC1ock(kH:i) Error %
Divisor
0 0 0 0
50 0.8
000 1
75 1.2
0 0 10
110 1.76
0 0 1 1
134.5 2.152
0 10 0
150 2.4
010 1
300 4.8
0 110
600 9.6
0 1 1 1 1200 19.2
1 0 0 0 1800 28.8
1 0 0 1 2000 32.0
1 0 1 0 2400 38.4
1 0 1 1 3600 57.6
1 1 0 0 4800 76.8
1 1 0 1 7200 115.2
1 1 1 0 9600 153.6
1 1 1 1 19200 307.2
0.8 1.2 1.76 2.1523 2.4 4.8 9.6 19.2 28.8 32.081 38.4 57.6 76.8 115.2 153.6 316.8
0.016
--' _.;
0.253
3.121
50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 513/50 50/50 50/50 50/50 50/50 50/50 48/52 50/50
6336 4224 2880 2355 2112 1056 528
264 176 158 132 88 66 44 33
16
Table4·0Cl01 :Qaudn.~ ~.~~~(:~~ l.1~80Mliz)
Transmit/Receive
Theoretical
.Actual' .
.. Duty
c Address
Baud Frequ~.
Frequ~ < ~ Cycle
D
B A Rate 16X.Clo.ck &lb) 16X\~~· EffliH:; % Divisor
0 0 0 0
50 0.8
000 1
75 1.2
0 0 1 0
110 1.76
00 11
1.34.5 2.152
0 100
150 2.4
0 101
200 3.2
0 110
300 4.8
0 1 1 1
600 9.6
1 0 0 0 1200 19.2
1 0 0 1 1800 28.8
1 0 1 0 2000 32.0
1 0 1 1 2400 38.4
1 1 0 0 3600 57.6
1 1 0 1 4800 76.8
1 1 1 0 9600 153.6
1 1 1 1 19200 307.2
0.8 1.2 1.76 2.1523 2.4 3.2
4$
9.6 19.2 28.8 32.149 38.4 57.6 76.8 153.6 307.2
0 0 -.006 -,.019
0 0 0 0 0 0 +.465 0 0 0 0 0
50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 44/56
3456 2304 1571 1285 1152
864 576 288 144
96 86 72 48 36 18
9
Confidential and.Proprietary
6-35
-
:~
Table5·nCl01S.ud:Qate~aand~~·!c.W~Fr~en'Y~·.,l8.nii.t~>
Transmit/Reeeive
Address
Baud
D c B A Rate
Theoretical
Ac Wal
Duty
Frequency
Frequenw
Percent Cycle
16X Qock (ldb) 16XQock (kHz) ErrQr %
Divisor
0 0 0 0
50 0.8
0 0 0 .1
75 1.2
0 .0 1 0
110 1.76
00 11
134.5 2.152
0 10 0
150 2.4
0 10 1
200 3.2
0 110
300 4.8
0l 11
600 9.6
1 0 0 0 1200 19.2
1 0 0 1 1800 28.8
1 0 1 0 2000 32.0
1 0 1 1 2400 38.4
1 1 0 0 3600 57.6
1 1 0 1 4800 76.8
1 1 1 0 9600 153.6
1 1 1 1 19200 307.2
0.8 1.20 1.76 2.152 2.4 3.2 4.8 9.6 19.23 28.8 32.0 38.33 57.6 76.8 153.6 307.2
0 0 0 0
O·
0 0 0 +,14 0 0 -.17 0 0 0 0
50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50
7523 5015 3420 2797 2508 1881 1254
627 313 209 188 157 104
78 39 20
Table 6 ··DC3ol Baud Rate Selection and Characteristics (Cfystal Frequency .5·.52960 MHz)
TransmitjR.eceive
Theoretical
Actual
Duty
Address
Baud Frequency
Frequency
Percent Cycle
c D
B A Rate. 16X Clock:1(kHz) 16X Clock (kHz) Error %
Divisor
0 0 0 0
100 1.6
000 1
150 2.4
0 0 1 0
220 3.52
0 0 1 1
0 1 0 ··o 0 1 o· 1
269 4.304 300 4.8 400 6.4
0 1 10
600 9.6
0 1 1 1 1200 19.2
1 0 0 0 2400 38.4
1 0 0 1 3600 57.6
1 0 1 0 4000 64.0
1 0 1 1 4800 76.8
1 1 0 0 7200 115.2
1 1 0 1 9600 153.6
1 1 1 0 19200 '307.2
1 1 1 1 38400 614.8
1.6 2.4 3:5197 4.3032 4.8 6.4 9.6 19.2 38.4 57.6 64.298 76.8 115.2 153.6 307.2 614.8
0 0 -.006 -.019 0 0 0 0 0 0 +.466 0 0
o··
0 0 .
50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 50/50 44/56
3456 2304 1571 1285 1152
864 576 288 144
96 86 72 48 36 18
9
6-36
Confidential and Proprietary
-
· Specifications
The mecllankal, electrlcal, and environmental characteristics and 'Specifications for the OC301 are described in the follOwing paragraphs; The test conditions for the electrical vahres are as ·· follows unless specified otherwise. Refer to Digital specification A-PS-2100002-GS for thej!en~ · eral specifications of integrated circuits.
· Power supply voltage (Vcc): 5.0 V ±5%
· Power supply wltage <Y~n):12. V ±:?.~
Meebani,c.t Configuration ..
. ' .. ·.
The
physical
dimensions
of
the
DC30118-pin
DIP
are
co.· ~in. . ,. n.tam · .
,,
' ··.~ ',
Appendix
E .
Absolut.e·Maximum Ratings
Stresses greater than the absolute maximum i:atings may cause pertnanent damage to the device;· Exposure to the absolute maximum nttingsfor extended. periodsJnay ad~rsely affect the relia- ·
bility of the device.
· Positive voltage on any pin with respect;~ grotmd <V«): 2,0 Y.i
· Negative voltage on any pin with respect to ground cYci:>: ....,o.3 V
· Operating tempeiatilre (T"): 0°C to 70°C
· Relative humidity: 0 to 95% (noncondensing)
RecommeDded Operating Conditions · Supply voltage (Vcc): 5 V ± 5% · Supply voltage (Vnn): 12 V ± 5% · Total power supply current: 105 mA
Confident:W and Proprietary
6-37
--·-·-------~------·---------------~.........___-
-
de Electrical Chatacteristics The de decttical parameter~ of the DC301 for the qperating voltage aqd temperature ranges
specified are listed in Table 7. Refer to Appendix C for the test cirruit configurations ref~nced
in the table.
Table 7 · DC301 de Input and Output Parameters
Parameter
Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage
Symbol Test condition
Vu.
Excluding crystal
input levels
Vm
Requirements M.m·. Max:
0.8
3.5
Vee
Vm.
loL=3.2 mA
0.4
VoH
loH=lOOµA
2.4
Units
v
v v v
Input current
Im
V.,=5V,
Excluding crystal
input levels
Input capacitance (all inputs)
c ..
V1.=2.0V
Excluding crystal
inputs
10
µA
10
pF
External input
1 TTLload
5.0
load
Power supply
Ice
Vcc=5.25V
current
V1.=open
v... =open
loo
Voo=l2.6 V*
75
mA
30
mA
Total power dissipation
500
mW
*Test not required when only 5 Vdc supply is used.
Test Circuit A;B A,B B A D
G
6-38
Confidential and Proprietary
DCJtn.
ac Electrical Characteristics The input and outputsignal timing for the DC301 is shown in Figure 3. and the pantll'ieters are defined in Table 8. Refer to Appendix D for the standard TTL input and out[rut voltage waveform parameters usedfor measuring the signal timing.
Table 8 · PC301 ac inning~
Symbol Definition
Requirements1
Min. Max.
Units
PW
Receiver strobe
pulse widtlt
Transmitter strobe pulse width2
t_,
Address input
setup time'
150
de
ns
150
de
ns
250
ns
thold
Address input
hold time
Strobe to new frequency delay
.50
ns
2.5
µs
1CL = 30 pF under normal operating conditions. Unit(s) shall meet CL= 80 pF with derated
conditions.
2Input setup time can be decreased to > 0 nshy increasing the minimum strobe width by 50 ns to a total of 200 ns.
STROBE(STR/STT) ADDRESS
Tew·-~ . . _
j T~~
· Address ·need only be valid during the last TPw, Min time of the input strobe.
Figure 3 · DC301 ac Timing Parameters
Confidential and Proprietary
6-39
-
DC101
External Frequency Figure 4 shows typical external circuit;; 1,1Sed to copnect the TTL frequency inputs and crystalcontrolled inputs to the DG}Ol.
TTL' INPUT
DC301
'fTL' INPUT
DC301
· totem pole or open collector output Typical TTL Input Circuit
DC301
Typical Crystal Input Connections
Figure 4 · DC301 External Frequency Connections
6-40
Confidential and Proprietary
Instruction Set
This appendix provides a s1in1mary of the VAX-11 instructions implemented by the MicroVAX 78032, the floating-paint instructio~ suppo~ by the floating-paint unit, andthe emUlated
instructions that are assisted by the MicrqVAX 780'2's microcode. The; standard notat,ion for
operand specifiers is
<name> <access type> <data type>
1. Name-A suggestive name for the ot>etand in the context of the instruction. It is the capitalized
name of a register or block for implied operands.
2. Access type-A letter denoting the opet'lUlclspecifier access type. a= address operand
b =branch displacement
m;,,.modified operand (both readamlcwritten)
r =read only operand
v =if not "Rn," same as address dperand, otherwise R[n + l]'R[n]
w =write only operand
·
.
3. Data type-A letter denoting the data type of the operand.
h=byte
'
d =D_floating
f =F_.Jloating
g =G__floating
l=longword
q=quadword
v =fidd (used only in implied operands)
w=word
*=multiple longwords (used only in implied~)
4. Implied operands-Locationf! that ~. acl:essed by the instruction, but nonpedfied in an
operand, are denoted by braces { }. The abbreviatfons for condition codes are *=conditionally set/cleared - =not affected O=cleared l=set
The abbreviations for exceptions are rsv =reserved operand fuult iov =integer overflow trap idvz =integer divide by zero trap
fov =floating overflow fault fuv =floating underflow fault fdvz =floating divide by zero fault dov =decimal overflow trap ddvz =decimal divide by zero trap
sub= subscript range trap prv =privileged instruction fault
Opcode values are given in hexadecimal.
C1;mfidential and Proprietary
A-1
· Integer.Arithmetic and Logical Instructions
OP Mnemonic and Arguments
58 ADAWl add.rw, sum.mw
80 ADDB2 add.rb, sum.rob
co ADDI2 add.rl, sum.ml
AO ADDW2 add.rw, sum.row
81 ADDB3 addl.rb, add2.rb, sum.wb
Cl ADDL3 addl.rl, add2.rl, sum.wl
Al ADDW3 addl.rw, add2.rw, sum.ww
DB ADWC add.rl, sum.ml
78 ASHL cnt.rb src.rl, dst.wl 79 ASHQ cnt.rb src.rq, dst.wq
8A BICB2 mask.rb, dst.mb CA BICL2 mask.rl, dst.ml AA BICW2 mask.rw, dst.mw
8B BICB3 mask.rb, src.rb, dst. wb
CB BICL3 mask.rl, src.rl, dst.ml
AB BICWJ mask.rw, src.rw, dst.mw
SS BISB2 mask.rb, dst.mb
cs BISI2 mask.rl, dst.ml
AS BISW2 mask.rw, dst.mw
89 BISB3 mask.rb, src.rb, dst.mb C9 BISLJ mask.rl, src.rl, dst.ml A9 BISW3 mask}rw, src.rw, dst.mw
93 BITE mask.rb, src.rb D3 BITL mask.rl, src.rl B3 BITW mask.rw, src.rw
94 CLRBdst.wb D4 CLRLdst.wl 7C CLRQdst.wq B4 CLRWdst.ww
91 CMPB srcl.rb, src2.rb Dl CMPL srcl.rl, src2.rl Bl CMPW srcl.rw, src2.rw
98 CVTBL src.rb, dst.wl 99 CVTBW src.rb, dst.wl F6 CVTLB src.rl, dst.wb F7 CVTLW src.rl, dst.ww 33 CVTWB src.rw, dst.wb 32 CVTWL src.rw, dst. wl
97 DECBdif.mb D7 DECLdif.l 97 DECWdif.mw
S6 DIVB2 divr.rb, quo.rob C62 DIVI2 divt:rl, quo.ml A6 DIVW2 divr.rw, quo.mw
Description
Add aligned word interlocked
Add byte 2-operand Add long 2-operand Add word 2-operand
Add byte 3-operand Add long 3-operand Add word 3-operand
Add with carry
Arithmetic shift left Arithmetic shift quad
Bit clear byte 2-operand Bit clear long 2-operand Bit dear word 2-operand
Bit clear byte 3-operand Bit clear long 3-operand Bit dear word 3-operand
Bit set byte 2-operand Bit set long 2-operand Bit set word 2-operand
Bit set byte 3-operand Bit set long 3-operand Bit set word 3-operand
Bit test byte Bit test long Bit test word
Clear byte Clear long Clear quad Clear word
Compare byte Compare long Compare word
Convert byte to long Convert byte to word Convert long to byte Convert long to word Convert word to byte Convert word to long
Decrement byte Decrement long Decrement word
Divide byte 2-operand Divide long 2-operand Divide word 2-operand
AP_t,,";."...-.l~:-A
NZ VC Exceptions
* * * * iov
* * * * iov * * * * iov * * * * iov
* * * * iov * * * * iov * * * * iov
* * * * iov
* * * 0 iov * * * 0 lOV
* * 0-
* * 0 -
* * 0 -
* * 0 * * 0 * * 0 -
* * 0 -
* * 0 -
* * 0 -
* * 0 -
* * 0 * * 0 * * 0 -
* * 0 * * 0 -
0 1 0 --
0 10 0 1 0 0 10-
* * 0 * * * 0 * * * 0 *
* * 00 * * 0 0 * * * 0 iov * * * 0 iov * * * 0 iov * * 0 0
* * * * iov * * * * iov * * * * iov
* * * 0 iov, idvz * * * 0 iov,idvz * * * 0 iov, idvz
A-2
Confidential and Proprietary
Preliminary
N z v c EEeptions
87 DIVB3 divr.rb, divd.rb, quo.wb C72 DIVL3 divr.rl, divd.rl, quo.wl A7 DIVW3 divr.rw, divd.rw, quo.ww
Divide byte 3-operand Divide long 3-operand Divide word 3-operand
* * * 0 iov, idvz * * * 0 iov, idvz * *' * () 'i.m', idvz
7B' EDIV divr.rl, divd.rq, qµo. wl, rem.wl Extended divide 7A' EMUL mulr.tl, rnuld.rl, add.rl, prod.wq . Extended multiply
* * * 0 iov,idvz * * 0 0
96 INCB sum.mb D6 INCL sum.ml
B6 INCW sum.mw
Increment byte Increment long Increment word
* * * * lov
* * * *· iov·
* * * * iov
92 MCOMB st'C.!b, dst.wb D2 MCOML sn:.rl, dst.wl B2 MCOMW sn:.rw, dst.WW
Move complemented byte
' MCi!Ve complemented long Move complemented word' ' '
* * 0 -
* *0-
* * 0 -
8E MNEGB src.rb, dst.wb
Move negated byte. ·
****kw
CE MNEGL sn:.rl, dst.wl
AE MNEGW src.rw, dst.ww
Mi:ive negated long
Move negated word
****ioV
* " * * iov
90 MOVB src.rb, dst.wb DO MOVL src.rl, dst.wl BO MOVW src.rw, dst.ww
Move byte
Move lopg Move word ·
* * 0 -
* *0* * 0 '-
9A MOVZBW src.rb, dst.wb 9B MOVZBL src.i;b, dst.wl 3C MOVZWL Sl'C.rw, dst.ww
* Move ze~mied byretoword 0 * 0 -
Move zet'(H!Xtep~ byte tolong. 0 0 Moveze~ word tololllf! 0 " 0
84 MULB2 mulr.rb, prod.rob C4' MULL2 mulr.rl, prod.ml A4 MULW2 mulr.rw, prod.mw
85 MULB3 mulr.rb, mUld.rb, prod.mb
"Mubiply byte.2·e>pemnd ·· Multiply long 2-operand Multiply ~f~operand
Multiply byte 3-opetahd
..'* * " 0 ,icw
* * 0 iov * * * 0 iotr. * *. * o iov
C51 MULL3 mulr.:tl, muld.rl, prod.ml A5 MULW3 mulr.rw; muld.rw, prod.mw
Mqltiply" lQng 3-operand
Multiplyword 3-operand
* * * O'wv
***Oiov
DD PUSHL src.rl,
Push long
9C ROTLcnt.rb, src.rl, dst.wl D9 SBWC sub.rl, dif.ml
Rotate long
.Subtraet With carry
* * 0 -
****Jov
82 SUBB2 sub.rb, dif.mb C2 SUBL2 sub;rl, dif.ml A2 SUBW2 sub.rw, dif.mw
83 SUBB3 sub.rb, min.rb, dif.mb C3 SUBL3 sub.rl, min.rl, dif.ml A3 SUBW3 sub.tw, min.rw, dif.mw
95 TSTB src.rb D5 TSTI src.rl B5 TSTW src.rw
Subtl;llct.byte 2-operand Subtract long 2-operand Subtract word 2-operand
Subtract byte 3-operand Subtract Ion~ 3-operand Subtract wprd,3~
rest byte
ThSt long rest word
*
*
* "
*..
*"
*
iov iov
* * * * iov
* * * * 1ov'·''' " * * * iov " * * * igv
.. * 0 0
* * 00 * * 0 0
8C XORB2 mask.rb, dst.mb CC XORL2 :mask.rl, dst.ml AC XORW2 mask.rw, dst.mw
8D XORB3 :mask.rb, src.rb, dst.wb CD XORL3 mask.rl, sl'C.rl, dst.wl AD XORW3 mask.rw, sl'C.rw, dst.ww
Exclusive or byte 2-operand Exclusive or long 2-operand Exclusive oi: word 2.;operand
Exclusive or byte 3-operand Exclusive or long 3.;operand Exclusi\l'e or word 3-operand
* *0 * * 0 * * 0 .-
* * o' -
* * 0 * " 0 -
1. The MicroVAX 78132 FPU, when present; accelerates execution of these integer multiplication
instructions.
Confidential and Proprietary
A-3
-
Preliminary
2. The MicroVAX 78132 FPU, when present, ~cd.erates execution of mese inte~r division, instructions.
· Address .Instructions
OP Mnemonic and Arguments
9E MOVAB src.ab, dst.wl DE MOVAL { =F} src.al, dst.wl 7E MOVAQ { =D=G} src.aq, dst.wl 3E MOVAW src.aw, dst.wl
9F PUSHAB src.ab, {-(SP).wl} DF PUSHAL { =F} src.al, {-(SP).wl} 7F PUSHAQ { =D=G} src.aq, {-(SP).wl} 3F PUSHAW src.aw, {-(SP).wl}
Description
Move address of byte Move address of long Move address of quad Move address of word
Push address of byte Push address of long Push address of quad Push·address of word
· Variable-length Bit Field Instructions
N Z V C Exceptions
* *0* * 0* * 0 * * 0-
* * 0 * * 0 _,
* * 0* *0-
OP Mnemonic and Arguments
EC CMPV pos.rl, size.rb, base.rb, {field.rv}, src.rl
ED CMPZV J?OS.rl, size.rb, base.vb, {field.rv}, src.rl
EE EXTV pos.rl, size.rb, base. vb, {field.rv}, dst.wl
EF EXTZV pos.rl, size.rb, base.vb, {field.rv}, dst.wl
FO INSV src.rl, pos.rl1 size.rb, base.vb, {field.wv}
EB FFC s~.rl size.rb, base.vb, {field.rv}, findpos. wl
EA FFS$~s.rl, size.rb, base.vb, {field.rv}, findpos. wl
Description Compare field Compare :tero-extended field Extract field Extract zero-extended field Insert field Find first clear bit Fil:ld first set bit
N Z V C Exceptions
* * 0 * rsv
**O*rsv **0-rsv
* * 0 · - rsv
----rsv **0-rsv **0-rsv
· Control Instructions
OP Mnemonic and Arguments
9D ACBB limit.rb, add.rb, index.mb, displ.bw
Fl ACBL limit.rl, add.rl, index.ml, displ.bw
3D ACBW limit.rw, add.rw, index.mw, dispLbw
F3 AOBLEQ lirriit.rl, index.ml, displ.bb
F2 AOBLSS limit,rl, index.ml, displ.bb
Description Add compare and branch byte Add compare and branch long Add compare and branch word Add one and branchon less or equal Add one and branch on less
N Z V C Exceptions ***-iov ***-iov
·* * * - iov * * * - iov * * * - iov
Con£ii.ientj.al 1Uld Proprietary
OP Mnemonic and Aigwnents
Description
lE BCC{=BGEQU}displ.hb lF BCS{ =BLSSU}~pl.bb 13 BEQL{ ==.BEQW},displ.bb 18 BGEQ disptbb 14 BGTRdispLbb lA BGTRU displ.bb 15 BLEQ displ.bb lB BLEQU displ.bb 19 BLSS disp1.bb 12 BNEQ {==BNEQU} displ.bb
lC BVC displ.bb 1D BVS displ.bb
Branch on carry clear
Branch on carry set
Branchion equal
Bratich on ,-eater or equal
Branch 6n greater
Branch on greatetunsigned
Branch on less 0r eq\lal
Branch on less or equal unsigned Branch on less Branch on not equal
Brandi on oYCrllPW:dear Branch on·~ set
El BBCpos.rl, base.vb, displ.bb,
{field.rv}
· .. ·
EO BBS pos.rl, base.vb, displ.bb, {field.rv}
E5 BBCC pos.rl, base.vb, displ.bb, {field.mv}
E3 BBCSpos.rl, base.vb, displ.bb,
{field.mv}
·
E4 BBSC pos.rl, base.vb, displ.bb, {field.mv}
E2 BBSS pos.rl, base.vb, displ.bb, {field,mv}
Branch ori bit cleat Branch on hit.set Bralich on bit clear and Clear Branch on bit~ and set Branch o~ .bitlM:t 11nd clear
Branch on bit set aild set
----l:Sv
rsv
·l:SV
rsv
rsv
E7 BB.CCI pos.rl, base.vb, dislp.bb,
{ field.mv}
.. Branch 911' < ~.and clear intciiloc;~
rsv
E6 BBSSI pos.rl, base.vb, dislp.bb,
{field.mv}
Branch on bit set and set interlocked
rsv
E9 BLBC src.rl, displ.bh .ES BLBS src.rl, displ.bb 11 ·· BRB displ.hb 31 BRWdispl.bw 10 BSBB displ.bb {-(SP).wl}
30 BSBW displ.bw {:-(SP).wl}
Branch on low bit clear Branch on I9W bit set
Branch. wit!i byre'dis~ment ...
.·B~withwonl.Ailipl~nt
Branch to sl.l~Wi.h bite
displacement dBisrapnlacchOtµo,esnutbr··out·ine w·· ith w·o··rd
8F CASEB selecto!:rb, base.rb, limit.rb, displ.bw-list
CF CASEL selectoul, base.rl,
limit.rl, displ.bw-list
AF CASEW selectoi:rw, base.rw,
limit.rw, displ.bw-list 17 JMPdst.ab 16 JSB dst.ab, {-(SP).wl} 05 RSB {(SP)+ .rl} F4 SOBGEQ index:ml, displ.bb
F5 SOBGTRindex.ml; displ.bb
Case long
Case word
Jump
Jump to si:ibfui:ttitie
Return from subroutine ·
Subttact one and branch on gt"l!ater
or equal . . .
· ··
Subtract one and branch on greater
* * 0 *
* * 0 *
*.,o *
***-iov * *··* - iov
A-5
----·--·-------
-;·
Preliminary
· Procedure Call Instructions
OP Mnemonic and Arguments
FA CALLG arglist.ab, dst.ab, {-(SP).w'}
FB CALLS numarg.rl, dst.ab, {-(SP).w'} 04 RET {(SP)+ .r'}
Descript·on Call with general argument list Call with argument list on stack
Return from procedure
NZ vc Exceptions
0 0 0 0 rsv 0 0 0 0 rsv * * * * rsv
· Miscellaneous Instructions
OP Mnemonic and Arguments B9 ·BICPSW mask.rw BS BISPSW mask.rw
03 BPT {-(KSP).w"} 00 HALT {-(KSP).w'}
ON INDEX subscript.rl, low.rl, hUth.rl,
size.rl, indexin.rl, indexout.wl DC MOVPSLdst.wl
01 NOP
BA POPRmask.rw, ;{(SP)+.r'} BB PUSHRmask.rw, ;{-(SP)+.w'} FC XFC {unspecified oeprands}
· Queue Instructions
Description
Bit clear processor status word Bit set processor status word Break point fault
Halt (kernel mode only)
N Z V C Exceptions ****rsv
* * * * rsv
0 0 0 0 - - - - prv
Index calculation Move processor status longlirord No operation Pop registers Push registers
Extended function call
* * 0 0 sub
---00 00
OP Mnemonic and Arguments 5C INSQHI entry.ab header.aq 5D INSQTI entry.ab header.aq
OE INSQUE entry.ab, pred.ab
5E REMQHI header.aq, adch:wl 5F REMQTI header.aq, addr.wl
OE REMQUE entry.ab, addr.wl
Description Insert at head of queue, interlocked Insert at tail of queue, interlocked Insert into queue Remove from head of queue, interlocked
Remove from tail of queue, interlocked Remove from queue
NZVC Exceptions
0 * 0 * rsv 0 * 0 * rsv * * 0 * 0 * * * rsv 0 * * * rsv ** **
· Character String Instructions
OP Mnemonic and Arguments
28 MOVC3 len.rw, srcaddr.ab, dstaddr.ab, {R0-5.wl}
2C MOVC5 srclen.rw, srcaddr.ab, fill.rb, dstlen.rw, dstadch:ab, {R0-5,wl}
Description Move character 3-operand Move character 5-operand
N Z V C Exceptions 0 1 0 0
* * 0*
Confidential and Propric;!tary
-
· System Support Insttuctions
Appendix A
OP Mnemonic and Arguments
Description
BD CHME param.rw, {-(ySP).w·}
Change mode to executive
BC CHMK param.rw, {-(ySP).w'}
Change mode to kernel
BE CHMS param.rw, {-(ySP).w'}
Change mode to supervisor
BF CHMU param.rw, {-(ySP).w'}
Change mode to user
Where y =MINU(x.PSL < Cl,ll'teO-LmOde <)
06 LDPCTX {PCB.r·, .,.(KSP).w'} DB MFPR procreg.rl, dst.wl DA MTPR src.rl, procreg.rl
oc PROBER mode.rb, len.rw, base.ab
OD PROBEW mode.rb, len.(W, b11SC.ab
· Loadpi:\Xess context {kemtil ~e only)
Move from processor register (kernel mode only) · ·
Move to processor register (kernel mode only)
Probe read access
J>rtthe write access
02 REI {(SP)+.r'}
lkturn ~ exceptio11 or interl'Qpt
07 SVPCTX {(SP)+ .r', PCB.w·}
Save pn>Cess context (kernel rnode only) ·
NZ vc Exeeptions
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- - - - rsv, prv
* * 0 - rsv, prv
* * 0 - rsv, prv
0 * 0 -
0 *0* * * * rsv
prv
· Microcode-assisted Emulated ThstructiOns
The MicroVAX 78032 provides microcode ass~tjlnce for the etnulatipn of these instructions by system software. The processor processes the Qpetand spedftet!(, i;reates a swidard argument list,
and takes an emulated instruction fault. For a description of e~ted instruction pl'Oee$sing, refer to the MicroVAX 78032 User's Guide.
OP Mnemonic and Aigumetits
Description
N Z V C Exceptions
20 ADDP4 addlen.rw, addaddr.ab, sumlen.rw,
suma.ckkab
Add packed 4-operand
* * * 0 rsv, dov
21 ADDP6 addllen.rw, addladdr.ah, add2len.rW,
add2adclr.ab, sumlen.rw, sumaddr.ab
Md packed ~pa-and
* * * 0 rsv, dov
F8 ASHP cnt.rb, stclen.rw, srcaddr.ab, round.rb, .· Arithmetic shi£~.and i:pund
dstlen.rw, dstaddr.ab
packed
· ·
* * * 0 rsv, dov
29 CMPC3 len.rw, srcladdi:ab, src2addr.ab
2D CMPC5 srcllen.rw, src1addr.ab, fill.rb, src2len.rw, src2addt:ab
35 CMPPJ len.rw, srcladdr.ab, src2addr.ab 37 CMPP4 srcllen.rw, srcladdt:ab, src2len.r\V,
src2add.ab
OB CRC tbl.ab, inicn::.rl, strien.rw, stream.ab
F9 CVTLP src.rl, dstlen.rw, dstaddr.ab 36 CVTPL sn::len.rw, srcaddr.ab, dst.wl
Compare character 3-operand
Compare chlll\lcter 5-operand · .,
.* 0 ·*
* *0 *
Compare packed 3-operand * * 0 0
_Com{>i!l'C packed 3-operand * * 0 *
Calculate cyclic redundancy check
* *0 0
Convert long to packed Convert packed to long
* * ·* 0 rsv, dov * * * 0 rsv, iov
08 CVTPS, srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab
09 CVTSP, srclen.rw, srcaddr., dstlen.rw, dstaddr.ab
Convert packed to leading
separat;e
* * * 0 rsv,dov
Convert leading separate to
packed
*
*
,.
0
rsv,dov
Confidential and 1\-opriet:ary
A-7
- - - - - - - - - - - - - - - - · - - - - - - - .. -·~------
.. -·----~-------·
.... AppelldiX'. A
OP Mnemonic and Argumep.ts
24 CVTPT srden.rw, srcaddr.ab, tbladdr.ab, dstlen.rw, dstaddr.ab
26 CVTTP srclen.rw, srcaddi:ab, tbladdr.ab, dstlen.rw, dstaddi:ab
27 DIVP divrien.rw, divraddr.ab, divdien.rw, quolen.rw, quoaddr.ab
38 EDITPC srden.rw, srcaddr.ab, pattern.ab, dstaddr.ab
3A LOCC char.rb, len.rw, addr.ab
J9 MATCHC objlen.rw, objaddr.ab, srclen.rw, srcaddr.ab
34 MOVP len.rw, srcaddr.ab, dstaddr.ab
2E MOVTC srclen.rw, srcaddr.ab, fill.rb, tbladdr.ab, dstlen.rw, dstaddr.ab
2F MOVTIJC srclen.rw, srcaddr.ab, esc.rb, tbladdr.ab, dstlen.rw, dstaddr.ab
25 MULP mulrien.rw, mulraddr.ab, muldlen.rw, muldaddr.ab, prodlen.rw, prodaddr.ab
2A SCANC len.rw, addr.ab, tbladdr.ab, mask.rb
3B SKPC char.rb, len.rw, addr.ab
2B SPANC len.rw, len.iw, tbladdi:ab, mask.rb
22 SuBP4 sublen.rw, subaddr.ab, diflen.rw, difaddr.ab
23 SUBP6 sublen.rw, subaddr.ab, minlen.rw, minaddr.ab, dillen.rw, difaddr.ab
Description
Convert packed to trailing * * * 0 rsv,dov Convert packed to trailing * * * 0 rsv,dov
Divide packed
Edit packed to character string
Locate character
* * * 0 rsv, dov, ddvz
* * * * rsv, dov 0 * 0 0
Match characters Move packed
0 * 0 0 * * 0 0
Move translated characters * * 0 *
Move translated until character
* * * *
Multiply packed Scan for character Skip character Scan characters
* * * 0 rsv, dov 0 * 0 0 0 * 0 0
0 * 0 0
Subtract packed 4-operand * * * 0 rsv, dov
~ubtract packed 6:operan,d * * * 0 rsv, dov
· MicroVAX 78032 Foating-point Instructions
These instructions are implemented in hardware if the optional MicroVAX 78132 floating-point
unit is present in the system. They must be software emulated if the MicroVAX 78132 is not
included.
OP Mnemonic and Arguments
Description
06F ACBD limit.rd, add.rd, index.md 04F ACBF limit.rf, add.rf, index.rf 4FFD ACBG limit.rg, add.rg, index.mg
Add compare and branch D_floating
Add compare and branch F_floating
Add compare and branch G_floating
060 ADDD2 add.rd, sum.rod 040 ADDF2 add.rf, sum.mf 40FD ADDG2 add.rg, sum.mg
Add D_floating 2-operand Add F_floating 2-operand Add G_floating 2-operand
061 ADDD3 addl.rd, add2.rd, sum.wd Add D_floating 3-opemnd
041 ADDF3 addl.rf, add2.rf, sum.wf Adel. F_floating 3-operand
41FD ADDG3 addl.rg, add2.rg, sum.wg Add G__.floating 3-operand
NZ v c Exceptions
* * 0 rsv, fov, fuv
* * 0 - rsv, fov, fuv
- * * 0 rsv, fov, fov
* * 0 0 rsv, fov, fuv * * 0 0 rsv, fov, fuv * * 0 0 rsv, fov, fuv * * * 0 rsv, fov, fuv * * * 0 rsv, fov, fuv * * * 0 rsv, fov, fuv
A-8
Confidential and Proprietary
A~A
OP Mnemonic aQCf Arguments
071 CMPD srcl.t:tl, src2.m 051 CMPF srcl.rf, src2.rf
51FD CMPG srcl.rg, FC2·1'8
06C CVTBD src.rb, dst.wd 04C CVTBF src.rb, dst.wf 4CFD CVTBG src.rb, dst.wg
068 CVTDB src.rb, dst.wb
076 CVTDF src.m, dst.wf 06A CVTDL src.m, dst.wl 069 CVTDW src.m, dst.ww 048 CVTFB src.rf, dst.wb 056 CVTFD src.rf, dst.wg
99FD CVTFG src.rf, dst.wg 04A · CVTFL src.rf, dst.wl 049 CVTFW src.rf, dst.WW 48FD CVTGB src.rg, dst.wb 33FD CVTGF src.rg, dst.wf 4AFD CVTGL src.rg, dst.wl 49FD CVTGW src.rg, dst.ww 06E CVTLD src.rl, dst. wb 04E CVTLF src:.ri dst.wf 4EFD CVTLG src.rl, dst.wg 060 CVTWD src.rw, dst.wd
640. CVTWF src.rw, dst.wf 4DFD CvTwG src.rw, dst.wg
06B CVTRDL src.m, dst. wl
04B CVTRFL src.rf, dst.w1
4BFD CVTRGL src.rg, dst.wl
066 DIVD2 divr.m, quo.md 046 DIVF2 divr.rf, quo.mf 46FD DIVG2 divr.rg, quo.mg
067 DIVD3 divr.rd, divi:m, quo. wd 047 DIVD3 div:c.rf, divr.rf, quo.wf 47FD DIVD3 div:r.rg, divr.rg, quo.wg
074 EMODD muir.rd, mulrx.rd, muld.m, int.wi, fract.wd
054 EMODF muir.rf,. mulrx.rb, muld.rd int.wl, fract. wf
54FD EMODG muir.rg, mulrx.rw, muld.rg int.wl, fract. wg
072 *MNEGD src.m, dst.wd 052 *MNEGF src.rf, dst.wf 52FD *MNEGG src.rg, dst.wg
070 *MOVD src.m, dst.wd 050 *MOVF src.rf, dst.wf 50FD *MOVG src.rg, dst.wg
N Z V C Exeptions
Compare D_floating Compare F_flooring Compare G_floating
* * 0 0 rsv * * 0 0 rsv
* * 0 0 rsv
Convert byte to D_ffoating ~byte toF_floating
Convert_ byte·toG_jloating
* * 0 0
* * 0 0 * * 0 .o
··Convert D..Jloating to byte
Convert D.;.;.fiC>ating to'F.JI.Oat
Cot1Vert D;.;;;ftooting to long Convert D,Jlqating to word Convert J1..,.tlQating to byte C~ l;".J,loating to D_ffoat Con:vert F__±L;,ating to G.Jloat
Coovm F....1lP~ting to Ii:>Qg
Coovtrt F~ to w0t:tl Co~G~to.~
CorMtt G.Jli;,ating to F_float Convert G_floati.ng to long Convert G.:...ftoating to woi:d
Convert long tO D_floating
Conyert long to F_floating Comlertlqt0G..Jl6&Jing' · Convert word to D_floating
Convert word to F.Jl<:>atiu8
Convert word to G.JlOa.ting.
Co~tro.u# b_ilO,ating t6lo~ . .· .. ..... Ctoolonnvgqt round.ed F.Jloatin.g
CoilVert tolltlded G_floijting to long
· I;>iv~Jl..Jloatin& 2~~
Divide F_floatil:ig 2~1-imd Divide G.Jloating 2-operand
DivideD_flo~&g)~
Divide F.Jioadng 3-opl.?nmd
DMde, GJioatit)g ~mt
* * * 0 rsv, fov
* * 0 0-· rsv,fov
i°"' *
* *
*
*
* "*
* *
0
-0
.o
rs:V;iov rsv, rs:v,. iov
* * 0 0 rsv
* * 0 0 rsv
* * * 0 rsv,iov
* * * 0 rsv,iov
* * * 6 rsv,fov
* * 0 o. rsv,Jov, fuv
* * * 0 m,iov * * * 0 nw, iov
* * 0 0
* * 0 0
* 00
* * 0 0
* * 0 0
* * 0 0
* * 0 0 rsv,iov
* .... * · 0 rsv,iov
* * * 0 rsv,iov
* * O O rsy fqy fuvJdvz
* * 0 0 rsv fov fuv fdvz * * 0 0 rsvfuvfov fdvz
* * .0 ()'''r:i~favfuvfdvz
* *··o c-· mfov fuv fdvz
* * . 0 0 rsvfeivfuv fdvz
Extended modulus D...floating * * * 0 rsv fov fuv iov
Extended modulus F_floating * * * 0 rsv fov fuv iov
Extended modulus G_floating
Move negated DJloating Move negated F_floating Move negated G_floating
Move D_floating Move F_floating Move G_floating
* **
* *0 * * 0 * * 0
* * 0 * * 0 * * 0
0 rsv fov fuv iov
0 rsv 0 rsv 0 rsv
- rsv - rsv
- rsv
Confidential.and Proprietary
A-9
~--·-~-~-~"~~---~·~~---------------~--.-...·-·-·-·-----.........____
-·
Preliminary
Appendix A
OP Mnemonic imd Arguments
Description
NZ vc Exceptions
064 MULD2 mulr.rd, prod.md 044 MULF2 mulr.rf, prod.mf 44FD MULG2 mulr.rg, prod.mg
Multiply D""'floating 2-operand * * 0 0 rsv, fov, fuv
Multiply F_floating 2-operand * * 0 0 rsv, fov, fuv Multiply G_floating 2-operand * * 0 0 rsv, fov, fuv
065 MULD3 mulr.rd, muld.rd, prod.wd Multiply D_floating 3-operand * * 0 0 rsv, fov, fuv 045 MULF3 mulr.rf, muld.rf, prod.wf Multiply F_floating 3-operand * * 0 0 rsv, fov, fuv 45FD MULG3 muli:rf, muld.rg, prod.wg Multiply G_floating 3-operand * * 0 0 rsv, fov, fuv
075 POLYD arg.rd, degree rw, tbladdei:ab Evaluate polynomial D_floating * * 0 0 rsv, fov, fuv 055 POIXF arg.rf, degree rw, tbladdei:ab Evaluate polynomial F_floating * * 0 0 rsv, fov, fuv 55FD POLYD arg.l'g, degree rw, tbladder.ab Evaluate polynomial G_floating * * 0 0 rsv, fov, fuv
062 SUBD2 sub.rd, dif.md 042 SUBF2 sub.rf, dif.mf 42FD SUBG2 sub.rg, dif.mg
Subtract D_floating 2-operand * * 0 0 rsv, fov, fuv Subtract F_floating 2-operand * * 0 0 rsv, fov, fuv Subtract G_floating 2-operand * * 0 0 rsv, fov, fuv
063 SUBD3 sub.rd, min rd, dif.md 043 SUBF2 sub.rf, min rf, dif.mf 43FD SUBG2 sub.rg, min rg, dif.mg
Sµbtract D_floating 3-operand * * * 0 rsvfovfuv
.. Subtract F_floating 3-operand * 0 0 rsv fov fuv .. Subtract G_floating 3-operand * 0 0 rsv fovfuv
073 *TSTD src.rd 053 *TSTF src.rf 53FD *TSTG src.rg
Test D_floating
Tust F_floating
Tust G_floating
* * 0 0 rsv
* * 0 0 rsv
* * 0 0 rsv
· MicroVAX 7802 FPU Integer Multiplication Instructions
OP Mnemonic and Arguments Description
07A Extended multiply OOA Index calculation
OC4 Multiply long 2-operand OC5 Multiply long 3-operand
EMUL mulr.rl, muld.rl, add.rl, prod.wq
INDEX subscript.rl, low.rl, hfah.rl, size.rl, indexin.rl, indexout.w1 MULL2 mulr.rl, prod.ml MULL3 mulr.rl, muld.rl, prod.wl
NZ v c Exceptions
* * 0 0
* * 0 0 subscript range * * * 0 iov * * * 0 iov
·MicroVAX 78132 FPU Integer Division Instructions
OP Mnemonic and Arguments OC6 Divide long 2-operand OC7 Divide long 3-opero.nd 07B Extended divide
Description DIVL2 divr.rl, quo.ml DIVL3 divr.rl, divd.rl, quo.wl EDIV clivr.rl, divd.rq, quo.wl, rem.wl
NZ vc Exceptions
* * * 0 iov, fdvz * * * 0 iov, fdvz * * * 0 iov, fdvz
A-10
Confidential and Proprietary
-
Preliminary
AppeOd&A
· MicroVAX 78132 FPU Operand Uansfer
The integer divide inStructions require th11t the lower 32-bits of the dividend be transferred first
and then. the upper 3A·bits.
VAX
FPU
P'tt1t
Mnemonic Opcode 1l.nsfer
ACBD 06F ACBF 04F ACBG 14F
limit.cl limit.£
Iimit.g
ADDDx ADDFx ADDGx
060,061 040,041 140,141
add2.d
add2.f
add2.g
CMPD 071 CMPF 051 CMPG 071
. src2.d src2.f src2.g
CVTBD 06C
src.b
CVTBF 04C
src.b
CVTBG 14C
src.b
CVTDB 068
src.d
CVTDF 076
src.d
CVTDL 06A
src.d
CVTDW 069
src.d
CVTFB 048
CVTFD 056
CVTFG 199 CVTFL 04A
CVTFW 049
CVTGB 148 CVTGF 133 CVTGL 14A CVTGW 149 CVTLD 06E CVTLF 04E CVTLG 14E
CVTWD 060
CVTWF 040 CVTWG 14E CVTRDL 14A
CVTRFL 14A
CVTRGL 14A
std src.f src.f src.f src.f src.g sn:.g sn:.g Sl'C.g src.l src.l src.l src.w sn:.w sn:.w src.d src.£ src.g
DIVDx DIVFx DIVGx
066,067 046,047 146,147
divd.d divd.f divd.g
EMO DD EMODF EMODG MULDx MULFx MULGx
074 054 154 064,065 044,045 144,145
mulrx.b mulrx.b mulrx.b mulr.d mulr.f mulr.g
Seco·.
T:ransfer add.d add.£ add;g addl.d addl.f addl.g sn:l.d sn:l.f sn:l.g
divr.d divr.f divr.g mulr.d mulr.f mulr.g muld.d muld.£ muld.g
TJUrd
'&ansler
index.d
index.£
index.g
muld.d muld.f muld.g
Operation.
Result 1
(index +add);,mrut (index.c;l~])
(iridex+~:.Iimit (index.f!lU) (index+ad~).;Iimit . (hiciex.g[RJ)
B.esult2
addl+add.? addl+ad42 addl+add2
suin.d{RJ sw,i.f[R] sum.g[R]
sn:l-src2 srcl-src.2 src1-src2
fit cvrt fit cvrt
fit cvrt fit cvrt
fit change intcvrt
int cvrt
d[rf4/.6]float[EJ-f[rf4/.6Jfloat[EJ --g[rf4/.6Jfloat[E] --byte(T] f[rf4/.6]float(R] --longword[E] wordln
intcvrt
fit change
int cvrt intcvrt int cvrt int cvrt fit change int cvrt int cvrt fit cvrt
fit cvrt fit cvrt fit cvrt fit cvrt fit cvrt md, int cvrt md, intcvrt md, intcvrt
byteln d[rf4/.6]float[E] --g[rf4/.6]float(E] longword[E] word[11 byte[TJ f[rf4/.6]float[R] - longwordff]
wordln
d[rf4/.6]float{E] - f[rf4/.6]float{R] ---
g(rf4/.61float[E] - d[rf4/.6]float(E]--f[rf4/.6]float[E] --g[rf4/.6]float[E] --longword(R] longword[R] longword[RJ
divd/divr divdfdivr divd/divr
quo.d(R] quo.f[R] quo.g[R]
muld*(mulr'mulrx) muld*(mulr'mulrx) muld*(mulr'mulrx) mulr*muld mulr*muld mulr*muld
int.l[E] int.l[E] int.l[E] prod.d{R] prod.f[R] prod.g[RJ
fract.d(R] fract.f[R] fract.g[R]
Confidential andProPrietary
A-11
-·
Prelimim1ey
VAX
FPU
M~<t~~
POIYD 075 POLYP 055 POIYG 155
First ~f!»'
arg.d arg.f arg.g
Second Third
Tt1U1s£er :. ;l't;tms£er
intl.d intl.f intl.g
#coeff.d #coeff.f #coeff.g
·~ r :
/),_".
Operation.
(arg*int 1) + coeff (~*intl)+ coeff
(arg*intl) +coeff
SUBDx SUBFx SUBGx
062,063 042,043
142,1~3.
min.cl min.£ min.g
sub.d · sub.f sub.g
min-sub min-sub min-sub
EMUL INDEX MULLx
07A
mulr.rl
OOA
(mulr.rl)
OC4,0C5 mulr.rl
muld.rl size.rl muld.rl
mulr*mhlcl · mulr*size mulr*muld
DIVLx EDIVx
OC6,0C7 divi:rl
07B
divr.rl
divd.rq · divd.rq
divdfdivr divd/divr
Result l
#int2.d[.NJ #int2.f[R] #int2.g[R]
#int3.d[Rl #int3.f[R] #int3.g[R]
diff.d[R] diff.f[R] diff.g[R]
prod.wq[EJ indexout.wq[E] --prod.wq[E]
quo.wl[E] quo.wl[E]
rem.,;.,.l[E] rem.wl(E.]
A-12
Confidential and Proprietary
The DCTll. and DCJ11···1&-bit microprocessors share the PDP-11 ru:chit~ lUld operate with a common instruction set and similar addressing.techniques..The following table list the instl"llction
set for both processors_ The .instructions diat do nOt ai>Ply to the. DCT11 nll,croproq:ssor are
indicated by a dagger (+) preceding the instruction mnemonic term. The DCTll microprocessor does not perform floating-point arithmetical operations and some of the :l}~Tll it\S~Oll executions are performed differently from those of the DCJll microprocessor.
The abbreviations {or the co11dition codes {N,Z,V,C) listed in~the t.able are as follows. For specific condition code information, refer to the µT11 u.~,c;.~,
*=conditionally set/cleared -=not affected O=cleared
l=set
The.block D preceding the opcode or base cOde;;;..O 'for woni/1 for byte
· Single Operand
Gene1'8I
Opcode
D050DD 0051DD 0052DD 0053DD 0054DD 0057DD 007>DD
Mnemonic
CLR(B) COM(B) INC (B) DEC{B) NEG (B) TST (B) tWRTI.CK
0072DD
tTSTSET
Shift and Rotate
Opcode
D062DD 0063DD 0060DD 0061DD 0003DD
Mnemonic
ASR(B) ASL (B) ROR(B) ROL(B) SWAB
Description
~Gear destination
Complemenrtklstination Increment destltmtion Decrement des;tfuatfon Negate destination Test destinatii:>p.. Read/lock destfu.ation, write/unlock RO int.o destination Test destination, set low bit
N zvc
0 100
* "1'
0 o;;l: ,
* * *
* * *
* * * *
'* * 0 0
* *0
*
*
0 * -,·:.<,,f,:;
Description
Arithmetic shift. right
Arithmetic shift left Rotiite right Rotate left Swap bytes
Nz vc
..
** * *
* * * * * * * *
* * * *
* * 0 0
Multiple-precision
Opcode
0055DD D056DD 0067DD
Mnemonic
ADC(B) SBC (B) SXT
Description
Add carry Subtract carry Sign extend
N z v c
* * * * * * * *
* 0
Confidential ~nd Prowetary
B-1
Preliminary
PNcessor Status (PS) Word 0petat0rs
Opcode
1067DD 1064SS
Mnemonic
MFPS MTPS
Description
Move byte from PS Move. byte to PS
· Double Operand
General
Opcode
DlSSDD 02SSDD 06SSDD 16SSDD 072RSS 073RSS 070RSS 071RSS
Mnemonic
MOV(B) CMP(B) ADD SUB +ASH tASHC tMUL
+mv
Description
Move source to destination Compare source to destination Add source to destination Subtract source from destination Arithmetic shift Arithmetic shift combine~ Multiply Divide
Logical
Opcode D3SSDD 04SSDD 05SSDD 074RDD
Mnemonic
BIT (B) BIC (B) BIS (B) XOR
Description
Bit test Bit dear Bit set Exclusive OR
· Program Control
Branch
Opcode or Base Code
000400 001000 001400 100000 100400 102000 102400 103000 103400
Mnemonic
BR BNE BEQ BPL BMI BVC BVS BCC BCS
Descripdon
Branch unconditional Branch if not equal to zero Branch if equal to zero Branch if plus Branch if minus Branch if overflow is clear Branch if overflow is set Branch if carry is clear Branch if carry is set
AppendiXB
' ,'
';'\
Nz v c
* * 0
* * * *
N z v c
* * 0 * * * * * * * * * * * * * * * * * * * * * *0* * * * *
Nz vc
* * 0 * *0 * * 0 * *0
N z v c
B-2
Confidential and Proprietary
-·
Signed Conditional Brandt
Opcode or Base Code
002000 002400 003000 003400
Mnemonic
BGE BLT BGT BLE
Unsigned Conditional Brandt
Opcode or Base Code
101000 101400 103000 103400
Mnemonic
BHI BLOS BHIS BLO
Jump and Subroutine
Opcode or Base Code
OOOlDD 004RDD 00020R 077ROO
Mnemonic
JMP JSR RTS SOB
'Ilap and Interrupt
Opcode or Base Code
104000 to 104377 104400 to 104777 000003 000004 000002 000006
Mnemonic
EMT
TRAP
BPT
IOT
RTI RTT
Preliminary
ApPendixB
Description
N z vc
Branch if greater than or equal to zero -
Branch if less than zero
Branch if greater than zero
Branch if less than or equal to zero
Description
Bran.chi£ higher Branchif lower or same Branch if higher 9r same Branch iflower
Nz vc
Description
Nz vc
Jump
Jump to subroutine
Return from subroutine Subtract one and branch if not equal to zero
Description
Emulator trap
Trap Breakpoint trap Input/output trap
Return from interrupt Return from interrupt
Nz vc
* * * *
* * * * * * * * * * * * * * * * * * * *
Confidential·ancl ·Proprietary
B-3
...
Miscellaneous Program Control
Opcode or Base Code
0070DD 0064NN 00023N
Mnemonic
tCSM tMARK tSPL
Preliminaey ·.
Description Call to supervisor mode Mark Set priority level
Appentti:]J N z vc
Miscellaneous
Opcode or Base Code
000000 000001 000005 000007 1066SS 0066SS 0065SS 1065SS
Mnemonic
HAIT WAIT
RESET MFPT tMTPD tMTPI tMFPD tMFPI
Description
Nz vc
Halt
\1Uaitforinterrupt
-
Reset external bus ·
Move processor type
Move to previous data space Move to previous instruction space Move from previous data space
* * 0
* * 0 * *0
Move from previous instruction space * * 0
· Condition Code Operators
Opcode or
Base Code
000241 000242 000244 000250 000257 000261 000262 000264 000270 000277 000240
Mnemonic
CLC
CLV CLZ CLN CCC SEC SEV SEZ
SEN
sec
NOP
Description
Cleare Clear V Clear Z Clear N
Clear all CC bits
SetC SetV SetZ SetN Set all CC bits No operation
N z V· c
0
0
0 0
0 0 0 o.
1 1 1 l 1 1 1 1
B-4
G.lnfidential and. Proprietary
used 'Die following electrical circuit configurations are usecl in performing the. de tests. A definition of
the parameters in the tests is contained in Table C.1.
Current flow into the device is a negative value a:nd current flow out ofthe device is a p6sitive
value.
.
.
·
High (H) assertion signals are true or asst;rtedfot high-level voltases and false or negated for low-
level voltages. Low (L) assertion si~nals are. true or· asserted for lmv"level voltages and false or
negated for high"level voltages.
·
Table C.1 · de T"st Specification Parameters
Syri.bol ·Name/Definition
Vm High-level input voltage-An input voltagelevd within the more positive (lessnegative)
of the two ranges of values used to represent the binary variables.
V1L
Low-level input voltage-An input voltage level within the less positive (more negative)
of the two ranges of values used to represent the binary variables.
Im
High-level input current-The current int:Q an input when a high level voltage is applied
to that input.
·
!IL
Low-level input current-The current into an input when a low level voltage is applied to
that input.
V1c
Input clamp voltage-An input.·1'(Gltage in a regionof ~ativdy low differential resistance
that serves to limit the input·vblt:age swin~. This,,parameter applies to TTL inputs that
have clamping diodes to ground that beci>me forward biased for negative excursions of
the input voltage.
ITM
Input current at maximum input voltage-The current into an input when the maximum
input voltage is applied to t~at input. This parameter applies to TTL inputs.
V08 High-level output voltage-The volt.age at an output terminal with input conditions
applied that according to the specification will establish a high level at the output.
VOL Low-level output voltage-The voltage at the output terminal with input conditions applied that according to the specification will establish a low level at the output.
Ioi.
Low-level output current-The current into an output with input conditions applied that
according to the specification will establish a low level at the output.
los
Short circuit output current-,The current into 'an Olltptitwhen that output is short-
circuited to ground with ihput conditions applied tO establish the output logic level
farthest from ground potential. This parameter applies to TTL outputs.
lozL Low-level output leakage current-The current from an output with a low level applied to
the output and with the input conditions applied so that the output is a high impedance.
ConfidentW and .Proprietary
C-1
__, ,.....,.m..,,,,..,.........,.,_ _,._ _ _ _ ·~..,,_,,,,,..·_..,,..,..&·""''
._..,..,llllilBl!""'-·---=---·--·-h---~·---,--_,
Preliminary
AppendixC
Symbol Name/Definition
Iom High-level output leakage current_:The current from an output with a high-level applied
to the output and with the input conditions applied so that the output is a high
impedance.
lee
Positive power supply current-The current into the Vcc input from the power supply. Vcc
represents the positive power supply voltage applied to the device.
IEE
Negative power supply current-The current into theVEE supply terminal of the device.
VEE represents the negative power supply voltage applied to the device.
c..
Input capacitance-The capacitance measured at the specified pins with power applied to
the device.
R.
Real input impedance-The real portion of the input impedance measured at the
specified pins with power applied to the device.
INPur CONDITIONS
V1HORVtlAS DICTATED BY THE LOGIC
Vee
loH
OPEN COLLECTOR OUTPUTS
(+) VoH
GND
TOTEM POLE OUTPUTS
-=
VoH
l
DC TEST CIRCUIT Cl
HtoH
!
T--+
Vee
IN PUT CONDITIONS
VtH ORV1LAS DICTATED BY LOGIC
GND
DC TEST CIRCUIT C2
T-
C.-2
Confidential and Proprietary
.,.· , I
IRNEPMUAT!.SNING {. OPEl\j
AppendkC
Vee Vee
OIJTPOTtsl OPEN
GNO
DC TEST CIRCUIT C3
l10Rl1H - - - -
REMAINING INPtlTS
Vee
GNO
.OUTPUT!SI
00 TEST CIRCUIT C4
Vee Vee
OUTPUT(SI OPEN GNO
DC TEST CIRCUIT C5
Confidential and Proprietary
C-3
-····
Pre.fD.11.tla.'rY.········.
IGNNPDUTORCO4.N.5DIVTAIOS.·NS {
DICTATED BYTHE
LOGIC
·
Vee
GND
! (-J·os
DC TEST CIRCUIT C6
+ Vee
'cc
INPUTCONDITIONS { . GNDOR 4.5VAS.
DICTATED BY THE
LOGIC
GND
OUTPUT(S) OPEN
OC T£ST CIRCUIT C7
INPUT CONDITIONS . { GND OR 3.0 VAS
OICTIUED 6YTHE LOGIC
Vee Vee
GND
DC TEST CIRCUIT CS
lozL(+J
l
T
C-4
Confidential~ Proprietary
Vee Vee
INPUT CONDITIONS { GND OR 3.0 V /IS DICTATED BY THE
LOGIC
GNO
VOL
!
DC TEST CIRCUIT C9
AppendixC
Confidential and Proprietary
C-5
Figure D.1 shows the waveforms and symbols used to measure the propagation delay for some
input and output voltages.
INPUT
OUTPUT VOLTAGE IN PHASE
tLH t;:____
1.5V
1.5 v
OUTPUT VOLTAGE OUT OF PHASE .
1.5V
Figure D.1 ·Input/Output Propagation Delay Symbols
Confidential and Proprietary
D-1
Figure E.1 and E.2 ~r9W the configurations of the molded plastic/t:er(Unic dga!-jnllpe pa#ges.
Figure E.3 shOws the configw.-ation of the DCTll 40-pin ceramic package. ".rabJe ~.lli:sts'i:he pin
and package dimensions.
Figure E.4 sho-.vs the dime~Si(li;i:; for the DC]ll 60-pin ceramic pa~!: ~l}d figµJ;t: &·:? shCl\ys the
dimensions for. the FPJU 40-pin ceratnic package.
·. '
..
Figure E.6 sh<>w$ the oo~figuratioit.and dimensions of the cerquad.ililine~. Figure E. 7 shows the configuratiti>n (If the pin grid array (PGA) p~ckage.and T~l~ E;2 U$ts.i:he
package dimensions.
Table E.1 ·Molded DIP Package Dimensions
Package r4·~pin
16·pm ···ig~pin · 20-pin
28-pin
40·pin
Dimension Min. Max. Min. Max. Mcin· Max. Min. Max.1~ ·MuFMin. ·Ma,x-.
A
0.28.
0.29 .0.28
__, --
-
:. - '
0.2'l O,;J8
.-·' ·-' '
'
0.29
0.28
0.29 ;0.58 '. ' -
0.59
0.58
0.59 ·. ·' - ·~
B
0.605 0.705 0.705 0.805 0.805 0.905 0.905 1.05 1.305 1.405 1.905 2:05
c
0.08 0.18 0.08 0.18 o.os 0.18 0.08 o.1s ..<toe: !'.Li&.cl.os o.1s.
D
0,12
o..J,2 - 0.12 - . 0;14
0.12
F
0.014 0.022 0.014 0.022 O.o.14 0.022 0.014 0.022 0.014 o.o~.0.014 0.022
G
0.015 0.06 0.015 0.06 0.015 0.06 0.015 0.06 0.015 0.06 0.015 0.06
H
0.044 0.07 0.044 0.07 0.044 0.07 0.044 0.07 0.044 0.07 0.044 0.07
I
0.008 0.075 0.008 0.075 0.008 Q.b75.0i008 0.075 0.008 0.075 0.008 0.075
J
0.008 0.014 0.008 0.014 0.008'0~014 0.008 0.014 0.012 0.02 0.012 0.02
:Fe
0.4
0.4
0.4
0.4
0.7
0.7
L
0.35
0.35
0.35·
0:35.
0.35' .:.:... 0.35
*Non-cumulative at seating plane
Confidential·ancl Proprietary
E-1
_::-d-1
,...
B
·I
:T En¥~ ¥vvnt --J d-- -11--F
14-PIN
16-PIN
11:::::::~
-11--H
~~I
C
B--
~O
18-PlN
L I· , . .B . . · .
~
F4I
f-- K --J Figure.E.1·14-, 16-, is- and 20-pin Plastic/Ceramic DIP Configurations
E-2
Confidential and Proprietary
-
~·.·
',.(
J
re::::::::::::::::J 1--l 1--
~J
1--K-\
Figure E.2 · 28- and 40-pin Plastic/Ceramic DIP Configurations
T A
1~1~~. ·~·r--,
~+ ~~. Jt] ±~i'7~~._,--.... +'. L ... --1· K __
Figure E.3 · DCT11 40-pin Ceramic DIP Configuration and Dimensions
- - - - - - - - .100x 29" 2.900< .008 _ _ _ _ _ _ __
. 100
TOL NON ACCUM .
±.008
r-.211 MAX
I
~·~r
.010 ± :::~
Figure E.4 · DC]ll 60-pin Ceramic DIP Configuration and Dimensions
E:.4
Confidential and :PtopHetacy
....
INOEXMAAK
Figure E.5 · FPJll 40-pilt-Cemmic DIPConjigurilWonamJDimensiom
MINIMUM CLEAR LEADFRAME ZONE
.020MIN
-I I- .030 MIN
Number of Leads
44 68 84 132 164
Dimensions
A
B
0.6
0.02
0.9
0.02
1.1
0.02
0.9
0.012
1.1
0.012
c
0.05 0.05 0.05 0.025 0.025
D 0.825 1.125 1.325 1.125 1.325
Figure E. 6 · Cerquad, Package Configuration and Dimensions
Cpnfidential and Propri~
PrelimifUlt\y
Table E.2 · Pin Grid kray Package Dimensions
Type*
Pins
··Dimensions
ABc DE F GHJ K
72 1.17 1.0 0.1 0.·05 0.16 0;1 0.36 b.145 0.88 0.17
132 1.4 1.3 0.1 N/A N/A N/A N/A N/A N/A 0.18
M,IE,F 132 i.4 1.3 0.12 0.05 0.12 OJ,12 0.35 o.n 0.74 0.18
BCI3
132 · '1.4 1.3 0.12 N/A ', N/A N{A N/A N/At N/A :Q.18
*Package Identification: ·
Type li=VAXBI bus BGAI and BIIC chips
M= V-11 M chip I/E = V-11 JjE chip
F =V-11 F chip
BCI3 = VAXBI bus BCl3 chip
E-7
KEY PIN 1
Pre·J.:¥-&.:U·.l...:..-.·1··.·'(
'
''
A
I!
r·MMA<
l 1.1 MAX,
l
PIN A1 2 INDICATOR
STANDOFF'
---i--H
G
0 ::::=~::==~ I ~~-£- fl- -....F....
PADS'
0.018 DIA
STANDOFF PINS
r:. .J i.to.OOB
~
0.05±0,005
r--..,
'---
PIN A1 ANO
PACKAGE IDENTIFICATION
E
(REFER TO TABLE E2)
1Key pin is nonelectrical and is for alignment on type l1 chips only.
2Pin Al is indicated by a protrusion on the standoff collar.
'Standoff pins are positioned at the four exterior corners of the 132-pin PGA and at the four interior corners of the 72-pin PGA.
*Capacitor pads not available on the ll and BCI3 PGA versions.
Figure E. 7 · PGA Package Configuration and Dimensions
E-8
Confidential and· Proprkt:aty
''\---~~~--~~~~~---~~
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