CCG3 Family CCG3 Architecture Technical Reference Manual (TRM) No. 002-04130 Rev. ** November 25, 2015 Book 1 of 2 Cypress Semiconductor 198 Champion Court
CCG3 Family. CCG3 Architecture Technical Reference. Manual (TRM). No. 002-04130 Rev. **. November 25, 2015. Book 1 of 2.
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CCG3 Family
CCG3 Architecture Technical Reference Manual (TRM)
Document No. 002-04130 Rev. ** November 25, 2015
Book 1 of 2
Cypress Semiconductor 198 Champion Court
San Jose, CA 95134-1709 Phone (USA): +1.800.858.1810 Phone (Intnl): +1.408.943.2600
http://www.cypress.com
Copyrights
License © 2015, Cypress Semiconductor Corporation. All rights reserved. This software, and associated documentation or materials (Materials) belong to Cypress Semiconductor Corporation (Cypress) and may be protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Unless otherwise specified in a separate license agreement between you and Cypress, you agree to treat Materials like any other copyrighted item. You agree to treat Materials as confidential and will not disclose or use Materials without written authorization by Cypress. You agree to comply with any Nondisclosure Agreements between you and Cypress. If Material includes items that may be subject to third party license, you agree to comply with such licenses.
Copyrights Copyright ©2015 Cypress Semiconductor Corporation. All rights reserved. All trademarks or registered trademarks referenced herein are the property of their respective owners.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. The information in this document is subject to change without notice and should not be construed as a commitment by Cypress. While reasonable precautions have been taken, Cypress assumes no responsibility for any errors that may appear in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Cypress.
Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Flash Code Protection Cypress products meet the specifications contained in their particular Cypress Datasheets. Cypress believes that its family of CCG3 products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products.
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CCG3 TRM, Document No. 002-04130 Rev. **
Contents Overview
Section A: Overview
13
1. Introduction ........................................................................................................... 15
2. Getting Started ...................................................................................................... 21
3. Document Construction ......................................................................................... 23
Section B: CPU System
27
4. Cortex-M0 CPU ..................................................................................................... 29
5. Interrupts .............................................................................................................. 35
Section C: Memory System
43
6. Memory Map ......................................................................................................... 45
Section D: System-Wide Resources
47
7. I/O System ............................................................................................................ 49
8. Clocking System .................................................................................................... 57
9. Power Supply and Modes ...................................................................................... 63
10. Chip Operational Modes ........................................................................................ 67
11. Watchdog Timer .................................................................................................... 69
12. Reset System ........................................................................................................ 73
13. Device Security ..................................................................................................... 75
Section E: Digital System
77
14. Serial Communications (SCB) ................................................................................ 79
15. Timer, Counter, and PWM .................................................................................... 117
16. Cryptography Block ............................................................................................. 137
17. USB Full Speed (USB FS) ................................................................................... 157
Section F: USB Power Delivery
169
18. USB Power Delivery ............................................................................................ 171
Section G: Program and Debug
187
19. Program and Debug Interface .............................................................................. 189
20. Nonvolatile Memory Programming........................................................................ 197
Glossary
211
Index
227
CCG3 TRM, Document No. 002-04130 Rev. **
3
Contents Overview
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CCG3 TRM, Document No. 002-04130 Rev. **
Contents
Section A: Overview
13
Document Revision History ..............................................................................................................13
1. Introduction
15
1.1 Top Level Architecture............................................................................................................16 1.2 Features..................................................................................................................................16 1.3 CPU and Memory Subsystem ................................................................................................17
1.3.1 Processor...............................................................................................................17 1.3.2 Interrupt Controller .................................................................................................17 1.4 USB PD Subsystem................................................................................................................17 1.4.1 USB-PD physical layer...........................................................................................17 1.4.2 VCONN Input .........................................................................................................17 1.4.3 ADC .......................................................................................................................17 1.4.4 Analog Crossbar ....................................................................................................17 1.4.5 Charger Detection..................................................................................................17 1.5 System-Wide Resources ........................................................................................................18 1.5.1 Clocking System ....................................................................................................18 1.5.2 Power System........................................................................................................18 1.5.3 GPIO ......................................................................................................................18 1.6 Fixed-Function Digital .............................................................................................................18 1.6.1 Timer/Counter/PWM Block.....................................................................................18 1.6.2 Serial Communication Block (SCB) .......................................................................18 1.6.3 Crypto ....................................................................................................................19
2. Getting Started
21
2.1 Support ...................................................................................................................................21 2.2 Product Upgrades...................................................................................................................21 2.3 Development Kits....................................................................................................................21
3. Document Construction
23
3.1 Major Sections ........................................................................................................................23 3.2 Documentation Conventions...................................................................................................23
3.2.1 Register Conventions.............................................................................................23 3.2.2 Numeric Naming ....................................................................................................23 3.2.3 Units of Measure....................................................................................................24 3.2.4 Acronyms ...............................................................................................................24
Section B: CPU System
27
Top Level Architecture .....................................................................................................................27
4. Cortex-M0 CPU
29
4.1 Features..................................................................................................................................29 4.2 Block Diagram ........................................................................................................................30 4.3 How It Works ..........................................................................................................................30
CCG3 TRM, Document No. 002-04130 Rev. **
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4.3.1 4.3.2 4.3.3 4.3.4 4.3.5
Registers ............................................................................................................... 30 Operating Modes ................................................................................................... 32 Instruction Set........................................................................................................ 32 Systick Timer ......................................................................................................... 33 Debug .................................................................................................................... 33
5. Interrupts
35
5.1 Features ................................................................................................................................. 35 5.2 How It Works .......................................................................................................................... 35 5.3 Interrupts and Exceptions - Operation.................................................................................... 36
5.3.1 Interrupt/Exception Handling in CCG3 .................................................................. 36 5.3.2 Level and Pulse Interrupts ..................................................................................... 36 5.3.3 Exception Vector Table .......................................................................................... 37 5.4 Exception Sources.................................................................................................................. 37 5.4.1 Reset Exception .................................................................................................... 37 5.4.2 Non-Maskable Interrupt (NMI) Exception .............................................................. 38 5.4.3 HardFault Exception ..............................................................................................38 5.4.4 Supervisor Call (SVCall) Exception ....................................................................... 38 5.4.5 PendSV Exception................................................................................................. 38 5.4.6 SysTick Exception ................................................................................................. 38 5.5 Interrupt Sources .................................................................................................................... 39 5.6 Exception Priority.................................................................................................................... 39 5.7 Enabling/Disabling Interrupts.................................................................................................. 40 5.8 Exception States..................................................................................................................... 40 5.8.1 Pending Exceptions ............................................................................................... 41 5.9 Stack Usage for Exceptions ................................................................................................... 41 5.10 Interrupts and Low-Power Modes........................................................................................... 41 5.11 Exception - Initialization and Configuration ............................................................................ 42 5.12 Registers ................................................................................................................................ 42 5.13 Associated Documents...........................................................................................................42
Section C: Memory System
43
Top Level Architecture ..................................................................................................................... 43
6. Memory Map
45
6.1 Features ................................................................................................................................. 45 6.2 How It Works .......................................................................................................................... 45
Section D: System-Wide Resources
47
Top Level Architecture ..................................................................................................................... 47
7. I/O System
49
7.1 Features ................................................................................................................................. 49 7.2 Block Diagram ........................................................................................................................ 50 7.3 GPIO Drive Modes ................................................................................................................. 51
7.3.1 High-Impedance Analog ........................................................................................ 52 7.3.2 High-Impedance Digital ......................................................................................... 52 7.3.3 Resistive Pull-Up or Resistive Pull-Down .............................................................. 52 7.3.4 Open Drain Drives High and Open Drain Drives Low............................................ 52 7.3.5 Strong Drive ...........................................................................................................52 7.3.6 Resistive Pull-Up and Resistive Pull-Down ........................................................... 52 7.4 Slew Rate Control................................................................................................................... 53 7.5 CMOS LVTTL Level Control................................................................................................... 53 7.6 GPIO-OVT .............................................................................................................................. 53
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7.7 High-Speed I/O Matrix ............................................................................................................53 7.8 Firmware Controlled GPIO .....................................................................................................53 7.9 I/O Port Reconfiguration .........................................................................................................54 7.10 I/O State on Power Up............................................................................................................54 7.11 Behavior in Low-Power Modes ...............................................................................................54 7.12 GPIO Interrupt ........................................................................................................................54
7.12.1 Features.................................................................................................................54 7.12.2 Interrupt Controller Block Diagram.........................................................................54 7.12.3 Function and Configuration....................................................................................54 7.13 Registers.................................................................................................................................55
8. Clocking System
57
8.1 Block Diagram ........................................................................................................................57 8.2 Clock Sources.........................................................................................................................59
8.2.1 Internal Main Oscillator ..........................................................................................59 8.2.2 Internal Low-speed Oscillator ................................................................................59 8.2.3 External Clock........................................................................................................59 8.3 Clock Distribution....................................................................................................................59 8.3.1 HFCLK Input Selection ..........................................................................................59 8.3.2 HFCLK Predivider Configuration............................................................................59 8.3.3 SYSCLK Prescaler Configuration ..........................................................................60 8.3.4 Peripheral Clock Divider Configuration ..................................................................60 8.4 Low-Power Mode Operation ...................................................................................................61 8.5 Register List............................................................................................................................61
9. Power Supply and Modes
63
9.1 Block Diagram ........................................................................................................................63 9.2 Power System Requirement Overview ...................................................................................63 9.3 Power Modes..........................................................................................................................64 9.4 Power Domain Model Diagram...............................................................................................64 9.5 Mode Transitions ....................................................................................................................65
10. Chip Operational Modes
67
10.1 Boot ........................................................................................................................................67 10.2 User ........................................................................................................................................67 10.3 Privileged ................................................................................................................................67 10.4 Debug .....................................................................................................................................67
11. Watchdog Timer
69
11.1 Features..................................................................................................................................69 11.2 Block Diagram ........................................................................................................................69 11.3 How It Works ..........................................................................................................................70
11.3.1 Enabling and Disabling WDT .................................................................................70 11.3.2 WDT Interrupts and Low-Power Modes.................................................................70 11.3.3 WDT Reset Mode ..................................................................................................70 11.4 Register List ...........................................................................................................................71
12. Reset System
73
12.1 Reset Sources ........................................................................................................................73 12.1.1 Power-on Reset .....................................................................................................73 12.1.2 Brownout Reset .....................................................................................................73 12.1.3 Watchdog Reset ....................................................................................................73 12.1.4 Software Initiated Reset.........................................................................................73 12.1.5 External Reset .......................................................................................................74
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12.1.6 Protection Fault Reset ........................................................................................... 74 12.2 Identifying Reset Sources....................................................................................................... 74 12.3 Register List............................................................................................................................ 74
13. Device Security
75
13.1 Features ................................................................................................................................. 75 13.2 How It Works .......................................................................................................................... 75
Section E: Digital System
77
Top Level Architecture ..................................................................................................................... 77
14. Serial Communications (SCB)
79
14.1 Features ................................................................................................................................. 79 14.2 Serial Peripheral Interface (SPI)............................................................................................. 79
14.2.1 Features ................................................................................................................ 79 14.2.2 General Description ............................................................................................... 80 14.2.3 SPI Modes of Operation ........................................................................................ 80 14.2.4 Easy SPI (EZSPI) Protocol .................................................................................... 85 14.2.5 SPI Registers......................................................................................................... 88 14.2.6 SPI Interrupts......................................................................................................... 88 14.2.7 Enabling and Initializing SPI .................................................................................. 89 14.2.8 Internally and Externally Clocked SPI Operations ................................................. 90 14.3 UART...................................................................................................................................... 92 14.3.1 Features ................................................................................................................ 92 14.3.2 General Description ............................................................................................... 93 14.3.3 UART Modes of Operation .................................................................................... 93 14.3.4 UART Registers..................................................................................................... 98 14.3.5 UART Interrupts..................................................................................................... 98 14.3.6 Enabling and Initializing UART .............................................................................. 98 14.4 Inter Integrated Circuit (I2C) .................................................................................................100 14.4.1 Features ..............................................................................................................100 14.4.2 General Description .............................................................................................100 14.4.3 Terms and Definitions ..........................................................................................100 14.4.4 I2C Modes of Operation ......................................................................................101 14.4.5 Easy I2C (EZI2C) Protocol ..................................................................................103 14.4.6 Memory Array Write.............................................................................................103 14.4.7 Memory Array Read ............................................................................................103 14.4.8 I2C Registers .......................................................................................................104 14.4.9 I2C Interrupts .......................................................................................................105 14.4.10 Enabling and Initializing the I2C ..........................................................................105 14.4.11 Internal and External Clock Operation in I2C ......................................................106 14.4.12 Wake up from Sleep ............................................................................................107 14.4.13 Master Mode Transfer Examples.........................................................................108 14.4.14 Slave Mode Transfer Examples........................................................................... 110 14.4.15 EZ Slave Mode Transfer Example....................................................................... 112 14.4.16 Multi-Master Mode Transfer Example.................................................................. 114
15. Timer, Counter, and PWM
117
15.1 Features ...............................................................................................................................117 15.2 Block Diagram ......................................................................................................................118
15.2.1 Enabling and Disabling Counter in TCPWM Block .............................................. 118 15.2.2 Clocking ............................................................................................................... 118 15.2.3 Events Based on Trigger Inputs........................................................................... 119 15.2.4 Output Signals ..................................................................................................... 119
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15.2.5 Power Modes .......................................................................................................121 15.3 Modes of Operation ..............................................................................................................121
15.3.1 Timer Mode ..........................................................................................................122 15.3.2 Capture Mode ......................................................................................................124 15.3.3 Quadrature Decoder Mode ..................................................................................126 15.3.4 Pulse Width Modulation Mode .............................................................................129 15.3.5 Pulse Width Modulation with Dead Time Mode ...................................................132 15.3.6 Pulse Width Modulation Pseudo-Random Mode .................................................134 15.4 TCPWM Registers ..............................................................................................................136
16. Cryptography Block
137
16.1 Features................................................................................................................................137 16.2 Block Diagram ......................................................................................................................138
16.2.1 Block Application Overview..................................................................................138 16.2.2 Sub Block Descriptions ........................................................................................139 16.3 Block Operation ....................................................................................................................150 16.3.1 Reset and Initialization.........................................................................................150 16.3.2 Functional Modes and Usage Requirements.......................................................150 16.4 Block Interface Requirements...............................................................................................154 16.4.1 Functional Timing Requirements and Diagrams ..................................................154 16.4.2 Bandwidth/Latency Requirements .......................................................................154 16.4.3 Bit/Byte Ordering..................................................................................................154 16.4.4 Data Underrun/Overrun .......................................................................................154 16.5 Power Architecture and Modes.............................................................................................155 16.5.1 SRSS-Lite ............................................................................................................155
17. USB Full Speed (USB FS)
157
17.1 Features................................................................................................................................157 17.2 Block Diagram ......................................................................................................................158
17.2.1 USB Physical Layer (USB PHY) ..........................................................................158 17.2.2 Serial Interface Engine (SIE) ...............................................................................158 17.2.3 Arbiter ..................................................................................................................158 17.3 How it Works.........................................................................................................................159 17.3.1 USB Physical Layer (USB PHY) ..........................................................................159 17.3.2 Endpoints .............................................................................................................160 17.3.3 Transfer Types .....................................................................................................161 17.3.4 Interrupts..............................................................................................................161 17.4 Logical Transfer Modes ........................................................................................................162 17.4.1 Store and Forward Mode .....................................................................................164 17.4.2 Control Endpoint Logical Transfer........................................................................165 17.5 Register Summary ................................................................................................................166
Section F: USB Power Delivery
169
Top Level Architecture ...................................................................................................................169
18. USB Power Delivery
171
18.1 Features................................................................................................................................171 18.2 Block Diagram ......................................................................................................................172 18.3 Configuration Options ...........................................................................................................173 18.4 Block Applications.................................................................................................................173
18.4.1 CC Block ..............................................................................................................173 18.4.2 CSA Block............................................................................................................174 18.4.3 20VReg Block ......................................................................................................175 18.4.4 UVOV Block .........................................................................................................176
CCG3 TRM, Document No. 002-04130 Rev. **
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18.4.5 18.4.6 18.4.7 18.4.8 18.4.9 18.4.10 18.4.11 18.4.12 18.4.13
SBU_Sw Block ....................................................................................................177 VDDD_Sw Block..................................................................................................178 NGDO Block ........................................................................................................179 DPSLP_Ref Block ...............................................................................................180 CPUMP block ......................................................................................................181 VCONN_Term Block ............................................................................................182 VBUS_DISCHG Block .........................................................................................183 CHGDET Block....................................................................................................184 ADC Block ...........................................................................................................186
Section G: Program and Debug
187
Top Level Architecture ...................................................................................................................187
19. Program and Debug Interface
189
19.1 Features ...............................................................................................................................189 19.2 Functional Description ..........................................................................................................189 19.3 Serial Wire Debug (SWD) Interface......................................................................................190
19.3.1 SWD Timing Details.............................................................................................191 19.3.2 ACK Details .........................................................................................................192 19.3.3 Turnaround (Trn) Period Details ..........................................................................192 19.4 Cortex-M0 Debug and Access Port (DAP) ...........................................................................192 19.4.1 Debug Port (DP) Registers ..................................................................................192 19.4.2 Access Port (AP) Registers .................................................................................193 19.5 Programming the CCG3 Device ...........................................................................................193 19.5.1 SWD Port Acquisition ..........................................................................................193 19.5.2 SWD Programming Mode Entry ..........................................................................194 19.5.3 SWD Programming Routines Executions ............................................................194 19.6 CCG3 SWD Debug Interface................................................................................................194 19.6.1 Debug Control and Configuration Registers ........................................................194 19.6.2 Breakpoint Unit (BPU) .........................................................................................194 19.6.3 Data Watchpoint (DWT).......................................................................................194 19.6.4 Debugging the CCG3 Device ..............................................................................195 19.7 Registers ..............................................................................................................................195
20. Nonvolatile Memory Programming
197
20.1 Features ...............................................................................................................................197 20.2 Functional Description ..........................................................................................................197 20.3 System Call Implementation.................................................................................................198 20.4 Blocking and Non-Blocking System Calls.............................................................................198
20.4.1 Performing a System Call ....................................................................................198 20.5 System Calls.........................................................................................................................199
20.5.1 Silicon ID .............................................................................................................199 20.5.2 Configure Clock ...................................................................................................200 20.5.3 Load Flash Bytes .................................................................................................201 20.5.4 Write Row ............................................................................................................201 20.5.5 Program Row.......................................................................................................202 20.5.6 Erase All ..............................................................................................................203 20.5.7 Checksum............................................................................................................203 20.5.8 Write Protection ...................................................................................................204 20.5.9 Non-Blocking Write Row......................................................................................205 20.5.10 Non-Blocking Program Row ................................................................................206 20.5.11 Resume Non-Blocking .........................................................................................206 20.6 System Call Status ...............................................................................................................207
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20.7 Non-Blocking System Call Pseudo Code .............................................................................208
Glossary
211
Index
227
CCG3 TRM, Document No. 002-04130 Rev. **
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CCG3 TRM, Document No. 002-04130 Rev. **
Section A: Overview
CCG3 Technical Reference Manual consists of 2 books. This CCG3 Architecture Technical Reference Manual is Book 1 of 2. For details on registers, refer to CCG3 Registers Technical Reference Manual (Book 2 of 2).
This section encompasses the following chapters: Introduction chapter on page 15 Getting Started chapter on page 21 Document Construction chapter on page 23
Document Revision History
Table 3-1. Document Revision History
Revision
Issue Date
Origin of Change
**
11/25/2015
VGT New CCG3 TRM.
Description of Change
CCG3 TRM, Document No.: 002-04130 Rev. **
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CCG3 TRM, Document No.: 002-04130 Rev. **
1. Introduction
CCG3 is a USB Type-C port controller that complies with the latest USB Type-C and USB Power Delivery standards. CCG3 provides a complete USB Type-C and USB Power Delivery port control solution for notebooks, dongles, monitors, docking stations and power adapters. CCG3 uses Cypress's proprietary M0S8 technology with a 32-bit, 48-MHz ARM® Cortex® -M0 processor with 128-KB flash, 8-KB SRAM, 20 GPIOs, full-speed USB device controller, a Crypto engine for authentication, a 20 V-tolerant regulator, and a pair of 1W FETs to generate a 5 V (VCONN) supply, which powers cables. CCG3 also integrates two pairs of gate drivers to control external VBUS FETs and system level ESD protection. CCG3 devices have these characteristics: High-performance, 32-bit 48 MHz Cortex-M0 CPU core Configurable Timer/Counter/PWM blocks Configurable Serial Communication blocks to support I2C, SPI, UART Integrated USB-PD BMC transceiver Integrated VCONN FETs Configurable resistors RA, RP and RD Hardware Crypto block enables Authentication Full-Speed USB Device Controller supporting Billboard Device Class This document describes each function block of the CCG3 device in detail. This information will help designers to create system-level designs.
CCG3 TRM, Document No.: 002-04130 Rev. **
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Introduction
1.1 Top Level Architecture
Figure 1-1 shows the major components of the CCG3 architecture. Figure 1-1. CCG3 Family Functional Block Diagram
CCG3
32-bit
AHB-Lite
System Resources Lite
Power Sleep Control
WIC POR REF
PWRSYS
Clock Clock Control
WDT IMO ILO
Reset Reset Control
XRES
CPU Subsystem
SWD/TC
Cortex M0
48 MHz
FAST MUL NVIC, IRQMX
SPCIF
FLASH 2x64 KB
Read Accelerator
SRAM 8 KB
SRAM Controller
ROM 8 KB
ROM Controller
Peripherals PCLK
System Interconnect (Single Layer AHB) Peripheral Interconnect (MMIO)
USB-PD SS
USB-FS
Test DFT Logic DFT Analog
IOSS GPIO (3 x ports) 4 x TCPWM 4 x SCB CRYPTO
HV REG OVP OCP
2 x 2 ANALOG XBAR 2 X VCONN FET
2 X GATE DRIVER CHG DET CC BB PHY ADC / ACA
Power Modes Active /Sleep Deep Sleep
High Speed I/O Matrix
22 x GPIOs, 2 x OVTs IO Subsystem
Pads, ESD
FS-PHY
1.2 Features
CCG3 family of USB Type-C cable controllers has these major components: 32-bit Cortex-M0 CPU at 48 MHz 128 KB flash and8 KB SRAM Integrated USB-PD BMC transceiver Integrated VCONN FETs Hardware Crypto block to enable authentication Full Speed USB device controller supporting Billboard
device class. Up to 4 dedicated Timers and Counters block to meet
response times required by the USB-PD protocol Four independent run-time reconfigurable Serial
Communication Blocks (SCB) with re-configurable I2C, SPI or UART functionality. Supports one USB Type-C port
Integrated oscillator eliminating the need of external clock
Programming and debugging through serial wire debug (SWD)
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Introduction
1.3 CPU and Memory Subsystem
1.3.1 Processor
The Cortex M0 in CCG3 is a 32-bit MCU, which is optimized for low power operation with extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2 instruction set which enables fully compatible binary upwards migration of code to higher performance processors such as the Cortex M3 and M4. The Cypress option includes a hardware multiplier, which provides a 32bit result in one cycle. It includes an Interrupt Controller (the NVIC block) with 32 Interrupt inputs and also includes a WIC (Wakeup Interrupt Controller) which can wake the processor up from Deep Sleep mode. The sub-system contains 128KB of Flash organized in two banks of 64KB. The two-bank flash allows the system to maintain two copies of the firmware and update one copy while continuing to execute from the other copy.
connection detection, plug orientation detection and for establishment of the USB DFP / UFP roles. The Ra resistor on the VCONN pin is used to identify a VCONN powered accessory/dongle to the host. The Rp resistor is implemented as a current source. In accessory applications, Rp is not used. In dongle applications, the Ra resistor is connected by default between the VCONN inputs and VSS. Upon booting up, firmware can disconnect the Ra resistors from VCONN inputs to save system power.
According to the USB Type-C spec, a Type-C controller such as CCG3 must present certain termination resistor depending on its role in its un-powered state. The powered accessory and UFP roles require that Ra and Rd resistors to be present on one of the CC pins whereas the DFP role, as in a power adapter, requires both CC lines to be open with neither Rd nor Ra. To enable flexibility in such applications, CCG3 includes the resistors required in un-powered state on separate pad or pins. The dead battery Ra resistor is available on a separate pin called VCONN and dead battery Rd resistors are available on both CC pins.
1.3.2 Interrupt Controller
The CPU subsystem of CCG3 includes a nested vectored interrupt controller (NVIC) with 32 interrupt inputs and a wakeup interrupt controller (WIC), which can wake the processor from Deep-Sleep mode. The ARM Cortex-M0 CPU provides a Non Maskable Interrupt (NMI) input, which is made available to the user when it is not in use for system functions requested by the user.
1.4 USB PD Subsystem
This subsystem provides the interface to the Type-C USB port. This sub-system comprises the USB-PD transceiver, the FS USB transceiver, the high voltage regulator, OVP, OCP and supply switch blocks. This sub-system also contains the analog switches, the VCONN FETs and the 8bit ADC. This sub-system also includes all ESD required / supported on the Type-C port.
1.4.1 USB-PD physical layer
The USB-PD Physical Layer consists of a transmitter and receiver that communicate BMC encoded data over the CC channel per the PD 2.0 standard. All communication is halfduplex. The Physical Layer or PHY practices collision avoidance to minimize communication errors on the channel.
The USB-PD block includes all termination resistors (Rp, Rd and Ra) and their switches as required by the USB-PD spec. Rp and Rd resistors are required to implement
1.4.2 VCONN Input
CCG3 has an input pin called VCONN for connecting to powered accessory's power supply input pin along with the VSYS input. The VCONN input provides the required Ra termination resistor as well as leaker circuits to ensure complete discharge of the CC line upon disconnection.
1.4.3 ADC
The ADC is a 8-bit SAR ADC that is available for general purpose A-D conversion applications in the chip. The ADC can be accessed from all GPIOs and the DP/DM pins through an on-chip analog mux.
1.4.4 Analog Crossbar
CCG3 contains a set of analog switches to connect SBU1 and SBU2 pins of the Type-C connector to AUX_P and/or AUX_N of a displayPort connector. All 4 pins are provided with switchable pull-up and pull-down resistors as required by their respective specs.
1.4.5 Charger Detection
The charger detection block connected to the DP/DM pins allow CCG3 to detect conventional battery chargers conforming to BC 1.2 or other proprietary charger specifications.
CCG3 TRM, Document No. 002-04130 Rev. **
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Introduction
1.5 System-Wide Resources
1.5.1 Clocking System
The clock system for the CCG3 controller consists of the internal main oscillator (IMO) and an internal low-speed oscillator (ILO) as internal clocks and has provision for an external clock.
The IMO is the primary source of internal clocking in CCG3. It is trimmed during production to achieve the desired accuracy of +/-2%. Trim values are stored in supervisory rows in the Flash memory. Additional trim settings from Flash can be used to compensate for changes. IMO Default frequency for CCG3 is 24 MHz+/-2%.
The ILO is a 32 KHz low-power, less accurate oscillator and is used to generate clocks for peripheral operation in DeepSleep power mode.
1.5.2 Power System
The power system provides assurance that voltage levels are as required for each respective mode and will either delay mode entry (on POR for instance) until voltage levels are as required for proper function or will generate Resets (BOD detection).
CCG3 shall be able to operate from two possible external supply sources VSYS and VBUS. The VSYS supply supports operation over 2.7 - 5.5 V while the VBUS input supports operation over 4.0 - 21.5 V. The range of VSYS is valid for Powered Accessory and UFP applications not requiring a billboard device function. All DFP and DRP applications require VSYS to be over 3.0 V to ensure this device can support disconnect thresholds of 2.7 V on CC pins. All use cases requiring Billboard function require VSYS or VBUS to be over 4.4 V.
CCG3 has 3 different power modes (Active, Sleep and Deep Sleep) transitions between which are managed by the Power System. A separate power domain VDDIO is provided for the GPIOs.
VDDD, the output of the VBUS regulator and VCCD, the output of the core (1.8V) regulator, are brought out only for connecting external capacitors. These pins are not supported as a power supply sources.
1.5.3 GPIO
20 GPIOs are brought out on the 40-pin QFN and 42-ball CSP package. Every GPIO in CCG3 has the following characteristics: Eight drive strength modes including strong push-pull,
resistive pull-up and pull-down, weak (resistive) pull-up
and pull-down, open drain and open source, input only, and disabled Input threshold select (CMOS or LVTTL) Individual control of input and output disables Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode) Selectable slew rates for dV/dt related noise control
The pins are organized in three logical entities called Ports. Port 0 contains the two OVT GPIOs. Ports 1, 2 and 3 are assigned 8, 7 and 7 GPIOs respectively. During Power-on and Reset, the blocks are forced to the Disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Pin locations for Fixed-function peripherals such as USB Type-C port are also fixed in order to reduce internal multiplexing complexity. Data Output Registers and Pin State Register store, respectively, the values to be driven on the pins and the states of the pins themselves. The configuration of the pins can be done by programming of registers through software for each digital I/O Port.
Every I/O pin can generate an interrupt if so enabled and each I/O Port has an Interrupt Request (IRQ) and Interrupt Service Routine (ISR) Vector associated with it.
The I/O Ports can retain their state during Deep Sleep mode or remain ON. If operation is restored using reset then the pins will go the High-Z state. If operation is restored by an interrupt event then the pin drivers will retain their state until firmware chooses to change it. The I/Os (on data bus) do not draw current on power down.
1.6 Fixed-Function Digital
1.6.1 Timer/Counter/PWM Block
The TCPWM block of CCG3 supports 4 timers. These timers are available for internal timer use by firmware or for providing PWM based functions on the GPIOs.
1.6.2 Serial Communication Block (SCB)
The CCG3 has four SCBs, which can each implement a serial communication interface as I2C, universal asynchronous receiver/transmitter (UART), or serial peripheral interface (SPI).
The features of SCB includes: Standard I2C multi-master and slave function
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Standard SPI master and slave function with Motorola, TI, and National (MicroWire) mode
Standard UART transmitter and receiver function
1.6.3 Crypto
The CCG3 Crypto block provides cryptography functionality. It includes hardware acceleration blocks for AES (Advanced Encryption Standard) block cipher, SHA-1 (Secure Hash Algorithm) and SHA-2 hash, CRC (Cyclic Redundancy Check) and pseudo random number generation.
Introduction
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Introduction
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2. Getting Started
2.1 Support
Free support for CCG3 products is available online at http://www.cypress.com. Resources include training seminars, discussion forums, application notes, CCG3 consultants, CRM technical support email, knowledge base articles, and application notes. For application assistance, visit http://www.cypress.com/support/ or call 1-800-541-4736.
2.2 Product Upgrades
Cypress provides scheduled upgrades and version enhancements for CCGx Software Development Kit. Upgrades can be downloaded from Cypress website www.cypress.com/CCG3 in the Software section. Critical updates to system documentation are also provided in the Documentation section.
2.3 Development Kits
Development kits are available from www.cypress.com/CY4531. The Cypress Online Store contains development kits you need to successfully develop CCG3 based systems.
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Getting Started
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3. Document Construction
The following sections in this document include these topics: Section B: CPU System on page 27 Section C: Memory System on page 43 Section D: System-Wide Resources on page 47 Section E: Digital System on page 77 Section F: USB Power Delivery on page 163 Section G: Program and Debug on page 187
3.1 Major Sections
For ease of use, information is organized into sections and chapters that are divided according to device functionality. Section Presents the top-level architecture, how to get started, and conventions and overview information about any
particular area that inform the reader about the construction and organization of the product. Chapter Presents the chapters specific to an individual aspect of the section topic. These are the detailed implementa-
tion and use information for some aspect of the integrated circuit. Glossary Defines the specialized terminology used in this technical reference manual (TRM). Glossary terms are pre-
sented in bold, italic font throughout. CCG3 Registers Technical Reference Manual Supplies all device register details summarized in the technical reference
manual. These are additional documents.
3.2 Documentation Conventions
This document uses only four distinguishing font types, besides those found in the headings. The first is the use of italics when referencing a document title or file name. The second is the use of bold italics when referencing a term described in the Glossary of this document. The third is the use of Times New Roman font, distinguishing equation examples. The fourth is the use of Courier New font, distinguishing code examples.
3.2.1 Register Conventions
Register conventions are detailed in the CCG3 Registers TRM.
3.2.2 Numeric Naming
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah') and hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h' or `b' are decimal.
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Document Construction
3.2.3 Units of Measure
This table lists the units of measure used in this document.
Table 3-1. Units of Measure
Symbol °C dB fF Hz k K KB Kbit kHz k MHz M µA µF µs µV µVrms mA ms mV nA ns nV pF pp ppm SPS V
Unit of Measure degrees Celsius decibels femtofarads Hertz kilo, 1000 kilo, 2^10 1024 bytes, or approximately one thousand bytes 1024 bits kilohertz (32.000) kilohms megahertz megaohms microamperes microfarads microseconds microvolts microvolts root-mean-square milliamperes milliseconds millivolts nanoamperes nanoseconds nanovolts ohms picofarads peak-to-peak parts per million samples per second sigma: one standard deviation volts
3.2.4 Acronyms
This table lists the acronyms used in this document
Table 3-2. Acronyms
Symbol ABUS AC ADC
AHB
Unit of Measure analog output bus alternating current analog-to-digital converter AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
Table 3-2. Acronyms (continued)
Symbol API APOR BMC BR BRA BRQ CAN CC CCG3 CI CMP CO CPU CRC CT DAC DC DFP DI DMA DNL DO DRP DSI DSM ECO
EEPROM
EMCA EMIF FB FIFO FSR GPIO HCI HFCLK I2C IDE ILO IMO INL I/O IOR
Unit of Measure application programming interface analog power-on reset Bi-Phase Mark Coding bit rate bus request acknowledge bus request controller area network Configuration Channel Cypress's 3rd Generation USB Type-C Controller carry in compare carry out central processing unit cyclic redundancy check continuous time digital-to-analog converter direct current Downstream Facing Port digital or data input direct memory access differential nonlinearity digital or data output Dual Role Port digital signal interface deep-sleep mode external crystal oscillator electrically erasable programmable read only memory Electronically Marked Cable Assembly external memory interface feedback first in first out full scale range general purpose I/O host-controller interface high-frequency clock inter-integrated circuit integrated development environment internal low-speed oscillator internal main oscillator integral nonlinearity input/output I/O read
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Table 3-2. Acronyms (continued)
Symbol IOW IRES IRA IRQ ISR IVR LRb LRB LSb LSB LUT MISO MMIO MOSI MSb MSB PC PCH PCL PD PGA PM PMA POR PPOR PRS PSRR PSSDC PWM RAM RETI RF ROM RW SAR SC SCB SIE SIO SE0 SNR SOF SOI
Unit of Measure I/O write initial power on reset interrupt request acknowledge interrupt request interrupt service routine interrupt vector read last received bit last received byte least significant bit least significant byte lookup table master-in-slave-out memory mapped input/output master-out-slave-in most significant bit most significant byte program counter program counter high program counter low power down programmable gain amplifier power management CCG3 memory arbiter power-on reset precision power-on reset pseudo random sequence power supply rejection ratio power system sleep duty cycle pulse width modulator random-access memory return from interrupt radio frequency read only memory read/write successive approximation register switched capacitor serial communication block serial interface engine special I/O single-ended zero signal-to-noise ratio start of frame start of instruction
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Document Construction
Table 3-2. Acronyms (continued)
Symbol SOP SP SPD SPI SPIM SPIS SRAM SROM SSADC SSC SYSCLK SWD TC TD UART UFP USB USBIO USB PD WCO WDT WDR XRES XRES_N
Unit of Measure Start of Packet stack pointer sequential phase detector serial peripheral interconnect serial peripheral interconnect master serial peripheral interconnect slave static random-access memory supervisory read only memory single slope ADC supervisory system call system clock single wire debug terminal count transaction descriptors universal asynchronous receiver/transmitter Upstream Facing Port universal serial bus USB I/O USB Power Delivery watch crystal oscillator watchdog timer watchdog reset external reset external reset, active low
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Document Construction
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Section B: CPU System
This section encompasses the following chapters: Cortex-M0 CPU chapter on page 29 Interrupts chapter on page 35
Top Level Architecture
CPU System Block Diagram
SWD/TC
Cortex M0 48 MHz
FAST MUL NVIC, IRQMX
System Interconnect
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4. Cortex-M0 CPU
The CCG3 ARM Cortex-M0 core is a 32-bit CPU optimized for low-power operation. It has an efficient three-stage pipeline, a fixed 4-GB memory map, and supports the ARMv6-M Thumb instruction set. The Cortex-M0 also features a low-latency interrupt service routine (ISR) entry and exit. The Cortex-M0 processor includes a number of other components that are tightly linked to the CPU core. These include a nested vectored interrupt controller (NVIC), a SYSTICK timer, and debug. This section gives an overview of the Cortex-M0 processor. For more details, see the ARM Cortex-M0 user guide or technical reference manual, both available at http://www.arm.com.
4.1 Features
The CCG3 ARM Cortex-M0 has the following features: Easy to use, program and debug, ensuring easier migration from 8- and 16-bit processors Operates at up to 0.9 DMIPS/MHz; this helps to increase execution speed or reduce power Supports Thumb instruction set for improved code density, ensuring efficient use of memory NVIC unit to support interrupts and exceptions for rapid and deterministic interrupt response Extensive debug support including:
Serial wire debug (SWD) port Breakpoints Watchpoints
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Cortex-M0 CPU
4.2 Block Diagram
Figure 4-1. CCG3 CPU Subsystem Block Diagram
Interrupts
CPU Subsystem
Flash Programming
Interface
ARM Cortex-M0 CPU
DAP
System Interconnect
Flash Accelerator
SRAM Controller
SROM Controller
Test Controller
Flash
SRAM
SROM
CPU and Memory Subsystem
AHB Bridge
4.3 How It Works
The Cortex-M0 is a 32-bit processor with a 32-bit data path, 32-bit registers, and a 32-bit memory interface. It supports most 16-bit instructions in the Thumb instruction set and some 32-bit instructions in the Thumb-2 instruction set.
4.3.1 Registers
The Cortex-M0 has 16 32-bit registers, as Table 4-1 shows: R0 to R12 General-purpose registers. R0 to R7 can be accessed by all instructions; the other registers can be accessed
by a subset of the instructions. R13 Stack pointer (SP). There are two stack pointers, with only one available at a time. In thread mode, the CONTROL
register indicates the stack pointer to use, Main Stack Pointer (MSP) or Process Stack Pointer (PSP). R14 Link register. Stores the return program counter during function calls. R15 Program counter. This register can be written to control program flow.
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Cortex-M0 CPU
Table 4-1. Cortex-M0 Registers
Name
Typea
Reset Value
Description
R0-R12
RW
Unknown R0-R12 are 32-bit general-purpose registers for data operations.
MSP
The stack pointer (SP) is register R13. In thread mode, bit[1] of the CONTROL register indicates the stack pointer to use:
PSP
RW
[0x00000000] 0 = Main stack pointer (MSP). This is the reset value.
1 = Process stack pointer (PSP).
On reset, the processor loads the MSP with the value from address 0x00000000.
LR
RW
Unknown
The link register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions.
The program counter (PC) is register R15. It contains the current program address. On reset,
PC
RW
[0x00000004] the processor loads the PC with the value from address 0x00000004. Bit[0] of the value is
loaded into the EPSR T-bit at reset and must be 1.
The program status register (PSR) combines:
PSR
Application Program Status Register (APSR).
RW
Unknownb
Execution Program Status Register (EPSR).
Interrupt Program Status Register (IPSR).
APSR
RW
Unknown
The APSR contains the current state of the condition flags from previous instruction executions.
EPSR
RO
Unknownb The EPSR contains the Thumb state bit.
IPSR
RO
0
The IPSR contains the exception number of the current ISR.
PRIMASK
RW
0
The PRIMASK register prevents activation of all exceptions with configurable priority.
CONTROL
RW
0
The CONTROL register controls the stack used when the processor is in Thread mode.
a. Describes access type during program execution in thread mode and handler mode. Debug access can differ. b. Bit[24] is the T-bit and is loaded from bit[0] of the reset vector.
Table 4-2 shows how the PSR bits are assigned.
Table 4-2. Cortex-M0 PSR Bit Assignments
Bit 31 30 29 28 2725 24 236
50
PSR Register APSR APSR APSR APSE
EPSR
Name
N Z C V
T
IPSR
N/A
Usage
Negative flag
Zero flag
Carry or borrow flag
Overflow flag
Reserved
Thumb state bit. Must always be 1. Attempting to execute instructions when the T bit is 0 results in a HardFault exception.
Reserved
Exception number of current ISR:
0 = thread mode 1 = reserved 2 = Non maskable interrupt (NMI) 3 = HardFault 4 10 = reserved 11 = SVCall 12, 13 = reserved 14 = PendSV 15 = SysTick 16 = IRQ0 ...
47 = IRQ31
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Cortex-M0 CPU
Use the MSR or CPS instruction to set or clear bit 0 of the PRIMASK register. If the bit is 0, exceptions are enabled. If the bit is 1, all exceptions with configurable priority, that is, all exceptions except HardFault, NMI, and Reset, are disabled. See the Interrupts chapter on page 35 for a list of exceptions.
4.3.2 Operating Modes
The Cortex-M0 processor supports two operating modes:
Thread Mode used by all normal applications. In the thread mode, the MSP or PSP can be used. The CONTROL register bit 1 determines which stack pointer is used:
0 = MSP is the current stack pointer
1 = PSP is the current stack pointer
Handler Mode used to execute exception handlers. The MSP is always used.
In thread mode, use the MSR instruction to set the stack pointer bit in the CONTROL register. When changing the stack pointer, use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB execute using the new stack pointer.
In handler mode, explicit writes to the CONTROL register are ignored, because the MSP is always used. The exception entry and return mechanisms automatically update the CONTROL register.
4.3.3 Instruction Set
The Cortex-M0 implements a version of the Thumb instruction set. For details, see the Cortex-M0 Generic User Guide.
An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. Many instructions are unable to use, or have restrictions on using, the PC or SP for the operands or destination register.
Table 4-3. Thumb Instruction Set
Mnemonic ADCS ADD{S} ADR ANDS ASRS B{cc} BICS BKPT BL BLX BX CMN CMP
Brief Description Add with Carry Add PC-relative Address to Register Bit wise AND Arithmetic Shift Right Branch {conditionally} Bit Clear Breakpoint Branch with Link Branch indirect with Link Branch indirect Compare Negative Compare
Table 4-3. Thumb Instruction Set
Mnemonic CPSID CPSIE DMB DSB EORS ISB LDM LDR LDRB LDRH LDRSB LDRSH LSLS LSRS MOV{S} MRS MSR MULS MVNS NOP ORRS POP PUSH REV REV16 REVSH RORS RSBS SBCS SEV STM STR STRB STRH SUB{S} SVC SXTB SXTH TST UXTB UXTH WFE WFI
Brief Description Change Processor State, Disable Interrupts Change Processor State, Enable Interrupts Data Memory Barrier Data Synchronization Barrier Exclusive OR Instruction Synchronization Barrier Load Multiple registers, increment after Load Register from PC-relative address Load Register with word Load Register with half-word Load Register with signed byte Load Register with signed half-word Logical Shift Left Logical Shift Right Move Move to general register from special register Move to special register from general register Multiply, 32-bit result Bit wise NOT No Operation Logical OR Pop registers from stack Push registers onto stack Byte-Reverse word Byte-Reverse packed half-words Byte-Reverse signed half-word Rotate Right Reverse Subtract Subtract with Carry Send Event Store Multiple registers, increment after Store Register as word Store Register as byte Store Register as half-word Subtract Supervisor Call Sign extend byte Sign extend half-word Logical AND based test Zero extend a byte Zero extend a half-word Wait For Event Wait For Interrupt
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4.3.3.1 Address Alignment
An aligned access is an operation where a word-aligned address is used for a word or multiple word access, or where a half word-aligned address is used for a half word access. Byte accesses are always aligned.
No support is provided for unaligned accesses on the Cortex-M0 processor. Any attempt to perform an unaligned memory access operation results in a HardFault exception.
4.3.3.2 Memory Endianness
The CCG3 ARM Cortex-M0 uses little-endian format, where the least-significant byte of a word is stored at the lowest address and the most significant byte is stored at the highest address.
4.3.4 Systick Timer
The Systick timer is integrated with the NVIC and generates the SYSTICK interrupt. This interrupt can be used for task management in a real-time system. The timer has a reload register with 24 bits available to use as a countdown value. The Systick timer uses the Cortex-M0 internal clock as a source and can work in Sleep mode.
4.3.5 Debug
CCG3 ARM Cortex-M0 contains a debug interface based on SWD; it features four breakpoint (address) comparators and two watchpoint (data) comparators.
Cortex-M0 CPU
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5. Interrupts
The ARM Cortex-M0 (CM0) CPU in CCG3 supports interrupts and exceptions. Interrupts refer to those events generated by peripherals external to the CPU such as timers, serial communication block, and port pin signals. Exceptions refer to those events that are generated by the CPU such as memory access faults and internal system timer events. Both interrupts and exceptions result in the current program flow being stopped and the exception handler or interrupt service routine (ISR) being executed by the CPU. CCG3 provides a unified exception vector table for both interrupt handlers/ISR and exception handlers.
5.1 Features
CCG3 supports the following interrupt features: Supports 32 interrupts Nested vectored interrupt controller (NVIC) integrated with CPU core, yielding low interrupt latency Vector table may be placed in either flash or SRAM Configurable priority levels from 0 to 3 for each interrupt Level-triggered and pulse-triggered interrupt signals
5.2 How It Works
Figure 5-1. Interrupts Block Diagram
IRQ0 IRQ1
Interrupt signals from CCG3
on-chip peripherals
IRQ32
Cortex-M0 Processor
Nested Vectored Interrupt Controller (NVIC)
Cortex-M0 Processor Core
Figure 5-1 shows the interaction between interrupt signals and the Cortex-M0 CPU. CCG3 has 32 interrupts; these interrupt signals are processed by the NVIC. The NVIC takes care of enabling/disabling individual interrupts, priority resolution, and communication with the CPU core. The exceptions are not shown in Figure 5-1 because they are part of CM0 core generated events, unlike interrupts, which are generated by peripherals external to the CPU.
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Interrupts
5.3 Interrupts and Exceptions Operation
5.3.1
Interrupt/Exception Handling in CCG3
The sequence of events that occur when an interrupt or exception event is triggered is:
1. Assuming that all the interrupt signals are initially low (idle or inactive state) and the processor is executing the main code, a rising edge on any one of the interrupt lines is registered by the NVIC. The interrupt line is now in a pending state waiting to be serviced by the CPU.
2. On detecting the interrupt request signal from the NVIC, the CPU stores its current context by pushing the contents of the CPU registers onto the stack.
3. The CPU also receives the exception number of the triggered interrupt from the NVIC. All interrupts and exceptions in CCG3 have a unique exception number, as given in Table 5-1. By using this exception number, the CPU fetches the address of the specific exception handler from the vector table.
4. The CPU then branches to this address and executes the exception handler that follows.
5. Upon completion of the exception handler, the CPU registers are restored to their original state using stack pop operations; the CPU resumes the main code execution.
Figure 5-2. Interrupt Handling When Triggered
Rising Edge on Interrupt Line is registered by the NVIC
CPU detects the request signal from NVIC and stores its current context by pushing contents onto the stack
CPU receives exception number of triggered interrupt and fetches the address of the specific exception handle from
vector table.
CPU branches to the received address and executes exception handler
CPU registers are restored using stack upon completion of
exception handler.
When the NVIC receives an interrupt request while another interrupt is being serviced or receives multiple interrupt requests at the same time, it evaluates the priority of all these interrupts, sending the exception number of the highest priority interrupt to the CPU. Thus, a higher priority interrupt can block the execution of a lower priority ISR at any time.
Exceptions are handled in the same way that interrupts are handled. Each exception event has a unique exception number, which is used by the CPU to execute the appropriate exception handler.
5.3.2 Level and Pulse Interrupts
CCG3 NVIC supports both level and pulse signals on the interrupt lines (IRQ0 to IRQ31). The classification of an interrupt as level or pulse is based on the interrupt source.
Figure 5-3. Level Interrupts
IRQn
CPU
Execution State
main
ISR
IRQn is still high
ISR
ISR
main
main
Figure 5-4. Pulse Interrupts
IRQn
CPU
Execution State
main
ISR
main
ISR
ISR main
Figure 5-3 and Figure 5-4 show the working of level and pulse interrupts, respectively. Assuming the interrupt signal is initially inactive (logic low), the following sequence of events explains the handling of level and pulse interrupts:
1. On a rising edge event of the interrupt signal, the NVIC registers the interrupt request. The interrupt is now in the pending state, which means the interrupt requests have not yet been serviced by the CPU.
2. The NVIC then sends the exception number along with the interrupt request signal to the CPU. When the CPU starts executing the ISR, the pending state of the interrupt is cleared.
3. When the ISR is being executed by the CPU, one or more rising edges of the interrupt signal are logged as a single pending request. The pending interrupt is serviced again after the current ISR execution is complete (see Figure 5-4 for pulse interrupts).
4. If the interrupt signal is still high after completing the ISR, it will be pending and the ISR is executed again. Figure 5-3 illustrates this for level triggered interrupts, where the ISR is executed as long as the interrupt signal is high.
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Interrupts
5.3.3 Exception Vector Table
The exception vector table (Table 5-1), stores the entry point addresses for all exception handlers in CCG3. The CPU fetches the appropriate address based on the exception number.
Table 5-1. CCG3 Exception Vector Table
Exception Number
Exception
Exception Priority
Vector Address
Base_Address - Can be 0x00000000 (start of flash mem-
Initial Stack Pointer Value
Not applicable (NA)
ory) or 0x20000000 (start of SRAM)a
1
Reset
3, the highest priority Base_Address + 0x04
2
Non Maskable Interrupt (NMI) 2
Base_Address + 0x08
3
HardFault
1
Base_Address + 0x0C
410
Reserved
NA
Base_Address + 0x10 to Base_Address + 0x28
11
Supervisory Call (SVCall)
Configurable (03)
Base_Address + 0x2C
1213
Reserved
NA
Base_Address + 0x30 to Base_Address + 0x34
14
PendSupervisory (PendSV) Configurable (03)
Base_Address + 0x38
15
System Timer (SysTick)
Configurable (03)
Base_Address + 0x3C
16
External Interrupt (IRQ0)
Configurable (03)
Base_Address + 0x40
...
...
Configurable (03)
...
47
External Interrupt (IRQ31)
Configurable (03)
Base_Address + 0xBC
a. Note that the reset exception address in SRAM vector table will never be used because the device comes out of reset with the flash vector table selected.
In Table 5-1, the first word (4 bytes) is not marked as exception number zero. This is because the first word in the exception table is used to initialize the main stack pointer (MSP) value on device reset; it is not considered as an exception. In CCG3, the vector table can be configured to be located either in flash memory (base address of 0x00000000) or SRAM (base address of 0x20000000). This configuration is done by writing to the VECT_IN_RAM bit field (bit 0) in the CPUSS_CONFIG register. When the VECT_IN_RAM bit field is `1', CPU fetches exception handler addresses from the SRAM vector table location. When this bit field is `0' (reset state), the vector table in flash memory is used for exception address fetches. You must set the VECT_IN_RAM bit field as part of the device boot code to configure the vector table to be in SRAM. The advantage of moving the vector table to SRAM is that the exception handler addresses can be dynamically changed by modifying the SRAM vector table contents. However, the nonvolatile flash memory vector table must be modified by a flash memory write.
The exception sources (exception numbers 1 to 15) are explained in 5.4 Exception Sources. The exceptions marked as Reserved in Table 5-1 are not used in CCG3, though they have addresses reserved for them in the vector table. The interrupt sources (exception numbers 16 to 47) are explained in 5.5 Interrupt Sources.
5.4 Exception Sources
This section explains the different exception sources listed in Table 5-1 (exception numbers 1 to 15).
5.4.1 Reset Exception
Device reset is treated as an exception in CCG3. It is always enabled with a fixed priority of 3, the highest priority exception. A device reset can occur due to multiple reasons, such as power-on-reset (POR), external reset signal on XRES pin, or watchdog reset. When the device is reset, the initial boot code for configuring the device is executed out of supervisory read-only memory (SROM). The boot code and other data in SROM memory are programmed by Cypress, and are not read/write accessible to external users. After completing the SROM boot sequence, the CPU code execution jumps to flash memory. Flash memory address 0x00000004 (Exception#1 in Table 5-1) stores the location of the startup code in flash memory. The CPU starts executing code out of this address. Note that the reset exception address in SRAM vector table will never be used because the device comes out of reset with the flash vector table selected. The register configuration to select the SRAM vector table can be done only as part of the startup code in flash after the reset is de-asserted.
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Interrupts
5.4.2
Non-Maskable Interrupt (NMI) Exception
Non-maskable interrupt (NMI) is the highest priority exception other than reset. It is always enabled with a fixed priority of 2. There are two ways to trigger an NMI exception in CCG3:
NMI exception by setting NMIPENDSET bit (user NMI exception): NMI exception can be triggered in software by setting the NMIPENDSET bit in the interrupt control state register (CM0_ICSR register). Setting this bit will execute the NMI handler pointed to by the active vector table (flash or SRAM vector table).
System Call NMI exception: This exception is used for nonvolatile programming operations in CCG3 such as flash write operation and flash checksum operation. It is triggered by setting the SYSCALL_REQ bit in the CPUSS_SYSREQ register. An NMI exception triggered by SYSCALL_REQ bit always executes the NMI exception handler code that resides in SROM. Flash or SRAM exception vector table is not used for system call NMI exception. The NMI handler code in SROM is not read/ write accessible because it contains nonvolatile programming routines that should not be modified by the user.
5.4.3 HardFault Exception
HardFault is an always-enabled exception that occurs because of an error during normal or exception processing. HardFault has a fixed priority of 1, meaning it has higher priority than any exception with configurable priority. HardFault exception is a catch-all exception for different types of fault conditions, which include executing an undefined instruction and accessing an invalid memory addresses. The CM0 CPU does not provide fault status information to the HardFault exception handler, but it does permit the handler to perform an exception return and continue execution in cases where software has the ability to recover from the fault situation.
5.4.4 Supervisor Call (SVCall) Exception
Supervisor Call (SVCall) is an always-enabled exception caused when the CPU executes the SVC instruction as part of the application code. Application software uses the SVC instruction to make a call to an underlying operating system and provide a service. This is known as a supervisor call. The SVC instruction enables the application to issue a supervisor call that requires privileged access to the system. Note that the CM0 in CCG3 uses a privileged mode for the system call NMI exception, which is not related to the SVCall exception. (See the Chip Operational Modes chapter on page 67 for details on privileged mode.) There is no other privileged mode support for SVCall at the architecture level in CCG3. The application developer must define the SVCall exception handler according to the end application requirements.
The priority of a SVCall exception can be configured to a value between 0 and 3 by writing to the two bit fields PRI_11[31:30] of the System Handler Priority Register 2 (SHPR2). When the SVC instruction is executed, the SVCall exception enters the pending state and waits to be serviced by the CPU. The SVCALLPENDED bit in the System Handler Control and State Register (SHCSR) can be used to check or modify the pending status of the SVCall exception.
5.4.5 PendSV Exception
PendSV is another supervisor call related exception similar to SVCall, normally being software-generated. PendSV is always enabled and its priority is configurable. The PendSV exception is triggered by setting the PENDSVSET bit in the Interrupt Control State Register, CM0_ICSR. On setting this bit, the PendSV exception enters the pending state, and waits to be serviced by the CPU. The pending state of a PendSV exception can be cleared by setting the PENDSVCLR bit in the Interrupt Control State Register, CM0_ICSR. The priority of a PendSV exception can be configured to a value between 0 and 3 by writing to the two bit fields PRI_14[23:22] of the System Handler Priority Register 3 (CM0_SHPR3). See the ARMv6-M Architecture Reference Manual for more details.
5.4.6 SysTick Exception
CM0 CPU in CCG3 supports a system timer, referred to as SysTick, as part of its internal architecture. SysTick provides a simple, 24-bit decrementing counter for various time keeping purposes such as an RTOS tick timer, high-speed alarm timer, or simple counter. The SysTick timer can be configured to generate an interrupt when its count value reaches zero, which is referred to as SysTick Exception. The exception is enabled by setting the TICKINT bit in the SysTick Control and Status Register (CM0_SYST_CSR). The priority of a SysTick exception can be configured to a value between 0 and 3 by writing to the two bit fields PRI_15[31:30] of the System Handler Priority Register 3 (SHPR3). The SysTick exception can always be generated in software at any instant by writing a one to the PENDSTSETb bit in the Interrupt Control State Register, CM0_ICSR. Similarly, the pending state of the SysTick exception can be cleared by writing a one to the PENDSTCLR bit in the Interrupt Control State Register, CM0_ICSR.
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5.5 Interrupt Sources
CCG3 supports 22 interrupts from peripherals. The source of each interrupt is listed in Table 5-2. CCG3 provides flexible sourcing options for each of the 22 interrupt lines. The interrupts include standard interrupts from on-chip peripherals such as TCPWM, serial communication block, and interrupts from ports. The interrupt generated is usually the logical OR of the different peripheral states. The peripheral status register should be read in the ISR to detect which condition generated the interrupt. These interrupts are usually level interrupts, which require the peripheral status register to be read in the ISR to clear the interrupt. If the status register is not read in the ISR, the interrupt will remain
asserted and the ISR will be executed continuously.
Table 5-2. List of CCG3 Interrupt Sources
Interrupt No.
Interrupt Source
NMI
0
GPIO Interrupt - Port0
1
GPIO Interrupt - Port1
2
GPIO Interrupt - Port2
3
GPIO Interrupt - Port3
4
GPIO Interrupt - Port 4 USB Wakeup
5
GPIO All ports
6
Ganged USBPD Interrupt
7
WDT or Temp (WDT only in DeepSleep)
8
SCB[0]
9
SCB[1]
10
SCB[2]
11
SCB[3]
12
SPC
13
Synchronous USBPD Interrupts
14
TCPWM counter #0
15
TCPWM counter #1
16
TCPWM counter #2
17
TCPWM counter #3
18
USB Start of Frame
19
USB EP1-EP8 data
20
USB EP1-EP8 data
21
Crypto block
See the I/O System chapter on page 49 for details on GPIO interrupts.
5.6 Exception Priority
Exception priority is useful for exception arbitration when there are multiple exceptions that need to be serviced by the CPU. CCG3 provides flexibility in choosing priority values for different exceptions. All exceptions except Reset, NMI, and HardFault can be assigned a configurable priority level. The Reset, NMI, and HardFault exceptions have a fixed priority of 3, 2, and 1 respectively. In CCG3, lower priority numbers represent higher priorities. This means that the Reset, NMI, and HardFault exceptions have the highest priorities. The other exceptions can be assigned a configurable priority level between 0 and 3.
CCG3 supports nested exceptions in which a higher priority exception can obstruct (interrupt) the currently active exception handler. This pre-emption does not happen if the incoming exception priority is the same as active exception. The CPU resumes execution of the lower priority exception handler after servicing the higher priority exception. The CM0 CPU in CCG3 allows nesting of up to four exceptions. When the CPU receives two or more exceptions requests of the same priority, the lowest exception number is serviced first.
The registers to configure the priority of exception numbers 1 to 15 are explained in Exception Sources on page 37.
The priority of the 32 interrupts (IRQ0IRQ31) can be configured by writing to the Interrupt Priority registers (CM0_IPR). This is a group of four 32-bit registers with each register storing the priority values of four interrupts, as given in Table 5-3. The other bit fields in the register are not used.
Table 5-3. Interrupt Priority Register Bit Definitions
Bits 7:6 15:14 23:22 31:30
Name PRI_N0 PRI_N1 PRI_N2 PRI_N3
Description Priority of interrupt number N. Priority of interrupt number N+1. Priority of interrupt number N+2. Priority of interrupt number N+3.
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5.7 Enabling/Disabling Interrupts
The NVIC provides registers to individually enable and disable the 32 interrupts in software. If an interrupt is not enabled, the NVIC will not process the interrupt requests on that interrupt line. The Interrupt Set-Enable Register (CM0_ISER) and the Interrupt Clear-Enable Register (CM0_ICER) are used to enable and disable the interrupts respectively. These registers are 32-bit wide and each bit corresponds to the same numbered interrupt. These registers can also be read in software to get the enable status of the interrupts. Table 5-4 shows the register access properties for these two registers. Note that writing zero to these registers has no effect.
Table 5-4. Interrupt Enable/Disable Registers
Register
Interrupt Set Enable Register (CM0_ISER)
Interrupt Clear Enable Register (CM0_ICER)
Operation Write Read Write Read
Bit Value 1 0 1 0 1 0 1 0
Comment To enable the interrupt No effect Interrupt is enabled Interrupt is disabled To disable the interrupt No effect Interrupt is enabled Interrupt is disabled
The CM0_ISER and CM0_ICER registers are applicable only for the interrupts (IRQ0IRQ31). These registers cannot be used to enable or disable the exception numbers 1 to 15. The 15 exceptions have their own support for enabling and disabling, as explained in Exception Sources on page 37.
The PRIMASK register in Cortex-M0 (CM0) CPU can be used as a global exception enable register to mask all the configurable priority exceptions irrespective of whether they are enabled. Configurable priority exceptions include all the exceptions except Reset, NMI, and HardFault listed in Table 5-1. They can be configured to a priority level between 0 and 3, 0 being the highest priority and 3 being the lowest priority. When the PM bit (bit 0) in PRIMASK register is set, none of the configurable priority exceptions can be serviced by the CPU, though they can be in the pending state waiting to be serviced by the CPU after the PM bit is cleared.
5.8 Exception States
Each exception can be in one of the following states.
Table 5-5. Exception States
Exception State Inactive Pending
Active
Active and Pending
Meaning
The exception is not active and not pending. Either the exception is disabled or the enabled exception has not been triggered.
The exception request has been received by the CPU/NVIC and the exception is waiting to be serviced by the CPU.
An exception that is being serviced by the CPU but whose exception handler execution is not yet complete. A high-priority exception can interrupt the execution of lower priority exception. In this case, both the exceptions are in the active state.
The exception is being serviced by the processor and there is a pending request from the same source during its exception handler execution.
The Interrupt Control State Register (CM0_ICSR) contains status bits describing the various exceptions states.
The VECTACTIVE bits ([8:0]) in the CM0_ICSR store the exception number for the current executing exception. This value is zero if the CPU is not executing any exception handler (CPU is in thread mode). Note that the value in VECTACTIVE bit fields is the same as the value in bits [8:0] of the Interrupt Control State Register (ICSR), which is also used to store the active exception number.
The VECTPENDING bits ([20:12]) in the CM0_ICSR store the exception number of the highest priority pending exception. This value is zero if there are no pending exceptions.
The ISRPENDING bit (bit 22) in the CM0_ICSR indicates if a NVIC generated interrupt (IRQ0 to IRQ31) is in a pending state.
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5.8.1 Pending Exceptions
When a peripheral generates an interrupt request signal to the NVIC or an exception event occurs, the corresponding exception enters the pending state. When the CPU starts executing the corresponding exception handler routine, the exception is changed from the pending state to the active state.
The NVIC allows software pending of the 32 interrupt lines by providing separate register bits for setting and clearing the pending states of the interrupts. The Interrupt Set-Pending Register (CM0_ISPR) and the Interrupt Clear-Pending Register (CM0_ICPR) are used to set and clear the pending status of the interrupt lines. These registers are 32 bits wide, and each bit corresponds to the same numbered interrupt. Table 5-6 shows the register access properties for these two registers. Note that writing zero to these registers has no effect.
Table 5-6. Interrupt Set Pending/Clear Pending Registers
Register
Interrupt SetPending Register (CM0_ISPR)
Interrupt ClearPending Register (CM0_ICPR)
Operation Write Read Write Read
Bit Value
1
0 1 0
1
0 1 0
Comment
To put an interrupt to pending state No effect Interrupt is pending Interrupt is not pending To clear a pending interrupt No effect Interrupt is pending Interrupt is not pending
Setting the pending bit when the same bit is already set results in only one execution of the ISR. The pending bit can be updated regardless of whether the corresponding interrupt is enabled. If the interrupt is not enabled, the interrupt line will not move to the pending state until it is enabled by writing to the CM0_ISER register.
Note that the CM0_ISPR and CM0_ICPR registers are used only for the 32 peripheral interrupts (exception numbers 1647). These registers cannot be used for pending the exception numbers 1 to 15. These 15 exceptions have their own support for pending, as explained in Exception Sources on page 37.
Active Stack Pointer bit in the Control register is used to define the current active stack pointer. When in handler mode, the MSP is always used as the stack pointer. The stack pointer in Cortex-M0 always grows downwards and points to the address that has the last pushed data.
When the CPU is in thread mode and an exception request comes, the CPU uses the stack pointer defined in the control register to store the general-purpose register contents. After the stack push operations, the CPU enters handler mode to execute the exception handler. When another higher priority exception occurs while executing the current exception, the MSP is used for stack push/pop operations, because the CPU is already in handler mode. See the Cortex-M0 CPU chapter on page 29 for details.
The Cortex-M0 uses two techniques, tail chaining and late arrival, to reduce latency in servicing exceptions. These techniques are not visible to the external user and are done as part of the internal processor architecture (http:// infocenter.arm.com/help/index.jsp?topic=/ com.arm.doc.ddi0419c/index.html).
5.10 Interrupts and Low-Power
Modes
CCG3 allows device wakeup from low-power modes when certain peripheral interrupt requests are generated. The Wakeup Interrupt Controller (WIC) block generates a wakeup signal that causes the device to enter Active mode when one or more wakeup sources generate an interrupt signal. After entering Active mode, the ISR of the peripheral interrupt is executed.
The Wait For Interrupt (WFI) instruction, executed by the CM0 CPU, triggers the transition into Sleep and Deep-Sleep modes. The sequence of entering the different low-power modes is detailed in the Power Modes chapter on page 69. Chip low-power modes have two categories of fixed-function interrupt sources:
Fixed-function interrupt sources that are available only in the Active and Deep-Sleep modes (watchdog timer interrupt, I2C interrupts, USB PD and GPIO interrupts)
Fixed-function interrupt sources that are available only in the Active mode (all other fixed-function interrupts)
5.9 Stack Usage for Exceptions
When the CPU executes the main code (in thread mode) and an exception request occurs, the CPU stores the state of its general-purpose registers in the stack. It then starts executing the corresponding exception handler (in handler mode). The CPU pushes the contents of the eight 32-bit internal registers into the stack. These registers are the Program and Status Register (PSR), ReturnAddress, Link Register (LR or R14), R12, R3, R2, R1, and R0. Cortex-M0 has two stack pointers - MSP and PSP. Only one of the stack pointers can be active at a time. When in thread mode, the
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5.11 Exception - Initialization and Configuration
This section covers the different steps involved in initializing and configuring exceptions in CCG3.
1. Configuring the Exception Vector Table Location: The first step in using exceptions is to configure the vector table location as required - either in flash memory or SRAM. This configuration is done by writing either a `1' (SRAM vector table) or `0' (flash vector table) to the VECT_IN_RAM bit field (bit 0) in the CPUSS_CONFIG register. This register write is done as part of device initialization code.
It is recommended that the vector table be available in SRAM if the application will need to change the vector addresses dynamically. If the table is located in flash, then a flash write operation is required to modify the vector table contents.
2. Configuring Individual Exceptions: The next step is to configure individual exceptions required in an application.
a. Configure the exception or interrupt source; this includes setting up the interrupt generation conditions. The register configuration depends on the specific exception required.
b. Define the exception handler function and write the address of the function to the exception vector table. Table 5-1 gives the exception vector table format; the exception handler address should be written to the appropriate exception number entry in the table.
c. Set up the exception priority, as explained in Exception Priority on page 39.
d. Enable the exception, as explained in Enabling/Disabling Interrupts on page 40.
Table 5-7. List of Registers
Register Name CM0_ISER CM0_ICER CM0_ISPR CM0_ICPR CM0_IPR CM0_ICSR CM0_AIRCR CM0_SCR CM0_CCR CM0_SHPR2 CM0_SHPR3 CM0_SHCSR CM0_SYST_CSR CPUSS_CONFIG CPUSS_SYSREQ
Description Interrupt Set-Enable Register Interrupt Clear Enable Register Interrupt Set-Pending Register Interrupt Clear-Pending Register Interrupt Priority Registers Interrupt Control State Register Application Interrupt and Reset Control Register System Control Register Configuration and Control Register System Handler Priority Register 2 System Handler Priority Register 3 System Handler Control and State Register Systick Control and Status CPU Subsystem Configuration System Request Register
5.13 Associated Documents
ARMv6-M Architecture Reference Manual - This document explains the ARM Cortex-M0 architecture, including the instruction set, NVIC architecture, and CPU register descriptions.
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Section C: Memory System
This section presents the following chapter: Memory Map chapter on page 45
Top Level Architecture
SPCIF
Memory System Block Diagram
FLASH 2x64 KB
SRAM 8 KB
Read Accelerator
SRAM Controller
SROM 8 KB
ROM Controller
System Interconnect (Single Layer AHB)
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6. Memory Map
All CCG3 memory (flash, SRAM, and SROM) and all registers are accessible by the CPU and in most cases by the debug system. This chapter contains an overall map of the addresses of the memories and registers.
6.1 Features
The CCG3 memory system has the following features: 128K bytes flash, 8K bytes SRAM 8K byte SROM contains boot and configuration routines ARM Cortex-M0 32-bit linear address space, with regions for code, SRAM, peripherals, and CPU internal registers Flash is mapped to the Cortex-M0 code region SRAM is mapped to the Cortex-M0 SRAM region Peripheral registers are mapped to the Cortex-M0 peripheral region The Cortex-M0 Private Peripheral Bus (PPB) region includes registers implemented in the CPU core. These include reg-
isters for NVIC, SysTick timer, and serial communication block (SCB). For more information, see the Cortex-M0 CPU chapter on page 29.
6.2 How It Works
The CCG3 memory map is detailed in the following tables. For additional information, refer to the CCG3 Registers TRM. The ARM Cortex-M0 has a fixed address map allowing access to memory and peripherals using simple memory access instructions. The 32-bit (4 GB) address space is divided into the regions shown in Table 6-1. Note that code can be executed from the code and SRAM regions.
Table 6-1. Cortex-M0 Address Map
Address Range
Name
0x000000000x1FFFFFFF
Code
0x200000000x3FFFFFFF 0x400000000x5FFFFFFF 0x600000000xDFFFFFFF 0xE00000000xE00FFFFF 0xE01000000xFFFFFFFF
SRAM Peripheral PPB Device
Use Executable region for program code. You can also put data here. Includes the exception vector table, which starts at address 0. Executable region for data. You can also put code here. All peripheral registers. Code cannot be executed out of this region. Not used Peripheral registers within the CPU core. CCG3 implementation-specific.
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Table 6-2 shows the CCG3 address map.
Table 6-2. CCG3 Address Map
Address Range
Use
0x000000000x0001FFFC 128 KB flash
0x0FFFF0000x0FFFF3FF 1 KB supervisory flash
0x200000000x20001FFE 8 KB SRAM
0x401000000x4011FFFF CPU subsystem registers
0x400200000x40023FFF I/O port control (high-speed I/O matrix) registers
0x400400000x40043FFF I/O port registers
0x400700000x4007FFFF TCPWM registers
0x400500000x4005FFFF SCB registers
0x400800000x4008FFFF USB Power Delivery Controller registers
0x400300000x4003FFFF Power, clock, reset control registers
0xE00000000xE00FFFFF Cortex-M0 PPB registers
0xF00000000xF0000FFF CoreSight ROM
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Section D: System-Wide Resources
This section encompasses the following chapters: I/O System chapter on page 49 Clocking System chapter on page 57 Power Supply and Monitoring chapter on page 63 Chip Operational Modes chapter on page 67 Power Modes chapter on page 69 Watchdog Timer chapter on page 69 Reset System chapter on page 73 Device Security chapter on page 75
Top Level Architecture
System-Wide Resources Block Diagram
System Resources
Power
Sleep Control
WIC
POR
REF
PWRSYS
Clock
Clock Control
WDT
IMO
ILO
Reset
Reset Control XRES
Peripheral Interconnect (MMIO)
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7. I/O System
This chapter explains the CCG3 I/O system, its features, architecture, operating modes, and interrupts. The general-purpose I/O (GPIOs) pins in CCG3 are grouped into ports; a port can have a maximum of eight GPIOs. The CCG3 die has a maximum of 24 GPIOs arranged in four ports. 20 GPIOs are brought out on the 40-QFN and 42-CSP packages. These GPIO pins are organized in four logical entities called Ports.
7.1 Features
The CCG3 GPIOs have these features: Analog and digital input and output capabilities 10-mA sink and 4-mA source current in digital mode Separate port read (PS) and write (DR) data registers to avoid read-modify-write errors Edge-triggered interrupts on rising edge, falling edge, or on both the edges, on pin basis Slew rate control Selectable CMOS and low-voltage LVTTL input buffer mode Two over voltage tolerant GPIOs (I2C pins from SCB0)
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I/O System
7.2
Block Diagram
Figure 7-1. GPIO Block Diagram
Digital Input Path
GPIO_PRTx_PC2[y] GPIO_PRTx_PS[y]
Digital System Input
GPIO_PRTx_INTR_CFG[2y+1:2y] GPIO_PRTx_INTR[y] Pin Interrupt Signal
Input Buffer Disable
Interrupt Logic
Input Buffer Disable
Naming Convention `x' = Port Number `y' = Pin Number
Digital Output Path
GPIO_PRTx_PC[25]
HSIOM_PORT_SELx[4y+3:4y]
4
HSIOM
GPIO_PRTx_DR[y] ACT_0 ACT_1 ACT_2 ACT_3 DPSLP_0 DPSLP_1
GPIO_PRTx_PC[3y+2:3y]
3
OUTPUT ENABLE
Analog
HSIOM_PORT_SELx[4y+3:4y]
4
AMUXBUS_A AMUXBUS_B
4
Vdd
Vdd
Vdd
In Digital
Slew
Logic
Cntl
PIN
Drive mode
OE
Switches
Note The GPIO features shown in this image may not be available on all the pins.
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7.3 GPIO Drive Modes
Each I/O is individually configurable into one of the eight drive modes listed in Table 7-1. Figure 7-2 is a simplified pin diagram that shows the pin view based on each of the eight drive modes.
ties of a port:
Output drive mode of each pin (three bits select a particular drive mode for a pin)
Slew rate of the whole port (see Slew Rate Control on page 53)
Two port configuration registers are used to configure GPIOs in CCG3: Port Configuration Register (GPIO_PRTx_PC) and Port Secondary Configuration Register (GPIO_PRTx_PC2). All CCG3 devices have ports with dedicated GPIO_PRTx_PC and GPIO_PRTx_PC2 registers.
GPIO_PRTx_PC is used to configure the following proper-
Input threshold selection of the whole port (see CMOS LVTTL Level Control on page 53)
GPIO_PRTx_PC2 is used to enable/disable the input buffer of each pin on the port, irrespective of the drive mode configured in GPIO_PRTx_PC. When analog signals are present on the pin, input buffer should be disabled by setting the bit to `1'.
Figure 7-2. I/O Drive Mode Block Diagram
Vdd
Vdd
DR PS
Pin
DR PS
Pin
DR PS
Pin
DR PS
Pin
0. High Impedance Analog
1. High Impedance Digital
Vdd
2. Resistive Pull Up
Vdd
3. Resistive Pull Down
Vdd
DR PS
Pin
DR PS
Pin
DR PS
Pin
DR PS
Pin
4. Open Drain, Drives Low
5. Open Drain, Drives High
6. Strong Drive
7. Resistive Pull Up and Pull Down
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Table 7-1. Drive Mode Settings
Bits 3y+2: 3y
GPIO_PRTx_PC ('x' denotes port number and 'y' denotes pin number)
Drive Mode
Value
Data = 1
Data = 0
SEL'y'
Selects Drive Mode for Pin 'y' (0 y 7)
High-Impedance Analog
0
High Z
High Z
High-impedance Digital
1
High Z
High Z
Resistive Pull Up
2
Weak 1
Strong 0
Resistive Pull Down
3
Strong 1
Weak 0
Open Drain, Drives Low
4
High Z
Strong 0
Open Drain, Drives High
5
Strong 1
High Z
Strong Drive
6
Strong 1
Strong 0
Resistive Pull Up and Down
7
Weak 1
Weak 0
Table 7-2. Input Buffer Disable (Port Configuration 2)
Bits 7:0
Name INP_DIS
GPIO_PRTx_PC2 ('x' denotes port number and 'y' denotes pin number)
Description
Disables the input buffer independent of the port control drive mode. This bit should be set when analog signals are present on the pin.
7.3.1 High-Impedance Analog
High-impedance analog mode is the default reset state; both output driver and digital input buffer are turned off. This state prevents an external voltage from causing a current to flow into the digital input buffer. This drive mode is recommended for pins that are floating or that support an analog voltage. High-impedance analog pins cannot be used for digital inputs. Reading the pin state register returns a 0x00 regardless of the data register value.
To achieve the lowest device current in low-power modes, unused GPIOs must be configured to the high-impedance analog mode.
7.3.2 High-Impedance Digital
High-impedance digital mode is the standard high-impedance (High Z) state recommended for digital inputs. In this state, the input buffer is enabled for digital input signals.
7.3.3
Resistive Pull-Up or Resistive PullDown
Resistive modes provide a series resistance in one of the data states and strong drive in the other. Pins can be used for either digital input or digital output in these modes. If resistive pull-up is required, a `1' must be written to that pin's Data Register bit. If resistive pull-down is required, a `0' must be written to that pin's Data Register. Interfacing mechanical switches is a common application of these drive modes. The resistive modes are also used to interface CCG3 with open drain drive lines. Resistive pull-up is used when input is open drain low and resistive pull-down is used when input is open drain high.
7.3.4
Open Drain Drives High and Open Drain Drives Low
Open drain modes provide high impedance in one of the data states and strong drive in the other. The pins can be used as digital input or output in these modes. Therefore, these modes are widely used in bi-directional digital communication. Open drain drive high mode is used when signal is externally pulled down and open drain drive low is used when signal is externally pulled high.
A common application for open drain drives low mode is driving I2C bus signal lines.
7.3.5 Strong Drive
The strong drive mode is the standard digital output mode for pins; it provides a strong CMOS output drive in both high and low states. Strong drive mode pins must not be used as inputs under normal circumstances. This mode is often used for digital output signals or to drive external transistors.
7.3.6
Resistive Pull-Up and Resistive Pull-Down
This mode is similar to the drive modes explained in 7.3.3 Resistive Pull-Up or Resistive Pull-Down. In the resistive pull-up and resistive pull-down mode, the GPIO will have a series resistance in both logic 1 and logic 0 output states. The high data state is pulled up while the low data state is pulled down. This mode is used when the bus is driven by other signals that may cause shorts.
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7.4 Slew Rate Control
GPIO pins have fast and slow output slew rate options in strong drive mode; this can be configured using the GPIO_PRTx_PC[25] bit. Slew rate is individually configurable for each port. This bit is cleared by default and the port works in fast slew mode. This bit can be set if a slow slew rate is required. The fast slew rate is recommended for signals higher than 1 MHz. Slower slew rate results in reduced EMI and crosstalk; hence, the slow option is recommended for signals that are not speed critical generally less than 1 MHz.
7.5 CMOS LVTTL Level Control
I/O pins can work at two voltage levels. These levels can be selected by writing to the GPIO_PRTx_PC[24] bit.
Input level is individually configurable for each port. This bit is cleared by default and the port works in CMOS mode. This bit can be set to reconfigure the port to LVTTL mode.
CMOS mode can be used in most cases, whereas LVTTL can be used for custom interface requirements, which works at lower voltage levels. See the device datasheet for the input voltage thresholds (VIH and VIL) for the modes.
7.6 GPIO-OVT
CCG3 device has two over-voltage tolerant (OVT) pins
I2C pins from SCB0. It is similar to regular GPIOs with the following additional features:
Over-voltage tolerant
Provides better pull-down drive strength
Serial Communication Block (SCB) when configured as I2C and its lines routed to GPIO-OVT pins; it meets the following I2C specifications:
Fast Mode hot-swap
Fast Mode Plus IOL Specification
Fast Mode and Fast Mode Plus Hysteresis and minimum fall time specifications
See the CCG3 datasheet for specifications.
7.7 High-Speed I/O Matrix
High-speed I/O matrix (HSIOM) is a group of high-speed switches that routes GPIOs to the resources inside CCG3. These resources include TCPWMs, SCB, and the USB PD. The HSIOM selects Active and Deep-Sleep power domain sources for a pin. HSIOM_PORT_SELx are 32-bit wide registers that control the routing of GPIOs. Each register controls one port; four dedicated bits are assigned to each GPIO in the port. This provides up to 16 different options for GPIO routing. This selection provides different pin functions, as listed in Table 7-3.
Table 7-3. HSIOM Port Settings
Bits 4y+3 : 4y
HSIOM_PORT_SELx ('x' denotes port number and 'y' denotes pin number)
Name (SEL 'y')
Value
Description (Selects pin 'y' source (0 y 7)
DR
0
Pin is regular firmware-controlled GPIO.
AMUXA
6
Pin is connected to AMUXBUS-A.
AMUXB
7
Pin is connected to AMUXBUS-B. This mode is also used for GPIO pre-charging of tank capacitors.
ACT_0
8
Pin-specific Active source # 0 (TCPWM, EXT CLOCK)
ACT_1
9
Pin-specific Active source #1.
ACT_2
10 Pin-specific Active source #2.
ACT_3
11 Pin-specific Active source #3.
DPSLP_0
14 Pin-specific Deep-Sleep source #0 (SCB - I2C)
DPSLP_1
15 Pin-specific Deep-Sleep source #1 (SWD)
Note The active and deep sleep sources are pin dependent. See the "Pinouts" section of the device datasheet for more details on the features supported by each pin.
7.8 Firmware Controlled GPIO
See Table 7-3 to know the HSIOM settings for a firmware controlled GPIO. GPIO_PRTx_DR is the data register used to read and write the output data for the GPIOs. A write operation to this register changes the GPIO output to the written value. Note that a read operation reflects the output data written to this register and not the current state of the GPIOs. Using this register, read-modify-write sequences can be safely performed on a port that has both input and
output GPIOs.
In addition to the data register, two other registers GPIO_PRTx_DR_SET and GPIO_PRTx_DR_CLR - are provided to set or clear the output data of specific GPIOs in port. Additionally, the GPIO_PRTx_DR_INV register can be used to invert the output data of a specific GPIO. GPIO_PRTx_PS is the port I/O pad register that provides the state of the GPIOs when read. Writes to this register have no effect.
See the CCG3 Registers TRM for the details of these registers.
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7.9 I/O Port Reconfiguration
Drive mode and GPIO can be reconfigured in runtime by changing the value of the GPIO_PRTx_PC and HSIOM_PORT_SELx registers. Take care to retain the pin state during reconfiguration of pins when they are connected directly to a digital peripheral. If the ports are driven by the data registers, state maintenance is automatic. During port configuration, the current configuration should be saved as follows: 1. Read the GPIO pin state - GPIO_PRTx_PS in software. 2. Write the GPIO_PRTx_PS value into the data registers -
GPIO_PRTx_DR. 3. Change the corresponding field in HSIOM_PORT_SELx
to drive the pin by the data register - GPIO_PRTx_DR.
7.10 I/O State on Power Up
By default, during power up all GPIOs are in high-impedance analog state and input buffers are disabled. When the chip is powered, its GPIOs can be configured according to the required application, by writing to the associated registers.
7.11 Behavior in Low-Power Modes
For more details, see the Power Modes chapter on page 69, Interrupts chapter on page 35, and Inter Integrated Circuit (I2C) chapter on page 100. To achieve the lowest device current in low-power modes, unused I/Os must be configured in the high-impedance analog mode.
7.12 GPIO Interrupt
This section describes the interrupt functionality of the CCG3 GPIOs.
7.12.1 Features
The features of the GPIO interrupt are: All eight pins in each port interface have an interrupt and
an associated interrupt vector Pin status bits provide easy determination of interrupt
source down to the pin level Rising, falling, or both edge-triggered interrupts are han-
dled Pin interrupts can be individually enabled or disabled AHB interfaces for read and write into its registers Sends out a single port interrupt request (PIRQ) signal,
derived from all GPIOs in a port, to the interrupt controller
The GPIOs maintain the current pin state during Sleep mode. In Sleep mode, all the GPIOs are active and can be driven by active peripherals, such as USB PD, TCPWM, and SCB.
In Deep-Sleep mode, all the pin states are latched and the pin signals are retained, except the SCB pins, which remain functional and can wake up the processor on I2C address matching event. GPIO interrupts are also available in DeepSleep mode with wake up ability.
7.12.2 Interrupt Controller Block Diagram
Each port has its own individual interrupt request and associated interrupt request (IRQ) vector and interrupt service routine (ISR). Additionally, one pin can be selected on each port that is routed through a 50-ns glitch filter to form a glitch-tolerant interrupt for the port. The details are shown in Figure 7-3.
Figure 7-3. Interrupt Generator
50 ns Glitch Filter
Edge Detector
Pin 0 Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7
Edge Detector Edge Detector Edge Detector Edge Detector Edge Detector Edge Detector Edge Detector Edge Detector
Port_irq
7.12.3 Function and Configuration
Each pin of the port can be configured independently to generate an interrupt on the rising edge, falling edge, or on both edges by writing to the GPIO_PRTx_INTR_CFG register.
Level-sensitive interrupts are not supported. GPIO_PRTx_INTR_CFG is also used to route a specific channel to the glitch filter and generate a ninth glitch-tolerant interrupt.
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When a GPIO interrupt is triggered by a signal on an interrupt-enabled port pin, the GPIO_PRTx_INTR register (Port Interrupt Status Register) is updated. The firmware can read this register to determine which GPIO triggered the interrupt. Firmware can then clear the IRQ bit by writing a `1' to its corresponding bit.
Additionally, when the Port Interrupt Control Status Register is read at the same time an interrupt is occurring on the cor-
responding port, it can result in the interrupt not being properly detected. Therefore, when using GPIO interrupts, it is recommended to read the status register only inside the corresponding interrupt service routine and not in any other part of the code.
See GPIO_PRTx_INTR_CFG and GPIO_PRTx_INTR in the CCG3 Registers TRM for details.
7.13 Registers
Table 7-4. I/O Registers
Name
Description
GPIO_PRTx_DR
Port Output Data Register
GPIO_PRTx_DR_SET Port Output Data Set Register
GPIO_PRTx_DR_CLR Port Output Data Clear Register
GPIO_PRTx_DR_INV Port Output Data Inverting Register
GPIO_PRTx_PS
Port Pin State Register - Used to read logical pin state of I/O
GPIO_PRTx_PC
Port Configuration Register - Configures the output drive mode, input threshold, and slew rate
GPIO_PRTx_PC2
Port Secondary Configuration Register - Configures the input buffer of I/O pin
GPIO_PRTx_INTR_CFG Port Interrupt Configuration Register
GPIO_PRTx_INTR
Port Interrupt Status Register
HSIOM_PORT_SELx HSIOM Port Selection Register
Note The 'x' in the register name denotes the port number. For example, GPIO_PTR1_DR is the port 1 output data register.
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8. Clocking System
The CCG3 clock system includes these clock resources: Two internal clock sources:
2448 MHz internal main oscillator (IMO) ±2 percent across all frequencies with trim. 32-kHz internal low-speed oscillator (ILO) External clock (EXTCLK) generated using a signal from an I/O pin High-frequency clock (HFCLK) of up to 48 MHz selected from IMO or external clock Dedicated prescaler for HFCLK Low-frequency clock (LFCLK) sourced by ILO Dedicated prescaler for system clock (SYSCLK) of up to 48 MHz sourced by HFCLK Eight peripheral clocks, 4 clocks with a 8 bit divider and rest of the 4 clocks are with 16 bit dividers
8.1 Block Diagram
Figure 8-1 gives a generic view of the clocking system in CCG3 devices.
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IMO EXTCLK
ILO
Figure 8-1. Clocking System Block Diagram
HFCLK Predivider
HFCLK
SYSCLK Prescaler
SYSCLK
LFCLK
WDT
Peripheral Divider 0 Peripheral Divider 1
Peripheral Divider 2
Peripheral Divider 3
Cortex-M0 CPU
SCBCLK SCB (I2C)
TCPWMCLK TCPWM
The three clock sources in the device are shown in Figure 8-1, on the left. The HFCLK mux selects the HFCLK source from an external clock source or the IMO. The HFCLK prescaler divides the HFCLK input. The SYSCLK prescaler generates the SYSCLK and the peripheral dividers generate the individual peripheral clocks. The ILO sources the LFCLK.
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8.2 Clock Sources
8.2.1 Internal Main Oscillator
The internal main oscillator operates with no external components and outputs a stable clock at frequencies spanning 24-48 MHz in 4-MHz increments. Frequencies are selected by setting the frequency range in the CLK_IMO_TRIM2 register and setting the IMO trim in the CLK_IMO_TRIM1 register. Each device has IMO trim measured during manufacturing to meet datasheet specifications; the trim is stored in manufacturing configuration data in SFLASH. These values may be loaded at startup to achieve the desired configuration. Firmware can retrieve these trim values and reconfigure the device to change the frequency at run-time.
8.2.1.1 Startup Behavior
After reset, the IMO is configured for 24-MHz operation. During the "boot" portion of startup, trim values are read from flash and the IMO is configured to achieve datasheet specified accuracy. The HFCLK predivider is initially set to a divide value of 4 to reduce current consumption at startup.
8.2.2 Internal Low-speed Oscillator
The internal low-speed oscillator operates with no external components and outputs a stable clock at 32-kHz nominal. The ILO is relatively low power and low accuracy. It is available in all power modes. The ILO is always used as the system low-frequency clock LFCLK in CCG3. The ILO is recommended to be always on, because it is the source of the WDT, which is required for reliable system operation. The ILO can be disabled by clearing the ENABLE bit in the CLK_ILO_CONFIG register. The WDT reset must be disabled before disabling the ILO. Otherwise, any register write to disable the ILO will be ignored. Enabling the WDT reset will automatically enable the ILO.
Note Disabling the ILO reset is not recommended if: WDT protection is required against firmware crashes WDT protection is required against the power supply
events that produce sudden brownout events that may in turn compromise the CPU functionality.
See the Clocking System chapter on page 57 for details.
8.2.3 External Clock
The external clock is a MHz range clock that can be generated from a signal on a designated CCG3 pin. This clock may be used in place of the IMO as the source of the system high-frequency clock HFCLK. The allowable range of external clock frequencies is 048 MHz. CCG3 always starts up using the IMO, and the external clock must be enabled in user mode, so the device cannot be started from a reset clocked by the external clock.
8.3 Clock Distribution
CCG3 clocks are developed and distributed throughout the device, as shown in Figure 8-1. The distribution configuration options are as follows: HFCLK input selection HFCLK predivider configuration SYSCLK prescaler configuration Peripheral divider configuration
8.3.1 HFCLK Input Selection
HFCLK in CCG3 has input options: IMO and EXTCLK. The HFCLK input is selected using the CLK_SELECT register's DIRECT_SEL bits, as described in Table 8-1.
Table 8-1. HFCLK Input Selection Bits DIRECT_SEL
Name DIRECT_SEL[2:0]
Description HFCLK input clock selection 0: IMO. Uses the IMO as the source of the HFCLK 1: EXTCLK. Uses the EXTCLK as the source of the HFCLK 27: Reserved. Do not use
When manually configuring a pin as the input to the EXTCLK, the drive mode of the pin must be set to high-impedance digital to enable the digital input buffer. See the I/O System chapter on page 49 for more details.
8.3.2 HFCLK Predivider Configuration
The HFCLK predivider allows the device to divide the HFCLK selection mux input before use as HFCLK. The predivider is capable of dividing the HFCLK by powers of 2 between 1 and 8. The predivider value is set using register CLK_SELECT bits HFCLK_DIV, as described in Table 8-2. The HFCLK predivider is set to a divide value of 4 during boot to reduce current consumption. Note HFCLK's frequency cannot exceed 16 MHz.
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Table 8-2. HFCLK Predivider Value Bits HFCLK_DIV
Name HFCLK_DIV[1:0]
HFCLK predivider value 0: 1. no divider on HFCLK 1: 2. divides HFCLK by 2 2: 4. divides HFCLK by 4 3: 8. divides HFCLK by 8
Description
8.3.3 SYSCLK Prescaler Configuration
The SYSCLK Prescaler allows the device to divide the predivided HFCLK before use as SYSCLK, which allows for non-integer relationships between peripheral clocks and the system clock. SYSCLK must be equal to or faster than all other clocks in the device that are derived from HFCLK. The SYSCLK prescaler is capable of dividing the HFCLK by powers of 2 between1 and 8. The prescaler divide value is set using register CLK_SELECT bits SYSCLK_DIV, as described in Table 8-3. The prescaler is initially configured to divide by 1.
Table 8-3. SYSCLK Prescaler Divide Value Bits SYSCLK_DIV
Name SYSCLK_DIV[1:0]
SYSCLK prescaler divide value 0: 1. SYSCLK = HFCLK 1: 2. SYSCLK = HFCLK/2 2: 4. SYSCLK = HFCLK/4 3: 8. SYSCLK = HFCLK/8
Description
8.3.4
Peripheral Clock Divider Configuration
The eight peripheral clocks are derived from the HFCLK using the 8-bit or 16-bit peripheral clock dividers. Each of the eight dividers is controlled by a PERI_DIV_8_CTL or PERI_DIV_16_CTL register, whose mapping is explained in Table 8-4 and Table 8-5.
Table 8-4. Peripheral Clock Divider Control Register PERI_DIV_8_CTLx
Bits
Name
0
EN
15:8 INT8_DIV
Description
Enables or disables the divider 0: Divider disabled 1: Divider enabled
Divide value of the divider. Output = Input/ (INT8_DIV + 1)
Table 8-5. Peripheral Clock Divider Control Register PERI_DIV_16_CTLx
Bits
Name
0
EN
23:8 INT16_DIV
Description
Enables or disables the divider 0: Divider disabled 1: Divider enabled
Divide value for the divider. Output = Input/ (INT16_DIV + 1) Acceptable divide values range from 0 to 65,536.
The PERI_DIV_CMD register can be used to enable, disable, and select the type of clock dividers for all peripheral clock dividers. See the PERI_DIV_CMD in the CCG3 Registers TRM for more details.
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Input clocks to the peripherals are selected by PERI_PCLK_CTLx registers. Table 8-6 shows the peripheral clocks and their respective registers. See theCCG3 Registers TRM for more details.
Table 8-6. Selecting Peripheral Clocks
Clock SCB0 SCB1 TCPWM USBPD (RX) USBPD (TX) USBPD (SAR)
Register PERI_PCLK_CTL0 PERI_PCLK_CTL1 PERI_PCLK_CTLx (x = 27) PERI_PCLK_CTL8 PERI_PCLK_CTL9 PERI_PCLK_CTL10
8.4 Low-Power Mode Operation
CCG3 clock behavior is different in different power modes. The MHz frequency clocks including the IMO, EXTCLK, HFCLK, SYSCLK, and peripheral clocks operate only in Active and Sleep modes. The ILO and LFCLK operate in all power modes.
8.5 Register List
Table 8-7. Clocking System Register List
Register Name CLK_IMO_TRIM1 CLK_IMO_TRIM2 CLK_ILO_CONFIG CLK_SELECT
PERI_DIV_16_CTLx PERI_PCLK_CTLx
Description IMO Trim Register - This register contains IMO trim, allowing fine manipulation of its frequency. IMO Frequency Selection Register - This register controls the frequency range of the IMO, allowing gross manipulation of its frequency. ILO Configuration Register - This register controls the ILO configuration.
Clock Select - This register controls clock tree configuration, selecting different sources for the system clocks.
Peripheral Clock Divider Control Registers - These registers configure each of the peripheral clock dividers, enabling or disabling the divider and setting the integer divide value.
Programmable clock control registers - These registers are used to select the input clocks to peripherals.
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9. Power Supply and Modes
9.1 Block Diagram
Figure 9-1. Power System Requirement Block Diagram
VSYS
1uF
VBUS_P OC
VBUS_P_CTRL VCONN VCCD
1uF
VDDIO VSS
Switch
Regulator
VBUS
1uF
VBUS_DISCHARGE
OCP Gate Driver
RA
OVP Gate Driver
Regulator
FS-USB TX/RX
VBUS_C_CTRL VDDD
1uF
DP, DM
GPIO
Core CCG3
CC Tx/Rx
CC1, CC2 VSS
9.2 Power System Requirement Overview
Figure 9-1 shows an overview of the CCG3 power system requirement. CCG3 shall be able to operate from two possible external supply sources VBUS (4.0 - 21.5 V) or VSYS (2.7 - 5.5 V). The VBUS supply is regulated inside the chip with a LDO. The chip's internal VDDD rail is intelligently switched between the output of the VBUS regulator and unregulated VSYS. The switched supply, VDDD is either used directly inside some analog blocks or further regulated down to VCCD which powers majority of the core using the regulators inside the SRSS-Lite block. CCG3 has 3 power modes: Active, Sleep and Deep Sleep, transitions between which are managed by the power system. A separate power domain VDDIO is provided for the GPIOs. The VDDD and VCCD pins, both the output of regulators are brought out for connecting a 1-uF capacitor for the regulator stability only. These pins are not supported as a power supplies.
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9.3 Power Modes
The power modes of the device accessible and observable by the user are listed in the following table.
Table 9-1. CCG3 Power Modes
MODE RESET ACTIVE SLEEP DEEP SLEEP
SCAN
DESCRIPTION
Power is Valid and XRES is not asserted. An internal reset source is asserted or SleepController is sequencing the system out of reset
Power is Valid and CPU is executing instructions. This mode includes the critical Type-C power spec requirements.
Power is Valid and CPU is not executing instructions. All logic that is not operating is clock gated to save power.
Main regulator and "most of the blocks of the chip are shut off. DeepSleep regulator powers logic, but only low-frequency clock is available
System is in SCAN mode. Scan mode is entered by applying DFT key during XRES and exited by applying something other than the DFT key (at least one bit).
9.4 Power Domain Model Diagram
Figure 9-2 shows the power domain model diagram of CCG3. All external components on the various power domains are shown. Depending on the application, the bypass capacitor on unused primary supplies corresponding supply pins can be skipped.
Figure 9-2. CCG3 Power Domain Model Diagram
VSYS
1uF
Switch
Regulator
VBUS
1uF
VBUS_P
VBUS_DISCHARGE
OC VBUS_P_CTRL
VCONN VCCD
1uF
VDDIO VSS
OCP Gate Driver
RA
GPIO
OVP Gate Driver
Regulator
FS-USB TX/RX
VBUS_C_CTRL VDDD
1uF
DP, DM
Core CCG3
CC Tx/Rx
CC1, CC2 VSS
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9.5 Mode Transitions
CCG3 follows the mode transitions supported for SRSS-Lite system resource block as described in Section 16.5.1 SRSSLite on page 155. The primary mode transition diagram is shown in Figure 9-3.
Figure 9-3. CCG3 Primary Mode Transition Diagram
Firmware Act io n
Ext ernal Power Ramps XRES Deasserted
RESET
Completed Reset Se qu en ce
In ter na l Rese ts
ACTIVE
WakeUp In terr up t
SLEEP
Debugger Session Ends
Internal Reset Event External Reset Event Power Down or Brown Our Event Firmware Action Debugger/ATE Action Other External Event
Internal Power Rails begin ramp up after
XRES deassert s.
XRES during SCAN does not exit SCAN unless Primary SWD port shift s in at least one (non-key) bit
SCAN
DEEPSLEEP
Debugger Session Starts
XRES Assert s from any other
sta te
XRES Dea sser ts
XRES Deassert and SCAN key
ob ser ved
XRES Asserts
XRES
OFF
Ext ernal Power Ramps XRES Assert ed
PowerDown or BrownOut
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10. Chip Operational Modes
CCG3 is capable of executing firmware in four different modes. These modes dictate execution from different locations in Flash and ROM, with different levels of hardware privileges. Only three of these modes are used in end-applications; debug mode is used exclusively to debug designs during firmware development. CCG3's operational modes are: Boot User Privileged Debug
10.1 Boot
Boot mode is an operational mode where the device is configured by instructions hard-coded in the device SROM. This mode is entered after the end of a reset, provided no debug-acquire sequence is received by the device. Boot mode is a privileged mode; interrupts are disabled in this mode so that the boot firmware can set up the device for operation without being interrupted. During the power-up phase, hardware trim settings are loaded from nonvolatile (NV) latches to guarantee proper operation during power-up. When boot concludes, the device enters user mode and code execution from flash begins.
10.2 User
User mode is an operational mode where normal user firmware from flash is executed. User mode cannot execute code from SROM. Firmware execution in this mode includes the automatically generated firmware by the IDE and the firmware written by the user. The automatically generated firmware can govern both the firmware startup and portions of normal operation. The boot process transfers control to this mode after it has completed its tasks.
10.3 Privileged
Privileged mode is an operational mode, which allows execution of special subroutines that are stored in the device ROM. These subroutines cannot be modified by the user and are used to execute proprietary code that is not meant to be interrupted or observed. Debugging is not allowed in privileged mode. The CPU can transition to privileged mode through the execution of a system call. For more information on how to perform a system call, see Performing a System Call on page 198. Exit from this mode returns the device to user mode.
10.4 Debug
Debug mode is an operational mode that allows observation of the CCG3 operational parameters. This mode is used to debug the firmware during development. The debug mode is entered when an SWD debugger connects to the device during the acquire time window, which occurs during the device reset. Debug mode allows IDEs such as Eclipse and ARM MDK to debug the firmware. Debug mode is only available on devices in open mode (one of the four protection modes). For more details on the debug interface, see the Program and Debug Interface chapter on page 189. For more details on protection modes, see the Device Security chapter on page 75.
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11. Watchdog Timer
The watchdog timer (WDT) is used to automatically reset the device in the event of an unexpected firmware execution path or a brownout that compromises the CPU functionality. The WDT runs from the LFCLK (32-kHz clock), generated by the ILO. The timer must be serviced periodically in firmware to avoid a reset. Otherwise, the timer will elapse and generate a device reset. The WDT can be used as an interrupt source or a wakeup source in low-power modes.
11.1 Features
The WDT has these features: Configurable timer period Can generate an interrupt in Sleep and Deep-Sleep power modes to wake up the device Can generate an interrupt in Active mode after a specified interval
11.2
Block Diagram
Figure 11-1. Watchdog Timer Block Diagram
AHB Interface Register
Internal Low-Speed Oscillator
(ILO) 32 kHz
CFG/ STATUS
INTERRUPT
Watchdog Timer
CLK
RESET
CPU Subsystem or
WIC
Reset Block
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11.3 How It Works
The WDT asserts a hardware reset to the device after three WDT interrupts each of programmable interval of up to 2048 ms, unless it is periodically serviced in firmware.The WDT is a 16-bit free-running wraparound up-counter.
The WDT_COUNTER register provides the count value of the WDT. The WDT generates an interrupt when the count value in WDT_COUNTER equals the match value stored in the WDT_MATCH register, but it does not reset the count to '0'. Instead, the WDT keeps counting until it overflows and rolls back to 0. When the count value again reaches the match value, another interrupt is generated.
A bit named WDT_MATCH in the SRSS_INTR register is set whenever the WDT interrupt occurs. This interrupt must be cleared by writing a '1' to the WDT_MATCH bit in SRSS_INTR to feed the watchdog timer. If the firmware does not feed the WDT for two consecutive interrupts, the third match event will generate a hardware reset.
For details, see the WDT_COUNTER, WDT_MATCH, and SRSS_INTR registers in theCCG3 Registers TRM.
When the WDT is used to protect against system crashes, clearing the WDT interrupt bit to feed the watchdog must be done from a portion of the code that is not directly associated with the WDT interrupt. Otherwise, even if the main function of the firmware crashes or is in an endless loop, the WDT interrupt vector can still be intact and feed the WDT periodically.
The safest way to use the WDT against system crashes is:
Feed the watchdog by clearing the interrupt bit regularly in the main body of the firmware code.
Guarantee that the interrupt is cleared at least once every WDT period.
Use the WDT interrupt service routine (ISR) only as a timer to trigger certain actions and to change the next WDT_MATCH value. Do not feed WDT in this ISR.
Follow these steps to use WDT as a periodic interrupt generator:
1. Write the desired match value to the WDT_MATCH register.
2. Clear the WDT_MATCH bit in SRSS_INTR to clear any pending WDT interrupt.
3. Enable the WDT interrupt by setting the WDT_MATCH bit in SRSS_INTR_MASK.
4. In the ISR, clear the WDT interrupt and add the desired match value to the existing match value. By doing so, another periodic interrupt will be generated when the counter reaches the new match value.
5. The IGNORE_BITS in the WDT_MATCH register can be used to reduce the entire WDT counter period. The ignore bits can specify the number of MSbs that needs to be discarded. For example, if the IGNORE_BITS value is 3, then WDT counter becomes a 13-bit counter.
11.3.1 Enabling and Disabling WDT
The WDT is a free-running counter that cannot be disabled. However, it is possible to disable the WDT reset by writing a key '0xACED8865' to the WDT_DISABLE_KEY register. Writing any other value to this register will enable the WDT reset. If WDT reset is disabled, the firmware does not need to periodically feed the WDT to avoid a reset. The WDT can still be used as an interrupt source or wakeup source. The only way to stop WDT from generating interrupts and wakeup events is to disable the ILO by clearing the ENABLE bit in the CLK_ILO_CONFIG register. The WDT reset must be disabled before disabling the ILO. Otherwise, any register write to disable the ILO will be ignored. Enabling the WDT reset will automatically enable the ILO.
Note Disabling the WDT reset is not recommended if:
Protection is required against firmware crashes
The power supply can produce sudden brownout events that may compromise the CPU functionality
11.3.2 WDT Interrupts and Low-Power Modes
The WDT counter sends the interrupt requests to the CPU in Active power mode and to the WakeUp Interrupt Controller (WIC) in Sleep and Deep-Sleep power modes. It works as follows:
Active Mode: In Active power mode, the WDT sends the interrupt to the CPU. The CPU acknowledges the interrupt request and executes the ISR. The interrupt must be cleared after entering the ISR in firmware.
Sleep or Deep-Sleep Mode: In this mode, the CPU subsystem is powered down. Therefore, the interrupt request from the WDT is directly sent to the WIC, which will then wake up the CPU. The CPU acknowledges the interrupt request and executes the ISR. The interrupt must be cleared after entering the ISR in firmware.
For more details, see the Power Modes chapter on page 69.
11.3.3 WDT Reset Mode
The RESET_WDT bit in the RES_CAUSE register indicates the reset generated by the WDT. This bit remains set until cleared or until a power-on reset (POR), brownout reset (BOD), or external reset (XRES) occurs. All other resets leave this bit untouched.
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For more details, see the Reset System chapter on page 73.
11.4 Register List
Table 11-1. WDT Registers
Register Name WDT_DISABLE_KEY WDT_COUNTER WDT_MATCH SRSS_INTR
Description Disables the WDT when 0XACED8865 is written, for any other value WDT works normally Provides the count value of the WDT Stores the match value of the WDT Feeds the WDT to avoid reset
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12. Reset System
CCG3 supports several types of resets that guarantee error-free operation during power up and allow the device to reset based on user-supplied external hardware or internal software reset signals. CCG3 also contains hardware to enable the detection of certain resets. The reset system has these sources: Power-on reset (POR) to hold the device in reset while the power supply ramps up Brownout reset (BOD) to reset the device if the power supply falls below specifications during operation Watchdog reset (WRES) to reset the device if firmware execution fails to service the watchdog timer Software initiated reset (SRES) to reset the device on demand using firmware External reset (XRES) to reset the device using an electrical signal external to CCG3 Protection fault reset (PROT_FAULT) to reset the device if unauthorized operating conditions occur
12.1 Reset Sources
The following sections provide a description of the reset sources available in CCG3.
12.1.1 Power-on Reset
Power-on reset is provided for system reset at power-up. POR holds the device in reset until the supply voltage, VDDD, is according to the datasheet specification. The POR activates automatically at power-up. POR events do not set a reset cause status bit, but can be partially inferred by the absence of any other reset source. If no other reset event is detected, then the reset is caused by POR, BOD, or XRES.
12.1.2 Brownout Reset
Brownout reset monitors the digital voltage supply VCCD and generates a reset if VCCD is below the minimum logic operating voltage specified in the device datasheet. BOD is available in all power modes. BOD events do not set a reset cause status bit, but in some cases they can be detected. In some BOD events, VCCD will fall below the minimum logic operating voltage, but remain above the minimum logic retention voltage. Thus, some BOD events may be distinguished from POR events by checking for logic retention.
12.1.3 Watchdog Reset
Watchdog reset (WRES) detects errant code by causing a reset if the watchdog timer is not cleared within the user-specified time limit. This feature is enabled by setting the WDT_ENABLEx bit in the WDT_CONTROL register. The RESET_WDT status bit of the RES_CAUSE register is set when a watchdog reset occurs. This bit remains set until cleared or until a POR or BOD reset; for example, in the case of a device power cycle. All other resets leave this bit untouched. For more details, see the Watchdog Timer chapter on page 69
12.1.4 Software Initiated Reset
Software initiated reset (SRES) is a mechanism that allows a software-driven reset. The Cortex-M0 application interrupt and reset control register (CM0_AIRCR) forces a device reset when a `1' is written into the SYSRESETREQ bit. CM0_AIRCR requires a value of A05F written to the top two bytes for writes. Therefore, write A05F0004 for the reset. The RESET_SOFT status bit of the RES_CAUSE register is set when a software reset occurs. This bit remains set until
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cleared or until a POR or BOD reset; for example, in the case of a device power cycle. All other resets leave this bit untouched.
12.1.5 External Reset
External reset (XRES) is a user-supplied reset that causes immediate system reset when asserted. The XRES_N pin is active low a high voltage on the pin causes no behavior and a low voltage causes a reset. The pin is pulled high inside the device. XRES_N is available as a dedicated pin in most of the devices. For detailed pinout, refer to the pinout section of the device datasheet .
The XRES pin holds the device in reset while held active. When the pin is released, the device goes through a normal boot sequence. The logical thresholds for XRES and other electrical characteristics, are listed in the Electrical Specifications section of the device datasheet.
XRES events do not set a reset cause status bit, but can be partially inferred by the absence of any other reset source. If no other reset event is detected, then the reset is caused by POR, BOD, or XRES.
12.1.6 Protection Fault Reset
Protection fault reset (PROT_FAULT) detects unauthorized protection violations and causes a device reset if they occur.
One example of a protection fault is if a debug breakpoint is reached while executing privileged code. For details about privilege code, see Privileged on page 67.
The RESET_PROT_FAULT bit of the RES_CAUSE register is set when a protection fault occurs. This bit remains set until cleared or until a POR or BOD reset; for example, in the case of a device power cycle. All other resets leave this bit untouched.
12.2 Identifying Reset Sources
When the device comes out of reset, it is often useful to know the cause of the most recent or even older resets. This is achieved in the device primarily through the RES_CAUSE register. This register has specific status bits allocated for some of the reset sources. The RES_CAUSE register supports detection of watchdog reset, software reset, and protection fault reset. It does not record the occurrences of POR, BOD, or XRES. The bits are set on the occurrence of the corresponding reset and remain set after the reset, until cleared or a loss of retention, such as a POR reset or brownout below the logic retention voltage.
If the RES_CAUSE register cannot detect the cause of the reset, then it can be one of the non-recorded and non-retention resets: BOD, POR, or XRES. These resets cannot be distinguished using on-chip resources.
12.3 Register List
Table 12-1. Reset System Register List
Register Name WDT_CONTROL CM0_AIRCR RES_CAUSE
Description Watchdog Timer Control Register - This register allows configuration of the device watchdog timer. Cortex-M0 Application Interrupt and Reset Control Register - This register allows initiation of software resets, among other Cortex-M0 functions. Reset Cause Register - This register captures the cause of recent resets.
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13. Device Security
CCG3 offers a number of options for protecting user designs from unauthorized access or copying. Disabling debug features and robust flash protection provide a high level of security. The debug circuits are enabled by default and can only be disabled in firmware. If disabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging. Additionally, all device interfaces can be permanently disabled for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. Permanently disabling interfaces is not recommended for most applications because the designer cannot access the device. For more information, as well as a discussion of flash row and chip protection, see the CCG3 Programming Specifications. Note Because all programming, debug, and test interfaces are disabled when maximum device security is enabled, CCG3 devices with full device security enabled may not be returned for failure analysis.
13.1 Features
The CCG3 device security system has the following features: User-selectable levels of protection In the most secure case provided, the chip can be "locked" such that it cannot be acquired for test/debug and it cannot
enter erase cycles. Interrupting erase cycles is a known way for hackers to leave chips in an undefined state and open to observation. CPU execution in a privileged mode by use of the non-maskable interrupt (NMI). When in privileged mode, NMI remains asserted to prevent any inadvertent return from interrupt instructions causing a security leak.
13.2 How It Works
The CPU operates in normal user mode or in privileged mode, and the device operates in one of four protection modes: BOOT, OPEN, PROTECTED, and KILL. Each mode provides specific capabilities for the CPU software and debug. You can change the mode by writing to the CPUSS_PROTECTION register. BOOT mode: The device comes out of reset in BOOT mode. It stays there until its protection state is copied from super-
visor flash to the protection control register (CPUSS_PROTECTION). The debug-access port is stalled until this has happened. BOOT is a transitory mode required to set the part to its configured protection state. During BOOT mode, the CPU always operates in privileged mode. OPEN mode: This is the factory default. The CPU can operate in user mode or privileged mode. In user mode, flash can be programmed and debugger features are supported. In privileged mode, access restrictions are enforced. PROTECTED mode: The user may change the mode from OPEN to PROTECTED. This disables all debug access to user code or memory. Access to most registers is still available; debug access to registers to reprogram flash is not available. The mode can be set back to OPEN but only after completely erasing the flash. KILL mode: The user may change the mode from OPEN to KILL. This removes all debug access to user code or memory, and the flash cannot be erased. Access to most registers is still available; debug access to registers to reprogram flash is not available. The part cannot be taken out of KILL mode; devices in KILL mode may not be returned for failure analysis.
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Section E: Digital System
This section encompasses the following chapters: Serial Communications (SCB) chapter on page 79 Timer, Counter, and PWM chapter on page 117 Cryptography Block chapter on page 137 USB Full Speed (USB FS) chapter on page 157
Top Level Architecture
Digital System Block Diagram
Peripheral Interconnect (MMIO)
USB-FS
CRYPTO 4x TCPWM
4x SCB
High Speed I/O Matrix
FS-PHY
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14. Serial Communications (SCB)
The Serial Communications Block (SCB) of CCG3 supports three serial interface protocols: SPI, UART, and I2C. Only one of the protocols is supported by an SCB at any given time. CCG3 devices have four SCBs.
14.1 Features
This block supports the following features: Standard SPI master and slave functionality with Motorola, Texas Instruments, and National Semiconductor protocols Standard UART functionality with SmartCard reader, Local Interconnect Network, and IrDA protocols Standard I2C master and slave functionality SPI and I2C EZ mode, which allows for operation without CPU intervention Low-power (Deep-Sleep) mode of operation for SPI and I2C protocols (using external clocking) Each of the three protocols is explained in the following sections.
14.2 Serial Peripheral Interface (SPI)
The SPI protocol is a synchronous serial interface protocol. Devices operate in either master or slave mode. The master initiates the data transfer. The SCB supports single master-multiple slaves topology for SPI. Multiple slaves are supported with individual slave select lines. You can use the SPI master mode when the CCG3 has to communicate with one or more SPI slave devices. The SPI slave mode can be used when the CCG3 has to communicate with an SPI master device.
14.2.1 Features
Supports master and slave functionality Supports 3 types of SPI protocols:
Motorola SPI modes 0, 1, 2, and 3 TI SPI, with coinciding and preceding data frame indicator for mode 1 National (MicroWire) SPI for mode 0 Data frame size programmable from 4 bits to 16 bits Interrupts or polling CPU interface Programmable oversampling Supports EZ mode of operation (Easy SPI (EZSPI) Protocol (applicable only for SPI slave functionality)) Supports externally clocked slave operation: In this mode, the slave operates in Active, Sleep, and Deep-Sleep system power modes EZSPI mode allows for operation without CPU intervention
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14.2.2 General Description
Figure 14-1 illustrates an example of SPI master with four slaves. Figure 14-1. SPI Example
SPI Master
SCLK MOSI MISO Slave Select (SS) 1
SPI Slave 1
Slave Select (SS) 2 Slave Select (SS) 3
SPI Slave 2
SPI Slave 3
Slave Select (SS) 4
SPI Slave 4
A standard SPI interface consists of four signals as follows.
SCLK: Serial clock (clock output from the master, input to the slave).
MOSI: Master-out-slave-in (data output from the master, input to the slave).
MISO: Master-in-slave-out (data input to the master, output from the slave).
Slave Select (SS): Typically an active low signal (output from the master, input to the slave).
A simple SPI data transfer involves the following: the master selects a slave by driving its SS line, then it drives data on the MOSI line and a clock on the SCLK line, The slave uses the edges of SCLK to capture the data on the MOSI line; it also drives data on the MISO line, which is captured by the master.
By default, the SPI interface supports a data frame size of eight bits (1 byte). The data frame size can be configured to any value in the range 4 to 16 bits. The serial data can be transmitted either most significant bit (MSB) first or least significant bit (LSB) first.
Three different variants of the SPI protocol are supported by the SCB:
Motorola SPI: This is the original SPI protocol.
Texas Instruments SPI: A variation of the original SPI protocol, in which data frames are identified by a pulse on the SS line.
National Semiconductors SPI: A half duplex variation of the original SPI protocol.
14.2.3 SPI Modes of Operation
14.2.3.1 Motorola SPI
The original SPI protocol was defined by Motorola. It is a full duplex protocol. Multiple data transfers may happen with the SS line held at '0'. As a result, slave devices must keep track of the progress of data transfers to separate individual data frames. When not transmitting data, the SS line is held at '1' and SCLK is typically off.
Modes of Motorola SPI
The Motorola SPI protocol has four different modes based on how data is driven and captured on the MOSI and MISO lines. These modes are determined by clock polarity (CPOL) and clock phase (CPHA).
Clock polarity determines the value of the SCLK line when not transmitting data. CPOL = '0' indicates that SCLK is '0' when not transmitting data. CPOL = '1' indicates that SCLK is '1' when not transmitting data.
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Clock phase determines when data is driven and captured. CPHA=0 means sample (capture data) on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. With CPHA=0, the data must be stable for setup time before the first clock cycle.
Mode 0: CPOL is '0', CPHA is '0': Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK.
Mode 1; CPOL is '0', CPHA is '1': Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK.
Mode 2: CPOL is '1', CPHA is '0': Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK.
Mode 3: CPOL is '1', CPHA is '1': Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK.
Figure 14-2 illustrates driving and capturing of MOSI/MISO data as a function of CPOL and CPHA.
Figure 14-2. SPI Motorola, 4 Modes
CPOL = 0
CPHA = 0
SCLK
MISO /
MSB
LSB
MOSI
CPOL = 0
CPHA = 1
SCLK
MISO /
MSB
LSB
MOSI
SCLK
CPOL = 1
CPHA = 0
MISO / MOSI
MSB
LSB
SCLK
CPOL = 1
CPHA = 1
MISO /
MOSI
MSB
LSB
LEGEND: CPOL : Clock Polarity CPHA : Clock Phase SCLK : SPI interface clock MOSI : SPI Master-Out-Slave-In MISO : SPI Master-In-Slave-Out
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Figure 14-3 illustrates a single 8-bit data transfer and two successive 8-bit data transfers in mode 0 (CPOL is '0', CPHA is '0'). Figure 14-3. SPI Motorola Data Transfer Example
CPOL = 0, CPHA = 0 single data transfer
SCLK
Slave Select MOSI MISO
MSB MSB
LSB LSB
SCLK
CPOL = 0, CPHA = 0 two successive data transfers
Slave Select MOSI
MSB
LSB MSB
LSB
MISO
MSB
LSB MSB
LSB
LEGEND: CPOL : Clock Polarity CPHA : Clock Phase SCLK : SPI interface clock MOSI : SPI Master-Out-Slave-In MISO : SPI Master-In-Slave-Out
Configuring SCB for SPI Motorola Mode
To configure the SCB for SPI Motorola mode, set various register bits in the following order: 1. Select SPI by writing '01' to the SCB_MODE (bits
[25:24]) of the SCB_CTRL register. 2. Select SPI Motorola mode by writing '00' to the
SCB_MODE (bits [25:24]) of the SCB_SPI_CTRL register. 3. Select the mode of operation in Motorola by writing to the SCB_CPHA and SCB_CPOL fields (bits 2 and 3 respectively) of the SCB_SPI_CTRL register. 4. Follow steps 2 to 4 mentioned in Enabling and Initializing SPI on page 89.
For more information on these registers, see the CCG3 Registers TRM.
14.2.3.2 Texas Instruments SPI
The Texas Instruments' SPI protocol redefines the use of the SS signal. It uses the signal to indicate the start of a data transfer, rather than a low active slave select signal, as in the case of Motorola SPI. As a result, slave devices need
not keep track of the progress of data transfers to separate individual data frames. The start of a transfer is indicated by a high active pulse on slave select signal for a single bit transfer period. This pulse can be configured to occur one cycle before the transmission of the first data bit, or coincide with the transmission of the first data bit. The TI SPI protocol supports only mode 1 (CPOL is '0' and CPHA is '1'): data is driven on a rising edge of SCLK and data is captured on a falling edge of SCLK.
Figure 14-4 illustrates a single 8-bit data transfer and two successive 8-bit data transfers. The SELECT pulse precedes the first data bit. Note how the SELECT pulse of the second data transfer coincides with the last data bit of the first data transfer.
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SCLK Slave Select
MOSI MISO
SCLK Slave Select
MOSI MISO
Figure 14-4. SPI TI Data Transfer Example
CPOL=0, CPHA=1 single data transfer
Serial Communications (SCB)
MSB MSB
LSB LSB CPOL=0, CPHA=1 two successive data transfers
MSB
LSB MSB
LSB
MSB
LSB MSB
LSB
LEGEND: CPOL : Clock Polarity CPHA : Clock Phase SCLK : SPI interface clock MOSI : SPI Master-Out-Slave-In MISO : SPI Master-In-Slave-Out
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Figure 14-5 illustrates a single 8-bit data transfer and two successive 8-bit data transfers. The SELECT pulse coincides with the first data bit of a frame.
Figure 14-5. SPI TI Data Transfer Example
CPOL=0, CPHA=1 single data transfer
SCLK
Slave Select MOSI
MSB
LSB
MISO
MSB
LSB
SCLK Slave Select
MOSI MISO
MSB MSB
CPOL=0, CPHA=1 two successive data transfers
LSB MSB
LSB
LSB MSB
LSB
LEGEND: CPOL : Clock Polarity CPHA : Clock Phase SCLK : SPI interface clock MOSI : SPI Master-Out-Slave-In MISO : SPI Master-In-Slave-Out
Configuring the SCB for SPI TI Mode
To configure the SCB for SPI TI mode, set various register bits in the following order: 1. Select SPI by writing '01' to the SCB_MODE (bits
[25:24]) of the SCB_CTRL register. 2. Select SPI TI mode by writing '01' to the SCB_MODE
(bits [25:24]) of the SCB_SPI_CTRL register. 3. Select the mode of operation in TI by writing to the
SELECT_PRECEDE field (bit 1) of the SCB_SPI_CTRL register ('1' configures the SELECT pulse to precede the first bit of next frame and '0' otherwise). 4. Follow steps 2 to 4 mentioned in Enabling and Initializing SPI on page 89.
For more information on these registers, see the CCG3 Registers TRM.
14.2.3.3 National Semiconductors SPI
The National Semiconductors' SPI protocol is a half duplex protocol. Rather than transmission and reception occurring
at the same time, they take turns. The transmission and reception data sizes may differ. A single "idle" bit transfer period separates transmission from reception. However, the successive data transfers are NOT separated by an "idle" bit transfer period.
The National Semiconductors SPI protocol only supports mode 0 (CPOL is `0' and CPHA is `0'): data is driven on a falling edge of SCLK and data is captured on a rising edge of SCLK.
Figure 14-6 illustrates a single data transfer and two successive data transfers. In both cases the transmission data transfer size is eight bits and the reception data transfer size is four bits.
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Figure 14-6. SPI NS Data Transfer Example
CPOL=0, CPHA=0 Transfer of one MOSI and one MISO data frame
SCLK
Slave Select MOSI MISO
SCLK
MSB
LSB
MSB
LSB
"idle" `0' cycle CPOL=0, CPHA=0 Successive transfer of two MOSI and one MISO data frame
Slave Select MOSI
MSB
LSB
MSB
MISO
MSB
LSB
"idle" `0' cycle
LEGEND: CPOL : Clock Polarity CPHA : Clock Phase SCLK : SPI interface clock MOSI : SPI Master-Out-Slave-In MISO : SPI Master-In-Slave-Out
No "idle" cycle
Configuring the SCB for SPI NS Mode
To configure the SCB for SPI NS mode, set various register bits in the following order: 1. Select SPI by writing '01' to the SCB_MODE (bits
[25:24]) of the SCB_CTRL register. 2. Select SPI NS mode by writing '10' to the SCB_MODE
(bits [25:24]) of the SCB_SPI_CTRL register. 3. Follow steps 2 to 4 mentioned in Enabling and Initializing
SPI on page 89.
For more information on these registers, see the CCG3 Registers TRM.
14.2.4 Easy SPI (EZSPI) Protocol
The easy SPI (EZSPI) protocol is based on the Motorola SPI operating in mode 0 (CPOL is `0' and CPHA is `0'). EZSPI mode is applicable only for slave functionality in a single slave topology. It allows communication between a master and a single slave without the need for CPU intervention at the level of individual frames.
The EZSPI protocol defines an 8-bit EZ address that indexes a memory array (32-entry array of eight bit per entry is supported) located on the slave device. To address these 32 locations, the lower five bits of the EZ address are used. All EZSPI data transfers have 8-bit data frames.
Note The SCB has a FIFO memory, which is a 16 word by 16-bit SRAM, with byte write enable. The access methods for EZ and non-EZ functions are different. In non-EZ mode, the FIFO is split into TXFIFO and RXFIFO. Each has eight entries of 16 bits per entry. The 16-bit width per entry is used to accommodate configurable data width. In EZ mode, it is used as a single 32x8 bit EZFIFO because only a fixed 8-bit width data is used in EZ mode.
EZSPI has three types of transfers: a write of the EZ address from the master to the slave, a write of data from the master to an addressed slave memory location, and a read by the master from an addressed slave memory location.
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14.2.4.1 EZ Address Write
A write of the EZ address starts with a command byte (0x00) on the MOSI line indicating the master's intent to write the EZ address. The slave then drives a reply byte on the MISO line to indicate that the command is observed (0xFE) or not (0xFF). The second byte on the MOSI line is the EZ address.
14.2.4.2 Memory Array Write
A write to a memory array index starts with a command byte (0x01) on the MOSI line indicating the master's intent to write to the memory array. The slave then drives a reply byte on the MISO line to indicate that the command was observed (0xFE) or not (0xFF). Any additional write data bytes on the MOSI line are written to the memory array at locations indicated by the communicated EZ address. The EZ address is automatically incremented by the slave as bytes are written into the memory array. When the EZ address exceeds the maximum number of memory entries (32), it wraps around to 0.
14.2.4.3 Memory Array Read
A read from a memory array index starts with a command byte (0x02) on the MOSI line indicating the master's intent to read from the memory array. The slave then drives a reply byte on the MISO line to indicate that the command was observed (0xFE) or not (0xFF). Any additional read data bytes on the MISO line are read from the memory array at locations indicated by the communicated EZ address. The EZ address is automatically incremented by the slave as bytes are read from the memory array. When the EZ address exceeds the maximum number of memory entries (32), it wraps around to 0.
Figure 14-7 illustrates the write of EZ address, write to a memory array and read from a memory array operations in the EZSPI protocol.
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SCLK Slave Select
MOSI MISO
SCLK Slave Select
MOSI MISO
SCLK Slave Select
MOSI MISO
Figure 14-7. EZSPI Example
Command 0x00 : Write EZ address
Serial Communications (SCB)
Command 0x00
EZ Address
Command 0x01 : Write DATA
EZ address (8 bits) EZ address
Command 0x01
Write DATA
EZ address Command 0x02 : Read DATA
Write DATA
EZ buffer (32 bytes SRAM)
Read DATA
Command 0x02
LEGEND : CPOL : Clock Polarity CPHA : Clock Phase SCLK : SPI Interface Clock MISO : SPI Master-In-Slave-Out MOSI : SPI Master-Out-Slave-In
Read DATA
0x00 : Write EZ address 0x01 : Write DATA 0x02 : Read DATA 0xFE : "slave ready" 0xFF : "slave busy"
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14.2.4.4 Configuring SCB for EZSPI Mode
By default, the SCB is configured for non-EZ mode of operation. To configure the SCB for EZSPI mode, set various register bits in the following order:
1. Select EZ mode by writing '1' to the EZ_MODE bit (bit 10) of the SCB_CTRL register.
2. Follow steps 2 to 4 mentioned in Enabling and Initializing SPI on page 89.
3. Use continuous transmission mode for transmitter by writing '1' to the SCB_CONTINUOUS bit of SCB_SPI_CTRL register.
4. EZSPI mode is applicable only for slave functionality (write '0' to the SCB_MASTER_MODE field, bit 31 of SCB_SPI_CTRL register).
5. Set the data frame width eight bits long (write `0111' to the SCB_DATA_WIDTH field, bits [3:0] of SCB_TX_CTRL and SCB_RX_CTRL registers).
6. Set the shift direction as MSB first (write '1' to the SCB_MSB_FIRST field, bit 8 of SCB_TX_CTRL and SCB_RX_CTRL registers).
For more information on these registers, see the CCG3 Registers TRM.
14.2.5 SPI Registers
The SPI interface is controlled using a set of 32-bit control and status registers listed in Table 14-1. For more information on these registers, see the CCG3 Registers TRM.
Table 14-1. SPI Registers
Register Name SCB_CTRL SCB_STATUS SCB_SPI_CTRL SCB_SPI_STATUS SCB_TX_CTRL SCB_RX_CTRL SCB_TX_FIFO_CTRL SCB_RX_FIFO_CTRL SCB_TX_FIFO_WR
SCB_RX_FIFO_RD
SCB_RX_FIFO_RD_SILENT
SCB_TX_FIFO_STATUS
SCB_RX_FIFO_STATUS SCB_EZ_DATA
Operation
Enables the SCB, selects the type of serial interface (SPI, UART, I2C), and selects internally and externally clocked operation, EZ and non-EZ modes of operation.
In EZ mode, this register indicates whether the externally clocked logic is potentially using the EZ memory.
Configures the SPI as either a master or a slave, selects SPI protocols (Motorola, TI, National) and clockbased submodes in Motorola SPI (modes 0,1,2,3), selects the type of SELECT signal in TI SPI.
Indicates whether the SPI bus is busy and sets the SPI slave EZ address in the internally clocked mode.
Enables the transmitter, specifies the data frame width, and specifies whether MSB or LSB is the first bit in transmission.
Performs the same function as that of the SCB_TX_CTRL register, but for the receiver.
Specifies the trigger level, clears the transmitter FIFO and shift registers, and performs the FREEZE operation of the transmitter FIFO.
Performs the same function as that of the SCB_TX_FIFO_CTRL register, but for the receiver.
Holds the data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation.
Holds the data read from the receiver FIFO. Reading a data frame removes the data frame from the FIFO behavior is similar to that of a POP operation. This register has a side effect when read by software: a data frame is removed from the FIFO.
Holds the data read from the receiver FIFO. Reading a data frame does not remove the data frame from the FIFO; behavior is similar to that of a PEEK operation.
Indicates the number of bytes stored in the transmitter FIFO, the location from which a data frame is read by the hardware (read pointer), the location from which a new data frame is written (write pointer), and decides if the transmitter FIFO holds the valid data.
Performs the same function as that of the SCB_TX_FIFO_STATUS register, but for the receiver.
Holds the data in EZ memory location
14.2.6 SPI Interrupts
The SPI supports both internal and external interrupt requests. The internal interrupt events are listed here.
The SPI predefined interrupts can be classified as TX interrupts and RX interrupts. The TX interrupt output is the logical OR of the group of all possible TX interrupt sources. This signal goes high when any of the enabled TX interrupt sources are true. The RX interrupt output is the logical OR of the group of all possible RX interrupt sources. This signal goes high when any of the enabled Rx interrupt sources are
true. Various interrupt registers are used to determine the actual source of the interrupt.
The SPI supports interrupts on the following events: SPI transfer done SPI is Idle TX FIFO is not full TX FIFO is empty SPI Byte/Word transfer complete RX FIFO is empty
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RX FIFO is not empty Attempt to write to a full RX FIFO. RX FIFO is Full
14.2.7 Enabling and Initializing SPI
The SPI must be programmed in the following order:
1. Program protocol specific information using the SCB_SPI_CTRL register, according to Table 14-2. This includes selecting the submodes of the protocol and selecting master-slave functionality.
2. Program the generic transmitter and receiver information using the SCB_TX_CTRL and SCB_RX_CTRL registers, as shown in Table 14-3:
a. Specify the data frame width.
b. Specify whether MSB or LSB is the first bit to be transmitted/received.
c. Enable the transmitter and receiver.
3. Program the transmitter and receiver FIFOs using the SCB_TX_FIFO_CTRL and SCB_RX_FIFO_CTRL registers respectively, as shown in Table 14-4:
a. Set the trigger level.
b. Clear the transmitter and receiver FIFO and Shift registers.
c. Freeze the TX and RX FIFO.
4. Program SCB_CTRL register to enable the SCB block. Also select the mode of operation. These register bits are shown in Table 14-5.
Table 14-2. SCB_SPI_CTRL Register
Bits [25:24] 31
Name
MODE
MASTER_ MODE
Value 00 01
10 11 0 1
Description SPI Motorola submode SPI Texas Instruments submode SPI National Semiconductors submode Reserved Master mode Slave mode
Table 14-3. SCB_TX_CTRL/SCB_RX_CTRL Registers
Bits [3:0] 8 31
Name DATA_ WIDTH MSB_FIRST
ENABLED
Description
'DATA_WIDTH + 1' is the number of bits in the transmitted or received data frame. The valid range is [3, 15]. This does not include start, stop, and parity bits.
1= MSB first
0= LSB first
Transmitter enable bit for SCB_TX_CTRL and receiver enable bit for SCB_RX_CTRL registers. They must be enabled for all the protocols. Otherwise, the block may not function or the data may get lost.
Table 14-4. SCB_TX_FIFO_CTRL/SCB_RX_FIFO_CTRL Registers
Bits [2:0] 16 17
Name
Description
TRIGGER_LE VEL
Trigger level. When the transmitter FIFO has less entries or receiver FIFO has more entries than the value of this field, a transmitter or receiver trigger event is generated in the respective case.
CLEAR
When '1', the transmitter or receiver FIFO and the shift registers are cleared.
FREEZE
When '1', hardware reads/writes to the transmitter or receiver FIFO have no effect. Freeze does not advance the TX or RX FIFO read/write pointer.
Table 14-5. SCB_CTRL Register
Bits
Name
[25:24] MODE
31
ENABLED
Value 00 01 10 11 0 1
Description I2C mode SPI mode UART mode Reserved SCB block enabled SCB block disabled
After the block is enabled, control bits should not be changed. Changes should be made AFTER disabling the block; for example, to modify the operation mode (from Motorola mode to TI mode) or to go from externally to internally clocked operation (explained in Internally and Externally Clocked SPI Operations on page 90). The change takes effect only after the block is re-enabled. Note that reenabling the block causes re-initialization and the associated state is lost (for example, FIFO content).
The last step of initialization should always be to enable the block (write a '1' to the ENABLED bit of the SCB_CTRL register).
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14.2.8 Internally and Externally Clocked SPI Operations
The SCB supports both internally and externally clocked operations for SPI and I2C functions. An internally clocked operation uses a clock provided by the chip. An externally clocked operation uses a clock provided by the serial interface. Externally clocked operation enables operation in the Deep-Sleep system power mode, in which a no-chip internal clock is provided to the block.
Internally clocked operation uses the high-frequency clock of the system. For more information on system clocking, see the Clocking System chapter on page 57. It also supports oversampling. Oversampling is implemented with respect to the high-frequency clock. The SCB_OVS (bits [3:0]) of the SCB_CTRL register specify the oversampling.
In SPI master mode, the valid range for oversampling is 4 to 16. Hence, the maximum bit rate is 12 Mbps. However, if
you consider the I/O cell and routing delays, the effective oversampling range becomes 6 to 16. So, the maximum bit rate is 8 Mbps. Note LATE_MISO_SAMPLE must be set to '1' in SPIM mode.
In SPI slave mode, the oversampling field (bits [3:0]) of SCB_CTRL register is not used. However, there is a frequency requirement for the SCB clock with respect to the interface clock (SCLK). This requirement is expressed in terms of the ratio (SCB clock/SCLK). This ratio is dependent on two fields: MEDIAN of SCB_RX_CTRL register and LATE_MISO_SAMPLE of SCB_CTRL register. With the MEDIAN bit set to `0' and LATE_MISO_SAMPLE bit set to `1', the SCB can achieve a maximum bit rate of 16 Mbps. However, if you consider the I/O cell and routing delays, the maximum data rate that can be achieved becomes 8 Mbps. Based on these bits, the maximum bit rates are given in Table 14-6.
Table 14-6. SPI Slave Maximum Data Rates
Median of SCB_RX_CTRL
0 0 1 1
LATE_MISO_SAMPLE of SCB_CTRL Ratio Requirement Maximum Bit Rate at Peripheral Clock of 48 MHz
0
12
1
6
0
16
1
8
4 Mbps 8 Mbps 3 Mbps 6 Mbps
Externally clocked operation is limited to:
Slave functionality.
EZ functionality. EZ functionality uses the block's SRAM as a memory structure. Non-EZ functionality uses the block's SRAM as TX and RX FIFOs; FIFO support is not available in externally clocked operation.
Motorola mode 0 (in the case of SPI slave functionality).
Externally clocked EZ mode of operation can support a data rate of 48 Mbps (at a peripheral clock of 48 MHz).
Internally and externally clocked operation is determined by two register fields of the SCB_CTRL register:
EC_AM_MODE: Indicates whether SPI slave selection is internally ('0') or externally ('1') clocked. SPI slave selection comprises the first part of the protocol.
EC_OP_MODE: Indicates whether the rest of the protocol operation (besides SPI slave selection) is internally ('0') or externally ('1') clocked. As mentioned earlier, externally clocked operation does NOT support non-EZ functionality.
These two register fields determine the functional behavior of SPI. The register fields should be set based on the required behavior in Active, Sleep, and Deep-Sleep system power mode. Improper setting may result in faulty behavior in certain system power modes. Table 14-7 and Table 14-8 describe the settings for SPI (in EZ and non-EZ mode).
14.2.8.1 Non-EZ Mode of Operation
In non-EZ mode there are two possible settings. As externally clocked operation is not supported for non-EZ functionality (no FIFO support), EC_OP_MODE should always be set to '0'. However, EC_AM_MODE can be set to '0' or '1'. Table 14-7 gives an overview of the possibilities. The combination EC_AM_MODE=0 and EC_OP_MODE=1 is invalid and the block will not respond.
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Table 14-7. SPI Non-EZ Mode
System Power Mode Active and Sleep Deep-Sleep
SPI, Standard (non-EZ) Mode
EC_OP_MODE = 0
EC_OP_MODE = 1
EC_AM_MODE = 0
EC_AM_MODE = 1
EC_AM_MODE = 1
EC_AM_MODE=0
Selection using internal clock.
Operation using internal clock.
Selection using external clock: Wakeup interrupt cause is disabled in Active mode (MASK = 0) and in the Sleep mode, the MASK bit can be configured by the user.
After that, selection using internal clock.
Operation using internal clock.
Not supported
Invalid configuration
Not supported
Selection using external clock: Wakeup interrupt cause in enabled (MASK = 1).
Generate 0xff bytes.
Not supported
EC_OP_MODE is '0' and EC_AM_MODE is '0': This setting only works in Active and Sleep system power modes. The entire block's functionality is provided in the internally clocked domain.
EC_OP_MODE is '0' and EC_AM_MODE is '1': This setting works in Active and Sleep system power mode and provides limited (wake up) functionality in Deep-Sleep system power mode. SPI slave selection is performed by both the internally and externally clocked logic: in Active system power mode both are active and in Deep-Sleep system power mode only the externally clocked logic is active. When the externally clocked logic detects slave selection, it sets a wakeup interrupt cause bit, which can be used to generate an interrupt to wake up the CPU.
In Active system power mode, the CPU and the block's internally clocked slave selection logic are active and the wakeup interrupt cause is disabled (associated MASK bit is '0'). But in the Sleep mode, wakeup interrupt cause can be either enabled or disabled (MASK bit can be either '1' or '0') based on the application. The remaining operations in the Sleep mode are same as that of the Active mode. The internally clocked logic takes care of the ongoing SPI transfer.
In Deep-Sleep system power mode, the CPU needs to be woken up and the wakeup interrupt cause is enabled (MASK bit is '1'). Waking up takes time, so the ongoing SPI transfer is negatively acknowledged ('1' bits or "0xFF" bytes are send out on the MISO line) and the internally clocked logic takes care of the next SPI transfer when it is woken up.
14.2.8.2 EZ Mode of Operation
EZ mode has three possible settings. EC_AM_MODE can be set to '0' or '1' when EC_OP_MODE is '0' and EC_AM_MODE must be set to '1' when EC_OP_MODE is '1'. Table 14-8 gives an overview of the possibilities. The grey cells indicate a possible, yet not recommended, setting because it involves a switch from the externally clocked logic (slave selection) to the internally clocked logic (rest of the operation). The combination EC_AM_MODE=0 and EC_OP_MODE=1 is invalid and the block will not respond.
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Table 14-8. SPI EZ Mode
SPI, EZ Mode
EC_OP_MODE = 0
System Power Mode
EC_AM_MODE = 0
EC_AM_MODE = 1
Active and Sleep
Selection using internal clock.
Operation using internal clock.
Selection using external clock: Wakeup interrupt cause is disabled in Active mode (MASK = 0) and in Sleep mode, the mask bit can be configured by the user.
After that, selection using internal clock.
Operation using internal clock.
Deep-Sleep
Not supported
Selection using external clock: Wakeup interrupt cause is enabled (MASK = 1).
Generate 0xff bytes.
EC_OP_MODE = 1
EC_AM_MODE = 1
EC_AM_MODE=0
Selection using external clock.
Operation using external clock.
Invalid configuration
Selection using external clock.
Operation using external clock.
EC_OP_MODE is '0' and EC_AM_MODE is '0': This setting only works in Active system power mode. The entire block's functionality is provided in the internally clocked domain.
EC_OP_MODE is '0' and EC_AM_MODE is '1': This setting works in Active system power mode and provides limited (wake up) functionality in Deep-Sleep system power mode. SPI slave selection is performed by both the internally and externally clocked logic: in Active system power mode both are active and in Deep-Sleep system power mode only the externally clocked logic is active. When the externally clocked logic detects slave selection, it sets a wakeup interrupt cause bit, which can be used to generate an interrupt to wake up the CPU.
In Active system power mode, the CPU and the block's internally clocked slave selection logic are active and the wakeup interrupt cause is disabled (associated MASK bit is '0'). But in Sleep mode, wakeup interrupt cause can be either enabled or disabled (MASK bit can be either '1' or '0') based on the application. The remaining operations in the Sleep mode are same as that of the Active mode. The internally clocked logic takes care of the ongoing SPI transfer.
In Deep-Sleep system power mode, the CPU needs to be woken up and the wakeup interrupt cause is enabled (MASK bit is '1'). Waking up takes time, so the ongoing SPI transfer is negatively acknowledged ('1' bits or "0xFF" bytes are send out on the MISO line) and the internally clocked logic takes care of the next SPI transfer when it is woken up.
EC_OP_MODE is '1' and EC_AM_MODE is '1': This setting works in Active system power mode and Deep-Sleep system power mode. The SCB functionality is provided in the
externally clocked domain. Note that this setting results in externally clocked accesses to the block's SRAM. These accesses may conflict with internally clocked accesses from the device. This may cause wait states or bus errors. The field FIFO_BLOCK of the SCB_CTRL register determines whether wait states ('1') or bus errors ('0') are generated.
14.3 UART
The Universal Asynchronous Receiver/Transmitter (UART) protocol is an asynchronous serial interface protocol. UART communication is typically point-to-point. The UART interface consists of two signals: TX: Transmitter output RX: Receiver input
14.3.1 Features
Asynchronous transmitter and receiver functionality Supports a maximum data rate of 1 Mbps Supports UART protocol
Standard UART SmartCard (ISO7816) reader. IrDA Supports Local Interconnect Network (LIN) Break detection Baud rate detection Collision detection (ability to detect that a driven bit
value is not reflected on the bus, indicating that another component is driving the same bus).
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Multi-processor mode Data frame size programmable from 4 bits to 16 bits. Programmable number of STOP bits, which can be set
to 1, 1.5, or 2 data bits Parity support (odd and even parity) Interrupt or polling CPU interface Programmable oversampling
parity can be set to either even parity or odd parity. The option of using the parity bit is available only in the Standard UART and SmartCard UART modes. For IrDA UART mode, the parity bit is automatically disabled. Figure 14-9 depicts the default configuration of the UART interface of the SCB.
Note UART interface does not support external clocking operation. Hence, UART operates only in the Active and Sleep system power modes.
14.3.2 General Description
14.3.3 UART Modes of Operation
Figure 14-8 illustrates a standard UART TX and RX. Figure 14-8. UART Example
TX
RX
UART
RX
UART
TX
A typical UART transfer consists of a "Start Bit" followed by multiple "Data Bits", optionally followed by a "Parity Bit" and finally completed by one or more "Stop Bits". The Start and Stop bits indicate the start and end of data transmission. The Parity bit is sent by the transmitter and is used be the receiver to detect single bit errors. As the interface does not have a clock (asynchronous), the transmitter and receiver use their own clocks; also, they need to agree upon the period of a bit transfer.
14.3.3.1 Standard Protocol
A typical UART transfer consists of a start bit followed by multiple data bits, optionally followed by a parity bit and finally completed by one or more stop bits. The start bit value is always '0', the data bits values are dependent on the data transferred, the parity bit value is set to a value guaranteeing an even or odd parity over the data bits, and the stop bits value is '1'. The parity bit is generated by the transmitter and can be used by the receiver to detect single bit transmission errors. When not transmitting data, the TX line is '1' the same value as the stop bits.
Because the interface does not have a clock, the transmitter and receiver need to agree upon the period of a bit transfer. The transmitter and receiver have their own internal clocks. The receiver clock runs at a higher frequency than the bit transfer frequency, such that the receiver may oversample the incoming signal.
Three different serial interface protocols are supported:
Standard UART protocol
Multi-Processor Mode
Local Interconnect Network (LIN)
SmartCard, similar to UART, but with a possibility to send a negative acknowledgement
IrDA, modification to the UART with a modulation scheme
By default, UART supports a data frame width of eight bits. However, this can be configured to any value in the range of 4 to 9. This does not include start, stop, and parity bits. The number of stop bits can be in the range of 1 to 3. The parity bit can be either enabled or disabled. If enabled, the type of
The transition of a stop bit to a start bit is represented by a change from '1' to '0' on the TX line. This transition can be used by the receiver to synchronize with the transmitter clock. Synchronization at the start of each data transfer allows error-free transmission even in the presence of frequency drift between transmitter and receiver clocks. The required clock accuracy is dependent on the data transfer size.
The stop period or the amount of stop bits between successive data transfers is typically agreed upon between transmitter and receiver, and is typically in the range of 1 to 3-bit transfer periods.
Figure 14-9 illustrates the UART protocol.
Figure 14-9. UART, Standard Protocol Example
TX / RX IDLE
Two successive data transfers (7data bits, 1 parity bit, 2 stop bits)
START DATA DATA DATA DATA DATA DATA DATA PAR
STOP
START DATA DATA DATA
LEGEND: TX / RX : Transmit or Receive line
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The receiver oversamples the incoming signal; the value of the sample point in the middle of the bit transfer period (on the receiver's clock) is used. Figure 14-10 illustrates this.
Figure 14-10. UART, Standard Protocol Example (Single Sample)
TX clock
TX / RX
IDLE
START DATA DATA DATA DATA DATA DATA DATA PAR
STOP
START DATA DATA DATA
RX clock
Synchronisation
Sample points
LEGEND: TX / RX : Transmit or Receive line
Synchronisation
Sample points
Alternatively, three samples around the middle of the bit transfer period (on the receiver's clock) are used for a majority vote to increase accuracy. Figure 14-11 illustrates this.
Figure 14-11. UART, Standard Protocol (Multiple Samples)
TX clock
TX / RX
IDLE
START DATA DATA DATA DATA DATA DATA DATA PAR
STOP
START DATA DATA DATA
RX clock
Synchronisation
Sample points
LEGEND: TX / RX : Transmit or Receive line
Synchronisation
Sample points
UART Multi-Processor Mode
The UART_MP (multi-processor) mode is defined with "single-master-multi-slave" topology, as shown in Figure 14-12. This mode is also known as UART 9-bit protocol because the data field is nine bits wide. UART_MP is part of Standard UART mode.
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Figure 14-12. UART MP Mode Bus Connections
UART MP Master
TX
RX
TX
RX
UART MP Slave 1
TX
RX
UART MP Slave 2
Master TX
Master RX
TX
RX
UART MP Slave 3
The main properties of UART_MP mode are: Single master with multiple slave concept (multi-drop network) Each slave is identified by a unique address Using 9-bit data field, with the ninth bit as address/data flag (MP bit). When set high, it indicates an address byte; when
set low it indicates a data byte. A data frame is illustrated in Figure 14-13 Parity bit is disabled
Figure 14-13. UART MP Data Frame
DATA Field
IDLE
START DATA DATA DATA DATA DATA DATA DATA DATA MP
STOP
The SCB can be used as either master or slave device in UART_MP mode. Both SCB_TX_CTRL and SCB_RX_CTRL registers should be set to 9-bit data frame size. When the SCB works as UART_MP master device, the firmware changes the MP flag for every address or data frame. When it works as UART_MP slave device, the MP_MODE field of the SCB_UART_RX_CTRL register should be set to '1'. The SCB_RX_MATCH register should be set for the slave address and address mask. The matched address is written in the RX_FIFO when SCB_ADDRESS_ACCEPT field of the SCB_CTRL register is set to '1'. If received address does not match its own address, then the interface ignores the following data, until next address is received for compare.
UART supports both LIN master and slave functionality. Figure 14-14 illustrates the UART_LIN and LIN Transceiver.
UART LIN (Local Interconnect Network) Mode
The LIN (Local Interconnect Network) protocol is supported by the SCB as part of the standard UART. LIN is designed with single master-multi slave topology. There is one master node and multiple slave nodes on the LIN bus. The SCB
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Figure 14-14. UART_LIN and LIN Transceiver
LIN Master 1
LIN Slave 1
LIN Slave 2
UART LIN
TX
RX
LIN Transceiver
UART LIN
TX
RX
LIN Transceiver
UART LIN
TX
RX
LIN Transceiver
LIN BUS
LIN protocol defines two tasks: Master task: This task involves sending a header packet
to initiate a LIN transfer. Slave task: This task involves transmitting or receiving a
response. The master node supports master task and slave task; the slave node supports only slave task, as shown in Figure 14-15. Figure 14-15. LIN Bus Nodes and Tasks
LIN is based on the transmission of frames at pre-determined moments of time. A frame is divided into header and response fields. The header field consists of:
Break field (at least 13 bit periods with the value '0'). Sync field (a 0x55 byte frame). A sync field can be
used to synchronize the clock of the slave task with that of the master task. Identifier field (a frame specifying a specific slave). The response field consists of data and checksum. The UART LIN of SCB supports slave task, receiving the header and transmitting the response. It provides baud rate detection (using sync field - 0x55) operation. Apart from the break field, a frame transmission (both header and response) consist of one or multiple byte frame transmissions, with each byte transmission consisting of a start bit, 8 data bits and 1 or more stop bits (on both the UART TX and RX lines). To support LIN, a dedicated (off-chip) line driver/receiver is required. Supply voltage range on the LIN bus is 7 V to 18 V. Typically, LIN line drivers will drive the LIN line with the value provided on the SCB TX line and present the value on the
LIN line to the SCB RX line. By comparing TX and RX lines in the SCB, bus collisions can be detected (indicated by the SCB_UART_ARB_LOST field of the SCB_INTR_TX register).
Configuring the SCB as Standard UART interface
To configure the SCB as a standard UART interface, set various register bits in the following order:
1. Configure the SCB as UART interface by writing '10' to the SCB_MODE field (bits [25:24]) of the SCB_CTRL register.
2. Configure the UART interface to operate as a Standard protocol by writing '00' to the SCB_MODE field (bits [25:24]) of the SCB_UART_CTRL register.
3. To enable the UART MP Mode or UART LIN Mode, write '1' to the SCB_MP_MODE (bit 11) or SCB_LIN_MODE (bit 12) respectively of the SCB_UART_RX_CTRL register.
4. Follow steps 2 to 4 described in Enabling and Initializing UART on page 98.
For more information on these registers, see the CCG3 Registers TRM.
14.3.3.2 SmartCard (ISO7816)
ISO7816 is asynchronous serial interface, defined with single-master-single slave topology. ISO7816 defines both Reader (master) and Card (slave) functionality. For more information, refer to the ISO7816 Specification. Only master (reader) function is supported by the SCB. This block provides the basic physical layer support with asynchronous character transmission. UART_TX line is connected to SmartCard IO line, by internally multiplexing between UART_TX and UART_RX control modules.
The SmartCard transfer is similar to a UART transfer, with the addition of a negative acknowledgement (NACK) that may be sent from the receiver to the transmitter. A NACK is always '0'. Both master and slave may drive the same line, although never at the same time.
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A SmartCard transfer has the transmitter drive the start bit and data bits (and optionally a parity bit). After these bits, it enters its stop period by releasing the bus. Releasing results in the line being '1' (the value of a stop bit). After one bit transfer period into the stop period, the receiver may drive a NACK on the line (a value of '0') for one bit transfer period. This NACK is observed by the transmitter, which reacts by extending its stop period by one bit transfer period. For this
protocol to work, the stop period should be longer than one bit transfer period. Note that a data transfer with a NACK takes one bit transfer period longer, than a data transfer without a NACK. Typically, implementations use a tristate driver with a pull-up resistor, such that when the line is not transmitting data or transmitting the Stop bit, its value is '1'.
Figure 14-16 illustrates the SmartCard protocol.
Figure 14-16. SmartCard Example
TX / RX IDLE
Two successive data transfers (7data bits, 1 parity bit, 2 stop bits) without NACK
START DATA DATA DATA DATA DATA DATA DATA PAR
STOP
START DATA DATA DATA
TX / RX IDLE
Two successive data transfers (7data bits, 1 parity bit, 2 stop bits) with NACK
START DATA DATA DATA DATA DATA DATA DATA PAR
STOP NACK STOP START DATA DATA
LEGEND: TX / RX : Transmit or Receive line
The communication Baud rate for ISO7816 is given as:
Baud rate= f7816 × (D/F)
Where f7816 is the clock frequency, F is the clock rate conversion integer, and D is the baud rate adjustment integer.
By default, F = 372, D = f1, and the maximum clock frequency is 5 MHz. Thus, maximum baud rate is 13.4 Kbps. Typically, a 3.57-MHz clock is selected. The typical value of the baud rate is 9.6 Kbps.
Configuring SCB as UART SmartCard Interface
To configure the SCB as a UART SmartCard interface, set various register bits in the following order. For more information on these registers, see the CCG3 Registers TRM. 1. Configure the SCB as UART interface by writing '10' to
the SCB_MODE (bits [25:24]) of the SCB_CTRL register. 2. Configure the UART interface to operate as a SmartCard protocol by writing '01' to the SCB_MODE (bits [25:24]) of the SCB_UART_CTRL register. 3. Follow steps 2 to 4 described in Enabling and Initializing UART on page 98.
14.3.3.3 IrDA
The SCB supports the Infrared Data Association (IrDA) protocol for data rates of up to 115.2 Kbps using the UART interface. It supports only the basic physical layer of IrDA protocol with rates less than 115.2 Kbps. Hence, the system instantiating this block must consider how to implement a
complete IrDA communication system with other available system resources.
The IrDA protocol adds a modulation scheme to the UART signaling. At the transmitter, bits are modulated. At the receiver, bits are demodulated. The modulation scheme uses a Return-to-Zero-Inverted (RZI) format. A bit value of '0' is signaled by a short '1' pulse on the line and a bit value of '1' is signaled by holding the line to '0'. For these data rates (<=115.2 Kbps), the RZI modulation scheme is used and the pulse duration is 3/16 of the bit period. The sampling clock frequency should be set 16 times the selected baud rate, by configuring the SCB_OVS field of the SCB_CTRL register.
Different communication speeds under 115.2 Kbps can be achieved by configuring corresponding block clock frequency. Additional allowable rates are 2.4 Kbps, 9.6 Kbps, 19.2 Kbps, 38.4 Kbps, and 57.6 Kbps. An IrDA serial infrared interface operates at 9.6 Kbps. Figure 14-17 shows how a UART transfer is IrDA modulated.
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TX / RX IDLE
START `1'
Figure 14-17. IrDA Example Two successive data transfers (7data bits, 1 parity bit, 2 stop bits)
`0'
`1'
`1'
`0'
`0'
`1' PAR
STOP
START `0'
`1'
`1'
`1'
IrDA TX / RX
LEGEND: TX / RX : Transmit or Receive line
Configuring the SCB as UART IrDA Interface
To configure the SCB as a UART IrDA interface, set various register bits in the following order. For more information on these registers, see the CCG3 Registers TRM.
1. Configure the SCB as UART interface by writing '10' to the SCB_MODE (bits [25:24]) of the SCB_CTRL register.
2. Configure the UART interface to operate as IrDA protocol by writing '10' to the SCB_MODE (bits [25:24]) of the SCB_UART_CTRL register.
3. Configure the SCB as described in Enabling and Initializing UART on page 98.
14.3.4 UART Registers
The UART interface is controlled using a set of 32-bit registers listed in Table 14-9. For more information on these registers, see the CCG3 Registers TRM.
Table 14-9. UART Registers
Register Name
Operation
Used to select the sub-modes of UART SCB_UART_CTRL (standard UART, SmartCard, IrDA), also
used for local loop back control.
SCB_UART_STAT Used to specify the BR_COUNTER value
US
that determines the bit period.
SCB_UART_TX_C TRL
Used to specify the number of stop bits, enable parity, select the type of parity, and enable retransmission on NACK.
SCB_UART_RX_C TRL
Performs same function as SCB_UART_TX_CTRL but is also used for enabling multi processor mode, LIN mode drop on parity error, and drop on frame error.
SCB_TX_CTRL
Used to enable the transmitter, also to specify the data frame width and to specify whether MSB or LSB is the first bit in transmission.
SCB_RX_CTRL
Performs the same function as that of the SCB_TX_CTRL register, but for the receiver.
14.3.5 UART Interrupts
The UART supports both internal and external interrupt requests. The internal interrupt events are listed in this section.
The UART predefined interrupts can be classified as TX interrupts and RX interrupts. The TX interrupt output is the logical OR of the group of all possible TX interrupt sources. This signal goes high when any of the enabled TX interrupt sources are true. The RX interrupt output is the logical OR of the group of all possible RX interrupt sources. This signal goes high when any of the enabled Rx interrupt sources are true. The UART provides interrupts on the following events: UART transmission done. UART TX received a NACK in SmartCard mode. UART arbitration lost (in LIN or SmartCard modes). Frame error in received data frame. Parity error in received data frame. LIN baud rate detection is completed. LIN break detection is successful.
14.3.6 Enabling and Initializing UART
The UART must be programmed in the following order: 1. Program protocol specific information using the
SCB_UART_CTRL register, according to Table 14-10. This includes selecting the submodes of the protocol, transmitter-receiver functionality, and so on. 2. Program the generic transmitter and receiver information using the SCB_TX_CTRL and SCB_RX_CTRL registers, as shown in Table 14-11. a. Specify the data frame width. b. Specify whether MSB or LSB is the first bit to be
transmitted or received. c. Enable the transmitter and receiver. 3. Program the transmitter and receiver FIFOs using the SCB_TX_FIFO_CTRL and SCB_RX_FIFO_CTRL registers respectively, as shown in Table 14-12. a. Set the trigger level. b. Clear the transmitter and receiver FIFO and Shift
registers.
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c. Freeze the TX and RX FIFOs.
4. Program the SCB_CTRL register to enable the SCB block. Also select the mode of operation, as shown in Table 14-13.
Table 14-10. SCB_UART_CTRL Register
Bits
Name
[25:24]
MODE
16
LOOP_BACK
Value
Description
00
Standard UART
01
SmartCard
10
IrDA
11
Reserved
Loop back control. This allows a SCB UART transmitter to communicate with its receiver counterpart.
Table 14-11. SCB_TX_CTRL/SCB_RX_CTRL Registers
Bits [3:0] 8
31
Name DATA_ WIDTH MSB_FIRST
ENABLED
Description
'DATA_WIDTH + 1' is the no. of bits in the transmitted or received data frame. The valid range is [3, 15]. This does not include start, stop, and parity bits.
1= MSB first 0= LSB first
Transmitter enable bit for SCB_TX_CTRL and receiver enable bit for SCB_RX_CTRL registers. They must be enabled for all the protocols. Otherwise, the block may not function or the data may get lost.
Table 14-12. SCB_TX_FIFO_CTRL/SCB_RX_FIFO_CTRL Registers
Bits [2:0] 16 17
Name TRIGGER_LEVEL CLEAR FREEZE
Description
Trigger level. When the transmitter FIFO has less entries or receiver FIFO has more entries than the value of this field, a transmitter or receiver trigger event is generated in the respective case.
When '1', the transmitter or receiver FIFO and the shift registers are cleared/invalidated.
When '1', hardware reads/writes to the transmitter or receiver FIFO have no effect. Freeze will not advance the TX or RX FIFO read/write pointer.
Table 14-13. SCB_CTRL Register
Bits
Name
[25:24]
MODE
31
ENABLED
Value 00 01 10 11 0 1
Description I2C mode SPI mode UART mode Reserved SCB block enabled SCB block disabled
After the block is enabled, control bits should not be changed. Changes should be made AFTER disabling the block; for example, to modify the operation mode (from SmartCard to IrDA). The change takes effect only after the block is re-enabled. Note that re-enabling the block causes re-initialization and the associated state is lost (for example FIFO content).
The last step of initialization should always be to enable the block (write a '1' to the ENABLED bit of the SCB_CTRL register).
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14.4 Inter Integrated Circuit (I2C)
CCG3 contains a Serial Communication Block (SCB) configured to operate as a I2C block. This section explains the I2C implementation in CCG3. For more information on the I2C protocol specification, refer to the I2C-bus specification available on the NXP website.
14.4.1 Features
CCG3 supports the following I2C features: Master, slave, and master/slave mode Slow-mode (50 kbps), standard-mode (100 kbps), fast-
mode (400 kbps), and fast-mode plus (1000 kbps) datarates
7- or 10-bit slave addressing (10-bit addressing requires firmware support)
Clock stretching and collision detection Programmable oversampling of I2C clock signal (SCL) Error reduction using an digital median filter on the input
path of the I2C data signal (SDA) Glitch-free signal transmission with an analog glitch filter Interrupt or polling CPU interface Supports EZ mode of operation (Easy I2C (EZI2C) Pro-
tocol - applicable only for I2C slave functionality)
14.4.2 General Description
Figure 14-18 illustrates an example of an I2C communication network.
Figure 14-18. I2C Interface Block Diagram
VDD
Rp
Rp
SCL SDA
I2C Master
I2C Slave
I2C Slave
I2C Slave
The standard I2C bus is a two wire interface with the following lines:
Serial Data (SDA)
Serial Clock (SCL)
I2C devices are connected to these lines using open collector or open-drain output stages, with pull-up resistors (Rp). A simple master/slave relationship exists between devices. Masters and slaves can operate as either transmitter or receiver. Each slave device connected to the bus is software addressable by a unique 7-bit address.
14.4.3 Terms and Definitions
Table 14-14 explains the commonly used terms in an I2C communication network.
Table 14-14. Definition of I2C Bus Terminology
Term Transmitter Receiver
Master
Description The device that sends data to the bus The device that receives data from the bus The device that initiates a transfer, generates clock signals, and terminates a transfer
Table 14-14. Definition of I2C Bus Terminology
Term Slave Multi-master
Arbitration
Synchronization
Description
The device addressed by a master
More than one master can attempt to control the bus at the same time without corrupting the message
Procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the winning message is not corrupted
Procedure to synchronize the clock signals of two or more devices
Bus Stalling (Clock Stretching)
When a slave device is not yet ready to process data, it may drive a `0' on the SCL line to hold it down. Due to the implementation of the I/O signal interface, the SCL line value will be '0', independent of the values that any other master or slave may be driving on the SCL line. This is known as clock stretching and is the only situation in which a slave drives the SCL line. The master device monitors the SCL line and detects it when it cannot generate a positive clock pulse ('1') on the SCL line. It then reacts by postponing the generation
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of a positive edge on the SCL line, effectively synchronizing with the slave device that is stretching the clock.
Bus Arbitration
The I2C protocol is a multi-master, multi-slave interface. Bus arbitration is implemented on master devices by monitoring the SDA line. Bus collisions are detected when the master observes an SDA line value that is not the same as the value it is driving on the SDA line. For example, when master 1 is driving the value '1' on the SDA line and master 2 is driving the value '0' on the SDA line, the actual line value will be '0' due to the implementation of the I/O signal interface. Master 1 detects the inconsistency and loses control of the bus. Master 2 does not detect any inconsistency and keeps control of the bus.
14.4.4 I2C Modes of Operation
I2C is a synchronous single master, multi-master, multislave serial interface. Devices operate in either master mode, slave mode, or master/slave mode. In master/slave mode, the device switches from master to slave mode when it is addressed. Only a single master may be active during a data transfer. The active master is responsible for driving the clock on the SCL line.
Table 14-15 illustrates the I2C modes of operation.
Table 14-15. I2C Modes
Mode Slave Master Multi-master
Multi-master-slave
Description Slave only operation (default) Master only operation Supports more than one master on the bus Simultaneous slave and multi-master operation
Table 14-16. I2C Bus Events Terminology
Bus Event STOP
ACK
NACK Repeated START
Description
A LOW to HIGH transition on the SDA line while SCL is HIGH
The receiver pulls the SDA line LOW and it remains LOW during the HIGH period of the clock pulse after the transmitter transmits each byte.
The receiver does not pull the SDA line LOW and it remains HIGH during the HIGH period of clock pulse after the transmitter transmits each byte.
START condition generated by master at the end of a transfer instead of a STOP condition
When operating in multi-master mode, the bus should always be checked to see if it is busy; another master may already be communicating with a slave. In this case, the master must wait until the current operation is complete before issuing a START signal (see Table 14-16, Figure 14-19 and Figure 14-20). The master looks for a STOP signal as an indicator that it can start its data transmission.
When operating in multi-master-slave mode, if the master loses arbitration during data transmission, the hardware reverts to slave mode and the received byte generates a slave address interrupt.
With all of these modes, there are two types of transfer read and write. In write transfer, the master sends data to slave; in read transfer, the master receives data from slave. Write and read transfer examples are available in Master Mode Transfer Examples on page 108, Slave Mode Transfer Examples on page 110, and Multi-Master Mode Transfer Example on page 114.
Data transfer through the I2C bus follows a specific format. Table 14-16 lists some common bus events that are part of an I2C data transfer. The Write Transfer and Read Transfer sections explain the format of bits on an I2C bus during data transfer.
Table 14-16. I2C Bus Events Terminology
Bus Event START
Description
A HIGH to LOW transition on the SDA line while SCL is HIGH
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14.4.4.1 Write Transfer
SDA
MSB
Figure 14-19. Master Write Data Transfer Write data transfer(Master writes the data)
LSB
SCL START
Slave address (7 bits)
Write ACK
Data(8 bits)
ACK STOP
LEGEND :
SDA: SCL:
Serial Data Line Serial Clock Line(always driven by the master)
Slave Transmit / Master Receive
A typical write transfer begins with the master generating a START condition on the I2C bus. The master then writes a 7-bit I2C slave address and a write indicator ('0') after the START condition. The addressed slave transmits an acknowledgement byte by pulling the data line low during the ninth bit time.
If the slave address does not match any of the slave devices or if the addressed device does not want to acknowledge the request, it transmits a no acknowledgement (NACK). The absence of an acknowledgement, results in an SDA line value of '1' due to the pullup resistor implementation.
If no acknowledgement is transmitted by the slave, the master may end the write transfer with a STOP event. The master can also generate a repeated START condition for a retry attempt.
The master may transmit write data to the bus if it receives an acknowledgement. The addressed slave transmits an acknowledgement to confirm the receipt of the write data. Upon receipt of this acknowledgement, the master may transmit another data byte.
When the transfer is complete, the master generates a STOP condition.
14.4.4.2 Read Transfer
Figure 14-20. Master Read Data Transfer
SDA
MSB
Read data transfer(Master reads the data)
LSB
SCL
START
Slave address (7 bits)
Read ACK
LEGEND : SDA: SCL:
Serial Data Line Serial Clock Line(always driven by the master)
Data(8 bits)
ACK STOP
Slave Transmit / Master Receive
A typical read transfer begins with the master generating a START condition on the I2C bus. The master then writes a 7-bit I2C slave address and a read indicator ('1') after the START condition. The addressed slave transmits an acknowledgement by pulling the data line low during the ninth bit time.
If the slave address does not match with that of the connected slave device or if the addressed device does not want to acknowledge the request, a no acknowledgement (NACK) is transmitted. The absence of an
acknowledgement, results in an SDA line value of '1' due to the pull-up resistor implementation.
If no acknowledgement is transmitted by the slave, the master may end the read transfer with a STOP event. The master can also generate a repeated START condition for a retry attempt.
If the slave acknowledges the address, it starts transmitting data after the acknowledgement signal. The master transmits an acknowledgement to confirm the receipt of each data byte sent by the slave. Upon receipt of this
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acknowledgement, the addressed slave may transmit another data byte.
The master can send a NACK signal to the slave to stop the slave from sending data bytes. This completes the read transfer.
When the transfer is complete, the master generates a STOP condition.
14.4.5 Easy I2C (EZI2C) Protocol
The Easy I2C (EZI2C) protocol is a unique communication scheme built on top of the I2C protocol by Cypress. EZI2C mode is applicable only for slave functionality. It uses a software wrapper around the standard I2C protocol to communicate to an I2C slave using indexed memory transfers. This removes the need for CPU intervention at the level of individual frames.
The EZI2C protocol defines an 8-bit EZ address that indexes a memory array (8-bit wide 32 locations) located on the slave device. Five lower bits of the EZ address is used to address these 32 locations. The number of bytes transferred to or from the EZI2C memory array can be found by comparing the EZ address at the START event and the EZ address at the STOP event.
Note The I2C block has a hardware FIFO memory, which is 16 bits wide and 16 locations deep with byte write enable. The access methods for EZ and non-EZ functions are different. In non-EZ mode, the FIFO is split into TXFIFO and RXFIFO. Each has 16-bit wide eight locations. In EZ mode, the FIFO is used as a single memory unit with 8-bit wide 32 locations.
EZI2C has two types of transfers: an EZ write of data from the master to an addressed slave memory location, and a read by the master from an addressed slave memory location.
14.4.6 Memory Array Write
An EZ write to a memory array index is by means of an I2C write transfer. The first transmitted write data is used to send an EZ address from the master to the slave. The five lowest significant bits of the write data are used as the "new" EZ address at the slave. Any additional write data elements in the write transfer are bytes that are written to the memory array. The EZ address is automatically incremented by the slave as bytes are written into the memory array. When the EZ address exceeds 32 memory entries, it wraps around to 0.
14.4.7 Memory Array Read
An EZ read from a memory array index is by means of an I2C read transfer. The EZ read relies on an earlier EZ write to have set the EZ address at the slave. The first received read data is the byte from the memory array at the EZ address memory location. The EZ address is automatically
incremented as bytes are read from the memory array. When the EZ address exceeds the 32 memory entries, it wraps around to 0.
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SDA
MS B
Figure 14-21. EZI2C Write and Read Data Transfer
Write data transfer(single write data)
LS B
SCL START Slave address (7 bits)
Write ACK
EZ address(8 bits)
ACK
Write Data(8 bits)
ACK STOP
EZ address
Data
Address
EZ Buffer (32 bytes SRAM)
SDA
MSB
SCL
Read data transfer(single read data)
LSB
START
Slave address (7 bits)
Read ACK
LEGEND :
SDA:
Serial Data Line
SCL:
Serial Clock Line(always driven by the master)
Slave Transmit / Master Receive
Read Data(8 bits)
ACK STOP
See EZ Slave Mode Transfer Example on page 112 for examples.
14.4.8 I2C Registers
The I2C interface is controlled by reading and writing a set of configuration, control, and status registers, as listed in Table 14-17.
Table 14-17. I2C Registers
Register SCB_CTRL SCB_I2C_CTRL SCB_I2C_STATUS SCB_I2C_M_CMD SCB_I2C_S_CMD SCB_STATUS
SCB_TX_CTRL
SCB_TX_FIFO_CTRL
SCB_TX_FIFO_STATUS
Function
Enables the SCB I2C block and selects the type of serial interface (SPI, UART, I2C). Also used to select internally and externally clocked operation and EZ and non-EZ modes of operation.
Selects the mode (master, slave) and sends an ACK or NACK signal based on receiver FIFO status.
Indicates bus busy status detection, read/write transfer status of the slave/master, and stores the EZ slave address.
Enables the master to generate START, STOP, and ACK/NACK signals.
Enables the slave to generate ACK/NACK signals.
Indicates whether the externally clocked logic is using the EZ memory. This bit can be used by software to determine whether it is safe to issue a software access to the EZ memory.
Enables the transmitter and specifies the data frame width; also used to specify whether MSB or LSB is the first bit in transmission.
Specifies the trigger level, clearing of the transmitter FIFO and shift registers, and FREEZE operation of the transmitter FIFO.
Indicates the number of bytes stored in the transmitter FIFO, the location from which a data frame is read by the hardware (read pointer), the location from which a new data frame is written (write pointer), and decides if the transmitter FIFO holds the valid data.
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Table 14-17. I2C Registers
Register
Function
SCB_TX_FIFO_WR
Holds the data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation.
SCB_RX_CTRL
Performs the same function as that of the SCB_TX_CTRL register, but for the receiver.
SCB_RX_FIFO_CTRL
Performs the same function as that of the SCB_TX_FIFO_CTRL register, but for the receiver.
SCB_RX_FIFO_STATUS
Performs the same function as that of the SCB_TX_FIFO_STATUS register, but for the receiver.
SCB_RX_FIFO_RD
Holds the data read from the receiver FIFO. Reading a data frame removes the data frame from the FIFO; behavior is similar to that of a POP operation. This register has a side effect when read by software: a data frame is removed from the FIFO.
SCB_RX_FIFO_RD_SILENT
Holds the data read from the receiver FIFO. Reading a data frame does not remove the data frame from the FIFO; behavior is similar to that of a PEEK operation.
SCB_RX_MATCH
Stores slave device address and is also used as slave device address MASK.
SCB_EZ_DATA
Holds the data in an EZ memory location.
Note Detailed descriptions of the I2C register bits are available in the CCG3 Registers TRM.
14.4.9 I2C Interrupts
The I2C block generates interrupts for the following conditions. Arbitration lost Slave address match I2C bus stop/start condition detected I2C bus error detected I2C byte/word transfer complete I2C TX FIFO not full I2C TX FIFO empty I2C RX FIFO empty I2C RX FIFO not empty I2C RX FIFO overrun I2C RX FIFO full
The I2C interrupt signal is hard-wired to the Cortex-M0 NVIC and cannot be routed to external pins.
The interrupt output is the logical OR of the group of all possible interrupt sources. The interrupt is triggered when any of the enabled interrupt conditions are met. Interrupt status registers are used to determine the actual source of the interrupt. For more information on interrupt registers, see the CCG3 Registers TRM.
Configuring for I2C Standard (Non-EZ) Mode
The I2C interface must be programmed in the following order.
1. Program protocol specific information using the SCB_I2C_CTRL register according to Table 14-18. This includes selecting master - slave functionality.
2. Program the generic transmitter and receiver information using the SCB_TX_CTRL and SCB_RX_CTRL registers, as shown in Table 14-19.
a. Specify the data frame width.
b. Specify whether MSB or LSB is the first bit to be transmitted/received.
c. Enable the transmitter and receiver.
3. Program transmitter and receiver FIFO using the SCB_TX_FIFO_CTRL and SCB_RX_FIFO_CTRL registers, respectively, as shown in Table 14-20.
a. Set the trigger level.
b. Clear the transmitter and receiver FIFO and Shift registers.
4. Program the SCB_CTRL register to enable the SCB block and select the I2C mode. These register bits are shown in Table 14-21. For a complete description of the I2C registers, see the CCG3 Registers TRM.
14.4.10 Enabling and Initializing the I2C
The following section describes the method to configure the I2C block for standard (non-EZ) mode and EZI2C mode.
Table 14-18. SCB_I2C_CTRL Register
Bits 30 31
Name SLAVE_MODE MASTER_MODE
Value 1 1
Slave mode Master mode
Description
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Table 14-19. SCB_TX_CTRL/SCB_RX_CTRL Register
Bits [3:0] 8
31
Name DATA_ WIDTH MSB_FIRST
ENABLED
Description 'DATA_WIDTH + 1' is the number of bits in the transmitted or received data frame. The valid range is [3, 15]. 1= MSB first 0= LSB first Transmitter enable bit for SCB_TX_CTRL and receiver enable bit for SCB_RX_CTRL registers. They must be enabled for all the protocols. Otherwise, the block may not function or the data may get lost.
Table 14-20. SCB_TX_FIFO_CTRL/ SCB_RX_FIFO_CTRL
Bits [2:0] 16 17
Name TRIGGER_LEVEL CLEAR FREEZE
Description
Trigger level. When the transmitter FIFO has less entries or the receiver FIFO has more entries than the value of this field, a transmitter or receiver trigger event is generated in the respective case.
When '1', the transmitter or receiver FIFO and the shift registers are cleared.
When '1', hardware reads/writes to the transmitter or receiver FIFO have no effect. Freeze does not advance the TX or RX FIFO read/write pointer.
Table 14-21. SCB_CTRL Registers
Bits
Name
[25:24]
MODE
31
ENABLED
Value 00 01 10 11 0 1
Description I2C mode SPI mode UART mode Reserved SCB block enabled SCB block disabled
Configuring for EZI2C Mode
To configure the SCB block for EZI2C mode, set the following I2C register bits 1. Select the EZI2C mode by writing '1' to the EZ_MODE
bit (bit 10) of the SCB_CTRL register. 2. Follow steps 2 to 4 mentioned in Configuring for I2C
Standard (Non-EZ) Mode. 3. Set the S_READY_ADDR_ACK (bit 12) and
S_READY_DATA_ACK (bit 13) bits of the SCB_I2C_CTRL register.
14.4.11 Internal and External Clock Operation in I2C
The SCB supports both internally and externally clocked operation for data-rate generation. Internally clocked operations use a clock signal derived from the CCG3 system bus clock. Externally clocked operations use a clock provided by the user. Externally clocked operation allows limited functionality in the Deep-Sleep power mode, in which on-chip clocks are not active. For more information on system clocking, see the Clocking System chapter on page 57.
Externally clocked operation is limited to the following cases: Slave functionality.
EZ functionality. TX and RX FIFOs do not support externally clocked operation; therefore, it is not used for nonEZ functionality.
Internally and externally clocked operations are determined by two register fields of the SCB_CTRL register:
EC_AM_MODE (Externally Clocked Address Matching Mode): Indicates whether I2C address matching is internally ('0') or externally ('1') clocked.
EC_OP_MODE (Externally Clocked Operation Mode): Indicates whether the rest of the protocol operation (besides I2C address match) is internally ('0') or externally ('1') clocked. As mentioned earlier, externally clocked operation does not support non-EZ functionality.
These two register fields determine the functional behavior of I2C. The register fields should be set based on the required behavior in Active, Sleep, and Deep-Sleep system power modes. Improper setting may result in faulty behavior in certain power modes. Table 14-22 and Table 14-22 describe the settings for I2C in EZ and non-EZ mode.
14.4.11.1 I2C Non-EZ Operation Mode
Externally clocked operation is not supported for non-EZ functionality because there is no FIFO support for this mode. So, the EC_OP_MODE should always be set to '0' for nonEZ mode. However, EC_AM_MODE can be set to '0' or '1'. Table 14-9 gives an overview of the possibilities. The combi-
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nation EC_AM_MODE = 0 and EC_OP_MODE = 1 is invalid and the block will not respond.
EC_AM_MODE is '0' and EC_OP_MODE is '0'. This setting only works in Active and Sleep system power modes. All the I2C's functionality is provided in the internally clocked domain.
EC_AM_MODE is '1' and EC_OP_MODE is '0'. This setting works in Active and Deep-Sleep system power modes. I2C address matching is performed by the externally clocked logic in both these modes. When the externally clocked logic matches the address, it sets a wakeup interrupt cause bit, which can be used to generate an interrupt to wakeup the CPU.
In Active system power mode, the CPU is active and the wakeup interrupt cause is disabled (associated MASK bit is '0'). The externally clocked logic takes care of the address matching and the internally locked logic takes care of the rest of the I2C transfer.
In the Sleep mode, wakeup interrupt cause can be either enabled or disabled based on the application. The remaining operations are similar to the Active mode.
In the Deep-Sleep mode, the CPU is shut down and will wake up on I2C activity if the wakeup interrupt cause is enabled. CPU wakeup up takes time and the ongoing I2C transfer is either negatively acknowledged (NACK) or the clock is stretched. In the case of a NACK, the internally clocked logic takes care of the first I2C transfer after it wakes up. For clock stretching, the internally clocked logic takes care of the ongoing/stretched transfer when it wakes up. The register bit S_NOT_READY_ADDR_NACK (bit 14) of the SCB_I2C_CTRL register determines whether the externally clocked logic performs a negative acknowledge ('1') or clock stretch ('0').
14.4.11.2 EZ Operation Mode
EZ mode has three possible settings. EC_AM_MODE can be set to '0' or '1' when EC_OP_MODE is '0' and EC_AM_MODE must be set to '1' when EC_OP_MODE is '1'. Table 14-22 gives an overview of the possibilities. The grey cells indicate a possible, yet not recommended setting because it involves a switch from the externally clocked logic (slave selection) to the internally clocked logic (rest of the operation). The combination EC_AM_MODE=0 and EC_OP_MODE=1 is invalid and the block will not respond.
Table 14-22. I2C EZ Mode
System Power Mode Active and Sleep Deep-Sleep
I2C, EZ Mode
EC_OP_MODE= 0
EC_AM_MODE = 0
EC_AM_MODE = 1
Address match using internal clock
Operation using internal clock
Address match using external clock
Operation using internal clock
Not supported
Address match using external clock
Operation using internal clock
EC_OP_MODE = 1
EC_AM_MODE = 1
EC_AM_MODE=0
Address match using external clock Operation using external clock
Address match using external clock Operation using external clock
Invalid configuration
EC_AM_MODE is '0' and EC_OP_MODE is '0'. This setting only works in Active/Sleep system power mode.
EC_AM_MODE is '1' and EC_OP_MODE is '0'. This setting works same as I2C non-EZ mode.
EC_AM_MODE is '1' and EC_OP_MODE is '1'. This setting works in Active system power mode and DeepSleep system power mode.
The SCB functionality is provided in the externally clocked domain. Note that this setting results in externally clocked accesses to the block's SRAM. These accesses may conflict with internally clocked accesses from the device. This may cause wait states or bus errors. The field FIFO_BLOCK (bit 17) of the SCB_CTRL register determines whether wait states ('1') or bus errors ('0') are generated.
14.4.12 Wake up from Sleep
The system wakes up from Sleep or Deep-Sleep system power modes when an I2C address match occurs. The I2C block performs either of two actions after address match: Address ACK or Address NACK.
Address ACK - The I2C slave executes clock stretching and waits until the device wakes up and ACKs the address.
Address NACK - The I2C slave NACKs the address immediately. The master must poll the slave again after the device wakeup time is passed. This option is only valid in the slave or multi-master-slave modes.
Note The interrupt bit WAKEUP (bit 0) of the INTR_I2C_EC register must be enabled for the I2C to wake up the device on slave address match while switching to the Sleep mode.
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14.4.13 Master Mode Transfer Examples
Master mode transmits or receives data.
14.4.13.1 Master Transmit
Figure 14-22. Single Master Mode Write Operation Flow Chart
Begin
Default
Disable Fixed Function I2C block
Select Master mode
Enable TX FIFO
Enable Fixed Function I2C block
Send START signal
RESTART
No
Transmission
(stretch)
of one byte
Error
slave address
E
complete?
Yes
Address ACK'ed or NACK'ed?
NACK
STOP/ RESTART
ACK
Set Fixed Function I2C block to transmit
mode
TX FIFO Empty?
Yes
E
No
No
(stretch)
Transmission
Error
of one byte
E
data complete?
Yes
Byte ACK'ed or NACK'ed?
ACK
NACK
STOP/ RESTART
No
Data transfer
complete?
Yes
Send STOP signal
STOP
Begin
E
Report and handle error
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14.4.13.2 Master Receive
Figure 14-23. Single Master Mode Read Operation Flow Chart
Begin
Default
Disable Fixed Function I2C block
RX FIFO full?
No
Yes E
Select Master mode
Enable RX FIFO
Enable Fixed Function I2C block
No
Receiving
one byte data
complete?
Yes
Send ACK
No Data transfer complete?
Yes
Send NACK
Error
E
STOP
Send START signal
RESTART
No
Transmission
(stretch)
of one byte
Error
slave address
E
complete?
Yes
Address ACK'ed or NACK'ed?
NACK
STOP/ RESTART
ACK
Set Fixed Function I2C block
to receive mode
Send STOP signal
Begin
E
Report and handle error
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14.4.14 Slave Mode Transfer Examples
Slave mode transmits or receives data.
14.4.14.1 Slave Transmit
Figure 14-24. Slave Mode Write Operation Flow Chart
Begin
Default
Disable Fixed Function I2C block
TX FIFO empty?
No
Yes E
Select Slave mode
Enable TX FIFO
Enable Fixed Function I2C block
START detected
No
Receiving
(stretch)
one byte slave
Error
address
E
complete?
Wake up Yes
Address ACK'ed or NACK'ed?
NACK
ACK
Set Fixed Function I2C block
to transmit mode
No
Transmitting one byte
Error
data complete?
E
Yes
Byte ACK'ed or NACK'ed?
ACK
NACK
Begin
No
Data transfer
complete?
Yes
Begin
E
Report and handle error
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14.4.14.2 Slave Receive
Figure 14-25. Slave Mode Read Operation Flow Chart
Begin
Default
Disable Fixed Function I2C block
Select Slave mode
Enable RX FIFO
Enable Fixed Function I2C block
START detected
No
Receiving
(stretch)
one byte
Error
slave address
E
complete?
Wake up Yes
NACK
Address ACK'ed or NACK'ed?
ACK
Set Fixed Function I2C block to receive mode
RX FIFO full?
No
Yes E
No (stretch)
Receiving one byte data complete?
Error E
Yes
Send ACK
No Data transfer complete?
Yes
Send NACK
Begin
E
Report and handle error
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14.4.15 EZ Slave Mode Transfer Example
The EZ Slave mode transmits or receives data.
14.4.15.1 EZ Slave Transmit
Figure 14-26. EZI2C Slave Mode Write Operation Flow Chart
Begin
Default
Disable Fixed Function I2C block
EZ buffer empty?
No
Yes E
Select Slave mode
Select EZ mode
Enable TX FIFO
Enable Fixed Function I2C block
START detected
No
Receiving
(stretch)
one byte slave
Error
address
E
complete?
Wake up Yes
NACK
Address ACK'ed or NACK'ed?
ACK
Select transmit mode
No
Transmitting one byte
Error
data complete?
E
Yes
Byte ACK'ed or NACK'ed?
NACK
Begin
ACK
No
Data transfer
complete?
Yes
Begin
E
Report and handle error
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14.4.15.2 EZ Slave Receive
Figure 14-27. EZI2C Slave Mode Read Operation Flow Chart
Begin
Default
Disable Fixed Function I2C block
Select Slave mode
Select EZ mode
Enable RX FIFO
Enable Fixed Function I2C block
START detected
No
Receiving
(stretch)
one byte slave address
Error
E
complete?
Wake up Yes
NACK
Address ACK'ed or NACK'ed?
ACK
Select receive mode
No (stretch)
Receiving one byte EZ
address complete?
Yes
Address ACK'ed or NACK'ed?
NACK
ACK
Begin
EZ buffer full
Yes E
No
No
(stretch)
Receiving one byte data complete?
Error
E
Yes
Send ACK
No Data transfer complete?
Yes
Send NACK
Begin E
Report and handle error
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14.4.16 Multi-Master Mode Transfer Example
In multi-master mode, data can be transferred with the slave mode enabled or not enabled.
14.4.16.1 Multi-Master - Slave Not Enabled
Figure 14-28. Multi-Master, Slave Not Enabled Flow Chart
Begin
Default
Disable Fixed Function I2C block
Select Master mode
Enable TX FIFO
Enable Fixed Function I2C block
Yes Bus busy?
No Send START
signal
Yes Bus busy?
No
Transmission
of one byte
slave address
E
No
complete?
Error
(stretch)
Yes
Lost arbitration? Yes
No
Continue with data transfer as in single master
Begin
E
Report and handle error
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14.4.16.2 Multi-Master - Slave Enabled
Figure 14-29. Multi-Master, Slave Enabled Flow Chart
Begin
Default
Disable Fixed Function I2C block
Select Master and Slave mode
Enable TX FIFO
Enable Fixed Function I2C block
Yes Bus busy?
No Send START
signal
No
Transmission
(stretch)
of one byte
Error
slave address
E
complete?
Yes
Bus busy or
Yes
lost arbitration?
No
Continue with data transfer as in single master
Continue with address recognition as a slave
E
Report and handle error
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15. Timer, Counter, and PWM
CCG3 includes four blocks of the Timer, Counter, and Pulse Width Modulator (TCPWM) block. Each TCPWM in CCG3 implements the 16-bit timer, counter, pulse width modulator (PWM), and quadrature decoder functionality. The block can be used to measure the period and pulse width of an input signal (timer), find the number of times a particular event occurs (counter), generate PWM signals, or decode quadrature signals. This chapter explains the features, implementation, and operational modes of the TCPWM block.
15.1 Features
Four 16-bit timers, counters, or pulse width modulators (PWM) The TCPWM block supports the following operational modes:
Timer Counter Capture Quadrature decoding Pulse width modulation Pseudo-random PWM PWM with dead time Multiple counting modes up, down, and up/down Clock pre-scaling (division by 1, 2, 4, ... 64, 128) Double buffering of compare/capture and period values Supports interrupt on: Terminal Count (TC) The final value in the counter register is reached Capture/Compare (CC) The count is captured to the capture/compare register or the counter value equals the com-
pare value Synchronized counters The counters can reload, start, stop, and count at the same time Complementary line output for PWMs
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15.2 Block Diagram
System Interface
Figure 15-1. TCPWM Block Diagram
CPU and Memory Sub-System Bus Interface
Bus Interface Logic
Trigger_in
Need to find the bus width
Counter 0 Counter 1 Counter 2 Counter 3
Trigger Synchronization Configuration Registers
4
clock_counter_en[3:0]
18 underflow[5:0], overflow[5:0], cc[5:0]
5
Interrupts[3:0],
Interrupt
12
line_out[5:0], line_out_en[5:0],
The block has these interfaces:
Bus interface: Connects the block to the CPU subsystem.
Interrupts: Provides interrupt request signals from each counter, based on terminal count (TC) or CC conditions, and a combined interrupt signal generated by the logical OR of all six interrupt request signals.
System interface: Consists of control signals such as clock and reset from the system resources subsystem.
This TCPWM block can be configured by writing to the TCPWM registers. See TCPWM Registers on page 136 for more information on all registers required for this block.
15.2.1 Enabling and Disabling Counter in TCPWM Block
The counter can be enabled by setting the COUNTER_ENABLED field (bit 0) of the control register TCPWM_CTRL.
Note The counter must be configured before enabling it. If the counter is enabled after being configured, registers are updated with the new configuration values. Disabling the counter retains the values in the registers until it is enabled again (or reconfigured).
15.2.2 Clocking
The TCPWM receives the HFCLK through the system interface to synchronize all events in the block. The counter enable signal (counter_en), which is generated when the counter is enabled, gates the HFCLK to provide a counterspecific clock (counter_clock). Output triggers (explained later in this chapter) are also synchronized with the HFCLK.
Clock Pre-Scaling: counter_clock can be pre-scaled, with divider values of 1, 2, 4... 64, 128. This is done by modifying the GENERIC field of the counter control (TCPWM_CNT_CTRL) register, as shown in Table 15-1.
Table 15-1. Bit-Field Setting to Pre-Scale Counter Clock
GENERIC[10:8] 0 1 2 3 4 5 6 7
Description Divide by 1 Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 Divide by 128
Note Clock pre-scaling cannot be done in quadrature mode and pulse width modulation mode with dead time (PWMDT).
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15.2.3 Events Based on Trigger Inputs
These are the events triggered by hardware or software.
Count
Reload
Capture/switch
Start Stop
Hardware triggers can be level signal, rising edge, falling edge, or both edges.
Figure 15-2. TCPWM Trigger Selection and Event Detection
Trigger_in [13:0]
14
System bus clock
1 Trigger signal
0
4
trigger control register 0
Trigger Synchronisation
Edge Detector Circuit
rising edge
falling edge both
event
pass through 2 counter command register (SW generated)
trigger control register 1
Figure 15-2 shows the trigger selection and event detection in the TCPWM block. The trigger control register 0 (TCPWM_CNT_TR_CTRL0) selects one of the 16 trigger inputs as the event signal. Additionally, a constant '0' and '1' signals are available to be used as the event signal.
Any edge (rising, falling, or both) or level (high or low) can be selected for the occurrence of an event by configuring the trigger control register 1 (TCPWM_CNT_TR_CTRL1). This edge/level configuration can be selected for each trigger event separately. Alternatively, firmware can generate an event by writing to the counter command register (TCPWM_CMD), as shown in Figure 15-2.
The events derived from these triggers can have different definitions in different modes of the TCPWM block.
Reload: A reload event initializes and starts the counter.
In up counting mode, the count register (TCPWM_CNT_COUNTER) is initialized with `0'.
In down counting mode, the counter is initialized with the period value stored in the TCPWM_CNT_PERIOD register.
In up/down counting mode, the count register is initialized with `0'.
In quadrature mode, the reload event acts as a quadrature index event. An index/reload event indicates a completed rotation and can be used to synchronize quadrature decoding.
Start: A start event is used to start counting; it can be used after a stop event or after re-initialization of the counter register to any value by software. Note that the count register is not initialized on this event.
In quadrature mode, the start event acts as quadrature phase input phiB, which is explained in detail in Quadrature Decoder Mode on page 126.
Count: A count event causes the counter to increment or decrement, depending on its configuration.
In quadrature mode, the count event acts as quadrature phase input phiA.
Stop: A stop event stops the counter from incrementing or decrementing. A start event will start the counting again.
In the PWM modes, the stop event acts as a kill event. A kill event disables all the PWM output lines.
Capture: A capture event copies the counter register value to the capture register and capture register value to the buffer capture register. In the PWM modes, the capture event acts as a switch event. It switches the values of the capture/compare and period registers with their buffer counterparts. This feature can be used to modulate the pulse width and frequency.
Notes
All trigger inputs are synchronized to the HFCLK.
When more than one event occurs in the same counter clock period, one or more events may be missed. This can happen for high-frequency events (frequencies close to the counter frequency) and a timer configuration in which a pre-scaled (divided) counter clock is used.
15.2.4 Output Signals
The TCPWM block generates several output signals, as shown in Figure 15-3.
Figure 15-3. TCPWM Output Signals
Interrupt 0 Interrupt 1 Interrupt 2 Interrupt 3
TCPWM block
Interrupt
6
Underflow
6
Overflow
6
CC
6 6
line_out
line_compl_out
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15.2.4.1 Signals upon Trigger Conditions
Counter generates an internal overflow (OV) condition when counting up and the count register reaches the period value.
Counter generates an internal underflow (UN) condition when counting down and the count register reaches zero.
The capture/compare (CC) condition is generated by the TCPWM when the counter is running and one of the following conditions occur:
The counter value equals the compare value.
A capture event occurs - When a capture event occurs, the TCPWM_CNT_COUNTER register value is copied to the capture register and the capture register value is copied to the buffer capture register.
Note These signals, when they occur, remain at logic high for one cycle of the HFCLK. For reliable operation, the condition that causes this trigger should occur in a frequency less than a quarter of the HFCLK. For example, if the HFCLK is running at 24 MHz, the condition causing the trigger should occur at a frequency less than 6 MHz.
15.2.4.2 Interrupts
The TCPWM block provides a dedicated interrupt output signal from the counter. An interrupt can be generated for a TC condition or a CC condition. The exact definition of these conditions is mode-specific. All six interrupt output signals from the four TCPWMs are also OR'ed together to produce a single interrupt output signal.
Four registers are used for interrupt handling in this block, as shown in Table 15-2.
Table 15-2. Interrupt Register
Interrupt Registers
TCPWM_CNT_INTR (Interrupt request register)
Bits
Name
0 TC
1 CC_MATCH
TCPWM_CNT_INTR_SET (Interrupt set request register)
TCPWM_CNT_INTR_MASK (Interrupt mask register)
TCPWM_CNT_INTR_MASKED (Interrupt masked request register)
0 TC
1 CC_MATCH 0 TC 1 CC_MATCH 0 TC 1 CC_MATCH
Description
This bit is set to '1', when a terminal count is detected. Write '1' to clear this bit.
This bit is set to `1' when the counter value matches capture/compare register value. Write with '1' to clear this bit.
Write '1' to set the corresponding bit in the interrupt request register. When read, this register reflects the interrupt request register status.
Write '1' to set the corresponding bit in the interrupt request register. When read, this register reflects the interrupt request register status.
Mask bit for the corresponding TC bit in the interrupt request register.
Mask bit for the corresponding CC_MATCH bit in the interrupt request register.
Logical AND of the corresponding TC request and mask bits.
Logical AND of the corresponding CC_MATCH request and mask bits.
15.2.4.3 Outputs
The TCPWM has two outputs, line_out and line_compl_out (complementary of line_out). Note that the OV, UN, and CC conditions can be used to drive line_out and line_compl_out if needed, by configuring the TCPWM_CNT_TR_CTRL2 register (see Table 15-3).
Table 15-3. Configuring Output Line for OV, UN, and CC Conditions
Field
Bit
CC_MATCH_MODE Default Value = 3
1:0
OVERFLOW_MODE Default Value = 3
3:2
Value 0 1 2 3 0 1 2 3
Event Set line_out to '1 Clear line_out to '0 Invert line_out No change Set line_out to '1 Clear line_out to '0 Invert line_out No change
Description
Configures output line on a compare match (CC) event
Configures output line on a overflow (OV) event
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Table 15-3. Configuring Output Line for OV, UN, and CC Conditions
Field
Bit
UNDERFLOW_MODE Default Value = 3
5:4
Value 0 1 2 3
Event Set line_out to '1 Clear line_out to '0 Invert line_out No change
Description
Configures output line on a underflow (UN) event
15.2.5 Power Modes
The TCPWM block works in Active and Sleep modes. The TCPWM block is powered from VCCD. The configuration registers and other logic are powered in Deep-Sleep mode to keep the states of configuration registers. See Table 15-4.
Table 15-4. Power Modes in TCPWM Block
Power Mode Active Sleep
Deep-Sleep
Block Status This block is fully operational in this mode with clock running and power switched on. All counter clocks are on, but bus interface cannot be accessed. In this mode, the power to this block is still on but no bus clock is provided; hence, the logic is not functional. All the configuration registers will keep their state.
15.3 Modes of Operation
The counter block can function in six operational modes, as shown in Table 15-5. The MODE [26:24] field of the counter control register (TCPWM_CNTx_CTRL) configures the counter in the specific operational mode.
Table 15-5. Operational Mode Configuration
Timer
Mode
Capture
Quadrature Decoder PWM PWM-DT PWM-PR
MODE Field [26:24] 000
010
011 100 101 110
Description
Implements a timer or counter. The counter increments or decrements by '1' at every counter clock cycle in which a count event is detected.
Implements a timer or counter with capture input. The counter increments or decrements by '1' at every counter clock cycle in which a count event is detected. When a capture event occurs, the counter value copies into the capture register.
Implements a quadrature decoder, where the counter is decremented or incremented, based on two phase inputs according to the selected (X1, X2 or X4) encoding scheme.
Implements edge/center-aligned PWMs with an 8-bit clock prescaler and buffered compare/ period registers.
Implements edge/center-aligned PWMs with configurable 8-bit dead time (on both outputs) and buffered compare/period registers.
Implements a pseudo-random PWM using a 16-bit linear feedback shift register (LFSR).
The counter can be configured to count up, down, and up/down by setting the UP_DOWN_MODE[17:16] field in the TCPWM_CNTx_CTRL register, as shown in Table 15-6.
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Table 15-6. Counting Mode Configuration
Counting Modes
UP_DOWN_M ODE[17:16]
Description
UP Counting Mode
00
Increments the counter until the period value is reached. A Terminal Count (TC) condition is generated when counter reaches the period value.
DOWN Counting Mode
01
Decrements the counter from the period value until 0 is reached. A TC condition is generated when the counter reaches `0'.
UP/DOWN Counting Mode 0
10
Increments the counter until the period value is reached, and then decrements the counter until `0' is reached. A TC condition is generated only when `0' is reached.
UP/DOWN Counting Mode 1
11
Similar to up/down counting mode 0 but a TC condition is generated when the counter reaches `0' and when the counter value reaches the period value.
15.3.1 Timer Mode
The timer mode is commonly used to measure time of occurrence of an event or to measure the time difference between two events.
15.3.1.1 Block Diagram
Figure 15-4. Timer Mode Block Diagram
Reload Start Stop Count
PERIOD COUNTER COMPARE
UN
==
OV
CC
TC ==
counter_clock
BUFFER COMPARE
15.3.1.2 How It Works
The timer can be configured to count in up, down, and up/ down counting modes. It can also be configured to run in either continuous mode or one-shot mode.
The following explains the working of the timer:
The timer is an up, down, and up/down counter.
The current count value is stored in the count register (TCPWM_CNTx_COUNTER). Note It is not recommended to write values to this register while the counter is running.
The period value for the timer is stored in the period register.
The counter is re-initialized in different counting modes as follows:
In the up counting mode, after the count reaches the period value, the count register is automatically reloaded with 0.
In the down counting mode, after the count register reaches zero, the count register is reloaded with the value in the period register.
In the up/down counting modes, the count register value is not updated upon reaching the terminal values. Instead the direction of counting changes when the count value reaches 0 or the period value.
The CC condition is generated when the count register value equals the compare register value. Upon this condition, the compare register and buffer compare register switch their values if enabled by the AUTO_RELOAD_CC bit-field of the counter control (TCPWM_CNT_CTRL) register. This condition can be used to generate an interrupt request.
Figure 15-5 shows the timer operational mode of the counter in four different counting modes. The period register contains the maximum counter value.
In the up counting mode, a period value of A results in A+1 counter cycles (0 to A).
In the down counting mode, a period value of A results in A+1 counter cycles (A to 0).
In the two up/down counting modes (both modes 0 and 1 both), a period value of A results in 2*A counter cycles (0 to A and back to 0).
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Figure 15-5. Timing Diagram for Timer in Multiple Counting Modes
Timer, down counting mode
counter_clock
Period
0xFF
Counter
0xFF 0xFE 0xFD 0xFC
0x01
0xFF 0xFE 0xFD 0xFC
0x00
0xFF 0xFE
0x01 0x00
0xFF
0x03 0x02
OV
UN
TC
counter_clock
Timer, up counting mode
Period Counter
0x03 0x02 0x01 0x00
0xFF 0xFF 0xFE
0x03 0x02 0x01 0x00
0xFF 0xFE
0x02 0x01 0x00
0xFE
OV UN TC
counter_clock Period
Counter
OV UN TC
Timer, up/down counting mode 1
0x03 0x02 0x01 0x00
0xFF 0xFF 0xFE 0xFE
0xFD 0xFC
0x01
0x03 0x02 0x01
0x00
0xFF 0xFE
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Figure 15-6.
Timer, up/down counting mode 0
counter_clock
Period
Counter
OV UN TC
0x03 0x02 0x01 0x00
0xFF 0xFF 0xFE 0xFE
0xFD 0xFC
0x01
0x03 0x02 0x01
0x00
0xFF 0xFE
Note The OV and UN signals remain at logic high for one cycle of the HFCLCK, as explained in Signals upon Trigger Conditions on page 120. The figures in this chapter assumes that HFCLK and counter clock are the same.
15.3.1.3 Configuring Counter for Timer Mode
The steps to configure the counter for Timer mode of operation and the affected register bits are as follows.
1. Disable the counter by writing '0' to the COUNTER_ENABLED field of the TCPWM_CTRL register.
2. Select Timer mode by writing '000' to the MODE[26:24] field of the TCPWM_CNTx_CTRL register.
3. Set the required 16-bit period in the TCPWM_CNT_PERIOD register.
4. Set the 16-bit compare value in the TCPWM_CNT_CC register and the buffer compare value in the TCPWM_CNT_CC_BUFF register. Set AUTO_RELOAD_CC field of counter control register, if required to switch values at every CC condition.
5. Set clock pre-scaling by writing to the GENERIC[10:8] field of the counter control (TCPWM_CNT_CTRL) register, as shown in Table 15-1.
6. Set the direction of counting by writing to the UP_DOWN_MODE[17:16] field of the TCPWM_CNT_CTRL register, as shown in Table 15-6.
7. The timer can be configured to run either in continuous mode or one-shot mode by writing 0 or 1, respectively to the ONE_SHOT[18] field of the TCPWM_CNT_CTRL register.
8. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Reload, Start, Stop, Capture, and Count).
9. Set the TCPWM_CNT_TR_CTRL1 register to select the edge of the trigger that causes the event (Reload, Start, Stop, Capture, and Count).
10. If required, set the interrupt upon TC or CC condition, as shown in Interrupts on page 120.
11. Enable the counter by writing '1' to the COUNTER_ENABLED field of the TCPWM_CTRL regis-
ter. A start trigger must be provided through firmware (TCPWM_CMD register) to start the counter if the hardware start signal is not enabled.
15.3.2 Capture Mode
In the capture mode, the counter value can be captured at any time either through a firmware write to command register (TCPWM_CMD) or a capture trigger input. This mode is used for period and pulse width measurement.
15.3.2.1 Block Diagram
Figure 15-7. Capture Mode Block Diagram
Reload Start Stop Count Capture
PERIOD COUNTER CAPTURE
UN
==
OV
CC
TC
counter_clock
CAPTURE BUFFER
15.3.2.2 How it Works
The counter can be set to count in up, down, and up/down
counting
modes
by
configuring
the
UP_DOWN_MODE[17:16] bit-field of the counter control
register (TCPWM_CNT_CTRL).
Operation in capture mode occurs as follows:
During a capture event, generated either by hardware or software, the current count register value is copied to the capture register (TCPWM_CNT_CC) and the capture register value is copied to the buffer capture register (TCPWM_CNT_CC_BUFF).
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A pulse on the CC output signal is generated when the counter value is copied to the capture register. This condition can also be used to generate an interrupt request.
Figure 15-8 illustrates the capture behavior in the up counting mode. Figure 15-8. Timing Diagram of Counter in Capture Mode, Up Counting Mode
Capture, up counting mode
counter_clock Period Capture trigger
0xFF
0xFE
0xFE
Counter
0x03 0x02 0x01 0x00
capture capture buffer
0x02
OV UN
TC
CC
In the figure, observe that: The period register contains the maximum count value. Internal overflow (OV) and TC conditions are generated
when the counter reaches the period value. A capture event is only possible at the edges or through
software. Use trigger control register 1 to configure the edge detection. Multiple capture events in a single clock cycle are handled as: Even number of capture events - no event is
observed Odd number of capture events - single event is
observed
This happens when the capture signal frequency is greater than the counter_clock frequency.
15.3.2.3 Configuring Counter for Capture Mode
The steps to configure the counter for Capture mode operation and the affected register bits are as follows. 1. Disable the counter by writing '0' to the
COUNTER_ENABLED field of the TCPWM_CTRL register. 2. Select Capture mode by writing '010' to the MODE[26:24] field of the TCPWM_CNT_CTRL register.
0x03 0x02 0x01 0x00
0xFE 0x02
0x02 0x01 0x00
0x03 0xFE
3. Set the required 16-bit period in the TCPWM_CNT_PERIOD register.
4. Set clock pre-scaling by writing to the GENERIC[10:8] field of the TCPWM_CNT_CTRL register, as shown in Table 15-1.
5. Set the direction of counting by writing to the UP_DOWN_MODE[17:16] field of the TCPWM_CNT_CTRL register, as shown in Table 15-6.
6. Counter can be configured to run either in continuous mode or one-shot mode by writing 0 or 1, respectively to the ONE_SHOT[18] field of the TCPWM_CNT_CTRL register.
7. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Reload, Start, Stop, Capture, and Count).
8. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (Reload, Start, Stop, Capture, and Count).
9. If required, set the interrupt upon TC or CC condition, as shown in Interrupts on page 120.
10. Enable the counter by writing '1' to the COUNTER_ENABLED field of the TCPWM_CTRL register. A start trigger must be provided through firmware (TCPWM_CMD register) to start the counter if the hardware start signal is not enabled.
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15.3.3 Quadrature Decoder Mode
Quadrature decoders are used to determine speed and position of a rotary device (such as servo motors, volume control wheels, and PC mice). The quadrature encoder signals are used as phiA and phiB inputs to the decoder.
15.3.3.1 Block Diagram
Figure 15-9. Quadrature Mode Block Diagram
index
PERIOD
0x0000 0xFFFF
phiA Stop phiB
== CC
COUNTER TC
CAPTURE
counter_clock
BUFFER CAPTURE
15.3.3.2 How It Works
Quadrature decoding only runs on counter_clock. It can operate in three sub-modes: X1, X2, and X4. These encoding modes can be controlled by the QUADRATURE_MODE[21:20] field of the counter control register (TCPWM_CNT_CTRL). This mode uses double buffered capture registers.
The Quadrature mode operation occurs as follows:
Quadrature phases phiA and phiB: Counting direction is determined by the phase relationship between phiA and phiB. These phases are connected to the count and the start trigger inputs, respectively as hardware input to the decoder.
Quadrature index signal: This is connected to the reload signal as a hardware input. This event generates a TC condition, as shown in Figure 15-10.
On TC, the counter is set to 0x0000 (in the up counting mode) or to the period value (in the down counting mode).
Note The down counting mode is recommended to be used with a period value of 0x8000 (the mid-point value).
A pulse on CC output signal is generated when the count register value reaches 0x0000 or 0xFFFF. On a CC condition, the count register is set to the period value (0x8000 in this case).
On TC or CC condition:
Count register value is copied to the capture register
Capture register value is copied to the buffer capture register
This condition can be used to generate an interrupt request
The value in the capture register can be used to determine which condition caused the event and whether:
A counter underflow occurred (value 0)
A counter overflow occurred (value 0xFFFF)
An index/TC event occurred (value is not equal to either 0 or 0xFFFF)
The DOWN bit field of counter status (TCPWM_CNTx_STATUS) register can be read to determine the current counting direction. Value '0' indicates a previous increment operation and value '1' indicates previous decrement operation. Figure 15-10 illustrates quadrature behavior in the X1 encoding mode.
A positive edge on phiA increments the counter when phiB is '0' and decrements the counter when phiB is '1'.
The count register is initialized with the period value on an index/reload event.
Terminal count is generated when the counter is initialized by index event. This event can be used to generate an interrupt.
When the count register reaches 0xFFFF (the maximum count register value), the count register value is copied to the capture register and the count register is initialized with period value (0x8000).
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Figure 15-10. Timing Diagram for Quadrature Mode, X1 Encoding
Quadrature, X1 encoding
counter_clock
index/reload event
phiA
phiB
Period
counter
0x8000
capture
buffer capture
0x8001
0x8000 0x8002
Y X
0x8003
0xFFFF
0x8000
0x7FFF
0xFFFF
Y
TC CC
The quadrature phases are detected on the counter_clock. Within a single counter period, the phases should not change value more than once.
The X2 and X4 quadrature encoding modes count twice and four times as fast as the X1 encoding mode.
Figure 15-11 illustrates the quadrature mode behavior in the X2 and X4 encoding modes.
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Figure 15-11. Timing Diagram for Quadrature Mode, X2 and X4 Encoding
Quadrature, X2 encoding counter_clock
index/reload event
phiA phiB
Period
4
counter TC
counter_clock index/reload
event phiA phiB Period
4
5
6
7
8
Quadrature, X4 encoding
4
7
6
counter TC
4 5 6 7 8 9 10 11
12
11 10 9 8
15.3.3.3 Configuring Counter for Quadrature Mode
The steps to configure the counter for quadrature mode of operation and the affected register bits are as follows.
1. Disable the counter by writing '0' to the COUNTER_ENABLED field of the TCPWM_CTRL register.
2. Select Quadrature mode by writing '011' to the MODE[26:24] field of the TCPWM_CNT_CTRL register.
3. Set the required 16-bit period in the TCPWM_CNT_PERIOD register.
4. Set the required encoding mode by writing to the QUADRATURE_MODE[21:20] field of the TCPWM_CNT_CTRL register.
5. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Index and Stop).
6. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (Index and Stop).
7. If required, set the interrupt upon TC or CC condition, as shown in Interrupts on page 120.
8. Enable the counter by writing '1' to the COUNTER_ENABLED field of the TCPWM_CTRL register.
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15.3.4 Pulse Width Modulation Mode
The PWM mode is also called the Digital Comparator mode. The comparison output is a PWM signal whose period depends on the period register value and duty cycle depends on the compare and period register values. PWM period = (period value/counter clock frequency) in left- and right-aligned modes PWM period = (2 × (period value/counter clock frequency)) in center-aligned mode Duty cycle = (compare value/period value) in left- and right-aligned modes Duty cycle = ((period value-compare value)/period value) in center-aligned mode
15.3.4.1 Block Diagram
Figure 15-12. PWM Mode Block Diagram
reload start stop switch count
BUFFER PERIOD PERIOD
COUNTER COMPARE
UN OV CC TC ==
line_out
PWM
line_out_compl
counter_clock
BUFFER COMPARE
15.3.4.2 How It Works
The PWM mode can output left, right, center, or asymmetrically aligned PWM signals. The desired output alignment is achieved by using the counter's up, down, and up/down counting modes selected using UP_DOWN_MODE [17:16] bits in the TCPWM_CNT_CTRL register, as shown in Table 15-6.
This CC signal along with OV and UN signals control the PWM output line. The signals can toggle the output line or set it to a logic '0' or '1' by configuring the TCPWM_CNT_TR_CTRL2 register. By configuring how the signals impact the output line, the desired PWM output alignment can be obtained.
The recommended way to modify the duty cycle is:
The buffer period register and buffer compare register are updated with new values.
On TC, the period and compare registers are automatically updated with the buffer period and buffer compare registers when there is an active switch event. The AUTO_RELOAD_CC and AUTO_RELOAD_PERIOD fields of the counter control register are set to `1'. When a switch event is detected, it is remembered until the next TC event. Pass through signal (selected during event detection setting) cannot trigger a switch event.
Updates to the buffer period register and buffer compare register should be completed before the next TC with an active switch event; otherwise, switching does not reflect the register update, as shown in Figure 15-14.
In the center-aligned mode, the output line is set to '0' at Terminal Count and toggled at the CC condition.
At the reload event, the count register is initialized and starts counting in the appropriate mode. At every count, the count register value is compared with compare register value to generate the CC signal on match.
Figure 15-13 illustrates center-aligned PWM with buffered period and compare registers (up/down counting mode 0).
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counter_clock
Figure 15-13. Timing Diagram for Center Aligned PWM
PWM center aligned buffered
SW update of buffers reload event
new period value B, new compare value N
period buffer
A
B
A
period A
B
B
compare buffer
M
N
M
compare
M
N
N
A
Counter M
Switch at TC condition B
N
0
TC
CC line_out
Figure 15-14 illustrates center-aligned PWM with software generated switch events: Software generates a switch event only after both the period buffer and compare buffer registers are updated. Because the updates of the second PWM pulse come late (after the terminal count), the first PWM pulse is repeated. Note that the switch event is automatically cleared by hardware at TC after the event takes effect.
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Figure 15-14. Timing Diagram for Center Aligned PWM (software switch event)
PWM, center aligned, buffered (software switch event) counter_clock
Switch event
reload event
period buffer
A
B
A
period
A
B
compare buffer
M
N
M
compare
M
A
Counter M
N
Switch at TC condition B N
0
TC
CC line_out
15.3.4.3 Other Configurations
For asymmetric PWM, the up/down counting mode 1 should be used. This causes a TC when the counter reaches either `0' or the period value. To create an asymmetric PWM, the compare register is changed at every TC (when the counter reaches either `0' or the period value), whereas the period register is only changed at every other TC (only when the counter reaches `0').
For left-aligned PWM, use the up counting mode; configure the OV condition to set output line to '1' and CC condition to reset the output line to '0'. See Table 15-3.
For right-aligned PWM, use the down counting mode; configure UN condition to reset output line to '0' and CC condition to set the output line to '1'. See Table 15-3.
15.3.4.4 Kill Feature
Kill feature gives the ability to disable both output lines immediately. This event can be programmed to stop the counter by modifying the PWM_STOP_ON_KILL and PWM_SYNC_KILL fields of the counter control register, as shown in Table 15-7.
Table 15-7. Field Setting for Stop on Kill Feature
PWM_STOP_ON_KI LL Field
Comments
0
The kill trigger temporarily blocks the PWM output line but the counter is still running.
1
The kill trigger temporarily blocks the PWM output line and the counter is also stopped.
A kill event can be programmed to be asynchronous or synchronous, as shown in Table 15-8.
Table 15-8. Field Setting for Synchronous/Asynchronous Kill
PWM_SYNC_KILL Field
Comments
An asynchronous kill event lasts as long as
0
it is present. This event requires pass
through mode.
A synchronous kill event disables the out-
1
put lines until the next TC event. This
event requires rising edge mode.
In the synchronous kill, PWM cannot be started before the next TC. To restart the PWM immediately after kill input is removed, kill event should be asynchronous (see
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Table 15-8). The generated stop event disables both output lines. In this case, the reload event can use the same trigger input signal but should be used in falling edge detection mode.
15.3.4.5 Configuring Counter for PWM Mode
The steps to configure the counter for the PWM mode of operation and the affected register bits are as follows.
1. Disable the counter by writing '0' to the COUNTER_ENABLED field of the TCPWM_CTRL register.
2. Select PWM mode by writing '100' to the MODE[26:24] field of the TCPWM_CNT_CTRL register.
3. Set clock pre-scaling by writing to the GENERIC[10:8] field of the TCPWM_CNT_CTRL register, as shown in Table 15-1.
4. Set the required 16-bit period in the TCPWM_CNT_PERIOD register and the buffer period value in the TCPWM_CNT_PERIOD_BUFF register to switch values, if required.
5. Set the 16-bit compare value in the TCPWM_CNT_CC register and the buffer compare value in the TCPWM_CNT_CC_BUFF register to switch values, if required.
6. Set the direction of counting by writing to the UP_DOWN_MODE[17:16] field of the TCPWM_CNT_CTRL register to configure left-aligned, right-aligned, or center-aligned PWM, as shown in Table 15-6.
7. Set the PWM_STOP_ON_KILL and PWM_SYNC_KILL fields of the TCPWM_CNT_CTRL register as required.
8. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Reload, Start, Kill, Switch, and Count).
9. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (Reload, Start, Kill, Switch, and Count).
10. line_out and line _out_compl can be controlled by the TCPWM_CNT_TR_CTRL2 register to set, reset, or invert upon CC, OV, and UN conditions.
11. If required, set the interrupt upon TC or CC condition, as shown in Interrupts on page 120.
12. Enable the counter by writing '1' to the COUNTER_ENABLED field of the TCPWM_CTRL register. A start trigger must be provided through firmware (TCPWM_CMD register) to start the counter if the hardware start signal is not enabled.
15.3.5 Pulse Width Modulation with Dead Time Mode
Dead time is used to delay the transitions of both `line_out' and `line_out_compl' signals. It separates the transition edges of these two signals by a specified time interval. Two complementary output lines 'dt_line' and 'dt_line_compl' are derived from these two lines. During the dead band period, both compare output and complement compare output are at logic `0' for a fixed period. The dead band feature allows the generation of two non-overlapping PWM pulses. A maximum dead time of 255 clocks can be generated using this feature.
15.3.5.1 Block Diagram
Figure 15-15. PWM-DT Mode Block Diagram
BUFFER PERIOD
Reload Start Stop Switch Count
PERIOD COUNTER COMPARE
CC
TC ==
PWM
Dead Time
dt_line dt_line_compl
counter_clock
BUFFER COMPARE
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15.3.5.2 How It Works
The PWM operation with Dead Time mode occurs as follows:
On the rising edge of the PWM line_out, depending upon UN, OV, and CC conditions, the dead time block sets the dt_line and dt_line_compl to '0'.
The dead band period is loaded and counted for the period configured in the register.
When the dead band period is complete, dt_line is set to '1'.
On the falling edge of the PWM line_out depending upon UN, OV, and CC conditions, the dead time block sets the dt_line and dt_line_compl to '0'.
The dead band period is loaded and counted for the period configured in the register.
When the dead band period has completed, dt_line_compl_is set to '1'.
A dead band period of zero has no effect on the dt_line and is the same as line_out.
When the duration of the dead time equals or exceeds the width of a pulse, the pulse is removed.
This mode follows PWM mode and supports the following features available with that mode:
Various output alignment modes
Two complementary output lines, dt_line and dt_line_compl, derived from PWM "line_out" and "line _out_compl", respectively
Stop/kill event with synchronous and asynchronous modes
Conditional switch event for compare and buffer compare registers and period and buffer period registers
This mode does not support clock pre-scaling.
Figure 15-16 illustrates how the complementary output lines "dt_line" and "dt_line_compl" are generated from the PWM output line, "line_out".
Figure 15-16. Timing Diagram for PWM, with and without Dead Time
PWM, Deadtime insertion
line_out
dt_line dt_line_compl
Dead time duration : 0
dt_line dt_line_compl
Deadtime duration :
15.3.5.3 Configuring Counter for PWM with Dead Time Mode
The steps to configure the counter for PWM with Dead Time mode of operation and the affected register bits are as follows:
1. Disable the counter by writing '0' to the COUNTER_ENABLED field of the TCPWM_CTRL register.
2. Select PWM with Dead Time mode by writing '101' to the MODE[26:24] field of the TCPWM_CNT_CTRL register.
3. Set the required dead time by writing to the GENERIC[15:8] field of the TCPWM_CNT_CTRL register, as shown in Table 15-1.
4. Set the required 16-bit period in the TCPWM_CNT_PERIOD register and the buffer period
value in the TCPWM_CNT_PERIOD_BUFF register to switch values, if required.
5. Set the 16-bit compare value in the TCPWM_CNT_CC register and the buffer compare value in the TCPWM_CNT_CC_BUFF register to switch values, if required.
6. Set the direction of counting by writing to the UP_DOWN_MODE[17:16] field of the TCPWM_CNT_CTRL register to configure left-aligned, right-aligned, or center-aligned PWM, as shown in Table 15-6.
7. Set the PWM_STOP_ON_KILL and PWM_SYNC_KILL fields of the TCPWM_CNT_CTRL register as required, as shown in the Pulse Width Modulation Mode on page 129.
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8. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Reload, Start, Kill, Switch, and Count).
9. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (Reload, Start, Kill, Switch, and Count).
10. dt_line and dt_line_compl can be controlled by the TCPWM_CNT_TR_CTRL2 register to set, reset, or invert upon CC, OV, and UN conditions.
11. If required, set the interrupt upon TC or CC condition, as shown in Interrupts on page 120.
12. Enable the counter by writing '1' to the COUNTER_ENABLED field of the TCPWM_CTRL register. A start trigger must be provided through firmware (TCPWM_CMD register) to start the counter if hardware start signal is not enabled.
15.3.6 Pulse Width Modulation PseudoRandom Mode
This mode uses the linear feedback shift register (LFSR). LFSR is a shift register whose input bit is a linear function of its previous state.
15.3.6.1 Block Diagram
Figure 15-17. PWM-PR Mode Block Diagram
BUFFER PERIOD
reload start stop switch
PERIOD LFSR / COUNTER
COMPARE
CC TC ==
line_out
<
counter_clock
BUFFER COMPARE
15.3.6.2 How It Works
The counter register is used to implement LFSR with the polynomial: x16+x14+x13+x11+1, as shown in Figure 15-18. It generates all the numbers in the range [1, 0xFFFF] in a pseudo-random sequence. Note that the counter register should be initialized with a non-zero value.
Figure 15-18. Pseudo-Random Sequence Generation using Counter Register
1 0 1 0 1 1 0 0 1 1 1 0 00 0 1
0
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The following steps describe the process:
The PWM output line `line_out' is driven with '1' when the lower 15-bit value of the counter register is smaller than the value in the compare register (when counter[14:0] < compare[15:0]). A compare value of `0x8000' or higher always results in a '1' on the PWM output line. A compare value of `0' always results in a '0' on the PWM output line.
A reload event behaves similar to a start event; however, it does not initialize the counter.
Terminal count is generated when the counter value equals the period value. LFSR generates a predictable pattern of counter values for a certain initial value. This predictability can be used to calculate the counter value after a certain amount of LFSR iterations `n'. This calculated counter value can be used as a period value and the TC is generated after `n' iterations.
At TC, a switch/capture event conditionally switches the compare and period register pairs (based on the AUTO_RELOAD_CC and AUTO_RELOAD_PERIOD fields of the counter control register).
A kill event can be programmed to stop the counter as described in previous sections.
One shot mode can be configured by setting the ONE_SHOT field of the counter control register. At terminal count, the counter is stopped by hardware.
In this mode, underflow, overflow, and trigger condition events do not occur.
CC condition occurs when the counter is running and its value equals compare value. Figure 15-19 illustrates pseudo-random noise behavior.
A compare value of 0x4000 results in 50 percent duty cycle (only the lower 15 bits of the 16- bit counter are used to compare with the compare register value).
Figure 15-19. Timing Diagram for Pseudo-Random PWM
Pseudo Random PWM
counter_clock
reload event compare
0x4000
period counter
0xACE1
0x5670
0xACE1
0xAB38
0x559C
0x2ACE
0x1567
line_out
A capture/switch input signal may switch the values between the compare and compare buffer registers and the period and period buffer registers. This functionality can be used to modulate between two different compare values using a trigger input signal to control the modulation.
Note Capture/switch input signal can only be triggered by an edge (rising, falling, or both). This input signal is remembered until the next terminal count.
15.3.6.3 Configuring Counter for PseudoRandom PWM Mode
The steps to configure the counter for pseudo-random PWM mode of operation and the affected register bits are as follows.
1. Disable the counter by writing '0' to the COUNTER_ENABLED field of the TCPWM_CTRL register.
2. Select pseudo-random PWM mode by writing '110' to the MODE[26:24] field of the TCPWM_CNT_CTRL register.
3. Set the required period (16 bit) in the TCPWM_CNT_PERIOD register and buffer period value
in the TCPWM_CNT_PERIOD_BUFF register to switch values, if required.
4. Set the 16-bit compare value in the TCPWM_CNT_CC register and the buffer compare value in the TCPWM_CNT_CC_BUFF register to switch values.
5. Set the PWM_STOP_ON_KILL and PWM_SYNC_KILL fields of the TCPWM_CNT_CTRL register as required.
6. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Reload, Start, Kill, and Switch).
7. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (Reload, Start, Kill, and Switch).
8. line_out and line_out_compl can be controlled by the TCPWM_CNT_TR_CTRL2 register to set, reset, or invert upon CC, OV, and UN conditions.
9. If required, set the interrupt upon TC or CC condition, as shown in Interrupts on page 120.
10. Enable the counter by writing '1' to the COUNTER_ENABLED field of the TCPWM_CTRL register.
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15.4 TCPWM Registers
Table 15-9. List of TCPWM Registers
Register
TCPWM_CTRL TCPWM_CMD TCPWM_INTR_CAUSE
Comment
TCPWM control register TCPWM command register TCPWM counter interrupt cause register
TCPWM_CNTx_CTRL
Counter control register
TCPWM_CNTx_STATUS TCPWM_CNTx_COUNTER TCPWM_CNTx_CC
Counter status register Count register Counter compare/capture register
TCPWM_CNTx_CC_BUFF
Counter buffered compare/capture register
TCPWM_CNTx_PERIOD
Counter period register
TCPWM_CNTx_PERIOD_BUFF Counter buffered period register
TCPWM_CNTx_TR_CTRL0
Counter trigger control register 0
TCPWM_CNTx_TR_CTRL1
Counter trigger control register 1
TCPWM_CNTx_TR_CTRL2
Counter trigger control register 2
TCPWM_CNTx_INTR
Interrupt request register
TCPWM_CNTx_INTR_SET
Interrupt set request register
TCPWM_CNTx_INTR_MASK
Interrupt mask register
TCPWM_CNTx_INTR_MASKED Interrupt masked request register
Features
Enables the counter block
Generates software events
Determines the source of the combined interrupt signal
Configures counter mode, encoding modes, one shot mode, switching, kill feature, dead time, clock pre-scaling, and counting direction
Reads the direction of counting, dead time duration, and clock pre-scaling; checks if counter is running
Contains the 16-bit counter value
Captures the counter value or compares the value with the counter value
Buffer register for counter CC register; switches compare value
Contains upper value of the counter
Buffer register for counter period register; switches period value
Selects trigger for specific counter events
Determines edge detection for specific counter input signals
Controls counter output lines upon CC, OV, and UN conditions
Sets the register bit when TC or CC condition is detected
Sets the corresponding bits in the interrupt request register
Mask for interrupt request register
Bitwise AND of interrupt request and mask registers
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16. Cryptography Block
The Cryptography block in CCG3 provides up to five cryptographic functionalities including: Advanced Encryption Standard (AES) functionality: The AES component can be used to encrypt/decrypt data blocks of
128-bit length and it supports programmable key length (128/192/256-bit key). Secure Hash Algorithm (SHA) functionality: This component can be used to produce a fixed length hash (also called
"message digest") from a variable length input data (called "message"). Cyclic Redundancy Check (CRC) functionality: This component performs a cyclic redundancy check with a programmable
polynomial of up to 32-bits. Pseudo Random Number Generator (PR): This component generates pseudo random numbers in a fixed range. This
generator is based on 3 Linear Feedback Shift Registers (LFSRs). True Random Number Generator (TR): This component generates true random numbers using up 6 sets of to ring oscilla-
tors.
16.1 Features
AES functionality supports both forward block cipher and inverse block cipher Programmable key length (128/192/256-bit key) for AES SHA functionality supports 160-bit hash or 224-bit hash or 256-bit hash Pseudo random (PR) number generator True random number generator (TR) Polynomial for Cyclic Redundancy Check (CRC) functionality is programmable up to 32-bits 2-KB SRAM memory buffer to store operands and results of all operations Trigger interface to support HW initiation of an operation
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16.2 Block Diagram
Figure 16-1. Crypto Block Diagram
AHB-Lite bus infrastructure AHB-Lite I/F
Trigger I /F: tr_in, tr_out
interrupt
32-bit accesses only
AHB-Lite slave interface
8-bit, 16-bit, 32-bit accesses
MMIO control & status registers
Memory buffer (SRAM)
(2KB)
Power: act_isolate_n, act_power_en_n,
act_bleed , dpslp_power_up_n,
dpslp_bleed
PR
Pseudo random numbers in the range [0, 2^32-1]
TR
True random numbers from ring
oscillators
AES
AES-128/192/256 Cipher and inverse
cipher
SHA
SHA1, SHA2-224, SHA2- 2 56
CRC
Programmable polynomial
(up to 32 bits)
protection _mode[]
Clock/reset I/F: clk_sys, rst_sys_act_n, rst_sys_dpslp_n
The Cryptography block functionality includes:
AES functionality (block cipher), per FIPS 197 standard
Forward block cipher (plaintext to ciphertext) with 128/192/256-bit key
Inverse block cipher (ciphertext to plaintext) with 128/192/256-bit key
SHA functionality (hash), per FIPS 180-4 standard
SHA1, 160-bit hash
SHA2, 224-bit hash
SHA2, 256-bit hash (not supported: 384-bit and 512bit hash)
Cyclic Redundancy Check (CRC) functionality
Programmable polynomial of up to 32-bits
Pseudo Random (PR) number generator
True Random (TR) number generator
Note: Only one of the functions can be used at any given time.
This block is connected to the bus infrastructure as an AHBLite slave: it can receive AHB-Lite transfers (from the CPU or another bus master) but it cannot initiate AHB-Lite transfers.
16.2.1 Block Application Overview
The AES component can be used to encrypt plain text data or decrypt cipher data.
The SHA component can be used to generate the signature (or message digest) for the data block to ensure integrity and authentication of the data.
The PR component will be used to obtain pseudo random values, which can be used as initialization vector (IV) for AES encryption and for other purposes.
The CRC is an optional component provided and it can be used to generate CRC of the given data, if the application requires it.
This block has the following interfaces:
An AHB-Lite slave interface connects the block to the AHB-Lite infrastructure. This interface supports 8/16/32bit AHB-Lite transfers. MMIO register accesses are 32bit accesses only (8/16-bit accesses to MMIO registers results in an AHB-Lite bus error). Memory buffer access can be 8/16/32-bit accesses.
Protection mode "protection_mode[]" signals (from the CPU subsystem) are provided to restrict the debug access port (DAP) accesses to the memory buffer.
A trigger interface allows a block operation to be started by an external trigger ("tr_in"). When the operation completes, the block generates a trigger ("tr_out").
A single interrupt signal "interrupt" is used to signal the completion of an operation.
A clock and reset signal interface connects to the System Resources subsystem (SRSS). The block operates of a gated version of "clk_sys" and uses both Active ("rst_sys_act_n") and DeepSleep ("rst_sys_dpslp_n") reset signals.
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16.2.2 Sub Block Descriptions
16.2.2.1 Pseudo random number generator
The pseudo random number generator component generates pseudo random numbers in a fixed range [0, PR_CTL.MAX[31:0]]. The generator is based on three Fibonacci based Linear Feedback Shift Registers (LFSRs). The following three polynomials are implemented: 32-bit polynomial: x32 + x30 + x26 + x25 + 1 31-bit polynomial: x31 + x28 + 1 29-bit polynomial: x29 + x27 + 1 The following figures illustrate the LFSR functionality.
Figure 16-2. Fixed Fibonacci based LFSRs
Software initializes the LFSRs need to be initialized with non-zero seed values The PR_LFSR_CTL0, PR_LFSR_CTL1, and PR_LFSR_CTL2 MMIO registers are provided for this purpose. At any time, the state of these MMIO registers can be read to retrieve the state of the LFSRs. The 32-bit LFSR generates a repeating bit sequence of 232 - 1 bits, the 31-bit LFSR generates a repeating bit sequence of 231 - 1, and the 29-bit LFSR generates a repeating bit sequence of 229 - 1.
The final pseudo random bit is the XOR of the three bits that are generated by the individual LFSRs.
Figure 16-3. XOR Reduction Logic
LFSR32 output LFSR31 output LFSR29 output
pseudo random bit
As the numbers 232-1, 231-1, and 229-1 are relatively prime, the XOR output is a repeating bit sequence of roughly 232+31+29.
A pseudo random number of n bits "pr[n-1:0]" uses 'n' pseudo random bits from the pseudo random number generator. The pseudo random number generator component uses a total of 33 pseudo random bits to generate a result in the range [0, PR_CTL.MAX[31:0]].
To generate a pseudo random number result, the following calculation is performed.
MAX_PLUS1[32:0] = PR_CTL.MAX[31:0] + 1;
product[63:0] = MAX_PLUS1[32:0] * pr[32:1] + PR_CTL.MAX[31:0] * pr[0];
result = product[63:32];
The result is provided through the MMIO register PR_RESULT.
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16.2.2.2 True Random Number Generator
The true random number generator component (TRNG) generates true random numbers. The bit size of these generated numbers is programmable in the range [0, 32].
The TRNG relies on up to six ring oscillators to provide physical noise sources. A ring oscillator consists of a series of inverters connected in a feedback loop to form a ring.
Post-processing produces bit samples that are considered true random bit samples. The true random bit samples are shifted into a register, to provide random values of up to 32 bits. The following figure gives an overview of the TRNG component.
START_RO11
START_RO15
START_GARO15 START_GARO31 POLYNOMIAL[30:0]
START_FIRO15 START_FIRO31 POLYNOMIAL[30:0]
Figure 16-4. TRNG Overview
SAMPLE_CLOCK_DIV[]
oscillating signal
digitized analog samples (DAS)
RO11
Sampler
Post-processing INIT_DELAY[] RED_CLOCK_DIV[]
RO15 GARO15
Sampler Sampler
von Neumann corrector
GARO31 FIRO15
Sampler Sampler
VON _NEUMANN_CORR
FIRO31
Sampler
true 0
random bit
TR_RESULT.DATA[31:0] 31
shift register
TR_RESULT.DATA_BIT_SIZE[5:0]
TR_CTL.DATA_BIT_SIZE[5:0]
B
A
A >= B
INTR.TR_INITIALIZED
INTR.TR_DATA_AVAILABLE
The following are the ring oscillators on which the TRNG relies: RO11: A fixed ring oscillator consisting of 11 inverters RO15: A fixed ring oscillator consisting of 15 inverters GARO15: A fixed Galois based ring oscillator of 15 inverters GARO31: A flexible Galois based ring oscillator of up to 31 inverters. A programmable polynomial of up to order 31 pro-
vides the flexibility in the oscillator feedback FIRO15: A fixed Galois based ring oscillator of 15 inverters FIRO31: A flexible Galois based ring oscillator of up to 31 inverters. A programmable polynomial of up to order 31 pro-
vides the flexibility in the oscillator feedback
Each ring oscillator can be started or stopped. When stopped, the ring is "broken" to prevent switching. The following figures illustrate the schematics of the fixed ring oscillators.
Figure 16-5. Fixed Ring Oscillators: RO11, RO15, GARO15, and FIRO15 RO11: oscillator with 11 inverters
START
10 9 8 7 6 5 4 3 2 1 0 output
START
RO15: oscillator with 15 inverters
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 output
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START
GARO15: fixed polynomia:l x15 + x14 + x7 + x6 + x5 + x4 + x2 + 1
output
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
The START signals originate from a MMIO register field. The flexible Galois and Fibonacci based ring oscillators rely on programmable polynomials to specify the oscillator feedback. This allows for rings of 1, 3, 5, ..., 31 inverters (an odd number is required to generate an oscillating signal). The following figure gives an overview of the Galois based ring oscillator.
Figure 16-6. Flexible Galois Ring Oscillator GARO31
POLYNOMIAL[0]
POLYNOMIAL[1]
`0' POLYNOMIAL[2]
`0' POLYNOMIAL[3]
`0' POLYNOMIAL[4]
`0' POLYNOMIAL[5]
`0' POLYNOMIAL[6]
`0'
POLYNOMIAL[7] `0'
POLYNOMIAL[8] `0'
POLYNOMIAL[9] `0'
POLYNOMIAL[10] `0'
POLYNOMIAL[22]
POLYNOMIAL[23]
POLYNOMIAL[24]
POLYNOMIAL[25]
`0' POLYNOMIAL[26]
`0' POLYNOMIAL[27]
`0' POLYNOMIAL[28]
`0' POLYNOMIAL[29]
`0' POLYNOMIAL[30]
`0'
30 29 28 27 26 25 24 23 22 21 output
10
9
8
7
6
5
4
3
2
1
0
When the ring oscillator is stopped, the polynomial is forced to "0" and the ring is broken as illustrated by the following figure. Figure 16-7. Flexible GARO31 when not Running
`0'
`0'
`0'
`0'
`0'
30 29 28 27 26 25 24 23 22 21 20 output
Constant ` 1'
30
29 28
27 26 25
24 23
22 21
20
output
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
`0'
The programmable polynomial specifies the oscillator feedback. The following figures illustrate two examples.
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Figure 16-8. Flexible GARO31 Examples
7-bit polynomial: x7 + x6 + 1 (POLYNOMIAL = 0x0000:0041 << 24)
Constant ` 0'
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 4 2 1 0 `0'
output
31 bit polynomial: x31 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 (POLYNOMIAL = 0x04c1:1db7)
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
32 1
0
output
The following figure gives an overview of the Fibonacci based ring oscillator.
Figure 16-9. Flexible Fibonacci Ring Oscillator FIRO31
30 29 28 27 26 25 24 23 22 21
10
9
8
7
6
5
4
3
2
1
0
output
POLYNOMIAL[0]
POLYNOMIAL[1]
`0' POLYNOMIAL[2]
`0' POLYNOMIAL[3]
`0' POLYNOMIAL[4]
`0' POLYNOMIAL[5]
`0' POLYNOMIAL[6]
`0' POLYNOMIAL[7]
`0' POLYNOMIAL[8]
`0' POLYNOMIAL[9]
`0'
POLYNOMIAL[10]
POLYNOMIAL[21]
POLYNOMIAL[22]
POLYNOMIAL[23]
POLYNOMIAL[24]
POLYNOMIAL[25]
POLYNOMIAL[26]
POLYNOMIAL[27]
POLYNOMIAL[28]
`0' POLYNOMIAL[29]
`0' POLYNOMIAL[30]
When the ring oscillator is stopped, the polynomial is forced to "0" and the ring is broken as illustrated by the following Figure.
Figure 16-10. Flexible FIRO31 when not Running
30 29 28 27 26 25 24 23 22 21 20 `0'
10
9
8
7
6
5
4
3
2
1
0
output
Constant ` 1'
30 29 28 27 26 25 24 23 22 21 20
10
9
8
7
6
5
4
3
2
1
0
output
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
The programmable polynomial specifies the oscillator feedback. The following figures illustrate two examples.
Figure 16-11. Flexible FIRO31 Examples
7-bit polynomia:l x7 + x6 + 1 (POLYNOMIAL = 0x0000:0041 << 24)
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 output
31 bit polynomial: x31 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 (POLYNOMIAL = 0x04c1:1db7)
30 29 28 27 26 25 24 23
22 21 20 19 18 17 16 15 14 13 12 11 10
98
7
65
4
32
1
0
output
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The TRNG has a build-in health monitor that performs tests on the digitized noise source to detect deviations from the intended behavior. E.g., the health monitor detects "stuck at" faults in the digitized analog samples. The health monitor tests one out of three selected digitized bit streams:
DAS bitstream. This is XOR of the digitized analog samples.
RED bitstream. This is the bitstream of reduction bits. Note that each reduction bit may be calculated over multiple DAS bits.
TR bitstream. This is the bitstream of true random bits (after the "von Neumann reduction" step).
The health monitor performs two different tests:
The repetition count test. This test checks for the repetition of the same bit value ('0' or '1') in a bitstream. A detection indicates that a specific active bit value (specified by a status field BIT) has repeated for a pre-programmed number of bits (specified by a control field CUTOFF_COUNT[7:0]). The test uses a counter to maintain the number of repetitions of the active bit value (specified by a status field REP_COUNT[7:0]).
If the test is started (specified by START_RC field) and a change in the bitstream value is observed, the active bit value BIT is set to the new bit value and the repetition counter REP_COUNT[] is set to "1". If the bitstream value is unchanged, the repetition counter REP_COUNT[] is incremented by "1".
A detection stops the test (the START_RC field is set to '0'), sets the associated interrupt status field to '1' and ensures that HW does NOT modify the status fields. When the test is stopped, REP_COUNT[] equals CUTOFF_COUNT[].
A detection stops the TRNG functionality (all TR_CMD
START
fields
are
set
to
'0')
if
TR_CTL.STOP_ON_RC_DETECT is set to '1'.
The adaptive proportion test. This test checks for a disproportionate occurrence of a specific bit value ('0' or '1') in a bit stream. A detection indicates that a specific active bit value (specified by a status field BIT) has occurred a pre-programmed number of times (specified by a control field CUTOFF_COUNT[15:0]) in a bit sequence of a specific bit window size (specified by a control field WINDOW_SIZE[15:0]). The test uses a counter to maintain an index in the current window (specified by WINDOW_INDEX[15:0]) and a counter to maintain the number of occurrences of the active bit value (specified by a status field OCC_COUNT[15:0]).
If the test is started (specified by START_AP field), the bitstream is partitioned in bit sequences of a specific window size. At the first bit of a bit sequence, the active bit value BIT is set to the first bit value, the counter WINDOW_INDEX is set to "0" and the counter OCC_COUNT is set to "1". For all other bits of a bit sequence, the counter WINDOW_INDEX is incremented by "1". If the new bit value equals the active bit value BIT, the counter OCC_COUNT[15:0] is incremented by "1". Note that the active bit value BIT is only set at the first bit of a bit sequence.
A detection stops the test (the START_AP field is set to '0'), sets the associated interrupt status field to '1' and ensures that HW does NOT modify the status fields. When the test is stopped, OCC_COUNT[] equals CUTOFF_COUNT[] and the WINDOW_INDEX identifies the bit sequence index on which the detection occurred.
A detection stops the TRNG functionality (all TR_CMD
START
fields
are
set
to
'0')
if
TR_CTL.STOP_ON_AP_DETECT is set to '1'.
The following figure illustrates the health monitor functionality.
Figure 16-12. TRNG Health Monitor Overview
digitized
analog samples (DAS)
Post-processing
INIT_DELAY[] RED_CLOCK_DIV[]
von Neumann corrector
true random
bit
BITSTREAM_SEL[]
DAS_SEL
Health monitor RED_SEL
TR_SEL
START_RC
Repetition count test
Adaptive proportion test
START_AP
CUTOFF_COUNT[]
CUTOFF_COUNT[] WINDOW_SIZE[] BIT REP_COUNT[] INTR.TR_RC_DETECT
BIT OCC_COUNT[] WINDOW_INDEX[] INTR.TR_AP_DETECT
16.2.2.3 AES
The AES component performs a block cipher or inverse block cipher per the AES standard (FIPS 197).
The block cipher translates a 128 bit block of plaintext data into a 128 bit block of ciphertext data.
The inverse block cipher translates a 128 bit block of ciphertext data into a 128 bit block of plaintext data
AES is a symmetric block cipher: the cipher and inverse cipher keys are the same. The component supports 128 bit, 192 bit and 256 bit keys. The AES algorithm generates so called round keys "on the fly" from the (start) round key as provided by SW. Round key generation is reversed for the cipher and inverse cipher.
The block cipher uses the symmetric key as the (start) round key for the first cipher round. The round key for second cipher round is derived from the symmetric key. The round key for the third cipher round is derived from the round key of the second cipher round, and so forth.
The inverse block cipher uses the round key of the final cipher round as the (start) round key for the first inverse cipher round. The round key for the second inverse cipher round is derived from the round key of the first inverse cipher round, and so forth.
The round key of the final inverse cipher round is the same as the symmetric key.
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The generated round keys are only dependent on the start key of the first round (in case of the block cipher this is the symmetric key). It is possible to derive the start round key for the inverse block cipher from the symmetric key, by performing a (forward) block cipher with arbitrary plaintext data.
The number of cipher (or inverse cipher) rounds depends on the key size. The following table gives the number of rounds.
Table 16-1. AES Key vs Rounds
AES key size 128-bit 192-bit 256-bit
Cipher (or inverse cipher) rounds 10 rounds 12 rounds 14 rounds
All AES operand data is provided by the memory buffer. For example, an AES block cipher operation has two source operands:
SRC_CTL0 specifies the offset of the start key (symmetric key).
SRC_CTL1 specifies the offset of the plaintext.
An AES block cipher operation has two destination operands:
DST_CTL0 specifies the offset of the last round key.
DST_CTL1 specifies the offset of the ciphertext. Note: It is a requirement that both source and destination key and both data buffers are fully (as in all bytes1) in the same memory type. For example if Start Key (SRC_CTRL0) is privileged then the Round Key (DST_CTL0) must be in privileged too (to avoid revealing the privileged key). The same must hold for the plaintext (SRC_CTL1) and ciphertext (DST_CTL1). If this is not the case then the algorithm is aborted and the ACCESS_ERROR interrupt is generated.
Note: To reduce space needed in the buffer it is allowed to overwrite the 'start key' with the 'last round key' and similarly it is also allowed to overwrite the input data with the output data.
The following figure illustrates the AES-128 cipher functionality. It illustrates how a forward block cipher translates a plaintext "pt_a[127:0]" into ciphertext "ct_a[127:0]" using a 128-bit start key "sk[127:0]". Besides the plaintext, the component produces the round key of the last cipher round "rk9[127:0]". If the round key of the last cipher round "rk9[127:0]" is used as the start key for an inverse block cipher on ciphertext "ct_a[127:0]", the original plaintext "pt_a[127:0]" is produced. Furthermore, the round key of the last inverse cipher round is the same as the forward block cipher key "sk[127:0]".
1. Take into account buffer wraparound.
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Figure 16-13. AES Operation Flow
Forward block cipher
Inverse block cipher
Memory buffer
SRC_CTL0
SRC_CTL1
Plaintext data pt_a[127:0]
SRC_CTL0
SRC_CTL1
Ciphertext data ct_a[127:0]
Start key sk[127:0]
Forward Round0
Start key irk0[127:0] equals rk9[127:0]
Inverse Round0
Forward rk1[127:0]
Forward Round1
Inverse irk1[127:0]
Inverse Round1
Forward rk8[127:0] Forward rk9[127:0]
DST_CTL0
Forward Round8
Inverse irk8[127:0]
Forward Round9
Inverse irk9[127:0] equals sk [127:0]
Ciphertext data ct _a[127:0]
DST_CTL1
DST_CTL0 Memory buffer
Inverse Round8
Inverse Round9
Plaintext data pt_a[127:0]
DST_CTL1
16.2.2.4 SHA
The SHA component performs a Secure Hash Algorithm (SHA) per the SHA standard (FIPS 180-4). The SHA algorithm calculates a fixed length hash value from a variable length message. The hash value is used to produce a message digest or signature.
It is computationally impossible to change the message without changing the signature.
The method is stateless: a given message always produces the same hash value. To prevent "replay attacks", a counter may be included in the message.
The SHA component supports a subset of the algorithms in the SHA standard: SHA1, SHA2-224 and SHA2-256.
Table 16-2. SHA Standard Hash Sizes
Algorithm
Block size
Word size
SHA1
512 bits 32 bits
SHA2-224 512 bits 32 bits
SHA2-256 512 bits 32 bits
Hash Message digest
value size
size
160 bits 160 bits
256 bits 224 bits
256 bits 256 bits
The memory buffer provides a message block on which the hash function is performed (SRC_CTL0) and the initial hash
value (SRC_CTL1). The message block must be laid out in little endian format.
The memory buffer provides working space for message schedule round constants (DST_CTL0). The HW derives these constants from the message. The round constants working space size depends on the algorithm.
Table 16-3. SHA SRAM Working Space Sizes
Algorithm SHA1 SHA2-224 SHA2-256
Working Space For Round Constants 320 Bytes 256 Bytes 256 Bytes
The memory buffer is used for the produced hash value (DST_CTL1).
The message must be preprocessed: a '1' bit must be appended to the message followed by '0's and a 64-bit bit size field. The preprocessed message consists of multiple 512-bit blocks. The SHA component processes a single 512-bit block at a time. The first SHA operation on the first message block uses the initial SHA hash value (as defined by the standard), subsequent SHA operations on successive blocks use the produced hash value of the previous SHA operation.
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The SHA operation on the last message block produces the final hash value. The message digest is a subset of the final hash value (SHA2-224) or the complete final hash value (SHA1 and SHA2-256). The following figure illustrates the SHA2-224 operation.
Figure 16-14. SHA Operation Flow
SHA2-224 operation
Memory buffer
SRC_CTL0
Produce round constants
SRC_CTL1
Initialize working registers with initial
hash value
Round 0
Round 1
Round 62 Round 63 Produce hash value
ister field CRC_DATA_CTL.DATA_SIZE[10:0] specifies the Byte size of the data. The MMIO register field CRC_DATA_CTL.DATA_XOR[7:0] specifies a byte pattern with which each data Byte is XOR'd. This allows for inversion of the data Byte value. The MMIO register field CRC_DATA_CTL.DATA_REVERSE allows for bit reversal of the data Byte (this provides support for serial interfaces that transfer Bytes in most-significant-bit first and least-significant bit first configurations).
The MMIO register field CRC_POL_CTL.POLYNOMIAL[31:0] specifies the polynomial. The polynomial specification omits the high order bit and should be left aligned. For example, popular 32-bit and 16-bit CRC polynomials are specified as follows:
CRC32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
CRC_POL_CTL.POLYNOMIAL[31:0] = 0x04c11db7
CRC16-CCITT: x16 + x12 + x5 + 1
CRC_POL_CTL.POLYNOMIAL[31:0] = (0x1021 << 16)
CRC16: x16 + x15 + x2 + 1
CRC_POL_CTL.POLYNOMIAL[31:0] = (0x8005 << 16)
The MMIO register field CRC_LFSR_CTL.LFSR[31:0] holds the state of the CRC calculation. Before the CRC operation, this field should be initialized with the CRC seed value.
The MMIO register field CRC_REM.REM[31:0] holds the result of the CRC calculation, and is derived from the end state of the CRC calculation (CRC_LFSR_CTL.LFSR[31:0]). The MMIO register field CRC_REM_CTL.REM_XOR[31:0] specifies a 32-bit pattern with which the end state is XOR'd. The MMIO register field CRC_REM_CTL.REM_REVERSE allows for bit reversal of the XOR'd state.
The following figure illustrates the CRC functionality.
DST_CTL0
DST_CTL0
DST_CTL1
Memory buffer
Note that it is a requirement that the memory locations used by the SHA operation are all of the same memory type, i.e. either all user or all privileged. If this is not the case then the algorithm is aborted and the ACCESS_ERROR interrupt is generated. This restriction is required to prevent user code from using the SHA operation to reveal information on data in privileged locations. Using the SHA operation on privileged data will require a new SystemCall API.
16.2.2.5 CRC
The CRC component performs a cyclic redundancy check with a programmable polynomial of up to 32 bits. The memory buffer provides the data on which the CRC is performed (SRC_CTL0 specifies the offset of the data in the buffer). The data must be laid out in little endian format (least significant Byte of a multi-Byte word should be located at the lowest memory address of the word). The MMIO reg-
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Figure 16-15. CRC Operation Flow
Memory buffer
Data control CRC_DATA_CTL. DATA_SIZE[10:0]
Data control CRC_DATA_CTL. DATA_XOR[7:0]
SRC_CTL0 data[7:0]
Data control CRC_DATA_CTL. DATA_REVERSE
Data bit reverse
Polynomial CRC_POL_CTL. POLYNOMIAL[31:0]
Remainder control CRC_REM_CTL. REM_XOR [31:0]
Linear Feedback Shift Register
CRC_LFSR_CTL. LFSR[31:0]
Remainder control CRC_REM_CTL. REM_REVERSE
Remainder bit reverse
Remainder CRC_REM.REM[31:0]
Note that the data must be in the user part of the buffer, if the data is in privileged locations then the algorithm is aborted and the ACCESS_ERROR interrupt is generated. The restriction is required to prevent user code from using the CRC operation to read privileged memory locations.
The Linear Feedback Shift Register functionality operates on the LFSR state. It uses the programmed polynomial and consumes a data bit for each iteration (8 iterations are performed per cycle to provide a throughput of one data Byte per cycle). The following Figure illustrates the functionality for the CRC32 polynomial (x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1).
Figure 16-16. CRC32 Polynomial
CRC32 (x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1)
data bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q
D
LFSR0 bit
clk
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Different CRC algorithms require different seed values and have different requirements w.r.t. XOR functionality and bit reversal. The following Table provides the proper settings for the CRC32, CRC16-CCITT and CRC16 algorithms.
Table 16-4. Standard CRC Settings and Results
MMIO Register Field
CRC_POL_CTL.POLYNOMIAL
0x04c11db7
CRC_DATA_CTL.DATA_REVERSE 1
CRC_DATA_CTL.DATA_XOR
0x00
CRC_LFSR_CTL.LFSR (seed)
0xffffffff
CRC_REM_CTL.REM_REVERSE 1
CRC_REM_CTL.REM_XOR
0xffffffff
CRC_REM.REM
0x3c4687af
CRC32
CRC16-CCITT 0x10210000 0 0x00 0xffff0000 0 0x00000000 0xf8a00000
CRC16 0x80050000 1 0x00 0xffff0000 1 0x00000000 0x000048d0
The Table also provides the remainder after the algorithm has been performed on a five byte array {0x12, 0x34, 0x56, 0x78, 0x9a}.
16.2.2.6 Trigger Interface
The crypto block operation is under SW control (MMIO CMD register) or under HW control (trigger interface). In both cases, the MMIO CTL.OPCODE register field specifies which operation needs to be performed.
In case of HW controlled operation, the rising edge of the input trigger "tr_in" starts an operation. When the operation completes, a two cycle high/'1' pulse (on "clk_sys") is generated on the output trigger "tr_out" to indicate operation completion.
Note that "tr_out" is generated for both SW initiated operation and HW initiated operation.
16.2.2.7 Memory Buffer
The block uses regular registers to capture its MMIO control and status information and uses SRAMs to capture its operand data. The SRAMs maintain their information in DeepSleep power mode. In DeepSleep power mode, the SRAM array is powered and the SRAM periphery is not powered. During DeepSleep, the functional SRAM inputs and outputs are isolated (the unpowered periphery is isolated from powered logic).
DST_CTL1 specifies the offset of the ciphertext.
Only a single operation can be performed at a time, e.g. it is not possible to perform an AES block cipher and SHA hash function simultaneously. However, it is possible to write the source operand data of the next operation in the memory buffer, when the current operation is active. Note that MMIO access to the SRAM memory has higher priority over the operation access to the SRAM memory.
16.2.2.8 Protection
The CCG3 chip platform uses a chip protection mode, which restricts DAP access to MMIO registers and memory regions. The block's memory buffer is a memory region and is subject to these restrictions.
Next to that, the chip's platform uses a user/privileged execution mode. When the platform is in user execution mode AHB does NOT have access to privileged MMIO and memory regions. When the platform is in Privileged execution mode both user and privileged MMIO and memory are freely accessible from AHB. The privilege/user boundary of the memory buffer is set with the PRIV_BUF register, which itself is privileged.
The offsets of operand data in the memory buffer are under SW control and as specified by the SRC_CTL0, SRC_CTL1, DST_CTL0 and DST_CTL1 MMIO registers. Offsets are 32bit offsets in the memory buffer. Operand data "wraps around" in the memory buffer. Operand data should not overlap in the memory buffer as destination operands may overwrite source operands.
SRC_CTL0 and SRC_CTL1 are used for source operands and DST_CTL0 and DST_CTL1 are used for destination operands. Operand data is dependent on the specific operation. For example, an AES block cipher operation has two source operands:
SRC_CTL0 specifies the offset of the start key (symmetric key).
SRC_CTL1 specifies the offset of the plaintext.
An AES block cipher operation has two destination operands:
DST_CTL0 specifies the offset of the last round key.
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The following table summarizes these restrictions.
Table 16-5. Protection
Protection Mode
VIRGIN OPEN PROTECTED KILL BOOT DMA: User mode only
CPU (and DW/DMA)
Memory Buffer Accesses
Mmio Register Accesses
Free access
Free access
Privileges enforced
Privileges enforced
Privileges enforced
Privileges enforced
Privileges enforced Free access
Privileges enforced CPU: Free access
Inoperable
Inoperable
DAP
Memory Buffer Accesses Mmio Register Accesses
Free access User mode only
Free access User mode only
Inoperable
Inoperable
Inoperable
Inoperable
Note: Blocking of DAP access to MMIO registers in PROTECTED, BOOT and KILL modes is not implemented. It implements MMIO register protection through m0s8ahbb_ahbslv_if3 module and this module depends on the fact that the MMIO accesses from DAP are blocked at source (in m0s8cpussv3) in PROTECTED, BOOT and KILL modes.
For the AES block cipher, the memory buffer is used to store cipher and inverse cipher keys. As mentioned, the DAP has no access to the memory buffer in BOOT, PROTECTED and KILL protection modes. As a result, the DAP cannot access keys in the memory buffer. To prevent accesses from "untrusted" user mode CPU code, the chip platform's user/privileged execution mode is used. This is achieved as follows:
Typically encryption Keys can either be on chip secrets stored in privileged flash memory. Or Keys can be ephemeral and stored in user SRAM.
The privileged flash memory region is ONLY accessible from privileged code. Cypress provides FW functions (SystemCalls) to write key information in privileged flash memory and to copy key information from privileged flash memory to the privileged part of the memory buffer.
The Cypress customer uses the Cypress FW function to write key information in privileged flash memory during his manufacturing flow.
The customer application uses the Cypress FW function to copy key information from privileged flash memory to the privileged region in the memory buffer. As a result, only the privileged Cypress FW function, privileged flash memory and the block HW have knowledge of the Secret Key.
Ephemeral AES Keys, typically resulting from authentication communication, are stored in SRAM user locations. The customer application (in user mode) can handle those keys directly.
Each operation has restrictions on user/privilege locations of keys and data. These restrictions are required to prevent exposing privileged data to user code. If the restriction is violated by the application then the operation is aborted and the ACCESS_ERROR interrupt is set.
The privileged/user boundary in the PRIV_BUF MMIO register (which itself is privileged) is typically set during boot with a value from the supervisory rows.
A new SystemCall allows the boundary to be moved, but as part of this SystemCall the privileged part of the memory buffer will first be cleared.
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16.3 Block Operation
16.3.1 Reset and Initialization
This block receives two active low asynchronous reset inputs "rst_sys_act_n" and "rst_sys_dpslp_n". The following diagram shows the reset connection strategy for this block.
Figure 16-17. Reset Strategy
rst_sys_dpslp_n
AES
Retained MMIO
registers
SHA
PR
TR
CRC
CTL.ENABLED rst_sys_act_n
m0s8tk_rst_and rst_crypto_act_n
AHB-Lite IF
Non-retained MMIO
registers
The "rst_sys_dpslp_n" is used to reset MMIO registers which can retain their value during DeepSleep power mode.
The AHB-Lite slave interface component is connected to "rst_sys_act_n" reset.
Rest of the Active power domain logic (AES, SHA, PR, CRC and Non-retention MMIO registers) is connected to "rst_crypto_act_n" reset signal as shown in the above figure. Hence this logic will be in reset state whenever the block is disabled.
16.3.2 Functional Modes and Usage Requirements
16.3.2.1 Pseudo Random Number Generator
Pseudo Random number generation is under SW control. It involves the following steps: 1. Enable the block. 2. Initialize the LFSRs with non-zero seed values. 3. Configure the range [0, PR_CTL.MAX[31:0]]. 4. Start a pseudo random number generation operation. 5. Retrieve the results when the operation has completed. Waiting for the operation to be completed can be done by either
polling or through an ISR.
The following code sequence illustrates how a pseudo random number in the range [0, 9] is generated.
*CRYPTO_CTL
= (1 << 31) | "CRC";// enable block
*CRYPTO_PR_LFSR_CTL0 = 0x12345678;// LFSR seed values
*CRYPTO_PR_LFSR_CTL1 = 0x7264f6a1;
*CRYPTO_PR_LFSR_CTL2 = 0x03456236;
*CRYPTO_PR_CTL
= 9;// results in the range [0, 9]
*CRYPTO_CMD
= (1 << 0);// start operation
while (*CRYPTO_CMD & (1 << 0)) ;// wait for operation to complete
result = *PR_RESULT;
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16.3.2.2 AES
The AES encryption operation is under SW control. It involves the following steps: 6. Enable the block. 7. Initialize the memory buffer with the start key. 8. Initialize the memory buffer with plaintext/ciphertext data. 9. Specify the memory buffer offsets of the source and destination operands. 10. Specify the key size. 11. Start a forward/inverse cipher operation. 12. Retrieve the results from the memory buffer when the operation has completed.
The following code sequence illustrates how a 128-bit forward block cipher operation is performed.
uint8_t Key[] = {
// encryption key
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
0x0f};
uint8_t PlainText[] = {
// plain text
0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee,
0xff};
uint8_t CipherText[16]; // cipher text
uint8_t Check[] = {
// expected cipher text
0x69, 0xc4, 0xe0, 0xd8, 0x6a, 0x7b, 0x04, 0x30, 0xd8, 0xcd, 0xb7, 0x80, 0x70, 0xb4, 0xc5,
0x5a};
*CRYPTO_CTL
= (1 << 31) | "AES cipher"; // enable block
for (i = 0 ; i < 16; i++) *(CRYPTO_MEM_BUFF
+ i) = Key[i];
for (i = 0 ; i < 16; i++) *(CRYPTO_MEM_BUFF + 0x10 + i) = PlainText[i];
*CRYPTO_SRC_CTL0
= 0x00;// key offset
*CRYPTO_SRC_CTL1
= 0x10;// plain text offset
*CRYPTO_DST_CTL0
= 0x20;// round key 9 offset
*CRYPTO_DST_CTL1
= 0x30;// cipher text offset
*CRYPTO_AES_CTL
= 0;// 128-bit key
*CRYPTO_CMD
= (1 << 0);// start block cipher operation
while (*CRYPTO_CMD & (1 << 0)) ;// wait for operation to complete
for (i = 0 ; i < 16; i++) CipherText[i] = *(CRYPTO_MEM_BUFF + 0x30 + i);
Note on AES operation modes. NIST (National Institute of Standards and Technology) publication 800-30A specifies block cipher modes of operation. It recommends five modes of operation for use with an underlying symmetric key block cipher algorithm. They are: ECB: Electronic Code Book CBC:Cipher Block Chaining CFB:Cipher FeedBack OFB: Output FeedBack CTR:Counter
The AES component of this block provides ECB mode of operation. The other modes of operation involve pre and/or post XOR operations of an initialization vector and plaintext/ciphertext. These XOR operations can be implemented in SW to implement other operation modes of AES.
16.3.2.3 SHA
The SHA operation is under SW control. It involves the following steps: 1. Enable the block. 2. Initialize the memory buffer with initial hash value. 3. Initialize the memory buffer with the message block. 4. Specify the memory buffer offsets of the source and destination operands.
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5. Specify the hash operation. 6. Start a hash operation.
7. Retrieve the results from the memory buffer when the operation has completed.
The following code sequence illustrates how a SHA2-224 operation is performed on a three Byte message "abc".
uint8_t Message[] = "abc"; uint8_t InitHash[32] = {// initial hash value per the standard
0xc1, 0x05, 0x9e, 0xd8, 0x36, 0x7c, 0xd5, 0x07, 0x30, 0x70, 0xdd, 0x17, 0xf7, 0x0e, 0x59, 0x39,
0xff, 0xc0, 0x0b, 0x31, 0x68, 0x58, 0x15, 0x11, 0x64, 0xf9, 0x8f, 0xa7, 0xbe, 0xfa, 0x4f, 0xa4}; uint8_t ProducedHash[32] = {// expected final hash
0x23, 0x09, 0x7d, 0x22, 0x34, 0x05, 0xd8, 0x22, 0x86, 0x42, 0xa4, 0x77, 0xbd, 0xa2, 0x55, 0xb3,
0x2a, 0xad, 0xbc, 0xe4, 0xbd, 0xa0, 0xb3, 0xf7, 0xe3, 0x6c, 0x9d, 0xa7, 0xd2, 0xda, 0x08, 0x2d};
*CRYPTO_CTL
= (1 << 31) | "SHA"; // enable block
size = sizeof (Message) - 1; // forget about trailing 0x00.
for (i = 0 ; i < size; i++) *(CRYPTO_MEM_BUFF + i) = Message[i]; *(CRYPTO_MEM_BUFF + i) = 0x80; i++;// append '1' for (i < 63; i++) *(CRYPTO_MEM_BUFF + i) = 0x00; *(CRYPTO_MEM_BUFF + 63) = 0x18;// bit size of message
for (i = 0 ; i < 32; i++) *(CRYPTO_MEM_BUFF + 0x80 + i) = InitHash[i];
*CRYPTO_SRC_CTL0
= 0x00;// message block offset
*CRYPTO_SRC_CTL1
= 0x80;// initial hash offset
*CRYPTO_DST_CTL0
= 0x100;// round keys (64 words) offset
*CRYPTO_DST_CTL1
= 0x80;// produced hash
*CRYPTO_SHA_CTL
= 2;// SHA2-224
*CRYPTO_CMD
= (1 << 0);// start operation
while (*CRYPTO_CMD & (1 << 0));// wait for operation to complete
for (i = 0 ; i < 32; i++) ProducedHash[i] = *(CRYPTO_MEM_BUFF + 0x80 + i);
16.3.2.4 CRC
CRC is under SW control. It involves the following steps: 1. Enable the block. 2. Initialize the memory buffer with the data. 3. Specify the size of the data array. 4. Specify the memory buffer offsets of the source operand (data). 5. Specify the processing of the data (XOR mask and bit reversal). 6. Specify the polynomial. 7. Specify the LFSR seed values. 8. Specify the processing of the remainder (XOR mask and bit reversal). 9. Start a CRC operation. 10. Retrieve the results from the CRC_REM MMIO register when the operation has completed. The following code sequence illustrates how a CRC operation is performed with a 32-bit polynomial: uint8_t Data[] = {
0x12, 0x34, 0x56, 0x78, 0x9a};
*CRYPTO_CTL
= (1 << 31) | "CRC";// enable block
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for (i = 0 ; i < 6; i++) *(CRYPTO_MEM_BUFF + i) = Data[i];
*CRYPTO_SRC_CTL0
= 0x00;// data offset
*CRYPTO_CRC_DATA_CTL0
= (5 << 16) | 1;// 6 Bytes, data byte bit reversal
*CRYPTO_CRC_DATA_CTL1
= 0x00;// data byte XOR pattern
*CRYPTO_CRC_POL_CTL
= 0x04c11db7;// polynomial
*CRYPTO_CRC_LFSR_CTL
= 0xffffffff;// seed value
*CRYPTO_CRC_DATA_CTL0
= 1;// remainder bit reversal
*CRYPTO_CRC_DATA_CTL1
= 0xffffffff;// remainder XOR pattern
*CRYPTO_CMD
= (1 << 0);// start CRC operation
while (*CRYPTO_CMD & (1 << 0)) ;// wait for operation to complete
result = *CRYPTO_CRC_REM;
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16.4 Block Interface Requirements
16.4.1 Functional Timing Requirements and Diagrams
Note the following:
The interrupt output ("interrupt") is level sensitive and remains high until SW clears it.
The trigger input can be asynchronous to "clk_sys", but its width should be at least two cycle pulse on "clk_sys".
The trigger output generated ("tr_out") is a two cycle pulse on "clk_sys".
16.4.2 Bandwidth/Latency Requirements
The following table documents the performance of crypto block. The clock cycles referred to are related to this particular block's clock cycles. The performance depends on the operation that is performed. The numbers are for the operation only, and do not include time that SW takes to setup the MMIO registers or memory buffer or the time that SW takes to retrieve the results from MMIO registers or memory buffer.
Note: There will be one more cycle delay when the operation is initiated by HW trigger input (because the trigger is synchronized inside the block) if the number of cycles is measured between "tr_in" and "tr_out".
Table 16-6. Performance
Performance
Operation
(Clock Cycles refer to block's clock cycles)
AES-128 forward cipher
106 clock cycles
AES-128 inverse cipher 103 clock cycles
AES-192 forward cipher
126 clock cycles
AES-192 inverse cipher 123 clock cycles
AES-256 forward cipher
146 clock cycles
AES-256 inverse cipher 143 clock cycles
PR number generation 34 clock cycles
SHA1
516 clock cycles
SHA2-224
413 clock cycles
SHA2-256
413 clock cycles
CRC
1 clock cycle per data Byte + 4
Note: SW should be aware of the number of cycles that an operation is going to take when implementing Sleep power mode and wake up through CRYPTO interrupt. A case might happen where CRYPTO interrupt occurs before even the WFI instruction is executed (depending on the delay between start of CRYPTO operation and execution of WFI instruction).
16.4.3 Bit/Byte Ordering
All the Bit/Byte ordering in this block is little-endian.
The operand data in the SRAM memory should also be laid out in little-endian format (Least Significant Byte of multi byte word should be located at the lowest memory address of the word).
16.4.4 Data Underrun/Overrun
The SRAM memory stores the operand data and results of the operation. Operand data should not overlap in the memory buffer as destination operands may overwrite source operands. For AES, it is allowed to overwrite the 'start key' with the 'last round key' and similarly it is also allowed to overwrite the input data with the output data if user want to reduce the space needed in buffer.
The following table shows the space required for each operand pointer for AES and SHA operations.
Table 16-7. AES and SHA Operand Space Requirements
Pointer AES-128 AES-192 AES-256 SHA1 SHA2
SRC_CTL0 16 Bytes 24 Bytes 32 Bytes 64 Bytes 64 Bytes
SRC_CTL1 16 Bytes 16 Bytes 16 Bytes 20 bytes 32 Bytes
DST_CTL0
16 Bytes 24 Bytes
32 Bytes
320 Bytes
256 Bytes
DST_CTL1 16 Bytes 16 Bytes 16 Bytes 20 bytes 32 Bytes
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16.5 Power Architecture and Modes
The following sections explain the power architecture for the SRSS-Lite based SoCs.
16.5.1.2 Power Domains
The following figure shows the power domains for SRSSLite based SoCs.
Figure 16-18. SRSS-Lite Power Domains
16.5.1 SRSS-Lite
crypto_crc
crypto_pr
crypto_sram_power
16.5.1.1 Power Modes
Active, Sleep, DeepSleep and XRES are the power modes defined in SRSS-Lite System Resources Subsystem. The following table describes the status of this block during different power modes in the SRSS-Lite based system.
Table 16-8. SRSS-Lite Power Modes
Power Mode
Description
Active, Sleep
All the logic is powered on along with the SRAM memory. The Crypto block is functional in Active and Sleep power modes.
All the logic is powered ON.
System clock "clk_sys" is gated OFF.
DeepSleep
SRAM memory periphery is powered OFF ("act_power_en_n" = 1).
SRAM array power is ON ("dpslp_power_up_n"=0).
SRAM content and configuration MMIO are retained
crypto_mmio crypto_aes
crypto_mem
0 0
crypto_sha
Memory buffer inputs (SRAM)
outputs
Active power domain Default power domain
The following figure shows the detailed SRAM power connections.
Figure 16-19. SRSS-Lite SRAM power connections
act_isolate_n
test_scan_mode act_power_en_n
CRYPTO logic (Active power domain with "vccd" supply)
0
0
vssd Bleeder
1'b0
DO WLBI
WLOFF
AD, DI, R_WB, EN,BEN
vpwrp
vpwra
TM vpwrpc
SRAM Memory
vpwrm vpb
vccd
act_bleed
dpslp_power_up_n
vpwrac
CLKin
vgnd vnb
vssd
clk_sys
clock_crypto_sram_en
ICG
Note the following:
All the logic belongs in Active power domain only.
The SRAM memory periphery will be switched OFF during DeepSleep power mode.
Isolation cells will be added both on inputs ("AD[]", "DI[]", "EN", "R_WB", and "BEN[]") and outputs ("DO[]") of SRAM memory as shown in the above Figure. Isolation
cells on SRAM memory inputs are required to reduce leakage power due to pass gate multiplexing structures used in SRAM circuit. UPF defines isolation strategy for these isolation cells.
The scan related pins of SRAM memory ("ScanOutCC", "ScanInCC", "ScanInDL", and "ScanInDR") will be hooked up only after DfT insertion and should be isolated after DfT insertion at chip level.
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The SRAM memory contents will be retained in DeepSleep power mode. Hence SRAM array power will not be switched OFF during DeepSleep power mode (Note how the array power control "vpwrac" is connected to "dpslp_power_up_en_n").
16.5.1.3 Retention Strategy
The MMIO registers are connected to "rst_sys_dpslp_n" and hence the MMIO configuration registers are retained in DeepSleep power mode.
The SRAM memory contents will be retained in DeepSleep power mode.
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17. USB Full Speed (USB FS)
The CCG3 USB block acts as a USB device that communicates with a USB host. The USB block is available as a fixed-function digital block in the CCG3 device. It supports full-speed communication (12 Mbps) and is designed to be compliant with the USB Specification Revision.2.0. USB devices can be designed for plug and play applications with the host and also support hot swapping. This chapter details the CCG3 USB block and transfer modes. For details about the USB specification, see the USB Implementers Forum web site.
17.1 Features
The PSoC USB has these features: Complies with USB Specification 2.0 Supports full-speed peripheral device operation with a signaling bit rate of 12 Mbps Supports eight data endpoints and one control endpoint Supports four types of transfers bulk, interrupt, isochronous, and control Supports bus- and self-powered configurations USB suspend mode for low power Supports the following logical transfer mode:
Store and Forward mode Differential signal (D+ and D-) output Integrated 22- USB termination resistors on D+ and D lines, and 1.5-k pull-up resistor on the D+ line Supports maximum packet size of 64 bytes using the Store and Forward mode for bulk endpoints and maximum packet
size of 512 for isochronous transfers in store and forward mode
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17.2 Block Diagram
Figure 17-1 illustrates the architecture of the USB block. It consists of the USB Physical Layer (USB PHY), Serial Interface Engine (SIE), Arbiter, and the local 512-byte memory buffer.
Figure 17-1. USB FS Block Diagram
USB Block
512 Bytes SRAM
Arbiter
Memory Interface
Arbiter Logic
CPU Interface
SIE Interface
CPU Subsystem
SIE
USB PHY D+ D-
17.2.1 USB Physical Layer (USB PHY)
This block takes care of physical layer communication with the USB host through the D+ and D- pins. It handles the differential mode communication with the host and monitoring events such as SE0 on the USB bus.
17.2.2 Serial Interface Engine (SIE)
The Serial Interface Engine (SIE) is responsible for handling the decoding and creating of data and control packets during transmit and receive. It decodes the USB bit streams into USB packets during receive and creates USB bit streams during transmit. The following are the features of the SIE block:
Conforms to the USB 2.0 Specification
Supports one device address
Supports eight data endpoints and control endpoint
Supports interrupt trigger event for each endpoint
Integrates an 8-byte buffer in the control endpoint
The registers for this block are mainly used to configure the data endpoint operations and the control endpoint data buffers. This block also controls the interrupt events available for each endpoint.
17.2.3 Arbiter
The Arbiter is the block that handles access of the SRAM memory by the endpoints. The SRAM memory can be accessed by the CPU or the SIE. The Arbiter handles the arbitration between the CPU and the SIE. The Arbiter consists of the following blocks:
SIE Interface Module
CPU Interface Module
Memory Interface
Arbiter Logic
The Arbiter registers are used to handle the endpoint configurations, Read address, and Write address for the endpoints. It also configures the logical transfer type required for each endpoint. The Arbiter in the CCG3 device family supports only mode 0.
17.2.3.1 SIE Interface Module
This module handles all the transactions with the SIE block. The SIE reads data from the SRAM memory and transmits to the host. Similarly, it writes the data received from the host to the SRAM memory. These requests are registered in the SIE Interface module and are handled by this block.
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17.2.3.2 Memory Interface
17.3 How it Works
The memory interface is used to control the interface between the USB block and the SRAM memory unit. The maximum memory size supported is 512 bytes organized as 256 x a 16-bit memory unit. This is a dedicated memory for the USB. The memory access can be requested by the SIE or by the CPU. The SIE Interface block and the CPU Interface block handle these requests.
17.2.3.3 Arbiter Logic
This is the main block of the Arbiter. It is responsible for arbitrations for all the transactions that happen in the Arbiter. It arbitrates the CPU and SIE access to the memory unit and the registers. This block also handles the memory management. The memory management is either "Manual" or "Automatic." In Manual memory management, the read and write address manipulations are done by the firmware. This block also handles the interrupt requests for each endpoint.
17.3.1 USB Physical Layer (USB PHY)
The USB block includes the transmitter and the receiver (transceiver), which corresponds to the USB PHY.
Figure 17-2 shows the PHY architecture. The USB PHY in PSoC also includes the pull-up resistor on the D+ line to identity the device as full-speed type to the host. The PHY integrates the 22- series termination resistors on the USB lines. The signal between the USB device and the host is a differential signal. The receiver receives the differential signal from the host and converts it to a single-ended signal for processing by the SIE. The transmitter converts the singleended signal from the SIE to the differential signal, and transmits it to the host. The differential signal is given to the upstream devices at a nominal voltage range of 0 V to 3.3 V.
Figure 17-2. USB PHY Architecture
CCG3
P0[0]
VBUS Detection and PHY Isolation
Logic
VDDD
Bus( Host) powered or Self Powered
Voltage Regulator (5 V to 3. 3 V mode or
Bypass mode)
USB D+ Pull Up Enable Logic
GPIO Mode Logic
ten td dpi dmi
rd dpo dmo rse0
Transmitter Logic
Receiver Logic
1. 5 K
22
22
D+
Upstream D- Host/ Hub
17.3.1.1 Power Scheme
The USB PHY is powered by the VDDD power pad of the CCG3 device. The USB PHY needs a nominal voltage of 3.3 V for its communication with the host. The REG_ENABLE bit in the USB_CR1 register controls the operation of the internal voltage regulator. CCG3's VDDD rail is derived from a regulated output from VBUS or VSYS. For applications using VBUS as the primary supply (bus-powered applications), the regulator inside the USB PHY must be bypassed by setting REG_ENABLE bit to 0. In applications using VSYS as the primary supply (self-powered applications), the regulator should be enabled when the VSYS is outside the 3.3 V (3.15 V to 3.45 V) range. When the VSYS supply voltage is in the 5-V range (4.35 V to 5.5 V), the REG_ENABLE bit must be set high to enable the internal regulator.
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17.3.1.2 VBUS Detection
USB devices have the option of deriving power from the VBUS power signal from the host (bus-powered configuration) or having an external power supply independent of host VBUS (self-powered configuration). The CCG3 VBUS regulator is inside the USBPD subsystem. The VBUS detect interrupt and status registers from the USBPD subsystem must be used.
The VBUS detect is mapped to the INT_WAKEUP interrupt of the USBPD subsystem. The corresponding VBUS status can be read from NCELL_STATUS register by reading the VBUS_C_STATUS field. Once VBUS is detected through the interrupt and status register, the CPU can enable the pull-ups in the device to signal attach to the host.
17.3.1.3 USB PHY Isolation Logic
The USB PHY has an isolation logic to disable the PHY output signals when the host VBUS is not present.
Figure 17-3. USB PHY Output Isolation Logic
VBUS_VALID_OVR [1:0]
0
0
1
1
P0[0]
2
P13[2]
3
(VBUS pad)
ISOLATE
iso_n (Control Signal to USB PHY)
The PHY is designed to operate from a VBUS supply independent from any other supplies such as VDDD and VCCD in the chip and contains the appropriate isolation logic. Figure 17-3 shows the isolation logic signal (iso_n) generation. iso_n is an active low signal which is used to isolate the output of the PHY (generated in the VBUS power domain) from the rest of the chip operating in other independent power domain. The device firmware can set the ISOLATE bit field in the USB_POWER_CTRL register to isolate the PHY outputs irrespective of the state of VBUS.
The CCG3 PHY does not require any dynamic isolation control by firmware since it operates from a common VDDD power rail. So the VBUS_VALID_OVR[1:0] bit fields in the USB_POWER_CTRL register should be either selected to 1 or 3 from the following selection:
1: Force vbus_valid=1
3: Use vbus_valid signal from PHY detector.
The device firmware should enable the USB block operation only after the host VBUS is present - detected by reading the status of VBUS from NCELL_STATUS register of USBPD (field VBUS_C_STATUS)
When VBUS is present, the device firmware should clear the ISOLATE bit field in the USB_POWER_CTRL register after a delay of at least 2 µs. Thereafter, the signal selected by VBUS_VALID_OVR[1:0] will take care of dynamic PHY output isolation. When the USB block is stopped in the device firmware, the ISOLATE bit field should be set as part of the stop sequence
17.3.1.4 USB D+ pin Pull-up Enable Logic
When a USB device is self-powered, the USB specification warrants that the device enable the pull-up resistor on its D+ pin to identify itself as a full-speed device to the host. When the host VBUS is removed, the device should disable the pull-up resistor on the D+ line so as to not back power the host. The USB PHY block includes an internal 1.5-k pull- up resistor on the D+ line to indicate to the host that the CCG3 is a full-speed device. The pull-up resistor can be enabled or disabled by configuring the USBPUEN bit in the USBIO_CR1 register. The firmware should read VBUS status to enable/disable the pull-up resistor on the D+ pin.
17.3.1.5 Transmitter and Receiver Logic
The transmitter logic takes care of differential transmission to the USB host.
The transmitter can be manually forced to transmit signals. The USB_USBIO_CR0 register is used to manually transmit the signals. Examples are as follows:
When the manual transmission is enabled, the register can be configured to transmit Single-Ended Zero signal (that is, D+ and D are low).
Configurable to transmit the USB signals. The USB signals can be two types:
D+ low and D high = J
D+ high and D low = K
The register also has a bit, which is used to read the received signal levels. The bit can show if D+ < D or D+ > D.
17.3.2 Endpoints
The SIE and Arbiter support eight data endpoints (EP1 to EP8) and one control endpoint (EP0). The data endpoints share the SRAM memory area of 512 bytes. The endpoint memory management can be either Manual or Automatic. The endpoints are configured for direction and other configuration using the SIE and arbiter registers. The endpoint read address and write address registers are accessed through the Arbiter.
The endpoints can be individually made active. In the Auto Management mode, the register USB_EP_ACTIVE is written to control the active state of the endpoint. The endpoint activation cannot be dynamically changed during runtime. In Manual Memory Management mode, the firmware decides the memory allocation, so it is not required to specify the active endpoints. The USB_EP_ACTIVE register is ignored during the manual memory management mode. The USB_EP_TYPE register is used to control the transfer direction (IN, OUT) for the endpoints. The control endpoint has separate eight bytes for its data (USB_EP0_DR registers).
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17.3.3 Transfer Types
The CCG3 USB supports full-speed transfers and is compliant with the USB 2.0 Specification. It supports four types of transfers:
Interrupt Transfer
Bulk Transfer
Isochronous Transfer
Control Transfer
For further details about these transfers, refer to the USB Specification 2.0.
17.3.4 Interrupts
The USB block has three general-purpose interrupt lines INTR_LO, INTR_MED, and INTR_HI. Refer to the Interrupts chapter on page 35 for the vector numbers of these interrupt lines. The USB block has a predefined set of 12 interrupt trigger events that can be mapped to either one of the three interrupts. The interrupt line to which each of the trigger event is mapped is configured through the USB_INTR_LVL_SEL register. Each of these three interrupt lines has a status register to identify the event that cause of the interrupt. These are the USB_INTR_CAUSE_LO, USB_INTR_CAUSE_MED, and USB_INTR_CAUSE_HI status registers.
The following 12 events can be used to generate an interrupt on one of the three interrupt lines.
USB Start of Frame (SOF) Event
USB Bus Reset Event
Eight Data Endpoint (EP1 EP8) interrupt events
Control Endpoint (EP0) interrupt event
Arbiter Interrupt event
The following sections provide details on each of these interrupt events.
17.3.4.1 Data Endpoint Interrupt Events
These are eight interrupt events corresponding to each data endpoint (EP1-EP8). Each of the endpoint interrupt events can be enabled/disabled by using the corresponding bit in the USB_SIE_EP_INT_EN register. The interrupt status of each endpoint can be known by reading the USB_SIE_EP_INT_SR status register. An endpoint whose interrupt is enabled can trigger the interrupt on the following events:
Successful completion of an IN/OUT transfer
NAK-ed IN/OUT transaction if the corresponding NAK_INT_EN bit in the SIE_EPx_CR0 register is set
When there is an error in the transaction, the bit ERR_IN_TXN in the SIE_EPx_CR0 register is set and interrupt is generated. Refer to the register description for details on the conditions under which this bit can be set.
If the STALL bit in SIE_EPx_CR0 is set, then stall events can generate interrupts. This stall event can happen if an
OUT packet is received for an endpoint whose mode bits in SIE_EPx_CR0 are set to ACK_OUT or if an IN packet is received with mode bits set to ACK_IN.
17.3.4.2 Control Endpoint (EP0) Interrupt Event
The interrupt event corresponding to the control endpoint (EP0) is generated under the following events:
Successful completion of an IN/OUT transfer
When a SETUP packet is received on the control endpoint
17.3.4.3 Arbiter Interrupt Event
The arbiter generates an interrupt event for the endpoints during the following events - the final arbiter interrupt event is the logical OR of these events.
IN endpoint local buffer full:
This event status is set on different conditions in Store and Forward mode.
Store and Forward Mode: This status is set when the entire packet data has been transferred to the local memory. The check is that data written for the particular endpoint is equal to the programmed Byte Count for that endpoint in the USB.SIE_EPx.CNT0 and USB.SIE_EPx.CNT1 registers.
17.3.4.4 USB Start of Frame (SOF) Event
Generated whenever the SOF is received. The SOF interrupt is enabled by setting the SOF_INTR_MASK bit in the USB_INTR_SIE_MASK register. The SOF interrupt status is reflected in the SOF_INTR status bit in the USB_INTR_SIE status register.
The SOF interrupt status is also available in the SOF_INTR_MASKED bit of the USB_INTR_SIE_MASKED register this bit is the logical AND of corresponding SOF bits in the USB_INTR_SIE_MASK register and the USB_INTR_SIE register.
The USB packet decoder in the SIE decodes the SOF PID and asserts a pulse of width one 12-MHz clock cycle. This pulse is synchronized to the system clock (SYSCLK) and can be routed as a digital signal through the Digital System Interconnect (DSI) interface. This routing feature is in addition to the interrupt feature.
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17.3.4.5 USB Bus Reset Event
Generated whenever a USB bus reset condition occurs. The bus reset interrupt is enabled by setting the BUS_RESET_INTR_MASK bit in the USB_INTR_SIE_MASK register. The bus reset interrupt status is reflected in the BUS_RESET_INTR status bit in the USB_INTR_SIE status register.
The bus reset interrupt status is also available in the BUS_RESET_INTR_MASKED bit of the USB_INTR_SIE_MASKED register this bit is the logical AND of corresponding bus reset bits in the USB_INTR_SIE_MASK register and the USB_INTR_SIE register.
The 32-kHz low-frequency clock (LFCLK) is used to detect the USB bus reset condition. It is required that the LFCLK is enabled in the application firmware. The SIE logic triggers on counter running on LFCLK when a SE0 condition is detected on the USB bus. When the counter reaches the count value configured in the USB_BUS_RST_CNT register, the bus reset interrupt is triggered. It is recommended to set the count value in the USB_BUS_RST_CNT register to three to detect the bus reset condition.
17.4 Logical Transfer Modes
The USB block in CCG3 devices supports only mode 1, which is store and forward logical transfer mode. Table 17-1
describes the details of Store and Forward transfer mode.
Table 17-1. USB Transfer Modes
Feature
Store and Forward Mode
SRAM Memory Usage
Requires more memory
SRAM Memory Management Manual
SRAM Memory Sharing IN Command
512 bytes of SRAM shared between endpoints. Sharing is done by firmware.
Entire packet present in SRAM memory before the IN command is received.
OUT Command
Entire packet is written to SRAM memory on OUT command. After entire data is available, it is copied from SRAM memory to the USB device.
Transfer of Data
Data is transferred when all bytes are written to the memory.
Supported Transfer Types Best suited for Interrupt and Bulk transfers
The logical transfer can be configured using the register setting for each endpoint. Any of the logical transfer methods can be adapted to support the three types of data transfers (Interrupt, Bulk, and Isochronous) mentioned in the USB 2.0 Specification. The Control transfer is mandatory in any USB device.
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Every endpoint has a set of registers that need to be handled during the modes of operation, as detailed in Table 17-2.
Table 17-2. Endpoint Registers
Register ARB_RWx_WA ARB_RWx_RA
Comment
Content
Endpoint Write Address reg- Address of the
ister
SRAM
Endpoint Read Address reg- Address of the
ister
SRAM
ARB_RWx_DR
Endpoint Data Register
8-Bit Data
SIE_EPx_CNT0 and SIE_EPx_CNT1
Endpoint Byte Count Register
Number of Bytes
"Mode" bits in SIE_EPx_CR0
Mode Values
Response to the Host
Usage
This register indicates the SRAM location to which the data in the Data register is to be written.
This register indicates the SRAM location from which the data must be read and stored to the Data register.
Data register is read/ written to perform any transaction.
IN command: Data written to the Data register is copied to the SRAM location specified by the WA register. After write, the WA value is automatically incremented to point to the next memory location.
OUT command: Data available in the SRAM location pointed by the RA register is read and stored to the DR. When the DR is read, the value of RA is automatically incremented to point to the next SRAM memory location that must be read.
Holds the number of bytes that can be transferred.
IN command: Holds the number of bytes to be transferred to host.
OUT command: Holds the maximum number of bytes that can be received. The firmware programs the maximum number of bytes that can be received for that endpoint. The SIE updates the register with the number of bytes received for the endpoint.
Controls how the USB device responds to the USB traffic and the USB host. Some examples of mode include ACK, NAK, STALL, etc. See Table 17-1 on page 162 for additional details.
In Manual Memory Management, the endpoint read and endpoint write address registers are updated by the firmware. So the memory allocation can be done as required by the user and the memory allocation decides which endpoints are active; that is, the user can decide to share the 512 bytes for all the eight endpoints or a lesser number of endpoints.
In Automatic memory management, the endpoint read and endpoint write address registers are updated by the USB block. The block assigns memory to the endpoints that are activated using the USB_EP_ACTIVE register. The size of memory allocated depends on the value in the USB_BUF_SIZE register. The rest of the memory, after allocation, is called the "Common Area" memory and used for the transfer of data.
In the following text, the algorithm for the IN and OUT transaction for each mode is discussed. An IN transaction is when the data is read by the USB host (for example, PC). An OUT transaction is when the data is written by the USB host to the USB device.
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17.4.1 Store and Forward Mode
17.4.1.1 No DMA Access
This is the Manual Memory Management mode with no DMA access.
IN Transaction (CPU Write, SIE Read): The steps for an IN transaction on an IN endpoint are shown in Figure 17-4. OUT Transaction (CPU Read, SIE Write): The steps for an OUT transaction on an OUT endpoint are shown in Figure 17-5.
Figure 17-4. No DMA Access IN Transaction
Figure 17-5. No DMA Access OUT Transaction
Write WA register (based on required memory allocation)
To inhibit CRC set the "crc_bypass" bit in the ARB_EPx_CFG
register
Write maximum packet size to Byte Count register
Set mode value in CR0 register
Write WA register (based on required memory allocation)
Write packet size to Byte Count register
Write data to Data register
No Is all
data written to SRAM?
Yes
Write the RA register (same as initial WA register)
Set mode value in CR0 register
Value automatically written to the SRAM specified by WA location. WA++
Wait No
Is IN command received?
Yes
USB Block reads value from RA and transmits to host.
RA++
No
Responds automatically with ACK (configured as Mode value)
Is all data transmitted?
Yes
Set the mode as NAK for the last byte in transfer. Status
bits set by the block
Interrupt Generated
Wait No
Is OUT command received?
Yes
Data received from host written to SRAM
location WA WA++
Is all data written to
SRAM?
Responds automatically with ACK (configured as mode value)
No
Yes
SIE sets mode to NAK. Updates Byte Count with actual number of data received and sets the data valid bit
Data in Data register is read
by CPU and given to device.
RA++ is done automatically.
Write the RA value (same as initial WA)
SIE Data Interrupt Generated
USB Block reads the data at location RA and writes to Data
register
No Is all data read from SRAM?
Yes
End
17.4.1.2 Manual DMA Access/CutThrough Mode
CCG3 does not support DMA modes (manual or cutthrough) as there is no DMA engine in CCG3 devices.
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17.4.2 Control Endpoint Logical Transfer
The control endpoint has a special logical transfer mode. It does not share the 512 bytes of memory. Instead, it has a dedicated 8-byte register buffer (USB_EP0_DRx registers). The IN and OUT transaction for the control endpoint is detailed in the following figures.
Figure 17-6. Control Endpoint IN Transaction
Set the mode bits to ACK the IN token
No
Is SETUP token received
Yes
The block ACKs it
Generates Interrupt and sets the bit to indicate that IN token is received.
Read the status bit and the Data valid bit
Is Data Valid?
Yes Read the EP0_DRx register to find the
type of request
Copy the required data to the EP0_DRx registers
Set the data valid bit and the mode bits. Also update the byte count value
No
Is IN token received?
No
No
Yes
The block transmits the data from the EP0_DRx registers
The block sets the mode value to NAK all further IN tokens.
Blocks generates interrupt on receiving ACK from host and sets the IN byte received bit.
Are all bytes transferred?
Yes
End
USB Full Speed (USB FS)
Figure 17-7. Control Endpoint OUT Transaction
Program the mode bits for ACK_OUT No Is the SETUP token
received? Yes
The block ACKs the SETUP token
Generates Interrupt and sets a bit in EP0_CR register to indicate that SETUP token was received.
Read the Data valid bit in EP0_CNT
Is data valid?
Yes Read EP0_DRx to read the type of request
Update the mode bits to ACK an OUT token
No
Is OUT token received?
Yes
The block stores the received byte to the EP0_DRx register and ACK the received byte.
Interrupt generated.
No
No
Read the status and data valid bits
Is data valid?
No
Yes
Set the mode bit to NAK all OUT tokens till all bytes have been received.
Are all bytes received?
Yes
End
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17.5 Register Summary
Register Name USBDEVv2_EP0_DRx USBDEVv2_CR0 USBDEVv2_CR1 USBDEVv2_SIE_EP_INT_EN USBDEVv2_SIE_EP_INT_SR USBDEVv2_SIE_EPx_CNT0
USBDEVv2_SIE_EPx_CNT1
USBDEVv2_SIE_EPx_CR0
USBDEVv2_USBIO_CR0
USBDEVv2_USBIO_CR1
USBDEVv2_DYN_RECONFIG USBDEVv2_SOF0 USBDEVv2_SOF1 USBDEVv2_OSCLK_DR0 USBDEVv2_OSCLK_DR1 USBDEVv2_EP0_CR USBDEVv2_EP0_CNT
USBDEVv2_ARB_EPx_CFG
USBDEVv2_ARB_EPx_INT_EN
USBDEVv2_ARB_EPx_SR USBDEVv2_ARB_RWx_WA USBDEVv2_ARB_RWx_WA_MSB USBDEVv2_ARB_RWx_RA USBDEVv2_ARB_RWx_RA_MSB USBDEVv2_ARB_RWx_DR USBDEVv2_BUF_SIZE USBDEVv2_EP_ACTIVE
Description
Control Endpoint EP0 Data Register. 'x' can be 07 for the 8-byte EP0 data buffer
USB Control 0 Register. Register to enable the USB device and specify the 7-bit device address
USB Control 1 Register. Register to configure the USB block regulator, read bus activity status, and enable the internal oscillator to the USB traffic
USB SIE Data Endpoints Interrupt Enable Register
USB SIE Data Endpoint Interrupt Status
Non-control Endpoint Byte Count Register. 'x' can be 18 corresponding to one of the eight data endpoints. This register stores the most significant 3-bits of the 11-bit byte counter, the toggle state of the data packet, and data valid status.
Non-control Endpoint Byte Count Register. 'x' can be 18 corresponding to one of the eight data endpoints. This register stores the lower eight bits of the 11-bit byte count value.
Non-control Endpoint Control Register. 'x' can be 18 corresponding to one of the eight data endpoints. This register contains the endpoint operating mode, error status, stall control, and the NAK interrupt generation.
USBIO Control 0 Register. This register contains the control and configuration bits for the USB I/Os (D+ and D pins respectively) for single-ended and differential mode operation.
USBIO Control 1 Register. This register contains the control and configuration bits for the USB I/Os (D+ and D pins respectively) for selecting the USB operating mode, reading the single ended USBIO receiver outputs, and enabling pull-up resistor on the D+ line.
USB Dynamic Reconfiguration Register. This register is used to control the status of dynamic reconfiguration of an endpoint.
Start Of Frame Register. This register contains the lower eight bits [7:0] of the SOF frame number.
Start Of Frame Register. This register contains the upper three bits [10:8] of the SOF frame number.
Oscillator Lock Data Register 0. This register contains the lower eight bits of the oscillator locking circuit's adder output.
Oscillator Lock Data Register 1. This register contains the upper seven bits of the oscillator locking circuit's adder output.
Endpoint0 Control Register. This register contains operating mode of the control endpoint, and the status bits for different packet conditions on the control endpoint.
Endpoint0 Count Register. This register stores the 4-bit byte counter, the toggle state of the data packet, and data valid status.
Endpoint Configuration Register. 'x' can be 18 corresponding to one of the eight data endpoints. This register contains the settings to reset the endpoint buffer pointers, CRC bypass feature, manual DMA request, and the data ready status.
Endpoint Interrupt Enable Register. 'x' can be 18 corresponding to one of the eight data endpoints. Register to configure the conditions under which an interrupt should be generated for an endpoint.
Endpoint Interrupt Status Register. 'x' can be 18 corresponding to one of the eight data endpoints. Register to read the interrupt status of an endpoint.
Endpoint Write Address value. 'x' can be 18 corresponding to one of the eight data endpoints. Lower eight bits of the 9-bit write address pointer.
Endpoint Write Address value. 'x' can be 18 corresponding to one of the eight data endpoints. Most significant bit of the 9-bit write address pointer.
Endpoint Read Address value. 'x' can be 18 corresponding to one of the eight data endpoints. Lower eight bits of the 9-bit read address pointer.
Endpoint Read Address value. 'x' can be 18 corresponding to one of the eight data endpoints. Most significant bit of the 9-bit read address pointer.
Endpoint Data Register. 'x' can be 18 corresponding to one of the eight data endpoints.
Dedicated Endpoint Buffer Size Register
Endpoint Active Indication Register
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Register Name
Description
USBDEVv2_EP_TYPE
Endpoint Type (IN/OUT) Indication register
USBDEVv2_ARB_CFG
Arbiter Configuration Register. This register is used to configure the buffer management mode of the USB block.
USBDEVv2_USB_CLK_EN
USB Block Clock Enable Register
USBDEVv2_ARB_INT_EN
Arbiter Interrupt Enable Register. This register contains the configuration to enable arbiter interrupt generation for each endpoint.
USBDEVv2_ARB_INT_SR
Arbiter Interrupt Status Register. This register contains the status of arbiter interrupt generation due to each endpoint.
USBDEVv2_CWA
Common Area Write Address Register. This register contains the lower eight bits of the 9-bit write address pointer for the common area.
USBDEVv2_CWA_MSB
Common Area Write Address Register. This register contains the most significant bit of the 9-bit write address pointer for the common area.
USBDEVv2_DMA_THRES
DMA Burst/Threshold Configuration Register. This register contains the lower eight bits of the 9bit threshold byte count value.
USBDEVv2_DMA_THRES_MSB
DMA Burst/Threshold Configuration Register. This register contains the most significant bit of the 9-bit threshold byte count value.
USBDEVv2_BUS_RST_CNT
Bus Reset Count Register. This register contains the number of clock cycles of LFCLK that should elapse to detect a bus reset condition.
USBDEVv2_MEM_DATAx
This is the 512-byte data buffer for storing the non-control endpoint data. 'x' can be 0 to 511.
USBDEVv2_SOF16
16-bit version of the Start Of Frame Register
USBDEVv2_OSCLK_DR16
16-bit version of the Oscillator Lock Data Register
USBDEVv2_ARB_RWx_WA16
16-bit version of the Endpoint Write Address Value Register. 'x' can be 1 to 8.
USBDEVv2_ARB_RWx_RA16
16-bit version of the Endpoint Read Address Value Register. 'x' can be 1 to 8.
USBDEVv2_CWA16
16-bit version of the Common Area Write Address Register
USBDEVv2_ARB_RWx_DR16
16-bit version of the Endpoint Data Register. 'x' can be 1 to 8
USBDEVv2_DMA_THRES16
16-bit version of the DMA Burst/Threshold Configuration Register
USBDEVv2_USB_POWER_CTRL
Power Control Register
USBDEVv2_USB_CHGDET_CTRL
Charger Detection Control Register
USBDEVv2_USB_USBIO_CTRL
USB I/O Control Register
USBDEVv2_USB_FLOW_CTRL
Flow Control Register
USBDEVv2_USB_LPM_CTRL
LPM Control Register
USBDEVv2_USB_LPM_STAT
LPM Status Register
USBDEVv2_USB_INTR_SIE
USB SOF, BUS RESET, and EP0 Interrupt Status Register
USBDEVv2_USB_INTR_SIE_SET
USB SOF, BUS RESET, and EP0 Interrupt Set Register
USBDEVv2_USB_INTR_SIE_MASK USB SOF, BUS RESET, and EP0 Interrupt Mask Register
USBDEVv2_USB_INTR_SIE_MASKED USB SOF, BUS RESET, and EP0 Interrupt Masked Register
USBDEVv2_USB_INTR_LVL_SEL
USB Interrupt Level Select Register
USBDEVv2_USB_INTR_CAUSE_HI High Priority Interrupt Cause Register
USBDEVv2_USB_INTR_CAUSE_MED Medium Priority Interrupt Cause Register
USBDEVv2_USB_INTR_CAUSE_LO Low Priority Interrupt Cause Register
USBDEVv2_USB_PHY_TRIM0
PHY Trim Control Register
USBDEVv2_USB_PHY_TRIM1
PHY Trim Control Register
USBDEVv2_USB_PHY_TRIM2
PHY Trim Control Register
USBDEVv2_USB_PHY_TRIM3
PHY Trim Control Register
USBDEVv2_USB_CHGDET_TRIM
Charger Detect Trim Values Register
USBDEVv2_USB_TRIM
Trim Values Register
USBDEVv2_USB_USBIO_TRIM
Trim Values for I/Os Register
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Section F: USB Power Delivery
This section encompasses the following chapter: USB Power Delivery chapter on page 165
Top Level Architecture
USB Power Delivery Block Diagram
Peripheral Interconnec(t (MM)IO)
USB-PD SS
HV REG OVP OCP
2 x 2 ANALOG XBAR 2 X VCONN FET
2 X GATE DRIVER CHG DET CC BB PHY ADC / ACA
Pads, ESD
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18. USB Power Delivery
CCG3 uses an inbuilt USB Power Delivery (USB PD) baseband PHY. This PHY supports all the features as per the USB Power Delivery 2.0 specification and USB Type-C Cable and Connector specification rev 1.0. USB PD block implements the PD communication using a dedicated Communication Channel (CC) using Bi-phase Mark Coding (BMC). USB PD block contains a dedicated SRAM to store USB PD Rx and Tx header and messages coming as a part of USB PD negotiations. In addition, it includes all termination resistors required to implement various Type-C roles such as DFP, UFP and DRP. This block includes everything necessary to support UFP, DFP, DRP and EMCAs for with the USB Type-C connector. The baseband transceiver is used for SOP, SOP' or SOP'' communication over the CC line. The Rp/Rd/Ra termination is chosen based on the application. The 8-bit ADC is used for generic voltage sensing of anything connected to the analog mux (AMUX) buses, as well as voltage supply measurement and temperature sensing.
18.1 Features
The CSA block implements a current sense amplifier and over current (OCP) detection circuit. This block can use the internal power FET as the sense resistor or it can use an external sense resistor for sensing the current.
The 20VREG block is a 20V to 5V regulator that can deliver a maximum of 30mA of load current. The UVOV block implements an under-voltage/over-voltage (UVOV) detection circuit. The thresholds for both OCP and
UVOV are made programmable. The SBU block implements four bi-directional analog switches between SBU1/SBU2 pins and AUX_P/ AUX_N pins. It
also implements terminations required for the DisplayPort 1.2 standard. The 300MA_SW block implements a 5 V/300 mA power FET to meet the requirements of a regular VCONN switch. The VDDD_SW block is a 5-V power-switcher, which selects from two power supplies to provide the VDDD output. In this
case the two supplies are the 20-V regulator output and the VSYS input. The DPSLP_REF block implements voltage and current references which are used by all other parts of the USBPD block. The CPUMP block generates the gate voltage for NMOS back-power protection devices. The VCONN_TERM implements Ra termination and VCONN detection for a single VCONN supply. This is necessary for
Type-C VCONN powered accessories. The VBUS_DISCHG block contains pull down control circuit for VBUS to ground discharge path. The CHGDET block implements PHY portion of BC.1.2 and quick charge protocols. CCG3 contains two ADC blocks. The ADC is an 8-bit SAR ADC, which can measure the voltage on either AMUX bus,
measure the supply voltage level, and measure the on-die temperature. The USBPD block also includes the 8kV IEC ESD protection circuits to be used for the 20V VBUS pad, 5V CC1/2 pads
and the 5V SBU1/2 pads.
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18.2 Block Diagram
Figure 18-1 shows the USB PD system block diagram.
Figure 18-1. USB PD Block Diagram
to amuxa/b
vddd to srss
ov_det
uv_det uvov_ctrl
UVOV
20VREG
vreg
dischg_en vddd_sw_ctrl
vconn_det
pump_en
cc_pump_en
5V Pump
cc_tx_data
CPUMP
cc_rx_data cc_ctrl cc_comp_out
adc_cmp_out
VDDD_SW
VCONN_TERM
VCONN Detect
Neg
Ra
Pump
CC
TX
Rp
RX
Ref
Comp Active Rd
USBPD Subsystem
usbpd_20v_iec
VBUS
20V pad, 8kV IEC ESD
DISCHG
LS
PUMP
VSYS VBUS_DISCHG
VGDIN NGDO
VCONN usbpd_cc_iec
CC1
CC2
DB Rd
8kV IEC ESD
vbg
dac_ctrl
DPSLP_REF
dpslp_ref_en Beta Mult Vref
& Iref Gen
vconn_sw_ctrl
Deepsleep voltage and current references
csa_ctrl ocp_out
sbu_sw_ctrl
8-bit DAC + Comp
ADC
CSA
Well Control
Gate Drive
300mA_SW
SBU_SW
V5V
INP INN SBU1 SBU2
chgdet_out chgdet_ctrl
CHGDET
Term Detect
Term Emulation
AUX_P AUX_N DP DM
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18.3 Configuration Options
Type-C Connector Pull-up and Pull-down termination trim
Baseband Transceiver Tx and Rx trim Options for increased Tx and Rx thresholds for addi-
tional Ground IR Drop Type-C Connector voltage detect threshold trim Termination configuration to support: UFP, DFP, DRP,
Powered cable Programmable overcurrent, overvoltage, and undervolt-
age thresholds
18.4 Block Applications
The USBPD block supports the USB Power Delivery Specification and the USB Type-C Specification. It implements the analog portions of the USBPD BMC PHY, and Type-C connector detect and termination functions. Figure 18-1 shows the internal architecture of the USBPD block. The CC cell contains a transceiver for communication over the Type-C connector CC1 or CC2 lines. It contains configurable pull-up and pull-down termination to communicate current capabilities and detach/attach events. It has three comparators to sense the connected device termination, determine current source capabilities and detect detach/attach events. The block also supports dead battery pull-down termination for the Rd impedance, which is connected to the RD1 and CC2 pins. 8kV IEC ESD protection is provided by the CC_IEC pad cell. A positive charge pump, CPUMP, provides a boosted supply to drive the gates of NMOS back-power protection transistors. VCONN power is supplied to the cable by the 300mA_Sw block, which connects the V5V supply to either the CC1 or CC2 pin.
The SBU_SW cell contains a 2x2 crossbar analog switch network. It allows connecting the SBU1/2 pins to the AUX_P and AUX_N pins in one of two combinations. It also contains controllable resistor termination that supports the auxiliary mode for the DisplayPort 1.2 spec.
The VCONN_TERM cell provides 8kV IEC ESD protection on the VCONN supply for VCONN-powered accessories. It contains dead battery Ra termination, a negative charge pump for disabling the Ra resistor, and a detector to determine if the VCONN supply is present.
The DPSLP_REF cell generates voltage and current references, which are used in deep sleep mode. Many of the blocks require these references during the deep sleep mode.
The ADC cell is an 8-bit DAC and comparator used to form an 8-bit SAR ADC with the appropriate SAR control logic. It is used to measure voltages on the AMUX busses, measure the supply voltage level, or measure the on-die temperature.
The 20VREG cell allows the chip to be powered off of the VBUS supply, even when it is operating at 20V. The regula-
tor supplies power to the chip level VDDD supply. The VDDD_SW cell can switch in the VSYS supply when it is available, and prevents back-powering from the regulator output in the VSYS supply. The DISCHG cell is a controlled pull-down path for an external resistor to discharge the VBUS supply.
The UVOV cell is used for detecting the voltage level of the VBUS supply. It has programmable settings for detecting two thresholds, and overvoltage threshold and an undervoltage threshold.
The CSA cell is a high-side CSA (Current Sensing Amplifier) used for detecting the amount of current flowing from an external power supply. It requires an external high precision sense resistor. When current flows through the resistor, the CSA amplifies and senses the small voltage developed across the resistor. The amplified voltage is compared against a reference voltage, and the output can be used for OCP (Overcurrent Protection) to disable the external power FET.
The CHGDET cell implements the charger detect and termination for legacy (pre-Type-C) charger schemes.
18.4.1 CC Block
18.4.1.1 CC Block Brief Architecture & Functional Description
The block in Figure 18-2 contains the USB PD transceiver for baseband signaling communication over the CC1/CC2 lines. The Transmitter (TX) drives 1.125V slew-rate controlled data onto the chosen CC line. The Receiver (RX) converts received data on the chosen CC line to a full-rail signal for decoding. The comparator (COMP) block contains two Deep Sleep comparators used to detect attach/detach and CC line activity events, and determine the voltage range on the chosen CC line. The idle voltage on the CC lines is generated by the voltage divider of the pull-up and pulldown termination, which indicates the advertised current capability of the DFP. The Reference generator block generates the necessary voltages for the transmitter voltage, receiver threshold, and comparator thresholds.
The IPU blocks generate current sources for the pull up termination on the CC lines and they are configurable to indicate which current profile the DFP or DRP supports.
When used in a DFP application and no cable is attached, it is important to have the lowest possible deep sleep power consumption. When waiting for attach, all blocks are disabled except for the DS (Deep Sleep) Attach Detect block. This implements a pull-up resistor and senses the CC lines to determine if any pull-down termination is attached.
The Rd pull-down resistors are used for the UFP termination. When no power is present, the dead battery termination is presented by the Rd_db pull-down resistors. The impedance of these resistors will be presented if the voltage
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on the CC line rises above a certain threshold, even if the rest of the chip is not powered up. The Rd_db termination is brought out to separate rd1_term and rd2_term ports, so that chip level connections can determine if dead battery termination is present on the CC lines.
Figure 18-2 shows the possible configuration options in order to support different Type-C applications. The DFP does not need any pull-down termination, so the chip level CC1 and CC2 pins are connected to the CC1 and CC2 ports. The UFP, DRP, and Debug Accessory applications need to have dead battery Rd termination on the CC1 and CC2 pins, so they are additionally connected to the rd1_term and rd2_term ports. The Powered Cable application requires data communication over the CC line, and Ra pull-down termination on the VCONN supply. The VCONN Powered Accessory, needs CC communication as well Rd termination on the CC line, with Ra pull-down termination on the VCONN supply. Ra termination is implemented in the VCONN_SW or VCONN_TERM block.
Figure 18-2. Block Diagram of CC Block
18.4.2 CSA Block
18.4.2.1 CSA Block's Brief Architecture & Functional Description
The CSA current sense amplifier translates an elevated differential signal across signals inp and inn to a ground referenced signal, out_a, and compares it against a reference voltage, vref, to produce an indicator output, out_d. Its primary function in the USB PD system is as an over current detector.
As illustrated in Figure 18-3, the CSA block consists of two stages. The first stage operates by reproducing the Vsense voltage as V'sense across resistor RP and sending the resulting current, IL, across RL. The DC gain is simply the ratio of RL/RP and the output signal at out_a is given by the following equation.
Vout _ a
RL RP
Vsense
RL RP
Vinp
Vinn
The second stage is a comparator that is used to signal the relative logic state of out_a compared to the input voltage reference signal, vref.
The iref_gen block receives an on-chip system reference current (via iref) and produces the bias currents necessary to activate the two stages.
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Figure 18-3. Block Diagram of CSA Block
VIN
Rsense Isense
inp
+ Vsense -
inn
vddd
iref
vgnd
RP + V'sense -
-
gate_ctl s
stage 1_amp
inp hv
+
MPOUT
out1
+ stage2_comp
-
iref_s1
iref_s2 iref_gen
Stage1
IL RL
Vgnd
Stage2
out_a
out_d vref
Either of the two outputs, out_a and out_d, can be used for mission-mode functionality, where out_a can be delivered to an on-die ADC.
18.4.3 20VReg Block
18.4.3.1 20VReg's Brief Architecture & Functional Description
Figure 18-4 shows the block diagram of the high voltage interface system. Per the USB PD specifications, VBUS can go from 4.75 V to 24 V. The regulator is based on Low drop out based architecture with PMOS pass element. Typical regulator output is 3.3 V and the reference voltage of 0.74 V is coming from DPSLP_REF block.
Figure 18-4. Block Diagram of 20VReg Block
VBUS
Source follower
c
Vrefdpslp
-
Opamp
+
biasn1 biasn2
biasp1
NMOS biasp2 protection
biasp3
PMOS pass transistor
PMOS protection
biasn3 biasn4
biasp4
VBUS_REG
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18.4.4 UVOV Block
18.4.4.1
UVOV Block's Brief Architecture & Functional Description
Figure 18-5. Block Diagram of UVOV Block
vbus
R64
vpwrhv
R63
vpwr
uv_det pd
comparator
+
CFILT1
-
R62 R61
R60
vref0p74
uv_in<5:0>
6 bit decoder and
R0
enable _hv
level-shifter
iso_n
vpwrhv +
CFILT2
-
comparator
vpwr
ov_det pd
6 bit decoder and level-shifter
ADFT
adft_ctrl<1:0>
ov_in<5:0>
enable _hv iso_n
adft1 adft2
Figure 18-5 shows the block diagram for UVOV block and how the UVOV block is used to detect the overvoltage and/or undervoltage condition on the VBUS input line. The threshold levels for the UV and OV detection can be set independent of each other. Both UV and OV detector have programmable thresholds and can be programmed from 64 available values.
A single resistor string from VBUS is used to drop the voltage from VBUS down to zero. The 6-bit input for both UV and OV is decoded in LV domain and the outputs are level-shifted. The level-shifted output chooses one of the switches from the resistor string. The output from the switch is applied to the comparator. The comparator compares the switch output to a fixed voltage of 0.74 V. The 0.74 V is generated in HV_REF block and is always available once the chip is powered-up.
This circuit is capable of detecting inputs all the way up to 28 V. However, the operating voltage is only 20 V. Higher voltages will cause stress on the high side of resistor ladder.
This block can be disabled in order to minimize power. The pd signal is used to turn off the comparator block UVOV_Comp and the bias generator block UVOV_Bias.
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18.4.5 SBU_Sw Block
18.4.5.1
SBU_Sw Block's Brief Architecture & Functional Description
Figure 18-6. Block Diagram of SBU_Sw Block
in1_out1_en
out 1_pu_en AUX_P
out1_pd_en
out2_pu_en AUX_N
out2_pd_en
usb_sw
in2_out1_en
usb_sw
in1_out2_en
usb_sw
in2_out2_en
usb_sw
in1_pu_en SBU1
in1_pd_en
in2_pu_en in2_pd_en
SBU2
Figure 18-7. Switch Architecture of SBU_Sw Block
in
vpwr
vpump
sw_en
LEVEL-SHIFTER
vpump
BULKSWITCHER
vgnd
Figure 18-6 shows the top level architecture of SBU block. It has four switches between SBU1/SBU2 and AUX_P/AUX_N pins. This block is used to route the SBU1/SBUS2 signals to AUX_P/AUX_N pins according to Type-C plug orientation.
Figure 18-7 shows the block diagram of switches shown in Figure 18-6. It is a simple CMOS switch. Bulk switcher block which is shown in the figure is used to pull the PMOS bulk to VPUMP voltage when switch is in OFF state to reduce the
out
off leakage current. When switch is ON PMOS bulk is connected to pin "in". Similarly bulk of NMOS is connected to ground when switch is OFF. When switch is ON bulk of NMOS is connected to pin "out".
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18.4.6 VDDD_Sw Block
18.4.6.1
VDDD_Sw Block's Brief Architecture & Functional Description
Figure 18-8. Block Diagram of VDDD_Sw Block VSYS
vpwr
pd iso_n
vsys _ovrd enable _hv
LEVEL-SHIFTER
VSYS Detector
vsys _det
Vddd
Figure 18-8 shows the block diagram of the VDDD switch circuit which connects the VSYS supply of the chip to the VDDD pin. It is a simple PMOS switch which is controlled using the "vsys_ovrd" signal of this block. This block is a CMOS logic block and hence does not require to be disabled to save power. It can be used for operation during deepsleep mode if appropriate LV power and control signals are provided.
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18.4.7 NGDO Block
18.4.7.1
NGDO Block's Brief Architecture & Functional Description
Figure 18-9. Block Diagram of NGDO Block
vpwr_in2
USB Power Delivery
CLK
C1 (MOM Cap)
C1 (MOM Cap)
N20VHV (20V NFET)
N20VHV (20V NFET)
P20VHV (20V PFET)
vout (vpwr_in1 + vpwr_in2)
P20VHV (20V PFET)
VBUS
p20vhv (pfet)
5M? (HRPOLY)
en<0> OR
en<1>
n20vhv (nfet)
Inverter's in "vpwr_in1" domain
CHARGE -PUMP
vpwr_in2 (20V)
VBUS_REG
vpwr_in1
(5V)
CLK (vpwr_in1 domain)
CHARGE PUMP
vout1 (25V)
vpwr_in1 (5V)
vpwr_in2 (25V)
CLK
CHARGE vout2
(vpwr_in1 domain)
PUMP
(30V)
p20vhv (pfet)
en<0>
n20vhv
PD
(nfet)
vpwr_in1 (5V)
vpwr_in2 (25V)
CLK
CHARGE vout2
(vpwr_in1 domain)
PUMP
(30V)
p20vhv (pfet)
en<1>
n20vhv
PD
(nfet)
5M? (HR POL Y)
5M? (HR POL Y)
5M? (HR POLY)
5M? (HR POLY)
gdo_out<0>
n20vhv (nfet )
gdo_out<1>
n20vhv (nfet )
Figure 18-9 shows the block diagram of the NMOS power FET gate driver block. The charge-pump block is used to boost the input VBUS to provide a higher voltage (VBUS + 2*VDDD) on the NGDO_OUT output.
This block can be disabled to save power. It is meant to be used for operation during Deep Sleep mode.
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18.4.8 DPSLP_Ref Block
18.4.8.1
DPSLP_Ref Block's Brief Architecture & Function Description
Figure 18-10. Block Diagram of DPSLP_Ref Block
dpslp_ref_pd
POWER GATING
trim_lv<3:0>
BETA MULT
vrefdpslp
adft_en_lv adft_ctrl
ADFT
vssq
ref_adft
itrim<7:0> itrim_tc<3:0>
DPSLP IREF
enable_hv iref_2p4u igen_en
IREF MIRROR
ib_2p4u<17:0> ib_0p6u<1:0> isnk_0p6u
Figure 18-10 shows the block diagram for the DPSLP_Ref block. This sub-block consists of three main blocks - Beta-Multiplier, Deepsleep IREF, and an IREF mirror.
The Beta multiplier block generates the reference voltage for the System Resources SubSystem block in the deep-sleep mode. The output of this block (vrefdpslp) is based on the difference between vth of the nhv device and the nhvnative device and its default value is 740mV.
The Deepsleep current reference generator creates a voltage and temperature compensated 2.4µA reference current. The block creates PTAT, CTAT, and currents proportional to the supply voltage, and combines them to reduce the variance due to temperature and voltage.
The current reference mirror block takes in one 2.4µA input and creates 20 copies of the same current by using a precision current mirror. It also creates a 0.6µA reference for the VCONN_Sw block.
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18.4.9 CPUMP block
18.4.9.1
CPUMP Block's Brief Architecture & Functional Description
Figure 18-11. Block Diagram of CPUMP Block
vpwr vddd
bypass_lv
ext_clk_sel clkin
pd en_hvapp
en_hv
Internal oscillator
Level shifter & control
adft <1:0>
ADFT
MUX
4-stage charge pump core
vfb comp_out
+ -
6 in series
vpump
3 in series
refh refl
adft1 adft2
ib2p4u<1:0>
This CPUMP block, shown in Figure 18-11, contains the analog circuitry for a charge pump that boosts the VCCD supply input of 1.2 V to an output of ~5.25 V. This voltage is used for the gate control of the CC block's NMOS back power protection devices. The block contents are: Control logic for level shifting and power down, Internal Oscillator, Clock MUX, 4-Stage Charge Pump Core, and Feedback Resistor and Comparator.
The internal oscillator produces a ~24MHz clock for use with the charge pump core. The clock MUX selects between the internal oscillator or an external clock source, clkin. The internal oscillator is necessary since this block may be operational in deep sleep mode, when no other clocks are available. The 4-stage charge pump core pumps the vccd supply voltage from 1.2 V to >5 V. The feedback loop created by the resistor divider and comparator (referenced to the bandgap voltage vrefin) clamp the voltage to 5.25 V.
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18.4.10 VCONN_Term Block
18.4.10.1 VCONN_Term Block's Brief Architecture & Functional Description
Figure 18-12. Block Diagram of VCONN_Term Block VCONN
en_comp
R1
R2
vref_0p74
-
Comparator
+
R3 vconn_det
VCONN
Leaker
Ra
Circuits
Negative Vth NMOS
pump_en
Negative charge pump
leaker _config<2:0>
Figure 18-12 shows the block diagram of VCONN_Term block. R1 and R2 form a voltage divider from the VCONN supply to ground, and the comparator checks against the 0.74V deep sleep reference to determine if VCONN is connected. The VCONN Ra termination is implemented a resistor and a Negative Vt NMOS device. When the Ra termination needs to be disabled, the gate voltage must be driven negative. A negative charge pump is implemented in order to generate the negative gate voltage required. If the use is intended for cable applications, it is the cable's responsibility to discharge the VCONN node when the cable is disconnected from the VCONN supply. Leaker circuits are implemented to meet this requirement.
To save power at the system level, the Ra termination should be disabled. This is accomplished by driving the Negative Vt NMOS gate to a negative voltage. The negative charge pump generates this voltage, and must always be on, even in deep sleep. However, if the VCONN supplies are not connected, then the charge pump can be disabled to save power during the deep sleep mode of operation.
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18.4.11 VBUS_DISCHG Block
18.4.11.1 VBUS_DISCHG Block's Brief Architecture & Functional Description
Figure 18-13. Block Diagram of VBUS_DISCHG Block
VBUS
vpwr vpump
dischg_en enable_hv
LEVEL -SHIFTER
20v DENFET DEVICE
Figure 18-13 shows the block diagram of VBUS_DISCHG block, which has 20-V drain extended NFET connected from VBUS supply to ground. The level shifted version of dischg_en controls the gate of the 20-V NFET after level shifted to VPUMP domain.
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18.4.12 CHGDET Block
18.4.12.1 CHGDET Block's Brief Architecture & Functional Description
Figure 18-14. Block Diagram of CHGDET Block
Figure 18-14 shows the CHGDET Block's top level architecture diagram. This block implements the following:
Charger detection circuit which is compliant to BC 1.2 specification. The charger detect block diagram is shown in Figure 18-15 which is part of the above architecture.
Figure 18-15. BC1.2 Charger Detect and Termination
vddd
vbg
+
-
600mV + -
Vdp_src /Vdm_src
10µA Idp_src
dp
325mV / Vdat_ref
dm
-
+
Ip u_ e n v_ d e te ct_ e n
v _src_en_dp/dm e n a b le_ ch g r d e t
i_ p d_ e n_ d p/ d m
Control Logic
100µA Idp_sink Idm_sink
dp/dm _vdet_out
A unity gain voltage buffer drives a voltage divider resistor chain with the bandgap voltage. The voltage divider produces a 600-mV reference to drive a voltage out onto datap or datan (Vdp_src/Vdm_src). The 325-mV reference is used for the comparator to detect Vdat_ref on datap or datan, which produces the chgrdet_out output signal. A 10-µA current source is used for the Idp_src source for data contact
detect. Two 100 µA current sources are used for the Idp_sink and Idm_sink sources for primary and secondary detection.
It also implements the various apple charger terminations and apple charger detection circuits. Figure 18-16 shows the apple termination implementation diagram.
Figure 18-16. Apple Terminations
apple_en_1a_2a_dp/dm apple_en
apple_enb_2a_dp/dm
apple_enb_1a_dp/dm
vbus_app
vbus_app
vbus_app
vbus_app
apple_enb_1a_dm apple_enb_2a_dm
apple_enb_2a_dp apple_enb_1a_dm
75k
47k apple_en
43k dm
75k
47k apple_en
43k dp
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The CHGDET block also implements Qualcomm charger terminations and charger detection circuit which is compliant to Qualcomm Quick Charge 2.0. Figure 18-17 shows the Qualcomm termination resistors.
Figure 18-17. Qualcomm Terminations
vbus_app
Portable device Termination
vbus_app
dm_pu_en
dp_pu_en
RDP_UP dm
dm_pd_en
RDM_DWN
dm_rdat_lk g_en
RDAT_LKG
RDP_UP dp
dp_pd_en
RDM _DWN
RDAT_LKG
dp_rdat_lk g_en
HVDCP Termination
When this block is used as Portable device then portable device terminations are used and when it is used as a HVDCP (High voltage dedicated charging port) then pull down terminations which are shown in Figure 18-17 are used.
According to Qualcomm quick charge 2.0 spec to detect Qualcomm terminations two comparators are needed with trip points of 0.375 V and 2 V. In the architecture shown in the Figure 18-17, there is a comparator with one input is connected to either dp/dm and other end is connected to configurable input where 0.375-V and 2-V inputs can be fed.
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18.4.13 ADC Block
18.4.13.1 ADC Block's Brief Architecture & Functional Description
This block contains the analog circuitry necessary to implement an 8-bit SAR (Successive Approximation Register) ADC (Analog to Digital Converter). The block contents are: Control logic for level shifting and power down, 8-bit DAC, DFT Switch, Comparator (COMP), and a BJT NPN device. These blocks are referenced to the Block Diagram in Figure 18-18.
The DAC takes an 8-bit control signal and outputs a voltage referenced to the supply voltage. The comparator (COMP) compares the DAC voltage versus one of the following input voltages: either the amux_a or amux_b line, the bandgap voltage (vbg), or the voltage generated from sourcing current into a diode-connected BJT NPN device. If the DAC voltage potential is greater than the muxed voltage, then the comparator digital output is high.
The DFT block contains an isolating switch that connects the DAC output voltage to the chip's ADFT network. The switch is closed when the dft_muxsel signal is high.
Figure 18-18. Block Diagram of ADC Block
pd_lv id_sel<1:0>
enable_hv iso_n
Control
dft_muxsel
iref
DFT
dft_mux1
dac_cntrl<7:0>
vbg ana_in1 ana_in2
DAC
iref_int
BJT
+ - COMP
cmp_out
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Section G: Program and Debug
This section encompasses the following chapters: Program and Debug Interface chapter on page 189 Nonvolatile Memory Programming chapter on page 197
Top Level Architecture
Program and Debug Block Diagram
PROGRAM AND DEBUG
Program
Debug and Trace
System Bus
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19. Program and Debug Interface
The CCG3 Program and Debug interface provides a communication gateway for an external device to perform programming or debugging. The external device can be a Cypress-supplied programmer and debugger, or a third-party device that supports CCG3 programming and debugging. The serial wire debug (SWD) interface is used as the communication protocol between the external device and CCG3.
19.1 Features
Programming and debugging through the SWD interface Four hardware breakpoints and two hardware watchpoints while debugging Read and write access to all memory and registers in the system while debugging, including the Cortex-M0 register bank
when the core is running or halted
19.2 Functional Description
Figure 19-1 shows the block diagram of the program and debug interface in CCG3. The Cortex-M0 debug and access port (DAP) acts as the program and debug interface. The external programmer or debugger, also known as the "host", communicates with the DAP of the CCG3 "target" using the two pins of the SWD interface - the bidirectional data pin (SWDIO) and the host-driven clock pin (SWDCK). The SWD physical port pins (SWDIO and SWDCK) communicate with the DAP through the high-speed I/O matrix (HSIOM). See the I/O System chapter on page 49 for details on HSIOM.
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SWDCK Host Device
SWDIO
HSIOM
Figure 19-1. Program and Debug Interface CCG3
ARM Cortex-M0 subsystem
Cortex-M0 DAP
SWD
Debug Port (DP)
AP Access AHB
Access Port (AP)
Cortex-M0 CPU
DAP AHB
AHB
AHB
SPC Interface
FLASH
SROM
SRAM
Peripheral Modules
The DAP communicates with the Cortex-M0 CPU using the ARM-specified advanced high-performance bus (AHB) interface. AHB is the systems interconnect protocol used inside CCG3, which facilitates memory and peripheral register access by the AHB master. CCG3 has two AHB masters ARM CM0 CPU core and DAP. The external device can effectively take control of the entire device through the DAP to perform programming and debugging operations.
Figure 19-2 shows the timing diagrams of read and write SWD packets.
19.3 Serial Wire Debug (SWD)
Interface
CCG3's Cortex-M0 supports programming and debugging through the SWD interface. The SWD protocol is a packetbased serial transaction protocol. At the pin level, it uses a single bidirectional data signal (SWDIO) and a unidirectional clock signal (SWDCK). The host programmer always drives the clock line, whereas either the host or the target drives the data line. A complete data transfer (one SWD packet) requires 46 clocks and consists of three phases:
Host Packet Request Phase The host issues a request to the CCG3 target.
Target Acknowledge Response Phase The CCG3 target sends an acknowledgement to the host.
Data Transfer Phase The host or target writes data to the bus, depending on the direction of the transfer.
When control of the SWDIO line passes from the host to the target, or vice versa, there is a turnaround period (Trn) where neither device drives the line and it floats in a highimpedance (Hi-Z) state. This period is either one-half or one and a half clock cycles, depending on the transition.
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Figure 19-2. SWD Write and Read Packet Timing Diagrams SWD Write Packet
SWDCK SWDIO
A[2:3]
...
...
1
0
0
...
ACK[0:2]
Start (1) APnDP RnW (0) Parity Stop (0) Park (1) Trn (Hi-Z) Trn (Hi-Z) wdata[0] wdata[1] wdata[31] Parity
Host Packet Request Phase
Target ACK Phase
Host Data Transfer Phase
SWD Read Packet
SWDCK SWDIO
A[2:3]
...
...
1
0
0
...
ACK[0:2]
Start (1) APnDP RnW (1) Parity Stop (0) Park (1) Trn (Hi-Z) rdata[0] rdata[1] rdata[31] Parity Trn (Hi-Z)
Host Packet Request Phase
Target ACK and Data Transfer Phases
The sequence to transmit SWD read and write packets are as follows:
1. Host Packet Request Phase: SWDIO driven by the host
a. The start bit initiates a transfer; it is always logic 1.
b. The "AP not DP" (APnDP) bit determines whether the transfer is an AP access 1b1 or a DP access 1b0.
c. The "Read not Write" bit (RnW) controls which direction the data transfer is in. 1b1 represents a `read from' the target, or 1b0 for a `write to' the target.
d. The Address bits (A[3:2]) are register select bits for AP or DP, depending on the APnDP bit value. See Table 19-3 and Table 19-4 for definitions. Note Address bits are transmitted with the LSB first.
e. The parity bit contains the parity of APnDP, RnW, and ADDR bits. It is an even parity bit; this means, when XORed with the other bits, the result will be 0.
If the parity bit is not correct, the header is ignored by CCG3; there is no ACK response (ACK = 3b111). The programming operation should be aborted and retried again by following a device reset.
f. The stop bit is always logic 0.
g. The park bit is always logic 1.
2. Target Acknowledge Response Phase: SWDIO driven by the target
a. The ACK[2:0] bits represent the target to host response, indicating failure or success, among other results. See Table 19-2 for definitions. Note ACK bits are transmitted with the LSB first.
3. Data Transfer Phase: SWDIO driven by either target or host depending on direction
a. The data for read or write is written to the bus, LSB first.
b. The data parity bit indicates the parity of the data read or written. It is an even parity; this means when XORed with the data bits, the result will be 0.
If the parity bit indicates a data error, corrective action should be taken. For a read packet, if the host detects a parity error, it must abort the programming operation and restart. For a write packet, if the target detects a parity error, it generates a FAULT ACK response in the next packet.
According to the SWD protocol, the host can generate any number of SWDCK clock cycles between two packets with SWDIO low. It is recommended to generate three or more dummy clock cycles between two SWD packets if the clock is not free-running or to make the clock free-running in IDLE mode.
The SWD interface can be reset by clocking the SWDCK line for 50 or more cycles with SWDIO high. To return to the idle state, clock the SWDIO low once.
19.3.1 SWD Timing Details
The SWDIO line is written to and read at different times depending on the direction of communication. The host drives the SWDIO line during the Host Packet Request Phase and, if the host is writing data to the target, during the Data Transfer phase as well. When the host is driving the SWDIO line, each new bit is written by the host on falling
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SWDCK edges, and read by the target on rising SWDCK edges. The target drives the SWDIO line during the Target Acknowledge Response Phase and, if the target is reading out data, during the Data Transfer Phase as well. When the target is driving the SWDIO line, each new bit is written by the target on rising SWDCK edges, and read by the host on falling SWDCK edges.
Table 19-1 and Figure 19-2 illustrate the timing of SWDIO bit writes and reads.
Table 19-1. SWDIO Bit Write and Read Timing
SWD Packet Phase
Host Packet Request Host Data Transfer Target Ack Response Target Data Transfer
SWDIO Edge
Falling
Rising
Host Write
Target Read
Host Read
Target Write
19.3.2 ACK Details
The acknowledge (ACK) bit-field is used to communicate the status of the previous transfer. OK ACK means that previous packet was successful. A WAIT response requires a data phase. For a FAULT status, the programming operation should be aborted immediately. Table 19-2 shows the ACK bit-field decoding details.
Table 19-2. SWD Transfer ACK Response Decoding
Response OK WAIT FAULT NO ACK
3b001 3b010 3b100 3b111
ACK[2:0]
Details on WAIT and FAULT response behaviors are as follows:
For a WAIT response, if the transaction is a read, the host should ignore the data read in the data phase. The target does not drive the line and the host must not check the parity bit as well.
For a WAIT response, if the transaction is a write, the data phase is ignored by the CCG3. But, the host must still send the data to be written to complete the packet. The parity bit corresponding to the data should also be sent by the host.
For a WAIT response, it means that the CCG3 is processing the previous transaction. The host can try for a maximum of four continuous WAIT responses to see if an OK response is received. If it fails, then the programming operation should be aborted and retried again.
For a FAULT response, the programming operation should be aborted and retried again by doing a device reset.
19.3.3 Turnaround (Trn) Period Details
There is a turnaround period between the packet request and the ACK phases, as well as between the ACK and the data phases for host write transfers, as shown in Figure 19-2. According to the SWD protocol, the Trn period is used by both the host and target to change the drive modes on their respective SWDIO lines. During the first Trn period after the packet request, the target starts driving the ACK data on the SWDIO line on the rising edge of SWDCK. This ensures that the host can read the ACK data on the next falling edge. Thus, the first Trn period lasts only onehalf cycle. The second Trn period of the SWD packet is one and a half cycles. Neither the host nor CCG3 should drive the SWDIO line during the Trn period.
19.4 Cortex-M0 Debug and
Access Port (DAP)
The Cortex-M0 program and debug interface includes a Debug Port (DP) and an Access Port (AP), which combine to form the DAP. The debug port implements the state machine for the SWD interface protocol that enables communication with the host device. It also includes registers for the configuration of access port, DAP identification code, and so on. The access port contains registers that enable the external device to access the Cortex-M0 DAP-AHB interface. Typically, the DP registers are used for a one time configuration or for error detection purposes, and the AP registers are used to perform the programming and debugging operations. Complete architecture details of the DAP is available in the ARM® Debug Interface v5 Architecture Specification.
19.4.1 Debug Port (DP) Registers
Table 19-3 shows the Cortex-M0 DP registers used for programming and debugging, along with the corresponding SWD address bit selections. The APnDP bit is always zero for DP register accesses. Two address bits (A[3:2]) are used for selecting among the different DP registers. Note that for the same address bits, different DP registers can be accessed depending on whether it is a read or a write operation. See the ARM® Debug Interface v5 Architecture Specification for details on all of the DP registers.
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Table 19-3. Main Debug Port (DP) Registers
Register APnDP
ABORT
0 (DP)
IDCODE
0 (DP)
CTRL/STAT 0 (DP)
SELECT RDBUFF
0 (DP) 0 (DP)
Address A[3:2] 2b00
2b00
2b01
2b10 2b11
RnW
Full Name
Register Functionality
0 (W) AP Abort Register
This register is used to force a DAP abort and to clear the error and sticky flag conditions.
1 (R)
Identification Code Register
This register holds the SWD ID of the Cortex-M0 CPU, which is 0x0BB11477.
X (R/W)
Control and Status Register
This register allows control of the DP and contains status information about the DP.
0 (W) AP Select Register This register is used to select the current AP. In CCG3, there
is only one AP, which interfaces with the DAP AHB.
1 (R) Read Buffer Register This register holds the result of the last AP read operation.
19.4.2 Access Port (AP) Registers
Table 19-4 lists the main Cortex-M0 AP registers that are used for programming and debugging, along with the corresponding SWD address bit selections. The APnDP bit is always one for AP register accesses. Two address bits (A[3:2]) are used for selecting the different AP registers.
Table 19-4. Main Access Port (AP) Registers
Register APnDP
CSW
1 (AP)
TAR DRW
1 (AP) 1 (AP)
Address A[3:2] 2b00
2b01 2b11
RnW
Full Name
Register Functionality
Control and Status X (R/W) Word Register
(CSW)
This register configures and controls accesses through the memory access port to a connected memory system (which is
the CCG3 Memory map)
X (R/W)
Transfer Address Register
This register is used to specify the 32-bit memory address to be read from or written to
X (R/W)
Data Read and Write Register
This register holds the 32-bit data read from or to be written to the address specified in the TAR register
19.5 Programming the CCG3 Device
CCG3 is programmed using the following sequence. Refer to the CCG3 Device Programming Specifications for complete details on the programming algorithm, timing specifications, and hardware configuration required for programming. 1. Acquire the SWD port in CCG3. 2. Enter the programming mode. 3. Execute the device programming routines such as Sili-
con ID Check, Flash Programming, Flash Verification, and Checksum Verification.
19.5.1 SWD Port Acquisition
19.5.1.1 Primary and Secondary SWD Pin Pairs
The first step in device programming is to acquire the SWD port in CCG3. Refer to the CCG3 device datasheet for information on SWD pins.
19.5.1.2 SWD Port Acquire Sequence
The first step in device programming is for the host to acquire the target's SWD port. The host first performs a device reset by asserting the external reset (XRES) pin. After removing the XRES signal, the host must send an SWD connect sequence for the device within the acquire window to connect to the SWD interface in the DAP. The pseudo code for the sequence is given here. Code 1. SWD Port Acquire Pseudo Code
ToggleXRES(); // Toggle XRES pin to reset device
//Execute ARM's connection sequence to acquire SWD-port do
{
SWD_LineReset(); //perform a line reset (50+ SWDCK clocks with SWDIO high)
ack = Read_DAP ( IDCODE, out ID); //Read the IDCODE DP register
}while ((ack != OK) && time_elapsed < 2 ms); // retry connection until OK ACK or timeout
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if (time_elapsed >= 2 ms) return FAIL; //check for acquire time out
if (ID != CM0_ID) return FAIL; //confirm SWD ID of Cortex-M0 CPU. (0x0BB11477)
In this pseudo code, SWD_LineReset() is the standard ARM command to reset the debug access port. It consists of more than 49 SWDCK clock cycles with SWDIO high. The transaction must be completed by sending at least one SWDCK clock cycle with SWDIO asserted LOW. This sequence synchronizes the programmer and the chip. Read_DAP() refers to the read of the IDCODE register in the debug port. The sequence of line reset and IDCODE read should be repeated until an OK ACK is received for the IDCODE read or a timeout (2 ms) occurs. The SWD port is said to be in the acquired state if an OK ACK is received within the time window and the IDCODE read matches with that of the CortexM0 DAP.
19.5.2 SWD Programming Mode Entry
After the SWD port is acquired, the host must enter the device programming mode within a specific time window. This is done by setting the TEST_MODE bit (bit 31) in the test mode control register (MODE register). The debug port should also be configured before entering the device programming mode. Timing specifications and pseudo code for entering the programming mode are detailed in the CCG3 Device Programming Specifications document.
19.5.3 SWD Programming Routines Executions
When the device is in programming mode, the external programmer can start sending the SWD packet sequence for performing programming operations such as flash erase, flash program, checksum verification, and so on. The programming routines are explained in the Nonvolatile Memory Programming chapter on page 197. The exact sequence of calling the programming routines is given in the CCG3 Device Programming Specifications document.
19.6 CCG3 SWD Debug Interface
Cortex-M0 DAP debugging features are classified into two types: invasive debugging and noninvasive debugging. Invasive debugging includes program halting and stepping, breakpoints, and data watchpoints. Noninvasive debugging includes instruction address profiling and device memory access, which includes the flash memory, SRAM, and other peripheral registers.
The DAP has three major debug subsystems:
Debug Control and Configuration registers
Breakpoint Unit (BPU) provides breakpoint support
Debug Watchpoint (DWT) provides watchpoint support. Trace is not supported in Cortex-M0 Debug.
See the ARMv6-M Architecture Reference Manual for complete details on the debug architecture.
19.6.1 Debug Control and Configuration Registers
The debug control and configuration registers are used to execute firmware debugging. The registers and their key functions are as follows. See the ARMv6-M Architecture Reference Manual for complete bit level definitions of these registers.
Debug Halting Control and Status Register (CM0_DHCSR) This register contains the control bits to enable debug, halt the CPU, and perform a singlestep operation. It also includes status bits for the debug state of the processor.
Debug Fault Status Register (CM0_DFSR) This register describes the reason a debug event has occurred. This includes debug events, which are caused by a CPU halt, breakpoint event, or watchpoint event.
Debug Core Register Selector Register (CM0_DCRSR) This register is used to select the general-purpose register in the Cortex-M0 CPU to which a read or write operation must be performed by the external debugger.
Debug Core Register Data Register (CM0_DCRDR) This register is used to store the data to write to or read from the register selected in the CM0_DCRSR register.
Debug Exception and Monitor Control Register (CM0_DEMCR) This register contains the enable bits for global debug watchpoint (DWT) block enable, reset vector catch, and hard fault exception catch.
19.6.2 Breakpoint Unit (BPU)
The BPU provides breakpoint functionality on instruction fetches. The Cortex-M0 DAP in CCG3 supports up to four hardware breakpoints. Along with the hardware breakpoints, any number of software breakpoints can be created by using the BKPT instruction in the Cortex-M0. The BPU has two types of registers.
The breakpoint control register (CM0_BP_CTRL) is used to enable the BPU and store the number of hardware breakpoints supported by the debug system (four for CM0 DAP in CCG3).
Each hardware breakpoint has a Breakpoint Compare Register (CM0_BP_COMPx). It contains the enable bit for the breakpoint, the compare address value, and the match condition that will trigger a breakpoint debug event. The typical use case is that when an instruction fetch address matches the compare address of a breakpoint, a breakpoint event is generated and the processor is halted.
19.6.3 Data Watchpoint (DWT)
The DWT provides watchpoint support on a data address access or a program counter (PC) instruction address. Trace is not supported by the Cortex-M0 in CCG3. The DWT supports two watchpoints. It also provides external program counter sampling using a PC sample register, which can be used for noninvasive coarse profiling of the
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program counter. The most important registers in the DWT are as follows.
The watchpoint compare (CM0_DWT_COMPx) registers store the compare values that are used by the watchpoint comparator for the generation of watchpoint events. Each watchpoint has an associated DWT_COMPx register.
The watchpoint mask (CM0_DWT_MASKx) registers store the ignore masks applied to the address range matching in the associated watchpoints.
The watchpoint function (CM0_DWT_FUNCTIONx) registers store the conditions that trigger the watchpoint events. They may be program counter watchpoint event or data address read/write access watchpoint events. A status bit is also set when the associated watchpoint event has occurred.
The watchpoint comparator PC sample register (CM0_DWT_PCSR) stores the current value of the program counter. This register is used for coarse, non-invasive profiling of the program counter register.
19.6.4 Debugging the CCG3 Device
The host debugs the target CCG3 device by accessing the debug control and configuration registers, registers in the BPU, and registers in the DWT. All registers are accessed through the SWD interface; the SWD debug port (SW-DP) in the Cortex-M0 DAP converts the SWD packets to appropriate register access through the DAP-AHB interface.
The first step in debugging the target CCG3 device is to acquire the SWD port. The acquire sequence consists of an SWD line reset sequence and read of the DAP SWDID through the SWD interface. The SWD port is acquired when the correct CM0 DAP SWDID is read from the target device. For the debug transactions to occur on the SWD interface, the corresponding pins should not be used for any other purpose. See the I/O System chapter on page 49 to understand how to configure the SWD port pins, allowing them to be used only for SWD interface or for other functions such as GPIO. If debugging is required, the SWD port pins should not be used for other purposes. If only programming support is needed, the SWD pins can be used for other purposes.
When the SWD port is acquired, the external debugger sets the C_DEBUGEN bit in the DHCSR register to enable debugging. Then, the different debugging operations such as stepping, halting, breakpoint configuration, and watchpoint configuration are carried out by writing to the appropriate registers in the debug system.
Debugging the target device is also affected by the overall device protection setting, which is explained in the Device Security chapter on page 75. Only the OPEN protected mode supports device debugging. The external debugger and the target device connection is not lost for a device transition from Active mode to either Sleep or Deep-Sleep modes. When the device enters the Active mode from either Deep-Sleep or Sleep modes, the debugger can resume its actions without initiating a connect sequence again.
19.7 Registers
Table 19-5. List of Registers
Register Name
Description
CM0_DHCSR
Debug Halting Control and Status Register
CM0_DFSR
Debug Fault Status Register
CM0_DCRSR
Debug Core Register Selector Register
CM0_DCRDR
Debug Core Register Data Register
CM0_DEMCR
Debug Exception and Monitor Control Register
CM0_BP_CTRL
Breakpoint control register
CM0_BP_COMPx
Breakpoint Compare Register
CM0_DWT_COMPx
Watchpoint Compare Register
CM0_DWT_MASKx
Watchpoint Mask Register
CM0_DWT_FUNCTIONx Watchpoint Function Register
CM0_DWT_PCSR
Watchpoint Comparator PC Sample Register
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20. Nonvolatile Memory Programming
Nonvolatile memory programming refers to the programming of flash memory in the CCG3 device. This chapter explains the different functions that are part of device programming, such as erase, write, program, and checksum calculation. Cypresssupplied programmers and other third-party programmers can use these functions to program the CCG3 device with the data in an application hex file. They can also be used to perform bootload operations where the CPU will update a portion of the flash memory.
20.1 Features
Supports programming through the debug and access port (DAP) and Cortex-M0 CPU Supports both blocking and non-blocking flash program and erase operations from the Cortex-M0 CPU
20.2 Functional Description
Flash programming operations are implemented as system calls. System calls are executed out of SROM in the privileged mode of operation. The user has no access to read or modify the SROM code. The DAP or the CM0 CPU requests the system call by writing the function opcode and parameters to the System Performance Controller Interface (SPCIF) input registers, and then requesting the SROM to execute the function. Based on the function opcode, the System Performance Controller (SPC) executes the corresponding system call from SROM and updates the SPCIF status register. The DAP or the CPU should read this status register for the pass/fail result of the function execution. As part of function execution, the code in SROM interacts with the SPCIF to do the actual flash programming operations. CCG3 flash is programmed using a Program Erase Program (PEP) sequence. The flash cells are all programmed to a known state, erased, and then the selected bits are programmed. This increases the life of the flash by balancing the stored charge. When writing to flash the data is first copied to a page latch buffer. The flash write functions are then used to transfer this data to flash. External programmers program the flash memory in CCG3 using the SWD protocol by sending the commands to the Debug and Access Port (DAP). The programming sequence for the CCG3 device with an external programmer is given in the CCG3 Device Programming Specifications . Flash memory can also be programmed by the CM0 CPU by accessing the relevant registers through the AHB interface. This type of programming is typically used to update a portion of the flash memory as part of a bootload operation, or other application requirements, such as updating a lookup table stored in the flash memory. All write operations to flash memory, whether from the DAP or from the CPU, are done through the SPCIF. Note It can take as much as 20 milliseconds to write to flash. During this time, the device should not be reset, or unexpected changes may be made to portions of the flash. Reset sources (see the Reset System chapter on page 73) include XRES pin, software reset, and watchdog; make sure that these are not inadvertently activated. In addition, the low-voltage detect circuits should be configured to generate an interrupt instead of a reset.
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20.3 System Call Implementation
A system call consists of the following items:
Opcode: A unique 8-bit opcode
Parameters: Two 8-bit parameters are mandatory for all system calls. These parameters are referred to as key1 and key2, and are defined as follows:
key1 = 0xB6
key2 = 0xD3 + Opcode
The two keys are passed to ensure that the user system call is not initiated by mistake. If the key1 and key2 parameters are not correct, the SROM does not execute the function, and returns an error code. Apart from these two parameters, additional parameters may be required depending on the specific function being called.
Return Values: Some system calls also return a value on completion of their execution, such as the silicon ID or a checksum.
Completion Status: Each system call returns a 32-bit status that the CPU or DAP can read to verify success or determine the reason for failure.
20.4 Blocking and Non-Blocking
System Calls
System call functions can be categorized as blocking or non-blocking based on the nature of their execution. Blocking system calls are those where the CPU cannot execute any other task in parallel other than the execution of the system call. When a blocking system call is called from a process, the CPU jumps to the code corresponding in SROM. When the execution is complete, the original thread execution resumes. Non-blocking system calls allow the CPU to execute some other code in parallel and communicate the completion of interim system call tasks to the CPU through an interrupt.
Non-blocking system calls are only used when the CPU initiates the system call. The DAP will only use system calls during the programming mode and the CPU is halted during this process.
The three non-blocking system calls are Non-Blocking Write Row, Non-Blocking Program Row, and Resume Non-Blocking, respectively. All other system calls are blocking.
Because the CPU cannot execute code from flash while doing an erase or program operation on the flash, the nonblocking system calls can only be called from a code executing out of SRAM. If the non-blocking functions are called from flash memory, the result is undefined and may return a bus error and trigger a hard fault when the flash fetch operation is being done.
The System Performance Controller (SPC) is the block that generates the properly sequenced high-voltage pulses required for erase and program operations of the flash memory. When a non-blocking function is called from SRAM, the SPC timer triggers its interrupt when each of the sub-operations in a write or program operation is complete. Call the
Resume Non-Blocking function from the SPC interrupt service routine (ISR) to ensure that the subsequent steps in the system call are completed. Because the CPU can execute code only from the SRAM when a non-blocking write or program operation is being done, the SPC ISR should also be located in the SRAM. The SPC interrupt is triggered once in the case of a non-blocking program function or thrice in a non-blocking write operation. The Resume Non-Blocking function call done in the SPC ISR is called once in a nonblocking program operation and thrice in a non-blocking write operation.
The pseudo code for using a non-blocking write system call and executing user code out of SRAM is given later in this chapter.
20.4.1 Performing a System Call
The steps to initiate a system call are as follows:
1. Set up the function parameters: The two possible methods for preparing the function parameters (key1, key2, additional parameters) are:
a. Write the function parameters to the CPUSS_SYSARG register: This method is used for functions that retrieve their parameters from the CPUSS_SYSARG register. The 32-bit CPUSS_SYSARG register must be written with the parameters in the sequence specified in the respective system call table.
b. Write the function parameters to SRAM: This method is used for functions that retrieve their parameters from SRAM. The parameters should first be written in the specified sequence to consecutive SRAM locations. Then, the starting address of the SRAM, which is the address of the first parameter, should be written to the CPUSS_SYSARG register. This starting address should always be a word-aligned (32-bit) address. The system call uses this address to fetch the parameters.
2. Specify the system call using its opcode and initiating the system call: The 8-bit opcode should be written to the SYSCALL_COMMAND bits ([15:0]) in the CPUSS_SYSREQ register. The opcode is placed in the lower eight bits [7:0] and 0x00 be written to the upper eight bits [15:8]. To initiate the system call, set the SYSCALL_REQ bit (31) in the CPUSS_SYSREG register. Setting this bit triggers a non-maskable interrupt that jumps the CPU to the SROM code referenced by the opcode parameter.
3. Wait for the system call to finish executing: When the system call begins execution, it sets the PRIVILEGED bit in the CPUSS_SYSREQ register. This bit can be set only by the system call, not by the CPU or DAP. The DAP should poll the PRIVILEGED and SYSCALL_REQ bits in the CPUSS_SYSREG register continuously to check whether the system call is completed. Both these bits are cleared on completion of the system call. The maximum execution time is one second. If these two bits are not cleared after one second, the operation should be considered a failure and aborted without executing the following steps. Note that unlike the DAP, the CPU application code cannot poll these bits during system call
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execution. This is because the CPU executes code out of the SROM during the system call. The application code can check only the final function pass/fail status after the execution returns from SROM.
4. Check the completion status: After the PRIVILEGED and SYSCALL_REQ bits are cleared to indicate completion of the system call, the CPUSS_SYSARG register should be read to check for the status of the system call. If the 32-bit value read from the CPUSS_SYSARG register is
0xAXXXXXXX (where `X' denotes don't care hex values), the system call was successfully executed. For a failed system call, the status code is 0xF00000YY where YY indicates the reason for failure. See Table 20-1 for the complete list of status codes and their description.
5. Retrieve the return values: For system calls that return values such as silicon ID and checksum, the CPU or DAP should read the CPUSS_SYSREG and CPUSS_SYSARG registers to fetch the values returned.
20.5 System Calls
Table 20-1 lists all the system calls supported in CCG3 along with the function description and availability in device protection modes. See the Device Security chapter on page 75 for more information on the device protection settings. Note that some system calls cannot be called by the CPU as given in the table. Detailed information on each of the system calls follows the table.
Table 20-1. List of System Calls
System Call
Description
DAP Access Open Protected Kill
Silicon ID
Returns the device Silicon ID, Family ID, and Revision ID
Load Flash Bytes
Loads data to the page latch buffer to be programmed later into the flash row, in 1 byte granularity, for a row size of 64 bytes
Write Row
Erases and then programs a row of flash with data in the page latch buffer
Program Row
Programs a row of flash with data in the page latch buffer
Erase All
Erases all user code in the flash array; the flash row-level protection data in the supervisory flash area
Checksum
Calculates the checksum over the entire flash memory (user and supervisory area) or checksums a single row of flash
Write Protection
This programs both flash row-level protection settings and chip-level protection settings into the supervisory flash (row 0)
Erases and then programs a row of flash with data in the page latch buf-
Non-Blocking Write Row fer. During program/erase pulses, the user may execute code from
SRAM. This function is meant only for CPU access
Non-Blocking Program Row
Programs a row of flash with data in the page latch buffer. During program/erase pulses, the user may execute code from SRAM. This function is meant only for CPU access
Resume Non-Blocking
Resumes a non-blocking write row or non-blocking program row. This function is meant only for CPU access
CPU Access
20.5.1 Silicon ID
This function returns a 12-bit family ID, 16-bit silicon ID, and an 8-bit revision ID, and the current device protection mode. These values are returned to the CPUSS_SYSARG and CPUSS_SYSREQ registers. Parameters are passed through the CPUSS_SYSARG and CPUSS_SYSREQ registers.
Parameters
Address
Bits [7:0] Bits [15:8]
0xB6 0xD3
Value to be Written CPUSS_SYSARG Register Key1 Key2
Description
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Address Bits [31:16] CPUSS_SYSREQ register Bits [15:0] Bits [31:16]
Return
0x0000
Value to be Written
0x0000 0x8000
Not used
Description
Silicon ID opcode Set SYSCALL_REQ bit
Address CPUSS_SYSARG register Bits [7:0] Bits [15:8] Bits [19:16] Bits [23:20] Bits [27:24] Bits [31:28] CPUSS_SYSREQ register Bits [11:0] Bits [15:12] Bits [31:16]
Return Value
Silicon ID Lo Silicon ID Hi Minor Revision Id Major Revision Id 0xXX 0xA
Family ID Chip Protection 0xXXXX
Description
See the CCG3 device datasheet for Silicon ID values for different part numbers See the CCG3 Device Programming Specifications for these values Not used (don't care) Success status code
Family ID is 0x093 for CCG3
See the Device Security chapter on page 75 Not used
20.5.2 Configure Clock
This function initializes the clock necessary for flash programming and erasing operations. This API is used to ensure that the charge pump clock (clk_pump) and the HF clock (clk_hf) are set to IMO at 48 MHz prior to calling the flash write and flash erase APIs. The flash write and erase APIs will exit without acting on the flash and return the "Invalid Pump Clock Frequency" status if the IMO is the source of the charge pump clock and is not 48 MHz.
Parameters
Address
Value to be Written
SRAM Address: 32'hYY (32-bit wide, word-aligned SRAM address)
Bits [7:0]
0xB6
Bits [15:8]
0xE8
Bits [31:16]
0xXXXX
CPUSS_SYSARG register
Bits [31:0]
32'hYY
CPUSS_SYSREQ register Bits [15:0] Bits [31:16]
0x0015 0x8000
Return
Description
Key1 Key2 Don't care
32-bit word-aligned address of the SRAM that stores the first function parameter (key1)
Configure clock opcode Set SYSCALL_REQ bit
Address CPUSS_SYSARG register Bits [31:28] Bits [27:0]
Return Value
0xA 0xXXXXXXX
Description
Success status code Not used (don't care)
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20.5.3 Load Flash Bytes
This function loads the page latch buffer with data to be programmed into a row of flash. The load size can range from 1-byte to the maximum number of bytes in a flash row, which is 64 bytes. Data is loaded into the page latch buffer starting at the location specified by the "Byte Addr" input parameter. Data loaded into the page latch buffer remains until a program operation is performed, which clears the page latch contents. The parameters for this function, including the data to be loaded into the page latch, are written to the SRAM; the starting address of the SRAM data is written to the CPUSS_SYSARG register. Note that the starting parameter address should be a word-aligned address.
Parameters
Address
Value to be Written
SRAM Address - 32'hYY (32-bit wide, word-aligned SRAM address)
Bits [7:0]
0xB6
Bits [15:8]
0xD7
Bits [23:16]
Byte Addr
Bits [31:24]
Flash Macro Select
SRAM Address- 32'hYY + 0x04
Bits [7:0]
Load Size
Bits [15:8]
0xXX
Bits [23:16]
0xXX
Bits [31:24]
0xXX
SRAM Address- From (32'hYY + 0x08) to (32'hYY + 0x08 + Load Size)
Byte 0
Data Byte [0]
.
.
.
.
Byte (Load size 1)
Data Byte [Load size 1]
CPUSS_SYSARG register
Bits [31:0]
32'hYY
CPUSS_SYSREQ register Bits [15:0] Bits [31:16]
0x0004 0x8000
Description
Key1 Key2 Start address of page latch buffer to write data 0x00 Byte 0 of latch buffer 0x40 - Byte 64 of latch buffer 0x00 Flash Macro 0 0x01 Flash Macro 1 (Refer to the Cortex-M0 CPU chapter on page 29 for the number of flash macros in the device)
Number of bytes to be written to the page latch buffer. 0x00 1 byte 0x3F - 64 bytes Don't care parameter Don't care parameter Don't care parameter
First data byte to be loaded . . Last data byte to be loaded
32-bit word-aligned address of the SRAM that stores the first function parameter (key1)
Load Flash Bytes opcode Set SYSCALL_REQ bit
Return
Address CPUSS_SYSARG register Bits [31:28] Bits [27:0]
Return Value
0xA 0xXXXXXXX
Description
Success status code Not used (don't care)
20.5.4 Write Row
This function erases and then programs the addressed row of flash with the data in the page latch buffer. If all data in the page latch buffer is 0, then the program is skipped. The parameters for this function are stored in SRAM. The start address of
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the stored parameters is written to the CPUSS_SYSARG register. This function clears the page latch buffer contents after the row is programmed.
Usage Requirements: Call the Configure Clock API before calling this function. The Configure Clock API ensures that the charge pump clock (clk_pump) and the HF clock (clk_hf) are set to IMO at 48 MHz. Call the Load Flash Bytes function before calling this function. This function can do a write operation only if the corresponding flash row is not write protected.
Note that the SROM does not modify, enable, or disable any clock during any flash operation. Refer to the CLK_IMO_CONFIG register in the CCG3 Registers TRM for more information.
Parameters
Address
Value to be Written
SRAM Address: 32'hYY (32-bit wide, word-aligned SRAM address)
Bits [7:0]
0xB6
Bits [15:8]
0xD8
Bits [31:16]
Row ID
CPUSS_SYSARG register
Bits [31:0]
32'hYY
CPUSS_SYSREQ register Bits [15:0] Bits [31:16]
0x0005 0x8000
Description
Key1 Key2 Row number to write 0x0000 Row 0
32-bit word-aligned address of the SRAM that stores the first function parameter (key1)
Write Row opcode Set SYSCALL_REQ bit
Return
Address CPUSS_SYSARG register Bits [31:28] Bits [27:0]
Return Value
0xA 0xXXXXXXX
Description
Success status code Not used (don't care)
20.5.5 Program Row
This function programs the addressed row of the flash, with data in the page latch buffer. If all data in the page latch buffer is 0, then the program is skipped. The row must be in an erased state before calling this function. This clears the page latch buffer contents after the row is programmed.
Usage Requirements: Call the Configure Clock API before calling this function. The Configure Clock API ensures that the charge pump clock (clk_pump) and the HF clock (clk_hf) are set to IMO at 48 MHz. Call the Load Flash Bytes function before calling this function. The row must be in an erased state before calling this function. This function can do a program operation only if the corresponding flash row is not write-protected.
Parameters
Address
Value to be Written
SRAM Address: 32'hYY (32-bit wide, word-aligned SRAM address)
Bits [7:0]
0xB6
Bits [15:8]
0xD9
Bits [31:16]
Row ID
CPUSS_SYSARG register
Description
Key1 Key2 Row number to program 0x0000 Row 0
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Address Bits [31:0] CPUSS_SYSREQ register Bits [15:0] Bits [31:16]
Return
32'hYY
Value to be Written
0x0006 0x8000
Description 32-bit word-aligned address of the SRAM that stores the first function parameter (key1)
Program Row opcode Set SYSCALL_REQ bit
Address CPUSS_SYSARG register Bits [31:28] Bits [27:0]
Return Value
0xA 0xXXXXXXX
Description
Success status code Not used (don't care)
20.5.6 Erase All
This function erases all the user code in the flash main arrays and the row-level protection data in supervisory flash row 0 of each flash macro.
Usage Requirements: Call the Configure Clock API before calling this function. The Configure Clock API ensures that the charge pump clock (clk_pump) and the HF clock (clk_hf) are set to IMO at 48 MHz. This API can be called only from the DAP in the programming mode and only if the chip protection mode is OPEN. If the chip protection mode is PROTECTED, then the Write Protection API must be used by the DAP to change the protection settings to OPEN. Changing the protection setting from PROTECTED to OPEN automatically does an erase all operation.
Parameters
Address
Value to be Written
SRAM Address: 32'hYY (32-bit wide, word-aligned SRAM address)
Bits [7:0]
0xB6
Bits [15:8]
0xDD
Bits [31:16]
0xXXXX
CPUSS_SYSARG register
Bits [31:0]
32'hYY
CPUSS_SYSREQ register Bits [15:0] Bits [31:16]
0x000A 0x8000
Description
Key1 Key2 Don't care
32-bit word-aligned address of the SRAM that stores the first function parameter (key1)
Erase All opcode Set SYSCALL_REQ bit
Return
Address CPUSS_SYSARG register Bits [31:28] Bits [27:0]
Return Value
0xA 0xXXXXXXX
Description
Success status code Not used (don't care)
20.5.7 Checksum
This function reads either the whole flash memory or a row of flash and returns the 24-bit sum of each byte read in that flash region. When performing a checksum on the whole flash, the user code and supervisory flash regions are included. When performing a checksum only on one row of flash, the flash row number is passed as a parameter. Bytes 2 and 3 of the parameters select whether the checksum is performed on the whole flash memory or a row of user code flash.
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Parameters
Address CPUSS_SYSARG register Bits [7:0] Bits [15:8]
Value to be Written
0xB6 0xDE
Bits [31:16]
Row ID
CPUSS_SYSREQ register Bits [15:0] Bits [31:16]
0x000B 0x8000
Return
Description
Key1 Key2 Selects the flash row number on which the checksum operation is done Row number 16 bit flash row number or 0x8000 Checksum is performed on entire flash memory
Checksum opcode Set SYSCALL_REQ bit
Address CPUSS_SYSARG register Bits [31:28] Bits [27:24] Bits [23:0]
Return Value
0xA 0xX Checksum
Description
Success status code Not used (don't care) 24-bit checksum value of the selected flash region
20.5.8 Write Protection
This function programs both the flash row-level protection settings and the device protection settings in the supervisory flash row. The flash row-level protection settings are programmed separately for each flash macro in the device. Each row has a single protection bit. The total number of protection bytes is the number of flash rows divided by eight. The chip-level protection settings (1-byte) are stored in flash macro zero in the last byte location in row zero of the supervisory flash. The size of the supervisory flash row is the same as the user code flash row size.
Usage Requirements: Call the Configure Clock API before calling this function. The Configure Clock API ensures that the charge pump clock (clk_pump) and the HF clock (clk_hf) are set to IMO at 48 MHz. The Load Flash Bytes function is used to load the flash protection bytes of a flash macro into the page latch buffer corresponding to the macro. The starting address parameter for the load function should be zero. The flash macro number should be one that needs to be programmed; the number of bytes to load is the number of flash protection bytes in that macro.
Then, the Write Protection function is called, which programs the flash protection bytes from the page latch to be the corresponding flash macro's supervisory row. In flash macro zero, which also stores the device protection settings, the device level protection setting is passed as a parameter in the CPUSS_SYSARG register.
Parameters
Address CPUSS_SYSARG register Bits [7:0] Bits [15:8]
Value to be Written
0xB6 0xE0
Bits [23:16]
Device Protection Byte
Description
Key1 Key2 Parameter applicable only for Flash Macro 0 0x01 OPEN mode 0x02 PROTECTED mode 0x04 KILL mode
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Address Bits [31:24] CPUSS_SYSREQ register Bits [15:0] Bits [31:16]
Return
Value to be Written Flash Macro Select
0x000D 0x8000
0x00 Flash Macro 0 0x01 Flash Macro 1
Description
Write Protection opcode Set SYSCALL_REQ bit
Address CPUSS_SYSARG register Bits [31:28] Bits [27:24] Bits [23:0]
Return Value
0xA 0xX 0x000000
Success status code Not used (don't care)
Description
20.5.9 Non-Blocking Write Row
This function is used when a flash row needs to be written by the CM0 CPU in a non-blocking manner, so that the CPU can execute code from SRAM while the write operation is being done. The explanation of non-blocking system calls is explained in Blocking and Non-Blocking System Calls on page 198.
The non-blocking write row system call has three phases: Pre-program, Erase, Program. Pre-program is the step in which all of the bits in the flash row are written a `1' in preparation for an erase operation. The erase operation clears all of the bits in the row, and the program operation writes the new data to the row.
While each phase is being executed, the CPU can execute code from SRAM. When the non-blocking write row system call is initiated, the user cannot call any system call function other than the Resume Non-Blocking function, which is required for completion of the non-blocking write operation. After the completion of each phase, the SPC triggers its interrupt. In this interrupt, call the Resume Non-Blocking system call.
Usage Requirements: Call the Configure Clock API before calling this function. The Configure Clock API ensures that the charge pump clock (clk_pump) and the HF clock (clk_hf) are set to IMO at 48 MHz.
Note The device firmware must not attempt to put the device to sleep during a non-blocking write row. This will reset the page latch buffer and the flash will be written with all zeroes.
Call the Load Flash Bytes function before calling this function to load the data bytes that will be used for programming the row. In addition, the non-blocking write row function can be called only from the SRAM. This is because the CM0 CPU cannot execute code from flash while doing the flash erase program operations. If this function is called from the flash memory, the result is undefined, and may return a bus error and trigger a hard fault when the flash fetch operation is being done.
Parameters
Address
Value to be Written
Description
SRAM Address 32'hYY (32-bit wide, word-aligned SRAM address)
Bits [7:0]
0xB6
Key1
Bits [15:8]
0xDA
Key2
Bits [31:16]
Row ID
Row number to write 0x0000 Row 0
CPUSS_SYSARG register
Bits [31:0]
32'hYY
32-bit word-aligned address of the SRAM that stores the first function parameter (key1)
CPUSS_SYSREQ register
Bits [15:0]
0x0007
Non-Blocking Write Row opcode
Bits [31:16]
0x8000
Set SYSCALL_REQ bit
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Return
Address CPUSS_SYSARG register Bits [31:28] Bits [27:0]
Return Value
0xA 0xXXXXXXX
Description
Success status code Not used (don't care)
20.5.10 Non-Blocking Program Row
This function is used when a flash row needs to be programmed by the CM0 CPU in a non-blocking manner, so that the CPU can execute code from the SRAM when the program operation is being done. The explanation of non-blocking system calls is explained in Blocking and Non-Blocking System Calls on page 198. While the program operation is being done, the CPU can execute code from the SRAM. When the non-blocking program row system call is called, the user cannot call any other system call function other than the Resume Non-Blocking function, which is required for the completion of the non-blocking write operation.
Unlike the Non-Blocking Write Row system call, the Program system call only has a single phase. Therefore, the Resume Non-Blocking function only needs to be called once from the SPC interrupt when using the Non-Blocking Program Row system call.
Usage Requirements: Call the Configure Clock API before calling this function. The Configure Clock API ensures that the charge pump clock (clk_pump) and the HF clock (clk_hf) are set to IMO at 48 MHz. Call the Load Flash Bytes function before calling this function to load the data bytes that will be used for programming the row. In addition, the non-blocking program row function can be called only from SRAM. This is because the CM0 CPU cannot execute code from flash while doing flash program operations. If this function is called from flash memory, the result is undefined, and may return a bus error and trigger a hard fault when the flash fetch operation is being done.
Parameters
Address
Value to be Written
SRAM Address 32'hYY (32-bit wide, word-aligned SRAM address)
Bits [7:0]
0xB6
Bits [15:8]
0xDB
Bits [31:16]
Row ID
CPUSS_SYSARG register
Bits [31:0]
CPUSS_SYSREQ register Bits [15:0] Bits [31:16]
32'hYY
0x0008 0x8000
Description
Key1 Key2 Row number to write 0x0000 Row 0
32-bit word-aligned address of the SRAM that stores the first function parameter (key1)
Non-Blocking Program Row opcode Set SYSCALL_REQ bit
Return
Address CPUSS_SYSARG register Bits [31:28] Bits [27:0]
Return Value
0xA 0xXXXXXXX
Description
Success status code Not used (don't care)
20.5.11 Resume Non-Blocking
This function completes the additional phases of erase and program that were started using the non-blocking write row and non-blocking program row system calls. This function must be called thrice following a call to Non-Blocking Write Row or once following a call to Non-Blocking Program Row from the SPC ISR. No other system calls can execute until all phases of the program or erase operation are complete. More details on the procedure of using the non-blocking functions are explained in Blocking and Non-Blocking System Calls on page 198.
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Parameters
Address
Value to be Written
SRAM Address 32'hYY (32-bit wide, word-aligned SRAM address)
Bits [7:0]
0xB6
Bits [15:8]
0xDC
Bits [31:16]
0xXXXX
CPUSS_SYSARG register
Bits [31:0]
32'hYY
CPUSS_SYSREQ register Bits [15:0] Bits [31:16]
0x0009 0x8000
Return
Description
Key1 Key2 Don't care. Not used by SROM
32-bit word-aligned address of the SRAM that stores the first function parameter (key1)
Resume Non-Blocking opcode Set SYSCALL_REQ bit
Address CPUSS_SYSARG register Bits [31:28] Bits [27:0]
Return Value
0xA 0xXXXXXXX
Description
Success status code Not used (don't care)
20.6 System Call Status
At the end of every system call, a status code is written over the arguments in the CPUSS_SYSARG register. A success status is 0xAXXXXXXX, where X indicates don't care values or return data in the case of the system calls that return a value. A failure status is indicated by 0xF00000XX, where XX is the failure code.
Table 20-2. System Call Status Codes
Status Code (32-bit value in CPUSS_SYSARG register)
Description
AXXXXXXXh
Success The "X" denotes a don't care value, which has a value of `0' returned by the SROM, unless the API returns parameters directly to the CPUSS_SYSARG register.
F0000001h
Invalid Chip Protection Mode This API is not available during the current chip protection mode.
F0000003h
Invalid Page Latch Address The address within the page latch buffer is either out of bounds or the size provided is too large for the page address.
F0000004h
Invalid Address The row ID or byte address provided is outside of the available memory.
F0000005h
Row Protected The row ID provided is a protected row.
F0000007h
Resume Completed All non-blocking APIs have completed. The resume API cannot be called until the next non-blocking API.
F0000008h
Pending Resume A non-blocking API was initiated and must be completed by calling the resume API, before any other API's may be called.
F0000009h
System Call Still In Progress A resume or non-blocking is still in progress. The SPC ISR must fire before attempting the next resume.
F000000Ah
Checksum Zero Failed The calculated checksum was not zero.
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Table 20-2. System Call Status Codes
Status Code (32-bit value in CPUSS_SYSARG register)
Description
F000000Bh
Invalid Opcode The opcode is not a valid API opcode.
F000000Ch
Key Opcode Mismatch The opcode provided does not match key1 and key2.
F000000Eh
Invalid Start Address The start address is greater than the end address provided.
F0000012h
Invalid Pump Clock Frequency - IMO must be set to 48 MHz and HF clock source to the IMO clock source before flash write/erase operations.
20.7 Non-Blocking System Call Pseudo Code
This section contains pseudo code to demonstrate how to set up a non-blocking system call and execute code out of SRAM during the flash programming operations.
#define REG(addr)(*((volatile uint32 *) (addr)))
#define CM0_ISER_REG REG( 0xE000E100 )
#define CPUSS_CONFIG_REGREG( 0x40100000 )
#define CPUSS_SYSREQ_REG REG( 0x40100004 )
#define CPUSS_SYSARG_REG REG( 0x40100008 )
#define ROW_SIZE
64
//Variable to keep track of how many times SPC ISR is triggered __ram int iStatusInt = 0x00;
__flash int main(void) {
DoUserStuff();
//CM0 interrupt enable bit for spc interrupt enable CM0_ISER_REG |= 0x00000040;
//Set CPUSS_CONFIG.VECS_IN_RAM because SPC ISR should be in SRAM CPUSS_CONFIG_REG |= 0x00000001; //Call non-blocking write row API
NonBlockingWriteRow();
//End Program while(1); }
__sram void SpcIntHandler(void) {
/* Call Resume API */
// Write key1, key2 parameters to SRAM REG( 0x20000000 ) = 0x0000DCB6;
//Write the address of key1 to the CPUSS_SYSARG reg CPUSS_SYSARG_REG = 0x20000000;
//Write the API opcode = 0x09 to the CPUSS_SYSREQ.COMMAND //register and assert the sysreq bit CPUSS_SYSREQ_REG = 0x80000009;
iStatusInt ++; // Number of times the ISR has triggered }
__sram void NonBlockingWriteRow(void) {
int iter;
/*Load the Flash page latch with data to write*/
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//Write key1, key2, byte address, //and macro sel parameters to SRAM REG( 0x20000000 ) = 0x0000D7B6;
//Write load size param (64 bytes) to SRAM REG( 0x20000004 ) = 0x0000003F;
for(i = 0; i < ROW_SIZE/4; i += 1); {
REG( 0x20000008 + i*4 ) = 0xDADADADA; }
//Write the address of the key1 param to CPUSS_SYSARG reg CPUSS_SYSARG_REG = 0x20000000;
//Write the API opcode = 0x04 to CPUSS_SYSREQ.COMMAND //register and assert the sysreq bit CPUSS_SYSREQ_REG = 0x80000004;
/*Perform Non-Blocking Write Row on Row 200 as an example */
//Write key1, key2, row id to SRAM //row id = 0xC8 -> which is row 200 REG( 0x20000000 ) = 0x00C8DAB6;
//Write the address of the key1 param to CPUSS_SYSARG reg CPUSS_SYSARG_REG = 0x20000000;
//Write the API opcode = 0x07 to CPUSS_SYSREQ.COMMAND //register and assert the sysreq bit CPUSS_SYSREQ_REG = 0x80000007;
//Execute user code until iStatusInt equals 3 to signify //3 SPC interrupts have happened. This should be 1 in case // of non-blocking program System Call while( iStatusInt != 0x03 ) {
DoOtherUserStuff(); }
//Get the success or failure status of System Call syscall_status = CPUSS_SYSARG_REG; }
In the code, the CM0 exception table is configured to be in SRAM by writing 0x01 to the CPUSS_CONFIG register. The SRAM exception table should have the vector address of the SPC interrupt as the address of the SpcIntHandler() function, which is also defined to be in SRAM. See the Interrupts chapter on page 35 for details on configuring the CM0 exception table to be in SRAM. The pseudo code for a non-blocking program system call is also similar, except that the function opcode and parameters will differ and the iStatusInt variable should be polled for 1 instead of 3. This is because the SPC ISR will be triggered only once for a non-blocking program system call.
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Glossary
The Glossary section explains the terminology used in this technical reference manual. Glossary terms are characterized in bold, italic font throughout the text of this manual.
A
accumulator
In a CPU, a register in which intermediate results are stored. Without an accumulator, it is necessary to write the result of each calculation (addition, subtraction, shift, and so on.) to main memory and read them back. Access to main memory is slower than access to the accumulator, which usually has direct paths to and from the arithmetic and logic unit (ALU).
active high
1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states.
active low
1. A logic signal having its asserted state as the logic 0 state. 2. A logic signal having its logic 1 state as the lower voltage of the two states: inverted logic.
address
The label or number identifying the memory location (RAM, ROM, or register) where a unit of information is stored.
algorithm
A procedure for solving a mathematical problem in a finite number of steps that frequently involve repetition of an operation.
ambient temperature The temperature of the air in a designated area, particularly the area surrounding the device.
analog
See analog signals.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog output
An output that is capable of driving any voltage between the supply rails, instead of just a logic 1 or logic 0.
analog signals
A signal represented in a continuous form with respect to continuous times, as contrasted with a digital signal represented in a discrete (discontinuous) form in a sequence of time.
analog-to-digital (ADC) A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.
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Glossary
AND
See Boolean Algebra.
API (Application Programming Interface)
A series of software routines that comprise an interface between a computer application and lower-level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications.
array
An array, also known as a vector or list, is one of the simplest data structures in computer programming. Arrays hold a fixed number of equally-sized data elements, generally of the same data type. Individual elements are accessed by index using a consecutive range of integers, as opposed to an associative array. Most high-level programming languages have arrays as a builtin data type. Some arrays are multi-dimensional, meaning they are indexed by a fixed number of integers; for example, by a group of two integers. One- and two-dimensional arrays are the most common. Also, an array can be a group of capacitors or resistors connected in some common form.
assembly
A symbolic representation of the machine language of a specific processor. Assembly language is converted to machine code by an assembler. Usually, each line of assembly code produces one machine instruction, though the use of macros is common. Assembly languages are considered low-level languages; where as C is considered a high-level language.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
attenuation
The decrease in intensity of a signal as a result of absorption of energy and of scattering out of the path to the detector, but not including the reduction due to geometric spreading. Attenuation is usually expressed in dB.
B
bandgap reference bandwidth
bias
bias current
A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or
loss); it is sometimes represented more specifically as, for example, full width at half maximum.
1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a
reference level to operate the device.
The constant low-level DC current that is used to produce a stable operation in amplifiers. This current can sometimes be changed to alter the bandwidth of an amplifier.
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binary bit bit rate (BR) block Boolean Algebra
break-before-make broadcast net buffer
bus byte
The name for the base 2 numbering system. The most common numbering system is the base 10 numbering system. The base of a numbering system indicates the number of values that may exist for a particular positioning within a number for that system. For example, in base 2, binary, each position may have one of two values (0 or 1). In the base 10, decimal, numbering system, each position may have one of ten values (0, 1, 2, 3, 4, 5, 6, 7, 8, and 9).
A single digit of a binary number. Therefore, a bit may only have a value of `0' or `1'. A group of 8 bits is called a byte. Because the CCG3's M8CP is an 8-bit microcontroller, the CCG3 devices's native data chunk size is a byte.
The number of bits occurring per unit of time in a bit stream, usually expressed in bits per second (bps).
1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital
CCG3 block or an analog CCG3 block.
In mathematics and computer science, Boolean algebras or Boolean lattices, are algebraic structures which "capture the essence" of the logical operations AND, OR and NOT as well as the set theoretic operations union, intersection, and complement. Boolean algebra also defines a set of theorems that describe how Boolean equations can be manipulated. For example, these theorems are used to simplify Boolean equations, which will reduce the number of logic elements needed to implement the equation.
The operators of Boolean algebra may be represented in various ways. Often they are simply written as AND, OR, and NOT. In describing circuits, NAND (NOT AND), NOR (NOT OR), XNOR (exclusive NOT OR), and XOR (exclusive OR) may also be used. Mathematicians often use + (for example, A+B) for OR and for AND (for example, A*B) (in some ways those operations are analogous to addition and multiplication in other algebraic structures) and represent NOT by a line drawn above the expression being negated (for example, ~A, A_, !A).
The elements involved go through a disconnected state entering (`break") before the new connected state ("make").
A signal that is routed throughout the microcontroller and is accessible by many blocks or systems.
1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device.
3. An amplifier used to lower the output impedance of a system.
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
A digital storage unit consisting of 8 bits.
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Glossary
C
C capacitance capture chaining
checksum
clear clock clock generator CMOS comparator compiler configuration
configuration space crowbar
CPUSS crystal oscillator
A high-level programming language.
A measure of the ability of two adjacent conductors, separated by an insulator, to hold a charge when a voltage differential is applied between them. Capacitance is measured in units of Farads.
To extract information automatically through the use of software or hardware, as opposed to hand-entering of data into a computer file.
Connecting two or more 8-bit digital blocks to form 16-, 24-, and even 32-bit functions. Chaining allows certain signals such as Compare, Carry, Enable, Capture, and Gate to be produced from one block to another.
The checksum of a set of data is generated by adding the value of each data word to a sum. The actual checksum can simply be the result sum or a value that must be added to the sum to generate a pre-determined value.
To force a bit/register to a value of logic `0'.
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks.
A circuit that is used to generate a clock signal.
The logic gates constructed using MOS transistors connected in a complementary manner. CMOS is an acronym for complementary metal-oxide semiconductor.
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements.
A program that translates a high-level language, such as C, into machine language.
In a computer system, an arrangement of functional units according to their nature, number, and chief characteristics. Configuration pertains to hardware, software, firmware, and documentation. The configuration will affect system performance.
In CCG3 devices, the register space accessed when the XIO bit, in the CPU_F register, is set to `1'.
A type of over-voltage protection that rapidly places a low-resistance shunt (typically an SCR) from the signal to one of the power supply rails, when the output voltage exceeds a predetermined value.
CPU subsystem
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components.
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Glossary
cyclic redundancy check (CRC)
A calculation used to detect errors in data communications, typically performed using a linear feedback shift register. Similar calculations may be used for a variety of other purposes such as data compression.
D
data bus
A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
data stream
A sequence of digitally encoded signals used to represent information in transmission.
data transmission
Sending data from one place to another by means of signals over a channel.
debugger
A hardware and software system that allows the user to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
decimal
A base-10 numbering system, which uses the symbols 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9 (called digits) together with the decimal point and the sign symbols + (plus) and - (minus) to represent numbers.
default value
Pertaining to the pre-defined initial, original, or specific setting, condition, value, or action a system will assume, use, or take in the absence of instructions from the user.
device
The device referred to in this manual is the CCG3 device, unless otherwise specified.
die
An non-packaged integrated circuit (IC), normally cut from a wafer.
digital
A signal or function, the amplitude of which is characterized by one of two discrete values: `0' or `1'.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI.
digital logic
A methodology for dealing with expressions containing two-state variables that describe the behavior of a circuit or system.
digital-to-analog (DAC) A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC) converter performs the reverse operation.
direct access
The capability to obtain data from a storage device, or to enter data into a storage device, in a sequence independent of their relative positions by means of addresses that indicate the physical location of the data.
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
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Glossary
E
External Reset (XRES_N)
F
falling edge feedback filter firmware flag Flash
Flash bank Flash block flip-flop
frequency
G
gain gate
An active high signal that is driven into the CCG3 device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state.
A transition from a logic 1 to a logic 0. Also known as a negative edge.
The return of a portion of the output, or processed portion of the output, of a (usually active) device to the input.
A device or process by which certain frequency components of a signal are attenuated.
The software that is embedded in a hardware device and executed by the CPU. The software may be executed by the end user, but it may not be modified.
Any of various types of indicators used for identification of a condition or event (for example, a character that signals the termination of a transmission).
An electrically programmable and erasable, volatile technology that provides users with the programmability and data storage of EPROMs, plus in-system erasability. Nonvolatile means that the data is retained when power is off.
A group of flash ROM blocks where flash block numbers always begin with `0' in an individual flash bank. A flash bank also has its own block level protection information.
The smallest amount of flash ROM space that may be programmed at one time and the smallest amount of flash space that may be protected. A flash block holds 64 bytes.
A device having two stable states and two input terminals (or types of input signals) each of which corresponds with one of the two states. The circuit remains in either state until it is made to change to the other state by application of the corresponding signal.
The number of cycles or events per unit of time, for a periodic function.
The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB.
1. A device having one output channel and one or more input channels, such that the output channel state is completely determined by the input channel states, except during switching transients.
2. One of many types of combinational logic elements having at least two inputs (for example, AND, OR, NAND, and NOR (also see Boolean Algebra)).
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Glossary
ground
H
hardware hardware reset hexadecimal
high time
1. The electrical neutral line having the same potential as the surrounding earth. 2. The negative side of DC power supply. 3. The reference point for an electrical system. 4. The conducting paths between an electric circuit or equipment and the earth, or some con-
ducting body serving in place of the earth.
A comprehensive term for all of the physical parts of a computer or embedded system, as distinguished from the data it contains or operates on, and the software that provides instructions for the hardware to accomplish tasks.
A reset that is caused by a circuit, such as a POR, watchdog reset, or external reset. A hardware reset restores the state of the device as it was when it was first powered up. Therefore, all registers are set to the POR value as indicated in register tables throughout this document.
A base 16 numeral system (often abbreviated and called hex), usually written using the symbols 0-9 and A-F. It is a useful system in computers because there is an easy mapping from four bits to a single hex digit. Thus, one can represent every byte as two consecutive hexadecimal digits. Compare the binary, hex, and decimal representations: bin = hex = dec 0000b = 0x0 = 0 0001b = 0x1 = 1 0010b = 0x2 = 2 ... 1001b = 0x9 = 9 1010b = 0xA = 10 1011b = 0xB = 11 ... 1111b = 0xF = 15 So the decimal numeral 79 whose binary representation is 0100 1111b can be written as 4Fh in hexadecimal (0x4F).
The amount of time the signal has a value of `1' in one period, for a periodic digital signal.
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Glossary
I
I2C
A two-wire serial computer bus by Phillips Semiconductors (now NXP Semiconductors). I2C is an
Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The
original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bidirectional
pins, clock and data, both running at +5 V and pulled high with resistors. The bus operates at
100 Kbps in standard mode and 400 Kbps in fast mode.
idle state
A condition that exists whenever user messages are not being transmitted, but the service is immediately available for use.
impedance
1. The resistance to the flow of current caused by resistive, capacitive, or inductive devices in a circuit.
2. The total passive opposition offered to the flow of electric current. Note the impedance is determined by the particular combination of resistance, inductive reactance, and capacitive reactance in a given circuit.
input
A point that accepts data, in a device, process, or channel.
input/output (I/O)
A device that introduces data into or extracts data from a system.
instruction
An expression that specifies one operation and identifies its operands, if any, in a programming language such as C or assembly.
instruction mnemonics A set of acronyms that represent the opcodes for each of the assembly-language instructions, for example, ADD, SUBB, MOV.
integrated circuit (IC) A device in which components such as resistors, capacitors, diodes, and transistors are formed on the surface of a single piece of semiconductor.
interface
The means by which two systems or devices are connected and interact with each other.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed.
interrupt service routine (ISR)
A block of code that normal code execution is diverted to when the M8CP receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution.
J
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
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Glossary
L
latency
The time or delay that it takes for a signal to pass through a given circuit or network.
least significant bit (LSb)
The binary digit, or bit, in a binary number that represents the least significant value (typically the right-hand bit). The bit versus byte distinction is made by using a lower case "b" for bit in LSb.
least significant byte (LSB)
The byte in a multi-byte word that represents the least significant values (typically the right-hand byte). The byte versus bit distinction is made by using an upper case "B" for byte in LSB.
Linear Feedback Shift A shift register whose data input is generated as an XOR of two or more elements in the register
Register (LFSR)
chain.
load
The electrical demand of a process expressed as power (watts), current (amps), or resistance (ohms).
logic function
A mathematical function that performs a digital operation on digital data and returns a digital value.
lookup table (LUT)
A logic block that implements several logic functions. The logic function is selected by means of select lines and is applied to the inputs of the block. For example: A 2 input LUT with 4 select lines can be used to perform any one of 16 logic functions on the two inputs resulting in a single logic output. The LUT is a combinational device; therefore, the input/output relationship is continuous, that is, not sampled.
low time
The amount of time the signal has a value of `0' in one period, for a periodic digital signal.
low-voltage detect (LVD)
A circuit that senses VDDD and provides an interrupt to the system when VDDD falls below a selected threshold.
M
M8CP macro
mask
An 8-bit Harvard Architecture microprocessor. The microprocessor coordinates all activity inside a CCG3 device by interfacing to the flash, SRAM, and register space.
A programming language macro is an abstraction, whereby a certain textual pattern is replaced according to a defined set of rules. The interpreter or compiler automatically replaces the macro instance with the macro contents when an instance of the macro is encountered. Therefore, if a macro is used five times and the macro definition required 10 bytes of code space, 50 bytes of code space will be needed in total.
1. To obscure, hide, or otherwise prevent information from being derived from a signal. It is usually the result of interaction with another signal, such as noise, static, jamming, or other forms of interference.
2. A pattern of bits that can be used to retain or suppress segments of another pattern of bits, in computing and data processing systems.
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Glossary
master device
A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device.
microcontroller
An integrated circuit device that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of devices, thus achieving maximal possible miniaturization. This in turn, will reduce the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor.
mnemonic
A tool intended to assist the memory. Mnemonics rely on not only repetition to remember facts, but also on creating associations between easy-to-remember constructs and lists of data. A two to four character string representing a microprocessor instruction.
mode
A distinct method of operation for software or hardware. For example, the Digital CCG3 block may be in either counter mode or timer mode.
modulation
A range of techniques for encoding information on a carrier signal, typically a sine-wave signal. A device that performs modulation is known as a modulator.
Modulator
A device that imposes a signal on a carrier.
MOS
An acronym for metal-oxide semiconductor.
most significant bit (MSb)
The binary digit, or bit, in a binary number that represents the most significant value (typically the left-hand bit). The bit versus byte distinction is made by using a lower case "b" for bit in MSb.
most significant byte (MSB)
The byte in a multi-byte word that represents the most significant values (typically the left-hand byte). The byte versus bit distinction is made by using an upper case "B" for byte in MSB.
multiplexer (mux)
1. A logic function that uses a binary value, or address, to select between a number of inputs and conveys the data from the selected input to the output.
2. A technique which allows different input (or output) signals to use the same lines at different times, controlled by an external signal. Multiplexing is used to save on wiring and I/O ports.
N
NAND negative edge net nibble noise
See Boolean Algebra.
A transition from a logic 1 to a logic 0. Also known as a falling edge.
The routing between devices.
A group of four bits, which is one-half of a byte.
1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current,
or data.
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Glossary
NOR NOT
See Boolean Algebra. See Boolean Algebra.
O
OR oscillator output
See Boolean Algebra. A circuit that may be crystal controlled and is used to generate a clock frequency. The electrical signal or signals which are produced by an analog or digital block.
P
parallel parameter parameter block parity path pending interrupts phase pin pinouts
port positive edge posted interrupts
The means of communication in which digital data is sent multiple bits at a time, with each simultaneous bit being sent over a separate line.
Characteristics for a given block that have either been characterized or may be defined by the designer.
A location in memory where parameters for the SSC instruction are placed prior to execution.
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity).
1. The logical sequence of instructions executed by a computer. 2. The flow of an electrical signal through a circuit.
An interrupt that is triggered but not serviced, either because the processor is busy servicing another interrupt or global interrupts are disabled.
The relationship between two signals, usually the same frequency, that determines the delay between them. This delay between signals is either measured by time or angle (degrees).
A terminal on a hardware component. Also called lead.
The pin number assignment: the relation between the logical inputs and outputs of the CCG3 device and their physical counterparts in the printed circuit board (PCB) package. Pinouts will involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names.
A group of pins, usually eight.
A transition from a logic 0 to a logic 1. Also known as a rising edge.
An interrupt that is detected by the hardware but may or may not be enabled by its mask bit. Posted interrupts that are not masked become pending interrupts.
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Glossary
Power On Reset (POR) A circuit that forces the CCG3 device to reset when the voltage is below a pre-set level. This is one type of hardware reset.
program counter
The instruction pointer (also called the program counter) is a register in a computer processor that indicates where in memory the CPU is executing instructions. Depending on the details of the particular machine, it holds either the address of the instruction being executed, or the address of the next instruction to be executed.
protocol
A set of rules. Particularly the rules that govern networked communications.
pulse
A rapid change in some characteristic of a signal (for example, phase or frequency), from a baseline value to a higher or lower value, followed by a rapid return to the baseline value.
pulse width modulator An output in the form of duty cycle which varies as a function of the applied measure. (PWM)
R
RAM
register reset resistance revision ID ripple divider
rising edge ROM
routine routing runt pulses
An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in.
A storage device with a specific capacity, such as a bit or byte.
A means of bringing a system back to a know state. See hardware reset and software reset.
The resistance to the flow of electric current measured in ohms for a conductor.
A unique identifier of the CCG3 device.
An asynchronous ripple counter constructed of flip-flops. The clock is fed to the first stage of the counter. An n-bit binary counter consisting of n flip-flops that can count in binary from 0 to 2n - 1.
See positive edge.
An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in.
A block of code, called by another block of code, that may have some general or frequent use.
Physically connecting objects in a design according to design rules set in the reference library.
In digital circuits, narrow pulses that, due to non-zero rise and fall times of the signal, do not reach a valid high or low level. For example, a runt pulse may occur when switching between asynchronous clocks or as the result of a race condition in which a signal takes two separate paths through a circuit. These race conditions may have different delays and are then recombined to form a glitch or when the output of a flip-flop becomes metastable.
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Glossary
S
sampling schematic seed value serial
set settling time shift
shift register sign bit signal silicon ID skew slave device
software
software reset
The process of converting an analog signal into a series of digital values or reversed.
A diagram, drawing, or sketch that details the elements of a system, such as the elements of an electrical circuit or the elements of a logic diagram for a computer.
An initial value loaded into a linear feedback shift register or random number generator.
1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a
single device or channel.
To force a bit/register to a value of logic 1.
The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
The movement of each bit in a word one position to either the left or right. For example, if the hex value 0x24 is shifted one place to the left, it becomes 0x48. If the hex value 0x24 is shifted one place to the right, it becomes 0x12.
A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
The most significant binary digit, or bit, of a signed binary number. If set to a logic 1, this bit represents a negative quantity.
A detectable transmitted energy that can be used to carry information. As applied to electronics, any transmitted electrical impulse.
A unique identifier of the CCG3 silicon.
The difference in arrival time of bits transmitted at the same time, in parallel transmission.
A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device.
A set of computer programs, procedures, and associated documentation about the operation of a data processing system (for example, compilers, library routines, manuals, and circuit diagrams). Software is often written first as source code, and then converted to a binary format that is specific to the device on which the code will be executed.
A partial reset executed by software to bring part of the system back to a known state. A software reset will restore the M8CP to a know state but not CCG3 blocks, systems, peripherals, or registers. For a software reset, the CPU registers (CPU_A, CPU_F, CPU_PC, CPU_SP, and CPU_X) are set to 0x00. Therefore, code execution will begin at flash address 0x0000.
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Glossary
SRAM
SROM stack stack pointer state machine sticky stop bit switching switch phasing
synchronous
T
tap terminal count threshold
An acronym for static random access memory. A memory device allowing users to store and retrieve data at a high rate of speed. The term static is used because, when a value is loaded into an SRAM cell, it will remain unchanged until it is explicitly altered or until power is removed from the device.
An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform flash operations. The functions of the SROM may be accessed in normal user code, operating from flash.
A stack is a data structure that works on the principle of Last In First Out (LIFO). This means that the last item put on the stack is the first item that can be taken off.
A stack may be represented in a computer's inside blocks of memory cells, with the bottom at a fixed location and a variable stack pointer to the current top cell.
The actual implementation (in hardware or software) of a function that can be considered to consist of a set of states through which it sequences.
A bit in a register that maintains its value past the time of the event that caused its transition, has passed.
A signal following a character or block that prepares the receiving device to receive the next character or block.
The controlling or routing of signals in circuits to execute logical or arithmetic operations, or to transmit data between specific points in a network.
The clock that controls a given switch, PHI1 or PHI2, in respect to the switch capacitor (SC) blocks. The CCG3 SC blocks have two groups of switches. One group of these switches is normally closed during PHI1 and open during PHI2. The other group is open during PHI1 and closed during PHI2. These switches can be controlled in the normal operation, or in reverse mode if the PHI1 and PHI2 clocks are reversed.
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
The connection between two blocks of a device created by connecting several blocks/components in a series, such as a shift register or resistive voltage divider.
The state at which a counter is counted down to zero.
The minimum value of a signal that can be detected by the system or sensor under consideration.
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Thumb-2
transistors
tristate
U
UART user user modules user space
V
VDDD volatile VSS
Glossary
The Thumb-2 instruction set is a highly efficient and powerful instruction set that delivers significant benefits in terms of ease of use, code size, and performance. The Thumb-2 instruction set is a superset of the previous 16-bit Thumb instruction set, with additional 16-bit instructions alongside 32-bit instructions. The transistor is a solid-state semiconductor device used for amplification and switching, and has three terminals: a small current or voltage applied to one terminal controls the current through the other two. It is the key component in all modern electronics. In digital circuits, transistors are used as very fast electrical switches, and arrangements of transistors can function as logic gates, RAM-type memory, and other devices. In analog circuits, transistors are essentially used as amplifiers. A function whose output can adopt three states: 0, 1, and Z (high impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net.
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. The person using the CCG3 device and reading this manual. Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital CCG3 Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program.
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 or 3.3 volts. Not guaranteed to stay the same value or level when not in scope. A name for a power net meaning "voltage source." The most negative power supply signal.
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Glossary
W
watchdog timer waveform
X
XOR
A timer that must be serviced periodically. If it is not serviced, the CPU will reset after a specified period of time. The representation of a signal as a plot of amplitude versus time.
See Boolean Algebra.
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Index
B
block diagram GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 port interrupt controller unit . . . . . . . . . . . . . . . . . . 54 program and debug interface . . . . . . . . . . . . . . . . 189 watchdog timer circuit . . . . . . . . . . . . . . . . . . . . . . 69
brownout reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
GPIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
H
high impedance analog drive mode . . . . . . . . . . . . . . . .52 high impedance digital drive mode . . . . . . . . . . . . . . . . .52
C
clocking system introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Cortex-M0 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
D
development kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 document
glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
E
exception HardFault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PendSV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SVCall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SysTick . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
F
features I/O system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 port interrupt controller unit . . . . . . . . . . . . . . . . . . 54 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
G
glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
I
I/O drive mode high impedance analog . . . . . . . . . . . . . . . . . . . . . .52 high impedance digital . . . . . . . . . . . . . . . . . . . . . . .52 open drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 resistive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 strong . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
I/O system features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 open drain modes . . . . . . . . . . . . . . . . . . . . . . . . . .52 port interrupt controller unit pin configuration . . . . .54 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .55 resistive modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 slew rate control . . . . . . . . . . . . . . . . . . . . . . . . . . .53 strong drive mode . . . . . . . . . . . . . . . . . . . . . . . . . .52
identifying reset sources . . . . . . . . . . . . . . . . . . . . . . . . .74 internal main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .59 introduction
clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 I/O system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
O
oscillators internal PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
overview, document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
P
port interrupt controller features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
port interrupt controller unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
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Index
pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 protection fault reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
R
register summary I/O system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
registers Cortex-M0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
reset identifying sources . . . . . . . . . . . . . . . . . . . . . . . . . 74 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
reset sources description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
S
slew rate control in I/O system . . . . . . . . . . . . . . . . . . . . 53 software initiated reset . . . . . . . . . . . . . . . . . . . . . . . . . . 73 support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SWD interface
program and debug interface . . . . . . . . . . . . . . . . 190 system call
overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
U
upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
W
watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 watchdog timer
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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