u blox 1EIQN2NN LTE Data Module User Manual LARA R2 series
u-blox AG LTE Data Module LARA R2 series
UserManual.wiki
>
u blox
>
1EIQN2NN User Manual
System Integrators Manual
Navigation menu
Upload a User Manual
Namespaces
Wiki Guide
HTML
PDF
Info
Views
User Manual
Discussion / Help
Navigation
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 13 of 148 Function Pin Name Pin No I/O Description Remarks USB VUSB_DET 17 I USB detect input VBUS (5 V typical) USB supply generated by the host must be connected to this input pin to enable the USB interface. If the USB interface is not used by the Application Processor, Test-Point for diagnostic / FW update access is recommended See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in. USB_D- 28 I/O USB Data Line D- USB interface for AT commands, data communication, FOAT, FW update by u-blox EasyFlash tool and diagnostic. 90 nominal differential impedance (Z0) 30 nominal common mode impedance (ZCM) Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 specifications [9] are part of the USB pin driver and need not be provided externally. If the USB interface is not used by the Application Processor, Test-Point for diagnostic / FW update access is recommended See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in. USB_D+ 29 I/O USB Data Line D+ USB interface for AT commands, data communication, FOAT, FW update by u-blox EasyFlash tool and diagnostic. 90 nominal differential impedance (Z0) 30 nominal common mode impedance (ZCM) Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 specifications [9] are part of the USB pin driver and need not be provided externally. If the USB interface is not used by the Application Processor, Test-Point for diagnostic / FW update access is recommended See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in. HSIC HSIC_DATA 99 I/O HSIC USB data line Not supported by “02” product versions. USB High-Speed Inter-Chip compliant interface for AT commands, data communication, FOAT, FW update by u-blox EasyFlash tool and diagnostic. 50 nominal characteristic impedance. Test-Point for diagnostic / FW update access is recommended. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in. HSIC_STRB 100 I/O HSIC USB strobe line Not supported by “02” product versions. HSIC interface for AT commands, data communication, FOAT, FW update by u-blox EasyFlash tool and diagnostic. 50 nominal characteristic impedance. Test-Point for diagnostic / FW update access is recommended. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in. DDC SCL 27 O I2C bus clock line 1.8 V open drain, for communication with I2C-slave devices. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in. SDA 26 I/O I2C bus data line 1.8 V open drain, for communication with I2C-slave devices. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-13.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 14 of 148 Function Pin Name Pin No I/O Description Remarks SDIO SDIO_D0 47 I/O SDIO serial data [0] Not supported by “02” product versions. SDIO interface for communication with u-blox Wi-Fi module See section 1.9.5 for functional description. See section 2.6.5 for external circuit design-in. SDIO_D1 49 I/O SDIO serial data [1] Not supported by “02” product versions. SDIO interface for communication with u-blox Wi-Fi module See section 1.9.5 for functional description. See section 2.6.5 for external circuit design-in. SDIO_D2 44 I/O SDIO serial data [2] Not supported by “02” product versions. SDIO interface for communication with u-blox Wi-Fi module See section 1.9.5 for functional description. See section 2.6.5 for external circuit design-in. SDIO_D3 48 I/O SDIO serial data [3] Not supported by “02” product versions. SDIO interface for communication with u-blox Wi-Fi module See section 1.9.5 for functional description. See section 2.6.5 for external circuit design-in. SDIO_CLK 45 O SDIO serial clock Not supported by “02” product versions. SDIO interface for communication with u-blox Wi-Fi module See section 1.9.5 for functional description. See section 2.6.5 for external circuit design-in. SDIO_CMD 46 I/O SDIO command Not supported by “02” product versions. SDIO interface for communication with u-blox Wi-Fi module See section 1.9.5 for functional description. See section 2.6.5 for external circuit design-in. Audio I2S_TXD 35 O / I/O I2S transmit data / GPIO I2S transmit data output, alternatively configurable as GPIO. I2S not supported by LARA-R204 module ‘02’ product version. See sections 1.10 and 1.12 for functional description. See sections 2.7 and 2.8 for external circuit design-in. I2S_RXD 37 I / I/O I2S receive data / GPIO I2S receive data input, alternatively configurable as GPIO. I2S not supported by LARA-R204 module ‘02’ product version. See sections 1.10 and 1.12 for functional description. See sections 2.7 and 2.8 for external circuit design-in. I2S_CLK 36 I/O / I/O I2S clock / GPIO I2S serial clock, alternatively configurable as GPIO. I2S not supported by LARA-R204 module ‘02’ product version. See sections 1.10 and 1.12 for functional description. See sections 2.7 and 2.8 for external circuit design-in. I2S_WA 34 I/O / I/O I2S word alignment / GPIO I2S word alignment, alternatively configurable as GPIO. I2S not supported by LARA-R204 module ‘02’ product version. See sections 1.10 and 1.12 for functional description. See sections 2.7 and 2.8 for external circuit design-in. Clock output GPIO6 19 O Clock output 1.8 V configurable clock output. See section 1.11 for functional description. See section 2.7 for external circuit design-in.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-14.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 16 of 148 1.4 Operating modes LARA-R2 series modules have several operating modes. The operating modes defined in Table 4 and described in detail in Table 5 provide general guidelines for operation. General Status Operating Mode Definition Power-down Not-Powered Mode VCC supply not present or below operating range: module is switched off. Power-Off Mode VCC supply within operating range and module is switched off. Normal operation Idle-Mode Module processor core runs with 32 kHz reference generated by the internal oscillator. Active-Mode Module processor core runs with 26 MHz reference generated by the internal oscillator. Connected-Mode RF Tx/Rx data connection enabled and processor core runs with 26 MHz reference. Table 4: Module operating modes definition Mode Description Transition between operating modes Not-Powered Module is switched off. Application interfaces are not accessible. When VCC supply is removed, the module enters not-powered mode. When in not-powered mode, the modules cannot be switched on by PWR_ON, RESET_N or RTC alarm. When in not-powered mode, the modules can be switched on applying VCC supply (see 2.3.1) so that the module switches from not-powered to active-mode. Power-Off Module is switched off: normal shutdown by an appropriate power-off event (see 1.6.2). Application interfaces are not accessible. When the module is switched off by an appropriate power-off event (see 1.6.2), the module enters power-off mode from active-mode. When in power-off mode, the modules can be switched on by PWR_ON, RESET_N or RTC alarm (see 2.3.1): the module switches from power-off to active-mode. When in power-off mode, the modules enter not-powered mode by removing VCC supply. Idle Module is switched on with application interfaces temporarily disabled or suspended: the module is temporarily not ready to communicate with an external device by means of the application interfaces as configured to reduce the current consumption. The module enters the low power idle-mode whenever possible if power saving is enabled by AT+UPSV (see u-blox AT Commands Manual [2]) reducing power consumption (see 1.5.1.4). The CTS output line indicates when the UART interface is disabled/enabled due to the module idle/active-mode according to power saving and HW flow control settings (see 1.9.1.3, 1.9.1.4). Power saving configuration is not enabled by default: it can be enabled by AT+UPSV (see the u-blox AT Commands Manual [2]). The module automatically switches from active-mode to idle-mode whenever possible if power saving is enabled (see sections 1.5.1.4, 1.9.1.4, 1.9.2.4 and to the u-blox AT Commands Manual [2], AT+UPSV command). The module wakes up from idle to active mode in the following events: Automatic periodic monitoring of the paging channel for the paging block reception according to network conditions (see 1.5.1.3, 1.9.1.4) Automatic periodic enable of the UART interface to receive and send data, if AT+UPSV=1 power saving is set (see 1.9.1.4) Data received on UART interface, according to HW flow control (AT&K) and power saving (AT+UPSV) settings (see 1.9.1.4) RTS input set ON by the host DTE, with HW flow control disabled and AT+UPSV=2 (see 1.9.1.4) DTR input set ON by the host DTE, with AT+UPSV=3 (see 1.9.1.4) USB detection, applying 5 V (typ.) to VUSB_DET input (see 1.9.2) The connected USB host forces a remote wakeup of the module as USB device (see 1.9.2.4) The connected u-blox GNSS receiver forces a wakeup of the cellular module using the GNSS Tx data ready function over the GPIO3 pin (see 1.9.4) The connected SDIO device forces a wakeup of the module as SDIO host (see 1.9.5) RTC alarm occurs (see u-blox AT Commands Manual [2], +CALA)](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-16.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 17 of 148 Mode Description Transition between operating modes Active The module is ready to communicate with an external device by means of the application interfaces unless power saving configuration is enabled by the AT+UPSV command (see sections 1.5.1.3, 1.9.1.4 and to the u-blox AT Commands Manual [2]). When the module is switched on by an appropriate power-on event (see 2.3.1), the module enters active-mode from not-powered or power-off mode. If power saving configuration is enabled by the AT+UPSV command, the module automatically switches from active to idle-mode whenever possible and the module wakes up from idle to active-mode in the events listed above (see idle to active transition description). When a voice call or a data call is initiated, the module switches from active-mode to connected-mode. Connected A voice call or a data call is in progress. The module is ready to communicate with an external device by means of the application interfaces unless power saving configuration is enabled by the AT+UPSV command (see sections 1.5.1.3, 1.9.1.4 and the u-blox AT Commands Manual [2]). When a data or voice connection is initiated, the module enters connected-mode from active-mode. Connected-mode is suspended if Tx/Rx data is not in progress, due to connected discontinuous reception and fast dormancy capabilities of the module and according to network environment settings and scenario. In such case, the module automatically switches from connected to active mode and then, if power saving configuration is enabled by the AT+UPSV command, the module automatically switches to idle-mode whenever possible. Vice-versa, the module wakes up from idle to active mode and then connected mode if RF Tx/Rx is necessary. When a data connection is terminated, the module returns to the active-mode. Table 5: Module operating modes description Figure 2 describes the transition between the different operating modes. Switch ON:•Apply VCCIf power saving is enabled and there is no activity for a defined time intervalAny wake up event described in the module operating modes summary table aboveIncoming/outgoing call or other dedicated device network communicationNo RF Tx/Rx in progress, Call terminated, Communication droppedRemove VCCSwitch ON:•PWR_ON•RTC alarm•RESET_N Not poweredPower offActiveConnected IdleSwitch OFF:•AT+CPWROFF Figure 2: Operating modes transition](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-17.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 19 of 148 1.5.1.1 VCC supply requirements Table 6 summarizes the requirements for the VCC module supply. See section 2.2.1 for all the suggestions to properly design a VCC supply circuit compliant to the requirements listed in Table 6. VCC supply circuit affects the RF compliance of the device integrating LARA-R2 series modules with applicable required certification schemes as well as antenna circuit design. Compliance is guaranteed if the VCC requirements summarized in the Table 6 are fulfilled. Item Requirement Remark VCC nominal voltage Within VCC normal operating range: 3.30 V min. / 4.40 V max RF performance is guaranteed when VCC PA voltage is inside the normal operating range limits. RF performance may be affected when VCC PA voltage is outside the normal operating range limits, though the module is still fully functional until the VCC voltage is inside the extended operating range limits. VCC voltage during normal operation Within VCC extended operating range: 3.00 V min. / 4.50 V max VCC voltage must be above the extended operating range minimum limit to switch-on the module. The module may switch-off when the VCC voltage drops below the extended operating range minimum limit. Operation above VCC extended operating range is not recommended and may affect device reliability. VCC average current Support with adequate margin the highest averaged VCC current consumption value in connected-mode conditions specified in LARA-R2 series Data Sheet [1] The highest averaged VCC current consumption can be greater than the specified value according to the actual antenna mismatching, temperature and VCC voltage. See 1.5.1.2, 1.5.1.3 for connected-mode current profiles. VCC peak current Support with margin the highest peak VCC current consumption value in connected-mode conditions specified in LARA-R2 series Data Sheet [1] The specified highest peak of VCC current consumption occurs during GSM single transmit slot in 850/900 MHz connected-mode, in case of mismatched antenna. See 1.5.1.2 for 2G connected-mode current profiles. VCC voltage drop during 2G Tx slots Lower than 400 mV VCC voltage drop directly affects the RF compliance with applicable certification schemes. Figure 5 describes VCC voltage drop during Tx slots. VCC voltage ripple during 2G/LTE Tx Noise in the supply has to be minimized VCC voltage ripple directly affects the RF compliance with applicable certification schemes. Figure 5 describes VCC voltage ripple during Tx slots. VCC under/over-shoot at start/end of Tx slots Absent or at least minimized VCC under/over-shoot directly affects the RF compliance with applicable certification schemes. Figure 5 describes VCC voltage under/over-shoot. Table 6: Summary of VCC supply requirements](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-19.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 20 of 148 1.5.1.2 VCC current consumption in 2G connected-mode When a GSM call is established, the VCC consumption is determined by the current consumption profile typical of the GSM transmitting and receiving bursts. The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which is regulated by the network. The transmitted power in the transmit slot is also the more relevant factor for determining the average current consumption. If the module is transmitting in 2G single-slot mode (as in GSM talk mode) in the 850 or 900 MHz bands, at the maximum RF power control level (approximately 2 W or 33 dBm in the Tx slot/burst), the current consumption can reach an high peak / pulse (see LARA-R2 series Data Sheet [1]) for 576.9 µs (width of the transmit slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), so with a 1/8 duty cycle according to GSM TDMA (Time Division Multiple Access). If the module is transmitting in 2G single-slot mode in the 1800 or 1900 MHz bands, the current consumption figures are quite less high than the one in the low bands, due to 3GPP transmitter output power specifications. During a GSM call, current consumption is not so significantly high in receiving or in monitor bursts and it is low in the bursts unused to transmit / receive. Figure 4 shows an example of the module current consumption profile versus time in GSM talk mode. Time [ms]RX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotRX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)Current [A]200 mA60-120 mA1900 mAPeak current depends on TX power and actual antenna loadGSM frame 4.615 ms (1 frame = 8 slots)60-120 mA10-40 mA0.01.51.00.52.0 Figure 4: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot) Figure 5 illustrates VCC voltage profile versus time during a GSM call, according to the related VCC current consumption profile described in Figure 4. TimeundershootovershootrippledropVoltage3.8 V (typ)RX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotRX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)GSM frame 4.615 ms (1 frame = 8 slots) Figure 5: Description of the VCC voltage profile versus time during a GSM call (1 TX slot, 1 RX slot)](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-20.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 21 of 148 When a GPRS connection is established, more than one slot can be used to transmit and/or more than one slot can be used to receive. The transmitted power depends on network conditions, which set the peak current consumption, but following the 3GPP specifications the maximum Tx RF power is reduced if more than one slot is used to transmit, so the maximum peak of current is not as high as can be in case of a 2G single-slot call. The multi-slot transmission power can be further reduced by configuring the actual Multi-Slot Power Reduction profile with the dedicated AT command, AT+UDCONF=40 (see the u-blox AT Commands Manual [2]). If the module transmits in GPRS class 12 in the 850 or 900 MHz bands, at the maximum RF power control level, the current consumption can reach a quite high peak but lower than the one achievable in 2G single-slot mode. This happens for 2.307 ms (width of the 4 transmit slots/bursts) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/2 duty cycle, according to 2G TDMA. If the module is in GPRS connected mode in the 1800 or 1900 MHz bands, the current consumption figures are quite less high than the one in the low bands, due to 3GPP transmitter output power specifications. Figure 6 reports the current consumption profiles in GPRS class 12 connected mode, in the 850 or 900 MHz bands, with 4 slots used to transmit and 1 slot used to receive. Time [ms]RX slotunused slotTX slotTX slotTX slotTX slotMON slotunused slotRX slotunused slotTX slotTX slotTX slotTX slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)Current [A]200mA60-130mAPeak current depends on TX power and actual antenna loadGSM frame 4.615 ms (1 frame = 8 slots)1600 mA0.01.51.00.52.0 Figure 6: VCC current consumption profile versus time during a 2G GPRS/EDGE multi-slot connection (4 TX slots, 1 RX slot) In case of EDGE connections the VCC current consumption profile is very similar to the GPRS current profile, so the image shown in Figure 6, representing the current consumption profile in GPRS class 12 connected mode, is valid for the EDGE class 12 connected mode as well.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-21.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 22 of 148 1.5.1.3 VCC current consumption in LTE connected-mode During an LTE connection, the module can transmit and receive continuously due to the Frequency Division Duplex (FDD) mode of operation used in LTE radio access technology. The current consumption depends on output RF power, which is always regulated by the network (the current base station) sending power control commands to the module. These power control commands are logically divided into a slot of 0.5 ms (time length of one Resource Block), thus the rate of power change can reach a maximum rate of 2 kHz. The current consumption profile is similar to that in 3G radio access technology. Unlike the 2G connection mode, which uses the TDMA mode of operation, there are no high current peaks since transmission and reception are continuously enabled in FDD. In the worst scenario, corresponding to a continuous transmission and reception at maximum output power (approximately 250 mW or 24 dBm), the average current drawn by the module at the VCC pins is considerable (see the “Current consumption” section in LARA-R2 series Data Sheet [1]). At the lowest output RF power (approximately 0.1 µW or –40 dBm), the current drawn by the internal power amplifier is strongly reduced and the total current drawn by the module at the VCC pins is due to baseband processing and transceiver activity. Figure 7 shows an example of the module current consumption profile versus time in LTE connected-mode. Detailed current consumption values can be found in LARA-R2 series Data Sheet [1]. Time [ms]Current [mA]Current consumption value depends on TX power and actual antenna load1 Slot1 Resource Block (0.5 ms) 1 LTE Radio Frame (10 ms)0300200100500400600700 Figure 7: VCC current consumption profile versus time during LTE connection (TX and RX continuously enabled)](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-22.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 23 of 148 1.5.1.4 VCC current consumption in cyclic idle/active-mode (power saving enabled) The power saving configuration is by default disabled, but it can be enabled using the appropriate AT command (see u-blox AT Commands Manual [2], AT+UPSV command). When power saving is enabled, the module automatically enters low power idle-mode whenever possible, reducing current consumption. When the power saving configuration is enabled and the module is registered or attached to a network, the module automatically enters the low power idle-mode whenever possible, but it must periodically monitor the paging channel of the current base station (paging block reception), in accordance to the 2G / LTE system requirements, even if connected-mode is not enabled by the application. When the module monitors the paging channel, it wakes up to the active-mode, to enable the reception of paging block. In between, the module switches to low power idle-mode. This is known as discontinuous reception (DRX). The module processor core is activated during the paging block reception, and automatically switches its reference clock frequency from 32 kHz to the 26 MHz used in active-mode. The time period between two paging block receptions is defined by the network. This is the paging period parameter, fixed by the base station through broadcast channel sent to all users on the same serving cell: In case of 2G radio access technology, the paging period can vary from 470.8 ms (DRX = 2, length of 2 x 51 2G frames = 2 x 51 x 4.615 ms) up to 2118.4 ms (DRX = 9, length of 9 x 51 2G frames = 9 x 51 x 4.615 ms) In case of LTE radio access technology, the paging period can vary from 320 ms (DRX = 5, i.e. length of 25 LTE frames = 32 x 10 ms) up to 2560 ms (DRX = 8, length of 28 LTE frames = 256 x 10 ms). Figure 8 illustrates a typical example of the module current consumption profile when power saving is enabled. The module is registered with network, automatically enters the low power idle-mode and periodically wakes up to active-mode to monitor the paging channel for the paging block reception. Detailed current consumption values can be found in LARA-R2 series Data Sheet [1]). ~50 msIDLE MODE ACTIVE MODE IDLE MODEActive Mode EnabledIdle Mode Enabled2G case: 0.44-2.09 s LTE case: 0.27-2.51 sIDLE MODE~50 msACTIVE MODETime [s]Current [mA]Time [ms]Current [mA]RX Enabled01000100 Figure 8: VCC current consumption profile with power saving enabled and module registered with the network: the module is in low-power idle-mode and periodically wakes up to active-mode to monitor the paging channel for paging block reception](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-23.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 24 of 148 1.5.1.5 VCC current consumption in fixed active-mode (power saving disabled) Power saving configuration is by default disabled, or it can be disabled using the appropriate AT command (see u-blox AT Commands Manual [2], AT+UPSV command). When power saving is disabled, the module does not automatically enter idle-mode whenever possible: the module remains in active-mode. The module processor core is activated during active-mode, and the 26 MHz reference clock frequency is used. Figure 9 illustrates a typical example of the module current consumption profile when power saving is disabled. In such case, the module is registered with the network and while active-mode is maintained, the receiver is periodically activated to monitor the paging channel for paging block reception. Detailed current consumption values can be found in LARA-R2 series Data Sheet [1]. ACTIVE MODE2G case: 0.44-2.09 s 3G case: 0.61-5.09 sLTE case: 0.32-2.56 sPaging periodTime [s]Current [mA]Time [ms]Current [mA]RX Enabled01000100 Figure 9: VCC current consumption profile with power saving disabled and module registered with the network: active-mode is always held and the receiver is periodically activated to monitor the paging channel for paging block reception](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-24.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 25 of 148 1.5.2 RTC supply input/output (V_BCKP) The V_BCKP pin of LARA-R2 series modules connects the supply for the Real Time Clock (RTC) and Power-On internal logic. This supply domain is internally generated by a linear LDO regulator integrated in the Power Management Unit, as described in Figure 10. The output of this linear regulator is always enabled when the main voltage supply provided to the module through the VCC pins is within the valid operating range, with the module switched off or switched on. Baseband Processor51VCC52VCC53VCC2V_BCKPLinear LDO RTCPower ManagementLARA-R2 series32 kHz Figure 10: RTC supply input/output (V_BCKP) and 32 kHz RTC timing reference clock simplified block diagram The RTC provides the module time reference (date and time) that is used to set the wake-up interval during the low power idle-mode periods, and is able to make available the programmable alarm functions. The RTC functions are available also in power-down mode when the V_BCKP voltage is within its valid range (specified in the “Input characteristics of Supply/Power pins” table in LARA-R2 series Data Sheet [1]). The RTC can be supplied from an external back-up battery through the V_BCKP, when the main module voltage supply is not applied to the VCC pins. This lets the time reference (date and time) run until the V_BCKP voltage is within its valid range, even when the main supply is not provided to the module. Consider that the module cannot switch on if a valid voltage is not present on VCC even when the RTC is supplied through V_BCKP (meaning that VCC is mandatory to switch on the module). The RTC has very low current consumption, but is highly temperature dependent. For example, V_BCKP current consumption at the maximum operating temperature can be higher than the typical value at 25 °C specified in the “Input characteristics of Supply/Power pins” table in the LARA-R2 series Data Sheet [1]. If V_BCKP is left unconnected and the module main voltage supply is removed from VCC, the RTC is supplied from the bypass capacitor mounted inside the module. However, this capacitor is not able to provide a long buffering time: within few milliseconds the voltage on V_BCKP will go below the valid range. This has no impact on cellular connectivity, as all the module functionalities do not rely on date and time setting.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-25.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 26 of 148 1.5.3 Generic digital interfaces supply output (V_INT) The V_INT output pin of the LARA-R2 series modules is connected to an internal 1.8 V supply with current capability specified in the LARA-R2 series Data Sheet [1]. This supply is internally generated by a switching step-down regulator integrated in the Power Management Unit and it is internally used to source the generic digital I/O interfaces of the cellular module, as described in Figure 11. The output of this regulator is enabled when the module is switched on and it is disabled when the module is switched off. Baseband Processor51VCC52VCC53VCC4V_INTSwitchingStep-DownDigital I/O InterfacesPower ManagementLARA-R2 series Figure 11: LARA-R2 series interfaces supply output (V_INT) simplified block diagram The switching regulator operates in Pulse Width Modulation (PWM) mode for greater efficiency at high output loads and it automatically switches to Pulse Frequency Modulation (PFM) power save mode for greater efficiency at low output loads. The V_INT output voltage ripple is specified in the LARA-R2 series Data Sheet [1].](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-26.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 27 of 148 1.6 System function interfaces 1.6.1 Module power-on When the LARA-R2 series modules are in the not-powered mode (switched off, i.e. the VCC module supply is not applied), they can be switched on as following: Rising edge on the VCC input pins to a valid voltage for module supply: the modules switch on if the VCC supply is applied with a rise time of less than 10 ms from 2.1 V to 3.0 V, reaching a proper nominal voltage value within the VCC operating range. Alternately, in case for example the fast rise time on VCC rising edge cannot be guaranteed by the application, LARA-R2 series modules can be switched on from not-powered mode as following: RESET_N input pin is held low by the external application during the VCC rising edge, so that the modules will switch on when the external application releases the RESET_N input pin from the low logic level after that the VCC supply voltage stabilizes at its proper nominal value within the operating range PWR_ON input pin is held low by the external application during the VCC rising edge, so that the modules will switch on when the external application releases the PWR_ON input pin from the low logic level after that the VCC supply voltage stabilizes at its proper nominal value within the operating range When the LARA-R2 series modules are in the power-off mode (i.e. switched off with valid VCC module supply applied), they can be switched on as following: Low pulse on the PWR_ON pin, which is normally set high by an internal pull-up, for a valid time period: the modules start the internal power-on sequence when the external application releases the PWR_ON pin from the low logic level after that it has been set low for an appropriate time period Rising edge on the RESET_N pin, i.e. releasing the pin from the low level, as that the pin is normally set high by an internal pull-up: the modules start the internal power-on sequence when the external application releases the RESET_N pin from the low logic level RTC alarm, i.e. pre-programmed alarm by AT+CALA command (see u-blox AT Commands Manual [2]). As described in Figure 12, the LARA-R2 series PWR_ON input is equipped with an internal active pull-up resistor to the V_BCKP supply: the PWR_ON input voltage thresholds are different from the other generic digital interfaces. Detailed electrical characteristics are described in LARA-R2 series Data Sheet [1]. Baseband Processor15PWR_ONLARA-R2 series2V_BCKPPower-onPower ManagementPower-on10k Figure 12: LARA-R2 series PWR_ON input description](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-27.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 28 of 148 Figure 13 shows the module power-on sequence from the not-powered mode, describing the following phases: The external supply is applied to the VCC module supply inputs, representing the start-up event. The V_BCKP RTC supply output is suddenly enabled by the module as VCC reaches a valid voltage value. The PWR_ON and the RESET_N pins suddenly rise to high logic level due to internal pull-ups. All the generic digital pins of the module are tri-stated until the switch-on of their supply source (V_INT). The internal reset signal is held low: the baseband core and all the digital pins are held in the reset state. The reset state of all the digital pins is reported in the pin description table of LARA-R2 series Data Sheet [1]. When the internal reset signal is released, any digital pin is set in a proper sequence from the reset state to the default operational configured state. The duration of this pins’ configuration phase differs within generic digital interfaces and the USB interface due to host / device enumeration timings (see section 1.9.2). The module is fully ready to operate after all interfaces are configured. VCC V_BCKPPWR_ONRESET_NV_INTInternal ResetSystem StateBB Pads StateInternal Reset → Operational OperationalTristate / Floating Internal ResetOFFONStart of interface configurationModule interfaces are configuredStart-up event Figure 13: LARA-R2 series power-on sequence description The greeting text can be activated by means of +CSGT AT command (see u-blox AT Commands Manual [2]) to notify the external application that the module is ready to operate (i.e. ready to reply to AT commands) and the first AT command can be sent to the module, given that autobauding has to be disabled on the UART to let the module sending the greeting text: the UART has to be configured at fixed baud rate (the baud rate of the application processor) instead of the default autobauding, otherwise the module does not know the baud rate to be used for sending the greeting text (or any other URC) at the end of the internal boot sequence. The Internal Reset signal is not available on a module pin, but the host application can monitor the V_INT pin to sense the start of the LARA-R2 series module power-on sequence. Before the switch-on of the generic digital interface supply source (V_INT) of the module, no voltage driven by an external application should be applied to any generic digital interface of the module. Before the LARA-R2 series module is fully ready to operate, the host application processor should not send any AT command over the AT communication interfaces (USB, UART) of the module.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-28.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 29 of 148 1.6.2 Module power-off LARA-R2 series can be properly switched off by: AT+CPWROFF command (see u-blox AT Commands Manual [2]). The current parameter settings are saved in the module’s non-volatile memory and a proper network detach is performed. An abrupt under-voltage shutdown occurs on LARA-R2 series modules when the VCC module supply is removed. If this occurs, it is not possible to perform the storing of the current parameter settings in the module’s non-volatile memory or to perform the proper network detach. It is highly recommended to avoid an abrupt removal of the VCC supply during LARA-R2 series modules normal operations: the power off procedure must be started by the AT+CPWROFF command, waiting the command response for a proper time period (see u-blox AT Commands Manual [2]), and then a proper VCC supply has to be held at least until the end of the modules’ internal power off sequence, which occurs when the generic digital interfaces supply output (V_INT) is switched off by the module. An abrupt hardware shutdown occurs on LARA-R2 series modules when a low level is applied on RESET_N pin. In this case, the current parameter settings are not saved in the module’s non-volatile memory and a proper network detach is not performed. It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low level on the RESET_N input pin during module normal operation: the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not reply to a specific AT command after a time period longer than the one defined in the u-blox AT Commands Manual [2]. An over-temperature or an under-temperature shutdown occurs on LARA-R2 series modules when the temperature measured within the cellular module reaches the dangerous area, if the optional Smart Temperature Supervisor feature is enabled and configured by the dedicated AT command. For more details see section 1.14.15 and u-blox AT Commands Manual [2], +USTS AT command.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-29.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 31 of 148 1.6.3 Module reset LARA-R2 series modules can be properly reset (rebooted) by: AT+CFUN command (see the u-blox AT Commands Manual [2] for more details). This command causes an “internal” or “software” reset of the module, which is an asynchronous reset of the module baseband processor. The current parameter settings are saved in the module’s non-volatile memory and a proper network detach is performed: this is the proper way to reset the modules. An abrupt hardware reset occurs on LARA-R2 series modules when a low level is applied on the RESET_N input pin for a specific time period. In this case, the current parameter settings are not saved in the module’s non-volatile memory and a proper network detach is not performed. It is highly recommended to avoid an abrupt hardware reset of the module by forcing a low level on the RESET_N input during modules normal operation: the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not provide a reply to a specific AT command after a time period longer than the one defined in the u-blox AT Commands Manual [2]. As described in Figure 15, the RESET_N input pins are equipped with an internal pull-up to the V_BCKP supply. Baseband Processor18RESET_NLARA-R2 series2V_BCKPResetPower ManagementReset10k Figure 15: LARA-R2 series RESET_N input equivalent circuit description For more electrical characteristics details see LARA-R2 series Data Sheet [1]. 1.6.4 Module / host configuration selection Selection of module / host configuration over HOST_SELECT is not supported by “02” product versions. The modules include one pin (HOST_SELECT) to select the module / host application processor configuration: the pin is available to select, enable, connect, disconnect and subsequently re-connect the HSIC interface. LARA-R2 series Data Sheet [1] describes the detailed electrical characteristics of the HOST_SELECT pin.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-31.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 32 of 148 1.7 Antenna interface 1.7.1 Antenna RF interfaces (ANT1 / ANT2) LARA-R2 series modules provide two RF interfaces for connecting the external antennas: The ANT1 represents the primary RF input/output for transmission and reception of LTE/3G/2G RF signals. The ANT1 pin has a nominal characteristic impedance of 50 and must be connected to the primary Tx / Rx antenna through a 50 transmission line to allow proper RF transmission and reception. The ANT2 represents the secondary RF input for the reception of the LTE RF signals for the Down-Link Rx diversity radio technology supported by LARA-R2 series modules as required feature for LTE category 1 UEs. The ANT2 pin has a nominal characteristic impedance of 50 and must be connected to the secondary Rx antenna through a 50 transmission line to allow proper RF reception. 1.7.1.1 Antenna RF interface requirements Table 7, Table 8 and Table 9 summarize the requirements for the antennas RF interfaces (ANT1 / ANT2). See section 0 for suggestions to properly design antennas circuits compliant with these requirements. The antenna circuits affect the RF compliance of the device integrating LARA-R2 series modules with applicable required certification schemes (for more details see section 4). Compliance is guaranteed if the antenna RF interfaces (ANT1 / ANT2) requirements summarized in Table 7, Table 8 and Table 9 are fulfilled. Item Requirements Remarks Impedance 50 nominal characteristic impedance The impedance of the antenna RF connection must match the 50 impedance of the ANT1 port. Frequency Range See the LARA-R2 series Data Sheet [1] The required frequency range of the antenna connected to ANT1 port depends on the operating bands of the used cellular module and the used mobile network. Return Loss S11 < -10 dB (VSWR < 2:1) recommended S11 < -6 dB (VSWR < 3:1) acceptable The Return loss or the S11, as the VSWR, refers to the amount of reflected power, measuring how well the antenna RF connection matches the 50 characteristic impedance of the ANT1 port. The impedance of the antenna termination must match as much as possible the 50 nominal impedance of the ANT1 port over the operating frequency range, reducing as much as possible the amount of reflected power. Efficiency > -1.5 dB ( > 70% ) recommended > -3.0 dB ( > 50% ) acceptable The radiation efficiency is the ratio of the radiated power to the power delivered to antenna input: the efficiency is a measure of how well an antenna receives or transmits. The radiation efficiency of the antenna connected to the ANT1 port needs to be enough high over the operating frequency range to comply with the Over-The-Air (OTA) radiated performance requirements, as Total Radiated Power (TRP) and the Total Isotropic Sensitivity (TIS), specified by applicable related certification schemes. Maximum Gain According to radiation exposure limits The power gain of an antenna is the radiation efficiency multiplied by the directivity: the gain describes how much power is transmitted in the direction of peak radiation to that of an isotropic source. The maximum gain of the antenna connected to ANT1 port must not exceed the herein stated value to comply with regulatory agencies radiation exposure limits. For additional info see sections 4.2.2 and/or 4.3.1 Input Power > 33 dBm ( > 2 W ) The antenna connected to the ANT1 port must support with adequate margin the maximum power transmitted by the modules Table 7: Summary of primary Tx/Rx antenna RF interface (ANT1) requirements](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-32.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 33 of 148 Item Requirements Remarks Impedance 50 nominal characteristic impedance The impedance of the antenna RF connection must match the 50 impedance of the ANT2 port. Frequency Range See the LARA-R2 series Data Sheet [1] The required frequency range of the antennas connected to ANT2 port depends on the operating bands of the used cellular module and the used Mobile Network. Return Loss S11 < -10 dB (VSWR < 2:1) recommended S11 < -6 dB (VSWR < 3:1) acceptable The Return loss or the S11, as the VSWR, refers to the amount of reflected power, measuring how well the antenna RF connection matches the 50 characteristic impedance of the ANT2 port. The impedance of the antenna termination must match as much as possible the 50 nominal impedance of the ANT2 port over the operating frequency range, reducing as much as possible the amount of reflected power. Efficiency > -1.5 dB ( > 70% ) recommended > -3.0 dB ( > 50% ) acceptable The radiation efficiency is the ratio of the radiated power to the power delivered to antenna input: the efficiency is a measure of how well an antenna receives or transmits. The radiation efficiency of the antenna connected to the ANT2 port needs to be enough high over the operating frequency range to comply with the Over-The-Air (OTA) radiated performance requirements, as the TIS, specified by applicable related certification schemes. Table 8: Summary of secondary Rx antenna RF interface (ANT2) requirements Item Requirements Remarks Efficiency imbalance < 0.5 dB recommended < 1.0 dB acceptable The radiation efficiency imbalance is the ratio of the primary (ANT1) antenna efficiency to the secondary (ANT2) antenna efficiency: the efficiency imbalance is a measure of how much better an antenna receives or transmits compared to the other antenna. The radiation efficiency of the secondary antenna needs to be roughly the same of the radiation efficiency of the primary antenna for good RF performance. Envelope Correlation Coefficient < 0.4 recommended < 0.5 acceptable The Envelope Correlation Coefficient (ECC) between the primary (ANT1) and the secondary (ANT2) antenna is an indicator of 3D radiation pattern similarity between the two antennas: low ECC results from antenna patterns with radiation lobes in different directions. The ECC between primary and secondary antenna needs to be enough low to comply with radiated performance requirements specified by related certification schemes. Isolation > 15 dB recommended > 10 dB acceptable The antenna to antenna isolation is the loss between the primary (ANT1) and the secondary (ANT2) antenna: high isolation results from low coupled antennas. The isolation between primary and secondary antenna needs to be high for good RF performance. Table 9: Summary of primary (ANT1) and secondary (ANT2) antennas relationship requirements](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-33.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 34 of 148 1.7.2 Antenna detection interface (ANT_DET) The antenna detection is based on ADC measurement. The ANT_DET pin is an Analog to Digital Converter (ADC) provided to sense the antenna presence. The antenna detection function provided by ANT_DET pin is an optional feature that can be implemented if the application requires it. The antenna detection is forced by the +UANTR AT command. See the u-blox AT Commands Manual [2] for more details on this feature. The ANT_DET pin generates a DC current (for detailed characteristics see the LARA-R2 series Data Sheet [1]) and measures the resulting DC voltage, thus determining the resistance from the antenna connector provided on the application board to GND. So, the requirements to achieve antenna detection functionality are the following: an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used an antenna detection circuit must be implemented on the application board See section 2.4.2 for antenna detection circuit on application board and diagnostic circuit on antenna assembly design-in guidelines. 1.8 SIM interface 1.8.1 SIM card interface LARA-R2 series modules provide a high-speed SIM/ME interface, including automatic detection and configuration of the voltage required by the connected SIM card or chip. Both 1.8 V and 3 V SIM types are supported: activation and deactivation with automatic voltage switch from 1.8 V to 3 V is implemented, according to ISO-IEC 7816-3 specifications. The VSIM supply output pin provides internal short circuit protection to limit start-up current and protect the device in short circuit situations. The SIM driver supports the PPS (Protocol and Parameter Selection) procedure for baud-rate selection, according to the values determined by the SIM Card. 1.8.2 SIM card detection interface (SIM_DET) The GPIO5 pin is by default configured to detect the external SIM card mechanical / physical presence. The pin is configured as input, and it can sense SIM card presence as intended to be properly connected to the mechanical switch of a SIM card holder as described in section 2.5: Low logic level at GPIO5 input pin is recognized as SIM card not present High logic level at GPIO5 input pin is recognized as SIM card present The SIM card detection function provided by GPIO5 pin is an optional feature that can be implemented / used or not according to the application requirements: an Unsolicited Result Code (URC) is generated each time that there is a change of status (for more details see u-blox AT Commands Manual [2], +UGPIOC, +CIND, +CMER). The optional function “SIM card hot insertion/removal” can be additionally configured on the GPIO5 pin by specific AT command (see the u-blox AT Commands Manual [2], +UDCONF=50), in order to enable / disable the SIM interface upon detection of external SIM card physical insertion / removal.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-34.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 35 of 148 1.9 Data communication interfaces LARA-R2 series modules provide the following serial communication interfaces: UART interface: Universal Asynchronous Receiver/Transmitter serial interface available for the communication with a host application processor (AT commands, data communication, FW update by means of FOAT), for FW update by means of the u-blox EasyFlash tool and for diagnostic. (see section 1.9.1) USB interface: Universal Serial Bus 2.0 compliant interface available for the communication with a host application processor (AT commands, data communication, FW update by means of the FOAT feature), for FW update by means of the u-blox EasyFlash tool and for diagnostic. (see section 1.9.2) HSIC interface: High-Speed Inter-Chip USB compliant interface available for the communication with a host application processor (AT commands, data communication, FW update by means of the FOAT feature), for FW update by means of the u-blox EasyFlash tool and for diagnostic. (see section 1.9.3) DDC interface: I2C bus compatible interface available for the communication with u-blox GNSS positioning chips or modules and with external I2C devices as an audio codec. (see section 1.9.4) SDIO interface: Secure Digital Input Output interface available for the communication with compatible u-blox short range radio communication Wi-Fi modules. (see section 1.9.5) 1.9.1 UART interface 1.9.1.1 UART features The UART interface is a 9-wire 1.8 V unbalanced asynchronous serial interface available on all the LARA-R2 series modules, supporting: AT command mode5 Data mode and Online command mode5 Multiplexer protocol functionality (see 1.9.1.5) FW upgrades by means of the FOAT feature (see 1.14.13 and Firmware update application note [23]) FW upgrades by means of the u-blox EasyFlash tool (see the Firmware update application note [23]) Trace log capture (diagnostic purpose) UART interface provides RS-232 functionality conforming to the ITU-T V.24 Recommendation [5], with CMOS compatible signal levels: 0 V for low data bit or ON state, and 1.8 V for high data bit or OFF state (for detailed electrical characteristics see LARA-R2 series Data Sheet [1]), providing: data lines (RXD as output, TXD as input), hardware flow control lines (CTS as output, RTS as input), modem status and control lines (DTR as input, DSR as output, DCD as output, RI as output). LARA-R2 series modules are designed to operate as cellular modems, i.e. as the data circuit-terminating equipment (DCE) according to the ITU-T V.24 Recommendation [5]. A host application processor connected to the module through the UART interface represents the data terminal equipment (DTE). UART signal names of the modules conform to the ITU-T V.24 Recommendation [5]: e.g. TXD line represents data transmitted by the DTE (host processor output) and received by the DCE (module input). LARA-R2 series modules’ UART interface is by default configured in AT command mode: the module waits for AT command instructions and interprets all the characters received as commands to execute. 5 See the u-blox AT Commands Manual [2] for the definition of the command mode, data mode, and online command mode.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-35.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 36 of 148 All the functionalities supported by LARA-R2 series modules can be set and configured by AT commands: AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7], 3GPP TS 27.010 [8] u-blox AT commands (for the complete list and syntax see the u-blox AT Commands Manual [2]) All flow control handshakes are supported by the UART interface and can be set by appropriate AT commands (see u-blox AT Commands Manual [2], &K, +IFC, \Q AT commands): hardware, software, or none flow control. Hardware flow control is enabled by default. The one-shot autobauding is supported: the automatic baud rate detection is performed only once, at module start up. After the detection, the module works at the detected baud rate and the baud rate can only be changed by AT command (see u-blox AT Commands Manual [2], +IPR command). One-shot automatic baud rate recognition (autobauding) is enabled by default. The following baud rates can be configured by AT command (see u-blox AT Commands Manual [2], +IPR): 9600 b/s 19200 b/s 38400 b/s 57600 b/s 115200 b/s, default value when one-shot autobauding is disabled 230400 b/s 460800 b/s 921600 b/s 3000000 b/s 3250000 b/s 6000000 b/s 6500000 b/s Baud rates higher than 460800 b/s cannot be automatically detected by LARA-R2 series modules. The modules support the one-shot automatic frame recognition in conjunction with the one-shot autobauding. The following frame formats can be configured by AT command (see u-blox AT Commands Manual [2], +ICF): 8N1 (8 data bits, No parity, 1 stop bit), default frame configuration with fixed baud rate, see Figure 16 8E1 (8 data bits, even parity, 1 stop bit) 8O1 (8 data bits, odd parity, 1 stop bit) 8N2 (8 data bits, No parity, 2 stop bits) 7E1 (7 data bits, even parity, 1 stop bit) 7O1 (7 data bits, odd parity, 1 stop bit) D0 D1 D2 D3 D4 D5 D6 D7Start of 1-BytetransferStart Bit(Always 0)Possible Start ofnext transferStop Bit(Always 1)tbit = 1/(Baudrate)Normal Transfer, 8N1 Figure 16: Description of UART 8N1 frame format (8 data bits, no parity, 1 stop bit)](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-36.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 37 of 148 1.9.1.2 UART AT interface configuration The UART interface of LARA-R2 series modules is available as AT command interface with the default configuration described in Table 10 (for more details and information about further settings, see the u-blox AT Commands Manual [2]). Interface AT Settings Comments UART interface AT interface: enabled AT command interface is enabled by default on the UART physical interface AT+IPR=0 One-shot autobauding enabled by default on the modules AT+ICF=3,1 8N1 frame format enabled by default AT&K3 HW flow control enabled by default AT&S1 DSR line (Circuit 107 in ITU-T V.24) set ON in data mode6 and set OFF in command mode6 AT&D1 Upon an ON-to-OFF transition of DTR line (Circuit 108/2 in ITU-T V.24), the module (DCE) enters online command mode6 and issues an OK result code AT&C1 DCD line (Circuit 109 in ITU-T V.24) changes in accordance with the Carrier detect status; ON if the Carrier is detected, OFF otherwise MUX protocol: disabled Multiplexing mode is disabled by default and it can be enabled by AT+CMUX command. For more details, see the Mux Implementation Application Note [21]. The following virtual channels are defined: Channel 0: control channel Channel 1 – 5: AT commands / data connection Channel 6: GNSS tunneling7 Table 10: Default UART AT interface configuration 1.9.1.3 UART signal behavior At the module switch-on, before the UART interface initialization (as described in the power-on sequence reported in Figure 13), each pin is first tri-stated and then is set to its related internal reset state8. At the end of the boot sequence, the UART interface is initialized, the module is by default in active-mode, and the UART interface is enabled as AT commands interface. The configuration and the behavior of the UART signals after the boot sequence are described below. See section 1.4 for definition and description of module operating modes referred to in this section. RXD signal behavior The module data output line (RXD) is set by default to the OFF state (high level) at UART initialization. The module holds RXD in the OFF state until the module does not transmit some data. TXD signal behavior The module data input line (TXD) is set by default to the OFF state (high level) at UART initialization. The TXD line is then held by the module in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the TXD input. 6 See the u-blox AT Commands Manual [2] for the definition of the command mode, data mode, and online command mode 7 Not supported by “02” product versions 8 Refer to the pin description table in the LARA-R2 series Data Sheet [1].](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-37.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 38 of 148 CTS signal behavior The module hardware flow control output (CTS line) is set to the ON state (low level) at UART initialization. If the hardware flow control is enabled, as it is by default, the CTS line indicates when the UART interface is enabled (data can be sent and received). The module drives the CTS line to the ON state or to the OFF state when it is either able or not able to accept data from the DTE over the UART (see 1.9.1.4 for more details). If hardware flow control is enabled, then when the CTS line is OFF it does not necessarily mean that the module is in low power idle-mode, but only that the UART is not enabled, as the module could be forced to stay in active-mode for other activities, e.g. related to the network or related to other interfaces. When the multiplexer protocol is active, the CTS line state is mapped to FCon / FCoff MUX command for flow control issues outside the power saving configuration while the physical CTS line is still used as a power state indicator. For more details, see Mux Implementation Application Note [21]. The CTS hardware flow control setting can be changed by AT commands (for more details, see u-blox AT Commands Manual [2], AT&K, AT\Q, AT+IFC, AT+UCTS AT command). When the power saving configuration is enabled by AT+UPSV command and the hardware flow-control is not implemented in the DTE/DCE connection, data sent by the DTE can be lost: the first character sent when the module is in low power idle-mode will not be a valid communication character (see section 1.9.1.4 and in particular the sub-section “Wake up via data reception” for further details). RTS signal behavior The hardware flow control input (RTS line) is set by default to the OFF state (high level) at UART initialization. The module then holds the RTS line in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the RTS input. If the HW flow control is enabled, as it is by default, the module monitors the RTS line to detect permission from the DTE to send data to the DTE itself. If the RTS line is set to the OFF state, any on-going data transmission from the module is interrupted until the subsequent RTS line change to the ON state. The DTE must still be able to accept a certain number of characters after the RTS line is set to the OFF state: the module guarantees the transmission interruption within two characters from RTS state change. Module behavior according to RTS hardware flow control status can be configured by AT commands (for more details, see u-blox AT Commands Manual [2], AT&K, AT\Q, AT+IFC command descriptions). If AT+UPSV=2 is set and HW flow control is disabled, the module monitors the RTS line to manage the power saving configuration (For more details, see section 1.9.1.4 and u-blox AT Commands Manual [2], AT+UPSV): When an OFF-to-ON transition occurs on the RTS input, the UART is enabled and the module is forced to active-mode. After ~20 ms, the switch is completed and data can be received without loss. The module cannot enter low power idle-mode and the UART is enabled as long as the RTS is in the ON state If the RTS input line is set to the OFF state by the DTE, the UART is disabled (held in low power mode) and the module automatically enters low power idle-mode whenever possible DSR signal behavior If AT&S1 is set, as it is by default, the DSR module output line is set by default to the OFF state (high level) at UART initialization. The DSR line is then set to the OFF state when the module is in command mode9 or in online command mode9 and is set to the ON state when the module is in data mode9. If AT&S0 is set, the DSR module output line is set by default to the ON state (low level) at UART initialization and is then always held in the ON state. 9 See the u-blox AT Commands Manual [2] for the definition of the command mode, data mode, and online command mode](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-38.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 39 of 148 DTR signal behavior The DTR module input line is set by default to the OFF state (high level) at UART initialization. The module then holds the DTR line in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the DTR input. Module behavior according to DTR status can be changed by AT command (for more details, see u-blox AT Commands Manual [2], AT&D command description). If AT+UPSV=3 is set, the DTR line is monitored by the module to manage the power saving configuration (for more details, see section 1.9.1.4 and u-blox AT Commands Manual [2], AT+UPSV command): When an OFF-to-ON transition occurs on the DTR input, the UART is enabled and the module is forced to active-mode. After ~20 ms, the switch is completed and data can be received without loss. The module cannot enter low power idle-mode and the UART is enabled as long as the DTR is in the ON state If the DTR input line is set to the OFF state by the DTE, the UART is disabled (held in low power mode) and the module automatically enters low power idle-mode whenever possible DCD signal behavior If AT&C1 is set, as it is by default, the DCD module output line is set by default to the OFF state (high level) at UART initialization. The module then sets the DCD line according to the carrier detect status: ON if the carrier is detected, OFF otherwise. In case of voice calls, DCD is set to the ON state when the call is established. In case of data calls, there are the following scenarios regarding the DCD signal behavior: Packet Switched Data call: Before activating the PPP protocol (data mode) a dial-up application must provide the ATD*99***<context_number># to the module: with this command the module switches from command mode to data mode and can accept PPP packets. The module sets the DCD line to the ON state, then answers with a CONNECT to confirm the ATD*99 command. The DCD ON is not related to the context activation but with the data mode Circuit Switched Data call: To establish a data call, the DTE can send the ATD<number> command to the module which sets an outgoing data call to a remote modem (or another data module). Data can be transparent (non reliable) or non transparent (with the reliable RLP protocol). When the remote DCE accepts the data call, the module DCD line is set to ON and the CONNECT <communication baudrate> string is returned by the module. At this stage the DTE can send characters through the serial line to the data module which sends them through the network to the remote DCE attached to a remote DTE The DCD is set to ON during the execution of the +CMGS, +CMGW, +USOWR, +USODL AT commands requiring input data from the DTE: the DCD line is set to the ON state as soon as the switch to binary/text input mode is completed and the prompt is issued; DCD line is set to OFF as soon as the input mode is interrupted or completed (for more details see the u-blox AT Commands Manual [2]). The DCD line is kept in the ON state, even during the online command mode10, to indicate that the data call is still established even if suspended, while if the module enters command mode10, the DSR line is set to the OFF state. For more details see DSR signal behavior description. For scenarios when the DCD line setting is requested for different reasons (e.g. SMS texting during online command mode10), the DCD line changes to guarantee the correct behavior for all the scenarios. For example, in case of SMS texting in online command mode10, if the data call is released, DCD is kept ON till the SMS command execution is completed (even if the data call release would request DCD set OFF). If AT&C0 is set, the DCD module output line is set by default to the ON state (low level) at UART initialization and is then always held in the ON state. 10 See the u-blox AT Commands Manual [2] for the definition of the command mode, data mode, and online command mode](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-39.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 40 of 148 RI signal behavior The RI module output line is set by default to the OFF state (high level) at UART initialization. Then, during an incoming call, the RI line is switched from the OFF state to the ON state with a 4:1 duty cycle and a 5 s period (ON for 1 s, OFF for 4 s, see Figure 17), until the DTE attached to the module sends the ATA string and the module accepts the incoming data call. The RING string sent by the module (DCE) to the serial port at constant time intervals is not correlated with the switch of the RI line to the ON state. Figure 17: RI behavior during an incoming call The RI line can notify an SMS arrival. When the SMS arrives, the RI line switches from OFF to ON for 1 s (see Figure 18), if the feature is enabled by the AT+CNMI command (see the u-blox AT Commands Manual [2]). Figure 18: RI behavior at SMS arrival This behavior allows the DTE to stay in power saving mode until the DCE related event requests service. For SMS arrival, if several events coincidently occur or in quick succession each event independently triggers the RI line, although the line will not be deactivated between each event. As a result, the RI line may stay to ON for more than 1 s. If an incoming call is answered within less than 1 s (with ATA or if auto-answering is set to ATS0=1) than the RI line is set to OFF earlier. As a result: RI line monitoring cannot be used by the DTE to determine the number of received SMSes. For multiple events (incoming call plus SMS received), the RI line cannot be used to discriminate the two events, but the DTE must rely on the subsequent URCs and interrogate the DCE with proper commands. The RI line can additionally notify all the URCs and all the incoming data (PPP, Direct Link, sockets, FTP), if the feature is enabled by the AT+URING command (for more details see u-blox AT Commands Manual [2]): the RI line is asserted when one of the configured events occur and it remains asserted for 1 s unless another configured event will happen, with the same behavior described in Figure 18. SMS arrives time [s] 0 RI ON RI OFF 1s SMS time [s] 0 RI ON RI OFF 1s 1stime [s]151050RI ONRI OFFCall incomes1stime [s]151050RI ONRI OFFCall incomes](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-40.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 41 of 148 1.9.1.4 UART and power-saving The power saving configuration is controlled by the AT+UPSV command (for the complete description, see u-blox AT Commands Manual [2]). When power saving is enabled, the module automatically enters low power idle-mode whenever possible, and otherwise the active-mode is maintained by the module (see section 1.4 for definition and description of module operating modes referred to in this section). The AT+UPSV command configures both the module power saving and also the UART behavior in relation to the power saving. The conditions for the module entering low power idle-mode also depend on the UART power saving configuration, as the module does not enter the low power idle-mode according to any required activity related to the network (within or outside an active call) or any other required concurrent activity related to the functions and interfaces of the module, including the UART interface. Three different power saving configurations can be set by the AT+UPSV command: AT+UPSV=0, power saving disabled (default configuration) AT+UPSV=1, power saving enabled cyclically AT+UPSV=2, power saving enabled and controlled by the UART RTS input line AT+UPSV=3, power saving enabled and controlled by the UART DTR input line The different power saving configurations that can be set by the +UPSV AT command are described in details in the following subsections. Table 11 summarizes the UART interface communication process in the different power saving configurations, in relation with HW flow control settings and RTS input line status. For more details on the +UPSV AT command description, refer to u-blox AT commands Manual [2]. AT+UPSV HW flow control RTS line DTR line Communication during idle-mode and wake up 0 Enabled (AT&K3) ON ON or OFF Data sent by the DTE are correctly received by the module. Data sent by the module is correctly received by the DTE. 0 Enabled (AT&K3) OFF ON or OFF Data sent by the DTE are correctly received by the module. Data sent by the module is buffered by the module and will be correctly received by the DTE when it is ready to receive data (i.e. RTS line will be ON). 0 Disabled (AT&K0) ON or OFF ON or OFF Data sent by the DTE is correctly received by the module. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise data is lost. 1 Enabled (AT&K3) ON ON or OFF Data sent by the DTE is buffered by the DTE and will be correctly received by the module when it is ready to receive data (when UART is enabled). Data sent by the module is correctly received by the DTE. 1 Enabled (AT&K3) OFF ON or OFF Data sent by the DTE is buffered by the DTE and will be correctly received by the module when it is ready to receive data (when UART is enabled). Data sent by the module is buffered by the module and will be correctly received by the DTE when it is ready to receive data (i.e. RTS line will be ON). 1 Disabled (AT&K0) ON or OFF ON or OFF The first character sent by the DTE is lost by the module, but after ~20 ms the UART and the module are woken up: recognition of subsequent characters is guaranteed only after the UART / module complete wake-up (after ~20 ms). Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise the data is lost. 2 Enabled (AT&K3) ON or OFF ON or OFF Not Applicable: HW flow control cannot be enabled with AT+UPSV=2. 2 Disabled (AT&K0) ON ON or OFF Data sent by the DTE is correctly received by the module. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise data is lost. 2 Disabled (AT&K0) OFF ON or OFF Data sent by the DTE is lost by the module. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise data is lost.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-41.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 43 of 148 set from 40 2G-frames (i.e. 40 x 4.615 ms = 184 ms) up to 65000 2G-frames (i.e. 65000 x 4.615 ms = 300 s). Default value is 2000 2G-frames (i.e. 2000 x 4.615 ms = 9.2 s). Every subsequent character received during the active-mode, resets and restarts the timer; hence the active-mode duration can be extended indefinitely. The CTS output line is driven to the ON or OFF state when the module is either able or not able to accept data from the DTE over the UART: Figure 19 illustrates the CTS output line toggling due to paging reception and data received over the UART, with AT+UPSV=1 configuration. time [s]~9.2 s (default)Data inputCTS ONCTS OFF Figure 19: CTS output pin indicates when module’s UART is enabled (CTS = ON = low level) or disabled (CTS = OFF = high level) AT+UPSV=2: power saving enabled and controlled by the RTS line This configuration can only be enabled with the module hardware flow control disabled (i.e. AT&K0 setting). The UART interface is disabled after the DTE sets the RTS line to OFF. Afterwards, the UART is enabled again, and the module does not enter low power idle-mode, as following: If an OFF-to-ON transition occurs on the RTS input, this causes the UART / module wake-up after ~20 ms: recognition of subsequent characters is guaranteed only after the complete wake-up, and the UART is kept enabled as long as the RTS input line is set to ON. If the module needs to transmit some data (e.g. URC), the UART is temporarily enabled to send data The module automatically enters the low power idle-mode whenever possible but it wakes up to active-mode according to any required activity related to the network (e.g. for the periodic paging reception described in section 1.5.1.4, or for any other required RF transmission / reception) or any other required activity related to the module functions / interfaces (including the UART itself). AT+UPSV=3: power saving enabled and controlled by the DTR line The UART interface is disabled after the DTE sets the DTR line to OFF. Afterwards, the UART is enabled again, and the module does not enter low power idle-mode, as following: If an OFF-to-ON transition occurs on the DTR input, this causes the UART / module wake-up after ~20 ms: recognition of subsequent characters is guaranteed only after the complete wake-up, and the UART is kept enabled as long as the DTR input line is set to ON If the module needs to transmit some data (e.g. URC), the UART is temporarily enabled to send data The module automatically enters the low power idle-mode whenever possible but it wakes up to active-mode according to any required activity related to the network (e.g. for the periodic paging reception described in section 1.5.1.4, or for any other required RF signal transmission or reception) or any other required activity related to the functions / interfaces of the module. The AT+UPSV=3 configuration can be enabled regardless the flow control setting on UART. In particular, the HW flow control can be enabled (AT&K3) or disabled (AT&K0) on UART during this configuration. In both cases, with the AT+UPSV=3 configuration, the CTS line indicates when the module is either able or not able to accept data from the DTE over the UART. When the AT+UPSV=3 configuration is enabled, the DTR input line can still be used by the DTE to control the module behavior according to AT&D command configuration (see u-blox AT commands Manual [2]).](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-43.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 45 of 148 The “wake-up via data reception” feature cannot be disabled. In command mode11, with “wake-up via data reception” enabled and autobauding enabled, the DTE should always send a dummy character to the module before the “AT” prefix set at the beginning of each command line: the first dummy character is ignored if the module is in active-mode, or it represents the wake-up character if the module is in low power idle-mode. In command mode11, with “wake-up via data reception” enabled and autobauding disabled, the DTE should always send a dummy “AT” to the module before each command line: the first dummy “AT” is not ignored if the module is in active-mode (i.e. the module replies “OK”), or it represents the wake up character if the module is in low power idle-mode (i.e. the module does not reply). Additional considerations If the USB is connected and not suspended, the module is kept ready to communicate over USB regardless the AT+UPSV settings, which have instead effect on the UART behavior, as they configure the UART power saving, so that UART is enabled / disabled according to the AT+UPSV settings. To set the AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 configuration over the USB interface, the autobauding must be previously disabled on the UART by the +IPR AT command over the used USB AT interface, and this +IPR AT command configuration must be saved in the module’ non-volatile memory (see the u-blox AT Commands Manual [2]). Then, after the subsequent module re-boot, AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 can be issued over the used AT interface (the USB): all the AT profiles are updated accordingly. 1.9.1.5 Multiplexer protocol (3GPP TS 27.010) LARA-R2 series modules include multiplexer functionality as per 3GPP TS 27.010 [8], on the UART physical link. This is a data link protocol which uses HDLC-like framing and operates between the module (DCE) and the application processor (DTE) and allows a number of simultaneous sessions over the used physical link (UART): the user can concurrently use AT interface on one MUX channel and data communication on another MUX channel. The following virtual channels are defined (for more details, see Mux implementation Application Note [21]): Channel 0: Multiplexer control Channel 1 – 5: AT commands / data connection Channel 6: GNSS data tunneling The GNSS data tunneling channel is not supported by “02” product versions. 11 See the u-blox AT Commands Manual [2] for the definition of the command mode, data mode, and online command mode.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-45.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 46 of 148 1.9.2 USB interface 1.9.2.1 USB features LARA-R2 series modules include a High-Speed USB 2.0 compliant interface with 480 Mb/s maximum data rate, representing the main interface for transferring high speed data with a host application processor, supporting: AT command mode12 Data mode and Online command mode12 FW upgrades by means of the FOAT feature (see 1.14.13 and Firmware update application note [23]) FW upgrades by means of the u-blox EasyFlash tool (see the Firmware update application note [23]) Trace log capture (diagnostic purpose) The module itself acts as a USB device and can be connected to a USB host such as a Personal Computer or an embedded application microprocessor equipped with compatible drivers. The USB_D+/USB_D- lines carry USB serial bus data and signaling according to the Universal Serial Bus Revision 2.0 specification [9], while the VUSB_DET input pin senses the VBUS USB supply presence (nominally 5 V at the source) to detect the host connection and enable the interface. The USB interface of the module is enabled only if a valid voltage is detected by the VUSB_DET input (see the LARA-R2 series Data Sheet [1]). Neither the USB interface, nor the whole module is supplied by the VUSB_DET input: the VUSB_DET senses the USB supply voltage and absorbs few microamperes. The USB interface is controlled and operated with: AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7] u-blox AT commands (for the complete list and syntax see the u-blox AT Commands Manual [2]) The USB interface of LARA-R2 series modules, according to the configured USB profile, can provide different USB functions with various capabilities and purposes, such as: CDC-ACM for AT commands and data communication CDC-ACM for GNSS tunneling CDC-ACM for SAP (SIM Access Profile) CDC-ACM for Diagnostic log CDC-NCM for Ethernet-over-USB CDC-ACM for GNSS tunneling, CDC-ACM for SAP, and CDC-NCM for Ethernet-over-USB are not supported by “02” product versions. The USB profile of LARA-R2 series modules identifies itself by its VID (Vendor ID) and PID (Product ID) combination, included in the USB device descriptor according to the USB 2.0 specification [9]. If the USB is connected to the host before the module is switched on, or if the module is reset (rebooted) with the USB connected to the host, the VID and PID are automatically updated during the boot of the module. First, VID and PID are the following: VID = 0x8087 PID = 0x0716 This VID and PID combination identifies a USB profile where no USB function described above is available: AT commands must not be sent to the module over the USB profile identified by this VID and PID combination. 12 See the u-blox AT Commands Manual [2] for the definition of the command mode, data mode, and online command mode.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-46.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 48 of 148 1.9.2.2 USB in Windows USB drivers are provided for Windows operating system platforms and should be properly installed / enabled by following the step-by-step instructions available in the EVK-R2xx User Guide [3] or in the Windows Embedded OS USB Driver Installation Application Note [4]. USB drivers are available for the following operating system platforms: Windows 7 Windows 8 Windows 8.1 Windows 10 Windows Embedded CE 6.0 Windows Embedded Compact 7 Windows Embedded Compact 2013 The module firmware can be upgraded over the USB interface by means of the FOAT feature, or using the u-blox EasyFlash tool (for more details see Firmware Update Application Note [23]. 1.9.2.3 USB in Linux/Android It is not required to install a specific driver for each Linux-based or Android-based operating system (OS) to use the module USB interface, which is compatible with standard Linux/Android USB kernel drivers. The full capability and configuration of the module USB interface can be reported by running “lsusb –v” or an equivalent command available in the host operating system when the module is connected. 1.9.2.4 USB and power saving The modules automatically enter the USB suspended state when the device has observed no bus traffic for a specific time period according to the USB 2.0 specifications [9]. In suspended state, the module maintains any USB internal status as device. In addition, the module enters the suspended state when the hub port it is attached to is disabled. This is referred to as USB selective suspend. If the USB is suspended and a power saving configuration is enabled by the AT+UPSV command, the module automatically enters the low power idle-mode whenever possible but it wakes up to active-mode according to any required activity related to the network (e.g. the periodic paging reception described in section 1.5.1.4) or any other required activity related to the functions / interfaces of the module. The USB exits suspend mode when there is bus activity. If the USB is connected and not suspended, the module is kept ready to communicate over USB regardless the AT+UPSV settings, therefore the AT+UPSV settings are overruled but they have effect on the power saving configuration of the other interfaces (see 1.9.1.4). The modules are capable of USB remote wake-up signaling: i.e. it may request the host to exit suspend mode or selective suspend by using electrical signaling to indicate remote wake-up, for example due to incoming call, URCs, data reception on a socket. The remote wake-up signaling notifies the host that it should resume from its suspended mode, if necessary, and service the external event. Remote wake-up is accomplished using electrical signaling described in the USB 2.0 specifications [9]. For the module current consumption description with power saving enabled and USB suspended, or with power saving disabled and USB not suspended, see sections 1.5.1.4, 1.5.1.5 and LARA-R2 series Data Sheet [1]. The additional VUSB_DET input pin available on LARA-R2 series modules provides the complete bus detach functionality: the modules disable the USB interface when a low logic level is sensed after a high-to-low logic level transition on the VUSB_DET input pin. This allows a further reduction of the module current consumption, in particular as compared to the USB suspended status during low-power idle mode with power saving enabled.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-48.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 49 of 148 1.9.3 HSIC interface The HSIC interface is not supported by “02” modules product versions except for diagnostic purpose. 1.9.3.1 HSIC features LARA-R2 series modules include a USB High-Speed Inter-Chip compliant interface with maximum 480 Mb/s data rate according to the High-Speed Inter-Chip USB Electrical Specification Version 1.0 [10] and USB Specification Revision 2.0 [9]. The module itself acts as a device and can be connected to any compatible host. The HSIC interface provides: AT command mode13 Data mode and Online command mode13 FW upgrades by means of the FOAT feature (see 1.14.13 and Firmware update application note [23]) FW upgrades by means of the u-blox EasyFlash tool (see the Firmware update application note [23]) Trace log capture (diagnostic purpose) The HSIC interface consists of a bi-directional DDR data line (HSIC_DATA) for transmitting and receiving data synchronously with the bi-directional strobe line (HSIC_STRB). The modules include also the HOST_SELECT pin to select the module / host application processor configuration: the pin is available to select, enable, connect, disconnect and subsequently re-connect the HSIC interface. The USB interface is controlled and operated with: AT commands according to 3GPP TS 27.007 [6], 3GPP TS 27.005 [7] u-blox AT commands (for the complete list and syntax see the u-blox AT Commands Manual [2]) 13 See the u-blox AT Commands Manual [2] for the definition of the command mode, data mode, and online command mode.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-49.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 50 of 148 1.9.4 DDC (I2C) interface Communication with u-blox GNSS receivers over I2C bus compatible Display Data Channel interface, AssistNow embedded GNSS positioning aiding, CellLocate® positioning through cellular info, and custom functions over GPIOs for the integration with u-blox positioning chips / modules are not supported by LARA-R2 series modules “02” product versions. The SDA and SCL pins represent an I2C bus compatible Display Data Channel (DDC) interface available for communication with u-blox GNSS chips / modules, communication with other external I2C devices as audio codecs. The AT commands interface is not available on the DDC (I2C) interface. DDC (I2C) slave-mode operation is not supported: the LARA-R2 series module can act as I2C master that can communicate with more I2C slaves in accordance to the I2C bus specifications [11]. The DDC (I2C) interface pins of the module, serial data (SDA) and serial clock (SCL), are open drain outputs conforming to the I2C bus specifications [11]. u-blox has implemented special features to ease the design effort required for the integration of a u-blox cellular module with a u blox GNSS receiver. Combining a u-blox cellular module with a u-blox GNSS receiver allows designers to have full access to the positioning receiver directly via the cellular module: it relays control messages to the GNSS receiver via a dedicated DDC (I2C) interface. A 2nd interface connected to the positioning receiver is not necessary: AT commands via the UART or USB serial interface of the cellular module allows a fully control of the GNSS receiver from any host processor. The modules feature embedded GNSS aiding that is a set of specific features developed by u-blox to enhance GNSS performance, decreasing the Time To First Fix (TTFF), thus allowing to calculate the position in a shorter time with higher accuracy. These GNSS aiding types are available: Local aiding AssistNow Online AssistNow Offline AssistNow Autonomous The embedded GNSS aiding features can be used only if the DDC (I2C) interface of the cellular module is connected to the u-blox GNSS receivers. The cellular modules provide additional custom functions over GPIO pins to improve the integration with u-blox positioning chips and modules. GPIO pins can handle: GNSS receiver power-on/off: “GNSS supply enable” function provided by GPIO2 improves the positioning receiver power consumption. When the GNSS functionality is not required, the positioning receiver can be completely switched off by the cellular module that is controlled by AT commands The wake up from idle-mode when the GNSS receiver is ready to send data: “GNSS Tx data ready” function provided by GPIO3 improves the cellular module power consumption. When power saving is enabled in the cellular module by the AT+UPSV command and the GNSS receiver does not send data by the DDC (I2C) interface, the module automatically enters idle-mode whenever possible. With the “GNSS Tx data ready” function the GNSS receiver can indicate to the cellular module that it is ready to send data by the DDC (I2C) interface: the positioning receiver can wake up the cellular module if it is in idle-mode, so the cellular module does not lose the data sent by the GNSS receiver even if power saving is enabled](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-50.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 51 of 148 The RTC synchronization signal to the GNSS receiver: “GNSS RTC sharing” function provided by GPIO4 improves GNSS receiver performance, decreasing the Time To First Fix (TTFF), and thus allowing to calculate the position in a shorter time with higher accuracy. When GPS local aiding is enabled, the cellular module automatically uploads data such as position, time, ephemeris, almanac, health and ionospheric parameter from the positioning receiver into its local memory, and restores this to the GNSS receiver at the next power up of the positioning receiver For more details regarding the handling of the DDC (I2C) interface, the GNSS aiding features and the GNSS related functions over GPIOs, see section 1.12, to the u-blox AT Commands Manual [2] (AT+UGPS, AT+UGPRF, AT+UGPIOC AT commands) and the GNSS Implementation Application Note [22]. “GNSS Tx data ready” and “GNSS RTC sharing” functions are not supported by all u-blox GNSS receivers HW or ROM/FW versions. See the GNSS Implementation Application Note [22] or to the Hardware Integration Manual of the u-blox GNSS receivers for the supported features. As additional improvement for the GNSS receiver performance, the V_BCKP supply output of the cellular modules can be connected to the V_BCKP supply input pin of u-blox positioning chips and modules to provide the supply for the GNSS real time clock and backup RAM when the VCC supply of the cellular module is within its operating range and the VCC supply of the GNSS receiver is disabled. This enables the u-blox positioning receiver to recover from a power breakdown with either a hot start or a warm start (depending on the duration of the GNSS receiver VCC outage) and to maintain the configuration settings saved in the backup RAM. 1.9.5 SDIO interface Secure Digital Input Output interface is not supported by LARA-R2 series modules “02” product versions. LARA-R2 series modules include a 4-bit Secure Digital Input Output interface (SDIO_D0, SDIO_D1, SDIO_D2, SDIO_D3, SDIO_CLK, SDIO_CMD) designed to communicate with an external u-blox short range Wi-Fi module: the cellular module acts as an SDIO host controller which can communicate over the SDIO bus with a compatible u-blox short range radio communication Wi-Fi module acting as SDIO device. The SDIO interface is the only one interface of LARA-R2 series modules dedicated for communication between the u-blox cellular module and the u-blox short range Wi-Fi module. The AT commands interface is not available on the SDIO interface of LARA-R2 series modules. Combining a u-blox cellular module with a u-blox short range communication module gives designers full access to the Wi-Fi module directly via the cellular module, so that a second interface connected to the Wi-Fi module is not necessary. AT commands via the AT interfaces of the cellular module allows a full control of the Wi-Fi module from any host processor, because Wi-Fi control messages are relayed to the Wi-Fi module via the dedicated SDIO interface. u-blox has implemented special features in the cellular modules to ease the design effort for the integration of a u-blox cellular module with a u-blox short range Wi-Fi module to provide Router functionality. Additional custom function over GPIO pins is designed to improve the integration with u-blox Wi-Fi modules: Wi-Fi enable Switch-on / switch-off the Wi-Fi Wi-Fi enable function over GPIO is not supported by LARA-R2 series modules “02” product versions.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-51.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 52 of 148 1.10 Audio interface Audio is not supported by LARA-R204 module “02” product version. 1.10.1 Digital audio interface LARA-R2 series modules include a 4-wire I2S digital audio interface (I2S_TXD data output, I2S_RXD data input, I2S_CLK clock input/output, I2S_WA world alignment / synchronization signal input/output), which can be configured by AT command for digital audio communication with external digital audio devices as an audio codec (for more details see the u-blox AT Commands Manual [2], +UI2S AT command). The I2S interface can be alternatively set in different modes, by <I2S_mode> parameter of AT+UI2S command: PCM mode (short synchronization signal): I2S word alignment signal is set high for 1 or 2 clock cycles for the synchronization, and then is set low for 16 clock cycles according to the 17 or 18 clock cycles frame length. Normal I2S mode (long synchronization signal): I2S word alignment is set high / low with a 50% duty cycle (high for 16 clock cycles / low for 16 clock cycles, according to the 32 clock cycles frame length). The I2S interface can be alternatively set in different roles, by <I2S_Master_Slave> parameter of AT+UI2S: Master mode Slave mode The sample rate of transmitted/received words, which corresponds to the I2S word alignment / synchronization signal frequency, can be alternatively set by the <I2S_sample_rate> parameter of AT+UI2S to: 8 kHz 11.025 kHz 12 kHz 16 kHz 22.05 kHz 24 kHz 32 kHz 44.1 kHz 48 kHz The modules support I2S transmit and I2S receive data 16-bit words long, linear, mono (or also dual mono in Normal I2S mode). Data is transmitted and read in 2’s complement notation. MSB is transmitted and read first. I2S clock signal frequency depends on the frame length, the sample rate and the selected mode of operation: 17 x <I2S_sample_rate> or 18 x <I2S_sample_rate> in PCM mode (short synchronization signal) 16 x 2 x <I2S_sample_rate> in Normal I2S mode (long synchronization signal) For the complete description of the possible configurations and settings of the I2S digital audio interface for PCM and Normal I2S modes refer to the u-blox AT Commands Manual [2], +UI2S AT command.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-52.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 53 of 148 1.11 Clock output LARA-R2 series modules provide master digital clock output function on GPIO6 pin, which can be configured to provide a 13 MHz or 26 MHz square wave. This is mainly designed to feed the master clock input of an external audio codec, as the clock output can be configured in “Audio dependent” mode (generating the square wave only when the audio path is active), or in “Continuous” mode. For more details see the u-blox AT Commands Manual [2], +UMCLK AT command. 1.12 General Purpose Input/Output (GPIO) LARA-R2 series modules include 9 pins (GPIO1-GPIO5, I2S_TXD, I2S_RXD, I2S_CLK, I2S_WA) which can be configured as General Purpose Input/Output or to provide custom functions via u-blox AT commands (for more details see the u-blox AT Commands Manual [2], +UGPIOC, +UGPIOR, +UGPIOW AT commands), as summarized in Table 12. Function Description Default GPIO Configurable GPIOs Network status indication Network status: registered home network, registered roaming, data transmission, no service -- GPIO1-GPIO4 GNSS supply enable14 Enable/disable the supply of u-blox GNSS receiver connected to the cellular module -- GPIO1-GPIO4 GNSS data ready14 Sense when u-blox GNSS receiver connected to the module is ready for sending data by the DDC (I2C) -- GPIO3 GNSS RTC sharing14 RTC synchronization signal to the u-blox GNSS receiver connected to the cellular module -- GPIO4 SIM card detection External SIM card physical presence detection GPIO5 GPIO5 SIM card hot insertion/removal Enable / disable SIM interface upon detection of external SIM card physical insertion / removal -- GPIO5 I2S digital audio interface15 I2S digital audio interface I2S_RXD, I2S_TXD, I2S_CLK, I2S_WA I2S_RXD, I2S_TXD, I2S_CLK, I2S_WA Wi-Fi control14 Control of an external Wi-Fi chip or module -- -- General purpose input Input to sense high or low digital level -- All General purpose output Output to set the high or the low digital level GPIO4 All Pin disabled Tri-state with an internal active pull-down enabled GPIO1-GPIO3 All Table 12: LARA-R2 series GPIO custom functions configuration 1.13 Reserved pins (RSVD) LARA-R2 series modules have pins reserved for future use, named RSVD: they can all be left unconnected on the application board, except the RSVD pin number 33 that must be externally connected to ground 14 Not supported by “02” product versions. 15 Not supported by LARA-R204 module “02” product version.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-53.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 54 of 148 1.14 System features 1.14.1 Network indication GPIOs can be configured by the AT command to indicate network status (for further details see section 1.12 and to u-blox AT Commands Manual [2], GPIO commands): No service (no network coverage or not registered) Registered 2G / LTE home network Registered 2G / LTE visitor network (roaming) Call enabled (RF data transmission / reception) 1.14.2 Antenna detection The antenna detection function provided by the ANT_DET pin is based on an ADC measurement as optional feature that can be implemented if the application requires it. The antenna supervisor is forced by the +UANTR AT command (see the u-blox AT Commands Manual [2] for more details). The requirements to achieve antenna detection functionality are the following: an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used an antenna detection circuit must be implemented on the application board See section 1.7.2 for detailed antenna detection interface functional description and see section 2.4.2 for detection circuit on application board and diagnostic circuit on antenna assembly design-in guidelines. 1.14.3 Jamming detection Congestion detection (i.e. jamming detection) is not supported by “02” product versions. In real network situations modules can experience various kind of out-of-coverage conditions: limited service conditions when roaming to networks not supporting the specific SIM, limited service in cells which are not suitable or barred due to operators’ choices, no cell condition when moving to poorly served or highly interfered areas. In the latter case, interference can be artificially injected in the environment by a noise generator covering a given spectrum, thus obscuring the operator’s carriers entitled to give access to the LTE/3G/2G service. The congestion (i.e. jamming) detection feature can be enabled and configured by the +UCD AT command: the feature consists of detecting an anomalous source of interference and signaling the start and stop of such conditions to the host application processor with an unsolicited indication, which can react appropriately by e.g. switching off the radio transceiver of the module (i.e. configuring the module in “airplane mode” by means of the +CFUN AT command) in order to reduce power consumption and monitoring the environment at constant periods (for more details see the u-blox AT Commands Manual [2], +UCD AT command).](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-54.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 55 of 148 1.14.4 Dual stack IPv4/IPv6 LARA-R2 series support both Internet Protocol version 4 and Internet Protocol version 6 in parallel. For more details about dual stack IPv4/IPv6 see the u-blox AT Commands Manual [2]. 1.14.5 TCP/IP and UDP/IP LARA-R2 series modules provide embedded TCP/IP and UDP/IP protocol stack: a PDP context can be configured, established and handled via the data connection management packet switched data commands. LARA-R2 series modules provide Direct Link mode to establish a transparent end-to-end communication with an already connected TCP or UDP socket via serial interfaces. In Direct Link mode, data sent to the serial interface from an external application processor is forwarded to the network and vice-versa. For more details about embedded TCP/IP and UDP/IP functionalities see the u-blox AT Commands Manual [2] 1.14.6 FTP LARA-R2 series provide embedded File Transfer Protocol (FTP) services. Files are read and stored in the local file system of the module. FTP files can also be transferred using FTP Direct Link: FTP download: data coming from the FTP server is forwarded to the host processor via serial interfaces (for FTP without Direct Link mode the data is always stored in the module’s Flash File System) FTP upload: data coming from the host processor via serial interfaces is forwarded to the FTP server (for FTP without Direct Link mode the data is read from the module’s Flash File System) When Direct Link is used for a FTP file transfer, only the file content pass through USB / UART serial interface, whereas all the FTP commands handling is managed internally by the FTP application. For more details about embedded FTP functionalities see u-blox AT Commands Manual [2]. 1.14.7 HTTP LARA-R2 series modules provide the embedded Hyper-Text Transfer Protocol (HTTP) services via AT commands for sending requests to a remote HTTP server, receiving the server response and transparently storing it in the module’s Flash File System (FFS). For more details about embedded HTTP functionalities see the u-blox AT Commands Manual [2].](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-55.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 56 of 148 1.14.8 SSL/TLS LARA-R2 series modules support the Secure Sockets Layer (SSL) / Transport Layer Security (TLS) with certificate key sizes up to 4096 bits to provide security over the FTP and HTTP protocols. The SSL/TLS support provides different connection security aspects: Server authentication: use of the server certificate verification against a specific trusted certificate or a trusted certificates list Client authentication: use of the client certificate and the corresponding private key Data security and integrity: data encryption and Hash Message Authentication Code (HMAC) generation The security aspects used during a connection depend on the SSL/TLS configuration and features supported. Table 13 contains the settings of the default SSL/TLS profile and Table 14 to Table 18 report the main SSL/TLS supported capabilities of the products. For a complete list of supported configurations and settings see the u-blox AT Commands Manual [2]. Settings Value Meaning Certificates validation level Level 0 The server certificate will not be checked or verified Minimum SSL/TLS version Any The server can use any of the TLS1.0/TLS1.1/TLS1.2 versions for the connection Cipher suite Automatic The cipher suite will be negotiated in the handshake process Trusted root certificate internal name None No certificate will be used for the server authentication Expected server host-name None No server host-name is expected Client certificate internal name None No client certificate will be used Client private key internal name None No client private key will be used Client private key password None No client private key password will be used Pre-shared key None No pre-shared key password will be used Table 13: Default SSL/TLS profile SSL/TLS Version SSL 2.0 NO SSL 3.0 YES TLS 1.0 YES TLS 1.1 YES TLS 1.2 YES Table 14: SSL/TLS version support Algorithm RSA YES PSK YES Table 15: Authentication Algorithm RC4 NO DES YES 3DES YES AES128 YES AES256 YES Table 16: Encryption](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-56.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 57 of 148 Algorithm MD5 NO SHA/SHA1 YES SHA256 YES SHA384 YES Table 17: Message digest Description Registry value TLS_RSA_WITH_AES_128_CBC_SHA 0x00,0x2F YES TLS_RSA_WITH_AES_128_CBC_SHA256 0x00,0x3C YES TLS_RSA_WITH_AES_256_CBC_SHA 0x00,0x35 YES TLS_RSA_WITH_AES_256_CBC_SHA256 0x00,0x3D YES TLS_RSA_WITH_3DES_EDE_CBC_SHA 0x00,0x0A YES TLS_RSA_WITH_RC4_128_MD5 0x00,0x04 NO TLS_RSA_WITH_RC4_128_SHA 0x00,0x05 NO TLS_PSK_WITH_AES_128_CBC_SHA 0x00,0x8C YES TLS_PSK_WITH_AES_256_CBC_SHA 0x00,0x8D YES TLS_PSK_WITH_3DES_EDE_CBC_SHA 0x00,0x8B YES TLS_RSA_PSK_WITH_AES_128_CBC_SHA 0x00,0x94 YES TLS_RSA_PSK_WITH_AES_256_CBC_SHA 0x00,0x95 YES TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA 0x00,0x93 YES TLS_PSK_WITH_AES_128_CBC_SHA256 0x00,0xAE YES TLS_PSK_WITH_AES_256_CBC_SHA384 0x00,0xAF YES TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 0x00,0xB6 YES TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 0x00,0xB7 YES Table 18: TLS cipher suite registry 1.14.9 Bearer Independent Protocol The Bearer Independent Protocol (BIP) is a mechanism by which a cellular module provides a SIM with access to the data bearers supported by the network. With the BIP for Over-the-Air SIM provisioning, the data transfer from and to the SIM uses either an already active PDP context or a new PDP context established with the APN provided by the SIM card. For more details, see the u-blox AT Commands Manual [2].. 1.14.10 AssistNow clients and GNSS integration AssistNow clients and u-blox GNSS receiver integration are not supported by “02” product versions. For customers using u-blox GNSS receivers, the LARA-R2 series cellular modules feature embedded AssistNow clients. AssistNow A-GPS provides better GNSS performance and faster Time-To-First-Fix. The clients can be enabled and disabled with an AT command (see the u-blox AT Commands Manual [2]). LARA-R2 series cellular modules act as a stand-alone AssistNow client, making AssistNow available with no additional requirements for resources or software integration on an external host micro controller. Full access to u-blox positioning receivers is available via the cellular modules, through a dedicated DDC (I2C) interface, while the available GPIOs can handle the positioning chipset / module power-on/off. This means that the cellular module and the GNSS receiver can be controlled through a single serial port from any host processor.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-57.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 60 of 148 The use of hybrid positioning requires a connection via the DDC (I2C) bus between the cellular modules and the u-blox GNSS receiver (see section 2.6.4). See GNSS Implementation Application Note [22] for the complete description of the feature. u-blox is extremely mindful of user privacy. When a position is sent to the CellLocate® server u-blox is unable to track the SIM used or the specific device. 1.14.12 Wi-Fi integration u-blox short range communication Wi-Fi modules integration is not supported by “02” product versions. Full access to u-blox short range communication Wi-Fi modules is available through a dedicated SDIO interface (see sections 1.9.5 and 2.6.5). This means that combining a LARA-R2 series cellular module with a u-blox short range communication module gives designers full access to the Wi-Fi module directly via the cellular module, so that a second interface connected to the Wi-Fi module is not necessary. AT commands via the AT interfaces of the cellular module (UART, USB) allows a full control of the Wi-Fi module from any host processor, because Wi-Fi control messages are relayed to the Wi-Fi module via the dedicated SDIO interface. All the management software for Wi-Fi module operations runs inside the cellular module in addition to those required for cellular-only operation. 1.14.13 Firmware upgrade Over AT (FOAT) This feature allows upgrading the module firmware over USB / UART serial interfaces, using AT commands. The +UFWUPD AT command triggers a reboot followed by the upgrade procedure at specified a baud rate A special boot loader on the module performs firmware installation, security verifications and module reboot Firmware authenticity verification is performed via a security signature during the download. The firmware is then installed, overwriting the current version. In case of power loss during this phase, the boot loader detects a fault at the next wake-up, and restarts the firmware download. After completing the upgrade, the module is reset again and wakes-up in normal boot For more details about Firmware update Over AT procedure see the Firmware Update Application Note [23] and the u-blox AT Commands Manual [2], +UFWUPD AT command. 1.14.14 Firmware update Over The Air (FOTA) This feature allows upgrading the module firmware over the LTE/3G/2G air interface. In order to reduce the amount of data to be transmitted over the air, the implemented FOTA feature requires downloading only a “delta file” instead of the full firmware. The delta file contains only the differences between the two firmware versions (old and new), and is compressed. The firmware update procedure can be triggered using dedicated AT command with the delta file stored in the module file system via over the air FTP. For more details about Firmware update Over The Air procedure see the Firmware Update Application Note [23] and the u-blox AT Commands Manual [2], .](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-60.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 61 of 148 1.14.15 Smart temperature management Cellular modules – independently from the specific model – always have a well-defined operating temperature range. This range should be respected to guarantee full device functionality and long life span. Nevertheless there are environmental conditions that can affect operating temperature, e.g. if the device is located near a heating/cooling source, if there is/is not air circulating, etc. The module itself can also influence the environmental conditions; such as when it is transmitting at full power. In this case its temperature increases very quickly and can raise the temperature nearby. The best solution is always to properly design the system where the module is integrated. Nevertheless an extra check/security mechanism embedded into the module is a good solution to prevent operation of the device outside of the specified range. Smart Temperature Supervisor (STS) The Smart Temperature Supervisor is activated and configured by a dedicated AT+USTS command. See u-blox AT Commands Manual [2] for more details. An URC indication is provided once the feature is enabled and at the module power on. The cellular module measures the internal temperature (Ti) and its value is compared with predefined thresholds to identify the actual working temperature range. Temperature measurement is done inside the module: the measured value could be different from the environmental temperature (Ta). Warningareat-1 t+1 t+2t-2Valid temperature rangeSafeareaDangerousarea Dangerousarea Warningarea Figure 23: Temperature range and limits The entire temperature range is divided into sub-regions by limits (see Figure 23) named t-2, t-1, t+1 and t+2. Within the first limit, (t-1 < Ti < t+1), the cellular module is in the normal working range, the Safe Area In the Warning Area, (t-2 < Ti < t.1) or (t+1 < Ti < t+2), the cellular module is still inside the valid temperature range, but the measured temperature is approaching the limit (upper or lower). The module sends a warning to the user (through the active AT communication interface), which can take, if possible, the necessary actions to return to a safer temperature range or simply ignore the indication. The module is still in a valid and good working condition Outside the valid temperature range, (Ti < t-2) or (Ti > t+2), the device is working outside the specified range and represents a dangerous working condition. This condition is indicated and the device shuts down to avoid damage For security reasons the shutdown is suspended in case an emergency call is in progress. In this case the device switches off at call termination. The user can decide at anytime to enable/disable the Smart Temperature Supervisor feature. If the feature is disabled there is no embedded protection against disallowed temperature conditions.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-61.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification System description Page 63 of 148 Threshold definitions When the application of cellular module operates at extreme temperatures with Smart Temperature Supervisor enabled, the user should note that outside the valid temperature range the device will automatically shut down as described above. The input for the algorithm is always the temperature measured within the cellular module (Ti, internal). This value can be higher than the working ambient temperature (Ta, ambient), since (for example) during transmission at maximum power a significant fraction of DC input power is dissipated as heat. This behavior is partially compensated by the definition of the upper shutdown threshold (t+2) that is slightly higher than the declared environmental temperature limit. The sensor measures board temperature inside the shields, which can differ from ambient temperature. 1.14.16 Power Saving The power saving configuration is by default disabled, but it can be enabled using the AT+UPSV command (for the complete description of the AT+UPSV command, see the u-blox AT Commands Manual [2]). When power saving is enabled, the module automatically enters the low power idle-mode whenever possible, reducing current consumption (see section 1.5.1.4, LARA-R2 series Data Sheet [1]). During the low power idle-mode, the module is temporarily not ready to communicate with an external device, as it is configured to reduce power consumption. The module wakes up from low power idle-mode to active-mode in the following events: Automatic periodic monitoring of the paging channel for the paging block reception according to network conditions (see 1.5.1.4, 1.9.1.4) Automatic periodic enable of the UART interface to receive / send data, with AT+UPSV=1 (see 1.9.1.4) RTS input set ON by the host DTE, with HW flow control disabled and AT+UPSV=2 (see 1.9.1.4) DTR input set ON by the host DTE, with AT+UPSV=3 (see 1.9.1.4) USB detection, applying 5 V (typ.) to VUSB_DET input (see 1.9.2) The connected USB host forces a remote wakeup of the module as USB device (see 1.9.2.4) The connected u-blox GNSS receiver forces a wakeup of the cellular module using the GNSS Tx data ready function over GPIO3 (see 1.9.4) The connected SDIO device forces a wakeup of the module as SDIO host (see 1.9.5) A preset RTC alarm occurs (see u-blox AT Commands Manual [2], AT+CALA) For the definition and the description of LARA-R2 series modules operating modes, including the events forcing transitions between the different operating modes, see the section 1.4.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-63.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 66 of 148 the typical choice when the charging source has a relatively low nominal voltage (~5 V). If both a permanent primary supply / charging source (e.g. ~12 V) and a rechargeable back-up battery (e.g. 3.7 V Li-Pol) are available at the same time as possible supply source, then a proper charger / regulator with integrated power path management function can be selected to supply the module while simultaneously and independently charging the battery. See sections 2.2.1.8, 2.2.1.9, and 2.2.1.4, 2.2.1.6, 2.2.1.7, 0, 2.2.1.12 for specific design-in. An appropriate primary (not rechargeable) battery can be selected taking into account the maximum current specified in LARA-R2 series Data Sheet [1] during connected-mode, considering that primary cells might have weak power capability. See sections 2.2.1.5, 2.2.1.6, 0, and 2.2.1.12 for specific design-in. The usage of more than one DC supply at the same time should be carefully evaluated: depending on the supply source characteristics, different DC supply systems can result as mutually exclusive. The usage of a regulator or a battery not able to support the highest peak of VCC current consumption specified in the LARA-R2 series Data Sheet [1] is generally not recommended. However, if the selected regulator or battery is not able to support the highest peak current of the module, it must be able to support with adequate margin at least the highest averaged current consumption value specified in the LARA-R2 series Data Sheet [1]. The additional energy required by the module during a 2G Tx slot can be provided by an appropriate bypass tank capacitor or super-capacitor with very large capacitance and very low ESR placed close to the module VCC pins. Depending on the actual capability of the selected regulator or battery, the required capacitance can be considerably larger than 1 mF and the required ESR can be in the range of few tens of m. Carefully evaluate the super-capacitor characteristics since aging and temperature may affect the actual characteristics. The following sections highlight some design aspects for each of the supplies listed above providing application circuit design-in compliant with the module VCC requirements summarized in Table 6. 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator The use of a switching regulator is suggested when the difference from the available supply rail to the VCC value is high: switching regulators provide good efficiency transforming a 12 V or greater voltage supply to the typical 3.8 V value of the VCC supply. The characteristics of the switching regulator connected to VCC pins should meet the following prerequisites to comply with the module VCC requirements summarized in Table 6: Power capability: the switching regulator with its output circuit must be capable of providing a voltage value to the VCC pins within the specified operating range and must be capable of delivering to VCC pins the specified maximum peak / pulse current consumption during Tx burst at maximum Tx power specified in LARA-R2 series Data Sheet [1] Low output ripple: the switching regulator together with its output circuit must be capable of providing a clean (low noise) VCC voltage profile. High switching frequency: for best performance and for smaller applications it is recommended to select a switching frequency ≥ 600 kHz (since L-C output filter is typically smaller for high switching frequency). The use of a switching regulator with a variable switching frequency or with a switching frequency lower than 600 kHz must be carefully evaluated since this can produce noise in the VCC voltage profile and therefore negatively impact LTE/2G modulation spectrum performance. An additional L-C low-pass filter between the switching regulator output to VCC supply pins can mitigate the ripple on VCC, but adds extra voltage drop due to resistive losses on series inductors. PWM mode operation: it is preferable to select regulators with Pulse Width Modulation (PWM) mode. While in connected-mode, the Pulse Frequency Modulation (PFM) mode and PFM/PWM modes transitions must be avoided to reduce noise on VCC voltage profile. Switching regulators can be used that are able to switch between low ripple PWM mode and high ripple PFM mode, provided that the mode transition occurs when the module changes status from the idle/active-modes to connected-mode. It is permissible to use a regulator that switches from the PWM mode to the burst or PFM mode at an appropriate current threshold.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-66.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 69 of 148 2.2.1.3 Guidelines for VCC supply circuit design using a Low Drop-Out (LDO) linear regulator The use of a linear regulator is suggested when the difference from the available supply rail and the VCC value is low: linear regulators provide high efficiency when transforming a 5 V supply to a voltage value within the module VCC normal operating range. The characteristics of the LDO linear regulator connected to the VCC pins should meet the following prerequisites to comply with the module VCC requirements summarized in Table 6: Power capabilities: the LDO linear regulator with its output circuit must be capable of providing a voltage value to the VCC pins within the specified operating range and must be capable of delivering to VCC pins the maximum peak / pulse current consumption during Tx burst at maximum Tx power specified in LARA-R2 series Data Sheet [1]. Power dissipation: the power handling capability of the LDO linear regulator must be checked to limit its junction temperature to the maximum rated operating range (i.e. check the voltage drop from the max input voltage to the min output voltage to evaluate the power dissipation of the regulator). Figure 28 and the components listed in Table 21 show an example of a high reliability power supply circuit, where the VCC module supply is provided by an LDO linear regulator capable of delivering the specified highest peak / pulse current, with proper power handling capability. The regulator described in this example supports a wide input voltage range, and it includes internal circuitry for reverse battery protection, current limiting, thermal limiting and reverse current protection. It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below the maximum limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit described in Figure 28 and Table 21). This reduces the power on the linear regulator and improves the whole thermal design of the supply circuit. 5VC1IN OUTADJGND12453C2R1R2U1SHDNLARA-R2 series52 VCC53 VCC51 VCCGND Figure 28: Example of high reliability VCC supply application circuit using an LDO linear regulator Reference Description Part Number - Manufacturer C1, C2 10 µF Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 - Murata R1 9.1 k Resistor 0402 5% 0.1 W RC0402JR-079K1L - Yageo Phycomp R2 3.9 k Resistor 0402 5% 0.1 W RC0402JR-073K9L - Yageo Phycomp U1 LDO Linear Regulator ADJ 3.0 A LT1764AEQ#PBF - Linear Technology Table 21: Components for high reliability VCC supply application circuit using an LDO linear regulator](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-69.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 71 of 148 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable Li-Ion or Li-Pol battery Rechargeable Li-Ion or Li-Pol batteries connected to the VCC pins should meet the following prerequisites to comply with the module VCC requirements summarized in Table 6: Maximum pulse and DC discharge current: the rechargeable Li-Ion battery with its related output circuit connected to the VCC pins must be capable of delivering a pulse current as the maximum peak / pulse current consumption during Tx burst at maximum Tx power specified in LARA-R2 series Data Sheet [1] and must be capable of extensively delivering a DC current as the maximum average current consumption specified in LARA-R2 series Data Sheet [1]. The maximum discharge current is not always reported in the data sheets of batteries, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour. DC series resistance: the rechargeable Li-Ion battery with its output circuit must be capable of avoiding a VCC voltage drop below the operating range summarized in Table 6 during transmit bursts. 2.2.1.5 Guidelines for VCC supply circuit design using a primary (disposable) battery The characteristics of a primary (non-rechargeable) battery connected to VCC pins should meet the following prerequisites to comply with the module VCC requirements summarized in Table 6: Maximum pulse and DC discharge current: the non-rechargeable battery with its related output circuit connected to the VCC pins must be capable of delivering a pulse current as the maximum peak current consumption during Tx burst at maximum Tx power specified in LARA-R2 series Data Sheet [1] and must be capable of extensively delivering a DC current as the maximum average current consumption specified in LARA-R2 series Data Sheet [1]. The maximum discharge current is not always reported in the data sheets of batteries, but the max DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour. DC series resistance: the non-rechargeable battery with its output circuit must be capable of avoiding a VCC voltage drop below the operating range summarized in Table 6 during transmit bursts.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-71.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 72 of 148 2.2.1.6 Additional guidelines for VCC supply circuit design To reduce voltage drops, use a low impedance power source. The series resistance of the power supply lines (connected to the VCC and GND pins of the module) on the application board and battery pack should also be considered and minimized: cabling and routing must be as short as possible to minimize power losses. Three pins are allocated for VCC supply. Several pins are designated for GND connection. It is recommended to properly connect all of them to supply the module to minimize series resistance losses. In case of modules supporting 2G radio access technology, to avoid voltage drop undershoot and overshoot at the start and end of a transmit burst during a GSM call (when current consumption on the VCC supply can rise up as specified in the LARA-R2 series Data Sheet [1]), place a bypass capacitor with large capacitance (at least 100 µF) and low ESR near the VCC pins, for example: 330 µF capacitance, 45 m ESR (e.g. KEMET T520D337M006ATE045, Tantalum Capacitor) To reduce voltage ripple and noise, improving RF performance especially if the application device integrates an internal antenna, place the following bypass capacitors near the VCC pins: 68 pF capacitor with Self-Resonant Frequency in 800/900 MHz range (e.g. Murata GRM1555C1E560J) 15 pF capacitor with Self-Resonant Frequency in 1800/1900 MHz range (e.g. Murata GRM1555C1E150J) 8.2 pF capacitor with Self-Resonant Frequency in 2500/2600 MHz range (e.g. Murata GRM1555C1H8R2D) 10 nF capacitor (e.g. Murata GRM155R71C103K) to filter digital logic noise from clocks and data sources 100 nF capacitor (e.g Murata GRM155R61C104K) to filter digital logic noise from clocks and data sources A suitable series ferrite bead can be properly placed on the VCC line for additional noise filtering if required by the specific application according to the whole application board design. C2GNDC3 C4LARA-R2 series52VCC53VCC51VCCC1 C63V8+Recommended for cellular modules supporting 2GC5Recommended for cellular modules supporting LTE band-7 Figure 30: Suggested schematic for the VCC bypass capacitors to reduce ripple / noise on supply voltage profile Reference Description Part Number - Manufacturer C1 8.2 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H8R2DZ01 - Murata C2 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H150JA01 - Murata C3 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H680JA01 - Murata C4 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata C5 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata C6 330 µF Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET Table 23: Suggested components to reduce ripple / noise on VCC The necessity of each part depends on the specific design, but it is recommended to provide all the bypass capacitors described in Figure 30 / Table 23 if the application device integrates an internal antenna. ESD sensitivity rating of the VCC supply pins is 1 kV (Human Body Model according to JESD22-A114). Higher protection level can be required if the line is externally accessible on the application board, e.g. if accessible battery connector is directly connected to VCC pins. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible point.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-72.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 77 of 148 2.2.1.10 Guidelines for removing VCC supply As described in section 1.6.2 and Figure 14, the VCC supply can be removed after the end of LARA-R2 series modules internal power-off sequence, which has to be properly started sending the AT+CPWROFF command (see u-blox AT Commands Manual [2]). Removing the VCC power can be useful in order to minimize the current consumption when the LARA-R2 series modules are switched off. Then, the modules can be switched on again by re-applying the VCC supply. If the VCC supply is generated by a switching or an LDO regulator, the application processor may control the input pin of the regulator which is provided to enable / disable the output of the regulator (as for example the RUN input pin for the regulator described in Figure 26, the INH input pin for the regulator described in Figure 27, the SHDNn input pin for the regulator described in Figure 28, the EN input pin for the regulator described in Figure 29), in order to apply / remove the VCC supply. If the regulator that generates the VCC supply does not provide an on / off pin, or for other applications such as the battery-powered ones, the VCC supply can be switched off using an appropriate external p-channel MOSFET controlled by the application processor by means of a proper inverting transistor as shown in Figure 35, given that the external p-channel MOSFET has provide: Very low RDS(ON) (for example, less than 50 m), to minimize voltage drops Adequate maximum Drain current (see LARA-R2 series Data Sheet [1] for module consumption figures) Low leakage current, to minimize the current consumption C3GNDC2C1 C4LARA-R2 series52 VCC53 VCC51 VCC+VCC Supply SourceGNDGPIO C5 C6R1R3R2T2T1Application Processor Figure 35: Example of application circuit for VCC supply removal Reference Description Part Number - Manufacturer R1 47 k Resistor 0402 5% 0.1 W RC0402JR-0747KL - Yageo Phycomp R2 10 k Resistor 0402 5% 0.1 W RC0402JR-0710KL - Yageo Phycomp R3 100 k Resistor 0402 5% 0.1 W RC0402JR-07100KL - Yageo Phycomp T1 P-Channel MOSFET Low On-Resistance AO3415 - Alpha & Omega Semiconductor Inc. T2 NPN BJT Transistor BC847 - Infineon C1 330 µF Capacitor Tantalum D_SIZE 6.3 V 45 m T520D337M006ATE045 - KEMET C2 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata C3 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata C4 56 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E560JA01 - Murata C5 15 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E150JA01 - Murata C6 8.2 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H8R2DZ01 - Murata Table 27: Components for VCC supply removal application circuit It is highly recommended to avoid an abrupt removal of the VCC supply during LARA-R2 series modules normal operations: the power off procedure must be started by the AT+CPWROFF command, waiting the command response for a proper time period (see u-blox AT Commands Manual [2]), and then a proper VCC supply has to be held at least until the end of the modules’ internal power off sequence, which occurs when the generic digital interfaces supply output (V_INT) is switched off by the module.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-77.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 79 of 148 2.2.2 RTC supply (V_BCKP) 2.2.2.1 Guidelines for V_BCKP circuit design LARA-R2 series modules provide the V_BCKP RTC supply input/output, which can be mainly used to: Provide RTC back-up when VCC supply is removed If RTC timing is required to run for a time interval of T [s] when VCC supply is removed, place a capacitor with a nominal capacitance of C [µF] at the V_BCKP pin. Choose the capacitor using the following formula: C [µF] = (Current_Consumption [µA] x T [s]) / Voltage_Drop [V] = 2.5 x T [s] For example, a 100 µF capacitor can be placed at V_BCKP to provide RTC backup holding the V_BCKP voltage within its valid range for around 40 s at 25 °C, after the VCC supply is removed. If a longer buffering time is required, a 70 mF super-capacitor can be placed at V_BCKP, with a 4.7 k series resistor to hold the V_BCKP voltage within its valid range for approximately 8 hours at 25 °C, after the VCC supply is removed. The purpose of the series resistor is to limit the capacitor charging current due to the large capacitor specifications, and also to let a fast rise time of the voltage value at the V_BCKP pin after VCC supply has been provided. These capacitors allow the time reference to run during battery disconnection. LARA-R2 seriesC1(a)2V_BCKPR2LARA-R2 seriesC2(superCap)(b)2V_BCKPD3LARA-R2 seriesB3(c)2V_BCKP Figure 36: Real time clock supply (V_BCKP) application circuits: (a) using a 100 µF capacitor to let the RTC run for ~1 minute after VCC removal; (b) using a 70 mF capacitor to let RTC run for ~10 hours after VCC removal; (c) using a non-rechargeable battery Reference Description Part Number - Manufacturer C1 100 µF Tantalum Capacitor GRM43SR60J107M - Murata R2 4.7 k Resistor 0402 5% 0.1 W RC0402JR-074K7L - Yageo Phycomp C2 70 mF Capacitor XH414H-IV01E - Seiko Instruments Table 28: Example of components for V_BCKP buffering If longer buffering time is required to allow the RTC time reference to run during a disconnection of the VCC supply, then an external battery can be connected to V_BCKP pin. The battery should be able to provide a proper nominal voltage and must never exceed the maximum operating voltage for V_BCKP (specified in the Input characteristics of Supply/Power pins table in the LARA-R2 series Data Sheet [1]). The connection of the battery to V_BCKP should be done with a suitable series resistor for a rechargeable battery, or with an appropriate series diode for a non-rechargeable battery. The purpose of the series resistor is to limit the battery charging current due to the battery specifications, and also to allow a fast rise time of the voltage value at the V_BCKP pin after the VCC supply has been provided. The purpose of the series diode is to avoid a current flow from the module V_BCKP pin to the non-rechargeable battery. If the RTC timing is not required when the VCC supply is removed, it is not needed to connect the V_BCKP pin to an external capacitor or battery. In this case the date and time are not updated when VCC is disconnected. If VCC is always supplied, then the internal regulator is supplied from the main supply and there is no need for an external component on V_BCKP.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-79.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 80 of 148 Combining a LARA-R2 series cellular module with a u-blox GNSS positioning receiver, the positioning receiver VCC supply is controlled by the cellular module by means of the “GNSS supply enable” function provided by the GPIO2 of the cellular module. In this case the V_BCKP supply output of the cellular module can be connected to the V_BCKP backup supply input pin of the GNSS receiver to provide the supply for the positioning real time clock and backup RAM when the VCC supply of the cellular module is within its operating range and the VCC supply of the GNSS receiver is disabled. This enables the u-blox GNSS receiver to recover from a power breakdown with either a hot start or a warm start (depending on the duration of the positioning VCC outage) and to maintain the configuration settings saved in the backup RAM. Refer to section 2.6.4 for more details regarding the application circuit with a u-blox GNSS receiver. The internal regulator for V_BCKP is optimized for low leakage current and very light loads. Do not apply loads which might exceed the limit for maximum available current from V_BCKP supply, as this can cause malfunctions in the module. LARA-R2 series Data Sheet [1] describes the detailed electrical characteristics. V_BCKP supply output pin provides internal short circuit protection to limit start-up current and protect the device in short circuit situations. No additional external short circuit protection is required. ESD sensitivity rating of the V_BCKP supply pin is 1 kV (Human Body Model according to JESD22-A114). Higher protection level can be required if the line is externally accessible on the application board, e.g. if an accessible back-up battery connector is directly connected to V_BCKP pin, and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to the accessible point. 2.2.2.2 Guidelines for V_BCKP layout design RTC supply (V_BCKP) requires careful layout: avoid injecting noise on this voltage domain as it may affect the stability of the 32 kHz oscillator.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-80.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 81 of 148 2.2.3 Interface supply (V_INT) 2.2.3.1 Guidelines for V_INT circuit design LARA-R2 series provide the V_INT generic digital interfaces 1.8 V supply output, which can be mainly used to: Indicate when the module is switched on (see sections 1.6.1, 1.6.2 for more details) Pull-up SIM detection signal (see section 2.5 for more details) Supply voltage translators to connect digital interfaces of the module to a 3.0 V device (see section 2.6.1) Pull-up DDC (I2C) interface signals (see section 2.6.4 for more details) Supply a 1.8 V u-blox 6 or subsequent GNSS receiver (see section 2.6.4 for more details) Supply an external device, as an external 1.8 V audio codec (see section 2.7.1 for more details) V_INT supply output pin provides internal short circuit protection to limit start-up current and protect the device in short circuit situations. No additional external short circuit protection is required. Do not apply loads which might exceed the limit for maximum available current from V_INT supply (see the LARA-R2 series Data Sheet [1]) as this can cause malfunctions in internal circuitry. Since the V_INT supply is generated by an internal switching step-down regulator, the V_INT voltage ripple can range as specified in the LARA-R2 series Data Sheet [1]: it is not recommended to supply sensitive analog circuitry without adequate filtering for digital noise. V_INT can only be used as an output: do not connect any external supply source on V_INT. ESD sensitivity rating of the V_INT supply pin is 1 kV (Human Body Model according to JESD22-A114). Higher protection level could be required if the line is externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to the accessible point. It is recommended to provide direct access to the V_INT pin on the application board by means of an accessible test point directly connected to the V_INT pin. 2.2.3.2 Guidelines for V_INT layout design V_INT supply output is generated by an integrated switching step-down converter, used internally to supply the generic digital interfaces. Because of this, it can be a source of noise: avoid coupling with sensitive signals.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-81.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 84 of 148 2.3.3 Module / host configuration selection 2.3.3.1 Guidelines for HOST_SELECT circuit design Selection of module / host configuration over HOST_SELECT is not supported by “02” product versions. LARA-R2 series modules include one pin (HOST_SELECT) to select the module / host application processor configuration: the pin is available to select, enable, connect, disconnect and subsequently re-connect the HSIC (USB High-Speed Inter-Chip) interface. LARA-R2 series Data Sheet [1] describes the detailed electrical characteristics of the HOST_SELECT pin. Further guidelines for HOST_SELECT pin circuit design will be described in detail in a successive release of the System Integration Manual. Do not apply voltage to HOST_SELECT pin before the switch-on of its supply source (V_INT), to avoid latch-up of circuits and allow a proper boot of the module. If the external signal connected to the cellular module cannot be tri-stated or set low, insert a multi channel digital switch (e.g. TI SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance before V_INT switch-on. ESD sensitivity rating of the HOST_SELECT pin is 1 kV (HBM as per JESD22-A114). Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points If the HOST_SELECT pin is not used, they can be left unconnected on the application board. 2.3.3.2 Guidelines for HOST_SELECT layout design The pin for the selection of the module / host application processor configuration (HOST_SELECT) is generally not critical for layout.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-84.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 93 of 148 The DC impedance at RF port for some antennas may be a DC open (e.g. linear monopole) or a DC short to reference GND (e.g. PIFA antenna). For those antennas, without the diagnostic circuit of Figure 43, the measured DC resistance is always at the limits of the measurement range (respectively open or short), and there is no means to distinguish between a defect on antenna path with similar characteristics (respectively: removal of linear antenna or RF cable shorted to GND for PIFA antenna). Furthermore, any other DC signal injected to the RF connection from ANT connector to radiating element will alter the measurement and produce invalid results for antenna detection. It is recommended to use an antenna with a built-in diagnostic resistor in the range from 5 k to 30 k to assure good antenna detection functionality and avoid a reduction of module RF performance. The choke inductor should exhibit a parallel Self Resonance Frequency (SRF) in the range of 1 GHz to improve the RF isolation of load resistor. For example: Consider an antenna with built-in DC load resistor of 15 k. Using the +UANTR AT command, the module reports the resistance value evaluated from the antenna connector provided on the application board to GND: Reported values close to the used diagnostic resistor nominal value (i.e. values from 13 k to 17 k if a 15 k diagnostic resistor is used) indicate that the antenna is properly connected. Values close to the measurement range maximum limit (approximately 50 k) or an open-circuit “over range” report (see u-blox AT Commands Manual [2]) means that that the antenna is not connected or the RF cable is broken. Reported values below the measurement range minimum limit (1 k) highlights a short to GND at antenna or along the RF cable. Measurement inside the valid measurement range and outside the expected range may indicate an improper connection, damaged antenna or wrong value of antenna load resistor for diagnostic. Reported value could differ from the real resistance value of the diagnostic resistor mounted inside the antenna assembly due to antenna cable length, antenna cable capacity and the used measurement method. If the primary / secondary antenna detection function is not required by the customer application, the ANT_DET pin can be left not connected and the ANT1 / ANT2 pins can be directly connected to the related antenna connector by means of a 50 transmission line as described in Figure 42. 2.4.2.2 Guidelines for ANT_DET layout design The recommended layout for the primary antenna detection circuit to be provided on the application board to achieve the primary antenna detection functionality, implementing the recommended schematic described in Figure 43 and Table 34, is explained here: The ANT1 / ANT2 pins have to be connected to the antenna connector by means of a 50 transmission line, implementing the design guidelines described in section 2.4.1 and the recommendations of the SMA connector manufacturer. DC blocking capacitor at ANT1 / ANT2 pins (C2, C3) has to be placed in series to the 50 RF line. The ANT_DET pin has to be connected to the 50 transmission line by means of a sense line. Choke inductors in series at the ANT_DET pin (L1, L2) have to be placed so that one pad is on the 50 transmission line and the other pad represents the start of the sense line to the ANT_DET pin. The additional components (R1, C1 and D1) on the ANT_DET line have to be placed as ESD protection.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-93.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 98 of 148 Guidelines for dual SIM card / chip connection Two SIM card / chip can be connected to the SIM interface of LARA-R2 series modules as described in Figure 47. LARA-R2 series modules do not support the usage of two SIM at the same time, but two SIM can be populated on the application board, providing a proper switch to connect only the first or only the second SIM at a time to the SIM interface of the modules, as described in Figure 47. LARA-R2 series modules support SIM hot insertion / removal on the GPIO5 pin, to enable / disable SIM interface upon detection of external SIM card physical insertion / removal: if the feature is enabled using the specific AT commands (see sections 1.8.2 and 1.12, and u-blox AT Commands Manual [2], +UGPIOC, +UDCONF=50 commands), the switch from first SIM to the second SIM can be properly done when a Low logic level is present on the GPIO5 pin (“SIM not inserted” = SIM interface not enabled), without the necessity of a module re-boot, so that the SIM interface will be re-enabled by the module to use the second SIM when a high logic level is re-applied on the GPIO5 pin. In the application circuit example represented in Figure 47, the application processor will drive the SIM switch using its own GPIO to properly select the SIM that is used by the module. Another GPIO may be used to handle the SIM hot insertion / removal function of LARA-R2 series modules, which can also be handled by other external circuits or by the cellular module GPIO according to the application requirements. The dual SIM connection circuit described in Figure 47 can be implemented for SIM chips as well, providing proper connection between SIM switch and SIM chip as described in Figure 45. If it is required to switch between more than 2 SIM, a circuit similar to the one described in Figure 47 can be implemented: in case of 4 SIM circuit, using proper 4-throw switch instead of the suggested 2-throw switches. Follow these guidelines connecting the module to two SIM connectors: Use a proper low on resistance (i.e. few ohms) and low on capacitance (i.e. few pF) 2-throw analog switch (e.g. Fairchild FSA2567) as SIM switch to ensure high-speed data transfer according to SIM requirements. Connect the contacts C1 (VCC) of the two UICC / SIM to the VSIM pin of the module by means of a proper 2-throw analog switch (e.g. Fairchild FSA2567). Connect the contact C7 (I/O) of the two UICC / SIM to the SIM_IO pin of the module by means of a proper 2-throw analog switch (e.g. Fairchild FSA2567). Connect the contact C3 (CLK) of the two UICC / SIM to the SIM_CLK pin of the module by means of a proper 2-throw analog switch (e.g. Fairchild FSA2567). Connect the contact C2 (RST) of the two UICC / SIM to the SIM_RST pin of the module by means of a proper 2-throw analog switch (e.g. Fairchild FSA2567). Connect the contact C5 (GND) of the two UICC / SIM to ground. Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line (VSIM), close to the related pad of the two SIM connectors, to prevent digital noise. Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line (VSIM, SIM_CLK, SIM_IO, SIM_RST), very close to each related pad of the two SIM connectors, to prevent RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM card holders. Provide a very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco Electronics PESD0402-140) on each externally accessible SIM line, close to each related pad of the two SIM connectors, according to the EMC/ESD requirements of the custom application. Limit capacitance and series resistance on each SIM signal to match the SIM specifications requirements (27.7 ns = max allowed rise time on SIM_CLK, 1.0 µs = max allowed rise time on SIM_IO and SIM_RST).](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-98.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 102 of 148 Providing the TXD, RXD, RTS and CTS lines only (not using the complete V.24 link) Connect the module DTR input to GND using a 0 series resistor, since it may be useful to set DTR active if not specifically handled (see u-blox AT Commands Manual [2], &D, S0, +CSGT, +CNMI AT commands) Leave DSR, DCD and RI lines of the module floating, with a test-point on DCD If RS-232 compatible signal levels are needed, the Maxim MAX13234E voltage level translator can be used. This chip translates voltage levels from 1.8 V (module side) to the RS-232 standard. If a 1.8 V Application Processor is used, the circuit should be implemented as described in Figure 52. TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDLARA-R2 series(1.8V DCE)12 TXD9DTR13 RXD10 RTS11 CTS6DSR7RI8DCDGND0ΩTP0ΩTP0ΩTPTP Figure 52: UART interface application circuit with partial V.24 link (5-wire) in the DTE/DCE serial communication (1.8 V DTE) If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART interface of the module (DCE) by means of appropriate unidirectional voltage translators using the module V_INT output as 1.8 V supply for the voltage translators on the module side, as described in Figure 53. 4V_INTTxDApplication Processor(3.0V DTE)RxDRTSCTSDTRDSRRIDCDGNDLARA-R2 series(1.8V DCE)12 TXD9DTR13 RXD10 RTS11 CTS6DSR7RI8DCDGND1V8B1 A1GNDU1B3A3VCCBVCCAUnidirectionalVoltage TranslatorC1 C23V0DIR3DIR2 OEDIR1VCCB2 A2B4A4DIR4TP0ΩTP0ΩTP0ΩTPTP Figure 53: UART interface application circuit with partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number - Manufacturer C1, C2 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata U1 Unidirectional Voltage Translator SN74AVC4T77418 - Texas Instruments Table 41: Component for UART application circuit with partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE) 18 Voltage translator providing partial power down feature so that the DTE 3.0 V supply can be also ramped up before V_INT 1.8 V supply](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-102.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 103 of 148 Providing the TXD and RXD lines only (not using the complete V24 link) If the functionality of the CTS, RTS, DSR, DCD, RI and DTR lines is not required in the application, or the lines are not available: Connect the module RTS input line to GND or to the CTS output line of the module: since the module requires RTS active (low electrical level) if HW flow-control is enabled (AT&K3, which is the default setting). Connect the module DTR input to GND using a 0 series resistor, since it may be useful to set DTR active if not specifically handled (see u-blox AT Commands Manual [2], &D, S0, +CSGT, +CNMI AT commands) Leave DSR, DCD and RI lines of the module floating, with a test-point on DCD If RS-232 compatible signal levels are needed, the Maxim MAX13234E voltage level translator can be used. This chip translates voltage levels from 1.8 V (module side) to the RS-232 standard. If a 1.8 V Application Processor (DTE) is used, the circuit that should be implemented as described in Figure 54: TxDApplication Processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDLARA-R2 series(1.8V DCE)12 TXD9DTR13 RXD10 RTS11 CTS6DSR7RI8DCDGND0ΩTP0ΩTP0ΩTPTP Figure 54: UART interface application circuit with partial V.24 link (3-wire) in the DTE/DCE serial communication (1.8 V DTE) If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART interface of the module (DCE) by means of appropriate unidirectional voltage translators using the module V_INT output as 1.8 V supply for the voltage translators on the module side, as described in Figure 55. 4V_INTTxDApplication Processor(3.0V DTE)RxDDTRDSRRIDCDGNDLARA-R2 series(1.8V DCE)12 TXD9DTR13 RXD6DSR7RI8DCDGND1V8B1 A1GNDU1VCCBVCCAUnidirectionalVoltage TranslatorC1 C23V0DIR1DIR2 OEVCCB2 A2RTSCTS10 RTS11 CTSTP0ΩTP0ΩTP0ΩTPTP Figure 55: UART interface application circuit with partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number - Manufacturer C1, C2 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata U1 Unidirectional Voltage Translator SN74AVC2T24519 - Texas Instruments Table 42: Component for UART application circuit with partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE) 19 Voltage translator providing partial power down feature so that the DTE 3.0 V supply can be also ramped up before V_INT 1.8 V supply](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-103.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 105 of 148 2.6.2 USB interface 2.6.2.1 Guidelines for USB circuit design The USB_D+ and USB_D- lines carry the USB serial data and signaling. The lines are used in single ended mode for full speed signaling handshake, as well as in differential mode for high speed signaling and data transfer. USB pull-up or pull-down resistors and external series resistors on USB_D+ and USB_D- lines as required by the USB 2.0 specification [9] are part of the module USB pins driver and do not need to be externally provided. The USB interface of the module is enabled only if a valid voltage is detected by the VUSB_DET input (see the LARA-R2 series Data Sheet [1]). Neither the USB interface, nor the whole module is supplied by the VUSB_DET input: the VUSB_DET senses the USB supply voltage and absorbs few microamperes. Routing the USB pins to a connector, they will be externally accessible on the application device. According to EMC/ESD requirements of the application, an additional ESD protection device with very low capacitance should be provided close to accessible point on the line connected to this pin, as described in Figure 56 and Table 43. The USB interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting a very low capacitance (i.e. less or equal to 1 pF) ESD protection (e.g. Tyco Electronics PESD0402-140 ESD protection device) on the lines connected to these pins, close to accessible points. The USB pins of the modules can be directly connected to the USB host application processor without additional ESD protections if they are not externally accessible or according to EMC/ESD requirements. LARA-R2 series D+D-GND29 USB_D+28 USB_D-GNDUSB DEVICE CONNECTORD1 D2VBUSLARA-R2 series D+D-GND29 USB_D+28 USB_D-GNDUSB HOST PROCESSORC117 VUSB_DETC117 VUSB_DETVBUSD3 Figure 56: USB Interface application circuits Reference Description Part Number - Manufacturer C1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata D1, D2, D3 Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics Table 43: Component for USB application circuits If the USB interface pins are not used, they can be left unconnected on the application board, but it is recommended providing accessible test points directly connected to VUSB_DET, USB_D+, USB_D- pins.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-105.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 106 of 148 2.6.2.2 Guidelines for USB layout design The USB_D+ / USB_D- lines require accurate layout design to achieve reliable signaling at the high speed data rate (up to 480 Mb/s) supported by the USB serial interface. The characteristic impedance of the USB_D+ / USB_D- lines is specified by the Universal Serial Bus Revision 2.0 specification [9]. The most important parameter is the differential characteristic impedance applicable for the odd-mode electromagnetic field, which should be as close as possible to 90 differential. Signal integrity may be degraded if PCB layout is not optimal, especially when the USB signaling lines are very long. Use the following general routing guidelines to minimize signal quality problems: Route USB_D+ / USB_D- lines as a differential pair. Route USB_D+ / USB_D- lines as short as possible. Ensure the differential characteristic impedance (Z0) is as close as possible to 90 . Ensure the common mode characteristic impedance (ZCM) is as close as possible to 30 . Consider design rules for USB_D+ / USB_D- similar to RF transmission lines, being them coupled differential micro-strip or buried stripline: avoid any stubs, abrupt change of layout, and route on clear PCB area. Avoid coupling with any RF line or sensitive analog inputs, since the signals can cause the radiation of some harmonics of the digital data frequency. Figure 57 and Figure 58 provide two examples of coplanar waveguide designs with differential characteristic impedance close to 90 and common mode characteristic impedance close to 30 . The first transmission line can be implemented in case of 4-layer PCB stack-up herein described, the second transmission line can be implemented in case of 2-layer PCB stack-up herein described. 35 µm35 µm35 µm35 µm270 µm270 µm760 µmL1 CopperL3 CopperL2 CopperL4 CopperFR-4 dielectricFR-4 dielectricFR-4 dielectric350 µm 400 µm400 µm350 µm400 µm Figure 57: Example of USB line design, with Z0 close to 90 and ZCM close to 30 , for the described 4-layer board layup 35 µm35 µm1510 µmL2 CopperL1 CopperFR-4 dielectric740 µm 410 µm410 µm740 µm410 µm Figure 58: Example of USB line design, with Z0 close to 90 and ZCM close to 30 , for the described 2-layer board layup](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-106.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 107 of 148 2.6.3 HSIC interface 2.6.3.1 Guidelines for HSIC circuit design The HSIC interface is not supported by “02” modules product versions except for diagnostic purpose. LARA-R2 series modules include a USB High-Speed Inter-Chip compliant interface with maximum 480 Mb/s data rate according to the High-Speed Inter-Chip USB Electrical Specification Version 1.0 [10] and USB Specification Revision 2.0 [9]. The module itself acts as a device and can be connected to any compatible host. The HSIC interface consists of a bi-directional DDR data line (HSIC_DATA) for transmitting and receiving data synchronously with the bi-directional strobe line (HSIC_STRB), intended to be directly connected to the Data and Strobe pins of the compatible USB High-Speed Inter-Chip host mounted on the same PCB of the LARA-R2 series module, without using connectors / cables, as described in Figure 59. The modules include also the HOST_SELECT pin to select the module / host application processor configuration: the pin is available to select, enable, connect, disconnect and subsequently re-connect the HSIC interface. LARA-R2 series DATASTROBEGND99 HSIC_DATA100 HSIC_STRBGNDUSB HSICHOST PROCESSOR Figure 59: HSIC interface application circuit Further guidelines for HSIC interface circuit design will be described in detail in a successive release of the System Integration Manual. ESD sensitivity rating of HSIC interface pins is 1 kV (HBM as per JESD22-A114). Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points If the HSIC interface pins are not used, they can be left unconnected on the application board, but it is recommended providing accessible test points directly connected to HSIC_DATA and HSIC_STRB pins.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-107.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 108 of 148 2.6.3.2 Guidelines for HSIC layout design HSIC lines require accurate layout design to achieve reliable signaling at high speed data rate (up to 480 Mb/s), as supported by the HSIC serial interface: signal integrity may be degraded if PCB layout is not optimal, especially when the HSIC lines are very long. The characteristic impedance of the HSIC_DATA and HSIC_STRB lines has to be as close as possible to 50 , as specified by the High-Speed Inter-Chip USB Electrical Specification Version 1.0 [10]. Use the following general routing guidelines to minimize signal quality problems: Route HSIC_DATA and HSIC_STRB lines as short as possible. HSIC interface is only recommended for intra-board interconnect. The connection should be point-to-point. Connectors and cables are not recommended. HSIC_DATA and HSIC_STRB lines must be matched in length to within 10 mils. Ensure the characteristic impedance of HSIC_DATA and HSIC_STRB lines is as close as possible to 50 . HSIC_DATA and HSIC_STRB signals are not differential signals and should not be routed as such. Consider design rules for HSIC_DATA and HSIC_STRB lines similar to RF transmission lines, routing them as micro-strips (conducting strips separated from ground plane by dielectric material) or striplines (flat strips of metal sandwiched between two parallel ground planes within a dielectric material). Avoid any stubs, abrupt change of layout, and route on clear PCB area. Avoid coupling with any RF line or sensitive analog inputs, since the signals can cause the radiation of some harmonics of the digital data frequency. Figure 40 and Figure 41 provide two examples of proper 50 coplanar waveguide designs. The first example of RF transmission line can be implemented in case of 4-layer PCB stack-up herein described, and the second example of RF transmission line can be implemented in case of 2-layer PCB stack-up herein described. If the two examples do not match the application PCB layup, the 50 characteristic impedance calculation can be made using the HFSS commercial finite element method solver for electromagnetic structures from Ansys Corporation, or using freeware tools like AppCAD from Agilent (www.agilent.com) or TXLine from Applied Wave Research (www.mwoffice.com), taking care of the approximation formulas used by the tools for the impedance computation. To achieve a 50 characteristic impedance, the width of the transmission line must be chosen depending on: the thickness of the transmission line itself (e.g. 35 µm in the example of Figure 40 and Figure 41) the thickness of the dielectric material between the top layer (where the transmission line is routed) and the inner closer layer implementing the ground plane (e.g. 270 µm in Figure 40, 1510 µm in Figure 41) the dielectric constant of the dielectric material (e.g. dielectric constant of the FR-4 dielectric material in Figure 40 and Figure 41) the gap from the transmission line to the adjacent ground plane on the same layer of the transmission line (e.g. 500 µm in Figure 40, 400 µm in Figure 41) If the distance between the transmission line and the adjacent GND area (on the same layer) does not exceed 5 times the track width of the micro strip, use the “Coplanar Waveguide” model for the 50 calculation.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-108.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 109 of 148 2.6.4 DDC (I2C) interface 2.6.4.1 Guidelines for DDC (I2C) circuit design General considerations Communication with u-blox GNSS receivers over DDC (I2C) is not supported by “02” product versions. The DDC I2C-bus master interface can be used to communicate with u-blox GNSS receivers and other external I2C-bus slaves as an audio codec. Beside the general considerations reported below, see: the following parts of this section for specific guidelines for the connection to u-blox GNSS receivers. the section 2.7.1 for an application circuit example with an external audio codec I2C-bus slave. To be compliant to the I2C-bus specifications, the module bus interface pins are open drain output and pull up resistors must be mounted externally. Resistor values must conform to I2C bus specifications [11]: for example, 4.7 k resistors can be commonly used. Pull-ups must be connected to a supply voltage of 1.8 V (typical), since this is the voltage domain of the DDC pins which are not tolerant to higher voltage values (e.g. 3.0 V). Connect the DDC (I2C) pull-ups to the V_INT 1.8 V supply source, or another 1.8 V supply source enabled after V_INT (e.g., as the GNSS 1.8 V supply present in Figure 60 application circuit), as any external signal connected to the DDC (I2C) interface must not be set high before the switch-on of the V_INT supply of the DDC (I2C) pins, to avoid latch-up of circuits and let a proper boot of the module. The signal shape is defined by the values of the pull-up resistors and the bus capacitance. Long wires on the bus increase the capacitance. If the bus capacitance is increased, use pull-up resistors with nominal resistance value lower than 4.7 k, to match the I2C bus specifications [11] regarding rise and fall times of the signals. Capacitance and series resistance must be limited on the bus to match the I2C specifications (1.0 µs is the maximum allowed rise time on the SCL and SDA lines): route connections as short as possible. ESD sensitivity rating of the DDC (I2C) pins is 1 kV (Human Body Model according to JESD22-A114). Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points. If the pins are not used as DDC bus interface, they can be left unconnected.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-109.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 111 of 148 Figure 61 illustrates an alternative solution as supply for u-blox 1.8 V GNSS receivers: the V_INT 1.8 V regulated supply output of the cellular module can be used to supply a u-blox 1.8 V GNSS receiver of the u-blox 6 generation (or any newer u-blox GNSS receiver generation) instead of using an external voltage regulator as shown in the previous Figure 60. The V_INT supply is able to support the maximum current consumption of these positioning receivers. The internal switching step-down regulator that generates the V_INT supply is set to 1.8 V (typical) when the cellular module is switched on and it is disabled when the module is switched off. The supply of the u-blox 1.8 V GNSS receiver can be switched off using an external p-channel MOSFET controlled by the GPIO2 pin by means of a proper inverting transistor as shown in Figure 61, implementing the “GNSS supply enable” function. If this feature is not required, the V_INT supply output can be directly connected to the u-blox 1.8 V GNSS receiver, so that it will be switched on when V_INT output is enabled. According to the V_INT supply output voltage ripple characteristic specified in LARA-R2 series Data Sheet [1]: Additional filtering may be needed to properly supply an external LNA, depending on the characteristics of the used LNA, adding a series ferrite bead and a bypass capacitor (e.g. the Murata BLM15HD182SN1 ferrite bead and the Murata GRM1555C1H220J 22 pF capacitor) at the input of the external LNA supply line. LARA-R2 series(except ‘02’ product version)u-blox GNSS1.8 V receiverTxD1EXTINT0GPIO3GPIO42425V_BCKP V_BCKP2SDA2SCL223 GPIO2SDASCL2627VCC1V8C1R34V_INTR5R4TPT2T1R1 R21V8 1V8GNSS data readyGNSS RTC sharingGNSS supply enabled Figure 61: Application circuit for connecting LARA-R2 series modules to u-blox 1.8 V GNSS receivers using V_INT as supply Reference Description Part Number - Manufacturer R1, R2 4.7 k Resistor 0402 5% 0.1 W RC0402JR-074K7L - Yageo Phycomp R3 47 k Resistor 0402 5% 0.1 W RC0402JR-0747KL - Yageo Phycomp R4 10 k Resistor 0402 5% 0.1 W RC0402JR-0710KL - Yageo Phycomp R5 100 k Resistor 0402 5% 0.1 W RC0402JR-07100KL - Yageo Phycomp T1 P-Channel MOSFET Low On-Resistance IRLML6401 - International Rectifier or NTZS3151P - ON Semi T2 NPN BJT Transistor BC847 - Infineon C1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata Table 45: Components for connecting LARA-R2 series modules to u-blox 1.8 V GNSS receivers using V_INT as supply For additional guidelines regarding the design of applications with u-blox 1.8 V GNSS receivers see the GNSS Implementation Application Note [22] and to the Hardware Integration Manual of the u-blox GNSS receivers.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-111.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 112 of 148 Connection with u-blox 3.0 V GNSS receivers Figure 62 shows an application circuit for connecting the cellular module to a u-blox 3.0 V GNSS receiver: As the SDA and SCL pins of the cellular module are not tolerant up to 3.0 V, the connection to the related I2C pins of the u-blox 3.0 V GNSS receiver must be provided using a proper I2C-bus Bidirectional Voltage Translator (e.g. TI TCA9406, which additionally provides the partial power down feature so that the GNSS 3.0 V supply can be ramped up before the V_INT 1.8 V cellular supply), with proper pull-up resistors. The GPIO2 is connected to the active-high enable pin of the voltage regulator that supplies the u-blox 3.0 V GNSS receiver providing the “GNSS supply enable” function. A pull-down resistor is provided to avoid a switch on of the positioning receiver when the cellular module is switched off or in the reset state. As the GPIO3 and GPIO4 pins of the cellular module are not tolerant up to 3.0 V, the connection to the related pins of the u-blox 3.0 V GNSS receiver must be provided using a proper Unidirectional General Purpose Voltage Translator (e.g. TI SN74AVC2T245, which additionally provides the partial power down feature so that the 3.0 V GNSS supply can be also ramped up before the V_INT 1.8 V cellular supply). The V_BCKP supply output of the cellular module can be directly connected to the V_BCKP backup supply input pin of the GNSS receiver as in the application circuit for a u-blox 1.8 V GNSS receiver. u-blox GNSS 3.0 V receiver24 GPIO31V8B1 A1GNDU3B2A2VCCBVCCAUnidirectionalVoltage TranslatorC4 C53V0TxD1R1INOUTGNSS LDO RegulatorSHDNnR2VMAIN3V0U123 GPIO226 SDA27 SCLR4 R51V8SDA_A SDA_BGNDU2SCL_ASCL_BVCCAVCCBI2C-bus Bidirectional Voltage Translator4V_INTC1C2 C3R3SDA2SCL2VCCDIR1DIR22V_BCKPV_BCKPOEnOEGNSS data readyGNSS supply enabledGNDLARA-R2 series(except ‘02’ product versions)EXTINT0 GPIO425GNSS RTC sharing Figure 62: Application circuit for connecting LARA-R2 series modules to u-blox 3.0 V GNSS receivers Reference Description Part Number - Manufacturer R1, R2, R4, R5 4.7 kΩ Resistor 0402 5% 0.1 W RC0402JR-074K7L - Yageo Phycomp R3 47 kΩ Resistor 0402 5% 0.1 W RC0402JR-0747KL - Yageo Phycomp C2, C3, C4, C5 100 nF Capacitor Ceramic X5R 0402 10% 10V GRM155R71C104KA01 - Murata U1, C1 Voltage Regulator for GNSS receiver and related output bypass capacitor See GNSS receiver Hardware Integration Manual U2 I2C-bus Bidirectional Voltage Translator TCA9406DCUR - Texas Instruments U3 Generic Unidirectional Voltage Translator SN74AVC2T245 - Texas Instruments Table 46: Components for connecting LARA-R2 series modules to u-blox 3.0 V GNSS receivers For additional guidelines regarding the design of applications with u-blox 3.0 V GNSS receivers see the GNSS Implementation Application Note [22] and to the Hardware Integration Manual of the u-blox GNSS receivers. 2.6.4.2 Guidelines for DDC (I2C) layout design The DDC (I2C) serial interface requires the same consideration regarding electro-magnetic interference as any other digital interface. Keep the traces short and avoid coupling with RF line or sensitive analog inputs, since the signals can cause the radiation of some harmonics of the digital data frequency.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-112.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 114 of 148 2.7 Audio interface Audio is not supported by LARA-R204 module “02” product version. 2.7.1 Digital audio interface 2.7.1.1 Guidelines for digital audio circuit design I2S digital audio interface can be connected to an external digital audio device for voice applications. Any external digital audio device compliant with the configuration of the digital audio interface of the LARA-R2 series cellular module can be used, given that the external digital audio device must provide: The opposite role: slave or master role, as LARA-R2 series modules may act as master or slave The same mode and frame format: PCM / short synch mode or Normal I2S / long synch mode with o data in 2’s complement notation o MSB transmitted first o data word length = 16-bit (16 clock cycles) o frame length = synch signal period: 17-bit or 18-bit in PCM / short alignment mode (16 + 1 or 16 + 2 clock cycles, with the Word Alignment / Synchronization signal set high for 1 clock cycle or 2 clock cycles) 32-bit in Normal I2S mode / long alignment mode (16 x 2 clock cycles) The same sample rate, i.e. synch signal frequency, configurable by AT+UI2S <I2S_sample_rate> parameter o 8 kHz o 11.025 kHz o 12 kHz o 16 kHz o 22.05 kHz o 24 kHz o 32 kHz o 44.1 kHz o 48 kHz The same serial clock frequency: o 17 x <I2S_sample_rate> or 18 x <I2S_sample_rate> in PCM / short alignment mode, or o 16 x 2 x <I2S_sample_rate> in Normal I2S mode / long alignment mode Compatible voltage levels (1.80 V typ.), otherwise it is recommended to connect the 1.8 V digital audio interface of the module to the external 3.0 V (or similar) digital audio device by means of appropriate unidirectional voltage translators (e.g. TI SN74AVC4T774 or SN74AVC2T245, providing partial power down feature so that the digital audio device 3.0 V supply can be also ramped up before V_INT 1.8 V supply), using the module V_INT output as 1.8 V supply for the voltage translators on the module side For the appropriate selection of a compliant external digital audio device, see section 1.10.1 and see the +UI2S AT command description in the u-blox AT Commands Manual [2] for further details regarding the capabilities and the possible settings of I2S digital audio interface of LARA-R2 series modules. An appropriate specific application circuit has to be implemented and configured according to the particular external digital audio device or audio codec used and according to the application requirements.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-114.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 115 of 148 Examples of manufacturers offering compatible audio codec parts are the following: Maxim Integrated (as the MAX9860, MAX9867, MAX9880A audio codecs) Texas Instruments / National Semiconductor Cirrus Logic / Wolfson Microelectronics Nuvoton Technology Asahi Kasei Microdevices Realtek Semiconductor Figure 63 and Table 47 describe an application circuit for the I2S digital audio interface providing basic voice capability using an external audio voice codec, in particular the Maxim MAX9860 audio codec. DAC and ADC integrated in the external audio codec respectively converts an incoming digital data stream to analog audio output through a mono amplifier and converts the microphone input signal to the digital bit stream over the digital audio interface, A digital side-tone mixer integrated in the external audio codec provides loopback of the microphones/ADC signal to the DAC/headphone output. The module’s I2S interface (I2S master) is connected to the related pins of the external audio codec (I2S slave). The GPIO6 of the LARA-R2 series module (that provides a suitable digital output clock) is connected to the clock input of the external audio codec to provide clock reference. The external audio codec is controlled by the LARA-R2 series module using the DDC (I2C) interface, which can concurrently communicate with other I2C devices and control an external audio codec. The V_INT output supplies the external audio codec, defining proper digital interfaces voltage level. Additional components are provided for EMC and ESD immunity conformity: a 10 nF bypass capacitor and a series chip ferrite bead noise/EMI suppression filter provided on each microphone line input and speaker line output of the external codec as described in Figure 63 and Table 47. The necessity of these or other additional parts for EMC improvement may depend on the specific application board design. Specific AT commands are available to configure the Maxim MAX9860 audio codec: for more details see the u-blox AT Commands Manual [2], +UEXTDCONF AT command. As various external audio codecs other than the one described in Figure 63 and Table 47 can be used to provide voice capability, the appropriate specific application circuit has to be implemented and configured according to the particular external digital audio device or audio codec used and according to the application requirements. LARA-R2 series(except LARA-R204 module “02” product version)R2R1BCLKGNDU1LRCLKAudio CodecSDINSDOUTSDASCLMCLKIRQnR3 C3C2C1VDD1V8MICBIASC4 R4C5C6MICLNMICLPD1Microphone Connector MICC12 C11J1MICGNDR5 C8 C7D2SPKSpeaker ConnectorOUTPOUTNJ2C10 C9C14 C13EMI3EMI4EMI1EMI2GPIO626SDA27SCL19GND4V_INT36I2S_CLK34I2S_WA35I2S_TXD37I2S_RXD Figure 63: I2S interface application circuit with an external audio codec to provide voice capability](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-115.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 121 of 148 2.12 Thermal guidelines Modules’ operating temperature range is specified in LARA-R2 series Data Sheet [1]. The most critical condition concerning module thermal performance is the uplink transmission at maximum power (data upload in connected-mode), when the baseband processor runs at full speed, radio circuits are all active and the RF power amplifier is driven to higher output RF power. This scenario is not often encountered in real networks (for example, see the Terminal Tx Power distribution for WCDMA, taken from operation on a live network, described in the GSMA TS.09 Battery Life Measurement and Current Consumption Technique [16]); however the application should be correctly designed to cope with it. During transmission at maximum RF power the LARA-R2 series modules generate thermal power that may exceed 2 W: this is an indicative value since the exact generated power strictly depends on operating condition such as the actual antenna return loss, the number of allocated TX resource blocks, the transmitting frequency band, etc. The generated thermal power must be adequately dissipated through the thermal and mechanical design of the application. The spreading of the Module-to-Ambient thermal resistance (Rth,M-A) depends on the module operating condition. The overall temperature distribution is influenced by the configuration of the active components during the specific mode of operation and their different thermal resistance toward the case interface. The Module-to-Ambient thermal resistance value and the relative increase of module temperature will differ according to the specific mechanical deployments of the module, e.g. application PCB with different dimensions and characteristics, mechanical shells enclosure, or forced air flow. The increase of the thermal dissipation, i.e. the reduction of the Module-to-Ambient thermal resistance, will decrease the temperature of the modules’ internal circuitry for a given operating ambient temperature. This improves the device long-term reliability in particular for applications operating at high ambient temperature. Recommended hardware techniques to be used to improve heat dissipation in the application: Connect each GND pin with solid ground layer of the application board and connect each ground area of the multilayer application board with complete thermal via stacked down to main ground layer. Provide a ground plane as wide as possible on the application board. Optimize antenna return loss, to optimize overall electrical performance of the module including a decrease of module thermal power. Optimize the thermal design of any high-power components included in the application, such as linear regulators and amplifiers, to optimize overall temperature distribution in the application device. Select the material, the thickness and the surface of the box (i.e. the mechanical enclosure) of the application device that integrates the module so that it provides good thermal dissipation. Further hardware techniques that may be considered to improve the heat dissipation in the application: Force ventilation air-flow within mechanical enclosure. Provide a heat sink component attached to the module top side, with electrically insulated / high thermal conductivity adhesive, or on the backside of the application board, below the cellular module, as a large part of the heat is transported through the GND pads of the LARA-R2 series LGA modules and dissipated over the backside of the application board. For example, the Module-to-Ambient thermal resistance (Rth,M-A) is strongly reduced with forced air ventilation and a heat-sink installed on the back of the application board, decreasing the module temperature variation. Beside the reduction of the Module-to-Ambient thermal resistance implemented by proper application hardware design, the increase of module temperature can be moderated by proper application software implementation: Enable power saving configuration using the AT+UPSV command (see section 1.14.16). Enable module connected-mode for a given time period and then disable it for a time period enough long to properly mitigate temperature increase.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-121.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 122 of 148 2.13 ESD guidelines The sections 2.13.1 and 2.13.2 are related to EMC / ESD immunity. The modules are ESD sensitive devices and the ESD sensitivity for each pin (as Human Body Model according to JESD22-A114F) is specified in LARA-R2 series Data Sheet [1]. Special precautions are required when handling: see section 3.2 for handling guidelines. 2.13.1 ESD immunity test overview The immunity of devices integrating LARA-R2 series modules to Electro-Static Discharge (ESD) is part of the Electro-Magnetic Compatibility (EMC) conformity, which is required for products bearing the CE marking, compliant with the R&TTE Directive (99/5/EC), the EMC Directive (89/336/EEC) and the Low Voltage Directive (73/23/EEC) issued by the Commission of the European Community. Compliance with these directives implies conformity to the following European Norms for device ESD immunity: ESD testing standard CENELEC EN 61000-4-2 [17] and the radio equipment standards ETSI EN 301 489-1 [18], ETSI EN 301 489-7 [19], ETSI EN 301 489-24 [20], which requirements are summarized in Table 50. The ESD immunity test is performed at the enclosure port, defined by ETSI EN 301 489-1 [18] as the physical boundary through which the electromagnetic field radiates. If the device implements an integral antenna, the enclosure port is defined as all insulating and conductive surfaces housing the device. If the device implements a removable antenna, the antenna port can be separated from the enclosure port. The antenna port includes the antenna element and its interconnecting cable surfaces. The applicability of the ESD immunity test to the whole device depends on the device classification as defined by ETSI EN 301 489-1 [18]. Applicability of the ESD immunity test to the relative device ports or the relative interconnecting cables to auxiliary equipments, depends on device accessible interfaces and manufacturer requirements, as defined by ETSI EN 301 489-1 [18]. Contact discharges are performed at conductive surfaces, while air discharges are performed at insulating surfaces. Indirect contact discharges are performed on the measurement setup horizontal and vertical coupling planes as defined in CENELEC EN 61000-4-2 [17]. For the definition of integral antenna, removable antenna, antenna port, device classification see ETSI EN 301 489-1 [18], whereas for contact and air discharges definitions see CENELEC EN 61000-4-2 [17] Application Category Immunity Level All exposed surfaces of the radio equipment and ancillary equipment in a representative configuration Contact Discharge 4 kV Air Discharge 8 kV Table 50: EMC / ESD immunity requirements as defined by CENELEC EN 61000-4-2, ETSI EN 301 489-1, 301 489-7, 301 489-24](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-122.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 124 of 148 2.15 Design-in checklist This section provides a design-in checklist. 2.15.1 Schematic checklist The following are the most important points for a simple schematic check: DC supply must provide a nominal voltage at VCC pin within the operating range limits. DC supply must be capable of supporting both the highest peak and the highest averaged current consumption values in connected-mode, as specified in the LARA-R2 series Data Sheet [1]. VCC voltage supply should be clean, with very low ripple/noise: provide the suggested bypass capacitors, in particular if the application device integrates an internal antenna. Do not apply loads which might exceed the limit for maximum available current from V_INT supply. Check that voltage level of any connected pin does not exceed the relative operating range. Provide accessible test points directly connected to the following pins of the LARA-R2 series modules: V_INT, PWR_ON and RESET_N for diagnostic purpose. Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications. Insert the suggested pF capacitors on each SIM signal and low capacitance ESD protections if accessible. Check UART signals direction, as the modules’ signal names follow ITU-T V.24 Recommendation [5]. Provide accessible test points directly connected to all the UART pins of the LARA-R2 series modules (TXD, RXD, DTR, DCD) for diagnostic purpose, in particular providing a 0 series jumper on each line to detach each UART pin of the module from the DTE application processor. Capacitance and series resistance must be limited on each high speed line of the USB interface. If the USB is not used, provide accessible test points directly connected to the USB interface (VUSB_DET, USB_D+ and USB_D- pins). Capacitance and series resistance must be limited on each high speed line of the HSIC interface. Consider providing appropriate low value series damping resistors on SDIO lines to avoid reflections. Add a proper pull-up resistor (e.g. 4.7 k) to V_INT or another proper 1.8 V supply on each DDC (I2C) interface line, if the interface is used. Check the digital audio interface specifications to connect a proper external audio device. Capacitance and series resistance must be limited on master clock output line and each I2S interface line Consider passive filtering parts on each used analog audio line. Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k resistor on the board in series to the GPIO when those are used to drive LEDs. Provide proper precautions for ESD immunity as required on the application board. Do not apply voltage to any generic digital interface pin of LARA-R2 series modules before the switch-on of the generic digital interface supply source (V_INT). All unused pins of LARA-R2 series modules can be left unconnected except the RSVD pin number 33, which must be connected to GND.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-124.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Design-in Page 125 of 148 2.15.2 Layout checklist The following are the most important points for a simple layout check: Check 50 nominal characteristic impedance of the RF transmission line connected to the ANT1 and the ANT2 ports (antenna RF interfaces). Ensure no coupling occurs between the RF interface and noisy or sensitive signals (primarily analog audio input/output signals, SIM signals, high-speed digital lines such as SDIO, USB and other data lines). Optimize placement for minimum length of RF line. Check the footprint and paste mask designed for LARA-R2 series module as illustrated in section 2.11. VCC line should be wide and as short as possible. Route VCC supply line away from RF lines / parts and other sensitive analog lines / parts. The VCC bypass capacitors in the picoFarad range should be placed as close as possible to the VCC pins, in particular if the application device integrates an internal antenna. Ensure an optimal grounding connecting each GND pin with application board solid ground layer. Use as many vias as possible to connect the ground planes on multilayer application board, providing a dense line of vias at the edges of each ground area, in particular along RF and high speed lines. Keep routing short and minimize parasitic capacitance on the SIM lines to preserve signal integrity. USB_D+ / USB_D- traces should meet the characteristic impedance requirement (90 differential and 30 common mode) and should not be routed close to any RF line / part. HSIC traces has to be designed as 50 nominal characteristic impedance transmission lines Keep the SDIO traces short, avoid stubs, avoid coupling with any RF line / part and consider low value series damping resistors to avoid reflections and other losses in signal integrity. Ensure appropriate RF precautions for the Wi-Fi and Cellular technologies coexistence Ensure appropriate RF precautions for the GNSS and Cellular technologies coexistence as described in the GNSS Implementation Application Note [22]. Route analog audio signals away from noisy sources (primarily RF interface, VCC, switching supplies). The audio outputs lines on the application board must be wide enough to minimize series resistance 2.15.3 Antenna checklist Antenna termination should provide 50 characteristic impedance with V.S.W.R at least less than 3:1 (recommended 2:1) on operating bands in deployment geographical area. Follow the recommendations of the antenna producer for correct antenna installation and deployment (PCB layout and matching circuitry). Ensure compliance with any regulatory agency RF radiation requirement, as reported in sections 4.2.2 and/or 4.3.1 for products marked with the FCC and/or IC. Ensure high and similar efficiency for both the primary (ANT1) and the secondary (ANT2) antenna. Ensure high isolation between the primary (ANT1) and the secondary (ANT2) antenna. Ensure low Envelope Correlation Coefficient between the primary (ANT1) and the secondary (ANT2) antenna: the 3D antenna radiation patterns should have radiation lobes in different directions. Ensure high isolation between the cellular antennas and any other antenna or transmitter.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-125.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Handling and soldering Page 126 of 148 3 Handling and soldering No natural rubbers, no hygroscopic materials or materials containing asbestos are employed. 3.1 Packaging, shipping, storage and moisture preconditioning For information pertaining to LARA-R2 series reels / tapes, Moisture Sensitivity levels (MSD), shipment and storage information, as well as drying for preconditioning, see the LARA-R2 series Data Sheet [1] and the u-blox Package Information Guide [25]. 3.2 Handling The LARA-R2 series modules are Electro-Static Discharge (ESD) sensitive devices. Ensure ESD precautions are implemented during handling of the module. Electrostatic discharge (ESD) is the sudden and momentary electric current that flows between two objects at different electrical potentials caused by direct contact or induced by an electrostatic field. The term is usually used in the electronics and other industries to describe momentary unwanted currents that may cause damage to electronic equipment. The ESD sensitivity for each pin of LARA-R2 series modules (as Human Body Model according to JESD22-A114F) is specified in the LARA-R2 series Data Sheet [1]. ESD prevention is based on establishing an Electrostatic Protective Area (EPA). The EPA can be a small working station or a large manufacturing area. The main principle of an EPA is that there are no highly charging materials near ESD sensitive electronics, all conductive materials are grounded, workers are grounded, and charge build-up on ESD sensitive electronics is prevented. International standards are used to define typical EPA and can be obtained for example from International Electrotechnical Commission (IEC) or American National Standards Institute (ANSI). In addition to standard ESD safety practices, the following measures should be taken into account whenever handling the LARA-R2 series modules: Unless there is a galvanic coupling between the local GND (i.e. the work table) and the PCB GND, then the first point of contact when handling the PCB must always be between the local GND and PCB GND. Before mounting an antenna patch, connect ground of the device. When handling the module, do not come into contact with any charged capacitors and be careful when contacting materials that can develop charges (e.g. patch antenna, coax cable, soldering iron,…). To prevent electrostatic discharge through the RF pin, do not touch any exposed antenna area. If there is any risk that such exposed antenna area is touched in non ESD protected work area, implement proper ESD protection measures in the design. When soldering the module and patch antennas to the RF pin, make sure to use an ESD safe soldering iron. For more robust designs, employ additional ESD protection measures on the application device integrating the LARA-R2 series modules, as described in section 2.13.3.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-126.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Handling and soldering Page 128 of 148 To avoid falling off, modules should be placed on the topside of the motherboard during soldering. The soldering temperature profile chosen at the factory depends on additional external factors like choice of soldering paste, size, thickness and properties of the base board, etc. Exceeding the maximum soldering temperature and the maximum liquidus time limit in the recommended soldering profile may permanently damage the module. Preheat Heating Cooling[°C] Peak Temp. 245°C [°C]250 250Liquidus Temperature217 217200 20040 - 60 sEnd Temp.max 4°C/s150 - 200°C150 150max 3°C/s60 - 120 s100 Typical Leadfree 100Soldering Profile50 50Elapsed time [s] Figure 68: Recommended soldering profile LARA-R2 series modules must not be soldered with a damp heat process. 3.3.3 Optical inspection After soldering the LARA-R2 series modules, inspect the modules optically to verify that the module is properly aligned and centered. 3.3.4 Cleaning Cleaning the soldered modules is not recommended. Residues underneath the modules cannot be easily removed with a washing process. Cleaning with water will lead to capillary effects where water is absorbed in the gap between the baseboard and the module. The combination of residues of soldering flux and encapsulated water leads to short circuits or resistor-like interconnections between neighboring pads. Water will also damage the sticker and the ink-jet printed text. Cleaning with alcohol or other organic solvents can result in soldering flux residues flooding into the two housings, areas that are not accessible for post-wash inspections. The solvent will also damage the sticker and the ink-jet printed text. Ultrasonic cleaning will permanently damage the module, in particular the quartz oscillators. For best results use a "no clean" soldering paste and eliminate the cleaning step after the soldering.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-128.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Approvals Page 130 of 148 4 Approvals For the complete list and specific details regarding the certification schemes approvals, see LARA-R2 series Data Sheet [1], or please contact the u-blox office or sales representative nearest you. 4.1 Product certification approval overview Product certification approval is the process of certifying that a product has passed all tests and criteria required by specifications, typically called “certification schemes” that can be divided into three distinct categories: Regulatory certification o Country specific approval required by local government in most regions and countries, as: CE (Conformité Européenne) marking for European Union FCC (Federal Communications Commission) approval for United States Industry certification o Telecom industry specific approval verifying the interoperability between devices and networks: GCF (Global Certification Forum), partnership between device manufacturers and network operators to ensure and verify global interoperability between devices and networks PTCRB (PCS Type Certification Review Board), created by United States network operators to ensure and verify interoperability between devices and North America networks Operator certification o Operator specific approval required by some mobile network operator, as: Verizon Wireless network operator in United States Even if the LARA-R2 series modules are approved under all major certification schemes, the application device that integrates the modules must be approved under all the certification schemes required by the specific application device to be deployed in the market. The required certification scheme approvals and relative testing specifications differ depending on the country or the region where the device that integrates LARA-R2 series modules must be deployed, on the relative vertical market of the device, on type, features and functionalities of the whole application device, and on the network operators where the device must operate. The certification of the application device that integrates a LARA-R2 series module and the compliance of the application device with all the applicable certification schemes, directives and standards are the sole responsibility of the application device manufacturer. LARA-R2 series modules are certified according to capabilities and options stated in the Protocol Implementation Conformance Statement document (PICS) of the module. The PICS, according to 3GPP Technical Specifications 51.010-2 [12], 36.521-2 [14] and 36.523-2 [15], is a statement of device capabilities and options. The PICS document of the application device integrating a LARA-R2 series module must be updated from the module PICS statement if any feature stated as supported by the module in its PICS document is not implemented or disabled in the application device. For more details regarding the AT commands settings that affect the PICS, see the u-blox AT Commands Manual [2]. Check the specific settings required for mobile network operators approvals as they may differ from the AT commands settings defined in the module as integrated in the application device.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-130.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Product testing Page 136 of 148 5.2 Test parameters for OEM manufacturer Because of the testing done by u-blox (with 100% coverage), an OEM manufacturer does not need to repeat firmware tests or measurements of the module RF performance or tests over analog and digital interfaces in their production test. An OEM manufacturer should focus on: Module assembly on the device; it should be verified that: o Soldering and handling process did not damaged the module components o All module pins are well soldered on device board o There are no short circuits between pins Component assembly on the device; it should be verified that: o Communication with host controller can be established o The interfaces between module and device are working o Overall RF performance test of the device including antenna Dedicated tests can be implemented to check the device. For example, the measurement of module current consumption when set in a specified status can detect a short circuit if compared with a “Golden Device” result. In addition, module AT commands can be used to perform functional tests on digital interfaces (communication with host controller, check SIM interface, GPIOs, etc.), on audio interfaces (audio loop for test purposes can be enabled by the AT+UPAR=2 command as described in the u-blox AT Commands Manual [2]), and to perform RF performance tests (see the following section 5.2.2 for details). 5.2.1 “Go/No go” tests for integrated devices A “Go/No go” test is typically to compare the signal quality with a “Golden Device” in a location with excellent network coverage and known signal quality. This test should be performed after data connection has been established. AT+CSQ is the typical AT command used to check signal quality in term of RSSI. See the u-blox AT Commands Manual [2] for detail usage of the AT command. These kinds of test may be useful as a “go/no go” test but not for RF performance measurements. This test is suitable to check the functionality of communication with host controller, SIM card as well as power supply. It is also a means to verify if components at antenna interface are well soldered. 5.2.2 Functional tests providing RF operation The overall RF functional test of the device including the antenna can be performed with basic instruments such as a spectrum analyzer (or an RF power meter) and a signal generator with the assistance of AT+UTEST command over AT command user interface. The AT+UTEST command provides a simple interface to set the module to Rx or Tx test modes ignoring the cellular signaling protocol. The command can set the module into: transmitting mode in a specified channel and power level in all supported modulation schemes and bands receiving mode in a specified channel to returns the measured power level in all supported bands See the u-blox AT Commands Manual [2] and the End user test Application Note [24], for the AT+UTEST command syntax description and examples of use.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-136.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Appendix Page 139 of 148 SARA and LARA modules are also form-factor compatible with u-blox LISA and TOBY cellular module families: although SARA, LARA, LISA (33.2 x 22.4 mm, 76-pin LCC) and TOBY (35.6 x 24.8 mm, 152-pin LGA) modules each have different form factors, the footprints of all the SARA, LARA, LISA and TOBY modules have been developed to ensure layout compatibility. With the u-blox “nested design” solution, any SARA, LARA, LISA or TOBY module can be alternatively mounted on the same space of a single “nested” application board as described in Figure 72, enabling straightforward development of products supporting different cellular radio access technologies. LISA cellular moduleLARA cellular moduleSARA cellular moduleNested application boardTOBY cellular module Figure 72: Nested design concept description: SARA, LARA, LISA and TOBY modules alternatively mounted on the same PCB A different top-side stencil (paste mask) is needed for each form factor (SARA, LARA, LISA and TOBY) to be alternatively mounted on the same space of a single “nested” application board, as described in Figure 73. LISA mounting optionwith LISA paste maskANT padTOBY mounting optionwith TOBY paste maskANT padSARA mounting optionwith SARA paste maskANT pad ANT padLARA mounting optionwith LARA paste maskLISATOBY SARA LARA Figure 73: Top-side stencil (paste mask) designs to alternatively mount SARA, LARA, LISA and TOBY modules on the same PCB Detailed guidelines to implement a nested application board, comprehensive description of the u-blox reference nested design and detailed comparison between u-blox SARA, LARA, LISA and TOBY modules are provided in the Nested Design Application Note [26].](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-139.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Appendix Page 142 of 148 SARA-U2 LARA-R2 Pin No Pin Name Description Pin Name Description Remarks for migration 26 SDA I2C Data I/O 1.8 V, open drain Driver strength: 1 mA SDA I2C Data I/O 1.8 V, open drain Driver strength: 1 mA No functional difference 27 SCL I2C Clock Output 1.8 V, open drain Driver strength: 1 mA SCL I2C Clock Output 1.8 V, open drain Driver strength: 1 mA No functional difference 28 USB_D- USB Data I/O (D-) High-Speed USB 2.0 USB_D- USB Data I/O (D-) High-Speed USB 2.0 No functional difference 29 USB_D+ USB Data I/O (D+) High-Speed USB 2.0 USB_D+ USB Data I/O (D+) High-Speed USB 2.0 No functional difference 30 GND Ground GND Ground 31 RSVD Reserved RSVD Reserved No functional difference 32 GND Ground GND Ground 33 RSVD Reserved To be externally connected to GND RSVD Reserved To be externally connected to GND No functional difference 34 I2S_WA I2S Word Alignment I/O, or GPIO 1.8 V, Driver strength: 2 mA I2S_WA I2S Word Alignment I/O21, or GPIO 1.8 V, Driver strength: 6 mA No functional difference 35 I2S_TXD I2S Data Output, or GPIO 1.8 V, Driver strength: 2 mA I2S_TXD I2S Data Output21, or GPIO 1.8 V, Driver strength: 6 mA No functional difference 36 I2S_CLK I2S Clock I/O, or GPIO 1.8 V, Driver strength: 2 mA I2S_CLK I2S Clock I/O21, or GPIO 1.8 V, Driver strength: 6 mA No functional difference 37 I2S_RXD I2S Data Input, or GPIO 1.8 V, Inner pull-down: ~9 k I2S_RXD I2S Data Input21, or GPIO 1.8 V, Inner pull-down: ~7.5 k No functional difference 38 SIM_CLK SIM Clock Output SIM_CLK SIM Clock Output No functional difference 39 SIM_IO SIM Data I/O SIM_IO SIM Data I/O No functional difference 40 SIM_RST SIM Reset Output SIM_RST SIM Reset Output No functional difference 41 VSIM SIM Supply Output VSIM SIM Supply Output No functional difference 42 SIM_DET 1.8V SIM Detection SIM_DET 1.8 V GPIO settable as SIM Detection No functional difference 43 GND Ground GND Ground 44 RSVD Reserved SDIO_D2 1.8 V, SDIO serial data [2]22 RSVD SDIO 45 RSVD Reserved SDIO_CLK 1.8 V, SDIO serial clock22 RSVD SDIO 46 RSVD Reserved SDIO_CMD 1.8 V, SDIO command22 RSVD SDIO 47 RSVD Reserved SDIO_D0 1.8 V, SDIO serial data [0]22 RSVD SDIO 48 RSVD Reserved SDIO_D3 1.8 V, SDIO serial data [3]22 RSVD SDIO 49 RSVD Reserved SDIO_D1 1.8 V, SDIO serial data [1]22 RSVD SDIO 50 GND Ground GND Ground 51-53 VCC Module Supply Input Normal range: 3.3 V – 4.4 V Extended range: 3.1 V – 4.5 V VCC Module Supply Input Normal range: 3.3 V – 4.4 V Extended range: 3.0 V – 4.5 V No functional difference Larger range for LARA-R2 54-55 GND Ground GND Ground 56 ANT RF Antenna Input/Output ANT1 RF Antenna Input/Output (primary) No functional difference 57-58 GND Ground GND Ground 59 GND Ground ANT_DET Antenna Detection Input GND ANT_DET 60-61 GND Ground GND Ground 62 ANT_DET Antenna Detection Input ANT2 RF Antenna Input (secondary) ANT_DET ANT2 63-96 GND Ground GND Ground 97-98 - Not Available RSVD Reserved No functional difference 99 - Not Available HSIC_DATA HSIC USB data line22 Not Available HSIC 100 - Not Available HSIC_STRB HSIC USB strobe line22 Not Available HSIC Table 52: SARA-U2 and LARA-R2 series modules pin assignment with remarks for migration For further details regarding the characteristics, capabilities, usage or settings applicable for each interface of the SARA-U2 and LARA-R2 series modules, see LARA-R2 series Data Sheet [1], SARA-U2 series Data Sheet [27], SARA-G3 / SARA-U2 series System Integration Manual [28], u-blox AT Commands Manual [2] and Nested Design Application Note [26]. 21 Not supported by LARA-R204 module “02” product version. 22 Not supported by “02” product versions.](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-142.png)
![LARA-R2 series - System Integration Manual UBX-16010573 - R02 Objective Specification Related documents Page 146 of 148 Related documents [1] u-blox LARA-R2 series Data Sheet, Docu No UBX-16005783 [2] u-blox AT Commands Manual, Docu No UBX-13002752 [3] u-blox EVK-R2xx User Guide, Docu No UBX-16016088 [4] u-blox Windows Embedded OS USB Driver Installation Application Note, Docu No UBX-14003263 [5] ITU-T Recommendation V.24 - 02-2000 - List of definitions for interchange circuits between the Data Terminal Equipment (DTE) and the Data Circuit-terminating Equipment (DCE). http://www.itu.int/rec/T-REC-V.24-200002-I/en [6] 3GPP TS 27.007 – AT command set for User Equipment (UE) (Release 1999) [7] 3GPP TS 27.005 – Use of Data Terminal Equipment – Data Circuit terminating; Equipment (DTE – DCE) interface for Short Message Service (SMS) and Cell Broadcast Service (CBS) (Release 1999) [8] 3GPP TS 27.010 – Terminal Equipment to User Equipment (TE-UE) multiplexer protocol (Release 1999) [9] Universal Serial Bus Revision 2.0 specification, http://www.usb.org/developers/docs/usb20_docs/ [10] High-Speed Inter-Chip USB Specification, Ver. 1.0, http://www.usb.org/developers/docs/usb20_docs/ [11] I2C-bus specification and user manual - Rev. 5 - 9 October 2012 - NXP Semiconductors, http://www.nxp.com/documents/user_manual/UM10204.pdf [12] 3GPP TS 51.010-2 – Technical Specification Group GSM/EDGE Radio Access Network; Mobile Station (MS) conformance specification; Part 2: Protocol Implementation Conformance Statement (PICS) [13] 3GPP TS 36.521-1 - Evolved Universal Terrestrial Radio Access; User Equipment conformance specification; Radio transmission and reception; Part 1: Conformance Testing [14] 3GPP TS 36.521-2 - Evolved Universal Terrestrial Radio Access (E-UTRA); User Equipment conformance specification; Radio transmission and reception; Part 2: Implementation Conformance Statement (ICS) [15] 3GPP TS 36.523-2 - Evolved Universal Terrestrial Radio Access (E-UTRA) and Evolved Packet Core (EPC); User Equipment conformance specification; Part 2: Implementation Conformance Statement (ICS) [16] GSM Association TS.09 - Battery Life Measurement and Current Consumption Technique http://www.gsma.com/newsroom/wp-content/uploads//TS.09_v8.0.pdf [17] CENELEC EN 61000-4-2 (2001) – Electromagnetic compatibility (EMC); Part 4-2: Testing and measurement techniques; Electrostatic discharge immunity test [18] ETSI EN 301 489-1 V1.8.1 – Electromagnetic compatibility and Radio spectrum Matters; EMC standard for radio equipment and services; Part 1: Common technical requirements [19] ETSI EN 301 489-7 V1.3.1 – Electromagnetic compatibility and Radio spectrum Matters; EMC standard for radio equipment and services; Part 7: Specific conditions for mobile and portable radio and ancillary equipment of digital cellular radio telecommunications systems (GSM and DCS) [20] ETSI EN 301 489-24 V1.4.1 – Electromagnetic compatibility and Radio spectrum Matters; EMC standard for radio equipment and services; Part 24: Specific conditions for IMT-2000 CDMA Direct Spread (UTRA) for Mobile and portable (UE) radio and ancillary equipment [21] u-blox Multiplexer Implementation Application Note, Docu No UBX-13001887 [22] u-blox GNSS Implementation Application Note, Docu No UBX-13001849 [23] u-blox Firmware Update Application Note, Docu No UBX-13001845 [24] u-blox End user test Application Note, Docu No UBX-13001922 [25] u-blox Package Information Guide, Docu No UBX-14001652 [26] u-blox Nested Design Application Note, Docu No UBX-16007243 [27] u-blox SARA-U2 series Data Sheet, Docu No UBX-13005287 [28] u-blox SARA-G3 and SARA-U2 series System Integration Manual, Docu No UBX-13000995 Some of the above documents can be downloaded from u-blox web-site (http://www.u-blox.com).](https://usermanual.wiki/u-blox/1EIQN2NN/User-Guide-3165118-Page-146.png)
