u blox LISAU201 3.75G HSPA Wireless Module User Manual LISA U2 series
u-blox AG 3.75G HSPA Wireless Module LISA U2 series
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![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 8 of 175 3G Transmission and Receiving: LISA-U2 modules implement 3G High-Speed Uplink Packet Access (HSUPA) category 6. LISA-U200, LISA-U201, LISA-U260 and LISA-U270 modules implement 3G High Speed Downlink Packet Access (HSDPA) category 8. LISA-U230 modules implement the 3G HSDPA category 14. HSUPA and HSDPA categories determine the maximum speed at which data can be respectively transmitted and received. Higher categories allow faster data transfer rates, as indicated in Table 1. The 3G network automatically performs adaptive coding and modulation using a choice of forward error correction code rate and choice of modulation type, to achieve the highest possible data rate and data transmission robustness according to the quality of the radio channel. 2G Transmission and Receiving: LISA-U2 series modules implement GPRS/EGPRS multislot class 12. GPRS and EGPRS multislot classes determine the maximum number of timeslots available for upload and download and thus the speed at which data can be transmitted and received. Higher classes typically allow faster data transfer rates, as indicated in Table 1. The 2G network automatically configures the number of timeslots used for reception or transmission (voice calls take precedence over GPRS/EGPRS traffic) and channel encoding (from Coding Scheme 1 up to Modulation and Coding Scheme 9), performing link adaptation to achieve the highest possible data rate. Table 2 summarizes the interfaces and features provided by LISA-U2 modules. Model UMTS Bands Interfaces Audio Functions Grade HSUPA [Mb/s] HSDPA [Mb/s] UMTS/HSPA [MHz] GSM/GPRS/EDGE quad-band UART SPI USB DDC (I2C) GPIO Analog Audio Digital Audio Network indication Antenna detection Jamming detection Embedded TCP/UDP Embedded FTP, HTTP Embedded SSL/TLS AssistNow software CellLocate® FOTA FW update via serial eCall / ERA-GLONASS Rx diversity GNSS via Modedm Standard Professional Automotive LISA-U200 5.76 7.2 800/850/900 1700/1900/2100 • 1 1 1 1 14 2 • • • • • • • • • •4 • LISA-U200 FOTA 5.76 7.2 800/850/900 1700/1900/2100 • 1 1 1 1 14 2 • • • • • • • • • • • • LISA-U201 5.76 7.2 800/850/900 1900/2100 • 1 1 1 1 14 2 • • • • • • • • • • • LISA-U230 5.76 21.1 800/850/900 1700/1900/2100 • 1 1 1 1 14 2 • • • • • • • • • • • LISA-U260 5.76 7.2 850/1900 • 1 1 1 1 14 2 • • • • • • • • • •4 • LISA-U270 5.76 7.2 900/2100 • 1 1 1 1 14 2 • • • • • • • • • •4 • LISA-U200-52S module product version is approved by SKT Korean network operator. LISA-U200-62S module product version is approved by NTT DoCoMo Japanese network operator LISA-U270-62S and LISA-U270-68S modules product versions are approved and locked for SoftBank Japanese network operator. Table 2: LISA-U2 series summary of interfaces and features 4 Not supported by ”01” product version](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-8.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 13 of 175 Function Pin Module No I/O Description Remarks GPIO GPIO1 All 20 I/O GPIO See section 1.12 GPIO2 All 21 I/O GPIO See section 1.12 GPIO3 All 23 I/O GPIO See section 1.12 GPIO4 All 24 I/O GPIO See section 1.12 GPIO5 All 51 I/O GPIO See section 1.12 GPIO6 All 39 I/O GPIO See section 1.12 GPIO7 All 40 I/O GPIO See section 1.12 GPIO8 All 53 I/O GPIO See section 1.12 GPIO9 All 54 I/O GPIO See section 1.12 GPIO10 All 55 I/O GPIO See section 1.12 GPIO11 All 56 I/O GPIO See section 1.12 GPIO12 All 57 I/O GPIO See section 1.12 GPIO13 All 58 I/O GPIO See section 1.12 GPIO14 All 59 I/O GPIO See section 1.12 USB VUSB_DET All 18 I USB detect input Input for VBUS (5 V typical) USB supply sense to enable USB interface. Provide access to the pin for FW update and debugging if the USB interface is not connected to the application processor. See section 1.9.3 USB_D- All 26 I/O USB Data Line D- 90 Ω nominal differential impedance (Z0) 30 Ω nominal common mode impedance (ZCM) Pull-up or pull-down resistors and external series resistors as required by USB 2.0 specifications [7] are part of the USB pad driver and need not be provided externally. Provide access to the pin for FW update and debugging if the USB interface is not connected to the application processor. See section 1.9.3 USB_D+ All 27 I/O USB Data Line D+ 90 Ω nominal differential impedance (Z0) 30 Ω nominal common mode impedance (ZCM) Pull-up or pull-down resistors and external series resistors as required by USB 2.0 specifications [7] are part of the USB pad driver and need not be provided externally. Provide access to the pin for FW update and debugging if the USB interface is not connected to the application processor. See section 1.9.3 System PWR_ON All 19 I Power-on input PWR_ON pin has high input impedance. Do not keep floating in noisy environment: external pull-up required. See section 1.6.1 RESET_N All 22 I External reset input Internal 10 kΩ pull-up to V_BCKP. See section 1.6.3](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-13.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 15 of 175 1.4 Operating modes LISA-U2 series modules have several operating modes. The operating modes are defined in Table 4 and described in details in Table 5, providing general guidelines for operation. General Status Operating Mode Definition Power-down Not-Powered Mode VCC supply not present or below operating range: module is switched off. Power-Off Mode VCC supply within operating range and module is switched off. Normal Operation Idle-Mode Module processor core runs with 32 kHz as reference oscillator. Active-Mode Module processor core runs with 26 MHz as reference oscillator. Connected-Mode Voice or data call enabled and processor core runs with 26 MHz as reference oscillator. Table 4: Module operating modes definition Operating Mode Description Transition between operating modes Not-Powered Module is switched off. Application interfaces are not accessible. Internal RTC timer operates only if a valid voltage is applied to V_BCKP pin. When VCC supply is removed, the module enters not-powered mode. When in not-powered mode, the module cannot be switched on by a low pulse on PWR_ON input, by a rising edge on RESET_N input, or by a preset RTC alarm. When in not-powered mode, the module can be switched on applying VCC supply (see 1.6.1) so that the module switches from not-powered to active-mode. Power-Off Module is switched off: normal shutdown by an appropriate power-off event (see 1.6.2). Application interfaces are not accessible. Only the internal RTC timer in operation. When the module is switched off by an appropriate power-off event (see 1.6.2), the module enters power-off mode from active-mode. When in power-off mode, the module can be switched on by a low pulse on PWR_ON input, by a rising edge on RESET_N input, or by a preset RTC alarm (see 1.6.1): module switches from power-off to active-mode. When VCC supply is removed, the module switches from power-off mode to not-powered mode. Idle Application interfaces are disabled: the module does not accept data signals from an external device connected to the module. The module automatically enters idle-mode whenever possible if power saving is enabled by AT+UPSV (see u-blox AT Commands Manual [2]), reducing current consumption (see 1.5.3.3). If HW flow control is enabled (default setting) and AT+UPSV=1 or AT+UPSV=3 has been set, the UART CTS line indicates when the UART is enabled (see 1.9.2.2, 1.9.2.3). If HW flow control is disabled by AT&K0, the UART CTS line is fixed to ON state (see 1.9.2.2). Power saving configuration is not enabled by default: it can be enabled by AT+UPSV (see the u-blox AT Commands Manual [2]). The module automatically switches from active-mode to idle-mode whenever possible if power saving is enabled (see 1.5.3.3, 1.9.2.3, 1.9.3.2, 1.9.4.2 and u-blox AT Commands Manual [2], AT+UPSV). The module wakes up from idle-mode to active-mode in these events: Automatic periodic monitoring of the paging channel for the paging block reception according to network conditions (see 1.5.3.3, 1.9.2.3) Automatic periodic enable of the UART interface to receive and send data, if AT+UPSV=1 has been set (see 1.9.2.3) RTC alarm occurs (see u-blox AT Commands Manual [2], AT+CALA) Data received on UART interface, if HW flow control has been disabled by AT&K0 and AT+UPSV=1 has been set (see 1.9.2.3) RTS input set ON by the DTE if HW flow control has been disabled by AT&K0 and AT+UPSV=2 has been set (see 1.9.2.3) DTR input set ON by DTE if AT+UPSV=3 has been set (see 1.9.2.3) USB detection, applying 5 V (typ.) to VUSB_DET input (see 1.9.3) The connected USB host forces a remote wakeup of the module as USB device (see 1.9.3) The connected SPI master indicates by the SPI_MRDY input signal that it is ready for transmission or reception (see 1.9.4) The connected u-blox GNSS receiver indicates by the GPIO3 pin that it is ready to send data (see 1.10, 1.12)](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-15.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 16 of 175 Operating Mode Description Transition between operating modes Active The module is ready to accept data signals from an external device unless power saving configuration is enabled by AT+UPSV (see sections 1.9.2.3, 1.9.3.2, 1.9.4.2 and u-blox AT Commands Manual [2]). When the module is switched on by an appropriate power-on event (see 1.6.1), the module enters active-mode from not-powered or power-off mode. If power saving configuration is enabled by the AT+UPSV command, the module automatically switches from active to idle-mode whenever possible and the module wakes up from idle to active-mode in the events listed above (see the idle to active transition description). When a voice call or a data call is initiated, the module switches from active-mode to connected-mode. Connected A voice call or a data call is in progress. When a voice or a data call is enabled, the application interfaces are kept enabled and the module is prepared to accept data from an external device unless power saving configuration is enabled by AT+UPSV (see 1.9.2.3, 1.9.3.2, 1.9.4.2 and u-blox AT Commands Manual [2]). When a voice call or a data call is initiated, the module enters connected-mode from active-mode. If power saving configuration is enabled by the AT+UPSV command, the module automatically switches from connected to idle-mode whenever possible in case of PSD data call with internal context activation, and then it wakes up from idle to connected mode in the events listed above (see the idle to active transition description). When a voice call or a data call is terminated, the module returns to the active-mode. Table 5: Module operating modes description Figure 2 describes the transition between the different operating modes. Switch ON:•Apply VCCIf power saving is enabled and there is no activity for a defined time intervalAny wake up event described in the module operating modes summary table aboveIncoming/outgoing call or other dedicated device network communicationCall terminated, communication droppedRemove VCCSwitch ON:•PWR_ON•RESET_N•RTC AlarmNot poweredPower offActiveConnected IdleSwitch OFF:•AT+CPWROFF•PWR_ON Figure 2: Operating modes transition](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-16.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 18 of 175 Pins with supply function are reported in Table 6, Table 12 and Table 15. LISA-U2 series modules must be supplied via the VCC pins. There is only one main power supply input, available on the three VCC pins that must be all connected to the external power supply. The VCC pins are directly connected to the RF power amplifiers and to the integrated Power Management Unit (PMU) within the module: all supply voltages needed by the module are generated from the VCC supply by integrated voltage regulators. V_BCKP is the Real Time Clock (RTC) supply. When the VCC voltage is within the valid operating range, the internal PMU supplies the Real Time Clock and the same supply voltage will be available to the V_BCKP pin. If the VCC voltage is under the minimum operating limit (for example, during not powered mode), the Real Time Clock can be externally supplied via the V_BCKP pin (see section 1.5.4). When a 1.8 V or a 3 V SIM card type is connected, LISA-U2 series modules automatically supply the SIM card via the VSIM pin. Activation and deactivation of the SIM interface with automatic voltage switch from 1.8 to 3 V is implemented, in accordance to the ISO-IEC 7816-3 specifications. The same voltage domain used internally to supply the digital interfaces is also available on the V_INT pin, to allow more economical and efficient integration of the LISA-U2 series modules in the final application. The integrated Power Management Unit also provides the control state machine for system start up and system reset control. 1.5.2 Module supply (VCC) The LISA-U2 series modules must be supplied through the VCC pins by a DC power supply. Voltages must be stable: during operation, the current drawn from VCC can vary by some orders of magnitude, especially due to surging consumption profile of the GSM system (described in the section 1.5.3). It is important that the system power supply circuit is able to support peak power (see LISA-U2 series Data Sheet [1] for the detailed specifications). Name Description Remarks VCC Module power supply input VCC pins are internally connected, but all the available pads must be connected to the external supply in order to minimize the power loss due to series resistance. Clean and stable supply is required: low ripple and low voltage drop must be guaranteed. Voltage provided must always be above the minimum limit of the operating range. Consider that during a GSM call there are large current spikes in connected mode. GND Ground GND pins are internally connected but a good (low impedance) external ground can improve RF performance: all available pads must be connected to ground. Table 6: Module supply pins VCC pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level can be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. The voltage provided to the VCC pins must be within the normal operating range limits as specified in the LISA-U2 series Data Sheet [1]. Complete functionality of the module is only guaranteed within the specified minimum and maximum VCC voltage normal operating range.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-18.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 19 of 175 The module cannot be switched on if the VCC voltage value is below the specified normal operating range minimum limit. Ensure that the input voltage at VCC pins is above the minimum limit of the normal operating range for more than 3 s after the start of the module switch-on sequence. When LISA-U2 series modules are in operation, the voltage provided to VCC pins can go outside the normal operating range limits but must be within the extended operating range limits specified in LISA-U2 series Data Sheet [1]. Occasional deviations from the ETSI specifications may occur when the input voltage at VCC pins is outside the normal operating range and is within the extended operating range. LISA-U2 series modules switch off when VCC voltage value drops below the specified extended operating range minimum limit: ensure that the input voltage at VCC pins never drops below the minimum limit of the extended operating range when the module is switched on, not even during a GSM transmit burst, where the current consumption can rise up to maximum peaks of 2.5 A in case of a mismatched antenna load. Operation above the normal operating range maximum limit is not recommended and extended exposure beyond it may affect device reliability. Stress beyond the VCC absolute maximum ratings can cause permanent damage to the module: if necessary, voltage spikes beyond VCC absolute maximum ratings must be restricted to values within the specified limits by using appropriate protection. When designing the power supply for the application, pay specific attention to power losses and transients. The DC power supply must be able to provide a voltage profile to the VCC pins with the following characteristics: o Voltage drop during transmit slots must be lower than 400 mV o No undershoot or overshoot at the start and at the end of transmit slots o Voltage ripple during transmit slots must be minimized: lower than 70 mVpp if fripple ≤ 200 kHz lower than 10 mVpp if 200 kHz < fripple ≤ 400 kHz lower than 2 mVpp if fripple > 400 kHz TimeundershootovershootripplerippledropVoltage3.8 V (typ)RX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotRX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)GSM frame 4.615 ms (1 frame = 8 slots) Figure 4: Description of the VCC voltage profile versus time during a GSM call](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-19.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 21 of 175 The usage of a regulator or a battery not able to withstand the maximum VCC peak current consumption stated in LISA-U2 series Data Sheet [1] is generally not recommended. However, if the selected regulator or battery is not able to withstand the maximum VCC peak current, it must be able to withstand at least the maximum average current consumption value specified in the module data sheet Error! Reference source not found.. The additional energy required by the module during a GSM/GPRS Tx slot (when in the worst case the current consumption can rise up to 2.5 A, as described in section 1.5.3.1) can be provided by an appropriate bypass tank capacitor or supercapacitor with very large capacitance and very low ESR placed close to the module VCC pins. Depending on the actual capability of the selected regulator or battery, the required capacitance can be considerably larger than 1 mF and the required ESR can be in the range of few tens of m. Carefully evaluate the implementation of this solution since aging and temperature conditions significantly affect the actual capacitor characteristics. The following sections highlight some design aspects for each of the supplies listed above. Switching regulator The characteristics of the switching regulator connected to VCC pins should meet the following requirements: Power capability: the switching regulator with its output circuit must be capable of providing a voltage value to the VCC pins within the specified operating range and must be capable of delivering 2.5 A current pulses with 1/8 duty cycle to the VCC pins Low output ripple: the switching regulator together with its output circuit must be capable of providing a clean (low noise) VCC voltage profile High switching frequency: for best performance and for smaller applications select a switching frequency ≥ 600 kHz (since L-C output filter is typically smaller for high switching frequency). The use of a switching regulator with a variable switching frequency or with a switching frequency lower than 600 kHz must be carefully evaluated since this can produce noise in the VCC voltage profile and therefore negatively impact GSM modulation spectrum performance. An additional L-C low-pass filter between the switching regulator output to VCC supply pins can mitigate the ripple on VCC, but adds extra voltage drop due to resistive losses on series inductors PWM mode operation: select preferably regulators with Pulse Width Modulation (PWM) mode. While in connected mode Pulse Frequency Modulation (PFM) mode and PFM/PWM mode transitions must be avoided to reduce the noise on the VCC voltage profile. Switching regulators able to switch between low ripple PWM mode and high efficiency burst or PFM mode can be used, provided the mode transition occurs when the module changes status from idle/active mode to connected mode (where current consumption increases to a value greater than 100 mA): it is permissible to use a regulator that switches from the PWM mode to the burst or PFM mode at an appropriate current threshold (e.g. 60 mA) Output voltage slope: the use of the soft start function provided by some voltage regulator must be carefully evaluated, since the voltage at the VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the module Figure 6 and the components listed in Table 7 show an example of a high reliability power supply circuit, where the module VCC is supplied by a step-down switching regulator capable of delivering 2.5 A current pulses with low output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz. The use of a switching regulator is suggested when the difference from the available supply rail to the VCC value is high: switching regulators provide good efficiency transforming a 12 V supply to the typical 3.8 V value of the VCC supply.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-21.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 27 of 175 1.5.3 Current consumption profiles During operation, the current drawn by the LISA-U2 series modules through the VCC pins can vary by several orders of magnitude. This ranges from the high peak of current consumption during GSM transmitting bursts at maximum power level in 2G connected mode, to continuous high current drawn in UMTS connected mode, to the low current consumption during power saving in idle-mode. 1.5.3.1 2G connected mode When a GSM call is established, the VCC consumption is determined by the current consumption profile typical of the GSM transmitting and receiving bursts. The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which is regulated by the network. If the module is transmitting in GSM talk mode in the GSM 850 or in the E-GSM 900 band and at the maximum RF power control level (approximately 2 W or 33 dBm in the allocated transmit slot/burst) the current consumption can reach up to 2500 mA (with a highly unmatched antenna) for 576.9 µs (width of the transmit slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), so with a 1/8 duty cycle according to GSM TDMA (Time Division Multiple Access). If the module is in GSM connected mode in the DCS 1800 or in the PCS 1900 band, the current consumption figures are lower than the one in the GSM 850 or in the E-GSM 900 band, due to 3GPP transmitter output power specifications (see LISA-U2 series Data Sheet [1]). During a GSM call, current consumption is in the order of 60-130 mA in receiving or in monitor bursts and is about 10-40 mA in the inactive unused bursts (low current period). The more relevant contribution to determine the average current consumption is set by the transmitted power in the transmit slot. An example of current consumption profile of the data module in GSM talk mode is shown in Figure 11. Time [ms]RX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotRX slotunused slotunused slotTX slotunused slotunused slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)Current [A]Peak current depends on TX power and actual antenna loadGSM frame 4.615 ms (1 frame = 8 slots)1.51.00.50.02.52.0 Figure 11: VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot)](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-27.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 28 of 175 When a GPRS connection is established there is a different VCC current consumption profile also determined by the transmitting and receiving bursts. In contrast to a GSM call, during a GPRS connection more than one slot can be used to transmit and/or more than one slot can be used to receive. The transmitted power depends on network conditions, which set the peak current consumption, but following the GPRS specifications the maximum transmitted RF power is reduced if more than one slot is used to transmit, so the maximum peak of current consumption is not as high as can be in case of a GSM call. If the module transmits in GPRS class 12 connected mode in the GSM 850 or in the E-GSM 900 band at the maximum power control level, the current consumption can reach up to 1600 mA (with unmatched antenna). This happens for 2.307 ms (width of the 4 transmit slots/bursts) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/bursts), so with a 1/2 duty cycle, according to GSM TDMA. If the module is in GPRS connected mode in the DCS 1800 or in the PCS 1900 band, the current consumption figures are lower than in the GSM 850 or in the E-GSM 900 band, due to 3GPP transmitter output power specifications (see LISA-U2 series Data Sheet [1]). Figure 12 reports the current consumption profiles in GPRS class 12 connected mode, in the GSM 850 or in the E-GSM 900 band, with 4 slots used to transmit and 1 slot used to receive. Time [ms]RX slotunused slotTX slotTX slotTX slotTX slotMON slotunused slotRX slotunused slotTX slotTX slotTX slotTX slotMON slotunused slotGSM frame 4.615 ms (1 frame = 8 slots)Current [A]GSM frame 4.615 ms (1 frame = 8 slots)1.51.00.50.02.52.0Peak current depends on TX power and actual antenna load Figure 12: VCC current consumption profile versus time during a GPRS/EDGE connection (4TX slots, 1 RX slot) In case of EDGE connections the VCC current consumption profile is very similar to the GPRS current profile, so the image shown in Figure 12, representing the current consumption profile in GPRS class 12 connected mode, is valid for the EDGE class 12 connected mode as well.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-28.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 29 of 175 1.5.3.2 3G connected mode During a 3G connection, the module can transmit and receive continuously due to the Frequency Division Duplex (FDD) mode of operation with the Wideband Code Division Multiple Access (WCDMA). The current consumption depends again on output RF power, which is always regulated by network commands. These power control commands are logically divided into a slot of 666 µs, thus the rate of power change can reach a maximum rate of 1.5 kHz. There are no high current peaks as in the 2G connection, since transmission and reception are continuously enabled due to FDD WCDMA implemented in the 3G that differs from the TDMA implemented in the 2G case. In the worst scenario, corresponding to a continuous transmission and reception at maximum output power (approximately 250 mW or 24 dBm), the current drawn by the module at the VCC pins is in the order of continuous 500-800 mA (see LISA-U2 series Data Sheet [1] for detailed values). Even at lowest output RF power (approximately 0.01 µW or -50 dBm), the current still remains in the order of 200 mA due to module baseband processing and transceiver activity. An example of current consumption profile of the data module in UMTS/HSxPA continuous transmission mode is shown in Figure 13. Time [ms]3G frame 10 ms (1 frame = 15 slots)Current [mA]Current consumption depends on TX power and actual antenna load170 mA1 slot 666 µs850 mA0300200100500400600700800 Figure 13: VCC current consumption profile versus time during a UMTS/HSPA connection When a packet data connection is established, the actual current profile depends on the amount of transmitted packets; there might be some periods of inactivity between allocated slots where current consumption drops about 100 mA. Alternatively, at higher data rates the transmitted power is likely to increase due to the higher quality signal required by the network to cope with enhanced data speed.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-29.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 30 of 175 1.5.3.3 2G and 3G cyclic idle/active mode (power saving enabled) The power saving configuration is by default disabled, but it can be enabled using the appropriate AT command (see the u-blox AT Commands Manual [2], AT+UPSV command). When power saving is enabled, the module automatically enters idle-mode whenever possible. When power saving is enabled, the module is registered or attached to a network and a voice or data call is not enabled, the module automatically enters idle-mode whenever possible, but it must periodically monitor the paging channel of the current base station (paging block reception), in accordance to GSM system requirements. When the module monitors the paging channel, it wakes up to active mode, to enable the reception of paging block. In between, the module switches to idle-mode. This is known as GSM discontinuous reception (DRX). The module processor core is activated during the paging block reception, and automatically switches its reference clock frequency from 32 kHz to the 26 MHz used in active-mode. The time period between two paging block receptions is defined by the network (2G or 3G). This is the paging period parameter, fixed by the base station through broadcast channel sent to all users on the same serving cell. In case of 2G network, the time interval between two paging block receptions can be from 470.76 ms (DRX = 2, i.e. width of 2 GSM multiframes = 2 x 51 GSM frames = 2 x 51 x 4.615 ms) up to 2118.42 ms (DRX = 9, i.e. width of 9 GSM multiframes = 9 x 51 frames = 9 x 51 x 4.615 ms). In case of 3G network, the principle is similar but time interval changes from 640 ms (DRX = 6, i.e. the width of 26 x 3G frames = 64 x 10 ms = 640 ms) up to 5120 ms (DRX = 9, i.e. width of 29 x 3G frames = 512 x 10 ms = 5120 ms). An example of a module current consumption profile is shown in Figure 14: the module is registered with the network (2G or 3G), automatically enters idle-mode and periodically wakes up to active mode to monitor the paging channel for paging block reception. 20-30 msIDLE MODE ACTIVE MODE IDLE MODEActive Mode EnabledIdle Mode Enabled2G case: 0.44-2.09 s 3G case: 0.61-5.09 sIDLE MODE20-30 msACTIVE MODETime [s]Current [mA]100500Time [ms]Current [mA]100500RX EnabledDSP Enabled Figure 14: Description of VCC current consumption profile versus time when the module is registered with 2G or 3G networks: the module is in idle-mode and periodically wakes up to active mode to monitor the paging channel for paging block reception](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-30.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 31 of 175 1.5.3.4 2G and 3G fixed active mode (power saving disabled) Power saving configuration is by default disabled, or it can be disabled using the appropriate AT command (see the u-blox AT Commands Manual [2], AT+UPSV command). When power saving is disabled, the module does not automatically enter idle-mode whenever possible: the module remains in active mode. The module processor core is activated during active-mode, and the 26 MHz reference clock frequency is used. An example of the current consumption profile of the data module when power saving is disabled is shown in Figure 15: the module is registered with the network, active-mode is maintained, and the receiver and the DSP are periodically activated to monitor the paging channel for paging block reception. ACTIVE MODE2G case: 0.47-2.12 s 3G case: 0.64-5.12 sPaging periodTime [s]Current [mA]100500Time [ms]Current [mA]100500RX EnabledDSP Enabled Figure 15: Description of the VCC current consumption profile versus time when power saving is disabled: the active-mode is always held, and the receiver and the DSP are periodically activated to monitor the paging channel for paging block reception](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-31.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 32 of 175 1.5.4 RTC Supply (V_BCKP) The V_BCKP pin connects the supply for the Real Time Clock (RTC) and Power-On / Reset internal logic. This supply domain is internally generated by a linear regulator integrated in the Power Management Unit. The output of this linear regulator is always enabled when the main voltage supply provided to the module through VCC is within the valid operating range, with the module switched-off or powered-on. V_BCKP supply output pin provides internal short circuit protection to limit start-up current and protect the device in short circuit situations. No additional external short circuit protection is required. Name Description Remarks V_BCKP Real Time Clock supply V_BCKP output voltage = 1.8 V (typical) Generated by the module to supply Real Time Clock when VCC supply voltage is within valid operating range. Table 12: Real Time Clock supply pin The V_BCKP pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. The RTC provides the time reference (date and time) of the module, also in power-off mode, when the V_BCKP voltage is within its valid range (specified in the Input characteristics of Supply/Power pins table in LISA-U2 series Data Sheet [1]). The RTC timing is normally used to set the wake-up interval during idle-mode periods between network paging, but is able to provide programmable alarm functions by means of the internal 32.768 kHz clock. The RTC can be supplied from an external back-up battery through the V_BCKP, when the main voltage supply is not provided to the module through VCC. This lets the time reference (date and time) run until the V_BCKP voltage is within its valid range, even when the main supply is not provided to the module. The RTC oscillator does not necessarily stop operation (i.e. the RTC counting does not necessarily stop) when V_BCKP voltage value drops below the specified operating range minimum limit (1.00 V): the RTC value read after a system restart could be not reliable, as explained in Table 13. V_BCKP voltage value RTC value reliability Notes 1.00 V < V_BCKP < 1.90 V RTC oscillator does not stop operation RTC value read after a restart of the system is reliable V_BCKP within operating range 0.05 V < V_BCKP < 1.00 V RTC oscillator does not necessarily stop operation RTC value read after a restart of the system is not reliable V_BCKP below operating range 0.00 V < V_BCKP < 0.05 V RTC oscillator stops operation RTC value read after a restart of the system is reliable V_BCKP below operating range Table 13: RTC value reliability as function of V_BCKP voltage value Consider that the module cannot switch on if a valid voltage is not present on VCC even when the RTC is supplied through V_BCKP (meaning that VCC is mandatory to switch-on the module). The RTC has very low power consumption, but is highly temperature dependent. For example at 25°C, with the V_BCKP voltage equal to the typical output value, the power consumption is approximately 2 µA (see the Input characteristics of Supply/Power pins table in the LISA-U2 series Data Sheet [1] for the detailed specification), whereas at 70°C and an equal voltage the power consumption increases to 5-10 µA.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-32.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 33 of 175 The internal regulator for V_BCKP is optimized for low leakage current and very light loads. It is not recommended to use V_BCKP to supply external loads. If V_BCKP is left unconnected and the module main voltage supply is removed from VCC, the RTC is supplied from the bypass capacitor mounted inside the module. However, this capacitor is not able to provide a long buffering time: within few milliseconds the voltage on V_BCKP will go below the valid range (1 V min). This has no impact on cellular connectivity, as all the functionalities of the module do not rely on date and time setting. Leave V_BCKP unconnected if the RTC is not required when the VCC supply is removed. The date and time will not be updated when VCC is disconnected. If VCC is always supplied, then the internal regulator is supplied from the main supply and there is no need for an external component on V_BCKP. If RTC is required to run for a time interval of T [s] at 25°C when VCC supply is removed, place a capacitor with a nominal capacitance of C [µF] at the V_BCKP pin. Choose the capacitor using the following formula: C [µF] = (Current_Consumption [µA] x T [s]) / Voltage_Drop [V] = 2.50 x T [s] for LISA-U2 series For example, a 100 µF capacitor (such as the Murata GRM43SR60J107M) can be placed at V_BCKP to provide a long buffering time. This capacitor will hold V_BCKP voltage within its valid range for around 50 s at 25°C, after the VCC supply is removed. If a very long buffering time is required, a 70 mF super-capacitor (e.g. Seiko Instruments XH414H-IV01E) can be placed at V_BCKP, with a 4.7 k series resistor to hold the V_BCKP voltage within its valid range for approximately 10 hours at 25°C, after the VCC supply is removed. The purpose of the series resistor is to limit the capacitor charging current due to the large capacitor specifications, and also to let a fast rise time of the voltage value at the V_BCKP pin after VCC supply has been provided. These capacitors will allow the time reference to run during battery disconnection. LISA-U2 seriesC1(a)2V_BCKPR2LISA-U2 seriesC2(superCap)(b)2V_BCKPD3LISA-U2 seriesB3(c)2V_BCKP Figure 16: Real time clock supply (V_BCKP) application circuits: (a) using a 100 µF capacitor to let the RTC run for ~50 s after VCC removal; (b) using a 70 mF capacitor to let RTC run for ~10 hours after VCC removal; (c) using a non-rechargeable battery Reference Description Part Number - Manufacturer C1 100 µF Tantalum Capacitor GRM43SR60J107M - Murata R2 4.7 kΩ Resistor 0402 5% 0.1 W RC0402JR-074K7L - Yageo Phycomp C2 70 mF Capacitor XH414H-IV01E - Seiko Instruments Table 14: Example of components for V_BCKP buffering If longer buffering time is required to allow the time reference to run during a disconnection of the VCC supply, then an external battery can be connected to V_BCKP pin. The battery should be able to provide a proper nominal voltage and must never exceed the maximum operating voltage for V_BCKP (specified in the Input characteristics of Supply/Power pins table in LISA-U2 series Data Sheet [1]). The connection of the battery to V_BCKP should be done with a suitable series resistor for a rechargeable battery, or with an appropriate series diode for a non-rechargeable battery. The purpose of the series resistor is to limit the battery charging current due to the battery specifications, and also to allow a fast rise time of the voltage value at the V_BCKP pin after](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-33.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 35 of 175 1.5.5 Interface supply (V_INT) The same voltage domain used internally to supply the digital interfaces is also available on the V_INT pin. The internal regulator that generates the V_INT supply is a switching step down converter that is directly supplied from VCC. The voltage regulator output is set to 1.8 V (typical) when the module is switched on and is disabled when the module is switched off or when the RESET_N pin is forced the low level. The switching regulator operates in Pulse Width Modulation (PWM) for high output current mode but automatically switches to Pulse Frequency Modulation (PFM) at low output loads for greater efficiency, e.g. when the module is in idle-mode between paging periods. V_INT supply output pin provides internal short circuit protection to limit start-up current and protect the device in short circuit situations. No additional external short circuit protection is required. Name Description Remarks V_INT Digital Interfaces supply output V_INT = 1.8V (typical) generated by the module when it is switched-on and the RESET_N (external reset input pin) is not forced to the low level. V_INT is the internal supply for digital interfaces. The user may draw limited current from this supply rail. Table 15: Interface supply pin The V_INT pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. Since it supplies internal digital circuits (see Figure 3), V_INT is not suited to directly supply any sensitive analog circuit: the voltage ripple can range from 15 mVpp during active mode (PWM), to 70 mVpp in idle-mode (PFM). V_INT can be used to supply external digital circuits operating at the same voltage level as the digital interface pins, i.e. 1.8 V (typical). It is not recommended to supply analog circuitry without adequate filtering for digital noise. Do not apply loads which might exceed the limit for maximum available current from V_INT supply, as this can cause malfunctions in internal circuitry supplies to the same domain. The detailed electrical characteristics are described in LISA-U2 series Data Sheet [1]. V_INT can only be used as an output; do not connect any external regulator on V_INT. If not used, this pin should be left unconnected. The V_INT digital interfaces supply output is mainly used to: Pull-up DDC (I2C) interface signals (see section 1.10.2 for more details) Pull-up SIM detection signal (see section 1.8 for more details) Supply voltage translators to connect digital interfaces of the module to a 3.0 V device (see sections 1.9.2.4, 1.9.4.4 for more details) Supply a 1.8 V u-blox 6 or subsequent GNSS receiver (see section 1.10.2 for more details) Indicate when the module is switched on and the RESET_N external hardware reset input is not forced low (see sections 1.6.1.5, 1.6.2 and 1.6.3 for more details)](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-35.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 36 of 175 1.6 System functions 1.6.1 Module power-on When the LISA-U2 series modules are in the not-powered mode (i.e. switched off with the VCC module supply not applied), they can be switched on by: Rising edge on the VCC pin to a valid voltage as module supply (i.e. applying module supply) Alternately, the RESET_N pin can be held to the low level during the VCC rising edge, so that the module switches on releasing the RESET_N pin when the VCC module supply voltage stabilizes at its proper nominal value within the normal operating range The status of the PWR_ON input pin of LISA-U2 series modules while applying the VCC module supply is not relevant: during this phase the PWR_ON pin can be set high or low by the external circuit. When the LISA-U2 series modules are in the power-off mode (i.e. switched off by means of the AT+CPWROFF command, with valid VCC module supply applied), they can be switched on by: Low pulse on the PWR_ON pin (i.e. forcing to the low level the pin normally high by external pull-up) Rising edge on the RESET_N pin (i.e. releasing from low level the pin, normally high by internal pull-up) RTC alarm (i.e. pre-programmed scheduled time by AT+CALA command) Name Description Remarks PWR_ON Power-on input PWR_ON pin has high input impedance. Do not keep floating in noisy environment: external pull-up required. Table 16: Power-on pin The PWR_ON pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. 1.6.1.1 Rising edge on VCC Applying a proper supply to VCC pins, the module supply supervision circuit controls the subsequent activation of the power up state machines: the module is switched on when the voltage rises up to the VCC normal operating range minimum limit starting from a voltage value lower than 2.25 V (see LISA-U2 series Data Sheet [1] for the VCC normal operating range minimum limit). The voltage at VCC pins must ramp from 2.5 V to 3.2 V within 1 ms to properly switch on the module. If the external supply circuit is not able to provide this VCC voltage slope, keep the RESET_N input low during the VCC rising edge, so that the module switches on, releasing the RESET_N pin when the VCC voltage stabilizes at its nominal value within the normal operating range. The status of the PWR_ON input pin during the VCC apply phase is not relevant: LISA-U2 modules switch on when a proper rising edge on the VCC pin is applied, during this phase the PWR_ON pin can be set high or low by the external circuit.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-36.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 37 of 175 1.6.1.2 Low pulse on PWR_ON When the module is in power-off mode, i.e. it has been properly switched off as described in the section 1.6.2 (e.g. by the AT+CPWROFF command) and a voltage within the operating range is maintained at the VCC pins, the module can be switched on by means of the PWR_ON input pin: a falling edge must be provided on the PWR_ON pin, which must be then held low for an appropriate time period as specified in LISA-U2 series Data Sheet [1]. The electrical characteristics of the PWR_ON input pin are different from the other digital I/O interfaces; the detailed electrical characteristics are described in LISA-U2 series Data Sheet [1]. The PWR_ON pin has high input impedance and is weakly pulled to the high level on the module. Avoid keeping it floating in a noisy environment. To hold the high logic level stable, the PWR_ON pin must be connected to a pull-up resistor (e.g. 100 kΩ) biased by the V_BCKP supply pin of the module. Following are some typical examples of application circuits to turn the module on using the PWR_ON input pin. Connecting the PWR_ON input to an external device (e.g. application processor), use an open drain output on the external device with an external pull-up resistor (e.g. 100 kΩ) biased by V_BCKP supply pin of the module. A push-pull output of an application processor can also be used: in this case the pull-up can be used to pull the PWR_ON level high when the application processor is switched off. If the high-level voltage of the push-pull output pin of the application processor is greater than the maximum input voltage operating range of the V_BCKP pin (see the V_BCKP Input characteristics of Supply/Power pins table in LISA-U2 series Data Sheet [1]), the V_BCKP supply cannot be used to bias the pull-up resistor: the supply rail of the application processor or the VCC supply could be used, but this will increase the V_BCKP (RTC supply) current consumption when the module is in not-powered mode (VCC supply not present). Using a push-pull output of the external device, take care to fix the proper level in all the possible scenarios to avoid an inappropriate switch-on of the module. Open Drain OutputApplication processorLISA-U2 seriesRext2V_BCKP19 PWR_ON Figure 17: PWR_ON application circuits using an open drain output of an application processor Reference Description Remarks Rext 100 kΩ Resistor 0402 5% 0.1 W External pull-up resistor Table 17: Example of pull-up resistor for the PWR_ON application circuit](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-37.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 38 of 175 1.6.1.3 Rising edge on RESET_N When the module is in power-off mode (i.e. switched off with VCC maintained), the module can be switched on by means of the RESET_N input pin alternatively to the PWR_ON input pin: the RESET_N signal must be forced low for at least 50 ms and then released to generate a rising edge that starts the module power-on sequence. RESET_N input pin can also be used to perform an “external” or “hardware” reset of the module, as described in the section 1.6.3. Electrical characteristics of the LISA-U2 series RESET_N input are slightly different from the other digital I/O interfaces: the pin provides different input voltage thresholds. Detailed electrical characteristics are described in LISA-U2 series Data Sheet [1]. RESET_N is pulled high to V_BCKP by an integrated pull-up resistor also when the module is in power-off mode. Therefore an external pull-up is not required on the application board. The simplest way to switch on the module by means of the RESET_N input pin is to use a push button that shorts the RESET_N pin to ground: the module will be switched on at the release of the push button, since the RESET_N will be forced to the high level by the integrated pull-up resistor, generating a rising edge. If RESET_N is connected to an external device (e.g. an application processor on an application board) an open drain output can be directly connected without any external pull-up. A push-pull output can be used too: in this case make sure that the high level voltage of the push-pull circuit is below the maximum voltage operating range of the RESET_N pin (specified in the RESET_N pin characteristics table in LISA-U2 series Data Sheet [1]). To avoid unwanted power-on or reset of the module make sure to fix the proper level at the RESET_N input pin in all possible scenarios. Some typical examples of application circuits using the RESET_N input pin are described in the section 1.6.3. 1.6.1.4 Real Time Clock (RTC) alarm When the module is in power-off mode (i.e. switched off with VCC maintained), it can be switched on by means of an RTC alarm previously programmed (see the u-blox AT Commands Manual [2], AT+CALA command) alternatively to the PWR_ON and RESET_N pins: the RTC system will initiate the power-on sequence. 1.6.1.5 Additional considerations The module is switched on when the VCC voltage rises up to the normal operating range (i.e. applying supply properly, as described in section 1.6.1.1): the module is commonly switched on in this way for the first time. Then, the module must be properly switched off as described in section 1.6.2, e.g. by AT+CPWROFF command. When the module is in power-off mode, i.e. it has been properly switched off as described in the section 1.6.2 (e.g. by the AT+CPWROFF command) and a voltage within the operating range is maintained at the VCC pins, the module can be switched on by a proper start-up event (i.e. by PWR_ON as described in Figure 18 and section 1.6.1.2, or by RESET_N as described in section 1.6.1.3, or by RTC alarm as described in section 1.6.1.4).](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-38.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 39 of 175 Figure 18 shows the modules power-on sequence from the power-off mode, describing the following phases: The external supply is still applied to the VCC inputs as it is assumed that the module has been previously switched off by means of the AT+CPWROFF command: the V_BCKP output is internally enabled as proper VCC is present, the RESET_N of LISA-U2 series is set to high logic level due to internal pull-up to V_BCKP, the PWR_ON is set to high logic level due to external pull-up connected to V_BCKP or VCC. The PWR_ON input pin is set low for a valid time period, representing the start-up event. All the generic digital pins of the modules are tri-stated until the switch-on of their supply source (V_INT): any external signal connected to the generic digital pins must be tri-stated or set low at least until the activation of the V_INT supply output to avoid latch-up of circuits and allow a proper boot of the module. The V_INT generic digital interfaces supply output is enabled by the integrated power management unit. The internal reset signal is held low by the integrated power management unit: the baseband processor core and all the digital pins of the modules are held in reset state, which is reported for each pin of the module in the pin description table of LISA-U2 series Data Sheet [1]. When the internal reset signal is released by the integrated power management unit, the processor core starts to configure the digital pins of the modules to each default operational state. The duration of these pins’ configuration phase differs within generic digital interfaces (3 s typical) and USB interface due to specific host / device enumeration timings (5 s typical, see the section 1.9.3.1). The host application processor should not send any AT command over the AT interfaces (USB, UART) of the modules until the end of these interfaces’ configuration phase to allow a proper boot of the module. After the interfaces’ configuration phase, the application can start sending AT commands, and the following starting procedure is suggested to check the effective completion of the module internal boot sequence: send AT and wait for the response with a 30 s timeout, iterate it 4 times without resetting or removing the VCC supply of the module, and then run the application. VCCV_BCKPPWR_ONV_INTInternal ResetSystem StateBB Pads StateInternal Reset → Operational OperationalTristate / Floating Internal ResetOFFONStart-up event0 ms~35 ms~3 sPWR_ON can be set highStart of interface configurationGeneric digital interfaces are configured Figure 18: LISA-U2 series power-on sequence description The Internal Reset signal is not available on a module pin, but the application can monitor the V_INT pin to sense the start of the power-on sequence. Any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and let a proper boot of the module. If the external signals connected to the cellular module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power on sequence.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-39.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 40 of 175 1.6.2 Module power-off The power-off sequence of LISA-U2 series modules can be correctly started, so that the current parameter settings are saved in the module’s non-volatile memory and a proper network detach is performed, in one of these ways: AT+CPWROFF command (more details in u-blox AT Commands Manual [2]) Low pulse on the PWR_ON pin for at least 1 s An over-temperature or an under-temperature shutdown occurs when the temperature measured within the cellular module reaches the dangerous area, if the optional Smart Temperature Supervisor feature is enabled and configured by the dedicated AT command. For more details see the section 3.15 and to the u-blox AT Commands Manual [2], +USTS AT command. An abrupt under-voltage shutdown occurs on LISA-U2 modules when the VCC supply is removed, but in this case the current parameter settings are not saved in the module’s non-volatile memory and a proper network detach cannot be performed. It is highly recommended to avoid an abrupt removal of the VCC supply: the power off sequence of the module must be properly started as described above (e.g. by means of the AT+CPWROFF command), and a proper VCC supply must be maintained at least until the end of the power off sequence, which occurs when the generic digital interfaces supply output (V_INT) is switched off by the module. An abrupt hardware shutdown occurs on LISA-U2 series modules when a low level is applied to the RESET_N pin. In this case, the current parameter settings are not saved in the module’s non-volatile memory and a proper network detach is not performed. It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low level on the RESET_N input pin during module normal operation: the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not reply to a specific AT command after a time period longer than the one defined in the u-blox AT Commands Manual [2].](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-40.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 42 of 175 1.6.3 Module reset LISA-U2 series modules can be properly reset (rebooted) by: AT+CFUN command (see the u-blox AT Commands Manual [2] for more details). This command causes an “internal” or “software” reset of the module, causing an asynchronous reset of the module baseband processor, excluding the integrated Power Management Unit and the RTC internal block. The V_INT interfaces supply is enabled and each digital pin is set in its internal reset state (reported in the pin description table in LISA-U2 series Data Sheet [1]), the V_BCKP supply and the RTC block are enabled. Forcing an “internal” or “software” reset, the current parameter settings are saved in the module’s non-volatile memory and a proper network detach is performed: this is the proper way to reset the modules. An abrupt hardware reset occurs on LISA-U2 series modules when a low level is applied on the RESET_N input pin for a specific time period. In this case, the current parameter settings are not saved in the module’s non-volatile memory and a proper network detach is not performed. It is highly recommended to avoid an abrupt “external” or “hardware” reset of the module by forcing a low level on the RESET_N input pin during the module normal operation: the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not provide a reply to a specific AT command after a time period longer than the one defined in the u-blox AT Commands Manual [2]. When a low level is applied to the RESET_N input, it causes an “external” or “hardware” reset of the module, with an asynchronous abrupt reset of the entire module, including the integrated Power Management Unit, except for the RTC internal block. The V_INT interfaces supply is switched off and all the digital pins of the modules are tri-stated, but the V_BCKP supply and the RTC block are enabled. Forcing an “external” or “hardware” reset, the current parameter settings are not saved in the module’s non-volatile memory and a proper network detach is not performed. When RESET_N is released from the low level, the module automatically starts its power-on sequence from the reset state. The same procedure is followed for the module reset via AT command after having performed the network detach and the parameter saving in non-volatile memory. Name Description Remarks RESET_N External reset input Internal 10 k pull-up to V_BCKP Table 18: Reset pin The RESET_N pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin, close to accessible point. For more details about RESET_N circuit precautions for ESD immunity, see section 2.5.3. The electrical characteristics of RESET_N are different from the other digital I/O interfaces. The detailed electrical characteristics are described in LISA-U2 series Data Sheet [1]. RESET_N is pulled high by an integrated 10 k pull-up resistor to V_BCKP. Therefore an external pull-up is not required on the application board. Following are some typical examples of application circuits using the RESET_N input pin. The simplest way to reset the module is to use a push button that shorts the RESET_N pin to ground.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-42.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 43 of 175 If RESET_N is connected to an external device (e.g. an application processor on an application board) an open drain output can be directly connected without any external pull-up. A push-pull output can be used too: in this case make sure that the high level voltage of the push-pull circuit is below the maximum voltage operating range of the RESET_N pin (specified in the RESET_N pin characteristics table in LISA-U2 series Data Sheet [1]). To avoid unwanted reset of the module make sure to fix the proper level at the RESET_N input pin in all possible scenarios. As ESD immunity test precaution, a 47 pF bypass capacitor (e.g. Murata GRM1555C1H470JA01), a proper series chip ferrite bead noise/EMI suppression filter (e.g. Murata BLM15HD182SN1) and a 220 nF bypass capacitor (e.g. Murata GRM155R60J224KE01) must be added as close as possible to the RESET_N pin of LISA-U2 series modules to avoid a module reset caused by an electrostatic discharge applied to the application board (for more details, see section 2.5.3). LISA-U2 series2V_BCKP22 RESET_NReset push buttonESDOpen Drain OutputApplication processorLISA-U2 series2V_BCKP22 RESET_NRintRintEMI1C1EMI2C3C2C4 Figure 20: RESET_N application circuits using a push button and an open drain output of an application processor Reference Description Remarks ESD Varistor for ESD protection. CT0402S14AHSG - EPCOS C1, C3 47 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H470JA01 - Murata C2, C4 220 nF Capacitor Ceramic X5R 0402 10% 6.3 V GRM155R60J224KE01 - Murata EMI1, EMI2 Chip Ferrite Bead Noise/EMI Suppression Filter 1800 Ω at 100 MHz, 2700 Ω at 1 GHz BLM15HD182SN1 - Murata Rint 10 kΩ Resistor 0402 5% 0.1 W Internal pull-up resistor Table 19: Example of ESD protection components for the RESET_N application circuit Any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the cellular module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-43.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 44 of 175 1.7 RF connection The ANT pin, provided by all LISA-U2 modules, represents the main RF input/output used to transmit and receive the 2G and 3G RF signal: the main antenna must be connected to this pad. The ANT pin has a nominal characteristic impedance of 50 and must be connected to the antenna through a 50 transmission line to allow transmission and reception of radio frequency (RF) signals in the 2G and 3G operating bands. The ANT_DIV pin, provided by LISA-U230 modules, represents the RF input for the integrated diversity receiver implemented for both 2G and 3G cases: the antenna for the Rx diversity must be connected to this pad. The ANT_DIV pin has a nominal characteristic impedance of 50 and must be connected to the antenna for the Rx diversity through a 50 transmission line to allow reception of radio frequency (RF) signals, improving the cellular link quality and reliability on all 2G and 3G operating bands except the 2G DCS 1800. Name Module Description Remarks ANT All RF input/output for main Tx/Rx antenna Zo = 50 nominal characteristic impedance. ANT_DIV LISA-U230 RF input for Rx diversity antenna Zo = 50 nominal characteristic impedance. Table 20: Antenna pins ESD immunity rating of ANT port is 1000 V (according to IEC 61000-4-2). Higher protection level could be required if the line is externally accessible on the application board (for further details see section 2.5.3). Choose an antenna with optimal radiating characteristics for the best electrical performance and overall module functionality. An internal antenna, integrated on the application board, or an external antenna, connected to the application board through a proper 50 connector, can be used. See section 2.4 and section 2.2.1.1 for further details regarding antenna guidelines. The recommendations of the antenna producer for correct installation and deployment (PCB layout and matching circuitry) must be followed. If an external antenna is used, the PCB-to-RF-cable transition must be implemented using either a suitable 50 connector, or an RF-signal solder pad (including GND) that is optimized for 50 characteristic impedance. If antenna supervisor functionality is required, the main antenna connected to the ANT pin should have a built in DC diagnostic resistor to ground to get proper detection functionality (See section 2.4.4). Connect the Rx diversity antenna to the ANT_DIV pin of LISA-U230 modules unless the 2G and 3G Rx diversity feature is disabled by AT command (see the u-blox AT Commands Manual [2], +URXDIV command). The same pin (74) is marked RSVD (reserved) on the other modules that do not implement Rx diversity: in this case the RSVD pin can be left unconnected.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-44.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 45 of 175 1.8 (U)SIM interface High-speed SIM/ME interface is implemented as well as automatic detection of the required SIM supporting voltage. Both 1.8 V and 3 V SIM types are supported: activation and deactivation with automatic voltage switch from 1.8 V to 3 V is implemented, according to ISO-IEC 7816-3 specifications. The SIM driver supports the PPS (Protocol and Parameter Selection) procedure for baud-rate selection, according to the values determined by the SIM Card. The VSIM supply output pin provides internal short circuit protection to limit start-up current and protect the device in short circuit situations. No additional external short circuit protection is required. Name Description Remarks VSIM SIM supply 1.80 V typical or 2.90 V typical Automatically generated by the module SIM_CLK SIM clock 3.25 MHz clock frequency SIM_IO SIM data Open drain, internal 4.7 k pull-up resistor to VSIM SIM_RST SIM reset Table 21: SIM Interface pins A low capacitance (i.e. less than 10 pF) ESD protection (e.g. Infineon ESD8V0L2B-03L or AVX USB0002RP) must be placed near the SIM card holder on each line (VSIM, SIM_IO, SIM_CLK, SIM_RST). The SIM interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F): higher protection level is required if the lines are connected to an SIM card connector, since they are externally accessible on the application board. For more details about the general precautions for ESD immunity about SIM interface pins, see section 2.5.3. The following SIM services are supported: Abbreviated Dialing Numbers (ADN) Fixed Dialing Numbers (FDN) Last Dialed Numbers (LDN) Service Dialing Numbers (SDN) SIM Application Toolkit and USIM Application Toolkit (USAT) are supported. The GPIO5 pin is configured as an external interrupt to detect the SIM card mechanical / physical presence. The pin is configured as input with an internal active pull-down enabled, and it can sense SIM card presence only if properly connected to the mechanical switch of a SIM card holder as described in section 1.8.1.4 and 1.8.1.5: Low logic level at GPIO5 input pin is recognized as SIM card not present High logic level at GPIO5 input pin is recognized as SIM card present The SIM card detection function provided by GPIO5 pin is an optional feature that can be implemented / used or not according to the application requirements. An Unsolicited Result Code (URC) can be generated each time that there is a change of status (for more details see the “simind” value of the <descr> parameter of +CIND and +CMER commands in the u-blox AT Commands Manual [2]). All the LISA-U2 series modules provide the additional function “SIM card hot insertion/removal” on the GPIO5 pin, which can be enabled using the AT+UDCONF=50 command. For more details on SIM detection function see section 1.12 as well as the u-blox AT Commands Manual [2], +UGPIOC, +UDCONF=50 commands.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-45.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 50 of 175 1.8.1.5 Dual SIM card connection Two SIM cards / chips can be connected to the module’s SIM interface, as described in the circuit of Figure 24. LISA-U2 modules do not support the usage of two SIMs at the same time, but two SIMs can be populated on the application board providing a proper switch to connect only the first SIM or only the second SIM per time to the SIM interface of the modules as described in Figure 24. All LISA-U2 series modules support SIM hot insertion / removal on the GPIO5 pin: if the feature is enabled using the specific AT commands, the switch from first SIM to the second SIM can be properly done when a Low logic level is present on the GPIO5 pin (‘SIM not inserted’ = SIM interface not enabled), without the necessity of a module re-boot, so that the SIM interface will be re-enabled by the module to use the second SIM when an High logic level will be re-applied on the GPIO5 pin. (For more details see section 1.12 and to the u-blox AT Commands Manual [2], +UGPIOC, +UDCONF=50 commands.) In the application circuit represented in Figure 24, the application processor will drive the SIM switch using its own GPIO to properly select the SIM that is used by the module. Another GPIO may be used to handle the SIM hot insertion / removal function of LISA-U2 series modules, which can also be handled by other external circuits or by the cellular module GPIO according to the application requirements. The dual SIM connection circuit described in Figure 24 can be implemented for SIM chips as well, providing proper connection between SIM switch and SIM chip as described in Figure 22. If it is required to switch between more than two SIMs, a circuit similar to the one described in Figure 24 can be implemented: for example, in case of four SIM circuits, using a proper 4-pole 4-throw switch (or, alternatively, four 1-pole 4-throw switches) instead of the suggested 4-pole 2-throw switch. Follow these guidelines connecting the module to two SIM connectors: Use a proper low on resistance (i.e. few ohms) and low on capacitance (i.e. few pF) 2-throw analog switch (e.g. Fairchild FSA2567) as SIM switch to ensure high-speed data transfer according to SIM requirements. Connect the contacts C1 (VCC) and C6 (VPP) of the two UICC / SIM to the VSIM pin of the module by means of a proper 2-throw analog switch (e.g. Fairchild FSA2567). Connect the contact C7 (I/O) of the two UICC / SIM to the SIM_IO pin of the module by means of a proper 2-throw analog switch (e.g. Fairchild FSA2567). Connect the contact C3 (CLK) of the two UICC / SIM to the SIM_CLK pin of the module by means of a proper 2-throw analog switch (e.g. Fairchild FSA2567). Connect the contact C2 (RST) of the two UICC / SIM to the SIM_RST pin of the module by means of a proper 2-throw analog switch (e.g. Fairchild FSA2567). Connect the contact C5 (GND) of the two UICC / SIM to ground. Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line (VSIM), close to the related pad of the two SIM connectors, to prevent digital noise. Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line (VSIM, SIM_CLK, SIM_IO, SIM_RST), very close to each related pad of the two SIM connectors, to prevent RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM card holders. Provide a very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco Electronics PESD0402-140) on each externally accessible SIM line, close to each related pad of the two SIM connectors, according to the EMC/ESD requirements of the custom application. Limit capacitance and series resistance on each SIM signal (SIM_CLK, SIM_IO, SIM_RST) to match the requirements for the SIM interface (27.7 ns is the maximum allowed rise time on the SIM_CLK line, 1.0 µs is the maximum allowed rise time on the SIM_IO and SIM_RST lines).](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-50.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 52 of 175 1.9 Serial communication LISA-U2 modules provide the following serial communication interfaces where AT command interface and Packet-Switched / Circuit-Switched Data communication are concurrently available: One asynchronous serial interface (UART) that provides complete RS-232 functionality conforming to ITU-T V.24 Recommendation [3], with limited data rate One Inter Processor Communication (IPC) interface that includes a synchronous SPI-compatible interface, with maximum data rate of 26 Mb/s One high-speed USB 2.0 compliant interface, with maximum data rate of 480 Mb/s. The LISA-U2 modules are designed to operate as an HSPA cellular modem, which represents the data circuit-terminating equipment (DCE) as described by the ITU-T V.24 Recommendation [3]. A customer application processor connected to the module through one of the interfaces represents the data terminal equipment (DTE). All the interfaces listed above are controlled and operated with: AT commands according to 3GPP TS 27.007 [4] AT commands according to 3GPP TS 27.005 [5] AT commands according to 3GPP TS 27.010 [6] u-blox AT commands For the complete list of supported AT commands and their syntax see u-blox AT Commands Manual [2]. The module firmware can be upgraded over all the serial interfaces listed above by means of AT command (for more details see section 3.1 as well as the u-blox AT Commands Manual [2], +UFWUPD command). The module firmware can be upgraded over the following serial interfaces using the u-blox EasyFlash tool: The UART interface (only the RxD and TxD lines are needed) The USB interface (all the provided lines VUSB_DET, USB_D+ and USB_D- are needed) To directly enable PC (or similar) connection to the module for firmware upgrade using the u-blox EasyFlash tool, provide direct access on the application board to the VUSB_DET, USB_D+ and USB_D- lines of the module (or to the RxD and TxD lines). Also provide access to the PWR_ON or the RESET_N pins, or enable the DC supply connected to the VCC pin to start the module firmware upgrade (see Firmware Update Application Note [17]). The following sub-sections describe the serial interfaces configuration and provide a detailed description of each interface for the application circuits.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-52.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 53 of 175 1.9.1 Serial interfaces configuration UART, USB and SPI/IPC serial interfaces are available as AT command interface and for Packet-Switched / Circuit-Switched Data communication. The serial interfaces are configured as described in Table 26 (for information about further settings, see the u-blox AT Commands Manual [2]). Interface AT Settings Comments UART interface Enabled Multiplexing mode can be enabled by AT+CMUX command providing following channels: Channel 0: control channel Channel 1 – 5: AT commands / data connection Channel 6: GNSS tunneling Channel 7: SAP (SIM Access Profile) AT+IPR=0 One-shot autobauding enabled by default AT+ICF=0 One-shot frame format recognition enabled by default AT&K3 HW flow control enabled AT&S1 DSR line set ON in data mode and set OFF in command mode5 AT&D1 Upon an ON-to-OFF transition of DTR, the DCE enters online command mode and issues an OK result code5 AT&C1 Circuit 109 changes in accordance with the Carrier detect status; ON if the Carrier is detected, OFF otherwise USB interface Enabled 6 CDCs are available, configured as described in the following list: USB1: AT commands / data connection USB2: AT commands / data connection USB3: AT commands / data connection USB4: GPS tunneling USB5: Primary TraceLog USB6: Secondary TraceLog USB7: SAP (SIM Access Profile) AT&K3 HW flow control enabled AT&S1 DSR line set ON in data mode and set OFF in command mode5 AT&D1 Upon an ON-to-OFF transition of DTR, the DCE enters online command mode and issues an OK result code5 AT&C1 Circuit 109 changes in accordance with the Carrier detect status; ON if the Carrier is detected, OFF otherwise SPI interface Enabled Multiplexing mode can be enabled by AT+CMUX command providing following channels: Channel 0: control channel Channel 1 – 5: AT commands / data connection Channel 6: GNSS tunneling Channel 7: SAP (SIM Access Profile) AT&K3 HW flow control enabled AT&S1 DSR line set ON in data mode and set OFF in command mode5 AT&D1 Upon an ON-to-OFF transition of DTR, the DCE enters online command mode and issues an OK result code5 AT&C1 Circuit 109 changes in accordance with the Carrier detect status; ON if the Carrier is detected, OFF otherwise Table 26: Default serial interfaces configuration 5 Refer to the u-blox AT Commands Manual [2] for the definition of the interface data mode, command mode and online command mode.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-53.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 54 of 175 1.9.2 Asynchronous serial interface (UART) The UART interface is a 9-wire unbalanced asynchronous serial interface that provides AT commands interface, PSD and CSD data communication. The module firmware can be upgraded over the UART interface using the u-blox EasyFlash tool or by means of AT command (for more details see section 3.1 and Firmware update application note [17]). UART interface provides RS-232 functionality conforming to the ITU-T V.24 Recommendation (more details available in ITU Recommendation [3]), with CMOS compatible signal levels: 0 V for low data bit or ON state, and 1.8 V for high data bit or OFF state. For detailed electrical characteristics see LISA-U2 series Data Sheet [1]. The LISA-U2 modules are designed to operate as an HSPA cellular modem, which represents the data circuit-terminating equipment (DCE) as described by the ITU-T V.24 Recommendation [3]. A customer application processor connected to the module through the UART interface represents the data terminal equipment (DTE). The signal names of the LISA-U2 modules UART interface conform to the ITU-T V.24 Recommendation [3]. UART interfaces include the following lines: Name Description Remarks DSR Data set ready Module output Circuit 107 (Data set ready) in ITU-T V.24 RI Ring Indicator Module output Circuit 125 (Calling indicator) in ITU-T V.24 DCD Data carrier detect Module output Circuit 109 (Data channel received line signal detector) in ITU-T V.24 DTR Data terminal ready Module input Circuit 108/2 (Data terminal ready) in ITU-T V.24 Internal active pull-up to V_INT (1.8 V) enabled. RTS Ready to send Module hardware flow control input Circuit 105 (Request to send) in ITU-T V.24 Internal active pull-up to V_INT (1.8 V) enabled. CTS Clear to send Module hardware flow control output Circuit 106 (Ready for sending) in ITU-T V.24 TxD Transmitted data Module data input Circuit 103 (Transmitted data) in ITU-T V.24 Internal active pull-up to V_INT (1.8 V) enabled. RxD Received data Module data output Circuit 104 (Received data) in ITU-T V.24 GND Ground Table 27: UART interface signals The UART interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins, close to accessible points.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-54.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 55 of 175 1.9.2.1 UART features All flow control handshakes are supported by the UART interface and can be set by appropriate AT commands (see u-blox AT Commands Manual [2], &K, +IFC, \Q AT commands): hardware flow control (RTS/CTS), software flow control (XON/XOFF), or none flow control. Hardware flow control is enabled by default. One-shot autobauding is supported: the baud rate detection is performed once, at module start up. Then the module works at the fixed baud rate (the detected one) and the baud rate can only be changed via the appropriate AT command (+IPR, for more details see the u-blox AT Commands Manual [2]). In particular: If automatic baud rate detection is configured in the active memory profile, the baud rate is detected once at the module power-on The factory-programmed setting enables the automatic baud rate detection (<rate> value is 0) Since autobauding is implemented as “one shot” autobauding, any setting of +IPR=0 should be avoided; the only exception is if the baud rate is fixed in the stored NVRAM profile. In this case, the module starts without autobauding and the host needs to reactivate it. If the system starts in autobauding (i.e. the +IPR is 0), the first “at” sequence provided to the module detects the baud rate. For example the first command sent from the DTE at any rate can be: AT+CPIN="1234".Characters different than “AT” are ignored during the baud rate detection since the “at” or “AT” sequence triggers the hardware detection sequence. “At” or “aT” sequences are invalid: both detection characters must be lowercase or uppercase. The module generates a response for the DTE once autobauding detection is successful, the command is accepted and the command response is available. Therefore, even if the detection was previously successful, it is only possible to assume that the detection phase was successful after a response. If the DTE does not receive any response after some time, it must retry (the timeout value should be adjustable inside the DTE application). In any case, use a very simple command as the first command, for which the execution time is short and almost constant (e.g. ATE). Note that the only way to recover from a detection failure is the detection reattempt, since the AT interface is only available after a successful detection. One-shot autobauding is enabled by factory programmed setting. The only way to recover from a detection failure is the detection reattempt, since the AT interface is only available after a successful detection. The following baud rates can be configured by AT command: 1200 b/s 2400 b/s 4800 b/s 9600 b/s 19200 b/s 38400 b/s 57600 b/s 115200 b/s, default value when the one-shot autobauding is disabled 230400 b/s 460800 b/s 921600 b/s 460800 b/s and 921600 b/s baud rates cannot be automatically detected by one-shot autobauding.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-55.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 57 of 175 1.9.2.2 UART signal behavior See Table 5 for a description of operating modes and states referred to in this section. At the switch on of the module, before the initialization of the UART interface, as described in the power-on sequence reported in the Figure 18, each pin is first tri-stated and then is set to its specific internal reset state that is reported in the pin description table in LISA-U2 series Data Sheet [1]. At the end of the boot sequence, the UART interface is initialized, the module is by default in active mode and the UART interface is enabled. The configuration and the behavior of the UART signals after the boot sequence are described below. For a complete description of data and command mode, see the u-blox AT Commands Manual [2]. RxD signal behavior The module data output line (RxD) is set by default to OFF state (high level) at UART initialization. The module holds RxD in OFF state until no data is transmitted by the module. TxD signal behavior The module data input line (TxD) is set by default to OFF state (high level) at UART initialization. The TxD line is then held by the module in the OFF state if the line is not activated by the DTE: an active pull -up is enabled inside the module on the TxD input. CTS signal behavior The module hardware flow control output (CTS line) is set to the ON state (low level) at UART initialization. If the hardware flow control is enabled, as it is by default, the CTS line indicates when the UART interface is enabled (data can be sent and received). The module drives the CTS line to the ON state or to the OFF state when it is either able or not able to accept data from the DTE over the UART (see 1.9.2.3 for more details). If hardware flow control is enabled, then when the CTS line is OFF it does not necessarily mean that the module is in low power idle-mode, but only that the UART is not enabled, as the module could be forced to stay in active-mode for other activities, e.g. related to the network or related to other interfaces. When the multiplexer protocol is active, the CTS line state is mapped to FCon / FCoff MUX command for flow control issues outside the power saving configuration while the physical CTS line is still used as a power state indicator. For more details, see Mux Implementation Application Note [15]. The CTS hardware flow control setting can be configured by AT commands (for more details, see u-blox AT Commands Manual [2], AT&K, AT\Q, AT+IFC, AT+UCTS AT command). If the hardware flow control is not enabled, the CTS line after the UART initialization behaves as follows: on LISA-U2 modules "01", "x2" and "68" product versions, the CTS line is always held in the ON state on LISA-U2 modules "03" product version onward, the CTS line is by default set in the ON state, but can be configured in the OFF state by the AT+UCTS command When the power saving configuration is enabled and the hardware flow-control is not implemented in the DTE/DCE connection, data sent by the DTE can be lost: the first character sent when the module is in the low power idle-mode will not be a valid communication character (see 1.9.2.3 for more details).](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-57.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 58 of 175 RTS signal behavior The hardware flow control input (RTS line) is set by default to the OFF state (high level) at UART initialization. The RTS line is then held by the module in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the RTS input. If the HW flow control is enabled (for more details see the u-blox AT Commands Manual [2] AT&K, AT\Q, AT+IFC command description) the RTS line is monitored by the module to detect permission from the DTE to send data to the DTE itself. If the RTS line is set to OFF state, any on-going data transmission from the module is immediately interrupted or any subsequent transmission forbidden until the RTS line changes to ON state. The DTE must be able to still accept a certain number of characters after the RTS line has been set to OFF state: the module guarantees the transmission interruption within 2 characters from RTS state change. If AT+UPSV=2 is set and HW flow control is disabled, the RTS line is monitored by the module to manage the power saving configuration: When an OFF-to-ON transition occurs on the RTS input line, the UART is enabled and the module is forced to active-mode: after 20 ms from the transition the switch is completed and data can be received without loss. The module cannot enter idle-mode and the UART is keep enabled as long as the RTS input line is held in the ON state If RTS is set to OFF state by the DTE, the UART is immediately disabled (held in low power mode) and the module automatically enters idle-mode whenever possible For more details on the power saving configuration controlled by the RTS input line see section 1.9.2.3 and u-blox AT Commands Manual [2], AT+UPSV command. DSR signal behavior If AT&S0 is set, the DSR module output line is set by default to ON state (low level) at UART initialization and is then always held in the ON state. If AT&S1 is set, the DSR module output line is set by default to OFF state (high level) at UART initialization. The DSR line is then set to the OFF state when the module is in command mode or in online command mode and is set to the ON state when the module is in data mode (see the u-blox AT Commands Manual [2] for the definition of the interface data mode, command mode and online command mode). The above behavior is valid for both Packet-Switched and Circuit-Switched Data transfer. DTR signal behavior The DTR module input line is set by default to OFF state (high level) at UART initialization. The DTR line is then held by the module in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the DTR input. Module behavior according to DTR status depends on the AT command configuration (see u-blox AT Commands Manual [2], &D AT command). Except for “01” product version, if AT+UPSV=3 is set, the DTR line is monitored by the module to manage the power saving configuration: When an OFF-to-ON transition occurs on the DTR input line, the UART is enabled and the module is forced to active-mode: after 20 ms from the transition the switch is completed and data can be received without loss. The module cannot enter idle-mode and the UART is keep enabled as long as the DTR input line is held in the ON state If DTR is set to OFF state by the DTE, the UART is immediately disabled (held in low power mode) and the module automatically enters idle-mode whenever possible For more details on the power saving configuration controlled by the DTR input line see section 1.9.2.3 and u-blox AT Commands Manual [2], AT+UPSV command.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-58.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 59 of 175 DCD signal behavior If AT&C0 is set, the DCD module output line is set by default to ON state (low level) at UART initialization and is then always held in the ON state. If AT&C1 is set, the DCD module output line is set by default to OFF state (high level) at UART initialization. The DCD line is then set by the module in accordance with the carrier detect status: ON if the carrier is detected, OFF otherwise. In case of voice call DCD is set to ON state when the call is established. For a data call there are the following scenarios (see the u-blox AT Commands Manual [2] for the definition of the interface data mode, command mode and online command mode): PSD data call: Before activating the PPP protocol (data mode) a dial-up application must provide the ATD*99***<context_number># to the module: with this command the module switches from command mode to data mode and can accept PPP packets. The module sets the DCD line to the ON state, then answers with a CONNECT to confirm the ATD*99 command. The DCD ON is not related to the context activation but with the data mode CSD data call: To establish a data call the DTE can send the ATD<number> command to the module which sets an outgoing data call to a remote modem (or another data module). Data can be transparent (non reliable) or non transparent (with the reliable RLP protocol). When the remote DCE accepts the data call, the module DCD line is set to ON and the CONNECT <communication baudrate> string is returned by the module. At this stage the DTE can send characters through the serial line to the data module which sends them through the network to the remote DCE attached to a remote DTE In case of a voice call DCD is set to ON state on all the serial communication interfaces supporting the AT command interface. (including MUX virtual channels, if active). DCD is set to ON during the execution of a command requiring input data from the DTE (all the commands where a prompt is issued; see AT commands +CMGS, +CMGW, +USOWR, +USODL, +UDWNFILE in u-blox AT Commands Manual [2]). The DCD line is set to ON state as soon as the switch to binary/text input mode is completed and the prompt is issued; DCD line is set to OFF as soon as the input mode is interrupted or completed. DCD line is kept to ON state even during the online command mode to indicate that the data call is still established even if suspended, while if the module enters command mode DSR line is set to OFF state. For more details see the DSR signal behavior description. In case of scenarios for which the DCD line setting is requested for different reasons (e.g. SMS texting during online command mode), the DCD line changes to guarantee the correct behavior for all the scenarios. For instance, in case of SMS texting in online command mode, if the data call is released, the DCD line will be kept to ON till the SMS command execution is completed (even if the data call release would request the DCD setting to OFF).](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-59.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 60 of 175 RI signal behavior The RI module output line is set by default to the OFF state (high level) at UART initialization. Then, during an incoming call, the RI line is switched from OFF state to ON state with a 4:1 duty cycle and a 5 s period (ON for 1 s, OFF for 4 s, see Figure 26), until the DTE attached to the module sends the ATA string and the module accepts the incoming data call. The RING string sent by the module (DCE) to the serial port at constant time intervals is not correlated with the switch of the RI line to the ON state. Figure 26: RI behavior during an incoming call The RI line can notify an SMS arrival. When the SMS arrives, the RI line switches from OFF to ON for 1 s (see Figure 27), if the feature is enabled by the proper AT command (see the u-blox AT Commands Manual [2], AT+CNMI command). Figure 27: RI behavior at SMS arrival This behavior allows the DTE to stay in power saving mode until the DCE related event requests service. In case of SMS arrival, if several events occur coincidently or in quick succession each event triggers the RI line independently, although the line will not be deactivated between each event. As a result, the RI line may stay to ON for more than 1 s. If an incoming call is answered within less than 1 s (with ATA or if autoanswering is set to ATS0=1) than the RI line will be set to OFF earlier. As a result: RI line monitoring cannot be used by the DTE to determine the number of received SMSes. In case of multiple events (incoming call plus SMS received), the RI line cannot be used to discriminate the two events, but the DTE must rely on the subsequent URCs and interrogate the DCE with the proper commands. The RI line can additionally notify all the URCs and all the incoming data (PPP, Direct Link, sockets, FTP) on all LISA-U2 series modules except for “01” product version, if the feature is enabled by the proper AT command (see the u-blox AT Commands Manual [2], AT+URING command): the RI line is asserted when one of the configured events occur and it remains asserted for 1 s unless another configured event will happen, with the same behavior described in Figure 27. SMS arrives time [s] 0 RI ON RI OFF 1s SMS time [s] 0 RI ON RI OFF 1s 1stime [s]151050RI ONRI OFFCall incomes1stime [s]151050RI ONRI OFFCall incomes](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-60.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 61 of 175 1.9.2.3 UART and power-saving The power saving configuration is controlled by the AT+UPSV command (for the complete description see the u-blox AT Commands Manual [2]). When power saving is enabled, the module automatically enters low power idle-mode whenever possible; otherwise the active-mode is maintained by the module (see section 1.4 for the definition and description of module operating modes). The AT+UPSV command configures both the module power saving and also the UART behavior in relation to the power saving. The conditions for the module entering idle-mode also depend on the UART power saving configuration. The AT+UPSV command can set these different power saving configurations: AT+UPSV=0, power saving disabled: module forced on active-mode and UART interface enabled (default) AT+UPSV=1, power saving enabled: module cyclic active / idle-mode and UART enabled / disabled AT+UPSV=2, power saving enabled and controlled by the UART RTS input line AT+UPSV=3, power saving enabled and controlled by the UART DTR input line The AT+UPSV=3 power saving configuration is not supported by “01” product version The different power saving configurations that can be set by the +UPSV AT command are described in details in the following subsections. UART interface communication process in the different power saving configurations, in relation with HW flow control settings and RTS input line status, is summarized in Table 28. For more details on the +UPSV AT command description, see the u-blox AT commands Manual [2]. AT+UPSV HW flow control RTS line DTR line Communication during idle-mode and wake up 0 Enabled (AT&K3) ON ON or OFF Data sent by the DTE is correctly received by the module. Data sent by the module is correctly received by the DTE. 0 Enabled (AT&K3) OFF ON or OFF Data sent by the DTE should be buffered by the DTE and will be correctly received by the module when RTS is set to ON. Data sent by the module is buffered by the module and will be correctly received by the DTE when it is ready to receive data (i.e. RTS line will be ON). 0 Disabled (AT&K0) ON or OFF ON or OFF Data sent by the DTE is correctly received by the module. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise the data is lost. 1 Enabled (AT&K3) ON ON or OFF Data sent by the DTE should be buffered by the DTE and will be correctly received by the module when active-mode is entered. Data sent by the module is correctly received by the DTE. 1 Enabled (AT&K3) OFF ON or OFF Data sent by the DTE is buffered by the DTE and will be correctly received by the module when active-mode is entered. Data sent by the module is buffered by the module and will be correctly received by the DTE when it is ready to receive data (i.e. RTS line will be ON). 1 Disabled (AT&K0) ON or OFF ON or OFF The first character sent by the DTE is lost, but after ~20 ms the UART and the module are waked up: recognition of subsequent characters is guaranteed after the complete UART / module wake-up. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise data is lost.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-61.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 63 of 175 The time period between two paging receptions is defined by the current base station (i.e. by the network): If the module is registered with a 2G network, the paging reception period can vary from ~0.47 s (DRX = 2, i.e. 2 x 51 2G-frames) up to ~2.12 s (DRX = 9, i.e. 9 x 51 2G-frames) If the module is registered with a 3G network, the paging reception period can vary from 0.64 s (DRX = 6, i.e. 26 3G-frames) up to 5.12 s (DRX = 9, i.e. 29 3G-frames) The time period of the UART enable/disable cycle is configured differently when the module is registered with a 2G network compared to when the module is registered with a 3G network: 2G: the UART is enabled concurrently to a paging reception, and then, as data has not been received or sent, the UART is disabled until the first paging reception that occurs after a timeout of 2.0 s, and therefore the interface is enabled again 3G: the UART is asynchronously enabled to paging receptions, as the UART is enabled for ~20 ms, and then, if data are not received or sent, the UART is disabled for 2.5 s, and afterwards the interface is enabled again Not registered: when a module is not registered with a network, the UART is enabled for ~20 ms, and then, if data has not been received or sent, the UART is disabled for 2.5 s and afterwards the interface is enabled again The module active-mode duration outside an active call depends on: Network parameters, related to the time interval for the paging block reception (minimum of ~11 ms) Duration of UART enable time in absence of data reception (~20 ms) The time period from the last data received at the serial port during the active-mode: the module does not enter idle-mode until a timeout expires. The second parameter of the +UPSV AT command configures this timeout, from 40 2G-frames (i.e. 40 x 4.615 ms = 184 ms) up to 65000 2G-frames (i.e. 65000 x 4.615 ms = 300 s). Default value is 2000 2G-frames (i.e. 2000 x 4.615 ms = 9.2 s) The active-mode duration can be extended indefinitely since every subsequent character received during the active-mode, resets and restarts the timer. The timeout is ignored immediately after AT+UPSV=1 has been sent, so that the UART interface is disabled and the module may enter idle-mode immediately after the AT+UPSV=1 is sent The hardware flow-control output (CTS line) indicates when the UART interface is enabled (data can be sent and received over the UART), if HW flow control is enabled, as illustrated in Figure 28. time [s]CTS ONCTS OFFUART disabled~10 ms (min)UART enabled~9.2 s (default)UART enabledData input0.47- 2.10 s Figure 28: CTS behavior with power saving enabled (AT+UPSV=1) and HW flow control enabled: the CTS output line indicates when the UART interface of the module is enabled (CTS = ON = low level) or disabled (CTS = OFF = high level)](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-63.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 64 of 175 AT+UPSV=2: power saving enabled and controlled by the RTS line This configuration can only be enabled with the module hardware flow control disabled by AT&K0 command. The UART interface is immediately disabled after the DTE sets the RTS line to OFF. Then, the module automatically enters idle-mode whenever possible according to any required activity related to the network or any other required activity related to the functions / interfaces of the module. The UART is disabled as long as the RTS line is held to OFF, but the UART is enabled in case the module needs to transmit some data over the UART (e.g. URC). When an OFF-to-ON transition occurs on the RTS input line, the UART is re-enabled and the module, if it was in idle-mode, switches from idle to active-mode after ~20 ms: this is the UART and module “wake up time”. If the RTS line is set to ON by the DTE the module is not allowed to enter the low power idle-mode and the UART is kept enabled. AT+UPSV=3: power saving enabled and controlled by the DTR line The AT+UPSV=3 configuration can be enabled regardless the flow control setting on UART. In particular, the HW flow control can be enabled (AT&K3) or disabled (AT&K0) on UART during this configuration. The UART interface is immediately disabled after the DTE sets the DTR line to OFF. Then, the module automatically enters idle-mode whenever possible according to any required activity related to the network or any other required activity related to the functions / interfaces of the module. The UART is disabled as long as the DTR line is set to OFF, but the UART is enabled in case the module needs to transmit some data over the UART (e.g. URC). When an OFF-to-ON transition occurs on the DTR input line, the UART is re-enabled and the module, if it was in idle-mode, switches from idle to active mode after 20 ms: this is the UART and module “wake up time”. If the DTR line is set to ON by the DTE, the module is not allowed to enter idle-mode and the UART is kept enabled until the DTR line is set to OFF. When the AT+UPSV=3 configuration is enabled, the DTR input line can still be used by the DTE to control the module behavior according to AT&D command configuration (see u-blox AT Commands Manual [2]). The CTS output line indicates the UART power saving state as illustrated in Figure 28, if HW flow control is enabled with AT+UPSV=3. The AT+UPSV=3 power saving configuration is not supported by “01” product version. Wake up via data reception The UART wake up via data reception consists of a special configuration of the module TXD input line that causes the system wake-up when a low-to-high transition occurs on the TXD input line. In particular, the UART is enabled and the module switches from the low power idle-mode to active-mode within ~20 ms from the first character received: this is the system “wake up time”. As a consequence, the first character sent by the DTE when the UART is disabled (i.e. the wake up character) is not a valid communication character even if the wake up via data reception configuration is active, because it cannot be recognized, and the recognition of the subsequent characters is guaranteed only after the complete system wake-up (i.e. after ~20 ms). The UART wake up via data reception configuration is active in the following case: the TXD input line is configured to wake up the system via data reception only if AT+UPSV=1 is set with hardware flow control disabled](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-64.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 66 of 175 Figure 30 shows the case where in addition to the wake-up character further (valid) characters are sent. The wake up character wakes-up the module UART. The other characters must be sent after the “wake up time” of ~20 ms. If this condition is satisfied, the module (DCE) recognizes characters. The module will disable the UART after 2000 GSM frames from the latest data reception. The “wake-up via data reception” feature cannot be disabled. In command mode6, if autobauding is enabled and the DTE does not implement HW flow control, the DTE must always send a character to the module before the “AT” prefix set at the beginning of each command line: the first character is ignored if the module is in active-mode, or it represents the wake-up character if the module is in idle-mode. In command mode6, if autobauding is disabled, the DTE must always send a dummy “AT” before each command line: the first character is not ignored if the module is in active-mode (i.e. the module replies “OK”), or it represents the wake up character if the module is in low power idle-mode (i.e. the module does not reply). No wake-up character or dummy “AT” is required from the DTE during a voice or data call since the module UART interface continues to be enabled and does not need to be woken-up. Furthermore in data mode6 a dummy “AT” would affect the data communication. Additional considerations The LISA-U2 series modules are forced to stay in active-mode if the USB is connected and not suspended, and therefore the AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 settings are overruled but they have effect on the UART behavior: they configure UART interface power saving, so that UART is enabled / disabled according to the AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 settings. To set the AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 configuration over the USB interface of LISA-U2 modules, the autobauding must be previously disabled on the UART by the +IPR AT command over the used AT interface (the USB), and this +IPR AT command configuration must be saved in the module’ non-volatile memory (see u-blox AT Commands Manual [2]). Then, after the subsequent module re-boot, AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 can be issued over the used AT interface (the USB): all the AT profiles are updated accordingly. 6 Refer to the u-blox AT Commands Manual [2] for the definition of the interface data mode, command mode and online command mode.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-66.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 67 of 175 1.9.2.4 UART application circuits Providing the full RS-232 functionality (using the complete V.24 link) If RS-232 compatible signal levels are needed, to provide full RS-232 (9 lines) functionality two different external voltage translators (e.g. Maxim MAX3237E and Texas Instruments SN74AVC4T774) can be used. The Texas Instruments chips provide the translation from 1.8 V to 3.3 V, while the Maxim chip provides the translation from 3.3 V to RS-232 compatible signal level. If a 1.8V application processor is used, for complete RS-232 functionality conforming to ITU Recommendation [3] in DTE/DCE serial communication, the complete UART interface of the module (DCE) must be connected to a 1.8V DTE as described in Figure 31. TxDApplication processor(1.8V DTE)RxDRTSCTSDTRDSRRIDCDGNDLISA-U2 series (1.8V DCE)15 TXD12 DTR16 RXD13 RTS14 CTS9DSR10 RI11 DCDGND0 Ω0 ΩTPTP0 Ω0 ΩTPTP Figure 31: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (1.8V DTE) If a 3.0 V Application Processor is used, appropriate unidirectional voltage translators must be provided using the module V_INT output as 1.8 V supply, as described in Figure 32. 4V_INTTxDApplication processor(3.0V DTE)RxDRTSCTSDTRDSRRIDCDGNDLISA-U2 series (1.8V DCE)15 TXD12 DTR16 RXD13 RTS14 CTS9DSR10 RI11 DCDGND0 Ω0 ΩTPTP0 Ω0 ΩTPTP1V8B1 A1GNDU1B3A3VCCBVCCAUnidirectionalVoltage TranslatorC1 C23V0DIR3DIR2 OEDIR1VCCB2 A2B4A4DIR41V8B1 A1GNDU2B3A3VCCBVCCAUnidirectionalVoltage TranslatorC3 C43V0DIR1DIR3 OEB2 A2B4A4DIR4DIR2 Figure 32: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE) Reference Description Part Number - Manufacturer C1, C2, C3, C4 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata U1, U2 Unidirectional Voltage Translator SN74AVC4T774 - Texas Instruments Table 29: Component for UART application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE)](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-67.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 72 of 175 In this case the first character sent when the module is in idle-mode will be a wake-up character and will not be a valid communication character (see section 1.9.2.3 for the complete description). If power saving is enabled the application circuit with the TxD and RxD lines only is not recommended. During command mode the DTE must send to the module a wake-up character or a dummy “AT” before each command line (see section 1.9.2.3 for the complete description), but during data mode the wake-up character or the dummy “AT” would affect the data communication. Additional considerations If a 3.0 V Application Processor (DTE) is used, the voltage scaling from any 3.0 V output of the DTE to the apposite 1.8 V input of the module (DCE) can be implemented, as an alternative low-cost solution, by means of an appropriate voltage divider. Consider the value of the pull-up integrated at the input of the module (DCE) for the correct selection of the voltage divider resistance values and mind that any DTE signal connected to the module has to be tri-stated or set low when the module is in power-down mode and during the module power-on sequence (at least until the activation of the V_INT supply output of the module), to avoid latch-up of circuits and allow a proper boot of the module (see the remark below).Moreover, the voltage scaling from any 1.8 V output of the cellular module (DCE) to the apposite 3.0 V input of the Application Processor (DTE) can be implemented by means of an appropriate low-cost non-inverting buffer with open drain output. The non-inverting buffer should be supplied by the V_INT supply output of the cellular module. Consider the value of the pull-up integrated at each input of the DTE (if any) and the baud rate required by the application for the appropriate selection of the resistance value for the external pull-up biased by the application processor supply rail. If the module USB interface is connected to the application processor, it is highly recommended to provide direct access to RxD, TxD, CTS and RTS lines of the module for execution of firmware upgrade over UART using the u-blox EasyFlash tool and for debug purpose: testpoints can be added on the lines to accommodate the access and a 0 Ω series resistor must be mounted on each line to detach the module pin from any other connected device. Otherwise, if the USB interface is not connected to the application processor, it is highly recommended to provide direct access to VUSB_DET, USB_D+, USB_D- lines for execution of firmware upgrade over USB and for debug purpose. In both cases, provide as well access to RESET_N pin, or to the PWR_ON pin, or enable the DC supply connected to the VCC pin to start the module firmware upgrade (see Firmware Update Application Note [17]). If the UART interface is not used, all the UART interface pins can be left unconnected, but it is highly recommended to provide direct access to the RxD, TxD, CTS and RTS lines for execution of firmware upgrade using the u-blox EasyFlash tool and for debug purpose. Any external signal connected to the UART interface must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the cellular module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-72.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 73 of 175 1.9.3 USB interface LISA-U2 modules provide a high-speed USB interface at 480 Mb/s compliant with the Universal Serial Bus Revision 2.0 specification [7]. It acts as a USB device and can be connected to any USB host such as a PC or other Application Processor. The USB-device shall look for all upper-SW-layers like any other serial device. This means that LISA-U2 modules emulate all serial control logical lines. Name Description Remarks VUSB_DET USB detect input Apply 5 V typical to enable USB USB_D+ USB Data Line D+ 90 Ω nominal differential characteristic impedance (Z0) 30 Ω nominal common mode characteristic impedance (ZCM) Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [7] are part of the USB pad driver and need not be provided externally. USB_D- USB Data Line D- 90 Ω nominal differential characteristic impedance (Z0) 30 Ω nominal common mode characteristic impedance (ZCM) Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [7] are part of the USB pad driver and need not be provided externally. Table 33: USB pins The USB interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting a very low capacitance (i.e. less or equal to 1 pF) ESD protection (e.g. Tyco Electronics PESD0402-140 ESD protection device) on the lines connected to these pins, close to accessible points. 1.9.3.1 USB features LISA-U2 modules include a High-Speed USB 2.0 compliant interface with maximum data rate of 480 Mb/s between the module and a host processor. The module itself acts as a USB device and can be connected to any USB host such as a Personal Computer or an embedded application microprocessor for AT commands, data communication, FW upgrade by means of the FOAT feature, FW upgrade by means of the u-blox EasyFlash tool and for diagnostic purpose. The USB_D+/USB_D- lines carry the USB serial bus data and signaling, while the VUSB_DET input pin senses the VBUS USB supply presence (nominally +5 V at the source) to detect the host connection and enable the interface. The USB interface of the module is enabled only if a valid voltage is detected by the VUSB_DET input (see the LISA–U2 series Data Sheet [1]). Neither the USB interface, nor the whole module is supplied by the VUSB_DET input: the VUSB_DET senses the USB supply voltage and absorbs few microamperes. LISA-U2 series modules can provide the following functions over the USB interface: CDC-ACM for AT commands and data communication CDC-ACM for GNSS tunneling CDC-ACM for diagnostic CDC-ACM for SAP (SIM Access Profile) CDC-ECM for Ethernet-over-USB CDC-ECM for Ethernet-over-USB function is not supported by "01", "x2" and "68" product versions.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-73.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 74 of 175 Each USB profile of LISA-U2 module identifies itself by its VID (Vendor ID) and PID (Product ID) combination, included in the USB device descriptor according to the USB 2.0 specifications [7]. If the USB interface is connected to the host before the module switch on, or if the module is reset with the USB interface connected to the host, the VID and PID are automatically updated runtime, after the USB detection. First, VID and PID are the following: VID = 0x058B PID = 0x0041 This VID and PID combination identifies a USB profile where no USB functions are available: AT commands must not be sent to the module over the USB profile identified by this VID and PID combination. Then, after a time period (roughly 5 s, depending on the host / device enumeration timings), the VID and PID are updated to the following ones, which are related to the LISA-U2 module default USB profile: VID = 0x1546 PID = 0x1102 The default configuration of the USB interface provides 7 USB CDC-ACM modem COM ports: USB1: AT and data USB2: AT and data USB3: AT and data USB4: GNSS tunneling USB5: Primary Log (diagnostic purpose) USB6: Secondary Log (diagnostic purpose) USB7: SAP (SIM Access Profile) The user can concurrently use the AT command interface on one CDC, and Packet-Switched / Circuit-Switched Data communication on another CDC. Figure 39 (left side) summarizes the USB end-points available with the default USB profile configuration. The USB interface of the LISA-U2 series can be configured by the AT+UUSBCONF command (for more details see the u-blox AT Commands Manual [2]) to select a different set of USB functions, available in a mutually exclusive way, and including 1 CDC-ECM for Ethernet-over-USB and 4 CDC-ACM modem COM ports enumerated as follows: USB1: AT and data USB2: GNSS tunneling USB3: Primary Log (diagnostic purpose) USB4: SAP (SIM Access Profile) The default profile of the USB interface cannot be changed on "01", "x2" and "68" product versions In the case of the USB profile with the set of functions described above, the VID and PID combination is the following: VID = 0x1546 PID = 0x1104 Figure 39 (right side) summarizes the USB end-points available with this alternative USB profile configuration.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-74.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 75 of 175 Default profile configurationInterface 0 Abstract Control ModelEndPoint Transfer: InterruptInterface 1 DataEndPoint Transfer: BulkEndPoint Transfer: BulkFunction AT and DataInterface 2 Abstract Control ModelEndPoint Transfer: InterruptInterface 3 DataEndPoint Transfer: BulkEndPoint Transfer: BulkFunction AT and DataInterface 4 Abstract Control ModelEndPoint Transfer: InterruptInterface 5 DataEndPoint Transfer: BulkEndPoint Transfer: BulkFunction AT and DataInterface 6 Abstract Control ModelEndPoint Transfer: InterruptInterface 7 DataEndPoint Transfer: BulkEndPoint Transfer: BulkFunction GNSS tunnelingInterface 8 Abstract Control ModelEndPoint Transfer: InterruptInterface 9 DataEndPoint Transfer: BulkEndPoint Transfer: BulkFunction Primary LogInterface 10 Abstract Control ModelEndPoint Transfer: InterruptInterface 11 DataEndPoint Transfer: BulkEndPoint Transfer: BulkFunction Secondary LogInterface 12 Abstract Control ModelEndPoint Transfer: InterruptInterface 13 DataEndPoint Transfer: BulkEndPoint Transfer: BulkFunction SAPAlternative profile configurationInterface 0 Abstract Control ModelEndPoint Transfer: InterruptInterface 1 DataEndPoint Transfer: BulkEndPoint Transfer: BulkFunction AT and DataInterface 2 Abstract Control ModelEndPoint Transfer: InterruptInterface 3 DataEndPoint Transfer: BulkEndPoint Transfer: BulkFunction GNSS tunnelingInterface 4 Abstract Control ModelEndPoint Transfer: InterruptInterface 5 DataEndPoint Transfer: BulkEndPoint Transfer: BulkFunction Primary LogInterface 6 Abstract Control ModelEndPoint Transfer: InterruptInterface 7 DataEndPoint Transfer: BulkEndPoint Transfer: BulkFunction SAPEthernet Networking Control ModelEndPoint Transfer: InterruptFunction EthernetInterface 8Interface 9 Data On / OffEndPoint Transfer: BulkEndPoint Transfer: Bulk Figure 39: LISA-U2 series end-points summary for the default and alternative USB profile configuration For more details on the configuration of the USB interface of LISA-U2 modules, see the u-blox AT Commands Manual [2], +UUSBCONF AT command. The module firmware can be upgraded over the USB interface using the u-blox EasyFlash tool or by means of AT command (for more details see section 3.12 and Firmware update application note [17]).](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-75.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 76 of 175 The USB drivers are available for the following operating system platforms: Windows XP Windows Vista Windows 7 Windows 8 Windows 8.1 Windows CE 5.0 Windows Embedded CE 6.0 Windows Embedded Compact 7 Windows Embedded Automotive 7 Windows Mobile 5 Windows Mobile 6 Windows Mobile 6.1 Windows Mobile 6.5 LISA-U2 modules are compatible with standard Linux/Android USB kernel drivers. 1.9.3.2 USB and power saving The modules automatically enter the USB suspended state when the device has observed no bus traffic for a specific time period according to the USB 2.0 specification [7]. In suspended state, the module maintains any USB internal status as device. In addition, the module enters the suspended state when the hub port it is attached to is disabled. This is referred to as USB selective suspend. If the USB is suspended and a power saving configuration is enabled by the AT+UPSV command, the module automatically enters the low power idle-mode whenever possible but it wakes up to active-mode according to any required activity related to the network (e.g. the periodic paging reception described in section 1.5.3.3) or any other required activity related to the functions / interfaces of the module. The USB exits suspend mode when there is bus activity. If the USB is connected and not suspended, the module is forced to stay in active-mode, therefore the AT+UPSV settings are overruled but they have effect on the power saving configuration of the other interfaces. The modules are capable of USB remote wake-up signaling: i.e. it may request the host to exit suspend mode or selective suspend by using electrical signaling to indicate remote wake-up, for example due to incoming call, URCs, data reception on a socket. The remote wake-up signaling notifies the host that it should resume from its suspended mode, if necessary, and service the external event. Remote wake-up is accomplished using electrical signaling described in the USB 2.0 specifications [7]. For the module current consumption description with power saving enabled and USB suspended, or with power saving disabled and USB not suspended, see the sections 1.5.3.3 and 1.5.3.4 and LISA-U2 series Data Sheet [1]. 1.9.3.3 USB application circuit Since the module acts as a USB device, the USB supply (5.0 V typ.) must be provided to VUSB_DET by the connected USB host. The USB interface is enabled only when a valid voltage as USB supply is detected by the VUSB_DET input. Neither the USB interface, nor the whole module is supplied by the VUSB_DET input: the VUSB_DET senses the USB supply voltage and absorbs few microamperes. The USB_D+ and USB_D- lines carry the USB serial data and signaling. The lines are used in single ended mode for relatively low speed signaling handshake, as well as in differential mode for fast signaling and data transfer. USB pull-up or pull-down resistors on pins USB_D+ and USB_D- as required by the Universal Serial Bus Revision 2.0 specification [7] are part of the USB pad driver and do not need to be externally provided.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-76.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 77 of 175 External series resistors on pins USB_D+ and USB_D- as required by the Universal Serial Bus Revision 2.0 specification [7] are also integrated: characteristic impedance of USB_D+ and USB_D- lines is specified by the USB standard. The most important parameter is the differential characteristic impedance (Z0) applicable for odd-mode electromagnetic field, which should be as close as possible to 90 differential: signal integrity may be degraded if the PCB layout is not optimal, especially when the USB signaling lines are very long. The common mode characteristic impedance (ZCM) of each USB data line should be as close as possible to 30 . LISA-U2 series VBUSD+D-GND18 VUSB_DET27 USB_D+26 USB_D-GNDC1USB DEVICE CONNECTORD1 D2 D3 Figure 40: USB Interface application circuit Reference Description Part Number - Manufacturer D1, D2, D3 Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics C2 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata Table 34: Component for USB application circuit If the USB interface is not connected to the application processor, it is highly recommended to provide direct access to the VUSB_DET, USB_D+, USB_D- lines for execution of firmware upgrade over USB using the u-blox EasyFlash tool and for debug purpose: testpoints can be added on the lines to accommodate the access. Otherwise, if the USB interface is connected to the application processor, it is highly recommended to provide direct access to the RxD, TxD, CTS and RTS lines for execution of firmware upgrade over UART and for debug purpose. In both cases, provide as well access to RESET_N pin, or to the PWR_ON pin, or enable the DC supply connected to the VCC pin to start the module firmware upgrade (see Firmware Update Application Note [17]). If the USB interface is not used, the USB_D+, USB_D- and VUSB_DET pins can be left unconnected, but it is highly recommended to provide direct access to the lines for FW upgrade and debug purpose.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-77.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 78 of 175 1.9.4 SPI interface SPI is a master-slave protocol: the module runs as an SPI slave, i.e. it accepts AT commands on its SPI interface without specific configuration. The SPI-compatible synchronous serial interface cannot be used for FW upgrade. The standard 3-wire SPI interface includes two signals to transmit and receive data (SPI_MOSI and SPI_MISO) and a clock signal (SPI_SCLK). LISA-U2 modules provide two handshake signals (SPI_MRDY and SPI_SRDY), added to the standard 3-wire SPI interface, implementing the 5-wire Inter Processor Communication (IPC) interface. The purpose of the IPC interface is to achieve high speed communication (up to 26 Mb/s) between two processors following the same IPC specifications: the module baseband processor and an external processor. High speed communication is possible only if both sides follow the same Inter Processor Communication (IPC) specifications. The module firmware can be upgraded over the SPI interface by means of AT command (for more details see section 3.1 and Firmware Update application note [17]). Name Description Remarks SPI_MISO SPI Data Line. Master Input, Slave Output Module Output. Idle high. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). MSB is shifted first. SPI_MOSI SPI Data Line. Master Output, Slave Input Module Input. Idle high. Shift data on rising clock edge (CPHA=1). Latch data on falling clock edge (CPHA=1). MSB is shifted first. Internal active pull-up to V_INT (1.8 V) enabled. SPI_SCLK SPI Serial Clock. Master Output, Slave Input Module Input. Idle low (CPOL=0). Supported clock frequency: from 260 kHz up to 26 MHz. Internal active pull-down to GND enabled. SPI_MRDY SPI Master Ready to transfer data control line. Master Output, Slave Input Module Input. Idle low. Internal active pull-down to GND enabled. SPI_SRDY SPI Slave Ready to transfer data control line. Master Input, Slave Output Module Output. Idle low. Table 35: SPI interface signals The SPI interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting a low capacitance (i.e. less than 10 pF) ESD protection (e.g. AVX USB0002 varistor array) on the lines connected to these pins, close to accessible points.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-78.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 81 of 175 4. If the data has been exchanged, the slave deactivates SPI_SRDY to process the received information. The master does not need to de-assert SPI_MRDY as it controls the SPI_SCLK 5. After the preparation, the slave activates again SPI_SRDY and wait for SPI_SCLK activation. When the clock is active, all data is transferred without intervention. If there is more data to transfer (flag set in any of the headers), the process will repeat from step 3 Slave ended transfer Figure 44: Data transfer terminated and then restarted by LISA-U2 module (slave) Starting from the state where data transfer is ongoing, the following actions will happen: 1. In case of the last transfer, the master will lower its SPI_MRDY line. After the data-transfer is finished the line must be low. If the slave has already set its SPI_SRDY line, the master must raise its line to initiate the next transfer (slave-waking-procedure) 2. If the data has been exchanged, the slave will deactivate SPI_SRDY to process the received information. This is the normal behavior 3. The slave will indicate the master that is ready to send data by activating SPI_SRDY 4. When the master is ready to send, it will signalize this by activating SPI_MRDY. This is optional, when SPI_MRDY is low before 5. The slave indicates immediately after a transfer termination that it is ready to start transmission again. In this case the slave will raise SPI_SRDY again. The SPI_MRDY line can be either high or low: the master has only to ensure that the SPI_SRDY change will be detected correctly via interrupt For more details regarding IPC communication protocol, see the SPI Application Note [18]. 1.9.4.4 IPC application circuits SPI_MOSI is the data line input for the module since it runs as SPI slave: it must be connected to the data line output (MOSI) of the application processor that runs as an SPI master. SPI_MISO is the data line output for the module since it runs as SPI slave: it must be connected to the data line input (MISO) of the application processor that runs as an SPI master. SPI_SCLK is the clock input for the module since it runs as SPI slave: it must be connected to the clock line output (SCLK) of the application processor that runs as an SPI master. SPI_MRDY is an input for the module able to detect an external interrupt which comes from the SPI master: it must be connected to a GPIO of the application processor that runs as an SPI master. SPI_SRDY is an output for the module that must be connected to a pin of the application processor that runs as an SPI master able to detect an external interrupt which comes from the module. Signal integrity of the high speed data lines may be degraded if the PCB layout is not optimal, especially when the SPI lines are very long: keep routing short and minimize parasitic capacitance to preserve signal integrity. It is recommended to match the length of SPI signals. SPI_MRDY SPI_SRDY DATA EXCHG 5 2 1 Header Data 3 4](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-81.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 83 of 175 If the SPI/IPC interface is not used, the SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_MRDY, SPI_SRDY pins can be left unconnected. Any external signal connected to the SPI / IPC interface must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the cellular module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence. 1.9.5 MUX Protocol (3GPP 27.010) LISA-U2 modules have a software layer with MUX functionality, 3GPP TS 27.010 Multiplexer Protocol [6], available either on the UART or on the SPI physical link. The USB interface does not support the multiplexer protocol. This is a data link protocol (layer 2 of OSI model) which uses HDLC-like framing and operates between the module (DCE) and the application processor (DTE) and allows a number of simultaneous sessions over the used physical link (UART or SPI): the user can concurrently use AT command interface on one MUX channel and Packet-Switched / Circuit-Switched Data communication on another MUX channel. The multiplexer protocol can be used on one serial interface (UART or SPI) at a time. Each session consists of a stream of bytes transferring various kinds of data such as SMS, CBS, PSD, GNSS, AT commands in general. This permits, for example, SMS to be transferred to the DTE when a data connection is in progress. The following virtual channels are defined: Channel 0: control channel Channel 1 – 5: AT commands / data connection Channel 6: GNSS tunneling Channel 7: SAP (SIM Access Profile) For more details see the Mux implementation Application Note [15]. If the module switch off AT command +CPWROFF is issued over a multiplexer channel, the completion of the module power off sequence could require up to 2.5 s, after the module OK reply. Therefore, if the Application Processor (AP) controls the VCC supply of the module, the AP should disable the multiplexer protocol and then issue the AT+CPWROFF command over the used AT interface, or otherwise the AP should issue the AT+CPWROFF command over a multiplexer channel and wait 2.5 s after OK reception before removing the module VCC supply.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-83.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 84 of 175 1.10 DDC (I2C) interface 1.10.1 Overview An I2C bus compatible Display Data Channel (DDC) interface for communication with u-blox GNSS receivers is available on LISA-U2 modules. The communication between a u-blox cellular module and a u-blox GNSS receiver is only provided by this DDC (I2C) interface. Name Description Remarks SCL I2C bus clock line Open drain. External pull-up required. SDA I2C bus data line Open drain. External pull-up required. Table 37: DDC pins The DDC (I2C) interface pins ESD sensitivity rating is 1 kV (HBM according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins, close to accessible points. u-blox has implemented special features in LISA-U2 series cellular modules to ease the design effort required for the integration of a u-blox cellular module with a u-blox GNSS receiver. Combining a u-blox cellular module with a u-blox GNSS receiver allows designers to have full access to the GNSS receiver directly via the cellular module: it relays control messages to the GNSS receiver via a dedicated DDC (I2C) interface. A 2nd interface connected to the GNSS receiver is not necessary: AT commands via the serial interfaces (UART, USB, SPI) of the cellular module allows a fully control of the GNSS receiver from any host processor. LISA-U2 modules feature embedded GPS aiding that is a set of specific features developed by u-blox to enhance GNSS performance, decreasing Time To First Fix (TTFF), thus allowing to calculate the position in a shorter time with higher accuracy. The DDC (I2C) interface of all LISA-U2 series modules can be used to communicate with u-blox GNSS receivers and with external I2C devices as an audio codec: the cellular module acts as an I2C master which can communicate to more I2C slaves as allowed by the I2C bus specifications [8]. See section 1.11 for an application circuit with an external audio codec. For more details regarding the handling of the DDC (I2C) interface and the GPS aiding features, see the u-blox AT Commands Manual [2] (AT+UGPS, AT+UGPRF, AT+UGPIOC, +UI2CO, +UI2CW, +UI2CR, +UI2CREGR, +UI2CC AT commands) and GNSS Implementation Application Note [16]. 1.10.2 DDC application circuits 1.10.2.1 General considerations The DDC I2C-bus master interface of LISA-U2 series modules can be used to communicate with u-blox GNSS receivers and with other external I2C-bus slaves as an audio codec: beside the general considerations reported below, see the section 1.10.2.2 for specific guidelines and application circuit examples for the connection to u-blox GNSS receivers and see the section 1.11 for an application circuit example with an external audio codec I2C-bus slave.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-84.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 85 of 175 To be compliant to the I2C bus specifications, the module bus interface pads are open drain output and pull up resistors must be mounted externally. Resistor values must conform to the I2C bus specifications [8]: for example, 4.7 k resistors can be commonly used. Pull-ups must be connected to a supply voltage of 1.8 V (typical), since this is the voltage domain of the DDC pins which are not tolerant to higher voltage values (e.g. 3.0 V). Connect the DDC (I2C) pull-ups to the V_INT 1.8 V supply source, or another 1.8 V supply source enabled after V_INT (e.g., as the GNSS 1.8 V supply present in Figure 47 application circuit), as any external signal connected to the DDC (I2C) interface must not be set high when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least until the switch on of the V_INT supply of DDC pins), to avoid latch-up of circuits and let a proper boot of the module. See Figure 18 for power-on sequence description and timings. DDC Slave-mode operation is not supported, the module can act as master only. Two lines, serial data (SDA) and serial clock (SCL), carry information on the bus. SCL is used to synchronize data transfers, and SDA is the data line. Since both lines are open drain outputs, the DDC devices can only drive them low or leave them open. The pull-up resistor pulls the line up to the supply rail if no DDC device is pulling it down to GND. If the pull-ups are missing, SCL and SDA lines are undefined and the DDC bus will not work. The signal shape is defined by the values of the pull-up resistors and the bus capacitance. Long wires on the bus will increase the capacitance. If the bus capacitance is increased, use pull-up resistors with nominal resistance value lower than 4.7 k, to match the I2C bus specifications [8] regarding rise and fall times of the signals. Capacitance and series resistance must be limited on the bus to match the I2C specifications (1.0 µs is the maximum allowed rise time on the SCL and SDA lines): route connections as short as possible. If the pins are not used as DDC bus interface, they can be left unconnected. 1.10.2.2 Connection with u-blox GNSS receivers General considerations LISA-U2 modules support these GPS aiding types: Local aiding AssistNow Online AssistNow Offline AssistNow Autonomous The embedded GPS aiding features can be used only if the DDC (I2C) interface of the cellular module is connected to the u-blox GNSS receivers. The GPIO pins of LISA-U2 series modules can handle: GNSS receiver power-on/off (“GNSS supply enable” function provided by GPIO2) The wake up from idle-mode when the GNSS receiver is ready to send data (“GNSS data ready” function provided by GPIO3) The RTC synchronization signal to the GNSS receiver (“GNSS RTC sharing” function provided by GPIO4) The GPIO2 is by default configured to provide the “GNSS supply enable” function (parameter <gpio_mode> of AT+UGPIOC command set to 3 by default), to enable or disable the supply of the u-blox GNSS receiver connected to the cellular module by the AT+UGPS command. The pin is set a Output / High, to switch on the u-blox GNSS receiver, if the parameter <mode> of AT+UGPS command is set to 1 Output / Low, to switch off the u-blox GNSS receiver, if the parameter <mode> of AT+UGPS command is set to 0 (default setting) The pin must be connected to the active-high enable pin (or the active-low shutdown pin) of the voltage regulator that supplies the u-blox GNSS receiver on the application board.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-85.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 87 of 175 or a warm start (depending on the duration of the GNSS VCC outage) and to maintain the configuration settings saved in the backup RAM. “GNSS data ready” and “GNSS RTC sharing” functions are not supported by all u-blox GNSS receivers HW or ROM/FW versions. See the GNSS Implementation Application Note [16] or to the Hardware Integration Manual of the u-blox GNSS receivers for the supported features. LISA-U2 series R1INOUTGNDGPS LDORegulatorSHDNu-blox GNSS1.8 V receiverSDA2SCL2R21V8 1V8VMAIN1V8U121 GPIO2SDASCLC1TxD1EXTINT0GPIO3GPIO446452324VCCR3V_BCKP V_BCKP2R4 Figure 47: DDC Application circuit for u-blox 1.8 V GNSS receiver Reference Description Part Number - Manufacturer R1, R2, R4 4.7 kΩ Resistor 0402 5% 0.1 W RC0402JR-074K7L - Yageo Phycomp R3 47 kΩ Resistor 0402 5% 0.1 W RC0402JR-0747KL - Yageo Phycomp U1 Voltage Regulator for GNSS receiver See GNSS receiver Hardware Integration Manual Table 38: Components for DDC application circuit for u-blox 1.8 V GNSS receiver As an alternative to using an external voltage regulator, the V_INT supply output of LISA-U2 cellular modules can be used to supply a u-blox 1.8 V GNSS receiver of the u-blox 6 generation (or later u-blox generation). The V_INT supply is able to withstand the maximum current consumption of these positioning receivers. The V_INT supply output provides low voltage ripple (up to 15 mVpp) when the module is in active-mode or in connected-mode, but it provides higher voltage ripple (up to 70 mVpp) when the module is in the low power idle-mode with power saving configuration enabled by AT+UPSV (see the u-blox AT Commands Manual [2]). According to the voltage ripple characteristic of the V_INT supply output: The power saving configuration cannot be enabled to use V_INT output to properly supply any 1.8 V GNSS receiver of the u-blox 6 generation and any 1.8 V GNSS receiver of the u-blox 7 generation or any newer u-blox GNSS receiver generation with TCXO. The power saving configuration can be enabled to use V_INT output to properly supply any 1.8 V GNSS receiver of the u-blox 7 generation or any newer u-blox GNSS receiver generation without TCXO. Additional filtering may be needed to properly supply an external LNA, depending on the characteristics of the used LNA, adding a series ferrite bead and a bypass capacitor (e.g. the Murata BLM15HD182SN1 ferrite bead and the Murata GRM1555C1H220J 22 pF capacitor) at the input of the external LNA supply line. See the GNSS Implementation Application Note [16] for additional guidelines using the V_INT supply output of LISA-U2 cellular modules to supply a u-blox 1.8 V GNSS receiver.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-87.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 89 of 175 1.11 Audio Interface All LISA-U2 series modules provide two bidirectional 4-wire I2S digital audio interfaces for connecting to remote digital audio devices: First 4-wire I2S digital audio interface (I2S_CLK, I2S_RXD, I2S_TXD and I2S_WA) Second 4-wire I2S digital audio interface (I2S1_CLK, I2S1_RXD, I2S1_TXD and I2S1_WA) Audio signal routing can be controlled by the dedicated AT command +USPM (see the u-blox AT Commands Manual [2]). This command allows setting the audio path mode, composed by the uplink audio path and the downlink audio path. Each uplink and downlink path mode defines the physical input / output, the set of parameters to process the uplink audio signal (uplink gains, uplink digital filters, echo canceller parameters) and the set of parameters to process the downlink audio signal (downlink gains, downlink digital filters and sidetone). The set of parameters to process the uplink or the downlink audio signal can be changed with dedicated AT commands for each uplink or downlink path and then stored in two profiles in the non volatile memory (see the u-blox AT Commands Manual [2] for audio parameters tuning commands). LISA-U2 series modules can act as I2S master or I2S slave. In master mode the word alignment and clock signals of the I2S digital audio interface are generated by the module. In slave mode these signal must be generated by the remote device. Table 40 lists the signals related to digital audio function. Name Description Remarks I2S_TXD I2S transmit data Module output I2S_RXD I2S receive data Module input I2S_CLK I2S clock Module output in master mode Module input in slave mode I2S_WA I2S word alignment Module output in master mode Module input in slave mode I2S1_TXD Second I2S transmit data Module output I2S1_RXD Second I2S receive data Module input I2S1_CLK Second I2S clock Module output in master mode Module input in slave mode I2S1_WA Second I2S word alignment Module output in master mode Module input in slave mode CODEC_CLK Digital clock output Digital clock output for external audio codec Configurable to 26 MHz or 13 MHz Table 40: Digital audio interface pins The I2S interfaces and CODEC_CLK pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting a general purpose ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to the I2S interfaces pins, close to accessible points, and a low capacitance (i.e. less than 10 pF) ESD protection (e.g. AVX USB0002) on the line connected to CODEC_CLK pin, close to accessible point. The I2S interface can be set to two modes, by the <I2S_mode> parameter of the AT+UI2S command: PCM mode Normal I2S mode](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-89.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 90 of 175 The I2S interface can be set to two configurations, by the <I2S_Master_Slave> parameter of AT+UI2S: Master mode Slave mode The sample rate of transmitted/received words can be set, by the <I2S_sample_rate> parameter of AT+UI2S, to: 8 kHz 11.025 kHz 12 kHz 16 kHz 22.05 kHz 24 kHz 32 kHz 44.1 kHz 48 kHz The <main_uplink> and <main_downlink> parameters of the AT+USPM command must be properly configured to select the I2S digital audio interfaces paths (for more details see the u-blox AT Commands Manual [2]): <main_uplink> has to be properly set to select: o the first I2S interface (using I2S_RXD module input) o the second I2S interface (using I2S1_RXD module input) <main_downlink> has to be properly set to select: o the first I2S interface (using I2S_TXD module output) o the second I2S interface (using I2S1_TXD module output) Parameters of digital path can be configured and saved as the normal analog paths, using appropriate path parameter as described in the u-blox AT Commands Manual [2], +USGC, +UMGC, +USTN AT command. Analog gain parameters are not used. The I2S receive data input and the I2S transmit data output signals can use the following resources: Digital filters and digital gains are available in both uplink and downlink direction. They can be properly configured by the AT commands Ringer tone and service tone are mixed on the TX path when active (downlink) The HF algorithm acts on I2S path See the u-blox AT Commands Manual [2] (AT+UI2S command) for the possible settings of I2S interface. 1.11.1 I2S interface - PCM mode Main features of the I2S interface in PCM mode: I2S runs in PCM - short alignment mode (configurable by AT commands) I2S word alignment signal can be configured to 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 kHz I2S word alignment toggles high for 1 or 2 CLK cycles of synchronization (configurable), then toggles low for 16 CLK cycles of sample width. Frame length can be 1 + 16 = 17 bits or 2 + 16 = 18 bits I2S clock frequency depends on frame length and <sample_rate>. Can be 17 x <sample_rate> or 18 x <sample_rate> I2S transmit and I2S receive data are 16 bit words long with the same sampling rate as I2S word alignment, mono. Data is in 2’s complement notation. MSB is transmitted first](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-90.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 91 of 175 When I2S word alignment toggles high, the first synchronization bit is always low. Second synchronization bit (present only in case of 2 bit long I2S word alignment configuration) is MSB of the transmitted word (MSB is transmitted twice in this case) I2S transmit data changes on I2S clock rising edge, I2S receive data changes on I2S clock falling edge 1.11.2 I2S interface - Normal I2S mode Normal I2S supports: 16 bits word Mono interface Configurable sample rate: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 kHz Main features of I2S interface in normal I2S mode: I2S word alignment signal always runs at <sample_rate> and synchronizes 2 channels (timeslots on word alignment high, word alignment low) I2S transmit data is composed of 16 bit words, dual mono (the words are written on both channels). Data are in 2’s complement notation. MSB is transmitted first. The bits are written on I2S clock rising or falling edge (configurable) I2S receive data is read as 16 bit words, mono (words are read only on the timeslot with WA high). Data is read in 2’s complement notation. MSB is read first. The bits are read on the I2S clock edge opposite to I2S transmit data writing edge (configurable) I2S clock frequency is 16 bits x 2 channels x <sample_rate> The modes are configurable through a specific AT command (see the u-blox AT Commands Manual [2], +UI2S AT command) and the following parameters can be set: MSB can be 1 bit delayed or non-delayed on I2S word alignment edge I2S transmit data can change on rising or falling edge of I2S clock signal (rising edge in this example) I2S receive data are read on the opposite front of I2S clock signal 1.11.3 I2S interface application circuits LISA-U2 I2S digital audio interfaces can be connected to an external digital audio device for voice applications. Any external digital audio device compliant to the configuration of the digital audio interface of the cellular module can be used, given that the external digital audio device has to provide: The opposite role: slave or master for LISA-U2 modules that may act as master or slave The same mode and frame format: PCM / short alignment or Normal I2S mode / long alignment mode with o data in 2’s complement notation o MSB transmitted first o word length = 16-bit o frame length = 17-bit or 18-bit in PCM / short alignment mode (16 + 1 or 16 + 2 clock cycles, with Word Aligment / Synchronization signal set high for 1 clock cycle or 2 clock cycles), or o frame length = 32-bit in Normal I2S mode / long alignment mode (16 x 2 clock cycles) The same sample rate and serial clock frequency: as the clock frequency depends on the frame length and the sample rate, the clock frequency can be o 17 x <I2S_sample_rate> or 18 x <I2S_sample_rate> in PCM / short alignment mode, or o 16 x 2 x <I2S_sample_rate> in Normal I2S mode / long alignment mode Compatible voltage levels (1.80 V typ.), otherwise it is recommended to connect the 1.8 V digital audio interface of the module to the external 3.0 V (or similar) digital audio device by means of appropriate](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-91.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 92 of 175 unidirectional voltage translators (e.g. Texas Instruments SN74AVC4T774 or SN74AVC2T245), using the module V_INT output as 1.8 V supply for the voltage translators on the module side For the appropriate selection of a compliant external digital audio device, see +UI2S AT command description in the u-blox AT Commands Manual [2] for further details regarding the capabilities and the possible settings of I2S digital audio interface of LISA-U2 series modules. Figure 49 shows an application circuit with a generic digital audio device. 43I2S_CLK41I2S_WAI2S ClockI2S Word AlignmentLISA-U2 series42I2S_TXD44I2S_RXDI2S Data InputI2S Data OutputGND GND1.8 V digital audio device Figure 49: I2S interface application circuit with a generic digital audio device As in general any external digital audio device compliant to the configuration of the digital audio interface of the cellular module can be used with LISA-U2 series modules, an appropriate specific application circuit has to be implemented and configured according to the particular external digital audio device or audio codec used and according to the application requirements. Examples of manufacturers offering compatible audio codec parts, suitable to provide basic analog audio voice capability on the application device, are the following: Maxim Integrated (as the MAX9860, MAX9867, MAX9880A audio codecs) Texas Instruments / National Semiconductor Cirrus Logic / Wolfson Microelectronics Nuvoton Technology Asahi Kasei Microdevices Realtek Semiconductor Figure 50 and Table 41 describe an application circuit for I2S digital audio interfaces of LISA-U2 series modules, providing voice capability using an external audio voice codec. DAC and ADC integrated in the external audio codec respectively converts an incoming digital data stream to analog audio output through a mono amplifier and converts the microphone input signal to the digital bit stream over the digital audio interface. An I2S digital audio interface of the LISA-U2 series modules that acts as an I2S master is connected to the digital audio interface of the external audio codec (that acts as an I2S slave). The first I2S interface can be used as well as the second I2S interface of the cellular module. The CODEC_CLK digital output clock of the cellular module is connected to the clock input of the external audio codec to provide clock reference. Signal integrity of the high speed lines may be degraded if the PCB layout is not optimal, especially when the CODEC_CLK clock line or also the I2S digital audio interface lines are very long: keep routing short and minimize parasitic capacitance to preserve signal integrity. The external audio codec is controlled by the cellular module using the DDC (I2C) interface: this interface can be used to communicate with u-blox GNSS receivers and at the same time to control an external audio codec on all LISA-U2 series modules. The V_INT supply output of the cellular module provides the supply to the external audio codec, defining a proper voltage level for the digital interfaces.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-92.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 95 of 175 UTRAN codecs: o UMTS AMR2 (UMTS Adaptive Multi Rate version 2 – Narrow Band) o UMTS AMR-WB (UMTS Adaptive Multi Rate – Wide Band) Mandatory sub-functions: o Discontinuous transmission, DTX (GSM 46.031, 46.041, 46.081 and 46.093 standards) o Voice activity detection, VAD (GSM 46.032, 46.042, 46.082 and 46.094 standards) o Background noise calculation (GSM 46.012, 46.022, 46.062 and 46.092 standards) Function configurable via specific AT commands (see the u-blox AT Commands Manual [2]) o Signal routing: +USPM command o Analog amplification, Digital amplification: +USGC, +CLVL, +CRSL, +CMUT command o Digital filtering: +UUBF, +UDBF commands o Hands-free algorithms (echo cancellation, Noise suppression, Automatic Gain control) +UHFP command o Sidetone generation (feedback of uplink speech signal to downlink path): +USTN command o Playing/mixing of alert tones: Service tones: Tone generator with 3 sinus tones +UPAR command User generated tones: Tone generator with a single sinus tone +UTGN command PCM audio files (for prompting): The storage format of PCM audio files is 8 kHz sample rate, signed 16 bits, little endian, mono](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-95.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 96 of 175 1.12 General Purpose Input/Output (GPIO) LISA-U2 series modules provide up to 14 pins (GPIO1-14) which can be configured as general purpose input or output, or can be configured to provide special functions via u-blox AT commands (for further details see the u-blox AT Commands Manual [2], +UGPIOC, +UGPIOR, +UGPIOW, +UGPS, +UGPRF, +USPM). The following functions are available in the LISA-U2 modules: GSM Tx burst indication: GPIO1 pin can be configured by AT+UGPIOC to indicate when a GSM Tx burst/slot occurs, setting the parameter <gpio_mode> of AT+UGPIOC command to 9. No GPIO pin is by default configured to provide the “GSM Tx burst indication” function. The pin configured to provide the “GSM Tx burst indication” function is set as o Output / High, since ~10 µs before the start of first Tx slot, until ~5 µs after the end of last Tx slot o Output / Low, otherwise The pin configured to provide the “GSM Tx burst indication” function can be connected on the application board to an input pin of an application processor to indicate when a GSM Tx burst/slot occurs. GNSS supply enable: The GPIO2 is by default configured by AT+UGPIOC command to enable or disable the supply of the u-blox GNSS receiver connected to the cellular module. The GPIO1, GPIO3, GPIO4 or GPIO5 pins can be configured to provide the “GNSS supply enable” function, alternatively to the default GPIO2 pin, setting the parameter <gpio_mode> of AT+UGPIOC command to 3. The “GNSS supply enable” mode can be provided only on one pin per time: it is not possible to simultaneously set the same mode on another pin. The pin configured to provide the “GNSS supply enable” function is set as o Output / High, to switch on the u-blox GNSS receiver, if the parameter <mode> of AT+UGPS command is set to 1 o Output / Low, to switch off the u-blox GNSS receiver, if the parameter <mode> of AT+UGPS command is set to 0 (default setting) The pin configured to provide the “GNSS supply enable” function must be connected to the active-high enable pin (or the active-low shutdown pin) of the voltage regulator that supplies the u-blox GNSS receiver on the application board. GNSS data ready: Only the GPIO3 pin provides the “GNSS data ready” function, to sense when a u-blox GNSS receiver connected to the cellular module is ready to send data via the DDC (I2C) interface, setting the parameter <gpio_mode> of AT+UGPIOC command to 4. The pin configured to provide the “GNSS data ready” function will be set as o Input, to sense the line status, waking up the cellular module from idle-mode when the u-blox GNSS receiver is ready to send data via the DDC (I2C) interface; this is possible if the parameter <mode> of AT+UGPS command is set to 1 and the parameter <GPS_IO_configuration> of AT+UGPRF command is set to 16 o Tri-state with an internal active pull-down enabled, otherwise (default setting) The pin that provides the “GNSS data ready” function must be connected to the data ready output of the u-blox GNSS receiver (i.e. the pin TxD1 of the u-blox GNSS receiver) on the application board.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-96.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 97 of 175 GNSS RTC sharing: Only the GPIO4 pin provides the “GNSS RTC sharing” function, to provide an RTC (Real Time Clock) synchronization signal to the u-blox GNSS receiver connected to the cellular module, setting the parameter <gpio_mode> of AT+UGPIOC command to 5. The pin configured to provide the “GNSS RTC sharing” function will be set as o Output, to provide an RTC (Real Time Clock) synchronization signal to the u-blox GNSS receiver if the parameter <mode> of AT+UGPS command is set to 1 and parameter <GPS_IO_configuration> of AT+UGPRF command is set to 32 o Output / Low, otherwise (default setting) The pin that provides the “GNSS RTC sharing” function must be connected to the RTC synchronization input of the u-blox GNSS receiver (i.e. the pin EXTINT0 of the u-blox GNSS receiver) on the application board. SIM card detection: The GPIO5 pin is by default configured by AT+UGPIOC command to detect SIM card presence. Only the GPIO5 pin can be configured to provide the “SIM card detection” function, setting the parameter <gpio_mode> of AT+UGPIOC command to 7 (default setting). The pin configured to provide the “SIM card detection” function is set as o Input with an internal active pull-down enabled, to sense SIM card presence The pin must be connected on the application board to SW2 pin of the SIM card holder, which must provide 2 pins for the mechanical card presence detection, with a 470 kΩ pull-down resistor. SW1 pin of the SIM card holder must be connected to V_INT pin of the module, by a 1 kΩ pull-up resistor. See Figure 52 and section 1.8 for the application circuit. The GPIO5 signal will be pulled low by the pull-down when a SIM card is not inserted in the holder, and will be pulled high by the pull-up when a SIM card is present. The GPIO5 pin is configured as an external interrupt to detect SIM card presence. An Unsolicited Result Code (URC) can be generated each time that there is a change of status (for more details see the “simind” value of the <descr> parameter of +CIND and +CMER commands in the u-blox AT Commands Manual [2]). All LISA-U2 series modules provide the additional function “SIM card hot insertion/removal” on the GPIO5 pin, which can be enabled using the AT+UDCONF=50 command (for more details see the u-blox AT Commands Manual [2]). Network status indication: GPIO1, GPIO2, GPIO3, GPIO4 or GPIO5 can be configured to indicate network status (i.e. no service, registered home 2G network, registered home 3G network, registered visitor 2G network, registered visitor 3G network, voice or data 2G/3G call enabled), setting the parameter <gpio_mode> of AT+UGPIOC command to 2. No GPIO pin is by default configured to provide the “Network status indication” function. The “Network status indication” mode can be provided only on one pin per time: it is not possible to simultaneously set the same mode on another pin. The pin configured to provide the “Network status indication” function is set as o Continuous Output / Low, if no service (no network coverage or not registered) o Cyclic Output / High for 100 ms, Output / Low for 2 s, if registered home 2G network o Cyclic Output / High for 50 ms, Output / Low for 50 ms, Output / High for 50 ms, Output / Low for 2 s, if registered home 3G network o Cyclic Output / High for 100 ms, Output / Low for 100 ms, Output / High for 100 ms, Output / Low for 2 s, if registered visitor 2G network (roaming) o Cyclic Output / High for 50 ms, Output / Low for 50 ms, Output / High for 50 ms, Output / Low for 100 ms, if registered visitor 3G network (roaming) o Continuous Output / High, if voice or data 2G/3G call enabled](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-97.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 98 of 175 The pin configured to provide the “Network status indication” function can be connected on the application board to an input pin of an application processor or can drive a LED by a transistor with integrated resistors to indicate network status. Module status indication: The GPIO1 and GPIO13 pins can be configured to indicate module status (power-off mode, i.e. module switched off, versus idle, active or connected mode, i.e. module switched on), properly setting the parameter <gpio_mode> of AT+UGPIOC command to 10. No GPIO pin is by default configured to provide the “Module status indication”. The pin configured to provide the “Module status indication” function is set as o Output / High, when the module is switched on (any operating mode during module normal operation: idle, active or connected mode) o Output / Low, when the module is switched off (power off mode) The “Module status indication” mode can be provided only on one pin at a time: it is not possible to simultaneously set the same mode on another pin. Module operating mode indication: The GPIO14 and GPIO5 pins can be configured to indicate module operating mode (idle-mode versus active or connected mode), properly setting the parameter <gpio_mode> of AT+UGPIOC command to 11. No GPIO pin is by default configured to provide the “Module operating mode indication”. The pin configured to provide the “Module operating mode indication” function is set as o Output / High, when the module is in active or connected mode o Output / Low, when the module is in idle-mode (that can be reached if power saving is enabled by +UPSV AT command: for further details see the u-blox AT Commands Manual [2]) The “Module operating mode indication” mode can be provided only on one pin at a time: it is not possible to simultaneously set the same mode on another pin. I2S digital audio interface: The GPIO6, GPIO7, GPIO8, GPIO9 pins are by default configured as the second I2S digital audio interface (I2S1_RXD, I2S1_TXD, I2S1_CLK, I2S1_WA respectively). Only these pins can be configured as the second I2S digital audio interface, correctly setting the parameter <gpio_mode> of AT+UGPIOC command to 12 (default setting). SPI serial interface: GPIO10, GPIO11, GPIO12, GPIO13 and GPIO14 pins are by default configured as the SPI / IPC serial interface (SPI_SCLK, SPI_MOSI, SPI_MISO, SPI_SRDY and SPI_MRDY respectively). Only these pins can be configured as the SPI / IPC serial interface, correctly setting the parameter <gpio_mode> of AT+UGPIOC command to 13 (default setting). General purpose input: All the GPIOs can be configured as input to sense high or low digital level through AT+UGPIOR command, setting the parameter <gpio_mode> of AT+UGPIOC command to 1. The “General purpose input” mode can be provided on more than one pin at a time: it is possible to simultaneously set the same mode on another pin (also on all the GPIOs). No GPIO pin is by default configured as “General purpose input”. The pin configured to provide the “General purpose input” function is set as o Input, to sense high or low digital level by AT+UGPIOR command.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-98.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 105 of 175 1.15 Approvals For all the certificates of compliancy and for the complete list of approvals (including countries’ and network operators’ approvals) of LISA-U2 series modules, see our website (http://www.u-blox.com/) or contact the u-blox office or sales representative nearest you. Product certification approval is the process of certifying that a product has passed all tests and criteria required by specifications, typically called “certification schemes” that can be divided into three distinct categories: Regulatory certification o Country specific approval required by local government in most regions and countries, as: CE (Conformité Européenne) marking for European Union FCC (Federal Communications Commission) approval for United States Industry certification o Telecom industry specific approval verifying the interoperability between devices and networks: GCF (Global Certification Forum), partnership between European device manufacturers and network operators to ensure and verify global interoperability between devices and networks PTCRB (PCS Type Certification Review Board), created by United States network operators to ensure and verify interoperability between devices and North America networks Operator certification o Operator specific approval required by some mobile network operator, as: AT&T network operator in United States Even if LISA-U2 modules are approved under all major certification schemes, the application device that integrates LISA-U2 modules must be approved under all the certification schemes required by the specific application device to be deployed in the market. The required certification scheme approvals and the related testing specifications differ depending on the country or the region where the device that integrates LISA-U2 modules must be deployed, on the corresponding vertical market of the device, on type, features and functionalities of the whole application device, and on the network operators where the device must operate. The certification of the application device that integrates a LISA-U2 module and the compliance of the application device with all the applicable certification schemes, directives and standards are the sole responsibility of the application device manufacturer. LISA-U2 modules are certified according to all capabilities and options stated in the Protocol Implementation Conformance Statement document (PICS) of the module. The PICS, according to 3GPP TS 51.010-2 [9] and 3GPP TS 34.121-2 [10], is a statement of the implemented and supported capabilities and options of a device. The PICS document of the application device integrating LISA-U2 series modules must be updated from the module PICS statement if any feature stated as supported by the module in its PICS document is not implemented or disabled in the application device. For more details regarding the AT commands settings that affect the PICS, see the u-blox AT Commands Manual [2]. Check the specific settings required for mobile network operators approvals as they may differ from the AT commands settings defined in the module as integrated in the application device.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-105.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information System description Page 106 of 175 1.15.1 R&TTED and European Conformance CE mark Products bearing the CE marking comply with the R&TTE Directive (99/5/EC), EMC Directive (89/336/EEC) and the Low Voltage Directive (73/23/EEC) issued by the Commission of the European Community. Compliance with these directives implies conformity to the following European Norms: Radio Frequency spectrum efficiency: o EN 301 511 o EN 301 908-1 o EN 301 908-2 Electromagnetic Compatibility: o EN 301 489-1 o EN 301 489-7 o EN 301 489-24 Safety o EN 60950-1: 2006 o EN 62311: 2008 Notified Body identification numbers for LISA-U2 series modules are 0682 and 1588; see the LISA-U2 series Data Sheet [1] for a complete list of the Notified Body numbers used in the certification of each module. 1.15.2 US Federal Communications Commission notice The Federal Communications Commission (FCC) IDs for the LISA-U2 modules are: LISA-U200: XPYLISAU200 LISA-U201: XPYLISAU201 LISA-U230: XPYLISAU230 LISA-U260: XPYLISAU200 LISA-U270: XPYLISAU200 1.15.2.1 Safety warnings review the structure Equipment for building-in. The requirements for fire enclosure must be evaluated in the end product The clearance and creepage current distances required by the end product must be withheld when the module is installed The cooling of the end product shall not negatively be influenced by the installation of the module Excessive sound pressure from earphones and headphones can cause hearing loss No natural rubbers, no hygroscopic materials nor materials containing asbestos are employed](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-106.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Design-In Page 113 of 175 2 Design-In 2.1 Design-in checklist This section provides a design-in checklist. 2.1.1 Schematic checklist The following are the most important points for a simple schematic check: DC supply must provide a nominal voltage at VCC pin above the minimum operating range limit. DC supply must be capable of providing 2.5 A current pulses, providing a voltage at VCC pin above the minimum operating range limit and with a maximum 400 mV voltage drop from the nominal value. VCC supply should be clean, with very low ripple/noise: provide the suggested series ferrite bead and bypass capacitors, in particular if the application device integrates an internal antenna. VCC voltage must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the module. Do not leave PWR_ON floating: add a pull-up resistor to V_BCKP. Do not apply loads which might exceed the limit for maximum available current from V_INT supply. Check that voltage level of any connected pin does not exceed the specific operating range. Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications. Insert the suggested low capacitance ESD protection and passive filtering parts on each SIM signal. Check UART signals direction, since the signal names follow the ITU-T V.24 Recommendation [3]. Provide appropriate access to USB interface and/or to UART RxD, TxD lines and access to PWR_ON and/or RESET_N lines to flash/upgrade the module firmware using the u-blox EasyFlash tool. Provide appropriate access to USB interface and/or to UART RxD, TxD, CTS, RTS lines for debugging. Capacitance and series resistance must be limited on each line of the SPI / IPC interface. Add a proper pull-up resistor to a proper supply on each DDC (I2C) interface line, if the interface is used. Capacitance and series resistance must be limited on each line of the DDC interface. Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 kΩ resistor on the board in series to the GPIO when those are used to drive LEDs. Connect the pin number 5 (RSVD) to ground. Check the digital audio interface specifications to connect a proper device. Capacitance and series resistance must be limited on CODEC_CLK line and each I2S interface line. Provide proper precautions for ESD immunity as required on the application board. Any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and let a proper boot of the module. All unused pins can be left floating on the application board except the PWR_ON pin (must be connected to V_BCKP by a pull-up resistor) and the RSVD pin number 5 (must be connected to GND).](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-113.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Design-In Page 124 of 175 2.2.2 Footprint and paste mask The following figure describes the footprint and provides recommendations for the paste mask for LISA-U2 modules. These are recommendations only and not specifications. Note that the copper and solder masks have the same size and position. 33.2 mm [1307.1 mil] 22.4 mm [881.9 mil]2.3 mm [90.6 mil]0.8 mm [31.5 mil]1.1 mm [43.3 mil]0.8 mm [31.5 mil]1.0 mm [39.3 mil]5.7 mm [224.4 mil]33.2 mm [1307.1 mil] 22.4 mm [881.9 mil]2.3 mm [90.6 mil]1.2 mm [47.2 mil]1.1 mm [43.3 mil]0.8 mm [31.5 mil]0.9 mm [35.4 mil]5.7 mm [224.4 mil]0.6 mm [23.6 mil]Stencil: 150 µm Figure 61: LISA-U2 modules suggested footprint and paste mask To improve the wetting of the half vias, reduce the amount of solder paste under the module and increase the volume outside of the module by defining the dimensions of the paste mask to form a T-shape (or equivalent) extending beyond the copper mask. The solder paste should have a total thickness of 150 µm. The paste mask outline needs to be considered when defining the minimal distance to the next component. The exact geometry, distances, stencil thicknesses and solder paste volumes must be adapted to the specific production processes (e.g. soldering etc.) of the customer. The implemetation of a step stencil (a stencil with different material thicknesses) should be considered if very different sized components must be soldered on the same application PCB: while high density chip housings with small pitch need small solder paste quantities for the avoidance of short-circuits and therefore require thin stencils, large components need more solder paste for a safe connection and thus thicker stencils. The bottom layer of LISA-U2 series modules has two unprotected copper areas for GND, shown in Figure 62. Consider “No-routing” areas for the LISA-U2 modules footprint as follows: signal keep-out area on the top layer of the application board, below LISA-U2 modules, due to GND opening on module bottom layer (see Figure 62).](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-124.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Design-In Page 125 of 175 33.2 mm5.25 mm22.4 mm5.3 mm 5.25 mm5.3 mm1.3 mm1.4 mm1.0 mmPIN 1LISA-U2 bottom side (through module view)Exposed GND on LISA-U module bottom layerSignals keep-out areas on application board Figure 62: Signals keep-out areas on the top layer of the application board, below LISA-U2 series modules 2.2.3 Placement Optimize placement for minimum length of RF line and closer path from DC source for VCC. Make sure that RF and analog circuits are clearly separated from any other digital circuits on the system board. Provide enough clearance between the module and any external part due to solder and paste masks design. Milled edges that are present at module PCB corners, away from module pins metallization, can slightly increase module dimensions from the width and the height described in the mechanical specifications sections of LISA-U2 series Data Sheet [1]: provide enough clearance between module PCB corners and any other external part mounted on the application board. The heat dissipation during continuous transmission at maximum power can significantly raise the temperature of the application base-board below the LISA-U2 modules: avoid placing temperature sensitive devices (e.g. GNSS receiver) close to the module.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-125.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Design-In Page 126 of 175 2.3 Thermal guidelines LISA-U2 module operating temperature range and module thermal resistance are specified in the LISA-U2 series Data Sheet [1]. The most critical condition concerning module thermal performance is the uplink transmission at maximum power (data upload or voice call in connected mode), when the baseband processor runs at full speed, radio circuits are all active and the RF power amplifier is driven to higher output RF power. This scenario is not often encountered in real networks; however the application should be correctly designed to cope with it. During transmission at maximum RF power the LISA-U2 modules generate thermal power that can exceed 2 W: this is an indicative value since the exact generated power strictly depends on operating condition such as the number of allocated TX slot and modulation (GMSK or 8PSK) or data rate (WCDMA), transmitting frequency band, etc. The generated thermal power must be adequately dissipated through the thermal and mechanical design of the application. The spreading of the Module-to-Ambient thermal resistance (Rth,M-A) depends on the module operating condition (e.g. 2G or 3G mode, transmit band): the overall temperature distribution is influenced by the configuration of the active components during the specific mode of operation and their different thermal resistance toward the case interface. Mounting a LISA-U2 module on a 90 mm x 70 mm x 1.46 mm 4-Layers PCB with a high coverage of copper in still air conditions7, the increase of the module temperature8 in different modes of operation, referred to idle state initial condition9, can be summarized as following: 7°C during a GSM voice call at max TX power 19°C during GPRS data transfer with 4 TX slots at max TX power 16°C during EDGE data transfer with 4 TX slots at max TX power 25°C in UMTS/HSxPA connection at max TX power The Module-to-Ambient thermal resistance value and the related increase of module temperature will be different for other mechanical deployments of the module, e.g. PCB with different dimensions and characteristics, mechanical shells enclosure, or forced air flow. The increase of thermal dissipation, i.e. the Module-to-Ambient thermal resistance reduction, will decrease the temperature for internal circuitry of LISA-U2 modules for a given operating ambient temperature. This improves the device long-term reliability for applications operating at high ambient temperature. Recommended hardware techniques to be used to improve heat dissipation in the application: Connect each GND pin with solid ground layer of the application board and connect each ground area of the multilayer application board with complete via stack down to main ground layer Provide a ground plane as wide as possible on the application board Optimize antenna return loss, to optimize overall electrical performance of the module including a decrease of module thermal power Optimize the thermal design of any high-power component included in the application, as linear regulators and amplifiers, to optimize overall temperature distribution in the application device Select the material, the thickness and the surface of the box (i.e. the mechanical enclosure of the application device that integrates the module) so that it provides good thermal dissipation 7 Refer to LISA-U2 series Data Sheet [1] for the Rth,M-A value in this application condition 8 Temperature is measured by internal sensor of wireless module 9 Steady state thermal equilibrium is assumed. The module’s temperature in idle state can be considered equal to ambient temperature](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-126.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Design-In Page 127 of 175 Further hardware techniques to be used to improve heat dissipation in the application: Force ventilation air-flow within mechanical enclosure Provide a heat sink component attached to the module top side, with electrically insulated / high thermal conductivity adhesive, or on the backside of the application board, below the cellular module, as a large part of the heat is transported through the GND pads and dissipated over the backside of the application board For example, after the installation of a robust aluminum heat-sink with forced air ventilation on the back of the same application board described above, the Module-to-Ambient thermal resistance (Rth,M-A) is reduced to 1.5 ÷ 3.5 °C/W. The effect of lower Rth,M-A can be seen from the module temperature increase, which now can be summarized as following: 1.5°C during a GSM voice call at max TX power 3°C during GPRS data transfer with 4 TX slots at max TX power 2.5°C during EDGE data transfer with 4 TX slots at max TX power 5.5°C in UMTS/HSxPA connection at max TX power Beside the reduction of the Module-to-Ambient thermal resistance implemented by the hardware design of the application device integrating a LISA-U2 module, the increase of module temperature can be moderated by the software implementation of the application. Since the most critical condition concerning module thermal power occurs when module connected mode is enabled, the actual module thermal power depends, as module current consumption, on the radio access mode (GERAN / UTRA), the operating band and the average TX power. A few software techniques may be implemented to reduce the module temperature increase in the application: Select the radio access mode which provides lower temperature increase (see the module temperature increase values summarized above) by means of AT command (see the u-blox AT Commands Manual [2], +COPS command) Select the operating band which provides lower current consumption in the selected radio access mode (see current consumption values reported in the LISA-U2 series Data Sheet [1]) by means of AT command (see the u-blox AT Commands Manual [2], +UBANDSEL command) Enable module connected mode for a given time period and then disable it for a time period enough long to properly mitigate temperature increase](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-127.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Design-In Page 128 of 175 2.4 Antenna guidelines Antenna characteristics are essential for good functionality of the module. Antenna radiating performance has direct impact on the reliability of connections over the Air Interface. A bad termination of the ANT pin (main RF input/output) and the ANT_DIV pin (RF input for diversity receiver provided by LISA-U230 modules) can result in poor performance of the module. The following parameters should be checked: Item Recommendations Impedance 50 Ω nominal characteristic impedance Frequency Range Depends on the LISA-U2 module HW version and on the Mobile Network used. LISA-U260: 824..960 MHz (GSM 850, GSM 900, UMTS B5) 1710..1990 MHz (GSM 1800, GSM 1900, UMTS B2) LISA-U270: 824..960 MHz (GSM 850, GSM 900, UMTS B8) 1710..2170 MHz (GSM 1800, GSM 1900, UMTS B1) LISA-U200, LISA-U201, LISA-U230: 824..960 MHz (GSM 850, GSM 900, UMTS B5, UMTS B6, UMTS B8) 1710..2170 MHz (GSM 1800, GSM 1900, UMTS B1, UMTS B2, UMTS B4) Input Power >2 W peak V.S.W.R <2:1 recommended, <3:1 acceptable Return Loss S11<-10 dB recommended, S11<-6 dB acceptable Table 46: General recommendation for GSM antenna The antenna gain shall remain below the levels reported in the section 1.15.2.2 to preserve the original u-blox FCC ID. Some 2G and 3G bands are overlapping. This depends on worldwide band allocation for telephony services, where different bands are deployed for different geographical regions. If LISA-U2 series modules are planned for use on the entire supported bands, then an antenna that supports the 824..960 MHz and the 1710..2170 MHz frequency range should be selected. Otherwise, for fixed applications in specific geographical region, antenna requirements can be relaxed for non-deployed frequency bands. See the operating RF frequency bands table in LISA-U2 series Data Sheet [1] for the detailed uplink and downlink frequency ranges of each supported band. LISA-U230 modules provide 2G and 3G dynamic receive diversity (Rx diversity) capability to improve the quality and reliability of the cellular link. This feature can be optionally used connecting a second antenna to the ANT_DIV pin, to receive an RF input signal that is processed by the module to increase the performance. It is recommended to properly connect the Rx diversity antenna to the ANT_DIV pin of LISA-U230 modules unless the 2G and 3G Rx diversity feature is disabled by AT command (see the u-blox AT Commands Manual [2], +URXDIV command). All the antenna guidelines and recommendations reported for the main Tx/Rx antenna design are applicable also to the Rx diversity antenna design, even if the antenna for the Rx diversity is not used to transmit.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-128.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Design-In Page 134 of 175 2.4.4 Antenna detection functionality The internal antenna detect circuit is based on ADC measurement at ANT: the RF port is DC coupled to the ADC unit in the baseband chip which injects a DC current (10 µA for 128 µs) on ANT and measures the resulting DC voltage to evaluate the resistance from ANT pad to GND. The antenna detection is forced by the +UANTR AT command: see the u-blox AT Commands Manual [2] for more details on how to access this feature. To achieve antenna detection functionality, use an RF antenna with built-in resistor from ANT signal to GND, or implement an equivalent solution with a circuit between the antenna cable connection and the radiating element as shown in Figure 67. Application Board Antenna AssemblyDiagnostic CircuitLISA-U2 seriesADCCurrent SourceRF ChokeDC BlockingFront-End RF ModuleRF ChokeDC BlockingRadiating ElementZo=50 ΩResistor for DiagnosticCoaxial Antenna CableANT Figure 67: Antenna detection circuit and antenna with diagnostic resistor Examples of components for the antenna detection diagnostic circuit are reported in the following table: Description Part Number - Manufacturer DC Blocking Capacitor Murata GRM1555C1H220JA01 or equivalent RF Choke Inductor Murata LQG15HS68NJ02, LQG15HH68NJ02 or equivalent (Self Resonance Frequency ~1GHz) Resistor for Diagnostic 15 k 5%, various Manufacturers Table 50: Example of components for the antenna detection diagnostic circuit The DC impedance at RF port for some antennas may be a DC open (e.g. linear monopole) or a DC short to reference GND (e.g. PIFA antenna). For those antennas, without the diagnostic circuit of Figure 67, the measured DC resistance will always be at the limits of the measurement range (respectively open or short), and there will be no mean to distinguish between a defect on antenna path with similar characteristics (respectively: removal of linear antenna or RF cable shorted to GND for PIFA antenna). Furthermore, any other DC signal injected to the RF connection from ANT connector to radiating element will alter the measurement and produce invalid results for antenna detection. It is recommended to use an antenna with a built-in diagnostic resistor in the range from 5 kΩ to 30 kΩ to assure good antenna detection functionality and to avoid a reduction of module RF performance. The choke inductor should exhibit a parallel Self Resonance Frequency (SRF) in the range of 1 GHz to improve the RF isolation of load resistor.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-134.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Design-In Page 135 of 175 For example: Consider a GSM antenna with built-in DC load resistor of 15 k. Using the +UANTR AT command, the module reports the resistance value evaluated from ANT connector to GND: Reported values close to the used diagnostic resistor nominal value (i.e. values from 13 kΩ to 17 kΩ if a 15 kΩ diagnostic resistor is used) indicate that the antenna is properly connected Values close to the measurement range maximum limit (approximately 50 kΩ) or an open-circuit “over range” report (see u-blox AT Commands Manual [2]) means that that the antenna is not connected or the RF cable is broken Reported values below the measurement range minimum limit (1 kΩ) will highlight a short to GND at antenna or along the RF cable Measurement inside the valid measurement range and outside the expected range may indicate an improper connection, damaged antenna or wrong value of antenna load resistor for diagnostic Reported value could differ from the real resistance value of the diagnostic resistor mounted inside the antenna assembly due to antenna cable length, antenna cable capacity and the used measurement method 2.5 ESD guidelines 2.5.1 ESD immunity test overview The immunity of devices integrating LISA-U2 modules to Electro-Static Discharge (ESD) is part of the Electro-Magnetic Compatibility (EMC) conformity which is required for products bearing the CE marking, compliant with the R&TTE Directive (99/5/EC), the EMC Directive (89/336/EEC) and the Low Voltage Directive (73/23/EEC) issued by the Commission of the European Community. Compliance with these directives implies conformity to the following European Norms for device ESD immunity: ESD testing standard CENELEC EN 61000-4-2 [11] and the radio equipment standards ETSI EN 301 489-1 [12], ETSI EN 301 489-7 [13], ETSI EN 301 489-24 [14], which requirements are summarized in Table 51. The ESD immunity test is performed at the enclosure port, defined by ETSI EN 301 489-1 [12] as the physical boundary through which the electromagnetic field radiates. If the device implements an integral antenna, the enclosure port is defined as all insulating and conductive surfaces housing the device. If the device implements a removable antenna, the antenna port can be separated from the enclosure port. The antenna port includes the antenna element and its interconnecting cable surfaces. The applicability of the ESD immunity test to the whole device depends on the device classification as defined by ETSI EN 301 489-1 [12]. Applicability of the ESD immunity test to the specific device ports or the specific interconnecting cables to auxiliary equipments, depends on device accessible interfaces and manufacturer requirements, as defined by ETSI EN 301 489-1 [12]. Contact discharges are performed at conductive surfaces, while air discharges are performed at insulating surfaces. Indirect contact discharges are performed on the measurement setup horizontal and vertical coupling planes as defined in CENELEC EN 61000-4-2 [11]. For the definition of integral antenna, removable antenna, antenna port, device classification see the ETSI EN 301 489-1 [12]. The contact and air discharges are defined in CENELEC EN 61000-4-2 [11]. Application Category Immunity Level All exposed surfaces of the radio equipment and ancillary equipment in a representative configuration Contact Discharge 4 kV Air Discharge 8 kV Table 51: Electro-Magnetic Compatibility ESD immunity requirements as defined by CENELEC EN 61000-4-2, ETSI EN 301 489-1, ETSI EN 301 489-7, ETSI EN 301 489-24](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-135.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Design-In Page 136 of 175 2.5.2 ESD immunity test of u-blox LISA-U2 series reference designs Although Electro-Magnetic Compatibility (EMC) certification is required for customized devices integrating LISA-U2 modules for R&TTED and European Conformance CE mark, EMC certification (including ESD immunity) has been successfully performed on LISA-U2 series modules reference designs according to the CENELEC EN 61000-4-2 [11], ETSI EN 301 489-1 [12], ETSI EN 301 489-7 [13] and ETSI EN 301 489-24 [14] European Norms. The EMC / ESD approved u-blox reference designs consist of a LISA-U2 series module soldered onto a motherboard which provides supply interface, SIM card, headset and communication port. An external antenna is connected to an SMA connector provided on the motherboard for the main Tx/Rx antenna. An additional external antenna is connected to an additional SMA connector provided on the motherboard for the Rx diversity antenna of LISA-U230 modules. Since an external antenna is used, the antenna port can be separated from the enclosure port. The reference design is not enclosed in a box so that the enclosure port is not indentified with physical surfaces. Therefore, some test cases cannot be applied. Only the antenna port is identified as accessible for direct ESD exposure. The u-blox LISA-U2 series reference designs implement all the ESD precautions described in section 2.5.3. u-blox LISA-U2 series reference designs ESD immunity test results are reported in the Table 52, according to test requirements stated in the CENELEC EN 61000-4-2 [11], ETSI EN 301 489-1 [12], ETSI EN 301 489-7 [13] and ETSI EN 301 489-24 [14]. Category Application Ref. Design Immunity Level Remarks Contact Discharge to coupling planes (indirect contact discharge) Enclosure All +4 kV / -4 kV Contact Discharges to conducted surfaces (direct contact discharge) Enclosure port All Not Applicable Test not applicable to u-blox reference design because it does not provide enclosure surface. The test is applicable only to equipments providing conductive enclosure surface. Main Antenna port All +4 kV / -4 kV Test applicable to u-blox reference design because it provides antenna with conductive & insulating surfaces. The test is applicable only to equipments providing antenna with conductive surface. Rx Div Antenna port LISA-U230 +4 kV / -4 kV Test applicable to u-blox reference design because it provides antenna with conductive & insulating surfaces. The test is applicable only to equipments providing antenna with conductive surface. Air Discharge at insulating surfaces Enclosure port All Not Applicable Test not applicable to the u-blox reference design because it does not provide an enclosure surface. The test is applicable only to equipments providing insulating enclosure surface. Main Antenna port All +8 kV / -8 kV Test applicable to u-blox reference design because it provides antenna with conductive & insulating surfaces. The test is applicable only to equipments providing antenna with insulating surface. Rx Div Antenna port LISA-U230 +8 kV / -8 kV Test applicable to u-blox reference design because it provides antenna with conductive & insulating surfaces. The test is applicable only to equipments providing antenna with insulating surface. Table 52: Enclosure ESD immunity level of u-blox LISA-U2 series modules reference designs](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-136.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Design-In Page 137 of 175 2.5.3 ESD application circuits The application circuits described in this section are recommended and should be implemented in any device that integrates a LISA-U2 module, according to the application board classification (see ETSI EN 301 489-1 [12]), to satisfy the requirements for ESD immunity test summarized in Table 51. Antenna interface The ANT pin of LISA-U2 modules provides ESD immunity up to 1000 V (contact and air discharge according to IEC 61000-4-2): higher protection level is required if the line is externally accessible on the device (i.e. the application board where LISA-U2 series module is mounted). The following precautions are suggested for satisfying ESD immunity test requirements using LISA-U2 series modules: If the device implements an embedded antenna, the device insulating enclosure should provide protection to direct contact discharge up to +4 kV / -4 kV and protection to air discharge up to +8 kV / -8 kV to the antenna interface If the device implements an external antenna, the antenna and its connecting cable should provide a completely insulated enclosure able to provide protection to direct contact discharge up to +4 kV / -4 kV and protection to air discharge up to +8 kV / -8 kV to the whole antenna and cable surfaces If the device implements an external antenna and the antenna and its connecting cable do not provide a completely insulated enclosure able to provide protection to direct contact discharge up to +4 kV / -4 kV and protection to air discharge up to +8 kV / -8 kV to the whole antenna and cable surfaces, an external high pass filter, consisting of a series 15 pF capacitor (Murata GRM1555C1H150JA01) and a shunt 39 nH coil (Murata LQG15HN39NJ02) should be implemented at the antenna port as described in Figure 68, as implemented in the EMC / ESD approved reference design LISA-U2 series modules Antenna detection functionality is not provided when implementing the high pass filter described in Figure 68 and Table 53 as ESD protection for the antenna port of LISA-U2 series modules. External Antenna EnclosureApplication BoardLISA-U2 seriesANTRadiating ElementZo = 50 OhmCoaxial Antenna CableAntenna PortEnclosure PortCL Figure 68: Antenna port ESD immunity protection application circuit for LISA-U2 series modules Reference Description Part Number - Manufacturer C 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H150JA01 - Murata L 39 nH Multilayer Chip Inductor L0G 0402 5% LQG15HN39NJ02 - Murata Table 53: Example of components for Antenna port ESD immunity protection application circuit for LISA-U2 series modules](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-137.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Design-In Page 138 of 175 With LISA-U230 modules, the ANT_DIV pin provides ESD immunity up to +4 kV / -4 kV for direct Contact Discharge and up to +8 kV / -8 kV for Air Discharge: no further precaution to ESD immunity test is needed, as implemented in the EMC / ESD approved reference design of LISA-U230 modules. RESET_N pin The following precautions are suggested for the RESET_N line of LISA-U2 modules, depending on the application board handling, to satisfy ESD immunity test requirements: A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470JA01) must be mounted on the line termination connected to the RESET_N pin to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure A proper series chip ferrite bead noise/EMI suppression filter (e.g. Murata BLM15HD182SN1) must be added on the line connected to the RESET_N pin to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure A 220 nF bypass capacitor (e.g. Murata GRM155R60J224KE01) must be mounted as close as possible to the RESET_N pin of LISA-U2 series modules to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure It is recommended to keep the connection line to RESET_N as short as possible Maximum ESD sensitivity rating of the RESET_N pin is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the RESET_N pin is externally accessible on the application board. The following precautions are suggested to achieve higher protection level: A general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG varistor array or EPCOS CT0402S14AHSG varistor) should be mounted on the RESET_N line, close to accessible point The RESET_N application circuit implemented in the EMC / ESD approved reference designs of LISA-U2 series moduels is described in Figure 20 and Table 19 (section 1.6.3). SIM interface The following precautions are suggested for LISA-U2 modules SIM interface (VSIM, SIM_RST, SIM_IO, SIM_CLK pins), depending on the application board handling, to satisfy ESD immunity test requirements: A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470J) must be mounted on the lines connected to VSIM, SIM_RST, SIM_IO and SIM_CLK pins to assure SIM interface functionality when an electrostatic discharge is applied to the application board enclosure It is suggested to use as short as possible connection lines at SIM pins Maximum ESD sensitivity rating of SIM interface pins is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if SIM interface pins are externally accessible on the application board. The following precautions are suggested to achieve higher protection level: A low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Infineon ESD8V0L2B-03L or AVX USB0002) should be mounted on each SIM interface line, close to accessible points (i.e. close to the SIM card holder) The SIM interface application circuit implemented in the EMC / ESD approved reference designs of LISA-U2 series modules versions is described in the section 1.8.1. Other pins and interfaces All the module pins that are externally accessible on the device integrating LISA-U2 module should be included in the ESD immunity test since they are considered to be a port as defined in ETSI EN 301 489-1 [12]. Depending on applicability, to satisfy ESD immunity test requirements according to ESD category level, all the module pins that are externally accessible should be protected up to +4 kV / -4 kV for direct Contact Discharge and up to +8 kV / -8 kV for Air Discharge applied to the enclosure surface.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-138.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Features description Page 140 of 175 3 Features description 3.1 Network indication The GPIO1, GPIO2, GPIO3, GPIO4 or GPIO5 alternatively from their default settings, can be configured to indicate network status (i.e. no service, registered home network, registered visitor network, voice or data call enabled), by means of the AT+UGPIOC command. For the detailed description, see section 1.12 and to u-blox AT Commands Manual [2], GPIO commands. 3.2 Antenna detection Antenna presence detection capability is provided, evaluating the resistance from the ANT pin to GND by means of an internal antenna detection circuit. The external antenna assembly must be provided with a built-in resistor (diagnostic circuit) to be detected. The antenna detection feature can be enabled through the +UANTR AT command. For more details regarding feature description and diagnostic circuit design-in see the section 2.4.4, and the u-blox AT Commands Manual [2]. 3.3 Jamming Detection In real network situations modules can experience various kind of out-of-coverage conditions: limited service conditions when roaming to networks not supporting the specific SIM, limited service in cells which are not suitable or barred due to operators’ choices, no cell condition when moving to poorly served or highly interfered areas. In the latter case, interference can be artificially injected in the environment by a noise generator covering a given spectrum, thus obscuring the operator’s carriers entitled to give access to the GSM/UMTS service. The Jamming Detection Feature detects such “artificial” interference and reports the start and stop of such conditions to the client, which can react appropriately by e.g. switching off the radio transceiver in order to reduce power consumption and monitoring the environment at constant periods. The feature consists of detecting, at radio resource level, an anomalous source of interference and signaling it to the client with an unsolicited indication when the detection is entered or released. The jamming condition occurs when: The module has lost synchronization with the serving cell and cannot select any other cell The band scan reveals at least n carriers with power level equal or higher than threshold On all such carriers, no synchronization is possible The number of minimum disturbing carriers and the power level threshold can be configured by the client by using the AT+UCD command [2]. The jamming condition is cleared when any of the above mentioned statements does not hold. The congestion (i.e. jamming) detection feature can be enabled and configured by the +UCD AT command (for more details see the u-blox AT Commands Manual [2]).](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-140.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Features description Page 141 of 175 3.4 TCP/IP and UDP/IP Via the AT commands it is possible to access the TCP/IP and UDP/IP functionalities over the Packet Switched data connection. For more details about AT commands see the u-blox AT Commands Manual [2]. LISA-U2 modules support the Direct Link mode for TCP and UDP sockets. Sockets can be set in Direct Link mode to establish a transparent end-to-end communication with an already connected TCP or UDP socket via serial interface. In Direct Link mode, data sent to the serial interface from an external application processor is forwarded to the network and vice-versa. To avoid data loss while using Direct Link, enable HW flow control on the serial interface. 3.4.1 Multiple PDP contexts and sockets Two PDP context types are defined: “external” PDP context: IP packets are built by the DTE, the MT’s IP instance runs the IP relay function only “internal” PDP context: the PDP context (relying on the MT’s TCP/IP stack) is configured, established and handled via the data connection management packet switched data commands described in u-blox AT commands manual [2] Multiple PDP contexts are supported. The DTE can access these PDP contexts either alternatively through the physical serial port, or simultaneously through the virtual serial ports of the multiplexer (multiplexing mode MUX), with the following constraints: Using the MT’s embedded TCP/IP stack, only 1 internal PDP context is supported. This IP instance supports up to 7 sockets Using only external PDP contexts, it is possible to have at most 3 IP instances (with 3 different IP addresses) simultaneously. If in addition the internal PDP context is used, at most 2 external PDP contexts can be activated Secondary PDP contexts (PDP contexts sharing the IP address of a primary PDP context) are also supported. Traffic Flow Filters for such secondary contexts shall be specified according to 3GPP TS 23.060 [19]. At most 2 secondary PDP contexts can be activated, since the maximum number of PDP contexts, both normal and secondary, is always 3. 3.5 FTP LISA-U2 modules support the File Transfer Protocol and Secure File Transfer Protocol functionalities via AT commands. Files are read and stored in the local file system of the module. For more details about AT commands see u-blox AT Commands Manual [2]. FTP files can also be transferred using FTP Direct Link: FTP download: the data coming from the FTP server is forwarded to the application processor via the serial interface (for FTP without Direct Link mode the data is always stored in the module’s FFS) FTP upload: the data coming from the application processor via the serial interface is forwarded to the FTP server (for FTP without Direct Link mode the data is read from the module’s FFS) When Direct Link is used for a FTP file transfer, only the file content pass through the serial interface, whereas all the FTP commands handling is managed internally by the FTP application. Due to the limited size of module FFS, FTP direct link is useful to transfer files with size greater than FFS. To avoid data loss while using direct link, enable HW flow control on the serial interface. 3.6 HTTP LISA-U2 modules support Hyper-Text Transfer Protocol (HTTP/1.0) functionalities as an HTTP client is implemented: HEAD, GET, POST, DELETE and PUT operations are available. The file size to be uploaded / downloaded depends on the free space available in the local file system (FFS) at the moment of the operation. Up to 4 HTTP client contexts can simultaneously be used.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-141.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Features description Page 142 of 175 LISA-U2 modules support also Secure Hyper-Text Transfer Protocol functionalities providing SSL encryption. For more details about AT commands see the u-blox AT Commands Manual [2]. 3.7 SSL/TLS The modules support the Secure Sockets Layer (SSL) / Transport Layer Security (TLS) with certificate key sizes up to 4096 bits to provide security over the FTP and HTTP protocols. The SSL/TLS support provides different connection security aspects: Server authentication10: use of the server certificate verification against a specific trusted certificate or a trusted certificates list Client authentication10: use of the client certificate and the corresponding private key Data security and integrity: data encryption and Hash Message Authentication Code (HMAC) generation The security aspects used during a connection depend on the SSL/TLS configuration and features supported. Table 55 contains the settings of the default SSL/TLS profile and Table 55 to Table 59 report the main SSL/TLS supported capabilities of the products. For a complete list of supported configurations and settings see the u-blox AT Commands Manual [2]. Settings Value Meaning Certificates validation level Level 0 The server certificate will not be checked or verified Minimum SSL/TLS version Any The server can use any of the TLS1.0/TLS1.1/TLS1.2 versions for the connection Cipher suite Automatic The cipher suite will be negotiated in the handshake process Trusted root certificate internal name None No certificate will be used for the server authentication Expected server host-name None No server host-name is expected Client certificate internal name None No client certificate will be used Client private key internal name None No client private key will be used Client private key password None No client private key password will be used Pre-shared key None No pre-shared key password will be used Table 54: Default SSL/TLS profile SSL/TLS Version Supported feature SSL 2.0 NO SSL 3.0 YES TLS 1.0 YES TLS 1.1 YES10 TLS 1.2 YES10 Table 55: SSL/TLS version support Algorithm Supported feature RSA YES10 PSK YES Table 56: Authentication 10 Not supported by "01", "x2" and "68" product versions](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-142.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Features description Page 143 of 175 Algorithm Supported feature RC4 NO11 DES YES 3DES YES10 AES128 YES AES256 YES10 Table 57: Encryption Algorithm Supported feature MD5 NO11 SHA/SHA1 YES SHA256 YES10 SHA384 YES10 Table 58: Message digest Description Registry value Supported feature TLS_RSA_WITH_AES_128_CBC_SHA 0x00,0x2F YES10 TLS_RSA_WITH_AES_128_CBC_SHA256 0x00,0x3C YES10 TLS_RSA_WITH_AES_256_CBC_SHA 0x00,0x35 YES10 TLS_RSA_WITH_AES_256_CBC_SHA256 0x00,0x3D YES10 TLS_RSA_WITH_3DES_EDE_CBC_SHA 0x00,0x0A YES10 TLS_RSA_WITH_RC4_128_MD5 0x00,0x04 NO11 TLS_RSA_WITH_RC4_128_SHA 0x00,0x05 NO11 TLS_PSK_WITH_AES_128_CBC_SHA 0x00,0x8C YES10 TLS_PSK_WITH_AES_256_CBC_SHA 0x00,0x8D YES10 TLS_PSK_WITH_3DES_EDE_CBC_SHA 0x00,0x8B YES10 TLS_RSA_PSK_WITH_AES_128_CBC_SHA 0x00,0x94 YES10 TLS_RSA_PSK_WITH_AES_256_CBC_SHA 0x00,0x95 YES10 TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA 0x00,0x93 YES10 TLS_PSK_WITH_AES_128_CBC_SHA256 0x00,0xAE YES10 TLS_PSK_WITH_AES_256_CBC_SHA384 0x00,0xAF YES10 TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 0x00,0xB6 YES10 TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 0x00,0xB7 YES10 Table 59: TLS cipher suite registry 3.8 Dual stack IPv4/IPv6 Not supported by "01", "x2" and "68" product versions. LISA-U2 modules support both Internet Protocol version 4 and Internet Protocol version 6. For more details about dual stack IPv4/IPv6 see the u-blox AT Commands Manual [2]. 11 Supported only by "01", "x2" and "68" product versions](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-143.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Features description Page 144 of 175 3.9 AssistNow clients and GNSS integration For customers using u-blox GNSS receivers, LISA-U2 cellular modules feature embedded AssistNow clients. AssistNow A-GPS provides better GNSS performance and faster Time-To-First-Fix. The clients can be enabled and disabled with an AT command (see the u-blox AT Commands Manual [2]). LISA-U2 modules act as a stand-alone AssistNow client, making AssistNow available with no additional requirements for resources or software integration on an external host micro controller. Full access to u-blox GNSS receivers is available via the LISA-U2 series, through a dedicated DDC (I2C) interface, while the available GPIOs can handle the positioning chipset / module power-on/off. This means that GSM/WCDMA and GNSS can be controlled through a single serial port from any host processor. 3.10 Hybrid positioning and CellLocate® Although GNSS is a widespread technology, its reliance on the visibility of extremely weak GNSS satellite signals means that positioning is not always possible. Especially difficult environments for GNSS are indoors, in enclosed or underground parking garages, as well as in urban canyons where GNSS signals are blocked or jammed by multipath interference. The situation can be improved by augmenting GNSS receiver data with cellular network information to provide positioning information even when GNSS reception is degraded or absent. This additional information can benefit numerous applications. 3.10.1 Positioning through cellular information: CellLocate® u-blox CellLocate® enables the estimation of device position based on the parameters of the mobile network cells visible to the specific device. To estimate its position the u-blox cellular module sends the CellLocate® server the parameters of network cells visible to it using a UDP connection. In return the server provides the estimated position based on the CellLocate® database. The u-blox cellular module can either send the parameters of the visible home network cells only (normal scan) or the parameters of all surrounding cells of all mobile operators (deep scan). Normal scan is only possible in 2G mode. The CellLocate® database is compiled from the position of devices which observed, in the past, a specific cell or set of cells (historical observations) as follows: 1. Several devices reported their position to the CellLocate® server when observing a specific cell (the As in the picture represent the position of the devices which observed the same cell A)](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-144.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Features description Page 146 of 175 3.10.2 Hybrid positioning With u-blox Hybrid positioning technology, u-blox cellular devices can be triggered to provide their current position using either a u-blox GNSS receiver or the position estimated from CellLocate®. The choice depends on which positioning method provides the best and fastest solution according to the user configuration, exploiting the benefit of having multiple and complementary positioning methods. Hybrid positioning is implemented through a set of three AT commands that allow configuration of the GNSS receiver (AT+ULOCGNSS), configuration of the CellLocate® service (AT+ULOCCELL), and requesting the position according to the user configuration (AT+ULOC). The answer is provided in the form of an unsolicited AT command including latitude, longitude and estimated accuracy (if the position has been estimated by CellLocate®), and additional parameters if the position has been computed by the GNSS receiver. The configuration of mobile network cells does not remain static (e.g. new cells are continuously added or existing cells are reconfigured by the network operators). For this reason, when a Hybrid positioning method has been triggered and the GNSS receiver calculates the position, a database self-learning mechanism has been implemented so that these positions are sent to the server to update the database and maintain its accuracy. The use of hybrid positioning requires a connection via the DDC (I2C) bus between the LISA-U2 cellular module and the u-blox GNSS receiver (see section 1.10). See the GNSS Implementation Application Note [16] for the complete description of the feature. u-blox is extremely mindful of user privacy. When a position is sent to the CellLocate® server u-blox is unable to track the SIM used or the specific device. 3.11 Control Plane Aiding / Location Services (LCS) Not supported by "01", "x2" and "68" product versions With the Assisted GPS feature, a location server provides the module with the GPS system information that otherwise has to be downloaded from satellites. The feature allows faster position fixes, increases sensitivity and reduces module power consumption. The feature is invoked by the module through LCS Supplementary Services or by the Network during emergency calls. The assisted GPS Location Services feature is based on the Radio Resources Location Protocol (RRLP), according to 3GPP TS 44.031 [27], and Radio Resource Control (RRC) according to 3GPP TS 25.331 [28]. For more details, see the u-blox AT Commands Manual [2]. 3.12 Firmware (upgrade) Over AT (FOAT) 3.12.1 Overview This feature allows upgrading the module Firmware over UART, USB and SPI interfaces, using AT Commands. AT Command AT+UFWUPD triggers a reboot followed by the upgrade procedure at specified a baud rate (see the u-blox AT Commands Manual [2] for more details) The Xmodem-1k protocol is used for downloading the new Firmware image via a terminal application A special boot loader on the module performs firmware installation, security verifications and module reboot Firmware authenticity verification is performed via a security signature during the download. The firmware is then installed, overwriting the current version. In case of power loss during this phase, the boot loader detects a fault at the next wake-up, and restarts the firmware download from the Xmodem-1k handshake. After completing the upgrade, the module is reset again and wakes-up in normal boot](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-146.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Features description Page 147 of 175 3.12.2 FOAT procedure The application processor must proceed in the following way: Send the AT+UFWUPD command through the UART or over the USB interface, specifying the file type and the desired baud rate Reconfigure the serial communication at the selected baud rate, without flow control with the Xmodem-1k protocol Send the new FW image via Xmodem-1k 3.13 In-Band modem (eCall / ERA-GLONASS) Not supported by supported by "01", "x2" and "68" product versions. LISA-U2 module supports an In-Band modem solution for eCall and ERA-GLONASS emergency call applications over cellular networks, implemented according to 3GPP TS 26.267 [24], BS EN 16062:2011 [25] and ETSI TS 122 101 [26] specifications. eCall (European) and ERA-GLONASS (Russian) are initiatives to combine mobile communications and satellite positioning to provide rapid assistance to motorists in the event of a collision, implementing automated emergency response system based the first on GPS the latter on GLONASS positioning system. When activated, the in-vehicle systems (IVS) automatically initiate an emergency call carrying both voice and data (including location data) directly to the nearest Public Safety Answering Point (PSAP) to determine whether rescue services should be dispatched to the known position. Figure 69: eCall and ERA-GLONASS automated emergency response systems diagram flow 3.14 SIM Access Profile (SAP) SIM access profile (SAP) feature allows LISA-U2 modules to access and use a remote (U)SIM card instead of the local SIM card directly connected to the module (U)SIM interface. LISA-U2 modules provide a dedicated USB SAP channel and dedicated multiplexer SAP channel over UART and SPI for communication with the remote (U)SIM card. The communication between LISA-U2 modules and the remote SIM is conformed to client-server paradigm: LISA-U2 module is the SAP client establishing a connection and performing data exchange to an SAP server directly connected to the remote SIM that is used by LISA-U2 module for GSM/UMTS network operations. SAP communication protocol is based on the SIM Access Profile Interoperability Specification [22]. LISA-U2 modules do not support SAP server role: the module acts as SAP client only.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-147.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Features description Page 148 of 175 A typical application using the SAP feature is the scenario where a device such as an embedded car-phone with an integrated LISA-U2 module uses a remote SIM included in an external user device (e.g. a simple SIM card reader or a portable phone), which is brought into the car. The car-phone accesses the GSM/UMTS network using the remote SIM in the external device. LISA-U2 modules, acting as an SAP client, can be connected to an SAP server by a completely wired connection, as shown in Figure 70. Device including LISAGSM/UMTS InterfaceSAP Serial Interface(USB SAP channel, or MUX SAP channel over UART or SPI)Local SIM(optional)LISA moduleSAP ClientApplicationProcessorDevice including SIMSAP Serial InterfaceRemote SIMMobileEquipmentSAP Server Figure 70: Remote SIM access via completely wired connection As stated in the SIM Access Profile Interoperability Specification [22], the SAP client can be connected to the SAP server by means of a Bluetooth cellular link, using additional Bluetooth transceivers. In this case, the application processor wired to LISA-U2 modules establishes and controls the Bluetooth connection using the SAP profile, and routes data received over a serial interface channel to data transferred over a Bluetooth interface and vice versa, as shown in Figure 71. Device including LISASAP Serial Interface(USB SAP channel, or MUX SAP channel over UART or SPI)GSM/UMTS InterfaceLocal SIM(optional)LISA moduleSAP ClientApplicationProcessorSAP Bluetooth InterfaceBluetoothTransceiverDevice including SIMRemote SIMMobileEquipmentSAP ServerBluetoothTransceiver Figure 71: Remote SIM access via Bluetooth and wired connection The application processor can start an SAP connection negotiation between LISA-U2 module SAP client and an SAP server using custom AT command (for more details see the u-blox AT Commands Manual [2]). While the connection with the SAP server is not fully established, the LISA-U2 module continues to operate with the attached (local) SIM, if present. Once the connection is established and negotiated, the LISA-U2 module performs a detach operation from the local SIM followed by an attach operation to the remote one. Then the remotely attached SIM is used for any GSM/UMTS network operation. URC indications are provided to inform the user about the state of both the local and remote SIM. The insertion and the removal of the local SIM card are notified if a proper card presence detection circuit using the GPIO5 of LISA-U2 modules is implemented as shown in the section 1.8.1, and if the related “SIM card detection” and “SIM hot insertion/removal” functions are enabled by AT commands (for more details see the u-blox AT Commands Manual [2], +UGPIOC, +UDCONF=50 AT commands). Upon SAP deactivation, the LISA-U2 modules perform a detach operation from the remote SIM followed by an attach operation to the local one, if present.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-148.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Features description Page 149 of 175 3.15 Smart Temperature Management Cellular modules – independent of the specific model – always have a well defined operating temperature range. This range should be respected to guarantee full device functionality and long life span. Nevertheless there are environmental conditions that can affect operating temperature, e.g. if the device is located near a heating/cooling source, if there is/isn’t air circulating, etc. The module itself can also influence the environmental conditions; such as when it is transmitting at full power. In this case its temperature increases very quickly and can raise the temperature nearby. The best solution is always to properly design the system where the module is integrated. Nevertheless an extra check/security mechanism embedded into the module is a good solution to prevent operation of the device outside of the specified range. 3.15.1 Smart Temperature Supervisor (STS) The Smart Temperature Supervisor is activated and configured by a dedicated AT+USTS command. See the u-blox AT Commands Manual [2] for more details. The cellular module measures the internal temperature (Ti) and its value is compared with predefined thresholds to identify the actual working temperature range. Temperature measurement is done inside the cellular module: the measured value could be different from the environmental temperature (Ta). Warningareat-1 t+1 t+2t-2Valid temperature rangeSafeareaDangerousarea Dangerousarea Warningarea Figure 72: Temperature range and limits The entire temperature range is divided into sub-regions by limits (see Figure 72) named t-2, t-1, t+1 and t+2. Within the first limit, (t-1 < Ti < t+1), the cellular module is in the normal working range, the Safe Area In the Warning Area, (t-2 < Ti < t.1) or (t+1 < Ti < t+2), the cellular module is still inside the valid temperature range, but the measured temperature approaches the limit (upper or lower). The module sends a warning to the user (through the active AT communication interface), which can take, if possible, the necessary actions to return to a safer temperature range or simply ignore the indication. The module is still in a valid and good working condition Outside the valid temperature range, (Ti < t-2) or (Ti > t+2), the device is working outside the specified range and represents a dangerous working condition. This condition is indicated and the device shuts down to avoid damage For security reasons the shutdown is suspended in case an emergency call in progress. In this case the device will switch off at call termination. The user can decide at anytime to enable/disable the Smart Temperature Supervisor feature. If the feature is disabled there is no embedded protection against disallowed temperature conditions.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-149.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Features description Page 151 of 175 3.15.2 Threshold Definitions When the application of cellular module operates at extreme temperatures with Smart Temperature Supervisor enabled, the user should note that outside the valid temperature range the device will automatically shut down as described above. The input for the algorithm is always the temperature measured within the cellular module (Ti, internal). This value can be higher than the working ambient temperature (Ta, ambient), since (for example) during transmission at maximum power a significant fraction of DC input power is dissipated as heat This behavior is partially compensated by the definition of the upper shutdown threshold (t+2) that is slightly higher than the declared environmental temperature limit. The temperature thresholds are defined according the Table 60. Symbol Parameter Temperature Remarks t-2 Low temperature shutdown –40 °C Equal to the absolute minimum temperature rating for the cellular module (the lower limit of the extended temperature range) t-1 Low temperature warning –30 °C 10°C above t-2 t+1 High temperature warning +77 °C 20°C below t+2. The higher warning area for upper range ensures that any countermeasures used to limit the thermal heating will become effective, even considering some thermal inertia of the complete assembly. t+2 High temperature shutdown +97 °C Equal to the internal temperature Ti measured in the worst case operating condition at typical supply voltage when the ambient temperature Ta in the reference setup (*) equals the absolute maximum temperature rating (upper limit of the extended temperature range) (*)LISA-U2 module mounted on a 90 mm x 70 mm x 1.46 mm 4-Layers PCB with a high coverage of copper within climatic chamber Table 60: Thresholds definition for Smart Temperature Supervisor on the LISA-U2 modules The sensor measures board temperature inside the shields, which can differ from ambient temperature. 3.16 Bearer Independent Protocol Not supported by "01", "x2" and "68" product versions. The Bearer Independent Protocol is a mechanism by which a cellular module provides a SIM with access to the data bearers supported by the network. With the Bearer Independent Protocol (BIP) for Over-the-Air SIM provisioning, the data transfer from and to the SIM uses either an already active PDP context or a new PDP context established with the APN provided by the SIM card. For more details, see the u-blox AT Commands Manual [2]. 3.17 Multi-Level Precedence and Pre-emption Service Not supported by "01", "x2" and "68" product versions. The Multi-Level Precedence and Pre-emption Service (eMLPP) permits to handle the call priority. The maximum priority associated to a user is set in the SIM: within this threshold, the user can assign different priorities to the calls. This results in a differentiated treatment of the calls by the network in case of abnormal events such as handovers to congested cells. For more details, see the u-blox AT Commands Manual [2].](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-151.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Features description Page 152 of 175 3.18 Network Friendly Mode Not supported by "01", "x2" and "68" product versions. The Network Friendly Mode (NFM) feature provides a more efficient access to the network since it regulates the number of network accesses per service type over a configurable amount of time, avoiding scenarios in which the cellular module continuously retries a registration or a PDP context activation procedure until it is successful. In case of appropriate network rejection errors, a back-off timer can be started: when the timer is running or the number of allowed accesses is reached, further attempts are denied and an URC may be enabled to indicate the time remaining before a further attempt can be served. The back-off timer controls the temporal spread of successive attempts to register to CS or PS services, to activate a PDP context and to send SMS messages. For more details, see the u-blox AT Commands Manual [2]. 3.19 Power saving The power saving configuration is by default disabled, but it can be enabled using the AT+UPSV command. When power saving is enabled, the module automatically enters the low power idle-mode whenever possible, reducing current consumption. During the low power idle-mode, the module is not ready to communicate with an external device by means of the application interfaces, since it is configured to reduce power consumption. The module wakes up from the low power idle-mode to the active-mode in these events: Automatic periodic monitoring of the paging channel for the paging block reception according to network conditions (see sections 1.5.3.3, 1.9.2.3) Automatic periodic enable of the UART interface to receive and send data, if AT+UPSV=1 has been set (see section 1.9.2.3) Data received on UART interface, if HW flow control has been disabled by AT&K0 and AT+UPSV=1 has been set (see section 1.9.2.3) RTS input set ON by the DTE if HW flow control has been disabled by AT&K0 and AT+UPSV=2 has been set (see section 1.9.2.3) DTR input set ON by DTE if AT+UPSV=3 has been set (not supported by “01” product versions, see section 1.9.2.3) USB detection, applying 5 V (typ.) to VUSB_DET input (see section 1.9.3) The connected USB host forces a remote wakeup of the module as USB device (see section 1.9.3) The connected SPI master indicates by means of the SPI_MRDY input signal of the module that it is ready for transmission or reception over the SPI interface (see section 1.9.4) The connected u-blox GNSS receiver indicates by means of the GPIO3 pin previously configured for the “GNSS data ready” function that it is ready to send data over the I2C / DDC interface (see sections 1.10, 1.12) RTC alarm previously configured by AT command (see u-blox AT Commands Manual [2], AT+CALA) For the complete description of the AT+UPSV command, see the u-blox AT Commands Manual [2]. For the definition and the description of LISA-U2 series modules operating modes, including the events forcing transitions between the different operating modes, see section 1.4. For the description of current consumption in idle and active operating modes, see sections 1.5.3.3, 1.5.3.4. For the description of the UART behavior related to module power saving configuration, see section 1.9.2.3. For the description of the USB behavior related to module power saving configuration, see section 1.9.3.2. For the description of the SPI behavior related to module power saving configuration, see section 1.9.4.2.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-152.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Handling and soldering Page 153 of 175 4 Handling and soldering No natural rubbers, no hygroscopic materials or materials containing asbestos are employed. 4.1 Packaging, shipping, storage and moisture preconditioning For information pertaining to reels and tapes, Moisture Sensitivity levels (MSD), shipment and storage information, as well as drying for preconditioning see the LISA-U2 series Data Sheet [1] and u-blox Package Information Guide [21]. The LISA-U2 modules are Electro-Static Discharge (ESD) sensitive devices. Ensure ESD precautions are implemented during handling of the module. 4.2 Soldering 4.2.1 Soldering paste Use of "No Clean" soldering paste is strongly recommended, as it does not require cleaning after the soldering process has taken place. The paste listed in the example below meets these criteria. Soldering Paste: OM338 SAC405 / Nr.143714 (Cookson Electronics) Alloy specification: 95.5% Sn / 3.9% Ag / 0.6% Cu (95.5% Tin / 3.9% Silver / 0.6% Copper) 95.5% Sn / 4.0% Ag / 0.5% Cu (95.5% Tin / 4.0% Silver / 0.5% Copper) Melting Temperature: 217°C Stencil Thickness: 150 µm for base boards The final choice of the soldering paste depends on the approved manufacturing procedures. The paste-mask geometry for applying soldering paste should meet the recommendations in section 2.2.2 The quality of the solder joints on the connectors (’half vias’) should meet the appropriate IPC specification. 4.2.2 Reflow soldering A convection type-soldering oven is strongly recommended over the infrared type radiation oven. Convection heated ovens allow precise control of the temperature and all parts will be heated up evenly, regardless of material properties, thickness of components and surface color. Consider the "IPC-7530 Guidelines for temperature profiling for mass soldering (reflow and wave) processes, published 2001". Reflow profiles are to be selected according to the following recommendations. Failure to observe these recommendations can result in severe damage to the device! Be aware that IPC/JEDEC J-STD-020 applies to integrated circuits, cannot be properly applied to module devices.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-153.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Handling and soldering Page 154 of 175 Preheat phase Initial heating of component leads and balls. Residual humidity will be dried out. This preheat phase will not replace prior baking procedures. Temperature rise rate: max 3°C/s If the temperature rise is too rapid in the preheat phase it may cause excessive slumping. Time: 60 – 120 s If the preheat is insufficient, rather large solder balls tend to be generated. Conversely, if performed excessively, fine balls and large balls will be generated in clusters. End Temperature: 150 - 200°C If the temperature is too low, non-melting tends to be caused in areas containing large heat capacity. Heating/ reflow phase The temperature rises above the liquidus temperature of 217°C. Avoid a sudden rise in temperature as the slump of the paste could become worse. Limit time above 217°C liquidus temperature: 40 - 60 s Peak reflow temperature: 245°C Cooling phase A controlled cooling avoids negative metallurgical effects (solder becomes more brittle) of the solder and possible mechanical tensions in the products. Controlled cooling helps to achieve bright solder fillets with a good shape and low contact angle. Temperature fall rate: max 4°C / s To avoid falling off, modules should be placed on the topside of the motherboard during soldering. The soldering temperature profile chosen at the factory depends on additional external factors like choice of soldering paste, size, thickness and properties of the base board, etc. Exceeding the maximum soldering temperature and the maximum liquidus time limit in the recommended soldering profile may permanently damage the module. Preheat Heating Cooling[°C] Peak Temp. 245°C [°C]250 250Liquidus Temperature217 217200 20040 - 60 sEnd Temp.max 4°C/s150 - 200°C150 150max 3°C/s60 - 120 s100 Typical Leadfree 100Soldering Profile50 50Elapsed time [s] Figure 74: Recommended soldering profile LISA-U2 modules must not be soldered with a damp heat process. When soldering lead-free LISA-U2 series modules in a leaded process, check the following temperatures:](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-154.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Product Testing Page 158 of 175 Component assembly on the device; it should be verified that: o Communication with host controller can be established o The interfaces between module and device are working o Overall RF performance test of the device including antenna Dedicated tests can be implemented to check the device. For example, the measurement of module current consumption when set in a specified status can detect a short circuit if compared with a “Golden Device” result. Module AT commands are used to perform functional tests (communication with host controller, check SIM card interface, check communication between module and GNSS, GPIOs, etc.) and to perform RF performance tests. 5.2.1 ‘Go/No go’ tests for integrated devices A ‘Go/No go’ test is to compare the signal quality with a “Golden Device” in a position with excellent 2G/3G network coverage and after having dialed a call (see the u-blox AT Commands Manual [2], AT+CSQ command: <rssi>, <ber> parameters). These kinds of test may be useful as a ‘go/no go’ test but not for RF performance measurements. This test is suitable to check the communication with host controller and SIM card, the audio and power supply functionality and verify if components at antenna interface are well soldered. 5.2.2 Functional tests providing RF operation Overall RF performance test of the device including antenna can be performed with basic instruments such as a spectrum analyzer (or an RF power meter) and a signal generator using AT+UTEST command over AT interface. The AT+UTEST command gives a simple interface to set the module to Rx and Tx test modes ignoring 2G/3G signaling protocol. The command can set the module: In transmitting mode in a specified channel and power level in all supported modulation schemes (single slot GMSK, single slot 8PSK, WCDMA) and bands 2G, 3G In receiving mode in a specified channel to returns the measured power level in all supported bands 2G, 3G See the u-blox AT Commands Manual [2], for AT+UTEST command syntax description. See the End user test Application Note [20], for AT+UTEST command user guide, limitations and examples of use.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-158.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Appendix Page 161 of 175 Appendix A Migration from LISA-U1 to LISA-U2 series Migrating LISA-U1 series designs to LISA-U2 series modules is a straight forward procedure. Nevertheless there are some points to be considered during the migration. A.1 Checklist for migration Have you chosen the optimal module? For HSDPA category 14, 6-band 3G, Digital Audio Interfaces support, select a LISA-U230 module. For HSDPA category 8, 6-band 3G, Digital Audio Interfaces support, select a suitable LISA-U200 module. For HSDPA category 8, 5-band 3G, Digital Audio Interfaces support, select LISA-U201 module. For HSDPA category 8, 2-band 3G 850/1900 (North America), Digital Audio Interfaces support, select a suitable LISA-U260 module. For HSDPA category 8, 2-band 3G 900/2100 (Europe, Asia, Middle-East and Africa), Digital Audio Interfaces support, select a suitable LISA-U270 module. Check LISA-U2 series Hardware Requirements Check the supported 3G bands for proper antenna circuit development, since LISA-U2 supports different 3G bands in comparison to LISA-U1 series cellular modules. Check audio requirements, since Analog Audio Interfaces are not supported by LISA-U2 series. Check audio requirements, since Digital Audio Interfaces are supported by LISA-U2 series modules. Check the PWR_ON low pulse time specified to switch-on the module, since PWR_ON low pulse time requirement is different in comparison to LISA-U1 series modules. Check the PWR_ON behavior, since LISA-U2 series modules can be switched off forcing PWR_ON pin to the low level for at least 1 s. Check the PWR_ON input voltage thresholds, since they are slightly changed in comparison to LISA-U1 series modules. By the way, this is not relevant driving the PWR_ON input by an open drain or open collector driver as recommended. Check the RESET_N input voltage thresholds, since they are slightly changed in comparison to LISA-U1 series modules. By the way, this is not relevant driving the RESET_N input by an open drain or open collector driver as recommended. Check the V_BCKP operating characteristics, since they are slightly changed in comparison to LISA-U1 series modules. Check internal active pull-up / down values at digital interface input pins and the current capability of digital interface output pins, since they are slightly changed in comparison to LISA-U1 series modules. Check board layout, since additional signals keep-out area must be implemented on the top layer of the application board, below LISA-U2 modules, due to GND opening on module bottom layer. A.2 Software migration A.2.1 Software migration from LISA-U1 series to LISA-U2 series modules Software migration from LISA-U1 to LISA-U2 series cellular modules is a straightforward procedure. Nevertheless there are some differences to be considered with firmware version. Like predecessors, LISA-U2 series cellular module supports AT commands according to 3GPP standards: TS 27.007 [4], TS 27.005 [5], TS 27.010 [6] and the u-blox AT command extension. Backward compatibility has been maintained as far as possible. For the complete list of supported AT commands and their syntax see u-blox AT Commands Manual [2].](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-161.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Appendix Page 163 of 175 The 5 pins of the SPI / IPC Serial Interface can be configured as GPIOs on LISA-U2 series. The DDC (I2C) interface of LISA-U2 series modules can be used to communicate with u-blox GNSS receivers and at the same time to control an external audio codec. The LISA-U2 series module acts as an I2C master which can communicate to two I2C slaves as allowed by I2C bus specifications [8]. LISA-U2 modules provide additional GPIO functions: Module Status and Operating Mode Indications. LISA-U2 modules are SMT modules and share the same compact form factor as the LISA-U1 series, featuring Leadless Chip Carrier (LCC) packaging technology. An additional signal keep-out area must be implemented on the top layer of the application board, below LISA-U2 modules, due to the GND opening on module bottom layer. Detailed pinout and layout comparisons between LISA-U1 series and LISA-U2 series modules, with remarks for migration, are provided in the subsections A.3.2 and A.3.3. For more information about the electrical characteristics of the LISA-U1 and LISA-U2 series modules, see the LISA-U1 series Data Sheet [29] and LISA-U2 series Data Sheet [1]. A.3.2 Pin-out comparison LISA-U1 series vs. LISA-U2 series 65646362616059585756555453525150494847464544434241GNDVCCVCCVCCGNDSPI_MRDYSPI_SRDYSPI_MISOSPI_MOSISPI_SCLKRSVD / SPK_NGNDRSVD / SPK_PRSVDGPIO5VSIMSIM_RSTSIM_IOSIM_CLKSDASCLRSVD / I2S_RXDRSVD / I2S_CLKRSVD / I2S_TXDRSVD / I2S_WA12345678910111213141516171819202122232425V_BCKPGNDV_INTRSVDGNDGNDGNDDSRRIDCDDTRGNDRTSCTSTXDRXDGNDVUSB_DETPWR_ONGPIO1GPIO2RESET_NGPIO3GPIO4GND2627USB_D-USB_D+4039RSVD / MIC_PRSVD / MIC_N28293031323334353637387675747372717069686766GNDRSVDGNDGNDGNDGNDGNDANTGNDGNDGNDLISA-U1Top ViewPin 28…38 = GNDRSVDAnalog AudioSPIRSVD Figure 77: LISA-U1 series pin assignment 65646362616059585756555453525150494847464544434241GNDVCCVCCVCCGNDSPI_MRDY / GPIO14SPI_SRDY / GPIO13SPI_MISO / GPIO12SPI_MOSI / GPIO11SPI_SCLK / GPIO10GPIO9 / I2S1_WAGNDGPIO8 / I2S1_CLKRSVD / CODEC_CLKGPIO5VSIMSIM_RSTSIM_IOSIM_CLKSDASCLRSVD / I2S_RXDRSVD / I2S_CLKRSVD / I2S_TXDRSVD / I2S_WA12345678910111213141516171819202122232425V_BCKPGNDV_INTRSVDGNDGNDGNDDSRRIDCDDTRGNDRTSCTSTXDRXDGNDVUSB_DETPWR_ONGPIO1GPIO2RESET_NGPIO3GPIO4GND2627USB_D-USB_D+4039GPIO7 / I2S1_TXDGPIO6 / I2S1_RXD28293031323334353637387675747372717069686766GNDRSVD / ANT_DIVGNDGNDGNDGNDGNDANTGNDGNDGNDLISA-U2Top ViewPin 28…38 = GNDClock OutDigital Audio or GPIORx DivSPI or GPIO Figure 78: LISA-U2 series pin assignment (highlighted name/function changes)](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-163.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Related documents Page 173 of 175 Related documents [1] u-blox LISA-U2 series Data Sheet, Docu No UBX-13001734 [2] u-blox AT Commands Manual, Docu No UBX-13002752 [3] ITU-T Recommendation V.24, 02-2000. List of definitions for interchange circuits between data terminal equipment (DTE) and data circuit-terminating equipment (DCE). http://www.itu.int/rec/T-REC-V.24-200002-I/en [4] 3GPP TS 27.007 - AT command set for User Equipment (UE) (Release 1999) [5] 3GPP TS 27.005 - Use of Data Terminal Equipment - Data Circuit terminating; Equipment (DTE - DCE) interface for Short Message Service (SMS) and Cell Broadcast Service (CBS) (Release 1999) [6] 3GPP TS 27.010 - Terminal Equipment to User Equipment (TE-UE) multiplexer protocol (Release 1999) [7] Universal Serial Bus Revision 2.0 specification, http://www.usb.org/developers/docs/ [8] I2C-Bus specification and user manual - Rev. 5 - 9 October 2012 - NXP Semiconductors, http://www.nxp.com/documents/user_manual/UM10204.pdf [9] 3GPP TS 51.010-2 - Technical Specification Group GSM/EDGE Radio Access Network; Mobile Station (MS) conformance specification; Part 2: Protocol Implementation Conformance Statement (PICS) [10] 3GPP TS 34.121-2 - Technical Specification Group Radio Access Network; User Equipment (UE) conformance specification; Radio transmission and reception (FDD); Part 2: Implementation Conformance Statement (ICS) [11] CENELEC EN 61000-4-2 (2001): "Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques - Electrostatic discharge immunity test". [12] ETSI EN 301 489-1 V1.8.1: “Electromagnetic compatibility and Radio spectrum Matters (ERM); ElectroMagnetic Compatibility (EMC) standard for radio equipment and services; Part 1: Common technical requirements” [13] ETSI EN 301 489-7 V1.3.1: “Electromagnetic compatibility and Radio spectrum Matters (ERM); ElectroMagnetic Compatibility (EMC) standard for radio equipment and services; Part 7: Specific conditions for mobile and portable radio and ancillary equipment of digital cellular radio telecommunications systems (GSM and DCS)“ [14] ETSI EN 301 489-24 V1.4.1: "Electromagnetic compatibility and Radio spectrum Matters (ERM); Electro-Magnetic Compatibility (EMC) standard for radio equipment and services; Part 24: Specific conditions for IMT-2000 CDMA Direct Spread (UTRA) for Mobile and portable (UE) radio and ancillary equipment" [15] u-blox Multiplexer Implementation Application Note, Docu No UBX-13001887 [16] u-blox GNSS Implementation Application Note, Docu No UBX-13001849 [17] u-blox Firmware Update Application Note, Docu No UBX-13001845 [18] u-blox SPI Interface Application Note, Docu No UBX-13001919 [19] 3GPP TS 23.060 - Technical Specification Group Services and System Aspects; General Packet Radio Service (GPRS); Service description [20] u-blox End user test Application Note, Docu No WLS-CS-12002 [21] u-blox Package Information Guide, Docu No GPS-X-11004 [22] SIM Access Profile Interoperability Specification, Revision V11r00, http://www.bluetooth.org [23] u-blox LISA-U1 / LISA-U2 Audio Application Note, Docu No UBX-13001835 [24] 3GPP TS 26.267 V10.0.0 – eCall Data Transfer; In-band modem solution; General description (Rel. 10) [25] BS EN 16062:2011 – Intelligent transport systems – eSafety – eCall high level application requirements [26] ETSI TS 122 101 V8.7.0 – Service aspects; Service principles (3GPP TS 22.101 v.8.7.0 Rel. 8) [27] 3GPP TS 44.031 Location Services (LCS); Mobile Station (MS) - Serving Mobile Location Centre (SMLC) Radio Resource LCS Protocol (RRLP) [28] 3GPP TS 25.331 Radio Resource Control (RRC); Protocol specification [29] u-blox LISA-U1 series Data Sheet, Docu No UBX-13002048 Some of the above documents can be downloaded from u-blox web-site (http://www.u-blox.com).](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-173.png)
![LISA-U2 series - System Integration Manual UBX-13001118 - R19 Early Production Information Revision history Page 174 of 175 Revision history Revision Date Name Status / Comments - 21-Oct-2010 sses Initial Release 1 11-Jan-2011 sses Thickness information added. GPIO description improved 2 26-Apr-2011 lpah Update to Advance Information status 3 07-Jul-2011 lpah Update to Preliminary status A 26-Oct-2011 sses Changed status to Objective Specification Initial release for LISA-U series: From LISA-U1x0-00S system integration manual, added the description and the integration of LISA-U1x0-01S, LISA-U200-00S, LISA-U2x0-01S Added notes regarding VCC normal and extended operating ranges. Added RTC value reliability as function of V_BCKP voltage value. Added recommendation regarding any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and GPIOs when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence: must be tri-stated to avoid latch-up of circuits and let a proper boot of the module. A1 22-Nov-2011 sses Update to Advance Information status Updated module behavior during power-off sequence. Added LISA-U200-00S ESD application circuit for antenna port. Added application circuit for the module status indication function. A2 02-Feb-2012 sses Update to Preliminary status Updated Federal Communications Commission notice. Updated LISA-U2 features in module power off and GPIO sections A3 25-May-2012 gcom Updated values for antenna gain A4 20-Jun-2012 sses Update to Advance Information status Updated PWR_ON behavior. Updated UART and power saving behavior. Added 3V / 1.8V SPI application circuit. Updated GPS RTC sharing application circuit. Added remote SIM access profile description A5 24-Aug-2012 sses Update to Preliminary status Updated Federal Communications Commission notice. Updated recommended VCC bypass capacitors. Added LISA-U110-60S and LISA-U130-60S A6 04-Oct-2012 lpah / sses Update to Advance Information status Added LISA-U260 and LISA-U270 A7 26-Nov-2012 lpah / sses Update to Preliminary status Removed document applicability to LISA-U1x0-00S versions Added document applicability to LISA-U110-50S versions A8 29-Mar-2013 sses Updated additional recommendations for VCC application circuits (Last revision with old doc number, 3G.G2-HW-10002) B 15-Jul-2013 sses Update status to Advance Information First release for LISA-U200-02S, LISA-U200-61S, LISA-U200-62S, LISA-U260-02S, LISA-U270-02S, LISA-U270-62S B1 21-Aug-2013 lpah Update status to Preliminary R16 20-Mar-2014 lpah / sses Extended document applicability to LISA-U200-52S and LISA-U200-82S (LISA-U200 FOTA) Updated recommended I2C voltage translator and clarified I2C application circuits remarks Clarified and improved power-on, power-off and reset timings and procedures descriptions R17 26-Jun-2015 sfal Extended document applicability to LISA-U200-03S and LISA-U201-03S R18 10-Aug-2015 sfal Early Production Information status Removed LISA-U1 series modules and LISA-U200-00S Extended applicability to LISA-U200-83S and LISA-U270-68S Comment [smos1]: I would remove this to make space on the page for further revision history. This is old and very detailed, so unnecessary.](https://usermanual.wiki/u-blox/LISAU201.Installation-Instructions/User-Guide-2744364-Page-174.png)
