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SARA-G3 and SARA-U2 series GSM/GPRS and GSM/EGPRS/HSPA Cellular Modules System Integration Manual Abstract This document describes the features and the system integration of the SARA-G3 series GSM/GPRS cellular modules and the SARA-U2 GSM/EGPRS/HSPA cellular modules. These modules are complete and cost efficient solutions offering voice and/or data communication over diverse cellular radio access technologies in the same compact SARA form factor: the SARA-G3 series support up to 4-band GSM/GPRS while the SARA-U2 series support 2-band high-speed HSPA and up to 2-band GSM/EGPRS. www.u-blox.com UBX-13000995 - R08

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Page 2 of 188 Document Information Title SARA-G3 and SARA-U2 series Subtitle GSM/GPRS and GSM/EGPRS/HSPA Cellular Modules Document type System Integration Manual Document number UBX-13000995 Revision, date R08 29-Apr-2014 Document status Objective Specification Document status explanation Objective Specification Document contains target values. Revised and supplementary data will be published later. Advance Information Document contains data based on early testing. Revised and supplementary data will be published later. Early Production Information Document contains data from product verification. Revised and supplementary data may be published later. Production Information Document contains the final product specification. This document applies to the following products: Product name Type number Firmware version PCN / IN SARA-G300 SARA-G300-00S-00 08.58 GSM.G2-TN-13007 SARA-G310 SARA-G310-00S-00 08.58 GSM.G2-TN-13007 SARA-G340 SARA-G340-00S-00 08.49 UBX-14000382 SARA-G350 SARA-G350-00S-00 08.49 GSM.G2-TN-13002 SARA-G350 ATEX SARA-G350-00X-00 08.49 GSM.G2-TN-13002 SARA-U260 SARA-U260-00S-00 TBD TBD SARA-U270 SARA-U270-00S-00 TBD TBD SARA-U280 SARA-U280-00S-00 TBD TBD SARA-U290 SARA-U290-00S-00 TBD TBD SARA-U290-60S-00 TBD TBD u-blox reserves all rights to this document and the information contained herein. Products, names, logos and designs described herein may in whole or in part be subject to intellectual property rights. Reproduction, use, modification or disclosure to third parties of this document or any part thereof without the express permission of u-blox is strictly prohibited. The information contained herein is provided “as is” and u-blox assumes no liability for the use of the information. No warranty, either express or implied, is given, including but not limited, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time. For most recent documents, please visit www.u-blox.com. Copyright © 2014, u-blox AG Trademark Notice Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. All other registered trademarks or trademarks mentioned in this document are property of their respective owners.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification Preface Page 3 of 188 Preface u-blox Technical Documentation As part of our commitment to customer support, u-blox maintains an extensive volume of technical documentation for our products. In addition to our product-specific technical data sheets, the following manuals are available to assist u-blox customers in product design and development.  AT Commands Manual: This document provides the description of the AT commands supported by the u-blox cellular modules.  System Integration Manual: This document provides the description of u-blox cellular modules’ system from the hardware and the software point of view, it provides hardware design guidelines for the optimal integration of the cellular modules in the application device and it provides information on how to set up production and final product tests on application devices integrating the cellular modules.  Application Notes: These documents provide guidelines and information on specific hardware and/or software topics on u-blox cellular modules. See Related documents for a list of application notes related to your cellular module. How to use this Manual The SARA-G3 and SARA-U2 series System Integration Manual provides the necessary information to successfully design in and configure these u-blox cellular modules. This manual has a modular structure. It is not necessary to read it from the beginning to the end. The following symbols are used to highlight important information within the manual: An index finger points out key information pertaining to module integration and performance. A warning symbol indicates actions that could negatively impact or damage the module. Questions If you have any questions about u-blox cellular Integration:  Read this manual carefully.  Contact our information service on the homepage http://www.u-blox.com Technical Support Worldwide Web Our website (www.u-blox.com) is a rich pool of information. Product information and technical documents can be accessed 24h a day. By E-mail If you have technical problems or cannot find the required information in the provided documents, contact the closest Technical Support office. To ensure that we process your request as soon as possible, use our service pool email addresses rather than personal staff email addresses. Contact details are at the end of the document. Helpful Information when Contacting Technical Support When contacting Technical Support, have the following information ready:  Module type (e.g. SARA-G350) and firmware version  Module configuration  Clear description of your question or the problem  A short description of the application  Your complete contact details

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification Contents Page 4 of 188 Contents Preface ................................................................................................................................ 3 Contents .............................................................................................................................. 4 1 System description ....................................................................................................... 8 1.1 Overview .............................................................................................................................................. 8 1.2 Architecture ........................................................................................................................................ 10 1.2.1 Internal blocks ............................................................................................................................. 12 1.3 Pin-out ............................................................................................................................................... 13 1.4 Operating modes ................................................................................................................................ 18 1.5 Supply interfaces ................................................................................................................................ 20 1.5.1 Module supply input (VCC) ......................................................................................................... 20 1.5.2 RTC supply input/output (V_BCKP) .............................................................................................. 29 1.5.3 Generic digital interfaces supply output (V_INT) ........................................................................... 30 1.6 System function interfaces .................................................................................................................. 31 1.6.1 Module power-on ....................................................................................................................... 31 1.6.2 Module power-off ....................................................................................................................... 34 1.6.3 Module reset ............................................................................................................................... 36 1.6.4 External 32 kHz signal input (EXT32K) ......................................................................................... 37 1.6.5 Internal 32 kHz signal output (32K_OUT) .................................................................................... 37 1.7 Antenna interface ............................................................................................................................... 38 1.7.1 Antenna RF interface (ANT) ......................................................................................................... 38 1.7.2 Antenna detection interface (ANT_DET) ...................................................................................... 39 1.8 SIM interface ...................................................................................................................................... 39 1.8.1 (U)SIM card interface ................................................................................................................... 39 1.8.2 SIM card detection interface (SIM_DET) ....................................................................................... 39 1.9 Serial interfaces .................................................................................................................................. 40 1.9.1 Asynchronous serial interface (UART)........................................................................................... 40 1.9.2 Auxiliary asynchronous serial interface (UART AUX) ..................................................................... 53 1.9.3 USB interface............................................................................................................................... 53 1.9.4 DDC (I2C) interface ...................................................................................................................... 55 1.10 Audio interface ............................................................................................................................... 57 1.10.1 Analog audio interface ................................................................................................................ 57 1.10.2 Digital audio interface ................................................................................................................. 59 1.10.3 Voice-band processing system ..................................................................................................... 61 1.11 General Purpose Input/Output (GPIO) ............................................................................................. 64 1.12 Reserved pins (RSVD) ...................................................................................................................... 68 1.13 System features............................................................................................................................... 69 1.13.1 Network indication ...................................................................................................................... 69 1.13.2 Antenna detection ...................................................................................................................... 69 1.13.3 Jamming detection ...................................................................................................................... 69

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification Contents Page 6 of 188 2.13.2 ESD immunity test of u-blox SARA-G3 and SARA-U2 reference designs..................................... 143 2.13.3 ESD application circuits .............................................................................................................. 144 2.14 SARA-G350 ATEX integration in explosive atmospheres applications ............................................ 146 2.14.1 General guidelines ..................................................................................................................... 146 2.14.2 Guidelines for VCC supply circuit design ................................................................................... 147 2.14.3 Guidelines for antenna RF interface design ................................................................................ 148 2.15 Schematic for SARA-G3 and SARA-U2 series module integration .................................................. 149 2.15.1 Schematic for SARA-G300 / SARA-G310 modules integration ................................................... 149 2.15.2 Schematic for SARA-G340 / SARA-G350 modules integration ................................................... 150 2.15.3 Schematic for SARA-U2 series modules integration ................................................................... 151 2.16 Design-in checklist ........................................................................................................................ 152 2.16.1 Schematic checklist ................................................................................................................... 152 2.16.2 Layout checklist ......................................................................................................................... 153 2.16.3 Antenna checklist ...................................................................................................................... 153 3 Handling and soldering ........................................................................................... 154 3.1 Packaging, shipping, storage and moisture preconditioning ............................................................. 154 3.2 Handling ........................................................................................................................................... 154 3.3 Soldering .......................................................................................................................................... 155 3.3.1 Soldering paste.......................................................................................................................... 155 3.3.2 Reflow soldering ....................................................................................................................... 155 3.3.3 Optical inspection ...................................................................................................................... 156 3.3.4 Cleaning .................................................................................................................................... 156 3.3.5 Repeated reflow soldering ......................................................................................................... 157 3.3.6 Wave soldering.......................................................................................................................... 157 3.3.7 Hand soldering .......................................................................................................................... 157 3.3.8 Rework ...................................................................................................................................... 157 3.3.9 Conformal coating .................................................................................................................... 157 3.3.10 Casting ...................................................................................................................................... 157 3.3.11 Grounding metal covers ............................................................................................................ 157 3.3.12 Use of ultrasonic processes ........................................................................................................ 157 4 Approvals .................................................................................................................. 158 4.1 Product certification approval overview ............................................................................................. 158 4.2 Federal Communications Commission and Industry Canada notice ................................................... 159 4.2.1 Safety warnings review the structure ......................................................................................... 159 4.2.2 Declaration of conformity – United States only .......................................................................... 159 4.2.3 Modifications ............................................................................................................................ 160 4.3 R&TTED and European conformance CE mark .................................................................................. 161 4.4 Anatel certification ........................................................................................................................... 162 4.5 SARA-G350 ATEX conformance for use in explosive atmospheres .................................................... 163 5 Product testing ......................................................................................................... 164 5.1 u-blox in-series production test ......................................................................................................... 164 5.2 Test parameters for OEM manufacturer ............................................................................................ 164

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification Contents Page 7 of 188 5.2.1 “Go/No go” tests for integrated devices .................................................................................... 165 5.2.2 Functional tests providing RF operation ..................................................................................... 165 Appendix ........................................................................................................................ 168 A Migration between LISA and SARA-G3 modules ................................................... 168 A.1 Overview .......................................................................................................................................... 168 A.2 Checklist for migration ..................................................................................................................... 169 A.3 Software migration ........................................................................................................................... 170 A.4 Hardware migration.......................................................................................................................... 170 A.4.1 Supply interfaces ....................................................................................................................... 170 A.4.2 System functions interfaces ....................................................................................................... 171 A.4.3 Antenna interface ..................................................................................................................... 172 A.4.4 SIM interface ............................................................................................................................. 173 A.4.5 Serial interfaces ......................................................................................................................... 173 A.4.6 Audio interfaces ........................................................................................................................ 174 A.4.7 GPIO pins .................................................................................................................................. 174 A.4.8 Reserved pins ............................................................................................................................ 174 A.4.9 Pin-out comparison between LISA and SARA-G3 ....................................................................... 175 B Migration between SARA-G3 and SARA-U2 ........................................................... 180 B.1 Overview .......................................................................................................................................... 180 B.2 Pin-out comparison between SARA-G3 and SARA-U2 ...................................................................... 181 B.3 Schematic for SARA-G3 and SARA-U2 integration ............................................................................ 183 C Glossary .................................................................................................................... 184 Related documents......................................................................................................... 186 Revision history .............................................................................................................. 187 Contact ............................................................................................................................ 188

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 8 of 188 1 System description 1.1 Overview SARA-G3 series GSM/GPRS cellular modules and SARA-U2 series GSM/EGPRS/HSPA cellular modules are versatile solutions offering voice and/or data communication over diverse radio access technologies in the same miniature SARA LGA form factor (26 x 16 mm) that allows seamless drop-in migration between the two SARA-G3 and SARA-U2 series and easy migration to u-blox LISA-U series GSM/EGPRS/HSPA+ modules, LISA-C2 series CDMA modules, TOBY-L1 series LTE modules and to TOBY-L2 series GSM/EGPRS/DC-HSPA+/LTE modules. SARA-G350 and SARA-G340 are respectively quad-band and dual-band full feature GSM/GPRS cellular modules with a comprehensive feature set including an extensive set of internet protocols and access to u-blox GNSS positioning chips and modules, with embedded A-GPS (AssistNow Online and AssistNow Offline) functionality. SARA-G310 and SARA-G300 are respectively quad-band and dual-band GSM/GPRS cellular modules targeted for high volume cost sensitive applications, providing GSM/GPRS functionalities with a reduced set of additional features to minimize the customer’s total cost of ownership. SARA-U2 series include variants supporting band combination for North America and band combination for Europe, Asia and other countries. For each combination, a complete UMTS/GSM variant and a cost-saving UMTS-only variant are available. All SARA-U2 series modules provide a rich feature set including an extensive set of internet protocols, dual-stack IPv4 / IPv6 and access to u-blox GNSS positioning chips and modules, with embedded A-GPS (AssistNow Online and AssistNow Offline) functionality. Table 1 describes a summary of interfaces and features provided by SARA-G3 and SARA-U2 series modules. Module Data rate Bands Interfaces Audio Functions 3G Up-Link [Mb/s] 3G Down-Link [Mb/s] 2G Up-Link [kb/s] 2G Down-Link [kb/s] 3G bands [MHz] 2G bands [MHz] UART SPI USB DDC (I2C) GPIO Analog audio Digital audio over USB Digital audio over I2S Network indication Antenna supervisor Jamming detection Embedded TCP / UDP Embedded HTTP, FTP Embedded SSL / TLS GNSS via Modem AssistNow Software CellLocate FW update via serial eCall / ERA-GLONASS Low power idle-mode ATEX certification Dual stack IPv4/IPv6 SARA-G300 42.8 85.6 900/1800 2 • E SARA-G310 42.8 85.6 4-band 2 • E SARA-G340 42.8 85.6 900/1800 2 1 4 1 1 • • • • • • • • • • • SARA-G350 42.8 85.6 4-band 2 1 4 1 1 • • • • • • • • • • • SARA-G350 ATEX 42.8 85.6 4-band 2 1 4 1 1 • • • • • • • • • • • • SARA-U260 5.76 7.2 85.6 236.8 850/1900 850/1900 1 1 1 9 F 1 • • • • • • • • • • • • SARA-U270 5.76 7.2 85.6 236.8 900/2100 900/1800 1 1 1 9 F 1 • • • • • • • • • • • • • SARA-U280 5.76 7.2 850/1900 1 1 1 9 F 1 • • • • • • • • • • • • SARA-U290 5.76 7.2 900/2100 1 1 1 9 F 1 • • • • • • • • • • • • • E = 32 kHz signal at EXT32K input pin is required for low power idle-mode F = not supported by initial FW release Table 1: SARA-G3 series1 and SARA-U2 series2 features summary 1 SARA-G350 ATEX modules provide the same feature set of the SARA-G350 modules plus the certification for use in potentially explosive atmospheres. Unless otherwise specified, SARA-G350 refers to all SARA-G350 ATEX modules and SARA-G350 modules. 2 SARA-U290 modules include ‘00’ and ‘60’ FW versions: SARA-U290-60S is approved and locked for SoftBank Japanese network operator.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 9 of 188 Table 2 reports a summary of 2G cellular characteristics of SARA-G3 and SARA-U2 series modules. Item SARA-U260 SARA-U270 SARA-G300 / SARA-G340 SARA-G310 / SARA-G350 Protocol stack 3GPP Release 7 3GPP Release 7 3GPP Release 99 3GPP Release 99 MS class Class B3 Class B3 Class B3 Class B3 Bands4 GSM 850 MHz PCS 1900 MHz E-GSM 900 MHz DCS 1800 MHz E-GSM 900 MHz DCS 1800 MHz GSM 850 MHz E-GSM 900 MHz DCS 1800 MHz PCS 1900 MHz Power class Class 4 (33 dBm) for 850 band Class 1 (30 dBm) for 1900 band Class 4 (33 dBm) for 900 band Class 1 (30 dBm) for 1800 band Class 4 (33 dBm) for 900 band Class 1 (30 dBm) for 1800 band Class 4 (33 dBm) for 850/900 bands Class 1 (30 dBm) for 1800/1900 bands PS data rate5 GPRS multi-slot class 126 CS 1-4, 85.6 kb/s DL CS 1-4, 85.6 kb/s UL EDGE multi-slot class 126 MCS 1-9, 236.8 kb/s DL MCS 1-4, 70.4 kb/s UL GPRS multi-slot class 126 CS 1-4, 85.6 kb/s DL CS 1-4, 85.6 kb/s UL EDGE multi-slot class 126 MCS 1-9, 236.8 kb/s DL MCS 1-4, 70.4 kb/s UL GPRS multi-slot class 107 CS 1-4, 85.6 kb/s DL CS 1-4, 42.8 kb/s UL5 GPRS multi-slot class 107 CS 1-4, 85.6 kb/s DL CS 1-4, 42.8 kb/s UL CS data rate5 Up to 9.6 kb/s DL/UL Transparent mode Non transparent mode Up to 9.6 kb/s DL/UL Transparent mode Non transparent mode Up to 9.6 kb/s DL/UL Transparent mode Non transparent mode Up to 9.6 kb/s DL/UL Transparent mode Non transparent mode Table 2: SARA-G3 series and SARA-U2 series 2G characteristics summary Table 3 reports a summary of 3G cellular characteristics of SARA-U2 series modules. Item SARA-U260 SARA-U270 SARA-U280 SARA-U290 Protocol stack 3GPP Release 7 3GPP Release 7 3GPP Release 7 3GPP Release 7 UE class Class A8 Class A8 Class A8 Class A8 Bands Band V (850 MHz) Band II (1900 MHz) Band VIII (900 MHz) Band I (2100 MHz) Band V (850 MHz) Band II (1900 MHz) Band VIII (900 MHz) Band I (2100 MHz) Power class Class 3 (24 dBm) for all bands Class 3 (24 dBm) for all bands Class 3 (24 dBm) for all bands Class 3 (24 dBm) for all bands PS data rate5 HSUPA category 6 5.76 Mb/s UL HSDPA category 8 7.2 Mb/s DL HSUPA category 6 5.76 Mb/s UL HSDPA category 8 7.2 Mb/s DL HSUPA category 6 5.76 Mb/s UL HSDPA category 8 7.2 Mb/s DL HSUPA category 6 5.76 Mb/s UL HSDPA category 8 7.2 Mb/s DL CS data rate5 Up to 64 kb/s DL/UL Up to 64 kb/s DL/UL Up to 64 kb/s DL/UL Up to 64 kb/s DL/UL Table 3: SARA-U2 series 3G characteristics summary 3 Device can be attached to both GPRS and GSM services (i.e. Packet Switch and Circuit Switch mode) using one service at a time. 4 The 2G 850 / 1900 MHz and 3G 850 / 1900 MHz bands are mainly operative in America. The 2G 900 / 1800 MHz and 3G 900 / 2100 MHz bands are mainly operative in Europe, Asia and other countries. 5 The maximum bit rate of the module depends on the actual network environmental conditions and settings. 6 GPRS/EDGE multi-slot class 12 implies a maximum of 4 slots in DL (reception) and 4 slots in UL (transmission) with 5 slots in total. 7 GPRS multi-slot class 10 implies a maximum of 4 slots in DL (reception) and 2 slots in UL (transmission) with 5 slots in total. 8 Device can work simultaneously in Packet Switch and Circuit Switch mode: voice calls are possible while the data connection is active without any interruption in service.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 10 of 188 1.2 Architecture Figure 1 summarizes the architecture of SARA-G300 and SARA-G310 modules, while Figure 2 summarizes the architecture of SARA-G340 and SARA-G350 modules, describing the internal blocks of the modules, consisting of the RF, Baseband and Power Management main sections, and the available interfaces. MemoryV_BCKP (RTC)V_INT (I/O)32 kHz26 MHzRF TransceiverPowerManagementANT SAWFilterSwitchVCC (Supply)32 kHzAuxiliary UARTSIMUARTPower-OnResetCellularBaseBandProcessorPA Figure 1: SARA-G300 and SARA-G310 modules block diagram MemoryV_BCKP (RTC)V_INT (I/O)26 MHz 32.768 kHzRF TransceiverPowerManagementCellularBaseBandProcessorANT SAWFilterSwitchPAVCC (Supply)Auxiliary UARTDDC (for GNSS)SIM Card DetectionSIMUARTPower-OnResetDigital AudioAnalog AudioGPIOAntenna Detection Figure 2: SARA-G340 and SARA-G350 modules block diagram

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 11 of 188 Figure 3 summarizes the architecture of SARA-U260 and SARA-U270 modules, while Figure 4 summarizes the architecture of SARA-U280 and SARA-U290 modules, describing the internal blocks of the modules, consisting of the RF, Baseband and Power Management main sections, and the available interfaces. MemoryV_BCKP (RTC)V_INT (I/O)RF TransceiverPowerManagementCellularBaseBandProcessorANTVCC (Supply)USBDDC (I2C)SIM card detectionSIMUARTPower-OnResetDigital audio (I2S)GPIOAntenna detection3G PA26 MHzDuplexerFilterSwitch2G PALNA32.768 kHz Figure 3: SARA-U260 and SARA-U270 modules block diagram MemoryV_BCKP (RTC)V_INT (I/O)RF TransceiverPowerManagementCellularBaseBandProcessorANTVCC (Supply)USBDDC (I2C)SIM card detectionSIMUARTPower-OnResetDigital audio (I2S)GPIOAntenna detection3G PA26 MHzDuplexerFilterSwitchLNA32.768 kHz Figure 4: SARA-U280 and SARA-U290 modules block diagram

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 12 of 188 1.2.1 Internal blocks SARA-G3 and SARA-U2 series modules internally consist of the RF, Baseband and Power Management sections here described with more details than the simplified block diagrams of Figure 1, Figure 2, Figure 3 and Figure 4. RF section The RF section is composed of the following main elements:  2G / 3G RF transceiver performing modulation, up-conversion of the baseband I/Q signals, down-conversion and demodulation of the RF received signals. The RF transceiver includes: Constant gain direct conversion receiver with integrated LNAs Highly linear RF quadrature GMSK demodulator Digital Sigma-Delta transmitter GMSK modulator Fractional-N Sigma-Delta RF synthesizer 3.8 GHz VCO Digital controlled crystal oscillator  2G / 3G Power Amplifier, which amplifies the signals modulated by the RF transceiver  RF switch, which connects the antenna input/output pin (ANT) of the module to the suitable RX/TX path  RX diplexer SAW (band pass) filters  26 MHz crystal, connected to the digital controlled crystal oscillator to perform the clock reference in active-mode or connected-mode Baseband and Power Management section The Baseband and Power Management section is composed of the following main elements:  Baseband processor, a mixed signal ASIC which integrates: Microprocessor for controller functions DSP core for 2G / 3G Layer 1 and audio processing Dedicated peripheral blocks for parallel control of the digital interfaces Audio analog front-end  Memory system in a multi-chip package integrating two devices: NOR flash non-volatile memory RAM volatile memory  Voltage regulators to derive all the system supply voltages from the module supply VCC  Circuit for the RTC clock reference in low power idle-mode: SARA-G340, SARA-G350 and SARA-U2 series modules are equipped with an internal 32.768 kHz crystal connected to the oscillator of the RTC (Real Time Clock) block that gives the RTC clock reference needed to provide the RTC functions as well as to reach the very low power idle-mode (with power saving configuration enabled by the AT+UPSV command). SARA-G300 and SARA-G310 modules are not equipped with an internal 32.768 kHz crystal: a proper 32 kHz signal must be provided at the EXT32K input pin of the modules to give the RTC clock reference and to provide the RTC functions as well as to reach the very low power idle-mode (with power saving configuration enabled by AT+UPSV). The 32K_OUT output pin of SARA-G300 and SARA-G310 provides a 32 kHz reference signal suitable only to feed the EXT32K input pin, furnishes the reference clock for the RTC, and allows low power idle-mode and RTC functions support with modules switched on.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 13 of 188 1.3 Pin-out Table 4 lists the pin-out of the SARA-G3 and SARA-U2 series modules, with pins grouped by function. Function Pin Name Module Pin No I/O Description Remarks Power VCC All 51, 52, 53 I Module supply input VCC pins are internally connected each other. VCC supply circuit affects the RF performance and compliance of the device integrating the module with applicable required certification schemes. See section 1.5.1 for functional description and requirements for the VCC module supply. See section 2.2.1 for external circuit design-in. GND All 1, 3, 5, 14, 20-22, 30, 32, 43, 50, 54, 55, 57-61, 63-96 N/A Ground GND pins are internally connected each other. External ground connection affects the RF and thermal performance of the device. See section 1.5.1 for functional description. See section 2.2.1 for external circuit design-in. V_BCKP All 2 I/O Real Time Clock supply input/output V_BCKP = 2.3 V (typical) on SARA-G3 series. V_BCKP = 1.8 V (typical) on SARA-U2 series. V_BCKP is generated by internal low power linear regulator when valid VCC supply is present. See section 1.5.2 for functional description. See section 2.2.2 for external circuit design-in. V_INT All 4 O Generic Digital Interfaces supply output V_INT = 1.8 V (typical), generated by internal DC/DC regulator when the module is switched on. See section 1.5.3 for functional description. See section 2.2.3 for external circuit design-in. System PWR_ON All 15 I Power-on input High input impedance: input voltage level has to be properly fixed, e.g. adding external pull-up. See section 1.6.1 for functional description. See section 2.3.1 for external circuit design-in. RESET_N All 18 I External reset input A series Schottky diode is integrated in the module as protection, and then an internal 10 k pull-up resistor to V_INT is provided. See section 1.6.3 for functional description. See section 2.3.2 for external circuit design-in. EXT32K SARA-G300 SARA-G310 31 I 32 kHz input Input for RTC reference clock, needed to enter the low power idle-mode and provide RTC functions. See section 1.6.4 for functional description. See section 2.3.3 for external circuit design-in. 32K_OUT SARA-G300 SARA-G310 24 O 32 kHz output 32 kHz output suitable only to feed the EXT32K input giving the RTC reference clock, allowing low power idle-mode and RTC functions support. See section 1.6.5 for functional description. See section 2.3.3 for external circuit design-in. Antenna ANT All 56 I/O RF input/output for antenna 50  nominal characteristic impedance. Antenna circuit affects the RF performance and compliance of the device integrating the module with applicable required certification schemes. See section 1.7 for functional description and requirements for the antenna RF interface. See section 2.4 for external circuit design-in. ANT_DET SARA-G340 SARA-G350 SARA-U2 62 I Input for antenna detection ADC input for antenna detection function. See section 1.7.2 for functional description. See section 2.4.2 for external circuit design-in.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 14 of 188 Function Pin Name Module Pin No I/O Description Remarks SIM VSIM All 41 O SIM supply output VSIM = 1.80 V typ. or 2.85 V typ. automatically generated according to the connected SIM type. See section 1.8 for functional description. See section 2.5 for external circuit design-in. SIM_IO All 39 I/O SIM data Data input/output for 1.8 V / 3 V SIM Internal 4.7 k pull-up to VSIM. See section 1.8 for functional description. See section 2.5 for external circuit design-in. SIM_CLK All 38 O SIM clock 3.25 MHz clock output for 1.8 V / 3 V SIM See section 1.8 for functional description. See section 2.5 for external circuit design-in. SIM_RST All 40 O SIM reset Reset output for 1.8 V / 3 V SIM See section 1.8 for functional description. See section 2.5 for external circuit design-in. SIM_DET All 42 I / I/O SIM detection / GPIO 1.8 V input for SIM presence detection function. Pin configurable also as GPIO on SARA-U2 series. See section 1.8.2 for functional description. See section 2.5 for external circuit design-in. UART RXD All 13 O UART data output 1.8 V output, Circuit 104 (RXD) in ITU-T V.24, for AT, data, FOAT on SARA-G3 series modules, for AT, data, FOAT, FW upgrade via EasyFlash tool and diagnostic on SARA-U2 series modules. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. TXD All 12 I UART data input 1.8 V input, Circuit 103 (TXD) in ITU-T V.24, for AT, data, FOAT on SARA-G3 series modules, for AT, data, FOAT, FW upgrade via EasyFlash tool and diagnostic on SARA-U2 series modules. Internal active pull-up to V_INT. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. CTS All 11 O UART clear to send output 1.8 V output, Circuit 106 (CTS) in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. RTS All 10 I UART ready to send input 1.8 V input, Circuit 105 (RTS) in ITU-T V.24. Internal active pull-up to V_INT. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. DSR All 6 O UART data set ready output 1.8 V output, Circuit 107 (DSR) in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. RI All 7 O UART ring indicator output 1.8 V output, Circuit 125 (RI) in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. DTR All 9 I UART data terminal ready input 1.8 V input, Circuit 108/2 (DTR) in ITU-T V.24. Internal active pull-up to V_INT. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in. DCD All 8 O UART data carrier detect output 1.8 V input, Circuit 109 (DCD) in ITU-T V.24. See section 1.9.1 for functional description. See section 2.6.1 for external circuit design-in.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 15 of 188 Function Pin Name Module Pin No I/O Description Remarks Auxiliary UART RXD_AUX SARA-G3 28 O Auxiliary UART data output 1.8 V output, Circuit 104 (RXD) in ITU-T V.24, for FW upgrade via EasyFlash tool and diagnostic. Access by external test-point is recommended. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in. TXD_AUX SARA-G3 29 I Auxiliary UART data input 1.8 V input, Circuit 103 (TXD) in ITU-T V.24, for FW upgrade via EasyFlash tool and diagnostic. Access by external test-point is recommended. Internal active pull-up to V_INT. See section 1.9.2 for functional description. See section 2.6.2 for external circuit design-in. USB VUSB_DET SARA-U2 17 I USB detect input High-Speed USB 2.0 interface input for VBUS (5 V typical) USB supply sense. USB available for AT, data, FOAT, FW upgrade via EasyFlash tool and diagnostic. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in. USB_D- SARA-U2 28 I/O USB Data Line D- High-Speed USB 2.0 interface data line for AT, data, FOAT, FW upgrade via EasyFlash tool and diagnostic. 90  nominal differential impedance. Pull-up, pull-down and series resistors as required by USB 2.0 specifications [14] are part of the USB pin driver and need not be provided externally. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in. USB_D+ SARA-U2 29 I/O USB Data Line D+ High-Speed USB 2.0 interface data line for AT, data, FOAT, FW upgrade via EasyFlash tool and diagnostic. 90  nominal differential impedance. Pull-up, pull-down and series resistors as required by USB 2.0 specifications [14] are part of the USB pin driver and need not be provided externally. See section 1.9.3 for functional description. See section 2.6.3 for external circuit design-in. DDC SCL SARA-G340 SARA-G350 SARA-U2 27 O I2C bus clock line 1.8 V open drain, for the communication with the u-blox positioning modules / chips. Communication with other external I2C-slave devices as an audio codec is additionally supported by SARA-U2 series. External pull-up required. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in. SDA SARA-G340 SARA-G350 SARA-U2 26 I/O I2C bus data line 1.8 V open drain, for the communication with u-blox positioning modules / chips. Communication with other external I2C-slave devices as an audio codec is additionally supported by SARA-U2 series. External pull-up required. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design-in.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 16 of 188 Function Pin Name Module Pin No I/O Description Remarks Analog Audio MIC_BIAS SARA-G340 SARA-G350 46 O Microphone supply output Supply output (2.2 V typ) for external microphone. See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in. MIC_GND SARA-G340 SARA-G350 47 I Microphone analog reference Local ground for the external microphone (reference for the analog audio uplink path). See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in. MIC_N SARA-G340 SARA-G350 48 I Differential analog audio input (negative) Differential analog audio signal input (negative) shared for all the analog uplink path modes: handset, headset, hands-free mode. No internal DC blocking capacitor. See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in. MIC_P SARA-G340 SARA-G350 49 I Differential analog audio input (positive) Differential analog audio signal input (positive) shared for all the analog uplink path modes: handset, headset, hands-free mode. No internal DC blocking capacitor. See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in. SPK_P SARA-G340 SARA-G350 44 O Differential analog audio output (positive) Differential analog audio signal output (positive) shared for all the analog downlink path modes: earpiece, headset and loudspeaker mode. See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in. SPK_N SARA-G340 SARA-G350 45 O Differential analog audio output (negative) Differential analog audio signal output (negative) shared for all the analog downlink path modes: earpiece, headset and loudspeaker mode. See section 1.10.1 for functional description. See section 2.7.1 for external circuit design-in. Digital Audio I2S_CLK SARA-G340 SARA-G350 SARA-U2 36 O / I/O I2S clock / GPIO 1.8 V serial clock for PCM / normal I2S modes. Pin configurable also as GPIO on SARA-U2 series. See section 1.10.2 for functional description. See section 2.7.2 for external circuit design-in. I2S_RXD SARA-G340 SARA-G350 SARA-U2 37 I / I/O I2S receive data / GPIO 1.8 V data input for PCM / normal I2S modes. Pin configurable also as GPIO on SARA-U2 series. Internal active pull-down to GND. See section 1.10.2 for functional description. See section 2.7.2 for external circuit design-in. I2S_TXD SARA-G340 SARA-G350 SARA-U2 35 O / I/O I2S transmit data / GPIO 1.8 V data output for PCM / normal I2S modes. Pin configurable also as GPIO on SARA-U2 series. See section 1.10.2 for functional description. See section 2.7.2 for external circuit design-in. I2S_WA SARA-G340 SARA-G350 SARA-U2 34 O / I/O I2S word alignment / GPIO 1.8 V word alignment for PCM / normal I2S modes Pin configurable also as GPIO on SARA-U2 series. See section 1.10.2 for functional description. See section 2.7.2 for external circuit design-in. CODEC_CLK SARA-U2 19 O Clock output 1.8 V master clock output for external audio codec See section 1.10.2 for functional description. See section 2.7.2 for external circuit design-in

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 17 of 188 Function Pin Name Module Pin No I/O Description Remarks GPIO GPIO1 SARA-G340 SARA-G350 SARA-U2 16 I/O GPIO 1.8 V GPIO by default configured as pin disabled. See section 1.11 for functional description. See section 2.8 for external circuit design-in. GPIO2 SARA-G340 SARA-G350 SARA-U2 23 I/O GPIO 1.8 V GPIO by default configured to provide the custom GNSS supply enable function. See section 1.11 for functional description. See section 2.8 for external circuit design-in. GPIO3 SARA-G340 SARA-G350 SARA-U2 24 I/O GPIO 1.8 V GPIO by default configured to provide the custom GNSS data ready function. See section 1.11 for functional description. See section 2.8 for external circuit design-in. GPIO4 SARA-G340 SARA-G350 SARA-U2 25 I/O GPIO 1.8 V GPIO by default configured to provide the custom GNSS RTC sharing function. See section 1.11 for functional description. See section 2.8 for external circuit design-in. Reserved RSVD All 33 N/A RESERVED pin This pin must be connected to ground. See section 2.9 RSVD SARA-G3 17, 19 N/A RESERVED pin Leave unconnected. See section 2.9 RSVD SARA-G340 SARA-G350 SARA-U2 31 N/A RESERVED pin Internally not connected. Leave unconnected. See section 2.9 RSVD SARA-G300 SARA-G310 16, 23, 25-27, 34-37 N/A RESERVED pin Pin disabled. Leave unconnected. See section 2.9 RSVD SARA-G300 SARA-G310 SARA-U2 44-49 N/A RESERVED pin Leave unconnected. See section 2.9 RSVD SARA-G300 SARA-G310 62 N/A RESERVED pin Leave unconnected. See section 2.9 Table 4: SARA-G3 and SARA-U2 series modules pin definition, grouped by function

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 18 of 188 1.4 Operating modes SARA-G3 modules have several operating modes. The operating modes defined in Table 5 and described in detail in Table 6 provide general guidelines for operation. General Status Operating Mode Definition Power-down Not-Powered Mode VCC supply not present or below operating range: module is switched off. Power-Off Mode VCC supply within operating range and module is switched off. Normal Operation Idle-Mode Module processor core runs with 32 kHz reference, that is generated by:  The internal 32 kHz oscillator (SARA-G340, SARA-G350 and SARA-U2 series)  The 32 kHz signal provided at the EXT32K pin (SARA-G300 and SARA-G310) Active-Mode Module processor core runs with 26 MHz reference generated by the internal oscillator. Connected-Mode Voice or data call enabled and processor core runs with 26 MHz reference. Table 5: Module operating modes definition Operating Mode Description Transition between operating modes Not-Powered Module is switched off. Application interfaces are not accessible. Internal RTC operates on SARA-G340/G350, SARA-U2 if a valid voltage is applied to V_BCKP. Additionally, a proper external 32 kHz signal must be fed to EXT32K on SARA-G300/G310 modules to let internal RTC timer running. When VCC supply is removed, the module enters not-powered mode. When in not-powered mode, the modules cannot be switched on by PWR_ON, RESET_N or RTC alarm. When in not-powered mode, the modules can be switched on applying VCC supply (see 2.3.1) so that the module switches from not-powered to active-mode. Power-Off Module is switched off: normal shutdown by an appropriate power-off event (see 1.6.2). Application interfaces are not accessible. Internal RTC operates on SARA-G340/G350, SARA-U2 as V_BCKP is internally generated. A proper external 32 kHz signal must be fed to the EXT32K pin on SARA-G300/G310 to let RTC timer running that otherwise is not in operation. When the module is switched off by an appropriate power-off event (see 1.6.2), the module enters power-off mode from active-mode. When in power-off mode, the modules can be switched on by PWR_ON, RESET_N or RTC alarm (see 2.3.1): the module switches from power-off to active-mode. When VCC supply is removed, the module switches from power-off mode to not-powered mode. Idle The module is not ready to communicate with an external device by means of the application interfaces as configured to reduce consumption. The module automatically enters idle-mode whenever possible if power saving is enabled by the AT+UPSV command (see u-blox AT Commands Manual [3]), reducing power consumption (see section 1.5.1.4). The CTS output line indicates when the UART interface is disabled/enabled due to the module idle/active-mode according to power saving and HW flow control settings (see 1.9.1.3, 1.9.1.4). Power saving configuration is not enabled by default: it can be enabled by AT+UPSV (see the u-blox AT Commands Manual [3]). A proper 32 kHz signal must be fed to the EXT32K pin of SARA-G300/G310 modules to let idle-mode that otherwise cannot be reached (this is not needed for the other SARA-G3 and SARA-U2 series modules). The module automatically switches from active-mode to idle-mode whenever possible if power saving is enabled (see sections 1.5.1.4, 1.9.1.4 and to the u-blox AT Commands Manual [3], AT+UPSV). The module wakes up from idle to active mode in the following events:  Automatic periodic monitoring of the paging channel for the paging block reception according to network conditions (see 1.5.1.4, 1.9.1.4)  Automatic periodic enable of the UART interface to receive and send data, if AT+UPSV=1 power saving is set (see 1.9.1.4)  RTC alarm occurs (see u-blox AT Commands Manual [3], +CALA)  Data received on UART interface, according to HW flow control (AT&K) and power saving (AT+UPSV) settings (see 1.9.1.4)  RTS input line set to the ON state by the DTE, if HW flow control is disabled by AT&K3 and AT+UPSV=2 is set (see 1.9.1.4)  DTR input line set to the ON state by the DTE, if AT+UPSV=3 power saving is set (see 1.9.1.4)  USB detection, applying 5 V (typ.) to VUSB_DET input (see 1.9.3)  The connected USB host forces a remote wakeup of the module as USB device (see 1.9.3)  GNSS data ready: when the GPIO3 pin is informed by the connected u-blox GNSS receiver that it is ready to send data over the DDC (I2C) communication interface (see 1.11, 1.9.4)

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 19 of 188 Operating Mode Description Transition between operating modes Active The module is ready to communicate with an external device by means of the application interfaces unless power saving configuration is enabled by the AT+UPSV command (see sections 1.5.1.4, 1.9.1.4 and to the u-blox AT Commands Manual [3]). When the module is switched on by an appropriate power-on event (see 2.3.1), the module enters active-mode from not-powered or power-off mode. If power saving configuration is enabled by the AT+UPSV command, the module automatically switches from active to idle-mode whenever possible and the module wakes up from idle to active-mode in the events listed above (see idle to active transition description). When a voice call or a data call is initiated, the module switches from active-mode to connected-mode. Connected A voice call or a data call is in progress. The module is ready to communicate with an external device by means of the application interfaces unless power saving configuration is enabled by the AT+UPSV command (see sections 1.5.1.4, 1.9.1.4 and the u-blox AT Commands Manual [3]). When a voice call or a data call is initiated, the module enters connected-mode from active-mode. When a voice call or a data call is terminated, the module returns to the active-mode. Table 6: Module operating modes description Figure 5 describes the transition between the different operating modes. Switch ON:•Apply VCCIf power saving is enabled and there is no activity for a defined time intervalAny wake up event described in the module operating modes summary table aboveIncoming/outgoing call or other dedicated device network communicationNo RF Tx/Rx in progress, Call terminated, Communication droppedRemove VCCSwitch ON:•PWR_ON•RTC alarm•RESET_N (SARA-U2)Not poweredPower offActiveConnected IdleSwitch OFF:•AT+CPWROFF•PWR_ON (SARA-U2) Figure 5: Operating modes transition

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 20 of 188 1.5 Supply interfaces 1.5.1 Module supply input (VCC) The modules must be supplied via the three VCC pins that represent the module power supply input. The VCC pins are internally connected to the RF power amplifier and to the integrated Power Management Unit: all supply voltages needed by the module are generated from the VCC supply by integrated voltage regulators, including V_BCKP Real Time Clock supply, V_INT digital interfaces supply and VSIM SIM card supply. During operation, the current drawn by the SARA-G3 and SARA-U2 series modules through the VCC pins can vary by several orders of magnitude. This ranges from the high peak of current consumption during GSM transmitting bursts at maximum power level in connected-mode (as described in section 1.5.1.2), to the low current consumption during low power idle-mode with power saving enabled (as described in section 1.5.1.4). 1.5.1.1 VCC supply requirements Table 7 summarizes the requirements for the VCC module supply. See section 2.2.1 for all the suggestions to properly design a VCC supply circuit compliant to the requirements listed in Table 7. VCC supply circuit affects the RF compliance of the device integrating SARA-G3 and SARA-U2 series modules with applicable required certification schemes as well as antenna circuit design. Compliance is guaranteed if the VCC requirements summarized in the Table 7 are fulfilled. For the additional specific requirement for SARA-G350 ATEX modules integration in potentially explosive atmospheres applications, see section 2.14. Item Requirement Remark VCC nominal voltage Within VCC normal operating range: 3.35 V min. / 4.50 V max for SARA-G3 series 3.30 V min. / 4.40 V max for SARA-U2 series The module cannot be switched on if VCC voltage value is below the normal operating range minimum limit. Ensure that the input voltage at VCC pins is above the minimum limit of the normal operating range for at least more than 3 s after the module switch-on. VCC voltage during normal operation Within VCC extended operating range: 3.00 V min. / 4.50 V max for SARA-G3 series 3.10 V min. / 4.50 V max for SARA-U2 series The module may switch off when VCC voltage drops below the extended operating range minimum limit. Operation above extended operating range limit is not recommended and may affect device reliability. VCC average current Considerably withstand maximum average current consumption value in connected-mode conditions specified in the SARA-G3 series Data Sheet [1] and in the SARA-U2 series Data Sheet [2]. The maximum average current consumption can be greater than the specified value according to the actual antenna mismatching, temperature and VCC voltage. See 1.5.1.2, 1.5.1.3 for connected-mode current profiles. VCC peak current Withstand the maximum peak current consumption specified in the SARA-G3 series Data Sheet [1] and in the SARA-U2 series Data Sheet [2]. The specified maximum peak of current consumption occurs during GSM single transmit slot in 850/900 MHz connected-mode, in case of mismatched antenna. See 1.5.1.2 for 2G connected-mode current profiles. VCC voltage drop during 2G Tx slots Lower than 400 mV VCC voltage drop directly affects the RF compliance with applicable certification schemes. Figure 7 describes VCC voltage drop during Tx slots. VCC voltage ripple during 2G/3G Tx Lower than 30 mVpp if fripple ≤ 200 kHz Lower than 10 mVpp if 200 kHz < fripple ≤ 400 kHz Lower than 2 mVpp if fripple > 400 kHz VCC voltage ripple directly affects the RF compliance with applicable certification schemes. Figure 7 describes VCC voltage ripple during Tx slots. VCC under/over-shoot at start/end of Tx slots Absent or at least minimized VCC under/over-shoot directly affects the RF compliance with applicable certification schemes. Figure 7 describes VCC voltage under/over-shoot. Table 7: Summary of VCC supply requirements

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 29 of 188 1.5.2 RTC supply input/output (V_BCKP) The V_BCKP pin of SARA-G3 and SARA-U2 series modules connects the supply for the Real Time Clock (RTC) and Power-On internal logic. This supply domain is internally generated by a linear LDO regulator integrated in the Power Management Unit, as described in Figure 15. The output of this linear regulator is always enabled when the main voltage supply provided to the module through the VCC pins is within the valid operating range, with the module switched off or switched on. Baseband Processor51VCC52VCC53VCC2V_BCKPLinear LDO RTCPower ManagementSARA-G340 / SARA-G350SARA-U2 series32 kHzBaseband Processor51VCC52VCC53VCC2V_BCKPLinear LDO RTCPower ManagementSARA-G300 / SARA-G31032 kHz31EXT32K Figure 15: RTC supply input/output (V_BCKP) and 32 kHz RTC timing reference clock simplified block diagram The RTC provides the module time reference (date and time) that is used to set the wake-up interval during the idle-mode periods between network paging, and is able to make available the programmable alarm functions. The RTC functions are available also in power-down mode when the V_BCKP voltage is within its valid range (specified in the “Input characteristics of Supply/Power pins” table in the SARA-G3 series Data Sheet [1] and SARA-U2 series Data Sheet [2]) and, for SARA-G300 / SARA-G310 modules only, when their EXT32K input pin is fed by an external 32.768 kHz signal with proper characteristics (specified in the “EXT32K pin characteristics” table in SARA-G3 series Data Sheet [1]). See the u-blox AT Commands Manual [3] for more details. The RTC can be supplied from an external back-up battery through the V_BCKP, when the main voltage supply is not provided to the module through VCC. This lets the time reference (date and time) run until the V_BCKP voltage is within its valid range, even when the main supply is not provided to the module. The RTC oscillator does not necessarily stop operation (i.e. the RTC counting does not necessarily stop) when V_BCKP voltage value drops below the specified operating range minimum limit (1.00 V): the RTC value read after a system restart could be not reliable, as explained in Table 8. V_BCKP voltage value RTC value reliability Notes 1.00 V < V_BCKP < 2.40 V RTC oscillator does not stop operation RTC value read after a restart of the system is reliable V_BCKP within operating range 0.05 V < V_BCKP < 1.00 V RTC oscillator does not necessarily stop operation RTC value read after a restart of the system is not reliable V_BCKP below operating range 0.00 V < V_BCKP < 0.05 V RTC oscillator stops operation RTC value read after a restart of the system is reliable V_BCKP below operating range Table 8: RTC value reliability as function of V_BCKP voltage value Consider that the module cannot switch on if a valid voltage is not present on VCC even when the RTC is supplied through V_BCKP (meaning that VCC is mandatory to switch on the module).

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 30 of 188 The RTC has very low power consumption, but is highly temperature dependent. For example at 25 °C, with the V_BCKP voltage equal to the typical output value, the current consumption is approximately 2 µA (see the “Input characteristics of Supply/Power pins” table in the SARA-G3 series Data Sheet [1] and SARA-U2 series Data Sheet [2] for the detailed specification), whereas at 70 °C and an equal voltage the current consumption increases to 5-10 µA. If V_BCKP is left unconnected and the module main voltage supply is removed from VCC, the RTC is supplied from the bypass capacitor mounted inside the module. However, this capacitor is not able to provide a long buffering time: within few milliseconds the voltage on V_BCKP will go below the valid range (1 V min). This has no impact on cellular connectivity, as all the module functionalities do not rely on date and time setting. 1.5.3 Generic digital interfaces supply output (V_INT) The same 1.8 V voltage domain used internally to supply the generic digital interfaces of SARA-G3 and SARA-U2 series modules is also available on the V_INT supply output pin, as described in Figure 16. Baseband Processor51VCC52VCC53VCC4V_INTSwitchingStep-DownDigital I/O InterfacesPower ManagementSARA-G3 / SARA-U2 series Figure 16: SARA-G3 and SARA-U2 series interfaces supply output (V_INT) simplified block diagram The internal regulator that generates the V_INT supply is a switching step-down converter that is directly supplied from VCC. The voltage regulator output is set to 1.8 V (typical) when the module is switched on and it is disabled when the module is switched off. The switching regulator operates in Pulse Width Modulation (PWM) for greater efficiency at high output loads when the module is in active-mode or in connected-mode. When the module is in low power idle-mode between paging periods and with power saving configuration enabled by the appropriate AT command, it automatically switches to Pulse Frequency Modulation (PFM) for greater efficiency at low output loads. See the u-blox AT Commands Manual [3], +UPSV command.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 31 of 188 1.6 System function interfaces 1.6.1 Module power-on 1.6.1.1 Switch-on events Table 9 summarizes the possible switch-on events for the SARA-G3 and SARA-U2 series modules. SARA-G3 SARA-U2 From Not-Powered Mode Applying valid VCC supply voltage (i.e. VCC rise edge), ramping from 2.5 V to 3.2 V within 4 ms Applying valid VCC supply voltage (i.e. VCC rise edge), ramping from 2.5 V to 3.2 V within 1 ms From Power-Off Mode Low level on PWR_ON pin for 5 ms min. Low pulse on PWR_ON pin for 50 µs min. / 80 µs max. RTC alarm programmed by AT+CALA command (Not supported by SARA-G300 / SARA-G310) RTC alarm programmed by AT+CALA command RESET_N pin released from low level Table 9: Summary of SARA-G3 and SARA-U2 modules’ switch-on events When the SARA-G3 and SARA-U2 series modules are in the not-powered mode (i.e. switched off with the VCC module supply not applied), they can be switched on by:  Rising edge on the VCC supply input to a valid voltage for modules supply: the modules switch on applying VCC supply starting from a voltage value lower than 2.25 V, providing a fast VCC voltage slope, as it must ramp from 2.5 V to 3.2 V within 4 ms on SARA-G3 modules and within 1 ms on SARA-U2 modules, and reaching a proper nominal VCC voltage value within the normal operating range.  Alternately, the RESET_N pin can be held low during the VCC rising edge, so that the module switches on by releasing the RESET_N pin when the VCC voltage stabilizes at its nominal value within the normal range. The status of the PWR_ON input pin of SARA-G3 and SARA-U2 series modules while applying the VCC module supply is not relevant: during this phase the PWR_ON pin can be set high or low by the external circuit. When the SARA-G3 and SARA-U2 series modules are in the power-off mode (i.e. switched off by means of the AT+CPWROFF command, with valid VCC module supply applied), they can be switched on by:  Low level / pulse on PWR_ON pin, which is normally set high by an external pull-up, for a valid time period. As described in Figure 17, there is no internal pull-up resistor on the PWR_ON pin of the modules: the pin has high input impedance and is weakly pulled high by the internal circuit. Therefore the external circuit must be able to hold the high logic level stable, e.g. providing an external pull-up resistor (for design-in see section 2.3.1). The PWR_ON input voltage thresholds are different from the other generic digital interfaces of the modules: refer to SARA-G3 series Data Sheet [1] and SARA-U2 series Data Sheet [2] for detailed electrical characteristics. Baseband Processor15PWR_ONSARA-G3 / SARA-U2 seriesPower-onPower ManagementPower-on Figure 17: PWR_ON input description The SARA-G340, SARA-G350 and SARA-U2 series can be also switched on from power-off mode by:  RTC alarm pre-programmed by AT+CALA command at specific time (see u-blox AT Commands Manual [3]). The SARA-U2 series modules can be also switched on from power-off mode by:  Low pulse on the RESET_N pin, which is normally set high by an internal pull-up (refer to section 1.6.3 and to the SARA-U2 series Data Sheet [2] for the description of the RESET_N input electrical characteristics).

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 32 of 188 1.6.1.2 Switch-on sequence from not-powered mode Figure 19 shows the modules power-on sequence from the not-powered mode, describing the following phases:  The external supply is applied to the VCC module supply inputs, representing the start-up event.  The status of the PWR_ON input pin while applying the VCC module supply is not relevant: during this phase the PWR_ON pin can be set high or low by the external circuit, but in Figure 19 it is assumed that the PWR_ON line rise suddenly to high logic level due to external pull-up connected to V_BCKP or VCC.  The V_BCKP RTC supply output is suddenly enabled by the module as VCC reaches a valid voltage value.  The RESET_N line of SARA-U2 series rise suddenly to high logic level due to internal pull-up to V_BCKP.  All the generic digital pins of the modules are tri-stated until the switch-on of their supply source (V_INT): any external signal connected to the generic digital pins must be tri-stated or set low at least until the activation of the V_INT supply output to avoid latch-up of circuits and allow a proper boot of the module.  The V_INT generic digital interfaces supply output is enabled by the integrated power management unit.  The RESET_N line of SARA-G3 series rise suddenly to high logic level due to internal pull-up to V_INT.  The internal reset signal is held low by the integrated power management unit: the baseband processor core and all the digital pins of the modules are held in reset state.  When the internal reset signal is released by the integrated power management unit, the processor core starts to configure the digital pins of the modules to each default operational state.  The duration of this pins’ configuration phase differs within generic digital interfaces (3 s typical) and the USB interface due to specific host / device enumeration timings (5 s typical, see section 1.9.3). The host application processor should not send any AT command over the AT interfaces (USB, UART) of the modules until the end of this interfaces’ configuration phase to allow a proper boot of the module.  After the interfaces’ configuration phase, the application can start sending AT commands, and the following starting procedure is suggested to check the effective completion of the module internal boot sequence: send AT and wait for the response with a 30 s timeout, iterate it 4 times without resetting or removing the VCC supply of the module, and then run the application VCCV_BCKPPWR_ONSARA-U2 RESET_NV_INTSARA-G3 RESET_NInternal ResetSystem StateDigital Pins StateInternal Reset → Operational OperationalTristate / Floating OFFONInternal Reset0 ms~35 ms~3 sStart of interface configurationModule interfaces are configuredStart-up event Figure 18: SARA-G3 and SARA-U2 series power-on sequence from not-powered mode The Internal Reset signal is not available on a module pin, but the application can monitor the V_INT pin to sense the start of the power-on sequence. Before the switch-on of the generic digital interface supply source (V_INT) of the module, no voltage driven by an external application should be applied to any generic digital interface of the modules.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 33 of 188 1.6.1.3 Switch-on sequence from power-off mode Figure 19 shows the modules power-on sequence from the power-off mode, describing the following phases:  The external supply is still applied to the VCC inputs as it is assumed that the module has been previously switched off by means of the AT+CPWROFF command: the V_BCKP output is internally enabled as proper VCC is present, the RESET_N of SARA-U2 series is set to high logic level due to internal pull-up to V_BCKP, the PWR_ON is set to high logic level due to external pull-up connected to V_BCKP or VCC.  The PWR_ON input pin is set low for a valid time period, representing the start-up event.  All the generic digital pins of the modules are tri-stated until the switch-on of their supply source (V_INT): any external signal connected to the generic digital pins must be tri-stated or set low at least until the activation of the V_INT supply output to avoid latch-up of circuits and allow a proper boot of the module.  The V_INT generic digital interfaces supply output is enabled by the integrated power management unit.  The RESET_N line of SARA-G3 series rise suddenly to high logic level due to internal pull-up to V_INT.  The internal reset signal is held low by the integrated power management unit: the baseband processor core and all the digital pins of the modules are held in reset state.  When the internal reset signal is released by the integrated power management unit, the processor core starts to configure the digital pins of the modules to each default operational state.  The duration of this pins’ configuration phase differs within generic digital interfaces (3 s typical) and the USB interface due to specific host / device enumeration timings (5 s typical, see section 1.9.3). The host application processor should not send any AT command over the AT interfaces (USB, UART) of the modules until the end of this interfaces’ configuration phase to allow a proper boot of the module.  After the interfaces’ configuration phase, the application can start sending AT commands, and the following starting procedure is suggested to check the effective completion of the module internal boot sequence: send AT and wait for the response with a 30 s timeout, iterate it 4 times without resetting or removing the VCC supply of the module, and then run the application. VCCV_BCKPPWR_ONSARA-U2 RESET_NV_INTSARA-G3 RESET_NInternal ResetSystem StateDigital Pins StateInternal Reset → Operational OperationalTristate / Floating OFFONInternal Reset0 ms~35 ms~3 sStart of interface configurationModule interfaces are configuredStart-up event Figure 19: SARA-G3 and SARA-U2 series power-on sequence from power-off mode The Internal Reset signal is not available on a module pin, but the application can monitor the V_INT pin to sense the start of the power-on sequence. Before the switch-on of the generic digital interface supply source (V_INT) of the module, no voltage driven by an external application should be applied to any generic digital interface of the modules.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 34 of 188 1.6.2 Module power-off 1.6.2.1 Switch-off events The SARA-G3 and SARA-U2 series modules can be properly switched off by:  AT+CPWROFF command (more details in u-blox AT Commands Manual [3]). The SARA-U2 series modules can be properly switched off also by:  Low pulse on the PWR_ON pin, which is normally set high by an external pull-up, for a valid time period (see the SARA-U2 series Data Sheet [2] for the detailed electrical characteristics of the PWR_ON input). In both the cases listed above, the current parameter settings are saved in the module’s non-volatile memory and a proper network detach is performed: these are the correct ways to switch off the modules. An abrupt under-voltage shutdown occurs on SARA-G3 and SARA-U2 series modules when the VCC module supply is removed, but in this case the current parameter settings are not saved in the module’s non-volatile memory and a proper network detach cannot be performed. It is highly recommended to avoid an abrupt removal of the VCC supply during SARA-G3 and SARA-U2 series modules normal operations: the power off procedure must be properly started by the appplication, as by the AT+CPWROFF command, waiting the command response for a proper time period (see u-blox AT Commands Manual [3]), and then a proper VCC supply must be held at least until the end of the modules’ internal power off sequence, which occurs when the generic digital interfaces supply output (V_INT) is switched off by the module. An abrupt hardware shutdown occurs on SARA-U2 modules when a low level is applied to the RESET_N input. In this case, the current parameter settings are not saved in the module’s non-volatile memory and a proper network detach is not performed. It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low level on the RESET_N input pin during module normal operation: the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not reply to a specific AT command after a time period longer than the one defined in the u-blox AT Commands Manual [3]. An over-temperature or an under-temperature shutdown occurs on SARA-G3 and SARA-U2 series modules when the temperature measured within the cellular module reaches the dangerous area, if the optional Smart Temperature Supervisor feature is enabled and configured by the dedicated AT command. For more details see section 1.13.10 and to the u-blox AT Commands Manual [3], +USTS AT command. The Smart Temperature Supervisor feature is not supported by SARA-G300 and SARA-G310.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 35 of 188 1.6.2.2 Switch-off sequence by AT+CPWROFF Figure 20 describes the SARA-G3 and SARA-U2 series modules power-off sequence, properly started sending the AT+CPWROFF command, allowing storage of current parameter settings in the module’s non-volatile memory and a proper network detach, with the following phases:  When the +CPWROFF AT command is sent, the module starts the switch-off routine.  The module replies OK on the AT interface: the switch-off routine is in progress.  At the end of the switch-off routine, all the digital pins are tri-stated and all the internal voltage regulators are turned off, including the generic digital interfaces supply (V_INT), except the RTC supply (V_BCKP).  Then, the module remains in power-off mode as long as a switch on event does not occur (e.g. applying a proper low level to the PWR_ON input, or applying a proper low level to the RESET_N input), and enters not-powered mode if the supply is removed from the VCC pins. VCC V_BCKPPWR_ONSARA-U2 RESET_N V_INTSARA-G3 RESET_N Internal ResetSystem StateDigital Pins State OperationalOFFTristate / FloatingONOperational → TristateAT+CPWROFFsent to the module0 s~2.5 s~5 sOKreplied by the moduleVCC can be removed Figure 20: SARA-G3 and SARA-U2 series power-off sequence description The Internal Reset signal is not available on a module pin, but the application can monitor the V_INT pin to sense the end of the SARA-G3 and SARA-U2 series power-off sequence. The duration of each phase in the SARA-G3 and SARA-U2 series modules’ switch-off routines can largely vary depending on the application / network settings and the concurrent module activities.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 36 of 188 1.6.3 Module reset SARA-G3 and SARA-U2 series modules can be properly reset (rebooted) by:  AT+CFUN command (see the u-blox AT Commands Manual [3] for more details). This command causes an “internal” or “software” reset of the module, which is an asynchronous reset of the module baseband processor. The current parameter settings are saved in the module’s non-volatile memory and a proper network detach is performed: this is the proper way to reset the modules. An abrupt hardware reset occurs on SARA-G3 and SARA-U2 series modules when a low level is applied on the RESET_N input pin for a specific time period. In this case, the current parameter settings are not saved in the module’s non-volatile memory and a proper network detach is not performed. It is highly recommended to avoid an abrupt hardware reset of the module by forcing a low level on the RESET_N input during modules normal operation: the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not provide a reply to a specific AT command after a time period longer than the one defined in the u-blox AT Commands Manual [3]. As described in Figure 21, both the SARA-G3 and SARA-U2 series modules are equipped with an internal pull-up resistor which pulls the line to the high logic level when the RESET_N pin is not forced low from the external. The pull-up is internally biased by V_INT on SARA-G3 modules and is biased by V_BCKP on SARA-U2 modules. A series Schottky diode is mounted inside the SARA-G3 modules, increasing the RESET_N input voltage range. Refer to the SARA-G3 series Data Sheet [1] and the SARA-U2 series Data Sheet [2] for the detailed electrical characteristics of the RESET_N input. Baseband Processor18RESET_NSARA-U2 seriesResetPower ManagementReset10kV_BCKPBaseband Processor18RESET_NSARA-G3 seriesReset10kV_INT Figure 21: RESET_N input description When a low level is applied to the RESET_N input, it causes an “external” or “hardware” reset of the modules, with the following behavior of SARA-G3 and SARA-U2 series modules due to different internal circuits:  SARA-G3 modules: reset of the processor core, excluding the Power Management Unit and the RTC block. The V_INT generic digital interfaces supply is switched on and each digital pin is set in its internal reset state. The V_BCKP supply and the RTC block are switched on.  SARA-U2 modules: reset of the processor core and the Power Management Unit, excluding the RTC block. The V_INT generic digital interfaces supply is switched off and all digital pins are tri-stated (not supplied). The V_BCKP supply and the RTC block are switched on. Before the switch-on of the generic digital interface supply source (V_INT) of the module, no voltage driven by an external application should be applied to any generic digital interface of the modules. The internal reset state of all digital pins is reported in the pin description table in the SARA-G3 series Data Sheet [1] and in the SARA-U2 series Data Sheet [2].

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 37 of 188 1.6.4 External 32 kHz signal input (EXT32K) The EXT32K pin is not available on SARA-G340, SARA-G350 and SARA-U2 series modules. The EXT32K pin of SARA-G300 / SARA-G310 modules is an input pin that must be fed by a proper 32 kHz signal to make available the reference clock for the Real Time Clock (RTC) timing, used by the module processor when in the low power idle-mode. SARA-G300 / SARA-G310 modules can enter the low power idle-mode only if a proper 32 kHz signal is provided at the EXT32K input pin, with power saving configuration enabled by the AT+UPSV command. In this way the different current consumption figures can be reached with the EXT32K input fed by the 32K_OUT output or by a proper external 32 kHz signal (for more details see section 1.5.1.4 and to “Current consumption” section in SARA-G3 series Data Sheet [1]). SARA-G300 / SARA-G310 modules can provide the RTC functions (as RTC timing by AT+CCLK command and RTC alarm by AT+CALA command) only if a proper 32 kHz signal is provided at the EXT32K input pin. The RTC functions will be available only when the module is switched on if the EXT32K input is fed by the 32K_OUT output, or they will be available also when the module is not powered or switched off if the EXT32K input is fed by a proper external 32 kHz signal. SARA-G3 series Data Sheet [1] describes the detailed electrical characteristics of the EXT32K input pin. The 32 kHz reference clock for the RTC timing is automatically generated by the internal oscillator provided on the SARA-G340, SARA-G350 and SARA-U2 series modules: the same pin (31) is a reserved (RSVD) pin internally not connected, since an external 32 kHz signal is not needed to enter the low power idle-mode and to provide the RTC functions. 1.6.5 Internal 32 kHz signal output (32K_OUT) The 32K_OUT pin is not available on SARA-G340, SARA-G350 and SARA-U2 series modules. The 32K_OUT pin of SARA-G300 / SARA-G310 modules is an output pin that provides a 32 kHz reference signal generated by the module, suitable only to feed the EXT32K input pin of SARA-G300 / SARA-G310 modules, to make available the reference clock for the Real Time Clock (RTC) timing, so that the modules can enter the low power idle-mode and can provide the RTC functions with modules switched on. The 32K_OUT pin does not provide the 32 kHz output signal when the SARA-G300 / SARA-G310 modules are in power down mode: the EXT32K input pin must be fed by an external proper 32 kHz signal to make available the RTC functions when the modules are not powered or switched off. SARA-G340, SARA-G350 and SARA-U2 series modules do not provide the 32K_OUT output, as there is no EXT32K input to feed on the modules: the pin 24 constitute the GPIO3 on these modules.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 38 of 188 1.7 Antenna interface 1.7.1 Antenna RF interface (ANT) The ANT pin of SARA-G3 and SARA-U2 series modules represents the RF input/output for transmission and reception of the 2G or 3G RF signals. The ANT pin has a nominal characteristic impedance of 50  and must be connected to the antenna through a 50  transmission line to allow proper RF transmission and reception in operating bands. 1.7.1.1 Antenna RF interface requirements Table 10 summarizes the requirements for the antenna RF interface (ANT). See section 2.4.1 for suggestions to properly design an antenna circuit compliant to these requirements. The antenna circuit affects the RF compliance of the device integrating SARA-G3 and SARA-U2 series module with applicable required certification schemes. Compliance is guaranteed if the antenna RF interface (ANT) requirements summarized in Table 10 are fulfilled. Item Requirements Remarks Impedance 50  nominal characteristic impedance The impedance of the antenna RF connection must match the 50  impedance of the ANT pin. Frequency Range See the SARA-G3 series Data Sheet [1] and the SARA-U2 series Data Sheet [2] The required frequency range of the antenna depends on the operating bands of the used modules. V.S.W.R Return Loss < 2:1 recommended, < 3:1 acceptable S11 < -10 dB recommended, S11 < -6 dB acceptable The impedance of the antenna termination must match as much as possible the 50  impedance of the ANT pin over the operating frequency range. Input Power > 2 W peak The antenna termination must withstand the maximum peak of power transmitted by the modules during a GSM single-slot call. Gain See section 4.2.2 for gain limits The antenna gain must not exceed the herein specified value to comply with FCC radiation exposure limits. Detection Application board with antenna detection circuit If antenna detection is required by the custom application, proper antenna detection circuit must be implemented on the application board as described in section 2.4.2. Antenna assembly with built-in diagnostic circuit If antenna detection is required by the custom application, the external antenna assembly must be provided with proper diagnostic circuit as described in section 2.4.2. Table 10: Summary of antenna RF interface (ANT) requirements For the additional specific requirement for SARA-G350 ATEX modules integration in potentially explosive atmospheres applications, see section 2.14.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 39 of 188 1.7.2 Antenna detection interface (ANT_DET) Antenna detection interface (ANT_DET) is not supported by SARA-G300 and SARA-G310 modules. The antenna detection is based on ADC measurement. The ANT_DET pin is an Analog to Digital Converter (ADC) provided to sense the antenna presence. The antenna detection function provided by ANT_DET pin is an optional feature that can be implemented if the application requires it. The antenna detection is forced by the +UANTR AT command. See the u-blox AT Commands Manual [3] for more details on this feature. The ANT_DET pin generates a DC current (20 µA for 5.4 ms on SARA-G340 / SARA-G350, 10 µA for 128 µs on SARA-U2 modules) and measures the resulting DC voltage, thus determining the resistance from the antenna connector provided on the application board to GND. So, the requirements to achieve antenna detection functionality are the following:  an RF antenna assembly with a built-in resistor (diagnostic circuit) must be used  an antenna detection circuit must be implemented on the application board See section 2.4.2 for antenna detection circuit on application board and diagnostic circuit on antenna assembly design-in guidelines. 1.8 SIM interface 1.8.1 (U)SIM card interface SARA-G3 and SARA-U2 series modules provide a high-speed SIM/ME interface, including automatic detection and configuration of the voltage required by the connected (U)SIM card or chip. Both 1.8 V and 3 V SIM types are supported: activation and deactivation with automatic voltage switch from 1.8 V to 3 V is implemented, according to ISO-IEC 7816-3 specifications. The VSIM supply output pin provides internal short circuit protection to limit start-up current and protect the device in short circuit situations. The SIM driver supports the PPS (Protocol and Parameter Selection) procedure for baud-rate selection, according to the values determined by the SIM Card. SIM Application Toolkit is supported by all SARA-G3 and SARA-U2 series except SARA-G300 and SARA-G310. 1.8.2 SIM card detection interface (SIM_DET) Not supported by SARA-G300-00S and SARA-G310-00S modules. The SIM_DET pin is configured as an external interrupt to detect the SIM card mechanical / physical presence. The pin is configured as input with an internal active pull-down enabled, and it can sense SIM card presence only if properly connected to the mechanical switch of a SIM card holder as described in section 2.5:  Low logic level at SIM_DET input pin is recognized as SIM card not present  High logic level at SIM_DET input pin is recognized as SIM card present The SIM card detection function provided by SIM_DET pin is an optional feature that can be implemented / used or not according to the application requirements: an Unsolicited Result Code (URC) is generated each time that there is a change of status (for more details see the u-blox AT Commands Manual [3], “simind” value of the <descr> parameter of the +CIND and +CMER commands. The optional function “SIM card hot insertion/removal” can be additionally enabled on the SARA-U2 modules’ SIM_DET pin by AT commands (see section 1.11 and u-blox AT Commands Manual [3], +UGPIOC, +UDCONF).

$SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 40 of 188 1.9 Serial interfaces SARA-G3 and SARA-U2 series modules provide the following serial communication interfaces:  UART interface: 9-wire unbalanced 1.8 V asynchronous serial interface available for AT commands, data communication, FW upgrades by means of the FOAT feature (see 1.9.1)  Auxiliary UART interface (not supported by SARA-U2 series): 3-wire unbalanced 1.8 V asynchronous serial interface available for FW upgrades by means of the u-blox EasyFlash tool and for diagnostic (see 1.9.2)  USB interface (not supported by SARA-G3 series): High-Speed USB 2.0 compliant interface available for AT commands, data communication, FW upgrades by means of the FOAT feature, FW upgrades by means of the u-blox EasyFlash tool and for diagnostic (see 1.9.3)  DDC interface (not supported by SARA-G300 / SARA-G310): I2C compatible 1.8 V interface available for the communication with u-blox positioning chips / modules and additionally, except for SARA-G3 series, with other external I2C devices as an audio codec (see 1.9.4) 1.9.1 Asynchronous serial interface (UART) 1.9.1.1 UART features The UART interface is a 9-wire 1.8 V unbalanced asynchronous serial interface available for AT commands and for packet-switched / circuit-switched data communication on all the SARA-G3 and SARA-U2 series modules. The UART interface provides RS-232 functionality conforming to the ITU-T V.24 Recommendation (more details available in ITU Recommendation [10]), with CMOS compatible signal levels: 0 V for low data bit or ON state, and 1.8 V for high data bit or OFF state. For detailed electrical characteristics see SARA-G3 series Data Sheet [1] and SARA-U2 series Data Sheet [2]. SARA-G3 and SARA-U2 series modules are designed to operate as a 2G or 3G cellular modem, which represents the Data Circuit-terminating Equipment (DCE) according to the ITU-T V.24 Recommendation [10]. The application processor connected to the module through the UART interface represents the Data Terminal Equipment (DTE). The signal names of SARA-G3 and SARA-U2 series modules’ UART interface conform to the ITU-T V.24 Recommendation [10]: e.g. the TXD line represents the data transmitted by the DTE (application processor data line output) and received by the DCE (module data line input). All flow control handshakes are supported by the UART interface and can be set by appropriate AT commands (see u-blox AT Commands Manual [3], &K, +IFC, \Q AT commands): hardware flow control (RTS/CTS), software flow control (XON/XOFF), or none flow control. Hardware flow control is enabled by default. SARA-G3 modules support the autobauding: the baud rate automatic detection is performed each time the DTE sends AT commands. After the detection the module works at the detected baud rate and the baud rate can be runtime changed by the DTE or by AT command (see u-blox AT Commands Manual [3], +IPR command). SARA-U2 modules support only the one-shot autobauding: the baud rate automatic detection is performed only once, at module start up. After the detection the module works at the detected baud rate and the baud rate can only be changed by AT command (see u-blox AT Commands Manual [3], +IPR command). SARA-G3 modules’ autobauding and SARA-U2 modules’ one-shot autobauding are enabled by default.$

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 41 of 188 The following baud rates can be configured by AT command (see u-blox AT Commands Manual [3], +IPR):  1200 b/s  2400 b/s  4800 b/s  9600 b/s  19200 b/s  38400 b/s  57600 b/s  115200 b/s, default value when the autobauding or the one-shot autobauding are disabled  230400 b/s  460800 b/s  921600 b/s 460800 b/s and 921600 b/s baud rates are not supported by SARA-G3 series modules. 1200 b/s and 230400 b/s baud rates cannot be automatically detected by SARA-G3 series modules. 460800 b/s and 921600 b/s baud rates cannot be automatically detected by SARA-U2 series modules. SARA-G3 modules support the automatic frame recognition in conjunction with autobauding. SARA-U2 modules support the one-shot automatic frame recognition in conjunction with one-shot autobauding. SARA-G3 series modules’ automatic frame recognition and SARA-U2 series modules’ one-shot automatic frame recognition are enabled by default, as autobauding and one-shot autobauding. The following frame formats can be configured by AT command (see u-blox AT Commands Manual [3], +ICF):  8N1 (8 data bits, No parity, 1 stop bit), default frame configuration with fixed baud rate  8E1 (8 data bits, even parity, 1 stop bit)  8O1 (8 data bits, odd parity, 1 stop bit)  8N2 (8 data bits, No parity, 2 stop bits)  7E1 (7 data bits, even parity, 1 stop bit)  7O1 (7 data bits, odd parity, 1 stop bit) Figure 22 describes the 8N1 frame format, which is the default configuration with fixed baud rate. D0 D1 D2 D3 D4 D5 D6 D7Start of 1-BytetransferStart Bit(Always 0)Possible Start ofnext transferStop Bit(Always 1)tbit = 1/(Baudrate)Normal Transfer, 8N1 Figure 22: Description of UART default frame format (8N1) with fixed baud rate

$SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 43 of 188 1.9.1.3 UART signal behavior At the module switch-on, before the UART interface initialization (as described in the power-on sequence reported in Figure 18 or Figure 19), each pin is first tri-stated and then is set to its related internal reset state10. At the end of the boot sequence, the UART interface is initialized, the module is by default in active-mode, and the UART interface is enabled as AT commands interface. The configuration and the behavior of the UART signals after the boot sequence are described below. See section 1.4 for definition and description of module operating modes referred to in this section. RXD signal behavior The module data output line (RXD) is set by default to the OFF state (high level) at UART initialization. The module holds RXD in the OFF state until the module does not transmit some data. TXD signal behavior The module data input line (TXD) is set by default to the OFF state (high level) at UART initialization. The TXD line is then held by the module in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the TXD input. CTS signal behavior The module hardware flow control output (CTS line) is set to the ON state (low level) at UART initialization. If the hardware flow control is enabled, as it is by default, the CTS line indicates when the UART interface is enabled (data can be sent and received). The module drives the CTS line to the ON state or to the OFF state when it is either able or not able to accept data from the DTE over the UART (see 1.9.1.4 for more details). If hardware flow control is enabled, then when the CTS line is OFF it does not necessarily mean that the module is in low power idle-mode, but only that the UART is not enabled, as the module could be forced to stay in active-mode for other activities, e.g. related to the network or related to other interfaces. When the multiplexer protocol is active, the CTS line state is mapped to FCon / FCoff MUX command for flow control issues outside the power saving configuration while the physical CTS line is still used as a power state indicator. For more details, see Mux Implementation Application Note [23]. The CTS hardware flow control setting can be changed by AT commands (for more details, see u-blox AT Commands Manual [3], AT&K, AT\Q, AT+IFC AT command). If the hardware flow control is not enabled, the CTS line after the UART initialization behaves as following:  on SARA-U2 modules the CTS line is always held in the ON state  on SARA-G3 modules the CTS line is set in the ON or OFF state accordingly to the power saving state as illustrated in Figure 25 if AT+UPSV=2 is set, and the CTS line is held in the ON state otherwise When the power saving configuration is enabled and the hardware flow-control is not implemented in the DTE/DCE connection, data sent by the DTE can be lost: the first character sent when the module is in the low power idle-mode will not be a valid communication character (see 1.9.1.4 for more details). 10 Refer to the pin description table in the SARA-G3 series Data Sheet [1] and SARA-U2 series Data Sheet [2].$

$SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 44 of 188 RTS signal behavior The hardware flow control input (RTS line) is set by default to the OFF state (high level) at UART initialization. The module then holds the RTS line in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the RTS input. If the HW flow control is enabled, as it is by default, the module monitors the RTS line to detect permission from the DTE to send data to the DTE itself. If the RTS line is set to the OFF state, any on-going data transmission from the module is interrupted until the subsequent RTS line change to the ON state. The DTE must still be able to accept a certain number of characters after the RTS line is set to the OFF state: the module guarantees the transmission interruption within two characters from RTS state change. Module behavior according to RTS hardware flow control status can be configured by AT commands (for more details, see u-blox AT Commands Manual [3], AT&K, AT\Q, AT+IFC command descriptions). If AT+UPSV=2 is set and HW flow control is disabled, the module monitors the RTS line to manage the power saving configuration:  When an OFF-to-ON transition occurs on the RTS input line, the UART is enabled and the module wakes up to active-mode: after ~20 ms from the OFF-to-ON transition the UART / module wake up is completed and data can be received without loss. The module cannot enter the low power idle-mode and the UART is kept enabled as long as the RTS input line is held in the ON state  If the RTS input line is set to the OFF state by the DTE, the UART is disabled (held in low power mode) and the module automatically enters low power idle-mode whenever possible For more details, see section 1.9.1.4 and u-blox AT Commands Manual [3], AT+UPSV command. DSR signal behavior If AT&S1 is set, as it is by default, the DSR module output line is set by default to the OFF state (high level) at UART initialization. The DSR line is then set to the OFF state when the module is in command mode or in online command mode and is set to the ON state when the module is in data mode (see the u-blox AT Commands Manual [3] for the definition of the interface data mode, command mode and online command mode). If AT&S0 is set, the DSR module output line is set by default to the ON state (low level) at UART initialization and is then always held in the ON state. DTR signal behavior The DTR module input line is set by default to the OFF state (high level) at UART initialization. The module then holds the DTR line in the OFF state if the line is not activated by the DTE: an active pull-up is enabled inside the module on the DTR input. Module behavior according to DTR status can be changed by AT command (for more details, see u-blox AT Commands Manual [3], AT&D command description). If AT+UPSV=3 is set, the DTR line is monitored by the module to manage the power saving configuration:  When an OFF-to-ON transition occurs on the DTR input line, the UART is enabled and the module wakes up to active-mode: after ~20 ms from the OFF-to-ON transition the UART / module wake up is completed and data can be received without loss. The module cannot enter the low power idle-mode and the UART is kept enabled as long as the DTR input line is held in the ON state  If the DTR input line is set to the OFF state by the DTE, the UART is disabled (held in low power mode) and the module automatically enters low power idle-mode whenever possible For more details, see section 1.9.1.4 and u-blox AT Commands Manual [3], AT+UPSV command. AT+UPSV=3 power saving configuration control by the DTR input is not supported by SARA-G3 modules.$

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 45 of 188 DCD signal behavior If AT&C1 is set, as it is by default, the DCD module output line is set by default to the OFF state (high level) at UART initialization. The module then sets the DCD line according to the carrier detect status: ON if the carrier is detected, OFF otherwise. For voice calls, DCD is set to the ON state when the call is established. For a data call there are the following scenarios (see the u-blox AT Commands Manual [3] for the definition of the interface data mode, command mode and online command mode):  Packet Switched Data call: Before activating the PPP protocol (data mode) a dial-up application must provide the ATD*99***<context_number># to the module: with this command the module switches from command mode to data mode and can accept PPP packets. The module sets the DCD line to the ON state, then answers with a CONNECT to confirm the ATD*99 command. The DCD ON is not related to the context activation but with the data mode  Circuit Switched Data call: To establish a data call, the DTE can send the ATD<number> command to the module which sets an outgoing data call to a remote modem (or another data module). Data can be transparent (non reliable) or non transparent (with the reliable RLP protocol). When the remote DCE accepts the data call, the module DCD line is set to ON and the CONNECT <communication baudrate> string is returned by the module. At this stage the DTE can send characters through the serial line to the data module which sends them through the network to the remote DCE attached to a remote DTE The DCD is set to ON during the execution of the +CMGS, +CMGW, +USOWR, +USODL AT commands requiring input data from the DTE: the DCD line is set to the ON state as soon as the switch to binary/text input mode is completed and the prompt is issued; DCD line is set to OFF as soon as the input mode is interrupted or completed (for more details see the u-blox AT Commands Manual [3]). The DCD line is kept in the ON state, even during the online command mode, to indicate that the data call is still established even if suspended, while if the module enters command mode, the DSR line is set to the OFF state. For more details see DSR signal behavior description. For scenarios when the DCD line setting is requested for different reasons (e.g. SMS texting during online command mode), the DCD line changes to guarantee the correct behavior for all the scenarios. For instance, in case of SMS texting in online command mode, if the data call is released, the DCD line is kept to ON till the SMS command execution is completed (even if the data call release would request the DCD setting to OFF). If AT&C0 is set, the DCD module output line is set by default to the ON state (low level) at UART initialization and is then always held in the ON state.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 46 of 188 RI signal behavior The RI module output line is set by default to the OFF state (high level) at UART initialization. Then, during an incoming call, the RI line is switched from the OFF state to the ON state with a 4:1 duty cycle and a 5 s period (ON for 1 s, OFF for 4 s, see Figure 23), until the DTE attached to the module sends the ATA string and the module accepts the incoming data call. The RING string sent by the module (DCE) to the serial port at constant time intervals is not correlated with the switch of the RI line to the ON state. Figure 23: RI behavior during an incoming call The RI line can notify an SMS arrival. When the SMS arrives, the RI line switches from OFF to ON for 1 s (see Figure 24), if the feature is enabled by the AT+CNMI command (see the u-blox AT Commands Manual [3]). Figure 24: RI behavior at SMS arrival This behavior allows the DTE to stay in power saving mode until the DCE related event requests service. For SMS arrival, if several events coincidently occur or in quick succession each event independently triggers the RI line, although the line will not be deactivated between each event. As a result, the RI line may stay to ON for more than 1 s. If an incoming call is answered within less than 1 s (with ATA or if auto-answering is set to ATS0=1) than the RI line is set to OFF earlier. As a result: RI line monitoring cannot be used by the DTE to determine the number of received SMSes. For multiple events (incoming call plus SMS received), the RI line cannot be used to discriminate the two events, but the DTE must rely on the subsequent URCs and interrogate the DCE with proper commands. The RI line can additionally notify all the URCs and all the incoming data (PPP, Direct Link, sockets, FTP), if the feature is enabled by the AT+URING command (for more details see u-blox AT Commands Manual [3]): the RI line is asserted when one of the configured events occur and it remains asserted for 1 s unless another configured event will happen, with the same behavior described in Figure 24. The AT+URING command for the notification of all the URCs and all the incoming data (PPP, Direct Link, sockets, FTP) over the RI line output is not supported by SARA-G3 modules. SMS arrives time [s] 0 RI ON RI OFF 1s SMS time [s] 0 RI ON RI OFF 1s 1stime [s]151050RI ONRI OFFCall incomes1stime [s]151050RI ONRI OFFCall incomes

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 47 of 188 1.9.1.4 UART and power-saving The power saving configuration is controlled by the AT+UPSV command (for the complete description, see u-blox AT Commands Manual [3]). When power saving is enabled, the module automatically enters low power idle-mode whenever possible, and otherwise the active-mode is maintained by the module (see section 1.4 for definition and description of module operating modes referred to in this section). The AT+UPSV command configures both the module power saving and also the UART behavior in relation to the power saving. The conditions for the module entering idle-mode also depend on the UART power saving configuration. Three different power saving configurations can be set by the AT+UPSV command:  AT+UPSV=0, power saving disabled: module forced on active-mode and UART interface enabled (default)  AT+UPSV=1, power saving enabled: module cyclic active / idle-mode and UART enabled / disabled  AT+UPSV=2, power saving enabled and controlled by the UART RTS input line  AT+UPSV=3, power saving enabled and controlled by the UART DTR input line The AT+UPSV=3 power saving configuration is not supported by SARA-G3 modules. The different power saving configurations that can be set by the +UPSV AT command are described in details in the following subsections. Table 12 summarizes the UART interface communication process in the different power saving configurations, in relation with HW flow control settings and RTS input line status. For more details on the +UPSV AT command description, refer to u-blox AT commands Manual [3]. AT+UPSV HW flow control RTS line DTR line Communication during idle-mode and wake up 0 Enabled (AT&K3) ON ON or OFF Data sent by the DTE are correctly received by the module. Data sent by the module is correctly received by the DTE. 0 Enabled (AT&K3) OFF ON or OFF Data sent by the DTE is correctly received by the module. Data sent by the module is buffered by the module and will be correctly received by the DTE when it is ready to receive data (i.e. RTS line will be ON). 0 Disabled (AT&K0) ON or OFF ON or OFF Data sent by the DTE is correctly received by the module. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise data is lost. 1 Enabled (AT&K3) ON ON or OFF Data sent by the DTE should be buffered by the DTE and will be correctly received by the module when active-mode is entered. Data sent by the module is correctly received by the DTE. 1 Enabled (AT&K3) OFF ON or OFF Data sent by the DTE should be buffered by the DTE and will be correctly received by the module when active-mode is entered. Data sent by the module is buffered by the module and will be correctly received by the DTE when it is ready to receive data (i.e. RTS line will be ON). 1 Disabled (AT&K0) ON or OFF ON or OFF The first character sent by the DTE is lost, but after ~20 ms the UART and the module are waked up: recognition of subsequent characters is guaranteed after the complete UART / module wake-up. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise data is lost. 2 Enabled (AT&K3) ON or OFF ON or OFF Not Applicable: HW flow control cannot be enabled with AT+UPSV=2. 2 Disabled (AT&K0) ON ON or OFF Data sent by the DTE is correctly received by the module. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise data is lost. 2 Disabled (AT&K0) OFF ON or OFF Data sent by the DTE is lost by SARA-U2 modules. The first character sent by the DTE is lost by SARA-G3 modules, but after ~20 ms the UART and the module are waked up: recognition of subsequent characters is guaranteed after the complete UART / module wake-up. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise data is lost.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 48 of 188 AT+UPSV HW flow control RTS line DTR line Communication during idle-mode and wake up 3 Enabled (AT&K3) ON ON Data sent by the DTE is correctly received by the module. Data sent by the module is correctly received by the DTE. 3 Enabled (AT&K3) ON OFF Data sent by the DTE is lost by the module. Data sent by the module is correctly received by the DTE. 3 Enabled (AT&K3) OFF ON Data sent by the DTE is correctly received by the module. Data sent by the module is buffered by the module and will be correctly received by the DTE when it is ready to receive data (i.e. RTS line will be ON). 3 Enabled (AT&K3) OFF OFF Data sent by the DTE is lost by the module. Data sent by the module is buffered by the module and will be correctly received by the DTE when it is ready to receive data (i.e. RTS line will be ON). 3 Disabled (AT&K0) ON or OFF ON Data sent by the DTE is correctly received by the module. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise data are lost. 3 Disabled (AT&K0) ON or OFF OFF Data sent by the DTE is lost by the module. Data sent by the module is correctly received by the DTE if it is ready to receive data, otherwise data are lost. Table 12: UART and power-saving summary AT+UPSV=0: power saving disabled, fixed active-mode The module does not enter idle-mode and the UART interface is enabled (data can be sent and received): the CTS line is always held in the ON state after UART initialization. This is the default configuration. AT+UPSV=1: power saving enabled, cyclic idle/active-mode On SARA-G3 modules, when the AT+UPSV=1 command is issued by the DTE, the UART is disabled after the timeout set by the second parameter of the +UPSV AT command (for more details see u-blox AT commands Manual [3]). On SARA-U2 modules, when the AT+UPSV=1 command is issued by the DTE, the UART is immediately disabled. Afterwards, the UART of SARA-G3 and SARA-U2 series modules is periodically enabled to receive or send data and, if data has not been received or sent over the UART, the interface is automatically disabled whenever possible according to the timeout configured by the second parameter of the +UPSV AT command. The module automatically enters the low power idle-mode whenever possible but it wakes up to active-mode according to the UART periodic wake up so that the module cyclically enters the low power idle-mode and the active-mode. Additionally, the module wakes up to active-mode according to any required activity related to the network or any other required activity related to the functions / interfaces of the module. The UART is enabled, and the module does not enter low power idle-mode, in the following cases:  During the periodic UART wake up to receive or send data  If the module needs to transmit some data over the UART (e.g. URC)  During a CSD data call and a PSD data call with external context activation  On SARA-G3 modules, during a voice call  If a character is sent by the DTE with HW flow control disabled, the first character sent causes the system wake-up due to the “wake up via data reception” feature described in the following subsection, and the UART will be then kept enabled after the last data received according to the timeout set by the second parameter of the AT+UPSV=1 command The module, outside an active call, periodically wakes up from idle-mode to active-mode to monitor the paging channel of the current base station (paging block reception), according to 2G or 3G discontinuous reception (DRX) specification.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 49 of 188 The time period between two paging receptions is defined by the current base station (i.e. by the network):  If the module is registered with a 2G network, the paging reception period can vary from ~0.47 s (DRX = 2, i.e. 2 x 51 2G-frames) up to ~2.12 s (DRX = 9, i.e. 9 x 51 2G-frames)  If the module is registered with a 3G network, the paging reception period can vary from 0.64 s (DRX = 6, i.e. 26 3G-frames) up to 5.12 s (DRX = 9, i.e. 29 3G-frames) The time period of the UART enable/disable cycle is configured differently when the module is registered with a 2G network compared to when the module is registered with a 3G network:  2G: the UART is synchronously enabled to every paging reception on SARA-G3 modules, whereas the UART is not necessarily enabled at every paging reception on SARA-U2 modules: the UART is enabled concurrently to a paging reception, and then, as data has not been received or sent, the UART is disabled until the first paging reception that occurs after a timeout of 2.0 s, and therefore the interface is enabled again  3G: the UART is asynchronously enabled to paging receptions, as the UART is enabled for ~20 ms, and then, if data are not received or sent, the UART is disabled for 2.5 s, and afterwards the interface is enabled again  Not registered: when a module is not registered with a network, the UART is enabled for ~20 ms, and then, if data has not been received or sent, the UART is disabled for ~2.1 s on SARA-G3 modules or for 2.5 s on SARA-U2 modules, and afterwards the interface is enabled again The module active-mode duration outside an active call depends on:  Network parameters, related to the time interval for the paging block reception (minimum of ~11 ms)  Duration of UART enable time in absence of data reception (~20 ms)  The time period from the last data received at the serial port during the active-mode: the module does not enter idle-mode until a timeout expires. The second parameter of the +UPSV AT command configures this timeout, from 40 2G-frames (i.e. 40 x 4.615 ms = 184 ms) up to 65000 2G-frames (i.e. 65000 x 4.615 ms = 300 s). Default value is 2000 2G-frames (i.e. 2000 x 4.615 ms = 9.2 s) The active-mode duration can be extended indefinitely since every subsequent character received during the active-mode, resets and restarts the timer. The timeout is ignored only by SARA-U2 modules immediately after AT+UPSV=1 has been sent, so that the UART interface is disabled and the module may enter idle-mode immediately after the AT+UPSV=1 is sent The hardware flow-control output (CTS line) indicates when the UART interface is enabled (data can be sent and received over the UART), if HW flow control is enabled, as illustrated in Figure 25. time [s]CTS ONCTS OFFUART disabled~10 ms (min)UART enabled~9.2 s (default)UART enabledData input0.47- 2.10 s Figure 25: CTS behavior with power saving enabled (AT+UPSV=1) and HW flow control enabled: the CTS output line indicates when the UART interface of the module is enabled (CTS = ON = low level) or disabled (CTS = OFF = high level)

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 50 of 188 AT+UPSV=2: power saving enabled and controlled by the RTS line This configuration can only be enabled with the module hardware flow control disabled by AT&K0 command. The UART interface is immediately disabled after the DTE sets the RTS line to OFF. Then, the module automatically enters idle-mode whenever possible according to any required activity related to the network or any other required activity related to the functions / interfaces of the module. The UART is disabled as long as the RTS line is held to OFF, but the UART is enabled in the following cases:  If the module needs to transmit some data over the UART (e.g. URC)  During a CSD data call and a PSD data call with external context activation  On SARA-G3 modules, during a voice call  On SARA-G3 modules, if a data is sent by the DTE, it causes the system wake-up due to the “wake up via data reception” feature described in the following subsection, and the UART will be then kept enabled after the last data received according to the timeout previously set with the AT+UPSV=1 configuration When an OFF-to-ON transition occurs on the RTS input line, the UART is re-enabled and the module, if it was in idle-mode, switches from idle to active-mode after ~20 ms: this is the UART and module “wake up time”. If the RTS line is set to ON by the DTE the module is not allowed to enter the low power idle-mode and the UART is kept enabled. On SARA-G3 modules, the CTS output line indicates the power saving state as illustrated in Figure 25, even with AT+UPSV=2. AT+UPSV=3: power saving enabled and controlled by the DTR line The AT+UPSV=3 power saving configuration is not supported by SARA-G3 modules. The AT+UPSV=3 configuration can be enabled regardless the flow control setting on UART. In particular, the HW flow control can be enabled (AT&K3) or disabled (AT&K0) on UART during this configuration. The UART interface is immediately disabled after the DTE sets the DTR line to OFF. Then, the module automatically enters idle-mode whenever possible according to any required activity related to the network or any other required activity related to the functions / interfaces of the module. The UART is disabled as long as the DTR line is set to OFF, but the UART is enabled in the following cases:  If the module needs to transmit some data over the UART (e.g. URC)  During a CSD data call and a PSD data call with external context activation When an OFF-to-ON transition occurs on the DTR input line, the UART is re-enabled and the module, if it was in idle-mode, switches from idle to active mode after 20 ms: this is the UART and module “wake up time”. If the DTR line is set to ON by the DTE, the module is not allowed to enter idle-mode and the UART is kept enabled until the DTR line is set to OFF. When the AT+UPSV=3 configuration is enabled, the DTR input line can still be used by the DTE to control the module behavior according to AT&D command configuration (see u-blox AT Commands Manual [3]). The CTS output line indicates the UART power saving state as illustrated in Figure 25, if HW flow control is enabled with AT+UPSV=3.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 51 of 188 Wake up via data reception The UART wake up via data reception consists of a special configuration of the module TXD input line that causes the system wake-up when a low-to-high transition occurs on the TXD input line. In particular, the UART is enabled and the module switches from the low power idle-mode to active-mode within ~20 ms from the first character received: this is the system “wake up time”. As a consequence, the first character sent by the DTE when UART is disabled (i.e. the wake up character) is not a valid communication character even if the wake up via data reception configuration is active, because it cannot be recognized, and the recognition of the subsequent characters is guaranteed only after the complete system wake-up (i.e. after ~20 ms). The UART wake up via data reception configuration is active in the following cases:  On SARA-G3 series, the TXD input line is configured to wake up the system via data reception if: o AT+UPSV=1 is set with HW flow control disabled o AT+UPSV=2 is set with HW flow control disabled, and the RTS line is set OFF  On SARA-U2 series, the TXD input line is configured to wake up the system via data reception only if o AT+UPSV=1 is set with hardware flow control disabled On SARA-U2 series, the UART wake up via data reception configuration is not active on the TXD input, and therefore all the data sent by the DTE is lost, if: o AT+UPSV=2 is set with HW flow control disabled, and the RTS line is set OFF o AT+UPSV=3 is set, regardless HW flow control setting, and the DTR line is set OFF Figure 26 and Figure 27 show examples of common scenarios and timing constraints:  AT+UPSV=1 power saving configuration is active and the timeout from last data received to idle-mode start is set to 2000 frames (AT+UPSV=1,2000)  Hardware flow control is disabled Figure 26 shows the case where the module UART is disabled and only a wake-up is forced. In this scenario the only character sent by the DTE is the wake-up character; as a consequence, the DCE module UART is disabled when the timeout from last data received expires (2000 frames without data reception, as the default case). OFFONDCE UART is enabled for 2000 GSM frames (~9.2 s)time Wake up time: ~20 mstime TXD inputWake up character Not recognized by DCEUARTOFFON Figure 26: Wake-up via data reception without further communication

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 52 of 188 Figure 27 shows the case where in addition to the wake-up character further (valid) characters are sent. The wake up character wakes-up the module UART. The other characters must be sent after the “wake up time” of ~20 ms. If this condition is satisfied, the module (DCE) recognizes characters. The module will disable the UART after 2000 GSM frames from the latest data reception. DCE UART is enabled for 2000 GSM frames (~9.2s) after the last data receivedtime Wake up time: ~20 mstime Wake up character Not recognized by DCEValid characters Recognized by DCEOFFONTXD inputUARTOFFON Figure 27: Wake-up via data reception with further communication The “wake-up via data reception” feature cannot be disabled. In command mode11, if autobauding is enabled and the DTE does not implement HW flow control, the DTE must always send a character to the module before the “AT” prefix set at the beginning of each command line: the first character is ignored if the module is in active-mode, or it represents the wake-up character if the module is in idle-mode. In command mode11, if autobauding is disabled, the DTE must always send a dummy “AT” before each command line: the first character is not ignored if the module is in active-mode (i.e. the module replies “OK”), or it represents the wake up character if the module is in low power idle-mode (i.e. the module does not reply). No wake-up character or dummy “AT” is required from the DTE during a voice or data call since the module UART interface continues to be enabled and does not need to be woken-up. Furthermore in data mode11 a dummy “AT” would affect the data communication. Additional considerations for SARA-U2 modules SARA-U2 modules are forced to stay in active-mode if the USB is connected and not suspended, and therefore the AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 settings are overruled but they have effect on the UART behavior: they configure UART interface power saving, so that UART is enabled / disabled according to the AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 settings. To set the AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 configuration over the USB interface of SARA-U2 modules, the autobauding must be previously disabled on the UART by the +IPR AT command over the used AT interface (the USB), and this +IPR AT command configuration must be saved in the module’ non-volatile memory (see u-blox AT Commands Manual [3]). Then, after the subsequent module re-boot, AT+UPSV=1, AT+UPSV=2 or AT+UPSV=3 can be issued over the used AT interface (the USB): all the AT profiles are updated accordingly. 11 Refer to the u-blox AT Commands Manual [3] for the definition of the interface data mode, command mode and online command mode.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 56 of 188 Combining a u-blox cellular module with a u-blox GNSS receiver allows designers to have full access to the positioning receiver directly via the cellular module: it relays control messages to the GNSS receiver via a dedicated DDC (I2C) interface. A 2nd interface connected to the positioning receiver is not necessary: AT commands via the UART or USB serial interface of the cellular module allows a fully control of the GNSS receiver from any host processor. SARA-G340, SARA-G350 and SARA-U2 modules feature embedded GNSS aiding that is a set of specific features developed by u-blox to enhance GNSS performance, decreasing the Time To First Fix (TTFF), thus allowing to calculate the position in a shorter time with higher accuracy. SARA-G340, SARA-G350 and SARA-U2 modules support these GNSS aiding types:  Local aiding  AssistNow Online  AssistNow Offline  AssistNow Autonomous The embedded GNSS aiding features can be used only if the DDC (I2C) interface of the cellular module is connected to the u-blox GNSS receivers. SARA-G340, SARA-G350 and SARA-U2 cellular modules provide additional custom functions over GPIO pins to improve the integration with u-blox positioning chips and modules. GPIO pins can handle:  GNSS receiver power-on/off: “GNSS supply enable” function provided by GPIO2 improves the positioning receiver power consumption. When the GNSS functionality is not required, the positioning receiver can be completely switched off by the cellular module that is controlled by AT commands  The wake up from idle-mode when the GNSS receiver is ready to send data: “GNSS data ready” function provided by GPIO3 improves the cellular module power consumption. When power saving is enabled in the cellular module by the AT+UPSV command and the GNSS receiver does not send data by the DDC (I2C) interface, the module automatically enters idle-mode whenever possible. With the “GNSS data ready” function the GNSS receiver can indicate to the cellular module that it is ready to send data by the DDC (I2C) interface: the positioning receiver can wake up the cellular module if it is in idle-mode, so the cellular module does not lose the data sent by the GNSS receiver even if power saving is enabled  The RTC synchronization signal to the GNSS receiver: “GNSS RTC sharing” function provided by GPIO4 improves GNSS receiver performance, decreasing the Time To First Fix (TTFF), and thus allowing to calculate the position in a shorter time with higher accuracy. When GPS local aiding is enabled, the cellular module automatically uploads data such as position, time, ephemeris, almanac, health and ionospheric parameter from the positioning receiver into its local memory, and restores this to the GNSS receiver at the next power up of the positioning receiver For more details regarding the handling of the DDC (I2C) interface, the GNSS aiding features and the GNSS related functions over GPIOs, see section 1.11, to the u-blox AT Commands Manual [3] (AT+UGPS, AT+UGPRF, AT+UGPIOC AT commands) and the GNSS Implementation Application Note [24]. “GNSS data ready” and “GNSS RTC sharing” functions are not supported by all u-blox GNSS receivers HW or ROM/FW versions. See the GNSS Implementation Application Note [24] or to the Hardware Integration Manual of the u-blox GNSS receivers for the supported features. As additional improvement for the GNSS receiver performance, the V_BCKP supply output of SARA-G340, SARA-G350 and SARA-U2 modules can be connected to the V_BCKP supply input pin of u-blox positioning chips and modules to provide the supply for the GNSS real time clock and backup RAM when the VCC supply of the cellular module is within its operating range and the VCC supply of the GNSS receiver is disabled. This enables the u-blox positioning receiver to recover from a power breakdown with either a hot start or a warm start (depending on the duration of the GNSS receiver VCC outage) and to maintain the configuration settings saved in the backup RAM.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 59 of 188 1.10.2 Digital audio interface SARA-G340, SARA-G350 and SARA-U2 modules provide one 1.8 V bidirectional 4-wire (I2S_TXD data output, I2S_RXD data input, I2S_CLK clock, I2S_WA world alignment) I2S digital audio interface that can be used for digital audio communication with external digital audio devices as an audio codec. The I2S interface can be set to two modes, by the <I2S_mode> parameter of the AT+UI2S command:  PCM mode  Normal I2S mode The I2S interface can be set to two configurations, by the <I2S_Master_Slave> parameter of AT+UI2S:  Master mode  Slave mode SARA-G340 and SARA-G350 modules do not support I2S slave mode: module acts as master only. The sample rate of transmitted/received words can be set, by the <I2S_sample_rate> parameter of AT+UI2S, to:  8 kHz  11.025 kHz  12 kHz  16 kHz  22.05 kHz  24 kHz  32 kHz  44.1 kHz  48 kHz SARA-G340 and SARA-G350 modules do not support the <I2S_sample_rate> parameter of AT+UI2S: the sample rate is fixed at 8 kHz only. The <main_uplink> and <main_downlink> parameters of the AT+USPM command must be properly configured to select the I2S digital audio interfaces paths (for more details, refer to u-blox AT Commands Manual [3]):  <main_uplink> must be properly set to select: o the I2S interface (using I2S_RXD module input)  <main_downlink> must be properly set to select: o the I2S interface (using I2S_TXD module output) Parameters of digital path can be configured and saved as described in the u-blox AT Commands Manual [3], +USGC, +UMGC, +USTN AT commands. Analog gain parameters are not used when digital path is selected. The I2S receive data input and the I2S transmit data output signals are respectively connected in parallel to the analog microphone input and speaker output signals, so resources available for analog path can be shared:  Digital filters and digital gains are available in both uplink and downlink direction  Ringer tone and service tone are mixed on the TX path when active (downlink)  The HF algorithm acts on I2S path Refer to the u-blox AT Commands Manual [3]: AT+UI2S command for possible settings of I2S interface.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 60 of 188 1.10.2.1 I2S interface – PCM mode Main features of the I2S interface in PCM mode (configurable by AT+UI2S command):  I2S runs in PCM – short alignment mode  I2S word alignment signal is configured by the <I2S_sample_rate> parameter  I2S word alignment is set high for 1 or 2 clock cycles for the synchronization, and then is set low for 16 clock cycles of sample width. The frame length, according to the length of the high pulse for the synchronization, can be 1 + 16 = 17 bits or 2 + 16 = 18 bits  I2S clock frequency depends on the frame length and the sample rate. It can be 17 x <I2S_sample_rate> or 18 x <I2S_sample_rate>  I2S transmit and I2S receive data are 16 bit words long with the same sampling rate as I2S word alignment, mono. Data is in 2’s complement notation. MSB is transmitted first  When I2S word alignment toggles high, the first synchronization bit is always low. Second synchronization bit (present only in case of 2 bit long I2S word alignment configuration) is MSB of the transmitted word (MSB is transmitted twice in this case)  I2S transmit data changes on I2S clock rising edge, I2S receive data changes on I2S clock falling edge 1.10.2.2 I2S interface – Normal I2S mode Normal I2S supports:  16 bits word  Mono interface  Sample rate: <I2S_sample_rate> parameter Main features of I2S interface in normal I2S mode (configurable by AT+UI2S command):  I2S runs in normal I2S – long alignment mode  I2S word alignment signal always runs at the <I2S_sample_rate> and synchronizes 2 channels (timeslots on word alignment high, word alignment low)  I2S transmit data is composed of 16 bit words, dual mono (the words are written on both channels). Data are in 2’s complement notation. MSB is transmitted first. The bits are written on I2S clock rising or falling edge (configurable)  I2S receive data is read as 16 bit words, mono (words are read only on the timeslot with WA high). Data is read in 2’s complement notation. MSB is read first. The bits are read on the I2S clock edge opposite to I2S transmit data writing edge (configurable)  I2S clock frequency is 16 bits x 2 channels x <I2S_sample_rate> The modes are configurable through a specific AT command (refer to the related section in the u-blox AT Commands Manual [3], +UI2S AT command) and the following parameters can be set:  MSB can be 1 bit delayed or non-delayed on I2S word alignment edge  I2S transmit data can change on rising or falling edge of I2S clock signal  I2S receive data are read on the opposite front of I2S clock signal

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 61 of 188 1.10.3 Voice-band processing system 1.10.3.1 SARA-G340 / SARA-G350 modules audio processing The voice-band processing on the SARA-G340 / SARA-G350 modules is implemented in the DSP core inside the baseband chipset. The analog audio front-end of the chipset is connected to the digital system through 16 bit ADC converters in the uplink path, and through 16 bit DAC converters in the downlink path. External digital audio devices can directly be interfaced to the DSP digital processing part via the I2S digital interface. The analog amplifiers are skipped in this case. The voice-band processing system can be split up into three different blocks:  Sample-based Voice-band Processing (single sample processed at 8 kHz, every 125 µs)  Frame-based Voice-band Processing (frames of 160 samples are processed every 20 ms)  MIDI synthesizer running at 47.6 kHz These three blocks are connected by buffers and sample rate converters (for 8 to 47.6 kHz conversion) I2S_RXDSwitchMIC Uplink Analog GainUplink Filter 2Uplink Filter 1To Radio TXUplinkDigital GainDownlink Filter 1Downlink Filter 2MIDI PlayerSPK SwitchI2Sx TXI2S_TXDScal_Rec Digital GainSPK Analog GainGain_Out Digital GainFrom Radio RXSpeech LevelI2Sx RXSample Based Processing Frame Based ProcessingCircular BufferSidetone Digital GainDACADCTone GeneratorAMR PlayerHands-FreeVoiceband Sample Buffer Figure 28: SARA-G340 / SARA-G350 modules audio processing system block diagram The sample-based voice-band processing main task is to transfer the voice-band samples from either analog audio front-end uplink path or I2Sx RX path to the Voice-band Sample Buffer and from the Voice-band Sample Buffer to the analog audio front-end downlink path and/or I2Sx TX path. While doing this the samples are scaled by digital gains and processed by digital filters both in the uplink and downlink direction and the sidetone is generated mixing scaled uplink samples to the downlink samples (refer to the u-blox AT Commands Manual [3], +UUBF, +UDBF, +UMGC, +USGC, +USTN commands). The frame-based voice-band processing implements the Hands-Free algorithm. This consists of the Echo Canceller, the Automatic Gain Control and the Noise Suppressor. Hands-Free algorithm acts on the uplink signal only. Algorithms are configurable with AT commands (refer to the u-blox AT Commands Manual [3], +UHFP command). The frame-based voice-band processing also implements an AMR player. The speech uplink path final block before radio transmission is the speech encoder. Symmetrically, on downlink path, the starting block is the speech decoder which extracts speech signal from the radio receiver. The circular buffer is a 3000 word buffer to store and mix the voice-band samples from Midi synthesizer. The buffer has a circular structure, so that when the write pointer reaches the end of the buffer, it is wrapped to the begin address of the buffer.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 62 of 188 Two different sample-based sample rate converters are used: an interpolator, required to convert the sample-based voice-band processing sampling rate of 8 kHz to the analog audio front-end output rate of 47.6 kHz; a decimator, required to convert the circular buffer sampling rate of 47.6 kHz to the I2Sx TX or the uplink path sample rate of 8 kHz. The following speech codecs are supported by SARA-G340 / SARA-G350 firmware on the DSP:  GSM Half Rate (TCH/HS)  GSM Full Rate (TCH/FS)  GSM Enhanced Full Rate (TCH/EFR)  3GPP Adaptive Multi Rate (AMR) (TCH/AFS+TCH/AHS) o In AMR Full Rate (AFS) the Active CODEC Set is selected from an overall set of 8 data rates: 12.2 – 10.2 – 7.95 – 7.40 – 6.70 – 5.90 – 5.15 – 4.75 kb/s o In AMR Half Rate (AHS) the overall set comprises 6 different data rates: 7.95 – 7.40 – 6.70 – 5.90 – 5.15 – 4.75 kb/s 1.10.3.2 SARA-U2 modules audio processing system The voiceband processing on the SARA-U2 modules is implemented in the DSP core inside the baseband chipset. The external digital audio devices can be interfaced directly to the DSP digital processing part via the I2S digital interface. With exception of the speech encoder/decoder, audio processing can be controlled by AT commands. The audio processing is implemented within the different blocks of the voiceband processing system:  Sample-based Voice-band Processing (single sample processed at 16 kHz for Wide Band AMR codec or 8 kHz for all other speech codecs)  Frame-based Voice-band Processing (frames of 320 samples for Wide Band AMR codec or 160 samples for all other speech codecs are processed every 20 ms) These blocks are connected by buffers (circular buffer and voiceband sample buffer) and sample rate converters (for 8 / 16 to 47.6 kHz conversion). The voiceband audio processing implemented in the DSP core of SARA-U2 modules is summarized in Figure 29. SwitchI2S_RXD UBF 2/6UBF 1/5Hands-freeTo Radio TXUplinkDigital GainI2S_TXDSwitchScal_Rec Digital GainTone GeneratorI2Sx RX UBF 4/8UBF 3/7DBF 3/7DBF 4/8DBF 1/5DBF 2/6Legend:UBF= Uplink Biquad FilterDBF = Downlink Biquad FilterI2Sx TXSidetoneFrom Radio RXSpeech levelPCM PlayerMix_Afe Figure 29: SARA-U2 modules audio processing system block diagram

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 63 of 188 SARA-U2 modules audio signal processing algorithms are:  Speech encoding (uplink) and decoding (downlink).The following speech codecs are supported in firmware on the DSP for speech encoding and decoding: GERAN GMSK codecs o GSM HR (GSM Half Rate) o GSM FR (GSM Full Rate) o GSM EFR (GSM Enhanced Full Rate) o HR AMR (GSM Half Rate Adaptive Multi Rate - Narrow Band) o FR AMR (GSM Full Rate Adaptive Multi Rate - Narrow Band) o FR AMR-WB (GSM Full Rate Adaptive Multi Rate - Wide Band) UTRAN codecs: o UMTS AMR2 (UMTS Adaptive Multi Rate version 2 – Narrow Band) o UMTS AMR-WB (UMTS Adaptive Multi Rate – Wide Band)  Mandatory sub-functions: o Discontinuous transmission, DTX (GSM 46.031, 46.041, 46.081 and 46.093 standards) o Voice activity detection, VAD (GSM 46.032, 46.042, 46.082 and 46.094 standards) o Background noise calculation (GSM 46.012, 46.022, 46.062 and 46.092 standards)  Function configurable via specific AT commands (refer to the u-blox AT Commands Manual [3]) o Signal routing: +USPM command o Analog amplification, digital amplification: +USGC, +CLVL, +CRSL, +CMUT command o Digital filtering: +UUBF, +UDBF commands o Hands-free algorithms (echo cancellation, Noise suppression, Automatic Gain control) +UHFP command o Sidetone generation (feedback of uplink speech signal to downlink path): +USTN command o Playing/mixing of alert tones: Service tones: Tone generator with 3 sinus tones +UPAR command User generated tones: Tone generator with a single sinus tone +UTGN command PCM audio files (for prompting): The storage format of PCM audio files is 8 kHz sample rate, signed 16 bits, little endian, mono

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 64 of 188 1.11 General Purpose Input/Output (GPIO) SARA-G300 and SARA-G310 modules do not support GPIOs. SARA-G340, SARA-G350 and SARA-U2 modules provide pins which can be configured as general purpose input or output, or can be configured to provide special functions via u-blox AT commands (for further details refer to the u-blox AT Commands Manual [3], +UGPIOC, +UGPIOR, +UGPIOW, +UGPS, +UGPRF):  SARA-G340 and SARA-G350 modules provide 4 configurable GPIO pins: GPIO1, GPIO2, GPIO3, GPIO4  SARA-U2 modules provide 9 configurable GPIO pins: GPIO1, GPIO2, GPIO3, GPIO4, I2S_RXD, I2S_TXD, I2S_CLK, I2S_WA, SIM_DET The following functions are available:  Network status indication: The GPIO1, or the GPIO2, GPIO3, GPIO4 and, on SARA-U2 series only, the SIM_DET, alternatively from their default settings, can be configured to indicate network status (i.e. no service, registered home network, registered visitor network, voice or data call enabled), setting the parameter <gpio_mode> of AT+UGPIOC command to 2. No GPIO pin is by default configured to provide the “Network status indication” function. The “Network status indication” mode can be provided only on one pin per time: it is not possible to simultaneously set the same mode on another pin. The pin configured to provide the “Network status indication” function is set as o Continuous Low, if no service (no network coverage or not registered) o Cyclically High for 100 ms, Low for 2 s, if registered home 2G network o Cyclically High for 50 ms, Low for 50 ms, High for 50 ms, Low for 2 s, if registered home 3G network o Cyclically High for 100 ms, Low for 100 ms, High for 100 ms, Low for 2 s, if registered visitor 2G network (roaming) o Cyclically High for 50 ms, Low for 50 ms, High for 50 ms, Low for 100 ms, if registered visitor 3G network (roaming) o Continuous High, if voice or data 2G/3G call enabled  GSM Tx burst indication: GPIO1 pin can be configured by AT+UGPIOC to indicate when a GSM Tx burst/slot occurs, setting the parameter <gpio_mode> of AT+UGPIOC command to 9. No GPIO pin is by default configured to provide the “GSM Tx burst indication” function. The pin configured to provide the “GSM Tx burst indication” function is set as o High, since ~10 µs before the start of first Tx slot, until ~5 µs after the end of last Tx slot o Low, otherwise SARA-U280 and SARA-U290 modules do not support the “GSM Tx burst indication” function on GPIO1, as the modules do not support 2G radio access technology.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 65 of 188  GNSS supply enable: The GPIO2 is by default configured by AT+UGPIOC command to enable or disable the supply of the u-blox GNSS receiver connected to the cellular module. The GPIO1, GPIO3, GPIO4 pins and, on SARA-U2 series only, also the SIM_DET pin, can be configured to provide the “GNSS supply enable” function, alternatively to the default GPIO2 pin, setting the parameter <gpio_mode> of AT+UGPIOC command to 3. The “GNSS supply enable” mode can be provided only on one pin per time: it is not possible to simultaneously set the same mode on another pin. The pin configured to provide the “GNSS supply enable” function is set as o High, to switch on the u-blox GNSS receiver, if AT+UGPS parameter <mode> is set to 1 o Low, to switch off the u-blox GNSS receiver, if AT+UGPS parameter <mode> is set to 0 (default)  GNSS data ready: Only the GPIO3 pin provides the “GNSS data ready” function, to sense when a u-blox GNSS receiver connected to the cellular module is ready to send data via the DDC (I2C) interface, setting the parameter <gpio_mode> of AT+UGPIOC command to 4. The pin configured to provide the “GNSS data ready” function is set as o Input, to sense the line status, waking up the cellular module from idle-mode when the u-blox GNSS receiver is ready to send data via the DDC (I2C) interface, if the first AT+UGPS parameter is set to 1 and the first AT+UGPRF parameter is set to 16 o Tri-state with an internal active pull-down enabled, otherwise (default setting)  GNSS RTC sharing: Only the GPIO4 pin provides the “GNSS RTC sharing” function, to provide an RTC (Real Time Clock) synchronization signal to the u-blox GNSS receiver connected to the cellular module, setting the parameter <gpio_mode> of AT+UGPIOC command to 5. The pin configured to provide the “GNSS RTC sharing” function is set as o Output, to provide an RTC (Real Time Clock) synchronization signal to the u-blox GNSS receiver if the first AT+UGPS parameter is set to 1 and the first AT+UGPRF parameter is set to 32 o Low, otherwise (default setting)  SIM card detection: The SIM_DET pin of SARA-G3 modules is by default configured to detect SIM card mechanical presence and this configuration cannot be changed by AT command. The SIM_DET pin of SARA-U2 modules is by default configured to detect SIM card mechanical presence as default setting of the AT+UGPIOC command: the “SIM card detection” function is enabled as the parameter <gpio_mode> of AT+UGPIOC command is set to 7 (default setting). The SIM_DET pin configured to provide the “SIM card detection” function is set as o Input with an internal active pull-down enabled, to sense SIM card mechanical presence The SIM_DET pin can sense the SIM card mechanical presence only if properly connected to the mechanical switch of a SIM card holder as described in section 2.5: o Low logic level at SIM_DET input pin is recognized as SIM card not present o High logic level at SIM_DET input pin is recognized as SIM card present SARA-U2 modules provide the additional function “SIM card hot insertion/removal” on the SIM_DET pin, which can be enabled using the AT+UDCONF=50 command if the “SIM card detection” function is enabled by AT+UGPIOC (for more details see u-blox AT Commands Manual [3]): in this case the SIM interface of the SARA-U2 modules is disabled when a Low logic level is recognized at SIM_DET input pin (within 20 ms from the start of the Low level) and it is enabled when an High logic level at SIM_DET input pin is recognized. SARA-G3 series do not support the additional function “SIM card hot insertion/removal”

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 66 of 188  Module status indication: The GPIO1 pin of SARA-U2 modules can be configured to indicate module status (power-off mode, i.e. module switched off, versus idle, active or connected mode, i.e. module switched on), by properly setting the parameter <gpio_mode> of AT+UGPIOC command to 10. No GPIO pin is by default configured to provide the “Module status indication”. The pin configured to provide the “Module status indication” function is set as o High, when the module is switched on (any operating mode during module normal operation) o Low, when the module is switched off (power off mode) SARA-G3 series do not support “Module status indication” function.  Module operating mode indication: The SIM_DET pin of SARA-U2 modules can be configured to indicate module operating mode status (the low power idle-mode versus active or connected mode), by properly setting the parameter <gpio_mode> of AT+UGPIOC command to 11. No GPIO pin is by default configured to provide the “Module operating mode indication”. The pin configured to provide the “Module operating mode indication” function is set as o Output / High, when the module is in active or connected mode o Output / Low, when the module is in idle-mode (that can be reached if power saving is enabled by +UPSV AT command: for further details see u-blox AT Commands Manual [3]) SARA-G3 series do not support “Module operating mode indication”.  I2S digital audio interface: The I2S_RXD, I2S_TXD, I2S_CLK, I2S_WA pins of SARA-U2 modules are by default configured as the I2S digital audio interface. Only these pins of SARA-U2 modules can be configured as the I2S digital audio interface, by correctly setting the parameter <gpio_mode> of AT+UGPIOC command to 12 (default setting). SARA-G3 series do not support the I2S digital audio interface over GPIOs.  General purpose input: All the GPIOs can be configured as input to sense high or low digital level through AT+UGPIOR command, setting the parameter <gpio_mode> of AT+UGPIOC command to 1. The “General purpose input” mode can be provided on more than one pin at a time. No GPIO pin is by default configured as “General purpose input”. The pin configured to provide the “General purpose input” function is set as o Input, to sense high or low digital level by AT+UGPIOR command.  General purpose output: All the GPIOs can be configured as output to set the high or the low digital level through AT+UGPIOW command, setting the parameter <gpio_mode> of +UGPIOC AT command to 0. The “General purpose output” mode can be provided on more than one pin per time. No GPIO pin is by default configured as “General purpose output”. The pin configured to provide the “General purpose output” function is set as o Output / Low, if the parameter <gpio_out_val> of AT+UGPIOW command is set to 0 o Output / High, if the parameter <gpio_out_val> of AT+UGPIOW command is set to 1

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 67 of 188  Pin disabled: All the GPIOs can be configured in tri-state with an internal active pull-down enabled, as a not used pin, setting the parameter <gpio_mode> of +UGPIOC AT command to 255. The “Pin disabled” mode can be provided on more than one pin per time: it is possible to simultaneously set the same mode on another pin (also on all the GPIOs). The pin configured to provide the “Pin disabled” function is set as o Tri-state with an internal active pull-down enabled Table 13 describes the configurations of all SARA-G340, SARA-G350 and SARA-U2 modules’ GPIO pins. Pin Module Name Description Remarks 16 SARA-G340 SARA-G350 GPIO1 GPIO By default, the pin is configured as Pin disabled. Can be alternatively configured by the AT+UGPIOC command as  Output  Input  Network Status Indication  GNSS Supply Enable  GSM Tx Burst Indication SARA-U260 SARA-U270 GPIO1 GPIO By default, the pin is configured as Pin disabled. Can be alternatively configured by the AT+UGPIOC command as  Output  Input  Network Status Indication  GNSS Supply Enable  GSM Tx Burst Indication  Module Status Indication SARA-U280 SARA-U290 GPIO1 GPIO By default, the pin is configured as Pin disabled. Can be alternatively configured by the AT+UGPIOC command as  Output  Input  Network Status Indication  GNSS Supply Enable  Module Status Indication 23 SARA-G340 SARA-G350 SARA-U2 series GPIO2 GPIO By default, the pin is configured to provide GNSS Supply Enable function. Can be alternatively configured by the +UGPIOC command as  Output  Input  Network Status Indication  Pin disabled 24 SARA-G340 SARA-G350 SARA-U2 series GPIO3 GPIO By default, the pin is configured to provide GNSS Data Ready function. Can be alternatively configured by the +UGPIOC command as  Output  Input  Network Status Indication  GNSS Supply Enable  Pin disabled 25 SARA-G340 SARA-G350 SARA-U2 series GPIO4 GPIO By default, the pin is configured to provide GNSS RTC sharing function. Can be alternatively configured by the +UGPIOC command as  Output  Input  Network Status Indication  GNSS Supply Enable  Pin disabled

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 68 of 188 Pin Module Name Description Remarks 42 SARA-G340 SARA-G350 SIM_DET SIM detection By default, the pin is configured to provide SIM card detection function. The pin cannot be alternatively configured by the +UGPIOC command. SARA-U2 series SIM_DET GPIO By default, the pin is configured to provide SIM card detection function. Can be alternatively configured by the +UGPIOC command as  Output  Input  Network Status Indication  GNSS Supply Enable  Module Operating Mode Indication  Pin disabled 34 SARA-U2 series I2S_WA GPIO By default, the pin is configured to provide I2S word alignment function. Can be alternatively configured by the +UGPIOC command as  Output  Input  Pin disabled 35 SARA-U2 series I2S_TXD GPIO By default, the pin is configured to provide I2S data output function. Can be alternatively configured by the +UGPIOC command as  Output  Input  Pin disabled 36 SARA-U2 series I2S_CLK GPIO By default, the pin is configured to provide I2S clock function. Can be alternatively configured by the +UGPIOC command as  Output  Input  Pin disabled 37 SARA-U2 series I2S_RXD GPIO By default, the pin is configured to provide I2S data input function. Can be alternatively configured by the +UGPIOC command as  Output  Input  Pin disabled Table 13: GPIO pins configurations 1.12 Reserved pins (RSVD) SARA-G3 and SARA-U2 series modules have pins reserved for future use: they can all be left unconnected on the application board, except the RSVD pin number 33 that must be externally connected to ground.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 69 of 188 1.13 System features 1.13.1 Network indication Not supported by SARA-G300 and SARA-G310 modules. The GPIO1, or the GPIO2, GPIO3, GPIO4 and, on SARA-U2 series only, the SIM_DET, alternatively from their default settings, can be configured to indicate network status (i.e. no service, registered home network, registered visitor network, voice or data call enabled), by means of the AT+UGPIOC command. For the detailed description, see section 1.11 and to u-blox AT Commands Manual [3], GPIO commands. 1.13.2 Antenna detection Not supported by SARA-G300 and SARA-G310 modules. ANT_DET pin of SARA-G340, SARA-G350 and SARA-U2 series modules is an Analog to Digital Converter (ADC) provided to sense the presence of an external antenna when optionally set by the +UANTR AT command. The external antenna assembly must be provided with a built-in resistor (diagnostic circuit) to be detected, and an antenna detection circuit must be implemented on the application board properly connecting the antenna detection input (ANT_DET) to the antenna RF interface (ANT). For more details regarding feature description and detection / diagnostic circuit design-in see sections 1.7.2 and 2.4.2, and to the u-blox AT Commands Manual [3]. 1.13.3 Jamming detection Not supported by SARA-G300 and SARA-G310 modules. In real network situations modules can experience various kind of out-of-coverage conditions: limited service conditions when roaming to networks not supporting the specific SIM, limited service in cells which are not suitable or barred due to operators’ choices, no cell condition when moving to poorly served or highly interfered areas. In the latter case, interference can be artificially injected in the environment by a noise generator covering a given spectrum, thus obscuring the operator’s carriers entitled to give access to the cellular service. The Jamming Detection Feature detects such “artificial” interference and reports the start and stop of such conditions to the client, which can react appropriately by e.g. switching off the radio transceiver to reduce power consumption and monitoring the environment at constant periods. The feature detects, at radio resource level, an anomalous source of interference and signals it to the client with an unsolicited indication when the detection is entered or released. The jamming condition occurs when:  The module has lost synchronization with the serving cell and cannot select any other cell  The band scan reveals at least n carriers with power level equal or higher than threshold  On all such carriers, no synchronization is possible The client can configure the number of minimum disturbing carriers and the power level threshold by using the AT+UCD command [3]. The jamming condition is cleared when any of the above mentioned statements does not hold. The congestion (i.e. jamming) detection feature can be enabled and configured by the +UCD AT command (for more details see the u-blox AT Commands Manual [3]).

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 70 of 188 1.13.4 TCP/IP and UDP/IP Not supported by SARA-G300 and SARA-G310 modules. Via the AT commands it is possible to access the embedded TCP/IP and UDP/IP stack functionalities over the Packet Switched data connection. For more details about AT commands see u-blox AT Commands Manual [3]. Direct Link mode for TCP and UDP sockets is supported. Sockets can be set in Direct Link mode to establish a transparent end-to-end communication with an already connected TCP or UDP socket via serial interface. In Direct Link mode, data sent to the serial interface from an external application processor is forwarded to the network and vice-versa. To avoid data loss while using Direct Link, enable HW flow control on the serial interface. 1.13.5 FTP Not supported by SARA-G300 and SARA-G310 modules. SARA-G340, SARA-G350 and SARA-U2 series modules support the File Transfer Protocol functionalities via AT commands. Files are read and stored in the local file system of the module. SARA-U2 series modules support also Secure File Transfer Protocol functionalities providing SSL encryption. For more details about AT commands see the u-blox AT Commands Manual [3]. 1.13.6 HTTP Not supported by SARA-G300 and SARA-G310 modules. SARA-G340, SARA-G350 and SARA-U2 modules support Hyper-Text Transfer Protocol functionalities as an HTTP client is implemented: HEAD, GET, POST, DELETE and PUT operations are available. The file size to be uploaded / downloaded depends on the free space available in the local file system (FFS) at the moment of the operation. Up to 4 HTTP client contexts can simultaneously be used. SARA-U2 modules support also Secure Hyper-Text Transfer Protocol functionalities providing SSL encryption. For more details about AT commands see the u-blox AT Commands Manual [3]. 1.13.7 SMTP Not supported by SARA-G300, SARA-G310 and SARA-U2 modules. SARA-G340 and SARA-G350 modules support SMTP client functionalities. It is possible to specify the common parameters (e.g. server data, authentication method, etc. can be specified), to send an email to a SMTP server. Emails can be sent with or without attachment. Attachments are stored in the module local file system. For more details about AT commands see the u-blox AT Commands Manual [3].

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 71 of 188 1.13.8 SSL Not supported by SARA-G3 modules. SARA-U2 modules support the Transport Layer Security (TLS) / Secure Sockets Layer (SSL) cryptographic protocols to provide security over the FTP and HTTP protocols. The following features are supported:  Protocol: TLS version 1  Certificate types: RSA  Certificate key size: up to 4096 bit  Certificate signature: MD5, SHA1, SHA256, SHA512  Data encryption algorithms: o AES 128 bits in CipherBlockChaining mode o RC4 128 bit in stream mode  Message authentication algorithms: o SHA1: 160 bits o MD5: 128 bits The SARA-U2 modules: o support the server authentication without the root certificate verification o do not support the mutual authentication (use of client certificates) Table 14 lists the TLS cipher suite registry values supported by SARA-U2 series modules. SSL features TLS Certificates Data Encryption Message authentication algorithms TLS_RSA_WITH_AES_128_CBC_SHA TLSv1 RSA key exchange AES 128 bits in CipherBlockChaining mode SHA1 160 bits TLS_RSA_WITH_RC4_128_SHA TLSv1 RSA key exchange RC4 128 bits in stream mode SHA1 160 bits TLS_RSA_WITH_RC4_128_MD5 TLSv1 RSA key exchange RC4 128 bits in stream mode MD5 128 bits TLS_RSA_WITH_NULL_SHA TLSv1 RSA key exchange No data encryption SHA1 160 bits Table 14: SARA-U2 TLS cipher suite registry 1.13.9 Dual stack IPv4/IPv6 Not supported by SARA-G3 modules. SARA-U2 modules support both Internet Protocol version 4 and Internet Protocol version 6. For more details about dual stack IPv4/IPv6 see the u-blox AT Commands Manual [3].

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 72 of 188 1.13.10 Smart temperature management Not supported by SARA-G300 and SARA-G310 modules. Cellular modules – independent of the specific model – always have a well-defined operating temperature range. This range should be respected to guarantee full device functionality and long life span. Nevertheless there are environmental conditions that can affect operating temperature, e.g. if the device is located near a heating/cooling source, if there is/is not air circulating, etc. The module itself can also influence the environmental conditions; such as when it is transmitting at full power. In this case its temperature increases very quickly and can raise the temperature nearby. The best solution is always to properly design the system where the module is integrated. Nevertheless an extra check/security mechanism embedded into the module is a good solution to prevent operation of the device outside of the specified range. Smart Temperature Supervisor (STS) The Smart Temperature Supervisor is activated and configured by a dedicated AT+USTS command. See u-blox AT Commands Manual [3] for more details. The cellular module measures the internal temperature (Ti) and its value is compared with predefined thresholds to identify the actual working temperature range. Temperature measurement is done inside the module: the measured value could be different from the environmental temperature (Ta). Warningareat-1 t+1 t+2t-2Valid temperature rangeSafeareaDangerousarea Dangerousarea Warningarea Figure 30: Temperature range and limits The entire temperature range is divided into sub-regions by limits (see Figure 30) named t-2, t-1, t+1 and t+2.  Within the first limit, (t-1 < Ti < t+1), the cellular module is in the normal working range, the Safe Area  In the Warning Area, (t-2 < Ti < t.1) or (t+1 < Ti < t+2), the cellular module is still inside the valid temperature range, but the measured temperature approaches the limit (upper or lower). The module sends a warning to the user (through the active AT communication interface), which can take, if possible, the necessary actions to return to a safer temperature range or simply ignore the indication. The module is still in a valid and good working condition  Outside the valid temperature range, (Ti < t-2) or (Ti > t+2), the device is working outside the specified range and represents a dangerous working condition. This condition is indicated and the device shuts down to avoid damage For security reasons the shutdown is suspended in case an emergency call in progress. In this case the device switches off at call termination. The user can decide at anytime to enable/disable the Smart Temperature Supervisor feature. If the feature is disabled there is no embedded protection against disallowed temperature conditions.

SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 73 of 188 Figure 31 shows the flow diagram implemented in the SARA-G340 and SARA-G350 modules for the Smart Temperature Supervisor. IF STS enabledRead temperatureIF(t-1<Ti<t+1)IF(t-2<Ti<t+2)Send notification (warning)Send notification(dangerous)Wait emergencycall terminationIFemerg. call in progressShut the device downYesNoYesYesNoNoNoYesSend shutdownnotificationFeature enabled (full logic or indication only)IF Full Logic EnabledFeature disabled: no actionTemperature is within normal operating rangeYesTempetature is within warning areaTempetature is outside valid temperature rangeNoFeatuere enabled in full logic modeFeature enabled in indication only mode:no further actionsSend notification (safe)Previously outside of Safe AreaTempetature is back to safe areaNoNo furtheractionsYes Figure 31: Smart Temperature Supervisor (STS) flow diagram

$SARA-G3 and SARA-U2 series - System Integration Manual UBX-13000995 - R08 Objective Specification System description Page 74 of 188 Threshold definitions When the module application operates at extreme temperatures with Smart Temperature Supervisor enabled, the user should note that outside the valid temperature range the device automatically shuts down as described above. The input for the algorithm is always the temperature measured within the cellular module (Ti, internal). This value can be higher than the working ambient temperature (Ta, ambient), since (for example) during transmission at maximum power a significant fraction of DC input power is dissipated as heat. This behavior is partially compensated by the definition of the upper shutdown threshold (t+2) that is slightly higher than the declared environmental temperature limit. Table 15 defines the temperature thresholds for SARA-G340 and SARA-G350 modules. Symbol Parameter Temperature Remarks t-2 Low temperature shutdown –40 °C Equal to the absolute minimum temperature rating for the cellular module (the lower limit of the extended temperature range) t-1 Low temperature warning –30 °C 10 °C above t-2 t+1 High temperature warning +85 °C 10 °C below t+2. The higher warning area for upper range ensures that any countermeasures used to limit the thermal heating will become effective, even considering some thermal inertia of the complete assembly. t+2 High temperature shutdown +95 °C Equal to the internal temperature Ti measured in the worst case operating condition at typical supply voltage when the ambient temperature Ta in the reference setup (*) equals the absolute maximum temperature rating (upper limit of the extended temperature range) (*) SARA-G340 / SARA-G350 module mounted on a 79 x 62 x 1.41 mm 4-Layers PCB with a high coverage of copper in still air conditions Table 15: Thresholds definition for Smart Temperature Supervisor on the SARA-G340 and SARA-G350 modules The sensor measures board temperature inside the shields, which can differ from ambient temperature. 1.13.11 AssistNow clients and GNSS integration Not supported by SARA-G300 and SARA-G310 modules. For customers using u-blox GNSS receivers, SARA-G340, SARA-G350 and SARA-U2 modules feature embedded AssistNow clients. AssistNow A-GPS provides better GNSS performance and faster Time-To-First-Fix. The clients can be enabled and disabled with an AT command (see the u-blox AT Commands Manual [3]). SARA-G340, SARA-G350 and SARA-U2 modules act as a stand-alone AssistNow client, making AssistNow available with no additional requirements for resources or software integration on an external host micro controller. Full access to u-blox positioning receivers is available via the cellular modules, through a dedicated DDC (I2C) interface, while the available GPIOs can handle the positioning chipset / module power-on/off. This means that the cellular module and the positioning chips and modules can be controlled through a single serial port from any host processor.$

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