Jorjin Technologies WG7833B0 Wireless Module User Manual WG7833 B0 DTS R03 20150731

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a module solution provider
WG7833-B0 WLAN/BT Module
TI WiLink8 IEEE 802.11a/b/g/n
BT/BLE Solution
Datasheet
Revision 0.3
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Index
1.
2.
OVERVIEW ................................................................................................................................... 4
1.1.
MODELS FUNCTIONAL BLOCKS ................................................................................................ 4
1.2.
GENERAL FEATURES ................................................................................................................. 4
FUNCTIONAL FEATURES ............................................................................................................ 5
2.1.
MODULE BLOCK DIAGRAM ..................................................................................................... 5
2.2.
BLOCK FUNCTIONAL FEATURE .................................................................................................. 5
2.2.1.
2.2.2.
2.2.3.
2.2.4.
3.
MODULE OUTLINE ....................................................................................................................... 8
3.1.
3.2.
4.
WLAN Features .......................................................................................................... 5
Bluetooth Features.................................................................................................... 6
BLE Features ................................................................................................................ 6
ANT Features .............................................................................................................. 7
SIGNAL LAYOUT (TOP VIEW).................................................................................................... 8
PIN DESCRIPTION ..................................................................................................................... 9
MODULE SPECIFICATION ....................................................................................................... 13
4.1.
GENERAL MODULE REQUIREMENTS AND OPERATION ............................................................ 13
4.1.1.
Absolute Maximum Ratings (1) ............................................................................. 13
4.1.2.
Recommended Operating Conditions ............................................................ 14
4.1.3.
External Slow Clock Input (SLOW_CLK) ............................................................ 15
4.1.4.
External Fast Clock Requirements (-40 to +85°C) .......................................... 15
4.2. WLAN RF PERFORMANCE .................................................................................................... 17
4.2.1.
WLAN 2.4-GHz Receiver Characteristics .......................................................... 17
4.2.2.
WLAN 2.4-GHz Transmitter Power ....................................................................... 18
4.2.4.
WLAN 5-GHz Transmitter Power (For WG7833/03 Only) ............................... 20
4.3. BLUETOOTH RF PERFORMANCE (FOR WG7833/31 ONLY) .................................................. 21
4.3.1.
BT Receiver Characteristics, In-Band Signals .................................................. 21
4.3.2.
BT Receiver Characteristics – General Blocking ............................................ 22
4.3.3.
BT Receiver Characteristics –BR, EDR Blocking Per Band ............................ 22
4.3.5.
BT Transmitter, EDR .................................................................................................. 23
4.3.6.
4.3.7.
4.3.8.
BT Modulation, BR ................................................................................................... 23
BT Modulation, EDR ................................................................................................ 24
BT BR, EDR Transceiver - Emissions ...................................................................... 24
4.3.9.
BT BR Transceiver - Spurs........................................................................................ 25
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4.3.10. BT EDR Transceiver - Spurs ..................................................................................... 25
4.4. BT LE RF PERFORMANCE ........................................................................................................... 26
4.4.1.
BT LE Receiver Characteristics, In-Band Signals ....................................................... 26
4.4.3.
BT LE Transmitter Characteristics .............................................................................. 27
4.4.4.
BT LE Modulation Characteristics .............................................................................. 27
4.4.6.
BT LE Transceiver - Spurs ........................................................................................... 28
4.5. ANT PERFORMANCE.................................................................................................................. 28
4.5.1.
ANT Receiver Characteristics, In-Band Signals .......................................................... 28
4.5.2.
4.6.
5.
ANT Transmitter Characteristics ................................................................................. 28
POWER CONSUMPTION ....................................................................................................... 29
HOST INTERFACE TIMING CHARACTERISTICS .................................................................... 32
5.1.
WLAN SDIO TRANSPORT L AYER ................................................................................................. 32
5.2.
5.3.
SDIO TIMING SPECIFICATIONS ..................................................................................................... 33
HCI UART SHARED TRANSPORT L AYERS FOR ALL FUNCTIONAL BLOCKS (EXCEPT WLAN) ....................... 35
5.4.
5.5.
UART TIMING SPECIFICATIONS .................................................................................................... 36
BLUETOOTH CODEC-PCM(AUDIO) TIMING SPECIFICATIONS .............................................................. 37
6.
CLOCK AND POWER MANAGEMENT .................................................................................. 39
6.1.
6.2.
RESET-POWER-UP SYSTEM ......................................................................................................... 39
WLAN POWER-UP SEQUENCE .................................................................................................... 39
6.3.
BLUETOOTH/BLE/ANT POWER-UP SEQUENCE .............................................................................. 40
7.
REFERENCE SCHEMATIC ......................................................................................................... 41
7.1.
MODULE REFERENCE DESIGN ...................................................................................................... 41
DESIGN RECOMMENDATIONS .............................................................................................. 42
8.
DESIGN NOTE ON DEBUG PORT.................................................................................................... 42
MODULE L AYOUT RECOMMENDATIONS ......................................................................................... 42
8.1.
8.2.
9.
PACKAGE INFORMATION ...................................................................................................... 44
9.1.
9.2.
9.3.
MODULE MECHANICAL OUTLINE.................................................................................................. 44
ORDERING INFORMATION ........................................................................................................... 45
PACKAGE MARKING ................................................................................................................... 46
9.4.
PACKAGING .............................................................................................................................. 47
10.
SMT AND BAKING RECOMMENDATION ......................................................................... 49
10.1.
10.2.
BAKING RECOMMENDATION ............................................................................................. 49
SMT RECOMMENDATION .................................................................................................. 49
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11.
HISTORY CHANGE ............................................................................................................... 50
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1. OVERVIEW
WG7833/31/03/01-B0, a WiFi, BT, BLE SiP (system in package) module, is the most demanded design
for mobile devices, Audio, Computer, PDA and embedded system applications with Wilink8 solution
from TI.
1.1. Models Functional Blocks
Model
WLAN 2.4GHz
WG7833-B0
WLAN 5GHz
BT/BLE/ANT
1.2.General Features
WLAN, Bluetooth, BLE, ANT with Integrated RF Front-End Module (FEM), Power Amplifier (PA),
and Power Management on a Single Module
LGA106 pin package
Dimension 12.8mm(L) x 12.0mm(W) x 1.63mm(H)
Provides efficient direct connection to battery by employing several integrated switched mode
power supplies (DC2DC).
Seamless Integration with TI Sitara™ and Other Application Processors
WLAN and BT/BLE/ANT cores are software and hardware compatible with prior WL127x and
WL128x offerings, for smooth migration to device.
Shared HCI transport for BT/BLE/ANT over UART and SDIO for WLAN.
Temperature detection and compensation mechanism ensures minimal variation in RF
performance over the entire temperature range.
BT 4.0, BLE, ANT and all audio processing features work in parallel and include full coexistence
with WLAN
Operating temperature: –40°C to 85°C
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2. FUNCTIONAL FEATURES
2.1. Module Block Diagram
WiLink8
VBAT_IN
Power
Management
VIO_IN
(5G only for WG7833/03-B0)
32.768KHz
WL 5G TX
SLOW CLK
WL 5G RX
OSC
CLK_REQ_OUT
SW
BPF
SW
BPF
WLAN
26MHz
WLAN 2.4G
FAST CLK
TCXO
BT
WLAN I/F: SDIO
BT
(BT only for WG7833/31-B0)
BT I/F: UART,
PCM, I2S
GPIO’s, Debug
WG7833-B0
Figure 2-1. WG7833-B0 Block Diagram
2.2. Block Functional Feature
2.2.1. WLAN Features
Integrated 2.4 & 5G GHz Power Amplifier (PA) for WLAN solution
WLAN Baseband Processor and RF transceiver Supporting IEEE Std 802.11a/b/g/n
WLAN 2.4/5 GHz SISO (20/40 MHz channels)
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Baseband Processor
 IEEE Std 802.11a/b/g/n data rates and IEEE Std 802.11n data rates with 20 or 40
MHz SISO.
Fully calibrated system. Production calibration not required.
Medium Access Controller (MAC)
Embedded ARM™ Central Processing Unit (CPU)
Hardware-Based Encryption/Decryption using 64-, 128-, and 256-Bit WEP, TKIP
or AES Keys,
Supports requirements for Wi-Fi Protected Access (WPA and WPA2.0) and IEEE
Std 802.11i [includes hardware-accelerated Advanced Encryption Standard
(AES)]
Designed to work with IEEE Std 802.1x
IEEE Std 802.11d,e,h,i,k,r PICS compliant.
New advanced co-existence scheme with BT/BLE/ANT.
2.4/5 GHz Radio
Internal LNA and PA
Supports: IEEE Std 802.11a, 802.11b, 802.11g and 802.11n
Supports 4 bit SDIO host interface, including high speed (HS) and V3 modes.
2.2.2. Bluetooth Features
Supports Bluetooth 4.0 as well as CSA2
Includes concurrent operation and built -in coexisting and prioritization handling of
Bluetooth, BLE, ANT, audio processing and WLAN
Dedicated Audio processor supporting on chip SBC encoding + A2DP:
 Assisted A2DP (A3DP) support - SBC encoding implemented internally
Assisted WB-Speech (AWBS) support - modified SBC codec implemented internally
2.2.3. BLE Features
Fully compliant with BT4.0 BLE dual mode standard
Support for all roles and role-combinations, mandatory as well as optional
Supports up to 10 BLE connections
Independent buffering for LE allows having large number of multiple connections without
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affecting BR/EDR performance
2.2.4. ANT Features
Fully compliant with all ANT Protocols:

 ANT solution optimized for the fitness and health use-cases

 Simple to complex network topologies
Supports high-resolution proximity pairing
The ANT protocol has been designed to very power-efficient, yet is flexible enough to support
various network topologies (point-to-point, star, 1-to-N, N-to-1) and data transfer modes
(broadcast, broadcast with acknowledge, mass data transfer). Each logical ANT channel can be
independently configured for 1-way or 2-way operation
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3. MODULE OUTLINE
3.1. Signal Layout (Top View)
Figure 3-1 Device pins
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3.2. Pin Description
Table 3-1. Pin Description
Pin
No.
A1
Shut
Signal Name
GND
After
Type Down Power
state Up(1)
Voltage
Level
GND
Description
Ground
WLAN SDIO Data bit 3. Changes state to
A2
WLAN_SDIO_D3
IO
HiZ
PU
1.8V
PU at WL_EN or BT_EN assertion for
card detects. Later disabled by software
during initialization. (2)
A3
WLAN_SDIO_CMD
I/O
HiZ
HiZ
1.8V
WLAN SDIO Command (2)
A4
WLAN_SDIO_D2
IO
HiZ
HiZ
1.8V
WLAN SDIO Data bit 2 (2)
A5
WLAN_SDIO_D0
IO
HiZ
HiZ
1.8V
WLAN SDIO Data bit 02)
A6
WLAN_SDIO_D1
IO
HiZ
HiZ
1.8V
WLAN SDIO Data bit 1 (2)
A7
WLAN_SDIO_CLK
IN
HiZ
HiZ
1.8V
A8
GND
A9
BT_HCI_CTS
GND
WLAN SDIO Clock. Must be driven by
the host.
Ground
IN
PU
PU
1.8V
A10 BT_HCI_RTS
OUT
PU
PU
1.8V
A11 BT_HCI_TX
OUT
PU
PU
1.8V
A12 BT_HCI_RX
IN
PU
PU
1.8V
UART CTS from host.
NC if not used.
UART RTS to host.
NC if not used.
UART TX to host.
NC if not used.
UART RX from host.
NC if not used.
A13 NC
NC
A14 NC
NC
A15 NC
NC
A16 GND
GND
NC
A17 NC
A18 GND
Ground
GND
Ground
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A19 VIO_IN
POW
A20 GND
GND
PD
PD
1.8V
Connect to 1.8V external VIO
Ground
B1
NC
NC
B2
NC
NC
B3
GPIO11
I/O
PU
PU
1.8V
Reserved for future use. NC if not used.
B4
GPIO9
I/O
PU
PU
1.8V
Reserved for future use. NC if not used.
B5
GPIO10
I/O
PU
PU
1.8V
Reserved for future use. NC if not used.
B6
GPIO12
I/O
PU
PU
1.8V
Reserved for future use. NC if not used.
B7
NC
NC
B8
NC
NC
B9
NC
NC
B10 NC
NC
B11 NC
NC
B12 NC
NC
B13 NC
NC
B14 NC
NC
B15 NC
NC
B16 NC
NC
C1
GND
C2
NC
NC
C3
NC
NC
C4
BT_UART_DEBUG
C5
NC
C6
WLAN_UART_DBG
OUT
PU
PU
1.8V
Option: WLAN logger
C7
GPIO1
I/O
PD
PD
1.8V
WL_RS232_TX (when IRQ_WL = 1 at
power up)
C8
NC
C9
TCXO_CLK_IN
C10 WLAN_EN
GND
OUT
Ground
PU
PU
1.8V
Option: Bluetooth logger
NC
NC
ANA
IN
TCXO clock input
PD
PD
1.8V
Mode setting: High = enable
SDIO available, interrupt out. Active
C11 WLAN_IRQ
OUT
C12 GND
GND
PD
1.8V
high. To use WL_RS232_TX and RX
lines, need to pull up with 10K
resistor.
Ground
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C13 GND
GND
Ground
C14 GND
GND
Ground
C15 GND
GND
Ground
C16 GND
GND
Ground
D1
GND
GND
Ground
D2
VBAT
POW
D3
NC
NC
D4
NC
NC
D5
NC
NC
D6
GND
D7
NC
D8
GND
GND
Ground
D9
PA_DC2DC_OUT
POW
Internal DC2DC output
VBAT
GND
Power supply input, 2.9 to 4.8 V
Ground
NC
D10 GPIO4
I/O
PD
PD
1.8V
D11 GPIO2
I/O
PD
PD
1.8V
D12 BT_EN
In
PD
PD
1.8V
Reserved for future use. NC if not used.
WL_RS232_RX (when IRQ_WL = 1 at
power up)
Mode setting: High = enable
D13 NC
NC
D14 NC
NC
D15 GND
GND
Ground
D16 GND
GND
Ground
D17 GND
GND
Ground
D18 GND
GND
Ground
D19 RF_ANT_WA
D20 GND
RF
WLAN 5G RF Port
GND
Ground
E1
GND
GND
Ground
E2
GND
GND
Ground
E3
GND
GND
Ground
E4
GND
GND
Ground
F1
GND
GND
Ground
F2
GND
GND
Ground
F3
GND
GND
Ground
F4
GND
GND
Ground
J1
GND
GND
Ground
J2
GND
GND
Ground
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J3
GND
GND
Ground
J4
NC
NC
J5
NC
NC
J6
NC
NC
J7
NC
NC
J8
NC
NC
J9
NC
NC
J10
CLK_REQ_OUT
OUT
J11
GND
GND
Ground
J12
GND
GND
Ground
J13
NC
K1
GND
K2
RF_ANT_BG
K3
GND
GND
Ground
K4
GND
GND
Ground
K5
GND
GND
Ground
K6
GND
GND
Ground
K7
BT_AUD_OUT
OUT
K8
GND
GND
Ground
K9
EXT_32K
ANA
Input Sleep clock: 32.768 KHz
GND
Ground
PD
PD
1.8V
TCXO clock request out
NC
GND
Ground
RF
K10 GND
WLAN/BT 2.4G RF Port
PD
PD
1.8V
Bluetooth PCM/I2S Bus. Data out.
NC if not used.
K11 BT_AUD_IN
IN
PD
PD
1.8V
Bluetooth PCM/I2S Bus. Data in.
NC if not used.
K12 BT_AUD_CLK
OUT
PD
PD
1.8V
Bluetooth PCM/I2S Bus. Clock.
NC if not used.
K13 BT_AUD_FSYNC
OUT
PD
PD
1.8V
Bluetooth PCM/I2S Bus. Frame sync.
NC if not used.
(1) PU=pull up; PD=pull down.
(2) Host must provide PU for all non-CLK SDIO signals
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4. MODULE SPECIFICATION
4.1. General Module Requirements and Operation
4.1.1. Absolute Maximum Ratings (1)
Parameter
Value
(2)
Units
VBAT
-0.5 to 5.5
VIO
-0.5 to 2.1
Input voltage to Analog pins
-0.5 to 2.1
Input voltage limits (CLK_IN)
-0.5 to VDD_IO
Input voltage to all other pins
-0.5 to (VDD_IO + 0.5V)
Operating ambient temperature range
-40 to +85
(3)
°C
Storage temperature range
-55 to +125
°C
>1000
>250
ESD Stress Voltage
(4)
Human Body Model
(5)
Charged Device Model
1)
(6)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated
under “operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
2)
5.5V up to 10s cumulative in 7 years, 5V cumulative to 250s, 4.8V cumulative to 2.33 years - all includes charging
dips and peaks.
3)
Operating free-air temperature range. The device can be reliably operated for 7 years at ambient of 85°C, assuming
25% active mode and 75% sleep mode (15,400 cumulative active power-on hours).
4) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges
into device.
5) Level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows
safe manufacturing with a standard ESD control process, and manufacturing with less than 500V HBM is possible if
necessary precautions are taken. Pins listed as 1000V may actually have higher performance.
6) Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows
safe
manufacturing with a standard ESD control process, and manufacturing with less than 250V CDM is possible if
necessary precautions are taken. Pins listed as 250 V may actually have higher performance
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4.1.2. Recommended Operating Conditions
Parameter
VBAT
Condition
(1)
Sym
DC supply range
Min
Max
2.9
4.8
1.62
1.95
Units
for all modes
1.8 V IO ring power supply voltage
IO high-level input voltage
VIH
0.65 x VDD_IO
VDD_IO
IO low-level input voltage
VIL
0.35 x VDD_IO
Enable inputs high-level input
VIH_EN
1.365
VDD_IO
VIL_EN
0.4
VOH
VDD_IO -0.45
VDD_IO
@ 1 mA
VDD_IO -0.112
VDD_IO
@ 0.3 mA
VDD_IO -0.033
VDD_IO
0.45
@ 1 mA
0.112
@ 0.09 mA
0.01
10
ns
ns
voltage
Enable inputs low-level input
voltage
High-level output voltage
@ 4 mA
Low-level output voltage
@ 4 mA
Input transitions time Tr/Tf from
10% to 90% (Digital IO)
CL < 25 pF
Tr
5.3
CL < 25 pF
Tf
4.9
(2)
Output fall time from 10% to 90%
(Digital pins)
Tr/Tf
(2)
Output rise time from 10% to 90%
(Digital pins)
VOL
(2)
Ambient operating temperature
Maximum power dissipation
-40
85
ºC
WLAN operation
2.8
BT operation
0.2
(1)
4.8V is applicable only for 2.3 years (30% of the time). Otherwise, the maximum VBAT should not exceed 4.3V.
(2)
Applies to all Digital lines except SDIO, UART, I2C, PCM and slow clock lines
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4.1.3. External Slow Clock Input (SLOW_CLK)
The supported digital slow clock is 32.768 kHz digital (square wave).
Parameter
Condition
Sym
Min.
Input slow clock Frequency
Typ.
Max.
Units
32.768
KHz
Input slow clock accuracy
WLAN, BT
+/-250
(Initial + temp + aging)
ANT
+/- 50
ppm
Input Transition time Tr/Tf
Tr/Tf
100
ns
85
10% to 90%
Frequency input duty Cycle
15
Input Voltage Limits
50
0.65x
Vih
VDD_IO
VDD_IO
Square Wave,
Vpeak
DC-coupled
0.35x
Vil
VDD_IO
Input Impedance
MΩ
Input Capacitance
pF
4.1.4. External Fast Clock Requirements (-40 to +85°°C)
Parameter
Condition
Min.
Frequency
Typ.
Max.
26
Frequency Accuracy
Unit
MHz
Short term (voltage and temp. effect)
± 20
Long term (including aging)
± 20
ppm
Input voltage limits
Sine wave/ clipped sine wave,
2.4GHz WLAN
0.2
1.4
(TCXO_CLK_IN)
ac-coupled
5GHz WLAN
0.8
1.4
Input impedance
Input resistance
20
KΩ
Input capacitance
2.5
pF
Vp-p
(1)
Power-up time
ms
Phase noise 2.4GHz
Measured at 1 KHz offset
-123.4
dBc/Hz
for 26MHz, 20MHz
Measured at 10 KHz offset
-133.4
dBc/Hz
SISO
Measured at 100 KHz offset
-138.4
dBc/Hz
Phase noise 2.4GHz
Measured at 1 KHz offset
-128.4
dBc/Hz
for 26MHz, 40MHz
Measured at 10 KHz offset
-135.4
dBc/Hz
SISO
Measured at 100 KHz offset
-139.9
dBc/Hz
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Phase noise 5GHz for
Measured at 1 KHz offset
-128.4
dBc/Hz
26MHz, 20/40 MHz
Measured at 10 KHz offset
-145.4
dBc/Hz
SISO
Measured at 100 KHz offset
-148.4
dBc/Hz
(1) Power-up time is calculated from the time CLK_REQ_OUT asserted till the time the TCXO_CLK amplitude is within
voltage limit specified above and TCXO_CLK frequency is within 0.1 ppm of final steady state frequency.
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4.2. WLAN RF Performance
4.2.1. WLAN 2.4-GHz Receiver Characteristics
Parameter
Condition
Operation frequency range
Sensitivity
Min
Typ
2412
Max
Units
2484
MHz
dBm
1 Mbps DSSS
-96.3
-93.4
2 Mbps DSSS
-93.2
-90.5
20MHz Bandwidth
5.5 Mbps CCK
-90.6
-87.9
At < 10% PER limit
11 Mbps CCK
-87.9
-85.7
6 Mbps OFDM
-92
-89.2
9 Mbps OFDM
-90.4
-87.7
12 Mbps OFDM
-89.5
-86.8
18 Mbps OFDM
-87.2
-84.5
24 Mbps OFDM
-84.1
-81.4
36 Mbps OFDM
-80.7
-78
48 Mbps OFDM
-76.5
-73.8
54 Mbps OFDM
-74.9
-72.4
MCS0 MM 4K
-90.4
-87.4
MCS1 MM 4K
-87.6
-84.9
MCS2 MM 4K
-85.9
-83.2
MCS3 MM 4K
-82.8
-80.1
MCS4 MM 4K
-79.4
-76.7
MCS5 MM 4K
-75.2
-72.5
MCS6 MM 4K
-73.5
-70.8
MCS7 MM 4K
-72.4
-69.7
MCS0 MM 4K 40MHz
-87.4
-82.7
MCS7 MM 4K 40MHz
-69
-65.5
Max Input Level
OFDM(11g/n)
-19
-9
At < 10% PER limit
CCK
-4
Adjacent channel rejection
2Mbps DSSS
42.7
Sensitivity level +3dB for OFDM, Sensitivity
11Mbps CCK
37.9
level +6dB for 11b
54Mbps OFDM
2.0
dBm
LO Leakage
-80
PER Floor
1.0
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dBm
2.0
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Doc No: WG7833-B0-DTS-R03
4.2.2. WLAN 2.4-GHz Transmitter Power
Parameter
Condition
Min
Typ
Max
Output Power
1 Mbps DSSS
15
17
–
- Maximum RMS output power
2 Mbps DSSS
15
17
–
measured at 1dB from IEEE
5.5 Mbps CCK
15
17
–
spectral mask or EVM
11 Mbps CCK
15
17
–
6 Mbps OFDM
15
17
–
9 Mbps OFDM
15
17
–
12 Mbps OFDM
15
17
–
18 Mbps OFDM
15
17
–
24 MbpS OFDM
14
16.2
–
36 Mbps OFDM
13.1
15.3
–
48 Mbps OFDM
12.4
14.6
–
54 Mbps OFDM
11.8
13.8
–
MCS0 MM
13.9
16.1
MCS1 MM
13.9
16.1
MCS2 MM
13.9
16.1
MCS3 MM
13.9
16.1
MCS4 MM
13.3
15.3
MCS5 MM
12.4
14.6
MCS6 MM
11.8
13.8
MCS7 MM
10.6
12.6
MCS0 MM 40MHz
12.3
14.8
MCS7 MM 40MHz
10.2
12.2
Output power accuracy
-1.5
Output power resolution
Operation frequency range
+1.5
0.125
2412
dBm
dB
dB
2484
MHz
Return loss
-10
dB
Reference input impedance
50
Ω
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4.2.3. WLAN 5-GHz Receiver Characteristics (For WG7833/03 Only)
Parameter
Condition
Operation frequency range
Min
Typ
4910
Max
Units
5825
MHz
Sensitivity
6 Mbps OFDM
–
-91.5
-87.6
- 20MHz bandwidth.
9 Mbps OFDM
–
-89.7
-85.7
- At < 10% PER limit
12 Mbps OFDM
–
-88.9
-84.9
18 Mbps OFDM
–
-86.4
-82.4
24 Mbps OFDM
–
-83.3
-79.3
36 Mbps OFDM
–
-79.9
-75.9
48 Mbps OFDM
–
-75.6
-71.6
54 Mbps OFDM
–
-74.0
-70.5
MCS0 MM 4K
–
-89.8
-85.4
MCS1 MM 4K
–
-87.0
-83.0
MCS2 MM 4K
–
-85.2
-81.2
MCS3 MM 4K
–
-82.1
-78.1
MCS4 MM 4K
–
-78.7
-74.7
MCS5 MM 4K
–
-74.4
-70.4
MCS6 MM 4K
–
-72.8
-68.8
MCS7 MM 4K
–
-71.5
-67.9
MCS0 MM 4K 40MHz
–
-87.0
-81.8
MCS7 MM 4K 40MHz
–
-68.3
-64.4
-9
Max Input Level, At < 10% PER limit
OFDM(11a/n)
-27
Adjacent channel rejection
54Mbps OFDM
dBm
Sensitivity level +3dB for OFDM
dBm
LO Leakage
-53
PER Floor
1.0
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2.0
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4.2.4. WLAN 5-GHz Transmitter Power (For WG7833/03 Only)
Parameter
Condition
Min
Typ
Max
Output Power
6 Mbps OFDM
14.7
16.8
–
- Maximum RMS output power
9 Mbps OFDM
14.7
16.8
–
measured at 1dB from IEEE
12 Mbps OFDM
14.7
16.8
–
spectral mask or EVM
18 Mbps OFDM
14.7
16.8
–
24 MbpS OFDM
14.1
15.7
–
36 Mbps OFDM
13.4
15.0
–
48 Mbps OFDM
12.6
14.2
–
54 Mbps OFDM
11.6
13.4
–
MCS0 MM
14.4
16.4
MCS1 MM
14.4
16.4
MCS2 MM
14.4
16.4
MCS3 MM
14.4
16.4
MCS4 MM
13.2
15.0
MCS5 MM
12.6
14.2
MCS6 MM
11.6
13.4
MCS7 MM
10.7
12.4
MCS0 MM 40MHz
13.0
15.9
MCS7 MM 40MHz
9.7
11.6
Output power accuracy
-1.5
Output power resolution
Operation frequency range
+1.5
0.125
4910
dBm
dB
dB
5825
MHz
Return loss
-10
dB
Reference input impedance
50
Ω
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Doc No: WG7833-B0-DTS-R03
4.3. Bluetooth RF Performance (For WG7833/31 Only)
4.3.1. BT Receiver Characteristics, In-Band Signals
Parameter
Condition
Min
Typ
Max
BT
Units
Spec
BT BR, EDR operation
2402
2480
MHz
frequency range
BT BR, EDR channel spacing
MHz
BT BR, EDR input
50
Ω
impedance
BT BR, EDR sensitivity
(1)
Dirty TX on
BR, BER = 0.1%
-92.0
-70
EDR2, BER = 0.01%
-91.5
-70
EDR3, BER = 0.01%
-84.5
-70
BT EDR BER floor at
EDR2
1e-6
1e-5
sensitivity + 10 dB, dirty TX
EDR3
1e-6
1e-5
BR, BER = 0.1%
-5.0
-20
EDR2, BER = 0.1%
-10.0
-20
EDR3, BER = 0.1%
-10.0
-20
BT BR intermodulation
Level of interferers For n = 3, 4, and 5
-36.0
BT BR, EDR C/I performance
BR, Co-channel
dBm
off (for 1,600,000 bits)
BT BR, EDR maximum
dBm
useable input power
EDR, Co-channel
Numbers show
wanted-signal to
interfering-signal ratio.
Smaller numbers indicate
-39
dBm
8.0
11
dB
EDR2
9.5
13
EDR3
16.5
21
-10.0
BR, adjacent ±1 MHz
EDR, adjacent ±1 MHz,
EDR2
-10.0
(image)
EDR3
-5.0
-38.0
-30
EDR2
-38.0
-30
EDR3
-38.0
-25
-28.0
-20
EDR2
-28.0
-20
EDR3
-22.0
-13
better C/I performances
(Image frequency = -1MHz)
-30.0
BR, adjacent +2 MHz
EDR, adjacent +2 MHz,
BR, adjacent -2 MHz
EDR, adjacent
-2 MHz
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BR, adjacent
≥Ι±3Ι MHz
-45.0
-40
EDR, adjacent ≥Ι±3Ι
EDR2
-45.0
-40
MHz
EDR3
-44.0
-33
BT BR, EDR RF return loss
-10.0
dB
(1) Sensitivity degradation up to -3dB may occur due to fast clock harmonics with dirty TX on.
4.3.2. BT Receiver Characteristics – General Blocking
Condition
Parameter
Blocking performance over full range,
according to BT specification
(1)
Min
Typ
BT spec
30-2000 MHz
-6
-10
2000-2399 MHz
-6
-27
2484-3000 MHz
-6
-27
3-12.75 GHz
-6
-10
Units
dBm
1) Exceptions taken out of the total 24 allowed in the BT spec.
4.3.3. BT Receiver Characteristics –BR, EDR Blocking Per Band
Parameter
Band
Min
Typ
-12
Blocking performance for various cellular
776-794 MHz
(CDMA)
bands
824-849 MHz
(GMSK)
824-849 MHz
(EDGE)
824-849 MHz
(CDMA, QPSK)
880-915 MHz
(GMSK)
-14
880-915 MHz
(EDGE)
-15
Hopping on.
Wanted signal: -3dB from sensitivity, with
Units
(1)
-3
(1)
-11
(1)
modulated continuous blocking signal.
-12
BER = 0.1% for BT BR, 0.01% for BT EDR.
PER = 1%
1710-1785 MHz
(GMSK)
-4
1710-1785 MHz
(EDGE)
-18
1850-1910 MHz
(GMSK)
-18
1850-1910 MHz
(EDGE)
-20
1850-1910 MHz
(CDMA, QPSK)
-20
1850-1910 MHz
(WCDMA, QPSK)
-16
1920-1980 MHz
(WCDMA, QPSK)
-17
dBm
1) Except for frequencies where [3 * F_BLOCKER] falls within the BT band (2400-2483.5 MHz)
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4.3.4. BT Transmitter, BR
Parameter
BR RF output power
Min
(1)
Typ
VBAT >= 3V
12.5
VBAT < 3V
7.0
BR Gain Control Range
Max
BT Spec
dBm
30
BR Power Control Step
Units
dB
2 to 8
BR Adjacent Channel Power |M-N| = 2
(2)
-43.0
≤ -20
BR Adjacent Channel Power |M-N| > 2
(2)
-48.0
≤ -40
dBm
1)
Values reflect maximum power. Reduced power is available using a vendor-specific (VS) command.
2)
Assumes 3dB insertion loss on external filter and traces
4.3.5. BT Transmitter, EDR
Min
Parameter
EDR output power
(1)
Typ
VBAT >= 3V
VBAT < 3V
EDR relative power
Max
-4 to +1
dB
30
EDR Power Control Step
Units
dBm
-2
EDR Gain Control Range
BT Spec
dB
2 to 8
dB
-36
≤ -26
dBc
(2)
-30
≤ -20
dBm
(2)
-42
≤ -40
EDR Adjacent Channel Power |M-N| = 1
(2)
EDR Adjacent Channel Power |M-N| = 2
EDR Adjacent Channel Power |M-N| > 2
1)
Values reflect maximum power. Reduced power is available using a vendor-specific (VS) command.
2)
Assumes 3dB insertion loss on external filter and traces.
4.3.6. BT Modulation, BR
Condition(1)
Parameter
Performances
Min
BR -20dB Bandwidth
Mod data = 4-ones,
BT
Typ
Max
spec
925
995
≤1000
160
kHz
4-zeros: 111100001111...
∆f2max ≥ limit for
characteristics
at least 99.9% of all
kHz
140 to
∆f1avg
BR modulation
Units
175
> 115
Mod data = 1010101...
130
kHz
Δf2max
∆f2avg / ∆f1avg
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> 80
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Doc No: WG7833-B0-DTS-R03
BR carrier frequency
One slot packet
-25
+25
< ±25
kHz
drift
Three and five slot packet
-35
35
< ±40
kHz
15
< 20
kHz/
BR drift rate
lfk+5 – fkl , k = 0 …. max
50μs
BR initial carrier
frequency tolerance
(2)
f0 – fTX
-25
25
< ±75
kHz
1) Performance figures at maximum power
2) This number is added on top of the reference clock frequency accuracy
4.3.7. BT Modulation, EDR
Parameter (1)
Condition
EDR Carrier frequency stability
EDR Initial Carrier Frequency Tolerance
(2)
EDR RMS DEVM
EDR 99% DEVM
EDR Peak DEVM
Min
Typ.
Max
BT spec Units
-5
≤10
kHz
-25
25
±75
kHz
EDR2
20
EDR3
13
EDR2
30
30
EDR3
20
20
EDR2
35
EDR3
25
1) Performance figures at maximum power
2) This number is added on top of the reference clock frequency accuracy
4.3.8. BT BR, EDR Transceiver - Emissions
Parameter (1)
Condition (2)
Performances
Min
Typ
Units
Max
-151
dBm/Hz
(WCDMA, GSM)
-149
dBm/Hz
(E-GSM)
-148
dBm/Hz
1570-1580 MHz
(GPS)
-145
dBm/Hz
1598-1607 MHz
(GLONASS)
-145
dBm/Hz
1805-1880 MHz
(DCS, WCDMA)
-141
dBm/Hz
1930-1990 MHz
(PCS)
-139
dBm/Hz
BT out-of-band
746-768 MHz
(CDMA)
emission
869-894 MHz
925-960 MHz
BR, EDR
(3)
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BR
-134
dBm/Hz
EDR
-129
dBm/Hz
2nd harmonic
1.5
dBm
3rd harmonic
-4
dBm
4th harmonic
-10
dBm
2110-2170 MHz
BT harmonics
(WCDMA)
1)
Meets FCC and ETSI requirements with suitable external filter
2)
Performance figures at maximum power
3)
Except for frequencies that corresponds to 2*RF_FREQ/3
4.3.9. BT BR Transceiver - Spurs
Parameter (1)
Condition (2)
Performances
Min
BT out-of-band spurs
76-108 MHz
(FM)
BR
Typ
Units
Max
-77
dBm
746-768 MHz
(WCDMA)
-79
dBm
869-894 MHz
(WCDMA, GSM)
-77
dBm
925-960 MHz
(E-GSM)
-77
dBm
1570-1580 MHz
(GPS)
-72
dBm
1598-1607 MHz
(GLONASS)
-74
dBm
1805-1880 MHz
(DCS, WCDMA)
-72
dBm
1930-1990 MHz
(PCS)
-70
dBm
2110-2170 MHz
(WCDMA)
-59
dBm
(3)
1)
Meets FCC and ETSI requirements with suitable external filter
2)
Performance figures at maximum power
3)
Except for frequencies that corresponds to 2*RF_FREQ/3
4.3.10. BT EDR Transceiver - Spurs
Parameter(1)
Condition (2)
Performances
Min
BT out-of-band spurs
76-108 MHz (FM)
EDR
Typ
Units
Max
-82
dBm
746-768 MHz (WCDMA)
-87
dBm
869-894 MHz (WCDMA, GSM)
-85
dBm
925-960 MHz (E-GSM)
-84
dBm
1570-1580 MHz (GPS)
-79
dBm
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Doc No: WG7833-B0-DTS-R03
1598-1607 MHz (GLONASS)
(3)
-78
dBm
1805-1880 MHz (DCS, WCDMA)
-76
dBm
1930-1990 MHz (PCS)
-74
dBm
2110-2170 MHz (WCDMA)
-63
dBm
1) Meets FCC and ETSI requirements with suitable external filter
2) Performance figures at maximum power
3) Except for frequencies that corresponds to 2*RF_FREQ/3
4.4. BT LE RF Performance
4.4.1. BT LE Receiver Characteristics, In-Band Signals
Condition (2)
Parameter
Min
BT LE Operation frequency range
Typ
2402
Max
BLE spec Units
2480
MHz
BT LE Channel spacing
MHz
BT LE Input impedance
50
Ω
(1)
-93
BT LE Sensitivity , Dirty Tx on
BT LE Maximum useable input power
BT LE Intermodulation characteristics
-5
-30
-36
Level of interferers. For
≤ -70
dBm
≥ -10
dBm
≥ -50
dBm
dB
n = 3, 4, 5
BT LE C/I performance Note:
LE, co-channel
12
≤ 21
Numbers show wanted
LE, adjacent ±1MHz
-5
≤ 15
signal-to-interfering signal ratio.
LE, adjacent +2MHz
-45
-38
≤ -17
LE, adjacent –2MHz
-22
-15
≤ -15
LE, adjacent ≥ |±3|MHz
-47
-40
≤ -27
Smaller numbers indicate better C/I
performance. Image = -1MHz
1) Sensitivity degradation up to -3dB may occur due to fast clock harmonics.
2) BER of 0.1% corresponds to PER of 30.8% for a minimum of 1500 transmitted packets, according to BT LE test spec
4.4.2. BT LE Receiver Characteristics – General Blocking
Parameter
Condition
Min
Typ
Max
BLE
spec
BT LE Blocking performance over
30–2000MHz
-15
≥ –30
full range, according to LE
2000–2399MHz
-15
≥ –35
2484–3000MHz
-15
≥ –35
specification
Unit
dBm
(1)
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Doc No: WG7833-B0-DTS-R03
-15
3–12.75GHz
≥ –30
1) Exceptions taken out of the total 10 allowed for fbf_1, according to the BT LE Spec
4.4.3. BT LE Transmitter Characteristics
Parameter
Min
Typ
Max
BT LE
Unit
Spec
BT LE RF output power
(1)
Vbat >= 3V
12.5
≤10
dBm
Vbat < 3V
870
≤10
dBm
dBm
BT LE Adjacent Channel Power |M-N| = 2
(2)
-51.0
≤ –20
BT LE Adjacent Channel Power |M-N| > 2
(2)
-54.0
≤ –30
1)
To reduce the maximum BLE power, use a VS command. The optional extra margin is offered to compensate for
design losses, such as trace and filter losses, and to achieve the maximum allowed output power at system level.
2)
Assumes 3dB insertion loss on external filter and traces
4.4.4. BT LE Modulation Characteristics
Condition (1)
Parameter
Performances
Min
Typ
Max
BT
Spec
Units
Mod data =
225 to
∆f1avg
4-ones, 4-zeros:
250
kHz
275
111100001111...
BT LE modulation
characteristics
∆f2max ≥ limit for at
Mod data =
least 99.9% of all Δf2max
1010101...
215
∆f2avg / ∆f1avg
≥185
kHz
≥80
25
≤±50
kHz
15
≤20
90
BT LE carrier frequency
lf0 – fnl , n = 2,3 …. K
-25
drift
kHz/
BT LE drift rate
lf1 – f0l and lfn – fn-5l ,n = 6,7…. K
50μs
LE initial carrier
frequency tolerance
(2)
fn – fTX
-25
25
≤±100
kHz
1) Performance figures at maximum power
2) This number is added on top of the reference clock frequency accuracy
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4.4.5. BT LE Transceiver – Emissions
See Section 4.3.8, BT BR, EDR Transceiver – Emissions.
4.4.6. BT LE Transceiver - Spurs
See Section 4.3.9, BT BR Transceiver – Spurs.
4.5. ANT Performance
4.5.1. ANT Receiver Characteristics, In-Band Signals
Parameter
Condition
ANT Operation frequency range
Min
2402
ANT Channel spacing
ANT Sensitivity
Typ
12.72% PER
(1)
Max
Units
2480
MHz
MHz
-85
dBm
1) Translation from BER=0.1%, assuming packet is 136 bits ( not including preamble )
4.5.2. ANT Transmitter Characteristics
Same as Bluetooth BR Transmitter Characteristics
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4.6. POWER CONSUMPTION
4.6.1. Shutdown and Sleep Currents
Parameter
Power Supply Current
Typ
Unit
uA
Shutdown mode
VBAT
10
All functions shut down.
VIO
WLAN sleep mode
VBAT
154
BT sleep mode
VBAT
110
4.6.2. WLAN Power Currents
Parameter
LPM
Receiver
Transmitter
Conditions
Typ (avg) - 25C
Units
2.4GHz RX LPM
43
mA
2.4GHz RX search SISO20
48
mA
2.4GHz RX search SISO40
53
mA
5GHz RX search SISO20
54
mA
5GHz RX search SISO40
58
mA
2.4GHz RX 20M SISO 11CCK
50
mA
2.4GHz RX 20M SISO 6OFDM
55
mA
2.4GHz RX 20M SISO MCS7
59
mA
2.4GHz RX 40MHz MCS7
71
mA
5GHz RX 20MHz 6OFDM
62
mA
5GHz RX 20MHz MCS7
67
mA
5GHz RX 40MHz MCS7
79
mA
2.4GHz TX 20M SISO 6OFDM 16.4dBm
285
mA
2.4GHz TX 20M SISO 11CCK 16.5dBm
273
mA
2.4GHz TX 20M SISO 54OFDM 13.1dBm
247
mA
2.4GHz TX 20M SISO MCS7 12.2dBm
238
mA
2.4GHz TX 40M SISO MCS7 11.8dBm
243
mA
5GHz TX 20M SISO 6OFDM 16.8dBm
366
mA
5GHz TX 20M SISO 54OFDM 13.4dBm
329
mA
5GHz TX 20M SISO MCS7 12.7dBm
324
mA
5GHz TX 40M SISO MCS7 11.9dBm
332
mA
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4.6.3. Bluetooth Currents
Current measurements are done at the following output power: BR at 12.5dBm, EDR at 7dBm.
Use Case (1)
Typ
Units
BR Voice HV3 + sniff
11.6
mA
EDR Voice 2-EV3 no retrans. + sniff
5.9
mA
Sniff 1 attempt 1.28s
178
uA
EDR A2DP EDR2 (master). SBC high quality – 345Kbs
10.4
mA
EDR A2DP EDR2 (master). MP3 high quality – 192Kbs
7.5
mA
(2) (3)
18
mA
(3)
50
mA
33
mA
Page or inquiry 1.28s/11.25ms
253
uA
P&I Scan (P=1.28/I=2.56)
332
uA
Typ
Units
131
uA
143
uA
266
uA
124
uA
132
uA
Full throughput ACL RX: RX-2DH5
Full throughput BR ACL TX: TX-DH5
Full throughput EDR ACL TX: TX-2DH5
(3)
1) BT role in all scenarios is Slave, except for A2DP
2) ACL RX has same current in all modulations
3) Full throughput assumed data transfer in one direction
4.6.4. Bluetooth LE Currents
All current measurements are done at output power of 8dBm
Use Case
Advertising, non-connectable
Advertising, discoverable
Scanning
(1)
(1)
(2)
Connected, master role, 1.28sec conn. Interval
Connected, slave role, 1.28sec conn. Interval
(3)
(3)
1) Advertising in all 3 channels, 1.28sec advertising interval, 15 Bytes advertise data.
2) Listening to a single frequency per window, 1.28sec scan interval, 11.25msec scan window.
3) Zero Slave connection latency Empty Tx/Rx LL packets.
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4.6.5. ANT Currents
Use Case
Conditions
Typ
Units
ANT Rx message mode
250ms interval
360
uA
ANT Rx message mode
500ms interval
220
uA
ANT Rx message mode
1000ms interval
150
uA
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5. HOST INTERFACE TIMING CHARACTERISTICS
The following table summarizes the Host Controller interface options. All interfaces operate
independently.
WLAN
Shared HCI for all functional
BT Voice/Audio
blocks except WLAN
WLAN HS SDIO
Over UART
BT PCM
The device incorporates UART module dedicated to the BT shared-transport Host Controller
Interface (HCI) transport layer. The HCI interface is used to transport commands, events and ACL
between the Bluetooth device and its host using HCI data packets. This acts as a shared transport for
all functional blocks except WLAN.
5.1. WLAN SDIO Transport Layer
The SDIO is the host interface for WLAN. The interface between the host and the WG7835-T0 uses
an SDIO interface and supports a maximum clock rate of 50MHz.
The Device SDIO also supports the following features of the SDIO V3 specification:

 4 bit data bus

 Synchronous and Asynchronous In-Band-Interrupt
Default and High-Speed (50MHz) timing
Sleep/wake commands
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5.2. SDIO Timing Specifications
5.2.1. SDIO Switching Characteristics – Default Rate
Figure 5-1. SDIO default input timing
Figure 5-2. SDIO default output timing
Table 5-1. SDIO Default Timing Characteristics(1)
PARAMETER(2)
MIN
MAX
UNIT
Fclock
Clock frequency, CLK
26
MHz
DC
Low/high duty cycle
40
60
tTLH
Rise time, CLK
10
ns
tTHL
Fall time, CLK
10
ns
tISU
Setup dme, input valid before CLK↑
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tIH
Hold dme, input valid afer CLK↑
tODLY
Delay dme, CLK↓ to output valid
2.5
CI
Capacitive load on outputs
ns
14.8
ns
15
pF
(1) To change the data out clock edge from the falling edge (default) to the rising edge, set the configuration bit.
(2) Parameter values reflect maximum clock frequency.
5.2.2. SDIO Switching Characteristics – High Rate
Figure 5-3. SDIO HS input timing
Figure 5-4. SDIO HS output timing
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Table 5-2. SDIO HS Timing Characteristics
PARAMETER
MIN
MAX
UNIT
Fclock
Clock frequency, CLK
50
MHz
DC
Low/high duty cycle
40
60
tTLH
Rise time, CLK
ns
tTHL
Fall time, CLK
ns
tISU
Setup dme, input valid before CLK↑
ns
tIH
Hold dme, input valid afer CLK↑
ns
tODLY
Delay dme, CLK↓ to output valid
2.5
CI
Capacitive load on outputs
14
ns
10
pF
5.3. HCI UART Shared Transport Layers for All Functional Blocks (Except WLAN)
The HCI UART supports most baud rates (including all PC rates) for all fast clock frequencies - up
to a maximum of 4 Mbps. After power up the baud rate is set for 115.2 kbps, regardless of fast
clock frequency. The baud rate can then be changed by using a VS command. The Device
responds with a Command Complete Event (still at 115.2 kbps), after which the baud rate change
occurs.
HCI hardware includes the following features:

 Receiver detection of break, idle, framing, FIFO overflow and parity error conditions.

 Receiver Transmitter underflow detection.

 CTS/RTS hardware flow control.

 4 wires (H4)
The below table lists the UART default settings
Table 5-3. UART Default Setting
Parameter
Value
Bit Rate
115.2 kbps
Data Length
8 bits
Stop Bit
Parity
None
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5.3.1. UART 4-Wires Interface – H4
The interface includes four signals: TXD, RXD, CTS and RTS. Flow control between the host and
the Device is byte-wise by hardware. ( See Figure 5-5 )
Figure 5-5. HCI UART Connection
When the UART RX buffer of the device passes the flow-control threshold, the buffer sets the
UART_RTS signal high to stop transmission from the host. When the UART_CTS signal is set high,
the device stops transmitting on the interface. If HCI_CTS is set high in the middle of transmitting
a byte, the device finishes transmitting the byte and stops the transmission.
5.4. UART Timing Specifications
Figure 5-6. UART Timing Diagram
Table 5-4. UART Timing Characteristics
Characteristic
Condition
Symbol
Baud rate
Min
Typ
Max
Unit
37.5
4364
Kbps
Baud rate accuracy per byte
RX/TX
-2.5
+1.5
Baud rate accuracy per bit
RX/TX
-12.5
+12.5
CTS low to TX_DATA on
t3
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CTS low to TX_DATA off
Hardware flow control
t4
CTS High Pulse Width
t6
RTS low to RX_DATA on
t1
RTS high to RX_DATA off
Interrupt set to 1/4 FIFO
STR-Start bit;
bit
us
t2
16
D0..Dn - Data bits (LSB first); PAR - Parity bit (if used);
Byte
Bytes
STP - Stop bit
Figure 5-7. UART Data Frame
5.5. Bluetooth Codec-PCM(Audio) Timing Specifications
Figure 5-8 shows the Bluetooth codec-PCM (audio) timing diagram.
Table 5-5 lists the Bluetooth codec-PCM master timing characteristics.
Table 5-6 lists the Bluetooth codec-PCM slave timing characteristics.
Figure 5-8. PCM Interface Timing
Table 5-5. Bluetooth Codec-PCM Master Timing Characteristics
Parameter
Symbol
Min
Max
Cycle time
Tclk
166.67 (6.144MHz)
15625 (64 kHz)
High or low pulse width
Tw
35% of Tclk min
AUD_IN setup time
tis
10.6
AUD_IN hold time
tih
AUD_OUT propagation time
top
15
AUD_FSYNC_OUT propagation time
top
15
Capacitive loading on outputs
Cl
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40
Unit
ns
pF
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Table 5-6. Bluetooth Codec-PCM Slave Timing Characteristics
Parameter
Symbol
Min
Cycle time
Tclk
81 (12.288MHz)
High or low pulse width
Tw
35% of Tclk min
AUD_IN setup time
tis
AUD_IN hold time
tih
AUD_OUT propagation time
top
AUD_FSYNC_OUT propagation time
top
Capacitive loading on outputs
Cl
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Max
Unit
ns
19
40
pF
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6. CLOCK AND POWER MANAGEMENT
The slow clock is a free-running, 32.768 kHz clock supplied from an external clock source. The
clock is connected to the RTC_CLK pin and is a digital square-wave signal in the range of 0 to 1.8V
nominal
6.1. Reset-Power-Up System
After VBAT and VIO are fed to the device and while BT_EN and WL_EN are deasserted (low), the
device is in SHUTDOWN state, during which functional blocks, internal DC-DCs, and LDOs are
disabled. The power supplied to the functional blocks is cut off. When one of the signals (BT_EN
or WL_EN) are asserted (high), a power-on reset (POR) is performed. Stable slow clock, VIO, and
VBAT are prerequisites for a successful POR.
6.2. WLAN Power-Up Sequence
Figure 6-1 shows the WLAN power-up sequence.
Figure 6-1. WLAN Power-Up Sequence
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6.3. Bluetooth/BLE/ANT Power-Up Sequence
Figure 6-2 shows the Bluetooth/BLE/ANT power-up sequence.
Figure 6-2 Bluetooth/BLE/ANT power-up sequence
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7. REFERENCE SCHEMATIC
7.1. Module Reference Design
VIO_IN
Must reserve PU cricuit
for Debug.
R1
NL_10K
RES1005
WLAN_IRQ_1V8
VDD_TCXO_OUT
TCXO1
TCXO/2016/26MHz
TCXO-2.0X1.6
GND OUT
VCC
GND
WL_EN_1V8
C1
33pF
CAP1005
R2
0R
RES1005
50 ohms single ended
VBAT_IN
R3
BT_EN_1V8
0R RES1005
J1
U.FL-R-SMT-1(10)
U.FL
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
GND
D19
D18
D20
GND
D16
D15
D17
NL
GND
NL
GND
NL
GND
NL
BT_AUD_OUT
U1
WG7833_03_31_01-B0 D01 Module
E-12X12.8-0.6-TOP
GND
SLOW_CLK
GND
GND
BT_AUD_IN
GND
BT_AUD_CLK
NL
BT_AUD_FSY NC
GND
GND
Pi-Circuit for Antenna matching.
C10
NL_10pF
CAP1005
K1
K3
C12
10pF
CAP1005
C11
10pF
CAP1005
K2
Reserved for RF test.
Closed to Module.
K4
L3
NL
IND1005
K5
K7
R4
BT_PCM_AUD_OUT
0R RES1005
Pi-Circuit for Antenna matching.
K8
K9
EXT_32K
For BT (WG7833/31)
HOST_SLOWCLK_1V8
R5
0R
RES1005
K10
K11
R7
0R RES1005
BT_PCM_AUD_IN
K12
R8
0R RES1005
BT_PCM_AUD_CLK
K13
R10
0R RES1005
BT_PCM_AUD_FSY NC
R9
0R
RES1005
R12
0R RES1005
R14
0R RES1005
SDIO_D0_1V8
R15
0R RES1005
SDIO_D1_1V8
R16
0R RES1005
SDIO_CLK_1V8
R18
GND
VCC
C16
0.1uF
CAP1005
F3
32.768KHz source select
F4
NL
NL
F2
CLK_REQ_OUT_1833
0R RES1005
SDIO_D2_1V8
VIO_IN
OSC1
OSC/3225/32.768kHz
OUT
EN
F1
VBAT_IN
R11
SDIO_CMD_1V8
ANT2
K6
VIO_IN
SDIO_D3_1V8
L4
NL
IND1005
B16
B15
NL
NL
NL
NL
B14
B13
B12
B11
NL
B10
NL
B9
NL
GP1O12
NL
B8
B7
B6
GPIO10
GPIO9
B5
B4
NL
GPIO11
B3
B2
NL
B1
VIO_IN
GND
A20
A19
GND
A18
NL
NL
NL
GND
A17
A16
A15
A14
NL
BT_HCI_RX
A13
A12
BT_HCI_RTS
BT_HCI_TX
A11
A10
GND
BT_HCI_CTS
A9
A8
WL_SDIO_D1
WL_SDIO_CLK
A7
WL_SDIO_D3
WL_SDIO_D0
A6
A5
A1
WL_SDIO_D2
GND
WL_SDIO_CMD
GND
GND
GND
GND
A4
E4
GND
A3
E3
GND
A2
E2
ANT1
J2
U.FL-R-SMT-1(10)
U.FL
For BT (WG7833/31)
E1
L2
NL
IND1005
GND
GND
D14
GND
GND
CLK_REQ_OUT
D12
D11 WL_RS232_RX
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D13
NL
GND
GND
RF_ANT_A
GND
NL
L1
NL
IND1005
WL/BT_2.4G ANT
RF_ANT_BG
NL
C6
10pF
CAP1005
C3
10pF
CAP1005
Reserved for RF test.
Closed to Module.
GPIO_2/WL_RS232_RX
GPIO_4
PA_DC2DC_OUT
GND
NL
GND
NL
NL
NL
GND
VBAT_IN
C16
C14
C13
C12
C15
GND
GND
GND
GND
GND
C11
C9
C10
WLAN_IRQ
C8
TCXO_CLK_IN
WLAN_EN
C7
C6
C5
GND
NL
GPIO1/WL_232_TX
C3
C2
C4
NL
BT_UART_DEBUG
GPIO3_WL_UART_DBG
J2
NL
GND
NL
C1
For Logger
J1
C5
NL_10pF
CAP1005
TP4
TCXO_CLK_IN
TP1
TP2
TP3
NL
C4
1uF
CAP1005
WL_RS232_TX
BT_EN
TP9
C2
0.1uF
CAP1005
CLK_REQ_OUT_1833
ANTENNA CIRCUITS
WL_5G ANT (For WG7833/03 Only)
C17
0.1uF
CAP1005
U2
TPS73618DBV
SOT-23-5
IN
EN
GND
OUT
NR/FB
VDD_TCXO_OUT
C18
0.1uF
CAP1005
C22
10nF
CAP1005
C19
10uF
CAP2012
C20
0.1uF
CAP1005
0R RES1005
For RTTT test
BD_HCI_CTS_1V8
R19
0R RES1005
BD_HCI_RTS_1V8
R20
0R RES1005
BD_HCI_TX_1V8
R21
0R RES1005
BD_HCI_RX_1V8
R22
0R RES1005
For BT (WG7833/31)
WiFi SDIO Matching Circuit
In green circle is a necessary part
**
It's recommended to reserve SDID matching circuits
and keep them close to module for signal optimization
**
The six traces from Module to Host must be
treated like a bus. The bus length shall be as short
as possible and every trace length must be the same as
the others. Enough space above 2 time trace width or
ground shielding between trace and trace will be benefit
to make sure signal quality, especially for SDIO_CLK
trace. Besides, please remember to keep them away from
the other digital or analog signal traces. To add ground
shielding to around the buses will be helpful.
Boot Conditions
VBAT_IN: 2.9~4.8V => 3.7V TYP
** SDIO lines should be held high by the host
** All test point must reserved for test
SDIO_D0_1V8
C7
NL
CAP1005
SDIO_D1_1V8
C8
NL
CAP1005
VIO_IN: 1.62~1.95V => 1.8V TYP
Slow Clock: 32.768KHz for module boot
and deep sleep
SDIO_D2_1V8
C9
NL
CAP1005
SDIO_D3_1V8
C13
NL
CAP1005
Scheme Brief
WiFi Interface: SDIO
SDIO_CMD_1V8
C14
NL
CAP1005
SDIO_CLK_1V8
C15
NL
CAP1005
Fast Clock:
External TCXO 26MHz
Slow Clock: 32.768KHz
Figure 7-1 Module Reference Schematic
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8. DESIGN RECOMMENDATIONS
8.1. Design Note on Debug Port

 Pin# C6, C4 serve as WLAN and BT debug port, respectively. So test points for these two
signals should be reserved for debugging purpose.

 Pin# C11 (WLAN_IRQ) needs to be pulled high via 10Kohm and use Pin# D11, C7
(WL_RS232_RX, WL_RS232_TX) as hardware interface to communicate with system platform
and TI RTTT test utility for WLAN RF performance test, debug and manufacturing application.
8.2. Module Layout Recommendations
Follow these module layout recommendations:

 Digital Signals Layout
 SDIO signals traces (CMD, D0, D1, D2 and D3) should be routed in parallel to each other and
as short as possible. (Less than 12cm) Besides, every trace length must be the same as the
others.
 Enough space above 1.5 time trace width or ground shielding between trace and trace will
be benefit to make sure signal quality, especially for SDIO_CLK trace. Remember to keep
them away from the other digital or analog signal traces. Adding ground shielding around
these bus is recommended.
 Route trace of SDIO_CLK at Top layer without vias.
 SDIO Clock, Audio Clock (PCM_AUD_CLK), these digital clock signals are a source of noise.
Keep the traces of these signals as short as possible. Whenever possible, maintain a
clearance around them.
 BT_AUD signals should be rounted in the same group and it’s better to rout them at the
same layer or confirm them referring to the same reference plane.

 RF Trace & Antenna
 Keep 50ohm trace impedance.
 Move all the high-speed traces and components far away from the antenna.
 Check antenna vendor for the layout guideline and clearance.

 Power Trace
 Power trace for VBAT should be 20mil wide. 1.8V trace should be 15mil wide, at least.
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Doc No: WG7833-B0-DTS-R03
 Isolate different power traces with Ground plane

 Ground
 Having a complete Ground and more GND vias under module in layer1 for system stable
and thermal dissipation.
 Have a complete Ground pour in layer 2 for thermal dissipation.
 Increase the GND pour in the 1st layer, move all the traces from the 1st layer to the inner
layers if possible.
 Move GND vias close to the pad.

 Clocks
 To avoid adding noise to the clock signal, keep the primary clock away from fast digital
switching lines and power traces.
 It is preferable to keep all clocks between the ground/power layers.
 Primary TCXO placement
- To reduce clock drift, place the TCXO far from a heat source on the board.
- For better thermal mass, ensure good grounding for the TCXO.
- If the TCXO cannot be placed far from a heat source, add a scratch in the ground layers to
isolate the heat spreading toward the TCXO
Primary TCXO placement:
 To reduce clock drift, place the TCXO far from a heat source on the board.
 For better thermal mass, ensure good grounding for the TCXO.
 If the TCXO cannot be placed far from a heat source, add a scratch in the ground layers
to isolate the heat spreading toward the TCXO
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9. PACKAGE INFORMATION
9.1. Module Mechanical Outline
12.8±0.1 mm
1.63±0.1 mm
12.0±0.1 mm
Figure 9-1. Module mechanical outline
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Figure 9-2. Module pad dimensions
*We recommend adopting the same dimensions listed above for building PCB footprint.
** Pad tolerance as +/- 30um
9.2. Ordering Information
Part number:
WG7833-B0
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9.3. Package Marking
PIN-1 Marking
Figure 9-3. Package Marking
Date Code: YYWWSSFAX
YY = Digit of the year, ex: 2011=11
WW = Week (01~52)
SS = Serial number from 01 ~99 match to manufacture’s lot number
= Reserve for internal use
A = Module version from A to Z
X = Chip version
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9.4. Packaging
9.4.1. Tape Specification


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Doc No: WG7833-B0-DTS-R03

Product label
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10. SMT AND BAKING RECOMMENDATION
10.1.
Baking Recommendation

 Baking condition：
Follow MSL Level 4 to do baking process.
After bag is opened, devices that will be subjected to reflow solder or other high
temperature process must be
a) Mounted within 72 hours of factory conditions <30°C/60% RH, or
b) Stored at <10% RH.
Devices require bake, before mounting, if Humidity Indicator Card reads >10%
If baking is required, Devices may be baked for 8 hrs. at 125 °C.
10.2.
SMT Recommendation
Recommended Reflow profile：
No.
Item
Temperature (°C)
Time (sec)
Pre-heat
D1: 140 ~ D2: 200
T1: 80 ~ 120
Soldering
D2: = 220
T2: 60 +/- 10
Peak-Temp.
D3: 250 °C max
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Note: (1) Reflow soldering is recommended two times maximum.
(2) Add Nitrogen while Reflow process： SMT solder ability will be better.
 Stencil thickness：
： 0.1~ 0.13 mm (Recommended)
 Soldering paste (without Pb)：
： Recommended SENJU N705-GRN3360-K2-V can get better
soldering effects.
11. HISTORY CHANGE
Revision
Date
Description
R 0.1
2014/08/28
New Released
R 0.2
2014/09/29
Modify the module thickness from 1.7±0.05 mm to 1.63±0.1 mm
Modify the package marking.
R 0.3
2015/07/30
Add FCC/NCC WARING STATEMENT
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FCC WARING STATEMENT
This equipment has been tested and found to comply with the limits for a Class B digital device,
pursuant to part 15 of the FCC rules. These limits are designed to provide reasonable protection
against harmful interference in a residential installation. This equipment generates, uses and can
radiate radio frequency energy and, if not installed and used in accordance with the instructions,
may cause harmful interference to radio communications. However, there is no guarantee that
interference will not occur in a particular installation. If this equipment does cause harmful
interference to radio or television reception, which can be determined by turning the equipment off
and on, the user is encouraged to try to correct the interference by one or more of the following
measures:
-Reorient or relocate the receiving antenna.
-Increase the separation between the equipment and receiver.
-Connect the equipment into an outlet on a circuit different from that to which the receiver is
connected.
-Consult the dealer or an experienced radio/TV technician for help.
You are cautioned that changes or modifications not expressly approved by the party responsible for
compliance could void your authority to operate the equipment.
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two
conditions: (1) this device may not cause harmful interference and (2) this device must accept any
interference received, including interference that may cause undesired operation.
FCC RF Radiation Exposure Statement:
1. This Transmitter must not be co-located or operating in conjunction with any other antenna or
transmitter.
2. This equipment complies with FCC RF radiation exposure limits set forth for an uncontrolled
environment. This equipment should be installed and operated with a minimum distance of 20
centimeters between the radiator and your body.
According to FCC 15.407(e), the device is intended to operate in the frequency band of 5.15GHz to
5.25GHz under all conditions of normal operation. Normal operation of this device is restricted to
indoor used only to reduce any potential for harmful interference to co-channel MSS operations.
Information to OEM integrator
The OEM integrator has to be aware not to provide information to the end user regarding how to
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install or remove this RF module in the user manual of the end product. The user manual which is
provided by OEM integrators for end users must include the following information in a prominent
location.
1. To comply with FCC RF exposure compliance requirements, the antenna used for this transmitter
must be installed to provide a separation distance of at least 20 cm from all persons and must not
be co- located or operating in conjunction with any other antenna or transmitter, except in
accordance with FCC multi-transmitter product transmitter product procedures.
2. Only those antennas with same type and lesser gain filed under this FCC ID number can be used
with this device.
3. The regulatory label on the final system must include the statement: “Contains FCC ID:
WS2-WG7833B0 “.
4. The final system integrator must ensure there is no instruction provided in the user manual or
customer documentation indicating how to install or remove the transmitter module except such
device has implemented two-ways authentication between module and the host system.
5. If the end product integrating this module is going to be operated in 5.15 ~5.25GHz frequency
range, the warning statement in the user manual of the end product should include the restriction
of operating this device in indoor could void the user’s authority to operate the equipment.
Copyright © JORJIN TECHNOLOGIES INC. 2015
http://WWW.JORJIN.COM.TW
CONFIDENTIAL
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Doc No: WG7833-B0-DTS-R03
NCC WARING STATEMENT
Article 12
Without permission, any company, firm or user
shall not alter the frequency, increase the
power, or change the characteristics and
functions of the original design of the
certified lower power frequency electric
machinery.
Article 14
The application of low power frequency electric
machineries shall not affect the navigation
safety nor interfere a legal communication, if
an interference is found, the service will be
suspended until improvement is made and the
interference no longer exists.
Copyright © JORJIN TECHNOLOGIES INC. 2015
http://WWW.JORJIN.COM.TW
CONFIDENTIAL
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