Amimon AMN11100R44 AMN11100 Transmitter - WHDI Wireless Modules User Manual AMN11100 WHDI Transmitter Module Datasheet
Amimon Ltd. AMN11100 Transmitter - WHDI Wireless Modules AMN11100 WHDI Transmitter Module Datasheet
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| Document ID | 874468 |
| Application ID | cFvWD0on1MCqq5w8RC1/SQ== |
| Document Description | User Manual |
| Short Term Confidential | No |
| Permanent Confidential | No |
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| Document Type | User Manual |
| Display Format | Adobe Acrobat PDF - pdf |
| Filesize | 84.39kB (1054918 bits) |
| Date Submitted | 2007-11-30 00:00:00 |
| Date Available | 2007-11-30 00:00:00 |
| Creation Date | 2007-11-11 13:24:48 |
| Producing Software | Acrobat Distiller 7.0.5 (Windows) |
| Document Lastmod | 2007-11-11 13:33:31 |
| Document Title | AMN11100 WHDI Transmitter Module Datasheet |
| Document Creator | Acrobat PDFMaker 7.0.5 for Word |
| Document Author: | Amimon |
AMN11100 WHDITM Transmitter Module Datasheet Version 1.0 Version 1.0 AMIMON Confidential Version 1.0 AMIMON Confidential ii Important Notice Important Notice AMIMON Ltd. reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to AMIMON's terms and conditions of sale supplied at the time of order acknowledgment. AMIMON warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with AMIMON's standard warranty. Testing and other quality control techniques are used to the extent AMIMON deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. AMIMON assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using AMIMON components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. AMIMON does not warrant or represent that any license, either express or implied, is granted under any AMIMON patent right, copyright, mask work right, or other AMIMON intellectual property right relating to any combination, machine, or process in which AMIMON products or services are used. Information published by AMIMON regarding third-party products or services does not constitute a license from AMIMON to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from AMIMON under the patents or other intellectual property of AMIMON. Reproduction of information in AMIMON data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. AMIMON is not responsible or liable for such altered documentation. Resale of AMIMON products or services with statements different from or beyond the parameters stated by AMIMON for that product or service voids all express and any implied warranties for the associated AMIMON product or service and is an unfair and deceptive business practice. AMIMON is not responsible or liable for any such statements. All company and brand products and service names are trademarks or registered trademarks of their respective holders. Contact Us US Office Israeli Headquarters 2350 Mission College Blvd. Suite 500 Santa Clara, CA 95054 Tel: +1 650 641 7178 2 Maskit St. Building D, 2nd Floor P.O Box 12618 Herzlia 46733, Israel Tel: +972-9-962-9222 Fax: +972-9-956-5467 contact@AMIMON.com Version 1.0 AMIMON Confidential iii Table of Contents Table of Contents Chapter 1, Introduction .................................................................................. 1 1.1 Features......................................................................................................................................................... 1 Chapter 2, Overview........................................................................................ 3 2.1 2.2 2.3 2.4 2.5 2.6 2.7 AMN2110 WHDI Baseband Transmitter...................................................................................................... 4 LPC2103 Mini-MAC µController .................................................................................................................. 4 MAX2828 5GHz (802.11a) Transceiver........................................................................................................ 5 Power Amplifier (PA).................................................................................................................................... 5 Board Connector (WHDITM Connector)....................................................................................................... 5 E2PROM......................................................................................................................................................... 5 40MHz Clock Gen.......................................................................................................................................... 5 Chapter 3, Interfaces ...................................................................................... 7 3.1 3.1.1 3.1.2 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.4 Video Data Input and Conversions ............................................................................................................. 7 Video Channel Mapping ............................................................................................................................... 8 Video Interface Input Timing Diagram.......................................................................................................... 8 Audio Data Capture ...................................................................................................................................... 9 I2S Bus Specification .................................................................................................................................. 10 S/PDIF Bus................................................................................................................................................. 11 Management Buses and Connectors ....................................................................................................... 12 Two-Wire Serial Bus Interface.................................................................................................................... 12 Interrupts .................................................................................................................................................... 13 Reset and Wake-up Timer.......................................................................................................................... 14 Chapter 4, WHDI Connector Pin-Outs............................................................ 15 4.1 4.2 4.3 Signals ......................................................................................................................................................... 15 Connector Schematics............................................................................................................................... 16 Pin List......................................................................................................................................................... 17 Chapter 5, Electrical Specifications ............................................................. 19 5.1 Operating Conditions and Electrical Characteristics ............................................................................. 19 Version 1.0 AMIMON Confidential iv Table of Contents Chapter 6, Design Guidelines ........................................................................ 21 6.1 Digital Layout Recommendation............................................................................................................... 21 6.1.1 Stuck up...................................................................................................................................................... 21 6.1.2 General Guidelines..................................................................................................................................... 22 6.1.3 WHDI Lines ................................................................................................................................................ 22 6.1.4 Power and Ground ..................................................................................................................................... 22 6.2 RF Design Recommendation..................................................................................................................... 24 6.2.1 RF Components ......................................................................................................................................... 24 6.2.2 Power Management ................................................................................................................................... 24 6.2.3 Device Application Notes ........................................................................................................................... 24 6.2.4 Antennas .................................................................................................................................................... 24 Chapter 7, Mechanical Dimensions............................................................... 25 Version 1.0 AMIMON Confidential List of Figures List of Figures Figure 1: AMN11100 Block Diagram .....................................................................................................................................3 Figure 2: WHDI Baseband Transmitter Chipset ..................................................................................................................4 Figure 3: Video Data Processing Path ..................................................................................................................................7 Figure 4: Timing Diagram........................................................................................................................................................9 Figure 5: I2S Simple System Configurations and Basic Interface Timing ......................................................................10 Figure 6: I2S Input Timings....................................................................................................................................................11 Figure 7: Two-Wire Application / MiniMAC Connection....................................................................................................12 Figure 8: Two-Wire MiniMAC Write Commands................................................................................................................12 Figure 9: Two-Wire Read Command...................................................................................................................................13 Figure 10: Reset Mechanism................................................................................................................................................14 Figure 11: WHDI Connector..................................................................................................................................................16 Figure 12: Transmitter RF Power Scheme .........................................................................................................................24 Figure 13: Mechanical Dimensions......................................................................................................................................25 List of Tables Table 1: Common Supported Video Input Resolutions.......................................................................................................8 Table 2: Video Channel Mapping...........................................................................................................................................8 Table 3: : Video Interface ........................................................................................................................................................8 Table 4: I2S Audio Interface Timing Requirements...........................................................................................................10 Table 5: Audio Interface Timing Requirements..................................................................................................................11 Table 6: Device Addresses ...................................................................................................................................................12 Table 7: WHDI Connector Signals .......................................................................................................................................15 Table 8: Tx WHDI Connector Pin List .................................................................................................................................17 Table 9: Absolute Maximum Ratings over Operating Case Temperature Range ........................................................19 Table 10: Recommended Operating Conditions................................................................................................................19 Table 11: Electrical Characteristics over Recommended Range of Supply Voltage and Operating Conditions.........................................................................................................................................................19 Table 12: Digital Layout Recommendation.........................................................................................................................21 Version 1.0 AMIMON Confidential vi Revision History Revision History Version Date 0.1 0.5 19-Jun-07 Description Initial Release Added Design Guidelines Updated Reset Mechanism Updated Two-Wire Serial Bus Protocol Definition 0.6 19-June-07 1.0 06-Nov-07 Added Mechanical Dimensions Added FCC certification and compliance Added Table 2 Updated Table 4 Version 1.0 AMIMON Confidential vii Revision History Version 1.0 AMIMON Confidential viii Introduction Chapter 1 Introduction The AMN11100 is the first generation of WHDITM transmitter board based on AMIMON's AMN2110 baseband transmitter chip. The AMN11100 WHDITM wireless transmitter module, together with the AMN12100 wireless receiver module, presents the ultimate solution for converting any High Definition (HD) system into a wireless one. This add-on module enables wireless A/V applications that easily fit into the living room and eliminate traditional A/V wiring. The ultimate HD video and audio quality and robustness are unmatched by any other wireless technology, and present a true alternative to cable. The WHDI system transmits uncompressed video and audio streams wirelessly and thus simplifies and eliminates system issues experienced with any other known wireless-based solutions, such as lip-sync, large buffers and other burdens like retransmissions or error propagation. 1.1 Features • Uncompressed and uncompromised HD video quality, using AMIMON's baseband chipsets: AMN2110: WHDITM Baseband Transmitter • WHDI – Wireless High Definition Interface: Digital video: 30-bit RGB or YCrCb Digital audio: I2S and SPDIF Two-Wire serial bus slave interface Two interrupt lines • Supports any uncompressed video resolutions, including: HD: 720p, 1080i, 1080p, 576i, 576p, 480p, 480i PC: VGA (640x480), SVGA (800x600), XGA (1024x768) Panel: 854x800, 1280x768, 1366x768 • Audio: Up to 3Mbps audio stream: I2S: Two PCM channels (sampled up to 48 KHz x 24 bit) SPDIF: Including AC-3, DTS • Strong 256-bit AES encryption • User-defined two-way channel with minimum 10 Kbps for data and control • Less than 1mSec latency between source and sink • Small mechanical footprint: With PCB integrated antennas. Optional external antennas Version 1.0 AMIMON Confidential Introduction • RF characteristics: MIMO technology, using 5GHz unlicensed band, 18MHz bandwidth. Coexists with 802.11a/n and 5.8GHz cordless devices. Support for Automatic Transmission Power Control (ATPC). No line of sight needed between transmitter and receiver. It has a range of over 30 meters, suitable for almost any room. 14mW typical transmission power. Maximum 45mW transmission power. • Power requirements: 3.3V (±5%), ~5.6W • Certification & Compliance: This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Any changes or modifications not expressly approved by Amimon for compliance could void the user's authority to operate the equipment. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. • Caution: The module should be positioned so that personnel in the area for prolonged periods may safely remain at least 20 cm (8 in) in an uncontrolled environment from the module. Observe FCC OET Bulletin 56 “Hazards of radio frequency and electromagnetic field” and Bulletin 65 “Human exposure to radio frequency electromagnetic fields.” Version 1.0 AMIMON Confidential Overview Chapter 2 Overview The AMN11100 WHDI Video Source Unit (VSU) is designed to modulate and transmit downstream video and audio content over the wireless medium and receive a control channel over the wireless upstream. The modulation uses 18MHz bandwidth and is carried over the 5GHz unlicensed band. Figure 1 displays a block diagram of the AMN11100. The inputs to the VSU are digital uncompressed video, digital audio and control, all via the WHDI connector. It has a MIMO design of four wireless output channels and a slow rate data input wireless channel. The MiniMAC uC is responsible for the control and the management. Analog MUX (RSSI/ PADET) 80 Pi n WHDITH Connector VIDEO Audio AMN2110 MAX2828 5Ghz Tx PA MAX2828 5Ghz Tx PA MAX2828 5Ghz Tx PA WHDITM Baseband Transmitter GPIO RESET Interrupt Clock SPI 20MHz Int uC Reset MAX2828 5Ghz Tx& Uplink PA uC Control Two-Wire MiniMAC E2PROM Clock 40M 40M CLOCK GEN. Figure 1: AMN11100 Block Diagram Version 1.0 AMIMON Confidential Overview The main building blocks of the AMN11100 are as follows: • AMN2110 WHDI Baseband Transmitter, as briefly described on page 4 • LPC2103 Mini-MAC µController, as briefly described on page 4 • MAX2828 5GHz (802.11a) Transceiver, as briefly described on page 5 • Power Amplifier (PA), as briefly described on page 5 • Board Connector (WHDI Connector), as described on page 5 • E2PROM, as described on page 5 • 40MHz Clock Gen, as described on page 5 2.1 AMN2110 WHDI Baseband Transmitter The AMN2110 WHDITM baseband transmitter chip is the heart of the AMN11100 WHDI transmitter module. The AMN2110 interfaces the A/V source through the WHDI connector, and is controlled on board by the MiniMAC uC. Figure 2: WHDI Baseband Transmitter Chipset The AMN2110 is based on MIMO technology transmitting through up to four output channels. Four digital-to-analog converters and one analog-to-digital converter are embedded within the chip. The AMN2110 internal PLL accepts an input clock frequency of 40MHz. The input frequency is multiplied and then used as an internal system clock. 2.2 LPC2103 Mini-MAC µController The LPC2103 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU, with embedded 32kB high-speed memory. It is used as an external microcontroller for implementing the MAC layer of the WHDI link. The LPC2103 internal PLL accepts an input clock frequency of 20MHz and generates an internal 60MHz system clock. Version 1.0 AMIMON Confidential Overview 2.3 MAX2828 5GHz (802.11a) Transceiver The VSU has four MAX2828 chips embedded in it. The MAX2828 is a single-chip, RF transceiver IC designed specifically for single-band 4.9GHz to 5.875GHz, OFDM, 802.11 WLAN applications. It includes all the circuitry necessary to implement the RF transceiver function, providing a fully integrated receive path, transmit path, VCO, frequency synthesizer and baseband/control interface. Only the PA, RF switches, RF bandpass filters (BPF), RF BALUNs and a small number of passive components are required to form the complete RF front-end solution. AMIMON's WHDITM technology uses the low cost and high availability of the 802.11a/n RF to allow low-cost RF for the video modem. Future generations of the WHDI modem will use an AMIMON-designed, cost-efficient, single-chip, integrated RFIC for multiple transmits on the transmitter side and a single-chip, integrated RFIC for multiple receivers on the receiver side. 2.4 Power Amplifier (PA) In order to extend the operating range for the AMN11100, the RF transmitter uses power amplifiers. Each power amplifier has an output power detector for TPC purposes. Amimon has implemented Anadigics AWL6951 PA on the AMN11100. 2.5 Board Connector (WHDITM Connector) For information regarding the connector specification and pin-outs, see section 4.1, AMN11100 Board Connector (WHDI Connector), page 15. 2.6 E2PROM The E2PROM is currently a system option, enabling mating and authentication in a multipoint design environment. 2.7 40MHz Clock Gen An on-board 40MHz TCXO is connected to the MAX2828 chipsets and the AMN2110 baseband. The clock is then divided by two by the AMN2110 and supplied to the LPC2103 uC. Version 1.0 AMIMON Confidential Overview Version 1.0 AMIMON Confidential Interfaces Chapter 3 Interfaces 3.1 Video Data Input and Conversions Figure 3: Video Data Processing Path Figure 3 shows the stages for processing video data through the AMN2110. The HSYNC and the VSYNC input signals are mandatory. The DE input signal is optional and can be created with the DE generator using the HSYNC and the VSYNC pulses. The video input data is uncompressed digital video up to 3*10 bits in width. Important: When connected to a 3*8 bits source, connect the appropriate LSBs to GND. The video interface provides a direct connection to the outputs from an HDMI receiver or from an MPEG decoder. The appropriate registers must be configured to describe which format of video to input into the AMN11100. Refer to the appropriate programmer's reference guide for more details. DATA Enable (DE) Generator The AMN2110 includes logic to construct the DE signal from the incoming HSYNC, VSYNC and clock. Registers are programmed to enable the DE signal to define the size of the active display region. Color Space Converter The AMN11100 can receive either RGB or YCbCr color space. For more details, you may refer to the MAC registers in the programmer's reference guide. Version 1.0 AMIMON Confidential Interfaces Common Video Input Format Table 1 describes the common supported video input resolutions. Table 1: Common Supported Video Input Resolutions Input Pixel Clock (MHz) Color Space Video Format Bus Width 480i 480p XGA 720p 1080i RGB/YCbCr 4:4:4 24 27 27 65 74.25 74.25 3.1.1 Video Channel Mapping The 30 bit video input signals are mapped to the RGB and YCbCr color space according to the options described in the following table: Table 2: Video Channel Mapping Option D[29:20] D[19:10] D[9:0] #1 #2 #3 #4 #5 #6 RED (Cr) RED (Cr) GREEN (Y) GREEN (Y) BLUE (Cb) BLUE (Cb) GREEN (Y) BLUE (Cb) RED (Cr) BLUE (Cb) RED (Cr) GREEN (Y) BLUE (Cb) GREEN (Y) BLUE (Cb) RED (Cr) GREEN (Y) RED (Cr) The AMN11100 allows any of the input video channels options. The first option is the default from power-up. In order to change the video channel mapping, please refer to the appropriate programmer's reference guide. 3.1.2 Video Interface Input Timing Diagram 3.1.2.1 Timing Requirements Important: The following parameters relate to the AMN2110 baseband chipset and not to the entire AMN11100 board. Table 3: : Video Interface Symbol Parameter MIN TYP MAX Units TDCKCYC DCLK period 12.8 40 ns TDCKFREQ DCLK frequency 25 78.125 MHz TDCKDUTY DCLK duty cycle 40% 60% ns TDCKSUR Setup time to DCLK rising edge 0.7 TDCKHDR Hold time to DCLK rising edge 1.1 ns ns TDCKSUF Setup time to DCLK falling edge 1.5 ns TDCKHDF Hold time to DCLK falling edge 0.5 ns Version 1.0 AMIMON Confidential Interfaces 3.1.2.2 Timing Diagram Figure 4: Timing Diagram 3.2 Audio Data Capture AMN11100 transports an explicit audio master clock with appropriate data-over-the-wireless link. No constraints exist for a coherent video and audio clock, where coherent means that the audio and the video clock must have been created from the same clock source. The AMN11100 can accept digital audio from either SPDIF or I2S inputs. The AMN11100 supports two channel audio sampling frequencies of up to 48KHz and of up to 32 bits per sample. Version 1.0 AMIMON Confidential Interfaces 3.2.1 I2S Bus Specification The AMN11100 supports a standardized communication structure inter-IC sound (I2S) bus. As shown in Figure 5, the bus has three lines: continuous serial clock (SCK), word select (WS) and serial data (SD). The external device generating SCK and WS is the audio source. Figure 5: I2S Simple System Configurations and Basic Interface Timing The AMN11100 supports an I2S format of up to 32 bits for each channel (left and right). The serial data is latched into the AMN11100 on the leading (LOW to HIGH) edge of the clock signal. The WS is also latched on the leading edge of the clock signal. The WS line should change one clock period before the first bit of the channel is transmitted. The AMN1110 transmits explicit clock SD and WS and does not process the audio content. The input audio at the transmitter end is mirrored to the receiver end. The source may have different word lengths, up to 32 bits. However, the AMN11100 always samples and transmits 24 bits over the wireless link. 3.2.1.1 Timing Requirements Table 4: I2S Audio Interface Timing Requirements Symbol Parameter MIN TYP MAX Units TSCKCYC SCK period 325 976 ns TSCKFREQ SCK frequency 1.024 3.072 MHz TSCKDUTY SCK duty cycle 40 60 TDCKSETUP Setup time to SCK rising edge 25 ns TDCKHOLD Hold time to SCK rising edge 25 ns Version 1.0 AMIMON Confidential 10 Interfaces 3.2.1.2 Timing Diagram TSCKCYC T SCKDUTY SCK 50% TDCKSETUP TDCKHOLD SD ,WS Figure 6: I2S Input Timings 3.2.2 S/PDIF Bus 3.2.2.1 Timing Requirements The AMN11100 does not require the SPDIF clock. The clock is produced internally by sampling the SPDIF data input at a high clock rate and processing it. Table 5: Audio Interface Timing Requirements Symbol Parameter MAX Units TSPCYC SPDIF data sampling rate Condition MIN 162 TYP 488 ns TSPFREQ SPDIF data sampling freq 2.048 6.144 MHz Version 1.0 AMIMON Confidential 11 Interfaces 3.3 Management Buses and Connectors 3.3.1 Two-Wire Serial Bus Interface The WHDI application observes and controls the AMN11100 via a Two-Wire interface and an interrupt line connecting the application microcontroller and the AMN11100 MiniMAC microcontroller. The protocol of the TwoWire bus for the WHDI application / MiniMAC interface is described in the following sections. The Two-Wire bus is bidirectional and, as its name implies, has only two wires: a Serial Clock Line (SCL) and a Serial Data Line (SDA). The Two-Wire architecture includes master and slave devices. The master initiates a data transfer on the bus and generates the clock signal. The AMN11100 MiniMAC operates as a slave device. Each slave device is recognized by a unique address and can operate as either a receive-only device or a transmitter with the ability to both receive and send information. SDA Application MicroController WHDI MiniMAC (Two-Wire Slave) (Two-Wire Master) SCL Figure 7: Two-Wire Application / MiniMAC Connection On top of the Two-Wire low level operation described in sections 3.3.1.2 and 3.3.1.3, the WHDI application and the MiniMAC microcontrollers communicate with each other in a defined protocol, which avoids all possibilities of confusion. The protocol defines command oriented transactions between the application and the WHDI MiniMAC. Each Two-Wire command has a predefined data byte length and is defined to be exactly one Two-Wire transaction long. 3.3.1.1 Device Addresses The MiniMAC device address may be altered by two jumpers on VDU/VSU board. Table 6: Device Addresses Device Address MiniMAC uC 0x62 or 0x82 or 0x90 or 0x70 (Board configuration dependant) Alternatively, the device address can be set in the MAC SW in advance. 3.3.1.2 MiniMAC uC Write Operation Figure 8 demonstrates a write transaction which sends 2 data bytes and which ends with the master stop bit. Each write transaction sends 1 or more data bytes to the MiniMAC, beginning at an explicit 2 bytes long address. Multiple data bytes may be written as the MiniMAC stores the received register data until the master sends a stop bit. The MiniMAC updates the register value upon a successful termination of a write transaction. Two-Wire Slave address START I6 I5 ... write ack register address A15 A14 ... A8 ack register address A7 A6 ... ack A0 register data0 D7 D6 ... ack D0 register data1 D7 D6 ... ack D0 STOP Figure 8: Two-Wire MiniMAC Write Commands Version 1.0 AMIMON Confidential 12 Interfaces 3.3.1.3 MiniMAC uC Read Operation This operation reads from a specific 2-byte address. The read transaction is divided into two parts. In the first part, the Two-Wire master sends a write command to the slave containing only the required start address. (The address is always 2 bytes long.) In the second part, multiple bytes may be read from consecutive addresses. The MiniMAC puts the appropriate data on the Two-Wire bus and the internal address is automatically incremented. A stop bit is sent by the master only when the entire transaction has been completed. Two-Wire Slave address START I6 I5 ... ack write register address A15 A14 ... ack A8 register address A7 A6 ... ack A0 Two-Wire slave address START I6 I5 ... ack read register data Data Byte 0 ack register data Data Byte 1 ack STOP Figure 9: Two-Wire Read Command 3.3.1.4 WHDI Application / MiniMAC Protocol The WHDI programmer’s reference defines the MiniMAC registers data structure. Each register has an associated group ID and index offset address. The group ID and the index offset are each 1 byte long. Together they define a register address that is 2 bytes long. Each register has an attributed length (in byte units). All registers within the same group have the same length. A Two-Wire transaction to a specific register includes 2 bytes of register address and the register data bytes. The register is written in one transaction. If the transaction terminates ahead of time or is too long, the MiniMAC issues an error interrupt and does not store the received values. The register is read in one transaction, as described in section 3.3.1.3. If the read transaction finishes ahead of time, the MiniMAC issues an error interrupt. 3.3.2 Interrupts There is one interrupt connected to the WHDI connector. The interrupt source is the AMN2110 MiniMAC uC. For details about the interrupt, please refer to the Programmer's User Guide. Version 1.0 AMIMON Confidential 13 Interfaces 3.4 Reset and Wake-up Timer The AMN11100 has one hard RESET input pin connected directly to the AMN2110 and through a MicroPower circuit to the LPC2103 uC, as described in Figure 10. Upon power up, the MicroPower circuit asserts the uC reset pin for about 150msec. Assertion of the LPC2103 reset starts its internal wake-up timer, causing the internal chip reset to remain asserted until the external reset is de-asserted, the 20MHz clock runs, a fixed number of clocks have passed and the on-chip flash controller has completed its initialization. When the LPC2103 internal reset is removed, the processor begins executing at address 0, which is the reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined reset values. The processor initializes the AMN2110 baseband chipset. After the reset is de-asserted for TBD msec, it is ready to operate. The wake-up timer monitors the 20MHz clock in order to check whether it is safe to begin code execution. Figure 10: Reset Mechanism Version 1.0 AMIMON Confidential 14 WHDI Connector Pin-Outs Chapter 4 WHDI Connector Pin-Outs 4.1 Signals Table 7: WHDI Connector Signals # of Pins Pin Name Description / Functionality Group Direction Remarks Tx 30 D[29:0] 30-bit RGB (10:10:10) or YCrCb (10:10:10) Video In DCLK Video data clock Video In DE Data enable Video In H_SYNC V_SYNC Horizontal sync Video In Vertical sync Video In SPDIF SPDIF audio interface SD I S audio interface Serial Data signals Audio In Audio In SCLK I S continuous serial clock Audio In WS(LRCLK) I S Word Select (Left/right clock) which defines also the sampling rate Audio In MCLK I S master clock coherent to WS according to specified ratio Audio NA SDA Two-wire Serial Bus Data (Slave Mode) Control I/O Control I/F for WHDI SCL Two-wire Serial Bus Clock (Slave Mode) Control In Control I/F for WHDI Up to 78.125 MHz Up to 3.072Mbps Rate is adjustable on RX side INT Interrupt from WHDI module Control Out RESET Reset / Power-down line Control In TBD6 TBD6 NA NA TBD[5:0] TBD0, TBD1, TBD4, TBD5 are reserved in AMN11100, AMN12100 as an option for external power rail to the on board uC TBD TBD 3.3V VCC Power Power 300 mA maximum rating per pin 3.3V_OR_5V High Power rail pins, In AMN11100, AMN12100 connect these power rail pins to the 3.3V power rail Power Power For board designed as "High-Power" PA connect this rail to 5V, For Rx (AMN12100) connect to 3.3V 15 GND Ground Power Power † Data in this table is preliminary. Version 1.0 AMIMON Confidential 15 WHDI Connector Pin-Outs 4.2 Connector Schematics WHDI Connector 3.3V Note: For AMN11100 and AMN12100 boards connect to 3.3V power rail 3.3V_OR_5V J1 FX10A-80P/8-SV1 FX10A-80P_8-SV1 S1 Note: uP external power option R0603 1 NC R1 WHDI_TBD0 R0603 1 NC R3 WHDI_TBD1 WHDI_RESET_ WHDI_INT WHDI_TBD2 WHDI_D28 WHDI_D26 WHDI_D24 WHDI_D22 WHDI_D20 WHDI_D18 11 13 15 17 19 21 23 25 27 29 S3 31 33 35 37 39 41 43 45 47 49 S5 WHDI_D16 WHDI_D14 WHDI_DCLK WHDI_TBD3 WHDI_D12 WHDI_D10 WHDI_D8 WHDI_D6 WHDI_D4 51 53 55 57 59 61 63 65 67 69 S7 WHDI_D2 WHDI_H_SYNC WHDI_MCLK WHDI_I2S_D1 WHDI_LRCLK 71 73 75 77 79 10 S1 S2 11 13 15 17 19 21 23 25 27 29 12 14 16 18 20 22 24 26 28 30 S3 S4 31 33 35 37 39 41 43 45 47 49 32 34 36 38 40 42 44 46 48 50 S5 S6 51 53 55 57 59 61 63 65 67 69 52 54 56 58 60 62 64 66 68 70 S7 S8 71 73 75 77 79 72 74 76 78 80 10 Note: For AMN11100 and AMN12100 boards connect to 3.3V power rail 3.3V_OR_5V S2 12 14 16 18 20 22 24 26 28 30 Note: uP external power option uP_V WHDI_TBD4 R0603 1 NC R2 WHDI_TBD5 WHDI_SCL WHDI_SDA WHDI_TBD6 WHDI_D29 WHDI_D27 WHDI_D25 WHDI_D23 WHDI_D21 WHDI_D19 R0603 1 NC R4 S4 32 34 36 38 40 42 44 46 48 50 S6 52 54 56 58 60 62 64 66 68 70 WHDI_D17 WHDI_D15 WHDI_D13 WHDI_D11 WHDI_D9 WHDI_D7 WHDI_D5 WHDI_D3 WHDI_D1 WHDI_D0 S8 72 74 76 78 80 WHDI_DE WHDI_V_SY NC WHDI_SPDIF WHDI_I2S_D0 WHDI_SCLK Note: Max. current rating per pin 0.3 Amp Figure 11: WHDI Connector Version 1.0 AMIMON Confidential 16 WHDI Connector Pin-Outs 4.3 Pin List Table 8: Tx WHDI Connector Pin List Pin Number Signal Pin Number Signal Pin Number Signal 3.3V 31 1.8V(*) 61 D12 3.3V 32 1.8V(*) 62 D7 3.3V 33 RESET 63 D10 3.3V 34 SCL 64 D5 3.3V 35 INT 65 D8 3.3V 36 SDA 66 D3 3.3V 37 N.C 67 D6 3.3V 38 N.C 68 D1 3.3V_OR_5V(**) 39 D28 69 D4 10 3.3V_OR_5V(**) 40 D29 70 D0 11 3.3V_OR_5V(**) 41 D26 71 D2 12 3.3V_OR_5V(**) 42 D27 72 DE 13 3.3V_OR_5V(**) 43 D24 73 HSYNC 14 3.3V_OR_5V(**) 44 D25 74 VSYNC 15 GND 45 D22 75 N.C 16 46 D23 76 SPDIF 47 D20 77 N.C 48 D21 78 I2S_D0 49 D18 79 LRCLK 50 D19 80 SCLK 51 D16 52 D17 53 D14 28 GND GND GND GND GND GND GND GND GND GND GND GND GND 29 1.8V(*) 30 1.8V(*) 60 D9 17 18 19 20 21 22 23 24 25 26 27 54 D15 55 GND 56 D13 57 DCLK 58 D11 59 N.C (*) Optional – Contact Amimon Ltd. for more details. (**) These lines should be connected to a 3.3V power supply. An option for a 5V power supply exists for extended range. Extended range requires a different AMN1110 version. Contact Amimon Ltd. for further details. Version 1.0 AMIMON Confidential 17 WHDI Connector Pin-Outs Version 1.0 AMIMON Confidential 18 Electrical Specifications Chapter 5 Electrical Specifications 5.1 Operating Conditions and Electrical Characteristics The following tables describe the operating conditions and electrical characteristics required for working with the AMN11100. Table 9: Absolute Maximum Ratings over Operating Case Temperature Range Supply input-voltage range, VI 0 to 3.6 V Ambient temperature range 0°C to 70°C Storage temperature range, Tstg -40°C to 125°C Table 10: Recommended Operating Conditions Parameter Min. Typ. Max. Unit 3.15 3.3 3.45 DVDD Module supply voltage VSS Supply ground VIH High-level input voltage VIL Low-level input voltage VOH High-level output voltage (DVDD = MIN, IOH = MAX) VOL Low-level output voltage (DVDD = MIN, IOL = MAX) IOH High-level output current -8 mA IOL Low-level output current mA TC Operating case temperature 70 °C 0.7 DVDD 0.3 DVDD 0.22 DVDD 0.8 DVDD Table 11: Electrical Characteristics over Recommended Range of Supply Voltage and Operating Conditions Max. Unit II Input current Parameter VI = VSS to DVDD Test Conditions Min. Typ. ±20 μA IOZ Off-state output current VO = DVDD or 0 V ±20 μA IDVDD Module supply DVDD = Max., Video Clock = 75 MHz, with activity on all I/O terminals and transmitting in maximum power. 1800 mA Ci Input capacitance 10 pF Co Output capacitance 10 pF Version 1.0 AMIMON Confidential 19 Electrical Specifications Version 1.0 AMIMON Confidential 20 Design Guidelines Chapter 6 Design Guidelines 6.1 Digital Layout Recommendation To better understand the layout guidelines, please refer to the AMN11100 schematics which are part of the HDK package. 6.1.1 Stuck up Recommended stuck up for 10 layers design: • Total thickness 1.6mm • Tolerance: 10% Table 12: Digital Layout Recommendation Conductor Width [mil] StuckUp thickness Title Cu Space Cu Space Cu Space Cu Space Cu Space Cu Space Cu Space Cu Space Cu Space Cu Des. Before Scale Oz/mil 0.5 Oz mil 0.5 Oz mil 0.5 Oz mil 0.5 Oz mil 0.5 Oz mil 0.5 Oz mil 0.5 Oz mil 0.5 Oz mil 0.5 Oz mil 0.5 Oz Control Impedance [ohm] Required Stripline Differential Before Before Design Layer Layer line space line space Required Design Required Design CS 5.25 5.25 100 100 15 30 14 31 50 48 11 12 50 50 L3 4.25 6.75 100 100 50 50 L4 L6 4.5 6.5 100 100 5.5 50 50 L7 L8 4.25 6.75 100 100 50 50 L9 11 12 50 50 15 30 14 31 50 48 5.25 5.25 100 100 L2 L5 PS Type No SIG L1 GND L2 SIG L3 GND L4 VCC L5 SIG L6 GND L7 SIG L8 GND L9 SIG L10 Version 1.0 AMIMON Confidential 21 Design Guidelines 6.1.2 General Guidelines • Keep traces as short as possible. • Traces should be routed over full solid reference plans. • Sensitive lines like reset and clocks should be routed with special care. These lines should be routed over full solid power plans (ground or power). Traces should be routed at least 2 times the trace width away from other lines in the same routing layer. Place a series resistor ~30 ohm at the clock source. • Keep digital signals away from the analog side. 6.1.3 WHDI Lines • Place series resistors on all output lines (near the outputs pins). • Series resistors on input lines are unnecessary. (The series resistors should be placed on the interface board.) 6.1.4 Power and Ground • Use a solid ground plan. • Ground plans separation is unnecessary. • Place decoupling capacitors near power pins. (Refer to the schematics and BOM for recommended values.) • Analog power pins should be filtered with ferrite beads. (Refer to the schematics and BOM for recommended values.) Version 1.0 AMIMON Confidential 22 Design Guidelines 6.1.4.1 Power Rails/Pins Summary for AMN2110 Chip: • Analog: 1.2 Volt: Pins names: DA10_0_AVDD1V2 DA10_1_AVDD1V2 DA10_2_AVDD1V2 DA10_3_AVDD1V2 AD8_AVDD1V2 AD10_AVDD1V2_0 AD10_AVDD1V2_1 PLL_AVDD 3.3 Volt: Pins: DA10_0_AVDD3V3_0 DA10_0_AVDD3V3_1 DA10_1_AVDD3V3_0 DA10_1_AVDD3V3_1 DA10_2_AVDD3V3_0 DA10_2_AVDD3V3_1 DA10_3_AVDD3V3_0 DA10_3_AVDD3V3_1 • Digital: 1.2 Volt: Pins names: VDD_0 to VDD_9 (total 10 pins) 3.3 Volt: Pins: VDD_IO_0 to VDD_IO_14 (total 15 pins) Version 1.0 AMIMON Confidential 23 Design Guidelines 6.2 RF Design Recommendation 6.2.1 RF Components All passive components must have compatible performance with components used in the Amimon reference design. 6.2.2 Power Management The power management is divided such that each channel has independent filtered power supply of 2.85Vdc. Figure 1 shows the power scheme of the RF section of the transmitter. LDO 300mA LDO 300mA LDO 300mA LDO 300mA LDO 120mA/Low Noise Vcc 120mA Vcc 120mA Vcc 120mA Vcc 120mA MAX2828 Synth. 70mA MAX2828 Synth. 70mA MAX2828 Synth. 70mA MAX2828 Synth. 70mA 20mA Clock Circuit TCXO+Buffers PADET MUX 3.3V/10mA Power Amplifier/ 200mA Power Amplifier/ 200mA Power Amplifier/ 200mA Power Amplifier/ 200mA Figure 12: Transmitter RF Power Scheme 6.2.3 Device Application Notes For the best performance, follow the application guidelines of the chosen devices. Regarding the MAX2828 transceiver, follow the Application Note AN3630 that can be downloaded from Maxim-ic website. 6.2.4 Antennas The design of the antennas and matching is performed individually for each product. Changing board stack-up or outline of the RF section can impact the system performance and a matching procedure should be performed. Version 1.0 AMIMON Confidential 24 Mechanical Dimensions Chapter 7 Mechanical Dimensions The following shows the mechanical dimensions for the AMN11100: Figure 13: Mechanical Dimensions Version 1.0 AMIMON Confidential 25 Mechanical Dimensions Version 1.0 AMIMON Confidential 26
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