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Intel® 820 Chipset
Design Guide
July 2000

Order Number: 290631-004

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
The Intel® 820 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I 2C bus/protocol and was developed by Intel.
Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and
North American Philips Corporation.
Alert on LAN and Wake on LAN are results of the IBM/Intel Advanced Manageability Alliance and are trademarks of IBM Corporation.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by:
calling 1-800-548-4725 or
by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2000
*Third-party brands and names are the property of their respective owners.

Intel® 820 Chipset Design Guide

Contents
1

Introduction ................................................................................................................1-1
1.1
1.2
1.3

1.4

2

About This Design Guide ..............................................................................1-1
References....................................................................................................1-2
System Overview ..........................................................................................1-2
1.3.1 Chipset Components .......................................................................1-3
1.3.2 Bandwidth Summary........................................................................1-4
1.3.3 System Configuration.......................................................................1-5
Platform Initiatives.........................................................................................1-8
1.4.1 Direct Rambus*................................................................................1-8
1.4.2 Streaming SIMD Extensions ............................................................1-8
1.4.3 AGP 2.0 ...........................................................................................1-8
1.4.4 Hub Interface ...................................................................................1-8
1.4.5 Manageability...................................................................................1-9
1.4.6 AC’97 .............................................................................................1-10
1.4.7 Low Pin Count (LPC) Interface ......................................................1-11

Layout/Routing Guidelines.........................................................................................2-1
2.1
2.2
2.3
2.4
2.5
2.6

2.7

2.8

General Recommendations ..........................................................................2-1
Component Quadrant Layout........................................................................2-1
Intel® 820 Chipset Component Placement ...................................................2-3
Core Chipset Routing Recommendations.....................................................2-4
Source Synchronous Strobing ......................................................................2-5
Direct Rambus* Interface..............................................................................2-7
2.6.1 Stackup ............................................................................................2-8
2.6.2 Direct Rambus* Layout Guidelines ..................................................2-8
2.6.3 Direct Rambus* Reference Voltage ...............................................2-25
2.6.4 High-speed CMOS Routing ...........................................................2-25
2.6.5 Direct Rambus* Clock Routing ......................................................2-28
2.6.6 Direct Rambus* Design Checklist ..................................................2-28
AGP 2.0 ......................................................................................................2-31
2.7.1 AGP Interface Signal Groups.........................................................2-32
2.7.2 1X Timing Domain Routing Guidelines ..........................................2-33
2.7.3 2X/4X Timing Domain Routing Guidelines.....................................2-33
2.7.4 AGP 2.0 Routing Summary............................................................2-35
2.7.5 AGP Clock Routing ........................................................................2-36
2.7.6 General AGP Routing Guidelines ..................................................2-36
2.7.7 VDDQ Generation and TYPEDET# ...............................................2-37
2.7.8 VREF Generation for AGP 2.0 (2X and 4X) ....................................2-39
2.7.9 Compensation................................................................................2-41
2.7.10 AGP Pull-ups .................................................................................2-41
2.7.11 Motherboard / Add-in Card Interoperability....................................2-42
Hub Interface ..............................................................................................2-43
2.8.1 Data Signals...................................................................................2-44
2.8.2 Strobe Signals................................................................................2-44
2.8.3 HREF Generation/Distribution .......................................................2-44
2.8.4 Compensation................................................................................2-45

Intel® 820 Chipset Design Guide

iii

2.9

2.10
2.11
2.12
2.13

2.14

2.15
2.16

2.17
2.18
2.19
2.20

3

Advanced System Bus Design ..................................................................................3-1
3.1
3.2

3.3

3.4

iv

System Bus Design ....................................................................................2-46
2.9.1 100/133 MHz System Bus .............................................................2-46
2.9.2 System Bus Ground Plane Reference ...........................................2-47
S.E.C.C. 2 Grounding Retention Mechanism (GRM) .................................2-47
Processor CMOS Pullup Values.................................................................2-49
Additional Host Bus Guidelines ..................................................................2-52
Ultra ATA/66 ...............................................................................................2-56
2.13.1 Ultra ATA/66 Detection ..................................................................2-56
2.13.2 Ultra ATA/66 Cable Detection........................................................2-57
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements ................................2-60
AC’97 ..........................................................................................................2-61
2.14.1 AC’97 Signal Quality Requirements...............................................2-63
2.14.2 AC’97 Motherboard Implementation ..............................................2-63
USB ............................................................................................................2-65
ISA (82380AB)............................................................................................2-66
2.16.1 ICH GPIO connected to 82380AB .................................................2-66
2.16.2 Sub Class Code.............................................................................2-66
IOAPIC Design Recommendation ..............................................................2-66
SMBus/Alert Bus.........................................................................................2-67
PCI..............................................................................................................2-67
RTC ............................................................................................................2-67
2.20.1 RTC Crystal ...................................................................................2-68
2.20.2 External Capacitors .......................................................................2-68
2.20.3 RTC Layout Considerations...........................................................2-69
2.20.4 RTC External Battery Connection..................................................2-69
2.20.5 RTC External RTCRST Circuit.......................................................2-70
2.20.6 RTC Routing Guidelines ................................................................2-70
2.20.7 VBIAS DC Voltage and Noise Measurements ...............................2-71
Terminology and Definitions .........................................................................3-1
AGTL+ Design Guidelines ............................................................................3-4
3.2.1 Initial Timing Analysis ......................................................................3-5
3.2.2 Determine General Topology, Layout, and Routing Desired ...........3-8
3.2.3 Pre-Layout Simulation .....................................................................3-8
3.2.4 Place and Route Board..................................................................3-10
3.2.5 Post-Layout Simulation..................................................................3-13
3.2.6 Validation .......................................................................................3-14
Theory.........................................................................................................3-15
3.3.1 AGTL+ ...........................................................................................3-15
3.3.2 Timing Requirements.....................................................................3-16
3.3.3 Cross-talk Theory ..........................................................................3-16
More Details and Insight .............................................................................3-19
3.4.1 Textbook Timing Equations ...........................................................3-19
3.4.2 Effective Impedance and Tolerance/Variation ...............................3-20
3.4.3 Power/Reference Planes, PCB Stackup, and High
Frequency Decoupling ...................................................................3-20
3.4.4 Clock Routing ................................................................................3-23

Intel® 820 Chipset Design Guide

3.5

3.6
4

Clocking .....................................................................................................................4-1
4.1
4.2

4.3
4.4
4.5
4.6
4.7
4.8

5

Clock Generation ..........................................................................................4-1
Component Placement and Interconnection Layout Requirements..............4-6
4.2.1 14.318 MHz Crystal to CK133 .........................................................4-6
4.2.2 CK133 to DRCG ..............................................................................4-6
4.2.3 MCH to DRCG .................................................................................4-7
4.2.4 DRCG to RDRAM Channel ..............................................................4-8
4.2.5 Trace Length....................................................................................4-8
DRCG Impedance Matching Circuit............................................................4-10
4.3.1 DRCG Layout Example..................................................................4-11
AGP Clock Routing Guidelines ...................................................................4-11
Series Termination Resistors for CK133 Clock Outputs .............................4-11
Unused Outputs ..........................................................................................4-12
Decoupling Recommendation for CK133 and DRCG .................................4-12
DRCG Frequency Selection and the DRCG+ .............................................4-12
4.8.1 DRCG Frequency Selection Table and Jitter Specification ...........4-12
4.8.2 DRCG+ Frequency Selection Schematic.......................................4-13

System Manufacturing ...............................................................................................5-1
5.1
5.2
5.3

6

Definitions of Flight Time Measurements/Corrections and Signal Quality ..3-24
3.5.1 VREF Guardband............................................................................3-24
3.5.2 Ringback Levels.............................................................................3-24
3.5.3 Overdrive Region ...........................................................................3-24
3.5.4 Flight Time Definition and Measurement .......................................3-25
Conclusion ..................................................................................................3-26

In Circuit LPC Flash BIOS Programming......................................................5-1
LPC Flash BIOS Vpp Design Guidelines ......................................................5-1
Stackup Requirement ...................................................................................5-1
5.3.1 Overview ..........................................................................................5-1
5.3.2 PCB Materials ..................................................................................5-2
5.3.3 Design Process................................................................................5-2
5.3.4 Test Coupon Design Guidelines ......................................................5-3
5.3.5 Recommended Stackup...................................................................5-3
5.3.6 Inner Layer Routing .........................................................................5-3
5.3.7 Impedance Calculation Tools...........................................................5-4
5.3.8 Testing Board Impedance................................................................5-4
5.3.9 Board Impedance/Stackup Summary ..............................................5-5

System Design Considerations..................................................................................6-1
6.1

6.2
6.3
6.4

Power Delivery..............................................................................................6-1
6.1.1 Terminology and Definitions ............................................................6-1
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery ......6-2
6.1.3 64/72Mbit RDRAM Excessive Power Consumption ........................6-5
Power Plane Splits........................................................................................6-7
Thermal Design Power .................................................................................6-7
Glue Chip 3 (Intel® 820 Chipset Glue Chip) .................................................6-8

A

Reference Design Schematics: Uni-Processor......................................................... A-1
A.1
Reference Design Feature Set .................................................................... A-1

B

Reference Design Schematics: Dual-Processor....................................................... B-1
B.1
Reference Design Feature Set .................................................................... B-1

Intel® 820 Chipset Design Guide

v

Figures
1-1
1-2
1-3
1-4
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
2-32
2-33
2-34
2-35
2-36
2-37
2-38
2-39
2-40
2-41
2-42
2-43

vi

Intel® 820 Chipset Platform Performance Desktop Block Diagram ..............1-5
Intel® 820 Chipset Platform Performance Desktop Block Diagram
(with ISA Bridge)...........................................................................................1-6
Intel® 820 Chipset Platform Dual-Processor Performance Desktop
Block Diagram ..............................................................................................1-7
AC’97 Connections .....................................................................................1-11
MCH 324-uBGA Quadrant Layout (Top View)..............................................2-2
ICH 241-uBGA Quadrant Layout (Top View)................................................2-2
Sample ATX MCH/ICH Component Placement............................................2-3
Primary Side MCH Core Routing Example (ATX) ........................................2-4
Secondary Side MCH Core Routing Example (ATX)....................................2-5
Data Strobing Example.................................................................................2-6
Effect of Crosstalk on Strobe Signal .............................................................2-6
RIMM Diagram..............................................................................................2-7
RSL Routing Dimensions..............................................................................2-9
RSL Routing Diagram...................................................................................2-9
Primary Side RSL Breakout Example.........................................................2-10
Secondary Side RSL Breakout Example ....................................................2-11
Direct RDRAM Termination ........................................................................2-11
Direct Rambus* Termination Example........................................................2-12
Incorrect Direct Rambus* Ground Plane Referencing ................................2-13
Direct Rambus Ground Plane Reference ...................................................2-13
Connector Compensation Example ............................................................2-16
Section A1, Top Layer.................................................................................2-17
Section A1, Bottom Layer ...........................................................................2-18
Section B1, Top Layer.................................................................................2-19
Section B1, Bottom Layer ...........................................................................2-20
RSL Signal Layer Alternation .....................................................................2-21
RDRAM Trace Length Matching Example..................................................2-22
"Dummy" Via vs. Real "Via" ........................................................................2-23
RAMRef Generation Example Circuit ........................................................2-25
High-Speed CMOS Termination .................................................................2-26
SIO Routing Example .................................................................................2-26
RDRAM CMOS Shunt Transistor ..............................................................2-27
AGP 2X/4X Routing Example for Interfaces < 6”........................................2-34
Top Signal Layer.........................................................................................2-37
AGP VDDQ Generation Example Circuit....................................................2-39
AGP 2.0 VREF Generation & Distribution ..................................................2-40
Hub Interface Signal Routing Example.......................................................2-43
Single Hub Interface Reference Divider Circuit ..........................................2-44
Locally generated Hub Interface Reference Dividers .................................2-45
Intel® Pentium® III Processor Dual Processor Configuration .....................2-46
Intel® Pentium® III Processor Uni-Processor Configuration .......................2-46
Ground Plane Reference (Four Layer Motherboard)..................................2-47
Hole Locations and Keepout Zones For Support Components ..................2-48
Grounding Pad Dimensions for the SECC2 GRM ......................................2-48
TCK/TMS Implementation Example for DP Designs ..................................2-52
Single Processor BREQ Strapping Requirements......................................2-52
Dual-Processor BREQ Strapping Requirements ........................................2-53

Intel® 820 Chipset Design Guide

2-44
2-45
2-46
2-47
2-48
2-49
2-50
2-51
2-52
2-53
2-54
2-55
2-56
2-57
2-58
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
5-1
5-2
5-3
5-4
6-1
6-2
6-3
6-4

BREQ0# Circuitry for DP Systems..............................................................2-53
HA7# Strapping Option Example Circuit (For Debug Purposes Only)........2-54
Host-Side IDE Cable Detection...................................................................2-57
Drive-Side IDE Cable Detection..................................................................2-58
Layout for Host- or Drive-Side IDE Cable Detection...................................2-59
Ultra ATA/66 Cable .....................................................................................2-59
Resistor Requirements for Primary IDE Connector ....................................2-60
Resistor Requirements for Secondary IDE Connector ...............................2-61
Tee Topology AC'97 Trace Length Requirements......................................2-62
Daisy-Chain Topology AC'97 Trace Length Requirements ........................2-62
USB Data Signals .......................................................................................2-65
PCI Bus Layout Example ............................................................................2-67
External Circuitry for the ICH RTC..............................................................2-68
Diode Circuit Connecting RTC External Battery .........................................2-69
RTCRST External Circuit for the ICH RTC .................................................2-70
PICD[1,0] Uni-Processor Topology.............................................................3-12
PICD[1,0] Dual-Processor Topology...........................................................3-12
Test Load vs. Actual System Load .............................................................3-14
Aggressor and Victim Networks..................................................................3-17
Transmission Line Geometry: (A) Microstrip (B) Stripline...........................3-17
One Signal Layer and One Reference Plane..............................................3-21
Layer Switch with One Reference Plane ....................................................3-21
Layer Switch with Multiple Reference Planes (same type) .........................3-21
Layer Switch with Multiple Reference Planes .............................................3-22
One Layer with Multiple Reference Planes.................................................3-22
Overdrive Region and VREF Guardband.....................................................3-25
Rising Edge Flight Time Measurement.......................................................3-25
Intel® 820 Chipset Platform Clock Distribution .............................................4-2
Intel® 820 Chipset Clock Routing Guidelines ...............................................4-4
CK133 to DRCG Routing Diagram ...............................................................4-6
MCH to DRCG Routing Diagram ..................................................................4-7
Direct Rambus* Clock Routing Dimensions..................................................4-7
Differential Clock Routing Diagram (Section ‘A’, ‘C’, & ‘D’)...........................4-9
Non-Differential Clock Routing Diagram (Section ‘B’)...................................4-9
Termination for Direct Rambus* Clocking Signals CFM/CFM# ....................4-9
DRCG Impedance Matching Network.........................................................4-10
DRCG Layout Example...............................................................................4-11
DRCG+ Frequency Selection .....................................................................4-13
28Ω Trace Geometry ....................................................................................5-2
Microstrip and Stripline Cross-section for 28 Ω Trace ..................................5-4
7 mil Stackup (Not Routable) ........................................................................5-5
4.5 mil Stackup .............................................................................................5-5
Intel® 820 Chipset Power Delivery Example.................................................6-2
1.8V and 2.5V Power Sequencing (Schottky Diode) ....................................6-4
Use a GPO to Reduce DRCG Frequency.....................................................6-6
Power Plane Split Example...........................................................................6-7

Intel® 820 Chipset Design Guide

vii

Tables
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
3-1
3-2
3-3
3-4
3-5
4-1
4-2
4-3
4-4
4-5
4-6
4-7
5-1
5-2
6-1
6-2

viii

Intel® 820 Chipset Platform Bandwidth Summary ........................................1-4
AGP 2X Data/Strobe Association .................................................................2-6
Placement Guidelines for Motherboard Routing Lengths .............................2-9
Copper Tab Area Calculation .....................................................................2-15
RSL Routing Layer Requirements ..............................................................2-21
Line Matching and Via Compensation Example .........................................2-24
Signal List ...................................................................................................2-28
AGP 2.0 Data/Strobe Associations.............................................................2-33
AGP 2.0 Routing Summary ........................................................................2-35
TYPDET#/VDDQ Relationship ...................................................................2-38
Connector/Add-in Card Interoperability ......................................................2-42
Voltage/Data Rate Interoperability..............................................................2-42
Segment Descriptions and Lengths for Figure 2-36 ...................................2-46
Processor and 82820 MCH Connection Checklist......................................2-49
Bus Request Connection Scheme for DP Intel® 820 Chipset Designs.......2-52
ICH Codec Options.....................................................................................2-61
AC'97 SDIN Pulldown Resistors .................................................................2-63
AGTL+ Parameters for Example Calculations ..............................................3-6
Example TFLT_MAX Calculations for 133 MHz Bus .......................................3-7
Example TFLT_MIN Calculations (Frequency Independent)...........................3-8
Trace Width Space Guidelines ...................................................................3-11
Host Clock Routing .....................................................................................3-12
Intel® 820 Chipset Platform System Clocks..................................................4-1
Intel® 820 Chipset Platform Clock Skews.....................................................4-3
Intel® 820 Chipset Platform System Clock Cross-Reference .......................4-5
Placement Guidelines for Motherboard Routing Lengths .............................4-8
External DRCG Component Values ...........................................................4-10
Unused Output Termination........................................................................4-12
DRCG Ratio................................................................................................4-12
28Ω Stackup Examples ................................................................................5-3
3D Field Solver vs ZCALC............................................................................5-4
Intel® 820 Chipset Component Thermal Design Power................................6-7
Glue Chip 3 Vendors ....................................................................................6-8

Intel® 820 Chipset Design Guide

Revision History
Revision
-001

Description
Initial Release.

Date
November 1999

• Added dual-processor schematics (Appendix B).
-002

-003

-004

• Uni-processor schematics have been updated (Appendix A). See the
schematic revision history page at the end of Appendix A for details.
- The following update is not in the schematic revision history.
Cap C249 (schematic page 9) has been changed from 0.022 uF to
0.047 uF.
• Updated the text descriptions in the two paragraphs in Section 4.2.3,
“MCH to DRCG”.
• Updated the first paragraph in Section 2.6.2.5, “RSL Signal Layer
Alternation“.
• Minor edits for clarity

Intel® 820 Chipset Design Guide

December 1999

January 2000

July 2000

ix

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x

Intel® 820 Chipset Design Guide

1
Introduction

This page is intentionally left blank.

Introduction

Introduction

1

The Intel® 820 Chipset Design Guide provides design recommendations for systems using the
Intel® 820 chipset. This includes motherboard layout and routing guidelines, system design issues
and requirements, debug recommendations, and board schematics. The design recommendations
should be used during system design. The guidelines have been developed to ensure maximum
flexibility for board designers while reducing the risk of board-related issues.
The Intel board schematics in Appendix A (uni-processor) and Appendix B (dual-processor) can be
used as references for board designers. A feature list is provided at the beginning of each appendix.
Although these schematics cover specific designs, the core schematics for each chipset component
remains the same for most Intel® 820 chipset platforms. The appendices provides a set of reference
schematics for each chipset component, in addition to common motherboard options. Additional
flexibility is possible through other permutations of these options and components.

1.1

About This Design Guide
This design guide is intended for hardware designers who are experienced with PC architectures
and board design. The design guide assumes that the designer has a working knowledge of the
vocabulary and practices of PC hardware design.

• This chapter introduces the designer to the purpose and organization of this design guide, and
provides a list of references of related documents. This chapter also provides an overview of
the Intel® 820 chipset.

• Chapter 2, "Layout/Routing Guidelines"—This chapter provides a detailed set of motherboard
layout and routing guidelines for designing an Intel® 820 chipset based platform. The
motherboard functional units are covered (e.g., chipset component placement, system bus
routing, system memory layout, display cache interface, hub interface, IDE, AC’97, USB,
interrupts, SMBUS, PCD, LPC/FWH Flash BIOS, and RTC).

• Chapter 3, "Advanced System Bus Design"— AGTL+ guidelines and theory of operation are
discussed. This chapter also provides more detail about the methodologies used to develop the
guidelines.

• Chapter 4, "Clocking"— This chapter provides motherboard clocking guidelines (e.g., clock
architecture, routing, capacitor sites, clock power decoupling, and clock skew).

• Chapter 5, "System Manufacturing"— This chapter includes board stackup requirements.
• Chapter 6, "System Design Considerations"— This chapter includes guidelines regarding
power delivery, decoupling, thermal, and power sequencing.

• Appendix A, "Reference Board Schematics: Uni-Processor "— This appendix provides a set
of schematics for Uni-processor designs. A feature list for the board design is also provided.

• Appendix B, "Reference Board Schematics: Dual-Processor "— This appendix provides a set
of schematics for dual-processor designs. A feature list for the board design is also provided.

Intel®820 Chipset Design Guide

1-1

Introduction

1.2

References
• Intel® 820 Chipset: Intel® 82820 Memory Controller Hub (MCH) Datasheet
•
•
•
•
•
•
•
•
•
•
•
•
•

1.3

(Order Number: 290630)
Intel® 82801AA (ICH) and Intel® 82801AB (ICH0) I/O Controller Hub Datasheet
(Order Number: 290655)
Intel® 82802AB/82802AC FirmWare Hub (FWH) Datasheet (Order Number: 290658)
Pentium® II Processor AGTL+ Guidelines (Order Number: 243330)
Pentium® II Processor Power Distribution Guideline (Order Number: 243332)
Pentium® II Processor Developer's Manual (Order Number: 243341)
Pentium® III Processor Specification Update (latest off of website)
AP 907 Pentium III processor Power Distribution Guidelines (Order Number 245085)
AP-585 Pentium II Processor AGTL+ Guidelines (Order Number: 243330)
AP-587 Pentium II Processor Power Distribution Guidelines (Order Number: 243332)
CK97 Clock Synthesizer Design Guidelines (Order Number 243867)
PCI Local Bus Specification, Revision 2.2
Universal Serial Bus Specification, Revision 1.0
VRM 8.4 DC-DC Converter Design Guidelines (when available)

System Overview
The Intel® 820 chipset is the third generation desktop chipset designed for Intel’s SC242
architecture and the first chipset to support the 4X capability of the AGP 2.0 Interface Specification
and 400 MHz Direct RDRAM. The 400 MHz, 16 bit, double clocked Direct RDRAM interface
provides 1.6 GB/s access to main memory. A new chipset component interconnect, the hub
interface, is designed into the Intel® 820 chipset to provide more efficient communication between
chipset components.
Support of AGP 4X, 400 MHz Direct RDRAM and the hub interface provides a balanced system
architecture for the Pentium III processor, minimizing bottlenecks and increasing system
performance. By increasing memory bandwidth to 1.6 GB/s through the use of 400 MHz Direct
RDRAM and increasing graphics bandwidth to 1 GB/s through the use of AGP 4X, the Intel® 820
chipset delivers the data throughput necessary to take advantage of the high performance provided
by the powerful Pentium III processor.
In addition, the Intel® 820 chipset architecture enables a new security and manageability
infrastructure through the Firmware Hub component.
The ACPI compliant Intel® 820 chipset platform can support the Full-on, Stop Grant, Suspend to
RAM, Suspend to Disk, and Soft-off power management states. Through the use of an appropriate
LAN device, Intel® 820 chipset also supports Wake on LAN* for remote administration and
troubleshooting.
The Intel® 820 chipset architecture removes the requirement for the ISA expansion bus that was
traditionally integrated into the I/O subsystem of Intel chipsets. This removes many of the conflicts
experienced when installing hardware and drivers into legacy ISA systems. The elimination of ISA
provides true plug-and-play for the Intel® 820 chipset platform. Traditionally, the ISA interface
was used for audio and modem devices. The addition of AC’97 allows the OEM to use software

1-2

Intel®820 Chipset Design Guide

Introduction

configurable AC’97 audio and modem coder/decoders (codecs) instead of the traditional ISA
devices. The ISA bus can be implemented through the use of the optional 82380AB PCI-ISA
bridge.
The Intel® 820 chipset contains two core components: the Memory Controller Hub (MCH) and the
I/O Controller Hub (ICH). The MCH integrates the 133 MHz processor system bus controller,
AGP 2.0 controller, 400 MHz Direct RDRAM controller and a high-speed hub interface for
communication with the ICH. The ICH integrates an UltraATA/66 controller, USB host controller,
LPC interface controller, FWH Flash BIOS interface controller, PCI interface controller, AC’97
digital controller and a hub interface for communication with the MCH. The Intel® 820 chipset
provides the data buffering and interface arbitration required to ensure that system interfaces
operate efficiently and provide the system bandwidth necessary to obtain peak performance with
the Pentium III processor.

1.3.1

Chipset Components
This section provides an overview of the 82820 Memory Controller Hub (MCH) and the 82801AA
I/O Controller Hub (ICH). Additional functionality can be provided using the 82380AB PCI-ISA
bridge.

Memory Controller Hub (MCH)
The MCH provides the interconnect between the Direct RDRAM and the system logic. It integrates
the following functions:

• Support for single or dual SC242 processors with 100 MHz or 133 MHz System Bus
• 256 MHz, 300 MHz, 356 MHz or 400 MHz Direct RDRAM interface supporting 1 GB of
Direct RDRAM

• 4X, 1.5V AGP interface (3.3V 1X, 2X and 1.5V 1X, 2X devices also supported)
• Downstream hub interface for access to the ICH
In addition, the MCH provides arbitration, buffering and coherency management for each of these
interfaces. Refer to Chapter 2, “Layout/Routing Guidelines” for more information regarding these
interfaces.

Intel®820 Chipset Design Guide

1-3

Introduction

I/O Controller Hub (ICH)
The I/O Controller Hub provides the I/O subsystem with access to the rest of the system.
Additionally, it integrates many I/O functions. The ICH integrates the following functions:

•
•
•
•
•
•
•
•
•
•
•

Upstream hub interface for access to the MCH
2 channel Ultra ATA/66 Bus Master IDE controller
USB controller
I/O APIC
SMBus controller
FWH interface (FWH Flash BIOS)
LPC interface
AC’97 2.1 interface
PCI 2.2 interface
Integrated System Management Controller
Alert on LAN*

The ICH also contains the arbitration and buffering necessary to ensure efficient utilization of these
interfaces. Refer to Chapter 2, “Layout/Routing Guidelines” for more information on these
interfaces.

ISA Bridge (82380AB)
For legacy needs, ISA support is an optional feature of the Intel® 820 chipset. Implementations that
require ISA support can benefit from the enhancements of the Intel® 820 chipset while “ISA-less”
designs are not burdened with the complexity and cost of the ISA subsystem.
The Intel® 820 chipset platform with optional ISA support takes advantage of the 82380AB ISA
bridge. The bridge is a PCI to ISA bridge and resides on the PCI bus of the ICH.

1.3.2

Bandwidth Summary
Table 1-1 provides a summary of the bandwidth requirements for the Intel® 820 chipset.

Table 1-1. Intel® 820 Chipset Platform Bandwidth Summary
Interface

Clock Speed
(MHz)

Samples
Per Clock

Data Rate
(Mega-samples/s)

Data Width
(Bytes)

Bandwidth
(MB/s)

Processor Bus

133

1

133

8

1066

266/300/356/400

2

533/600/711/800

2

1066/1200/1422/1600

RDRAM

1-4

AGP 2.0

66

4

266

4

1066

Hub Interface

66

4

266

1

266

PCI 2.2

33

1

33

4

133

Intel®820 Chipset Design Guide

Introduction

1.3.3

System Configuration
The following figures show typical platform configurations using the Intel® 820 chipset.

Figure 1-1. Intel® 820 Chipset Platform Performance Desktop Block Diagram

Processor

4X AGP
Graphics
Controller

AGP 2.0

82820
Memory
Controller Hub
(MCH)

Main
Memory

Hub Interface
PCI Slots
4 IDE Drives
PCI Bus
2 USB Ports

AC'97 Codec(s)
(optional)

Keyboard,
Mouse, FD,
PP, SP, IR

AC'97 2.1

82801AA
I/O Controller Hub
(ICH)

LPC I/F
Super I/O

GPIO

FWH Flash
BIOS

Intel®820 Chipset Design Guide

1-5

Introduction

Figure 1-2. Intel® 820 Chipset Platform Performance Desktop Block Diagram (with ISA Bridge)

Processor

4X AGP
Graphics
Controller

AGP 2.0

82820
Memory
Controller Hub
(MCH)

Main
Memory

Hub Interface
PCI Slots
4 IDE Drives
PCI Bus
2 USB Ports

AC'97 Codec(s)
(optional)

Keyboard,
Mouse, FD,
PP, SP, IR

AC'97 2.1

Super I/O

82801AA
I/O Controller Hub
(ICH)

LPC I/F

ISA Bridge
(optional)

ISA Slots

GPIO

FWH Flash
BIOS

1-6

Intel®820 Chipset Design Guide

Introduction

Figure 1-3. Intel® 820 Chipset Platform Dual-Processor Performance Desktop Block Diagram

Processor

Processor

Optional 2-Way/MP

4X AGP
Graphics
Controller

AGP 2.0

82820
Memory
Controller Hub
(MCH)

Main
Memory

Hub Interface
PCI Slots
4 IDE Drives
PCI Bus
2 USB Ports

AC'97 Codec(s)
(optional)

Keyboard,
Mouse, FD,
PP, SP, IR

AC'97 2.1

Super I/O

82801AA
I/O Controller Hub
(ICH)

LPC I/F

ISA Bridge
(optional)

ISA Slots

GPIO

FWH Flash
BIOS
blk3

Intel®820 Chipset Design Guide

1-7

Introduction

1.4

Platform Initiatives

1.4.1

Direct Rambus*
The Direct Rambus* (RDRAM) initiative provides the memory bandwidth necessary to obtain
optimal performance from the Pentium III processor as well as a high-performance AGP graphics
controller. The MCH RDRAM interface supports 266 MHz, 300 MHz, 356 MHz, and 400 MHz
operation; the latter delivers 1.6 GB/s of theoretical memory bandwidth; twice the memory
bandwidth of 100 MHz SDRAM systems. Coupled with the greater bandwidth, the RDRAM
protocol, which is heavily pipelined, provides substantially more efficient data transfer. The
RDRAM memory interface can achieve greater than 95% utilization of the 1.6 GB/s theoretical
maximum bandwidth.
In addition to RDRAM’s performance features, the new memory architecture provides enhanced
power management capabilities. The powerdown mode of operation enables Intel® 820 chipset
based systems to cost-effectively support suspend-to-RAM.

1.4.2

Streaming SIMD Extensions
The Pentium III processor provides 70 new Streaming SIMD (single instruction, multiple data)
Extensions. The Pentium III new extensions are floating point SIMD extensions. Intel MMX™
technology provides integer SIMD extensions. The Pentium III processor new extensions
complement the Intel MMX™ technology SIMD extensions and provide a performance boost to
floating-point intensive 3D applications.

1.4.3

AGP 2.0
The AGP 2.0 interface, along with Direct Rambus* memory technology, allows graphics
controllers to access main memory at over 1 GB/s; twice the AGP bandwidth of previous AGP
platforms. AGP 2.0 provides the infrastructure necessary for photorealistic 3D. In conjunction with
Direct Rambus* and the Pentium III processor new Streaming SIMD Extensions, AGP 2.0 delivers
the next level of 3D graphics performance.

1.4.4

Hub Interface
As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become
significant. With the addition of AC’97 and ATA/66, coupled with the existing USB, I/O
requirements will begin to impact PCI bus performance. The Intel® 820 chipset’s hub interface
architecture ensures that the I/O subsystem, both PCI and the integrated I/O features (IDE, AC’97,
USB, etc.), receives adequate bandwidth. By placing the I/O bridge on the hub interface instead of
PCI, the hub architecture ensures that both the I/O functions integrated into the ICH and the PCI
peripherals obtain the bandwidth necessary for peak performance. In addition, the hub interface’s
lower pin count allows a smaller package for the MCH and ICH.

1-8

Intel®820 Chipset Design Guide

Introduction

1.4.5

Manageability
The Intel® 820 chipset platform integrates several functions designed to manage the system and
lower the total cost of ownership (TCO) of the system. These system management functions are
designed to report errors, diagnose the system, and recover from system lockups without the aid of
an external microcontroller.

TCO Timer
The ICH integrates a programmable TCO Timer. This timer is used to detect system locks. The first
expiration of the timer generates an SMI# which the system can use to recover from a software
lock. The second expiration of the timer causes a system reset to recover from a hardware lock.

CPU Present Indicator
The ICH looks for the CPU to fetch the first instruction after reset. If the CPU does not fetch the
first instruction, the ICH will reboot the system at the safe-mode frequency multiplier.

ECC Error Reporting
Upon detecting an ECC error, the MCH can send one of several messages to the ICH. The MCH
can instruct the ICH to generate either an SMI#, NMI#, SERR#, or TCO interrupt.

Function Disable
The ICH provides the ability to disable the following functions: AC'97 Modem, AC'97 Audio,
IDE, USB or SMBus. Once disabled, these functions no longer decode I/O, memory, or PCI
configuration space. Also, no interrupts or power management events are generated from the
disabled functions.

Intruder Detect
The ICH provides an input signal (INTRUDER#) that can be attached to a switch that is activated
by the system case being opened. The ICH can be programmed to generate an SMI# or TCO
interrupt due to an active INTRUDER# signal.

SMBus
The ICH integrates an SMBus controller. The SMBus provides an interface to manage peripherals
(e.g., serial presence detection (SPD) on RIMMs and thermal sensors).

Alert on LAN*
The ICH supports Alert on LAN*. In response to a TCO event (intruder detect, thermal event, CPU
not booting) the ICH sends a message over ALERTCLK and ALERTDATA. A LAN controller can
decode this alert message and send a message over the network to alert the network manager.

Intel®820 Chipset Design Guide

1-9

Introduction

1.4.6

AC’97
The Audio Codec’97 (AC’97) Specification defines a digital link that can be used to attach an
audio codec (AC), a modem codec (MC), an audio/modem codec (AMC), or both an AC and an
MC. The AC’97 Specification defines the interface between the system logic and the audio or
modem codec known as the AC’97 Digital Link.
The ability to add cost-effective audio and modem solutions is important as the platform migrates
away from ISA. In addition, the AC’97 audio and modem components are software configurable.
This reduces configuration errors. Intel® 820 chipset’s AC’97 (with the appropriate codecs) not
only replaces ISA audio and modem functionality, but also improves overall platform integration
by incorporating the AC’97 digital link. Using Intel® 820 chipset’s integrated AC’97 digital link
reduces cost and eases migration from ISA.
By using an audio codec, the AC’97 digital link allows for cost-effective, high-quality, integrated
audio on the Intel® 820 chipset platform. In addition, an AC’97 soft modem can be implemented
with the use of a modem codec. Several system options exist when implementing AC’97. Intel®
820 chipset’s integrated digital link allows two external codecs to be connected to the ICH. The
system designer can provide audio with an audio codec (Figure 1-4a) or a modem with a modem
codec (Figure 1-4b). For systems requiring both audio and a modem, there are two solutions. The
audio codec and the modem codec can be integrated into a single Audio Modem Codec (AMC)
(Figure 1-4c), or separate audio and modem codecs can be connected to the ICH (Figure 1-4d).
Modem implementation for different countries must be considered as telephone systems may vary.
By using a split design, the audio codec can be on-board and the modem codec can be placed on a
riser. With a single integrated codec, or AMC, both audio and modem can be routed to a connector
near the rear panel where the external ports can be located.
The digital link in the ICH is AC’97 Rev. 2.1 compliant, supporting two codecs with independent
PCI functions for audio and modem. Microphone input and left and right audio channels are
supported for a high quality two-speaker audio solution. Wake on ring from suspend is also
supported with an appropriate modem codec.

1-10

Intel®820 Chipset Design Guide

Introduction

Figure 1-4. (a-d) AC’97 Connections
a) AC'97 With Audio Codec

ICH
(241 mBGA)

AC'97 Digital
Link

AC'97
Audio
Codec

Audio Ports

b) AC'97 With Modem Codec

ICH
(241 mBGA)

AC'97 Digital
Link

AC'97
Modem
Codec

Modem Port

c) AC'97 With Audio/Modem Codec

ICH
(241 mBGA)

AC'97 Digital
Link

AC'97
Audio/
Modem
Codec

Modem Port

Audio Ports

d) AC'97 With Audio and Modem Codec

ICH
(241 mBGA)

AC'97
Digital Link

AC'97
Modem
Codec

AC'97
Audio
Codec

1.4.7

Modem Port

Audio Ports

Low Pin Count (LPC) Interface
In the Intel® 820 chipset platform, the super I/O component has migrated to the Low Pin Count
(LPC) interface. Migration to the LPC interface allows for lower cost super I/O designs. The LPC
super I/O component requires the same feature set as traditional super I/O components. It should
include a keyboard and mouse controller, floppy disk controller and serial and parallel ports. In
addition to the super I/O features, an integrated game port is recommended because the AC’97
interface does not provide support for a game port. In a system with ISA audio, the game port
typically existed on the audio card. The fifteen pin game port connector provides for two joysticks
and a two-wire MPU-401 MIDI interface. Consult your super I/O vendor for a comprehensive list
of devices offered and features supported.
In addition, depending on system requirements, a device bay controller and USB hub could be
integrated into the LPC super I/O component. For systems requiring ISA support, an ISA-IRQ to
serial-IRQ converter is required. Potentially, this converter could be integrated into the super I/O.

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Introduction

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1-12

Intel®820 Chipset Design Guide

2
Layout and Routing
Guidelines

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Layout/Routing Guidelines

Layout/Routing Guidelines

2

This chapter documents motherboard layout and routing guidelines for Intel® 820 chipset based
systems. This section does not discuss the functional aspects of any bus, or the layout guidelines
for an add-in device.
Caution:

2.1

If the guidelines listed in this document are not followed, it is very important that thorough
signal integrity and timing simulations are completed for each design. Even when the
guidelines are followed, critical signals should still be simulated to ensure proper signal integrity
and flight time. As bus speeds increase, it is imperative that the guidelines documented are
followed precisely. Any deviation from these guidelines must be simulated!

General Recommendations
The trace impedance typically noted (i.e., 60 Ω ±10%) is the “nominal” trace impedance. That is,
the impedance of the trace when not subjected to the fields created by changing current in
neighboring traces. When calculating flight times, it is important to consider the minimum and
maximum impedance of a trace based on the switching of neighboring traces. Using wider spaces
between the traces can minimize this trace-to-trace coupling. In addition, these wider spaces reduce
crosstalk and settling time.
Coupling between two traces is a function of the coupled length, the distance separating the traces,
the signal edge rate, and the degree of mutual capacitance and inductance. In order to minimize the
effects of trace-to-trace coupling, the routing guidelines documented in this section should be
followed. In addition, the PCB should be fabricated as documented in Section 5.3, “Stackup
Requirement” on page 5-1 of this document.
All recommendations in this section (except where noted) assume 5 mil wide traces. If trace width
is greater than 5 mils then the trace spacing requirements must be adjusted accordingly (linearly).
For example, this section recommends routing most AGP signals with 5 mil traces on 20 mil spaces
(1:4). If 6 mil traces are used, then 24 mil spaces must be used (also 1:4). Using a wider trace (and
therefore wider spaces) will make routing more difficult.
Additionally, these routing guidelines are created using the stack-up described in section
Section 5.3, “Stackup Requirement” on page 5-1. If this stack-up is not used, extremely thorough
simulations of every interface must be completed. Using a thicker dielectric (prepreg) will make
routing very difficult or impossible.

2.2

Component Quadrant Layout
The quadrant layouts shown are approximate and the exact ball assignments should be used to
conduct routing analysis. These quadrant layouts are designed for use during component
placement.

Intel®820 Chipset Design Guide

2-1

Layout/Routing Guidelines

Figure 2-1. MCH 324-uBGA Quadrant Layout (Top View)

System Bus

AGP 2.0

System Bus

Hub Interface

MCH
(324-uBGA)

Direct RDRAM

Figure 2-2. ICH 241-uBGA Quadrant Layout (Top View)
Pin #1 Corner
PCI

Processor

ICH
241 uBGA

Hub Interface

AC'97,
SMBus

LPC

2-2

IDE

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

2.3

Intel® 820 Chipset Component Placement
Notes:
1. The ATX placements and layouts shown in Figure 2-3 is recommended for single (UP) Intel® 820
chipset based system design.

2. The trace length limitation between critical connections will be addressed later in this
document.
3. The figure is for reference only.
Figure 2-3. Sample ATX MCH/ICH Component Placement

Processor Host Bus

MCH

H

ub

In

te

rfa

ce

AGP
2.0

Direct
RDRAM

RDRAM Termination
ICH

Intel®820 Chipset Design Guide

2-3

Layout/Routing Guidelines

2.4

Core Chipset Routing Recommendations
Figure 2-4 and Figure 2-5 show MCH core routing examples.

Figure 2-4. Primary Side MCH Core Routing Example (ATX)

2-4

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

Figure 2-5. Secondary Side MCH Core Routing Example (ATX)

2.5

Source Synchronous Strobing
Source synchronous strobing is one of the technologies used in AGP 4X, Direct RDRAM and hub
interface that allow very high data transfer rates. As buses get faster, and cycle times get shorter,
the propagation delay is becoming a limiting factor in bus speed. Source synchronous strobing is
used to minimize the impact of propagation delay (Tprop) on maximum bus frequency.
A source synchronous strobed interface uses strobe signals (instead of the clock) to indicate that
data is valid. Refer to Figure 2-6 for an example.

Intel®820 Chipset Design Guide

2-5

Layout/Routing Guidelines

Figure 2-6. Data Strobing Example
Data
Sample
Clock
Strobe
Data
data_str.vsd

For a source synchronous strobed interface, it is very important that the strobe signals are routed
carefully. These signals must be very clean (free of noise). Data signals are typically latched on the
rising or falling edge of the strobe signal (or both). If there is noise on these signals, it could cause
an extra “edge” to be detected, thus latching incorrect data. Refer to Figure 2-7 for examples.
Figure 2-7. Effect of Crosstalk on Strobe Signal
a) Correct Strobing Example (no noise)

b) Effect of Crosstalk on Strobe Signal

Data is correctly
latchecd as a "0"

clock
Data

clock
Data

Data is incorrectly
latchecd as a "1"

Noise
(i.e.,
crosstalk)

Threshold

Threshold

Strobe

Strobe

Some buses have more than one strobe (i.e., AGP). The AGP 1.0 specification (1X and 2X mode)
employs 3 strobe signals. These three strobe signals are each used to strobe different data signals.
That is, each strobe has an associated set of data signals. The associations for AGP 1.0 (AGP 2X)
are documented in Table 2-1. Refer to Section 2.7, “AGP 2.0” on page 2-31 for more information
on AGP 2.0 (AGP 4X, 1.5v).
Table 2-1. AGP 2X Data/Strobe Association
Data

Associated Strobe

AD[15:0] and C/BE[1:0]#

AD_STB0

AD[31:16] and C/BE[3:2]#

AD_STB1

SBA[7:0]

SB_STB

In this example, the lower address signals (AD[15:0]) are sampled on the rising and falling edges
of AD_STB0, while the upper address signals (AD[31:16]) are sampled on the rising and falling
edges of AD_STB1.

2-6

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

When routing strobes and their associated data lines, trace length mismatch is very important (in
addition to noise immunity). The primary benefit of source synchronous strobing is that the data
and the strobe arrive at the receiver simultaneously. Thus, a strobe and its associated data signals
have very critical length mismatch requirements. With well matched trace lengths (as well as
matched impedance), the propagation delay for the strobe, and the propagation delay for the data
will be very close. Hence, the strobe and the data arrive at the receiver simultaneously. For some
interfaces, the trace length mismatch requirement is less than 0.25 inch.

2.6

Direct Rambus* Interface
The Direct Rambus* Channel is a multi-symbol interconnect. Due to the length of the interconnect
and the frequency of operation, this bus is designed to allow multiple command and data packets to
be present on a signal wire at any given instant. The driving device sends the next data out before
the previous data has left the bus.

Figure 2-8. RIMM Diagram

The nature of the multi-symbol interconnect forces many requirements on the bus design and
topology. First and foremost, a drastic reduction in reflected voltage levels is required. The
interconnect transmission lines must be terminated at their characteristic impedance, or the
reflected voltage resulting from a mismatch in impedance will degrade signal quality. These
reflections will reduce noise and timing margins, and reduce the maximum operating frequency of
the bus. Potentially, the reflections could create data errors.
Due to the tolerances of components such as PCBs, connectors, and termination resistors, there will
be some reflected voltage on the interconnect. In this multi-symbol interconnect, timings are
pattern dependent due to the reflections interfering with the next transfer.
Additionally, coupled noise can greatly affect the performance of high-speed interfaces. Just as in
source synchronous designs, the odd and even mode propagation velocity change creates skew
between the clock and data or command lines which reduces the maximum operating frequency of
the bus. Efforts must be made to significantly decrease crosstalk, as well as the other sources of
skew.
To achieve these bus requirements, the Direct Rambus* channel is designed to operate as a
transmission line; all components, including the individual RDRAMs, are incorporated into the
design to create a uniform bus structure that can support up to 33 devices (including the MCH)
running at 800 MegaTransfers/second (MT/s).

Intel®820 Chipset Design Guide

2-7

Layout/Routing Guidelines

2.6.1

Stackup
The perfect matching of transmission line impedance and uniform trace length are essential for the
Direct RDRAM interface to work properly. Maintaining 28 Ω (±10%) loaded impedance for every
RSL (Direct Rambus* Signaling Level) signal has changed the requirements for trace width and
prepreg thickness for the Intel® 820 chipset platform (refer to Section 5.3, “Stackup Requirement”
on page 5-1).
Achieving a 28 Ω nominal impedance with a traditional 7 mil prepreg requires 28 mil wide traces.
These traces are too wide to break out of the two rows of RSL balls on the MCH. To reduce trace
width, a 4.5 mil thick prepreg is required. This thinner prepreg allows 18 mil wide traces to meet
the 28 Ω (±10%) nominal impedance requirement. Refer to Section 5.3, “Stackup Requirement” on
page 5-1 for detailed stackup requirements.

2.6.2

Direct Rambus* Layout Guidelines
The signals on the Direct Rambus* Channel are broken into three groups: RSL signals, CMOS
signals, and Clocking signals. The signal groups are:

• RSL Signals
— DQA[8:0]
— DQB[8:0]
— RQ[7:0]

• CMOS Signals
— CMD (high-speed CMOS signal)
— SCK (high-speed CMOS signal)
— SIO

• Clocking Signals
— CTM, CTM#
— CFM, CFM#

2.6.2.1

RSL Routing
The RSL signals enter the first RIMM on the left side, propagate through the RIMM, and exit on
the right. The signal continues through the rest of the existing RIMMs until it is terminated at
Vterm. All unpopulated slots must have continuity modules in place to ensure that the signals
propagate to the termination.

2-8

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

Figure 2-9. RSL Routing Dimensions
RIMM_0

RIMM_1

MCH
0"-3.50"

0.4"-0.45"

0"-3"

A

B

C

RIMM to
RIMM

RIMM to
Termination

MCH to
First RIMM

To maintain a nominal 28 Ω trace impedance, the RSL signals must be 18 mils wide. To control
crosstalk and odd/even mode velocity deltas, there must be a 10 mil ground isolation trace routed
between adjacent RSL signals. The 10 mil ground isolation traces must be connected to ground
with a via every 1”. A 6 mil gap is required between the RSL signals and the ground isolation trace.
These signals must be length matched to ±10 mils in line section “A” and ±2 mils in both line
sections labeled “B” using the trace length matching methods in Section 2.6.2.6, “Length Matching
Methods” on page 2-21. To ensure uniform trace lines, trace width variation must be uniform on all
RSL signals at every neck-down for each line section. All RSL signals must have the same number
of vias. It may be necessary to place vias on RSL signals where they are not necessary to meet this
via loading requirement (i.e., dummy vias).
Table 2-2. Placement Guidelines for Motherboard Routing Lengths
Reference

Trace Description

Maximum Trace Length (in.)

A

MCH to first RIMM Connector

0” to 3.50”

B

RIMM to RIMM

0.4” – 0.45”

C

RIMM to Termination

0” to 3”

Figure 2-10 shows a top view of the trace width/spacing requirements for the RSL signals.
Figure 2-10. RSL Routing Diagram

18 mils

6 mils

RSL Signal Trace
Space

10 mils
6 mils

Space

Ground

18 mils

RSL Signal Trace
6 mils

Space

10 mils
6 mils

Intel®820 Chipset Design Guide

Space

Ground

2-9

Layout/Routing Guidelines

Figure 2-11 and Figure 2-12 show a top view of an example RSL breakout and route.
Figure 2-11. Primary Side RSL Breakout Example

Ground Flood
(Shaded area)

18 mil clock
traces when
not 14:6

14 on 6
Differential
clock pair
Neckdown for BJT

Neckdown to
pass vias

BJT

2-10

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

Figure 2-12. Secondary Side RSL Breakout Example

2.6.2.2

RSL Termination
All RSL signals must be terminated to 1.8V (Vterm) using 27Ω-2% or 28Ω-1% resistors at the end
of the channel opposite the MCH. Resistor packs are acceptable. Vterm must be decoupled using
high speed bypass capacitors (one 0.1 µF ceramic chip capacitor per two RSL lines) near the
terminating resistors. Additionally, bulk capacitance is required. Assuming a linear regulator with
approximate 20 ms response time, two 100 µF tantalum capacitors are recommended. The trace
length between the last RIMM and the termination resistors should be less than 3”. Length
matching in this section of the channel is not required. The Vterm power island should be at
LEAST 50 mils wide. This voltage does not need to be supplied during suspend-to-RAM.

Figure 2-13. Direct RDRAM Termination
Terminator
R-packs

RSL Signals

Vterm

Intel®820 Chipset Design Guide

2-11

Layout/Routing Guidelines

Note:

It is necessary to compensate for the slight difference in electrical characteristics between a dummy
via and a real via. Refer to Section 2.6.2.7, “VIA Compensation” on page 2-23 for more
information on Via Compensation.

Figure 2-14. Direct Rambus* Termination Example

2 GND VIAS /
Capacitor

2-12

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

2.6.2.3

Direct Rambus* Ground Plane Reference
All RSL signals must be referenced to GND to provide an optimal current return path. The direct
Rambus ground plane reference must be continuous to the Vterm capacitors. The ground reference
island under the RSL signals must be continuous from the last RIMM to the back of the termination
capacitors. Choose the reference island shape such that power delivery to the components is not
compromised. The return current will flow through the Vterm capacitors into the ground island and
under the RSL traces. Any split in the ground island will provide a sub-optimal return path. In a 4
layer board, this will require the Vterm island to be on an outer layer. The Vterm island should
ALWAYS be placed on the top layer. Refer to Section 6.2, “Power Plane Splits” on page 6-7 for an
example of power plane splits.

Figure 2-15. Incorrect Direct Rambus* Ground Plane Referencing

Wrong

MCH

3.3V Plane

1.8V Plane
RIMM1

Wrong
RIMM2

Figure 2-16. Direct Rambus Ground Plane Reference

Required
MCH

GND Plane

1.8V Plane

3.3V Plane

RIMM1
GND Plane

GND Plane
RIMM2

Vterm Resistors
Extend GND PLANE
Reference Island Beyond
Vterm Capacitors

Vterm Capacitors
Vterm Layer Not Shown

The ground reference island under the RSL signals MUST be connected to the ground pins on the
RIMM connector and the ground vias used to connect the ground isolation on the 1st and 4th layers.

Intel®820 Chipset Design Guide

2-13

Layout/Routing Guidelines

All 4 layers of the motherboard require correct grounding between the RSL signals on the
motherboard:

•
•
•
•

Layer 1 = Ground Isolation
Layer 2 = Ground Plane
Layer 3 = Ground Reference in the Power Plane
Layer 4 = Ground Isolation

All ground vias and pins MUST be connected to all 4 layers.

2.6.2.4

Direct Rambus* Connector Compensation
The RIMM connector inductance causes an impedance discontinuity on the Direct Rambus*
channel. This may reduce voltage and timing margin.
To compensate for the inductance of the connector, approximately 0.65 pF–0.85 pF compensating
capacitive tab (C-TAB) is required on each RSL connector pin. This compensating capacitance
must be added to the following connector pins at each connector:
LCTM
RCTM
LCFM
RCFM
LROW[2:0]
LCOL[4:0]
RDQA[8:0]
RDQB[8:0]
SCK

LCTM#
RCTM#
LCFM#
RCFM#
RROW[2:0]
RCOL[4:0]
LDQA[8:0]
LDQB[8:0]
CMD

This can be achieved on the motherboard by adding a copper tab to the specified RSL pins at each
connector. The target value is approximately 0.65 pF–0.85 pF. The copper tab area for the
recommended stackup was determined through simulation. The placement of the copper tabs can
be on any signal layer, independent of the layer on which the RSL signal is routed.
Equation is an approximation that can be used for calculating copper tab area on an outer layer.
Equation 2-1. Approximate Copper Tab Area Calculation
Length*Width = Area = Cplate * Thickness of prepreg / [(ε0) (εr) (1.1)]

Where:
—
—
—
—
—

ε0 = 2.25 x 10-16 Farads/mil
εr = Relative dielectric constant of prepreg material
Thickness of prepreg = Stackup dependent
Length, Width = Dimensions in mils of copper plate to be added
Factor of 1.1 accounts for fringe capacitance.

Based on the stackup requirement in Section 5.3, “Stackup Requirement” on page 5-1 the copper
tab area should be 2800 to 3600 sq mils. Different stackups require different copper tab areas.
Table 2-3 shows example copper tab areas.

2-14

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

Table 2-3. Copper Tab Area Calculation
Dielectric
Thickness
(D)

Separation
Between
Signal Trace &
Copper Tab

Minimum
Ground
flood

Air Gap
between
Signal &
GND Flood

Compensating
Capacitance
in pF

Copper Tab
(C-TAB)
Area (A) In
sq mils

4.5

6

10

6

0.65

2800

C-TAB
Shape
(mils)
140 L x 20 W
70 L x 40 W

Based on Equation 1, the tab area is 2800 sq mils, where εr is 4.2 and D is 4.5. These values are
based on 2116 prepreg material.
Note that more than one copper tab shape may be used. The tab dimensions are based on copper
area over the ground plane. The actual length and width of the tabs may be different due to routing
constraints (e.g., if tab must extend to center of hole, or antipad); however, each copper tab should
have equivalent area. For example, the copper tabs in Figure 2-17 have the following dimensions,
when measured tangent to the antipad:
Inner C-TAB = 140 (length) x 20(width)
Outer C-TAB = 70 (length) x 40 (width)
The following figures show a routing example of tab compensation capacitors. Note that ground
floods around the RIMM pins must not be interrupted by the capacitor tabs, and they must be
connected to avoid discontinuity in the ground plane as shown.

Intel®820 Chipset Design Guide

2-15

Layout/Routing Guidelines

Figure 2-17. Connector Compensation Example

S
E
C
T
I
O
N
A

MCH

S
E
C
T
I
O
N
B

2-16

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

Figure 2-18. Section A1, Top Layer
Outer C-tab
Inner C-tab

NOTES:
1. Refer to Figure 2-17. Ground flood removed from picture for clarity

Intel®820 Chipset Design Guide

2-17

Layout/Routing Guidelines

Figure 2-19. Section A1, Bottom Layer

NOTES:
1. Refer to Figure 2-17. Ground flood removed from picture for clarity

2-18

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

Figure 2-20. Section B1, Top Layer

NOTES:
1. Refer to Figure 2-17. Ground flood removed from picture for clarity

Intel®820 Chipset Design Guide

2-19

Layout/Routing Guidelines

Figure 2-21. Section B1, Bottom Layer

NOTES:
1. Refer to Figure 2-17. Ground flood removed from picture for clarity

2.6.2.5

RSL Signal Layer Alternation
RSL signals must alternate layers as they are routed through the channel. If a signal is routed on the
primary layer from the MCH to the first RIMM socket, it must be routed on the secondary layer
from the first RIMM to the second RIMM as shown in Figure 2-22 (signal B). If a signal is routed
on the secondary layer from the MCH to the first RIMM socket, it must be routed on the primary
layer from the first RIMM to the second RIMM as shown in Figure 2-22 (signal A). Signals to the
termination resistors can be routed on either layer from the last RIMM.

2-20

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

Figure 2-22. RSL Signal Layer Alternation
Signal B

Signal on Secondary Side
Signal on Primary Side

Signal A

Signal A

MCH

Route on EITHER layer.
Ground Isolation is
REQUIRED!

Term

Signal B

Table 2-4. RSL Routing Layer Requirements

2.6.2.6

MCH to 1st RIMM

1st RIMM to 2nd RIMM

Method 1

Primary Side

Secondary Side

Method 2

Secondary Side

Primary Side

Length Matching Methods
In order to allow for greater routing flexibility, the RSL signals require pad-to-pin length matching
between the MCH and the first connector. If the trace lengths are matched between the balls of the
MCH and the pin of RIMM connector, the length mismatch between the pad (on the die) and the
ball has not been accounted. However, given the package dimension, a representation of the length
from the pad to the ball, the routing can compensate for this package mismatch. Therefore, the
board length mismatch can be increased.
The RSL channel requires matching trace lengths from pad-to-pin within ±10 mils.
Given these definitions:

• Package Dimension: a representation of the length from the pad to the ball.
• Board Trace Length: the trace length on the board.
• Nominal RSL Length: the length to which all signals are matched. (note: there is not
necessarily a trace that is EXACTLY to nominal length, but all RSL signals must be matched
to within ±10mil of a nominal length). The Nominal RSL Length is an arbitrary length (within
the limits of the routing guidelines) to which all the RSL signals will be matched (within
10 mils).
ALL RSL signals must meet the following equation.

Intel®820 Chipset Design Guide

2-21

Layout/Routing Guidelines

Equation 2-2. RDRAM RSL Signal Trace Length Calculation
Package Dimension + Board Trace Length = Nominal RSL Length ± 10mils

Figure 2-23. RDRAM Trace Length Matching Example

L1, L2 -> Package Dimensions
L3, L4 -> Board Trace Length
L1
MCH Package

Ball

MCH
Die

L2

L3

R
I
M
M

R
I
M
M

C
o
n
n
e
c
t
o
r

C
o
n
n
e
c
t
o
r

L4

V
t
e
r
m

L1 + L3 = Nominal RSL Length ±10 mils
L2 + L4 = Nominal RSL Length ±10 mils
NOTE: Refer to the Intel® 820 Chipset: Intel® 82820 Memory Controller Hub (MCH) Datasheet for component
package dimensions.

The RDRAM clocks (CTM, CTM#, CFM and CFM#) must be longer than the RDRAM signals
due to their increased trace velocity (because they are routed as a differential pair). To calculate the
length for each clock, the following formula should be used:
Equation 2-3. RDRAM Clock Signal Trace Length Calculation
Clock Length = Nominal RSL Signal Length (package + board) * 1.021

Using this formula, the clock signals will be 21 mils/inch longer than the Nominal Length. The
lengthening of the clock signals, to compensate for their trace velocity change, ONLY applies to
routing between the MCH and the first RIMM. The clock signals should be matched in length to
the RSL signals between RIMMs. Refer to Chapter 4, “Clocking” for more detailed clock routing
guidelines.
The high-speed CMOS signals must be length matched to the RSL signals within 1200 mils
(1.2 in) due to a timing requirement between CMOS and RSL signals during NAP Exit and PDN
Exit.
It is necessary to compensate for the slight difference in electrical characteristics between a dummy
via and a real via. Refer to the following section for more information on Via Compensation.

2-22

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

2.6.2.7

VIA Compensation
As described in Section 2.8.2, “Strobe Signals” on page 2-44, all signals must have the same
number of vias. As a result, each trace will have 1 via (near the BGA pad) because some of the
RSL signals must be routed on the bottom of the motherboard. Therefore, it is necessary to place a
dummy via on all signals that are routed on the top layer. Because the electrical characteristics of a
dummy via do not match the electrical characteristics of a real via exactly, additional compensation
must be performed on each signal that has a dummy via. Each signal with a dummy via must have
25 mils of additional trace length. That is: a real via = a dummy via + 25 mils of trace length.
This 25 mils of additional trace length must be added to each signal routed on the top layer after
length matching, as documented in Section 2.6.2.6, “Length Matching Methods” on page 2-21.

Figure 2-24. "Dummy" Via vs. Real "Via"
“DUMMY Via”

“REAL Via”
Trace

Trace

PCB

PCB

PCB

Via

PCB

Via
Trace

2.6.2.8

Length Matching & Via Compensation Example
Table 2-5 can be used to ensure that the RSL signals are the correct length.

Note:

2000 mils was chosen as an EXAMPLE Nominal RSL Length.

Intel®820 Chipset Design Guide

2-23

Layout/Routing Guidelines

Table 2-5. Line Matching and Via Compensation Example1,2,3,4,5,6,7,8,9,10

Signal

Ball
on
MCH

Nominal
RSL
Length
(mils)

Package
Dimension
(mils)

Motherboard Trace
Length when
Routed on Bottom
(i.e., Real Via)
Min
(mils)

Max
(mils)

Formula A

Motherboard Trace
Length when
Routed on Top
(i.e., Dummy Via)
Min
(mils)

Recommended
To Route On

Max
(mils)

Formula B

DQA0
DQA1
DQA2
DQA3

A13
C13
A14
C14

2000
2000
2000
2000

138.14
19.11
163.16
39.87

1851.86
1970.89
1826.84
1950.13

1871.86
1990.89
1846.84
1970.13

1876.86
1995.89
1851.84
1975.13

1896.86
2015.89
1871.84
1995.13

Top
Bottom
Top
Bottom

DQA4
DQA5
DQA6
DQA7
DQA8
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
RQ0
RQ1
RQ2
RQ3
RQ4
RQ5
RQ6
RQ7

B14
C15
A15
C16
A16
C7
B7
C6
A6
C5
A5
B5
A4
C4
A7
C8
A8
C9
B9
A9
A10
C10

2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000

97.54
62.67
186.11
95.70
230.20
39.56
95.83
63.49
153.69
97.33
191.43
152.47
237.71
138.29
179.49
27.12
162.21
5.80
71.70
133.88
122.20
0.00

1892.46
1927.33
1803.90
1894.30
1759.81
1950.44
1894.17
1926.51
1836.31
1892.67
1798.57
1837.53
1752.29
1851.71
1810.51
1962.88
1827.79
1984.20
1918.30
1856.12
1867.81
1990.00

1912.46
1947.33
1823.90
1914.30
1779.81
1970.44
1914.17
1946.51
1856.31
1912.67
1818.57
1857.53
1772.29
1871.71
1830.51
1982.88
1847.79
2004.20
1938.30
1876.12
1887.81
2010.00

1917.46
1952.33
1828.90
1919.30
1784.81
1975.44
1919.17
1951.51
1861.31
1917.67
1823.57
1862.53
1777.29
1876.71
1835.51
1987.88
1852.79
2009.20
1943.30
1881.12
1892.81
2015.00

1937.46
1972.33
1848.90
1939.30
1804.81
1995.44
1939.17
1971.51
1881.31
1937.67
1843.57
1882.53
1797.29
1896.71
1855.51
2007.88
1872.79
2029.20
1963.30
1901.12
1912.81
2035.00

Top
Bottom
Top
Bottom
Top
Bottom
Top
Bottom
Top
Bottom
Top
Bottom
Top
Bottom
Top
Bottom
Top
Bottom
Top
Bottom
Top
Bottom

CFM
CFM#
CTM
CTM#

A12
B12
B11
A11

2000
2000
2000
2000

132.37
64.63
56.06
126.34

FORMULA C

FORMULA D

1906.85
1976.02
1984.76
1913.01

1932.37
2001.54
2010.29
1938.53

Bottom
Bottom
Top
Top

NOTES:
1. Signals connecting to the "A" side of the RIMM connector (i.e., A1, A2, A3, etc.) should be routed on the top
(primary side) of the motherboard;
2. Signals connecting to the "B" side of the RIMM connector should be routed on bottom (solder side).
3. These trace lengths ONLY apply from MCH to the 1st RIMM. All signals must match EXACTLY from RIMM to
RIMM.
4. Clock trace lengths include 1.021 trace velocity factor.
5. Formula A min: Motherboard Trace = (Nominal RSL Length - Package Dimension) - 10 mil
6. Formula A max: Motherboard Trace = (Nominal RSL Length - Package Dimension) + 10 mil
7. Formula B min: Motherboard Trace = (Nominal RSL Length - Package Dimension) - 10 mil + 25 mil
8. Formula B max: Motherboard Trace = (Nominal RSL Length - Package Dimension) + 10 mil + 25 mil
9. Formula C: Motherboard Trace = (Nominal RSL Length - Package Dimension) * 1.021
10.Formula D: Motherboard Trace = (Nominal RSL Length - Package Dimension + 25 mil) * 1.021

2-24

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

2.6.3

Direct Rambus* Reference Voltage
The Direct Rambus* reference voltage (RAMREF) must be generated as shown in Figure 2-25.
RAMREF should be generated from a typical resistor divider using 2% tolerance resistors.
Additionally, RAMREF must be decoupled locally at EACH RIMM connector, at the resistor
divider and at the MCH. Finally, as shown in Figure 2-25, a 100 Ω series resistor is required near
the MCH. The RAMREF signal should be routed with a 10 mil wide trace.

Figure 2-25. RAMRef Generation Example Circuit
Vterm

MCH
100 Ω

RAMREFA

R1
160 Ω 2%

RAMREFB
R3
C4
0.1 uF

C10
0 .1 uF

R2
560 Ω 2%
R
I
M
M

2.6.4

C8
0.1 uF

C5
0.1 uF

R
I
M
M

High-speed CMOS Routing
• The high-speed CMOS signals (CMD & SCK) must be routed using 28 Ω traces. Using the
recommended stackup, these signals will be 18 mils wide.

• The high-speed CMOS signals must be length matched to the RSL signals within 1200 mils
(1.2in) due to a timing requirement between CMOS and RSL signals during NAP Exit and
PDN Exit.

• The high-speed CMOS signals require termination as shown in Figure 2-26 due to the buffer
strengths in the MCH.

• The resistors must be 91 Ω pullup and 39 Ω pulldown; they also must 2% or better for S3
mode reliability. The trace impedances remain 28 Ω.

Intel®820 Chipset Design Guide

2-25

Layout/Routing Guidelines

Figure 2-26. High-Speed CMOS Termination
RIMM_0

RIMM_1
Vterm

R1

91 Ω

R2

39 Ω

MCH

2.6.4.1

SIO Routing
The SIO signal must be routed from RIMM to RIMM as shown in Figure 2-17. The SIO signal
requires a 2.2 KΩ – 10 KΩ terminating resistor on the SOUT pin of the last RIMM. SIO is routed
with a standard 5 mil wide 60 Ω trace. The motherboard routing lengths for the SIO signal are the
same as RSL signals (see Figure 2-17).

Figure 2-27. SIO Routing Example

82820
MCH

SIN

B36

N

N

3

3

2

2

1

A36 SOUT
SIN

B
A

1

A36 SOUT

B36
2.2KΩ 10KΩ

0.4" - 0.45"

0" - 3.50"

2.6.4.2

Suspend-to-RAM Shunt Transistor
When an Intel® 820 chipset system enters or exits Suspend-to-RAM, power will be ramping to the
MCH (i.e., it will be powering-up or powering-down). When power is ramping, the state of the
MCH outputs is not guaranteed. Therefore, the MCH could drive the CMOS signals and issue
CMOS commands. One of the commands (the only one the RDRAMs would respond to) is the
powerdown exit command. To avoid the MCH inadvertently taking the RDRAMs out of powerdown due to the CMOS interface being driven during power ramp, the SCK (CMOS clock) signal
must be shunted to ground when the MCH is entering and exiting Suspend-to-RAM. This shunting
can be accomplished using the NPN transistor shown in circuit shown in Figure 2-28. The
transistor should have a Cobo of 4 pf or less (i.e., MMBT3904LT1).
In addition, to match the electrical characteristics on the SCK signal, the CMD signal needs a
dummy transistor. This transistor’s base should be tied to ground (i.e., always turned off).

2-26

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

To minimize impedance discontinuities, the traces for CMD and SCK must have a neckdown from
18 mil traces to 5 mil traces for 175 mils on either side of the SCK/CMD attach point as shown in
Figure 2-28.
Figure 2-28. RDRAM CMOS Shunt Transistor
18 mils
wide

18 mils
wide

5 mils
wide

MCH
R
I
M
M
S

VCC5SBY 175 mils 175 mils

2N3904

2N3904

PWROK

SCK

18 mils
wide

5 mils
wide

18 mils
wide
R
I
M
M
S

MCH
175
mils

175
mils

2N3904

CMD

Intel®820 Chipset Design Guide

2-27

Layout/Routing Guidelines

2.6.5

Direct Rambus* Clock Routing
Refer to Chapter 4, “Clocking” for Intel® 820 chipset platform Direct Rambus* clock routing
guidelines.

2.6.6

Direct Rambus* Design Checklist
Use the following checklist as a final check to ensure the motherboard incorporates solid design
practices. This list is only a reference. For correct operation, all of the design guidelines within this
document must be followed.

Table 2-6. Signal List
RSL Signals

DQA[8:0]
DQB[8:0]
RQ[7:0]

High-Speed
CMOS Signals

Serial CMOS Signal

Clocks
CTM

CMD
SCK

SIO

CTM#
CFM
CFM#

• Ground Isolation Well Grounded

•

2-28

— Via to ground every ½ inch around edge of isolation island
— Via to ground every ½ inch between RIMMs
— Via to ground every ½ inch between signals (from MCH to first RIMM)
— Via between every signal within 100mils of the MCH edge and the connector edge
— No unconnected ground floods
— All ground isolation at least 10 mils wide
— Ground isolation fills between serpentines
— Ground isolation not broken by C-TABs
— Ground isolation connects to the ground pins in the middle of the RIMM connectors
— Ground isolation vias connect on all 4 layers and should NOT have thermal reliefs
— Ground pins in RIMM connector connect on all 4 layers
Vterm Layout Yields Low Noise
— Solid Vterm island is on top layer – do not split this plane
— Ground island (for ground side of Vterm caps) is on top
— Termination Resistors connect DIRECTLY to the Vterm island on the top layer (without
vias)
— Decoupling Vterm is CRITICAL!
— Decoupling capacitors connect to top layer Vterm island and top layer ground island
directly (see layout example)
— Use AT LEAST 2 vias per decoupling capacitor in the top layer ground island
— Use 2 x 100 uF TANTALUM capacitors to decouple Vterm
(Aluminum/Electrolytic capacitors are too slow!)
— High-frequency decoupling capacitors MUST be spread-out across the termination island
so that all termination resistors are near high-frequency capacitors
— 100uF TANTALUM capacitors should be at each end of the Vterm island
— 100uF TANTALUM capacitors must be connected to Vterm island directly
— 100uF TANTALUM capacitors must have AT LEAST 2 vias/cap to ground

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

•

•

•

•

— Vterm island should be 50 – 75 mils wide
— Vterm island should not be broken
— If any RSL signals are routed out of the last RIMM (towards termination) on the bottom
side (even for a short distance), ensure Ground Reference Plane (on the third layer) is
continuous under the termination resistors/capacitors
— Ensure current path for power delivery to the MCH does not go through the Vterm island
CTM/CTM# Routed Properly
— CTM/CTM# are routed differentially from DRCG to last RIMM
— CTM/CTM# are ground isolated from DRCG to last RIMM
— CTM/CTM# are ground referenced from DRCG to last RIMM
— Vias are placed in ground isolation and ground reference every ½”
— When CTM/CTM# serpentine together, they MUST maintain EXACTLY 6 mils spacing
Clean DRCG Power Supply
— 3.3V DRCG power flood on the top layer. This should connect to each
— High frequency (0.1 uF) capacitors are near the DRCG power pins. One capacitor next to
each power pin.
— 10uF bulk tantalum capacitor near DRCG connected directly to the 3.3V DRCG power
flood on the top layer
— Ferrite bead isolating DRCG power flood from 3.3V main power also connecting directly
to the 3.3VDRCG power flood on the top layer
— Use 2 vias on the ground side of each
Good DRCG Output Network Layout
— Series resistors (39 Ω) should be VERY near CTM/CTM# pins
— Parallel resistors (51 Ω) should be very near series resistors
— CTM/CTM# should be 18mils wide from the CTM/CTM# pins to the resistors
— CTM/CTM# should be 14 on 6 routed differential as soon as possible after the resistor
network
— When not 14 on 6, the clocks should be 18 mils wide
— Ensure CTM/CTM# are ground referenced and the ground reference is connected to the
ground plane every ½” to 1”
— Ensure CTM/CTM# are ground isolated and the ground isolation is connected to the
ground plane every ½” to 1”
— Ensure 15 pf EMI capacitors to ground are removed (the pads are not necessary and
removing the pads provides more space for better placement of other components)
— Ensure the 4 pf EMI capacitor is implemented (but do not assemble the capacitor)
Good RSL Transmission Lines
— RSL traces are 18 mils wide
— When RSL traces neck down to exit MCH BGA, the minimum width is 15 mils and the
neckdown is no longer than 25 mils in length
— RSL traces do NOT neckdown when routing into the RIMM connector
— If tight serpentining is necessary, 10 mil ground isolation MUST be between serpentine
segments (i.e., an RSL signal CAN NOT serpentine so tightly that the signal is adjacent to
itself with no ground isolation between the serpentines).
— RSL traces do not cross power plane splits. RSL signals must also not be routed on next to
a power plane splits (e.g., the RSL signals on the 4th layer can not be routed directly below
the ground isolation split on the 3rd layer)
— Uniform ground isolation flood is exactly 6 mils from the RSL signals at all times

Intel®820 Chipset Design Guide

2-29

Layout/Routing Guidelines

•

•

— ALL RSL, CMD/SCK and CTM/CTM#/CFM/CFM# signals have CTABs on each RIMM
connector pin
— All RSL signals are routed adjacent to a ground reference plane. This includes all signals
from the last RIMM to the termination. If signals are routed on the bottom from the last
RIMM to the termination, the ground reference plane on the 3rd layer MUST extend under
these signals AND include the ground side of the Vterm decoupling capacitors.
— CTABs must not cross (or be on top of) power plane splits. They must be ENTIRELY
referenced to ground.
— At least 10 mils ground flood isolation required around ALL RSL signals (ground
isolation must be exactly 6 mils from RSL signals). Ground flood recommended for
isolation. This ground flood should be as close to the MCH (and the 1st RIMM) as
possible. If possible connect the flood to the ground balls/pins on the MCH/connector.
Clean VREF Routing
— Ensure 1 x 0.1 uF capacitor on VREF at each connector
— Use 10 mil wide trace (6 mils minimum)
— Do not route VREF near high-speed signals
RSL Routing
— All signals must be length matched within ±10 mils of the Nominal RSL Length (note:
use the table in the Intel® 820 chipset: 82820 Memory Controller Hub (MCH) Datasheet
to verify trace lengths). Ensure that signals with a dummy via are compensated correctly.
— ALL RSL signals must have 1 via near the MCH BGA pad. Signals routed on the
secondary side of the MB will have a “real via” while signals routed on the primary side
will have a “dummy via”. Additionally, all signals with a dummy via must have an
additional trace length of 25 mils.
— “B” side RIMM connector signals are routed on the secondary side of the motherboard.
“A” side RIMM connector signals are routed on the primary side of the motherboard.
— Signals must “alternate” layers as shown in the following table.
If Signal Routed from MCH to the 1st RIMM on:

Then Route Signal from 1st RIMM to Next
RIMM on:

Primary Side

Secondary Side

Secondary Side

Primary Side

• Clock Routing
— Clock signals must be routed as a differential pair. The traces must be 14 mils wide and 6
mils apart (with no ground isolation) when they are routed as a differential pair. For very
short sections under the MCH and under the 1st RIMM, it will not be possible to route as
a differential pair. In these sections, the clocks signals MUST neck up to 18 mils and be
ground isolated with at least 10 mils ground isolation.
— Clock signals must be length compensated (using the 1.021 length factor described in
Section 2.7.3, “2X/4X Timing Domain Routing Guidelines” on page 2-33). Ensure that
each clock pair is length matched within ±2 mils.
— When clock signals serpentine, they must serpentine together (to maintain differential
14:6 routing).
— 22 mils ground isolation required on each side of the differential pair.

2-30

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

2.7

AGP 2.0
For detailed AGP Interface functionality (protocols, rules and signaling mechanisms, etc.) refer to
the latest AGP Interface Specification revision 2.0, which can be obtained from http://
www.agpforum.org. This document focuses only on specific Intel® 820 chipset platform
recommendations.
The AGP Interface Specification revision 2.0 enhances the functionality of the original AGP
Interface Specification (revision 1.0) by allowing 4X data transfers (4 data samples per clock) and
1.5 volt operation. In addition to these major enhancements, additional performance enhancement
and clarifications, such as fast write capability, are included in the AGP Interface Specification,
Revision 2.0. The Intel® 820 chipset is the first Intel chipset that supports the enhanced features of
AGP 2.0.
The 4X operation of the AGP interface provides for “quad-pumping” of the AGP AD (Address/
Data) and SBA (Side-band Addressing) buses. That is, data is sampled four times during each
66 MHz AGP clock. This means that each data cycle is ¼ of a 15 ns (66 MHz) clock or 3.75 ns. It
is important to realize that 3.75 ns is the data cycle time, not the clock cycle time. During 2X
operation, data is sampled twice during a 66 MHz clock cycle; therefore, the data cycle time is
7.5 ns.
To allow for these high speed data transfers, the 2X mode of AGP operation uses source
synchronous data strobing (refer to Section 2.5, “Source Synchronous Strobing” on page 2-5).
During 4X operation, the AGP interface uses differential source synchronous strobing.
With data cycle times as small as 3.75 ns, and setup/hold times of 1 ns, propagation delay
mismatch is critical. In addition to reducing propagation delay mismatch, it is important to
minimize noise. Noise on the data lines will cause the settling time to be large. If the mismatch
between a data line and the associated strobe is too great, or there is noise on the interface,
incorrect data will be sampled.
The low-voltage operation on AGP (1.5V) requires even more noise immunity. For example,
during 1.5V operation, Vilmax is 570 mv. Without proper isolation, crosstalk could create signal
integrity issues.

Intel®820 Chipset Design Guide

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Layout/Routing Guidelines

2.7.1

AGP Interface Signal Groups
The signals on the AGP interface are broken into three groups: 1X timing domain signals, 2X/4X
timing domain signals and miscellaneous signals. Each group has different routing requirements.
In addition, within the 2X/4X timing domain signals, there are three sets of signals. All signals in
the 2X/4X timing domain must meet minimum and maximum trace length requirements as well as
trace width and spacing requirements. However, trace length matching requirements only need to
be met within each set of 2X/4X timing domain signals.

Signal groups

• 1X Timing Domain
—
—
—
—
—
—
—
—
—
—
—
—
—

CLK (3.3V)
RBF#
WBF#
ST[2:0]
PIPE#
REQ#
GNT#
PAR
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#

• 2X/4X Timing Domain
Set #1
— AD[15:0]
— C/BE[1:0]#
— AD_STB0
— AD_STB0# (used in 4X mode ONLY)
Set #2
— AD[31:16]
— C/BE[3:2]#
— AD_STB1
— AD_STB1# (used in 4X mode ONLY)
Set #3
— SBA[7:0]
— SB_STB
— SB_STB# (used in 4X mode ONLY)

• Miscellaneous, Async
—
—
—
—
—
—
—
—
—

2-32

USB+
USBOVRCNT#
PME#
TYPDET#
PERR#
SERR#
INTA#
INTB#

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

Table 2-7. AGP 2.0 Data/Strobe Associations
Associated
Strobe in 1X

Data

Associated
Strobe in 2X

Associated
Strobes in 4X

AD[15:0] and
C/BE[1:0]#

Strobes are not used in 1X mode. All data is
sampled on rising clock edges.

AD_STB0

AD_STB0, AD_STB0#

AD[31:16] and
C/BE[3:2]#

Strobes are not used in 1X mode. All data is
sampled on rising clock edges.

AD_STB1

AD_STB1, AD_STB1#

SBA[7:0]

Strobes are not used in 1X mode. All data is
sampled on rising clock edges.

SB_STB

SB_STB, SB_STB#

Throughout this section the term data refers to AD[31:0], C/BE[3:0]# and SBA[7:0]. The term
strobe refers to AD_STB[1:0], AD_STB#[1:0], SB_STB and SB_STB#. When the term data is
used, it is referring to one of the three sets of data signals. When the term strobe is used, it is
referring to one of the strobes as it relates to the data in its associated group.
The routing guidelines for each group of signals (1X timing domain signals, 2X/4X timing domain
signals and miscellaneous signals) will be addressed separately.

2.7.2

1X Timing Domain Routing Guidelines
• The AGP 1X timing domain signals (refer to Signal Groups previously shown) have a
maximum trace length of 7.5 inches. This maximum applies to ALL of the signals listed as 1X
timing domain signals in Signal Groups section.

• AGP 1X timing domain signals can be routed with 5 mil minimum trace separation.
• There are no trace length matching requirements for 1X timing domain signals.

2.7.3

2X/4X Timing Domain Routing Guidelines
These trace length guidelines apply to ALL of the signals listed as 2X/4X timing domain signals.
These signals should be routed using 5 mil (60 Ω) traces.
The maximum line length and length mismatch requirements are dependent on the routing rules
used on the motherboard. These routing rules were created to give design freedom by making
tradeoffs between signal coupling (trace spacing) and line lengths. The maximum length of the
AGP interface defines which set of routing guidelines must be used. Guidelines for short AGP
interfaces (e.g., < 6”) and the long AGP interfaces (e.g., > 6” and < 7.25”) are documented
separately. The maximum length allowed for the AGP interface is 7.25 inches.

Interfaces < 6”
If the AGP interface is less than 6 inches, a minimum 1:3 trace spacing is required for 2X/4X lines
(data and strobes). These 2X/4X signals must be matched their associated strobe within ±0.5
inches. These guidelines are for designs that require less than 6 inches between the AGP connector
and the MCH.
For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) are 5.3” long, the data
signals which are associated to those strobe signals (e.g., AD[15:0] and C/BE[2:0]#), can be 4.8” to
5.8” long. Another strobe set (e.g., SB_STB and SB_STB#) could be 4.2” long, and the data
signals which are associated to those strobe signals (e.g., SBA[7:0]), can be 3.7” to 4.7” long.

Intel®820 Chipset Design Guide

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Layout/Routing Guidelines

The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB and SB_STB#) act
as clocks on the source synchronous AGP interface; therefore, special care must be taken when
routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed
together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in
a strobe pair should be routed on 5 mil traces with at least 15 mils of space (1:3) between them.
This pair should be separated from the rest of the AGP signals (and all other signals) by at least
20 mils (1:4). The strobe pair must be length matched to less than ±0.1” (i.e., a strobe and its
compliment must be the same length within 0.1”).
Figure 2-29. AGP 2X/4X Routing Example for Interfaces < 6”
5 mil trace

2X/4X Signal
2X/4X Signal

15 mils
5 mil trace

2X/4X Signal
2X/4X Signal

20 mils
5 mil trace

AGP STB#
AGP STB#

15 mils
5 mil trace

AGP STB
AGP STB

20 mils
5 mil trace

2X/4X Signal
2X/4X Signal

15 mils
2X/4X Signal

2X/4X Signal

STB/STB# Length
Associated AGP 2X/4X Data Signal Length
0.5"
Min

0.5"
Max

Interfaces > 6” and < 7.25”
Longer lines have more crosstalk; therefore, to reduce skew, longer line lengths require a greater
amount of spacing between traces. For line lengths greater than 6 inches and less than 7.25 inches,
1:4 routing is required for all data lines and strobes. For these designs, the line length mismatch
must be less than ±0.125” within each signal group (between all data signals and the strobe
signals).
For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) are 6.5” long, the data
signals which are associated with those strobe signals (e.g., AD[15:0] and C/BE[2:0]#), can be
6.475” to 6.625” long. Another strobe set (e.g., SB_STB and SB_STB#) could be 6.2” long, and
the data signals that are associated with those strobe signals (e.g., SBA[7:0]), can be 6.075” to
6.325” long.
The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB and SB_STB#) act
as clocks on the source synchronous AGP interface; therefore, special care must be taken when
routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed
together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in
a strobe pair should be routed on 5 mil traces with at least 20 mils of space (1:4) between them.

2-34

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

This pair should be separated from the rest of the AGP signals (and all other signals) by at least
20 mils (1:4). The strobe pair must be length matched to less than ±0.1” (i.e., a strobe and its
compliment must be the same length within 0.1”).

All AGP Interfaces
The 2X/4X Timing Domain Signals can be routed with 5 mil spacing when breaking out of the
MCH. The routing must widen to the documented requirements within 0.3” of the MCH package.
When matching trace length for the AGP 4X interface, all traces should be matched from the ball
of the MCH to the pin on the AGP connector. It is not necessary to compensate for the length of the
AGP signals on the MCH package.
Reduce line length mismatch to insure added margin. In order to reduce trace to trace coupling
(cross talk), separate the traces as much as possible. All signals in a signal group should be routed
on the same layer. The trace length and trace spacing requirements must not be violated by any
signal. Trace length mismatch for all signals within a signal group should be as close to zero as
possible to provide timing margin.

2.7.4

AGP 2.0 Routing Summary

Table 2-8. AGP 2.0 Routing Summary1,2
Signal

Maximum
Length

Trace Spacing
(5 mil traces)

Length
Mismatch

Relative To

1X Timing Domain

7.5”

5 mils

No
Requirement

N/A

2X/4X Timing
Domain Set#1

7.25”

20 mils

±0.125”

AD_STB0 and
AD_STB0#

AD_STB0, AD_STB0#
must be the same
length

2X/4X Timing
Domain Set#2

7.25”

20 mils

±0.125”

AD_STB1 and
AD_STB1#

AD_STB1, AD_STB1#
must be the same
length

2X/4X Timing
Domain Set#3

7.25”

20 mils

±0.125”

SB_STB and
SB_STB#

SB_STB, SB_STB#
must be the same
length

2X/4X Timing
Domain Set#1

6”

15 mils1

±0.5”

AD_STB0 and
AD_STB0#

AD_STB0, AD_STB0#
must be the same
length

2X/4X Timing
Domain Set#2

6”

15 mils1

±0.5”

AD_STB1 and
AD_STB1#

AD_STB1, AD_STB1#
must be the same
length

2X/4X Timing
Domain Set#3

6”

15 mils1

±0.5”

SB_STB and
SB_STB#

Notes
None

SB_STB, SB_STB#
must be the same
length

NOTES:
1. Each strobe pair must be separated from other signals by at least 20 mils
2. These guidelines apply to board stackups with 10% impedance tolerance

Intel®820 Chipset Design Guide

2-35

Layout/Routing Guidelines

2.7.5

AGP Clock Routing
The maximum total AGP clock skew (between the MCH and the graphics component) is 1 ns for
all data transfer modes. This 1 ns includes skew and jitter which originates on the motherboard,
add-in card, and clock synthesizer. Clock skew must be evaluated not only at a single threshold
voltage, but at all points on the clock edge that fall in the switching range. The 1 ns skew budget is
divided such that the motherboard is allotted 0.9 ns of clock skew (the motherboard designer shall
determine how the 0.9 ns is allocated between the board and the synthesizer). For Intel® 820
chipset platform AGP clock routing guidelines, refer to Chapter 4, “Clocking”.

2.7.6

General AGP Routing Guidelines
The following routing guidelines are recommended for an optimal system design. The main focus
of these guidelines is to minimize signal integrity problems on the AGP interface of the 82820
MCH. The guidelines below are not intended to replace thorough system validation on Intel® 820
chipset based products.

Recommendations
Decoupling

• For VDDQ decoupling, a minimum of six (6) 0.01 uF capacitors are required and at least four
(4) must be within 70 mils of the outer row of balls on the MCH. (see Figure 2-30).

• Evenly distribute placement of decoupling capacitors among the AGP interface signal field.
• Use a low ESL ceramic capacitor (e.g., 0603 body type, X7R dielectric).
• In addition to the minimum decoupling capacitors, bypass capacitors should be placed at vias
that transition AGP signals from one reference signal plane to another. On a typical four layer
PCB design the signals transition from one side of the board to the other.

• One extra 0.01 uF capacitor is required per 10 vias. The capacitor should be placed as close to
the center of the via field as possible.

• Ensure that the AGP connector is well decoupled as described in the AGP Design Guide,
Revision 1.0 (Section 1.5.3.3).
Note:

2-36

To add the decoupling capacitors close as possible to the MCH and/or close to the vias, the trace
spacing may be reduced as the traces go around each capacitor. The narrowing of space between
traces should be minimal and for as short a distance as possible (1” maximum).

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

Figure 2-30. Top Signal Layer

Must add six 0.01 uF ceramic 603 Type Capacitors

Ground Reference
It is strongly recommended that, at a minimum, the following critical signals be referenced to
ground from the MCH to an AGP connector (or to an AGP video controller if implemented as a
“down” solution) utilizing a minimum number of vias on each net; AD_STB0, AD_STB0#,
AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_GTRY#, G_IRDY#, G_GNT# and ST[2:0].
In addition to the minimum signal set listed above, it is strongly recommended that half of all your
AGP signals be reference to ground depending on board layout. An ideal design would have the
complete AGP interface signal field referenced to ground.
The recommendations above are not specific to any particular PCB stackup, but are applied to all
Intel® Chipset designs.

2.7.7

VDDQ Generation and TYPEDET#
AGP specifies two separate power planes (VCC and VDDQ). VCC is the core power for the
graphics controller. VCC is always 3.3V. VDDQ is the interface voltage. In AGP 1.0
implementations VDDQ was also 3.3V. For the designer developing an AGP 1.0 motherboard,
there is no distinction between VCC and VDDQ as both are tied to the 3.3V power plane on the
motherboard.

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Layout/Routing Guidelines

AGP 2.0 requires that these power planes be separate. In conjunction with the 4X data rate, the
AGP 2.0 Interface Specification provides for low-voltage (1.5V) operation. The AGP 2.0
Specification implements a TYPEDET# (type detect) signal on the AGP connector that determines
the operating voltage of the AGP 2.0 interface (VDDQ). The motherboard must provide either
1.5V or 3.3V to the add-in card depending on the state of the TYPEDET# signal (refer to
Table 2-9. The 1.5V low-voltage operation applies ONLY to the AGP interface (VDDQ); VCC is
always 3.3V.
Note:

The motherboard provides 3.3V to the Vcc pins of the AGP connector. If the graphics controller
needs a lower voltage, then the add-in card must regulate the 3.3V VCC voltage to the controller’s
requirements. The graphics controller may ONLY power AGP I/O buffers with the VDDQ power
pins.
The TYPEDET# signal indicates whether the AGP 2.0 interface operates 1.5 volts or 3.3 volts. If
TYPEDET# is floating (no connect) on an AGP add-in card, the interface is 3.3 volts. If
TYPEDET# is shorted to ground, the interface is 1.5 volts.

Table 2-9. TYPDET#/VDDQ Relationship
TYPEDET# (on add-in card)

VDDQ (supplied by MB)

GND

1.5V

N/C

3.3V

As a result of this requirement, the motherboard must provide a flexible voltage regulator. This
regulator must supply the appropriate voltage to the VDDQ pins on the AGP connector. For
specific design recommendations, refer to the schematics in Appendix A, “Reference Design
Schematics: Uni-Processor” and Appendix B, “Reference Design Schematics: Dual-Processor”.
VDDQ generation and AGP VREF generation must be considered together. Before developing
VDDQ generation circuitry, refer to the AGP 2.0 Interface Specification.
Figure 2-31 demonstrates one way to design the VDDQ voltage regulator. This regulator is a linear
regulator with an external, low RDS-ON FET. The source of the FET is connected to 3.3V. This
regulator will convert 3.3V to 1.5V or pass 3.3V depending on the state of TYPEDET#. If a linear
regulator is used, it must draw power from 3.3V (not 5V) in order to control thermals (i.e., 5V
regulated down to 1.5V with a linear regulator will dissipate approximately 7W at 2A). Because it
must draw power from 3.3V and, in some situations, must simply pass that 3.3V to VDDQ (when a
3.3V add-in card is placed in the system), the regulator MUST use a low Rdson FET.
AGP 1.0 modified VDDQ3.3min to 3.1V. Using an ATX power supply; the 3.3Vmin is 3.168V.
Therefore, 68 mV of drop is allowed across the FET at 2A. This corresponds to a FET with an
Rdson of 34 mW.
How does the regulator switch? The feedback resistor divider is set to 1.5V. When a 1.5V card is
placed in the system, the transistor is off and the regulator regulates to 1.5V. When a 3.3V card is
placed in the system, the transistor is on, and the feedback is pulled to ground. When this happens,
the regulator drives to gate of the FET to nearly 12V. This turns the FET on and passes 3.3V - 2A *
RDS-ON to VDDQ.

2-38

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

Figure 2-31. AGP VDDQ Generation Example Circuit
+3.3V
O
+12V
O

VDDQ
O

C2
47 uF

U1
1

LT1575

SHDN

IPOS

VIN

INEG

5
6

2

5Ω

C3
220 uF

R2

R1
1 KΩ

3
C1
1 uF

4

GND

GATE

FB

COMP

7
8
C4
10 pF

C5
47 uF

R5
7.5 KΩ
R3
301 Ω

TYPEDET#

R4
1.21 KΩ

agp vddq generation vsd

2.7.8

VREF Generation for AGP 2.0 (2X and 4X)
VREF generation for AGP 2.0 will be different depending on the AGP card type used. The 3.3V
AGP cards generate VREF locally (i.e., they have a resistor divider on the card that divides VDDQ
down to VREF) as shown in Figure 2-32. To account for potential differences between VDDQ and
GND at the MCH and graphics controller, 1.5V cards use source generated VREF (i.e., the VREF
signal is generated at the graphics controller and sent to the MCH, and another VREF is generated at
the MCH and sent to the graphics controller). Refer to Figure 2-32.
Both the graphics controller and the MCH are required to generate VREF and distribute it through
the connector (1.5V add-in cards only). There are two pins defined on the AGP 2.0 universal
connector to allow this VREF passing. These pins are:

• VREFGC
• VREFCG

- Vref from the graphics controller to the chipset
- Vref from the chipset to the graphics controller

To preserve the common mode relationship between the VREF and data signals, it is important the
routing of the two Vref signals must be matched in length to the strobe lines within 0.5 inches on
the motherboard and within 0.25 inches on the add-in card.
The voltage divider networks consists of AC and DC elements as shown in the figure.
The VREF divider network should be placed as close to the AGP interface as is practical to get the
benefit of the common mode power supply effects. However, the trace spacing around the VREF
signals must be a minimum of 25 mils to reduce cross-talk and maintain signal integrity.

Intel®820 Chipset Design Guide

2-39

Layout/Routing Guidelines

During 3.3V AGP 2.0 operation, VREF must be 0.4VDDQ. However, during 1.5V AGP 2.0
operation, Vref must be 0.5VDDQ. This requires a flexible voltage divider for VREF. Various
methods of accomplishing this exist, and one such example is shown in Figure 2-32.
Figure 2-32. AGP 2.0 VREF Generation & Distribution
+12V
O

R7
1K

1.5V AGP
Card

Note: R7 is the same resistor seen in
AGP VDDQ Generation Example Circuit
Figure (R1)

R9
300
1%

TYPEDET#

VDDQ
500pF
C8

R11
200
1%

VrefGC

U6

VDDQ
REF

mosfet

VDDQ
AGP
Device

0.1uF
C10

REF

R6
1K

R5
82

R2
1K

R4
82

MCH

GND

500pF
C9

GND

Place C10 close to the MCH

VrefCG
The resistor dividers should be placed near the MCH. Both VrefGC and VrefCG
signals must be 5 mils wide and routed 25 mils from adjacent signals.

+12V
O

3.3V AGP
Card

R7
1K

Note: R7 is the same resistor seen in AGP
VDDQ Generation Example Circuit Figure
(R1)

TYPEDET#

R9
300
1%

VDDQ

R11
200
1%

VrefGC

500pF
C8

U6

VDDQ

R6
1K

R5
82

R2
1K

R4
82

VDDQ
AGP
Device

REF

REF
mosfet

GND

VrefCG

0.1uF
C10

MCH

GND

500pF
C9

Place C10 close to the MCH

The resistor dividers should be placed near the MCH. Both VrefGC and VrefCG
signals must be 5 mils wide and routed 25 mils from adjacent signals.

The flexible VREF divider shown in Figure 2-32 uses a FET switch to switch between the locally
generated VREF (for 3.3V add-in cards) and the source generated VREF (for 1.5V add-in cards).
Usage of the source generated VREF at the receiver is optional and is a product implementation
issue which is beyond the scope of this document.

2-40

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

2.7.9

Compensation
The MCH AGP interface supports resistive buffer compensation (RCOMP). Tie the GRCOMP pin
to a 40 Ω 2% (or 39 Ω 1%) pull-down resistor (to ground) via a 10 mil wide, very short (<0.5”)
trace.

2.7.10

AGP Pull-ups
AGP control signals require pull-up resistors to VDDQ on the motherboard to ensure they contain
stable values when no agent is actively driving the bus. The signals requiring pull-up resistors are:

• 1X Timing Domain Signals
— FRAME#
— TRDY#
— IRDY#
— DEVSEL#
— STOP#
— SERR#
— PERR#
— RBF#
— PIPE#
— REQ#
— WBF#
— GNT#
— ST[2:0]
It is critical that these signals are pulled up to VDDQ (NOT 3.3V).
The trace stub to the pull-up resistor on 1X timing domain signals should be kept to less than
0.5 inch to avoid signal reflections from the stub.
The strobe signals require pull-up/pull-downs on the motherboard to ensure they contain stable
values when no agent is driving the bus.
Note: INTA# and INTB# should be pulled to 3.3V – not VDDQ.

• 2X/4X Timing Domain Signals
— AD_STB[1:0]

(pull-up to VDDQ)

— SB_STB

(pull-up to VDDQ)

— AD_STB[1:0]#

(pull-down to ground)

— SB_STB#
(pull-down to ground)
The trace stub to the pull-up/pull-down resistor on 2X/4X timing domain signals should be
kept to less than 0.1 inch to avoid signal reflections from the stub.
The pull-up/pull-down resistor value requirements are shown in the table below:
Rmin

Rmax

4 KΩ

16 KΩ

The recommended AGP pull-up/pull-down resistor value is 8.2 KΩ.

Intel®820 Chipset Design Guide

2-41

Layout/Routing Guidelines

2.7.10.1

AGP Signal Voltage Tolerance List
The following signals on the AGP interface are 3.3V tolerant during 1.5V operation:

•
•
•
•
•
•
•

PME#
INTA#
INTB#
GPERR#
GSERR#
CLK
RST

The following signals on the AGP interface are 5V tolerant (refer to the USB specification):

• USB+
• USB• OVRCNT#
The following signal is a special AGP signal. It is either Grounded or No Connected on an AGP
card.

• TYPEDET#
Note:

2.7.11

All other signals on the AGP interface are in the VDDQ group. They are not 3.3V tolerant
during 1.5V AGP operation.

Motherboard / Add-in Card Interoperability
Currently, there are three AGP connectors:

• 3.3V AGP connector
• 1.5V AGP connector
• Universal AGP connector.
To maximize add-in flexibility, implementing the universal connector in Intel® 820 chipset based
system is strongly recommended. All add-in cards are either 3.3V or 1.5V cards. Due to timings,
4X transfers at 3.3V are not allowed.
Table 2-10. Connector/Add-in Card Interoperability
1.5V Connector

3.3V Connector

Universal Connector

1.5V Card

Yes

No

Yes

3.3V Card

No

Yes

Yes

1X

2X

4X

1.5V VDDQ

Yes

Yes

Yes

3.3V VDDQ

Yes

Yes

No

Table 2-11. Voltage/Data Rate Interoperability

2-42

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

2.8

Hub Interface
The MCH and ICH ball assignments have been optimized to simplify hub interface routing. It is
recommended that the hub interface signals be routed directly from the MCH to the ICH on the top
signal layer (they do not need to be run through vias) (refer to Figure 2-4).
The hub interface is broken into two signal groups: data signals and strobe signals. These groups
are:

• Data Signals
— HL[10:0]

• Strobe Signals
— HL_STB
— HL_STB#
Note:

HL_STB/HL_STB# is a differential strobe pair.
There are no pull-ups or pull-downs required on the hub interface.
Each signal must be routed such that it meets the guidelines documented for the signal group to
which it belongs.

Figure 2-33. Hub Interface Signal Routing Example
1.8V
O

10 KΩ

HL_STB
HL11

HL_STB#

ICH

MCH

HL[10:0]

GCLK

CLK66

Clocks

Intel®820 Chipset Design Guide

2-43

Layout/Routing Guidelines

2.8.1

Data Signals
The Hub interface data signals (HL[10:0]) should be routed 5 on 20. These signals can be routed 5
on 15 for navigation around components or mounting holes. In order to break-out of the MCH
uBGA and the ICH uBGA, the hub interface data signals can be routed 5 on 5. The signals must be
separated to 5 on 20 within 300 mil of the uBGA package.
The maximum trace length for the hub interface data signals is 7”. These signals must each be
matched within ±0.1” of the HL_STB and HL_STB# signals.

2.8.2

Strobe Signals
Due to their differential nature, the hub interface strobe signals should be 5 mils wide and routed 20
mils apart. This strobe pair should be a minimum of 20 mils from any adjacent signals. The
maximum length for the strobe signals is 7” and the two strobes must be the same length.
Additionally, the trace length for each data signal must be matched to the trace length of the strobes
with ±0.1”.

2.8.3

HREF Generation/Distribution
HREF is the hub interface reference voltage. It is 0.5 * 1.8V = 0.9V ±2%. It can be generated using
a single HREF divider or locally generated dividers (as shown in Figure 2-34 and Figure 2-35).
The resistors should be equal in value and rated at 1% tolerance (to maintain 2% tolerance on
0.9V). The value of these resistors must be chosen to ensure that the reference voltage tolerance is
maintained over the entire input leakage specification. The recommended range for the resistor
value is from minimum 100 ohm to maximum 1K ohm (300 ohm shown in example).
The single HREF divider should not be located more than 4" away from either MCH or ICH. If the
single HREF divider is located more than 4" away, then the locally generated hub interface
reference dividers should be used instead.
The reference voltage generated by a single HREF divider should be bypassed to ground at each
component with a 0.01 uF capacitor located close to the component HREF pin. If the reference
voltage is generated locally, the bypass capacitor needs to be close to the component HREF pin.

Figure 2-34. Single Hub Interface Reference Divider Circuit
1.8V

300Ω
HUBREF

MCH

HUBREF

0.01uF

0.01uF

300Ω

ICH

0.1uF
HubRef1.vsd

2-44

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

Figure 2-35. Locally generated Hub Interface Reference Dividers
1.8V

1.8V

300Ω

300Ω

HUBREF

HUBREF

ICH

MCH
300Ω
300Ω
0.1uF

0.1uF

HubRef2.vsd

2.8.4

Compensation
There are two options for the ICH hub interface compensation (HLCOMP). HLCOMP is used by
the ICH to adjust buffer characteristics to specific board characteristics. Refer to the ICH Datasheet
for details on compensation. It can be used as either Impedance Compensation (ZCOMP) or
Resistive Compensation (RCOMP). The guidelines are below:

• RCOMP: Tie the COMP pin to a 40 Ω 2% (or 39 Ω 1%) pull-up resistor (to 1.8V) via a 10 mil
wide, very short (<0.5”) trace.

• ZCOMP: The COMP pin must be tied to a 10 mil trace that is AT LEAST 18” long. This trace
must be unterminated and care should be taken when routing the signal to avoid crosstalk
(15–20 mil separation between this signal and any adjacent signals is recommended). This
signal may not cross power plane splits.
The MCH also has a hub interface compensation pin. This signal (HLCOMP) can be routed using
either the RCOMP method or ZCOMP method described for the ICH.

Intel®820 Chipset Design Guide

2-45

Layout/Routing Guidelines

2.9

System Bus Design

2.9.1

100/133 MHz System Bus
First, determine the approximate location of the processor and the chip set on the base board. An
example topology is shown in Figure 2-36. This example “star” topology is valid for 133 MHz and
100 MHz 2-way processor/Intel® 820 chipset designs. The 82820 MCH should be placed
electrically in the center of the bus. The SC242 connectors should be placed on either end of the
bus to allow the processors to terminate each end.
Table 2-12 below provides segment descriptions and length recommendations for the investigated
topology shown in Figure 2-36. Segment lengths are defined at the pins of the devices or
components. For 2-way processor / Intel® 820 chipset designs, a termination card must be placed
in the unused slot when only one processor is populated. This is necessary to ensure signal integrity
requirements are met.

Figure 2-36. Intel® Pentium® III Processor Dual Processor Configuration

Processor

Processor

L1

L2
L3
L(1,2,3): Z 0 = 60Ω ± 15%

MCH

Table 2-12. Segment Descriptions and Lengths for Figure 2-36
Segment

Description

Min length
(inches)

Max length
(inches)

L1

SC242 connector to Centerpoint

1.5

3.0

L2

SC242 connector to Centerpoint

1.5

3.0

L3
L1+L3 or L2+L3
L1 + L2

Chip set breakout stub

0.0

1.5

SC242 distance from MCH

2.0

4.5

SC242 spacing

5.5

Figure 2-37 shows the topology and trace lengths required for single processor designs.
Figure 2-37. Intel® Pentium® III Processor Uni-Processor Configuration

MCH

Processor
L1 Min = 1.75"
L1 Max = 4.5"

L(1): Z 0 = 60Ω ± 15%

2-46

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

2.9.2

System Bus Ground Plane Reference
All system bus signals must be referenced to GND to provide optimal current return path. The
ground reference must be continuous from the MCH to the SC242 connector. This may require a
GND reference island on the plane layers closest to the signals. Any split in the ground island will
provide a sub-optimal return path. In a 4 layer board, this will require the VCCID island to be on an
outer signal layer. Figure 2-38 shows a four layer motherboard power plane with ground reference
for system bus signals.

Figure 2-38. Ground Plane Reference (Four Layer Motherboard)
Required
SC242

GND Plane

MCH
4laym pwr plane vsd

2.10

S.E.C.C. 2 Grounding Retention Mechanism (GRM)
Intel is enabling a new S.E.P.P. (Single Edge Processor Package) style retention mechanism which
will provide a grounding path for the heatsink on processors in the S.E.C.C. 2 package. This
solution is referred to as the S.E.C.C.2 (Single Edge Contact Cartidge 2) Grounding Retention
Mechanism (GRM). OEMs who choose to utilize this new solution will need to add grounding
pads on the primary side of the motherboard which will interface with the enabled GRM. If the
motherboard or heat sink do not have the proper interfaces, the GRM may not be utilized to its full
ability and damage could occur to the motherboard.
The most notable interface requirement to accommodate the GRM is the addition of grounding
pads around two of the Retention Mechanism (RM) mounting holes within the existing RM keepout zone on the motherboard. The other interface is a contact area on the heat sink flanges. The
interface size and locations for the motherboard are discussed in detail further in this section.
The reference design GRM is asymmetric, and requires 0.159” mounting holes. To minimize the
impact to trace routing, only two ground pads are required. This makes it necessary to key the
GRM to prevent the ground clips from being installed on the soldermask instead of the grounding
pads. This keying is accomplished by making the GRM asymmetric. The requirement for the
0.159” mounting holes is for the supported plastic fastener attachment mechanism.

Intel®820 Chipset Design Guide

2-47

Layout/Routing Guidelines

Motherboard Interfaces
Figure 2-39 shows the Hole Locations and Keepout Zones For Support Components (from the
motherboard surface to 0.100” above the motherboard surface.).
Figure 2-39. Hole Locations and Keepout Zones For Support Components1,2
Primary Side

1.270

4x Thru ∅ 0.159

0.232

0.806

+0.002
-0.001

1.038
0.175

0.231
0.375
4x ∅ 0.300 Keepout

4.706
4.881
5.256

Secondary Side
1. All dimensions are in inches and all toler
ances ±0.04, unless
otherwise specified.
2. Dash lines represent control line for connector key features when
placed on planar.
3. Retention solution not to exceed height of 2.75" off of primary
side of planar and 0.150" off of secondary side of planar.
4. Retention mechanism must stay within cross-hat
ch area.

NOTES:
1. The dashed lines represent the centerlines for the connector keying features.
2. Drawing not to scale

Figure 2-40 shows the dimensions of the grounding pad needed to ground the heat sink.
Figure 2-40. Grounding Pad Dimensions for the SECC2 GRM
Ground Pad Areas,
See Detail A

0.364
0.182

Heat Sink Area

0.232
0.464
Notes:
1. All dimensions are in inches and all
tolerances are ±0.004, unless otherwise
specified.
2. Retention mechanisim must stay within
Cross-Hatch area.
3. Entire specified plating area must be plated
and grounded with a minimum of eight VIAS.
Detail A

NOTE: Drawing not to scale.

It is not recommended to use the GRM without the minimum size ground pads in the correct
locations. If the GRM is used without the correct pads, then there is a high risk that the metal clip
that grounds to the motherboard will be touching the solder mask on the top layer of the board, and
possibly short out traces immediately beneath the solder mask, resulting in board failure. The
required thickness of the pad is less than 0.001” (using 1/2 oz. copper).

2-48

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

2.11

Processor CMOS Pullup Values
Table 2-13 contains the pullup values for the Intel® Pentium® III processor with the Intel® 820
chipset. This table supports both single and dual processor configurations.

Table 2-13. Processor and 82820 MCH Connection Checklist1,2
CPU Pin

UP Pin Connection (CPU0)

DP Pin Connection (CPU1)

AGTL+ Signals
A[35:3]# 1

Connect A[31:3]# to MCH. Leave A[35:32]#
as N/C (not supported by chipset).

Connect A[31:3]# to 2nd processor

ADS# 1

Connect to MCH

Connect to 2nd processor

AERR#

Leave as N/C (not supported by chipset).

Leave as N/C

AP[1:0]#

Leave as N/C (not supported by chipset).

Leave as N/C

BERR#

Leave as N/C (not supported by chipset).

Leave as N/C

BINIT#

Leave as N/C (not supported by chipset).

Leave as N/C

BNR# 1

Connect to MCH

Connect to 2nd processor

BP[3:2]#

Leave as N/C

Leave as N/C

BPM[1:0]

Leave as N/C

Leave as N/C

Connect to MCH

Connect to 2nd processor

BREQ0# (BR0#)

10 Ω pull down to GND

See and

BREQ1# (BR1#)

Leave as N/C

See and

Connect to MCH

Connect to 2nd processor

DBSY# 1

Connect to MCH

Connect to 2nd processor

DEFER# 1

Connect to MCH

Connect to 2nd processor

DEP[7:0]#

Leave as N/C (not supported by chipset).

Leave as N/C

Connect to MCH

Connect to 2nd processor

Connect to MCH

Connect to 2nd processor

Connect to MCH

Connect to 2nd processor

Connect to MCH

Connect to 2nd processor

REQ[4:0]# 1

Connect to MCH

Connect to 2nd processor

RESET# 1

Connect to MCH, 240 Ω series resistor to ITP Connect to 2nd processor

RP#

Leave as N/C (not supported by chipset).

Leave as N/C

Connect to MCH

Connect to 2nd processor

Leave as N/C (not supported by chipset).

Leave as N/C

Connect to MCH

Connect to 2nd processor

BPRI#

1

D[63:0]#

DRDY#

1

1

HIT# 1
HITM# 1
LOCK#

1

RS[2:0]#

1

RSP#
TRDY#

1

Intel®820 Chipset Design Guide

2-49

Layout/Routing Guidelines

Table 2-13. Processor and 82820 MCH Connection Checklist1,2 (Continued)
CPU Pin

UP Pin Connection (CPU0)

DP Pin Connection (CPU1)

CMOS Signals
A20M#

150 Ω pull up to Vcc2.5, connect to ICH

Connect to 2nd processor

FERR#

150 Ω pull up to Vcc2.5, connect to ICH

Connect to 2nd processor

FLUSH#

150 Ω pull up to Vcc2.5 (not used by chipset).

Connect to 2nd processor

IERR#

150 Ω pull up to Vcc2.5 if tied to custom logic
or leave as N/C (not used by chipset).

Connect to 2nd processor

IGNNE#

150 Ω pull up to Vcc2.5, connect to ICH

Connect to 2nd processor

INIT#

150 Ω pull up to Vcc2.5, connect to ICH and
FWH Flash BIOS

Connect to 2nd processor

LINT0/INTR

150 Ω pull up to Vcc2.5, connect to ICH

Connect to 2nd processor

LINT1/NMI

150 Ω pull up to Vcc2.5, connect to ICH

Connect to 2nd processor

PICD[1:0]

150 Ω pull up to Vcc2.5, connect to ICH

Two 300–330 Ω pull ups to Vcc2.5 located
at each end of trace. Connect to 2nd
processor

PREQ#

~200–330 Ω pull up to Vcc2.5, connect to ITP
pin 16

~200–330 Ω pull up to Vcc2.5, connect to
ITP pin 20

PWRGOOD

150–330 Ω pull up to 2.5V, output from the
PWRGOOD logic

Connect to 2nd processor

SLP#

150 Ω pull up to Vcc2.5, connect to ICH

SMI#

150 Ω pull up to Vcc2.5, connect to ICH

STPCLK#

150 Ω pull up to Vcc2.5, connect to ICH

THERMTRIP#

150 Ω pull up to Vcc2.5 and connect to power
off logic or ASIC, or leave as N/C

Connect to 2nd processor. Could tie
separately to a monitoring ASIC.

PRDY#

150 Ω pull up to VTT, 240 Ω series resistor to
ITP pin 18

150 Ω pull up to VTT, 240 Ω series resistor
to ITP pin 22

TCK

1k Ω pull up to Vcc2.5, 47 Ω series resistor to
ITP pin 5

Each processor should receive a
separately buffered copy of TCK from the
ITP. Tank circuit is optional for signal
integrity. See

TDO

150 Ω pull up to Vcc2.5 and connect to ITP
10

TDO of CPU1 is connected to the ITP TDO
pin 10. Pull up both sets of TDI/TDO nets
as described.

TDI

~150–330 Ω pull up to Vcc2.5 and connect to
ITP pin 8

TDI of CPU0 is connected to the ITP pin 8,
TDI of CPU1 is connected to TDO of
CPU0. Pull up both sets of TDI/TDO nets
as described.

TAP Signals

TMS

TRST#

2-50

1 KΩ pull up to Vcc2.5, 47 Ω series resistor
to ITP pin 7

~680 Ω pull down, connect to ITP pin 12

Each processor should receive a
separately buffered copy of TMS from the
ITP.
Tank circuit is optional for signal integrity.
See
Connect to 2nd processor

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

Table 2-13. Processor and 82820 MCH Connection Checklist1,2 (Continued)
CPU Pin

UP Pin Connection (CPU0)

DP Pin Connection (CPU1)

BCLK

Connect to CK133. 22 – 33 Ω series resistor
(Though OEM needs to simulate based on
driver characteristics). To reduce pin-to-pin
skew, tie host clock outputs together at the
clock driver then route to the MCH and
processor.

Use separate BCLK from TAP and CPU0,
or use ganged clock. Terminate as
described.

PICCLK

Connect to CK133. 22 – 33 Ω series resistor
(Though OEM needs to simulate based on
driver characteristics)

Use separate PICCLK from CPU0.
Terminate as described.

BSEL0

100/133 MHz support: 220 Ω pull up to 3.3V,
connected to PWRGOOD logic such that a
logic low on BSEL0 negates PWRGOOD

Connect to 2nd processor

BSEL1

220 Ω pull up to 3.3V, connect to CK133
SEL133/100# pin. Connect to MCH HL10 pin
via 8.2 KΩ series resistor.

Connect to 2nd processor

EMI[5:1]

Tie to GND. Zero ohm resistors are an option
instead of direct connection to GND.

Implement in same manner as CPU0.

SLOTOCC#

Tie to GND, leave it N/C, or could be
connected to powergood logic to gate system
from powering on if no processor is present.
If used, 1 KΩ – 10 KΩ pull up to any voltage.

Implement in same manner as CPU0.

Clock Signals

Other Signals

1 K –100 KΩ pull up to Vcc2.5
TESTHI

If a legacy design pulls this up to VCCCORE,
use a 1 KΩ – 10 KΩ pull up

Implement in same manner as CPU0.

Connect to on-board VR or VRM. For onboard VR, 10 KΩ pull up to power-solution
compatible voltage required (usually pulled
up to input voltage of the VR). Some of these
solutions have internal pull-ups. Optional
override (jumpers, ASIC, etc.) could be used.
May also connect to system monitoring
device.

Implement in same manner as CPU0.
CPU0 and CPU1 should have different
VR/VRMs.

VCCCORE

Connect to core voltage regulator. Provide
high & low frequency decoupling.

Implement in same manner as CPU0.

VTT

Connect to 1.5V regulator. Provide high and
low frequency decoupling.

Implement in same manner as CPU0.

The following pins must be left as noconnects: A16, A47, A88, A113, A116, B12,
B20, B76, and B112.

Implement in same manner as CPU0.

VID[4:0]

Power

No Connects
Reserved

NOTES:
1. For single processor designs, the AGTL+ bus can be dual-ended or single-ended termination based on
simulation results. Single-ended termination is provided by the processor.
2. This checklist supports Intel® Pentium® II processors at all current speeds, Intel® Pentium® III processors to
a FMB guideline of 19.3A, and future Intel® Pentium® III processors to the current FMB guideline of 18.4A.

Intel®820 Chipset Design Guide

2-51

Layout/Routing Guidelines

Figure 2-41. TCK/TMS Implementation Example for DP Designs
Vcc2.5
RI

1 KΩ

SC242
Connector A

non-inverting buffer

ITP Port
TCK
or
TMS

100 nH

motherboard trace
56 pF
SC242
Connector B

non-inverting buffer

100 nH

motherboard trace
56 pF

itp vsd

Table 2-14. Bus Request Connection Scheme for DP Intel® 820 Chipset Designs

2.12

Bus Signal

Agent 0 Pins

Agent 1 Pins

BREQ0#

BR0#

BR1#

BREQ1#

BR1#

BR0#

Additional Host Bus Guidelines
BREQ Pins
UP Systems: For uni-processor systems, the BREQ0 pin should be pulled down to ground through
a 10 Ω resistor. The BREQ1 pin should be left as a no-connect.

Figure 2-42. Single Processor BREQ Strapping Requirements

CPU #1
BREQ0#

BREQ1#
No Connect

2-52

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

DP Systems: For dual processor systems, BREQ0# (to one of the processors) needs to be driven
for arbitration ID strapping. Refer to Figure 2-43 for an example of the BREQ connections in a DP
system. It is a requirement that the on-board logic tri-state BREQ0# after the arbitration ID
strapping is complete. Additionally, BREQ0# and BREQ1# are high-speed AGTL+ signals and the
loading characteristics of the on-board logic must be considered even when the logic is tri-stated.
Figure 2-43. Dual-Processor BREQ Strapping Requirements

CPU #1
BREQ0#

CPU #2

BREQ1#

BREQ0# BREQ1#

on-board logic

Figure 2-44. BREQ0# Circuitry for DP Systems
5V
5V

5V

R2
Ω
2.7 KΩ

BREQ0#
4

CPURST#

R2
4.7 KΩ
Ω

4

2

D /PRE Q

5

2

D /PRE Q

5

3

CLK
/Q
/CLR

6

3

CLK
/Q
/CLR

6

4.7 KΩ
Ω
2N3904

2N3904

1

74F74

1

74F74

CPUCLK

This circuit holds BREQ0 low for two clocks after the deassertion of reset. The 2N3904 connected
to BREQ0 should be connected to the BREQ0 AGTL trace with a very short stub. Additionally, the
series current limiting resistor on CPURESET should be attached to the CPURESET trace with a
very short stub.

External Circuit Recommendation for HA7 Strapping for IOQ Depth of 1
For debug purpose, the external logic to set the IOQ depth of 1 on the front side bus may be
needed. Do not add this circuit for production since overall system performance will be degraded.
The external logic for HA7# strapping is very similar to the BREQ0 strapping that is described in
the previous section.
The timing requirement of HA7# strapping is also similar to BREQ0 strapping for the hold time
after the deassertion of RESET# (RSTIN# signal from MCH). The value of the strapping needs to
be held for a minimum of 2 host clocks after the deassertion of RSTIN#. Refer to the latest version
of the processor datasheets for complete description on the timing requirement.

Intel®820 Chipset Design Guide

2-53

Layout/Routing Guidelines

The recommendation for the layout and the schematic example are shown below. Layout
guidelines are:

• Place the transistor and stub as close as possible to MCH (or place the transistor pad on top of
trace)

• The max stub for transistor is less than 0.25”
• The recommended loading of transistor is less than 5 pf.
• For dual processor design, the stub is recommended to place on the stub of the MCH and as
close as possible to the MCH, and is less than 0.25”
Note:

This circuit is only recommended for the debug situation that requires to set the IOQ depth equal to
1. For the production, do not add this circuit, since the overall system performance will be
degraded. Also, Intel does not guarantee the above layout recommendation will work under the
worst case condition.

Figure 2-45. HA7# Strapping Option Example Circuit (For Debug Purposes Only)
5V
5V

5V

R2
Ω
2.7 KΩ
4

CPURST#

R2
Ω
4.7 KΩ

2

D

/PRE

4
Q

5

2

5
D /PRE Q

2N3904
3

CLK
6
/Q
/CLR
1

74F74

3

CLK
/Q
/CLR
1

HA7
Ω
4.7 KΩ

jumper

6

2N3904

74F74
R2
Ω
4.7 KΩ

CPUCLK

In-Target Probe (ITP)
It is important that all of the processor electrical characteristic requirements are met. It is
recommended that prototype boards implement the ITP connector.

Logic Analyzer Interface (LAI)
Note that 1 KΩ resistors that are used to pull-up several processor signals in the schematics in
Appendix A, “Reference Design Schematics: Uni-Processor” and Appendix B, “Reference Design
Schematics: Dual-Processor” (e.g., HINIT#, IGNNE#, SMI#, etc.) preclude use of the Intel
Pentium III processor LAI. The Intel Pentium III processor LAI will function correctly with these
1 KΩ pull-up resistors.

2-54

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

Minimizing Crosstalk on the AGTL+ Interface
The following general rules will minimize the impact of crosstalk in the high speed AGTL+ bus
design:

• Maximize the space between traces. Maintain a minimum of 0.010” between traces wherever
possible. It may be necessary to use tighter spacings when routing between component pins.

• Avoid parallelism between signals on adjacent layers.
• Since AGTL+ is a low signal swing technology, it is important to isolate AGTL+ signals from
other signals by at least 0.025”. This will avoid coupling from signals that have larger voltage
swings, such as 5V PCI.

• Select a board stack-up that minimizes the coupling between adjacent signals.
• Route AGTL+ address, data and control signals in separate groups to minimize crosstalk
between groups. The Pentium III processor uses a split transaction bus. In a given clock cycle,
the address lines and corresponding control lines could be driven by a different agent than the
data lines and their corresponding control lines.

Additional Considerations

• Distribute VTT with a wide trace. A 0.050” minimum trace is recommended to minimize DC

losses. Route the VTT trace to all components on the host bus. Be sure to include decoupling
capacitors. Guidelines for VTT distribution and decoupling are contained in “Slot 1 Processor
Power Distribution Guidelines.”

• Place resistor divider pairs for VREF generation at the MCH component. No VREF generation

is needed at the processor(s). VREF is generated locally on the processor. Be sure to include
decoupling capacitors. Guidelines for VREF distribution and decoupling are contained in “Slot
1 Processor Power Distribution Guidelines.”

• Special Case AGTL+ signals for simulation: There are six AGTL+ signals that can be driven
by more than one agent simultaneously. These signals may require extra attention during the
layout and validation portions of the design. When a signal is asserted (driven low) by two
agents on the same clock edge, the two falling wave fronts will meet at some point on the bus.
This can create a large undershoot, followed by ringback which may violate the ringback
specifications. This “wired-OR” situation should be simulated for the following signals:
AERR#, BERR#, BINIT#, BNR#, HIT#, and HITM#.

Intel®820 Chipset Design Guide

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Layout/Routing Guidelines

2.13

Ultra ATA/66
This section contains guidelines for connecting and routing the ICH IDE interface. The ICH has
two independent IDE channels. This section provides guidelines for IDE connector cabling and
motherboard design, including component and resistor placement, and signal termination for both
IDE channels. The ICH has integrated the 33 Ω series resistors that have been typically required on
the IDE data signals running to the two ATA connectors.
The IDE interface can be routed with 5 mil traces on 5 mil spaces, and must be less than 8 inches
long (from ICH to IDE connector). Additionally, the shortest IDE signal (on a given IDE channel)
must be less than 0.5” shorter than the longest IDE signal (on that channel).

Cable

• Length of cable: Each IDE cable must be equal to or less than 18 inches.
• Capacitance: Less than 30 pF.
• Placement: A maximum of 6 inches between drive connectors on the cable. If a single drive is

•
•
•

2.13.1

placed on the cable it should be placed at the end of the cable. If a second drive is placed on the
same cable it should be placed on the next closest connector to the end of the cable (6” away
from the end of the cable).
Grounding: Provide a direct low impedance chassis path between the motherboard ground
and hard disk drives.
ICH Placement: The ICH must be placed equal to or less than 8 inches from the ATA
connector(s).
PC99 requirement: Support Cable Select for master-slave configuration is a system design
requirement for Microsoft* PC99. CSEL signal needs to be pulled down at the host side by
using a 470 Ω pull-down resistor for each ATA connector.

Ultra ATA/66 Detection
The Intel® 820 chipset supports many Ultra DMA modes including ATA/66. The Intel® 820
chipset needs to determine the installed IDE device mode and the type of cable to configure its own
hardware and software to support it.
A new IDE cable is required for Ultra ATA/66. This cable is an 80 conductor cable; however the 40
pin connectors do not change. The wires in the cable alternate: ground, signal, ground, signal,
ground, signal, ground… All the ground wires are tied together on the cable (and they are tied to
the ground on the motherboard through the ground pins in the 40 pin connector). This cable
conforms to the Small Form Factor Specification SFF-8049. This specification can be obtained
from the Small Form Factor Committee.
To determine if ATA/66 mode can be enabled, the Intel® 820 chipset requires the system BIOS to
attempt to determine the cable type used in the system. The BIOS does this in one of two ways:

• Host Side Detection
• Device Side Detection
If the BIOS detects an 80-conductor cable, it may use any Ultra DMA mode up to the highest
transfer mode supported by both the Intel® 820 chipset and the IDE device. Otherwise, the BIOS
can only enable modes that do not require an 80-conductor cable (e.g., Ultra ATA/33 Mode).
After determining the Ultra DMA mode to be used, the BIOS will configure the Intel® 820 chipset
hardware and software to match the selected mode.

2-56

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Layout/Routing Guidelines

2.13.2

Ultra ATA/66 Cable Detection
The Intel® 820 chipset can use two methods to detect the cable type. Each mode requires a
different motherboard layout.

Host-Side Detection (BIOS Detects Cable Type Using GPIOs)
Host side detection requires the use of two GPI pins (1 per IDE controller). The proper way to
connect the PDIAG/CBLID signal of the IDE connector to the host is shown in Figure 2-46. All
IDE devices have a 10 KΩ pull-up resistor to 5 volts. The GPI and GPIO pins on the ICH and GPI
pins on the FWH Flash BIOS are not 5 volt tolerant. This requires a resistor divider so that 5 volts
will not be driven to the ICH or FWH Flash BIOS pins. The proper value of the series resistor is
15 KΩ (as shown in Figure 2-46). This creates a 10 KΩ / 15 KΩ resistor divider and produces
approximately 3 volts for a logic high.
This mechanism allows the host, after diagnostics, to sample PDIAG/CBLID. If PDIAG/CBLIB is
high then there is 40-conductor cable in the system and ATA modes 3 and 4 should not be enabled.
If PDIAG/CBLID is low then there is an 80-conductor cable in the system.
Figure 2-46. Host-Side IDE Cable Detection
IDE Drive
5V
To Secondary
IDE Connector

10 KΩ
40-Conductor
Cable

GPIO
ICH

PDIAG
GPIO
15 KΩ
IDE Drive
5V
To Secondary
IDE Connector

10 KΩ

80-Conductor
IDE Cable

GPIO
ICH

PDIAG
GPIO
15 KΩ
Open

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Layout/Routing Guidelines

Device-Side Detection (BIOS Queries IDE Drive for Cable Type)
Device side detection requires only a 0.047 uF capacitor on the motherboard as shown in
Figure 2-47. This mechanism creates a resistor-capacitor (RC) time constant. The ATA mode 3 or 4
drive will drive PDIAG/CBLID low and then release it (pulled up through a 10 KΩ resistor) The
drive will sample the PDIAG signal after releasing it. In an 80-conductor cable, PDIAG/CBLID is
not connected through and, therefore, the capacitor has no effect. In a 40-conductor cable, PDIAG/
CBLID is connected though to the drive. Therefore, the signal rises more slowly. The drive can
detect the difference in rise times and it reports the cable type to the BIOS when it sends the
IDENTIFY_DEVICE packet during system boot as described in the ATA/66 specification.
Figure 2-47. Drive-Side IDE Cable Detection
IDE Drive
5V

10 KΩ
40-Conductor
Cable
ICH

PDIAG

0.047 uF
IDE Drive
5V

10 KΩ
80-Conductor
IDE Cable
ICH

PDIAG

0.047 uF
Open

Layout for BOTH Host-Side and Drive-Side Cable Detection
It is possible to layout for both Host-Side and Drive-Side cable detection and decide the method to
be used during assembly. Figure 2-48 shows the layout that allows for both host-side and drive-side
detection.

• For Host-Side Detection:
— R1 is a 0 Ω resistor
— R2 is a 15 KΩ resistor
— C1 is not stuffed

• For Drive-Side Detection:
— R1 is not stuffed
— R2 is not stuffed
— C1 is a 0.047 uF capacitor

2-58

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Layout/Routing Guidelines

Figure 2-48. Layout for Host- or Drive-Side IDE Cable Detection

ICH

R1

R2

C1

id

1

d

Figure 2-49. Ultra ATA/66 Cable

IDE Connector

Black wires are ground
Grey wires are signals

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Layout/Routing Guidelines

2.13.3

Ultra ATA/66 Pullup/Pulldown Requirements
• 22 Ω – 47 Ω series resistors are required on RESET#. The correct value should be determined
for each unique motherboard design, based on signal quality.

• An 8.2 KΩ to 10 KΩ pull-up resistor is required on IRQ14 and IRQ15 to VCC5.
• A 10 KΩ pull-down resistor is required on PDD7 and SDD7 (as required by the ATA-4
specification).

• A 5.6 KΩ pull-down resistor is required on PDDREQ# and SDDREQ# (as required by the
ATA-4 specification).

• A 1K Ω pull-up resistor is required on PIORDY and SIORDY (as required by the ATA-4
specification).
Figure 2-50. Resistor Requirements for Primary IDE Connector
22 - 47 ohm
Reset#

PCIRST_BUF#*
PDD[15:8]
PDD[7]
PDD[6:0]
PDA[2:0]
PDCS1#
PDCS3#
PDIOR#

Primary IDE Connector

PDIOW#
PDDREQ
5V
1k
ohm

5V
8.2k-10k
ohm

5.6k
ohm

10k
ohm

PIORDY
IRQ14
PDDACK#
470 ohm

CSEL

ICH

N.C.

Pin 32

N.C.

Pin 34

*Due to ringing, PCIRST# must be buffered.

2-60

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Layout/Routing Guidelines

Figure 2-51. Resistor Requirements for Secondary IDE Connector
22 - 47 ohm
Reset#

PCIRST_BUF#*
SDD[15:8]
SDD[7]
SDD[6:0]
SDA[2:0]
SDCS1#
SDCS3#
SDIOR#

Secondary IDE Connector

SDIOW#
SDDREQ
5V
1k
ohm

5V
8.2k-10k
ohm

5.6k
ohm

10k
ohm

SIORDY
IRQ15
SDDACK#
470 ohm

CSEL

ICH

N.C.

Pin 32

N.C.

Pin 34

*Due to ringing, PCIRST# must be buffered.

2.14

AC’97
The ICH implements an AC’97 2.1 compliant digital controller. Any codec attached to the ICH
AC-link must be AC’97 2.1 compliant as well. Contact your codec IHV for information on 2.1
compliant products. The AC’97 2.1 specification is on the Intel website. The ICH supports the
following combinations of codecs:

Table 2-15. ICH Codec Options
Primary

Secondary

Audio (AC)

None

Modem (MC)

None

Audio (AC)

Modem (MC)

Audio/Modem (AMC)

None

As shown in the table, the ICH does not support two codecs of the same type on the link. For
example, if an AMC is on the link, it must be the only codec. If an AC is on the link, another AC
cannot be present.
Intel has developed a common connector specification known as the Audio/Modem Riser (AMR).
This specification defines a mechanism for allowing OEM plug-in card options.

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Layout/Routing Guidelines

The AMR specification provides a mechanism for AC’97 codecs to be on a riser card. This is
important for modem codecs as it helps ease international certification of the modem.
For increased part placement flexibility, there are two routing methods for the AC’97 interface: the
tee topology and the daisy-chain topology. The AC’97 interface can be routed using 5 mil traces
with 5 mil space between the traces.
Figure 2-52. Tee Topology AC'97 Trace Length Requirements
4" Max

Codec

A
M
R

ICH
2" Max

3" Max

Figure 2-53. Daisy-Chain Topology AC'97 Trace Length Requirements

ICH
5" Max

2-62

A
M
R

3" Max

Codec

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

Clocking is provided from the primary codec on the link via BITCLK, and is derived from a
24.576 MHz crystal or oscillator. Refer to the primary codec vendor for crystal or oscillator
requirements. BITCLK is a 12.288 MHz clock driven by the primary codec to the digital controller
(ICH), and any other codec present. That clock is used as the timebase for latching and driving
data.
On the Intel® 820 chipset platform, the ICH supports Wake on Ring from S1, S3, and S4 via the
AC’97 link. The codec asserts SDATAIN to wake the system. To provide wake capability and/or
caller ID, standby power must be provided to the modem codec.
The ICH has weak pulldowns/pullups that are only enabled when the AC-Link Shut Off bit in the
ICH is set. This will keep the link from floating when the AC-link is off, or there are no codecs
present.
If the Shut-off bit is not set, it implies that there is a codec on the link. Therefore, BITCLK and
AC_SDOUT will be driven by the codec and ICH respectively. However, AC_SDIN0 and
AC_SDIN1 may not be driven. If the link is enabled, the assumption can be made that there is at
least one codec. If there is an onboard codec only (i.e., no AMR), then the unused SDIN pin should
have a weak (10 KΩ) pulldown to keep it from floating. If an AMR is used, any SDIN signal that
could be no connected (e.g., with no codec, both can be NC), then both SDIN pins must have a
10 KΩ pulldown.
Table 2-16. AC'97 SDIN Pulldown Resistors
System Solution

Pullup Requirements

On-board Codec Only

Pulldown the SDIN pin that is NOT connected to the codec

AMR Only

Pulldown BOTH SDIN pins

BOTH AMR and On-board Codec

Pulldown any SDIN pin that could be NC*

NOTE: If the on-board codec can be disabled, both SDIN pins must have pulldowns. If the on-board codec can
not be disabled, only the SDIN not connected to the on-board codec requires a pulldown.

2.14.1

AC’97 Signal Quality Requirements
In a lightly loaded system (e.g., single codec down), AC'97 signal integrity should be evaluated to
confirm that the signal quality on the link is acceptable to the codec used in the design. A series
resistor at the driver and a capacitor at the codec can be implemented in order to compensate for
any signal integrity issues. The values used will be design dependent and should be verified for
correct timings. The ICH AC-link output buffers are designed to meet the AC'97 2.1 specification
with the specified load of 50pF.

2.14.2

AC’97 Motherboard Implementation
The following design considerations are provided for the implementation of an ICH0/ICH platform
using AC’97. These design guidelines have been developed to ensure maximum flexibility for
board designers while reducing the risk of board related issues. These recommendations do not
represent the only implementation or a complete checklist, but provides recommendations based on
the ICH0/ICH platform.

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Layout/Routing Guidelines

• Codec Implementation

•

•
•

2-64

— The motherboard can implement any valid combination of codecs on the motherboard and
on the riser. For ease of homologation, it is recommended that a modem codec be
implemented on the AMR module; however, nothing precludes a modem codec on the
motherboard.
— Only one primary codec can be present on the link. A maximum of two present codecs can
be supported in an ICH0/ICH platform.
— If the motherboard implements an active primary codec on the motherboard and provides
an AMR connector, it must tie PRI_DN# to ground.
— The PRI_DN# pin is provided to indicate a primary codec is present on the motherboard.
Therefore, the AMR module and/or codec must provide a means to prevent contention
when this signal is asserted by the motherboard, without software intervention.
— Components (e.g., FET switches), buffers, or logic states should not be implemented on
the AC-link signals, except for AC_RST#. Doing so will potentially interfere with timing
margins and signal integrity.
— If the motherboard requires that an AMR module override a primary codec down, a means
of preventing contention on the AC-link must be provided for the onboard codec.
— The ICH0/ICH supports Wake on Ring* from S1-S4 states via the AC’97 link. The codec
asserts SDATAIN to wake the system. To provide wake capability and/or caller ID,
standby power must be provided to the modem codec. If no codec is attached to the link,
internal pulldowns will prevent the inputs from floating, therefore external resistors are
not required. The ICH0/ICH does not wake from the S5 state via the AC’97 link.
— The SDATAIN[0:1] pins should not be left in a floating state if the pins are not connected
and the AC-link is active—they should be pulled to ground through a weak
(approximately 10 KΩ) pull-down resistor. If the AC-link is disabled (by setting the shutoff bit to 1), then the ICH0/ICH’s internal pull-down resistors are enabled, and thus there
is no need for external pull-down resistors. However, if the AC-link is to be active, then
there should be pull-down resistors on any SDATAIN signal that has the potential of not
being connected to a codec. For example, if a dedicated audio codec is on the
motherboard, and cannot be disabled via a hardware jumper or stuffing option, then its
SDATAIN signal does not need a pull-down resistor. If however, the SDATAIN signal has
no codec connected, or is connected to an AMR slot, or is connected to an onboard codec
that can be hardware disabled, then the signal should have an external pull-down resistor
to ground.
AMR Slot Special Connections
— AUDIO_MUTE#: No connect on the motherboard.
— AUDIO_PWRDN: No connect on the motherboard. Codecs on the AMR card should
implement a powerdown pin, per the AC’97 2.1 specification, to control the amplifier.
— MONO_PHONE: Connect top onboard audio codec if supported.
— MONO_OUT/PC_BEEP: Connect to SPKR output from the ICH0/ICH, or MONO_OUT
from onboard codec.
— PRIMARY_DN#: See discussion above.
— +5VDUAL/+5VSB: Connect to VCC5 core on the motherboard, unless adequate power
supply is available. An AMR card using this standby/dual supply should not prevent basic
operation if this pin is connected to core power.
— S/P-DIF_IN: Connect to ground on the motherboard.
— AC_SDATAIN[3:2]: No connect on the motherboard. The ICH0/ICH supports a
maximum of two codecs, which should be attached to SDATAIN[1:0].
— AC97_MSTRCLK: Connect to ground on the motherboard.
The ICH0/ICH provides internal weak pulldowns. Therefore, the motherboard does not need
to provide discrete pulldown resistors.
PC_BEEP should be routed through the audio codec. Care should be taken to avoid the
introduction of a pop when powering the mixer up or down.

Intel®820 Chipset Design Guide

Layout/Routing Guidelines

2.15

USB
The following are general guidelines for the USB interface:
• Unused USB ports should be terminated with 15 KΩ pulldown resistors on both P+/P- data
lines.
• 15 Ω series resistors should be placed as close as possible to the ICH (<1 inch). These series
resistors are required for source termination of the reflected signal.
• 47 pF caps must be placed as close to the ICH as possible and on the ICH side of the series
resistors on the USB data lines (P0+/-, P1+/-). These caps are there for signal quality (rise/fall
time) and to help minimize EMI radiation.
• 15 KΩ ±5% pulldown resistors should be placed on the USB side of the series resistors on the
USB data lines (P0+/-, P1+/-), and are REQUIRED for signal termination by USB
specification. The length of the stub should be as short as possible.
• The trace impedance for the P0+/-, P1+/- signals should be 45 Ω (to ground) for each USB
signal P+ or P-. Using the stackup recommended in section Section 5.3, “Stackup
Requirement” on page 5-1. USB requires 9 mils traces. The impedance is 90 Ω between the
differential signal pairs P+ and P- to match the 90 Ω USB twisted pair cable impedance. Note
that twisted pair characteristic impedance of 90 Ω is the series impedance of both wires,
resulting in an individual wire presenting a 45 Ω impedance. The trace impedance can be
controlled by carefully selecting the trace width, trace distance from power or ground planes,
and physical proximity of nearby traces.
• USB data lines must be routed as critical signals. The P+/P- signal pair must be routed together
and not parallel with other signal traces to minimize crosstalk. Doubling the space from the
P+/P- signal pair to adjacent signal traces will help to prevent crosstalk. Do not worry about
crosstalk between the two P+/P- signal traces. The P+/P- signal traces must also be the same
length. This will minimize the effect of common mode current on EMI.
Figure 2-54 illustrates the recommended USB schematic.

Figure 2-54. USB Data Signals

Motherboard Trace

Driver

15 ohm
< 1"

45 ohm
47 pf

15k
Motherboard Trace

Driver

15 ohm
< 1"

P-

Intel®820 Chipset Design Guide

90 ohm

45 ohm
47 pf

ICH

USB Connector

P+

15k

Transmission Line

USB Twisted Pair Cable

2-65

Layout/Routing Guidelines

Recommended USB trace characteristics

•
•
•
•
•

Impedance ‘Z0’ = 45.4 Ω
Line Delay = 160.2 ps
Capacitance = 3.5 pF
Inductance = 7.3 nH
Res @ 20° C = 53.9 mOhm

2.16

ISA (82380AB)

2.16.1

ICH GPIO connected to 82380AB
At reset, the ICH LPC Bridge defaults to subtractive decode. Since the LPC bridge logically sits on
PCI there will be two subtractive decode bridges in systems with the 82380AB (which is also a
subtractive decode device). A GPO that defaults high (i.e., ICH GPO 21) must be connected to the
NOGO signal on the 82380AB. Asserting NOGO prevents the 82380AB from subtractively
decoding cycles on the PCI bus. The BIOS must configure the 82380AB, program the ICH to
positively decode LPC cycles, and release the NOGO signal to the 82380AB.

2.16.2

Sub Class Code
Both the LPC Bridge and the 82380AB have the same Sub Class code indicating an ISA bridge.
This can not be handled by the OS’s PCI PnP code. The ICH provides the ability to hide IDSEL to
the 82380AB. ICH A22 must be connected to the 82380AB IDSEL signal. After the BIOS
configures the 82380AB, it will set a bit in the ICH that hides the 82380AB from the OS by not
asserting the IDSEL (A22) to the 82380AB during OS enumeration.

2.17

IOAPIC Design Recommendation
UP systems not using the IOAPIC should follow these recommendations:

• On the ICH
— Connect PICCLK directly to ground
— Connect PICD0, PICD1 to ground through a 10 KΩ resistor

• On the CPU
— PICCLK must be connected from the clock generator to the PICCLK pin on the processor
— Connect PICD0 to 2.5V through 10 KΩ resistors
— Connect PICD1 to 2.5V through 10 KΩ resistors

2-66

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Layout/Routing Guidelines

2.18

SMBus/Alert Bus
The Alert on LAN* signals can be used as:

• Alert on LAN* signals: 4.7 KΩ pullup resistors to 3.3VSB are required.
Pullup resistors to 3.3VSB and the signals must be allowed to
• GPIOs:
change states on powerup (e.g., on power-up, the ICH drives
heartbeat messages until the BIOS programs these signals as
GPIOs). The value of the pullup resistors depends on the loading on
the GPIO signal.

• Not Used:

4.7 KΩ pullup resistors to 3.3VSB are required.

If the SMBus is used only for the three SPD EEPROMs (one on each RIMM), both signals should
be pulled up with a 4.7 KΩ resistor to 3.3V.

2.19

PCI
The ICH provides a PCI Bus interface that is compliant with the PCI Local Bus Specification
Revision 2.2. The implementation is optimized for high-performance data streaming when the ICH
is acting as either the target or the initiator on the PCI bus. For more information on the PCI Bus
interface, refer to the PCI Local Bus Specification Revision 2.2.
The ICH supports six PCI Bus masters (excluding the ICH), by providing six REQ#/GNT# pairs.
In addition, the ICH supports two PC/PCI REQ#/GNT# pairs, one of which is multiplexed with a
PCI REQ#/GNT# pair.

Figure 2-55. PCI Bus Layout Example

ICH

2.20

RTC
The ICH contains a real time clock (RTC) with 256 bytes of battery backed SRAM. The internal
RTC module provides two key functions: keeping date and time, and storing system data in its
RAM when the system is powered down.
This section will present the recommended hookup for the RTC circuit for the ICH. This circuit is
not the same as the circuit used for the PIIX4.

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Layout/Routing Guidelines

2.20.1

RTC Crystal
The ICH RTC module requires an external oscillating source of 32.768 KHz connected on the
RTCX1 and RTCX2 pins. Figure 2-56 documents the external circuitry that comprises the
oscillator of the ICH RTC.

Figure 2-56. External Circuitry for the ICH RTC2
VCCRTC 3

VCC3_3SBY
1 µF

1 kΩ

RTCX2 4
1 kΩ

Vbat_rtc

32768 Hz
Xtal

R1
10 M Ω
RTCX1 5

C1
0.047 uF

C3 1

R2
10 M Ω
VBIAS 6

C2 1
VSS 7

NOTES:
1. The exact capacitor value needs to based on what the crystal maker recommends.
2. This circuit is not the same as the one used for PIIX4.
3. VCCRTC: Power for RTC Well
4. RTCX2: Crystal Input 2 – Connected to the 32.768 KHz crystal.
5. RTCX1: Crystal Input 1 – Connected to the 32.768 KHz crystal.
6. VBIAS: RTC BIAS Voltage – This pin is used to provide a reference voltage, and this DC voltage sets a
current which is mirrored throughout the oscillator and buffer circuitry.
7. VSS: Ground

2.20.2

External Capacitors
To maintain the RTC accuracy, the external capacitor C1 needs to be 0.047 uF, and the external
capacitor values (C2 and C3) should be chosen to provide the manufacturer’s specified load
capacitance (Cload) for the crystal when combined with the parasitic capacitance of the trace,
socket (if used), and package. When the external capacitor values are combined with the
capacitance of the trace, socket, and package, the closer the capacitor value can be matched to the
actual load capacitance of the crystal used, the more accurate the RTC will be.
Equation 2-4 can be used to choose the external capacitance values (C2 and C3):

Equation 2-4. External Capacitance Calculation
Cload = (C2 * C3)/(C2+C3) + Cparasitic

C3 can be chosen such that C3 > C2. Then C2 can be trimmed to obtain the 32.768 kHz.

2-68

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2.20.3

RTC Layout Considerations
•
•
•
•

Keep the RTC lead lengths as short as possible; around ¼ inch is sufficient.
Minimize the capacitance between Xin and Xout in the routing.
Put a ground plane under the XTAL components.
Do not route switching signals under the external components (unless on the other side of the
board).

• The oscillator VCC should be clean; use a filter, such as an RC lowpass, or a ferrite inductor.

2.20.4

RTC External Battery Connection
The RTC requires an external battery connection to maintain its functionality and its RAM while
the ICH is not powered by the system.
Example batteries are Duracell 2032, 2025, or 2016 (or equivalent), which can give many years of
operation. Batteries are rated by storage capacity. The battery life can be calculated by dividing the
capacity by the average current required. For example, if the battery storage capacity is 170 mAh
(assumed usable) and the average current required is 3 uA, the battery life will be at least:
170,000 uAh / 3 uA = 56,666 h = 6.4 years

The voltage of the battery can affect the RTC accuracy. In general, when the battery voltage
decays, the RTC accuracy also decreases. High accuracy can be obtained when the RTC voltage is
in the range of 3.0V to 3.3V.
The battery must be connected to the ICH via an isolation schottky diode circuit. The schottky
diode circuit allows the ICH RTC-well to be powered by the battery when the system power is not
available, but by the system power when it is available. To do this, the diodes are set to be reverse
biased when the system power is not available. Figure 2-57 is an example of a diode circuitry that
is used.
Figure 2-57. Diode Circuit Connecting RTC External Battery
VCC3_3SBY

1 KΩ
VccRTC
1.0 uF

rtc e t bat sd

A standby power supply should be used in a desktop system to provide continuous power to the
RTC when available, which will significantly increase the RTC battery life and thereby increase the
RTC accuracy.

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Layout/Routing Guidelines

2.20.5

RTC External RTCRST Circuit
The ICH RTC requires some additional external circuitry. The RTCRST# signal is used to reset the
RTC well. The external capacitor and the external resistor between RTCRST# and the RTC battery
(Vbat) were selected to create an RC time delay, such that RTCRST# will go high some time after
the battery voltage is valid. The RC time delay should be in the range of 10-20 ms. When
RTCRST# is asserted, bit 2 (RTC_PWR_STS) in the GEN_PMCON_3 (General PM Configuration
3) register is set to 1, and remains set until software clears it. As a result of this, when the system
boots, the BIOS knows that the RTC battery has been removed.

Figure 2-58. RTCRST External Circuit for the ICH RTC
VCC3_3SBY
Diode/
Battery
Circuit

1K
VccRTC
1.0 uF

8.2K

RTCRST#
2.2 uF

RTCRST
Circuit

This RTCRST# circuit is combined with the diode circuit (Figure 2-57) which allows the RTC well
to be powered by the battery when the system power is not available. Figure 2-56 is an example of
this circuitry that is used in conjuction with the external diode circuit.

2.20.6

RTC Routing Guidelines
• All RTC OSC signals (RTCX1, RTCX2, VBIAS) should all be routed with trace lengths of
less than 1”, the shorter the better

• Minimize the capacitance between RTCX1 and RTCX2 in the routing (optimal would be a
ground line between them)

• Put a ground plane under all of the external RTC circuitry
• Do not route any switching signals under the external components (unless on the other side of
the ground plane)

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2.20.7

VBIAS DC Voltage and Noise Measurements
• Steady state VBIAS will be a DC voltage of about 0.38V ±0.06V.
• VBIAS will be “kicked” when the battery is inserted to about 0.7–1.0V, but it will come back
to its DC value within a few ms.

• Noise on VBIAS must be kept to a minimum, 200 mV or less.
• VBIAS is very sensitive and cannot be directly probed; it can be probed through a 0.01 uF
capacitor.

• Excess noise on VBIAS can cause the ICH internal oscillator to misbehave or even stop
completely.

• To minimize noise of VBIAS, it is necessary to implement the routing guidelines described
above and the required external RTC circuitry.

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Advanced System Bus Design

Advanced System Bus Design

3

Section 2.9, “System Bus Design” on page 2-46 describes the recommendations for designing
Intel® 820 chipset based platforms. This chapter discusses more detail about the methodology used
to develop the guidelines. Section 3.2, “AGTL+ Design Guidelines” on page 3-4 discusses specific
system guidelines. This is a step-by-step methodology that Intel has successfully used to design
high performance desktop systems. Section 3.3, “Theory” on page 3-15 introduces the theories that
are applicable to this layout guideline. Section 3.4, “More Details and Insight” on page 3-19
contains more details and insights. The items in Section 3.4 expand on some of the rationale for the
recommendations in the step-by-step methodology. This section also includes equations that may
be used for reference.

3.1

Terminology and Definitions
Term

Definition

Aggressor

A network that transmits a coupled signal to another network is called the
aggressor network.

AGTL+

The processor system bus uses a bus technology called AGTL+, or Assisted
Gunning Transceiver Logic. AGTL+ buffers are open-drain and require pull-up
resistors for providing the high logic level and termination. The processor
AGTL+ output buffers differ from GTL+ buffers with the addition of an active
pMOS pull-up transistor to “assist” the pull-up resistors during the first clock of
a low-to-high voltage transition. Additionally, the processor Single Edge
Connector (S.E.C.) cartridge contains 56 Ω pull-up resistors to provide
termination at each bus load.

Bus Agent

A component or group of components that, when combined, represent a single
load on the AGTL+ bus.

Corner

Describes how a component performs when all parameters that could impact
performance are adjusted to have the same impact on performance. Examples of
these parameters include variations in manufacturing process, operating
temperature, and operating voltage. The results in performance of an electronic
component that may change as a result of corners include (but are not limited
to): clock to output time, output driver edge rate, output drive current, and input
drive current. Discussion of the “slow” corner would mean having a component
operating at its slowest, weakest drive strength performance. Similar discussion
of the “fast” corner would mean having a component operating at its fastest,
strongest drive strength performance. Operation or simulation of a component at
its slow corner and fast corner is expected to bound the extremes between
slowest, weakest performance and fastest, strongest performance.

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Term

Definition

Cross-talk

The reception on a victim network of a signal imposed by aggressor network(s)
through inductive and capacitive coupling between the networks.

• Backward Cross-talk - coupling which creates a signal in a victim network
that travels in the opposite direction as the aggressor’s signal.

• Forward Cross-talk - coupling which creates a signal in a victim network
that travels in the same direction as the aggressor’s signal.

• Even Mode Cross-talk - coupling from multiple aggressors when all the
aggressors switch in the same direction that the victim is switching.

• Odd Mode Cross-talk - coupling from multiple aggressors when all the
aggressors switch in the opposite direction that the victim is switching.
Edge Finger

The cartridge electrical contact that interfaces to the SC242 connector.

Flight Time

Flight Time is a term in the timing equation that includes the signal propagation
delay, any effects the system has on the TCO of the driver, plus any adjustments
to the signal at the receiver needed to guarantee the setup time of the receiver.
More precisely, flight time is defined to be:

• The time difference between a signal at the input pin of a receiving agent
crossing VREF (adjusted to meet the receiver manufacturer’s conditions
required for AC timing specifications; i.e., ringback, etc.), and the output
pin of the driving agent crossing VREF if the driver was driving the Test
Load used to specify the driver’s AC timings.
See Section for details regarding flight time simulation and validation.
The VREF Guardband takes into account sources of noise that may affect the
way an AGTL+ signal becomes valid at the receiver. See the definition of
the VREF Guardband.

• Maximum and Minimum Flight Time - Flight time variations can be
caused by many different parameters. The more obvious causes include
variation of the board dielectric constant, changes in load condition, crosstalk, VTT noise, VREF noise, variation in termination resistance and
differences in I/O buffer performance as a function of temperature, voltage
and manufacturing process. Some less obvious causes include effects of
Simultaneous Switching Output (SSO) and packaging effects.

• The Maximum Flight Time is the largest flight time a network will
experience under all variations of conditions. Maximum flight time is
measured at the appropriate VREF Guardband boundary.

• The Minimum Flight Time is the smallest flight time a network will
experience under all variations of conditions. Minimum flight time is
measured at the appropriate VREF Guardband boundary.
For more information on flight time and the VREF Guardband, see the
Pentium® II Processor Developer’s Manual.
GTL+

3-2

GTL+ is the bus technology used by the Pentium® Pro processor. This is an
incident wave switching, open-drain bus with pull-up resistors that provide both
the high logic level and termination. It is an enhancement to the GTL (Gunning
Transceiver Logic) technology. See thePentium® II Processor Developer’s
Manual for more details of GTL+.

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Term

Definition

Network

The trace of a Printed Circuit Board (PCB) that completes an electrical
connection between two or more components.

Network
Length

The distance between extreme bus agents on the network and does not include
the distance connecting the end bus agents to the termination resistors.

Overdrive
Region

Is the voltage range, at a receiver, located above and below VREF for signal
integrity analysis. See the Intel® Pentium® II Processor Developer’s Manual for
more details.

Overshoot

Maximum voltage allowed for a signal at the processor core pad. See each
processor’s datasheet for overshoot specification.

Pad

A feature of a semiconductor die contained within an internal logic package on
the S.E.C cartridge substrate used to connect the die to the package bond wires.
A pad is only observable in simulation.

Pin

A feature of a logic package contained within the S.E.C. cartridge used to
connect the package to an internal substrate trace.

Ringback

Ringback is the voltage that a signal rings back to after achieving its maximum
absolute value. Ringback may be due to reflections, driver oscillations, etc. See
the respective processor’s datasheet for ringback specification.

Settling Limit

Defines the maximum amount of ringing at the receiving pin that a signal must
reach before its next transition. See the respective processor’s datasheet for
settling limit specification.

Setup Window

Is the time between the beginning of Setup to Clock (TSU_MIN) and the arrival of
a valid clock edge. This window may be different for each type of bus agent in
the system.

Simultaneous
Switching
Output (SSO)
Effects

Refers to the difference in electrical timing parameters and degradation in signal
quality caused by multiple signal outputs simultaneously switching voltage
levels (e.g., high-to-low) in the opposite direction from a single signal (e.g., lowto-high) or in the same direction (e.g., high-to-low). These are respectively
called odd-mode switching and even-mode switching. This simultaneous
switching of multiple outputs creates higher current swings that may cause
additional propagation delay (or “pushout”), or a decrease in propagation delay
(or “pull-in”). These SSO effects may impact the setup and/or hold times and are
not always taken into account by simulations. System timing budgets should
include margin for SSO effects.

Stub

The branch from the trunk terminating at the pad of an agent.

Test Load

Intel uses a 50 Ω test load for specifying its components.

Trunk

The main connection, excluding interconnect branches, terminating at agent
pads.

Undershoot

Maximum voltage allowed for a signal to extend below VSS at the processor core
pad. See the respective processor’s datasheet for undershoot specifications.

Victim

A network that receives a coupled cross-talk signal from another network is
called the victim network.

VREF Guardband A guardband (∆VREF) defined above and below VREF to provide a more realistic
model accounting for noise such as cross-talk, VTT noise, and VREF noise.

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Advanced System Bus Design

3.2

AGTL+ Design Guidelines
The following step-by-step guideline was developed for systems based on two processor loads and
one Intel 82820 MCH load. Systems using custom chipsets will require timing analysis and analog
simulations specific to those components.
The guideline recommended in this section is based on experience developed at Intel while
developing many different Intel Pentium® Pro processor family and Intel Pentium III processorbased systems. Begin with an initial timing analysis and topology definition. Perform pre-layout
analog simulations for a detailed picture of a working “solution space” for the design. These prelayout simulations help define routing rules prior to placement and routing. After routing, extract
the interconnect database and perform post-layout simulations to refine the timing and signal
integrity analysis. Validate the analog simulations when actual systems become available. The
validation section describes a method for determining the flight time in the actual system.
Guideline Methodology:

• Initial Timing Analysis
• Determine General Topology, Layout, and Routing
• Pre-Layout Simulation
— Sensitivity sweep
— Monte Carlo Analysis

• Place and Route Board
— Estimate Component to Component Spacing for AGTL+ Signals
— Layout and Route Board

• Post-Layout Simulation
— Interconnect Extraction
— Inter-Symbol Interference (ISI), Cross-talk, and Monte Carlo Analysis

• Validation
— Measurements
— Determining Flight Time

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3.2.1

Initial Timing Analysis
Perform an initial timing analysis of the system using Equation 3-1 and Equation 3-2 shown below.
These equations are the basis for timing analysis. To complete the initial timing analysis, values for
clock skew and clock jitter are needed, along with the component specifications. These equations
contain a multi-bit adjustment factor, MADJ, to account for multi-bit switching effects such as SSO
pushout or pull-in that are often hard to simulate. These equations do not take into consideration all
signal integrity factors that affect timing. Additional timing margin should be budgeted to allow for
these sources of noise.

Equation 3-1. Setup Time
TCO_MAX + TSU_MIN + CLKSKEW + CLKJITTER + TFLT_MAX + MADJ ≤ Clock Period

Equation 3-2. Hold Time
TCO_MIN + TFLT_MIN - MADJ ≥ THOLD + CLKSKEW

Symbols used in Equation 3-1 and Equation 3-2:
— TCO_MAX is the maximum clock to output specification1.
— TSU_MIN is the minimum required time specified to setup before the clock1.
— CLKJITTER is the maximum clock edge-to-edge variation.
— CLKSKEW is the maximum variation between components receiving the same clock edge.
— TFLT_MAX is the maximum flight time as defined in Section 3.1, “Terminology and
Definitions” on page 3-1.
— TFLT_MIN is the minimum flight time as defined in Section 3.1, “Terminology and
Definitions” on page 3-1.
— MADJ is the multi-bit adjustment factor to account for SSO pushout or pull-in.
— TCO_MIN is the minimum clock to output specification1.
— THOLD is the minimum specified input hold time.
Note:

The Clock to Output (TCO) and Setup to Clock (TSU) timings are both measured from the signals
last crossing of VREF, with the requirement that the signal does not violate the ringback or edge
rate limits. See the respective Processor’s datasheet and thePentium® III Processor Developer’s
Manual for more details.
Solving these equations for TFLT results in the following equations:

Equation 3-3. Maximum Flight Time
TFLT_MAX ≤ Clock Period - T CO_MAX - TSU_MIN - CLKSKEW - CLKJITTER - MADJ

Equation 3-4. Minimum Flight Time
TFLT_MIN ≥ THOLD + CLKSKEW - TCO_MIN + MADJ

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There are multiple cases to consider. Note that while the same trace connects two components,
component A and component B, the minimum and maximum flight time requirements for
component A driving component B as well as component B driving component A must be met. The
cases to be considered are:

• Processor driving processor
• Processor driving chipset
• Chipset driving processor
A designer using components other than those listed above must evaluate additional combinations
of driver and receiver.
Table 3-1. AGTL+ Parameters for Example Calculations1,2
Intel® Pentium® III
processor core at
133 MHz Bus

Intel 82820
MCH

Clock to Output maximum (TCO_MAX)

2.7

3.6

Clock to Output minimum (TCO_MIN)

-0.1

0.5

4

Setup time (TSU_MIN)

1.2

2.27

3,4

Hold time (THOLD)

0.8

0.28

4

IC Parameters

Notes
4

NOTES:
1. All times in nanoseconds.
2. Numbers in table are for reference only. These timing parameters are subject to change. Please check the
appropriate component documentation for valid timing parameter values.
3. TSU_MIN = 1.9 ns assumes the 82820 MCH sees a minimum edge rate equal to 0.3 V/ns.
4. The Pentium III substrate nominal impedance is set to 65 Ω ±15%. Future Pentium III processor substrate
may be set at 60 Ω ±15%

Table 3-1 lists the AGTL+ component timings of the processors and 82820 MCH defined at the
pins. These timings are for reference only.
Table 3-2 gives an example AGTL+ initial maximum flight time and Table 3-3 is an example
minimum flight time calculation for a 133 MHz, 2-way Pentium III processor/Intel 820 chipset
system bus. Note that assumed values for clock skew and clock jitter were used. Clock skew and
clock jitter values are dependent on the clock components and distribution method chosen for a
particular design and must be budgeted into the initial timing equations as appropriate for each
design.
Intel highly recommends adding margin as shown in the “MADJ” column to offset the degradation
caused by SSO push-out and other multi-bit switching effects. The “Recommended TFLT_MAX”
column contains the recommended maximum flight time after incorporating the MADJ value. If
edge rate, ringback, and monotonicity requirements are not met, flight time correction must first be
performed as documented in the Pentium® II Processor Developer’s Manual with the additional
requirements noted in Section 3.5, “Definitions of Flight Time Measurements/Corrections and
Signal Quality” on page 3-24. The commonly used “textbook” equations used to calculate the
expected signal propagation rate of a board are included in Section 3.2, “AGTL+ Design
Guidelines” on page 3-4.
Simulation and control of baseboard design parameters can ensure that signal quality and
maximum and minimum flight times are met. Baseboard propagation speed is highly dependent on
transmission line geometry configuration (stripline vs. microstrip), dielectric constant, and loading.
This layout guideline includes high-speed baseboard design practices that may improve the amount

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of timing and signal quality margin. The magnitude of MADJ is highly dependent on baseboard
design implementation (stackup, decoupling, layout, routing, reference planes, etc.) and needs to
be characterized and budgeted appropriately for each design.
Table 3-2 and Table 3-3 are derived assuming:

• CLKSKEW = 0.2 ns (Note: Assumes clock driver pin-to-pin skew is reduced to 50 ps by tying

two host clock outputs together (“ganging”) at clock driver output pins, and the PCB clock
routing skew is 150 ps. System timing budget must assume 0.175 ns of clock driver skew if
outputs are not tied together and a clock driver that meets the CK98 clock driver specification
is being used.)

• CLKJITTER = 0.250 ns
Some clock driver components may not support ganging the outputs together. Be sure to
verify with your clock component vendor before ganging the outputs. See the appropriate Intel
820 chipset documentation for details on clock skew and jitter specifications. Refer to
Section 2.6.2, “Direct Rambus* Layout Guidelines” on page 2-8 and Chapter 4, “Clocking” for
host clock routing details.
Table 3-2. Example TFLT_MAX Calculations for 133 MHz Bus1
Receiver

Clk
Period2

TCO_MAX

TSU_MIN

ClkSKEW

ClkJITTER

Processor4

7.50

2.7

1.20

0.20

0.250

0.40

2.75

82820 MCH

7.50

2.7

2.27

0.20

0.250

0.40

1.68

7.50

3.63

1.20

0.20

0.25

0.40

1.82

Driver

Processor4
Processor

4

82820 MCH

Processor

4

MAD
J

Recommended
TFLT_MAX3

NOTES:
1. All times in nanoseconds.
2. BCLK period = 7.50 ns @ 133.33 MHz.
3. The flight times in this column include margin to account for the following phenomena that Intel has observed
when multiple bits are switching simultaneously. These multi-bit effects can adversely affect flight time and
signal quality and are sometimes not accounted for in simulation. Accordingly, maximum flight times depend
on the baseboard design and additional adjustment factors or margins are recommended.
- SSO push-out or pull-in.
- Rising or falling edge rate degradation at the receiver caused by inductance in the current return
path, requiring extrapolation that causes additional delay.
- Cross-talk on the PCB and internal to the package can cause variation in the signals.
There are additional effects that may not necessarily be covered by the multi-bit adjustment factor and
should be budgeted as appropriate to the baseboard design. Examples include:
- The effective board propagation constant (SEFF), which is a function of:
• Dielectric constant (εr) of the PCB material.
• The type of trace connecting the components (stripline or microstrip).
• The length of the trace and the load of the components on the trace. Note that the board propagation
constant multiplied by the trace length is a component of the flight time but not necessarily equal
to the flight time.
4. Processor values specified in this table are examples only. Refer to the appropriate processor datasheet for
specification values.

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Advanced System Bus Design

Table 3-3. Example TFLT_MIN Calculations (Frequency Independent)
THOLD

ClkSKEW

TCO_MIN

Recommended
TFLT_MIN

Processor2

0.8

0.2

-0.1

1.2

Processor2

82820 MCH

0.28

0.2

-0.1

.58

82820 MCH

Processor2

0.8

0.2

0.5

.5

Driver
Processor2

Receiver

NOTES:
1. All times in nanoseconds.
2. Processor values specified in this table are examples only. Refer to the appropriate processor datasheet for
specification values.

3.2.2

Determine General Topology, Layout, and Routing Desired
After calculating the timing budget, determine the approximate location of the processor and the
chipset on the base board (see Section 2.9, “System Bus Design” on page 2-46).

3.2.3

Pre-Layout Simulation

3.2.3.1

Methodology
Analog simulations are recommended for high speed system bus designs. Start simulations prior to
layout. Pre-layout simulations provide a detailed picture of the working “solution space” that meets
flight time and signal quality requirements. The layout recommendations in the previous sections
are based on pre-layout simulations conducted at Intel. By basing board layout guidelines on the
solution space, the iterations between layout and post-layout simulation can be reduced.
Intel recommends running simulations at the device pads for signal quality and at the device pins
for timing analysis. However, simulation results at the device pins may be used later to correlate
simulation performance against actual system measurements.

3.2.3.2

Sensitivity Analysis
Pre-layout analysis includes a sensitivity analysis using parametric sweeps. Parametric sweep
analysis involves varying one or two system parameters while all others such as driver strength,
package, Z0, and S0 are held constant. This way, the sensitivity of the proposed bus topology to
varying parameters can be analyzed systematically. Sensitivity of the bus to minimum flight time,
maximum flight time, and signal quality should be covered. Suggested sweep parameters include
trace lengths, termination resistor values, and any other factors that may affect flight time, signal
quality, and feasibility of layout. Minimum flight time and worst signal quality are typically
analyzed using fast I/O buffers and interconnect. Maximum flight time is typically analyzed using
slow I/O buffers and slow interconnects.
Outputs from each sweep should be analyzed to determine which regions meet timing and signal
quality specifications. To establish the working solution space, find the common space across all
the sweeps that result in passing timing and signal quality. The solution space should allow enough
design flexibility for a feasible, cost-effective layout.

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3.2.3.3

Monte Carlo Analysis
Perform a Monte Carlo analysis to refine the passing solution space region. A Monte Carlo analysis
involves randomly varying parameters (independent of one another) over their tolerance range.
This analysis intends to ensure that no regions of failing flight time and signal quality exists
between the extreme corner cases run in pre-layout simulations. For the example topology, vary the
following parameters during Monte Carlo simulations:

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3.2.3.4

Lengths L1 through L3
Termination resistance RTT on the processor cartridge #1
Termination resistance RTT on the processor cartridge #2
Z0 of traces on processor cartridge #1
Z0 of traces on processor cartridge #2
S0 of traces on processor cartridge #1
S0 of traces on processor cartridge #2
Z0 of traces on baseboard
S0 of traces on baseboard
Fast and slow corner processor I/O buffer models for cartridge #1
Fast and slow corner processor I/O buffer models for cartridge #2
Fast and slow package models for processor cartridge #1
Fast and slow package models for processor cartridge #2
Fast and slow corner 82820 MCH I/O buffer models
Fast and slow 82820 MCH package models

Simulation Criteria
Accurate simulations require that the actual range of parameters be used in the simulations. Intel
has consistently measured the cross-sectional resistivity of the PCB copper to be approximately
1 Ω*mil2/inch, not the 0.662 Ω*mil2/inch value for annealed copper that is published in reference
material. Using the 1 Ω*mil2/inch value may increase the accuracy of lossy simulations.
Positioning drivers with faster edges closer to the middle of the network typically results in more
noise than positioning them towards the ends. However, Intel has shown that drivers located in all
positions (given appropriate variations in the other network parameters) can generate the worstcase noise margin. Therefore, Intel recommends simulating the networks from all driver locations,
and analyzing each receiver for each possible driver.
Analysis has shown that both fast and slow corner conditions must be run for both rising and
falling edge transitions. The fast corner is needed because the fast edge rate creates the most noise.
The slow corner is needed because the buffer’s drive capability will be a minimum, causing the VOL
to shift up, which may cause the noise from the slower edge to exceed the available budget. Slow
corner models may produce minimum flight time violations on rising edges if the transition starts
from a higher VOL. So, Intel highly recommends checking for minimum and maximum flight time
violations with both the fast and slow corner models. The fast and slow corner I/O buffer models
are contained in the processor and Intel 820 chipset electronic models provided by Intel.
The transmission line package models must be inserted between the output of the buffer and the net
it is driving. Likewise, the package model must also be placed between a net and the input of a
receiver model. Editing the simulator’s net description or topology file generally does this.

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Intel has found wide variation in noise margins when varying the stub impedance and the PCB’s
Z0 and S0. Intel therefore recommends that PCB parameters are controlled as tightly as possible,
with a sampling of the allowable Z0 and S0 simulated. The Intel® Pentium® III processor nominal
effective line impedance is 65 Ω ±15%. Future Intel® Pentium® III processor effective line
impedance (ZEFF) may be 60 Ω ±15%. Intel recommends the baseboard nominal effective line
impedance to be at 60 Ω ±15% for the recommended layout guidelines to be effective. Intel also
recommends running uncoupled simulations using the Z0 of the package stubs; and performing
fully coupled simulations if increased accuracy is needed or desired. Accounting for cross-talk
within the device package by varying the stub impedance was investigated and was not found to be
sufficiently accurate. This lead to the development of full package models for the component
packages.

3.2.4

Place and Route Board

3.2.4.1

Estimate Component To Component Spacing for AGTL+ Signals
Estimate the number of layers that will be required. Then determine the expected interconnect
distances between each of the components on the AGTL+ bus. Using the estimated interconnect
distances, verify that the placement can support the system timing requirements.
The required bus frequency and the maximum flight time propagation delay on the PCB determine
the maximum network length between the bus agents. The minimum network length is independent
of the required bus frequency. Table 3-2 and Table 3-3 assume values for CLKSKEW and
CLKJITTER - parameters that are controlled by the system designer. To reduce system clock skew to
a minimum, clock buffers that allow their outputs to be tied together are recommended. Intel
strongly recommends running analog simulations to ensure that each design has adequate noise and
timing margin.

3.2.4.2

Layout and Route Board
Route the board satisfying the estimated space and timing requirements. Also stay within the
solution space set from the pre-layout sweeps. Estimate the printed circuit board parameters from
the placement and other information including the following general guidelines:

• Distribute VTT with a power plane or a partial power plane. If this cannot be accomplished,

use as wide a trace as possible and route the VTT trace with the same topology as the AGTL+
traces.

• Keep the overall length of the bus as short as possible (but do not forget minimum componentto-component distances to meet hold times).

• Plan to minimize cross-talk with the following guidelines developed for the example topology
given (signal spacing recommendations were based on fully coupled simulations - spacing
may be decreased based upon the amount of coupled length):
— Use a spacing to line width to dielectric thickness ratio of at least 3:1:2. If εr = 4.5, this
should limit coupling to 3.4%.
— Minimize the dielectric process variation used in the PCB fabrication.
— Eliminate parallel traces between layers not separated by a power or ground plane.
Figure 3-3 contains the trace width:space ratios assumed for this topology. The cross-talk cases
considered in this guideline involve three types: Intragroup AGTL+, Intergroup AGTL+, and
AGTL+ to non-AGTL+. Intra-group AGTL+ cross-talk involves interference between AGTL+
signals within the same group (See Section 3.4, “More Details and Insight” on page 3-19 for a
description of the different AGTL+ group types). Intergroup AGTL+ cross-talk involves

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interference from AGTL+ signals in a particular group to AGTL+ signals in a different group. An
example of AGTL+ to non-AGTL+ cross-talk is when CMOS and AGTL+ signals interfere with
each other.
Table 3-4. Trace Width Space Guidelines
Cross-talk Type
Intragroup AGTL+ (same group AGTL+)

Trace Width:Space Ratio
5:10 or 6:12

Intergroup AGTL+ (different group AGTL+)

5:15 or 6:18

AGTL+ to non-AGTL+

5:20 or 6:24

The spacing between the various bus agents causes variations in trunk impedance and stub
locations. These variations cause reflections that can cause constructive or destructive interference
at the receivers. A reduction of noise may be obtained by a minimum spacing between the agents.
Unfortunately, tighter spacing results in reduced component placement options and lower hold
margins. Therefore, adjusting the inter-agent spacing may be one way to change the network’s
noise margin, but mechanical constraints often limit the usefulness of this technique. Always be
sure to validate signal quality after making any changes in agent locations or changes to inter-agent
spacing.
There are six AGTL+ signals that can be driven by more than one agent simultaneously. These
signals may require more attention during the layout and validation portions of the design. When a
signal is asserted (driven low) by two or more agents on the same clock edge, the two falling edge
wave fronts will meet at some point on the bus and can sum to form a negative voltage. The ringback from this negative voltage can easily cross into the overdrive region. The signals are AERR#,
BERR#, BINIT#, BNR#, HIT#, and HITM#.
This document addresses AGTL+ layout for both 1 and 2-way 133 MHz/100 MHz processor/
Intel® 820 chipset systems. Power distribution and chassis requirements for cooling, connector
location, memory location, etc., may constrain the system topology and component placement
location; therefore, constraining the board routing. These issues are not directly addressed in this
document. Section 1.2, “References” on page 1-2 contains a listing of several documents that
address some of these issues.

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3.2.4.3

Host Clock Routing
Host clock nets should be routed as point-to-point connections through a series resistor placed as
close to the output pins of the clock driver as possible. The value of the series resistor is dependent
on the clock driver characteristic impedance. However, a value of 33 Ω is a good starting point.
Table 3-5 provides the trace length recommendations for this topology. “H” indicates the length of
the host clock trace starting from the clock driver output pin and ending at the SC242 connector
BCLK pin. Note that the clock route from the clock driver to the Intel 82820 MCH will require an
additional trace length of approximately 4.6” to compensate for the additional propagation delay
along the processor host clock path (SC242 connector plus processor cartridge trace). This value of
4.6” assumes a propagation speed of 180 ps/in.

Table 3-5. Host Clock Routing
Clock Net

3.2.4.4

Trace length

Clock driver to SC242 connector

H

Clock driver to Intel 82820 MCH

H + (clock delay from the processor edge to core) +
connector delay

APIC Data Bus Routing
Intel recommends using the in-line topology shown in Figure 3-1 and Figure 3-2 for the APIC Data
signals, PICD[1:0]. For dual-processor systems, the network should be dual-end terminated with
330 Ω resistors. The combined routing lengths of L1 plus L2 should be between 0.0” and 12.0”.

Figure 3-1. PICD[1,0] Uni-Processor Topology
2.5V
SC242

150 Ω
Intel® 820
Chipset

L1 < 8"
PICD[1,0]
Z0=60 Ω ±15%.

L(1):

Figure 3-2. PICD[1,0] Dual-Processor Topology
2.5V

2.5V

330 Ω

SC242

SC242
L1

Intel ® 820
Chipset:
ICH

330 Ω

L2

L1 + L2 < 12"
PICD[1,0]

L(1):

3-12

Z0=60 Ω ±15%.

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Advanced System Bus Design

3.2.5

Post-Layout Simulation
Following layout, extract the interconnect information for the board from the CAD layout tools.
Run simulations to verify that the layout meets timing and noise requirements. A small amount of
“tuning” may be required; experience at Intel has shown that sensitivity analysis dramatically
reduces the amount of tuning required. The post layout simulations should take into account the
expected variation for all interconnect parameters.
Intel specifies signal integrity at the device pads and therefore recommends running simulations at
the device pads for signal quality. However, Intel specifies core timings at the device pins, so
simulation results at the device pins should be used later to correlate simulation performance
against actual system measurements.

3.2.5.1

Intersymbol Interference
Intersymbol Interference (ISI) refers to the distortion or change in the waveform shape caused by
the voltage and transient energy on the network when the driver begins its next transition.
Intersymbol Interference (ISI) occurs when transitions in the current cycle interfere with transitions
in subsequent cycles. ISI can occur when the line is driven high, low, and then high in consecutive
cycles (the opposite case is also valid). When the driver drives high on the first cycle and low on
the second cycle, the signal may not settle to the minimum VOL before the next rising edge is driven.
This results in improved flight times in the third cycle. Intel performed ISI simulations for the
topology given in this section by comparing flight times for the first and third cycle. ISI effects do
not necessarily span only 3 cycles so it may be necessary to simulate beyond 3 cycles for certain
designs. After simulating and quantifying ISI effects, adjust the timing budget accordingly to take
these conditions into consideration.

3.2.5.2

Cross-Talk Analysis
AGTL+ cross-talk simulations can consider the processor core package, Intel 82820 MCH
package, and SC242 connectors as non-coupled. Treat the traces on the processor cartridge and
baseboard as fully coupled for maximum cross-talk conditions. Simulate the traces as lossless for
worst case cross-talk and lossy where more accuracy is needed. Evaluate both odd and even mode
cross-talk conditions.
AGTL+ Cross-talk simulation involves the following cases:

• Intra-group AGTL+ cross-talk
• Inter-group AGTL+ cross-talk
• Non-AGTL+ to AGTL+ cross-talk
3.2.5.3

Monte Carlo Analysis
Perform a Monte Carlo analysis on the extracted baseboard. Vary all parameters recommended for
the pre-layout Monte Carlo analysis within the region that they are expected to vary. The range for
some parameters will be reduced compared to the pre-layout simulations. For example, baseboard
lengths L1 through L7 should no longer vary across the full min and max range on the final
baseboard design. Instead, baseboard lengths should now have an actual route, with a length
tolerance specified by the baseboard fabrication manufacturer.

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3.2.6

Validation
Build systems and validate the design and simulation assumptions.

3.2.6.1

Measurements
Note that the AGTL+ specification for signal quality is at the pad of the component. The expected
method of determining the signal quality is to run analog simulations for the pin and the pad. Then
correlate the simulations at the pin against actual system measurements at the pin. Good correlation
at the pin leads to confidence that the simulation at the pad is accurate. Controlling the temperature
and voltage to correspond to the I/O buffer model extremes should enhance the correlation between
simulations and the actual system.

3.2.6.2

Flight Time Simulation
As defined in Section 3.1, “Terminology and Definitions” on page 3-1, flight time is the time
difference between a signal crossing VREF at the input pin of the receiver, and the output pin of the
driver crossing VREF were it driving a test load. The timings in the tables and topologies discussed
in this guideline assume the actual system load is 50 Ω and is equal to the test load. While the DC
loading of the AGTL+ bus in a DP mode is closer to 25 Ω, AC loading is approximately 29 Ω since
the driver effectively “sees” a 56 Ω termination resistor in parallel with a 60 Ω transmission line on
the cartridge.

Figure 3-3. Test Load vs. Actual System Load
VTT
I/O Buffer
Driver
Pad

Vcc

Driver
Pin

D SETQ

CLK

RTEST Test Load

CLR Q

TREF
TCO

I/O Buffer
Driver
Pad

Vcc
CLK

Actual
System
Load

VTT
RTT
Receiver
Pin

D SETQ
CLR Q

TFLIGHTSYSTEM

Figure 3-3 above shows the different configurations for TCO testing and flight time simulation. The
flip-flop represents the logic input and driver stage of a typical AGTL+ I/O buffer. TCO timings are
specified at the driver pin output. TFLIGHT-SYSTEM is usually reported by a simulation tool as the
time from the driver pad starting its transition to the time when the receiver’s input pin sees a valid
data input. Since both timing numbers (TCO and TFLIGHT-SYSTEM) include propagation time from
the pad to the pin, it is necessary to subtract this time (TREF) from the reported flight time to avoid

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double counting. TREF is defined as the time that it takes for the driver output pin to reach the
measurement voltage, VREF, starting from the beginning of the driver transition at the pad. TREF
must be generated using the same test load for TCO. Intel provides this timing value in the AGTL+
I/O buffer models.
In this manner, the following valid delay equation is satisfied:
Equation 3-5. Valid Delay Equation
Valid Delay = TCO + TFLIGHT-SYS - TREF = TCO-MEASURED + TFLIGHT-MEASURED

This valid delay equation is the total time from when the driver sees a valid clock pulse to the time
when the receiver sees a valid data input.

3.2.6.3

Flight Time Hardware Validation
When a measurement is made on the actual system, TCO and flight time do not need TREF
correction since these are the actual numbers. These measurements include all of the effects
pertaining to the driver-system interface and the same is true for the TCO. Therefore the addition of
the measured TCO and the measured flight time must be equal to the valid delay calculated above.

3.3

Theory

3.3.1

AGTL+
AGTL+ is the electrical bus technology used for the processor bus. This is an incident wave
switching, open-drain bus with external pull-up resistors that provide both the high logic level and
termination at each load. The processor AGTL+ drivers contain a full-cycle active pull-up device
to improve system timings. The AGTL+ specification defines:

•
•
•
•
•
•
•
•
•
•
•

Termination voltage (VTT).
Receiver reference voltage (VREF) as a function of termination voltage (VTT).
processor termination resistance (RTT).
Input low voltage (VIL).
Input high voltage (VIH).
NMOS on resistance (RONN).
PMOS on resistance (RONP).
Edge rate specifications.
Ringback specifications.
Overshoot/Undershoot specifications.
Settling Limit.

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3.3.2

Timing Requirements
The system timing for AGTL+ is dependent on many things. Each of the following elements
combine to determine the maximum and minimum frequency the AGTL+ bus can support:

• The range of timings for each of the agents in the system.
— Clock to output [TCO]. (Note that the system load is likely to be different from the
“specification” load therefore the TCO observed in the system might not be the same as the
TCO from the specification.)
— The minimum required setup time to clock [TSU_MIN] for each receiving agent.

• The range of flight time between each component. This includes:
— The velocity of propagation for the loaded printed circuit board [SEFF].
— The board loading impact on the effective TCO in the system.

• The amount of skew and jitter in the system clock generation and distribution.
• Changes in flight time due to cross-talk, noise, and other effects.

3.3.3

Cross-talk Theory
AGTL+ signals swing across a smaller voltage range and have a correspondingly smaller noise
margin than technologies that have traditionally been used in personal computer designs. This
requires that designers using AGTL+ be more aware of cross-talk than they may have been in past
designs.
Cross-talk is caused through capacitive and inductive coupling between networks. Cross-talk
appears as both backward cross-talk and as forward cross-talk. Backward cross-talk creates an
induced signal on a victim network that propagates in a direction opposite that of the aggressor’s
signal. Forward cross-talk creates a signal that propagates in the same direction as the aggressor’s
signal. On the AGTL+ bus, a driver on the aggressor network is not at the end of the network;
therefore it sends signals in both directions on the aggressor’s network. Figure 3-4 shows a driver
on the aggressor network and a receiver on the victim network that are not at the ends of the
network. The signal propagating in each direction causes cross-talk on the victim network.

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Figure 3-4. Aggressor and Victim Networks

Zo

Zo

Victim

Zo

Zo
Signal propagates in both
directions on aggressor line.

Aggressor

Figure 3-5. Transmission Line Geometry: (A) Microstrip (B) Stripline
Signal Lines
Signal Lines
W
Dielectric, εr

Dielectric, εr

Sp

t

AC Ground Plane
A. Microstrip

B. Stripline
li

d

Additional aggressors are possible in the z-direction, if adjacent signal layers are not routed in
mutually perpendicular directions. Because cross-talk-coupling coefficients decrease rapidly with
increasing separation, it is rarely necessary to consider aggressors that are at least five line widths
separated from the victim. The maximum cross-talk occurs when all the aggressors are switching in
the same direction at the same time.
There is cross-talk internal to the IC packages, which can also affect the signal quality.
Backward cross-talk is present in both stripline and microstrip geometry’s (see Figure 3-5). A way
to remember which geometry is stripline and which is microstrip is that a stripline geometry
requires stripping a layer away to see the signal lines. The backward coupled amplitude is
proportional to the backward cross-talk coefficient, the aggressor’s signal amplitude, and the
coupled length of the network up to a maximum that is dependent on the rise/fall time of the
aggressor’s signal. Backward cross-talk reaches a maximum (and remains constant) when the

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Advanced System Bus Design

propagation time on the coupled network length exceeds one half of the rise time of the aggressor’s
signal. Assuming the ideal ramp on the aggressor from 0% to 100% voltage swing, and the fall
time on an unloaded coupled network, then:
1--× F allTime
2
LengthforMaxBackwardCrosstalk = -----------------------------------------------------------------------BoardDelayPerUnitLength

An example calculation follows when the fast corner fall time is 3 V/ns and board delay is
175 ps/inch (2.1 ns/foot):
Fall time = 1.5 V÷3 V/ns = 0.5 ns
Length for Max Backward Cross-talk
= ½ * 0.5 ns * 1000 ps/ns ÷175 ps/in
= 1.43 inches
Agents on the AGTL+ bus drive signals in each direction on the network. This causes backward
cross-talk from segments on two sides of a driver. The pulses from the backward cross-talk travel
toward each other and meet and add at certain moments and positions on the bus. This can cause
the voltage (noise) from cross-talk to double.

3.3.3.1

Potential Termination Cross-Talk Problems
The use of commonly used “pull-up” resistor networks for AGTL+ termination may not be
suitable. These networks have a common power or ground pin at the extreme end of the package,
shared by 13 to 19 resistors (for 14- and 20-pin components). These packages generally have too
much inductance to maintain the voltage/current needed at each resistive load. Intel recommends
using discrete resistors, resistor networks with separate power/ground pins for each resistor, or
working with a resistor network vendor to obtain resistor networks that have acceptable
characteristics.

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3.4

More Details and Insight

3.4.1

Textbook Timing Equations
The “textbook” equations used to calculate the propagation rate of a PCB are the basis for
spreadsheet calculations for timing margin based on the component parameters. These equations
are:

Equation 3-6. Intrinsic Impedance

Z0 =

L0
C
0 (Ω)

Equation 3-7. Stripline Intrinsic Propagation Speed
S0_ STRIPLINE = 1017
.
* εr

(ns/ft)

Equation 3-8. Microstrip Intrinsic Propagation Speed
S0_ MICROSTRIP = 1017
.
* 0.475 * εr + 0.67
(ns/ft)

Equation 3-9. Effective Propagation Speed
C
S EFF = S0∗ 1 + D
C
0

(ns/ft)

Equation 3-10. Effective Impedance
Z

EFF

=

Z

0
C

1+ D
C
0

(Ω)

Equation 3-11. Distributed Trace Capacitance
S
C = 0
0 Z
0 (pF/ft)

Equation 3-12. Distributed Trace Inductance

L0 = 12∗ Z0 ∗ S0

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(nH/ft)

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Advanced System Bus Design

Symbols for Equation 3-5 through Equation 3-12:

• S0 is the speed of the signal on an unloaded PCB in ns/ft. This is referred to as the board
propagation constant.

• S0 MICROSTRIP and S0 STRIPLINE refer to the speed of the signal on an unloaded microstrip or
stripline trace on the PCB in ns/ft.

• Z0 is the intrinsic impedance of the line in Ω and is a function of the dielectric constant (εr), the
line width, line height and line space from the plane(s). The equations for Z0 are not included
in this document. See the MECL System Design Handbook by William R. Blood, Jr. for these
equations.

• C0 is the distributed trace capacitance of the network in pF/ft.
• L0 is the distributed trace inductance of the network in nH/ft.
• CD is the sum of the capacitance of all devices and stubs divided by the length of the network’s

trunk, not including the portion connecting the end agents to the termination resistors in pF/ft.

• SEFF and ZEFF are the effective propagation constant and impedance of the PCB when the
board is “loaded” with the components.

3.4.2

Effective Impedance and Tolerance/Variation
The impedance of the PCB needs to be controlled when the PCB is fabricated. The method of
specifying control of the impedance needs to be determined to best suit each situation. Using
stripline transmission lines (where the trace is between two reference planes) is likely to give better
results than microstrip (where the trace is on an external layer using an adjacent plane for reference
with solder mask and air on the other side of the trace). This is in part due to the difficulty of
precise control of the dielectric constant of the solder mask, and the difficulty in limiting the plated
thickness of microstrip conductors, which can substantially increase cross-talk.
The effective line impedance (ZEFF) is recommended to be 60 Ω ±15%, where ZEFF is defined by
Equation 3-10.

3.4.3

Power/Reference Planes, PCB Stackup, and High
Frequency Decoupling

3.4.3.1

Power Distribution
Designs using the Pentium III processor require several different voltages. The following
paragraphs describe some of the impact of two common methods used to distribute the required
voltages. Refer to the Flexible Motherboard Power Distribution Guidelines for more information
on power distribution.
The most conservative method of distributing these voltages is for each of them to have a dedicated
plane. If any of these planes are used as an “AC ground” reference for traces to control trace
impedance on the board, then the plane needs to be AC coupled to the system ground plane. This
method may require more total layers in the PCB than other methods. A 1-ounce/ft2 thick copper is
recommended for all power and reference planes.
A second method of power distribution is to use partial planes in the immediate area needing the
power, and to place these planes on a routing layer on an as-needed basis. These planes still need to
be decoupled to ground to ensure stable voltages for the components being supplied. This method
has the disadvantage of reducing area that can be used to route traces. These partial planes may also

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change the impedance of adjacent trace layers. (For instance, the impedance calculations may have
been done for microstrip geometry, and adding a partial plane on the other side of the trace layer
may turn the microstrip into a stripline.)

3.4.3.2

Reference Planes and PCB Stackup
It is strongly recommended that baseboard stackup be arranged such that AGTL+ signals are
referenced to a ground (VSS) plane, and that the AGTL+ signals do not traverse multiple signal
layers. Deviating from either guideline can create discontinuities in the signal’s return path that can
lead to large SSO effects that degrade timing and noise margin. Designing an AGTL+ platform
incorporating discontinuities will expose the platform to a risk that is very hard to predict in prelayout simulation. Figure 3-6 shows the ideal case where a particular signal is routed entirely
within the same signal layer, with a ground layer as the single reference plane.

Figure 3-6. One Signal Layer and One Reference Plane
Signal Layer A
Ground Plane
1lay 1ref plane vsd

When it is not possible to route the entire AGTL+ signal on a single VSS referenced layer, there
are methods to reduce the effects of layer switches. The best alternative is to allow the signals to
change layers while staying referenced to the same plane (see Figure 3-7). Figure 3-8 shows
another method of minimizing layer switch discontinuities, but may be less effective than
Figure 3-7. In this case, the signal still references the same type of reference plane (ground). In
such a case, it is important to stitch (i.e., connect) the two ground planes together with vias in the
vicinity of the signal transition via.
Figure 3-7. Layer Switch with One Reference Plane
Signal Layer A
Ground Plane
Signal Layer B
l

1 f l

d

Figure 3-8. Layer Switch with Multiple Reference Planes (same type)
Signal Layer A
Ground Plane
Layer
Layer
Ground Plane
Signal Layer B
l

Intel®820 Chipset Design Guide

M lt

f l

d

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Advanced System Bus Design

When routing and stackup constraints require that an AGTL+ signal reference VCC or multiple
planes, special care must be given to minimize the SSO impact to timing and noise margin. The
best method of reducing adverse effects is to add high-frequency decoupling wherever the
transitions occur, as shown in Figure 3-9 and Figure 3-10. Such decoupling should, again, be in the
vicinity of the signal transition via and use capacitors with minimal effective series resistance
(ESR) and effective series inductance (ESL). When placing the caps it is recommended to space
the VSS and VCC vias as close as possible and/or use dual vias since the via inductance may
sometimes be higher than the actual capacitor inductance.
Figure 3-9. Layer Switch with Multiple Reference Planes
Signal Layer A
Power Plane
Layer
Layer
Ground Plane
Signal Layer B

Figure 3-10. One Layer with Multiple Reference Planes
Signal Layer A

Ground

Power

1l

3.4.3.3

M lt

f l

d

High Frequency Decoupling
This section contains several high frequency decoupling recommendations that will improve the
return path for an AGTL+ signal. These design recommendations will very likely reduce the
amount of SSO effects.
Just as layer switching and multiple reference planes can create discontinuities in an AGTL+ signal
return path, discontinuities may also occur when a signal transitions between the baseboard and
cartridge. Therefore, providing adequate high-frequency decoupling across VCCCORE and ground
at the SC242 connector interface on the baseboard will minimize the discontinuity in the signal’s
reference plane at this junction. Note that these additional high-frequency decoupling capacitors
are in addition to the high-frequency decoupling already on the processor.
Transmission line geometry also influences the return path of the reference plane. The following
are decoupling recommendations that take this into consideration:

• A signal that transitions from a stripline to another stripline should have close proximity
•
•

3-22

decoupling between all four reference planes.
A signal that transitions from a stripline to a microstrip (or vice versa) should have close
proximity decoupling between the three reference planes.
A signal that transitions from a stripline or microstrip through vias or pins to a component
(Intel 82820 MCH, etc.) should have close proximity decoupling across all involved reference
planes to ground for the device.

Intel®820 Chipset Design Guide

Advanced System Bus Design

3.4.3.4

SC242 Connector
Intel studies indicate that the use of thermal reliefs on the connector pin layout pattern (especially
ground pins) should be minimized. Such reliefs (cartwheels or wagon-wheels) increase the net
ground inductance and reduce the integrity of the ground plane to which many signals are
referenced. Increased ground inductance has been shown to aggravate SSO effects. Also, the antipad diameters (clearance holes in the planes) for the signal pins should be minimized since large
anti-pads also reduce the integrity of the ground plane and increase inductance.
Some additional layout and EMI-reduction guidelines regarding the SC242 connector follow:

• Extend power/ground planes up to the SC242 connector pins.
• Extend the reference planes for AGTL+ and other controlled-impedance signals up to the
SC242 connector pins.

• Minimize or remove thermal reliefs on power/ground pins.
• Route VTT power with the widest signal trace or mini-plane as possible. Place decoupling caps
across VTT and ground in the vicinity of the connector pins.

• Use a ground plane under the principal component side of the baseboard (and secondary side if
it contains active components).

• Distribute decoupling capacitors across power and ground pins evenly around the connector
(less than 0.5 inch spacing) on the primary and secondary sides.

• Minimize serpentine traces on outer layers.

3.4.4

Clock Routing
Analog simulations are required to ensure clock net signal quality and skew is acceptable. The
system clock skew must be kept to a minimum (The calculations and simulations for the example
topology given in this document have a total clock skew of 200 ps and 150 ps of clock jitter). For a
given design, the clock distribution system, including the clock components, must be evaluated to
ensure these same values are valid assumptions. Each processor’s datasheet specifies the clock
signal quality requirements. To help meet these specifications, follow these general guidelines:

• Tie clock driver outputs if clock buffer supports this mode of operation.
• Match the electrical length and type of traces on the PCB (microstrip and stripline may have
different propagation velocities).

• Maintain consistent impedance for the clock traces.
— Minimize the number of vias in each trace.
— Minimize the number of different trace layers used to route the clocks.
— Keep other traces away from clock traces.

• Lump the loads at the end of the trace if multiple components are to be supported by a single
clock output.

• Have equal loads at the end of each network.
The ideal way to route each clock trace is on the same single inner layer, next to a ground plane,
isolated from other traces, with the same total trace length, to the same type of single load, with an
equal length ground trace parallel to it, and driven by a zero skew clock driver. When deviations
from ideal are required, going from a single layer to a pair of layers adjacent to power/ground
planes would be a good compromise. The fewer number of layers the clocks are routed on, the
smaller the impedance difference between each trace is likely to be. Maintaining an equal length

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Advanced System Bus Design

and parallel ground trace for the total length of each clock ensures a low inductance ground return
and produces the minimum current path loop area. (The parallel ground trace will have lower
inductance than the ground plane because of the mutual inductance of the current in the clock
trace.)

3.5

Definitions of Flight Time Measurements/
Corrections and Signal Quality
Acceptable signal quality must be maintained over all operating conditions to ensure reliable
operation. Signal Quality is defined by four parameters: Overshoot, Undershoot, Settling Limit,
and Ringback. Timings are measured at the pins of the driver and receiver, while signal integrity is
observed at the receiver chip pad. When signal integrity at the pad violates the following guidelines
and adjustments need to be made to flight time, the adjusted flight time obtained at the chip pad can
be assumed to have been observed at the package pin, usually with a small timing error penalty.

3.5.1

VREF Guardband
To account for noise sources that may affect the way an AGTL+ signal becomes valid at a receiver,
VREF is shifted by ∆VREF for measuring minimum and maximum flight times. The VREF
Guardband region is bounded by VREF-∆VREF and VREF+∆VREF. ∆VREF has a value of 100 mV,
which accounts for the following noise sources:

• Motherboard coupling
• VTT noise
• VREF noise

3.5.2

Ringback Levels
The example topology covered in this guideline assumes ringback tolerance allowed to within
200 mV of 2/3 VTT. Since VTT is specified with approximate total ±11% tolerance, this implies a
2/3 VTT (VREF) range from approximately 0.89 V to 1.11 V. This places the absolute ringback
limits at:

• 1.3 V (1.1 V + 200 mV) for rising edge ringback
• 0.69 V (0.89 V – 200 mV) for falling edge ringback
A violation of these ringback limits requires flight time correction as documented in the Intel®
Pentium® II Processor Developer’s Manual.

3.5.3

Overdrive Region
The overdrive region is the voltage range, at a receiver, from VREF to VREF + 200 mV for a low-tohigh going signal and VREF to VREF - 200 mV for a high-to-low going signal. The overdrive
regions encompass the VREF Guardband. So, when VREF is shifted by ∆VREF for timing
measurements, the overdrive region does not shift by ∆VREF. Figure 3-11 depicts this relationship.
Corrections for edge rate and ringback are documented in the Intel® Pentium® II Processor
Developer’s Manual. However, there is an exception to the documented correction method. The
Intel®Pentium® II Processor Developer’s Manual states that extrapolations should be made from
the last crossing of the overdrive region back to VREF. Simulations performed on this topology

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should extrapolate back to the appropriate VREF Guardband boundary, and not VREF. So, for
maximum rising edge correction, extrapolate back to VREF + ∆VREF. For maximum falling edge
corrections, extrapolate back to VREF - ∆VREF.
Figure 3-11. Overdrive Region and VREF Guardband

VREF+ 200 mV
VREF+ 100 mV
∆VREF
VREFGuardband
VREF ∆ V
REF
VREF- 100 mV
VREF- 200 mV

3.5.4

Overdrive Region (200 mV)
Overdrive Region (200 mV)

Flight Time Definition and Measurement
Timing measurements consist of minimum and maximum flight times to take into account that
devices can turn on or off anywhere in a VREF Guardband region. This region is bounded by
VREF-∆VREF and VREF+∆VREF. The minimum flight time for a rising edge is measured from the
time the driver crosses VREF when terminated to a test load, to the time when the signal first
crosses VREF-∆VREF at the receiver (see Figure 3-12). Maximum flight time is measured to the
point where the signal first crosses VREF+∆VREF, assuming that ringback, edge rate, and
monotonicity criteria are met. Similarly, minimum flight time measurements for a falling edge are
taken at the VREF+∆VREF crossing and maximum flight time is taken at the VREF-∆VREF crossing.

Figure 3-12. Rising Edge Flight Time Measurement

Receiver Pin
Driver Pin into
Test Load
VREF + 200 mV
VREF + 100 mV
VREF ∆V
REF
VREF - 100 mV

∆VREF

Overdrive Regio
VREF Guardband

Tflight-max
Tflight-min

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3.6

Conclusion
AGTL+ routing requires a significant amount of effort. Planning ahead and leaving the necessary
time available for correctly designing a board layout will provide the designer with the best chance
of avoiding the more difficult task of debugging inconsistent failures caused by poor signal
integrity. Intel recommends planning a layout schedule that allows time for each of the tasks
outlined in this document.

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4
Clocking

This page is intentionally left blank.

Clocking

4

Clocking
4.1

Clock Generation
There are two clock generator components required in an Intel® 820 chipset based system. The
Direct Rambus* Clock Generator (DRCG) generates clock for the Direct Rambus* interface while
the CK133 component generates clocks for the rest of the system. Clock synthesizers that meet the
Intel CK98 Clock Specification are suitable for an Intel® 820 chipset based system. The CK133
generates the clocks listed in Table 4-1.

Table 4-1. Intel® 820 Chipset Platform System Clocks
Number

Name on
CK133

Used for

Routed to
2 Processors

4

3

8

4

CPUCLK[0-3]

APIC[0-2]

PCICLK[1-7,F]

3V66[0-3]

2

REF[0-1]

1

48 MHz

2

CPU_DIV2[0-1]

System Bus Clock

Name on
Receiver

Voltage

CLK

MCH

HCLKIN

ITP

BCLK

2 Processors

PICCLK

ICH

APICCLK

PCI Bus Clock

5 PCI
Devices

CLK

PCI, LPC, FWH Flash
BIOS Bus Clock

ICH

PCICLK

FWH Flash BIOS
Interface Clock

FWH Flash
BIOS

CLK

LPC Interface Clock

LPC

CLK

Hub Interface/AGP Bus
Clock

MCH

CLK66

Hub Interface Clock

ICH

CLK66

AGP Bus Clock

AGP device/
slot

CLK

APIC Bus Clock

Frequency

100/133 MHz

2.5V

33 MHz

2.5V

33 MHz

3.3V

66 MHz

3.3V

Unused

N/A

N/A

Internal ICH Logic

ICH

CLK14

Internal Super I/O Logic

Super I/O

Vendor
Specific

14 MHz

3.3V

USB

ICH

CLK48

48 MHz

3.3V

50/66 MHz

2.5V

DRCG Reference Clock

DRCG

REFCLK

Unused

N/A

N/A

The CK133 is a mixed voltage component. Some of the output clocks are 3.3V and some of the
output clock are 2.5V. As a result, the CK133 device requires both 3.3V and 2.5V. These power
supplies should be a clean as possible. Noise in the power delivery system for the clock driver can
cause noise on the clock lines.
The MCH uses the same clock for hub interface and AGP. It is important that the
hub interface/AGP clocks are routed to ensure the skew requirements are met between:

• The MCH hub interface/AGP clock and the AGP connector (or device)

Intel®820 Chipset Design Guide

4-1

Clocking

• The MCH hub interface/AGP clock and the ICH hub interface clock.
The DRCG reference clock operates at one-half the CPU clock frequency. It is an input into the
DRCG and is used to generate the Direct RDRAM “Clock to Master” differential pair (CTM,
CTM#).
The DRCG generates one pair of differential Direct RDRAM Clocks (CTM, CTM#) from the
reference clock generated by the CK133. In addition, the DRCG uses phase information provided
by the MCH to phase align the direct RDRAM clock with the CPU clocks. This phase alignment
information is provided to the DRCG via the SYNCLKN and PCLKM pins.
Figure 4-1. Intel® 820 Chipset Platform Clock Distribution
A
B
CPUCLK
APIC
CPUCLK
APIC
CPUCLK
3V66

Processor
CLK
PICCLK

C
D

Processor
CLK
PICCLK

RDRAM
RCLK TCLK

MCH
CTM
CFM
HCLKIN
F CLK66 PHASEINFO

RDRAM
RCLK TCLK

RDRAM
RCLK TCLK

RDRAM

TERM

RCLK TCLK

E
CPU_DIV2
3V66
APIC
PCICLK*
3V66
CK133
REF
48Hz

P
G APICCLK
H PCICLK
I
CLK66
J CLK14
K CLK48

ICH

CLK

AGP
CONNECTOR

N CLK

FWH
Flash BIOS

M CLK

PCICLK
PCICLK
PCICLK

PHASEINFO
Q REFCLK DRCG

LPC
L

L

L

L

CLK
PCI SLOTS

CLK
PCI SLOTS

CLK
PCI SLOTS

CLK
PCI SLOTS

* The free-running PCI clock should be connected to the ICH.

4-2

Intel®820 Chipset Design Guide

Clocking

Table 4-2. Intel® 820 Chipset Platform Clock Skews
Skew
Clock Symbols
See Figure 4-1

A leads C,

Relationship

Pin-to-Pin
(ps)

Board
(ps)

Total
(ps)

Notes

Min

Max

Min

Max

Min

Max

-175

+175

-125

+125

-300

+300

1, 7

SC242 HCLK to SC242
HCLK (DP ONLY)
And

A leads E

SC242 HCLK to MCH

(or C leads E)

HCLK (DP ONLY)

A leads E

SC242 HCLK to MCH
HCLK (UP ONLY)

0

0

-125

+125

-125

+125

2, 3, 7

P leads F

MCH CLK66 to AGP
graphics device
AGPCLK

0

0

-125

+125

-125

+125

4, 8

PCICLK to PCICLK

-500

+500

-1500

+1500

-2000

+2000

+1500

+4000

-500

+500

+1000

+4500

L leads another L
(or L leads H)
I leads H

ICH CLK66 leads ICH
PCICLK

F leads I

ICH CLK66 to MCH
CLK66

-250

250

-125

+125

-375

+375

8

Worst case skew
between H, L, M
and N

Worst case FWHCLK,
LPCCLK, PCICLK

-500

+500

-1500

+1500

-2000

+2000

5

-250

+250

-125

+125

-375

+375

6

B leads D,

Processor PICCLK leads
Processor PICCLK
And

B leads G

Processor PICCLK leads
ICH APICCLK

NOTES:
1. DP Only
2. UP: MCH and CPU clock drivers are tied together to eliminate pin-to-pin skew. –175 and +175 pin-to-pin
skew only apply to DP.
3. UP Only
4. Clock drivers tied together to eliminate pin-to-pin skew.
5. The skew between any PCICLK clocks on any two inputs in the system.
6. The skew between any APIC clocks on any two inputs in the system.
7. If SSC is enabled, an additional ±40ps must is added to the pin-to-pin skew
8. If SSC is enabled, an additional ±60ps must is added to the pin-to-pin skew

Intel®820 Chipset Design Guide

4-3

Clocking

Figure 4-2 shows the Intel® 820 chipset clock length routing guidelines.
Figure 4-2. Intel® 820 Chipset Clock Routing Guidelines1,2
Y
CPUCLK to SC242

Y

5.3"

CPUCLK to MCH

±0"

Note: Tie CPUCLK for the MCH to CPUCLK to the SC242 to eliminate pin-to-pin skew.

3V66 Clock for
AGP Slot

Z

PCI Clock for
PCI Slots

Z

3V66 Clock for
MCH and ICH

Z

4"

Z

4"

Z

4"

1.5"

±TBD3

PCI Clock for ICH

PCI Clock for On-Board
Devices (excluding ICH)

±0"

±0"

±TBD3

Note:
1. Tie 3V66 clock for the MCH to 3V66 clock for the AGP connector to eliminate pin-to-pin skew.
2. These calculations based on 150ps/in trace velocity.
3. The TBD value will be derived from the PCI Revision 2.2 Specification which allows for a maximum of ±2ns
clock skew.
820

4-4

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Intel®820 Chipset Design Guide

Clocking

Table 4-3. Intel® 820 Chipset Platform System Clock Cross-Reference
CK133/DRCG Pin Name

PCICLK

3V66

48 MHz

CPUCLK

CPU_div2

APIC

Clk/ClkB1
CFM/CFM#

1,2

Component

Pin Name

PCI Slot

CLK

PCI Slot

CLK

PCI Slot

CLK

PCI Slot

CLK

PCI Slot

CLK

ICH

PCICLK-F

LPC Super I/O

CLK

FWH Flash BIOS

CLK

MCH

GCLKIN

ICH

CLK66

AGP Connector (on-board device)

CLK

ICH

CLK48

CPU

BCLK

CPU

BCLK

MCH

HCLKIN

DRCG

Refclk

CPU

PICCLK

CPU

PICCLK

ICH

APICCLK

RDRAMs
MCH

CTM/CTM#

RDRAMs

PclkM

MCH

HCLKOUT

SynclkN

MCH

RCLKOUT

NOTES:
1. Differential Clocking Pair
2. CFM/CFM# driven by MCH

Intel®820 Chipset Design Guide

4-5

Clocking

4.2

Component Placement and Interconnection Layout
Requirements
Detailed explanation of layout requirements for each interconnections are provided in the
following sections:

•
•
•
•

4.2.1

Crystal to CK133
CK133 to DRCG
MCH to DRCG
DRCG to RDRAM channel

14.318 MHz Crystal to CK133
The distance between the crystal and the CK133 should be minimized. The maximum trace length
is 500 mils.

4.2.2

CK133 to DRCG
• CPU_div2
• VDDIR – Used as a reference for 2.5V signaling

Figure 4-3. CK133 to DRCG Routing Diagram
6 mils

6 mils

Ground

6 mils

VddiR

6 mils

6 mils
CPU_div2

Ground

6 mils

6 mils

6 mils

Ground

6 mils

1.4 mils

4.5 mils

Ground/Power Plane

1.4 mils

VddIR and CPU_div2 must be routed as shown in Figure 4-3. Note that the VddiR pin can be
connected directly to 2.5V near the DRCG if the 2.5V plane extends near the DRCG. However, if a
2.5V trace must be used, it should originate at the CK133 and be routed as shown.

4-6

Intel®820 Chipset Design Guide

Clocking

4.2.3

MCH to DRCG
• PclkM
• PclkN
• VddIPD

Figure 4-4. MCH to DRCG Routing Diagram
6 mils

6 mils

Ground

6 mils

VddiPD

6 mils

6 mils

Ground

6 mils

Hclkout

6 mils

6 mils

6 mils

Rclkout

6 mils

Ground

6 mils

1.4 mils

4.5 mils

1.4 mils

Ground/Power Plane

The Hclkout, Rclkout and VddiPD should be routed as shown in Figure 4-4. Note that the VddiPD
pin can be connected directly to 1.8V near the DRCG if the 1.8V plane extends near the DRCG.
However, if a 1.8V trace must be run, it should originate at the MCH and be routed as shown.
The maximum length for Hclkout and Rclkout is 6”. Additionally, Hclkout and Rclkout must be
length matched (to each other) within 50 mils. These signals should be routed on the same layer. If
the signals must switch layers, then BOTH signals should change layers together.
If VddiPD is connected to the 1.8V plane using a via (e.g., a trace is not run from the MCH),
Hclkout and Rclkout must still be routed differentially and ground isolated.
Figure 4-5. Direct Rambus* Clock Routing Dimensions
(A) = CTM/CTM# RIMM to MCH
(A) = CFM/CFM# MCH to RIMM
(B) = RIMM to RIMM for Clocks
(C) = RIMM to Termination
(D) = DRCG to RIMM

RIMM_0

RIMM_1

CFM/CFM#
CTM/CTM#

DRCG

MCH
0"-3.50"

0.4"-0.45"

0"-3"

A

B

C

Term

0"-6"
D
b

Intel®820 Chipset Design Guide

lk

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4-7

Clocking

4.2.4

DRCG to RDRAM Channel
The Direct Rambus* clock signals (CTM/CTM# and CFM/CFM#) are high-speed, impedance
matched transmission lines. The Direct Rambus* clocks begin at the end of the Direct Rambus*
channel and propagate to the controller as CTM/CTM# (see Figure 4-5), where it loops back as
CFM/CFM#. Table 4-4 lists the placement guidelines.

Table 4-4. Placement Guidelines for Motherboard Routing Lengths
Direct Rambus* Clock Routing Length Guidelines
Clock
CTM/CTM#

CFM/CFM#

From
DRCG

To

Length (inches)

Section*

Last RIMM Connector

0.000 – 6.000

D

RIMM

RIMM

0.400 – 0.450

B

1st RIMM Connector

Chipset

0.000 – 3.500

A

st

Chipset

1 RIMM Connector

0.000 – 3.500

A

RIMM

RIMM

0.400 – 0.450

B

Last RIMM Connector

Termination

0.000 – 3.000

C

NOTE: * Refer to Figure 4-5

Trace Geometry
In Sections labeled ‘A’ and ‘D’ (Figure 4-5) the clock signals (CTM/CTM# and CFM/CFM#) must
be 14 mils wide and routed as shown in Figure 4-6. For all other sections (‘B’ and ‘C’) the clock
signals must be routed with 18 mil wide traces. There must be a 22 mil ground isolation trace
routed around the clock differential pair signals. The 22 mil ground isolation traces must be
connected to ground with a via every 1”. A 6 mil gap is required between the clock signals and the
ground isolation traces. For the section labeled “A” in Figure 4-5, 0.021 inches of CLK per 1 inch
of RSL trace length must be added to compensate for the clocks faster trace velocity as described in
Section 2.6.2.1, “RSL Routing” on page 2-8. The CTM/CTM# and the CFM/CFM# differential
signal pairs must be length matched to ±2 mils in line section labeled ‘A’ and for the line sections
labeled ‘B’ using the trace length methods in Section 2.6.2.1, “RSL Routing” on page 2-8. For the
section labeled ‘D’ the trace length matching for CTM/CTM# is ±2 mils, and for the section
labeled ‘C’, ±2 mil trace length matching is required for the CFM/CFM# signals.
The CTM/CTM# signals must be ground referenced (with a continuous ground island/plane) from
the DRCG to the Last RIMM.

4.2.5

Trace Length
For the section labeled “A” in Figure 4-5 (1st RIMM to MCH and MCH to 1st RIMM),
CTM/CTM# and CFM/CFM# must be length matched within ±2 mils (exact trace length matching
is recommended). Package trace compensation (as described in Section 2.6.2.1, “RSL Routing”
on page 2-8), via compensation, and RSL signal layer alternation must also be completed on
the clock signals. Additionally, 0.021 inches of CLK per 1 inch of RSL trace length must be added
to compensate for the clocks faster trace velocity as described in Section 2.6.2.1.
For the line sections labeled ‘B’ (Figure 4-5) (RIMM to RIMM) the clock signals must be matched
within ±2 mils to the trace length of every RSL signal. Exact length matching is preferred.

4-8

Intel®820 Chipset Design Guide

Clocking

For the line section labeled ‘D’ (DRCG to Last RIMM) the CTM/CTM# must be length matched
within ±2 mils (exactly is recommended), and for the section labeled ‘C’, ±2 mil trace length
matching is required for the CFM/CFM# signals.
Note:

Total trace length matching for the entire CTM/CTM# signal trace (Sections A+B+D) and for the
CFM/CFM# signal trace (Sections A+B) is ±2 mils (exact length matching is recommended).

Figure 4-6. Differential Clock Routing Diagram (Section ‘A’, ‘C’, & ‘D’)
22 mils
Ground

14 mils

6 mils

CLOCK

14 mils

6 mils

22 mils

CLOCK#

2.1 mils

Ground

6 mils

4.5 mils

4.5 mils

1.4 mils

Ground/Power Plane
dif

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Figure 4-7. Non-Differential Clock Routing Diagram (Section ‘B’)
10 mils
Ground

18 mils
CLOCK/CLOCK#

6 mils

10 mils
Ground

6 mils

4.5 mils

2.1 mils

4.5 mils

1.4 mils

Ground/Power Plane

The CFM/CFM# differential pair signals require termination using either 27 Ω 1% or 28 Ω 2%
resistors and a 0.1 uF capacitor as shown in Figure 4-8.
Figure 4-8. Termination for Direct Rambus* Clocking Signals CFM/CFM#
CFM
R1
28 Ω 2%
or
27 Ω 1%
R2
28 Ω 2%
or
27 Ω 1%

C1
0 .1 uF

CFM#

Intel®820 Chipset Design Guide

4-9

Clocking

4.3

DRCG Impedance Matching Circuit
The external DRCG impedance matching circuit is shown in Figure 4-9. The values for the
elements are listed in Table 4-5.

Figure 4-9. DRCG Impedance Matching Network
3.3v
To 3.3V DRCG
Supply Connection

CD2

C

C

D
V
DD IR

V

DD

FBead

CD2

D

O
Z
CH

V
DD P
C

R

R

S
C

R

D

R
T
CMID2

P
C

D
DRCG

C

MID

F

S

R

P

Z
CH

R
T

V
C
DD
V IPD
DD
C

CBulk

CD
V O
DD

D

Table 4-5. External DRCG Component Values1,2
Component

Nominal Value

CD

0.1 uF

RS

39 Ohms

Series termination resistor

RP

51 Ohms

Parallel termination resistor

CMID, CMID2

0.1 uF

RT

27 Ohms

Notes
Decoupling caps to ground

Virtual ground caps
End of channel termination

CF

4 pF

Do not stuff

FBead

50 Ohms at 100 MHz

Ferrite bead

CD2

0.1 uF

Additional 3.3V decoupling caps

CBulk

10 uF

Bulk cap on device side of ferrite bead

NOTES:
1. The ferrite bead and 10 uF bulk cap combination improves jitter and helps to keep the clock noise away from
the rest of the system.
2. 0.1 uF capacitors are better than 0.01 uF or 0.001 uF caps for DRCG decoupling.

The circuit shown in Figure 4-9 is required to match the impedance of the DRCG to the 28 Ω
channel impedance. More detailed information can be found in the Direct Rambus Clock Generator
Specification.

4-10

Intel®820 Chipset Design Guide

Clocking

4.3.1

DRCG Layout Example

Figure 4-10. DRCG Layout Example
Cmid - 100pF
EMI Cap - 4pF
Do Not Stuff

CTM/CTM# route on
bottom layer

Rs - 39 Ω

(Keep trace from DRCG to
Rs VERY short)

Rp - 51 Ω

(Keep trace from Rs
to Rp short)

Decoupling Cap - 0.1uF
(Place VERY Near DRCG 3.3V Pin!)

Decoupling Cap - 0.1uF
(Place VERY Near DRCG 3.3V Pin!)

3.3V-DRCG Flood
Flood 3.3V-DRCG on the top layer
around DRCG. Flood MUST include:
4 DRCG Power Pins
4 0.1uF Capacitors
1 10uF Bulk Capacitor
1 Isolation Ferrite Bead

Decoupling Cap - 0.1uF
(Place VERY Near DRCG 3.3V Pin!)

Decoupling Cap - 0.1uF
(Place VERY Near DRCG 3.3V Pin!)

Bulk Decoupling Cap - 10uF
(Place Near DRCG)

Ferrite Bead
(L22 in Reference Schematics)

4.4

AGP Clock Routing Guidelines
The AGP clock must be routed with 20 mil spacing to all other signals and it must meet the length
guidelines in Figure 4-2.

4.5

Series Termination Resistors for CK133 Clock
Outputs
All used outputs require series termination resistors. The recommended resistor value will be
defined by simulations. The stub length to the CK133 of these resistors can be compromised to
make room for decoupling caps. The rule is to keep all resistor stubs within 250 mils of the CK133.
If routing rules allow, Rpacks can be used if power dissipation is not exceeded for the Rpack.

Intel®820 Chipset Design Guide

4-11

Clocking

4.6

Unused Outputs
All unused clock outputs must be tied to ground through a series resistor approximately the
impedance of the output buffer (shown below.) The intent of these resistors is to terminate the
unused outputs to eliminate EMI.

Table 4-6. Unused Output Termination
VCC Range (V)

Impedance
(Ohms)

If Unused Output
Termination to VSS

CPU, CPU_Div2, IOAPIC

2.375 - 2.625

13.5 - 45

30 Ohms

48 MHz, REF

3.135 - 3.465

20 - 60

40 Ohms

PCI, 3V66

3.135 - 3.465

12 - 55

33 Ohms

Buffer Name

4.7

Decoupling Recommendation for CK133 and DRCG
Some CK133 vendors may integrate the XTAL_IN and XTAL_OUT frequency adjust capacitors.
However, pads should be placed on the board for these external capacitors for testing/debug.
To further reduce jitter and voltage supply noise, the addition of a ferrite filter with 2 caps (10 uF
and 0.1 uF) on both the 2.5V and 3.3V planes close to the clock devices is recommended. This
applies to both DRCG and CK133.

4.8

DRCG Frequency Selection and the DRCG+

4.8.1

DRCG Frequency Selection Table and Jitter Specification
To allow additional flexibility in board design, Intel has enabled a variation of the DRCG labeled
the DRCG+. The device has the same specifications, pinout and form-factor as the existing DRCG
device document. There are two modifications made to the DRCG+.
1. The DRCG+ Mult[0:1] select table has changed to modify two of the multiplier ratios. The
DRCG+ will support 133/356 MHz using 66 MHZ DRCG+ input clock and a 16/3 multiplier.
An additional 9/2 multiplier allows 133/300 MHz (not supported by the Intel® 820 chipset).
Support for 300 MHz and 400 MHz memory bus is unchanged. The following table lists the
DRCG Ratio.

Table 4-7. DRCG Ratio

4-12

Mult[0:1]

DRCG

DRCG+

0:0

4:1

9:2

0:1

6:1

6:1

1:0

8:3

16:3

1:1

8:1

8:1

Intel®820 Chipset Design Guide

Clocking

2. The Intel® 820 chipset supports the following ratios and can be supported by the DRCG and
DRCG+ or derivative devices. Contact your DRCG vendor for information on DRCG,
DRCG+, and derivative products.
100 MHz Host Bus

133 MHz Host Bus

Frequency

Multiplier

Frequency

Multiplier

100 / 300

6:1

133 / 266

4:1

100 / 400

8:1

133 / 356

16:3

133 / 400

6:1

3. The jitter timing specifications are expanded to encompass both the component specification
(for DRCG or derivative products) and the channel specification. Follow the component
specification when measuring jitter at the DRCG output resistor. Follow the channel jitter
guidelines when measuring jitter at the MCH or at the termination for CFM/CFM# on the
RDRAM interface.

4.8.2

Output Frequency
(MHz)

Component Jitter
Specification

Channel Jitter
Guidelines

400

50 ps

100 ps

356

60 ps

110 ps

300

70 ps

120 ps

266

80 ps

130 ps

DRCG+ Frequency Selection Schematic
DRCG+ frequency selection can be accomplished using two GPIOs connected to the MULT[0:1]
pins as shown in Figure 4-11. This allows selection of all frequencies supported by the Intel® 820
chipset.

REFCLK
PWRD#
STOPB#
MULTO
MULT1
S0
S1
GND
PCLKM
SYNCLKN
NC

CLK
CLKB#

20
18

17
21
4
8
5

GNDO1
GNDO2
GNDP
GNDC
GNDI

GPO1
GPO2

2
12
11
15
14
24
23
13
6
7
19

VDDIR
VDDIPD
VDDO1
VDDO2
VDDP
VDDC

U?
DRCG

1
10
16
22
3
9

Figure 4-11. DRCG+ Frequency Selection

Intel®820 Chipset Design Guide

4-13

Clocking

This page is intentionally left blank.

4-14

Intel®820 Chipset Design Guide

5
System
Manufacturing

This page is intentionally left blank.

System Manufacturing

System Manufacturing
5.1

5

In Circuit FWH Flash BIOS Programming
All cycles destined for the FWH Flash BIOS appear on PCI. The ICH hub interface to PCI Bridge
puts all processor boot cycles out on PCI (before sending them out on the FWH Flash BIOS
interface to the FWH Flash BIOS). If the ICH is set for subtractive decode, these boot cycles can be
accepted by a positive decode agent out on PCI. The enables the ability to boot from of a PCI card
that positively decodes these memory cycles. To boot from a PCI card it is necessary to keep the
ICH in subtractive decode mode. If a PCI boot card is inserted and the ICH is programmed for
positive decode, there will be two devices positively decoding the same cycle. In systems with the
82380AB (ISA bridge), it is also necessary to keep the NOGO signal asserted when booting from a
PCI ROM. Note that it is not possible to boot from a ROM behind the 82380AB. Once you have
booted from the PCI card, you could potentially program the FWH Flash BIOS in circuit and
program the ICH CMOS.

5.2

FWH Flash BIOS Vpp Design Guidelines
The Vpp pin on the FWH Flash BIOS is used for programming the flash cells. The FWH Flash
BIOS supports Vpp of 3.3V or 12V. If Vpp is 12V, the flash cells will program about 50% faster
than at 3.3V. However, the FWH Flash BIOS only supports 12V Vpp for 80 hours. The 12V Vpp
would be useful in a programmer environment that is typically an event that occurs very
infrequently (much less than 80 hours). The VPP pin MUST be tied to 3.3V on the motherboard.

5.3

Stackup Requirement

5.3.1

Overview
The Intel® 820 chipset platform requires a board stackup with a 4.5 mil prepreg. This change in
dimension (previously, typically 7 mil) is required because of the signaling environment used for
Direct RDRAM, AGP 2.0 and hub interface. The RDRAM Channel is designed for 28 Ω and
mismatched impedance will cause signal reflections which will reduce voltage and timing margins.
For example, with a 2X clock at 400 MHz operation, which equals a 1.25 ns sampling window,
only 100 ps is allotted for total channel timing error. Channel error results not only from PCB
impedance, but also PCB and Z0 process variation. Therefore, it is critical to attain the required
28 Ω impedance.

Intel®820 Chipset Design Guide

5-1

System Manufacturing

5.3.2

PCB Materials
PCB tolerances determine Z0 variation. Those tolerances include trace width, pre-preg thickness,
plating thickness, and dielectric constant. Pre-preg type impacts H tolerance and εr including single
ply, 2-ply, and resin content.
To design to the correct Z0 variation, PCB’s typically need to meet the following (see Table 5-2):
• Height tolerance ±10% (~ 0.4 mil)
• Width tolerance ±2.5% (~ 0.4 mil)
• εr tolerance ±5% (~0.2)
Stackup Requirement: 28Ω ±10%

Figure 5-1. 28Ω Trace Geometry

W
T

S

ε

5.3.3

H

Design Process
To meet the tight tolerances required a good design process to use is:

•
•
•
•

Specify the material to be used
Calculate board geometries for the desired impedance - or use the example stackup provided
Build test boards and coupons
Measure board impedance using a TDR and follow Intel’s Impedance Test Methodology
Document (found on developer.intel.com)

• Measure geometries with cross-section
• Adjust design parameters and/or material as required
• Build a new board, re-measure the key parameters and be prepared to generate one or two
board iterations
This process will require iteration: design, build, test, modify, build, test…

5-2

Intel®820 Chipset Design Guide

System Manufacturing

5.3.4

Test Coupon Design Guidelines
Characterization and understanding of the trace impedance is critical for delivering reliable
systems at the increased bus frequencies. Incorporating a test coupon design into the motherboard
makes testing simpler and more accurate. The test coupon pattern must match the probe type being
used.
The location of the test coupon is listed in order of preference below:

• 1st Choice (Ideal Location) =
• 2nd Choice
=
rd
• 3 Choice
=

Memory section of the motherboard
Any section of the motherboard
Separate location in the panel

The Intel Impedance Test Methodology Document should be used to ensure boards are within the
28Ω ±10% requirement. The Intel Controlled Impedance Design and Test Document should be
used for the test coupon design and implementation. These documents can be found at:
http://developer.intel.com/design/chipsets/memory/rdram.htm

— Select “Application Notes”

5.3.5

Recommended Stackup
Though numerous variations of stackup are possible, it is recommended that the following should
be used as a starting point:
W=18 mil, H=4.5 mil, T=2.0, 1 ply 2116 pre-preg
For other possibilities see Table 5-1 and following figures:

Table 5-1. 28Ω Stackup Examples

5.3.6

Sample

Zo

H

W

T

SM(max)

Resin %

1

27.1

4.3

18.0

2.1

0.6

53.0

2

28.1

3.8

18.5

1.6

1.2

72.0

3

28.6

4.8

19.0

2.5

0.7

61.0

Inner Layer Routing
Inner Layer Routing also has many possible stackups. For Inner Layer Routing, it is recommended
to use the following as a starting point:
W=13.5 mil, H1=7 mil, H2=5, T=1.2
With these parameters, initial TDR should fall within acceptable limits - 28 Ω ±10%
Figure 5-2 shows examples of both Stripline and Microstrip cross sections.

Intel®820 Chipset Design Guide

5-3

System Manufacturing

Figure 5-2. (a,b) Microstrip and Stripline Cross-section for 28 Ω Trace
a) Microstrip Cross-Section for 28 Ohm trace
10 mils

18 mils
6 mils
S

G

2.1 mils

G

4.5 mils

b) Stripline Cross-Section for 28 Ohm trace
1.2 mils
6 mils

7 mils

13.5 mils
5 mils

G

S

G

1.2 mils

5 mils
1.2 mils

Note:

5.3.7

Don’t forget ground floods and stitching

Impedance Calculation Tools
The 3D Field Solvers (e.g., those by HP, Ansoft, Sonnet, and Polar) are the most accurate for
calculating impedance. Z calculators based on equations (zcalc) are also fairly accurate. The
differences are shown in Table 5-2.

Table 5-2. 3D Field Solver vs ZCALC
H

#2

#3

#4

#5

#6

4.5

4.2

4.8

4.5

4.5

W

18

18

18

18

17

19

W1

18.1

18.1

18.1

18.1

17.1

19.1

T

5.3.8

#1
4.5

εr

1.4

2.8

1.4

1.4

1.4

1.4

4.5

4.5

4.5

4.5

4.5

4.5

Z0(3D)

29.0

28.4

27.6

30.4

30.2

27.9

Z0(zcalc)

29.1

28.7

27.7

30.4

30.2

28.0

Testing Board Impedance
The Intel Impedance Test Methodology Document should be used to ensure boards are within the
28 Ω ±10% requirement. This document can be found at: http://developer.intel.com.

5-4

Intel®820 Chipset Design Guide

System Manufacturing

5.3.9

Board Impedance/Stackup Summary
1. 7628 Cloth, 1 ply 0.007” when cured with 40% resin is the most popular and highest volume
PCB in production today. This stackup will make routing impossible.
• Fab Construction (4 Layers)
• Zo = 70 Ω ± 15%

Figure 5-3. 7 mil Stackup (Not Routable)
Component Side Layer: 1/2 oz Cu
7 Mil Prepreg
Ground Layer 2: 1 oz Cu

Not Routable

Total Thickness = 62 mils

Ground Layer 3: 1 oz Cu
7 Mil Prepreg
Solder Side Layer 4: 1/2 oz Cu

2. 2116 Cloth, 1 ply 0.0045” when cured with 53% resin is the second largest volume in
production today. Due to the impedance & layout requirement of traces for Direct RDRAM,
AGP 2.0, and hub interface, this stackup is recommended for Intel® 820 chipset platform
design.
• Fab Construction (4 Layers)
• Zo = 60 ohms ± 10%
Figure 5-4. 4.5 mil Stackup
Component Side Layer: 1/2 oz Cu
4.5 Mil Prepreg
Ground Layer 2: 1 oz Cu

~48 Mil Core

Total Thickness = 62 mils

Ground Layer 3: 1 oz Cu
4.5 Mil Prepreg
Solder Side Layer 4: 1/2 oz Cu
4 5 il

Intel®820 Chipset Design Guide

t

k

d

5-5

System Manufacturing

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5-6

Intel®820 Chipset Design Guide

6
System Design
Considerations

This page is intentionally left blank.

System Design Considerations

System Design Considerations
6.1

Power Delivery

6.1.1

Terminology and Definitions

6

Term

Definition

Suspend-ToRAM (STR)

In the STR state, the system state is stored in main memory and all unnecessary
system logic is turned off. Only main memory and logic required to wake the
system remain powered. This state is used in the Reference Board (refer to
Appendix A, “Reference Design Schematics: Uni-Processor” or Appendix B,
“Reference Design Schematics: Dual-Processor”) to satisfy the S3 ACPI power
management state.

Full-power
operation

During full-power operation, all components on the motherboard remain
powered. Note that full-power operation includes both the full-on operating state
and the S1 (CPU stop-grant state) state.

Suspend
operation

During suspend operation, power is removed from some components on the
motherboard. The customer reference board supports two suspend states:
Suspend-to-RAM (S3) and Soft-off (S5).

Power rails

An ATX power supply has 6 power rails: +5V, -5V, +12V, -12V, +3.3V, 5VSB.
In addition to these power rails, several other power rails are created with
voltage regulators on the Intel® 820 Chipset Reference Board.

Core power rail A power rail that is only on during full-power operation. These power rails are
on when the PSON signal is asserted to the ATX power supply. The core power
rails that are distributed directly from the ATX power supply are: ±5V, ±12V
and +3.3V.
Standby power
rail

A power rail that in on during suspend operation (these rails are also on during
full-power operation). These rails are on at all times (when the power supply is
plugged into AC power). The only standby power rail that is distributed directly
from the ATX power supply is: 5VSB (5V Standby). There are other standby
rails that are created with voltage regulators on the motherboard.

Derived power
rail

A derived power rail is any power rail that is generated from another power rail
using an on-board voltage regulator. For example, 3.3VSB is usually derived (on
the motherboard) from 5VSB using a voltage regulator (on the Intel® 820
Chipset Reference Board, 3.3VSB is derived from 5V_DUAL).

Dual power rail A dual power rail is derived from different rails at different times (depending on
the power state of the system). Usually, a dual power rail is derived from a
standby supply during suspend operation and derived from a core supply during
full-power operation. Note that the voltage on a dual power rail may be
misleading.

Intel®820 Chipset Design Guide

6-1

System Design Considerations

6.1.2

Intel® 820 Chipset Customer Reference Board Power
Delivery
Figure 6-1 shows the power delivery architecture for the Intel® 820 Chipset Reference Board. This
power delivery architecture supports the “Instantly Available PC Design Guidelines” via the
suspend-to-RAM (STR) state. During STR, only the necessary devices are powered. These devices
include: main memory, the ICH resume well, PCI wake devices (via 3.3V aux) and USB (USB can
only be powered if sufficient standby power is available). To ensure that enough power is available
during STR, a thorough power budget must be completed. The power requirements must include
each device’s power requirements, both in suspend and in full-power. The power requirements
must be compared against the power budget supplied by the power supply. Due to the requirements
of main memory and PCI 3.3V aux (and possibly other devices in the system), it is necessary to
create a dual power rail.

Figure 6-1. Intel® 820 Chipset Power Delivery Example
ATX P/S
with 1A 5VSB
5VSB

5V

3.3V

12V

VRM

Slot1 Core: VCC_VID
18.6A S0, S1

VTT Regulator

Slot1 VTT: 1.5V
2.7A S0, S1
Slot1 VCC5: 5V
1A S0, S1

5V Dual
Switch

Slot1 VCC3: 3.3V
1.8A S0, S1
2.5V
Regulator

CK133-2.5: 2.5V
CK133-3.3: 3.3V

DRCG: 3.3V
100mA S0, S1
MCH Core: 1.8V
MCH Hubinterface I/O: 1.8V
950mA S0, S1

RDRAM Core: 2.5V
4.5A S0, S1; 32ma S3
RDRAM VTerm: 1.8V
704mA S0, S1

MCH VDDQ: 1.5V/3.3V*
2A S0, S1

2.5V
VCC CMOS: 1.8V
3mA S0, S1, S3

1.8V

1.8V Regulator
VDDQ
Regulator

ICH Core: 3.3V
300mA S0, S1

2.5V CPU CMOS
Regulator (STR)

Processor |
CMOS P/Us: 2.5V

ICH Hubinterface I/O: 1.8V**
55mA S0, S1
ICH 5V Rail: 5V

3.3VSB
Regulator

PCI 3.3Vaux: 3.3V
1.5A S0, S1; 435ma S3, S5

ICH Resume: 3.3V
10mA S0, S1; 300uA S3, S5

LPC Super I/O: 3.3V

ICH RTC: Vbat
5uA S0, S1, S3, S5
USB Cable Power: 5V
1A S0, S1; 1mA S3, S5
FWH Flash BIOS
Core: 3.3V
67mA S0, S1

AC'97 Modem Codec: 5V

* Vddq also connects to the AGP connector. 2A is the TOTAL VDDQ current requirement.
** Actual MCH and ICH hub interface max. power is 110 mA. However, only one of the devices may be driving the bus at any given time (i.e., only one will
be consuming 110 mA). Therefore, 55 mA has been budgeted to each device. The MCH hub interface I/O power is accounted for in the 2A, 1.8V requirement
Shaded regulators/components are on in S3, S5 (Note RDRAM core and VCC CMOS must be OFF in S5)
LEGEND:
ATX Power Planes

Intel® 820 Chipset Power Planes

5VSB

5V Dual

1.8V

5V

VCCVID

VDDQ

3.3V

VTT

3.3VSB

12V

2.5VSBY

2.5V

The examples given in this Design Guide are only examples. There are many power distribution
methods that achieve the similar results. It is critical, when deviating from these examples in any
way, to consider the effect of the change.

6-2

Intel®820 Chipset Design Guide

System Design Considerations

In addition to the power planes provided by the ATX power supply, an instantly available Intel®
820 chipset based system (using Suspend-to-RAM) requires 7 power planes to be generated on the
board. The requirements for each power plane are documented in this section. In addition to onboard voltage regulators, the Intel® 820 Chipset Reference Board will have a 5V Dual Switch.

5V Dual Switch
This switch powers the 5V Dual plane from the 5V core ATX supply during full-power operation.
During Suspend-to-RAM, the 5V Dual plane is powered from the 5V Standby power supply.
Note:

The voltage on the 5V Dual plane is not 5V! There is a resistive drop through the 5V Dual Switch
that must be considered. Therefore, NO COMPONENTS should be connected directly to the 5V
Dual plane. On the Intel® 820 chipset Reference Board, the only devices connected to the 5V Dual
plane are voltage regulators (to regulate to lower voltages).

Note:

This switch is not required in a Intel® 820 chipset based system that does not support Suspend-toRAM (STR).

VCCVID
This power plane is used to power the SC242 processor. Refer to the latest revisions of:

• VRM 8.4 DC-DC Converter Design Guidelines
• Slot 1 Power Delivery Guidelines
Note:

This regulator is required in ALL designs.

VTT
This power plane is used to power the AGTL+ termination resistors. Refer to the latest revisions of:

• Intel® Pentium® III Processor Datasheet
Note:

This regulator is required in ALL designs.

2.5VSBY
The 2.5VSBY power plane is used to power the RDRAM core and the VCMOS rail on the
RDRAMs. The RDRAM core requires approximately 4.5A maximum average DC current at 2.5V
(refer to Section 6.1.3, “64/72Mbit RDRAM Excessive Power Consumption” on page 6-5). In the
Intel® 820 Chipset Reference Board, the 2.5VSBY plane is derived from the 5V Dual power plane
using a switching regulator. It is important, that during the maximum load-step of 2A, the
maximum voltage fluctuation is less than 50 mV. The maximum 2.5V tolerance is 125 mV,
however during any 10 uS period, the voltage can not fluctuate more than 50 mV. The highfrequency bypassing requirements are met using capacitors on the RIMM itself. Low frequency
bypass requirements vary depending on the voltage regulator used. Using a switching regulator,
with a relatively slow response time, the low frequency bypass recommendation is: 8 100 uF bulk
capacitors (0.1Ω ESR) near the RIMM connectors. These capacitors must be placed near the
RIMM connector. Preferably spread the capacitors around where 2.5V connects to the RIMMs.
The VCMOS rail requires a maximum of 3ma at 1.8V. This rail MUST be powered during
Suspend-to-RAM and therefore, the VCMOS rail can not be connected to the MCH core power.
Because the current requirements of VCMOS are so low, a resistor divider can be used to generate
VCMOS from 2.5VSBY. The resistor divider should be 36 Ω (top) / 100 Ω (bottom). Additionally,
it should be bypassed with a 0.1 µF chip capacitor.

Intel®820 Chipset Design Guide

6-3

System Design Considerations

The Intel® 820 Chipset Reference Board is using a switching regulator from 5V Dual. It may be
possible to use a linear regulator to regulate from 3.3VSB, however the thermal characteristics
must be considered. Additionally, a low drop out linear regulator would be necessary. If 2.5VSBYis
regulated from 3.3VSB, it is important the 3.3VSB regulator can supply enough current for all the
3.3VSB device requirements as well as the 2.5VSBY requirements.
Refer to the 1.8V power plane information for 1.8V and 2.5V power sequencing requirement.
Note:

Refer to section Section 6.1.3, “64/72Mbit RDRAM Excessive Power Consumption” on page 6-5
for more details.

Note:

This regulator is required in ALL designs, however in systems that do not support STR, the 2.5V
rail would be powered from either the 3.3V or 5V core well.

1.8V
The 1.8V plane powers the MCH core, the ICH hub interface I/O buffers and the RDRAM
termination resistors. This power plane has a total power requirement of approximately 1.7A. The
1.8V plane should be decoupled with a 0.1 uF and a 0.01 uF chip capacitor at each corner of the
MCH and with a single 1 uF and 0.1 uF capacitor at the ICH. Additionally, the 1.8V plane should
be decoupled at the RDRAM termination as shown in Section 2.6.2, “Direct Rambus* Layout
Guidelines” on page 2-8.
Power MUST NOT be applied to the RDRAM termination resistors (Vterm) prior to applying
power to the RDRAM Core (2.5VSBY in this design). This can be guaranteed by placing a
Schottky diode between 1.8V and 2.5V as shown in Figure 6-2.
Figure 6-2. 1.8V and 2.5V Power Sequencing (Schottky Diode)

1.8V

2.5V
Note:

This regulator is required in ALL designs.

VDDQ
The VDDQ plane is used to power the MCH AGP interface and the graphics component AGP
interface. Refer to the AGP Interface Specification Revision 2.0 (http://www.agpforum.org).
Note:

This regulator is required in ALL designs (unless the design does not support 1.5V AGP, and
therefore does not support 4X AGP).
For the consideration of component long term reliability, the following power sequence is required
while the AGP interface of MCH is running at 3.3V. If the AGP interface is running at 1.5V, the
following power sequence requirement is no longer applicable. The power sequence requirements
are:
1. During the power-up sequence, the 1.8V must ramp up to 1.0V BEFORE 3.3V ramps up to
2.2V
2. During the power-down sequence, the 1.8V CAN NOT ramp below 1.0V BEFORE 3.3V
ramps below 2.2V
3. The same power sequence recommendation also applies to the entrance and exit of S3 state,
since MCH power is completely off during the S3 state.

6-4

Intel®820 Chipset Design Guide

System Design Considerations

System designers need to be aware of this requirement while designing the voltage regulators and
selecting the power supply. For further details on the voltage sequencing requirements, refer to the
latest Intel® 820 Chipset: 82820 Memory Controller Hub (MCH) datasheet.

3.3VSB
The 3.3VSB plane powers the suspend well of the ICH and the PCI 3.3Vaux suspend power pins.
The 3.3Vaux requirement state that during suspend, the system must deliver 375mA to each wakeenabled card and 20 mA to each non wake-enabled card. During full-power operation, the system
must be able to supply 375 mA to EACH card. Therefore, the total current requirement is:

• Full-power Operation:
• Suspend Operation:

375 mA * number of PCI slots
375+20 * (number of PCI slots – 1)

In addition to the PCI 3.3V aux, the ICH suspend well power requirements must be considered as
shown in Figure 6-1.
Note:

This regulator is required in ALL designs.

2.5V
The 2.5V plane powers the CPU CMOS pull-up resistors. These pull-up resistors must not be
powered when the system is in S3 (because the ICH core is powered down). Therefore, this power
plane must be separate from the 2.5VSBY regulator. The total current requirement is
approximately 180 mA. This power plane could also be implemented using a FET switch from
2.5VSBY (and controlled by SLP_S3#). If using a FET switch, the resistive drop across the FET
switch should be considered.
Note:

6.1.3

This regulator is not required in a Intel® 820 chipset based system that does not support Suspendto-RAM (STR).

64/72Mbit RDRAM Excessive Power Consumption
Some 64/72Mbit RDRAM devices interpret non-broadcast, device-directed commands as
broadcast commands. These commands are the SET_FAST_CLOCK, SET_RESET, and
CLEAR_RESET commands. RDRAM devices consume more current during these initialization
steps than during normal operation. As a result of these devices accepting device directed
commands as broadcast commands, the device can not be reset/initialized serially. All devices must
be reset/initialize simultaneously. This will result in excessive current draw during the initialization
of memory. The amount of excessive current will depend on the number of devices and frequency
used. The worst case current draw is 7.5A, in a system with 32 devices and a frequency of
400 MHz. There are two potential solutions:
1. Reduce the clock frequency during initialization (Section 6.1.3.1, “Option 1: Reduce the Clock
Frequency During Initialization” on page 6-6);
2. Increase the current capability of the 2.5V voltage regulator (Section 6.1.3.2, “Option 2:
Increase the Current Capability of the 2.5V Voltage Regulator” on page 6-6).

Intel®820 Chipset Design Guide

6-5

System Design Considerations

6.1.3.1

Option 1: Reduce the Clock Frequency During Initialization
Tie a single core well GPO with a default high state to both the S0 and S1 pins of the DRCG
(i.e., tie S0 and S1 together and then connect to a GPO as shown in Figure 6-3). When the core
power supply to the system is turned on, the DRCG enters a test mode and the output frequency
will match the input REFCLK frequency. For details on this DRCG mode, refer to the latest DRCG
specification. By slowing down the DRCG output clock, the power consumption from the 2.5V
power supply is reduced. After the SetR/ClrR commands have been issued, the BIOS drives the
GPO low to bring the DRCG back to normal operation.

Note:

If a default low GPO is used, on power up, all the devices may come up in the standby state at full
speed; thus, requiring more power.

Figure 6-3. Use a GPO to Reduce DRCG Frequency

S0
DRCG

GPO
S0

6.1.3.2

Option 2: Increase the Current Capability of the 2.5V Voltage
Regulator
The second implementation option requires that the 2.5V power supply be modified to maintain the
maximum amount of current required by a fully populated RDRAM channel (~7.5A).

6-6

Intel®820 Chipset Design Guide

System Design Considerations

6.2

Power Plane Splits
Figure 6-4 shows an EXAMPLE of the power plane splits on an Intel® 820 chipset platform.

Figure 6-4. Power Plane Split Example

6.3

Thermal Design Power
The thermal design power is the estimated maximum possible expected power generated in a
component by a realistic application. It is based on extrapolations in both hardware and software
technology over the life of the product. It does not represent the expected power generated by a
power virus. Refer to the Intel® 820 Chipset Application Note: Thermal Design Considerations,
for the thermal measurement methodology.
The thermal design power numbers for the MCH, MTH, and the ICH are listed in Table 6-1.

Table 6-1. Intel® 820 Chipset Component Thermal Design Power
Component

Thermal Design Power (133/400 MHz)

MCH

3.5W ±15%

MTH

2.5W ±15%

ICH

1.3W ±15%

Intel®820 Chipset Design Guide

6-7

System Design Considerations

6.4

Glue Chip 3 (Intel® 820 Chipset Glue Chip)
To reduce the component count and BOM cost of the Intel® 820 chipset platform, Intel has
developed an ASIC component that integrates miscellaneous platform logic into a single chip. The
Glue Chip 3 is designed to integrate some or all of the following functions into a single device. By
integrating much of the required glue logic into a single device, overall board cost can be reduced.

Features

•
•
•
•
•
•
•
•
•
•
•
•
•

PWROK signal generation
Control circuitry for Suspend To RAM
Power Supply power up circuitry
RSMRST# generation
Backfeed cutoff circuit for suspend to RAM
5V reference generation
Flash FLUSH# / INIT# circuit
HD single color LED driver
IDE reset signal generation/PCIRST# buffers
Voltage translation for Audio MIDI signal
Audio-disable circuit
Voltage translation for DDC to monitor
Tri-state buffers for test

More information regarding this component is available from the following vendors:
Table 6-2. Glue Chip 3 Vendors
Vendor Intel

6-8

Contact

Contact Information

Fujitsu Microelectronics

Customer Response Center

3545 North 1st Street, M/S 104
San Jose, CA 95134-1804
fax: 1-408-922-9179
email: fmicrc@fmi.fujitsu.com

Mitel Semiconductor

Mitel Semiconductor

http://www.mitelsemi.com

Intel®820 Chipset Design Guide

A
Reference Board
Schematics: Uni-Processor

This page is intentionally left blank.

Reference Design Schematics: Uni-Processor

Reference Design Schematics:
Uni-Processor
A.1

A

Reference Design Feature Set
The reference schematics feature the following core feature set:

• Intel® 820 Chipset
— Memory Controller Hub (MCH)
— I/O Controller Hub (ICH)
— FWH Flash BIOS Interface

• Support for the Pentium III (SC242) Processor
— 100/133 MHz System Bus Frequency
— Debug Port

• IOAPIC Integrated into the ICH
• Direct RDRAM Memory Interface
— 266 MHz, 300 MHz, 356 MHz and 400 MHz Direct RDRAM Support

• 4 PCI Add-in Slots
— Via 4 REQ/GNT pairs (ICH supports 6 REQ#/GNT# pairs)

• AGP Universal Connector
— 3.3V - 1X,2X signaling
— 1.5V – 1X, 2X, 4X signaling

•
•
•
•

2 IDE Connectors with Ultra ATA/66 Support

•
•
•
•

AC‘97 Bus Connector and Audio Codec

2 USB Connectors
ATX Power Connector
LPC Ultra I/O
— Floppy Disk Controller
— 1 Parallel Port, 2 Serial Ports
— Keyboard Controller

WfM Support
Integrated System Management
Integrated Power Management
— ACPI Rev. 1.0 Compliant
— APM Rev. 1.2 Compliant

• Pentium III on-board VRM 8.4 compliant regulator
• 4 Layer Design

Intel®820 Chipset Design Guide

A-1

8

7

6

5

4

3

2

1

INTEL(R) 820 CHIPSET
UNIPROCESSOR CUSTOMER REFERENCE SCHEMATICS
REV F (2 RIMM)
D

Title
Cover Sheet

1

Block Diagram

2

Processor Connector

3, 4

Clock Synthesizer

C

5

MCH

6, 7

ICH

8, 9

FWH

10

RIMM Sockets

11

Super I/O

12

Audio

13,14

Audio/Modem Riser

15

LAN

16,17

System

B

18

Note that these schematics are preliminary and are subject to change.
C

T H E S E S C H E M A T IC S A R E P R O V ID E D “A S IS ” W IT H N O W A R R A N T IE S W H A T S O E V E R ,
IN C L U D IN G A N Y W A R R A N T Y O F M E R C H A N T A B IL IT Y , F IT N E S S F O R A N Y P A R T IC U L A R
P U R P O S E , O R A N Y W A R R A N T Y O T H E R W IS E A R IS IN G O U T O F P R O P O S A L ,
S P E C IF IC A T IO N O R S A M P L E S .
In fo rm a tio n in th is d o c u m e n t is p ro vid e d in c o n n e c tio n w ith In te l p ro d u c ts. N o lic e n s e , e x p re s s o r
im p lie d , b y e sto p p e l o r o th e rw is e , to a n y in te lle c tu a l p ro p e rty rig h ts is g ra n te d b y th is d o c u m e n t.
E x ce p t a s p ro vid e d in In te l's T e rm s a n d C o n d itio n s o f S a le fo r su c h p ro d u c ts, In te l a ss u m e s n o
lia b ility w h a tso e ve r, a n d In te l d is cla im s a n y e xp re s s o r im p lie d w a rra n ty, re la tin g to sa le a n d /o r
u s e o f In te l p ro d u c ts in c lu d in g lia b ility o r w a rra n tie s re la tin g to fitn e ss fo r a p a rtic u la r p u rp o se ,
m e rc h a n ta b ility, o r in frin g e m e n t o f a n y p a te n t, c o p yrig h t o r o th e r in te lle c tu a l p ro p e rty rig h t. In te l
p ro d u c ts a re n o t in te n d e d fo r u s e in m e d ica l, life sa vin g , o r life s u s ta in in g a p p lic a tio n s . In te l m a y
m a k e ch a n g e s to sp e cifica tio n s a n d p ro d u c t d e s crip tio n s a t a n y tim e , w ith o u t n o tic e .

AGP Connector

19

PCI Connectors

20,21

IDE Connectors

22

USB Connectors

23

Parallel Port

24

T h e In te l 8 2 8 2 0 c h ip se t m a y co n ta in d e sig n d e fe cts o r e rro rs k n o w n a s e rra ta w h ic h m a y c a u s e
th e p ro d u c t to d e via te fro m p u b lis h e d s p e c ific a tio n s. C u rre n t c h a ra cte rize d e rra ta a re a va ila b le o n
re q u e s t.

Serial Ports

25

In te l m a y m a k e ch a n g e s to s p e cifica tio n s a n d p ro d u c t d e s c rip tio n s a t a n y tim e , w ith o u t n o tic e .

Keyboard/Mouse/Floppy Ports

26

C o p yrig h t © In te l C o rp o ra tio n 1 9 9 9 .

Game Port

27

VRM

28

Voltage Regulators
A

D

Page

*T h ird -p a rty b ra n d s a n d n a m e s a re th e p ro p e rty o f th e ir re s p e c tive o w n e rs .

29,30

Pow er Connector

31

PCI/AGP Pullups/Pulldow ns

32

Rambus Termination

33

Decoupling

A

34,35

Revision History
8

B

7

6

REV:
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TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD

36

R

5

4

3

PCD PLATFORM DESIGN
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2

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1 OF 36

1

8

7

6

5

4

3

2

1

Block Diagram
Device Table
VRM

D

Processor

Clock

DATA

CTRL

ADDR

REFERENCE
DESIGNATOR

DATA

CTRL

ADDR

AGP Bus
AGP

Rambus
2 RIMM
Modules

MCH

C
IDE Primary

UltraDMA/66
PCI CNTRL

USB Port 2

AC’97 Link

LPC Bus

AC’97 Audio

Modem
82559 LAN

SIO

B
FWH

Keyboard

Floppy

Parallel

PCI CONN 4

PCI CONN 3

PCI ADDR/DATA

USB

PCI CONN 2

ICH
USB Port 1

PCI CONN 1

IDE Secondary

U20
U14
U19
U3
U15
U18
U13
U10
U5
U8
U2
U11
U12
U16
U4, U6
U1
U17
U9
U7

DEVICE
TYPE
74LVC06A
74LVC07A
74LVC07A
74LVC08A
74LVC14a
74LS132
82820 (ICH)
82820 (MCH)
82559
93C46A
AD1881
CK133
DRCG
FWH
GD75232
LM4880
LPC47B27X
ADM1021
TPS2042

GATES
USED
A,
A,
A,
A,
A,
B,

B,
B,
C,
B
B,
C

C
C
D
C, D

SHEET
NUMBER
31
18, 29
18, 22
15, 31
31
29, 31
8, 9
6, 7
16
16
13
5
5
10
25
14
12
3
23

D

C

B

Game Conn

Mouse
Serial 1
Serial 2

A

A

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8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Processor Connector
HA#[31:0]

HD#[63:0]

6

J14

B

A

8

7

D

SC242

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HA#32
HA#33
HA#34
HA#35

B98
A100
A97
B99
B96
B95
A99
A96
B92
B94
A93
A95
B90
A92
B91
A91
A89
B86
B87
A85
A87
B83
B88
B82
A84
B84
B80
A81
A83
B79
A79
A80
B78

VID0
VID1
VID2
VID3
VID4

B120
A120
A119
B119
A121

VID0
VID1
VID2
VID3
VID4

VID[4:0]

RS#0
RS#1
RS#2

B108
A112
B111

RS#0
RS#1
RS#2

RS#[2:0]

RSP#

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

C

VCC3_3

28

B102
B103
A107
A108
B104

RP#

B114

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

DXP
DXN

1
5
9
13
16

NC1
NC5
NC9
NC13
NC16

STBY#

15

ADD0
ADD1

10
6

SMBCLK
SMBDATA
ALERT#

14
12
11

6

B115

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4

3
4

HREQ#[4:0]

6

VCC3_3

B

U9
ADM1021

2

C

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

VCC2

D

B72
A73
B71
A72
B70
A71
B68
B67
A69
A68
A65
A64
B66
A63
A67
B64
A61
B63
B60
B59
B62
A60
B58
A59
A57
B56
B55
A56
B52
B54
A55
A53
B51
A51
B48
A52
B46
A49
B50
A45
B47
B42
A43
A48
B44
A44
A39
B43
B39
A40
B35
A41
B40
A36
B36
A33
B34
A37
B31
B38
A35
A32
B30
B32

SMBCLK_CORE
SMBDATA_CORE
THRM#

9,11,32
9,11,32
9

7
8

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

GND8
GND7

6

THRMDN
THRMDP

B15
B14

RESERVED3

B12

RESERVED2
RESERVED1
RESERVED0

A116
A88
A47

R122
0K

THRMDN
R121
THRMDP
0K
THRMDP and THRMDN signals must be disconnected from onboard thermal sensor
during SECC2 thermal testing of the processor. Please see the "Pentium(R) II processor Single Edge
Contact Cartridge 2 Thermal Validation" document for further details.
Place R121,R122 very close to processor.

THRMDN_R
THRMDP_R

A

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6

5

4

3

2

1

8

7

6

5

4

3

2

1

Processor Connector

VTT1_5

VCCVID

VCC5

VCC3_3

D

ITP

D

VCC3_3

VCC2_5

VTT1_5

VCC2_5

R19

150

330

R142

330

R139

R145

1K

1K
R171

1K
R167

R157

240

TDI
TDO
TRST#

680

R140

ITPREQ#
ITPRDY#_R

240

47

R152

ITPCLK

5

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

4

PICD0
PICD1
PICCLK

8,32
8,32
5
ITPPRDY#

47

R163

0K

0K

R100

0K

R93

0K

R103

R104

0K

R101

5
31
4,6

0.1UF

C80

CPUHCLK

A75

BCLK

PWRGOOD
CPURST#

A12
B74

PWRGOOD
RESET#

AP0#
AP1#
BNR#
BPRI#
TRDY#
DEFER#
LOCK#
DRDY#
HITM#
HIT#
DBSY#
HADS#

SC242

TESTHI
BSEL0
BSEL1

B21
A14
B2

THMTRP#

A15

A20M#
STPCLK#
SLP#
SMI#
LINT0
LINT1
INIT#
FERR#
IGNNE#
IERR#
BERR#
AERR#
RES0
RES1
RES2
RES3

A5
B6
B8
B3
A17
B16
B4
A7
A8
A4
A77
B118
A16
B20
B112
A113

BNR#
BPRI#
HTRDY#
DEFER#
HLOCK#
DRDY#
HITM#
HIT#
DBSY#
HADS#
ITPREQ#
ITPPRDY#
BREQ#0

TESTHI
VRM_PWRGD
SEL133/100#
FLUSH#

A20M#
STPCLK#
SLP#
SMI#
LINT0
LINT1
HINIT#
FERR#
IGNNE#

6
6
6
6
6
6
6
6
6
6
4
4
32

32
28,31
5,7
32

8,32
8,32
8,32
8,32
8,32
8,32
8,10,32
8,32
8,32

A118
A114
A110
A106
A102
A98
A94
A90
A86
A82
A78
A74
A70
A66
A62
A58
A54
A50
A46
A42

7

6

5

4

B

A

REV:
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PROCESSOR CONNECTOR
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8

C

GND29
GND28
GND27
GND26
GND25
GND24
GND23
GND22
GND21
GND20
GND19
GND18
GND17
GND16
GND15
GND14
GND13
GND12
GND11
GND10

A38
A34
A30
A26
A22
A18
A10
A6
A2

A

A117
B116
A101
A103
A104
A105
B106
B107
A109
B110
A111
A115
A20
B23
A76
B75
B76
A13

PREQ#
PRDY#
BREQ0#
BREQ1#
RES4

FLUSH#

JP16

GND9
GND8
GND7
GND6
GND5
GND4
GND2
GND1
GND0

1
2
3

PICD0
PICD1
PICCLK

EMI_1
EMI_2
EMI_3
EMI_4
EMI_5

EMI2
EMI3
EMI4
EMI5

CPU Fan Header

A19
B22
B18

B61
B100
B81
B1
B41

EMI1

VCC12

BP2#
BP3#
BPM0#
BPM1#
BINIT#

SLOTOCC#
TDI
TDO
TRST#
TCK
TMS

4

R163 and R152 should be placed within 1" of ITP connector.

B19
A21
A23
B24
A24

B101
A9
A11
B11
B7
B10

TCK
TMS

B

DEP#0
DEP#1
DEP#2
DEP#3
DEP#4
DEP#5
DEP#6
DEP#7

B121 VCC3_3
B117 VCC3_2
B113 VCC3_1

TCK_R

TMS_R

J15

R138

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

A25
A27
B26
A28
B27
A29
A31
B28

B109 VCC5

R149
4,6 CPURST#
CPURST#_R
DBRESET# 240

VCCP19
VCCP18
VCCP17
VCCP16
VCCP15
VCCP14
VCCP13
VCCP12
VCCP11
VCCP10
VCCP9
VCCP8
VCCP7
VCCP6
VCCP5
VCCP4
VCCP3
VCCP2
VCCP1

VTT4
VTT3
VTT2
VTT1

ITP_PU_R

C 31

B105
B97
B93
B89
B85
B77
B73
B69
B65
B57
B53
B49
B45
B37
B33
B29
B25
B17
B13

B9
B5
A3
A1

J14

3

2

1

8

7

6

5

4

3

2

1

VCC2_5

Clock Synthesizer

VCC3_3

1

L20

1

2

L21

2

FBHS01L
Provide at least one 0.1uF decoupling cap per power pin.

FBHS01L

VCC2_5_CK133_FB

VCC_3_3_CK133_FB

10UF

0.1UF

0.1UF

0.1UF

0.1UF
R164

ICHPCLK
8
PCLK1
20
PCLK2
20
PCLK3
21
PCLK4
21
PCLK5
16
FWHPCLK
10
SIO_PCLK7
12
AGPCLK_CONN
19
MCH_CLK66
7
ICH_CLK66
9
TEST_CLK6637
ICH_48MHZ
9
ICH_14MHZ
9
SIO_14MHZ
12

33

33
R183

33

33
R187

33

33
R194

33

R201
R195
R211
R147

33
33
22

22

No stuff R106
for debug.
VCC1_8

VDDIR pin on DRCG should be decoupled at the component with a 0.1uF cap.
CLKTM and CLKTM# RC network must use 5% or better tolerance components.
VCC3_3
VCC2_5
2

VCC1_8

F u ncti on
A ll outputs Tri-S t ate
Res erved
A c tive 100M Hz , 48M Hz P LL inac t ive

0
1
1
1
1

O UT
IN
IN
O UT
O UT

O UT
IN
O UT
IN
O UT

A c tive 100M Hz , 48M Hz P LL ac tive
Tes t M ode
Res erved
A c tive 133M Hz ,48M Hz P LL inac tive
A c tive 133M Hz ,48M Hz P LL ac t ive*

9

DRCG_CTRL

MULT1_GPIO

1
2
3

1
10
16
22
3
9
VDDIR
VDDIPD
VDDO1
VDDO2
VDDP
VDDC

10K

10K

R199

10K

C204

C220

C209

B
Place C364 next to VDDP

DRCG_CLK
CLK
CLKB#

39-1%

CLKTM

R182

20
18

39-1%
DRCG_CLKB#

51-1%

51-1%

R185

R200

11

C363

CLKTM#

R205

11

No stuff C363

JP18

6

5

A

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CLOCK SYNTHESIZER
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5 OF 36

No stuff R161, JP11.

All jumpers may not be required, but are included for test purposes.

7

HCLKOUT
RCLKOUT

C196

C205
9,12
JP11

8

R204

10K

7
7

REFCLK
PWRDN#
STOPB#
MULT0
MULT1
S0
S1
GND
PCLKM
SYNCLKN
NC

C208

0.1UF

JP 17
IN
O UT
IN

DRCG_PWRDWN#
STOPB#
MULT0
MULT1

2
12
11
15
14
24
23
13
6
7
19

GNDO1
GNDO2
GNDP
GNDC
GNDI

JP 15
IN
IN
O UT

1
2
3

C364

17
21
4
8
5

S EL 133/ 100#
0
0
0

MULT0_GPIO

JP13 is for debug only. JP13

10K

JP 14
IN
OUT

9

VCC3_3

R217

S p rd S p e ct
E n a b le d *
D is a b le d

JP 18
OUT
OUT
OUT
1 -2

1

CLKTM_RD

A

JP 13
2 -3
OUT
2 -3
1 -2

R161

B

R219

U12
DRCG+

HOST
B U S /R A M B U S
1 0 0 /3 0 0
1 0 0 /4 0 0
1 3 3 /4 0 0
G P O C N TR L *

L22

FBHS01L

VCC3_3_DRCG_FB

1
7
13
19
20
24
52
48
44
40
38
29

VCC3_3

C

10UF

33

R210
ICH_CLK66_R
33
TEST_CLK66_R
R221
IHC_48MHZ_R
22
IHC_14MHZ_R
R150
SIO_14MHZ_R

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12

JP19 is for debug only.

R165
ICHPCLK_R
PCLK1_R
R169
PCLK2_R
PCLK3_R
R186
PCLK4_R
PCLK5_R
R191
FWHPCLK_R
SIO_PCLK7_R
MCH_CLK66_R 33

4PF

JP19

4
6
4

0.1UF

JP14

R189

CPUCLK3_R

0.1UF

JP15

Keep stubs on unused outputs as short as possible.
Tie CPUCLK and MCHCLK outputs together.

ITPCLK
MCHCLK
CPUHCLK

0.1UF

JP17

8
9
11
12
14
15
17
18
21
22
25
26
30
2
3

22
R184

22

8

CPU_DIV2

22

CPUHCLK_R

4

APICCLK

R148

0.1UF

SEL0

PCICLK_F
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7
3V66_0
3V66_1
3V66_2
3V66_3
48MHZ
REF0
REF1

SEL133/100#
PCISTOP#
CPUSTOP#
PWRDWN#
SPREAD#
SEL1
SEL0

R156

82PF

28
37
36
35
34
33
32

22
22

30

220

4,7
SEL133/100#
PCISTOP#
CPUSTOP#
CK133_PWRDWN#
SPREAD#
SEL1

C

XTAL_IN
XTAL_OUT

PICCLK

22

R151

5
6

R155
PICCLK_R
APICCLK_R
APIC2_R
CPU_DIV2_1_R
CPU_DIV2_2_R
R188
ITPCLK_R

30

10PF

53
54
55
50
49
41
42
45
46

R166

R224

10K

10K
R192

10K
R196

10K
R197

10K
R202

10K
R203

10PF

APIC0
APIC1
APIC2
CPU_DIV2_1
CPU_DIV2_2
CPUCLK0
CPUCLK1
CPUCLK2
CPUCLK3

R170

C189

30

1
2
14.318MHZ

2_5V

C185

R206

56
51
47
43

CK133_XOUT
VCC3_3

D

33

Y3
XTAL
VCC3_3

R220

CK133_XIN

VDD25V_1
VDD25V_2
VDD25V_3
VDD25V_4

VDD3V_1
VDD3V_2
VDD3V_3
VDD3V_4
VDD3V_5
VDD3V_6
VDD3V_7

10UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

D

4
10
16
23
27
39
31

C180 C190 C192 C199 C171
U11
CK133

C207 C215 C223 C186 C198 C206 C214 C170

4

3

2

1

3

RAMREF

2

VTT1_5

VTT1_5

75-1%

R143

0.001UF

150-1%

R144
C187

80.6-1%

R160

C

MCH_AGPREF

470PF

VCC1_8

B

RS#[2:0]
3

RAMREF

6,11

HREQ#[4:0]
3
VCC1_8

MCHCLK

V2

RSTIN#
HLCOMP

F20
A18

PCIRST#
MCH_HLCOMP

TEST/GRCOMP

T15

GRCOMP

5

MCH_AGPREF_CG

Place MCH_AGPREF circuit near the MCH.

4
4
4
4
4
4
4
4
4
4
4

HCLKIN

80.6-1%

19
R153

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

1K-1%

H1
G4
E4
E3
G2

MCH_AGPREF_CV

162-1%

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

470PF

562-1%

RS#0
RS#1
RS#2

C183

VDDQ

R154

E5
C1
E2

C158

1K-1%

RS#0
RS#1
RS#2

GTLREF1

R159

CPURST#
HADS#
BNR#
BPRI#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HTRDY#

GTLREF2

C182

P4
D2
F5
G1
D1
F2
F1
D3
E1
F3
F4

3

R190

CPURST#
ADS#
BNR#
BPRI#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HTRDY#

D

HA#[31:0]

R181

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

0.001UF

J1
H3
H4
G5
K2
H5
H2
J4
L1
J5
K1
J2
K5
K3
L4
K4
L2
N2
M3
M2
M1
N5
M4
P1
N1
P2
P3
N4
M5

R130

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

75-1%

0.1UF

R131
HOST

1

6,11

C203

0.1UF

GTLREFA
GTLREFB

HOST

VCC1_8;D4,E6,F6,G6,E7,R6,R7,E8,E9,D10,D11,E12
VCC1_8;E13,E14,F14,T14,E15,P15,B17,C17,C19
VDDQ;F15,R15,J17,L17,N17,T17
GND;A1,A3,G3,J3,L3,N3,R3,V3,B4,D5,L5,U5,B6,D6,D7,V7,B8,D8
GND;D9,J9,K9,L9,M9,V9,B10,J10,K10,L10,M10,C11,J11,K11,L11
GND;M11,V11,C12,D12,J12,K12,L12,M12,B13,D13,V13,T13,D14
GND;B15,D15,B16,D16,E16,F16,A17,E18,V18,A19,H19,K19,M19
GND;P19,T19,D20

0.1UF

6
6

C3
V12

7

RAMREFA
RAMREFB

Y1
U2
W4
W3
V4
U4
T3
Y4
Y5
T4
V5
T5
Y6
W5
U6
V6
W6
T6
W7
U7
Y8
Y7
T8
W8
T7
W9
U8
W10
Y10
V8
U9
Y9
W11
T9
Y11
T10
T12
U10
V10
W12
T11
U13
Y13
Y12
W14
U11
U12
Y14
V14
W13

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

AGPREF

8

U10
MCH_096
R2
R1
R4
P5
T1
R5
V1
Y2
W1
U1
T2
Y3
W2
U3

E11
E10

A

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HUBREF

B

GTLREF2
GTLREF1

C155

U14

C

0.01UF

E20

D

4
R168
100-1%
C191

MCH
HD#[63:0]

5
RAMREF_R

CONN_AGPREF

R180

C194 19

3

6

HUBREF

150-1%

7
8,37

40.2-1%

8

8,10,11,12,16,19,20,21,22

A

R129

Place R129 and R180 less than 0.5" from MCH using 10 mil trace.

40.2-1%

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
REV:
MCH
1.01
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-24-1999_11:15
6 OF 36

6

5

4

3

2

1

8

7

6

5

4

3

2

1

MCH
U10
MCH_096

B

5
VCC1_8

C361
C359

0.1UF

C360

0.1UF

C362

A

19,32
19,32

GFRAME#
GDEVSEL#
GIRDY#
GTRDY#
GSTOP#
GPAR
GREQ#
GGNT#
PIPE#

19,32
19,32
19,32

0.1UF

19,32

G_FRAME#
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
PIPE#

W18 CLK66

RBF#
WBF#

V16 RBF#
V15 WBF#
ST0
ST1
ST2

ST[2:0]

0.1UF

L16
N19
N20
M20
M18
K16
U15
Y16
W16

MCH_CLK66

19
19,32
19,32

G_C/BE#0
G_C/BE#1
G_C/BE#2
G_C/BE#3

W15
Y15
Y17

ADSTB0
ADSTB#0

J19
H20
R18
R19
Y20
Y19

ADSTB1
ADSTB#1
SBSTB
SBSTB#

MEMORY

HL_STB
HL_STB#

D19
C20

HL_STB
HL_STB#

RCLKOUT
HCLKOUT

B1
A2

8

D

7,8,37

C7
B7
C6
A6
C5
A5
B5
A4
C4

LDQB0
LDQB1
LDQB2
LDQB3
LDQB4
LDQB5
LDQB6
LDQB7
LDQB8

RQ0
RQ1
RQ2
RQ3
RQ4
RQ5
RQ6
RQ7

A7
C8
A8

LCOL0
LCOL1
LCOL2
LCOL3
LCOL4
LROW0
LROW1
LROW2

11

VCC3_3SBY

U14
9,16,29,31

VCC
12

13

PWROK

SN74LVC07A

C

PWROK_CTRL
7

GND

LDQB[8:0]
11

LSCK and LCMD must neck down to 5 mils for 175 mils at Q10 and Q9 attach points.
Place Q10 and Q9 as close as possible to MCH.
VCC5SBY
LCOL[4:0]
11

LSCK

4.7K

B

11

LROW[2:0]
11

LCLKTM
LCLKTM#
LCLKFM
LCLKFM#

B11
A11
A12
B12

VCC3_3SBY

R248

DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8

5
5
LDQA[8:0]

14

LDQA0
LDQA1
LDQA2
LDQA3
LDQA4
LDQA5
LDQA6
LDQA7
LDQA8

11
11
11
11

SCK_CTRL
C

Q10
3

1

B

7

E

C

Q14

2
PWROK_CTRL

B

1

3
2
E

ST0
ST1
ST2
AD_STB0
AD_STB#0
AD_STB1
AD_STB#1

CMD
SCK
SIO

B3
B2
C2

SBA0
SBA1

W20
V17
Y18
W17
V20
W19
V19
U16

SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

AGP

SB_STB
SB_STB#

LCMD 11
C

Q9

LSIO

11
SBA[7:0]

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

B
19

1

3
2
E

A

REV:
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
MCH
1.01
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-18-1999_11:34
7 OF 36

No stuff. For test only.

8

8.2K

4,5

4.7K

RCLKOUT
HCLKOUT

A13
C13
A14
C14
B14
C15
A15
C16
A16

CTM
CTM#
CFM
CFM#

SEL133/100#

8,37
8,37

DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8

C9
B9
A9
A10
C10

R209

HL10

MMBT3904LT1

19,32
19,32
19,32
19,32
19,32
19,32
19,32
19,32
19,32

H16
L20
N18
R16

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10

R346

GC/BE#0
GC/BE#1
GC/BE#2
GC/BE#3

AGP

F19
F18
E17
E19
B20
B19
B18
A20
D17
C18
D18

MMBT3904LT1

GC/BE#[3:0]
19

HUB

HL[10:0]

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10

MMBT3904LT1

C

G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD10
G_AD11
G_AD12
G_AD13
G_AD14
G_AD15
G_AD16
G_AD17
G_AD18
G_AD19
G_AD20
G_AD21
G_AD22
G_AD23
G_AD24
G_AD25
G_AD26
G_AD27
G_AD28
G_AD29
G_AD30
G_AD31

8.2K

D

F17
G18
G17
G19
G16
G20
H17
H18
J20
J16
K17
K18
J18
L19
K20
L18
M17
P18
M16
P17
N16
P20
P16
R20
T20
R17
U17
T16
U18
T18
U20
U19

7

GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

R227

GAD[31:0]
19

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

ICH
U13
ICH_096

5

CBE0#
CBE#1
CBE#2
CBE#3

DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PCIRST#
PLOCK#
SERR#
PERR#
PCI_PME#
REQ#A
GNT#A

D9
B3
A2
C4
D5
A9
J5
B9
A1
E9
K1
N6

DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PCIRST#
PLOCK#
SERR#
PERR#/GPIO7
PME#
GPIO0/REQ#A

P5

GPIO16/GNT#A

ICHPCLK

C14

PCICLK

HUB

AD22
AD23
AD24
AD25
AD26
AD27
AD28

HL0

D17

HL1
HL2
HL3
HL4
HL5

E17
F17
G16
J15
K16

HL6
HL7
HL8
HL9

K17
L17
H15
J17

HL10
HL11

J14
F16
G17
H17
M17
J13

HL_STB
HL_STB#
HLCOMP
HUBREF

PCI

4,32
4,32
4,32
4,32
4,10,32
4,32
4,32
4,32
4,32
12,32
12,32
HL[10:0]

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HL11_TP

D

7

Place R239 less than 0.5" from the ICH using a 10 mil trace.
VCC1_8

TP1

HL_STB
HL_STB#
ICH_HLCOMP

7,37

C

7,37
HUBREF

6,8,37

C237

IRQ

PCI

PIRQA#
PIRQB#
PIRQC#

D10

PIRQD#

C10

PIRQ#A
PIRQ#B
PIRQ#C
PIRQ#D

IRQ14
IRQ15
APICCLK
APICD0
APICD1
SERIRQ

P11
N14
C16
E16
C17
R4

IRQ14
IRQ15
APICCLK
PICD0
PICD1
SERIRQ

A10
B10

REQ#0 A14
REQ#1 B13
REQ#2 B12
REQ#3 D12
REQ#4 B11
P4
GPIO1/REQ#B/REQ#5

PREQ#0
PREQ#1
PREQ#2
PREQ#3
PREQ#4
PREQ#5

A13
C13
A12
C12

PGNT#0
PGNT#1
PGNT#2
PGNT#3
PGNT#4
PGNT#5

GNT#0
GNT#1
GNT#2
GNT#3

GNT#4 A11
GPIO17/GNT#B/GNT#5 R5

16,19,20,21,32
19,20,21,32
20,21,32
20,21,32

0.01UF
Place C237 close to ICH.

22,32
22,32
5
4,32
4,32
12,21,32

VCC1_8

B

20,32
20,32
21,32
16,32
32
21,32

6,8,37

20,32
20,32
21,32
16,32
32
21,32

301-1%

D2
B2
A3
D6

ICH_A

E15
E14
B16
F14
A17
A15
B15

A20M#
SLP#
FERR#
IGNNE#
HINIT#
LINT0
LINT1
SMI#
STPCLK#
KBRST#
A20GATE

R225

B

C_BE#0
C_BE#1
C_BE#2
C_BE#3

CPU

IGNNE#
INIT#
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE

F13
E12
F15
B17

301-1%

16,20,21,32
16,20,21,32
16,20,21,32
16,20,21,32
16,20,21,32
16,20,21
6,10,11,12,16,19,20,21,22
20,21,32
16,20,21,32
16,20,21,32
16,19,20,21
21,32
21,32

AD29
AD30
AD31

B1
D4
C3
A4
B4
C5
C6
B5
E7

A20M#
CPUSLP#
FERR#

R226

C_BE#[3:0]
16,20,21

A6
B6
D7
B8
A7
A8
B7
C9
D8
C7

D1
D3
E4
C2
C1

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13’
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21

R239

C

G2
G4
F2
F3
F4
F5
E1
E2

40.2-1%

D

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

VCC1_8;G13,H14,K14,G15,L15,H16,J16
VCC3_3;C11,E13,N13,R13,M14,D16,T16
VCC3_3;E3,A5,E5,G5,N5,E6,P6,T7,C8,U10
GND;R2,G3,H8,J8,K8,H9,J9,K9,H10,J10,K10,G14,K15

AD[31:0]
16,20,21

HUBREF

C218
0.1UF

Place HUBREF circuit between MCH and ICH
HUBREF voltage = 0.9V +/- 2%

A

A

REV:
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
ICH
1.01
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-24-1999_11:14
8 OF 36

8

7

6

5

4

3

2

1

6

5

4

C246
+
1UF

R317

R254
8.2K

1K

R233

C247
+

1K
VBAT_RTC

3,11,32
3,11,32
32

2

2.2UF

R250

VBAT_RC

12
12

C249

+

2 1

C
3

1

8.2K

8.2K

R232
8.2K

R247

BAT1

10M
5
5
5

R249
10M
Y4
XTAL

Use CR2032 battery.

S tra p
S afe M ode
ICH s trap*

JP 5
IN
O UT

12PF

JP 26
IN
O UT

12PF

C250

S tra p
No W D Reboot
Reboot on W D*

15
13,15
13,15
9,13,15
13,15
15
9,18

2
1
32.768KHZ
C251

R212
8.2K

R215

B

CM O S
Norm al*
Clear

8.2K
21

R98

PCI_TEST

5
18
16,32
16,32

0K
R162
DRCG_CTRL

5

0K
No stuff R98.

JP 20
1-2
2-3

10,12
10,12
10,12
10,12

VCC3_3SBY

12

R238

9,18

8.2K

SPKR

VCC3_3

10,12
23
23
23
23

A

R90

JP26

SPKR_STRAP

2.7K

SMBDATA_CORE
SMBCLK_CORE
SMB_ALERT

J1

SMBDATA

J2
M1

SMBCLK
GPIO11/SMBALERT#

23
23

LPC_SMI#
LPC_PME#
INTRUDER#

E11

GPIO6

D11
J4

GPIO5
GPIO10/INTRUDER#

RTCRST#
VBIAS
RTCX1
RTCX2

H1

RTCRST#

H2
H3
H4

VBIAS
RTCX1

ICH_CLK66
ICH_14MHZ
ICH_48MHZ

A16
U6
U2

CLK66
CLK14
CLK48

AC_RST#
AC_SYNC
AC_BITCLK
AC_SDATAOUT
AC_SDATAIN0
AC_SDATAIN1
SPKR

T1
T3

AC_RST#
AC_SYNC
AC_BIT_CLK
AC_SDOUT
ACSDIN0
GPIO9/AC_SDIN1
SPKR

GPIO12
GPIO13
GPIO21
MULT0_GPIO
GPIO23_FPLED
ALERTCLK_SBY
ALERTDATA_SBY

N4
L2
B14
D13
D15

LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ#0
GPIO8
LFRAME#/FWH4

R6
U5
T5
T4

USBP1P
USBP1N
USBP0P
USBP0N
OC#1
OC#0

R1
P2
P1
N2
M4
M3

M5
L5

T6
N3
U4

GPIO12
GPIO13
GPIO21
GPIO22

ICH_B

R12
T12

PDA0
PDA1
PDA2
SDA0
SDA1
SDA2

P12
M16
M15
L13

AC97

IDE

GPIO

PDD13
PDD14
PDD15

P9
T10
P10

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

P15
R16
T17
U16
U15
R14
P13
T13
U14
T14
P14
T15
U17
R15
R17
P16

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

LPC

USB

0.1UF

A

-C

D
22
22
22
22

PDA[2:0]
22
SDA[2:0]
22

PDREQ
SDREQ
PDDACK#
SDDACK#
PDIOR#
SDIOR#
PDIOW#
SDIOW#
PIORDY
SIORDY
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

PDD0 R10
PDD1 N9
PDD2 R9
PDD3 U9
PDD4 R8
PDD5 U8
PDD6 R7
PDD7 U7
PDD8 P7
PDD9 N7
PDD10 T8
PDD11 P8
PDD12 T9

LFRAME#/FWH4
USBP1+
USBP1USBP0+
USBP0OC1#
OC0#

PDA0

PDDREQ U11
SDDREQ P17
PDDACK# U12
SDDACK# M13
PDIOR# R11
SDIOR# N16
PDIOW# T11
SDIOW# N15
PIORDY N11
SIORDY N17

GPIO23
GPIO27/ALERT_CLK
GPIO28/ALERT_DATA
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ0#
GPIO8/LDRQ1#

PDCS#1
SDCS#1
PDCS#3
SDCS#3

SDA0
SDA1
SDA2

RTCX2

R3
T2
U1
P3
U3

N12
L14
U13
L16

PDA1
PDA2

SYSTEM

0.047UF

+

CR5

BAT17

A

RTC_CLR

L3
F1

PDCS1#
SDCS1#
PDCS3#
SDCS3#

+

BAT17

R241

L4
K4

THRM#
GPIO24/SLP_S3#
SLP_S5#
PWROK
PWRBTN#
RI#
RSMRESET#
GPIO25/SUSSTAT#
SUSCLK/GPIO26

C233

CR3

2
3

D14
K3
K2
J3
M2

2

VCC5REF

VCC3_3
JP20
1

RTC_RST_JP

THRM#
3
SLP_S3#
SLP_S5#
PWROK
PWRBTN#
ICH_RI#
RSMRST#
MULT1_GPIO
GPIO26_FPLED

VCCSUS1

VBAT_CR

8.2K

C15

R231
29,31
30
7,16,29,31
18
25
17,31
5,12
18

2

VCCSUS

1
1K

L1

VCCRTC

R245

D

N1

VCC3_3

C234
+

1

G1

CR4

-C

VCC5

VCC5_REF
U13
ICH_096

BAT17

A

1
VCC3_3

VCC_RTC_JP
+

2

1UF

ICH

C-

3

VCC3_3SBY

1K

7
VCC3_3SBY

R230

8

22
22
22
22
22
22
22
22
22
22
PDD[15:0]

C

22

B
SDD[15:0]
22

A

R341

AC_SDOUT_STRAP
2.7K
JP5

AC_SDATAOUT

8

7

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
ICH
DRAWN BY:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
FOLSOM, CALIFORNIA 95630
12-2-1999_16:22

9,13,15

6

5

4

3

2

1

REV:
1.01
PROJECT:
SHEET:
9 OF 36

8

7

6

5

4

3

2

1

FWH
VCC3_3

D

C301

C298

C297

C308
0.1UF

VCC3_3

0.1UF

Do not tie Vpp to 12V. Vpp should be tied
to VCC3_3 for onboard programming.

0.1UF

VCC3_3

0.1UF

D

U16
C305

C300

0.1UF

0.1UF

1
FWH_IC 2
8.2K
3
4
5
6
R298
FGPI4 7
8.2K
8
FWHPCLK
9
10
VPP_R
11
PCIRST#
12
13
14
R300
15
FGPI3
8.2K
FGPI2
16
FGPI1
17
FGPI0
18
R296

C

5
R299
0K
6,8,11,12,16,19,20,21,22

R303
22
22

S66DETECT
P66DETECT

R305
R306

8.2K

0K

0K

19
20

15K

R307

15K

R304

For drive side detection, stuff R304,R307. No stuff R305,R306.
For host side detection, stuff R304,R305,R306,R307.

NC1
IC
NC3
NC4
NC5
NC6
FGPI4
NC8
CLK
VCC10
VPP
RST#
NC13
NC14
FGPI3
FGPI2
FGPI1
FGPI0
WP#
TBL#

FWH

GNDA
VCCA
FWH4
INIT#
RFU36
RFU35
RFU34
RFU33
RFU32
VCC31
GND30
GND29
FWH3
FWH2
FWH1
FWH0
ID0
ID1
ID2
ID3

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

LFRAME#/FWH4
HINIT#

9,12
4,8,32

C

LAD3/FWH3
LAD2/FWH2
LAD1/FWH1
LAD0/FWH0

9,12
9,12
9,12
9,12

VCC3_3

VCC3_3

R308

WPROT

4.7K

B

B

JP21

Top Block Lock
TBLK_LCK

4.7K

R310

FW H
O UT
IN

JP 21
Loc k ed
U n lo c k e d *

A

A

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
REV:
FWH
1.01
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-18-1999_10:44
10 OF 36

8

7

6

5

4

3

2

1

8

7

6

5

4

2

As shown, RIMMs are 184-pin connectors.

7

LDQB[8:0]
7

LROW[2:0]
7
LCOL[4:0]
7

7
7
7
7
7
7
7
6,11

A10
B8
A8
B6
A6
B4
A4
B2
A2
B24
A26
B26
A28
B28
A30
B30
A32
B32

LDQA0
LDQA1
LDQA2
LDQA3
LDQA4
LDQA5
LDQA6
LDQA7
LDQA8
LDQB0
LDQB1
LDQB2
LDQB3
LDQB4
LDQB5
LDQB6
LDQB7
LDQB8

LROW2
LROW1
LROW0
LCOL4
LCOL3
LCOL2
LCOL1
LCOL0

B16
A18
B18
A20
B20
A22
B22
A24

LROW2
LROW1
LROW0
LCOL4
LCOL3
LCOL2
LCOL1
LCOL0

LCLKFM
LCLKFM#
LCLKTM
LCLKTM#

B10 LCFM
B12 LCFM#
A14 LCTM
A12 LCTM#

LCMD
LSCK
LSIO

B34
A34
B36

RAMREF

LCMD
LSCK
SIO/SIN

A51 VREFA
B51 VREFB

3,9,11,32
SMBCLK_CORE

A53
A55
A57
B56
A56

SMBDATA_CORE
3,9,11,32

C228
0.1UF

J18
RIMM
RCMD
RSCK
SIO/SOUT

SCL
SDA
SWP
SVDDB

RCMD_A
B59
RSCK_A
A59
A36 MR1OUT 11

B59
A59
A36

RCMD
RSCK
SIO/SOUT

RDQA0
RDQA1
RDQA2
RDQA3
RDQA4
RDQA5
RDQA6
RDQA7
RDQA8
RDQB0
RDQB1
RDQB2
RDQB3
RDQB4
RDQB5
RDQB6
RDQB7
RDQB8

A83
B85
A85
B87
A87
B89
A89
B91
A91
B69
A67
B67
A65
B65
A63
B63
A61
B61

RDQA0_A
RDQA1_A
RDQA2_A
RDQA3_A
RDQA4_A
RDQA5_A
RDQA6_A
RDQA7_A
RDQA8_A
RDQB0_A
RDQB1_A
RDQB2_A
RDQB3_A
RDQB4_A
RDQB5_A
RDQB6_A
RDQB7_A
RDQB8_A

A83
B85
A85
B87
A87
B89
A89
B91
A91
B69
A67
B67
A65
B65
A63
B63
A61
B61

RDQA0
RDQA1
RDQA2
RDQA3
RDQA4
RDQA5
RDQA6
RDQA7
RDQA8
RDQB0
RDQB1
RDQB2
RDQB3
RDQB4
RDQB5
RDQB6
RDQB7
RDQB8

RROW0
RROW1
RROW2
RCOL0
RCOL1
RCOL2
RCOL3
RCOL4

B75
A75
B77
A69
B71
A71
B73
A73

RROW0_A
RROW1_A
RROW2_A
RCOL0_A
RCOL1_A
RCOL2_A
RCOL3_A
RCOL4_A

B75
A75
B77
A69
B71
A71
B73
A73

RROW0
RROW1
RROW2
RCOL0
RCOL1
RCOL2
RCOL3
RCOL4

RCFM
RCFM#
RCTM
RCTM#

B83
B81
A79
A81

RCFM_A
RCFMN_A
RCTM_A
RCTMN_A

B83
B81
A79
A81

RCFM
RCFM#
RCTM
RCTM#

SA0
SA1
SA2

B53
B55
B57

RSRV4/RESET

B38

VCC3_3

B53
B55
B57

B38

SA0
SA1
SA2

VCMOS1_8SBY;A35,A37,B35,B37
VCC2_5SBY;A41,A42,A54,A58,B41,B42,B54,B58
GND;A1,A3,A5,A7,A9,A11,A13,A15,A17,A29,A21,A23,A25,A27,A19,A31,A33,A39
GND;A52,A60,A62,A64,A66,A68,A70,A72,A74,A76,A78,A80,A82,A84,A86,A88,A90,A92
GND;B1,B3,B5,B7,B9,B11,B13,B15,B17,B29,B21,B23,B25,B27,B19,B31,B33,B39
GND;B52,B60,B62,B64,B66,B68,B70,B72,B74,B76,B78,B80,B82,B84,B86,B88,B90,B92
NC;A43,A44,A45,A46,A47,A48,A49,A50,B43,B44,B45,B46,B47,B48,B49,B50 RSV_SRIMM:
NC;A16,A77,B14,B79 RSV_EXP:
NC;A38,A40,B40 RSV_SPARE:

C

J16
RIMM
LDQA0
LDQA1
LDQA2
LDQA3
LDQA4
LDQA5
LDQA6
LDQA7
LDQA8
LDQB0
LDQB1
LDQB2
LDQB3
LDQB4
LDQB5
LDQB6
LDQB7
LDQB8

VCMOS1_8SBY;A35,A37,B35,B37
VCC2_5SBY;A41,A42,A54,A58,B41,B42,B54,B58
GND;A1,A3,A5,A7,A9,A11,A13,A15,A17,A29,A21,A23,A25,A27,A19,A31,A33,A39
GND;A52,A60,A62,A64,A66,A68,A70,A72,A74,A76,A78,A80,A82,A84,A86,A88,A90,A92
GND;B1,B3,B5,B7,B9,B11,B13,B15,B17,B29,B21,B23,B25,B27,B19,B31,B33,B39
GND;B52,B60,B62,B64,B66,B68,B70,B72,B74,B76,B78,B80,B82,B84,B86,B88,B90,B92
RSV_SRIMM: NC;A43,A44,A45,A46,A47,A48,A49,A50,B43,B44,B45,B46,B47,B48,B49,B50
RSV_EXP: NC;A16,A77,B14,B79
RSV_SPARE: NC;A38,A40,B40

LDQA[8:0]

D

RSRV4/RESET

A10
B8
A8
B6
A6
B4
A4
B2
A2
B24
A26
B26
A28
B28
A30
B30
A32
B32

TERM_DQA0
TERM_DQA1
TERM_DQA2
TERM_DQA3
TERM_DQA4
TERM_DQA5
TERM_DQA6
TERM_DQA7
TERM_DQA8
TERM_DQB0
TERM_DQB1
TERM_DQB2
TERM_DQB3
TERM_DQB4
TERM_DQB5
TERM_DQB6
TERM_DQB7
TERM_DQB8

LROW2
LROW1
LROW0
LCOL4
LCOL3
LCOL2
LCOL1
LCOL0

B16
A18
B18
A20
B20
A22
B22
A24

TERM_ROW2
TERM_ROW1
TERM_ROW0
TERM_COL4
TERM_COL3
TERM_COL2
TERM_COL1
TERM_COL0

6,8,10,12,16,19,20,21,22

3,9,11,32
3,9,11,32

TERM_DQB[8:0]
33

TERM_ROW[2:0]

TERM_COL[4:0]
33

R287

LCMD
LSCK
SIO/SIN

B34
A34
B36

33
33

C291
0.1UF

VREFA A51
VREFB B51

B

A53
VCC3_3

A55
A57
B56
A56

C165

0.1UF

SMBCLK_CORE
SMBDATA_CORE

R229
4.7K

C243

0.1UF

6,11

C236

0.1UF

0.1UF

A

Do not stuff R228

R228
4.7K

5
5

TERM_CMD
TERM_SCK
MR1OUT11

C256

0.1UF

CTERM_RIMM

R286
28-1%

CLKTM#

RAMREF

SWP

C

33

28-1%

C169

A

D

33

CLKFM
CLKFM#
CLKTM

LCFM B10
LCFM# B12
LCTM A14
LCTM# A12

SVDDA

PCIRST#

TERM_DQA[8:0]

LDQA0
LDQA1
LDQA2
LDQA3
LDQA4
LDQA5
LDQA6
LDQA7
LDQA8
LDQB0
LDQB1
LDQB2
LDQB3
LDQB4
LDQB5
LDQB6
LDQB7
LDQB8

SCL
SDA
SWP
SVDDB

SVDDA
VCC3_3

VCC3_3

8

1

R500
8.2K

2 RIMM Sockets

B

3

MR2OUT

REV:
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
RIMM SOCKETS
1.01
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-24-1999_13:14
11 OF 36

7

6

5

4

3

2

1

8

7

6

5

4
VCC5

3

2

1

VCC3_3

9
8,12,21,32

SIO_PCLK7

5,12
KBDAT

26

KBCLK
MDAT
MCLK

26
26
26

KBRST#
A20GATE

8,32
8,32

IRRX
IRTX

18
18

C

C320

C317

470PF

470PF

25
25
25
25
25
25
25
25

25
25

LPC header. For debug only.

B

J20
9,10,12
LAD3/FWH3
9,10,12
LAD2/FWH2
9,10,12
LAD1/FWH1
9,10,12
LAD0/FWH0
9,10,12
LFRAME#/FWH4
6,8,10,11,12,16,19,20,21,22 PCIRST#
5,12
SIO_PCLK7
9,12
LDRQ#0
5,9
8,12,21,32

MULT1_GPIO
SERIRQ

1
3
5
7
9
11
13
15
17
19
21
23
25
27

2
4
6
8
10
12
14
16
18
20
22
24
26
28

26
26
26
26
26
26
26
26
26
26
26
26
26
26

A

84
85
86
87
88
89
90
91

RXD1
TXD1

95
96
97
98
99
100
92
94
2
1
3
5
8
9
10
11

RXD1
TXD1
DSR1#
RTS1#
CTS1#
DTR1#
RI1#
DCD1#

RXD2_IRRX
TXD2_IRTX
DSR2#
RTS2#
CTS2#
DTR2#
RI2#
DCD2#

RDATA#
DSKCHG#

12
13
14
15
16
4

DRVDEN1
DRVDEN0
MTR0#
DS0#
DIR#
STEP#
WDATA#
WGATE#
HDSEL#
INDEX#
TRK0#
WRTPRT#
RDATA#
DSKCHG#

SIO_14MHZ

6
19

CLKI32
CLOCKI

DIR#
STEP#
WDATA#
WGATE#
HDSEL#
INDEX#
TRK#0
WRTPRT#

53
65
93

80
81
82
83

FAN2/GP32
FAN1/GP33

54
55

FDC_PP/DDRC/GP43

28

PARALLEL PORT I/F

SIO
LPC47B27X
KYBD/MSE I/F

INFRARED I/F

PAR_INIT#

VCC3_3

24

SLIN#
PDR7
PDR6
PDR5
PDR4
PDR3
PDR2
PDR1
PDR0
SLCT
PE
BUSY
ACK#
ERR#
AFD#
STB#

D

24
24

PDR[7:0]

1
C349
+

IRRX2/GP34
IRTX2/GP35

VCC1
VCC2
VCC3

61
62

VREF
VTR

KDAT
KCLK
MDAT
MCLK
KBDRST
A20GATE

PCI_CLK

VCC5
66
67
75
74
73
72
71
70
69
68
77
78
79

INIT#
SLCTIN#
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
SLCT#
PE
BUSY
ACK#
ERROR#
ALF#
STROBE#

LPC I/F

C309

C348

C321

C313

0.1UF

0.1UF

0.1UF

0.1UF 0.1UF

C323

2

24
24
24
24
24

Place next to VREF.

2.2UF

Place decoupling caps near each power pin.

24
24

PWM2

18

PWM1

C

18

SERIAL PORT 1

VCC3_3

SERIAL PORT 2

FDC I/F

CLOCKS

7
31
60
76

5

DRVDEN#1
DRVDEN#0
MTR#0
DS#0

56
57
58
59
63
64

RXD0
TXD0
DSR#0
RTS#0
CTS#0
DTR#0
RI#0
DCD#0

DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

25
25
25
25
25
25

LFRAME#
LAD3
LAD2
LAD1
LAD0
LDRQ#
LRESET#
LPCPD#
PME#
SERIRQ

GP60/LED1
GP61/LED2
GP27/IO_SMI#
GP30/FAN_TACH2
GP31/FAN_TACH1
GP25/MIDI_IN
GP26/MIDI_OUT

48
49
50
51
52
46
47

GP10/J1B1
GP11/J1B2
GP12/J2B1
GP13/J2B2
GP14/J1X
GP15/J1Y
GP16/J2X
GP17/J2Y
GP20/P17
GP21/P16
GP22/P12

32
33
34
35
36
37
38
39
41
42
43

GP24/SYSOPT

45

LPC_SMI#
TACH2
CPU_TACH1
MIDI_IN
MIDI_OUT
J1BUTTON1
J1BUTTON2
J2BUTTON1
J2BUTTON2
JOY1X
JOY1Y
JOY2X
JOY2Y
KEYLOCK#

9
18

4.7K

9,10,12
9,10,12
9,12
6,8,10,11,12,16,19,20,21,22

24
23
22
21
20
25
26
27
17
30
29

R313

LAD3/FWH3
LAD2/FWH2
LAD1/FWH1
LAD0/FWH0
LDRQ#0
PCIRST#
LPCPD#
LPC_PME#
SERIRQ

B

27
27
27
27
27
27
27
27
27
27
18

SYSOPT
Pulldown on SYSOPT for IO address of 0x02E
R312

8 7 6 5

4.7K

LFRAME#/FWH4

AVSS

RP5

4.7K

1 2 3 4

9,10,12
9,10,12
9,10,12

A

4.7K

40

R315

D

44

U17

GND1
GND2
GND3
GND4

VCC3_3

26 VCC5_KBMS_J

18

Super I/O

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
REV:
SUPER I/O
1.01
DRAWN BY:
PROJECT:
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R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
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11-18-1999_10:46
12 OF 36

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

AC’97 Audio
VCC3_3
VCC12
VR2
MC78M05CDT

1

10UF

0.1UF
2

C49

C21

AGND

AGND

C77
C48

+

C62

0.1UF

1

GND 4

C83

10UF

2

13,14

VCC3_3

L17

13,14

D

No stuff C358.
C358
0.1UF

0.1UF

2
C57

+

1

VCC5_AUDIO

0.1UF

3

+5V
1 VIN

0.1UF

VCC5_AUDIO

D

AGND

AGND

0.1UF
R67

AC97_SPKR_R
C76
0.1UF

VCC3_3

10PF

R29

No stuff C84.
100K
No stuff

R28

14

100K
No stuff

14

AC_XTAL_IN
Y1
XTAL
AC_XTAL_OUT

C94

C95

2
24.576MHZ

2

22PF

1
22PF

C16

EAPD

0.1UF
C17

+
C1
2

1UF-TANT

2

0.047UF

1

+
C7

C18

15
9,15
9,15
9,15
9,15

C84

1

1

1UF-TANT

C19

46
45
48
47

AUD_VREFOUT

AC_VREF_C

270PF-NPO

CS1
CS0
CHAIN_CLK
EAPD

Series resistors are for test purposes only.
PRI_DWN_RST#_R
PRI_DWN_RST#
R31
AC_SDATAOUT_R 0K
AC_SDATAOUT
R77
AC_SDATAIN_R
AC_SDATAIN0
R116 0K
0K
AC_SYNC_R
AC_SYNC
R106
0K
AC_BITCLK
AC_BITCLK_R
R56
0K

2
3

28
27

34 CX3D_C
33 RX3D_C
31 FILT_R_C
32
30
29

270PF-NPO

11
5
8
10
6

XTL_IN
XTL_OUT

CX3D
RX3D
FILT_R
FILT_L
AFLIT2
AFILT1
AFILT1_C
AFILT2_C
FILT_L_C

A

RESET#
SDATA_OUT
SDATA_IN
SYNC
BIT_CLK

B
VREFOUT
VREF

14

AD1881

+
C9
10UF-TANT

14

C

NC43
NC44
NC40

B

43
44
40

15

AVSS1
AVDD1

15

PC_BEEP
LINE_IN_R
LINE_IN_L
MIC1
MIC2
CD_R
CD_L
CD_REF
VIDEO_R
VIDEO_L
AUX_L
AUX_R
PHONE
MONO_OUT
LINE_OUT_R
LINE_OUT_L
LNLVL_OUT_R
LNLVL_OUT_L

AVSS2
AVDD2

14
14
14

AC97_SPKR_C 12
24
23
21
22
CD_R
20
CD_L
18
CD_REF
19
17
C63
16
MONO_PHONE 2
1
+
14
1UF-TANT
15
MONO_PHONE_C
13
C12
2
1 MONO_OUT_C
MONO_OUT
37
+
36
1UF-TANT
35
LNLVL_OUT_R
41
LNLVL_OUT_L
39
LINE_IN_R
LINE_IN_L
MIC_IN

9 DVDD2
7 DVSS2

1 DVDD1
4 DVSS1

14
14
14

1UF-TANT C70
2
1
+

42
38

U2

26
25

C85

C

C20

1K

10K

0.1UF

AC97_SPKR

R66

18

A

AGND
AGND

8

7

6

5

4

REV:
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
AUDIO
1.01
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-18-1999_10:46
13 OF 36

3

2

1

8

7

6

5

4

3

2

AC’97 Audio

Stereo HP/Spkr out

HP_OUTA

D

C8

AGND

+
1UF-TANT
C25
1
2
+
1UF-TANT

1

1

2
L3

AGND

OUTA
VDD
INA
OUTB
BYPASS
INB
GND
SHUTDN

VCC5_AUDIO
HP_OUTB

8
7
6
5

EAPD

13

C4

13
1

AGND

2

AGND

+

1

R3
20K

1
2
3
4

C14

LNLVL_L_C

+

C13
1
2
+
1UF-TANT

20K

U1
LM4880

LNLVL_R_R
AC_BYPASS

2

C

AGND

LNLVL_L_R

AGND

1

2

+
1UF-TANT

R1

LNLVL_R_C

C26

2

+
10PF-NPO
C22

+
10PF-NPO

1

2

J5
LINE_IN_R_FB
LI25
LI24
LI23
LI22
LINE_IN_L_FB
LI21
DB15_AUD_STK

2
L2

LINE_IN_L_C

C6

1UF

LINE_IN_R_C

LNLVL_OUT_L

13

1

R2

2

AGND

100PF

LINE_IN_L

13

C23

AGND

20K

13

1

LNLVL_OUT_R

13

Line_In Analog Input
LINE_IN_R

D

R4

AGND

C

2

2
L1

100PF

20K
AGND

AGND

1

0.1UF

C28

2

0.01UF

1
L5

HP_OUTB_C 1
1

2

C2

1

J5
HP_OUTA_FB
HP30
HP29
HP28
HP_OUTB_FB
HP27
HP26
DB15_AUD_STK

2
L4

C11

2

1K

HP_OUTA_C 1

+
10PF-NPO
C24

R9

MIC_IN_C

+
10PF-NPO

1
2
+
1UF-TANT
C34

C10
1
2
+
100UF
C3
1
2
+
100UF

+
10PF-NPO

C27

J5
MIC_IN_FBM20
M19
M18
M17
M16
DB15_AUD_STK

MIC_IN_R

2.2K

MIC_IN

13

Microphone Input

R7

AUD_VREFOUT

13

1

AGND

B

B

CD Analog Input
R52

J4
1 CD_L_J
2 CD_REF_J
3
4 CD_R_J

CD_L_C

2

CD_REF_C

2

CD_R_C

2

4.7K
R27
4.7K
R18
4.7K

C59
+
1UF
C58
+
1UF
C50
+
1UF

1

CD_L

1

CD_REF

1

CD_R

13

13

13

A

AGND

8

4.7K

R25

4.7K

R30

4.7K

R51

A

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
REV:
AUDIO
1.01
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-18-1999_10:47
14 OF 36

AGND AGND

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

AC’97 Audio/Modem Riser
D

D

VCC3_3SBY

VCC3_3 VCC5 VCC12 VCC12-

R68

VCC3_3SBY

J8
4.7K

U3 14
6
PRI_DWN_RST#

C

13

13

4 PRI_DWN_U
5

7
SN74LVC08A

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11

MONO_OUT

PRI_DWN#
3

1

JP2

2

B12
B13
B14
B15
B16
9,13
9

AC_SDATAOUT
AC_RST#

Au d io Do w n
E nable*
Dis able

JP 2
1-2
2-3

KEY
KEY
GND[3]
RESV[3]
RESV[4]
+3.3VD
GND[4]
AC97_SDATA_OUT
AC97_RESET#
AC97_SDATA_IN3
GND[5]
AC97_SDATA_IN2
GND[6]
AC97_MSTRCLK

AC’97_RISER
AMR_CONNECTOR

AUDIO_PWRDWN
MONO_PHONE
RESV[5]
RESV[6]
RESV[7]
GND[7]
+5VDUAL/5VSBY
USB_OC
GND[8]
USB+
USBKEY
KEY
GND[9]
S/P_DIF_IN
GND[10]
+3VDUAL/3VSBY
GND[11]
AC97_SYNC
GND[12]
AC97_SDATA_IN1
GND[13]
AC97_SDATA_IN0
GND[14]
AC97_BITCLK

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

MONO_PHONE

13

VCC5

C
AC97_OC#
AC97_USB+
AC97_USB-

23
23
23

VCC3_3SBY

A12
A13
A14
A15
A16
A17
A18
A19 AC_SDATAIN1_R
A20
A21
A22
A23

AC_SYNC
R113

9,13

AC_SDATAIN1

9

0K
AC_SDATAIN0
AC_BITCLK

9,13

B

9,13

R108
10K
R125
10K

B

B17
B18
B19
B20
B21
B22
B23

AUDIO_MUTE#
GND[0] (ISOLATED)
MONO_OUT/PC_BEEP
RESV[1]
RESV[2]
PRIMARY_DN#
-12V
GND[1]
+12V
GND[2]
+5VD

A

A

REV:
1.01
PROJECT:

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
AUDIO/MODEM RISER
DRAWN BY:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
FOLSOM, CALIFORNIA 95630

8

7

6

5

4

3

2

SHEET:
15 OF 36

1

8

7

6

5

4

3

2

1

VCC3_3SBY

PWROK
LAN_RSMRST#

7,9,29,31
17
2
25MHZ

Y2
XTAL

A

9,32
9,32

1

C101
22PF

8

B9
A9

ALERTCLK_SBY A10
ALERTDATA_SBY C9

C96
22PF

7

E12
G5
G6
H5
H6
H7
H8
J5
J6
J7
J8
J9
J10
J11
K4
K5
K6
K7
K8
K9
K10
K11
L4
L5
L9
L10
VCC[0]
VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]

LAN_X1

N11

X1

LAN_X2

P11

X2

C13
C14
E13
E14

TDP
TDN
RDP
RDN

SMBALRT#
CSTSCHG
PME#

B10
C5
A6

PCI_PME#

FLA0/PCIMODE#
FLA1/AUXPWR
FLA2
FLA3
FLA4
FLA5
FLA6
FLA7
FLA8/IOCHRDY
FLA9/MRST
FLA10/MRING#
FLA11/MINT
FLA12/MCNTSM#
FLA13/EEDI
FLA14/EEDO
FLA15/EESK
FLA16

J13
J12
K14
L14
L13
L12
M14
M13
N14
P13
N13
M12
M11
P10
N10
M10
P9

FLD0
FLD1
FLD2
FLD3
FLD4
FLD5
FLD6
FLD7

F14
F13
F12
G12
H14
H13
H12
J14

6

P7
N9
M8
M9
C8

TEST
TEXEC
TCK
TI
TO

A13
D13
D14
D12
B12

RBIAS10
RBIAS100
VREF

B14
B13
C12

D

17
17

17
17
17
17

VCC3_3SBY

R59

A3
A7
E1
K3
N6
P2

A11

VCCPL[0]
VCCPL[1]
VCCPL[2]
VCCPL[3]

SMBCLK
SMBD
VIO

TDP
TDN
RDP
RDN

EECS
FLCS#
FLOE#
FLWE#
CLKRUN#

ISOLATE#
ALTRST#

G2

A12
C11
B11

8,19,20,21

3.3K

AUXPWR

C

EEDI
EEDO
EESK

VCC3_3SBY

U8
93C46
3
4
2
1

FLD5
FLD6

EECS

8
VCC
EEDI
EEDO
NC2
EESK
NC1
EECS
GND
5

7
6

B

No stuff R57, R58
R58
3.3K
R57
3.3K
R11

CLKRUN#_LAN

62K
R14

TEST_LAN

3.3K

R16

RBIAS10
RBIAS100

549
R15
619

A
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]

6,8,10,11,12,19,20,21,22
5

FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
INTA#
PERR#
SERR#
IDSEL
REQ#
GNT#
RST#
CLK

LILED
ACTLED
XREF1=17
SPEEDLED

LILED
ACTLED
SPEEDLED

D4
D5
D6
D7
D8
D11
E4
E5
E6
E7
E8
E9
E10
E11
F4
F5
F6
F7
F8
F9
F10
F11
G7
G8
G9
G10
G11
H9
H10
H11
L6
L11

AD20

F2
F1
G3
H3
H1
J1
H2
J2
SERR#
A2
R75
AD20_RLAN A4
100 PREQ#3
C3
PGNT#3
J3
PCIRST#
C2
PCLK5
G1

VSSPP[0]
VSSPP[1]
VSSPP[2]
VSSPP[3]
VSSPP[4]
VSSPP[5]

VCC5SBY

C/BE0#
C/BE1#
C/BE2#
C/BE3#

VSSPT

8,20,21,32
8,16
8,32
8,32

M4
L3
F3
C4

FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
PIRQ#A
PERR#

8,20,21,32
8,20,21,32
8,20,21,32
8,20,21,32
8,20,21,32
8,20,21
8,19,20,21,32
8,20,21,32

B

C_BE#0
C_BE#1
C_BE#2
C_BE#3

B3
B7
E2
K2
M6
N1

8,20,21

82559

C10

C_BE#[3:0]

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

VSSPL[0]
VSSPL[1]
VSSPL[2]
VSSPL[3]

C

N7
M7
P6
P5
N5
M5
P4
N4
P3
N3
N2
M1
M2
M3
L1
L2
K1
E3
D1
D2
D3
C1
B1
B2
B4
A5
B5
B6
C6
C7
A8
B8

G14
K12
P8
N12

D

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

VCCPT

U5
AD[31:0]
8,20,21

VCCPP[0]
VCCPP[1]
VCCPP[2]
VCCPP[3]
VCCPP[4]
VCCPP[5]

G13
K13
N8
P12

LAN

5

4

3

REV:
1.01
PROJECT:

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
LAN CONTROLLER
DRAWN BY:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
FOLSOM, CALIFORNIA 95630
11-18-1999_10:48

2

SHEET:
16 OF 36

1

8

7

6

5

4

3

2

1

LAN

0.1UF

RDN

0.1UF

RXC_J
75

R10

75

R8

75

R5

75

SPEED_J

R73
330
R78
330
R60
330
LI_J

ACT_J

330

ACTLED

ACTLED

C

16,17

9,31
16

RDC_J

C31

SPEEDLED

16

For debug only. Hold LAN in reset.
J17
1
2
3

RSMRST#
LAN_RSMRST#

C78
0.1UF

XC_R

82559 L A N

E n a b le *
D is a b le

C5
No stuff C5.
C5 must be rated at 1500V.

LILED

16,17
16,17

0.1UF

B

16,17

16
15

TXC_J

R6

LILED

13

RJ-4
RJ-5
RJ-7
RJ-8

2
1

RJ4_J

14

TDC
RDC

16

3
4
5
6

RJMAG

RJ-45

C79

TD+
TDRD+
RD-

TDC_J 11
8

C61

R63
49.9-1%

10
12
9
7

TXC
RXC

No stuff C61, C79.

RD_C

R62
49.9-1%

RJ_7_J

C

TDN
RDP

J2

SHLD1
SHLD2

16

No stuff JP1,JP3,JP4,R60,R73,R78.

JP1

R26
49.9-1%
R20
49.9-1%

17
18

16

JP3

TDP

JP4

Place termination resistors close to 82559.
16
TD_C

D

VCC3_3

ACT_CR

R61

LI_CR 330
R64

VCC3_3

D

470PF
No stuff C31.

J17
1 -2
2 -3

B

A

A

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
LAN
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LAST REVISED:
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8

7

6

5

4

3

2

REV:
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PROJECT:
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1

6

5

4

VCC3_3SBY

1M

470

14

7
SN74LVC07A
VCC3_3

IDE_ACTIVE

GND

VCC3_3
C354

C355

470PF
U19

R355

470PF

14

VCC
8

9

220

R354

10K

C

VCC5

7
SN74LVC07A

GND
KEYLOCK#

12

SPKR_FP

JP25
AC97_SPKR

3

Speaker Circuit

13

2
PC_BEEP

R350

O n b o a rd S p k r
E n a b le *
D is a b le

P_BEEP

B

1

3
2

2.2K

JP 25
2 -3
1 -2

R352

SPKR_Q
C

Q15

E

INFRARED
VCC3_3
C316
POWER SW.

1
2
3

TACH2

PWM1

VCC12

C

KEYLOCK
VCC3_3
C327

SPEAKER

1
2
3

JP24

68

PWM1

SP1
1+
POS
2 NEG
SPKR_ONBOARD

C353

12

POWER LED

VCC5

R353

JP22

H.D. LED

68

0.1UF

SPKR

MMBT3904LT1

1
9

TACH2

VCC12

4.7K

10K

R344

10K

VCC
2

1

IDEACTP#

IDEACTS#

R358

PWRBTN_FP#

HDLED_R

22

R357

4.7K

R345

12

1
2
3
4
5 KEY
6
7
8
9
10
11
12
13 KEY
14
15
16 KEY
17
18 KEY
PLED_R
19
20 KEY
21
22
23
24 KEY
25
26
FNT_PNL_CONN

82 IRTX_R

IRTX

R356

U19

D

J25
IRRX

12
No stuff.
For test only

VCC5

VCC3_3

22

2

R316

1UF

1

2

9

R257
C267

VCC5

1

4.7K

PWRBTN#

VCC5

R329

0K
SW1

1

0.1UF

R252

ICH has internal pullup and debounce on PWRBTN#

R359

100K

No stuff.
For test only

D

2

0.1UF

System

3

VCC3_3

C350
+
50V
C356
+
10UF
16V

7

0.1UF

8

12

PWM2

VCC12

VCC3_3SBY

B

B

VCC3_3

CR7

GPIO23_FPLED

14

9

VCC
4

3

1

4.7K

R326

PWM2
12
PWM outputs from SIO need power buffers for driving fan inputs.
VCC
6

2

LED_PU0

LED_PU1

GND

CR6

4.7K

R234

Onboard LED indicates the standby well is on
to prevent hot swapping memory.
For debug only.

A

GND

JP23

U14
5

GPIO26_FPLED 9

7

7
SN74LVC07A

1
2
3

VCC3_3SBY

R246

U14

330

1

R253

330

2

VCC3_3SBY

VCC3_3SBY

14

R289

330

VCC3_3SBY

SBY_LED_CR

0.1UF

C322

SN74LVC07A

DUAL_COLOR

A

REV:
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
SYSTEM
1.01
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
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11-18-1999_10:49
18 OF 36

8

7

6

5

4

3

2

1

7

6

5

4

AGP Connector

2

1

VCC12

SBA[7:0]

D
PIRQ#B

8,20,21,32

5

VCC3_3SBY

C

B

A

7 GAD[31:0]
7
GC/BE#[3:0]

7

J13
AGP4XU_20

VCC5
B1
B2
B3
USBAGP+ B4
23
B5
B6
B7
AGPCLK_CONN
GREQ# B8
7,32
B9
B10
ST0
B11
ST2
B12
RBF#
7,32
B13
B14
B15
SBA0
B16
B17
SBA2
SBSTB B18
7,32
B19
B20
SBA4
B21
SBA6
B22
B23
B24
B25
B26
GAD31
B27
GAD29
B28
B29
GAD27
B30
GAD25
B31
ADSTB1 B32
7,32
B33
GAD23
B34
B35
GAD21
B36
GAD19
B37
B38
GAD17
B39
GC/BE#2
B40
GIRDY# B41
7,32
B42
B43
B44
B45
B46
GDEVSEL#
7,32
B47
B48
GPERR#
32
B49
B50
GSERR#
32
B51
GC/BE#1
B52
B53
GAD14
B54
GAD12
B55
B56
GAD10
B57
GAD8
B58
B59
ADSTB0
7,32
B60
GAD7
B61
B62
GAD5
B63
GAD3
B64
B65
GAD1
MCH_AGPREF B66
6

6

AGP_OC#

5

OVRCNT#

12V

5V_A

TYPEDET#

5V_B

RESV_A

USB+

USB-

GND_K
INTB#

GND_A
INTA#

CLK

RST#

REQ#

GNT#

VCC3_3_F

VCC3_3_A

ST0

ST1

ST2

RESV_B

RBF#
GND_L
RESV_H
SBA0
VCC3_3_G
SBA2

PIPE#
GND_B
WBF#
SBA1
VCC3_3_B
SBA3

SB_STB

SB_STB#

GND_M

GND_C

SBA4

SBA5

SBA6

SBA7

RESV

RESV_C

GND_N

GND_D

3_3VAUX1

RESV_D

VCC3_3_H

VCC3_3_C

AD31

AD30

AD29

AD28

VCC3_3_I
AD27
AD25
GND_O
AD_STB1
AD23
VDDQ_F
AD21
AD19
GND_P
AD17
C/BE2#

VCC3_3_D
AD26
AD24
GND_E
AD_STB1#
C/BE3#
VDDQ_A
AD22
AD20
GND_F
AD18
AD16

VDDQ_G

VDDQ_B

IRDY#

FRAME#

3_3VAUX2

RESV_E

GND_Q

GND_G

RESV_K
VCC3_3_J

RESV_F
VCC3_3_E

DEVSEL#

TRDY#

VDDQ_H

STOP#

PERR#

PME#

GND_R

GND_H

SERR#

PAR

C/BE1#

AD15

VDDQ_I

VDDQ_C

AD14
AD12
GND_S
AD10
AD8
VDDQ_J
AD_STB0
AD7
GND_T
AD5
AD3
VDDQ_K
AD1
VREF_CG

AD13
AD11
GND_I
AD9
C/BE0#
VDDQ_D
AD_STB0#
AD6
GND_J
AD4
AD2
VDDQ_E
AD0
VREF_GC

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66

4

TYPEDET#

19,29

USBAGP-

D

23
PIRQ#A

PCIRST#
GGNT#

8,16,20,21,32

6,8,10,11,12,16,20,21,22
7,32
ST1

PIPE#

7,32

WBF#

7,32

SBA1
SBA3

SBSTB#

7,32

VDDQ

SBA5
SBA7

C
AGPREF circuitry should be placed close to MCH.
GAD30
GAD28

3

Q8
3
7,32

GC/BE#3

301-1%

CON_AGPREF_Q

GAD26
GAD24
ADSTB#1

R193

ST[2:0]

19,29

TYPEDET#

1

1

2

R208

7
7

23

8

3
VDDQ

VCC3_3

2N7002LT1

8

200-1%

2

GAD22
GAD20
GAD18
GAD16
GFRAME#

GTRDY#
GSTOP#
PCI_PME#
GPAR

B

7,32

7,32
7,32
8,16,20,21
7,32
GAD15
GAD13
GAD11
CONN_AGPREF
GAD9
GC/BE#0

ADSTB#0

6

7,32

A

GAD6
GAD4
GAD2
GAD0

3

REV:
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
AGP CONNECTOR
1.01
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
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1900 PRAIRIE CITY ROAD
LAST REVISED:
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11-18-1999_10:49
19 OF 36

2

1

8

7

6

5

4

3

2

1

VCC5 VCC5
VCC3_3

8,19,20,21,32
8,20,21,32

PIRQ#B
PIRQ#D
PRSNT#11

20

PRSNT#12

20

PREQ#0

8,32

AD31
AD29

C

AD27
AD25

AD21
AD19
AD17
C_BE#2

8,16,20,21,32
8,20,21,32
8,16,20,21,32

B

IRDY#

A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27

PLOCK#
PERR#
SERR#

C_BE#1
AD14
AD12
AD10

PIRQ#A
PIRQ#C

A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

8,16,19,20,21,32
8,20,21,32

PIRQ#C
PIRQ#A

8,20,21,32
8,16,19,20,21,32

PRSNT#21

20
VCC3_3SBY

PCIRST#

PRSNT#22

20

6,8,10,11,12,16,19,20,21,22

PCLK2

5

PGNT#0

8,32

PCI_PME#

8,32

8,16,19,20,21
AD30

PREQ#1

AD31
AD29

AD28
AD26

AD27
AD25
C_BE#3
AD23

20
AD22
AD20

AD21
AD19

AD18
AD16
FRAME#
TRDY#
STOP#

AD17
C_BE#2

8,16,20,21,32

IRDY#

8,16,20,21,32

DEVSEL#

8,16,20,21,32

SDONEP1
SBOP1
PAR

PLOCK#
PERR#

20
20

SERR#

8,16,20,21
AD15

C_BE#1
AD14

AD13
AD11

A1
A2

B3
B4
B5
B6
B7
B8
B9
B10
B11

A3
A4
A5

AD12
AD10

AD9

AD5
AD3

B55
B56
B57
B58
B59
B60
B61
B62

AD1

A

20

8,16,21

C_BE#[3:0]

8,16,21

AD[31:0]

8

PU1_ACK64#

8,19,20,21,32
8,20,21,32

20
20
20
20

A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27

B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

SDONEP1
SDONEP2
SBOP1
SBOP2

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

AD8
AD7

C_BE#0
AD6
AD4

AD5
AD3

AD2
AD0
PU1_REQ64#

20

AD1
PU2_ACK64#

20

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

D

8
7
6
5
5.6K

C117 0.1UF

PCIRST#

6,8,10,11,12,16,19,20,21,22

PGNT#1

PRSNT#11

20

C123 0.1UF

8,32

PRSNT#12

20

PCI_PME#
AD30

8,16,19,20,21

C113 0.1UF
PRSNT#21

20
AD28
AD26

C

C122 0.1UF
PRSNT#22

20

AD24
R_AD17

20
AD22
AD20

A30
A31
A32
A33

AD18
AD16
VCC5

A34
A35
A36
A37
A38
A39

FRAME#

A40
A41
A42
A43
A44
A45
A46
A47

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

1
2
3
4

VCC3_3SBY

A28
A29

A48
A49

VCC5

TRDY#

20

PU1_ACK64#

STOP#

20

PU1_REQ64#

SDONEP2
SBOP2

20

PU2_ACK64#

20

PU2_REQ64#

R178
2.7K
R179
2.7K
R176

B

2.7K
R177

PAR

2.7K
AD15
AD13
AD11
AD9

8,16

AD16

AD17

8,16

C_BE#0

R120

R_AD16

100

key

B52
B53
B54

20,21

RP12

PIRQ#B
PIRQ#D

A6
A7
A8

B12
B13
B14
B15
B16
B17
B18
B19
B20
B21

key

AD8
AD7

PTRST#
PTMS
20,21
PTDI
20,21

R72

B1
B2

R79

VCC12
VCC5

PCI Slot 1
J9
PCI3_CON

B22
B23
B24
B25

AD24
R_AD16

A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39

PTCK

20,21

R74

PTMS
20,21
PTDI
20,21

B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

DEVSEL#

8,16,20,21,32

PTRST#
20,21

A3
A4
A5

B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36

C_BE#3
AD23

8,16,20,21,32

A1
A2

B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25

PCLK1

5

B1
B2

5.6K

PCI Slot 0
J10
PCI3_CON

PTCK

20,21

VCC3_3
VCC12- VCC5

5.6K

VCC3_3
VCC5 VCC12

5.6K
R76

VCC3_3

VCC12- VCC5

D

For pullups, see 4.3.3 of PCI 2.1 Specification

5.6K

PCI Connectors
0 and 1

R119
100

R_AD17

20

20

AD6
AD4
AD2
AD0

A
PU2_REQ64#

20

REV:
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
PCI CONNECTORS 1 AND 2
1.01
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-18-1999_10:50
20 OF 36

7

6

5

4

3

2

1

8

7

PCI Connectors
2 and 3

6

VCC3_3

B3
B4
B5
B6
PIRQ#A
PIRQ#C
PRSNT#31

8,16,19,20,21,32
8,20,21,32
21

PRSNT#32

21

5
8,32

PCLK3
PREQ#2

AD31
AD29

C

AD27
AD25

AD21
AD19
AD17
C_BE#2

8,16,20,21,32
8,20,21,32
8,16,20,21,32

B

8,16,20,21,32

IRDY#
DEVSEL#

SERR#

C_BE#1
AD14
AD12
AD10

PCIRST#

A40
A41
A42
A43
A44
A45

R255
0K

6,8,10,11,12,16,19,20,21,22

PCLK4

5

PGNT#2

8,32

PREQ#5

8,32

PCI_PME#
AD30

8,16,19,20,21

AD31
AD29

AD28
AD26

AD27
AD25

AD24
R_AD23

C_BE#3
AD23

21
AD22
AD20

AD21
AD19

AD18
AD16
FRAME#
TRDY#
STOP#

8,16,20,21,32

IRDY#

8,16,20,21,32

DEVSEL#

8,16,20,21,32

SDONEP3
SBOP3
PAR
AD15

A46
A47
A48
A49

AD17
C_BE#2

PLOCK#
PERR#

21
21

SERR#

8,16,20,21

C_BE#1
AD14

AD13
AD11

AD12
AD10

AD9

B1
B2

A6
A7
A8
A9
A10
A11 GNT#A_R
A12
A13
A14
A15
A16

B7
B8
B9
B10
B11
B12
B13
SERIRQ_RB14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25

A17
A18
A19
A20
A21
A22
A23

AD1

A
21

8,16,20

C_BE#[3:0]

8,16,20

AD[31:0]

8

PU3_ACK64#

PTRST#

PIRQ#C
PIRQ#A

R99
0K

B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48

A52
A53

B57
B58
B59

A54
A55
A56
A57
A58
A59

B60
B61
B62

A60
A61
A62

AD8
AD7

C_BE#0
AD6
AD4

AD5
AD3

AD2
AD0
PU3_REQ64#

21

AD1

21

PU4_ACK64#

B52
B53
B54
B55
B56

PCIRST#
6,8,10,11,12,16,19,20,21,22
PGNT#5
8,32

RP13
21
21
21
21

R107
0K
R110
REQ#A 8,32
0K
No Stuff R110.
REQ#A for debug only

21

8
7
6
5

PRSNT#31

PRSNT#32
C116 0.1UF

21

AD28
AD26

FRAME#

A40
A41
A42
A43
A44
A45

SDONEP4
SBOP4

PRSNT#41

C
C126 0.1UF

21

AD24

A34
A35
A36
A37
A38
A39

PRSNT#42

21
AD22
AD20
AD18
AD16
VCC5

TRDY#
21

STOP#

21
21
21

21

PAR

21

AD15

PU3_ACK64#
PU3_REQ64#
PU4_ACK64#
PU4_REQ64#

R174
2.7K
R175
2.7K
R172

B

2.7K
R173
2.7K

AD13
AD11
AD9
8,16

A60
A61
A62

1
2
3
4

C112 0.1UF
21

8,16,19,20,21

R_AD22

A54
A55
A56
A57
A58
A59

SDONEP3
SDONEP4
SBOP3
SBOP4

C121 0.1UF
PCI_PME#
AD30

A26
A27
A28
A29
A30
A31
A32
A33

A52
A53

B57
B58
B59
B60
B61
B62

VCC3_3SBY

5.6K

VAUX_JP

A46
A47
A48
A49

B49

8,20,21,32
8,16,19,20,21,32

GNT#A for debug only
GNT#A 8,32

C_BE#0
8,16
AD6
AD4

AD23

R118

R_AD23

21

100
AD22

R117

R_AD22

21

100

AD2
AD0

A
PU4_REQ64#

21

TITLE: INTEL(R) 820 CHIPSET - FCPGA REFERENCE BOARD
PCI CONNECTORS 3 AND 4
DRAWN BY:
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R
1900 PRAIRIE CITY ROAD
LAST REVISED:
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11-9-1999_11:43

7

6

5

4

D

VCC5

20,21
20,21

A24
A25

B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36

20,21

PTMS
PTDI

key

AD5
AD3

J9 must be furthest from the processor.
A1
A2
A3
A4
A5

key

B52
B53
B54
B55
B56

AD8
AD7

1

VCC5 VCC12

PCI Slot 3
J11
PCI3_CON

B3
B4
B5
B6

SERIRQ for debug only
8,12,32
SERIRQ

A26
A27
A28
A29
A30
A31
A32
A33

B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

PLOCK#
PERR#

PTCK

PIRQ#D
8,20,21,32
PIRQ#B
8,19,20,21,32
PRSNT#41
21
PCI_TEST
PCI_TEST for debug only 9
VCC3_3SBY
PRSNT#42
21

A24
A25

A34
A35
A36
A37
A38
A39

20,21

20,21
20,21

PIRQ#D
8,20,21,32
PIRQ#B
8,19,20,21,32

A17
A18
A19
A20
A21
A22
A23

B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36

C_BE#3
AD23

8,16,20,21,32

A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16

B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25

PTMS
PTDI

20,21

2

VCC3_3

VCC12- VCC5

PTRST#

A1
A2
A3
A4
A5

3

VCC3_3

VCC5 VCC12

PCI Slot 2
J12
PCI3_CON
B1
B2

PTCK

20,21

4

VCC3_3

VCC12- VCC5

D

5

3

2

1

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PROJECT:
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8

7

6

5

4

3

2

1

IDE Connectors
Primary IDE

Secondary IDE

PDD[15:0]

SDD[15:0]

9

J21

PIORDY
9
8,32

5.6K

R335

9

PDIOW#
PDIOR#

9
9

PDDACK#
IRQ14
PDA1
PDA0

C

9
18

PDCS#1
IDEACTP#

1K

R321
9

SDIOW#
SDIOR#

9
9

SIORDY
9
8,32

SDDACK#
IRQ15
SDA1
SDA0

9

9
18
C329

PDA2

SDCS#1
IDEACTS#

D

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

IDE_JS

S66DETECT10
SDCS#3
9

SDA2

0.047UF

PDA[2:0]

C
C318

SDA[2:0]

0.047UF
R319

10K

9
R334

9

SDREQ

IDE_JP

P66DETECT10

PCIRST#_RS1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

33

SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0

VCC5

9

PDCS#3

R318

PCIRST_BUF#

22

PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

10K

PDREQ

9

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

5.6K

1K

R336

PCIRST#_RP1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

33

R320

PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0

VCC5

470

R333

PCIRST_BUF#

R337

22

470

J22

D

R322

9

For drive side detection, stuff C329,C318.
For host side detection, no stuff C329,C318.
P66DETECT and S66DETECT can be connected to a GPI for BIOS cable detection.

VCC3_3

B

B

R351

VCC3_3

U19
6,8,10,11,12,16,19,20,21

14

PCIRST#

VCC
6

5

7
SN74LVC07A

8.2K

PCIRST_BUF#

22

GND

A

A

REV:
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
IDE CONNECTORS
1.01
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22 OF 36

8

7

6

5

4

3

2

1

8

7

4

3

2

1

VCC3_3

R83

D

5

330K

USB Connectors

6

D

L11
USBPWR1_F

2

1

AC97_OC#

15

C99

C44

68UF-TANT

0.1UF

0K

R82

Do Not
Stuff
C98, C99 must have low ESR.

VCC3_3

USBV0

VCC5
9

R242

9

USBD0P

0K

USBG0

VCC3_3

Do Not
Stuff

0K

0K

R48

47PF

15K

C241

47PF

15K

C239

R50

7
6
3
4

R47

OUT1
OUT2
EN#1
EN#2

R49

IN
OC#1
OC#2
GND

J3
1
2
3
4
5
6
7
8

1
C38
AC97_USB+
AC97_USB-

15
15

L7

2
8
5
1

OC#0_RC

R87
C109

R502

USBD0P_R

15-1%

U7
TPS2042
10K

USBD0N

0K

15-1%
USBP0P

0.1UF

C
OC#0

R501

USBD0N_R

C102

4.7K

R86

9

R240

USBP0N

470PF

2

4.7K

R91

0.1UF

10K

OC#1_RC
2

1

C39

USBPWR2_F

C41

47PF

L10

R97
C120

47PF

OC#1

C40

C42

9

C

USB_STK
VCC0
DATA0DATA0+
GND0
VCC1
DATA1DATA1+
GND1

C39-C42 for test and debug only.
Place caps close to connector.

VCC3_3
C43

68UF-TANT

B

0.1UF

0K

R88

R92

330K

Do Not
Stuff

47PF

C98

47PF

0.1UF

B

USBV1
AGP_OC#
USBP1N

USBP1N_R

15

R44

USBP1P_R

0K

R42

0K

R41

15K

47PF

USBG1

1

Do Not
Stuff

C37

L6

C245

47PF

USBD1P

0K

15

C244

USBD1N

0K

R244

USBP1P

15K

9

R46

R43

9

R243

R45

19

470PF

A

USBAGP+

2

A

19

USBAGP-

19

15 ohm resistors and 47pf caps should be within 1" of ICH
REV:
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
USB CONNECTORS
1.01
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PROJECT:
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11-18-1999_10:57
23 OF 36

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Parallel Port
VCC5

CR1
1

D

3

VCC5_DB25_CR

D

MMBD914LT1
5 6 7 8

2.2K

RP4

2.2K

RP3

2.2K

4 3 2 1

4 3 2 1

5 6 7 8

5 6 7 8

RP2

RP1

2.2K

2.2K

R40

5 6 7 8

4 3 2 1

4 3 2 1

J6
DB25_DB9_STK
12
12
12

C

12

SLCT

P13
P25
P12
P24
P11
P23
P10
P22
P9
P21
P8
P20
P7
P19
P6
P18
P5
P17
P4
P16
P3
P15
P2
P14
P1

PE
BUSY
ACK#

PDR[7:0]
RP19

12

PDR7
PDR6
PDR5
PDR4

1
2
3
4

PDR3
PDR2

1
2
3
4

8
7
6
5

PDR7_R
PDR6_R
PDR5_R
PDR4_R

8
7
6
5

PDR3_R
PDR2_R
SLIN#_R
PAR_INIT#_R

RP18 33

12
12
12

SLIN#
PAR_INIT#

33
ERR#

C

B

B
RP20

8
180PF
CP5

1

6
180PF
CP5
7
180PF
CP5

2

3

8
180PF
CP4
5
180PF
4
CP5

CP4
7
180PF
CP4

2

1

6
180PF
3

8
180PF
CP3
5
180PF
CP4

4

1

6
180PF
CP3
7
180PF
2
CP3

3
CP3

6
180PF
2

7
180PF

CP2

4
5
180PF

180PF

3

1

CP2

33

CP2

PDR1_R
PDR0_R
AFD#_R
STB#_R

8
180PF
4
5
180PF

AFD#
STB#

1
2
3
4

C81

12
12

8
7
6
5

CP2

PDR1
PDR0

A

A

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
REV:
PARALLEL PORT
1.01
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8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Serial Ports
VCC5

VCC12

D

U4
1
2
3
4
5
6
7
8
9
10

J6
DB25_DB9_STK
DCD
DSR
RXD
RTS
TXD
CTS
DTR
RI
GND

A1
A6
A2
A7
A3
A8
A4
A9
A5

DCD0_C
DSR0_C
RXD0_C
RTS0_C
TXD0_C
CTS0_C
DTR0_C
RI0_C

2
CP8

4
CP8

8
100PF

6
100PF

6
100PF

CR2
BAT54C
3
1

RI_CR

ICH_RI#

8
100PF

5
100PF
3
CP1
7
100PF
1
CP1
5
100PF
3
CP8
7
100PF
1
CP8

4
CP1

VCC12-

R17
10K

C
9

D

COM1

GD75232
VCC12
VCC
RY0
RA0
RY1
RA1
RY2
RA2
DA0
DY0
DA1
DY1
RY3
RA3
DA2
DY2
RY4
RA4
GND
VCC-12

2
CP1

12
12
12
12
12
12
12
12

VCC3_3SBY

20
19
18
17
16
15
14
13
12
11

DCD#0
RXD0
DSR#0
DTR#0
TXD0
CTS#0
RTS#0
RI#0

C

3

R70
47K

2
Q1

VCC5

1

VCC12

RI_Q

COM2
J7
1
3
5
7
9

DCD1_C
RXD1_C
DSR1_C
DTR1_C
TXD1_C
CTS1_C
RTS1_C
RI1_C

2
4
6
8
10

B

3
CP6

7
100PF

8
100PF

COM2 is a 2x5 pin header for a cabled port.

1
CP6

VCC12-

7
100PF

1
2
3
4
5
6
7
8
9
10

2
CP6

GD75232
VCC12
VCC
RY0
RA0
RY1
RA1
RY2
RA2
DA0
DY0
DA1
DY1
RY3
RA3
DA2
DY2
RY4
RA4
GND
VCC-12

1
CP7

20
19
18
17
16
15
14
13
12
11

5
100PF
2
CP7
6
100PF
6
100PF

B

DCD#1
RXD1
DSR#1
DTR#1
TXD1
CTS#1
RTS#1
RI#1

12
12
12
12
12
12
12
12

8
100PF

1UF

C92

5
100PF

R69
47K

U6

4
CP6

1

3
CP7

2
2

4
CP7

2N7002LT1

3

A

A

REV:
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
SERIAL PORTS
1.01
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25 OF 36

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Keyboard/Mouse/Floppy
VCC5

D

D
RP17
1
2
3
4

VCC5

8
7
6
5

Floppy Connector

F1

1

VCC5_KBMS_F

2

1.0A

2

VCC5_KBMS_J 12

R328

1

L15

J23

J1
1
L16

12

C

KBCLK

1

1
2
3
4
5
6

KBDAT_FB

2

GND_KBMS_C
2

KBCLK_FB

2

MDAT_FB

L12
12

MDAT

1
L14

12

MCLK

1

MCLK_FB

2
L13
C45

C33

C32

C46

12
12
12
12

17
16
15
14
13

C47

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34

DRVDEN#0
DRVDEN#1
INDEX#
MTR#0
DS#0
DIR#
STEP#
WDATA#
WGATE#
TRK#0
WRTPRT#
RDATA#
HDSEL#
DSKCHG#

C

L8

0.1UF

100PF

100PF

100PF

100PF

2

12
12
12
12
12
12
12
12
12

GND_KBMS_FB

7
8
9
10
11
12

12

PS/2 Kybd

KBDAT

PS/2 Mse

12

1K

1K

1

L9

2

B

1

B

A

A

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
REV:
KEYBOARD/MOUSE/FLOPPY
1.01
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8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Game Port

D

D

VCC5

VCC5

VCC5

VCC5

VCC5

VCC5

12
12
12
12

C

12

J1BUTTON1
J2BUTTON1
JOY1X
JOY2X

1K

1K

R33

R32

1K

R36

1K

R37

4.7K

R35

4.7K

R39

VCC5

R21
R22

JOY1X_R
JOY2X_R

2.2K 5%

2.2K 5%
R34

MIDI_OUT

MIDI_OUT_R

47
12
12
12
12
12

JOY2Y_R

R23

JOY2Y
JOY1Y
J2BUTTON2
J1BUTTON2
MIDI_IN

R24

2.2K

JOY1Y_R

5%

2.2K 5%
R38

MIDI_IN_R

47

J5
DB15_AUD_STK
31
1
9
2
10
3
11
4
12
5
13
6
14
7
15
8
32

C

C69
0.01UF 25V
10%
C68
1
1

470PF
C67
0.01UF 25V
10%

50V

1
C54

2 47PF

C53
470PF

50V

C52

2 47PF
50V

B

1
C51
2 47PF

+

+

C55
2 47PF

+

C56

+

25V
0.01UF 10%

B

50V

C66
0.01UF 25V
10%

Tie game port capacitors together and to SIO AVSS. Tie to system ground at only a single point.

A

A

REV:
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PROJECT:

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
GAME PORT
DRAWN BY:
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8

7

6

5

4

3

2

SHEET:
27 OF 36

1

8

7

6

5

4

3

2
VCC3_3

VCC12

VRM

1

VCC5

R71

5.6K

220

R332

5.1-5%

VCC5

D

R53

VRM requirements are based on VRM8.4 spec .

D

VRM_PWRGD

PVCC_R

4,31

C97

+
1UF-X7R

L19

1UH

1

2

DO3316P-102
Place caps next to output FETs.
C82,C87,C107,C111 must support >6A of RMS current.

1

1

1

+
1200UF
C107

+
1200UF
C82

1

C118, C119 must be next to FETs.

5 6 7 8

5 6 7 8

C118

1.0UH-20A
ETQP6F0R8L

1

C119

B

1

C110

2

2

+
2200UF

2

C103

1

C93

C100

2

+
2200UF

1

1

4 3 2 1

4 3 2 1

+
2200UF

C71

0.1UF
No Stuff C106

C86

C

5 6 7 8

5 6 7 8

+
2200UF

C74

VCCVID

L18

20

0.01UF

JP9

2

IFB_Q

R65

1000PF

SENSE
6

5

2
GND

SGND

SS

PVCC
3

4

VCC
C75

8.2K

VRM_COMP_R

JP7

R55

150PF

C73
JP10

1

4 3 2 1

4 3 2 1

Q5
SI4410DY
D1
S1
D2
S2
D3
S3
D4
G1

JP8

VRM_FAULT
VRM_G1
VRM_IFB
VRM_G2

Q4
SI4410DY
D1
S1
D2
S2
D3
S3
D4
G1

JP6

VID Override Jumpers

7
13
12
20
8
1
11

VRM_SS

VRM_COMP

B

IMAX
PWRGD
FAULT#
G1
IFB
G2
VFB

VRM_VFB

LTC1753

COMP

OUTEN
VID0
VID1
VID2
VID3
VID4

9

19
18
17
16
15
14

10

OUTEN
VID0
VID1
VID2
VID3
VID4

VID[4:0]

0.1UF

3

VRM_IMAX

Q2
SI4410DY
D1
S1
D2
S2
D3
S3
D4
G1

C

Q3
SI4410DY
D1
S1
D2
S2
D3
S3
D4
G1

VR3

+
1UF-X7R

R54

2

2.7K

1

+
1UF-X7R

2

+
0.01UF

2

2

C72

2

+
1200UF

C87

0.1UF

+
10UF

C90

C140

R80

10K

2

+
1200UF
C111

VRM_VCC5

1

2

Sanyo 4SP2200M

A

A

REV:
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
VRM 8.2
1.01
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PROJECT:
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R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
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11-18-1999_11:24
28 OF 36

8

7

6

5

4

3

2

1

7

6

5

4

3

Voltage Regulators
VCC 5V DUAL VOLTAGE SWITCHER

VCC5SBY

The VCC5DUAL plane should not drive any logic components requiring 5V.
It should be used only for further regulation of lower voltage power planes
because the true voltage of VCC5DUAL will not remain constant
Rdson of the FET is not negligible for large currents

VCC12
VCC12

D
VCC5DUAL

+
10UF

B

1

2

10K

1

1

+

+

+

2

2

2

2

2

22UF

1

Route VR6 GND to VDDQ output caps and then via to ground.

1K

+
100UF

E

E
R362

3

R146

R360

1

1.21K-1%

TYPEDET#

MMBT3904LT1

2

C

Q7

19

1

1UF-X7R
C242

2.2K

R158

7.5K-1%

+

1K

R218
3

MMBT3904LT1

C

1

C142

+
100UF

2

1VDDQ_COMP_R

C168
0.001UF

1K

R361

1

C124

+
1UF-X7R

B

C104

2

+

C

R137

VDDQ_FB

VR_SDB B

2

2

10PF

1UF-X7R
C179

2

Q16

VOUT 2
GND 1

2

1%

C164

VR4
LT1587-1_5

3 VIN

3
3

1

VR_SHUTDOWN

VTT 1.5 VOLTAGE REGULATOR

1

Q6

VDDQ_COMP

VTT1_5

1

8
7
R135
VDDQ_G2 1
6 VDDQ_G
5.1-5%
5

VCC3_3

VCC1_8

VCC3_3

IPOS
INEG
GATE
COMP

1UF-X7R
C211

+

C174

2

SHDN
VIN
GND
FB

IRL2203NS

0K

1
2
3
4

1

+

E

C160
VR6
LT1575

1UF-X7R
C225

2

220UF
1 +
2

No stuff R363

2

C200

3

VDDQ

R141

VD_G3

1K

1

2

2

2

301

VD_G2

B

1
C336
+
1500UF

C193
R340

VD_G1
GND
SN74LVC07A

C

Q13

VCC
2

1

MMBT3904LT1

1

7

7 GND

1K

R331

U14

14

U18
74LS132 14VCC
4
6
5

SLP_S3#
PWROK

VCC3_3SBY

D1 8
D1A 7
D2 6
D2A 5

R363

SN74LVC07A has 5V input and output tolerance.

9,31
7,9,16,31

1

Q12
SI4562DY
1 S1
2 G1
3 S2
4 G2

VCC5DUAL_R

VCC5SBY

C173

47UF

1K

R330

47UF

C

1

C324

+
47UF

C347

VCC5SBY

1

VCC3_3

VCC5

C352
+
1500UF

D

2

AGP VDDQ VOLTAGE REGULATOR

1UF

8

B

VCC2_5
VCC1_8

VCC2_5SBY
VCC5DUAL

VCC2_5 VOLTAGE REGULATOR

131-1%

R134

100-1%

301-1%

R311

1

+
100UF

R309

VOUT 1
SENSE 2

2

C91

2

4 SHDN#

TAB 6
GND3 3

+
1UF-X7R

2

1

C35

+
1UF-X7R

2

+
330UF-T510

VCC2_5_ADJ

VR1
LT1529-3_3
5 VIN

1

C161

+
100UF

C159

2

1

2

C15

1

+
100UF

ADJ 1

3 VIN

VCC1_8_ADJ

ADJ 1

VOUT 2

C167

2

C333

+
100UF

+
100UF
C108

+
1UF-X7R

2

2

1

VR5
LT1587ADJ

CR11

C268

+
100UF

2

C319

A

+
100UF

3 VIN
1

1

2

C311

VOUT 2

1

1

-

+

1

VR8
LT1587ADJ

VCC3_3SBY

VCC3_3SBY VOLTAGE REGULATOR

VCC5

BAT17
C

R133

A

100-1%

VCC 1.8 VOLTAGE REGULATOR
VCC3_3

A

Place C311 at regulator.
Place C108 and C333 at RIMM termination
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VOLTAGE REGULATORS
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8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Voltage Regulators
VCC5DUAL

D

D

C315 1UF-X7R
1 +
2

VCC 2.5 Standby Voltage Regulator

C314 100UF
1 +
2

VCC2_5SBY_TG
VCC2_5SBY_SW

R295

D3
D4
S2
G2

+

11K
+

R302

1
C326

2

R294

VCC2_5SBY_BG

100-1%

R301

+

1
C325

2

T510

10K

A

100-1%

C-

R297

D1
D2
S1
G1
8
7
1
2
0.1UF

CR10

C307

C312

MBRS130LT3

-C

CMDSH-3

+
0.1UF

4.7UF

330PF

C306

2

C299 1000PF

C292

+

2

C

C304

100PF

100PF

SBY_ITH_R

68PF
0.1UF

100-1%

R258

1
1

A

0.01

330UF

C263

Do not stuff C304.
R325

VCC2_5SBY_INTVCC
V_BOOST

330UF

C293

L23

10UH
CDRH127-6R1

100PF

C296

VIN 13
TG 16
SW 14
INTVCC 12
BOOST 15
BG 11
PGND 10

CR9

VCMOS1_8SBY

C294

SENSE+ 8

R259

C295

SFB
COSC
RUN/SS
ITH
SGND
VOSENSE
EXTVCC

SENSE- 7

35.7-1%

MMBD914LT1

4
1
2
3
5
6
9

VCC2_5SBY_COSC
VCC2_5SBY_RUN
VCC2_5SBY_ITH

CR8
1

10K

C

3

SLP_S5#

VCC2_5SBY_L

9

0.1UF

VCC2_5SBY

VCC2_5SBY

Q11
SI4966DY

+

VCMOS Generator For Rambus

6
5
3
4

VR7
LT1435

VCC2_5SBY_SENSE+
VCC2_5SBY_SENSEVCC2_5SBY_VOSENSE

Do not stuff C292.

B

B

A

A

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VOLTAGE REGULATORS
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30 OF 36

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Power Connector
ITP Reset circuit. For debug only.

VCC3_3

U15 14

1

VCC5SBY

C

U20 14VCC
5
6
SLP_S3#
GND
SN74LVC06A7

VCC5

SLP_S3

SN74LVC06A has 5V output tolerance.

11
12
13
14
15
16
17
18
19
20

U15 14

3

POK_U1

4

POK_U2 1
2

74LVC14A7

3_3V11
-12V
GND13
PS_0N
GND15
GND16
GND17
-5V
5V19
5V20

3_3V1
3_3V2
GND3
5V4
ATX
GND5
5V6
GND7
PW_OK
5VSB
12V

1
2
3
4
5
6
7
8
9
10

4

U3
3 POK_U3

14

7
SN74LVC08A

VCC12

J24

4.7K

9,29

R347

VCC3_3SBY

2

74LVC14A7

DBRESET#
330 ohm pullup to VCC3_3 located on CPU sheet.

VCC2_5

VCC3_3SBY

SN74LVC06A has 5V input tolerance.
VCC5SBY

R342

ATX_PWOK

U18
74LS132 14VCC
9
8
10

ATX_PWOK_R

0K
No stuff R342 when ITP is used.

7 GND

C

330

ATX Connector

R96

VCC12-

D

VCC3_3SBY

0K

VCC5SBY

VCC3_3SBY

R339

74LVC14A has 5V input tolerance.
VCC3_3SBY

D

U20 14VCC
1
2
GND
SN74LVC06A7

PWRGOOD

4

VCC3_3SBY
PWROK_INV

4,28

U20 14VCC
3
4

VRM_PWRGD

4.7K

R349

VCC3_3SBY

PWROK 7,9,16,29

GND
SN74LVC06A7

B

B

220 ohm pullup to VCC3_3 is located on VRM sheet.

RSTBTN_SW

R343
22

SW2

VCC3_3SBY

VCC3_3SBY
C335

C328

0.01UF

10UF

JP12

R251
22K

U15 14

5

RSMRST_U

6

1M

R348

Reset Button
No stuff.
For test only

VCC3_3SBY

U15 14
RSMRST

74LVC14A7

9

8

RSMRST#

9,17

74LVC14A7

1UF

1M

R288

C266

No stuff.
For test only

A

A
Resume Reset circuitry
using a 22 msec delay
and Schmitt trigger logic.
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
REV:
POWER CONNECTOR
1.01
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8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

PCI/AGP Pullups/Pulldowns
VCC5

PCI
D

8,20,21
8,20,21

AGP

PIRQ#C
PIRQ#D

8
7
6
5

FRAME#
IRDY#
TRDY#
DEVSEL#

8
7
6
5

RP6

1
2
3
4

2.7K
8,16,20,21
8,16,20,21
8,16,20,21
8,16,20,21

RP10

19
19

1
2
3
4

PROCESSOR

RP11

8
7
6
5

STOP#
PLOCK#
PERR#
SERR#

4,8
4,8
4

2.7K

8,20

C

8,20
8,21
8,16
8
8,21

R112

4,8

R111

2.7K

4,8

2.7K

R115

R216

2.7K

2.7K

R213

R109

2.7K

PREQ#0
PREQ#1
PREQ#2
PREQ#3
PREQ#4
PREQ#5

4,8

FLUSH#
STPCLK#
SMI#
FERR#

150

150

R85

R94

150

150

R123

8
7
6
5

RP16

4,8
4,8
4,8
4,8,10

1
2
3
4

8
8,21

B

8,21
8,21
8,16,19,20,21
8,19,20,21

8.2K

8.2K

R114

GNT#A

R105

8.2K

8.2K

R81

R89

8.2K

PIRQ#A
PIRQ#B

8.2K

8,22

IRQ14
IRQ15

RP9

1
2
3
4

1
2
3
4

C

RP8

8
7
6
5

HINIT#

RP7

8
7
6
5

8.2K

1
2
3
4

7,19
7,19

R198

ADSTB0
ADSTB1

8.2K

R132
8.2K

150
VCC2_5

7,19
7,19
4

ST0
ST1
ST2

R505
8.2K

R506

R507

8.2K

B

8.2K

R127

TESTHI

100K

4,8

VCC5
4

8,22

8
7
6
5

150
LINT0
LINT1
IGNNE#

7,19

R256

REQ#A

GGNT#
PIPE#
WBF#

7,19
7,19
7,19

R214

PGNT#5

8
7
6
5

GREQ#

8.2K
PGNT#4

RP14

8.2K

R126

2.7K

PGNT#1
PGNT#0
PGNT#3
PGNT#2

RBF#
SBSTB#
SBSTB

7,19
7,19
7,19

150

A20M#

D
1
2
3
4

8.2K

VCC2_5

4,8

1
2
3
4

R124

R84

7,19

VCC3_3

8,20
8,20
8,16
8,21

150

PICD1

GSTOP#
GPAR

7,19
7,19

R128

PICD0

RP15

8.2K
GFRAME#
GTRDY#

7,19
7,19

1
2
3
4

8
7
6
5

VCC2_5

2.7K
8,16,20,21
8,20,21
8,16,20,21
8,16,20,21

GIRDY#
GDEVSEL#
GPERR#
GSERR#

7,19
7,19

VDDQ

R95

SLP#

150

7,19
7,19

R102

BREQ#0

ADSTB#0
ADSTB#1

R207
8.2K

R136
8.2K

10

R338
8.2K

R323

VCC3_3
VCC3_3

8.2K
SMBCLK_CORE

3,9,11

SMBDATA_CORE

3,9,11

R235
4.7K

R237
4.7K

A
9
9,16
9,16

8

8,12
VCC3_3SBY

8,12,21

R236

SMB_ALERT

8,12

R324

KBRST#
A20GATE
SERIRQ

8.2K

R327

R314

8.2K

A

8.2K

4.7K
ALERTCLK_SBY
ALERTDATA_SBY

R13
4.7K

R12

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PCI/AGP PULLUPS/PULLDOWNS
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32 OF 36

4.7K

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Rambus Termination

D

D

VCC1_8

C280

TERM_DQB3
TERM_DQB4
TERM_DQB5
TERM_DQB6
TERM_DQB7
TERM_DQB8
TERM_ROW0
TERM_ROW1

TERM_ROW[2:0]
11

TERM_ROW2
TERM_COL0
TERM_COL1
TERM_COL2

TERM_COL[4:0]
11

TERM_COL3
TERM_COL4

B

C283

R284
R268
R267
R266

28
28
28
28

0.1UF

C275

R265
R264
R263
R262

28
28
28
28

0.1UF

C276

R261
R260
R275
R274

28
28
28
28

0.1UF

C271

R276
R269
R271
R270

28
28
28
28

0.1UF

C277

R273
R272

28
28

C282
0.1UF

C273
0.1UF

C274

C

TERM_CMD
TERM_SCK

11
11

0.1UF

90.9-1% R291

11

0.1UF

C279
0.1UF

39.2-1%

C

0.1UF
Stuff C270,C272 with 0 ohm resistors.

R280
R283
R282
R285

28
28
28
28

C278
VCC1_8

C281

R290

TERM_DQA8
TERM_DQB0
TERM_DQB1
TERM_DQB2

TERM_DQB[8:0]

0.1UF

90.9-1% R293

TERM_DQA4
TERM_DQA5
TERM_DQA6
TERM_DQA7

R277
R279
R278
R281

28
28
28
28

39.2-1%

TERM_DQA0
TERM_DQA1
TERM_DQA2
TERM_DQA3

R292

TERM_DQA[8:0]
11

C269
0.1UF

0.1UF

B

NOTE :
Use one 0.1uF cap
per two RSL signals.

A

A

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RAMBUS TERMINATION
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33 OF 36

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Decoupling
MCH Decoupling

0.01UF

0.01UF

0.01UF

0.01UF

C288

C226

C284

C264

C289

C235

C302

0.1UF

Place a VCMOS1_8SBY 0.1uF cap at each RIMM.

VCC3_3SBY

U15 14

U3
8

14

11

U15 14
12
13

13

U3
11

14

10

74LVC14A7

VCC3_3

U19

12

3

74LVC14A7

VCC
4
14

C344

0.1UF

Un-used Gates
VCC3_3SBY

Place these caps on solder side

9
10

C343

0.1UF

C

7
SN74LVC08A

0.01UF

100UF

Place 100uF caps, 0.1 ohm ESR, among RIMM connectors.

VDDQ

B

0.1UF

100UF

100UF

C365

4.7UF

0.1UF

100UF

100UF

C366

4.7UF

0.01UF

100UF

C303

0.01UF

0.1UF

C210

C105

0.1UF

100UF

100UF

C285

C60

0.1UF

VCMOS1_8SBY

C219

C29

0.1UF

VCC2_5SBY

C258

C30

0.1UF

C88

0.1UF

0.1UF

VCC2_5SBY

C290

VDDQ

C253

0.1UF

C231

Place these caps on solder side

C232

0.01UF

0.1UF

C254 C248

0.01UF

0.1UF

C224

0.1UF

0.1UF

C230

0.1UF

VCC3_3SBY

C252

C257
C265
C184

C156

0.01UF

C213

0.1UF

C260

C201

0.01UF

C202

0.1UF

C261

C157
C212

0.1UF

0.01UF

RIMM Decoupling
D

0.1UF

For chipset decoupling, use 0.1UF and
0.01UF decoupling capacitor at each
corner of the device. If there is room,
add 0.01UF capacitors in the middle
of each quad.

82559 Decoupling.

VCC3_3

C221

C

ICH Decoupling

VCC1_8

C197

VCC1_8

C262

D

B

7

0.01UF

U14
0.01UF

9

VCC
8

U18
74LS132 14VCC
1
3
2

7
SN74LVC07A

GND

7 GND

U20 14VCC
9
8
GND
SN74LVC06A7

U19

VCC
10

U18
74LS132 14VCC
12
11
13

14

11

7

A

SN74LVC07A

GND

13

7

U14

SN74LVC07A

U20 14VCC
11
10
GND
SN74LVC06A7

0.01UF

VCC
10
14

11
0.01UF

14

C162

U19

VCC5SBY

7

C367

GND

VCC3_3SBY
VCC3_3SBY

C368

SN74LVC07A

GND

VCC
12
14

C166

7
SN74LVC08A

SN74LVC07A

GND

U20 14VCC
13
12

7 GND

A

GND
SN74LVC06A7

Place VDDQ capacitors within
70 mils of outer balls of MCH.

REV:
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
DECOUPLING
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8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Decoupling

C339
C331
C36

C346
1
2
+
22UF

C342
1
2
+
22UF

0.1UF

0.1UF

C89

0.1UF

0.1UF

0.1UF

D

C

Termination Decoupling
VTT1_5

VCC3_3SBY

C127
C129
C150

C133

10UF

0.1UF

0.1UF

0.1UF

C128 C149

10UF

0.1UF

B

0.1UF
0.01UF

C130

C138

10UF

0.1UF

0.01UF

C115

10UF

0.1UF

0.01UF

C148

C132

10UF

C357

C131

10UF

C65

C141

10UF

0.1UF

C259

C136

10UF

0.1UF

C64

C135

10UF

C240

C137

10UF

C139

VCCVID

C134

B

0.1UF

0.1UF

C340
2
1
+
22UF

Core Voltage Decoupling
VCCVID

C345

0.1UF

C338
1
2
+
22UF

0.1UF

C334

0.1UF

0.1UF

C332

0.1UF

0.1UF

VCC120.1UF

C341

0.1UF

0.1UF

C330

0.1UF

0.1UF

VCC12

VCC5

C337

0.1UF

C172

0.1UF

0.1UF

0.1UF

C195

0.1UF

C152

C144

0.1UF

0.1UF

C176

0.1UF

C163

0.1UF

C178

C310

0.1UF

C147

C351

C154

0.1UF

C151

C146

C153

0.1UF

C181

0.1UF

C175

C143

0.1UF

C238

0.1UF

C145

C125

0.1UF

Bulk Power Decoupling
VCC3_3

C177

C216

0.1UF

C188

C

VCC2_5 Decoupling
VCC2_5

C114

D

VCC3_3 Decoupling
VCC3_3

C106

VCC3_3 Decoupling
VCC3_3

0.01UF

A

A

Place caps at VTT pins on Slot 1 connector.
REV:
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
BULK DECOUPLING
1.01
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35 OF 36

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2

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1

Revision History

Revision 1.01

D

D
Pg 6

Modified MCH_AGPREF circuit, changed 432 ohm to 1K ohm and 62 ohm to 80.6 ohm.
Changed value of capacitor C194 from 0.1uF to 0.01uF.

Pg 8

Modified HUBREF circuit, deleted R222, R223 & C217, changed C218 from 470pF to 0.1uF.

Pg 11

Modified RIMM connectors to eliminate 3.3V, added 0.1uF decoup caps to SVDDA & SVDDB on each RIMM.

Pg 33

Modified CMD and SCK termination values. Removed 470pF capacitors, Changed 93 ohm to 90.9 ohm,
and changed 39 ohm to 39.2 ohm resistors.

Pg 34

Deleted 3.3V decoupling for RIMM connectors. Added solder side decoup for MCH.
Changed VDDQ cap values from 0.1uF to 0.01uF.

C

C

B

B

A

A

REV:
TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
REVISION HISTORY
1.01
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Hub Link Connector
For debug only.
D

D

7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8

B
7,8

HL0
HL1
HL2
HL3
HL9
HL_STB
HL_STB#
HL10
HL8
HL4
HL5
HL6
HL7

HUBREF

49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

C

TEST_CLK66

50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6

5
7,8

PROBE CONNECTOR

4 2

J26

6,8

C

VCC1_8

B

P08-050-SL-A-G

A

A

REV:
1.01
PROJECT:

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD
R

8

7

6

5

4

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1

B
Reference Board
Schematics: Dual-Processor

This page is intentionally left blank.

Reference Design Schematics: Dual-Processor

Reference Design Schematics:
Dual-Processor
B.1

B

Reference Design Feature Set
The reference schematics feature the following core feature set:

• Intel® 820 Chipset
— Memory Controller Hub (MCH)
— I/O Controller Hub (ICH)
— FWH Flash BIOS interface

• Support for the two Pentium III (SC242) Processors
— 100/133 MHz System Bus Frequency
— Debug Port

• IOAPIC Integrated into the ICH
• Direct RDRAM Memory Interface
— 266 MHz, 300 MHz, 356 MHz and 400 MHz Direct RDRAM Support
— 2 RIMM Sockets

• 4 PCI Add-in Slots
— Via 4 REQ/GNT pairs (ICH supports 6 REQ#/GNT# pairs)

• AGP Universal Connector
— 3.3V - 1X,2X signaling
— 1.5V – 1X, 2X, 4X signaling

•
•
•
•

2 IDE Connectors with Ultra ATA/66 Support

•
•
•
•

AC‘97 Bus Connector and Audio Codec

2 USB Connectors
ATX Power Connector
LPC Ultra I/O
— Floppy Disk Controller
— 1 Parallel Port, 2 Serial Ports
— Keyboard Controller

WfM Support
Integrated System Management
Integrated Power Management
— ACPI Rev. 1.0 Compliant
— APM Rev. 1.2 Compliant

• Pentium III on-board VRM 8.4 compliant regulator
• 4 Layer Design
Intel®820 Chipset Design Guide

B-1

8

7

6

5

4

3

2

1

INTEL(R) 820 CHIPSET
DUAL PROCESSOR CUSTOMER REFERENCE SCHEMATICS
D

Title

Pa g e

Co v e r S h e e t
B lo c k Dia g r a m

2

Pr o c e s s o r Co n n e c to r

3, 4, 5, 6

Clo c k S y n th e s iz e r

7

MCH

8, 9

ICH

10, 11

FW H
C

12

RIMM S o c ke ts

13

S u p e r I/O

14

A u d io

15, 16

A u d io /Mo d e m Ris e r

17

LA N

B

18, 19

S y s te m

20

A G P Co n n e c to r

21

PCI Co n n e c to r s

22, 23

IDE Co n n e c to r s

24

US B Co n n e c to r s

25

Pa r a lle l Po r t

26

S e r ia l Po r ts

27

K e y b o a r d /Mo u s e /Flo p p y Po r ts

28

G a me Po r t

29

V RM

30

V o lta g e Re g u la to r s

Note that these schematics are preliminary and are subject to change.
C

THESE SCHEMATICS ARE PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER,
INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR
PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL,
SPECIFICATION OR SAMPLES.
Information in this document is provided in connection with Intel products. No license, express or
implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or
use of Intel products including liability or warranties relating to fitness for a particular purpose,
merchantability, or infringement of any patent, copyright or other intellectual property right. Intel
products are not intended for use in medical, life saving, or life sustaining applications. Intel may
make changes to specifications and product descriptions at any time, without notice.

33

PCI/A G P Pu llu p s /Pu lld o w n s

34

Ra mb u s Te r min a tio n

35

De c o u p lin g

36, 37

Re v is io n His to r y

The Intel® 820 chipset may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. Current characterized errata are available on
request.
Intel may make changes to specifications and product descriptions at any time, without notice.
Copyright © Intel Corporation 1999.
A

*Third-party brands and names are the property of their respective owners.

38
TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
3.03
DRAWN BY:
PROJECT:
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1900 PRAIRIE CITY ROAD
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1 OF 38

8

B

31, 32

Po w e r Co n n e c to r

A

D

1

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Block Diagram
Clock

Device Table
VRM

D

Processor

Processor

VRM

DATA

CTRL

ADDR

DATA

CTRL

ADDR

REFERENCE
DESIGNATOR

DATA

CTRL

ADDR

AGP Bus
Rambus

AGP

3 RIMM
Modules

MCH

C
IDE Primary

UltraDMA/66

IDE Secondary
PCI CNTRL

ICH

AC’97 Link

LPC Bus

AC’97 Audio

Modem
82559 LAN

SIO

B
FWH

Keyboard

Floppy

Parallel

Game Conn

Mouse
Serial 1
Serial 2

A

PCI CONN 4

PCI ADDR/DATA

USB Port 2

PCI CONN 3

USB

PCI CONN 2

PCI CONN 1

USB Port 1

U20
U14
U19
U3
U9
U26
U15
U23
U18
U22
U25
U13
U10
U5
U24
U2
U11
U12
U16
U4, U6
U1
U17
U21
U8
U7

DEVICE
TYPE
74LVC06A
74LVC07A
74LVC07A
74LVC08A
74LVC08A
74LVC08A
74LVC14a
74LVC14a
74LS132
74LVC07A
74F74
82801 (ICH)
82820 (MCH)
82559
93C46A
AD1881
CK133
DRCG
FWH
GD75232
LM4880
LPC47B27X
ADM1021
ADM1021
TPS2042

GATES
USED
A,
A,
A,
A,
A,
A
A,
A,
A,
A,
A,

B,
B,
B,
B,
B

C,
C,
C,
C,

D, E, F
D, E, F
D, E, F
D

B, C, D, E, F
B, C, D
B, C, D
B
B

SHEET
NUMBER
33, 36
9,20,31,36
20,24,36
36, 33, 17
33
33
33, 36
33
31, 33, 36
33
4
10, 11
8, 9
18
18
15
7
7
12
27
16
14
3
5
25

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
BLOCK DIAGRAM
3.03
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2 OF 38

8

7

6

5

4

3

2

1

D

C

B

A

8

7

6

5

4

3

2

1

Processor Connector 0
HA#[31:0]

HD#[63:0]

5,8

J15

B

A

8

7

D

SC242

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HA#32
HA#33
HA#34
HA#35

B98
A100
A97
B99
B96
B95
A99
A96
B92
B94
A93
A95
B90
A92
B91
A91
A89
B86
B87
A85
A87
B83
B88
B82
A84
B84
B80
A81
A83
B79
A79
A80
B78

VID0
VID1
VID2
VID3
VID4

B120
A120
A119
B119
A121

VID0
VID1
VID2
VID3
VID4

VID[4:0]

RS#0
RS#1
RS#2

B108
A112
B111

RS#0
RS#1
RS#2

RS#[2:0]

RSP#

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

C

VCC3_3

30

B102
B103
A107
A108
B104

RP#

B114

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

DXP
DXN

1
5
9
13
16

NC1
NC5
NC9
NC13
NC16

STBY#

15

ADD0
ADD1

10
6

SMBCLK
SMBDATA
ALERT#

14
12
11

5,8

B115

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4

3
4

HREQ#[4:0]

5,8

B

U21
VCC3_3
ADM1021

2

C

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

VCC2

D

B72
A73
B71
A72
B70
A71
B68
B67
A69
A68
A65
A64
B66
A63
A67
B64
A61
B63
B60
B59
B62
A60
B58
A59
A57
B56
B55
A56
B52
B54
A55
A53
B51
A51
B48
A52
B46
A49
B50
A45
B47
B42
A43
A48
B44
A44
A39
B43
B39
A40
B35
A41
B40
A36
B36
A33
B34
A37
B31
B38
A35
A32
B30
B32

SMBCLK_CORE
SMBDATA_CORE
THRM#

5,11,13,34
5,11,13,34
5,11

7
8

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

GND8
GND7

5,8

THRMDN
THRMDP

B15
B14

RESERVED3

B12

RESERVED2
RESERVED1
RESERVED0

A116
A88
A47

R19
0K

THRMDN
R100
THRMDP
0K
THRMDP and THRMDN signals must be disconnected from onboard thermal sensor
during SECC2 thermal testing of the processor. Please see the "Pentium(R) II processor Single Edge
Contact Cartridge 2 Thermal Validation" document for further details.
Place R19, R100 very close to processor.

THRMDN_R
THRMDP_R

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
PROCESSOR CONNECTOR
3.03
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6

5

4

3

2

1

8

7

6

5

4

3

2

1

Processor Connector 0
VTT1_5

VCCVID

VCC5

VCC3_3

D

ITP

D

VCC3_3

VCC2_5

VTT1_5

VCC2_5

VTT1_5

150
R218

BINIT#

B19
A21
A23
B24
A24

BP2#
BP3#
BPM0#
BPM1#
BINIT#

PICD0
PICD1
PICCLK

A19
B22
B18

PICD0
PICD1
PICCLK

150

330

R380

330

R76

R387

1K

1K
R18

1K
R63

240

R159

R17

4
4

R376

TRST# 6
ITPREQ#
4
ITPRDY#_R
ITPREQ1#
ITPRDY1#_R

8.2K
6

6

6,10,34
6,10,34
7

240

R94

47

R11

240

ITPCLK

7

TDI
TDO

680

6

VCC3_3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

R93

TCK_R XREF=6

TMS_R

J26

R386

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

ITPPRDY#

47

R7

SLOTOCC0#
4
4,6

33

4
6

ITPRDY1#

B101
A9
A11
B11
B7
B10

SLOTOCC#
TDI
TDO
TRST#
TCK
TMS

B61
B100
B81
B1
B41

EMI_1
EMI_2
EMI_3
EMI_4
EMI_5

CPUHCLK

A75

BCLK

PWRGOOD
CPURST#

A12
B74

PWRGOOD
RESET#

TDI_0
TDO_0

TCK 6
TMS
EMI1
EMI2
EMI3
EMI4
EMI5

R7 and R11 should be placed within 1" of ITP connector.

R5

0K

R4

R3

0K

R2

0K

R1

CPU TACH0

0K

VCC12

0K

B

C36

6,7

HITM#
HIT#
DBSY#
HADS#

SC242

1
2

6

TDO

4

4 TDI

3

TDO_1

7

330

BSEL0
BSEL1

B21
A14

FLUSH#

B2

THMTRP#

A15

A20M#
STPCLK#
SLP#
SMI#
LINT0
LINT1
INIT#
FERR#
IGNNE#
IERR#
BERR#
AERR#
RES0
RES1
RES2
RES3

A5
B6
B8
B3
A17
B16
B4
A7
A8
A4
A77
B118
A16
B20
B112
A113

ITPREQ#
ITPPRDY#
BREQ#0
BREQ#1
TESTHI

SEL133/100#
FLUSH#

A20M#
STPCLK#
SLP#
SMI#
LINT0
LINT1
HINIT#
FERR#
IGNNE#

6,8
6,8
6,8
6,8
6,8
6,8
6,8
6,8
6,8
6,8

C
VCC3_3

4
4
6
6

R375

220
34

6,7,9
6,34

6,10,34
6,10,34
6,10,34
6,10,34
6,10,34
6,10,34
6,10,12,34
6,10,34
6,10,34

TDI_0

4

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
PROCESSOR CONNECTOR
3.03
DRAWN BY:
PROJECT:
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4 OF 38

2
3

6

5

4

B

A

JP34

1

TDO_0

R388

150

R92

JP33
4,6

TESTHI

A20
B23
A76
B75
B76
A13

PREQ#
PRDY#
BREQ0#
BREQ1#
RES4

BNR#
BPRI#
HTRDY#
DEFER#
HLOCK#
DRDY#
HITM#
HIT#
DBSY#
HADS#

A118
A114
A110
A106
A102
A98
A94
A90
A86
A82
A78
A74
A70
A66
A62
A58
A54
A50
A46
A42

JP34
1-2
1-2
2-3

A117
B116
A101
A103
A104
A105
B106
B107
A109
B110
A111
A115

GND29
GND28
GND27
GND26
GND25
GND24
GND23
GND22
GND21
GND20
GND19
GND18
GND17
GND16
GND15
GND14
GND13
GND12
GND11
GND10

JP33
1-2
2-3
2-3

A38
A34
A30
A26
A22
A18
A10
A6
A2

ITP Config
Single CPU0
Dual CPU
Single CPU1

GND9
GND8
GND7
GND6
GND5
GND4
GND2
GND1
GND0

A

8

TRDY#
DEFER#
LOCK#
DRDY#

VCC2_5

150

1
2
3

AP0#
AP1#
BNR#
BPRI#

VCC2_5

JP31

R64

0.1UF

6,33
4,6,8

B121 VCC3_3
B117 VCC3_2
B113 VCC3_1

DEP#0
DEP#1
DEP#2
DEP#3
DEP#4
DEP#5
DEP#6
DEP#7

B109 VCC5

R95
4,6,8CPURST#
CPURST#_R
DBRESET# 240

VCCP19
VCCP18
VCCP17
VCCP16
VCCP15
VCCP14
VCCP13
VCCP12
VCCP11
VCCP10
VCCP9
VCCP8
VCCP7
VCCP6
VCCP5
VCCP4
VCCP3
VCCP2
VCCP1

VTT4
VTT3
VTT2
VTT1

A25
A27
B26
A28
B27
A29
A31
B28

ITP_PU_R

C 33

B105
B97
B93
B89
B85
B77
B73
B69
B65
B57
B53
B49
B45
B37
B33
B29
B25
B17
B13

B9
B5
A3
A1

J15

3

2

1

8

7

6

5

4

3

2

1

Processor Connector 1
HA#[31:0]

HD#[63:0]

3,8

J120

B

A

8

7

D

SC242

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HA#32
HA#33
HA#34
HA#35

B98
A100
A97
B99
B96
B95
A99
A96
B92
B94
A93
A95
B90
A92
B91
A91
A89
B86
B87
A85
A87
B83
B88
B82
A84
B84
B80
A81
A83
B79
A79
A80
B78

VID0
VID1
VID2
VID3
VID4

B120
A120
A119
B119
A121

VID1[0]
VID1[1]
VID1[2]
VID1[3]
VID1[4]

VID1[4:0]

RS#0
RS#1
RS#2

B108
A112
B111

RS#0
RS#1
RS#2

RS#[2:0]

RSP#

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

C

VCC3_3

30

B102
B103
A107
A108
B104

RP#

B114

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

DXP
DXN

1
5
9
13
16

NC1
NC5
NC9
NC13
NC16

STBY#

15

ADD0
ADD1

10
6

SMBCLK
SMBDATA
ALERT#

14
12
11

3,8

B115

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4

3
4

HREQ#[4:0]

3,8

VCC3_3

B

U8
ADM1021

2

C

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

VCC2

D

B72
A73
B71
A72
B70
A71
B68
B67
A69
A68
A65
A64
B66
A63
A67
B64
A61
B63
B60
B59
B62
A60
B58
A59
A57
B56
B55
A56
B52
B54
A55
A53
B51
A51
B48
A52
B46
A49
B50
A45
B47
B42
A43
A48
B44
A44
A39
B43
B39
A40
B35
A41
B40
A36
B36
A33
B34
A37
B31
B38
A35
A32
B30
B32

SMBCLK_CORE
SMBDATA_CORE
THRM#

3,11,13,34
3,11,13,34
3,11

7
8

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

GND8
GND7

3,8

THRMDN
THRMDP

B15
B14

RESERVED3

B12

RESERVED2
RESERVED1
RESERVED0

A116
A88
A47

THRMDN1_R
THRMDP1_R

R121
0K

THRMDN1
R122
THRMDP1
0K
THRMDP and THRMDN signals must be disconnected from onboard thermal sensor
during SECC2 thermal testing of the processor. Please see the "Pentium(R) II processor Single Edge
Contact Cartridge 2 Thermal Validation" document for further details.
Place R121, R122 very close to processor.

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
PROCESSOR CONNECTOR
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-30-1999_9:57
5 OF 38

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Processor Connector 1
VTT1_5

D

VCC5

VCC5

C

BREQ#0

14
5
6
9
8

1K

B

A25
A27
B26
A28
B27
A29
A31
B28

DEP#0
DEP#1
DEP#2
DEP#3
DEP#4
DEP#5
DEP#6
DEP#7

BINIT#

B19
A21
A23
B24
A24

BP2#
BP3#
BPM0#
BPM1#
BINIT#

PICD0
PICD1
PICCLK1

A19
B22
B18

PICD0
PICD1
PICCLK

C

Q16
R392

1

3
2
E

7

VCC3_3

R390
C

Q17
4.7K

B

1

3

2N3904

CPURST# R103

2

8.2K
4

E
4,10,34
4,10,34
7
33

4
4

R395

TCK_R
TMS_R

R391

SLOTOCC1#

47

47

B101
A9
A11
B11
B7
B10

SLOTOCC#
TDI
TDO
TRST#
TCK
TMS

B61
B100
B81
B1
B41

EMI_1
EMI_2
EMI_3
EMI_4
EMI_5

CPUHCLK1

A75

BCLK

PWRGOOD
CPURST#

A12
B74

PWRGOOD
RESET#

TDO_0
TDO_1
TRST#

4
4
4
TCK

TMS1

B

EMI1_1
EMI1_2
EMI1_3
EMI1_4
EMI1_5

VCC12

0K

0K

R145

0K

R142

0K

R140

0K

R139

R138

CPU TACH1
7
4,33
4,6,8

0.1UF

C110

AP0#
AP1#
BNR#
BPRI#
TRDY#
DEFER#
LOCK#
DRDY#
HITM#
HIT#
DBSY#
HADS#

SC242

TESTHI
BSEL0
BSEL1

B21
A14
B2

THMTRP#

A15

A20M#
STPCLK#
SLP#
SMI#
LINT0
LINT1
INIT#
FERR#
IGNNE#
IERR#
BERR#
AERR#
RES0
RES1
RES2
RES3

A5
B6
B8
B3
A17
B16
B4
A7
A8
A4
A77
B118
A16
B20
B112
A113

BNR#
BPRI#
HTRDY#
DEFER#
HLOCK#
DRDY#
HITM#
HIT#
DBSY#
HADS#
ITPREQ1#
ITPRDY1#
BREQ#1
BREQ#0
TESTHI1

SEL133/100#
FLUSH#

A20M#
STPCLK#
SLP#
SMI#
LINT0
LINT1
HINIT#
FERR#
IGNNE#

4,8
4,8
4,8
4,8
4,8
4,8
4,8
4,8
4,8
4,8

C
VCC3_3

4
4
4
4,6

R389

220
34

4,7,9
4,34

4,10,34
4,10,34
4,10,34
4,10,34
4,10,34
4,10,34
4,10,12,34
4,10,34
4,10,34

A118
A114
A110
A106
A102
A98
A94
A90
A86
A82
A78
A74
A70
A66
A62
A58
A54
A50
A46
A42

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
PROCESSOR CONNECTOR
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:45
6 OF 38

8

7

6

5

4

B

GND29
GND28
GND27
GND26
GND25
GND24
GND23
GND22
GND21
GND20
GND19
GND18
GND17
GND16
GND15
GND14
GND13
GND12
GND11
GND10

A38
A34
A30
A26
A22
A18
A10
A6
A2

A

A117
B116
A101
A103
A104
A105
B106
B107
A109
B110
A111
A115
A20
B23
A76
B75
B76
A13

PREQ#
PRDY#
BREQ0#
BREQ1#
RES4

FLUSH#

JP32

GND9
GND8
GND7
GND6
GND5
GND4
GND2
GND1
GND0

1
2
3

D

4,6

2N3904

D1
VCC
CLK1 Q1
CLR1# Q1#
PR1#
D2
Q2
CLK2 Q2#
CLR2#
PR2# GND
74F74

4,6,8

VCC3_3

B121 VCC3_3
B117 VCC3_2
B113 VCC3_1

2
3
1
4
12
11
13
10

CPUHCLK

B109 VCC5

U25
4,7

VCCP19
VCCP18
VCCP17
VCCP16
VCCP15
VCCP14
VCCP13
VCCP12
VCCP11
VCCP10
VCCP9
VCCP8
VCCP7
VCCP6
VCCP5
VCCP4
VCCP3
VCCP2
VCCP1

VTT4
VTT3
VTT2
VTT1

2.7K

2.7K

VCC5

B105
B97
B93
B89
B85
B77
B73
B69
B65
B57
B53
B49
B45
B37
B33
B29
B25
B17
B13

B9
B5
A3
A1

J120

R102

R101

VCCVID1

VCC5

3

2

1

8

7

6

5

4

3

2

1

VCC2_5

Clock Synthesizer

VCC3_3

1

L20

1

2

L21

2

FBHS01L
Provide at least one 0.1uF decoupling cap per power pin.

FBHS01L

VCC_3_3_CK133_FB

VCC2_5_CK133_FB
10UF

0.1UF

0.1UF

0.1UF

0.1UF

10
6

ITPCLK
R189
MCHCLK
22
R184
CPUHCLK
22
CPUHCLK1
R170
R164

33

33
R183

33

33
R187

33

33
R194

33

R201
R195
R211
R147

33
33
22

SIO_14MHZ

22
No stuff R106
for debug.
VCC1_8

10
22
22
23
23

C

18
12
14
21
9
11

VDDIR pin on DRCG should be decoupled at the component with a 0.1uF cap.
CLKTM and CLKTM# RC network must use 5% or better tolerance components.
VCC3_3

11
11
14

VCC2_5
1

VCC1_8

JP17
IN
OUT
IN

OUT
IN
IN
OUT
OUT

OUT
IN
OUT
IN
OUT

11

HCLKOUT
RCLKOUT

DRCG_CTRL

11,14

Active 100MHz, 48MHz PLL active
Test Mode
Reserved
Active 133MHz,48MHz PLL inactive
Active 133MHz,48MHz PLL active*

MULT1_GPIO

1
2
3

JP18

6

C209

B

DRCG_CLK
CLK
CLKB#

C220

39-1%

CLKTM

13

R182

20
18

39-1%
DRCG_CLKB#

51-1%

51-1%

R185

R200

C80

CLKTM#

R205

13

No stuff C80

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
CLOCK SYNTHESIZER
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
7 OF 38

No stuff R161, JP11.

7

REFCLK
PWRDN#
STOPB#
MULT0
MULT1
S0
S1
GND
PCLKM
SYNCLKN
NC

C204

C205

All jumpers may not be required, but are included for test purposes.

8

1
10
16
22
3
9
VDDIR
VDDIPD
VDDO1
VDDO2
VDDP
VDDC

10K

10K

R199

10K
R204

10K

R217

9
9

Function
All outputs Tri-State
Reserved
Active 100MHz, 48MHz PLL inactive

JP11

0
1
1
1
1

DRCG_PWRDWN#
STOPB#
MULT0
MULT1

2
12
11
15
14
24
23
13
6
7
19

GNDO1
GNDO2
GNDP
GNDC
GNDI

JP 14
IN
OUT

1
2
3

C196

0.1UF

A

JP15
IN
IN
OUT

MULT0_GPIO

JP13 is for debug only. JP13

C208

17
21
4
8
5

SEL133/100#
0
0
0

JP 18
OUT
OUT
OUT
OUT

2

CLKTM_RD

S p rd S p e c t
E n a b le d *
D is a b le d

11

VCC3_3

JP 13
2 -3
OUT
2 -3
1 -2

10K

HOST
B U S /R A M B U S
100/300
100/400
133/400
G P O C N TR L *

R161

B

R219

U12
DRCG

L22

FBHS01L

VCC3_3_DRCG_FB

1
7
13
19
20
24
52
48
44
40
38
29

VCC3_3

Keep stubs on unused outputs as short as possible.
Tie CPUCLK and MCHCLK outputs together.

4
8
4,6
6

ICHPCLK
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
FWHPCLK
SIO_PCLK7
AGPCLK_CONN
MCH_CLK66
ICH_CLK66
TEST_CLK66
ICH_48MHZ
ICH_14MHZ

33

R210
33
ICH_CLK66_R
TEST_CLK66_R
R221
IHC_48MHZ_R
22
IHC_14MHZ_R
R150
SIO_14MHZ_R

4

APICCLK
PICCLK1
CPU_DIV2

R148

10UF

R156

4PF

JP14

R165
ICHPCLK_R
PCLK1_R
R169
PCLK2_R
PCLK3_R
R186
PCLK4_R
PCLK5_R
R191
FWHPCLK_R
SIO_PCLK7_R
MCH_CLK66_R 33

22
22

0.1UF

8
9
11
12
14
15
17
18
21
22
25
26
30
2
3

PICCLK

22

0.1UF

PCICLK_F
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7
3V66_0
3V66_1
3V66_2
3V66_3
48MHZ
REF0
REF1

SEL133/100#
PCISTOP#
CPUSTOP#
PWRDWN#
SPREAD#
SEL1
SEL0

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12

JP15

28
37
36
35
34
33
32

R155
PICCLK_R
APICCLK_R
22
PICCLK1_R
CPU_DIV2_1_R R151
CPU_DIV2_2_R
R188
22
ITPCLK_R
CPUHCLK_R
22
CPUHCLK1_R

0.1UF

JP17

XTAL_IN
XTAL_OUT

220

4,6,9 SEL133/100#
PCISTOP#
CPUSTOP#
CK133_PWRDWN#
SPREAD#
SEL1
SEL0

C

5
6

53
54
55
50
49
41
42
45
46

0.1UF

10PF

APIC0
APIC1
APIC2
CPU_DIV2_1
CPU_DIV2_2
CPUCLK0
CPUCLK1
CPUCLK2
CPUCLK3

30

R224

10K

10K
R192

10K
R196

10K
R197

10K
R202

10K
R203

10PF

C189

R166

1
2
14.318MHZ

2_5V

C185

R206

56
51
47
43

CK133_XOUT
VCC3_3

D

33

Y3
XTAL
VCC3_3

R220

CK133_XIN

VDD25V_1
VDD25V_2
VDD25V_3
VDD25V_4

VDD3V_1
VDD3V_2
VDD3V_3
VDD3V_4
VDD3V_5
VDD3V_6
VDD3V_7

10UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

D

4
10
16
23
27
39
31

C180 C190 C192 C199 C171
U11
CK133

C207 C215 C223 C186 C198 C206 C214 C170

5

4

3

2

1

3

RAMREF

2

VTT1_5

VTT1_5

75-1%

R143

0.001UF

150-1%

R144
C187

80.6-1%

R160

C

MCH_AGPREF

470PF

VCC1_8

B

RS#[2:0]
3,5

RAMREF

8,13

HREQ#[4:0]
3,5
VCC1_8

MCHCLK

V2

RSTIN#
HLCOMP

F20
A18

PCIRST#
MCH_HLCOMP

TEST/GRCOMP

T15

GRCOMP

7

MCH_AGPREF_CG

Place MCH_AGPREF circuit near the MCH.

4,6
4,6
4,6
4,6
4,6
4,6
4,6
4,6
4,6
4,6
4,6

HCLKIN

80.6-1%

21
R153

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

1K-1%

H1
G4
E4
E3
G2

MCH_AGPREF_CV

162-1%

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

470PF

562-1%

RS#0
RS#1
RS#2

C183

VDDQ

R154

E5
C1
E2

C158

1K-1%

RS#0
RS#1
RS#2

GTLREF1

R149

CPURST#
HADS#
BNR#
BPRI#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HTRDY#

GTLREF2

C182

P4
D2
F5
G1
D1
F2
F1
D3
E1
F3
F4

3,5

R190

CPURST#
ADS#
BNR#
BPRI#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HTRDY#

D

HA#[31:0]

R181

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

0.001UF

J1
H3
H4
G5
K2
H5
H2
J4
L1
J5
K1
J2
K5
K3
L4
K4
L2
N2
M3
M2
M1
N5
M4
P1
N1
P2
P3
N4
M5

R130

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

75-1%

0.1UF

R131
HOST

1

8,13

C203

0.1UF

GTLREFA
GTLREFB

HOST

VCC1_8;D4,E6,F6,G6,E7,R6,R7,E8,E9,D10,D11,E12
VCC1_8;E13,E14,F14,T14,E15,P15,B17,C17,C19
VDDQ;F15,R15,J17,L17,N17,T17
GND;A1,A3,G3,J3,L3,N3,R3,V3,B4,D5,L5,U5,B6,D6,D7,V7,B8,D8
GND;D9,J9,K9,L9,M9,V9,B10,J10,K10,L10,M10,C11,J11,K11,L11
GND;M11,V11,C12,D12,J12,K12,L12,M12,B13,D13,V13,T13,D14
GND;B15,D15,B16,D16,E16,F16,A17,E18,V18,A19,H19,K19,M19
GND;P19,T19,D20

0.1UF

8
8

C3
V12

7

RAMREFA
RAMREFB

Y1
U2
W4
W3
V4
U4
T3
Y4
Y5
T4
V5
T5
Y6
W5
U6
V6
W6
T6
W7
U7
Y8
Y7
T8
W8
T7
W9
U8
W10
Y10
V8
U9
Y9
W11
T9
Y11
T10
T12
U10
V10
W12
T11
U13
Y13
Y12
W14
U11
U12
Y14
V14
W13

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

AGPREF

8

U10
MCH_096
R2
R1
R4
P5
T1
R5
V1
Y2
W1
U1
T2
Y3
W2
U3

E11
E10

A

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HUBREF

B

GTLREF2
GTLREF1

C155

U14

C

0.01UF

E20

D

4
R168
100-1%
C191

MCH
HD#[63:0]

5
RAMREF_R

CONN_AGPREF

R180

C194 21

3,5

6

HUBREF

150-1%

7
10

40.2-1%

8

10,12,13,14,18,21,22,23,24

A

R129

Place R129 and R180 less than 0.5" from MCH using 10 mil trace.

40.2-1%

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
MCH
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-30-1999_10:02
8 OF 38

6

5

4

3

2

1

8

7

6

5

4

3

2

1

MCH
U10
MCH_096

B

7
VCC1_8

C361
C359

0.1UF

C360

0.1UF

C362

A

21,34
21,34

GFRAME#
GDEVSEL#
GIRDY#
GTRDY#
GSTOP#
GPAR
GREQ#
GGNT#
PIPE#

21,34
21,34
21,34

0.1UF

21,34

G_FRAME#
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
PIPE#

W18 CLK66

RBF#
WBF#

V16 RBF#
V15 WBF#
ST0
ST1
ST2

ST[2:0]

0.1UF

L16
N19
N20
M20
M18
K16
U15
Y16
W16

MCH_CLK66

21
21,34
21,34

G_C/BE#0
G_C/BE#1
G_C/BE#2
G_C/BE#3

W15
Y15
Y17

ADSTB0
ADSTB#0

J19
H20
R18
R19
Y20
Y19

ADSTB1
ADSTB#1
SBSTB
SBSTB#

MEMORY

HL_STB
HL_STB#

D19
C20

HL_STB
HL_STB#

RCLKOUT
HCLKOUT

B1
A2

10

D

9,10

C7
B7
C6
A6
C5
A5
B5
A4
C4

LDQB0
LDQB1
LDQB2
LDQB3
LDQB4
LDQB5
LDQB6
LDQB7
LDQB8

RQ0
RQ1
RQ2
RQ3
RQ4
RQ5
RQ6
RQ7

A7
C8
A8

LCOL0
LCOL1
LCOL2
LCOL3
LCOL4
LROW0
LROW1
LROW2

13

VCC3_3SBY

U14
11,18,31,33

VCC
12

13

PWROK

SN74LVC07A

C

PWROK_CTRL
9

GND

LDQB[8:0]
13

LSCK and LCMD must neck down to 5 mils for 175 mils at Q10 and Q9 attach points.
Place Q10 and Q9 as close as possible to MCH.
VCC5SBY
LCOL[4:0]
13

LSCK

4.7K

B

13

LROW[2:0]
13

LCLKTM
LCLKTM#
LCLKFM
LCLKFM#

B11
A11
A12
B12

VCC3_3SBY

R248

DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8

7
7
LDQA[8:0]

14

LDQA0
LDQA1
LDQA2
LDQA3
LDQA4
LDQA5
LDQA6
LDQA7
LDQA8

13
13
13
13

SCK_CTRL
C

Q10
3

1

B

9

E

C

Q14

2
PWROK_CTRL

B

1

3
2
E

ST0
ST1
ST2
AD_STB0
AD_STB#0
AD_STB1
AD_STB#1

CMD
SCK
SIO

B3
B2
C2

SBA0
SBA1

W20
V17
Y18
W17
V20
W19
V19
U16

SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

AGP

SB_STB
SB_STB#

LCMD 13
C

Q9

LSIO

13
SBA[7:0]

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

B
21

1

3
2
E

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
MCH
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
9 OF 38

No stuff. For test only.

8

8.2K

4,6,7

4.7K

RCLKOUT
HCLKOUT

A13
C13
A14
C14
B14
C15
A15
C16
A16

CTM
CTM#
CFM
CFM#

SEL133/100#

10
10

DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8

C9
B9
A9
A10
C10

R209

HL10

MMBT3904LT1

21,34
21,34
21,34
21,34
21,34
21,34
21,34
21,34
21,34

H16
L20
N18
R16

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10

R346

GC/BE#0
GC/BE#1
GC/BE#2
GC/BE#3

AGP

F19
F18
E17
E19
B20
B19
B18
A20
D17
C18
D18

MMBT3904LT1

GC/BE#[3:0]
21

HUB

HL[10:0]

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10

MMBT3904LT1

C

G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD10
G_AD11
G_AD12
G_AD13
G_AD14
G_AD15
G_AD16
G_AD17
G_AD18
G_AD19
G_AD20
G_AD21
G_AD22
G_AD23
G_AD24
G_AD25
G_AD26
G_AD27
G_AD28
G_AD29
G_AD30
G_AD31

8.2K

D

F17
G18
G17
G19
G16
G20
H17
H18
J20
J16
K17
K18
J18
L19
K20
L18
M17
P18
M16
P17
N16
P20
P16
R20
T20
R17
U17
T16
U18
T18
U20
U19

7

GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

R227

GAD[31:0]
21

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

ICH
U13
ICH_096

7

CBE0#
CBE#1
CBE#2
CBE#3

DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PCIRST#
PLOCK#
SERR#
PERR#
PCI_PME#
REQ#A
GNT#A

D9
B3
A2
C4
D5
A9
J5
B9
A1
E9
K1
N6

DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PCIRST#
PLOCK#
SERR#
PERR#/GPIO7
PME#
GPIO0/REQ#A

P5

GPIO16/GNT#A

ICHPCLK

C14

PCICLK

HUB

AD22
AD23
AD24
AD25
AD26
AD27
AD28

HL0

D17

HL1
HL2
HL3
HL4
HL5

E17
F17
G16
J15
K16

HL6
HL7
HL8
HL9

K17
L17
H15
J17

HL10
HL11

J14
F16
G17
H17
M17
J13

HL_STB
HL_STB#
HLCOMP
HUBREF

PCI

4,6,34
4,6,34
4,6,34
4,6,34
4,6,12,34
4,6,34
4,6,34
4,6,34
4,6,34
14,34
14,34
HL[10:0]

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HL11_TP

D

9

Place R239 less than 0.5" from the ICH using a 10 mil trace.
VCC1_8

TP1

HL_STB
HL_STB#
ICH_HLCOMP

9

C

9
HUBREF

8,10

C237

IRQ

PCI

PIRQA#
PIRQB#
PIRQC#

D10

PIRQD#

C10

PIRQ#A
PIRQ#B
PIRQ#C
PIRQ#D

IRQ14
IRQ15
APICCLK
APICD0
APICD1
SERIRQ

P11
N14
C16
E16
C17
R4

IRQ14
IRQ15
APICCLK
PICD0
PICD1
SERIRQ

A10
B10

REQ#0 A14
REQ#1 B13
REQ#2 B12
REQ#3 D12
REQ#4 B11
P4
GPIO1/REQ#B/REQ#5

PREQ#0
PREQ#1
PREQ#2
PREQ#3
PREQ#4
PREQ#5

A13
C13
A12
C12

PGNT#0
PGNT#1
PGNT#2
PGNT#3
PGNT#4
PGNT#5

GNT#0
GNT#1
GNT#2
GNT#3

GNT#4 A11
GPIO17/GNT#B/GNT#5 R5

0.01UF

18,21,22,23,34
21,22,23,34
22,23,34
22,23,34

Place C237 close to ICH.

24,34
24,34
7
4,6,34
4,6,34
14,23,34

VCC1_8

B

22,34
22,34
23,34
18,34
34
23,34

8,10

22,34
22,34
23,34
18,34
34
23,34

301-1%

D2
B2
A3
D6

ICH_A

E15
E14
B16
F14
A17
A15
B15

A20M#
SLP#
FERR#
IGNNE#
HINIT#
LINT0
LINT1
SMI#
STPCLK#
KBRST#
A20GATE

R225

B

C_BE#0
C_BE#1
C_BE#2
C_BE#3

CPU

IGNNE#
INIT#
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE

F13
E12
F15
B17

301-1%

18,22,23,34
18,22,23,34
18,22,23,34
18,22,23,34
18,22,23,34
18,22,23
8,12,13,14,18,21,22,23,24
22,23,34
18,22,23,34
18,22,23,34
18,21,22,23
23,34
23,34

AD29
AD30
AD31

B1
D4
C3
A4
B4
C5
C6
B5
E7

A20M#
CPUSLP#
FERR#

R226

C_BE#[3:0]
18,22,23

A6
B6
D7
B8
A7
A8
B7
C9
D8
C7

D1
D3
E4
C2
C1

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13’
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21

R239

C

G2
G4
F2
F3
F4
F5
E1
E2

40.2-1%

D

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

VCC1_8;G13,H14,K14,G15,L15,H16,J16
VCC3_3;C11,E13,N13,R13,M14,D16,T16
VCC3_3;E3,A5,E5,G5,N5,E6,P6,T7,C8,U10
GND;R2,G3,H8,J8,K8,H9,J9,K9,H10,J10,K10,G14,K15

AD[31:0]
18,22,23

HUBREF

C218
0.1UF

Place HUBREF circuit between MCH and ICH

A

A

HUBREF voltage = 0.9V +/- 2%

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
ICH
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
10OF 38

8

7

6

5

4

3

2

1

6

5

4

C246
1
+
2
1UF

2
1
+

1K
VBAT_RTC

3

C

VBAT_RC

R317
8.2K

R254
8.2K

1K

2
2.2UF

R250

R233

C247
1
+

8.2K

3,5,13,34
3,5,13,34
34

14
14

C249

R232
8.2K

R247

BAT1

10M
7
7
7

R249
Use CR2032 battery.

10M
Y4
XTAL

12PF

12PF

C250

17
15,17
15,17
11,15,17
15,17
17
11,20

2
1
32.768KHZ
C251

R212
R215

B

S tra p
No W D Reboot
Reboot on W D*
S tra p
S afe M ode
ICH s trap*

JP 26
IN
O UT
JP 5
IN
O UT

8.2K

8.2K

23

PCI_TEST

7
20
18,34
18,34

R98
0K

7

DRCG_CTRL

R162

12,14
12,14
12,14
12,14

0K
VCC3_3SBY

14

R238

CM O S
Norm al*
Clear

JP 20
1-2
2-3

8.2K
11,20

SPKR

12,14

VCC3_3
25
25
25
25

A

R90

JP26

SPKR_STRAP

25
25

2.7K

SMBDATA_CORE
SMBCLK_CORE
SMB_ALERT

J1

SMBDATA

J2
M1

SMBCLK
GPIO11/SMBALERT#

LPC_SMI#
LPC_PME#
INTRUDER#

E11

GPIO6

D11
J4

GPIO5
GPIO10/INTRUDER#

RTCRST#
VBIAS
RTCX1
RTCX2

H1

RTCRST#

H2
H3
H4

VBIAS
RTCX1

ICH_CLK66
ICH_14MHZ
ICH_48MHZ

A16
U6
U2

CLK66
CLK14
CLK48

AC_RST#
AC_SYNC
AC_BITCLK
AC_SDATAOUT
AC_SDATAIN0
AC_SDATAIN1
SPKR

T1
T3

AC_RST#
AC_SYNC
AC_BIT_CLK
AC_SDOUT
ACSDIN0
GPIO9/AC_SDIN1
SPKR

GPIO12
GPIO13
GPIO21
MULT0_GPIO
GPIO23_FPLED
ALERTCLK_SBY
ALERTDATA_SBY

N4
L2
B14
D13
D15

LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ#0
GPIO8
LFRAME#/FWH4

R6
U5
T5
T4

USBP1P
USBP1N
USBP0P
USBP0N
OC#1
OC#0

R1
P2
P1
N2
M4
M3

M5
L5

T6
N3
U4

GPIO12
GPIO13
GPIO21
GPIO22

R12
T12

PDA0
PDA1
PDA2

P12
M16
M15
L13

AC97

IDE

GPIO

LPC

USB

D

PDA[2:0]
24
SDA[2:0]
24

PDREQ
SDREQ
PDDACK#
SDDACK#
PDIOR#
SDIOR#
PDIOW#
SDIOW#
PIORDY
SIORDY

PDD13
PDD14
PDD15

P9
T10
P10

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

P15
R16
T17
U16
U15
R14
P13
T13
U14
T14
P14
T15
U17
R15
R17
P16

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

A

-C

24
24
24
24

SDA0
SDA1
SDA2

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

PDD0 R10
PDD1 N9
PDD2 R9
PDD3 U9
PDD4 R8
PDD5 U8
PDD6 R7
PDD7 U7
PDD8 P7
PDD9 N7
PDD10 T8
PDD11 P8
PDD12 T9

0.1UF

C234
1
+
2

ICH_B

LFRAME#/FWH4
USBP1+
USBP1USBP0+
USBP0OC1#
OC0#

PDA0

PDDREQ U11
SDDREQ P17
PDDACK# U12
SDDACK# M13
PDIOR# R11
SDIOR# N16
PDIOW# T11
SDIOW# N15
PIORDY N11
SIORDY N17

GPIO23
GPIO27/ALERT_CLK
GPIO28/ALERT_DATA
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ0#
GPIO8/LDRQ1#

PDCS#1
SDCS#1
PDCS#3
SDCS#3

SDA0
SDA1
SDA2

RTCX2

R3
T2
U1
P3
U3

N12
L14
U13
L16

PDA1
PDA2

SYSTEM

0.047UF

+

A

RTC_CLR
CR5

BAT17

R241

L4
K4

L3
F1

PDCS1#
SDCS1#
PDCS3#
SDCS3#

+

BAT17

2
3

THRM#
GPIO24/SLP_S3#
SLP_S5#
PWROK
PWRBTN#
RI#
RSMRESET#
GPIO25/SUSSTAT#
SUSCLK/GPIO26

C233

CR3

1

D14
K3
K2
J3
M2

VCC5REF

VCC3_3
JP20
RTC_RST_JP

THRM# 3,5
SLP_S3#
SLP_S5#
PWROK
PWRBTN#
ICH_RI#
RSMRST#
MULT1_GPIO
GPIO26_FPLED

VCCSUS1

VBAT_CR

8.2K

C15

R231
31,33
32
9,18,31,33
20
27
19,33
7,14
20

VCCSUS

1K

L1

VCCRTC

VCC3_3

R245

D

N1

G1

CR4

-C

VCC5

VCC5_REF
U13
ICH_096

BAT17

A

1
VCC3_3

VCC_RTC_JP
+

2

1UF

ICH

C-

3

VCC3_3SBY

1K

7
VCC3_3SBY

R230

8

24
24
24
24
24
24
24
24
24
24
PDD[15:0]

C

24

B
SDD[15:0]
24

A

R341

AC_SDOUT_STRAP
2.7K
JP5

AC_SDATAOUT

8

7

6

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
ICH
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
11OF 38

11,15,17

5

4

3

2

1

8

7

6

5

4

3

2

1

FWH
VCC3_3

D

C301

C298

C297

C308
0.1UF

VCC3_3

0.1UF

Do not tie Vpp to 12V. Vpp should be tied
to VCC3_3 for onboard programming.

0.1UF

VCC3_3

0.1UF

D

U16
C305

C300

0.1UF

0.1UF

1
FWH_IC 2
8.2K
3
4
5
6
R298
FGPI4 7
8.2K
8
FWHPCLK
9
10
VPP_R
11
PCIRST#
12
13
14
R300
15
FGPI3
8.2K
FGPI2
16
FGPI1
17
FGPI0
18
R296

C

7
R299
0K
8,10,13,14,18,21,22,23,24

R303
24
24

S66DETECT
P66DETECT

R305
R306

8.2K

0K

0K

19
20

15K

R307

15K

R304

For drive side detection, stuff R304,R307. No stuff R305,R306.
For host side detection, stuff R304,R305,R306,R307.

NC1
IC
NC3
NC4
NC5
NC6
FGPI4
NC8
CLK
VCC10
VPP
RST#
NC13
NC14
FGPI3
FGPI2
FGPI1
FGPI0
WP#
TBL#

FWH

GNDA
VCCA
FWH4
INIT#
RFU36
RFU35
RFU34
RFU33
RFU32
VCC31
GND30
GND29
FWH3
FWH2
FWH1
FWH0
ID0
ID1
ID2
ID3

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

LFRAME#/FWH4
HINIT#

11,14
4,6,10,34

C

LAD3/FWH3
LAD2/FWH2
LAD1/FWH1
LAD0/FWH0

11,14
11,14
11,14
11,14

VCC3_3

VCC3_3

R308

WPROT

4.7K

B

B

JP21

Top Block Lock
TBLK_LCK

4.7K

R310

FW H
OUT
IN

JP21
Locked
Unlocked*

A

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
FWH
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
12 OF 38

8

7

6

5

4

3

2

1

8

7

6

5

4

3

1

J17
RIMM

LDQA[8:0]

D

9

C

LCOL[4:0]
9

9
9
9
9
9
9
9
8,13

LROW2
LROW1
LROW0
LCOL4
LCOL3
LCOL2
LCOL1
LCOL0

B16
A18
B18
A20
B20
A22
B22
A24

LCLKFM
LCLKFM#
LCLKTM
LCLKTM#

B10 LCFM
B12 LCFM#
A14 LCTM
A12 LCTM#

LCMD
LSCK
LSIO

B34
A34
B36

RAMREF

LCMD
LSCK
SIO/SIN

A51 VREFA
B51 VREFB

3,5,11,13,34
SMBCLK_CORE
SMBDATA_CORE

A53
A55
A57
B56
A56

3,5,11,13,34

C228
0.1UF

LROW2
LROW1
LROW0
LCOL4
LCOL3
LCOL2
LCOL1
LCOL0

SCL
SDA
SWP
SVDDB
SVDDA

RCMD_A
B59
RSCK_A
A59
A36 MR1OUT 13

B59
A59
A36

RCMD
RSCK
SIO/SOUT

RDQA0
RDQA1
RDQA2
RDQA3
RDQA4
RDQA5
RDQA6
RDQA7
RDQA8
RDQB0
RDQB1
RDQB2
RDQB3
RDQB4
RDQB5
RDQB6
RDQB7
RDQB8

A83
B85
A85
B87
A87
B89
A89
B91
A91
B69
A67
B67
A65
B65
A63
B63
A61
B61

RDQA0_A
RDQA1_A
RDQA2_A
RDQA3_A
RDQA4_A
RDQA5_A
RDQA6_A
RDQA7_A
RDQA8_A
RDQB0_A
RDQB1_A
RDQB2_A
RDQB3_A
RDQB4_A
RDQB5_A
RDQB6_A
RDQB7_A
RDQB8_A

A83
B85
A85
B87
A87
B89
A89
B91
A91
B69
A67
B67
A65
B65
A63
B63
A61
B61

RDQA0
RDQA1
RDQA2
RDQA3
RDQA4
RDQA5
RDQA6
RDQA7
RDQA8
RDQB0
RDQB1
RDQB2
RDQB3
RDQB4
RDQB5
RDQB6
RDQB7
RDQB8

RROW0
RROW1
RROW2
RCOL0
RCOL1
RCOL2
RCOL3
RCOL4

B75
A75
B77
A69
B71
A71
B73
A73

RROW0_A
RROW1_A
RROW2_A
RCOL0_A
RCOL1_A
RCOL2_A
RCOL3_A
RCOL4_A

B75
A75
B77
A69
B71
A71
B73
A73

RROW0
RROW1
RROW2
RCOL0
RCOL1
RCOL2
RCOL3
RCOL4

RCFM
RCFM#
RCTM
RCTM#

B83
B81
A79
A81

RCFM_A
RCFMN_A
RCTM_A
RCTMN_A

B83
B81
A79
A81

RCFM
RCFM#
RCTM
RCTM#

SA0
SA1
SA2

B53
B55
B57

RSRV4/RESET

B38

VCC3_3

B53
B55
B57

B38

SA0
SA1
SA2

VCMOS1_8SBY;A35,A37,B35,B37
VCC2_5SBY;A41,A42,A54,A58,B41,B42,B54,B58
GND;A1,A3,A5,A7,A9,A11,A13,A15,A17,A29,A21,A23,A25,A27,A19,A31,A33,A39
GND;A52,A60,A62,A64,A66,A68,A70,A72,A74,A76,A78,A80,A82,A84,A86,A88,A90,A92
GND;B1,B3,B5,B7,B9,B11,B13,B15,B17,B29,B21,B23,B25,B27,B19,B31,B33,B39
GND;B52,B60,B62,B64,B66,B68,B70,B72,B74,B76,B78,B80,B82,B84,B86,B88,B90,B92
NC;A43,A44,A45,A46,A47,A48,A49,A50,B43,B44,B45,B46,B47,B48,B49,B50 RSV_SRIMM:
NC;A16,A77,B14,B79 RSV_EXP:
NC;A38,A40,B40 RSV_SPARE:

LROW[2:0]
9

RCMD
RSCK
SIO/SOUT

VCMOS1_8SBY;A35,A37,B35,B37
VCC2_5SBY;A41,A42,A54,A58,B41,B42,B54,B58
GND;A1,A3,A5,A7,A9,A11,A13,A15,A17,A29,A21,A23,A25,A27,A19,A31,A33,A39
GND;A52,A60,A62,A64,A66,A68,A70,A72,A74,A76,A78,A80,A82,A84,A86,A88,A90,A92
GND;B1,B3,B5,B7,B9,B11,B13,B15,B17,B29,B21,B23,B25,B27,B19,B31,B33,B39
GND;B52,B60,B62,B64,B66,B68,B70,B72,B74,B76,B78,B80,B82,B84,B86,B88,B90,B92
RSV_SRIMM: NC;A43,A44,A45,A46,A47,A48,A49,A50,B43,B44,B45,B46,B47,B48,B49,B50
RSV_EXP: NC;A16,A77,B14,B79
RSV_SPARE: NC;A38,A40,B40

9

A10
B8
A8
B6
A6
B4
A4
B2
A2
B24
A26
B26
A28
B28
A30
B30
A32
B32

TERM_DQA0
TERM_DQA1
TERM_DQA2
TERM_DQA3
TERM_DQA4
TERM_DQA5
TERM_DQA6
TERM_DQA7
TERM_DQA8
TERM_DQB0
TERM_DQB1
TERM_DQB2
TERM_DQB3
TERM_DQB4
TERM_DQB5
TERM_DQB6
TERM_DQB7
TERM_DQB8

LROW2
LROW1
LROW0
LCOL4
LCOL3
LCOL2
LCOL1
LCOL0

B16
A18
B18
A20
B20
A22
B22
A24

TERM_ROW0
TERM_ROW1
TERM_ROW2
TERM_COL0
TERM_COL1
TERM_COL2
TERM_COL3
TERM_COL4

35

D

TERM_DQB[8:0]
35

TERM_ROW[2:0]
35
TERM_COL[4:0]

R287

CTERM_RIMM

28-1%

LCMD
LSCK
SIO/SIN

B34
A34
B36

R286
28-1%

7

CLKTM#
TERM_CMD
TERM_SCK
MR1OUT
XREF=13

7
35
35

C291
0.1UF

VREFA A51
VREFB B51
A53

B

A55
A57
B56
A56

VCC3_3
C184
0.1UF

VCC3_3

PCIRST#
8,10,12,14,18,21,22,23,24

VCC3_3

3,5,11,13,34
3,5,11,13,34

SMBCLK_CORE
SMBDATA_CORE

R229
4.7K

RAMREF

C256

C169
SWP

0.1UF

0.1UF

C243
0.1UF

8,13

C236
0.1UF

R228
4.7K

Do not stuff R228

A

C

35

CLKFM
CLKFM#
CLKTM

LCFM B10
LCFM# B12
LCTM A14
LCTM# A12

SCL
SDA
SWP
SVDDB
SVDDA

RSRV4/RESET

TERM_DQA[8:0]

LDQA0
LDQA1
LDQA2
LDQA3
LDQA4
LDQA5
LDQA6
LDQA7
LDQA8
LDQB0
LDQB1
LDQB2
LDQB3
LDQB4
LDQB5
LDQB6
LDQB7
LDQB8

R152

As shown, RIMMs are 184-pin connectors.
J16
RIMM
LDQA0
A10 LDQA0
LDQA1
B8 LDQA1
LDQA2
A8 LDQA2
LDQA3
B6 LDQA3
LDQA4
A6 LDQA4
LDQA5
B4 LDQA5
LDQA6
A4 LDQA6
LDQA7
B2 LDQA7
LDQA8
A2 LDQA8
LDQB[8:0]
LDQB0
B24 LDQB0
LDQB1
A26 LDQB1
LDQB2
B26 LDQB2
LDQB3
A28 LDQB3
LDQB4
B28 LDQB4
LDQB5
A30 LDQB5
LDQB6
B30 LDQB6
LDQB7
A32 LDQB7
LDQB8
B32 LDQB8

10K

For MTH down solution, this sheet should be replaced by Appendix A (sheets 38-41).

RIMM Sockets

B

2

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
RIMM SOCKETS
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
13 OF 38

8

7

6

5

4

3

2

1

8

7

6

5

4
VCC5

3

2

1

VCC3_3

11,12,14
11,12,14
11,14
8,10,12,13,14,18,21,22,23,24
11
10,14,23,34

SIO_PCLK7

7,14
KBDAT

28

KBCLK
MDAT
MCLK

28
28
28

KBRST#
A20GATE

10,34
10,34

IRRX
IRTX

20
20

C

C320

C317

470PF

470PF

27
27
27
27
27
27
27
27

24
23
22
21
20
25
26
27
17
30
29

LFRAME#
LAD3
LAD2
LAD1
LAD0
LDRQ#
LRESET#
LPCPD#
PME#
SERIRQ
PCI_CLK

56
57
58
59
63
64

KDAT
KCLK
MDAT
MCLK
KBDRST
A20GATE

61
62

IRRX2/GP34
IRTX2/GP35

RXD0
TXD0
DSR#0
RTS#0
CTS#0
DTR#0
RI#0
DCD#0

84
85
86
87
88
89
90
91

RXD1
TXD1

95
96
97
98
99
100
92
94

RXD1
TXD1
DSR1#
RTS1#
CTS1#
DTR1#
RI1#
DCD1#

53
65
93

VCC5
66
67
75
74
73
72
71
70
69
68
77
78
79

INIT#
SLCTIN#
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
SLCT#
PE
BUSY
ACK#
ERROR#
ALF#
STROBE#

80
81
82
83

FAN2/GP32
FAN1/GP33

54
55

FDC_PP/DDRC/GP43

28

LPC I/F
PARALLEL PORT I/F

SIO
LPC47B27X
KYBD/MSE I/F

INFRARED I/F

PAR_INIT#

VCC3_3

26

SLIN#
PDR7
PDR6
PDR5
PDR4
PDR3
PDR2
PDR1
PDR0
SLCT
PE
BUSY
ACK#
ERR#
AFD#
STB#

D

26
26

PDR[7:0]

26
26
26
26
26

C349
1
+

LAD3/FWH3
LAD2/FWH2
LAD1/FWH1
LAD0/FWH0
LDRQ#0
PCIRST#
LPCPD#
LPC_PME#
SERIRQ

VCC1
VCC2
VCC3

LFRAME#/FWH4

C309

C348

C321

C313

0.1UF

0.1UF

0.1UF

0.1UF 0.1UF

Place next to VREF.

C323

2

R315

4.7K

11,12,14
11,12,14
11,12,14

8
7
6
5

RP5

4.7K

1
2
3
4

D

44

U17

VREF
VTR

VCC3_3

28 VCC5_KBMS_J

18

Super I/O

2.2UF

Place decoupling caps near each power pin.

26
26

PWM2

20

PWM1

C

20

SERIAL PORT 1

10,14,23,34

MULT1_GPIO
SERIRQ

2
4
6
8
10
12
14
16
18
20
22
24
26
28

28
28
28
28
28
28
28
28
28
28
28
28
28
28

A

2
1
3
5
8
9
10
11

RDATA#
DSKCHG#

12
13
14
15
16
4

DRVDEN1
DRVDEN0
MTR0#
DS0#
DIR#
STEP#
WDATA#
WGATE#
HDSEL#
INDEX#
TRK0#
WRTPRT#
RDATA#
DSKCHG#

SIO_14MHZ

6
19

CLKI32
CLOCKI

DIR#
STEP#
WDATA#
WGATE#
HDSEL#
INDEX#
TRK#0
WRTPRT#

FDC I/F

CLOCKS

7
31
60
76

7

DRVDEN#1
DRVDEN#0
MTR#0
DS#0

GP24/SYSOPT

45

J1BUTTON1
J1BUTTON2
J2BUTTON1
J2BUTTON2
JOY1X
JOY1Y
JOY2X
JOY2Y
KEYLOCK#

4.7K

32
33
34
35
36
37
38
39
41
42
43

4.7K

GP10/J1B1
GP11/J1B2
GP12/J2B1
GP13/J2B2
GP14/J1X
GP15/J1Y
GP16/J2X
GP17/J2Y
GP20/P17
GP21/P16
GP22/P12

LPC_SMI#
CPU_TACH2
CPU_TACH1
MIDI_IN
MIDI_OUT

R313

48
49
50
51
52
46
47

11

B

29
29
29
29
29
29
29
29
29
29
20

SYSOPT
Pulldown on SYSOPT for IO address of 0x02E
R312

7,11

1
3
5
7
9
11
13
15
17
19
21
23
25
27

AVSS

J20

11,12,14
LAD3/FWH3
11,12,14
LAD2/FWH2
11,12,14
LAD1/FWH1
11,12,14
LAD0/FWH0
11,12,14
LFRAME#/FWH4
8,10,12,13,14,18,21,22,23,24PCIRST#
7,14
SIO_PCLK7
11,14
LDRQ#0

GP60/LED1
GP61/LED2
GP27/IO_SMI#
GP30/FAN_TACH2
GP31/FAN_TACH1
GP25/MIDI_IN
GP26/MIDI_OUT

A

4.7K

40

B

SERIAL PORT 2

GND1
GND2
GND3
GND4

LPC header. For debug only.

DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

27
27
27
27
27
27

RXD2_IRRX
TXD2_IRTX
DSR2#
RTS2#
CTS2#
DTR2#
RI2#
DCD2#

R157

VCC3_3 VCC3_3
27
27

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
SUPER I/O
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
14 OF 38

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

AC’97 Audio
VCC3_3
VCC12
VR2
MC78M05CDT

1

C48

+

C62
0.1UF

1

2

C49

C21

AGND

AGND

C77

VCC3_3

L17

D

15,16

No stuff C358.
C358
0.1UF

0.1UF

10UF
2
C57

10UF
2
C83

+

1

GND 4

0.1UF

15,16

1 VIN

0.1UF

VCC5_AUDIO

3

+5V

0.1UF

VCC5_AUDIO

D

AGND

AGND

0.1UF
R67

AC97_SPKR_R
C76
0.1UF

46
45
48
47

17
11,17
11,17
11,17
11,17

VCC3_3

C84
10PF
No stuff C84
R29

CS1
CS0
CHAIN_CLK
EAPD

Series resistors are for test purposes only.
PRI_DWN_RST#_R
PRI_DWN_RST#
R31
AC_SDATAOUT_R 0K
AC_SDATAOUT
R77
AC_SDATAIN_R
AC_SDATAIN0
R116 0K
0K
AC_SYNC_R
AC_SYNC
R106
0K
AC_BITCLK
AC_BITCLK_R
R56
0K

100K
No stuff

R28

AC_XTAL_OUT

1
+
C9
10UF-TANT

C94

22PF

C95

2
24.576MHZ

22PF

C16

100K
No stuff

Y1
XTAL

0.1UF

1
+
C1
2
1UF-TANT

C17

C18

1
+
C7

16

16

AC_XTAL_IN

1

0.047UF

C19

AUD_VREFOUT

AC_VREF_C

270PF-NPO
2
1UF-TANT

2
3

28
27

34 CX3D_C
33 RX3D_C
31 FILT_R_C
32
30
29

270PF-NPO

EAPD

XTL_IN
XTL_OUT

CX3D
RX3D
FILT_R
FILT_L
AFLIT2
AFILT1
AFILT1_C
AFILT2_C
FILT_L_C

A

11
5
8
10
6

B
VREFOUT
VREF

16

AD1881

RESET#
SDATA_OUT
SDATA_IN
SYNC
BIT_CLK

A

2

16

C

NC43
NC44
NC40

B

43
44
40

17

AVSS1
AVDD1

17

PC_BEEP
LINE_IN_R
LINE_IN_L
MIC1
MIC2
CD_R
CD_L
CD_REF
VIDEO_R
VIDEO_L
AUX_L
AUX_R
PHONE
MONO_OUT
LINE_OUT_R
LINE_OUT_L
LNLVL_OUT_R
LNLVL_OUT_L

AVSS2
AVDD2

16
16
16

AC97_SPKR_C 12
24
23
21
22
CD_R
20
CD_L
18
CD_REF
19
17
C63
16
MONO_PHONE 2
1
+
14
1UF-TANT
15
MONO_PHONE_C
13
C12
2
1
MONO_OUT
MONO_OUT_C
37
+
36
1UF-TANT
35
LNLVL_OUT_R
41
LNLVL_OUT_L
39
LINE_IN_R
LINE_IN_L
MIC_IN

9 DVDD2
7 DVSS2

1 DVDD1
4 DVSS1

16
16
16

1UF-TANT C70
2
1
+

42
38

U2

26
25

C85

C

C20

1K

10K

0.1UF

AC97_SPKR

R66

20

AGND
AGND

8

7

6

5

4

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
AUDIO
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
15 OF 38

3

2

1

8

7

6

5

4

3

2

AC’97 Audio

Stereo HP/Spkr out

HP_OUTA

D

AGND

2

LINE_IN_R_C

+
1UF-TANT
C25
1
2
+
1UF-TANT

1

20K

J5
LINE_IN_R_FB LI25
LI24
LI23
LINE_IN_L_FB LI22
LI21
DB15_AUD_STK

2
L2

LINE_IN_L_C

1

2
L3

C26
1
2
+
10PF-NPO
C22
1
2
+
10PF-NPO
AGND

VCC5_AUDIO
HP_OUTB

8
7
6
5

C4

15
1

EAPD

15

AGND

+

R361

OUTA
VDD
INA
OUTB
BYPASS
INB
GND
SHUTDN

C14

LNLVL_L_C

1
2
3
4

2

C13
1
2
+
1UF-TANT

20K

U1
LM4880

LNLVL_R_R
AC_BYPASS

1

+
1UF-TANT

R171

LNLVL_R_C

+

2

C2

C6

1UF

LNLVL_OUT_L

15

1

2
LINE_IN_L

15

C23

AGND

20K

15

1

AGND

R362

LNLVL_OUT_R

15

Line_In Analog Input
LINE_IN_R

D

100PF

20K

AGND

C

2
L1

R360

AGND
AGND

HP_OUTB_C 1

100PF

C28
2
+
10PF-NPO

0.01UF

J5
HP_OUTA_FB HP30
HP29
HP28
HP_OUTB_FB HP27
HP26
DB15_AUD_STK

2
L4

AGND

C

0.1UF

1
L5

C8

2

1K

HP_OUTA_C 1

C11
1
2
+
10PF-NPO
C24
2
+
10PF-NPO

R9

MIC_IN_C

1

1
2
+
1UF-TANT
C34

MIC_IN_FB

C10
1
2
+
100UF
C3
1
2
+
100UF

1

C27

J5
M20
M19
M18
M17
M16
DB15_AUD_STK

MIC_IN_R

2.2K

MIC_IN

15

Microphone Input

R163

AUD_VREFOUT

15

1

AGND

LNLVL_L_R

AGND

AGND

B

B

CD Analog Input
R52

J4
CD_L_J
CD_REF_J

1
2
3
4

R27
CD_R_J

CD_L_C

2

CD_REF_C

2

CD_R_C

2

4.7K

4.7K
R167
4.7K

C59
+
1UF
C58
+
1UF
C50
+
1UF

1

CD_L

1

CD_REF

1

CD_R

15

15

15

A

AGND

8

4.7K

R25

4.7K

R30

4.7K

R51

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
AUDIO
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
16 OF 38

AGND AGND

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

AC’97 Audio/Modem Riser
D

D

VCC3_3SBY

VCC3_3 VCC5 VCC12 VCC12-

R68

VCC3_3SBY

J8
4.7K

U3 14
6
PRI_DWN_RST#

C

15

15

4 PRI_DWN_U
5

7
SN74LVC08A

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11

MONO_OUT

PRI_DWN#
3

1

JP2

2

B12
B13
B14
B15
B16
11,15
11

Audio Down
Enable*
Disable

B17
B18
B19
B20
B21
B22
B23

JP2
1-2
2-3

KEY
KEY
GND[3]
RESV[3]
RESV[4]
+3.3VD
GND[4]
AC97_SDATA_OUT
AC97_RESET#
AC97_SDATA_IN3
GND[5]
AC97_SDATA_IN2
GND[6]
AC97_MSTRCLK

AC’97_RISER
AMR_CONNECTOR

AUDIO_PWRDWN
MONO_PHONE
RESV[5]
RESV[6]
RESV[7]
GND[7]
+5VDUAL/5VSBY
USB_OC
GND[8]
USB+
USBKEY
KEY
GND[9]
S/P_DIF_IN
GND[10]
+3VDUAL/3VSBY
GND[11]
AC97_SYNC
GND[12]
AC97_SDATA_IN1
GND[13]
AC97_SDATA_IN0
GND[14]
AC97_BITCLK

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23

MONO_PHONE

15

VCC5

C
AC97_OC#
AC97_USB+
AC97_USB-

25
25
25

VCC3_3SBY

AC_SYNC
R113

AC_SDATAIN1_R

11,15

AC_SDATAIN1

11

0K
AC_SDATAIN0
AC_BITCLK

11,15

B

11,15

R108
10K
R125
10K

B

AC_SDATAOUT
AC_RST#

AUDIO_MUTE#
GND[0] (ISOLATED)
MONO_OUT/PC_BEEP
RESV[1]
RESV[2]
PRIMARY_DN#
-12V
GND[1]
+12V
GND[2]
+5VD

A

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
AUDIO/MODEM RISER
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST
REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
17 OF 38

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

VCC3_3SBY

PWROK
LAN_RSMRST#

9,11,31,33
19
2
25MHZ

Y2
XTAL

A

11,34
11,34

1

C101
22PF

8

B9
A9

ALERTCLK_SBY A10
ALERTDATA_SBY C9

C96
22PF

7

E12
G5
G6
H5
H6
H7
H8
J5
J6
J7
J8
J9
J10
J11
K4
K5
K6
K7
K8
K9
K10
K11
L4
L5
L9
L10
VCC[0]
VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]

LAN_X1

N11

X1

LAN_X2

P11

X2

C13
C14
E13
E14

TDP
TDN
RDP
RDN

SMBALRT#
CSTSCHG
PME#

B10
C5
A6

PCI_PME#

FLA0/PCIMODE#
FLA1/AUXPWR
FLA2
FLA3
FLA4
FLA5
FLA6
FLA7
FLA8/IOCHRDY
FLA9/MRST
FLA10/MRING#
FLA11/MINT
FLA12/MCNTSM#
FLA13/EEDI
FLA14/EEDO
FLA15/EESK
FLA16

J13
J12
K14
L14
L13
L12
M14
M13
N14
P13
N13
M12
M11
P10
N10
M10
P9

FLD0
FLD1
FLD2
FLD3
FLD4
FLD5
FLD6
FLD7

F14
F13
F12
G12
H14
H13
H12
J14

6

P7
N9
M8
M9
C8

TEST
TEXEC
TCK
TI
TO

A13
D13
D14
D12
B12

RBIAS10
RBIAS100
VREF

B14
B13
C12

D

19
19

19
19
19
19

VCC3_3SBY

R59

A3
A7
E1
K3
N6
P2

A11

VCCPL[0]
VCCPL[1]
VCCPL[2]
VCCPL[3]

SMBCLK
SMBD
VIO

TDP
TDN
RDP
RDN

EECS
FLCS#
FLOE#
FLWE#
CLKRUN#

ISOLATE#
ALTRST#

G2

A12
C11
B11

10,21,22,23

3.3K

AUXPWR

C

EEDI
EEDO
EESK

VCC3_3SBY

U24
93C46
3
4
2
1

FLD5
FLD6

EECS

8
VCC
EEDI
EEDO
NC2
EESK
NC1
EECS
GND
5

7
6

B

No stuff R57, R58
R58
3.3K
R57

CLKRUN#_LAN

3.3K
R363
62K
R14

TEST_LAN

3.3K

R16

RBIAS10
RBIAS100

549
R15
619

A
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]

8,10,12,13,14,21,22,23,24
7

FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
INTA#
PERR#
SERR#
IDSEL
REQ#
GNT#
RST#
CLK

LILED
ACTLED
XREF1=19
SPEEDLED

LILED
ACTLED
SPEEDLED

D4
D5
D6
D7
D8
D11
E4
E5
E6
E7
E8
E9
E10
E11
F4
F5
F6
F7
F8
F9
F10
F11
G7
G8
G9
G10
G11
H9
H10
H11
L6
L11

AD20

F2
F1
G3
H3
H1
J1
H2
J2
SERR#
A2
R75
AD20_RLAN A4
100 PREQ#3
C3
PGNT#3
J3
PCIRST#
C2
PCLK5
G1

VSSPP[0]
VSSPP[1]
VSSPP[2]
VSSPP[3]
VSSPP[4]
VSSPP[5]

VCC5SBY

C/BE0#
C/BE1#
C/BE2#
C/BE3#

VSSPT

10,22,23,34
10,18,22,23
10,34
10,34

M4
L3
F3
C4

FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
PIRQ#A
PERR#

10,22,23,34
10,22,23,34
10,22,23,34
10,22,23,34
10,22,23,34
10,22,23
10,21,22,23,34
10,22,23,34

B

C_BE#0
C_BE#1
C_BE#2
C_BE#3

B3
B7
E2
K2
M6
N1

10,22,23

82559

C10

C_BE#[3:0]

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

VSSPL[0]
VSSPL[1]
VSSPL[2]
VSSPL[3]

C

N7
M7
P6
P5
N5
M5
P4
N4
P3
N3
N2
M1
M2
M3
L1
L2
K1
E3
D1
D2
D3
C1
B1
B2
B4
A5
B5
B6
C6
C7
A8
B8

G14
K12
P8
N12

D

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

VCCPT

U5
AD[31:0]
10,22,23

VCCPP[0]
VCCPP[1]
VCCPP[2]
VCCPP[3]
VCCPP[4]
VCCPP[5]

G13
K13
N8
P12

LAN

5

4

3

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
LAN CONTROLLER
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
18 OF 38

2

1

8

7

6

5

4

3

2

1

LAN

0.1UF

RDN

0.1UF

RXC_J
75

R10

75

R8

75

R365

75

SPEED_J

R73
330
R78
330
R60
330
LI_J

ACT_J

330

18,19

LILED

18,19

ACTLED

18,19
16
ACTLED

0.1UF

C

18,19

11,33
18

RDC_J

C31

SPEEDLED

18

15

TXC_J

R6

LILED

13

RJ-4
RJ-5
RJ-7
RJ-8

2
1

RJ4_J

14

TDC
RDC

18

3
4
5
6

RJMAG

RJ-45

C79

TD+
TDRD+
RD-

TDC_J 11
8

C61

R364
49.9-1%

10
12
9
7

TXC
RXC

No stuff C61, C79.

RD_C

R62
49.9-1%

RJ_7_J

C

TDN
RDP

J2

SHLD1
SHLD2

18

No stuff JP1,JP3,JP4,R60,R73,R78.

JP1

R26
49.9-1%
R20
49.9-1%

17
18

18

JP3

TDP

JP4

Place termination resistors close to 82559.
18
TD_C

D

VCC3_3

ACT_CR

R61

LI_CR 330
R366

VCC3_3

D

For debug only. Hold LAN in reset.
J18
1
2
3

RSMRST#
LAN_RSMRST#

C78
0.1UF

XC_R

82559 LAN

Enable*
Disable

C5

B

No stuff C5.
C5 must be rated at 1500V.

470PF
No stuff C31.

J17
1-2
2-3

B

A

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
3.03
LAN
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST
REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
19 OF 38

8

7

6

5

4

3

2

1

6

5

4

VCC3_3SBY

1M

10K

10K

R344

470

14

7
SN74LVC07A
VCC3_3

IDE_ACTIVE

GND

VCC3_3
C354

C355

470PF
U19

14

R354

VCC
8

9

IDEACTS#

470PF

10K

C

VCC5

7
SN74LVC07A

GND
KEYLOCK#

14

SPKR_FP

JP25
AC97_SPKR

3

Speaker Circuit

15

2
PC_BEEP

R350

Onboa rd S pkr
E nable*
Dis able

JP 25
2-3
1-2

P_BEEP

B

1

3
2

2.2K

R352

SPKR_Q
C

Q15

E

INFRARED
VCC3_3
C316
POWER SW.

1
2
3

TACH2

POWER LED

PWM1

VCC12

VCC3_3
C327

SPEAKER

1
2
3

JP24

68

PWM1

SP1
1+
POS
2 NEG
SPKR_ONBOARD

C353

C

KEYLOCK

VCC5

R353

JP22

H.D. LED

68

0.1UF

SPKR

MMBT3904LT1

1
11

TACH2

VCC12

4.7K

PWRBTN_FP#

VCC
2

1

IDEACTP#

24

5%R358

4.7K

R345

14

HDLED_R

24

1
2
82 IRTX_R
3
R357 5%
4
5 KEY
6
7
8
9
10
11
12
13 KEY
14
15
16 KEY
17
18 KEY
R355
PLED_R
19
220
20 KEY
21
22
23
24 KEY
25
26
FNT_PNL_CONN

IRTX

R356

U19

D

J25
IRRX

14
No stuff.
For test only

VCC5

VCC3_3

2

R316

1UF

1

2

11

R257
C267

VCC5

1

4.7K

PWRBTN#

VCC5

R329

0K
SW1

1

0.1UF

R252

ICH has internal pullup and debounce on PWRBTN#

R359

100K

No stuff.
For test only

D

2

0.1UF

System

3

VCC3_3

C350
+
50V
C356
+
10UF
16V

7

0.1UF

8

14

PWM2

VCC12

VCC3_3SBY

B

B

VCC3_3

CR7

GPIO23_FPLED

14

11

VCC
4

3

1

4.7K

R326

PWM2
14
PWM outputs from SIO need power buffers for driving fan inputs.
VCC
6

2

LED_PU0

LED_PU1

GND

CR6

4.7K

R234

Onboard LED indicates the standby well is on
to prevent hot swapping memory.
For debug only.

A

GND

JP23

U14
5

GPIO26_FPLED11

7

7
SN74LVC07A

1
2
3

VCC3_3SBY

R246

U14

330

1

R253

330

2

VCC3_3SBY

VCC3_3SBY

14

R289

330

VCC3_3SBY

SBY_LED_CR

0.1UF

C322

SN74LVC07A

DUAL_COLOR

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
SYSTEM
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
20 OF 38

8

7

6

5

4

3

2

1

7

6

5

4

AGP Connector

2

1

VCC12

SBA[7:0]

VCC5

D
PIRQ#B

10,22,23,34

7

VCC3_3SBY

C

B

A

9 GAD[31:0]
9
GC/BE#[3:0]

7

J13

B1
B2
B3
USBAGP+ B4
25
B5
B6
B7
AGPCLK_CONN
GREQ# B8
9,34
B9
B10
ST0
B11
ST2
B12
RBF#
9,34
B13
B14
B15
SBA0
B16
B17
SBA2
SBSTB B18
9,34
B19
B20
SBA4
B21
SBA6
B22
B23
B24
B25
B26
GAD31
B27
GAD29
B28
B29
GAD27
B30
GAD25
B31
ADSTB1 B32
9,34
B33
GAD23
B34
B35
GAD21
B36
GAD19
B37
B38
GAD17
B39
GC/BE#2
B40
GIRDY# B41
9,34
B42
B43
B44
B45
B46
GDEVSEL#
9,34
B47
B48
GPERR#
34
B49
B50
GSERR#
34
B51
GC/BE#1
B52
B53
GAD14
B54
GAD12
B55
B56
GAD10
B57
GAD8
B58
B59
ADSTB0
9,34
B60
GAD7
B61
B62
GAD5
B63
GAD3
B64
B65
GAD1
MCH_AGPREF B66
8

6

AGP_OC#

5

OVRCNT#

AGP4XU_20
12V

5V_A

TYPEDET#

5V_B

RESV_A

USB+

USB-

GND_K
INTB#

GND_A
INTA#

CLK

RST#

REQ#

GNT#

VCC3_3_F

VCC3_3_A

ST0

ST1

ST2

RESV_B

RBF#
GND_L
RESV_H
SBA0
VCC3_3_G
SBA2

PIPE#
GND_B
WBF#
SBA1
VCC3_3_B
SBA3

SB_STB

SB_STB#

GND_M

GND_C

SBA4

SBA5

SBA6

SBA7

RESV

RESV_C

GND_N

GND_D

3_3VAUX1

RESV_D

VCC3_3_H

VCC3_3_C

AD31

AD30

AD29

AD28

VCC3_3_I
AD27
AD25
GND_O
AD_STB1
AD23
VDDQ_F
AD21
AD19
GND_P
AD17
C/BE2#

VCC3_3_D
AD26
AD24
GND_E
AD_STB1#
C/BE3#
VDDQ_A
AD22
AD20
GND_F
AD18
AD16

VDDQ_G

VDDQ_B

IRDY#

FRAME#

3_3VAUX2

RESV_E

GND_Q

GND_G

RESV_K
VCC3_3_J

RESV_F
VCC3_3_E

DEVSEL#

TRDY#

VDDQ_H

STOP#

PERR#

PME#

GND_R

GND_H

SERR#

PAR

C/BE1#

AD15

VDDQ_I

VDDQ_C

AD14
AD12
GND_S
AD10
AD8
VDDQ_J
AD_STB0
AD7
GND_T
AD5
AD3
VDDQ_K
AD1
VREF_CG

AD13
AD11
GND_I
AD9
C/BE0#
VDDQ_D
AD_STB0#
AD6
GND_J
AD4
AD2
VDDQ_E
AD0
VREF_GC

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66

4

TYPEDET#

21,31

USBAGP-

D

25
PIRQ#A

PCIRST#
GGNT#

10,18,22,23,34

8,10,12,13,14,18,22,23,24
9,34
ST1

PIPE#

9,34

WBF#

9,34

SBA1
SBA3

SBSTB#

9,34

VDDQ

SBA5
SBA7

C
AGPREF circuitry should be placed close to MCH.
GAD30
GAD28

3

Q8
3
9,34

GC/BE#3

301-1%

CON_AGPREF_Q

GAD26
GAD24
ADSTB#1

R193

ST[2:0]

21,31

TYPEDET#

1

1

2

R208

9
9

25

8

3
VDDQ

VCC3_3

2N7002LT1

8

200-1%

2

GAD22
GAD20
GAD18
GAD16
GFRAME#

GTRDY#
GSTOP#
PCI_PME#
GPAR

B

9,34

9,34
9,34
10,18,22,23
9,34
GAD15
GAD13
GAD11
CONN_AGPREF
GAD9
GC/BE#0

ADSTB#0

8

9,34

A

GAD6
GAD4
GAD2
GAD0

3

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
AGP CONNECTOR
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-30-1999_10:10
21 OF 38

2

1

8

7

6

5

4

3

2

1

VCC5 VCC5
VCC3_3

10,21,22,23,34
10,22,23,34

PIRQ#B
PIRQ#D
PRSNT#11

22

PRSNT#12

22

PREQ#0

10,34

AD31
AD29

C

AD27
AD25
C_BE#3
AD23

AD17
C_BE#2

10,18,22,23,34
10,22,23,34
10,18,22,23,34

B

IRDY#
DEVSEL#

A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27

PERR#
SERR#

C_BE#1
AD14
AD12
AD10

PIRQ#A
PIRQ#C

A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

10,18,21,22,23,34
10,22,23,34

10,22,23,34
10,18,21,22,23,34
22

VCC3_3SBY

PCIRST#

PIRQ#C
PIRQ#A
PRSNT#21
PRSNT#22

22

8,10,12,13,14,18,21,22,23,24

PCLK2

7

PGNT#0

10,34

PCI_PME#

10,34

10,18,21,22,23
AD30

PREQ#1

AD31
AD29

AD28
AD26

AD27
AD25

AD24
R_AD16

C_BE#3
AD23

22
AD22
AD20

A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39

AD21
AD19

AD18
AD16
FRAME#
TRDY#
STOP#

AD17
C_BE#2

10,18,22,23,34

IRDY#

10,18,22,23,34

DEVSEL#

10,18,22,23,34

SDONEP1
SBOP1
PAR

VCC12

PLOCK#
PERR#

22
22

SERR#

10,18,22,23
AD15

C_BE#1
AD14

AD13
AD11

AD12
AD10

AD9

B1
B2

A1
A2

B3
B4
B5
B6
B7
B8
B9
B10
B11

A3
A4
A5

B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25

AD5
AD3

B55
B56
B57
B58
B59
B60
B61
B62

AD1

A

22

PU1_ACK64#

A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27

B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36

22

10,21,22,23,34
10,22,23,34

22
22
22

SDONEP1
SDONEP2
SBOP1
SBOP2

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

AD8
AD7

C_BE#0
AD6
AD4

AD5
AD3

AD2
AD0
PU1_REQ64#

22

AD1
PU2_ACK64#

22

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

D

8
7
6
5
5.6K

C117 0.1UF

PCIRST#

8,10,12,13,14,18,21,22,23,24

PGNT#1

PRSNT#11

22

C123 0.1UF

10,34

PRSNT#12

22

PCI_PME#
AD30

10,18,21,22,23

C113 0.1UF
PRSNT#21

22
AD28
AD26

C

C122 0.1UF
PRSNT#22

22

AD24
R_AD17

22
AD22
AD20
AD18
AD16
VCC5

A34
A35
A36
A37
A38
A39

FRAME#

A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

1
2
3
4

VCC3_3SBY

TRDY#

22

PU1_ACK64#

STOP#

22

PU1_REQ64#

SDONEP2
SBOP2

22

PU2_ACK64#

22

PU2_REQ64#

R178
2.7K
R179
2.7K
R176

B

2.7K
R177

PAR

2.7K
AD15
AD13
AD11
AD9

10,18,22,23

AD16

R120

R_AD16

100
AD17

10,18,22,23

C_BE#0

R119
100

R_AD17

22

22

AD6
AD4
AD2
AD0

A
PU2_REQ64#

22

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
PCI CONNECTORS 1 AND 2
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
22 OF 38

10,18,23 C_BE#[3:0]

10,18,23 AD[31:0]

8

VCC5

RP12

PIRQ#B
PIRQ#D

A28
A29
A30
A31
A32
A33

B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

22,23

key

B52
B53
B54

PTRST#
PTMS
22,23
PTDI
22,23

A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16

R79

PCI Slot 1
J11
PCI3_CON

key

AD8
AD7

VCC5

R72

PTCK

22,23

R74

PTMS
22,23
PTDI
22,23

B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

PLOCK#

10,18,22,23,34

PTRST#
22,23

A3
A4
A5

B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36

AD21
AD19

10,18,22,23,34

A1
A2

B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25

PCLK1

7

B1
B2

5.6K

PCI Slot 0
J12
PCI3_CON

PTCK

22,23

VCC3_3
VCC12- VCC5

5.6K

VCC3_3
VCC5 VCC12

5.6K
R367

VCC3_3

VCC12- VCC5

D

For pullups, see 4.3.3 of PCI 2.1 Specification

5.6K

PCI Connectors
0 and 1

7

6

5

4

3

2

1

8

7

PCI Connectors
2 and 3

6

VCC3_3

B3
B4
B5
B6
PIRQ#A
PIRQ#C
PRSNT#31

10,18,21,22,23,34
10,22,23,34
23

PRSNT#32

23

7
10,34

PCLK3
PREQ#2

AD31
AD29

C

AD27
AD25

AD21
AD19
AD17
C_BE#2

10,18,22,23,34
10,22,23,34
10,18,22,23,34

B

10,18,22,23,34

IRDY#
DEVSEL#

SERR#

C_BE#1
AD14
AD12
AD10

PCIRST#

A40
A41
A42
A43
A44
A45

R255
0K

8,10,12,13,14,18,21,22,23,24
7

PGNT#2

PCLK4

10,34

PREQ#5

10,34

PCI_PME#
AD30

10,18,21,22,23

AD31
AD29

AD28
AD26

AD27
AD25

AD24
C_BE#3
AD23
AD22
AD20

AD21
AD19

AD18
AD16
FRAME#
TRDY#
STOP#

10,18,22,23,34

IRDY#

10,18,22,23,34

DEVSEL#

10,18,22,23,34

SDONEP3
SBOP3
PAR
AD15

AD17
C_BE#2

PLOCK#
PERR#

23
23

SERR#

10,18,22,23

C_BE#1
AD14

AD13
AD11

A46
A47
A48
A49

AD12
AD10

AD9

B1
B2

A6
A7
A8
A9
A10
A11 GNT#A_R
A12
A13
A14
A15
A16

B7
B8
B9
B10
B11
B12
B13
SERIRQ_RB14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25

A17
A18
A19
A20
A21
A22
A23

AD5
AD3

B57
B58
B59
B60
B61
B62

AD1

A
23

PU3_ACK64#

PTRST#

PIRQ#C
PIRQ#A

R99
0K

A52
A53

AD6
AD4

A54
A55
A56
A57
A58
A59
A60
A61
A62

AD8
AD7

C_BE#0

10,22,23,34
10,18,21,22,23,34

GNT#A for debug only
GNT#A 10,34

AD5
AD3

AD2
AD0
PU3_REQ64#

23

AD1

23

PU4_ACK64#

1
2
3
4

8
7
6
5

C112 0.1UF
23

PRSNT#31
C121 0.1UF

PCI_PME#
AD30

10,18,21,22,23

23

PRSNT#32
C116 0.1UF

AD28
AD26

23

B34
B35
B36

A34
A35
A36
A37
A38
A39

FRAME#

A40
A41
A42
A43
A44
A45

SDONEP4
SBOP4

PRSNT#41

C
C126 0.1UF

23

AD24
R_AD22

PRSNT#42

23
AD22
AD20
AD18
AD16
VCC5

TRDY#
23

STOP#

23
23
23

23

PAR

23

AD15

PU3_ACK64#
PU3_REQ64#
PU4_ACK64#
PU4_REQ64#

R174
2.7K
R175
2.7K
R172

B

2.7K
R173
2.7K

AD13
AD11

A46
A47
A48
A49

AD9
10,18,22,23
C_BE#0
10,18,22,23

A54
A55

AD6
AD4

B57
B58
B59

A56
A57
A58
A59

AD2
AD0

B60
B61
B62

A60
A61
A62

AD23

R118

R_AD23

100
AD22

R117

R_AD22

23

100

A
PU4_REQ64#

23

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
3.03
PCI CONNECTORS 3 AND 4
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST
REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
23 OF 38

AD[31:0]

8

SDONEP3
SDONEP4
SBOP3
SBOP4

5.6K

10,18,22 C_BE#[3:0]

10,18,22

RP13
23
23
23
23

VCC3_3SBY

R107
0K
R110
REQ#A 10,34
PCIRST#
8,10,12,13,14,18,21,22,23,24 0K
No Stuff R110.
PGNT#5
REQ#A for debug only
10,34

A26
A27
A28
A29
A30
A31
A32
A33

A52
A53

7

6

5

4

D

VAUX_JP

B26
B27
B28
B29
B30
B31
B32
B33

B52
B53
B54
B55
B56

VCC5

22,23
22,23

A24
A25

B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

22,23

PTMS
PTDI

key

B52
B53
B54
B55
B56

J9 must be furthest from the processor.
A1
A2
A3
A4
A5

key

AD8
AD7

1

VCC5 VCC12

PCI Slot 3
J9
PCI3_CON

B3
B4
B5
B6

SERIRQ for debug only
10,14,34 SERIRQ

A26
A27
A28
A29
A30
A31
A32
A33

B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

PLOCK#
PERR#

PTCK

PIRQ#D
10,22,23,34
PIRQ#B
10,21,22,23,34
PRSNT#41
23
PCI_TEST for debug only11
PCI_TEST
VCC3_3SBY
PRSNT#42
23

A24
A25

A34
A35
A36
A37
A38
A39

22,23

22,23
22,23

PIRQ#D
10,22,23,34
PIRQ#B
10,21,22,23,34

A17
A18
A19
A20
A21
A22
A23

B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36

C_BE#3
AD23

10,18,22,23,34

A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16

B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25

PTMS
PTDI

22,23

2

VCC3_3

VCC12- VCC5

PTRST#

A1
A2
A3
A4
A5

3

VCC3_3

VCC5 VCC12

PCI Slot 2
J10
PCI3_CON
B1
B2

PTCK

22,23

4

VCC3_3

VCC12- VCC5

D

5

3

2

1

8

7

6

5

4

3

2

1

IDE Connectors
Primary IDE

Secondary IDE

PDD[15:0]

SDD[15:0]

11

J21

PIORDY
11
10,34

5.6K

R335

11

11
11

PDIOW#
PDIOR#

PDDACK#
IRQ14
PDA1
PDA0

C

11
20

PDCS#1
IDEACTP#

1K

R321
11

SDIOW#
SDIOR#

11
11

SIORDY
11
10,34

SDDACK#
IRQ15
SDA1
SDA0

11

11
20
C329

PDA2

SDCS#1
IDEACTS#

D

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

IDE_JS

S66DETECT12
SDCS#3
11

SDA2

0.047UF

PDA[2:0]

C
C318

SDA[2:0]

0.047UF
R319

10K

11
R334

11

SDREQ

IDE_JP

P66DETECT12

PCIRST#_RS1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

33

SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0

VCC5

11

PDCS#3

R318

PCIRST_BUF#

24

PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

10K

PDREQ

11

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

5.6K

1K

R336

PCIRST#_RP1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

33

R320

PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0

VCC5

470

R333

PCIRST_BUF#

R337

24

470

J22

D

R322

11

For drive side detection, stuff C329,C318.
For host side detection, no stuff C329,C318.
P66DETECT and S66DETECT can be connected to a GPI for BIOS cable detection.

VCC3_3

B

B

R351

VCC3_3

U19
8,10,12,13,14,18,21,22,23

14

PCIRST#

VCC
6

5

7
SN74LVC07A

8.2K

PCIRST_BUF#

24

GND

A

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
IDE CONNECTORS
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
24 OF 38

8

7

6

5

4

3

2

1

8

7

4

3

2

1

VCC3_3

R83

D

5

330K

USB Connectors

6

D

L11
USBPWR1_F

2

1

AC97_OC#

17

C99

C44

68UF-TANT

0.1UF

0K

R82

Do Not
Stuff
C98, C99 must have low ESR.

VCC3_3

USBV0

VCC5
11

R242

11

R378

USBD0P

0K

USBG0

VCC3_3

Do Not
Stuff

0K

0K

R48

47PF

15K

C241

47PF

15K

C239

R50

7
6
3
4

R47

OUT1
OUT2
EN#1
EN#2

R49

IN
OC#1
OC#2
GND

J3
1
2
3
4
5
6
7
8

1
C38
AC97_USB+
AC97_USB-

17
17

L7

2
8
5
1

OC#0_RC

R87
C109

USBD0P_R

15-1%

U7
TPS2042
10K

USBD0N

0K

15-1%
USBP0P

R377

0.1UF

C
OC#0

USBD0N_R

C102

4.7K

R86

11

R240

USBP0N

470PF

2

4.7K

R91

0.1UF

10K

OC#1_RC
2

1

C39

USBPWR2_F

C41

47PF

L10

R97
C120

47PF

OC#1

C40

C42

11

C

USB_STK
VCC0
DATA0DATA0+
GND0
VCC1
DATA1DATA1+
GND1

Place caps close to connector.
C39-C42 for test and debug only.

VCC3_3
C43

68UF-TANT

B

0.1UF

0K

R88

330K

R368

Do Not
Stuff

47PF

C98

47PF

0.1UF

B

USBV1
AGP_OC#
USBP1N

USBP1N_R

15

R44

USBP1P_R

15

0K

R42

0K

R41

47PF

15K

C245

47PF

USBD1P

0K

USBG1

1

Do Not
Stuff

C37

L6

C244

USBD1N

0K

R244

USBP1P

15K

11

R46

R43

11

R243

R45

21

470PF

A

USBAGP+

2

A

21

USBAGP-

21

15 ohm resistors and 47pf caps should be within 1" of ICH
TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
USB CONNECTORS
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
25 OF 38

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Parallel Port
VCC5

CR1
1

D

3

VCC5_DB25_CR

D

MMBD914LT1
5 6 7 8

2.2K

RP4

2.2K

RP3

2.2K

4 3 2 1

4 3 2 1

5 6 7 8

5 6 7 8

RP2

RP1

2.2K

2.2K

R40

5 6 7 8

4 3 2 1

4 3 2 1

J6
DB25_DB9_STK
14
14
14

C

14

SLCT

P13
P25
P12
P24
P11
P23
P10
P22
P9
P21
P8
P20
P7
P19
P6
P18
P5
P17
P4
P16
P3
P15
P2
P14
P1

PE
BUSY
ACK#

PDR[7:0]
RP19

14

PDR7
PDR6
PDR5
PDR4

1
2
3
4

PDR3
PDR2

1
2
3
4

8
7
6
5

PDR7_R
PDR6_R
PDR5_R
PDR4_R

8
7
6
5

PDR3_R
PDR2_R
SLIN#_R
PAR_INIT#_R

RP18 33

14
14
14

SLIN#
PAR_INIT#

33
ERR#

C

B

B
RP20

8
180PF
CP5

1

6
180PF
CP5
7
180PF
CP5

2

3

8
180PF
CP4
5
180PF
4
CP5

CP4
7
180PF
CP4

2

1

6
180PF
3

8
180PF
CP3
5
180PF
CP4

4

1

6
180PF
CP3
7
180PF
2
CP3

3
CP3

6
180PF
2

7
180PF

CP2

4
5
180PF

180PF

3

1

CP2

33

CP2

PDR1_R
PDR0_R
AFD#_R
STB#_R

8
180PF
4
5
180PF

AFD#
STB#

1
2
3
4

C81

14
14

8
7
6
5

CP2

PDR1
PDR0

A

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
PARALLEL PORT
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
26 OF 38

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Serial Ports
VCC5

VCC12

D

U4
1
2
3
4
5
6
7
8
9
10

J6
DB25_DB9_STK
DCD
DSR
RXD
RTS
TXD
CTS
DTR
RI
GND

A1
A6
A2
A7
A3
A8
A4
A9
A5

DCD0_C
DSR0_C
RXD0_C
RTS0_C
TXD0_C
CTS0_C
DTR0_C
RI0_C

2
CP8

4
CP8

8
100PF

6
100PF

6
100PF

CR2
BAT54C
3
1

RI_CR

ICH_RI#

8
100PF

5
100PF
3
CP1
7
100PF
1
CP1
5
100PF
3
CP8
7
100PF
1
CP8

4
CP1

VCC12-

R369
10K

C
11

D

COM1

GD75232
VCC12
VCC
RY0
RA0
RY1
RA1
RY2
RA2
DA0
DY0
DA1
DY1
RY3
RA3
DA2
DY2
RY4
RA4
GND
VCC-12

2
CP1

14
14
14
14
14
14
14
14

VCC3_3SBY

20
19
18
17
16
15
14
13
12
11

DCD#0
RXD0
DSR#0
DTR#0
TXD0
CTS#0
RTS#0
RI#0

C

3

R70
47K

2
Q1

VCC5

1

VCC12

RI_Q

COM2
J7
1
3
5
7
9

DCD1_C
RXD1_C
DSR1_C
DTR1_C
TXD1_C
CTS1_C
RTS1_C
RI1_C

2
4
6
8
10

B

3
CP6

7
100PF

8
100PF

COM2 is a 2x5 pin header for a cabled port.

1
CP6

VCC12-

7
100PF

1
2
3
4
5
6
7
8
9
10

2
CP6

GD75232
VCC12
VCC
RY0
RA0
RY1
RA1
RY2
RA2
DA0
DY0
DA1
DY1
RY3
RA3
DA2
DY2
RY4
RA4
GND
VCC-12

1
CP7

20
19
18
17
16
15
14
13
12
11

5
100PF
2
CP7
6
100PF
6
100PF

B

DCD#1
RXD1
DSR#1
DTR#1
TXD1
CTS#1
RTS#1
RI#1

14
14
14
14
14
14
14
14

8
100PF

1UF

C92

5
100PF

R69
47K

U6

4
CP6

1

3
CP7

2
2

4
CP7

2N7002LT1

3

A

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
SERIAL PORTS
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
27 OF 38

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Keyboard/Mouse/Floppy
VCC5

D

D
RP17
1
2
3
4

VCC5

8
7
6
5

Floppy Connector

F1

1

VCC5_KBMS_F

2

1.0A

2

VCC5_KBMS_J 14

R328

1

L15

J23

J1
1
L16

14

C

KBCLK

1

1
2
3
4
5
6

KBDAT_FB

2

GND_KBMS_C
2

KBCLK_FB

2

MDAT_FB

L12
14

MDAT

1
L14

14

MCLK

1

MCLK_FB

2
L13
C45

C33

C32

C46

14
14
14
14

17
16
15
14
13

C47

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34

DRVDEN#0
DRVDEN#1
INDEX#
MTR#0
DS#0
DIR#
STEP#
WDATA#
WGATE#
TRK#0
WRTPRT#
RDATA#
HDSEL#
DSKCHG#

C

L8

0.1UF

100PF

100PF

100PF

100PF

2

14
14
14
14
14
14
14
14
14

GND_KBMS_FB

7
8
9
10
11
12

14

PS/2 Kybd

KBDAT

PS/2 Mse

14

1K

1K

1

L9

2

B

1

B

A

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
KEYBOARD/MOUSE/FLOPPY
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
28 OF 38

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Game Port

D

D

VCC5

VCC5

VCC5

VCC5

VCC5

VCC5

14
14
14
14

C

14

J1BUTTON1
J2BUTTON1
JOY1X
JOY2X

1K

1K

R33

R32

1K

R36

1K

R37

4.7K

R35

4.7K

R39

VCC5

R21
R22

JOY1X_R
JOY2X_R

2.2K 5%

2.2K 5%
R34

MIDI_OUT

MIDI_OUT_R

47
14
14
14
14
14

JOY2Y_R

R23

JOY2Y
JOY1Y
J2BUTTON2
J1BUTTON2
MIDI_IN

R24

2.2K

JOY1Y_R

5%

2.2K 5%
R38

MIDI_IN_R

47

J5
DB15_AUD_STK
31
1
9
2
10
3
11
4
12
5
13
6
14
7
15
8
32

C

C69
0.01UF 25V
10%
C68
1
1

470PF
C67
0.01UF 25V
10%

50V

1
C54

2 47PF

C53
470PF

50V

C52

2 47PF
50V

B

1
C51
2 47PF

+

+

C55
2 47PF

+

C56

+

25V
0.01UF 10%

B

50V

C66
0.01UF 25V
10%

Tie game port capacitors together and to SIO AVSS. Tie to system ground at only a single point.

A

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
3.03
GAME PORT
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST
REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
29 OF 38

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2
VCC3_3

VCC12

VRM

1

VCC5

R71

5.6K

220

R332

5.1-5%

VCC5

D

R53

VRM requirements are based on VRM8.4 spec .

D

VRM_PWRGD

PVCC_R

33

C97

+
1UF-X7R

L19

1UH

1

2

DO3316P-102
Place caps next to output FETs.
C82,C87,C107,C111 must support >6A of RMS current.

1

1

1

+
1200UF
C107

+
1200UF
C82

1

C118, C119 must be next to FETs.

5 6 7 8

5 6 7 8

30
30
30

VID1_0R
VID1_2R
VID1_4R

A

B1

V5_IN4

B2

V5_IN5

B3
B4

V12_IN0

A5

V12_IN2

RSV

B5

A6

ISHARE

OUT_EN

B6

A7

VID0

VID1

B7

A8

VID2

A9

VID4

A10

V_OUT0

A11

GND0

A12

V_OUT1

A13

GND1

A14

V_OUT2

A15

GND2

A16

V_OUT3

A17

GND3

A18

V_OUT4

A19

GND4

A20

V_OUT5

VID3
PWR_GOOD

B10
B11

GND6

B12

V_OUT7

B13

GND7

B14

V_OUT8

B15

GND8

B16

V_OUT9

B17

GND9

B18

V_OUT10

B19

GND10

B20

C71

C118
C119

B

1

C366

2

+
2200UF

2

C103

C93

+
2200UF

SENSE
6

GND

SGND

C100

1

1

+
2200UF

2

5
C75

1000PF

2

2

4 3 2 1

4 3 2 1

1

1

2

Sanyo 4SP2200M

VRM1_PWRGD 33

B9

GND5

1.0UH-20A
ETQP6F0R8L

VID1_1R 30
VID1_3R 30

B8

V_OUT6

C

5 6 7 8

5 6 7 8

220

V5_IN3

V12_IN1

V5_IN2

R370

V5_IN1

A4

10K

V5_IN0

A3

R371

A1
A2

C74

J14
VRM8_4

VCCVID

L18

20

+
2200UF

VCC3_3

B

2

IFB_Q

R65

0.01UF

VCC5 VCC12 VCCVID1
VCC3_3

8.2K

VRM_COMP_R

VCC5

R55

150PF

VRM_COMP

C73
VCCVID1 VCC12

PVCC

VCC

JP9

0.1UF
No Stuff C106

JP7

C86

JP10

1

4 3 2 1

4 3 2 1

Q5
SI4410DY
D1
S1
D2
S2
D3
S3
D4
G1

JP8

VRM_FAULT
VRM_G1
VRM_IFB
VRM_G2

VRM_SS

JP6

Default JP6-JP10 OUT.
Remove RP21, R398 for VID override.

7
13
12
20
8
1
11

Q4
SI4410DY
D1
S1
D2
S2
D3
S3
D4
G1

LTC1753

VID Override Jumpers

IMAX
PWRGD
FAULT#
G1
IFB
G2
VFB

VRM_VFB

R398

SS

0K

VID4

3

OUTEN
VID0
VID1
VID2
VID3
VID4

4

0K

19
18
17
16
15
14

COMP

OUTEN
VID0_R
VID1_R
VID2_R
VID3_R
VID4_R

8
7
6
5

9

RP21

1
2
3
4

VID0
VID1
VID2
VID3

10

VID[4:0]

0.1UF

3

VRM_IMAX

Q2
SI4410DY
D1
S1
D2
S2
D3
S3
D4
G1

C

Q3
SI4410DY
D1
S1
D2
S2
D3
S3
D4
G1

VR3

+
1UF-X7R

R54

2

2.7K

1

+
1UF-X7R

2

+
0.01UF

2

2

C72

2

+
1200UF

C87

0.1UF

+
10UF

C90

C140

R80

10K

2

+
1200UF
C111

VRM_VCC5

1

5

VID1[4:0]

VID1[0]
VID1[1]
VID1[2]
VID1[3]

RP24

1
2
3
4

8
7
6
5

VID1_0R
VID1_1R
VID1_2R
VID1_3R
VID1_4R

0K

30
30
30
30
30

0K

VID1[4]
R104

JP16

JP27

JP29

JP28

JP30

A

VID Override Jumpers
Default JP16, JP27-JP30 OUT.
Remove RP24, R104 for VID override.
TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
VRM
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
30 OF 38

8

7

6

5

4

3

2

1

7

6

5

4

3

Voltage Regulators

1

AGP VDDQ VOLTAGE REGULATOR

VCC 5V DUAL VOLTAGE SWITCHER

VCC5SBY

The VCC5DUAL plane should not drive any logic components requiring 5V.
It should be used only for further regulation of lower voltage power planes
because the true voltage of VCC5DUAL will not remain constant
Rdson of the FET is not negligible for large currents

VCC3_3

VCC5
VCC12

VCC12

D

+

C173

VDDQ

C336
1
+
1500UF

2

VOUT 2

R158
R379

TYPEDET#

10K

B
1
TYPEDET_R#

3
2

1

2
+
100UF

C124

2
+
1UF-X7R

2
+
100UF

1

1
C104

C142

GND 1

1

1
+

+

1

1%

1
+

2.2K

C

Q7

21

3 VIN

B

VDDQ_FB

E

1K

R383

VR4
LT1585A-1_5

7.5K-1%

1UF-X7R
C242 2

3

VDDQ_COMP_R
1

22UF

1

+

C168
47UF

C

R137

MMBT3904LT1

B

VTT 1.5 VOLTAGE REGULATOR

MMBT3904LT1

R382

1K

C

Q18
VTT1_5

2

10PF

+

+

C174

1UF

2

C164
2

VCC3_3

2

VDDQ_COMP

1

E

VCC1_8

+

2

VD_G3

1K

3
3

1

2
1UF-X7R
C225 2
1UF-X7R
C211 2
1UF-X7R
C179 2

3

1

Q6

C200

VD_G2

B

8
7
R135
VDDQ_G2 1
6 VDDQ_G
5.1-5%
5

R141

7 GND

1K

R340

VD_G1
GND
SN74LVC07A

C

Q13

VCC
2

IPOS
INEG
GATE
COMP

R146

1

SHDN
VIN
GND
FB

301

1
2
3
4

1K

U14

R381

U18
74LS132 14VCC
4
6
5

MMBT3904LT1

SLP_S3#
PWROK

7

11,33
9,11,18,33

14

C

R331

VCC3_3

220UF
+
2

C160

IRL2203NS

VR6
LT1575
1

VCC3_3SBY

1

1.21K-1%

SN74LVC07A has 5V input and output tolerance.
VCC5SBY

D1 8
D1A 7
D2 6
D2A 5

2

Q12
SI4562DY
1 S1
2 G1
3 S2
4 G2

VCC5DUAL_R

2

VCC5SBY

C352
1
+
1500UF

2

C193

1

1K

47UF

47UF

C324

47UF
R330

1

VCC5DUAL
C347

2

D

2

+
10UF

8

E
VCC1_8

Route VR6 GND to VDDQ output caps and then via to ground.

B

VCC2_5SBY
BAT17

A
+

C-

VCC2_5

CR11
VCC5DUAL

VCC2_5 VOLTAGE REGULATOR
VCC 1.8 VOLTAGE REGULATOR

VCC3_3SBY

VCC3_3SBY VOLTAGE REGULATOR

VCC5

VCC3_3

100-1%

R134

100-1%

R133

301-1%
131-1%

2
+
100UF

C91

2
+
1UF-X7R

C161

2
+
1UF-X7R

C35

R311

VOUT 1
SENSE 2

1

4 SHDN#

TAB 6
GND3 3

1

2
+
330UF-T510

C15

1

2
+
100UF

2
+
1UF-X7R

C268

2
+
100UF

C319

C159

1

1

R309

1

VCC2_5_ADJ

2
+
100UF

ADJ 1

3 VIN

1

VCC1_8_ADJ

ADJ 1

VOUT 2

C167

3 VIN

VR1
LT1529-3_3
5 VIN

1

C372
1
2
+
100UF
C368
1
2
+
100UF
C311
2
+
100UF

VOUT 2

A

VR5
LT1587ADJ

1

VR8
LT1587ADJ

A

Place C311 at regulator.
Place C108, C333 at RIMMs
TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
VOLTAGE REGULATORS
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
31 OF 38

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Voltage Regulators
VCC5DUAL

D

D

C315 1UF-X7R
+
1
2
C314 100UF
+
1
2

VCC 2.5 Standby Voltage Regulator
VCC2_5SBY_TG
VCC2_5SBY_SW

VCC2_5SBY

100PF

C326

+
2

+

C325

1

11K

R302

1
2
R294

VCC2_5SBY_BG

100-1%

R301

+

AVX 330uF
TPS x2

10K

A

100-1%

C-

R297

0.1UF

CR10

MBRS140T3

C312

Q11
SI4966DY
8 D1
7 D2
1 S1
2 G1

CMDSH-3

1
+
0.1UF

1 4.7UF
+

2

C306

330PF

SBY_ITH_R
10K

-C

C

C304

330UF

R295

+

A

0.01

330UF

100PF

Do not stuff C304.
R325

VCC2_5SBY_INTVCC
V_BOOST

C299 1000PF

C292

L23

10UH
CDRH125

100PF

VIN 13
TG 16
SW 14
INTVCC 12
BOOST 15
BG 11
PGND 10

CR9

C293

SENSE+ 8

C296

SENSE- 7

C294

SFB
COSC
RUN/SS
ITH
SGND
VOSENSE
EXTVCC

2
C307

C295
68PF

MMBD914LT1

4
1
2
3
5
6
9

VCC2_5SBY_COSC
VCC2_5SBY_RUN
VCC2_5SBY_ITH

CR8
1

0.1UF

C

3

SLP_S5#

VCC2_5SBY_L

11

D3 6
D4 5
S2 3
G2 4

VR7
LT1435

VCC2_5SBY_SENSE+
VCC2_5SBY_SENSEVCC2_5SBY_VOSENSE

VCMOS Generator For Rambus

Do not stuff C292.

VCC2_5SBY

B

R259

VCMOS1_8SBY

C263
0.1UF

100-1%

R258

35.7-1%

B

A

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
VOLTAGE REGULATORS
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
32 OF 38

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Power Connector
ITP Reset circuit. For debug only.

VCC3_3

U15 14

1

VCC5SBY

U20 14VCC
11,31 SLP_S3#
5
6
GND
SN74LVC06A7

C

4.7K

R347

VCC3_3SBY

VCC5M

11
12
13
14
15
16
17
18
19
20

SLP_S3

SN74LVC06A has 5V output tolerance.

U15 14
POK_U1

3

74LVC14A7

4

POK_U2 1
2

VCC12

J24

VCC5

2

74LVC14A7

3_3V11
-12V
GND13
PS_0N
GND15
GND16
GND17
-5V
5V19
5V20

3_3V1
3_3V2
GND3
5V4
ATX
GND5
5V6
GND7
PW_OK
5VSB
12V

1
2
3
4
5
6
7
8
9
10

DBRESET#
330 ohm pullup to VCC3_3 located on CPU sheet.

4

14

U3
3 POK_U3

7
SN74LVC08A

VCC2_5

VCC3_3SBY

SN74LVC06A has 5V input tolerance.
VCC5SBY

220 ohm pullup to VCC3_3 is located on VRM sheet.
VCC3_3SBY

R342

ATX_PWOK

U20 14VCC
1
2
GND
SN74LVC06A7

U18
74LS132 14VCC
9
8
10

ATX_PWOK_R

0K
No stuff R342 when ITP is used.

VCC3_3SBY

C

330

ATX Connector

R96

VCC12-

D

VCC3_3SBY

0K

VCC5SBY

VCC3_3SBY

R339

74LVC14A has 5V input tolerance.
VCC3_3SBY

D

PWRGOOD
4,6

VCC3_3SBY
PWROK_INV

7 GND

6

SN74LVC08A

VCC3_3SBY

VCC3_3SBY

7

U20 14VCC
3
4
U22
1 14
2

B

9
10

3

7
74LVC32

VCC5SBY

9

8

74LVC14A7

U9
8

VCC3_3SBY

VCC3_3SBY

30 VRM1_PWRGD
U23 14

SLOTOCC1#

14

1
2

SN74LVC08A

14

U26
3

PWROK 9,11,18,31

GND
SN74LVC06A7

B

7
SN74LVC08A

VCC3_3SBY

6

4.7K

5

74LVC14A7

U9
3

R251

VCC3_3SBY

7

22K

U15 14

5

RSMRST_U

6

VCC3_3SBY

U15 14
RSMRST

74LVC14A7

9

8

RSMRST#

1M

SLOTOCC0#

14

R348

4

1
2

R349

VCC3_3SBY
30 VRM_PWRGD

U23 14

No stuff.
For test only

11,19

74LVC14A7

Reset Button
RSTBTN_SW

A

R343

1M

R288

1UF

VCC3_3SBY

No stuff.
For test only
U23 14

3

22

SW2

VCC3_3SBY

220K

R372

C266

C335

74LVC14A7
C328

0.01UF

10UF

4

U23 14
RS_SCH

1

2

74LVC14A7

A

Resume Reset circuitry
using a 22 msec delay
and Schmitt trigger logic.

JP12
TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
POWER CONNECTOR
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
33 OF 38

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

PCI/AGP Pullups/Pulldowns
VCC5

PCI
D

10,22,23
10,22,23

AGP

PIRQ#C
PIRQ#D

8
7
6
5

FRAME#
IRDY#
TRDY#
DEVSEL#

8
7
6
5

RP6

1
2
3
4

9,21
9,21

2.7K
10,18,22,23
10,18,22,23
10,18,22,23
10,18,22,23

RP10

21
21

1
2
3
4

PROCESSOR

RP11

8
7
6
5

STOP#
PLOCK#
PERR#
SERR#

4,6,10
4,6,10

10,22

C

10,22
10,23
10,18
10
10,23

R112

4,6,10

2.7K

4,6,10

2.7K

R115

R216

2.7K

2.7K

R213

R109

2.7K

PREQ#2
PREQ#3
PREQ#4
PREQ#5

4,6,10

R111

PREQ#0
PREQ#1

FLUSH#

4,6

2.7K

STPCLK#
SMI#
FERR#

8
7
6
5

PGNT#1
PGNT#0
PGNT#3
PGNT#2

150

1K

R85

R374

1K

1K

R123

10,23

B

10,23
10,23
10,18,21,22,23
10,21,22,23

10,24
10,24

4,6,10
4,6,10
4,6,10
4,6,10,12

1
2
3
4

PGNT#5

R256

8.2K

8.2K

R114

R105

8.2K

8.2K

R81

R89

8.2K

REQ#A
GNT#A
PIRQ#A
PIRQ#B

IRQ15

8
7
6
5

8
7
6
5

RP9

1
2
3
4

8.2K
GREQ#
GGNT#
PIPE#
WBF#

9,21
9,21
9,21

R126

A20M#

RP14

1
2
3
4

RP8

C
8
7
6
5

8.2K

1K
LINT0
LINT1
IGNNE#
HINIT#

8
7
6
5

RP7

9,21

1
2
3
4

9,21
9,21

1K

9,21
VCC2_5

9,21

R198

ADSTB0
ADSTB1

8.2K

R132
8.2K

R385

ST0
ST1

8.2K

R384
8.2K

R394

ST2

8.2K

R214

PGNT#4

IRQ14

SBSTB#
SBSTB

9,21
9,21

8.2K
10

RBF#

9,21

VCC2_5

4,6,10

D
1
2
3
4

8.2K

1K

2.7K

RP16

R124

R84

9,21

VCC3_3

10,22
10,22
10,18
10,23

150

PICD1

1
2
3
4

GSTOP#
GPAR

9,21
9,21

R128

PICD0

GFRAME#
GTRDY#

RP15

8.2K

9,21
9,21

1
2
3
4

8
7
6
5

VCC2_5

2.7K
10,18,22,23
10,22,23
10,18,22,23
10,18,22,23

GIRDY#
GDEVSEL#
GPERR#
GSERR#

VDDQ

8.2K

R393

TESTHI1

6

100K
R127

TESTHI

4

9,21

100K

4,6,10

9,21

ADSTB#0
ADSTB#1

B

R207
8.2K

R136
8.2K

R373

SLP#

1K

VCC5

R338
8.2K

R323

VCC3_3

8.2K
3,5,11,13
3,5,11,13

SMBCLK_CORE
SMBDATA_CORE

R235
4.7K

R237
4.7K

A

VCC3_3
VCC3_3SBY

A
11
11,18
11,18

8

R236

SMB_ALERT

10,14

4.7K
ALERTCLK_SBY
ALERTDATA_SBY

R13
4.7K

10,14
R12

10,14,23

KBRST#
A20GATE
SERIRQ

6

8.2K

R327

R314

8.2K
TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
PCI/AGP PULLUPS/PULLDOWNS
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:46
34 OF 38

8.2K

4.7K

7

R324

5

4

3

2

1

8

7

6

5

4

3

2

1

Rambus Termination

D

D

VCC1_8

C280

TERM_DQB3
TERM_DQB4
TERM_DQB5
TERM_DQB6
TERM_DQB7
TERM_DQB8
TERM_ROW0
TERM_ROW1

TERM_ROW[2:0]
13

TERM_ROW2
TERM_COL0
TERM_COL1
TERM_COL2

TERM_COL[4:0]
13

TERM_COL3
TERM_COL4

B

0.1UF

C283

R284
R268
R267
R266

28
28
28
28

0.1UF

C275

R265
R264
R263
R262

28
28
28
28

0.1UF

C276

R261
R260
R275
R274

28
28
28
28

0.1UF

C271

R276
R269
R271
R270

28
28
28
28

0.1UF

C277

R273
R272

28
28

C282
0.1UF

C273
0.1UF

C274

C

TERM_CMD
TERM_SCK

13
13

0.1UF

90.9-1% R291

13

0.1UF
VCC1_8

R280
R283
R282
R285

28
28
28
28

C278

C279
0.1UF

39.2-1%

C

C281

R290

TERM_DQA8
TERM_DQB0
TERM_DQB1
TERM_DQB2

TERM_DQB[8:0]

0.1UF

90.9-1% R293

TERM_DQA4
TERM_DQA5
TERM_DQA6
TERM_DQA7

R277
R279
R278
R281

28
28
28
28

39.2-1%

TERM_DQA0
TERM_DQA1
TERM_DQA2
TERM_DQA3

R292

TERM_DQA[8:0]
13

C269
0.1UF

0.1UF

B

NOTE :
Use one 0.1uF cap
per two RSL signals.

A

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
RAMBUS TERMINATION
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
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11-29-1999_14:46
35 OF 38

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Decoupling
ICH Decoupling

VCC2_5SBY

VDDQ

0.01UF

0.1UF

0.1UF

C272
C197
C144

0.01UF

C143

0.01UF

C288

C226

C284

C264

C289

C235

C303

100UF

Un-used Gates
VCC3_3SBY

VCC3_3SBY

9
10

U15 14

U3
8

14

11

VCC3_3

10

74LVC14A7
U19

VCC
4
14

Place these caps on solder side

3

12
13

13

U3
11

14

12

SN74LVC07A

7
SN74LVC08A

U19

VCC
10

11

7

VCC3_3SBY

VCC5SBY

9

U18
74LS132 14VCC
1
3
2

GND

7 GND

SN74LVC07A
U20 14VCC
9
8
GND
SN74LVC06A7

U19

SN74LVC07A

11

7
SN74LVC07A

GND

GND

U20 14VCC
11
10
GND
SN74LVC06A7

U18
74LS132 14VCC
12
11
13

VCC
10
14

U14

A

VCC
12

13

7
SN74LVC07A

GND

7

VCC
8
14

U14

B

GND

74LVC14A7

VCC3_3SBY

Place VDDQ capacitors within
70 mils of outer balls of MCH.

0.1UF

Place a VCMOS1_8SBY 0.1uF cap at each RIMM.

U15 14

0.01UF

0.1UF

100UF

C

7
SN74LVC08A

0.01UF

100UF

100UF

14

C221
C270

0.01UF

100UF

0.1UF

7

B

D

VCMOS1_8SBY

100UF

Place 100uF caps, 0.1 ohm ESR, among RIMM connectors.

VDDQ
0.01UF

C210

4.7UF

0.01UF

100UF

C285

C30
C29
C60
C105
C88
C290

C253
C254 C248

4.7UF

100UF

14

For chipset decoupling, use 0.1UF and
0.01UF decoupling capacitor at each
corner of the device. If there is room,
add 0.01UF capacitors in the middle
of each quad.

0.1UF

0.01UF

0.01UF

C165

0.01UF

0.1UF

Place these caps on solder side

0.01UF

0.01UF

0.1UF

0.1UF

0.1UF

C224

0.1UF

0.1UF

C230

C229

0.1UF

0.1UF

C252

C222
C227

0.1UF

C255

C156 C166

0.01UF

C202

C213

0.1UF

C162

C

0.1UF

0.1UF

C258

C157
C212

0.1UF

C201

0.1UF

VCC2_5SBY

VCC3_3SBY
0.1UF

C231

VCC3_3
VCC1_8

C219

VCC1_8

C232

D

RIMM Decoupling

82559 Decoupling.

C302

MCH Decoupling

A
U20 14VCC
13
12
GND
SN74LVC06A7

7 GND

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
DECOUPLING
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:44
36 OF 38

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Bulk Decoupling
VCC2_5 Decoupling

C136
C135

0.1UF

C134

0.1UF

C131

0.1UF

C371
1
2
+
22UF

0.01UF

0.01UF

0.1UF

0.01UF

0.1UF

0.01UF

VCC120.1UF

0.1UF

C130

+
22UF

2

C132 C133

C369

C129

VCC12

1

C146

0.1UF

+
22UF

2

C145

0.1UF

C370

0.1UF

0.1UF

C138

0.1UF

0.1UF

D

VTT1_5
0.1UF

C137

0.1UF

0.1UF

C148

0.1UF

0.1UF

1

C147

0.1UF

0.1UF

0.1UF

C141

0.1UF

0.1UF

Termination Decoupling

VCC5

C139

0.1UF

C176

0.1UF

C175

0.1UF

0.1UF

C172

0.1UF

Bulk Power Decoupling
VCC3_3

C163

C310
C259
C240
C238

0.1UF

C177

C216

C337

0.1UF

C195

C338

0.1UF

C334

0.1UF

C188

C339

0.1UF

C333

0.1UF

C181

C340

0.1UF

C332

0.1UF

C178

C341

0.1UF

C331

VCC2_5

C330

C

VCC3_3 Decoupling
VCC3_3

C154

VCC3_3 Decoupling
VCC3_3

D

C

C367
2
1
+
22UF

Place caps at VTT pins on Slot 1 connector.

Core Voltage Decoupling
VCC3_3SBY
VCCVID1

10UF

C351

10UF

10UF

C357

10UF

10UF

C363

10UF

C153

C365
C346

10UF

B
0.1UF

C152

C364
C342

10UF

10UF

C343

10UF

10UF

C344

10UF

10UF

C345

C64

C115

10UF

C114

C125

10UF

C108

C127

10UF

10UF

C106

C128

10UF

10UF

C89

C65

10UF

0.1UF

C151

VCCVID1

B

0.1UF

C150

VCCVID

0.1UF

C149

VCCVID

0.1UF

A

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
BULK DECOUPLING
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:44
37 OF 38

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Revision History

D

D
Pg 8

Modified MCH_AGPREF circuit, changed 432 ohm to 1K ohm and 62 ohm to 80.6 ohm.
Changed value of capacitor C194 from 0.1uF to 0.01uF.

Pg 10

Modified HUBREF circuit, deleted R222, R223 & C217, changed C218 from 470pF to 0.1uF.

Pg 13

Modified RIMM connectors to eliminate 3.3V, added 0.1uF decoup caps to SVDDA & SVDDB on each RIMM.

Pg 35

Modified CMD and SCK termination values. Removed 470pF capacitors, Changed 93 ohm to 90.9 ohm,
and changed 39 ohm to 39.2 ohm resistors.

Pg 36

Deleted 3.3V decoupling for RIMM connectors. Added solder side decoup for MCH.
Changed VDDQ cap values from 0.1uF to 0.01uF.

C

C

B

B

A

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV:
REVISION HISTORY
3.03
DRAWN BY:
PROJECT:
PCD PLATFORM DESIGN
R
1900 PRAIRIE CITY ROAD
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
11-29-1999_14:44
38 OF 38

8

7

6

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2

1

Intel around the world
United States and Canada
Intel Corporation
Robert Noyce Building
2200 Mission College Boulevard
P.O. Box 58119
Santa Clara, CA 95052-8119
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Phone: (800) 628-8686
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Phone:
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Phone: (852) 2844 4555
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Phone: (81) 298 47 8522
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Phone: (55) 11 5505 2296
For more information
To learn more about Intel Corporation, visit our site
on the World Wide Web at www.intel.com

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