Cypress Semiconductor 2006 Bluetooth Module User Manual

Cypress Semiconductor Bluetooth Module

User Manual

Document Number: 002-15631 Rev.PRELIMINARY Page 2 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11More InformationCypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you toquickly and effectively integrate the module into your design. nOverview: EZ-BLE Module Portfolio, Module RoadmapnEZ-BLE PRoC Product OverviewnPRoC BLE Silicon DatasheetnApplication notes: Cypress offers a number of BLE application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with EZ-BLE modules are:pAN96841 - Getting Started with EZ-BLE ModulepAN94020 - Getting Started with PRoC BLEpAN97060 - PSoC® 4 BLE and PRoC™ BLE - Over-The-Air (OTA) Device Firmware Upgrade (DFU) GuidepAN91162 - Creating a BLE Custom ProfilepAN91184 - PSoC 4 BLE - Designing BLE ApplicationspAN92584 - Designing for Low Power and Estimating Battery Life for BLE ApplicationspAN85951 - PSoC® 4 CapSense® Design GuidepAN95089 - PSoC® 4/PRoC™ BLE Crystal Oscillator Selec-tion and Tuning TechniquespAN91445 - Antenna Design and RF Layout GuidelinesnKnowledge Base ArticlespKBA97095 - EZ-BLE™ Module PlacementnTechnical Reference Manual (TRM): pPRoC® BLE Technical Reference ManualnDevelopment Kits:pCYBLE-212006-EVAL, CYBLE-212006-01 Evaluation BoardpCYBLE-202007-EVAL, CYBLE-202007-01 Evaluation BoardpCYBLE-202013-EVAL, CYBLE-202013-11 Evaluation BoardpCY8CKIT-042-BLE, Bluetooth® Low Energy (BLE) Pioneer KitpCY8CKIT-002, PSoC® MiniProg3 Program and Debug KitnTest and Debug Tools:pCYSmart, Bluetooth® LE Test and Debug Tool (Windows)pCYSmart Mobile, Bluetooth® LE Test and Debug Tool (Android/iOS Mobile App)PSoC® Creator™ Integrated Design Environment (IDE) PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling anddebugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, PRoC BLE and EZ-BLE module systems with no code size limitations. PSoCperipherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified,production-ready PSoC Components™. PSoC Components are analog and digital “virtual chips,” represented by an icon that users can drag-and-drop into a design andconfigure to suit a broad array of application requirements.Bluetooth Low Energy ComponentThe Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.1 compliant BLE protocol stack and provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS) hardware via the stack. Technical SupportnFrequently Asked Questions (FAQs): Learn more about our BLE ECO System.nForum: See if your question is already answered by fellow developers on the PSoC 4 BLE and PRoC BLE forums.nVisit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.
Document Number: 002-15631 Rev.PRELIMINARY Page 3 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11ContentsOverview............................................................................ 4Module Description...................................................... 4Pad Connection Interface ................................................ 6Recommended Host PCB Layout ................................... 7Power Supply Connections and Recommended External Components.................................................................... 10Connection Options................................................... 10External Component Recommendation .................... 10Critical Components List ........................................... 13Antenna Design......................................................... 13Qualified Antenna for CYBLE-202007-01 and CY .........BLE-202013-11 ................................................................ 13Power Amplifier (PA) and Low Noise Amplifier (LNA) 13Electrical Specification .................................................. 14GPIO ......................................................................... 16XRES......................................................................... 17Digital Peripherals ..................................................... 20Serial Communication ............................................... 22Memory ..................................................................... 23System Resources .................................................... 23Environmental Specifications ....................................... 29Environmental Compliance ....................................... 29RF Certification.......................................................... 29Safety Certification .................................................... 29Environmental Conditions ......................................... 29ESD and EMI Protection ........................................... 29Regulatory Information .................................................. 30FCC........................................................................... 30Industry Canada (IC) Certification ............................. 31European R&TTE Declaration of Conformity ............ 31MIC Japan................................................................. 32KC Korea................................................................... 32Packaging........................................................................ 33Ordering Information...................................................... 35Part Numbering Convention...................................... 35Acronyms........................................................................ 36Document Conventions ................................................. 36Units of Measure ....................................................... 36Document History Page ................................................. 37Sales, Solutions, and Legal Information ...................... 38Worldwide Sales and Design Support....................... 38Products .................................................................... 38PSoC® Solutions ...................................................... 38Cypress Developer Community................................. 38Technical Support ..................................................... 38
Document Number: 002-15631 Rev.PRELIMINARY Page 4 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11OverviewModule DescriptionThe CYBLE-2X20XX-X1 module is a complete module designed to be soldered to the applications main board. Module Dimensions and DrawingCypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLEmodule functionality. Such selections will still guarantee that all height restrictions of the component area are maintained. Designsshould be held within the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm).Table 1. Module Design DimensionsSee Figure 1 on page 5 for the mechanical reference drawing for CYBLE-2X20XX-X1.Dimension Item SpecificationModule dimensions Length (X) 15.00 ± 0.15 mmWidth (Y) 23.00 ± 0.15 mmAntenna location dimensions Length (X) 15.00 ± 0.15 mmWidth (Y) 4.65 ± 0.15 mmPCB thickness Height (H) 0.80 ± 0.10 mmShield height Height (H) 1.20 ± 0.10 mmMaximum component height Height (H)1.20 mm typical (shield) - CYBLE-212006-011.25 mm typical (connector) - CYBLE-202007-010.75mm typical (crystal) - CYBLE-202013-11Total module thickness (bottom of module to highest component) Height (H)2.00 mm typical - CYBLE-212006-012.05 mm typical - CYBLE-202007-011.55 mm typical - CYBLE-202013-11
Document Number: 002-15631 Rev.PRELIMINARY Page 5 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Figure 1. Module Mechanical DrawingTop View (View from Top)Bottom View (Seen from Bottom)Side ViewNote1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Figure 3, Figure 4, Figure 5, and Figure 6 and Ta ble 3.
Document Number: 002-15631 Rev.PRELIMINARY Page 6 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Pad Connection InterfaceAs shown in the bottom view of Figure 1 on page 5, the CYBLE-2X20XX-X1 connects to the host board via solder pads on the backsideof the module. Tab le 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-2X20XX-X1 module. Figure 2. Solder Pad Dimensions (Seen from Bottom)To maximize RF performance, the host layout should follow these recommendations:1. The ideal placement of the Cypress BLE module is in a corner of the host board with the trace antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Please refer to AN96841 for module placement best practices.2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional keep out area, where no grounding or signal trace are contained. The keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 3 (dimensions are in mm). Figure 3. Recommended Host PCB Keep Out Area Around the CYBLE-2X20XX-X1 AntennaTable 2. Solder Pad Connection DescriptionName Connections Connection Type Pad Length Dimension Pad Width Dimension Pad PitchSP 30 Solder Pads 1.02 mm 0.71 mm 1.27 mmHost PCB Keep Out Area Around Trace Antenna
Document Number: 002-15631 Rev.PRELIMINARY Page 7 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Recommended Host PCB LayoutFigure 4, Figure 5, Figure 6, and Table 3 provide details that can be used for the recommended host PCB layout pattern for theCYBLE-212006-01. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the padon either side) shown in Figure 6 is the minimum recommended host pad length. The host PCB layout pattern can be completed usingeither Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern. Figure 4. Host Layout Pattern for CYBLE-2X20XX-X1 Figure 5. Module Pad Location from OriginTop View (On Host PCB)Top View (On Host PCB)
Document Number: 002-15631 Rev.PRELIMINARY Page 8 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Table 3 provides the center location for each solder pad on the CYBLE-2X20XX-X1. All dimensions reference the to the center of thesolder pad. Refer to Figure 6 for the location of each module solder pad. Table 3. Module Solder Pad Location Figure 6. Solder Pad Reference LocationSolder Pad(Center of Pad)Location (X,Y) from Orign (mm)Dimension from Orign (mils)1 (0.38, 10.54) (14.96, 414.96)2 (0.38, 11.81) (14.96, 464.96)3 (0.38, 13.08) (14.96, 514.96)4 (0.38, 14.35) (14.96, 564.96)5 (0.38, 15.62) (14.96, 614.96)6 (0.38, 16.89) (14.96, 664.96)7 (0.38, 18.16) (14.96, 714.96)8 (0.38, 19.43) (14.96, 764.96)9 (0.38, 20.70) (14.96, 814.96)10 (0.38, 21.97) (14.96, 864.96)11 (2.32, 22.62) (91.34, 890.55)12 (3.59, 22.62) (141.34, 890.55)13 (4.86, 22.62) (191.34, 890.55)14 (6.13, 22.62) (241.34, 890.55)15 (7.40, 22.62) (291.34, 890.55)16 (8.67, 22.62) (341.34, 890.55)17 (9.94, 22.62) (391.34,8 90.55)18 (11.21, 22.62) (441.34, 890.55)19 (12.48, 22.62) (491.34, 890.55)20 (13.75, 22.62) (541.34, 890.5521 (14.62, 20.70) (575.59, 814.96)22 (14.62, 19.43) (575.59, 764.96)23 (14.62, 18.16) (575.59, 714.96)24 (14.62, 16.89) (575.59, 664.96)25 (14.62, 15.62) (575.59, 614.96)26 (14.62, 14.35) (575.59, 564.96)27 (14.62, 13.08) (575.59, 514.96)28 (14.62, 11.81) (575.59, 464.96)29 See Figure 2 See Figure 230 See Figure 2 See Figure 2
Document Number: 002-15631 Rev.PRELIMINARY Page 9 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Table 4 details the solder pad connection definitions and available functions for each connection pad. Ta ble 4 lists the solder pads onCYBLE-2X20XX-X1, the BLE device port-pin, and denotes whether the function shown is available for each solder pad. Eachconnection is configurable for a single option shown with a 3.Table 4. Solder Pad Connection DefinitionsSolder Pad NumberDevice Port Pin UART SPI I2CTCPWM[2] Cap-SenseWCO OutECO Out LCD SWD GPIO1 GND Ground Connection2 XRES External Reset Hardware Connection Input3P4.0[3] 3(SCB1_RTS) 3(SCB1_MOSI) 3(TCPWM0_P) 3(CMOD)334P3.73(SCB1_CTS) 3(TCPWM3_N) 3(Sensor) 33 35P3.63(SCB1_RTS) 3(TCPWM3_P) 3(Sensor) 336P3.53(SCB1_TX) 3(SCB1_SCL) 3(TCPWM2_N) 3(Sensor) 337P3.43(SCB1_RX) 3(SCB1_SDA) 3(TCPWM2_P) 3(Sensor) 338 VREF Reference Voltage Input (Optional)9P2.6 3(Sensor) 3310 P2.4 3(Sensor) 3311 P2.3 3(Sensor) 33 312 P2.2 3(SCB0_SS3) 3(Sensor) 3313 P2.0 3(SCB0_SS1) 3(Sensor) 3314 P1.7 3(SCB0_CTS) 3(SCB0_SCLK 3(TCPWM3_N) 3(Sensor) 3315 P1.6 3(SCB0_RTS)3(SCB0_SS0) 3(TCPWM3_P) 3(Sensor) 3316 P1.5 3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM2_N) 3(Sensor) 3317 P1.4 3(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM2_P) 3(Sensor) 3318 P0.7 3(SCB0_CTS) 3(SCB0_SCLK 3(TCPWM2_N) 3(Sensor) 33(SWDCLK) 319 P1.0 3(TCPWM0_P) 3(Sensor) 3320 P0.4 3(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA) 3(TCPWM1_P) 3(Sensor) 33 321 P0.5 3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL) 3(TCPWM1_N) 3(Sensor) 3322 VDD Digital Power Supply Input (1.8 to 5.5V)23 P0.6 3(SCB0_RTS) 3(SCB0_SS0) 3(TCPWM2_P) 3(Sensor) 33(SWDIO) 324 GND[4] Ground Connection25 GND Ground Connection26 GND Ground Connection27 GND Ground Connection28 VDDR Radio Power Supply (2V to 3.6V)29 ANT RF Pin to External Antenna30 GND Ground ConnectionNotes2. TCPWM: Timer, Counter, and Pulse Width Modulator. If supported, the pad can be configured to any of these peripheral functions.3. When using the capacitive sensing functionality, Pad 3 (P4.0) must be connected to a CMOD capacitor (located off of Cypress BLE Module). The value of this capacitor is 2.2 nF and should be placed as close to the module as possible. 4. The main board needs to connect all GND connections (Pad 24/25/26/27) on the module to the common ground of the system. 5. If the I2S feature is used in the design, the I2S pins shall be dynamically routed to the appropriate available GPIO by PSoC Creator.
Document Number: 002-15631 Rev.PRELIMINARY Page 10 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Power Supply Connections and Recommended External ComponentsPower ConnectionsThe CYBLE-2X20XX-X1 contains two power supply connec-tions, VDD and VDDR. The VDD connection supplies power forboth digital and analog device operation. The VDDR connectionsupplies power for the device radio. VDD accepts a supply range of 1.71 V to 5.5 V. VDDR acceptsa supply range of 2.0V to 3.6V. These specifications can befound in Table 12 . The maximum power supply ripple for bothpower connections on the module is 100 mV, as shown inTable 10. The power supply ramp rate of VDD must be equal to or greaterthan that of VDDR. Connection OptionsTwo connection options are available for any application: 1. Single supply: Connect VDD and VDDR to the same supply. 2. Independent supply: Power VDD and VDDR separately. External Component RecommendationIn either connection scenario, it is recommended to place anexternal ferrite bead between the supply and the moduleconnection. The ferrite bead should be positioned as close aspossible to the module pin connection. Figure 7 details the recommended host schematic options for asingle supply scenario. The use of one or two ferrite beads willdepend on the specific application and configuration of theCYBLE-2X20XX-X1.Figure 8 details the recommended host schematic for anindependent supply scenario. The recommended ferrite bead value is 330 Ω, 100 MHz. (MurataBLM21PG331SN1D).Figure 7. Recommended Host Schematic Options for a Single Supply OptionTwo Ferrite Bead OptionSingle Ferrite Bead Option
Document Number: 002-15631 Rev.PRELIMINARY Page 11 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Figure 8. Recommended Host Schematic for an Independent Supply Option
Document Number: 002-15631 Rev.PRELIMINARY Page 12 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11The CYBLE-2X20XX-X1 schematic is shown in Figure 9.Figure 9. CYBLE-2X20XX-X1 Schematic Diagram
Document Number: 002-15631 Rev.PRELIMINARY Page 14 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Electrical SpecificationTable 10 details the absolute maximum electrical characteristics for the Cypress BLE module.Table 10. CYBLE-2X20XX-X1 Absolute Maximum RatingsTable 11 details the RF characteristics for the Cypress BLE module.Table 11. CYBLE-2X20XX-X1 RF Performance CharacteristicsTable 12 through Table 51 list the module level electrical characteristics for the CYBLE-2X20XX-X1. All specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.Parameter Description Min Typ Max Units Details/ConditionsVDDD_ABS Analog, digital, or radio supply relative to VSS (VSSD = VSSA)–0.5 – 6 V Absolute maximumVCCD_ABS Direct digital core voltage input relative to VSSD –0.5 – 1.95 V Absolute maximumVDD_RIPPLE Maximum power supply ripple for VDD and VDDR input voltage – – 100 mV3.0V supplyRipple frequency of 100 kHz to 750 kHzVGPIO_ABS GPIO voltage –0.5 – VDD +0.5 V Absolute maximumIGPIO_ABS Maximum current per GPIO –25 – 25 mA Absolute maximumIGPIO_injection GPIO injection current: Maximum for VIH > VDD and minimum for VIL < VSS –0.5 – 0.5 mA Absolute maximum current injected per pinLU Pin current for latch up –200 200 mA –Parameter Description Min Typ Max Units Details/ConditionsRFO RF output power on ANT 1 7.5 dBm Configurable via register settings (CYBLE-212006-01)RXSRF receive sensitivity on ANT – –93 – dBm Measured value (CYBLE-212006-01)FRModule frequency range 2402 – 2480 MHz –GPPeak gain – –0.5 – dBi –RL Return loss – –10 – dB –Table 12. CYBLE-2X20XX-X1 DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVDD1 Power supply input voltage 1.8 – 5.5 V With regulator enabledVDD2 Power supply input voltage unregulated 1.71 1.8 1.89 V Internally unregulated supplyVDDR1 Radio supply voltage (radio on) 2.0 – 3.6 V Restricted by RFX2401CVDDR2 Radio supply voltage (radio off) 2.0 – 3.6 V –Active Mode, VDD = 1.71 V to 5.5 VIDD3 Execute from flash; CPU at 3 MHz – 1.7 – mA T = 25 °C, VDD = 3.3 VIDD4 Execute from flash; CPU at 3 MHz – – – mA T = –40 °C to 85 °CIDD5 Execute from flash; CPU at 6 MHz – 2.5 – mA T = 25 °C, VDD = 3.3 VIDD6 Execute from flash; CPU at 6 MHz – – – mA T = –40 °C to 85 °CIDD7 Execute from flash; CPU at 12 MHz – 4 – mA T = 25 °C, VDD = 3.3 VIDD8 Execute from flash; CPU at 12 MHz – – – mA T = –40 °C to 85 °C
Document Number: 002-15631 Rev.PRELIMINARY Page 15 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11IDD9 Execute from flash; CPU at 24 MHz – 7.1 – mA T = 25 °C, VDD = 3.3 VIDD10 Execute from flash; CPU at 24 MHz – – – mA T = –40 °C to 85 °CIDD11 Execute from flash; CPU at 48 MHz – 13.4 – mA T = 25 °C, VDD = 3.3 VIDD12 Execute from flash; CPU at 48 MHz – – – mA T = –40 °C to 85 °CSleep Mode, VDD = 1.8 to 5.5 VIDD13 IMO on – – – mA T = 25 °C, VDD = 3.3 V, SYSCLK = 3 MHzSleep Mode, VDD and VDDR = 1.9 to 5.5 VIDD14 ECO on – – – mA T = 25 °C, VDD = 3.3 V, SYSCLK = 3 MHzDeep-Sleep Mode, VDD = 1.8 to 3.6 VIDD15 WDT with WCO on – 1.5 – μAT = 25 °C,VDD = 3.3 VIDD16 WDT with WCO on – – – μA T = –40 °C to 85 °CIDD17 WDT with WCO on – – – μAT = 25 °C, VDD = 5 VIDD18 WDT with WCO on – – – μA T = –40 °C to 85 °CDeep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)IDD19 WDT with WCO on – – – μA T = 25 °CIDD20 WDT with WCO on – – – μA T = –40 °C to 85 °CHibernate Mode, VDD = 1.8 to 3.6 VIDD27 GPIO and reset active – 150 – nA T = 25 °C, VDD = 3.3 VIDD28 GPIO and reset active – – – nA T = –40 °C to 85 °CHibernate Mode, VDD = 3.6 to 5.5 VIDD29 GPIO and reset active – – – nA T = 25 °C, VDD = 5 VIDD30 GPIO and reset active – – – nA T = –40 °C to 85 °CStop Mode, VDD = 1.8 to 3.6 VIDD33 Stop-mode current (VDD)–20–nAT = 25 °C, VDD = 3.3 VIDD34 Stop-mode current (VDDR)–40–- nAT = 25 °C, VDDR = 3.3 VIDD35 Stop-mode current (VDD) – – – nA T = –40 °C to 85 °CIDD36 Stop-mode current (VDDR)–––nAT = –40 °C to 85 °C, VDDR = 1.9 V to 3.6 VStop Mode, VDD = 3.6 to 5.5 VIDD37 Stop-mode current (VDD)–––nAT = 25 °C, VDD = 5 VIDD38 Stop-mode current (VDDR)–––nAT = 25 °C, VDDR = 5 VIDD39 Stop-mode current (VDD) – – – nA T = –40 °C to 85 °CIDD40 Stop-mode current (VDDR) – – – nA T = –40 °C to 85 °CTable 12. CYBLE-2X20XX-X1 DC Specifications (continued)Parameter Description Min Typ Max Units Details/Conditions
Document Number: 002-15631 Rev.PRELIMINARY Page 16 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Table 13. AC SpecificationsGPIOParameter Description Min Typ Max Units Details/ConditionsFCPU CPU frequency DC – 48 MHz 1.71 V ≤ VDD ≤ 5.5 VTSLEEP Wakeup from Sleep mode – 0 – μs Guaranteed by characterizationTDEEPSLEEP Wakeup from Deep-Sleep mode – – 25 μs24-MHz IMO. Guaranteed by characterizationTHIBERNATE Wakeup from Hibernate mode – – 2 ms Guaranteed by characterizationTSTOP Wakeup from Stop mode – – 2 ms XRES wakeupTable 14. GPIO DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVIH[6]Input voltage HIGH threshold 0.7 × VDD – – V CMOS inputLVTTL input, VDD < 2.7 V 0.7 × VDD – – V –LVTTL input, VDD ≥ 2.7 V 2.0 – – V –VILInput voltage LOW threshold – – 0.3 × VDD VCMOS inputLVTTL input, VDD < 2.7 V – – 0.3 × VDD V–LVTTL input, VDD ≥ 2.7 V – – 0.8 V –VOHOutput voltage HIGH level VDD –0.6 – – V IOH = 4 mA at 3.3-V VDD Output voltage HIGH level VDD –0.5 – – V IOH = 1 mA at 1.8-V VDDVOLOutput voltage LOW level – – 0.6 V IOL = 8 mA at 3.3-V VDDOutput voltage LOW level – – 0.6 V IOL = 4 mA at 1.8-V VDDOutput voltage LOW level – – 0.4 V IOL = 3 mA at 3.3-V VDDRPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ–RPULLDOWN Pull-down resistor 3.5 5.6 8.5 kΩ–IIL Input leakage current (absolute value) – – 2 nA 25 °C, VDD = 3.3 VIIL_CTBM Input leakage on CTBm input pins – – 4 nA –CIN Input capacitance – – 7 pF –VHYSTTL Input hysteresis LVTTL 25 40 – mV VDD > 2.7 VVHYSCMOS Input hysteresis CMOS 0.05 × VDD – – 1 –IDIODE Current through protection diode to VDD/VSS – – 100 μA–ITOT_GPIO Maximum total source or sink chip current – – 200 mA –Note6. VIH must not exceed VDD + 0.2 V.
Document Number: 002-15631 Rev.PRELIMINARY Page 17 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Table 15. GPIO AC SpecificationsXRESParameter Description Min Typ Max Units Details/ConditionsTRISEF Rise time in Fast-Strong mode 2 – 12 ns 3.3-V VDDD, CLOAD = 25 pFTFALLF Fall time in Fast-Strong mode 2 – 12 ns 3.3-V VDDD, CLOAD = 25 pFTRISES Rise time in Slow-Strong mode 10 – 60 ns 3.3-V VDDD, CLOAD = 25 pFTFALLS Fall time in Slow-Strong mode 10 – 60 ns 3.3-V VDDD, CLOAD = 25 pFFGPIOUT1 GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V Fast-Strong mode ––33MHz90/10%, 25 pF load, 60/40 duty cycleFGPIOUT2 GPIO Fout; 1.7 V≤ VDD ≤ 3.3 V Fast-Strong mode – – 16.7 MHz 90/10%, 25 pF load, 60/40 duty cycleFGPIOUT3 GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V Slow-Strong mode –– 7 MHz90/10%, 25 pF load, 60/40 duty cycleFGPIOUT4 GPIO Fout; 1.7 V ≤ VDD ≤ 3.3 V Slow-Strong mode ––3.5MHz90/10%, 25 pF load, 60/40 duty cycleFGPIOIN GPIO input operating frequency1.71 V ≤ VDD ≤ 5.5 V – – 48 MHz 90/10% VIOTable 16. OVT GPIO DC Specifications (P5_0 and P5_1 Only)Parameter Description Min Typ Max Units Details/ConditionsIIL Input leakage (absolute value).VIH > VDD ––10 μA 25°C, VDD = 0 V, VIH = 3.0 VVOL Output voltage LOW level – – 0.4 V IOL = 20 mA, VDD > 2.9 V Table 17. OVT GPIO AC Specifications (P5_0 and P5_1 Only)Parameter Description Min Typ Max Units Details/ConditionsTRISE_OVFS Output rise time in Fast-Strong mode 1.5 – 12 ns 25-pF load, 10%–90%, VDD = 3.3 VTFALL_OVFS Output fall time in Fast-Strong mode 1.5 – 12 ns 25-pF load, 10%–90%, VDD = 3.3 VTRISESS Output rise time in Slow-Strong mode 10 – 60 ns 25 pF load, 10%-90%, VDD = 3.3 VTFALLSS Output fall time in Slow-Strong mode 10 – 60 ns 25 pF load, 10%-90%, VDD = 3.3 VFGPIOUT1 GPIO FOUT; 3.3 V ≤ VDD ≤ 5.5 VFast-Strong mode ––24MHz90/10%, 25 pF load, 60/40 duty cycleFGPIOUT2 GPIO FOUT; 1.71 V ≤ VDD ≤ 3.3 VFast-Strong mode ––16MHz90/10%, 25 pF load, 60/40 duty cycleTable 18. XRES DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVIH Input voltage HIGH threshold 0.7 × VDDD – – V CMOS inputVIL Input voltage LOW threshold – – 0.3 × VDDD V CMOS inputRPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ–CIN Input capacitance – 3 – pF –VHYSXRES Input voltage hysteresis – 100 – mV –IDIODE Current through protection diode to VDD/VSS – – 100 μA–
Document Number: 002-15631 Rev.PRELIMINARY Page 18 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Temperature SensorSAR ADCTable 19. XRES AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTRESETWIDTH Reset pulse width 1 – – μs–Table 20. Temperature Sensor Specifications Parameter Description Min Typ Max Units Details/ConditionsTSENSACC Temperature-sensor accuracy –5 ±1 5 °C –40 °C to +85 °CTable 21. SAR ADC DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsA_RES Resolution – – 12 bitsA_CHNIS_S Number of channels - single-ended – – 8 8 full-speedA-CHNKS_D Number of channels - differential – – 4 Diff inputs use neighboring I/OA-MONO Monotonicity – – – YesA_GAINERR Gain error – – ±0.1 % With external reference A_OFFSET Input offset voltage – – 2 mV Measured with 1-V VREFA_ISAR Current consumption – – 1 mAA_VINS Input voltage range - single-ended VSS –VDDA VA_VIND Input voltage range - differential VSS – VDDA VA_INRES Input resistance – – 2.2 kΩA_INCAP Input capacitance – – 10 pFVREFSAR Trimmed internal reference to SAR –1 – 1 % Percentage of Vbg (1.024 V)Table 22. SAR ADC AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsA_PSRR Power-supply rejection ratio 70 – – dB Measured at 1-V referenceA_CMRR Common-mode rejection ratio 66 – – dBA_SAMP Sample rate – – 1 MspsFsarintref SAR operating speed without external ref. bypass – – 100 Ksps 12-bit resolutionA_SNR Signal-to-noise ratio (SNR) 65 – – dB FIN = 10 kHzA_BW Input bandwidth without aliasing – – A_SAMP/2 kHzA_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V, 1 Msps –1.7 – 2 LSB VREF = 1 V to VDDA_INL Integral nonlinearity. VDDD = 1.71 V to 3.6 V, 1 Msps –1.5 – 1.7 LSB VREF = 1.71 V to VDDA_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps –1.5 – 1.7 LSB VREF = 1 V to VDDA_dnl Differential nonlinearity. VDD = 1.71 V to 5.5 V, 1 Msps –1 – 2.2 LSB VREF = 1 V to VDD
Document Number: 002-15631 Rev.PRELIMINARY Page 19 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11CSDA_DNL Differential nonlinearity. VDD = 1.71 V to 3.6 V, 1 Msps –1 – 2 LSB VREF = 1.71 V to VDDA_DNL Differential nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps –1 – 2.2 LSB VREF = 1 V to VDDA_THD Total harmonic distortion – – –65 dB FIN = 10 kHzTable 22. SAR ADC AC Specifications (continued)Parameter Description Min Typ Max Units Details/ConditionsCSD Block SpecificationsParameter Description Min Typ Max Units Details/ConditionsVCSD Voltage range of operation 1.71 – 5.5 V –IDAC1 DNL for 8-bit resolution –1 – 1 LSB –IDAC1 INL for 8-bit resolution –3 – 3 LSB –IDAC2 DNL for 7-bit resolution –1 – 1 LSB –IDAC2 INL for 7-bit resolution –3 – 3 LSB –SNR Ratio of counts of finger to noise 5 – – RatioCapacitance range of 9 pF to 35 pF, 0.1-pF sensitivity. Radio is not operating during the scanIDAC1_CRT1 Output current of IDAC1 (8 bits) in High range –612 – μA–IDAC1_CRT2 Output current of IDAC1 (8 bits) in Low range –306 – μA–IDAC2_CRT1 Output current of IDAC2 (7 bits) in High range –305 – μA–IDAC2_CRT2 Output current of IDAC2 (7 bits) in Low range –153 – μA–
Document Number: 002-15631 Rev.PRELIMINARY Page 20 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Digital PeripheralsTimer Counter Table 23. Timer DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsITIM1 Block current consumption at 3 MHz – – 42 μA 16-bit timerITIM2 Block current consumption at 12 MHz – – 130 μA 16-bit timerITIM3 Block current consumption at 48 MHz – – 535 μA 16-bit timerTable 24. Timer AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTTIMFREQ Operating frequency FCLK –48MHzTCAPWINT Capture pulse width (internal) 2 × TCLK ––nsTCAPWEXT Capture pulse width (external) 2 × TCLK ––nsTTIMRES Timer resolution TCLK ––nsTTENWIDINT Enable pulse width (internal) 2 × TCLK ––nsTTENWIDEXT Enable pulse width (external) 2 × TCLK ––nsTTIMRESWINT Reset pulse width (internal) 2 × TCLK ––nsTTIMRESEXT Reset pulse width (external) 2 × TCLK ––nsTable 25. Counter DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsICTR1 Block current consumption at 3 MHz – – 42 μA 16-bit counterICTR2 Block current consumption at 12 MHz – – 130 μA 16-bit counterICTR3 Block current consumption at 48 MHz – – 535 μA 16-bit counterTable 26. Counter AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTCTRFREQ Operating frequency FCLK –48MHz –TCTRPWINT Capture pulse width (internal) 2 × TCLK ––ns –TCTRPWEXT Capture pulse width (external) 2 × TCLK ––ns –TCTRES Counter Resolution TCLK ––ns –TCENWIDINT Enable pulse width (internal) 2 × TCLK ––ns –TCENWIDEXT Enable pulse width (external) 2 × TCLK ––ns –TCTRRESWINT Reset pulse width (internal) 2 × TCLK ––ns –TCTRRESWEXT Reset pulse width (external) 2 × TCLK –– ns –
Document Number: 002-15631 Rev.PRELIMINARY Page 21 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Pulse Width Modulation (PWM) LCD Direct Drive Table 27. PWM DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsIPWM1 Block current consumption at 3 MHz – – 42 μA 16-bit PWMIPWM2 Block current consumption at 12 MHz – – 130 μA 16-bit PWMIPWM3 Block current consumption at 48 MHz – – 535 μA 16-bit PWMTable 28. PWM AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTPWMFREQ Operating frequency FCLK –48MHz –TPWMPWINT Pulse width (internal) 2 × TCLK ––ns –TPWMEXT Pulse width (external) 2 × TCLK ––ns –TPWMKILLINT Kill pulse width (internal) 2 × TCLK ––ns –TPWMKILLEXT Kill pulse width (external) 2 × TCLK ––ns –TPWMEINT Enable pulse width (internal) 2 × TCLK ––ns –TPWMENEXT Enable pulse width (external) 2 × TCLK ––ns –TPWMRESWINT Reset pulse width (internal) 2 × TCLK ––ns –TPWMRESWEXT Reset pulse width (external) 2 × TCLK ––ns –Table 29. LCD Direct Drive DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsILCDLOW Operating current in low-power mode – 17.5 – μA16 × 4 small segment display at 50 HzCLCDCAP LCD capacitance per segment/common driver – 500 5000 pF –LCDOFFSET Long-term segment offset – 20 – mV –ILCDOP1 LCD system operating current, VBIAS = 5 V – 2 – mA 3 2 × 4 se gm en ts . 5 0 H z a t 25 °CILCDOP2 LCD system operating current, VBIAS = 3.3 V – 2 – mA 32 × 4 segments50 Hz at 25 °CTable 30. LCD Direct Drive AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsFLCD LCD frame rate 10 50 150 Hz –
Document Number: 002-15631 Rev.PRELIMINARY Page 22 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Serial CommunicationTable 31. Fixed I2C DC SpecificationsTable 33. Fixed UART DC SpecificationsTable 34. Fixed UART AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsII2C1 Block current consumption at 100 kHz – – 50 μA–II2C2 Block current consumption at 400 kHz – – 155 μA–II2C3 Block current consumption at 1 Mbps – – 390 μA–II2C4 I2C enabled in Deep-Sleep mode – – 1.4 μA–Table 32. Fixed I2C AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsFI2C1 Bit rate – – 400 kHzParameter Description Min Typ Max Units Details/ConditionsIUART1 Block current consumption at 100 kbps – – 55 μA–IUART2 Block current consumption at 1000 kbps – – 312 μA–Parameter Description Min Typ Max Units Details/ConditionsFUART Bit rate – – 1 Mbps –Table 35. Fixed SPI DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsISPI1 Block current consumption at 1 Mbps – – 360 μA–ISPI2 Block current consumption at 4 Mbps – – 560 μA–ISPI3 Block current consumption at 8 Mbps – – 600 μA–Table 36. Fixed SPI AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsFSPI SPI operating frequency (master; 6x over sampling) – – 8 MHz –Table 37. Fixed SPI Master Mode AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTDMO MOSI valid after SCLK driving edge – – 18 ns –TDSI MISO valid before SCLK capturing edge Full clock, late MISO sampling used 20 – – ns Full clock, late MISO samplingTHMO Previous MOSI data hold time 0 – – ns Referred to Slave capturing edgeTable 38. Fixed SPI Slave Mode AC SpecificationsParameter Description Min Typ Max UnitsTDMI MOSI valid before SCLK capturing edge 40 – – nsTDSO MISO valid after SCLK driving edge – – 42 + 3 × TCPU nsTDSO_ext MISO Valid after SCLK driving edge in external clock mode. VDD < 3.0 V – – 50 nsTHSO Previous MISO data hold time 0 – – nsTSSELSCK SSEL valid to first SCK valid edge 100 – – ns
Document Number: 002-15631 Rev.PRELIMINARY Page 23 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11MemorySystem ResourcesPower-on-Reset (POR) Table 39. Flash DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVPE Erase and program voltage 1.71 – 5.5 V –TWS48 Number of Wait states at 32–48 MHz 2 – – CPU execution from flashTWS32 Number of Wait states at 16–32 MHz 1 – – CPU execution from flashTWS16 Number of Wait states for 0–16 MHz 0 – – CPU execution from flashTable 40. Flash AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTROWWRITE[7] Row (block) write time (erase and program) – – 20 ms Row (block) = 256 bytesTROWERASE[7] Row erase time – – 13 ms –TROWPROGRAM[7] Row program time after erase – – 7 ms –TBULKERASE[7] Bulk erase time (256 KB) – – 35 ms –TDEVPROG[7] Total device program time – – 25 seconds –FEND Flash endurance 100 K – – cycles –FRET Flash retention. TA ≤ 55 °C, 100 K P/E cycles 20 – – years –FRET2 Flash retention. TA ≤ 85 °C, 10 K P/E cycles 10 – – years –Note7. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.Table 41. POR DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVRISEIPOR Rising trip voltage 0.80 – 1.45 V –VFALLIPOR Falling trip voltage 0.75 – 1.40 V –VIPORHYST Hysteresis 15 – 200 mV –Table 42. POR AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTPPOR_TR Precision power-on reset (PPOR) response time in Active and Sleep modes ––1μs–Table 43. Brown-Out DetectParameter Description Min Typ Max Units Details/ConditionsVFALLPPOR BOD trip voltage in Active and Sleep modes 1.64 – – V –VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 – – V –Table 44. Hibernate ResetParameter Description Min Typ Max Units Details/ConditionsVHBRTRIP BOD trip voltage in Hibernate 1.1 – – V –
Document Number: 002-15631 Rev.PRELIMINARY Page 24 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Voltage Monitors (LVD) SWD Interface Table 45. Voltage Monitor DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsVLVI1 LVI_A/D_SEL[3:0] = 0000b 1.71 1.75 1.79 V –VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V –VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V –VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V –VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V –VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V –VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V –VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V –VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V –VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V –VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V –VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V –VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V –VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V –VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V –VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V –LVI_IDD Block current – – 100 μA–Table 46. Voltage Monitor AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTMONTRIP Voltage monitor trip time – – 1 μs–Table 47. SWD Interface SpecificationsParameter Description Min Typ Max Units Details/ConditionsF_SWDCLK1 3.3 V ≤ VDD ≤ 5.5 V – – 14 MHz SWDCLK ≤ 1/3 CPU clock frequencyF_SWDCLK2 1.71 V ≤ VDD ≤ 3.3 V – – 7 MHz SWDCLK ≤ 1/3 CPU clock frequencyT_SWDI_SETUP T = 1/f SWDCLK 0.25 × T – – ns –T_SWDI_HOLD T = 1/f SWDCLK 0.25 × T – – ns –T_SWDO_VALID T = 1/f SWDCLK – – 0.5 × T ns –T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns –
Document Number: 002-15631 Rev.PRELIMINARY Page 25 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Internal Main OscillatorInternal Low-Speed Oscillator Table 52. ECO Trim Value SpecificationBLE SubsystemTable 48. IMO DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsIIMO1 IMO operating current at 48 MHz – – 1000 μA–IIMO2 IMO operating current at 24 MHz – – 325 μA–IIMO3 IMO operating current at 12 MHz – – 225 μA–IIMO4 IMO operating current at 6 MHz – – 180 μA–IIMO5 IMO operating current at 3 MHz – – 150 μA–Table 49. IMO AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsFIMOTOL3 Frequency variation from 3 to 48 MHz – – ±2 % With API-called calibrationFIMOTOL3 IMO startup time – 12 – μs–Table 50. ILO DC SpecificationsParameter Description Min Typ Max Units Details/ConditionsIILO2 ILO operating current at 32 kHz – 0.3 1.05 μA–Table 51. ILO AC SpecificationsParameter Description Min Typ Max Units Details/ConditionsTSTARTILO1 ILO startup time – – 2 ms –FILOTRIM1 32-kHz trimmed frequency 15 32 50 kHz –Parameter Description Value Details/ConditionsECOTRIM 24-MHz trim value (firmware configuration) 0x00007FDC Optimum trim value that needs to be loaded to register CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG Table 53. BLE SubsystemParameter Description Min Typ Max Units Details/ConditionsRF Receiver SpecificationRXS, IDLE RX sensitivity with idle transmitter – –89 – dBm –RX sensitivity with idle transmitter excluding Balun loss – –91 – dBm Guaranteed by design simulationRXS, DIRTY RX sensitivity with dirty transmitter – –87 –70 dBm RF-PHY Specification (RCV-LE/CA/01/C)RXS, HIGHGAIN RX sensitivity in high-gain mode with idle transmitter – –91 – dBm –PRXMAX Maximum input power –10 –1 – dBm RF-PHY Specification (RCV-LE/CA/06/C)CI1Cochannel interference, Wanted signal at –67 dBm and Interferer at FRX– 9 21 dB RF-PHY Specification (RCV-LE/CA/03/C)
Document Number: 002-15631 Rev.PRELIMINARY Page 26 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11CI2Adjacent channel interferenceWanted signal at –67 dBm and Interferer at FRX ±1 MHz – 3 15 dB RF-PHY Specification (RCV-LE/CA/03/C)CI3Adjacent channel interferenceWanted signal at –67 dBm and Interferer at FRX ±2 MHz – –29 – dB RF-PHY Specification (RCV-LE/CA/03/C)CI4Adjacent channel interferenceWanted signal at –67 dBm and Interferer at ≥FRX ±3 MHz – –39 – dB RF-PHY Specification (RCV-LE/CA/03/C)CI5Adjacent channel interferenceWanted Signal at –67 dBm and Interferer at Image frequency (FIMAGE)– –20 – dB RF-PHY Specification (RCV-LE/CA/03/C)CI3Adjacent channel interferenceWanted signal at –67 dBm and Interferer at Image frequency (FIMAGE ± 1 MHz) – –30 – dB RF-PHY Specification (RCV-LE/CA/03/C)OBB1Out-of-band blocking,Wanted signal at –67 dBm and Interferer at F = 30–2000 MHz–30 –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C)OBB2Out-of-band blocking,Wanted signal at –67 dBm and Interferer at F = 2003–2399 MHz–35 –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C)OBB3Out-of-band blocking,Wanted signal at –67 dBm and Interferer at F = 2484–2997 MHz–35 –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C)OBB4Out-of-band blocking,Wanted signal a –67 dBm and Interferer at F = 3000–12750 MHz–30 –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C)IMDInter modulation performanceWanted signal at –64 dBm and 1-Mbps BLE, third, fourth, and fifth offset channel–50 – – dBm RF-PHY Specification (RCV-LE/CA/05/C)RXSE1 Receiver spurious emission30 MHz to 1.0 GHz –––57dBm100-kHz measurement bandwidthETSI EN300 328 V1.8.1RXSE2 Receiver spurious emission1.0 GHz to 12.75 GHz –––47dBm1-MHz measurement bandwidthETSI EN300 328 V1.8.1RF Transmitter SpecificationsTXP, ACC RF power accuracy – ±1 – dB –TXP, RANGE RF power control range – 20 – dB –TXP, 0dBm Output power, 0-dB Gain setting (PA7) – 0 – dBm –TXP, MAX Output power, maximum power setting (PA10) –3 – dBm –TXP, MIN Output power, minimum power setting (PA1) – –18 – dBm –F2AVG Average frequency deviation for 10101010 pattern 185 – – kHz RF-PHY Specification (TRM-LE/CA/05/C)F1AVG Average frequency deviation for 11110000 pattern 225 250 275 kHz RF-PHY Specification (TRM-LE/CA/05/C)Table 53. BLE Subsystem (continued)Parameter Description Min Typ Max Units Details/Conditions
Document Number: 002-15631 Rev.PRELIMINARY Page 27 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11EO Eye opening = ΔF2AVG/ΔF1AVG 0.8 – – RF-PHY Specification (TRM-LE/CA/05/C)FTX, ACC Frequency accuracy –150 – 150 kHz RF-PHY Specification (TRM-LE/CA/06/C)FTX, MAXDR Maximum frequency drift –50 – 50 kHz RF-PHY Specification (TRM-LE/CA/06/C)FTX, INITDR Initial frequency drift –20 – 20 kHz RF-PHY Specification (TRM-LE/CA/06/C)FTX, DR Maximum drift rate –20 – 20 kHz/50 μsRF-PHY Specification (TRM-LE/CA/06/C)IBSE1 In-band spurious emission at 2-MHz offset –––20dBmRF-PHY Specification (TRM-LE/CA/03/C)IBSE2 In-band spurious emission at ≥3-MHz offset ––-30dBmRF-PHY Specification (TRM-LE/CA/03/C)TXSE1 Transmitter spurious emissions (average), <1.0 GHz – – -55.5 dBm FCC-15.247TXSE2 Transmitter spurious emissions (average), >1.0 GHz – – -41.5 dBm FCC-15.247RF Current SpecificationsIRX Receive current in normal mode – 18.7 – mA –IRX_RF Radio receive current in normal mode – 16.4 – mA Measured at VDDRIRX, HIGHGAIN Receive current in high-gain mode – 21.5 – mA –ITX, 3dBm TX current at 3-dBm setting (PA10) – 20 – mA –ITX, 0dBm TX current at 0-dBm setting (PA7) – 16.5 – mA –ITX_RF, 0dBm Radio TX current at 0 dBm setting (PA7) – 15.6 – mA Measured at VDDRITX_RF, 0dBm Radio TX current at 0 dBm excluding Balun loss – 14.2 – mA Guaranteed by design simulationITX,-3dBm TX current at –3-dBm setting (PA4) – 15.5 – mA –ITX,-6dBm TX current at –6-dBm setting (PA3) – 14.5 – mA –ITX,-12dBm TX current at –12-dBm setting (PA2) – 13.2 – mA –ITX,-18dBm TX current at –18-dBm setting (PA1) – 12.5 – mA –Iavg_1sec, 0dBm Average current at 1-second BLE connection interval – 17.1 – μATXP: 0 dBm; ±20-ppm master and slave clock accuracy.For empty PDU exchangeIavg_4sec, 0dBm Average current at 4-second BLE connection interval –6.1 – μATXP: 0 dBm; ±20-ppm master and slave clock accuracy.For empty PDU exchangeGeneral RF SpecificationsFREQ RF operating frequency 2400 – 2482 MHz –CHBW Channel spacing – 2 – MHz –DR On-air data rate – 1000 – kbps –Table 53. BLE Subsystem (continued)Parameter Description Min Typ Max Units Details/Conditions
Document Number: 002-15631 Rev.PRELIMINARY Page 28 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11IDLE2TX BLE.IDLE to BLE. TX transition time – 120 140 μs–IDLE2RX BLE.IDLE to BLE. RX transition time – 75 120 μs–RSSI SpecificationsRSSI, ACC RSSI accuracy – ±5 – dB –RSSI, RES RSSI resolution – 1 – dB –RSSI, PER RSSI sample period – 6 – μs–Table 53. BLE Subsystem (continued)Parameter Description Min Typ Max Units Details/Conditions
Document Number: 002-15631 Rev.PRELIMINARY Page 29 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Environmental SpecificationsEnvironmental ComplianceThis Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF)directives. The Cypress module and components used to produce this module are RoHS and HF compliant.RF CertificationThe CYBLE-212006-01 and CYBLE-202007-01 modules will be certified under the following RF certification standards at production release.nFCC: WAP2006nCEnIC: 7922A-2006nMIC: TBDnKC: TBDSafety CertificationThe CYBLE-212006-01 and CYBLE-202007-01 modules comply with the following regulations:nUnderwriters Laboratories, Inc. (UL) - Filing E331901nCSAnTUVEnvironmental ConditionsTable 54 describes the operating and storage conditions for the Cypress BLE module.Table 54. Environmental Conditions for CYBLE-2X20XX-X1ESD and EMI ProtectionExposed components require special attention to ESD and electromagnetic interference (EMI).A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.Description Minimum Specification Maximum SpecificationOperating temperature –40 °C 85 °COperating humidity (relative, non-condensation) 5% 85%Thermal ramp rate – 3 °C/minuteStorage temperature –40 °C 85 °CStorage temperature and humidity – 85 ° C at 85%ESD: Module integrated into system Components[8] –15 kV Air2.2 kV ContactNote8. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.
RF Exposure distance of the device is 15mm.
RF Exposure distance of the device is 15mm.la distance d'exposition RF de l'appareil est de 15mm.
Document Number: 002-15631 Rev.PRELIMINARY Page 32 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11MIC JapanCYBLE-212006-01 and CYBLE-202007-01 are certified as a module with type certification number TBD. End products that integrateCYBLE-212006-01 and CYBLE-202007-01 do not need additional MIC Japan certification for the end product.End product can display the certification label of the embedded module.KC KoreaCYBLE-212006-01 and CYBLE-202007-01 are certified for use in Korea with certificate number TBD.
Document Number: 002-15631 Rev.PRELIMINARY Page 33 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11PackagingThe CYBLE-2X20XX-X1 is offered in tape and reel packaging. Figure 10 details the tape dimensions used for the CYBLE-2X20XX-X1.Figure 10. CYBLE-2X20XX-X1 Tape DimensionsFigure 11 details the orientation of the CYBLE-2X20XX-X1 in the tape as well as the direction for unreeling.Figure 11. Component Orientation in Tape and Unreeling Direction (Illustration Only) - TBDTable 55. Solder Reflow Peak TemperatureModule Part Number Package Maximum Peak Temperature Maximum Time at Peak Temperature No. of CyclesCYBLE-2X20XX-X1 30-pad SMT 260 °C 30 seconds 2Table 56. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2Module Part Number Package MSL CYBLE-2X20XX-X1 30-pad SMT MSL 3
Document Number: 002-15631 Rev.PRELIMINARY Page 34 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Figure 12 details reel dimensions used for the CYBLE-2X20XX-X1.Figure 12. Reel DimensionsThe CYBLE-2X20XX-X1 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBLE-2X20XX-X1 is detailed in Figure 13.Figure 13. CYBLE-2X20XX-X1 Center of Mass (Seen from Top) - TBD
Document Number: 002-15631 Rev.PRELIMINARY Page 35 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Ordering InformationTable 57 lists the CYBLE-2X20XX-X1 part numbers and features. Part Numbering ConventionThe part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows.For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website.Table 57. Ordering InformationPart NumberCPU Speed (MHz)Flash Size (KB)CapSense SCB TCPWM12-Bit SAR ADCI2SLCD Package Packing CertifiedCYBLE-212006-01 48 256 Yes 2 4 1 Msps Yes Yes 30-SMT Tape and Reel YesCYBLE-202007-01 48 256 Yes 2 4 1 Msps Yes Yes 30-SMT Tape and Reel YesCYBLE-202013-11 48 256 Yes 2 4 1 Msps Yes Yes 30-SMT Tape and Reel NoU.S. Cypress Headquarters Address 198 Champion Court, San Jose, CA 95134U.S. Cypress Headquarter Contact Info (408) 943-2600Cypress website address http://www.cypress.com
Document Number: 002-15631 Rev.PRELIMINARY Page 36 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Acronyms Document ConventionsUnits of MeasureTable 58. Acronyms Used in this DocumentAcronym DescriptionBLE Bluetooth Low EnergyBluetooth SIG Bluetooth Special Interest GroupCE European ConformityCSA Canadian Standards AssociationEMI electromagnetic interferenceESD electrostatic dischargeFCC Federal Communications CommissionGPIO general-purpose input/outputIC Industry CanadaIDE integrated design environmentKC Korea CertificationMIC Ministry of Internal Affairs and Communications (Japan)PCB printed circuit boardRX receiveQDID qualification design IDSMTsurface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBsTCPWM timer, counter, pulse width modulator (PWM)TUV Germany: Technischer Überwachungs-Verein (Technical Inspection Association)TX transmitTable 59. Units of MeasureSymbol Unit of Measure°C degree CelsiuskV kilovoltmA milliamperesmm millimetersmV millivoltμA microamperesμm micrometersMHz megahertzGHz gigahertzVvolt
Document Number: 002-15631 Rev.PRELIMINARY Page 37 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11Document History Page Document Title: CYBLE-212006-01, CYBLE-202007-01, CYBLE-202013-11 EZ-BLE™ PRoC™ 4.2 XR ModuleDocument Number: 002-09764Revision ECN Orig. of ChangeSubmission Date Description of Change** PRELIM-INARY MINS PRELIM-INARYPreliminary datasheet for CYBLE-212006-01, CYBLE-202007-01 and CYBLE-202013-11module.
Document Number: 002-15631 Rev.PRELIMINARY Revised July 28, 2016 Page 38 of 38PRELIMINARYCYBLE-212006-01CYBLE-202007-01CYBLE-202013-11© Cypress Semiconductor Corporation, 2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, includingany software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectualproperty rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress herebygrants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify andreproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (eitherdirectly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as providedby Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of theSoftware is prohibited.TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWAREOR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extentpermitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of anyproduct or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It isthe responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress productsare not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices orsystems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of thedevice or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonablyexpected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and otherliabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the UnitedStates and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.Sales, Solutions, and Legal InformationWorldwide Sales and Design SupportCypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.ProductsARM® Cortex® Microcontrollers cypress.com/armAutomotive cypress.com/automotiveClocks & Buffers cypress.com/clocksInterface cypress.com/interfaceLighting & Power Control cypress.com/powerpsocMemory cypress.com/memoryPSoC cypress.com/psocTouch Sensing cypress.com/touchUSB Controllers cypress.com/usbWireless/RF cypress.com/wirelessPSoC® SolutionsPSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LPCypress Developer CommunityForums | Projects | Video | Blogs | Training | ComponentsTechnical Supportcypress.com/support

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