Cypress Semiconductor 2006 Bluetooth Module User Manual
Cypress Semiconductor Bluetooth Module
User Manual
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| Mirror Download [FCC.gov] | |
| Document ID | 3115390 |
| Application ID | GBxCVoNAyU9nVGR84ikZxw== |
| Document Description | User Manual |
| Short Term Confidential | No |
| Permanent Confidential | No |
| Supercede | No |
| Document Type | User Manual |
| Display Format | Adobe Acrobat PDF - pdf |
| Filesize | 382.39kB (4779882 bits) |
| Date Submitted | 2016-08-29 00:00:00 |
| Date Available | 2016-08-29 00:00:00 |
| Creation Date | 2016-07-27 17:01:00 |
| Producing Software | Acrobat Distiller 9.5.5 (Windows) |
| Document Lastmod | 2016-08-24 13:45:03 |
| Document Title | CYBLE-022001-00 Bluetooth®Low Energy (BLE) Module |
| Document Creator | FrameMaker 7.0 |
| Document Author: | Cypress Semiconductor |
PRELIMINARY
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to
quickly and effectively integrate the module into your design.
Overview: EZ-BLE Module Portfolio, Module Roadmap
EZ-BLE PRoC Product Overview
PRoC BLE Silicon Datasheet
Application notes: Cypress offers a number of BLE application
notes covering a broad range of topics, from basic to advanced
level. Recommended application notes for getting started with
EZ-BLE modules are:
p AN96841 - Getting Started with EZ-BLE Module
p AN94020 - Getting Started with PRoC BLE
®
p AN97060 - PSoC 4 BLE and PRoC™ BLE - Over-The-Air
(OTA) Device Firmware Upgrade (DFU) Guide
p AN91162 - Creating a BLE Custom Profile
p AN91184 - PSoC 4 BLE - Designing BLE Applications
p AN92584 - Designing for Low Power and Estimating Battery
Life for BLE Applications
®
®
p AN85951 - PSoC 4 CapSense Design Guide
®
p AN95089 - PSoC 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques
AN91445 - Antenna Design and RF Layout Guidelines
Knowledge Base Articles
p KBA97095 - EZ-BLE™ Module Placement
n Technical Reference Manual (TRM):
®
p PRoC BLE Technical Reference Manual
Development Kits:
p CYBLE-212006-EVAL, CYBLE-212006-01 Evaluation Board
p CYBLE-202007-EVAL, CYBLE-202007-01 Evaluation Board
p CYBLE-202013-EVAL, CYBLE-202013-11 Evaluation Board
®
p CY8CKIT-042-BLE, Bluetooth Low Energy (BLE) Pioneer
Kit
®
p CY8CKIT-002, PSoC MiniProg3 Program and Debug Kit
Test and Debug Tools:
®
p CYSmart, Bluetooth LE Test and Debug Tool (Windows)
®
p CYSmart Mobile, Bluetooth LE Test and Debug Tool
(Android/iOS Mobile App)
PSoC® Creator™ Integrated Design Environment (IDE)
PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling and
debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, PRoC BLE and EZ-BLE module systems with no code size limitations. PSoC
peripherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified,
production-ready PSoC Components™.
PSoC Components are analog and digital “virtual chips,” represented by an icon that users can drag-and-drop into a design and
configure to suit a broad array of application requirements.
Bluetooth Low Energy Component
The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you
quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.1 compliant BLE protocol stack and
provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS)
hardware via the stack.
Technical Support
Frequently Asked Questions (FAQs): Learn more about our BLE ECO System.
Forum: See if your question is already answered by fellow developers on the PSoC 4 BLE and PRoC BLE forums.
Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,
you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.
Document Number: 002-15631 Rev.PRELIMINARY
Page 2 of 38
PRELIMINARY
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Contents
Overview............................................................................ 4
Module Description...................................................... 4
Pad Connection Interface ................................................ 6
Recommended Host PCB Layout ................................... 7
Power Supply Connections and Recommended External
Components.................................................................... 10
Connection Options................................................... 10
External Component Recommendation .................... 10
Critical Components List ........................................... 13
Antenna Design......................................................... 13
Qualified Antenna for CYBLE-202007-01 and CY .........
BLE-202013-11 ................................................................ 13
Power Amplifier (PA) and Low Noise Amplifier (LNA) 13
Electrical Specification .................................................. 14
GPIO ......................................................................... 16
XRES......................................................................... 17
Digital Peripherals ..................................................... 20
Serial Communication ............................................... 22
Memory ..................................................................... 23
System Resources .................................................... 23
Environmental Specifications ....................................... 29
Environmental Compliance ....................................... 29
RF Certification.......................................................... 29
Document Number: 002-15631 Rev.PRELIMINARY
Safety Certification ....................................................
Environmental Conditions .........................................
ESD and EMI Protection ...........................................
Regulatory Information ..................................................
FCC ...........................................................................
Industry Canada (IC) Certification .............................
European R&TTE Declaration of Conformity ............
MIC Japan .................................................................
KC Korea...................................................................
Packaging........................................................................
Ordering Information......................................................
Part Numbering Convention ......................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
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Page 3 of 38
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
PRELIMINARY
Overview
Module Description
The CYBLE-2X20XX-X1 module is a complete module designed to be soldered to the applications main board.
Module Dimensions and Drawing
Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE
module functionality. Such selections will still guarantee that all height restrictions of the component area are maintained. Designs
should be held within the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm).
Table 1. Module Design Dimensions
Dimension Item
Specification
Length (X)
15.00 ± 0.15 mm
Width (Y)
23.00 ± 0.15 mm
Length (X)
15.00 ± 0.15 mm
Width (Y)
4.65 ± 0.15 mm
PCB thickness
Height (H)
0.80 ± 0.10 mm
Shield height
Height (H)
1.20 ± 0.10 mm
Maximum component height
Height (H)
1.20 mm typical (shield) - CYBLE-212006-01
1.25 mm typical (connector) - CYBLE-202007-01
0.75mm typical (crystal) - CYBLE-202013-11
Total module thickness (bottom of module to highest component)
Height (H)
2.00 mm typical - CYBLE-212006-01
2.05 mm typical - CYBLE-202007-01
1.55 mm typical - CYBLE-202013-11
Module dimensions
Antenna location dimensions
See Figure 1 on page 5 for the mechanical reference drawing for CYBLE-2X20XX-X1.
Document Number: 002-15631 Rev.PRELIMINARY
Page 4 of 38
PRELIMINARY
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Figure 1. Module Mechanical Drawing
Top View (View from Top)
Side View
Bottom View (Seen from Bottom)
Note
1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on
recommended host PCB layout, see Figure 3, Figure 4, Figure 5, and Figure 6 and Table 3.
Document Number: 002-15631 Rev.PRELIMINARY
Page 5 of 38
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
PRELIMINARY
Pad Connection Interface
As shown in the bottom view of Figure 1 on page 5, the CYBLE-2X20XX-X1 connects to the host board via solder pads on the backside
of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-2X20XX-X1 module.
Table 2. Solder Pad Connection Description
Name
SP
Connections Connection Type
30
Pad Length Dimension
Pad Width Dimension
Pad Pitch
1.02 mm
0.71 mm
1.27 mm
Solder Pads
Figure 2. Solder Pad Dimensions (Seen from Bottom)
To maximize RF performance, the host layout should follow these recommendations:
1. The ideal placement of the Cypress BLE module is in a corner of the host board with the trace antenna located at the far corner.
This placement minimizes the additional recommended keep out area stated in item 2. Please refer to AN96841 for module
placement best practices.
2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional
keep out area, where no grounding or signal trace are contained. The keep out area applies to all layers of the host board. The
recommended dimensions of the host PCB keep out area are shown in Figure 3 (dimensions are in mm).
Figure 3. Recommended Host PCB Keep Out Area Around the CYBLE-2X20XX-X1 Antenna
Host PCB Keep Out Area Around Trace Antenna
Document Number: 002-15631 Rev.PRELIMINARY
Page 6 of 38
PRELIMINARY
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Recommended Host PCB Layout
Figure 4, Figure 5, Figure 6, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the
CYBLE-212006-01. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad
on either side) shown in Figure 6 is the minimum recommended host pad length. The host PCB layout pattern can be completed using
either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern.
Figure 4. Host Layout Pattern for CYBLE-2X20XX-X1
Top View (On Host PCB)
Document Number: 002-15631 Rev.PRELIMINARY
Figure 5. Module Pad Location from Origin
Top View (On Host PCB)
Page 7 of 38
PRELIMINARY
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Table 3 provides the center location for each solder pad on the CYBLE-2X20XX-X1. All dimensions reference the to the center of the
solder pad. Refer to Figure 6 for the location of each module solder pad.
Table 3. Module Solder Pad Location
Figure 6. Solder Pad Reference Location
Solder Pad
(Center of Pad)
Location (X,Y) from
Orign (mm)
Dimension from
Orign (mils)
(0.38, 10.54)
(14.96, 414.96)
(0.38, 11.81)
(14.96, 464.96)
(0.38, 13.08)
(14.96, 514.96)
(0.38, 14.35)
(14.96, 564.96)
(0.38, 15.62)
(14.96, 614.96)
(0.38, 16.89)
(14.96, 664.96)
(0.38, 18.16)
(14.96, 714.96)
(0.38, 19.43)
(14.96, 764.96)
(0.38, 20.70)
(14.96, 814.96)
10
(0.38, 21.97)
(14.96, 864.96)
11
(2.32, 22.62)
(91.34, 890.55)
12
(3.59, 22.62)
(141.34, 890.55)
13
(4.86, 22.62)
(191.34, 890.55)
14
(6.13, 22.62)
(241.34, 890.55)
15
(7.40, 22.62)
(291.34, 890.55)
16
(8.67, 22.62)
(341.34, 890.55)
17
(9.94, 22.62)
(391.34,8 90.55)
18
(11.21, 22.62)
(441.34, 890.55)
19
(12.48, 22.62)
(491.34, 890.55)
20
(13.75, 22.62)
(541.34, 890.55
21
(14.62, 20.70)
(575.59, 814.96)
22
(14.62, 19.43)
(575.59, 764.96)
23
(14.62, 18.16)
(575.59, 714.96)
24
(14.62, 16.89)
(575.59, 664.96)
25
(14.62, 15.62)
(575.59, 614.96)
26
(14.62, 14.35)
(575.59, 564.96)
27
(14.62, 13.08)
(575.59, 514.96)
28
(14.62, 11.81)
(575.59, 464.96)
29
See Figure 2
See Figure 2
30
See Figure 2
See Figure 2
Document Number: 002-15631 Rev.PRELIMINARY
Page 8 of 38
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
PRELIMINARY
Table 4 details the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on
CYBLE-2X20XX-X1, the BLE device port-pin, and denotes whether the function shown is available for each solder pad. Each
connection is configurable for a single option shown with a 3.
Table 4. Solder Pad Connection Definitions
Solder Pad Device
Number Port Pin
UART
SPI
I2 C
CapSense
TCPWM[2]
GND
Ground Connection
XRES
External Reset Hardware Connection Input
P4.0[3]
P3.7
P3.6
P3.5
P3.4
VREF
P2.6
10
P2.4
11
P2.3
12
P2.2
13
P2.0
14
P1.7
15
P1.6
16
P1.5
17
P1.4
18
P0.7
19
P1.0
20
P0.4
21
P0.5
3(SCB1_RTS) 3(SCB1_MOSI)
3(SCB1_CTS)
3(SCB1_RTS)
3(SCB1_TX)
3(SCB1_SCL)
3(SCB1_RX)
3(SCB1_SDA)
3(TCPWM0_P)
3(TCPWM3_N)
3(TCPWM3_P)
3(TCPWM2_N)
3(TCPWM2_P)
WCO ECO LCD
Out Out
3(CMOD)
3(Sensor) 3
3(Sensor)
3(Sensor)
3(Sensor)
SWD
GPIO
3 3(SWDCLK)
3(SWDIO)
Reference Voltage Input (Optional)
3(SCB0_CTS)
3(SCB0_RTS)
3(SCB0_TX)
3(SCB0_RX)
3(SCB0_CTS)
3(SCB0_SS3)
3(SCB0_SS1)
3(SCB0_SCLK
3(SCB0_SS0)
3(SCB0_MISO) 3(SCB0_SCL)
3(SCB0_MOSI) 3(SCB0_SDA)
3(SCB0_SCLK
3(SCB0_RX) 3(SCB0_MOSI) 3(SCB0_SDA)
3(SCB0_TX) 3(SCB0_MISO) 3(SCB0_SCL)
3(TCPWM3_N)
3(TCPWM3_P)
3(TCPWM2_N)
3(TCPWM2_P)
3(TCPWM2_N)
3(TCPWM0_P)
3(TCPWM1_P)
3(TCPWM1_N)
3(Sensor)
3(Sensor)
3(Sensor) 3
3(Sensor)
3(Sensor)
3(Sensor)
3(Sensor)
3(Sensor)
3(Sensor)
3(Sensor)
3(Sensor)
3(Sensor)
3(Sensor)
22
VDD
23
P0.6
24
GND[4]
Ground Connection
25
GND
Ground Connection
26
GND
Ground Connection
27
GND
Ground Connection
28
VDDR
Radio Power Supply (2V to 3.6V)
29
ANT
RF Pin to External Antenna
30
GND
Ground Connection
Digital Power Supply Input (1.8 to 5.5V)
3(SCB0_RTS) 3(SCB0_SS0)
3(TCPWM2_P) 3(Sensor)
Notes
2. TCPWM: Timer, Counter, and Pulse Width Modulator. If supported, the pad can be configured to any of these peripheral functions.
3. When using the capacitive sensing functionality, Pad 3 (P4.0) must be connected to a CMOD capacitor (located off of Cypress BLE Module). The value of this
capacitor is 2.2 nF and should be placed as close to the module as possible.
4. The main board needs to connect all GND connections (Pad 24/25/26/27) on the module to the common ground of the system.
5. If the I2S feature is used in the design, the I2S pins shall be dynamically routed to the appropriate available GPIO by PSoC Creator.
Document Number: 002-15631 Rev.PRELIMINARY
Page 9 of 38
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
PRELIMINARY
Power Supply Connections and Recommended External Components
Power Connections
External Component Recommendation
The CYBLE-2X20XX-X1 contains two power supply connections, VDD and VDDR. The VDD connection supplies power for
both digital and analog device operation. The VDDR connection
supplies power for the device radio.
In either connection scenario, it is recommended to place an
external ferrite bead between the supply and the module
connection. The ferrite bead should be positioned as close as
possible to the module pin connection.
VDD accepts a supply range of 1.71 V to 5.5 V. VDDR accepts
a supply range of 2.0V to 3.6V. These specifications can be
found in Table 12. The maximum power supply ripple for both
power connections on the module is 100 mV, as shown in
Table 10.
Figure 7 details the recommended host schematic options for a
single supply scenario. The use of one or two ferrite beads will
depend on the specific application and configuration of the
CYBLE-2X20XX-X1.
The power supply ramp rate of VDD must be equal to or greater
than that of VDDR.
Connection Options
Figure 8 details the recommended host schematic for an
independent supply scenario.
The recommended ferrite bead value is 330 Ω, 100 MHz. (Murata
BLM21PG331SN1D).
Two connection options are available for any application:
1. Single supply: Connect VDD and VDDR to the same supply.
2. Independent supply: Power VDD and VDDR separately.
Figure 7. Recommended Host Schematic Options for a Single Supply Option
Single Ferrite Bead Option
Document Number: 002-15631 Rev.PRELIMINARY
Two Ferrite Bead Option
Page 10 of 38
PRELIMINARY
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Figure 8. Recommended Host Schematic for an Independent Supply Option
Document Number: 002-15631 Rev.PRELIMINARY
Page 11 of 38
PRELIMINARY
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
The CYBLE-2X20XX-X1 schematic is shown in Figure 9.
Figure 9. CYBLE-2X20XX-X1 Schematic Diagram
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Page 12 of 38
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
PRELIMINARY
Electrical Specification
Table 10 details the absolute maximum electrical characteristics for the Cypress BLE module.
Table 10. CYBLE-2X20XX-X1 Absolute Maximum Ratings
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VDDD_ABS
Analog, digital, or radio supply relative to VSS
(VSSD = VSSA)
–0.5
–
Absolute maximum
VCCD_ABS
Direct digital core voltage input relative to VSSD
–0.5
–
1.95
Absolute maximum
VDD_RIPPLE
Maximum power supply ripple for VDD and VDDR
input voltage
–
–
100
mV
VGPIO_ABS
GPIO voltage
–0.5
–
VDD +0.5
Absolute maximum
IGPIO_ABS
Maximum current per GPIO
–25
–
25
mA
Absolute maximum
IGPIO_injection
GPIO injection current: Maximum for VIH > VDD
and minimum for VIL < VSS
–0.5
–
0.5
mA
Absolute maximum current
injected per pin
LU
Pin current for latch up
–200
200
mA
–
Max
Units
Details/Conditions
7.5
dBm
Configurable via register
settings (CYBLE-212006-01)
–93
–
dBm
Measured value
(CYBLE-212006-01)
3.0V supply
Ripple frequency of 100 kHz
to 750 kHz
Table 11 details the RF characteristics for the Cypress BLE module.
Table 11. CYBLE-2X20XX-X1 RF Performance Characteristics
Parameter
Description
Min
RFO
RF output power on ANT
RXS
RF receive sensitivity on ANT
–
Typ
FR
Module frequency range
2402
–
2480
MHz
–
GP
Peak gain
–
–0.5
–
dBi
–
RL
Return loss
–
–10
–
dB
–
Table 12 through Table 51 list the module level electrical characteristics for the CYBLE-2X20XX-X1. All specifications are valid for
–40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.
Table 12. CYBLE-2X20XX-X1 DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VDD1
Power supply input voltage
1.8
–
5.5
With regulator enabled
VDD2
Power supply input voltage unregulated
1.71
1.8
1.89
Internally unregulated
supply
VDDR1
Radio supply voltage (radio on)
2.0
–
3.6
Restricted by RFX2401C
VDDR2
Radio supply voltage (radio off)
2.0
–
3.6
–
Active Mode, VDD = 1.71 V to 5.5 V
IDD3
Execute from flash; CPU at 3 MHz
–
1.7
–
mA
T = 25 °C,
VDD = 3.3 V
IDD4
Execute from flash; CPU at 3 MHz
–
–
–
mA
T = –40 °C to 85 °C
IDD5
Execute from flash; CPU at 6 MHz
–
2.5
–
mA
T = 25 °C,
VDD = 3.3 V
IDD6
Execute from flash; CPU at 6 MHz
–
–
–
mA
T = –40 °C to 85 °C
IDD7
Execute from flash; CPU at 12 MHz
–
–
mA
T = 25 °C,
VDD = 3.3 V
IDD8
Execute from flash; CPU at 12 MHz
–
–
–
mA
T = –40 °C to 85 °C
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PRELIMINARY
Table 12. CYBLE-2X20XX-X1 DC Specifications (continued)
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
T = 25 °C,
VDD = 3.3 V
IDD9
Execute from flash; CPU at 24 MHz
–
7.1
–
mA
IDD10
Execute from flash; CPU at 24 MHz
–
–
–
mA
T = –40 °C to 85 °C
IDD11
Execute from flash; CPU at 48 MHz
–
13.4
–
mA
T = 25 °C,
VDD = 3.3 V
IDD12
Execute from flash; CPU at 48 MHz
–
–
–
mA
T = –40 °C to 85 °C
–
–
–
mA
T = 25 °C, VDD = 3.3 V,
SYSCLK = 3 MHz
–
–
–
mA
T = 25 °C, VDD = 3.3 V,
SYSCLK = 3 MHz
T = 25 °C,
VDD = 3.3 V
Sleep Mode, VDD = 1.8 to 5.5 V
IDD13
IMO on
Sleep Mode, VDD and VDDR = 1.9 to 5.5 V
IDD14
ECO on
Deep-Sleep Mode, VDD = 1.8 to 3.6 V
IDD15
WDT with WCO on
–
1.5
–
μA
IDD16
WDT with WCO on
–
–
–
μA
IDD17
WDT with WCO on
–
–
–
μA
IDD18
WDT with WCO on
–
–
–
μA
Deep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)
IDD19
WDT with WCO on
–
–
–
IDD20
WDT with WCO on
–
–
–
μA
μA
T = –40 °C to 85 °C
T = 25 °C,
VDD = 5 V
T = –40 °C to 85 °C
T = 25 °C
T = –40 °C to 85 °C
Hibernate Mode, VDD = 1.8 to 3.6 V
IDD27
GPIO and reset active
–
150
–
nA
T = 25 °C,
VDD = 3.3 V
IDD28
GPIO and reset active
–
–
–
nA
T = –40 °C to 85 °C
Hibernate Mode, VDD = 3.6 to 5.5 V
IDD29
GPIO and reset active
–
–
–
nA
T = 25 °C,
VDD = 5 V
IDD30
GPIO and reset active
–
–
–
nA
T = –40 °C to 85 °C
Stop Mode, VDD = 1.8 to 3.6 V
IDD33
Stop-mode current (VDD)
–
20
–
nA
T = 25 °C,
VDD = 3.3 V
IDD34
Stop-mode current (VDDR)
–
40
–-
nA
T = 25 °C,
VDDR = 3.3 V
IDD35
Stop-mode current (VDD)
–
–
–
nA
T = –40 °C to 85 °C
IDD36
Stop-mode current (VDDR)
–
–
–
nA
T = –40 °C to 85 °C,
VDDR = 1.9 V to 3.6 V
Stop Mode, VDD = 3.6 to 5.5 V
IDD37
Stop-mode current (VDD)
–
–
–
nA
T = 25 °C,
VDD = 5 V
IDD38
Stop-mode current (VDDR)
–
–
–
nA
T = 25 °C,
VDDR = 5 V
IDD39
Stop-mode current (VDD)
–
–
–
nA
T = –40 °C to 85 °C
IDD40
Stop-mode current (VDDR)
–
–
–
nA
T = –40 °C to 85 °C
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Table 13. AC Specifications
Parameter
Description
Min
Typ
Max
Units
DC
–
48
MHz
Wakeup from Sleep mode
–
–
μs
TDEEPSLEEP
Wakeup from Deep-Sleep mode
–
–
25
μs
24-MHz IMO. Guaranteed by
characterization
THIBERNATE
Wakeup from Hibernate mode
–
–
ms
Guaranteed by characterization
TSTOP
Wakeup from Stop mode
–
–
ms
XRES wakeup
FCPU
CPU frequency
TSLEEP
Details/Conditions
1.71 V ≤ VDD ≤ 5.5 V
Guaranteed by characterization
GPIO
Table 14. GPIO DC Specifications
Parameter
VIH[6]
VIL
VOH
VOL
Min
Typ
Max
Units
Input voltage HIGH threshold
Description
0.7 × VDD
–
–
Details/Conditions
LVTTL input, VDD < 2.7 V
0.7 × VDD
–
–
–
LVTTL input, VDD ≥ 2.7 V
2.0
–
–
–
Input voltage LOW threshold
–
–
0.3 × VDD
LVTTL input, VDD < 2.7 V
–
–
0.3 × VDD
CMOS input
CMOS input
–
LVTTL input, VDD ≥ 2.7 V
–
–
0.8
Output voltage HIGH level
VDD –0.6
–
–
Output voltage HIGH level
VDD –0.5
–
–
IOH = 1 mA at 1.8-V VDD
Output voltage LOW level
–
–
0.6
IOL = 8 mA at 3.3-V VDD
Output voltage LOW level
–
–
0.6
IOL = 4 mA at 1.8-V VDD
Output voltage LOW level
–
–
0.4
IOL = 3 mA at 3.3-V VDD
–
IOH = 4 mA at 3.3-V VDD
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
–
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
kΩ
–
IIL
Input leakage current (absolute value)
–
–
nA
IIL_CTBM
Input leakage on CTBm input pins
–
–
nA
25 °C, VDD = 3.3 V
–
CIN
Input capacitance
–
–
pF
VHYSTTL
Input hysteresis LVTTL
25
40
–
mV
–
VHYSCMOS
Input hysteresis CMOS
0.05 × VDD
–
–
–
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
μA
–
ITOT_GPIO
Maximum total source or sink chip
current
–
–
200
mA
–
VDD > 2.7 V
Note
6. VIH must not exceed VDD + 0.2 V.
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PRELIMINARY
Table 15. GPIO AC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
TRISEF
Rise time in Fast-Strong mode
–
12
ns
3.3-V VDDD, CLOAD = 25 pF
TFALLF
Fall time in Fast-Strong mode
–
12
ns
3.3-V VDDD, CLOAD = 25 pF
TRISES
Rise time in Slow-Strong mode
10
–
60
ns
3.3-V VDDD, CLOAD = 25 pF
TFALLS
Fall time in Slow-Strong mode
10
–
60
ns
3.3-V VDDD, CLOAD = 25 pF
FGPIOUT1
GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V
Fast-Strong mode
–
–
33
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT2
GPIO Fout; 1.7 V≤ VDD ≤ 3.3 V
Fast-Strong mode
–
–
16.7
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT3
GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V
Slow-Strong mode
–
–
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT4
GPIO Fout; 1.7 V ≤ VDD ≤ 3.3 V
Slow-Strong mode
–
–
3.5
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOIN
GPIO input operating frequency
1.71 V ≤ VDD ≤ 5.5 V
–
–
48
MHz
90/10% VIO
Min
Typ
Max
Units
Table 16. OVT GPIO DC Specifications (P5_0 and P5_1 Only)
Parameter
Description
IIL
Input leakage (absolute value).
VIH > VDD
–
–
10
μA
VOL
Output voltage LOW level
–
–
0.4
Typ
Max
Units
Details/Conditions
25°C, VDD = 0 V, VIH = 3.0 V
IOL = 20 mA, VDD > 2.9 V
Table 17. OVT GPIO AC Specifications (P5_0 and P5_1 Only)
Parameter
Description
Min
Details/Conditions
TRISE_OVFS
Output rise time in Fast-Strong mode
1.5
–
12
ns
25-pF load, 10%–90%, VDD = 3.3 V
TFALL_OVFS
Output fall time in Fast-Strong mode
1.5
–
12
ns
25-pF load, 10%–90%, VDD = 3.3 V
TRISESS
Output rise time in Slow-Strong mode
10
–
60
ns
25 pF load, 10%-90%,
VDD = 3.3 V
TFALLSS
Output fall time in Slow-Strong mode
10
–
60
ns
25 pF load, 10%-90%,
VDD = 3.3 V
FGPIOUT1
GPIO FOUT; 3.3 V ≤ VDD ≤ 5.5 V
Fast-Strong mode
–
–
24
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT2
GPIO FOUT; 1.71 V ≤ VDD ≤ 3.3 V
Fast-Strong mode
–
–
16
MHz
90/10%, 25 pF load, 60/40 duty
cycle
XRES
Table 18. XRES DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VIH
Input voltage HIGH threshold
0.7 × VDDD
–
–
CMOS input
VIL
Input voltage LOW threshold
–
–
0.3 × VDDD
CMOS input
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
–
CIN
Input capacitance
–
–
pF
–
VHYSXRES
Input voltage hysteresis
–
100
–
mV
–
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
μA
–
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Table 19. XRES AC Specifications
Parameter
TRESETWIDTH
Description
Min
Typ
Max
Units
Details/Conditions
–
–
μs
–
Reset pulse width
Temperature Sensor
Table 20. Temperature Sensor Specifications
Parameter
TSENSACC
Description
Temperature-sensor accuracy
Min
–5
Typ
±1
Max
Units
°C
Details/Conditions
–40 °C to +85 °C
Details/Conditions
SAR ADC
Table 21. SAR ADC DC Specifications
Parameter
Description
Min
Typ
Max
Units
bits
A_RES
Resolution
–
–
12
A_CHNIS_S
Number of channels - single-ended
–
–
8 full-speed
A-CHNKS_D
Number of channels - differential
–
–
Diff inputs use
neighboring I/O
A-MONO
Monotonicity
–
–
–
Yes
A_GAINERR
Gain error
–
–
±0.1
A_OFFSET
Input offset voltage
–
–
mV
A_ISAR
Current consumption
–
–
mA
A_VINS
Input voltage range - single-ended
VSS
–
VDDA
A_VIND
Input voltage range - differential
VSS
–
VDDA
A_INRES
Input resistance
–
–
2.2
kΩ
A_INCAP
Input capacitance
–
–
10
pF
VREFSAR
Trimmed internal reference to SAR
–1
–
Min
Typ
Max
Units
With external
reference
Measured with 1-V
VREF
Percentage of Vbg
(1.024 V)
Table 22. SAR ADC AC Specifications
Parameter
Description
Details/Conditions
Measured at 1-V
reference
A_PSRR
Power-supply rejection ratio
70
–
–
dB
A_CMRR
Common-mode rejection ratio
66
–
–
dB
A_SAMP
Sample rate
–
–
Msps
Fsarintref
SAR operating speed without external ref.
bypass
–
–
100
Ksps
A_SNR
Signal-to-noise ratio (SNR)
65
–
–
dB
A_BW
Input bandwidth without aliasing
–
–
A_SAMP/2
kHz
A_INL
Integral nonlinearity. VDD = 1.71 V to 5.5 V,
1 Msps
–1.7
–
LSB
VREF = 1 V to VDD
A_INL
Integral nonlinearity. VDDD = 1.71 V to 3.6 V,
1 Msps
–1.5
–
1.7
LSB
VREF = 1.71 V to VDD
A_INL
Integral nonlinearity. VDD = 1.71 V to 5.5 V,
500 Ksps
–1.5
–
1.7
LSB
VREF = 1 V to VDD
A_dnl
Differential nonlinearity. VDD = 1.71 V to
5.5 V, 1 Msps
–1
–
2.2
LSB
VREF = 1 V to VDD
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12-bit resolution
FIN = 10 kHz
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Table 22. SAR ADC AC Specifications (continued)
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
A_DNL
Differential nonlinearity. VDD = 1.71 V to
3.6 V, 1 Msps
–1
–
LSB
VREF = 1.71 V to VDD
A_DNL
Differential nonlinearity. VDD = 1.71 V to
5.5 V, 500 Ksps
–1
–
2.2
LSB
VREF = 1 V to VDD
A_THD
Total harmonic distortion
–
–
–65
dB
Description
Min
Typ
Max
Units
Details/Conditions
VCSD
Voltage range of operation
1.71
–
5.5
–
IDAC1
DNL for 8-bit resolution
–1
–
LSB
–
IDAC1
INL for 8-bit resolution
–3
–
LSB
–
IDAC2
DNL for 7-bit resolution
–1
–
LSB
–
IDAC2
INL for 7-bit resolution
–3
–
LSB
SNR
Ratio of counts of finger to noise
–
–
Ratio
–
Capacitance range of
9 pF to 35 pF, 0.1-pF
sensitivity. Radio is not
operating during the
scan
IDAC1_CRT1
Output current of IDAC1 (8 bits) in High
range
–
612
–
μA
–
IDAC1_CRT2
Output current of IDAC1 (8 bits) in Low
range
–
306
–
μA
–
IDAC2_CRT1
Output current of IDAC2 (7 bits) in High
range
–
305
–
μA
–
IDAC2_CRT2
Output current of IDAC2 (7 bits) in Low
range
–
153
–
μA
–
FIN = 10 kHz
CSD
CSD Block Specifications
Parameter
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Digital Peripherals
Timer
Table 23. Timer DC Specifications
Parameter
ITIM1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
42
Units
μA
ITIM2
Block current consumption at 12 MHz
–
–
130
ITIM3
Block current consumption at 48 MHz
–
–
535
μA
μA
Min
FCLK
Typ
–
Max
48
Units
MHz
Details/Conditions
16-bit timer
16-bit timer
16-bit timer
Table 24. Timer AC Specifications
Parameter
TTIMFREQ
Description
Operating frequency
TCAPWINT
Capture pulse width (internal)
2 × TCLK
–
–
ns
TCAPWEXT
Capture pulse width (external)
2 × TCLK
–
–
ns
TTIMRES
Timer resolution
TCLK
–
–
ns
TTENWIDINT
Enable pulse width (internal)
2 × TCLK
–
–
ns
TTENWIDEXT
Enable pulse width (external)
2 × TCLK
–
–
ns
TTIMRESWINT
Reset pulse width (internal)
2 × TCLK
–
–
ns
TTIMRESEXT
Reset pulse width (external)
2 × TCLK
–
–
ns
Units
μA
Details/Conditions
Counter
Table 25. Counter DC Specifications
Parameter
ICTR1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
42
ICTR2
Block current consumption at 12 MHz
–
–
130
ICTR3
Block current consumption at 48 MHz
–
–
535
μA
μA
Details/Conditions
16-bit counter
16-bit counter
16-bit counter
Table 26. Counter AC Specifications
Parameter
TCTRFREQ
Description
Operating frequency
Min
FCLK
Typ
–
Max
48
Units
MHz
Details/Conditions
–
TCTRPWINT
Capture pulse width (internal)
2 × TCLK
–
–
ns
–
TCTRPWEXT
Capture pulse width (external)
2 × TCLK
–
–
ns
–
TCTRES
Counter Resolution
TCLK
–
–
ns
–
TCENWIDINT
Enable pulse width (internal)
2 × TCLK
–
–
ns
–
TCENWIDEXT
Enable pulse width (external)
2 × TCLK
–
–
ns
–
TCTRRESWINT
Reset pulse width (internal)
2 × TCLK
–
–
ns
–
TCTRRESWEXT
Reset pulse width (external)
2 × TCLK
–
–
ns
–
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Pulse Width Modulation (PWM)
Table 27. PWM DC Specifications
Parameter
Description
Min
Typ
Max
Units
μA
μA
μA
Details/Conditions
IPWM1
Block current consumption at 3 MHz
–
–
42
IPWM2
Block current consumption at 12 MHz
–
–
130
16-bit PWM
IPWM3
Block current consumption at 48 MHz
–
–
535
Min
Typ
Max
Units
Details/Conditions
16-bit PWM
16-bit PWM
Table 28. PWM AC Specifications
Parameter
Description
TPWMFREQ
Operating frequency
FCLK
–
48
MHz
–
TPWMPWINT
Pulse width (internal)
2 × TCLK
–
–
ns
–
TPWMEXT
Pulse width (external)
2 × TCLK
–
–
ns
–
TPWMKILLINT
Kill pulse width (internal)
2 × TCLK
–
–
ns
–
TPWMKILLEXT
Kill pulse width (external)
2 × TCLK
–
–
ns
–
TPWMEINT
Enable pulse width (internal)
2 × TCLK
–
–
ns
–
TPWMENEXT
Enable pulse width (external)
2 × TCLK
–
–
ns
–
TPWMRESWINT
Reset pulse width (internal)
2 × TCLK
–
–
ns
–
TPWMRESWEXT
Reset pulse width (external)
2 × TCLK
–
–
ns
–
LCD Direct Drive
Table 29. LCD Direct Drive DC Specifications
Parameter
ILCDLOW
Description
Operating current in low-power mode
Min
Typ
Max
Units
–
17.5
–
μA
Details/Conditions
16 × 4 small segment
display at 50 Hz
–
500
5000
pF
–
LCDOFFSET
LCD capacitance per segment/common
driver
Long-term segment offset
–
20
–
mV
ILCDOP1
LCD system operating current, VBIAS = 5 V
–
–
mA
ILCDOP2
LCD system operating current, VBIAS = 3.3 V
–
–
mA
–
32 × 4 segments. 50 Hz at
25 °C
32 × 4 segments
50 Hz at 25 °C
Min
10
Typ
50
Max
150
Units
Hz
CLCDCAP
Table 30. LCD Direct Drive AC Specifications
Parameter
FLCD
Description
LCD frame rate
Document Number: 002-15631 Rev.PRELIMINARY
Details/Conditions
–
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Serial Communication
Table 31. Fixed I2C DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
–
–
50
–
1.4
μA
μA
μA
μA
Typ
Max
Units
Details/Conditions
–
400
kHz
II2C1
Block current consumption at 100 kHz
II2C2
Block current consumption at 400 kHz
–
–
155
II2C3
Block current consumption at 1 Mbps
–
–
390
–
–
Min
–
I C enabled in Deep-Sleep mode
II2C4
–
–
–
Table 32. Fixed I2C AC Specifications
Parameter
FI2C1
Description
Bit rate
Table 33. Fixed UART DC Specifications
Description
Min
Typ
Max
Units
Details/Conditions
IUART1
Parameter
Block current consumption at 100 kbps
–
–
55
–
IUART2
Block current consumption at 1000 kbps
–
–
312
μA
μA
Min
Typ
Max
Units
Details/Conditions
–
–
Mbps
–
–
Table 34. Fixed UART AC Specifications
Parameter
FUART
Description
Bit rate
Table 35. Fixed SPI DC Specifications
Min
Typ
Max
Units
Details/Conditions
ISPI1
Parameter
Block current consumption at 1 Mbps
Description
–
–
360
–
ISPI2
Block current consumption at 4 Mbps
–
–
560
ISPI3
Block current consumption at 8 Mbps
–
–
600
μA
μA
μA
–
–
Table 36. Fixed SPI AC Specifications
Parameter
FSPI
Description
Min
Typ
Max
Units
Details/Conditions
SPI operating frequency (master; 6x over sampling)
–
–
MHz
–
Table 37. Fixed SPI Master Mode AC Specifications
Min
Typ
Max
Units
Details/Conditions
TDMO
Parameter
MOSI valid after SCLK driving edge
Description
–
–
18
ns
–
TDSI
MISO valid before SCLK capturing edge
Full clock, late MISO sampling used
20
–
–
ns
Full clock, late MISO sampling
THMO
Previous MOSI data hold time
–
–
ns
Referred to Slave capturing edge
Table 38. Fixed SPI Slave Mode AC Specifications
Parameter
Description
Min
Typ
Max
Units
TDMI
MOSI valid before SCLK capturing edge
40
–
–
ns
TDSO
MISO valid after SCLK driving edge
–
–
42 + 3 × TCPU
ns
TDSO_ext
MISO Valid after SCLK driving edge in
external clock mode. VDD < 3.0 V
–
–
50
ns
THSO
Previous MISO data hold time
TSSELSCK
SSEL valid to first SCK valid edge
Document Number: 002-15631 Rev.PRELIMINARY
–
–
ns
100
–
–
ns
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Memory
Table 39. Flash DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
1.71
–
5.5
–
Number of Wait states at 32–48 MHz
–
–
CPU execution from flash
Number of Wait states at 16–32 MHz
–
–
CPU execution from flash
Number of Wait states for 0–16 MHz
–
–
CPU execution from flash
Min
Typ
Max
VPE
Erase and program voltage
TWS48
TWS32
TWS16
Table 40. Flash AC Specifications
Parameter
Description
Units
Details/Conditions
TROWWRITE[7]
TROWERASE[7]
Row (block) write time (erase and program)
–
–
20
ms
Row erase time
–
–
13
ms
–
TROWPROGRAM[7]
TBULKERASE[7]
TDEVPROG[7]
Row program time after erase
–
–
ms
–
Bulk erase time (256 KB)
–
–
35
ms
–
–
–
25
seconds
–
FEND
Flash endurance
100 K
–
–
cycles
–
FRET
Flash retention. TA ≤ 55 °C, 100 K P/E cycles
20
–
–
years
–
FRET2
Flash retention. TA ≤ 85 °C, 10 K P/E cycles
10
–
–
years
–
Min
Typ
Max
Units
Details/Conditions
Total device program time
Row (block) = 256 bytes
System Resources
Power-on-Reset (POR)
Table 41. POR DC Specifications
Parameter
Description
VRISEIPOR
Rising trip voltage
0.80
–
1.45
–
VFALLIPOR
Falling trip voltage
0.75
–
1.40
–
VIPORHYST
Hysteresis
15
–
200
mV
–
Min
Typ
Max
Units
Details/Conditions
–
–
μs
–
Table 42. POR AC Specifications
Parameter
TPPOR_TR
Description
Precision power-on reset (PPOR) response
time in Active and Sleep modes
Table 43. Brown-Out Detect
Description
Min
Typ
Max
Units
Details/Conditions
VFALLPPOR
Parameter
BOD trip voltage in Active and Sleep modes
1.64
–
–
–
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.4
–
–
–
Table 44. Hibernate Reset
Parameter
VHBRTRIP
Description
BOD trip voltage in Hibernate
Min
Typ
Max
Units
Details/Conditions
1.1
–
–
–
Note
7. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have
completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make
certain that these are not inadvertently activated.
Document Number: 002-15631 Rev.PRELIMINARY
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PRELIMINARY
Voltage Monitors (LVD)
Table 45. Voltage Monitor DC Specifications
Parameter
VLVI1
Description
LVI_A/D_SEL[3:0] = 0000b
Min
1.71
Typ
1.75
Max
1.79
Units
Details/Conditions
–
VLVI2
LVI_A/D_SEL[3:0] = 0001b
1.76
1.80
1.85
–
VLVI3
LVI_A/D_SEL[3:0] = 0010b
1.85
1.90
1.95
–
VLVI4
LVI_A/D_SEL[3:0] = 0011b
1.95
2.00
2.05
–
VLVI5
LVI_A/D_SEL[3:0] = 0100b
2.05
2.10
2.15
–
VLVI6
LVI_A/D_SEL[3:0] = 0101b
2.15
2.20
2.26
–
VLVI7
LVI_A/D_SEL[3:0] = 0110b
2.24
2.30
2.36
–
VLVI8
LVI_A/D_SEL[3:0] = 0111b
2.34
2.40
2.46
–
VLVI9
LVI_A/D_SEL[3:0] = 1000b
2.44
2.50
2.56
–
VLVI10
LVI_A/D_SEL[3:0] = 1001b
2.54
2.60
2.67
–
VLVI11
LVI_A/D_SEL[3:0] = 1010b
2.63
2.70
2.77
–
VLVI12
LVI_A/D_SEL[3:0] = 1011b
2.73
2.80
2.87
–
VLVI13
LVI_A/D_SEL[3:0] = 1100b
2.83
2.90
2.97
–
VLVI14
LVI_A/D_SEL[3:0] = 1101b
2.93
3.00
3.08
–
VLVI15
LVI_A/D_SEL[3:0] = 1110b
3.12
3.20
3.28
–
VLVI16
LVI_A/D_SEL[3:0] = 1111b
4.39
4.50
4.61
–
LVI_IDD
Block current
–
–
100
μA
–
Min
Typ
Max
Units
Details/Conditions
–
–
μs
–
Min
Typ
Max
Units
Details/Conditions
–
–
14
MHz
SWDCLK ≤ 1/3 CPU clock frequency
Table 46. Voltage Monitor AC Specifications
Parameter
TMONTRIP
Description
Voltage monitor trip time
SWD Interface
Table 47. SWD Interface Specifications
Parameter
Description
F_SWDCLK1
3.3 V ≤ VDD ≤ 5.5 V
F_SWDCLK2
1.71 V ≤ VDD ≤ 3.3 V
–
–
MHz
SWDCLK ≤ 1/3 CPU clock frequency
T_SWDI_SETUP T = 1/f SWDCLK
0.25 × T
–
–
ns
–
T_SWDI_HOLD
0.25 × T
–
–
ns
–
T_SWDO_VALID T = 1/f SWDCLK
T = 1/f SWDCLK
–
–
0.5 × T
ns
–
T_SWDO_HOLD
–
–
ns
–
T = 1/f SWDCLK
Document Number: 002-15631 Rev.PRELIMINARY
Page 24 of 38
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
PRELIMINARY
Internal Main Oscillator
Table 48. IMO DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
–
IIMO1
IMO operating current at 48 MHz
–
–
1000
IIMO2
IMO operating current at 24 MHz
–
–
325
IIMO3
IMO operating current at 12 MHz
–
–
225
IIMO4
IMO operating current at 6 MHz
–
–
180
IIMO5
IMO operating current at 3 MHz
–
–
150
μA
μA
μA
μA
μA
–
–
–
–
Table 49. IMO AC Specifications
Min
Typ
Max
Units
FIMOTOL3
Parameter
Frequency variation from 3 to 48 MHz
Description
–
–
±2
Details/Conditions
FIMOTOL3
IMO startup time
–
12
–
μs
–
Min
Typ
Max
Units
Details/Conditions
–
0.3
1.05
μA
–
With API-called calibration
Internal Low-Speed Oscillator
Table 50. ILO DC Specifications
Parameter
IILO2
Description
ILO operating current at 32 kHz
Table 51. ILO AC Specifications
Min
Typ
Max
Units
Details/Conditions
TSTARTILO1
Parameter
ILO startup time
Description
–
–
ms
–
FILOTRIM1
32-kHz trimmed frequency
15
32
50
kHz
–
Table 52. ECO Trim Value Specification
Parameter
ECOTRIM
Description
24-MHz trim value
(firmware configuration)
Value
Details/Conditions
0x00007FDC
Optimum trim value that needs to be loaded to register
CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG
BLE Subsystem
Table 53. BLE Subsystem
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
RX sensitivity with idle transmitter
–
–89
–
dBm
–
RX sensitivity with idle transmitter
excluding Balun loss
–
–91
–
dBm
Guaranteed by design
simulation
RXS, DIRTY
RX sensitivity with dirty transmitter
–
–87
–70
dBm
RF-PHY Specification
(RCV-LE/CA/01/C)
RXS, HIGHGAIN
RX sensitivity in high-gain mode with idle
transmitter
–
–91
–
dBm
PRXMAX
Maximum input power
–10
–1
–
dBm
RF-PHY Specification
(RCV-LE/CA/06/C)
CI1
Cochannel interference,
Wanted signal at –67 dBm and Interferer
at FRX
–
21
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
RF Receiver Specification
RXS, IDLE
Document Number: 002-15631 Rev.PRELIMINARY
–
Page 25 of 38
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
PRELIMINARY
Table 53. BLE Subsystem (continued)
Parameter
Description
Min
Typ
Max
Units
CI2
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at FRX ±1 MHz
Details/Conditions
–
15
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
CI3
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at FRX ±2 MHz
–
–29
–
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
CI4
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at ≥FRX ±3 MHz
–
–39
–
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
CI5
Adjacent channel interference
Wanted Signal at –67 dBm and Interferer
at Image frequency (FIMAGE)
–
–20
–
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
CI3
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at Image frequency (FIMAGE ± 1 MHz)
–
–30
–
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
OBB1
Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 30–2000 MHz
–30
–27
–
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
OBB2
Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 2003–2399 MHz
–35
–27
–
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
OBB3
Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 2484–2997 MHz
–35
–27
–
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
OBB4
Out-of-band blocking,
Wanted signal a –67 dBm and Interferer
at F = 3000–12750 MHz
–30
–27
–
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
IMD
Inter modulation performance
Wanted signal at –64 dBm and 1-Mbps
BLE, third, fourth, and fifth offset channel
–50
–
–
dBm
RF-PHY Specification
(RCV-LE/CA/05/C)
RXSE1
Receiver spurious emission
30 MHz to 1.0 GHz
–
–
–57
dBm
100-kHz measurement
bandwidth
ETSI EN300 328 V1.8.1
RXSE2
Receiver spurious emission
1.0 GHz to 12.75 GHz
–
–
–47
dBm
1-MHz measurement
bandwidth
ETSI EN300 328 V1.8.1
RF Transmitter Specifications
TXP, ACC
RF power accuracy
–
±1
–
dB
–
TXP, RANGE
RF power control range
–
20
–
dB
–
TXP, 0dBm
Output power, 0-dB Gain setting (PA7)
–
–
dBm
–
TXP, MAX
Output power, maximum power setting
(PA10)
–
–
dBm
–
TXP, MIN
Output power, minimum power setting
(PA1)
–
–18
–
dBm
–
F2AVG
Average frequency deviation for
10101010 pattern
185
–
–
kHz
RF-PHY Specification
(TRM-LE/CA/05/C)
F1AVG
Average frequency deviation for
11110000 pattern
225
250
275
kHz
RF-PHY Specification
(TRM-LE/CA/05/C)
Document Number: 002-15631 Rev.PRELIMINARY
Page 26 of 38
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
PRELIMINARY
Table 53. BLE Subsystem (continued)
Parameter
Description
EO
Eye opening = ΔF2AVG/ΔF1AVG
FTX, ACC
Min
Typ
Max
Units
Details/Conditions
RF-PHY Specification
(TRM-LE/CA/05/C)
0.8
–
–
Frequency accuracy
–150
–
150
kHz
RF-PHY Specification
(TRM-LE/CA/06/C)
FTX, MAXDR
Maximum frequency drift
–50
–
50
kHz
RF-PHY Specification
(TRM-LE/CA/06/C)
FTX, INITDR
Initial frequency drift
–20
–
20
kHz
RF-PHY Specification
(TRM-LE/CA/06/C)
FTX, DR
Maximum drift rate
–20
–
20
kHz/
50 μs
RF-PHY Specification
(TRM-LE/CA/06/C)
IBSE1
In-band spurious emission at 2-MHz
offset
–
–
–20
dBm
RF-PHY Specification
(TRM-LE/CA/03/C)
IBSE2
In-band spurious emission at ≥3-MHz
offset
–
–
-30
dBm
RF-PHY Specification
(TRM-LE/CA/03/C)
TXSE1
Transmitter spurious emissions
(average), <1.0 GHz
–
–
-55.5
dBm
FCC-15.247
TXSE2
Transmitter spurious emissions
(average), >1.0 GHz
–
–
-41.5
dBm
FCC-15.247
RF Current Specifications
IRX
Receive current in normal mode
–
18.7
–
mA
–
IRX_RF
Radio receive current in normal mode
–
16.4
–
mA
IRX, HIGHGAIN
Receive current in high-gain mode
–
21.5
–
mA
–
ITX, 3dBm
TX current at 3-dBm setting (PA10)
–
20
–
mA
–
ITX, 0dBm
TX current at 0-dBm setting (PA7)
–
16.5
–
mA
–
ITX_RF, 0dBm
Radio TX current at 0 dBm setting (PA7)
–
15.6
–
mA
Measured at VDDR
ITX_RF, 0dBm
Radio TX current at 0 dBm excluding
Balun loss
–
14.2
–
mA
Guaranteed by design
simulation
ITX,-3dBm
TX current at –3-dBm setting (PA4)
–
15.5
–
mA
–
ITX,-6dBm
TX current at –6-dBm setting (PA3)
–
14.5
–
mA
–
ITX,-12dBm
TX current at –12-dBm setting (PA2)
–
13.2
–
mA
–
ITX,-18dBm
TX current at –18-dBm setting (PA1)
–
12.5
–
mA
–
Iavg_1sec, 0dBm
Average current at 1-second BLE
connection interval
–
17.1
–
μA
TXP: 0 dBm; ±20-ppm
master and slave clock
accuracy.
For empty PDU exchange
Iavg_4sec, 0dBm
Average current at 4-second BLE
connection interval
Measured at VDDR
–
6.1
–
μA
TXP: 0 dBm; ±20-ppm
master and slave clock
accuracy.
For empty PDU exchange
2400
–
2482
MHz
–
General RF Specifications
FREQ
RF operating frequency
CHBW
Channel spacing
–
–
MHz
–
DR
On-air data rate
–
1000
–
kbps
–
Document Number: 002-15631 Rev.PRELIMINARY
Page 27 of 38
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
PRELIMINARY
Table 53. BLE Subsystem (continued)
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
–
IDLE2TX
BLE.IDLE to BLE. TX transition time
–
120
140
IDLE2RX
BLE.IDLE to BLE. RX transition time
–
75
120
μs
μs
RSSI, ACC
RSSI accuracy
–
±5
–
dB
–
RSSI, RES
RSSI resolution
–
–
dB
–
RSSI, PER
RSSI sample period
–
–
μs
–
–
RSSI Specifications
Document Number: 002-15631 Rev.PRELIMINARY
Page 28 of 38
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
PRELIMINARY
Environmental Specifications
Environmental Compliance
This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF)
directives. The Cypress module and components used to produce this module are RoHS and HF compliant.
RF Certification
The CYBLE-212006-01 and CYBLE-202007-01 modules will be certified under the following RF certification standards at production
release.
FCC: WAP2006
CE
IC: 7922A-2006
MIC: TBD
KC: TBD
Safety Certification
The CYBLE-212006-01 and CYBLE-202007-01 modules comply with the following regulations:
Underwriters Laboratories, Inc. (UL) - Filing E331901
CSA
TUV
Environmental Conditions
Table 54 describes the operating and storage conditions for the Cypress BLE module.
Table 54. Environmental Conditions for CYBLE-2X20XX-X1
Description
Operating temperature
Operating humidity (relative, non-condensation)
Thermal ramp rate
Minimum Specification
Maximum Specification
–40 °C
85 °C
5%
85%
–
3 °C/minute
–40 °C
85 °C
Storage temperature and humidity
–
85 ° C at 85%
ESD: Module integrated into system Components[8]
–
15 kV Air
2.2 kV Contact
Storage temperature
ESD and EMI Protection
Exposed components require special attention to ESD and electromagnetic interference (EMI).
A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure
near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground.
Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.
Note
8. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.
Document Number: 002-15631 Rev.PRELIMINARY
Page 29 of 38
RF Exposure distance of the device is 15mm.
RF Exposure distance of the device is 15mm.
la distance d'exposition RF de l'appareil est de 15mm.
PRELIMINARY
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
MIC Japan
CYBLE-212006-01 and CYBLE-202007-01 are certified as a module with type certification number TBD. End products that integrate
CYBLE-212006-01 and CYBLE-202007-01 do not need additional MIC Japan certification for the end product.
End product can display the certification label of the embedded module.
KC Korea
CYBLE-212006-01 and CYBLE-202007-01 are certified for use in Korea with certificate number TBD.
Document Number: 002-15631 Rev.PRELIMINARY
Page 32 of 38
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
PRELIMINARY
Packaging
Table 55. Solder Reflow Peak Temperature
Module Part Number
Package
Maximum Peak Temperature
Maximum Time at Peak
Temperature
No. of Cycles
CYBLE-2X20XX-X1
30-pad SMT
260 °C
30 seconds
Table 56. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Module Part Number
Package
MSL
CYBLE-2X20XX-X1
30-pad SMT
MSL 3
The CYBLE-2X20XX-X1 is offered in tape and reel packaging. Figure 10 details the tape dimensions used for the CYBLE-2X20XX-X1.
Figure 10. CYBLE-2X20XX-X1 Tape Dimensions
Figure 11 details the orientation of the CYBLE-2X20XX-X1 in the tape as well as the direction for unreeling.
Figure 11. Component Orientation in Tape and Unreeling Direction (Illustration Only) - TBD
Document Number: 002-15631 Rev.PRELIMINARY
Page 33 of 38
PRELIMINARY
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Figure 12 details reel dimensions used for the CYBLE-2X20XX-X1.
Figure 12. Reel Dimensions
The CYBLE-2X20XX-X1 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The
center-of-mass for the CYBLE-2X20XX-X1 is detailed in Figure 13.
Figure 13. CYBLE-2X20XX-X1 Center of Mass (Seen from Top) - TBD
Document Number: 002-15631 Rev.PRELIMINARY
Page 34 of 38
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
PRELIMINARY
Ordering Information
Table 57 lists the CYBLE-2X20XX-X1 part numbers and features.
Table 57. Ordering Information
Part Number
CPU
Speed
(MHz)
Flash
Size
(KB)
CYBLE-212006-01
48
256
Yes
CYBLE-202007-01
48
256
Yes
CYBLE-202013-11
48
256
Yes
12-Bit
SAR
ADC
I2S
LCD
Package
Packing
Certified
1 Msps
Yes
Yes
30-SMT
Tape and Reel
Yes
1 Msps
Yes
Yes
30-SMT
Tape and Reel
Yes
1 Msps
Yes
Yes
30-SMT
Tape and Reel
No
CapSense SCB TCPWM
Part Numbering Convention
The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows.
For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales
representative. To locate the nearest Cypress office, visit our website.
U.S. Cypress Headquarters Address
U.S. Cypress Headquarter Contact Info
Cypress website address
Document Number: 002-15631 Rev.PRELIMINARY
198 Champion Court, San Jose, CA 95134
(408) 943-2600
http://www.cypress.com
Page 35 of 38
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
PRELIMINARY
Acronyms
Document Conventions
Table 58. Acronyms Used in this Document
Units of Measure
Acronym
Description
BLE
Bluetooth Low Energy
Bluetooth
SIG
Bluetooth Special Interest Group
CE
European Conformity
CSA
Canadian Standards Association
EMI
electromagnetic interference
ESD
electrostatic discharge
FCC
Federal Communications Commission
GPIO
general-purpose input/output
IC
Industry Canada
IDE
integrated design environment
KC
Korea Certification
MIC
Ministry of Internal Affairs and Communications
(Japan)
PCB
printed circuit board
RX
receive
QDID
qualification design ID
SMT
surface-mount technology; a method for producing
electronic circuitry in which the components are
placed directly onto the surface of PCBs
TCPWM
timer, counter, pulse width modulator (PWM)
TUV
Germany: Technischer Überwachungs-Verein
(Technical Inspection Association)
TX
transmit
Document Number: 002-15631 Rev.PRELIMINARY
Table 59. Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
kV
kilovolt
mA
milliamperes
mm
millimeters
mV
millivolt
μA
μm
microamperes
MHz
megahertz
micrometers
GHz
gigahertz
volt
Page 36 of 38
PRELIMINARY
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Document History Page
Document Title: CYBLE-212006-01, CYBLE-202007-01, CYBLE-202013-11 EZ-BLE™ PRoC™ 4.2 XR Module
Document Number: 002-09764
Revision
ECN
Orig. of
Change
Submission
Date
**
PRELIMINARY
MINS
PRELIMINARY
Description of Change
Preliminary datasheet for CYBLE-212006-01, CYBLE-202007-01 and
CYBLE-202013-11module.
Document Number: 002-15631 Rev.PRELIMINARY
Page 37 of 38
PRELIMINARY
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including
any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.
Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual
property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby
grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and
reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided
by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-15631 Rev.PRELIMINARY
Revised July 28, 2016
Page 38 of 38
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