Delta Electronics orporated DFZM-E8210 ZigBee Module User Manual DFZM E82xx S2

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DFZM-E82xx
Data sheet
DFZM-E82xx
An IEEE 802.15.4 System–On-Chip ZigBee
module
Data Sheet
Sheet 1 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
Contents
1.
Features ............................................................................................................................................... 4
2.
ZigBee Model No. Definition ............................................................................................................. 6
3.
Architecture......................................................................................................................................... 7
3-1.Block Diagram .............................................................................................................................. 7
3-2.Block Diagram Description .......................................................................................................... 8
3-2-1.Overview ........................................................................................................................... 8
3-2-2.CPU and Memory.............................................................................................................. 8
3-2-3.Clocks and Power Management ...................................................................................... 10
3-2-4.Peripherals ....................................................................................................................... 12
4.
Pin-out and Signal Description ......................................................................................................... 15
4-1.Device Pin-out Diagram (Module top view) .............................................................................. 15
5.
4-2.Module Pins Description ............................................................................................................ 16
Electrical Characteristics .................................................................................................................. 23
5-1.Absolute Maximum Rating......................................................................................................... 23
5-2.Recommended Operating Conditions ......................................................................................... 23
5-3.Power Consumption.................................................................................................................... 24
5-4.Digital I/O and nRESET Pin Specifications ............................................................................... 25
5-5.Wake-up and Timing................................................................................................................... 26
5-6.Radio Parameters ........................................................................................................................ 27
6.
5-7.ADC Parameters ......................................................................................................................... 28
Package and Layout Guidelines ........................................................................................................ 29
6-1.Recommended PCB Footprint and Dimensions ......................................................................... 29
6-2.Layout Guidelines....................................................................................................................... 32
6-2-1.Surface Mount Assembly ................................................................................................ 33
6-3.Recommended Stencil Aperture ................................................................................................. 35
7.
Ordering Information ........................................................................................................................ 36
8.
Package ............................................................................................................................................. 36
8-1.Information of carrier tape direction&packaging dimension ..................................................... 36
8-2.Reel dimension ........................................................................................................................... 38
8-3.Total Package .............................................................................................................................. 39
Data Sheet
Sheet 2 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
Revision History
Version
0.1
Date
Reason of change
Maker
2013/12/31 Initial release
Monch
1. Add RF exposure warning statement including FCC
0.2
2014/06/27
statement.
Monch
2. Modify 5.6 Radio Parameter for DFZM-E821x .
Data Sheet
Sheet 3 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
DFZM-E82xx
IEEE802.15.4 System-On-Chip ZigBee Module
describes the DFZM-E82xx ZigBee module hardware specification. The EM3587
based modules provide cost effective, low power, and flexible platform to add ZigBee connectivity
for embedded devices for a variety of applications, such as wireless sensors、energy and security
HIS DOCUMENT
monitoring、building( or home ) automation and control . It combines 32-bit ARM Cortex-M3 processor,
in-system programable flash memory, 64-KB RAM, 512KB flash memory and off module certified
antenna options, and various RF front end options for end customer range needs in order to provide a
ZigBee and regulatory certified. The module has various operating modes, making it highly suit for
system where ultralow power consumption is required. Short transition times between operating modes
further ensure low energy consumption.
1. Features
► Family of modules with different antenna and output power options:

DFZM-E82xx 27 mm by 16 mm by 3.3 mm (Length * Width * Height) 28-pin Dual Flat pack PCB
Surface Mount Package.

DFZM-E8220, DFZM-E8221, DFZM-E8210, and DFZM-E8211 are all pin to pin compatible (see
section 7 Ordering Information), and the user has to account only for power consumption for various
end applications.

Simple API for embedded markets covering large areas of applications.
► Compliant with IEEE 802.15.4-2003 and regulatory domains:

RoHS compliant.
► Microcontroller:

Industry-leading ARM Cortex-M3 processor.

512KB Flash with optional read protection.

64KB RAM memory.
Data Sheet
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DFZM-E82xx

Flexible nested vectored interrupt controller.
► Interfaces:

Internal antenna or external antenna options.

Flexible ADC, UART/SPI/TWI serial communications, and general purpose timers.

Up to 24 configurable general purpose I/Os.

Single voltage operation: 2.1~3.6V
► Embedded RTC (Real Time Clock) can run directly from battery.
Data Sheet
Sheet 5 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
2. ZigBee Model No. Definition
D F Z M - E 8 2 2 0
Data Sheet
DT 0 R
Sheet 6 of 41
Free-lead
E=Pb free
R=RoHS
N=NG
L=Process with Lead
Serial no.
0~9 then A~Z
Customer code
DT= Delta Define
Antenna Version
0= External Antenna
1=PCB printed Antenna
Power Version
1= High Power
2= Low Power
Frequency
2= 2.4GHz
Chip Type
8=EM3587
Chip Vendor
E=Ember(Silicon Labs)
Product-type
M= Module
Property
Z= ZigBee
Substrate
F= FR4
Company
D= DELTA
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
3. Architecture
3-1.Block Diagram
Figure 3-1: DFZM-E822x Block Diagram
24M X’tal
ANT
Digital I/O
SE2432L
VCC
Figure 3-2: DFZM-E821x Block Diagram
Data Sheet
Sheet 7 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
3-2.Block Diagram Description
3-2-1.Overview
DFZM-E82xx module is a highly integrated ZigBee system-on-chip (SOC) that contains the following:
 The module includes Silicon Labs EM3587 SoC, which contains CPU- and memory-related,
peripherals-related, clocks and power management-related in a single package.
 The module features an IEEE802.15.4-compliant radio transceiver with onboard 24 MHz crystal circuitries,
RF, and certified antenna or external antenna options.
The low power module option has a capability of +8dBm output power at the antenna (see Figure
3-1).
The high power module option has a capability of +18.5dBm output power at the antenna (see
Figure 3-2).
 Variety of interfaces are available such as UART, SPI, TIMER, ADC, Operational amperifier and GPIO.
 DFZM-E82xx contains single power supply (VCC).
3-2-2.CPU and Memory
The EM3587 integrates the ARM® Cortex-M3 microprocessor. The ARM® Cortex-M3 is an advanced 32-bit
modified Harvard architecture processor that has separate internal program and data buses, but presents a unified
program and data address space to software. The word width is 32 bits for both the program and data sides. The
ARM® Cortex-M3 allows unaligned word and half-word data accesses to support efficiently-packed data
structures.
The ARM® Cortex-M3 clock speed is configurable to 6 , 12 , or 24 MHz. For normal operation 24 MHz is
preferred over 12 MHz due to improved performance for all applications and improved duty cycling for
applications using sleep modes. The 6 MHz operation can only be used when radio operations are not required
since the radio requires an accurate 12 MHz clock.
The ARM® Cortex-M3 in the EM3587 has also been enhanced to support two separate memory protection levels.
Basic protection is available without using the MPU, but normal operation uses the MPU. The MPU allows for
protecting unimplemented areas of the memory map to prevent common software bugs from interfering with
software operation. The architecture could also allow for separation of the networking stack from the application
code using a fine granularity RAM protection module. Errant writes are captured and details are reported to the
Data Sheet
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Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
developer to assist in tracking down and fixing issues. Figure 3.3 shows the EM357 ARM® Cortex-M3 memory
map.
Figure 3-3: DFZM-E82xx memory map
Data Sheet
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Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
3-2-3.Clocks and Power Management
The DFZM-E82xx integrates three oscillators:
12
MHz RC oscillator
24
MHz crystal oscillator
10
kHz RC oscillator
Figure 3-4 shows a block diagram of the clocks in the DFZM-E82xx. This simplified view shows all the clock
sources and the general areas of the chip to which they are routed
Figure 3-4: DFZM-E82xx block diagram of the clocks
Data Sheet
Sheet 10 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
The DFZM-E82xx’s power management system is designed to achieve the lowest deep sleep current consumption
possible while still providing flexible wakeup sources, timer activity, and debugger operation. The DFZM-E82xx
has four main sleep modes:
Idle
Sleep: Puts the CPU into an idle state where execution is suspended until any interrupt occurs. All power
domains remain fully powered and nothing is reset.
Deep
Sleep 1: The primary deep sleep state. In this state, the core power domain is fully powered down and
the sleep timer is active.
Deep
Sleep 2: The same as Deep Sleep 1 except that the sleep timer is inactive to save power. In this mode the
sleep timer cannot wake up the DFZM-E82xx.
Deep
Sleep 0 (also known as Emulated Deep Sleep): The chip emulates a true deep sleep without powering
down the core domain. Instead, the core domain remains powered and all peripherals except the system debug
components (ITM, DWT, FPB, NVIC) are held in reset. The purpose of this sleep state is to allow DFZM-E82xx
software to perform a deep sleep cycle while maintaining debug configuration such as breakpoints.
The power management state diagram in Figure 3-5 shows the basic operation of the power management
controller.
Figure 3-5: DFZM-E82xx power management state diagram
Data Sheet
Sheet 11 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
3-2-4.Peripherals
The DFZM-E82xx has 24 multipurpose GPIO pins, which may be individually configured as:
General
purpose output
General
purpose open-drain output
Alternate
output controlled by a peripheral device
Alternate
open-drain output controlled by a peripheral device
Analog
General
purpose input
General
purpose input with pull-up or pull-down resistor
The GPIO signal assignments are shown in Table 3-1.
GPIO
Analog
Alternate Output
Input
TIM2C31, SC2MOSI
PA0
Output Current Drive
TIM2C31, SC2MOSI
Standard
PA1
TIM2C3 , SC2MISO, SC2SDA
TIM2C3 , SC2MISO, SC2SDA
Standard
PA2
TIM2C41, SC2SCLK, SC2SCL
TIM2C41, SC2SCLK, SC2SCL
Standard
PA3
PA4
PA5
TIM2C2
ADC4
ADC5
PA6
TIM2C2 , SC2nSSEL
Standard
PTI_DATA, TRACEDATA3
nBOOTMODE
TIM1C3
TIM1C3
High
TIM1C4
High
TIM1C4, REG_EN
VREF
SC1MISO, SC1SDA
Standard
TRACEDATA2, TIM2MSK,
TRACEDATA2
Standard
IRQA,TIM1CLK
TIM2C14, SC1TXD, SC1MOSI,
PB1
Standard
PTI_EN, TRACEDATA2
PA7
PB0
TIM2C14, SC1SDA
Standard
TIM2C24, SC1MISO, SC1MOSI,
Standard
PB2
TIM2C2 , SC1SCL
PB3
TIM2C34, SC1SCLK
TIM2C34, SC1SCLK, SC1nCTS
Standard
PB4
TIM2C44, SC1nRTS
TIM2C44, SC1nSSEL
Standard
TIM2CLK, TIM1MSK
Standard
SC1SCL, SC1RXD
PB5
ADC0
PB6
ADC1
TIM1C1
TIM1C1, IRQB
High
PB7
ADC2
TIM1C2
TIM1C2, IRQC
High
Data Sheet
Sheet 12 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
PC0
TRACEDATA1
PC1
ADC3
JRST, IRQD
High
TRACEDATA3
Standard
PC2
JTDO , SWO , TRACEDATA0
PC3
TRACECLK
JTDI TRACECLK
PC4
SWDIO
PC5
TX_ACTIVE
Standard
5,
SWDIO , JTMS
Standard
Standard
Standard
Notes:
1.Default signal assignment (not remapped).
2. Overrides during reset as an input with pull up.
3. Overrides after reset as an open-drain output.
4. Alternate signal assignment (remapped).
5. Overrides in JTAG mode as a input with pull up.
6. Overrides in JTAG mode as a push-pull output.
7. Overrides in Serial Wire mode as either a push-pull output, or a floating input, controlled by the debugger.
Table 3-1: DFZM-E82xx GPIO signal assignments
The DFZM-E82xx has two serial controllers, SC1 and SC2, which provide several options for full-duplex
synchronous and asynchronous serial communications.
SPI
(Serial Peripheral Interface), master or slave
TWI
(Two Wire serial Interface), master only
UART
(Universal Asynchronous Receiver/Transmitter), SC1 only
Receive
and transmit FIFOs and DMA channels, SPI and UART modes
Before using a serial controller, configure and initialize it as follows:
1. Set up the parameters specific to the operating mode (master/slave for SPI, baud rate for UART, etc.).
2. Configure the GPIO pins used by the serial controller as shown in Tables 3-2 and 3-3.
3. If using DMA, set up the DMA and buffers.
4. If using interrupts, select edge- or level-triggered interrupts with the SCx_INTMODE register, enable the
desired second-level interrupt sources in the INT_SCxCFG register, and finally enable the top-level SCx interrupt
in the NVIC.
5. Write the serial interface operating mode (SPI, TWI, or UART) to the SCx_MODE register
Data Sheet
Sheet 13 of 41
Dec 31, 2013
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DFZM-E82xx
PB1
SC1MOSI Alternate
SPI-Master
Output
SC1MISO Alternate
SPI-Slave
TWI-Master
UART
Output
PB2
SC1MISO Input
SC1MOSI Input
SC1SDA Alternate
SC1SCL Alternate
Output (open-drain)
Output (open-drain)
TXD Alternate Output
RXD Input
PB3
SC1SCLK Alternate
Output
PB4
(not used)
SC1SCLK Input
SC1nSSEL Input
(not used)
(not used)
SC1nCTS Input
SC1nRTS Alternate
Output
Table 3-2: DFZM-E82xx SC1 GPIO Usage and Configuration
PA0
SC2MOSI Alternate
SPI-Master
SPI-Slave
TWI-Master
Output
SC2MOSI Input
(not used)
PA1
SC2MISO Input
SC2MISO Alternate
Output
PA2
SC2SCLK Alternate
Output
SC2SCLK Input
SC2SDA Alternate
SC2SCL Alternate
Output (open-drain)
Output (open-drain)
PA3
(not used)
SC2nSSEL Input
(not used)
Table 3-3: DFZM-E82xx SC2 GPIO Usage and Configuration
Data Sheet
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DFZM-E82xx
4. Pin-out and Signal Description
4-1.Device Pin-out Diagram (Module top view)
Figure 4-1: DFZM-E82xx Device Pin-out Diagram (Module top view)
Data Sheet
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DFZM-E82xx
4-2.Module Pins Description
Pins
Name
Pin Type
GND
Ground
PC5
I/O
Description
Ground
Digital I/O(Not available for DFZM-E821X-DT0R)
Logic-level control for external Tx/Rx switch .The EM358 baseband controls Tx active
TX_ACTIVE
and drives it high(VDD_PADS) when in Tx mode. Select alternate output function with
GPIO_PCCFGH[7:4].
nRESET
PA7
I/O
Active low chip reset(internal pull-up)
Digital I/O, High current, Disable REG_EN with GPIO_DBGCFG[4]
Timer 1 Channel 4 output, Enable timer output with TIM1_CCER
TIM1C4
Select alternate output function with GPIO_PACFGH[15:12]
Disable REG_EN with GPIO_DBGCFG[4]
TIM1C4
Timer 1 Channel 4 input, Cannot be remapped
REG_EN
External regulator open drain output, Enabled after reset
PB3
I/O
Digital I/O
Timer 2 channel 3 output, Enable remap with TIM2_OR[6]
TIM2C3
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PBCFGL[15:12]
TIM2C3
SC1nCTS
Timer 2 channel 3 input, Enable remap with TIM2_OR[6]
UART CTS handshake of Serial Controller 1
Enable with SC1_UARTCFG[5], Select UART with SC1_MODE
SPI master clock of Serial Controller 1
SC1SCLK
Either disable timer output in TIM2_CCER, or disable remap with TIM2_OR[6]
Enable master with SC1_SPICFG[4], Select SPI with SC1_MODE
Select alternate output function with GPIO_PBCFGL[15:12]
SC1SCLK
PB4
I/O
TIM2C4
Data Sheet
SPI slave clock of Serial Controller 1
Enable slave with SC1_SPICFG[4], Select SPI with SC1_MODE
Digital I/O
Timer 2 channel 4 output, Enable remap with TIM2_OR[7]
Enable timer output in TIM2_CCER
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DFZM-E82xx
Select alternate output function with GPIO_PBCFGH[3:0]
TIM2C4
Timer 2 channel 4 input, Enable remap with TIM2_OR[7]
UART RTS handshake of Serial Controller 1
SC1nRTS
Either disable timer output in TIM2_CCER,or disable remap with TIM2_OR[7]
Enable with SC1_UARTCFG[5], Select UART with SC1_MODE
Select alternate output function with GPIO_PBCFGH[3:0]
SC1nSSEL
PA0
I/O
SPI slave select of Serial Controller 1
Enable slave with SC1_SPICFG[4], Select SPI with SC1_MODE
Digital I/O
Timer 2 channel 1 output, Disable remap with TIM2_OR[4]
TIM2C1
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PACFGL[3:0]
TIM2C1
Timer 2 channel 1 input, Disable remap with TIM2_OR[4]
SPI master data out of Serial Controller 2
SC2MOSI
Either disable timer output in TIM2_CCER, or enable remap with TIM2_OR[4]
Enable master with SC2_SPICFG[4], Select SPI with SC2_MODE
Select alternate output function with GPIO_PACFGL[3:0]
SC2MOSI
PA1
I/O
SPI slave data in of Serial Controller 2
Enable slave with SC2_SPICFG[4], Select SPI with SC2_MODE
Digital I/O
Timer 2 channel 3 output, Disable remap with TIM2_OR[6]
TIM2C3
Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PACFGL[7:4]
TIM2C3
Timer 2 channel 3 input, Disable remap with TIM2_OR[6]
TWI data of Serial Controller 2, Either disable timer output in TIM2_CCER,
SC2SDA
I/O
or enable remap with TIM2_OR[6], Select TWI with SC2_MODE
Select alternate open-drain output function with GPIO_PACFGL[7:4]
SPI slave data out of Serial Controller 2, Either disable timer output in TIM2_CCER,
SC2MISO
or enable remap with TIM2_OR[6], Enable slave with SC2_SPICFG[4],
Select SPI with SC2_MODE, Select alternate output function with GPIO_PACFGL[7:4]
SC2MISO
Data Sheet
SPI master data in of Serial Controller 2
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DFZM-E82xx
Enable slave with SC2_SPICFG[4], Select SPI with SC2_MODE
PA2
I/O
Digital I/O
Timer 2 channel 4 output
TIM2C4
Disable remap with TIM2_OR[7], Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PACFGL[11:8]
TIM2C4
Timer 2 channel 4 input, Disable remap with TIM2_OR[7]
TWI clock of Serial Controller 2, Either disable timer output in TIM2_CCER,
SC2SCL
I/O
or enable remap with TIM2_OR[7], Select TWI with SC2_MODE
Select alternate open-drain output function with GPIO_PACFGL[11:8]
SPI master clock of Serial Controller 2
SC2SCLK
Either disable timer output in TIM2_CCER, or enable remap with TIM2_OR[7]
Enable master with SC2_SPICFG[4], Select SPI with SC2_MODE
Select alternate output function with GPIO_PACFGL[11:8]
SC2SCLK
PA3
I/O
SC2nSSEL
10
SPI slave clock of Serial Controller 2
Enable slave with SC2_SPICFG[4], Select SPI with SC2_MODE
Digital I/O
SPI slave select of Serial Controller 2
Enable slave with SC2_SPICFG[4], Select SPI with SC2_MODE
Timer 2 channel 2 output
TIM2C2
Disable remap with TIM2_OR[5], Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PACFGL[15:12]
TIM2C2
PA4
I/O
ADC4
Analog
Timer 2 channel 2 input, Disable remap with TIM2_OR[5]
Digital I/O
ADC Input 4, Select analog function with GPIO_PACFGH[3:0]
Frame signal of Packet Trace Interface (PTI)
PTI_EN
11
Disable trace interface in ARM core, Enable PTI in Ember software
Select alternate output function with GPIO_PACFGH[3:0]
Synchronous CPU trace data bit 2
TRACEDATA2
Select 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PACFGH[3:0]
Data Sheet
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DFZM-E82xx
PA5
I/O
ADC5
Analog
Digital I/O
ADC Input 5, Select analog function with GPIO_PACFGH[7:4]
Data signal of Packet Trace Interface (PTI)
PTI_DATA
Disable trace interface in ARM core, Enable PTI in Ember software
Select alternate output function with GPIO_PACFGH[7:4]
12
nBOOTMODE
Activate FIB monitor instead of main program or bootloader when coming out of reset.
Signal is active during and immediately after a reset on nRESET.
Synchronous CPU trace data bit 3
TRACEDATA3
Select 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PACFGH[7:4]
PA6
13
I/O
TIM1C3
TIM1C3
Digital I/O, High current
Timer 1 channel 3 output, Enable timer output in TIM1_CCER
Select alternate output function with GPIO_PACFGH[11:8]
Timer 1 channel 3 input, Cannot be remapped
14
GND
Ground
Ground
15
VCC
Power
Power Supply Input
PB1
I/O
Digital I/O
SPI slave data out of Serial Controller 1
SC1MISO
Either disable timer output in TIM2_CCER, or disable remap with TIM2_OR[4]
Select SPI with SC1_MODE, Select slave with SC1_SPICR
Select alternate output function with GPIO_PBCFGL[7:4]
SPI master data out of Serial Controller 1
16
SC1MOSI
Either disable timer output in TIM2_CCER, or disable remap with TIM2_OR[4]
Select SPI with SC1_MODE, Select master with SC1_SPICR
Select alternate output function with GPIO_PBCFGL[7:4]
TWI data of Serial Controller 1, Either disable timer output in TIM2_CCER,
SC1SDA
I/O
or disable remap with TIM2_OR[4], Select TWI with SC1_MODE
Select alternate open-drain output function with GPIO_PBCFGL[7:4]
SC1TXD
Data Sheet
UART transmit data of Serial Controller 1
Either disable timer output in TIM2_CCER, or disable remap with TIM2_OR[4]
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DFZM-E82xx
Select UART with SC1_MODE
Select alternate output function with GPIO_PBCFGL[7:4]
Timer 2 channel 1 output
TIM2C1
Enable remap with TIM2_OR[4], Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PACFGL[7:4]
TIM2C1
PB2
I/O
SC1MISO
SC1MOSI
Timer 2 channel 1 input, Disable remap with TIM2_OR[4]
Digital I/O
SPI master data in of Serial Controller 1
Select SPI with SC1_MODE, Select master with SC1_SPICR
SPI slave data in of Serial Controller 1
Select SPI with SC1_MODE, Select slave with SC1_SPICR
TWI clock of Serial Controller 1, Either disable timer output in TIM2_CCER,
17
SC1SCL
I/O
or disable remap with TIM2_OR[5], Select TWI with SC1_MODE
Select alternate open-drain output function with GPIO_PBCFGL[11:8]
SC1RXD
UART receive data of Serial Controller 1, Select UART with SC1_MODE
Timer 2 channel 2 output
TIM2C2
Enable remap with TIM2_OR[5], Enable timer output in TIM2_CCER
Select alternate output function with GPIO_PBCFGL[11:8]
TIM2C2
SWCLK
I/O
18
Timer 2 channel 2 input, Enable remap with TIM2_OR[5]
Serial Wire clock input/output with debugger
Selected when in Serial Wire mode (see JTMS description, Pin 35)
JTAG clock input from debugger
JTCK
Selected when in JTAG mode (default mode, see JTMS description, Pin 35)
Internal pull-down is enabled
PC2
JTDO
I/O
19
Digital I/O, Enable with GPIO_DBGCFG[5] and GPIO_PCCFGH[1] clear
JTAG data out to debugger
Selected when in JTAG mode (default mode, see JTMS description, Pin 35)
Serial Wire Output asynchronous trace output to debugger
SWO
Select asynchronous trace interface in ARM core, Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[11:8]
Enable Serial Wire mode (see JTMS description, Pin 35), Internal pull-up is enabled
Data Sheet
Sheet 20 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
Synchronous CPU trace data bit 3 , Select 4-wire synchronous trace interface in ARM
TRACEDATA0
core , Enable trace interface in ARM core , Select alternate output function with
GPIO_PCCFGL[11:8].
PC3
I/O
Digital I/O, Either Enable with GPIO_DBGCFG[5]
or enable Serial Wire mode (see JTMS description)
JTAG data in from debugger
20
JTDI
Selected when in JTAG mode (default mode, see JTMS description, Pin 35)
Internal pull-up is enabled
TRACECLK
PC4
I/O
Synchronous CPU trace clock , Enable trace interface in ARM core , Select alternate
output function with GPIO_PCCFGL[15:12].
Digital I/O, Enable with GPIO_DBGCFG[5]
JTAG mode select from debugger, Selected when in JTAG mode (default mode)
JTMS
21
JTAG mode is enabled after power-up or by forcing nRESET low
Select Serial Wire mode using the ARM-defined protocol through a debugger
Internal pull-up is enabled
Serial Wire bidirectional data to/from debugger
SWDIO
I/O
Enable Serial Wire mode (see JTMS description)
Select Serial Wire mode using the ARM-defined protocol through a debugger
Internal pull-up is enabled
PB0
I/O
VREF
Analog O
VREF
Analog I
IRQA
22
Digital I/O(Not available for DFZM-E821X-DT0R)
ADC reference output, Enable analog function with GPIO_PBCFGL[3:0]
ADC reference input, Enable analog function with GPIO_PBCFGL[3:0]
Enable reference output with an Ember system function
External interrupt source A
Synchronous CPU trace data bit 2
TRACEDATA2
Select 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core,
Select alternate output function with GPIO_PCCFGL[3:0]
23
TIM1CLK
Timer 1 external clock input
TIM2MSK
Timer 2 external clock mask input
PC1
Data Sheet
I/O
Digital I/O
Sheet 21 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
ADC3
Analog
ADC Input 3, Enable analog function with GPIO_PCCFGL[7:4]
Synchronous CPU trace data bit 3
TRACEDATA3
Select 1-, 2- or 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[7:4]
PC0
I/O
Digital I/O, High current, Either enable with GPIO_DBGCFG[5]
or enable Serial Wire mode (see JTMS description, Pin 35) and disable TRACEDATA1
JTAG reset input from debugger
JRST
Selected when in JTAG mode (default mode, see JTMS description) and
TRACEDATA1 is disabled, Internal pull-up is enabled
24
IRQD
Default external interrupt source D
Synchronous CPU trace data bit 1
TRACEDATA1
Select 2- or 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core,
Select alternate output function with GPIO_PCCFGL[3:0]
PB7
25
I/O
ADC2
Analog
IRQC
TIM1C2
TIM1C2
PB6
26
I/O
ADC1
Analog
IRQB
TIM1C1
TIM1C1
PB5
I/O
ADC0
Analog
Digital I/O, High current
ADC Input 2, Enable analog function with GPIO_PBCFGH[15:12]
Default external interrupt source C
Timer 1 channel 2 output, Enable timer output in TIM1_CCER
Select alternate output function with GPIO_PBCFGH[15:12]
Timer 1 channel 2 input, Cannot be remapped
Digital I/O, High current
ADC Input 1, Enable analog function with GPIO_PBCFGH[11:8]
External interrupt source B
Timer 1 channel 1 output, Enable timer output in TIM1_CCER
Select alternate output function with GPIO_PBCFGH[11:8]
Timer 1 channel 1 input, Cannot be remapped
Digital I/O(Not available for DFZM-E821X-DT0R)
ADC Input 0, Enable analog function with GPIO_PBCFGH[7:4]
27
TIM2CLK
Timer 2 external clock input
TIM1MSK
Timer 1 external clock mask input
Data Sheet
Sheet 22 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
28
GND
Ground
Ground
5. Electrical Characteristics
5-1.Absolute Maximum Rating
Conditions beyond those cited in Table 5-1 may cause permanent damage to the DFZM-E72xx, and must be
avoided.
Parameter
Minimum
Maximum
Unit
Supply voltage(VCC)
-0.3
3.6
Storage temperature range
-40
125
ºC
Voltage on any digitai I/O
-0.3
VCC+0.3
Table 5-1: Absolute Maximum Ratings
5-2.Recommended Operating Conditions
Parameter
Minimum
Maximum
Unit
Operating supply voltage(VCC)
2.1
3.6
Operating ambient temperature range(TA)
-40
+85
ºC
Table 5-2: Recommended Operating Conditions
Data Sheet
Sheet 23 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
5-3.Power Consumption
Test Conditions: TA=25 ºC, VCC=3.0V
Parameter
Test conditions
Mim
Typ
Max
Unit
Deep Sleep Current
Quiescent current, internal RC oscillator
disabled
Quiescent current, including internal RC
oscillator
Simulated deep sleep (debug mode)
current
With no debugger activity
uA
1.25
uA
500
uA
Reset Current
Quiescent current, nRESET asserted
mA
Processor and Peripheral Currents
ARM® Cortex-M3, RAM, and flash
ARM® Cortex-M3 running at 24 MHz from crystal
memory
oscillator Radio and all peripherals off
ARM® Cortex-M3, RAM, and flash
ARM® Cortex-M3 sleeping, CPU clock set to 12 MHz
memory sleep current
from the crystal oscillator Radio and all peripherals off
Serial controller current
8.5
mA
7.5
mA
For each controller at maximum data rate
0.2
mA
General purpose timer current
For each timer at maximum clock rate
0.25
mA
General purpose ADC current
At maximum sample rate, DMA enabled
1.1
mA
ARM® Cortex-M3 sleeping, CPU clock set to 12 MHz
22
mA
RX Current
Radio receiver, MAC, and baseband
Total RX current ( = IRadio receiver,
MAC and baseband, CPU + IRAM, and
ARM® Cortex-M3 running at 24 MHz
26.5
ARM® Cortex-M3 running at 24 MHz
28.5
31
mA
Flash memory )
Boost mode total RX current ( = IRadio
receiver, MAC and baseband, CPU+
IRAM, and flash memory )
Data Sheet
Sheet 24 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
mA
DFZM-E82xx
TX current
max. power out (+3 dBm typical)
26.0
mA
43.5
mA
110
mA
Radio transmitter, MAC, and baseband
ARM® Cortex-M3 sleeping, CPU clock set to 12 MHz
Total TX current ( = IRadio transmitter,
MAC and baseband, CPU + IRAM, and
flash memory)
maximum power setting (+8 dBm); ARM® Cortex-M3
running at 24 MHz
maximum power setting (+18.5 dBm); ARM® Cortex-M3
running at 24 MHz
Table 5-3: Poewr Consumption
5-4.Digital I/O and nRESET Pin Specifications
Test Conditions: TA=25 ºC, VCC=3.0V
Parameter
Low Schmitt switching threshold
High Schmitt switching threshold
Test conditions
Min
Typ
Max
VSWIL, Schmitt input threshold going from high to
0.42 x
0.5 x
low
VCC
VCC
VSWIH, Schmitt input threshold going from low to
0.62 x
0.80 x
high
VCC
VCC
Unit
Input current for logic 0
IIL
-0.5
uA
Input current for logic 1
IIH
+0.5
uA
Input pull-up resistor value
RIPU
24
29
34
kΩ
Input pull-down resistor value
RIPD
24
29
34
kΩ
VOL(IOL = 4 mA for standard pads, 8 mA for high
current pads)
0.18 x
VCC
Output voltage for logic 0
>85 °C VOL(IOL = 2 mA for standard pads, 4 mA
for high current pads)
0.18 x
VOH(IOH = 4 mA for standard pads, 8 mA for high
0.82 x
current pads)
VCC
>85 °C VOH(IOH = 2 mA for standard pads, 4 mA
0.82 x
for high current pads)
VCC
VCC
VCC
VCC
mA
Output voltage for logic 1
Output source current
Data Sheet
IOHS
Sheet 25 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
Parameter
Test conditions
Min
Typ
Max
Unit
IOLS
mA
IOHH
mA
IOLH
mA
IOH + IOL
40
mA
Max
Unit
(standard current pad)
Output sink current
(standard current pad)
Output source current high current pad:
PA6, PA7, PB6, PB7, PC0
Output sink current high current pad:
PA6, PA7, PB6, PB7, PC0
Total output current (for I/O Pads)
Table 5-4: Digital I/O Specifications
Parameter
Low Schmitt switching threshold
High Schmitt switching threshold
Test conditions
Min
Typ
VSWIL, Schmitt input threshold going from high to
0.42 x
0.5 x
low
VCC
VCC
VSWIH, Schmitt input threshold going from low to
0.62 x
0.68 x
high
VCC
VCC
Input current for logic 0
IIL
-0.5
uA
Input current for logic 1
IIH
+0.5
uA
Input pull-up resistor value
RIPU, Pull-up value while the chip is not reset
24
29
34
kΩ
Input pull-down resistor value
RIPURESET, Pull-up value while the chip is reset
12
14.5
17
kΩ
Table 5-5: nRESET pin Specifications
5-5.Wake-up and Timing
Test Conditions: TA=25 ºC, VCC=3.0V
Parameter
System wake time from deep sleep
Test conditions
Min
From wakeup event to first ARM® Cortex-M3 instruction
Typ
Max
110
running from 6 MHz internal RC clock Includes supply ramp
Data Sheet
Sheet 26 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
Unit
us
DFZM-E82xx
Parameter
Test conditions
Min
Typ
Max
Unit
time and oscillator startup time
Shutdown time going into deep sleep
From last ARM® Cortex-M3 instruction to deep sleep mode
Table 5-6: Wake-up and Timing
5-6.Radio Parameters
Test Conditions: TA=25 ºC, VCC=3.0V
Parameter
Min
RF Frequency range
2400
Typ
Max
Unit
2500
MHz
Notes
TX/RX specification for DFZM-E822x
Output power(boost mode)
dBm
Output power
-3
dBm
Error vector magnitude (EVM)
15
30
ppm
Receiver sensitivity(boost mode)
-102
-96
dBm
PER = 1%
Receiver sensitivity
-100
-94
dBm
PER = 1%
dBm
PER = 1%,
Frequency error tolerance
Saturation(Maximum input level)
-30
TX/RX specification for DFZM-E821x
Output power
16
Error vector magnitude (EVM)
Frequency error tolerance
-30
Receiver sensitivity(boost mode)
Saturation(Maximum input level)
17.5
23
dBm
15
30
ppm
-102
-96
dBm
PER = 1%,
dBm
PER = 1%,
Table 5-7: Radio Parameters
Data Sheet
Sheet 27 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
us
DFZM-E82xx
5-7.ADC Parameters
Test Conditions: TA=25 ºC, VCC=3.0V
Parameter
Min
Typ
Max
Unit
1.17
1.2
1.23
VREF output current
mA
VREF load capacitance
10
nF
1.3
VREF
External VREF voltage range
1.1
1.2
External VREF input impedance
MΩ
Minimum input voltage
Maximum input vlotage
Single-ended signal range
Differential signal range
Common mode range
Input referred ADC offset
VREF
VREF
-VREF
+VREF
VREF
-10
10
mV
Input Impedence
1MHz sample clock
6MHz sample clock
0.5
Not sample
10
MΩ
*Note: The signal-ended ADC measurements are limited in their range and only guaranteed for
accuracy within the limits shown in this table. The ADC's internal design allows for
measurements outside of this range (±200 mV), but the accuracy of such measurements is not
guaranteed. The maximum input voltage is of more interest to the differential sampling where a
differential measurement might be small, but a common mode can push the actual input voltage
on one of the signals towards the upper voltage limit.
Table 5-8: ADC Parameters
Data Sheet
Sheet 28 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
6. Package and Layout Guidelines
6-1.Recommended PCB Footprint and Dimensions
Figure 6-1: DFZM-E82xx Module Recommended PCB Footprint (in mm)
Data Sheet
Sheet 29 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
Figure 6-2: DFZM-E821x Module Dimensions (in mm)
Data Sheet
Sheet 30 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
Figure 6-3: DFZM-E822x Module Dimensions (in mm)
Data Sheet
Sheet 31 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
6-2.Layout Guidelines
Keep out area for onboard antenna. All layers on the
PCB must be clear.
(i.e. No GND, Power trace/plane, traces.)
Note: If guidelines are not followed, DFZM-E72xx
range with onboard antenna will be compromised.
Figure 6-4: DFZM-E82xx module onboard antenna keep-out layout guidelines (in mm)
Notes:
1. All Dimensions are in mm. Tolerances shall be ±0.10 mm.
2. Absolutely no metal trace or ground layer underneath this area.
3. It is recommended not to run circuit traces underneath the module.
4. In performing SMT or manual soldering of the module to the base board, please align the two row of pins.
In addition to the guidelines in Figure 6-4, note the following suggestions:
DFZM-E82xx
 External Bypass capacitors for all module supplies should be as close as possible to the module pins.
 Never place the antenna very close to metallic objects.
 The external dipole antennas need a reasonable ground plane area for antenna efficiency.
DFZM-E8221; DFZM-E8211 onboard antenna specific
Data Sheet
Sheet 32 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
 The onboard antenna keep out area, as shown in Figure 6-4, must be adhered to. In addition it is
recommended to have clearance above and below the PCB trace antenna (Figure 6-4) for optimal range
performance.
 Do not use a metallic or metalized plastic for the end product enclosure.
 Recommendation is to keep plastic enclosure clearance of 1cm from top and bottom of the DFZM-E82xx
onboard antenna keep-out area, if possible. 5-mm (0.2 in) clearance shall be the minimum as shown in
Figure 6-5.
Figure 6-5 Recommended clearance above and below the PCB trace antenna
6-2-1.Surface Mount Assembly
The reflow profile is shown in Figure 6-6.
Data Sheet
Sheet 33 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
(° C )
Peak temp
250° c max 10 sec max
245° c±5° c for
10 ~30 sec
245
217
200
150
Room temp.
Time
50 sec max
60-180 sec
60-150 sec
Figure 6-6: Reflow temperature profile
Note:
1. Perform adequate test in advance as the reflow temperature profile will vary accordingly to the
conditions of the parts and boards, and the specifications of the reflow furnace.
2. Be careful about rapid temperature rise in preheat zone as it may cause excessive slumping of the
solder paste.
3. If the preheat is insufficient, rather large solder balls tend to be generated. Conversely, if performed
excessively, fine balls and large balls will generate in clusters at a time.
4. If the temperature is too low, non-melting tends to be caused in the area with large heat capacity after
reflow.
5. Be careful about sudden rise in temperature as it may worsen the slump of solder paste.
6. Be careful about slow cooling as it may cause the positional shift of parts and decline in joining
strength at times.
Data Sheet
Sheet 34 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
6-3.Recommended Stencil Aperture
Note: The thickness of the stencil should be 0.15mm over this area.
Figure 6-7: DFZM-E82xx recommended PCB footprint ( in mm )
Data Sheet
Sheet 35 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
7. Ordering Information
DEVICE DESCRIPTION
ORDERING NUMBER
Extended range module using external antenna
DFZM-E8210-DT0R
Extended range module using onboard antenna
DFZM-E8211-DT0R
Low power module using external antenna
DFZM-E8220-DT0R
Low power module using onboard antenna
DFZM-E8221-DT0R
8. Package
8-1.Information of carrier tape direction&packaging dimension
Data Sheet
Sheet 36 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
:20
ZL
Unreeling direction
06
5.7
60
03
00
YYWWNNNNN
DFZM-TS210-DT0R
FCC ID : H79DFZM-TS210
YYWWNNNNN
DFZM-TS210-DT0R
FCC ID : H79DFZM-TS210
YYWWNNNNN
DFZM-TS210-DT0R
FCC ID : H79DFZM-TS210
10-DT0R
H79DFZM-TS210
YYWWNNNNN
YYWWNNNNN
DFZM-TS210-DT0R
FCC ID : H79DFZM-TS210
YYWWNNNNN
DFZM-TS210-DT0R
YYWWNNNNN
FCC ID : H79DFZM-TS210
Pb
DFZM-TS210-DT0R
RoHS Compliant
FCC ID : H79DFZM-TS210
Accepted
CUSTOMER:
MODEL:
Q'TY:
DATE:
Components
◆ Quantity:750pcs
FQC:
Trailer
20PCS(min)
Leader
20PCS min
Carrier tape
Cover tape
YYWWNNNNN
DFZM-TS210-DT0R
FCC ID : H79DFZM-TS210
Reel
Protective Tape
(width=56mm,Thickness=0.5mm)
06
:2 0
ZL
.7
05
36
00
20
PS
RoHS Compliant
Adhesive Tape
Pb
Accepted
CUSTOMER:
MODEL:
Q'TY:
DATE:
FQC:
Data Sheet
Sheet 37 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
8-2.Reel dimension
W1
ZL:200620003605.7
W0
規
格
品
名
瑋鋒編號
W0
W1
13" 100*44mm旋轉式圓盤 RUR-26-3-XL 45.0±0.5 50.0±1.0
* 代表顏色編碼 B 黑色 , C 寶藍色 ﹐L 藍色﹐W 白色
Data Sheet
Sheet 38 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
8-3.Total Package
Data Sheet
Sheet 39 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
8-4. RF exposure warning statement
FCC Label Statement
This device complies with part 15 of the FCC rules. Operation is subject to
the following two conditions:
1. This device may not cause harmful interference, and
2. This device must accept any interference received, including interference that may cause undesired
operation.
Federal Communications Commission (FCC) Statement
15.21
You are cautioned that changes or modifications not expressly approved by the part responsible for compliance
could void the user’s authority to operate the equipment.
15.105(b)
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part
15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference in a
residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed
and used in accordance with the instructions, may cause harmful interference to radio communications. However,
there is no guarantee that interference will not occur in a particular installation. If this equipment does cause
harmful interference to radio or television reception, which can be determined by turning the equipment off and
on, the user is encouraged to try to correct the interference by one or more of the following measures:
-Reorient or relocate the receiving antenna.
-Increase the separation between the equipment and receiver.
-Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
-Consult the dealer or an experienced radio/TV technician for help.
FCC RF Radiation Exposure Statement:
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. End users
must follow the specific operating instructions for satisfying RF exposure compliance. This transmitter must not
Data Sheet
Sheet 40 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
be co-located or operating in conjunction with any other antenna or transmitter.
Data Sheet
Sheet 41 of 41
Dec 31, 2013
Proprietary Information and Specifications are Subject to Change

---

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