Select> CL06532065-033.eps 180500 The first line indicates that the Diagnostic software has been activated and contains the version number of the diagnostic; this is also an indication that the first basic nucleus (nucleus number 1) has been executed succesfully. The next three lines are the succesful result of the subsequent basic tests (nuclei 2, 3, 4 and initialisation of Karaoke chip respectively). If not all these messages appear on the terminal screen, then the related nucleus found an error. The last line is the prompt asking to choose for an interface form. If a choice for Menu Interface has been made, the main menu will appear. For the layout of the menus, see page 25. To switch between interfaces, the DVD player needs to be switched off and on again. Note1 : The DVDv2B player has no power-ON key, but should be turned on by connecting the power-cable. Note2 : The Dram tests are no longer executed because the player has no DRAM . Note3 : When the stack is located in the internal memory, the test with the SRAM doesn't work and will be left out. Note4 : The karaoke initialisation will also take place if there is no karaoke-chip in the player. Usage A selection can be given by the user by typing the number of the menu-item chosen at the prompt. Each entry must be terminated with a . Invalid selections will cause an error message by the Menu Handler. Example: Select > 60 0001 Invalid menu selection ER @ Press RETURN to continue @ CL96532111_021.eps 071099 Set-up physical interface components Hardware required: • Service PC • one free COM port on the Service PC • special cable to connect DVD player to Service PC The service PC must have a terminal emulation program (e.g. OS2 WarpTerminal or Procomm) installed and must have a free COM port (e.g. COM1). Activate the terminal emulation program and check that the port settings for the free COM port are: 19200 bps, 8 data bits, no parity, 1 stop bit and no flow control. The free COM port must be connected via a special cable to the RS232 port of the DVD player. This special cable will also connect the test pin, which is available on the connector, to ground (i.e. activate test pin). 5.9.2 Result and output of an activated (and terminated) nucleus will be sent back to the service terminal. Example: Select > 16 1601 Data line X is not connected to the SDRAM ER @ Press RETURN to continue @ CL96532111_022.eps 071099 After the user presses a key, the current menu is rebuilt on screen. Pressing < return > at the prompt without any further input at the terminal will always rebuild the main menu. Code nr. PC interface cable: 3122 785 90017 Activation Switch the player on and the following text will appear on the screen of the terminal (program): Termination The menu interface is terminated by switching off the DVD player. Test instructions mono board DVD-ASD1 5.9.3 ASD-1 Command Line Interface 5. GB 19 Example in case the command is correct: The command line interface is part of level 1 diagnostic mode. Via a command line interface the execution of Diagnostic Nuclei can be controlled. Set-up physical interface components Hardware required: • Control PC • one free COM port on the Control PC • special cable to connect DVD player to the Control PC The control PC must use the following port settings for the used COM port: 19200 bps, 8 data bits, no parity, 1 stop bit and no flow control. The control PC is connected with a special cable to the RS232 port of the DVD player. Via the same connection the test pin will be connected to ground. DD > CompSdarmWrR 1600 OK @ DD> CL96532111_025.eps 071099 Example in case the result is an error: DD > CompSdarmWrR 1601 Address line X not connected to the SDRAM @ DD> CL96532111_026.eps 071099 Activation After power on the next text will sent to the control PC DVDv2 Diagnostic Software version 1.0 SDRAM Interconnection test passed Basic SDRAM test passed Karaoke init OK Termination The command line interface is terminated by switching off the DVD player. 5.9.4 (M)enu, (C)ommand (S)2B-interface or (D)ownload? [M]:@ C

CL06532065_034.eps 180500 The first line indicates that the Diagnostic software has been activated and contains the version number; this is also an indication that the first basic nucleus (nucleus number 1) has been executed succesfully. The next three lines are the succesful result of two subsequent basic tests (nuclei 2, 3, 4and karaoke initialisation respectively). If not all these messages appear on the terminal screen, then the related nucleus found an error. The fifth line lets the user choose between the two possible interface forms. The last line is the prompt ("DD>"). The diagnostic software is now ready to receive commands. Note1 : The DVDv2B player has no power-ON key, but should be turned on by connecting the power-cable. Note2 : When it is a player without DRAM, the DRAM tests are left out. Usage The commands that can be given are the names or the numbers of the nuclei. A command must be terminated with a < return > character from the control PC. When typing commands, the backspace key can be used to make corrections. In case of typing errors in the command, an error message is returned. Example: DD > CompSdarmWrR 0001 Unknown command ER @ DD> S2B Interface (not for service) Set-up physical interface components Hardware needed: • Control PC • one free COM port on the Control PC • special cable to connect DVD player to Control PC • S2B monitor tool running on the Control PC Activation To start the S2B interface, connect the RS232 cable to the Control PC in the correct manner. Then start the PC, start the monitor tool and start the DVD player; turn off the monitor tool, turn on S2B monitor tool. The S2B monitor tool now takes all communication. The S2B interface is activated by sending the bit pattern 110x xxxx with the first character to the DVD player, when the user is asked to choose an interface type. The command handler will then activate the S2B pass-through nucleus. The character sent will be passed to this nucleus without loss. Note: The DVDv2B player has no power-ON key, but should be turned on by connecting the power-cable. Termination To terminate S2B pass-through mode, switch off the DVD player. 5.10 Script Interfaces This interface is used during execution of the Player Script and the Dealer Script to display output and error messages. The local display will be used to display the output and the error messages. 5.10.1 Dealer Script CL96532111_024.eps 071099 If the command (the nucleus name or number) is recognised, the nucleus is executed. Result and output of an activated (and terminated) nucleus will be sent back to the control PC according to the standard layout as defined in Appendix C. Set-up physical interface components Hardware required: • DVD player The DVD player is tested stand-alone: no other equipment than the DVD player is needed. Activation The dealer script is activated by pressing OPEN/CLOSE and PAUSE on the local keyboard of the DVD player simultaneously during power-on. GB 20 5. Test instructions mono board DVD-ASD1 ASD-1 Note : The DVDv2B player has no power-ON key, but should be turned on by connecting the power-cable. Usage The test requires no user interaction. A number of nuclei will be run before a message is returned indicating if there is a failure in the DVD player. During the execution of a script, a progress indicator is displayed on the local display of the DVD player. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + CL96532111_017.eps 071099 The counter at the right side of the display counts down from the number of nuclei to be run to zero. At zero all nuclei from the script have been run and the result (PASS/Error) is displayed on the local display of the DVD player. When the dealer script has been completed, the results are displayed in the following manner: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CL96532111_018.eps 071099 local keyboard on the DVD player. Which keys can be used for this purpose is described with each test. Module test (with user interaction) During the first phase of the dealer test, the three main modules (Digital PWB, Display PWB and Basic Engine) are tested; some interaction from the user is required. 1. Testing the Display PWB This involves testing the local display and keyboard, but also testing the remote control and the leds. The Display Test During the display test, different patterns will be shown on the local display of the DVD player. The user needs to step through these patterns using the PLAY key on the local keyboard. If any of the displayed patterns is incorrect, the display test has failed, and also the player test has failed. The test patterns on display will be repeated in a loop (stepped through using PLAY) until the user presses NEXT on the local keyboard to proceed to the next test. The LED Test Next is the LED test; the LEDs on the DVD player are lit. Pressing PLAY will indicate that all LEDs are operational. To indicate that a LED did not light up, the user must press the PAUSE key. Pressing PLAY or PAUSE will proceed the user into the next test. The Keyboard Test During the keyboard test, the user needs to press all the keys on the local keyboard one by one. On the local display each key is represented by its scancode (a hexadecimal 2-digit code identifying the key to the DVD player). Pressing a key will show its representing code on the local display of the DVD player: the first hexadecimal digit identifies the key pressed, the second indicates how many times this particular key was detected. In case the key is pressed more than once, the scancode is displayed as many times, with the second digit of its code increased each time. The display of scancodes scrolls from right to left, with the most recent scancode at the right. The following example gives a possible layout of the local display during the display/remote control test: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + CL96532111_019.eps 071099 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + Termination To turn off the dealer test, the DVD player must be powered down. 5.10.2 Player Script Set-up physical interface components Hardware needed: • DVD player • television set, connected to the DVD player • 6 audio speakers • an external video source Activation To activate the player script, press OPEN, CLOSE and STOP keys on the local keyboard of the DVD player simultaneously during power-on. Usage The player test requires human interaction to decide whether nuclei give correct output, e.g. the user needs to confirm the results of the display test. This needs to be given through the CL 96532097_004.eps 130999 To terminate the keyboard test, press the NEXT key on the local keyboard of the DVD player and keep it pressed for 1 (one) full second. The keyboard test will terminate with a message on the local display. In case the keyboard test was successful, the message is: 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + CL 96532097_007.eps 130999 In case the keyboard test was not successful, the message will be: Test instructions mono board DVD-ASD1 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ CL 96532097_008.eps 130999 If the "tbFAIL"-message is displayed, the player test has failed. This is the end of the player test: turn off the DVD player, or press NEXT on the local keyboard of the DVD player to proceed to the next test. The remote control test For the remote control test, the user must press a key (any key) on the DVD's remote control. The display at the start of the test looks as follows: ASD-1 5. GB 21 1 ⋅2 ⋅3 ⋅4 ⋅5 ⋅6 ⋅7 ⋅8 ⋅9 ⋅1 0 ⋅1 1 ⋅1 2 ⋅1 3 ⋅1 4 ⋅1 5 + CL 96532097_012.eps 130999 if the test fails. Pressing NEXT on the local keyboard again will proceed to the next test. 2. Testing the Monoboard The picture tests involve putting a predefined picture on the connected television set, and asking the user for confirmation. When the picture has been put on screen, the local display asks for confirmation by the user as follows: 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + CL 96532111_032.eps 071099 When a remote control code has been received, its scancode is displayed as follows: 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + CL 96532097_013.eps 130999 If the user presses PLAY, he confirms the test; pressing PAUSE will indicate a fault in the test. At this time, the player test had failed and the DVD player can be switched off, or the user can proceed to the next test by pressing NEXT on the local keyboard of the DVD player. Pressing the NEXT key on the local keyboard will start the next picture test (Colour set-up functional test). When the picture tests are finished, the sound tests are run. A predefined sound will be generated, and again the user is asked to confirm this. The local display looks as follows: CL 96532097_009.eps 130999 The NEXT key can be pressed to exit this test. However, if the user requires to test all keys on the remote control, (s)he can continue to press keys and these will all be displayed on the local display. With a code-table at hand this test can be used to test the full functionality of the DVD's remote control. When the user has pressed NEXT on the local keyboard (NOT on the remote control!), the result of the remote control test is shown on the local display as follows: 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + CL 96532097_011.eps 130999 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + CL 96532097_014.eps 130999 Pressing PLAY confirms the test, PAUSE indicates test failure. If the test is faulty, the player test failed and the DVD player can be shut off. Subsequent sound tests will be numbered in ascending order. Pressing NEXT on the local keyboard of the DVD player will take the user into the next test. 3. Testing the Basic Engine Most tests on the basic engine require user interaction. When the basic engine tests are started, the version of the basic engine which is present in the DVD player is shown on the local display, as follows: in case of succes; 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + CL 96532097_015.eps 130999 GB 22 5. Test instructions mono board DVD-ASD1 ASD-1 The version number is displayed in decimal representation (the underscore replacing the dot). When the user presses NEXT on the local keyboard, the tests on the basic engine are started. First, the tray operation is tested. The user can move the tray in and out by pressing the PLAY or PAUSE key on the local keyboard (both keys have essentially the same function). The results need to be checked visually by the user, the software cannot detect any faults. The local display looks as follows: 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + CL 96532097_019.eps 130999 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + CL 96532097_016.eps 130999 To indicate this is a test of which the result is to be checked by the user, the first word on the local display is "do". Except for testing the tray, this test is also meant to give the user the opportunity to put a disc into the DVD player for subsequent basic engine tests. Some of the following tests need a disc in the DVD player to operate properly. Always put a disc into the DVD player during this test! At the end of the basic engine tests there is opportunity to remove it (before the looptests start). Pressing the NEXT key on the local keyboard proceeds to the next test. Second test is the sledge test; the user is asked to move the sledge by using the keys PLAY and PAUSE on the local keyboard (both keys have essentially the same function). This test needs to be checked visually by the user; the software cannot detect any faults. The local display during this test looks as follows: By pressing PLAY the user confirms successful focussing by the basic engine; pressing PAUSE indicates a fault in the focus function. Pressing NEXT on the local keyboard starts the radial function; the local display looks as follows: 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + CL 96532097_020.eps 130999 Again, PLAY confirms the result, PAUSE indicates an error. After pressing NEXT on the local keyboard, the grooves/jump test is started. As this is also a test that cannot be checked by the software, the user needs to perform a visual test. The local display looks as follows: 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + CL 96532097_021.eps 130999 CL96532097_017.eps 130999 After pressing NEXT on the local keyboard the discmotor is tested; the local display looks as follows: 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + By pressing PLAY the next grooves/jump position is taken; pressing PAUSE will go to the previous grooves/jump position. Switching through the different positions is done in a cyclic manner. Press the NEXT key on the local keyboard to proceed to the last basic engine test: again, the tray is tested. This has been done at the beginning of the basic engine test already, the repeat is only meant to enable the user to remove the disc in the tray before proceeding. The local display will look as follows: CL 96532097_018.eps 130999 The user is required to listen if the disc motor is running; this must be confirmed by pressing PLAY on the local keyboard. The PAUSE key is used to indicate the discmotor does not run. Pressing NEXT on the local keyboard starts the focus test. The local display looks as follows during this test: 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + CL 96532097_016.eps 130999 Press PLAY or PAUSE to operate the tray; remove the disc in the tray. The tray will be closed automatically (if needed) before proceeding to the next tests (by pressing NEXT on the local keyboard). Read Error Log Test instructions mono board DVD-ASD1 The contents of the error log will be displayed on the local display, as follows : ASD-1 5. GB 23 The leftmost three digits indicate which of the DVD player's modules is faulty; the explanation is in the following table: Note: This is an example only; no actual errorcode is intended Displayed Value Indication for each module Loader 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ CL 96532097_022.eps 130999 The first two characters on the local display ("EL") indicate that the read-out mode of the error log is activated. After the hyphen 8 hexadecimal digits (one faultcode) are displayed. Below the row of 7-segment displays the highlighted number indicates the number of the faultcode being displayed. (Not for DVDv2B) The highest number indicates the oldest faultcode. If, in the future, more than 15 faultcodes need to be displayed, the "+" character can be used to indicate the display of a faultcode in the range 16 - 30. To step through the different fault codes, the PLAY (next) and PAUSE (previous) key on the local keyboard can be used. The display of faultcodes is cyclic. If the error log does not contain any fault codes, all displayed error codes will be "000 00000". To switch off the display of the error log, the NEXT key must be pressed on the local keyboard. Read Error Bits The error bits are used to indicate that an error occurred once or more times; if that is the case the bit representing the error is set. To read out this field of error bits, the local display is used. Only the numbers of the errors where the bit is set will be displayed on the local display. The layout of the local display is (globally) as follows2: 000 001 010 011 100 101 110 111 ok ok ok ok faulty faulty faulty faulty Monoboard ok ok faulty faulty ok ok faulty faulty Display PCB ok faulty ok faulty ok faulty ok faulty CL 06532065_052.eps 230500 After the hyphen the (decimal) number indicates the number of times the looptest was performed. The right side of the display shows an error code DNER (in decimal representation), which is built from a nucleus number (DN) and an error number (ER). This code indicates the last nucleus that returned an error code. For explanation of this DNER code, see document [SDD_DN]. Pressing NEXT on the local keyboard of the DVD player will exit this loop and show the end result of the player test. End result of the player test is equal to the last display shown above: it shows which module is faulty and which nucleus caused the last error, as well as how many loops were performed. Termination To terminate the player test, switch off the DVD player. 5.11 Download Interfaces (not for service) 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + CL 96532097_023.eps 130999 The number of the set bits is displayed in a cyclic manner. Scrolling through the set error bits can be done with the PLAY key for 'next' and PAUSE key for 'previous'. Pressing the PLAY key at the last bit number will display the first bit number again, pressing the PAUSE button at the first bit number will display the last bit number in the list. The representation of bit numbers is decimal. If no error bits are set, the number on the right side of the display will be "00" Module Looptest The module looptest is an infinite loop in which a number of nuclei are executed over and over again. The nuclei run are the same as in the dealer test; user interaction is not required. During this looptest, the display looks as follows3: The download interface enables the user to download another version of diagnostic software into the RAM of the DVD player. The downloaded software will overrule the software which is placed in the DVD player's ROM; running the original diagnostic software is disabled until the DVD player is switched off and on again. For download of diagnostic software, the RS232 port may be used. 5.11.1 Set-up physical interface components Hardware required: • Service PC • one free COM port on the Service PC • special cable to connect DVD player to Service PC The service PC must have a terminal emulation program (e.g. OS2 WarpTerminal or Procomm in Windows95) installed and must have a free COM port (e.g. COM1). Activate the terminal emulation program and check that the port settings for the free COM port are: 19200 bps, 8 data bits, no parity, 1 stop bit and no flow control. The free COM port must be connected via a special cable to the RS232 port of the DVD player. This special cable will also connect the test pin, which is available on the connector, to ground (i.e. activate test pin). 5.11.2 Activation 1 ⋅ 2 ⋅ 3 ⋅ 4 ⋅ 5 ⋅ 6 ⋅ 7 ⋅ 8 ⋅ 9 ⋅ 10 ⋅ 11 ⋅ 12 ⋅ 13 ⋅ 14 ⋅ 15 + CL 96532097_025.eps 130999 Switch the DVD player on and the following text will appear on the screen of the terminal (emulation program): GB 24 5. Test instructions mono board DVD-ASD1 ASD-1 DVDv2 Diagnostic Software version 1.0 SDRAM Interconnection test passed Basic SDRAM test passed Karaoke init OK (M)enu, (C)ommand (S)2B-interface or (D)ownload? [M]:@ D CL96532111_028.eps 071099 Progress seen by the diagnostic software is indicated by displaying the character "*" on screen repeatedly; if the download software encounters an error, the end of the downloaded file will be awaited and instead of the "*"character, the "+"- character will be used to indicate (erroneous) progress. When download is finished, the following message will come from the DVD player: Download succesful Press return to start downloaded program... CL96532111_029.eps 071099 When the user then presses a key, the DVD player will report The scripts that can be made externally are therefor in one of the following two forms: 1. A Procomm or Telex script Procomm or Telex can be used to write diagnostic scripts. The script language of both communication packages contains possibilities for construction of loops and branches in the scripts. Commands then going over the line will be exactly the same as described in the chapter "Command Interface". The diagnostic software (the engine) will receive normal RS232 commands and processes these as defined, sending results of these nuclei back over the RS232 line. In the Terminal the Procomm or Telex script determines which command sequence is followed 2. An Asterix-script Asterix-scripts are C-programs in which commands are sent to the diagnostic software (the engine). The construction of branches and loops is again located in the remote machine, i.e. the Asterix machine. Commands going over the line will be exactly the same as described in the chapter "Command Interface". The diagnostic software (the engine) will receive normal RS232 commands and processes these as defined, sending results of the called nuclei back over the RS232 line. In the Asterix PC the C-program determines which command sequence is followed. Layout of menus and submenus for the Service Terminal NOTE: a symbol "-->" in the next menu layouts indicates that that specific menu choice will invoke the display of a submenu. This symbol will also be used in the implementation of the menus (i.e. the "-->" will also appear in the user interface). Main Menu MAIN MENU 1. Audio --> 2. Basic Engine --> 3. Display PWB --> 4. Processor & Peripherals --> 5. Karaoke --> 6. Log --> 7. Miscellaneous --> 8. Video --> First Level Submenus DVD Diagnostic Software version X.X CL96532111_030.eps 071099 and start to run the downloaded software. Note1 : The DVDv2B player has no power-ON key, but should be turned on by connecting the power-cable. Note2 : For players without DRAM, the DRAM-tests will be scipped. 5.11.3 Usage The usage of the downloaded software depends on the contents of that software and cannot be described here. 5.11.4 Termination (not for service) To exit the download-interface and remove the downloaded software from the DVD player, switch off the DVD player. External Scripts A script is a sequence of nucleus calls. Internal scripts (e.g. scripts built into the diagnostic software itself) are in the form of a C-language module. However it cannot be expected from a customer to write C-modules in order to create new scripts. AUDIO MENU 1. Deemphasis --> 2. Mute --> 3. PinkNoise --> 4. SineWave --> BASIC ENGINE MENU 1. Disc Motor --> 2. Focus --> 3. Grooves --> 4. Radial --> 5. Reset [44] 6. Sledge --> 7. Tray --> 8. Version [37] DISPLAY PWB MENU 1. Display [30] 2. Keyboard [27] 3. LEDs [29] 4. Remote control [28] 5. Version [28] LOG MENU 1. Read last errors [31] 2. Read error bits [32] Test instructions mono board DVD-ASD1 3. Reset [33] PROCESSOR AND PERIPHERALS MENU 1. Clock --> 2. DRAM Write/Read [9] 3. Flash --> 4. I2C --> 5. S2B --> 6. SDRAM Write/Read [16] MISCELLANEOUS MENU 1. NVRam Utils --> 2. PalNtsc Line --> (Not for DVDv2B) 3. 2B Utils --> 4. Statistics Info --> 5. Read Application Version [46] VIDEO MENU 1. Colourbar --> 2. Scart --> KARAOKE MENU 1. Karaoke Mode Off [48a] 2. Karaoke Mode On [48b] 3. KaraokeMicInput [49] 4. KaraokeKey On [50a] 5. KaraokeKey Off [50b] 6. Karaoke Echo On [51a] 7. Karaoke Echo Off [51b] Second level submenus DEEMPHASIS MENU 1. Deemphasis 0 On [18a] 2. Deemphasis 0 Off [18b] 3. Deemphasis 1 On [18c] 4. Deemphasis 1 Off [18d] for DVDv2B: 1. Deemphasis On [18a] 2. Deemphasis Off [18b] 3. Deemp 0 Tristate On [18e] 4. Deemp 0 Tristate Off [18f] 5. Deemp 1 Tristate On [18g] 6. Deemp 1 Tristate Off [18h] MUTE MENU 1. Mute On [19a] 2. Mute Off [19b] PINKNOISE MENU 1. Pinknoise On [20a] 2. Pinknoise Off [20b] SINEWAVE MENU 1. Audio Sine On [21a] 2. Audio Burst On [21b] DISC MOTOR MENU 1. Disc Motor On [39a] 2. Disc Motor Off [39b] FOCUS MENU 1. Focus On [38a] 2. Focus Off [38b] GROOVES MENU 1. Jump Grooves to Inside [42a] 2. Jump Grooves to Middle [42b] 3. Jump Grooves to Outside [42c] ASD-1 RADIAL MENU 1. Radial Control On [40a] 2. Radial Control Off [40b] SLEDGE MENU 1. Sledge Inwards [41a] 2. Sledge Outwards [41b] TRAY MENU 1. Open Tray [43b] 2. Close Tray [43a] LASER MENU 1. Laser Cd On[58a] 2. Laser Cd Off[58b] 3. Laser DVD On[58c] 4. Laser DVD Off[58d] UCLOCK MENU 1. µClock A_CLK in CDDA Mode [7a] 2. µClock A_CLK in DVD Mode [7b] FLASH MENU 1. Checksum FLASH [6] 2. Flash write access [10] I2C MENU 1. I2C NVRAM Access [11] 2. I2C Display PWB [12] S2B MENU 1. S2B Echo [13] 2. S2B Pass-through [14] NVRAM MENU 1. NVRAM Config [34] 2. NVRAM reset [35] 3. NVRAM Mod [36] 4. NVRAM write/read [15] PAL/NTSC MENU (Not for DVDv2B) 1. PalNtscHi [45a] 2. PalNtscLo [45b] 2B UTILS MENU 1. I2C Scart Check [54] 2. Scart to DVD [55a] 3. Scart Pass through [55b] 4. VideoColSetupI2C [52] 5. VideoColSetupHi [53a] 6. VideoColSetupLo [53b] VIDEO COLOURBAR MENU 1. Colourbar DENC On [23a] 2. Colourbar DENC Off [23b] SCART MENU 1. Scart Low [25a] 2. Scart Medium [25b] 3. Scart High [25c] STATISTICS INFO MENU 1. Total Nr of Times Tray Open [47a] 2. Toat Time Power On [47b] 3. Total Play-time CDDA & VCD [47c] 4. Total Play-time DVD [47d] 5. GB 25 GB 26 5. ASD-1 Test instructions mono board DVD-ASD1 Screen layout with menus When menus are used, no specific screen layout can be given: menu information will not be in a special format, except for the layout as mentioned in the previous paragraphs. A typical menu session can look as follows: ---------------< top of screen >------------------------------------------DVDv2 Diagnostic Software version 1.0 SDRAM Interconnection test passed Basic SDRAM test passed Karaoke init OK (M)enu, (C)ommand, (S)2B-interface or (D)ownload? [M]:@ M <-MAIN MENU 1. Audio --> 2. Basic Engine --> 3. Display PWB --> 4. Processor & Peripherals --> 5. Karaoke --> 6. Log --> 7. Miscellaneous --> 8. Video --> Select> 4 <-PROCESSOR AND PERIPHERALS MENU 1. Clock --> 2. DRAM Write/Read [9] 3. Flash --> 4. I2C --> 5. S2B --> 6. SDRAM Write/Read [16] Select> 6 <-------------------< bottom of screen >---------------------------Depending on the height of the screen, the text will start scrolling off the top of the screen. Layout of Results diagnostic nuclei on control/service PC Results returned from a Diagnostic Nucleus to the control/ service PC will have a maximum length of 300 characters and are terminated by a CR character (included in the string length) The result has the following layout < number >< string > [OK l ER] @< CR > The use of the "@" enables the Asterix system on the Control PC to parse the output string of each nucleus into a database. < number > is a 4-digit decimal number padded with leading zeros if its value is less than 4 digits. The first two digits identify the generating nucleus (or goup of nuclei), the latter two digits indicate the error number. < string > is a text string containing information about the result of the Diagnostic Nucleus. < number > and < string > are defined in [SDD_DN] in the output sections of each Nucleus. Examples: 1. 0001 Unknown command ER @ 2. 3100 OK @ 3. 0901 Data line X is not connected to the DRAM ER @ CL96532111_031.eps 071099 Test instructions mono board DVD-ASD1 5.12 Diagnostic Nuclei ASD-1 Ref. Reference Name Remark 17 AudioSig Audio Signature (Optional) 18a AudioDeemp0On Audio De-emphasis 0 On AudioDeempOn (DVD2B) Audio De-emphasis On (DVDv2B) AudioDeemp0Off Audio De-emphasis 0 Off AudioDeempOff (DVD2B) Audio De-emphasis Off (DVDv2B) 18c AudioDeemp1On Audio De-emphasis 1 On (Not for DVDv2B) 18d AudioDeemp1Off Audio De-emphasis 1 Off (Not for DVDv2B) 18e AudioDeemp0Tristat eOn Audio De-emphasis 0 in tristate/bidirectional mode (DVDv2B) 18f AudioDeemp0Tristat eOff Audio De-emphasis 0 back in output mode (Off) (DVDv2B) 18g AudioDeemp1Tristat eOn Audio De-emphasis 1 in tristate/bidirectional mode (DVDv2B) 18h AudioDeemp1Tristat eOff Audio De-emphasis 1 back in output mode (Off) (DVDv2B) 19a AudioMuteOn Audio Mute On 19b AudioMuteOff Audio Mute Off 20a AudioPinkNoiseOn Audio Pinknoise On 20b AudioPinkNoiseOff Audio Pinknoise Off 21a AudioSineOn Audio Sine signal On/Off 21b AudioSineBurst Audio Sine signal Burst 56a AudioDeemp0On PIO-pins as used in 2A for Deemphasis 56b AudioDeemp0Off PIO-pins as used in 2A for Deemphasis 56c AudioDeemp1On PIO-pins as used in 2A for Deemphasis 56d AudioDeemp1Off PIO-pins as used in 2A for Deemphasis Remark 18b 5.12.1 Basic Diagnostic Nuclei Ref. Reference Name Remark 1 BasicSpAcc Serial port Access test/ initialisation 2b BasicInterconDram BasicInterconSdram GB 27 5.12.4 Audio Each nucleus contains an atomic and independent diagnostic test, testing a functional part of the DVD player hardware on component level. Each Nucleus returns a result message to its caller. Some tests (e.g. generating a colour bar) can only return an "OK" result. Internal communication will be done via a uniform interface between the diagnostic Engine, Scripts and the Diagnostic Nuclei. The diagnostic Engine can only operate if a certain (minimal) set of hardware is functioning properly. To test this set of hardware, a set of basic diagnostic nuclei is embedded in the DVD player. Each basic diagnostic nucleus will only test that part of the hardware which is required for execution of the diagnostic Engine, e.g. a RAM test will only test that part of RAM that is used by the diagnostic engine. After the Diagnostic Engine is operational it is possible to do a full RAM diagnostic. All basic diagnostic nuclei start with prefix 'Basic'. In the overview each Diagnostic Nucleus consists of a reference number, a reference name and remarks. Reference number and name are coupled and one of them is enough for unique identification. The reference number can be used to find the description of the Diagnostic Nucleus in paragraph Error! Reference source not found..# where # is the reference number. 2a 5. Data and address bus Interconnection (only for DVDv2A) Data and address bus interconnection 3 BasicDramWrR DRAM Write Read (only for DVDv2A) 4 BasicSdramWrR SDRAM Write Read 5 BasicSramWrR SRAM Write Read 5.12.2 Processor and Peripherals Ref. Reference Name Remark 6 PapChksFl Checksum FLASH 7a PapUclkAclkCdda uClock A_CLK in CD-DA mode 7b PapUclkAclkDvd uClock A_CLK in DVD mode Ref. Reference Name 23a VideoColDencOn Colourbar DENC On 9 PapDramWrR DRAM Write Read (only for DVDv2A) 23b VideoColDencOff Colourbar DENC Off 10 PapFlashWrAcc FLASH Write Access 25a VideoScartLo Scart Low 25b VideoScartMi Scart Medium 25c VideoScartHi Scart High 52 VideoColSetupCom Colour Setup Communication 53a VideoColSetupHi Colour Setup High 53b VideoColSetupLo Colour Setup Low 54 VideoScartSwCom m Scart Switch communication 55a VideoScartSwDvd Scart Switch Dvd 55b VideoScartSwPass Scart Switch Pass-through 11 PapI2cNvram I2C NVRAM access 12 PapI2cDisp I2C Display PWB 13 PapS2bEcho S2B Echo 14 PapS2bPass S2B Pass-through 15 PapNvramWrR NVRAM Write Read 5.12.3 Components Ref. # Reference Name Remark 16 CompSdramWrR SDRAM Write Read 5.12.5 Video GB 28 5. Test instructions mono board DVD-ASD1 ASD-1 Ref. Reference Name Remark Ref. Reference Name Remark 57a VideoScartPinLo PIO-pins as used in 2A for Scart-switching 40a BeRadialOn Radial control On 40b BeRadialOff Radial control Off 57b VideoScartPinMi PIO-pins as used in 2A for Scart-switching 41a BeSledgeIn Sledge Inwards 57c VideoScartPinHi PIO-pins as used in 2A for Scart-switching 41b BeSledgeOut Sledge Outwards 42a BeGroovesIn jump Grooves to Inside 5.12.6 DisplayPWB (slave processor) Ref. Reference Name Remark 26 DispVer Version number 27 DispKeyb Keyboard 28 DispRc Remote Control 29 DispLed LEDs 30 DispDisplay Display 5.12.7 Log (error logging in NVRAM) 42b BeGroovesMid jump Grooves to Middle 42c BeGroovesOut jump Grooves to Outside 43a BeTrayIn Tray In 43b BeTrayOut Tray Out 44 BeReset Reset Basic Engine 58a LaserCdOn CD Laser on 58b LaserCdOff CD Laser off 58c LaserDvdOn DVD Laser on 58d LaserDvdOff DVD Laser off 5.12.10 Karaoke Ref. Reference Name Remark 31 LogReadErr Read last Errors 32 LogReadBits Read errors Bits 33 LogReset Reset Ref. Reference Name Remark 48a KaraokeModeOff Switch Karaoke mode off 48b KaraokeModeOn Switch Karaoke mode on 49 KaraokeMicInput Check path from the microphone input to audio output 50a KaraokeKeyOn Set Karaoke Key to the maximum level (1200 cent) 5.12.8 Miscellaneous Ref. Reference Name Remark 34 MiscReadConfig Read Configuration area from NVRAM 50b KaraokeKeyOff Set Karaoke Key to flat octave (0 cent) 35 MiscNvramReset NVRAM Reset 51a KaraokeEchoOn Set Echo Control fuction on 36 MiscNvramMod Modify NVRAM contents 51b KaraokeEchoOff Set Echo Control function off 45a MiscPalNtscHi Check if PAL/NTSC line is high (Not for DVDv2B) 45b MiscPalNtscLo Check if PAL/NTSC line is low (Not for DVDv2B) 46 MiscApplVer Read version of application software 47a MiscTrayOpenNr Read the number of times the tray opened 47b MiscPowerOnTime Read the total time the player's power has been on 47c MiscPlayTimeCddaVcd Read the Playtime of CDDA and VCD discs 47d MiscPlayTimeDvd Read the Playtime of DVD discs 5.12.9 Basic Engine Ref. Reference Name Remark 37 BeVer Version number 38a BeFocusOn Focus On 38b BeFocusOff Focus Off 39a BeDiscmotorOn Discmotor On 39b BeDiscmotorOff Discmotor Off Note: A new Compair version for repair of the MONO boards will be developed. Block diagrams ASD-1 6. 29 6. Block diagrams Servo ASD1 BOARD SERVO PART LOADER CDM OPU 1 3 MEMORY CD-LASER DVDALAS2+ 7310 7102 S-RAM 132K TZA1033 CY7C199-15C 7110-7111 Var Gain MUX Diode Amplifiers Processing EQUALIZER DVD 15 1 CONTROL Header 8 ADDRESS HPSW DATA 4 7100-7106-7101 7311 Land 1104 DPD DVD-LASER MUX 6 CD FLEX 24P Push Pull Servo Signals Land/Groove Swap Mute Offset compensations RFo HF-IN D1-D6 6 3 Beam Tracking 2 CALF_MACE 4 +5 GND DECODER HD61 SAA7335HL/E/M2 O_CENTRAL 4 STB_DALAS V & I references Dual Laser MOTOR-IC Supply SILD FOCUS BA6856FP Serial SICL Laser#1 TACHO-OUT I/Face RADIAL 7304 SIDA Laser#2 B_V4 B_SYNC B_FLAG B_DATA B_BCLK B_WCLK I2S6 TO STi5505 ON DIAGRAM 5 3 MOTO-IN 1 DISK MOTOR 1301 M DRIVE HALL-FEEDBACK FLEX 11P HALL AD[0:7] SLEDGE MOTOR BLOCKDIAGRAM DIGITAL PART 1106 2 7207 CONTROL LINES ADC SERVO MACE2 SAA7399 PCS-PRE-AMPL 7104 TRAY MOTOR LM833D uP (8051 CORE) FLASH ROM 7202 PSENN AD[0:7] AD[0:7] A[0:16] AM29F002 PHI-INPUT M CONTROL BUS FLEX 8P HALL DATA/ADDRESS BUS 6 MHz M 2 PCS 4 END-SWITCH REF A[8:16] 2 ADRESS LATCH 7201 DRIVERS 7103 BA5938FM SLEDGE AD[0:7] A[0:7] 2 74HCT573D RADIAL TXD_BE RXT_BE CFR SUR SERVO OUTPUTS 4 FOCUS 5 TRAY-SWITCH POR 1100 TRAY1 4-WIRES S2B 4 t RSTN TO/FROM STi5505 ON DIAGRAM 5 TRAY2 4 8.46 MHz 1 4268_136 2012 CL06532065_036.eps 180500 Block diagrams ASD-1 6. 30 Didital ASD1 BOARD DIGITAL PART 6 5 TXD_SER RXD_SER RTS_SER CTS_SER 4 7600 CONN. 1602 4 SERVICE SERVICE SERIAL INTERFACE CONN. 1603 SERVICE 7503 2 DEEM[0:1] RSTN S2B 4 TO /FROM MACE2 (DIAGRAM 2) TXD_BE RXD_BE CFR SUR 7604, 7607 SCART[0:1] UART UART PROGRAMMABLE I/O OSD SCART 0/6/12V MUTE 0_6_12V 7608,7609,7610 MUTE_AV MUTE I2S 6 B_V4 B_WCLK B_DATA B_BCLK B_FLAG B_SYNC DEMULTIPLEXER VIDEO 3V3 DIG_OUT 5V R_OUT G_OUT B_OUT C_OUT CVBS_OUT Y_OUT VIDEO ENCODER MPEG DECODER ACLK CVBS RGB S-VHS 6 R/C G B/CVBS CVBS/Y 7612-7618 VIDEO FILTER BUFFER SUBPICTURE PCM__CLK HOST ST20 4 P50 7616 +5V -5V CLOCK SYNTHESIZER SEL_ACLK MK2742 CONN. 1604 STi5505 2 SDRAM CONTROLLER I2C CONTROLLER SDA SCLK 2 SDA SCLK RESETN Y-C +3V3 +6Vstby +12Vstby -8Vstby PCMout1 PCMout2 HSYNC I2C MEMORY INTERFACE TO/FROM A/V-MUX BOARD 7611 PCM (3X) DIG. OUT 4 PCM_CLK FRONT END INTERFACE BCLK DATA WCLK 3 SCLK PCM_OUT0 LRCLK SPDIF_OUT AUDIO DECODER AUDIO FROM HD61 DECODER (DIAGRAM 3) 2 TO A/V-MUX BOARD 2 OPTION 7504 CONN. 1600 +3V3 27 MHz SDRAM INTERFACE SYSTEM CONTROL BUS SYSTEM ADDRESS BUS SYSTEM DATA BUS +5V POWER SUPPLY +5Vstby -8Vstby 7505 +6Vstby EEPROM 2 +12Vstby ST24E32M6 STB_CONT P50 4 7401 16Mb FLASH AM29LV160BT 7404 16Mb SDRAM MT48LC1M16A1TG -7S 7405 SDA SCLK STB_CONT 2 16Mb SDRAM CONN. 1501 TO/FROM DISPLAY MT48LC1M16A1TG-7S 4268_136 2012 CL06532065_037.eps 180500 Electrical diagrams and PWB’s ASD-1 7. 31 7. Electrical diagrams and PWB’s SERVO DALAS 1 2 3 4 5 6 7 8 9 10 11 12 13 3118 F114 3119 3197 2R2 3137 VCC1 GND2 MT1 100n 2117 F142 3131 2R2 2R2 3132 3133 2R2 2R2 FOC+ FOC- 7114 F174 F175 S2 A1_MACE +5Vx +5Vx F157 22K 2119 3148 F189 5 8 7105-B MC34072 7 2.5V 2.5V 3177 68K 2139 100n 120R 15K 3165 3176 3181 100n 3168 F179 10M SLSL+ VO2VO2+ V-REF H 2123 F172 OPTION F199 120K 4 100n 2.0V 2138 100n CALF_MACE 2 100R STB_DALAS ALPHA0 8 7105-A MC34072 1 F198 22R 3158 STB NC4 V-REF 3 6 4 3194 G 2137 F022 100n F197 F163 3153 OPTION 3120 1K +5V 39K F191 3173 100K 2142 10n +3V3S 3166 2.0V E 7116 BC847B 3174 F178 +5V 3179 220R BC847B F S1 6K8 LPF-DPD1 38 3186 O-CENTRAL 7115 BC857B +5V 220R NC5 NC6 RF-REF COP VSSD SILD 28 4R7 F152 47R 3140 RFP RFN VSSA3 SIDA F013 SILD +3V3S SL3187 29 30 2R2 1.5V SL+ SICL F012 F176 1.5V F011 3130 GND3 3183 100R 22n 47R 2R2 F151 F195 1R 100K 2141 +5A4 FTC 33 +5V 3185 3180 22p VSSA2 VDDD3 HEADER 3178 4 I 100n 12K R-EXT VDDA2 CD-LO F023 +3V3D OPTION OPTION 12K 3161 F021 LPF-DPD2 39 +5D F193 F192 COSPH 6 NC2 V-REF 14 C 03 F024 2140 7104-B LM833D 7 100n LAND 1R 8 2124 S1 42 04 TD1 35 2136 5 F169 10K 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2135 +5V 1 3157 3159 TDO 34 V-REF 2133 22p 15p 100K 2130 2131 3 2 F168 TD2 37 HEADER 17 FO 2127 RADRAD+ FOCFOC+ 330R 16 DVD-REF VO3- 3193 +9V F137 7113 BC847B 3182 1K 3138 F188 18 12K 3155 10K F166 22n 15 DVD-D 100R Ax 3172 F165 F036 10K 3143 F186 VO3+ X2 MT +5V +5V 2118 3171 100R X2 F039 3199 FTC-REF 36 14 DVD-C O1 180p F185 22K +5V 7112 BC847B F037 RFP 12K 3152 OPTION 2129 F183 15p 6 3169 100R 3127 19 O2 10K O-CENTRAL 40 100n D 13 DVD-B F159 VSSA4 43 3 BEAM TRACKING 100R 3170 C O-D 45 MUX SINPH 2 12 DVD-A 10K3147 VDDA4 44 DPD PUSH PULL OFFSET COMPENS. 10 DVD-MI F180 F158 S2 41 9 VSSA1 3167 12K O-C 46 LAND/ GROOVE MUTE 11 NC1 B F182 F156 O-A 48 SWAP LAND 7104-A LM833D 1 3146 3149 8 VDDA1 F016 +5A1 2125 2132 8 100n F155 560R 100R RA +3V3S 3124 470R F038 3145 O-B 47 7 CD-F SICL 2R2 F173 3122 20 F133 VIN3 LOGIC TRAY X2 B 3192 27K VREF MT2 X2 F035 180p 6 CD-E 3162 F120 3121 2111 100n 3198 470R OPTION DIODE AMPLIFIERS PROCESSING 23 F123 470R +5V 1.5V 2128 22n F171 OPTION 3136 4 CD-D 5 CD-REF MON2 4 F190 F167 2122 22n 3 F181 F187 3156 100R 24 RAD+ D RFo 1105 +5A3 VAR GAIN 100R 3164 100n 4 3 CD-C +5V F177 5 F164 3160 2126 F184 100R 3154 100R E F +5V 3163 27K 2 CD-B 2R2 100p F020 F194 REFSIN 1 CD-A F162 SIDA F170 F161 F196 D Ax F 3150 3151 100R B C 2R2 F146 2113 100n 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 MUX 2121 220n 100n +5V 2120 24 OPTION LD-DVD VDDL MON2 F160 23 3142 7102 TZA1033 CD-MI 4R7 F154 22 F017 LD-DVD TM 91R +5L 3139 F015 2116 NC3 3144 21 F153 +5V 1R +5V V-REF 3115 TRAY1 F145 2114 RFP 15p 20 F150 3141 DVD-LO F149 19 100n F018 18 2115 +5L 2R2 3114 + - VOLTAGE CONTROL FWD 3K9 3129 3135 E VCC2 VCC3 3188 390R F109 68p 390p 2108 2107 180R 3117 3123 680R 4n7 47u 2104 2103 1K5 3103 F107 OPTION 1 6 NC2 1n +5A2 NC7 MON1 VDDD5 F 3134 330R 3175 2R2 F148 VIN4 BIAS - MUTE TRAY2 3184 16 +5V NC8 F147 LDCD 25 + - 15 16 8 VDDA3 15 D VIN5 5 NC1 VO2+ F139 COO C 17 TO LOADER 3196 12 VO2+ COM F144 RAD- 2R2 + F126 7 MUTE 9 NC3 330p 14 2134 TO / FROM LOADER 13 CL06532065_038.eps 180500 3195 REFCOS 27K 1 - + F125 +5V 26 4 VIN2 OPTION F019 B 3108 3107 F115 VO4+ F118 3191 F119 3 VIN1 13 VO2- F143 7 X2 SL VO2- 12 1106 52271-XX90 8 X2 Ax F141 +3V3S 2 VOL+ SL+ F140 11 F108 27 VO4- X2 11 NC5 LDCD 10 X2 SL- 7111 BC847B F134 2112 F138 MON1 8 E 1 VOL- 21 10 22 47R 10K F136 A 7103 BA5938FM GND1 7 91R 2101 100n REV 3128 47R F104 3 7106 BFS20 2 +9V 2 RAC-SW F132 3126 6 F135 47R 3 7101 BFS20 2 3110 1 F129 RAD- 7110 BST82 10K FOCFOC+ 1n5 F127 F128 2109 3 +12Vstby F113 1 3112 150R F122 RAD+ 4 F112 3111 7100 BFS20 OPTION F131 2 F124 2105 22p 3104 390R F101 OUT GND 2100 100n F102 10K F014 2110 2n2 F121 9 H 22p HPSW 1 5 F130 G 2106 IN 47R F106 3K9 2145 220p 3116 2144 220p 1104 C 3190 VO22143 220p B D 3189 VO2+ 3125 F116 8K2 F111 4 3113 1100-4 TRAYSW 3 +12Vstby 3106 15p 1100-3 47p F110 2 3101 1K5 F103 2102 F117 1100-2 1 F105 10K 1100-1 7109 L78M09 1 3 OPTION 3102 OPTION 3105 A TO / FROM LOADER +5V 4R7 3100 +5V 2 3 4 5 6 7 8 9 10 11 12 I 1100-1 A1 1100-2 A1 1100-3 A1 1100-4 A1 1104 B1 1105 D8 1106 G1 2100 A9 2101 A10 2102 A3 2103 A5 2104 A6 2105 A7 2106 B3 2107 B6 2108 B6 2109 B3 2110 B3 2111 B11 2112 C4 2113 D8 2114 D7 2115 D5 2116 E4 2117 E6 2118 G9 2119 G10 2120 E2 2121 E2 2122 F4 2123 H10 2124 F7 2125 G3 2126 G2 2127 I10 2128 G8 2129 G8 2130 H2 2131 H3 2132 H3 2133 H4 2134 H3 2135 H4 2136 H5 2137 G12 2138 H6 2139 I8 2140 I6 2141 I2 2142 F11 2143 B1 2144 B2 2145 B2 3100 A5 3101 A6 3102 A5 3103 A4 3104 A7 3105 A2 3106 A7 3107 A12 3108 A12 3110 A8 3111 A5 3112 A6 3113 B4 3114 B12 3115 B12 3116 B4 3117 B5 3118 B8 3119 B7 3120 F12 3121 B12 3122 B12 3123 B5 3124 B12 3125 C4 3126 C4 3127 C12 3128 C2 3129 C5 3130 C12 3131 C13 3132 D12 3133 D13 3134 D7 3135 D5 3136 D6 3137 D6 3138 G9 3139 E4 3140 E5 3141 E2 3142 E5 3143 G9 3144 E1 3145 E7 3146 E8 3147 E8 3148 G9 3149 E8 3150 E3 3151 E3 3152 E8 3153 H9 3154 F3 3155 F8 3156 F3 3157 F8 3158 H9 3159 F7 3160 F3 3161 F8 3162 F3 3163 F1 3164 F3 3165 I9 3166 G8 3167 G3 3168 I9 3169 G3 3170 G3 3171 G3 3172 G2 3173 F12 3174 G12 3175 H6 3176 H8 3177 H8 3178 I5 3179 E11 3180 I2 3181 I8 3182 F10 3183 F10 3184 I6 3185 I5 3186 I7 3187 I2 3188 A8 3189 A3 3190 A4 3191 B9 3192 B12 3193 C13 3194 H8 3195 I8 3196 B9 3197 C9 3198 D10 3199 E9 7100 A5 7101 A8 7102 E4 7103 A10 7104-A G2 7104-B H2 7105-A G12 7105-B G10 7106 A7 7109 A9 7110 C4 7111 C5 7112 E10 7113 E10 7114 E10 7115 D11 7116 E12 F011 I2 F012 I2 F013 I2 F014 B4 F015 E4 F016 F4 F017 E5 F018 E5 F019 D6 F020 D6 F021 F7 F022 G12 F023 H5 F024 H6 F035 E9 F036 E9 F037 E10 F038 E11 F039 E11 F101 A10 F102 A6 F103 A4 F104 A7 F105 A1 F106 A5 F107 A4 F108 A12 F109 A7 F110 A1 F111 A2 F112 A6 F113 A6 F114 A8 F115 B12 F116 A2 F117 B3 F118 B9 F119 B9 F120 B12 F121 B2 F122 B5 F123 B11 F124 B2 F125 B6 F126 B9 F127 B2 F128 C2 F129 C5 F130 C1 F131 C3 F132 C4 F133 C11 F134 C4 F135 C1 F136 C2 F137 C12 F138 C2 F139 C7 F140 C2 F141 D2 F142 D12 F143 D2 F144 D2 F145 D7 F146 D8 13 PB 4268 ASD1 MONO-BOARD 3104 123 4268.4 F147 D2 F148 D2 F149 E2 F150 E1 F151 E5 F152 D6 F153 E2 F154 E2 F155 E7 F156 E8 F157 G10 F158 E7 F159 E8 F160 E2 F161 E4 F162 E4 F163 H10 F164 F4 F165 F7 F166 F8 F167 F4 F168 F7 F169 F8 F170 F2 F171 F3 F172 H9 F173 F4 F174 F8 F175 F8 F176 G7 F177 G1 F178 G7 F179 I9 F180 G4 F181 G1 F182 G2 F183 G4 F184 G1 F185 G4 F186 G4 F187 G1 F188 G4 F189 G8 F190 H1 F191 H7 F192 H2 F193 H6 F194 I5 F195 I5 F196 I5 F197 G11 F198 G12 F199 I7 Electrical diagrams and PWB’s ASD-1 7. 32 SERVO MACE 4 5 6 7 CSTCC +3A 100n 3205 SINPH 2205 10K F215 3206 REFCOS 100n 10K REFCOS 126 COSPHI 128 ACT_EMFP 22K F220 1 ACT_EMFN 3243 3246 3242 127 PCS 5200 3202 1R +3A F298 CLOCK GEN. F202 DEBUG TEST A VddDp1 57 2203 100n VssDp2 95 VddDp2 96 43 31 VssDp4 VssDp3 32 VddDp4 VddDp3 44 11 21 VssDc2 12 22 VddDc2 VssDp5 109 VssAs VddDp5 110 VddAs VssDp6 68 119 VddDp6 69 120 VssDc1 82 F203 +3A +3A +3A +3A VssAop F209 MON_D 73 +3A 2228 100n VddAop F206 2227 100n +3A 100MHZ 3201 1R PB 4268 ASD1 MONO-BOARD 3104 123 4268.4 Port 4 H7 30 F212 H6 29 F214 H5 28 H4 27 26 25 H1|A17 24 F218 23 F219 TRAYSW 3240 10K AM(0:17) AM(17) SL Slegde control F226 3210 4K7 80 RP F227 70 RA F224 3K9 F230 3211 81 Radial control TL_FTL Port ROM 2 4K7 F233 F234 71 3214 FO Focus control 3K9 2210 1n 8051 A15 52 F222 A14 51 F223 A13 50 F225 A12 49 F228 A11 48 F229 A10 47 F231 A9 46 F232 A8 45 F235 F236 93 3215 92 10K DEFOn core Defect detector DEFIn I6 AD7 65 F237 AD6 64 F239 63 F241 AD5 115 FTCH 116 FTCL 79 E OTD Port RAM Track counter AD4 AD3 0 AD1 AD0 O1 106 D1|MIRN O2 107 D2|TLN 03 108 D3|REN 04 111 D4|FEN F258 112 S1 F261 113 S2 3219 3221 10K SFR Signal cond. Dx AM(11) 7201 74HCT573 AM(10) AM(9) 1 AM(8) 11 59 F249 58 F252 DSDen 78 RSTI 98 A1_MACE Port 1 NC1 2 NC2 3 NC3 36 NC4 37 GND 2208 10 F033 100n 19 F238 2 3 18 F240 AMD(2) 4 17 F242 AMD(3) 5 16 F244 AMD(4) 6 15 F246 AMD(5) 7 14 F248 AMD(6) 8 13 F251 AMD(7) 9 12 F253 AMD(4) AMD(3) AMD(2) AMD(1) AMD(0) 1D F254 3220 10K 10K PORN F257 CSI F259 OTD-HD61 ALE 3213 4R7 +5VC 100n 7202 M29F002 32 AM(0:17) AM(0) 12 A0 AM(1) 11 A1 AM(2) 10 A2 13 DQ0 AM(3) 9 A3 14 DQ1 AM(4) 8 A4 15 DQ2 AM(5) 7 A5 17 DQ3 AM(6) 6 A6 18 DQ4 AM(7) 5 A7 19 DQ5 AM(8) 27 A8 20 DQ6 AM(9) 26 A9 21 DQ7 AM(10)23 A10 AM(11)25 A11 AM(12) 4 1 A12 RP_NC AM(13)28 A13 24 G_ AM(14)29 A14 22 E_ AM(15) 3 A15 31 W_ AM(16) 2 A16 30 A17 F284 INT2 O-CENTRAL +3V3S 2215 22u +3V3S 4K7 3 4 5 6 7 AMD(4) AMD(5) AMD(6) AMD(7) +5VC F PSENn F260 WE G 6200 F286 2R2 BAS316 3234 3258 8K2 2214 22n 2216 1n BC857B 7203 3232 3235 100K 3227 4K7 H F281 3229 12K F285 1201 RSTN I F294 POR RFo INT WE WRI {CFR,SUR,RXD_BE,TXD_BE} 8 9 E AMD(3) +3V3S +3V3S HPSW STB_DALAS +3V3S +3V3S CL06532065_039.eps 180500 {ALE,PSENn,RDI,WRI,CSI,WE,OTD-HD61,POR,PORN,RSTN,INT,MOTO1,RFo,T1,T2,T3} 2 AMD(2) NC7 100 3236 F293 3257 F031 TXD_BE RXD_BE F030 p93-89 3238 10K F290 SUR F289 SIDA +5V AMD(1) +3A F295 RDI F296 CFR F292 TRAY2 F291 T1 TRAY1 I 3256 3255 E2 3228 10K p93-89 STBY 3230 10K AMD(0) 16 F270 13 PXT2en INT3|ALEh 14 PXT2 15 PXT0 F266 17 PXT1 18 F272 16 RDNH WRNH RXD1 F267 33 20 TXD1 F271 34 19 ATIP_IN E2 OPTION 3231 10K D NC8 101 H2 +5V 1 2209 F034 67 NC6 F032 3252 INT0_PWD F268 35 +5V 3251 3254 INT1 RXD2 39 TXD2 40 F269 38 RDN WRN TPWM 84 41 TEN 85 42 FOK CLO 87 I2CSCL F276 90 F277 86 I2CSDA F275 91 P6 104 F273 IREFT 3225 200K F283 3226 10K 114 VRH F274 105 ALPHA0 F282 +3V3S F029 LLP H9 F279 F278 94 ALPHAO LDON 4 F264 3224 2213 150R 100n 3253 ATIP_IN H 2212 100n 118 F265 10K 117 3237 +3A C1 20 NC5 ATIPin OPC_INT OPC SRV_INT_LGR PW 77 Port 3 Port 5 P6 88 124 ADC/ AGC ref. Laser control 89 CALF F280 A2 123 Uopt F027 122 F028 97 F025 A1 Uopb F263 121 CALF_MACE F026 3250 G Vcc F262 OPTION 3249 EN AMD(1) AMD(5) POR 3248 OPTION 3212 4R7 AMD(0) AMD(6) F247 10K 3223 11K AMD(7) 55 F256 3239 PSENn EAn interface 61 +5V +5V AM(12) ALE 53 F255 3247 PSENn System F243 F245 54 ALE Ex 62 60 AD2 F250 3222 11K AM(13) VSS p93-89 S2 AM(14) AMD(0:7) +3V3S S1 C AM(15) VCC F221 72 3208 3209 2207 1n+3V3S F B F216 H3|CSBN H0|A16 SILD SICL H2|CSDN XDET 2K7 2206 33n +3V3S D 14 VssDp1 56 3260 1R F288 22K OPTION SL FO 13 3244 RAD- RA SINPHI F217 OPTION C 9 3259 1R REFSIN 3241 COSPH RAD+ 125 12 F287 B REFSIN F207 2204 MON_A 74 F210 TS3 103 F201 3245 F200 F208 99 TS2 102 TS1 CLKOUT 76 RAC_SW 11 +3V3S +3A DEB_OUT 75 8 5 F213 6 F211 10 XTLI F299 2226 100n XXTLO RAC-SW 7 7207 SAA7399HL 1M 3204 330R 10 OPTION F297 SELPLL F204 A 9 +3V3S 3200 10K 1205 3203 8 +3V3S +3V3S VddDc1 83 3 2 F205 1 10 11 12 13 14 1201 I13 1205 A4 2203 A10 2204 B2 2205 B2 2206 C1 2207 D1 2208 D13 2209 D14 2210 D1 2212 H3 2213 H4 2214 H13 2215 H11 2216 H12 2226 A4 2227 A6 2228 A7 3200 A4 3201 A6 3202 A7 3203 A4 3204 A4 3205 B2 3206 B2 3208 C2 3209 C2 3210 C2 3211 D2 3212 D13 3213 D14 3214 D2 3215 D2 3219 F2 3220 F10 3221 F2 3222 F1 3223 F2 3224 H3 3225 H5 3226 H4 3227 H13 3228 I8 3229 H13 3230 H8 3231 H6 3232 H12 3234 I11 3235 I12 3236 H9 3237 H2 3238 I8 3239 F10 3240 B10 3241 B1 3242 C1 3243 C2 3244 C2 3245 A5 3246 C2 3247 F10 3248 G2 3249 G2 3250 G2 3251 H8 3252 H8 3253 H5 3254 H8 3255 I7 3256 I7 3257 I8 3258 I12 3259 A6 3260 A7 5200 A9 6200 H12 7201 D12 7202 D13 7203 H12 7207 A3 F025 G2 F026 G2 F027 G2 F028 H4 F029 H5 F030 I8 F031 I8 F032 H8 F033 D13 F034 D13 F200 A5 F201 A5 F202 A9 F203 A6 F204 A4 F205 A7 F206 A5 F207 A6 F208 A5 F209 A6 F210 A5 F211 A4 F212 B10 F213 B2 F214 B10 F215 B2 F216 B10 F217 B2 F218 C10 F219 C10 F220 C2 F221 C2 F222 C11 F223 C11 F224 C2 F225 C11 F226 C1 F227 C2 F228 C11 F229 D11 F230 D2 F231 D11 F232 D11 F233 D1 F234 D2 F235 D11 F236 D2 F237 D10 F238 D13 F239 D10 F240 D13 F241 E10 F242 E13 F243 E10 F244 E13 F245 E10 F246 E13 F247 E10 F248 E13 F249 E10 F250 E2 F251 E13 F252 E10 F253 E13 F254 F10 F255 F10 F256 F10 F257 F11 F258 F2 F259 F11 F260 F14 F261 F2 F262 F10 F263 G2 F264 H4 F265 H3 F266 H9 F267 H8 F268 H8 F269 H7 F270 H9 F271 H8 F272 H9 F273 H5 F274 H5 F275 H5 F276 H6 F277 H6 F278 H4 F279 H4 F280 H6 F281 H14 F282 H7 F283 H7 F284 H8 F285 H13 F286 H12 F287 I11 F288 I12 F289 I7 F290 I7 F291 I6 F292 I6 F293 I8 F294 I12 F295 I7 F296 I7 F297 A4 F298 A10 F299 B2 Electrical diagrams and PWB’s ASD-1 7. 33 Decoder 1 3 2 4 5 6 7 8 9 10 11 12 13 3300 F300 2300 CSTCC F306 +5VB +5VB +5VB F302 +5VB VSSD9 VSSD8 VDDD9 VSSD7 VDDD8 VSSD6 VDDD7 VSSD5 VDDD6 VSSD4 VDDD5 VSSD3 VDDD4 VSSD2 VDDD3 VSSD1 VDDD2 94 10 11 19 20 31 32 44 45 59 60 72 73 81 82 92 93 98 99 CRIN 95 CLOCK GENERATION CONTROL 21 TEST1 F309 RDA1 RDA2 22 TEST2 2K7 3K3 RDA3 25 NC3 3305 2K7 2305 3332 C RDA4 2304 F314 3 REFLO 22n RDA5 F316 4 REFHI 22n ANALOG DATA CAPTURE 5 VREF 3K3 6 HFIN 2319 3309 F319 2 IREF 27p 10K BIT DETECTOR RDA6 DEMOD RDA7 3339 F322 8 AGCOUT 43 DA0 41 DA1 AMD(1) AMD(3) AMD(5) AMD(7) 46 WRI WRI 8 RAMAD81 7 RAMAD91 6 A12 A11 A10 C A6 A4 RAMAD31 25 A3 RAMAD21 24 D A2 RAMAD11 23 A1 RAMAD01 21 A0 GND 14 RAD12 89 F333 RAMAD121 RAD13 90 F334 RAMAD131 E CFLG NC9 WCLK BCLK FLAG DATA RAD14 91 F335 RAMAD141 SYNC EBUOUT V4 SERIAL OUT INTERFACE STOPCLK T1 TACHO BLOCK T2 NC8 MOTO2|T3 MOTO1 NC7 MEAS1 NC5 CL1 36 NC4 NC6 49 CSI 22K INT 3310 +5V SCL E MOTOR INTERFACE 48 ALE ALE B RAD11 88 F332 RAMAD111 47 RDI RDI I|O2 RAMAD141 1 A5 RAMAD41 26 RAD8 84 F329 RAMAD81 RAD9 85 F330 RAMAD91 RAD10 87 F331 RAMAD101 33 DA7 I|O3 RAMDA21 13 A8 RAD7 83 F328 RAMAD71 34 DA6 AMD(6) I|O4 RAMDA71 15 RAMAD121 3 A7 RAMAD131 2 RAD6 80 F327 RAMAD61 SUB-CPU INTERFACE I|O5 RAMDA61 16 RAMAD101 5 A9 RAMAD111 4 RAD5 79 F326 RAMAD51 35 DA5 I|O6 RAMDA51 17 A13 RAD3 77 F324 RAMAD31 37 DA4 AMD(4) I|O7 RAMDA41 18 RAMAD71 RAD4 78 F325 RAMAD41 SDA D RAMDA31 19 RAMAD51 10 A14 RAMAD61 9 RAD2 76 F323 RAMAD21 39 DA3 A OE_ I|O0 RAD1 75 F321 RAMAD11 40 DA2 AMD(2) BCAIN AMD(0:7) AMD(0) 20 RAMDA11 12 I|O1 RAMDA01 11 RAD0 74 F320 RAMAD01 12 OTD DETECTOR F312 3331 120p 61 F305 RAMRW 71 F307 RAMDA01 70 F308 RAMDA11 68 F310 RAMDA21 67 F311 RAMDA31 66 F313 RAMDA41 65 F315 RAMDA51 64 F317 RAMDA61 63 F318 RAMDA71 WE_ CE_ NC10 2318 27 22 RRW 23 PORE +5VA 2307 22n 7 +5VB 100n VCC RAMRW 100n +5VB RDA0 22K 2306 10u F304 NC2 24 MUXSW +5V 3304 VSSA1 NC1 16 9 VSSA2 CROUT 7311 SAA7335HL 100 1 14 3330 +5VB 3302 220R VDDA2 2303 47u 2302 100n B 1M +5VA VDDD1 +5VA +5VA 2301 100MHZ +5VB 3301 VDDA1 F303 A +5V 100MHZ 5301 5300 4R7 28 7310 CY7C199 +5VB 1300 PB 4268 ASD1 MONO-BOARD 3104 123 4268.4 +5V F301 +5V +5V 3337 100R F347 3338 100R F343 B_BCLK B_WCLK F342 3336 100R F346 B_DATA 100R 3335 100R F345 F344 3334 B_FLAG 100n B_SYNC 3313 4K7 B_V4 3312 4K7 3333 2309 F348 F338 F336 F337 F341 3311 22K MEAS1 100R F F340 F339 38 27 28 29 30 42 26 97 51 13 15 62 17 18 50 52 53 54 55 56 57 58 69 96 86 F +5V +5V 2310 3317 F351 1R 3316 1R 6301 6303 6302 +12Vstby +5V 7304 BA6856FB 100n VCC A3 27 VM2 DRIVER 26 VM1 GAIN CONTROL S1D S1D S1D 28 RNF A2 5 A1 7 NC1 1 NC2 2 H1+ 9 4K7 3318 - + F355 H F357 STBY F358 3320 7315 BC847B 4K7 F360 2314 100n MOTO1 F361 3340 F362 3322 4K7 3323 4K7 F363 3324 100K 2315 100n +5V T1 23 PS 22 EC 21 + ECR - 20 CNF 19 VH 18 FG1 FG2 16 FG3 F371 T3 REV F368 17 T2 I 24 + - REV + - PS + - H BIAS H1- 10 NC3 4 NC4 6 H2+ 11 + - H2- 12 + + - NC5 15 H3+ 13 H3- 14 F350 11 F352 10 F353 9 NOT MOUNTED 2311 100n 2312 100n 2313 100n 6 F354 3319 F356 5 F359 47R MT2 MT1 GND 30 29 8 4 3321 6K8 2 F364 6K8 1 3326 47R F367 6K8 F370 3328 F372 22K 52271-1190 I 7312 BC857B 3329 22K F373 +5V +5V 1 2 3 4 5 6 7 8 9 10 11 12 H 3 F366 3327 8 7 3325 + - G 1301 3 TO LOADER F349 F369 G F365 25 CL06532065_040.eps 180500 13 1300 A6 1301 G13 2300 A11 2301 A8 2302 A5 2303 A5 2304 B5 2305 C5 2306 C2 2307 C3 2309 F7 2310 G11 2311 H12 2312 H12 2313 H12 2314 H8 2315 I9 2318 B3 2319 C4 3300 A11 3301 A6 3302 A7 3304 B3 3305 C3 3309 C5 3310 E5 3311 F7 3312 F6 3313 F6 3316 G9 3317 G9 3318 H7 3319 H13 3320 H6 3321 H12 3322 H8 3323 H8 3324 I9 3325 I12 3326 I13 3327 I12 3328 I12 3329 I13 3330 B5 3331 B4 3332 C4 3333 F8 3334 F8 3335 F8 3336 F8 3337 F9 3338 F9 3339 C5 3340 H9 5300 A8 5301 A5 6301 G8 6302 G9 6303 G8 7304 G11 7310 A10 7311 A6 7312 I13 7315 H7 F300 A11 F301 A8 F302 A7 F303 A5 F304 A6 F305 B10 F306 B5 F307 B10 F308 B10 F309 B4 F310 B10 F311 B10 F312 B4 F313 B10 F314 B5 F315 C10 F316 C5 F317 C10 F318 C10 F319 C5 F320 C10 F321 C10 F322 C5 F323 C10 F324 D10 F325 D10 F326 D10 F327 D10 F328 D10 F329 D10 F330 D10 F331 E10 F332 E10 F333 E10 F334 E10 F335 E10 F336 F7 F337 F7 F338 F8 F339 F6 F340 F6 F341 F7 F342 F9 F343 F9 F344 F8 F345 F8 F346 F8 F347 F9 F348 F8 F349 G9 F350 G12 F351 G9 F352 G12 F353 G12 F354 H12 F355 H9 F356 H13 F357 H6 F358 H7 F359 H12 F360 H8 F361 H9 F362 H8 F363 H9 F364 H12 F365 I13 F366 I12 F367 I12 F368 I9 F369 I13 F370 I12 F371 I9 F372 I12 F373 I12 Electrical diagrams and PWB’s ASD-1 7. 34 Memory 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PB 4268 ASD1 MONO-BOARD 3104 123 4268.4 MEMORY PART OPTION RD_ DB3 11 D3 INT_|SCL-OUT DB2 9 D2 IACK_|SDA-IN DB1 8 D1 CLK DB0 7 D0 +5V_DS 7400-D 74HCT00D 12 F406 3 14 2 11 3418 13 3412 WAIT 3413 7 7 F435 3405 +5V_DS F F434 OPTION 7400-B 74HCT00D 4 3414 14 6 CE1 VSS1 10K 5 VDD_MEM 3416 100n 100n 2412 2413 100n 100n 100n 100n 1 25 7 VDD 19 BA AD11 20 BANK SELECT 25 AD0 21 A0 DATA INPUT 27 AD1 22 A1 REGISTER 29 AD2 23 A2 31 AD3 24 A3 AD4 27 A4 AD5 28 A5 AD6 29 A6 AD7 30 A7 AD8 31 A8 AD9 32 A9 AD10 20 A10 LCKE CLK VDD_MEM2 3403 F432 100n 35 CLK 34 CKE 10K F415 18 CS_ RASN 17 RAS_ CASN 16 CAS_ WEN 15 WE_ DQMU 36 DQMH DQML 14 DQML 512Kx16 LWE LDQM COLUMN DECODER AD0 21 A0 DATA INPUT DQ3 6 AD1 22 A1 REGISTER DQ4 8 AD2 23 A2 DQ5 9 AD3 24 A3 DQ6 11 AD4 27 A4 DQ7 12 AD5 28 A5 DQ8 39 AD6 29 A6 DQ9 40 AD7 30 A7 DQ10 42 AD8 31 A8 DQ11 43 AD9 32 A9 DQ12 45 AD10 20 A10 DQ0 2 LCKE DQ14 48 CLK 3404 DQ15 49 PROGRAMMING REGISTER LWCBR LWE LQDM VSSQ 4 DQ1 3 35 CLK 34 CKE 10K F41618 VDD_MEM2 CSN2 33 17 RASN NC 37 16 CASN 15 WEN 36 DQML 14 DQMU CS_ RAS_ CAS_ WE_ DQMH DQML DQ2 5 DQ3 6 LDQM DQ4 8 DQ5 9 512Kx16 512Kx16 E DQ6 11 COLUMN DECODER DQ7 12 DQ8 39 DQ9 40 DQ10 42 DQ11 43 DQ12 45 F DQ13 46 LATENCY & BURST LENGTH DQ14 48 DQ15 49 PROGRAMMING REGISTER LRAS LCBR LWE 33 LWCBR NC 37 LWE G LQDM VSS VSSQ 26 50 10 41 47 4 10 41 47 H +5V_DS 2 4 3407 22R 3 NC 1 27M_CLK1 7400-C 74HCT00D 9 2414 2 3 DQ2 5 14 3406 8 I +3V3 100R 7 27M_CLKOUT 3410 CLK_8MHz F419 5402 F428 10 100MHZ F420 5403 VDD_MEM +3V3 VDD_MEM2 100MHZ 100u F430 D BANK SELECT DQ13 46 LATENCY & BURST LENGTH LRAS LCBR 512Kx16 2418 4 19 BA 100n 2417 100n 2416 F431 TOP 13 38 44 VDDQ OPTION 3409 5 1 AUXCLK 7 DQ1 3 OPTION 5 25 AD11 DQ0 2 22 CSN1 7403 74HCT1G04 1 VDD 26 50 7402 74HCT1G79 7405 MT48LC1M16A1TG BOTTOM 13 38 44 VDDQ VSS H C 18 VDD_MEM +5VOSC 100n 2411 16 VDD_MEM G 100n 2410 7404 MT48LC1M16A1TG 30 OPTION 7 2409 28 13 32 3415 2408 I 47u 14 2407 2420 7400-A 74HCT00D 1 100n 2406 47u DTACKn OPTION +5V_DS 26 100n 2419 10K 100n 3402 E 2415 +5V_DS 24 2403 100n OUTPUT BUFFER A1 D 21 2402 100n I/O CONTROL RWN 19 2404 2401 SENSE AMP 10 17 ROW DECODER VSS 15 SDRAM Interface VDD_MEM2 VDD_MEM2 COL. BUFFER SCL|SCL-IN 7401 Am29LV160BT 23 11 VCC A0 DQ0 10 A1 DQ1 9 A2 DQ2 8 A3 DQ3 7 A4 DQ4 6 A5 DQ5 5 A6 DQ6 4 A7 DQ7 42 A8 DQ8 41 A9 DQ9 40 A10 DQ10 39 A11 DQ11 38 A12 DQ12 37 A13 DQ13 36 A14 DQ14 35 A15 DQ15|A-1 34 A16 3 A17 2 A18 43 A19 12 CE_ 14 OE_ 44 WE_ 1 RESET_ 33 BYTE_ ROW BUFFER REFRESH COUNTER SDA|SDA-OUT 100R CL06532065_041.eps 290500 1 2 B RAM/ROM Interface LCBR 3 100n LCAS F425 12 D4 ADDRESS REGISTER 3401 SCL_EXE DB4 LRAS 100R 2 2405 WR_ TIMING REGISTER 3400 SDA_EXE 13 D5 OUTPUT BUFFER F424 DB5 I/O CONTROL 1 A0 SYSTEM ADDRESS Bus VDD_MEM SENSE AMP F423 CLK_8MHz 14 D6 ROW DECODER 4 C DB6 COL. BUFFER 5 CS_ ROW BUFFER REFRESH COUNTER 16 IRQ_I2C 15 D7 LCBR F422 DTACKn DB7 LCAS 6 18 VDD RESET_|STROBE_ ADDRESS REGISTER CE1 20 LRAS 17 +5V_DS TIMING REGISTER 19 RESET_I2C A SYSTEM DATA Bus 7406 PCF8584T B OPTION = NOT USED FOR FUTURE APPLICATION: I2C FROM MASTER TO SLAVE FOR SYSTEMS / COMBI'S 100n F421 2400 5400 100MHZ +5Vstby VSS2 A 3 4 5 6 7 8 9 10 11 12 13 14 2400 B3 2401 C9 2402 C10 2403 C12 2404 C13 2405 B6 2406 C9 2407 C10 2408 C12 2409 C13 2410 C9 2411 C10 2412 C12 2413 C13 2414 H7 2415 E1 2416 H2 2417 H3 2418 I10 2419 I13 2420 I13 3400 C1 3401 C2 3402 E1 3403 F8 3404 F11 3405 F5 3406 I7 3407 I3 3409 H7 3410 I6 3412 E5 3413 F5 3414 F5 3415 F5 3416 G5 3418 E4 5400 A3 5402 I9 5403 I12 7400-A E2 7400-B F2 7400-C I6 7400-D E3 7401 C6 7402 H2 7403 H3 7404 D9 7405 D12 7406 B3 F406 E2 F415 G8 F416 G11 F419 I10 F420 I13 F421 A3 F422 C2 F423 C2 F424 C2 F425 C2 F428 I8 F430 H2 F431 H1 F432 G5 F434 F5 F435 F5 Electrical diagrams and PWB’s ASD-1 7. 35 STI 5505 2 1 3 4 5 6 7 8 9 10 11 12 13 14 OPTION RAS1ND RWN CAS0ND CAS1ND CE1 CE_ROMN F568 RAS0ND OEND RAS1n_OR_HOLDREQ R|W_|DMAACK WE0n WE1n CAS0n_OR_HOLDACK CAS1n_OR_DMAREQn CE1n CE2n F501 3548 VDD_STI 100R 11 10K 12 F513 13 YC6 14 22n 10K 2505 3509 F517 3503 10K 3504 10K 68R 3508 10 VDD_STI 3505 3553 3552 YC5 15 YC7 100p VSYNC F523 19 20 27M_CLKOUT 3517 F054 23 25 IRQ0 IRQ1 TEST5 21 22 3K3 F557 3523 30 31 32 F556 33 41 F541 3522 10K 3520 F537 10K IRQ_I2C TEST1 TEST2 TEST3 TEST4 TDO TMS TRSTn 18 4 3521 10K F522 F525 2504 F528 188 186 189 187 190 TCK TDI TCK TDI TDO TMS TRSTN F534 F533 F532 191 192 193 194 195 196 197 14 F530 17 HSYNC PIO-4|0 PIO-4|1 PIO-4|2 PIO-4|3 PIO-4|4 PIO-4|5 PIO-4|6 PIO-4|7 F531 F521 SEL_ACLK2 RESET_I2C F524 207 2 201 202 203 204 205 206 1506-8 1506-9 23 VDD_STI 3K3 PCM-OUT1 24 PORT 4 I/O TEST JTAG IRQ AUDIO LPCM DECODER MPEG1/2 CE3n CSn RAS0n_OR_CE4n OEn B 1506-14 1506-15 1506-16 1506-17 1506-18 1506-19 C 1506-20 1506-21 1506-22 1506-23 48 VSSA_PCM 50 VREF_PCM 49 10u 330p 2509 PORT 3 I/O 1506-12 1506-13 100R F558 2506 PORT 2 I/O PORT 1 I/O 1506-11 1506-24 24 F055 3524 VDDA_PCM PORT 0 I/O 1506-10 2507 centre_on 3549 3554 3551 100R 9 43 44 45 46 47 SCLK PCM_OUTO PCM_CLK LRCLK SPDIF_OUT 100n SERVICE RXD_SER RTS_SER F510 F504 F509 OSLINKIN OSLINKOUT CPUreset CPUanalyse ErrorOUT VDD_STI YC4 16 F544 F545 F546 F547 F548 F549 F539 4K7 3540 PIO-3|0 PIO-3|1 PIO-3|2 PIO-3|3 PIO-3|4 PIO-3|5 PIO-3|6 PIO-3|7 10K F542 F519 RSTN OPTION 3519 SERVICE 3568 3 5 6 7 8 F554 7 64 PIO-2|0 PIO-2|3 PIO-2|4 PIO-2|5 PIO-2|7 1506-7 YC3 8 VDD_STI 3558 3556 3559 3555 F507 F506 3561 3557 YC6 3550 100R kar_by_pass YC4 YC5 YC3 YC2 YC1 CTS_SER YC0 F505 F508 3560 OPTION F514 3565 OPTION F060 OPTION 3564 F529 F553 PCMout2 MUTE OPTION F053 3546 F552 3567 100R kar_by_pass centre_on 15 16 17 20 21 22 3566 F526 3563 FLASH_OEN F052 RESETN 1506-6 6 uP ST20cpu PCMout1 6 VDD_STI 3545 D 220R 3525 2508 10K 3n3 E F560 SCLKo F562 F564 PCM_OUTO F566 PCM_CLK LRCLKo F567 F569 3570 SPDIF_OUT 100R F I_REF_DAC_RGB F590 I_REF_DAC_YCC 66 59 F587 V_REF_DAC_RGB 58 F589 F588 680R 15K 3535 3538 OSD_ACTIVE V_REF_DAC_YCC 65 OPTION 3534 10K 330R 27M_CLK HSYNC 4u7 +5VOSC 100n 7504 FXO-31FT 4 VDD 1 TS OSC 4 5 6 7 8 9 10 11 27M_CLK OUT 3 3536 100R GND 2 3569 OPTION F050 12 F051 27M_CLK1 4 CL06532065_042.eps 180500 6 3 R_OUT G_OUT B_OUT C_OUT CVBS_OUT Y_OUT 27M_CLK 4u7 2531 2530 VDD_STI VDD_STI VDD_STI VDD_STI VDD_STI VDD_STI VDD_STI VDD_STI CLK DQML DQMU CSN1 CSN2 CASN RASN WEN DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 100n HSYNC 2 F576 2527 3537 PIXCLK_27MHz 2u2 2528 VDD_STI 2529 117 118 3573 100R VSSA1 54 F586 HSYNCn VDDA2 60 ODD_OR_EVEN VDDA1 53 51 GND17 52 VDD17 208 200 2526 100n VSYNC GND16 185 2525 100n VSSA2 VDD16 184 61 GND15 2524 100n 2523 100n 2522 100n 2521 100n 2520 100n 2519 100n F599 F593 F592 2u2 5502 100n AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 SDRAM Interface VDD_STI 5501 OSD_ACTIVE VDD_STI F596 F598 F594 F595 F597 2518 100n 2517 100n VDD_STI 2516 100n VDD_STI 2515 100n VDD_STI VDD_STI 2514 100n 2513 100n VDD_STI VDD_STI 2511 100n VDD_STI 2510 100n VDD_STI PB 4268 ASD1 MONO-BOARD 3104 123 4268.4 2512 100n F585 VDD15 171 172 VDD13 149 GND14 GND12 140 160 VDD12 139 GND13 GND11 131 VDD14 VDD11 130 159 GND10 120 150 VDD10 119 SDCASn SDRASn SDWEn MEMCLKIN MEMCLKOUT DQML DQMU SDCS0n SDCS1n GND9 111 84 85 89 88 90 104 76 91 105 VDD9 110 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 GND8 103 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 VDD8 102 AD0 AD1 AD2 GND7 96 78 79 80 81 69 70 71 72 73 74 82 83 GND6 VDD7 VDD6 86 95 GND5 77 87 GND4 VDD5 75 VDD3 34 68 GND2 19 SDRAM CONTROLLER DATA DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 Interface GND1 VDD2 18 VDD1 4 1 H F056 F573 F574 Subpicture decoder ADDRESS GND3 B_V4 ENCODER Subpicture 2 IS VDD4 F582 B_DATA B_WCLK B_BCLK B_FLAG B_SYNC 67 F581 36 40 37 38 39 42 35 F580 FRONT-END F578 F579 B_OUT C_OUT CVBS_OUT Y_OUT Video DECODER 57 56 55 63 64 62 R_OUT G_OUT VIDEO MPEG {SCLKo,PCM_OUTO,PCM_CLK,LRCLKo,SPDIF_OUT,R_OUT,G_OUT,B_OUT,C_OUT,CVBS_OUT,Y_OUT,27M_CLK} Audio F583 1 1506-5 5 YC2 A 1506-4 4 F559 demultiplexer I 1506-3 3 YC1 AC3 VDD_STI B_DATA B_WCLK B_BCLK B_FLAG B_SYNC B_V4 F543 F527 3562 F538 PIO-0|0 PIO-0|3 PIO-0|4 PIO-0|5 PCM-OUT2|PIO-0|6 PIO-0|7 ADR14 ADR15 ADR16 ADR17 ADR18 ADR19 ADR20 ADR21 SYSTEM USE A/V/Sub G F520 FLASH_OEN 3541 47R F058 F059 YC7 3542 47R SEL_ACLK1 100n F536 F535 173 174 175 176 177 178 179 180 181 182 183 ADR11 ADR12 ADR13 161 162 163 164 165 166 167 168 169 170 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 ADR10 151 152 153 154 155 156 157 158 F555 128 133 121 122 129 132 124 125 126 135 127 123 MEMORY interface 2 1506-2 2 DATA2 DATA1 DATA0 3526 10K F DATA7 DATA6 DATA5 DATA4 DATA3 6 92 93 94 97 98 99 100 101 106 107 108 109 112 113 114 115 E 148 147 146 145 144 143 142 141 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 RAM/ROM Interface 4 3K3 AUXCLK A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 D8 D9 D10 D11 D12 D13 D14 D15 SYSTEM DATA Bus D7 D6 D5 D4 D3 D2 D1 D0 3547 3K3 VDD_STI 7503 STI5505 D 4u7 2502 OPTION 6 4 1506-1 1 YC0 OPTION 6 WAIT SYSTEM ADDRESS Bus C 4 VDD_STI SCL 4 3514 10K 3515 F518 10K 3516 VDD_STI 10K 4 22K 3502 VSS 6 P50 10K 6 3K3 F516 +5Vstby 7501 BC847B 3512 1n 6 3506 STB_CONT F540 2535 STB_CONT 6 SDA 5 SDA OPTION F502 OS_BOOT F515 8 28 27 26 29 116 136 137 134 138 1501-5 1n 68R VCC BRM2 BRM1_OR_BOOTFROMROM BRM0_OR_OSLINK_SEL RSTn AUXCLK READY PPC_CLK DMAXFER PPCn_MODE 1501-4 2534 3572 3511 1501-3 4 5504 F503 100n 4K7 47p F512 7505 M24C32 1 E0 2 E1 3 E2 6 SCL 7 WC_ 3507 SDA_EXE 3K3 2532 +5Vstby 2503 2500 68R 1501-2 SDA SCL VDD_STI 3500 F511 +5Vstby 3571 3K3 TO/FROM DISPLAY 5503 3513 9 10 198 199 11 12 13 4 47p 1501-1 I2C Bus VDD_STI PIO-1|0 PIO-1|2 PIO-1|3 PIO-1|4 PIO-1|5 PIO-1|6 PIO-1|7 SCL_EXE 3501 2533 TXD_BE RXD_BE BASIC ENGINE INTERFACE Bus A B TXD_SER OSD_ACTIVE F500 10K 13 14 G H I 1501-1 A1 1501-2 B1 1501-3 B1 1501-4 B1 1501-5 B1 1506-1 A14 1506-10 B14 1506-11 B14 1506-12 B14 1506-13 B14 1506-14 B14 1506-15 B14 1506-16 C14 1506-17 C14 1506-18 C14 1506-19 C14 1506-2 A14 1506-20 C14 1506-21 C14 1506-22 C14 1506-23 D14 1506-24 D14 1506-3 A14 1506-4 A14 1506-5 A14 1506-6 A14 1506-7 A14 1506-8 A14 1506-9 B14 2500 A3 2502 B5 2503 B6 2504 C11 2505 B11 2506 D14 2507 D14 2508 E14 2509 E13 2510 I3 2511 I3 2512 I4 2513 I4 2514 I4 2515 I4 2516 I5 2517 I5 2518 I5 2519 I9 2520 I9 2521 I9 2522 I10 2523 I10 2524 I10 2525 I10 2526 I11 2527 H13 2528 I11 2529 I11 2530 I11 2531 I11 2532 B1 2533 A1 2534 B1 2535 B1 3500 B3 3501 B3 3502 B5 3503 B11 3504 B11 3505 B11 3506 B4 3507 B5 3508 B11 3509 B11 3511 C6 3512 C6 3513 A10 3514 C6 3515 C6 3516 C6 3517 C13 3519 C9 3520 C11 3521 C12 3522 C12 3523 D13 3524 D14 3525 E14 3526 F2 3534 I12 3535 I13 3536 I14 3537 I12 3538 I13 3540 C9 3541 B7 3542 B8 3545 D14 3546 C7 3547 B6 3548 A10 3549 B10 3550 B10 3551 B10 3552 B10 3553 B11 3554 B10 3555 B9 3556 B9 3557 B9 3558 B9 3559 B9 3560 B9 3561 B9 3562 C7 3563 C7 3564 C7 3565 C8 3566 C7 3567 C7 3568 C8 3569 I12 3570 F14 3571 A2 3572 B2 3573 I12 5501 H11 5502 I11 5503 A1 5504 B1 7501 B5 7503 D2 7504 I13 7505 A2 F050 I14 F051 I14 F052 C7 F053 C7 F054 C12 F055 D14 F056 F14 F058 C7 F059 C8 F060 C8 F500 A13 F501 A11 F502 B5 F503 A6 F504 B9 F505 B9 F506 B9 F507 B9 F508 B9 F509 B9 F510 B9 F511 A1 F512 B1 F513 B11 F514 B8 F515 B1 F516 B1 F517 B11 F518 B6 F519 C9 F520 C7 F521 C10 F522 C11 F523 C13 F524 C10 F525 C11 F526 C7 F527 C7 F528 C11 F529 D7 F530 C10 F531 C10 F532 C10 F533 C10 F534 C10 F535 C5 F536 C6 F537 C11 F538 C6 F539 C6 F540 C6 F541 C12 F542 C9 F543 C7 F544 C9 F545 C9 F546 C9 F547 C9 F548 C9 F549 C9 F552 C7 F553 C8 F554 D8 F555 D6 F556 D12 F557 D12 F558 D14 F559 E14 F560 E14 F562 E14 F564 F14 F566 F14 F567 F14 F568 F2 F569 F14 F573 G14 F574 G14 F576 G14 F578 G2 F579 G2 F580 G2 F581 G2 F582 G2 F583 G2 F585 H11 F586 H11 F587 H13 F588 H12 F589 H12 F590 H13 F592 I8 F593 I8 F594 I8 F595 I8 F596 I8 F597 I8 F598 I8 F599 I8 Electrical diagrams and PWB’s ASD-1 7. 36 Service interface and Back-end 2 3 4 5 6 7 8 9 10 11 12 13 5600 SERVICE 1602-7 +5V 2600 F6011602-2 22K 4 13 VDD1 F 1603-3 1603-2 1603-6 3675 430R 47p 3661 2621 47p 2620 430R 3657 430R 47p 2623 1n5 2601 F603 F606 6K8 3635 100K 1n5 2602 6K8 3636 100K 22p 22p 2645 22p 2644 2643 22p 22p 2641 -Vvid 1604 1K 1 F656 5 HSYNC 5 PCMout2 3660 3684 3685 Y_OUT F663 {SCLKo,PCM_OUTO,PCM_CLK,LRCLKo,SPDIF_OUT,R_OUT,G_OUT,B_OUT,C_OUT,CVBS_OUT,Y_OUT,27M_CLK} 4 5 6 3655 430R 47p 2627 47p 3654 430R 2626 C_VID 7 8 9 10 5 SDA +6Vstby -Vvid 1K 7618 BC847B 15u PB 4268 ASD1 MONO-BOARD 3104 123 4268.4 6 +12Vstby 3659 +5V 11 12 +3V3 F665 F666 H 5 F659 13 F664 5608 4 -8Vstby 7617 BC847B 15u OPTION F658 -Vvid 5 SCL F661 5607 F660 3683 2 3 F657 +5V C_OUT F645 3 G 7615 BC847B OPTION SEL_ACLK2 11 2 1603-5 F653 3662 +5V F655 430R 27M 9 I 1 1K 5 PCMout1 GND2 5 6 1K OPTION +2 GND1 3647 OUTPUT 3_68M 14 BUFFER OUTPUT BUFFER 5606 47p 3 X1 CVBS -Vvid 7614 BC847B 15u OUTPUT 13_5M 10 BUFFER CLOCK BUFFER/ CRYSTAL OSCILL. F654 3681 CVBS_OUT 3656 2 X2 2646 22p 7 2625 CLOCK SYNTHESIS H OUTPUT PCLK BUFFER 47p CLOCK SYNTHESIS AND CONTROL CICUITRY 3673 2622 1 PS2 6 430R 16 PS1 ACLK 47p OUTPUT BUFFER 2624 CLOCK SYNTHESIS AND CONTROL CICUITRY 15 PS0 3648 +5VOSC F652 5605 15u 3651 12 AS1 3670 F651 3679 B_OUT VDD2 8 AS0 430R 3669 2 3663 +5V E G_OUT 3680 3691 G 7616 MK2742 B_VID F649 3682 OPTION 430R 3632 47p 3664 430R 47p 2617 47p 2616 3678 R_OUT G_VID 3 7613 BC847B D OPTION R_VID 5 3626 1K F648 15u 3633 100n 5604 F647 3677 1 100n F646 +5V 3 +5VOSC 2619 7612 BC847B -Vvid 430R +5VOSC 4 2615 5 2 SPDIF_OUT F643 15u 22p 5602 2640 100MHZ F641 F644 47p +5V 22R +5V F628 5601 7611 74HCT1G125 F F640 C TO AUDIO / VIDEO MUX. BOARD 100R -8Vstby 2618 10K 3617 3665 F639 F637 F638 3676 3631 +5VOSC +5VOSC 4K7 3625 430R 7621 BC817-25 F672 F632 3671 47K 3629 F622 3606 3622 100R 100u 100u 2606 100u 2632 2633 22K 3618 3667 100R 330R 100n F673 F635 LRCLKo 3689 SEL_ACLK1 1603-8 8 1603-11 11 1603-9 9 1603-10 10 1603-7 7 1603-12 12 1603-22 22 1603-17 17 1603-13 13 1603-4 4 1603-20 20 1603-19 19 1603-1 1 SCLK 1603-16 16 1603-14 14 1603-18 18 LRCLK 1603-15 15 1603-21 21 F633 PCM_CLK 22K 5603 F625 +5V OPTION PCM_OUTO OPTION 3688 4K7 +5V OPTION 100R 3624 2610 MEAS1 0_6_12V +5V +5V 3623 OPTION 1608 F674 3690 B_FLAG 22K 1607 6 PH-S -8Vstby MUTE_AV 10K 3674 SCLKo 2614 22K 7620 BC857B B F6161602-6 F630 -Vvid F671 10K +5V F669 3K3 2642 100u CFLG 3687 E +5Vstby +5V 1606 4 PH-S 1602-5 3611 9 -8Vstby 3615 7610 BC847B F629 3637 VDD_STI 3686 1605 2611 100MHZ BLM31 F6111602-4 -8Vstby 7608 7609 BC857B BC857B F626 22K F627 3 PH-S A 5 PH-S 22n F617 F621 100n 2639 F624 VDD_STI 3605 F6071602-3 F620 3619 +3V3 7600-D 74HCT14D 14 8 F619 6600 MUTE P50 +5V 7 1PS76SB10 5 100n 2638 F623 10K +5Vstby STB_CONT 47R +12Vstby 100n F636 2637 11 220R 10K -8Vstby 3672 F634 100u 10 F670 2607 F618 470R 1 PH-S 100R 7 0_6_12V 2605 SCART0 3630 100R -8Vstby 3621 F612 4 CTS_SER 3628 3607 3627 470R F609 3614 8 9 7607 BC847B 10K 3642 100n 2636 6 100u 2604 7 +6Vstby 100n 2609 6 2635 F615 100n 5 5610 14 3 7600-B 74HCT14D VDD_STI +5Vstby 2634 F614 12 RTS_SER +5V 4 47u FROM SUPPLY C 7604 BC847B 10K F631 3 +5V 7 2 PH-S F6021602-1 3610 5 7 3616 2 3613 SCART1 10u 1 +5V 10K +3V3S 2608 1 B F608 2 7 3620 +5V 7600-C 74HCT14D 14 6 RXD_SER 11 3608 OUT GND +5V 7600-E 74HCT14D 14 10 13 7 7600-A 74HCT14D 100K IN F610 3 3612 7605 LD1117 1600 +12Vstby VDD_STI +3V3 100MHZ BLM31 2603 100n F604 10K 5609 7600-F 74HCT14D 14 12 2 F613 +5V D 1 TXD_SER 3609 A TO/FROM PC INTERFACE 22n 14 F605 7 PH-S F600 +5V SERIAL PC INTERFACE TO AUDIO/VIDEO MUX. BOARD 1 14 Y_VID 15 3658 -Vvid 16 1K CL06532065_043.eps 180500 7 8 9 10 11 12 13 I 1600 B1 1602-1 A13 1602-2 A13 1602-3 A13 1602-4 B13 1602-5 B13 1602-6 B13 1602-7 A13 1603-1 E13 1603-10 C13 1603-11 C13 1603-12 D13 1603-13 D13 1603-14 E13 1603-15 E13 1603-16 E13 1603-17 D13 1603-18 E13 1603-19 E13 1603-2 G13 1603-20 E13 1603-21 F13 1603-22 D13 1603-3 F13 1603-4 D13 1603-5 F13 1603-6 G13 1603-7 D13 1603-8 C13 1603-9 C13 1604 G13 1605 E1 1606 E1 1607 E1 1608 E1 2600 A12 2601 A13 2602 B13 2603 B2 2604 C3 2605 C8 2606 C9 2607 D2 2608 B3 2609 C2 2610 F6 2611 D1 2614 F9 2615 F10 2616 G9 2617 G10 2618 F2 2619 F2 2620 G9 2621 G10 2622 H9 2623 H10 2624 I9 2625 I9 2626 I9 2627 I9 2632 C9 2633 C9 2634 C2 2635 C3 2636 C4 2637 D2 2638 D3 2639 D4 2640 F12 2641 F12 2642 F12 2643 F12 2644 F13 2645 F13 2646 H4 3605 D5 3606 C10 3607 B12 3608 B11 3609 C12 3610 A13 3611 B13 3612 B6 3613 B6 3614 C6 3615 C11 3616 D12 3617 D12 3618 D8 3619 D9 3620 A13 3621 B13 3622 C9 3623 E11 3624 E11 3625 E11 3626 F11 3627 B7 3628 C7 3629 C10 3630 C8 3631 F9 3632 F10 3633 G9 3635 B13 3636 C13 3637 C12 3642 B6 3647 G9 3648 H9 3651 I9 3654 I9 3655 I10 3656 I10 3657 H10 3658 I10 3659 I10 3660 H11 3661 G10 3662 G11 3663 G11 3664 G10 3665 E11 3667 E11 3669 G1 3670 G1 3671 G1 3672 C3 3673 G3 3674 D11 3675 I4 3676 E5 3677 F8 3678 G6 3679 G8 3680 G8 3681 H8 3682 H8 3683 I8 3684 I8 3685 I8 3686 E2 3687 E2 3688 E3 3689 F3 3690 E4 3691 G1 5600 A13 5601 E5 5602 F10 5603 F1 5604 F10 5605 G10 5606 H9 5607 I9 5608 I9 5609 A2 5610 D1 6600 C9 7600-A A11 7600-B B11 7600-C A12 7600-D B12 7600-E A9 7600-F A8 7604 B7 7605 B3 7607 B6 7608 C11 7609 C10 7610 D10 7611 F5 7612 F11 7613 F11 7614 G10 7615 H10 7616 G1 7617 I10 7618 I10 7620 E2 7621 E3 F600 A13 F601 A13 F602 A13 F603 A12 F604 A3 F605 A2 F606 A12 F607 A13 F608 B3 F609 B6 F610 B7 F611 B13 F612 B12 F613 B12 F614 B2 F615 B2 F616 B13 F617 B7 F618 C2 F619 C11 F620 C13 F621 C6 F622 C10 F623 D2 F624 C10 F625 D13 F626 D10 F627 D2 F628 E6 F629 D10 F630 D12 F631 B3 F632 F1 F633 E12 F634 C3 F635 E12 F636 C2 F637 E12 F638 E12 F639 E8 F640 E11 F641 E11 F643 F10 F644 E11 F645 I3 F646 F11 F647 F9 F648 F10 F649 F11 F651 G9 F652 G10 F653 G11 F654 H9 F655 H10 F656 H13 F657 H11 F658 H13 F659 H13 F660 I9 F661 I10 F663 I9 F664 I10 F665 I13 F666 I11 F669 C11 F670 C2 F671 E2 F672 E2 F673 E3 F674 E3 Electrical diagrams and PWB’s ASD-1 7. 37 Top view I2C SERVICE AV2 AV1 SUPPLY CL06532065_044.eps 230500 Electrical diagrams and PWB’s ASD-1 7. 38 Detailed Top view 1 CL06532065_045.eps 180500 Electrical diagrams and PWB’s ASD-1 7. 39 Detailed Top view 2 CL06532065_046.eps 180500 Electrical diagrams and PWB’s ASD-1 7. 40 Bottom view CL06532065_047.eps 180500 Electrical diagrams and PWB’s ASD-1 7. 41 Detailed Bottom view 1 CL06532065_048.eps 180500 Electrical diagrams and PWB’s ASD-1 7. 42 Detailed Bottom view 2 CL06532065_049.eps 180500 Electrical diagrams and PWB’s ASD-1 7. 43 Testpoint overview SL H3- T3 VH SL+ SL- Cosph FO RA Sinph Stby-out T2 MOTO1 H3+ H1+ H2+ A1 A2 A3 H1H2Stby R-VID G-VID CVBS T1 CL1 9V FOCO1 O2 O4 O3 STOPCLK RFO B_V4 B_BCLK B_WCLK B_SYNC LRCLK PCMOUT0 SCLK DEEMPH1 SPDIF PCM_CLK DEEMPH0 HSYNC C_VID PCMOUT2 MUTE PCMOUT1 SCART Y_VID RAD+ FOC+ RADS1 S2 A B C D F E 2.5V 3V3 PCM_CLK B_VID VO2- STB_CONT VO2+ RSTN 27M_CLK CL06532065_050.eps 180500 Electrical diagrams and PWB’s Personal notes: ASD-1 7. 44 Personal notes: Alignments ASD-1 8. GB 45 8. Alignments No alignments available 9. IC Descriptions. 9.1 SAA7399 (MACE2) General. Mace2 is a name used for the successor of the ACE1 IC. The term MACE (mini-ACE) is used because MACE2 does not have a decoder on board. Application area's: Mainly CDR(W) and prototyping of DVD(-ROM) or high speed CDROM. Functions implemented on-board of MACE2: A further improved digital servo module. Derived from the ACE1 servo module, but with improvements (make the input switchable between diode signal and error signal processing, improved brake). The 80C51 micro-controller with external ROM. The OPC. Optimum Power calibration, used for CDR. The PCS. Position Control Sledge. A way to speed up sledge movement using hall sensors. • 9.3 Sledge stepper motor support. The Digital Servo block. In a CD system, there are some 12 control loops active. About six of them are needed to adjust the servo error signals, that is once per disc rotation offsets, signal amplitudes and loop gains (AGC's) are adjusted to enlarge system robustness and to avoid expensive potentiometer adjustments in production. The other six loops determine the laser spot position on the disc in the radial, axial (focus) and tangential directions. The servo in MACE2 takes care of these controls. The servo inside Mace2 also has to take care that the spot accesses a required position as fast as possible. This access system consists of two parts, namely the actuator and the sled, which are within a certain range, mechanically and electrically independent. So during an access the servo has to control as well the actuator as the sled. 9.4 Functional description servo Figure 9-1 Overall block diagram MACE2. 9.2 Features • • • • • • • • • • • • • • • • • • Focus and Radial servo loop. Built-in access procedure. Selectable servo error or servo diode inputs. Focus noise performance equivalent to DSICS Automatic closed loop gain control available for focus and radial loops High speed track crossing velocity measurement > 350 kHz. Fast Radial Brake circuitry. Sledge motor servo loop, with pulsed sledge support and PCS Incorporated micro-controller equivalent to 80C51 --> 66MHz. Programmable wait state controller. Two embedded RAM's of 416 bytes and 1.5 kB res. Optimum Power Calibration Hardware support up to write at N=8. Debug facilities. Memory mapped interface to sub-modules. Programmable clock multiplier. 8 Multipurpose I/O lines. 5 external interrupt lines. External Flash ROM support. Figure 9-2 Mace2 servo block diagram. The following functions can be distinguished: – A to D conversion: a direct AD-conversion of the diode/ error currents. – Pulse density D to A conversion: Noise shaper output stages. – Control unit: Provides mainly the communication and on/ off functions. – Focus normaliser: A partial division of focus and sum signal. Special saturating provisions are included when dividing through very small numbers. – Initialisation control: Includes the radial normaliser, automatic radial offset compensation and level initialisation for the Track Position Indicator (TPI) for both diode and error input signals. – TPI/TL generation and adaptive debounce: Generates Track loss (TL) which is protected against disc defects. The TL is made out of the unprotected TPI signal. The debouncer (with improved debounce times) minimises the disturbing effect of HF on the TL and Rp crossovers for the track count circuitry. GB 46 – – – – – – 9.5 9. ASD-1 IC Descriptions. Defect detector: Holds the focus and/or radial control signal on disc dropouts. Speed control: Used during access. With radial actuator feed forward. Focus control: PID controller with wide range adjustable characteristics. Radial control: PID controller with wide range adjustable characteristics. Sledge control: PID controller with wide range adjustable characteristics and a pulsed sledge controller. Laser Low Power: Switches the laser from write back to read power whenever the device tends to go off-track. 9.6 Focus control. 9.6.1 Focus start-up. To bring the actuator in focus position a triangular shaped voltage is applied to the actuator to perform a search movement. When the lens moves from or to the disc, CA (central aperture) is monitored to reach a certain programmable absolute level. When this value is CA level is reached, the FOK signal becomes true and FEn is passed to the FEn level detector. At the moment this FEn level is reached the wait for the focus mode is entered and the focus control loop is enabled to detect a sign inversion in the FEn signal. When this zero crossing in this FEn signal is detected, the loop is closed to function as PID controlled loop and is switched to the PID mode. During focus start-up a dither signal is added to the output signal of the integrator. It prevents the actuator from hitting its natural resonance. With this technique quantisation, effects are compensated for during start-up. Focus Position Control loop. The focus control loop contains a digital PID controller that has 5 parameters available to the user. These coefficients influence the integrating, proportional and differential action of this PID and a digital low pass filter following the PID. The fifth coefficient influences the loop gain. 9.6.3 Dropout detection. This detector can be influenced by one parameter. The FOK signal will become false and the integrator of the PID will hold if the CA signal drops below this programmable absolute CA level. When the FOK signal becomes false, it is assumed as caused by a black dot in the first place. 9.6.4 Focus Loss detection and Fast restart. Whenever FOK is false longer than about 2 ms, it is assumed that the focus point is lost. A fast restart procedure is initiated which is capable of restarting the focus loop within 200 to 300 ms depending on the uP-programmed coefficients. 9.6.5 9.7 Focus Automatic Gain Control loop. The loop gain of the focus control loop can be corrected automatically to eliminate tolerances in the focus loop. This gain control injects a signal into the loop that is used to Radial control. The MACE2 digital controller includes the following radial servo functions: 9.7.1 Level initialisation: During start-up an automatic adjustment procedure is activated to set the values of the radial error gain, offset and satellite sum/MIRN signal gain for TPI level generation. The initialisation procedure runs in a radial open loop situation and is < 200 ms. This start-up time period may coincide with the last part of the turntable motor start-up time period. Input circuits servo Five out of six of the MACE2 servo inputs can be switched between diode current inputs (for audio and data application) and error signal inputs (for recordable applications). The analogue signals from the diode pre processor are converted into a digital representation using A/D converters. 9.6.2 correct the loop gain. Since this decreases the optimal performance, the gain control should only activated shortly (for instance when starting a new disc). 9.7.2 Automatic gain adjustment: Because of this initialisation the amplitude of the RE signal is adjusted within _10% around the nominal RE amplitude. Offset adjustment: The additional offset in RE due to the limited accuracy of the start-up procedure is less than +/50nm. 9.7.3 TPI level generation: The accuracy of the initialisation procedure is such that the duty cycle range of TPI becomes 0.4 < duty cycle < 0.6. Sledge home: Sledge moves to reference position at the inner side of the disc with user defined voltage. Tracking control: The actuator is controlled using a PID loop filter with user defined coefficients. Access: In Mace2 there are two fundamentally different ways to perform an access: Using the PCS A more detailed description of this access method is given in an other section. Using the servo controlled access: The way it was done in the predecessors of Mace2.This access procedure is divided into 3 different modes, depending on the requested jump size: access type size access speed Actuator jump decreasing velocity Sledge jump maximum power to sledge 1 Controlled sl. jump controlled brake power The access procedure makes use of a track counting mechanism, a velocity signal based upon the number of tracks passed within a fixed time interval, a velocity setpoint calculated from the number of tracks to go and a user programmable parameter indicating the maximum sledge performance. If the number of tracks to jump is too large, then the Sledge jump mode is activated, else the actuator jump is performed. The requested jump size together with the required sledge braking distance at maximum access speed defines the value of the maximum numbers of tracks. During the actuator jump mode, velocity control with a PI controller is used for the actuator. The sledge is then continuously controlled using the filtered value of the integrator contents of the actuator. All filter parameters (for actuator and sledge) are user programmable. IC Descriptions. In the sledge jump mode maximum power (user programmable) is applied to the sledge in the correct direction, while the actuator becomes idle. Radial Automatic Gain Control loop: The loop gain of the radial control loop can be corrected automatically to eliminate tolerances in the radial loop. This gain control injects a signal into the loop which is used to correct the loop gain. Since this decreases the optimal performance the gain control should only be activated shortly (for instance when starting a new disc). This gain control differs from the earlier mentioned level initialisation. This level initialisation should be done first. The level initialisation without the gain control reduces tolerances from the frontend only. 9.8 The radial PID. Since we are dealing with a big variety of applications and drives, the servo controllers in MACE2 should be adjustable within a large frequency range. In order to read out the track properly -a track consists of sequential ordered data pit's which hold audio, video or ROM data - the focus and radial position controls must follow the moving track within some tenths of a micrometer, despite of disc imperfections and external disturbances. For instance, a rotating disc causes, due to track eccentricity, track unroundness, or disc skew, track movements up to some millimetres. The control loop reduces this to about one tenth of a micrometer. 9.9 Initialisation control. Due to optical, electrical and mechanical tolerances in CD players, properties of the servo signals such as offset and gain can vary. In general, without proper signal processing, a simple PID controller function cannot cope with this relatively large offset and gain spreads. Therefore, gain and offset adjustments during manufacture or active control, to compensate for these signal imperfections, become inevitable. Adjustment procedures in the factory are expensive. So, automatic adjustment procedures have been implemented in order to avoid most of the potentiometer adjustments. In the MACE2 servo automatic adjustments are applied to the radial error signal only. 9.10 The AGC. The Automatic Gain Control is used in the MACE2 digital servo to adjust the radial and focus bandwidths to a nominal value. Injecting a signal in the loop and measuring the phase of its resulting signal (wobble method) does this. Principle of the Automatic Gain Control. The principle of the Automatic Gain Control (AGC) circuit, as used in MACE2, is drawn in the next figure. ASD-1 9. GB 47 measured before the injection point. The injected signal is shaped by H/1+H . This measured signal is multiplied by a phase shifted version of the injected signal. The result of the multiplication is low pass filtered and integrated. (The integrator is started at the nominal gain of the control loop). The result of the integration is fed to the adjustable loop gain. This principle, synchronous detection, is also known as 'wobble method'. 9.11 The Fast brake. The fast brake is an aid to speed up radial capture after a high-speed jump. It is a separate radial control with a much higher bandwidth. The radial control output can be switched between fast brake mode and original radial control mode. The fast brake helps the radial actuator at the end of a jump to "stick" to the right track. In fast brake mode, the actuator starts to follow the track movements. It's a bit like jumping on a moving train. If you run as fast as the train, you can just step in. After a radial open loop jump the tracks are moving (as a result of eccentricity) at a very high speed underneath the radial actuator. This speed is too high for a normal radial control loop to do radial capture. When the radial control is switched over to fast brake mode for a short term, this moving of the tracks underneath the actuator becomes much slower, (because the actuator follows the track movement), so when you switch back to original radial control, it's much easier to do radial capture. 9.12 The Defect Detector. Because of the possible earlier mentioned defects (fingerprints, etc) a defect detection circuit is incorporated into the MACE2 servo. If a defect is detected, the radial and focus error signals may be zeroed, resulting in better playability. 9.12.1 Operation: The defect detector prevents the light spot from going out of focus and going off track due to disc dropout excitations. The defect detector can be switched on and off under software control and can be applied to the focus control only, or both to the focus and radial control. Whenever this circuit detects a defect, it will hold all radial and focus controls. The hold signal is generated whenever the reflected light intensity drops rapidly (< 1:5 ms) down to roughly 75% of the actual intensity level. In that case the output of the comparator becomes active and controls the focus and radial signal switch. This circuit improves the playability of the application (black dot performance, etc) and is programmable to optimise it for specific disc defects. The actions of this circuit can be monitored on the DEFO pin (active high). An external defect detection circuit can be added by removing the connection between DEFO and DEFI (normal operation) and inserting the external circuitry. These signals are afflicted with some uncertainties caused by: – Disc defects like scratches and fingerprints – The HF information on the disc, which is considered as noise by the detector signals. 9.13 Laser Drive On. Figure 9-3 Principle of the automatic gain control. A sine wave signal with a certain frequency is injected in the control loop at the summation point. The resulting signal is The LDON pin is used to switch the laser drive off and on. It is an open drain output. In case the laser is on, the output has a high impedance. The pin will be automatically driven if the focus control loop is switched on. GB 48 9. ASD-1 IC Descriptions. 9.14 Laser Low Power (LLP). The LLP output can be used by write-able systems to switch the laser back to read power when the light spot goes offtrack while writing discs. To prevent that the neighbour tracks are damaged when the spot goes off-track the laser has to be switched very fast to the safe read power. The laser is not switched off (like LDON does), so the system can carry on reading. The tracking (radial) and focus error signals are used to disable the laser write power. This is done through the LLPn, active low Laser Low Power, signal. Note that LLPn is a servo output, which is inverted before it is output via the LLP pin, so the LLP pin is active high. So, if any of the following conditions is true, the laser write power is disabled by the MACE2 servo. – Off Track, more than a quarter off a track away from the correct one – ORD, radial error signal too large. Larger than the given setpoint, which should be chosen at a critical write failure level. An adjustable band pass filter first processes the radial error signal. – OFD, focus error signal too large. Larger than the given setpoint, which should also be chosen with care. An adjustable band pass filter also first processes the focus error signal. All settings of the focus and radial part are independent. – OTR, prot stat flag which becomes active if ORD becomes active during an actual laser write ( LWR) action. This flag is reset only by a status read ( RSTAT) command. So until then LLPN stays active. – OFO, prot stat flag that becomes active if OFD becomes active during an actual laser write action. Same idea as OTR. This error detection circuit can be switched off (apart from the Off Track detection) by raising the setpoint levels to its maximum value. 9.15 The OPC. The OPC block in Mace2 is used for the following functions: • During write actions, it stores Pw samples, which can be evaluated by the microprocessor. • During OPC read actions, it stores A1, A2 and CALF samples, which are used for calculating the asymmetry and the modulation index. • The OPC block is used for EFM detection. • During reading of a disc, it stores A1 and CALF samples, which can be monitored. Although the OPC block is used for multiple functions, it got it's name from the OPC procedure, which is it's main task. The OPC (Optimum Power Calibration) procedure is used in CD-R/CD-RW/DVD-RAM applications. It is used to "calibrate" the laser write power in writable systems. It reads in 3 analogue signals from an analogue preprocessor like AEGER-2 (A1, A2, and CALF) and the actual write power (Pw) from the laser controller and feeds an analogue output signal Alpha0 back to AEGER-2. A1, A2 and CALF represent the max, min and average value of the EFM signal respectively. Alpha0 controls the laser write power. All analogue signals are converted to an 8 bit digital signal. Conversion frequency at 16.9MHz base clock is 88kHz (each channel). Figure 9-4 Definition of the A1, A2 and CALF signals. 9.16 Definition of terms. The asymmetry ( and modulation index m of the EFM signal are calculated from the analogue inputs: A1- A2 A1+A2 m A1+ A2 A1+CALF 9.17 Rough description of the OPC procedure Basically the OPC procedure tries to find out the optimum laser power to be used on a specific disc. The OPC procedure uses about 15 ATIP frames. These frames are located in the "PCA" area. This is a special part of the disc used only for power calibration. The drive first checks whether there are 15 frames "empty" in the PCA. Next the OPC is performed in these 15 frames. The OPC operation consists of two stages: A "write" and a "read" stage. First 15 ATIP frames are written (during which the OPC block stores Pw samples), and then the same 15 ATIP frames are read back again, (during which the OPC block stores A1, A2 and CALF samples). During the write stage, random EFMis written in a test area located on the inner side of the disc. During this recording the write power is increased stepwise from a low to a high power level. Figure 9-5 Figure 5: OPC write profile. First during 3 ATIP frames the power is increased in rather big steps (rough OPC). During this action Pw samples are stored into memory. During the rough OPC, the OPC makes 7 steps per ATIP frame. This gives 21 samples into the OPC memory. From these samples, the microprocessor can calculate what's roughly the best alpha0 setting for this typical disc. After 2 frames of calculations, another 10 ATIP frames are written using smaller steps (fine OPC) around the alpha0 setting, which gave the best result during the rough OPC. The second stage of the OPC procedure is the "read" phase IC Descriptions. in which the pattern recorded in the previous stage is read back. During this read phase the OPC block stores A1, A2 and CALF samples from exact the same location where during the OPC write phase the Pw samples where stored. The samples for A1, A2, CALF and Pw are listed side by side into memory. After the read back phase the processor calculates at which setting of alpha0 the least jitter is encountered. This setting will be used to write the disc with. 9.18 The OPC top level. The OPC block as a whole has 5 possible modes: – Recording mode: This can be either OPC writing (writing EFM test patterns to disc and Alpha0 stepping) or standard write mode (i.e. alpha0 is constant). – OPC reading: Reading back OPC test patterns from disc. – Normal read mode: detects the presence of EFM. – DVD read mode: used for DVD-RAM experiments. – EFMD only mode: no data being written to the AUX RAM, but the EFM detector and the PW monitor still running. Contents of the QUX RAM remain unchanged. All actions in the OPC hardware are synchronised to the ATIP frame sync, which can be either generated internally or received from the encoder/decoder during writing. The microprocessor writes data asynchronously to the OPC hardware. The OPC block synchronises this data to the sync either internally generated, or obtained from CDR60. ASD-1 9. the input LPF's, the OPC pre-processor and the EFM detector. The sequencer controls the timing of all the hardware actions in the OPC hardware. The sequencer is started either by an external ATIP sync or an internally generated sync (programmable). All data acquisition and alpha0 settings change synchronised to this sync signal (rising edge of the ATIP sync). An exception on this is the switching of the ATIP input itself, which is immediately changed whenever the bit in the OPC ctrl register is changed. When this was latched on the ATIP source itself, it would create a deadlock when there was no ATIPin from CDR-60. 9.23 The Pw monitor The Pw monitor is used during the "OPC write" and normal write mode. The comparator compares the incoming Pw with two programmable thresholds PW MAX and PW MIN. Both these thresholds can be programmed via the OPC PW register, which contains 4 bits for each threshold. Internally both 4-bit thresholds PW MAX and PW MIN are extended to 8 bit values. The compare function performs an unsigned compare. The first threshold is used to detect fingerprints. The second is used to check the correct operation of the laser driver. 9.19 The Analogue to Digital converter. The analogue to digital converter of the OPC is shared with the ADC required by the PCS. 9.20 The digital input filters. The combined ADC for the OPC and the PCS delivers a multiplexed stream of 8 bit words. A sequential low-pass filter filters this multiplexed stream. The 4 analogue multiplexed input signals from the OPC (A1, A2, CALF and Pw) are filtered by 4 identical LPF's. (One for each channel). This filters can be adapted to various speeds by changing the subsampling factor (i.e. the sample rate of the filter), the cut off frequency scales with the sample frequency. The sample frequency of the filter is equivalent to the OPC timebase frequency, which is the output of the pre-scaler. 9.21 OPC demux. The OPC demux block demultiplexes the stream supplied by the LPF. This same block also changes the format of the digital data from signed (representation inside the filter) to unsigned (representation in the rest of the OPC). The demultiplexing process introduces one baseclock delay. 9.22 The sequencer. The OPC sequencer controls the timing of all the hardware actions in the OPC hardware. It generates the OPC timebase and locks it to the ATIP pulse. A programmable pre-scaler generates the OPC timebase. Dividing the ADC sample clock by 8 derives the input clock of this pre-scaler. (= Identical to the sample rate per channel). The pre-scaler can divide this clock by a number in the range from 1-16. The division factor can be programmed via the OPC ctrl register. The OPC timebase is locked to the selected ATIP source, which can be either an external ATI P sync or an internally generated sync. (Programmable). The OPC timebase clock supplies the sample frequency for GB 49 Figure 9-6 OPC PW monitor. GB 50 9. IC Descriptions. ASD-1 DVDALAS2plus Advanced Analogue DVD Signal Processor and Laser Supply TZA1033 FEATURES GENERAL DESCRIPTION • Operates with DVD-ROM,DVD-RAM, DVD+RW, DVD-RW, CD-ROM and CD-RW media The DVDALAS2 is an analogue preprocessor and laser supply circuit for DVD / CD read only players. The device contains data amplifiers, several options for radial tracking and focus control. The preamplifier forms a versatile, programmable interface between dual, voltage output CD/DVD mechanisms to Philips' digital signal processor family for CD and DVD (Gecko, HDR65, Iguano, etc..) • Operates up to 64x CD-ROM and 8x DVD-ROM • Support for Dual Light pen DVD systems (DVD/CDRW) • DVD-RAM (C) playback capability • DVD-RAM Land-Groove servo polarity switching • 3 different tracking servo strategies: Conventional 3 beam tracking for CD Differential Phase Detection (DPD) for DVD-ROM (including option to emulate traditional drop out detection; drop out concealment) Advanced Push Pull with dynamic offset compensation for DVD-RAM (recorded and unrecorded areas) The device contains serval options for radial tracking: Conventional 3 beam tracking for CD; Differential Phase Detector (DPD) for DVD; Push Pull for DVD-RAM with flexible L/R weighing to compensate dynamic offsets e.g. beamlanding offset. A radial error signal is generated to allow fast track count (FTC) during track jumps. • Radial error signal for fast track counting (FTC) • 2 different strategies to read header data: - Full bandwidth Push Pull signal - Left and Right side signal The dynamic range of this preamp/processor combination can be optimized for the LF servo and RF data paths. The gain in both channels can be programmed separately. This will guarantee an optimal playability for all kind of discs. • Universal photo diode IC interface using internal conversion resistors and offset cancelation Several functions are included to allow playback of DVD-RAM(C) discs: • Flexible adaption to different light pen configurations • The header information can be read via the data output path (RF) • Input buffer amplifiers with low-pass filtering • RF data amplifier with wide (programmable) bandwidth equivalent to 64xCD / 8x DVD when using equaliser function • DC offset compensation techniques provide a fast settling after disc errors. • Built-in equalisers cover CAV inner-outer disc range at highest speed. • two settings for focus offset correction for land and groove • Programmable RF gain for DVD-ROM / DVD-RAM / CD-RW / CDROM applications(approx 50dB range) The device can accommodate astigmatic, single foucault and double foucault detectors and can be used with P-type lasers with N- or P-sub monitor diodes. After an initial adjustment, the circuit will maintain control over the laser diode current. With an on-chip reference voltage generator, a constant and stabilized output power is ensured independent of ageing. A separate power supply connection allows the internal power dissipation to be reduced by connecting a low voltage supply. • Balanced RF-Data signal transfer (single ended still supported) • Fully automatic laser control including stabilization and an ON/OFF switch, plus a separate supplypin for power efficiency • Automatic monitor diode polarity selection. • Radial servo Polarity switch for land/groove • 3 and 5 V compatible digital interface • Enhanced signal conditioning in DPD circuit for optimal tracking performance under noisy conditions. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TZA1023 LQFP64 DESCRIPTION Plastic low pro?le QFP64; body 10 x 10 x 1.4 mm VERSION SOT314-2 IC Descriptions. ASD-1 DVDALAS2plus Advanced Analogue DVD Signal Processor and Laser Supply 9. TZA1033 DEVICE BLOCK DIAGRAM Var Gain MUX Diode Ampli?ers Processing DVD Balanced HF Data & header OPU Interface Header Land MUX DPD CD Push Pull Offset compensations Servo Signals D1-D6 Land/Groove Swap Mute 3 Beam Tracking FTC V & I references Rext Dual Laser Supply FTC comp. Laser#1 Serial Laser#2 I/Face Control Interface GB 51 GB 52 9. ASD-1 IC Descriptions. DVDALAS2plus Advanced Analogue DVD Signal Processor and Laser Supply PINNING Name Pin Description CD-A 1 CD pick up input A CD-B 2 CD pick up input B CD-C 3 CD pick up input C CD-D 4 CD pick up input D CD-REF 5 CD pick up reference voltage CD-E 6 CD pick up input E CD-F 7 CD pick up input F DVD-A 12 DVD pick up input A DVD-B 13 DVD pick up input B DVD-C 14 DVD pick up input C DVD-D 15 DVD pick up input D DVD-ref 16 DVD pick up reference voltage O-A 48 Servo current output for Focus-A O-B 47 Servo current output for Focus-B O-C 46 Servo current output for Focus-C O-D 45 Servo current output for Focus-D O-central 40 Testpin for offset cancelation TD2 37 Internally connected FTC-ref 36 Servo output voltage reference input S1 42 Servo current output for radial tracking S2 41 Servo current output for radial tracking TD1 35 Internally connected FTC 33 Fast track count voltage output RFP 55 pos. RF output signal RFN 56 neg. RF output signal RF-REF 54 DC Reference signal input RF LPF-DPD1 38 DPD Low pass bandwidth capacitor, channel pos LPF-DPD2 39 DPD Low passbandwidth capacitor, channel neg Land 20 Land/groove toggle input HEADER 21 Header detector window input CD-MI 62 CD laser monitor input DVD-MI 10 DVD laser monitor input CD-LO 61 CD laser output DVD-LO 64 DVD laser output COP 27 Positive inputFTC comparator COM 28 Inverting inputFTC comparator COO 29 FTC comparator output TZA1033 IC Descriptions. DVDALAS2plus Advanced Analogue DVD Signal Processor and Laser Supply Name Pin Description SIDA 23 Serial host interface data input SICL 24 Serial host interface clock input SILD 25 Serial host interface load VDDA1 8 Analog Supply voltage 1 (RF input) VDDA2 59 Analog Supply voltage 2 (RF internal) VDDA3 53 Analog Supply voltage 3 (RF output stage) VDDA4 44 Analog Supply voltage 4 (Servo) VDDD5 30 Digital Supply voltage (5V dig core) VDDD3 22 Digital Supply voltage (3V I/O pads and FTC comp.) VDDL 63 Supply voltage for laser VSSA1 9 Analog Ground 1 VSSA2 58 Analog Ground 2 VSSA3 57 Analog Ground 3 VSSA4 43 Analog Ground 4 VSSD 26 Digital ground Rext 60 Reference current input (Connect 12k1 to VSSA4) STB 31 Standby input TM 19 Testmode input TDO 34 test data out ASD-1 9. TZA1033 GB 53 9. IC Descriptions. ASD-1 DVDALAS2plus Advanced Analogue DVD Signal Processor and Laser Supply TZA1033 DVD-LO VDDL CD-MI CD-LO R-EXT VDDA2 VSSA2 VSSA3 RFN RFP RF-REF VDDA3 - - - - 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 handbook, full pagewidth 64 PINNING CD-A 1 48 O-A CD-B 2 47 O-B CD-C 3 46 O-C 4 45 O-D 5 44 VDDA4 CD-E 6 43 VSSA4 CD-F 7 42 S1 VDDA1 8 41 S2 VSSA1 9 40 O-CENTRAL DVD-MI 10 39 LPF-DPD2 - 11 38 LPF-DPD1 DVD-A 12 37 TD2 DVD-B 13 36 FTC-REF DVD-C 14 35 TD1 DVD-D 15 34 TDO DVD-REF 16 33 FTC TZA1023 CD-D CD-REF 23 24 25 26 27 28 29 30 31 32 VDDD3 SIDA SICL SILD VSSD COP COM COO VDDD5 STB - 21 22 20 LAND 19 HEADER 18 - TM 17 XXX - GB 54 Fig.2 Pin configuration. NEW MXXxxx IC Descriptions. ASD-1 9. BA6856FP: 3 PHASE MOTOR DRIVER FOR DVD PLAYERS Features • /3-phase, full-wave pseudo linear driving system • built-in power save • built-in therma shut down circuit • built-in current limit circuit • built in Hall bias circuit • built in FG-output (3-phase parallel output) • with switching function of regular/ reverse rotations blockdiagram 28 RNF 27 VM2 26 25 BA6856FB VCC DRIVER GAIN CONTROL VM1 A3 3 A2 5 A1 7 NC1 1 NC2 2 H1+ 9 H1- 10 NC3 4 NC4 6 H2+ 11 H2- 12 NC5 15 H3+ 13 H3- 14 - + 24 23 REV PS REV EC 21 + ECR - 20 CNF VH 18 FG1 17 FG2 16 FG3 MT2 30 + - PS 22 19 + - + + - H BIAS + + MT1 29 GND 8 GB 55 GB 56 9. ASD-1 RNF VM1 VM2 VCC REV PS EC ECR CNF VH FG1 FG2 FG3 N.C. GND H1+ H1H2+ H2H3+ H3- DESCRIPTION Not connected Not connected Output 3 for motor Not connected Output 2 for motor Not connected Output 1 for motor Ground Hall input Amp1. positive input Hall input Amp1. negative input Hall input Amp2. positive input Hall input Amp2. negative input Hall input Amp3. positive input Hall input Amp3. negative input Not connected FG3 signal output terminal FG2 signal output terminal FG1 signal output terminal Hall Bias Capacitor connection pin for phase compensation Torque control standard voltage input terminal Torque control voltage input terminal POWER SAVE switch Reverse terminal Power supply for sinal division Power supply 2 for driver Power supply 2 for driver Power supply for driver division GND N.C. N.C. A3 N.C. A2 N.C. A1 pin description PIN No PIN NAME 1 N.C. 2 N.C. 3 A3 4 N.C. 5 A2 6 N.C. 7 A1 8 GND + 9 H1 10 H1 + 11 H2 12 H2 + 13 H3 14 H3 15 N.C. 16 FG3 17 FG2 18 FG1 19 VH 20 CNF 21 ECR 22 EC 23 PS 24 REV 25 VCC 26 VM2 27 VM1 28 RNF FIN FIN Terminal lay-out IC Descriptions. IC Descriptions. ASD-1 9. SAA7335 DSP for CD and DVD-ROM systems FEATURES • Compatibility with CD-I, CD-ROM, MPEG-video DVD-ROM and DVD-video applications • Designed for very high playback speeds • Typical CD-ROM operation up to n = 12, DVD-ROM to n = 1.9, maximum rates (tbf) • Matched filtering, quad-pass error correction (C1-C2-C1-C2), overspeed audio playback function included (up to 3 kbytes buffer) In DVD modes double-pass C1-C2 error correction is used which is capable of correcting up to 5 C1 frame errors and 16 C2 frame errors. • Lock-to-disc playback, Constant Angular Velocity (CAV), pseudo-Constant Linear Velocity (CLV) and CLV motor control loops The SAA7335 contains all the functions required to decode an EFM or EFM+ HF signal directly from the laser pre-amplifier, including analog front-end, PLL data recovery, demodulation and error correction. The spindle motor interface provides both motor control signals from the demodulator and, in addition, contains a tachometer loop that accepts tachometer pulses from the motor unit. • Interface to 32 kbytes SRAM for DVD error correction and de-interleave • Sub-code/ header processing for DVD and CD formats • Programmable HF equalizer • In DVD mode it is still compatible with Philips block decoders • Sub-CPU interface can be parallel or fast I2C-bus • On-chip clock multiplier. GENERAL DESCRIPTION This device is a high-end combined Compact Disc (CD) and Digital Versatile Disc (DVD) compatible decoding device. The device operates with an external 32 kbytes S-RAM memory for de-interleaving operations. The device provides quad-pass error correction for CD-ROM applications (C1-C2-C1-C2) and operates in lock-to-disk, CAV, pseudo CLV and CLV modes. The SAA7335 has two independent microcontroller interfaces. The first is a serial I2C-bus and the second is a standard 8-bit multiplexed parallel interface. Both of these interfaces provide access to a total of 32 × 8-bit registers for control and status. This data sheet contains an descriptive overview of the device together with electrical and timing characteristics. For a detailed description of the device refer to the user guide “SAU/UM96018”. Supply of this CD/DVD IC does not convey an implied license under any patent right to use this IC in any CD or DVD application. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDD digital supply voltage 4.5 5.0 5.5 IDDD digital supply current − 70 300 mA VDDA analog supply voltage 4.5 5.0 5.5 V V IDDA analog supply current − 70 300 mA fxtal crystal input frequency 4 25 tbf MHz Tamb operating ambient temperature −20 − +70 °C Tstg storage temperature −55 − +125 °C GB 57 GB 58 9. IC Descriptions. ASD-1 SAA7335 DSP for CD and DVD-ROM systems ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION SAA7335GP LQFP100 plastic low pro?le quad ?at package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1 BLOCK DIAGRAM handbook, full pagewidth HF input SRAM 32 KBYTES ADC PLL BIT DETECTOR DEMODULATOR EFM/EFM+ DECODER clock input CLOCK GENERATOR SPINDLE MOTOR CONTROL SAA7335 I2S-BUS OUTPUT INTERFACE block decoder output SUB-CPU INTERFACE MGK242 motor control Fig.1 Simplified block diagram. IC Descriptions. ASD-1 SAA7335 DSP for CD and DVD-ROM systems PINNING SYMBOL PIN TYPE DESCRIPTION VSSA1 1 supply Iref 2 I analog current reference input for ADC REFLo 3 I analog low reference input for ADC analog ground 1 REFHi 4 I analog high reference input for ADC VREF 5 I analog negative input HFIN 6 I VSSA2 7 supply analog positive input analog ground 2 AGCOUT 8 O VDDA2 9 supply analog supply voltage 2 digital supply voltage 1 analog test pin output VDDD1 10 supply VSSD1 11 supply OTD 12 I off track detect input MOTO1 13 O 3-state motor control output n.c. 14 − MOTO2/T3 15 I/O n.c. 16 − not connected, reserved T1 17 I tachometer 1 input digital ground 1 not connected, reserved motor control output/tachometer 3 input T2 18 I VDDD2 19 supply VSSD2 20 supply TEST1 21 I test input 1 TEST2 22 I test input 2 POR 23 I power-on reset input MUXSWICH 24 I use clock multiplier input n.c. 25 − not connected, reserved CL1 26 O divided clock output BCAIN 27 I BCA input SDA 28 I/O SCL 29 I 9. tachometer 2 input digital supply voltage 2 digital ground 2 sub-CPU I2C-bus serial data input/output sub-CPU I2C-bus serial clock input INT 30 O VDDD3 31 supply digital supply voltage 3 sub-CPU interrupt output (open-drain) VSSD3 32 supply digital ground 3 da7 33 I/O sub-CPU data bus bit 7 input/output (parallel) da6 34 I/O sub-CPU data bus bit 6 input/output (parallel) da5 35 I/O sub-CPU data bus bit 5 input/output (parallel) n.c. 36 − da4 37 I/O n.c. 38 − da3 39 I/O sub-CPU data bus bit 3 input/output (parallel) da2 40 I/O sub-CPU data bus bit 2 input/output (parallel) not connected, reserved sub-CPU data bus bit 4 input/output (parallel) not connected, reserved GB 59 GB 60 9. ASD-1 IC Descriptions. SAA7335 DSP for CD and DVD-ROM systems SYMBOL PIN TYPE DESCRIPTION da1 41 I/O n.c. 42 − da0 43 I/O VDDD4 44 supply VSSD4 45 supply WRi 46 I sub-CPU write enable input (active LOW) RDi 47 I sub-CPU read enable input (active LOW) ALE 48 I sub-CPU address latch enable input CSi 49 I sub-CPU chip select input (active HIGH) STOPCLOCK 50 O stop clock output n.c. 51 − not connected, reserved V4 52 O serial subcode output (for CD) EBUOUT 53 O digital audio output SYNC 54 O I2S-bus sector sync output FLAG 55 O I2S-bus correction ?ag output DATA 56 O I2S-bus serial data output BCLK 57 I/O I2S-bus bit serial clock input/output WCLK 58 I/O I2S-bus word clock input/output sub-CPU data bus bit 1 input/output (parallel) not connected, reserved sub-CPU data bus bit 0 input/output (parallel) digital supply voltage 4 digital ground 4 VDDD5 59 supply digital supply voltage 5 VSSD5 60 supply digital ground 5 RAMRW 61 O n.c. 62 − RAMDA7 63 I/O RAM data bus bit 7 input/output RAMDA6 64 I/O RAM data bus bit 6 input/output RAMDA5 65 I/O RAM data bus bit 5 input/output RAMDA4 66 I/O RAM data bus bit 4 input/output RAMDA3 67 I/O RAM data bus bit 3 input/output RAMDA2 68 I/O RAM data bus bit 2 input/output n.c. 69 − RAMDA1 70 I/O RAMDA0 71 I/O VDDD6 72 supply digital supply voltage 6 VSSD6 73 supply digital ground 6 RAMAD0 74 O RAM address bit 0 output RAMAD1 75 O RAM address bit 1 output RAMAD2 76 O RAM address bit 2 output RAMAD3 77 O RAM address bit 3 output RAMAD4 78 O RAM address bit 4 output RAMAD5 79 O RAM address bit 5 output RAMAD6 80 O RAM address bit 6 output VDDD7 81 supply RAM read/write control output not connected, reserved not connected, reserved RAM data bus bit 1 input/output RAM data bus bit 0 input/output digital supply voltage 7 IC Descriptions. ASD-1 SAA7335 DSP for CD and DVD-ROM systems SYMBOL 9. PIN TYPE DESCRIPTION VSSD7 82 supply RAMAD7 83 O RAM address bit 7 output RAMAD8 84 O RAM address bit 8 output RAMAD9 85 O RAM address bit 9 output n.c. 86 − not connected, reserved RAMAD10 87 O RAM address bit 10 output RAMAD11 88 O RAM address bit 11 output RAMAD12 89 O RAM address bit 12 output RAMAD13 90 O RAM address bit 13 output RAMAD14 91 O RAM address bit 14 output VDDD8 92 supply digital supply voltage 8 VSSD8 93 supply digital ground 8 CRIN 94 I analog crystal input CROUT 95 O analog crystal output digital ground 7 CFLG 96 O correction statistics output MEAS1 97 O front-end telemetry output VDDD9 98 supply digital supply voltage 9 VSSD9 99 supply digital ground 9 VDDA1 100 supply analog supply voltage 1 GB 61 9. IC Descriptions. ASD-1 SAA7335 76 RAMAD2 77 RAMAD3 78 RAMAD4 79 RAMAD5 81 VDDD7 80 RAMAD6 82 VSSD7 83 RAMAD7 84 RAMAD8 85 RAMAD9 86 n.c. 87 RAMAD10 88 RAMAD11 89 RAMAD12 90 RAMAD13 93 VSSD8 92 VDDD8 94 CRIN 95 CROUT 96 CFLG 97 MEAS1 99 VSSD9 98 VDDD9 100 VDDA1 handbook, full pagewidth 91 RAMAD14 DSP for CD and DVD-ROM systems VSSA1 1 75 RAMAD1 Iref 2 74 RAMAD0 REFLo 3 REFHi 4 73 VSSD6 72 VDDD6 VREF 5 71 RAMDA0 HFIN 6 70 RAMDA1 VSSA2 7 69 n.c. AGCOUT 8 68 RAMDA2 VDDA2 9 67 RAMDA3 VDDD1 10 66 RAMDA4 VSSD1 11 65 RAMDA5 OTD 12 64 RAMDA6 SAA7335 MOTO1 13 63 RAMDA7 n.c. 14 62 n.c. MOTO2/T3 15 61 RAMRW n.c. 16 60 VSSD5 T1 17 59 VDDD5 T2 18 58 WCLK VDDD2 19 57 BCLK VSSD2 20 56 DATA TEST1 21 55 FLAG TEST2 22 54 SYNC 53 EBUOUT POR 23 MUXSWICH 24 52 V4 51 n.c. Fig.2 Pin configuration. STOPCLOCK 50 CSi 49 RDi 47 ALE 48 WRi 46 VSSD4 45 VDDD4 44 da0 43 n.c. 42 da1 41 da2 40 da3 39 n.c. 38 da4 37 n.c. 36 da5 35 da6 34 da7 33 VSSD3 32 VDDD3 31 INT 30 SCL 29 SDA 28 CL1 26 n.c. 25 BCAIN 27 GB 62 MGK241 IC Descriptions. ASD-1 SAA7335 DSP for CD and DVD-ROM systems FUNCTIONAL DESCRIPTION Analog front-end This block converts the HF input to the digital domain using an 8-bit ADC proceeded by an AGC circuit to obtain the optimum performance from the convertor. This block is clocked by ADCCLK which is set by the external crystal frequency plus a flexible clock multiplier and divider block. PLL and bit detector This subsystem recovers the data from the channel stream. The block corrects asymmetry, performs noise filtering and equalisation and finally recovers the bit clock and data from the channel using a digital PLL. 9. 1. The coincidence counter: this is used to detect the coincidence of successive syncs. It generates a sync coincidence signal if 2 syncs are 588 ±1 EFM clocks apart. 2. The main counter: this is used to partition the EFM signal into 17-bit words. This counter is reset when: a) A sync coincidence is generated b) A sync is found within ±6 EFM clocks of its expected position. The sync coincidence signal is also used to generate the lock signal which will go active HIGH when 1 sync coincidence is found. It will reset to LOW when, during 61 consecutive frames, no sync coincidence is found. The equalizer and the data slicer are programmable. FRAME SYNC PROTECTION DVD MODE Digital logic This circuit detects the frame synchronization signals. Two synchronization counters are used in the SAA7335: All the digital system logic is clocked from the master ADC clock (ADCCLK) described above. Advanced bit detector 1. The coincidence counter: this is used to detect the coincidence of successive syncs. It generates a sync coincidence signal if 2 syncs are 1488 ±3 EFM+ clocks apart. The advanced bit detector offers improved data recovery for multi-layer discs and contains two extra detection circuits to increase the margins in the bit recovery block: 2. The main counter: this is used to partition the EFM+ signal into 16-bit words. This counter is reset when: 1. Adaptive slicer: adds a second stage slicer with higher bandwidth b) A sync is found within ±10 EFM+ clocks of its expected position. 2. Run length 2 push-back: all T2 run lengths are pushed back to T3, thereby automatically determining the erroneous edge and shifting the transitions on that edge. a) A sync coincidence is generated The sync coincidence signal is also used to generate the lock signal which will go active HIGH when 1 sync coincidence is found. It will reset to LOW when, during 61 consecutive frames, no sync coincidence is found. Demodulator EFM/EFM+ demodulation FRAME SYNC PROTECTION CD MODE This circuit detects the frame synchronization signals. Two synchronization counters are used in the SAA7335: The 14-bit EFM (16-bit EFM+) data and subcode words are decoded into 8-bit symbols. GB 63 GB 64 9. ASD-1 IC Descriptions. SAA7335 DSP for CD and DVD-ROM systems Microcontroller interface The SAA7335 has two microcontroller interfaces, one serial I2C-bus and one parallel (8051 microcontroller compatible). The sequence for a write data command (1 data byte) is as follows: • Send START condition • Send address 3EH (write) The two communication modes may be operated at the same time, the modes are described below: • Write command address byte 1. Parallel mode: protocol compatible with 8052 multiplexed bus: • Send STOP condition. • Write data byte a) da0 to da7 = address/data bus The sequence for a read data command (that reads 1 data byte) is as follows: b) ALE = Address Latch Enable, latches the address information on the bus • Send START condition c) WRi = active LOW write signal for write to SAA7335 • Write status address byte d) RDi = active LOW read signal for read from SAA7335 e) CSi = active HIGH Chip Select signal (this signal gates the RDi and WRi signals). 2. I2C-bus mode: I2C-bus protocol where SAA7335 behaves as slave device where: • Send address 3EH (write) • Send STOP condition • Send START condition • Send address 3FH (read) • Read data byte • Send STOP condition. a) SDA = I2C-bus data READING AND WRITING DATA TO THE SAA7335 b) SCL = I2C-bus clock The SAA7335 has 32 × 8-bit configuration and status registers as shown in Table 1. Not all locations are currently defined and some remain reserved for future upgrades. These can be written to or read from via the microcontroller interface using either the serial or parallel control bus. c) I2C-bus slave address (write mode) = 3EH d) I2C-bus slave address (read mode) = 3FH e) Maximum data transfer rate = 400 kbits/s. MICROCONTROLLER INTERFACE (I2C-BUS MODE) Bytes are transferred over the interface in single bytes of which there are two types; write data commands and read data commands. IC Descriptions. ASD-1 9. GB 65 Am29LV160BT/Am29LV160BB 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Sector Erase Flash Memory DISTINCTIVE CHARACTERISTICS ■ Single power supply operation — Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications ■ Top or bottom boot block configurations available ■ Embedded Algorithms — Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors ■ Manufactured on 0.35 µm process technology — Embedded Program algorithm automatically writes and verifies data at specified addresses ■ Supports Common Flash Memory Interface (CFI) ■ High performance — Full voltage range: access times as fast as 90 ns — Regulated voltage range: access times as fast as 80 ns ■ Ultra low power consumption (typical values at 5 MHz) — 200 nA Automatic Sleep mode current — 200 nA standby mode current ■ Minimum 100,000 write cycle guarantee per sector ■ Package option — 48-ball FBGA — 48-ball µBGA — 48-pin TSOP — 44-pin SO ■ Compatibility with JEDEC standards — 10 mA read current — Pinout and software compatible with singlepower supply Flash — 20 mA program/erase current — Superior inadvertent write protection ■ Flexible sector architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Kbyte sectors (byte mode) — One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors ■ Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion ■ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion (not available on 44-pin SO) ■ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data GB 66 9. ASD-1 IC Descriptions. GENERAL DESCRIPTION The Am29LV160B is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball FBGA, 48-ball µBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the bytewide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. A 12.0 V VPP or 5.0 VCC are not required for write or erase operations. The device can also be programmed in standard EPROM programmers. The device offers access times of 80, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The Am29LV160B is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. IC Descriptions. ASD-1 9. GB 67 PRODUCT SELECTOR GUIDE Family Part Number Ordering Part Number: Am29LV160B VCC =3.0–3.6 V V CC 80R = 2.7–3.6 V 90 120 Max access time, ns (tACC) 80 90 120 Max CE# access time, ns (tCE) 80 90 120 Max OE# access time, ns (tOE) 30 35 50 Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM DQ0–DQ15 (A-1) RY/BY# VCC Sector Switches VSS Erase Voltage Generator RESET# WE# BYTE# Input/Output Buffers State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# VCC Detector A0–A19 Timer Address Latch STB STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix 21358C-1 GB 68 9. ASD-1 IC Descriptions. CONNECTION DIAGRAMS A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Standard TSOP Reverse TSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 21358C-2 IC Descriptions. SYNCHRONOUS DRAM FEATURES 1M16A1 • Plastic Package - OCPL* 50-pin TSOP (400 mil) -6 -7 -8A • Refresh 2K or 4K with Self Refresh Mode at 64ms -6 -7 -8A SETUP 166 MHz 143 MHz 125 MHz *Off-center parting line **CL = CAS (READ) latency Configuration 512Kx6banks Refr shCount RowAd res ing BankAd res ing ColumnAd res ing 2Kor4K 2K(A0-A10) 2(BA) 256(A0-A7) 1 Meg x 16 GENERAL DESCRIPTION HOLD CL=3* 5.5ns 5.5ns 6ns Vss DQ15 DQ14 VssQ DQ13 DQ12 VDDQ DQ11 DQ10 VssQ DQ9 DQ8 VDDQ NC DQMH CLK CKE NC A9 A8 A7 A6 A5 A4 Vss Note: The # symbol indicates signal is active LOW. PARTNUMBER ARCHITECTURE MT48LC1M16A1TG S KEY TIMING PARAMETERS AC ES TIME 50 49 48 47 46 45 4 43 42 41 40 39 38 37 36 35 34 3 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 1 12 13 14 15 16 17 18 19 20 21 2 23 24 25 16Mb (x16) SDRAM PART NUMBER S • Part Number Example: MT48LC1M16A1TG-7S CLOCK VDD DQ0 DQ1 VssQ DQ2 DQ3 VDDQ DQ4 DQ5 VssQ DQ6 DQ7 VDDQ DQML WE# CAS# RAS# CS# BA A10 A0 A1 A2 A3 VDD 1Megx16 TG • Timing (Cycle Time) 6ns (166 MHz) 7ns (143 MHz) 8ns (125 MHz) SPE D GB 69 PIN ASSIGNMENT (Top View) 50-Pin TSOP MARKING • Configuration 1 Meg x 16 (512K x 16 x 2 banks) 9. MT48LC1M16A1 S - 512K x 16 x 2 banks • PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge 1 Meg x 16 - 512K x 16 x 2 banks architecture with 11 row, 8 column addresses per bank • Programmable burst lengths: 1, 2, 4, 8 or full page • Auto Precharge Mode, includes CONCURRENT AUTO PRECHARGE • Self Refresh and Adaptable Auto Refresh Modes - 32ms, 2,048-cycle refresh or - 64ms, 2,048-cycle refresh or - 64ms, 4,096-cycle refresh • LVTTL-compatible inputs and outputs • Single +3.3V ±0.3V power supply • Supports CAS latency of 1, 2 and 3 OPTIONS ASD-1 2ns 2ns 2ns 1ns 1ns 1ns The 16Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 16,777,216 bits. It is internally configured as a dual 512K x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16-bit banks is organized as 2,048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed GB 70 9. ASD-1 IC Descriptions. 16Mb: x16 SDRAM G E N E R A L D E S C R IP T IO N (c o n tin u e d ) sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA selects the bank, A0-A10 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 1 Meg x 16 SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing the alternate bank will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation. The 1 Meg x 16 SDRAM is designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic columnaddress generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. IC Descriptions. ASD-1 9. GB 71 16Mb: x16 SDRAM ROWADDRESS LATCH 11 11 ROW DECODER FUNCTIONAL BLOCK DIAGRAM 1 Meg x 16 SDRAM 2,048 BANK0 MEMORY ARRAY (2,048 x 256 x 16) CKE CLK DQML, DQMH COMMAND DECODE CS# WE# CAS# RAS# 256 (x16) CONTROL LOGIC SENSE AMPLIFIERS I/O GATING DQM MASK LOGIC MODE REGISTER COLUMNADDRESS BUFFER BURST COUNTER 8 COLUMNADDRESS LATCH 12 8 COLUMN DECODER REFRESH CONTROLLER ADDRESS REGISTER REFRESH COUNTER SENSE AMPLIFIERS I/O GATING DQM MASK LOGIC 11 ROWADDRESS MUX 256 (x16) 11 11 ROWADDRESS LATCH 11 ROW DECODER 12 DATA OUTPUT REGISTER 16 16 DATA INPUT8 REGISTER 256 A0-A10, BA 16 256 2,048 BANK1 MEMORY ARRAY (2,048 x 256 x 16) DQ0DQ15 GB 72 9. IC Descriptions. ASD-1 16Mb: x16 SDRAM PIN DESCRIPTIONS P IN N U M B E R S S Y M B O L T Y P E D E S C R IP T IO N 35 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. 34 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), ACTIVE POWER-DOWN (row ACTIVE in either bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during powerdown and self refresh modes, providing low standby power. CKE may be tied HIGH. 18 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. 15, 16, 17 WE#, CAS#, RAS# Input Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being entered. 14, 36 DQML, DQMH Input Input/Output Mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle. DQML corresponds to DQ0-DQ7; DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered same state when referenced as DQM. 19 BA Input Bank Address Inputs: BA defines to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. BA is also used to program the twelfth bit of the Mode Register. 21-24, 27-32, 20 A0-A10 Input Address Inputs: A0-A10 are sampled during the ACTIVE command (rowaddress A0-A10) and READ/WRITE command (column-address A0-A7, with A10 defining AUTO PRECHARGE) to select one location out of the 512K available in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE REGISTER command. 2, 3, 5, 6, 8, 9, 11, 12, 39, 40, 42, 43, 45, 46, 48, 49 33, 37 DQ0DQ15 7, 13, 38, 44 4, 10, 41, 47 VDDQ VSSQ 1, 25 VDD Supply Power Supply: +3.3V ±0.3V. 26, 50 VSS Supply Ground. NC Input/ Data I/Os: Data bus. Output – No Connect: These pins should be left unconnected. Supply DQ Power: Provide isolated power to DQs for improved noise immunity. Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. IC Descriptions. ASD-1 9. GB 73 STi5505 (Rev. Ax) DVD BACKEND DECODER WITH INTEGRATED HOST PROCESSOR . .. . . . . INTEGRATED 32-BIT RISC HOST CPU - 2KBYTES INSTRUCTION CACHE, 2KBYTES DATA CACHE/SRAM - 50K DHRYSTONES/SEC (2.1) - 50MHz VIDEO DECODER - FULLY SUPPORTS MPEG-2 MP@ML - MEMORY REDUCTION - PAL IN 12MBITS SUBPICTURE DECODER HIGH PERFORMANCE ON-SCREEN DISPLAY AUDIO DECODER - 5.1 CHANNEL DOLBY AC-3® / MULTI CHANNEL MPEG-2 DECODING - DOWNMIX TO STEREO OR TO DOLBY PRO-LOGIC COMPATIBLE OUTPUTS FOR MPEG-2 AND AC-3 - IEC6958 - IEC61937 COMPATIBLE OUTPUT - LPCM (DVD) MODE SUPPORTED - 6 CHANNELS OUTPUT PAL/NTSC ENCODER - MACROVISIONTM 7.01/6.1 COMPATIBLE - TELETEXT, AND CLOSED CAPTION HIGH PERFORMANCE SDRAM INTERFACE PROGRAMMABLE MEMORY INTERFACE FOR DRAM, ROM, PERIPHERALS ETC. FRONT-END CHANNEL IC INTERFACE - DVD, VCD AND CD-DA COMPATIBLE - DSS - DVB BISTREAMS - SERIAL AND PARALLEL INTERFACES - HARDWARE SECTOR FILTERING - INTEGRATED CSS DECRYPTION AND TRACK BUFFER INTEGRATED PERIPHERALS - 2 UARTS, 1 I2C CONTROLLER, 3 PWM OUTPUTS, 3 TIMERS, 3 CAPTURE TIMERS, SMART CARD - 34 BITS OF PROGRAMMABLE I/O - OS LINK PROFESSIONAL TOOLSET SUPPORT - ANSI C COMPILER AND LIBRARIES - OPERATING SYSTEMS SUPPORT - ADVANCED DEBUGGING TOOLS 208 PIN PQFP PACKAGE DESCRIPTION The STi5505 provides a very highly integrated backend solution for DVD and combo DVD-DVB (Set Top Box) applications. The STi5505 incorporates a host CPU which handles both general application (DVD navigation, CD-DA, VCD, DVB) and drivers of the different embedded periphals (audio/video, subpicture decoders, OSD, PAL/NTSC encoder...). The STi5505 offers one of the best cost-effective (memory savings, internal peripherals availability) solution to DVD-DVB applications with rapid time to market (Reference design, DVD-DVB Software Toolkit). Figure 1 : General Block Diagram DMA CHANNELS ARBITOR FRONT-END INTERFACE (SECTOR PROCESSOR & DVD DECRYPTION) ST20 CPU . . .. . PRODUCT PREVIEW 2K INSTRUC. CACHE EXTERNAL MEMORY INTERFACE MPEG2/AC3 AUDIO 5.1 CHANNEL MPEG2 VIDEO SUBPICTURE OSD 2K DATA CACHE AND 2K SRAM OS LINK 2 UART 1 I2C PIO 3 PWM SMART CARD DIAGNOSTICS CONTROLLER AND SYSTEM SERVICES PAL/NTSC TELETEXT INTERFACE PQFP208 (Plastic Quad Flat Pack) ORDER CODE : STi5505ACV GB 74 9. ASD-1 IC Descriptions. STi5505 (Rev. Ax) I - GENERAL DESCRIPTION The performance offered by the ST20 CPU and its associated hardware (decoders, encoder, peripherals...) allows an integrated and unified DVD or DVD-DVB software solution. All the following operations are performed inside the STi5505 : - application management (DVD Navigation, VCD, CD-DA, DVB-Program Guide ...), - device data retrieval drivers (demultiplex, stream buffer management ...), - device presentation drivers (video decoder, subpicture decoder, on-screen display, audio decoder, PAL/NTSC encoder ...), - embedded peripherals drivers (UART, I2C, Programmable I/O, Smart Card ...). I.1 - ST20 32-bit CPU The ST20 micro-core family has been developped by SGS-THOMSON Microelectronics to provide the tools and building blocks to enable the development of highly integrated application-specific 32bits device at the lowest cost and fastest time to market. The STi5505 integrates a ST20 C2 core with the following characteristics : - 50K Dhrystones/s at 50MHz, - 8/16 bits instructions (32 most common instructions in 8 bits), - instruction cache 2Kbytes - write back replacement policy, - internal SRAM 2Kbytes to ensure fast access to critical code, data, interrupt handler ... - data cache 2 Kbytes - write back replacement policy, The STi5505's ST20 is provided with advanced debugging tools : - on-chip real-time emulation, - debugging with minimal impact on software and performance, - non intrusive attachment to the host via JTAG (IEEE1149.1), - no intrusion into the performance of the CPU core, - no intrusion into user code space by a debug kernel, - only 40bytes used for breakpoint handler. I.2 - Video Decoder The video decoder implemented in the STi5505 uses a patented memory reduction/bandwith reduction scheme to offer the user the best band- width/memory size compromise. The algorithm is lossless and uses "on-the-fly" decoding to reduce the memory requirements to two frame buffers in memory reduction mode. In this mode, PAL decoding is contained in 12Mbits. When used in bandwith reduction mode, the memory usage is the normal three buffers but the bandwith required by the decoder is significantly reduced compared to a classical implementation. In summary, the features of the decoder are : - MPEG-2 Main Profile/Main Level (MP@ML) support, - MPEG-2 program streams, Packet Elementary streams and MPEG-1 system streams support, - memory reduction architecture allowing sharing of single 16 Mbits SDRAM between MPEG decoding, micro and transport functions - memory expandable to 32 Mbits of SDRAM, - letter box (16:9) filter, - pan-scan, horizontal and vertical image resizing, - automatic error concealment. I.3 - Subpicture Decoder The STi5505 has a hardware DVD compliant subpicture decoder. Subpicture units are copied by DMA into subpicture bit buffer. The subpicture decoder can decode complete subpicture units without any interaction from the ST20. The main subpicture decoder features are : - up to 720x480 or 720x576 subpicture area, - internal LUTs for Sub Picture, Highlight and PCI (4 bits color and contrast outputs), - internal color LUT (4 bits from SP, HL, PCI to 24 Y,Cr,Cb bits) for SP color inputs to MPEG, OSD, SP mixer. I.4 - Audio Decoder The audio decoder cell is a fully compatible Dolby AC-3 / MPEG-1/MPEG-2 decoder capable of decoding both 5.1 and 2 channel streams compatible with the DVD standard. Downmix from 5.1 channels is supported for both Dolby and MPEG-2 streams. The output can be sent directly to external DACs or formatted for transmission in accordance with the IE6958 standard. The decoder can also handle linear PCM in accordance with the DVD standard. An integrated downsampler is provided for conversion from 96 kHz to 48kHz. IC Descriptions. ASD-1 9. GB 75 STi5505 (Rev. Ax) I - GENERAL DESCRIPTION (continued) The main features of the decoder core are : - Decodes 5.1 Dolby AC-3 Digital surround, - Output to 6 channels. Downmix modes : 1, 2, 3 or 4 channels for MPEG and AC-3 streams, - Karaoke mode for DVD. MPEG-2 capable, AC-3 capable, - MPEG-1, 2-channel audio decoder layers 1 and 2, - MPEG-2, 6-channel audio decoder layer 2, - PCM : transparent. downsampling 96 to 48 kHz, - Accepts MPEG-2 PES stream format for : MPEG2, MPEG-1, Dolby AC-3 and Linear PCM, - IEC6958 Output Interface, - CD-DA PCM format (subcode output in IEC6958 user data), - Downmix for Dolby Pro Logic compatible outputs for AC-3 and MPEG-2 (Pro Logic encoder), - Pro Logic decoder, - PLL for Internal 44.1 and 48kHz PCM clock generation, - On chip pink noise generator. I.5 - High Performance On-Screen Display The graphics performance of the STi5505 supports the new requirements for intelligent program guides and interactive applications. The display interface supports up to 256 colors for each OSD region and a transparency feature allows mixing of video with the OSD. Fast access graphics and many other additional features are available and are supported by a graphics library. Very high system performance is obtained by closely coupling the ST20 RISC processor and cache with the MPEG audio/video core and display memory. Low latency RISC access and DMA engines allow rapid construction of bit maps. I.6 - PAL/NTSC Encoder The STi5505 integrates a PAL/NTSC encoder. It converts the digital MPEG/Sub Picture/OSD stream into a standard analog baseband PAL/NTSC signal and into RGB analog components. Six analog output pins are available on which it is possible to output CVBS, S-VHS (Y/C) and RGB formats. The encoder handles interlaced and non-interlaced mode. It can perform Closed Captions, CGMS or Teletext encoding and allows Macrovision 7.01/6.1 copy protection. The encoder supports both master and slave modes for synchronization. I.7 - Memory Interfaces The STi5505 has been designed to minimize system costs by enabling various memory savings. Two kinds of memory interfaces are used on the STi5505 : a programmable External Memory Interface (EMI) and a high performance SDRAM interface. The External Memory Interface supports several address ranges (memory banks). In each bank, a set of signals are entirely programmable and can be used to map 8/16 bits peripherals such as Front End channel ICs in DVD applications. The EMI contains a zero glue logic DRAM and a low-cost EPROM interface. This interface can be programmed to interface very easily peripherals. The SDRAM memory interface supports gluelessly 125 MHz SDRAMs providing the adequate bandwiths to achieve MPEG decoding and display, OSD drawing and display, and general system use. Memory savings can be realized on ROM requirements too : the ST20 VL-RISC micro-core has the highest code density of any 32 bit CPU, leading to the lowest cost program ROM. I.8 - Front-End Interface The STi5505 's front end interface accepts : - DVD, VCD and CD-DA sectors, - DVB-DSS transport stream. In DVD mode, DVD, VCD and CD-DA information can be input into STi5505 through a serial interface or a generic parallel interface. In serial mode, data are captured and filtered from I2S and V4 interfaces by an internal sector processor. V4 interface is used to capture VCD and CDDA subcode information. In parallel mode, sector processor is bypassed. GB 76 9. ASD-1 IC Descriptions. STi5505 (Rev. Ax) I - GENERAL DESCRIPTION (continued) The main features of the DVD interface are : - DVD, VCD and CD-DA compatible, - hardware sector filtering, - subcode error correction for CD-DA, - integrated CSS decryption, - integrated track buffer support, - DMA engine to ST20 memory. In DVB-DSS mode, DVB-DSS transport stream is input through a serial interface. The STi5505 extracts and descrambles Packet Elementary Streams belonging to one user selected program to be decoded and presented. The main features of the DVB-DSS interface are : - descrambling (transport packet and packet elementary streams in DVB mode, transport packet in DSS mode ; up to 32 streams descrambling), - PID and section filtering, - clock recovery, - DMA engine. In DVB-DSS mode, a high speed digital interface allows to transfer packets between the Set Top Box and external units, either for recording or playback purposes. This interface provides also full support for an external IEEE1394 connection. I.9 - Integrated Peripherals Several peripherals generally used in DVD players or DVD-DVB combos have been integrated into the STi5505. They are : - two UARTs to interface remote control receivers, DVD front end, modem ..., - one I2C controller to interface serial memories, remote control receivers, microcontrollers..., - 2 SmartCard interfaces (ISO7816-3) for DVBDSS conditionnal access, pay per view ..., - PWM/timer module for control of system clock, - 34 programmable I/O pins, - OS Link interface, - JTAG with boundary scan for debug. IC Descriptions. ASD-1 9. GB 77 STi5505 (Rev. Ax) II - PIN DESCRIPTION VDD PIO3[6] PIO3[5] PIO3[4] PIO3[3] PIO3[2] PIO3[1] PIO3[0] GND PIO1[4] PIO1[3] PIO4[6] PIO4[5] PIO4[4] PIO4[3] PIO4[2] PIO4[1] PIO4[0] TRST TDO TCK TMS TDI GND VDD ADR[21] ADR[20] ADR[19] ADR[18] ADR[17] ADR[16] ADR[15] ADR[14] ADR[13] ADR[12] ADR[11] GND VDD ADR[10] ADR[9] ADR[8] ADR[7] ADR[6] ADR[5] ADR[4] ADR[3] ADR[2] ADR[1] GND VDD DATA[15] DATA[14] 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 II.1 - Pin Connections VDD 1 156 DATA[13] PIO3[7] 2 155 DATA[12] PIO2[0] 3 154 DATA[11] GND 4 153 DATA[10] PIO2[3] 5 152 DATA[9] PIO2[4] 6 151 DATA[8] PIO2[5] 7 150 GND PIO2[7] 8 149 VDD PIO1[0] 9 148 DATA[7] PIO1[2] 10 147 DATA[6] PIO1[5] 11 146 DATA[5] PIO1[6] 12 145 DATA[4] PIO1[7] 13 144 DATA[3] PIO4[7] 14 143 DATA[2] PIO0[0] 15 142 DATA[1] PIO0[3] 16 141 DATA[0] PIO0[4] 17 140 GND VDD 18 139 VDD GND 19 138 PPC_MODE PIO0[5] 20 137 PROCCLK PIO0[6]/PCM_OUT2 21 136 WAIT/READY PIO0[7] 22 135 CS IRQ[0] 23 134 DMAXFER PCM_OUT1 24 133 R/W/DMAACK STi5505 IRQ[1] 25 132 CAS1/DMAREQ PWM0/OSLINK_SEL 26 131 GND PWM1/BOOTFROMROM 27 130 VDD PWM2 28 129 CAS0/HOLDACK RST 29 128 RAS1 TEST1 30 127 RAS0/CE[0] TEST2 31 126 CE[3] TEST3 32 125 CE[2] TEST4 33 124 CE[1] VDD 34 123 OE PQFP208 (Top View) GND 35 122 BE[1] B_DATA 36 121 BE[0] B_BCLK 37 120 GND B_FLAG 38 119 VDD B_SYNC 39 118 PIXCLK_27MHz B_WCLK 40 117 OSD_ACTIVE TEST5 41 116 AUXCLK B_V4 42 115 DQ[15] SCLK 43 114 DQ[14] PCM_OUT0 44 113 DQ[13] PCM_CLK 45 112 DQ[12] LRCLK 46 111 GND SPDIF_OUT 47 110 VDD 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 VSSA Y_OUT C_OUT CV_OUT V_REF_DAC_YCC I_REF_DAC_YCC VDD GND AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] VDD MEMCLKOUT GND AD[0] AD[1] AD[2] AD[3] AD[10] AD[11] SDCS[0] SDCS[1] VDD GND SDRAS SDCAS SDWE DQML DQ[0] DQ[1] DQ[2] VDD GND DQ[3] DQ[4] DQ[5] DQ[6] DQ[7] VDD GND MEMCLKIN 60 VDDA VDDA DQMU 59 105 I_REF_DAC_RGB 52 58 DQ[8] ODD/EVEN V_REF_DAC_RGB 106 57 51 56 DQ[9] HSYNC R_OUT 107 G_OUT 50 55 DQ[10] VSSA_PCM 54 DQ[11] 108 53 109 49 VSSA 48 B_OUT VDDA_PCM V_REF_PCM GB 78 9. IC Descriptions. ASD-1 STi5505 (Rev. Ax) II - PIN DESCRIPTION (continued) II.2 - Pin List Pin Name Type Function 1, 18, 34, 67, 75, 86, 95, 102, 110, 119, 130, 139, 149, 159, 171, 184, 208 4, 19, 35, 68, 77, 87, 96, 103, 111, 120, 131, 140, 150, 160, 172, 185, 200 53, 60 54, 61 48 49 50 VDD Power Supply GND Ground VDDA VSSA Analog Power Supply for DENC D/A Converters Analog Ground for DENC D/A Converters Analog Power Supply for PLL PCM Analog Reference for PLL PCM Analog Ground for PLL PCM SUPPLIES VDDA_PCM V_REF_PCM VSSA_PCM FRONT-END INTERFACE I2S Data (DVD) or PARA_DATA[2] (DVD//) or Link Data (DVB/DSS) I2S Word Clock or PAR A_DATA[6] (DVD//) or NRSS_CLK (DVB/DSS) I2S Bit Clock (DVD) or PARA_DATA[3] (DVD//) or Link Bit Clock (DVB/DSS) Error Flag (DVD) or PARA_DATA [4] (DVD//) or Link Sync (DVB/DSS) Sector / Abs Time Sync (DVD) or PARA_DATA[5] (DVD//) or Link Not Valid (DVB/DSS) Versatile Input Pin (Subcode Input) or PARA_DATA[7] (DVD//) or NRSS_IN (DVB/DSS) 36 B_DATA I 40 B_WCLK I/O 37 B_BCLK I 38 B_FLAG I 39 B_SYNC I 42 B_V4 I R_OUT G_OUT B_OUT C_OUT CV_OUT Y_OUT I_REF_DAC_RGB I_REF_DAC_YCC V_REF_DAC_RGB V_REF_DAC_YCC OSD_ACTIVE PIXCLK_27MHz HSYNC ODD/EVEN O O O O O O I I I I I/O I I/O I/O Red Output Green Output Blue Output Chroma Output Composite Video Output Luma Output DAC Current Reference DAC Current Reference DAC Voltage Reference DAC Voltage Reference OSD Active System Clock Input Horizontal Sync Vertical Sync O O O O I/O O O Serial Bit Clock Audio Serial Output Data 0 Audio Serial Output Data 1 Audio Serial Output Data 2 PCM Clock In or Out Left/Right Clock SPDIF Output VIDEO OUTPUT INTERFACE 57 56 55 63 64 62 59 66 58 65 117 118 51 52 AC-3/MPEG1-2 AUDIO OUTPUT INTERFACE 43 44 24 21 45 46 47 SCLK PCM_OUT0 PCM_OUT1 PCM_OUT2 PCM_CLK LRCLK SPDIF_OUT IC Descriptions. ASD-1 9. GB 79 STi5505 (Rev. Ax) II - PIN DESCRIPTION (continued) II.2 - Pin List (continued) Pin Name Type IRQ[0:1] I Function EXTERNAL INTERRUPTS 23, 25 External Interrupts PROGRAMMABLE I/O AND ALTERNATE FUNCTION (see Device Configuration Chapter) 15 PIO0 [0] I/O 16 PIO0 [3] I/O 17 PIO0 [4] I/O 20 PIO0 [5] I/O 21 22 PIO0 [6] PIO0 [7] I/O I/O 9 10 198, 199 11 12 13 3 5 6 7 PIO1 [0] PIO1 [2] PIO1 [3:4] PIO1 [5] PIO1 [6] PIO1 [7] PIO2 [0] PIO2 [3] PIO2 [4] PIO2 [5] I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 8 201 202 203 204 205 206, 207, 2 191-197 14 PIO2 [7] PIO3 [0] PIO3 [1] PIO3 [2] PIO3 [3] PIO3 [4] PIO3 [5:7] PIO4 [0:6] PIO4 [7] I/O I/O I/O I/O I/O I/O I/O I/O I/O General Purpose I/O or PARA_SYNC (DVD//Front End) or Sc1Data (Smart Card 1 Data I/O) General Purpose I/O or PARA_REQ (DVD//Front End) or Sc1Clk (Smart Card 1 Clock) General Purpose I/O or PARA_STR (DVD//Front End) or Sc1RST (Smart Card 1 Reset) General Purpose I/O or PARA_DATA[0] (DVD//Front End) or Sc1Cmd VCC (Smart Card 1 Voltage Enable) General Purpose IO or Sc1DataDir (Smart Card 1 Dir) General Purpose I/O or PARA_DATA[1] (DVD//Front End) or Sc1Detect(Smart Card 1 Detect) General Purpose I/O or I2C Data General Purpose I/O or I2C Clock General Purpose IO General Purpose IO or ASC1 TXD General Purpose IO or ASC1 RXD General Purpose IO or ASC3 TXD General Purpose I/O or Sc0Data (Smart Card 0 Data I/O) General Purpose I/O or Sc0Clk (Smart Card 0 Clock) General Purpose I/O or Sc0RST (Smart Card 0 Reset) General Purpose I/O or Sc0CmdVCC (Smart Card 0 Voltage Enable) General Purpose I/O or Sc0Detect (Smart Card 0 Detect) General Purpose IO or OSLink In General Purpose IO or OSLink Out General Purpose IO or CPUReset General Purpose IO or CPU Analyse General Purpose IO or ErrorOut General Purpose IO General Purpose IO General Purpose IO or ASC3 RXD TCK TDI TDO TMS TRST I I O I I Test Clock Test Data Input Test Data Input Test Mode Select Test Reset PWM2 PWM1/BOOTFROMROM PWM0/OSLINK_SEL RST AUXCLK O O/I O/I I O PWM2 Output PWM1 Output or Configuration Oslink Pins PWM0 Output or Boot from ROM during Reset Reset Auxilary Clock for Any Purpose JTAG INTERFACE 188 186 189 187 190 SYSTEM USE 28 27 26 29 116 GB 80 9. IC Descriptions. ASD-1 STi5505 (Rev. Ax) II - PIN DESCRIPTION (continued) II.2 - Pin List (continued) Pin Name Type Function AD[0:11] DQ[0:15] O I/O SDRAM Address Bus SDRAM Data (Lower Byte) SDCS[0:1] SDCAS SDRAS SDWE MEMCLKIN MEMCLKOUT DQML DQMU O O O O I O O O SDRAM Chip Selects SDRAM CAS SDRAM RAS SDRAM Write Enable SDRAM Memory Clock Input SDRAM Memory Clock Output DQ Mask Enable (Lower) DQ Mask Enable (Upper) ADR[1:21] DATA[0:15] RAS1/HOLDREQ WAIT/READY R/W/DMAACK BE[0:1] CAS0/HOLDACK CAS1/DMAREQ CE[1:3] CS PROCCLK RAS0/CE0 DMAXFER PPC_MODE OE I/O I/O O I/O I/O O O/I O O I I/O O I I I/O External Memory Address Bus External Memory Data Bus DRAM RAS or reserved External Wait States or Reserved DRAM R/W Strobe or Reserved Byte enable DRAM CAS or Reserved DRAM CAS or Reserved Chip Select for Banks 1 - 3 Reserved ST20 Clock or Reserved DRAM RAS or Chip Select for Bank 0 Reserved Reserved Output Enable or Reserved 30 TEST1 I/O 31 TEST2 I/O 32 TEST3 I/O DATA_RX/STROBE_TX (SDAV Mode) or SDAV_CLK (P1394 Mode) ST R O BE _ R X/ D AT A _ TX ( SD A V M od e) o r DATA_IN/DATA_OUT (P1394 Mode) Direction (SDAV Mode) or DATA_VALID In/Out (P1394 Mode) TEST5 O SDRAM INTERFACE 78-81, 69, 70-74, 82, 83 92-94, 97-101, 106-109, 112-115 84, 85 89 88 90 104 76 91 105 EXTERNAL MEMORY INTERFACE 161-170, 173-183 141-148, 151-158 128 136 133 121, 122 129 132 124-126 135 137 127 134 138 123 SDAV/P1394 INTERFACE MISCELLANEOUS 41 NRSS_OUT (DVB/DSS) IC Descriptions. ASD-1 9. GB 81 STi5505 (Rev. Ax) III - FUNCTIONAL DESCRIPTION III.1 - Functional Modules Figure 1 shows the subsystem modules that make up the STi5505. These modules are outlined below. III.1 - CPU The Central Processing Unit (CPU) on the STi5505 is the ST20-C2 32-bit processor core. It contains instruction processing logic, instruction and data pointers and an operand register. It directly accesses the high speed on-chip SRAM memory, which can store data or programs, and uses the Caches to reduce access time to off chip program and data memory. The processor can access memory via the general purpose External Memory Interface (EMI) or via the SDRAM EMI which is shared with the MPEG decoder. III.2 - Memory Subsystem The STi5505 on-chip SRAM memory system provides 160 Mbytes/s internal data bandwidth, supporting pipelined 2 cycles internal memory access at 25ns cycle times. The STi5505 memory system consists of 2 Kbytes of SRAM, 2Kbytes of instruction cache, a 2Kbytes data cache that can be programmed to be SRAM, and an external memory interface (EMI). The STi5505 product has 2 Kbytes of on-chip SRAM. The advantage of this is the ability to store time critical code on chip, for instance interrupt routines, software kernels or device drivers, and even frequently used data without these being flushed from the caches. The instruction and data caches are direct mapped with a write-back system for the data cache and support burst accesses to the external memories for refill and write-back which are effective for increasing performance with page-mode and SDRAM memories. The STi5505 EMI controls access to the external memory and peripherals while the SDRAM EMI provides access to the SDRAM buffer for the MPEG decoders, ST20 and DMA peripherals. The STi5505 EMI can access a 16 Mbytes (or greater if DRAM is used) physical address space in each of the four general purpose memory banks, and provides sustained transfer rates of up to 80 Mbytes/s. Peripherals that support an asynchronous data acknowledge are supported as is an external Power PC which can share the bus with the STi5505 and access the SDRAM buffer through the device. High memory bandwidths up to 200 Mbytes/s can be supported by the SDRAM EMI. The STi5505 internal memory interconnect provides buffering and arbitration of memory access requests to sustain very high throughput of memory accesses. III.3 - Syste m Services Module The STi5505 system services module includes : - Phase locked loop (PLL) - accepts 27MHz input and generates all the internal high frequency clocks needed for the CPU and the OS-Link. - test access port - JTAG compatible. - Diagnostics controller accessed via the JTAG port providing : - Bootstrapping during development - Hardware breakpoint and watchpoint - Real time trace - External LSA triggering support. III.4 - Serial Communications To facilitate the connection of this system the front end device and other peripherals, two UARTs (ASCs) are included in the device. The UARTs provide an asynchronous serial interface. The UART can be programmed to support a range of baud rates and data formats, for example, data size, stop bits and parity. Two synchronous serial communications (SSC) interfaces are provided on the device. These can be used for a remote control device for example via an I2C or SPI bus. III.5 - Interrupt Subsystem The STi5505 interrupt subsystem supports eight prioritized interrupt levels. Two external interrupt pins are provided. Level assignment logic allows any of the internal or external interrupts to be assigned and, if necessary, share any interrupt level. III.6 - Front End Interf ace & DVD Decryption The front end interface accepts sectors in the case of DVD, MPEG-1 system stream in the case of VCD and PCM data for CD-DA applications on an I2S interface. In the case of VCD and CD-DA disks the subcode information is input via a simple asynchronous serial interface similar to a UART. The bitstream and subcode stream then pass through a "sector processor" block which handles sector filtering in the case of DVD and sectorizing using the subcode stream for VCD and CD-DA systems. GB 82 9. ASD-1 IC Descriptions. STi5505 (Rev. Ax) III - FUNCTIONAL DESCRIPTION (continued) The block also handles overspeed processing for all systems. The capturing of CD-DA sectors is based on a flywheel tiner to improve robusters by concealing erros in the subcode stream. For DVD the data, having had sector headers removed, then passes through a DVD conformant de-cryption stage and is written into any of the system memories using a programmable DMA engine. When a subcode stream is present it is locally buffered, by subcode block and can be read by the CPU for subsequent processing, if required. III.7 - PWM and counter module This unit includes three separate pulse width modulator (PWM) generators using a shared counter, and three timer compare and capture channels sharing a second counter. The counters can be clocked from a pre-scaled internal clock or from a pre-scaled external clock via the capture clock input and the event on which the timer value is captured is also programmable. The PWM counters are 8-bit with 8-bit registers to set the output high time. The capture/compare counter and the compare and capture registers are 32-bit. III.8 - Parallel Programmable IO module 40 bits of parallel I/O are provided. 34 of then are connected to actual PIO pins. Each bit is programmable as an output or an input. The output can be configured as a totem pole or open drain driver. Input compare logic is provided which can generate an interrupt on any change on any input bit. Many pins of the STi5505 device are multi-function and can either be configured as PIO or connected to an internal peripheral signal. III.9 - MPEG Video decoder The video decoder is a real-time video compression processor supporting the MPEG-1 and MPEG2 standards at video rates up to 720 x 480 x 60 Hz and 720 x 576 x 50 Hz. Picture format conversion for display is performed by vertical and horizontal filters. User-defined bitmaps may be superimposed on the display picture through use of the on-screen display function. III.10 - PAL/NTSC encoder The digital encoder which is integrated in the STi5505 converts a multiplexed 4:2:2 YUV stream into a standard analog baseband PAL/NTSC signal and into RGB analog components. The encoder can also perform closed-caption, CGMS or teletext encoding and allows MacrovisionTM 7.01/6.1 copy protection. III.11 - MPEG-2 Audio / Dolby AC-3 Decoder The audio decoder is a Dolby AC-3 decoder capable of decoding both 5.1 and 2 channel DVD comformant bitstreams. The decoder also handles MPEG1 (layers 1 & 2) and MPEG-2 layer 2 (6 channels). Downmix to 2 channels is possible for Dolby and MPEG standards with optional pro-logic encoding. The decoder directly accepts MPEG-2 PES streams as input. The decoder is capable of supporting IEC6958-IEC61937 formatted outputs for AC-3 and MPEG audio, linear PCM (left & right,16, 18, 20 & 24 bits), zero output (Mute mode) and PCM audio. IC Descriptions. ASD-1 9. GB 83 ST24E32 ST25E32 32K SERIAL I2C EEPROM with EXTENDED ADDRESSING NOT FOR NEW DESIGN COMPATIBLE with I2C EXTENDED ADDRESSING TWO WIRE SERIAL INTERFACE, SUPPORTS 400kHz PROTOCOL 1 MILLION ERASE/WRITE CYCLES, OVER the FULL SUPPLY VOLTAGE RANGE 40 YEARS DATA RETENTION SINGLE SUPPLY VOLTAGE ± 4.5V to 5.5V for ST24E32 version ± 2.5V to 5.5V for ST25E32 version WRITE CONTROL FEATURE BYTE and PAGE WRITE (up to 32 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH UP PERFORMANCES ST24E32 and ST25E32 are replaced by the M24C32 DESCRIPTION The ST24/25E32 are 32K bit electrically erasable programmable memories (EEPROM), organized as 8 blocks of 512 x 8 bits. The ST25E32 operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available. 8 8 1 1 PSDIP8 (B) 0.25mm Frame SO8 (M) 200mil Width Figure 1. Logic Diagram VCC 3 E0-E2 SCL SDA ST24E32 ST25E32 WC Table 1. Signal Names E0 - E2 Chip Enable Inputs SDA Serial Data Address Input/Output SCL Serial Clock WC Write Control VCC Supply Voltage VSS Ground VSS AI01201B GB 84 9. IC Descriptions. ASD-1 ST24E32, ST25E32 Figure 2A. DIP Pin Connections Figure 2B. SO Pin Connections ST24E32 ST25E32 ST24E32 ST25E32 E0 E1 E2 VSS 1 2 3 4 8 7 6 5 VCC WC SCL SDA E0 E1 E2 VSS AI01202B 1 2 3 4 8 7 6 5 VCC WC SCL SDA AI01203C Table 2. Absolute Maximum Ratings (1) Symbol Value Unit Ambient Operating Temperature ±40 to 125 °C TSTG Storage Temperature ±65 to 150 °C TLEAD Lead Temperature, Soldering 215 260 °C TA Parameter (SO8) (PSDIP8) 40 sec 10 sec VIO Input or Output Voltages ±0.6 to 6.5 V VCC Supply Voltage ±0.3 to 6.5 V VESD Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model) (3) (2) 4000 V 500 V Notes: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. 100pF through 1500Ω; MIL-STD-883C, 3015.7 3. 200pF through 0Ω; EIAJ IC-121 (condition C) DESCRIPTION (cont'd) Each memory is compatible with the I2C extended addressing standard, two wire serial interface which uses a bi-directional data bus and serial clock. The ST24/25E32carry a built-in 4 bit, unique device identification code (1010) corresponding to the I2C bus definition. The ST24/25E32 behave as slave devices in the I 2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START conditiongenerated by the bus master. The START condition is followed by a stream of 4 bits (identification code 1010), 3 bit Chip Enable input to form a 7 bit Device Select, plus one read/write bit and terminated by an acknowledge bit. Spare parts list ASD-1 10. GB 85 10. Spare parts list VAL6011 Various 0001 0002 0003 0004 0005 0006 0007 3139 197 60090 GENEVA LP LOADER ASSY 9305 022 60101 VAM6001/01 3139 194 00710 SUSPENSION 3139 194 00710 SUSPENSION 3139 194 00620 SUSPENSION 3139 194 00620 SUSPENSION 3139 197 60060 CLAMPER ASSEMBLY Loader Various 0004 0009 0010 0011 0012 4822 358 10266 3139 198 80010 4822 532 13097 TULE 3139 194 00270 3139 197 50060 Monoboard Various 1104 1106 1205 1300 1301 1603 1604 2422 025 15963 CON BM H 24P F 0.50 FFC SMD R 2422 025 16158 CON BM H 8P F 1.00 FFC 0.3 R 2422 540 98428 RES CER SM 8M467 CSTCC8.46MHz R 2422 540 98426 RES CER SM 6MHz CSTCC6.00MHz R 4822 267 51454 CONN. 11P FEMALE 2422 025 16389 CON BM V 22P F 1.00 FFC 0.3 R 2422 025 16388 CON BM V 16P F 1.00 FFC 0.3 R g 2100 2101 2103 2104 2105 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2120 2121 2123 2124 2125 2126 2127 2128 2129 2130 2131 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2203 2204 2205 2206 2207 4822 126 14305 4822 126 14305 4822 124 80151 4822 126 13193 4822 122 33761 4822 126 13956 4822 126 14315 2020 552 95697 2222 861 15222 4822 126 14305 5322 126 11578 4822 126 14305 4822 122 31765 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 13879 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14508 4822 126 14508 4822 122 33761 4822 126 14494 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14241 4822 122 33761 5322 126 11583 4822 126 13883 4822 126 13883 4822 126 13883 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14549 5322 126 11578 100nF 10% 16V 0603 100nF 10% 16V 0603 47µF 16V 4.7nF 10% 63V 22pF 5% 50V 68pF 5% 63V CASE 0603 390pF 5% 50V 0603 50V 2N2 PM5 100nF 10% 16V 0603 1nF 10% 50V 0603 100nF 10% 16V 0603 100pF 2% 63V 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 220nF 20% 16V 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 180pF 5% 50V 0603 180pF 5% 50V 0603 22pF 5% 50V 22nF 10% 25V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 0603 50V 330P COL R 22pF 5% 50V 10nF 10% 50V 0603 220pF 5% 50V 220pF 5% 50V 220pF 5% 50V 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 33nF 16V O6O3 1nF 10% 50V 0603 2208 2209 2210 2212 2213 2215 2216 2226 2227 2228 2300 2301 2302 2303 2306 2309 2310 2314 2315 2318 2319 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2418 2419 2420 2500 2502 4822 126 14305 4822 126 14305 5322 126 11578 4822 126 14305 4822 126 14305 4822 124 23237 5322 126 11578 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 124 80349 4822 124 23002 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 5322 122 33861 4822 126 11669 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 124 12095 4822 124 80349 4822 124 80349 4822 126 14305 3198 030 74780 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 4822 126 14305 4822 122 31765 4822 126 14494 4822 124 23002 4822 126 14305 5322 126 11579 4822 126 14241 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 3198 030 74780 2531 3198 030 74780 2532 2533 2534 2535 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2614 2615 4822 122 33777 4822 122 33777 5322 126 11578 5322 126 11578 4822 126 14494 4822 126 14247 4822 126 14247 4822 126 14305 4822 124 12095 4822 126 14494 4822 124 12095 4822 124 12095 4822 124 23002 4822 124 80151 4822 126 14305 4822 124 12095 4822 122 33777 4822 122 33777 100nF 10% 16V 0603 100nF 10% 16V 0603 1nF 10% 50V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 22µF 6.3V 1nF 10% 50V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 47µF 20% 6.3V 10µF 16V 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 120pF 10% 50V 27pF 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100µF 20% 16V 47µF 20% 6.3V 47µF 20% 6.3V 100nF 10% 16V 0603 EL SM 35V 4U7 PM20 COL R 100nF 10% 16V 0603 100pF 2% 63V 22nF 10% 25V 0603 10µF 16V 100nF 10% 16V 0603 3.3nF 10% 63V 0603 50V 330P COL R 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 EL SM 35V 4U7 PM20 COL R EL SM 35V 4U7 PM20 COL R 47pF 5% 63V 47pF 5% 63V 1nF 10% 50V 0603 1nF 10% 50V 0603 22nF 10% 25V 0603 0603 50V 1N5 COL R 0603 50V 1N5 COL R 100nF 10% 16V 0603 100µF 20% 16V 22nF 10% 25V 0603 100µF 20% 16V 100µF 20% 16V 10µF 16V 47µF 16V 100nF 10% 16V 0603 100µF 20% 16V 47pF 5% 63V 47pF 5% 63V 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2632 2633 2634 2635 2636 2637 2638 2639 4822 122 33777 4822 122 33777 4822 126 14305 4822 126 14305 4822 122 33777 4822 122 33777 4822 122 33777 4822 122 33777 4822 122 33777 4822 122 33777 4822 122 33777 4822 122 33777 4822 124 12095 4822 124 12095 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 4822 126 14305 47pF 5% 63V 47pF 5% 63V 100nF 10% 16V 0603 100nF 10% 16V 0603 47pF 5% 63V 47pF 5% 63V 47pF 5% 63V 47pF 5% 63V 47pF 5% 63V 47pF 5% 63V 47pF 5% 63V 47pF 5% 63V 100µF 20% 16V 100µF 20% 16V 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 100nF 10% 16V 0603 f 3100 3102 3103 3104 3105 3106 3107 3108 3110 3111 3112 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3137 3138 3139 3140 3141 3142 3143 3144 3146 3147 3148 3153 3155 3157 3158 3160 3161 3162 3163 3164 4822 117 11152 4Ω7 5% 5322 117 13034 1k5 1% 0.063W 0603 RC22H 5322 117 13034 1k5 1% 0.063W 0603 RC22H 5322 117 13062 390Ω 1% 0.063W 0603 RC22H 4822 051 30103 10k 5% 0.062W 4822 051 30479 47Ω 5% 0.062W 4822 051 20228 2Ω2 5% 0.1W 4822 051 20228 2Ω2 5% 0.1W 4822 051 30479 47Ω 5% 0.062W 5322 117 13058 150Ω 1% 0.063W 0603 RC22H 5322 117 13021 47Ω 1% 0.063W 0603 RC22H 4822 051 20228 2Ω2 5% 0.1W 4822 051 20228 2Ω2 5% 0.1W 5322 117 13042 3k9 1% 0.063W 0603 RC22H 4822 051 30181 180Ω 5% 0.062W 4822 051 30681 680Ω 5% 0.062W 5322 117 13062 390Ω 1% 0.063W 0603 RC22H 4822 051 30102 1k 5% 0.062W 4822 051 30273 27k 5% 0.062W 4822 051 30471 470Ω 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 051 30471 470Ω 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 051 30223 22k 5% 0.062W 2322 704 69109 4822 051 30392 3k9 5% 0.063W 0603 4822 051 20228 2Ω2 5% 0.1W 4822 051 20228 2Ω2 5% 0.1W 4822 051 20228 2Ω2 5% 0.1W 4822 051 20228 2Ω2 5% 0.1W 5322 117 13047 330Ω 1% 0.063W 0603 RC22H 4822 117 13613 2Ω2 5% 0603 4822 117 13613 2Ω2 5% 0603 5322 117 13053 6k8 1% 0.063W 0603 RC22H 4822 117 12917 1Ω 5% 0.062W CASE0603 4822 051 30479 47Ω 5% 0.062W 4822 117 11152 4Ω7 5% 5322 117 13028 12k 1% 0.063W 0603 RC22H 5322 117 13043 220Ω 1% 0.063W 0603 RC22H 2322 704 69109 4822 051 30103 10k 5% 0.062W 4822 051 30103 10k 5% 0.062W 5322 117 13022 22k 1% 0.063W 0603 RC22H 4822 117 12139 22Ω 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 051 30103 10k 5% 0.062W 5322 117 13017 100Ω 1% 0.063W 0603 RC22H 4822 051 30101 100Ω 5% 0.062W 4822 117 13613 2Ω2 5% 0603 4822 051 30101 100Ω 5% 0.062W 4822 051 30273 27k 5% 0.062W 4822 117 13613 2Ω2 5% 0603 GB 86 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3178 3179 3180 3181 3182 3183 3184 3185 3187 3189 3190 3191 3192 3193 3194 3195 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3208 3209 3210 3211 3212 3213 3214 3215 3219 3220 3221 3224 3225 3226 3227 3229 3230 3231 3232 3234 3235 3236 3237 3238 3239 3240 3242 3243 3246 3247 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3300 3301 3302 3304 3305 3309 3310 3311 10. Spare parts list ASD-1 5322 117 13063 120Ω 1% 0.063W 0603 RC22H 4822 051 30393 39k 5% 0.062W 4822 051 30101 100Ω 5% 0.062W 5322 117 13047 330Ω 1% 0.063W 0603 RC22H 4822 051 30101 100Ω 5% 0.062W 4822 051 30101 100Ω 5% 0.062W 4822 051 30101 100Ω 5% 0.062W 4822 117 13632 100k 1% 0603 0.62W 4822 117 13632 100k 1% 0603 0.62W 4822 117 11152 4Ω7 5% 4822 117 13613 2Ω2 5% 0603 4822 051 30153 15k 5% 0.062W 4822 117 11151 1Ω 5% 4822 051 30221 220Ω 5% 0.062W 4822 117 13632 100k 1% 0603 0.62W 4822 051 30561 560Ω 5% 0.062W 5322 117 13018 1k0 1% 0.063W 0603 RC22H 5322 117 13017 100Ω 1% 0.063W 0603 RC22H 2322 704 61204 4822 117 11151 1Ω 5% 4822 051 30273 27k 5% 0.062W 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 5322 117 13049 470Ω 1% 0.063W 0603 RC22H 5322 117 13042 3k9 1% 0.063W 0603 RC22H 4822 051 30103 10k 5% 0.062W 4822 117 11151 1Ω 5% 4822 117 11151 1Ω 5% 4822 051 30105 1M 5% 0.062W 4822 051 30331 330Ω 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 051 30272 2k7 5% 0.062W 4822 051 30472 4k7 5% 0.062W 4822 051 30392 3k9 5% 0.063W 0603 4822 051 30472 4k7 5% 0.062W 4822 117 11152 4Ω7 5% 4822 117 11152 4Ω7 5% 4822 051 30392 3k9 5% 0.063W 0603 4822 051 30103 10k 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 051 30151 150Ω 5% 0.062W 2322 704 62004 4822 051 30103 10k 5% 0.062W 4822 051 30472 4k7 5% 0.062W 4822 051 30123 12k 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 117 13613 2Ω2 5% 0603 4822 117 12902 8k2 1% 0.063W 0603 4822 117 13632 100k 1% 0603 0.62W 4822 051 30472 4k7 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 051 30008 0Ω jumper 4822 117 11151 1Ω 5% 4822 117 11151 1Ω 5% 4822 117 11152 4Ω7 5% 4822 051 30105 1M 5% 0.062W 4822 051 30221 220Ω 5% 0.062W 4822 051 30272 2k7 5% 0.062W 4822 051 30272 2k7 5% 0.062W 4822 051 30103 10k 5% 0.062W 4822 051 30223 22k 5% 0.062W 4822 051 30223 22k 5% 0.062W 3312 3313 3316 3317 3318 3319 3320 3321 3322 4822 051 30472 4822 051 30472 4822 051 20108 4822 051 20108 4822 051 30472 4822 051 30479 4822 051 30472 4822 051 30682 5322 117 13026 3323 5322 117 13026 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3403 3404 3405 3412 3414 3416 3500 3501 3502 3503 3504 3505 3506 3507 3508 4822 117 13632 4822 051 30682 4822 051 30479 4822 051 30682 4822 051 30223 4822 051 30223 4822 051 30223 4822 051 30332 4822 051 30332 4822 051 30101 4822 051 30101 4822 051 30101 4822 051 30101 4822 051 30101 4822 051 30101 4822 051 30008 4822 051 30008 4822 051 30103 4822 051 30103 4822 051 30103 4822 051 30008 4822 051 30008 4822 051 30008 4822 051 30332 4822 051 30332 4822 051 30223 4822 051 30103 4822 051 30103 4822 051 30103 4822 051 30103 4822 051 30472 4822 051 30689 3509 3511 3512 3513 3514 3515 3516 3517 3519 3520 3521 3522 3523 3524 3525 3526 3534 3535 3536 3537 3538 3541 3542 3545 3546 3548 3549 3550 3551 3552 3554 3564 3566 3570 3571 4822 051 30103 4822 051 30332 4822 051 30332 4822 051 30103 4822 051 30103 4822 051 30103 4822 051 30103 4822 051 30332 4822 051 30103 4822 051 30103 4822 051 30103 4822 051 30103 4822 051 30332 4822 051 30101 4822 051 30103 4822 051 30103 4822 051 30103 4822 051 30153 4822 051 30101 4822 051 30331 4822 051 30681 4822 051 30479 4822 051 30479 4822 051 30221 4822 051 30101 4822 051 30008 4822 051 30008 4822 051 30101 4822 051 30101 4822 051 30008 4822 051 30008 4822 051 30008 4822 051 30008 4822 051 30101 4822 051 30689 3572 4822 051 30689 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 4822 051 30008 4822 117 12925 4822 117 13632 4822 117 13632 4822 117 13632 4822 051 30103 4822 051 30103 4822 051 30103 4822 051 30103 4822 051 30103 4822 051 30103 4k7 5% 0.062W 4k7 5% 0.062W 1Ω 5% 0.1W 1Ω 5% 0.1W 4k7 5% 0.062W 47Ω 5% 0.062W 4k7 5% 0.062W 6k8 5% 0.062W 4k7 1% 0.063W 0603 RC22H 4k7 1% 0.063W 0603 RC22H 100k 1% 0603 0.62W 6k8 5% 0.062W 47Ω 5% 0.062W 6k8 5% 0.062W 22k 5% 0.062W 22k 5% 0.062W 22k 5% 0.062W 3k3 5% 0.062W 3k3 5% 0.062W 100Ω 5% 0.062W 100Ω 5% 0.062W 100Ω 5% 0.062W 100Ω 5% 0.062W 100Ω 5% 0.062W 100Ω 5% 0.062W 0Ω jumper 0Ω jumper 10k 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 0Ω jumper 0Ω jumper 0Ω jumper 3k3 5% 0.062W 3k3 5% 0.062W 22k 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 4k7 5% 0.062W 68Ω 5% 0.063W 0603 RC21 RST SM 10k 5% 0.062W 3k3 5% 0.062W 3k3 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 3k3 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 3k3 5% 0.062W 100Ω 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 15k 5% 0.062W 100Ω 5% 0.062W 330Ω 5% 0.062W 680Ω 5% 0.062W 47Ω 5% 0.062W 47Ω 5% 0.062W 220Ω 5% 0.062W 100Ω 5% 0.062W 0Ω jumper 0Ω jumper 100Ω 5% 0.062W 100Ω 5% 0.062W 0Ω jumper 0Ω jumper 0Ω jumper 0Ω jumper 100Ω 5% 0.062W 68Ω 5% 0.063W 0603 RC21 RST SM 68Ω 5% 0.063W 0603 RC21 RST SM 0Ω jumper 47k 1% 0.063W 0603 100k 1% 0603 0.62W 100k 1% 0603 0.62W 100k 1% 0603 0.62W 10k 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 10k 5% 0.062W 3616 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 4822 051 30103 4822 051 30223 4822 051 30223 4822 051 30101 4822 051 30101 4822 051 30101 4822 051 30101 4822 051 30101 4822 051 30101 4822 051 30102 4822 051 30471 4822 051 30471 4822 051 30472 4822 051 30221 2322 704 64301 3632 2322 704 64301 3633 2322 704 64301 3635 3636 3637 3642 3647 4822 051 30682 4822 051 30682 4822 051 30332 4822 051 30103 2322 704 64301 3648 2322 704 64301 3651 2322 704 64301 3654 2322 704 64301 3655 2322 704 64301 3656 2322 704 64301 3657 2322 704 64301 3658 3659 3660 3661 4822 051 30102 4822 051 30102 4822 051 30102 2322 704 64301 3662 3663 3664 4822 051 30102 4822 051 30102 2322 704 64301 3665 3667 3669 3670 3671 3672 3673 3677 3678 3679 3681 3683 3685 3686 3687 3688 3689 4822 117 12139 4822 051 30331 4822 051 30008 4822 051 30008 4822 051 30223 4822 051 30479 4822 051 30101 4822 051 30008 4822 051 30008 4822 051 30008 4822 051 30008 4822 051 30008 4822 051 30008 4822 051 30223 4822 051 30223 4822 051 30472 4822 051 30223 10k 5% 0.062W 22k 5% 0.062W 22k 5% 0.062W 100Ω 5% 0.062W 100Ω 5% 0.062W 100Ω 5% 0.062W 100Ω 5% 0.062W 100Ω 5% 0.062W 100Ω 5% 0.062W 1k 5% 0.062W 470Ω 5% 0.062W 470Ω 5% 0.062W 4k7 5% 0.062W 220Ω 5% 0.062W RST SM 0603 RC22H 430Ω PM1 R RST SM 0603 RC22H 430Ω PM1 R RST SM 0603 RC22H 430Ω PM1 R 6k8 5% 0.062W 6k8 5% 0.062W 3k3 5% 0.062W 10k 5% 0.062W RST SM 0603 RC22H 430Ω PM1 R RST SM 0603 RC22H 430Ω PM1 R RST SM 0603 RC22H 430Ω PM1 R RST SM 0603 RC22H 430Ω PM1 R RST SM 0603 RC22H 430Ω PM1 R RST SM 0603 RC22H 430Ω PM1 R RST SM 0603 RC22H 430Ω PM1 R 1k 5% 0.062W 1k 5% 0.062W 1k 5% 0.062W RST SM 0603 RC22H 430Ω PM1 R 1k 5% 0.062W 1k 5% 0.062W RST SM 0603 RC22H 430Ω PM1 R 22Ω 5% 0.062W 330Ω 5% 0.062W 0Ω jumper 0Ω jumper 22k 5% 0.062W 47Ω 5% 0.062W 100Ω 5% 0.062W 0Ω jumper 0Ω jumper 0Ω jumper 0Ω jumper 0Ω jumper 0Ω jumper 22k 5% 0.062W 22k 5% 0.062W 4k7 5% 0.062W 22k 5% 0.062W 4822 157 11717 4822 157 11717 4822 157 11717 4822 157 11499 4822 157 11499 4822 157 70299 4822 157 70299 4822 157 71206 4822 157 71206 4822 157 71206 4822 157 11499 4822 157 10547 4822 157 71206 4822 157 10547 4822 157 10547 4822 157 10547 4822 157 10547 4822 157 10547 4822 157 11717 4822 157 11717 BLM31P500SPT BLM31P500SPT BLM31P500SPT BLM11P600SPT BLM11P600SPT 2.2µH (NL322522T-2R2J) 2.2µH (NL322522T-2R2J) BLM21A601SPT BLM21A601SPT BLM21A601SPT BLM11P600SPT 15µH 5% BLM21A601SPT 15µH 5% 15µH 5% 15µH 5% 15µH 5% 15µH 5% BLM31P500SPT BLM31P500SPT b 5200 5300 5301 5402 5403 5501 5502 5503 5504 5600 5601 5602 5603 5604 5605 5606 5607 5608 5609 5610 d 6200 6301 4822 130 11397 BAS316 9322 128 69685 S1D Spare parts list 6302 6303 6600 9322 128 69685 S1D 9322 128 69685 S1D 4822 130 11528 1PS76SB10 ce 7100 7101 7102 7103 7104 7105 7106 7109 7110 7111 7112 7113 7114 7115 7116 7201 7202 7203 7207 7304 7310 7311 7312 7315 7401 7404 5322 130 42718 5322 130 42718 9352 637 37518 4822 209 17229 4822 209 30095 4822 209 32073 5322 130 42718 4822 209 15083 5322 130 60803 5322 130 60159 5322 130 60159 5322 130 60159 5322 130 60159 4822 130 60373 5322 130 60159 9351 869 80118 3104 123 95660 4822 130 60373 9352 636 60557 4822 209 16877 4822 209 15899 9352 622 13557 4822 130 60373 5322 130 60159 9322 132 01668 9322 144 59668 7405 9322 144 59668 7501 7503 5322 130 60159 9322 151 16671 7504 7505 4822 242 10838 8204 056 05580 7600 7604 7605 7607 7608 7609 7610 7611 7612 7613 7614 7615 7616 7617 7618 7620 7621 5322 209 71568 5322 130 60159 4822 209 17398 5322 130 60159 4822 130 60373 4822 130 60373 5322 130 60159 9352 456 80115 5322 130 60159 5322 130 60159 5322 130 60159 5322 130 60159 4822 209 16062 5322 130 60159 5322 130 60159 4822 130 60373 4822 130 42804 BFS20 BFS20 BA5938FM LM833D MC34072D BFS20 AN78M09 BST72A BC846B BC846B BC846B BC846B BC856B BC846B BC856B SAA7399HL/M2A BA6856FP CY7C199-15C SAA7335HL BC856B BC846B AM29LV160B IC SM MT48LC1M16A1TG7S (MRN)R IC SM MT48LC1M16A1TG7S (MRN)R BC846B IC SM STI5505AVC (ST00) Y 27MHZ 120P FX0-31FT IC SM M24C32WMN6TNKSA PC74HCT14T BC846B LD1117DT33 BC846B BC856B BC856B BC846B BC846B BC846B BC846B BC846B MK2742-03S BC846B BC846B BC856B BC817-25 ASD-1 10. GB 87