Presentation ER 4096B 20120823 S203C Chevallier
User Manual: ER 4096B
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Christophe Chevallier Rambus Inc. August 22, 2012 © 2012 Rambus Inc. Tuesday, August 28, 12 1 True Cross Point Arrays, without a transistor per cell, are necessary to achieve high density memories. Can they be fast too? Typical RRAM cell has a transistor as select device © 2012 Rambus Inc. Tuesday, August 28, 12 RRAM cell in a cross point for very high density 2 True Cross Point Arrays, without a transistor per cell, are necessary to achieve high density memories. Can they be fast too? Typical RRAM cell has a transistor as select device © 2012 Rambus Inc. Tuesday, August 28, 12 RRAM cell in a cross point for very high density 2 True Cross Point Arrays, without a transistor per cell, are necessary to achieve high density memories. Can they be fast too? Typical RRAM cell has a transistor as select device © 2012 Rambus Inc. Tuesday, August 28, 12 RRAM cell in a cross point for very high density 2 Cross Point Arrays can achieve high read and write bandwidth in high density memories • Techniques: • • • • • Hierarchical Bit Line structure IR drop compensation Low current cell Gain Stage Sensing Parallelism • Impact: • Improved read / write throughput • Improved read latency © 2012 Rambus Inc. Tuesday, August 28, 12 3 Section 3b: Local Bitline Cross Point Array – Architecture Local Bitline Architecture .. .. .. .. .. . . . . . Local Bitline “breaks” 128 Rows = Local Bitline 128 Rows = Local Bitline Local Bitline Xdecoder LBL gate drv VIA drops down to CMOS Xdecoder 2 Mb arrays LBL gate drv Xdecoder Global Bitline LBL gate drv Local Bit Line select transistor SA Global Bit Line Mux 256 Mb arrays “Bricks” divided in 2Mb local blocks © 2012 Rambus Inc. Tuesday, August 28, 12 4 Row IR Drop with ΔV and location compensation, plus counter bias 1.5V 1.6V 2.5V across cell to be written ratio ratio ~0.5V -1.0V Floating lines • Adjust Driver voltage depending on location of cells being programmed • Added bias on unselected Word Lines will bias unselected Bit Lines • Total Word Line current around 100 uA © 2012 Rambus Inc. Tuesday, August 28, 12 5 Latency - constrained by sensing Small array è shorter latency Low current è longer latency Cell LBL LBL 255 Unselected Cell GBL Gain Stage Gain Stage Sensing 1)Isolates Local Bit Line from Global Bit Line capacitance 2)Amplifies LBL signal 3)Bypass for write access 4)Vt offset compensation 5)Reduced Latency from 50 µs to under 5 µs. © 2012 Rambus Inc. Tuesday, August 28, 12 Sense-amp 6 Power and Speed: Single Block Throughput Read 16 rows in 1 Block to fill page buffer 16x50uS = 800µS à 10MB/sec I/O 8kB Page Buffer 4096b 4096b 4096b 4096b 4096b 4096b = 4096b sub-word read from Tile in one 50us sensing cycle © 2012 Rambus Inc. Tuesday, August 28, 12 7 4096b Power and Speed: Single Block Throughput Read 16 rows in 1 Block to fill page buffer 16x50uS = 800µS à 10MB/sec I/O 8kB Page Buffer 4096b 4096b 4096b 4096b 4096b 4096b = 4096b sub-word read from Tile in one 50us sensing cycle © 2012 Rambus Inc. Tuesday, August 28, 12 7 4096b Power and Speed: Single Block Throughput Read 16 rows in 1 Block to fill page buffer 16x50uS = 800µS à 10MB/sec I/O 8kB Page Buffer 4096b 4096b 4096b 4096b 4096b 4096b 16x = 4096b sub-word read from Tile in one 50us sensing cycle © 2012 Rambus Inc. Tuesday, August 28, 12 7 4096b Power and Speed: 16 Block Throughput Read 1 row in 16 Blocks to fill page buffer 1x50uS = 50uS à 160MB/sec I/O 8kB Page Buffer 64kb (+5) • • • 4096b 4096b 4096b • • • (+5) 4096b 4096b = 4096b sub-word read from Tile in one 50us sensing cycle © 2012 Rambus Inc. Tuesday, August 28, 12 8 4096b Power and Speed: 16 Block Throughput Read 1 row in 16 Blocks to fill page buffer 1x50uS = 50uS à 160MB/sec I/O 8kB Page Buffer 64kb (+5) • • • 1x 4096b 1x 4096b 1x 4096b 1x • • • (+5) 4096b 1x 4096b = 4096b sub-word read from Tile in one 50us sensing cycle © 2012 Rambus Inc. Tuesday, August 28, 12 8 1x 4096b Power and Speed: 16 Block Throughput Read 1 row in 16 Blocks to fill page buffer 1x50uS = 50uS à 160MB/sec I/O 8kB Page Buffer 64kb (+5) • • • 1x 4096b 1x 4096b 1x 4096b 1x • • • (+5) 4096b 1x 4096b 1x 4096b + Page Erase / Simplified block management = 4096b sub-word read from Tile in one 50us sensing cycle © 2012 Rambus Inc. Tuesday, August 28, 12 8 512Gb/1Tb Storage Chip with Multi-Plane Architecture (4k x 128 x 4) x 128 = 256Mb per Brick [ (4k x 128 x 4) x 128 ] x 16 = 4Gb per Sub-Plane Page is 1 row of cells across 16 Blocks/Bricks Tile PB µC Ana 125MB/s µC PB © 2012 Rambus Inc. Tuesday, August 28, 12 µC Ana Ana 125MB/s 125MB/s Timing Master µC I/F ≥500MB/s DDR 9 (4k x 128 x 4) x 128 x 16 x 32 = 128Gb per Plane x4 = 512Gb (SLC) X2 (MLC) Plane 3 Plane 1 PB Plane 2 “Erase” Block is 1 row of Blocks across 16 Bricks Plane 0 (32 Sub-Planes) Brick = 128 Tiles Sub-Plane = 16 Bricks PB µC Ana 125MB/s = 1Tb (256K Tiles) Conclusion from RRAM Cell to System © 2012 Rambus Inc. Tuesday, August 28, 12 10 Conclusion from RRAM Cell to System Low Current Cell © 2012 Rambus Inc. Tuesday, August 28, 12 Vertical Processing 10 Self-select (no select transistor) Conclusion from RRAM Cell to System Stackable Cross-Point Hierarchical BL Low Current Cell © 2012 Rambus Inc. Tuesday, August 28, 12 Small Arrays / Parallelism Vertical Processing 10 Self-select (no select transistor) Conclusion from RRAM Cell to System WL Control Gain Stage Sensing Stackable Cross-Point Hierarchical BL Low Current Cell © 2012 Rambus Inc. Tuesday, August 28, 12 Byte / Page Erase Small Arrays / Parallelism Vertical Processing 10 Self-select (no select transistor) Conclusion from RRAM Cell to System High Speed Interface Low Power WL Control Gain Stage Sensing Stackable Cross-Point Hierarchical BL Low Current Cell © 2012 Rambus Inc. Tuesday, August 28, 12 Byte / Page Erase Small Arrays / Parallelism Vertical Processing 10 Self-select (no select transistor) Conclusion from RRAM Cell to System Tb Memory, High System Bandwidth High Speed Interface Low Power WL Control Gain Stage Sensing Stackable Cross-Point Hierarchical BL Low Current Cell © 2012 Rambus Inc. Tuesday, August 28, 12 Byte / Page Erase Small Arrays / Parallelism Vertical Processing 10 Self-select (no select transistor)
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