MSP430x5xx And MSP430x6xx Family (Rev. O) 5529 User's Guide Slau208o

User Manual:

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Table of Contents
Preface
1 System Resets, Interrupts, and Operating Modes, System Control Module (SYS)
- 1.1 System Control Module (SYS) Introduction
- 1.2 System Reset and Initialization
  - 1.2.1 Device Initial Conditions After System Reset
- 1.3 Interrupts
- 1.4 Operating Modes
- 1.5 Principles for Low-Power Applications
- 1.6 Connection of Unused Pins
- 1.7 Reset Pin (RST/NMI) Configuration
- 1.8 Configuring JTAG Pins
- 1.9 Boot Code
- 1.10 Bootstrap Loader (BSL)
- 1.11 Memory Map – Uses and Abilities
  - 1.11.1 Vacant Memory Space
  - 1.11.2 JTAG Lock Mechanism Using the Electronic Fuse
- 1.12 JTAG Mailbox (JMB) System
- 1.13 Device Descriptor Table
- 1.14 SFR Registers
- 1.15 SYS Registers
2 Power Management Module and Supply Voltage Supervisor
- 2.1 Power Management Module (PMM) Introduction
- 2.2 PMM Operation
- 2.3 PMM Registers
3 Battery Backup System
- 3.1 Battery Backup Introduction
- 3.2 Battery Backup Operation
- 3.3 Battery Backup Registers
  - 3.3.1 BAKCTL Register
  - 3.3.2 BAKCHCTL Register
4 Auxiliary Supply System (AUX)
- 4.1 Auxiliary Supply System Introduction
- 4.2 Auxiliary Supply Operation
- 4.3 AUX Registers
5 Unified Clock System (UCS)
- 5.1 Unified Clock System (UCS) Introduction
- 5.2 UCS Operation
- 5.3 Module Oscillator (MODOSC)
  - 5.3.1 MODOSC Operation
- 5.4 UCS Registers
6 CPUX
- 6.1 MSP430X CPU (CPUX) Introduction
- 6.2 Interrupts
- 6.3 CPU Registers
- 6.4 Addressing Modes
- 6.5 MSP430 and MSP430X Instructions
  - 6.5.1 MSP430 Instructions
  - 6.5.2 MSP430X Extended Instructions
- 6.6 Instruction Set Description
7 Flash Memory Controller
- 7.1 Flash Memory Introduction
- 7.2 Flash Memory Segmentation
  - 7.2.1 Segment A
- 7.3 Flash Memory Operation
- 7.4 FCTL Registers
8 Memory Integrity Detection (MID)
- 8.1 MID Overview
- 8.2 Flash Memory With MID Support
- 8.3 MID Parity Check Logic
- 8.4 Detecting Unprogrammed Memory Accesses
- 8.5 MID ROM
- 8.6 MID Support Software Function
- 8.7 User's UNMI Interrupt Handler
9 RAM Controller (RAMCTL)
- 9.1 RAM Controller (RAMCTL) Introduction
- 9.2 RAMCTL Operation
- 9.3 RAMCTL Registers
  - 9.3.1 RCCTL0 Register
10 Backup RAM
- 10.1 Backup RAM Introduction and Operation
- 10.2 Battery Backup Registers
11 Direct Memory Access (DMA) Controller Module
- 11.1 Direct Memory Access (DMA) Introduction
- 11.2 DMA Operation
- 11.3 DMA Registers
12 Digital I/O Module
- 12.1 Digital I/O Introduction
- 12.2 Digital I/O Operation
- 12.3 I/O Configuration and LPMx.5 Low-Power Modes
- 12.4 Digital I/O Registers
13 Port Mapping Controller
- 13.1 Port Mapping Controller Introduction
- 13.2 Port Mapping Controller Operation
  - 13.2.1 Access
  - 13.2.2 Mapping
- 13.3 Port Mapping Controller Registers
14 Cyclic Redundancy Check (CRC) Module
- 14.1 Cyclic Redundancy Check (CRC) Module Introduction
- 14.2 CRC Standard and Bit Order
- 14.3 CRC Checksum Generation
  - 14.3.1 CRC Implementation
  - 14.3.2 Assembler Examples
    - 14.3.2.1 General Assembler Example
    - 14.3.2.2 Reference Data Sequence
- 14.4 CRC Registers
15 AES Accelerator
- 15.1 AES Accelerator Introduction
- 15.2 AES Accelerator Operation
- 15.3 AES_ACCEL Registers
16 Watchdog Timer (WDT_A)
- 16.1 WDT_A Introduction
- 16.2 WDT_A Operation
- 16.3 WDT_A Registers
  - 16.3.1 WDTCTL Register
17 Timer_A
- 17.1 Timer_A Introduction
- 17.2 Timer_A Operation
- 17.3 Timer_A Registers
18 Timer_B
- 18.1 Timer_B Introduction
  - 18.1.1 Similarities and Differences From Timer_A
- 18.2 Timer_B Operation
- 18.3 Timer_B Registers
19 Timer_D
- 19.1 Timer_D Introduction
  - 19.1.1 Differences From Timer_B
- 19.2 Timer_D Operation
- 19.3 Timer_D Registers
20 Timer Event Control (TEC)
- 20.1 Timer Event Control Introduction
- 20.2 TEC Operation
- 20.3 TEC Registers
21 Real-Time Clock (RTC) Overview
- 21.1 RTC Overview
22 Real-Time Clock (RTC_A)
- 22.1 RTC_A Introduction
- 22.2 RTC_A Operation
- 22.3 RTC_A Registers
23 Real-Time Clock B (RTC_B)
- 23.1 Real-Time Clock RTC_B Introduction
- 23.2 RTC_B Operation
- 23.3 RTC_B Registers
24 Real-Time Clock C (RTC_C)
- 24.1 Real-Time Clock (RTC_C) Introduction
- 24.2 RTC_C Operation
- 24.3 RTC_C Operation - Device-Dependent Features
  - 24.3.1 Counter Mode
  - 24.3.2 Real-Time Clock Event/Tamper Detection With Time Stamp
    - 24.3.2.1 Real-Time Clock Event/Tamper Detection Interrupts
- 24.4 RTC_C Registers
25 32-Bit Hardware Multiplier (MPY32)
- 25.1 32-Bit Hardware Multiplier (MPY32) Introduction
- 25.2 MPY32 Operation
- 25.3 MPY32 Registers
  - 25.3.1 MPY32CTL0 Register
26 REF
- 26.1 REF Introduction
- 26.2 Principle of Operation
- 26.3 REF Registers
  - 26.3.1 REFCTL0 Register (offset = 00h) [reset = 0080h]
27 ADC10_A
- 27.1 ADC10_A Introduction
- 27.2 ADC10_A Operation
- 27.3 ADC10_A Registers
28 ADC12_A
- 28.1 ADC12_A Introduction
- 28.2 ADC12_A Operation
- 28.3 ADC12_A Registers
29 SD24_B
- 29.1 SD24_B Introduction
- 29.2 SD24_B Operation
- 29.3 SD24_B Registers
30 CTSD16
- 30.1 CTSD16 Introduction
- 30.2 CTSD16 Operation
- 30.3 CTSD16 Registers
31 DAC12_A
- 31.1 DAC12_A Introduction
- 31.2 DAC12_A Operation
- 31.3 DAC Outputs
- 31.4 DAC12_A Registers
32 Comp_B
- 32.1 Comp_B Introduction
- 32.2 Comp_B Operation
- 32.3 Comp_B Registers
33 Operational Amplifier (OA)
- 33.1 OA Introduction
- 33.2 OA Operation
- 33.3 Ground Switches
- 33.4 OA and Power Modes
- 33.5 OA Registers
34 LCD_B Controller
- 34.1 LCD_B Controller Introduction
- 34.2 LCD_B Controller Operation
- 34.3 LCD_B Registers
35 LCD_C Controller
- 35.1 LCD_C Introduction
- 35.2 LCD_C Operation
- 35.3 LCD_C Registers
36 Universal Serial Communication Interface – UART Mode
- 36.1 Universal Serial Communication Interface (USCI) Overview
- 36.2 USCI Introduction – UART Mode
- 36.3 USCI Operation – UART Mode
- 36.4 USCI_A UART Mode Registers
37 Universal Serial Communication Interface – SPI Mode
- 37.1 Universal Serial Communication Interface (USCI) Overview
- 37.2 USCI Introduction – SPI Mode
- 37.3 USCI Operation – SPI Mode
- 37.4 USCI_A SPI Mode Registers
- 37.5 USCI_B SPI Mode Registers
38 Universal Serial Communication Interface – I2C Mode
- 38.1 Universal Serial Communication Interface (USCI) Overview
- 38.2 USCI Introduction – I2C Mode
- 38.3 USCI Operation – I2C Mode
- 38.4 USCI_B I2C Mode Registers
39 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode
- 39.1 Enhanced Universal Serial Communication Interface A (eUSCI_A) Overview
- 39.2 eUSCI_A Introduction – UART Mode
- 39.3 eUSCI_A Operation – UART Mode
- 39.4 eUSCI_A UART Registers
40 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode
- 40.1 Enhanced Universal Serial Communication Interfaces (eUSCI_A, eUSCI_B) Overview
- 40.2 eUSCI Introduction – SPI Mode
- 40.3 eUSCI Operation – SPI Mode
- 40.4 eUSCI_A SPI Registers
- 40.5 eUSCI_B SPI Registers
41 Enhanced Universal Serial Communication Interface (eUSCI) – I2C Mode
- 41.1 eUSCI_B I2C Registers
42 USB Module
- 42.1 USB Introduction
- 42.2 USB Operation
- 42.3 USB Transfers
- 42.4 USB Registers
43 LDO-PWR Module
- 43.1 LDO-PWR Introduction
- 43.2 LDO-PWR Operation
- 43.3 LDO-PWR Registers
44 Embedded Emulation Module (EEM)
- 44.1 Embedded Emulation Module (EEM) Introduction
- 44.2 EEM Building Blocks
- 44.3 EEM Configurations
Revision History
Important Notice

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