AD9850
User Manual: AD9850
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a FEATURES 125 MHz Clock Rate On-Chip High Performance DAC & High Speed Comparator DAC SFDR > 50 dB @ 40 MHz AOUT 32-Bit Frequency Tuning Word Simplified Control Interface: Parallel Byte or Serial Loading Format Phase Modulation Capability +3.3 V or +5 V Single Supply Operation Low Power: 380 mW @ 125 MHz (+5 V) Low Power: 155 mW @ 110 MHz (+3.3 V) Power-Down Function Ultrasmall 28-Lead SSOP Packaging APPLICATIONS Frequency/Phase–Agile Sine-Wave Synthesis Clock Recovery and Locking Circuitry for Digital Communications Digitally Controlled ADC Encode Generator Agile Local Oscillator Applications GENERAL DESCRIPTION The AD9850 is a highly integrated device that uses advanced DDS technology, coupled with an internal high speed, high performance, D/A converter, and comparator, to form a complete digitally programmable frequency synthesizer and clock generator function. When referenced to an accurate clock source, the AD9850 generates a spectrally-pure, frequency/ phase-programmable, analog output sine wave. This sine wave can be used directly as a frequency source, or converted to a square wave for agile-clock generator applications. The AD9850’s innovative high speed DDS core provides a 32-bit frequency tuning word, which results in an output tuning resolution of 0.0291 Hz, for a 125 MHz reference clock input. The AD9850’s circuit architecture allows the generation of output frequencies of up to one-half the reference clock frequency, or 62.5 MHz, and the output frequency can be digitally changed (asynchronously) at a rate of up to 23 million new frequencies per second. The device also provides 5 bits of digitally controlled CMOS, 125 MHz Complete DDS Synthesizer AD9850 FUNCTIONAL BLOCK DIAGRAM +VS DAC RSET REF CLOCK IN HIGH SPEED DDS MASTER RESET 32-BIT TUNING WORD FREQUENCY UPDATE/ DATA REGISTER RESET WORD LOAD CLOCK GND 10-BIT DAC PHASE AND CONTROL WORDS ANALOG OUT ANALOG IN FREQUENCY/PHASE DATA REGISTER CLOCK OUT CLOCK OUT COMPARATOR DATA INPUT REGISTER SERIAL LOAD 1-BIT x 40 LOADS AD9850 PARALLEL LOAD 8-BITS x 5 LOADS FREQUENCY, PHASE, AND CONTROL DATA INPUT phase modulation which enables phase shifting of its output in increments of 180°, 90°, 45°, 22.5°, 11.25°, and any combination thereof. The AD9850 also contains a high speed comparator which can be configured to accept the (externally) filtered output of the DAC to generate a low jitter square wave output. This facilitates the device’s use as an agile clock generator function. The frequency tuning, control, and phase modulation words are loaded into the AD9850 via a parallel byte or serial loading format. The parallel load format consists of five iterative loads of an 8-bit control word (byte). The first byte controls phase modulation, power-down enable, and loading format; bytes 2–5 comprise the 32-bit frequency tuning word. Serial loading is accomplished via a 40-bit serial data stream on a single pin. The AD9850 Complete-DDS uses advanced CMOS technology to provide this breakthrough level of functionality and performance on just 155 mW of power dissipation (+3.3 V supply). The AD9850 is available in a space saving 28-lead SSOP, surface mount package. It is specified to operate over the extended industrial temperature range of –40°C to +85°C. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD9850–SPECIFICATIONS (V = +5 V 6 5% except as noted, R S Parameter SET = 3.9 kV) Temp Test Level Min FULL FULL IV IV 1 1 +25°C +25°C IV IV 3.2 4.1 +25°C +25°C +25°C FULL +25°C FULL +25°C +25°C +25°C +25°C +25°C +25°C V V I V I V I I V IV IV I +25°C +25°C +25°C IV IV IV +25°C +25°C +25°C +25°C IV IV IV IV COMPARATOR INPUT CHARACTERISTICS Input Capacitance Input Resistance Input Current Input Voltage Range Comparator Offset* +25°C +25°C +25°C +25°C FULL V IV I IV VI COMPARATOR OUTPUT CHARACTERISTICS Logic “1” Voltage +5 V Supply Logic “1” Voltage +3. 3 V Supply Logic “0” Voltage Propagation Delay, +5 V Supply (15 pF Load) Propagation Delay, +3.3 V Supply (15 pF Load) Rise/Fall Time, +5 V Supply (15 pF Load) Rise/Fall Time, +3.3 V Supply (15 pF Load) Output Jitter (p-p) FULL FULL FULL +25°C +25°C +25°C +25°C +25°C VI VI VI V V V V V CLOCK OUTPUT CHARACTERISTICS Clock Output Duty Cycle (Clk Gen. Config.) +25°C IV CLOCK INPUT CHARACTERISTICS Frequency Range +5 V Supply +3.3 V Supply Pulse Width High/Low +5 V Supply +3.3 V Supply DAC OUTPUT CHARACTERISTICS Full-Scale Output Current RSET = 3.9 kΩ RSET = 1.95 kΩ Gain Error Gain Temperature Coefficient Output Offset Output Offset Temperature Coefficient Differential Nonlinearity Integral Nonlinearity Output Slew Rate (50 Ω, 2 pF Load) Output Impedance Output Capacitance Voltage Compliance Spurious-Free Dynamic Range (SFDR): Wideband (Nyquist Bandwidth) 1 MHz Analog Out 20 MHz Analog Out 40 MHz Analog Out Narrowband 40.13579 MHz ± 50 kHz 40.13579 MHz ± 200 kHz 4.513579 MHz ± 50 kHz/20.5 MHz CLK 4.513579 MHz ± 200 kHz/20.5 MHz CLK –2– AD9850BRS Typ Max 125 110 –10 +10 150 10 50 0.5 0.5 400 120 0.75 1 8 1.5 63 50 46 MHz MHz ns ns 10.24 20.48 50 Units mA mA % FS ppm/°C µA nA/°C LSB LSB V/µs kΩ pF V 72 58 54 dBc dBc dBc 80 77 84 84 dBc dBc dBc dBc 3 pF kΩ µA V mV 500 –12 0 30 +12 VDD 30 +4.8 +3.1 5.5 7 3 3.5 80 V V V ns ns ns ns ps 50 ± 10 % +0.4 REV. 0 AD9850 AD9850BRS Min Typ Max Parameter Temp Test Level CMOS LOGIC INPUTS (Including CLKIN) Logic “1” Voltage, +5 V Supply Logic “1” Voltage, +3.3 V Supply Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance +25°C +25°C +25°C +25°C +25°C +25°C I I I I I V FULL FULL FULL FULL VI VI VI VI 30 47 44 76 48 60 64 96 mA mA mA mA FULL FULL FULL FULL VI VI VI VI 100 155 220 380 160 200 320 480 mW mW mW mW FULL FULL V V 30 10 POWER SUPPLY (AOUT = 1/3 CLKIN) +VS Current @: 62.5 MHz Clock, +3.3 V Supply 110 MHz Clock, +3.3 V Supply 62.5 MHz Clock, +5 V Supply 125 MHz Clock, +5 V Supply PDISS @: 62.5 MHz Clock, +3.3 V Supply 110 MHz Clock, +3.3 V Supply 62.5 MHz Clock, +5 V Supply 125 MHz Clock, +5 V Supply PDISS Power-Down Mode +5 V Supply +3.3 V Supply Units 3.5 3.0 V V V µA µA pF 0.4 12 12 3 mW mW NOTES *Tested by measuring output duty cycle variation. Specifications subject to change without notice. TIMING CHARACTERISTICS* (V = +5 V 6 5% except as noted, R S SET = 3.9 kV) Parameter Temp Test Level AD9850BRS Min Typ Max Units tDS tDH tWH tWL tWD tCD tFH tFL tCF FULL FULL FULL FULL FULL FULL FULL FULL IV IV IV IV IV IV IV IV 3.5 3.5 3.5 3.5 7.0 3.5 7.0 7.0 ns ns ns ns ns ns ns ns FULL FULL FULL FULL FULL FULL FULL FULL +25°C IV IV IV IV IV IV IV IV V 18 13 7.0 3.5 3.5 5 13 2 CLKIN Cycles CLKIN Cycles ns ns ns CLKIN Cycles CLKIN Cycles CLKIN Cycles µs tFD tRH tRL tRS tOL tRR (Data Setup Time) (Data Hold Time) (W_CLK min. Pulse Width High) (W_CLK min. Pulse Width Low) (W_CLK Delay After FQ_UD) (CLKIN Delay After FQ_UD) (FQ_UD High) (FQ_UD Low) (Output Latency from FQ_UD) Frequency Change Phase Change (FQ_UD Min. Delay After W_CLK) (CLKIN Delay After RESET Rising Edge) (RESET Falling Edge After CLKIN) (Minimum RESET Width) (RESET Output Latency) (Recovery from RESET) Wake-Up Time from Power-Down Mode NOTES *Control functions are asynchronous with CLKIN. Specifications subject to change without notice. REV. 0 –3– 5 AD9850 ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS Maximum Junction Temperature . . . . . . . . . . . . . . . . +165°C VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS Digital Output Continuous Current . . . . . . . . . . . . . . . . 5 mA DAC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . +300°C SSOP θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 82°C/W Test Level I – 100% Production Tested. III – Sample Tested Only. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – All devices are 100% production tested at +25°C. 100% production tested at temperature extremes for military temperature devices; guaranteed by design and characterization testing for industrial devices. *Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9850 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Model Temperature Range Package Option* AD9850BRS –40°C to +85°C RS-28 *RS = Shrink Small Outline (SSOP). –4– REV. 0 AD9850 Table I. Lead Function Descriptions Mnemonic Lead No. CLKIN 9 Reference Clock Input. This may be a continuous CMOS-level pulse train or sine input biased at 1/2 V supply. The rising edge of this clock initiates operation. RSET 12 This is the DAC’s external RSET connection. This resistor value sets the DAC full-scale output current. For normal applications (FS IOUT = 10 mA), the value for RSET is 3.9 kΩ connected to ground. The RSET/IOUT relationship is: IOUT = 32 (1.248 V/RSET). AGND 10, 19 Analog Ground. These leads are the ground return for the analog circuitry (DAC and comparator). Function DGND 5, 24 Digital Ground. These are the ground return leads for the digital circuitry. DVDD 6, 23 Supply Voltage Leads for digital circuitry. AVDD 11, 18 Supply Voltage for the analog circuitry (DAC and comparator). W_CLK 7 Word Load Clock. This clock is used to load the parallel or serial frequency/phase/control words. FQ_UD 8 Frequency Update. On the rising edge of this clock, the DDS will update to the frequency (or phase) loaded in the data input register, it then resets the pointer to Word 0. D0–D7 1–4, 25–28 8-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and 8-bit phase/ control word. D7 = MSB; D0 = LSB. D7 (Pin 25) also serves as the input pin for the 40-bit serial data word. RESET 22 Reset. This is the master reset function; when set high it clears all registers (except the input register) and the DAC output will go to Cosine 0 after additional clock cycles—see Figure 19. IOUT 21 Analog Current Output of the DAC. IOUTB 20 The Complementary Analog Output of the DAC. DACBL 17 DAC Baseline. This is the DAC baseline voltage reference; this lead is internally bypassed and should normally be considered a “no connect” for optimum performance. VIN 16 Noninverting voltage input. This is the comparator’s positive input. VINN 15 Inverting Voltage Input. This is the comparator’s negative input. QOUT 14 Output True. This is the comparator’s true output. QOUTB 13 Output Complement. This is the comparator’s complement output. PIN CONFIGURATIONS D3 1 28 D4 D2 2 27 D5 D1 3 26 D6 LSB D0 4 DGND 5 25 D7 MSB/SERIAL LOAD AD9850 24 DGND DVDD 6 TOP VIEW 23 DVDD W_CLK 7 (Not to Scale) 22 RESET FQ_UD 8 21 IOUT CLKIN 9 20 IOUTB AGND 10 19 AGND AVDD 11 18 AVDD RSET 12 17 DACBL (NC) QOUT 13 16 VINP QOUTB 14 15 VINN NC = NO CONNECT REV. 0 –5– AD9850–Typical Performance Characteristics CH1 Spectrum S AD9850 10dB/REF ∆ 76.642 dB –8.6dBm CLOCK _125MHz CH1 S Fxd∆ Spectrum 10dB/REF ∆ 59.925 dB –10dBm CLOCK _125MHz AD9850 Fxd∆ 0 0 RBW # 100Hz START 0Hz VBW 100Hz ATN # 30dB SWP 762 sec STOP 62.5MHz RBW # 300Hz START 0Hz Figure 1. SFDR, CLKIN = 125 MHz/FOUT = 1 MHz CH1 Spectrum S AD9850 10dB/REF ATN # 30dB SWP 182.6 sec STOP 62.5MHz Figure 4. SFDR, CLKIN = 125 MHz/FOUT = 20 MHz ∆ 54.818 dB –10dBm CLOCK _125MHz VBW 300Hz CH1 S Spectrum 12dB/REF 0dBm –85.401 dB –23 kHz AD9850 Fxd∆ ∆Mkr 0 0 RBW # 300Hz START 0Hz VBW 300Hz ATN # 30dB RBW # 3Hz VBW 3Hz CENTER 4.513579MHz SWP 182.6 sec STOP 62.5MHz ATN # 20dB SWP 399.5 sec SPAN 400kHz Figure 5. SFDR, CLKIN = 20.5 MHz/FOUT = 4.5 MHz Figure 2. SFDR, CLKIN = 125 MHz/FOUT = 41 MHz Tek Run: 100GS/s ET Sample –105 ∆: 300ps @: 25.26ns PN.3RD –110 –115 –120 dBc –125 –130 –135 –140 –145 1 –150 Ch 1 500mVΩ M 20.0ns D 500ps Ch 1 1.58V Runs After –155 100 Figure 3. Typical Comparator Output Jitter, AD9850 Configured as Clock Generator w/42 MHz LP Filter (40 MHz AOUT/125 MHz CLKIN) 10k 1k OFFSET FROM 5MHz CARRIER – Hz 100k Figure 6. Output Phase Noise (5 MHz AOUT/125 MHz CLKIN) –6– REV. 0 AD9850 Tek Run: 50.0GS/s ET Average Tek Run: 50.0GS/s ET Average Ch 1 Fall 3.202ns Ch 1 Rise 2.870ns 1 1 Ch1 1.00VΩ M 1.00ns Ch 1 Ch1 1.00VΩ 1.74V 1.74V Figure 10. Comparator Output Fall Time (5 V Supply/15 pF Load) Figure 7. Comparator Output Rise Time (5 V Supply/15 pF Load) 90 68 fOUT = 1/3 OF CLKIN 80 64 70 SUPPLY CURRENT – mA 66 62 SFDR – dB M 1.00ns Ch 1 60 VCC = 5V 58 VCC = 3.3V 56 VCC = 5V 60 50 40 30 VCC = 3.3V 20 54 10 52 0 20 40 60 80 CLKIN – MHz 100 120 0 140 75 80 70 VCC = 5V 120 140 fOUT = 1MHz 65 SFDR – dB SUPPLY CURRENT – mA 90 60 VCC = 3.3V 50 40 60 80 100 CLOCK FREQUENCY – MHz Figure 11. Supply Current vs. CLKIN Frequency (AOUT = 1/3 of CLKIN) Figure 8. SFDR vs. CLKIN Frequency (AOUT = 1/3 of CLKIN) 70 20 60 fOUT = 20MHz 55 fOUT = 40MHz 40 50 30 0 10 20 30 FREQUENCY OUT – MHz 45 40 5 Figure 9. Supply Current vs. AOUT Frequency (CLKIN = 125/110 MHz for 5 V/3.3 V Plot) REV. 0 10 15 DAC IOUT – mA 20 Figure 12. SFDR vs. DAC IOUT (AOUT = 1/3 of CLKIN) –7– AD9850 5-POLE ELLIPTICAL 42MHz LOW PASS 200Ω IMPEDANCE GND +VS DATA BUS 8-b x 5 PARALLEL DATA, OR 1-b x 40 SERIAL DATA, RESET, AND 2 CLOCK LINES XTAL OSC CLK 125MHz 470pF AD9850 COMPLETE-DDS 100kΩ AD9850 FILTER 200Ω 100kΩ IOUTB VINN VINP QOUT QOUTB RF FREQUENCY OUT FILTER LOW PASS FILTER IOUT PROCESSOR IF FREQUENCY IN 100Ω TUNING WORD REFERENCE a. Frequency/Phase–Agile Local Oscillator 200Ω CMOS CLOCK OUTPUTS RSET 125MHz COMP TRUE REFERENCE CLOCK Figure 13. Basic AD9850 Clock Generator Application with Low-Pass Filter AD9850 COMPLETEDDS FILTER PHASE COMPARATOR LOOP FILTER RF FREQUENCY OUT VCO DIVIDE-BY-N TUNING WORD b. Frequency/Phase–Agile Reference for PLL I 8 I/Q MIXER AD9059 AND DUAL 8-BIT 8 LOW PASS Q ADC FILTER Rx IF IN VCA ADC CLOCK FREQUENCY LOCKED TO Tx CHIP/ SYMBOL PN RATE 125MHz REFERENCE CLOCK DIGITAL DEMODULATOR Rx BASEBAND DIGITAL DATA OUT REF FREQUENCY PHASE COMPARATOR AGC ADC ENCODE VCO PROGRAMMABLE “DIVIDE-BY-N” FUNCTION FILTER AD9850 32 CLOCK GENERATOR CHIP/SYMBOL/PN RATE DATA LOOP FILTER RF FREQUENCY OUT AD9850 COMPLETEDDS TUNING WORD Figure 14. AD9850 Clock Generator Application in a Spread-Spectrum Receiver c. Digitally-Programmable ”Divide-by-N“ Function in PLL Figure 15. AD9850 Complete-DDS Synthesizer in Frequency Up-Conversion Applications THEORY OF OPERATION AND APPLICATION The AD9850 utilizes direct digital synthesis (DDS) technology, in the form of a numerically controlled oscillator, to generate a frequency/phase-agile sine wave. The digital sine wave is converted to analog form via an internal 10-bit high speed D/A converter and an onboard high speed comparator is provided to translate the analog sine wave into a low-jitter TTL/CMOScompatible output square wave. DDS technology is an innovative circuit architecture that allows fast and precise manipulation of its output frequency, under full digital control. DDS also enables very high resolution in the incremental selection of output frequency; the AD9850 allows an output frequency resolution of 0.0291 Hz, with a 125 MHz reference clock applied. The AD9850’s output waveform is phase-continuous when changed. The basic functional block diagram and signal flow of the AD9850 configured as a clock generator is shown in Figure 16. The DDS circuitry is basically a digital frequency divider function whose incremental resolution is determined by the frequency of the reference clock, divided by the 2N number of bits in the tuning word. The phase accumulator is a variable-modulus counter that increments the number stored in it each time it receives a clock pulse. When the counter overflows it wraps around which makes the phase accumulator’s output contiguous. The frequency tuning word sets the modulus of the counter which effectively determines the size of the increment (∆ Phase) that gets added to the value in the phase accumulator on the next clock pulse. The larger the added increment, the faster the accumulator overflows, which results in a higher output frequency. The AD9850 utilizes an innovative and proprietary algorithm that mathematically converts the 14-bit truncated value of the phase accumulator to the appropriate COS value. This unique algorithm uses a much reduced ROM look-up table and DSP techniques to perform this function, which contributes to the small size and low power dissipation of the AD9850. The relationship of the output frequency, reference clock, and tuning word of the AD9850 is determined by the formula: FOUT = (∆ Phase × CLKIN)/232 where: ∆Phase = value of 32-bit tuning word CLKIN = input reference clock frequency in MHz FOUT = frequency of the output signal in MHz The digital sine wave output of the DDS block drives the internal high speed 10-bit D/A converter which reconstructs the sine –8– REV. 0 AD9850 REF CLOCK DDS CIRCUITRY N PHASE ACCUMULATOR AMPLITUDE/COS CONV. ALGORITHM D/A CONVERTER LP COMPARATOR CLK OUT TUNING WORD SPECIFIES OUTPUT FREQUENCY AS A FRACTION OF REF CLOCK FREQUENCY IN DIGITAL DOMAIN COS (x) Figure 16. Basic DDS Block Diagram and Signal Flow of AD9850 wave in analog form. This DAC has been optimized for dynamic performance and low glitch energy as manifested in the low jitter performance of the AD9850. Since the output of the AD9850 is a sampled signal, its output spectrum follows the Nyquist sampling theorem. Specifically, its output spectrum contains the fundamental plus aliased signals (images) that occur at multiples of the Reference Clock Frequency ± the selected output frequency. A graphical representation of the sampled spectrum, with aliased images, is shown in Figure 17. SIGNAL AMPLITUDE fOUT sin(x)/x ENVELOPE x=(pi)fo/fc fc–fo fc+fo 2fc–fo fc 2fc+fo 3fc–fo The reference clock frequency of the AD9850 has a minimum limitation of 1 MHz. The device has internal circuitry that senses when the minimum clock rate threshold has been exceeded and automatically places itself in the power-down mode. When in this state, if the clock frequency again exceeds the threshold, the device resumes normal operation. This shutdown mode prevents excessive current leakage in the dynamic registers of the device. The D/A converter output and comparator inputs are available as differential signals which can be flexibly configured in any manner desired to achieve the objectives of the end-system. The typical application of the AD9850 is with single-ended output/ input analog signals, a single low-pass filter, and generating the comparator reference midpoint from the differential DAC output, as shown in Figure 13. Programming the AD9850 20MHz 80MHz FUNDAMENTAL 1ST IMAGE 120MHz 2ND IMAGE 180MHz 3RD IMAGE 220MHz 4TH IMAGE 280MHz 5TH IMAGE 100MHz REFERENCE CLOCK FREQUENCY Figure 17. Output Spectrum of a Sampled Signal In this example, the reference clock is 100 MHz and the output frequency is set to 20 MHz. As can be seen, the aliased images are very prominent and of a relatively high energy level as determined by the sin(x)/x roll-off of the quantized D/A converter output. In fact, depending on the fo/Ref Clk relationship, the first aliased image can be on the order of –3 dB below the fundamental. A low-pass filter is generally placed between the output of the D/A converter and the input of the comparator to further suppress the effects of aliased images. Obviously, consideration must be given to the relationship of the selected output frequency and the Reference Clock frequency to avoid unwanted (and unexpected) output anomalies. A good rule-of-thumb for applying the AD9850 as a clock generator is to limit the selected output frequency to <33% of Reference Clock frequency to avoid generating aliased signals that fall within, or close to, the output band of interest (generally dc-selected output frequency). This practice will ease the complexity (and cost) of the external filter requirement for the clock generator application. REV. 0 The AD9850 contains a 40-bit register which is used to program the 32-bit frequency control word, the 5-bit phase modulation word, and the power-down function. This register can be loaded in a parallel or serial mode. In the parallel load mode, the register is loaded via an 8-bit bus; the full 40-bit word requires five iterations of the 8-bit word. The W_CLK and FQ_UD signals are used to address and load the registers. The rising edge of FQ_UD loads the (up to) 40-bit control data word into the device and resets the address pointer to the first register. Subsequent W_CLK rising edges load the 8-bit data on words [7:0] and move the pointer to the next register. After five loads, W_CLK edges are ignored until either a reset or an FQ_UD rising edge resets the address pointer to the first register. In serial load mode, subsequent rising edges of W_CLK shift the 1-bit data on Lead 25 (D7) through the 40 bits of programming information. After 40 bits are shifted through, an FQ_UD pulse is required to update the output frequency (or phase). The function assignments of the data and control words are shown in Table III; the detailed timing sequence for updating the output frequency and/or phase, resetting the device, and powering-up/down, are shown in the timing diagrams of Figures 18–24. Note: There are specific control codes, used for factory test purposes, which render the AD9850 temporarily inoperable. The user must take deliberate precaution to avoid inputting the codes listed in Table II. –9– AD9850 Table II. Factory-Reserved Internal Test Control Codes Loading Format Factory-Reserved Codes Parallel 1) W0 = XXXXXX10 2) W0 = XXXXXX01 Serial 1) W32 = 1; W33 = 0 2) W32 = 0; W33 = 1 3) W32 = 1, W33 = 1 W0* DATA tDS W1 W2 tWH t DH W3 W4 tWL W_CLK tFD tWD tCD FQ_UD t FH t FL REF CLK t CF COS OUT VALID DATA OLD FREQ (PHASE) *OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD AND IS ASYNCHRONOUS WITH THE REFERENCE CLOCK SYMBOL tDS tDH tWH tWL tWD tCD tFH tFL tFD tCF DEFINITION NEW FREQ (PHASE) MIN DATA SETUP TIME 3.5ns DATA HOLD TIME 3.5ns W_CLK HIGH 3.5ns W_CLK HIGH 3.5ns W_CLK DELAY AFTER FQ_UD 7.0ns CLK DELAY AFTER FQ_UD 3.5ns FQ_UD HIGH 7.0ns FQ_UD LOW 7.0ns FQ_UD DELAY AFTER W_CLK 7.0ns OUTPUT LATENCY FROM FQ_UD FREQUENCY CHANGE 18 CLOCK CYCLES PHASE CHANGE 13 CLOCK CYCLES Figure 18. Parallel-Load Frequency/Phase Update Timing Sequence Table III. 8-Bit Parallel-Load Data/Control Word Functional Assignment Word data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] W0 Phase-b4 (MSB) Phase-b3 Phase-b2 Phase-b1 Phase-b0 (LSB) Power-Down Control Control W1 Freq-b31 (MSB) Freq-b30 Freq-b29 Freq-b28 Freq-b27 Freq-b26 Freq-b25 Freq-b24 W2 Freq-b23 Freq-b22 Freq-b21 Freq-b20 Freq-b19 Freq-b18 Freq-b17 Freq-b16 W3 Freq-b15 Freq-b14 Freq-b13 Freq-b12 Freq-b11 Freq-b10 Freq-b9 Freq-b8 W4 Freq-b7 Freq-b6 Freq-b5 Freq-b4 Freq-b3 Freq-b2 Freq-b1 Freq-b0 (LSB) –10– REV. 0 AD9850 REF CLK tRL tRH t RR RESET t RS t OL COS OUT COS (0) SYMBOL tRH tRL tRR tRS tOL DEFINITION MIN SPEC CLK DELAY AFTER RESET RISING EDGE 3.5ns RESET FALLING EDGE AFTER CLK 3.5ns RECOVERY FROM RESET 2 CLK CYCLES MINIMUM RESET WIDTH 5 CLK CYCLES RESET OUTPUT LATENCY 13 CLK CYCLES RESULTS OF RESET: – FREQUENCY/PHASE REGISTER SET TO 0 – ADDRESS POINTER RESET TO W0 – POWER-DOWN BIT RESET TO “0” – DATA INPUT REGISTER UNEFFECTED Figure 19. Master Reset Timing Sequence DATA (W0) XXXXX100 W_CLK FQ_UD REF CLK DAC STROBE INTERNAL CLOCKS DISABLED Figure 20. Parallel-Load Power-Down Sequence/Internal Operation DATA (W0) XXXXX000 W_CLK FQ_UD REF CLK INTERNAL CLOCKS ENABLED DAC STROBE 18 CLOCK CYCLE LATENCY COS OUT VALID OUTPUT Figure 21. Parallel-Load Power-Up Sequence/Internal Operation REV. 0 –11– AD9850 DATA (W0) (PARALLEL) XXXXX011 DATA (SERIAL) REQUIRED TO RESET CONTROL REGISTERS W32 = 0 W33 = 0 W34 = 0 NOTE: AT LEAST 1ST 8 BITS OF 40-BIT SERIAL LOAD WORD IS REQUIRED TO SHIFT IN REQUIRED W32–W34 DATA W_CLK FQ_UD RESET ADDRESS TO (W0) RESET CONTROL WORDS ENABLE SERIAL MODE NOTE: FOR DEVICE START-UP IN SERIAL MODE, HARD-WIRE LEAD 2 AT “0," LEAD 3 AT “1," AND LEAD 4 AT “1” (SEE FIGURE 23). Figure 22. Serial-Load Enable Sequence 2 3 AD9850BRS +V SUPPLY 4 Figure 23. Leads 2–4 Connection for Default Serial-Mode Operation DATA – W0 W1 W2 W3 W39 FQ_UD W_CLK 40 W_CLK CYCLES Figure 24. Serial-Load Frequency/Phase Update Sequence Table IV. 40-Bit Serial-Load Word Function Assignment W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 Freq-b0 (LSB) Freq-b1 Freq-b2 Freq-b3 Freq-b4 Freq-b5 Freq-b6 Freq-b7 Freq-b8 Freq-b9 Freq-b10 Freq-b11 Freq-b12 Freq-b13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 Freq-b14 Freq-b15 Freq-b16 Freq-b17 Freq-b18 Freq-b19 Freq-b20 Freq-b21 Freq-b22 Freq-b23 Freq-b24 Freq-b25 Freq-b26 Freq-b27 –12– W28 W29 W30 W31 W32 W33 W34 W35 W36 W37 W38 W39 Freq-b28 Freq-b29 Freq-b30 Freq-b31 (MSB) Control Control Power-Down Phase-b0 (LSB) Phase-b1 Phase-b2 Phase-b3 Phase-b4 (MSB) REV. 0 AD9850 DATA (7) – W32=0 W33=0 W34=1 W35=X W36=X W37=X W38=X W39=X FQ_UD W_CLK Figure 25. Serial-Load Power-Down Sequence VCC VCC VCC QOUT/ QOUTB IOUT VINP/ VINN DIGITAL IN IOUTB DAC Output Comparator Output Comparator Input Digital Inputs Figure 26. AD9850 I/O Equivalent Circuits PCB LAYOUT INFORMATION Analog Devices, Inc., applications engineering support is available to answer additional questions on grounding and PCB layout. Call 1-800-ANALOGD. The AD9850/CGPCB and AD9850/FSPCB evaluation boards (Figures 27–30) represent typical implementations of the AD9850 and exemplify the use of high frequency/high resolution design and layout practices. The printed circuit board that contains the AD9850 should be a multilayer board that allows dedicated power and ground planes. The power and ground planes should be free of etched traces that cause discontinuities in the planes. It is recommended that the top layer of the multilayer board also contain interspatial ground plane which makes ground available for surface-mount devices. If separate analog and digital system ground planes exist, they should be connected together at the AD9850 for optimum results. Evaluation Boards Avoid running digital lines under the device as these will couple noise onto the die. The power supply lines to the AD9850 should use as large of a track as possible to provide a lowimpedance path and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signal paths. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the circuit board. Use microstrip techniques where possible. Good decoupling is also an important consideration. The analog (AVDD) and digital (DVDD) supplies to the AD9850 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. All analog and digital supplies should be decoupled to AGND and DGND respectively with high quality ceramic capacitors. To achieve best performance from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply is used to drive both the AVDD and DVDD supplies of the AD9850, it is recommended that the system’s AVDD supply be used. REV. 0 Two versions of evaluation boards are available for the AD9850 that facilitate the implementation of the device for benchtop analysis, and serve as a reference for PCB layout. The AD9850/FSPCB is intended for applications where the device will primarily be used as frequency synthesizer. This version facilitates connection of the AD9850’s internal D/A converter output to a 50 Ω spectrum analyzer input; the internal comparator on the AD9850 DUT is not enabled (see Figure 28 for electrical schematic of AD9850/FSPCB). The AD9850/CGPCB is intended for applications using the device in the clock generator mode. It connects the AD9850’s DAC output to the internal comparator input via a single-ended, 42 MHz low-pass, 5-pole Elliptical filter. This model facilitates the access of the AD9850’s comparator output for evaluation of the device as a frequencyand phase-agile clock source (see Figure 29 for electrical schematic of AD9850/CGPCB). Both versions of the AD9850 evaluation boards are designed to interface to the parallel printer port of a PC. The operating software runs under Microsoft Windows and provides a userfriendly and intuitive format for controlling the functionality and observing the performance of the device. The 3.5" floppy provided with the evaluation board contains an executable file which loads and displays the AD9850 function-selection screen. The evaluation board may be operated with +3.3 V or +5 V supplies. The evaluation boards are configured at the factory for an external reference clock input; if the onboard crystal clock source is utilized, remove R2. –13– AD9850 AD9850/XXPCB Evaluation Board Instructions Required hardware/software: IBM compatible computer operating in a Windows™ environment Printer port and Centronics compatible printer cable 3.5" disk drive Mouse AD9850 evaluation board software disk AD9850/XXPCB evaluation board XTAL clock or signal generator—if using a signal generator, dc offset the clock signal to 1/2 the supply voltage and apply at least 3 V p-p signal across the 50 Ω (R2) input resistor. Remove R2 for a high Z clock input impedance. +3.3 V or +5 V supply Setup: Copy the contents of the AD9850 disk onto host computer’s hard drive. Connect printer cable from computer’s printer port to the AD9850/XXPCB evaluation board. Apply power to AD9850/XXPCB evaluation board. Apply external TTL-compatible reference clock to the AD9850/ XXPCB evaluation board or install crystal clock source in socket (remember to remove R2). Locate the WIN9850.EXE file and execute that program. Your monitor should display a “control panel” to allow operation of the AD9850/XXPCB evaluation board. Operation: On the control panel, locate the box called “COMPUTER I/O.” With the mouse (or by tabbing over) click on the selection marked “LPT1” and then click on the “TEST” box. A message will appear indicating whether or not this choice of output ports is valid. Choose alternate ports as necessary to achieve a correct setting. On the control panel, click on “MASTER RESET” button. This will reset the AD9850 to 0 Hz, 0° COS phase; the DAC output should be a dc voltage equal to the full-scale output of the AD9850. Place the cursor in the “OUTPUT FREQUENCY” box and type in the desired output frequency in MHz. Click on the “LOAD” button (or press enter on the keyboard). The BUS MONITOR display on the control panel will display the hexadecimal value of the input 32-bit tuning word. Upon completion of this step, the AD9850/XXPCB evaluation board should be generating the desired sine wave. (Note: VER 1.1 of the AD9850/XXPCB operating software is resolution limited to the nearest Hz.) Changing the phase of the AD9850/XXPCB’s output sine wave is accomplished by clicking on the down arrow in the “OUTPUT PHASE DELAY” box, selecting the desired delay increment, and clicking on the “LOAD” button. Other operational modes available on the control panel are activated by pointing and clicking. The AD9850/FSPCB provides access into and out of the onchip comparator via test point pairs (each pair has an active input and a ground connection). The two active inputs are labeled TP1 and TP2. The unmarked hole next to each labeled test point is a ground connection. The two active outputs are labeled TP5 and TP6. Adjacent to each of those test points are unmarked ground connections. The AD9850/CGPCB provides BNC inputs and outputs associated with the on-chip comparator and the on-board, 5th order, 200 Ω input/output Z, elliptic 45 MHz low-pass filter. Jumpering (soldering a wire between) E1 to E2, E3 to E4, and E5 to E6 will connect the on-board filter and the midpoint switching voltage to the comparator. Users may elect to insert their own filter and threshold voltage by removing the jumpers and inserting a filter between J7 and J6 and providing a threshold voltage at E1. If you choose to utilize the XTAL socket to supply the clock to the AD9850 DUT, you must remove R2 (50 Ω chip resistor). The XTAL oscillator must be either TTL or (preferably) CMOS compatible. Place the cursor in the “CLOCK” box and type in the exact clock frequency in MHz that will be applied to the evaluation board. Click on the “LOAD” button (or press enter on the keyboard). –14– REV. 0 AD9850 C36CRPX J1 1 RRESET 2 9 3 8 4 7 5 6 6 5 7 4 8 3 9 2 8D 8Q 7D 7Q 6D 5Q 4D 4Q 3D 3Q 2D 2Q 1D 1Q C,K 11 1 6Q 5D 10 P O R T J2 U2 74HCT574 12 D0 13 GND D3 1 D3 D3 16 D4 17 14 +V 6 VDD WCLK 7 W_CLK 1 10mA RESET +5V 16 R3 2.2kΩ 17 18 19 12 RSET TP5 COMPARATOR OUTPUTS STROBE 20 VDD 23 +V IOUT 21 +V 11 AVCC R5 25Ω AGND 19 GND AVCC 18 C1 0.01pF DACBP 17 13 QOUT VINP 16 14 QOUTB VINN 15 GND TP8 GND TP2 U3 74HCT574 23 24 RRESET 25 WWCLK 26 FFQUD 27 RRESET 9 8 7 6 28 5 29 4 30 3 8D 8Q 7D 7Q 6D 6Q 5D 5Q 4D 4Q 3D 3Q 2D 2Q WWCLK 1D 1Q CHECK C,K 2 33 GND TP4 12 13 14 15 GND CLKIN RESET R2 50Ω WCLK +5V FQUD 14 CHECK 16 17 18 VCC XTAL Y1 OSC SW41 OUT 8 REMOVE WHEN USING Y1 GND 19 7 OE 11 +5V +V C6 10µF STROBE +5V +V 1 STROBE 35 C7 10µF C2 0.1µF C3 0.1µF C4 0.1µF C5 0.1µF Figure 27. AD9850/FSPCB Electrical Schematic COMPONENT LIST Integrated Circuits U1 U2, U3 Capacitors C2–C5, C8–C10 C6, C7 AD9850BRS (28-Pin SSOP) 74HCT574 H-CMOS Octal Flip-Flop 0.1 µF Ceramic Chip Capacitor 10 µF Ceramic Chip Capacitor Resistors R1 R2, R4 R3 R5 R6, R7 3.9 kΩ Resistor 50 Ω Resistor 2.2 kΩ Resistor 25 Ω Resistor 1 kΩ Resistor Connectors J1 J2, J3 J5, J6 REV. 0 COMPARATOR INPUTS R7 1kΩ J5 34 36 TP3 +V 22 32 GND R6 1kΩ 21 31 +V TP1 TP6 TP7 R4 50Ω RESET 22 RESET IOUTB 20 GND 10 AGND DAC OUT TO 50Ω DGND 24 GND FQUD 8 FQ_UD R1 3.9kΩ FFQUD J6 D7 25 D7 CLKIN 9 CLKIN STROBE 15 U1 D6 26 D6 AD9850 D7 12 13 D5 27 D5 D1 3 D1 GND 5 DGND D6 19 D4 28 D4 D2 2 D2 D0 4 D0 D5 18 H4 #6 MOUNTING HOLES D2 15 H3 #6 +5V D1 14 H2 #6 J4 OE 11 H1 #6 +V BANANA J3 JACKS 36-Pin D Connector Banana Jack BNC Connector –15– C8 0.1µF C9 0.1µF C10 0.1µF AD9850 a. AD9850/FSPCB Top Layer c. AD9850/FSPCB Power Plane b. AD9850/FSPCB Ground Plane d. AD9850/FSPCB Bottom Layer Figure 28. AD9850/FSPCB Evaluation Board Layout –16– REV. 0 AD9850 J2 H1 #6 +V C36CRPX J1 1 BANANA J3 JACKS RRESET 2 9 3 8 4 7 5 6 5 6 7 4 8 3 2 9 10 1 8D 8Q 7D 7Q 6D 6Q 5D 5Q 4D 4Q 3D 3Q 2D 2Q 1D 1Q C,K 11 P O R T U2 74HCT574 14 MOUNTING HOLES GND 12 13 14 15 16 17 18 19 D0 D3 1 D3 D4 28 D4 D1 D2 2 D2 D5 27 D5 D2 D1 3 D1 D3 D0 4 D0 U1 D6 26 D6 AD9850 D4 D5 FQUD 8 FQ_UD IOUT 21 IOUTB 20 GND 10 AGND 10mA RESET 15 +5V BNC 16 18 19 8.2pF 200Ω 22µF 33pF 100kΩ AVCC 18 100Ω C1 0.01pF DACBP 17 13 QOUT VINP 16 14 QOUTB VINN 15 22pF +V 200Ω J6 470pF R3 2.2kΩ 17 100kΩ AGND 19 GND +V 11 AVCC 12 RSET 3.3pF RESET 22 RESET CLKIN 9 CLKIN R1 3.9kΩ STROBE L2 1008CS 680nH 1 2 E5 E6 VDD 23 +V WCLK 7 W_CLK D7 L1 1008CS 910nH 1 2 DGND 24 GND +V 6 VDD D6 200Ω Z 42MHz ELLIPTIC LOW PASS FILTER BNC D7 25 D7 GND 5 DGND 1 FFQUD H4 #6 +5V 12 13 H3 #6 J4 OE 11 H2 #6 BNC E1 STROBE E2 E4 E3 20 21 22 24 RRESET 25 WWCLK 26 FFQUD 27 RRESET 9 8 7 6 28 5 29 4 30 3 31 32 8D 8Q 7D 7Q 6D 6Q 5D 5Q 4D 4Q 3D 3Q 2D 2Q WWCLK 1D 1Q CHECK C,K 2 33 11 CLKIN 12 13 14 15 R2 50Ω RESET WCLK +5V 14 FQUD VCC CHECK 16 REMOVE WHEN USING Y1 GND 18 7 19 +5V +V OE 1 STROBE 35 8 Y1 OUT SW41 XTAL OSC 17 +5V +V 34 36 J5 U3 74HCT574 23 C6 10µF C7 10µF C2 0.1µF C3 0.1µF C4 0.1µF C5 0.1µF C8 0.1µF C9 0.1µF STROBE Figure 29. AD9850/CGPCB Electrical Schematic COMPONENT LIST Integrated Circuits U1 U2, U3 Resistors AD9850BRS (28-Pin SSOP) 74HCT574 H-CMOS Octal Flip-Flop Capacitors C1 C2–C5, C8–C10 C6, C7 C11 C12 C13 C14 C15 REV. 0 470 pF Ceramic Chip Capacitor 0.1 µF Ceramic Chip Capacitor 10 µF Ceramic Chip Capacitor 22 µF Ceramic Chip Capacitor 3.3 pF Ceramic Chip Capacitor 33 pF Ceramic Chip Capacitor 8.2 pF Ceramic Chip Capacitor 22 pF Ceramic Chip Capacitor R1 R2 R3 R4, R5 R6, R7 R8 3.9 kΩ Resistor 50 Ω Resistor 2.2 kΩ Resistor 100 kΩ Resistor 200 Ω Resistor 100 Ω Resistor Connectors J2, J3, J4 J5–J9 Banana Jack BNC Connector Inductors L1 L2 –17– 910 nH Surface Mount 680 nH Surface Mount C10 0.1µF AD9850 a. AD9850/FSPCB Top Layer c. AD9850/FSPCB Power Plane b. AD9850/FSPCB Ground Plane d. AD9850/FSPCB Bottom Layer Figure 30. AD9850/FSPCB Evaluation Board Layout –18– REV. 0 AD9850 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Shrink Small Outline Package (RS-28) 0.407 (10.34) 0.397 (10.08) 15 1 14 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) 28 0.07 (1.79) 0.066 (1.67) 0.078 (1.98) PIN 1 0.068 (1.73) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC REV. 0 0.015 (0.38) 0.010 (0.25) SEATING 0.009 (0.229) PLANE 0.005 (0.127) –19– 8° 0° 0.03 (0.762) 0.022 (0.558) –20– PRINTED IN U.S.A. C2155–18–7/96
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