ARM1176JZF S Technical Reference Manual S+Technical+Reference+Manual
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- ARM1176JZF-S Technical Reference Manual
- Contents
- List of Tables
- List of Figures
- Preface
- Introduction
- 1.1 About the processor
- 1.2 Extensions to ARMv6
- 1.3 TrustZone security extensions
- 1.4 ARM1176JZF-S architecture with Jazelle technology
- 1.5 Components of the processor
- 1.6 Power management
- 1.7 Configurable options
- 1.8 Pipeline stages
- 1.9 Typical pipeline operations
- 1.10 ARM1176JZF-S instruction set summary
- 1.11 Product revisions
- Programmer’s Model
- 2.1 About the programmer’s model
- 2.2 Secure world and Non-secure world operation with TrustZone
- 2.3 Processor operating states
- 2.4 Instruction length
- 2.5 Data types
- 2.6 Memory formats
- 2.7 Addresses in a processor system
- 2.8 Operating modes
- 2.9 Registers
- 2.10 The program status registers
- 2.11 Additional instructions
- 2.12 Exceptions
- 2.12.1 New instructions for exception handling
- 2.12.2 Exception entry and exit summary
- 2.12.3 Entering an ARM exception
- 2.12.4 Leaving an ARM exception
- 2.12.5 Reset
- 2.12.6 Fast interrupt request
- 2.12.7 Interrupt request
- 2.12.8 Low interrupt latency configuration
- 2.12.9 Interrupt latency example
- 2.12.10 Aborts
- 2.12.11 Imprecise Data Abort mask in the CPSR/SPSR
- 2.12.12 Supervisor call instruction
- 2.12.13 Secure Monitor Call (SMC)
- 2.12.14 Undefined instruction
- 2.12.15 Breakpoint instruction (BKPT)
- 2.12.16 Exception vectors
- 2.12.17 Exception priorities
- 2.13 Software considerations
- System Control Coprocessor
- 3.1 About the system control coprocessor
- 3.1.1 System control coprocessor functional groups
- 3.1.2 System control and configuration
- 3.1.3 MMU control and configuration
- 3.1.4 Cache control and configuration
- 3.1.5 TCM control and configuration
- 3.1.6 Cache Master Valid Registers
- 3.1.7 DMA control
- 3.1.8 System performance monitor
- 3.1.9 System validation
- 3.1.10 Use of the system control coprocessor
- 3.2 System control processor registers
- 3.2.1 Register allocation
- 3.2.2 c0, Main ID Register
- 3.2.3 c0, Cache Type Register
- 3.2.4 c0, TCM Status Register
- 3.2.5 c0, TLB Type Register
- 3.2.6 c0, CPUID registers
- 3.2.7 c1, Control Register
- 3.2.8 c1, Auxiliary Control Register
- 3.2.9 c1, Coprocessor Access Control Register
- 3.2.10 c1, Secure Configuration Register
- 3.2.11 c1, Secure Debug Enable Register
- 3.2.12 c1, Non-Secure Access Control Register
- 3.2.13 c2, Translation Table Base Register 0
- 3.2.14 c2, Translation Table Base Register 1
- 3.2.15 c2, Translation Table Base Control Register
- 3.2.16 c3, Domain Access Control Register
- 3.2.17 c5, Data Fault Status Register
- 3.2.18 c5, Instruction Fault Status Register
- 3.2.19 c6, Fault Address Register
- 3.2.20 c6, Watchpoint Fault Address Register
- 3.2.21 c6, Instruction Fault Address Register
- 3.2.22 c7, Cache operations
- 3.2.23 c8, TLB Operations Register
- 3.2.24 c9, Data and instruction cache lockdown registers
- 3.2.25 c9, Data TCM Region Register
- 3.2.26 c9, Instruction TCM Region Register
- 3.2.27 c9, Data TCM Non-secure Control Access Register
- 3.2.28 c9, Instruction TCM Non-secure Control Access Register
- 3.2.29 c9, TCM Selection Register
- 3.2.30 c9, Cache Behavior Override Register
- 3.2.31 c10, TLB Lockdown Register
- 3.2.32 c10, Memory region remap registers
- 3.2.33 c11, DMA identification and status registers
- 3.2.34 c11, DMA User Accessibility Register
- 3.2.35 c11, DMA Channel Number Register
- 3.2.36 c11, DMA enable registers
- 3.2.37 c11, DMA Control Register
- 3.2.38 c11, DMA Internal Start Address Register
- 3.2.39 c11, DMA External Start Address Register
- 3.2.40 c11, DMA Internal End Address Register
- 3.2.41 c11, DMA Channel Status Register
- 3.2.42 c11, DMA Context ID Register
- 3.2.43 c12, Secure or Non-secure Vector Base Address Register
- 3.2.44 c12, Monitor Vector Base Address Register
- 3.2.45 c12, Interrupt Status Register
- 3.2.46 c13, FCSE PID Register
- 3.2.47 c13, Context ID Register
- 3.2.48 c13, Thread and process ID registers
- 3.2.49 c15, Peripheral Port Memory Remap Register
- 3.2.50 c15, Secure User and Non-secure Access Validation Control Register
- 3.2.51 c15, Performance Monitor Control Register
- 3.2.52 c15, Cycle Counter Register
- 3.2.53 c15, Count Register 0
- 3.2.54 c15, Count Register 1
- 3.2.55 c15, System Validation Counter Register
- 3.2.56 c15, System Validation Operations Register
- 3.2.57 c15, System Validation Cache Size Mask Register
- 3.2.58 c15, Instruction Cache Master Valid Register
- 3.2.59 c15, Data Cache Master Valid Register
- 3.2.60 c15, TLB lockdown access registers
- 3.1 About the system control coprocessor
- Unaligned and Mixed-endian Data Access Support
- 4.1 About unaligned and mixed-endian support
- 4.2 Unaligned access support
- 4.3 Endian support
- 4.3.1 Load unsigned byte, endian independent
- 4.3.2 Load signed byte, endian independent
- 4.3.3 Store byte, endian independent
- 4.3.4 Load unsigned halfword, little-endian
- 4.3.5 Load unsigned halfword, big-endian
- 4.3.6 Load signed halfword, little-endian
- 4.3.7 Load signed halfword, big-endian
- 4.3.8 Store halfword, little-endian
- 4.3.9 Store halfword, big-endian
- 4.3.10 Load word, little-endian
- 4.3.11 Load word, big-endian
- 4.3.12 Store word, little-endian
- 4.3.13 Store word, big-endian
- 4.3.14 Load double, load multiple, load coprocessor (little-endian, E = 0)
- 4.3.15 Load double, load multiple, load coprocessor (big-endian, E=1)
- 4.3.16 Store double, store multiple, store coprocessor (little-endian, E=0)
- 4.3.17 Store double, store multiple, store coprocessor (big-endian, E=1)
- 4.4 Operation of unaligned accesses
- 4.5 Mixed-endian access support
- 4.6 Instructions to reverse bytes in a general-purpose register
- 4.7 Instructions to change the CPSR E bit
- Program Flow Prediction
- Memory Management Unit
- 6.1 About the MMU
- 6.2 TLB organization
- 6.3 Memory access sequence
- 6.4 Enabling and disabling the MMU
- 6.5 Memory access control
- 6.6 Memory region attributes
- 6.7 Memory attributes and types
- 6.8 MMU aborts
- 6.9 MMU fault checking
- 6.10 Fault status and address
- 6.11 Hardware page table translation
- 6.12 MMU descriptors
- 6.13 MMU software-accessible registers
- Level One Memory System
- Level Two Interface
- 8.1 About the level two interface
- 8.2 Synchronization primitives
- 8.3 AXI control signals in the processor
- 8.4 Instruction Fetch Interface transfers
- 8.5 Data Read/Write Interface transfers
- 8.5.1 Linefills
- 8.5.2 Noncacheable LDRB
- 8.5.3 Noncacheable LDRH
- 8.5.4 Noncacheable LDR or LDM1
- 8.5.5 Noncacheable LDRD or LDM2
- 8.5.6 Noncacheable LDM3
- 8.5.7 Noncacheable LDM4
- 8.5.8 Noncacheable LDM5
- 8.5.9 Noncacheable LDM6
- 8.5.10 Noncacheable LDM7
- 8.5.11 Noncacheable LDM8
- 8.5.12 Noncacheable LDM9
- 8.5.13 Noncacheable LDM10
- 8.5.14 Noncacheable LDM11
- 8.5.15 Noncacheable LDM12
- 8.5.16 Noncacheable LDM13
- 8.5.17 Noncacheable LDM14
- 8.5.18 Noncacheable LDM15
- 8.5.19 Noncacheable LDM16
- 8.5.20 Half-line Write-Back
- 8.5.21 Full-line Write-Back
- 8.5.22 Cacheable Write-Through or Noncacheable STRB
- 8.5.23 Cacheable Write-Through or Noncacheable STRH
- 8.5.24 Cacheable Write-Through or Noncacheable STR or STM1
- 8.5.25 Cacheable Write-Through or Noncacheable STRD or STM2
- 8.5.26 Cacheable Write-Through or Noncacheable STM3
- 8.5.27 Cacheable Write-Through or Noncacheable STM4
- 8.5.28 Cacheable Write-Through or Noncacheable STM5
- 8.5.29 Cacheable Write-Through or Noncacheable STM6
- 8.5.30 Cacheable Write-Through or Noncacheable STM7
- 8.5.31 Cacheable Write-Through or Noncacheable STM8
- 8.5.32 Cacheable Write-Through or Noncacheable STM9
- 8.5.33 Cacheable Write-Through or Noncacheable STM10
- 8.5.34 Cacheable Write-Through or Noncacheable STM11
- 8.5.35 Cacheable Write-Through or Noncacheable STM12
- 8.5.36 Cacheable Write-Through or Noncacheable STM13
- 8.5.37 Cacheable Write-Through or Noncacheable STM14
- 8.5.38 Cacheable Write-Through or Noncacheable STM15
- 8.5.39 Cacheable Write-Through or Noncacheable STM16
- 8.6 Peripheral Interface transfers
- 8.7 Endianness
- 8.8 Locked access
- Clocking and Resets
- Power Control
- Coprocessor Interface
- Vectored Interrupt Controller Port
- Debug
- 13.1 Debug systems
- 13.2 About the debug unit
- 13.3 Debug registers
- 13.3.1 Accessing debug registers
- 13.3.2 CP14 c0, Debug ID Register (DIDR)
- 13.3.3 CP14 c1, Debug Status and Control Register (DSCR)
- 13.3.4 CP14 c5, Data Transfer Registers (DTR)
- 13.3.5 CP14 c6, Watchpoint Fault Address Register (WFAR)
- 13.3.6 CP14 c7, Vector Catch Register (VCR)
- 13.3.7 CP14 c64-c69, Breakpoint Value Registers (BVR)
- 13.3.8 CP14 c80-c85, Breakpoint Control Registers (BCR)
- 13.3.9 CP14 c96-c97, Watchpoint Value Registers (WVR)
- 13.3.10 CP14 c112-c113, Watchpoint Control Registers (WCR)
- 13.3.11 CP14 c10, Debug State Cache Control Register
- 13.3.12 CP14 c11, Debug State MMU Control Register
- 13.4 CP14 registers reset
- 13.5 CP14 debug instructions
- 13.6 External debug interface
- 13.7 Changing the debug enable signals
- 13.8 Debug events
- 13.9 Debug exception
- 13.10 Debug state
- 13.11 Debug communications channel
- 13.12 Debugging in a cached system
- 13.13 Debugging in a system with TLBs
- 13.14 Monitor debug-mode debugging
- 13.15 Halting debug-mode debugging
- 13.16 External signals
- Debug Test Access Port
- 14.1 Debug Test Access Port and Debug state
- 14.2 Synchronizing RealView ICE
- 14.3 Entering Debug state
- 14.4 Exiting Debug state
- 14.5 The DBGTAP port and debug registers
- 14.6 Debug registers
- 14.7 Using the Debug Test Access Port
- 14.7.1 Entering and leaving Debug state
- 14.7.2 Executing instructions in Debug state
- 14.7.3 Using the ITRsel IR instruction
- 14.7.4 Transferring data between the host and the core
- 14.7.5 Using the debug communications channel
- 14.7.6 Target to host debug communications channel sequence
- 14.7.7 Host to target debug communications channel
- 14.7.8 Transferring data in Debug state
- 14.7.9 Example sequences
- 14.8 Debug sequences
- 14.8.1 Debug macros
- 14.8.2 General setup
- 14.8.3 Forcing the processor to halt
- 14.8.4 Entering Debug state
- 14.8.5 Leaving Debug state
- 14.8.6 Reading a current mode ARM register in the range R0-R14
- 14.8.7 Writing a current mode ARM register in the range R0-R14
- 14.8.8 Reading the CPSR/SPSR
- 14.8.9 Writing the CPSR/SPSR
- 14.8.10 Reading the PC
- 14.8.11 Writing the PC
- 14.8.12 General notes about reading and writing memory
- 14.8.13 Reading memory as words
- 14.8.14 Writing memory as words
- 14.8.15 Reading memory as halfwords or bytes
- 14.8.16 Writing memory as halfwords/bytes
- 14.8.17 Coprocessor register reads and writes
- 14.8.18 Reading coprocessor registers
- 14.8.19 Writing coprocessor registers
- 14.9 Programming debug events
- 14.10 Monitor debug-mode debugging
- Trace Interface Port
- Cycle Timings and Interlock Behavior
- 16.1 About cycle timings and interlock behavior
- 16.2 Register interlock examples
- 16.3 Data processing instructions
- 16.4 QADD, QDADD, QSUB, and QDSUB instructions
- 16.5 ARMv6 media data-processing
- 16.6 ARMv6 Sum of Absolute Differences (SAD)
- 16.7 Multiplies
- 16.8 Branches
- 16.9 Processor state updating instructions
- 16.10 Single load and store instructions
- 16.11 Load and Store Double instructions
- 16.12 Load and Store Multiple Instructions
- 16.13 RFE and SRS instructions
- 16.14 Synchronization instructions
- 16.15 Coprocessor instructions
- 16.16 SVC, SMC, BKPT, Undefined, and Prefetch Aborted instructions
- 16.17 No operation
- 16.18 Thumb instructions
- AC Characteristics
- Introduction to the VFP coprocessor
- 18.1 About the VFP11 coprocessor
- 18.2 Applications
- 18.3 Coprocessor interface
- 18.4 VFP11 coprocessor pipelines
- 18.5 Modes of operation
- 18.6 Short vector instructions
- 18.7 Parallel execution of instructions
- 18.8 VFP11 treatment of branch instructions
- 18.9 Writing optimal VFP11 code
- 18.10 VFP11 revision information
- The VFP Register File
- VFP Programmer’s Model
- VFP Instruction Execution
- 21.1 About instruction execution
- 21.2 Serializing instructions
- 21.3 Interrupting the VFP11 coprocessor
- 21.4 Forwarding
- 21.5 Hazards
- 21.6 Operation of the scoreboards
- 21.7 Data hazards in full-compliance mode
- 21.8 Data hazards in RunFast mode
- 21.9 Resource hazards
- 21.10 Parallel execution
- 21.11 Execution timing
- VFP Exception Handling
- 22.1 About exception processing
- 22.2 Bounced instructions
- 22.3 Support code
- 22.4 Exception processing
- 22.5 Input Subnormal exception
- 22.6 Invalid Operation exception
- 22.7 Division by Zero exception
- 22.8 Overflow exception
- 22.9 Underflow exception
- 22.10 Inexact exception
- 22.11 Input exceptions
- 22.12 Arithmetic exceptions
- Signal Descriptions
- Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences
- B.1 About the differences between the ARM1136JF-S and ARM1176JZF-S processors
- B.2 Summary of differences
- B.2.1 TrustZone
- B.2.2 ARMv6k extensions support
- B.2.3 Power management
- B.2.4 SmartCache
- B.2.5 CPU ID
- B.2.6 Block transfer operations
- B.2.7 Tightly-Coupled Memories
- B.2.8 Fault Address Register
- B.2.9 Fault Status Register
- B.2.10 Prefetch Unit
- B.2.11 System control coprocessor operations
- B.2.12 DMA
- B.2.13 Debug
- B.2.14 Level two interface
- B.2.15 Memory BIST
- Revisions
- Glossary