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ARM1176JZF-S

™

Revision: r0p7

Technical Reference Manual

ARM1176JZF-S
Technical Reference Manual
Copyright © 2004-2009 ARM Limited. All rights reserved.
Release Information
The following changes have been made to this book.
Change history
Date

Issue

Confidentiality

Change

19 July 2004

Non-Confidential

First release.

18 April 2005

Non-Confidential

Minor corrections and enhancements.

29 June 2005

Non-Confidential

r0p1 changes, addition of CPUCLAMP
Figure 10-1 updated.
Section 10.4.3 updated.
Table 23-1 updated.
Minor corrections and enhancements.

22 March 2006

Non-Confidential

Update for r0p2. Minor corrections and enhancements.

19 July 2006

Non-Confidential

Patch update for r0p4.

19 April 2007

Non-Confidential

Update for r0p6 release. Minor corrections and enhancements.

15 February 2008

Non-Confidential

Update for r0p7 release. Minor corrections and enhancements.

27 November 2009

Non-Confidential

Update for r0p7 maintenance release. Minor corrections and enhancements.

Proprietary Notice
Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® Limited in the EU and other
countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may
be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the
product and its use contained in this document are given by ARM in good faith. However, all warranties implied or
expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any
loss or damage arising from the use of any information in this document, or any error or omission in such information,
or any incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Figure 14-1 on page 14-2 reprinted with permission from IEEE Std. 1149.1-2001, IEEE Standard Test Access Port and
Boundary-Scan Architecture by IEEE Std. The IEEE disclaims any responsibility or liability resulting from the
placement and use in the described manner.
Some material in this document is based on IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std
754-1985. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described
manner
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license
restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this
document to.
Unrestricted Access is an ARM internal classification.

ARM DDI 0301H
ID012310

Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com

ARM DDI 0301H
ID012310

iii

Contents
ARM1176JZF-S Technical Reference Manual

Preface
About this book ........................................................................................................ xxii
Feedback ................................................................................................................ xxvi

Chapter 1

Introduction
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11

Chapter 2

Programmer’s Model
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11

ARM DDI 0301H
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About the processor ................................................................................................. 1-2
Extensions to ARMv6 .............................................................................................. 1-3
TrustZone security extensions ................................................................................. 1-4
ARM1176JZF-S architecture with Jazelle technology ............................................. 1-6
Components of the processor .................................................................................. 1-8
Power management ............................................................................................... 1-23
Configurable options .............................................................................................. 1-25
Pipeline stages ...................................................................................................... 1-26
Typical pipeline operations .................................................................................... 1-28
ARM1176JZF-S instruction set summary .............................................................. 1-32
Product revisions ................................................................................................... 1-47

About the programmer’s model ............................................................................... 2-2
Secure world and Non-secure world operation with TrustZone ............................... 2-3
Processor operating states .................................................................................... 2-12
Instruction length ................................................................................................... 2-13
Data types .............................................................................................................. 2-14
Memory formats ..................................................................................................... 2-15
Addresses in a processor system .......................................................................... 2-16
Operating modes ................................................................................................... 2-17
Registers ................................................................................................................ 2-18
The program status registers ................................................................................. 2-24
Additional instructions ............................................................................................ 2-30
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access

Contents

2.12
2.13

Chapter 3

System Control Coprocessor
3.1
3.2

Chapter 4

About the level two interface .................................................................................... 8-2
Synchronization primitives ....................................................................................... 8-6
AXI control signals in the processor ........................................................................ 8-8
Instruction Fetch Interface transfers ...................................................................... 8-14
Data Read/Write Interface transfers ...................................................................... 8-15
Peripheral Interface transfers ................................................................................ 8-37
Endianness ............................................................................................................ 8-38
Locked access ....................................................................................................... 8-39

Clocking and Resets
9.1

ARM DDI 0301H
ID012310

About the level one memory system ........................................................................ 7-2
Cache organization .................................................................................................. 7-3
Tightly-coupled memory .......................................................................................... 7-7
DMA ....................................................................................................................... 7-10
TCM and cache interactions .................................................................................. 7-12
Write buffer ............................................................................................................ 7-16

Level Two Interface
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8

Chapter 9

About the MMU ........................................................................................................ 6-2
TLB organization ...................................................................................................... 6-4
Memory access sequence ....................................................................................... 6-7
Enabling and disabling the MMU ............................................................................. 6-9
Memory access control .......................................................................................... 6-11
Memory region attributes ....................................................................................... 6-14
Memory attributes and types ................................................................................. 6-20
MMU aborts ........................................................................................................... 6-27
MMU fault checking ............................................................................................... 6-29
Fault status and address ....................................................................................... 6-34
Hardware page table translation ............................................................................ 6-36
MMU descriptors .................................................................................................... 6-43
MMU software-accessible registers ....................................................................... 6-53

Level One Memory System
7.1
7.2
7.3
7.4
7.5
7.6

Chapter 8

About program flow prediction ................................................................................. 5-2
Branch prediction ..................................................................................................... 5-4
Return stack ............................................................................................................. 5-7
Memory Barriers ...................................................................................................... 5-8
ARM1176JZF-S IMB implementation .................................................................... 5-10

Memory Management Unit
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13

Chapter 7

About unaligned and mixed-endian support ............................................................ 4-2
Unaligned access support ....................................................................................... 4-3
Endian support ......................................................................................................... 4-6
Operation of unaligned accesses .......................................................................... 4-13
Mixed-endian access support ................................................................................ 4-17
Instructions to reverse bytes in a general-purpose register ................................... 4-20
Instructions to change the CPSR E bit .................................................................. 4-21

Program Flow Prediction
5.1
5.2
5.3
5.4
5.5

Chapter 6

About the system control coprocessor ..................................................................... 3-2
System control processor registers ....................................................................... 3-13

Unaligned and Mixed-endian Data Access Support
4.1
4.2
4.3
4.4
4.5
4.6
4.7

Chapter 5

Exceptions ............................................................................................................. 2-36
Software considerations ........................................................................................ 2-59

About clocking and resets ........................................................................................ 9-2

Contents

9.2
9.3
9.4

Chapter 10

Clocking and resets with no IEM ............................................................................. 9-3
Clocking and resets with IEM .................................................................................. 9-5
Reset modes .......................................................................................................... 9-10

Power Control
10.1
10.2
10.3
10.4

Chapter 11

About power control ...............................................................................................
Power management ...............................................................................................
VFP shutdown .......................................................................................................
Intelligent Energy Management .............................................................................

Coprocessor Interface
11.1
11.2
11.3
11.4
11.5
11.6
11.7

Chapter 12

About the coprocessor interface ............................................................................ 11-2
Coprocessor pipeline ............................................................................................. 11-3
Token queue management .................................................................................... 11-9
Token queues ...................................................................................................... 11-12
Data transfer ........................................................................................................ 11-15
Operations ........................................................................................................... 11-19
Multiple coprocessors .......................................................................................... 11-22

Vectored Interrupt Controller Port
12.1
12.2
12.3
12.4

Chapter 13

Debug systems ...................................................................................................... 13-2
About the debug unit .............................................................................................. 13-3
Debug registers ..................................................................................................... 13-5
CP14 registers reset ............................................................................................ 13-25
CP14 debug instructions ...................................................................................... 13-26
External debug interface ...................................................................................... 13-28
Changing the debug enable signals .................................................................... 13-31
Debug events ....................................................................................................... 13-32
Debug exception .................................................................................................. 13-35
Debug state ......................................................................................................... 13-37
Debug communications channel .......................................................................... 13-42
Debugging in a cached system ............................................................................ 13-43
Debugging in a system with TLBs ....................................................................... 13-44
Monitor debug-mode debugging .......................................................................... 13-45
Halting debug-mode debugging ........................................................................... 13-50
External signals ................................................................................................... 13-52

Debug Test Access Port and Debug state ............................................................. 14-2
Synchronizing RealView ICE ................................................................................. 14-3
Entering Debug state ............................................................................................. 14-4
Exiting Debug state ................................................................................................ 14-5
The DBGTAP port and debug registers ................................................................. 14-6
Debug registers ..................................................................................................... 14-8
Using the Debug Test Access Port ...................................................................... 14-21
Debug sequences ................................................................................................ 14-29
Programming debug events ................................................................................. 14-40
Monitor debug-mode debugging .......................................................................... 14-42

Trace Interface Port
15.1

ARM DDI 0301H
ID012310

12-2
12-3
12-5
12-7

Debug Test Access Port
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10

Chapter 15

About the PL192 Vectored Interrupt Controller ......................................................
About the processor VIC port ................................................................................
Timing of the VIC port ............................................................................................
Interrupt entry flowchart .........................................................................................

Debug
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
13.10
13.11
13.12
13.13
13.14
13.15
13.16

Chapter 14

10-2
10-3
10-6
10-7

About the ETM interface ........................................................................................ 15-2

Contents

Chapter 16

Cycle Timings and Interlock Behavior
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
16.10
16.11
16.12
16.13
16.14
16.15
16.16
16.17
16.18

Chapter 17

AC Characteristics
17.1
17.2

Chapter 18

About the programmer’s model ............................................................................. 20-2
Compliance with the IEEE 754 standard ............................................................... 20-3
ARMv5TE coprocessor extensions ........................................................................ 20-8
VFP11 system registers ....................................................................................... 20-12

VFP Instruction Execution
21.1
21.2
21.3
21.4
21.5
21.6
21.7

ARM DDI 0301H
ID012310

About the register file ............................................................................................. 19-2
Register file internal formats .................................................................................. 19-3
Decoding the register file ....................................................................................... 19-5
Loading operands from ARM11 registers .............................................................. 19-6
Maintaining consistency in register precision ........................................................ 19-8
Data transfer between memory and VFP11 registers ............................................ 19-9
Access to register banks in CDP operations ....................................................... 19-10

VFP Programmer’s Model
20.1
20.2
20.3
20.4

Chapter 21

About the VFP11 coprocessor ............................................................................... 18-2
Applications ........................................................................................................... 18-3
Coprocessor interface ............................................................................................ 18-4
VFP11 coprocessor pipelines ................................................................................ 18-5
Modes of operation .............................................................................................. 18-11
Short vector instructions ...................................................................................... 18-13
Parallel execution of instructions ......................................................................... 18-14
VFP11 treatment of branch instructions .............................................................. 18-15
Writing optimal VFP11 code ................................................................................ 18-16
VFP11 revision information .................................................................................. 18-17

The VFP Register File
19.1
19.2
19.3
19.4
19.5
19.6
19.7

Chapter 20

Processor timing diagrams .................................................................................... 17-2
Processor timing parameters ................................................................................. 17-3

Introduction to the VFP coprocessor
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
18.9
18.10

Chapter 19

About cycle timings and interlock behavior ............................................................ 16-2
Register interlock examples ................................................................................... 16-6
Data processing instructions .................................................................................. 16-7
QADD, QDADD, QSUB, and QDSUB instructions ................................................ 16-9
ARMv6 media data-processing ............................................................................ 16-10
ARMv6 Sum of Absolute Differences (SAD) ........................................................ 16-11
Multiplies .............................................................................................................. 16-12
Branches .............................................................................................................. 16-14
Processor state updating instructions .................................................................. 16-15
Single load and store instructions ........................................................................ 16-16
Load and Store Double instructions ..................................................................... 16-19
Load and Store Multiple Instructions ................................................................... 16-21
RFE and SRS instructions ................................................................................... 16-23
Synchronization instructions ................................................................................ 16-24
Coprocessor instructions ..................................................................................... 16-25
SVC, SMC, BKPT, Undefined, and Prefetch Aborted instructions ...................... 16-26
No operation ........................................................................................................ 16-27
Thumb instructions .............................................................................................. 16-28

About instruction execution .................................................................................... 21-2
Serializing instructions ........................................................................................... 21-3
Interrupting the VFP11 coprocessor ...................................................................... 21-4
Forwarding ............................................................................................................. 21-5
Hazards ................................................................................................................. 21-6
Operation of the scoreboards ................................................................................ 21-7
Data hazards in full-compliance mode ................................................................. 21-13
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access

vii

Contents

21.8
21.9
21.10
21.11

Chapter 22

Global signals .......................................................................................................... A-2
Static configuration signals ...................................................................................... A-4
TrustZone internal signals ....................................................................................... A-5
Interrupt signals, including VIC interface ................................................................. A-6
AXI interface signals ................................................................................................ A-7
Coprocessor interface signals ............................................................................... A-12
Debug interface signals, including JTAG ............................................................... A-14
ETM interface signals ............................................................................................ A-15
Test signals ............................................................................................................ A-16

Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences
B.1
B.2

Appendix C

About exception processing ................................................................................... 22-2
Bounced instructions ............................................................................................. 22-3
Support code ......................................................................................................... 22-5
Exception processing ............................................................................................. 22-8
Input Subnormal exception .................................................................................. 22-12
Invalid Operation exception ................................................................................. 22-13
Division by Zero exception ................................................................................... 22-15
Overflow exception .............................................................................................. 22-16
Underflow exception ............................................................................................ 22-17
Inexact exception ................................................................................................. 22-18
Input exceptions ................................................................................................... 22-19
Arithmetic exceptions ........................................................................................... 22-20

Signal Descriptions
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9

Appendix B

21-16
21-17
21-20
21-22

VFP Exception Handling
22.1
22.2
22.3
22.4
22.5
22.6
22.7
22.8
22.9
22.10
22.11
22.12

Appendix A

Data hazards in RunFast mode ...........................................................................
Resource hazards ................................................................................................
Parallel execution ................................................................................................
Execution timing ..................................................................................................

About the differences between the ARM1136JF-S and ARM1176JZF-S processors ....
B-2
Summary of differences ........................................................................................... B-3

Revisions
Glossary

ARM DDI 0301H
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viii

List of Tables
ARM1176JZF-S Technical Reference Manual

Table 1-1
Table 1-2
Table 1-3
Table 1-4
Table 1-5
Table 1-6
Table 1-7
Table 1-8
Table 1-9
Table 1-10
Table 1-11
Table 1-12
Table 1-13
Table 1-14
Table 1-15
Table 1-16
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 2-9
Table 3-1
Table 3-2
Table 3-3
Table 3-4
ARM DDI 0301H
ID012310

Change history ................................................................................................................................ ii
TCM configurations ................................................................................................................... 1-13
Double-precision VFP operations ............................................................................................. 1-20
Flush-to-zero mode ................................................................................................................... 1-20
Configurable options ................................................................................................................. 1-25
ARM1176JZF-S processor default configurations .................................................................... 1-25
Key to instruction set tables ...................................................................................................... 1-32
ARM instruction set summary ................................................................................................... 1-33
Addressing mode 2 ................................................................................................................... 1-40
Addressing mode 2P, post-indexed only .................................................................................. 1-41
Addressing mode 3 ................................................................................................................... 1-42
Addressing mode 4 ................................................................................................................... 1-42
Addressing mode 5 ................................................................................................................... 1-42
Operand2 .................................................................................................................................. 1-43
Fields ........................................................................................................................................ 1-43
Condition codes ........................................................................................................................ 1-43
Thumb instruction set summary ................................................................................................ 1-44
Write access behavior for system control processor registers .................................................... 2-9
Secure Monitor bus signals ....................................................................................................... 2-11
Address types in the processor system .................................................................................... 2-16
Mode structure .......................................................................................................................... 2-17
Register mode identifiers .......................................................................................................... 2-19
GE[3:0] settings ........................................................................................................................ 2-26
PSR mode bit values ................................................................................................................ 2-28
Exception entry and exit ............................................................................................................ 2-37
Exception priorities .................................................................................................................... 2-57
System control coprocessor register functions ........................................................................... 3-3
Summary of CP15 registers and operations ............................................................................. 3-14
Summary of CP15 MCRR operations ....................................................................................... 3-19
Main ID Register bit functions ................................................................................................... 3-20
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access

List of Tables

Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 3-9
Table 3-10
Table 3-11
Table 3-12
Table 3-13
Table 3-14
Table 3-15
Table 3-16
Table 3-17
Table 3-18
Table 3-19
Table 3-20
Table 3-21
Table 3-22
Table 3-23
Table 3-24
Table 3-25
Table 3-26
Table 3-27
Table 3-28
Table 3-29
Table 3-30
Table 3-31
Table 3-32
Table 3-33
Table 3-34
Table 3-35
Table 3-36
Table 3-37
Table 3-38
Table 3-39
Table 3-40
Table 3-41
Table 3-42
Table 3-43
Table 3-44
Table 3-45
Table 3-46
Table 3-47
Table 3-48
Table 3-49
Table 3-50
Table 3-51
Table 3-52
Table 3-53
Table 3-54
Table 3-55
Table 3-56
Table 3-57
Table 3-58
Table 3-59
Table 3-60
Table 3-61
Table 3-62
Table 3-63
Table 3-64

ARM DDI 0301H
ID012310

Results of access to the Main ID Register ................................................................................
Cache Type Register bit functions ............................................................................................
Results of access to the Cache Type Register .........................................................................
Example Cache Type Register format ......................................................................................
TCM Status Register bit functions ............................................................................................
TLB Type Register bit functions ................................................................................................
Results of access to the TLB Type Register .............................................................................
Processor Feature Register 0 bit functions ...............................................................................
Results of access to the Processor Feature Register 0 ............................................................
Processor Feature Register 1 bit functions ...............................................................................
Results of access to the Processor Feature Register 1 ............................................................
Debug Feature Register 0 bit functions ....................................................................................
Results of access to the Debug Feature Register 0 .................................................................
Auxiliary Feature Register 0 bit functions .................................................................................
Results of access to the Auxiliary Feature Register 0 ..............................................................
Memory Model Feature Register 0 bit functions .......................................................................
Results of access to the Memory Model Feature Register 0 ....................................................
Memory Model Feature Register 1 bit functions .......................................................................
Results of access to the Memory Model Feature Register 1 ....................................................
Memory Model Feature Register 2 bit functions .......................................................................
Results of access to the Memory Model Feature Register 2 ....................................................
Memory Model Feature Register 3 bit functions .......................................................................
Results of access to the Memory Model Feature Register 3 ....................................................
Instruction Set Attributes Register 0 bit functions .....................................................................
Results of access to the Instruction Set Attributes Register 0 ..................................................
Instruction Set Attributes Register 1 bit functions .....................................................................
Results of access to the Instruction Set Attributes Register 1 ..................................................
Instruction Set Attributes Register 2 bit functions .....................................................................
Results of access to the Instruction Set Attributes Register 2 ..................................................
Instruction Set Attributes Register 3 bit functions .....................................................................
Results of access to the Instruction Set Attributes Register 3 ..................................................
Instruction Set Attributes Register 4 bit functions .....................................................................
Results of access to the Instruction Set Attributes Register 4 ..................................................
Results of access to the Instruction Set Attributes Register 5 ..................................................
Control Register bit functions ....................................................................................................
Results of access to the Control Register .................................................................................
Resultant B bit, U bit, and EE bit values ...................................................................................
Auxiliary Control Register bit functions .....................................................................................
Results of access to the Auxiliary Control Register ..................................................................
Coprocessor Access Control Register bit functions ..................................................................
Results of access to the Coprocessor Access Control Register ...............................................
Secure Configuration Register bit functions ..............................................................................
Operation of the FW and FIQ bits .............................................................................................
Operation of the AW and EA bits ..............................................................................................
Secure Debug Enable Register bit functions ............................................................................
Results of access to the Coprocessor Access Control Register ...............................................
Non-Secure Access Control Register bit functions ...................................................................
Results of access to the Auxiliary Control Register ..................................................................
Translation Table Base Register 0 bit functions .......................................................................
Results of access to the Translation Table Base Register 0 ....................................................
Translation Table Base Register 1 bit functions .......................................................................
Results of access to the Translation Table Base Register 1 ....................................................
Translation Table Base Control Register bit functions ..............................................................
Results of access to the Translation Table Base Control Register ...........................................
Domain Access Control Register bit functions ..........................................................................
Results of access to the Domain Access Control Register .......................................................
Data Fault Status Register bit functions ....................................................................................
Results of access to the Data Fault Status Register .................................................................
Instruction Fault Status Register bit functions ...........................................................................
Results of access to the Instruction Fault Status Register ........................................................

3-20
3-21
3-23
3-23
3-24
3-25
3-25
3-26
3-27
3-28
3-28
3-29
3-29
3-30
3-30
3-31
3-31
3-32
3-33
3-34
3-35
3-35
3-36
3-36
3-37
3-38
3-38
3-39
3-40
3-41
3-41
3-42
3-43
3-43
3-45
3-47
3-48
3-49
3-50
3-51
3-51
3-52
3-53
3-53
3-54
3-55
3-56
3-57
3-58
3-58
3-59
3-60
3-61
3-62
3-63
3-63
3-64
3-66
3-67
3-67

List of Tables

Table 3-65
Table 3-66
Table 3-67
Table 3-68
Table 3-69
Table 3-70
Table 3-71
Table 3-72
Table 3-73
Table 3-74
Table 3-75
Table 3-76
Table 3-77
Table 3-78
Table 3-79
Table 3-80
Table 3-81
Table 3-82
Table 3-83
Table 3-84
Table 3-85
Table 3-86
Table 3-87
Table 3-88
Table 3-89
Table 3-90
Table 3-91
Table 3-92
Table 3-93
Table 3-94
Table 3-95
Table 3-96
Table 3-97
Table 3-98
Table 3-99
Table 3-100
Table 3-101
Table 3-102
Table 3-103
Table 3-104
Table 3-105
Table 3-106
Table 3-107
Table 3-108
Table 3-109
Table 3-110
Table 3-111
Table 3-112
Table 3-113
Table 3-114
Table 3-115
Table 3-116
Table 3-117
Table 3-118
Table 3-119
Table 3-120
Table 3-121
Table 3-122
Table 3-123
Table 3-124

ARM DDI 0301H
ID012310

Results of access to the Fault Address Register ...................................................................... 3-68
Results of access to the Instruction Fault Address Register ..................................................... 3-69
Functional bits of c7 for Set and Index ...................................................................................... 3-72
Cache size and S parameter dependency ................................................................................ 3-72
Functional bits of c7 for MVA .................................................................................................... 3-73
Functional bits of c7 for VA format ............................................................................................ 3-74
Cache operations for entire cache ............................................................................................ 3-74
Cache operations for single lines .............................................................................................. 3-75
Cache operations for address ranges ....................................................................................... 3-76
Cache Dirty Status Register bit functions ................................................................................. 3-78
Cache operations flush functions .............................................................................................. 3-79
Flush Branch Target Entry using MVA bit functions ................................................................. 3-79
PA Register for successful translation bit functions .................................................................. 3-80
PA Register for unsuccessful translation bit functions .............................................................. 3-81
Results of access to the Data Synchronization Barrier operation ............................................. 3-84
Results of access to the Data Memory Barrier operation ......................................................... 3-85
Results of access to the Wait For Interrupt operation ............................................................... 3-85
Results of access to the TLB Operations Register ................................................................... 3-86
Instruction and data cache lockdown register bit functions ....................................................... 3-88
Results of access to the Instruction and Data Cache Lockdown Register ................................ 3-88
Data TCM Region Register bit functions ................................................................................... 3-90
Results of access to the Data TCM Region Register ................................................................ 3-91
Instruction TCM Region Register bit functions .......................................................................... 3-92
Results of access to the Instruction TCM Region Register ....................................................... 3-93
Data TCM Non-secure Control Access Register bit functions .................................................. 3-94
Effects of NS items for data TCM operation ............................................................................. 3-94
Instruction TCM Non-secure Control Access Register bit functions ......................................... 3-95
Effects of NS items for instruction TCM operation .................................................................... 3-95
TCM Selection Register bit functions ........................................................................................ 3-96
Results of access to the TCM Selection Register ..................................................................... 3-97
Cache Behavior Override Register bit functions ....................................................................... 3-98
Results of access to the Cache Behavior Override Register .................................................... 3-98
TLB Lockdown Register bit functions ...................................................................................... 3-100
Results of access to the TLB Lockdown Register ................................................................... 3-100
Primary Region Remap Register bit functions ........................................................................ 3-102
Encoding for the remapping of the primary memory type ....................................................... 3-103
Normal Memory Remap Register bit functions ....................................................................... 3-103
Remap encoding for Inner or Outer cacheable attributes ....................................................... 3-104
Results of access to the memory region remap registers ....................................................... 3-104
DMA identification and status register bit functions ................................................................ 3-106
DMA Identification and Status Register functions ................................................................... 3-106
Results of access to the DMA identification and status registers ........................................... 3-107
DMA User Accessibility Register bit functions ........................................................................ 3-108
Results of access to the DMA User Accessibility Register ..................................................... 3-108
DMA Channel Number Register bit functions ......................................................................... 3-109
Results of access to the DMA Channel Number Register ...................................................... 3-109
Results of access to the DMA enable registers ...................................................................... 3-111
DMA Control Register bit functions ......................................................................................... 3-112
Results of access to the DMA Control Register ...................................................................... 3-113
Results of access to the DMA Internal Start Address Register ............................................... 3-114
Results of access to the DMA External Start Address Register ............................................. 3-115
Results of access to the DMA Internal End Address Register ................................................ 3-116
DMA Channel Status Register bit functions ............................................................................ 3-117
Results of access to the DMA Channel Status Register ......................................................... 3-119
DMA Context ID Register bit functions ................................................................................... 3-120
Results of access to the DMA Context ID Register ................................................................ 3-120
Secure or Non-secure Vector Base Address Register bit functions ....................................... 3-121
Results of access to the Secure or Non-secure Vector Base Address Register .................... 3-122
Monitor Vector Base Address Register bit functions ............................................................... 3-123
Results of access to the Monitor Vector Base Address Register ............................................ 3-123

List of Tables

Table 3-125
Table 3-126
Table 3-127
Table 3-128
Table 3-129
Table 3-130
Table 3-131
Table 3-132
Table 3-133
Table 3-134
Table 3-135
Table 3-136
Table 3-137
Table 3-138
Table 3-139
Table 3-140
Table 3-141
Table 3-142
Table 3-143
Table 3-144
Table 3-145
Table 3-146
Table 3-147
Table 3-148
Table 3-149
Table 3-150
Table 3-151
Table 3-152
Table 3-153
Table 4-1
Table 4-2
Table 4-3
Table 4-4
Table 4-5
Table 4-6
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Table 6-5
Table 6-6
Table 6-7
Table 6-8
Table 6-9
Table 6-10
Table 6-11
Table 6-12
Table 6-13
Table 6-14
Table 6-15
Table 6-16
Table 6-17
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
Table 8-1
Table 8-2
Table 8-3

ARM DDI 0301H
ID012310

Interrupt Status Register bit functions ..................................................................................... 3-124
Results of access to the Interrupt Status Register .................................................................. 3-124
FCSE PID Register bit functions ............................................................................................. 3-126
Results of access to the FCSE PID Register .......................................................................... 3-126
Context ID Register bit functions ............................................................................................ 3-128
Results of access to the Context ID Register ......................................................................... 3-128
Results of access to the thread and process ID registers ....................................................... 3-129
Peripheral Port Memory Remap Register bit functions ........................................................... 3-131
Results of access to the Peripheral Port Remap Register ...................................................... 3-131
Secure User and Non-secure Access Validation Control Register bit functions ..................... 3-132
Results of access to the Secure User and Non-secure Access Validation Control Register .. 3-133
Performance Monitor Control Register bit functions ............................................................... 3-134
Performance monitoring events .............................................................................................. 3-135
Results of access to the Performance Monitor Control Register ............................................ 3-137
Results of access to the Cycle Counter Register .................................................................... 3-138
Results of access to the Count Register 0 .............................................................................. 3-139
Results of access to the Count Register 1 .............................................................................. 3-140
System validation counter register operations ........................................................................ 3-140
Results of access to the System Validation Counter Register ................................................ 3-141
System Validation Operations Register functions ................................................................... 3-142
Results of access to the System Validation Operations Register ........................................... 3-143
System Validation Cache Size Mask Register bit functions .................................................... 3-145
Results of access to the System Validation Cache Size Mask Register ................................. 3-146
TLB Lockdown Index Register bit functions ............................................................................ 3-149
TLB Lockdown VA Register bit functions ................................................................................ 3-150
TLB Lockdown PA Register bit functions ................................................................................ 3-150
Access permissions APX and AP bit fields encoding ............................................................. 3-151
TLB Lockdown Attributes Register bit functions ..................................................................... 3-151
Results of access to the TLB lockdown access registers ....................................................... 3-152
Unaligned access handling ......................................................................................................... 4-4
Memory access types ............................................................................................................... 4-13
Unalignment fault occurrence when access behavior is architecturally unpredictable ............. 4-14
Legacy endianness using CP15 c1 ........................................................................................... 4-17
Mixed-endian configuration ....................................................................................................... 4-19
B bit, U bit, and EE bit settings ................................................................................................. 4-19
Access permission bit encoding ................................................................................................ 6-12
TEX field, and C and B bit encodings used in page table formats ............................................ 6-15
Cache policy bits ....................................................................................................................... 6-16
Inner and Outer cache policy implementation options .............................................................. 6-16
Effect of remapping memory with TEX remap = 1 .................................................................... 6-17
Values that remap the shareable attribute ................................................................................ 6-18
Primary region type encoding ................................................................................................... 6-18
Inner and outer region remap encoding .................................................................................... 6-18
Memory attributes ..................................................................................................................... 6-20
Memory region backwards compatibility ................................................................................... 6-26
Fault Status Register encoding ................................................................................................. 6-34
Summary of aborts .................................................................................................................... 6-35
Translation table size ................................................................................................................ 6-43
Access types from first-level descriptor bit values .................................................................... 6-45
Access types from second-level descriptor bit values .............................................................. 6-47
CP15 register functions ............................................................................................................. 6-53
CP14 register functions ............................................................................................................. 6-54
TCM configurations ..................................................................................................................... 7-7
Access to Non-secure TCM ........................................................................................................ 7-8
Access to Secure TCM ............................................................................................................... 7-8
Summary of data accesses to TCM and caches ...................................................................... 7-14
Summary of instruction accesses to TCM and caches ............................................................. 7-15
AXI parameters for the level 2 interconnect interfaces ............................................................... 8-3
AxLEN[3:0] encoding ................................................................................................................ 8-10
AxSIZE[2:0] encoding ............................................................................................................... 8-11

xii

List of Tables

Table 8-4
Table 8-5
Table 8-6
Table 8-7
Table 8-8
Table 8-9
Table 8-10
Table 8-11
Table 8-12
Table 8-13
Table 8-14
Table 8-15
Table 8-16
Table 8-17
Table 8-18
Table 8-19
Table 8-20
Table 8-21
Table 8-22
Table 8-23
Table 8-24
Table 8-25
Table 8-26
Table 8-27
Table 8-28
Table 8-29
Table 8-30
Table 8-31
Table 8-32
Table 8-33
Table 8-34
Table 8-35
Table 8-36
Table 8-37
Table 8-38
Table 8-39
Table 8-40
Table 8-41
Table 8-42
Table 8-43
Table 8-44
Table 8-45
Table 8-46
Table 8-47
Table 8-48
Table 8-49
Table 8-50
Table 8-51
Table 8-52
Table 8-53
Table 8-54
Table 8-55
Table 8-56
Table 8-57
Table 8-58
Table 8-59
Table 8-60
Table 8-61
Table 8-62
Table 8-63

ARM DDI 0301H
ID012310

AxBURST[1:0] encoding ...........................................................................................................
AxLOCK[1:0] encoding .............................................................................................................
AxCACHE[3:0] encoding ...........................................................................................................
AxPROT[2:0] encoding .............................................................................................................
AxSIDEBAND[4:1] encoding .....................................................................................................
ARSIDEBANDI[4:1] encoding ...................................................................................................
AXI signals for Cacheable fetches ............................................................................................
AXI signals for Noncacheable fetches ......................................................................................
Linefill behavior on the AXI interface ........................................................................................
Noncacheable LDRB ................................................................................................................
Noncacheable LDRH ................................................................................................................
Noncacheable LDR or LDM1 ....................................................................................................
Noncacheable LDRD or LDM2 .................................................................................................
Noncacheable LDRD or LDM2 from word 7 .............................................................................
Noncacheable LDM3, Strongly Ordered or Device memory .....................................................
Noncacheable LDM3, Noncacheable memory or cache disabled ............................................
Noncacheable LDM3 from word 6, or 7 ....................................................................................
Noncacheable LDM4, Strongly Ordered or Device memory .....................................................
Noncacheable LDM4, Noncacheable memory or cache disabled ............................................
Noncacheable LDM4 from word 5, 6, or 7 ................................................................................
Noncacheable LDM5, Strongly Ordered or Device memory .....................................................
Noncacheable LDM5, Noncacheable memory or cache disabled ............................................
Noncacheable LDM5 from word 4, 5, 6, or 7 ............................................................................
Noncacheable LDM6, Strongly Ordered or Device memory .....................................................
Noncacheable LDM6, Noncacheable memory or cache disabled ............................................
Noncacheable LDM6 from word 3, 4, 5, 6, or 7 ........................................................................
Noncacheable LDM7, Strongly Ordered or Device memory .....................................................
Noncacheable LDM7, Noncacheable memory or cache disabled ............................................
Noncacheable LDM7 from word 2, 3, 4, 5, 6, or 7 ....................................................................
Noncacheable LDM8 from word 0 ............................................................................................
Noncacheable LDM8 from word 1, 2, 3, 4, 5, 6, or 7 ................................................................
Noncacheable LDM9 ................................................................................................................
Noncacheable LDM10 ..............................................................................................................
Noncacheable LDM11 ..............................................................................................................
Noncacheable LDM12 ..............................................................................................................
Noncacheable LDM13 ..............................................................................................................
Noncacheable LDM14 ..............................................................................................................
Noncacheable LDM15 ..............................................................................................................
Noncacheable LDM16 ..............................................................................................................
Half-line Write-Back ..................................................................................................................
Full-line Write-Back ...................................................................................................................
Cacheable Write-Through or Noncacheable STRB ..................................................................
Cacheable Write-Through or Noncacheable STRH ..................................................................
Cacheable Write-Through or Noncacheable STR or STM1 ......................................................
Cacheable Write-Through or Noncacheable STRD or STM2 to words 0, 1, 2, 3, 4, 5, or 6 .....
Cacheable Write-Through or Noncacheable STM2 to word 7 ..................................................
Cacheable Write-Through or Noncacheable STM3 to words 0, 1, 2, 3, 4, or 5 ........................
Cacheable Write-Through or Noncacheable STM3 to words 6 or 7 .........................................
Cacheable Write-Through or Noncacheable STM4 to word 0, 1, 2, 3, or 4 ..............................
Cacheable Write-Through or Noncacheable STM4 to word 5, 6, or 7 ......................................
Cacheable Write-Through or Noncacheable STM5 to word 0, 1, 2, or 3 ..................................
Cacheable Write-Through or Noncacheable STM5 to word 4, 5, 6, or 7 ..................................
Cacheable Write-Through or Noncacheable STM6 to word 0, 1, or 2 ......................................
Cacheable Write-Through or Noncacheable STM6 to word 3, 4, 5, 6, or 7 ..............................
Cacheable Write-Through or Noncacheable STM7 to word 0 or 1 ...........................................
Cacheable Write-Through or Noncacheable STM7 to word 2, 3, 4, 5, 6 or 7 ...........................
Cacheable Write-Through or Noncacheable STM8 to word 0 ..................................................
Cacheable Write-Through or Noncacheable STM8 to word 1, 2, 3, 4, 5, 6, or 7 ......................
Cacheable Write-Through or Noncacheable STM9 ..................................................................
Cacheable Write-Through or Noncacheable STM10 ................................................................

8-11
8-11
8-12
8-12
8-13
8-13
8-14
8-14
8-15
8-16
8-16
8-17
8-17
8-18
8-18
8-18
8-18
8-19
8-19
8-19
8-20
8-20
8-20
8-20
8-21
8-21
8-21
8-21
8-21
8-22
8-22
8-22
8-23
8-23
8-24
8-24
8-24
8-25
8-25
8-26
8-26
8-27
8-27
8-28
8-29
8-29
8-29
8-29
8-30
8-30
8-30
8-30
8-31
8-31
8-31
8-32
8-32
8-32
8-32
8-33

xiii

List of Tables

Table 8-64
Table 8-65
Table 8-66
Table 8-67
Table 8-68
Table 8-69
Table 8-70
Table 9-1
Table 11-1
Table 11-2
Table 11-3
Table 11-4
Table 11-5
Table 12-1
Table 13-1
Table 13-2
Table 13-3
Table 13-4
Table 13-5
Table 13-6
Table 13-7
Table 13-8
Table 13-9
Table 13-10
Table 13-11
Table 13-12
Table 13-13
Table 13-14
Table 13-15
Table 13-16
Table 13-17
Table 13-18
Table 13-19
Table 13-20
Table 13-21
Table 13-22
Table 13-23
Table 13-24
Table 13-25
Table 13-26
Table 14-1
Table 14-2
Table 15-1
Table 15-2
Table 15-3
Table 15-4
Table 15-5
Table 15-6
Table 15-7
Table 15-8
Table 15-9
Table 15-10
Table 15-11
Table 16-1
Table 16-2
Table 16-3
Table 16-4
Table 16-5
Table 16-6
Table 16-7

ARM DDI 0301H
ID012310

Cacheable Write-Through or Noncacheable STM11 ................................................................ 8-33
Cacheable Write-Through or Noncacheable STM12 ................................................................ 8-34
Cacheable Write-Through or Noncacheable STM13 ................................................................ 8-34
Cacheable Write-Through or Noncacheable STM14 ................................................................ 8-35
Cacheable Write-Through or Noncacheable STM15 ................................................................ 8-35
Cacheable Write-Through or Noncacheable STM16 ................................................................ 8-36
Example Peripheral Interface reads and writes ........................................................................ 8-37
Reset modes ............................................................................................................................. 9-10
Coprocessor instructions .......................................................................................................... 11-3
Coprocessor control signals ...................................................................................................... 11-4
Pipeline stage update ............................................................................................................... 11-7
Addressing of queue buffers ................................................................................................... 11-10
Retirement conditions ............................................................................................................. 11-20
VIC port signals ......................................................................................................................... 12-3
Terms used in register descriptions .......................................................................................... 13-5
CP14 debug register map ......................................................................................................... 13-5
Debug ID Register bit field definition ......................................................................................... 13-7
Debug Status and Control Register bit field definitions ............................................................. 13-8
Data Transfer Register bit field definitions .............................................................................. 13-12
Vector Catch Register bit field definitions ............................................................................... 13-14
Summary of debug entry and exception conditions ................................................................ 13-14
Processor breakpoint and watchpoint registers ...................................................................... 13-16
Breakpoint Value Registers, bit field definition ........................................................................ 13-17
Processor Breakpoint Control Registers ................................................................................. 13-17
Breakpoint Control Registers, bit field definitions ................................................................... 13-18
Meaning of BCR[22:20] bits .................................................................................................... 13-19
Processor Watchpoint Value Registers .................................................................................. 13-20
Watchpoint Value Registers, bit field definitions ..................................................................... 13-21
Processor Watchpoint Control Registers ................................................................................ 13-21
Watchpoint Control Registers, bit field definitions ................................................................... 13-21
Debug State Cache Control Register bit functions ................................................................. 13-23
Debug State MMU Control Register bit functions ................................................................... 13-24
CP14 debug instructions ......................................................................................................... 13-26
Debug instruction execution .................................................................................................... 13-27
Secure debug behavior ........................................................................................................... 13-28
Behavior of the processor on debug events ........................................................................... 13-33
Setting of CP15 registers on debug events ............................................................................ 13-34
Values in the link register after exceptions ............................................................................. 13-36
Read PC value after Debug state entry .................................................................................. 13-39
Example memory operation sequence ................................................................................... 13-41
Supported public instructions .................................................................................................... 14-6
Scan chain 7 register map ...................................................................................................... 14-19
Instruction interface signals ...................................................................................................... 15-2
ETMIACTL[17:0] ....................................................................................................................... 15-3
ETMIASECCTL[1:0] .................................................................................................................. 15-4
Data address interface signals .................................................................................................. 15-4
ETMDACTL[17:0] ...................................................................................................................... 15-5
Data value interface signals ...................................................................................................... 15-6
ETMDDCTL[3:0] ....................................................................................................................... 15-6
ETMPADV[2:0] .......................................................................................................................... 15-6
Coprocessor interface signals ................................................................................................... 15-7
ETMCPSECCTL[1:0] format ..................................................................................................... 15-7
Other connections ..................................................................................................................... 15-8
Pipeline stages .......................................................................................................................... 16-3
Definition of cycle timing terms ................................................................................................. 16-5
Register interlock examples ...................................................................................................... 16-6
Data Processing Instruction cycle timing behavior if destination is not PC ............................... 16-7
Data Processing Instruction cycle timing behavior if destination is the PC ............................... 16-7
QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior ................................... 16-9
ARMv6 media data-processing instructions cycle timing behavior ......................................... 16-10

xiv

List of Tables

Table 16-8
Table 16-9
Table 16-10
Table 16-11
Table 16-12
Table 16-13
Table 16-14
Table 16-15
Table 16-16
Table 16-17
Table 16-18
Table 16-19
Table 16-20
Table 16-21
Table 16-22
Table 16-23
Table 17-1
Table 17-2
Table 17-3
Table 17-4
Table 17-5
Table 17-6
Table 17-7
Table 17-8
Table 17-9
Table 19-1
Table 19-2
Table 19-3
Table 19-4
Table 19-5
Table 19-6
Table 19-7
Table 19-8
Table 19-9
Table 19-10
Table 20-1
Table 20-2
Table 20-3
Table 20-4
Table 20-5
Table 20-6
Table 20-7
Table 20-8
Table 20-9
Table 20-10
Table 21-1
Table 21-2
Table 21-3
Table 21-4
Table 21-5
Table 21-6
Table 21-7
Table 21-8
Table 21-9
Table 21-10
Table 21-11
Table 21-12
Table 21-13
Table 21-14

ARM DDI 0301H
ID012310

ARMv6 sum of absolute differences instruction timing behavior ............................................ 16-11
Example interlocks .................................................................................................................. 16-11
Example multiply instruction cycle timing behavior ................................................................. 16-12
Branch instruction cycle timing behavior ................................................................................. 16-14
Processor state updating instructions cycle timing behavior .................................................. 16-15
Cycle timing behavior for stores and loads, other than loads to the PC ................................. 16-16
Cycle timing behavior for loads to the PC ............................................................................... 16-17
and LDR example instruction explanation ............... 16-17
Load and Store Double instructions cycle timing behavior ..................................................... 16-19
and LDRD example instruction explanation ............. 16-19
Cycle timing behavior of Load and Store Multiples, other than load multiples including the PC .......
16-21
Cycle timing behavior of Load Multiples, where the PC is in the register list .......................... 16-22
RFE and SRS instructions cycle timing behavior .................................................................... 16-23
Synchronization Instructions cycle timing behavior ................................................................ 16-24
Coprocessor Instructions cycle timing behavior ...................................................................... 16-25
SVC, BKPT, undefined, prefetch aborted instructions cycle timing behavior ......................... 16-26
Global signals ........................................................................................................................... 17-3
AXI signals ................................................................................................................................ 17-3
Coprocessor signals ................................................................................................................. 17-5
ETM interface signals ............................................................................................................... 17-5
Interrupt signals ........................................................................................................................ 17-5
Debug interface signals ............................................................................................................ 17-6
Test signals ............................................................................................................................... 17-6
Static configuration signals ....................................................................................................... 17-6
TrustZone internal signals ......................................................................................................... 17-7
VFP11 MCR instructions ........................................................................................................... 19-6
VFP11 MRC instructions ........................................................................................................... 19-6
VFP11 MCRR instructions ........................................................................................................ 19-6
VFP11 MRRC instructions ........................................................................................................ 19-7
Single-precision data memory images and byte addresses ..................................................... 19-9
Double-precision data memory images and byte addresses .................................................... 19-9
Single-precision three-operand register usage ....................................................................... 19-13
Single-precision two-operand register usage .......................................................................... 19-13
Double-precision three-operand register usage ...................................................................... 19-13
Double-precision two-operand register usage ........................................................................ 19-13
Default NaN values ................................................................................................................... 20-4
QNaN and SNaN handling ........................................................................................................ 20-5
VFP11 system registers .......................................................................................................... 20-12
Accessing VFP11 system registers ........................................................................................ 20-13
FPSID bit fields ....................................................................................................................... 20-14
Encoding of the Floating-Point Status and Control Register ................................................... 20-15
Vector length and stride combinations .................................................................................... 20-16
Encoding of the Floating-Point Exception Register ................................................................. 20-17
Media and VFP Feature Register 0 bit functions .................................................................... 20-19
Media and VFP Feature Register 1 bit functions .................................................................... 20-20
Single-precision source register locking ................................................................................... 21-8
Single-precision source register clearing .................................................................................. 21-9
Double-precision source register locking ................................................................................ 21-10
Double-precision source register clearing for one-cycle instructions ...................................... 21-11
Double-precision source register clearing for two-cycle instructions ...................................... 21-11
FCMPS-FMSTAT RAW hazard .............................................................................................. 21-13
FLDM-FADDS RAW hazard ................................................................................................... 21-14
FLDM-short vector FADDS RAW hazard ................................................................................ 21-14
FMULS-FADDS RAW hazard ................................................................................................. 21-15
Short vector FMULS-FLDMS WAR hazard ............................................................................. 21-15
Short vector FMULS-FLDMS WAR hazard in RunFast mode ................................................ 21-16
FLDM-FLDS-FADDS resource hazard ................................................................................... 21-18
FLDM-short vector FMULS resource hazard .......................................................................... 21-18
Short vector FDIVS-FADDS resource hazard ......................................................................... 21-19

List of Tables

Table 21-15
Table 21-16
Table 22-1
Table 22-2
Table 22-3
Table 22-4
Table 22-5
Table 22-6
Table 22-7
Table 22-8
Table 22-9
Table 22-10
Table 22-11
Table 22-12
Table 22-13
Table A-1
Table A-2
Table A-3
Table A-4
Table A-5
Table A-6
Table A-7
Table A-8
Table A-9
Table A-10
Table A-11
Table A-12
Table A-13
Table A-14
Table B-1
Table B-2
Table B-3
Table C-1

ARM DDI 0301H
ID012310

Parallel execution in all three pipelines ................................................................................... 21-21
Throughput and latency cycle counts for VFP11 instructions ................................................. 21-22
Exceptional short vector FMULD followed by load/store instructions ....................................... 22-9
Exceptional short vector FADDS with a FADDS in the pretrigger slot .................................... 22-10
Exceptional short vector FADDD with an FMACS trigger instruction ...................................... 22-11
Possible Invalid Operation exceptions .................................................................................... 22-13
Default results for invalid conversion inputs ............................................................................ 22-14
Rounding mode overflow results ............................................................................................. 22-16
LSA and USA determination ................................................................................................... 22-20
FADD family bounce thresholds ............................................................................................. 22-21
FMUL family bounce thresholds ............................................................................................. 22-22
FDIV bounce thresholds ......................................................................................................... 22-23
FCVTSD bounce thresholds ................................................................................................... 22-24
Single-precision float-to-integer bounce thresholds and stored results .................................. 22-25
Double-precision float-to-integer bounce thresholds and stored results ................................. 22-26
Global signals ............................................................................................................................. A-2
Static configuration signals ......................................................................................................... A-4
TrustZone internal signals ........................................................................................................... A-5
Interrupt signals .......................................................................................................................... A-6
Port signal name suffixes ............................................................................................................ A-7
Instruction read port AXI signal implementation ......................................................................... A-8
Data port AXI signal implementation ........................................................................................... A-9
Peripheral port AXI signal implementation ................................................................................ A-10
DMA port signals ....................................................................................................................... A-11
Core to coprocessor signals ..................................................................................................... A-12
Coprocessor to core signals ..................................................................................................... A-12
Debug interface signals ............................................................................................................ A-14
ETM interface signals ............................................................................................................... A-15
Test signals ............................................................................................................................... A-16
TCM for ARM1176JZF-S processors .......................................................................................... B-6
CP15 c15 features common to ARM1136JF-S and ARM1176JZF-S processors ...................... B-8
CP15 c15 only found in ARM1136JF-S processors .................................................................... B-9
Differences between issue G and issue H .................................................................................. C-1

xvi

List of Figures
ARM1176JZF-S Technical Reference Manual

Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 1-5
Figure 1-6
Figure 1-7
Figure 1-8
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 2-7
Figure 2-8
Figure 2-9
Figure 2-10
Figure 2-11
Figure 2-12
Figure 2-13
Figure 2-14
Figure 2-15
Figure 2-16
Figure 2-17
Figure 2-18
Figure 3-1
Figure 3-2
Figure 3-3
ARM DDI 0301H
ID012310

Key to timing diagram conventions ............................................................................................ xxiv
ARM1176JZF-S processor block diagram .................................................................................. 1-8
ARM1176JZF-S pipeline stages ............................................................................................... 1-26
Typical operations in pipeline stages ........................................................................................ 1-28
Typical ALU operation ............................................................................................................... 1-28
Typical multiply operation ......................................................................................................... 1-29
Progression of an LDR/STR operation ..................................................................................... 1-30
Progression of an LDM/STM operation ..................................................................................... 1-30
Progression of an LDR that misses .......................................................................................... 1-31
Secure and Non-secure worlds ................................................................................................... 2-3
Memory in the Secure and Non-secure worlds ........................................................................... 2-6
Memory partition in the Secure and Non-secure worlds ............................................................. 2-7
Big-endian addresses of bytes within words ............................................................................. 2-15
Little-endian addresses of bytes within words .......................................................................... 2-15
Register organization in ARM state .......................................................................................... 2-20
Processor core register set showing banked registers ............................................................. 2-21
Register organization in Thumb state ....................................................................................... 2-22
ARM state and Thumb state registers relationship ................................................................... 2-23
Program status register ............................................................................................................. 2-24
LDREXB instruction .................................................................................................................. 2-30
STREXB instructions ................................................................................................................ 2-30
LDREXH instruction .................................................................................................................. 2-31
STREXH instruction .................................................................................................................. 2-32
LDREXD instruction .................................................................................................................. 2-33
STREXD instruction .................................................................................................................. 2-33
CLREX instruction ..................................................................................................................... 2-34
NOP-compatible hint instruction ............................................................................................... 2-34
System control and configuration registers ................................................................................. 3-5
MMU control and configuration registers .................................................................................... 3-7
Cache control and configuration registers .................................................................................. 3-8
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access

xvii

List of Figures

Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Figure 3-11
Figure 3-12
Figure 3-13
Figure 3-14
Figure 3-15
Figure 3-16
Figure 3-17
Figure 3-18
Figure 3-19
Figure 3-20
Figure 3-21
Figure 3-22
Figure 3-23
Figure 3-24
Figure 3-25
Figure 3-26
Figure 3-27
Figure 3-28
Figure 3-29
Figure 3-30
Figure 3-31
Figure 3-32
Figure 3-33
Figure 3-34
Figure 3-35
Figure 3-36
Figure 3-37
Figure 3-38
Figure 3-39
Figure 3-40
Figure 3-41
Figure 3-42
Figure 3-43
Figure 3-44
Figure 3-45
Figure 3-46
Figure 3-47
Figure 3-48
Figure 3-49
Figure 3-50
Figure 3-51
Figure 3-52
Figure 3-53
Figure 3-54
Figure 3-55
Figure 3-56
Figure 3-57
Figure 3-58
Figure 3-59
Figure 3-60
Figure 3-61
Figure 3-62
Figure 3-63

ARM DDI 0301H
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TCM control and configuration registers ..................................................................................... 3-8
Cache Master Valid Registers .................................................................................................... 3-9
DMA control and configuration registers ..................................................................................... 3-9
System performance monitor registers ..................................................................................... 3-10
System validation registers ....................................................................................................... 3-11
CP15 MRC and MCR bit pattern ............................................................................................... 3-12
Main ID Register format ............................................................................................................ 3-20
Cache Type Register format ..................................................................................................... 3-21
TCM Status Register format ..................................................................................................... 3-24
TLB Type Register format ......................................................................................................... 3-25
Processor Feature Register 0 format ........................................................................................ 3-26
Processor Feature Register 1 format ........................................................................................ 3-28
Debug Feature Register 0 format ............................................................................................. 3-29
Memory Model Feature Register 0 format ................................................................................ 3-31
Memory Model Feature Register 1 format ................................................................................ 3-32
Memory Model Feature Register 2 format ................................................................................ 3-34
Memory Model Feature Register 3 format ................................................................................ 3-35
Instruction Set Attributes Register 0 format .............................................................................. 3-36
Instruction Set Attributes Register 1 format .............................................................................. 3-38
Instruction Set Attributes Register 2 format .............................................................................. 3-39
Instruction Set Attributes Register 3 format .............................................................................. 3-40
Instruction Set Attributes Register 4 format .............................................................................. 3-42
Control Register format ............................................................................................................. 3-44
Auxiliary Control Register format .............................................................................................. 3-49
Coprocessor Access Control Register format ........................................................................... 3-51
Secure Configuration Register format ....................................................................................... 3-52
Secure Debug Enable Register format ..................................................................................... 3-54
Non-Secure Access Control Register format ............................................................................ 3-56
Translation Table Base Register 0 format ................................................................................ 3-57
Translation Table Base Register 1 format ................................................................................ 3-59
Translation Table Base Control Register format ....................................................................... 3-61
Domain Access Control Register format ................................................................................... 3-63
Data Fault Status Register format ............................................................................................. 3-64
Instruction Fault Status Register format .................................................................................... 3-66
Cache operations ...................................................................................................................... 3-70
Cache operations with MCRR instructions ............................................................................... 3-71
c7 format for Set and Index ....................................................................................................... 3-72
c7 format for MVA ..................................................................................................................... 3-73
Format of c7 for VA ................................................................................................................... 3-73
Cache Dirty Status Register format .......................................................................................... 3-78
c7 format for Flush Branch Target Entry using MVA ................................................................ 3-79
PA Register format for successful translation ........................................................................... 3-80
PA Register format for aborted translation ................................................................................ 3-80
TLB Operations Register MVA and ASID format ...................................................................... 3-87
TLB Operations Register ASID format ...................................................................................... 3-87
Instruction and data cache lockdown register formats .............................................................. 3-88
Data TCM Region Register format ............................................................................................ 3-90
Instruction TCM Region Register format ................................................................................... 3-91
Data TCM Non-secure Control Access Register format ........................................................... 3-93
Instruction TCM Non-secure Control Access Register format .................................................. 3-95
TCM Selection Register format ................................................................................................. 3-96
Cache Behavior Override Register format ................................................................................ 3-97
TLB Lockdown Register format ............................................................................................... 3-100
Primary Region Remap Register format ................................................................................. 3-102
Normal Memory Remap Register format ................................................................................ 3-103
DMA identification and status registers format ....................................................................... 3-106
DMA User Accessibility Register format ................................................................................. 3-108
DMA Channel Number Register format .................................................................................. 3-109
DMA Control Register format .................................................................................................. 3-112
DMA Channel Status Register format ..................................................................................... 3-117

xviii

List of Figures

Figure 3-64
Figure 3-65
Figure 3-66
Figure 3-67
Figure 3-68
Figure 3-69
Figure 3-70
Figure 3-71
Figure 3-72
Figure 3-73
Figure 3-74
Figure 3-75
Figure 3-76
Figure 3-77
Figure 3-78
Figure 3-79
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 4-7
Figure 4-8
Figure 4-9
Figure 4-10
Figure 4-11
Figure 4-12
Figure 4-13
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-5
Figure 6-6
Figure 6-7
Figure 6-8
Figure 6-9
Figure 6-10
Figure 6-11
Figure 6-12
Figure 6-13
Figure 6-14
Figure 6-15
Figure 6-16
Figure 6-17
Figure 6-18
Figure 7-1
Figure 8-1
Figure 8-2
Figure 8-3
Figure 8-4
Figure 9-1
Figure 9-2
Figure 9-3
Figure 9-4
Figure 9-5
Figure 9-6
Figure 10-1

ARM DDI 0301H
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DMA Context ID Register format ............................................................................................ 3-120
Secure or Non-secure Vector Base Address Register format ................................................ 3-121
Monitor Vector Base Address Register format ........................................................................ 3-122
Interrupt Status Register format .............................................................................................. 3-124
FCSE PID Register format ...................................................................................................... 3-126
Address mapping with the FCSE PID Register ....................................................................... 3-127
Context ID Register format ..................................................................................................... 3-128
Peripheral Port Memory Remap Register format .................................................................... 3-130
Secure User and Non-secure Access Validation Control Register format .............................. 3-132
Performance Monitor Control Register format ........................................................................ 3-133
System Validation Counter Register format for external debug request counter .................... 3-141
System Validation Cache Size Mask Register format ............................................................. 3-145
TLB Lockdown Index Register format ..................................................................................... 3-149
TLB Lockdown VA Register format ......................................................................................... 3-149
TLB Lockdown PA Register format ......................................................................................... 3-150
TLB Lockdown Attributes Register format .............................................................................. 3-151
Load unsigned byte ..................................................................................................................... 4-6
Load signed byte ......................................................................................................................... 4-6
Store byte .................................................................................................................................... 4-7
Load unsigned halfword, little-endian ......................................................................................... 4-7
Load unsigned halfword, big-endian ........................................................................................... 4-8
Load signed halfword, little-endian ............................................................................................. 4-8
Load signed halfword, big-endian ............................................................................................... 4-9
Store halfword, little-endian ........................................................................................................ 4-9
Store halfword, big-endian ........................................................................................................ 4-10
Load word, little-endian ............................................................................................................. 4-10
Load word, big-endian .............................................................................................................. 4-11
Store word, little-endian ............................................................................................................ 4-11
Store word, big-endian .............................................................................................................. 4-12
Memory ordering restrictions .................................................................................................... 6-24
Translation table managed TLB fault checking sequence part 1 .............................................. 6-30
Translation table managed TLB fault checking sequence part 2 .............................................. 6-31
Backwards-compatible first-level descriptor format .................................................................. 6-37
Backwards-compatible second-level descriptor format ............................................................. 6-38
Backwards-compatible section, supersection, and page translation ........................................ 6-38
ARMv6 first-level descriptor formats with subpages disabled ................................................... 6-39
ARMv6 second-level descriptor format ..................................................................................... 6-40
ARMv6 section, supersection, and page translation ................................................................. 6-41
Creating a first-level descriptor address ................................................................................... 6-44
Translation for a 1MB section, ARMv6 format .......................................................................... 6-46
Translation for a 1MB section, backwards-compatible format .................................................. 6-46
Generating a second-level page table address ........................................................................ 6-47
Large page table walk, ARMv6 format ...................................................................................... 6-48
Large page table walk, backwards-compatible format .............................................................. 6-49
4KB small page or 1KB small subpage translations, backwards-compatible format ................ 6-50
4KB extended small page translations, ARMv6 format ............................................................. 6-51
4KB extended small page or 1KB extended small subpage translations,
backwards-compatible format ................................................................................................... 6-52
Level one cache block diagram .................................................................................................. 7-4
Level two interconnect interfaces ................................................................................................ 8-2
Channel architecture of reads ..................................................................................................... 8-8
Channel architecture of writes .................................................................................................... 8-8
Swizzling of data and strobes in BE-32 big-endian configuration ............................................. 8-38
Processor clocks with no IEM ..................................................................................................... 9-3
Read latency with no IEM ........................................................................................................... 9-4
Processor clocks with IEM .......................................................................................................... 9-6
Processor synchronization with IEM ........................................................................................... 9-6
Read latency with IEM ................................................................................................................ 9-8
Power-on reset .......................................................................................................................... 9-10
IEM structure ............................................................................................................................. 10-8

xix

List of Figures

Figure 11-1
Figure 11-2
Figure 11-3
Figure 11-4
Figure 11-5
Figure 11-6
Figure 11-7
Figure 11-8
Figure 11-9
Figure 11-10
Figure 12-1
Figure 12-2
Figure 12-3
Figure 13-1
Figure 13-2
Figure 13-3
Figure 13-4
Figure 13-5
Figure 13-6
Figure 13-7
Figure 14-1
Figure 14-2
Figure 14-3
Figure 14-4
Figure 14-5
Figure 14-6
Figure 14-7
Figure 14-8
Figure 14-9
Figure 14-10
Figure 14-11
Figure 14-12
Figure 14-13
Figure 14-14
Figure 15-1
Figure 18-1
Figure 18-2
Figure 18-3
Figure 19-1
Figure 19-2
Figure 19-3
Figure 19-4
Figure 20-1
Figure 20-2
Figure 20-3
Figure 20-4
Figure 20-5
Figure 20-6
Figure 20-7
Figure 20-8
Figure 20-9

ARM DDI 0301H
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Core and coprocessor pipelines ............................................................................................... 11-5
Coprocessor pipeline and queues ............................................................................................ 11-5
Coprocessor pipeline ................................................................................................................ 11-6
Token queue buffers ................................................................................................................. 11-9
Queue reading and writing ...................................................................................................... 11-10
Queue flushing ........................................................................................................................ 11-11
Instruction queue .................................................................................................................... 11-12
Coprocessor data transfer ...................................................................................................... 11-15
Instruction iteration for loads ................................................................................................... 11-16
Load data buffering ................................................................................................................. 11-17
Connection of a VIC to the processor ....................................................................................... 12-3
VIC port timing example ............................................................................................................ 12-5
Interrupt entry sequence ........................................................................................................... 12-7
Typical debug system ............................................................................................................... 13-2
Debug ID Register format ......................................................................................................... 13-6
Debug Status and Control Register format ............................................................................... 13-8
DTR format ............................................................................................................................. 13-12
Vector Catch Register format .................................................................................................. 13-13
Breakpoint Control Registers, format ...................................................................................... 13-17
Watchpoint Control Registers, format ..................................................................................... 13-21
JTAG DBGTAP state machine diagram .................................................................................... 14-2
RealView ICE clock synchronization ......................................................................................... 14-3
Bypass register bit order ........................................................................................................... 14-8
Device ID code register bit order .............................................................................................. 14-9
Instruction register bit order ...................................................................................................... 14-9
Scan chain select register bit order ......................................................................................... 14-10
Scan chain 0 bit order ............................................................................................................. 14-11
Scan chain 1 bit order ............................................................................................................. 14-11
Scan chain 4 bit order ............................................................................................................. 14-13
Scan chain 5 bit order, EXTEST selected ............................................................................... 14-15
Scan chain 5 bit order, INTEST selected ................................................................................ 14-15
Scan chain 6 bit order ............................................................................................................. 14-17
Scan chain 7 bit order ............................................................................................................. 14-18
Behavior of the ITRsel IR instruction ...................................................................................... 14-22
ETMCPADDRESS format ......................................................................................................... 15-7
FMAC pipeline .......................................................................................................................... 18-6
DS pipeline ................................................................................................................................ 18-8
LS pipeline ................................................................................................................................ 18-9
Single-precision data format ..................................................................................................... 19-3
Double-precision data format .................................................................................................... 19-4
Register file access ................................................................................................................... 19-5
Register banks ........................................................................................................................ 19-10
FMDRR instruction format ........................................................................................................ 20-8
FMRRD instruction format ........................................................................................................ 20-9
FMSRR instruction format ....................................................................................................... 20-10
FMRRS instruction format ....................................................................................................... 20-11
Floating-Point System ID Register .......................................................................................... 20-13
Floating-Point Status and Control Register ............................................................................. 20-14
Floating-Point Exception Register ........................................................................................... 20-17
Media and VFP Feature Register 0 format ............................................................................. 20-19
Media and VFP Feature Register 1 format ............................................................................. 20-20

Preface

This preface introduces the ARM1176JZF-S™ Technical Reference Manual (TRM). It contains the
following sections:
•
About this book on page xxii
•
Feedback on page xxvi.

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xxi

Preface

About this book
This book is for ARM1176JZF-S processor. In this manual the generic term processor means
the ARM1176JZF-S processor.
Product revision status
The rnpn identifier indicates the revision status of the product described in this book, where:
rn
Identifies the major revision of the product.
pn
Identifies the minor revision or modification status of the product.
Intended audience
This document has been written for hardware and software engineers implementing the
processor system designs. It provides information to enable designers to integrate the processor
into a target system as quickly as possible.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
Read this for an introduction to the processor and descriptions of the major
functional blocks.
Chapter 2 Programmer’s Model
Read this for a description of the processor registers and programming details.
Chapter 3 System Control Coprocessor
Read this for a description of the processor’s system control coprocessor CP15
registers and programming details.
Chapter 4 Unaligned and Mixed-endian Data Access Support
Read this for a description of the processor support for unaligned and
mixed-endian data accesses.
Chapter 5 Program Flow Prediction
Read this for a description of the functions of the processor’s Prefetch Unit,
including static and dynamic branch prediction and the return stack.
Chapter 6 Memory Management Unit
Read this for a description of the processor’s Memory Management Unit (MMU)
and the address translation process.
Chapter 7 Level One Memory System
Read this for a description of the processor’s level one memory system, including
caches, TCM, DMA, TLBs, and write buffer.
Chapter 8 Level Two Interface
Read this for a description of the processor’s level two memory interface and the
peripheral port.
Chapter 9 Clocking and Resets
Read this for a description of the processor’s clocking modes and the reset
signals.

ARM DDI 0301H
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xxii

Preface

Chapter 10 Power Control
Read this for a description of the processor’s power control facilities.
Chapter 11 Coprocessor Interface
Read this for details of the processor’s coprocessor interface.
Chapter 12 Vectored Interrupt Controller Port
Read this for a description of the processor’s Vectored Interrupt Controller
interface.
Chapter 13 Debug
Read this for a description of the processor’s debug support.
Chapter 14 Debug Test Access Port
Read this for a description of the JTAG-based processor Debug Test Access Port.
Chapter 15 Trace Interface Port
Read this for a description of the trace interface port.
Chapter 16 Cycle Timings and Interlock Behavior
Read this for a description of the processor’s instruction cycle timing and for
details of the interlocks.
Chapter 17 AC Characteristics
Read this for a description of the timing parameters applicable to the processor.
Chapter 18 Introduction to the VFP coprocessor
Read this to get an overview of the VFP11 coprocessor.
Chapter 19 The VFP Register File
Read this to learn about the structure and operation of the VFP11 register file.
Chapter 20 VFP Programmer’s Model
Read this to learn about the VFPv2 programmer’s model, including the
ARMv5TE coprocessor extension instructions and the architecture compliance of
VFPv2 with the IEEE 754 standard.
Chapter 21 VFP Instruction Execution
Read this to learn about forwarding, hazards, and parallel execution in the VFP11
instruction pipelines.
Chapter 22 VFP Exception Handling
Read this to learn about VFP11 exceptional conditions and how they are handled
in hardware and software.
Appendix A Signal Descriptions
Read this for a description of the processor signals.
Appendix B Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences
Read this for a summary of the differences between the ARM1136JF-S™ and
ARM1176JZF-S processors.
Appendix C Revisions
Read this for a description of the technical changes between released issues of this
book.
ARM DDI 0301H
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xxiii

Preface

Glossary

Read this for definitions of terms used in this book.

Conventions
Conventions that this book can use are described in:
•
Typographical
•
Timing diagrams
•
Signals on page xxv.
Typographical
The typographical conventions are:
italic

Highlights important notes, introduces special terminology, denotes
internal cross-references, and citations.

bold

Highlights interface elements, such as menu names. Denotes signal
names. Also used for terms in descriptive lists, where appropriate.

monospace

Denotes text that you can enter at the keyboard, such as commands, file
and program names, and source code.

monospace

Denotes a permitted abbreviation for a command or option. You can enter
the underlined text instead of the full command or option name.

monospace italic

Denotes arguments to monospace text where the argument is to be
replaced by a specific value.

monospace bold

Denotes language keywords when used outside example code.

< and >

Enclose replaceable terms for assembler syntax where they appear in code
or code fragments. For example:
MRC p15, 0 , , ,

Timing diagrams
The figure named Key to timing diagram conventions explains the components used in timing
diagrams. Variations, when they occur, have clear labels. You must not assume any timing
information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the
shaded area at that time. The actual level is unimportant and does not affect normal operation.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus

Key to timing diagram conventions

ARM DDI 0301H
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xxiv

Preface

Signals
The signal conventions are:
Signal level

The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means:
•
HIGH for active-HIGH signals
•
LOW for active-LOW signals.

Lower-case n

At the start or end of a signal name denotes an active-LOW signal.

Additional reading
This section lists publications by ARM and by third parties.
See Infocenter, http://infocenter.arm.com, for access to ARM documentation.
ARM publications
This book contains information that is specific to this product. See the following documents for
other relevant information:
•
ARM Architecture Reference Manual (ARM DDI 0406)
Note
The ARM DDI 0406 edition of the ARM Architecture Reference Manual (the ARM ARM)
incorporates the supplements to the previous ARM ARM, including the Security
Extensions supplement.
•
•
•
•
•
•
•
•
•
•

Jazelle® V1 Architecture Reference Manual (ARM DDI 0225)
AMBA® AXI Protocol V1.0 Specification (ARM IHI 0022)
Embedded Trace Macrocell Architecture Specification (ARM IHI 0014)
ARM1136J-S Technical Reference Manual (ARM DDI 0211)
ARM11 Memory Built-In Self Test Controller Technical Reference Manual
(ARM DDI 0289)
ARM1176JZF-S™ and ARM1176JZ-S™ Implementation Guide (ARM DII 0081)
CoreSight ETM11™ Technical Reference Manual (ARM DDI 0318)
RealView™ Compilation Tools Developer Guide (ARM DUI 0203)
ARM PrimeCell® Vectored Interrupt Controller (PL192) Technical Reference Manual
(ARM DDI 0273).
Intelligent Energy Controller Technical Overview (ARM DTO 0005).

Other publications
This section lists relevant documents published by third parties:
•

IEEE Standard Test Access Port and Boundary-Scan Architecture specification, IEEE Std.
1149.1-1990 (JTAG).

•

IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std 754-1985.

Figure 14-1 on page 14-2 is printed with permission IEEE Std. 1149.1-1990, IEEE Standard
Test Access Port and Boundary-Scan Architecture Copyright 2001, by IEEE. The IEEE
disclaims any responsibility or liability resulting from the placement and use in the described
manner.

ARM DDI 0301H
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xxv

Preface

Feedback
ARM welcomes feedback on this product and its documentation.
Feedback on this product
If you have any comments or suggestions about this product, contact your supplier and give:
•

The product name.

•

The product revision or version.

•

An explanation with as much information as you can provide. Include symptoms and
diagnostic procedures if appropriate.

Feedback on content
If you have comments on content then send an e-mail to errata@arm.com. Give:
•
the title
•
the number, ARM DDI 0301H
•
the page numbers to which your comments apply
•
a concise explanation of your comments.
ARM also welcomes general suggestions for additions and improvements.

ARM DDI 0301H
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xxvi

Chapter 1
Introduction

This chapter introduces the ARM1176JZF-S processor and its features. It contains the following
sections:
•
About the processor on page 1-2
•
Extensions to ARMv6 on page 1-3
•
TrustZone security extensions on page 1-4
•
ARM1176JZF-S architecture with Jazelle technology on page 1-6
•
Components of the processor on page 1-8
•
Power management on page 1-23
•
Configurable options on page 1-25
•
Pipeline stages on page 1-26
•
Typical pipeline operations on page 1-28
•
ARM1176JZF-S instruction set summary on page 1-32
•
Product revisions on page 1-47.

ARM DDI 0301H
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1-1

Introduction

1.1

About the processor
The ARM1176JZF-S processor incorporates an integer core that implements the ARM11 ARM
architecture v6. It supports the ARM and Thumb™ instruction sets, Jazelle technology to enable
direct execution of Java bytecodes, and a range of SIMD DSP instructions that operate on 16-bit
or 8-bit data values in 32-bit registers.
The ARM1176JZF-S processor features:
•
TrustZone™ security extensions
•
provision for Intelligent Energy Management (IEM™)
•
high-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced Extensible
Interface (AXI) level two interfaces supporting prioritized multiprocessor
implementations.
•
an integer core with integral EmbeddedICE-RT logic
•
an eight-stage pipeline
•
branch prediction with return stack
•
low interrupt latency configuration
•
internal coprocessors CP14 and CP15
•
Vector Floating-Point (VFP) coprocessor support
•
external coprocessor interface
•
Instruction and Data Memory Management Units (MMUs), managed using MicroTLB
structures backed by a unified Main TLB
•
Instruction and data caches, including a non-blocking data cache with Hit-Under-Miss
(HUM)
•
virtually indexed and physically addressed caches
•
64-bit interface to both caches
•
level one Tightly-Coupled Memory (TCM) that you can use as a local RAM with DMA
•
trace support
•
JTAG-based debug.
Note
The only functional difference between the ARM1176JZ-S and ARM1176JZF-S processor is
that the ARM1176JZF-S processor includes a Vector Floating-Point (VFP) coprocessor.

ARM DDI 0301H
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1-2

Introduction

1.2

Extensions to ARMv6
The ARM1176JZF-S processor provides support for extensions to ARMv6 that include:
•

Store and Load Exclusive instructions for bytes, halfwords and doublewords and a new
Clear Exclusive instruction.

•

A true no-operation instruction and yield instruction.

•

Architectural remap registers.

•

Cache size restriction through CP15 c1. You can restrict cache size to 16KB for Operating
Systems (OSs) that do not support page coloring.

•

Revised use of TEX remap bits. The ARMv6 MMU page table descriptors use a large
number of bits to describe all of the options for inner and outer cachability. In reality, it is
believed that no application requires all of these options simultaneously. Therefore, it is
possible to configure the ARM1176JZF-S processor to support only a small number of
options by means of the TEX remap mechanism. This implies a level of indirection in the
page table mappings.
The TEX CB encoding table provides two OS managed page table bits. For binary
compatibility with existing ARMv6 ports of OSs, this gives a separate mode of operation
of the MMU. This is called the TEX Remap configuration and is controlled by bit [28] TR
in CP15 Register 1.

•

ARM DDI 0301H
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Revised use of AP bits. In the ARM1176JZF-S processor the APX and AP[1:0] encoding
b111 is Privileged or User mode read only access. AP[0] indicates an abort type, Access
Bit fault, when CP15 c1[29] is 1.

1-3

Introduction

1.3

TrustZone security extensions
Caution
TrustZone security extensions enable a Secure software environment. The technology does not
protect the processor from hardware attacks and the implementor must take appropriate steps to
secure the hardware and protect trusted code.
The ARM1176JZF-S processor supports TrustZone security extensions to provide a secure
environment for software. This section summarizes processor elements that TrustZone uses. For
details of TrustZone, see the ARM Architecture Reference Manual.
The TrustZone approach to integrated system security depends on an established trusted code
base. The trusted code is a relatively small block that runs in the Secure world in the processor
and provides the foundation for security throughout the system. This security applies from
system boot and enforces a level of trust at each stage of a transaction.
The processor has:
•
seven operating modes that can be either Secure or Non-secure
•
Secure Monitor mode, that is always Secure.
Except when the processor is in Secure Monitor mode, the NS bit in the Secure Configuration
Register determines whether the processor runs code in the Secure or Non-secure worlds. The
Secure Configuration Register is in CP15 register c1, see c1, Secure Configuration Register on
page 3-52.
Secure Monitor mode is used to switch operation between the Secure and Non-secure worlds.
Secure Monitor mode uses these banked registers:
R13_mon
Stack Pointer
R14_mon
Link Register
SPSR_mon Saved Program Status Register
The processor implements this instruction to enter Secure Monitor mode:
SMC

Secure Monitor Call, switches from one of the privileged modes to the Secure
Monitor mode.

The processor implements these TrustZone related signals:
nDMASIRQ Secure DMA transfer request, see c11, DMA Channel Status Register on
page 3-117.
nDMAEXTERRIR
Not maskable error DMA interrupt, see c11, DMA Channel Status Register on
page 3-117.
SPIDEN

Secure privileged invasive debug enable, see Secure Monitor mode and debug on
page 13-4.

SPNIDEN

Secure privileged non-invasive debug enable, see Secure Monitor mode and
debug on page 13-4.

Note
Do not confuse Secure Monitor mode with the Monitor debug-mode.

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AXI supports trusted peripherals through these signals:
AxPROT[1]
Protection type signal, see AxPROT[2:0] on page 8-12.
RRESP[1:0]
Read response signal, see AXI interface signals on page A-7.
BRESP[1:0]
Write response signal, see AXI interface signals on page A-7.
ETMIASECCTL[1:0] and ETMCPSECCTL[1:0]
TrustZone information for tracing, see Secure control bus on page 15-4.

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1.4

ARM1176JZF-S architecture with Jazelle technology
The ARM1176JZF-S processor has three instruction sets:
•
the 32-bit ARM instruction set used in ARM state, with media instructions
•
the 16-bit Thumb instruction set used in Thumb state
•
the 8-bit Java bytecodes used in Jazelle state.
For details of both the ARM and Thumb instruction sets, see the ARM Architecture Reference
Manual. For full details of the ARM1176JZF-S Java instruction set, see the Jazelle V1
Architecture Reference Manual.

1.4.1

Instruction compression
A typical 32-bit architecture can manipulate 32-bit integers with single instructions, and address
a large address space much more efficiently than a 16-bit architecture. When processing 32-bit
data, a 16-bit architecture takes at least two instructions to perform the same task as a single
32-bit instruction.
When a 16-bit architecture has only 16-bit instructions, and a 32-bit architecture has only 32-bit
instructions, overall the 16-bit architecture has higher code density, and greater than half the
performance of the 32-bit architecture.
Thumb implements a 16-bit instruction set on a 32-bit architecture, giving higher performance
than on a 16-bit architecture, with higher code density than a 32-bit architecture.
The ARM1176JZ-S processor can easily switch between running in ARM state and running in
Thumb state. This enables you to optimize both code density and performance to best suit your
application requirements.

1.4.2

The Thumb instruction set
The Thumb instruction set is a subset of the most commonly used 32-bit ARM instructions.
Thumb instructions are 16 bits long, and have a corresponding 32-bit ARM instruction that has
the same effect on the processor model. Thumb instructions operate with the standard ARM
register configuration, enabling excellent interoperability between ARM and Thumb states.
Thumb has all the advantages of a 32-bit core:
•
32-bit address space
•
32-bit registers
•
32-bit shifter and Arithmetic Logic Unit (ALU)
•
32-bit memory transfer.
Thumb therefore offers a long branch range, powerful arithmetic operations, and a large address
space.
The availability of both 16-bit Thumb and 32-bit ARM instruction sets, gives you the flexibility
to emphasize performance or code size on a subroutine level, according to the requirements of
their applications. For example, you can code critical loops for applications such as fast
interrupts and DSP algorithms using the full ARM instruction set, and linked with Thumb code.

1.4.3

Java bytecodes
ARM architecture v6 with Jazelle technology executes variable length Java bytecodes. Java
bytecodes fall into two classes:
Hardware execution
Bytecodes that perform stack-based operations.

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Software execution
Bytecodes that are too complex to execute directly in hardware are executed in
software. An ARM register is used to access a table of exception handlers to
handle these particular bytecodes.
A complete list of the ARM1176JZF-S processor-supported Java bytecodes and their
corresponding hardware or software instructions is in the Jazelle V1 Architecture Reference
Manual.

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1.5

Components of the processor
The main components of the ARM1176JZF-S processor are:
•
Integer core
•
Load Store Unit (LSU) on page 1-11
•
Prefetch unit on page 1-11
•
Memory system on page 1-12
•
AMBA AXI interface on page 1-16
•
Coprocessor interface on page 1-17
•
Debug on page 1-17
•
Instruction cycle summary and interlocks on page 1-19
•
Vector Floating-Point (VFP) on page 1-19
•
System control on page 1-21
•
Interrupt handling on page 1-21.
Figure 1-1 shows the structure of the ARM1176JZF-S processor.
ARM1176JZF-S
JTAG interface

ETM interface

Coprocessor
interface

VIC interface

Vector Floating
Point Coprocessor

Instruction
Cache

Prefetch
Unit

Integer
core

Load Store
Unit

Data
Cache

Instruction
TCM

L1 instruction
side controller

Memory
management
unit

L1 data side
controller

Data
TCM

System
metrics

L2 instruction
interface

Power
control

L2 data
interface

Peripheral
port

L2 DMA
interface

Figure 1-1 ARM1176JZF-S processor block diagram

1.5.1

Integer core
The ARM1176JZF-S processor is built around the ARM11 integer core. It is an implementation
of the ARMv6 architecture, that runs the ARM, Thumb, and Java instruction sets. The processor
contains EmbeddedICE-RT™ logic and a JTAG debug interface to enable hardware debuggers to
communicate with the processor. The following sections describe the core in more detail:
•
Instruction set categories on page 1-9
•
Conditional execution on page 1-9

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•
•
•
•
•
•
•
•

Registers
Modes and exceptions
Thumb instruction set on page 1-10
DSP instructions on page 1-10
Media extensions on page 1-10
Datapath on page 1-10
Branch prediction on page 1-11
Return stack on page 1-11.

Instruction set categories
The main instruction set categories are:
•
branch instructions
•
data processing instructions
•
status register transfer instructions
•
load and store instructions
•
coprocessor instructions.
•
exception-generating instructions.
Note
Only load, store, and swap instructions can access data from memory.

Conditional execution
The processor conditionally executes nearly all ARM instructions. You can decide if the
condition code flags, Negative, Zero, Carry, and Overflow, are updated according to their result.
Registers
The ARM1176JZF-S core contains:
•
33 general-purpose 32-bit registers
•
7 dedicated 32-bit registers.
Note
At any one time, 16 general-purpose registers are visible. The remainder are banked registers
used to speed up exception processing.

Modes and exceptions
The core provides a set of operating and exception modes, to support systems combining
complex operating systems, user applications, and real-time demands. There are eight operating
modes, six of them are exception processing modes:
•
User
•
Supervisor
•
fast interrupt
•
normal interrupt
•
abort
•
system
•
Undefined

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•

Secure Monitor.

Thumb instruction set
The Thumb instruction set contains a subset of the most commonly-used 32-bit ARM
instructions encoded into 16-bit wide opcodes. This reduces the amount of memory required for
instruction storage.
DSP instructions
The DSP extensions to the ARM instruction set provide:
•
16-bit data operations
•
saturating arithmetic
•
MAC operations.
The processor executes multiply instructions using a single-cycle 32x16 implementation. The
processor can perform 32x32, 32x16, and 16x16 multiply instructions (MAC).
Media extensions
The ARMv6 instruction set provides media instructions to complement the DSP instructions.
There are four media instruction groups:
•

Multiplication instructions for handling 16-bit and 32-bit data, including
dual-multiplication instructions that operate on both 16-bit halves of their source registers.
This group includes an instruction that improves the performance and size of code for
multi-word unsigned multiplications.

•

Single Instruction Multiple Data (SIMD) Instructions to perform operations on pairs of
16-bit values held in a single register, or on sets of four 8-bit values held in a single
register. The main operations supplied are addition and subtraction, selection, pack, and
saturation.

•

Instructions to extract bytes and halfwords from registers and zero-extend or sign-extend
them. These include a parallel extraction of two bytes followed by extension of each byte
to a halfword.

•

Unsigned Sum-of-Absolute-Differences (SAD) instructions. This is used in MPEG motion
estimation.

Datapath
The datapath consists of three pipelines:
•
ALU, shift and Sat pipeline
•
MAC pipeline
•
load or store pipeline, see Load Store Unit (LSU) on page 1-11.
ALU, shift or Sat pipe

The ALU, shift and Sat pipeline executes most of the ALU operations, and includes a 32-bit
barrel shifter. It consists of three pipeline stages:
Shift

The Shift stage contains the full barrel shifter. This stage performs all shifts,
including those required by the LSU.
The Shift stage implements saturating left shift that doubles the value of an
operand and saturates it.

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ALU

The ALU stage performs all arithmetic and logic operations, and generates the
condition codes for instructions that set these flags.
The ALU stage consists of a logic unit, an arithmetic unit, and a flag generator.
The pipeline logic evaluates the flag settings in parallel with the main adder in the
ALU. The flag generator is enabled only on flag-setting operations.
The ALU stage separates the carry chains of the main adder for 8-bit and 16-bit
SIMD instructions.

Sat

The Sat stage implements the saturation logic required by the various classes of
DSP instructions.

MAC pipe

The MAC pipeline executes all of the enhanced multiply, and multiply-accumulate instructions.
The MAC unit consists of a 32x16 multiplier and an accumulate unit that is configured to
calculate the sum of two 16x16 multiplies. The accumulate unit has its own dedicated single
register read port for the accumulate operand.
To minimize power consumption, the processor only clocks each of the MAC and ALU stages
when required.
Return stack
The processor includes a three-entry return stack to accelerate returns from procedure calls. For
each procedure call, the processor pushes the return address onto a hardware stack. When the
processor recognizes a procedure return, the processor pops the address held in the return stack
that the prefetch unit uses as the predicted return address.
Note
See Pipeline stages on page 1-26 for details of the pipeline stages and instruction progression.
See Chapter 3 System Control Coprocessor for system control coprocessor programming
information.

1.5.2

Load Store Unit (LSU)
The Load Store Unit (LSU) manages all load and store operations. The load-store pipeline
decouples loads and stores from the MAC and ALU pipelines.
When the processor issues LDM and STM instructions to the LSU pipeline, other instructions
run concurrently, subject to the requirements of supporting precise exceptions.

1.5.3

Prefetch unit
The prefetch unit fetches instructions from the instruction cache, Instruction TCM, or from
external memory and predicts the outcome of branches in the instruction stream.
See Chapter 5 Program Flow Prediction for more details.
Branch prediction
The core uses both static and dynamic branch prediction. All branches are predicted where the
target address is an immediate address, or fixed-offset PC-relative address.

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The first level of branch prediction is dynamic, through a 128-entry Branch Target Address
Cache (BTAC). If the PC of a branch matches an entry in the BTAC, the processor uses the
branch history and the target address to fetch the new instruction stream.
The processor might remove dynamically predicted branches from the instruction stream, and
might execute such branches in zero cycles.
If the address mappings are changed, the BTAC must be flushed. A BTAC flush instruction is
provided in the CP15 coprocessor.
The processor uses static branch prediction to manage branches not matched in the BTAC. The
static branch predictor makes a prediction based on the direction of the branches.
1.5.4

Memory system
The level-one memory system provides the core with:
•
separate instruction and data caches
•
separate instruction and data Tightly-Coupled Memories
•
64-bit datapaths throughout the memory system
•
virtually indexed, physically tagged caches
•
memory access controls and virtual memory management
•
support for four sizes of memory page
•
two-channel DMA into TCMs
•
I-fetch, D-read/write interface, compatible with multi-layer AMBA AXI
•
32-bit dedicated peripheral interface
•
export of memory attributes for second-level memory system.
The following sections describe the memory system in more detail:
•
Instruction and data caches
•
Cache power management on page 1-13
•
Instruction and data TCM on page 1-13
•
TCM DMA engine on page 1-14
•
DMA features on page 1-14
•
Memory Management Unit on page 1-14.
Instruction and data caches
The core provides separate instruction and data caches. The cache has the following features:

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Independent configuration of the instruction and data cache during synthesis to sizes
between 4KB and 64KB.

•

4-way set-associative instruction and data caches. You can lock each way independently.

•

Pseudo-random or round-robin replacement.

•

Eight word cache line length.

•

The MicroTLB entry determines whether cache lines are write-back or write-through.

•

Ability to disable each cache independently, using the system control coprocessor.

•

Data cache misses that are non-blocking. The processor supports up to three outstanding
data cache misses.

•

Streaming of sequential data from LDM and LDRD operations, and sequential instruction
fetches.
Copyright © 2004-2009 ARM Limited. All rights reserved.
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1-12

Introduction

•

Critical word first filling of the cache on a cache-miss.

•

You can implement all the cache RAM blocks, and the associated tag and valid RAM
blocks using standard ASIC RAM compilers. This ensures optimum area and
performance of your design.

•

Each cache line is marked with a Secure or Non-secure tag that defines if the line contains
Secure or Non-secure data.

Cache power management
To reduce power consumption, the core uses sequential cache operations to reduce the number
of full cache reads. If a cache read is sequential to the previous cache read, and the read is within
the same cache line, only the data RAM set that was previously read is accessed. The core does
not access tag RAM during sequential cache operations.
To reduce unnecessary power consumption additionally, the core only reads the addressed
words within a cache line at any time.
Instruction and data TCM
Because some applications might not respond well to caching, configurable memory blocks are
provided for Instruction and Data Tightly Coupled Memories (TCMs). These ensure high-speed
access to code or data.
An Instruction TCM typically holds an interrupt or exception code that the processor must
access at high speed, without any potential delay resulting from a cache miss.
A Data TCM typically holds a block of data for intensive processing, such as audio or video
processing.
You can configure each TCM to be Secure or Non-secure.
Level one memory system

You can separately configure the size of the Instruction TCM (ITCM) and the size of the Data
TCM (DTCM) to be 0KB, 4KB. 8KB, 16KB, 32KB or 64KB. For each side (ITCM and DTCM):
•

If you configure the TCM size to be 4KB you get one TCM, of 4KB, on this side.

•

If you configure the TCM size to be larger than 4KB you get two TCMs on this side, each
of half the configured size. So, for example, if you configure an ITCM size of 16KB you
get two ITCMs, each of size 8KB.

Table 1-1 lists all possible TCM configurations. See Configurable options on page 1-25 for
more information about configuring your ARM1176JZF-S implementation.
Table 1-1 TCM configurations

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Number of TCMs

Size of each TCM

0KB

4KB

8KB

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Introduction

Table 1-1 TCM configurations (continued)
Configured TCM size

Number of TCMs

Size of each TCM

16KB

8KB

32KB

16KB

64KB

32KB

The TCM can be anywhere in the memory map. The INITRAM pin enables booting from the
ITCM.
See Chapter 7 Level One Memory System for more details.
TCM DMA engine
To support use of the TCMs by data-intensive applications, the core provides two DMA
channels to transfer data to or from the Instruction or Data TCM blocks. DMA can proceed in
parallel with CPU accesses to the TCM blocks. Arbitration is on a cycle-by-cycle basis. The
DMA channels connect with the System-on-Chip (SoC) backplane through a dedicated 64-bit
AMBA AXI port.
The DMA controller is programmed using the CP15 system-control coprocessor. DMA accesses
can only be to or from the TCM, and an external memory. There is no coherency support with
the caches.
Note
Only one of the two DMA channels can be active at any time.

DMA features
The DMA controller has the following features:
•
runs in background of CPU operations
•
enables CPU priority access to TCM during DMA
•
programmed with Virtual Addresses
•
controls DMA to either the instruction or data TCM
•
allocated by a privileged process (OS)
•
software can check and monitor DMA progress
•
interrupts on DMA event
•
ability to configure each channel to transfer data between Secure TCM and Secure
external memory.
Memory Management Unit
The Memory Management Unit (MMU) has a unified Translation Lookaside Buffer (TLB) for
both instructions and data. The MMU includes a 4KB page mapping size to enable a smaller
RAM and ROM footprint for embedded systems and operating systems such as WindowsCE
that have many small mapped objects. The ARM1176JZF-S processor implements the Fast
Context Switch Extension (FCSE) and high vectors extension that are required to run Microsoft
WindowsCE. See Chapter 6 Memory Management Unit for more details.

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The MMU is responsible for protection checking, address translation, and memory attributes,
and some of these can be passed to an external level two memory system. The memory
translations are cached in MicroTLBs for each of the instruction and data caches, with a single
Main TLB backing the MicroTLBs.
The MMU has the following features:
•
matches Virtual Address, ASID, and NSTID
•
each TLB entry is marked with the NSTID
•
checks domain access permissions
•
checks memory attributes
•
translates virtual-to-physical address
•
supports four memory page sizes
•
maps accesses to cache, TCM, peripheral port, or external memory
•
hardware handles TLB misses
•
software control of TLB.
Paging

Four page sizes are supported:
•
16MB super sections
•
1MB sections
•
64KB large pages
•
4KB small pages.
Domains

Sixteen access domains are supported.
TLB

A two-level TLB structure is implemented. Eight entries in the main TLB are lockable.
Hardware TLB loading is supported, and is backwards compatible with previous versions of the
ARM architecture.
ASIDs

TLB entries can be global, or can be associated with particular processes or applications using
Application Space IDentifiers (ASIDs). ASIDs enable TLB entries to remain resident during
context switches to avoid subsequent reload of TLB entries and also enable task-aware
debugging.
NSTID

TrustZone extensions enable the system to mark each entry in the TLB as Secure or Non-secure
with the Non-secure Table IDentifier (NSTID).
System control coprocessor
Cache, TCM, and DMA operations are controlled through a dedicated coprocessor, CP15,
integrated within the core. This coprocessor provides a standard mechanism for configuring the
level one memory system, and also provides functions such as memory barrier instructions. See
System control on page 1-21 for more details.

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1.5.5

AMBA AXI interface
The bus interface provides high bandwidth connections between the processor, second level
caches, on-chip RAM, peripherals, and interfaces to external memory.
There are separate bus interfaces for:
•
instruction fetch, 64-bit data
•
data read/write, 64-bit data
•
peripheral access, 32-bit data
•
DMA, 64-bit data.
All interfaces are AMBA AXI compatible. This enables them to be merged in smaller systems.
Additional signals are provided on each port to support second-level cache.
The ports support the following bus transactions:
Instruction fetch
Servicing instruction cache misses and noncacheable instruction fetches.
Data read/write
Servicing data cache misses, hardware handled TLB misses, cache eviction and
noncacheable data reads and writes.
DMA

Servicing the DMA engine for writing and reading the TCMs. This behaves as a
single bidirectional port.

These ports enable several simultaneous outstanding transactions, providing:
•
high performance from second-level memory systems that support parallelism
•
high use of pipelined and multi-page memories such as SDRAM.
The following sections describe the AMBA AXI interface in more detail:
•
Bus clock speeds
•
Unaligned accesses
•
Mixed-endian support
•
Write buffer on page 1-17
•
Peripheral port on page 1-17.
Bus clock speeds
The bus interface ports operate synchronously to the CPU clock if IEM is not implemented.
Unaligned accesses
The core supports unaligned data access. Words and halfwords can align to any byte boundary.
This enables access to compacted data structures with no software overhead. This is useful for
multi-processor applications and reducing memory space requirements.
The Bus Interface Unit (BIU) automatically generates multiple bus cycles for unaligned
accesses.
Mixed-endian support
The core provides the option of switching between little-endian and byte invariant big endian
data access modes. This means the core can share data with big-endian systems, and improves
the way the core manages certain types of data.

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Write buffer
All memory writes take place through the write buffer. The write buffer decouples the CPU
pipeline from the system bus for external memory writes. Memory reads are checked for
dependency against the write buffer contents.
Peripheral port
The peripheral port is a 32-bit AMBA AXI interface that provides direct access to local,
Non-shared devices separately. The peripheral port does not use the main bus system. The
memory regions that these non-shared devices use are marked as Device and Non-Shared.
Accesses to these memory regions are routed to the peripheral port instead of to the data
read-write ports.
See Chapter 8 Level Two Interface for more details.
1.5.6

Coprocessor interface
The ARM1176JZF-S processor connects to external coprocessors through the coprocessor
interface. This interface supports all ARM coprocessor instructions:
•
LDC
•
LDCL
•
STC
•
STCL
•
MRC
•
MRRC
•
MCR
•
MCRR
•
CDP.
The memory system returns data for all loads to coprocessors in the order of the accesses in the
program. The processor suppresses HUM operation of the cache for coprocessor instructions.
The external coprocessor interface relies on the coprocessor executing all its instructions in
order.
Externally-connected coprocessors follow the early stages of the core pipeline to permit the
exchange of instructions and data between the two pipelines. The coprocessor runs one pipeline
stage behind the core pipeline.
To prevent the coprocessor interface introducing critical paths, wait states can be inserted in
external coprocessor operations. These wait states enable critical signals to be retimed.
The VFP unit connects to the internal coprocessor interface that has different timings and
behavior, using controlled delays for internal interconnections.
Chapter 11 Coprocessor Interface describes the interface for on-chip coprocessors such as
floating-point or other application-specific hardware acceleration units.

1.5.7

Debug
The ARM1176JZF-S core implements the ARMv6.1 Debug architecture that includes
extensions of the ARMv6 Debug architecture to support TrustZone. It introduces three levels of
debug:
•
debug everywhere
•
debug in Non-secure privileged and user, and Secure user

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Introduction

•

debug in Non-secure only.

The debug coprocessor, CP14, implements a full range of debug features that Chapter 13 Debug
and Chapter 14 Debug Test Access Port describe.
The core provides extensive support for real-time debug and performance profiling.
The following sections describe debug in more detail:
•
System performance monitoring
•
ETM interface
•
ETM trace buffer
•
Software access to trace buffer
•
Real-time debug facilities on page 1-19
•
Debug and trace Environment on page 1-19.
System performance monitoring
This is a group of counters that you can configure to monitor the operation of the processor and
memory system. See System performance monitor on page 3-10 for more details.
ETM interface
You can connect an external Embedded Trace Macrocell (ETM) unit to the processor for
real-time code tracing of the core in an embedded system.
The ETM interface collects various processor signals and drives these signals from the core. The
interface is unidirectional and runs at the full speed of the core. The ETM interface connects
directly to the external ETM unit without any additional glue logic. You can disable the ETM
interface for power saving.
For more information see:
•
the Embedded Trace Macrocell Architecture Specification
•
Chapter 15 Trace Interface Port
•
Appendix A Signal Descriptions, for details of ETM-related signals.
ETM trace buffer
You can extend the functionality of the ETM by adding an on-chip trace buffer. The trace buffer
is an on-chip memory area. The trace buffer stores trace information during capture that
otherwise passes immediately through the trace port at the operating frequency of the core.
When capture is complete the stored information can be read out at a reduced clock rate from
the trace buffer using the JTAG port of the SoC, instead of through a dedicated trace port.
This is a two-step process that avoids you implementing a wide trace port that has many
high-speed device pins. In effect, a zero-pin trace port is created where the device already has a
JTAG port and associated pins.
Software access to trace buffer
You can access buffered trace information through an APB slave-based memory-mapped
peripheral included as part of the trace buffer. You can perform internal diagnostics on a closed
system where a JTAG port is not normally brought out.

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Introduction

Real-time debug facilities
The ARM1176JZF-S processor contains an EmbeddedICE-RT logic unit that provides the
following real-time debug facilities:
•
up to six breakpoints
•
thread-aware breakpoints
•
up to two watchpoints
•
Debug Communications Channel (DCC).
The EmbeddedICE-RT logic connects directly to the core and monitors the internal address and
data buses. You can access the EmbeddedICE-RT logic in one of two ways:
•
executing CP14 instructions
•
through a JTAG-style interface and associated TAP controller.
The EmbeddedICE-RT logic supports two modes of debug operation:
Halting debug-mode
On a debug event, such as a breakpoint or watchpoint, the debug logic stops the
core and forces the core into Debug state. This enables you to examine the internal
state of the core, and the external state of the system, independently from other
system activity. When the debugging process completes, the core and system state
is restored, and normal program execution resumes.
Monitor debug-mode
On a debug event, the core generates a debug exception instead of entering Debug
state, as in Halting debug-mode. The exception entry activates a debug monitor
program that performs critical interrupt service routines to debug the processor.
The debug monitor program communicates with the debug host over the DCC.
Debug and trace Environment
Several external hardware and software tools are available for you to enable:
•
real-time debugging using the EmbeddedICE-RT logic
•
execution trace using the ETM.
1.5.8

Instruction cycle summary and interlocks
Chapter 16 Cycle Timings and Interlock Behavior describes instruction cycles and gives
examples of interlock timing.

1.5.9

Vector Floating-Point (VFP)
The VFP coprocessor supports floating point arithmetic operations and is a functional block
within the ARM1176JZF-S processor. The VFP coprocessor is mapped as coprocessor numbers
10 and 11. Software can determine whether the VFP is present by the use of the Coprocessor
Access Control Register. See c1, Coprocessor Access Control Register on page 3-51 for more
details.
The VFP implements the ARM VFPv2 floating point coprocessor instruction set. It supports
single and double-precision arithmetic on vector-vector, vector-scalar, and scalar-scalar data
sets. Vectors can consist of up to eight single-precision, or four double-precision elements.
The VFP has its own bank of 32 registers for single-precision operands that you can:
•
use in pairs for double-precision operands
•
operate loads and stores of VFP registers in parallel with arithmetic operations.

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Introduction

The VFP supports a wide range of single and double precision operations, including ABS, NEG,
COPY, MUL, MAC, DIV, and SQRT. The VFP effectively executes most of these in a single
cycle. Table 1-2 lists the exceptions. These issue latencies also apply to individual elements in
a vector operation.
Table 1-2 Double-precision VFP operations
Instruction types

Issue latency

DP MUL and MAC

2 cycle

SP DIV, SQRT

14 cycles

DP DIV, SQRT

28 cycles

All other instructions

1 cycle

Compliance with the IEEE 754 standard
The VFP supports all five floating point exceptions defined by the IEEE 754 standard:
•
invalid operation
•
divide by zero
•
overflow
•
underflow
•
inexact.
You can individually enable or disable these exception traps. If disabled, the default results
defined by IEEE 754 are returned. All rounding modes are supported, and basic single and basic
double formats are used.
For full compliance, the VFP requires support code to handle arithmetic where operands or
results are de-norms. This support code is normally installed on the Undefined instruction
exception handler.
Flush-to-zero mode
A flush-to-zero mode is provided where a default treatment of de-norms is applied. Table 1-3
lists the default behavior in flush-to-zero mode.
Table 1-3 Flush-to-zero mode
Operation

Flush-to-zero

De-norm operand(s)

Treated as 0+. Inexact flag set.

De-norm result

Returned as 0+. Inexact Flag set.

Operations not supported
The following operations are not directly supported by the VFP:
•
remainder
•
binary (decimal) conversions
•
direct comparisons between single and double-precision values.
These are normally implemented as C library functions.

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Introduction

1.5.10

System control
The control of the memory system and its associated functionality, and other system-wide
control attributes are managed through a dedicated system control coprocessor, CP15. See
System control and configuration on page 3-5 for more details.

1.5.11

Interrupt handling
Interrupt handling in the ARM1176JZF-S processor is compatible with previous ARM
architectures, but has several additional features to improve interrupt performance for real-time
applications.
The following sections describe interrupt handling in more detail:
•
Vectored Interrupt Controller port
•
Low interrupt latency configuration
•
Configuration on page 1-22
•
Exception processing enhancements on page 1-22.
Note
The nIRQ and nFIQ signals are level-sensitive and must be held LOW until a suitable interrupt
response is received from the processor.

Vectored Interrupt Controller port
The core has a dedicated port that enables an external interrupt controller, such as the ARM
Vectored Interrupt Controller (VIC), to supply a vector address along with an interrupt request
(IRQ) signal. This provides faster interrupt entry but you can disable it for compatibility with
earlier interrupt controllers.
Low interrupt latency configuration
This mode minimizes the worst-case interrupt latency of the processor, with a small reduction
in peak performance, or instructions-per-cycle. You can tune the behavior of the core to suit the
requirements of the application.
The low interrupt latency configuration disables HUM operation of the cache. In low interrupt
latency configuration, on receipt of an interrupt, the ARM1176JZF-S processor:
•
abandons any pending restartable memory operations
•
restarts memory operations on return from the interrupt.
To obtain maximum benefit from the low interrupt latency configuration, software must only use
multi-word load or store instructions that are fully restartable. The software must not use
multi-word load or store instructions on memory locations that produce side-effects for the type
of access concerned. This applies to:
ARM

LDC, all forms of LDM, LDRD, and STC, and all forms of STM and STRD.

Thumb

LDMIA, STMIA, PUSH, and POP.

To achieve optimum interrupt latency, memory locations accessed with these instructions must
not have large numbers of wait-states associated with them. To minimize the interrupt latency,
the following is recommended:
•

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multiple accesses to areas of memory marked as Device or Strongly Ordered must not be
performed

1-21

Introduction

•

access to slow areas of memory marked as Device or Strongly Ordered must not be
performed. That is, those that take many cycles in generating a response

•

SWP operations must not be performed to slow areas of memory.

Configuration
You configure the processor for low interrupt latency mode by use of the system control
coprocessor. To ensure that a change between normal and low interrupt latency configurations
is synchronized correctly, you must use software systems that only change the configuration
while interrupts are disabled.
Exception processing enhancements
The ARMv6 architecture contains several enhancements to exception processing, to reduce
interrupt handler entry and exit time:
SRS
Save return state to a specified stack frame.
RFE
Return from exception.
CPS
Directly modify the CPSR.
Note
With TrustZone, in Non-secure state, specifying Secure Monitor mode in the field of the
SRS instruction causes the processor to take the Undefined exception.

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Introduction

1.6

Power management
The ARM1176JZF-S processor includes several micro-architectural features to reduce energy
consumption:
•

Accurate branch and return prediction, reducing the number of incorrect instruction fetch
and decode operations.

•

Use of physically tagged caches that reduce the number of cache flushes and refills, to
save energy in the system.

•

The use of MicroTLBs reduces the power consumed in translation and protection
look-ups for each memory access.

•

The caches use sequential access information to reduce the number of accesses to the Tag
RAMs and to unmatched data RAMs.

•

Extensive use of gated clocks and gates to disable inputs to unused functional blocks.
Because of this, only the logic actively in use to perform a calculation consumes any
dynamic power.

•

Optionally supports IEM. The ARM1176JZF-S is separated into three different blocks to
support three different power domains:
—

all the RAMS

—

the core logic that is clocked by CLKIN and FREECLKIN

—

four optional IEM Register Slices to have an asynchronous interface between the
Level 2 ports powered by VCore and clocked by CLKIN, and the AXI system
powered by VSoc and clocked by ACLK clocks, one for each port.

The ARM1176JZF-S processor support four levels of power management:
Run mode

This mode is the normal mode of operation when the processor can use all its
functions.

Standby mode
This mode disables most of the processor clocks of the device, while processor
remains powered up. This reduces the power drawn to the static leakage current,
plus a tiny clock power overhead required to enable the processor to wake up from
the standby state. One of the following events cause a transition from the standby
mode to the run mode:
•

an interrupt, either masked or unmasked

•

a debug request, regardless of whether debug is enabled

•

reset.

Shutdown mode
This mode powers down the entire processor. The processor must save all states,
including cache and TCM state, externally. The processor is returned to the run
state by the assertion of reset. The processor saves the states with interrupts
disabled, and finishes with a Data Synchronization Barrier operation. The
ARM1176JZF-S processor then communicates with the power controller that it is
ready to be powered down.

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1-23

Introduction

Dormant mode
This mode powers down the processor and leaves the caches and the TCM
powered up and maintaining their state. The valid bits remain visible to software
to enable you to implement dormant mode. For full implementation of dormant
mode you must:
•

modify the RAM blocks to include an input clamp

•

implement separate power domains.

For full implementation of dormant mode see ARM1176JZF-S and ARM1176JZ-S
Implementation Guide.
For more details of power management features see Chapter 10 Power Control.

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1-24

Introduction

1.7

Configurable options
Note
These options are configurable features of your ARM1176JZF-S processor implementation.
They are not programmable options of the implemented device.
Table 1-4 lists the ARM1176JZF-S processor configurable options.
Table 1-4 Configurable options
Feature

Range of options

IEM support

Yes or No

Cache way size

1KB, 2KB, 4KB, 8KB, or 16KB

Number of cache ways

4, not configurable

TCM block size

4KB, 8KB, 16KB, or 32KB

Number of TCM blocks

0, or auto-configures a to 1, or 2

a. Number of TCM blocks depends only on the size of the
TCM RAM.

In addition, the form of the BIST solution for the RAM blocks in the ARM1176JZF-S design is
determined when the processor is implemented. For details, see the ARM11 Memory Built-In
Self Test Controller Technical Reference Manual.
Table 1-5 lists the default configuration of ARM1176JZF-S processor.
Table 1-5 ARM1176JZF-S processor default configurations

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Feature

Default value

IEM support

Cache way size

4KB

Number of cache ways

TCM block size

8KB

Number of TCM blocks

1-25

Introduction

1.8

Pipeline stages
Figure 1-2 shows:
•
the two Fetch stages
•
a Decode stage
•
an Issue stage
•
the four stages of the ARM1176JZF-S integer execution pipeline.
These eight stages make up the processor pipeline.
Fe1

Fe2

Iss

ALU

Sat

WBex

1st fetch
stage

2nd fetch
stage

Instruction
decode

Reg. read
and issue

Shifter
stage

ALU
operation

Saturation
stage

Writeback
Mul/ALU

MAC1

MAC2

MAC3

1st multiply
acc. stage

2nd multiply
acc. stage

3rd multiply
acc. stage

ADD

DC1

DC2

WBls

Address
generation

Data
cache 1

Data
cache 2

Writeback
from LSU

Figure 1-2 ARM1176JZF-S pipeline stages

From Figure 1-2, the pipeline operations are:
Fe1

First stage of instruction fetch where address is issued to memory and data returns
from memory

Fe2

Second stage of instruction fetch and branch prediction.

Instruction decode.

Iss

Shifter stage.

ALU

Main integer operation calculation.

Sat

Pipeline stage to enable saturation of integer results.

WBex

Write back of data from the multiply or main execution pipelines.

MAC1

First stage of the multiply-accumulate pipeline.

MAC2

Second stage of the multiply-accumulate pipeline.

MAC3

Third stage of the multiply-accumulate pipeline.

ADD

Address generation stage.

DC1

First stage of data cache access.

DC2

Second stage of data cache access.

WBls

Write back of data from the Load Store Unit.

By overlapping the various stages of operation, the ARM1176JZF-S processor maximizes the
clock rate achievable to execute each instruction. It delivers a throughput approaching one
instruction for each cycle.

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1-26

Introduction

The Fetch stages can hold up to four instructions, where branch prediction is performed on
instructions ahead of execution of earlier instructions.
The Issue and Decode stages can contain any instruction in parallel with a predicted branch.
The Execute, Memory, and Write stages can contain a predicted branch, an ALU or multiply
instruction, a load/store multiple instruction, and a coprocessor instruction in parallel execution.

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1-27

Introduction

1.9

Typical pipeline operations
Figure 1-3 shows all the operations in each of the pipeline stages in the ALU pipeline, the
load/store pipeline, and the HUM buffers.
Ex1
Sh

Ex2
ALU

Ex3
Sat

Fe1

Fe2

Iss

Shifter
operation

Calculate
writeback
value

Saturation

WBex

1st fetch
stage

2nd fetch
stage

Instruction
decode

MAC1

MAC2

MAC3

Base
register
writeback

1st
multiply
stage

2nd
multiply
stage

3rd
multiply
stage

ALU
pipeline

Multiply
pipeline

Common decode pipeline
ADD

DC1

DC2

WBls

Data
address
calculation

First stage
of data
cache
access

Second
stage of
data cache
access

Writeback
from LSU

Load/store
pipeline

Hit under
miss

Load miss
waits

Figure 1-3 Typical operations in pipeline stages

Figure 1-4 shows a typical ALU data processing instruction. The processor does not use the
load/store pipeline or the HUM buffer.
Ex1
Sh

Ex2
ALU

Ex3
Sat

Fe1

Fe2

Iss

Shifter
operation

Calculate
writeback
value

Saturation

WBex

1st fetch
stage

2nd fetch
stage

Instruction
decode

MAC1

MAC2

MAC3

Base
register
writeback

Not used

ADD

DC1

DC2

WBls

Not used

ALU
pipeline

Multiply
pipeline

Common decode pipeline

Not used

Load/store
pipeline

Hit under
miss

Figure 1-4 Typical ALU operation

Figure 1-5 on page 1-29 shows a typical multiply operation. The MUL instruction can loop in
the MAC1 stage until it has passed through the first part of the multiplier array enough times.
The MUL instruction progresses to MAC2 and MAC3 where it passes through the second half
of the array once to produce the final result.

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1-28

Introduction

Ex1
Sh

Ex2
ALU

Ex3
Sat

Fe1

Fe2

Iss

Not used

WBex

1st fetch
stage

2nd fetch
stage

Instruction
decode

MAC1

MAC2

MAC3

Base
register
writeback

1st
multiply
stage

2nd
multiply
stage

3rd
multiply
stage

ADD

DC1

DC2

WBls

Not used

ALU
pipeline

Multiply
pipeline

Common decode pipeline

Load/store
pipeline

Hit under
miss

Not used

Figure 1-5 Typical multiply operation

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1-29

Introduction

1.9.1

Instruction progression
Figure 1-6 shows an LDR/STR operation that hits in the data cache.
Ex1
Sh

Ex2
ALU

Ex3
Sat

Fe1

Fe2

Iss

Shifter
operation

Calculate
writeback
value

Saturation

WBex

1st fetch
stage

2nd fetch
stage

Instruction
decode

MAC1

MAC2

MAC3

Base
register
writeback

Not used

ALU
pipeline

Multiply
pipeline

Common decode pipeline
ADD

DC1

DC2

WBls

Data
address
calculation

First stage
of data
cache
access

Second
stage of
data cache
access

Writeback
from LSU

Load/store
pipeline

Hit under
miss

Not used

Figure 1-6 Progression of an LDR/STR operation

Figure 1-7 shows the progression of an LDM/STM operation that completes by use of the
load/store pipeline. Other instructions can use the ALU pipeline at the same time as the
LDM/STM completes in the load/store pipeline.
Ex1
Sh

Ex2
ALU

Ex3
Sat

Fe1

Fe2

Iss

Shifter
operation

Calculate
writeback
value

Saturation

WBex

1st fetch
stage

2nd fetch
stage

Instruction
decode

MAC1

MAC2

MAC3

Base
register
writeback

Not used

ALU
pipeline

Multiply
pipeline

Common decode pipeline
ADD

DC1

DC2

WBls

Data
address
calculation

First stage
of data
cache
access

Second
stage of
data cache
access

Writeback
from LSU

Not used
unless a
miss
occurs

Load/store
pipeline

Hit under
miss

Figure 1-7 Progression of an LDM/STM operation

Figure 1-8 on page 1-31 shows the progression of an LDR that misses. When the LDR is in the
HUM buffers, other instructions, including independent loads that hit in the cache, can run under
it.

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1-30

Introduction

Ex1
Sh 5
Fe1 1
1st fetch
stage

Fe2 2
2nd fetch
stage

Instruction
decode

Iss
Register
read and
instruction
issue

Ex2
ALU 6

Ex3
Sat 7

Shifter
operation

Calculate
writeback
value

Saturation

MAC1

MAC2

MAC3

Not used

WBex 8

ALU
pipeline

Base
register
writeback

Multiply
pipeline

Common decode pipeline
ADD 5
Data
address
calculation

DC1 6
First stage
of data
cache
access

DC2 11
Second
stage of
data cache
access

WBls 12
Writeback
from LSU

Load/store
pipeline

9,10
Load

Hit under
miss

Figure 1-8 Progression of an LDR that misses

See Chapter 16 Cycle Timings and Interlock Behavior for details of instruction cycle timings.

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1-31

Introduction

1.10

ARM1176JZF-S instruction set summary
This section provides:
•
an Extended ARM instruction set summary on page 1-33
•
a Thumb instruction set summary on page 1-44.
Table 1-6 lists a key to the ARM and Thumb instruction set tables.
The ARM1176JZF-S processor implements the ARM architecture v6 with ARM Jazelle
technology. For a description of the ARM and Thumb instruction sets, see the ARM Architecture
Reference Manual. Contact ARM Limited for complete descriptions of all instruction sets.
Table 1-6 Key to instruction set tables
Symbol

Description

{!}

Update base register after operation if ! present.

{^}

For all STMs and LDMs that do not load the PC, stores or restores the User mode banked registers
instead of the current mode registers if ^ present, and sets the S bit. For LDMs that load the PC,
indicates that the CPSR is loaded from the SPSR.

Byte operation.

Halfword operation.

Forces execution to be handled as having User mode privilege. Cannot be used with pre-indexed
addresses.

Selects HIGH or LOW 16 bits of register Rm. T selects the HIGH 16 bits,
T = top, and B selects the LOW 16 bits, B = bottom.

Selects HIGH or LOW 16 bits of register Rs. T selects the HIGH 16 bits,
T = top, and B selects the LOW 16 bits, B = bottom.

{cond}

Updates condition flags if cond present. See Table 1-15 on page 1-43.

{field}

See Table 1-14 on page 1-43.

{S}

Sets condition codes, optional.

See Table 1-8 on page 1-40.

See Table 1-9 on page 1-41.

See Table 1-10 on page 1-42.

See Table 1-11 on page 1-42.

See Table 1-12 on page 1-42.

One of the coprocessors p0 to p15.

Specifies the effect required on the interrupt disable bits, A, I, and F in the CPSR:
IE = Interrupt enable
ID = Interrupt disable.
specifies the bits affected if is specified.

BE = Set E bit in instruction, set CPSR E bit.
LE = Reset E bit in instruction, clear CPSR E bit.

Specifies a register in the range R8 to R15.

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1-32

Introduction

Table 1-6 Key to instruction set tables (continued)

1.10.1

Symbol

Description

A sequence of one or more of the following:
a = Set A bit.
i = Set I bit.
f = Set F bit.
If is specified, the sequence determines the interrupt flags that are affected.

A 10-bit constant, formed by left-shifting an 8-bit value by two bits.

An 8-bit constant.

A 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits.

The target address to branch to.

Specifies a register in the range R0 to R7.

The new mode number for a mode change. See Mode bits on page 2-28.

Specify, in a coprocessor-specific manner, the coprocessor operation to perform.

See Table 1-13 on page 1-43.

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Author : ARM Limited
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Subject : Technical Reference Manual for ARM1176JZF-S processor. The processor provides TrustZone security extensions. It supports the ARM and Thumb instruction sets with SIMD DSP instructions, and implements Jazelle technology to provide direct execution of Java bytecodes. The processor includes A VFP unit.
Keywords : ARM1176JZF-S, ARM1176, TRM, macrocell, "ARM instruction", Thumb, SIMD, "virtual memory", MMU, VFP, "Thumb instruction", TrustZone, security, "Intelligent Energy Management", IEM, AMBA, AXI
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Description : Technical Reference Manual for ARM1176JZF-S processor. The processor provides TrustZone security extensions. It supports the ARM and Thumb instruction sets with SIMD DSP instructions, and implements Jazelle technology to provide direct execution of Java bytecodes. The processor includes A VFP unit.
Title : ARM1176JZF-S Technical Reference Manual
Creator : ARM Limited
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