Atari 2600 TIA Technical Manual Text

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TIA lA
TrJ-EV:SIOK INTERFACE ADAPTOH (MODEL lA)

GJ:NtR>.L D SSCP.IPTXON

The TIAIA is an HOS integrated circuit designed to interface between an eight (8) bit microprocessor and a television
video ibodulator and to convert eight (8) bit parallel data into
serial outputs for the color, Ivuninosity , and composite syT\C
required by a video modulator.
This circuit operates on a •line by line" basis, always
oiitputing the saine infonnation every television line unless new
data is written into it by the microprocessor.
A hardware sync counter produces horizontal sync timing
independent of the microprocessor.
Vertical sync timing is supplied
and combined into composite
microprocessor
to this circuit by the
sync.

Horizontal position counters are used to trigger the serial
output of five (5) horizontally moveable objects; two players,
The XLicroprocessor can add or subtwo*niissiles;anc a ball.
tract from these position counters to move these objects right
or left.
The microprocessor determines all vertical position and
motion by vritinc zeros or ones into object registers before
each appropriate horizontal line.
Kails, clouds and other seldom moved objects are produced
bv a low resolution data register called the playfield register.
A fifteen (15) bit collision register detects all fifteen
Dossible two object collisions between these six (6) objects
This collision register
"(five moveable and one playfield) •
can be read and reset by the microprocessor. Six input ports
are also provided on this chip that can be read by the j&icroprocessor. These input ports and the collision register are
the only chip addresses that can be read by the microprocessor.
All other addresses are vuitire only.
Color luminosity registers are included that can be prograimned by the microprocessor with eight (8) luminosity and
fifteen (15) color values. A digital phase shifter is included
on this chip to provide a single color output with fifteen (15)
phase angles
Two (2) independent audio generating circuits are included,
each with programmable frequency, noise content, and volume
control registers.

DKTAIL DE SCRIPTION
1,

Data and addressinc

Aecisters on this chip are addressed by the microprocessor as part of its overall RAM- ROM iaeDor%* space.
The attached taJDle of read-write addresses svinMri^es
the addressable functions. There are no registers
that are both read and write. Some addresses however are both read and write, with write data 50ing
into one register and read data returning fron a
different register.
If the read-write line is low, the data bits indicated
in this table will be written into the addressed
write locotion when the^2 clock goes from high to
Soae registers arc eight bits wide, sose only
lew.
one bit, ar some (strobes) have no bits, perforitdng
only control functions (such as resets) when their
address is written.
If the read-write line is high, the addressed location
can be read by the niicroprocessor on data lines 6 and
7 while they line, allowing
the microprocessor to begin its conput&tior. and
register writing for this horizontal television
line or line pair.

vfield crachics R egister

Description
Objects, (such as walls, clouds, and score) which
are not recuired to move, are written into a 20
bit register called the playfield register. This
reoister (Figure 5) is loaded from the data bus
(PFO, PFl, PF2)
bv'three separate write addresses
Playfield may be loaded at any time. To clear
the playfield, zeros must be written into all
three addresses.

Normal Serial Output
The playfield reoister is automatically scanned
(and converted to serial output) by a bi-direct_
ional shift register clocked at a rate which spreacs
the twenty (20) bits out over the left half of
This scanning is initiated
a horizontal line.
by the end of horizontal blank (left edge of teleNormally the same scan is then
vision screen)
repeated, duplicating the same twenty (20) bit
sequence over the right half of the horizontal
line.
.

Reflected Serial. Output

A relected playfield may be requested by writing

a one into bit zero of the playf ield control register (CTRLPF) • When this bit is true the
scanning shift register will scan the opposite
direction during the right half of the horizontal line, reversing the twenty (20) bit sequence.
p.

Timing Constraints

tven though the playfield bytes (PFO,
&ay be written at any tiae, if one of
changed while being serially scanned,
the new value nay both show up on the
horizontal line.
4

•

PFl, PF2)
then is
part of

television

Eojrizon tal Position Counters
•

D_e_scrip tion

The plavfield is a 'fijced* t./aphics register,
always starting its serial output when triggered
by the becinning of each television line.
This chip'also includes five "moveable" graphics
recisters, whose serial outputs are triggered
by' five separate horizontal position counters
every tice these coiinters pass through zero
count* These position counters «re clocXed
continuously during the unblanke portion of
every horizontal line and their counr length
is exactly ecual to the normal nusiber of clocks
supplied to the-n during this tisve. They will
therefore pass throxigh zero at the sane time
du ing each horizontal television line and the
triogered outputs will have no horizontal
motion. A typical horizontal counter is shown
in ficure 4.
If extra clocks are supplied to these counters
(or normal clocks s'orpressed) the zero crossing
time will shift and he object will have moved
left (extra clocks) or right (fewer Clocks)
Sor.e position counters have extra decodes
(in addition to a zero decode) to trigger multiple
copies of the same object across a horizontal
line*
All position counters can be reset to zero count
by the microprocessor at any tijne, by a write
instruction to the reset addresses (RESBL, RESMO,
RESHl, RESPOr RESPl) . If reset occurs during
horizontal blank, the object will appear at
the left side of the televisioa screea^. Properly timed resets may position an object,
at any horizontal location consistent with the
microprocessor cycle time*
B:. .r.Ball

Position Counter

The ball position counter has only the zero

crossing decode and therefore cannot trigcer
multiple copies o£ the ball graphics.
C* Play e r Position Counters

Each player position counter has three decodes
in addition to the zero crossing decode. Th*se
decodes are controlled by bits 0,1,2 of the
r ainher size control registers (NUSIZO, KU5I21)
and trigger 1,2, or 3 copies of the player
{at various spacings) across a horizontal line
These sasie control bits
as shown on page ^O
are used for the Hecodes on the aissile position
counter, insuring an equal number of players
and cissiles.
,

"

.

'

D. Missije Po s ition Counters

Missile position counters are identical to
player positon counters except that they have
another* type of reset in addition to the previously discussed horizontal position reset.
RESHPl)
These extra reset addresses
write data bit 1 into a one bit register vbose
output is used to position the missile (horizontally) directly on top of its corresponding
player, and to disable the missile serial output.
£,

Horizontal Motion Recisters
A. General Description

There sure five write only registers on this
chip that contain the horizontal motion values
for each of the five moving objects. A typical
horizontal motion register is shewn in figure
The data bus (bits4 through? ) is written
4. .
into these addresses (KMPO, HKPl, HMMO,
Hml, HMBL) to load these registers with motion
values. These registers supply extra (or
fewer) clocks to the horizontal position counters
only when commanded to do so by an HMOVZ
address from the microprocessor. These registers cay all be cleared to zero (no mc.ionl
sijaultaneously by an HMCLR command
from the microprocessor, or individually by
loading zeros into each register*
These registers are each foxir bits in length
and may be loaded with positive (left notion)
negative (right motion) or zero (no motion)
values. Negative values are represented
in twos complement format.

D. Tij

.Lng

Constraints

These registers nay be loaded or cleared atalxaost
any tine. The ro.Dtion. values they contain will
be used only when aji EHOVT conixand is addressed,
£md then all five notion values will be used
simultaneously into all five horizontal position
counters once* The only tixcdng constraint on
this operation involves the EHOVE conniand.
The EKOVE cotocand must be located in the nicroprocessor progr^.'a imcdiately after a wait
for sync (WSYKC) cor^sand. This insures that
the EHOVE operation begins at the leading edge
of horizont9».l blainJ:, stnd has the full blaiiX
tine to supply extra or fever clocks to the
horizontal* position counters* Ibese reglsttrs should
^*

not bt aodifled for at least 26 CoLiputer cycles after the
EH?ve cotriar*d.
Hovin g Objec t Graphi cs Registers

A. General D e script ion

There are five graphics registers for noving
objects on this chip. These graphics registers
are loaded (written) in parallel by the niicroprocessor and like the playfield register
are scanned and converted to serial output,
CnliXe the playfield register, which is always
scanned beginning at the left side of each horizontal line, moving object graphics registers
are scanned only when triggered by a start
decode fron their horizontal position counter.
craohics register is shows in figure
A tyoical
'
4

B. Missile Graphics

The graphics registers for both nissiles are
identical and very simple. They each consist
of a one bit register called nissile enable
This graphics bit is scanned
(EKAMOi ENAMI) .
triggered by its correwhen
(outputed) only
sponding position counter. There are control
bits (bits AfS, of NUSIZO, KUSI21) that can
stretch this single graphics bit out over
widths of 1, 2, 4, or 8 clocks of horizontal
(A full line is 160 clocks!
line tine.
C. Player Graphics

The graphics registers for both players are
identical and are rather conplex. They each
consist of eight bit parallel, registers (GRPO,
GRPl) and a bi-directional parallel to serial

scan coujiter that converts the parallel data
into serial output.
A one bit control register (RZFPO, KEFPl) ceterniines the direction (reflection) of the
parallel to serial scan, outputicg either
D7 throuch DO, or DO through D7, This allows
reflection (horizontal flipping) of player
serial graphics data without having to flip
tl^e microprocessor data.
The clocJc into the scan counter caii be controlled
(three bits of KUSIZO and NUSIZl) to slow
the scan rate and stretch the eight bits of
serial Graphics out over widths of 5, 16,
or 32 clocks of horizontal line time* These
sajse control bits are used in the player-^
missile motion counters to control multiple
copies, so only three player widths (scan
rates) are available.

Vertical Delav

,

Each of the player graphics registers actually
consists of two 8 bit .pjiraliel registers.
The first (GRPO, GRPl) is loaded (written)
fron the microprocessor 8 bit data bus. The
second is autoinatically loaded from the cutout of the first. The reason for this is a
complex subject called vertical delay.
A large aioount of microprocessor tiae is re*
quired to generate player, missile and playfield graphics (table look up, mas)cing,
con;parisons,-ect.) and load these into this
chip's registers. For most game programs this
tijoe is just too lajrge to fit into one horizontal
In fact for most games it will
line time.
barely fit into two line times (127 microseconds)
Therefore, individual graphics registers are
loaded (written) every two lines, arid used
twice for serial output between loads.
This type of programming will obviously licit
the vertical height resolution of objects
It also will
to multiples of two lines.
motion to
vertical
of
resolution
the
limit
jumps.
two lines
Nothing can be done about the vertical
heioht resolution; however, vertical motion
can'be resolved to a single line by addition
of a second graphics register that is automatically parallel loaded from the output
of the first, one line time after the first
was loaded from the data bus. This second graphics
reoister output is therefore always delayed
vertically by one line. A control bit called

vertical delay (VDELO, VDELl) selects which
of these two registers is to be used for
If this control bit is set
serial output.
by the microprocessor between picture franes
the object will be moved ^dcvn (delayed) by
one line ouxinc the next frame.
In most prograjrming applications player
graphics and player 1 graphics are loaded
(written) alternately, during the blanX time
just prior to each line as shown in (figure 1)
Since GPJ^O and GHPl addresses from the microprocessor alternate, they are delayed by
one line from each other. The GRPO address
decode can therefore be used to load the delayed graphics register for player 1, and
GRPl likewise to load the delayed graphics
register for player 0. The two vertical delay bats (VDELO, VBELl) then select delayed
ana
or'undelayed registers for player
player 1 as serial outputs,
^

•

Ball G raphics
The ball graphics register is almost identical
It also
to the r;issiie graphics register.
consist?, of a single enable bit (EJiASL) whose
output is triggered by the ball position counter.
It also has two control bits (bits 4, 5 of
CTRLPF) that can stretch this single graphics
bit out over widths of 1, 2, 4, or 8 clocks
of horizontal line time.
Unlike the missile graphics, however, the
ball graphics register has capability for
vertical delay similar to the player graphics,
A second graphics (enable) bit is alternately
loaded from the output of the first, one
line after the first was loaded from the data
bus.
A ball vertical delay bit {VDZLBD selects which of these two graphics bits is
used for the ball serial output. The first
graphics bit (ENABL) should be loaded during the
(GRPO), be
sane horizontal blank tiroe as player.
cause GrlPl is used to* load the second enable
bit from the output of the first on alternate
lines.

7

*

Collision Detection
A.

I/at'ches

Definitions
The serial outputs from all the graphics registers represent real time horizontal location
If any
of objects on the television screen.
of these outputs occur at the same time,
^

they vill overlap (colHde) on the screen. There are six objects
generated on this chip -'five noving and playfield ellowing
fifteen possible tvo object collisions. These overlaps (collisions)
are detected by fifteen "and" gates whenever they occur, aftd
figur
are stored in fifteen individual latch register bits, as shown in
£.

E•

^ e.^din'o

Collision

:-

The laicroprocessor can read these fifteen collision bits on
d^ta lines 6 and 7 by addressing the:n tvo at a time. This
could be done at any time but is usually done between frames
{curing vertical blank) after all possible collisions have serially
occured.
C.

R eset

All collision bits are reset simultaneously by the microprocessor
using the reset address CXCLR. This is usually done near the
end of vertical blsnW, after collisions have been tested.

Input ports
A.

General Description
r.ay be
There are 6 input ports on this chip whose logic state
1NPT5.
read on data line 7 with read addresses INPTO through
''latched'
These 6 ports are divided into two types, "dumped" and
See figure 6.

B,

Du rToed Input Ports

'.10

through 13)

position from
Thes- ii input ports are normally used to read paddle
to discharge
order
In
circuit.
an external potentiometer-capacitor
transistor,
large
a
has
these capacitors each of these input ports
into
writing
vhich may be turned on grounding the input ports) by
the
cleared
bit is
bit 7 of the register VBLAS'K. Vhen this control
potentimeters begin to recharge the capacitors and the microprocessor
por^.
measures the time requirfed to detect a logic 1 at each input
ports
long as bit 7 of register VBLASX is zero, these four
When this bit is a
are general purpose high inpedance input ports.
1 these ports are grounded.
C.

Latched Input ports (14, 15)

enabled or disabled
These two input ports have latches which can be
VBLAKK.
by writing into bit 6 of register
coropletly
When disabled, these latches are removed from the circuit
ports, whose
and these ports become two general purpose input
microprocessor.
the
by
directly
present logic state can be read

zero logic level)
When enabled, these latches will store negative
the input por^
signals appearing on these tvo input ports, and
ports.
input
the
of
instead
addresses will read the latches

latched Input Ports (lA, 15) * continued
Vhen first enabled these latches vill remain positive as
long as the input ports remain positive (logic one;. A
zero input port signal vill clear a latch value to zero,
where it vill remsin (even after the port returns positive 5
until disabled. Both latches cay be sirultaneously
disabled by writing a zero into bit $ of register VBLANK.

i

Priority Encoder
A.

Purpose
As discussed in the section on collisions,
simultaneous serial outputs from the graphics
registers reoresent overlap on the television
screen. In order to have color-luminosity
values assigned to individual objects it is
necessarv ro establish priorities between
objects when overlapped. The priority encoder
is shown in figure 3*

B.

Priority Assicnnent
The lack of any objects results in a color-lu=
value called the backorounc. The background
when
(BK) has lowest priority and only appears
sinpli^y
to
order
In
no objects e.re outputing.
the logic each missile is given the sane colorluB value and priority as it's corresponding
plaver (PO, MO) and the ball is given the sane
color-lum value and priority as the playfield
(PF /

BXi)

.

priority
The 'following table illustrates the normal
assignment:
^«
PO, KO
Hichest Priority
Pl# Ml
Second Highest
PF, BL
Third Highest
BK
Lowest Priority
to
appear
will
priority
Objects with higher
priority.
lower
with
move in front of objects
Players will therefore move in front of playfielc
(clouds, walls, etc.).
C,

priority Control
There are two playfield control bits that affect
priority, one called playfield priority (PFP) (bit 2 o*
CTRLPF) and one called s .:ore (bit 1 of CTBLPF)
When a one is written into the PFP bit the priority
assignment is modified as shown below.
PF, BL
Highest Priority
PO, MO
Hiohest
Second
Pi/ Ml
Third Highest
BK
Lowest Priority

Players will then move behind playfield (clouds
vail etc.)
When a one is written into the score control
bit, the playfield is forced to take the colorin the left half of the screen
lura of player
and player 1 in the right half of the screen.
This is* used when displaying score and identifi-es
the score with the correct player.
The prioritv enco der produces 4 register select
lines (shown in figure 3) that arc mutnally
exclusive. These 4 lines select either bachgroxind, p' ayer 0, player 1 or playfield, and
only one' of" them can be true at a time.
I

5

•

Co1o

A

,

Lumin^.r.ce l^egisters

Desc ription
There are four registers (shown in figure 3) that
contain color-lum codes* Tour bits of color
code and three bits of luainance code may be
written into each of these registers (COLUPO,
COL0P1, COLUPF, COLUBK> by the microprocessor
These co!es (representing 16 color
at any tirse.
values and 8 luminance values) are given in
the Detailed Address List.

3.

Multiplexing
The serial graphics output from all six objects
is examined by" the priority encoder which
activates one of the four select lines into
This multiplexer (shown
a 4 X 7 multiplexer.
in figure 3) then selects one of the four color
luE registers as a 7 line output. Three
of these lines are binary coded luminosity and
go directly to chip output pads. The other
four lines go to the color phase shifter.

10.

Color Phase Shifter
This portion of the chip (shown in figure 3) produces
a reference color output (color burst) during horizontal hl&Tik and then during the unblanked portion
of the line it produces a color output shifted
in phase with respect to the color burst.- The
The amount of phase shift determines the color and
is selected by the four color code lines from the
selects no
Color-lum multiplexer. Binary code
phase
as color
(same
gold
selects
color. Code 1
shift
(1111)
15
through
burst) . Codes 2 (0010)
degrees
360
almost
the phase from zero through
allowing selection of 15 total colors around the
television color wheel.

Ay Uo.\Circuits

Two audio circuits are incorporated on this chip*
Thev are identical and completely independent, although their outputs could be combined externally
into one speaker. Each audio circuit consists of
parts described below, and in figure 7.
A.

Frecuency Select

Clock pulses (at apprcy.iffiately 30 KHZJ fron
the horizontal sync coxinter pass through a
•divide by N" circuit which is controlled
bv the output code from a five bit frequency
register (AUDF) . This register can be loaded
(written) by the rucroprocessor at any tiae,
and causes the 30 KHZ clocks to be divided
bv 1 (code 00000) through 32. (code 11111)
This produces pulses that are digitally adjustable froa approxinately 30 KHZ to 1 KE2
and are used to clock the noise- tone generator.
B.

N oise-Tone Generator

This circuit contains a nine bit shift counter
which nay be controlled by the ouput code frczi
a four bit audio control register (AUDC)
and is clocked by the frequency select circuit.
The control register can be loaded by the mcroprocessor at any time, and selects different
shift counter feedback taps and count lengths
to produce a variety of noise and tone qualities.
C.

V oluce Select
The shift counter ouput is used to drive the
audio output pad through four driver transistors
graduated in size. Each transistor
that
is twice as large as the previous one and
is enabled by one bit frora the audio volune
register (AUDV) . This audio volume register^
nay be loaded by the microprocessor at any tine.
through 15 are loaded, the
As binary codes
pad drive transistors are enabled in a binary
sequence. The shift counter output therefore
can pull down on the audio ouput pad with 16
selectable impedance levels.

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SARA PPnnRAMMING INSTRUCTIONS

VCS
Sara is a 128 by 8 RAM that is Memory mapped into the
FOOD
are
addresses
write
RAM
FFFF)
to
cartridee slot (FOOD
read
RAM
The
FOFF.
to
are
F080
addresses
RAM read
to F07F
space.
and write adresses over ride the ROM in that address storage
data
i.e..
space
program
as
used
Sara RAM cannot be
only.
.

address
Accessing Sara can be done by most instructions with,
by
indexed
^^solute
absolute, absolute indexed by X
modes:
exceptions
The
by
Y.
Y, indexed indirect, or indirect indexed
RAM, modify
are any instruction that required the 6507 to read
in the
Also
memory.
into
the data, and write that data back
a page
cross
cannot
index
the
indexing modes, the address plus
bytes.
256
is
size
boundry, where a page boundry

VCS CARTRIDGE MEMORY MAP

FFFF

ROM

FlOO
FOFF
F080

RAM Read

F07F
FOOO

RAM Write



---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.5
Linearized                      : Yes
Page Layout                     : TwoPageRight
Page Count                      : 38
XMP Toolkit                     : XMP Core 4.1.1
Metadata Date                   : 2013:09:25 05:54:18Z
Create Date                     : 2013:09:25 05:49:21Z
Modify Date                     : 2013:09:25 05:54:18Z
Creator Tool                    : Digitized by the Internet Archive
Producer                        : Recoded by LuraDocument PDF v2.60
Part                            : 2
Conformance                     : B
Document ID                     : uuid:uuid:97a7c828-b8da-62eb-c235-cd87285d35d0
Version ID                      : 2
Title                           : Atari 2600 TIA Technical Manual
Creator                         : Digitized by the Internet Archive
Keywords                        : http://archive.org/details/Atari_2600_TIA_Technical_Manual

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