COMPAL LA 4481P

User Manual:

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A

B

C

D

E

1

/x
/

1

su

Compal confidential

2

om

p.

2

yc

Schematics Document

//
m

Calypso 13.3"
Mobile AMD S1G2 CPU with ATI
3

RS780M(NB) & SB700(SB) core logic
3

tp
:

2008-09-04

ht

LA-4481P REV:0.4

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Cover Sheet
Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

1

of

46

A

B

C

D

E

Compal Confidential

Consumer AMD 13.3" UMA - Sally
Thermal Sensor
ADM1032ARMZ

Accelerometer
ST LIS302DLTR

1

AMD S1G2 CPU

Page 7

Page 31

Fan conn

72QFN

DDR2-SO-DIMM X2

DDR2 800MHz 1.8V

BANK 0, 1, 2, 3

Dual Channel

638-PIN uFCPGA 638

1

Clock Generator
SLG8SP626VTR

Page 9, 10

Page 16

Page 5
Page 5, 6, 7, 8

Hyper Transport Link
16X16

ATI RS780M

18

su

CRT

A-Link Express II

Page 19

4X PCI-E

WLAN
Page 27

RJ45/11 CONN

3

om

Page 27

ht

LED
P35

CardReader
RTS5158E-GR_LQFP48

Page 32

2

Mini-Card WLAN

Page 27

Azalia (HDA I/F)

CardReader Socket

USB WebCam

SATA Master-1

Page 28

Page 18

SATA Master-2
SATA Slave

FingerPrinter AES1610
USBx1
page 32

SATA Slave

Page 20, 21, 22, 23, 24

tp
:

Page 26

Express Card

//
m

Mini-Card*1

yc

ATI SB700
Page 26

Page 32

Page 28

USB2.0 X12

PCI-E BUS*3

Page 28

USB conn x2
e-SATA Combo
BT Conn

p.

HDMI

Realtek
8111C(GLAN)

Page 13

Page 10, 11, 12, 13, 14

Page 17

2

DDR2 400MHz

/x
/

LVDS Panel
Interface Page

Side-Port DDR2 SDRAM
512Mbits(32Mbx16)-64MB

Audio CKT

AMP & Audio Jack

Codec_IDT9271B7

TPA6017A2

Page 29

Page 30

LPC BUS

3

SATA HDD Connector

Page 25

KBC
ENE KB926

SATA ODD Connector

Page 25

Page 34

SATA Multi-Bay Connector

Touch Pad CONN.

Page 25

Int.KBD

Page 34

Page 35

RTC CKT.

e-SATA Combo

Page 20

SPI

Consumer IR
Page 30

Power OK CKT.

Page 32

SPI ROM
SST25VF080B
Page 33

P35
4

4

Power On/Off CKT.
P35

Compal Secret Data

Security Classification

DC/DC Interface CKT.

2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Page 36

Date:

A

Compal Electronics, Inc.

B

C

D

Block Diagram
Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

2

of

46

A

B

Voltage Rails

O MEANS ON

C

X MEANS OFF

D

E

Symbol Note :
Layout Notes

L
1

1

: means Digital Ground

UMA@ : means for RS780M.
Please see VGA@ as no install. No support RX780M.

+5VS
+3VS

: means Analog Ground

11/14 update

+1.5VS

power
plane

+0.9V

@ : means just reserve , no build
DEBUG@ : means just reserve for debug.

+VCCP
+5VALW

: Question Area Mark.(Wait check)

+CPU_CORE

+1.8V

+B
+VGA_CORE

USB-1 Right side

+1.2VS
+0.9VGA

2

O

O

S1

O

O

O

O

S3

O

O

O

X

S5 S4/AC

O

O

X

X

S5 S4/ Battery only

O

X

X

X

S5 S4/AC & Battery
don't exist

X

X

X

X

HEX

ADDRESS

DDR SO-DIMM 0

A0

10100000

DDR SO-DIMM 1

A4

10100100

CLOCK GENERATOR (EXT.)

D2

11010010

Device

HEX

Address

Smart Battery

16H

0001 011X b

A0H

1010 000X b

24C16

2

USB-9 Express card
USB-10 X

yc

USB-11 X

//
m

EC SM Bus2 address

SMBUS Control Table
SOURCE

SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
I2C_CLK

KB926
KB926
RS780M

I2C_DATA
DDC_CLK0
DDC_DATA0
DDC_DATA1
SCL0

Device

HEX

Address

CPU

98H

1001 100X b

SCL1

ADI1032-2 CPU 9AH

1001 101X b

SDA1

RS780M
RS780M
SB700

SDA0

SB700

SCL2

SB700

SDA2
4

PCIe-6 GLAN (Marvell)

USB-8 MiniCard(WWAN/TV)

DDC_CLK1

EC SM Bus1 address

PCIe-5 Card reader

USB-5 WLAN

USB-7 Finger Printer

tp
:

DEVICE

PCIe-4 New Card

USB-4 Camera

USB-6 Bluetooth

SMB_EC_CK1

I2C / SMBUS ADDRESSING

PCIe-3 WLAN

USB-3 Dock

p.

O

PCIe-2 X

USB-2 Left side(with ESATA)

om

O

ht

3

S0

PCIe-1 TV tuner/WWAN/Robeson

USB-0 Right side

+1.8VS

State

PCIe assignment:

/x
/

USB assignment:

+2.5VS

su

+3VALW

SCL3

SB700

SDA3

X
X
X
X
X
X
X
X
X

BATT

V
X
X
X
X
X
X
X
X

SERIAL
EEPROM

V
X
X
X
X
X
X
X
X

THERMAL
SENSOR
CPU &
ADM1032

SODIMM
I / II

X
V
X
X
X
X
X
X
X

X
X
X
X
X
V
X
X
X

CLK CHIP

X
X
X
X
X
V
X
X
X

Compal Secret Data

Security Classification
2007/08/02

Issued Date

INVERTER

2008/08/02

Deciphered Date

Title

MINI CARD
Slot 2

X
X
X
X
X
X
V
X
X

Date:

B

C

D

HDMI

X
X
V
X
X
X
X
X
X

X
X
X
V
X
X
X
X
X

G-Sensor
3

X
X
X
X
X
X
X
V
X

4

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

LCD

Notes List
Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

3

of

46

5

4

3

2

1

SB700
0.3A

INVPWR_B+

300mA

LVDS CON

LAN

60mA
1.7A
D

2A

CardReader
Finger printer

+3VAUX_BT

DDR

B++

LEDs

5.39A

+3VS

10mA

1A

??A

+3VL_EC
79.67mA

SB700

2mA

CIR

1.3A

+5VALW

+5VS

su

HDMI

+3VL_CAP

10mA

C

35mA

p.

+VDDA_CODEC
IDT 9271B7

+1.8V

3.7A

B

tp
:

3.7 X 3=11.1V

BATT

B+++

+1.1VS

RS780M
+LCDVDD
G-sensor

+5VAMP

+3VS_CLK

LVDS CON

C

ODD

SB700

Audio codec

Side port RAM

DDR2 x2

723.6mA

+1.8VS

+0.9V

+1.5VS

New card

RS780M

WLAN

B

CPU

ht

3.7A

Thermal sensor

LEDs

+1.35VS

yc
12.11A

CPU

WLAN

CPU

//
m
8 A

B+++

1.5A

USB Power

3.7A

B+

DC

om

1.3A

1.8A

New card
+2.5VS

FAN

20mA

+5VL

HDD

SPI ROM

/x
/

+3VL

0.58A

PC Camera

D

5.89A

VIN

50mA

+3VALW

700mA

AC

50mA

DDR2 x2
8.84A

RS780M
CPU
SB700
+VDDCLK_IO

+1.2VALW
A

+1.2V_HT

273mA

RS780M

A

SB700
Compal Secret Data

Security Classification
Issued Date

2007/09/26

Deciphered Date

2007/09/26

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Power delivery
Rev
0.4

LA-4481P

Date:

5

4

3

2

Monday, September 08, 2008
1

Sheet

4

of

46

A

B

C

D

E

VLDT CAP.

+1.2V_HT

250 mil
1

C1
4.7U_0805_10V4Z

2

1

1

1

C2
4.7U_0805_10V4Z

2

C3
0.22U_0603_16V4Z

2

1

C4
0.22U_0603_16V4Z

2

1

1

C5
180P_0402_50V8J

2

C6
180P_0402_50V8J

2

1

Near CPU Socket

<11> H_CADIP[0..15]
<11> H_CADIN[0..15]

H_CADIP[0..15]

H_CADOP[0..15]

H_CADIN[0..15]

H_CADON[0..15]

H_CADOP[0..15]

<11>

H_CADON[0..15]

<11>

If VLDT is connected only on one side, one
4.7uF cap should be added to the island
side.

+1.2V_HT
JCPU1A

3

<11>
<11>
<11>
<11>

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

J3
J2
J5
K5

L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1

L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1

Y1
W1
Y4
Y3

<11>
<11>
<11>
<11>

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

N1
P1
P3
P4

L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1

L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1

R2
R3
T5
R5

TYCO_4-1903401-4_AMD
CONN@

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

<11>
<11>
<11>
<11>

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

<11>
<11>
<11>
<11>

2

3

ht

Athlon 64 S1
Processor Socket

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

/x
/

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

su

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15

2
4.7U_0805_10V4Z

p.

L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15

AE2 +VLDT_B 1
C7
AE3
AE4
AE5

om

E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

yc

2

VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3

//
m

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

HT LINK

D1
D2
D3
D4

tp
:

VLDT=1500mA

+5VS

500mA

PWM Fan Control circuit
1

JP1
1

D1
CH751H-40PT_SOD323-2

4.7U_0805_10V4Z

1
2
3
4

C9
0.1U_0402_16V4Z

2

2

2

1

C8

1
2
GND
GND
ACES_85205-02001

1

1
2
5
6

+VCC_FAN

D Q1

@ D2

G
RLZ5.1B_LL34

3

S

SI3456BDV-T1-E3_TSOP6

2

FAN_PWM

4

<34>
4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

4

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
AMD CPU S1G2 HT I/F

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

5

of

46

A

B

C

D

0801 add Cap for EMI request

C129
2

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH
+3VALW

0.1U_0402_16V4Z

+1.8V

@
1

DDR_A_CLK#0

2

+5VALW

+1.8V

2

1

C123
2

C10
1.5P_0402_50V9C

DDR_A_CLK1

0.1U_0402_16V4Z
@
1

DDR_A_CLK#1

+5VS

0.1U_0402_16V4Z

2

C11
1.5P_0402_50V9C
+1.8V

DDR_B_CLK0
1

2

R1
C12
1.5P_0402_50V9C

1K_0402_1%
1

DDR_B_CLK#0

1

2

R2
C13
1.5P_0402_50V9C

C14

1K_0402_1%
1

DDR_B_CLK#1

750mA

2

+MCH_REF

2

DDR_B_CLK1

+0.9V

1

C15

1

2
2
1000P_0402_25V8J
0.1U_0402_16V4Z

+0.9V
JCPU1B

T19
V22
U21
V19

MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

T20
U19
U20
V20

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

<9> DDR_CKE0_DIMMA
<9> DDR_CKE1_DIMMA

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA

J22
J20

MA_CKE0
MA_CKE1

<9> DDR_A_CLK0
<9> DDR_A_CLK#0
<9> DDR_A_CLK1
<9> DDR_A_CLK#1
<9> DDR_A_MA[15..0]

<9> DDR_A_BS#0
<9> DDR_A_BS#1
<9> DDR_A_BS#2
<9> DDR_A_RAS#
<9> DDR_A_CAS#
<9> DDR_A_WE#

DDR_A_ODT0
DDR_A_ODT1

VTT_SENSE

Y10

MEMVREF

W17

VTT_SENSE

RSVD_M2

B18

MB0_ODT0
MB0_ODT1
MB1_ODT0

W26
W23
Y26

DDR_B_ODT0
DDR_B_ODT1

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

V26
W25
U22

DDR_CS0_DIMMB#
DDR_CS1_DIMMB#

MB_CKE0
MB_CKE1

J25
H26

DDR_CKE0_DIMMB
DDR_CKE1_DIMMB

N19
N20
E16
F16
Y16
AA16
P19
P20

MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4

MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4

P22
R22
A17
A18
AF18
AF17
R26
R25

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

R20
R23
J21

MA_BANK0
MA_BANK1
MA_BANK2

MB_BANK0
MB_BANK1
MB_BANK2

R24
U26
J26

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

R19
T22
T24

MA_RAS_L
MA_CAS_L
MA_WE_L

MB_RAS_L
MB_CAS_L
MB_WE_L

U25
U24
U23

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

PAD

T1

PAD

T3

+MCH_REF

om

RSVD_M1

PAD

DDR_B_ODT0 <10>
DDR_B_ODT1 <10>

yc

<9> DDR_CS0_DIMMA#
<9> DDR_CS1_DIMMA#

MEMZP
MEMZN

H16

T2
<9> DDR_A_ODT0
<9> DDR_A_ODT1

AF10
AE10

W10
AC10
AB10
AA10
A10

DDR_CS0_DIMMB# <10>
DDR_CS1_DIMMB# <10>

//
m

39.2_0402_1%
2
2
39.2_0402_1%

MEM:CMD/CTRL/CLK VTT5
VTT6
VTT7
VTT8
VTT9

DDR_CKE0_DIMMB <10>
DDR_CKE1_DIMMB <10>

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1

tp
:

R3
1
1
R4

VTT1
VTT2
VTT3
VTT4

<10>
<10>
<10>
<10>

<10> DDR_B_DM[7..0]
DDR_B_MA[15..0] <10>

ht

+1.8V

D10
C10
B10
AD10

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

p.

750mA
Place them close to CPU within 1"

3

MEM:DATA

1

C124

DDR_B_BS#0 <10>
DDR_B_BS#1 <10>
DDR_B_BS#2 <10>
DDR_B_RAS# <10>
DDR_B_CAS# <10>
DDR_B_WE# <10>

<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

A12
B16
A22
E25
AB26
AE22
AC16
AD12

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7

C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

TYCO_4-1903401-4_AMD
Athlon 64 S1
CONN@
Processor
Socket

4

1

JCPU1C

<10> DDR_B_D[63..0]
DDR_A_CLK0

/x
/

@
1

su

+1.8V

Processor DDR2 Memory Interface

2

1

E

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

E12
C15
E19
F24
AC24
Y19
AB16
Y13

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

2

3

DDR_A_DM[7..0]

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

<9>

<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>

4

Compal Secret Data
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
AMD CPU S1G2 DDRII I/F

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

B

<9>

Athlon 64 S1 TYCO_4-1903401-4_AMD
Processor Socket
CONN@

Security Classification

A

DDR_A_D[63..0]

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

6

of

46

B

C

D

+2.5VDDA
VDDA=300mA
L1
3300P_0402_50V7K
1
2
FBM_L11_201209_300L_0805
1
1
1
1
+
4.7U_0805_10V4Z
C17
C18
C19
0.22U_0603_16V4Z
2
2
2
2

+2.5VS

A:Need to re-Link "SGN00000200"

+1.8V

R5

1

1
R6

2
10K_0402_5%
2
300_0402_5%
B

C16
@ 100U_D2_10VM

E

@ R7
1

0_0402_5%
2

1
R8
1
R9

2
0_0402_5%
2
0_0402_5%

EN0

<37,39>

2

A

E

Q2
CPU_THERMTRIP#_R
3
1
MMBT3904_NL_SOT23-3

H_THERMTRIP#_EC <34>

C

H_THERMTRIP# <21>

JCPU1D

1

LDT_RST#
H_PWRGD_CPU
LDT_STOP#
CPU_LDT_REQ#

R12
169_0402_1%
2
3900P_0402_50V7K

CPU_SIC
CPU_SID

Address:100_1100
R16
R17

2 44.2_0402_1% CPU_HTREF0
2 44.2_0402_1% CPU_HTREF1

1
1

F6
E6

VDD0_FB_H
VDD0_FB_L

VDDIO_FB_H
VDDIO_FB_L

W9
Y9

PAD
PAD

<43> CPU_VDD1_FB_H
<43> CPU_VDD1_FB_L

VDD1_FB_H
VDD1_FB_L

VDDNB_FB_H
VDDNB_FB_L

H6
G6

VDD_NB_FB_H
VDD_NB_FB_L

T11 PAD
T13 PAD

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST27_SINGLECHAIN

Close to CPU
+CPU_CORE_1
R23

10_0402_5%
1
2CPU_VDD1_FB_H
1
2CPU_VDD1_FB_L

R24

TEST18
TEST19

10_0402_5%

1

R25

E9
E8

TEST21
TEST20
TEST24
TEST22
TEST12
TEST27

C2
AA6

TEST9
TEST6

A3
A5
B3
B5
C1

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

2 0_0402_5%

2

1

R28

2

+3VS

H_PWRGD_CPU

0.1U_0402_16V4Z

1

2

1

@ 34.8K_0402_1%~N

@ 20K_0402_5%

2.09V for Gate

3

+1.8V
+1.8VS
2

+1.8V
R31
300_0402_5%

CPU_SID
R29
2
1
2.2K_0402_5%
R30
2
1
2.2K_0402_5%
CPU_SIC

4

3

1

6

1

Q14A
<12,20> LDT_STOP#
1

+3VS

2
4

1

R47
300_0402_5%
CPU_LDT_REQ#

1

2

C27
1
CPU_LDT_REQ# <12,20>

C28
0.01U_0402_25V4Z
@

EC is PU to 5VALW

2
U1

THERMDC_CPU 3
2
2200P_0402_50V7K
4

2200p change to
1000p for ADT7421

J7
H8

CPU_TEST28_H_PLLCHRZ_P
CPU_TEST28_L_PLLCHRZ_N

TEST17
TEST16
TEST15
TEST14

D7
E7
F7
C7

CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0

TEST7
TEST10

C3
K8

TEST8

C4

TEST29_H
TEST29_L

C9
C8

RSVD10
RSVD9
RSVD8
RSVD7
RSVD6

2

+CPU_CORE_NB

PAD
PAD
PAD
PAD
PAD
PAD

CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

T7
T8

VDD_NB_FB_H
VDD_NB_FB_L

route as differential
as short as possible
testpoint under package

10_0402_5%
2
2
10_0402_5%
2

Close to CPU

T9
T10
T12
T14

PAD
PAD

R18
1
1
R19

T15
T16

H18
H19
AA7
D5
C5

+1.8V

+1.8V

C26

1

CPU_TDO

0605 change value

1

THERMDA_CPU 2

CPU_DBREQ#

AE9

3

FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V

0.215mA

+1.8VS

E10

TDO

SMB_EC_CK1 <33,34,35,37>

@ 2N7002DW-7-F_SOT363-6

C25
0.01U_0402_25V4Z
@

0.1U_0402_16V4Z

2

LDT_STOP#

VDD_NB_FB_H <43>
VDD_NB_FB_L <43>

SMB_EC_DA1 <33,34,35,37>

tp
:

@ Q14B
2N7002DW-7-F_SOT363-6

ht

C24 @
0.1U_0402_16V4Z

2

1

5

2

DBREQ_L

1K_0402_5%
2
2
1K_0402_5%

CONN@
TYCO_4-1903401-4_AMD

//
m

1
<20> H_PWRGD_CPU

2

@ C23
R27

+1.8V sense no support

T4
T5

TEST28_H
TEST28_L

yc

+1.8VS

R26
300_0402_5%

TEST25_H
TEST25_L

AB8
AF7
AE7
AE8
AC8
AF8

+1.8V
R14
CPU_SVC
1
CPU_SVD
1
R15

SCLK

8

SMB_EC_CK2 <34>

D+

SDATA

7

SMB_EC_DA2 <34>

D-

ALERT#

6

GND

5

VDD

THERM#

ADM1032ARMZ-2REEL_MSOP8

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.

HDT Connector
JP2
1
3
5
7
9
11
13
15
17
19
21
23

2
4
6
8
10
12
14
16
18
20
22
24
26

CPU_TEST27_SINGLECHAIN

R32

1

2 @ 300_0402_5%

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

R33
R34
R35
R41
R42
R43
R44
R45
R46

1
2
2
2
2
2
2
2
2

2
1
1
1
1
1
1
1
1

300_0402_5%
@ 300_0402_5%
300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%
@ 300_0402_5%

+3VS
5

2

LDT_RST#
C22
0.01U_0402_25V4Z
@

TEST23

H10
G9

+1.8V

U2
HDT_RST#

4

P

1

AD7

CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

1

B

2

G

LDT_RST#

CPU_TEST23_TSTUPD

DBRDY
TMS
TCK
TRST_L
TDI

3

@ R246 0_0402_5%
1
2

R13
2

A

1

Y
3

<20>

R22

PAD

G10
AA9
AC9
AD9
AF9

1

MMBT3904_NL_SOT23-3
Q3 @
1
H_PROCHOT# <20>

THERMDC_CPU
THERMDA_CPU

CPU_VDD1_FB_H
Y6
CPU_VDD1_FB_L AB6

2
1
@ 220_0402_5% R36
2
1
@ 220_0402_5% R37
2
1
@ 220_0402_5% R38
2
1
@ 220_0402_5% R39
2
1
300_0402_5% R40

1

R21
300_0402_5%

T6
10_0402_5%
1
2CPU_VDD0_FB_H
1
2CPU_VDD0_FB_L
10_0402_5%

HT_REF0
HT_REF1

W7
W8

CPU_VDD0_FB_H
CPU_VDD0_FB_L

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
+CPU_CORE_0
R20

2

2

R6
P6

1
@ 10K_0402_5%
2
300_0402_5%

@ 300_0402_5%
THERMDC
THERMDA

<43> CPU_VDD0_FB_H
<43> CPU_VDD0_FB_L

0605 change power rail to solve +3vs leakage
+1.8VS

SIC
SID
ALERT_L

CPU_THERMTRIP#_R
CPU_PROCHOT#_1.8
CPU_MEMHOT#_1.8V

AF6
AC7
AA8

2
R10
1
R11

CPU_PROCHOT#_1.8

/x
/

+1.2V_HT

AF4
AF5
AE6

THERMTRIP_L
PROCHOT_L
MEMHOT_L

CPU_SVC <43>
CPU_SVD <43>

su

C21

1

SVC
SVD

RESET_L
PWROK
LDTSTOP_L
LDTREQ_L

CPU_SVC
CPU_SVD

A6
A4

p.

0718 Silego -- 216 ohm
<16> CLK_CPU_BCLK#

CLKIN_H
CLKIN_L

B7
A7
F10
C6

+1.8V

M11
W18

C

2

C20

A9
A8

KEY1
KEY2

E

<16> CLK_CPU_BCLK

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

2 3900P_0402_50V7K

1

VDDA1
VDDA2

B

F8
F9

Place close to CPU wihtin 1.5"

om

1

@ SAMTEC_ASP-68200-07

LDT_RST#
4

SB_PWRGD <21,34,43>

@ NC7SZ08P5X_NL_SC70-5

9/20 SP020016900
Address:100_1101

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
AMD CPU S1G2 CTRL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

7

of

46

A

B

C

D

18000mA

VDD(+CPU_CORE) decoupling.
+CPU_CORE_0

1

+

1

+

C29
330U_X_2VM_R6M

2

+

C30
330U_X_2VM_R6M

2

1
C31
330U_X_2VM_R6M

2

+

C32
330U_X_2VM_R6M

2

Near CPU Socket
+CPU_CORE_0

+CPU_CORE_1

3000mA
+CPU_CORE_NB

2
22U_0805_6.3V6M

1

C34

2
22U_0805_6.3V6M

1

C35

2
22U_0805_6.3V6M

C36
22U_0805_6.3V6M

1

2

C37
22U_0805_6.3V6M

2

1

C39
22U_0805_6.3V6M

2

1

C40
22U_0805_6.3V6M

2

+1.8V

2000mA

+CPU_CORE_1

C41
0.22U_0603_16V4Z

2

C38
22U_0805_6.3V6M

2

+CPU_CORE_0

1

1

1

C42
0.01U_0402_25V4Z

2

1

1

C43
180P_0402_50V8J

2

C44
0.22U_0603_16V4Z

2

1

C45
0.01U_0402_25V4Z

2

1

C46
180P_0402_50V8J

2

G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23

K16
M16
P16
T16
V16

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

Under CPU Socket

om

p.

2

+CPU_CORE_NB
VDDIO decoupling.

yc

+CPU_CORE_NB

1

+1.8V

C47
22U_0805_6.3V6M

1

C50
22U_0805_6.3V6M

2

1

C51
22U_0805_6.3V6M

1

1

C52

0.22U_0603_16V4Z
2

2

1

C53

0.22U_0603_16V4Z
2

1

C54

C55

180P_0402_50V8J 180P_0402_50V8J
2
2

Under CPU Socket

Between CPU Socket and DIMM

2

C58
0.22U_0603_16V4Z

2

C59
0.22U_0603_16V4Z

2

+1.8V

1

1

1

2

1

C70
0.01U_0402_25V4Z

2

C60
0.22U_0603_16V4Z

2

+1.8V

C69
0.01U_0402_25V4Z

1

ht

1

C57
0.22U_0603_16V4Z

1

C71
180P_0402_50V8J

2

1

C72
180P_0402_50V8J

2

C73
180P_0402_50V8J

2

1

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

+1.8V

TYCO_4-1903401-4_AMD
Athlon 64 S1
CONN@
Processor Socket

C49 @
22U_0805_6.3V6M

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

1

2

CONN@
Athlon 64 S1 TYCO_4-1903401-4_AMD
Processor Socket

+0.9V
3

Near Power Supply
1

C: Change to NBO CAP

+ C56
220U_Y_4VM
2

+0.9V

1

1

C61
4.7U_0805_10V4Z

2

180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4

2

VTT decoupling.

+1.8V

1

1

tp
:

3

2

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

decoupling.

C48
22U_0805_6.3V6M

//
m

2

1

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

/x
/

1

C33

+CPU_CORE_1

JCPU1E

su

1

JCPU1F

18000mA

+CPU_CORE_0

+CPU_CORE_1

1
1

E

C62
4.7U_0805_10V4Z

2

1

C63
0.22U_0603_16V4Z

2

1

C64
0.22U_0603_16V4Z

2

1

C65
1000P_0402_25V8J

2

1

C66
1000P_0402_25V8J

2

1

C67
180P_0402_50V8J

2

1

C68
180P_0402_50V8J

2

Near CPU Socket Right side.
C74
180P_0402_50V8J

+0.9V

2
1

+1.8V

1

C75
4.7U_0805_10V4Z

2

C76
4.7U_0805_10V4Z

2

1

C77
0.22U_0603_16V4Z

2

1

C78
0.22U_0603_16V4Z

2

1

C79
1000P_0402_25V8J

2

1

2

C80
1000P_0402_25V8J

1

C81
180P_0402_50V8J

2

1

C82
180P_0402_50V8J

2

4

4

1
1

2

1
C84
4.7U_0805_10V4Z

2

1
C85
4.7U_0805_10V4Z

2

1
C86
4.7U_0805_10V4Z

2

C87
4.7U_0805_10V4Z

C: Change to NBO CAP

+ C83
220U_Y_4VM
@

Near CPU Socket Left side.

2

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
AMD CPU S1G2 PWR & GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

8

of

46

A

B

C

D

E

+V_DDR_MCH_REF

4.5A

2A

+1.8V

DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0

1

DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

DDR_A_D[0..63]

DDR_A_D4
DDR_A_D5

DDR_A_D[0..63]

DDR_A_DM[0..7]
DDR_A_DM0
DDR_A_DQS[0..7]
DDR_A_D6
DDR_A_D7

DDR_A_MA[0..15]
DDR_A_DQS#[0..7]

DDR_A_D12
DDR_A_D13

DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

<6>

DDR_A_DM[0..7]

<6>

DDR_A_DQS[0..7]

<6>

DDR_A_MA[0..15] <6>
DDR_A_DQS#[0..7]

8
7
6
5

DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_CKE1_DIMMA
DDR_A_MA15

<6>

DDR_A_DM1
DDR_A_CLK0 <6>
DDR_A_CLK#0 <6>
DDR_A_D14
DDR_A_D15

47_0804_8P4R_5%
RP4
8
1
7
2
6
3
5
4

<6> DDR_CKE0_DIMMA
<6> DDR_A_BS#2

DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

<6> DDR_A_BS#0
<6> DDR_A_WE#
<6> DDR_A_CAS#
<6> DDR_CS1_DIMMA#
<6> DDR_A_ODT1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35

3

DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59

4

<10,16,21,31> SMB_CK_DAT0
<10,16,21,31> SMB_CK_CLK0
+3VS

1
C104
0.1U_0402_16V4Z

2

2
1000P_0402_25V8J

DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3

1

1

+V_DDR_MCH_REF <10>

DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA

DDR_CKE1_DIMMA <6>

DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_ODT0
DDR_A_MA13

R49
1K_0402_1%

2

0.1U_0402_16V4Z

/x
/

C98

2

C97

1

DDR_A_D22
DDR_A_D23

su

DDR_A_D26
DDR_A_D27

+V_DDR_MCH_REF
DDR_A_DM2
1

DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12

p.

2

R48
1K_0402_1%

DDR_A_D20
DDR_A_D21

om

DDR_A_DM3

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

1

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1

C90
C91

C92
C93

C94
C95

1
1

1
1

1
1

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

DDR_A_BS#0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3

47_0804_8P4R_5%
RP5
8
1
7
2
6
3
5
4

DDR_A_ODT1
DDR_CS1_DIMMA#
DDR_A_CAS#
DDR_A_WE#

47_0804_8P4R_5%
RP6
8
1
7
2
6
3
5
4

1
C100
1
C101

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

47_0804_8P4R_5%
RP7
DDR_A_RAS#
8
1
DDR_CS0_DIMMA#
7
2
DDR_A_ODT0
6
3
DDR_A_MA13
5
4

1
C102
1
C103

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

C96
C99

1
1

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2

47_0804_8P4R_5%

Cross between +1.8V and +0.9V power plan

DDR_A_BS#1 <6>
DDR_A_RAS# <6>
DDR_CS0_DIMMA# <6>
DDR_A_ODT0 <6>

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38
DDR_A_D39

3

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53

DDR_A_CLK1 <6>
DDR_A_CLK#1 <6>
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

4

TYCO_292527-4
CONN@

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
DDRII SO-DIMM 0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

C89

1

yc

DDR_A_D24
DDR_A_D25

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND

C88

//
m

DDR_A_D18
DDR_A_D19

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND

47_0804_8P4R_5%
RP2
8
1
7
2
6
3
5
4
47_0804_8P4R_5%
RP3
8
1
7
2
6
3
5
4

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1

+1.8V

1
2
3
4

tp
:

DDR_A_DQS#2
DDR_A_DQS2

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201

ht

DDR_A_D16
DDR_A_D17

+1.8V

+0.9V
RP1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

2

DDR_A_D10
DDR_A_D11

+1.8V

JDIMM1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

9

of

46

A

B

C

D

E

4.5A
+1.8V

+1.8V

DDR_B_D0
DDR_B_D1
C107
1000P_0402_25V8J

1

2

1

DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D13
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11

+1.8V

+0.9V

JDIMM2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

<9> +V_DDR_MCH_REF

RP8

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

DDR_B_D[0..63]

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DDR_B_D4
DDR_B_D5

DDR_B_D[0..63]

DDR_B_DM[0..7]

DDR_B_DM0

DDR_B_DQS[0..7]

DDR_B_D6
DDR_B_D7

DDR_B_MA[0..15]
DDR_B_DQS#[0..7]

DDR_B_D12
DDR_B_D9

DDR_B_MA6
DDR_B_MA2
DDR_B_MA0
DDR_CS0_DIMMB#

<6>

DDR_B_DM[0..7]

<6>

DDR_B_DQS[0..7]

<6>

8
7
6
5

2
C105
1
C106

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C108
1
C109

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C110
1
C111

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C112
1
C113

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C114
1
C115

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C116
1
C117

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C118
1
C119

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

47_0804_8P4R_5%

DDR_B_MA[0..15] <6>
DDR_B_DQS#[0..7]

1
2
3
4

RP9
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA4

<6>

8
7
6
5

DDR_B_DM1

1
2
3
4

1

47_0804_8P4R_5%
DDR_B_CLK0 <6>
DDR_B_CLK#0 <6>

RP10
DDR_B_BS#2
DDR_CKE0_DIMMB
DDR_B_MA15
DDR_CKE1_DIMMB

DDR_B_D14
DDR_B_D15

8
7
6
5

1
2
3
4

47_0804_8P4R_5%

<6> DDR_B_BS#2

DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

<6> DDR_B_BS#0
<6> DDR_B_WE#
<6> DDR_B_CAS#
<6> DDR_CS1_DIMMB#
<6> DDR_B_ODT1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35

3

DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
<9,16,21,31> SMB_CK_DAT0
<9,16,21,31> SMB_CK_CLK0
+3VS
4

C120
0.1U_0402_16V4Z

1

/x
/

DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3

su

<6> DDR_CKE0_DIMMB

DDR_B_DM2

DDR_B_D30
DDR_B_D31
DDR_CKE1_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

1
2
3
4

47_0804_8P4R_5%
RP12
DDR_B_BS#0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA3

8
7
6
5

1
2
3
4

47_0804_8P4R_5%
RP13

DDR_CKE1_DIMMB <6>

DDR_B_MA15
DDR_B_MA14

8
7
6
5

DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#
DDR_B_WE#

p.

DDR_B_D26
DDR_B_D27
2

RP11
DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12

8
7
6
5

1
2
3
4

RP14
8
7
6
5

1
2
3
4

47_0804_8P4R_5%

Cross between +1.8V and +0.9V power plan

DDR_B_BS#1 <6>
DDR_B_RAS# <6>
DDR_CS0_DIMMB# <6>

DDR_B_ODT0
DDR_B_MA13

DDR_B_ODT0 <6>

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45

3

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_CLK1 <6>
DDR_B_CLK#1 <6>
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63

+3VS

4

TYCO_292531-4
CONN@

2

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

2

47_0804_8P4R_5%
DDR_B_BS#1
DDR_B_RAS#
DDR_B_ODT0
DDR_B_MA13

om

DDR_B_DM3

DDR_B_D20
DDR_B_D16

yc

DDR_B_D24
DDR_B_D25

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

//
m

DDR_B_D18
DDR_B_D19

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

tp
:

DDR_B_DQS#2
DDR_B_DQS2

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

ht

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_B_D21
DDR_B_D17

B

C

D

DDRII SO-DIMM 1
Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

10

of

46

A

B

C

D

E

U3B

<20>
<20>
<20>
<20>
<20>
<20>
<20>
<20>

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)

AC8
AB8

PCIE I/F GPP

PCIE I/F SB

PCIE_ITX_PRX_P0
PCIE_ITX_PRX_N0

C121 1
C122
1

2

0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_ITX_C_PRX_P0 <27>
PCIE_ITX_C_PRX_N0 <27>

PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3

C125 1
C126
1
C127 1
C128
1

2

0.1U_0402_16V7K
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_ITX_C_PRX_P2 <27>
PCIE_ITX_C_PRX_N2 <27>
GLAN_TXP <26>
GLAN_TXN <26>

2

New Card

WLAN
GLAN

<5> H_CADOP[0..15]

<5> H_CADON[0..15]

SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
R50
R51

C131
C132
C133
C134
C135
C136
C137
C138

1
1
1
1
1
1
1
1

1
1

2
2

2
2
2
2
2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

1.27K_0402_1%
2K_0402_1%

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

<20>
<20>
<20>
<20>
<20>
<20>
<20>
<20>

yc

RS780M Display Port Support (muxed on GFX)
GFX_TX0,TX1,TX2 and TX3
DP0

//
m

GFX_TX4,TX5,TX6 and TX7
DP1
AUX1 and HPD1

ht

tp
:

3

H_CADOP[0..15]

H_CADIP[0..15]

H_CADON[0..15]

H_CADIN[0..15]

H_CADIP[0..15]

<5>

H_CADIN[0..15]

<5>

2

U3A

+1.1VS

RS780M_FCBGA528

AUX0 and HPD0

/x
/

AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

1

<5>
<5>
<5>
<5>

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

<5>
<5>
<5>
<5>

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
1 R52

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

T22
T23
AB23
AA22

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

M22
M23
R21
R20

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

2 301_0402_1% C23
A24

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

H24
H25
L21
L20

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

M24
M25
P19
R18

HT_RXCALP
HT_RXCALN

HT_TXCALP
HT_TXCALN

B24
B25

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

PART 1 OF 6

HYPER TRANSPORT CPU I/F

2

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

TMDS_B_DATA2 <19>
TMDS_B_DATA2# <19>
TMDS_B_DATA1 <19>
TMDS_B_DATA1# <19>
TMDS_B_DATA0 <19>
TMDS_B_DATA0# <19>
TMDS_B_CLK <19>
TMDS_B_CLK# <19>

su

PCIE_PTX_C_IRX_P2
PCIE_PTX_C_IRX_N2
GLAN_RXP
GLAN_RXN

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

p.

<27>
<27>
<26>
<26>

AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

PART 2 OF 6

om

<27> PCIE_PTX_C_IRX_P0
<27> PCIE_PTX_C_IRX_N0

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

PCIE I/F GFX

1

D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3

RS780M_FCBGA528

0718 Place within 1"
layout 1:2

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

3

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

<5>
<5>
<5>
<5>

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

<5>
<5>
<5>
<5>

1 R53

2 301_0402_1%

0718 Place within 1"
layout 1:2

NEED CHECK R68 & R69 WITH AMD
4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
RS780-HT/PCIE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

11

of

46

A

B

C

D

E

1

1

+3VS

110mA

L2
1
2 +AVDD1
BLM18PG121SN1D_0603
1
L3
+AVDD2
+1.8VS
0_0603_5%
1
2
L4
C140
1
2 +AVDDQ
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
2
1
+1.8VS

+1.8VS

CRT_HSYNC
CRT_VSYNC

<15,17> CRT_HSYNC
<15,17> CRT_VSYNC
<17> UMA_CRT_CLK
<17> UMA_CRT_DAT

1
2
BLM18PG121SN1D_0603
1
L6
C142

200 Ohm @ 100Mhz

1
2
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
1
2
L8
C143
+NB_PLLVDD
1
2
+NB_HTPVDD
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
1
2
+1.8VS
L9
C145
1
2
+VDDA18HTPLL
BLM18PG121SN1D_0603 1
2.2U_0603_6.3V4Z
2
+1.8VS

R59

C146
2.2U_0603_6.3V4Z

+VDDA18PCIEPLL
2

20mA
20mA

1
R61

+1.8VS

<16> NBGFX_CLK
<16> NBGFX_CLK#

3

tp
:

<16> CLK_SBLINK_BCLK
<16> CLK_SBLINK_BCLK#

ht

<18> LCD_DDC_CLK
<18> LCD_DDC_DAT
<19> HDMIDAT_UMA
<19> HDMICLK_UMA
<15> RS780_DFT_GPIO_0

0605 umount to follow Trinity
<15>

AUX_CAL

H17

VDDA18HTPLL

D7
E7

VDDA18PCIEPLL1
VDDA18PCIEPLL2

D8
A10
C10
C12

SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP

C25
C24

HT_REFCLKP
HT_REFCLKN

//
m

1
2
R65
4.7K_0402_5%

PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)

E11
F11

<16> NB_OSC_14.318M
1
2
R64
4.7K_0402_5%

DAC_RSET(PWM_GPIO1)

A12
D14
B12

120mA

<16> CLK_NBHT
<16> CLK_NBHT#

+1.1VS

DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)

20mA

R60 0_0402_5%
1
2 NB_RESET#
NB_PWRGD
LDT_STOP#
CPU_LDT_REQ#
2
300_0402_5%

<15,20,26,27,33,34> PLT_RST#
<21> NB_PWRGD

A11
B11
F8
E8

2 715_0402_1% G14

1

200 Ohm @ 100Mhz
200 Ohm @ 100Mhz

RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)

+3VS

Strap pin

2
1
@ R67 10K_0402_5%

Strap pin

REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)

T2
T1

GFX_REFCLKP
GFX_REFCLKN

U1
U2

GPP_REFCLKP
GPP_REFCLKN

V4
V3

GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)

B9
A9
B8
A8
B7
A7

I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)

B18
A18
A17
B17
D20
D21
D18
D19

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

B16
A16
D16
D17

VDDLTP18(NC)
VSSLTP18(NC)

A13
B13

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

A15
B15
A14
B14

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

C14
D15
C16
C18
C20
E20
C22

LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)

E9
F7
G12

LVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2+
LVDS_A2-

<18>
<18>
<18>
<18>
<18>
<18>

/x
/

BLUE

<17> BLUE

G18
G17
E18
F18
E19
F19

CRT/TVOUT

GREEN

<17> GREEN

C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)

su

200 Ohm @ 100Mhz

L5

RED

<17> RED

E17
F17
F15

A22
B22
A21
B21
B20
A20
A19
B19

p.

+1.1VS

2

TV_CRMA
TV_LUMA
TV_COMPS

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)

PART 3 OF 6

PLL PWR
LVTM

RED
2
140_0402_1%
GREEN
2
150_0402_1%
BLUE
2
150_0402_1%

PAD
PAD
PAD

AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)

om

T17
T18
T19

140OHM
1
R56
1
R57
1
R58

2

20mA

4mA

PM

C141
2.2U_0603_6.3V4Z

U3C
F12
E12
F14
G15
H15
H14

CLOCKs

LDT_STOP#
CPU_LDT_REQ#

<7,20> LDT_STOP#
<7,20> CPU_LDT_REQ#

C139
2.2U_0603_6.3V4Z

yc

0605 remove 0 ohm resisters

2

LVDS_ACLK+ <18>
LVDS_ACLK- <18>

L7
300mA
2.2U_0603_6.3V4Z
1
2
BLM18PG121SN1D_0603
1
1
C144
0.1U_0402_16V4Z
+VDDLT18
C444

+VDDLTP18

2
1
C147
0.1U_0402_16V4Z

2

1

2

2
L10
1
2
BLM18PG121SN1D_0603
C148
4.7U_0805_10V4Z

+1.8VS

+1.8VS

80mA

0901 uninstall D39 without VB
0801 Change Vari-Bright circuit

LVDS_DIGON
BLON
LVDS_ENA_BL

R62 1
R63 1

2 0_0402_5%
2LCD_BLON 1
2 D39 @
0_0402_5%
CH751H-40PT_SOD323-2
R76
0_0402_5%
1
2
ENBKL
<34>
LVDS_ENA_BL <18>

UMA_ENVDD <18>
LVDS_BLON <18>

3

MIS.

TMDS_HPD(NC)
HPD(NC)
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N
TESTMODE

D9
D10

HPD

1
2
D12
R66
0_0402_5%
AE8 NB_THERMAL_DA
AD8 NB_THERMAL_DC
D13

AUX_CAL(NC)

<19>

SUS_STAT_R# <15>
SUS_STAT# <21>
PAD
PAD

Strap pin

T20
T21

1
2
R68
1.8K_0402_5%

RS780M_FCBGA528

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
RS780 VEDIO/CLK GEN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

12

of

46

A

B

C

D

E

Side-Port DDR2 SDRAM
512Mbits(32Mbx16)-64MB
U3D

1

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

MEM_CLKN
MEM_CLKP

K8
J8

CK
CK

K2

CKE

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

MEM_DQ15
MEM_DQ11
MEM_DQ13
MEM_DQ12
MEM_DQ8
MEM_DQ10
MEM_DQ9
MEM_DQ14
MEM_DQ3
MEM_DQ7
MEM_DQ1
MEM_DQ6
MEM_DQ5
MEM_DQ0
MEM_DQ4
MEM_DQ2

L8

CS

MEM_WE#

K3

WE

MEM_RAS#

K7

RAS

MEM_CAS#

L7

CAS

MEM_DM0
MEM_DM1

F3
B3

LDM
UDM

MEM_ODT

K9

ODT

MEM_DQS_P0
MEM_DQS_N0

F7
E8

LDQS
LDQS

MEM_DQS_P1
MEM_DQS_N1

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+MEM_VREF

MEM_BA2
3

MEM_CLKP
MEM_CLKN

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

AE12
AD12

MEM_CKP(NC)
MEM_CKN(NC)
MEM_COMPP(NC)
MEM_COMPN(NC)
RS780M_FCBGA528

L13
+VDDL

1

2

2
0_0603_5%

+1.8V_MEM_VDDQ

C152
1U_0603_10V6K

Layout Note: 50 mil for VSSDL

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)

Y17
W18
AD20
AE21

MEM_DQS_P0
MEM_DQS_N0
MEM_DQS_P1
MEM_DQS_N1

MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)

W17
AE19

MEM_DM0
MEM_DM1

IOPLLVDD18(NC)
IOPLLVDD(NC)

AE23
AE24

+NB_IOPLLVDD

IOPLLVSS(NC)

AD23

MEM_VREF(NC)

AE18

+MEM_VREF1

MEM_COMP_P and MEM_COMP_N trace
width >=10mils and 10mils spacing from
other Signals in X,Y,Z directions

15mA
1

2

1
2
BLM18PG121SN1D_0603
C149
2.2U_0603_6.3V4Z

+1.8VS
L11
1
2
BLM18PG121SN1D_0603

+1.8V_IOPLLVDD

L12

+1.1VS
1
1

2

C151
0.1U_0402_16V4Z

2

C150
2.2U_0603_6.3V4Z

2

AMD recommends 200 Ohm @ 100Mhz

3

ht

@ HY5PS561621F-25

Side Port disable,VREF need
connect to +1.8VS for DDR2
+1.8V_MEM_VDDQ

V15
W14

MEM_COMP_P
1
40.2_0402_1%
MEM_COMP_N
1
40.2_0402_1%

2
R70
2
R71

+1.8V_MEM_VDDQ

1

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

p.

MEM_CS#

W12
Y12
AD18
AB13
AB18
V14

om

2

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT

yc

2

MEM_CKE

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

//
m

100_0402_1%

+1.8V_MEM_VDDQ

AD16
AE17
AD17

tp
:

R69

MEM_BA0
MEM_BA1
MEM_BA2

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15

/x
/

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

su

BA0
BA1

MEM_A12
MEM_A11
MEM_A10
MEM_A9
MEM_A8
MEM_A7
MEM_A6
MEM_A5
MEM_A4
MEM_A3
MEM_A2
MEM_A1
MEM_A0
1

L2
L3

AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14

SBD_MEM/DVO_I/F

U4
MEM_BA0
MEM_BA1

1

PAR 4 OF 6

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12

+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ
+1.8VS

2

1
C159
2

22U_0805_6.3V6M

C158

2

1

0.1U_0402_16V4Z

C157

1

0.1U_0402_16V4Z

C156

1

1U_0402_6.3V4Z

C155

2

1U_0402_6.3V4Z

1

2

2
0_0805_5%
ZZZ2

220 ohm @ 100MHz,2A

VRAM_x76

1

1K_0402_1%

2

4

R75

2

0.1U_0402_16V4Z

C161

2

2

+MEM_VREF1

1

1K_0402_1%

C160

1

1

4

0.1U_0402_16V4Z
R74
2

+MEM_VREF

1K_0402_1%

R73
1

2

0.1U_0402_16V4Z

1
C154

2

1K_0402_1%

C153

1

0.1U_0402_16V4Z
R72
1
2

L14
1

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
RS780 Side-Port DDR2 SDRAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

13

of

46

A

B

C

D

E

U3F

0_0805_5%
2

0.6A

+VDDHT
0.1U_0402_16V4Z 0.1U_0402_16V4Z
C1651
1 C163 1
1
1
C166

2

1
C200

1
C201

1
C202

2
2
2
2
0.1U_0402_16V4Z 0.1U_0402_16V4Z

10mA

F9
G9
AE11
AD11

+1.8VS
+1.8VS
3

C208
1U_0402_6.3V4Z

25 mA

1

1

2

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

2

VDD33_1(NC)
VDD33_2(NC)

AE10
AA11
Y11
AD10
AB10
AC10

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

C185

+
2

L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34

PART 6/6

1

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

RS780M_FCBGA528

+1.8VS

70mA
4.7U_0805_10V4Z 2
0.1U_0402_16V4Z 2
0.1U_0402_16V4Z 2
0.1U_0402_16V4Z 2
0.1U_0402_16V4Z 2

H11
H12

RS780M_FCBGA528

/x
/

su
1

VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27

1
1
1
1
1

C203
C204
C205
C206
C207
3

+3VS

C209
1U_0402_6.3V4Z

60mA

1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z

2
2

C210
C211

ht

2

J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10

C196

2

1
C199

0.7A

C195

1
C198

0.1U_0402_16V4Z +VDDA18PCIE

10U_0805_10V4Z

1
C197
4.7U_0805_10V4Z

0.1U_0402_16V4Z

330U_D2E_2.5VM_R15

C194

4.7U_0805_10V4Z

10A

10U_0805_10V4Z

0_0805_5%
1
2

+NB_VDDC

0.1U_0402_16V4Z

L22

tp
:

+1.8VS

2

PAD-OPEN 4x4m

C193

4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

1

+1.1VS

C192

2

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

PJP606

0.1U_0402_16V4Z

2

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

0605 change to jump pad

C191

2

1
C184

1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1
C183

2
2

0.1U_0402_16V4Z

2

1
C182

2
2
2
2

p.

1
C181

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

1
1
1
1

C190

1
C180

AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17

C178
C179

+1.1VS

4.7U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z

C189

L18

+VDDHTTX

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

C167
C168
C169
C170
C171
C177

0.1U_0402_16V4Z

0.4A

H18
G19
F20
E21
D22
B23
A23

+VDDA11PCIE

C188

0.1U_0402_16V4Z

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

0.1U_0402_16V4Z

0_0805_5%
2

2

PART 5/6

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

C187

C174
2
2
2
0.1U_0402_16V4Z

2

VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

0.1U_0402_16V4Z

+VDDHTRX
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1 C175 1
1
C173
C176

FBMA-L11-201209-221LMA30T_0805
L16
1
2

2.5A

U3E
J17
K16
L16
M16
P16
R16
T16

C186

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

2

om

1

2
2
0.1U_0402_16V4Z

0.7A

C172
4.7U_0805_10V4Z

+1.2V_HT

C164

0.1U_0402_16V4Z

0_0805_5%
2

2

yc

L17
1

2

POWER

C162
4.7U_0805_10V4Z

//
m

L15
1

+1.1VS

A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25

GROUND

1

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

RS780 PWR/GND
Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

14

of

46

A

B

C

D

1

E

1

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

RS780 DFT_GPIO5 mux at CRT_VSYNC pull low to 3K
2
R81
2
@ R82

1
1K_0402_5%
1
1K_0402_5%

Enables the Test Debug Bus using GPIO.
1 : Disable (RS740) Disable (RX780, RS780)
0 : Enable (Rs740) Enable (RX780, RS780)
PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#

+3VS

su

/x
/

<12,17> CRT_VSYNC

2

om

p.

2

D3
2

<12> SUS_STAT_R#

2
150_0402_1%
@ CH751H-40PT_SOD323-2
1

PLT_RST# <12,20,26,27,33,34>

//
m

RS780 DFT_GPIO1

yc

DFT_GPIO1: LOAD_EEPROM_STRAPS

1
@ R83

<12> AUX_CAL

Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.

2
@ R84

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb

1
1K_0402_5%

RX780: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable

ht

<12> RS780_DFT_GPIO_0

3

tp
:

3

RS780 use HSYNC to enable SIDE PORT (internal pull high)
2
R85

<12,17> CRT_HSYNC

RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS740/RS780)
0 : Enable (RS740/RS780)

1
3K_0402_5%

2
1
+3VS
@ R248 10K_0402_5%

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

RS780 STRAPS
Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

15

of

46

A

B

C

D

+3VS_CLK

+3VS
+VDDCLK_IO

+1.2V_HT
R87
1
2
0_0805_5%

0.1U_0402_16V4Z
1

1

C225
10U_0805_10V4Z

R86
1
2
0_0805_5%

110mA

2

0.1U_0402_16V4Z
1

1

C226
2

C227

C228

2
0.1U_0402_16V4Z

2

250mA
1

0.1U_0402_16V4Z
1

1

C229

2

C230

2
0.1U_0402_16V4Z

E

1
C217
10U_0805_10V4Z

2

1

C218
0.1U_0402_16V4Z

2

1

C219
0.1U_0402_16V4Z

2

1

C220
0.1U_0402_16V4Z

2

1

C221
0.1U_0402_16V4Z

2

1

C222
0.1U_0402_16V4Z

2

1
@ C224

C223
0.1U_0402_16V4Z

2

1U_0402_6.3V4Z

2
1

1

C231

1

C232

1

C233

C234

1

1

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

EMI Caps for single end clock.
R249 1

2

22_0402_5%

R88

2

22_0402_5%

+3VS_CLK

<12> CLK_SBLINK_BCLK#
<12> CLK_SBLINK_BCLK

MiniCard_2

<27> CLK_PCIE_MCARD2#
<27> CLK_PCIE_MCARD2
+3VS_CLK
+VDDCLK_IO

tp
:

3

+3VS_CLK

2

2

SEL_SATA

1

/x
/

su

@ C235
5P_0402_50V8C
2
@ C236
2 5P_0402_50V8C
1

C622
2

1
CLK_CPU_BCLK <7>

1U_0402_6.3V4Z

2

2
0_0402_1%
2
0_0402_1%

2

R94
@ 261_0402_1%

CPU
CLK_CPU_BCLK# <7>

+3VS_CLK
+VDDCLK_IO
CLKREQ_NCARD#
CLKREQ_MCARD2#

CLKREQ_NCARD# <27>
CLKREQ_MCARD2# <27>

+3VS_CLK

CLK_SBSRC_BCLK <20>
CLK_SBSRC_BCLK# <20> SB
+3VS_CLK
CLKREQ_MCARD1#
CLKREQ4
1
2
R96
10K_0402_5%

SRC

CLKREQ_MCARD1#
+3VS_CLK

For ICS need to pull high.
For SLG is NC

+3VS_CLK
+VDDCLK_IO
3

SLG8SP626VTR_QFN72_10x10

NBGFX_CLK <12>
NBGFX_CLK# <12>

CLKREQ_LAN#
R104
8.2K_0402_5%

1

R103
8.2K_0402_5%

1.1V 200R/100R

1
R97
1
R98
CLKREQ_MCARD1#
1
R99
CLKREQ_LAN#
1
R101
CLKREQ4
1
@ R102
CLKREQ_MCARD2#

+VDDCLK_IO

2
1

@ R100
8.2K_0402_5%

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

1.8V 75R/100R

RS780

CLKREQ_NCARD#

ht

+3VS_CLK

VDD_CPU
VDD_CPU_I/O
VSS_CPU
CLKREQ_1#
CLKREQ_2#
VDD_A
VSS_A
VSS_SATA
SRC_6/SATA
SRC_6#/SATA#
VDD_SATA
CLKREQ_3#
CLKREQ_4#
SB_SRC_SLOW#
SB_SRC_0
SB_SRC_0#
VDD_SB_SRC
VDD_SB_SRC_IO

+3VS_CLK

+VDDCLK_IO

SCL
SDA
VDD_DOT
SRC_7#/27M
SRC_7/27M_SS
VSS_DOT
SRC_5#
SRC_5
SRC_4#
SRC_4
VSS_SRC
VDD_SRC_IO
SRC_3#
SRC_3
SRC_2#
SRC_2
VDD_SRC
VDD_SRC_IO

//
m

SB LINK

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

om

GND
<9,10,21,31> SMB_CK_CLK0
<9,10,21,31> SMB_CK_DAT0

yc

U6

Routing the trace at least 10mil

1
R93
CLK_CPU_BCLK#_R 1
R95

p.

22P_0402_50V8J

CLK_CPU_BCLK_R

1

RX780

NB

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55

2

2
+3VS_CLK
8.2K_0402_5%

VSS_48
48MHz_0
48MHz_1
VDD_48
XTAL_OUT
XTAL_IN
VSS_REF
REF_0/SEL_HTT66
REF_1/SEL_SATA
REF_2/SEL_27
VDD_REF
VDD_HTT
HTT_0/66M_0
HTT_0#/66M_1
VSS_HTT
PD#
CPU_K8_0
CPU_K8_0#

22P_0402_50V8J
2

CLK_XTAL_OUT
CLK_XTAL_IN

14.31818MHZ_20P_6X1430004201
1
C239

73

1

2
90.9_0402_1%

CLK_NBHT <12>
CLK_NBHT# <12>

1
R92

VSS_SRC
SRC_1#
SRC_1
SRC_0#
SRC_0
CLKREQ_0#
ATIGCLK_2#
ATIGCLK_2
VSS_ATIG
VDD_ATIG_IO
VDD_ATIG
ATIGCLK_1#
ATIGCLK_1
ATIGCLK_0#
ATIGCLK_0
SB_SRC_1#
SB_SRC_1
VSS_SB_SRC

C238

1

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

2

CLK_48M_USB_R

Y1

NB_OSC_14.318M <12>

1
R90

NB_OSC_14.318M

OSC_14M_NB

CLK_48M_USB <21>

2
158_0402_1%

NB_OSC_14.318M_R
SEL_SATA
27M_SEL
+3VS_CLK
+3VS_CLK

CLK_XTAL_IN

2

1
R89

+3VS_CLK

CLK_XTAL_OUT

CLK_48M_USB

CLK_48M_CR <28>

1

1

27M_SEL

SEL_SATA
0

1 *

configure as SATA output
*

CLKREQ_LAN# <26>
CLK_PCIE_LAN <26>
CLK_PCIE_LAN# <26>

GLAN

CLK_PCIE_NCARD <27>
CLK_PCIE_NCARD# <27>

New Card

NB CLOCK INPUT TABLE
NB CLOCKS

* default

0

RX780

RS780

HT_REFCLKP
100M DIFF
100M DIFF

100M DIFF
100M DIFF

configure as 27M and 27M_SS output

REFCLK_N

14M SE (1.8V)
NC

14M SE (1.1V)
vref

GFX_REFCLK

100M DIFF

100M DIFF(IN/OUT)*

REFCLK_P

27M_SEL
configure as normal SRC(SRC_6) output

+3VS_CLK

NB GFX

HT_REFCLKN
1
4

2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%

configure as SRC_7 output
* default

4

Use voltage divider resistor R379 & R380 to pull low
1

Compal Secret Data

Security Classification

configure as single-ended 66MHz output

NB_OSC_14.318M

2007/08/02

Issued Date

0*
configure as differential 100MHz output
* default

2008/08/02

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

Compal Electronics, Inc.

B

C

D

Clock generator
Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

16

of

46

A

B

C

D

E

CRT CONNECTOR

1

+5VS

@ D7

+CRT_VCC
F1

2

1

@ D6

+R_CRT_VCC
D4

DAN217_SC59

1

@ D5

DAN217_SC59

1

DAN217_SC59

1

1

1

2
1

RB491D_SOT23 1A_6VDC_MINISMDC110
C240
0.1U_0402_16V4Z

2

3

2

3

2

3

2

+3VS

JCRT

2

C244

2

2

2

/x
/
D_DDCCLK

SUYIN_070546FR015S265ZR
CONN@

5

Q7A
2N7002DW-7-F_SOT363-6

<12> UMA_CRT_CLK

D_DDCCLK

4
3
Q7B
2N7002DW-7-F_SOT363-6

1

1

2

2 470P_0402_50V8J

@ C249

@ C250

3

<12,15> CRT_VSYNC

tp
:

470P_0402_50V8J

5
1
P
OE#

2

A

G

<12,15> CRT_HSYNC

1
2
C248
0.1U_0402_16V4Z
2

Y

4

D_HSYNC

R112 1

2 0_0603_5%

HSYNC

R113 1

2 0_0603_5%

VSYNC

U7
SN74AHCT1G125GW_SOT353-5

3

6.8K_0402_5%
D_DDCDATA

6

5
1

1

//
m

1

2
<12> UMA_CRT_DAT

R111

A

G

R110
6.8K_0402_5%

+CRT_VCC
1
2
C247
0.1U_0402_16V4Z

3

R109
4.7K_0402_5%
2

R108
4.7K_0402_5%

yc

2

1

+CRT_VCC

P
OE#

om

SM01000E100 (S SUPPRE_ KING CORE FBMA-10-100505-800T 0402)
+3VS

2

16 GND
17 GND

Y

4

D_VSYNC

U8
SN74AHCT1G125GW_SOT353-5

1
@ C251

1

@ C252
2

3

ht

2

10P_0402_50V8J

C243

VSYNC

10P_0402_50V8J

2

1
C246

su

C242

1
C245

+CRT_VCC

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

p.

2

1

HSYNC

BLUE_L
6P_0402_50V8K

C241

1

D_DDCDATA

GREEN_L

6P_0402_50V8K

R107

1

RED_L

6P_0402_50V8K

2

R106
2

R105
2

1

6P_0402_50V8K

BLUE
6P_0402_50V8K

BLUE

2
1
150_0402_1%

<12>

1

GREEN

150_0402_1%

GREEN

1

RED

<12>

140_0402_1%

<12>

6P_0402_50V8K

L23
1
2
BLM15AG121SN1D_0402
L24
1
2
BLM15AG121SN1D_0402
L25
1
2
BLM15AG121SN1D_0402

RED

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

CRT Connector
Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

17

of

46

A

B

C

D

E

LVDS PWR circuit

LVDS CONN

+LCDVDD

+5VALW

B+

L26
1
2
FBMA-L11-201209-221LMA30T_0805 1

2

1

1.35A
INVPWR_B+

R114
220_0402_5%

+3VS

R115
1M_0402_5%

BKOFF#

1

2

C257
0.1U_0402_16V4Z

3

1

1

3

/x
/

su

LVDS_BLON <12>
LVDS_ENA_BL <12>

+USB_CAM

+5VS

0901 add R410
0619 Solve LED panel flash issue
+3VS

C253
680P_0402_50V7K

C264

R410

680P_0402_50V7K
@ C261

2 0_0402_5%

1

@ R55

2

10K_0402_1%

@ Q4
2N7002_SOT23-3
1

3

INV_PWM_LED

GND

3

EN

1
VOUT

R122

BP

4

@ 215K_0402_1%
2
C263

2

RT9193-39GB_SOT23-5

1

C265
0.1U_0402_16V4Z

R124

1

R123

1

10U_0805_10V4Z

@ 100K_0402_1%

0_0402_5%

2

Close to JLVDS
D8

@ R125

+USB_CAM

1
2
0_0402_5%

CAM_SHDN# <22>

USB20_N5

1

INV_PWM_R

10U_0805_10V4Z

VIN

2

5

1

680P_0402_50V7K
C258

U9
1

2

PJP604
PAD-OPEN 2x2m

2

C253 install when U9 is
RT9193-39GB

1

+3VS

USB_VCCA is +3.9V, R115:100K;
R114:215Kohm
G916 Vref=1.25V when U54 install
G916-390T1UF

2

1

2 0_0402_5%
2 0_0402_5%

1
1

p.

INV_PWM_R @ R395
BKOFF#_R @ R394

1

1

2

2

1
C256
4.7U_0805_10V4Z

Camera PWR circuit

2

LVDS_A0+ <12>
LVDS_A0- <12>
LCD_DDC_DAT <12>
LCD_DDC_CLK <12>

680P_0402_50V7K
@ C262

2N7002DW-7-F_SOT363-6
Q9B

1

LVDS_A0+
LVDS_A0LCD_DDC_DAT
LCD_DDC_CLK

2

ACES_88316-4000
conn@

+LCDVDD

0901 Delete D38 for without VB
@ C259

LVDS_A1+ <12>
LVDS_A1- <12>

1

80mil

1000P_0402_50V7K

0801 Change Vari-Bright circuit

680P_0402_50V7K

LVDS_A1+
LVDS_A1-

2A

C255

2

2

LVDS_A2+ <12>
LVDS_A2- <12>

R120
2.2K_0402_5%

om

LVDS_ACLK+ <12>
LVDS_ACLK- <12>

LVDS_A2+
LVDS_A2-

C260 @
680P_0402_50V7K

yc

USB20_N5 <21>
USB20_P5 <21>

LVDS_ACLK+
LVDS_ACLK-

INV_PWM <34>

1

5

<12> UMA_ENVDD

//
m

USB20_N5
USB20_P5

2

1

2

DMIC_DAT <29>
DMIC_CLK <29>
+USB_CAM

+LCDVDD

1

R397
+5VS
DAC_BRIG <34>

DAC_BRIG
DMIC_DAT
DMIC_CLK

0_0402_5%
1
2

S

R121
1
2
200_0805_5%

2
R119

SI2301BDS-T1-E3_SOT23-3
Q8

2

R118
1
2
100K_0402_5%

2

1

80mil

<34>
INV_PWM_R

+V_LOG

LCD_DDC_DAT 1
4.7K_0402_5%

Q9A
2N7002DW-7-F_SOT363-6

4

2 200_0402_5% R396

2
R117

1

R397 & R396 for RS780 VariBright function and EC control option
BKOFF#_R 1
INV_PWM_LED

LCD_DDC_CLK 1
4.7K_0402_5%

2

2

RS780 VariBright function

1

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

2

2

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

2
R116

D

2
41
42
43
44
45
46

BKOFF#
1
@ 4.7K_0402_5%

D

41
42
43
44
45
46

C623
680P_0402_50V7K

G

C254
680P_0402_50V7K

JLVDS

6 2

1

+3VS

S

1

4

VIN

IO1

2

3

IO2 GND

1

USB20_P5

@ PRTR5V0U2X_SOT143-4

2
G

R54

2

BKOFF#_R

100K_0402_1%

3

ht

tp
:

3

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
LCD CONN. / WebCam

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

18

of

46

A

B

C

D

E

+HDMI_5V_OUT

2

1

+3VS

R126
4.7K_0402_5%

HDMI_HPD

G

A

2

2

2.2K_0402_5%
Y

4

HPD

R131
100K_0402_5%
<12>

U10
SN74AHCT1G125GW_SOT353-5

HDMI_SDATA

C267
0.1U_0402_16V4Z

HDMI_SCLK

4
3
Q10B
2N7002DW-7-F_SOT363-6

<12> HDMICLK_UMA

su

/x
/

3

1
1

2

+3VS

1

R129
6.8K_0402_5%

5

5
1
1

P
OE#

0.1U_0402_16V4Z

1
R130

R128
6.8K_0402_5%

1
6
Q10A
2N7002DW-7-F_SOT363-6

<12> HDMIDAT_UMA

2
2

1

2

+HDMI_5V_OUT

C266

R127
4.7K_0402_5%
2

1

p.

2

HDMI_CLK+

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_CLKHDMI_CLK+

<11> TMDS_B_DATA0#
<11> TMDS_B_DATA0

C271 1
C272 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_TX0HDMI_TX0+

<11> TMDS_B_DATA1#
<11> TMDS_B_DATA1

C273 1
C274 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_TX1HDMI_TX1+

C275 1
C276 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_TX2HDMI_TX2+

2

2

D9

2

2

4

4

3

3

+HDMI_5V_OUT

1

2
0_0402_5%

2

HDMI_R_CK-

1

1

2

2

4

4

3

3

WCM-2012-900T_4P
1
2
R135
0_0402_5%

1

2
0_0402_5%

1

1

2

2

4

4

3

3

WCM-2012-900T_4P
1
2
@ R145
0_0402_5%

C268
0.1U_0402_16V4Z

HDMI_R_D0+

HDMI Connector
+HDMI_5V_OUT
JHDMI1
18 +5V
16 SDA
15 SCL
19 HP_DET

HDMI_R_D0-

HDMI_R_D1+

L29

HDMI_TX1-

65mA

1

1
WCM-2012-900T_4P
1
2
@ R133
0_0402_5%

@ R136

715_0402_1%
R144

2

RB491D_SOT23

1
1

+5VS

HDMI_SDATA
HDMI_SCLK
HDMI_HPD

CEC
Reserved

13
14

HDMI_R_CKHDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+

GND
GND
GND
GND
GND
GND
GND
GND
DDC/CEC_GND

2
5
8
11
20
21
22
23
17

12
10
9
7
6
4
3
1

CKCK+
D0D0+
D1D1+
D2D2+

3

CONN@ SUYIN_100042MR019S153ZL
HDMI_R_D1-

5
1

4

Q11A
Q11B
Q12A
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
1

1

HDMI_TX1+

3

+5VS
6

1
1
5

715_0402_1%
R140
R143
715_0402_1%

1
1

715_0402_1%
R142

@

2
2

R139
715_0402_1%

3

+5VS
6

+5VS

HDMI_TX2HDMI_TX2+

HDMI_R_CK+
+5VS

1

@ R134

HDMI_TX0-

ht

2
2

R138
715_0402_1%
R141
715_0402_1%

1
2

R137
715_0402_1%

//
m

HDMI_TX1HDMI_TX1+

2
0_0402_5%

L28

tp
:

HDMI_TX0HDMI_TX0+
2
1

HDMI_CLKHDMI_CLK+

2
2

3

1

L27

HDMI_TX0+

Q12B
2N7002DW-7-F_SOT363-6

4

<11> TMDS_B_DATA2#
<11> TMDS_B_DATA2

HDMI_CLK-

yc

<11> TMDS_B_CLK#
<11> TMDS_B_CLK

C269 1
C270 1

om

@ R132

2

HDMI_TX2+
@ R146

1

2
0_0402_5%

HDMI_R_D2+

L30

HDMI_TX2@

1

1

2

2

4

4

3

3

WCM-2012-900T_4P
1
2
R147
0_0402_5%

HDMI_R_D2-

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

HDMI
Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

19

of

46

B

C

D

E

STRAP PIN

Check AMD need pull low or not

+1.2V_HT

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

V23
V22
V24
V25
U25
U24
T23
T22

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N

U22
U21
U19
V19
R20
R21
R18
R17

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N

1 562_0402_1%
1 2.05K_0402_1%

2
2

+SB_PCIEVDD

T25
T24

PCIE_CALRP
PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

1

2

2

C286
1U_0402_6.3V4Z

Part 1 of 5

5

U12
4PLT_RST#

Y
A

Close to SB

P

B

PLT_RST# <12,15,26,27,33,34>

@ NC7SZ08P5X_NL_SC70-5

18P_0402_50V8J

4

R155
20M_0603_5%

1

NC

3

OSC

NC

2

Y2
SB_32KHO

2

GPP_CLK0P
GPP_CLK0N

L20
L19

GPP_CLK1P
GPP_CLK1N

M19
M20

GPP_CLK2P
GPP_CLK2N

N22
P22

GPP_CLK3P
GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

25M_X2

H_PROCHOT#
1
10K_0402_5%
<7,12> CPU_LDT_REQ#
<7> H_PROCHOT#

A3

X1

SB_32KHO

B3

X2

F23
F24
F22
G25
G24

R150 1

2 22_0402_5%

ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28

INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ

PAD

T22

PAD
PAD

T23
T24

AD3
AC4
AE2
AE3 PCI_PIRQH#

R156 2

G22 CLK_PCI_EC_R
E22
H24
H23
J25
J24
H25
PAD T25
H22
AB8
AD7
V15

2

R416 1

1 0_0402_5%

33_0402_5%

2

CLK_PCI_SIO <33>

3

ACCEL_INT <31>
CLK_PCI_EC <24,34>

STRAP PIN
EC & Debug
ZZZ1

LPC_DRQ# <33>

C3
C2
B2

SIRQ

<33,34>

RTC_CLK

<24>

STRAP PIN
+3VL

+SB_VBAT

+SB_VBAT

+RTCVCC_R
R161
120_0402_5%
1
2

1
C290

1

W=20mils

C291
2

H_PWRGD_SB
0.1U_0402_16V4Z

+RTCBATT
D10
2

1

DAN202U_SC70
J1
@ JUMP_43X39

R163
3
1
2
W=20mils
1K_0402_5%

W=20mils
W=20mils

0_0402_5%

JBATT1
1
2
3
4

1
2
GND
GND

CONN@ ACES_85205-02001
1

2
1U_0402_6.3V4Z

+RTCVCC

R162
120_0402_5%
1
2

+RTCBATT_R

9/20 SP020008T00

1

4

<24>
<24>
<24>
<24>
<24>
<24>

22_0402_5%
R157 1
2 CLK_PCI_EC
LPCCLK1 <24>
LPC_AD0 <33,34>
LPC_AD1 <33,34>
LPC_AD2 <33,34>
LPC_AD3 <33,34>
LPC_FRAME# <33,34>

R160
2

1

PCB-MB
RTCCLK
INTRUDER_ALERT#
VBAT

9/20 SA00001S510 S IC 218S7EALA11FG SB700 BGA 528P SB 0FH

1

PCI_CLK3 <24>
PCI_CLK4 <24>
PCI_CLK5 <24>

LPCCLK1

218S7EALA11FG_BGA528_SB700

<7> H_PWRGD_CPU

<24>

PCI_SERR# <34>

RTC

<7,12> LDT_STOP#
<7>
LDT_RST#

CPU_LDT_REQ#
H_PROCHOT#
H_PWRGD_SB

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#

om

PCI INTERFACE

SLT_GFX_CLKP
SLT_GFX_CLKN

J19
J18

SB_32KHI

ht

Close to SB

2
R159

CPU_HT_CLKP
CPU_HT_CLKN

M23
M22

J20

18P_0402_50V8J

+3VS

NB_HT_CLKP
NB_HT_CLKN

P17
M18

tp
:

3

1
2

C289

OSC

M24
M25

//
m

SB_32KHI
32.768KHZ_12.5PF_9H03200413

2
1

1

N1

yc

C288

NB_DISP_CLKP
NB_DISP_CLKN

CLOCK GENERATOR

@ R154 20M_0402_5%
1
2

K23
K22

LPC

1
33_0402_5%

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

CPU

2
R153

N25
N24

RTC XTAL

2

<16> CLK_SBSRC_BCLK
<16> CLK_SBSRC_BCLK#

PCIRST#

CLK_PCI_SIO_R

su

3

1

P4
P3
P1
P2
T4
T3

STRAP PIN

1

@ 0.1U_0402_16V4Z
2
NB_RST#_R

C285
10U_0805_10V4Z

G

2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

R151
R152
+PCIE_VDDR
L31
1
2
BLM18PG121SN1D_0603
1

+3VALW

C287

2
2
2
2
2
2
2
2

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41

2

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

1
1
1
1
1
1
1
1

A_RST#

/x
/

<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>

C277
C278
C279
C280
C281
C282
C283
C284

N2

PCI CLKS

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

PCICLK2

SB700

NB_RST#_R

p.

1

<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>

@

U11A

PCI EXPRESS INTERFACE

1
R148

2 NB_RST#_R
8.2K_0402_5%

2

A

4

R403
<43> H_PWRGD

1

2
0_0402_5%

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
SB700-PCIE/PCI/ACPI/LPC/RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

20

of

46

A

B

C

CH751H-40PT_SOD323-2
1
2
D33

<39,41> 3/5V_OK

D

E

EC_RSMRST#

U11D

2 2.2K_0402_5%

SMB_CK_CLK0

R172

1

2 2.2K_0402_5%

SMB_CK_DAT0

EC_RSMRST#

<34> EC_RSMRST#

D3

SB700 has internal PD

R173
100K_0402_5%
1

+3VALW
R174

1

2 2.2K_0402_5%

SMB_CK_CLK1

R175

1

2 2.2K_0402_5%

SMB_CK_DAT1

<29> SB_SPKR
<9,10,16,31> SMB_CK_CLK0
<9,10,16,31> SMB_CK_DAT0
<27> SMB_CK_CLK1
<27> SMB_CK_DAT1
+3VS
R404

2

SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1

2

+3VALW

SB_GPIO5

1
2
10K_0402_5%

AE18
AD18
AA19
W17
V17
W20
W21
AA18
W18
K1
K2
AA20
Y18
C1
Y19
G5

R179 0_0402_5%
EXP_CPPE#
1
2

<34> EC_LID_OUT#
<27> EXP_CPPE#
<26> LAN_DSM#
R181
R182

<29> HDA_BITCLK_CODEC
<29> HDA_SDOUT_CODEC
<29> HDA_SDIN0

33_0402_5%
33_0402_5%

1
1

2
2

R247 0_0402_5%
HDABITCLK 2
1HDA_BITCLK
HDA_SDOUT
HDA_SDIN0

HDA_SYNC

<29> HDA_SYNC_CODEC
<29> HDA_RST#_CODEC

3

R183

33_0402_5%

1

2

R184

33_0402_5%

1

2

HDARST#

ht

+3VS

HDABITCLK
6
@ R405
2
1 5
10K_0402_5%
1
4
2

CLKIN

1

CLKOUT

NC

2

SSON

NC

8

GND

SS

3

ASM3P623S00BF-08TR_TSSOP8

HDA_BITCLK

A11
B11

USB_HSD8P
USB_HSD8N

C10
D10

USB20_P8
USB20_N8

USB_HSD7P
USB_HSD7N

G11
H12

USB20_P7
USB20_N7

USB_HSD6P
USB_HSD6N

E12
E14

USB20_P6
USB20_N6

USB_HSD5P
USB_HSD5N

C12
D12

USB20_P5
USB20_N5

USB_HSD4P
USB_HSD4N

B12
A12

USB20_P4
USB20_N4

USB_HSD3P
USB_HSD3N

G12
G14

USB20_P3
USB20_N3

USB_HSD2P
USB_HSD2N

H14
H15

USB20_P2
USB20_N2

USB_HSD1P
USB_HSD1N

A13
B13

USB20_P1
USB20_N1

USB_HSD0P
USB_HSD0N

B14
A14

USB20_P0
USB20_N0

IMC_GPIO8
IMC_GPIO9
IMC_PWM0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PWM1/IMC_GPIO15
IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17

A18
B18
F21
D21
F19
E20
E21
E19
D19
E18

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO42
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
AZ_SYNC
AZ_RST#
AZ_DOCK_RST#/GPM8#

IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25

G20
G21
D25
D24
C25
C24
B25
C23

IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

H19
H20
H21
F25

IMC_GPIO0
IMC_GPIO1
SPI_CS2#/IMC_GPIO2
IDE_RST#/F_RST#/IMC_GPO3

D22
E24
E25
D23

IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7

1

2
R166

USB20_P8 <27>
USB20_N8 <27>

USB-8 NEW Card

USB20_P7 <28>
USB20_N7 <28>

USB-7 CardReader

USB20_P6 <27>
USB20_N6 <27>

USB-6 WLAN

USB20_P5 <18>
USB20_N5 <18>

USB-5 USB Camera

USB20_P4 <32>
USB20_N4 <32>

USB-4 FPR

USB20_P3 <32>
USB20_N3 <32>

USB-3 BT

USB20_P2 <32>
USB20_N2 <32>

USB-2 Right Side (Upper)

USB20_P1 <32>
USB20_N1 <32>

USB-1 Right side (E-SATA Combo)

USB20_P0 <32>
USB20_N0 <32>

USB-0 Right side (S/W Debug Port)

2

STRAP PIN
STRAP PIN

GPIO16 <24>
GPIO17 <24>

3

218S7EALA11FG_BGA528_SB700
@ R406
2

@ U30
7 VDD

@C626

M1
M2
J7
J8
L8
M3
L6
M4
L5

tp
:

STRAP PIN
82P_0402_50V8J
HDA_BITCLK_CODEC
2
82P_0402_50V8J
HDA_SDOUT_CODEC
2

0.1U_0402_16V4Z

USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GPM5#
USB_OC4#/IR_RX0/GPM4#
USB_OC3#/IR_RX1/GPM3#
USB_OC2#/GPM2#
USB_OC1#/GPM1#
USB_OC0#/GPM0#

PAD T27

<24,34> HDARST#

C624
1
C625
1

B9
B8
A8
A9
E5
F8
E4

yc

<27> MINI_PCIE_WAKE#

PCIE_WAKE#
1
0_0402_5%
1
@ 0_0402_5%

2
R177
2
R178

USB_HSD9P
USB_HSD9N

SATA_IS0#/GPIO10
CLK_REQ3#/SATA_IS1#/GPIO6
SMARTVOLT1/SATA_IS2#/GPIO4
CLK_REQ0#/SATA_IS3#/GPIO0
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LLB#/GPIO66
SMARTVOLT2/SHUTDOWN#/GPIO5
DDR3_RST#/GEVENT7#

//
m

<26> LAN_PCIE_WAKE#

E11
F11

RSMRST#

1

R176
10K_0402_5%

H11
J10

USB_HSD10P
USB_HSD10N

su

1

USB_HSD11P
USB_HSD11N

USB 2.0

0605 remove 0 ohm resisters
R171

<7> H_THERMTRIP#
<12> NB_PWRGD

F7
E8

GPIO

+3VS

USB_FSD12P
USB_FSD12N

CLK_48M_USB <16>
USB_RCOMP 1
11.8K_0402_1%

/x
/

SB_TEST0

E6
E7

p.

SB_TEST1

USB_FSD13P
USB_FSD13N

INTEGRATED uC

SB_TEST2

2
@ 2.2K_0402_5%
2
@ 2.2K_0402_5%
2
@ 2.2K_0402_5%

GATEA20
KB_RST#
EC_SCI#
EC_SMI#

2

1
R168
1
R169
1
R170

<34>
<34>
<34>
<34>

USB MISC

+3VALW

G8

USB OC

SUS_STAT#

INTEGRATED uC

2
4.7K_0402_5%

C8

USB_RCOMP

om

1
R167

USBCLK/14M_25M_48M_OSC

USB 1.1

demo circuit
<34> SLP_S3#
<34> SLP_S5#
<34> PWRBTN_OUT#
<7,34,43> SB_PWRGD
<12> SUS_STAT#

+3VS

Part 4 of 5

SB700
PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S2/GPM9#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST2
TEST1
TEST0
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD

ACPI / WAKE UP EVENTS

E1
E2
LID use RI#
H7
F5
G1
H2
H1
SUS_STAT#
K3
SB_TEST2
H5
SB_TEST1
H4
SB_TEST0
H3
Y15
W15
K4
K24
F1
PAD T26
J2
PCIE_WAKE#
H6
F2
H_THERMTRIP# J6
NB_PWRGD
W14

HD AUDIO

1

+3VS

2
1
10K_0402_5%
@ R407
10K_0402_5%
4

1

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
SB700 USB/AC97

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P
Sheet

Monday, September 08, 2008
E

21

of

46

A

B

E

1

Y3

D

SATA_X1

1 C292
1

10P_0402_50V8J 2

C

R185
10M_0402_5%

10P_0402_50V8J 2

2

2

25MHz_20pF_6X25000017
1 C293

SATA_X2

1

1

U11B

SATA_TXP2
SATA_TXN2

C298
C299

1
1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_STX_DRX_P1
SATA_STX_DRX_N1

<25> SATA_RXN1_C
<25> SATA_RXP1_C
SATA_STX_DRX_P2
SATA_STX_DRX_N2

<32> SATA_RXN2_C
<32> SATA_RXP2_C

2

2
R191

+3VS

R192 10K_0402_5%
1
2

+PLLVDD_SATA

1

1

1mA

L33

AD13
AE13

SATA_TX3P
SATA_TX3N

AB14
AC14

SATA_RX3N
SATA_RX3P

AE14
AD14

SATA_TX4P
SATA_TX4N

AD15
AE15

SATA_RX4N
SATA_RX4P

AB16
AC16

SATA_TX5P
SATA_TX5N

AE16
AD16

SATA_RX5N
SATA_RX5P

V12

SATA_CAL

Y12

SATA_X1

SATA_X2

AA12

SATA_X2
SATA_ACT#/GPIO67

77mA
AA11

PLLVDD_SATA

W12

XTLVDD_SATA

+XTLVDD_SATA
2

1

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23

SPI_DI/GPIO12
SPI_DO/GPIO11
SPI_CLK/GPIO47
SPI_HOLD#/GPIO31
SPI_CS1#/GPIO32

G6
D2
D1
F4
F3

LAN_RST#/GPIO13
ROM_RST#/GPIO14

U15
J1

FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49

M8
M5
M7

FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52

P5
P8
R8

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64

C6
B6
A6
A5
B5

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

A4
B4
C4
D4
D5
D6
A7
B7

AVDD

F6

Local Frame Buffer Strapping List
Copy from Becks.

LFB_ID2 LFB_ID1 LFB_ID0

AVSS

G7

218S7EALA11FG_BGA528_SB700

Hynix

0

0

0

Qimonda

0

0

1

Samsung

0

1

0

LFB_ID0 to LFB_ID2 got internal PU 10K to S5.
2

+3VALW
+3VALW

@ R187
1
2
10K_0402_5%
1
2
@ 10K_0402_5%
R189

+3VALW
ISOLATEB <26>
HDD_HALTLED# <35>
THERMAL_DC R193

LFB_ID2

@ R186 1

2 1K_0402_5%

LFB_ID1

@ R188 1

2 1K_0402_5%

LFB_ID0

@ R190 1

2 1K_0402_5%

0605 Change value to solve AC
plugged/unplugged power status
issue.

2 0_0402_5%
WLOFF# <27>
BT_COMBO_EN# <27>

1

R408
300K_0402_5%

EC_THERM# <34>
AC_IN_SB
BT_OFF
<32>
CAM_SHDN# <18>

2
1
AC_IN
D34
CH751H-40PT_SOD323-2

<34,38>

LFB_ID0
LFB_ID1
LFB_ID2

3

5mA

ht

C304
1U_0402_6.3V4Z

SATA_RX2N
SATA_RX2P

tp
:

3

SATA_TX2P
SATA_TX2N

AE12
AD12

C303
1U_0402_6.3V4Z

+3VS
2
1
BLM18PG121SN1D_0603

SATA_RX1N
SATA_RX1P

AB12
AC12

HW MONITOR

2

AD11
AE11

//
m

C302
1U_0402_6.3V4Z

2

SATA_TX1P
SATA_TX1N

W11

L32
2
1
BLM18PG121SN1D_0603

SATA_RX0N
SATA_RX0P

AE10
AD10

SATA_CAL
1
1K_0402_1%
SATA_X1

<35> SATA_LED#

+1.2V_HT

AB10
AC10

1

<32>
<32>

<25> SATA_RXN0_C
<25> SATA_RXP0_C

AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24

2

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

IDE_IORDY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DRQ
IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

/x
/

1
1

Part 2 of 5

su

C296
C297

SATA_TX0P
SATA_TX0N

p.

SATA_TXP1
SATA_TXN1

SB700

AD9
AE9

om

<25>
<25>

SATA_STX_DRX_P0
SATA_STX_DRX_N0

ATA 66/100/133

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

SPI ROM

1
1

yc

C294
C295

SERIAL ATA

SATA_TXP0
SATA_TXN0

SATA PWR

<25>
<25>

+SB_AVDD
1
1

2
C305
0.1U_0402_16V4Z

2

+3VALW
L34
2
1
BLM18PG121SN1D_0603
C306
2.2U_0603_6.3V4Z

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
SB700 SATA/IDE/SPI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

22

of

46

C

2
2
2
2
2
2
2
2

1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

L21
L22
L24
L25

0.45A/30mil/3vias

0.8A/50mil/4vias

+PCIE_VDDR

1 10U_0805_10V4Z

C333
C334
C335
C337
C338
C340

2
2
2
2
2
2

1
1
1
1
1
1

L37

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7

C346 2

1 10U_0805_10V4Z

C347
C349
C351
C352

2
2
2
2

AA14
AB18
AA15
AA17
AC18
AD17
AE17

10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

A17
A24
B17
J4
J5
L1
L2

+S5_3V R197 1

S5_1.2V_1
S5_1.2V_2

G2
G4

+S5_1.2V

+3VALW
2 0_0805_5%

10U_0805_10V4Z 1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

A10
B10

L39

2
2
2
2
2
2
2

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5

PLL

1
1
1
1
1
1
1

A16
B16
C16
D16
D17
E17
F15
F17
F18
G15
G17
G18

10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

V5_VREF

AE7

AVDDCK_3.3V

J16

AVDDCK_1.2V

AVDDC

1

2 C353

2
2

1
1

0_0603_5%

1U_0402_6.3V4Z
0.1U_0402_16V4Z

1K_0402_5% 2

+AVDDCK_3.3V

K17

C357
+AVDDCK_1.2V 0.1U_0402_16V4Z

E9

+AVDDC
L41

2

2

1

C358
1U_0603_10V4Z
1

2.2U_0603_6.3V4Z
0.1U_0402_16V4Z

+AVDDCK_1.2V

L42

1

2

1

C365

2

1

C366

0.1U_0402_16V4Z

L43

D11

1

1
1

C348
C350

1 R198

+5VS

2

+3VS

1

0.1U_0402_16V4Z

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20

A15
B15
C14
D8
D9
D11
D13
D14
D15
E15
F12
F14
G9
H9
H17
J9
J11
J12
J14
J15
K10
K12
K14
K15

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24

F9

PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8
AVSSC

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21

Part 5 of 5

AVSSCK

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

1

2

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25
3

L17

218S7EALA11FG_BGA528_SB700

+1.2V_HT

2

1

C367

2

1

C368

2 0_0805_5%

2.2U_0603_6.3V4Z

T10
U10
U11
U12
V11
V14
W9
Y9
Y11
Y14
Y17
AA9
AB9
AB11
AB13
AB15
AB17
AC8
AD8
AE8

H18
J17
J22
K25
M16
M17
M21
P16

CH751H-40PT_SOD323-2

0_0805_5%
2

2.2U_0603_6.3V4Z

+AVDDCK_3.3V

2
2

2 0_0805_5% +3VALW

1

218S7EALA11FG_BGA528_SB700

ht

+1.2VALW
L38

C354
C355

+V5_VREF

//
m

3

2 0_0805_5%

1

C339
C341
C342
C343
C344
C345

1
1
1
1
1
1

0_0603_5%

10U_0805_10V4Z

tp
:

L40

+AVDD_USB

2 C336

2
2
2
2
2
2

+1.2VALW

+1.2_USB

USB_PHY_1.2V_1
USB_PHY_1.2V_2

USB I/O

1.25A/50mil/4vias

C356
C359
C360
C361
C362
C363
C364

+1.2V_HT

C328
0.1U_0402_16V4Z

0.1A/30mil/2vias

+1.2V_SATA

2 0_0805_5%

1

1
1
1
1

P18
P19
P20
P21
R22
R24
R25

1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

SB700

C310
C312
C314
C316
C318
C320

1
1
1
1
1
1

L35
2
1
BLM18PG121SN1D_0603

1U_0402_6.3V4Z
1U_0402_6.3V4Z

+3VALW

2
2
2
2
2
2

POWER

3.3V_S5 I/O

C332 2

1.25A/50mil/4vias
+1.2V_HT

+1.2V_CKVDD
1

2

CORE S5

2

1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

2 0_0805_5%

1

A-LINK I/O

+1.2V_HT

VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4

SATA I/O

L36

Y20
AA21
AA22
C329
AE25
1U_0402_6.3V4Z

CLKGEN I/O

1

1

+1.2V_HT

0.3A/30mil/2vias

+3.3V_SB_IDE
2

IDE/FLSH I/O

+3VS

0_0603_5%
R196 1
2

2
0_0805_5%
2 C308

su

1
1
1
1
1
1
1
1

Part 3 of 5

1
R195
10U_0805_10V4Z

p.

C309
C311
C313
C315
C317
C319
C321
C322

10U_0805_10V4Z

U11E

+1.2V_SB_CORE

om

1

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

yc

2

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12

L15
M12
M14
N13
P12
P14
R11
R15
T16

CORE S0

C307
1

SB700

PCI/GPIO I/O

+3VS

L9
M9
T15
U9
U16
U17
V8
W7
Y6
AA4
AB5
AB21

E

0.6A/50mil/4vias

U11C

0.45A/40mil/3vias

D

GROUND

B

/x
/

A

+3VS

2

1 C369

2

1 C370

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SB700 PWR/GND
Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

23

of

46

B

C

REQUIRED STRAPS

E

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

PCI_CLK2

PCI_CLK3

PCI_CLK4

PCI_CLK5 AZ_RST_CD# LPC_CLK1

RTC_CLK

BOOTFAIL
TIMER
ENABLED

USE
DEBUG
STRAPS

RESERVED

RESERVED

INTERNAL
RTC

ENABLE PCI
MEM BOOT

CLKGEN
ENABLED

LPC_CLK0

GP17

EC
ENABLED

Internal pull up

BOOTFAIL
TIMER
DISABLED

IGNORE
DEBUG
STRAPS

DISABLE PCI CLKGEN
MEM BOOT
DISABLED

DEFAULT

DEFAULT

DEFAULT

@

+3VALW

+3VALW

@

@

@

+3VALW

su
R217
2.2K_0402_5%
2
1

R216
10K_0402_5%
2
1

R215
2.2K_0402_5%
2
1

p.

2

@

@

yc

DEBUG STRAPS

R214
10K_0402_5%
2
1

@

om

R212
10K_0402_5%
2
1

@

R213
10K_0402_5%
2
1

R211
10K_0402_5%
2
1

R210
10K_0402_5%
2
1

R209
10K_0402_5%
2
1

2

+3VALW

R207
10K_0402_5%
2
1

@

L,L = FWH ROM

R206
10K_0402_5%
2
1

@

@

L,H = LPC ROM (Default)

DEFAULT

/x
/

@

@

<20>
PCICLK2
<20> PCI_CLK3
<20>
PCI_CLK4
<20>
PCI_CLK5
<20,34> CLK_PCI_EC
<20>
LPCCLK1
<20>
RTC_CLK
<21,34> HDARST#
<21>
GPIO17
<21>
GPIO16

EC
DISABLED

R205
10K_0402_5%
2
1

R204
10K_0402_5%
2
1

+3VALW

R203
10K_0402_5%
2
1

+3VALW

R202
10K_0402_5%
2
1

+3VS

R201
10K_0402_5%
2
1

+3VS

R200
10K_0402_5%
2
1

+3VS

R199
10K_0402_5%
2
1

+3VS

H,L = SPI ROM

EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)

DEFAULT

1

H,H = Reserved

DEFAULT

PULL
LOW

GP16

R208
2.2K_0402_5%
2
1

PULL
HIGH

1

D

R218
2.2K_0402_5%
2
1

A

//
m

SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

PCI_AD28
PULL
HIGH

PCI_AD27

PCI_AD26

PCI_AD25

PCI_AD24

PCI_AD23

USE PCI
PLL

USE ACPI
BCLK

USE IDE
PLL

USE DEFAULT
PCIE STRAPS

RESERVED

DEFAULT

DEFAULT

DEFAULT

DEFAULT

USE
SHORT
RESET

BYPASS
PCI PLL

BYPASS
ACPI
BCLK

BYPASS IDE
PLL

USE EEPROM
PCIE STRAPS

R221
2.2K_0402_5%
2
1

R222
2.2K_0402_5%
2
1

3

ht

PULL
LOW

DEFAULT

R220
2.2K_0402_5%
2
1

tp
:

3

USE
LONG
RESET

@

@

@

@

R224
2.2K_0402_5%
2
1

@

R223
2.2K_0402_5%
2
1

PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
R219
2.2K_0402_5%
2
1

<20>
<20>
<20>
<20>
<20>
<20>

@

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
SB700 STRAPS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

24

of

46

A

B

C

D

E

HDD Connector
JHDD

1

1

1

1
C372

2

1
C373

2
0.1U_0402_16V4Z

GND
A+
AGND
BB+
GND

C374
0.1U_0402_16V4Z

C371
10U_0805_10V4Z

1.8A

2
2
0.1U_0402_16V4Z

Pleace near HD CONN

1

1
@ C378

2

1
@ C379

2
0.1U_0402_16V4Z

2
2
0.1U_0402_16V4Z

24
23

GND
GND

SATA_TXP0
SATA_TXN0
0.01U_0402_16V7K
SATA_RXN0
2
SATA_RXP0
2
0.01U_0402_16V7K

+3VS

+5VS

0605 add 150uF Cap to solve hot-plug
+5VS
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

1
C381

2

1
C382

2

1
C383

C384

2
0.1U_0402_16V4Z

2

+ C643
150U_D_6.3VM

+3VS

+5VS

2

Pleace near HD CONN

VCC5
VCC5
VCC5
VCC3
VCC3
VCC3
GND
GND

GND
TX+
TXGND
RXRX+
GND
GND

18

GND

GND

yc

+3VS
10U_0805_10V4Z

JP3
16
15
14
13
12
11
10
9

1
2
3
4
5
6
7
8

om

1

p.

Multi-Bay Connector-option

2

10U_0805_10V4Z

1

SATA_RXN0_C <22>
SATA_RXP0_C <22>

Near CONN side.
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

OCTEK_SAT-22EH1G_RV
CONN@

Pleace near HD CONN

SATA_TXP0 <22>
SATA_TXN0 <22>

1 C375 SATA_RXN0_C
1 C376 SATA_RXP0_C

su

@

1

C380
0.1U_0402_16V4Z

10U_0805_10V4Z
C377

+3VS

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

1
2
3
4
5
6
7

/x
/

+5VS

0.1U_0402_16V4Z

0.01U_0402_16V7K
SATA_RXN1
2
SATA_RXP1
2
0.01U_0402_16V7K

2

SATA_TXP1
SATA_TXN1

SATA_TXP1 <22>
SATA_TXN1 <22>

1 C385 SATA_RXN1_C
1 C386 SATA_RXP1_C

SATA_RXN1_C <22>
SATA_RXP1_C <22>

Near CONN side.

17

CONN@ TYCO_2023087

2

1
C387
@

1
@ C388

2
0.1U_0402_16V4Z

2

Pleace near HD CONN

C390

2
0.1U_0402_16V4Z

3

ht

tp
:

3

1
@ C389

//
m

1

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

HDD/CDROM
Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

25

of

46

A

B

C

D

1025 add to meet HP request
+3VALW

C397

68mA

0.1U_0402_16V4Z
@
R226

Close to Pin16,37,46,53

+3V_LAN

+3V_LAN

1

2

2

1

1

E

C398

+3V_LAN

0.1U_0402_16V4Z
2
2
C399
C400

2

1

1

2

C401

C402

0.1U_0402_16V4Z

2
0_1206_5%

1

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

S

Close to Pin2 & pin59
3

D

1

2
G

1

e
Hk
uo
7
h
.
c
4

1

Q13
AP2305GN

+LAN_VDD12

<34> LAN_POWER_OFF

+LAN_VDD12

+CTRL_18

0.1U_0402_16V4Z

L45
1
2
4.7UH_1008HC-472EJFS-A_5%_1008

Close to Pin1

2

C409
22U_0805_6.3VAM

Place Close to Chip

2

2

1

1

2

C403

1

C410

C404

1

2

C405

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

C406

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

2

C407

1

C408

1

0.1U_0402_16V4Z

U13

<16> CLK_PCIE_LAN#
2

<12,15,20,27,33,34> PLT_RST#
+CTRL_18
+LAN_VDD12
R229

+3V_LAN

0_0603_5%

R230 1
R231
1
2
0_0402_5%

<21> LAN_PCIE_WAKE#
<22> ISOLATEB

1

+3VS

2

33

CLKREQB

26

REFCLK_P

27

REFCLK_N

20

PERSTB

1

SROUT12

5

FB12

62

LED3
LED2
LED1
LED0

54
55
56
57

LAN_LINK#
LAN_ACTIVITY#

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3

3
4
6
7
9
10
12
13

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-

64

RSET

GLAN_WAKE#

19

LANWAKEB

ISOLATEB

36

ISOLATEB

LAN_X1

60

CKTAL1

LAN_X2

61

CKTAL2

65

EXPOSE_PAD

25

EGND

DVDD12
DVDD12
DVDD12
DVDD12
DVDD12
DVDD12

21
32
38
43
49
52

EVDD12
EVDD12

22
28

VDD33
VDD33
VDD33
VDD33

16
37
46
53

@
R232

ISOLATEB

31

R233
15K_0402_5%

15
17
18
34
35
39
40
41
42

EGND
NC
NC
NC
NC
NC
NC
NC
NC
NC

VDDSR

63

AVDD33
AVDD33

2
59

AVDD12
AVDD12
AVDD12
AVDD12

8
11
14
58

IGPIO
OGPIO

50
51

RTL8111C-GR_QFN64_9X9
U15

LAN_MDI2LAN_MDI2+
LAN_MDI1LAN_MDI1+
LAN_MDI3LAN_MDI3+

TCT1
TD1+
TD1TCT2
TD2+
TD2TCT3
TD3+
TD3TCT4
TD4+
TD4-

MCT1
MX1+
MX1MCT2
MX2+
MX2MCT3
MX3+
MX3MCT4
MX4+
MX4-

24
23
22
21
20
19
18
17
16
15
14
13

C426
RJ45_MIDI0RJ45_MIDI0+

25MHZ_20P

C421

+LAN_EVDD12

+3V_LAN

1

2

L47

C423
22U_0805_6.3VAM

1

2

1

2

0.01U_0402_16V7K
0.01U_0402_16V7K

2

2

1

2

C436

1

1

0.1U_0402_16V4Z

C417

1

0.1U_0402_16V4Z

2

L46

+LAN_VDD12

0_0603_5%
2

C419

2

C420

0.1U_0402_16V4Z
1

1U_0402_6.3V6K

close to pin 28 for EMI

LAN Conn.
+3V_LAN
LAN_ACTIVITY#

2
0.01U_0402_16V7K
2
0.01U_0402_16V7K

C429

1

2
0.01U_0402_16V7K

C430

1

2
0.01U_0402_16V7K

1
@ R235
1
R236

R234 2

1 300_0402_5%

1

2
10K_0402_5%
2
0_0402_5%

@
C425
68P_0402_50V8K 2

+3VALW
LAN_DSM# <21>

R237
1
2
75_0402_1%
R238
1
2
75_0402_1%
R239
1
2
75_0402_1%
R241
1
2
75_0402_1%

@
C428
68P_0402_50V8K

2

R240 2

Yellow LED+

14

Yellow LED-

3

SHLD1

RJ45_MIDI3-

8

PR4-

RJ45_MIDI3+

7

PR4+

RJ45_MIDI1-

6

PR2-

RJ45_MIDI2-

5

PR3-

RJ45_MIDI2+

4

PR3+

RJ45_MIDI1+

3

PR2+

RJ45_MIDI0-

2

PR1-

RJ45_MIDI0+

1

PR1+

11

+3V_LAN
1

LAN_LINK#

13

1 300_0402_5%

12

9

DETCET PIN2

10

SHLD1

15

Green LED+
Green LEDFOX_JM36113-P1123-7F
CONN@

LAN_LINK#

LANGND
1

@ D36
PSOT24C_SOT23-3

1000P_1808_3KV7K

2

1

C431
0.1U_0402_16V4Z

2

C432
4.7U_0805_10V4Z
4

1

C433
1
2

16

DETECT PIN1

LAN_ACTIVITY#

C437

0.01U_0402_16V7K
2 0.01U_0402_16V7K

Compal Secret Data

Security Classification

Place these components
colsed to LAN chip

2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
RTL8111C/8102E 10/100/1000 LAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

2

C416

27P_0402_50V8J

0.1U_0402_16V4Z

RJ45_GND
C435

0.1U_0402_16V4Z

1

2

JRJ45

HP PoE solution
1

1

C415

+LAN_EVDD12

C424

4

C434

C414

C422

NS692405

1

1

0.1U_0402_16V4Z
2

1

+LAN_VDD12

1

C413

+3V_LAN

0_0603_5%

+3V_LAN

1

RJ45_MIDI1RJ45_MIDI1+

1

27P_0402_50V8J
2

C427
RJ45_MIDI2RJ45_MIDI2+

RJ45_MIDI3RJ45_MIDI3+

+LAN_VDD12

DSM#

2

1LAN_X2

3

1
2
3
4
5
6
7
8
9
10
11
12

LAN_MDI0LAN_MDI0+

Y4
LAN_X1 2

ENSR

2
2.49K_0402_1%

1K_0402_1%

3

HSIN

0.1U_0402_16V4Z
2

/x
/

<16> CLK_PCIE_LAN

HSIP

24

close to pin 5 for EMI

1

2

GLAN_REQ#
2
0_0402_5%

1
R228

<16> CLKREQ_LAN#

23

45
47
48
44

su

<11> GLAN_TXN

HSON

3.6K_0402_5%
R227
2
+3V_LAN

EEDO
EEDI/AUX
EESK
EECS

p.

0.1U_0402_16V4Z

<11> GLAN_TXP

HSOP

om

30

PCIE_RXN2_LAN

2

yc

<11> GLAN_RXN

C412 1

//
m

29

tp
:

0.1U_0402_16V4Z
PCIE_RXP2_LAN
C411 1
2

ht

<11> GLAN_RXP

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

26

of

46

A

B

C

Mini Card Slot 1---WLAN
+3VS

+3VS_WLAN

Max 1A

+1.5VS

2 R242 1
0_0805_5%

+1.5VS_WLAN

Max 0.5A

C438
0.1U_0402_16V4Z

1

1

2

C439

R244
1

2

1

C440

4.7U_0805_10V4Z

1

0.01U_0402_16V7K
2

1

C441

2

2

1

C442
4.7U_0805_10V4Z

C443

E

+3VALW
+3VS_WLAN
0_0805_5%
2

+3VALW_WLAN

R243 2
1
0_0805_5%

D

1
R245

2
@ 0_0805_5%

0.1U_0402_16V4Z

2

0804 change power rail

0.1U_0402_16V4Z
1

1

JP4

<11> PCIE_PTX_C_IRX_N2
<11> PCIE_PTX_C_IRX_P2
<11> PCIE_ITX_C_PRX_N2
<11> PCIE_ITX_C_PRX_P2

R250 1

1 R252

<22> BT_COMBO_EN#

2 0_0603_5%

CH_CLK

2

2

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

1

0_0402_5%

2
4
6
8
10
12
14
16

+3VS_WLAN
+1.5VS_WLAN

CH751H-40PT_SOD323-2
2
1
D35

WL_OFF#
PLT_RST#

WLOFF#

<22>

+3VALW_WLAN
Max 0.3A
SMB_CK_CLK1
SMB_CK_DAT1
USB20_N6 <21>
USB20_P6 <21>
WL_LED#

WL_LED#

<35>

G1
G2
G3
G3

+3VS_WLAN

1
3
5
7
9
11
13
15

/x
/

<16> CLK_PCIE_MCARD2#
<16> CLK_PCIE_MCARD2

1
3
5
7
9
11
13
15

su

MINI_PCIE_WAKE#
CH_DATA
CH_CLK

<21> MINI_PCIE_WAKE#
<32>
CH_DATA
<32>
CH_CLK
<16> CLKREQ_MCARD2#

53
54
55
56

R253

CONN@
FOX_AS0B226-S99N-7F

4.7K_0402_5%

Express Card Power Switch
+1.5VS

U16
11
13

+1.5VS_PEC

2
4

3.3Vin
3.3Vin

3.3Vout
3.3Vout

3
5

+3VS_PEC

17
PLT_RST#

<12,15,20,26,33,34> PLT_RST#

3

1.5Vout
1.5Vout

6

AUX_IN

15

OC#

19

SYSRST#

20

SHDN#

PERST#

<29,34,36,38,41> SUSP#

1

STBY#

NC

10

CPPE#

GND

EXP_CPPE#

9
18

Max 1.3A

AUX_OUT

<34,35,36,40> SYSON

<21> EXP_CPPE#

Max 0.65A

CPUSB#
THERMAL_PAD
RCLKEN

+3V_PEC

PERST#

8
16
7
21

R5538D001-TR-F_QFN20_4X4~D

USE TI TPS2231MRGPR

<21> USB20_N8
<21> USB20_P8

JEXP

EXP_CPPE#

<21> SMB_CK_CLK1
<21> SMB_CK_DAT1
+1.5VS_PEC

SMB_CK_CLK1
SMB_CK_DAT1
MINI_PCIE_WAKE#

+3V_PEC

PERST#

+3VS_PEC
<16> CLKREQ_NCARD#

CLKREQ_NCARD#
EXP_CPPE#

<16> CLK_PCIE_NCARD#
<16> CLK_PCIE_NCARD
4

<11> PCIE_PTX_C_IRX_N0
<11> PCIE_PTX_C_IRX_P0
<11> PCIE_ITX_C_PRX_N0
<11> PCIE_ITX_C_PRX_P0
1
@ C466
330P_0402_50V7K

2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND

27
28
29
30

GND
GND
GND
GND

3

ht

+3VS_PEC

Near to Express Card slot.

yc

1 0.1U_0402_16V4Z

2
C457

1.5Vin
1.5Vin

//
m

+3VS
C456
2
1 0.1U_0402_16V4Z

12
14

tp
:

C453
2
1 0.1U_0402_16V4Z

Max 0.275A
+3VALW

om

9/20 STANDOFF (H=7.5 mm) ES000000D00

New Card

2

p.

2

9/20 SP01000HS00/SP01000LX00

4.7U_0805_10V4Z
1

1

C460

C461
2

2
0.1U_0402_16V4Z

+1.5VS_PEC

1

4.7U_0805_10V4Z
1

C462

C463
2

2
0.1U_0402_16V4Z
4

+3V_PEC
4.7U_0805_10V4Z
1
C464

1
C465

2
ACES_91740-02644_LB
CONN@

2
0.1U_0402_16V4Z

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

Compal Electronics, Inc.
WLAN/TV tuner/Express Card

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

27

of

46

5

4

3

2

1

2

+3VS

+VCC_4IN1

R417
100K_0402_5%
0_0402_5%
RST#
1

1

2

+3VS

1

2

White
R276

D16

2

1.2K_0402_5%

2

R277
0_0402_5%
1 1
2

1
3
7
9
11
33

AV_PLL
NC
NC
CARD_3V3
D3V3
D3V3

RST#
MODE SEL
XTLO
XTLI

8
44
45
47
48

3V3_IN
RST#
MODE_SEL
XTLO
XTLI

USB20_N7
USB20_P7
CR_LED#

4
5
14

DM
DP
GPIO0

2

1 C636

2

0804 Change value for brightness

2

0.1U_0402_16V4Z
1
C632
C633

0.1U_0402_16V4Z

C6351
4.7U_0603_6.3V6K

1

2

0.1U_0402_16V4Z

<21>
<21>

USB20_N7
USB20_P7

CR_LED#

HT-110TW_WHITE

0901 Change D16 footprint
0901 Change power rail for Vendor suggestion
MODE SEL
6.19K_0402_1%

2
1

2

2

R424 @
10K_0402_5%

R425

1

1

C

2
0_0402_5%

U31
C6311
1U_0603_16V6K

+3VS

+3VS

1
R419

47P_0402_50V8J
@ C638

2

RREF

12
32

DGND
DGND

6
46

AGND
AGND

D

C634
1U_0603_10V4Z
1
2

VREG
MS_D4
NC

10
22
30

XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17
SD_DAT2/XD_RE#_SP16
SD_DAT3/XD_WE#_SP15
XD_RDY_SP14
SD_DAT4/XD_WP#/MS_D7_SP13
SD_DAT5/XD_D0/MS_D6_SP12
SD_CLK/XD_D1/MS_CLK_SP11
SD_DAT6/XD_D7/MS_D3_SP10
MS_INS#_SP9
SD_DAT7/XD_D2/MS_D2_SP8
SD_DAT0/XD_D6/MS_D0_SP7
SD_DAT1/XD_D3/MS_D1_SP6
XD_D5_SP5
XD_D4/SD_DAT1_SP4
SD_CD#_SP3
SD_WP_SP2
XD_CD#_SP1
EEDI

43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18

XTAL_CTR
MS_D5

13
24

EEDO
EECS
EESK
SD_CMD

15
16
17
36

Card Reader Connector
JREAD
+VCC_4IN1
XD_CLE
XDCE#
XD_ALE
XD_RE#_SDD2
XDWE#_SDD3
XDRDY
XDWP#_SDD4
XDD0_SDD5
XDD1
XDD7_SDD6_MSD3
MSINS#
XDD2_SDD7_MSD2
XDD6_SDD0_MSD0
XDD3_MSD1
XDD5_MSBS
XDD4_SDD1
SDCD#
SDWP
XDCD#
R423
1

1
1

2
0_0402_5%
2
0_0402_5%

0_0402_5%
2
+3VS

SDCMD

RTS5158E-GR_LQFP48_7X7

1

1

2

C641
6P_0402_50V8J

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

XDWE#_SDD3
XDWP#_SDD4
XD_ALE
XDCD#
XDRDY
XD_RE#_SDD2
XDCE#
XD_CLE

34
33
35
40
39
38
37
36

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

11
31

7IN1 GND
7IN1 GND

41
42

7IN1 GND
7IN1 GND

7 IN 1 CONN

SD-VCC
MS-VCC

21
28

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW

20
14
12
30
29
27
23
18
16
25
1

SDCLK
XDD6_SDD0_MSD0
XDD4_SDD1
XD_RE#_SDD2
XDWE#_SDD3
XDWP#_SDD4
XDD0_SDD5
XDD7_SDD6_MSD3
XDD2_SDD7_MSD2
SDCMD
SDCD#

SD-WP-SW

2

SDWP

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS

26
17
15
19
24
22
13

MSCLK
XDD6_SDD0_MSD0
XDD3_MSD1
XDD2_SDD7_MSD2
XDD7_SDD6_MSD3
MSINS#
XDD5_MSBS

+VCC_4IN1

C

TAITW_R015-B10-LM
CONN@

om

1
10P_0402_50V8J
@ C639

2

//
m

C640
6P_0402_50V8J

1
10P_0402_50V8J
@ C637

32
10
9
8
7
6
5
4

2

@ 48MHZ_16PF_FSX3M 12.000M16FAQ
Y6
XTLO
4 4
3 3
XTLI
1 1
2 2
2
2

XD-VCC

XDD0_SDD5
XDD1
XDD2_SDD7_MSD2
XDD3_MSD1
XDD4_SDD1
XDD5_MSBS
XDD6_SDD0_MSD0
XDD7_SDD6_MSD3

yc

R278
0_0402_5%
1
2

<16> CLK_48M_CR

R427
@ 10_0402_5%

2

R422
@ 10_0402_5%

1

SDCLK

1

MSCLK

MSCLK
R421
SDCLK
R428

3

/x
/

2

0.1U_0402_16V4Z
C629
1
2

su

1U_0402_6.3V6K
D

C628
0.1U_0402_16V4Z

2

R420
499K_0402_1%~D
@

1

C630

p.

1

R418
2

1

B

ht

tp
:

B

A

A

Compal Secret Data

Security Classification
Issued Date

2007/08/28

Deciphered Date

2006/10/06

Title

Compal Electronics, Inc.
USB CardReader&CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
0.4

LA-4481P

Monday, September 08, 2008
1

Sheet

28

of

46

A

B

C

D

E

CODEC POWER
+3VS_HDA

+3VDD_CODEC
+3VS

R279
1
2
BLM18BD601SN1D_0603
C486

C487

2

+VDDA_CODEC_R

+VDDA_CODEC

R280
1
2
BLM18BD601SN1D_0603

0.1U_0402_16V4Z
1

+3VS

1

1

2

2

R281
1
2
0_0603_5%

C488

C489

0.1U_0402_16V4Z

1U_0603_10V4Z

1

1

2

2

+5VALW

W=40Mil
1
C485

1

C490
1U_0603_10V4Z

+VDDA_CODEC

U19

2
0.1U_0402_16V4Z

<27,34,36,38,41> SUSP#

IN

2

GND

3

SHDN

OUT

5

BYP

4

1

G9191-475T1U_SOT23-5 1

0.1U_0402_16V4Z

2

(4.75V(4.56~4.94V))
300mA

C491
2.2U_0805_16V4Z

C492

1

1

2

0.1U_0402_16V4Z

U20

DVDD_CORE

25

AVDD1*

38

AVDD2**

<21> HDA_SDOUT_CODEC

HDA_SDOUT_CODEC

5

SDO

R283 1

8

SDI_CODEC

<21> HDA_SYNC_CODEC

HDA_SYNC_CODEC

10

<21> HDA_RST#_CODEC

HDA_RST#_CODEC

11

DMIC_CLK

<34>

EC_BEEP

@ R287 1

2 47K_0402_5%

<21>

SB_SPKR

R289 1

2 47K_0402_5%

R290 1

2 10K_0402_5%

C497

1

43

GPIO 6

44

SPDIF OUT1 / GPIO 7

45

SPDIF OUT0

48

VREFOUT-B

28

VREFOUT-C

29

SYNC

2 0.1U_0402_16V4Z

+VDDA_CODEC_R

10K_0402_5%
2
1
R301

0730 add R301 fix MIC auto switch

40

10U_0805_10V4Z
C500 1
2

VC_REFA

SENSE_B / NC

37

NC

18

NC

19

NC

27
26

3

PORTA_R

VREFOUT_B <30>

41

SENSE

HP_OUTR

39

HP_OUTL

PORTB_R

22

MIC_EXTR

PORTB_L

21

MIC_EXTL

PORTC_R

24

PORTC_L

23

R284
R285
R286

1
1
1

C494

2

+VDDA_CODEC_R
2 5.1K_0402_1%
2 20K_0402_1%
2 39.2K_0402_1%

EXTMIC_DET# <30>
JACK_DET# <30>

0.1U_0402_16V4Z
1
2
HP_OUTR <30>

HP Jack & Dock

HP_OUTL <30>
1
C498
1
C499

2
2

MIC_EXT_R <30>

1U_0603_10V6K

36

LINE_OUT_R

LINE_OUT_R <30>

PORTD_L

35

LINE_OUT_L

LINE_OUT_L <30>

VREFFILT

PORTE_R

15

AVSS1*

PORTE_L

14

PORTF_R

17

PORTF_L

16

Jack MIC

MIC_EXT_L <30>

1U_0603_10V6K

PORTD_R

Internal SPKR.

3

AVSS2**

7

13

PORTA_L

NC

tp
:

42

SENSE_A

NC / OTP

34

20

0509 Solve MIC no function

RESET#

R288
1
2
46
FBMA-L10-160808-301LMT 0603 DMIC_CLK
33
2
1
C495
1U_0603_10V4Z CAP2
MONO_INR
1
2
12 PCBEEP
0.1U_0402_16V4Z
C496

EAPD_CODEC <34>
DMIC_DAT <18>

om

<18>

2

31

GPIO 5

BITCLK

EAPD_CODEC

30

VREFOUT-E / GPIO 4

yc

1
@C493
33P_0402_50V8K

6

2 33_0402_5%

4

//
m

2

2

<21> HDA_BITCLK_CODEC

<21> HDA_SDIN0

VOL_DN/DMIC_1/GPIO 2

MONO_OUT

HDA_BITCLK_CODEC

1

@
R282
47_0402_5%

2

DVDD_IO

32
HDA_BITCLK_CODEC

47

VOL_UP/DMIC_0/GPIO 1

GPIO 3

3

+3VS_HDA

EAPD/ SPDIF OUT 0 or 1 / GPIO 0

/x
/

DVDD_CORE*

1

su

+VDDA_CODEC_R

9

p.

+3VDD_CODEC

DVSS**

ht

92HD71B7X5NLGXA1X8_QFN48_7X7

@ C501
1
2
0.1U_0402_16V4Z
@ C502
1
2
0.1U_0402_16V4Z

SENSE A

4

@ C503
1
2
0.1U_0402_16V4Z

SENSE B

@ C504
1
2
0.1U_0402_16V4Z

Port

Resistor

Port

Resistor

A

39.2K

E

39.2K

@ R291
1
2
0_0402_5%

B

20K

F

20K

@R292
1
2
0_0805_5%

C

10K

G

10K

R293
1
2
0_1206_5%

D

5.11K

H

5.11K

GND

Use an 80mil to
connection or place
a 1206 resistor under
CODEC with double
vias.

4

Compal Secret Data

Security Classification
GNDA

GNDA

<30>

2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Audio Codec-IDT9271B7

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

Compal Electronics, Inc.

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

29

of

46

A

B

C

D

+5VAMP

GAIN0

GAIN1

0

0

E

Av(inv)

SPEAKER

R294

0_0402_5%

C514
C515
C516
C517

R300
<29> LINE_OUT_L

2

1

0_0402_5%

C518
C519

1
1

2 0.022U_0603_25V7K
2
47P_0402_50V8J

9

1
1

2 0.022U_0603_25V7K
2
47P_0402_50V8J

5

19

GAIN1

3

ROUT+

18

SPKR+

ROUT-

14

SPKR-

LOUT+

4

SPKL+

LOUT-

8

SPKL-

R298

LIN+

1

1

21.6dB

2
100P_0402_50V8J

1

2

C511
2

5
6

GND1
GND2

CONN@ E&T_3806-F04N-02R

2

1

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

R299 @
100K_0402_5%

@ D55
PSOT24C_SOT23-3

@ D56
PSOT24C_SOT23-3

100K_0402_5%

LIN-

SHUTDOWN

20
13
11
1

GND1
GND2
GND3
GND4

<34> EC_MUTE#

EC_MUTE#

GAIN0

2

R296
100K_0402_5%

1
C510

2

RIN-

1
C509

3

17

1

2

2 0.022U_0603_25V7K
2
47P_0402_50V8J

15.6dB

3

1
1

0

1

1

RIN+

1

1
2
3
4

NC

12

BYPASS

10

Keep 10 mil width
1

2

C520
1U_0805_25V4Z

TPA6017A2_TSSOP20

1UF

2

//
m

yc

om

p.

2

0804 Reserve ESD doide

/x
/

2

7

10dB

1
2
3
4

su

<29> LINE_OUT_R

2 0.022U_0603_25V7K
2
47P_0402_50V8J

THERMAL PAD

C513

R297

1
1

@ R295
100K_0402_5%

21

C512

1

1

1

0

SPKRSPKR+
SPKLSPKL+

C508

2

U21

1

2

1

10 dB

VDD
PVDD1
PVDD2

2
2
0.1U_0402_16V4Z

C507

JP7

6dB

2

C506

1

1

1

+5VS

2

1
C505

10U_0805_10V4Z

1

0.1U_0402_16V4Z

2

2
1
0_1206_5%

16
15
6

+5VS

3

3

R429
2
1
0_0402_5%
R430

ht
HP_OUTL

+

1
C523

1

+

<29>

HP_OUTR

C524

HP_OUT_R
2
150U_B_6.3VM_R40M

2

HP_OUT_L

R431
4.7K_0402_5%
2

4.7K_0402_5%

JP48

0605 change Cap size to solve DFB issue.
<29>

2

1U_0603_10V4Z

2

0605 Remove Transisters.

C642 1
1

<29> VREFOUT_B

1

tp
:

0509 Solve MIC no function

13
14

GND
GND

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
11
12

EXT_MIC_R
EXT_MIC_L

MIC_EXT_R <29>
MIC_EXT_L <29>

HP_OUT_R
HP_OUT_L
EXTMIC_DET#
JACK_DET#
CIR_IN

EXTMIC_DET# <29>
JACK_DET# <29>
CIR_IN

<34>

+5VL

ACES_85201-1205N
CONN@

150U_B_6.3VM_R40M

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

AMP & Audio Jack
Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

30

of

46

A

B

C

D

E

ACCELEROMETER
+3VS

+3VS_ACL
D19
2

+3VS_ACL_IO
0_0603_5%
2

R308
1

1

CH751H-40PT_SOD323-2
1

C527

1

1

2

1

C528
10U_0805_6.3V6M

2

0.1U_0402_16V4Z

SMB_CK_CLK0

2

Vdd_IO

2

GND

3

Reserved

4

GND

5
6

14

SMB_CK_DAT0

SDA / SDI / SDO

13

SDO

12

Reserved

11

GND

10

GND

INT 2

9

HDD_HALTLED <35>

Vdd

INT 1

8

ACCEL_INT <20>

SMB_CK_DAT0 <9,10,16,21>

R311
0_0402_5%
1
2

CS

+3VS_ACL

1

/x
/

R310
0_0402_5%
1
2

0011101b

su

+3VS_ACL_IO

SMB_CK_CLK0 <9,10,16,21>

om

7

LIS302DLTR_LGA14_3x5

2
R312

2

p.

VDDIO absolute man
rating is VDD+0.1

SCL / SPC

U22

1
10K_0402_5%

//
m

yc

Must be placed in the center of the system.

3

ht

tp
:

3

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Accelerometer
Rev
0.4

LA-4481P
Sheet

Monday, September 08, 2008
E

31

of

46

A

B

C

D

E-SATA Combo & USB-1

E

D20
+USB_VCCA
USB20_N1_R

4

VIN

IO1

2

3

IO2 GND

1

USB20_P1_R

ESATA Combo

@ PRTR5V0U2X_SOT143-4
Max 0.5A
+USB_VCCA

Max 2.5A
+USB_VCCA

+5VALW

+USB_VCCA

1

SUYIN_020173MR004S592ZL
JP9

L55
U23
OUT
OUT
OUT
OC#

TPS2061IDGN_MSOP8~N
4.7U_0805_10V4Z

<34>

2

1
+
2

1000P_0402_50V7K
C533

C531

GND
IN
IN
EN#

0.1U_0402_16V4Z
C532

1

W=100mils

8
7
6
5

C530
150U_D_6.3VM

1
2
3
4

1

2

1

<21>

USB20_N0

4

4

3

3

<21>

USB20_P0

1

1

2

2

USB20_N0_R
USB20_P0_R

1
2
3
4

USB+5V
USBN1
USBP1 SHADIN
GND
SHADIN

+5VALW
USB20_P0_R

USB_EN#

VIN

IO1

2

3

IO2 GND

1

L54
4 4

3

3

<21>

USB20_P1

1

2

2

<22>
<22>

1

C534
C535

USB20_N0_R

2 1000P_0402_50V7KSATA_RXN2
2 1000P_0402_50V7KSATA_RXP2

1
1

SATA_TXN2

4

VIN

IO1

2

3

IO2 GND

1

2

+
2

1

2

1

0605 add GND shaping

+3VAUX_BT

USB20_N3

2

2

1
2
3
4

6
5

2

SUYIN_020173MR004S592ZL
CONN@

D24

USB20_N2_R

4

VIN

IO1

2

3

IO2 GND

1

USB20_P3

1

+3VAUX_BT
SI2301BDS-T1-E3_SOT23-3
0.1U_0402_16V4Z

1

C540

R315

1U_0603_10V4Z

100K_0402_5%

1

2

C541

1

C542

2

1

C543

2

0.01U_0402_16V7K

4.7U_0805_10V4Z

R316

<22>

BT_OFF

tp
:

+5VALW

2
1

2

1

USB+5V
USBN1
USBP1 SHADIN
GND
SHADIN

WCM-2012-900T_0805
3

IO1

IO2 GND

2

1

USB20_N2_R
USB20_P2_R

//
m

1

USB20_P2

3

3

VIN

3

G

<21>

JP11

4

4

D

S

3

4

<21>
<21>
<35>
<27>
<27>

@ PRTR5V0U2X_SOT143-4

+3VALW

+USB_VCCB
USB20_N2

USB20_P3
USB20_N3
BT_LED
CH_DATA
CH_CLK

1K_0402_5%
1K_0402_5%

2
2

Q21

<21>

2

D23

ACES 87213-0800G
2

USB_EN#

L56

12
13
14
15

/x
/
USB20_P3
USB20_N3
@ R313 1
@ R314 1

yc

4.7U_0805_10V4Z

1

1000P_0402_50V7K
C539

TPS2061IDGN_MSOP8~N

0.1U_0402_16V4Z
C538

W=100mils
C536
150U_D_6.3VM

1

C537

SHIELD
SHIELD
SHIELD
SHIELD

+3VAUX_BT

p.

U24

10
9
8
7
6
5
4
3
2
1

om

GND2
GND1
8
7
6
5
4
3
2
1

Max 2.5A
+USB_VCCB

8
7
6
5

ESATA

0509 Solve MIC no function

CONN@ JP10
2

OUT
OUT
OUT
OC#

GND
A+
AGND
BB+
GND

su

BT Connector

GND
IN
IN
EN#

5
6
7
8
9
10
11

1

USB

SATA_TXP2

@ PRTR5V0U2X_SOT143-4

1
2
3
4

B_VCC
B_DB_D+
B_GND

TYCO_1759576-1

+USB_VCCA

+5VALW

CONN@
JP8
1
2
3
4

D22

@ PRTR5V0U2X_SOT143-4

USB-3

USB20_N1_R
USB20_P1_R

SATA_TXP2
SATA_TXN2

SATA_TXP2
SATA_TXN2

<22> SATA_RXN2_C
<22> SATA_RXP2_C

D21
4

USB20_N1

WCM-2012-900T_4P

CONN@

WCM-2012-900T_0805

2

6
5

<21>

USB20_P2_R

3

1
2
10K_0402_5%

1
C544

2
0.1U_0402_16V4Z

Check BT power consumption < 1A

ht

@ PRTR5V0U2X_SOT143-4

Finger printer
R317
1
+3VALW

2
@ 0_0603_5%
@ SI2301BDS-T1-E3_SOT23-3

Q20

+3VS
+3VS_FB

D

S

3

1
1

2

G
USB_EN#

C545
0.1U_0402_16V4Z

2
USB20_N4
USB20_P4

<21> USB20_N4
<21> USB20_P4

4

R318
1
2
0_0603_5%

D25
+3VS_FB

4

VIN

IO1

2

USB20_N4

3

IO2 GND

1

USB20_P4

PRTR5V0U2X_SOT143-4

JP12
1
2
3
4

1
2
3
4

G1
G2

5
6

4

ACES_85201-04051
CONN@

0730 change conn fix DFB issue.

2007/08/02

Issued Date

0804 moute it for ESD.

Compal Secret Data

Security Classification

2008/08/02

Deciphered Date

Title

USB, BT, eSATA,FPR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

Compal Electronics, Inc.

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

32

of

46

A

B

C

D

+3VL

+3VL
1

SPI Flash (8Mb*1)

1

C546
R319@
100K_0402_5%

@ 0.1U_0402_16V4Z
2
C547

VCC
WP
SCL
SDA

1

20mils

CONN@
U25
8

VCC

3

W

7

HOLD

SPI_CS#

1

S

SPI_CLK

6

C

<34> EC_SO_SPI_SI

5

0.1U_0402_16V4Z

2

2

U26
8
7
6
5

<7,34,35,37> SMB_EC_CK1
<7,34,35,37> SMB_EC_DA1

1

E

A0
A1
A2
GND

1
2
3
4

<34>

@ AT24C16AN-10SI-2.7_SO8

1

<34>

&U1
VSS

4

45@ SST25VF080B-50-4C-S2AF_SO8

D

Q

2

1

EC_SI_SPI_SO <34>

WIESON G6179 8P SPI
R324@
100K_0402_5%

0605 remove 0 ohm resisters
2

2

SPI_CLK

1

R325 @
33_0402_5%

@ C548

1

2

su

/x
/

22P_0402_25V8K

2

//
m

yc

om

p.

2

H1

+3VALW

<20,34> LPC_AD3
<20,34> LPC_AD1

7

4

LPC_AD3

8

LPC_AD1

9

LPC_FRAME#

10

LPC_DRQ#
PLT_RST#

3

LPC_AD2

2

LPC_AD0

1

CLK_PCI_SIO

LPC_DRQ# <20>

PLT_RST# <12,15,20,26,27,34>

LPC_AD2 <20,34>
LPC_AD0 <20,34>
CLK_PCI_SIO <20>

2

<20,34> LPC_FRAME#

5

ht

<20,34> SIRQ

6
SIRQ

3

tp
:

LPC Debug Port

3

0605 Remove LPC debug connector

@ R329
22_0402_5%
1

@ DEBUG_PAD

2

1

@ C550
22P_0402_50V8J

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
BIOS ROM/Debug Tool

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

33

of

46

A

B

C

D

E

+3VL_EC

0605 Change pin assignment
1
+3VL

C555

<21>
<21>
<21>
<35>

0509 change value to solve ENE cap-board could not detect

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
<35>
ESB_CLK
<35>
ESB_DAT

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

VLDT_EN

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
ESB_CLK
ESB_DAT

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

<35> NUM_LED#

4.7K_0402_5%

C587
15P_0402_50V8J
1
2

CRY2

2

1

Y5

VLDT_EN
3

NC

OSC

4

2

NC

OSC

1

1

1

122
123

1

25
26

67

EC_MUTE# <30>
USB_EN# <32>
I2C_INT <35>

TP_CLK
TP_DATA
AC_LED#

R409

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

EC_RSMRST#

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

V18R

124

GPI

TP_CLK <35>
TP_DATA <35>
2

AC_LED# <37>

VGATE <43>
2
100K_0402_5%

+3VS

EC_SI_SPI_SO <33>
EC_SO_SPI_SI <33>
SPI_CLK <33>
SPI_CS# <33>
CIR_IN

CIR_IN

GPIO

1

CIR_IN

FSTCHG
BAT_LED#
ON/OFFBTN_LED#
SYSON
VR_ON
ACIN_D

<30>

+5VL

FSTCHG <38>
STD_ADP <38>
CAPS_LED# <35>
BAT_LED# <35>
ON/OFFBTN_LED# <35>
SYSON
<27,35,36,40>
VR_ON

1

R340
1

TP_CLK

R342
1

TP_DATA

R343
1

2
+5V_TP

2
10K_0402_5%
2
10K_0402_5%

0605 Change value to solve AC
plugged/unplugged power status
issue.

<43>

2
1
R344 10K_0402_5%

WL_BLUE_LED#
SB_PWRGD
BKOFF#
TP_LED#

1

2
+3VL
300K_0402_5%

D26
ACIN_D

2

1

AC_IN

<22,38>

CH751H-40PT_SOD323-2
3

TP_LED# <35>

SUSP#
PWRBTN_OUT#

2
C588

R345
1

EC_RSMRST# <21>
EC_LID_OUT# <21>
EC_ON
<36,39>
WL_BLUE_LED# <35>
SB_PWRGD <7,21,43>
BKOFF#
<18>

2
C586

VFIX_EN <43>
ENBKL <12>
EAPD_CODEC <29>
EC_THERM# <22>
SUSP# <27,29,36,38,41>
PWRBTN_OUT# <21>
PCI_SERR# <20>

1
100P_0402_50V8J

KB Back Light Conn
+5VS

4.7U_0805_10V4Z

KB926QFC0_LQFP128_14X14

2
0.1U_0402_16V4Z

TP_BTN#

10K_0402_5%

2
1
R341 10K_0402_5%

@ R426

L57
0_0603_5%

1

ACES_85201-24051
CONN@

+3VL_EC

1
C590
2

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

DAC_BRIG <18>
VCTRL <38>
IREF
<38>
AC_SET <38>

IREF

73
74
89
90
91
92
93
95
121
127

2

R414
LAN_POWER_OFF

97
98
99
109

TP_BTN#

1
CRY1

2

C589
15P_0402_50V8J

<26> LAN_POWER_OFF

83
84
85
86
87
88

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

XCLK1
XCLK0

+EC_AVCC

4

GND1
GND2

BATT_TEMP <37>
BATT_OVP <37>
ADP_I <38>
ADP_ID <37>
TP_BTN# <35>

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

SM Bus

@
R350
20M_0402_5%

32.768KHZ_12.5PF_9H03200413

R412
10K_0402_5%

SPI Flash ROM

77
78
79
80

E51_TXD
E51_RXD

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

ht

+3VL

PS2 Interface

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

R348
1

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

tp
:

<36>

2

68
70
71
72

DA Output

<7> H_THERMTRIP#_EC

<35> ON/OFF#

AD

2

3

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

C574

100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

10_0805_5%~D

1

<7,33,35,37>
<7,33,35,37>
<7>
<7>

2 4.7K_0402_5%
2 4.7K_0402_5%

1
1

BATT_TEMP
BATT_OVP

R433
10K_0402_5%

R413

2

0619 change pin assignment

2
Q24

1EC_BEEP
0_0402_5%
R353

JP16
L58
1

5
6

2
0_0603_5%

E51_RXD

G1
G2

1
2
3
4

1
2
3
4

1

+3VL
R346
R347

63
64
65
66
75
76

PWM Output

<18>
<5>
<29>
<38>
0.01U_0402_16V7K
ECAGND
1
2

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2

2
LID_SW#

ESB_CLK
ESB_DAT

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

INV_PWM
FAN_PWM
EC_BEEP
ACOFF

ACOFF

1

1
R339
10K_0402_5%

2

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

0.1U_0402_16V4Z

1
R338
100K_0402_5%

2

2

R337
100K_0402_5%

12
13
37
20
38

INV_PWM
FAN_PWM

1

C585

+3VALW

SYSON

1

SUSP#

CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#

21
23
26
27

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

om

2

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

32

<12,15,20,26,27,33> PLT_RST#
2
47K_0402_5%
<21>
EC_SCI#
<21,24> HDARST#

R336 1

1
2
3
4
5
7
8
10

KSI1 @ C556
KSI7 @ C557
KSI6 @ C558
KSO9 @ C559
KSI4 @ C560
KSI5 @ C561
KSO0 @ C562
KSI2 @ C564
KSI3 @ C565
KSO5 @ C566
KSO1 @ C567
KSI0 @ C568
KSO2 @ C569
KSO4 @ C570
KSO7 @ C571
KSO8 @ C572
KSO6 @ C575
KSO3 @ C576
KSO12@ C577
KSO13@ C578
KSO14@ C579
KSO11@ C580
KSO10@ C581
KSO15@ C582

0_0805_5%

2
@ 33_0402_5%

<20,24> CLK_PCI_EC
+3VL

For EMI
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

2

1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

1
C563

/x
/

R335
2

@ 15P_0402_50V8J

GATEA20
KB_RST#
SIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

su

<21>
GATEA20
<21>
KB_RST#
<20,33> SIRQ
<20,33> LPC_FRAME#
<20,33> LPC_AD3
<20,33> LPC_AD2
<20,33> LPC_AD1
<20,33> LPC_AD0

yc

C573
1

+3VS

BATT_OVP 2
100P_0402_50V8J

//
m

2 4.7K_0402_5%
2 4.7K_0402_5%

GND
GND
GND
GND
GND

1
1

11
24
35
94
113

SMB_EC_DA2 R333
SMB_EC_CK2 R334

VCC
VCC
VCC
VCC
VCC
VCC

U28
2 4.7K_0402_5%
2 4.7K_0402_5%

AVCC

+3VL
1
1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

+EC_AVCC

2
0_0805_5%

p.

R330
1

1

SMB_EC_DA1 R331
SMB_EC_CK1 R332

KBD CONN

+3VL_EC

JP15

2

AGND

2
2
1000P_0402_50V7K

69

C554

ECAGND

2
2
0.1U_0402_16V4Z

C553

9
22
33
96
111
125

C552

D

C551

1000P_0402_50V7K

S

1

0.1U_0402_16V4Z
1

G

0.1U_0402_16V4Z
1
1

+BK_PWR

SI2301BDS-T1-E3_SOT23-3

30 mils
4

ACES_85201-04051

0_0402_5%

CONN@

EC DEBUG port
Compal Secret Data

Security Classification

@ R415
1

2

2007/08/02

Issued Date

E51_TXD

2008/08/02

Deciphered Date

Title

EC KB926/KB conn

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0_0603_5%

Date:

A

Compal Electronics, Inc.

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

34

of

46

A

B

C

D

E

Max 0.5A

TouchPAD ON/OFF

+5VALW

R351
1

+5V_TP
0_0603_5%
2
Q19 @ SI2301BDS-T1-E3_SOT23-3
1

1
+5VS
<34>
<34>

@ 10K_0402_5%
2

TP_LED#
TP_BTN#

R352

2

TP_LED#
TP_BTN#

1

1

1

C595
0.1U_0402_16V4Z 2

0.1U_0402_16V4Z
C606

2

1

ACES_85201-04051
CONN@

D

3

G1
G2

1
2
3
4

1
2
3
4

G

5
6
1

D

S

3

JP18

S

Q18

2
G

<27,34,36,40> SYSON

@ 2N7002_SOT23-3

0804 add Caps for ESD reserve

TP_DATA
TP_CLK
3

Max 0.5A
+5V_TP

2

M/B TO TP/B

TP_CLK
TP_DATA

ACES_85201-04051
CONN@

TP_CLK <34>
TP_DATA <34>

1

9/20
SP01000KC00/SP01E000900

1

@ C592
100P_0402_50V8J 2

@ C593
2 100P_0402_50V8J

2

0616 Reserve ENE Capboard EMI solution
300 ohm bead+ 33PF

15P_0402_50V8J
1
C601

om
2

2
4

3
Q23B

D28

3

2N7002DW-7-F_SOT363-6
Q22
2N7002_SOT23-3

D

@

S

HT-297UY5/BP5_YELLOW-WHITE

1 R363
2
0_0402_5%

HDD_HALTLED# <22>

2
G

HDD_HALTLED <31>

ESB_DAT_R

11/10 update

Battery Charge LED

C598 33P_0402_50V8J

G1
G2

C596
10U_0805_10V4Z
@
2

1
2
3
4
5
6
7
8
9
10
11
12

ESB_CLK_R
ESB_DAT_R

1
C597
C594
2
0.1U_0402_16V4Z

@ C600 33P_0402_50V8J
ESB_CLK_R
2
1

1

1

2

2

C599
4.7U_0603_6.3V6K

15P_0402_50V8J

1
2
3
4
5
6
7
8
9
10
GND
GND
ACES_85201-1005N
CONN@

0804 Mout it for ESD

ON/OFF Button Connector

+5VS

CONN@
JP49

5
6

2 0_0402_5%
2 FBMA-11-100505-301T_0402
2 FBMA-11-100505-301T_0402

1

2

+5VALW
1
2
3
4

1
2
3
4

CONN@
JP19

CAPS_LED# <34>

1
ON/OFF#
2
ON/OFFBTN_LED# 3
4

<34>
ON/OFF#
<34> ON/OFFBTN_LED#

ACES_85201-04051

1
2
3
4

3

G1
G2

5
6

ACES_85201-04051

WLAN and BT LED inform pin to KBC
+3VS

R398
1

R399
2
1
@ 10K_0402_5%

2

+3VS

47K_0402_5%
+5VALW

<34> WL_BLUE_LED#

<34> BAT_LED#

2

WL_BLUE_LED#

WL/WW_LED#
2
1
D32
CH751H-40PT_SOD323-2

1

D29
1

D
Q43
2N7002_SOT23-3

1 R367
2
200_0402_5%

HT-F196BP5_WHITE
3

S

2
G

1

<34> NUM_LED#

100K_0402_5%

R369
2

<27>

2

D30

WL_LED#

R402

+5VS

WHITE

2
0_0402_5%

BT_LED <32>

0804 Change value to adjust brightness

Num LOCK LED

1
R400

1

WHITE

4

2

1
R354
0_0805_5%

2 0_0402_5%

1

Capa-Lock Conn

ht

3

2N7002DW-7-F_SOT363-6

1

2

1

Q23A
<22> SATA_LED#

1

4

6

5

YELLOW

WHITE

2

10K_0402_5%

390_0402_5%

2

1
R361

3

R360

//
m

R359
200_0402_5%

tp
:

+5VS

R358

+3VL

JP21

0616 Reserve ENE Capboard EMI solution

yc

+3VS

1

+5VS

1

HDD/G-Sensor LED

R355 1
R356 1
R357 1

SMB_EC_DA1

<7,33,34,37> SMB_EC_DA1

Cypress

SMB_EC_CK1
ESB_CLK
ESB_DAT

+3VL_CAP

+3VL_CAP

@ PJP605
PAD-OPEN 2x2m

<7,33,34,37> SMB_EC_CK1
<34> ESB_CLK
<34> ESB_DAT
<34>
I2C_INT
<34> LID_SW#

ENE

2

1

1
1
2
3
4

+5VS

1

+3VL

su

2

1
2
3
4

G1
G2

0605 Remove LDO

p.

5
6

0804 Mout it for ESD

@

2

JP20

2

D27
PSOT24C_SOT23-3

/x
/

Capacitor Sensor Conn

1
@ C591
0.1U_0402_16V4Z

1
2
1.2K_0402_5%

4

HT-F196BP5_WHITE

POWER LED

+5VALW

WHITE
D31
ON/OFFBTN_LED#

1

2

Compal Secret Data

Security Classification

1 R372
2
200_0402_5%

2007/08/02

Issued Date

HT-F196BP5_WHITE

2008/08/02

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

White LED: VF=3V, IF = 10mA, Res = 200 ohm
Amber LED: VF=1.8V, IF = 8mA, Res = 390 ohm

Date:

A

Compal Electronics, Inc.
TP,MDC,ON/OFF,S/W,LED,Reed

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

35

of

46

A

B

+5VALW TO +5VS

D

E

+1.2VALW

+3VALW

2

+3VALW TO +3VS

+5VS

+3VS

4.7U_0805_10V4Z

2

8
7
6
5

2

D
D
D
D

S
S
S
G

C610

RUNON

2

1U_0402_6.3V4Z
RUNON
2 R376
1
330K_0402_5%

C608
2

1

2

1

C609
SUSP

5

Q36B
2N7002DW-7-F_SOT363-6

2

VLDT_EN#

2N7002DW-7-F_SOT363-6
Q36A

430K_0402_5%
470K_0402_5%

yc

JBK00-->10M

JBK00-->750K

Discharge circuit

Q31A

6 1

1
3
SUSP

6
2

SUSP

5

2N7002DW-7-F_SOT363-6

<42>

SUSP#

<27,29,34,38,41>

2N7002DW-7-F_SOT363-6

Q31B

3

FM1
H2
HOLEA

H3
HOLEA

H4
HOLEA

H5
HOLEA

H6
HOLEA

H12
HOLEA

H13
HOLEA

FM2
1

FM3

FM4
1

1

1

1

1
R393
470_0805_5%

Q32A

1
1

2

R392
470_0805_5%

Q30B

100K_0402_5%

Q33B
SYSON

<27,34,35,40> SYSON

+1.8V

2

2
3 1

3 1

Q29B

SYSON#

SYSON#

FM6
1
H7
HOLEA

H8
HOLEA

H10
HOLEA

H11
HOLEA

H14
HOLEA

FM5
1

H9
HOLEA

Q32B

2007/08/02

2008/08/02

Deciphered Date

Title

H24
HOLEA

1

H23
HOLEA

1

1

1

H22
HOLEA

DC/DC Circuits

Date:

C

H20
HOLEA

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

H19
HOLEA

1

H25
HOLEA

1

H18
HOLEA

1

H16
HOLEA

Compal Secret Data

Security Classification
Issued Date

H17
HOLEA

1

1

4

H15
HOLEA

1

H21
HOLEA

A

1

1

1

1

1

5

2N7002DW-7-F_SOT363-6

1

SYSON#

2

2N7002DW-7-F_SOT363-6

4

SYSON#

5

1

SUSP

2N7002DW-7-F_SOT363-6

4

2N7002DW-7-F_SOT363-6

1

5
4

SUSP

R391
470_0805_5%

<42>

ht

+0.9V

2

+1.5VS

R389

4

2N7002DW-7-F_SOT363-6

+3VS

R387
470_0805_5%

R388
100K_0402_5%

tp
:

2N7002DW-7-F_SOT363-6

+5VL

5

3 1

2N7002DW-7-F_SOT363-6

SUSP
1

2N7002DW-7-F_SOT363-6

VLDT_EN# 2

2
1

SUSP

2
1

SUSP

//
m

Q30A

3

+5VL

Q33A

R383
470_0805_5%

3 1

R386
470_0805_5%
6 1

6 1

R385
470_0805_5%

Q29A

+1.1VS
2

2

2
R384
470_0805_5%
6 1

+1.2V_HT
2

+1.8VS

+5VS

2N7002DW-7-F_SOT363-6

2

om

0605 Add Resister to protect Q42

0605 Add Resister to protect Q41

VLDT_EN

4

2
R401

2

0.01U_0402_25V7K

2N7002DW-7-F_SOT363-6

2

2
6

C620

<34>

1

4

2

2N7002DW-7-F_SOT363-6

1

5

SUSP

1

C619

2

R381

2

1

Q35B

VLDT_EN 5

3

Q34B

1

0.01U_0402_25V7K

B+

4

C621

R379
1
2
330K_0402_5%

2

<34,39> EC_ON

1

2

3

1.8VS_ENABLE
1

B+

VLDT_EN#

VLDT_EN#
Q35A

1

1U_0402_6.3V4Z
2 R378
1
330K_0402_5%

1

2

4.7U_0805_10V4Z

2

1

2

4

4.7U_0805_10V4Z

C618

C616

EC_ON#

1
2
3

4

1

100K_0402_5%

2

1U_0402_6.3V4Z

C615

1

6

8
7
6
5

R390

100K_0402_5%

1

C614
10U_0805_10V4Z

1

/x
/

1

Q42
IRF8113PBF_SO8

su

2

R382

p.

1
2
3

2

C613

+1.2V_HT

1

1

8
7
6
5

+5VL

1

+1.8VS
+1.2VALW

4.7U_0805_10V4Z

2

2N7002DW-7-F_SOT363-6

+1.2VALW TO +1.2V_HT

Q41
IRF8113PBF_SO8

2

EC_ON#
B+

+5VL

+1.8V TO +1.8VS
+1.8V

1

Q34A

2

3

1U_0402_6.3V4Z

R380
470_0805_5%

1
4.7U_0805_10V4Z

C603

2

SI4800BDY_SO8
4.7U_0805_10V4Z

4.7U_0805_10V4Z

SI4800BDY_SO8
1

1

C602
1
2
3
4

6 1

Q38

1

4

S
S
S
G

C605

0.01U_0402_25V7K

1

D
D
D
D

1

C604

1
2
3
4

1

Q39
8
7
6
5

1

+5VALW

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

36

of

46

4

A

B

C

D

E

BATT1

45@ CR2032

RTC BATTERY

+3VALW

+3VL

1

3

1

1

PR9
100K_0402_5%

8

105K_0402_1%
PR6 1
2

1
2

P
G

/x
/
0.01U_0402_25V7K
PC6

su
p.
om
1
PC10
0.22U_0603_10V7K

5

+

1

6

-

PR15
150K_0402_1%
2

2

D

<7,39>

0

S

PQ2
SSM3K7002FU_SC70-3

2
G

7

PU1B
LM358ADT_SO8

PC11
1000P_0402_50V7K

2

PR17
1K_0402_5%

1

2
PR11
150K_0402_1%

PR12
2.21K_0402_1%
2

+3VL

1

PR16
6.49K_0402_1%
1
2

+5VALW

EN0

PR10
200K_0402_1%
1
2

3

<38>

SMB_EC_CK1 <7,33,34,35>

1

BAT_ID

10KB_0603_1%_TH11-3H103FT
8

SMB_EC_CK1

3

PH1

SMB_EC_DA1 <7,33,34,35>

ht

2

SMB_EC_DA1

PR7
604K_0402_1%
1
2

+5VS

CPU

4

PD3
PJSOT24C_SOT23-3

2

1

PR14
100_0402_5%

PR13
100_0402_5%

PC9
0.01U_0402_50V4Z

1

2

3
1

1

3

PH1 under CPU botten side :
CPU thermal protection at 95 +-3 degree C

2

PC8
1000P_0402_50V7K

SUYIN_200275MR006G113ZL

PU1A
LM358ADT_SO8

BATT_OVP <34>

2

1

1
2

-

PR5
10K_0402_5%
2
1

1

1

GND

1
2
PL4
HCB2012KF-121T50_0805

0

BATT_A

tp
:

GND

2

GND

8

PD2
PJSOT24C_SOT23-3
3

PL3
HCB2012KF-121T50_0805
1
2

2

6

7

EC_SMD
EC_SMC

+

yc

2
3
4
5

SMD
SMC
B/I
TS

1

1

2

1

VMB
PJP2

2

1
2

PC3
1000P_0402_50V7K

//
m

1

@PJSOT24C_SOT23-3

2
1
PC2
100P_0402_50V8J

3

2

PD1
2

PC7
2200P_0402_50V7K
2
1

HCB2012KF-121T50_0805
1
2
PL2

PC5
1000P_0402_50V7K
2
1

ADPIN

3

4

2

PL1
HCB2012KF-121T50_0805
1
2

ACES_87343-047N-2

BATT+

VIN

RLZ3.6B TE-11 LL-34

1
2
PR3
10K_0402_5%

PC4
100P_0402_50V8J
2
1

4
3
2
1

2

2

1
4
3
2
1

@1000P_0402_50V7K

+5VALW

P

PD4
PR2
10K_0402_5%

ADP_SIGNAL

PJP1

PC12
1

PR8
2K_0402_5%


1

1

2 1

ADP_ID <34>

0.01U_0402_25V7K
PC1
2
1

TP0610K-T1-E3_SOT23-3

G

PQ3

499K_0402_1% 340K_0402_1%
PR4 1
PR1 1
2
2

2

BATT_A

AC_LED# <34>

2

BATT_TEMP <34>

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
DC Connector/CPU_OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

37

of

46

A

B

P2

4

PC122
@0.1U_0603_25V7K

1
2

1

1
3

3

1

470K_0402_5%
PQ117

1
3

1
PU106
4

S
SSM3K7002FU_SC70-3

NC

5

3

PC124
0.1U_0603_25V7K

2

1
1

1
SSM3K7002FU_SC70-3
3

P
PACIN

yc

PR142

2
2
1
2

3
2
1

1

1

2

<37>

Y

74LVC1G14GW_SOT353-5

PR122
681K_0402_1%
1
2

3

Add one shoot schmeatic.

1

1

-

O

1

4

7

PACIN

LM393DG_SO8

PR134
10K_0402_5%
2

2

PD103
RLZ4.3B_LL34

2

PC126
1000P_0402_50V7K

PR133
10K_0603_0.1%

PU102B

1

+

6

<22,34>

2

8
5

1

74LVC1G17GW TSSOP

PR130
10K_0402_1%
1
2

P

PACIN_2

G

2

1
PU104
4

Y

1

A

AC_IN

PR127
10K_0402_1%

2

2

NC

5
P

PC132
0.047UF_0402_16V7
1

G

2

PR126
100K_0402_1%

3

74LVC1G17GW TSSOP

2

2
1
PD105
RLS4148_LL34-2

PR148
PU105 10K_0402_5%
4
1

Y

PR149
560K_0402_1%
2
1

NC

1

5

P
G

A

PR124
1K_0402_5%
1
2

VIN
VIN
+3VL

S
FSTCHG#
D

S

PQ113
SSM3K7002FU_SC70-3

2
G

FSTCHG

PR136
60.4K_0402_1%
1
2 VIN_1

PU103

ACDET

2

2

1

22P_0402_50V8J

2

PR137
20K_0402_1%

PC127

100K_0402_1%
PR138

1

REF

3

NC

2

5

NC

1

1.24VREF

ANODE

4

APL1431LBBC-TR_SOT23-5

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

2008/05/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

B

CATHODE

1

4

A

A

D

2
G

2

<34>

2

3

ht

PQ112
SSM3K7002FU_SC70-3

STD_ADP <34>

4

2

1

2

2

om

21

20

19
1

1

<34>

2

1

1

PC129
1500P_0402_50V7K

PC128
220P_0402_50V7K
2
1

p.

1

DPMDET

CELLS

SRP

SRN
18

17
BATT

//
m

PU102A
LM393DG_SO8

PACIN_1

PR132
100K_0402_5%
2
1

D

2
G
3

G

1

1

1

P

1

8

CHGEN#

2

1.24VREF

IREF

PR121
200K_0402_1%

2

PR128
10K_0402_5%
2
1

1
2

PR129
10K_0402_1%
2
1

2

1
2

PC125
0.1U_0603_25V7K

+3VL

3

1

+3VL

O
-

PR120
2
1
133K_0402_1%

+3VL

PQ119
BAT_ID

PQ116

2

PR147
220K_0402_1%

STD_ADP 3
47K_0402_5%
PR119

2
G

+3VL

PR131
133K_0402_1%

2

PC118
0.1U_0402_10V7K

S

tp
:

+3VL

PR125
47_1206_5%

2

16

15
IADAPT
PC121
100P_0402_50V8J
2
1

PC120
0.22U_0603_10V7K
2
1
2
1

PR123
1M_0402_5%
1
2

VIN_1

PR135
10K_0603_0.1%

PQ111
SSM3K7002FU_SC70-3

1

BQ24740VREF

D

PC123
0.1U_0402_10V7K

PD104
1SS355_SOD323-2


+

PR117
100K_0402_5%
1
2

PQ110

FDS6690AS_SO8

G

VIN

3

PC119

1U_0603_10V6K

2
G
S
PQ115

D

PR118
10K_0402_5%
1
2

ADP_I

22

PGND
SRSET

IADAPT

1
2

2

ISYNSET
BAT

14

SSM3K7002FU_SC70-3

+3VL

S

<34>

5
6
7
8

4

PR115
100K_0402_1%
PR116
39K_0402_5%

4

4

DL_CHG

23

LODRV

PR139
@4.7_1206_5%

S

D

G

EXTPWR

1 1

13

Charge Detector

VIN

1

5
6
7
8

1

D

3

2

PQ120

2
G

47P_0402_50V8J

REGN

2

1

24

S

2

REGN

D

PC133
1
2

VADJ

1

12

BATT

2

LX_CHG

ACOFF

PR112
0.015_1206_1%
1
2

PC115
4.7U_0805_25V6-K
2
1
4.7U_0805_25V6-K
PC116

25

<34>

PC114
4.7U_0805_25V6-K

PH

1

VDAC

2

11

DTC115EUA_SC70-3

PL102
10U_LF919AS-100M-P3_4.5A_20%
1
2

1SS355_SOD323-2

2

PC117
1U_0603_10V6K

3

2

DH_CHG

PD102
VADJ

1

2
1SS355_SOD323-2

PC105
4.7U_0805_25V6-K
2
1

26

PQ106
PQ108
AO4466_SO8

2

VCTRL

1

HIDRV

+3VL

1

S

2

27

1

2
G

SSM3K7002FU_SC70-3

2
1

CHGEN

2

ACP

ACN

LPMD

BTST

2

VREF

28

1
PQ109
SSM3K7002FU_SC70-3
<34>

PC104
4.7U_0805_25V6-K

2
1

1
2

PC108
3

4

5

ACSET

ACDET

PU101
BQ24740RHDR_QFN28_5X5

PVCC

PC110
1U_0805_25V6K
1
2
PR141
PC111
0_0402_5% 0.1U_0402_10V7K
BST_CHG 1
2
1
2
4

PR144
0_0402_5%
1

2

3
2
1

10

PR108
10_1206_5%
1
2
29

PR143
470K_0402_5%

PR146
4.7K_0402_5%

PACIN_2

PC113
4.7U_0805_25V6-K
2
1

AGND

PR105
10K_0402_5%

ACOFF#

/x
/

9

VIN

CHG_B+

TP

1
2
3

SSM3K7002FU_SC70-3

PC109
@0.1U_0603_25V7K

PC131
@680P_0603_50V7K

IADSLP

BQ24740VREF

2

1

PR113
143K_0402_1%
PR114
@0_0402_5%
1
2

D

2
G
3

8

8
7
6
5

PR103
47K_0402_5%
1
2

CHG_B+

su

PQ107
SSM3K7002FU_SC70-3

6

7

S

1

LPREF

2

PC112
1
2

PD101

0.1U_0603_25V7K

1
1
SUSP#

PR109
150K_0402_5%

PACIN_1 <39>

ACOFF#

2

PR110
0_0402_5%
1
2

1

1
3
3

<27,29,34,36,41>

PQ105
DTC115EUA_SC70-3

PR111
3K_0402_1%
1
2

PC102
1U_0603_6.3V6M
1
2

ACSET ACSET

PC107
@0.01U_0402_16V7K

1U_0603_6.3V6M

PACIN

ACDET

PR104
0_0402_5%
2

HCB2012KF-121T50_0805
2
PL101

1

2

CHGEN#

2

1

D

2
G

1

2

PQ104
DTA144EUA_SC70-3
1

1
1

1

PR151
150K_0402_5%

2

AC_SET

2
1
PR106
200K_0402_5%

2

<34>
2

PR140
100K_0402_5%

3

1

3

PC106
0.47U_0603_16V7K
2
1

2

2

PR107
47K_0402_1%

PC101
47P_0402_50V8J

PR150
200K_0402_5%
2
1

3

DTA144EUA_SC70-3
PQ118

PR102
0.012_2512_1%
4
1

4

PR101
47K_0402_5%
1
2

1

BATT_A
PQ114
FDS6675BZ 1P SO8

PQ102
FDS6675BZ 1P SO8
8
7
6
5

1
2
3

1

1
2
3

PC103
4.7U_0805_25V6-K

1
2
3

4

8
7
6
5

BATT

B+

PQ103
SI4835BDY-T1-E3 1P SO8
8
7
6
5

PC130
@0.068U_0402_16V7K
1
2

P4
PQ101
SI4835BDY-T1-E3 1P SO8

2

D

3

VIN

C

C

Compal Electronics, Inc.
Charger
Document Number

Rev
0.4

LA-4481P
Monday, September 08, 2008
D

Sheet

38

of

46

A

B

C

D

E

1

2VREF_51125

1

PR304
20K_0402_1%
2

ht

PR313
100K_0402_5%
2

PC313
4.7U_0805_25V6-K

1
2

5
6
7
8

2

+3VL
4

+5VALWP

PQ304
FDS6690AS_NL_SO8

2

1
1

PR317
100K_0402_5%

1

2

PU301
TPS51125RGER_QFN24_4X4

2

LG_5V

3/5V_OK <21,41>

PC315
@680P_0603_50V8J

19

PL303
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2
PR316
@4.7_1206_5%

DRVL1

3
2
1

LX_5V
5
6
7
8

20

+

PC310
150U_D_6.3VM

PC311
10U_0805_10V6K

1

2

1

2

2

B++
PC312
0.1U_0603_25V7K

3

2VREF_51125

+3VL

+3VLP
PJP301

PJP302
1

+5VALWP

2
2

+5VALW

(4.5A,180mils ,Via NO.= 9)

+3VALW

(3A,120mils ,Via NO.= 6)

1
PAD-OPEN 2x2m

PAD-OPEN 4x4m
PJP303

VL

PQ307
SSM3K7002FU_SC70-3
2
G

PC305
4.7U_0805_25V6-K
2
1

su
LL1

p.

22

21

VCLK
18

VIN

VREG5

17

16

PC304
2200P_0402_50V7K
2
1

/x
/

2

1

VFB1

VREF

ENTRIP1

VBST1

DRVH1

VL

2

//
m
S

4

PR308
PC308
2.2_0402_5% 0.1U_0402_10V7K
BST_5V 1
PR310
2 1
2
0_0402_5%
UG_5V
1
2

3
2
1

EN0

GND

PR312
1M_0402_1%
2

tp
:

1
3

ENTRIP2
1

1

DRVL2

15

12

23

PQ302
AO4466_SO8

1

+3VALWP

2

+5VL

VL
PJP304

PAD-OPEN 4x4m

2

EC_ON <34,36>

1
PAD-OPEN 2x2m

S

1

3

1
3

LL2

yc

<7,37>

1
2
3

ENTRIP1
3

D

1

S

11

24

PQ306
SSM3K7002FU_SC70-3

1

PR314
100K_0402_5%
2

2

PC318
0.047U_0603_16V7K

D

2
G

S

<38> PACIN_1

DRVH2

VO1

PGOOD

PR311
191K_0402_1%

1
2
G

D

VBST2

1

PQ303
AO4468_SO8

D

PQ308
SSM3K7002FU_SC70-3
1
2
2
PR318
G
604K_0402_1%

9
10

13

B++

VREG3

EN0

4

VO2

8

om

LG_3V

3

PQ305
SSM3K7002FU_SC70-3

UG_3V

1
1
2

150U_D_6.3VM

2

2

PC309

+

PC314
@680P_0603_50V8J

1

PR315
@4.7_1206_5%

8
7
6
5

1
2 1
2
0_0402_5%
PC307
0.1U_0402_10V7K
LX_3V

BST_3V

7

SKIPSEL

PR309
0_0402_5%
1
2

PL302
4.7UH_SIQB74B-4R7PF_4A_20%
2
1

+3VALWP

PR307

TONSEL

P PAD

2
1
2
3

UG1_3V

2

VFB2

ENTRIP2

25

14

PC306
10U_0805_6.3V6M

4

1

PQ301
AO4466_SO8

B++

PR306
115K_0402_1%
2

1

3

2

6

8
7
6
5

1
2

PC303
4.7U_0805_25V6-K

PR305
115K_0402_1%
1

ENTRIP1

PR303
20K_0402_1%
1
2

+3VLP

2
PC301
2200P_0402_50V7K
2
1

1

PR302
30.9K_0402_1%
2

4

PL301
HCB2012KF-121T50_0805

1

ENTRIP2

B++

B+

2

5

PR301
13.7K_0402_1%
1

1

1

PC302
0.22U_0603_10V7K

2

1

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
3.3VALWP/5VALWP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

39

of

46

A

B

C

D

1

1

+5VALW

1

1
2
PC413
@10P_0402_50V8J

ht

2

1
2

4.7U_0805_25V6-K
PC404
2
1

1
+

PQ402
FDS6690AS_NL_SO8

2

+1.8VP

3

tp
:

3

4

TPS51117RGYR_QFN14_3.5x3.5
DL_1.8V

//
m

1
2
14.3K_0603_0.1%

PR409
10K_0603_0.1%

DRVL

yc

7

PR408

PGOOD

PC415
4.7U_0805_10V6K

9

PC408
220U_D2_4VY_R25M

10

2
PR406
10.7K_0402_1%

PC412
@680P_0603_50V8J

V5DRV

1

1

11

B+

2

PL402
2.2UH_PCMC063T-2R2MN_8A_20%
1
2

2

TRIP

PQ401
AO4466_SO8

1

LX_1.8V

2

2

6

su

15
TP

14

12

DH_1.8V_1

2

VFB

LL

PR410
1
2
0_0402_5%

PR407
@4.7_1206_5%

5

DH_1.8V

4.7U_0805_25V6-K
PC403
2
1

5
6
7
8
V5FILT

13

3
2
1

4

DRVH

HCB1608KF-121T30_0603
1
2

4

om

VOUT

VBST

3

PGND

PC409
1U_0603_10V6K
+1.8VP

TON

2

PC402
0.1U_0402_10V7K

3
2
1

BST1_1.8V 1

1

2
1
0_0402_5%

2

8

2
PR405

1

PU401
PR404
255K_0402_1%
1
2

EN_PSV

PR403
316_0402_1%

1

2

PR402
0_0402_5%

p.

BST_1.8V
1

GND

2

5
6
7
8

1+5VALW

+5VALW

+1.8VP

PL401

1.8V_B+

2

PC401
@1000P_0402_50V7K

2200P_0402_50V7K
PC405

1

<27,34,35,36> SYSON

/x
/

PR401
0_0402_5%
1
2

1

+1.8VP

PJP401

2

+1.8V

(7A,280mils ,Via NO.= 14)

PAD-OPEN 4x4m

4

4

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

2008/05/29

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

Compal Electronics, Inc.
1.8VP
Document Number

Rev
0.4

LA-4481P
Monday, September 08, 2008
D

Sheet

40

of

46

A

B

C

D

E

1

1

1

2

2

2

B+++

1

1

LX_1.2V

DR VL1

19

LG_1.2V

4

PR512
33K_0402_5%
2

2

PC512
0.1U_0402_16V7K

1

1
2

PC515
4.7U_0805_10V6K

(4A,160mils ,Via NO.=8)

PJP501
1

1

+

3

+5VALW

(6A,240mils ,Via NO.=12)

+1.1VSP

+1.2VALWP

3/5V_OK <21,39>

2

1

+1.2VALWP

PL503
3.3UH 30% MSCDRI-7030AB-3R3N 4.1A
1
2

PQ504
AO4468_SO8

PR510
10.5K_0402_1%

2

2

1
2

ht

PC514
1U_0603_10V6K

2
UG1_1.2V

TPS51124RGER_QFN24_4x4

PR514
3.3_0402_5%

PC513
@0.1U_0402_10V7K

1

1
PR509
0_0402_5%

PC510
4.7U_0805_6.3V6K
1
2

20

PC505
2200P_0402_50V7K
2
1

su

1

2
VFB1

4

3
GND

VO1
LL1

2

PR515
1K_0402_5%
2
1

14

PR511
15.4K_0402_1%
1
2

tp
:

<27,29,34,36,38> SUSP#

UG_1.2V

1

PR513
0_0402_5%
2

21

PC507
0.1U_0402_10V7K

PC511
220U_B_2.5VM_R35M

PQ503
FDS6690AS_NL_SO8

22

4

2

2

3

13

4

p.

DR VL2

BST_1.2V

VBST1

DR VH1

om

12

PR507
0_0402_5%
2
1

PGND1

LG_1.1V

TRIP1

LL2

23

18

11

17

LX_1.1V

24

EN1

yc

DR VH2

PGOOD1

PQ502
AO4466_SO8

1

VBST2

10

TONSEL

6

5

VO2

9

UG_1.1V

PGND2

BST_1.1V

//
m

2

1
2
3

+

PC509
4.7U_0805_6.3V6K
2
1

PC508
220U_D2_4VY_R25M

1

EN2

V5IN

1
PR508

PGOOD2

8

V5FILT

2
0_0402_5%

8
7
6
5

+1.1VSP

UG1_1.1V

PL501
2.2UH_PCMC063T-2R2MN_8A_20%
2
1

7

16

1
2
3

PC506
PR506
0.1U_0402_10V7K
0_0402_5%
2
1 2
1

15

4

P PAD

VFB2

2

AO4466_SO8

+1.1VSP

PU501
25

TRIP2

PC503
@0.022U_0603_25V7K

1

8
7
6
5

VCCP_POK

PQ501

B+
PL502
HCB2012KF-121T50_0805
2
1

5
6
7
8

+1.1VSP

2

+1.2VALWP

1

1

PR505
0_0402_5%

PC502
2200P_0402_50V7K
2
1

1
2

PC501
4.7U_0805_25V6-K
2
1

PC517
4.7U_0805_25V6-K

B+++

1

PC504
4.7U_0805_25V6-K
2
1

2

PR504
11.5K_0402_1%

5
6
7
8

1

PR503
18.7K_0402_1%

3
2
1

1
2
PR517
10_0402_5%

PR502
24.9K_0402_1%

3
2
1

PR501
11.5K_0402_1%

2

/x
/

+1.1VSP

2

PR518
0_0402_5%
1

+1.1VS

B+++

PJP502
2

+1.1VS

1

+1.2VALWP

PAD-OPEN 4x4m

2

+1.2VALW

PAD-OPEN 4x4m

PJP503
4

+1.1VSP

1

2

4

+1.1VS

PAD-OPEN 4x4m

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

1.1VSP/1.2VALWP
Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

41

of

46

A

B

C

D

E

1

1

+1.8V
+1.8V

GND

VCNTL

6

NC

5

PU603

+5VALW

NC

8

TP

9

PR606
1K_0402_1%

G2992F1U_SO8

3

VREF

NC

7

4

VOUT

NC

8

TP

9

+5VALW

PC612
1U_0603_16V6K

G2992F1U_SO8

2

S

+1.5VSP
1

2

2

1

D

2
G

2
1
PC611
0.1U_0402_16V7K

PR608
0_0402_5%

PC606
@0.1U_0402_16V7K

PR607
5.1K_0402_1%
2

2

3

1

<36> SUSP

1

su

1
PC605
10U_0805_6.3V6M

1

S

PQ602
SSM3K7002FU_SC70-3

p.

2
G

+0.9VP

2

PR603
1K_0402_1%

D
2

2

PR604
@0_0402_5%

1

1

2
1
PC604
0.1U_0402_16V7K

PQ601
SSM3K7002FU_SC70-3

1

1

2
PR602
0_0402_5%

2

<36> SUSP

5

VREF1.5V

1

3

<36> SYSON#

6

NC

2

2

PC603
1U_0603_16V6K

VCNTL

GND

2

VOUT

VIN

2
1

4

PC613
10U_0805_10V4Z

/x
/

NC

1

VREF

7

2

PR601
1K_0402_1%

3

2

2

PC601
10U_0805_10V4Z

1

1

VIN

2

1

1

1

1

PU601

PC614
10U_0805_6.3V6M

2

+1.5VS

(1A,40mils ,Via NO.= 2)

+2.5VSP

GND
1

3

1

3
1

OUT

PR605
@150_1206_5%

ht

1

IN

2

PJP603
+1.5VSP

2

2

PAD-OPEN 3x3m

(2A,80mils ,Via NO.= 4)

PC608
4.7U_0805_6.3V6K

+0.9V

1

2

2

1

PC607
1U_0603_6.3V6M

+0.9VP

3

(500mA,40mils ,Via NO.= 1)

PU602
APL5508-25DC-TRL_SOT89-3
+3VS

tp
:

PJP601

//
m

yc

om

2

PC610
@0.1U_0402_16V7K

PAD-OPEN 3x3m

PJP602
+2.5VSP

1

2

+2.5VS

(500mA,40mils ,Via NO.= 1)

PAD-OPEN 3x3m

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
0.9VSP/2.5VSP/1.5VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

42

of

46

B

C

2

1

4.7U_0805_25V6-K

1
2

UGATE NB1

1
PR241
0_0402_5%

1

<7> CPU_VDD1_FB_H

2

1
PR239
0_0402_5%

PC242
2 1000P_0402_50V7K

2

2

B

2

PC238
100U_25V_M

PC215
1000P_0402_50V7K
2
1

+

1
+
2

3
2
1

PR221
16.5K_0402_1%
2
1

PR217
4.02k_0603_1%
1
2

PC219
0.1U_0603_25V7K

1

2

ISP 0

1
PR228
2.2_0603_5%

TP

PC224
0.22U_0603_10V7K

4

+CPU_CORE_1

4

3
2
1

AO4714 1N SO8

PQ208
3
2
1

PQ207

ISP 1

PC226
@680P_0603_50V8J

AO4714 1N SO8

PC231
180P_0402_50V8J
1

2

PR236
6.81K_0402_1%
2

1

PC257
390P_0402_50V7K
2
1

PC222
2200P_0402_50V7K
2
1

PC221
4.7U_0805_25V6-K
2
1

1
+CPU_CORE_1
PL204
0.36UH_PCMC104T-R36MN1R17_30A_20%

PR233
4.02k_0603_1%
1
2

PC229
0.1U_0603_25V7K

PC230
1000P_0402_50V7K
2
1

2

PC220
4.7U_0805_25V6-K
2
1

3

2
PR231
16.5K_0402_1%
2
1

BOOT1

PC236
4.7U_0805_25V6-K
2
1

25

UGATE1_1

PR229
@4.7_1206_5%
1 2
1

BOOT1

4
PR226
1
2
0_0603_5%
2
1
2

2

UGATE1

UGATE1

CPU_B+

3
2
1

PHASE1

5
6
7
8

27

26

PC237
4.7U_0805_25V6-K
2
1

LGATE1

PHASE1

PC240
220P_0402_50V7K
2
1

5
6
7
8
PQ206
AO4474_SO8

PC256
1500P_0402_50V7K
2
1

2

PC218
@680P_0603_50V8J

1
1 2

PR220
@4.7_1206_5%

5
6
7
8
3
2
1

3
2
1

PQ205
AO4714 1N SO8

+CPU_CORE_0

PL203

1

2

ISP 1

1
PR238
54.9K_0402_1%
2
1

PC232
1200P_0402_50V7K
PR240
1K_0402_1%
2
1

2

1

4

PR243
255_0402_1%
2
1

4700P_0402_25V7K
PC233

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

PC255
390P_0402_50V7K
2
1

PC254
1500P_0402_50V7K
2
1

PC214
2200P_0402_50V7K
2
1

PC213
4.7U_0805_25V6-K
2
1

PC212
4.7U_0805_25V6-K
2
1

PC235
4.7U_0805_25V6-K
2
1

PC234
4.7U_0805_25V6-K
2
1

/x
/
PC239
220P_0402_50V7K
2
1

su
p.

om

BOOT0

UGATE_NB

PHASE_NB
ISP1

ISN1

24

23

4

5
6
7
8

28

4

yc

29

PGND1

0.36UH_PCMC104T-R36MN1R17_30A_20%
2
1

LGATE0

//
m
LGATE1

1

UGATE0_1

5
6
7
8

2

4

<7> CPU_VDD1_FB_L

5
6
7
8

1
2

1
2
BOOT_NB

UGATE NB

PHASE NB
38

37

30

tp
:
COMP1

VW1

22

ht

21

FB1
20

VSEN1

VDIFF1
19

18
VSEN1

PVCC

PC211
@47U_25V_M

1
BOOT_NB1 2

PR207
14K_0402_1%
LGATE NB
PGND_NB

LGATE_NB

OCSET_NB

RTN_NB

VSEN_NB

FSET_NB
17

32
31

PQ204
AO4714 1N SO8

2

1

PC241
2 1000P_0402_50V7K

2
1
PR237
0_0402_5%

<7> CPU_VDD0_FB_L

PHASE NB

1
PR209
0_0402_5%
2

1
43

44

45

46

16

2

6.81K_0402_1%

1
PR235
0_0402_5%

COMP_NB

VCC

RTN1

1

VSEN0

VW0
ISN0

COMP0

12

1
2
PC228
1000P_0402_50V7K

<7> CPU_VDD0_FB_H

ISL6265IRZ-T_QFN48_6X6

FB0

11

PGND0
LGATE0

1

2

49

VDIFF0

PR232

54.9K_0402_1%

FB_NB

RBIAS

PC225
1
2

1200P_0402_50V7K
1
2
PC227
180P_0402_50V8J

48

ENABLE

RTN0

2

SVC

ISP0

PR230
1

PHASE0

OCSET

2

1K_0402_1%

33

15

1

PHASE0

VSEN0

3

SVD

9
10

4700P_0402_25V7K
PR227

UGATE0

UGATE0

14

2

255_0402_1%

PWROK

34

8

PQ203
AO4474_SO8

1
2
0_0603_5%
PR219

36

13

1

82.5K_0402_1%

PC210
2.2U_0603_6.3V6K

2.2_0603_5% 0.22U_0603_10V7K
PR214
PC217
1
2 1
2

35

1
@1000P_0402_50V7K
PC244
2
1
@1000P_0402_50V7K
PC245
2
1
@1000P_0402_50V7K
PC246
1
@1000P_0402_50V7K
PC247

34.8K_0402_1%
PC223
1
2

2

4

BOOT0

PGOOD

PL202
SMB3025500YA_2P

+5VS

BOOT_NB

OFS/VFIXEN

ISP 0

VR_ON

PR225

VIN
1

+CPU_CORE_0

<7> CPU_SVC

47

PR216
10K_0402_1%
2
1
CPU_SVD

<34>

PU201

2
PR246 1100K_0402_5%
2
ISL6265_PWROK 3
1
2
PR234 @100K_0402_5%
PR218 1
SVD
4
2
0_0402_5%
PR222 1
SVC
5
2
0_0402_5%
6
PR223
PR224
7
1
2
1
2

<34>
VGATE
<20> H_PWRGD
<7,21,34> SB_PWRGD
<7>

PR215
@10K_0402_5%

B+

CPU_B+

PR211
1_0603_5%

39

2
PR212
0_0402_5%
1
2
PR213
@0_0402_5%
1
2

PC206
0.1U_0402_16V7K

2

VSEN_NB

1

RTN1

+5VS

+3VS

1

40

2

PC216
0.1U_0603_25V7K

41

1

CPU_B+

RTN0

Connect to EC pin 110.

PC243
1000P_0402_50V7K

PR208
2_0402_5%
1
2

RTN_NB

S

42

2

33P_0402_50V8K
PC209
2
1

3

PC207
0.1U_0402_16V7K

2
1
2
1
PR210
PC208
44.2K_0402_1% 1200P_0402_50V7K

1

1

PQ209
SSM3K7002FU_SC70-3

2

1

PR205
2_0402_5%
1
2

D

2
G

VFIX_EN

PC204

2

PC205
1000P_0402_50V7K

+5VS
<34>

LGATE NB

ISL6265_PWROK

1

CPU_B+

PR203
0_0402_5%

2

PR206
0_0402_5%
2
1

1

PR204
22K_0402_1%
1
2

8
7
6
5

PC203
2200P_0402_50V7K

1
2
3

4

2

E

PQ202
AO4466_SO8

PQ201
AO4468_SO8
8
7
6
5

1
2
3

2

1
2
<7> VDD_NB_FB_L

10U_0805_6.3V6M
PC201

<7> VDD_NB_FB_H

1

+

D

2
1
4.7UH 30% MSCDRI-7030AB-4R7N 3.3A

4

PL201

+CPU_CORE_NB

PC202
220U_B_2.5VM_R35M

A

C

D

CPU_CORE
Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

43

of

46

A

B

C

D

E

Version Change List ( P. I. R. List ) for Power Circuit
1

37

2

38

3

39

4

40

5

41

6

42

7

38

8

37

9

38

10

39

11

38

Date

Request
Owner

2008/05/21

PWR

HW request

PR8 change the value from 100 to 2K.

0.2

Charger

2008/05/21

PWR

Modify PR102 footprint and PQ101,PQ103 change from AM4835 to SI4835BDY,
PWR request, solve inrush current. PQ103 change from AM4835 to FDS6675BZ, PC106 change from 0.22u to 0.47u,

0.2

3.3VALWP/5VALWP

2008/05/21

PWR

PWR request, modify OCP

PR305 change the value from 140K to 95.3K, PR306 change the value
from 133K to 105K, PC318 change the value from 0.022u to 0.047u.

0.2

2008/05/21

PWR

PWR request, modify OCP.

PR406 change the value from 15.4K to 10.7K.

0.2

2008/05/21

PWR

For PWR request, prevent leakage
power and modify OCP.

Add PR515 1k_0402_5%, PR511 change the value from 18.2K to 15.4K,
PR510 change the value from 17.8K to 10.5K.

0.2

CPU_CORE

2008/05/21

PWR

PWR request

Modify PC206 change the footprint from 0603 to 0402,
PR207 change the value from 15.4K to 14K.

0.2

Charger

2008/06/04

PWR

HP request

Add 4 cell schematic, add net name BATT_A.

0.2

2008/06/12

PWR

Thermal request, prevent PH1
will OTP on TPDL.

PR12 change the value from 2.55K to 2.21K.

0.2

2008/06/18

PWR

PWR request

Add PC133 220P_0402, PR147 change the value
from 100K_0402_5% to 470K_0402_1%.

2008/07/21

PWR

PWR request

2008/07/28

PWR

PWR request

Title
DC Connector
/CPU_OTP

1.8VP
1.1VSP/1.2VALWP

Issue Description

Add PR311 191K_0402_1%, PR312 1M_0402_1%.

0.2

Add 4 cell one shoot schematic, add net name PACIN_2

0.3

//
m

Charger

om

3.3VALWP/5VALWP

0.2

yc

Charger

1

2

p.

2

DC Connector
/CPU_OTP

Rev.

Solution Description

/x
/

Page#

su

1

Item

3

ht

tp
:

3

4

4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

Title

Compal Electronics, Inc.
Power Changed-List History-1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.4

LA-4481P

Monday, September 08, 2008

Sheet
E

44

of

46

5

4

Item

<2008.06.05>

30

Add R429, R430, R431, C642

0.2

Fix Audio MIC no function and follow Ripley schematics

2

Fix ENE cap-board could not detect

34

Remove R410 & R411 & C627

0.2

3

Fix BT no function and follow Ripley schematics

32

change BT pin assignment

0.2

1

change power rail to solve +3vs leakage

07

LDT_RST# & H_PWRGD_CPU & LDT_STOP# & CPU_LDT_REQ# change
power rail to +1.8VS

2

Remove 0 ohm resisters at LDT_STOP# & CPU_LDT_REQ#

12

Remove R54 & R55 (0 ohm)

3

Remove 0 ohm resisters at NB_PWRGD

21

Remove R164 (0 ohm)

0.2

4

Change value to solve AC plugged/unplugged power status issue.

22

Change R408 to 300k ohm

0.2

5

add 150uF Cap to solve hot-plug for Multi-bay ODD

25

Add C643 150uF

0.2

6

Remove HP switch Transisters and change Cap size to solve DFB issue.

30

Change C523 & C524 size and remove Q16, Q17, Q24...

0.2

7

Remove LPC debug connector

33

Remove JP14

0.2

8

Remove 0 ohm resisters at SPI ROM

33

Remove R320~323 (0 ohm)

0.2

9

add GND shaping at E-SATA

32

Add E-SATA GND shaping

change pin assignment (follow Ripley)

Change Keyboard pin assignment to follow Ripley design

34
34

12

Add Keyboard backlight control circuit

34

13

Remove Cap-sensor baord power LDO

35

remove U29....

0.2

14

Add Resister to protect Q42, Q41

36

Add R381 & R401

0.2

35

Add C600, C601 and Change R356, R357 size to 300ohm bead

0.2

18

Add Q4 and R54

0.2

<2008.06.19>

Solve LED panel flash issue when AC IN

cap-board

34

yc

change KB backlight connector pin assignment

1

<2008.08.01>

1

Vari-Bright design change for EC & RS780 common use

<2008.08.04>

1

Reserve Caps to protect ESD

2

Change R value for LED brightness
Fix

4

0.2

C

Reserve Cap to protect T/P ON/OFF

7

0804 Change value to adjust LED brightness

ht

Fix FPR ESD issue

6

pin1 & 2 (Power), pin3 & 4 (GND) swapped

0.2

add R301 and pull up +VDDA_CODEC_R

0.3

32

change pin count from 6 pins to 4 pins

0.3

35

OTS#0392705 (WLAN Slot Pin 24 is tied to different power than pins 2, 52, 39 and 41)

Reserve ESD diode to protect SPK

5

0.2

add Q24, R426

29

18, 12

tp
:

change FPR connector to fix Assy DFB issue.

//
m

Fix external and internal MIC auto switch issue

2

3

0.2

change R345 to 300Kohm

p.

om

Add and reserve EMI soulution for ENE

1

D

0.2

Change value to solve AC plugged/unplugged power status issue.

2

A

0.2

11

1

<2008.09.04>

0.2

10

<2008.06.16>

B

M.B. Ver.

1

C

<2008.07.30>

1

Modify List

/x
/

D

2

PAGE

su

<2008.05.09>

3

Fixed Issue and change item

Add D38, D39, R76

0.3

Add C595, C606

0.3

pin1 & 2 (Pow

28

Change R276 value to 1.2Kohm

0.3

27

Unmount R245 and install R244

0.3

30

Add D55, D56

0.3

32

Install D25

0.3

35

Add C595, C606

0.3

35

Change R369 value to 1.2kohm

0.3

35

Install C597

0.3

Uninstall D39, Delete D38

0.4
0.4

8

Install Cap to fix ESD issue

1

Remove Varibright function

2

Fix SMT DFX issue

28

Change D16 footprint

3

Follow Vendor suggestion to change CR_LED#

28

Change power rail from+5VS to +3vs

4

Reserve R for protect LED panel flash control

18

Add R410

12, 18

B

0.4
0.4

5

A

0.4

6

0.4
Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

Title

Compal Electronics, Inc.
HW PIR(1)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.4

LA-4481P

Date:

5

4

3

2

Monday, September 08, 2008

Sheet
1

45

of

46

A

om

p.

su

/x
/

Calypso power sequence

1

ht

tp
:

//
m

yc

1

Compal Secret Data

Security Classification
2007/08/28

Issued Date

Deciphered Date

2006/03/10

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Notes List
Rev
0.4

LA-4481P

Date:

A

Monday, September 08, 2008

Sheet

46

of

46



---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.4
Linearized                      : No
Page Count                      : 46
XMP Toolkit                     : XMP toolkit 2.9.1-13, framework 1.6
About                           : uuid:cd18e935-dec3-4231-bd86-d3b7e5c0e0cf
Producer                        : Acrobat Distiller 6.0 (Windows)
Modify Date                     : 2008:09:10 12:12:38+08:00
Create Date                     : 2008:09:10 12:12:38+08:00
Document ID                     : uuid:a29ffd8a-6791-418f-8a0c-e6cfbd6c391d
Format                          : application/pdf
Title                           : untitled

EXIF Metadata provided by EXIF.tools