VOYAGER_LA 6601P_MB_1130 Compal LA 6601P
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A B C D E MODEL NAME : PAR00 PCB NO : LA-6601P (DAA00002000) BOM P/N : TBD 1 1 Compal Confidential Voyager Schematic Document 2 2 Rev: 1.0(A00) 2010-11-30 3 3 @ : Nopop Component 4 4 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title Cover Sheet Size B C D Rev 1.0 LA-6601P Date: A Document Number Tuesday, November 30, 2010 Sheet E 1 of 63 A B C Compal Confidential HDMI 1.3 input Conn Project Code : PAR00 File Name : LA-6601P LVDS LVDS MUX LVDS Panel Conn P.26 LVDS MUX LVDS MUX P.26 P.25 eDP Panel P.24 Conn DP MUX P.24 mini DP Conn P.29 DP Rediver P.29 CRT Conn 2 P.38 DP MUX P.29 P.27 P.28 Mini Card -2 Wireless Display DMC (Full) P.38 Intel Sandy Bridge Processor eDP DP (DIS) P.27 HDMI MUX FDI x8 (UMA) HDMI SATA Port 2 P.14 HDMI (DIS) HDMI SATA2.0 DisplayPort CRT P.30 HDMI PCIE BUS Port 4 Card Reader USB 3.0/2.0 Host Ctrl. P.39 USB 3.0 /2.0 8 in 1 Combo Conns x 2 Socket P.39 Card Reader/B LAN(GbE) AR8151 4 USB2.0 BGA 989 Balls HD Audio SPI P.36 SATA ODD Conn. ESATA Redriver P.38 USB Charger LPC Bus 3D IR USB 2.0 Conn x 2 dual-stack USB Port 2 USB Port 3 Digital Camera ( LVDS port3/eDP port2 ) P.26,24 USB Port 8 AlienFX/ELC P.41 BT 2.1 /BT 3.0 P.38 3 IDT 92HD73 P.34 ENE KB930 P.44 P.44 PS2 Amplifier x2 MAX9724 P.34 SPI Int.KBD BIOS ROM P.46 P.44 Array Mics x2 P.34 S/PIDF Jack x1 P.35 MIC Jack x1 P.34 Media / Mode Buttons P.42 HeadPhone Jack x2 P.34 Amplifier x1 MAX9736 P.35 P.47 4 Int. Speaker P.35 5W x2 DC/DC Interface CKT. Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Power Circuit DC/DC P.48~P57 Title Block Diagram Size B C D Document Number Rev 1.0 LA-6601P Date: A P.40 Audio Codec P.15 P.42 P.37 P15~22 SPI ROM Touch Pad 2 P.37 USB / eSATA Conn. USB Port 4 P.33 P.46 SATA HDD-2 Conn. USB Port 1 USB Port 6 RJ45 P.15 Power On/Off CKT. USB Port 7 USB Port 0 Mini Card-1 WLAN (Half) P.33 P.36 P.46 Port 3 ENE 3810 RTC CKT. Intel Cougar Point PCH HDMI Port 1 SATA Rediver SATA Port 1 USB Port 9 Port 2 3 DMI x4 gen 2 SATA3.0 LVDS Port 6 SATA HDD-1 Conn. SATA Port 4 P.28 HDMI MUX P.10~13 P.36 HDMI HDMI (DIS) HDMI BANK 0, 1, 2, 3 P.4~9 100MHz 5GB/s 100MHz 2.7GT/s MXM III Conn. 204pin DDRIII SO-DIMM x4 SATA Port 0 rPGA 988 Socket CRT Dual Channel 1 1.5V DDRIII 1066/1333 MHz DisplayPort LVDS DisplayPort (DDRIII) Memory Bus 2C 35W 4C 45W PEG x16 (DIS) CRT (DIS) CRT CPU XDP Conn. P.5 P.45 P.31 LVDS to DP SW STDP4028 P.32 LVDS (DIS) LVDS DP (DIS) DP Fan Control P.36 P.23 CRT MUX HDMI Rediver HDMI 1.4 Conn P.28 SIM Card DP MUX Free Fall Sensor P.31 LVDS DisplayPort E HDMI to LVDS SW STDP6038 P.25 1 D Tuesday, November 30, 2010 Sheet E 2 of 63 A Board ID Table for AD channel Vcc Ra Board ID 0 1 2 3 4 5 6 7 3.3V +/100K +/Rb 0 8.2K +/18K +/33K +/56K +/100K +/200K +/NC 5% 5% USB PORT# BOARD ID Table V AD_BID min 0 V 0.168 V 0.375 V 0.634 V 0.958 V 1.372 V 1.851 V 2.433 V 5% 5% 5% 5% 5% 5% V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max 0.155 V 0.362 V 0.621 V 0.945 V 1.359 V 1.838 V 2.420 V 3.300 V EC AD3 0x00-0x0C 0x0D-0x1C 0x1D-0x30 0x31-0x49 0x4A-0x69 0x6A-0x8E 0x8F-0xBB 0xBC-0xFF Board ID 0 1 2 3 4 5 6 7 PCB Revision 0.1 0.2 0.3 0.4 1.0 USB SMBUS Control Table SOURCE EC_SMB_CK1 EC_SMB_DA1 KB930 EC_SMB_CK2 EC_SMB_DA2 KB930 PCH_SMBCLK PCH_SMBDATA PCH MEM_SMBCLK MEM_SMBDATA PCH MIINI1 BATT MINI2 EXPRESS CARD SODIMM MXM X X V X X X X X X X V X V X V V X X X X X X V X CLKOUT PCI0 DESTINATION PCH_LOOPBACK PCI1 EC PCI2 None PCI3 None PCI4 None DESTINATION 0 JUSB1 1 JUSB2 2 eDP CAMERA 3 LVDS CAMERA 4 JMINI1 (WLAN) 5 JMINI2 (DMC) 6 AlienFX/ELC 7 IR SENSOR 8 Bluetooth 9 JESATA 10 None 11 None 12 None 13 None 1 1 DIFFERENTIAL CLK DESTINATION FLEX CLOCKS DESTINATION SATA DESTINATION PCI EXPRESS DESTINATION CLKOUT_PCIE0 None CLKOUTFLEX0 None SATA0 HDD1 Lane 1 10/100/1G LAN CLKOUT_PCIE1 10/100/1G LAN CLKOUTFLEX1 CLK_14M SATA1 HDD2 Lane 2 MINI CARD-2 DMC CLKOUT_PCIE2 MINI CARD-2 DMC CLKOUTFLEX2 None SATA2 ODD Lane 3 MINI CARD-1 WLAN CLKOUT_PCIE3 MINI CARD-1 WLAN CLKOUTFLEX3 None SATA3 NA Lane 4 CARD READER CLKOUT_PCIE4 CARD READER CLKOUT_PCIE5 None CLKOUT_PCIE6 USB 3.0 CLKOUT_PCIE7 None CLKOUT_PEG_A MXM Symbol Note : SATA4 ESATA Lane 5 None SATA5 None Lane 6 USB 3.0 Lane 7 None Lane 8 None : means Digital Ground : means Analog Ground DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A Title Notes List Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 3 of 63 5 4 3 2 1 PEG_GTX_HRX_P[0..15] 14 PEG_GTX_HRX_N[0..15] 14 PEG_HTX_C_GRX_P[0..15] 14 PEG_HTX_C_GRX_N[0..15] 14 JCPU1A DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 B28 B26 A24 B23 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] 17 17 17 17 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 G21 E22 F21 D21 17 17 17 17 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 G22 D22 F20 C21 17 17 17 17 17 17 17 17 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 A21 H19 E19 F18 B21 C20 D18 E17 17 17 17 17 17 17 17 17 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 A22 G19 E20 G18 B20 C19 D19 F17 FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI_FSYNC0 FDI_FSYNC1 J18 J17 FDI0_FSYNC FDI1_FSYNC FDI_INT H20 FDI_LSYNC0 FDI_LSYNC1 J19 H17 FDI0_LSYNC FDI1_LSYNC EDP_COM EDP_HPD#_Q A18 A17 B16 eDP_COMPIO eDP_ICOMPO eDP_HPD EDP_AUXP EDP_AUXN C15 D15 EDP_TX0P EDP_TX1P EDP_TX2P EDP_TX3P C17 F16 C16 G15 EDP_TX0N EDP_TX1N EDP_TX2N EDP_TX3N C18 E16 D16 F15 17 FDI_FSYNC0 17 FDI_FSYNC1 17 FDI_INT 17 FDI_LSYNC0 17 FDI_LSYNC1 23 23 B EDP_AUXP EDP_AUXN 23 23 23 23 EDP_TX0P EDP_TX1P EDP_TX2P EDP_TX3P 23 23 23 23 EDP_TX0N EDP_TX1N EDP_TX2N EDP_TX3N DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI_INT eDP_AUX eDP_AUX# eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] PCI EXPRESS* - GRAPHICS 17 17 17 17 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 JCPU1I PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO Intel(R) FDI C 17 17 17 17 B27 B25 A25 B24 eDP D DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 J22 J21 H22 PEG_COMP PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 PEG_GTX_C_HRX_N0 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_N15 CC1 CC2 CC3 CC4 CC5 CC13 CC6 CC7 CC8 CC9 CC10 CC11 CC12 CC14 CC15 CC16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D PEG_GTX_HRX_N0 PEG_GTX_HRX_N1 PEG_GTX_HRX_N2 PEG_GTX_HRX_N3 PEG_GTX_HRX_N4 PEG_GTX_HRX_N5 PEG_GTX_HRX_N6 PEG_GTX_HRX_N7 PEG_GTX_HRX_N8 PEG_GTX_HRX_N9 PEG_GTX_HRX_N10 PEG_GTX_HRX_N11 PEG_GTX_HRX_N12 PEG_GTX_HRX_N13 PEG_GTX_HRX_N14 PEG_GTX_HRX_N15 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 PEG_GTX_C_HRX_P0 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_P15 CC17 CC18 CC19 CC20 CC21 CC22 CC23 CC24 CC25 CC26 CC27 CC28 CC29 CC30 CC31 CC32 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D PEG_GTX_HRX_P0 PEG_GTX_HRX_P1 PEG_GTX_HRX_P2 PEG_GTX_HRX_P3 PEG_GTX_HRX_P4 PEG_GTX_HRX_P5 PEG_GTX_HRX_P6 PEG_GTX_HRX_P7 PEG_GTX_HRX_P8 PEG_GTX_HRX_P9 PEG_GTX_HRX_P10 PEG_GTX_HRX_P11 PEG_GTX_HRX_P12 PEG_GTX_HRX_P13 PEG_GTX_HRX_P14 PEG_GTX_HRX_P15 M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 PEG_HTX_GRX_N0 PEG_HTX_GRX_N1 PEG_HTX_GRX_N2 PEG_HTX_GRX_N3 PEG_HTX_GRX_N4 PEG_HTX_GRX_N5 PEG_HTX_GRX_N6 PEG_HTX_GRX_N7 PEG_HTX_GRX_N8 PEG_HTX_GRX_N9 PEG_HTX_GRX_N10 PEG_HTX_GRX_N11 PEG_HTX_GRX_N12 PEG_HTX_GRX_N13 PEG_HTX_GRX_N14 PEG_HTX_GRX_N15 CC33 CC34 CC35 CC36 CC37 CC38 CC39 CC40 CC41 CC42 CC43 CC44 CC45 CC46 CC47 CC48 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N15 M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25 PEG_HTX_GRX_P0 PEG_HTX_GRX_P1 PEG_HTX_GRX_P2 PEG_HTX_GRX_P3 PEG_HTX_GRX_P4 PEG_HTX_GRX_P5 PEG_HTX_GRX_P6 PEG_HTX_GRX_P7 PEG_HTX_GRX_P8 PEG_HTX_GRX_P9 PEG_HTX_GRX_P10 PEG_HTX_GRX_P11 PEG_HTX_GRX_P12 PEG_HTX_GRX_P13 PEG_HTX_GRX_P14 PEG_HTX_GRX_P15 CC49 CC50 CC51 CC52 CC53 CC54 CC55 CC56 CC57 CC58 CC59 CC60 CC61 CC62 CC63 CC64 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P15 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 Near MXM Connector Sandy Bridge_rPGA_Rev1p0 CONN@ HPD Inversion for eDP VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 D C B +VCCP +VCCP 1 1 RC35 1 RC36 PEG_COMP 2 24.9_0402_1%~D EDP_COM 2 24.9_0402_1%~D Sandy Bridge_rPGA_Rev1p0 CONN@ R1472 1K_0402_5%~D 2 PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with - max length = 500 mils - typical impedance = 14.5 mohms EDP_HPD# 1 23 D 3 EDP_HPD#_Q S EDP_HPD# 2 G Q9 BSS138_SOT23~D A A Note: Place pull up resistor within 2 inches of CPU DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Compal Electronics, Inc. Title PROCESSOR(1/6) DMI,FDI,PEG Size 4 3 2 Rev 1.0 LA-6601P Date: 5 Document Number Tuesday, November 30, 2010 Sheet 1 4 of 63 5 4 3 2 1 +VCCP 17,44 PCH_PWROK SYS_PWROK_XDP 1K_0402_5%~D 17,44 SYSTEM_PWROK +3VALW XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7 @RC22 @ RC22 1K_0402_5%~D H_CPUPWRGD 1 H_CPUPWRGD_XDP 2 CFD_PWRBTN#_XDP @ 0_0402_5%~D 1 2 RC23 CFG0 XDP_HOOK2 1 RC24 2 SYS_PWROK_XDP 1K_0402_5%~D 1 2 @ RC26 0_0402_5%~D 17,44 PBTN_OUT# CFG0 VGATE 10,11,12,13,16,37,38 10,11,12,13,16,37,38 PCH_SMBDATA PCH_SMBCLK 15 PCH_JTAG_TCK 1 2 @ RC30 0_0402_5%~D XDP_TCK1 XDP_TCK_R 7 7 CFG0_R CFG1_R @ RC7 @ RC9 1 1 2 0_0402_5%~D 2 0_0402_5%~D CFG0 CFG1 7 7 CFG2_R CFG3_R @ RC10 1 @ RC12 1 2 0_0402_5%~D 2 0_0402_5%~D CFG2 CFG3 7 7 CFG8_R CFG9_R @ RC14 1 @ RC16 1 2 0_0402_5%~D 2 0_0402_5%~D CFG8 CFG9 7 7 CFG4_R CFG5_R @ RC17 1 @ RC18 1 2 0_0402_5%~D 2 0_0402_5%~D CFG4 CFG5 7 7 CFG6_R CFG7_R @ RC20 1 @ RC21 1 2 0_0402_5%~D 2 0_0402_5%~D CFG6 CFG7 7 7 CLK_CPU_ITP CLK_CPU_ITP# RC4 200_0402_1% 1 XDP_TDO @ RC28 1 XDP_TRST#_R XDP_TDI @ RC31 1 XDP_TMS_R @ RC29 1 B 2 17 PM_DRAM_PWRGD A UC5 MC74VHC1G09DFT2G_SC70-5 Y D RC8 200_0402_1% VDDPWRGOOD 4 PLT_RST# 2 0_0402_5%~D PCH_JTAG_TDO 15 2 0_0402_5%~D 2 0_0402_5%~D PCH_JTAG_TDI 15 PCH_JTAG_TMS 15 D S QC1 SSM3K7002FU_SC70-3~D 2 G 9,47 RUN_ON_CPU1.5VS3# +VCCP +3VS SAMTE_BSH-030-01-L-D-A The resistor for HOOK2 should be placed such that the stub is very small on CFG0 net RC12 CRB 1.1K CHECK LIST 0.7 --> 4.75K INTEL recommand 1.1K PDG 0.71 rev -->200 RC19 39_0402_1% CLK_CPU_ITP 16 CLK_CPU_ITP# 16 XDP_RST#_R 2 RC25 1 @ XDP_DBRESET# 1K_0402_5%~D 2 @ RC6 10K_0402_5%~D 1 CFG16 CFG17 2 2 0_0402_5%~D 2 0_0402_5%~D 5 1 1 G VCC CFG16_R @ RC3 CFG17_R @ RC5 +1.5V_CPU_VDDQ 2 1 1 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 1 RC13 CFG10_R 1 RC15 CFG11_R @ 0_0402_5%~D 2 @ 0_0402_5%~D 2 CFG10 CFG11 GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 3 XDP_BPM#2 XDP_BPM#3 GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 2 XDP_BPM#0 XDP_BPM#1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 CC65 0.1U_0402_16V4Z~D +3VS @JXDP1 @ JXDP1 XDP_PREQ# XDP_PRDY# CC68 1 2 C RC32 75_0402_5% 0.1U_0402_16V4Z~D 2 NC 3 PAD~D 19,44 B 44,49 H_PROCHOT# T1 @ H_CATERR# H_PECI H_PECI AL33 AN33 2 H_PROCHOT#_R AL32 56_0402_5% 1 RC41 H_THERMTRIP# AN32 19 H_THRMTRIP# CLOCKS SKTOCC# BCLK BCLK# DPLL_REF_CLK DPLL_REF_CLK# A28 A27 CLK_CPU_DMI_R CLK_CPU_DMI#_R RC37 RC38 1 1 2 33_0402_5%~D 2 33_0402_5%~D CLK_CPU_DMI 16 CLK_CPU_DMI# 16 A16 A15 CLK_CPU_DPLL_R CLK_CPU_DPLL#_R RC39 RC40 1 1 2 0_0402_5%~D 2 0_0402_5%~D CLK_CPU_DPLL 16 CLK_CPU_DPLL# 16 CATERR# PECI PROCHOT# BUFO_CPU_RST# SM_DRAMRST# R8 H_DRAMRST# XDP_DBRESET# AK1 A5 A4 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 AP29 AP27 XDP_PRDY#_R XDP_PREQ#_R RC121 RC125 1 1 @ @ 2 0_0402_5%~D XDP_PRDY# 2 0_0402_5%~D XDP_PREQ# AR26 AR27 AP30 XDP_TCK XDP_TMS XDP_TRST# RC126 RC127 RC128 1 1 1 @ @ @ 2 0_0402_5%~D XDP_TCK_R 2 0_0402_5%~D XDP_TMS_R 2 0_0402_5%~D XDP_TRST#_R AR28 AP26 XDP_TDI_R XDP_TDO_R RC50 RC51 1 1 @ @ 2 0_0402_5%~D 2 0_0402_5%~D H_DRAMRST# 6 1K_0402_5%~D 1 2 RC42 H_CPUPWRGD_R10K_0402_5%~D 1 2 RC44 BUF_CPU_RST# 2 43_0402_1% 1 RC33 UC2 SN74LVC1G07DCKR_SC70-5~D +3VS DDR3 MISC AN34 PROC_SELECT# MISC C26 THERMAL H_SNB_IVB# 19 H_SNB_IVB# 4 Y A G 1 18,33,35,38,39,44 PLT_RST# JCPU1B P 5 2 C 2 0_0402_5%~D +VCCP Place near JXDP1 7 56 2 0_0402_5%~D +3V_PCH D 7 7 1 @ RC74 1 1 +VCCP RC113 3 2 1 1 @ RC27 2 2 +3VALW @ @ 1 CC66 0.1U_0402_16V4Z~D 2 CC67 0.1U_0402_16V4Z~D 1 Processor Pullups H_PROCHOT# 62_0402_5% 1 SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] 2 +VCCP RC43 B THERMTRIP# PU/PD for JTAG signals H_PM_SYNC 19 H_CPUPWRGD 1 2 RC49 1 2 RC53 VDDPWRGOOD 1 RC57 2 H_PM_SYNC_R 0_0402_5%~D AM34 H_CPUPWRGD_R 0_0402_5%~D AP33 VDDPWRGOOD_R 130_0402_1%~D V8 BUF_CPU_RST# AR33 PM_SYNC UNCOREPWRGOOD SM_DRAMPWROK RESET# JTAG & BPM 17 PWR MANAGEMENT PRDY# PREQ# TCK TMS TRST# TDI TDO DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] AL35 XDP_DBRESET#_R RC56 AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R XDP_BPM#4_R XDP_BPM#5_R XDP_BPM#6_R XDP_BPM#7_R RC59 RC61 RC62 RC63 RC64 RC65 RC66 RC67 2 0_0402_5%~D 1 1 1 1 1 1 1 1 1 @ @ @ @ @ @ @ @ 2 2 2 2 2 2 2 2 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D XDP_TDI XDP_TDO +VCCP DDR3 Compensation Signals SM_RCOMP0 140_0402_1% 1 2 RC55 XDP_TMS 51_0402_5% 1 2 RC45 SM_RCOMP1 25.5_0402_1%~D 1 2 RC58 XDP_TDI_R 51_0402_5% 1 2 RC46 SM_RCOMP2 200_0402_1% 2 RC60 XDP_PREQ#_R 51_0402_5% 1 2 RC47 @ XDP_TDO_R 51_0402_5% 1 2 RC48 XDP_TCK 51_0402_5% 1 2 RC52 XDP_TRST# 51_0402_5% 1 2 RC54 1 XDP_DBRESET# 17 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7 A A DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Compal Electronics, Inc. Title PROCESSOR(2/6) PM,XDP,CLK Size 4 3 2 Rev 1.0 LA-6601P Date: 5 Document Number Tuesday, November 30, 2010 Sheet 1 5 of 63 5 4 3 2 1 Need to confired when Intel spec release. JCPU1C JCPU1D C B C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 AE10 AF10 V6 10,12 DDR_A_BS0 10,12 DDR_A_BS1 10,12 DDR_A_BS2 AE8 AD9 AF9 10,12 DDR_A_CAS# 10,12 DDR_A_RAS# 10,12 DDR_A_WE# SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_RAS# SA_WE# SA_CLK[0] SA_CLK#[0] SA_CKE[0] AB6 AA6 V9 M_CLK_DDR0 M_CLK_DDR#0 DDR_CKE0_DIMMA M_CLK_DDR0 12 M_CLK_DDR#0 12 DDR_CKE0_DIMMA AA5 AB5 V10 M_CLK_DDR1 M_CLK_DDR#1 DDR_CKE1_DIMMA M_CLK_DDR1 12 M_CLK_DDR#1 12 DDR_CKE1_DIMMA RSVD_TP[1] RSVD_TP[2] RSVD_TP[3] AB4 AA4 W9 M_CLK_DDR4 M_CLK_DDR#4 DDR_CKE4_DIMMC M_CLK_DDR4 10 M_CLK_DDR#4 10 DDR_CKE4_DIMMC AB3 AA3 W10 M_CLK_DDR5 M_CLK_DDR#5 DDR_CKE5_DIMMC M_CLK_DDR5 10 M_CLK_DDR#5 10 DDR_CKE5_DIMMC 10 SA_CS#[0] SA_CS#[1] RSVD_TP[7] RSVD_TP[8] AK3 AL3 AG1 AH1 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS4_DIMMC# DDR_CS5_DIMMC# DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS4_DIMMC# DDR_CS5_DIMMC# 12 12 10 10 SA_ODT[0] SA_ODT[1] RSVD_TP[9] RSVD_TP[10] AH3 AG3 AG2 AH2 M_ODT0 M_ODT1 M_ODT4 M_ODT5 C4 G6 J3 M6 AL6 AM8 AR12 AM15 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 D4 F6 K3 N6 AL5 AM9 AR11 AM14 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] M_ODT0 M_ODT1 M_ODT4 M_ODT5 11,13 DDR_B_D[0..63] 12 SA_CLK[1] SA_CLK#[1] SA_CKE[1] RSVD_TP[4] RSVD_TP[5] RSVD_TP[6] DDR SYSTEM MEMORY A DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 12 10 12 12 10 10 DDR_A_DQS#[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..15] 10,12 10,12 10,12 C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 AA9 AA7 R6 11,13 DDR_B_BS0 11,13 DDR_B_BS1 11,13 DDR_B_BS2 11,13 DDR_B_CAS# 11,13 DDR_B_RAS# 11,13 DDR_B_WE# D S 1 M_CLK_DDR2 M_CLK_DDR#2 DDR_CKE2_DIMMB M_CLK_DDR2 13 M_CLK_DDR#2 13 DDR_CKE2_DIMMB 13 SB_CLK[1] SB_CLK#[1] SB_CKE[1] AE1 AD1 R10 M_CLK_DDR3 M_CLK_DDR#3 DDR_CKE3_DIMMB M_CLK_DDR3 13 M_CLK_DDR#3 13 DDR_CKE3_DIMMB 13 RSVD_TP[11] RSVD_TP[12] RSVD_TP[13] AB2 AA2 T9 M_CLK_DDR6 M_CLK_DDR#6 DDR_CKE6_DIMMD M_CLK_DDR6 11 M_CLK_DDR#6 11 DDR_CKE6_DIMMD 11 AA1 AB1 T10 M_CLK_DDR7 M_CLK_DDR#7 DDR_CKE7_DIMMD M_CLK_DDR7 11 M_CLK_DDR#7 11 DDR_CKE7_DIMMD 11 AD3 AE3 AD6 AE6 DDR_CS2_DIMMB# DDR_CS3_DIMMB# DDR_CS6_DIMMD# DDR_CS7_DIMMD# DDR_CS2_DIMMB# DDR_CS3_DIMMB# DDR_CS6_DIMMD# DDR_CS7_DIMMD# 13 13 11 11 AE4 AD4 AD5 AE5 M_ODT2 M_ODT3 M_ODT6 M_ODT7 SB_CS#[0] SB_CS#[1] RSVD_TP[17] RSVD_TP[18] SB_ODT[0] SB_ODT[1] RSVD_TP[19] RSVD_TP[20] 13 13 11 11 C SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] SB_CAS# SB_RAS# SB_WE# M_ODT2 M_ODT3 M_ODT6 M_ODT7 D D7 F3 K6 N3 AN5 AP9 AK12 AP15 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 C7 G3 J6 M3 AN6 AP8 AK11 AP14 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_DQS#[0..7] 11,13 DDR_B_DQS[0..7] 11,13 DDR_B_MA[0..15] 11,13 B 2 1 RC75 1K_0402_5%~D QC2 BSS138_SOT23~D 3 AE2 AD2 R9 Sandy Bridge_rPGA_Rev1p0 CONN@ +1.5V 5 H_DRAMRST# SB_CLK[0] SB_CLK#[0] SB_CKE[0] RSVD_TP[14] RSVD_TP[15] RSVD_TP[16] SB_BS[0] SB_BS[1] SB_BS[2] AA10 AB8 AB9 Sandy Bridge_rPGA_Rev1p0 CONN@ H_DRAMRST# SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] DDR SYSTEM MEMORY B 10,12 DDR_A_D[0..63] D DDR3_DRAMRST#_R DG 0.7 RC76 1 Figure 57 2 1K_0402_5%~D DDR3_DRAMRST# 10,11,12,13 RC124=1K 2 1 G 2 RC77 4.99K_0402_1%~D A DRAMRST_CNTRL 1 2 CC69 0.047U_0402_16V4Z~D 0_0402_5%~D 2 1 RC72 DRAMRST_CNTRL_PCH 0_0402_5%~D 2 1 RC73 @ DRAMRST_CNTRL_EC 16 A 44 DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Compal Electronics, Inc. Title PROCESSOR(3/6) DDRIII Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 6 of 63 5 4 3 2 1 CFG Straps for Processor CFG2 1 1 @ RC91 2 VSS_VAL_SENSE 49.9_0402_1% 5 5 CFG16 CFG17 VCC_AXG_VAL_SENSE VSS_AXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE C PAD~D +V_DDR_REFA T19 @ AJ31 AH31 AJ33 AH33 VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE AJ26 RSVD5 +V_DDR_REFB 2 0_0402_5%~D 2 0_0402_5%~D +V_DDR_REFA_R +V_DDR_REFB_R RC85 1K_0402_1%~D 1 RC88 2 @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 PAD~D T44 @ PAD~D T45 @ H_VCCP_SEL 0_0402_5%~D J20 B18 A19 PAD~D T25 T26 T27 T28 T30 T32 T33 T34 T35 T37 T38 T39 T40 T41 T42 T43 T49 @ J15 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 VCCIO_SEL PEG Static Lane Reversal - CFG2 is for the 16x 1:(Default) Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed CFG2 T8 J16 H16 G16 @ T10 @T10 @T11 @ T11 @T12 @ T12 @T13 @ T13 PAD~D PAD~D PAD~D PAD~D AR35 AT34 AT33 AP35 AR34 @ T14 @T14 @T15 @ T15 @T16 @ T16 @T17 @ T17 @T18 @ T18 PAD~D PAD~D PAD~D PAD~D PAD~D CFG4 C Display Port Presence Strap RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 VCC_DIE_SENSE RSVD54 RSVD55 RSVD56 RSVD57 RSVD58 B34 A33 A34 B35 C35 @ T20 @T20 @T21 @ T21 @T22 @ T22 @T23 @ T23 @T24 @ T24 PAD~D PAD~D PAD~D PAD~D PAD~D AJ32 AK32 @ T29 @T29 @T31 @ T31 PAD~D PAD~D AH27 @T36 @ T36 PAD~D AN35 AM35 AT2 AT1 AR1 1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port CFG4 CFG6 CFG5 CLK_RES_ITP 16 CLK_RES_ITP# 16 @ T46 @T46 @T47 @ T47 @T48 @ T48 PAD~D PAD~D PAD~D @ RC86 1K_0402_1%~D INTEL 12/28 recommand to add 1k pull down B RSVD6 RSVD7 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 PAD~D PAD~D PAD~D 1K_0402_1%~D @ RC87 PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D 2 2 RC84 1K_0402_1%~D 52 VCCP_PWRCTRL B4 D1 1 1 1 1 @ RC82 @ RC83 RSVD37 RSVD38 RSVD39 RSVD40 @ T7 @T7 @T8 @ T8 @T9 @ T9 1 VSS_AXG_VAL_SENSE 49.9_0402_1% AT26 AM33 AJ27 2 2 PAD~D PAD~D PAD~D PAD~D PAD~D 1 1 @ RC90 @ T2 @T2 @T3 @ T3 @T4 @ T4 @T5 @ T5 @T6 @ T6 1 1 VCC_VAL_SENSE 49.9_0402_1% RSVD33 RSVD34 RSVD35 L7 AG7 AE7 AK2 W8 RC81 1K_0402_1%~D 2 @ RC80 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] 2 1 VCC_AXG_VAL_SENSE 49.9_0402_1% 2 @ RC79 +VCC_CORE AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 2 +VCC_GFXCORE_AXG CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 T51 T52 T53 T54 RESERVED 5 5 5 5 5 5 5 5 5 5 5 5 @PAD~D @PAD~D @PAD~D @PAD~D 2 JCPU1E D @RC78 @ RC78 1K_0402_1%~D D PCIE Port Bifurcation Straps 11: (Default) x16 - Device 1 functions 1 and 2 disabled RSVD27 B 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled KEY B1 @T50 @ T50 PAD~D CFG[6:5] 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled Sandy Bridge_rPGA_Rev1p0 CONN@ 2 @RC89 @ RC89 1K_0402_1%~D 1 CFG7 PEG DEFER TRAINING CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title PROCESSOR(4/6) RSVD,CFG Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 7 of 63 5 4 3 JCPU1F 2 1 POWER +VCC_CORE 2 @ C J23 SVID VIDALERT# VIDSCLK VIDSOUT AJ29 AJ30 AJ28 H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT RC94 RC92 RC96 1 2 2 1 +VCCP Note: Place the PU resistors close to CPU 300 - 1500mils 2 43_0402_1% 2 0_0402_5%~D 2 0_0402_5%~D 1 1 1 VR_SVID_ALRT# 56 VR_SVID_CLK 56 VR_SVID_DAT 56 B 1 +VCC_CORE AJ35 VCCSENSE_R RC98 AJ34 VSSSENSE_R RC99 1 1 2 0_0402_5%~D 2 0_0402_5%~D VCCSENSE VSSSENSE 56 56 1 VCC_SENSE VSS_SENSE 2 RC97 100_0402_1%~D VCCIO_SENSE VSSIO_SENSE B10 A10 RC100 100_0402_1%~D VCCIO_SENSE 52 VSSIO_SENSE 52 2 SENSE LINES @ @ @ @ 1 2 CC95 22U_0805_6.3VAM~D 2 2 1 CC109 22U_0805_6.3VAM~D 1 1 CC94 22U_0805_6.3VAM~D 2 2 CC108 22U_0805_6.3VAM~D 1 1 CC93 22U_0805_6.3VAM~D 2 2 CC107 22U_0805_6.3VAM~D 1 1 CC92 22U_0805_6.3VAM~D 2 2 CC106 22U_0805_6.3VAM~D 1 1 CC81 22U_0805_6.3VAM~D 2 CC105 22U_0805_6.3VAM~D 2 1 CC80 22U_0805_6.3VAM~D 1 CC104 22U_0805_6.3VAM~D 2 2 CC79 22U_0805_6.3VAM~D 2 2 1 1 RC95 130_0402_1%~D + 2 1 CC103 22U_0805_6.3VAM~D 2 1 + 2 2 1 2 CC78 22U_0805_6.3VAM~D + 2 1 2 1 RC93 75_0402_1%~D 2 1 + 2 1 CC102 22U_0805_6.3VAM~D + 2 1 1 2 1 CC112 330U_D2_2VM_R6M~D 2 1 VCCIO40 + 2 CC111 330U_D2_2VM_R6M~D + CC135 470U_D2_2VM_R4.5M~D 2 1 CC134 470U_D2_2VM_R4.5M~D + CC137 470U_D2_2VM_R4.5M~D 2 1 CC133 470U_D2_2VM_R4.5M~D + CC136 470U_D2_2VM_R4.5M~D 1 CC132 470U_D2_2VM_R4.5M~D B 2 1 CC110 330U_D2_2VM_R6M~D +VCC_CORE 2 1 CC115 22U_0805_6.3VAM~D 2 1 CC114 22U_0805_6.3VAM~D 2 1 CC113 22U_0805_6.3VAM~D 2 1 CC128 22U_0805_6.3VAM~D 2 1 CC127 22U_0805_6.3VAM~D 2 1 CC126 22U_0805_6.3VAM~D 2 1 CC125 22U_0805_6.3VAM~D 2 1 CC124 22U_0805_6.3VAM~D 2 1 CC123 22U_0805_6.3VAM~D 2 1 CC122 22U_0805_6.3VAM~D 1 2 CC121 22U_0805_6.3VAM~D 2 2 1 CC131 22U_0805_6.3VAM~D 1 1 CC120 22U_0805_6.3VAM~D 2 2 CC130 22U_0805_6.3VAM~D 1 CC129 22U_0805_6.3VAM~D 2 CC116 22U_0805_6.3VAM~D 1 2 1 CC119 22U_0805_6.3VAM~D 2 1 CC118 22U_0805_6.3VAM~D 1 CC117 22U_0805_6.3VAM~D C 2 1 1 CC88 22U_0805_6.3VAM~D +VCC_CORE VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 1 2 CC101 22U_0805_6.3VAM~D 2 1 CC77 22U_0805_6.3VAM~D 1 2 CC100 22U_0805_6.3VAM~D 2 1 CC76 22U_0805_6.3VAM~D 1 2 CC99 22U_0805_6.3VAM~D 2 2 1 CC75 22U_0805_6.3VAM~D 1 2 1 CC98 22U_0805_6.3VAM~D 2 2 1 CC74 22U_0805_6.3VAM~D 1 1 CC97 22U_0805_6.3VAM~D 2 D CC73 22U_0805_6.3VAM~D 1 AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 CC96 22U_0805_6.3VAM~D 2 CC84 10U_0805_4VAM~D 1 CC83 10U_0805_4VAM~D 2 CC71 10U_0805_4VAM~D 1 CC87 10U_0805_4VAM~D 2 CC91 10U_0805_4VAM~D 1 CC86 10U_0805_4VAM~D 2 CC70 10U_0805_4VAM~D 1 CC85 10U_0805_4VAM~D 2 CC90 10U_0805_4VAM~D 1 CC89 10U_0805_4VAM~D 2 CC82 10U_0805_4VAM~D 1 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 8.5A CC72 22U_0805_6.3VAM~D +VCC_CORE AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 CORE SUPPLY D VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 PEG AND DDR +VCCP 94AAG35 A A Sandy Bridge_rPGA_Rev1p0 CONN@ DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title PROCESSOR(5/6) PWR,BYPASS Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 8 of 63 5 4 3 2 1 +1.5V_CPU_VDDQ Source 1 4 2 1 1 2 1 5,47 1 3 1 4 RUN_ON_CPU1.5VS3# 2 0_0402_5%~D 1 +V_SM_VREF_CNT +V_SM_VREF 2 2 D @RC106 @ RC106 RC116 100_0402_1%~D CC178 @ 0.1U_0402_10V7K~D S 2 3 1 +1.5V QC4 NTR4503NT1G_SOT23-3~D 2 RC108 100K_0402_5%~D 2 1 2 6 1 2 0_0402_5%~D 2 RC112 100_0402_1%~D 1 S 1 CC139 0.1U_0603_25V7K~D RC107 D 2 G RC105 330K_0402_1% 2 0_0402_5%~D QC5A 1 DMN66D0LDW-7_SOT363-6~D 44 CPU1.5V_S3_GATE @RC104 @ RC104 D 5 G QC5B DMN66D0LDW-7_SOT363-6~D RUN_ON_CPU1.5VS3# RC103 20K_0402_5%~D 2 RUN_ON_CPU1.5VS3 D 20,44,47,52,53,54 SUSP# 1 CC138 10U_0805_10V4Z~D RC101 100K_0402_5%~D RC102 100K_0402_5%~D +1.5V_CPU_VDDQ 1 2 3 1 QC3 AO4728L_SO8~D 8 7 6 5 2 +1.5V B+_BIAS +3VALW RUN_ON_CPU1.5VS3 1 0.1U_0402_10V7K~D CC181 2 1 0.1U_0402_10V7K~D CC182 2 1 0.1U_0402_10V7K~D 2 1 2 + 2 2 +1.5V PAD-OPEN 4x4m PJP30 OPEN +VCCSA VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 VCCSA_SENSE M27 M26 L26 J26 J25 J24 H26 H25 6A 1 2 1 2 1 2 1 2 1 + 2 RC120 2 0_0402_5%~D 1 H23 C22 C24 VCCSA_SENSE 55 H_FC_C22 VCCSA_SEL 55 SENSE LINES 2 FC_C22 VCCSA_VID1 VSS_AXG_SENSE 56 1 Sandy Bridge_rPGA_Rev1p0 CONN@ RC110 0_0402_5%~D MISC 1 0.1U_0402_10V7K~D 2 CC171 330U_D2_2VM_R6M~D 1.8V RAIL 2 1 1 @ 2 1 1 CC166 330U_D2_2VM_R6M~D 2 1 CC165 10U_0805_4VAM~D 2 1 CC164 10U_0805_4VAM~D 1 RC111 10K_0402_5%~D 2 VCCPLL1 VCCPLL2 VCCPLL3 2 CC177 1 CC163 10U_0805_4VAM~D + B6 A6 A2 5A CC170 10U_0603_6.3V6M~D 2 1 CC176 330U_D2_2.5VM_R6M~D 2 1 CC175 1U_0402_6.3V6K~D 1 CC174 1U_0402_6.3V6K~D 2 CC172 10U_0805_4VAM~D 1 3A +1.8VS_VCCPLL 2 0_0805_5% VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 CC173 @J8 @ J8 CC169 10U_0805_4VAM~D 1 +1.5V_CPU_VDDQ CC162 10U_0805_4VAM~D RC109 +V_SM_VREF should have 10 mil trace width CC168 10U_0805_4VAM~D +1.8VS AL1 CC167 10U_0805_4VAM~D B +V_SM_VREF_CNT SM_VREF @ 2 @ 1 VCC_AXG_SENSE 56 VSS_AXG_SENSE 56 55 2 2 @ @ @ 1 VCC_AXG_SENSE VSS_AXG_SENSE AK35 AK34 CC161 10U_0805_4VAM~D @ 2 VAXG_SENSE VSSAXG_SENSE CC160 10U_0805_4VAM~D 2 1 CC155 22U_0805_6.3VAM~D + 2 CC154 22U_0805_6.3VAM~D 2 1 1 CC153 22U_0805_6.3VAM~D + 2 CC159 470U_D2_2VM_R4.5M~D 1 1 CC152 22U_0805_6.3VAM~D 2 2 CC151 22U_0805_6.3VAM~D + 1 CC158 470U_D2_2VM_R4.5M~D 1 CC157 470U_D2_2VM_R4.5M~D 2 2 CC150 22U_0805_6.3VAM~D + CC156 470U_D2_2VM_R4.5M~D 1 1 CC149 22U_0805_6.3VAM~D 2 CC148 22U_0805_6.3VAM~D 1 JCPU1H @ C VREF 2 VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 DDR3 -1.5V RAILS 2 1 CC147 22U_0805_6.3VAM~D 2 1 CC146 22U_0805_6.3VAM~D 2 1 CC145 22U_0805_6.3VAM~D 2 1 CC144 22U_0805_6.3VAM~D 2 1 CC143 22U_0805_6.3VAM~D 2 1 CC142 22U_0805_6.3VAM~D 1 CC141 22U_0805_6.3VAM~D 2 CC140 22U_0805_6.3VAM~D 1 AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 SA RAIL JCPU1G 33A GRAPHICS +VCC_GFXCORE_AXG POWER AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2 C B Sandy Bridge_rPGA_Rev1p0 CONN@ A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title PROCESSOR(6/6) PWR,VSS Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 9 of 63 5 4 3 2 1 +1.5V RD2 +V_DDR_REFA 1 2 0_0402_5%~D 1 +1.5V 1 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 D DDR_A_D10 DDR_A_D11 Layout Note: Place near JDIMM1 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 +1.5V 2 1 2 DDR_A_D24 DDR_A_D25 CD6 1U_0402_6.3V6K~D 2 1 CD5 1U_0402_6.3V6K~D 1 CD4 1U_0402_6.3V6K~D CD3 1U_0402_6.3V6K~D 2 DDR_A_D18 DDR_A_D19 DDR_A_D26 DDR_A_D27 DDR_CKE4_DIMMC 6 DDR_CKE4_DIMMC DDR_A_BS2 6,12 DDR_A_BS2 +1.5V DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 2 + 2 @ CD14 330U_SX_2VY~D 2 1 CD13 10U_0603_6.3V6M~D 2 1 CD12 10U_0603_6.3V6M~D 2 1 CD11 10U_0603_6.3V6M~D 2 1 CD10 10U_0603_6.3V6M~D 2 1 CD9 10U_0603_6.3V6M~D 1 CD8 10U_0603_6.3V6M~D 2 CD7 10U_0603_6.3V6M~D 1 C 1 DDR_A_MA3 DDR_A_MA1 6 6 M_CLK_DDR4 M_CLK_DDR#4 M_CLK_DDR4 M_CLK_DDR#4 DDR_A_MA10 DDR_A_BS0 6,12 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# 6,12 DDR_A_WE# 6,12 DDR_A_CAS# DDR_A_MA13 DDR_CS5_DIMMC# 6 DDR_CS5_DIMMC# DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 SA0 SA1 Layout Note: Place near JDIMM1.203,204 1 0 DIMM1 1 1 DIMM2 0 0 DIMM3 0 1 DIMM4 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 +3VS DDR_A_D50 DDR_A_D51 +0.75VS DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 1 1 @ RD36 10K_0402_5%~D 1 1 2 +0.75VS 1 2 CD22 2.2U_0603_6.3V6K~D RD7 10K_0402_5%~D CD21 0.1U_0402_16V4Z~D RD6 @ 10K_0402_5%~D 2 +3VS 1 2 RD35 10K_0402_5%~D 2 2 1 CD20 1U_0402_6.3V6K~D 2 1 CD19 1U_0402_6.3V6K~D 1 CD18 1U_0402_6.3V6K~D 2 CD17 1U_0402_6.3V6K~D 1 2 2 B 205 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT GND1 GND2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_A_D4 DDR_A_D5 DDR_A_DQS#0 DDR_A_DQS0 CPU 3 (H5.2) 4 (H9.2) DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 DDR3_DRAMRST# D DDR3_DRAMRST# 6,11,12,13 DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 DDR_CKE5_DIMMC DDR_CKE5_DIMMC 6 DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR5 M_CLK_DDR#5 DDR_A_BS1 DDR_A_RAS# DDR_CS4_DIMMC# M_ODT4 M_ODT5 M_CLK_DDR5 6 M_CLK_DDR#5 6 DDR_A_BS1 DDR_A_RAS# C +1.5V 6,12 6,12 DDR_CS4_DIMMC# 6 M_ODT4 6 M_ODT5 RD4 1K_0402_1%~D 6 +VREF_CA DDR_A_D36 DDR_A_D37 1 DDR_A_D38 DDR_A_D39 2 DDR_A_D44 DDR_A_D45 1 2 CD16 0.1U_0402_16V4Z~D DDR_A_DQS#4 DDR_A_DQS4 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS CD15 2.2U_0603_6.3V6K~D DDR_A_D32 DDR_A_D33 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS 1 2 DDR_A_D0 DDR_A_D1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 2 2 2 RD3 100_0402_1%~D 1 CD2 0.1U_0402_16V4Z~D All VREF traces should have 10 mil trace width CD1 2.2U_0603_6.3V6K~D 2 +V_DDR_REFA 1 1 2 (H8) JDIMM1 (H4) +1.5V JDIMM1 +DIMM0_VREF 1 RD1 100_0402_1%~D RD5 1K_0402_1%~D 2 6,12 DDR_A_DQS#[0..7] 6,12 DDR_A_DQS[0..7] 6,12 DDR_A_D[0..63] 6,12 DDR_A_MA[0..15] DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 B DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 M_THERMAL# PCH_SMBDATA PCH_SMBCLK M_THERMAL# 11,12,13,44 PCH_SMBDATA 5,11,12,13,16,37,38 PCH_SMBCLK 5,11,12,13,16,37,38 +0.75VS 206 TYCO_2-2013287-1 Link Done A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title DDRIII DIMMA Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 10 of 63 5 4 3 2 1 +1.5V 1 +V_DDR_REFB RD14 1 2 0_0402_5%~D +1.5V RD15 100_0402_1%~D 1 RD16 100_0402_1%~D 6,13 DDR_B_D[0..63] D 2 6,13 DDR_B_MA[0..15] 2 All VREF traces should have 10 mil trace width 1 2 DDR_B_D0 DDR_B_D1 CD26 0.1U_0402_16V4Z~D 6,13 DDR_B_DQS#[0..7] CD27 2.2U_0603_6.3V6K~D 2 +DIMM1_VREF +V_DDR_REFB 1 6,13 DDR_B_DQS[0..7] JDIMM2 (H8) 1 (H4) +1.5V JDIMM2 DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 Note: Check voltage tolerance of VREF_DQ at the DIMM socket DDR_B_D10 DDR_B_D11 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 Layout Note: Place near JDIMMB DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDR_B_D4 DDR_B_D5 CPU DDR_B_DQS#0 DDR_B_DQS0 3 (H5.2) 4 (H9.2) DDR_B_D6 DDR_B_D7 D DDR_B_D12 DDR_B_D13 DDR3_DRAMRST# DDR3_DRAMRST# 6,10,12,13 DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 +1.5V DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 C 6 6 +1.5V M_CLK_DDR6 M_CLK_DDR#6 M_CLK_DDR6 M_CLK_DDR#6 DDR_B_MA10 DDR_B_BS0 6,13 DDR_B_BS0 2 @ 1 + 2 DDR_B_WE# DDR_B_CAS# 6,13 DDR_B_WE# 6,13 DDR_B_CAS# 6 DDR_CS7_DIMMD# DDR_B_MA13 DDR_CS7_DIMMD# DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35 DDR_B_D40 DDR_B_D41 Layout Note: Place near JDIMMB.203,204 SA0 SA1 1 DIMM1 0 1 1 DIMM2 0 0 DIMM3 0 1 DIMM4 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 +0.75VS B +3VS 2 2 DDR_B_D56 DDR_B_D57 RD38 10K_0402_5%~D RD19 10K_0402_5%~D DDR_B_D58 DDR_B_D59 1 2 1 2 1 CD45 1U_0402_6.3V6K~D 2 1 CD44 1U_0402_6.3V6K~D 1 CD43 1U_0402_6.3V6K~D 2 CD42 1U_0402_6.3V6K~D 1 DDR_B_D50 DDR_B_D51 +0.75VS 1 1 +3VS 2 2 1 2 1 2 CD47 2.2U_0603_6.3V6K~D @ RD37 10K_0402_5%~D CD46 0.1U_0402_16V4Z~D @ RD20 10K_0402_5%~D 205 GND1 GND2 DDR_CKE7_DIMMD DDR_CKE7_DIMMD 6 DDR_B_MA15 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR7 M_CLK_DDR#7 DDR_B_BS1 DDR_B_RAS# DDR_CS6_DIMMD# M_ODT6 M_ODT7 C M_CLK_DDR7 6 M_CLK_DDR#7 6 +1.5V DDR_B_BS1 6,13 DDR_B_RAS# 6,13 DDR_CS6_DIMMD# 6 M_ODT6 6 M_ODT7 RD17 1K_0402_1%~D 6 +VREF_CB DDR_B_D36 DDR_B_D37 1 DDR_B_D38 DDR_B_D39 DDR_B_D44 DDR_B_D45 2 1 2 CD41 0.1U_0402_16V4Z~D DDR_B_D32 DDR_B_D33 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 CD40 2.2U_0603_6.3V6K~D CD39 330U_SX_2VY~D 2 1 CD38 10U_0603_6.3V6M~D 2 1 CD37 10U_0603_6.3V6M~D 2 1 CD36 10U_0603_6.3V6M~D 2 1 CD35 10U_0603_6.3V6M~D 2 1 CD34 10U_0603_6.3V6M~D 1 CD33 10U_0603_6.3V6M~D 2 CD32 10U_0603_6.3V6M~D 1 CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT 1 2 DDR_B_BS2 2 2 1 DDR_CKE6_DIMMD 1 2 1 CD31 1U_0402_6.3V6K~D 1 CD30 1U_0402_6.3V6K~D CD29 1U_0402_6.3V6K~D 2 CD28 1U_0402_6.3V6K~D 1 6,13 DDR_B_BS2 RD18 1K_0402_1%~D 2 6 DDR_CKE6_DIMMD DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 B DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 M_THERMAL# PCH_SMBDATA PCH_SMBCLK M_THERMAL# 10,12,13,44 PCH_SMBDATA 5,10,12,13,16,37,38 PCH_SMBCLK 5,10,12,13,16,37,38 +0.75VS 206 TYCO_2-2013298-1 Link Done A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title DDRIII DIMMB Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 11 of 63 5 4 3 RD28 +V_DDR_REFA 2 0_0402_5%~D 1 +1.5V 6,10 DDR_A_DQS#[0..7] 1 2 (H8) 1 (H4) +1.5V JDIMM3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 D DDR_A_D10 DDR_A_D11 Layout Note: Place near JDIMM1 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 +1.5V 2 1 2 DDR_A_D24 DDR_A_D25 CD56 1U_0402_6.3V6K~D 2 1 CD55 1U_0402_6.3V6K~D 1 CD54 1U_0402_6.3V6K~D 2 CD53 1U_0402_6.3V6K~D 1 DDR_A_D18 DDR_A_D19 DDR_A_D26 DDR_A_D27 6 DDR_CKE0_DIMMA DDR_CKE0_DIMMA DDR_A_BS2 6,10 DDR_A_BS2 +1.5V DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 2 + 2 @ CD64 330U_SX_2VY~D 2 1 CD63 10U_0603_6.3V6M~D 2 1 CD62 10U_0603_6.3V6M~D 2 1 CD61 10U_0603_6.3V6M~D 2 1 CD60 10U_0603_6.3V6M~D 2 1 CD59 10U_0603_6.3V6M~D 1 CD58 10U_0603_6.3V6M~D 2 CD57 10U_0603_6.3V6M~D 1 1 DDR_A_MA3 DDR_A_MA1 6 6 M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#0 DDR_A_MA10 DDR_A_BS0 6,10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# 6,10 DDR_A_WE# 6,10 DDR_A_CAS# 6 DDR_CS1_DIMMA# DDR_A_MA13 DDR_CS1_DIMMA# DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 SA0 SA1 +0.75VS DIMM1 1 DIMM2 0 0 DIMM3 0 1 DIMM4 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 +3VS DDR_A_D50 DDR_A_D51 B DDR_A_D56 DDR_A_D57 1 2 0 1 1 2 1 CD70 1U_0402_6.3V6K~D 2 1 CD69 1U_0402_6.3V6K~D 1 CD68 1U_0402_6.3V6K~D 2 CD67 1U_0402_6.3V6K~D 1 1 RD39 @ 10K_0402_5%~D DDR_A_D58 DDR_A_D59 2 2 @ RD32 10K_0402_5%~D +0.75VS 2 1 +3VS 1 205 1 2 1 2 CD72 2.2U_0603_6.3V6K~D 2 RD33 10K_0402_5%~D CD71 0.1U_0402_16V4Z~D RD40 10K_0402_5%~D CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT GND1 GND2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_A_DQS#0 DDR_A_DQS0 CPU JDIMM3 (H5.2) 4 (H9.2) DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 DDR3_DRAMRST# D DDR3_DRAMRST# 6,10,11,13 DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 DDR_CKE1_DIMMA DDR_CKE1_DIMMA 6 DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 M_ODT1 M_CLK_DDR1 6 M_CLK_DDR#1 6 DDR_A_BS1 DDR_A_RAS# C +1.5V 6,10 6,10 DDR_CS0_DIMMA# 6 M_ODT0 6 M_ODT1 RD30 1K_0402_1%~D 6 +VREF_CC DDR_A_D36 DDR_A_D37 1 DDR_A_D38 DDR_A_D39 2 DDR_A_D44 DDR_A_D45 1 2 CD66 0.1U_0402_16V4Z~D Layout Note: Place near JDIMM1.203,204 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT DDR_A_D4 DDR_A_D5 CD65 2.2U_0603_6.3V6K~D DDR_A_D32 DDR_A_D33 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 DDR_A_D2 DDR_A_D3 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS 2 2 DDR_A_D0 DDR_A_D1 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS 1 2 1 CD52 0.1U_0402_16V4Z~D 1 CD51 2.2U_0603_6.3V6K~D 6,10 DDR_A_D[0..63] 6,10 DDR_A_MA[0..15] 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 RD31 1K_0402_1%~D 2 +DIMM3_VREF 6,10 DDR_A_DQS[0..7] C 2 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 B DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 M_THERMAL# PCH_SMBDATA PCH_SMBCLK M_THERMAL# 10,11,13,44 PCH_SMBDATA 5,10,11,13,16,37,38 PCH_SMBCLK 5,10,11,13,16,37,38 +0.75VS 206 TYCO_2-2013289-1 Link Done A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title DDRIII DIMMC Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 12 of 63 5 4 3 +V_DDR_REFB RD41 1 2 +1.5V 2 0_0402_5%~D 1 2 (H8) 1 (H4) +1.5V JDIMM4 +DIMM4_VREF 2 6,11 DDR_B_D[0..63] D 6,11 DDR_B_MA[0..15] 1 2 DDR_B_D0 DDR_B_D1 CD77 0.1U_0402_16V4Z~D 6,11 DDR_B_DQS[0..7] CD76 2.2U_0603_6.3V6K~D 1 6,11 DDR_B_DQS#[0..7] DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 Note: Check voltage tolerance of VREF_DQ at the DIMM socket DDR_B_D10 DDR_B_D11 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 Layout Note: Place near JDIMMB DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDR_B_D4 DDR_B_D5 DDR_B_DQS#0 DDR_B_DQS0 CPU 3 (H5.2) JDIMM4 (H9.2) DDR_B_D6 DDR_B_D7 D DDR_B_D12 DDR_B_D13 DDR3_DRAMRST# DDR3_DRAMRST# 6,10,11,12 DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 +1.5V DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 C 6 6 +1.5V M_CLK_DDR2 M_CLK_DDR#2 6,11 DDR_B_BS0 2 @ 1 + 2 6,11 DDR_B_WE# 6,11 DDR_B_CAS# 6 DDR_CS3_DIMMB# DDR_B_MA10 DDR_B_BS0 DDR_B_WE# DDR_B_CAS# DDR_B_MA13 DDR_CS3_DIMMB# DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35 SA0 SA1 Layout Note: Place near JDIMM4.203,204 1 0 DIMM1 1 1 DIMM2 0 0 DIMM3 0 1 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DIMM4 DDR_B_D48 DDR_B_D49 +3VS DDR_B_DQS#6 DDR_B_DQS6 +0.75VS B DDR_B_D50 DDR_B_D51 2 1 DDR_B_D56 DDR_B_D57 @ RD46 10K_0402_5%~D RD50 10K_0402_5%~D DDR_B_D58 DDR_B_D59 1 2 2 2 1 CD95 1U_0402_6.3V6K~D 2 1 CD94 1U_0402_6.3V6K~D 1 CD93 1U_0402_6.3V6K~D 2 CD92 1U_0402_6.3V6K~D 1 +3VS 1 2 2 RD49 @ 10K_0402_5%~D 2 CD96 0.1U_0402_16V4Z~D RD48 10K_0402_5%~D 1 2 CD97 2.2U_0603_6.3V6K~D 1 1 +0.75VS 205 GND1 GND2 DDR_CKE3_DIMMB 6 DDR_B_MA15 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 M_ODT3 C M_CLK_DDR3 6 M_CLK_DDR#3 6 DDR_B_BS1 DDR_B_RAS# +1.5V 6,11 6,11 DDR_CS2_DIMMB# 6 M_ODT2 6 M_ODT3 RD44 1K_0402_1%~D 6 +VREF_CD DDR_B_D36 DDR_B_D37 1 DDR_B_D38 DDR_B_D39 DDR_B_D44 DDR_B_D45 2 1 2 CD91 0.1U_0402_16V4Z~D DDR_B_D32 DDR_B_D33 DDR_CKE3_DIMMB CD90 2.2U_0603_6.3V6K~D CD89 330U_SX_2VY~D 2 1 CD88 10U_0603_6.3V6M~D 2 1 CD87 10U_0603_6.3V6M~D 2 1 CD86 10U_0603_6.3V6M~D 2 1 CD85 10U_0603_6.3V6M~D 2 1 CD84 10U_0603_6.3V6M~D 1 CD83 10U_0603_6.3V6M~D 2 CD82 10U_0603_6.3V6M~D 1 M_CLK_DDR2 M_CLK_DDR#2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 1 2 CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT 2 2 1 DDR_B_BS2 1 2 1 CD81 1U_0402_6.3V6K~D 1 CD80 1U_0402_6.3V6K~D CD79 1U_0402_6.3V6K~D 2 CD78 1U_0402_6.3V6K~D 1 DDR_CKE2_DIMMB 6,11 DDR_B_BS2 RD45 1K_0402_1%~D 2 6 DDR_CKE2_DIMMB DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 B DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 M_THERMAL# PCH_SMBDATA PCH_SMBCLK M_THERMAL# 10,11,12,44 PCH_SMBDATA 5,10,11,12,16,37,38 PCH_SMBCLK 5,10,11,12,16,37,38 +0.75VS 206 TYCO_2-2013310-1 Link Done A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title DDRIII DIMMD Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 13 of 63 5 4 3 2 +3V_MXM 1 VIN+ A 49 1 VIN- 2 2 0_0402_5%~D +3V_MXM R596 VIN+ VINGND VS A1 A0 SDA SCL 8 7 6 5 5 B VGA_PRSNT_R# 19 A Y PEG_GTX_HRX_N1 PEG_GTX_HRX_P1 MC74VHC1G09DFT2G_SC70-5 PEG_GTX_HRX_N0 PEG_GTX_HRX_P0 R5 R6 16 CLK_PEG_PCH# 16 CLK_PEG_PCH 1 1 +3VMXM 2 0_0402_5%~D 2 0_0402_5%~D 2 10K_0402_5%~D 2 CLK_PEG_PCH#_R CLK_PEG_PCH_R 1 2 PAD-OPEN 4x4m LVDS PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_P12 +3V_MXM 2 HDMI R682 10K_0402_5%~D 25 VGA_TZOUT125 VGA_TZOUT1+ VGA_TZOUT1VGA_TZOUT1+ 25 VGA_TZOUT025 VGA_TZOUT0+ VGA_TZOUT0VGA_TZOUT0+ 28 GPU_HDMI_TXD228 GPU_HDMI_TXD2+ GPU_HDMI_TXD2GPU_HDMI_TXD2+ 28 GPU_HDMI_TXD128 GPU_HDMI_TXD1+ GPU_HDMI_TXD1GPU_HDMI_TXD1+ 28 GPU_HDMI_TXD028 GPU_HDMI_TXD0+ GPU_HDMI_TXD0GPU_HDMI_TXD0+ 28 GPU_HDMI_TXC28 GPU_HDMI_TXC+ GPU_HDMI_TXCGPU_HDMI_TXC+ 28 GPU_HDMI_SDATA 28 GPU_HDMI_SCLK B+_MXM_A0 GPU_HDMI_SDATA GPU_HDMI_SCLK R692 @ 10K_0402_5%~D 1 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_P9 VGA_TZOUT2VGA_TZOUT2+ 2 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_P10 25 VGA_TZOUT225 VGA_TZOUT2+ 1 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_P13 VGA_TZCLKVGA_TZCLK+ 1 PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_P14 25 VGA_TZCLK25 VGA_TZCLK+ J13 @ SYSTEM PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_P6 +3V_MXM 2 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_P7 @R681 @ R681 10K_0402_5%~D PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_P3 1 DMC B+_MXM_A1 2 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_P4 R691 10K_0402_5%~D 30 VGA_DPD_N0 30 VGA_DPD_P0 VGA_DPD_N0 VGA_DPD_P0 30 VGA_DPD_N1 30 VGA_DPD_P1 VGA_DPD_N1 VGA_DPD_P1 30 VGA_DPD_N2 30 VGA_DPD_P2 VGA_DPD_N2 VGA_DPD_P2 30 VGA_DPD_N3 30 VGA_DPD_P3 VGA_DPD_N3 VGA_DPD_P3 1 2 G VGA_SMB_CK1 S 1 D 3 Q2 SSM3K7002F_SC59-3~D GND GND PEX_RX2# PEX_TX2# PEX_RX2 PEX_TX2 GND GND PEX_RX1# PEX_TX1# PEX_RX1 PEX_TX1 GND GND PEX_RX0# PEX_TX0# PEX_RX0 PEX_TX0 GND GND PEX_REFCLK# PEX_CLK_REQ# PEX_REFCLK PEX_RST# GND VGA_DDC_DAT RSVD VGA_DDC_CLK RSVD VGA_VSYNC RSVD VGA_HSYNC RSVD GND RSVD VGA_RED LVDS_UCLK# VGA_GREEN LVDS_UCLK VGA_BLUE GND GND LVDS_UTX3# LVDS_LCLK# LVDS_UTX3 LVDS_LCLK GND GND LVDS_UTX2# LVDS_LTX3# LVDS_UTX2 LVDS_LTX3 GND GND LVDS_UTX1# LVDS_LTX2# LVDS_UTX1 LVDS_LTX2 GND GND LVDS_UTX0# LVDS_LTX1# LVDS_UTX0 LVDS_LTX1 GND GND DP_C_L0# LVDS_LTX0# DP_C_L0 LVDS_LTX0 GND GND DP_C_L1# DP_D_L0# DP_C_L1 DP_D_L0 GND GND DP_C_L2# DP_D_L1# DP_C_L2 DP_D_L1 GND GND DP_C_L3# DP_D_L2# DP_C_L3 DP_D_L2 GND GND DP_C_AUX# DP_D_L3# DP_C_AUX DP_D_L3 RSVD GND RSVD DP_D_AUX# RSVD DP_D_AUX RSVD DP_C_HPD RSVD DP_D_HPD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GND RSVD DP_B_L0# RSVD DP_B_L0 RSVD GND GND DP_B_L1# DP_A_L0# DP_B_L1 DP_A_L0 GND GND DP_B_L2# DP_A_L1# DP_B_L2 DP_A_L1 GND GND DP_B_L3# DP_A_L2# DP_B_L3 DP_A_L2 GND GND DP_B_AUX# DP_A_L3# DP_B_AUX DP_A_L3 DP_B_HPD GND DP_A_HPD DP_A_AUX# 3V3 DP_A_AUX 3V3 PRSNT_L# 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262 264 266 268 270 272 274 276 278 280 282 284 286 288 290 292 294 296 298 300 302 304 306 308 GND 312 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P0 PEG_CLKREQ# PLTRST_VGA# VGA_DDC_DATA VGA_DDC_CLK VGA_CRT_VSYNC VGA_CRT_HSYNC PEG_CLKREQ# 16 PLTRST_VGA# 18 VGA_DDC_DATA 27 VGA_DDC_CLK 27 VGA_CRT_VSYNC 27 VGA_CRT_HSYNC 27 VGA_CRT_R VGA_CRT_G VGA_CRT_B VGA_CRT_R VGA_CRT_G VGA_CRT_B VGA_TXCLKVGA_TXCLK+ VGA_TXCLK- 25 VGA_TXCLK+ 25 VGA_TXOUT2VGA_TXOUT2+ VGA_TXOUT2- 25 VGA_TXOUT2+ 25 VGA_TXOUT1VGA_TXOUT1+ VGA_TXOUT1- 25 VGA_TXOUT1+ 25 VGA_TXOUT0VGA_TXOUT0+ VGA_TXOUT0- 25 VGA_TXOUT0+ 25 MXM_TX0N MXM_TX0P MXM_TX0N MXM_TX0P 23 23 MXM_TX1N MXM_TX1P MXM_TX1N MXM_TX1P 23 23 MXM_TX2N MXM_TX2P MXM_TX2N MXM_TX2P 23 23 MXM_TX3N MXM_TX3P MXM_TX3N MXM_TX3P 23 23 MXM_DPB_AUXN/DDC MXM_DPB_AUXP/DDC VGA_HDMI_DET MXM_DPB_HPD MXM_DPB_AUXN/DDC 23 MXM_DPB_AUXP/DDC 23 VGA_HDMI_DET 28 MXM_DPB_HPD 23 VGA_DPC_N0 VGA_DPC_P0 VGA_DPC_N0 29 VGA_DPC_P0 29 VGA_DPC_N1 VGA_DPC_P1 VGA_DPC_N1 29 VGA_DPC_P1 29 VGA_DPC_N2 VGA_DPC_P2 VGA_DPC_N2 29 VGA_DPC_P2 29 VGA_DPC_N3 VGA_DPC_P3 VGA_DPC_N3 29 VGA_DPC_P3 29 VGA_DPC_AUXN/DDC VGA_DPC_AUXP/DDC VGA_DPC_HPD VGA_DMC_HPD VGA_DPC_AUXN/DDC VGA_DPC_AUXP/DDC VGA_DPC_HPD 29 VGA_DMC_HPD 30 27 27 27 CRT C LVDS eDP B mDP 29 29 +3V_MXM 40mil(1A) 1 30 VGA_DPD_AUXN/DDC 30 VGA_DPD_AUXP/DDC 19 VGA_PRSNT_L# 2 1 2 G 3 Q1 SSM3K7002F_SC59-3~D 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231 233 235 237 239 241 243 245 247 249 251 253 255 257 259 261 263 265 267 269 271 273 275 277 279 281 283 285 287 289 291 293 295 297 299 301 303 305 307 309 310 VGA_SMB_DA1 S 1 D 2 AC_BATT# +3V_MXM VGA_SMB_DA1 VGA_SMB_CK1 44 44,48 EC_SMB_DA1 D 1 1 2 PEG_GTX_HRX_N2 PEG_GTX_HRX_P2 4 DGPU_PWROK 19 VGA_ON 16 AC_BATT# VGA_TH_OVERT# 1 R8 TH_OVERT# 44,48 EC_SMB_CK1 U622 3 VGA_PRSNT_R# VGA_WAKE# DGPU_PWROK VGA_ON 1 2 JMXM1B G VCC 2 44 EC_AC_BAT# B+_MXM_A1 B+_MXM_A0 MXM_CURI2C_DATA MXM_CURI2C_CLK INA219AIDCNRG4_SOT23-8 5 1 ACIN 3 +3V_MXM Q3 SSM3K7002F_SC59-3~D C1823 0.1U_0402_25V6K~D 2 4 0_0402_5%~D 2 0_0402_5%~D 2 1 R694 VGA_SMB_DA1 1 R693 VGA_SMB_CK1 311 GND JAE_MM70-314-310B1-1 CONN@ For B+_MXM slave address : 1000010 please placemnet near R-sense U51 1 2 3 4 1 VGA_TH_OVERT# 1 (Pull-UP 10K at PCH) Link Done 1 @ C852 @C852 .1U_0402_16V7K~D 17,41,44,50 JAE_MM70-314-310B1-1 CONN@ 2 0_0402_5%~D R594 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 2 2 2 D 49 GND GND GND GND GND E4 GND GND GND GND PRSNT_R# W AKE# PW R_GOOD PW R_EN RSVD RSVD RSVD RSVD PW R_LEVEL TH_OVERT# TH_ALERT# TH_PW M GPIO0 GPIO1 GPIO2 SMB_DAT SMB_CLK GND OEM OEM OEM OEM GND PEX_TX15# PEX_TX15 GND PEX_TX14# PEX_TX14 GND PEX_TX13# PEX_TX13 GND PEX_TX12# PEX_TX12 GND PEX_TX11# PEX_TX11 GND PEX_TX10# PEX_TX10 GND PEX_TX9# PEX_TX9 GND PEX_TX8# PEX_TX8 GND PEX_TX7# PEX_TX7 GND PEX_TX6# PEX_TX6 GND PEX_TX5# PEX_TX5 GND PEX_TX4# PEX_TX4 GND PEX_TX3# PEX_TX3 GND 2 1 C5 4.7U_0805_10V4Z~D B GND GND GND GND GND E3 GND GND GND GND 5V 5V 5V 5V 5V GND GND GND GND PEX_STD_SW # VGA_DISABLE# PNL_PW R_EN PNL_BL_EN PNL_BL_PW M HDMI_CEC DVI_HPD LVDS_DDC_DAT LVDS_DDC_CLK GND OEM OEM OEM OEM GND PEX_RX15# PEX_RX15 GND PEX_RX14# PEX_RX14 GND PEX_RX13# PEX_RX13 GND PEX_RX12# PEX_RX12 GND PEX_RX11# PEX_RX11 GND PEX_RX10# PEX_RX10 GND PEX_RX9# PEX_RX9 GND PEX_RX8# PEX_RX8 GND PEX_RX7# PEX_RX7 GND PEX_RX6# PEX_RX6 GND PEX_RX5# PEX_RX5 GND PEX_RX4# PEX_RX4 GND PEX_RX3# PEX_RX3 GND 2 1 +3VALW S C 1 3.3K_0402_5% 3.3K_0402_5% 4.3K_0402_5% 4.3K_0402_5% 10K_0402_5%~D +3VALW 1 C1 0.1U_0603_25V7K~D 19 21 23 25 2 2 27 29 31 +5V_MXM 33 35 37 39 41 43 45 47 100mil(2.5A, 5VIA) 49 Add R7 increase NV MXM PEG Swing 51 53 R7 1 2 0_0402_5%~D 55 VGA_DISABLE# 57 59 26 DGPU_ENVDD 61 26 DGPU_BKL_EN 63 26 VGA_PNL_PWM VGA_HDMI_CEC 65 67 VGA_LCD_DAT 69 26 VGA_LCD_DAT VGA_LCD_CLK 71 26 VGA_LCD_CLK 73 LVDS DDC Module have 4.7K Pull-UP 75 @ R9 10K_0402_5%~D 1 2 77 +3V_MXM @ R10 1 236K_0402_1% 79 81 34,35 SPDIF_OUT 83 PEG_GTX_HRX_N15 85 PEG_GTX_HRX_P15 87 89 PEG_GTX_HRX_N14 91 PEG_GTX_HRX_P14 93 95 PEG_GTX_HRX_N13 97 PEG_GTX_HRX_P13 99 101 PEG_GTX_HRX_N12 103 PEG_GTX_HRX_P12 105 107 PEG_GTX_HRX_N11 109 PEG_GTX_HRX_P11 111 113 PEG_GTX_HRX_N10 115 PEG_GTX_HRX_P10 117 119 PEG_GTX_HRX_N9 121 PEG_GTX_HRX_P9 123 125 PEG_GTX_HRX_N8 127 PEG_GTX_HRX_P8 129 131 PEG_GTX_HRX_N7 133 PEG_GTX_HRX_P7 135 137 PEG_GTX_HRX_N6 139 PEG_GTX_HRX_P6 141 143 PEG_GTX_HRX_N5 145 PEG_GTX_HRX_P5 147 149 PEG_GTX_HRX_N4 151 PEG_GTX_HRX_P4 153 155 PEG_GTX_HRX_N3 157 PEG_GTX_HRX_P3 159 161 1 2 2 2 2 1 400mil(10A) 2 4 6 8 10 12 14 16 18 C4 68P_0402_50V8J~D C328 10U_0603_6.3V6M~D 1 PAD-OPEN 4x4m C7 0.1U_0402_16V4Z~D 2 E2 PW R_SRC PW R_SRC PW R_SRC PW R_SRC PW R_SRC PW R_SRC PW R_SRC PW R_SRC PW R_SRC C3 680P_0603_50V7K~D J12 @ PW R_SRC PW R_SRC PW R_SRC PW R_SRC PW R_SRCE1 PW R_SRC PW R_SRC PW R_SRC PW R_SRC C2 10U_1206_25V6M~D +5V_MXM +5VMXM 1 1 1 1 2 B+_MXM JMXM1A 1 3 5 7 9 11 13 15 17 D MXM_CURI2C_CLK @ R1818 MXM_CURI2C_DATA @ R1819 VGA_DDC_DATA R23 VGA_DDC_CLK R24 AC_BATT# R1816 G B+_MXM @ @ 4.3K_0402_5% 4.3K_0402_5% 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D R2 4.7K_0402_5%~D PEG_GTX_HRX_P[0..15] 2 2 1 2 2 2 R1 4.7K_0402_5%~D PEG_GTX_HRX_N[0..15] 4 PEG_GTX_HRX_P[0..15] 1 1 2 1 1 1 R16 10K_0402_5%~D 4 PEG_GTX_HRX_N[0..15] R13 R14 R15 R18 R19 R20 R11 10K_0402_5%~D VGA_LCD_CLK VGA_LCD_DAT DGPU_PWROK VGA_HDMI_CEC VGA_DISABLE# VGA_WAKE# PEG_HTX_C_GRX_P[0..15] 4 PEG_HTX_C_GRX_P[0..15] +3V_MXM +3V_MXM PEG_HTX_C_GRX_N[0..15] 4 PEG_HTX_C_GRX_N[0..15] 1 +3V_MXM A Link Done DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 3 2 Title MXMIII Connector A Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 14 of 63 3 2 18P_0402_50V8J~D 2 RH2 10M_0402_5%~D D 18P_0402_50V8J~D 2 1 1 CH2 YH1 1 4 PCH_RTCX2 4 PCH_RTCX1 1 OSC NC OSC NC 3 2 D 32.768KHZ_12.5PF_Q13MC14610002 2 5 Far away hot spot 1 CH3 +RTCVCC 1 RH11 2 1M_0402_5%~D SM_INTRUDER# UH1A RH55 1K_0402_5%~D ME1 @ SHORT PADS 2 ME CMOS CLP1 & CLP2 place near DIMM 34 HDA_SDOUT_AUDIO 34 HDA_BITCLK_AUDIO RH30 1 2 R1960 1M_0402_5%~D 1 1 HDA_SPKR 34 3 1 D RH33 1 S 34 HDA_SYNC_AUDIO RH28 34 +5VS HDA_SDOUT 33_0402_5%~D HDA_BIT_CLK 2 33_0402_5%~D HDA_RST# 2 33_0402_5%~D HDA_SYNC_R 2 33_0402_5%~D 2 G RH27 34 HDA_RST_AUDIO# 1 RH36 @ FWH4 / LFRAME# G22 SRTCRST# SM_INTRUDER# K22 INTRUDER# PCH_INTVRMEN C17 N34 HDA_SYNC L34 HDA_SYNC HDA_SPKR T10 SPKR HDA_RST# K34 HDA_RST# HDA_SYNC 44 HDA_SDO RH50 HDA_SDOUT 2 0_0402_5%~D 1 E34 EDP_DETECT# SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP HDA_SDIN0 G34 HDA_SDIN1 C34 HDA_SDIN2 HDA_SDIN3 A36 SATA2RXN SATA2RXP SATA2TXN SATA2TXP HDA_SDO C36 25 EDP_DETECT# SERIRQ HDA_BCLK A34 2 0_0402_5%~D LDRQ0# LDRQ1# / GPIO23 INTVRMEN HDA_BIT_CLK QH1 BSS138_SOT23~D 1 RTCRST# PCH_SRTCRST# HDA_SDIN0 HDA_SDIN0 LPC D20 FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 HDA_DOCK_EN# / GPIO33 N32 SATA3RXN SATA3RXP SATA3TXN SATA3TXP SATA4RXN SATA4RXP SATA4TXN SATA4TXP HDA_DOCK_RST# / GPIO13 200_0402_5% 1 2 @ RH39 PCH_JTAG_TMS 1 2 @ RH38 PCH_JTAG_TDO 2 2 1 PCH_JTAG_TMS H7 JTAG_TMS 5 PCH_JTAG_TDI PCH_JTAG_TDI K5 JTAG_TDI 5 PCH_JTAG_TDO PCH_JTAG_TDO H1 T3 PCH_SPI_CS# Y14 V4 PCH_SPI_SO U3 SATA3RBIAS 44 44 44 44 LPC_FRAME# 44 SERIRQ 44 +3VS SERIRQ AM3 AM1 AP7 AP5 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 36 36 36 36 HDD2 AM10 AM8 AP11 AP10 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 36 36 36 36 HDD1 AD7 AD5 AH5 AH4 SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 SATA_PTX_DRX_N2 SATA_PTX_DRX_P2 37 37 37 37 ODD Y7 Y5 AD3 AD1 SATA_PRX_DTX_N4 SATA_PRX_DTX_P4 SATA_PTX_DRX_N4 SATA_PTX_DRX_P4 1 @ 2 RH59 @ 33_0402_5%~D 2 3.3K_0402_5% RH56 1 2 3.3K_0402_5% PCH_SPI_HOLD# CS# DO WP# GND SPI_CS1# SPI_MOSI SATALED# SATA0GP / GPIO21 SPI_MISO SATA1GP / GPIO19 2 1 10K_0402_5%~D BBS_BIT0_R RH47 2 1 10K_0402_5%~D :: +1.05VS_VCC_SATA SATA_COMP 1 RH41 +3VS 2 37.4_0402_1% HDA_SPKR @ RH37 +1.05VS_SATA3 AB12 AB13 SATA3_COMP 1 RH43 2 49.9_0402_1% AH1 RBIAS_SATA3 1 RH48 2 750_0402_1% 2 Reserve for EMI please close to U48 B P3 PCH_SATALED# +3V_PCH V14 PCH_GPIO21 P1 BBS_BIT0_R HDA_SDOUT PCH_SATALED# 42 @ RH42 2 1 1K_0402_5%~D *Low = Disabled High = Enabled HDA_SDO +3V_PCH 8 7 6 5 PCH_SPI_HOLD# PCH_SPI_CLK_R 1 15_0402_5%~D PCH_SPI_SI_R 1 0_0402_5%~D PCH_SPI_CLK RH60 2 PCH_SPI_SI RH61 2 1 SPI ROM FOR ME ( 4MByte ) This signal has a weak internal pull-down On Die PLL VR is supplied by 1.5V when smapled high 1.8V when sampled low Needs to be pulled High for Huron River platfrom +3V_PCH (5)DIO (6)CLK (7)HOLD# (8)VCC 2 A HDA_SYNC RH52 DELL CONFIDENTIAL/PROPRIETARY W25X32 Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 1 1K_0402_5%~D *LOW=Default HIGH=No Reboot 1 1K_0402_5%~D (1)CS# (2)DO (3)WP# (4)GND @ RH34 330K_0402_5% H Integrated VRM enable L Integrated VRM disable E-SATA ME debug mode , this signal has a weak internal PD L=>security measures defined in the Flash Descriptor will be in effect (default) H=>Flash Descriptor Security will be overridden 1 @ SPI BIOS Pinout 1 10K_0402_5%~D 2 SPI_CS0# 2 CH8 22P_0402_50V8J~D 1 2 RH35 HDA_SYNC VCC HOLD# CLK DI W25Q32BVSSIG_SO8 A RH32 PCH_SATALED# PCH_SPI_WP# RH54 1 1 2 3 4 PCH_GPIO21 RH31 330K_0402_5% * 40 40 40 40 U48 PCH_SPI_CS#_R PCH_SPI_SO_R PCH_SPI_WP# 1 10K_0402_5%~D PCH_INTVRMEN CH6 0.1U_0402_16V4Z~D 2 PCH_SPI_CS# PCH_SPI_SO RH58 0_0402_5%~D 1 2 1 2 RH62 0_0402_5%~D 2 INTVRMEN +3V_PCH RH57 3.3K_0402_5% PCH_SPI_CLK RH29 +RTCVCC CougarPoint_Rev_1p0 +3V_PCH SERIRQ C AB8 AB10 AF3 AF1 Y10 SPI_CLK T1 PCH_SPI_SI V5 Y11 JTAG_TDO LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 E36 K36 SATAICOMPI SATA3COMPI PCH_SPI_CLK LPC_FRAME# SATAICOMPO SATA3RCOMPO RH44 100_0402_1%~D RH45 100_0402_1%~D RH46 100_0402_1%~D 2 5 PCH_JTAG_TMS D36 Y3 Y1 AB3 AB1 JTAG_TCK JTAG PCH_JTAG_TDI 1 1 2 @ RH40 1 1 200_0402_5% B PCH_JTAG_TCK RH53 2 200_0402_5% J3 SPI 51_0402_5% 5 PCH_JTAG_TCK LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 SATA5RXN SATA5RXP SATA5TXN SATA5TXP +3V_PCH PCH_JTAG_TCK C38 A38 B37 C37 1 1 CH5 1U_0603_10V4Z~D +RTCBATT PCH_RTCRST# RTCX2 2 CHN202UPT_SC70-3 2 C20 2 2 20K_0402_5%~D W=20mils 3 1 PCH_RTCX2 RTCX1 1 RH23 1 1 A20 SATA 6G 2 2 20K_0402_5%~D 2 C CH7 1U_0603_10V4Z~D 1 +CHGRTC PCH_RTCX1 SATA W=20mils RH25 1 W=20mils 1 2 2 2 DH1 COMS1 @ SHORT PADS RTC +RTCVCC CMOS IHDA CH4 1U_0603_10V4Z~D 2 +RTCVCC 1 1 RTC Battery 4 3 2 Title PCH (1/8) SATA,HDA,SPI, LPC Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 15 of 63 5 4 3 2 1 +3V_PCH UH1B Card Reader ---> PCIE_LAN# PCIE_LAN 2 2 2 1 0_0402_5%~D 1 0_0402_5%~D 1 10K_0402_5%~D PCIE_MINI2# PCIE_MINI2 38 CLK_PCIE_MINI2# 38 CLK_PCIE_MINI2 +3VS 38 MINI2CLK_REQ# RH96 RH97 RH100 38 CLK_PCIE_MINI1# 38 CLK_PCIE_MINI1 +3V_PCH 38 MINI1CLK_REQ# RH101 RH102 RH103 35 CLK_PCIE_CD# 35 CLK_PCIE_CD +3V_PCH 35 CDCLK_REQ# 2 2 2 RH104 RH106 RH107 2 2 2 1 0_0402_5%~D 1 0_0402_5%~D 1 10K_0402_5%~D 1 0_0402_5%~D 1 0_0402_5%~D 1 10K_0402_5%~D J2 AB49 AB47 LANCLK_REQ# M1 AA48 AA47 C13 GPIO74 SML1CLK / GPIO58 E14 SML1CLK SML1DATA / GPIO75 M16 SML1DATA CLKOUT_PCIE1N CLKOUT_PCIE1P +3V_MXM M7 +3V_PCH CLKOUT_PCIE3N CLKOUT_PCIE3P CL_RST1# P10 1 3 AB37 AB38 CLK_PEG_PCH# CLK_PEG_PCH CLK_PEG_PCH# 14 CLK_PEG_PCH 14 CLKOUT_DMI_N CLKOUT_DMI_P AV22 AU22 CLK_CPU_DMI# CLK_CPU_DMI CLK_CPU_DMI# 5 CLK_CPU_DMI 5 CLKOUT_DP_N CLKOUT_DP_P AM12 AM13 CLK_CPU_DPLL# CLK_CPU_DPLL CLK_CPU_DPLL# 5 CLK_CPU_DPLL 5 CLKIN_DMI_N CLKIN_DMI_P BF18 BE18 CLKIN_DMI# CLKIN_DMI CLKIN_GND1_N CLKIN_GND1_P BJ30 BG30 CLKIN_DMI2# CLKIN_DMI2 G24 E24 CLKIN_DOT96# CLKIN_DOT96 VGA CDCLK_REQ# L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_N CLKIN_SATA_P CLKOUT_PCIE5N CLKOUT_PCIE5P AK7 AK5 RH92 @ 10K_0402_5%~D QH3A DMN66D0LDW-7_SOT363-6~D RH110 1 2 10K_0402_5%~D +3V_PCH RH112 1 2 10K_0402_5%~D PEG_B_CLKREQ# RH114 RH115 RH116 2 2 1 1 0_0402_5%~D 1 0_0402_5%~D 2 10K_0402_5%~D PCIE_USB30# PCIE_USB30 V40 V42 CLKOUT_PCIE6N CLKOUT_PCIE6P USB30_CLKREQ# T13 PCIECLKRQ6# / GPIO45 V38 V37 CLKOUT_PCIE7N CLKOUT_PCIE7P VGA_ON K12 PCIECLKRQ7# / GPIO46 CLK_BCLK_ITP# CLK_BCLK_ITP AK14 AK13 @ RH118 1 2 10K_0402_5%~D VGA_ON 5 CLK_CPU_ITP# 5 CLK_CPU_ITP CLK_CPU_ITP# CLK_CPU_ITP RH119 RH120 2 2 1 0_0402_5%~D 1 0_0402_5%~D 7 CLK_RES_ITP# 7 CLK_RES_ITP CLK_RES_ITP# CLK_RES_ITP @ RH121 @ RH122 2 2 1 0_0402_5%~D 1 0_0402_5%~D PCIECLKRQ5# / GPIO44 CLKOUT_PEG_B_N CLKOUT_PEG_B_P 6 1 CLKIN_SATA# CLKIN_SATA K45 CLK_PCH_14M CLKIN_PCILOOPBACK H45 CLK_PCI_LPBACK XTAL25_IN XTAL25_OUT V47 V49 XTAL25_IN XTAL25_OUT XCLK_RCOMP Y47 XCLK_RCOMP CLK_PCI_LPBACK CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P RH113 CLKOUTFLEX0 / GPIO64 K43 KB_DET# CLKOUTFLEX1 / GPIO65 F47 DMC_PCH_DET# CLKOUTFLEX2 / GPIO66 H47 BT_DET# CLKOUTFLEX3 / GPIO67 K49 CAM_DET# 1 2 KB_DET# +1.05VS_VCCDIFFCLKN 90.9_0402_1% 46 DMC_PCH_DET# BT_DET# 38 CAM_DET# 24,26 100K_0402_5%~D 1 2 R1745 CAM_DET# 10K_0402_5%~D 1 2 RH166 DMC_PCH_DET# 10K_0402_5%~D 1 2 RH109 BT_DET# 10K_0402_5%~D 1 2 RH108 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 2 RH76 RH77 RH78 RH79 RH80 RH81 RH82 RH83 RH84 A 1 2 @ 2 1 @ 1 CH22 22P_0402_50V8J~D 2 4 5,10,11,12,13,37,38 If use extenal CLK gen, please place close to CLK gen else, please place close to PCH DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Reserve for EMI please close to UH1 5 PCH_SMBDATA KB_DET# CLKIN_DMI2# CLKIN_DMI2 CLKIN_DMI# CLKIN_DMI CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA# CLKIN_SATA CLK_PCH_14M @ 2 1 CH24 12P_0402_50V8J~D CH23 12P_0402_50V8J~D 2 1 CH21 22P_0402_50V8J~D 25MHZ_12PF_X5H025000DC1H-H 1 RH89 33_0402_5%~D 2 4 38 CLK_PCI_LPBACK @ YH2 1 QH3B DMN66D0LDW-7_SOT363-6~D 3 +3VS CougarPoint_Rev_1p0 RH86 33_0402_5%~D A 5,10,11,12,13,37,38 RH111 @ 1 2 0_0402_5%~D 18 XTAL25_IN XTAL25_OUT PCH_SMBCLK PEG_B_CLKRQ# / GPIO56 CLK_PCH_14M 2 RH117 1 1M_0402_5%~D +3VS RH105 @ 1 2 0_0402_5%~D REFCLK14IN C 2 RH90 @ 1 B +3V_PCH +3V_PCH 14 S 0_0402_5%~D +3VS FLEX CLOCKS USB 3.0 ---> QH2B DMN66D0LDW-7_SOT363-6~D 1 SMBDATA 39 CLK_PCIE_USB30# 39 CLK_PCIE_USB30 +3V_PCH 39 USB30_CLKREQ# RH88 @ 10K_0402_5%~D 4 2 M10 SMBCLK CLKOUT_PCIE4N CLKOUT_PCIE4P 14 5 PEG_CLKREQ# QH2A DMN66D0LDW-7_SOT363-6~D 6 CLKOUT_PEG_A_N CLKOUT_PEG_A_P CLKIN_DOT_96N CLKIN_DOT_96P Y43 Y45 E6 D RH85 1K_0402_5%~D R21 10K_0402_5%~D RH87 10K_0402_5%~D PEG_CLKREQ#_R PCIECLKRQ3# / GPIO25 PCIE_CD# PCIE_CD AB42 AB40 2 RH73 2 CL_DATA1 T11 CLKOUT_PCIE2N CLKOUT_PCIE2P Y37 Y36 L14 1 G CL_CLK1 PCIECLKRQ1# / GPIO18 PCIE_MINI1# PCIE_MINI1 V45 V46 2.2K_0402_5%~D 1 PCIECLKRQ0# / GPIO73 PCIECLKRQ2# / GPIO20 B 2 RH74 SML1DATA +3V_MXM PEG_A_CLKRQ# / GPIO47 V10 A8 SML1ALERT# / PCHHOT# / GPIO74 CLKOUT_PCIE0N CLKOUT_PCIE0P MINI2CLK_REQ# MINI1CLK_REQ# 1 2 PCIECLKREQ0# 2 0_0402_5%~D 2 0_0402_5%~D 2 10K_0402_5%~D 2.2K_0402_5%~D 1 2 10K_0402_5%~D 1 1 1 G12 2 RH167 SML1CLK SML0DATA SML0DATA 1 RH99 2.2K_0402_5%~D MiniWLAN (Mini Card 1)---> 1 RH93 RH94 @ RH95 10K_0402_5%~D RH98 2.2K_0402_5%~D MiniDMC (Mini Card 2)---> RH91 2 RH75 2 10/100/1G LAN ---> +3V_PCH 33 CLK_PCIE_LAN# 33 CLK_PCIE_LAN +3VS 33 LANCLK_REQ# 2 RH72 1K_0402_5%~D 1 1 Y40 Y39 SML0CLK S PERN8 PERP8 PETN8 PETP8 SML0ALERT# / GPIO60 6 D BE38 BC38 AW38 AY38 1 5 PERN7 PERP7 PETN7 PETP7 2.2K_0402_5%~D G BG40 BJ40 AY40 BB40 2 RH70 SML0DATA GPIO74 DRAMRST_CNTRL_PCH D PERN6 PERP6 PETN6 PETP6 SML0CLK 2 RH69 1 2 BJ38 BG38 AU36 AV36 C8 1 2.2K_0402_5%~D G C PERN5 PERP5 PETN5 PETP5 DRAMRST_CNTRL_PCH 2.2K_0402_5%~D SML0CLK DRAMRST_CNTRL_PCH S 2 0.1U_0402_10V7K~D 2 0.1U_0402_10V7K~D PCIE_PRX_USB3TX_N6 PCIE_PRX_USB3TX_P6 PCIE_PTX_USB3RX_N6_C PCIE_PTX_USB3RX_P6_C BG37 BH37 AY36 BB36 A12 SMBDATA MEMORY SMBDATA 1 PERN4 PERP4 PETN4 PETP4 SMBDATA 2 BF36 BE36 AY34 BB34 C9 2 RH67 2 2 0.1U_0402_10V7K~D 2 0.1U_0402_10V7K~D PCIE_PRX_CARDTX_N4 PCIE_PRX_CARDTX_P4 PCIE_PTX_CARDRX_N4_C PCIE_PTX_CARDRX_P4_C SMBCLK 41,42,44 G PERN3 PERP3 PETN3 PETP3 H14 44 LID_SW_IN# 1 S CH19 1 CH20 1 BG36 BJ36 AV34 AU34 SMBCLK EC_LID_OUT# D USB 3.0 ---> PCIE_PRX_USB3TX_N6 PCIE_PRX_USB3TX_P6 PCIE_PTX_USB3RX_N6 PCIE_PTX_USB3RX_P6 2 0.1U_0402_10V7K~D 2 0.1U_0402_10V7K~D PCIE_PRX_WLANTX_N1 PCIE_PRX_WLANTX_P1 PCIE_PTX_WLANRX_N1_C PCIE_PTX_WLANRX_P1_C PCH_LID_SW_IN# D 39 39 39 39 CH12 1 CH13 1 PERN2 PERP2 PETN2 PETP2 E12 1 PCIE_PRX_CARDTX_N4 PCIE_PRX_CARDTX_P4 PCIE_PTX_CARDRX_N4 PCIE_PTX_CARDRX_P4 BE34 BF34 BB32 AY32 2 EC_LID_OUT# RH68 2 LID_SW_IN# RH71 @ 1 0_0402_5%~D 1 0_0402_5%~D SMBALERT# / GPIO11 2.2K_0402_5%~D 2 CARD_READER ---> 35 35 35 35 CH11 1 CH16 1 2 0.1U_0402_10V7K~D 2 0.1U_0402_10V7K~D PCIE_PRX_WANTX_N2 PCIE_PRX_WANTX_P2 PCIE_PTX_WANRX_N2_C PCIE_PTX_WANRX_P2_C PERN1 PERP1 PETN1 PETP1 1 PCIE_PRX_WLANTX_N1 PCIE_PRX_WLANTX_P1 PCIE_PTX_WLANRX_N1 PCIE_PTX_WLANRX_P1 BG34 BJ34 AV32 AU32 2 MiniWLAN (Mini Card 1)---> 38 38 38 38 CH10 1 CH15 1 PCIE_PRX_GLANTX_N3 PCIE_PRX_GLANTX_P3 PCIE_PTX_GLANRX_N3_C PCIE_PTX_GLANRX_P3_C SMBUS PCIE_PRX_WANTX_N2 PCIE_PRX_WANTX_P2 PCIE_PTX_WANRX_N2 PCIE_PTX_WANRX_P2 2 0.1U_0402_10V7K~D 2 0.1U_0402_10V7K~D Link 38 38 38 38 CH9 1 CH14 1 Controller D PCIE_PRX_GLANTX_N3 PCIE_PRX_GLANTX_P3 PCIE_PTX_GLANRX_N3 PCIE_PTX_GLANRX_P3 CLOCKS MiniDMC (Mini Card 2)---> 33 33 33 33 PCI-E* 10/100/1G LAN ---> SMBCLK 3 2 Title PCH (2/8) PCIE, SMBUS, CLK Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 16 of 63 5 4 3 2 1 UH1C DMI0RXN DMI1RXN DMI2RXN DMI3RXN DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 BE24 BC20 BJ18 BJ20 DMI0RXP DMI1RXP DMI2RXP DMI3RXP 4 4 4 4 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 AW24 AW20 BB18 AV18 4 4 4 4 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 AY24 AY20 AY18 AU18 DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_INT +1.05VS BJ24 DMI_IRCOMP 2 49.9_0402_1% RBIAS_CPY 2 750_0402_1%~D 1 RH124 1 RH125 BG25 BH21 DMI_ZCOMP FDI_FSYNC0 DMI_IRCOMP FDI_FSYNC1 DMI2RBIAS FDI_LSYNC0 FDI_LSYNC1 4mil width and place within 500mil of the PCH System Power Management DSWVRMEN C 2 SUSACK#_R 0_0402_5%~D 1 @ RH127 26,44 SG_AMD_BKL XDP_DBRESET# 5 XDP_DBRESET# C12 K3 5,44 SYSTEM_PWROK 1 RH129 2 0_0402_5%~D P12 5,44 PCH_PWROK 1 RH130 2 PM_PWROK_R 0_0402_5%~D L22 1 RH131 2 0_0402_5%~D 44 PCH_APWROK 5 PM_DRAM_PWRGD 44 PCH_RSMRST# 44 L10 PM_DRAM_PWRGD SYS_PWROK PWROK APWROK DRAMPWROK WAKE# CLKRUN# / GPIO32 SUS_STAT# / GPIO61 SUSCLK / GPIO62 SLP_S5# / GPIO63 2 PCH_RSMRST#_R C21 0_0402_5%~D RSMRST# 1 2 GPIO30 0_0402_5%~D SUSWARN#/SUSPWRDNACK/GPIO30 @RH134 @ RH134 1 RH135 5,44 PBTN_OUT# SYS_RESET# K16 2 PBTN_OUT#_R 0_0402_5%~D E20 ACIN_PCH H20 SLP_S4# SLP_S3# PWRBTN# SLP_A# 4 4 4 4 4 4 4 4 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 4 4 4 4 4 4 4 4 AW16 FDI_INT AV12 FDI_FSYNC0 FDI_FSYNC0 4 BC10 FDI_FSYNC1 FDI_FSYNC1 4 AV14 FDI_LSYNC0 FDI_LSYNC0 4 BB10 FDI_LSYNC1 FDI_LSYNC1 4 FDI_INT E22 B9 J47 M45 26 IGPU_BKLT_EN 26,44 PCH_ENVDD P45 L_BKLTCTL T40 K47 L_DDC_CLK L_DDC_DATA CTRL_CLK CTRL_DATA T45 P39 L_CTRL_CLK L_CTRL_DATA 1 2.37K_0402_1%~D LVDS_IBG AF37 AF36 26 PCH_INV_PWM 26 PCH_LCD_CLK 26 PCH_LCD_DATA RH144 2 AE48 AE47 25 PCH_TXCLK25 PCH_TXCLK+ 4 25 PCH_TXOUT025 PCH_TXOUT125 PCH_TXOUT225 PCH_TXOUT0+ 25 PCH_TXOUT1+ 25 PCH_TXOUT2+ PCH_DPWROK_R RH159 2 WAKE# 1 RH128 N3 1 PCH_RSMRST#_R 2 0_0402_5%~D 1 @ 2 0_0402_5%~D PCH_DPWROK 44 PCIE_WAKE# 33,38,39,44 0_0402_5%~D PM_CLKRUN# G8 SUS_STAT# N14 SUSCLK 2 RH132 25 PCH_TZOUT025 PCH_TZOUT125 PCH_TZOUT225 PCH_TZOUT0+ 25 PCH_TZOUT1+ 25 PCH_TZOUT2+ @ T76 PAD~D 1 0_0402_5%~D 25 PCH_TZCLK25 PCH_TZCLK+ SUSCLK_R D10 PM_SLP_S5# PM_SLP_S5# 41,44 H4 PM_SLP_S4# PM_SLP_S4# 44 F4 PM_SLP_S3# PM_SLP_S3# 41,44 44 27 PCH_CRT_BLU 27 PCH_CRT_GRN 27 PCH_CRT_RED AK39 AK40 LVDSA_CLK# LVDSA_CLK PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2- AN48 AM47 AK47 AJ48 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 PCH_TXOUT0+ PCH_TXOUT1+ PCH_TXOUT2+ AN47 AM49 AK49 AJ47 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 PCH_TZCLKPCH_TZCLK+ AF40 AF39 LVDSB_CLK# LVDSB_CLK PCH_TZOUT0PCH_TZOUT1PCH_TZOUT2- AH45 AH47 AF49 AF45 PCH_TZOUT0+ PCH_TZOUT1+ PCH_TZOUT2+ AH43 AH49 AF47 AF43 27 PCH_CRT_DDC_CLK 27 PCH_CRT_DDC_DAT 27 PCH_CRT_HSYNC 27 PCH_CRT_VSYNC G10 RH136 RH138 1 1 N48 P49 T49 PCH_CRT_DDC_CLK PCH_CRT_DDC_DAT T39 M40 2 33_0402_5%~D HSYNC 2 33_0402_5%~D VSYNC M47 M49 E10 RI# A10 PMSYNCH RI# SLP_LAN# / GPIO29 PM_SLP_SUS# AP14 H_PM_SYNC K14 +3V_PCH CougarPoint_Rev_1p0 Can be left NC when IAMT is not support on the platfrom H_PM_SYNC 5 SDVO_INTN SDVO_INTP AP39 AP40 P38 M39 HDMICLK_NB HDMIDAT_NB DDPB_AUXN DDPB_AUXP DDPB_HPD AT49 AT47 AT40 TMDS_B_HPD DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49 TMDS_B_DATA2# TMDS_B_DATA2 TMDS_B_DATA1# TMDS_B_DATA1 TMDS_B_DATA0# TMDS_B_DATA0 TMDS_B_CLK# TMDS_B_CLK P46 P42 PCH_DPC_CLK PCH_DPC_DAT DDPC_AUXN DDPC_AUXP DDPC_HPD AP47 AP49 AT38 PCH_DPC_AUXN PCH_DPC_AUXP DP_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 PCH_DPC_N0 PCH_DPC_P0 PCH_DPC_N1 PCH_DPC_P1 PCH_DPC_N2 PCH_DPC_P2 PCH_DPC_N3 PCH_DPC_P3 M43 M36 PCH_DPD_CLK PCH_DPD_DAT AT45 AT43 BH41 PCH_DMC_HPD BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 PCH_DPD_N0 PCH_DPD_P0 PCH_DPD_N1 PCH_DPD_P1 PCH_DPD_N2 PCH_DPD_P2 PCH_DPD_N3 PCH_DPD_P3 SDVO_CTRLCLK SDVO_CTRLDATA LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 CRT_BLUE CRT_GREEN CRT_RED CRT_DDC_CLK CRT_DDC_DATA T43 T42 HDMI DDPC_CTRLCLK DDPC_CTRLDATA mDP DDPD_CTRLCLK DDPD_CTRLDATA CRT_HSYNC CRT_VSYNC D DDPD_AUXN DDPD_AUXP DDPD_HPD DMC HDMI DAC_IREF CRT_IRTN DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P HDMICLK_NB 28 HDMIDAT_NB 28 TMDS_B_HPD 28 TMDS_B_DATA2# 28 TMDS_B_DATA2 28 TMDS_B_DATA1# 28 TMDS_B_DATA1 28 TMDS_B_DATA0# 28 TMDS_B_DATA0 28 TMDS_B_CLK# 28 TMDS_B_CLK 28 PCH_DPC_CLK 29 PCH_DPC_DAT 29 PCH_DPC_AUXN 29 PCH_DPC_AUXP 29 DP_HPD 29 PCH_DPC_N0 PCH_DPC_P0 PCH_DPC_N1 PCH_DPC_P1 PCH_DPC_N2 PCH_DPC_P2 PCH_DPC_N3 PCH_DPC_P3 C 29 29 29 29 29 29 29 29 PCH_DPD_CLK 30 PCH_DPD_DAT 30 PCH_DMC_HPD 30 PCH_DPD_N0 PCH_DPD_P0 PCH_DPD_N1 PCH_DPD_P1 PCH_DPD_N2 PCH_DPD_P2 PCH_DPD_N3 PCH_DPD_P3 30 30 30 30 30 30 30 30 CougarPoint_Rev_1p0 B RH140 1K_0402_0.5%~D If not using integrated LAN,signal may be left as NC. 1 +3V_PCH PM_SLP_SUS# 44 SDVO_STALLN SDVO_STALLP AM42 AM40 1 BATLOW# / GPIO72 G16 AP43 AP45 LVD_VREFH LVD_VREFL PCH_TXCLKPCH_TXCLK+ PCH_CRT_BLU PCH_CRT_GRN PCH_CRT_RED SDVO_TVCLKINN SDVO_TVCLKINP 2 BATLOW# B SLP_SUS# LVD_IBG LVD_VBG Minimum speacing of 20mils for LVD_IBG CRT_IREF ACPRESENT / GPIO31 L_BKLTEN L_VDD_EN DSWODVREN A18 RH126 DPWROK 1 RH133 SUSWARN# B13 SUSACK# FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 Digital Display Interface DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 BC24 BE20 BG18 BG20 LVDS 4 4 4 4 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 CRT DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI 4 4 4 4 FDI UH1D D 1 R1900 10K_0402_5% G 1 ACIN_PCH D 5 G RH147 330K_0402_5% S 1 2 2.2K_0402_5%~D PCH_CRT_DDC_CLK RH152 1 2 2.2K_0402_5%~D PCH_CRT_DDC_DAT RH155 1 2 2.2K_0402_5%~D CTRL_CLK RH157 1 2 2.2K_0402_5%~D CTRL_DATA @R78 @ R78 1 2 8.2K_0402_5% RV1 1 2 2.2K_0402_5%~D PCH_LCD_CLK RV2 1 2 2.2K_0402_5%~D PCH_LCD_DATA 1 1 RH142 1 RH149 1 RH153 1 RH156 1 RH158 1 RH123 1 R1697 S 2 1 DSWODVREN QH11A DMN66D0LDW-7_SOT363-6~D RH148 R1696 2 QH11B DMN66D0LDW-7_SOT363-6~D 4 2 3 2 6 14,41,44,50 ACIN D +RTCVCC +3VS 2 R1899 10K_0402_5% @ RH151 330K_0402_5% A 28 GPIO30 RH143 1 2 10K_0402_5%~D RI# RH145 1 2 10K_0402_5%~D WAKE# RH146 1 GPIO30 RH154 1 2 1K_0402_5%~D @ 2 10K_0402_5%~D 1 +3V_PCH BATLOW# PM_CLKRUN# PM_CLKRUN# 10K_0402_5%~D 2 TMDS_B_HPD 110K_0402_1%~D 2 PCH_CRT_BLU 150_0402_1% 2 PCH_CRT_GRN 150_0402_1% 2 PCH_CRT_RED 150_0402_1% 2 PCH_ENVDD 100K_0402_5%~D 2 IGPU_BKLT_EN 100K_0402_5%~D 2 PCH_RSMRST# 10K_0402_5%~D 2 A * :: DSWODVREN - On Die DSW VR Enable H Enable L Disable DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title PCH (3/8) DMI,FDI,PM,GFX,DP Size 4 3 2 Rev 1.0 LA-6601P Date: 5 Document Number Tuesday, November 30, 2010 Sheet 1 17 of 63 5 4 3 2 1 C 23,25,26,27,28 DGPU_SELECT# 47 DGPU_PWR_EN 38 DMC_RADIO_OFF# 26 HDMI_IN_PWMSEL# 38 WL_OFF# 37 FFS_INT1 37 ODD_DA# 29 DP_CBL_DET 38 BT_ON# PAD~D CLK_PCI_LPBACK CLK_PCI_LPC RH164 RH165 2 1 PAD~D PAD~D PAD~D TP21 TP22 TP23 TP24 BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40 PIRQA# PIRQB# PIRQC# PIRQD# DGPU_HOLD_RST# DGPU_SELECT# DGPU_PWR_EN C46 C44 E40 REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 DMC_RADIO_OFF# HDMI_IN_PWMSEL# WL_OFF# D47 E42 F46 GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 FFS_INT1 ODD_DA# DP_CBL_DET BT_ON# G42 G40 C42 D44 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 K10 PME# T123 @ 1 22_0402_5% 2 22_0402_5% T165 @ T166 @ T124 @ CLK_PCI0 CLK_PCI1 CLK_PCI2 CLK_PCI3 CLK_PCI4 C6 H49 H43 J48 K42 H40 +3VS AY7 AV7 AU3 BG4 RSVD5 RSVD6 AT10 BC8 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 RSVD23 RSVD24 AV5 AV10 RSVD25 AT8 RSVD26 RSVD27 AY5 BA2 RSVD28 RSVD29 AT12 BF3 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32 USBRBIAS# C33 USBRBIAS B33 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 A14 K20 B17 C16 L16 A16 D14 C14 PCI K40 K38 H38 G38 RSVD1 RSVD2 RSVD3 RSVD4 Intel Anti-Theft Techonlogy High=Endabled NV_ALE Low=Disable(floating) D * +1.8VS NV_ALE @ RH160 1 2 1K_0402_5%~D NV_ALE USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9 40 40 40 40 24 24 26 26 38 38 38 38 41 41 46 46 38 38 40 40 USB/B USB/B eDP Camera C LVDS Camera Mini Card(WLAN) Mini Card(Mini2) ELC LED IR sensor Bluetooth USB/ESATA Conn. Within 500 mils +3V_PCH PLTRST# CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 USBRBIAS RH163 1 2 22.6_0402_1% RPH1 USB_OC0# USB_OC2# USB3_SMI# USB_OC5# USB_OC0# USB_OC1# 1.5VDDR_VID0 1.5VDDR_VID1 USB_OC2# USB_OC5# USB_OC6# USB3_SMI# USB_OC0# 40 USB_OC1# 40 1.5VDDR_VID0 54 1.5VDDR_VID1 54 USB_OC2# 40 USB3_SMI# 4 3 2 1 (For USB Port 0) (For USB Port 1) USB_OC1# 1.5VDDR_VID0 1.5VDDR_VID1 USB_OC6# (For USB Port 9) 39 5 6 7 8 10K_1206_8P4R_5%~D RPH2 4 5 3 6 2 7 1 8 B 10K_1206_8P4R_5%~D CougarPoint_Rev_1p0 RPH3 +3VS WL_OFF# PCI_PIRQB# PCI_PIRQD# PCI_PIRQC# HDMI_IN_PWMSEL# PCI_PIRQA# 2 4 14 PLTRST_VGA# ODD_DA# P UH5 SN74AHC1G08DCKR_SC70-5 5 2 PCH_PLTRST# B 2 DGPU_HOLD_RST# G 1 2 O A 1 PCH_PLTRST# Y UH6 NC7SZ08P5X_NL_SC70-5 2 1 2 3 4 1 IN2 .1U_0402_16V7K~D R28 100K_0402_5%~D RPH4 8 7 6 5 IN1 C1806 2 1 @ 3 8.2K_8P4R_5% +3VS 1 .1U_0402_16V7K~D 5 4 PLT_RST# 1 5,33,35,38,39,44 RH171 100K_0402_5%~D 1 DMC_RADIO_OFF# BT_ON# 2 DGPU_SELECT# 3 FFS_INT1 4 8 7 6 5 2 1 1 RPH5 P 8.2K_8P4R_5% +3V_MXM C1805 G 2 +3VS RH170 100K_0402_5%~D 1 2 3 4 @ RH169 10K_0402_5%~D 8 7 6 5 3 16 CLK_PCI_LPBACK 44 CLK_PCI_LPC B21 M20 AY16 BG46 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCH_PLTRST# B TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 USB D BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45 RSVD UH1E 8.2K_8P4R_5% A A RH173 2 @ 1DGPU_HOLD_RST# 10K_0402_5%~D DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title PCH (4/8) PCI, USB, NVRAM Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 18 of 63 5 4 3 2 1 2 +3VS RH198 10K_0402_5%~D D CRT_DET# QH5 SSM3K7002F_SC59-3~D D S CRT_DET 23,26,28 GPIO28 DGPU_EDIDSEL# 28 DGPU_HPD_INT# On-Die PLL Voltage Regulator This signal has a weak internal pull up :: On-Die voltage regulator enable *HL On-Die PLL Voltage Regulator disable @ RH177 1 2 DMI Termination Voltage UH1F 3 44 EC_SCI# 44 EC_SMI# 38 BT_RADIO_DIS# PCH_GPIO28 1K_0402_5%~D T7 BMBUSY# / GPIO0 DGPU_EDIDSEL# A42 TACH1 / GPIO1 DGPU_HPD_INT# H36 TACH2 / GPIO6 EC_SCI# E38 TACH3 / GPIO7 EC_SMI# C10 GPIO8 C40 DGPU_BKL_PWM_SEL# TACH5 / GPIO69 B41 EDP_CAB_DET# TACH6 / GPIO70 C41 LVDS_CAB_DET# TACH7 / GPIO71 A40 TACH4 / GPIO68 C4 LAN_PHY_PWR_CTRL / GPIO12 PCH_GPIO15 G2 GPIO15 PCH_GPIO16 U2 A20GATE P5 AY11 H_CPUPWRGD THRMTRIP# AY10 H_THERMTRIP#_C ODD_EN# E8 GPIO24 / MEM_LED PCH_GPIO27 T14 INIT3_3V# AY1 NV_CLE E16 GPIO27 PCH_GPIO28 P8 GPIO28 K1 STP_PCI# / GPIO34 STP_PCI# RH181 @ 1K_0402_5%~D 1 37 ODD_DETECT# K4 GPIO35 ODD_DETECT# V8 SATA2GP / GPIO36 PCH_GPIO37 M5 SATA3GP / GPIO37 VGA_PRSNT_R# N2 VGA_PRSNT_L# M3 PCH_GPIO37 1 14 VGA_PRSNT_R# 14 VGA_PRSNT_L# 37 FFS_INT2 2 RH182 10K_0402_5%~D 36 HDD2_DETECT# GPIO27 * FFS_INT2 V13 GPIO49 V3 HDD2_DETECT# VSS_NCTF_1 PCH_GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable Low: VCCVRM VR Disable @ RH186 1 2 PCH_GPIO27 10K_0402_5%~D When Used as SATA2GP/SATA3GP for Mechanical Presence detect - Use a weak external pull-up (150K-200K ohms) to Vcc3_3 * check list Rev 1.0 +3VS RH255 2 1 ODD_DETECT# 200K_0402_5% A4 Weak internal PU,Do not pull low+1.8VS DF_TVS 2 RH175 TS_VSS1 AH8 TS_VSS2 AK11 TS_VSS3 AH10 TS_VSS4 AK10 5,44 KB_RST# 1 NC_1 P37 VSS_NCTF_15 BG2 VSS_NCTF_15 VSS_NCTF_16 BG48 VSS_NCTF_16 VSS_NCTF_17 BH3 VSS_NCTF_17 VSS_NCTF_18 BH47 VSS_NCTF_18 VSS_NCTF_19 SLOAD / GPIO38 SATA5GP / GPIO49 GPIO57 VSS_NCTF_1 VSS_NCTF_19 BJ4 H_SNB_IVB# RH162 H_THRMTRIP# 5 +3VS INIT3_3V This signal has weak internal PU, can't pull low DGPU_HPD_INT# RH179 1 2 10K_0402_5%~D DGPU_EDIDSEL# RH180 1 2 10K_0402_5%~D VGA_PRSNT_L# RH183 1 2 10K_0402_5%~D VGA_PRSNT_R# RH184 1 2 10K_0402_5%~D CRT_DET# RH192 1 2 10K_0402_5%~D @ RH194 1 2 10K_0402_5%~D STP_PCI# RH195 1 2 10K_0402_5%~D KB_RST# RH196 1 2 10K_0402_5%~D PCH_GPIO22 RH197 1 2 10K_0402_5%~D GPIO49 RH229 1 2 10K_0402_5%~D LVDS_CAB_DET# RH251 1 2 10K_0402_5%~D GATEA20 RH174 1 2 10K_0402_5%~D PCH_GPIO16 A44 VSS_NCTF_2 VSS_NCTF_20 BJ44 VSS_NCTF_20 VSS_NCTF_3 A45 VSS_NCTF_3 VSS_NCTF_21 BJ45 VSS_NCTF_21 VSS_NCTF_4 A46 VSS_NCTF_4 VSS_NCTF_22 BJ46 VSS_NCTF_22 VSS_NCTF_5 A5 VSS_NCTF_5 VSS_NCTF_23 BJ5 VSS_NCTF_23 VSS_NCTF_6 A6 VSS_NCTF_6 VSS_NCTF_24 BJ6 VSS_NCTF_24 VSS_NCTF_7 B3 VSS_NCTF_25 C2 VSS_NCTF_25 ODD_EN# RH187 1 2 10K_0402_5%~D VSS_NCTF_8 B47 VSS_NCTF_8 VSS_NCTF_26 C48 VSS_NCTF_26 HDD2_DETECT# RH188 1 2 10K_0402_5%~D VSS_NCTF_9 BD1 VSS_NCTF_9 VSS_NCTF_27 D1 VSS_NCTF_27 PCH_GPIO15 RH189 1 2 1K_0402_5%~D VSS_NCTF_10 BD49 VSS_NCTF_10 VSS_NCTF_28 D49 VSS_NCTF_28 EC_SMI# RH190 1 2 10K_0402_5%~D VSS_NCTF_11 BE1 VSS_NCTF_11 VSS_NCTF_29 E1 VSS_NCTF_29 VSS_NCTF_12 BE49 VSS_NCTF_12 VSS_NCTF_30 E49 VSS_NCTF_30 VSS_NCTF_13 BF1 VSS_NCTF_13 VSS_NCTF_31 F1 VSS_NCTF_31 VSS_NCTF_14 BF49 VSS_NCTF_14 VSS_NCTF_32 F49 VSS_NCTF_32 VSS_NCTF_7 5 5 2 RH176 SDATAOUT0 / GPIO39 SDATAOUT1 / GPIO48 1 CLOSE TO THE BRANCHING POINT 44 H_CPUPWRGD 390_0402_5% NV_CLE 2 1K_0402_5%~D 44 H_PECI VSS_NCTF_2 B SATA2GP/GPIO36 D6 INIT3_3V# @ 1 SCLOCK / GPIO22 26 2 +3VS T5 CPU/MISC to same voltage (DC Coupling Mode) ODD_EN# 2 C 37 PCH_GPIO22 AU16 @ RH178 10K_0402_5%~D *LOW - Tx, Rx terminated TACH0 / GPIO17 23,24 LVDS_CAB_DET# GATEA20 PROCPWRGD SATA4GP / GPIO16 GPIO FDI TERMINATION VOLTAGE OVERRIDE D40 P4 PCH_PECI_R 1 0_0402_5%~D KB_RST# PECI NCTF PCH_GPIO37 DGPU_PWROK EDP_CAB_DET# Set to Vcc when HIGH NV_CLE Set to Vss when LOW 26 RH161 2.2K_0402_5%~D BT_RADIO_DIS# RCIN# 14 DGPU_PWROK DGPU_BKL_PWM_SEL# 1 27 D 1 2 G 2 CRT_DET 1 High: CRT Plugged C +3V_PCH B CougarPoint_Rev_1p0 Layout note: Trace wide 10mil & length 30mil All NCTF pins should have thick traces at 45°from the pad. A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title PCH (5/8) GPIO, CPU, MISC Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 19 of 63 5 4 3 +1.05VS_VCCDPLLEXP AN19 +VCCAPLLEXP 2 C AN16 AN17 AN21 AN26 AN27 +1.05VS +1.05VS_VCC_EXP 2 0_0805_5% 1 2 VCCIO[20] VCCIO[21] AP24 VCCIO[23] AT24 VCCIO[24] AN34 BH29 +VCCAFDI_VRM +1.05VS_VCCAPLL_FDI B @ 1 Place CH64 Near BG6 pin 2 60mA VCCTX_LVDS[3] AP36 VCCTX_LVDS[4] AP37 CRT LVDS 1 2 +3VS_VCC3_3_6 V33 1 2 VCC3_3[6] 1 V34 VCC3_3[7] 2 VCCVRM[3] VCCDMI[1] 1 RH202 2 0_0805_5% AT16 +VCCAFDI_VRM 1 AT20 +VCCP_VCCDMI 2 +3VS 0_0805_5% 1 1 2 +1.05VS 100NH_HK1608R10J-T_5%_0603~D 2 1 2 VCCDFTERM[1] CH42 1U_0402_6.3V6K~D VCC3_3[3] 190mAVCCDFTERM[2] Vcc3_3 3.3 0.266 VccADAC 3.3 0.001 VccADPLLA 1.05 0.08 VccADPLLB 1.05 0.08 VccCore 1.05 1.3 VccDMI 1.05 0.042 VccIO 1.05 2.925 VccASW 1.05 1.01 VccSPI 3.3 0.02 VccDSW 3.3 0.003 VccpNAND 1.8 0.19 VccRTC 3.3 6 uA 3.3 0.119 CH43 1U_0402_6.3V6K~D +1.8VS AG16 0.001 2 RH204 1 VCCIO[26] 5 C +1.05VS_VCC_DMI_CCI AB36 0.001 V5REF_Sus +1.05VS LH11 20mA VCCCLKDMI 0.001 5 0.1uH inductor, 200mA +VCCP_VCCDMI VCCIO[25] CH44 0.1U_0402_10V7K~D 1 0_0603_5%~D AM38 VCCTX_LVDS[2] 1.05 V5REF +VCCPNAND VccSus3_3 +3VS_VCCA3GBG CH46 1U_0402_6.3V6K~D 2 @ RH208 2925mA VCCIO[22] AP26 AN33 VCCTX_LVDS[1] LH2 2 1 0.1UH_MLF1608DR10KT_10%~D +VCCTX_LVDS AM37 VCCIO[18] AP23 +1.05VS AP16 BG6 2+1.05VS_VCCDPLL_FDI AP17 0_0805_5% 1 RH209 AU20 +VCCP_VCCDMI VCCVRM[2] VccAFDIPLL VCCIO[27] VCCDMI[2] Voltage S0 Iccmax Current (A) RH199 2 +1.8VS VCCIO[17] VCCIO[19] Voltage Rail 0_0805_5% AG17 AJ16 VCCDFTERM[3] 1 AJ17 VCCDFTERM[4] V1 20mA VCCSPI 2 +3V_VCCPSPI 1 2 RH207 CH45 0.1U_0402_10V7K~D 2 VCCIO[16] AP21 1 +1.05VS VCCIO[15] D PCH Power Rail Table V_PROC_IO 1 VCCAPLLEXP FDI 2 2 1 CH41 1U_0402_6.3V6K~D 2 1 CH40 1U_0402_6.3V6K~D 2 1 CH39 1U_0402_6.3V6K~D RH206 0_0805_5% 1 CH38 1U_0402_6.3V6K~D 2 +3VS CH37 10U_0805_4VAM~D 1 2 AK37 VSSALVDS DFT / SPI RH2031 +VCCA_LVDS 0_0805_5% AK36 1mA VCCALVDS HVCMOS Place CH35 Near BJ22 pin BJ22 VCCIO 1 1 CH36 0.1U_0402_10V7K~D 2 @ LH3 1UH_LB2012T1R0M_20%~D CH35 10U_0805_4VAM~D 0_0603_5%~D 2 VCCIO[28] @ 1 +VCCAPLLEXP_R1 2 @ RH201 2 1 CH34 22U_0805_6.3VAM~D 1 0_0603_5%~D VSSADAC U47 +VCCADAC CH33 0.01U_0402_16V7K~D RH200 2 +1.05VS U48 CH32 0.01U_0402_16V7K~D +1.05VS VCCADAC +3VS DMI 2 1mA VCC CORE 1 VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17] 1 +3VS LH1 2 1 BLM18PG181SN1_0603~D CH31 10U_0805_4VAM~D 2 CH26 1U_0402_6.3V6K~D 2 1 CH25 1U_0402_6.3V6K~D 2 1 CH28 1U_0402_6.3V6K~D CH27 10U_0805_4VAM~D 1 PAD-OPEN 4x4m AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31 CH30 0.1U_0402_10V7K~D +1.05VS_VCCCORE 1 CH29 0.01U_0402_16V7K~D 2 1 1300mA J10 @ D POWER UH1G +1.05VS 2 1 RH210 2 0_0805_5% 2 3.3 / 1.5 0.01 VccVRM 1.8 / 1.5 0.16 VccCLKDMI 1.05 0.02 VccSSC 1.05 0.095 VccDIFFCLKN 1.05 0.055 VccALVDS 3.3 0.001 VccTX_LVDS 1.8 0.06 B +3V_PCH 1 CougarPoint_Rev_1p0 VccSusHDA CH47 1U_0402_6.3V6K~D +3VALW C432 1U_0402_6.3V6K~D 1 3 2 9,44,47,52,53,54 SUSP# +1.5VS SUSP# 1 +VCCAFDI_VRM @ RH211 2 U47 VIN EN VOUT NC GND RH212 2 5 4 2 1 0_0603_5%~D +VCCAFDI_VRM 1 0_0603_5%~D RT9013-15GB_SOT23-5 A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title PCH (6/8) PWR Size 4 3 2 Rev 1.0 LA-6601P Date: 5 Document Number Tuesday, November 30, 2010 Sheet 1 20 of 63 5 4 3 2 1 +1.05VS AA21 D S +1.05VM_VCCASW AA27 AA29 AA31 AC26 C 2 1 2 CH62 1U_0402_6.3V6K~D 2 1 CH61 1U_0402_6.3V6K~D 1 CH60 1U_0402_6.3V6K~D 2 0_0805_5% 2 AA26 AC27 AC29 AC31 AD29 +3VS LH5 10UH_LBR2012T100M_20%~D +3VS_VCC_CLKF33_R 1 2+3VS_VCC_CLKF33 1 VCCASW[2] VCCASW[4] VCCASW[5] VCCASW[6] VCCASW[7] VCCASW[8] VCCASW[9] VCCASW[10] VCCASW[11] VCCASW[12] VCCASW[14] W23 VCCASW[15] W24 VCCASW[16] W33 1mA V5REF_SUS VCCASW[3] VCCASW[13] W31 VCCIO[34] 1010mA W21 W29 P24 VCCASW[1] AD31 W26 V24 VCCSUS3_3[6] DCPSUS[4] VCCSUS3_3[1] +VCCRTCEXT 2 +VCCDIFFCLK +VCCDIFFCLK 1 +1.05VS_SSCVCC 1 2 +1.05VS 1 CH77 1U_0402_6.3V6K~D 2 VCCASW[19] VCC3_3[8] VCC3_3[4] T34 2 2 2 RH226 1 0_0603_5%~D VCCVRM[4] VCCIO[13] VCCADPLLA 80mA VCCADPLLB 80mA VCCIO[6] VCCAPLLSATA VCCVRM[1] VCCIO[7] VCCDIFFCLKN[1] 55mA VCCDIFFCLKN[2] VCCDIFFCLKN[3] VCCSSC T17 V19 DCPSUS[1] DCPSUS[2] 0_0805_5% +3VS 2 AF13 CH69 0.1U_0402_10V7K~D 1 RH233 0_0805_5% +1.05VS @ LH6 10UH_LBR2012T100M_20%~D 1 2 +VCCSATAPLL_R +VCCSATAPLL +VCCAFDI_VRM 1 +1.05VS_VCC_SATA +1.05VS @ RH236 0_0805_5% 2 1 1 @ +1.05VS @ CH73 10U_0805_10V4Z~D B VCCIO[2] VCCIO[4] AC16 AC17 1 AD17 2 1 RH238 0_0805_5% +1.05VS V_PROC_IO 1mA VCCASW[22] VCCASW[23] VCCASW[21] T21 +VCCME_22 RH240 2 1 0_0603_5%~D V21 +VCCME_23 RH241 2 1 0_0603_5%~D T19 +VCCME_21 RH243 2 1 0_0603_5%~D +RTCVCC 2 1 2 1 2 A22 VCCRTC CougarPoint_Rev_1p0 10mA VCCSUSHDA +VCCSUSHDA P32 1 2 CH85 0.1U_0402_10V7K~D 1 +1.05VS_VCCA_A_DPL 2 0_0603_5%~D 1 RH244 +3V_PCH RH246 @ 150_0402_1% A +1.05VS_VCCA_B_DPL + 2 1 2 CH89 1U_0402_6.3V6K~D 2 1 CH88 220U_B2_2.5VM_R35M~D 2 1 CH87 1U_0402_6.3V6K~D + CH86 220U_B2_2.5VM_R35M~D 1 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title PCH (7/8) PWR Size 4 3 2 Document Number Rev 1.0 LA-6601P Date: 5 2 CH70 1U_0402_6.3V6K~D AF14 AF11 2 +VCCA_USBSUS 2 2 CH64 1U_0603_10V6K~D 1 1 +1.05VS_SATA3 AK1 2 CH68 0.1U_0402_10V7K~D AH13 AH14 1 0_0603_5%~D RH231 +PCH_V5REF_RUN 1 +1.05VS_SATA3 1 C DH3 RB751S40T1_SOD523-2~D +3VS 2 RH232 0_0603_5%~D 2 1 +3VS 1 +3VS_VCCPPCI +VCC3_3_2 CH56 0.1U_0402_10V7K~D RH227 10_0402_5%~D CH65 0.1U_0402_10V7K~D 2 +PCH_V5REF_SUS 2 95mA DCPSST +5VS +3V_PCH +3VS +3VS_VCCPCORE 2 RH228 1 1 AJ2 DH2 RB751S40T1_SOD523-2~D 1 2 2 DCPRTC RH222 10_0402_5%~D +3V_PCH CH63 1U_0402_6.3V6K~D P22 W16 VCCASW[20] V16 BJ8 CH84 1U_0402_6.3V6K~D LH7 10UH_LBR2012T100M_20%~D 1 2 LH8 10UH_LBR2012T100M_20%~D 1 2 2 1 @ CH83 0.1U_0402_10V7K~D CH79 4.7U_0603_6.3V6K~D P20 AA16 VCC3_3[2] +1.05VS +3V_PCH +1.05VM_VCCSUS CH82 0.1U_0402_10V7K~D +VCCA_DPLL_L 2 CH81 0.1U_0402_10V7K~D 2 2 RH247 0_0805_5% 1 CH80 0.1U_0402_10V7K~D 1 1 +3V_VCCPSUS 1 2 +VCCSST +V_CPU_IO 1 RH242 2 0_0603_5%~D 1 AG33 +PCH_V5REF_RUN N22 VCC3_3[1] VCCIO[3] CH76 1U_0402_6.3V6K~D 2 RH239 1 0_0603_5%~D AF17 AF33 AF34 AG34 +1.05VS_VCCDIFFCLKN CH78 0.1U_0402_10V7K~D 2 +1.05VS +1.05VS BF47 1 0_0603_5%~D 1 CH75 1U_0402_6.3V6K~D 2 RH237 1 0_0603_5%~D CH74 1U_0402_6.3V6K~D 2 A +1.05VS_VCCA_B_DPL CH72 +1.05VS_VCCDIFFCLKN 1U_0402_6.3V6K~D AN24 +3V_VCCPSUS_1 N20 VCCSUS3_3[5] MISC +1.05VS BD47 +VCCA_USBSUS VCCSUS3_3[2] VCCSUS3_3[4] HDA 1 B +1.05VS_VCCA_A_DPL AN23 VCCASW[18] CPU 2 RH235 1 0_0603_5%~D Y49 2 RH223 2 RH224 1 0_0603_5%~D P34 VCCIO[12] +VCCAFDI_VRM +PCH_V5REF_SUS VCCASW[17] RTC +1.05VS N16 M26 1mA V5REF VCCSUS3_3[3] SATA +1.05VM_VCCSUS 1 0_0603_5%~D 2 @ RH234 CH71 0.1U_0402_10V7K~D 1 T26 2 47 PCH_PWR_EN# +5V_PCH 2 VCCIO[5] +1.05VS 2 +1.05VS_VCCAUPLL 1 0_0603_5%~D D CH55 1U_0402_6.3V6K~D 2 CH67 1U_0402_6.3V6K~D 2 CH66 10U_0805_10V4Z~D 1 VCCSUS3_3[10] 2 +3V_VCCAUBG 2 RH218 1 CH59 0.1U_0402_10V7K~D 2 +1.05VS 1 CH58 22U_0805_6.3V6M~D 44 PCH_VREG_EN# CH57 22U_0805_6.3V6M~D G 1 2 AA24 V23 1 2 AA19 2 1 0_0603_5%~D +3V_PCH 1 2 DCPSUS[3] VCCSUS3_3[9] T24 +5V_PCH 1 2 AL24 CH54 @ 1U_0402_6.3V6K~D VCCSUS3_3[8] VCCIO[14] 3 1 +VCCSUS1 1 VCCAPLLDMI2 2 RH217 1 AL29 QH7 AO3413_SOT23-3~D +5VALW_PCH 1 BH23 +VCCDPLL_CPY USB +VCCAPLL_CPY_PCH +3V_VCCPUSB 1 RH215 0_0603_5%~D 2 1 2 119mA VCCSUS3_3[7] T23 +5VALW +3V_PCH 2 T29 PCI/GPIO/LPC 2 0_0603_5%~D 1 RH230 0_0805_5% 1 2 VCCIO[33] 2 VCC3_3[5] Clock and Miscellaneous @ 1 RH219 2 1 RH225 T27 R22 20K_0402_5%~D T38 P28 VCCIO[32] C8 0.1U_0402_10V7K~D +3VS_VCC_CLKF33 VCCIO[31] G 3 DCPSUSBYP 2 +3V_DSW @ QH6 AO3413_SOT23-3~D V12 1 D @ CH90 0.1U_0402_10V7K~D P26 CH53 0.1U_0402_10V7K~D +3VALW +PCH_VCCDSW 1 N26 VCCIO[30] CH52 0.1U_0402_10V7K~D CH49 10U_0805_10V4Z~D 1 @ RH216 VCCDSW3_3 3mA 1 0_0603_5%~D S D @ LH4 @LH4 10UH_LBR2012T100M_20%~D 2 +VCCAPLL_CPY 1 2 0_0805_5% 1 +1.05VS VCCIO[29] VCCACLK T16 2 RH220 1 2 +1.05VS AD49 +VCCPDSW +1.05VS_VCCUSBCORE 2 1 POWER UH1J CH50 1U_0402_6.3V6K~D 2 0_0603_5%~D 2 0_0603_5%~D CH48 0.1U_0402_10V7K~D 1 RH245 1 @ RH221 +1.05VS +VCCACLK 1 0_0603_5%~D 2 @ RH213 +3V_PCH +3V_DSW Tuesday, November 30, 2010 Sheet 1 21 of 63 5 4 3 2 1 UH1I AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3 UH1H D H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3 C B VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28 CougarPoint_Rev_1p0 A VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28 VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] D C B A CougarPoint_Rev_1p0 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title PCH (8/8) VSS Size 4 3 2 Rev 1.0 LA-6601P Date: 5 Document Number Tuesday, November 30, 2010 Sheet 1 22 of 63 5 4 3 2 1 D D 1 2 C374 0.1U_0402_16V4Z~D 2 C372 0.1U_0402_16V4Z~D 1 +3VS CPU & MXM SW for EDP 2 1 4.7K_0402_1%~D DP_IN3_AEQ# @ R1720 2 1 4.7K_0402_1%~D DP_IN4_AEQ# U130 54 31 49 50 3 51 VDD VDD SW_AUX OUT_AUXp_SCL OUT_AUXn_SDA IN2_PEQ/SDA_CTL IN1_PEQ/SCL_CTL IN1_AEQ# IN2_AEQ# AC_AUXp AC_AUXn 47 DGPU_EDIDSEL# EDP_AUXP_L EDP_AUXN_L 28 27 30 29 EDP_AUXP_L 24 EDP_AUXN_L 24 C437 2 C438 2 EDP_AUXP_L_C EDP_AUXN_L_C INy_AEQ# (y=1, 2),Automatic RX equalization enable L:Disable input automatic equalization H:Enable input automatic equalization 19,26,28 1 0.1U_0402_10V6K~D 1 0.1U_0402_10V6K~D +3VS +3VS 2 DP_IN3_PEQ# DP_IN4_PEQ# DP_IN3_AEQ# DP_IN4_AEQ# @ R1721 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 C375 C376 C377 C378 C379 C380 C381 C382 EDP_C_TX0P EDP_C_TX0N EDP_C_TX1P EDP_C_TX1N EDP_C_TX2P EDP_C_TX2N EDP_C_TX3P EDP_C_TX3N 7 8 10 11 13 14 15 16 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 2 2 1 C435 1 C436 EDP_AUXP_C EDP_AUXN_C 26 25 22 21 OUT_D0p OUT_D0n OUT_D1p OUT_D1n OUT2_D2p OUT2_D2n OUT_D3p OUT_D3n IN1_AUXp IN1_AUXn IN1_SCL IN1_SDA IN2_D0p IN2_D0n IN2_D1p IN2_D1n IN2_D2p IN2_D2n IN2_D3p IN2_D3n SW_ML/I2C_ADDR CFG_HPD OUT_HPD REXT CEXT IN1_HPD IN2_HPD GND GND Epad PD EDP_CAB_DET# 42 41 39 38 36 35 33 32 LV_DP_A0P LV_DP_A0N LV_DP_A1P LV_DP_A1N LV_DP_A2P LV_DP_A2N LV_DP_A3P LV_DP_A3N 48 DGPU_SELECT# 46 43 CFG_HPD_1 LV_DP_HPD 45 12 57 40 PS8321QFN56GTR-A0_QFN56_7X7 MXM_DPB_AUXP/DDC 1 19,24 DGPU_SELECT# LV_DP_HPD 24 24 24 24 24 24 24 24 24 +3VS R1716 @ 4.7K_0402_1%~D 1 1 DP_MXM_CARD_SEL 1 Q277A DMN66D0LDW-7_SOT363-6~D R1719 4.7K_0402_1%~D 3 4 CFG_HPD_1 R1718 @ 4.7K_0402_1%~D 5 NVDIA 0 ATI 1 Q277B DMN66D0LDW-7_SOT363-6~D 2 MXM_MFG_SEL GPU Source G S R1717 4.7K_0402_1%~D 29,44 1 2 2 B +3VS CFG_OUTPUT_1 G S D R1713 @ 4.7K_0402_1%~D CFG_OUTPUT: output configuration L:Output is tracking DPCD register setting (auto interception) H:Output swing level fixed at 600mV and no pre-emphasis M:Output swing level is fixed at 400mV and no pre-emphasis 6 2 D C DP_IN4_PEQ# INy_PEQ(y = 1, 2),Programmable input equalization level setting L:Low EQ setting (LEQ), default H:High EQ setting (HEQ) M:No EQ 18,25,26,27,28 R530 100K_0402_5%~D R508 100K_0402_5%~D DP_IN3_PEQ# R1722 @ 4.7K_0402_1%~D 1 MXM_DPB_AUXN/DDC LV_DP_A0P LV_DP_A0N LV_DP_A1P LV_DP_A1N LV_DP_A2P LV_DP_A2N LV_DP_A3P LV_DP_A3N 18 17 2 B EDP_CAB_DET# R1715 @ 4.7K_0402_1%~D 1 44 R1733 4.99K_0402_1% IN2_AUXp IN2_AUXn IN2_SCL IN2_SDA CFG_OUTPUT_1 1 CA_DET R1712 @ 4.7K_0402_1%~D 34 C1802 2.2U_0402_6.3V6M~D 6 9 14 MXM_DPB_HPD 4 EDP_HPD# CFG_OUTPUT 2 MXM_DPB_AUXP/DDC_C 24 MXM_DPB_AUXN/DDC_C 23 20 19 IN1_D0p IN1_D0n IN1_D1p IN1_D1n IN1_D2p IN1_D2n IN1_D3p IN1_D3n 1 1 1 52 53 55 56 1 2 4 5 1 C371 2 C373 2 MXM_C_TX0P MXM_C_TX0N MXM_C_TX1P MXM_C_TX1N MXM_C_TX2P MXM_C_TX2N MXM_C_TX3P MXM_C_TX3N 2 EDP_AUXP EDP_AUXN C176 C174 C171 C175 C172 C177 C170 C173 1 4 4 1 1 1 1 1 1 1 1 2 CPU EDP_TX0P EDP_TX0N EDP_TX1P EDP_TX1N EDP_TX2P EDP_TX2N EDP_TX3P EDP_TX3N 2 2 2 2 2 2 2 2 1 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 14 MXM_DPB_AUXP/DDC 14 MXM_DPB_AUXN/DDC 4 4 4 4 4 4 4 4 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 2 MXM_TX0P MXM_TX0N MXM_TX1P MXM_TX1N MXM_TX2P MXM_TX2N MXM_TX3P MXM_TX3N 2 14 14 14 14 14 14 14 14 1 MXM 37 2 C I2C_CTL_EN 2 +3VS AUX_SEL/SEL1&2 Chanel Source 0 A CPU 1 B MXM CFG_HPD,HPD switching configuration L:HPD is switched by SW_ML H:HPD is switched by SW_AUX M:HPD is switched with overlap A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title eDP SW- GPU & CPU Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 23 of 63 5 4 3 2 1 +3VS QV8 FDS4435BZ_SO8~D 5 RV37 @ S 2 DP_IN6_AEQ# R1726 @ 4.7K_0402_1%~D CFG_OUTPUT_2 1 INy_AEQ# (y=1, 2),Automatic RX equalization enable L:Disable input automatic equalization H:Enable input automatic equalization R1729 4.7K_0402_1%~D D +3VS 2 2 +3VS R1723 @ 4.7K_0402_1%~D DP_IN5_PEQ# R1732 @ 4.7K_0402_1%~D QV9B DMN66D0LDW-7_SOT363-6~D CFG_OUTPUT: output configuration L:Output is tracking DPCD register setting (auto interception) H:Output swing level fixed at 600mV and no pre-emphasis M:Output swing level is fixed at 400mV and no pre-emphasis R1725 @ 4.7K_0402_1%~D +3VS DP_IN6_PEQ# R1724 @ 4.7K_0402_1%~D R1727 4.7K_0402_1%~D CFG_HPD_2 1 2 2 2 1 D G 1 4.7K_0402_1%~D 1 RV49 2 1 3 2 @ R1730 1 1 RV36 220K_0402_1% DP_IN5_AEQ# 1 2 QV9A DMN66D0LDW-7_SOT363-6~D 2 1 4 1 2 1 2 2 4 0_0402_5%~D 26,44 EC_ENVDD 1 2 6 1 0_0402_5%~D 1 CV45 4.7U_0805_10V4Z~D S 25,26 LCDVDD_ON 2 1 2 3 1 4.7K_0402_1%~D CV46 0.1U_0603_25V7K~D G Close to JEDP1 1 CV16 4.7U_0805_10V4Z~D D RV38 47K_0402_5%~D 2 RV40 100_0402_5%~D 2 1 CV44 0.1U_0402_16V4Z~D 2 1 CV14 0.1U_0402_16V4Z~D 1 CV42 10U_0805_10V4Z~D 2 D CV41 0.1U_0402_16V4Z~D 1 8 7 6 5 2 2 +INVPWR_B+ @ R1731 1 +5VS 1 +EDPVDD +3VS W=60mils +EDPVDD 2 eDP POWER +EDPVDD Q39 FDC654P-G_SSOT-6~D G 1 PWR_SRC_ON 2 D 2 1 47K_0402_5%~D @ LV7 1 2 FBMA-L11-201209-221LMA30T_0805 DP_IN5_PEQ# DP_IN6_PEQ# DP_IN5_AEQ# DP_IN6_AEQ# FDC654P: P CHANNAL 32 32 32 32 32 32 32 32 Panel backlight power control by EC 4028 I-PEX_20505-044E-011G~D 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2 SW_AUX OUT_AUXp_SCL OUT_AUXn_SDA IN2_PEQ/SDA_CTL IN1_PEQ/SCL_CTL IN1_AEQ# IN2_AEQ# AC_AUXp AC_AUXn EDP_A0N EDP_A0P +3VS 32 32 EDP_A1N EDP_A1P R324 EDP_A2N EDP_A2P R339 EDP_A3N EDP_A3P 1 EDP_HPD 100K_0402_5%~D 2 EDP_AUX+ 100K_0402_5%~D 1 R336 23 23 23 23 23 23 23 23 2 R222 EDP_AUX+ EDP_AUX- 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D LV_DP_AUXP LV_DP_AUXN 1 EDP_CAB_DET# 100K_0402_5%~D 2 EDP_AUX100K_0402_5%~D 2 1 CPU/MXM EDP_HPD 23 23 +3VS USB20_P2 USB20_N2 LV_DP_A0P_L LV_DP_A0N_L LV_DP_A1P_L LV_DP_A1N_L LV_DP_A2P_L LV_DP_A2N_L LV_DP_A3P_L LV_DP_A3N_L LV_DP_A0P_L LV_DP_A0N_L LV_DP_A1P_L LV_DP_A1N_L LV_DP_A2P_L LV_DP_A2N_L LV_DP_A3P_L LV_DP_A3N_L 2 C439 2 C440 LV_DP_AUXP_C LV_DP_AUXN_C LV_DP_A0P LV_DP_A0N LV_DP_A1P LV_DP_A1N LV_DP_A2P LV_DP_A2N LV_DP_A3P LV_DP_A3N LV_DP_A0P LV_DP_A0N LV_DP_A1P LV_DP_A1N LV_DP_A2P LV_DP_A2N LV_DP_A3P LV_DP_A3N 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D EDP_AUXP_L EDP_AUXN_L 1 1 52 53 55 56 1 2 4 5 1 1 2 C441 2 C442 @ R328 10K_0402_5%~D DMIC_CLK DMIC0 EDP_CAB_DET# EDP_CAB_DET# 19,23 7 8 10 11 13 14 15 16 EDP_AUXP_C_L EDP_AUXN_C_L CAM_DET# DISPOFF# 26 25 22 21 6 9 32 DP_4028_HPD 23 LV_DP_HPD CFG_OUTPUT CA_DET OUT_D0p OUT_D0n OUT_D1p OUT_D1n OUT2_D2p OUT2_D2n OUT_D3p OUT_D3n IN1_AUXp IN1_AUXn IN1_SCL IN1_SDA IN2_D0p IN2_D0n IN2_D1p IN2_D1n IN2_D2p IN2_D2n IN2_D3p IN2_D3n SW_ML/I2C_ADDR CFG_HPD OUT_HPD IN2_AUXp IN2_AUXn IN2_SCL IN2_SDA REXT CEXT IN1_HPD IN2_HPD GND GND Epad PD L100 1 2 BLM18BB221SN1D_2P~D CAM_DET# DISPOFF# 24 23 20 19 I2C_CTL_EN IN1_D0p IN1_D0n IN1_D1p IN1_D1n IN1_D2p IN1_D2n IN1_D3p IN1_D3n INV_PWM C169 @ 120P_0402_50VNPO~D Chanel 0 A 1 B 18 USB20_P2 +INVPWR_B+ 2 34 CFG_OUTPUT_2 44 EDP_CAB_DET# 42 41 39 38 36 35 33 32 5 EDP_CAB_DET# 19,23 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D EDP_A0P_L EDP_A0N_L EDP_A1P_L EDP_A1N_L EDP_A2P_L EDP_A2N_L EDP_A3P_L EDP_A3N_L 48 HDMI_IN_SELECT# 46 43 CFG_HPD_2 EDP_HPD 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 C419 C418 C421 C420 C424 C422 C425 C423 EDP_A0P EDP_A0N EDP_A1P EDP_A1N EDP_A2P EDP_A2N EDP_A3P EDP_A3N USB20_P2 18 USB20_N2 USB20_N2 45 12 57 40 1 4028 CPU/MXM A 1 3 V I/O V I/O Ground V BUS 6 DMIC0 5 DELL CONFIDENTIAL/PROPRIETARY 4 V I/O V I/O IP4223CZ6_SO6~D DMIC0 26,34 Compal Electronics, Inc. +5VS DMIC_CLK DMIC_CLK Title eDP SW- 4028 & eDP CONN 26,34 Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P 4 B 18 17 2 2 1 2 0.1U_0402_10V7K~D 2 0.1U_0402_10V7K~D 37 C248 0.1U_0603_50V4Z~D Link Done 26,35,44 EDP_AUX+ EDP_AUX- C443 1 C444 1 EDP_AUX+_C EDP_AUX-_C Source D48 +EDPVDD 30 29 PS8321QFN56GTR-A0_QFN56_7X7 AUX_SEL/SEL1&2 +3VS +3VS_CAM HDMI_IN_SELECT# 28 27 2 26 16,26 26 1 47 R1734 4.99K_0402_1% CONNTST GND LANE1_N LANE1_P GND LANE0_N LANE0_P GND AUX_CH_P AUX_CH_N GND LCD_VCC LCD_VCC LCD_VCC TEST GND HPD BL_GND BL_GND BL_PWR BL_PWR BL_PWR BL_PWR BL_GND BL_GND BL_PWM SMBUS_CLK SMBUS_DATA ALS_VCC ALS_INT# GND CAM_MIC_CBL_DET# USB+ USBUSB_VCC MIC_CLK MIC_GND MIC_DAT GND PWR_LED BATT2_LED BATT1_LED GND CONNTST 49 50 3 51 1 MGND1 MGND2 MGND3 MGND4 MGND5 MGND6 MGND7 MGND8 MGND9 MGND10 MGND11 MGND12 MGND13 VDD VDD C1803 2.2U_0402_6.3V6M~D A 45 46 47 48 49 50 51 52 53 54 55 56 57 CONN@ 2 B U131 54 31 44 LCD_BKL_EN 80 mil JEDP1 2 CPU/GPU & 4028 SW for DPB 3 2 G +INVPWR_B+ 1 S Q28 SSM3K7002FU_SC70-3~D 1 R423 C 1 1 3 C331 0.1U_0603_50V4Z~D 2 2 Inverter power B+ +3VS 1 C181 0.1U_0402_16V4Z~D R422 100K_0402_5%~D CFG_HPD,HPD switching configuration L:HPD is switched by SW_ML H:HPD is switched by SW_AUX M:HPD is switched with overlap +INVPWR_B+ C179 0.1U_0402_16V4Z~D 2 C332 1000P_0402_50V7K~D 1 S 4 80 mil 6 5 2 1 D 80 mil C 2 B+ Back light power R1728 @ 4.7K_0402_1%~D INy_PEQ(y = 1, 2),Programmable input equalization level setting L:Low EQ setting (LEQ), default H:High EQ setting (HEQ) M:No EQ 3 2 Sheet 1 24 of 63 5 4 3 2 1 SEL L H STDP6038 SW STDP4028 PCH/GPU AUX for LVDS Y GPU PCH D D U46 U1 SLE1 32 LVDS_SW _TXOUT032 LVDS_SW _TXOUT0+ 26 LVDS_MUX_TXOUT026 LVDS_MUX_TXOUT0+ 32 LVDS_SW _TXOUT132 LVDS_SW _TXOUT1+ 26 LVDS_MUX_TXOUT126 LVDS_MUX_TXOUT1+ 32 LVDS_SW _TXOUT232 LVDS_SW _TXOUT2+ 26 LVDS_MUX_TXOUT226 LVDS_MUX_TXOUT2+ 32 LVDS_SW _TXCLK32 LVDS_SW _TXCLK+ C 26 LVDS_MUX_TXCLK26 LVDS_MUX_TXCLK+ STDP4028 Panel MUX 2 1 LVDS_MUX_TXOUT0LVDS_MUX_TXOUT0+ 80 79 0B2 1B2 LVDS_SW _TXOUT1LVDS_SW _TXOUT1+ 78 77 2B1 3B1 LVDS_MUX_TXOUT1LVDS_MUX_TXOUT1+ 76 75 2B2 3B2 LVDS_SW _TXOUT2LVDS_SW _TXOUT2+ 73 72 4B1 5B1 LVDS_MUX_TXOUT2LVDS_MUX_TXOUT2+ 71 70 4B2 5B2 LVDS_SW _TXCLKLVDS_SW _TXCLK+ 68 67 6B1 7B1 LVDS_MUX_TXCLKLVDS_MUX_TXCLK+ 66 65 6B2 7B2 64 63 8B1 9B1 62 61 8B2 9B2 output LVDS_SW _TZOUT0LVDS_SW _TZOUT0+ 32 LVDS_SW _TZOUT032 LVDS_SW _TZOUT0+ 26 LVDS_MUX_TZOUT026 LVDS_MUX_TZOUT0+ 32 LVDS_SW _TZOUT132 LVDS_SW _TZOUT1+ 26 LVDS_MUX_TZOUT126 LVDS_MUX_TZOUT1+ 32 LVDS_SW _TZOUT232 LVDS_SW _TZOUT2+ 26 LVDS_MUX_TZOUT226 LVDS_MUX_TZOUT2+ B LVDS_SW _TXOUT0LVDS_SW _TXOUT0+ 32 LVDS_SW _TZCLK32 LVDS_SW _TZCLK+ 26 LVDS_MUX_TZCLK26 LVDS_MUX_TZCLK+ 0B1 1B1 60 59 10B1 11B1 LVDS_MUX_TZOUT0LVDS_MUX_TZOUT0+ 58 57 10B2 11B2 LVDS_SW _TZOUT1LVDS_SW _TZOUT1+ 56 55 12B1 13B1 LVDS_MUX_TZOUT1LVDS_MUX_TZOUT1+ 54 53 12B2 13B2 LVDS_SW _TZOUT2LVDS_SW _TZOUT2+ 51 50 14B1 15B1 LVDS_MUX_TZOUT2LVDS_MUX_TZOUT2+ 49 48 14B2 15B2 LVDS_SW _TZCLKLVDS_SW _TZCLK+ 46 45 16B1 17B1 LVDS_MUX_TZCLKLVDS_MUX_TZCLK+ 44 43 16B2 17B2 42 41 18B1 19B1 40 39 18B2 19B2 A0 A1 16 5 6 EDP_DETECT# 15 LVDS_6038_TXOUT0LVDS_6038_TXOUT0+ LVDS_6038_TXOUT0- 31 LVDS_6038_TXOUT0+ 31 14 VGA_TXOUT014 VGA_TXOUT0+ 17 PCH_TXOUT017 PCH_TXOUT0+ A2 A3 8 9 LVDS_6038_TXOUT1LVDS_6038_TXOUT1+ LVDS_6038_TXOUT1- 31 LVDS_6038_TXOUT1+ 31 14 VGA_TXOUT114 VGA_TXOUT1+ 17 PCH_TXOUT117 PCH_TXOUT1+ A4 A5 11 12 LVDS_6038_TXOUT2LVDS_6038_TXOUT2+ LVDS_6038_TXOUT2- 31 LVDS_6038_TXOUT2+ 31 14 VGA_TXOUT214 VGA_TXOUT2+ 17 PCH_TXOUT217 PCH_TXOUT2+ A6 A7 14 15 LVDS_6038_TXCLKLVDS_6038_TXCLK+ LVDS_6038_TXCLK- 31 LVDS_6038_TXCLK+ 31 14 VGA_TXCLK14 VGA_TXCLK+ 17 PCH_TXCLK17 PCH_TXCLK+ A8 A9 SEL2 A10 A11 23 24 LVDS_6038_TZOUT0LVDS_6038_TZOUT0+ LVDS_6038_TZOUT0- 31 LVDS_6038_TZOUT0+ 31 14 VGA_TZOUT014 VGA_TZOUT0+ 17 PCH_TZOUT017 PCH_TZOUT0+ A12 A13 26 27 LVDS_6038_TZOUT1LVDS_6038_TZOUT1+ LVDS_6038_TZOUT1- 31 LVDS_6038_TZOUT1+ 31 14 VGA_TZOUT114 VGA_TZOUT1+ 17 PCH_TZOUT117 PCH_TZOUT1+ A14 A15 29 30 LVDS_6038_TZOUT2LVDS_6038_TZOUT2+ LVDS_6038_TZOUT2- 31 LVDS_6038_TZOUT2+ 31 14 VGA_TZOUT214 VGA_TZOUT2+ 17 PCH_TZOUT217 PCH_TZOUT2+ A16 A17 32 33 LVDS_6038_TZCLKLVDS_6038_TZCLK+ LVDS_6038_TZCLK- 31 LVDS_6038_TZCLK+ 31 14 VGA_TZCLK14 VGA_TZCLK+ 17 PCH_TZCLK17 PCH_TZCLK+ A18 A19 0B2 1B2 VGA_TXOUT1VGA_TXOUT1+ 78 77 2B1 3B1 A2 A3 8 9 SYS_TXOUT1SYS_TXOUT1+ PCH_TXOUT1PCH_TXOUT1+ 76 75 2B2 3B2 VGA_TXOUT2VGA_TXOUT2+ 73 72 4B1 5B1 A4 A5 11 12 SYS_TXOUT2SYS_TXOUT2+ PCH_TXOUT2PCH_TXOUT2+ 71 70 4B2 5B2 VGA_TXCLKVGA_TXCLK+ 68 67 6B1 7B1 A6 A7 14 15 SYS_TXCLKSYS_TXCLK+ PCH_TXCLKPCH_TXCLK+ 66 65 6B2 7B2 64 63 8B1 9B1 A8 A9 17 18 62 61 8B2 9B2 SEL2 34 VGA_TZOUT0VGA_TZOUT0+ 60 59 10B1 11B1 A10 A11 23 24 SYS_TZOUT0SYS_TZOUT0+ PCH_TZOUT0PCH_TZOUT0+ 58 57 10B2 11B2 VGA_TZOUT1VGA_TZOUT1+ 56 55 12B1 13B1 A12 A13 26 27 SYS_TZOUT1SYS_TZOUT1+ PCH_TZOUT1PCH_TZOUT1+ 54 53 12B2 13B2 VGA_TZOUT2VGA_TZOUT2+ 51 50 14B1 15B1 A14 A15 29 30 SYS_TZOUT2SYS_TZOUT2+ PCH_TZOUT2PCH_TZOUT2+ 49 48 14B2 15B2 VGA_TZCLKVGA_TZCLK+ 46 45 16B1 17B1 A16 A17 32 33 SYS_TZCLKSYS_TZCLK+ PCH_TZCLKPCH_TZCLK+ 44 43 16B2 17B2 42 41 18B1 19B1 A18 A19 35 36 40 39 18B2 19B2 3 13 20 21 31 38 52 74 25 7 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 OE2# OE1# DGPU_SELECT# 18,23,26,27,28 SYS_TXOUT0- 26 SYS_TXOUT0+ 26 SYS_TXOUT1- 26 SYS_TXOUT1+ 26 SYS_TXOUT2- 26 SYS_TXOUT2+ 26 SYS_TXCLK- 26 SYS_TXCLK+ 26 C SEL=LOW SEL=HIGH B1,GPU B2,PCH SYS_TZOUT0- 26 SYS_TZOUT0+ 26 SYS_TZOUT1- 26 SYS_TZOUT1+ 26 SYS_TZOUT2- 26 SYS_TZOUT2+ 26 B SYS_TZCLK- 26 SYS_TZCLK+ 26 +3VS 1 2 1 2 1 2 1 LCDVDD_ON RV11 100K_0402_5%~D 2 2 4 10 19 22 28 37 47 69 3 1 QV3 SSM3K7002F_SC59-3~D VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 PI3LVD1012BE_BQSOP80 4 10 19 22 28 37 47 69 1 2 1 2 1 2 CV11 4.7U_0603_6.3V6K~D 1 SYS_TXOUT0SYS_TXOUT0+ CV10 0.1U_0402_16V4Z~D 2 A0 A1 5 6 CV9 0.1U_0402_16V4Z~D VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 D QV10 SSM3K7002F_SC59-3~D GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 OE2# OE1# S 3 13 20 21 31 38 52 74 25 7 G 1 DGPU_SELECT# +3VS CV47 4.7U_0603_6.3V6K~D D S 3 80 79 +3VS CV50 0.1U_0402_16V4Z~D 2 0B1 1B1 PCH_TXOUT0PCH_TXOUT0+ 35 36 CV49 0.1U_0402_16V4Z~D G RV45 100K_0402_5%~D 2 1 STDP6038 input +3VS 24,26 LCDVDD_ON VGA_TXOUT0VGA_TXOUT0+ 17 18 34 16 SLE1 PI3LVD1012BE_BQSOP80 A A SEL L H 5 Y DELL CONFIDENTIAL/PROPRIETARY STDP4028 Panel MUX Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 4 3 2 Title LVDS SW- 1 to 2 & GPU/PCH Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 25 of 63 5 4 3 2 1 PCH/GPU MUX & 6038 MUX SW for LVDS LCD Backlight Selector 1 +3VS RV62 @ 10K_0402_5%~D 2 0_0402_5%~D HDMI_IN_PWM_SELECT# 2 0_0402_5%~D U44 0_0402_5%~D RV41 1 2 VGA_EC_PWM HDMI_IN_PWM PCH_INV_PWM 6 5 4 3 1B1 1B2 1B3 1B4 INV_PWM ENBKL 1 2 0_0402_5%~D 8 2 SN74CB3Q3253PWR_TSSOP16 25 SYS_TXOUT225 SYS_TXOUT2+ 25 LVDS_MUX_TXCLK25 LVDS_MUX_TXCLK+ 25 SYS_TXCLK25 SYS_TXCLK+ LVDS_MUX_TXOUT2LVDS_MUX_TXOUT2+ 73 72 SYS_TXOUT2SYS_TXOUT2+ 71 70 LVDS_MUX_TXCLKLVDS_MUX_TXCLK+ 68 67 SYS_TXCLKSYS_TXCLK+ 66 65 S1 LCD DDC Selector C DGPU_SELECT# B1=B3 1 B2 1 0 B1=B3 1 1 B4 VGA_LCD_CLK DHMI_IN_NV_CLK PCH_LCD_CLK 6 5 4 3 2 VGA_LCD_DAT DHMI_IN_NV_DAT PCH_LCD_DATA 10 11 12 13 1 1B1 1B2 1B3 1B4 VCC 2B1 2B2 2B3 2B4 1A 2A 2OE 1OE GND S0 S1 16 14 2 HDMI_IN_SELECT# DGPU_EDIDSEL_R# 7 9 I2CC_SCL I2CC_SDA HDMI IN (I) 25 LVDS_MUX_TZOUT025 LVDS_MUX_TZOUT0+ UMA 25 SYS_TZOUT025 SYS_TZOUT0+ 25 LVDS_MUX_TZOUT125 LVDS_MUX_TZOUT1+ 25 SYS_TZOUT125 SYS_TZOUT1+ 25 LVDS_MUX_TZOUT225 LVDS_MUX_TZOUT2+ 25 SYS_TZOUT225 SYS_TZOUT2+ 25 LVDS_MUX_TZCLK25 LVDS_MUX_TZCLK+ 15 25 SYS_TZCLK25 SYS_TZCLK+ 8 60 59 SYS_TZOUT0SYS_TZOUT0+ 58 57 LVDS_MUX_TZOUT1LVDS_MUX_TZOUT1+ 56 55 SYS_TZOUT1SYS_TZOUT1+ 54 53 LVDS_MUX_TZOUT2LVDS_MUX_TZOUT2+ 51 50 SYS_TZOUT2SYS_TZOUT2+ 49 48 LVDS_MUX_TZCLKLVDS_MUX_TZCLK+ 46 45 SYS_TZCLKSYS_TZCLK+ 44 43 42 41 SN74CB3Q3253PWR_TSSOP16 0 B1=B3 0 1 B2 1 0 B1=B3 1 1 B4 Y 40 39 DSC LCDVDD_ON RV32 100K_0402_5%~D HDMI IN (I) G 2 2 UMA 3 13 20 21 31 38 52 74 25 7 D S 3 1 QV4 SSM3K7002F_SC59-3~D 2 3 D 44 10B1 11B1 A10 A11 0_0402_5%~D 1 2 RV6 @ 2 1 5 D 2 G S 1 2 14 DGPU_ENVDD 31 HDMI_IN_ENVDD 17,44 PCH_ENVDD 10 11 12 13 1 1B1 1B2 1B3 1B4 VCC 2B1 2B2 2B3 2B4 1A 2A 2OE 1OE GND S0 S1 14 2 12B1 13B1 A12 A13 TZOUT1TZOUT1+ 26 27 1 SEL L H 12B2 13B2 14B1 15B1 A14 A15 TZOUT2TZOUT2+ 29 30 Y 2 EN_CAM control circuit 1 2 Close to JLVDS1 1 2 14B2 15B2 16B1 17B1 A16 A17 TZCLKTZCLK+ 32 33 44 BKOFF# BKOFF# 1 RV12 LVDS Conn. 16B2 17B2 2 DISPOFF# 0_0402_5%~D JLVDS1 18B1 19B1 A18 A19 35 36 18B2 19B2 +3VS GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 OE2# OE1# VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 4 10 19 22 28 37 47 69 1 2 1 2 1 2 55 54 53 52 51 50 49 48 47 46 45 GND11 GND10 GND9 GND8 GND7 GND6 GND5 GND4 GND3 GND2 GND1 +3VS CV67 0.1U_0402_16V4Z~D @ RV112 10K_0402_5%~D DGPU_SELECT# LCDVDD_ON S 2 B1 B2 LCDVDD_ON 18,23,25,27,28 24,25 15 SN74CB3Q3253PWR_TSSOP16 1 1 C HDMI_IN_SELECT# 8 2 +3VS DGPU_SELECT# 7 9 1 +LCDVDD 10B2 11B2 2 16 3 TZOUT0TZOUT0+ 23 24 1 6 5 4 3 1 2 G EN_CAM 34 2 S 2 G 1 4 1 2 RV16 5 2 QV2A DMN66D0LDW-7_SOT363-6~D RV7 100K_0402_5%~D 24,44 EC_ENVDD 1 RV5 2 1 220K_0402_1% 2 0_0402_5%~D 1 3 D 1 2 6 1 LCDVDD_ON 1 CV6 .047U_0402_16V7K~D S +3VS QV1 SI2301CDS-T1-GE3_SOT23-3~D CV4 4.7U_0805_10V4Z~D G A A8 A9 3 17 18 8B2 9B2 W=60mils U610 CV3 4.7U_0805_10V4Z~D RV4 47K_0402_5%~D D +5VALW RV3 100_0402_5%~D CV2 0.1U_0402_16V4Z~D CV1 0.1U_0402_16V4Z~D 2 1 +LCDVDD 2 8B1 9B1 +3VS +LCDVDD 1 1 6B2 7B2 PI3LVD1012BE_BQSOP80 LCD POWER 1 2 TXCLKTXCLK+ 14 15 +3VS HDMI IN (D) 1 0 A6 A7 CV33 4.7U_0603_6.3V6K~D Output 6B1 7B1 CV35 0.1U_0402_16V4Z~D S0 4B2 5B2 CV34 0.1U_0402_16V4Z~D B S1 A4 A5 +3VS_CAM Q43 SI2301CDS-T1-GE3_SOT23-3~D CV7 10U_0805_10V4Z~D 1 DGPU_EDIDSEL_R# 4B1 5B1 SEL2 LVDS_MUX_TZOUT0LVDS_MUX_TZOUT0+ TXOUT2TXOUT2+ +3VS HDMI IN (D) DSC 11 12 CV36 0.1U_0402_16V4Z~D 14 VGA_LCD_DAT 31 DHMI_IN_NV_DAT 17 PCH_LCD_DATA 0 0 62 61 +3VS U613 14 VGA_LCD_CLK 31 DHMI_IN_NV_CLK 17 PCH_LCD_CLK 0 Y CV48 0.1U_0402_16V4Z~D RV9 0_0402_5%~D 1 2 19,23,28 DGPU_EDIDSEL# Output 8 9 D CV15 0.1U_0402_16V4Z~D @ RV8 0_0402_5%~D 1 2 S0 A2 A3 2B2 3B2 Q26 SSM3K7002F_SC59-3~D 64 63 2B1 3B1 +5VS DMIC_CLK 4 V I/O V I/O IP4223CZ6_SO6~D CV5 10U_0805_10V4Z~D 1 1 RV46 17,44 SG_AMD_BKL 24 44 25 LVDS_MUX_TXOUT225 LVDS_MUX_TXOUT2+ 0B2 1B2 5 C1748 0.1U_0402_16V4Z~D 15 19 76 75 3 DMIC0 6 V I/O Ground V BUS D GND DGPU_BKL_PWM_SEL# 78 77 SYS_TXOUT1SYS_TXOUT1+ USB20_N3 TXOUT1TXOUT1+ V I/O 2 G 1OE INV_PWM ENBKL 25 SYS_TXOUT125 SYS_TXOUT1+ TXOUT0TXOUT0+ 5 6 S 1A 2A 7 9 25 LVDS_MUX_TXOUT125 LVDS_MUX_TXOUT1+ 1 R1652 100K_0402_5%~D 2OE HDMI_IN_PWM_SELECT# LVDS_MUX_TXOUT1LVDS_MUX_TXOUT1+ A0 A1 USB20_P3 C1747 0.1U_0402_16V4Z~D 2B1 2B2 2B3 2B4 14 2 RH141 100K_0402_5%~D 14 DGPU_BKL_EN 31 HDMI_IN_BKL_EN 17 IGPU_BKLT_EN S0 S1 RV48 100K_0402_5%~D 10 11 12 13 2 16 VCC 25 SYS_TXOUT025 SYS_TXOUT0+ @ RV13 10K_0402_5%~D 80 79 0B1 1B1 D49 24,35,44 2 RV42 1 SYS_TXOUT0SYS_TXOUT0+ 2 1 HDMI_IN_SELECT# 1 14 VGA_PNL_PWM 31 HDMI_IN_PWM 17 PCH_INV_PWM @ LVDS_MUX_TXOUT0LVDS_MUX_TXOUT0+ R1741 0_0402_5%~D 1 2 16 2 1 CV43 0.1U_0402_16V4Z~D D 25 LVDS_MUX_TXOUT025 LVDS_MUX_TXOUT0+ +3VS 1 1 +3VS 44 EC_INV_PWM SLE1 2 RV44 18 HDMI_IN_PWMSEL# 2 0_0402_5%~D 1 1 @ RV43 2 DGPU_SELECT# 2 U42 S1 S0 YA YB Y 0 0 A0 B0 HDMI IN 0 1 A1 B1 DSC 1 0 A2 B2 HDMI IN 1 1 A3 B3 UMA 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TXOUT0TXOUT0+ 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TXOUT1TXOUT1+ TXOUT2TXOUT2+ TXCLKTXCLK+ B TZOUT0TZOUT0+ TZOUT1TZOUT1+ TZOUT2TZOUT2+ TZCLKTZCLK+ I2CC_SCL I2CC_SDA USB20_N3 USB20_P3 LCD_TEST 18 18 CAM_DET# 16,24 DMIC_CLK 24,34 DMIC0 24,34 DISPOFF# 24 LVDS_CAB_DET# +3VS_CAM LCD_TEST 44 W=60mils +INVPWR_B+ 19 +3VS +LCDVDD B+ @ LV1 1 2 FBMA-L11-201209-221LMA30T_0805 W=80mils JAE_FI-TD44SB-E-R750_44P Link Done USB20_N3 USB20_P3 CAM_DET# DMIC_CLK DMIC0 DISPOFF# INV_PWM LVDS_CAB_DET# A DELL CONFIDENTIAL/PROPRIETARY QV2B DMN66D0LDW-7_SOT363-6~D Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 4 3 2 Title LVDS SW- 6038/SYSTEM & CONN Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 26 of 63 B C D VGA SW for PCH / GPU +3VS 0_0402_5%~D 1 6 D_DDCDATA DGPU_SELECT# 18,23,25,26,28 Q274A DMN66D0LDW-7_SOT363-6~D CRT_DDC_CLK 4 3 D_DDCCLK Q274B DMN66D0LDW-7_SOT363-6~D SEL1/SEL2 PI3V712-AZLEX_TQFN32_6X3~D Chanel Source 0 A=B1 GPU 1 A=B2 PCH 32 32 R932 1 R986 1 UART_TX UART_RX 2 0_0402_5%~D CRT_UART_TX 2 0_0402_5%~D CRT_UART_RX 1 2 CV26 100P_0402_50V8J~D 3 11 28 31 33 GND GND GND GND GPAD 1 G 2 30 SEL2 0B2 1B2 2B2 3B2 4B2 5B2 6B2 CRT_DDC_DATA RV20 1 5 CRT_DDC_DATA CRT_DDC_CLK 2 D 9 10 A5 A6 2 S DGPU_SELECT#_CRT 2 D 8 2 S SEL1 2 +3VS G 26 24 21 19 17 13 15 17 PCH_CRT_VSYNC 17 PCH_CRT_HSYNC 17 PCH_CRT_RED 17 PCH_CRT_GRN 17 PCH_CRT_BLU 17 PCH_CRT_DDC_DAT 17 PCH_CRT_DDC_CLK CRT_VSYNC CRT_HSYNC CRT_R CRT_G CRT_B 1 C15 0.01U_0402_16V7K~D 0B1 1B1 2B1 3B1 4B1 5B1 6B1 1 2 5 6 7 1 C14 0.01U_0402_16V7K~D 27 25 22 20 18 12 14 2 A0 A1 A2 A3 A4 1 C13 0.01U_0402_16V7K~D 14 VGA_CRT_VSYNC 14 VGA_CRT_HSYNC 14 VGA_CRT_R 14 VGA_CRT_G 14 VGA_CRT_B 14 VGA_DDC_DATA 14 VGA_DDC_CLK VDD VDD VDD VDD VDD 1 C12 0.1U_0402_16V4Z~D U2 4 16 23 29 32 1 C11 0.1U_0402_16V4Z~D C10 10U_0805_10V4Z~D 1 +3VS 1 E 2 A 2 2 +3VS 2 3 1 2 3 1 2 1 CRT_G 1 2 1 2 2 1 CV19 0.1U_0402_16V4Z~D 2 CRT Connector CRT_DET# JCRT1 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 CRT_UART_TX CRT_B_2 1 2 1 2 1 2 CV25 8P_0402_50V8D~D 2 2 5A_125V_R451005.MRL~D 1 2 R1961 0_1206_5%~D CRT_G_2 CV24 8P_0402_50V8D~D 2 1 @ FV1 1 1 +CRT_VCC W=40mils CRT_R_2 CV23 8P_0402_50V8D~D 2 1 CV22 8P_0402_50V8D~D 1 CV21 8P_0402_50V8D~D CV20 8P_0402_50V8D~D RV24 150_0402_1% RV23 150_0402_1% 3 RV22 150_0402_1% 1 CRT_B 2 RB491D_SC59-3 19 LV2 1 2 BLM18BB600SN1D_0603~D LV3 1 2 BLM18BB600SN1D_0603~D LV4 1 2 BLM18BB600SN1D_0603~D CRT_R +R_CRT_VCC DV5 @DV4 DAN217T146_SC59-3 @ DV3 DAN217T146_SC59-3 @DV2 DAN217T146_SC59-3 3 +5VS CRT_UART_RX 16 17 3 SUYIN_070112HR015M270ZR CONN@ Link Done D_DDCDATA +CRT_VCC 1 RV25 D_DDCCLK CV27 1 2 0.1U_0402_16V4Z~D 2 CRT_HSYNC_1 4 1 LV5 MBC1608121YZF_0603 1 2 1 CRT_HSYNC_2 G OE# 5 P UV8 Y 1 3 74AHCT1G125GW_SOT353-5 +CRT_VCC 2 P A UV9 Y 4 CRT_VSYNC_1 LV6 MBC1608121YZF_0603 1 2 CRT_VSYNC_2 74AHCT1G125GW_SOT353-5 3 4 2 1 2 CV32 10P_0402_50V8J~D 2 G CRT_VSYNC 1 5 2 0.1U_0402_16V4Z~D OE# CV30 1 2 1 CV29 68P_0402_50V8J~D A CV31 10P_0402_50V8J~D 2 10K_0402_5%~D CV28 68P_0402_50V8J~D CRT_HSYNC 1 RV26 1 RV27 +CRT_VCC 2 2.2K_0402_5%~D 2 2.2K_0402_5%~D 4 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title CRT SW Size B C D Rev 1.0 LA-6601P Date: A Document Number Tuesday, November 30, 2010 Sheet E 27 of 63 4 3 2 +3VS +5VS_SEL REXT @ 3 4 3 C_DVI_R_TXD0+ 4 C_DVI_R_TXD0- 4 2 0_0402_5%~D 2 0_0402_5%~D 1 WCM-2012-900T_4P 3 4 4 3 DVI_TXC+_R L7 2 2 1 1 DGPU_SEL# @ R40 C_DVI_R_TXCC_DVI_R_TXC+ 1 2 0_0402_5%~D C 2 0_0402_5%~D 1 DGPU_SELECT# +3VS 1 DVI_TXD2DVI_TXD2+ DVI_TXD1DVI_TXD1+ DVI_TXD0DVI_TXD0+ DVI_TXCDVI_TXC+ SEL 9 DGPU_SELECT#_R GND_PAD 43 1 0_0603_5%~D R931 1 R985 1 Y 0 A 0.01U_0402_16V7K~D DGPU_EDIDSEL#_R 4 B +HDMI_5V_OUT DVI_SDATA_R DVI_SCLK_R L8 1 L9 1 Place LC Filter closed to JHDMI1 P G 1 2 0_0402_5%~D DGPU_EDIDSEL# 1 DGPU_EDIDSEL# 19,23,26 2 GPIO30 HDMI Connector JHDMI2 2 FCM2012CF-800T06_2P 2 FCM2012CF-800T06_2P 1 2 0_0402_5%~D HDMI_UART_TX 2 0_0402_5%~D HDMI_UART_RX B 17 U624 SN74AHC1G08DCKR_SC70-5 HDMI_SINK_HPD_R 1 2 1 2 3 DGPU_SELECT# 18,23,25,26,27 GPIO30 +HDMI_5V_OUT DVI_SDATA DVI_SCLK HDMI_UART_TX HDMI_UART_RX C_DVI_R_TXCC_DVI_R_TXC+ C_DVI_R_TXD0C_DVI_R_TXD0+ C_DVI_R_TXD1- C_DVI_R_TXD2+ 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ 20 21 22 23 A Link Done SUYIN_100042GR019M23UZL CONN@ DELL CONFIDENTIAL/PROPRIETARY QV11 SSM3K7002F_SC59-3~D 2 G IN1 O IN2 pin 14 Utility / HEAC+ pin 17 DDC / CEC GND / HEAC Shield pin 19 Hot Plug Detect / HEAC- HDMI_OE# 2 CV57 2 1 SEL FOR HDMI 1.4 :TO BE UPDATE: 1 1 U623 SN74AHC1G08DCKR_SC70-5 C_DVI_R_TXD1+ C_DVI_R_TXD2R1950 100K_0402_5%~D D IN2 +3VS 2 31 UART_TX_6038 31 UART_RX_6038 O @R57 @ R57 29,30 DGPU_EDIDSEL#_R 1 +1.5VS_HDMI +VCCAFDI_VRM 2 IN1 2 DGPU_SEL# 4 30K_0402_1%~D PI3HDMI412FT-BZHE_TQFN42_9X3P5 RH254 5 0.01U_0402_16V7K~D 1 R1737 3 2 DGPU_SELECT#_R P 15 14 12 11 7 6 4 3 2 1 CV56 1 5 2 1 2 Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title HDMI SW Size 3 2 Document Number Rev 1.0 LA-6601P Date: 5 2 0_0402_5%~D DVI_TXC-_R PS121QFN48G_QFN48_7X7 2 S +5VS L6 DVI_TXD0-_R 3 3 VSS VSS VSS VSS VSS VSS VSS VSS VSS D3D3+ D2D2+ D1D1+ D0D0+ 1 1 2 D3-_A D3+_A D2-_A D2+_A D1-_A D1+_A D0-_A D0+_A 42 40 30 20 18 16 8 2 1 1 VDD VDD VDD VDD VDD VDD VDD VDD +1.5VS_HDMI 2 3 1 3 2 1 2 1 @ 2 1 2 1 2 @ R42 C30 10P_0402_50V8J~D 1 C_DVI_R_TXD1+ WCM-2012-900T_4P 1 1 DVI_TXD0+_R 2 DVI_SDATA_L DVI_SCLK_L 29 28 C29 10P_0402_50V8J~D R925 10K_0402_5%~D R33 200K_0402_5% R58 HDMI_SW_DETECT 2 0_0402_5%~D D2@ BAV99-7-F_SOT23-3 1 1 Reserve for EMI please close to JHDMI2 2 1 1 CEXT R55 2.2K_0402_5%~D R53 100K_0402_5%~D 2 B E 1 0_0402_5%~D @ R39 @ R43 R54 2.2K_0402_5%~D Q13 SSM3K7002F_SC59-3~D 1 2 G L3 MBK1608221YZF_2P HDMI_SINK_HPD 1 2 C16 220P_0402_50V7K~D @Q275 MMST3904-7-F_SOT323-3~D @ R566 200K_0402_5% 1 2 4 C_DVI_R_TXD1- 2 1 +3VS C D 4 1 @ R41 +3VS A 3 L5 DVI_TXD1+_R 2 2 I2C_ADDR0/PC0 I2C_ADDR1/PC1 5 12 18 24 27 31 36 37 43 49 2 2 2 2 2 2 GND/PC2 6 D3-_B D3+_B D2-_B D2+_B D1-_B D1+_B D0-_B D0+_B 39 41 21 19 17 13 10 5 1 C1208 .1U_0402_16V7K~D 2 C1163 10U_0603_6.3V6M~D 1 499_0402_1%~D 499_0402_1%~D 499_0402_1%~D 499_0402_1%~D 499_0402_1%~D 499_0402_1%~D 499_0402_1%~D 499_0402_1%~D 2 1 1 +1.5VS_HDMI 1 1 1 1 1 R51 R50 R49 R48 R47 R46 R45 R44 2 PC_2 1 2 2 1 1 2 1 31 32 33 34 35 36 37 38 1 2 4.7K_0402_5%~D SDAZ SCLZ R1735 680K_0402_1% HDMI_C_TX2HDMI_C_TX2+ HDMI_C_TX1HDMI_C_TX1+ HDMI_C_TX0HDMI_C_TX0+ HDMI_C_CLKHDMI_C_CLK+ S 2 0_0402_5%~D 1 WCM-2012-900T_4P HDMI_SINK_HPD 7 R1736 36K_0402_1% .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D 2 RV52 1 IN SDA_CTL/CFG1 SCL_CTL/CFG0 C17 10U_0603_6.3V6M~D 1 1 1 1 1 1 1 1 S 3 3 4 C18 .1U_0402_16V7K~D 2 2 2 2 2 2 2 2 2 G PC_0 PC_1 C19 .1U_0402_16V7K~D C20 C21 C22 C23 C24 C25 C26 C27 1 R52 2 0_0402_5%~D HPD OUT 2 4.7K_0402_5%~D 2 4.7K_0402_5%~D CV55 2.2U_0402_6.3V6M~D 22 23 24 25 26 27 28 29 +3V_MXM SDA SCL RV50 1 @ RV54 1 2 @ R37 DVI_TXD1-_R 3 @ R38 NC/OE# HDMI_CFG1 34 HDMI_CFG0 35 10 DVI_TXD2-_R DVI_TXD2+_R DVI_TXD1-_R DVI_TXD1+_R DVI_TXD0-_R DVI_TXD0+_R DVI_TXC-_R DVI_TXC+_R 23 22 20 19 17 16 14 13 0_0402_5%~D NC/DDCBUF_EN# 2 4.7K_0402_5%~D 2 4.7K_0402_5%~D RV53 499_0402_1%~D 619_0402_1%~D 619_0402_1%~D PCH_HDMI_C_TXD2PCH_HDMI_C_TXD2+ PCH_HDMI_C_TXD1PCH_HDMI_C_TXD1+ PCH_HDMI_C_TXD0PCH_HDMI_C_TXD0+ PCH_HDMI_C_TXCPCH_HDMI_C_TXC+ D 11 15 21 33 40 46 I2C_CTL_EN# U3 .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D .1U_0402_16V7K~D DGPU_HPD_INT# Repeater @ RV14 1 @ RV15 1 1 OUT1p OUT1n OUT2p OUT2n OUT3p OUT3n OUT4p OUT4n POW 26 8 9 C_DVI_R_TXD2- 2 +3VS 2 2 2 2 2 2 2 2 1 D DVI_SDATA_R DVI_SCLK_R 4 4 1 HPD_SINK 25 C_DVI_R_TXD2+ @ R36 29,30 DGPU_SEL# 1 1 1 1 1 1 1 1 Q11 SSM3K7002F_SC59-3~D 2 4.7K_0402_5%~D 1 L4 DVI_TXD2-_R 3 3 +3VS B 19 DGPU_HPD_INT# RV55 1 +3VS IN1p IN1n IN2p IN2n IN3p IN3n IN4p IN4n 30 8 GND C1783 C1784 C1785 C1786 C1787 C1788 C1789 C1790 GPU_HDMI_TXD2GPU_HDMI_TXD2+ GPU_HDMI_TXD1GPU_HDMI_TXD1+ GPU_HDMI_TXD0GPU_HDMI_TXD0+ GPU_HDMI_TXCGPU_HDMI_TXC+ 2 HDMI_SINK_HPD_R R983 R982 619_0402_1%~D 619_0402_1%~D 2 3 R974 R977 1 S 619_0402_1%~D 619_0402_1%~D 2 1 2 G R976 R975 GPU_HDMI_TXD2GPU_HDMI_TXD2+ GPU_HDMI_TXD1GPU_HDMI_TXD1+ GPU_HDMI_TXD0GPU_HDMI_TXD0+ GPU_HDMI_TXCGPU_HDMI_TXC+ 619_0402_1%~D 619_0402_1%~D 14 14 14 14 14 14 14 14 TMDS_B_DATA2# TMDS_B_DATA2 TMDS_B_DATA1# TMDS_B_DATA1 TMDS_B_DATA0# TMDS_B_DATA0 TMDS_B_CLK# TMDS_B_CLK D R984 R981 TMDS_B_DATA2# TMDS_B_DATA2 TMDS_B_DATA1# TMDS_B_DATA1 TMDS_B_DATA0# TMDS_B_DATA0 TMDS_B_CLK# TMDS_B_CLK 38 39 41 42 44 45 47 48 +3VS DGPU_EDIDSEL#_R Q99 SSM3K7002F_SC59-3~D R972 0_0402_5%~D 1 2 C 17 17 17 17 17 17 17 17 DVI_TXD2DVI_TXD2+ DVI_TXD1DVI_TXD1+ DVI_TXD0DVI_TXD0+ DVI_TXCDVI_TXC+ +3VS R973 100K_0402_5%~D +3VS 15 1 OE# S 2 32 2 2 1 R1896 DVI_SCLK_L DVI_SDATA_L HDMI_SW_DETECT 4 7 9 12 1A 2A 3A 4A 2 1 HDMI_OE# 1 0_1206_5%~D 2 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 SN74CBT3257CPWR_TSSOP16~D 2 1 1 @ NC D28 BAT1000-7-F_SOT23-3~D CV38 1U_0603_10V4Z~D 2 CV39 1U_0603_10V6K~D 1 @ FV2 1 +HDMI_5V 1 2 5A_125V_R451005.MRL~D Vcc 2 3 5 6 11 10 14 13 2 1 G W=40mils 3 2 16 1 2 +HDMI_5V_OUT 1 2 14 GPU_HDMI_SCLK 17 HDMICLK_NB 14 GPU_HDMI_SDATA 17 HDMIDAT_NB 14 VGA_HDMI_DET 17 TMDS_B_HPD 1 +5VS B2 U37 2 1 R31 GPU_HDMI_SCLK 1 1 R29 GPU_HDMI_SDATA 4.7K_0402_5%~D 2 2 4.7K_0402_5%~D 2 1 D 2 B1 1 2 0_0402_5%~D 1 WCM-2012-900T_4P DVI_TXD2+_R 2 2 1 1 2 0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 1 R27 HDMICLK_NB 2.2K_0402_5%~D 2 +3V_MXM 1 UV2 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 1 @ R34 CV52 0.01U_0402_16V7K~D 2 0_0603_5%~D Close to UV2 VCC pins Y CV54 0.1U_0402_16V4Z~D +3VS @R1965 @ R1965 1 SEL CV53 0.1U_0402_16V4Z~D 2 0_0603_5%~D CV51 0.01U_0402_16V7K~D R1964 1 C187 .1U_0402_16V7K~D 1 R26 HDMIDAT_NB 2.2K_0402_5%~D 2 +5VS C186 .1U_0402_16V7K~D +3VS 1 +3VS 2 5 Tuesday, November 30, 2010 Sheet 1 28 of 63 A +3VS B +3VS C D E DP Redriver +3VS 2 2 1 CFG_HPD,HPD switching configuration L:HPD is switched by SW_ML H:HPD is switched by SW_AUX M:HPD is switched with overlap R1711 4.7K_0402_1%~D DISP_A0P_L C35 DISP_A0N_L C36 2 2 1 1 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D PCH_DISP_A0P_C 1 PCH_DISP_A0N_C 2 DISP_A1P_L C37 DISP_A1N_L C38 2 2 1 1 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D PCH_DISP_A1P_C 3 PCH_DISP_A1N_C 4 DISP_A2P_L C40 DISP_A2N_L C45 2 2 1 1 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D PCH_DISP_A2P_C 6 PCH_DISP_A2N_C 7 2 2 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 1 1 PCH_DISP_A3P_C 9 PCH_DISP_A3N_C 10 DP_RP_CAB_DET 12 DP_RP_HPD 13 CFG_OUTPUT: output configuration L:Output is tracking DPCD register setting (auto interception) H:Output swing level fixed at 600mV and no pre-emphasis M:Output swing level is fixed at 400mV and no pre-emphasis +3VS @ R1702 2 1 4.7K_0402_1%~D DP_IN1_AEQ# @ R1703 2 1 4.7K_0402_1%~D DP_IN2_AEQ# CAB_DET_SINK DISP_HPD_SINK 14 15 16 SW_AUX INy_AEQ# (y=1, 2),Automatic RX equalization enable L:Disable input automatic equalization H:Enable input automatic equalization 2 5 29 21 17 11 36 D1+ D1D2+ D2D3+ D3- 2 DISP_A3P_L C48 DISP_A3N_L C49 D0+ D0- Chanel 0 IN1 GPU 1 IN2 PCH 2 1 DISP_A0P_C DISP_A0N_C C42 C43 2 2 1 1 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D DISP_A0P DISP_A0N D1+A D1-A 26 25 DISP_A1P_C DISP_A1N_C C39 C44 2 2 1 1 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D DISP_A1P DISP_A1N D2+A D2-A 23 22 DISP_A2P_C DISP_A2N_C C46 C47 2 2 1 1 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D DISP_A2P DISP_A2N 20 19 DISP_A3P_C DISP_A3N_C C50 C51 1 1 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D DISP_A3P DISP_A3N C54 C55 33 32 AUXSRC+ AUXSRC- DISP_AUXP_RC DISP_AUXN_RC 1 0.1U_0402_10V7K~D 1 0.1U_0402_10V7K~D 2 2 DISP_AUXN DISP_AUXP 35 34 DDCSDA DDCSCL 2 2 DISP_CLK_AUXP_CONN DISP_DAT_AUXN_CONN 31 30 NC Source 2 1 28 27 AUX_SINK+ AUX_SINK- CAD_SINK HPD_SINK 1 D0+A D0-A D3+A D3-A CAD HPDSRC 8 18 24 37 2 CFG_OUTPUT INy_PEQ(y = 1, 2),Programmable input equalization level setting L:Low EQ setting (LEQ), default H:High EQ setting (HEQ) M:No EQ 2 U5 VDD15 VDD15 VDD15 VDD15 VDD15 R1710 @ 4.7K_0402_1%~D 1 2 GND GND GND GND R1705 @ 4.7K_0402_1%~D R1708 @ 4.7K_0402_1%~D 1 R1707 @ 4.7K_0402_1%~D 1 1 1 1 2 CFG_HPD VCC33 1 1 2 DP_IN2_PEQ# C34 0.1U_0402_16V4Z~D +3VS DP_IN1_PEQ# 1 C41 0.1U_0402_16V4Z~D R1709 4.7K_0402_1%~D C33 0.1U_0402_16V4Z~D R1704 @ 4.7K_0402_1%~D C32 0.1U_0402_16V4Z~D R1706 @ 4.7K_0402_1%~D 2 2 1 +3VS +1.5VS +3VS_DP PI2EQXDP101ZFEX_TQFN36_6X5 R56 2 DISP_DAT_AUXN_CONN DISP_CLK_AUXP_CONN R59 1 100K_0402_5%~D 2 100K_0402_5%~D 1 2 +3VS 17 PCH_DPC_AUXP 17 PCH_DPC_AUXN 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 1 VGA_DPC_AUXP/DDC_C 24 1 VGA_DPC_AUXN/DDC_C 23 20 19 C426 C427 C416 C417 C369 C370 C121 C367 1 C299 1 C300 VGA_DPC_HPD DP_HPD CA_DET DGPU_SEL# CFG_HPD OUT_HPD 46 43 CFG_HPD DP_RP_HPD 18 17 26 25 22 21 IN2_AUXp IN2_AUXn IN2_SCL IN2_SDA REXT CEXT IN1_HPD IN2_HPD GND GND Epad PD 45 12 57 40 DGPU_SEL# 1 G 1 0 NVDIA 1 ATI A Chanel 2 1 1 2 @ 2 1 2 1 2 S 1 2 1 2 1 2 0_0402_5%~D 1 2 R61 28,30 1M_0402_5%~D 2 1 R65 CAB_DET_SINK 5.1M_0402_5% 2 1 R64 DISP_CEC 1M_0402_5%~D 2 1 R62 DISP_HPD_SINK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DISP_HPD_SINK DISP_A0P CAB_DET_SINK DISP_A0N DISP_CEC 3 DISP_A1P DISP_A3P DISP_A1N DISP_A3N DISP_A2P DISP_CLK_AUXP_CONN DISP_A2N DISP_DAT_AUXN_CONN Place close JDP1 @ D5 DISP_A0P 1 10 DISP_A0P Source DISP_A2N 2 9 DISP_A2N DISP_A0N 2 9 DISP_A0N 4 7 DISP_A3P DISP_A1P 4 7 DISP_A1P 5 6 DISP_A3N DISP_A1N 5 6 DISP_A1N 0 IN1 GPU DISP_A3P 1 IN2 PCH DISP_A3N DP_MXM_CARD_SEL 23,44 GND HOT PLUG LANE0_P CONFIG1 LANE0_N CONFIG2 GND GND LANE1_P LANE3_P LANE1_N LANE3_N GND GND LANE2_P AUX_CH_P LANE2_N AUX_CH_N GND DP_PWR GND1 GND2 GND3 GND4 21 22 23 24 JAE_DP2R020JQ2-1-CP CONN@ Link Done 3 8 4 8 RCLAMP0524P.TCT~D RCLAMP0524P.TCT~D 3 G Compal Electronics, Inc. 5 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. S 4 MXM_MFG_SEL GPU Source 2 G @ D4 Q278A DMN66D0LDW-7_SOT363-6~D S D Q12 BSS138_SOT23~D 3 2 4 D 6 2 R507 100K_0402_5%~D D 10 DISP_A2P 1 SW_ML/I2C_ADDR +3VS_DP 1 1 R529 100K_0402_5%~D DISP_AUXP_R DISP_AUXN_R DISP_A2P PS8321QFN56GTR-A0_QFN56_7X7 VGA_DPC_AUXN/DDC 8 3 6 4 SN74CBTD3306CPWR_TSSOP8~D CAB_DET_SINK# 18 DP_CBL_DET SW_ML/I2C_ADDR 1A VCC 2A 1B 1OE# 2B 2OE# GND JMDP1 2 VGA_DPC_AUXP/DDC 2 5 1 7 1 CAB_DET_SINK 48 IN2_D0p IN2_D0n IN2_D1p IN2_D1n IN2_D2p IN2_D2n IN2_D3p IN2_D3n DISP_AUXP DISP_AUXN 2 DP_RP_CAB_DET U75 1 44 DISP_A0P_L DISP_A0N_L DISP_A1P_L DISP_A1N_L DISP_A2P_L DISP_A2N_L DISP_A3P_L DISP_A3N_L 7 8 10 11 13 14 15 16 6 9 CFG_OUTPUT 42 41 39 38 36 35 33 32 OUT_D0p OUT_D0n OUT_D1p OUT_D1n OUT2_D2p OUT2_D2n OUT_D3p OUT_D3n IN1_AUXp IN1_AUXn IN1_SCL IN1_SDA 34 3 CFG_OUTPUT 37 R1701 4.99K_0402_1% 14 VGA_DPC_HPD 17 DP_HPD PCH_DPC_AUXP_C PCH_DPC_AUXN_C PCH_DPC_CLK PCH_DPC_DAT I2C_CTL_EN IN1_D0p IN1_D0n IN1_D1p IN1_D1n IN1_D2p IN1_D2n IN1_D3p IN1_D3n C1801 2.2U_0402_6.3V6M~D 17 PCH_DPC_CLK 17 PCH_DPC_DAT PCH_DPC_C_P0 PCH_DPC_C_N0 PCH_DPC_C_P1 PCH_DPC_C_N1 PCH_DPC_C_P2 PCH_DPC_C_N2 PCH_DPC_C_P3 PCH_DPC_C_N3 DISP_AUXP_RC DISP_AUXN_RC AC_AUXp AC_AUXn 2 +3VS 1 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D PCH_DPC_P0 PCH_DPC_N0 PCH_DPC_P1 PCH_DPC_N1 PCH_DPC_P2 PCH_DPC_N2 PCH_DPC_P3 PCH_DPC_N3 52 53 55 56 1 2 4 5 30 29 IN2_PEQ/SDA_CTL IN1_PEQ/SCL_CTL IN1_AEQ# IN2_AEQ# DGPU_EDIDSEL#_R 28,30 2 17 17 17 17 17 17 17 17 DISP_C_A0P DISP_C_A0N DISP_C_A1P DISP_C_A1N DISP_C_A2P DISP_C_A2N DISP_C_A3P DISP_C_A3N DISP_AUXP DISP_AUXN C71 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 3 C68 C69 C65 C67 C63 C64 C57 C66 28 27 C70 22U_0805_6.3VAM~D C297 C298 1 1 1 1 1 1 1 1 47 OUT_AUXp_SCL OUT_AUXn_SDA C62 0.1U_0402_16V4Z~D 14 VGA_DPC_AUXP/DDC 14 VGA_DPC_AUXN/DDC 2 2 2 2 2 2 2 2 49 50 3 51 SW_AUX DGPU_EDIDSEL#_R C61 10U_0603_6.3V6M~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D VGA_DPC_P0 VGA_DPC_N0 VGA_DPC_P1 VGA_DPC_N1 VGA_DPC_P2 VGA_DPC_N2 VGA_DPC_P3 VGA_DPC_N3 DP_IN2_PEQ# DP_IN1_PEQ# DP_IN1_AEQ# DP_IN2_AEQ# 1 VDD VDD F2 1.5A_6V_1206L150PR~D 14 14 14 14 14 14 14 14 54 31 R1473 100K_0402_5%~D Near to NV +5VS U129 R60 0_1206_5%~D 2 PCH/GPU AUX&LANE SW for DPB +3VS R1959 4.7K_0402_1%~D 2 1 R1958 4.7K_0402_1%~D 1 C53 0.1U_0402_16V4Z~D 2 C60 0.1U_0402_16V4Z~D 2 C56 0.1U_0402_16V4Z~D PCH_DPC_CLK 2.2K_0402_5%~D PCH_DPC_DAT 2.2K_0402_5%~D DP_HPD 1 100K_0402_5%~D 1 RV28 1 RV29 2 R509 2 +3VS 1 +3VS Q278B DMN66D0LDW-7_SOT363-6~D B C D Title DP SW for mDP CONN Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet E 29 of 63 5 4 3 2 1 D D +3VS +3VS 1 R170 C VGA_DPD_AUXP/DDC 2 2.2K_0402_5%~D VGA_DPD_AUXN/DDC 2 2.2K_0402_5%~D 14 14 14 14 14 14 14 14 VGA_DPD_P0 VGA_DPD_N0 VGA_DPD_P1 VGA_DPD_N1 VGA_DPD_P2 VGA_DPD_N2 VGA_DPD_P3 VGA_DPD_N3 17 17 17 17 17 17 17 17 PCH_DPD_P0 PCH_DPD_N0 PCH_DPD_P1 PCH_DPD_N1 PCH_DPD_P2 PCH_DPD_N2 PCH_DPD_P3 PCH_DPD_N3 14 VGA_DMC_HPD 17 PCH_DMC_HPD 14 VGA_DPD_AUXP/DDC 14 VGA_DPD_AUXN/DDC 17 PCH_DPD_CLK 17 PCH_DPD_DAT 1 2 U58 C213 C214 C211 C212 C209 C210 C207 C208 C327 C330 C199 C198 C217 C218 C215 C216 R175 R174 2 2 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D VGA_DPD_SW_P0 VGA_DPD_SW_N0 VGA_DPD_SW_P1 VGA_DPD_SW_N1 VGA_DPD_SW_P2 VGA_DPD_SW_N2 VGA_DPD_SW_P3 VGA_DPD_SW_N3 44 45 47 48 1 2 4 5 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D PCH_DPD_SW_P0 PCH_DPD_SW_N0 PCH_DPD_SW_P1 PCH_DPD_SW_N1 PCH_DPD_SW_P2 PCH_DPD_SW_N2 PCH_DPD_SW_P3 PCH_DPD_SW_N3 8 9 11 12 13 14 16 17 VGA_DMC_HPD_R PCH_DMC_HPD_R 46 10 41 42 19 20 DGPU_EDIDSEL#_R DGPU_SEL# 22 21 DMC_IN1_PEQ DMC_IN2_PEQ 3 15 1 10K_0402_5%~D 1 10K_0402_5%~D 28,29 DGPU_EDIDSEL#_R 28,29 DGPU_SEL# B 18 43 49 2 2 R1875 499_0402_1%~D C1821 2.2U_0603_6.3V6K~D 1 6 31 PWDN_ASQ 25 DMC_PWDN 28 DMC_CFG_HPD DDCBUF PRE_EMI RTERM 40 34 7 DMC_DDCBUF DMC_PRE_EMI OUT_D1n OUT_D1p OUT_D2n OUT_D2p OUT_D3n OUT_D3p OUT_D4n OUT_D4p 36 35 33 32 30 29 27 26 DMC_SW_P0 DMC_SW_N0 DMC_SW_P1 DMC_SW_N1 DMC_SW_P2 DMC_SW_N2 DMC_SW_P3 DMC_SW_N3 CFG_HPD IN2_D1n IN2_D1p IN2_D2n IN2_D2p IN2_D3n IN2_D3p IN2_D4n IN2_D4p 1 RV30 2 RV31 2 @ R1861 1 @R1861 @R1863 @ R1863 1 R1865 1 @R1867 @ R1867 1 @R1871 @ R1871 1 @R1873 @ R1873 1 1 1 2 2 2 2 2 2 2.2K_0402_5%~D 2.2K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D DMC_PWDN DMC_CFG_HPD DMC_DDCBUF DMC_PRE_EMI DMC_IN1_PEQ DMC_IN2_PEQ @ R1862 1 @R1862 @R1864 @ R1864 1 @R1866 @ R1866 1 @R1868 @ R1868 1 @R1872 @ R1872 1 @R1874 @ R1874 1 2 2 2 2 2 2 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D C R970 R969 R968 R967 R966 R965 R964 R963 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D DP_DMC_ML0P DP_DMC_ML0N DP_DMC_ML1P DP_DMC_ML1N DP_DMC_ML2P DP_DMC_ML2N DP_DMC_ML3P DP_DMC_ML3N DP_DMC_ML0P DP_DMC_ML0N DP_DMC_ML1P DP_DMC_ML1N DP_DMC_ML2P DP_DMC_ML2N DP_DMC_ML3P DP_DMC_ML3N 38 38 38 38 38 38 38 38 IN1_HPD IN2_HPD IN1_SCL IN1_SDA IN2_SCL IN2_SDA SW_DDC SW_MAIN OUT_HPD OUT_SCL OUT_SDA 39 38 37 DP_DMC_HPD DP_DMC_AUXP DP_DMC_AUXN DP_DMC_HPD 38 DP_DMC_AUXP 38 DP_DMC_AUXN 38 IN1_PEQ IN2_PEQ B CEXT REXT 1 23 24 IN1_D1n IN1_D1p IN1_D2n IN1_D2p IN1_D3n IN1_D3p IN1_D4n IN1_D4p VDD VDD 2 C197 0.1U_0402_16V4Z~D 1 R169 C188 10U_0603_6.3V6M~D PCH/GPU AUX&LANE SW for DPB +3V_MXM PCH_DPD_CLK PCH_DPD_DAT DMC_PWDN DMC_CFG_HPD DMC_DDCBUF DMC_PRE_EMI DMC_IN1_PEQ DMC_IN2_PEQ GND GND PAD PS8271QFN48GTR-A1_QFN48_7X7 SEL Y 0 IN1 1 IN2 A A DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Compal Electronics, Inc. Title HDMI SW for DMC Size 4 3 2 Rev 1.0 LA-6601P Date: 5 Document Number Tuesday, November 30, 2010 Sheet 1 30 of 63 4 1 1 For 4028 4 1 VDD 3 2 1 5 NC VIN VOUT EN ADJ 6 7 1 2 8 9 PGOOD GND GND 1 +3.3V_DVDD 2 U611 RT9025-25PSP_SO8 2 2 C1775 10U_0805_4VAM~D 1 2 L31 2 1 BLM18AG601SN1D_0603~D R1655 20K_0402_5%~D 1 2 C92 0.1U_0603_25V7K~D 1 2 C91 0.1U_0603_25V7K~D 2 2 C89 0.1U_0603_25V7K~D 1 2 C88 0.1U_0603_25V7K~D Close to respective power Pins 2 1 C86 0.1U_0603_25V7K~D AVDD_RPLL pin10 C610 0.1uF to AVSS_RPLL pin7 2 C84 22U_0805_6.3VAM~D 1 L13 1 2 BLM18AG601SN1D_0603~D C85 0.1U_0603_25V7K~D 1 2 BLM18BD601SN1D_0603~D C90 0.1U_0603_25V7K~D 1 +3.3V_AVDD_RPLL L11 C87 22U_0805_6.3VAM~D 1 2 +3.3V_AVDD C96 0.1U_0603_25V7K~D 1 2 C95 0.1U_0603_25V7K~D 2 C94 0.1U_0603_25V7K~D 2 C93 22U_0805_6.3VAM~D 1 +1.2V_DVDD L52 2 1 BLM18AG601SN1D_0603~D 2 100K_0402_5%~D 1 1 +1.2VS_HDMI 2 +3VS R1651 R172 0_0402_5%~D 2 1 +3.3V_DVDD L14 1 2 BLM18BD601SN1D_0603~D 1 +1.2VS_A 1 C433 22U_0805_6.3VAM~D 1 1.2V TDC 0.52A Peak Current 0.73A OCP current 3.5A R1653 10K_0402_5%~D 1 2 C183 .1U_0402_16V7K~D 1 2 +1.2VS C1772 1U_0402_6.3V6K~D 1 2 C83 0.1U_0603_25V7K~D 2 2 +5VS C82 0.1U_0603_25V7K~D 1 1 C81 0.1U_0603_25V7K~D 1 2 C80 0.1U_0603_25V7K~D Can not place large capacitor to prevent pulse happened when LVDS 1 power switch off/on 2 C79 22U_0805_6.3VAM~D 2 1 +1.2VS_HDMI L12 1 2 BLM18BD601SN1D_0603~D C78 0.1U_0603_25V7K~D 1 L32 1 2 BLM18BD601SN1D_0603~D C77 0.1U_0603_25V7K~D 1 2 C182 0.1U_0603_25V7K~D 1 2 C76 0.1U_0402_16V4Z~D 2 C75 0.1U_0603_25V7K~D +3VS 1 C74 0.1U_0603_25V7K~D 2 2 2 +1.2VS_HDMI +1.2V_AVDD C73 0.1U_0603_25V7K~D 1 C72 22U_0805_6.3VAM~D L10 1 2 BLM18BD601SN1D_0603~D D 3 +3.3V_AVDD_LVTX 1 +3.3V_AVDD +3.3V_AVDD 2 5 +3VS R100 1 2 10K_0402_5%~D BS_I2C_DEV_ID2 R99 1 2 10K_0402_5%~D BS_I2C_DEV_ID1 R98 1 2 10K_0402_5%~D BS_I2C_DEV_ID0 R90 1 2 10K_0402_5%~D BS_UART_FUNCTION_SEL R91 1 2 10K_0402_5%~D BS_RESERVED_R R92 1 2 10K_0402_5%~D BS_SPI_R 1 2 10K_0402_5%~D BS_I2C_SRC_R R103 1 2 10K_0402_5%~D BS_I2C_ON_R R96 1 2 10K_0402_5%~D BS_EXTKEY_EN R89 1 2 10K_0402_5%~D BS_OCM_BOOT_SEL R86 1 2 10K_0402_5%~D BS_INTERFACE_SEL1 R84 1 2 10K_0402_5%~D BS_INTERFACE_SEL0 R82 1 2 10K_0402_5%~D BS_XTAL_TCLK_SEL R79 1 2 10K_0402_5%~D BS_OSC_SEL R1665 1 2 10K_0402_5%~D HDMI_IN_AUD_CODEC R93 2 D +3.3V_DVDD DPRX_VDDD_1V2 2 R1687 BS_OSC_SEL 2 0_0402_5%~D 2 0_0402_5%~D DHMI_IN_NV_CLK 26 2 0_0402_5%~D DHMI_IN_NV_DAT 26 UART_TX_6038 28 UART_RX_6038 28 65 66 67 68 47 55 61 77 83 CRVSS CRVSS CRVSS CRVSS DPRX_VSSD DPRX_VSSA DPRX_VSSA ADC_VSSA ADC_VSSA ADC_VSSA ADC_VSSD HDMI_VSSA HDMI_VSSA 1 2 34,44 97 94 91 89 2 4 1 2 0_0402_5%~D @ R72 0_0402_5%~D HDMI_R_D1+ 1 HDMI_R_D1- 4 1 2 4 3 2 HDMI_IN_D1+ 3 HDMI_IN_D1- 1 2 1 2 0_0402_5%~D 0_0402_5%~D 1 1 2 2 @ R77 2 L18 HDMI_R_D2+ 1 HDMI_R_D2- 4 2 E0 E1 E2 VSS 2Kbit VCC WC SCL SDA 8 7 6 5 2 4 3 2 HDMI_IN_D2+ 3 HDMI_IN_D2- B WCM2012F2S-900T04_0805 1 @ R80 R1686 1 RC123 1 RC124 1 HDMI_SW_CLK HDMI_SW_DAT 1 2 22_0402_5% 2 100_0402_1%~D 2 100_0402_1%~D 2 +HDMI_IN_5VS EDID_WP HDMI_CLK HDMI_DAT 0_0402_5%~D R1681 1K_0402_1%~D HDMI_IN_CAB_DET# 44 C 1 HDMI_IN_CAB_DET# 33K_0402_5% +HDMI_IN_5VS HDMI_IN_HPD 1 22_0402_5% 2 R1682 2 B L101 2 1 MBK1608221YZF_2P HDMI_IN_HPD 1 2 D G +HDMI_IN_5VS 2 S HDMI_IN_DET# HDMI_DAT HDMI_CLK HDMI_IN_CKHDMI_IN_CK+ HDMI_IN_D0HDMI_IN_D0+ HDMI_IN_D1- HDMI_IN_CAB_DET# R1845 1 2 0_0402_5%~D HDMI_IN_DET# HDMI_IN_D1+ HDMI_IN_D2HDMI_IN_D2+ +HDMI_IN_5VS Link Done (pin 19) plug in 5V JHDMI1 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ 20 21 22 23 A SUYIN_100042GR019M23UZL CONN@ Compal Electronics, Inc. UART_RX_6038 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. STDP6038-AC_PQFP128_20X14~D 5 2 2KBit BAV99-7-F_SOT23-3 D50 @ R333 4.7K_0402_5%~D HDMI_IN_D0- 1 E +5VS 1 3 3 WCM2012F2S-900T04_0805 HDMI_R_D0- M24C02 2 HDMI_IN_SW_HPD 115 107 69 37 4 HDMI_IN_D0+ 2 2 M24C02-WMN6TP_SO8 R330 7 34 22 1 1 2 LVVSS LVVSS SPI_CSn / IRQ_IN / GPO_8 SPI_CLK / GPO_9(BS_INTERFACE_SEL1) SPI_DI / GPO_10(BS_INTERFACE_SEL0) SPI_DO / GPO_11(BS_UART_FUNCTION_SEL) HDMI_TOGGLE 2 D23 1SS355TE-17_SOD323-2 +5VS_HDMI_IN_EDID U614 1 HDMI_SPI_CS# HDMI_SPI_CLK HDMI_SPI_SO HDMI_SPI_SI 2 0_0402_5%~D 2 0_0402_5%~D 2 0_0402_5%~D VSSA_33 R1668 2 1 10K_0402_5%~D HDMI_PLUG_IN_CAB_DET R1670 2 1 10K_0402_5%~D R1671 2 1 10K_0402_5%~D 2 R149 1 R150 1 R151 1 I2S_0 (S/PDIF) / GPO_12(BS_RESERVED) I2S_AUMCLK / GPO_13(BS_SPI_FUN_SEL) I2S_WS / GPO_14(BS_I2C_SRC_SEL) I2S_SCLK / GPO_15(BS_I2C_ON_SPI_EN) 110 C1792 0.1U_0402_16V4Z~D +3.3V_DVDD 3 BS_INTERFACE_SEL1 BS_INTERFACE_SEL0 BS_UART_FUNCTION_SEL LBADC_IN4 / GPIO_35 LBADC_IN3 / GPIO_34 LBADC_IN2 / GPIO_33 / TTL_SYNC4 LBADC_IN1 / GPIO_32 / TTL_SYNC3 103 104 101 102 1 1 1 2 3 4 5 C365 0.1U_0402_16V4Z~D 39 40 41 42 34 HDMI_PLUG_IN_CAB_DET GPIO_45 20_0402_5%~D BS_RESERVED_R 2 0_0402_5%~D BS_SPI_R 2 0_0402_5%~D BS_I2C_SRC_R 2 0_0402_5%~D BS_I2C_ON_R A HDMI 2 B E 2 1 1 1 1 HDMI_RXCN HDMI_RXCP HDMI_RX0N HDMI_RX0P HDMI_RX1N HDMI_RX1P HDMI_RX2N HDMI_RX2P HDMI_REXT HDMI_HPD / GPIO_22 HDMI_CEC / GPIO_23 HDMI_R_D0+ 1 R153 R164 R168 R171 20_0402_5%~D VBUFC_RPLL 2 0_0402_5%~D L16 Q260 MMST3904-7-F_SOT323-3~D @ R156 1 75 76 78 79 81 82 84 85 87 113 114 1 0_0402_5%~D @ R71 1 1 22_0402_5% 2 0_0402_5%~D HDMI_IN_AUDIO_CODEC HDMI_IN_PWM 26 1 1 C C1782 220P_0402_50V7K~D 35 BS_RESERVED 35 BS_SPI_FUN_SEL 35 BS_I2C_SRC_SEL 35 BS_I2C_ON_SPI_EN 10_0402_5%~D HDMI_R_SW_CK10_0402_5%~D HDMI_R_SW_CK+ 10_0402_5%~D HDMI_R_SW_D010_0402_5%~D HDMI_R_SW_D0+ 10_0402_5%~D HDMI_R_SW_D110_0402_5%~D HDMI_R_SW_D1+ 10_0402_5%~D HDMI_R_SW_D210_0402_5%~D HDMI_R_SW_D2+ 249_0402_1%~D HDMI_IN_SW_HPD C 2 @ R69 R1968 100K_0402_5%~D 34 I2S_DAT/SPDIF_IN 2 2 2 2 2 2 2 2 2 HDMI_IN_CK- 1 @ R74 1 Q285A DMN66D0LDW-7_SOT363-6~D +3.3V_AVDD R1688 1 R1689 1 R1690 1 R1691 1 R1692 1 R1693 1 R1694 1 R1695 1 R87 1 HDMI_IN_CK+ 3 3 BS_EXTKEY_EN UART_TX_6038 UART_RX_6038 2 WCM2012F2S-900T04_0805 +5VS 2 1 D30 2 1 1SS355TE-17_SOD323-2 C1791 .1U_0402_16V7K~D HDMI_R_CKHDMI_R_CK+ HDMI_R_D0HDMI_R_D0+ HDMI_R_D1HDMI_R_D1+ HDMI_R_D2HDMI_R_D2+ +HDMI_IN_5VS 1 119 118 117 3 WCM2012F2S-900T04_0805 2 BS_XTAL_TCLK_SEL 0_0402_5%~D 1 R1667 2 4 @ R73 1 BS_OCM_BOOT_SEL HDMI_IN_AUD_CODEC R1842 1 HDMI_IN_PWM BS_I2C_DEV_ID2 BS_I2C_DEV_ID1 1 BS_I2C_DEV_ID0 R1663 DHMI_IN_NV_CLK_R R1843 1 DHMI_IN_NV_DAT_R R1844 1 4 4 DHMI_IN_NV_CLK_R DHMI_IN_NV_DAT_R 2 22_0402_5% 2 22_0402_5% 2 1 127 126 124 123 122 121 120 26 26 R1743 1 R1742 1 HDMI_R_CK- 1 L17 EDID_WP HDMI_IN_BKL_EN HDMI_IN_ENVDD 8 7 6 5 VCC WC SCL SDA 1 M24C16-WMN6TP_SO8 LVDS_6038_TZOUT0- 25 LVDS_6038_TZOUT0+ 25 LVDS_6038_TZOUT1- 25 LVDS_6038_TZOUT1+ 25 LVDS_6038_TZOUT2- 25 LVDS_6038_TZOUT2+ 25 LVDS_6038_TZCLK- 25 LVDS_6038_TZCLK+ 25 1 DPRX_AUXN DPRX_AUXP DPRX_ML_L0P DPRX_ML_L0N DPRX_ML_L1P DPRX_ML_L1N DPRX_ML_L2P DPRX_ML_L2N DPRX_ML_L3P TTL_CKOUT / GPIO16(BS_EXTKEY_EN) DPRX_ML_L3N UART_TX / TTL_SYNC1 / GPO_7(BS_XTAL_TCLK_SEL) DPRX_REXT UART_RX / TTL_SYNC2 / GPO_6 DPRX_HPD_OUT / GPO_5 HDMI_IN_BKL_EN HDMI_IN_ENVDD E0 E1 E2 VSS R1669 10K_0402_5%~D 2 300_0402_1% GPO_2 / TTL_D7 / PWM2(BS_OCM_BOOT_SEL) STI_TM1 / PWM1 / TTL_D6 / GPO_1 GPO_0 / PWM0 / TTL_D5(BS_OSC_SEL) TTL_D4 / GPIO_21(BS_I2C_DEV_ID2) TTL_D3 / GPIO_20(BS_I2C_DEV_ID1) TTL_D2 / GPIO_19(BS_I2C_DEV_ID0) TTL_D1 / GPIO18 / M_I2C_SCL TTL_D0 / GPIO17 / M_I2C_SDA 3 2 U39 1 2 3 4 2 1 R76 48 49 53 54 56 57 59 60 62 63 51 43 GPIO_44 / S_I2C_SCL GPIO_43 / S_I2C_SDA PBIAS / TTL_D9 / GPO_4 PPOWER / TTL_D8 / GPO_3 2 R1685 4.7K_0402_1%~D +1.2V_AVDD 111 112 A_I2C_SDA A_I2C_SCL D1_I2C_SDA / GPIO_28 D1_I2C_SCL / GPIO_29 D2_I2C_SDA / GPIO_24 D2_I2C_SCL / GPIO_25 LVDS_6038_TZOUT0LVDS_6038_TZOUT0+ LVDS_6038_TZOUT1LVDS_6038_TZOUT1+ LVDS_6038_TZOUT2LVDS_6038_TZOUT2+ LVDS_6038_TZCLKLVDS_6038_TZCLK+ 1 R1684 4.7K_0402_1%~D 2 0_0402_5%~D 2 0_0402_5%~D 71 72 73 74 44 45 VEDID_VDD_3V3 E_CH0N_LV / TTL_D19 / GPIO_57 E_CH0P_LV / TTL_D18 / GPIO_56 E_CH1N_LV / TTL_D17 / GPIO_55 E_CH1P_LV / TTL_D16 / GPIO_54 E_CH2N_LV / TTL_D15 / GPIO_53 E_CH2P_LV / TTL_D14 / GPIO_52 E_CLKN_LV / TTL_D13 / GPIO_51 E_CLKP_LV / TTL_D12 / GPIO_50 E_CH3N_LV / TTL_D11 / GPIO_49 E_CH3P_LV / TTL_D10 / GPIO_48 21 20 19 18 17 16 15 14 13 12 16KBit NVRAM R1683 4.7K_0402_1%~D @1 R1876 @ @1 R1877 B 70 LVDS ADC_A_N ADC_A_P ADC_B_N ADC_B_P ADC_C_N ADC_C_P HSYNC_IN VSYNC_IN LVDS_6038_TXOUT0- 25 LVDS_6038_TXOUT0+ 25 LVDS_6038_TXOUT1- 25 LVDS_6038_TXOUT1+ 25 LVDS_6038_TXOUT2- 25 LVDS_6038_TXOUT2+ 25 LVDS_6038_TXCLK- 25 LVDS_6038_TXCLK+ 25 1 +3.3V_DVDD 0.1U_0402_16V4Z~D EC_HDMI_DAT EC_HDMI_CLK HDMI_SW_DAT HDMI_SW_CLK RESETn STI_TM2 33 32 31 30 29 28 27 26 25 24 2 2 NC O_CH0N_LV / TTL_D29 / GPIO_67 O_CH0P_LV / TTL_D28 / GPIO_66 O_CH1N_LV / TTL_D27 / GPIO_65 O_CH1P_LV / TTL_D26 / GPIO_64 O_CH2N_LV / TTL_D25 / GPIO_63 O_CH2P_LV / TTL_D24 / GPIO_62 O_CLKN_LV / TTL_D23 / GPIO_61 O_CLKP_LV / TTL_D22 / GPIO_60 O_CH3N_LV / TTL_D21 / GPIO_59 O_CH3P_LV / TTL_D20 / GPIO_58 2 1 C1781 XTAL TCLK 2 HDMI_R_CK+ 6 0.1U_0402_16V4Z~D 92 0.1U_0402_16V4Z~D 93 0.1U_0402_16V4Z~D 95 0.1U_0402_16V4Z~D 96 0.1U_0402_16V4Z~D 98 0.1U_0402_16V4Z~D 99 0.1U_0402_16V4Z~D 105 0.1U_0402_16V4Z~D 106 1 +3.3V_DVDD LVDS_6038_TXOUT0LVDS_6038_TXOUT0+ LVDS_6038_TXOUT1LVDS_6038_TXOUT1+ LVDS_6038_TXOUT2LVDS_6038_TXOUT2+ LVDS_6038_TXCLKLVDS_6038_TXCLK+ Q261 MMST3904-7-F_SOT323-3~D 2 2 2 2 2 2 2 2 +3.3V_DVDD 1 2 1 1 1 1 1 1 1 1 6 RVDD_33 RVDD_33 RVDD_33 2 1 C1793 C1794 C1795 C1796 C1797 C1798 C1799 C1800 1 4 125 +1.2V_AVDD R1754 4.7K_0402_1%~D C1780 4700P_0402_25V7K~D HDMI_RST# 1 2 10K_0402_5%~D 64 58 52 R1753 4.7K_0402_1%~D 36 R70 50 L15 2 VDDA_1V2 2 0_0402_5%~D 1 HDMI_SPI_CLK_R C445 0.1U_0402_16V4Z~D 8 9 @ R68 W25X20BVSNIG_SO8 R1744 4.7K_0402_1%~D R75 2.2K_0402_5%~D XTAL TCLK R1660 HDMI_SPI_CLK R1661 HDMI_SPI_SI 2 2 C1779 15P_0402_50V8J~D 38 109 128 +3.3V_DVDD +3.3V_DVDD DPRX_VDDA_1V2 DPRX_VDDA_1V2 DPRX_VDDA_1V2 1 R1656 15_0402_5%~D 1 15_0402_5%~D 1 88 1 27MHZ_10PF_X3S027000BA1H-U~D HDMI_VDDA_3V3 HDMI_VDDA_3V3 ADC_AVDD_3V3 ADC_AVDD_3V3 8 7 10K_0402_5%~D 2 HDMI_SPI_CLK_R 6 HDMI_SPI_SI_R 5 /CS VCC DO_IO1 /HOLD /WP CLK GND DIO_IO0 3 80 86 90 100 +3.3V_AVDD 1 2 3 4 2 ADC_DVDD_1V2 HDMI_SPI_CS#_R HDMI_SPI_SO_R 15_0402_5%~D 10K_0402_5%~D 1 AVDD_OUT_33 AVDD_OUT_33 +1.2V_DVDD @ CVDD_12 CVDD_12 CVDD_12 CVDD_12 116 108 46 35 1 11 23 +3.3V_AVDD_LVTX VDDA_3V3 XTAL 3 G2 4 G1 U7 10 +3.3V_AVDD_RPLL 1 U612 @ 1 2 R1658 15_0402_5%~D HDMI_SPI_CS# 2 1 HDMI_SPI_SO 1 2 R1659 1 2 +3.3V_DVDD R1657 2 @ R1662 15_0402_5%~D TCLK C 2 Y3 EC_HDMI_CLK 32 EC_HDMI_DAT 32 2 2 C98 10P_0402_50V8J~D C97 10P_0402_50V8J~D 1 EC_HDMI_CLK EC_HDMI_DAT 2 22_0402_5% 2 22_0402_5% C1778 .1U_0402_16V7K~D 44 EC_SMB_CK2_R 44 EC_SMB_DA2_R +3.3V_AVDD_RPLL 1 R1700 1 R1714 1 2Mbit SPI ROM 3 2 Title HDMI input - STDP6038 Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 31 of 63 5 4 3 2 +3VS +1.2VS_A U606C I2C_SCL/GPIO_24 I2C_SDA/GPIO_25 B13 A13 I2C_SCL I2C_SDA DPTX_HPD_IN/GPIO_23 1 0_0402_5%~D 1 0_0402_5%~D 2 2 1 EC_HDMI_CLK 31 EC_HDMI_DAT 31 2 DPTX_AUXN DPTX_AUXP 2 1 2 1 2 1 2 1 2 1 C389 0.1U_0603_25V7K~D C10 D10 EC_HDMI_CLK_R @ R335 EC_HDMI_DAT_R @ R341 C388 0.1U_0603_25V7K~D LV_DP_AUXN LV_DP_AUXP C12 LV_DP_AUXN LV_DP_AUXP C13 B14 C387 0.1U_0603_25V7K~D 24 24 DP_4028_HPD AUX_I2C_SCL/GPIO_15 AUX_I2C_SDA_GPIO_16 C386 0.1U_0603_25V7K~D 24 DP_4028_HPD DPTX_REXT C385 0.1U_0603_25V7K~D 2 C11 C384 0.1U_0603_25V7K~D 1 240_0402_1% +AVDD_OUT_LV_33 L45 2 1 BLM18AG601SN1D_0603~D C383 22U_0805_6.3VAM~D C390 0.1U_0603_25V7K~D R308 2 1 1 2 1 D D @ 1 1 2 2 1 2 1 2 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 3D_VIDEO AUX_UART_TX GPIO_3/BOOT6 I2C_SCL I2C_SDA EC_HDMI_DAT_R EC_HDMI_CLK_R R315 @ R317 R319 R321 R322 @ R325 R327 1 1 1 1 1 1 1 2 2 2 2 2 2 2 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D UART_TX AUX_UART_TX GPIO_0/BOOT3 GPIO_1/BOOT2 GPIO_2/BOOT5 GPIO_3/BOOT6 IRQ/BOOT7 1 2 3 4 S# Q W# VSS 8 7 6 5 VCC RESET# C D E7 E8 K6 K9 PVDD1 PVDD1 PVDD1 PVDD1 LVDS_SW_TZOUT2- M10 LVDS_SW_TZOUT2+ L10 25 LVDS_SW_TZOUT225 LVDS_SW_TZOUT2+ LVDS_SW_TZCLKLVDS_SW_TZCLK+ 25 LVDS_SW_TZCLK25 LVDS_SW_TZCLK+ N11 M11 P12 N12 P13 N13 M13 M14 L12 L13 O0_LVRX_CH1N_VIDIN21 O0_LVRX_CH1P_VIDIN20 O0_LVRX_CH6N_VIDIN24 O0_LVRX_CH6P_VIDIN25 L11 M12 25 LVDS_SW_TXOUT125 LVDS_SW_TXOUT1+ O0_LVRX_CH2N_VIDIN19 O0_LVRX_CH2P_VIDIN18 25 LVDS_SW_TXOUT225 LVDS_SW_TXOUT2+ O0_LVRX_CLKN_VIDIN17 O0_LVRX_CLKP_VIDIN16 25 LVDS_SW_TXCLK25 LVDS_SW_TXCLK+ O0_LVRX_CH3N_VIDIN15 O0_LVRX_CH3P_VIDIN14 O0_LVRX_CH4N_VIDIN3 O0_LVRX_CH4P_VIDIN2 O1_LVRX_CH0N_VIDIN23 O1_LVRX_CH0P_VIDIN22 O1_LVRX_CH1N_VIDIN21 O1_LVRX_CH1P_VIDIN20 K12 K11 O1_LVRX_CH2N_VIDIN19 O1_LVRX_CH2P_VIDIN18 J12 J13 O1_LVRX_CLKN_VIDIN17 O1_LVRX_CLKP_VIDIN16 H13 H14 O1_LVRX_CH3N_VIDIN15 O1_LVRX_CH3P_VIDIN14 G13 G14 25 LVDS_SW_TXOUT025 LVDS_SW_TXOUT0+ O1_LVRX_CH4N_VIDIN3 O1_LVRX_CH4P_VIDIN2 O1_LVRX_CH5N_VIDIN_CLK O1_LVRX_CH5P_VIDIN_DE O1_LVRX_CH6N_VIDIN24 O1_LVRX_CH6P_VIDIN25 LVDS_SW_TXOUT0LVDS_SW_TXOUT0+ P2 N2 LVDS_SW_TXOUT1LVDS_SW_TXOUT1+ P3 N3 LVDS_SW_TXOUT2LVDS_SW_TXOUT2+ N4 M4 LVDS_SW_TXCLKLVDS_SW_TXCLK+ M5 L5 N6 M6 P7 N7 G1 G2 H1 H2 E0_LVRX_CH0N_VIDIN13 E0_LVRX_CH0P_VIDIN12 E0_LVRX_CH5N_VIDIN_VSYNC E0_LVRX_CH5P_VIDIN_HSYNC E0_LVRX_CH1N_VIDIN11 E0_LVRX_CH1P_VIDIN10 E0_LVRX_CH6N_VIDIN26 E0_LVRX_CH6P_VIDIN27 M7 L6 G5 E0_LVRX_CH3N_VIDIN5 E0_LVRX_CH3P_VIDIN4 E1_LVRX_CH0N_VIDIN13 E1_LVRX_CH0P_VIDIN12 E1_LVRX_CH1N_VIDIN11 E1_LVRX_CH1P_VIDIN10 LVDS J2 J3 E1_LVRX_CH2N_VIDIN9 E1_LVRX_CH2P_VIDIN8 K3 K4 E1_LVRX_CLKN_VIDIN7 E1_LVRX_CLKP_VIDIN6 J10 H11 L2 L3 E1_LVRX_CH3N_VIDIN5 E1_LVRX_CH3P_VIDIN4 E1_LVRX_CH5N_VIDIN_VSYNC E1_LVRX_CH5P_VIDIN_HSYNC K10 J11 M1 M2 E1_LVRX_CH4N_VIDIN1 E1_LVRX_CH4P_VIDIN0 E1_LVRX_CH6N_VIDIN26 E1_LVRX_CH6P_VIDIN27 B11 C7 C8 D9 PVDD22 DPTX_VDDA_1V2 DPTX_VDDA_1V2 DPTX_VDDA_1V2 DPTX_VDDA_1V2 +AVDD_3V3 D6 D5 VDDA_3V3 VDD33_TX +VDD_RPLL_1V2 A3 F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9 B D7 D8 E9 E10 DPTX_VSSA DPTX_VSSA DPTX_VSSA DPTX_VSSA A2 VSS_RPLL VDD_RPLL C5 VSSA_TX +AVDD_LVRX_1V2 K7 AVSS_LVRX_12 L7 AVDD_LVRX_12 STDP4028-AB_LFBGA164 J5 H4 P1 AVSS_OUT_LVRX +AVDD_OUT_LV_33 J4 K5 H12 H3 L8 N1 N14 A STDP4028-AB_LFBGA164 PVDD21 +1.2VS_A E0_LVRX_CLKN_VIDIN7 E0_LVRX_CLKP_VIDIN6 A1 A14 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 M3 L4 E0_LVRX_CH2N_VIDIN9 E0_LVRX_CH2P_VIDIN8 E0_LVRX_CH4N_VIDIN1 E0_LVRX_CH4P_VIDIN0 2 PVSS3 PVSS3 PWR & GND N9 M9 G11 E0 & E1 LVDS Input LVDS_SW_TZOUT1LVDS_SW_TZOUT1+ M8 L9 O0 & O1 LVDS Input B 25 LVDS_SW_TZOUT125 LVDS_SW_TZOUT1+ O0_LVRX_CH5N_VIDIN_CLK O0_LVRX_CH5P_VIDIN_DE C U606D U606A O0_LVRX_CH0N_VIDIN23 O0_LVRX_CH0P_VIDIN22 1 M25PE20-VMN6TP_SO8N8 +1.2VS VEGA STDP4028 DPTx BootStraps P8 N8 20mils SPI_CLK_4028 SPI_DO_4028 +3VS LVDS_SW_TZOUT0LVDS_SW_TZOUT0+ 1 1 1 2Mbit U607 SPI_CSN_4028 SPI_DI_4028 STDP4028-AB_LFBGA164 25 LVDS_SW_TZOUT025 LVDS_SW_TZOUT0+ 2 2 2 1 R312 R318 R320 R307 R306 R304 R305 U606B 1 +3VS 2 @ 2 1 2 SYS, Audio & DPTX 1 TESTMODE1 2 C398 0.1U_0603_25V7K~D GPIO_3/BOOT6 1 2 R1673 10K_0402_5%~D F11 1 C397 0.1U_0603_25V7K~D G3 G10 GPIO_2/BOOT5 GPIO_3/BOOT6 C396 0.1U_0603_25V7K~D 1 R311 GPIO_2/BOOT5 TESTMODE0 2 C363 0.1U_0402_16V4Z~D 0_0402_5%~D 2 GPIO_1/BOOT2 1 2 C406 0.1U_0603_25V7K~D F3 D4 C395 0.1U_0603_25V7K~D 1 R310 GPIO_1/BOOT2 VBUFC_RPLL 1 2 +1.2VS_A C405 0.1U_0603_25V7K~D 0_0402_5%~D 2 PWM0/GPIO_0/BOOT3 GPIO_0/BOOT3 2 AUX_UART_RX +3VS E5 2 C394 22U_0805_6.3VAM~D C3 2 1 C404 0.1U_0603_25V7K~D 1 R309 1 1 C401 0.1U_0603_25V7K~D 0_0402_5%~D 2 IRQ/BOOT7/GPIO_12 1 2 C403 0.1U_0603_25V7K~D D12 IR_IN/GPIO_6 F12 G12 D11 E11 B2 B3 1 2 1 C402 22U_0805_6.3VAM~D IRQ/BOOT7 NC1 NC2 NC3 NC4 NC5 NC6 2 2 +3VS R1666 10K_0402_5%~D G4 SPI_DI/HOST_D1/GPO_19 SPI_DO/HOST_D0/GPO_20 SPI_CLK/HOST_CLK/GPIO_18 SPI_CSn/HOST_CS/GPIO_17 2 2 2 C400 0.1U_0603_25V7K~D 3D_VIDEO 1 C399 22U_0805_6.3VAM~D E3 1 2 1 BLM18AG601SN1D_0603~D +AVDD_LVRX_1V2 L48 2 1 BLM18AG601SN1D_0603~D 1 1 1 2 C415 0.1U_0603_25V7K~D D13 C14 E12 F10 +1.2VS_A 2 C414 0.1U_0603_25V7K~D SPI_DI_4028 SPI_DO_4028 SPI_CLK_4028 SPI_CSN_4028 UART_RX C1 2 1 2 2 +5VS E4 +AVDD_3V3 +1.2VS C413 22U_0805_6.3VAM~D CLK_OUT/GPIO_5/BOOT0 1 1 C412 0.1U_0603_25V7K~D RESETn I2S_BCLK/GPIO_7 I2S_WCLK/GPIO_4 +3VS L47 2 1 BLM18AG601SN1D_0603~D +5VS D2 F5 F4 D3 +VDD_RPLL_1V2 L46 C411 0.1U_0603_25V7K~D E6 TX_TCLK AUX_UART_TX AUX_UART_RX +1.2VS_A 27 27 C410 22U_0805_6.3VAM~D Y4 27MHZ_10PF_X3S027000BA1H-U~D RESET C4 B12 A12 UART_TX UART_RX R332 4.7K_0402_5%~D C C409 47P_0402_50V8J~D 3 G2 4 TX_TCLK TX_TCLK I2S_0/GPIO_8 I2S_1/GPIO_9 I2S_2/GPIO_10 I2S_3/GPIO_11 UART_TX UART_RX C364 0.1U_0402_16V4Z~D 1 R331 2.7K_0402_5% 1 2 G1 2 C408 10P_0402_50V8J~D 1 TX_XTAL C407 10P_0402_50V8J~D 2 eDP AUX_UART_TX/BOOT4/GPIO_21 AUX_UART_RX/GPIO_22 C2 B1 C393 0.1U_0603_25V7K~D TX_XTAL +3VS UART_TX/BOOT1/GPIO_13 UART_RX/GPIO_14 C392 0.1U_0603_25V7K~D B4 +AVDD_3V3 DPTX_ML_L0N DPTX_ML_L0P DPTX_ML_L1N DPTX_ML_L1P DPTX_ML_L2N DPTX_ML_L2P DPTX_ML_L3N DPTX_ML_L3P R334 4.7K_0402_5%~D TX_XTAL B6 C6 A7 B7 A8 B8 B9 C9 C391 22U_0805_6.3VAM~D LV_DP_A0N_L LV_DP_A0P_L LV_DP_A1N_L LV_DP_A1P_L LV_DP_A2N_L LV_DP_A2P_L LV_DP_A3N_L LV_DP_A3P_L LV_DP_A0N_L LV_DP_A0P_L LV_DP_A1N_L LV_DP_A1P_L LV_DP_A2N_L LV_DP_A2P_L LV_DP_A3N_L LV_DP_A3P_L C366 0.1U_0402_16V4Z~D 24 24 24 24 24 24 24 24 STDP4028-AB_LFBGA164 AVDD_OUT_LVRX_33 AVDD_OUT_LVRX_33 AVDD_OUT_LVRX_33 AVDD_OUT_LVRX_33 AVDD_OUT_LVRX_33 F2 F13 H10 H5 K8 P14 AVSS_OUT_LVRX AVSS_OUT_LVRX AVSS_OUT_LVRX AVSS_OUT_LVRX AVSS_OUT_LVRX AVSS_OUT_LVRX A Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title LVDS transfer eDP-STDP4028 Size 4 3 2 Rev 1.0 LA-6601P Date: 5 Document Number Tuesday, November 30, 2010 Sheet 1 32 of 63 5 4 3 2 1 UL1 CL1 16 PCIE_PRX_GLANTX_N3 2 1 .1U_0402_16V7K~D PCIE_PRX_GLANTX_P3_C 30 2 1 .1U_0402_16V7K~D PCIE_PRX_GLANTX_N3_C 29 PCIE_PTX_GLANRX_P3 35 RX_P 16 PCIE_PTX_GLANRX_N3 PCIE_PTX_GLANRX_N3 36 RX_N 16 CLK_PCIE_LAN 16 CLK_PCIE_LAN# D 16 LANCLK_REQ# RL12 1 0_0402_5%~D 2 5,18,35,38,39,44 PLT_RST# 17,38,39,44 PCIE_WAKE# 33 32 REFCLK_N CLKREQ_LAN#_R 4 CLKREQ# PLT_RST# 2 PCIE_WAKE# 3 2 4.7K_0402_5%~D PCIE_WAKE# @ RL11 1 2 4.7K_0402_5%~D CLKREQ_LAN#_R RL13 1 2 4.7K_0402_5%~D PERST# W=40mils LL1 +LX 1 2 +VDDCT 2.2UH_1225AS-H-2R2M-P2_1.3A_20%~D WAKE# NC TESTMODE GND AVDDH AVDDH AVDDH_REG 16 22 9 +AVDDH DVDDL DVDDL_REG 24 37 +DVDDL XTLO XTLI 1 VDD33 LX VDDCT LED_0 LED_1 LED_2 2 W=40mils 1 2 1 2 1 2 1 2 +LAN_IO 40 5 +LX 10 +RBIAS 1 2 1 2 close to Lan pin24 close to Lan pin37 close to Lan pin 40 +VDDCT close to Lan pin5 1 RBIAS 1 CL17 .1U_0402_16V7K~D SMCLK SMDATA W=20mils +DVDDL CL16 .1U_0402_16V7K~D 2 @ RL10 1 CL15 1U_0603_10V6K~D 1 PLT_RST# CL14 .1U_0402_16V7K~D 2 +LAN_IO CL13 .1U_0402_16V7K~D 1 1000P_0402_50V7K~D .1U_0402_16V7K~D 1000P_0402_50V7K~D .1U_0402_16V7K~D 1000P_0402_50V7K~D .1U_0402_16V7K~D 1000P_0402_50V7K~D .1U_0402_16V7K~D 2 2 2 2 2 2 2 2 AR8151-BL1A-RL_QFN40_5X5 W=20mils W=20mils close to Lan pin9 close to Lan pin6 +AVDDH close to Lan pin31 close to Lan pin19 +AVDDL 2 1 2 1 2 1 2 CL30 .1U_0402_16V7K~D 2 1 CL29 .1U_0402_16V7K~D 2 1 CL28 .1U_0402_16V7K~D 2 1 CL27 .1U_0402_16V7K~D 2 1 CL26 .1U_0402_16V7K~D 2 1 CL25 1U_0603_10V6K~D 2 1 CL24 .1U_0402_16V7K~D 1 CL23 .1U_0402_16V7K~D Version A will be fail on 802.3a need to update to Version B CL22 .1U_0402_16V7K~D 2 1 1 1 1 1 1 1 1 D CL21 1U_0603_10V6K~D 2 CL3 CL4 CL5 CL6 CL7 CL8 CL9 CL10 +AVDDL 13 19 31 34 6 AVDDL AVDDL AVDDL AVDDL AVDDL_REG RL14 25MHZ_12PF_X5H025000DC1H-H 1 1 49.9_0402_1% +LAN0 49.9_0402_1% 49.9_0402_1% +LAN1 49.9_0402_1% 49.9_0402_1% +LAN2 49.9_0402_1% 49.9_0402_1% +LAN3 49.9_0402_1% close to Lan chip 1000p reserved for EMI 2.37K_0402_1%~D LAN_X2 LAN_ACTIVITY# 38 LAN_LINK# 39 LAN_LED2# 23 RL16 5.1K_0402_1%~D 2 CL19 15P_0402_50V8J~D CL18 15P_0402_50V8J~D C 1 RL15 0_0402_5%~D YL1 7 8 1 1 1 1 1 1 1 1 CL12 10U_0603_6.3V6M~D LAN_X1 LAN_X2_R 2 2 2 2 2 2 2 2 CL11 1000P_0402_50V7K~D 28 27 41 RL2 RL1 RL3 RL4 RL5 RL7 RL8 RL9 REFCLK_P CLK_PCIE_LAN# 25 26 LAN_MDIP0 LAN_MDIN0 LAN_MDIP1 LAN_MDIN1 LAN_MDIP2 LAN_MDIN2 LAN_MDIP3 LAN_MDIN3 11 12 14 15 17 18 20 21 TRXP0 TRXN0 TRXP1 TRXN1 TRXP2 TRXN2 TRXP3 TRXN3 TX_N 16 PCIE_PTX_GLANRX_P3 CLK_PCIE_LAN Atheros AR8151-BL1A TX_P 2 CL2 16 PCIE_PRX_GLANTX_P3 C TS1 1 2 3 LAN_MDIP2 LAN_MDIN2 4 5 6 LAN_MDIP1 LAN_MDIN1 7 8 9 LAN_MDIP0 LAN_MDIN0 10 11 12 TCT1 TD1+ TD1- MCT1 MX1+ MX1- TCT2 TD2+ TD2- MCT2 MX2+ MX2- TCT3 TD3+ TD3- MCT3 MX3+ MX3- TCT4 TD4+ TD4- MCT4 MX4+ MX4- 24 23 22 RJ45_CT3 RJ45_MDI3+ RJ45_MDI3- RL21 1 2 75_0402_1%~D 21 20 19 RJ45_CT2 RJ45_MDI2+ RJ45_MDI2- RL22 1 2 75_0402_1%~D 18 17 16 RJ45_CT1 RJ45_MDI1+ RJ45_MDI1- RL23 1 2 75_0402_1%~D 15 14 13 RJ45_CT0 RJ45_MDI0+ RJ45_MDI0- RL24 1 2 75_0402_1%~D 1 1 1 2 CL48 .1U_0402_16V7K~D 2 2 @CL47 @ CL47 1000P_0402_50V7K~D 1 1 CL46 .1U_0402_16V7K~D 2 2 LAN_ACTIVITY# 2 @CL45 @ CL45 1000P_0402_50V7K~D 1 1 CL44 .1U_0402_16V7K~D 2 2 @CL43 @ CL43 1000P_0402_50V7K~D 1 CL42 .1U_0402_16V7K~D 1 @CL41 @ CL41 1000P_0402_50V7K~D 2 CL40 1U_0603_10V6K~D close to LL2 2 LAN_LINK# D S G 2 1 2 1 1 3 RJ45_MDI2- 5 RJ45_MDI2+ 4 PR3+ RJ45_MDI1+ 3 PR2+ RJ45_MDI0- 2 RJ45_MDI0+ 1 2 1 0_0402_5%~D LAN_LED_VCC1 12 1 2 330_0402_5% LAN_LED2#_R 13 2 1 2 1 2 1 2 CL35 10U_0603_6.3V6M~D S 2 CL36 0.1U_0402_25V6K~D QL2 SSM3K7002FU_SC70-3~D 2 G RL19 1.5M_0402_5%~D EN_WOL# 1 1 CL34 10U_0603_6.3V6M~D 2 CL33 1U_0603_10V6K~D 1 EN_WOL 44 6 1 2 1A 4 D RJ45_MDI1- RL20 2 CL32 .1U_0402_16V7K~D 6 5 2 1 7 LAN_LED2# RL27 +LAN_IO CL31 1000P_0402_50V7K~D 2 CL20 1U_0402_6.3V6K~D RL18 300K_0402_5%~D A 1 RJ45_MDI3+ 11 QL1 SI3456DDV-T1-GE3_TSOP6~D B+_BIAS 8 LAN_LINK#_R 1 4 PR4PR4+ PR2PR3- B PR1- SHLD2 PR1+ SHLD1 15 14 Green LEDLED+ ORANGE_LEDTYCO_2041332-1 Link Done A DELL CONFIDENTIAL/PROPRIETARY close to Pin 1 Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title GLAN AR8151 AL1A Size 3 2 Document Number Rev 1.0 LA-6601P Date: 5 Yellow LED+ RJ45_MDI3- 2 130_0402_1%~D CONN@ Yellow LED- 1 330_0402_5% LAN_ACTIVITY_R# 10 1 W=40mils 3 +3VALW RL25 2 RL26 +LAN_IO close to TS1 W=40mils close to Lan pin13 JLAN1 350UH_GST5009-CLF 1 close to Lan pin34 9 TIMAG: S X'FORM_ IH-160 LAN , SP050006F00 BOTHHAND: S X'FORM_ GST5009-D LF LAN,SP050006B00 B close to Lan pin16 close to Lan pin22 CL39 1000P_1808_3KV7K~D +VDDCT_L LAN_MDIP3 LAN_MDIN3 CL49 470P_0402_50V7K~D LL2 2 1 BLM18AG601SN1D_0603~D CL38 470P_0402_50V7K~D +VDDCT Tuesday, November 30, 2010 Sheet 1 33 of 63 A B C D +3VS +3VS 5 G 25 38 AVDD1 AVDD2 SYNC RESET# INB HP_JD 4 Y 1 1 2 2 SENSE_A SENSE_B PC_BEEP 31 I2S_DAT/SPDIF_IN TC7SZ02FU_SSOP5 +3VS +3VS 1 +3VS HDA_RST_AUDIO# 3 U15 74AHC1G08GW_SOT353-5~D 1 2 S 3 S EAPD/SPDIF IN/GPIO0 PORTI_L PORTI_C PORTI_R 2 1 2 1 2 0_1206_5%~D R329 1 2 0_1206_5%~D R340 1 2 0_1206_5%~D @ R338 10K_0402_5%~D 1 2 2 Q6B DMN66D0LDW-7_SOT363-6~D +3VS B3 VDD SET PACIN 2 B2 C138 270P_0402_50V7K~D 1 2 1 2 R116 4.7K_0402_5%~D R128 2K_0402_1%~D 6 8 HP_AMP_MUTE# 5 1 2 +3VS_AVDD C135 270P_0402_50V7K~D 44 BEEP# 1 C144 BEEP_C# 2 0.1U_0402_16V4Z~D 1 R134 2 100K_0402_5%~D 15 HDA_SPKR 1 C145 PCH_SPKR_C 2 0.1U_0402_16V4Z~D R135 2 1 100K_0402_5%~D 12 INL INR SHDN VDD MIC_CD_L OUTR OUTL 35,44 SPK_MUTE# PVSS SVSS HP1_AMP_R1_JK 2 MAX9892ERT+T_UCSP6~D Link Done L21 BLM18BD601SN1D_0603~D 1 2 MIC_CD_L1_JK L22 1 2 MIC_CD_R1_JK BLM18BD601SN1D_0603~D PGND SGND GND CONN@ HP2_AMP_R1_JK A3 B1 1 B3 6 1 2 1 INL 2 INR /MUTE +3VS VDD SET 3 4 MIC_JD 1 2 2 7 13 1 TYCO_2041187-1~D 3 @ D8 PJDLC05C_SOT23-3 3 B2 2 HP2_AMP_L1 1 2 68_0603_1%~D L23 HP2_AMP_R1 1 2 68_0603_1%~D L24 Place close to Jack MAX9892ERT+T_UCSP6~D Link Done HP2_AMP_L1_JK 2 BLM18BD601SN1D_0603~D HP2_AMP_R1_JK 2 BLM18BD601SN1D_0603~D 1 2 C1842 2.2U_0603_10V7K~D HDMI_L R157 1 HDMI_R R158 1 1 1 2 S 1 2 560_0402_5%~D 560_0402_5%~D 2 2 MIC_CD_R1_JK 2 1 C1841 2.2U_0603_10V7K~D HDMI_IN_L 1 2 HDMI_IN_R 1 2 MIC_CD_L1_JK 1 1 2 CONN@ 6 1 2 Center HP2_AMP_L 1 R127 HP2_AMP_R 1 R130 7 8 G G 5 JHP2 4 9 R136 @ 10K_0402_5%~D 2 HP1_AMP_L1_JK 2 1000P_0402_50V7K~D Setting the Turn-Off Time: Ton (ms) = 0.02 x Cset (pF) HP2_AMP_R HP2_AMP_L 10 11 2 35 3 @ D6 PJDLC05C_SOT23-3 R117 4.7K_0402_5%~D 2 MIC_CD_L1 2.2U_0603_10V7K~D 2 MIC_CD_R1 2.2U_0603_10V7K~D 1 C129 MIC_CD_R 1 C130 +3VS MAX9724BETC+T_TQFN-EP12_3X3 PC_BEEP Place close to Jack 1 JMIC1 Rear or MIC HP2_AMP_L1_JK A1 HP2_CD_L2 HP2_CD_R2 2 C125 1 2 +3VS_AVDD C139 1U_0603_10V4Z~D U16 1 2 1 C1P 3 C1N 1 7 8 G G TYCO_2041187-1~D +MIC1_VREFO W=10 mil AGND C137 R129 2.2U_0805_10V7K~D 2K_0402_1%~D HP2_CD_L HP2_CD_L1 1 2 HP2_CD_R HP2_CD_R1 1 2 Link Done +MIC1_VREFO 49,50 C1844 0.1U_0402_16V4Z~D HP2_JD 5 HP2_JD HDMI_IN_AUD_L 35 HDMI_IN_AUD_R 35 3 4 G G 5 7 8 TYCO_2041187-1~D @ D9 PJDLC05C_SOT23-3 3 1 2 HP2_AMP_L1_JK 4 HP2_AMP_R1_JK Place close to Jack Compal Electronics, Inc. Title HD Audio_IDT92HD73C Size Document Number Rev 1.0 LA-6601P Tuesday, November 30, 2010 Date: A B C D 1 +3VS 2 LINE_OUT_JD 35 1 1 14,35 2 1 D7 SDMK0340L-7-F_SOD323-2~D 1 2 @ R115 0_0402_5%~D L51 2 1 BLM18AG601SN1D_0603~D GND 2 3 1 1 +3VS 1 1 1 2 6 R316 1 C1839 2700P_0402_50V7~D Q16A DMN66D0LDW-7_SOT363-6~D 2 7 13 5 C141 220P_0402_50V7K~D 1 2 0_1206_5%~D 1 INR /MUTE C140 220P_0402_50V7K~D 2 1 INL 27 33 VREFFILT CAP2 R303 A3 B1 Setting the Turn-Off Time: Ton (ms) = 0.02 x Cset (pF) C1838 2700P_0402_50V7~D 2 DVSS AVSS1 AVSS2 1 R131 2 5.1K_0402_1%~D R1678 100K_0402_5%~D G HDMI_IN_L HDMI_IN_R 48 40 SPDIF OUT0 SPDIF OUT1/GPIO3 A1 C1845 0.1U_0402_16V4Z~D SPDIF_OUT C131 1U_0603_10V4Z~D 1 C142 1000P_0402_50V7K~D 2 PORTH_L PORTH_R 45 46 U621 U620 +AVDD_AUDIO R1677 20K_0402_1%~D D 43 44 +3VS C136 2.2U_0805_10V7K~D R132 39.2K_0402_1% R133 100K_0402_5%~D HP1_JD 2 S 4 2 1 4 DMN66D0LDW-7_SOT363-6~D 2 6 1 G Q6A DMN66D0LDW-7_SOT363-6~D SENSE_A +3VS PORTG_L PORTG_R PCBEEP 18 19 20 1 2 3 1 2 6 1 G PGND SGND GND VDD 3 4 2 C143 1U_0603_10V4Z~D Q284A DMN66D0LDW-7_SOT363-6~D D 1 R126 100K_0402_5%~D D HDMI_TOGGLE 31,44 4 16 17 2 1 R122 2 5.1K_0402_1%~D C134 2 R124 20K_0402_1%~D S MIC_JD R125 100K_0402_5%~D D 2 G SENSE_B +3VS SHDN 2 HP1_AMP_R1_JK HP1_JD L20 BLM18BD601SN1D_0603~D +MIC1_VREFO 1 +AVDD_AUDIO R123 39.2K_0402_1% S Q284B G 4 9 HP1_AMP_R1 1 1 2 R113 68_0603_1%~D C132 220P_0402_50V7K~D D PVSS SVSS HP1_AMP_R EAPD# 2 SDMK0340L-7-F_SOD323-2~D HP1_AMP_L1_JK SPK_CD_L 35 SPK_CD_R 35 HP1_AMP_R1_JK SPK_MUTE# Place under codec 1000P_0402_50V7K~D 5 R1902 100K_0402_5%~D PORTF_L PORTF_R HP2_CD_L HP2_CD_R 35 35 C133 220P_0402_50V7K~D +3VS MIC_CD_L MIC_CD_R 92HD73C1X5PRGXC1X8_QFP48_7X7 R1903 10K_0402_1%~D 3 SENSE_A SENSE_B SENSE_C 47 7 26 42 2 P HP_AMP_MUTE# IN2 Q15 PMF3800SN_SC70-3~D HP_JD 2 G DMIC1/GPIO5 CODEC_EAPD# 1 D54 SPK_CD_L SPK_CD_R 14 15 31 PORTE_L PORTE_R VREFOUT-E LINEOUT_L LINEOUT_R C127 10U_0603_6.3V6M~D 1 D O INL INR 5 HP1_AMP_R HP1_AMP_L JHP1 CONN@ Int. Speaker and Sub woofer C126 1U_0402_6.3V6K~D 2 4 G HP_JD# IN1 12 VOL_DN/DMIC_0/GPIO2 LINEOUT_L LINEOUT_R 35 36 PORTD_L PORTD_R VOL_UP/DMIC_CLK/GPIO1 R1680 4.7K_0402_1%~D 5 1 2 EA_EC_SPK_MUTE# 1 13 34 32 C28 .1U_0402_16V7K~D R118 10K_0402_5%~D 2 0.1U_0402_10V6K~D 30 31 HDMI_IN_AUDIO_CODEC INA C128 1 6 8 6 1 2 GND U14 P 2 4 G 1 HP2_JD 3 HP1_JD 2 2 5 C124 0.1U_0402_10V6K~D 1 2 FBMA-10-100505-301T_2P 0_0402_5%~D C120 15P_0402_50V8J~D C119 15P_0402_50V8J~D +3VS 2 10 11 L19 BLM18BD601SN1D_0603~D HP1_AMP_L1 1 2 HP1_AMP_L1_JK A2 2 2 @ DMIC0 R110 1 @ 24,26 L102 1 21 22 28 23 24 29 PORTC_L PORTC_R VREFOUT-C Reserve for EMI please close to U12 DMIC_CLK OUTR OUTL R111 68_0603_1%~D HP1_AMP_L 1 2 Front GND 11 PORTB_L PORTB_R VREFOUT-B SDO HP1_CD_L HP1_CD_R A2 10 15 HDA_SYNC_AUDIO SDI_CODEC 39 41 37 1 5 PORTA_L PORTA_R VREFOUT-A BITCLK C122 1000P_0402_50V7K~D U11 74AHC1G08GW_SOT353-5~D 8 1 1 HDA_SDIN0_R 33_0402_5%~D 15 HDA_RST_AUDIO# 24,26 C1P C1N 12 2 G 2 15 HDA_SDOUT_AUDIO 132mA C123 1000P_0402_50V7K~D 3 1 R107 HDA_SDIN0 SPK_AMP_MUTE# 35 2 2 3 5 P 4 O 6 15 HDA_BITCLK_AUDIO DVDD_CORE DVDD_CORE DVDD_IO 2 0.1U_0402_10V6K~D 15 IN1 9 1 3 U12 2 0_0402_5%~D C114 1 IN2 2 U9 1 3 MAX9724BETC+T_TQFN-EP12_3X3 +3VS 2 2 C116 1U_0603_10V4Z~D C113 270P_0402_50V7K~D 1 2 C115 R106 1 2 2.2U_0805_10V7K~D 2K_0402_1%~D HP1_CD_L HP1_CD_L1 1 HP1_CD_L2 2 HP1_CD_R HP1_CD_R1 1 HP1_CD_R2 2 C111 C112 R105 270P_0402_50V7K~D HP_AMP_MUTE# 2.2U_0805_10V7K~D 2K_0402_1%~D 1 2 +3VS_AVDD C100 1U_0603_10V4Z~D 1 @ R112 HP_JD 2 1 74AHC1G08GW_SOT353-5~D 75mA EA_EC_SPK_MUTE# 1 2 1 H C117 1U_0603_10V4Z~D P 2 2 1 G +5VS LL3 2 1 BLM18AG601SN1D_0603~D C109 0.1U_0402_10V6K~D 4 EA_EC_SPK_MUTE# O 2 1 C108 1U_0402_6.3V6K~D IN2 2 1 1 C107 10U_0603_6.3V6M~D IN1 2 2 U8 1 1 C104 10U_0603_6.3V6M~D SPK_MUTE# 35,44 SPK_MUTE# 1 C103 0.1U_0402_10V6K~D 1 2 0.1U_0402_16V4Z~D L49 2 1 +DVDD_CORE BLM18BD601SN1D_0603~D C102 1U_0402_6.3V6K~D C99 1 C101 0.1U_0402_10V6K~D +3VS 1 +DVDD_AUDIO 2 R102 1 0_0603_5%~D C106 0.1U_0402_10V6K~D 1 R101 1 R104 EAPD# F +AVDD_AUDIO C105 1U_0402_6.3V6K~D EAPD# 20K_0402_1%~D 2 SPK_MUTE# 10K_0402_5%~D 2 E +3VS E F G Sheet 34 H of 63 5 4 3 2 1 B+ 1 2 U17 27 30 28 29 PVDD1 PVDD2 L25 AMP_SPKL- 1 2 BLM18PG181SN1_0603~D 1 2 OUTL-1 OUTL-2 2 PGND2 PGND1 D 2 10 11 9 IN_R 25 26 OUTR+1 OUTR+2 L28 AMP_SPKR+ 1 2 BLM18PG181SN1_0603~D L29 AMP_SPKR+_R AMP_SPK_JK_R+ 1 2 22UH_LQH55PN220MR0L_0.85A_20%~D 1 SHDN# REGEN MUTE# 2 +3VS For filterless modualation/spread-spectrum mode R147 1 2 0_0402_5%~D Mono Select. Set MONO high for mono mode. 2 SDMK0340L-7-F_SOD323-2~D SPK_AMP_MUTE_R# 2 2 1 2 13 14 S 3 AGND AGND 2 1 34 LINEOUT_R 34 LINEOUT_L 34 LINE_OUT_JD 1 2 1 2 1 1 D11 PJSOT24C_SOT23-3 1 2 LINEOUT_R C738 1 LINEOUT_L C739 1 LINE_OUT_JD R1650 2 2 1 220U_6.3V_M SPDIF OUT JACK 220U_6.3V_M 2 0_0402_5%~D 34 34 LINE2-L 9 6 1 4 SPDIF_PLUG# 5 LINE2-R 7 8 3 10 14,34 SPDIF_OUT +5VS U619 1 @D24 @ D24 A1 3 LINE2-R 2 LINE2-L 1 A3 B1 34,44 SPK_MUTE# INL INR /MUTE 2 +3VS PJDLC05C_SOT23-3 2 3 1 Card Reader/B CONN PJDLC05C_SOT23-3 SPDIF_PLUG# SPDIF_OUT 2 D25 1 B3 VDD SET C1843 0.1U_0402_16V4Z~D JSPD1 CONN@ G B G 2 2 1 B2 C735 0.1U_0402_16V4Z~D 2 Q10 SSM3K7002F_SC59-3~D D10 PJSOT24C_SOT23-3 C741 100P_0402_50V8J~D 2 G C MAX9736AETJ+T_TQFN32_7X7 R155 C1832 25.5_0402_1%~D .1U_0402_16V7K~D 1 33 EP Link Done C1P HDMI_IN_AUD_L HDMI_IN_AUD_R 14 2 1U_0805_25V4Z~D C1828 1U_0603_10V4Z~D 1 16 2 WM8524GEDT-R_TSSOP16 1 2 2 R154 C1831 25.5_0402_1%~D .1U_0402_16V7K~D 24,26,44 HDMI_IN_SELECT# HDMI_IN_SELECT# 2 1 1 C1830 1U_0402_6.3V6K~D D 5 3 C1829 2.2U_0603_6.3V6K~D 13 4 AIFMODE MUTE LINEVOUTL LINEVOUTR CPVOUTN AGND LINEGND VMID 15 6 B+ 1 2 3 G5 5 4 G6 6 MOLEX_53398-0471~D CONN@ +3VS 2 2 10K_0402_5%~D 12 2 10K_0402_5%~D 11 active low CPCA CPCB C163 1 R1675 20K_0402_5%~D R1883 1 R1884 1 AVDD LINEVDD 2 R1674 20K_0402_5%~D +3VS MCLK BCLK LRCLK DACDAT C1N 3 JSPK1 1 2 3 4 AMP_SPK_JK_R- 1 BOOT C1827 4.7U_0603_6.3V6K~D B 10 9 8 7 C1826 4.7U_0603_6.3V6K~D 31 BS_SPI_FUN_SEL 31 BS_I2C_ON_SPI_EN 31 BS_I2C_SRC_SEL 31 BS_RESERVED BS_SPI_FUN_SEL BS_I2C_ON_SPI_EN BS_I2C_SRC_SEL BS_RESERVED 21 L30 AMP_SPKR- 1 2 BLM18PG181SN1_0603~D L50 2 1 BLM18AG601SN1D_0603~D +3VS U4 REG COM C164 0.1U_0603_50V4Z~D 2 22 +3VS_DAC 1 VS 15 12 1 1U_0603_25V6-K~D C168 2 1 1U_0603_25V6-K~D C167 1 1U_0603_25V6-K~D C166 1 C165 2.2U_0603_10V6K~D 16 23 24 OUTR-1 OUTR-2 MONO 2 1 2 330K_0402_5% 34 SPK_AMP_MUTE# Internal Regulator Output. Internal 2V Bias. MODE A2 R148 4 + 1 C 20 Speaker Connector 15 mils trace AMP_SPK_JK_LAMP_SPK_JK_L+ AMP_SPK_JK_RAMP_SPK_JK_R+ 330P_0402_50V7K~D C162 D12 + High-Pass Filiter,16dB, Av=6.3V/V Speaker amp impedance of JBL is 4 ohm. 2 SPK_AMP_MUTE# SPK_AMP_MUTE_R# FB_R 3 18 1 19 SPK_CD_R4 2 R143 1 2 182K_0402_1% 0.022U_0402_25V7K~D 2 20K_0402_1%~D 1 D SPK_CD_R2_FBL C158 0.022U_0402_25V7K~D C159 1 2 SPK_CD_R3 1 2 R145 7 8 17 IN_L 330P_0402_50V7K~D C160 R146 1 2 182K_0402_1% PC_BEEP_2 2 0.1U_0402_10V6K~D R142 1 2 16.2K_0402_1%~D SPK_CD_R2 1 2 16.5K_0402_1% NC1 NC2 NC3 FB_L 0.022U_0402_25V7K~D 2 20K_0402_1%~D 1 R144 SPK_CD_R1 2 1U_0603_10V6K~D PC_BEEP 1 C161 R140 6 1 3 SPK_CD_R 1 C157 SPK_CD_R R141 1 2 182K_0402_1% PC_BEEP_1 2 0.1U_0402_10V6K~D 5 SPK_CD_L4 L27 AMP_SPKL+_L AMP_SPK_JK_L+ 1 2 22UH_LQH55PN220MR0L_0.85A_20%~D 1 PC_BEEP 1 C156 PC_BEEP 1 2 16.5K_0402_1% L26 AMP_SPKL+ 1 2 BLM18PG181SN1_0603~D 2 34 SPK_CD_L1 2 1U_0603_10V6K~D R138 1 2 182K_0402_1% 31 32 1 34 SPK_CD_L 1 C153 SPK_CD_L C154 0.022U_0402_25V7K~D C155 1 2 SPK_CD_L3 1 2 R139 OUTL+1 OUTL+2 TYCO_1775792-1 Link Done GND 34 SPKER_CD_L2_FBL 330P_0402_50V7K~D C152 R137 1 2 16.2K_0402_1%~D SPK_CD_L2 AMP_SPK_JK_L- 1 330P_0402_50V7K~D C151 2 0.1U_0603_50V4Z~D C149 1 1 0.1U_0603_50V4Z~D C148 1 2 22U_1210_25V6K~D C147 2 22U_1210_25V6K~D C150 1 22U_1210_25V6K~D C146 2 MAX9892ERT+T_UCSP6~D Setting the Turn-Off Time: Ton (ms) = 0.02 x Cset (pF) +3VS JIO2 16 PCIE_PTX_CARDRX_P4 16 PCIE_PTX_CARDRX_N4 16 PCIE_PRX_CARDTX_P4 A 16 PCIE_PRX_CARDTX_N4 16 CLK_PCIE_CD 16 CLK_PCIE_CD# 5,18,33,38,39,44 PLT_RST# 16 CDCLK_REQ# PCIE_PTX_CARDRX_P4 PCIE_PTX_CARDRX_N4 PCIE_PRX_CARDTX_P4 PCIE_PRX_CARDTX_N4 CLK_PCIE_CD CLK_PCIE_CD# PLT_RST# CDCLK_REQ# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CONN@ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A Compal Electronics, Inc. GND1 GND2 HRS_FH28E-20S-0.5SH(11) Link Done 5 4 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 3 2 Title Speaker AMP / CardReader_B conn Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 35 of 63 A B C D JHDD1 15 SATA_PTX_DRX_P0 15 SATA_PTX_DRX_N0 15 SATA_PRX_DTX_N0 15 SATA_PRX_DTX_P0 1 1 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P0_C 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N0_C CS9 1 CS10 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N0_C 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P0_C CS6 CS7 +3VS +3VS +5VS Close to JHDD1 2 +5VS 1 2 CS5 10U_0805_10V4Z~D 2 1 CS4 1U_0402_6.3V4Z~D 2 1 CS3 0.1U_0402_16V4Z~D 1 CS2 1000P_0402_50V7K~D 2 CS1 0.1U_0402_16V4Z~D 1 FFS_INT2_CONN 37 FFS_INT2_CONN 1 2 3 4 5 6 7 E CONN@ GND HTX+ HTXGND HRXHRX+ GND 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 VCC3.3 VCC3.3 VCC3.3 GND GND GND VCC5 VCC5 VCC5 GND RESERVED GND VCC12 VCC12 GND1 VCC12 GND2 23 24 MOLEX_47662-2100 HDD Redriver 2 +3VS 2 2 US2 6 16 A2_EQ 2 0_0402_5%~D 2 5.1K_0402_1%~D A2_EM A2_OS 2 4.3K_0402_5% RS18 1 RS20 1 RS23 1 15 SATA_PTX_DRX_P1 15 SATA_PTX_DRX_N1 15 SATA_PRX_DTX_N1 15 SATA_PRX_DTX_P1 3 17 18 19 CS29 1 CS31 1 2 0.01U_0402_16V7K~DSATA_PTX_DRX_P1_R 1 2 0.01U_0402_16V7K~DSATA_PTX_DRX_N1_R 2 CS33 1 CS35 1 2 0.01U_0402_16V7K~DSATA_PRX_DTX_N1_RC4 2 0.01U_0402_16V7K~DSATA_PRX_DTX_P1_RC 5 21 DNC DNC VDD3P3 VDD3P3 A_EN# A_EQ A_EM A_OS AI+ AIBOBO+ B_EN# B_EQ B_EM B_OS AO+ AOBIBI+ 10 20 13 7 8 9 CS27 0.1U_0402_16V4Z~D 1 B2_EQ B2_EM B2_OS RS19 2 RS21 2 RS24 2 1 0_0402_5%~D 1 5.1K_0402_1%~D 1 4.3K_0402_5% 15 SATA_PTX_DRX_P1_RC CS30 1 14 SATA_PTX_DRX_N1_RC CS32 1 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P1_C SATA_PTX_DRX_N1_C 12 SATA_PRX_DTX_N1_R CS34 1 11 SATA_PRX_DTX_P1_R CS36 1 2 0.01U_0402_16V7K~D 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N1_C SATA_PRX_DTX_P1_C EP PI3EQX6701ZDEX_TQFN20_4X4~D 3 3 JHDD2 Close to JHDD2 +3VS 2 1 2 1 2 CS23 10U_0805_10V4Z~D 1 CS22 1U_0402_6.3V4Z~D 2 SATA_PRX_DTX_N1_C SATA_PRX_DTX_P1_C CS21 0.1U_0402_16V4Z~D 1 CS20 1000P_0402_50V7K~D 2 CS19 0.1U_0402_16V4Z~D 1 SATA_PTX_DRX_P1_C SATA_PTX_DRX_N1_C +5VS +3VS 19 HDD2_DETECT# +5VS FFS_INT2_CONN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CONN@ GND HTX+ HTXGND HRXHRX+ GND VCC3.3 VCC3.3 VCC3.3 GND GND GND VCC5 VCC5 VCC5 GND RESERVED GND VCC12 VCC12 GND1 VCC12 GND2 23 24 MOLEX_47662-2100 4 4 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title SATA HDD1 & HDD2 Size B C D Rev 1.0 LA-6601P Date: A Document Number Tuesday, November 30, 2010 Sheet E 36 of 63 A B C D E 1 1 ODD power Free Fall Sensor +5VS QS1 +5VS_ODD SI3456DDV-T1-GE3_TSOP6~D D +3VS 1 7 FFS_INT1 connect to PCH GPIO & EC discuss with BIOS to use which pin S G 2 INT 1 INT 2 GND GND GND GND SDO SDA / SDI / SDO SCL / SPC RSVD CS RSVD 2 4 5 10 19 D QS2 SSM3K7002FU_SC70-3~D 2 G ODD_EN# S 1 VDD_IO VDD 8 9 1 1 6 12 13 14 2 +3VS 1 2 CS46 0.1U_0402_25V6K~D PCH_SMBDATA PCH_SMBCLK 4 RS27 1.5M_0402_5%~D 5,10,11,12,13,16,38 PCH_SMBDATA 5,10,11,12,13,16,38 PCH_SMBCLK ODD_EN DE351DLTR FFS_INT1 FFS_INT2 FFS_INT1 FFS_INT2 2 6 5 2 1 3 2 RS26 300K_0402_5%~D U19 3 2 1 CS41 1U_0402_6.3V6K~D 18 19 1 C190 10U_0805_10V4Z~D 2 2 C189 0.1U_0402_16V4Z~D 1 B+_BIAS 3 11 DE351DLTR8_LGA14_3X5~D SATA ODD Conn. +5VS JODD1 CONN@ 1 +3VS 18 @R173 @ R173 1 ODD_DA# 2 0_0402_5%~D +5VS_ODD 2 G 2 @ R159 100K_0402_5%~D ODD_DA#_R 3 1 S D FFS_INT2 1 D14 FFS_INT2_CONN 2 SDM10U45-7_SOD523-2~D FFS_INT2_CONN 36 19 ODD_DETECT# 3 Q17 SSM3K7002FU_SC70-3~D 15 SATA_PRX_DTX_P2 15 SATA_PRX_DTX_N2 15 SATA_PTX_DRX_N2 15 SATA_PTX_DRX_P2 CS45 CS44 1 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P2_C 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N2_C CS43 CS42 1 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N2_C 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P2_C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3 GND GND 17 18 FCI_10089708-016010LF~D +5VS_ODD 2 1 2 CS40 10U_0805_10V4Z~D 2 1 CS39 1U_0402_6.3V4Z~D 1 CS38 0.1U_0402_16V4Z~D 2 CS37 1000P_0402_50V7K~D 1 Link Done Placea caps. near ODD CONN. 4 4 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title SATA HDD3 & ODD & FFS Size B C D Rev 1.0 LA-6601P Date: A Document Number Tuesday, November 30, 2010 Sheet E 37 of 63 A B C D E +3VS 1 3 18 BT_ON# G 1 RU1 2 10K_0402_5%~D 1 Link Done W=40mils JMINI1 CONN@ 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 BT_ON# +3VS_WLAN 2 0_0603_5%~D 2 0_0603_5%~D MINI1_SMBCLK RE24 1 MINI1_SMBDATA RE25 1 USB20_N4 USB20_P4 @ @ WL_OFF# PLT_RST# +3VS +3VALW 2 0_0402_5%~D 2 0_0402_5%~D 53 54 55 56 2 D +3VS_BT LOTES_AAA-PCI-073-P02-A +3VS_DMC BT_RADIO_DIS# COEX2 +1.5VS_DMC 13 14 1 2 GND1 GND2 78 USB20_N5 USB20_P5 2 0_0402_5%~D PCH_SMBCLK 2 0_0402_5%~D PCH_SMBDATA UICC_CLK USB20_N5 18 USB20_P5 18 1 4 1 UICC_DATA 2 SIM Connector +UICC_PWR DP_DMC_HPD 30 DP_DMC_ML3N 30 DP_DMC_ML3P 30 +UICC_PWR SIM card board 4.7uF change to 1uF for Tiger detect issue. +UICC_PWR DP_DMC_HPD DP_DMC_ML1N DP_DMC_ML1P 5 CM1293A-04SO_SOT23-6~D R165 1M_0402_5%~D 1 2 DP_DMC_ML3N DP_DMC_ML3P 2 1 77 @ @ 2 54 56 58 60 62 64 66 68 70 72 74 76 MINI2_SMBCLK RE33 1 MINI2_SMBDATA RE34 1 3 UICC_VPP JSIM1 CONN@ UICC_VPP UICC_DATA DP_DMC_ML1N 30 DP_DMC_ML1P 30 Reserve for SIM card does not meet rise time and pull-up is needed. 5 6 7 8 4 GND VPP I/O NC NC VCC RST CLK 1 2 3 1 UICC_RESET UICC_CLK GND 10 GND 9 MOLEX_475531001~D 2 1 2 1 2 C430 0.1U_0402_16V4Z~D 54 56 58 60 62 64 66 68 70 72 74 76 DMC_RADIO_OFF# 18 6 C429 4.7U_0603_6.3V6K~D DP_DMC_ML0N DP_DMC_ML0P 53 55 57 59 61 63 65 67 69 71 73 75 DMC_RADIO_OFF# PLT_RST# 3 C428 1U_0402_6.3V4Z~D 30 DP_DMC_ML0N 30 DP_DMC_ML0P 4 DP_DMC_ML2N DP_DMC_ML2P 53 55 57 59 61 63 65 67 69 71 73 75 UICC_RESET @ R95 10K_0402_5%~D 30 DP_DMC_ML2N 30 DP_DMC_ML2P DMC_PCH_DET# DP_DMC_AUXN DP_DMC_AUXP Link Done For ESD Cap closeU41 to@JSIM1 R88 10K_0402_5%~D 16 DMC_PCH_DET# 30 DP_DMC_AUXN 30 DP_DMC_AUXP EC_TX_DAT EC_RX_CLK 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND GND AMPHE_G846A12211EU +UICC_PWR 2 2 0_0402_5%~D 2 0_0402_5%~D 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 UICC_DATA UICC_CLK UICC_RESET UICC_VPP @ RE35 1 RE36 1 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 2 +1.5VS_DMC 1 44 E51TXD_P80DATA 44 E51RXD_P80CLK 2 4 6 8 10 12 14 16 2 1 2 3 4 5 6 7 8 9 10 11 12 C431 0.1U_0402_16V4Z~D +3VS_DMC 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 1 @ C193 100P_0402_50V8J~D 2 USB20_N8 USB20_P8 R167 10K_0402_5%~D 2 18 18 C192 33P_0402_50V8J~D 2 1 CE22 0.1U_0402_16V4Z~D 2 1 CE21 0.1U_0402_16V4Z~D 1 1 CE20 4.7U_0805_10V4Z~D L94 2 1 BLM18AG601SN1D_0603~D CE19 0.1U_0402_16V4Z~D 2 CE23 4.7U_0805_10V4Z~D 1 JDMC1CONN@ 16 PCIE_PTX_WANRX_N2 16 PCIE_PTX_WANRX_P2 1 2 3 4 5 6 7 8 9 10 11 12 COEX1 +3VS_DMC PCIE_PTX_WANRX_N2 PCIE_PTX_WANRX_P2 C191 1 2 JBT CONN@ 16 BT_DET# Display Mini Card (DMC) PCIE_PRX_WANTX_N2 PCIE_PRX_WANTX_P2 3 0.1U_0402_16V4Z~D L93 2 1 BLM18PG330SN1D_2P~D 16 PCIE_PRX_WANTX_N2 16 PCIE_PRX_WANTX_P2 QU2 SSM3K7002F_SC59-3~D S Bluetooth +3VS 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 1 2 G PCH_SMBCLK 5,10,11,12,13,16,37 PCH_SMBDATA 5,10,11,12,13,16,37 19 BT_RADIO_DIS# 3 +3VS_BT_D 18 5,18,33,35,39,44 USB20_N4 18 USB20_P4 18 +1.5VS PCIE_WAKE# @ RE30 @RE30 1 2 0_0402_5%~D 1 COEX2 R163 1 2 0_0402_5%~D 3 COEX1 R162 1 2 0_0402_5%~D 5 MINI2CLK_REQ# 7 16 MINI2CLK_REQ# 9 CLK_PCIE_MINI2# 11 16 CLK_PCIE_MINI2# CLK_PCIE_MINI2 13 16 CLK_PCIE_MINI2 15 2 @ BT_ON# WL_OFF# PLT_RST# RE22 1 @ RE23 1 G1 G2 G3 G3 18 2 1 @ +3VS +1.5VS 1 PCIE_PTX_WLANRX_N1 PCIE_PTX_WLANRX_P1 16 PCIE_PTX_WLANRX_N1 16 PCIE_PTX_WLANRX_P1 1 2 PCIE_PRX_WLANTX_N1 PCIE_PRX_WLANTX_P1 16 PCIE_PRX_WLANTX_N1 16 PCIE_PRX_WLANTX_P1 1 +3VS_BT +3VS 1 2 4 6 8 10 12 14 16 2 2 4 6 8 10 12 14 16 @ 1 3 5 7 9 11 13 15 RU2 300_0603_5% 16 MINI1CLK_REQ# 16 CLK_PCIE_MINI1# 16 CLK_PCIE_MINI1 @ RE12 1 2 0_0402_5%~D 1 R160 1 2 0_0402_5%~D 3 R161 1 2 0_0402_5%~D 5 MINI1CLK_REQ# 7 9 CLK_PCIE_MINI1# 11 CLK_PCIE_MINI1 13 15 CU5 0.1U_0402_16V4Z~D PCIE_WAKE# COEX2 COEX1 CU4 4.7U_0805_10V4Z~D 17,33,39,44 PCIE_WAKE# @ 1 2 QU1 AO3413_SOT23-3~D 2 D 2 CU2 1U_0603_10V4Z~D 2 1 CE17 0.1U_0402_16V4Z~D 2 1 CE16 0.1U_0402_16V4Z~D 2 1 CE15 4.7U_0805_10V4Z~D 2 1 CE14 0.1U_0402_16V4Z~D 2 1 CE13 0.1U_0402_16V4Z~D WLAN CE12 4.7U_0805_10V4Z~D 1 +3VS S +1.5VS 4 LOTES_AAA-PCI-112-K01 Compal Electronics, Inc. Link Done PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title Mini Card WLAN / DMC / BT Size B C D Rev 1.0 LA-6601P Date: A Document Number Tuesday, November 30, 2010 Sheet E 38 of 63 5 4 3 +1.5V to +1.05V Transfer 16 PCIE_PTX_USB3RX_P6 16 PCIE_PTX_USB3RX_N6 PETXP PETXN PERXP PERXN SPEC Max:+3V---200mA;+1.05V---800mA Idle mode:0.489W: +3V---43mA;+1.05V---328mA D3 mode:0.066W: +3V---5.4mA;+1.05V---45mA R181 R182 5,18,33,35,38,44 PLT_RST# 17,33,38,44 PCIE_WAKE# R185 @ R186 R187 @ R201 R202 +3V +3V 18 USB3_SMI# +3V R188 2 0_0402_5%~D H2 2 0_0402_5%~D K1 CLKREQ_USB3 K2 10K_0402_1%~D 2 2100_0402_1%~D J2 2 10K_0402_1%~D J1 2 0_0402_5%~D H1 2 0_0402_5%~D P4 1 1 1 1 1 1 1 2 10K_0402_1%~D 1 1 2 D17 1 2 1SS355TE-17_SOD323-2 P5 1 2 C254 1U_0603_10V6K~D SPI_CLK_USB 1 2 M2 SPI_CS_USB# R337 0_0402_5%~D N2 USB_SO_SPI_SI N1 USB_SI_SPI_SO M1 2 +3V +3V K13 K14 J13 P13 D7 A6 N8 U3TX_C_DN2 1 U2DN2_L U2DP2 U3RXDP2 P8 B8 C251 U2DP2_L .1U_0402_16V7K~D U3RXDP2_L A8 U3RXDN2_L AUXDET PSEL SMI SMIB PONRSTB PPON2 PPON1 H14 J14 U3TXDP1 B10 PCI Express/ExpressCard select signal 1:others 0:Express Card or Mini card SPISCK SPISCB SPISI SPISO U3TXDN1 U2DM1 U2DP1 U3RXDP1 GND GND GND U3RXDN1 U3TXDN2_L U3TXDN2_L 2 1 U3TXDN2 U3TXDP1_L 3 U3RXDN1_L 2 U3RXDN2_L 2 1 U3RXDN2 U3RXDP1_L 3 +3V 1 P6 1 SPI_CS_USB# USB_SI_SPI_SO MX25L5121EMC-20G_SO8 USB3_XT1 USB3_XT2 1 2 USB3_XT2_R A10 U3TX_C_DN1 1 N10 U2DN1_L U3RXDN2 U3RXDP2 U3TXDN2 U3TXDP2 2 Pin compare table for support USB remote wakeup or not AUXDET(Pin J2) CSEL(Pin P6) CLK Support USB remote wakeup pull high 10k to VDD33 Tied to GND Must use 24MHz crystal: mount Y1,R19,C40,C41 Not support USB remote wakeup Tied to GND pull high to VDD33 Can use either 48MHz or 24MHz When use 48MHz clock: mount R22,R25 5 3 1 U2DN2 U2DN1_L 2 +USB3_VCCA C253 U2DP1_L .1U_0402_16V7K~D U3RXDP1_L A12 U3RXDN1_L RR+ TT+ VCC GND DD+ 8 7 6 5 1 4 U2DP1 1 U2DN1 U3RXDN1 U3RXDP1 U3TXDN1 U3TXDP1 1 2 3 4 +5VALW U26 1 2 3 4 USB_PWR_EN# JUSB1 U3RXDN2 U3RXDP2 U3TXDN2 U3TXDP2 VCC GND DD+ OC1# OUT1 OUT2 OC2# 1 2 3 4 5 6 7 8 9 U2DN1 U2DP1 R190 10K_0402_5%~D 1 2 OCI2B +USB3_VCCB 2.0A GND IN EN1# EN2# OC1# OUT1 OUT2 OC2# W=60mils 8 7 6 5 B R195 10K_0402_5%~D 1 2 OCI1B +USB3_VCCA CONN@ VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+ For ESD request GND GND R199 1 2 0_0603_5%~D R200 1 2 0_0603_5%~D C258 1 USBGND1 10 11 1 + 2 2 .1U_0402_16V7K~D SUYIN_020052GR009M2126L Link Done +USB3_VCCB 8 7 6 5 W=60mils 8 7 6 5 TPS2062ADR_SO8~D +USB3_VCCA U2DN2 U2DP2 GND IN EN1# EN2# U27 1 2 3 4 USB_PWR_EN# 40,44 USB_PWR_EN# RR+ TT+ 2.0A TPS2062ADR_SO8~D +5VALW D6 8/11 update +USB3_VCCB +USB3_VCCA C255 .1U_0402_16V7K~D 1 2 2 1.6K_0402_1%~D C LXES4XBAA6-027_MSOP8 1 2 +USB3_VCCB JUSB2 U2DN1 U2DP1 U3RXDN1 U3RXDP1 U3TXDN1 U3TXDP1 1 2 3 4 5 6 7 8 9 VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+ CONN@ For ESD request GND GND 10 11 USBGND2 R204 1 2 0_0603_5%~D R205 1 2 0_0603_5%~D C329 1 1 + 2 2 .1U_0402_16V7K~D SUYIN_020052GR009M2126L Link Done UPD720200AF1DAPA_FBGA176P-NH~D 1 2 A Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title USB3.0 PD720200 Size 3 2 Document Number Rev 1.0 LA-6601P Date: 4 2 For ESD request U2DN2 U2DP2 N11 P14 P11 P9 P7 P2 P1 N13 N9 N7 N3 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 L12 L11 L7 L6 4 D16 C256 .1U_0402_16V7K~D 1 2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 3 WCM-2012-670T_4P LXES4XBAA6-027_MSOP8 P10 B12 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 2 1 2 3 4 U3TXDN1_L 2 C12 C13 D3 D4 D11 D12 D13 D14 E1 E2 E13 E14 F4 F6 F7 F8 F9 F11 F12 G1 G2 G6 G7 G8 G9 G11 G12 G13 H6 H7 H8 H9 H12 J3 J4 J6 J7 J8 J9 J11 J12 K3 K4 L1 L2 L3 L4 1 C260 12P_0402_50V8J~D C259 12P_0402_50V8J~D A 2 U2DP1_L WCM-2012-670T_4P C252 .1U_0402_16V7K~D U3TX_C_DP1 1 2 U3TXDP1_L P/N: SA000048H0L (S IC UPD720200AF1-DAP-A FBGA 176P USB3.0) A version GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 1 U2DP2 C794 10U_0603_6.3V6M~D Y2 1 A1 A2 A3 A4 A5 A7 A9 A11 A13 A14 B3 B4 B5 B7 B9 B11 B13 B14 C1 C2 C3 C10 C11 2 4 +3V XT1 XT2 CSEL 4U3RXDP1 C244 150U_D _10VM_R40M~D Place as close as possibile to R198 100_0402_5%~DU3.N14 and U3.M14 24MHZ_12PF_X5H024000DC1H 1 U3AVSS 1U3RXDN1 C793 10U_0603_6.3V6M~D 1 2 3 4 CS# SO WP# GND USB3_XT1 N14 USB3_XT2 M14 4 For ESD request R191 1 4U3TXDP1 L38 3 D15 P12 N12 1U3TXDN1 C247 150U_D _10VM_R40M~D VCC NC SCLK SI GND 2 1 2 2 1 U28 8 7 SPI_CLK_USB 6 USB_SO_SPI_SI 5 RREF U2AVSS U2PVSS R207 0_0402_5%~D 1 R193 47K_0402_5%~D R192 10K_0402_1%~D 2 C257 .1U_0402_16V7K~D R1555 10K_0402_1%~D 1 2 +3VALW C14 @ +3VALW R196 0_0402_5%~D Q19 SSM3K7002FU_SC70-3~D B As short as possible CLKREQ_USB3 2 S 1 3 D 16 USB30_CLKREQ# 1 D DLW21SN670HQ2L_4P L37 2 2 L36 4 U3RXDP2 U2DN2_L 2 1 DLW21SN670HQ2L_4P U3RXDP2_L 3 3 2 1 L34 U3TXDN1_L 2 U2DP2_L 1 For EMI request 4 U3TXDP2 DLW21SN670HQ2L_4P R183 10K_0402_5%~D 1 2 1 2 R184 10K_0402_5%~D G14 OCI2B H13 OCI1B 2 L35 U3TXDN2 U2DM2 OCI2B OCI1B 2 1 DLW21SN670HQ2L_4P B6 Can be attach to EC, either. 2 1 L33 U3TXDP2 2 2 1 U3TXDP2_L 3 2 G R189 10K_0402_1%~D PERSTB PEWAKEB PECREQB 2 2 1 For EMI request C245 .1U_0402_16V7K~D U3TX_C_DP2 1 2 U3TXDP2_L U3RXDN2 C 1 U2AVDD10 U3AVDO33 H11 K11 K12 L8 VDD10 VDD10 VDD10 VDD10 H3 H4 L5 VDD10 VDD10 VDD10 E11 E12 VDD10 VDD10 E3 E4 VDD10 VDD10 C8 C9 D8 D9 VDD10 VDD10 VDD10 VDD10 C4 C5 C6 C7 D5 VDD10 VDD10 VDD10 VDD10 VDD10 L13 L14 VDD33 VDD33 L9 L10 VDD33 VDD33 F3 G3 G4 VDD33 VDD33 VDD33 D10 F13 F14 VDD33 VDD33 VDD33 F2 F1 N4 N5 N6 P3 1 2 PCIE_PTX_USB3RX_P6 PCIE_PTX_USB3RX_N6 PECLKP PECLKN +3VA L39 BLM18AG601SN1D_2P 1 2 VDD33 VDD33 VDD33 VDD33 GND 1 2 .1U_0402_16V7K~D PCIE_PRX_USB3TX_C_P6 D2 2 .1U_0402_16V7K~D PCIE_PRX_USB3TX_C_N6 D1 C246 1 C250 1 16 PCIE_PRX_USB3TX_P6 16 PCIE_PRX_USB3TX_N6 B2 B1 2 1 C233 0.01U_0402_16V7K~D CLK_PCIE_USB30 CLK_PCIE_USB30# 16 CLK_PCIE_USB30 16 CLK_PCIE_USB30# 2 1 C232 0.01U_0402_16V7K~D GND RT9701-PB_SOT23-5 +3V 2 1 C239 0.01U_0402_16V7K~D 2 U50 0.2A +3VA 2 1 C231 0.01U_0402_16V7K~D VIN VOUT VIN/CE VOUT +1.05VR 2 1 C238 .1U_0402_16V7K~D SYSON 1 5 2 1 C792 10U_0603_6.3V6M~D 44,47,54 3 4 R180 0_0805_5% 1 2 +1.05V 2 1 C222 .1U_0402_16V7K~D +3V +3V U24 1 C225 .1U_0402_16V7K~D +3VALW to +3V Transfer 2 C230 0.01U_0402_16V7K~D 1 @ R1967 2 C237 0.01U_0402_16V7K~D 2 0_0603_5%~D 2 0_0603_5%~D R1966 +3VS 2 1 C224 0.01U_0402_16V7K~D 2 1 +3VALW 2 1 C236 .1U_0402_16V7K~D 1 2 1 C235 0.01U_0402_16V7K~D R1957 32.4K_0402_1%~D 2 1 C241 0.01U_0402_16V7K~D FB 1 R178 2 10K_0402_1%~D 1 C229 0.01U_0402_16V7K~D 2 1.042 ~ 1.0469 ~ 1.0519V Spec: 0.9975 ~ 1.05 ~ 1.1025 +3V_3.0 1 +3V_3.0 SYSON 8 EN 2 1 7 POK R177 5.1K_0402_1%~D APL5930KAI-TRG_SO8 Vout=0.8(1+10K/32.4K) C228 0.01U_0402_16V7K~D 1 @ R1963 @ C234 8P_0402_50V8D~D 2 0_0603_5%~D 2 0_0603_5%~D R1962 +1.5VS C227 0.01U_0402_16V7K~D 1 +1.5V 1A 3 4 VOUT VOUT C240 .1U_0402_16V7K~D +5VALW VCNTL VIN VIN @ C223 8P_0402_50V8D~D 6 5 9 C221 0.01U_0402_16V7K~D 2 +1.05VR +3VA C226 .1U_0402_16V7K~D 1 +3VA +1.05V U23 C242 10U_0603_6.3V6M~D D +1.5V_3.0 C220 10U_0603_6.3V6M~D 2 C219 1U_0603_10V6K~D 1 1 Close to U50.P13 +3V +5VALW +1.5V_3.0 +5VALW +1.5V_3.0 2 Close to U50.D7 Tuesday, November 30, 2010 Sheet 1 39 of 63 A B C D E +5VALW 1 2 1 Power share C263 0.1U_0402_16V4Z~D 2 C262 10U_1206_16V4Z 1 USB charger Power 2.0A PWRSHARE_EN# 1 PWRSHARE_EN_R# 2 R1699 10K_0402_5%~D GND IN EN1# EN2# CEN DM DP GND GND CB TDM TDP VCC 8 7 6 5 PWRSHARE_OE# USB20_N9 USB20_P9 MAX14566EETA+_TDFN-EP8_2X2~D PWRSHARE_OE# 44 USB20_N9 18 USB20_P9 18 44 PWRSHARE_EN_EC# 8 7 6 5 USB_OC2# 1 18 1 S OE# Function X H L H L L Disconnect D=1D D=2D 2 2 1 1 D31 1SS355TE-17_SOD323-2 +5VALW 2 C261 0.1U_0402_16V4Z~D 1 2 3 4 9 OC1# OUT1 OUT2 OC2# TPS2062ADR_SO8~D U30 PWRSHARE_EN# SW_USB20_N9 SW_USB20_P9 +5V_CHGUSB U29 1 2 3 4 @ R206 PWRSHARE_OE# R203 1 2 100K_0402_5%~D PWRSHARE_EN# R97 2 10K_0402_5%~D 2 0_0402_5%~D 1 L40 1 SW_USB20_P9 1 SW_USB20_N9 4 1 2 4 3 2 USB20_P9_CONN 3 USB20_N9_CONN WCM2012F2S-900T04_0805 1 +3VS NC NC VDD VDD 10 20 3 17 18 19 NC NC MODE(VDD) EN A_EQ B_EQ A_EM B_EM 13 7 8 9 B1_EQ B1_EM 15 SATA_PTX_DRX_P4 15 SATA_PTX_DRX_N4 CS11 1 CS13 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P0_R 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N0_R 2 15 SATA_PRX_DTX_N4 15 SATA_PRX_DTX_P4 CS15 1 CS17 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N0_RC 4 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P0_RC 5 21 RS7 RS9 2 D18 USB20_P9_CONN 6 5 +5VALW 1 0_0402_5%~D 1 15K_0402_1%~D 2 2 4 V I/O 1 V I/O 3 V I/O 2 IP4223CZ6_SO6~D AI+ AI- AO+ AO- 15 14 SATA_PTX_DRX_P0_R4 SATA_PTX_DRX_N0_R4 BOBO+ BIBI+ 12 11 SATA_PRX_DTX_N0_R4 SATA_PRX_DTX_P0_R4 HEATGND PI3EQX4951STZDEX_TQFN20_4X4~D 1 + 2 V BUS Ground V I/O USB20_N9_CONN 1 2 C265 0.1U_0402_16V4Z~D 1 150K_0402_1%~D MODE A1_EQ 1 0_0402_5%~D 1 5.1K_0402_1%~D A1_EM @RS11 @ RS11 2 RS6 2 RS8 2 2 6 16 +5V_CHGUSB C264 150U_B2_6.3V-M~D US3 0_0402_5%~D L40 close to JESA1 CS8 0.1U_0402_16V4Z~D 1 2 2 @ R209 2.0A USB/ESATA CONN JESAT1 CONN@ D18 close to JESA1 1 2 3 4 USB20_N9_CONN USB20_P9_CONN ESATA repeater SATA_PTX_DRX_P0_R4 CU6 SATA_PTX_DRX_N0_R4 CU7 1 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P4_C 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N4_C SATA_PRX_DTX_N0_R4 CU8 SATA_PRX_DTX_P0_R4 CU9 1 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N4_C 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P4_C 5 6 7 8 9 10 11 USB USB_V USB_DUSB_D+ USB_GND GND A+ ESATA AGND GND BGND B+ GND GND GND 12 13 14 15 TYCO_1759599-3~D Link Done 2.0A +5VALW 3 +5V_USB2_A U32 1 2 3 4 39,44 USB_PWR_EN# USB_OC0# 18 18 USB20_N0 18 USB20_P0 USB20_N0 1 USB20_P0 4 1 2 3 4 GND IN EN1# EN2# 3 USB20_N0_CONN 3 USB20_P0_CONN 4 +5VALW 5 I/O 3 VDD I/O 2 GND USB20_N0_CONN 3 1 + +5V_USB2_B 8 7 6 5 I/O 4 I/O 1 1 USB20_P0_CONN 3 USB20_N1_CONN D29 @ USB_OC1# 18 2 1 2 0_0402_5%~D 4 I/O 3 I/O 2 18 USB20_N1 USB20_P1 4 2 4 3 +5VALW VDD GND 1 2 0_0402_5%~D L41, L42 close to JUSB3, JUSB4 USB power 1 I/O 4 I/O 1 USB20_P1_CONN 1 +5V DD+ GND GNDGND 6 5 SUYIN_020133MR004M25GZL Link Done 2.0A + 6 2 2 IP4223CZ6_SO6-6 Place near USB connector JUSB4 CONN@ 1 2 3 4 USB20_N1_CONN USB20_P1_CONN 2 USB20_P1_CONN 3 WCM2012F2S-900T04_0805 @R215 @ R215 5 1 1 2 C270 0.1U_0402_16V4Z~D USB20_P1 1 USB20_N1_CONN 2 C268 150U_B2_6.3V-M~D 18 1 JUSB3 CONN@ 1 2 3 4 USB20_N0_CONN USB20_P0_CONN +5V_USB2_B L42 USB20_N1 USB CONN 2.0A 2 2 0_0402_5%~D 1 @R214 @ R214 OC1# OUT1 OUT2 OC2# TPS2062ADR_SO8~D C275 0.1U_0402_16V4Z~D C274 10U_1206_16V4Z 4 4 2 IP4223CZ6_SO6-6 2.0A 2 2 6 USB_PWR_EN# 2 1 @ R213 U33 1 +5V_USB2_A D22 @ WCM2012F2S-900T04_0805 +5VALW 1 3 2 0_0402_5%~D 1 L41 C271 0.1U_0402_16V4Z~D 2 8 7 6 5 C269 150U_B2_6.3V-M~D 1 @ R212 OC1# OUT1 OUT2 OC2# TPS2062ADR_SO8~D C273 0.1U_0402_16V4Z~D 2 C272 10U_1206_16V4Z 1 GND IN EN1# EN2# +5V DD+ GND GNDGND 6 5 SUYIN_020133MR004M25GZL Link Done 4 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title USB/ESATA TS3USB221RSER Size B C D Rev 1.0 LA-6601P Date: A Document Number Tuesday, November 30, 2010 Sheet E 40 of 63 5 4 3 2 1 +3.3V_F347 +3.3V_F347 6 VDD 4 5 D+ D- 7 8 REGIN VBUS C1716 C1721 C1717 C1722 C1718 1 1 1 1 1 1 1 1 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 9 10 RST#/C2CK P3.0/C2D 18 17 16 15 14 13 12 11 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 4.7K_0402_5%~D 2 1 R1570 I2C_CLK 4.7K_0402_5%~D 2 1 R1571 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 GND 2 1 32 31 30 29 28 27 SPI_MOCLK SPI_MOCLK_R 1 2 SPI_MOSO R1564 0_0402_5%~D SPI_MOSI SPI_MOCS# I2C_DAT I2C_DAT 42,43 I2C_CLK I2C_CLK 42,43 C1710 @ 1 2 0.1U_0402_16V4Z~D R1576 1 2 1K_0402_5%~D +3.3V_F347 26 25 24 23 22 21 20 19 SLP_S3 BATT_CHG_LED 10K_0402_5% 2 1 R1841 +3.3V_F347 ACIN# LID_SW_IN#_D LID_SW_IN# 2 1 BATT_LOW_LED D70 SLP_S5 SDMK0340L-7-F_SOD323-2~D C1713 @ 1 2 0.1U_0402_16V4Z~D C1714 @ 1 2 0.1U_0402_16V4Z~D D LID_SW_IN# 16,42,44 3 C8051F347-GQ_LQFP32_7X7 @ C1720 GND1 GND2 7 8 C1715 We are Green SA00003IR20 U604 SPI_MOSI 15_0402_5% 2 1 R1584 5 DI SPI_MOCLK_R 15_0402_5% 2 1 R1583 6 CLK +3.3V_F347 2 2 2 2 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 1 2 1 2 R1580 R1582 SPI_MOCS# 10K_0402_5%~D 1 7 10K_0402_5%~D 1 2 R1581 3 10K_0402_5%~D +3.3V_F347 1 2 8 C1724 22P_0402_50V8J~D 2 C1723 0.1U_0402_16V4Z~D 2 0.1U_0402_16V4Z~D C 2 0.1U_0402_16V4Z~D AMPHE_G846A06201EU 2 0.1U_0402_16V4Z~D CONN@ Cloase to JP1 1 2 3 4 5 6 1 2 3 4 5 6 C1719 2 +3.3V_F347 JP1 C1730 0.1U_0402_16V4Z 1 R1577 1K_0402_1%~D @ +3.3V_F347 I2C_DAT U602 2 @ 2 1 @ 2 1 C1712 0.1U_0402_16V4Z~D C1711 1U_0805_10V7 1 +3.3V_F347 place R1564 as close as U602 USB20_P6 USB20_N6 @ 2 0_0603_5%~D 1 +3.3V_F347 @ @ 2 USB20_P6 USB20_N6 W=40mils @ R1575 1 2 0_0603_5%~D @ +5VS R1572 1 2 18 18 D +5VALW 1 C1708 22P_0402_50V8J~D 2 C1707 0.1U_0402_16V4Z~D 1 C1706 0.1U_0402_16V4Z~D 2 C1705 1U_0805_10V7 1 +3.3V_F347_R 1 R1569 2 0_0603_5%~D 1 2 SO 2 2 15_0402_5% SPI_MOSO R1585 1 CS HOLD WP C VCC VSS 4 EN25F80-75HCP_SO8 1 +3.3V_F347 +3.3V_F347 +3VALW J11 @ 2 2 D +3.3V_F347 1 17,44 PM_SLP_S5# G 3 2 1 B+_BIAS Q213 SSM3K7002F_SC59-3~D 3 2 1 +3VALW 1 +3.3V_F347 3V_F347_ON 3 Q216 SSM3K7002F_SC59-3~D 2 G S 1 44 1 A 44 BATT_CHG_LED# 2 G S BATT_CHG_LED D Q249 SSM3K7002F_SC59-3~D 1 2 G S Q215 3 SSM3K7002F_SC59-3~D 2 G S +3.3V_F347 behavior STATE S0 S3 S4 S5 1 2 AC IN ON ON ON ON BAT only ON ON OFF OFF AC mode battery full in S5:turn off ELC controller 3 2 2 D 44 BATT_LOW_LED# 1 R1593 100K_0402_1%~D R1592 100K_0402_1%~D 2 2 1 D BATT_LOW_LED 2 C1727 0.1U_0402_25V6K~D D +3.3V_F347 1 R1815 300K_0402_5%~D R1590 100K_0402_1%~D Q214 SSM3K7002F_SC59-3~D R1664 100K_0402_1%~D R1632 100K_0402_1%~D 1 2 1 C1725 4.7U_0603_6.3V6M~D 4 ACIN# 1 2 G S 6 5 2 1 3 R1589 100K_0402_1%~D 14,17,44,50 ACIN B SI3456DDV-T1-GE3_TSOP6~D C1726 0.1U_0402_25V6K~D D 1 Q212 Q211 SSM3K7002F_SC59-3~D S 2 JUMP_43X118 1 2 G R1588 100K_0402_1%~D SLP_S5 1 1 B ADDRESS 000b 001b 000b +3.3V_F347 R1587 100K_0402_1%~D 3 2 S 1 2 G 2 Q210 SSM3K7002F_SC59-3~D 1 17,44 PM_SLP_S3# SLP_S3 1 SMBUS 0100 0100 1010 D D DEVICE MAXIM - LED MAXIM - GPIO I2C EEPROM S 2 R1586 100K_0402_1%~D A DELL CONFIDENTIAL/PROPRIETARY 3 Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title ELC (1) Size 4 3 2 Rev 1.0 LA-6601P Date: 5 Document Number Tuesday, November 30, 2010 Sheet 1 41 of 63 5 43 4 3 2 1 7313_INT# +3.3V_F347 +3.3V_F347 1 2 1 1 2 R1597 4.7K_0402_1%~D 4.7K_0402_1%~D R1596 2 2 21 19 20 1 SCL SDA 2 44 TP_CLK TP_DATA +3VALW 44 +3.3V_F347 2 1 2 JTPMB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TP_CLK TP_DATA LID_SW_IN# TP_LED_R_DRV# TP_LED_G_DRV# TP_LED_B_DRV# 3 TP_CLK 2 TP_DATA 1 +3.3V_F347 1 1 22 2 1 2 1 2 2 U608 7313_INT# V+ 21 SCL SDA 2 +5VALW D 1 1 S +5VS 2 Q217 SSM3K7002F_SC59-3~D R1603 100K_0402_5%~D HDD_B 44 44 44 1 2 R1602 100K_0402_5%~D D HDD_R D 16,41,44 LID_SW_IN# 1 LED_R_7313#_1 LED_B_7313#_1 LED_G_7313#_1 CAPS_LED# NUM_LED# SCR_LED# 44 44,46 44,46 44,46 44,46 32 2 1 2 3 4 5 6 7 8 GND1 GND2 +5VS 1 2 CONN@ JLOGO 20mil 1 2 3 4 5 6 1 2 3 4 7 5 G7 8 6 G8 MOLEX_53398-0671~D LID_SW LOGO_LED_R_DRV# LOGO_LED_G_DRV# LOGO_LED_B_DRV# 1 2 C JSPK2 LSPK_LED_R_DRV# LSPK_LED_G_DRV# LSPK_LED_B_DRV# RSPK_LED_R_DRV# RSPK_LED_G_DRV# RSPK_LED_B_DRV# Link Done 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 11 6 12 7 8 9 10 FOX_HS8108E CONN@ 11 12 FOX_HS6110E-M~D CONN@ Link Done Link Done LOGO Board CONN SPK LED Board CONN Q222 SSM3K7002F_SC59-3~D 2 G S Q218 SSM3K7002F_SC59-3~D 2 G KSI3 KSI5 KSI7 KSO9 Link Done JCAP 1 2 3 4 5 6 7 8 9 10 WLES ON/OFF LED# KSI3 KSI5 KSI7 KSO9 PWR_G_7313# PWR_B_7313# Media Board CONN 1 Num LED CONN 1 G2 D LED_B_7313#_1 WLES ON/OFF LED# +5VS LID_SW 3 HDD_B_7313# SATA_LED_ACT CAPS_LED# NUM_LED# SCR_LED# G1 2 20mil 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 AMPHE_G846A302101EU +5VS 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 C1735 0.1U_0402_16V4Z 1 P0 2 P1 3 P2 AD2_0 LED_R_7313#_1 18 4 AD0 P3 AD2_1 LED_G_7313#_1 23 5 AD1 P4 AD2_2 LED_B_7313#_1 24 6 AD2 P5 7 P6 HDD_R_7313# 14 8 P7 HDD_G_7313# 15 P12 10 P8 HDD_B_7313# 16 P13 PWR_R_7313# 11 P14 P9 PWR_G_7313# 17 12 OSC P10 PWR_B_7313# 13 P11 9 25 GND GND MAX7313DATG+T_TQFN-EP24_4X4~D 2 G 31 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 C1736 0.1U_0402_16V4Z 1 INT#/O16 KSI2 KSI4 KSI6 KSO3 LID_SW PWR_R_7313# KSI2 KSI4 KSI6 KSO3 C1732 0.1U_0402_16V4Z R1601 4.7K_0402_1%~D 2 19 20 44,46 44,46 44,46 44,46 Touchpad LED CONN C1729 0.1U_0402_16V4Z C I2C_CLK I2C_DAT LED_R_7313#_1 LED_G_7313#_1 Link Done C1733 0.1U_0402_16V4Z 4.7K_0402_1%~D R1600 4.7K_0402_1%~D R1598 4.7K_0402_1%~D R1599 1 JMEDIA CONN@ 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 MOLEX_53398-1371~D CONN@ D71 PJSOT05C_SOT23-3 CAP, Media, Eyes, Rim 1 2 3 4 5 6 7 8 9 10 11 12 13 GND1 GND2 1 C1744 0.1U_0402_16V4Z V+ LSPK_LED_R_DRV# 1 P0 LSPK_LED_G_DRV# 2 P1 LSPK_LED_B_DRV# 3 P2 AD0_0 RSPK_LED_R_DRV# 18 4 AD0 P3 AD0_1 RSPK_LED_G_DRV# 23 5 AD1 P4 AD0_2 RSPK_LED_B_DRV# 24 6 AD2 P5 7 P6 TP_LED_R_DRV# 14 8 P12 P7 TP_LED_G_DRV# 15 10 P13 P8 TP_LED_B_DRV# LOGO_LED_R_DRV# 16 11 P14 P9 LOGO_LED_G_DRV# 17 12 OSC P10 LOGO_LED_B_DRV# 13 P11 9 25 GND GND MAX7313DATG+T_TQFN-EP24_4X4~D 41,43 I2C_CLK 41,43 I2C_DAT I2C_CLK I2C_DAT INT#/O16 C1745 0.1U_0402_16V4Z 22 +5VALW +5VS +5VS_TP_LED C555 0.1U_0402_16V4Z~D U605 C554 0.1U_0402_16V4Z~D D 1 L/R Headlight, Logo +5VS C1728 0.1U_0402_16V4Z~D 4.7K_0402_1%~D R1594 1 R1595 2 4.7K_0402_1%~D 3 B B AD1 AD0 0 1 0 L/R Headlight , Logo, TP 1 Num, CAP , SCR EJECT, REV, PLAY/PAUSE FFWD, Vol_DWN, Vol_UP Wireless ON/OFF AWCC Button Alien Adrenaline Power Button Eyes Power Button Rim 0 1 5 D 44 EN_TPLED# MAX7313 2 G Q44 S S G 3 1 D 2 2 1 EN_TPLED 3 2 1 2 46 ON/OFFBTN# C185 0.1U_0402_25V6K~D AD2 A U608 3 HDD_G_7313# 2 R1654 1.5M_0402_5%~D U605 S 1 SSM3K7002FU_SC70-3~D S Q221 SSM3K7002F_SC59-3~D LID_SW 2 G Q220 SSM3K7002F_SC59-3~D 1 D 1 1 3 D 2 G Reference SATA_LED_ACT HDD_G C1737 0.1U_0402_16V4Z 3 +5VS Q45 +5VS_TP_LED SI3456DDV-T1-GE3_TSOP6~D 6 5 4 2 1 1 C184 1U_0603_10V4Z~D S HDD_R_7313# +5VS 0.1U_0402_16V4Z C1746 2 G B+_BIAS 3 R166 300K_0402_5%~D 15 PCH_SATALED# 1 Q219 SSM3K7002F_SC59-3~D D S 1 2 JBTN CONN@ 1 2 3 4 5 6 ON/OFFBTN# HDD_R HDD_G HDD_B 1 2 3 4 5 6 G7 G8 7 8 MOLEX_53398-0671~D Link Done Touchpad LED circuit PWR BTN Board CONN A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 4 3 2 Title ELC (2) Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet 1 42 of 63 5 4 14 15 16 17 P12 P13 P14 OSC 1 2 9 GND 6 1 3 2 2 S JKBBL1 CONN@ S Q262A DMN66D0LDW-7_SOT363-6~D Q262B DMN66D0LDW-7_SOT363-6~D +3VS KB_LED_G2_DRV# 1 R1610 4.7K_0402_1%~D R1611 4.7K_0402_1%~D MAX7313DATG+T_TQFN-EP24_4X4~D +5VS F4 +3VS 5 KB_LED_G2_DRV KB_LED_G2_DRV#_A# 2 D 1 6 2 D KB_LED_B4_DRV D 2 Q266A DMN66D0LDW-7_SOT363-6~D KB_LED_B4_DRV#_A# 6 5 D G G 4 S Q269A DMN66D0LDW-7_SOT363-6~D Q269B DMN66D0LDW-7_SOT363-6~D S S Q266B DMN66D0LDW-7_SOT363-6~D A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 4 Q265B DMN66D0LDW-7_SOT363-6~D B 1 2 3 KB_LED_B4_DRV# Title ELC (3) Size 3 2 Document Number LA-6601P Date: 5 Q265A DMN66D0LDW-7_SOT363-6~D 6 4 D Q273A S DMN66D0LDW-7_SOT363-6~D Q273B S DMN66D0LDW-7_SOT363-6~D Q264A DMN66D0LDW-7_SOT363-6~D 1 2 3 2 1 2 1 S S S G G D 1 3 2 4 6 1 D 2 G R1626 4.7K_0402_1%~D KB_LED_G3_DRV#_A# G G 4 5 2 1 3 2 KB_LED_B3_DRV# KB_LED_B3_DRV 5 4 1 R1631 4.7K_0402_1%~D 3 2 KB_LED_G3_DRV# KB_LED_B3_DRV#_A# R1630 4.7K_0402_1%~D KB_LED_G3_DRV 2 +3VS R1627 4.7K_0402_1%~D 6 R1629 4.7K_0402_1%~D KB_LED_G4_DRV D Q268A DMN66D0LDW-7_SOT363-6~D Q268B DMN66D0LDW-7_SOT363-6~D R1628 4.7K_0402_1%~D 1 Q272B DMN66D0LDW-7_SOT363-6~D KB_LED_G4_DRV#_A# D 1 4 +3VS 1 +3VS S +3VS S +3VS A 2 Q272A DMN66D0LDW-7_SOT363-6~D G 1 S S D Q264B S DMN66D0LDW-7_SOT363-6~D G G G 4 2 D D 5 +3VS G 4 5 D KB_LED_B1_DRV#_A# 6 2 3 2 KB_LED_B1_DRV# KB_LED_B1_DRV 5 2 KB_LED_G4_DRV# 1 1 R1624 4.7K_0402_1%~D R1625 4.7K_0402_1%~D 3 2 1 KB_LED_R3_DRV# KB_LED_R3_DRV#_A# KB_LED_R3_DRV S R1620 4.7K_0402_1%~D R1621 4.7K_0402_1%~D 1 R1623 4.7K_0402_1%~D D C +3VS R1622 4.7K_0402_1%~D 1 1 Q271B S DMN66D0LDW-7_SOT363-6~D +3VS +3VS Q267B DMN66D0LDW-7_SOT363-6~D +3VS S Q271A DMN66D0LDW-7_SOT363-6~D D G Q267A S DMN66D0LDW-7_SOT363-6~D 1 6 2 3 B D D +3VS 2 G +3VS G G 4 5 5 KB_LED_R4_DRV G G 2 1 2 KB_LED_G1_DRV# D 2 D S 2 1 3 KB_LED_B2_DRV 1 5 KB_LED_G1_DRV#_A# 2 KB_LED_R4_DRV# 6 R1617 4.7K_0402_1%~D KB_LED_B2_DRV# KB_LED_G1_DRV KB_LED_R4_DRV#_A# 1 +3VS KB_LED_B2_DRV#_A# R1616 4.7K_0402_1%~D 2 Q270B DMN66D0LDW-7_SOT363-6~D R1618 4.7K_0402_1%~D R1615 4.7K_0402_1%~D 1 Q270A DMN66D0LDW-7_SOT363-6~D R1614 4.7K_0402_1%~D 6 4 S +3VS R1619 4.7K_0402_1%~D Link Done +3VS 1 +3VS 2 D S S Q263B DMN66D0LDW-7_SOT363-6~D +3VS G 1 3 2 G 4 5 KB_LED_R1_DRV D 1 2 KB_LED_R1_DRV# GND GND +3VS Q263A DMN66D0LDW-7_SOT363-6~D S D TYCO_1-2041070-6~D 2 G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 C1750 0.1U_0402_16V4Z KB_LED_R1_DRV#_A# 6 R1613 4.7K_0402_1%~D 0.5A_13.2V_NANOSMDC050F-13.2-2 1 G 1 1 R1612 4.7K_0402_1%~D 2 C 2 KB_LED_R1_DRV#_A# KB_LED_G1_DRV#_A# KB_LED_B1_DRV#_A# KB_LED_R2_DRV#_A# KB_LED_G2_DRV#_A# KB_LED_B2_DRV#_A# KB_LED_R3_DRV#_A# KB_LED_G3_DRV#_A# KB_LED_B3_DRV#_A# KB_LED_R4_DRV#_A# KB_LED_G4_DRV#_A# KB_LED_B4_DRV#_A# +5VS_KBBL D +3VS +3VS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 G 6 AD0 AD1 AD2 D K/B Backlight CONN D 1 18 23 24 KB_LED_R1_DRV# KB_LED_G1_DRV# KB_LED_B1_DRV# KB_LED_R2_DRV# KB_LED_G2_DRV# KB_LED_B2_DRV# KB_LED_R3_DRV# KB_LED_G3_DRV# KB_LED_B3_DRV# KB_LED_R4_DRV# KB_LED_G4_DRV# KB_LED_B4_DRV# 4 AD3_0 AD3_1 AD3_2 1 2 3 4 5 6 7 8 10 11 12 13 25 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 GND 2 1 SCL SDA KB_LED_R2_DRV 2 19 20 KB_LED_R2_DRV#_A# G 3 I2C_CLK I2C_DAT 5 2 21 KB_LED_R2_DRV# 1 1 R1607 4.7K_0402_1%~D 2 INT#/O16 V+ R1604 4.7K_0402_1%~D 1 +3.3V_F347 U609 22 1 1 +3VS 1 R1609 4.7K_0402_1%~D R1608 4.7K_0402_1%~D 1 AD0 1 7313_INT# 2 2 42 41,42 I2C_CLK 41,42 I2C_DAT 2 AD1 0 C1749 0.1U_0402_16V4Z R1606 4.7K_0402_1%~D R1605 4.7K_0402_1%~D 1 AD2 0 2 +3VS K/B Backlight +3.3V_F347 D 3 Tuesday, November 30, 2010 Sheet 1 Rev 1.0 43 of 63 5 4 3 14,48 EC_SMB_CK1 14,48 EC_SMB_DA1 31 EC_SMB_CK2_R 31 EC_SMB_DA2_R PCH_PWR_EN H_PROCHOT#_EC need add 19 49 17 B H_PROCHOT# 1 R256 2 0_0402_5%~D VR_HOT# 56 1 D SYSTEM_FAN_FB MXM1_FAN_FB E51TXD_P80DATA E51RXD_P80CLK ON/OFF SG_AMD_BKL NUM_LED# 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 2 U36 1 2 3 4 CS# SO WP# GND VCC HOLD# SCLK SI 8 7 6 5 SPI_CLK_R SPI_FWR# PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO GPIO0C SUS_PWR_DN_ACK/GPIO0D INVT_PWM/PWM2/GPIO11 FAN_SPEED1/FANFB0/GPIO14 FANFB1/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A 100 101 102 103 104 105 106 107 108 PM_SLP_S4#/GPXIOD01 ENBKL/GPXIOD02 EAPD/GPXIOD03 EC_THERM#/GPXIOD04 SUSP#/GPXIOD05 PBTN_OUT#/GPXIOD06 EC_PME#/GPXIOD07 110 112 114 115 116 117 118 V18R 124 GPI XCLK1 XCLK0 AGND 122 123 KB930QF-A1_LQFP128_14X14 2 69 1 Close to U34 1 R259 1 R260 SPI_CLK FWR# FSTCHG 50 BATT_CHG_LED# 41 CAPS_LED# 42 BATT_LOW_LED# 41 PCH_PWR_EN 47 SYSON 39,47,54 VR_ON 56 ACIN 14,17,41,50 1 4 OSC @ 1 Rb R240 1 2 43_0402_1% Please place R240 close to EC with in 750mil 20mil H_PECI 5,19 1 2 2 31,34 HDMI_TOGGLE RST# 3 EC_ESB_DAT 4 USB_PWR_EN# 39,40 USB_PWR_EN# HDMI_IN_SELECT# 24,26,35 HDMI_IN_SELECT# Analog Board ID definition,Please see page 3. EC_ESB_CLK GPIO00 @ R251 33_0402_5%~D 1 2 Reserve for EMI please close to U36 TEST_EN# GPIO08/CAS_DAT RST# GPIO09 Reserve for EMI please close to U35 13 14 EC_ENVDD 24,26 15 EN_TPLED# 42 50 ESB_DAT GPIO0A 16 CP_SEL GPIO01 GPIO0B 17 PWRSHARE_OE# 40 6 GPIO02 GPIO0C/PWM0 18 WLES ON/OFF LED# GPIO03 GPIO0D/PWM1 19 EC_AC_BAT# 14 GPIO04 GPIO0E/PWM2 GPIO05 GPIO0F/PWM3 7 49 DYN_TURBO_SEL 8 6 DRAMRST_CNTRL_EC 9 26 EC_INV_PWM 10 GPIO06 17,26 PCH_ENVDD 11 GPIO07/CAS_CLK GND 20 TH_OVERT#_EC DP_MXM_CARD_SEL 23,29 GPIO10/ESB_RUN# 22 LCD_TEST 26 GPIO11/BaseAddOpt 23 3V_F347_ON 41 VCC 24 +3VALW 2 Rev 1.0 LA-6601P Date: Tuesday, November 30, 2010 Sheet 44 of 63 2 1 C294 0.1U_0402_16V4Z~D 60 mil 1 EC ENE-KB930 Document Number 42 21 Title Size B 5 31 HDMI_IN_CAB_DET# Compal Electronics, Inc. 2 @ R257 33_0402_5%~D PM_SLP_S4#_R R480 1 2 0_0402_5%~D PM_SLP_S4# 17 ENBKL ENBKL 26 M_THERMAL# M_THERMAL# 10,11,12,13 ACOFF ACOFF 49,50 SUSP# SUSP# 9,20,47,52,53,54 PBTN_OUT# PBTN_OUT# 5,17 PCIE_WAKE#_EC1 2 PCIE_WAKE# 17,33,38,39 R266 0_0402_5%~D +V18R U35 EC_ESB_CLK 1 ESB_CLK 1 2 1 R225 56K_0402_5% SPI_CLK_R KC3810_QFN24_4X4 3 C AD_BID0 12 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. R219 100K_0402_5%~D Ra 1 100P_0402_50V8J~D PCH_RSMRST# 17 P/N: SA00002C100 4 NC 2 +3VALW EC_ON 46,51 3S/4S# 50 PCH_PWROK 5,17 BKOFF# 26 SCR_LED# 42 PCH_APWROK 17 EC_LID_OUT# 16 MX25L1005AMC-12G_SO8 5 OSC 2 2 PCH_VREG_EN# 21 EC_ON 3S/4S# PCH_PWROK BKOFF# SCR_LED# PCH_APWROK EC_LID_OUT# L44 FBMA-L11-160808-800LMT_0603 0_0402_5%~D 2 0_0402_5%~D 2 Q21 SSM3K7002F_SC59-3~D 1 EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04 EC_ON/GPXIOA05 EC_SWI#/GPXIOA06 ICH_PWROK/GPXIOA07 BKOFF#/GPXIOA08 GPO RF_OFF#/GPXIOA09 GPXIOA10 GPXIOA11 EC_SMB_CK1/SCL0/GPIO44 EC_SMB_DA1/SDA0/GPIO45 EC_SMB_CK2/SCL1/GPIO46 EC_SMB_DA2/SDA1/GPIO47 PCH_VREG_EN# EC_PECI FSTCHG BATT_CHG_LED# CAPS_LED# BATT_LOW_LED# PCH_PWR_EN SYSON VR_ON ACIN 2 C550 PCH_RSMRST# 2 ECAGND C295 0.1U_0402_16V4Z~D R258 0_0402_5%~D 1 2 SPI_FSEL# SPI_SO 2 1 R265 0_0402_5%~D C1846 20P_0402_50V8J~D R152 100K_0402_5%~D +3VALW 1 EC_CRY1 EC_CRY2 1 R253 2 0_0402_5%~D SUSCLK_R 3 Board ID EC_MUTE FRD# FWR# SPI_CLK FSEL# 2 33_0402_5%~D 2 33_0402_5%~D 2 33_0402_5%~D 1 1 1 C293 4.7U_0805_10V4Z~D 17 1Mb SPI ROM A 73 74 89 90 91 92 93 95 121 127 H_PROCHOT#_EC S Q22 3 SSM3K7002F_SC59-3~D FSEL# FRD# GPIO40 H_PECI/GPIO41 FSTCHG/GPIO50 BATT_CHG_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 PWR_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 GPIO R234 R236 R237 1 2 G 119 120 126 128 SPI Flash ROM GND GND GND GND GND 5,49 H_PROCHOT# 45 SYSTEM_FAN_FB 45 MXM1_FAN_FB 38 E51TXD_P80DATA 38 E51RXD_P80CLK 46 ON/OFF 17,26 SG_AMD_BKL 42 NUM_LED# SPIDI/MISO SPIDO/MOSI SPICLK/GPIO58 SPICS# 1 0_0402_5%~D SA_PGOOD 55 LCD_BKL_EN 24 PWRSHARE_EN_EC# 40 TP_CLK 42 TP_DATA 42 SYSTEM_PWROK 5,17 EN_WOL# 33 HDA_SDO 15 LID_SW_IN# 16,41,42 SPI Device I/F 11 24 35 94 113 R255 SYSTEM_PWROK EN_WOL# HDA_SDO LID_SW_IN# S C291 22P_0402_50V8J~D TH_OVERT#_EC 2 0_0402_5%~D 1 TH_OVERT# PS2 EC_MUTE#/PSCLK1/GPIO4A USB_EN#/PSDAT1/GPIO4B CAP_INT#/PSCLK2/GPIO4C Interface PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F SM Bus 2 0_0402_5%~D PM_SLP_S3#_R 2 0_0402_5%~D PM_SLP_S5#_R EC_SMI# EC_SMI# PS_ID PS_ID EC_ESB_CLK_R EC_ESB_DAT SUSWARN# SUSWARN# R249 1 R250 1 17,41 PM_SLP_S3# 17,41 PM_SLP_S5# 77 78 79 80 97 98 99 109 49 50 50 2 G C296 22P_0402_50V8J~D 14 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 R245 1 2 0_0402_5%~D R246 1 2 0_0402_5%~D 45 EC_SMB_CK2 45 EC_SMB_DA2 SDICS#/GPXIOA00 WOL_EN/SDICLK/GPXIOA01 ME_EN/SDIMOSI/GPXIOA02 LID_SW#/GPXIOD00 AC_SEL IREF CHGVADJ EC_MUTE 2 PCH_DPWROK 17 PCH_DPWROK EC_MUTE_R R228 2 SA_PGOOD LCD_BKL_EN PWRSHARE_EN_EC# TP_CLK TP_DATA 56 34,35 1 Reserve for EMI please close to U36 83 84 85 86 87 88 DA Output KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 IMON SPK_MUTE# 1 @ 2 H_PROCHOT#_EC AC_SEL IREF CHGVADJ IMON D 2 1 DAC_BRIG/DA0/GPO3C EN_DFAN1/DA1/GPO3D IREF/DA2/GPO3E DA3/GPO3F 68 70 71 72 CLK_PCI_EC/PCICLK PCIRST#/GPIO05 EC_RST#/ECRST# EC_SCI#/GPIO0E CLKRUN#/GPIO1D SPK_MUTE# BATT_TEMP 48 PM_SLP_SUS# 17 ADP_I 49,50 1 2 EC_SMB_CK1 EC_SMB_DA1 KSO1 KSO2 EC_MUTE EC_SMI# SPK_MUTE# EC_ESB_CLK EC_ESB_DAT LID_SW_IN# EN_WOL# 2.2K_0402_5%~D 2.2K_0402_5%~D 47K_0402_5%~D 47K_0402_5%~D 10K_0402_5%~D 1K_0402_1%~D 10K_0402_5%~D 4.7K_0402_5%~D 4.7K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D @ @ @ @ 2 2 2 2 2 2 2 2 2 2 1 C284 22P_0402_50V8J~D R229 1 R230 1 R231 1 R232 1 R238 1 R239 1 R241 1 R242 1 R243 1 R1679 1 R1698 2 C BATT_TEMP PM_SLP_SUS# ADP_I AD_BID0 X1 32.768KHZ_12.5PF_Q13MC14610002 2 R226 @ 33_0402_5%~D 63 64 65 66 75 76 D ECAGND 1 100P_0402_50V8J~D 2 C286 1 +3VALW BATT_TEMP/AD0/GPI38 BATT_OVP/AD1/GPI39 ADP_I/AD2/GPI3A AD3/GPI3B AD Input AD4/GPI42 AD5/GPI43 LPC & MISC CPU1.5V_S3_GATE 9 BEEP# 34 SYSTEM_FAN_PWM 45 MXM1_FAN_PWM 45 @ 1 2 EC_ESB_CLK_R 0_0402_5%~D 21 23 26 27 GND CLK_PCI_LPC EC_ESB_CLK 1 R252 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 PWM CPU1.5V_S3_GATE BEEP# SYSTEM_FAN_PWM MXM1_FAN_PWM PWM0/GPIO0F BEEP#/PWM1/GPIO10 Output FANPWM0/GPIO12 ACOFF/FANPWM1/GPIO13 2 C283 0.1U_0402_16V4Z~D KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 12 13 37 20 38 GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ# LPC_FRAME#/LFRAME# LPC_AD3/LAD3 LPC_AD2/LAD2 LPC_AD1/LAD1 LPC_AD0/LAD0 25 EC_SCI# EN_CAM 1 2 3 4 5 7 8 10 R519 10K_0402_5%~D 1 19 26 2 1 2 2 1 2 CLK_PCI_LPC PLT_RST# EC_RST# EC_SCI# EN_CAM 18 CLK_PCI_LPC 5,18,33,35,38,39 PLT_RST# C292 .1U_0402_16V7K~D 2 RST# C285 0.1U_0402_16V4Z~D 1 15 15 15 15 GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 19 GATEA20 19 KB_RST# 15 SERIRQ 15 LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 EC_CRY2 1 2 @ R248 47K_0402_5%~D R221 47K_0402_5%~D EC_RST# EC_CRY1 1 NC +3VALW 1 +3VALW 1 R224 AVCC VCC VCC VCC VCC VCC VCC U34 2 2 3 1 TP_DATA 4.7K_0402_5%~D @ 1 ECAGND 2 1 R223 67 2 9 22 33 96 111 125 2 1 2 C288 15P_0402_50V8J~D BKOFF# EC_SCI# M_THERMAL# EC_SMB_CK2 EC_SMB_DA2 2 4.7K_0402_5%~D C287 15P_0402_50V8J~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 2.2K_0402_5%~D 2.2K_0402_5%~D 2 2 2 2 2 2 TP_CLK C282 0.1U_0402_16V4Z~D D 1 1 1 1 1 1 C281 1000P_0402_50V7K~D R217 R218 R220 R244 R247 1 C280 1000P_0402_50V7K~D 2 +3VS 1 C279 0.1U_0402_16V4Z~D 1 C278 0.1U_0402_16V4Z~D KSO[0..15] L43 FBMA-L11-160808-800LMT_0603 1 2 +EC_VCCA +3VALW_EC 0_0805_5% 2 C276 0.1U_0402_16V4Z~D KSI[0..7] R216 1 C277 0.1U_0402_16V4Z~D 42,46 42,46 KSO[0..15] 1 +5VS +3VALW KSI[0..7] 2 A A B C D +3VS 1 R1796 2 0_0402_5%~D 1 REMOTE_P1 1 1 2 B E Q276 MMBT3904W T1G_SC70-3~D 2 SENSOR_DIODE_N1 R1797 C1815 470P_0402_50V7K~D 2 0_0402_5%~D 1 +3VS Diode circuit s used for skin temp sensor (placed between CPU and MXM). Place C1814 close to Q276 as possible. R1798 U617 1 REMOTE_N1 2 4.7K_0402_5%~D 1 SMCLK 8 DP SMDATA 7 DN ALERT 6 GND 5 VDD 2 3 4 THERM#/ADDR 1 EC_SMB_CK2 EC_SMB_CK2 44 EC_SMB_DA2 EC_SMB_DA2 44 EMC1412-A-ACZL-TR_MSOP8 1 48,49,51 MAINPW ON 3 S 2 C D 1 3 @ C1814 100P_0402_50V8J~D 2 SENSOR_DIODE_P1 C1816 0.1U_0402_10V7K~D System FAN Controller 1 E +5VS 2 G +3VS 1 +3VS 2 1 2 1 1 2 R1802 10K_0402_5%~D R1801 10K_0402_5%~D R1800 10K_0402_5%~D 2 C243 22U_0805_6.3VAM~D Q282 SSM3K7002FU_SC70-3~D JFAN1 CONN@ 2 SYSTEM_FAN_PW M SYSTEM_FAN_FB 44 SYSTEM_FAN_PW M 44 SYSTEM_FAN_FB 1 2 3 4 2 1 D65 SDMK0340L-7-F_SOD323-2~D 1 2 3 4 2 G5 G6 5 6 MOLEX_53398-0471~D Link Done +3VS 1 2 SENSOR_DIODE_P2 1 2 0_0402_5%~D REMOTE_P2 1 1 1 2 C 3 @ 100P_0402_50V8J~D C1818 3 R1806 2 B E Q279 MMBT3904W T1G_SC70-3~D 2 SENSOR_DIODE_N2 R1807 1 R1808 U618 C1817 470P_0402_50V7K~D 2 0_0402_5%~D +3VS C1819 0.1U_0402_10V7K~D MXM1 FAN Controller REMOTE_N2 1 2 6.8K_0402_5%~D 1 VDD 2 DP 3 DN 4 THERM#/ADDR SMCLK 8 SMDATA 7 ALERT 6 GND 5 EC_SMB_CK2 EC_SMB_DA2 3 EMC1412-A-ACZL-TR_MSOP8 3 S 1 D MAINPW ON 2 G Q283 SSM3K7002FU_SC70-3~D +5VS +3VS +3VS 2 1 2 1 2 1 R1811 10K_0402_5%~D MXM1_FAN_PW M MXM1_FAN_FB R1810 10K_0402_5%~D R1813 10K_0402_5%~D 44 MXM1_FAN_PW M 44 MXM1_FAN_FB 2 C249 22U_0805_6.3VAM~D 1 2 1 D66 SDMK0340L-7-F_SOD323-2~D JFAN2 CONN@ 1 2 3 4 1 2 3 4 G5 G6 5 6 MOLEX_53398-0471~D 4 4 Link Done DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A B C D Title Thermal Sensor & FAN Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet E 45 of 63 C D FD2 @ 1 1 FD1 FIDUCIAL_C40M80 E FD3 @ FIDUCIAL_C40M80 FD4 @ 1 B 1 A FIDUCIAL_C40M80 @ FIDUCIAL_C40M80 Fiducial Mark 1 1 KSO7 @ C303 1 2 100P_0402_50V8J~D KSO14 @ C304 1 2 100P_0402_50V8J~D KSO6 @ C305 1 2 100P_0402_50V8J~D KSO13 @ C306 1 2 100P_0402_50V8J~D KSO5 @ C307 1 2 100P_0402_50V8J~D KSO12 @ C308 1 2 100P_0402_50V8J~D KSO4 @ C309 1 2 100P_0402_50V8J~D KSI0 @ C310 1 2 100P_0402_50V8J~D KSO3 @ C311 1 2 100P_0402_50V8J~D KSO11 @ C312 1 2 100P_0402_50V8J~D KSI4 @ C313 1 2 100P_0402_50V8J~D KSO10 @ C314 1 2 100P_0402_50V8J~D KSO2 @ C315 1 2 100P_0402_50V8J~D KSI1 2 100P_0402_50V8J~D KSO1 @ C317 1 2 100P_0402_50V8J~D +3VALW 2 2 100P_0402_50V8J~D 2 100P_0402_50V8J~D Power Button R262 100K_0402_5%~D 1 KB_DET# @ C434 1 KSO15 @ C302 1 D26 @ C318 1 2 100P_0402_50V8J~D KSO0 @ C319 1 2 100P_0402_50V8J~D KSO9 @ C320 1 2 100P_0402_50V8J~D KSI5 @ C321 1 2 100P_0402_50V8J~D KSI3 @ C322 1 2 100P_0402_50V8J~D KSI6 @ C323 1 2 100P_0402_50V8J~D KSO8 @ C324 1 2 100P_0402_50V8J~D KSI7 @ C325 1 2 100P_0402_50V8J~D 2 2 3 2 EC_ON EC_ON 1 Q23 SSM3K7002F_SC59-3~D 2 2 3 1 S 1 1 1 1 1 1 49 2 G R263 100K_0402_5%~D 1 44 51ON# @ DAN202UT106_SC70-3 D27 PSOT24C_SOT23 @ H1 @ H2 @ H3 @ H5 @ H6 @ @H1 @H7 H7 @ H8 @ H9 @ H18 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P5N H_4P0X2P5N H_3P3 1 ON/OFF 3 D 44,51 1 2 1 1 KSI2 1 C326 0.1U_0402_25V6K~D @ C316 1 ON/OFFBTN# 42 ON/OFFBTN# 1 1 1 1 1 1 1 1 1 1 @ H11 @ H12 @ H13 @ H14 @ H15 @ @H11 @H16 H16 @ H17 @ H10 @ H19 @ H20 H_3P2 H_2P8 H_2P8 H_2P8 H_3P2 H_3P2 H_3P2 H_3P3 H_2P8 H_2P8 INT_KBD Conn. @ H21 @ H22 @ H23 @ H24 @ H25 @ @H21 @H26 H26 @ H27 @ H28 H_2P8 H_3P8 H_3P3 H_3P8 H_3P3 H_2P8 H_2P8 H_2P8 1 1 1 1 1 1 1 1 KSI[0..7] KSO[0..15] KSI[0..7] 42,44 KSO[0..15] 42,44 IR SENSOR connector JKB1 16 ZZZ1 PCB-MB KB_DET# KSO7 KSO0 KSI1 KSI7 KSO9 KSI6 KSI5 KSO3 KSI4 KSI2 KSO1 KSI3 KSI0 KSO13 KSO5 KSO2 KSO4 KSO8 KSO6 KSO11 KSO10 KSO12 KSO14 KSO15 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 KB_DET# KSO7 KSO0 KSI1 KSI7 KSO9 KSI6 KSI5 KSO3 KSI4 KSI2 KSO1 KSI3 KSI0 KSO13 KSO5 KSO2 KSO4 KSO8 KSO6 KSO11 KSO10 KSO12 KSO14 KSO15 +5VS C446 0.1U_0402_16V4Z~D 3 KB_DET# 18 18 USB20_N7 USB20_P7 USB20_N7 USB20_P7 3 1 2 JIR1 CONN@ 1 2 3 4 5 6 7 8 1 2 3 4 5 6 GND GND AMPHE_G846A06211EU Link Done AMPHE_G28301021AHR CONN@ Link Done 4 4 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title KB & Power Button & IR Size B C D Rev 1.0 LA-6601P Date: A Document Number Tuesday, November 30, 2010 Sheet E 46 of 63 A B C D E DC to DC +3VALW to +3V_PCH +3VALW 6 @ 1 1 2 4 1 4 2 @ 4 6 1 2 4 D 1 G Q8A DMN66D0LDW-7_SOT363-6~D 1 2 2 +5VMXM_GATE 1 1 2 1 3 2 2 2 S 2 1 1 4 1 @ 2 S DGPU_PWR_EN# 100mil(2.5A) 1 R278 0_0402_5%~D 1 Q31 SSM3K7002FU_SC70-3~D 2 G R275 200K_0402_5% 1 2 B+_BIAS D 2 C353 0.1U_0603_25V7K~D 1 R284 2 10K_0402_5%~D 2 1 C344 0.1U_0402_16V4Z~D 2 1 +5VMXM U40 SI4800BDY-T1-E3_SO8~D 8 1 7 2 6 3 5 C343 10U_0805_10V4Z~D 1 C342 10U_0805_10V4Z~D 2 C357 .1U_0402_16V7K~D 1 2 3 C356 10U_0805_10V4Z~D SUSP 8 7 6 5 1 R285 100K_0402_5%~D 3 +1.5VS C358 0.1U_0603_25V7K~D S 2 C448 10U_0805_10V4Z~D 2 G 1 2 R281 0_0402_5%~D D C354 0.1U_0603_25V7K~D 1 Q29 SSM3K7002F_SC59-3~D R279 102K_0402_1% 1 R283 100K_0402_5%~D 2 +3VS_GATE 2 SUSP 1 B+_BIAS C348 1U_0603_10V4Z~D 1 B+_BIAS 2 +5VALW to +5VMXM U20 AO4728L_SO8~D 1 2 3 C347 10U_0805_10V4Z~D 2 2 +5VALW +1.5V 8 7 6 5 C346 10U_0805_10V4Z~D C345 10U_0805_10V4Z~D 2 1 S +3VS Q27 SI4800BDY-T1-E3_SO8~D 1 1 Q7A DMN66D0LDW-7_SOT363-6~D +1.5V To +1.5VS +3VALW D G 2 1 @ 4 3 4 +3VALW to +3VS 3 2 2 +3VMXM_GATE 1 R272 0_0402_5%~D 2 G S 1 R282 0_0402_5%~D D PCH_PWR_EN# 1 C355 0.1U_0603_25V7K~D S 2 2 +3V_PCH_GATE Q30 SSM3K7002F_SC59-3~D D G R273 0_0402_5%~D 5 C340 0.1U_0603_25V7K~D SUSP 1 DGPU_PWR_EN# R280 1 2 102K_0402_1% B+_BIAS Q25B DMN66D0LDW-7_SOT363-6~D 2 R270 102K_0402_1% 2 C341 0.1U_0603_25V7K~D +5VS_GATE 1 B+_BIAS 40mil(1A) 1 @ R269 200K_0402_5% 1 2 B+_BIAS 1 1 2 3 C339 0.1U_0402_16V4Z~D 2 8 7 6 5 C447 10U_0805_10V4Z~D 2 1 C333 10U_0805_10V4Z~D 2 1 C352 1U_0603_10V4Z~D 2 1 +3VMXM U18 SI4800BDY-T1-E3_SO8~D 1 2 3 C351 10U_0805_10V4Z~D 2 1 +3VALW 8 7 6 5 C350 10U_0805_10V4Z~D 2 1 C349 10U_0805_10V4Z~D 2 1 C338 1U_0603_10V4Z~D 1 +3VALW to +3VMXM Transfer +3V_PCH Q40 SI4800BDY-T1-E3_SO8~D C337 10U_0805_10V4Z~D 2 Q24 SI4800BDY-T1-E3_SO8~D 8 1 7 2 6 3 5 C336 10U_0805_10V4Z~D C335 10U_0805_10V4Z~D 1 1 +5VS 2 +5VALW 2 +5VALW to +5VS Discharge Circuit +1.5V +5VALW +1.5VS +VCCP +5VALW +3VALW +5VMXM +3VMXM 1 1 2 @ @ 1 2 1 @ 2 1 2 3 D 1 2 G 18 DGPU_PWR_EN 1 1 2 S @ S 1 2 @ 1 2 1 3 R294 100K_0402_5%~D DGPU_PWR_EN# 1 2 G 39,44,54 SYSON 2 2 2 S +5VALW 2 1 1 3 1 3 4 3 2 2 2 1 1 1 2 6 1 S 1 3 3 Q36 SSM3K7002F_SC59-3~D D 2 G 2 G SUSP# C362 0.1U_0603_25V7K~D S 9,20,44,52,53,54 R301 100K_0402_5%~D D D Q35 SSM3K7002F_SC59-3~D 2 G Q37 5,9 RUN_ON_CPU1.5VS3# SYSON# C361 0.1U_0603_25V7K~D S 3 R295 100K_0402_5%~D R300 100K_0402_5%~D G 2 S +5VALW Q38 SSM3K7002FU_SC70-3~D 5 1 +0.75VS +DDR_CHG SUSP D Q5B DMN66D0LDW-7_SOT363-6~D S +3VS_D 2 G Q5A DMN66D0LDW-7_SOT363-6~D +3V_D PCH_PWR_EN# 4 D Q8B S 2 G 44 PCH_PWR_EN R293 22_0603_5%~D R299 470_0603_5% R298 470_0603_5% SSM3K7002FU_SC70-3~D R292 220_0603_5%~D +1.5V_CPU_VDDQ_CHG +3VS +3V_PCH D G 2 4 3 4 +1.5V_CPU_VDDQ S 5 1 3+3VMXM_D1 2 2 1 DMN66D0LDW-7_SOT363-6~D 6 1 6 1 2 1 3 SSM3K7002FU_SC70-3~D Q7B SUSP 1 Q33 SSM3K7002F_SC59-3~D D G D C360 0.1U_0603_25V7K~D S 5 1 R291 100K_0402_5%~D G SUSP D Q32 SSM3K7002F_SC59-3~D D 21 PCH_PWR_EN# C359 0.1U_0603_25V7K~D 5 R288 100K_0402_5%~D SUSP R302 100K_0402_5%~D S SUSP R287 100K_0402_5%~D R286 10K_0402_5%~D DMN66D0LDW-7_SOT363-6~D S D G DMN66D0LDW-7_SOT363-6~D Q25A SUSP 2 Q4B DMN66D0LDW-7_SOT363-6~D D G +VCCP_D S SUSP 2 Q4A DMN66D0LDW-7_SOT363-6~D +1.5VS_D D +5VS_D SYSON# 2 G Q34 R268 470_0603_5% R297 470_0603_5% 3+5VMXM_D1 R296 470_0603_5% R267 470_0603_5% +1.5V_D 3 R274 470_0603_5% 1 R289 470_0603_5% 4 2 2 1 2 1 +5VS 4 Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A B C D Title DC/DC Interface Size Document Number Date: Tuesday, November 30, 2010 Rev 1.0 LA-6601P Sheet E 47 of 63 3 2 6 8 2 1 1 2 PU1B LM393DG_SO8 1 VL PR237 100K_0402_1% C PR233 100K_0402_1% 2 2 PC200 1000P_0402_50V7K 1 +3VALW 2 PR7 10K_0402_1%~D 1 2 PR11 100_0402_5%~D 1 2 PC201 0.22U_0603_25V7K 2 1 BATT_TEMP 44 PR12 100_0402_5%~D 1 2 CLK_SMB DAT_SMB BATT_PRS SYS_PRS PR234 16.9K_0402_1% EC_SMB_DA1 14,44 7 O 1 - P + 6 4 PR10 100_0402_5%~D 1 2 5 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TM_REF1 G EC_SMB_CK1 14,44 PQ67A DMN66D0LDW-7 2N SOT363-6 MAINPWON 45 PR6 0_0402_5%~D 2 GND GND 13 12 11 10 9 8 7 6 5 4 3 2 1 @ JMBTY 2 VL PR238 13.7K_0402_1% 1 2 SUYIN_200275GR013G10PZR D 1 1 PR235 47K_0402_1% 1 2 PH6 3 2 3 2 100K_0402_1%_TSM0B104F4251RZ 2 PC1 1000P_0402_50V7K~D 1 2 1 PC3 0.01U_0402_25V7K~D 2 1 PC2 100P_0402_50V8J~D 2 C VL PR236 47K_0402_1% JIMBTY battery connector SMART Battery: 13.BAT+ 12.BAT+ 11.BAT+ 10.BAT+ 09.CLK_SMB 08.DAT_SMB 07.BATT_PRS 06.SYS_PRES 05.BAT_ALERT 04.GND 03.GND 02.GND 01.GND 1 VL BATT++ 1 BATT+ PL2 C8B BPH 853025_2P 1 2 BATT++ PD2 @ PESD24VS2UT_SOT23-3 PC4 100P_0402_50V8J~D BATT+ D PD1 @ PESD24VS2UT_SOT23-3 PL1 C8B BPH 853025_2P 1 2 2 1 4 1 5 PQ1 TP0610K-T1-E3_SOT23-3 2 2 @ JRTC1 B+_BIAS B @ PC9 0.1U_0603_25V7K~D 2 - + 1 +RTCBATT SUYIN_060003FA002G202NL CONN@ PR15 100K_0402_1%~D @ PD18 1 2 +3VLP D S PQ2 SSM3K7002FU_SC70-3 2 G PC10 0.1U_0402_16V7K~D 2 1 PR16 0_0402_5%~D 2 1 1 3 RB751V-40_SOD323-2 1 SPOK +RTCBATT 2 1 PC8 0.22U_0603_25V7K~D +5VALW 2 1 PR13 100K_0402_1%~D 2 PR14 22K_0402_1%~D 1 2 1 1 3 B+ B @ A A Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title BATTERY CONN/OTP Size Document Number Rev 0.3 LA-6601P Date: Tuesday, November 30, 2010 Sheet 48 of 63 B C D PR18 2.2K_0402_5%~D 1 2 2 PD6 DA204U_SOT323~D 10K_0402_1%~D 1 1 2 2 1 1 2 2 1 2 PC16 0.1U_0603_25V7K~D 2 5 1U_0603_25V6K #SHDN PR41 @ 200_0805_5% 1 2 PC83 2 1 1 GND 5/3+ IN @ 2 1 4 1 @ @ + D 2 G 1 @ PR122 2 1 PACIN 47K_0402_5%~D PC85 0.01U_0402_25V7K~D 1 2 PRG++ 2 @ PR121 499K_0402_1%~D @ 2 1 @ PR119 34K_0402_1%~D 2 1 PQ10 RHU002N06_SOT323-3 @ 1 2 1 LM393DR_SO8 @ PU13A @ PACIN 34,50 S PQ9 DTC115EUA_SC70-3 3 - PC206 1000P_0402_50V7K~D 2 1 RB715F_SOT323-3 + O 3 1 PR156 191K_0402_1%~D 2 8 1 3 P ACON G 44 @ PR155 499K_0402_1%~D 4 AC_SEL PC84 0.1U_0603_25V7K~D 45 MAINPWON 2 PR40 0_0402_5%~D VS @ @ PD10 2 2 +5VALW @ 4 3 44,50 PR135 100K_0402_1%~D 1 ADP_I 1 1 PR37 0_0402_5%~D 1 B+ 2 1 @ PR42 2.2M_0402_5%~D B+ Compal Electronics, Inc. VIN+ PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Add MXM power net for HW request. A OUT +CHGRTC 2 14 VIN- 2 2 G PL6 SMB3025500YA_2P 1 2 1 14 @ VL 1 2 3 VS TP0610K-T1-E3_SOT23-3 3 2 1 2 PC19 1000P_0402_50V7K~D 8 P 4 2 1 @ PU2 MAX1615EUK+_SOT23-5~D PR271 0_0603_5%~D 1 2 @ 1 1 1 51ON# 2 3 PC15 0.22U_0603_25V7K~D 46 PR34 22K_0402_5%~D 1 2 2 2 2 PC209 PC203 4 + - 5 100U_25V_M~D 1 3 O PU1A LM393DG_SO8 PR239 0.004_2512_1% B+_MXM + 4 1 PC18 1000P_0402_50V7K~D 0_0402_5%~D 2 PR33 100K_0402_5%~D 100U_25V_M~D 1 PR32 68_1206_5%~D 3 1 2 PR39 2 5,44 H_PROCHOT# PQ67B DMN66D0LDW-7 2N SOT363-6 4 3 0_0402_5%~D PR31 68_1206_5%~D Pre_V @ 44 Dyn_Turbo_Sel PR21 1 @ PR35 0_0402_5%~D 2 1 PR38 10K_0402_1%~D 1 PQ4 MMST3904-7-F_SOT323~D 3 2 PQ8 +3VLP VL 2 PSID_DISABLE# PD8 BAS32L_SOD80C +CHGRTC +3VALW PR36 2 2 3 @ @ PR24 1 VIN 1 PR30 1 3 BAS40CW _SOT323 @ 10K_0402_1%~D Pre_V 3 2 BATT ONLY Precharge detector Min. typ. Max. H-->L 4.92V 6.1V 5.25V L-->H 6.062V 6.244V 6.43V @ PQ7 DDTC115EUA-7-F_SOT323 @ 1 3 +5VALW BATT+ Precharge detector Min. typ. Max. H-->L 14.589V 14.84V 15.243V L-->H 15.562V 15.97V 16.388V 1 2 PQ6 DDTC115EUA-7-F_SOT323 1 @ PD19 2 15K_0402_1%~D ACIN @ 44,50 ACOFF E PD9 BAS32L_SOD80C 2 @ S D 2 B B+ 1 100K_0402_5%~D @ PR29 1 PR28 1 @ PR27 1K_1206_5%~D 1 2 PreCHG 2 2 +5VALW C 1 3 1 1 44 +5VALW 2 G FDV301N_NL_SOT23-3~D 2 2 @ PR26 1K_1206_5%~D 1 2 PS_ID PQ3 2 PR22 1 @ PQ5 TP0610K-T1-E3_SOT23-3 2 VIN @ PD7 BAS32L_SOD80C 100K_0402_5%~D @ PR25 1K_1206_5%~D 1 2 100K_0402_5%~D @ PR23 1K_1206_5%~D 1 2 PR19 33_0402_5%~D 1 2 3 1 2 1 1 PR20 @ PD5 SM24_SOT23 100K_0402_1%~D 3 2 1 2 DOCK_PSID 1 FOX_JPD23L-D4672-7H PC14 1000P_0402_50V7K~D 5 1 4 V- GND 2 V- GND 9 1 3 2 V+ 8 PC12 100P_0402_50V8J~D 2 1 1 V+ GND 2 ID 7 PC11 1000P_0402_50V7K~D 1 @ PR17 1 2 0_0402_5%~D PC13 100P_0402_50V8J~D PL3 C8B BPH 853025_2P 1 2 DC_IN_S1 @ JDCIN 6 GND +3VALW 2 VIN 3 ADPIN PC17 4.7U_0603_6.3V6K PL4 FBM-L11-160808-601LMT 0603~D 2 1 DOCK_PSID PD4 DA204U_SOT323~D +5VALW 3 A B C Title DCIN & DETECTOR Size Document Number Date: Tuesday, November 30, 2010 Rev 0.3 LA-6601P D Sheet 49 of 63 A B @ PD11 B540C-13-F_SMC2~D 2 PQ11 AOD403_TO252-3 P2 1 C D B+ Iada=0~12.3A(240W) @ 1 PD17 B540C-13-F_SMC2~D 2 D S ADP_I = 19.9*Iadapter*Rsense 16 10 ACLIM VDDP 15 PGND 13 5 6 7 8 PR68 4.7_0603_5%~D PC44 4.7U_0805_6.3V6K~D 2 AO4712L_SO8~D PQ24 1 2 4 26251VDD 1 2 5 6 7 8 1 3 2 1 1 PL8 10UH_PCMB104T-100MS_6A_20% PR62 0.02_2512_1% 1 2 1CHG 4 3 2 1 LGATE GND DL_CHG 2 VADJ 12 PD16 RB751V-40_SOD323-2 1 2 2 BATT+ 3 PC46 10U_0805_25V5K~D 2 1 BOOT @ PC82 10U_0805_25V5K~D 2 1 CHLIM PACIN PC41 10U_0805_25V5K~D 2 1 9 PR66 PC37 2.2_0603_5%~D 0.1U_0603_25V7K~D BST_CHG 1 2 BST_CHGA 2 1 2 G S 3 DH_CHG VIN @ PQ22 SSM3K7002FU_SC70-3 PC40 10U_0805_25V5K~D 2 1 17 ACPRN PC32 0.1U_0603_25V7K~D 2 1 UGATE S 2 G @ D PC39 10U_0805_25V5K~D 2 1 VREF D PQ60 SSM3K7002FU_SC70-3 8 1 18 @ PD15 1SS355_SOD323 1 2 3 PHASE PR231 V1 2 1 100K_0402_1%~D PC31 2200P_0402_25V7K~D 2 1 ICM 14 2 2 7 11 PC21 2200P_0402_25V7K~D 2 1 1 1 19 3 CSIP 4 2 PR65 4.7_1206_5%~D VCOMP 6251VDDP @ PR51 200K_0402_1%~D 1 2 PC43 680P_0402_50V7K~D 6 PQ21 CSIN CSOP PQ18 AO4466L_SO8~D DDTC115EUA-7-F_SOT323 2 1 2 PR49 15.4K_0402_1%~D PC27 1000P_0402_25V8J~D 2 1 ICOMP 20 2 1 PR48 10_1206_5%~D 2 1 1 21 CELLS 1 CSOP 5 ISL6251AHAZ-T_QSOP24 1 2 3 D PR71 57.6K_0402_1%~D 1 2 6251VDD 1 PR72 100K_0402_1%~D PR73 47K_0402_1%~D ACPRN PR74 10K_0402_1%~D CHGVADJ PR75 10K_0402_1%~D 1 2 ACIN 14,17,41,44 PACIN 1 2 S 1 3 CSON VIN @ PD13 1SS355_SOD323 ACOFF 1 2 PR50 10K_0402_1%~D ACPRN 1 PC42 0.01U_0402_25V7K~D 2 1 ACSETIN PR56 20_0603_5% 1 2 2 CSON PC20 0.1U_0603_25V7K~D 2 1 1 2 PC26 2.2U_0603_6.3V6K~D 2 1 EN 22 2 240W 23 PR47 47K_0402_1%~D 1 2 DCIN 2 1 PC29 0.1U_0603_25V7K~D 1 0 ACSET ACPRN 1 PR70 1.3K_0402_1%~D 2 G PQ63 SSM3K7002FU_SC70-3 150W CP_SEL 6251VREF 6251aclim 2 PR132 0_0402_5%~D 1 2 1 1 1 2 PR54 PC38 1 2 1 PR69 11.5K_0402_1%~D 3 44 PR61 100_0402_1%~D 1 2 24 0.1U_0402_16V7K~D PR67 100K_0402_1%~D 6251VREF PR59 10K_0402_1%~D 2 DCIN 1 3 PR45 191K_0402_1%~D PC30 0.047U_0603_16V7K~D 1 2 PR57 20_0603_5% 2 1 PR58 20_0603_5% PC34 0.1U_0603_25V7K~D 1 2 PR60 2.2_0603_5%~D LX_CHG 4 PC33 6800P_0402_25V7K~D 1 2 0.01U_0402_25V7K~D 44,49 ADP_I PR64 40.2K_0402_1%~D 2 1 IREF CP_SEL 1 3 VDD 1 2 @ PR232 0_0402_5%~D 1 PC35 1 2 4S 2 6251_EN 2 3S 1 100K_0402_1%~D DDTC115EUA-7-F_SOT323 Low 2 1 3 ACOFF 2 1 3 High PD12 RB751V-40_SOD323-2 PU3 1 2 PC28 0.1U_0402_16V7K~D 2 PQ19 DMN66D0LDW-7 2N SOT363-6 PQ66B 3 4 3S/4S# signal PQ25 DDTC115EUA-7-F_SOT323 PR63 47K_0402_5%~D PACIN 1 2 PD14 1SS355_SOD323 1 2 2 3S/4S# 5 ACSETIN PR52 10K_0402_5%~D 2 1 PR53 47K_0402_5%~D 2 PQ17 DDTC115EUA-7-F_SOT323 PC25 5600P_0402_25V7K~D 1 2 2 1 2 1 1 1 2 2 PR230 0_0402_5%~D 6251VDD FSTCHG 6251VDD 1 PreCHG 1 PC24 10U_0805_25V5K~D 2 1 VIN PR46 200K_0402_1%~D 1 2 3 PC22 0.1U_0603_25V7K~D S 2 2 3 6 ACOFF CSIP D G 200K_0402_1%~D PQ16 PDTA144EU PNP_SOT323 ACON 49 CSIN 1 PQ15 AOD403_TO252-3 PC23 10U_0805_25V5K~D 2 1 2 S D G 2 3 3 PQ66A DMN66D0LDW-7 2N SOT363-6 1 PACIN 3 G 34,49 2 CHG_B+ JUMP_43X118 @ PL7 FBMA-L18-453215-900LMA90T_1812 1 2 G 1 V1 2 4 S PQ32 AOD403_TO252-3 PR55 150K_0402_1%~D 2 1 D D PC36 2.2U_0805_25V6K PR113 PR114 1 2 2 1 2 1 3.3_1210_5%~D 3.3_1210_5%~D PR44 2 1 PQ14 AOD403_TO252-3 S 1 P3 3 1 1 G 1 PR43 0.005_2512_1% 3 2 @ PJP10 2 2 1 G VIN PQ12 AOD403_TO252-3 S PQ13 AOD403_TO252-3 1 D 3 PQ26 DDTC115EUA-7-F_SOT323 2 1 CP mode Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05) PR76 14.3K_0402_1%~D 2 3 Vaclim=2.87*((11.5K//152K)/((2.87K//152K)+(11.5K//152K))) 4 CC=0.22~5.04A CHGVADJ IREF=1*Icharge CV mode 0V 4V per cell 1.882V 4.2V per cell 4 IREF=0.22V~3.294V - A 3.3V Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 4.35V per cell B C Title CHARGER Size Document Number Date: Tuesday, November 30, 2010 Rev 0.3 LA-6601P D Sheet 50 of 63 5 4 3 2 1 2VREF_RT8209E D +3VALWP 2 1 PC45 1U_0603_10V6K~D Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO D PR77 13K_0402_1%~D 1 2 PR78 30K_0402_1%~D 1 2 PR79 20K_0402_1%~D 1 2 PR80 20K_0402_1%~D 1 2 +5VALWP 6 1 1 PR92 100K_0402_1%~D 1 1 2 PR264 0_0402_5%~D EC_ON PQ33 DDTC115EUA-7-F_SOT323 3 1 2 PC67 2.2U_0603_16V5K~D 1 2 PR89 @ 0_0402_5% RT8205E_B+ PC80 4.7U_0805_25V6-K~D 2 1 PC53 0.1U_0603_25V7K~D 2 1 PC55 2200P_0402_50V7K~D 2 1 PC52 4.7U_0805_25V6-K~D 2 1 + VL 1 1 1 Typ: 175mA 2 PC63 330U_D_6.3VM_R18M~D 4 +5VALWP PC61 680P_0402_50V7K~D RT8205EGQW _W QFN24_4X4 18 17 16 15 EN 14 13 1 LG_5V PR86 4.7_1206_5%~D 1 2 19 FDMS0310S_POWER56-8~D LGATE1 C PL11 2.2UH_FDVE1040-2R2M=P3_14.2A_20%~D 1 2 5 LGATE2 NC 12 VREG5 LG_3V VIN LX_5V GND 20 SKIPSEL PHASE1 PR84 0_0603_5%~D SIR472DP-T1-GE3_POWERPAK8-5~D 5 PQ28 UG_5V 3 2 1 21 PQ30 2 1 ENTRIP1 UGATE1 VFB=2.0V B 5VALWP TDC 8.9A Peak Current 12.8A OCP current 15.3A PJP5 2 @ 2 PJP3 1 1 2 JUMP_43X118 PJP6 +3VALW P 2 @ 2 1 2 1 1 @ JUMP_43X118 PJP4 2 2 1 1 +5VALW P 1 +3VALW @ +5VALW A JUMP_43X118 JUMP_43X118 2 Compal Electronics, Inc. 3 46 S 2 G PQ61 SSM3K7002FU_SC70-3 1 A D 3 ACPRN PR112 200K_0402_1%~D 1 2 3 UGATE2 PC57 0.1U_0603_25V7K~D 2 2 1 3.3VALWP TDC 7.2A Peak Current 10A OCP current 12A 2 2 1 PR94 40.2K_0402_1%~D 2 100K_0402_1%~D FB1 BST_5V 1 2VREF_RT8209E PR93 1 VS REF 22 3 2 1 PR91 @ 499K_0402_1%~D 1 2 PQ31A DMN66D0LDW-7 2N SOT363-6 PQ31B DMN66D0LDW-7 2N SOT363-6 4 3 2 VL 45 MAINPWON 2 4 23 BOOT1 B 5 TONSEL 6 5 FB2 PGOOD BOOT2 PC65 22U_0805_6.3VAM~D Pre_V VREG3 2 ENTRIP2 ENTRIP2 1 PR90 499K_0402_1%~D 1 2 VS ENTRIP1 2 PC54 4.7U_0805_10V6K~D @ 4 24 PHASE2 PR87 499K_0402_1%~D 1 2 B+ SPOK VO1 VO2 11 1 2 @ PR272 0_0402_5%~D 45 MAINPWON PR82 60.4K_0402_1%~D 2 LX_3V PQ29 4 P PAD 1 2 PC56 8 0.1U_0603_25V7K~D 2 1 1 2 BST_3V 9 PR83 0_0603_5%~DUG_3V 10 1 2 PC66 0.1U_0603_25V7K~D 2 + 25 PC64 1U_0603_25V6K~D 2 1 1 PC60 680P_0402_50V7K~D PR85 4.7_1206_5%~D 1 2 1 PC58 330U_D_6.3VM_R18M~D +3VALWP PU4 7 FDMS0310S_POWER56-8~D 1 2 3 5 PL10 2.2UH_FDVE1040-2R2M=P3_14.2A_20%~D 1 2 4 PR81 47K_0402_1%~D 1 2 PR88 100K_0402_1%~D 2 1 C PQ27 SIR472DP-T1-GE3_POWERPAK8-5~D 1 2 3 5 PC50 2200P_0402_50V7K~D 2 1 PC49 4.7U_0805_25V6-K~D 2 1 PC48 4.7U_0805_25V6-K~D 2 1 PC47 0.1U_0603_25V7K~D 2 1 PC81 0.1U_0603_25V7K~D 2 1 2 PL25 FBMA-L11-453215-121LMA90T_2 ENTRIP2 +3VLP 1 ENTRIP1 Typ: 175mA B+ 2 RT8205E_B+ PC51 4.7U_0805_25V6-K~D 2 1 RT8205E_B+ 5 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. PQ62 DDTC115EUA-7-F_SOT323 4 3 2 Title +5VALWP/+3VALWP Size Document Number Date: Tuesday, November 30, 2010 Rev 0.3 LA-6601P Sheet 1 51 of 63 A B C D @ PJP22 2 2 1 1 1 1 JUMP_43X118 VCCP_RT8290B_B+ LGATE 9 1 8 7 1 2 @ PC69 4.7U_0805_25V6-K~D 2 1 PC68 4.7U_0805_25V6-K~D 2 1 PC59 2200P_0402_50V7K~D 2 1 PC198 4.7U_0805_25V6-K~D 2 1 1 + 2 VTTPW RGOOD 2 VSSIO_SENSE PR106 0_0402_5%~D 1 2 VCCP_AGND PR107 0_0402_5%~D 2 1 VCCIO_SENSE 8 +3VS 10K_0402_1%~D 2 PR105 10K_0402_1%~D 1 3 @ 8 PR109 1 3 @ PR229 10K_0402_1%~D VCCP TDC 8.8A Peak Current 12.5A OCP current 15A 1 2 @ PQ36 SSM3K7002FU_SC70-3 VCCP_PWRCTRL S 2 G PC79 0.01U_0402_16V7K~D 3 100K_0402_5%~D PR111 1 PR110 2 1 10K_0402_5%~D @ D 2 1 2 @ PR117 0_0402_5%~D 1 2 1 @PR108 @PR108 10K_0402_5%~D PC76 4.7U_0805_10V6K~D PR99 10_0402_5%~D 1 PR104 4.02K_0402_1%~D 1 2 2 VCCP_AGND +5VS @ PR103 35.7K_0402_1%~D 1 2 RT8209BGQW _W QFN14_3P5X3P5 PR102 0_0402_5% 2 @ PC77 47P_0402_50V8J~D 1 2 3 2 1 4 1 PGOOD +5VALW DL_VCCP PC73 330U 2.5V Y D2 LESR9M~D 10 2 1 VDDP VFB=0.75V +VCCPP 2 LX_VCCP 11 1 12 CS AON6784L-1N_DFN8~D PHASE 5 DH_VCCP PQ35 NC 14 13 B+ @ PL12 2.2UH_FDVE1040-2R2M=P3_14.2A_20%~D 1 2 3 2 1 FB UGATE 2 5 BOOT VDD 6 15 1 EN/DEM VOUT 4 2 PC75 1U_0603_10V6K~D 3 PR97 PC72 0_0603_5%~D 0.1U_0603_25V7K~D 1 2BST_VCCP-1 2 1 BST_VCCP PR101 4.99K_0402_1%~D 1 +5VALW TON PGND PR100 10_0603_5% 1 2 2 2 GND 1 PU5 @PC71 @PC71 0.1U_0402_16V7K~D 2 2 @ PR267 300K_0402_5%~D PR98 4.7_1206_5%~D 4 1 9,20,47,54 SUSP# 680P_0402_50V7K~D PC78 2 1 2 PR96 0_0402_5%~D 1 2 PC62 0.1U_0603_25V7K~D 2 1 SIR472DP-T1-GE3_POWERPAK8-5~D 5 PQ34 PR95 267K_0402_1%~D 1 2 1 2 PL26 FBMA-L11-453215-121LMA90T_2 PJP7 2 2 1 1 @ +VCCPP JUMP_43X118 PJP8 2 2 1 1 @ +VCCP JUMP_43X118 PJP9 2 @ 2 +1.05VS 1 1 JUMP_43X118 4 4 Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A B C Title +VCCPP Size Document Number Date: Tuesday, November 30, 2010 Rev 0.3 LA-6601P D Sheet 52 of 63 A B C D 1 1 PJP25 1.8VSP_RT8290B_B+ 2 2 1 1 B+ PC70 4.7U_0805_25V6-K~D 2 1 2 PR153 267K_0402_1%~D 1 2 PR123 0_0402_5%~D 2 2 RT8209BGQW _W QFN14_3P5X3P5 3 PC89 4.7U_0805_10V6K~D 1 PC93 NC 8 7 @ PC88 47P_0402_50V8J~D 1 2 3 2 1 4 + 2 220U_6.3VM_R15 +5VALW DL_1.8VSP 1 9 PR115 4.7_1206_5%~D 10 680P_0402_50V7K~D PC86 2 1 2 VDDP LGATE VFB=0.75V AO4712L_SO8~D LX_1.8VSP 11 +1.8VSP 5 6 7 8 12 CS PQ59 PGOOD PHASE 3 2 1 FB 6 BOOT 5 14 1 VDD DH_1.8VSP PL14 3.3UH_PCMB064T-3R3MS_7A_20% 1 2 1 FB_1.8VSP VOUT 4 13 1 PC90 1U_0603_10V6K~D 3 UGATE 2 1 VDD_1.8VSP TON PR158 PC92 0_0603_5%~D 0.1U_0603_25V7K~D BST_1.8VSP 1 2 BST_1.8VSP-1 2 1 PR125 2.87K_0402_1%~D PR116 10_0603_5% 1 2 2 +5VALW 2 PGND 2 TON_1.8VSP PU7 EN/DEM @PC91 @PC91 0.1U_0402_16V7K~D GND 2 @ PR268 300K_0402_5%~D 15 1 4 1 9,20,47,54 SUSP# 1 AO4466L_SO8~D PQ58 5 6 7 8 2 PC87 2200P_0402_50V7K~D 2 1 PC74 0.1U_0603_25V7K~D 2 1 @ JUMP_43X118 3 1 PR154 14.3K_0402_1%~D 1 2 2 PR151 10K_0402_1%~D 1.8VSP TDC 1A Peak Current 1.45A OCP current 1.7A PJP13 +1.8VSP 2 @ 2 1 1 +1.8VS JUMP_43X118 4 4 Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A B C Title +1.8VSP Size Document Number Date: Tuesday, November 30, 2010 Rev 0.3 LA-6601P D Sheet 53 of 63 10 LGATE 9 +5VALW DL_1.5VP 2 3 2 1 PC100 4.7U_0805_25V6-K~D 2 1 PC168 0.1U_0603_25V7K~D 2 1 PC94 0.1U_0603_25V7K~D 2 1 B+ JUMP_43X118 @ PL16 2.2UH_FDVE1040-2R2M=P3_14.2A_20%~D 1 2 1 +1.5VP 3 2 1 + 2 PC108 @ 680P_0402_50V7K~D 2 PC106 4.7U_0805_10V6K~D 1 PR129 @ 4.7_1206_5%~D 1 PR249 2 75K_0402_1%~D 2 PR134 10K_0402_1%~D 1 RT8209BGQW _W QFN14_3P5X3P5 2 NC 8 1 4 PR131 5.9K_0402_1%~D PGOOD 1 1 PC103 220U_6.3VM_R15 CS_1.5VP VDDP VFB=0.75V 2 1 LX_1.5VP 11 @ PJP23 2 2 12 CS AON6784L-1N_DFN8~D PHASE PC102 0.1U_0603_25V7K~D 2 1 PL27 FBMA-L11-453215-121LMA90T_2 1 2 5 DH_1.5VP PR128 0_0603_5%~D 1 2 BST_1.5VP_2 PQ38 13 PGND 6 BOOT FB 14 1 5 PR133 10K_0402_1%~D 1 2 6 2 1 @ PC618 0.01UF_0402_25V7K 1 PR250 2 1 10K_0402_5%~D 3 DMN66D0LDW-7 2N SOT363-6 1 2 @ PC616 0.01UF_0402_25V7K 4 PR244 PQ64B 10K_0402_5%~D 1 2 5 DMN66D0LDW-7 2N SOT363-6 2 PQ64A 1 1.5VDDR_VID0 VDD BST_1.5VP UGATE 1 1 PR248 150K_0402_1%~D 1 2 2 PR246 10K_0402_5%~D 2 1 2 2 18 VOUT 4 GND @ PC107 47P_0402_50V8J~D 1 2 +3VALW +3VALW 3 7 PC105 1U_0603_10V6K~D PR242 10K_0402_5%~D TON 1 PR130 10_0603_5% 1 2 2 +5VALW 2 EN/DEM PU8 2 2 @PC101 @PC101 0.1U_0402_16V7K~D 15 1 1 4 @ PR269 300K_0402_5%~D PR240 10K_0402_5%~D PQ37 PR127 0_0402_5%~D 1 2 39,47 SYSON 1 5 PR126 267K_0402_1%~D 1 2 SIR472DP-T1-GE3_POWERPAK8-5~D 1.5VP_RT8290B_B+ PC99 4.7U_0805_25V6-K~D 2 1 D PC98 4.7U_0805_25V6-K~D 2 1 C PC95 2200P_0402_50V7K~D 2 1 B 1 A 2 1.5VP TDC 10.3A Peak Current 14.7A OCP current 17.8A +3VALW DDR Vout 0 0 1.65V 0 1 1.6V 1 0 1.55V 1 1 1.5V (Default) 1 PR252 1.2K_0402_1%~D 1 2 3 1 2 PC113 4.7U_0805_6.3V6K~D 1 @ VTT 5 VTTSNS 8 6 S5 9 S3 7 PR136 10K_0402_1%~D 1 2 1 +3VALW @ 1 +1.5VP 2 PC111 1U_0603_10V6K~D GND VTTREF 3 10 +1.5V PJP16 JUMP_43X118 1 1 2 2 PC114 0.1U_0402_16V7K~D @ 1 SUSP# PC115 .1U_0402_16V7K~D PJP14 JUMP_43X118 1 2 2 @ 1 VLDOIN 2 2 PC112 4.7U_0805_6.3V6K~D +0.75VSP @ VDDQSNS VIN 2 1 JUMP_43X118 1 GND 2 11 2 PGND 1 PC109 2 1 1 4 @ PJP15 +1.5VP PU9 RT9026_MSOP10 2 PR253 1K_0402_1%~D 2 1 1 2 PC619 0.01UF_0402_25V7K @ bit1 = 1.5DDR_VID1 +3VALW 4.7U_0805_6.3V6K~D 2 2 1 1 @ PR247 10K_0402_5%~D 4 5 3 PR251 2 1 10K_0402_5%~D PQ65B DMN66D0LDW-7 2N SOT363-6 PR245 10K_0402_5%~D 1 2 PC617 0.01UF_0402_25V7K 1.5VDDR_VID1 2 3 2 PC110 2 1 1 PR241 10K_0402_5%~D 2 PQ65A 4.7U_0805_6.3V6K~D +3VALW 6 PR243 10K_0402_5%~D DMN66D0LDW-7 2N SOT363-6 1 DDR GPIO Output Voltage Selection bit2 = 1.5DDR_VID0 PJP20 JUMP_43X118 1 2 2 9,20,44,47,52,53 PJP17 0.75VSP TDC 1.4A Peak Current 2A OCP current 3A 4 2 +0.75VSP @ 2 1 1 +0.75VS JUMP_43X118 4 Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A B C Title +1.5VSP/0.75VSP Size Document Number Date: Tuesday, November 30, 2010 Rev 0.3 LA-6601P D Sheet 54 of 63 5 4 3 2 1 D D +5VALW @ PR256 10K_0402_1%~D 2 PC121 1 PR144 1 1U_0603_10V6K~D 2 0_0603_5%~D 2 2 +VCCP PR124 2.2_0603_1%~D 1 PL24 2 RTN UGATE VID1 PHASE VID0 EN 18 PL13 2.2UH_FDVE0630-2R2M_8.3A_20%~D 2 1 SET0 FSEL 13 1 PR255 PR140 0_0402_5%~D 12 3 2 1 VO 4 1 OCSET FB 10 PR150 1 11 SET1 2 9 +3VS 2 0_0402_5%~D ISL95870AHRUZ_UTQFN20_1P8X3P2 1 PC120 0.01U_0603_16V7K~D 1 2 SA_PGOOD PC116 4.7U_0805_6.3V6K~D 2 1 8 PR137 10_0402_5%~D 2 1 PR141 130K_0402_1%~D PC122 0.068U_0402_16V7K 1 2 1 10K_0402_1%~D 1 2 14 2 PGOOD PC123 680P_0402_50V7K~D SREF AO4710L_SO8 PR148 4.7_1206_5%~D 2 1 0_0402_5%~D 7 @ PR263 10K_0402_1%~D PC104 220U_6.3VM_R15 VTTPWRGOOD 2 1 1 VID0_SA 1 2 1 2 0_0402_5%~D C 15 5 6 7 8 6 16 PQ39 1 2 PC127 4.7U_0805_25V6-K~D 2 1 +VCCSAP 17 PR118 PR120 16.5K_0402_1%~D 2 1 2 0_0402_5%~D VID0_SA PR261 4.7K_0402_1%~D PR258 PR145 0_0402_5%~D 1 1 VCCSA_SEL VID[1] 5 2 2 9 PR254 1 VID1_SA 2 C B+ PR138 15.4K_0402_1%~D 4 VID1_SA @ PR262 10K_0402_1%~D PC194 1000P_0402_50VX7R~D 2 1 4 PC125 4.7U_0805_25V6-K~D 2 1 5 6 7 8 PC118 0.1U_0603_25V7K~D 2 1 PC126 2200P_0402_50V7K~D 2 1 PR152 0_0603_5%~D 1 2 PC96 0.1U_0603_25V7K~D 2 1 19 PQ40 1 BOOT 2 +VCCP VCC GND 2 FBMA-L11-453215-121LMA90T_2 3 2 1 PR146 2.67K_0402_1%~D 1 2 PGND SI4128DY_SO8~D 3 PC117 2 LGATE 1 2 20 PU10 10K_0402_1%~D PVCC PR257 1 2 1U_0603_10V6K~D PC119 2 1 0_0402_5%~D .1U_0402_16V7K~D 1 0_0402_5%~D VID[0] 1 + 2 PR149 10_0402_5%~D 2 1 H_FC_C22 PR259 1 2 1 9 @ PR266 1 2 PR143 715K_0402_1%~D PR147 1 2 4.7K_0402_1%~D PR142 1 2 1 20K_0402_1%~D 2 PR139 2.67K_0402_1%~D B B PR260 1 2 0_0402_5%~D VCCSA_SENSE 9 PR265 0_0402_5%~D 1 2 Note: RTN pin need reference output GND VID[0] 0 0 VID[1] 0 1 VCCSA Vout 0.9V 0.8V Required Yes Yes VSSSA_SENSE +VCCSAP TDC 4.2A Peak Current 6A OCP current 7.2A Yes Yes @ PJP26 2 2 1 +VCCSAP 1 +VCCSA JUMP_43X118 A A Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title PWR-VCCSA_COREP Size Document Number Date: Tuesday, November 30, 2010 Rev 0.3 LA-6601P Sheet 1 55 of 63 3 2 1 1 1 5 3 2 1 PC152 470P_0402_50V7K~D 2 1 1 ISPG 2 ISNG PC158 10U_0805_25V5K~D 2 1 2 2 + @PC163 220U_25V_M PC166 220U_25V_M 2 2 1 3 +VCC_CORE 2 PR207 ISEN2 1 2 10K_0603_1%~D PR208 2 1ISEN1 10K_0402_1%~D B PR209 VSUM+ 1 2 3.65K_0603_1%~D 3 2 1 2 PR210 2 1 ISEN3 10K_0402_1%~D PR213 1 1_0402_5%~D PC187 10U_0805_25V5K~D 2 1 PC188 10U_0805_25V5K~D 2 1 PC189 10U_0805_25V5K~D 2 1 @ PC190 10U_0805_25V5K~D 2 1 @ AON6414AL-1N_DFN 5 PQ54 AON6414AL-1N_DFN 3 2 1 4 PL23 0.36UH_ETQP4LR36AFC_28A_20%~D 4 1 4 3 PC197 680P_0402_50V7K~D 3 2 1 4 PR223 4.7_1206_5%~D 1 2 1 BOOT1 2 2.2_0603_5%~D PC196 0.1U_0603_25V7K~D 1 2 1 PQ56 PR222 5 PHASE1 LGATE1 1 + PR206 4.7_1206_5%~D PC178 680P_0402_50V7K~D 1 PC134 680P_0402_50V7K~D 2 1 PC133 470P_0402_50V7K~D 2 1 10U_0805_25V5K~D 2 1 PC135 PC205 10U_0805_25V5K~D 2 1 0.1U_0603_25V7K~D 2 1 PC97 AON6414AL-1N_DFN PC155 10U_0805_25V5K~D 2 1 PC156 10U_0805_25V5K~D 2 1 PC157 10U_0805_25V5K~D 2 1 5 PQ46 3 2 1 5 5 PQ51 5 PQ53 4 VSUM- 2 1 10_0402_1%~D A PR196 1 1_0402_5%~D PL22 0.36UH_ETQP4LR36AFC_28A_20%~D 4 1 2 2 1 PC192 0.01U_0402_16V7K~D PH5 10KB_0402_5%_ERTJ0ER103J~D UGATE1 AON6702L-1N_DFN8 PR221 +VCC_CORE 2 PR224 ISEN1 1 2 10K_0603_1%~D PR225 2 1 ISEN2 10K_0402_1%~D PR226 VSUM+ 1 2 3.65K_0603_1%~D PR227 2 1 ISEN3 10K_0402_1%~D PR228 VSUM- 2 1 1_0402_5%~D Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 C CPU_B+ 3 2 1 8 VSSSENSE PR214 2.61K_0402_1%~D 1 PR219 909_0402_1% PR191 2 1ISEN2 10K_0402_1%~D 1 @ VSUM- AON6702L-1N_DFN8 PC191 2 1 330P_0402_50V7K~D 8 VCCSENSE PC193 330P_0402_50V7K~D 2 1 +VCC_CORE 4 5 2 1 10_0402_1%~D 4 VSUM+ PQ55 PC202 560P_0402_50V7K~D 2 1 2 @ 2 @ 1 PR220 2K_0402_1% PR218 2 1 2 ISEN1 ISEN2 ISEN3 1 0.22U_0402_6.3V6K~D .1U_0402_16V7K~D PR216 1 3.57K_0402_1% 1 0.22U_0402_6.3V6K~D PC138 2 1 0.1U_0603_25V7K~D 2 1 PC124 3 2 1 1 2 2 PC183 2 1 2 470P_0402_50V7K~D PC181 2 4 2 VSUM- PC176 1U_0603_10V6K~D PC182 1 PC195 2 1 PC184 150P_0402_50V8J~D PC174 PR204 0.1U_0603_25V7K~D BOOT2 2 1 2 1 2.2_0603_5%~D LGATE2 PR217 2 1 11K_0402_1%~D PR215 316K_0402_1%~D 1 2 1 2 10U_0805_25V5K~D 0.1U_0603_25V7K~D 2 1 PC128 4 PC177 0.22U_0603_25V7K~D 0.022U_0402_16V7K~D 2 PR212 2 1 499_0402_1%~D 1 0.22U_0402_6.3V6K~D VSUM2 +VCC_CORE PR187 2 1ISEN1 10K_0402_1%~D 2 PR193 1 2 3.65K_0603_1%~D PHASE2 PR202 0_0402_5%~D +5VALW 1 PR205 1_0603_5%~D 0.47U_0603_16V7K~D PC186 2 1 499K_0402_1%~D PC179 2 2 PC185 2 1 @PR211 @ PR211 @ PC175 @PC175 10P_0402_25V8J 2 1 PC199 0.068U_0402_16V7K~D 2 1 PC180 39P_0402_50V7K~D 2 1 2 PR201 0_0603_5%~D 1 2 PC169 AON6702L-1N_DFN8 10U_0805_25V5K~D 2 1 2 1 2 1 PC170 10U_0805_25V5K~D PC159 PR188 680P_0402_50V7K~D 4.7_1206_5%~D 2 1 PC171 10U_0805_25V5K~D 2 1 PC172 10U_0805_25V5K~D 2 1 UGATE2 CPU_B+ 1 1 1000P_0402_50V7K~D PC173 2 1 1 8.06K_0402_1%~D PR203 2 B 1 PR200 27.4K_0402_1%~D @PR178 @ PR178 2 CPU_B+ 1 2 BOOT1 2 @ PR182 442_0402_1%~D 3 PR189 ISEN3 1 2 10K_0603_1%~D 2 UGATE1 25 D 100_0402_1%~D PL21 0.36UH_ETQP4LR36AFC_28A_20%~D 4 1 VSUM+ AON6702L-1N_DFN8 PHASE1 26 4 PQ50 27 2 +5VS PR192 0_0603_5%~D 5 LGATE1 PQ48 AON6414AL-1N_DFN 1 28 PC137 10U_0805_25V5K~D 2 1 0.1U_0603_25V7K~D 2 1 PC129 2 LGATE2 4 29 4 PQ47 43P_0603_50V8 1 2 PC148 680P_0402_50V7K~D PR169 4.7_1206_5%~D 1 2 1 5 PQ45 1 9 @ PR190 @PR190 0_0603_5%~D 1 2 31 30 PC136 10U_0805_25V5K~D 2 1 0.1U_0603_25V7K~D 2 1 AON6702L-1N_DFN8 0.1U_0603_25V7K~D 2 1 AON6414AL-1N_DFN 5 PQ41 5 3 2 1 5 4 4 3 2 1 PROG1 7 1 1 1 2 PC167 .033U_0402_16V7K~D @ ISL6208ACRZ-T_QFN8_3X3 PU12 24 VIN 23 ISUMP VDD 22 21 RTN ISUMN 20 470P_0402_50V7K~D 2 1 2 PH4 3.83K_0402_1%~D 470K_0402_5%_ERTJ0EV474J~D 19 13 PR199 BOOT1 LGATE PQ52 PH1 UG1 PHASE GND @ 3 2 1 VR_HOT# PWM 8 AON6414AL-1N_DFN VSSP1 UGATE AON6702L-1N_DFN8 LG1 33 32 FCCM 3 2 1 PWM3 ISL95831CRZ-T_TQFN48_6X6 IMON @ PC165 @PC165 2 1 PC154 0.1U_0603_25V7K~D PR171 1_0402_5%~D PC146 .1U_0402_16V7K~D 2 11K_0402_1%~D 2 PC150 1 5 VR_ON VW 1 PQ49 VDDP NTC BOOT AON6414AL-1N_DFN PHASE2 +VCC_GFXCORE_AXG 2 1 PR173 CPU_B+ B+ PL20 0.36UH_ETQP4LR36AFC_28A_20%~D 4 1 PH3 10KB_0402_5%_ERTJ0ER103J~D PR172 1 2 1 2 7.5K_0402_1%~D AON6702L-1N_DFN8 34 2 1 PC161 1U_0603_10V6K~D SCLK PGOOD VCC PGND PR186 @ 3 3 2 1 UGATE2 @ PL19 PR170 10K_0603_1%~D 5 BOOT2 35 0_0603_5%~D 36 2 LG2 VSEN 12 VSSP2 ALERT# 18 9 SDA ISEN1 8 2 1 PR181 2.2_0603_5%~D 1 BOOT2 HCB4532KF-800T90_1812 1 2 .1U_0402_16V7K~D 2 37 LGG 3 PH2 17 7 3 2 1 3 2 1 LGATEG PHASEG ISNG UGATEG 38 40 39 PHG UGG 41 PROG2 BOOTG 42 43 ISNG NTCG 45 46 47 48 44 ISPG RTNG VSENG FBG COMPG 2 PGOODG ISEN2 2 PR195 1.91K_0402_1%~D 4 PU11 5 UG2 16 6 PQ44 PQ43 3 2 1 +5VS PR177 2 1 10_0402_1%~D IMONG ISEN3/ FB2 SVID_SCLK 0_0402_5%~D 2 GND 49 5 11 2 @PR198 @ PR198 1 2 499_0402_1%~D 4 SVID_ALERT# 10 PC164 +VCCP SVID_SDA VGATE 1 VR_HOT# 3 VWG 15 PC160 .047U_0603_25V7~D 1 2 1 PR197 2 19.1K_0402_1%~D 5 2 FB 1 PR194 VSSSENSE 1 COMP VR_ON IMON 0.01U_0402_16V7K~D 4 6 14 VGATEG Alert# PU resister need close CPU, so the PU resister in HW schematic. but DAT and CLK need close PWM-IC, so the PU resister in POWER schematic. LGATEG VSS_AXG_SENSE 9 @ 2 1 1.91K_0402_1%~D 8 VR_SVID_CLK 1 330P_0402_50V7K~D PC145 2 1 4 PHASEG +3VS PR185 8 VR_SVID_ALRT# +3VS PC141 1 2 NTCG PR180 1 2 0_0402_5%~D BOOTG ISPG PR184 2 1 54.9_0402_1%~D 1 2 PR183 130_0402_1%~D PC153 .1U_0402_16V7K~D 1 2 PC151 2 1 @ 8 VR_SVID_DAT 4 PC140 PR165 0.1U_0603_25V7K~D BOOTG 2 1 2 1 2 1 10_0402_1%~D PR166 VCC_AXG_SENSE 9 2.2_0603_5%~D +VCCP .047U_0603_25V7~D PR179 2 1 18.2K_0402_1%~D 9 VSS_AXG_SENSE +VCC_GFXCORE_AXG PR174 0_0603_5%~D 2 1 PC143 2 1 2 1 422_0402_1%~D 39P_0402_50V7K~D 680P_0402_50V7K~D PC147 PR175 PR176 2 1 2 1 2 1 475K_0402_1%~D 2.32K_0402_1%~D 150P_0402_50V8J~D IMONG C PC144 2 1 PR168 330P_0402_50V7K~D PR164 27.4K_0402_1%~D PC142 2 1 @ UGATEG 2 1U_0603_10V6K~D 1 2 1 PC162 1U_0603_10V6K~D 1000P_0402_50V7K~D PC139 2 1 PR163 2 8.06K_0402_1%~D 1 PR167 499K_0402_1%~D 2 1 D 2 1 PH2 470K_0402_5%_ERTJ0EV474J~D PC149 2 1 PR162 2 1 3.83K_0402_1%~D 1 PC204 330P_0402_50V7K~D 2 1 2 PR270 2K_0402_1% AON6414AL-1N_DFN PQ42 NTCG 470P_0402_50V7K~D 1 PC130 2 CPU_B+ PC131 3 @ PC132 @PC132 2 1 AON6702L-1N_DFN8 4 5 5 2 Title PWR-CPU_CORE Size Document Number Date: Tuesday, November 30, 2010 Rev 0.3 LA-6601P Sheet 1 56 of 63 A 5 4 3 Version Change List ( P. I. R. List ) Item Page# 1 Title 56 CPU_CORE Date Request Owner 10'06/17 Compal_Alvin 2 Page 1 Issue Description Improve thermal compensation. 1 Solution Description Rev. Change PR164 from 0ohm to 27.4Kohm. X00 D D 10'06/17 Compal_Alvin Improve dc to dc power efficiency. Delete all snuber for all dc-dc. Delete PR85, PR86, PR98, PR115, PR129, PR148, PR169, PR188, PR206, PR223. Delete PC60, PC61, PC78, PC86, PC108, PC123, PC148, PC159, PC178, PC197. X00 Charger 10'07/22 Compal_Alvin Voltage rating enhancement. Change PR49 form 14.3K to 15K. X01 Charger 10'07/22 Compal_Alvin Output capacitor rating enhancement. Add PC46 10uF 0805 to output. X01 +5VALWP/+3VALWP 10'07/22 Compal_Alvin Enhance Input capacitor rating and switch waveform. Add PC80 4.7uF 0805 to input and change low side to FDMS0310S. X01 56 CPU_CORE 10'07/22 Compal_Alvin Improve EMC solution. Add PC97, PC124, PC128, PC129, PC130, PC131 0.1uF 0603. X01 7 51 +5VALWP/+3VALWP 10'07/22 Compal_Alvin Improve EMC solution. Add PC80 0.1uF 0603. X01 8 54 +1.5VP/0.75VSP 10'07/22 Compal_Alvin Improve EMC solution. Add PC168 0.1uF 0603. X01 9 55 VCCSAP 10'07/22 Compal_Alvin Improve EMC solution. Add PL24 120ohm bead, and PC194 1000pF 0402. X01 10 53 +1.8VSP 10'07/22 Compal_Alvin Improve low side switching waveform. Change PQ59 from AO4466 to AO4712L X01 11 49 DCIN/DECTOR 10'08/03 Compal_Alvin Add dynmatic trubo function to control trubo. Add dynamatic trubo function. X01 12 52 +VCCPP 10'08/10 Compal_Alvin For met Intel SPEC. Change VCCPP output CAP to 470uF. X01 13 56 CPU_CORE 10'08/10 Compal_Alvin Adjust the CPU loadline and transient to met Intel SPEC. PC167 and PC186. PR216, PR219, PR202, PR180, PR176, PR179, PR182, PR167, PR186. X01 14 56 CPU_CORE 10'09/28 Compal_Alvin Improve CPUCore PWRGOOD signal. Change VDD power rail from 5VS to 5VALW and add PR220 and PC202. X02 15 55 VCCSAP 10'09/28 Compal_Alvin Improve VCCSA PWRGOOD signal. Change VCC power rail from 5VS to 5VALW. X02 16 49/50 DCIN/DECTOR BATTERY CONN/OTP 10'09/28 Compal_Alvin Saving S4/S5 power consumption. Change PU1 Pin8 from Pre_V to VL. X02 10'10/12 Compal_Alvin For EMI solution. Add PL25, PL26, PL27 P/N:SM01000DJ00 (S SUPPRE_ FBMA-L11-453215-121LMA90T 1812) Add 10uF PC205 and change PC23, PC24 to 10uF. Pop PC133 and PC134. X02 2 51-57 3 50 4 50 5 51 6 all DC-DC schematic C B C 51/52/54 +5VALWP/+3VALWP +VCCPP +1.5VP/0.75VSP 17 A B A Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title PWR-PIR Size Document Number Date: Tuesday, November 30, 2010 Rev 0.3 LA-6601P Sheet 1 57 of 63 5 4 3 Version Change List ( P. I. R. List ) Item Page# 18 Title 51-56 all DC-DC schematic Date Request Owner 10'10/13 Compal_Alvin EMI solution. 50 Charger 10'11/02 Compal_Alvin Precharger schematic bom change for old solution 1 Page 1 Issue Description D 19 2 Solution Description Rev. Add all snuber for all dc-dc. Add PR85, PR86, PR98, PR115, PR129, PR148, PR169, PR188, PR206, PR223. Add PC60, PC61, PC78, PC86, PC108, PC123, PC148, PC159, PC178, PC197. X02 Delete PD13, PD15, PR51, PQ22, PC32. Add PQ60, PR231. X02 D C C B B A A Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5 4 3 2 Title PWR-PIR Size Document Number Date: Tuesday, November 30, 2010 Rev 0.3 LA-6601P Sheet 1 58 of 63 5 4 3 Version Change List ( P. I. R. List ) Item Page# 1 Title 29 DP SW for mDP CONN Date Request Owner 10'07/22 Compal_Yungmao 2 1 Page 1 Issue Description Solution Description Mini DP no function Modified JMDP1 pin define Rev. X00 D D 2 39 USB 3.0 PD720200 10'08/10 Compal_Yungmao USB3.0 transfer speed is too low L33 L34 L35 L36 3 31 HDMI input - STDP6038 10'07/22 Compal_Yungmao HDMI-IN no function Change U7 pin111, 112 to U7 pin72,pin71 X00 4 34-35 HD Audio_IDT92HD73C 10'08/3 Compal_Yungmao S/PDIF jack no function net LINE_OUT_JD connect to R1677 pin2 delete R721, R722, C740 X00 5 38 10'08/11 Compal_Yungmao Install Bluetooth module might be cause system can't bootable remove net name BT_ACTIVE X00 6 33 GLAN AR8151 AL1A 10'08/9 Compal_Yungmao LOM can't work in 1000Mbps speed and no LED is on swap JLAN1 pin11 with pin13, 7 34 HD Audio_IDT92HD73C 10'08/10 Compal_Yungmao Audio left and right channel reverse swap U9, U16 pin6 with pin8 8 40 10'08/3 Compal_Yungmao USB charging Device can't be charging in S4/S5 with" AC and Battery " mode change D18 from +5VS to +5VALW X00 9 14 10'07/22 Compal_Yungmao -9% of 3.3V (3.003) will cause no display when system power on add R1817, R1816, Q281 X00 10 5 PROCESSOR(2/6) PM,XDP,CLK 10'07/15 Compal_Yungmao for EMI/EDS requirement add RC121,RC125,RC126,RC127,RC128 X00 11 10~13 DDRIII DIMMA ~ DDRIII DIMMD 10'07/15 Compal_Yungmao for DDR3 module can select serial address add RD35,RD36,RD37,RD38,RD39,RD47,RD49 X00 10'08/4 Compal_Yungmao Mini Card -WLAN / DMC / BT swap swap swap swap pin3 pin3 pin3 pin3 with with with with pin4, pin4, pin4, pin4, net net net net U3TXDN2_L, U3TXDP1_L, U3RXDN2_L, U3RXDP1_L, U3TXDN2 U3TXDP1 U3RXDN2 U3RXDP1 X00 net LAN_LINK#, LAN_LED2# X00 C C B USB/ESATA TS3USB221RSER MXMIII Connector A 14 MXMIII Connector A for MXM3.0 module power saving B X00 12 13 X00 add R1818, R1819 pull high 25 LVDS SW- 1 to 2 & GPU/PCH 10'07/13 Compal_Yungmao X00 add R313, R314 STDP6038 chipset vendor require to add for debug used 14 04 PROCESSOR(6/6) 10'09/20 Compal_Ray derating fail QC4 change to SB00000090L X02 15 14 MXMIII Connector 10'09/20 Compal_Ray battery can't charge R1818, R1819 depop, change connection EC_SMB_DA1 to VGA_SMB_DA1 X02 16 17 A 17 26 PCH (3/8) 10'09/20 Compal_Ray can't boot when plug bluetooth module. pop RH95 X02 LVDS SW & CONN 10'09/20 Compal_Ray Web CAM can't work. Change CAM power to 3VS X02 A Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title EE PIR(1) Size 4 3 2 Rev 1.0 LA-6601P Date: 5 Document Number Tuesday, November 30, 2010 Sheet 1 59 of 63 5 4 3 Version Change List ( P. I. R. List ) Item Page# 17 28 Title HDMI SW Date 10'09/20 Request Owner 2 Page 2 Issue Description Compal_Ray 1 Solution Description Follow A18 +HDMI_5V_OUT circuit Rev. X02 remove QV5,CV40,RV35,QV6,RV34,Add R1896 D D 18 28 HDMI SW 10'09/20 Compal_Ray HDMI can't work Change UV2 HPD connection X02 19 30 HDMI SW for DMC 10'09/20 Compal_Ray DP can't work pop R1865 add R1958,R1959, remove C52,C53 X02 20 40 USB/ESATA 10'09/20 Compal_Ray eSATA can't work remove RS12 X02 21 40 USB/ESATA 10'09/20 Compal_Ray update for eSATA power share function PWRSHARE_EN# GPIO assign to EC pin 86 Add R97 for PWRSHARE_EN# pull down add R1699,D31 X02 22 15 PCH (1/8) 10'09/20 Compal_Ray ME position redifned for HDD. Swap HDD1(Port 1) ,HDD2(Port 0) X02 23 39 USB3.0 PD720200 10'09/27 Compal_Ray USB3.0 can't work depop R201, pop R202 0 ohm X02 24 17 PCH (3/8) 10'09/27 Compal_Ray AV17 doesn't support deep sleep mode pop RH126, add RH159 and depop it depop RH139 ,RH134 X02 25 15 PCH (1/8) 10'09/27 Compal_Ray Add HDA BUS ON/OFF control circuit, add CH17,UH9,RH30,RH50,QH10,RH267 X02 26 15 PCH (1/8) 10'09/27 Compal_Ray follow Design guide Add RH47 for BBS_BIT0_R X02 27 17 PCH (3/8) 10'09/27 Compal_Ray follow Design guide Add R1687 for PCH_RSMRST# pull down X02 28 17 PCH (3/8) 10'09/27 Compal_Ray Change ACIN connection Remove RH150 ,RH137,Add R1900,R1899,QH11 X02 29 35 Speaker AMP 10'09/27 Compal_Ray To solve po noise when HDMI IN toggling add Q10 30 04 PROCESSOR(6/6) 10'09/27 Compal_Ray derating fail QC4 change to SB00000090L 31 34 HD Audio 10'09/27 Compal_Ray Add HDMI IN audio sense circuit. add Q284 R1902,R1903 X02 32 34 HD Audio 10'09/27 Compal_Ray to solve backdrive issue on +3VS add D54 X02 33 15 PCH (1/8) 10'09/27 Compal_Ray follow DG1.5 recommand Add R1960 X02 C B C B X02 X02 A A Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title EE PIR(2) Size 4 3 2 Rev 1.0 LA-6601P Date: 5 Document Number Tuesday, November 30, 2010 Sheet 1 60 of 63 5 4 3 Version Change List ( P. I. R. List ) Item Page# 34 16 Title Date PCH (4/8) 10'09/27 Request Owner 2 Page 2 Issue Description Compal_Ray 1 Solution Description PLTREST_VGA issue Rev. X02 Add R28 D13 and change RH170 to 0 ohm D D 35 28 HDMI SW 10'10/01 Compal_Ray Addd R58 for HMI_SW_DETECT bypass direct due to it's desn't need level shift to 5V Add R58 X02 36 35 Speaker AMP 10'10/01 Compal_Ray add mute siwtch to solve po noise issue Add U619 ,C1843 X02 37 33 GLAN AR8151 AL1A 10'10/01 Compal_Ray Change CL39 to 3KV spec for Hi-port test change CL39 to 1000P_1808_3KV7K~D X02 38 15 PCH 10'10/07 Compal_Ray Change X02 39 39 USB 3.0 10'10/07 Compal_Ray Add power option 40 31 HDMI 10'10/07 For double pull high Remove R81,R83 X02 41 15 PCH 10'10/07 Change RTC circuit Change RTC circuit and change DH1 to CHN202UPT,Reomve RH250 X02 42 33 GLAN AR8151 AL1A 10'10/07 Compal_Ray Crystal EA result 43 9,10,11 CPU 10'10/07 Compal_Ray Remove XDP 0 ohm resistor 44 16 PCH 10'10/07 Compal_Ray 45 5 CPU 10'10/07 Compal_Ray Follow Design guide 1.5 31 ST6038 10'10/07 Compal_Ray Derating issue 47 9 CPU 10'10/07 Compal_Ray S3 issue Reserve CC178 for CPU1.5V_S3_GATE timing delay 48 31 ST6038 10'10/07 Compal_Ray By vendor review Follow vendor to depop R1744 X02 49 32 ST4028 10'10/07 Compal_Ray By vendor review Change U607 to M25PE20 X02 50 31 ST6038 10'10/08 Compal_Ray Timing issue Rename location CLIP1 to COMS1 and CLIP2 to ME1 Add R1964,R1965,R1966,R1967 X02 for U37 power option C B C 46 Compal_Ray Compal_Ray Change CL18,CL19 to 15pF by crystal EA result X02 CPU XDP depop, Remove:RC68~RC71, Change to depop RC59,RC61~RC67,RC121,RC121,RC125~RC128,RC50,RC51 Add T51~T54 Crystal EA result X02 X02 Change YH2 to X5H025000DC1H-H, CH23,CH24 to 12pF by crystal EA result Add RC113 to reserve PCH_PWROK for VDDPWRGOOD B X02 X02 Change L13 to BLM18AG601SN1D for derating issue X02 X02 Add R172 for LDO timing enable timing delay A A Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title EE PIR(2) Size 4 3 2 Rev 1.0 LA-6601P Date: 5 Document Number Tuesday, November 30, 2010 Sheet 1 61 of 63 5 4 3 Version Change List ( P. I. R. List ) Item Page# 51 Title 16 Codec Date 2010/10/8 Request Owner 2 Page 2 Issue Description Compal_Ray 1 Solution Description Mute issue Rev. X02 Add U620,C1844,U621,C1845 for mute D D 52 28 MXM 2010/10/8 Compal_Ray Follow A18 Change AC_BATT# to EC_AC_BAT# , and remove R1817,D72, add U622,C1823 X02 53 35 USB3.0 2010/10/8 Compal_Ray EMI issue Change L33~L38 to DLW21SN670HQ2L X02 54 26 LVDS SW 2010/10/8 Compal_Ray Remove resistor for double pull high Remove R323 ,R326 X02 55 35 Audio 2010/10/12 Compal_Ray By Maxim review result Change C154,C158 to .022uF and R140,R145 to 20K X02 56 15 PCH 2010/10/12 Compal_Ray Reserve o ohm for Add RH51 X02 57 44 ENE 2010/10/12 Compal_Ray Change GPIO Change GPIO46 to VGA_ON and depop RH118 X02 58 24,44 ENE 2010/10/12 Compal_Ray Change GPIO, and add backlight control circuit Change VGA_ON to LCD_BKL_EN, and add backlight control circuit, add Q39,C332,R422,R423,Q28,C331 X02 59 29 DP 2010/10/12 Compal_Ray DP dual mode can't display Remove C301,C308 X02 60 35 Audio 2010/10/12 Compal_Ray To reach 16dB 61 15 PCH 2010/10/22 Compal_Ray Pop RH50 for ME lock issue Pop RH50 62 37 ODD 2010/10/22 Compal_Ray Re define ODD pin For ODD power require, add one more power pin A00 63 37 ODD 2010/10/22 Compal_Ray Remove zero power ODD switch. Remove SW1 and add R173 0 ohm for ODD_DA# A00 64 46 2010/10/22 Compal_Ray Remove reserve power switch Remove SW4,SW5 A00 65 24,44 LCD 2010/10/22 Compal_Ray Correct net name Rename LCD_BKL_EN# to LCD_BKL_EN A00 66 44 BID 2010/10/22 Compal_Ray Change BID Change BID, R225 to 56K A00 67 34 BID 2010/10/22 Compal_Ray HDMI in audio issue. change HDMI_IN_SELECT# to HDMI_TOGGLE HDA_SDOUT C B C power switch X02 Change R137,R142 to 16.2K A00 B A00 A A Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title EE PIR(2) Size 4 3 2 Rev 1.0 LA-6601P Date: 5 Document Number Tuesday, November 30, 2010 Sheet 1 62 of 63 5 4 3 Version Change List ( P. I. R. List ) Item Page# 68 Title 26 AMD Date Request Owner 2 Page 2 Issue Description 2010/10/22 Compal_Ray 1 Solution Description AMD MXM card Brightness Contrl Hot/Key issue Rev. A00 add RV46 and connect to SG_AMD_BKL. D D 69 17,28, 29,30 NV 2010/10/22 Compal_Ray Meet NV Optimus V1.2 Change AC_BATT# to EC_AC_BAT# , and remove R1817,D72, add U622,C1823 A00 70 27 CRT 2010/10/22 Compal_Ray CRT switch high EOS failure rate Change C13~C15 to 0.01uF. A00 71 31 HDMI 2010/10/22 Compal_Ray HDMI in cable detect issue Add R1968,Q285,R1845 A00 72 44 ENE 2010/10/22 Compal_Ray Crystal remove for ENE Add C1846 for not use crystal for ENE A00 73 24 EDP 2010/10/29 Compal_Ray Remove RV39 Remove RV39 for LCDVDD_ON double pull down A00 74 36 HDD 2010/10/30 Compal_Ray Left HDD pin to NC Left JHDD2 Pin 20,21,22 to NC A00 C C B B A A Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Title EE PIR(2) Size 4 3 2 Rev 1.0 LA-6601P Date: 5 Document Number Tuesday, November 30, 2010 Sheet 1 63 of 63
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