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User Manual: DVDR980
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DVD-Video Recorder
DVDR980 & DVDR985
/001 /021 /051
CL 26532011_000.eps
160102
Contents
1
2
3
4
5
6
7
Page
Technical Specifications and
Connection Facilities
Warnings, Laser Safety Instructions and Notes
Directions for Use
Mechanical Instructions and Exploded Views
Diagnostic Software Descriptions and
Troubleshooting
Block and Wiring Diagram
Block Diagram
Wiring Diagram
Electrical Diagrams And Print-Layouts
Power Supply
(Diagram 1)
Power Supply
(Diagram 2)
Display Panel
(Diagram 1)
Front AV Part
IR & Standby Panel
Analog Board: All In One 1
(Diagram 1)
Analog Board: All In One 2
(Diagram 2)
Analog Board: Tuner / Demodul. (Diagram 3)
Analog Board: In / Out 1
(Diagram 4)
Analog Board: In / Out 2
(Diagram 5)
Analog Board: In / Out 3
(Diagram 6)
Analog Board: In / Out 4
(Diagram 7)
Analog Board: Sound Processing (Diagram 8)
Analog Board: Follow Me
(Diagram 9)
Analog Board: VPS
(Diagram 10)
Analog Board: Power Supply
(Diagram 11)
Contents
2
5
7
33
38
93
94
Diagram
95
96
101
105
107
108
109
110
111
112
113
114
115
116
116
117
PWB
97-100
97-100
102->
106
107
121->
121->
121->
121->
121->
121->
121->
121->
121->
121->
121->
Page
Analog Board: Audio Converter (Diagram 12)
Analog Board: RGB-YUV Conv. (Diagram 13)
Analog Board: Digital In / Out
(Diagram 14)
Analog Board: Fan Control
(Diagram 15)
DVIO Front Board
DVIO Board: 1394 Interface
(Diagram 1)
DVIO Board: Microprocessor
(Diagram 2)
DVIO Board: FIFO & Control
(Diagram 3)
DVIO Board: DVCODEC
(Diagram 4)
DVIO Board: A/V Output
(Diagram 5)
Digital Board: VSM Buffer Mem. (Diagram 1)
Digital Board: AV Dec. STI5508 (Diagram 2)
Digital Board: AV Decoder Mem. (Diagram 3)
Digital Board: Video Enc. Empress(Diagram 4)
Digital Board: VIP CVBS Y/C
(Diagram 5)
Digital Board: Video In/Out
(Diagram 6)
Digital Board: Progressive Scan (Diagram 7)
Digital Board: Progressive Scan (Diagram 8)
Digital Board: Audio Clock
(Diagram 9)
8 Electrical Alignments
9 Circuit Descriptions and
List of Abbreviations
10 Spare Part List
118
119
119
120
129
130
131
132
133
134
139
140
141
142
143
144
145
146
147
157
160
322
327
121->
121->
121->
121->
129
135->
135->
135->
135->
135->
148->
148->
148->
148->
148->
148->
148->
148->
148->
©
Copyright 2002 Philips Consumer Electronics B.V. Eindhoven, The Netherlands.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.
Published by MT 0261 Service PaCE
Printed in the Netherlands
Subject to modification
EN 3122 785 11970
EN 2
1.
DVDR980-985 /0X1
Technical Specifications and Connection Facilities
1. Technical Specifications and Connection Facilities
1.1
General:
Mains voltage
Mains frequency
Power consumption mains
Power consumption standby
Power consumption low power
stand-by
1.2
1.2.1
1.2.7
Automatic Search Tuning
scanning time without antenna
stop level (vision carrier)
Maximum tuning error of a recalled
program
Maximum tuning error during
operation
: 220V-240V (198 264V AC) for Europe/
Asia
: 50 Hz - 60Hz
: 32 W
: <7W
1.2.3
Test equipment:Fluke 54200 TV Signal generator
Test streams:PAL BG Philips Standard test pattern
1.3
Analogue Inputs
System:
1.3.1
SCART 1 (Connected to TV)
1.2.4
: 45 MHz - 860 MHz
: -4 dB /±2 dB
Radio Interference:
: typ. 80 dBµV at 75Ω
Receiver:
PLL tuning with AFC for optimum reception
Frequency range:
: 45.25 MHz - 860 MHz
Sensitivity at 40 dB S/N
: ≥ 60dBµV at 75Ω
(video unweighted )
1.2.5
Video Performance:
Channel 25 / 503,25 MHz,
Test pattern: PAL BG PHILIPS standard test pattern,
RF Level 74 dBV
Measured on SCART 1
Frequency response:
: 1 MHz - 4.00 MHz ±
2 dB
Group delay ( 0.1 MHz - 4.4 MHz ) : 0 nsec ± 30 nsec
1.2.6
Audio Performance:
Audio Performance Analogue - HiFi:
Frequency response at SCART 1
(L+R) output:
: 40 Hz - 15 kHz / ± 1.5
dB
S/N according to DIN 45405, 7, 1967 :
and PHILIPS standard test pattern
video signal:
: -50 dB unweighted
Harmonic distortion ( 1 kHz, ± 25
kHz deviation ):
: 0.5 %
Audio Performance NICAM:
Frequency response at SCART
1(L+R) output:
: ± 62.5 kHz
: ± 100 kHz
Pin Signals:
1
- Audio R
1.8V RMS
2
- Audio R
3
- Audio L
1.8V RMS
4
- Audio GND
5
- Blue/Chroma
GND
6
- Audio L
7
- Blue out/
Chroma in
0.7Vpp ± 0.1V into 75 Ohm (*)
8
- Function
switch
<2V = TV
>4.5V / <7V = asp. ratio 16:9 DVD
>9.5V / <12V = asp. ratio 4:3 DVD
9
- Green GND
10 - P50 control
11 - Green
0.7Vpp ± 0.1V into 75 Ohm (*)
12 - Nc
13 - Red/Chroma
GND
14 - fast switch
GND
15 - Red out/
Chroma out
0.7Vpp ± 0.1V into 75 Ohm (*)
± 3dB 0.3Vpp Chroma (burst)
16 - fast switch
RGB/ CVBS
or Y <0.4V into 75 Ohm = CVBS
>1V / <3V into 75 Ohm = RGB
17 - Y/CVBS GND
OUT
18 - Y/CVBS GND
IN
19 - CVBS/Y
1Vpp ± 0.1V into 75 Ohm (*)
20 - CVBS/Y
21 - Shield
RF - Loop Through:
input voltage /3 tone method (+40
dB min)
2.5 min. PAL
75 V, 75
Tuning Principle
automatic B,G, I, DK and L/L’detection
manual selection in "STORE" mode
RF Tuner
Frequency range
Gain: (ANT IN - ANT OUT)
:
:
: <3W
PAL B/G, PAL D/K, SECAM L/L’, PAL I
1.2.2
Tuning
: 40 Hz - 15 kHz ± 1.5
dB
S/N according to DIN 45405, 7, 1967 :
and PHILIPS standard test pattern
video signal:
: -60 dB unweighted
Harmonic distortion (1 kHz):
: 0.1 %
1.3.2
,
,
,
,
,
,
,
,
SCART 2 (Connected to AUX)
Pin Signals:
1
-Audio R
1.8V RMS
2
-Audio R
3
-Audio L
1.8V RMS
4
-Audio GND
5
-Blue/Chroma
GND
6
-Audio L
7
-Blue in/
Chroma out ± 3dB 0.3Vpp Chroma (burst)
8
-Function
switch
9
-Green GND
10 -P50 control
,
,
,
Technical Specifications and Connection Facilities
11 -Green
12 -Nc
13 -Red/Chroma
GND
14 -fast switch
GND
15 -Red in/
Chroma in
16 -fast switch
RGB/ CVBS or
Y
17 -CVBS GND
OUT
18 -CVBS GND
IN
19 -CVBS/Y/RGB
sync
1Vpp ± 0.1V into 75 Ohm (*)
20 -CVBS/Y
21 -Shield
SNR C - AM
SNR C - PM
Bandwidth Y
,
,
1.4.3
,
1.5
Audio Performance
1.5.1
Cinch Output Rear
,
Output voltage 2 channel mode
Output voltage 5.1 channel Dolby
Channel unbalance (1kHz)
Crosstalk 1kHz
Crosstalk 20Hz-20kHz
Frequency response 20Hz- 20kHz
Signal to noise ratio
Dynamic range 1kHz
Dynamic range 20Hz-20kHz
Distortion and noise 1kHz
Distortion and noise20Hz-20kHz
Intermodulation distortion
Phase non linearity
Level non linearity
Mute (spin-up, pause, access)
Outband attenuation:
,
Audio/Video Front Input Connectors
Audio
Input voltage
Input impedance
: 2 Vrms
: >10kΩ
Video - Cinch
Input voltage
Input impedance
: 1 Vpp ± 0.1V
: 75 Ω
1.5.2
Video - YC (Hosiden)
Input voltage Y
Input impedance Y
Input voltage C
Input impedance C
1.3.4
1.3.5
Audio (EXT1)
Input voltage
Input impedance
: 2 Vrms
: >10k Ω
Video (EXT4)
Input voltage
Input impedance
: 1 Vpp ± 0.1V
: 75 Ω
YC Input Rear (Hosiden; EXT3)
GND
GND
Input
voltage Y 1Vpp ± 0.1V/ 75 Ω
Input
voltage C Burst 300 mVpp ± {x} dB/ 75 Ω
Digital Output
1.6.1
Coaxial
CDDA/ LPCM (incl MPEG1)
MPEG2, AC3 audio
DTS
1.6.2
: > -65 dB
: > -65 dB
: > -65 dB
: 5 MHz ± 1 dB
YC Output Rear (Hosiden ; EXT3)
SNR
: > -65 dB
: > -65 dB
: 5 MHz ± 1 dB
: > -65 dB on all output
: 5 MHz ± 1 dB
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
2Vrms ± 1.5dB
1.41Vrms ± 1.5dB
<0.85dB
>105dB
> 95dB
± 0.1dB max
>100 dB
>90dB
>88dB
>90dB
>80dB
>87dB
± 1ο max.
± 0.5dB max.
>100dB
> 50dB above 25kHz
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
2Vrms ± 1.5dB
1.41Vrms ± 1.5dB
<0.85dB
>105dB
> 95dB
± 0.1dB max
>100 dB
>90dB
>88dB
>90dB
>80dB
>87dB
± 1o max
± 0.5dB max
>100dB
> 50dB above 25kHz
: according IEC958
: according IEC1937
: according IEC1937,
amendment 1
Optical
identical to coaxial
CVBS Output Rear (EXT4)
SNR Luminance
SNR Chrominance AM
SNR Chrominance PM
Bandwidth Luminance
1.4.2
1.6
Video Performance
All outputs loaded with 75 Ohm
SNR measurements over full bandwidth without weighting.
1.4.1
!
!
: > -65 dB
EN 3
Scart Audio
Output voltage 2 channel mode
Output voltage 5.1 channel Dolby
Channel unbalance (1kHz)
Crosstalk 1kHz
Crosstalk 20Hz-20kHz
Frequency response 20Hz- 20kHz
Signal to noise ratio
Dynamic range 1kHz
Dynamic range 20Hz-20kHz
Distortion and noise 1kHz
Distortion and noise20Hz-20kHz
Intermodulation distortion
Phase non linearity
Level non linearity
Mute (spin-up, pause, access)
Outband attenuation:
Cinch Audio/Video Line Input Rear
1
2
3
4
1.4
: 1Vpp ± 0.1V
: 75 Ω
: burst 300 mVpp ± {x}
dB
: 75 Ω
1.
SCART (RGB)
SNR
Bandwidth
(*) for 100% white
1.3.3
DVDR980-985 /0X1
1.7
Digital Video Input (IEEE 1394)
1.7.1
Applicable Standards
Implementation according:
IEEE Std 1394-1995
IEC 61883 - Part 1
IEC 61883 - Part 2 SD-DVCR (02-01-1997)
EN 4
1.
DVDR980-985 /0X1
Technical Specifications and Connection Facilities
Specification of consumer use digital VCR’s using 6.3 mm
magnetic tape - dec.1994
Mechanical connection according:
Annex A of 61883-1
1.7.2
Audio Quality
Output voltage 2 channel mode
Channel unbalance (1kHz)
Crosstalk 1kHz
Crosstalk 20Hz-20kHz
Frequency response 20Hz- 12kHz
Signal to noise ratio
Dynamic range 1kHz
Dynamic range 20Hz-20kHz
Distortion and noise 1kHz
Distortion and noise 20Hz-20kHz
Intermodulation distortion
Phase non linearity
Level non linearity
Outband attenuation
1.8
:
:
:
:
:
:
:
:
:
:
:
:
:
:
2Vrms +/- 1.5dB
Tbd
> 85 dB
> 95 dB
+/- 1dB max
>95 dB
tbd
Tbd
>65dB
>65dB
>80dB
tbd
tbd
tbd
P50 System Control
Via SCART pin nr 10
1.9
Dimensions and Weight
Height of feet
Apparatus tray closed
Apparatus tray open
Weight without packaging
Weight accesoiries
: 12mm
: WxDxH :435 x 325 x
107
: WxDxH :435 x 465 x
107
: 5.67 Kg
: 1.675 Kg
1.10 Laser Output Power & Wavelength
1.10.1 DVD
Output power during reading
Output power during writing
Wavelength
: 0.8mW
: 20mW
: 660nm
1.10.2 CD
Output power
Wavelength
: 0.3mW
: 780nm
Safety Instructions, Warnings, Notes, and Service Hints
DVDR980-985 /0X1
2.
EN 5
2. Safety Instructions, Warnings, Notes, and Service Hints
2.1
Safety Instructions
2.2
Warnings
2.1.1
General Safety
2.2.1
General
Safety regulations require that during a repair:
• Connect the unit to the mains via an isolation transformer.
• Replace safety components, indicated by the symbol ,
only by components identical to the original ones. Any
other component substitution (other than original type) may
increase risk of fire or electrical shock hazard.
Safety regulations require that after a repair, you must return
the unit in its original condition. Pay, in particular, attention to
the following points:
• Route the wires/cables correctly, and fix them with the
mounted cable clamps.
• Check the insulation of the mains lead for external
damage.
• Check the electrical DC resistance between the mains plug
and the secondary side:
1. Unplug the mains cord, and connect a wire between
the two pins of the mains plug.
2. Set the mains switch to the 'on' position (keep the
mains cord unplugged!).
3. Measure the resistance value between the mains plug
and the front panel, controls, and chassis bottom.
4. Repair or correct unit when the resistance
measurement is less than 1 MΩ.
5. Verify this, before you return the unit to the customer/
user (ref. UL-standard no. 1492).
6. Switch the unit ‘off’, and remove the wire between the
two pins of the mains plug.
•
•
•
2.2.2
Laser
•
•
2.1.2
Laser Safety
•
This unit employs a laser. Only qualified service personnel may
remove the cover, or attempt to service this device (due to
possible eye injury).
Laser Device Unit
Type
: Semiconductor laser
GaAlAs
: 650 nm (DVD)
: 780 nm (VCD/CD)
: 20 mW
(DVD+RW writing)
: 0.8 mW
(DVD reading)
: 0.3 mW
(VCD/CD reading)
: 60 degree
Wavelength
Output Power
Beam divergence
All ICs and many other semiconductors are susceptible to
electrostatic discharges (ESD, "). Careless handling
during repair can reduce life drastically. Make sure that,
during repair, you are at the same potential as the mass of
the set by a wristband with resistance. Keep components
and tools at this same potential.
Available ESD protection equipment:
–
Complete kit ESD3 (small tablemat, wristband,
connection box, extension cable and earth cable) 4822
310 10671.
–
Wristband tester 4822 344 13999.
Be careful during measurements in the live voltage section.
The primary side of the power supply (pos. 1005), including
the heatsink, carries live mains voltage when you connect
the player to the mains (even when the player is 'off'!). It is
possible to touch copper tracks and/or components in this
unshielded primary area, when you service the player.
Service personnel must take precautions to prevent
touching this area or components in this area. A 'lightning
stroke' and a stripe-marked printing on the printed wiring
board, indicate the primary side of the power supply.
Never replace modules, or components, while the unit is
‘on’.
•
The use of optical instruments with this product, will
increase eye hazard.
Only qualified service personnel may remove the cover or
attempt to service this device, due to possible eye injury.
Repair handling should take place as much as possible
with a disc loaded inside the player.
Text below is placed inside the unit, on the laser cover
shield:
CAUTION VISIBLE AND INVISIBLE LASER RADIATI ON WHEN OPEN AVO ID EXPOSURE TO BEAM
ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING VED ÅBNING UNDGÅ UDSÆTTELSE FOR STRÅLING
!
ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING NÅR DEKSEL
ÅPNES UNNGÅ EKSPONERING FOR STRÅLEN
VARNING SYNLIG OCH OSYNLIG LASERSTRÅLNING NÄR DENNA DEL ÄR ÖPPNAD BETRAKTA EJ STRÅLEN
VARO! AVATT AESSA OLET ALTTIINA NÄKYVÄLLE JA NÄKYMÄTT ÖMÄLLE LASER SÄTEILYLLE. ÄLÄ KAT SO SÄT EESEEN
VORSICHT SICHTBARE UND UNSICHTBARE LASERSTRAHLUNG WENN ABDECKUNG GEÖFFNET NICHT DEM STRAHL AUSSETSEN
DANGER VISIBLE AND INVISIBLE LASER RADIATI ON WHEN OPEN AVO ID DIRECT EXPOSURE TO BEAM
AT TENTION RAYO NNEMENT LASER VISIBLE ET INVISIBLE EN CAS D'OUVERTURE EXPOSITION DANGEREUSE AU FAISCEAU
Figure 2-2
2.2.3
Notes
Dolby
Manufactered under licence from Dolby Laboratories. “Dolby”,
“Pro Logic” and the double-D symbol are trademarks of Dolby
Laboratories. Confidential Unpublished Works.
©1992-1997 Dolby Laboratories, Inc. All rights reserved.
Figure 2-3
Figure 2-1
Note: Use of controls or adjustments or performance of
procedure other than those specified herein, may result in
hazardous radiation exposure. Avoid direct exposure to beam.
Trusurround
TRUSURROUND, SRS and symbol (fig 2-4) are trademarks of
SRS Labs, Inc. TRUSURROUND technology is manufactured
under licence frm SRS labs, Inc.
Figure 2-4
EN 6
2.
DVDR980-985 /0X1
Safety Instructions, Warnings, Notes, and Service Hints
Video Plus
“Video Plus+” and “PlusCode” are registered trademarks of the
Gemstar Development Corporation. The “Video Plus+” system
is manufactored under licence from the Gemstar Development
Corporation.
Figure 2-5
Macrovision
This product incorporates copyright protection technology that
is protected by method claims of certain U.S. patents and other
intellectual property rights owned by Macrovision Corporation
and other rights owners.
Use of this copyright protection technology must be autorized
by Macrovision Corporation, and is intended for home and
other limited viewing uses only unless otherwise authorized by
Macrovision Corporation. Reverse engineering or disassembly
is prohibited.
English
Philips DVD
recorder
DVD Video
player
From now on you will enjoy full-length movies with true
cinema picture quality, and stereo or Multi-channel
sound (depending on the disc, and on your playback setup).You will find your recorder remarkably easy to use,
by way of the On-Screen Display on your TV and the
display on the DVD recorder, in combination with the
remote control.
With it, you will be able to record TV programmes or
to edit and archive your own camcorder recordings.
Superb digital picture and sound quality, quick access to
the tracks you have recorded and extensive playback
features contribute to a completely new video
experience.
l Place the recorder on a firm, flat surface.
l Keep away from domestic heating equipment and
direct sunlight.
l In a cabinet, allow about 2.5 cm (1 inch) of free
space all around the recorder for adequate
ventilation.
l The lense may cloud over when the DVD recorder
is suddenly moved from cold to warm surroundings.
Playing a CD/DVD is not possible then. Leave the
DVD recorder in a warm environment for two
hours before use, so the moisture can evaporate.
l The recorder should not be exposed to dripping or
splashing, no objects filled with liquids, such as vases,
should be placed on the recorder.
Placement
Keep the packaging materials; you may need them to
transport your recorder in the future.
If any item should be damaged or missing, please inform
your supplier without delay.
First check and identify the contents of your DVD
recorder package, as listed below:
- DVD recorder
- Remote Control Handset with separately-packed
batteries
- 2-core power cord
- SCART cable
- S-video cable
- Antenna (aerial) cable
- Audio cable
- Video cable
- DVD+RW disc
- User Manual
- Warranty card
Box contents
INTRODUCTION 7
Caution:
Do not mix old and new batteries. Never mix
different types of batteries (standard, alkaline,
etc.). This may reduce the lifetime of the
batteries.
l Open the battery compartment cover.
l Insert two 'AA' (LR-6) batteries as indicated inside
the battery compartment.
l Close the cover.
Loading the batteries
Remote control
Caution:
Do not use solvents such as benzine, thinner,
commercially available cleaners, or anti-static
spray intended for analogue discs.
Do not use commercially available cleaning discs
to clean the lens, as these discs may damage the
optical unit.
l When a disc becomes dirty, clean it with a cleaning
cloth. Wipe the disc from the centre out.
Some problems may occur because the disc inside the
recorder is dirty. To avoid these problems clean your
discs regularly, in the following way:
Cleaning discs
DVDR980-985 /0X1
3.
6 INTRODUCTION
DVD+R(W)
pre-recorded DVD
Your Philips DVD recorder is a recorder and player
for digital video discs, with a two-way compatibility
to the universal DVD-Video standard. This means that:
- existing pre-recorded DVD-Video discs can be
played on your Philips DVD recorder and
- recordings, made on your Philips DVD recorder, can
be played on most DVD-Video players and
DVD-ROM drives.
DVD recording is the next step in video technology.
DVD+ReWritable (DVD+RW) uses phase-change media,
the same technology that formed the basis for CDReWritable. A high-power laser is used to change the
reflectivity of the recording layer. This process can be
repeated more than a thousand times. DVD+Recordable
(DVD+R) uses discs based on an organic dye, a
technology pioneered with the successful CDRecordable format, to produce discs that keep your data
for a lifetime.
DVD (Digital Versatile Disc) is the new storage medium
that combines the convenience of the Compact Disc
with the latest advanced digital video technology.
DVD-Video uses state-of-the-art MPEG2 data
compression technology to register an entire movie on a
single 5-inch disc. DVD’s variable bitrate compression,
running at up to 9.8 Mbits/second, captures even the
most complex pictures in their original quality.
The crystal-clear digital pictures have a horizontal
resolution of over 500 lines, with 720 pixels (picture
elements) to each line. This resolution is more than
double that of VHS, superior to Laser Disc, and entirely
comparable with digital masters made in recording
studios.
DVD Video Recorder
English
3.
Introduction
Directions For Use
EN 7
Directions For Use
English
EXT 3
EXT 1
TO TV I/0
2
8 INSTALLATION
If your TV set is not equipped with a SCART connector,
you can connect the DVD recorder with the S-video
(Y/C) sockets.
EXT 4
EXT 2
AUX- I/0
TV
l Connect the bottom SCART connector (EXT 1) to
the TV set, using the SCART cable supplied (2) as
shown in the drawing. If your TV set is equipped
with EasyLink or Cinema Link, make sure you use
the correct SCART connector. For this refer to the
user manual of your TV set.
To obtain the highest possible picture and sound quality
from your TV set it is recommended to use the SCART
connector on both DVD recorder and TV set.
Connecting to a TV set
l Remove the antenna (aerial) cable plug from your
TV set and insert it into the antenna socket at the
back of the DVD recorder.
l Plug one end of the antenna (aerial) cable supplied (1)
into the TV socket on the DVD recorder and the other
end into the antenna input socket on your TV set.
EXT 3
EXT 1
TO TV I/0
EXT 4
EXT 3
EXT 1
TO TV I/0
EXT 2
AUX- I/0
TV
5
l Connect the Video (CVBS) output socket (yellow)
to the corresponding input socket on the TV set
using the video cable supplied (4).
l Connect the audio Left (white) and Right (red)
output sockets to the corresponding sockets on the
TV set using the audio cable supplied (5).
Video (CVBS) connection
If your TV set is not equipped with S-video sockets, then
connect the DVD recorder with the CVBS sockets to
your TV set.
EXT 4
EXT 2
AUX- I/0
5
EXT 4
4
EXT 3
3
EXT 1
TO TV I/0
EXT 2
AUX- I/0
TV
6
8
AMPLIFIER
7
Note:
If the audio type of the digital output does not match the
capabilities of your receiver, the receiver will produce a
strong, distorted sound. The audio type of the DVD disc in
play is displayed in the Status Window, when changing the
language. 6 Channel Digital Surround Sound via digital
connection can only be obtained if your receiver is equipped
with a Digital Multi-channel decoder.
If you do not own a digital coaxial audio cable (not
supplied), you may use the supplied video cable (4).
l Connect the recorder’s digital audio output to the
corresponding input on the receiver. Use a digital
coaxial cable (7) or a digital optical audio cable (8).
Digital Multi-channel sound
Digital Multi-channel connection provides the optimum
sound quality. For this you need a Multi-channel A/V
receiver that supports one or more of the audio types
supported by your DVD recorder (MPEG 2, Dolby
Digital and DTS). For this you can check the receiver
manual and the logos on the front of the receiver.
EXT 3
EXT 1
TO TV I/0
INSTALLATION 9
l If you have a receiver with two-channel analogue
stereo without any of the above mentioned sound
systems, connect the audio Left and Right output
sockets to the corresponding sockets on your
receiver, amplifier or stereo system. Use the audio
cable supplied (6).
Connecting to a receiver with two channel
analogue stereo
l Connect the recorder to the TV set as described in
chapter ‘Connecting to a TV set’.
Connecting to a TV set equipped with a
Dolby Pro Logic decoder
l Make the appropriate Sound settings for Analogue
Output in the user preferences menu.
EXT 4
EXT 2
AUX- I/0
6
AMPLIFIER
l Connect the recorder to the TV set and connect the
recorder’s audio Left and Right output sockets to the
corresponding inputs on the Dolby Pro Logic
Audio/Video receiver, using the audio cable supplied (6).
Connecting to a receiver equipped with
Dolby Pro Logic
l Connect the recorder’s digital audio output to the
corresponding input on your receiver. Use the
supplied video (CVBS) cable (7) or an optional
digital optical audio cable (8).
l After installation you will need to activate PCM on
the DVD recorder’s digital output (see ‘User
Preferences’).
Connecting to a receiver equipped with
two channel digital stereo (PCM)
If you cannot connect your DVD recorder to an A/V
receiver with Multi-channel decoder, choose one of the
following alternatives.
DVDR980-985 /0X1
Connecting to the antenna
Caution:
Do not connect the recorder’s audio output to
the phono input of your audio system in order to
avoid damage to your equipment.
TV
Connecting to A/V receiver or A/V
amplifier with digital Multi-channel
decoder
l Connect the S-video output socket to the
corresponding input socket on the TV set, using the
supplied S-video cable (3).
l Connect the audio Left (white) and Right (red)
output sockets to the corresponding sockets on the
TV set using the audio cable supplied (5).
The best possible sound quality is obtained by
connecting your DVD recorder to an A/V receiver with
Multi-channel decoder (Dolby Digital, MPEG 2 and DTS).
Connecting to audio equipment
S-video (Y/C) connection
3.
- Please refer to your TV set, VCR, Stereo System and
any other User Manual(s) as necessary to make the
optimal connections.
- Do not connect the power until all other connections
are made.
- Do not connect your DVD recorder to your TV set
via your VCR, because the video quality could be
distorted by the copy protection system.
- For better sound reproduction you can connect the
recorder audio outputs to your amplifier, receiver,
stereo system or A/V equipment. For this see
‘Connecting to A/V receiver or A/V amplifier’.
Connections - back side of your
DVD recorder
Installation
EN 8
Directions For Use
English
English
EXT 4
4
EXT 1
TO TV I/0
EXT 2
AUX- I/0
2
Set top box
EXT 3
3
5
S-VIDEO
VIDEO
L AUDIO R
1
Camcorder
2
3
l If you have a DV, Digital 8, Hi-8 or S-VHS(C)
camcorder, connect the S-video input socket to the
corresponding output socket on the camcorder,
using the S-video cable supplied (1) and connect the
audio cable (3) supplied.
l Otherwise connect the Video input socket (yellow)
to the corresponding output socket on the
camcorder using the video cable supplied (2) and
connect the audio Left (white) and Right (red) input
sockets to the corresponding sockets on the
camcorder using the audio cable supplied (3).
l If your camcorder has mono sound, use only the left
audio connector. In this case the sound will be
recorded on both audio channels.
Camcorder connection
Connections - frontside of your
DVD recorder
l Switch on the TV set and select the programme
number that you have chosen for video playback
(see operating manual for your TV set).
l Press B STANDBY/ON.
‰ The recorder display lights up. If you have not yet
installed your DVD recorder, it will enter ‘virgin
mode’. In this mode you will have to set your
personal preferences.
Switching on
Note:
Always check if the local mains voltage matches the required
220V - 240V.
When the recorder is in the Standby position, it is still
consuming some power.
If you wish to disconnect your DVD recorder completely from
the mains, withdraw the plug from the AC Outlet.
When the DVD recorder is disconnected from the mains, TV
channels and timer data will be stored typically 1 year.
l Make sure that all necessary connections are made
before connecting the DVD recorder to the power
supply.
l Plug the power cable supplied into the Power
connector on the rear of the recorder.
l Plug the mains plug into an AC outlet.
Power supply
TM
TM
TM
TM
TM
INSTALLATION 11
Easy Link
loading data from TV please wait
Follow TV
Note:
Preferences have to be set in the order in which the item
menus will appear on the screen.
If the recorder is switched off while setting user preferences,
all preferences have to be set again after switching the
recorder on again.
The ‘virgin mode’ will only be concluded after the
preferences for the last item have been confirmed.
When preferences are taken over from your TV set, the
message ‘Easy Link loading data from TV-please
wait’ will appear.
Menus for which no preferences are available will be
displayed. They have to be set manually.
TM
When your TV set is equipped with EasyLink , Cinema
Link , NEXTVIEW Link , SmartLink , Q-Link or
MegaLogic , the TV settings will be taken over from the
TV set but they cannot be changed manually afterwards.
Automatic setting
If the ‘virgin mode screen’ does not appear, your DVD
recorder has been installed already. You may still change
the settings via the ‘installation menu’.
Depending on the kind of TV set, preferences will have
to be set manually or they will be taken over
automatically from the TV set.
In ‘virgin mode’ you may have to set your preferences
for some of the recorder features.
After switching on the DVD recorder for the very first
time the ‘virgin mode screen’ will appear.
First time set-up: virgin mode
DVDR980-985 /0X1
3.
10 INSTALLATION
Notes:
- If the power is off or Low Power Standby is selected (see
User Preferences - features), the signal from EXT 2 will not
be passed on to the TV set on EXT 1.
- EasyLink functionality will not be available to devices
connected via the DVD recorder’s EXT 2 SCART connector.
1
TV
For installation of a decoder, see ‘User Preferences’ ‘Installation’.
- Satellite receiver or Set top box,
- VCR,
- DVD-Video player
Most pre-recorded video cassettes and DVD discs are
copy protected. If you try to copy them the display
shows ‘COPY PROTECT’.
Use the top SCART connector (EXT 2) on your DVD
recorder to make connections to a:
Connecting to other equipment
Directions For Use
EN 9
English
English
12 INSTALLATION
Press OK to continue
Italiano
Português
Français
Español
English
Subtitle language
Virgin mode
Subtitle language
The subtitles of DVD-Video discs will be in the language
you choose provided this is available on the disc in play. If
not, subtitles will revert to the first subtitle language on
the disc.
Press OK to continue
Italiano
Português
Français
Español
English
Audio language
Virgin mode
Audio language
The sound of DVD-Video discs will be in the language
you choose, provided this is available on the disc in play.
If not, speech will revert to the first spoken language on
the disc. Also the DVD-Video disc menu will be in the
language you choose, provided this is available on the disc.
Press OK to continue
Deutsch
Italiano
Français
You can choose:
- 16:9 if you have a wide screen (16:9) TV set.
- 4:3 if you have a regular (4:3) TV set. In this case you
can also choose between:
- Letterbox for a ‘wide-screen’ picture with black
bars at the top and bottom,
- Pan Scan, for a full-height picture with the sides
trimmed. If a disc has Pan Scan, the picture then
moves (pans) horizontally to keep the main action
on the screen.
Press OK to continue
Virgin mode
After Auto channel search you can have TV channels
stored automatically in the same order as your TV set.
See ‘User preferences installation’ - ‘Follow TV’.
‰ When Auto search is completed ‘Autom.
search complete - XX channels found’ appears
on the TV screen.
Please wait
XX c h a n n e l s f o u n d
Searching for TV channels
Autom.search
Auto TV Channel Search
Make sure the antenna is connected. See ‘Connecting to
the antenna’. Your DVD recorder will search for all TV
channels.
It stores channels in the sequence they are found.
l Confirm with OK.
‰ Auto search starts. This can take several minutes.
Press OK to continue
France
Finland
Denmark
Belgium
Austria
Country
Country
Select your country. This is used as input for the
‘Parental Control’ feature (see ‘Access Control’) as well
as the searching of TV channels.
To continue
Press OK
09: 40
2001
02
09
INSTALLATION 13
Virgin mode settings are now completed.
All settings can still be changed. See ‘User preferences’.
Note:
All these items may have to be set after first start up (‘virgin
mode’). After that they can always be adapted in the user
preferences menu. When your TV set is equipped with
EasyLink the TV set presets will be taken over from the TV
set but they cannot be changed manually afterwards.
l Adjust ’Time’, ’Year’, ’Month’, ’Date’ if required,
with the w (down cursor) or v (up cursor) key.
l Change values with the the t (left cursor) or u
(right cursor) key or the digit keys 0-9.
l To end, press OK.
Time
Year
Month
Date
Autom.search
Autom.search complete
XX c h a n n e l s f o u n d
Time/Date
When Channel auto search is completed the actual Time
and Date are also set automatically.
If the time in the DVD recorder display is not correct,
the clock must be set manually.
DVDR980-985 /0X1
Español
English
Menu language
Virgin mode
Menu language
The on-screen menus of DVD-Video discs will be
displayed in the language you choose.
16:9
4:3 panscan
4:3 letterbox
TV Shape
Virgin mode
TV Shape
3.
The following items may have to be set in virgin mode:
When a menu is displayed:
l Use the wv (down up cursor) keys to go through
the options in the menu. The icon of the selected
option will be highlighted.
l Use OK to confirm your selection and to select the
next menu.
Manual setting
English
EN 10
Directions For Use
English
VIDEO
L AUDIO R
Disc loading tray
S-VIDEO
- Video input socket to connect a
camcorder or video recorder
VIDEO (CVBS)
- Video input socket to connect a
camcorder or video recorder
AUDIO (Left/Right)
- Audio input socket left/right to
connect a camcorder or video
recorder
DIGITAL
MANUAL
- 3 4 to increase/decrease
the recording level
AUTO/MAN REC VOLUME
- to adjust the recording level
automatically or manually
/ OPEN/CLOSE
- opens/closes the disc tray
0 RECORD
- direct recording of the selected programme
on TV or the recorder (depending on the
DIRECT RECORD setting)
2 PLAY
- starts video/audio play
9 STOP
- stops video/audio play or recording
CHANNEL
- to select channels manually
Display
- displays the current status of the recorder
MONITOR
- switches between disc mode and monitor mode
Infrared remote control receiver
Standby indicator
- lights up red when the recorder is in standby mode
- lights up green when the recorder is operative
B STANDBY/ON
- switches the recorder to power/standby mode
EXT 4
EXT 1
TO TV I/0
TO TV I/O (EXT I)
- for connection to a TV with SCART
EXT 3
EXT 2
AUX- I/0
OUT COAX
- connection to an amplifier, receiver or stereo system
with a digital (coaxial) audio input
OUT OPTICAL
- connection to an amplifier, receiver or stereo system
with a digital (optical) audio input
FUNCTIONAL OVERVIEW 15
AUX I/O (EXT II)
- for connection to a satellite receiver, decoder, video recorder, set top box
etc. via SCART
S-video (Y/C)
- OUT: for connection to a TV, receiver or amplifier with S-video (Y/C) inputs
- IN: for connecting a video source with S-video (Y/C) outputs
Video (CVBS)
- OUT: for connection to a TV, receiver or amplifier with CVBS video inputs
- IN: for connecting a video source with CVBS outputs
ANTENNA
- RF connection to antenna/cable TV signal
TV
- RF connection to TV set
MAINS
- connection to the mains
AUDIO OUT L/R
- connection to an amplifier, receiver, stereo system or
to a TV that is not equipped with a SCART connector
AUDIO IN L/R
- connection to the audio output of a video source that
is not equipped with a SCART connector
Apparatus Claims of U. S. Patent Nos.
4,631,603, 4,577,216, 4,819,098, and 4,907,093
licensed for limited viewing uses only.
Rear of recorder
DVDR980-985 /0X1
3.
14 FUNCTIONAL OVERVIEW
S-VIDEO
Front of recorder
Functional overview
Directions For Use
EN 11
English
English
MPEG
-30
SA V CD
DIGITAL - DTS - MPEG - PCM
16 FUNCTIONAL OVERVIEW
- Active audio format
-10
PCM
0
OVER
-40
-30
SAT
-20
TIMER
REMAIN
-10
SAT
NICAM
Disc bar
- Displays disc content, recording level or
formatting progress
dB scale
- indicates recording volume when using
manual level control
- Stereo sound from tuner
STEREO
- NICAM digital stereo sound on current
preset
NICAM
STEREO
RECORD
0
CHANNEL
OVER
DECODER
VPS/PDC
- Remote control active (flashing)
- Total remaining playback or recording time
in hours, minutes and seconds
TOTAL REMAIN
- Total playback or recording time in hours,
minutes and seconds
TOTAL TRACK TIME
MANUAL
TRACK TIME
TOTAL TIME
- Track time in minutes and seconds
- Recorder prepared for or engaged in satellite
recording
DIGITAL DTS
-20
HQ SP LP EP+
CHAPTER
- Manual recording level control
MANUAL
RW
DVD
-40
TRACK
TITLE
- DVD chapter number
CHAPTER
- Selected recording mode: High Quality,
Standard Play, Long Play or Extended Play
HQ - SP - LP - EP
- Super Video CD inserted
SVCD
- Audio CD inserted
- Timer programmed or active
TIMER
- Recording in progress
RECORD
- Preset name or number
CHANNEL
- Video Programming System/Programme
Delivery Control active on current preset
VPS/PDC
- Decoder activated for current preset
a ZOOM
- enlarge video image
ANGLE
- select DVD camera angle
Z SUBTITLE
- subtitle language selector
Y AUDIO
- audio language selector
VOL +/–
- TV volume up/down
c
- TV Mute ON/OFF
CH +/–
- programme up/down
J
- previous chapter, track or title
0
- direct recording of the currently
selected programme
K
- next chapter, track or title
Q
- search backward
;
- pause
H
- slow motion
R
- search forward
9
- stop
FSS
- displays Favorite Scene Selection
menu for DVD+RW or DVD+R
disc
2
- play
MONITOR
- switches between disc mode and
monitor mode
Remote control
REPEAT
SCAN
Y
AUDIO
A/CH
CH
PLAY
FORWARD
NEXT
ON/OFF
SELECT
SUBTITLE
DIM
REPEAT
ANGLE
MUTE
TIMER
FSS
SLOW
Z
CLEAR
PAUSE
REC/OTR
a
ZOOM
T/C
VOL
STOP
REVERSE
PREVIOUS
MONITOR
FUNCTIONAL OVERVIEW 17
DIM
- changes brightness setting of
display
REPEAT
- repeat chapter, track, title, disc
REPEAT A-B
- repeat sequence
SCAN
- playback of the first 10 seconds
of each chapter within a title
(DVD) or the first 10 seconds of
each track on a disc (VCD/CD)
SIDE SWITCH
- enables other keys to operate
the TV set (see Appendix)
0-9
- numerical key pad
T/C
- select title
- select chapter
A/CH Alternate Channel
- switches to the previous TV
channel
DISC MENU
- displays DVD disc menu or index
picture screen
SYSTEM MENU
- displays recorder system menu
bar
w v u t
- down/up/right/left cursor
movement
RETURN
- return to previous menu on
(S)VCD disc
CLEAR
- delete last entry/clear timer
TIMER
- displays the ‘timer menu’
SELECT
- switches between different values
in a menu
- switches between record modes
in the Index Picture Screen and in
monitor mode
OK
- acknowledge menu selection
ON/OFF B
DVDR980-985 /0X1
CD
- Video CD inserted
VCD
- VCD/CD track number
TRACK
- DVD title number
TITLE
- DVD+Rewritable disc inserted
DVD+RW
- DVD+Recordable disc inserted
DVD+R
- DVD Video disc inserted
DECODER
3.
DVD
Display
English
EN 12
Directions For Use
English
REC/OTR
PAUSE
SLOW
FORWARD
NEXT
ON/OFF
Press / OPEN/CLOSE on the front of the
recorder. The disc loading tray opens.
Lay your chosen disc in the tray, label side up.
Make sure it is sitting properly in the correct recess.
Press / Open/Close, to close the tray.
‰ ‘READING’ appears in the status box and on the
recorder display. If the inserted disc is pre-recorded
or write-protected, playback always starts
automatically.
DVD-R
Only plays if it contains DVD-Video.
DVD-Video
The following disc type can be used for
playback only:
DVD+R
Records and plays.
DVD+RW
Records and plays; In case of a new blank disc, after the
first recording, some more time (up to two minutes) is
needed to make the disc compatible with DVD-Video
players.
ReWritable
DVD-Audio
DVD-RAM
The following disc types cannot be used at
all, neither for recording nor for playback:
Recordable
CD-R/CD-RW
Plays if it contains Audio CD.
(Super) Video CD
Depending on the material on the disc (a movie, video
clips, a drama series, etc.) these discs may have one or
more tracks, and tracks may have one or more indexes,
as indicated on the disc case. To make access easy and
convenient, your recorder lets you move between
tracks, and between indexes.
Super Audio CD
Of hybrid SACD discs, the CD layer can be played.
CD Digital Audio
You can play digital audio CDs in conventional style
through a stereo system, using the keys on the remote
control and/or front panel, or via the TV set using the
on-screen display (OSD).
R W
DVD-RW
Only plays if it is recorded in Video mode and has been
finalized.
Y
SCAN
Sound
Time search
Audio language
Subtitle language
3.
OPERATION 19
The system menu bar contains a ‘Temporary Feedback
Field’ with information concerning prohibited actions,
playback modes, available angles, etc.
Temporary Feedback Field
Zoom
Angle
Slow motion
Fast motion
Chapter/Index
Step motion
User preference
Title/Track
PART 2
PART 1
System menu bar icons
Widescreen (16:9) TV sets may show only part of the
system menu bar in certain screen modes. Select a
different screen mode on the TV to see the full menu.
A number of recorder functions can be controlled via
the system menu bar. You can navigate between the two
parts of the system menu bar with the t (left cursor)
and the u (right cursor) key.
Z
REPEAT
REPEAT
a
DIM
A/CH
AUDIO
SUBTITLE
T/C
ZOOM
ANGLE
The system menu bar can be called up by pressing any of
the following keys on the remote control: SYSTEM
MENU, T/C,
ANGLE, Z SUBTITLE, Y
AUDIO and a ZOOM.
System menu bar
On-screen display information
DVDR980-985 /0X1
18 OPERATION
Note:
If ‘Child Lock’ is set to ON and the disc inserted is not in the
‘child safe’ list (not authorized), the PIN code must be entered
and/or the disc has to be authorized. (see ‘Access Control’)
You can always unload a disc by pressing
/ OPEN/CLOSE again or pressing 9 STOP on the
remote control for two seconds.
3
2
1
Loading discs
When you switch off the DVD recorder, the display will
briefly show ‘WAIT’.
REVERSE
PREVIOUS
MONITOR
Both the DVD recorder and the remote control have an
’Emergency interrupt’ button. You can use the
B STANDBY/ON button to interrupt a function.
When you have an operating problem, you can interrupt
the function and start again.
You will recognize the different types of discs, that can
be used in your DVD recorder by the logo. Depending
on the disc type you can either use it for recording and
playback or playback only. Some discs are not suitable at
all to be used in the DVD recorder.
In the next table a summary is given of all excisting disc
types and their DVD recorder compatibility.
You can switch on the DVD recorder with the
B STANDBY/ON key. Keep your DVD recorder
connected to the mains at all times to ensure that
programmed recordings can be made and that the
television functions normally.
The following disc types can be used for
recording and playback:
Disc types
Important notes for operation
Operation
Directions For Use
EN 13
English
English
20 OPERATION
Installation
Record settings
Remote control settings
Feature settings
Language settings
Sound settings
Picture settings
User preference menu icons
The following functions can be operated via the user
preference menu.
l Press SYSTEM MENU on the remote control.
l Select
in the system menu bar and press w
(down cursor).
‰ The user preferences menu appears.
l Use the t u v w (left right up down cursor) keys
to toggle through the menus, sub menus and
submenu options.
‰ When a menu item is selected, the cursor keys
(on the remote control) to operate the item are
displayed next to the item.
l Press OK to confirm and return to the main menu.
User preference menu operation
Action prohibited
Resume
off
on
off
The status box on the left hand side of the screen
displays the current status of the recorder and the disc
type loaded for several seconds.
Status box
l By pressing SYSTEM MENU the system menu bar
will disappear from the screen.
---
stop
playing
pause play
play
pause
slow motion
fast reverse
fast forward
erasing
12 BBC1
12BBC1
Copy-protected signal
No signal
Current channel
The tuner info box is located at the bottom left of the
screen and is displayed in monitor mode (See: Recording
Checking input). It displays the currently selected input.
When the tuner is selected it shows programme number
and/or channel name.
Tuner info box
slow
H
8x
Q
8x
R
erasing
0
pause
0 ;
;
2
record pause
recording
stop
9
rec
0
Disc status icons
Timer event due on another day
Timer event due today
OTR recording in progress
10: 13 hr
Disc locked
OPERATION 21
The warning box will be displayed near the bottom of
the screen when appropriate. For instance: ‘Disc locked’.
Warning box
Note:
Tuner info box and timer info box disappear during playback
and after recording is started.
Current time
When no timer is programmed it displays the current
time.
10: 15hr
When an OTR recording is in progress it shows the end
time.
10: 13hr
When a timer is programmed it shows a timer indication
and the start time or date of the first programmed
recording.
The timer info box is located above the tuner info box
and is displayed in monitor mode. It displays the current
status of the timer.
Timer info box
DVDR980-985 /0X1
Child Safe
Child Lock On
Angle
--
Super Video-CD
DVD-Video
disc error
off
no disc
on
Repeat A-B
off
Video-CD
---
DVD+R
Repeat A to end
--
DVD+R
DVD+RW
Disc type icons
Repeat Chapter
Repeat Track
Repeat Title
l You can navigate between the various items of the
user preferences menu with the v (up cursor) and
the w (down cursor) key. To select an item press u
(right cursor) key.
3.
Repeat All
Scan
English
EN 14
Directions For Use
English
Timer Info Box
- displays the current time or time/date
of the next timer programme
Tuner Info Box
- displays the selected channel
Disc Bar
- shows an overview of
all titles on disc
Empty title.
00:00:59SP
V R T 11: 13.
00:00:57 SP.
T h u 08 02 2001
2
Black level shift (NTSC only)
Adapts the colour dynamics to obtain richer contrasts.
Select ‘On’ or ‘Off’.
TV Shape
With TV Shape you can adjust the output of your DVD
Recorder to optimally fit your TV screen. You can
choose:
- 16:9 if you have a wide screen (16:9) TV set.
- 4:3 if you have a regular (4:3) TV set. In this case you
can also choose between:
- Letterbox: for a ‘wide-screen’ picture with black
bars at the top and bottom,
- Pan Scan: for a full-height picture with the sides
trimmed. If a disc has Pan Scan, the picture then
moves (pans) horizontally to keep the main action
on the screen.
Picture settings
The following items can be adapted:
You can set your user preferences for some of the
recorder features. (See ‘Operation’ - ‘User preferences
menu operation’)
Setting user preferences
User preferences
---
off
OK to exit
on
off
Sound settings
---
3D sound
Surround
Stereo
off
on
off
Sound
3.
OPERATION 23
Select ‘Stereo’, ‘Surround’ or ‘3D Sound’. Factory
setting is Stereo.
Night mode
Analogue output
Digital output
--
Analogue output
Digital output
Factory setting ‘All’ means that both coaxial and optical
outputs are switched on, and that Dolby Digital Multichannel is fed to the outputs as such MPEG audio is
converted to PCM. If your equipment doesn’t include a
digital Multi-channel decoder, set the digital output to
‘PCM only’ (Pulse Code Modulation). Both coaxial and
optical outputs are then switched on, and Dolby Digital
and MPEG audio are converted to PCM. If you are not
connecting equipment with a digital input, change the
setting to ‘Off’.
SCART
Picture
SCART Video
Factory setting is RGB. Select ‘S-video’ (Y/C) via
when connecting to an S-VHS recorder.
SCART video
Video shift
Black Level shift
TV shape
--
Video shift
Factory setting is such that the video will be centered on
your screen. Use this setting to adjust the position of
the picture on your TV set by scrolling it to the left or
right.
DVDR980-985 /0X1
22 OPERATION
4
Cue to go to title on next screen
01 Z D F
1:15 hr
Cue to go to Disc Info Screen
or to title on previous screen
Z D F 11: 11.
00:00:55 SP.
T h u 08 02 2001
Disc Pointer
- shows number and place
of current title on disc
Other title
Indication what disc area
will be overwritten by
upcoming timer event
Current title
Empty title
l On the right hand side of the Index Picture Screen,
you can see the disc bar. This gives an overview of
all titles on the disc, as well as any empty spaces.
On the disc bar, an arrow – the disc pointer –
indicates your current position on the disc. From
this point you may resume playback or recording.
l If you navigate trough the list of titles with w v
(down up cursor) or J PREVIOUS / K NEXT, the
disc pointer will move along.
l Press 9 STOP to reset the disc pointer to the
beginning of the disc.
l To move the disc pointer to the end of the last title,
keep K NEXT pressed.
l If you navigate from an Index Picture to the box
right next to it (containing name, rec mode, etc.),
you enter the title settings menu (see under
‘Managing disc content - Title settings’).
Title description
- programme name
- duration + recording mode
- recording date
Index Picture
- image that represents a recorded title
The Index Picture Screen displays an overview of the
titles recorded on the disc. Each title is represented by
an index picture. Next to the index picture the
programme name, duration, recording mode and
recording date of the title are shown. If no name is
known, the DVD recorder will fill in the source and the
time of the recording instead.
Empty spaces (erased titles, or blank space at the end of
the disc) are also shown as such.
l At maximum three titles will be shown on the
screen at once. If more titles are present, you can
navigate to those with the w v (down up cursor)
keys.
Index Picture Screen
Directions For Use
EN 15
English
English
Off
Amplifier or TV with two channel
analogue stereo
Stereo
Amplifier with two channel digital
stereo
Surround
Multi-channel A/V receiver with
6-ch connectors
24 OPERATION
Access Control
Access Control contains the following features:
Child Lock - When Child Lock is set on, a 4-digit code
needs to be entered in order to play discs.
Parental Level - Allows the conditional presentation of
DVD discs containing Parental Level information.
Change country - Allows conditional presentation of
DVD-Video discs containing country information.
Change code - To change the pin code.
See ‘Acces Control’.
Feature settings
The preferred language can be adapted via the system
menu bar. Also see ‘virgin mode’. Settings can be
changed for:
- Playback audio language
- Subtitle language
- Menu language
- Country setting.
r Language settings
Night Mode
Night mode optimizes the dynamics of the sound with
low volume playback for less disturbance in quiet
environments. This only works for Dolby Digital audio
on DVD-Video discs.
Off
Stereo or
Surround
A/V receiver with Multi-channel
All
decoder (Dolby Digital, MPEG, DTS)
PCM only
Surround
On
Off
Off
Off
Status box
Autoresume
Low power standby
PBC
off
Enter code...
---
Access control
--
on
Features
off
Notes:
When the recorder is in low power standby mode:
- the output of the equipment connected to EXT 2 will not
be passed through to the TV set on EXT 1,
- the Display will be Off,
- the Standby indicator on the recorder will still light up in
standby mode.
Low power standby
If low power standby is ‘On’, the recorder will consume
minimum power in standby mode.
Factory setting is ‘Off’.
Auto resume
The Auto resume setting only applies to pre-recorded
DVD-video and Video CD discs only - not only to the
disc in the recorder but also to the last twenty discs you
have played.
If ‘Auto resume’ is set to ‘On’, playback will start from
the point where it was stopped the last time the disc
was played.
When ‘Auto resume’ is set to ‘Off’, the recorder will
start playing from the beginning of a disc. In this case you
can still resume when
appears on screen by
pressing 2 PLAY. Factory setting is ‘On’.
Status box
The status box displays the current status of the recorder
and the disc type loaded (See ‘Operation’ - ‘On-screen
display information’). You can switch it On or Off.
Off = always Off.
On = displayed together with the system menu bar or
displayed temporarily (disappears after time-out)
when changing the playback or record status.
Factory setting is ‘On’.
System information
When you move further down in the Remote Control
settings menu, the system status screen will appear.
Press v (cursor up) to go back.
Remote control used
If you want to use the remote control of a Philips DVD
player instead of the standard DVD recorder remote
control, select ‘DVD player’. Factory setting is ‘DVD
recorder’.
Key sound
The recorder makes a ‘beep’ sound upon every key
command given via recorder or remote control keys.
Select ‘Off’ to disable this sound. Factory setting is ‘On’.
Remote Control settings
Finalise disc
This option is only available on unfinalised DVD+R discs.
See ‘Managing disc content - Finalising a DVD+R disc’.
PBC
This feature is only available when a (Super) Video CD is
loaded. It allows you to disable or enable the PBC
(Playback Control) menu of VCD discs. See under
‘Special VCD features’: Factory settings is ‘On’.
pre-recorded
DVD quality
better than
S-VHS picture quality
SP
(Standard Play)
LP
(Long Play)
240 minutes
180 minutes
120 minutes
60 minutes
Total recording
time
To exit press
SYSTEM MENU
SP
Off
Off
On
Stndrd
OPERATION 25
It is not possible to switch record modes during
recording.
Record Mode: LP
An alternative way to select the record mode is available
in the Index Picture Screen and in monitor mode:
l Press SELECT.
‰ The new record mode appears on the screen and
the display.
l Alter the recording mode with t or u (left right
cursor).
l Confirm with the OK key.
l To end, press SYSTEM MENU.
Record mode
Direct record
Sat record
Auto chapters
LP/EP rec mode
Record settings
In practice, the DVD recorder may record a few
minutes more than indicated. For playback, the correct
recording mode will automatically be selected.
The HQ mode is optimised for recording via the
external inputs. For tuner recordings it is recommended
to use SP, LP or EP.
l In the record settings menu, select ‘Record mode’.
better than
VHS picture quality
best possible
picture quality
HQ
(High Quality)
EP
(Extended Play)
Picture quality
Mode
Record mode
By selecting a recording mode you define picture quality
of recordings and maximum recording time for a disc.
Record Settings
DVDR980-985 /0X1
Amplifier or TV with Dolby Surround Off
or Dolby Pro Logic
Stereo
Digital out Analogue out
Adapt disc format
This option is only available when a DVD+RW or
DVD+R disc recorded on a different brand of recorder
is loaded. You can adapt the menu to your own
recorder.
A DVD+RW video disc that has been recorded on a
different type or brand of recorder can be played, but
may not provide all features commonly available to
DVD+RW discs, such as the on-screen disc bar, the disc
settings menu, the title settings menu, and editing. If the
disc is not write-protected, the disc format can be
adapted to the own recorder, after which these
functions are available.
3.
Connected audio system
Surround: Select this setting when using equipment
with a Dolby Surround Pro Logic decoder.
In this setting the 5.1 audio channels (Dolby
Digital, MPEG-2) are downmixed to a
Surround-compatible 2-channel output.
3D Sound: In a set-up without rear speakers (analogue
stereo output), this option remixes the six
channels of digital surround (Dolby Digital,
MPEG-2) into a two speaker output, while
retaining all of the original audio information.
The result is the listening sensation of being
surrounded by multiple speakers.
English
EN 16
Directions For Use
English
l
l
l
l
‰ When ‘NOTV’ (no signal from TV set) appears on
the display, the TV channels can not be allocated
automatically. In this case read ‘Manual TV channel
search’.
Select programme number ‘1’ on the TV set.
Confirm with OK on the remote control of the
DVD recorder.
‰ The DVD recorder compares the TV channels on
the TV set and the DVD recorder. If the channels
match, this channel is stored at ‘P01’.
Wait until 'TV02’ appears and repeat the previous
two steps for programme number 2 and the rest of
the channels you want to store.
To end, press SYSTEM MENU.
TV 01
l Press OK.
‰ If the DVD recorder recognizes that the TV set
has been connected with a SCART cable, ‘TV01’
appears on the display.
To exit press
SYSTEM MENU
Autom.search
Follow TV
Manual search
Sort TV channels
Time Date
Installation
Follow TV
With Follow TV you can programme the same channel
sequence on the DVD recorder as on the TV set.
This only functions if the recorder socket (EXT1) and
the TV set are connected with a SCART cable. Additional
equipment connected to socket EXT2 must be switched
off.
Note:
All channels stored so far will be erased.
Auto TV Channel Search
Your DVD recorder will search for all TV channels.
It stores channels in the sequence they are found. (See
‘Installation - First time Set-up’)
Installation
Connecting a decoder:
l Switch on the TV set and select the programme
number for the DVD recorder.
l Select the TV programme you wish to link with the
decoder function with CH+ or CH-.
l Press SYSTEM MENU
l Select ‘Installation’.
l Select ‘Manual search’.
l Select ‘Decoder’.
l Select ‘On’ with t (left cursor) or u (right cursor).
l Confirm with OK.
‰ ‘DECODER’ apperars on the display.
l To end, press SYSTEM MENU.
l Press OK to store the TV channel.
l To end, press SYSTEM MENU.
Important: This re-tuning is only necessary and useful
in special cases, e.g. when stripes appear on your TV
screen when using a cable-TV system.
l In the line ‘NICAM’ select ‘On’ or ‘Off’ with the t
(left cursor) or u (right cursor) key.
If you want to change the automatic TV channel setting,
select the line ‘Fine tuning’. With the t (left cursor) or
u (right cursor) key you can vary the automatic TV
channel setting.
This DVD recorder can receive HiFi sound transmissions
in NICAM Stereo. However, if sound distorsion occurs,
due to poor reception, you can switch off NICAM:
Manual TV channel search
You can perform a search to select and store TV
channels manually. If the DVD recorder is connected via
EasyLink, this function is not available.
l Press SYSTEM MENU.
l Select ‘Installation’.
l Select ‘Manual search’.
l In the line ‘Channel/freq.’ select the display for:
Freq. : frequency
CH : channel
S-CH : special channel
l If you know the frequency or channel of the desired
TV channel, you can enter the data in line
‘Entry/search’ with the digit keys 0-9. If you don’t
know the frequency or channel of the TV channel of
your choice, press u (right cursor) to start channel
search.
l In the line ‘Programme number’ select the
programme number you want, using t or u (left
right cursor) or digit keys 0-9.
l If you want to change the TV channel name, press
the u (right cursor) key in line ‘TV channel name’.
l Select the character you want to change with the t
(left cursor) or u (right cursor) key.
l Change the character with the w (down cursor) or
v (up cursor) key.
l Press OK to confirm.
To exit press
SYSTEM MENU
Time
Year
Month
Date
Installation
Time/Date
OPERATION 27
To exit press
SYSTEM MENU
09: 38
2001
02
09
Time/Date
To adjust ‘Time’, ‘Year’, ‘Month’ and ‘Date’ with the
digit keys 0-9. Switch between fields with the w v
(down up cursor) keys.
l Select the TV channel to which you want to allocate
a programme number (starting with ‘P01’) with the
v (up cursor) or w (down cursor) key and press the
u (right cursor) key.
l Select the desired position with v or w (up down
cursor) key.
l To store, press OK.
l To end, press SYSTEM MENU.
To sort
Press
NED 1
NED 2
NED 3
RTL 4
RTL 5
VERON
.
.
.
PO1
PO2
PO3
PO4
PO5
PO6
.
.
.
Installation
Sort TV channels
Sort/Clear TV channels manually
l If the DVD recorder is connected to the TV set
with EasyLink or a similar system, manual sort
cannot be executed. In all other cases, you can
select.
l Press SYSTEM MENU.
l Select the line ’Installation’.
l Select the line ’Sort TV channels’.
DVDR980-985 /0X1
3.
26 OPERATION
LP/EP rec mode
In long play or extended play recording mode you can
select the ‘Sport’ setting to optimize the video
recording for images that contain fast movements, like
sports programmes. The setting does not influence high
quality or standard play recording mode.
Factory setting is ‘Stndrd’.
Auto chapters
If autochapters is ‘On’ every five to six minutes a
chapter marker (beginning of a new chapter) is inserted
during recording. This enables easy navigation through a
title during playback. In either case you can manually
insert chapter markers afterwards. (See ‘Managing disc
content’ - ‘Edit in playback mode’.)
Sat record
You can only use this function, when you have a satellite
receiver, which can control other equipment by a
’programming’ function. In this mode your DVD
recorder starts recording when the satellite receiver
releases a signal. The start and end of the recording is
controlled via one of the SCART sockets.
l In the record settings menu, select ‘Sat record’.
l Select the SCART socket to which the satellite
receiver is connected with t or u (left right cursor).
l Confirm with OK.
l Insert a recordable DVD+RW disc.
l Press B STANDBY/ON.
‰ When this function is switched on, SAT appears
on the display.
‰ The DVD recorder is now prepared for
recording.
Factory setting is ‘Off’.
Direct record
With the Direct Record function switched ‘On’ and the
DVD recorder switched to standby, the channel number
selected on your television will be automatically taken
over by the DVD recorder, at the moment it starts
recording. This only applies for televisions connected via
SCART, which have video output via SCART or which have
EasyLink. Factory setting is ‘Off’.
l In the record settings menu, select ‘Direct record’.
l Select ‘On’. If you select ‘Off’, the function will be
switched off.
l Confirm with OK.
l To end, press SYSTEM MENU.
Directions For Use
EN 17
English
English
TITLE 1
CHAPTER 2
CHAPTER 3
CHAPTER 2
TITLE 2
CHAPTER 1
28 RECORDING
Note:
- On a disc containing PAL recordings, no NTSC recordings
can be made and vice versa. On an empty disc, either type of
recordings can be made.
- No recordings can be made from so-called ‘Pseudo-PAL’ or
PAL-60 sources.
Your DVD recorder always checks the disc that you
have inserted:
‰ When a DVD+RW disc is inserted on which
recordings have been made, the Index Picture
Screen is shown on your TV screen.
‰ If the inserted disc is a completely empty
recordable disc, the message ‘EMPTY DISC’ appears
on the display.
‰ If the inserted disc is a DVD+RW disc with a
content that is not DVD-Video compatible (e.g. a
data disc), a dialog box is shown with the option to
erase or eject the disc. You can only record on this
disc after erasing it with the RECORD key.
In the Index Picture Screen you can select the point
where you want to start your recording. Use the w v
(down up cursor) and 5 REVERSE / 6 FORWARD
keys. You can see the the current location on the disc
bar, indicated by the arrow.
press REC to erase disc
Press OK to open tray or
l Insert a recordable DVD+RW or DVD+R disc.
l Normally, the DVD recorder displays the contents
of the disc on the screen.
l Use the MONITOR button to see the currently
selected TV channel.
l Use CHANNEL 3 or CHANNEL 4 (on the
recorder) or CH+, CH- (on the remote control) to
select the programme number (programme name)
from which you wish to record.
‰ When a TV channel transmits a channel name,
it will be shown on the display.
Recording
Normally, the DVD recorder displays the contents of
the disc on screen.
l Press MONITOR in order to switch to the internal
tuner, or whichever other source is selected, if you
want to check the input before starting a recording.
‰ On the TV screen, you will see the actual picture
quality that you will get if you record: the video has
been encoded and decoded again. This is why you
will see a delay of about 1.5 seconds when using a
‘live’ source such as a camera.
l In monitor mode you can choose programme
numbers directly with the digit keys 0-9 on the
remote control.
l Press SELECT repeatedly to select the desired
record mode.
l Press MONITOR again to go back to disc mode.
Checking input
Manual recording
‰ A disc can hold up to 48 titles (including empty
titles). When this maximum is reached the onscreen message ‘Too many titles’ appears, if you
want to make a new recording. You have to erase a
title first next to an empty title. (See ‘Managing Disc
Content’.)
01 B B C 1
11:15
Disc is not a DVD video disc
MUTE
A/CH
CH
STOP
REVERSE
PREVIOUS
MONITOR
PAUSE
FSS
REC/OTR
SLOW
PLAY
FORWARD
NEXT
ON/OFF
l To bring back the status box during recording press
SYSTEM MENU. Pressing SYSTEM MENU once
more will remove the status box again.
l Press ; PAUSE to pause recording. You can
resume recording by pressing ; PAUSE once more.
The DVD recorder will make a seamless connection.
l Press 9 STOP to stop recording. If you are recording
from a camcorder watch the video output of the
DVD recorder on the TV - instead of the camcorder
viewer - to determine the right moment to stop.
l Press RECORD (on the recorder) or REC/OTR
(on the remote control).
‰ RECORD is shown on the display.
‰ The status box is shown on the screen for a few
seconds.
‘EXT1’ : TV set via SCART 1 socket
‘EXT2’ : for recording from external sources via
SCART 2 socket
’EXT3’ : rear S-video
‘EXT4’ : rear CVBS
‘CAM1’ : front S-video (Y/C)
‘CAM2’ : front Video (CVBS)
The following programme numbers are provided for
recording from external sources:
T/C
VOL
-30
-20
SP
-40
CHAPTER
RW
TITLE
DVD
-10
0
OVER
MANUAL
-40
TIME
-30
REMAIN
-10
STEREO
0
OVER
RECORDING 29
-20
RECORD
CHANNEL
You can control the audio recording level of your DVD
recorder manually.
l In monitor mode, press AUTO/MAN REC
VOLUME on the DVD recorder.
‰ The display will show the current audio level and
MANUAL appears.
Manual audio control
Notes :
- Don’t select another programme number on your TV set,
until the ‘WAIT’ on the display of your DVD recorder
disappears. This can take up to one minute.
- When ‘NOTV’ appears on the display, the programme
number could not be found. The DVD recorder switches off
automatically.
- If your loudspeakers are connected (via an amplifier /
receiver) to your DVD recorder, the sound will be delayed
relative to the TV picture when recording directly from the TV
set.
- You can use Direct Record in combination with Safe Record.
Direct Record
With Direct Record you can start recording immediately
from the programme selected on the TV set.
l Make sure ‘Direct record’ is switched ‘On’.
(See record settings).
l On the TV set, select the programme number you
want make the recording from.
l Make sure the DVD recorder is switched to
standby.
l Press RECORD (on the recorder) or REC/OTR
(on the remote control).
Safe Recording
When you start recording on a DVD+RW disc by briefly
pressing the RECORD or REC/OTR key, a recording
on DVD+RW will be made from the current position of
the disc pointer. To prevent this do the following:
l Hold the RECORD key (on the recorder) or
REC/OTR key (on the remote control) press for
about two seconds until ‘SAFE RECORD’ appears
on the display.
l The recorder automatically jumps to the end of the
last title on the disc and starts recording.
‰ If no free space is left. The display will show
‘DISC FULL’. Safe record is not possible then.
Recordings on DVD+RW are always automatically made
after the last title on the disc.
DVDR980-985 /0X1
If you want to make a recording without the risk
of overwriting earlier recordings use the safe
Record Function (see Manual Recording - Safe
Record)
Important:
Recordings on a DVD+RW disc are normally
started from the position of the so-called disc
pointer, i.e. the point where the last recording
was stopped. From there on earlier recordings
may be overwritten without notice, unless the
disc is write protected. In this respect your DVD
recorder behaves just like a Video Cassette
Recorder.
For more information about how to go to other titles or
chapters see ‘Playback - general features’.
CHAPTER 1
stop
l The Index Picture Screen is updated.
‰ ‘MENU UPDATE’ is shown on the display.
l After a short recording on a new DVD+RW disc, a
few minutes will be needed to complete the
formatting of the disc.
3.
DVD+RW
Recordings on a DVD disc are called ‘titles’. Every title
consists of one or more chapters.
Before you start recording
Recording
EN 18
Directions For Use
English
English
MUTE
TIMER
SELECT
A/CH
CH
STOP
REVERSE
PREVIOUS
MONITOR
PAUSE
FSS
REC/OTR
SLOW
PLAY
FORWARD
NEXT
ON/OFF
SELECT
l Press u (right cursor).
To exit
Press TIMER
ShowView programming
Timer programming
Timer list
Timer
To store
Press OK
l
l
l
l
l
l
‰ The data will appear on the TV screen.
Press u (right cursor).
Use SELECT to select the programming key at
daily or weekly intervals. Mo-Fr: Recording at daily
intervals from Mondays to Fridays inclusive. Weekly:
Recording at weekly intervals on the same day of
the week.
Press u (right cursor).
Use SELECT to switch VPS/PDC on or off.
‰ When VPS/PDC is switched on, the start time is
marked with an asterisk.
Press u (right cursor).
Use SELECT to select the recording mode (‘HQ’,
‘SP’, ‘LP’, ‘EP’).
Please enter
programme number
Timer
VIDEO Plus+ programming
l Enter the entire PlusCode number (up to nine digits)
printed in your TV guide next to the start time of a
TV programme. If you made a mistake, you can
correct it with CLEAR.
l Confirm with OK.
l If the VIDEO Plus+ system does not recognize the
TV channel, the message ‘Please enter
programme number’ will appear on screen. Select
the required programme number (programme name)
with t u (left right cursor) or the digit keys 0-9 and
confirm with OK.
Mo-Fr/Weekly
Press SELECT
ShowView number
ShowView programming
Timer
VPS
PDC
To store
Press OK
11:35
End
SP
Rec
Mode
TIMER
SELECT
RECORDING 31
l Press u (right cursor).
l Enter the date with v (up cursor) or w (down
cursor), or with the digit keys 0-9.
To exit
Press TIMER
ShowView programming
Timer programming
Timer list
Timer
l Press TIMER on the remote control.
l Select ‘Timer programming’ with v (up cursor) or
w (down cursor).
CLEAR
Timer programming without the VIDEO
Plus+ system
l Confirm with OK.
‰ The data has been stored in a timer block.
l To end, press TIMER.
l Make sure that you inserted a recordable disc.
If you inserted a write-protected disc recording
will be refused.
l Switch off with B STANDBY/ON.
LP/SP
Press SELECT
NED 1
09
09:35
Prog. Start
Date
ShowView programming
Timer
3.
30 RECORDING
TIMER
A PlusCode number is a number of up to nine digits,
printed in most TV guides next to the start time of a TV
programme.
All the information required for a programming is
contained encoded in the PlusCode programming number.
l Select ‘VIDEO Plus+ programming’ with v (up
cursor) or w (down cursor).
CLEAR
Timer programming with the VIDEO
Plus+® system
What is ’VPS’/‘PDC’?
With ’VPS/PDC’, the TV station controls the
beginning and the length of the programmed
recording. This means that the video recorder
switches itself on and off at the right time even if a
TV programme you have programmed begins earlier
or finishes later than expected.
Usually the start time is the same as the VPS/PDC
time. If, however, in the TV guide, in addition to a TV
programmes start time, a different VPS/PDC time is
given, e.g.: ’20.15 (VPS 20.14)’, you must enter ’20.14’
as the start time exactly to the minute. If you want
to enter a time that differs from the VPS/PDC time,
you must switch off ’VPS/PDC’.
When all timer blocks are full, the options timer
programming and VIDEO Plus+ programming cannot be
accessed. For clearing a timer block, see ‘How to clear a
timer block’.
When you have programmed the timer, a red line on
the disc bar (both on the display and on the Index
Picture Screen) indicates what part of the disc will be
overwritten by the programmed recording from the
current disc position (on DVD+RW) or after the last
title (on DVD+R).
DVDR980-985 /0X1
The DVD recorder stores all the information mentioned
above in a timer block. You can programme up to six
timer blocks, one month in advance.
The DVD recorder needs the following information for
every programmed recording:
- the date on which the recording is to be made;
- the channel;
- the start and stop time of the recording;
- VPS/PDC on or off;
- the recording mode (HQ, SP, LP or EP).
Timer programming
l Press RECORD or REC/OTR again to obtain a
30 minute increment.
l Shortly after pressing REC/OTR, OTR can be
cancelled by pressing CLEAR.
10: 15hr
l Insert a recordable DVD+RW or DVD+R disc.
l Use CHANNEL 3 or CHANNEL 4 (on the
recorder) or CH+, CH- (on the remote control) to
select the programme number (programme name)
from which you wish to record.
l Press RECORD (on the recorder) or REC/OTR
(on the remote control) twice.
‰ A recording will be made of 30 minutes.
‰ The required end time of the recording is shown
in the timer box on screen. The remaining recording
time is shown on the display.
T/C
VOL
CLEAR
Recording with automatic switch-off (OTR
One-Touch Recording)
l Adjust the recording level with MANUAL 3 or 4
on the DVD recorder, so that the ‘0 dB’ mark lights
up during the loudest parts of the recording.
l You can switch back to automatic audio level control
by pressing AUTO/MAN REC VOLUME again.
‰ The display will show the current disc position
and MANUAL disappears.
Directions For Use
EN 19
English
English
*
VPS
PDC
To store
Press OK
11:35
End
SP
Rec
Mode
32 RECORDING
l Confirm with OK .
‰ The data has been stored in a timer block.
l To end, press TIMER .
‰ Make sure that you inserted a disc without write
protection. If you inserted a write-protected
(locked) disc, recording will be refused.
l Switch off with B STANDBY/ON.
Mo Fr Weekly
Press SELECT
NED 1
09
09:35
Prog. Start
Date
Timer programming
Memory full
The maximum number of recording programmes is used.
Solution:
l Delete one of the recording programmes.
Weekend programming - not possible
Date was incorrectly entered. Daily programming can
only be used for recordings to be made from Mondays
to Fridays inclusive.
PlusCode number wrong
You entered an incorrect PlusCode number or the
incorrect date.
Solution:
l Repeat the entry or end by pressing TIMER.
Please enter programme number
The VIDEO Plus+ system does not recognize the TV
channel.
Solution:
l Select the required programme number
(programme name) with t or u (left right
cursor).
l Confirm with OK.
09: 35
21: 00
20: 30
*
*
VPS
PDC
11: 35
23: 00
22: 00
End
SP
SP
SP
Rec
Mode
l Select the timer block you want to check or alter
with w or v (down up cursor).
l Press u (right cursor).
l Select what you want to check or alter with t or u
(left right cursor).
l Alter data with w or v (down up cursor) or with
the digit keys 0-9.
l Confirm with OK.
l To end, press TIMER.
l Switch off by pressing B STANDBY/ON.
To exit
Press TIMER
T o t a l r e c o r d t i m e 05: 30
NED 1
RTL 2
VRT
Prog. Start
To change
Press
09
12
14
Date
Timer list
Timer
l Press u (right cursor).
To exit
Press TIMER
ShowView programming
Timer programming
Timer list
TIMER
SELECT
RECORDING 33
Press TIMER on the remote control.
Select ‘Timer list’ with w or v (down up cursor).
Press u (right cursor).
Select the timer block you want to clear with w or
v (down up cursor).
l Press CLEAR.
l Confirm with OK.
l Switch off by pressing TIMER.
l
l
l
l
CLEAR
How to clear a timer block
DVDR980-985 /0X1
Collision
recording programme overlaps with another recording
programme.
Solution:
l Ignore by pressing TIMER. The programme
with the earlier start time will be recorded
completely before the later programme starts.
l Edit one or both timers.
l Delete one of the recording programmes.
The following warnings can be displayed in the timer
menu:
If a timer setting is incorrect
l Press TIMER on the remote control.
l Select ‘Timer list’ with w or v (down up cursor).
This DVD recorder is equipped with the function
’NEXTVIEW Link’. If your television is also equipped with
this function, you can mark TV programmes on the
television for programming. These TV programmes will
automatically be transmitted to a timer block on the
DVD recorder. If you clear the marking of the TV
programme on the television, the corresponding timer
block on the DVD recorder will also be cleared.
For more information, read the instruction manual of
your TV set.
Timer
How to check or alter a timer block
Programming with ’NEXTVIEW Link’
3.
Timer
l If desired, select recording at daily or weekly
intervals in the field ‘Date’ with SELECT. ‘Mo-Fr’:
Recording to be made from Mondays to Fridays
inclusive. ‘Weekly’: Recording at weekly intervals on
the same day of the week.
l Press u (right cursor).
l Enter the programme number from which you want
to record. If you want to record from an external
source, select ‘EXT1’, ‘EXT2’, ‘EXT3’, ‘EXT4’, ‘CAM1’
or ‘CAM2’ with vw (up down cursor).
l Press u (right cursor).
l Enter the Start time with vw (up down cursor) or
the digit keys 0-9.
l After entering the Start time, use SELECT to
switch VPS/PDC on or off. With most TV stations
the VPS/PDC time is always the same as the start
time.
‰ When VPS/PDC is switched on, the start time is
marked with an asterisk.
l Press u (right cursor).
l Enter the End time with vw (up down cursor) or
the digit keys 0-9.
l Use SELECT to choose the recording mode ‘HQ’,
‘LP’, ‘SP’ or ‘EP’.
l If you made a mistake, you can go back with t (left
cursor).
English
EN 20
Directions For Use
English
PAUSE
FSS
REC/OTR
SLOW
PLAY
FORWARD
NEXT
l Insert a (Super) Video CD.
‰ When ‘autoresume’ is set to ‘On’ (see ‘User
Preferences’) playback starts automatically from the
point where it was stopped, the last time the disc
was played.
‰ The disc may invite you to select an item from a
menu. If the selections are numbered, press the
appropriate numerical key 0-9.
l To stop play at any time, press 9 STOP.
‰ The default screen will appear.
Playing a (Super) Video CD disc
Note:
During playback you can display and enter the menu by
pressing DISC MENU.
STOP
REVERSE
PREVIOUS
l The disc may invite you to select an item from a
menu. If the selections are numbered, press the
appropriate numerical key; if not, use the w v u t
(down up right left cursor) keys to highlight your
selection, and press OK.
l To stop play at any time, press 9 STOP.
‰ The default screen will appear, giving information
about the current status of the recorder.
Notes:
- DVD movies to be released at different times in different
regions of the world, all players have region codes and discs
can have an optional region code. If you load a disc of a
different region code to your recorder, you will see the region
code notice on the screen. The disc will not play, and should
be unloaded.
- The region code is stated on a label on the
back side of your recorder.
- Regional coding is not applicable for
recordable DVD discs.
SUBTITLE
SCAN
Y
CLEAR
FSS
REC/OTR
PAUSE
SLOW
NEXT
SELECT
PLAY
FORWARD
INDEX 1
CHAPTER 1
INDEX 2
TRACK 1
CHAPTER 2
TITLE 1
INDEX 3
VIDEO CD
CHAPTER 3
DVD VIDEO
CHAPTER 2
INDEX 1
INDEX 2
TRACK 2
CHAPTER 1
TITLE 2
Notes:
- If the number has more than one digit, press the keys in
rapid succession.
- If the system menu bar is on screen, make sure the
icon
is selected.
l Press T/C.
l Press K NEXT during play to step forward to the
next title.
l Press J PREVIOUS during play to return to the
beginning of the current title. Rapidly press
J PREVIOUS twice to step back to the previous
title.
l To go directly to any title or track, enter the title
number using the numerical keys 0-9.
REPEAT
DIM
REPEAT
Z
AUDIO
ANGLE
ZOOM
a
A/CH
T/C
STOP
REVERSE
PREVIOUS
When a disc has more than one title or track, you can
move to another title as follows:
Moving to another title/track
Note:
Unless stated otherwise, all operations described are based
on remote control operation. A number of operations can also
be carried out via the system menu bar on the screen. (see
‘System menu bar operation’)
General features
FSS
REC/OTR
PAUSE
SLOW
NEXT
PLAY
FORWARD
0 1/8 1/4 1/2 1
PLAYBACK 35
l Use the t u (left right cursor) keys to select the
required speed: ‘-1’, ‘-1/2’, ‘-1/4’ or ‘-1/8’
(backward); ‘1/8’, ‘1/4’, ‘1/2’ or ‘1’ (forward).
l Select ‘1’ to play at normal speed again.
l If ; PAUSE is pressed, the speed will be set to ‘0’.
l Press 2 PLAY to exit slow motion mode.
l Press v (up cursor) to delete the slow motion menu.
You can also select Slow Motion speeds by using the
SLOW key on the remote control.
- 1 - 1 /2 - 1 / 4 - 1 / 8
l Select
(Slow motion) in the system menu bar.
l Use the w (down cursor) key to enter the slow
motion menu.
‰ The recorder will now go into pause mode.
STOP
REVERSE
PREVIOUS
Slow Motion
Notes:
- If the number has more than one digit, press the keys in
rapid succession.
- If the system menu bar is on screen, make sure the
icon
is selected.
When a title on a disc has more than one chapter or a
track has more than one index, you can move to
another chapter/index as follows:
l Press K NEXT during play to select the next
chapter/index.
l Press J PREVIOUS during play to return to the
beginning of the current chapter/index. Rapidly press
J PREVIOUS twice to step back to the previous
chapter/index.
l To go directly to any chapter or index, enter the
chapter or index number using the numerical keys
0-9.
Moving to another chapter/index
DVDR980-985 /0X1
3.
34 PLAYBACK
l Insert a pre-recorded DVD-Video disc. Make sure
the label is facing up. If the disc is two-sided, make
sure the label of the side you want to play is facing
up.
‰ When ‘autoresume’ is set to ‘On’ (see ‘User
Preferences’) playback starts automatically from the
point where it was stopped, the last time the disc
was played.
‰ When ‘autoresume’ is set to ‘Off’, the disc will
play from the start of the disc. You can however
resume play from the point at which you stopped,
the last time the disc was played, by pressing
2 PLAY when
appears on screen.
‰ The currently playing title and chapter number
are displayed on the recorder display. The elapsed
time is shown also.
Some DVD discs are produced in a way that requires
specific operation or allows only limited operation
during playback. In these cases the recorder may not
respond to all operating commands. When this occurs,
please refer to the instructions in the disc inlay. When a
appears on the TV screen, the operation is not
permitted by the recorder or the disc.
Playing a pre-recorded DVDVideo disc
l Insert a DVD+RW or DVD+R disc.
‰ If the inserted disc is write-protected, playback
starts automatically otherwise the Index Picture
Screen appears.
l Press 2 PLAY.
‰ Playback starts automatically from the point
where it was stopped the last time the disc was
played or recorded. If you want to start playback
from the beginning of the disc, you can do so via the
Index Picture Screen (see ‘Index Picture Screen’).
‰ If the disc is a new blank disc, the display will
show ‘EMPTY DISC’.
l To stop playback at any time, press 9 STOP.
‰ You return to the Index Picture Screen.
Playing a DVD+RW or DVD+R
disc
Playback
Directions For Use
EN 21
English
English
FSS
SLOW
PLAY
FORWARD
NEXT
PAUSE
FSS
REC/OTR
SLOW
PLAY
FORWARD
NEXT
1
4 8 32
36 PLAYBACK
l Use the t u (left right cursor) keys to select the
required speed: ‘-32’, ‘-8’ or ‘-4’ (backward); ‘4’,
‘8’, ‘32’ (forward).
l Select ‘1’ to play at normal speed again.
l Press 2 PLAY to exit fast motion mode.
l Press v (up cursor) to delete the fast motion menu.
To search forward or backward through different speeds,
you can also press 5 REVERSE or 6 FORWARD
again.
-32 -8 -4
l Select
(Fast motion) in the system menu bar.
l Use the w (down cursor) keys to enter the fast
motion menu.
STOP
REVERSE
PREVIOUS
Search
Z
REPEAT
REPEAT
SUBTITLE
a
ANGLE
DIM
ZOOM
SCAN
Y
AUDIO
REPEAT
DIM
SUBTITLE
Z
REPEAT
ANGLE
a
ZOOM
SCAN
Y
AUDIO
‰
repeat appears on screen, and the repeat
sequence begins.
l To exit the sequence, press REPEAT A-B.
‰
appears on screen.
l Press REPEAT A-B again at your chosen end
point;
To repeat or loop a sequence in a title:
l Press REPEAT A-B at your chosen starting point;
Repeat A-B
‰
appears on screen.
l To exit repeat mode, press REPEAT a third time.
‰
appears on screen.
l To repeat the entire disc, press REPEAT a second
time.
Video CDs - Repeat track/disc
l To repeat the currently playing track, press
REPEAT.
‰
appears on screen.
l To exit repeat mode, press REPEAT a fourth time.
‰
appears on screen.
l To repeat the entire disc, press REPEAT a third
time
‰
appears on screen.
l To repeat the currently playing title, press REPEAT
a second time
DVD Discs - Repeat chapter/title/disc
l To repeat the currently playing chapter, press
REPEAT.
Repeat
Z
REPEAT
REPEAT
SUBTITLE
a
ANGLE
DIM
ZOOM
SCAN
Y
AUDIO
l Use the digit keys 0-9 to enter the required start
time. Enter hours, minutes and seconds in the box.
‰ Each time an item has been entered, the next
item will be highlighted.
l Press OK to confirm the start time.
‰ The time entry box will disappear and play starts
from the selected time position.
The Time Search function allows you to start playing at
any chosen time stamp.
l Select
(Time Search) in the system menu bar.
l Press w (down cursor).
‰ The recorder will now go into pause mode.
‰ A time entry box appears on the screen showing
the elapsed playing time of the current disc.
Time search
Plays the first 10 seconds of each chapter/index on the
disc.
l Press SCAN.
l To continue play at your chosen chapter/index,
press SCAN again or press 2 PLAY.
Scan
ANGLE
REPEAT
REPEAT
Z
SUBTITLE
SCAN
Y
AUDIO
A/CH
STOP
CLEAR
REVERSE
PREVIOUS
TIMER
FSS
REC/OTR
PAUSE
SLOW
NEXT
SELECT
PLAY
FORWARD
PLAYBACK 37
‰ The picture will change accordingly.
l Press OK to confirm the selection.
‰ The panning icons appear on the screen:
w v u t (down up right left cursor) and OK.
l Use the w v u t (down up right left cursor) keys
to pan all over the screen.
l When OK is pressed only the zoomed picture will
be shown on the screen.
l If you wish to zoom at any moment, press a Zoom
and select the required zoom factor as described
above.
l Press 2 PLAY to exit zoom mode.
press OK to pan
The Zoom function allows you to enlarge the video
image and to pan through the enlarged image.
l Select a Zoom in the system menu bar.
l Press w v (down up cursor) to activate the Zoom
function and select the required zoom factor; 1.33
or 2 or 4.
‰ The recorder will go into pause mode.
‰ The selected zoom factor appears below the
Zoom icon in the system menu bar and ‘Press OK
to pan’ appears below the system menu bar.
DIM
a
ZOOM
T/C
Zoom
DVDR980-985 /0X1
l Use t u (left right cursor) keys to select previous
or next picture.
l Press 2 PLAY to exit picture by picture mode.
l Press v (up cursor) to exit the picture by picture
menu.
You can also step forward by using the ; PAUSE
repeatedly on the remote control.
l Select
(picture by picture) in the system menu
bar.
l Use the w (down cursor) key to enter the picture
by picture menu.
‰ The recorder will now go into pause mode.
STOP
PAUSE
REC/OTR
3.
REVERSE
PREVIOUS
Still Picture and Step Frame
English
EN 22
Directions For Use
English
SUBTITLE
Y
Z
Y
Y
Z
SUBTITLE
Y
AUDIO
ANGLE
ZOOM
a
A/CH
T/C
l Select Z (Subtitle) in the system menu bar.
l Press Z SUBTITLE or w v (down up cursor)
repeatedly to step through the different subtitles, or
to switch the subtitles off.
l You can enter the required subtitle number directly
using the numerical keys 0-9.
Subtitles
Z
AUDIO
SUBTITLE
ZOOM
a
A/CH
T/C
ANGLE
l Select Y (Audio) in the system menu bar.
l Press Y AUDIO or w v (down up cursor)
repeatedly to step through the different languages.
l You can enter the required language number directly
using the numerical keys 0-9.
Changing the audio language
l Use the w v keys to select the required angle in the
angle box.
l To go to any angle directly, enter the angle number
using the numerical keys 0-9.
‰ After a small delay, play changes to the selected
angle. The angle box remains displayed until multiple
angles are no longer available.
a
A/CH
SUBTITLE
AUDIO
ANGLE
T/C
ZOOM
PAUSE
FSS
REC/OTR
SLOW
PLAY
FORWARD
NEXT
1
track
time
2 78
14
total tracks
total time
1 12 78
l To stop play at any time, press 9 STOP.
‰ The number of tracks and the total playing time
will be shown on the screen and the recorder
display.
play
repeat track
Audio disc mode
l Insert the disc.
‰ After loading the disc, playback starts
automatically.
‰ If the TV set is on, the Audio CD screen appears.
‰ During play, the current track number and its
elapsed playing time will be shown on the screen
and the recorder display.
Playing an audio CD
l Make sure PBC is switched ‘On’. See ‘User
Preferences-features settings’.
l Load a (Super) Video CD with PBC and press
2 PLAY.
‰ The PBC menu appears on screen.
l Go through the menu with the keys indicated on the
TV screen until your chosen passage starts to play.
If a PBC menu consists of a list of titles, you can
select a title directly.
l Enter your choice with the numerical keys 0-9.
l Press RETURN to go back to the previous menu.
STOP
REVERSE
PREVIOUS
Playback Control (PBC)
Special VCD features
STOP
REVERSE
PAUSE
FSS
SLOW
PLAY
FORWARD
STOP
REVERSE
PAUSE
FSS
SLOW
PLAY
FORWARD
PAUSE
REC/OTR
SLOW
FORWARD
NEXT
1
2
3
4
5
6
7
TRACKS
8
AUDIO CD
3.
PLAYBACK 39
9 10 11 12 ...
l Press K NEXT during play to step forward to the
next track.
l Press J PREVIOUS during play to return to the
beginning of the current track. Rapidly press
J PREVIOUS twice to step back to the previous
track.
l To go directly to any track, enter the track number
using the numerical keys 0-9.
REVERSE
PREVIOUS
Moving to another track
l To search forwards or backwards through the disc
at 4x normal speed, press 5 REVERSE or 6
FORWARD.
‰ Search begins.
l To step up to 8x normal speed, press 5 REVERSE
or 6 FORWARD again.
‰ Search goes to 8x speed, and the sound is muted.
l To return to 4x normal speed, press 5 REVERSE
or 6 FORWARD again.
l If the TV set is on, search speed and direction are
indicated on the screen each time 5 REVERSE or
6 FORWARD is pressed.
l To end the search, press 2 PLAYor 9 STOP as
desired.
Search
l Press ; PAUSE during play.
l To return to play, press 2 PLAY.
Pause
DVDR980-985 /0X1
38 PLAYBACK
If the disc contains sequences recorded from different
camera angles, the angle box appears, showing the
number of available angles, and the angle being shown.
You can then change the camera angle if you wish.
Camera Angle
If a DVD-Video disc has separate disc and title menus,
you can navigate to the disc menu as follows:
l Press T/C followed by DISC MENU .
‰ The disc menu is displayed.
l To remove the disc menu, press DISC MENU
again.
Z
AUDIO
ANGLE
ZOOM
a
A/CH
T/C
Disc menu
Note:
Most DVD discs do not have separate disc and title menus.
l Press DISC MENU .
‰ If the current title has a menu, this appears on
the screen. If no menu is present in the title, the
disc menu will be displayed.
l The menu can list camera angles, spoken language
and subtitle options, and chapters for the title.
l To exit the title menu, press DISC MENU again.
Title menus
For titles and chapters, selection menus may be included
on the disc.
The DVD’s menu feature allows you to make selections
from these menus. Press the appropriate numerical key;
or use the w v u t (down up right left cursor) keys to
highlight your selection, and press OK .
Menus on the disc
Special DVD-Video features
Directions For Use
EN 23
English
English
Y
REPEAT
REPEAT
DIM
SUBTITLE
Z
ANGLE
a
ZOOM
SCAN
Y
AUDIO
Y
SCAN
Z
REPEAT
a
DIM
REPEAT
AUDIO
SUBTITLE
ANGLE
ZOOM
40 PLAYBACK
Plays the first 10 seconds of each track on the disc.
l Press SCAN.
l To continue play at your chosen track, press SCAN
again or press 2 PLAY.
Scan
ANGLE
Z
SUBTITLE
Y
AUDIO
A/CH
---
off
Enter code
on
Features
off
Change code
Autoresume
PBC
Low power standby
Change country
Status box
Child lock
off
Parental level
---
Access control
--
on
Features
off
l Enter a 4-digit PIN code of your own choice using
the digit keys 0-9.
l Enter the code a second time.
l Move to ‘Child lock’ using wv (down up cursor).
l Move to Ç / É using the u (right cursor) key.
PBC
Low power standby
Autoresume
Status box
Access control
--
l Select ‘Access control’ in the features menu using
wv (down up cursor) and press u (right cursor).
a
ZOOM
T/C
Activating/deactivating the child lock
When activating Child lock, only discs that are authorised
can be played without PIN code.
The recorder memory maintains a list of 50 authorized
(‘Child safe’) disc titles. A disc will be placed in the list
when ‘Play Always’ is selected in the ‘Child protect’ dialog.
Each time a ‘Child safe’ disc is played it will be placed on
top of the list. When the list is full and a new disc is added,
the least recently used will be removed from the list.
Child Lock (DVD and VCD)
Play always
Play once
Access Control
ACCESS CONTROL 41
l Insert the disc.
‰ Playback starts automatically.
l Press 9 STOP while { is visible.
‰ | will appear and the disc is now banned i.e. it is
not Child safe any longer.
Securing discs
Note:
Double sided DVD discs may have a different ID for each
side. In order to make the disc ‘Child safe’, each side has to
be authorized.
Multi volume VCD disc may have a different ID for each
volume. In order to make the complete set ‘Child safe’, each
volume has to be authorized.
the child-safe list
Choose 'Play always' to insert the disc in
locked
l Insert the disc.
‰ The ‘Child protect’ dialog will appear. You will be
asked to enter your secret code for ‘Play once ’ or
‘Play always ’. If you select ‘Play once ’, the disc
can be played as long as it is in the recorder and the
recorder is in the On position. If you select ‘Play
always ’, the disc will become Child safe
(authorized) and can always be played even if the
Child lock is set to ‘On’.
Authorizing discs when Child Lock is
activated
Note:
Reconfirmation of the 4-digit PIN code is necessary when:
The code is entered for the very first time (see above);
The code is changed (see ‘Changing the 4-digit code’);
The code is cancelled (see ‘Changing the 4-digit code’);
Both Child Lock and Parental Control are switched Off and
the code is requested.
l Select Ç using wv (down up cursor).
l Press OK or t (left cursor) to confirm and press
SYSTEM MENU again to exit the menu.
‰ Now unauthorized discs will not be played unless
the 4-digit code is entered.
l Select É to deactivate the Child Lock.
DVDR980-985 /0X1
To repeat or loop a sequence:
l Press REPEAT A-B at your chosen starting point;
‰ ‘Repeat A’ appears on screen.
l Press REPEAT A-B again at your chosen end
point;
‰ ‘Repeat A-B’ appears on the display, and the
repeat sequence begins.
l To exit the sequence, press REPEAT A-B again.
Repeat A-B
l To repeat the currently playing track, press
REPEAT.
‰ ‘Repeat track’ appears on screen.
l To repeat the entire disc, press REPEAT a second
time.
‰ ‘Repeat disc’ appears on screen.
l To exit repeat mode, press REPEAT a third time.
SCAN
Z
REPEAT
a
DIM
REPEAT
AUDIO
SUBTITLE
ANGLE
3.
ZOOM
Repeat track/disc
Access control
EN 24
Directions For Use
English
English
Y
Change code
Autoresume
on
-Features
off
a
Z
Y
A/CH
SUBTITLE
AUDIO
ANGLE
T/C
ZOOM
---
l Select a country using wv (down up cursor).
l Press OK or t (left cursor) to confirm and press
SYSTEM MENU again to exit the menu.
PBC
Low power standby
Z
SUBTITLE
A/CH
Y
AUDIO
Change code
Change country
Parental level
Child lock
off
on
Features
off
Note:
If you forgot your code, press 9 STOP four times while in
the access control PIN code box and exit with OK. Access
control is now switched off. You can then enter a new code
as described above.
Press u (right cursor).
Enter the new 4-digit PIN code.
Enter the code a second time and reconfirm with OK.
Press SYSTEM MENU to exit the menu.
PBC
Low power standby
Status box
Finland
l
l
l
l
---
Access control
--
Auto resume
off
Autoresume
on
Denmark.
Belgium
Austria
off
ANGLE
l Select ‘Access control’ in the features menu using
wv (down up cursor) and press u (right cursor).
l Enter the old code.
l Move to ‘Change code’ using w (down cursor).
a
ZOOM
T/C
Changing the 4-digit code
Status box
Access control
--
l Select ‘Access control’ in the features menu using
wv (down up cursor) and press u (right cursor).
l Enter the four digit PIN code.
l Move to ‘Change country’ using w (down cursor).
l Press u (right cursor).
Country
ACCESS CONTROL 43
DVDR980-985 /0X1
3.
42 ACCESS CONTROL
l Use the w v (down up cursor) keys or the
numerical keys 0-9 on the remote control to select
a rating from 1 to 8 for the disc inserted.
Rating 0 (displayed as ‘– –’):
Parental Control is not activated. The disc will be played
in full.
Ratings 1 to 8 (1 = childsafe - 8 = adults only):
The disc contains scenes not suitable for children. If you
set a rating for the recorder, all scenes with the same
rating or lower will be played. Higher rated scenes will
not be played unless an alternative is available on the
disc. The alternative must have the same rating or a
lower one. If no suitable alternative is found, play will
stop and the 4-digit code has to be entered.
l Press OK or t (left cursor) to confirm and press
SYSTEM MENU again to exit the menu.
PBC
Low power standby
Change country
Status box
Child lock
off
Parental level
---
Access control
--
l Select ‘Access control’ in the features menu using
wv (down up cursor) and press u (right cursor).
l Enter your 4-digit PIN code using the digit keys 0-9.
If necessary enter the code a second time.
l Move to ‘Parental level’ using wv (down up cursor).
l Move to the Value Adjustment bar using u (right
cursor).
Z
SUBTITLE
AUDIO
ANGLE
ZOOM
a
A/CH
T/C
Activating/Deactivating Parental Control
Movies on pre-recorded DVD discs may contain scenes
not suitable for children. Therefore discs may contain
‘Parental Control’ information which applies to the
complete disc or to certain scenes on the disc.
These scenes are rated from 1 to 8 and alternative, more
suitable scenes are available on the disc. Ratings are
country dependent. The ‘Parental Control’ feature allows
you to prevent discs from being played by your children
or to have certain discs played with alternative scenes.
Parental Level (DVD-Video only)
Directions For Use
EN 25
English
English
44 MANAGING DISC CONTENT
You may simply erase a title on DVD+RW by recording
over it, but if you want to erase the whole title instantly,
do the following:
l In the Index Picture Screen, select the required title
with wv (down up cursor).
l Press u (right cursor) to enter the title settings menu.
l Select ‘Erase this title’.
‰ The message 'This will completely erase this
title', 'Press OK to confirm' is shown.
Erasing a title
l In the Index Picture Screen, select the required title
with wv (down up cursor).
l Press u (right cursor) to enter the title settings menu.
l Select ‘Play full title
’.
When this item is selected the title will be played in full,
including hidden chapters. Follow the instructions on the
screen. (See ‘managing disc content - Favorite Scene
Selection’)
Play full title
l Enter the new name. A name may contain a
maximum of 64 characters.
l Use t u (left right cursor) for the position of the
characters. Use w v (down up cursor) to change
characters.
l Use SELECT to toggle between capitals and lower
case characters.
l Use CLEAR to erase a character.
l Confirm by pressing OK.
BBC soccer
Cue to go back to the Index Picture
Screen
12 B B C 1
23:13 h r
Unlocked5
5
5
PAL5
5
5
DVD playback
Edits
Summer holiday5
02:05:10 used5
S u n 13 12 99
DVD+R disc status
- unlocked
Disc description
- locked
- disc name
- finalised
- total recording duration
- date of last recording
Video system
- PAL or SECAM
- NTSC
Compatibility status
- indicates compatibility of any edits
with DVD players
The Disc Info Screen contains the following
information:
l When on the Index Picture Screen, press 9 STOP.
‰ You are now on Title 1.
l Press v (up cursor).
‰ You enter the Disc Info Screen.
l Press w (down cursor) to exit the Disc Info Screen.
Disc Info Screen
On DVD+R titles can also be erased but the space
occupied cannot be used anymore. During
finalisation erased titles are removed from the Index
Picture Screen.
Summer holiday
Unprotected
Protection
This option is only aivailable for DVD+RW discs that are
not erase-protected.
l In the Disc Info Screen press u (right cursor).
‰ You will now enter the ‘disc settings’ menu.
l Select ‘Erase disc’ and press OK.
‰ The message 'This will erase all titles’ is
displayed.
Erasing a disc
l In the Disc Info Screen press u (right cursor).
‰ You will now enter the ‘disc settings’ menu.
l Select ‘Protection’ and press u (right cursor).
l Select ‘Protected’ with w v (down up cursor).
l Press OK on the remote control to confirm.
‰ No further changes can be made to the disc.
It will also disable most title/disc settings options, as
well as the complete edit menu.
‰ Future editing is only possible after resetting the
Protection feature to ‘Unprotected’ again.
Protection of recordings
l Enter the new name. A name may contain a
maximum of 64 characters.
l Use t u (left right cursor) for the position of the
characters. Use wv (down up cursor) to change
characters.
l Use SELECT to toggle between capitals and lower
case characters.
l Use CLEAR to erase a character.
l Confirm by pressing OK.
Erase disc
Disc name
Settings for Summer holiday
l In the Disc Info Screen press u (right cursor).
‰ You will now enter the ‘disc settings’ menu.
Changing the Disc Name
For each DVD+RW or DVD+R disc the settings can be
changed to your personal preference in the disc settings
menu.
l In the Disc Info Screen press u (right cursor).
‰ You will now enter the ‘disc settings’ menu.
Disc Settings
Unpr o t e ct e d
on
Features
off
MANAGING DISC CONTENT 45
Press OK
Off
Finalise disc
Off
Low power standby
On
Autoresume
Enter code ...
off
Status box
---
Access control
--
l Select ‘Finalise disc’ and press OK to confirm.
‰ ‘Finalise disc’ is shown until the action is
completed.
‰ After finalisation the Index Picture Screen will
appear.
If the DVD+R disc was recorded on a different brand of
DVD recorder you may not be able to access the Disc
Settings screen. In this case you can use the ‘Finalise
disc ’ option in the features menu of the user
preferences menu.
Fi n a l i s e cd i s
Pr e ss O K
Summer holiday
Pr o t ect i o n
Er a se d ics
Di sc n a m e
Settings for Summer holida
y
While a DVD+RW disc can be played instantly on most
DVD players, a DVD+R disc can be played only on the
DVD recorder until it is finalised. After finalisation no
changes can be made to the disc anymore.
l In the Disc Info Screen press u (right cursor).
‰ You will now enter the ‘disc settings’ menu.
Finalising a DVD+R disc
l Press OK to confirm or t (left cursor) to cancel.
‰ ‘Erasing disc’ is shown until the action is
completed.
‰ After the disc has been erased, the Index Picture
Screen will show the free space on the disc.
DVDR980-985 /0X1
Erase this title
Play full title
Name
Settings for title BBC soccer
l In the Index Picture Screen, select the required title
with wv (down up cursor).
l Press u (right cursor) to enter the title settings menu.
l Press OK to confirm.
‰ ‘Erasing title...’ is shown until the action is
completed.
‰ After the title has been erased, the Index Picture
Screen will show an empty space instead. If there
was an empty space in front of or behind this title,
then these are combined into one empty space.
Empty spaces of less then one minute will not be
shown.
3.
Changing the title name
For each title on a DVD+RW or DVD+R disc the
default settings can be changed to your personal
preference in the title settings menu.
Title settings
Managing disc content
EN 26
Directions For Use
English
English
PAUSE
FSS
REC/OTR
SLOW
PLAY
FORWARD
NEXT
ON/OFF
CLEAR
TIMER
SELECT
Hidden
Divide title
Use picture as index
Delete all chapter markers
Delete chapter marker
Press OK
Current chapter
Favourite scene selection
Insert chapter marker
1
FSS
REC/OTR
PAUSE
SLOW
NEXT
PLAY
FORWARD
Divide title
Delete all chapter markers
Delete chapter marker
Current chapter
Insert chapter marker
2
Hidden
Favourite scene selection
FSS on the remote control to
l Select ‘‘Current chapter‘’with w or v (down up
cursor).
l Select ‘Visible’ or ‘Hidden’ with the u (right cursor)
key.
l You can toggle between ‘Visible’ and ‘Hidden’
directly from any line in the FSS menu with the
SELECT key on the remote control.
play
1
l In play mode press
call up the FSS menu.
Initially all chapters are visible. You can hide chapters or
make them visible again on playback. In FSS mode however
hidden chapters are displayed in a dimmed mode.
Hiding chapters
STOP
REVERSE
PREVIOUS
During recording you can add chapter markers by
pressing
FSS on the remote control. The message
‘Chapter marker inserted’ will appear on the screen.
MANAGING DISC CONTENT 47
You can define the current video frame as a miniature
picture to be used for this title’s entry in the Index
Picture Screen.
l In play mode press
FSS on the remote control
to call up the FSS menu.
l Select ‘New index picture‘.
l You can use ; PAUSE and/or x SLOW to
accurately choose the desired picture.
l Press OK on the remote control to confirm.
‰ ‘Updating menu’ will appear.
Changing the index picture
3.
l Use w or v (down up cursor) to toggle through the
menu’s functions.
play
1
Note:
The Favourite Scene Selection menu may disappear after
about five minutes if you do not edit any information.
l Play the title you want to edit.
l Press the
FSS key on the remote control.
‰ The video image is overlayed with a transparant edit
menu. Title and chapter information appear in an
information box at the top of the screen.
STOP
REVERSE
PREVIOUS
MONITOR
Calling up the FSS menu
After editing, the modified version of a title is the default
playback version. The original can be accessed via the
‘Play full title’ option in the title settings menu. Other
DVD players may still play the original. To guarantee
that the edited version will play on these DVD players,
choose ‘Make edits DVD-compatible’ in the disc
settings menu (only available on DVD+RW discs).
Each title consists of chapters. With the FSS menu any
chapter can be made hidden or made visible again.
Normally, during recording, chapter markers are inserted
automatically every five to six minutes (this setting can be
changed in the record settings menu). After the recording
is finished, you can manually add and remove chapter
markers via the FSS menu. Both automatically generated
and manually inserted chapter markers can be removed.
DVDR980-985 /0X1
46 MANAGING DISC CONTENT
l Press OK on the remote control to confirm.
‰ The messages ‘This will take ...’ and ‘Press OK
to confirm’ will appear to indicate how long the
action will take.
l Press OK on the remote control to confirm.
‰ ‘Processing...’ and a progress bar are shown
until the action is completed.
Make edits DVD compatible
Press OK
Unprotected
Protection
Erase disc
Summer holiday
Disc name
Settings for Summer holiday
l If the Disc Settings menu shows the option ‘Make
edits DVD compatible ’, select this option. If the
menu does not show this option, then your
DVD+RW disc is already compatible, and no
conversion is needed.
The maximum number of chapter markers is 99.
When this maximum is reached the on-screen message
‘Too many chapters’ appears. You have to delete some,
before inserting new chapter markers.
You van combine a chapter with the previous chapter in
the current title by deleting the chapter at the beginning
of the current chapter.
l In play mode press
FSS on the remote control
to call up the FSS menu.
l Select ‘Delete chapter marker‘.
l Press OK on the remote control to confirm
‰ ‘Deleting marker’ will appear.
You can delete all chapter markers (manually and
automatically generated) in the current title.
l In play mode press
FSS on the remote control
to call up the FSS menu.
l Select ‘Delete chapter markers‘.
l Press OK on the remote control to confirm
‰ ‘Deleting markers’ will appear.
l In play mode press
FSS on the remote control,
to call up the FSS menu.
l Select ‘Insert chapter marker’.
l Press OK on the remote control to insert a marker.
The basic function of any edit operations is to improve
accessibility and handling of your recordings. For instance:
scenes you do not want to see during playback (e.g.
commercials during a movie) can be marked as chapters
and made hidden. During playback you will see your
recording without the hidden chapters as one sequence.
If one or more titles have been edited (see ‘Favourite
Scene Selection’), then the edits will play on your DVD
recorder, but a DVD player may show the original
versions instead of the edits. You can prepare your
DVD+RW discs so that also a DVD player will show the
edited version. This is not possible with DVD+R discs.
Note:
In between the scenes the picture may freeze for a short moment.
Deleting chapter markers
Inserting chapter markers
Favourite Scene Selection
Making your edits DVD-compatible
Directions For Use
EN 27
English
English
PAUSE
FSS
SLOW
PLAY
FORWARD
NEXT
a
CLEAR
TIMER
SELECT
P
Divide title
Use picture as index
Delete all chapter markers
Delete chapter marker
Current chapter
Insert chapter marker
Press OK
Hidden
Favourite scene selection
48 MANAGING DISC CONTENT
If you want to divide one title into more than two titles,
use the above procedure several times.
The Index Picture Screen will show two titles instead of
one. Both will have the same name. If you want to
change the name, you can do so in the title settings
menu. For one of the two resulting titles, a new index
picture is created.
l Press OK on the remote control to confirm.
‰ ‘Dividing title...’ is shown until the action is
completed. This divide operation cannot be undone.
play
2
PAUSE
FSS
REC/OTR
SLOW
PLAY
FORWARD
NEXT
PREVIOUS
MONITOR
REC/OTR
NEXT
ON/OFF
Any remaining video material that is not overwritten,
which may include the last part of the original title, is
maintained. You can access these titles from the Index
Picture Screen.
The video recording will now be appended from this
point. Video material beyond this point is overwritten.
This may include titles following the current title.
If you want to append a video recording to an earlier
recorded title, do the following.
l On the Index Picture Screen, select the title to
which you want to add a video recording.
l Press 2 PLAY.
l At the point where you want to append the title
press ; PAUSE.
l To monitor the video input you may press
MONITOR.
l Press RECORD (on the recorder) or REC/OTR
(on the remote control).
STOP
REVERSE
PREVIOUS
• Check to make sure that no audio connections are made to amplifier
phono input.
• Check to make sure that analogue input of the amplifier is not
connected to the digital output of the DVD recorder.
• The disc format is not according to the TV set used (PAL/NTSC).
• Check the digital connections.
• Check the settings menu to make sure that the digital output is set to
on.
• Check if the audio format of the selected audio language matches your
receiver capabilities.
• Some operations are not permitted by the disc. Refer to the
instructions in the disc inlay.
Distorted sound from HiFi amplifier
Distorted or black and white picture with
DVD or Video CD disc
No audio at digital output
Recorder does not respond to all
operating commands during playback
of a DVD-Video disc
TROUBLESHOOTING 49
• Ensure the disc label is upwards and that the right disc type is inserted.
• Clean the disc.
• Check if the disc is defective by trying another disc.
• Check if the region code of the disc matches the region code of the
recorder. (pre-recorded DVD discs only). See ‘playing a pre-recorded
DVD-Video disc’.
• Check if Child Lock is activated.
Recorder does not play disc
• Check the disc for fingerprints and clean with a soft cloth, wiping from
centre to edge.
• Sometimes a small amount of picture distortion may appear. This is
not a malfunction.
• Check if the TV set is switched on.
• Check the video connection.
• When the DVD recorder is connected to the TV set via SCART, you
may not see the picture at the DVD recorder after selecting the correct
programme number on your TV set when a timer recording takes place.
• This way, you can still view another device (e.g. a satellite receiver).
• To view the DVD recorder press TV/DVD on the remote control.
No picture
Distorted picture distorted sound
• The DVD recorder may still be in Virgin mode. See ‘First time set-up:
virgin mode’.
• Otherwise disconnect and reconnect the DVD recorder from the
mains.
• If this does not solve the problem, check if the remote control still
works. If so, the recorder is probably in trade mode.
Disconnect the recorder from the mains and reconnect it while holding
/ OPEN/CLOSE and 9 STOP pressed.
• The remote control may be configured for a second DVD recorder.
Hold SELECT+1 pressed simultaneously to revert to DVD recorder 1.
• Aim the remote control directly at the sensor on the front of the
recorder.
• Avoid all obstacles which may interfere with the signal path.
• Inspect or replace the batteries.
Remedy
Keys on the DVD recorder do not work
The recorder does not respond to
the remote control
Symptom
DVDR980-985 /0X1
1
l On the Index Picture Screen, select the title you
want to divide.
l Press 2 PLAY.
l Go to the point where you want to divide the title
and press ; PAUSE.
l Press
FSS.
‰ The Favourite Scene Selection menu is shown.
l Select ‘Divide title’.
STOP
REVERSE
REC/OTR
This function is only available on DVD+RW discs.
On a DVD+RW disc you split one title into two
separate titles. (On DVD+R this is not possible.)
If it appears that the DVD recorder is faulty, first consult this checklist. It may be that something has been overlooked.
Under no circumstances attempt to repair the system yourself; this will invalidate the warranty. Look for the specific
symptom(s). Then perform only the actions listed to remedy the specific symptom(s).
3.
PREVIOUS
Append recording
Dividing a title
Troubleshooting
EN 28
Directions For Use
English
English
• Check if the maximum number of titles has been reached (message:
‘too many titles’ on screen). If so, delete a title next to a free space.
• Check if the disc is write protected. If so, unlock the disc in the disc
settings menu (message: ‘Disc locked’ on screen).
• Check if the (DVD+R) disc has been finalized. If so, no new titles can
be recorded anymore.
• Clean the disc. The recording was most probably done correctly.
• A write error has occured, but it could be corrected. No user action
is required.
• A write error has occured from which the recorder could not
recover. Inspect the disc and clean it if necessary (refer to ‘Intoduction Cleaning discs’ for cleaning instruction). Record (overwrite) again over
the same part of the disc to see if the problem is solved
• A disc might be corrupted because of dust, scratches or fingerprints.
If the disc cannot be accessed anymore, use the back-up disc erase
procedure to repair it. Proceed as follows:
1. Clean the disc.
2. Put disc in the drawer (do not close the tray).
3. Press and hold CLEAR for several seconds until the tray closes.
• When the TV set does not automatically detect the dual-language
signal,use left/right audio balance on the TV set to amplify the one or
the other language.
1. Open the tray while leaving the disc in.
2. Hold CLEAR pressed for around 5 seconds until the tray closes. The
disc is technically not yet erased but you can start a new recording like
on a blank disc.
No new title can be recorded
Service codes on the display
‘Disc warning’ message on screen
‘Disc error’ message on screen
Disc errors
Two languages are ‘mixed’ when
recording from a stereo VCR
The disc cannot be erased because the
Index Picture Screen does not appear
• To revert the disc to the original state, follow the same procedure
with the 1 key on the remote control.
l Unplug the power cord of the recorder.
l Press the 2 PLAY key and keep them pressed
while you plug the recorder.
‰ On the display the message ‘BUSY’ appears
together with a counter. This counter indicates the
termination of the test when zero is reached.
‰ After a few minutes the message on the local
display changes over from ‘BUSY’ to ‘FAIL’ or to
‘PASS’.
‰ If the message ‘FAIL’ appears on the display,
there is apparently a failure in your recorder and
your recorder should be repaired.
l Consult your dealer or the Philips Customer Care
Centre for the nearest Service Repair Shop in your
country. The phone number is given in your
warranty booklet.
l If the message ‘PASS’ appears on the display, there
is apparently no failure in your recorder, in this case
the failure can be caused by incorrect interpretation
of the operating instructions or a wrong disc is used
or your recorder is not correctly connected. In this
case you should consult your dealer or the Philips
Customer Care Centre for further assistance in
solving the problem.
l If the problem remains, then consult your Philips
Customer Care Centre.
Instructions
You can operate the Diagnosis Programme by following
the instructions step by step.
If the recorder is still faulty you can start the Diagnosis
Programme in the recorder.
Diagnosis programme
TROUBLESHOOTING 51
After a power interruption during recording, the Index
Picture Screen will may not match with the actual video
content on the disc. The last recorded title may be lost.
Because of the Variable Bit Rate, a title map take up less
or more space than the overwritten title, even though
the duration is the same. As a result, a part of the
original title may remain, or a part of the next title may
be lost. The maximum deviation is five minutes.
When using manual recording, the DVD recorder will
warn before adapting the format of the disc or removing
non-video data. When using timer recording however,
the DVD recorder will always start to record, unless the
disc is write-protected. Menus, edits and other data
recorded on a different device (e.g. a PC) may be lost.
A DVD+RW video disc that has been recorded on a
different type or brand of recorder can be played, but
may not provide all features commonly available to
DVD+RW discs, such as the on-screen disc bar, the disc
settings menu, the title settings menu, and editing.
Refer to ‘Adapt disc format’. If the disc is writeprotected, the status cannot be changed.
DVD+RW and DVD+R discs may not play on certain
DVD Video players.
System limitations
DVDR980-985 /0X1
3.
50 TROUBLESHOOTING
• There are DVD Players that will not play recordings made with a DVD
Recorder. With a special procedure the recorder will solve this problem
for some players. Proceed as follows:
1. Put the disc in the drawer (do not close the tray)
2. Press and hold the 2 key on the remote control for several seconds
until the tray closes. The disc is now modified.
3. If the change has no effect, you may perform the same procedure
with the 3 key on the remote control.
A DVD+RW disc does not play
on a certain DVD player
Note :
Modifying the disc can solve the problem for a specific player model, but
playback in other DVD players may no longer be possible.
It is therefore recommended to use this procedure carefully and only when
needed.
• Press 9 STOP to exit the Index Picture Screen, then press 2 PLAY.
A DVD player shows the Index Picture
Screen but does not react to
the 2 PLAY key
The Index Picture Screen does not appear • Take out the disc. Clear the disc. Insert the disc.
but the titles on the disc can still be played Choose ‘Adapt to own disc format’ (See ‘User Preferences - Features).
• Make sure that the recorder is switched to standby before the timer
starts.
The recorder does not record
timer programme
Directions For Use
EN 29
English
Audio Coding 3, also known as Dolby Digital. Multi-channel digital audio
compression system from Dolby Labs.
Audio/Video
A part of a title.
A graphical representation of the contents of a (DVD+RW) disc.
An arrow indicating the current playback/recording position on the
DVD+RW disc, displayed on the ‘disc bar’.
Digital Theater System. A high-end Multi-channel audio compression
format.
Digital Video. A camcorder format for high-quality video, different from
MPEG. It is converted into MPEG 2 Video when recorded on DVD+RW
Digital Versatile Disc
DVD+Recordable. The write-once disc standard used by the DVD
recorder.
DVD+ReWritable. One of the disc standards used by the DVD
recorder.
If your TV set and your video recorder are equipped with this feature,
they can exchange information to adjust certain settings to each other,
such as the TV channel order and other user preferences.
Favorite Scene Selection. see ‘Managing disc content’.
Also known as ‘FireWire’ and ‘IEEE 1394’. A cable for transfer of highbandwidth digital signals, as used by Digital Video camcorders.
A screen that gives an overview of a DVD+RW disc, wih ‘index
pictures’ that each represent a recording.
Motion Picture Experts Group. A collection of compression systems for
digital audio and video.
A system that enables easy programming of a video recorder via a TV
set. Also see EasyLink.
System for reception of digital stereo TV sound.
See TV system.
On-screen Display. The ‘user interface’ by which you can control the
DVD recorder via the TV screen.
One-Touch Recording. With this feature you can easily start a
recording (by pushing just one button) and select the switch-off time in
intervals of 30 minutes.
AC-3
A/V
Chapter
Disc Bar
Disc Pointer
DTS
DV
DVD
DVD+R
DVD+RW
EasyLink
FSS
i.LINK
Index Picture Screen
MPEG
NEXTVIEW Link
NICAM
NTSC
OSD
OTR
3.
DVDR980-985 /0X1
English
52 GLOSSARY
Explanation
Term
This section explains most important terms, abbreviations, and acronyms used in this document.
Glossary
EN 30
Directions For Use
English
CLEAR
MUTE
TIMER
SELECT
CH
NEXT
CH +
CH 0-9
B
-
FORWARD
PLAY
SLOW
FSS
REC/OTR
PAUSE
ON/OFF
SCAN
Y
AUDIO
A/CH
CH
057
036
490
244
119
057
291
243
398
321
207
244
064
036
036
244
245
233
136
478
233
309
BSR . . . . . . . . . . . . . . . . . . . 321
BTC . . . . . . . . . . . . . . . . . . 245
Bang & Olufsen . . . . . . . . . . 592
Basic Line . . . . . . . . . . 036, 245
Baur. . . . . . . . . . . 064, 037, 581
Baysonic . . . . . . . . . . . . . . . 207
Beaumark . . . . . . . . . . . . . . 205
Beko . . . . . . . . . . . . . . . . . . 397
Belcor . . . . . . . . . . . . . . . . . 046
Bell & Howell . . . . . . . . . . . 181
Beon . . . . . . . . . . . . . . . . . . 064
Binatone . . . . . . . . . . . . . . . 244
Blaupunkt . . . . . . . . . . . . . . 581
Blue Sky . . . . . . . . . . . . . . . 245
Blue Star . . . . . . . . . . . . . . . 309
Boots . . . . . . . . . . . . . . . . . 244
Bradford . . . . . . . . . . . . . . . 207
Brandt. . . . . . . . . . . . . . . . . 136
Britannia . . . . . . . . . . . . . . . 243
Brockwood . . . . . . . . . . . . . 046
Broksonic . . . . . . . . . . 263, 490
Bush . . 064, 398, 245, 036, 063,
. . . . . . . . . . . . . . 309, 321, 401
CCE . . . . . . . . . . . . . . 064, 244
CS Electronics. . . . . . . . . . . 243
PAUSE
FSS
REC/OTR
SLOW
PLAY
FORWARD
NEXT
ON/OFF
VOL
CLEAR
MUTE
TIMER
SELECT
CH
CXC . . . . . . . . . . . . . . . . . . 207
Candle. . . . . . . . . . . . . 057, 083
Carnivale. . . . . . . . . . . . . . . 057
Carrefour . . . . . . . . . . . . . . 063
Carver . . . . . . . . . . . . . . . . 081
Cascade . . . . . . . . . . . . . . . 036
Cathay . . . . . . . . . . . . . . . . 064
Celebrity. . . . . . . . . . . . . . . 027
Centurion . . . . . . . . . . . . . . 064
Cimline . . . . . . . . . . . . . . . . 036
Cineral . . . . . . . . . . . . 478, 119
Citizen . . . . 083, 057, 066, 087,
. . . . . . . . . . . . . . . . . . . . . . 119
Clarivox . . . . . . . . . . . . . . . 064
Clatronic. . . . . . . . . . . . . . . 397
Concerto . . . . . . . . . . . . . . 083
Condor . . . . . . . . . . . . 347, 397
Contec. . . . . 036, 063, 207, 243
Craig . . . . . . . . . . . . . . . . . . 207
Crosley . . . . . . . . . . . . . . . . 081
Crown . . . . 397, 036, 064, 066,
. . . . . . . . . . . . . . . . . . 207, 445
Crystal . . . . . . . . . . . . . . . . 458
Curtis Mathes . . . 087, 057, 066,
. . . . . . 074, 078, 081, 083, 120,
. . . . . . . . . . 172, 181, 193, 478
Cybertron. . . . . . . . . . . . . . 245
Daewoo . . . 119, 046, 401, 478,
. . . . . . . . . . . . . . 036, 064, 066
Dainichi. . . . . . . . . . . . . . . . 245
Dansai . . . . . . . . . . . . . . . . . 064
Dayton . . . . . . . . . . . . . . . . 036
Daytron . . . . . . . . . . . . . . . 046
Decca . . . . . . . . . . . . . 064, 099
Denon. . . . . . . . . . . . . . . . . 172
Dixi . . . . . . . . . . . . . . . 036, 064
Dual Tec . . . . . . . . . . . . . . . 244
Dumont. . . . . . . . 044, 046, 097
Electroband. . . . . . . . . . . . . 027
Elin . . . . . . . . . . . . . . . . . . . 064
Elite. . . . . . . . . . . . . . . 245, 347
Elta . . . . . . . . . . . . . . . . . . . 036
Emerson . . . 263, 207, 205, 206,
. . . . . . 490, 309, 066, 046, 181
Envision. . . . . . . . . . . . . . . . 057
Erres . . . . . . . . . . . . . . 039, 064
Expert . . . . . . . . . . . . . . . . . 233
Ferguson . . . . . . . . . . . 136, 064
Fidelity . . . . . . . . . . . . . . . . 243
Finlux . . 064, 132, 097, 099, 206
l Switch on your television set.
l Press and hold the RETURN and SELECT key
simultaneously for at least 3 seconds.
l Release both keys.
l Point the remote control to your TV set.
l Press and hold the B STANDBY key.
‰ Your TV set switches off when the right code is
found.
l When your TV set switches off, immediately release
the B STANDBY key.
‰ Your remote control is now re-programmed.
l This complete procedure may take up to 2 minutes.
STOP
REVERSE
PREVIOUS
MONITOR
Alternative procedure:
If your TV set does not respond to the remote control,
you can re-programme your remote control. Below you
will find a list of all available remote control codes for
various TV brands. The following procedure reprogrammes your remote control:
l Look up the set-up code for your TV set in the
code list below.
l Press and hold the RETURN and SELECT key
simultaneously for at least 3 seconds.
l Release both keys.
l Enter, within 30 seconds, the correct three-digit
code with the digit keys 0-9.
l If the selected code does not work with your TV
set, or if the brand of your TV set is not in the list,
try out the codes one after the other.
Firstline . . . . 348, 036, 243, 244,
. . . . . . . . . . . . . . . . . . . . . . 321
Fisher . . . . . . . . . 244, 181, 397
Flint. . . . . . . . . . . . . . . . . . . 482
Formenti . . . . . . . . . . . 347, 064
Frontech . . . . . . . . . . . 458, 291
Fujitsu . . . . . . . . . 206, 099, 233
Funai . . 321, 198, 206, 207, 291
Futuretech . . . . . . . . . . . . . 207
GE. . . . 048, 074, 078, 205, 478,
. . . . . . . . . . . . . . . . . . 120, 309
GEC . . . . . . . . . . 099, 064, 244
GPM . . . . . . . . . . . . . . . . . . 245
Geloso . . . . . . . . . . . . . . . . 036
Genexxa . . . . . . . . . . . . . . . 245
Gibralter . . . . . . . 044, 046, 057
GoldStar . . . 064, 046, 057, 205,
. . . . . . . . . . . . . . 244, 083, 136
Goodmans . . . . . 064, 099, 206,
. . . . . . . . . . 398, 063, 244, 401
Gorenje. . . . . . . . . . . . . . . . 397
Gradiente . . . . . . . . . . 083, 080
Granada . . . . . . . . 064, 099, 244
Grandin . . . . . . . . . . . . . . . . 309
Grundig . . . . . . . . 097, 581, 064
Grunpy . . . . . . . . . . . . 206, 207
HCM . . . . . . . . . . . . . . 036, 309
Hallmark . . . . . . . . . . . . . . . 205
Hanseatic. . . . . . . . . . . 064, 347
Harley Davidson . . . . . . . . . 206
Harman/Kardon . . . . . . . . . 081
Harvard. . . . . . . . . . . . . . . . 207
Hinari . . . . . 036, 063, 064, 245,
. . . . . . . . . . . . . . . . . . . . . . 206
Hisawa. . . . . . . . . . . . . 309, 482
Hitachi. . . . . 136, 071, 172, 244,
. . . . . . . . . . . . . . 063, 083, 132
Huanyu . . . . . . . . . . . . 243, 401
Hypson . . . . . . . . 291, 064, 309
ICE . . . . . . . . . . . 244, 291, 398
ICeS . . . . . . . . . . . . . . . . . . 245
ITS . . . . . . . . . . . . . . . . . . . 398
Imperial . . . . . . . . . . . . 445, 397
Indiana. . . . . . . . . . . . . . . . . 064
Infinity . . . . . . . . . . . . . . . . . 081
Inno Hit. . . . . . . . . . . . . . . . 099
Innova . . . . . . . . . . . . . . . . . 064
Inteq . . . . . . . . . . . . . . . . . . 044
Interfunk . . . . . . . . . . . . . . . 064
Intervision . . 064, 129, 244, 291
Isukai. . . . . . . . . . . . . . . . . . 245
JBL . . . . . . . . . . . . . . . . . . . 081
JCB . . . . . . . . . . . . . . . . . . . 027
JVC . . . . . . . 080, 063, 398, 680
KEC . . . . . . . . . . . . . . . . . . 207
KTV . . . . . . . 207, 244, 057, 066
Kaisui . . 245, 244, 036, 243, 309
Kamp . . . . . . . . . . . . . . . . . 243
Kapsch . . . . . . . . . . . . . . . . 233
Kawasho . . . . . . . . . . . . . . . 243
Kendo . . . . . . . . . . . . . . . . . 064
Kenwood. . . . . . . . . . . 057, 046
Kingsley. . . . . . . . . . . . . . . . 243
Korpel. . . . . . . . . . . . . . . . . 064
Koyoda . . . . . . . . . . . . . . . . 036
LG. . . . . . . . . . . . . . . . . . . . 083
LXI . . . . 181, 074, 081, 183, 205
Leyco . . . . . . 099, 064, 291, 321
Liesenk & Tter . . . . . . . . . . 064
Luma . . . . . . . . . . . . . . . . . . 233
Luxman . . . . . . . . . . . . . . . . 083
M Electronic . . . . 132, 244, 036,
. . . . . . . . . . . . . . 064, 136, 401
MGA . . . . . . 177, 046, 057, 205
MTC. . . 087, 057, 046, 083, 243
Magnadyne . . . . . . . . . . . . . 129
Magnafon. . . . . . . . . . . . . . . 129
Magnavox. . . 081, 057, 063, 206
Manesth . . . . . . . . 347, 244, 291
Marantz . . . . . . . . 064, 081, 057
Mark . . . . . . . . . . . . . . . . . . 064
Matsui . 036, 064, 244, 398, 062,
. . . . . . . . . . . . . . 063, 099, 321
Matsushita . . . . . . . . . . 277, 677
Mediator . . . . . . . . . . . 039, 064
Megatron. . . . . . . . . . . 172, 205
Memorex . . 205, 036, 083, 177,
. . . . . . . . . . . . . . 181, 277, 490
Midland . . . . 044, 066, 074, 078
Minerva . . . . . . . . . . . . 097, 581
Minutz . . . . . . . . . . . . . . . . . 048
Mitsubishi . . 063, 135, 177, 205,
. . . . . . . . . . . . . . . . . . 046, 120
Mivar. . . . . . . . . . . . . . . . . . 243
Motorola . . . . . . . . . . . . . . . 120
Multitech . . . 036, 129, 207, 243,
. . . . . . . . . . . . . . . . . . . . . . 244
NAD . . . . . . . . . . 183, 193, 205
NEC . . . 057, 063, 046, 083, 482
NEI . . . . . . . . . . . . . . . 064, 458
NTC . . . . . . . . . . . . . . . . . . 119
Neckermann . . . . . . . . 064, 581
Nesco . . . . . . . . . . . . . . . . . 206
Netsat . . . . . . . . . . . . . . . . . 064
Nikkai . 064, 062, 245, 099, 243,
. . . . . . . . . . . . . . . . . . . . . . 291
Nikko . . . . . . . . . 205, 057, 119
Nobliko. . . . . . . . . . . . . . . . 129
Nordmende . . . . . . . . . . . . 136
Onwa . . . . . . . . . . . . . . . . . 207
Optimus. . . . 277, 193, 181, 677
Optonica . . . . . . . . . . . 120, 192
Orion . 321, 490, 064, 206, 263,
. . . . . . . . . . . . . . . . . . 347, 348
Osaki . . . . . . 099, 244, 245, 291
Oso. . . . . . . . . . . . . . . . . . . 245
Osume . . . . . . . . . . . . . . . . 099
Otto Versand . . . 064, 037, 063,
. . . . . . . . . . . . . . 244, 347, 581
Palladium . . . . . . . . . . . 397, 445
Panama . . . . . . . . . . . . 244, 291
Panasonic . . . . . . . 078, 277, 677
Pathe Cinema . . . . . . . 347, 243
Pausa. . . . . . . . . . . . . . . . . . 036
Penney . . . . 074, 087, 057, 048,
. . . . . . . . . . 205, 078, 066, 046,
. . . . . . . . . . . . . . . . . . 083, 183
Perdio . . . . . . . . . . . . . . . . . 347
Philco . . 172, 046, 057, 081, 490
Philips. . 064, 039, 081, 401, 581
Phonola . . . . . . . . . . . . 064, 039
Pilot . . . . . . . . . . . 046, 057, 066
Pioneer . . . . . . . . . . . . 136, 193
Portland. . . . . . . . 046, 066, 119
Prism. . . . . . . . . . . . . . . . . . 078
Profex . . . . . . . . . . . . . . . . . 036
Proline . . . . . . . . . . . . . . . . 348
Proscan . . . . . . . . . . . . . . . . 074
Protech . . . . 064, 129, 036, 458,
. . . . . . . . . . . . . . 244, 291, 445
Proton. . . . . . . . . . . . . . . . . 205
Pulsar . . . . . . . . . . . . . 044, 046
Pye . . . . . . . . . . . . . . . . . . . 039
Quasar . . . . . 078, 277, 192, 677
Quelle . . . . . 064, 097, 037, 581
Questa . . . . . . . . . . . . . . . . 063
R-Line . . . . . . . . . . . . . . . . . 064
RBM . . . . . . . . . . . . . . . . . . 097
RCA . . . 074, 046, 078, 117, 120
Radio Shack . . . . 192, 207, 057,
. . . . . . . . . . 205, 066, 181, 046,
. . . . . . . . . . . . . . . . . . 074, 083
Radiola . . . . . . . . . . . . 064, 039
Rank Arena . . . . . . . . . . . . . 063
Realistic. . . . 192, 207, 181, 057,
. . . . . . . . . . 066, 205, 046, 083
Revox . . . . . . . . . . . . . . . . . 064
Rex . . . . . . . . . . . . . . . 233, 291
Rhapsody. . . . . . . . . . . . . . . 243
Roadstar . . . 036, 291, 245, 445
Runco . . . . . . . . . . . . . 044, 057
SBR . . . . . . . . . . . . . . . 039, 064
SEG . . . . . . . . . . . 244, 063, 291
SEI . . . . . . . . . . . . 129, 037, 321
SKY . . . . . . . . . . . . . . . . . . . 064
SSS . . . . . . . . . . . . . . . 046, 207
Saba. . . . . . . . . . . . . . . . . . . 136
Saisho . . . . . . . . . 036, 291, 458
Sambers . . . . . . . . . . . . . . . 129
Sampo . . . . . . . . . . . . . 057, 066
Samsung . . . 064, 046, 205, 244,
. . . . . . . . . . 291, 397, 036, 057,
. . . . . . . . . . 066, 083, 087, 117
Samsux . . . . . . . . . . . . . . . . 066
Sandra . . . . . . . . . . . . . . . . . 243
Sansei . . . . . . . . . . . . . . . . . 478
Sansui . . . . . . . . . . . . . . . . . 490
Sanyo . . . . . . . . . . 181, 063, 099
Schneider. . . . . . . 064, 245, 398
Scimitsu. . . . . . . . . . . . . . . . 046
Scotch . . . . . . . . . . . . . . . . . 205
Scott. . . 263, 046, 205, 206, 207
Sears . . 181, 083, 183, 074, 081,
. . . . . . . . . . . . . . 198, 205, 206
Seleco . . . . . . . . . . . . . . . . . 233
Semivox . . . . . . . . . . . . . . . 207
Semp . . . . . . . . . . . . . . . . . . 183
Sentra . . . . . . . . . . . . . . . . . 062
Sharp . . . . . . 120, 192, 063, 066
Shogun . . . . . . . . . . . . . . . . 046
Shorai . . . . . . . . . . . . . . . . . 321
Siarem . . . . . . . . . . . . . . . . . 129
Siemens . . . . . . . . . . . . 581, 064
Silver . . . . . . . . . . . . . . . . . . 063
Sinudyne . . . . . . . 129, 037, 321
Sonoko . . . . . . . . . . . . 036, 064
Sontec . . . . . . . . . . . . . . . . . 064
Sony. . . . . . . . . . . 037, 063, 027
3.
APPENDIX 55
Soundesign. . . . . . 205, 206, 207
Soundwave . . . . . . . . . 064, 445
Squareview . . . . . . . . . . . . . 198
Standard . . . . . . . 244, 245, 036
Starlite. . . . . . . . . . . . . . . . . 207
Stern . . . . . . . . . . . . . . . . . . 233
Sunkai . . . . . . . . . . . . . 321, 348
Supra. . . . . . . . . . . . . . . . . . 083
Supreme . . . . . . . . . . . . . . . 027
Susumu . . . . . . . . . . . . . . . . 245
Sylvania . . . . . . . . . . . . 081, 057
Symphonic. . . . . . . . . . . . . . 198
Sysline . . . . . . . . . . . . . . . . . 064
TMK . . . . . . . . . . . . . . 083, 205
Tandy. . . . . . 245, 099, 244, 120
Tashiko . . . . . . . . . . . . 063, 244
Tatung . . . . . . . . . 099, 244, 064
Tec . . . . . . . . . . . . . . . . . . . 244
Technema . . . . . . . . . . . . . . 347
Technics . . . . . . . 078, 277, 677
Technol Ace . . . . . . . . . . . . 206
Techwood . . . . . . . . . . 078, 083
Teknika . . . . 081, 206, 207, 046,
. . . . . . . 066, 119, 083, 087, 177
Telefunken. . . . . . . . . . 136, 083
Telemeister . . . . . . . . . . . . . 347
Teletech . . . . . . . . . . . . . . . 036
Teleton . . . . . . . . 233, 063, 244
Tensai . . . . . . . . . 245, 321, 347
Texet. . . . . . . . . . . . . . 243, 245
Thomson. . . . . . . . . . . . . . . 136
Thorn . . . . . . . . . 064, 062, 099
Tomashi . . . . . . . . . . . . . . . 309
Toshiba . . . . 062, 183, 063, 097,
. . . . . . . . . . . . . . . . . . 087, 181
Totevision . . . . . . . . . . . . . . 066
Uher . . . . . . . . . . . . . . 233, 347
Ultravox . . . . . . . . . . . . . . . 129
Universum . . 132, 064, 291, 397
Vector Research . . . . . . . . . 057
Vestel . . . . . . . . . . . . . . . . . 064
Victor . . . . . . . . . . . . . . . . . 080
Videotechnic . . . . . . . . . . . . 244
Vidikron . . . . . . . . . . . . . . . 081
Vidtech . . . . . . . . 046, 063, 205
Vision . . . . . . . . . . . . . . . . . 347
Waltham . . . . . . . . . . . . . . . 244
Wards . . . . . 081, 192, 205, 046,
. . . . . . . . . . 048, 057, 083, 206
Watson . . . . . . . . . . . . 347, 064
Watt Radio . . . . . . . . . . . . . 129
Wega . . . . . . . . . . . . . . . . . 063
White Westinghouse . . . . . 347,
. . . . . . . . . . . . . . 064, 243, 490
Yamaha . . . . . . . . . . . . 046, 057
Yoko . . . . . . 244, 064, 291, 458
Zanussi . . . . . . . . . . . . . . . . 233
Zenith . . . . . . . . . 044, 119, 490
DVDR980-985 /0X1
54 APPENDIX
AOC . . . . . . . . . . . . . . 046,
Acura . . . . . . . . . . . . . . . . .
Admiral . . . . . . . . . . . . 120,
Adyson . . . . . . . . . . . . . . . .
Aiko . . . . . . . . . . . . . . . . . .
Akai . . . . . . . . . . . . . . . . . .
Akura . . . . . . . . . . . . . 245,
Alaron . . . . . . . . . . . . . 206,
Alba . . . 064, 036, 245, 063,
Allorgan . . . . . . . . . . . . . . .
America Action. . . . . . . . . .
Amplivision . . . . . . . . . . . . .
Amstrad. . . . 198, 398, 036,
Anam . . . . . . . . . . . . . 207,
Anitech . . . . . . . . . . . . . . . .
Arcam . . . . . . . . . . . . . 243,
Asuka . . . . . . . . . . . . . . . . .
Atlantic . . . . . . . . . . . . . . . .
Audiosonic . . . . . . . . . 064,
Audiovox. . . . . . . 119, 207,
Autovox . . . . . . . . . . . . . . .
BPL . . . . . . . . . . . . . . . . . . .
REPEAT
REPEAT
DIM
SUBTITLE
Z
ANGLE
MUTE
a
ZOOM
T/C
VOL
next TV programme number
previous TV programme number
choose TV channel
switch TV set to standby
Remote control set-up codes
for television
STOP
REVERSE
PREVIOUS
MONITOR
Some other keys normally operate the DVD recorder,
but will operate the TV set when you keep the button
on the side of the remote control pressed:
- VOL+ increase TV volume
- VOL - decrease TV volume
- c
mute TV
VOL
Your DVD recorder remote control can transmit
several commands to TV sets of different brands.
The following keys will always operate the TV set:
Using your DVD recorder
remote control with your TV set
Appendix
Directions For Use
EN 31
English
English
56 APPENDIX
Italy
tel: 800-820026 (Toll Free)
Ireland
tel: 353-1-7640292
Greece
tel: 30-0-0800-3122 1280
Germany
tel: 49-0-180-535 6767
France
tel: 33-1-825 889 789
Finland
tel: 358-09-6158 0250
Denmark
tel: 808 82 814
Belgium
tel: 32-2-070 222 303
Poland
tel: 48-22-571 0571
United Kingdom
tel: 44-0-208 665 6350
Switzerland
tel: 0844 800 544
Sweden
tel: 08 5985 2250
Spain
tel: 34-902-113 384
Portugal
tel: 352-1-4163063
Norway
tel: 22-748 250
DVDR980-985 /0X1
Netherlands
tel: 0900-8406
Luxembourg
tel: 352-404061215
3.
Austria
tel: 43-0810 001 203
Philips Customer Care Centers
Personal Notes:
EN 32
Directions For Use
Mechanical Instructions
DVDR980-985 /0X1
4.
EN 33
4. Mechanical Instructions
4.1
Service Positions
4.1.1
Front
DVIO 2
Front
Figure 4-4
4.1.3
Figure 4-1
4.1.2
DVIO board
To put the DVIO board in a service position, an extender board
must be used. This extender board can be ordered with
codenumber 3104 128 07770.
Digital board
After demounting of DVIO board, the top side of the digital
board is in reach. To reach the bottom side of the digital board,
the DVDR module must be demounted together with the digital
board. Connected to each other, the assembly can be set in a
service position. In this position, the bottom side of the digital
board and the servo board are in reach to be serviced.
Digital 1
DVIO Extender
Figure 4-5
Figure 4-2
Digital 2
DVIO 1
Figure 4-6
Figure 4-3
EN 34
4.1.4
4.
DVDR980-985 /0X1
Mechanical Instructions
Analog board
To put the analog board in service position, demount the
assembly of analog board and backplate as follows:
1. Remove 3 screws from the backplate to the frame
2. Remove the screw from the backplate to the mains inlet of
the power supply
3. Remove the screw of the analog board to the frame
4. Release the snaps of the 4 spacers of the analog board to
the frame.
Turn the assembly of the backplate and the analog board
against the loader.
Analog Europe
Figure 4-7
Analog NAFTA
Figure 4-8
Mechanical Instructions
4.
EN 35
Exploded View of the Front Assembly
FRONT DV IN
FRONT AV IN
DISPLAY
Front EV
IR/STBY
4.2
DVDR980-985 /0X1
CL 26532011_019.eps
160102
Figure 4-9
Display board 1001
⇒ Remove 8 screws 31 → 38
(board → front)
⇒ demount the board
⇒
demount the board
⇒
demount the board
FRONT AV Board1007
⇒ remove screws 48+49
(board → front)
backplate)
release the snaps of 4 spacers
185 → 188 (board → frame)
⇒ demount the board
⇒
IR/STBY Board 1001
⇒ remove screws 41+42
(board → front)
remove 4 screws 75 → 78
(front assy → frame 181)
unlock the front from the
frame by releasing
successively 6 snaps
(1 on the left, 2 in the middle,
1 on the right and 2 in the
bottom of the frame. The
snaps in the bottom can be
released inside the set
via the holes in the bottom.
Analog board 1003
⇒ remove the connections
⇒ remove 1 screw(215)
(board → frame)
⇒ remove screws (cinches →
⇒
Remove the connections
⇒ Remove 4 screws 207 → 210
(Digital board → frame 181)
⇒ demount the board.
Digital board 1001
⇒
Remove 2 screws 217 and 218
(DVIO board → frame 181)
⇒ Release the snaps of 2 spacers
(DVIO board → Digital board)
⇒ demount carefully the board.
(board to board connection to
the Digital board)
DVIO board 1005 (DVDR985)
↑
↓
demounting
mounting
⇒ Release the snaps of 2 spacers
183 and 184 (board → frame)
⇒ Demount the board
Switched Operating Power supply 1002
⇒ Remove the connections
⇒ Remove screws 204 → 206
(board → frame)
⇒ Remove screw 268
(mains inlet → backplate)
Via a hole in the frame and by way of a
screwdriver, it is possible to unlock the tray.
Push the white pin of the slider at the bottom
side of the loader to the left.
⇒ Open the unlocked tray.
⇒
In case the loader is defective and cannot be
opened electrically, you can open the tray
as follows:
Manually removal of tray front 65
⇒
⇒
the tray front 65
Remove 4 screws
200 → 203 (loader 81→ frame 181)
Demount the DVDR loader
DVDR LOADER 81
⇒ Remove the connections
⇒ Remove 4 screws (192 → 195)
(air filter 198 → loader 81)
⇒ Remove screw 196
(air filter inlet 191 → frame 181)
⇒ Remove air filter assy
⇒ Open the tray and remove
DVDR980-985 /0X1
FRONT DV Board 1006(DVDR985)
⇒ Remove screw 17
(board → front)
⇒ demount the board
⇒
⇒
Front assy
⇒ open the tray and remove the
tray front 65
rearside to remove
Cover 151
⇒ Remove 9 screws
171→174 at both sides
175→179 at the rearside
⇒ Lift the cover at the
4.
See exploded view of front assy
See exploded view for item numbers
4.3
DISMANTLING INSTRUCTIONS
EN 36
Mechanical Instructions
Dismantling Instructions
Dismantling Instructions
Figure 4-10
CL 26532011_020.eps
160102
Mechanical Instructions
4.
EN 37
Exploded View of the Set
DVIO PCB
DIGITAL PCB
I/O ANALOG PCB
SOPS
Complete Set EV
DVDR LOADER
4.4
DVDR980-985 /0X1
CL 26532011_021.eps
160102
Figure 4-11
EN 38
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
5. Diagnostic Software and Faultfinding Trees
Due to the complexity of the DVD recorder, the time to find a
defect in the recorder can become long. To reduce this time,
the recorder has been equipped with Diagnostic and Service
software (DS). The DS offers functionality to diagnose the
DVDR hardware and tests the following:
• Interconnections between components
• Accessibility of components
• Functionality of the audio and video paths
This functionality can be accessed via several interfaces:
1. End user/Dealer script interface
2. Player script interface
3. Menu and command interface
5.1
End User/Dealer Script Interface
5.1.1
Description
5.1.2
Contents
Unplug the power cord
Hold key pressed
while you plug the recorder
During the test, the following display
is shown: the counter counts down
from the number of nuclei to be run
before the test finishes. Example:
SET O.K.?
NO
YES
The End user/Dealer script interface gives a diagnosis on a
stand alone DVD recorder; no other equipment is needed.
During this mode, a number of hardware tests (nuclei) are
automatically executed to check if the recorder is faulty. The
diagnosis is simply a "fail" or "pass" message. If the message
"FAIL" appears on the display, there is apparently a failure in
the recorder. If the message "PASS" appears, the nuclei in this
mode have been executed successfully. There can be still a
failure in the recorder because the nuclei in this mode don't
cover the complete functionality of the recorder.
To exit DEALER SCRIPT, unplug the power cord
CL 16532095_068.eps
150801
Figure 5-1
The End use/Dealer script executes all diagnostic nuclei that
do not need any user interaction and are meaningful on a
standalone DVD recorder. The nuclei called in the End user/
Dealer script are the following:
Counter
Nucleus Name
Description
22
104
HostdSdramWrR
checks all memory locations of the 4MB SDRAM
21
106
HostdDramWrR
checks all the DRAM connected to the microprocessor of the digital board
20
123
HostdI2cNvram
checks the data line (SDA) and the clock line (SCL) of the I2C bus between the host decoder
and NVRAM
19
202
SAA7118I2c
checks the interface between the Host I2C controller and the AVENC SAA7118 Video Input
Processor
18
200
VideoEncI2c
checks the interface between the host I2C controller and Empress SAA6752
17
207
AudioEncI2c
checks the I2C connection between the host decoder and Empress SAA6752
16
204
AudioEncAccess
tests the HIO8 interface lines between the host decoder and the audio encoder
15
203
AudioEncSramAccess
checks the access of the SRAM by the audio encoder (address and data lines).
14
205
AudioEncSramWrR
tests the SRAM connected to the audio encoder
13
206
AudioEncInterrupt
tests the interrupt line between the host decoder and the audio encoder
12
300
VsmAccess
checks whether the VSM interrupt controllers and DRAM are accessible
11
303
VsmInterrupt
checks both interrupt lines between the VSM and the host decoder
10
302
VsmSdramWrR
tests the entire SDRAM of the VSM
9
1400
Clock11_289MHz
switches the A_CLK of the micro clock to 11.2896 MHz
8
1401
Clock12_288MHz
switches the A_CLK of the micro clock to 12.288 MHz
7
601
BeS2Bengine
checks the S2B interface with the Basic Engine by sending an echo command
6
500
DisplayEcho
checks the interface between the host processor and the slave processor on the display
board
5
700
AnalogueEcho
checks the interface between the host processor and the microprocessor on the analogue
board
4
711
AnalogueNvram
checks the NVRAM on the analogue board
3
706
AnalogueTuner
checks whether the tuner on the analogue board is accessible
2
901
LoopAudioUserDealer
This nucleus tests the components on the audio signal path The host decoder
- The analogue board
- The audio encoder
- The VSM
On the analogue board the audio is internally looped back to the digital board
1
906
LoopVideoUserDealer
Nucleus for testing the components on the video signal system path:
- The VIP
- The video encoder
- The VSM
- The host decoder
- The analogue board
On the analogue the video signal is internally routed back to the digital board.
Diagnostic Software and Faultfinding Trees
5.2
Player Script Interface
5.2.1
Description
5.2.2
The Player script will give the opportunity to perform a test that
will determine which of the DVD recorder's modules are faulty,
to read the error log and to perform an endurance loop test. To
successfully perform the tests, the DVD recorder must be
connected to a TV set.
To be able to check results of certain nuclei, the player script
expects some interaction of the user (i.e. to approve a test
picture or a test sound). Some nuclei (e.g. nuclei that test
functionality of the DVDR module) require that a DVD+RW disc
is inserted.
Only tests within the scope of the diagnostic software will be
executed hence only faults within this scope can be detected.
DVDR980-985 /0X1
5.
EN 39
Structure of the Player Script
The player script consists of a set of nuclei testing the hardware
modules in the DVD recorder: the Display PWB, the Digital
PWB, the Analogue In/Out PWB and the DVDR module.
Nuclei run by the player test need some user interaction; in the
next table this interaction is described. The player test is done
in two phases:
• Interactive tests: this part of the player test depends
strongly on user interaction and input to determine nucleus
results and to progress through the full test. Reading the
error log information can be useful to determine any errors
that occurred recently during normal operation of the DVD
player.
• The loop test will perform the same nuclei as the dealer
test, but it will loop through the list of nuclei indefinitely.
STEP DESCRIPTION
NUCLEUS
1
Press OPEN/CLOSE and PLAY at the same time and POWER ON the recorder to start the playerscript
2
2
The local display shows FPSEGMENTS. Press PLAY to start the test.
502
First the starburst pattern is lit, then the horizontal segments are lit, followed by the vertical segments and the
last test is light all segments test. After each of the 4 tests the user has to confirm that the correct pattern was
lit.
Press PLAY to confirm that the correct pattern was lit (four times if the FPSEGMENTS test was successful).
Press RECORD to indicate that the correct pattern was not successfully lit.
Press STOP to skip this nucleus.
3
The local display shows FPLABELS. Press PLAY to start the test.
Press PLAY to confirm that all labels are lit.
Press RECORD to indicate that not all labels are lit.
Press STOP to skip this nucleus.
503
4
The local display shows FPLIGHT ALL. Press PLAY to start the test.
Press PLAY to confirm that everything was lit.
Press RECORD to indicate that not all patterns are lit.
Press STOP to skip this nucleus.
520
5
The local display shows FPLED. Press PLAY to start the test.
Press PLAY to confirm that the led is lit.
Press RECORD to indicate that the led is not lit.
Press STOP to skip this nucleus.
504
6
The local display shows FPFLAP OPEN. Press PLAY to start the test.
Press PLAY to confirm that the flap has opened.
Press RECORD to indicate that the flap did not open.
Press STOP to skip this nucleus.
522
7
505
The local display shows FPKEYBOARD. Press PLAY to start the test.
Attention all keys have to be pressed to get a positive result!
Press PLAY for more than one second to confirm that all the keys were pressed and shown on the local display. If not all the keys were pressed, a FAIL message will appear on the local display.
Press RECORD for more than one second to indicate that not all keys were pressed and shown on the local
display.
Press STOP for more than one second to skip this nucleus.
8
The local display shows FPREMOTE CONTROL. Press PLAY to start the test.
506
Press PLAY to confirm that a key on the remote control was pressed and shown on the local display. Only
one key has to be pressed to get a successful result.
Press RECORD to indicate that the key on the remote control was pressed but not shown on the local display.
Press STOP to skip this nucleus.
9
The local display shows FPDIMMER. Press PLAY to start the test.
Press PLAY to confirm that the text on the local display was dimmed.
Press RECORD to indicate that the text on the local display was not dimmed.
Press STOP to skip this nucleus.
518
10
The local display shows FPBEEPER. Press PLAY to start the test.
Press PLAY to confirm that the beeper on the front panel sounded.
Press RECORD to indicate that the beeper on the front panel did not sound.
Press STOP to skip this nucleus.
514
11
The local display shows FPFLAP CLOSE. Press PLAY to start the test.
Press STOP to skip this nucleus.
523
12
The local display shows ROUTE VIDEO. Press PLAY to start the test.
Press STOP to skip this nucleus.
712
13
The local display shows ROUTE AUDIO. Press PLAY to start the test.
Press STOP to skip this nucleus.
713
14
The local display shows COLOUR-BAR ON. Press PLAY to start the test.
Press STOP to skip this nucleus.
120
EN 40
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
STEP DESCRIPTION
NUCLEUS
15
The local display shows PINK NOISE ON. Press PLAY to start the test.
Press STOP to skip this nucleus.
115
16
The local display shows PINK NOISE OFF. Press PLAY to start the test.
Press STOP to skip this nucleus.
116
17
The local display shows SINE ON. Press PLAY to start the test.
Press STOP to stop the sine.
Press STOP to skip this nucleus.
117
18
The local display shows COLOUR-BAR OFF. Press PLAY to start the test.
Press STOP to skip this nucleus.
121
19
The local display shows BERESET. Press PLAY to start the test.
Press STOP to skip this nucleus.
603
20
The local display shows BETRAY OPEN. Press PLAY to start the test.
Press STOP to skip this nucleus.
616
21
The local display shows BETRAY CLOSE. Press PLAY to start the test.
Press STOP to skip this nucleus.
615
22
The local display shows BEWRITE READ. Press PLAY to start the test.
Press STOP to skip this nucleus.
617
23
The local display shows BETRAY OPEN. Press PLAY to start the test.
Press STOP to skip this nucleus.
616
24
The local display shows BETRAY CLOSE. Press PLAY to start the test.
Press STOP to skip this nucleus.
615
25
The local display shows READ ERRORLOG. Press PLAY to start the test.
Press STOP to skip this nucleus.
If the player test succeeded, the user/dealer script will start in an endless loop.
If the player test failed, the local display will display FAIL and the error code
633
Remark
In case of failure, the display shows " FAIL XXXXXX ". The
description of the shown error code can be retrieved in the
survey of Nuclei Error Codes (paragraph 5.4). Once an error
occurs, it is not possible to continue the player script. Unplug
the set and restart the player script. By pressing the STOP key,
it is possible to jump over the failure and to continue the player
script.
Figure 5-2
PRESS IF OK
PRESS IF NOT OK
PRESS IF OK
PRESS TO ABORT
PRESS IF OK
PRESS TO ABORT
PRESS IF OK
PRESS TO ABORT
PRESS
TO SKIP TEST
CHAPTER
PCM
EP+
CHAPTER
HQ SP L:P
-30
-20
MPEG DD DIGITAL DTS
SAVCD
-10
PCM
EP+
0
TOTAL
OVER
MANUAL
MONITOR
TOTAL
MANUAL
MONITOR
DIGITAL
TIMER
REMAIN
SAT
AM
NICAM
PM
CHANNEL
STEREO
RECORD
VPS/PDC
SAP
DECODER
-30
DIGITAL
AM
PM
-20
NICAM
TIMER
REMAIN
SAT
CHANNEL
-10
0
STEREO
RECORD
VPS/PDC
OVER
SAP
DECODER
LED BECOMES RED
PRESS
TO SKIP TEST
PRESS IF OK
PRESS IF NOT OK
-40
TRACK TIME
PRESS
TO SKIP TEST
PRESS IF OK
PRESS IF NOT OK
TRACK TIME
PRESS
TO SKIP TEST
PRESS IF OK
PRESS IF NOT OK
PRESS
TO START TEST
PROLOGIC
DVD
-40
TRACK
RW
TITLE
PRESS
TO START TEST
DTS
HQ SP L:P
DD DIGITAL
SAVCD
MPEG
DVD
PROLOGIC
TRACK
RW
TITLE
PRESS
TO START TEST
I
PRESS
TO START TEST
II
FRONTPANEL TEST
I
Hold 2 keys
+
simultaneously pressed while
you plug the recorder
II
Unplug the power cord
PRESS
TO SKIP TEST
PRESS ALL KEYS AT LEAST ONCE
SEE TABLE FOR KEY CODES
XX TIMES
PRESSED
AUTOMAN
REC VOLUME
MANUAL UP
MANUAL DOWN
CHANNEL UP
CHANNEL DOWN
STANDBY/ON
MONITOR
OPEN/CLOSE
STOP
PLAY
RECORD
FRONT KEY NAME
00B
00C
009
00A
00D
00E
00F
001
002
003
004
FRONT KEY CODE
PRESS MORE THAN 1S IF TEST IS OK
PRESS MORE THAN 1S IF TEST IS NOT OK
HEXADECIMAL
KEY CODE
PRESS
TO START TEST
PRESS
TO SKIP TEST
PRESS AT LEAST ONE KEY
ON THE REMOTE CONTROL
SEE TABLE FOR RC KEY CODES
XX TIMES
PRESSED
EE
MONITOR
ON/OFF
STOP
REC/OTR
PLAY
REVERSE
PAUSE
SLOW
FORWARD
PREVIOUS
FSS
NEXT
DISC
SYSTEM
UP
LEFT
RIGHT
DOWN
RETURN
OK
CLEAR
TIMER
SELECT
VOL +
VOL CH +
CH MUTE
1
2
3
4
5
6
7
8
9
0
T/C
13
1D
3B
2A
DIM
REPEAT
REPEAT A-B
SCAN
5.
EE
F7
85
4B
4E
PRESS IF OK
PRESS IF NOT OK
BEEP IS AUDIBLE
PRESS IF OK
PRESS IF NOT OK
PRESS
TO SKIP TEST
DIGITAL BOARD TEST
PRESS
TO START TEST
PRESS
TO START TEST
DVDR980-985 /0X1
A/CH
ZOOM
ANGLE
SUBTITLE
AUDIO
ONLY FOR TV
ONLY FOR TV
1E
1F
ONLY FOR TV
01
02
03
04
05
06
07
08
09
00
C8
0C
31
37
2C
29
30
22
28
21
CF
20
54
0F
58
5A
5B
59
83
5C
41
FE
FA
RC KEY CODE
RC KEY NAME
TO EXIT TEST: PRESS ONE OF FOLLOWING KEYS
ON THE LOCAL KEYBOARD
PRESS IF TEST IS OK
PRESS IF TEST IS NOT OK
HEXADECIMAL
RC KEY CODE
PRESS
TO START TEST
Diagnostic Software and Faultfinding Trees
EN 41
Player Script
CL 265362011_022.eps
160102
EN 42
5.
FRONTPANEL
TEST
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
DIGITAL BOARD &
ANALOG BOARD
TEST
BASIC ENGINE
TEST
press to execute
press < STOP > to skip
press to execute
press to skip
press to execute
press < STOP > to skip
press to execute
press to skip
INSERT DVD +RW DISC TO EXECUTE
WRITE / READ TEST
press to execute
press < STOP > to skip
press to execute
press to skip
press to execute
press < STOP > to skip
press to execute
press to skip
press to execute
press to skip
press to execute
press to skip
press to execute
press < STOP > to skip
press to execute
press to skip
press to continue
press to skip
press to execute
PRESS
TO STEP DOWN
NO ERRORS LOGGED
PRESS
TO STEP DOWN
PRESS
TO STEP UP
PRESS
TO STEP UP
PRESS TO CONTINUE
IF ERROR
To exit PLAYER SCRIPT, unplug the power cord
Figure 5-3
5.2.3
Error Log
Explanation:
The application errors will be logged in the NVRAM. The
maximum number of error bytes that will be visible is 19. The
last reported error is shown as DN D0000000, the oldest visible
error as D0000000 UP and the errors in between as DN
D0000000 UP. DN stands for DOWN, UP stands for
UPWARDS. The shown
D error codes are identical to the Nuclei Error Codes
(paragraph 5.4).
CL 16532095_070.eps
031201
Diagnostic Software and Faultfinding Trees
5.2.4
Trade Mode
5.3.2
When the recorder is in Trade Mode, the recorder cannot be
controlled by means of the front key buttons, but only by means
of the remote control.
+
+
PLUG THE RECORDER
PLUG THE RECORDER
RECORDER IS IN TRADE MODE
WHEN PRESSING FRONT
KEYS, THE RECORDER
DOESN'T RESPOND
RECORDER IS IN NORMAL MODE
WHEN PRESSING FRONT
KEYS, THE RECORDER
WILL RESPOND
Figure 5-4
Virgin mode
If you want that the recorder starts up in Virgin mode, follow this
procedure:
• Unplug the recorder
• plug the recorder again while you keep the STAND BY/ON
key pressed
• the set starts up in Virgin mode.
5.3
Menu and Command Mode Interface
5.3.1
Nuclei Numeration
Each nucleus has a unique number of four digits. This number
is the input of the command mode.
[ XX YY
CL 06532152_013.eps
051200
PRESS 2 KEYS
SIMULTANEOUSLY
CL 16532095_071.eps
150801
5.2.5
Error Handling
Error code
Nucleus number
Nucleus group number
UNPLUG THE RECORDER
PRESS 2 KEYS
SIMULTANEOUSLY
]
EN 43
[ XX YY ZZ ]
IF TRADE MODE ON
UNPLUG THE RECORDER
5.
Each nucleus returns an error code. This code contains six
numerals, which means:
TRADE MODE
IF TRADE MODE OFF
DVDR980-985 /0X1
Figure 5-6
The nucleus group numbers and nucleus numbers are the
same as above.
5.3.3
Command Mode Interface
Set-Up Physical Interface Components
Hardware required:
• Service PC
• one free COM port on the Service PC
• special cable to connect DVD recorder to Service PC
The service PC must have a terminal emulation program (e.g.
OS2 WarpTerminal or Procomm) installed and must have a
free COM port (e.g. COM1). Activate the terminal emulation
program and check that the port settings for the free COM port
are: 19200 bps, 8 data bits, no parity, 1 stop bit and no flow
control. The free COM port must be connected via a special
cable to the RS232 port of the DVD recorder. This special cable
will also connect the test pin, which is available on the
connector, to ground (i.e. activate test pin).
Code number of PC interface cable: 3122 785 90017
Activation
Plug the recorder to the mains and the following text will appear
on the screen of the terminal (program):
DVD Video Recorder Diagnostic Software version 48
Basic SDRAM Data bus test passed
Basic SDRAM Address bus test passed
Basic SDRAM Device test passed
Nucleus number
Nucleus group number
(M) enu, (C) ommand or (S) 2B-interface?
DD:>
CL 16532095_073.eps
150801
CL 06532152_012.eps
051200
Figure 5-5
The following groups are defined:
Group number Group name
0
Basic / Scripts
1
Host decoder (Sti5505 and memory)
2
Audio / video encoder (DVDR only)
3
VSM (DVDR only)
4
NVRAM
5
Front Panel
6
Basic Engine
7
Analogue board (DVDR only)
8
DVIO (DVDR only)
9
Loop nuclei (DVDR only)
10
Library sub nuclei (I2C nuclei)
11
User interface
12
Furore (SACD only)
13
DAC (SACD only)
14
Miscellaneous
[M] : @ C
Figure 5-7
The first line indicates that the Diagnostic software has been
activated and contains the version number. The next lines are
the successful result of the SDRAM interconnection test and
the basic SDRAM test. The last line allows the user to choose
between the three possible interface forms. If pressing C has
made a choice for Command Interface, the prompt ("DD>") will
appear. The diagnostic software is now ready to receive
commands. The commands that can be given are the numbers
of the nuclei.
EN 44
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Command Overview
We provide an overview of the nuclei and their numbers. This
overview is preliminary and subject to modifications.
Host Decoder [01]
[xx yy] Nuclei
Number
100
Checksum Flash
101
Flash Write Access 1
102
Flash Write Access 2
103
Flash Write Read
104
SdRam Write Read
105
SdRam Write Read Fast
106
Dram Write Read
107
Dram Write Read Fast
108
Hardware Version
109
Mute On
110
Mute Off
115
Pink Noise On
116
Pink Noise Off
117
Sine On
118
Sine Burst 1kHz
119
Sine Burst 12kHz
120
Colour-bar On
121
Colour-bar Off
122
NvramWrR
123
NvramI2c
130
Boot Version
131
Application Version
132
Diagnostics Version
133
Download Version
[xx yy] Nuclei
Number
402
Modify
403
UniqueNr Read
404
Read Error Log
407
Reset Error Log
409
Line2 Region-Code Reset
410
UniqueNr Store
Front Panel [05]
[xx yy] Nuclei
Number
500
Echo
501
Version
502
Segment
503
Label
504
Led
505
Keyboard
506
Remote-Control
507
Segment Starburst
508
Segment Vertical
509
Segment Horizontal
514
Beeper
515
Discbar
516
Discbar Dots
517
Vu / Grid
518
Dimmer
519
Blinking
520
Light All Segments
522
Flap Open
523
Flap Close
134
Write / read I2C message to / from digital board
135
Video Test Signal On
Basic Engine [06]
136
Video Test Signal Off
137
Macrovision Off
[xx yy] Nuclei
Number
Audio Video Decoder [02]
[xx yy] Nuclei
Number
200
Video Encoder I2C
202
SAA7118 I2C
203
Audio Encoder SRAM Access
204
Audio Encoder Access
205
Audio Encoder SRAM Write Read
206
Audio Encoder Interrupts
207
Audio Encoder I2C
208
SAA7118 select input
209
Empress Version
600
S2B Pass
601
S2B Echo
602
Version
603
Reset
604
Focus On
605
Focus Off
606
Disc Motor On
607
Disc Motor Off
608
Radial On
609
Radial Off
615
Tray In
616
Tray Out
617
Write Read
VSM [03]
618
Write Read Endless Loop
[xx yy] Nuclei
Number
619
Selftest
620
BE Test
300
Register Access
621
Laser Test
301
SDRAM Access
622
Spindle (Disc) Motor Test
302
SDRAM Write Read
623
Focus Test
303
Interrupt lines
624
Sledge Motor Test
304
VSM Interconnection
625
Sledge Motor Slow
305
UART
626
Tilt
627
EEPROM Read
NVRAM [04]
628
EEPROM Write
[xx yy] Nuclei
Number
629
Optimise Jitter
630
Radial ATLS Calibration
400
Reset
631
Get Statistics Information
401
Read
632
Reset Statistics Information
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
[xx yy] Nuclei
Number
[xx yy] Nuclei
Number
633
BE Read Error Log
906
User / Dealer Video Loop
634
BE Reset Error Log
907
User / Dealer Video VBI Loop
638
Get Self Test Result
908
System Audio Loop SCART
639
Radial Initialisation
909
System Audio Loop CINCH
640
Get OPU info
910
Digital DVIO Video Loop
641
Write read +R
911
System Video Vip
642
Write read +R endless loop
5.
EN 45
Miscellanious [14]
Analog Board [07]
[xx yy] Nuclei
Number
[xx yy] Nuclei
Number
1400
Clock 11.289 MHz
700
Echo
1401
Clock 12.288 MHz
703
Boot Version
1412
Progressive Scan I2C
704
Hardware Version
1413
Progressive Scan test image on
705
Clock Adjust
1414
Progressive Scan test image off
706
Tuner
1415
Progressive Scan Route Enable
707
Frequency Download
1416
Progressive Scan Route Disable
708
Data Slicer
709
Sound Processor
710
AV Selector
711
Nvram
712
Route Video
713
Route Audio
715
Set Slash Version
716
Application Version
717
Diagnostics Version
718
Download Version
720
Bargraph Level Adjustment
721
Clock correction
722
Clock reference
723
Re-virginise Recorder
Scripts [00]
[xx yy] Nuclei
Number
5.3.4
1
UserDealer Script
2
Player Script
Menu Mode Interdace
Activation
Plug the recorder to the mains and the following text will appear
on the screen of the terminal (program):
724
Flash Checksum
DVD Video Recorer Diagnostic Software version 48
Basic SDRAM Data bus test passed
Basic SDRAM Address bus test passed
Basic SDRAM Device test passed
725
Tuner frequency selection
(M) enu, (C) ommand or (S) 2B-interface?
727
Set virgin bit
Main Menu
728
Clear Virgin Bit
729
Write / read I2C message to / from analogue board
1.
2.
3.
4.
5.
6.
7.
8.
9.
730
Store external presets
731
Get slash version
732
AFC Reference Voltage Tuner
DVIO [08]
Digital Board
Analogue Board
Front Panel
Basic Engine
DVIO
Progressive Scan Board
Loop tests
Log
Scripts
->
->
->
->
->
->
->
->
->
Select>
[xx yy] Nuclei
Number
800
Check DVIO board presence
801
Reset DVIO
802
DVIO Access
803
Get DVIO error codes
804
Get DVIO module Ids
805
Execute DVIO module SelfTest
806
Set DVIO led on.
807
Set DVIO led off.
Loop Nuclei [09]
[xx yy] Nuclei
Number
900
Digital Audio Loop
901
User / Dealer Audio Loop
902
Digital Video Loop
903
Digital Video VBI Loop
904
System Video Loop
905
System Video VBI Loop
[M] : @ M
CL 16532095_074.eps
150801
Figure 5-8
The first line indicates that the Diagnostic software has been
activated and contains the version number. The next lines are
the successful result of the SDRAM interconnection test and
the basic SDRAM test. The last line allows the user to choose
between the three possible interface forms. If pressing M has
made a choice for Menu Interface, the Main Menu will appear.
EN 46
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Menu Structure
The following menu structure is given after starting up the DVD
recorder in menu mode. The symbol -> indicates that the
current menu choice will invoke the display of a submenu.
Main Menu
1.Digital Board
2.Analogue Board
3.Front Panel
4.Basic Engine
5.DVIO
6.Progressive Scan Board
7.Loop Tests
8.Log
9.Scripts
Digital Board Menu
1.Host Decoder
2.VSM
3.AVENC
4.NVRAM
Audio Mute Menu
1.Audio Mute On
2.Audio Mute Off
Colourbar Menu
1.Colourbar On
2.Colourbar Off
Pink Noise Menu
1.Pink Noise On
2.Pink Noise Off
Sine Generate Menu
1.Sine On
2.Sine Burst 1kHz
3.Sine Burst 12kHz
VSM Menu
1.Register Access
2.SDRAM Access
3.VSM SDRAM Write/Read
4.Interrupt Lines
5.VSM Interconnection
6.UART
->
->
Empress Menu
1.Version number
->
->
->
->
->
->
->
->
->
->
->
->
->
Host Decoder Menu
1.Flash Checksum
2.Flash1 Write Access
3.Flash2 Write Access
4.Flash Write/Read
5.Host SDRAM Write/Read
6.Host SDRAM Fast Write/Read
7.Host DRAM Write/Read
8.Host DRAM Fast Write/Read
9.I2C NVRAM
10.NVRAM Write/Read
11.Engine S2B Echo
12.Versions
->
13.Audio Mute
->
14.Colourbar
->
15.Pink Noise
->
16.Sine Generate
->
Digital Board Versions Menu
1.Hardware Version
2.Bootcode version
3.Applications Version
4.Diagnostics Version
5.Download Version
AVENC Menu
1.Empress
2.Video Input Processors
Video Input Processors Menu
1.SAA7118 I2C Access
NVRAM Menu
1.Read Error Log
2.Reset Error Log
3.Read DVIO Unique ID
Analogue Board Menu
1.Echo
2.Obsolete
3.Route Video Input back to Digital board
4.Route Audio Input back to Digital board
5.Flash Checksum
6.Versions
->
7.Components
->
8.Re-virginize Recorder
->
Analogue Board Versions Menu
1.Hardware Version
2.Bootcode version
3.Application version
4.Diagnostics version
5.Download version
Analogue Components Menu
1.Tuner
2.Data Slicer
3.Sound Processor
4.AV Selector
5.NVRAM
Analogue Board Re-virginize Menu
1.Re-virginize Recorder
2.Set Virgin-bit
3.Clear Virgin-bit
4.Store external presets
Front Panel Menu
1.Echo
2.Version
3.Flap Control
4.Segment Test
5.Light Labels
6.Led test
7.Keyboard test
8.Remote Control
9.Beep
10.Disc Bar
11.Disc Bar Dots
12.Vu Grid
13.Dimmer
14.Blink
15.Light All Segments
Flap Control Menu
1.Open Flap
2.Close Flap
Segment Test Menu
1.Starburst
2.Light Horizontal Segments
3.Light Vertical Segments
4.Light All Segments
->
->
Diagnostic Software and Faultfinding Trees
Basic Engine Menu
1.Reset
2.S2B Pass-through
3.S2B Echo
4.Focus On
5.Focus Off
6.Version
7.Self Test
8.Get Self Test Result
9.Basic Engine Test
10.Laser Test
11.Focus Test
12.Tilt Test
13.Optimise Jitter
14.Statistics Info
15.Log
16.Spindle Motor
17.Radial
18.Sledge
19.Tray
5.
EN 47
User/Dealer Loops Menu
1.User/Dealer Audio Loop
2.User/Dealer Video Loop
3.User/Dealer Video Loop VBI
System Loops Menu
1.System Video Loop
2.System Video Loop VBI
3.System Audio Loop SCART(EURO)
4.System Audio Loop CINCH (NAFTA)
Basic Engine Loops Menu
1.Basic Engine write read
2.Basic Engine write read endless loop
->
->
->
->
->
Log Menu
1.Read Error Log
2.Reset Error Log
Script Menu
1.User/Dealer Script
2.Player Script
Basic Engine Error Log
1.Read Error Log
2.Reset Error Log
5.4
Basic Engine Spindle Motor Menu
1.Spindle Motor On
2.Spindle Motor Off
3.Spindle Motor Test
Nuclei Error Codes
In the following table the error codes will be described.
Basic Engine Radial Menu
1.Radial On
2.Radial Off
3.Radial Initialisation
4.Radial ATLS Calibration
Basic Engine Sledge Menu
1.Sledge test
2.Sledge test slow
Basic Engine Tray Menu
1.Tray In
2.Tray Out
DVIO Menu
1.Check Presence
2.Reset
3.Access
4.Error Codes
5.Module Identifiers
6.Led
DVDR980-985 /0X1
Error Nr
Error String
10000
"Checksum is OK"
10001
"segment name Checksum doesn't match" or "segment name segment not found"
10100
""
10101
"FLASH 1 Write access test failed"
10200
""
10201
"FLASH 2 Write access test failed"
10300
""
10301
"FLASH write test failed"
10302
"FLASH write command failed"
10303
"FLASH write test done max. number of times"
10400
""
10401
"HostDec SDRAM Memory data bus test goes
wrong."
10402
" HostDec SDRAM Memory address bus test goes
wrong."
10403
" HostDec SDRAM Physical memory device test
goes wrong."
10500
""
10501
" HostDec SDRAM Memory data bus test goes
wrong."
DVIO Led Menu
1.Led On
2.Led Off
10502
" HostDec SDRAM Memory address bus test goes
wrong."
10503
" HostDec SDRAM Physical memory device test
goes wrong."
Progressive Scan Board Menu
1.I2C Access
2.Test Image On
3.Test Image Off
10600
""
10601
"HostDec DRAM Memory data bus test goes
wrong."
10602
"HostDec DRAM Memory address bus test goes
wrong."
10603
"HostDec DRAM Physical memory device test
goes wrong."
Loop Tests Menu
1.Digital Board Loops
2.User/Dealer Loops
3.System Loops
4.Basic Engine Loops
Digital Board Loops Menu
1.Obsolete
2.Digital Video Loop
3.Digital Video Loop VBI
->
->
->
->
->
10700
""
10701
"HostDec DRAM Memory data bus test goes
wrong."
10702
"HostDec DRAM Memory address bus test goes
wrong."
10703
"HostDec DRAM Physical memory device test
goes wrong."
EN 48
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Error Nr
Error String
Error Nr
Error String
10800
"Host Decoder version(cut) number: version
number""Digital hardware version"
20004
"No data send/received to or from Video Encoder"
20005
"SAA7118 VIP can not be initialised"
10801
"Can not find version in FLASH."
20200
""
10900
""
20201
"I2C bus busy before start"
10901
"Error muting audio"
20202
"SAA7118 VIP access time-out"
11000
""
20203
"No acknowledge from SAA7118 VIP"
11001
"Error demuting audio"
20204
"No data received from SAA7118 VIP"
11500
""
20300
""
11501
"Init of I2C failed"
20301
11502
"The selection of the clock source failed"
"Error audio encoder SRAM access cannot initialise I2C"
20302
"Error audio encoder SRAM access cannot reset
DSP through I2C"
20303
"Error audio encoder SRAM access cannot download boot"
20304
"Error audio encoder cannot download test code"
11504
"The demute of the audio failed"
11600
""
11601
"Init of I2C failed"
11602
"The mute of the audio failed"
11700
""
11701
11702
"Init of I2C failed"
"The muting of the audio failed"
11703
"The demute of the audio failed"
11704
"The selection of the clock source failed"
11707
"Setup of Front panel failed"
11708
"Sine on Front panel keyboard failed"
11800
""
11801
"Init of I2C failed"
11802
"The muting of the audio failed"
11803
"The demute of the audio failed"
11804
"The selection of the clock source failed"
11805
"Error cannot start VSM audio in port"
11900
""
11901
"Init of I2C failed"
11902
"The muting of the audio failed"
20305
"Error audio encoder cannot obtain result of test"
20306
"Error audio encoder SRAM access stuck-at-zero
data line "
20307
"Error audio encoder SRAM access stuck-at-one
data line "
20308
"Error audio encoder SRAM access stuck-at-one
address line "
20309
"Error audio encoder SRAM access address line
address line x is connected to data line data line y"
20310
"Error audio encoder SRAM access address lines
address line x and address line y are connected "
20311
"Error audio encoder SRAM access data lines data
line x and data line y are connected "
20312
"Error audio encoder SRAM access illegal data received"
20400
""
20401
"Error audio encoder access cannot initialise I2C"
20402
"Error audio encoder access cannot reset DSP
through I2C"
11903
"The demute of the audio failed"
11904
"The selection of the clock source failed"
11905
"Error cannot start VSM audio in port"
20403
"Error audio encoder accessing ICR register"
12000
""
20404
12001
"Invalid input
"Error audio encoder access stuck-at-zero of data
line "
12100
""
20405
12200
""
"Error audio encoder access stuck-at-one of data
line "
20406
"Audio encoder access data lines data line x and
data line y are interconnected "
12201
"I2C bus busy before start"
12202
"NVRAM access time-out"
12203
"No NVRAM acknowledge"
20500
""
12204
"NVRAM time-out"
20501
12205
"NVRAM Write/Read back failed"
"Error audio encoder SRAM WRR cannot initialise
I2C"
12300
""
20502
"Error audio encoder SRAM WRR cannot reset
DSP through I2C"
12301
"I2C bus busy before start"
12302
"NVRAM read access time-out"
12303
"No NVRAM read acknowledge"
12304
"NVRAM read failed"
13000
"Bootcode application version : bootversion"
13001
"Can not find version in FLASH."
13100
"Recorder application version : recorderversion"
13101
"Can not find version in FLASH."
13200
"Diagnostics application version : diagversion"
13201
"Can not find version in FLASH."
13300
"Download application version : downloadversion"
13301
"Can not find version in FLASH."
13700
""
13701
"Turning off MacroVision failed"
20000
""
20001
"I2C bus busy before start"
20002
"Video Encoder access time-out"
20003
"No acknowledge from Video Encoder"
20503
"Error audio encoder WRR cannot download boot"
20504
"Error audio encoder cannot download test code"
20505
"Error audio encoder SRAM WRR cannot obtain
result of test"
20506
"Error audio encoder WRR SRAM stuck-at-zero
data bit "
20507
"Error audio encoder WRR SRAM stuck-at-one
data bit "
20508
"Error audio encoder WRR SRAM data lines data
line x and data line y are connected"
20509
"Error audio encoder WRR SRAM illegal data received"
20600
""
20601
"Error audio encoder interrupt cannot initialise I2C"
20602
"Error audio encoder interrupt cannot reset DSP
through I2C"
20603
"Error audio encoder cannot download test code"
20604
"Error occurred accessing VSM"
20605
"Audio encoder interrupt not received"
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
5.
EN 49
Error Nr
Error String
Error Nr
Error String
20606
"Error occurred while activating the encoder"
30203
20607
"Error audio encoder interrupt cannot initialise empress"
"VSM SDRAM Bank1 Physical memory device test
goes wrong."
30204
20608
"Error occurred while getting interrupt reason"
" VSM SDRAM Bank2 Memory databus test goes
wrong."
20700
""
30205
20701
"Error audio encoder I2C cannot reset DSP
through I2C"
" VSM SDRAM Bank2 Memory addressbus test
goes wrong."
30206
" VSM SDRAM Bank2 Physical memory device
test goes wrong."
20702
"Error audio encoder cannot download boot"
20703
"Error audio encoder cannot download TEST
code"
20704
"Error audio encoder I2C bus busy"
20705
"Error audio encoder I2C cannot write slave address"
20706
"Error audio encoder I2C no acknowledge received"
30300
""
30301
"VSM interrupt register A has a -stuck at- error for
value:"
30302
"VSM interrupt register B has a -stuck at- error for
value:"
30303
"Interrupt A wasn't raised."
30304
"Interrupt B wasn't raised."
"Interrupts A and B were raised."
20707
"Error audio encoder I2C cannot send/receive data"
30305
30400
""
20708
"Error audio encoder received data through I2C
was invalid"
30401
"VSM SDRAM Bank1 Memory databus test goes
wrong."
20800
""
30402
20801
"I2C access failed."
"VSM SDRAM Bank1 Memory addressbus test
goes wrong."
20802
"SAA7118 VIP can not be initialised."
30403
20803
"Invalid input"
"VSM SDRAM Bank1 Physical memory device test
goes wrong."
20900
"B1.B2. B3.B4. B5.B6. B7.B8. B9.B10. B11.B12."
30404
20901
"Firmware download of EMPRESS failed"
" VSM SDRAM Bank2 Memory databus test goes
wrong."
20902
"I2C bus busy before start"
30405
" VSM SDRAM Bank2 Memory addressbus test
goes wrong."
20903
"EMPRESS access time-out"
30406
20904
"No acknowledge from the EMPRESS"
" VSM SDRAM Bank2 Physical memory device
test goes wrong."
20905
"No data send to the EMPRESS"
30500
""
20906
"No data received from the EMPRESS"
30501
"Communication with the analogue board fails."
30000
""
30502
30001
"VSM SDRAM Bank1 Memory databus test goes
wrong."
"Echo test to analogue board returned wrong
string."
40000
""
30002
"VSM SDRAM Bank1 Memory addressbus test
goes wrong."
40001
"NVRAM Reset; I2C failed"
40100
30003
"VSM SDRAM Bank1 Physical memory device test
goes wrong."
"NVRAM address = 0xaddress -> Byte value =
0xvalue"
40101
"NVRAM Read; I2C failed"
30004
" VSM SDRAM Bank2 Memory databus test goes
wrong."
40102
"NVRAM Read; Invalid input"
30005
" VSM SDRAM Bank2 Memory addressbus test
goes wrong."
40200
""
40201
"NVRAM Modify; I2C failed"
40202
"NVRAM Modify; Invalid input"
30006
" VSM SDRAM Bank2 Physical memory device
test goes wrong."
40300
"DV Unique ID = id"
30007
"VSM SDRAM Bank1 VSM interrupt register A has
a -stuck at- error for value:"
40301
"NVRAM Read DV Unique ID; I2C failed"
40400
"\r\n Error log:\r\n errorString \r\n Ö "
30008
"VSM SDRAM Bank2 VSM interrupt register A has
a -stuck at- error for value:"
40401
"NVRAM error log; I2C failed"
40402
"NVRAM error log is invalid"
30100
""
40403
"Front panel failed"
30101
"VSM SDRAM Bank1 Memory databus test goes
wrong."
40700
""
40701
"NVRAM error log reset; I2C failed"
"VSM SDRAM Bank1 Memory addressbus test
goes wrong."
40900
"Region code Change counter is reset"
"VSM SDRAM Bank1 Physical memory device test
goes wrong."
40901
"NVRAM region code reset; I2C failed"
41000
""
41001
"NVRAM Store DV Unique ID; I2C failed"
41002
"NVRAM Store DV Unique ID; Invalid input"
30102
30103
30104
" VSM SDRAM Bank2 Memory databus test goes
wrong."
30105
" VSM SDRAM Bank2 Memory addressbus test
goes wrong."
50000
""
50007
"Execution of the command on the analogue board
failed."
50008
"The frontpanel could not be accessed by the analogue board."
30106
" VSM SDRAM Bank2 Physical memory device
test goes wrong."
30200
""
30201
"VSM SDRAM Bank1 Memory databus test goes
wrong."
50009
"The echo from the frontpanel processor was not
correct."
30202
"VSM SDRAM Bank1 Memory addressbus test
goes wrong."
50100
" Front panel version: FPversion "
EN 50
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Error Nr
Error String
Error Nr
Error String
50102
"Execution of the command on the analogue board
failed."
50901
"Execution of the command on the analogue board
failed."
50103
"The frontpanel could not be accessed by the analogue board."
50902
"The frontpanel could not be accessed by the analogue board."
50200
""
50903
"The frontpanel did not show horizontal segments."
50204
"Execution of the command on the analogue board
failed."
50904
"The user skipped the FP-horizontal segments
test."
50205
"The frontpanel could not be accessed by the analogue board."
50905
"The user returned an unknown confirmation: confirmation "
50206
"The frontpanel did not show a starburst."
51400
""
50207
"The user skipped the FP-which pattern test."
51401
50208
"The user returned an unknown confirmation: confirmation "
"Execution of the command on the analogue board
failed."
51402
50209
"The frontpanel did not show horizontal segments."
"The frontpanel could not be accessed by the analogue board."
50210
"The frontpanel did not show vertical segments."
51403
"The beeper did not sound."
50300
""
51404
"The user skipped the FP-Beep test."
50304
"Execution of the command on the analogue board
failed."
51405
"The user returned an unknown confirmation: confirmation"
50305
"The frontpanel could not be accessed by the analogue board."
51500
""
51501
"Execution of the command on the analogue board
failed."
50306
"The frontpanel did not light all labels."
50307
"The user skipped the rest of the FP-label test."
51502
50308
"The user returned an unknown confirmation: confirmation"
"The frontpanel could not be accessed by the analogue board."
51503
"The discbar did not display properly."
""
51504
"The user skipped the discbar test."
50404
"Execution of the command on the analogue board
failed."
51505
"The user returned an unknown confirmation: confirmation"
50405
"The frontpanel could not be accessed by the analogue board."
51600
""
51601
"Execution of the command on the analogue board
failed."
50400
50406
"The LED's could not be turned on."
50407
"The user skipped the rest of the FP-LED test."
51602
50408
"The user returned an unknown confirmation: confirmation"
"The frontpanel could not be accessed by the analogue board."
51603
"The discbar dots did not display properly."
50500
""
51604
"The user skipped the discbar dots test."
50502
"Front panel Keyboard; test failed"
51605
50503
"Front panel Keyboard; test aborted"
"The user returned an unknown confirmation: confirmation"
50504
"Front panel Keyboard; not all keys were pressed"
51700
""
51701
"Execution of the command on the analogue board
failed."
51702
"The frontpanel could not be accessed by the analogue board."
"The VU grid did not display properly."
50505
"Front panel keyboard I2C connection failed"
50506
"Unable to get slashversion"
50600
""
50602
"Front panel Remote control; test failed"
51703
50603
"Front panel Remote control; test aborted"
51704
"The user skipped the VU gridtest."
50604
"Front panel remote control; can not access FP"
51705
50605
"Front panel remote control; no user input received"
"The user returned an unknown confirmation: confirmation"
50700
""
50701
51800
""
51801
"Execution of the command on the analogue board
failed."
"Execution of the command on the analogue board
failed."
51802
50702
"The frontpanel could not be accessed by the analogue board."
"The frontpanel could not be accessed by the analogue board."
51803
"The frontpanel could not be dimmed."
50703
"The frontpanel did not show a starburst."
51804
"The user skipped the FP-Dim test."
50704
"The user skipped the FP-starburst test."
51805
50705
"The user returned an unknown confirmation: confirmation "
"The user returned an unknown confirmation: confirmation"
50800
""
50801
51900
""
51901
"Execution of the command on the analogue board
failed."
"Execution of the command on the analogue board
failed."
51902
50802
"The frontpanel could not be accessed by the analogue board."
"The frontpanel could not be accessed by the analogue board."
51903
"The frontpanel did not show segments blinking."
50803
"The frontpanel did not show vertical segments."
51904
"The user skipped the FP-blinking test."
50804
"The user skipped the FP-vertical segments test."
51905
50805
"The user returned an unknown confirmation: confirmation "
"The user returned an unknown confirmation: confirmation"
52000
""
50900
""
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
5.
EN 51
Error Nr
Error String
Error Nr
Error String
52001
"Execution of the command on the analogue board
failed."
60803
"Communication time-out error"
60804
"Unexpected response from Basic Engine"
52002
"The frontpanel could not be accessed by the analogue board."
60805
"Radial loop could not be closed"
60900
""
60901
"Basic
Engine
0xerrornumber"
60902
"Parity error from Basic Engine to Serial"
60903
"Communication time-out error"
60904
"Unexpected response from Basic Engine"
52003
"The frontpanel did not show all segments lit."
52004
"The user skipped the FP-light all segments test."
52005
"The user returned an unknown confirmation: confirmation"
52200
""
52201
"Communication with Analogue Board fails."
52202
"Frontpanel can not be accessed by the Analogue
Board."
52300
""
52301
"Communication with Analogue Board fails."
52302
"Frontpanel can not be accessed by the Analogue
Board."
60000
""
60100
""
60101
"Basic
Engine
0xerrornumber"
returned
error
60102
"Parity error from Basic Engine to Serial"
60103
"Communication time-out error"
60104
"Unexpected response from Basic Engine"
60105
"Echo loop could not be closed"
60106
"Wrong echo pattern received"
60200
"Version: nr1.nr2.nr3"
60201
"Basic
Engine
0xerrornumber"
60202
60203
60204
error
61500
""
61501
"Basic
Engine
0xerrornumber"
61502
"Parity error from Basic Engine to Serial"
61503
"Communication time-out error"
61504
"Unexpected response from Basic Engine"
returned
error
61600
""
61601
"Basic
Engine
0xerrornumber"
61602
"Parity error from Basic Engine to Serial"
61603
"Communication time-out error"
61604
"Unexpected response from Basic Engine"
returned
61700
""
61701
"BE tray-in command failed"
61702
"BE read-TOC command failed"
error
61703
"BE VSM interrupt initialisation failed"
61704
"BE set irq command failed"
61705
"BE no disc or wrong disc inserted"
"Parity error from Basic Engine to Serial"
61706
"BE rec-pause command failed"
"Communication time-out error"
61707
"BE VSM BE out DMA initialisation failed"
returned
error
number
"Unexpected response from Basic Engine"
60205
"Front Panel failed."
60300
""
60301
number
returned
"Basic-Engine time-out error"
60400
""
60401
"Basic
Engine
0xerrornumber"
returned
error
number
61708
"BE VSM BE out initialisation failed"
61709
"BE VSM BE out DMA start failed"
61710
"BE VSM BE out start failed"
61711
"BE rec command failed"
61712
"BE VSM out underrun error occurred"
61713
"BE record complete interrupt not raised"
61714
"BE get irq command failed"
"BE no interrupt was raised by BE"
"BE VSM DMA out not finished"
number
number
number
60402
"Parity error from Basic Engine to Serial"
61715
60403
"Communication time-out error"
61716
"Unexpected response from Basic Engine"
61717
"BE stop command after writing failed"
60405
"Focus loop could not be closed"
61718
"BE VSM Sector processor initialisation failed"
60500
""
61719
60501
"Basic
Engine
0xerrornumber"
"BE VSM sector processor DMA initialisation
failed"
61720
"BE VSM sector processor DMA start failed"
60502
"Parity error from Basic Engine to Serial"
61721
"BE VSM sector processor start failed"
60503
"Communication time-out error"
61722
"BE seek command failed"
60504
"Unexpected response from Basic Engine"
61723
"BE VSM sector processor error occurred"
61724
"BE read timeout occurred"
60404
60600
""
60601
"Basic
Engine
0xerrornumber"
returned
returned
error
error
60602
"Parity error from Basic Engine to Serial"
60603
"Communication time-out error"
60604
"Unexpected response from Basic Engine"
60700
""
"BE stop command after reading failed"
61726
"BE difference found in data at disc sector
0xdiscsector"
61727
"This nucleus cannot be executed because the
Self-Test failed"
61800
""
61801
"BE i2c initialisation failed"
61802
"This nucleus cannot be executed because the
Self-Test failed"
60702
"Parity error from Basic Engine to Serial"
60703
"Communication time-out error"
61900
""
60704
"Unexpected response from Basic Engine"
61901
"The SelfTest failed with result: 0xnr1 0xnr2 0xnr3"
60800
""
61902
60801
"Basic
Engine
0xerrornumber"
"Basic
Engine
0xerrornumber"
61903
"Parity error from Basic Engine to Serial"
61904
"Communication time-out error"
error
"Parity error from Basic Engine to Serial"
number
61725
"Basic
Engine
0xerrornumber"
returned
error
number
60701
60802
returned
number
number
returned
error
number
EN 52
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Error Nr
Error String
Error Nr
Error String
61905
"Unexpected response from Basic Engine"
63100
" Number of times Tray went Open/Closed : nr1""
Total hours the CD laser was on : nr2"" Total hours
the DVD laser was on : nr3"" Total hours the write
laser was on : nr4"
63101
"Basic
Engine
0xerrornumber"
63102
"Parity error from Basic Engine to Serial"
62000
""
62001
"Self-Test
:
errorstring1 Laser-Test :
errorstring2 SpindleM-Test: errorstring3 SledgeM-Test : errorstring4 Focus-Test : errorstring5"
62100
"The forward sense level is 0xlevel"
62101
"Basic
Engine
0xerrornumber"
returned
error
number
returned
error
63103
"Communication time-out error"
"Parity error from Basic Engine to Serial"
63104
"Unexpected response from Basic Engine"
62103
"Communication time-out error"
63200
""
62104
"Unexpected response from Basic Engine"
63201
62200
""
"Basic
Engine
0xerrornumber"
62201
"The BE-self-diagnostic-spindle-motor-test failed"
63202
"Parity error from Basic Engine to Serial"
62102
62202
62203
"Basic
Engine
0xerrornumber"
returned
error
number
"Parity error from Basic Engine to Serial"
62204
"Communication time-out error"
62205
"Unexpected response from Basic Engine"
returned
error
"Communication time-out error"
63204
"Unexpected response from Basic Engine"
63300
Momentary errors (Byte 1 - Byte 7) : 0xb1 0xb2
0xb3 0xb4 0xb5 0xb6 0xb7 Cumulative errors
(Byte 1 - Byte 7): : 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6
0xb7 Fatal errors (Oldest - Youngest) : : 0xb1
0xb2 0xb3 0xb4 0xb5
63301
"Basic
Engine
0xerrornumber"
63302
"Parity error from Basic Engine to Serial"
""
62301
"The BE-focus-test failed"
62302
"Basic
Engine
0xerrornumber"
62303
"Parity error from Basic Engine to Serial"
63303
"Communication time-out error"
62304
"Communication time-out error"
63304
"Unexpected response from Basic Engine"
62305
"Unexpected response from Basic Engine"
63400
""
62400
""
63401
62401
"The BE-self-diagnostic-sledge-motor-test failed"
"Basic
Engine
0xerrornumber"
62402
"Basic
Engine
0xerrornumber"
63402
"Parity error from Basic Engine to Serial"
returned
error
error
number
number
returned
returned
error
error
63403
"Communication time-out error"
"Parity error from Basic Engine to Serial"
63404
"Unexpected response from Basic Engine"
62404
"Communication time-out error"
63500
""
62405
"Unexpected response from Basic Engine"
63501
62500
""
"Basic
Engine
0xerrornumber"
"Parity error from Basic Engine to Serial"
62403
number
63203
62300
returned
number
returned
error
number
number
number
62600
""
63502
62700
"BE EEPROM address = address -> Byte value =
0xvalue"
63503
"Communication time-out error"
63504
"Unexpected response from Basic Engine"
62701
"Basic
Engine
0xerrornumber"
63505
"errorstring ÖThe basic engine will reject all player
commands"
62702
"Parity error from Basic Engine to Serial"
63900
""
62703
"Communication time-out error"
63901
62704
"Unexpected response from Basic Engine"
"Basic
Engine
0xerrornumber"
62705
"BE read EEPROM; invalid input"
63902
"Parity error from Basic Engine to Serial"
62800
""
63903
"Communication time-out error"
62801
"Basic
Engine
0xerrornumber"
63904
"Unexpected response from Basic Engine"
62802
"Parity error from Basic Engine to Serial"
62803
"Communication time-out error"
returned
returned
error
error
number
number
returned
error
64000
"BE OPU number = opunumber"
64001
"Basic
Engine
0xerrornumber"
"Parity error from Basic Engine to Serial"
returned
error
number
number
62804
"Unexpected response from Basic Engine"
64002
62805
"BE write EEPROM; invalid input"
64003
"Communication time-out error"
62900
""
64004
"Unexpected response from Basic Engine"
62901
"Basic
Engine
0xerrornumber"
64100
"The data was successfully written on and read
from a DVD disc"
62902
"Parity error from Basic Engine to Serial"
64101
"The tray-in command failed"
62903
"Communication time-out error"
64102
"The read-TOC command failed"
62904
"Unexpected response from Basic Engine"
64103
"The VSM interrupt initialisation failed"
62905
"Radial loop could not be closed"
64104
"The set irq command failed"
63000
""
64105
"No disc or wrong disc inserted"
63001
"Basic
Engine
0xerrornumber"
returned
returned
error
error
number
number
64106
"The rec-pause command failed"
64107
"The VSM BE out DMA initialisation failed"
63002
"Parity error from Basic Engine to Serial"
64108
"The VSM BE out initialisation failed"
63003
"Communication time-out error"
64109
"The VSM BE out DMA start failed"
63004
"Unexpected response from Basic Engine"
64110
"The VSM BE out start failed"
64111
"The rec command failed"
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
5.
EN 53
Error Nr
Error String
Error Nr
Error String
64112
"The VSM out underrun error occurred"
71001
64113
"The record complete interrupt was not raised"
"Test of the AV Selector on the Analogue Board
fails."
64114
"The get irq command failed"
71002
"Communication with Analogue Board fails"
64115
"There was no interrupt raised by BE"
71100
"NVRAM test OK"
64116
"The VSM DMA did not finished"
71101
"Test of the NVRAM on the Analogue Board fails."
"The stop command after writing failed"
71102
"Communication with Analogue Board fails"
64118
"The VSM Sector processor initialisation failed"
71200
"Video routing on the Analogue Board OK"
64119
"The VSM sector processor DMA initialisation
failed"
71201
"Routing the video on the Analogue Board fails."
71202
"Invalid input."
64120
"The VSM sector processor DMA start failed"
71203
"Communication with Analogue Board fails"
64121
"The VSM sector processor start failed"
71300
"Audio routing on the Analogue Board OK"
64122
"The seek command failed"
71301
"Routing the audio on the Analogue Board fails."
64123
"The VSM sector processor error occurred"
71302
"Invalid input."
64124
"The read timeout occurred"
71303
"Communication with Analogue Board fails"
64125
"The stop command after reading failed"
71500
""
64126
"There was a difference found in data at a specific
disc sector"
71501
"Invalid slash version, default slash version is set."
71502
64127
"The result of the self test contains errors"
"Setting the slash version on the Analogue Board
fails."
64128
"An error interrupt was raised by BE"
71503
"Communication with Analogue Board fails"
64129
"The calibrate-record command failed"
71600
"ApplicationVersion"
64130
"To many retries"
71601
64131
"BE update RAI command after writing failed"
"Can not find segment in FLASH ROM on the Analogue Board"
64132
"BE find first recordable address command failed"
71602
"Communication with Analogue Board fails"
64133
"DVD+R disc is full"
71700
"DiagnosticsVersion"
64200
""
71701
"Can not find segment in FLASH ROM on the Analogue Board"
71702
"Communication with Analogue Board fails"
71800
"DownloadVersion"
71801
"Can not find segment in FLASH ROM on the Analogue Board"
71802
"Communication with Analogue Board fails"
72300
""
64117
64201
"BE i2c initialisation failed"
64202
"This nucleus cannot be executed because the
Self-Test failed"
70000
"Echo test OK"
70001
"Echo test returned wrong string."
70002
"Communication with Analogue Board fails"
70300
"SoftwareVersion"
72000
""
72001
"Adjusting BarGraphLevel failed"
"Communication with Analogue Board fails"
72002
"Communication with Analogue Board fails"
"HardwareVersion"
72100
""
70401
"Can not find segment in FLASH ROM on the Analogue Board"
72101
"Storing clock correction failed"
72102
"Value out of range : default value stored "
70402
"Communication with Analogue Board fails"
72103
"Invalid input."
70500
"Clock adjusted OK"
72104
"Communication with Analogue Board fails"
70501
"Can not adjust the clock on the Analogue Board."
72200
""
70502
"Wrong date/time text size."
72201
"Initialising the 1Hz signal on the Clock IC failed"
70503
"Communication with Analogue Board fails"
72202
"Communication with Analogue Board fails"
70600
"Tuner accessibility test OK"
72301
"Clearing the NVRAM on the Analogue Board fails"
70601
"Can not access tuner on the Analogue Board."
72302
"Communication with Analogue Board fails"
70602
"Communication with Analogue Board fails"
72400
"segment checksum is : checksum which is correct" for every segment
72401
"segment could not be found" or "segment checksum is : checksumC ,however it should be : checksumE" for every segment
70301
70302
70400
"Can not find segment in FLASH ROM on the Analogue Board"
70700
"Frequency download OK"
70701
"Wrong frequency table size."
70702
"Can not download the frequency table into the analogue NVRAM."
70703
"Can not download the frequency table into the analogue NVRAM."
72402
"Communication with Analogue Board fails"
72900
"Date received"
70704
"Communication with Analogue Board fails"
72901
"Data returned"
70800
"Data slicer test OK"
72902
70801
"Test of the Data slicer on the Analogue Board
fails."
"Communication on I2C-bus failed on the Analogue Board fails."
72903
"Communication with Analogue Board fails"
"Communication with Analogue Board fails"
73000
""
70900
"Sound Processor test OK"
73001
70901
"Test of the Sound Processor on the Analogue
Board fails."
"Storing the external presets on the Analogue
Board fails"
73002
"Communication with Analogue Board fails"
70902
"Communication with Analogue Board fails"
73100
71000
"AV Selector test OK"
"0xslashversion" where slashversion is the slash
version read from the analogue board
73101
"Error while reading out slash version."
70802
EN 54
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Error Nr
Error String
Error Nr
Error String
73102
"I2C Write error."
80311
for
73103
"I2C Read error."
"We
tried
to
receive
a
reply
DVIO_MAX_RETRIES_ACKREPLY times !!"
73104
"Communication with Analogue Board fails"
80312
"We
tried
to
receive
a
reply
DVIO_MAX_RETRIES_REPLY times !!"
for
80313
"We
tried
to
receive
an
DVIO_MAX_RETRIES_ACK times!!"
for
73200
""
73201
"Storing the Reference Voltage for the Tuner
failed"
73202
"Invalid input."
73203
"Communication with Analogue Board fails"
80000
"The DVIO module is present in the system."
80001
"The DVIO module is not present in the system."
80100
"The DVIO module has been reset OK."
80101
"The DVIO module is not present in the system."
80102
"The DVIO module could not be reset."
Ack
80314
"VSM UART error timeout transmitting command"
80315
"VSM UART error timeout receiving reply"
80316
"VSM UART frame error occurred receiving from
DVIO board"
80317
"VSM UART parity error occurred receiving from
DVIO board"
80318
"The confirmation/indication from the DVIO module
is invalid."
"The accessibility of the DVIO module is OK."
80103
"Could not initialise I2C before Reset."
80400
80200
"The accessibility of the DVIO module is OK."
80401
"The DVIO board is not present in this DVDR."
80201
"The DVIO board is not present in this DVDR."
80402
"Could not initialise I2C."
80202
"Could not initialise I2C."
80403
"Unable to reset the DVIO module."
80203
"Unable to reset the DVIO module."
80404
80204
"Unable to receive the reset indication from the
DVIO module."
"Unable to receive the reset indication from the
DVIO module."
80405
80205
"Unable to send the configuration to the DVIO
module."
"Unable to send the configuration to the DVIO
module."
80406
80206
"Unable to download the chip ID to the DVIO module."
"Unable to download the chip ID to the DVIO module."
80407
80207
"Unable to set the mode of the DVIO module to
IDLE."
"Unable to set the mode of the DVIO module to
IDLE."
80408
80208
"Software Error in function HandleStateAwaitingReply !!"
"Software Error in function HandleStateAwaitingReply !!"
80409
80209
"Maximal number of retries reached by HandleStateSending !!"
"Maximal number of retries reached by HandleStateSending !!"
80410
80210
"Maximal number of retries (NACKs) reached
(HandleStateSending)"
"Maximal number of retries (NACKs) reached
(HandleStateSending)"
80411
"We
tried
to
receive
a
reply
DVIO_MAX_RETRIES_ACKREPLY times !!"
for
"We
tried
to
receive
a
reply
DVIO_MAX_RETRIES_ACKREPLY times !!"
for
80211
80412
"We
tried
to
receive
a
reply
DVIO_MAX_RETRIES_REPLY times !!"
for
"We
tried
to
receive
a
reply
DVIO_MAX_RETRIES_REPLY times !!"
for
80212
80413
"We
tried
to
receive
an
DVIO_MAX_RETRIES_ACK times!!"
for
"We
tried
to
receive
an
DVIO_MAX_RETRIES_ACK times!!"
for
80213
80414
"VSM UART error timeout transmitting command"
80214
"VSM UART error timeout transmitting command"
80415
"VSM UART error timeout receiving reply"
80215
"VSM UART error timeout receiving reply"
80416
80216
"VSM UART frame error occurred receiving from
DVIO board"
"VSM UART frame error occurred receiving from
DVIO board"
80417
80217
"VSM UART parity error occurred receiving from
DVIO board"
"VSM UART parity error occurred receiving from
DVIO board"
80418
80218
"The confirmation/indication from the DVIO module
is invalid."
"The confirmation/indication from the DVIO module
is invalid."
80500
""
80300
"The accessibility of the DVIO module is OK."
80501
"The DVIO board is not present in this DVDR."
80301
"The DVIO board is not present in this DVDR."
80502
"The I2C could not be initialised."
80302
"Could not initialise I2C."
80503
"The DVIO module could not be reset."
80303
"Unable to reset the DVIO module."
80504
80304
"Unable to receive the reset indication from the
DVIO module."
"Unable to receive the reset indication from the
DVIO module."
80505
80305
"Unable to send the configuration to the DVIO
module."
"Unable to send the configuration to the DVIO
module."
80506
80306
"Unable to download the chip ID to the DVIO module."
"Unable to download the chip ID to the DVIO module."
80507
80307
"Unable to set the mode of the DVIO module to
IDLE."
"Unable to set the mode of the DVIO module to
IDLE."
80508
80308
"Software Error in function HandleStateAwaitingReply !!"
"Software Error in HandleStateAwaitingReply function!"
80509
80309
"Maximal number of retries reached by HandleStateSending !!"
"Maximal number of retries reached by HandleStateSending!"
80510
80310
"Maximal number of retries (NACKs) reached
(HandleStateSending)"
"Maximal number of retries (NACK's) reached
"(HandleStateSending)
80511
"We
tried
to
receive
a
reply
DVIO_MAX_RETRIES_ACKREPLY times!"
Ack
Ack
for
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
5.
EN 55
Error Nr
Error String
Error Nr
Error String
80512
"We
tried
to
receive
a
reply
DVIO_MAX_RETRIES_REPLY times!"
for
80709
"Maximal number of retries reached by HandleStateSending!"
80513
"We tried to receive an Acknowledge
DVIO_MAX_RETRIES_ACK times!"
for
80710
"Maximal number of retries (NACK's) reached
"(HandleStateSending)
80514
"VSM UART error timeout transmitting command"
80711
"VSM UART error timeout receiving reply"
"We
tried
to
receive
a
reply
DVIO_MAX_RETRIES_ACKREPLY times!"
for
80515
80516
"VSM UART frame error occurred receiving from
DVIO board"
80712
"We
tried
to
receive
a
reply
DVIO_MAX_RETRIES_REPLY times!"
for
80517
"VSM UART parity error occurred receiving from
DVIO board"
80713
"We tried to receive an Acknowledge
DVIO_MAX_RETRIES_ACK times!"
for
80518
"The confirmation/indication from the DVIO module
is invalid."
80714
"VSM UART error timeout transmitting command"
80715
"VSM UART error timeout receiving reply"
"Setting the DVIO module in/out diagnostics mode
failed"
80716
"VSM UART frame error occurred receiving from
DVIO board"
80520
"Invalid input"
80717
80521
"Getting the errors of the self-test failed"
"VSM UART parity error occurred receiving from
DVIO board"
80522
"Self-test failed"
80718
"The confirmation/indication from the DVIO module
is invalid."
80719
"Setting the DVIO module in/out diagnostics mode
failed"
90121
"Error: audio data in host memory contains wrong
frequency: frequency Hz"
80519
80600
""
80601
"The DVIO board is not present in this DVDR."
80602
"The I2C could not be initialised."
80603
"The DVIO module could not be reset."
80604
"Unable to receive the reset indication from the
DVIO module."
90122
"Error: audio data in host memory contains silence!"
80605
"Unable to send the configuration to the DVIO
module."
90123
"There is no correct audio frame in the buffer"
80606
"Unable to download the chip ID to the DVIO module."
90124
"The audio frame has an illegal version bit"
90125
"The audio frame has an illegal bitrate-index"
80607
"Unable to set the mode of the DVIO module to
IDLE."
90126
"The audio frame has an illegal sampling rate"
90127
"The CRC of the audio frame is wrong"
"Software Error in HandleStateAwaitingReply function!"
90128
"The audio frame is not MPEG-I layer II !"
90129
"Error cannot de-mute DAC on analogue board"
"Maximal number of retries reached by HandleStateSending!"
90200
""
90201
"Initialisation of I2C failed"
80610
"Maximal number of retries (NACK's) reached
"(HandleStateSending)
90202
"Initialisation of VIP and EMPIRE failed"
90203
"Initialisation of PLL / Link failed."
80611
"We
tried
to
receive
a
reply
DVIO_MAX_RETRIES_ACKREPLY times!"
for
90204
"Next descriptor address set wrong."
80612
"We
tried
to
receive
a
reply
DVIO_MAX_RETRIES_REPLY times!"
for
90205
"Turning on the colourbar failed"
90206
80613
"We tried to receive an Acknowledge
DVIO_MAX_RETRIES_ACK times!"
for
"No I2C communication possible to start video encoder."
80608
80609
80614
"VSM UART error timeout transmitting command"
80615
"VSM UART error timeout receiving reply"
80616
"VSM UART frame error occurred receiving from
DVIO board"
90207
"Starting the video encoder failed."
90208
"Transfer of data from video encoder to VSM
failed."
90209
"Stopping the encoder failed."
90210
"Turning off the colourbar failed."
"VSM UART parity error occurred receiving from
DVIO board"
90211
"Cannot intialize hostdecoder parallel input"
90212
"Cannot initialise VSM AV-out DMA port"
"The confirmation/indication from the DVIO module
is invalid."
90213
"Cannot initialise VSM AV-out port"
90214
"Cannot start VSM AV-out DMA port"
"Setting the DVIO module in/out diagnostics mode
failed"
90215
"Cannot start VSM AV-out port"
90216
"Transfer of data from VSM to host decoder failed."
80700
""
90217
80701
"The DVIO board is not present in this DVDR."
"VSM and Hostdec memory do not match (compared after transfer)"
90218
"Decoding of the video data in the hostdecoder
memory failed"
80617
80618
80619
80702
"The I2C could not be initialised."
80703
"The DVIO module could not be reset."
80704
"Unable to receive the reset indication from the
DVIO module."
90219
"The data in the hostdecoder is not equal to a colourbar"
80705
"Unable to send the configuration to the DVIO
module."
90220
"The video encoder did not return the Group Of
Picture count."
80706
"Unable to download the chip ID to the DVIO module."
90221
"The video encoder did not receive data from the
VIP."
80707
"Unable to set the mode of the DVIO module to
IDLE."
90223
"Initialisation of VIP and EMPRESS failed"
90224
"The video encoder did not return the current status."
80708
"Software Error in HandleStateAwaitingReply function!"
EN 56
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Error Nr
Error String
Error Nr
Error String
90225
"The video encoder timed out in BUSY mode. (no
VIP input)"
90429
"The video encoder did not switch from IDLE to
STOP mode."
90226
"The video encoder did not return the current bitrate."
90500
""
90501
"Initialisation of I2C failed"
"The video encoder did not switch to ENCODING
mode."
90502
"I2C communication to VIP failed"
90503
"Initialisation of VIP failed"
90228
"The video encoder could not start from STOP/
IDLE mode."
90504
"Generation of Close Caption data failed"
90229
"The video encoder did not switch from IDLE to
STOP mode."
90505
"VIP not locked to video signal"
90506
"Initialisation of VBI Extractor failed
90507
"No CC data received"
90508
"Closed Caption data overrun"
90227
90300
""
90301
"Initialisation of I2C failed"
90302
"I2C communication to VIP failed"
90303
"Initialisation of VIP failed"
90304
"Generation of Close Caption data failed"
90305
"VIP not locked to video signal"
90306
"Initialisation of VBI Extractor failed
90307
"No CC data received"
90308
"Closed Caption data overrun"
90309
"Closed Caption data does not match"
90310
"Switch off ColourBar failed"
90400
""
90509
"Closed Caption data does not match"
90510
"Switch off ColourBar failed"
90511
"Execution of the command on the analogue board
failed."
90600
""
90601
"Initialisation of I2C failed"
90602
"Initialisation of VIP and EMPIRE failed"
90603
"Initialisation of PLL / Link failed."
90604
"Next descriptor address set wrong."
90605
"Turning on the colourbar failed"
90606
"No I2C communication possible to start video encoder."
90401
"Initialisation of I2C failed"
90402
"Initialisation of VIP and EMPIRE failed"
90607
"Starting the video encoder failed."
90403
"Initialisation of PLL / Link failed."
90608
90404
"Next descriptor address set wrong."
"Transfer of data from video encoder to VSM
failed."
90405
"Turning on the colourbar failed"
90609
"Stopping the encoder failed."
90406
"No I2C communication possible to start video encoder."
90610
"Turning off the colourbar failed."
90611
"Cannot intialize hostdecoder parallel input"
90407
"Starting the video encoder failed."
90612
"Cannot initialise VSM AV-out DMA port"
90408
"Transfer of data from video encoder to VSM
failed."
90613
"Cannot initialise VSM AV-out port"
90614
"Cannot start VSM AV-out DMA port"
90615
"Cannot start VSM AV-out port"
90409
"Stopping the encoder failed."
90410
"Turning off the colourbar failed."
90411
"Cannot intialize hostdecoder parallel input"
90412
"Cannot initialise VSM AV-out DMA port"
90616
"Transfer of data from VSM to host decoder failed."
90617
"VSM and Hostdec memory do not match (compared after transfer)"
90618
"Decoding of the video data in the hostdecoder
memory failed"
90619
"The data in the hostdecoder is not equal to a colourbar"
90413
"Cannot initialise VSM AV-out port"
90414
"Cannot start VSM AV-out DMA port"
90415
"Cannot start VSM AV-out port"
90416
"Transfer of data from VSM to host decoder failed."
90417
"VSM and Hostdec memory do not match (compared after transfer)"
90620
"The video encoder did not return the Group Of
Picture count."
90418
"Decoding of the video data in the hostdecoder
memory failed"
90621
"The video encoder did not receive data from the
VIP."
90419
"The data in the hostdecoder is not equal to a colourbar"
90622
"Execution of the command on the analogue board
failed."
90420
"The video encoder did not return the Group Of
Picture count."
90623
"Initialisation of VIP and EMPRESS failed"
90624
"The video encoder did not return the current status."
90421
"The video encoder did not receive data from the
VIP."
90625
90422
"Execution of the command on the analogue board
failed."
"The video encoder timed out in BUSY mode. (no
VIP input)"
90626
90423
"Initialisation of VIP and EMPRESS failed"
"The video encoder did not return the current bitrate."
90424
"The video encoder did not return the current status."
90627
"The video encoder did not switch to ENCODING
mode."
90425
"The video encoder timed out in BUSY mode. (no
VIP input)"
90628
"The video encoder could not start from STOP/
IDLE mode."
90426
"The video encoder did not return the current bitrate."
90629
"The video encoder did not switch from IDLE to
STOP mode."
90427
"The video encoder did not switch to ENCODING
mode."
90700
""
90701
"Initialisation of I2C failed"
"The video encoder could not start from STOP/
IDLE mode."
90702
"I2C communication to VIP failed"
90428
90703
"Initialisation of VIP failed"
90704
"Generation of Close Caption data failed"
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
5.
EN 57
Error Nr
Error String
Error Nr
Error String
90705
"VIP not locked to video signal"
90919
"Error transfer data from VSM to host decoder"
90706
"Initialisation of VBI Extractor failed
90920
90707
"No CC data received"
"Error: audio data in host memory and VSM memory differ"
90708
"Closed Caption data overrun"
90921
"Error: audio data in host memory contains wrong
frequency: frequency Hz"
90922
"Error: audio data in host memory contains silence!"
90923
"There is no correct audio frame in the buffer"
90709
"Closed Caption data does not match"
90710
"Switch off ColourBar failed"
90711
"Execution of the command on the analogue board
failed."
90800
""
90801
"Error routing the audio back to the digital board."
90802
"Error cannot initialise I2C"
90803
"Error cannot initialise VIP"
90804
"Error cannot set ADC enable pin"
90805
"Error cannot set VSM audio clock"
90806
"Error preparing the 12kHz audio-sine"
90807
"Error cannot initialise audio encoder"
90808
"Error cannot initialise VSM audio in port"
90809
"Error cannot initialise VSM audio in DMA port"
90810
"Error cannot initialise VSM audio out DMA port"
90811
"Error cannot initialise audio VSM out port"
90812
"Error cannot initialise host decoder audio in"
90813
"Error loop audio user/dealer cannot start audio encoder"
90814
"Error cannot start VSM audio in DMA port"
90924
"The audio frame has an illegal version bit"
90925
"The audio frame has an illegal bitrate-index"
90926
"The audio frame has an illegal sampling rate"
90927
"The CRC of the audio frame is wrong"
90928
"The audio frame is not MPEG-I layer II !"
90929
"Error cannot de-mute DAC on analogue board"
140000
""
140001
"I2C to Clock failed" or "I2C initialisation failed"
140100
""
140101
"I2C to Clock failed" or "I2C initialisation failed"
141200
""
141201
"Progressive Scan Board I2C bus busy"
141211
"Progressive Scan Board I2C FLI2200 bus busy"
141212
"Progressive Scan Board I2C FLI2200 read access
time-out"
141213
"Progressive Scan Board I2C FLI2200 no read acknowledge"
141214
"Progressive Scan Board I2C FLI2200 read failed"
141215
"Progressive Scan Board I2C FLI2200 write access time-out"
141216
"Progressive Scan Board I2C FLI2200 no write acknowledge"
90815
"Error starting the 12kHz audio-sine"
90816
"Error transfer data from audio encoder to VSM"
90817
"Error cannot start VSM AV out DMA port"
90818
"Error cannot start VSM AV out port"
90819
"Error transfer data from VSM to host decoder"
90820
"Error: audio data in host memory and VSM memory differ"
141217
"Progressive Scan Board I2C FLI2200 write failed"
141218
"Progressive Scan Board I2C FLI2200 failed"
"Error: audio data in host memory contains wrong
frequency: frequency Hz"
141221
"Progressive Scan Board I2C AD7196 bus busy"
141222
"Progressive Scan Board I2C AD7196 read access
time-out"
141223
"Progressive Scan Board I2C AD7196 no read acknowledge"
90821
90822
"Error: audio data in host memory contains silence!"
90823
"There is no correct audio frame in the buffer"
90824
"The audio frame has an illegal version bit"
141224
"Progressive Scan Board I2C AD7196 read failed"
90825
"The audio frame has an illegal bitrate-index"
141225
90826
"The audio frame has an illegal sampling rate"
"Progressive Scan Board I2C AD7196 write access time-out"
141226
"Progressive Scan Board I2C AD7196 no write acknowledge"
90827
"The CRC of the audio frame is wrong"
90828
"The audio frame is not MPEG-I layer II !"
90829
"Error cannot de-mute DAC on analogue board"
141227
"Progressive Scan Board I2C AD7196 write failed"
90900
""
141228
"Progressive Scan Board I2C AD7196 failed"
90901
"Error routing the audio back to the digital board."
141300
""
90902
"Error cannot initialise I2C"
141301
"Progressive Scan Route Enable failed"
90903
"Error cannot initialise VIP"
141302
"Generating test image in Hostdecoder failed"
90904
"Error cannot set ADC enable pin"
141400
""
90905
"Error cannot set VSM audio clock"
141401
"Progressive Scan Route Disable failed"
90906
"Error preparing the 12kHz audio-sine"
141402
"Turning off test image in Hostdecoder failed"
90907
"Error cannot initialise audio encoder"
141500
""
90908
"Error cannot initialise VSM audio in port"
141501
"Progressive Scan Board I2C failed"
90909
"Error cannot initialise VSM audio in DMA port"
141600
""
90910
"Error cannot initialise VSM audio out DMA port"
141601
"Progressive Scan Board I2C failed"
90911
"Error cannot initialise audio VSM out port"
90912
"Error cannot initialise host decoder audio in"
90913
"Error loop audio user/dealer cannot start audio encoder"
90914
"Error cannot start VSM audio in DMA port"
90915
"Error starting the 12kHz audio-sine"
90916
"Error transfer data from audio encoder to VSM"
90917
"Error cannot start VSM AV out DMA port"
90918
"Error cannot start VSM AV out port"
5.5
Loop tests
The following loops can be distinguished:
• Loops performed on the digital board only
• User Dealer loops performed on the digital and analogue
board
• System loops performed via an external connection:
outputs are looped back to the inputs.
EN 58
5.5.1
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Nucleus 900: Digital Audio Loop
This nucleus tests the audio path through the digital board
NUCLEUS 901: AUDIO USER DEALER LOOP
NUCLEUS 900: AUDIO LOOP DIGITAL
ANALOGUE BOARD
ANALOGUE BOARD
7507
7002
STV6410
7004
7100
ADC
DAC
1900
connector
1900
connector
1602
connector
1602
connector
DIGITAL BOARD
7500
I2S
VIP
7500
7200
VIP
VIP_ICLK: 27MHz
STI 5508
7403
EMPRESS
7403
EMPRESS
7100
VSM
7100
VSM
GND
CL 16532145_037.eps
031201
CL 16532145_036.eps
031201
Figure 5-9
5.5.2
7200
STI 5508
VIP_ICLK: 27MHz
DIGITAL BOARD
I2S
Nucleus 901: Audio User Dealer Loop
A PCM audio sine of 12kHz is generated in the Host Decoder
for a while and sent to the analogue board. The signal coming
from the analogue board is encoded again and sent to the
memory of the host decoder for comparison. This nucleus tests
the components on the audio signal path:
• Host decoder
• Flex connection between connector 1602 (digital board)
and connector 1900 (analogue board)
• DAC
• Op-amp
• Scart switch IC
• ADC
• Audio Encoder
• VIP
• VSM
Figure 5-10
Diagnostic Software and Faultfinding Trees
5.5.3
Nucleus 902: Digital Video Loop
A colourbar generated in the host decoder is looped through
the VIP, Empire, and VSM and checked again in the host
decoder. The following components are tested on the video
signal path:
• VIP
• Empire
• VSM
• Host decoder
NUCLEUS 902: DIGITAL VIDEO LOOP
ANALOGUE BOARD
7507
STV6410
DIGITAL BOARD
7500
7200
VIP
VIP_ICLK: 27MHz
STI 5508
7403
EMPRESS
7100
VSM
CL 16532145_038.eps
031201
Figure 5-11
DVDR980-985 /0X1
5.
EN 59
EN 60
5.5.4
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Nucleus 903: Digital Video VBI Loop
5.5.5
Nucleus for testing the components on the video VBI signal
path:
• The VIP
• The VSM
• The Host Decoder
This is done by using the internal test signal source (digital
board only)
Remark: this test is only successful if nucleus 121 is carried out
first.
Nucleus 904: System Video Loop
Nucleus for testing the components on the video signal system
path:
• The VIP
• The video encoder
• The VSM
• The host decoder
• The analogue board
On the analogue board the video signal will be routed to the
SCART (EUROPE) or CINCH (NAFTA). There it will be looped
back externally by means of the proper cable
NUCLEUS 903: DIGITAL VIDEO VBI LOOP
NUCLEUS 904: SYSTEM VIDEO LOOP
ANALOGUE BOARD
SCART AUX
SCART TV
ANALOGUE BOARD
7507
STV6410
7507
STV6410
1954
1954
connector
connector
DIGITAL BOARD
1601
7500
7200
VIP
VIP_ICLK: 27MHz
STI 5508
7500
connector
DIGITAL BOARD
VIP
VIP_ICLK: 27MHz
7200
STI 5508
7100
7403
EMPRESS
1601
connector
VSM
7403
EMPRESS
7100
VSM
CL 16532145_039.eps
031201
CL 16532145_040.eps
121201
Figure 5-12
Figure 5-13
Diagnostic Software and Faultfinding Trees
5.5.6
Nucleus 905: System Video VBI Loop
5.5.7
This nucleus tests the components on the video signal path:
• The VIP
• The VSM
• The Host Decoder
The video CVBS signal is routed to the output of the analogue
board where it will be looped back by means of an external
cable
Remark: this test is only successful if nucleus 121 is carried out
first.
DVDR980-985 /0X1
EN 61
Nucleus 906: Video User Dealer Loop
Nucleus for testing the components on the video signal system
path:
• The VIP
• The video encoder
• The VSM
• The host decoder
• The analogue board
On the analogue board, the video signal is internally routed
back to the digital board.
NUCLEUS 906: VIDEO USER DEALER LOOP
NUCLEUS 905: SYSTEM VIDEO VBI LOOP
SCART AUX
5.
SCART TV
ANALOGUE BOARD
ANALOGUE BOARD
7507
7507
STV6410
STV6410
1954
1954
connector
1601
VIP
VIP_ICLK: 27MHz
EMPRESS
connector
7200
STI 5508
7403
connector
1601
connector
DIGITAL BOARD
1954
connector
1601
connector
7500
1954
connector
7100
VSM
1601
DIGITAL BOARD
7500
7200
VIP
VIP_ICLK: 27MHz
STI 5508
7100
7403
EMPRESS
VSM
CL 16532145_042.eps
031201
CL 16532145_041.eps
031201
Figure 5-14
connector
Figure 5-15
EN 62
5.5.8
5.
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
Nucleus 907: Video VBI User Dealer Loop
5.5.9
This nucleus tests the components on the video VBI signal
path:
• The VIP
• The VSM
• The Host Decoder
The signal is routed back internally on the analogue board
Remark: this test is only successful if nucleus 121 is carried out
first.
Nucleus 908: System Audio Loop Scart (Europe)
Nucleus for testing the components on the audio signal path:
• The hostdecoder
• The analogue board
• The audio encoder
• The VSM
On the analogue board, audio is passed to the SCART
connector, where a SCART cable needs to be used to loop
back the audio signal to the digital board
NUCLEUS 907: VIDEO VBI USER DEALER LOOP
NUCLEUS 908: SYSTEM AUDIO LOOP SCART
SCART AUX
ANALOGUE BOARD
SCART TV
ANALOGUE BOARD
7507
7507
STV6410
7002
STV6410
7100
7004
DAC
ADC
1954
1954
1601
1601
connector
7200
STI 5508
7100
7403
1602
connector
DIGITAL BOARD
7500
VIP_ICLK: 27MHz
connector
1602
connector
connector
DIGITAL BOARD
VIP
1900
1900
connector
connector
connector
VSM
7500
7200
VIP
VIP_ICLK: 27MHz
STI 5508
7403
EMPRESS
7100
VSM
EMPRESS
CL 16532145_043.eps
031201
Figure 5-16
CL 16532145_044.eps
121201
Figure 5-17
Diagnostic Software and Faultfinding Trees
5.5.10 Nucleus 909: System Audio Loop CINCH (Nafta)
Nucleus for testing the components on the audio signal path:
• The hostdecoder
• The analogue board
• The audio encoder
• The VSM
On the analogue board the audio is passed to the CINCH
connector, where a CINCH cable needs to be used to loop back
the audio signal to the digital board
NUCLEUS 909: SYSTEM AUDIO LOOP CINCH
CINCH OUT
(NAFTA)
CINCH IN
(NAFTA)
ANALOGUE BOARD
7507
STV6410
7002
7100
7004
DAC
ADC
1900
1900
connector
1602
connector
connector
DIGITAL BOARD
1602
connector
7500
7200
VIP
VIP_ICLK: 27MHz
STI 5505
7403
EMPRESS
7100
VSM
CL 16532145_045.eps
031201
Figure 5-18
DVDR980-985 /0X1
5.
EN 63
EN 64
5.
DVDR980-985 /0X1
5.6
Faultfinding trees
5.6.1
General
Diagnostic Software and Faultfinding Trees
PLAYBACK MODE
Plug Recorder
to the mains.
No disc loaded
Standby LED changes
from green to red.
Display shows time
NOK
Check PSU(see chapter 5.6.2)
Check Analog PCB(see chapter 5.6.4)
Check Front PCB(see chapter 5.6.5)
NOK
Check Trade Mode(see chapter 5.2.4)
Check Front PCB(see chapter 5.6.5)
Check Digital PCB(see chapter 5.6.3)
NOK
Check Front PCB(see chapter 5.6.5)
Check Basic Engine(see chapter 5.6.3)
NOK
Check Digital PCB(see chapter 5.6.3)
Check Basic Engine(see chapter 5.6.3)
NOK
Check Digital PCB(see chapter 5.6.3)
Check Analog PCB(see chapter 5.6.4)
OK
Press "STOP" button
Standby LED changes
from Red to Green.
Display shows successively
"READING"
"NO DISC"
OK
Press "OPEN/CLOSE" button
Display shows successively
"OPENING"
"TRAY OPEN"
Tray is open
OK
Insert DVD Disc
Press "OPEN/CLOSE" button
Display shows successively
"CLOSING"
"READING"
Recorder starts playback of
DVD-disc
OK
Audio & Video OK ?
OK
Playback DVD OK
CL 16532095_243.eps
170801
Figure 5-19
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
5.
EN 65
RECORD MODE
Insert DVDR Disc
Display shows:
- Disc content
- Source
- DVD+RW
- Disc Bar
NOK
- Check Basic Engine(see chapter 5.6.3)
OK
Press NEXT button to
select empty title
Press "RECORD" button
Recording starts
NOK
OK
- Check Analog PCB(see chapter 5.6.4)
- Check Digital PCB(see chapter 5.6.3)
- Check Basic Engine(see chapter 5.6.3)
- Check DVDR Disc
Press "STOP" button
Menu update
Check recorded title
NOK
- Check Basic Engine(see chapter 5.6.3)
- Check DVDR Disc
OK
Recording OK
CL 16532095_242.eps
170801
Figure 5-20
EN 66
5.6.2
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Power supply
Remove all the connectors from the PSU
Check DC voltages on connector 0205:
+12Vstby, +5V2stby, -5Nstby, -Vgnstby, +33Vstby
None of the voltages are present
+12Vstby and +5V2stby are oke.
All voltages are present.
Check +12Vreg circuit:
- D6210, C2210, C2212
Check +Vreg circuit:
- D6240, C2240, C2242
Check Prot_3V3 circuit:
- D6215, C2214, C2215,
- R3520, R3521, D6520
Check +33Vstby circuit:
- D6200, C2200, R3200, D6201, R3201
Check -5Nstby circuit:
- D6220, C2220, IC7220, C2222, C2221
Check FLYB circuit:
- D6221, T7241, R3220, R3221, R3222,
R3223.
Check -Vgnstby circuit:
- D6230, C2230, R3230, D6231, R3233,
R3234, C2235.
Standby voltages are oke. Check DC
voltages on connectors 0207 and 0209.
Connector 0207:
+3V3, +5V, -5V, +12V.
Connector 0209:
+3V3, +12V, +5V, -5V, STBY_ctrl.
Connect PSU to a mains isolated variac.
Turn the input voltage up and measure
voltage across C2125. Do not exceed
max. mains voltage indicated on player.
This voltage must be +/- 1.41 x Vin AC.
If not oke, check supply path of failed
supply voltages.
Check if STBY_ctrl is LOW.
- Check standby control path via digital
board to analog board.
Check primary circuit:
- F1120, D6151, D6152, D6153, D6154,
- R3120, L5120, L5520, C2125.
If fuse 1120 is defective, always check
Q7125, D6145, T7140, Rsense (R3133,
R3134, R3135, R3136 and R3137).
Check with an oscilloscope Vds and Vg
of Q7125.
NO
Is PSU ticking?
YES
Check power switch circuit:
- Q7125, D6130, D3131, D6132
- D6145, D6146, L5125
- C2136
- R3131, R3132, R3133, R3134
- R3135, R3136, R3137, R3146
Check start-up circuit:
- R3125, R3126, R3141, R3132
- Q7125, L5131, R3150, C2146
Check +12V circuit:
must be present for the other voltages
- Q7511, T7512, D6511, D6512,
- R3511, R3513, R3514, L551, C2512.
Check +3V3 circuit:
- Q7520, Q7521, L5520, C2521, F1520,
- R3522, R3523, R3524, R3525, C2520.
Check +5V circuit:
- Q7501, Q7502, L5501, C2502, R3501
- R3502, R3503, R3504, C2540.
Check +3V3E circuit:
- Q7505, Q7506, D6505, L5505, C2506,
- R3505, R3506, R3507, R3508, C2502.
Check -5V circuit:
- Q7515, D6515, L5515, C2515, R3515.
If oke, the power supply seems to be ok.
Check the other boards in the player
for the cause of the overload.
Check Control circuit
- T7140, D6141, D6142, L5131,
- C2144, C2145, C2147, C2151
- R3151, R3147, R3148, R3150
Check Regulation circuit
- T7251, Q7200, R3250, R3253
- R3254, R3255, R3256, C2251
Check Overvoltage circuit
- T7142, D6143, D6144,
- R3149, R3144, C2152, C2142
Check Overload circuit
- T7141, T7143, R3145, R3143,
- R3142, C2143.
CL 16532095_085.eps
150801
Figure 5-21
Digital board
Diagnostic Software and Faultfinding Trees
5.6.3
Digital Board
Start-up DSW
START UP DSW
NOT OK
OK
Check Power Supplies on con. 1900
(ION should be LOW)
NOK
- Check connection to PSU
- Check Power Supply
OK
Check that Sysclk_5505 on I819
appears earlier then Resetn_5505
is high on I202
NOK
- Check IC 7202
- Check IC 7916-C
- Check IC 7801
OK
Check VDD_STi(+3V3) on I272
Check VDDA(+3V3) on I275
Check VDDA_PCM(+3V3) on I252
NOK
- Check IC 7202
- Check R 3266
- Check L 5200, 5201 and 5202
OK
Check EMI_PROCCLK(50MHz)
on I181
NOK
- Check IC 7100
OK
Check if F201 is HIGH and I201 is LOW
Check if I208 is LOW and I209 is HIGH
NOK
- Check IC 7202
- Check L 5200
OK
Check TCK (HIGH) on I247
Check TDI (HIGH) on I248
Check TMS (HIGH) on I249
Check TRST (LOW) on I250
NOK
- Check IC 7202
OK
Check if service pin is LOW on testpoint I207
NOK
- Check Jumper 4206
OK
Check VDD_MEM(+3V3) on I306
Check VDD_MEM1(+3V3) on I310
NOK
- Check L 5300
- Check L 5302
NOK
- Check L 5100
- Check L 5101
NOK
- Check IC 7202
- Check IC 7305
OK
Check VCC3_VSM(+3V3) on I100
Check VCC3_VSM_MEM(+3V3) on I141
OK
Check LOW pulses on EMI_CE3n
on pin 126 of IC 7202
OK
Check activity on EMI_CE3n(pin1 of IC 7305)
Check activity on ROMH_CEn(pin6 of IC 7305)
Check activity on EMI_OEn(pin29 of IC 7301)
NOK
- Check IC 7305
- Check IC 7301
- Check IC 7202
OK
Check if FLASH_OEn is LOW on I245
Check if EMI_RWn is HIGH(pin133 of IC7202)
NOK
- Check IC 7202
- Check IC 7302 and IC 7304
- Check IC 7100
OK
Check for short circuits or open circuits on the
IC pins which are connected to the EMI-bus
OK
START UP DSW
OK
CL 16532095_086.eps
150801
Figure 5-22
DVDR980-985 /0X1
5.
EN 67
EN 68
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Power part check
POWER PART CHECK DIGITAL BOARD
USE DIGITAL BOARD CIRCUIT DIAGRAMS 1 2, 3, 4, 5, 7 AND 8 AND DIGITAL BOARD BOTTOM VIEW TESTPOINTS
Power On and exit
stand-by mode
OK
Check +3V3 on Testpoints I905
Check +12V on Testpoint I907
Check +5V on Testpoint I906
Check -5V on Testpoint I908
NOK
OK
NOK
Vcc3_VSM(+3V3) on testpoint I100
Vcc3_VSM_mem(+3V3) on testpoint I141
Vdd_sti(+3V3) on tespoint I244
check L5100
NOK
NOK
check L5101
check L5200
OK
NOK
Vdd_flash_L(+3V3) on testpoint I304
Vdd_flash_H1(+3V3) on testpoint I301
check L5300
NOK
check L5302
OK
VDD_EMP(+3V3) on tespoint I413
NOK
VDD_EMP_CORE(+3V3) on tespoint I412
check L5404
NOK
check IC7404
OK
VDDA_7118(+3V3) on testpoint I509
NOK
VDDA_1A_7118(+3V3) on testpoint I508
VDDA_2A_7118(+3V3) on testpoint I510
VDDA_3A_7118(+3V3) on testpoint I513
VDDA_4A_7118(+3V3) on testpoint I514
VDDX_7118(+3V3) on testpoint I518
check L5507
NOK
check L5500
NOK
check L5501
NOK
check L5502
NOK
NOK
check L5503
check L5508
OK
VDDE_7118(+3V3) on testpoint I511
VDDI_7118(+3V3) on testpoint I515
VDD_LVC32(+3V3) on testpoint I526
NOK
NOK
NOK
check L5506
check L5505
check L5504
OK
VDD5_OSC(+5V) on tespoint I925
VCC5_4046(+5V) on testpoint I130
NOK
NOK
VCC3_CLK_BUF(+3V3) on testpoint I930
check L5905
check L5103
NOK
check L5907
OK
Power Part OK
CL 16532145_046.eps
031201
Figure 5-23
- Check connection to PSU
- Check PSU
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
5.
EN 69
Reset and Clock Check
RESET & CLOCK CHECK DIGITAL BOARD
USE DIGITAL BOARD CIRCUIT DIAGRAMS 1,2,7 AND 8 AND DIGITAL BOARD BOTTOM VIEW TESTPOINTS
Power on and exit
stand-by mode
Resetn(+3V3) on testpoint I912
NOK
- Check IC7902
- Check D6900
- Check R3924 and R3925
OK
Resetn_BE(+3V3) on testpoint I126
Resetn_DVIO(+3V3) on testpoint I659
Resetn_VE(+3V3) on testpoint I206
NOK
- Check IC7702
- Check IC7200
- Check IC7403
OK
Sysclk_VSM_5508(27MHz) on testpoint I917
Sysclk_ProgScan(27MHz) on testpoint I920
Sysclk_Empress(27MHz) on testpoint I924
NOK
- Check Oscillator 7906
- Check IC7904
- Check R3906, R3908 and R3917
OK
ACC_ACLK_PLL(12MHz) on testpoint I902
NOK
- Check Oscillator 7906
- Check IC7900
- Check R3901
OK
ACC_ACLK_OSC(12MHz) on testpoint I143
NOK
- Check IC7102
- Check R3125
OK
EMI_PROCCLK(60MHz) on testpoint I170
NOK
- Check IC7200
- Check R3208
- Check IC7100
OK
VIP_ICLK(27MHz) on testpoint I101
NOK
- Check IC7500
- Check IC7100
- Check R3505
OK
Reset- & clock signals are OK
Figure 5-24
CL 16532145_047.eps
031201
EN 70
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
DSW Memory Tests
DSW MEMORY TESTS
Start Diagnostic Software
and select Command mode
Flash Checksum
Command: 100
NOK
- Check IC 7301
- Check IC 7302
OK
Flash 1 Write Access
Command: 101
NOK
- Check IC 7301
OK
Flash 2 Write Access
Command: 102
NOK
- Check IC 7302
OK
Flash Write/Read
Command: 103
NOK
- Check IC 7301
- Check IC 7302
OK
SDRAM Write/Read
Command: 104
NOK
- Check IC 7300
OK
SDRAM Write/Read fast
Command: 105
NOK
- Check IC 7300
OK
NVRAM I2C Test
Command: 123
NVRAM Write Read Test
Command: 122
NOK
- Check I2C-signals
- Check 7201
OK
MEMORY PART OK
CL 16532145_048.eps
031201
Figure 5-25
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
5.
EN 71
DSW VSM Tests
DSW VSM TESTS
Start Diagnostic Software
and select Command mode
VSM Interconnection Test
Command: 304
NOK
- Check IC 7100
OK
SDRAM Access Test
Command: 301
NOK
- Check IC 7101
OK
SDRAM Write/Read Test
Command: 302
NOK
- Check IC 7100
- Check IC 7101
NOK
- Check IC 7100
- Check IC 7101
OK
VSM Interrupt Test
Command: 303
OK
VSM Connection to analog board Test
Command: 305
NOK
- Check IC 7100
- Check connection to analog
board
OK
VSM PART OK
CL 16532145_049.eps
031201
Figure 5-26
EN 72
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
DSW Audio Part Check
DSW AUDIO PART CHECK
Start Diagnostic Software
and select Command mode
Audio Clock Test
Command: 1400
Measure ACC_ACLK_PLL on I902
(11.289MHz)
NOK
- Check IC 7900
- Check IC 7906
- Check IC 7100
OK
Audio Clock Test
Command: 1401
Measure ACC_ACLK_PLL on I902
(12.288MHz)
NOK
- Check IC 7900
- Check IC 7906
- Check IC 7100
OK
Host Pink Noise ON
Command: 115
Check AD_BCLK(3.072MHz) on pin14 of con.1602
Check AD_WCLK(48KHz) on pin12 of con.1602
Check AD_ACLK(12.288MHz) on pin9 of con.1602
Check AD_DATAO(Activity) on pin11 of con.1602
Check AD_SPDIF33(Activity) on pin2 of con.1602
NOK
- Check IC 7202
- Check IC 7200
NOK
- Check IC 7202
- Check IC 7200
NOK
- Check IC 7100
- Check IC 7403
OK
Host Pink Noise OFF
Command: 116
Check AD_BCLK(3.072MHz) on pin14 of con.1602
Check AD_WCLK(48KHz) on pin12 of con.1602
Check AD_ACLK(12.288MHz) on pin9 of con.1602
Check AD_DATAO(No Activity) on pin11 of con.1602
Check AD_SPDIF33(No Activity) on pin2 of con.1602
OK
Audio I2S Encoding Path Test
Command: 900
Check AE_BCLK(3.072MHz) on pin21 of con.1602
Check AE_WCLK(48KHz) on pin20 of con.1602
Check AE_DATAI(Activity) on pin18 of con.1602
Check AE_DATAO(Activity) on testpoint I155
Check AE_ACLK on pin16 of con. 1602
OK
Video Encoding Path Test
Command: 902
Check VIP_ICLK(27MHz) on testpoint I101
Check VIP_VS(50Hz) on pin1 of IC7502
Check VE_DSn(Activity) on testpoint I104
Check VE_DTACKn(Activity) on testpoint I103
NOK
- Check IC 7100
- Check IC 7500
- Check IC 7502
OK
Mute ON Test --> Command: 109
Check Mute level(high) on testpoint I609
Mute OFF Test --> Command: 110
Check Mute Level(low) on testpoint I609
NOK
- Check IC 7200
- Check IC 7202
OK
AUDIO PART OK
CL 16532145_050.eps
031201
Figure 5-27
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
5.
EN 73
DSW Vidoe Part Check
DSW VIDEO PART CHECK
Start Diagnostic Software
and select Command mode
Gateway Test to Analog Board
Command: 700
NOK
- Check Analog Board
- Check IC 7100
OK
Color Bar ON Test
Command: 120
OK
Check Red Video Out on pin 5 of con.1601
Check Green Video Out on pin 3 of con.1601
Check Blue Video Out on pin 1 of con.1601
Check CVBS Video Out on pin 11 of con.1601
Check Y-Video Out on pin 9 of con.1601
Check C-Video Out on pin 7 of con.1601
NOK
- Check T7600, T7601, T7603
T7604, T7605 and T7606
- Check IC 7200
OK
Check HSYNC on testpoint I221
Check VSYNC on testpoint I701
NOK
- Check IC 7200
- Check IC 7701
- Check IC 7702
OK
Color Bar OFF Test
Command: 121
OK
VBI(Vertical Blanking Interval) Loopback Test
Command: 903
Check the Color Bar on the TV creen
NOK
- Check IC 7200
- Check IC 7500
- Check IC 7100
OK
VIDEO PART OK
CL 16532145_051.eps
031201
Figure 5-28
EN 74
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
DSW Video Part Check Progressive Scan
VIDEO PART CHECK PROGRESSIVE SCAN
Start Diagnostic Software
and select Command mode
Generate NTSC Testpicture
Command: 135 10 1
Switch off Macrovision
Command: 137
Route PS to Analog Board
Command: 1415
Route Video on Analog Board
Command: 712
Check activity on Yy_OUT(0:7) of IC7801
Check activity on Cr_OUT(0:7) of IC7801
Check activity on Cb_OUT(0:7) of IC7801
NOK
- Check IC 7800
- Check IC 7801
NOK
- Check IC 7701 and IC 7702
- Check IC 7200
OK
Check HSOUT on testpoint I824
Check VSOUT on testpoint I825
OK
Check DAC-A/Y on testpoint I808
Check DAC-B on testpoint I809
Check DAC-C on testpoint I812
NOK
- Check IC 7801
OK
Check Y-signal on testpoint I821
Check Cb-signal on testpoint I822
Check Cr-signal on testpoint I823
NOK
- Check IC 7802
- Check IC 7803
- Check R3801, R3812 and R3819
OK
Video Part Progressive Scan OK
Figure 5-29
CL 265362011_023.eps
160102
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
5.
EN 75
DSW Basic Engine Check
DSW BASIC ENGINE TESTS
Start Diagnostic Software
and select Command mode
Basic Engine S2B Echo Test
Command: 601
NOK
- Check IC 7202
- Check Basic Engine
OK
Basic Engine Tray Open Test
Command: 616
NOK
- Check Basic Engine
OK
Insert a DVDRW video disc
OK
Basic Engine Tray Close Test
Command: 615
NOK
- Check Basic Engine
OK
Basic Engine S2B Write Read Test
Command: 617
NOK
- Check Basic Engine
- Check IC 7100
OK
BASIC ENGINE PART OK
Figure 5-30
CL 16532095_094.eps
150801
EN 76
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Waveforms
Waveforms Digital Board
Sysclk_VSM
2V / div DC
20ns / div
Sysclk_5505
2V / div DC
27M_clk_PS
2V / div DC
20ns / div
acc_aclk_pll
2V / div DC
EMI_PROCCLK
2V / div DC
10ns / div
50ns / div
DSP_clk
2V / div DC
VIP_ICLK
2V / div DC
20ns / div
10ms / div
VSM_M_CLK
20ns / div
2V / div DC
20ns / div
CL 16532145_053.eps
031201
Figure 5-31
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
5.
EN 77
Waveforms Digital Board
AD_WCLK; AE_WCLK
2V / div AC
10us / div
AD_DATAO; AE_DATAO; AE_DATAI
2V / div AC
5us / div
R_OUT
200mV / div AC
20us / div
20us / div
VSYNC
2V / div DC
2V / div AC
200ns / div
AD_SPDIF
2V / div AC
250ns / div
G_OUT
CVBS_OUT
200mV / div AC
AD_BCLK; AE_BCLK
200mV / div AC
2V / div AC
I401
50ns / div
VIP_VS
2V / div DC
5ms / div
B_OUT
20us / div
Y_OUT
200mV / div AC
AD_ACLK
200mV / div AC
20us / div
C_OUT
20us / div
200mV / div AC
20us / div
HSYNC
20ms / div
2V / div DC
Figure 5-32
20ms / div
CL 16532145_054.eps
031201
EN 78
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Waveforms Digital Board
DAC-B
500mV / div AC
10us / div
DAC-C
500mV / div AC
10us / div
10us / div
2V / div DC
10ms / div
20us / div
2V / div DC
10ms / div
500mV / div AC
10us / div
2V / div DC
10ms / div
YUV_IN
Cb-signal
10us / div
500mV / div AC
VSOUT
VS_IN
Y-signal
500mV / div AC
500mV / div AC
HS_IN
FRAME_IN
2V / div DC
Cr-signal
DAC-A/Y
2V / div DC
10ms / div
HSOUT
10us / div
2V / div DC
10us / div
Y_OUT; Cr_OUT; Cb_OUT
2V / div DC
CL 16532145_055.eps
031201
20us /div
Figure 5-33
MP
F800
F3201
F3202
F3203
F3204
F3205
F3206
F3207
F0017
F0001
F803
F900
F902
F8111
F303
F9336
F8105
F8107
F810
F811
F8104
F8101
F8110
F5306
F8102
F8202
F8203
F8204
F8205
F8108
F8109
F8201
F513
F517
F519
F534
F525
F5001
F5003
F5004
F5019
F5021
F516
F518
F531
X
Y
Signal
Signal
Name
Description
F_MODE
Fact. Mode
12V
12 V Supply
5V
5 V Supply
5NSTBY
5 V Supply
VGNSTBY
Supply GND
33STBY
33 V Supply
FLYB
Controls PS
GNDA
Ground Analogue
3VD
3V3 Supply
GNDD
Ground Digital
INT Clock
Clock Adjust
5STBY2
5V AIO
IReset
Inverse Reset
5M
5 V Motor
5SW
5SW
8SW
8SW
SDA
IIC1
SCL
IIC1
SCL1
IIC2
SDA1
IIC2
IPOR1
IPOR to DC
12STBY
12 V to DC
5STB
5 V to DC
8SW
8 SW to FRONT
VGNSTBY
VGN to DC
A_DATA
To DIGI
D_DATA
To DIGI
A_RDY
To DIGI
D_RDY
To DIGI
INT
TO DC
RC
TO DC
IRESET_DIG
TO DIGI
GNDA
SC1 GND A
ARIn_SC1
SC1 A R IN
ALIn_SC1
SC1 A L IN
YCVBSIN_SC1
SC1 Y IN
GNDV
SC1 GND V
AROut_SC2
SC2 A R Out
ALOutSC2
SC2 A L Out
GNDA
SC2 GND A
YCVBSOut_SC2
SC2 Y Out
GNDV
SC2 GND V
AROut_SC1
SC1 A R Out
ALOutSC1
SC1 A L Out
YCVBSOut_SC1
SC1 Y Out
Signal
Type
Condition
PS IN
PS IN
PS IN
PS IN
PS IN
DC Gen
GND
PS IN
GND
Count Out
DC Out
DC Out *
DC Out
DC Out
DC Out
IIC IO
IIC IO
IIC IO
IIC IO
DC OUT
DC Out
DC Out
DC Out
GND
DC IN
DC IN
DC IN
DC IN
DC IN
DC IN
DC IN
DC IN
NF IN
NF IN
V IN
GND
NF Out
NF Out
GND
V Out
GND
NF Out
NF Out
V Out
Part
AIO1
1932 1
1932 2
1932 3
1932 4
1932 5
1932 6
1932 7
1900 17
1900 01
7811 7
7803 12
7803 115
1987 12
7703 21
2321
1981 6
1981 8
3804
3805
1981 5
1981 2
1981 11
1953 6
1981 3
1982 2
1982 3
1982 4
1982 5
1981 9
1981 10
1982 1
1950 4A
1950 2A
1950 6A
1950 20A
1950 21A
1950 1B
1950 3B
1950 4B
1950 19B
1950 21B
1950 1A
1950 3A
1950 19A
Schematics
Name Coord.
AIO1 C10
PS
C1
PS
C1
PS
C1
PS
C1
PS
D1
PS
D1
PS
D1
DAC B1
DAC E1
AIO1 H5
AIO2 D3
AIO2 D2
AIO1 F14
TU B10
PS
B6
AIO1 E13
AIO1 E13
AIO1 A9
AIO1 A9
AIO1 E13
AIO1 D13
AIO1 F13
IO1
I1
AIO1 E13
AIO1 H13
AIO1 H13
AIO1 H13
AIO1 H13
AIO1 F13
AIO1 F13
AIO1 H13
IO1 E14
IO1 E13
IO1 E14
IO1 I13
IO1 H14
IO4
C9
IO4
C9
IO4
C9
IO4
C9
IO4
C9
IO1 E14
IO1 E14
IO1 G13
MP
F5002
F5006
F5020
F536
F521
F515
F524
F527
F530
F5007
F5008
F5011
F5015
F5016
F5401
F5402
F5403
F5405
F5407
F5409
F5412
F5414
F5416
F5418
F5420
F5422
F5301
F5303
F5304
F5307
F5309
F012
F013
F014
F0002
F0003
F0005
F0007
F0009
F0011
F0012
F0014
F0016
F010
F011
F331
F334
F336
X
Y
Signal
Name
ARIn_SC2
ALIn_SC2
YCVBSIN_SC2
BC_SC1
8_SC1
P50_SC1
Gout_SC1
RCOut_SC1
FBOut_SC1
BC_SC2
8_SC2
Gin_SC2
RCin_SC2
FBin_SC2
A_V
GNDV
A_U
A_Y
A_C
A_YCVBS
D_CVBS
D_Y
D_C
D_R
D_G
D_B
AFCRI
AFCLI
CVBSFIN
CFIN
YFIN
DAINOPT
DAINCOAX
DAOUT
A_BCLK
A_WCLK
A_DAT
A_PCMCLK
D_BCLK
D_WCLK
D_DATA0
D_PCMCLK
D_KILL
ARDAC
ALDAC
RCALOut
RCAROut
RCVBSOut
Signal
Description
SC2 A R IN
SC2 A L IN
SC2 Y IN
SC1 BC
SC1 Pin 8
SC1 P50
SC1 G Out
SC1 RC Out
SC1 FB Out
SC2 B IN C Out
SC2 Pin 8
SC2 G In
SC2 RC In
SC2 FB In
A_V to DIGI
GNDV to DIGI
A_U to DIGI
A_Y to DIGI
A_C to DIGI
AYCVBS to DIGI
D_CVBS f. DIGI
D_Y f. DIGI
D_C f. DIGI
D_T f. DIGI
D_G f. DIGI
D_B f. DIGI
A R from FC
A L from FC
CVBS from FC
C from FC
Y from FC
A D Opt to DIGI
A D Coax to DIGI
A D from DIGI
BCLK from DIGI
WCLK from DIGI
A Data to DIGI
PCMCLK from DIGI
BCLK from DIGI
WCLK from DIGI
A Data from DIGI
PCMCLK from DIGI
A Kill from DIGI
A R from DAC
A L from DAC
A L Rear Cinch Out
A R Rear Cinch Out
V Rear Cinch Out
Figure 5-34
CLK In
CLK In
Data Out
CLK In
CLK In
CLK In
Data In
CLK In
DC In
NF Out
NF Out
NF Out
NF Out
V Out
Signal
Type
NF IN
NF IN
Sin IN
Sin Out*
DC Out
DC Out
Sin Out
Sin Out
DC Out
Sin In*
DC Out
Sin In
Sin In
DC In
Sin Out
GND
Sin Out
V Out
Sin Out
V Out
V In
V In
Sin In
Sin In
Sin In
Sin In
NF In
NF In
V In
Sin In
V In
Part
1950 2B
1950 6B
1950 20B
1950 7A
1950 8A
1950 10A
1950 11A
1950 15A
1950 16A
1950 7B
1950 8B
1950 11B
1950 15B
1950 16B
1954 01
1954 02
1954 03
1954 05
1954 07
1954 09
1954 12
1954 14
1954 16
1954 18
1954 20
1954 22
1953 1
1953 3
1953 4
1953 7
1953 9
1900 20
1900 21
1900 20
1900 2
1900 3
1900 5
1900 7
1900 9
1900 11
1900 12
1900 14
1900 16
7002 1
7002 7
1958 4B
1958 5B
1959 1B
Schematics
Name Coord.
IO4
C9
IO4
C9
IO4
F9
IO1 E13
IO1 F13
IO1 F14
IO1 F13
IO1 G14
IO1 H13
IO4
D9
IO4
D9
IO4
D9
IO4
E9
IO4
E9
IO1
I3
IO1
I4
IO1
I4
IO1
I4
IO1
I4
IO1
I4
IO1
I5
IO1
I5
IO1
I5
IO1
I6
IO1
I6
IO1
I6
IO1
I1
IO1
I1
IO1
I1
IO1
I2
IO1
I2
DAC A1
DAC A1
DAC A1
DAC E2
DAC D2
DAC D2
DAC D2
DAC D2
DAC D2
DAC C2
DAC C2
DAC C2
DAC C9
DAC E9
IO3
E9
IO3
E9
IO3
C9
5.6.4
Measurement Point Overview for EURO
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
5.
EN 79
Analogue board
Measurement Points Overview
CL 16532095_097.eps
150801
X
Y
Signal
Name
ARCRI
ARCLI
RCVBSIn
RSVHSYIn
RSVHSCIn
RSVHSYOut
RSVHSCOut
DVAR
GNDA
DVAL
IF
IF In
GNDFV
GNDFV
40.4
AGC
SYNC
DIG OUT L
DIG OUT H
OPT OUT
FAN OUT
FAN IN
ION
BE_FAN
FB
GNDD
Signal
Description
A L Rear Cinch In
A R Rear Cinch In
V Rear Cinch In
Y Rear SVHS In
C Rear SVHS In
Y Rear SVHS Out
C Rear SVHS Out
A R from DIGI
GNDA
A L from DIGI
IF Out
IF In
GND FV
GND FV
40.4 Trap
AGC
SYNC from Sepa.
Digital Out Low
Digital Out High
Optical Out
FAN Out
FAN In
ION_FAN
BE_FAN
FBIN SC2
GNDD
Signal
Type
NF In
NF In
V In
V In
Sin In
V Out
Sin Out
Sin In
GND
Sin In
DC Out
Sin In
GND
GND
Sin Out
DC Out
Freq Out
GND
Sin Out
DC Out
DC Out
DC In
DC Out
DC Out
DC Out
GNDD
Part
1958 1A
1958 2A
1959 2A
1955 3B
1955 4B
1955 3A
1955 4A
1960 1
1960 2
1960 4
1705 11
1705 11
1705 12
1700 3
1700 1
3701
7803 33
1954 2
1945 3
1943 1
1984 1
1985 1
1982 6
1982 8
1982 9
1982 10
Schematics
Name Coord.
IO2
D2
IO2
E2
IO2
C2
IO2
B2
IO2
B2
IO3
A9
IO3
A9
AP
D1
AP
D1
AP
D1
TU
C3
TU
C3
TU
C2
TU
B6
TU
B5
TU
A4
AIO1 F6
DIGI B4
DIGI A4
DIGI D3
FACO C5
FACO F1
AIO1 H13
AIO1 I13
AIO1 I13
AIO1 I13
MP
F800
F3201
F3202
F3203
F3204
F3205
F3206
F3207
F0017
F0001
F803
F900
F902
F8111
F303
F9336
F8105
F8107
F810
F811
F8104
F8101
F8110
F5306
F8102
F8202
F8203
F8204
F8205
F8108
F8109
F8201
F5103
F5101
F5906
F5806
F510
F509
F5201
F5105
F5104
F5202
F5905
F5801
F5805
F5802
X
Y
Signal
Name
F_MODE
12V
5V
5NSTBY
VGNSTBY
33STBY
FLYB
GNDA
3VD
GNDD
INT Clock
5STBY2
IReset
5M
5SW
8SW
SDA
SCL
SCL1
SDA1
IPOR1
12STBY
5STB
8SW
VGNSTBY
A_DATA
D_DATA
A_RDY
D_RDY
INT
RC
IRESET_DIG
ARIn_2
ALIn_2
GNDV
GNDV
ARout_1
ALout_1
RCVBSOut2
ARIn_1
ALIn_1
RCVBSIn
Y_OUT
U_IN
Y_IN
V_IN
Signal
Description
Fact. Mode
12 V Supply
5 V Supply
5 V Supply
Supply GND
33 V Supply
Controls PS
Ground Analogue
3V3 Supply
Ground Digital
Clock Adjust
5V AIO
Inverse Reset
5 V Motor
5SW
8SW
IIC1
IIC1
IIC2
IIC2
IPOR to DC
12 V to DC
5 V to DC
8 SW to FRONT
VGN to DC
To DIGI
To DIGI
To DIGI
To DIGI
TO DC
TO DC
TO DIGI
A R IN 2
A L IN 2
GND V
GND V
A R Out 1
A L Out 1
SC1 Y Out
A R IN 1
A L IN 1
Y IN
Y Out
U IN
Y IN
V IN
Signal
Type
Condition
PS IN
PS IN
PS IN
PS IN
PS IN
DC Gen
GND
PS IN
GND
Count Out
DC Out
DC Out *
DC Out
DC Out
DC Out
IIC IO
IIC IO
IIC IO
IIC IO
DC OUT
DC Out
DC Out
DC Out
GND
DC_In
DC_In
DC_In
DC_In
DC_In
DC_In
DC_In
NF IN
NF IN
GND
GND
NF Out
NF Out
V Out
NF IN
NF IN
Sin IN
Sin Out*
Sin In*
Sin In
Sin In
Part
AIO1
1932 1
1932 2
1932 3
1932 4
1932 5
1932 6
1932 7
1900 17
1900 01
7811 7
7803 12
7803 115
1987 12
7703 21
2321
1981 6
1981 8
3804
3805
1981 5
1981 2
1981 11
1953 6
1981 3
1982 2
1982 3
1982 4
1982 5
1981 9
1981 10
1982 1
1958 3A
1958 1A
1957 6A
1956 6A
1959 5B
1959 4B
1997 1B
1959 1A
1959 4A
1997 2A
1957 5A
1956 1B
1956 5A
1956 2B
Schematics
Name Coord.
AIO1 C10
PS
C1
PS
C1
PS
C1
PS
C1
PS
D1
PS
D1
PS
D1
DAC B1
DAC E1
AIO1 H5
AIO2 D3
AIO2 D2
AIO1 F14
TU B10
PS
B6
AIO1 E13
AIO1 E13
AIO1 A9
AIO1 A9
AIO1 E13
AIO1 D13
AIO1 F13
IO1
I1
AIO1 E13
AIO1 H13
AIO1 H13
AIO1 H13
AIO1 H13
AIO1 F13
AIO1 F13
AIO1 H13
IO3 E13
IO3 E14
IO1 H12
IO1
I8
IO1 E13
IO1 D13
IO3
A8
IO2
E2
IO2
E2
IO2
C2
IO1 I12
IO1 I10
IO1
I9
IO1 I10
5.
DVDR980-985 /0X1
Figure 5-35
Remark:
Indicator * means more than one signal type
MP
F5101
F5103
F5202
F5503
F5504
F338
F337
F6001
F6002
F6004
F700
F701
F702
F703
F704
F705
F812
F4202
F4203
F4204
F806
F807
F8206
F8208
F8209
F8210
Measurement Point Overview for NAFTA
EN 80
Diagnostic Software and Faultfinding Trees
CL 16532095_098.eps
150801
MP
F5401
F5402
F5403
F5405
F5407
F5409
F5412
F5414
F5416
F5418
F5420
F5422
F5301
F5303
F5304
F5307
F5309
F012
F013
F014
F0002
F0003
F0005
F0007
F0009
F0011
F0012
F0014
F0016
F010
F011
F513
F512
F5205
F5503
F5504
F338
F337
F6001
F6002
F6004
F700
F701
F702
F703
F705
F812
F330
X
Y
Signal
Name
A_V
GNDV
A_U
A_Y
A_C
A_YCVBS
D_CVBS
D_Y
D_C
D_R
D_G
D_B
AFCRI
AFCLI
CVBSFIN
CFIN
YFIN
DAINOPT
DAINCOAX
DAOUT
A_BCLK
A_WCLK
A_DAT
A_PCMCLK
D_BCLK
D_WCLK
D_DATA0
D_PCMCLK
D_KILL
ARDAC
ALDAC
ALOut_2
AROut_2
RCVBSOut1
RSVHSYIn
RSVHSCIn
RSVHSYOut
RSVHSCOut
DVAR
GNDA
DVAL
IF
IF In
GNDFV
GNDFV
AGC
SYNC
RC IN
Signal
Description
A_V to DIGI
GNDV to DIGI
A_U to DIGI
A_Y to DIGI
A_C to DIGI
AYCVBS to DIGI
D_CVBS f. DIGI
D_Y f. DIGI
D_C f. DIGI
D_T f. DIGI
D_G f. DIGI
D_B f. DIGI
A R from FC
A L from FC
CVBS from FC
C from FC
Y from FC
A D Opt to DIGI
A D Coax to DIGI
A D from DIGI
BCLK from DIGI
WCLK from DIGI
A Data to DIGI
PCMCLK from DIGI
BCLK from DIGI
WCLK from DIGI
A Data from DIGI
PCMCLK from DIGI
A Kill from DIGI
A R from DAC
A L from DAC
A L Rear Out 2
A R Rear Out 2
V Rear Cinch Out1
Y Rear SVHS In
C Rear SVHS In
Y Rear SVHS Out
C Rear SVHS Out
A R from DIGI
GNDA
A L from DIGI
IF Out
IF In
GND FV
GND FV
AGC
SYNC from Sepa.
Remote Control In
Part
1954 01
1954 02
1954 03
1954 05
1954 07
1954 09
1954 12
1954 14
1954 16
1954 18
1954 20
1954 22
1953 1
1953 3
1953 4
1953 7
1953 9
1900 20
1900 21
1900 20
CLK In 1900 2
CLK In 1900 3
Data Out 1900 5
CLK In 1900 7
CLK In 1900 9
CLK In 1900 11
Data In 1900 12
CLK In 1900 14
DC In 1900 16
NF Out 7002 1
NF Out 7002 7
NF Out 1958 4B
NF Out 1958 5B
V Out 1997 5C
V In
1955 3B
Sin In 1955 4B
V Out 1955 3A
Sin Out 1955 4A
Sin In
1960 1
GND
1960 2
Sin In
1960 4
DC Out 1705 11
Sin In 1705 11
GND
1705 12
GND
1700 3
DC Out
3701
Freq Out 7803 33
DC Out 1993 2
Signal
Type
Sin Out
GND
Sin Out
V Out
Sin Out
V Out
V In
V In
Sin In
Sin In
Sin In
Sin In
NF In
NF In
V In
Sin In
V In
Schematics
Name Coord.
IO1
I3
IO1
I4
IO1
I4
IO1
I4
IO1
I4
IO1
I4
IO1
I5
IO1
I5
IO1
I5
IO1
I6
IO1
I6
IO1
I6
IO1
I1
IO1
I1
IO1
I1
IO1
I2
IO1
I2
DAC A1
DAC A1
DAC A1
DAC E2
DAC D2
DAC D2
DAC D2
DAC D2
DAC D2
DAC C2
DAC C2
DAC C2
DAC C9
DAC E9
IO1 B13
IO1 C13
IO3
A8
IO2
B2
IO2
B2
IO3
A9
IO3
A9
AP
D1
AP
D1
AP
D1
TU
C3
TU
C3
TU
C2
TU
B6
TU
A4
AIO1 F6
IO3
E2
X
Y
Signal
Name
DIG OUT L
DIG OUT H
OPT OUT
FAN OUT
FAN IN
ION
BE_FAN
FB
GNDD
Remark:
Indicator * means more than one signal type
MP
F4202
F4203
F4204
F806
F807
F8206
F8208
F8209
F8210
Signal
Description
Digital Out Low
Digital Out High
Optical Out
FAN Out
FAN In
ION_FAN
BE_FAN
FBIN SC2
GNDD
Signal
Type
GND
Sin Out
DC Out
DC Out
DC In
DC Out
DC Out
DC Out
GNDD
Part
1954 2
1945 3
1943 1
1984 1
1985
1982 6
1982 8
1982 9
1982 10
Schematics
Name Coord.
DIGI B4
DIGI A4
DIGI D3
FACO C5
FACO F1
AIO1 H13
AIO1 I13
AIO1 I13
AIO1 I13
Diagnostic Software and Faultfinding Trees
Figure 5-36
DVDR980-985 /0X1
5.
CL 16532095_099.eps
150801
EN 81
EN 82
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Power Part Check
Check internal Power supply voltages
5M on testpoint F9340
NOK
check Fuse 1327
12STBY on testpoint F810
NOK
check Fuse 1326
NOK
check IC 7332
NOK
check
NOK
check Fuse 1325
NOK
check
8STBY on pin 3 of IC7332
8SW on testpoint F9336
5STBY on testpoint F9333
5SW on testpoint F303
5STBY2 on testpoint F900
5STBY_uP on IC7803
NOK
NOK
- ISTBY HIGH?
- T7329, T7324, MOSFET7321
- ISTBY HIGH?
- T7329, T7324, MOSFET7323
check L5901, IC7900
check L5903, IC7803
OK
Power Part OK
Figure 5-37
CL 16532145_056.eps
031201
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
DSW Check Analoge Board
DSW CHECK ANALOGUE BOARD
Start Diagnostic Software
and select Command mode
Echo Test Analogue Board
Command: 700
NOK
- Check Reset signal(+5V) on F902
- Check Clock(20MHz) on I915
- Check connection to Digital Board
- Check IC 7803
OK
Boot Code Version Test
Command: 703
Analogue Flash Checksum Test
Command: 724
NOK
- Check IC 7906
OK
Hardware Version Check
Command: 704
NOK
- Check IC 7906
OK
Clock Adjust Test
Command: 705 2001 07 16 09 15 45
NOK
(YYYY MM DD HH MM SS)
- Check IC 7811
- Check x-tal 1602
OK
Tuner Test
Command: 706
NOK
- Check tuner 1705
OK
Frequency Download Test
Command: 707
NVRAM Test
Commdo: 711
NOK
- Check IC 7815
OK
Data Slicer Test
Command: 708
NOK
- Check IC 7990
OK
Sound Processor Test
Command: 709
NOK
- Check IC 7600
OK
Audio Video Selector Test
Command: 710
NOK
- Check IC 7507
OK
DCW CHECK ANALOGUE
BOARD OK
CL 16532095_101.eps
150801
Figure 5-38
5.
EN 83
EN 84
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Routing Audio and Video
Route Video
Nucleus Number: 712
Description
This nucleus routes the video signals on the analogue board to
the destination determined by the input parameters
The paths that are available for video routing and their
description(Europe version)
PATH ID DESCRIPTION
00
Input signal is VIDEO(CVBS) from digital board
and will be re-routed back to the digital board.
01
Input signal is from FRONT VIDEO(CVBS) IN and
will be routed to the digital board.
02
Input signal is from REAR VIDEO(CVBS) IN and
will be routed to the digital board.
03
Input signal is from FRONT S-VIDEO(Y/C) and will
be routed to the digital board.
04
Input signal is from REAR S-VIDEO(Y/C) and will
be routed to the digital board.
05
Input signal is CVBS from SCART1 and will be
routed to the digital board.
06
Input signal is CVBS from SCART2 and will be
routed to the digital board.
07
No routing.
08
Input signal is VIDEO(CVBS) from ANTENNA IN
and will be routed to SCART1.
09
Input signal is VIDEO(CVBS) from SCART1 and
will be routed to SCART2.
10
Input signal is VIDEO(CVBS) from SCART2 and
will be routed to SCART1.
11
No routing.
12
Input signal is from REAR VIDEO(CVBS) IN and
will be routed to SCART1 and SCART2.
13
Input signal is from FRONT VIDEO(CVBS) IN and
will be routed to SCART1.
14
Input signals VIDEO(CVBS and Y/C) from SCART
1 will be routed to SCART2.
15
Input signal is from REAR S-VIDEO(Y/C) IN and
will be routed to SCART2.
16
Input signal is from FRONT S-VIDEO(Y/C) IN and
will be routed to SCART2.
17
No routing
18
No routing
19
Input signals VIDEO(RGB and FAST BLANKING)
from SCART2 will be routed to the corresponding
pins of SCART1.
20
Signal path is routed from digital board RGB to
RGB SCART1 and from RGB SCART2 to digital
board YUV and from digital board CVBS to digital
board CVBS.
21
Signal path is routed from digital board YC to
REAR S-VIDEO(YC) OUT and from REAR S-VIDEO(YC) IN to digital board YC.
The paths that are available for video routing and their
description (Nafta region)
PATH ID DESCRIPTION
04
Input signal is from REAR S-VIDEO(Y/C) IN and
will be routed to the digital board.
05
Input signal is from YUV IN and will be routed to the
digital board.
06
No routing.
07
No routing.
08
Input signal is VIDEO(CVBS) from ANTENNA IN
and will be routed to VIDEO(CVBS) OUT and .
09
Input signal is from YUV IN and will be routed to
YUV OUT.
10
No routing.
11
No routing.
12
Input signal is from REAR VIDEO(CVBS) IN and
will be routed to REAR VIDEO(CVBS) OUT.
13
Input signal is from FRONT VIDEO(CVBS) IN and
will be routed to REAR VIDEO(CVBS) OUT.
14
Input signal is from REAR S-VIDEO(Y/C) IN and
will be routed to REAR S-VIDEO(Y/C) OUT.
15
Input signal is from FRONT S-VIDEO(Y/C) IN and
will be routed to REAR S-VIDEO(Y/C) OUT.
16
No routing.
17
Signal path is routed from digital board RGB to
REAR VIDEO(YUV) OUT and from REAR VIDEO(YUV) IN to digital board YUV and from digital
board CVBS to digital board CVBS.
18
Signal path is routed from digital board CVBS to
REAR VIDEO(CVBS) OUT and from REAR VIDEO(CVBS) IN to digital board CVBS.
19
Signal path is routed from digital board YC to
REAR S-VIDEO(YC) OUT and from REAR S-VIDEO(YC) IN to digital board YC.
Example
DD:> 712 01
71200: Video routing on the Analogue Board OK.
Test OK @
Route Audio
Nucleus Number: 713
Description
This nucleus routes the audio on the analogue board to the
destination determined by the input parameters
The paths that are available for audio routing and their
description (Europe version)
PATH ID DESCRIPTION
00
Input signal is VIDEO(CVBS) from digital board
and will be re-routed back to the digital board.
01
Input signal is from FRONT AUDIO IN and will be
routed to the digital board.
02
Input signal is from REAR AUDIO IN and will be
routed to the digital board.
03
Input signal is AUDIO from SCART1 and will be
routed to the digital board.
04
Input signal is AUDIO from SCART2 and will be
routed to the digital board.
05
No routing.
06
No routing.
PATH ID DESCRIPTION
07
No routing.
00
Input signal is VIDEO(CVBS) from digital board
and will be re-routed back to the digital board.
08
Input signal is VIDEO(CVBS) and AUDIO from ANTENNA IN and will be routed to SCART1.
01
Input signal is from FRONT VIDEO(CVBS) IN and
will be routed to the digital board.
09
Input signal is VIDEO(CVBS) and AUDIO from
SCART1 and will be routed to SCART2.
02
Input signal is from REAR VIDEO(CVBS) IN and
will be routed to the digital board.
10
Input signal is VIDEO(CVBS) and AUDIO from
SCART2 and will be routed to SCART1.
03
Input signal is from FRONT S-VIDEO(Y/C) IN and
the signal received will be routed to the digital
board.
11
Input signal is AUDIO from dvio board and will be
routed to SCART1.
Diagnostic Software and Faultfinding Trees
PATH ID DESCRIPTION
12
No routing.
13
No routing.
14
No routing.
15
No routing.
16
No routing.
17
Input signal is from REAR AUDIO IN and will be
routed to SCART1.
18
Input signal is from FRONT AUDIO IN and will be
routed to SCART1.
The paths that are available for audio routing and their
description (Nafta region)
PATH ID DESCRIPTION
00
Input signal is VIDEO(CVBS) from digital board
and will be re-routed back to the digital board.
01
Input signal is from FRONT AUDIO IN and will be
routed to the digital board.
02
Input signal is from REAR AUDIO IN 2 and will be
routed to the digital board.
03
Input signal is from FRONT AUDIO IN and will be
routed to the digital board.
04
No routing.
05
No routing.
06
No routing.
07
No routing.
08
Input signal is VIDEO(CVBS) and AUDIO from ANTENNA IN and will be routed to VIDEO(CVBS)
OUT and REAR CINCH OUT 2.
09
No routing.
10
Input signal is from REAR AUDIO CINCH IN 2 and
will be routed to REAR AUDIO CINCH OUT 2.
11
Input signal is from FRONT AUDIO CINCH IN and
will be routed to REAR AUDIO CINCH OUT 2.
12
No routing.
13
No routing.
14
No routing.
15
No routing.
16
Input signal is AUDIO from dvio board and will be
routed to AUDIO CINCH OUT 2.
17
No routing.
18
No routing.
19
No routing.
20
Input signal is from digital board and will be routed
to the REAR AUDIO OUT 1 and input signal is from
REAR AUDIO IN 2 and will be routed to the digital
board.
21
Input signal is from digital board and will be routed
to the REAR AUDIO OUT 1 and input signal is from
REAR AUDIO IN 1 and will be routed to the digital
board.
22
Input signal is from digital board and will be routed
to the REAR AUDIO OUT 2 and input signal is from
REAR AUDIO IN 1 and will be routed to the digital
board.
EXAMPLE
DD:> 713 00
71300: Audio routing on the Analogue Board OK.
Test OK @
DVDR980-985 /0X1
5.
EN 85
EN 86
5.6.5
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Display Board
TROUBLESHOOTING DISPLAY BOARD
• Check supply voltage
NO DISC
POWER ON
⇒
⇒
⇒
⇒
Connector1916-2
Connector1916-3
Connector1916-11
Connector1916-12
12STBY
VGNSTB
5STBY
5M
+12V
-32V
+5V
+5.2V
• Check filament voltage
NO
DISPLAY?
12STBYSI
⇒ Testpoint F105
⇒ AC voltage is created via oscillator circuit (7152-7153).
⇒ Check heater voltage on testpoints F102 and F101
+12V
3.2VAC, -24,4VDC, 42 kHz.
• Check oscillator frequency of 12MHz at pin 91 of IC7156
• Check I2C bus SDA / SCL nucleus 500 of diagnostic software
• Check version of software nucleus 501 of diagnostic software
• Diagnostic software : Player script of Front panel
YES
Key Function
NO
• Diagnostic software “Player script” : Keyboard test.
• Check appropriate key and resistor
YES
• Check if voltage at connector 1915-2 is 5V when power on (green light)
Standby LED ?
NO
• Check if voltage at base of Tr 7141 is 2V when power on (green light).
• Check if voltage at base of Tr7141 is 0V when switching to standby (red light)
• Diagnostic software “Player script” : LED test.
YES
• Check presence of low pulses at pin 5 of connector 1917 while pressing a key on remote control.
Remote control?
NO
• Check IR receiver 7140.
• Diagnostic software “Player script” : Remote control test.
YES
CL 265362011_024.eps
160102
DISPLAY PCB OK.
Figure 5-39
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
5.
EN 87
DVIO Board
Power part check
POWER PART CHECK DVIO
USE DVIO BOARD CIRCUIT DIAGRAMS 1 2, 3, 4 AND 5 AND DVIO TOP VIEW TESTPOINTS
Power On and exit
stand-by mode
OK
+5V on testpoint F536
NOK
Check connector 1500
to Digital board
NOK
Check L 5200
Check IC 7203
NOK
Check IC 7204
Check IC 7208
+3V3 on testpoint F531
OK
+5V_PROC on testpoint F212
OK
PSEN(+5V) on testpoint F203
OK
+3V3_FPGA on testpoint F311
+3V3_FPGA_CONF on testpoint F312
+3V3_SRAM on testpoint F313
+3V3_PLL on testpoint F325
NOK
Check L 5302
Check L 5303
Check L 5304
OK
+3V3_IEEE_PLL on testpoint F138
+3V3_IEEE_A on testpoint F139
+3V3_IEEE_D on testpoint F140
+3V3_LINK on testpoint F141
NOK
Check L 5106
Check L 5109
Check L 5110
Check L 5103
OK
+Vcc_DV_RAM(+3V3) on testpoint F417
+35V_DV_EDO(+3V3) on testpoint F425
+3V3_DV on testpoint F416
NOK
Check L 5404
Check L 5403
Check L 5402
OK
Power Part OK
Figure 5-40
CL 16532145_057.eps
031201
EN 88
5.
DVDR980-985 /0X1
Diagnostic Software and Faultfinding Trees
Reset and Clock check
RESET & CLOCK CHECK DVIO
USE DVIO BOARD CIRCUIT DIAGRAMS 2, 3, 4 AND 5 AND DVIO TOP VIEW TESTPOINTS
Power On and exit
stand-by mode
Enable DVIO board:
- press channel up or down
untill the display shows CAM3
- press tuner key in order to
switch to the DV-source
The red LED above the
DV-input will light up.
NOK
OK
Check Reset signal (LOW)
on testpoint F214
NOK
- Check connection
to Front DVIO
- Check IC 7203
- Check T 7207
- Check R 3203
- Check IC 7203
- Check T 7202
OK
Check uP clock
on testpoint F201
(11,05MHz)
NOK
- Check x-tal1200
- Check IC 7203
- Check R 3201
OK
Check CLOCKAUDTMP
on testpoint F303
(8,192MHz)
NOK
- Check IC 7303
- Check IC 7307
- Check R 3315
OK
Check Clock 27MHz
on testpoint F305
NOK
- Check IC 7308
- Check IC 7303
- Check R 3317
OK
Check Clock 27M_DV
on testpoint F307
(27MHz)
NOK
- Check IC 7308
- Check IC 7404
- Check R 3318
OK
Check Clock 27M_CON
on testpoint F308
(27MHz)
NOK
- Check IC 7308
- Check IC 7500
- Check R 3319
OK
Reset- and clock signals
are OK
Figure 5-41
CL 16532145_057.eps
031201
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
5.
DSW DVIO tests
DSW DVIO TESTS
Start Diagnostic Software
and select Command mode
DVIO Board Presence Test
Command: 800
NOK
- Check DVIO Board
- Check Connector 1500
NOK
- Check IC7303
- Check IC 7203
OK
Reset DVIO Test
Command: 801
OK
DVIO Access Test
Command: 802
NOK
- Check DVIO Board
- Check Connector 1500
- Check Digital Board
OK
DVIO Module ID's Test
Command: 804
NOK
- Check IC 7303
- Check IC 7404
OK
DVIO Selftest
Command: 805
NOK
Check ERROR LIST
in COMPAIR
OK
DVIO DSW CHECK OK
CL 16532145_059.eps
031201
Figure 5-42
EN 89
EN 90
5.
Diagnostic Software and Faultfinding Trees
DVDR980-985 /0X1
Waveforms
Waveforms DVIO
uP_clock
2V / div DC
Clockaudtmp
100ns / div
2V / div DC
Clock 27MHz
2V / div DC
50ns / div
Clock 27M_DV
20ns / div
2V / div DC
20ns / div
Clock 27M_CON
2V / div DC
20ns / div
CL 16532145_060.eps
031201
Figure 5-43
Diagnostic Software and Faultfinding Trees
Personal Notes:
DVDR980-985 /0X1
5.
EN 91
EN 92
5.
DVDR980-985 /0X1
Personal Notes:
Diagnostic Software and Faultfinding Trees
Block and Wiring Diagram.
DVDR980-985 /0X1
6.
EN 93
6. Block and Wiring Diagram.
Block Diagram DVDR980-985 EU
ANALOG BOARD
FAN
12VDC
INTELLIGENT
CONTROL
AUDIO L
AUDIO R
FRONT
Analog input
1911
A1
1
AFCRI
1953
2
AFCLI
CVBSFIN
3
A1
4
V1
A1
9
ANALOG AUDIO VIDEO
A1
3
V1
4
6
8SW
CFIN
8
S-VIDEO
DVIO
V3
V2
INPUT/OUTPUT
8SW
7
+3V3
DRAM
V3
9
+12V
CONTROL
uP
CFIN
8
+5V
AUDIO DIGITAL
CVBSFIN
6
1500
9
YFIN
AFCLI
5
V2
7
AFCRI
2
5
CVBS
P50
1
YFIN
DV_HS_OUT
8051
DV_VS
DV CODEC
DV_CLK
VSM_UART2 4
FRONT
Digital Video input
YUV(7:0)
CVBS_Y_IN
Y_IN
60
CVBS_OUT_B
V9
CVBS-RGB-Y/C
DATA
&CONTROL
1
A2
4
AUDIO L/R
ANA_R
ANA_L
1954
C_IN
ONLY FOR DVDR985
A2
AUDIO L/R
YUV-YCVBS/C
V8
SRAM
U_IN
IEEE 1394
V7
AUDIO DAC
V6
FPGA
ANALOG AUDIO L/R
V_IN
LINK
4
V5
PHY
PROCESSING &
SOURCE
SELECTION
1960
1501
1101
4
V4
1001
(DATA+CONTROL+PSU)
4
AUDIO OPTICAL
Y_OUT_B
V10
C_OUT_B
V11
R_OUT_B
V12
G_OUT_B
V13
B_OUT_B
V14
SCART II
AUXI/O
12
14
16
18
20
22
22 20 18 16 14
DIGITAL PCB
DVD & RW ENGINE
1402
FRONT-END I2S
7
TRAY CONTROL
VSM
BE_FAN
SERVO
BE_LOADN
FRONT-END I2S or //
LASER
S2B
6
A3
S2B
WRITE
1900
AUDIO ENCODER I2S
AE_BCLK
ADC
AD_DATAI
18
MPEG
AV
DECODER
+ HOST
(Sti5508)
1
ION
1602
AE_WCLK
ANAL.VIDEO
SCARTI
TO TV
- I/O
4
IRESET_DIG
5
20
21
READ
5
1982
VSM_UART1
VIDEO INPUT
PROCESSING
Stream
Manager
RESETN_BE
1600
10
MPEG VIDEO
ENCODING
EMPRESS
AUDIO MPEG1
I2S
1601
DIG.VIDEO
1902
VIDEO MPEG2
DISC
1501
SDRAM
S-VIDEO
COAX_IN
3
OPT_IN
4
2
S-VIDEO
SPDIF
MUTEN
7
AD_ACLK
9
CVBS
A4
DIG. AUDIO
11
AD_DATAO
12
AD_WCLK
14
AD_BCLK
AUDIO PCM I2S
DAC
CVBS
EMI BUS
DRAM
3
4
5
6
7
8
1
2
3
4
5
6
7
9
8
CLOCK
&
BACKUP
1903
1
8
6
4
2
1
8
6
4
2
1
2
2MB
SDRAM
RS232
1900
1000
1
FLASH 4MB
-5V
GND
ION
+5V
GND
GND
+12V
GND
+3V3
+3V3
+3V3
+3V3
+12V
GND
-5V
GND
+4V6E
GND
+5V
+3V3
SDRAM
ANTENNE INPUT
TUNER
TV OUT
10 11 12
-5Nstby
-Vgnstby
FLYB
GND
2
INFRA RED
EYE
+33Vstby
PSU
INT/IPOR1
+5V2stby
SERVICE
PSU
PSU
+12Vstby
1981
1
2
3
4
5
6
7
1
2
3
4
5
6
7
I2C
SCL
SDA
IPOR1
INT
5M
5STBY
+12Vstby
1915
-Vgnstby
1932
7
2
3 11 12
9
5
6
8
1917
TITLE
TRACK
TOTAL
CHAPTER
TRACK TIME
REMAIN
CHANNEL
5STBY
1916
DIGITAL PCB
VPS/PDC
AM
1
2
3
4
5
6
7
8
9
10 11 12
PM
FRONT PROCESSOR
DISPLAY & CONTROL
OPEN/CLOSE
PLAY
STOP
RECORD
REC-LEVEL
RELEASE
CHANNEL
MANUAL
TRACK
SEARCH
GND
8
+12V
GND
7
FLYB
6
-5V
+33Vstby
GND
-Vgnstby
+4V6E
5
-5Nstby
GND
4
+12Vstby
+5V
3
+5V2stby
2
-5V
1
ION
OVER
SAP
+5V
-10
0
STEREO
GND
-20
NICAM
+3V3
GND
-30
DIGITAL
0205
0207
GND
-40
MANUAL
0209
DECODER
GND
OVER
RECORD
+12V
0
PCM
TIMER
+3V3
-10
DTS
SAT
+3V3
-20
AC-3
MONITOR
+3V3
-30
MPEG
EP+
+3V3
-40
PROLOGIC
HQ SP L:P
ENGINE
SAVCD
I
RW
II
DVD
MAINS
AC
MULTI-MODE SOPS
CL 26532011_026.eps
170102
Block and Wiring Diagram.
DVDR980-985 /0X1
6.
EN 94
Wiring Diagram
8001
WIRING DIAGRAM
1962
1
GND
Y
GND
Cb
GND
Cr
GND
ANALOG
1984
1
21
8006
ANA_R
GNDA
GNDA
ANA_L
1900
22
1
1982
10
1
1954
22
8002
8006
pH-pH LF SHIELDED
1
1960
1953
1981
8004
1
2
3
4
7
ONLY FOR NAFTA
8015
1962
7
6
5
4
3
2
1
8001
8015
1800
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
FAN
EH
12 1
9
1
1932
4
1
7
pH
8007
EH
8
pH-pH LF SHIELDED
1
1
0209
1
0207
0205
7
12
1
1
7
1917
1915
1
1911
WIRE WRAP
7
8014
9
8011
1200 1100
FRONT
DV INPUT
TPB1TPB1+
TPA1TPA1+
1
2
3
4
5
6
7
8
9
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
IR & STBY
12
1918
1
2
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
B_OUT_B
GNDD
G_OUT_B
GNDD
R_OUT_B
GNDD
C_OUT_B
GNDD
Y_OUT_B
GNDD
CVBS_OUT_B
GNDD
GNDD
CVBS_Y_IN
GNDD
C_IN
GNDD
Y_IN
GNDD
U_IN
GNDD
V_IN
1600 1982
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GNDD
GNDD
NC
GNDD
BE_DATA_WR
GNDD
BE_SYNC
GNDD
BE_FLAG
GNDD
BE_BCLK
GNDD
BE_DATA_RD
GNDD
BE_WCLK
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GNDD
BE_RXD
GNDD
BE_TXD
BE_CPR
BE_IRQn
BE_SUR
BE_V4
GNDD
BE_LOAD
GNDD
BE_FAN
RESETn_BE
GNDD
GNDD
1
2
3
4
5
6
10
9
8
7
6
5
7
4
8
3
9
2
10
1
GNDD
FB
BE_FAN
ANA_WE
ION
VSM_UART1_RTSn
(D_RDY)
VSM_UART1_CTSn
(A_RDY)
VSM_UART1_TX
(D_DATA)
VSM_UART1_RX
(A_DATA)
IRESET_DIG
1101
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8008
+12Vstby
+5V2stby
-5Nstby
-Vgnstby
+33Vstby
FLYB
GND
1
2
3
4
5
6
7
8
8009
+3V3
+5V
GND
+4V6E
GND
-5V
GND
+12V
1
2
3
4
5
6
7
8
9
10
11
12
+3V3
+3V3
+3V3
+3V3
GNDD
+12V
GNDD
GNDD
+5V
ION(STBY_ctrl
GNDD
-5V
8011
8005
8013
1
2
3
4
FRONT
AV INPUT
pH
1 1916
DISPLAY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
8004
8007
8005
4
12
1
1001 1002
1000
1
4
GND
YUV_IN(7)
GND
YUV_IN(6)
+3V3
YUV_IN(5)
+3V3
YUV_IN(4)
+5V
YUV_IN(3)
GND
YUV_IN(2)
GND
YUV_IN(1)
GND
YUV_IN(0)
GND
CLK_27MHZ
GND
HS_IN
FRAME_IN
SCL
SDA
GND
1
SERVO
8013
IEEE WIRE
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
8
8003
1402
DVIO
EH
1
DIGITAL
8008
1
2
FAN
pH
30
1501
60
BOARD
TO
BOARD
1000
1900 12 1 1603 7
2
1
1201
60
1
1601
15 1101 1
1
15 1100
1501
22
1
1
1
4
1
1600
SERVICE
INTERFACE
1500
ONLY USED FOR DVDR985
4
1
1101
1 10
1800
1601 1954
GNDD
SPDIF
COAX_IN
OPT_IN
+5V
+3V3
MUTEN
GNDD
AD_ACLK
GNDD
AD_DATAO
AD_WCLK
GNDD
AD_BCLK
GNDD
AD_ACLK
GNDD
AD_DATAI
GNDD
AE_WCLK
AE_BCLK
GNDD
1100 1402
EH
EH
1 7
1602
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
8003
PSU
8009
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
8002
1602 1900
AFCRI
GNDA
AFCLI
VBSFIN
GNDV
8SW
CFIN
GNDV
YFIN
1
2
3
4
5
6
7
8
9
10
11
12
TEMP_SENSE
12VSTBY
VGNSTBY
-GNDD
IPOR1
SDA
GNDD
SCL
INT
RC
5STBY
5M
CL 26532011_027.eps
170102
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 95
7. Electrical Diagrams and Print-Layouts
Power Supply
1
2
3
4
5
6
7
8
9
10
11
12
POWER SUPPLY
1R5
33K
2201
3201
6201
47u
2211
100u
680u
2210
2130
5125
2214
2m2
3127
220K
3128
+5Vstby
1u
BYW29EX
0240
Heatsink
6221
6144
3221
7220
L7905
BAV21
6220
11
IN
3
GND
E
-5Nstby
OUT
1
2220
220u
2152
BYV27-200
22K
-5V
2
BAV21 BZX284-B15
330p
D
100n
7
FLYB
4K7
3222
4K7
16
6143
3223
BC857B
7241
2K2
8
+5V
5240
3220
68R
Vreg
6240
17
2241
BAV21
0260
MECHPART
13
2221
2223
3151
2145
100K
470n
2143
100n
E
+3V9
STPS745FP
100u
3150
2K2
2K2
6142
C
100u
2K2
+12Vstby
10u
+3.9V
6215
12
2240
-13V
3147
2144
10u
1N4004
1000u
22K
1R5
3134
3135
68p
BYW29EX
B
+12V
5210
Vd
3149
22K
3152
6211
0210
Heatsink
Vs
100n
2147
3145
100R
2153
3148
2151
7140
BC847B
470n
Vg
47R
3146
-0.07V
(-0.3V)
7143
BC847B
3132
470p
7125
STP5NB60FP
+33Vstby
15
2136
47R
2146
220p
BAV21
6146
2K7
6145
3131
6141
22K
BAS216
2141
BAS216
3141
3139
470p
2140
100n
100K
3142
3143
100n
1K
6140
BC857B
7141
2142
1K
D
3144
220p
BC847B
7142
2139
220R
C
3140
BAS216
30V
(20V)
6210
2
MECHPART
0125
6130
1M
6131
1M
2K7
+33V
+12Vreg
6132
3125
6125
47p
3126
3200
BYD33J
10
14
83R
1N4006
1N4004 1N4004 1N4004
6154
1N4006
10n
1N4006
6152
BYD33J
3 5120 4
1125
1N4006
2129
220K
UF1922P4
2
1
1R5
3133
2u2
6153
5131
CT286D8
4
68u
5115
1n
0101-1
HSC0528 1
6151
2125
220n
2120
3122
680K
3120
V
B
300V
2u2
VALUE
2119
HSC0528 2
1n
5110
2200
1124
1120
0101-2
A
+33Vctrl
6200
100n
2131
BZX79-C33
A
0290
Heatsink
18
0205
2251
3253
3255
3254
47K
22n
7251
TL431CZ
4K7
470R
+12Vstby
1
+5Vstby
2
-5Nstby
3
-Vgnstby
4
+33Vstby
5
FLYB
6
2235
330u
10K
3234
10K
3233
47R
-Vgnstby
6231
F
2230
100u
BYD33J
BZX79-C33
3230
6230
7
EH-B
F
+4.4V
(+1.7V)
Vreg
1
TCET1102
7200
3250
G
3256
3
+12Vreg
G
4K7
470R
(.....V) MEASURED IN STANDBY
2
Prot_3V3
Vdrain (no disc loaded)
Vdrain (standby)
Vgate (no disc loaded)
Vgate(standby)
Vsource(standby)
Vsource (no disc loaded)
H
H
50V/div DC
5us/div
50V/div DC
5us/div
10V/div DC
5us/div
10V/div DC
5us/div
500mV/div DC
5us/div
500mV/div DC
5us/div
CL 16532095_024.eps
080801
1
2
3
4
5
6
7
8
9
10
11
12
0101-1 B1
0101-2 A1
0125 C6
0205 F12
0210 C8
0240 D8
0260 D8
0290 E9
1120 A2
1124 A4
1125 B4
2119 B4
2120 B3
2125 B6
2126 B6
2127 A4
2129 B6
2130 B7
2131 A7
2136 C7
2139 D3
2140 C4
2141 D4
2142 D2
2143 E3
2144 E4
2145 E4
2146 C5
2147 D5
2151 E5
2152 E7
2153 D5
2200 B9
2201 B10
2210 B9
2211 B10
2212 B9
2214 C9
2215 C9
2220 E9
2221 E10
2222 E10
2223 E10
2230 F9
2235 F10
2240 D9
2241 D10
2242 D9
2251 G9
3120 B3
3122 B3
3123 B2
3125 B5
3126 B5
3127 B7
3128 B7
3129 A5
3131 C6
3132 C6
3133 D6
3134 D6
3135 D6
3139 D4
3140 C5
3141 C4
3142 C3
3143 D3
3144 D2
3145 D4
3146 D5
3147 D5
3148 E5
3149 E7
3150 D6
3151 E4
3152 D5
3200 A10
3201 B10
3220 E11
3221 E11
3222 D11
3223 D11
3230 F9
3233 F9
3234 F10
3250 G8
3253 G9
3254 G10
3255 G9
3256 G9
5110 A3
5115 B3
5120 B4
5121 B4
5125 C7
5131 B7
5210 B10
5240 D9
6125 B7
6128 A4
6129 A5
6130 D7
6131 D7
6132 D7
6140 C5
6141 D4
6142 D6
6143 E6
6144 E6
6145 C4
6146 C6
6151 B5
6152 B5
6153 B5
6154 B5
6200 A9
6201 B10
6210 B9
6211 B9
6215 C9
6220 E8
6221 E8
6230 F8
6231 F9
6240 D9
7125 C6
7140 D4
7141 D3
7142 D2
7143 D3
7200 G7
7220 E9
7241 D11
7251 G8
9110 A3
9115 B3
Electrical Diagrams and Print-Layouts
Power Supply
1
2
3
DVDR980-985 /0X1
4
5
7.
EN 96
6
7
8
9
10
11
12
POWER SUPPLY
A
0209
1
+3V3
2
+3V3
3
+3V3
0221
MECHPART
0207
1
+3V3
1520
2u2
3A15
MP
+3V3
7520
STP16NE06 2520
1
100u
3523
2K2
3522
1K
3521
680R
22n
2
4K7
C
7521
TL431CZ
7
4
8
B
9
+5V
10
STBY_ctrl
7
11
8
12
-5V
3524
+12V
6
+12V
3
6
-5V
3
+12V
5
5
2521
1K5
6520
Prot_3V3
BAS216
+5V
4
+3V3
EH-B
2
+4V6
3525
510R
B
3520
+3V9
5520
A
EH-B
C
5501
+5V
D
4K7
BZX79-C6V8
10K
6515
+4V6
+33Vctrl
+12V
100n
10u
2513
1N4004
E
2511
3511
10K
7512
BC847B
100n
10K
STBY_ctrl
3514
47K
2506
10u
5511
2512
7511
10K
3516
3515
+12V
5505
100u
BYV10-40
+12Vreg
IRLML2502
E
6505
2515
100u
4K7
7502
TL431CZ
3504
2
+5V
-5V
10u
+12V
6512
5515
100u
IRLML2502
3513
-5Nstby
6511
7515
3
BZX284-C8V2
3503
680R
2K2
3501
22n
1
2502
4K7
2501
D
100u
7501
IRLML2502
3502
2u2
3512
+5Vstby
F
F
0200
0201
0202
G
G
H
H
CL 16532095_025.eps
080801
1
2
3
4
5
6
7
8
9
10
11
12
0200 G10
0201 G11
0202 G11
0207 B8
0209 A10
0221 B3
1520 B4
2501 D4
2502 D5
2506 F4
2511 E9
2512 E10
2513 E11
2515 E8
2520 B4
2521 B5
3501 D3
3502 D4
3503 D4
3504 E4
3511 E9
3512 E9
3513 F9
3514 E10
3515 E7
3516 E7
3520 B3
3521 C3
3522 C3
3523 C4
3524 C4
3525 B4
5501 C4
5505 E4
5511 D10
5515 D7
5520 B4
6505 E3
6511 E9
6512 D9
6515 E7
6520 B2
7501 D3
7502 E3
7511 E9
7512 E9
7515 D7
7520 B3
7521 C3
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 97
Layout Power Supply (Top View)
0101 A1
0125 B3
0200 A3
0201 A7
0202 A5
0205 A6
0207 B6
0209 B6
0210 A5
0221 A6
0240 A5
0260 A5
0290 B5
1120 B1
1520 B5
2119 A2
2120 B1
2125 B2
2126 B2
2127 B1
2129 A3
2130 A3
2131 A4
2136 A3
2147 B4
2200 A5
2210 A5
2211 A6
2212 A5
2214 A5
2215 A5
2220 B5
2221 A7
2230 A5
2235 A7
2240 A5
2241 A6
2242 A4
2502 B6
2506 B7
2512 A6
2515 B7
2521 B6
3120 B1
3122 B1
3123 A1
3125 B2
3126 B2
3127 A3
3128 A3
3129 B2
3131 B3
3132 B3
3133 A2
3134 A3
3135 A3
3141 B3
3146 B3
3148 B2
3149 A3
3150 B3
3152 B3
3200 A6
3223 A6
3230 A6
3250 A5
3254 A4
3501 B7
3514 A6
5110 A1
5115 A1
5120 A2
5121 A1
5125 A3
5131 A4
5210 A6
5240 A5
5501 A7
5505 A7
5511 A6
5515 B7
5520 B5
6125 A3
6128 B1
6129 B1
6130 A3
6131 A3
6132 A3
6140 B3
6142 B2
6143 B2
6151 B2
6152 A2
6153 A2
6154 A2
6200 B4
6201 A7
6210 A5
6211 A6
6215 A5
6220 B4
6221 A4
6230 A4
6231 A7
6240 A4
6505 A7
6512 A6
6515 B7
7125 A3
7200 B4
7220 B5
7251 B4
7502 A7
7520 A5
7521 A6
9110 B1
9115 A1
9207 B6
9209 B6
9214 A4
9215 A4
9220 B5
9221 A6
9222 A7
9250 B4
9251 B4
9511 A6
9512 A6
9520 A5
9521 A5
CL 16532095_048.eps
100801
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 98
Layout Power Supply (Overview Bottom View)
2139
2140
2141
2142
A2
A2
A3
A2
2143
2144
2145
2146
A2
A2
A2
A3
2151
2152
2153
2201
A2
B3
A3
B7
2222
2223
2251
2501
A5
B7
A4
A7
2511
2513
2520
3139
B6
A6
B6
A3
3140
3142
3143
3144
PART 1
CL 16532095_49a.eps
A4
A2
A2
A2
3145
3147
3151
3201
A2
A4
A2
B6
3220
3221
3222
3233
B6
B6
B6
B7
3234
3253
3255
3256
B7
A4
A4
A4
3502
3503
3504
3511
B7
B7
B6
B6
3512
3513
3515
3516
B6
B7
B7
A7
3520
3521
3522
3523
B5
B5
B6
B6
3524
3525
6141
6144
B6
B6
A3
A3
6145
6146
6511
6520
A3
B3
B6
B5
7140
7141
7142
7143
A2
A2
A2
A2
7241
7501
7511
7512
B6
A7
B6
B7
7515 B7
PART 2
CL 16532095_49b.eps
CL 16532095_049.eps
100801
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 99
Layout Power Supply (Part 1 Bottom View)
CL 16532095_49a.eps
100801
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 100
Layout Power Supply (Part 2 Bottom View)
CL 16532095_49b.eps
100801
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 101
Display Panel
1
3
4
6
5
STEREO
0
13
10
NICAM
20
DIGITAL
30
MANUAL
40
PCM
OVER
DTS
0
AC-3
10
20
MPEG
DISPLAY HOLDER
PROLOGIC
30
40
VGNSTBY1
2K2
I101
I100
6169
BAW56W
22K
3155
3158
100n
2155
6152
C
7152
I102
3153
6168
BAW56W
6155
BAW56W
6159
1N4148
6157
1N4148
6166
1N4148
A
1N4148
TITLE
67 68 69
B
STN3NE06
F108
GNDD
BC847BW
TRACK
6158
CHAPTER
1N4148
TOTAL
6167
TIME TRACK
1N4148
REMAIN
47n
6151
DVD+RW
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
2152
7153
SAVCD
BAW56W
1 2 3
6197
GNDD
HQ
6165
CHANNEL
1N4148
B
SP
6164
L:P
1N4148
MONITOR
VGNSTBY1
6196
1N4148
6195
1N4148
6193
1N4148
6191
1N4148
6189
1N4148
6187
1N4148
6185
6183
1N4148
SAT
AM
VPS/PDC
3
TIMER
1N4148
6194
1N4148
6192
1N4148
6190
1N4148
6188
1N4148
6186
RECORD
PM
S16977-03
GNDD
1
10u
1N4148
6184
1N4148
6
5
4
22K
3152
DECODER
F107
330u
12
BZX284-C6V8
5153
2154
11
6150
F105
F106
GNDD
10
6161
BAW56W
F104
250mA
PSC
I SAP
OVER
7150
BJ801GNK
VGNSTBY1
F101
F103
1150
9
0206
F102
5151
8
12STBYSI
II
A
7
6160
BAW56W
12STBY
2
3160
C
F109
I150
77
I151
76
I153
75
I158
PH-B
1916
I157
83
10K
10K
3166
I172
270R
I173
3168
7157
BC847BW
HIGH FR
5STBY
14
15
5
11
12
97
NC*
98
99
100
1
NC* NC*
2
3
4
25
26
NC*
27
28
17
18
19
20
21
22
23
24
VASS
P47
P46
P45
P44
P43
P42
P41
P40
P53
P4
P52
P50
P07
P06
P05
P5
P04
P03
P02
P01
P00
P17
P16
P15
P13
P12
P11
P14
10
30
8-BIT
A/D
CONV
31
96
93
BAW56W
6174
BAW56W
94
3165
GND_FC
GND_FC
10K
F116
I167
3
4
6
3194
5STBY
7
2177
4K7
3197
MONITOR
I191
1K
3177
2K2
I188
3178
I
GNDD
GNDD
5
10n
GNDD
CL 26532011_004.eps
150102
GNDD
2
H
10K
2179
1163
1167
OPEN/CLOSE
10K 3147
I166
3146
I165
I164
F114
F113
4100
2K2
1K
3186
2K2
I180
3187
I179
1168
CHANNEL
4K7
3188
3189
47K
10K
I178
REC VOLUME
1174
1K
1159
3151
<
REC VOLUME
GNDD
CHANNEL
I401
I187
GNDD
<
1160
GNDD
7164
GNDD
3145
5STBY
GNDD
I185
12STBYSI
2170
EARTH SPRING
I175
2K2
10K
0204
EARTH SPRING
5STBY
5STBY
3156
0203
EARTH SPRING
3190
5STBY
7166
F136
0202
1u
GNDD
5STBY
5STBY
<
2175
BC847BW
2K2
EARTH SPRING
<
PDTC124EU
I197
1K
0201
2K2
7165
PLAY
MCL4148
GNDD
10K
GNDD
GNDD
1169
GNDD
STOP
7
7
I177
6198
1170
I184
AUTO-MAN
REC VOLUME
3192
3
RECORD
7
I400
GNDD
4151
9
7
5STBY
5STBY
OPTION
10n
GNDD 7160-A
7160-B
HEF4093BT 14
HEF4093BT 14
5
1
4
10 6
2
BC847BW
1
BAW56W
P2
G
1K
I176
11
F129
10n
1171
7160-C
HEF4093BT 14
8
5STBY
5STBY
1
F
15p
I406
3183
7160-D
HEF4093BT 14
12
GNDD
GNDD
I404
2173
5STBY
5STBY
2169
F135
NC
9
3180
stbyled
8
2K2
F134
7
10n
1162
4
6
3171
Key in
P10
P33
P32
16
P0
P51
P1
I402
3170
MCL4148
1156
F133
GNDD
GNDD
3148
6156
I199
5STBY
100n
47u
2151
2150
5
OPTION
2165
10n
F121
470p
2167
3173
IRR
CST
2163
LOW FR
I168
13
F132
Hz
4M7
temp_sense
6
I156
XOUT 91
12M
3174
F130
GNDD
15p
I155
XIN 89
PF0
13
GNDD GNDD
10u
1917
6173
I143
GENERATOR
2162
GNDD
100R
5STBY1 GNDD
CABLE TREE
6171
I142
P87
CLOCK
WATCHDOG
TC1
TC2
GNDD
PF1
I403
GNDD
VGNSTBY1
I141
ETC1
SIO0/1
TIMING GENERATOR
TIMER
4K7 I174
5STBY
5M
5150
1
INTERFACES
SIO3
I2C BUS
F122
3172
GNDD
5STBY
2
TC4
TEST 95
STANDBY CONTROLLER
TIME BASE
TIMER
16-BIT
TIMER/
COUNTERS
EXPANSION
TIMER/
COUNTER 1
SERIAL
P3
220n
3
SYSTEM CONTROLLER
82
2171
F131
PF2
P31
RC
3167
PF3
8-BIT
TIMER/
COUNTER
P30
INT
I171
E
OPTION
INTERRUPT CONTROLLER
PE0
1K5
9 F125
10 F126
10K
3182
SCL
RAM
RESET_ 92
270R
GNDD
8 F124
3164
I170
I198
7 F123
VDD3 51
TLCS-870/X
CPU
DATA MEMORY
PE1
10n
SDA
PROGRAM MEMORY
ROM
PE2
PF
I162
IPOR1
6 F120
10K
I161
84
GNDD
3154
85
3193
86
I160
3169
I159
5STBY1
VDD2 32
PF4
12STBY
5 F119
12 F128
5STBY 5STBY
VGNSTBY
4 F118
11 F127
5STBY
100p
3 F117
temp_sensor
10K
2 F115
PE3
74
2168
1 F112
7
BAW56W
6172
78
VGNSTBY1
PE4
1153
I149
F111
100n
68K
GNDD
VKK 87
VDD1 88
2159
79
VSS2 90
VFT DRIVE CIRCUIT
PE5
100n
I147
P6
P7
2158
3161
P8
GNDD
80
P9
PD
PE6
P22
I146
68K
GNDD
3162
GNDD
BZX384-C2V7
GNDD
6154
GNDD
PE7
81
P21
9100
I154
100n
2174
E
I152
D
VSS1 29
I144
I145
7155
BC847BW
P90
PD0
VGNSTBY1
7156
TMP88CU77F
P67
I140
40
P66
I139
39
P65
I138
38
P64
I137
37
P63
I136
36
P62
I135
35
P61
I134
34
P60
I133
33
P77
I132
48
P76
I131
47
P75
I130
46
P74
I129
45
P73
I128
44
P72
I127
43
P71
I126
42
P70
I125
41
P86
I124
57
P85
I123
56
P84
I122
55
P83
I121
54
P82
I120
53
P81
I119
52
P80
I118
50
P97
I117
49
P96
I116
65
P95
I115
64
P94
I114
63
P93
I113
62
P92
I112
61
P91
I111
60
PD7
I110
59
PD6
I107
58
PD5
I106
73
PD4
I109
72
PD3
I108
71
PD2
I105
70
PD1
I104
1N4148
6176
1N4148
6178
1N4148
6180
69
P20
VGNSTBY
12STBY
100n
2161
100n
2160
100n
2156
GNDD
I
68
VAREF
5STBY
I148
H
67
PE
5M
VGNSTBY1
VGNSTBY
G
66
10K
1N4148
6182
F110
F
BAW56W
6170
6175
1N4148
6177
1N4148
{P(37:0),G(15:0),P(77)}
GNDD
D
3163
6179
GNDD
1N4148
5K6
6181
5K6
1N4148
3159
10n
3150
47K
5R6
BC847BW
100n
2157
5R6
MCL4148
7151
I103
3157
2180
8
9
10
11
12
13
0201 I1
0202 I2
0203 I3
0204 I4
0206 A12
1150 A1
1153 F13
1156 I5
1159 I9
1160 I9
1162 I8
1163 H12
1167 H9
1168 H9
1169 H9
1170 H8
1171 H8
1174 I10
1916 E1
1917 H1
2150 H2
2151 H2
2152 B2
2154 B1
2155 B1
2156 E1
2157 D1
2158 E12
2159 E13
2160 E1
2161 E2
2162 E13
2163 F13
2165 F13
2167 G2
2168 G1
2169 H4
2170 I8
2171 G3
2173 H8
2174 E2
2175 H11
2177 I12
2179 H12
2180 C1
3145 H13
3146 H10
3147 H11
3148 G9
3150 C1
3151 I6
3152 A1
3153 C2
3154 F3
3155 B1
3156 I7
3157 C3
3158 B1
3159 C1
3160 C2
3161 E4
3162 E4
3163 D1
3164 F3
3165 I6
3166 F3
3167 G3
3168 G3
3169 F2
3170 G5
3171 I8
3172 G1
3173 G1
3174 G3
3177 I9
3178 I9
3180 I8
3182 H5
3183 H8
3186 H9
3187 H9
3188 H9
3189 H8
3190 H8
3192 I1
3193 F2
3194 I13
3197 I10
4100 G10
4151 H5
5150 H1
5151 A1
5153 A2
6150 A4
6151 C1
6152 B9
6154 E3
6155 A13
6156 G3
6157 A13
6158 A13
6159 A13
6160 A11
6161 A12
6164 A12
6165 A12
6166 A12
6167 A13
6168 A13
6169 B9
6170 D12
6171 D13
6172 C13
6173 D13
6174 C13
6175 D4
6176 D4
6177 D4
6178 D4
6179 D4
6180 D4
6181 D3
6182 D3
6183 B3
6184 A3
6185 B3
6186 A3
6187 B4
6188 A4
6189 B4
6190 A4
6191 B4
6192 A4
6193 B4
6194 A5
6195 B5
6196 A5
6197 B6
6198 H6
7150 A5
7151 C1
7152 C2
7153 C2
7155 E4
7156 D12
7157 G2
7160-A H4
7160-B H4
7160-C H3
7160-D H3
7164 I6
7165 H6
7166 I6
9100 E3
F101 A3
F102 A2
F103 A2
F104 A1
F105 A1
F106 A1
F107 B1
F108 B2
F109 C3
F110 D1
F111 E13
F112 F1
F113 G10
F114 G10
F115 F1
F116 H11
F117 F1
F118 F1
F119 F1
F120 F1
F121 H7
F122 H7
F123 F1
F124 G1
F125 G1
F126 G1
F127 G1
F128 G1
F129 H5
F130 H2
F131 H1
F132 I1
F133 I1
F134 I1
F135 I1
F136 I1
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 102
Layout Display Panel (Top View)
0206
1140
1150
1153
A4
B2
A1
A5
1156
1159
1160
1162
A7
B9
A9
B8
1163
1167
1168
1169
B7
B9
A9
A8
1170
1171
1174
1910
A9
A7
A1
B4
1911
1915
1916
1917
B4
B1
A1
A1
2140
2150
2152
2154
B1
A3
A2
A2
3110
3135
3152
3154
B4
B1
A1
A1
3156
3157
3164
3166
A3
A2
A5
A4
3167
3168
5150
5151
A4
A3
A2
A1
5153
6140
6157
6158
A2
B2
A3
A3
6159
6164
6165
6166
A3
A3
A3
A3
6167
6175
6176
6177
A3
A5
A5
A5
6178
6179
6180
6181
A5
A5
A5
A5
6182
6183
6184
6185
A5
A5
A5
A5
6186
6187
6188
6189
A5
A5
A6
A6
6190
6191
6192
6193
A6
A6
A6
A6
6194
6195
6196
6197
A6
A6
A6
A6
7140
7150
9100
9101
B1
A4
A2
A5
9102
9103
9104
9105
A4
A3
A3
A3
9106
9107
9108
9109
A2
A4
A5
A6
9110
9111
9112
9113
A4
A4
A4
A3
9114
9115
9116
9151
A3
A2
A2
B3
CL 26532011_007.eps
170102
Layout Display Panel (Overview Bottom View)
2100
2101
2102
2103
2104
2105
2106
B6
B7
B7
B7
B7
B7
B5
2151
2155
2156
2157
2158
2159
2160
A7
A8
A9
A8
A5
A5
A8
2161
2162
2163
2165
2167
2168
2169
A9
A5
A5
A5
A8
A8
A7
2170
2171
2173
2174
2175
2177
2179
B2
A8
A3
A9
A7
A9
B3
2180
3100
3101
3102
3103
3104
3105
A8
B7
B7
B7
B7
B7
B7
3106
3107
3108
3109
3111
3112
3113
B7
B7
B7
B7
B6
B6
B5
3136
3137
3138
3139
3140
3141
3142
B8
B8
B8
B8
B9
B8
B8
3143
3144
3145
3146
3147
3148
3149
B8
B8
A9
A7
A7
A7
B9
3150
3151
3153
3155
3158
3159
3160
A8
A9
A8
A9
A8
A8
A8
3161
3162
3163
3165
3169
3170
3171
A7
A7
A8
A7
A8
A7
A9
3172
3173
3174
3177
3178
3180
3182
A8
A8
A8
B1
A1
B2
A4
3183
3186
3187
3188
3189
3190
3192
A9
B1
A1
A2
A1
A3
A9
3193
3194
3197
3999
4100
4101
4102
A8
A9
A9
B9
A7
B7
B7
4103
4104
4105
4106
4107
4108
4109
A9
A9
A9
A9
A9
A8
A8
4110
4111
4112
4113
4114
4115
4116
A8
A8
A7
A7
A6
A5
A7
4117
4118
4119
4120
4121
4122
4151
A9
A9
A9
A9
A9
A9
A7
4300
6100
6101
6102
6103
6104
6150
B9
B7
B6
B6
B6
B6
A8
6151
6152
6154
6155
6156
6160
6161
A8
A8
A8
A6
A8
A8
A7
6168
6169
6170
6171
6172
6173
6174
A7
A7
A5
A6
A6
A6
A6
6198
7100
7101
7141
7142
7143
7144
A7
B7
B6
B8
B8
B8
B8
7145
7151
7152
7153
7155
7156
7157
B8
A8
A8
A8
A7
A6
A8
7160
7164
7165
7166
A7
A9
A7
A7
Part 1
CL 26532011_08a.eps
Part 2
CL 26532011_08b.eps
CL 26532011_008.eps
170102
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 103
Layout Display Panel (Part 1 Bottom View)
CL 26532011_08a.eps
170102
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 104
Layout Display Panel (Part 2 Bottom View)
CL 26532011_08b.eps
170102
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 105
Front AV Part
5
6
A
F200
3101
8
2101
1K
I301
7100
BC847BW
1u
A
GND_FC
4K7
3104
3103
680K
4101
3102
2102
YKC22-0489 7
1910-B
1M
6100
6
330p
AR
I300
8
100n
3100
OPTION
7
2100
4
8SW_FC
3
8SW_FC
2
470K
1
F201
3105
OPTION
C
F202
3106
11
2104
1K
I303
7101
BC847BW
1u
C
GND_FC
4K7
3109
3108
680K
4102
3107
2105
YKC22-048910
1910-C
1M
6101
9
330p
AL/MONO
I302
B
8SW_FC
GND_FC
100n
GND_FC
2103
GND_FC
8SW_FC
GND_FC
470K
GND_FC
GND_FC
8SW_FC
DF3A6.8FU
B
DF3A6.8FU
GND_FC
GND_FC
D
GND_FC
F206
12
F211
GND_FC
150R
75R
3111
13
YKC22-0489
1910-A
GND_FC
3110
6102
CVBS
GND_FC
GND_FC
DF3A6.8FU
GND_FC
GND_FC
1911
F203
1
F204
2
F205
3
F207
4
F208
5
F209
6
F210
7
F212
8
F213
9
AFCRI_FC
GND_FC
AFCLI_FC
CVBSFIN_FC
GND_FC
8SW_FC
CFIN_FC
GND_FC
YFIN_FC
6103
75R
GND_FC
3112
PH-S
E
D
E
GND_FC
DF3A6.8FU
3
4
1
2
1910-D
GND_FCGND_FC
F
GND_FC
GND_FC
6104
75R
YKC22-0489
3113
2106
I304
F
DF3A6.8FU
100n
5
GND_FC
CL 26532011_006.eps
150102
GND_FC
1
2
3
4
5
6
7
8
1910-A D1
1910-B B1
1910-C C1
1910-D F1
1911 D8
2100 A6
2101 A5
2102 B3
2103 C6
2104 C5
2105 D3
2106 F2
3100 A5
3101 A3
3102 B4
3103 B5
3104 B6
3105 C5
3106 C3
3107 D4
3108 D5
3109 D6
3110 D4
3111 D2
3112 E2
3113 F2
4101 B4
4102 D4
6100 A3
6101 C3
6102 D3
6103 E3
6104 F3
7100 A6
7101 C6
F200 A2
F201 B1
F202 C2
F203 D7
F204 D7
F205 D7
F206 D2
F207 D7
F208 D7
F209 D7
F210 D7
F211 E1
F212 E7
F213 E7
I300 A3
I301 A5
I302 C3
I303 C5
I304 F2
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 106
Layout Front AV Part
CL 16532095_035.eps
080801
2100
2101
2102
2103
2104
2105
2106
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3111
3112
A3
A3
A3
A2
A2
A2
A1
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
A1
A1
1910
1911
A2
A2
3113
4101
4102
6100
6101
6102
6103
6104
7100
7101
A1
A3
A2
A3
A3
A2
A1
A1
A3
A2
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 107
IR and Standby Panel
I312
A
7143
BC857BW
4K7
I314
7141
PDTC124EU
3137
I313
7142
BC847BW
4K7
B
6140
GND LTL-14CHJ
2
GND
B
5VSTBY
3139
10K
3138
1
2
F301
3
F302
4
F303 key in 3142
5
F304 IRR
6
F305
7
F306 temp_sense
NC
I317
5VSTBY
stbyled
I315
1140
I319
3141
STBY
47K
I318
GND
3142
3140
7145
BC847BW
4K7
5VSTBY
D
GND
220R
GND
7140
TSOP2236
I320
2 VS
CTRL
CIRCUIT
GND
1 OUT
2140
E
22u
DEM
GND
1
C
7144
BC857BW
4K7
3140
CABLE TREE
I316
3149
F300
t
2322640
D
1915
3135
C
390R
1
5VSTBY
Layout IR and Standby Panel (Bottom View)
3149
I311
3136
3138
I310
3999
A
3139
390R
3144
10K
3143
5VSTBY
3141
5VSTBY
IR and Standby Panel
3143
4
3144
3
3136
2
Layout IR and Standby Panel (Top View)
3137
1
1140 D2
1915 C1
2140 E2
3135 D1
3136 A3
3137 B3
3138 C3
3139 C4
3140 D2
3141 D3
3142 D2
3143 A3
3144 A4
3149 C3
3999 A2
6140 B4
7140 D4
7141 A2
7142 B4
7143 A4
7144 C4
7145 D4
F300 C1
F301 C1
F302 C1
F303 D1
F304 D1
F305 D1
F306 D1
I310 A4
I311 A2
I312 A3
I313 B3
I314 A4
I315 D4
I316 C4
I317 C3
I318 D3
I319 D2
I320 D3
2
BAND
PASS
INP
AGC PIN
3 GND
E
GND
3
4
CL 26532011_005.eps
170102
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 108
Analog Board: All in One 1
4K7
27
28
29
100R
P63|PMW7
PC3|AIN14
PA5|PWM3|HWR_
PC4|AIN15
PA3|PWM2
P80|CTLIN
PWM1
P81|DFGIN
PWM0
P82|RMTIN
PA2|CR|TPG00
PA1|HA|TPG05
P84|DPGIN
PA0|PV|PH
P85|CFGIN
P97|TPG11
P86|CSYNCIN
P87|COMPIN
36
37
38
39
P96|TPG10
GNDD
VGNSTBY
12STBY
E0
ST24E16
7815 E1
E2
1
3
100R 5,2V 5
SCL
VSS
109 I843
4 0V
5,2V
6 0V
7
3914
WC_
0V
2 0V
108 I844
107 I845
3840
106 I846
100R
102 I948
3844
100R
101 I848
1K
3846
100 I849
3847
1K
99
I862
3K3
98
I863
I865
95
I867
SCL
F8112 4801
GNDD 1987
1981
1
3889
1
1K
3865
12STBY
VGNSTBY
GNDD
100R
91
GNDD
89
SDA
88
GNDD
87
SCL
86
100n
D
GNDD
GNDD
TEMP_SENSE
2823
100p
not used
2809
100p
not used
2808
SDA
10K
I864
96
C
3841
3899
97
100R I946
2K2
3834
2K2
3833
100R
3836
not used
10K
3823
I833 3819
PB4|SDA1
100R
PB5|SCL1
1K
I832 3818
P50|INT4|TI3
100R
P51|INT3|TI2
I831 3817
I830 3816
P52|INT2|TI1
I829
P64|PWM8
P83|EXT
5STBY2
5STBY
8
F8008
5SW
7
F8007
8SW
6
5NSTBY
IPOR_EPG
PH-B
INT_EPG
5
not used
F8003
F8006
4
F8001
100p
2805
not used
F8005
3
1980
2
1
2K2
F811
100p
2804
not used
F810
SCL1
GNDD
SDA1
5SW
A_YCVBS
GNDD
A_YCVBS
from VPS
SDA1
to TU, AP, VPS
3805
3804
2n2
100K
2K2
3802
FOME
from FOME
SCL1
to TU, AP, VPS
2801
not used
P53|INT1
P65|PWM9
PC2|AIN13
85
84
42
F8101 2
2
F8102 3
3
F8103 4
4
F8104 5
5
F8105 6
6
12STBY
VGNSTBY
GNDD
IPOR1
F8106 7
7
8
F8108 9
9
F8109 10
10
F8110 11
11
PH-B
41
E
SDA
F8107 8
GNDD
SCL
INT
RC
5STBY
12
5M
F
PH-B
5M
F8111
40
6807
GNDD
100R
100R
3890
100R
3864
3863
100R
2K2
3885
I854
3870
100R
3K3
I855
3869
10K
I856
3868
100R
I857
3897
for SATCONTROL only
I858
1K
for HDR only
3884
470u
not used
2813
220m
2811
10K
TMP93C071
PC1|AIN12
10K
3879
BAS385
6805
I875
from PS
I892
MCL4148
G
I876
2
3
4
5
5
3875
F8206
6
1K
F8207
7
10K
3880
D_DATA
F8208
8
3814 for SAA7118 (VIP) only F8209
9
I813
F808
GNDD
F8210
6
7
8
9
10
ION
WE
BE_FAN
FB
10
GNDD
BE_FAN
FBIN_SC2
WE
RC
ISTBY
CL 16532095_009.eps
070801
11
12
13
H
D_RDY
FMN
YUV_ON
GNDD
SW_CAB_FAN
TEMP
GNDD
4
GNDD
SW_BE_FAN
GNDA
F8204
100R
FL_READY
A_YCVBS
GNDA
3
F8205
ADDRESS
REGISTER
SC1YC_H
10K
7813
BC847BW
I878
F8203
A_RDY
CLOCK /
4
I877
5,1V
0,1V
GNDA
CONTROL
LOGIC
VSS
3881
47R
2
A_DATA
SC2RGB_H
3887
5STBY2
I880
470K
BC857BW
7812
3886
1
IRESET_DIG
DIVIDER
VMUTE
100R
I881
I 2 C-BUS
INTERFACE
1982
F8201
F8202
5STBY2
I822
100R
7811
PCF8593T
SATCO
3878
12K
CALENDAR
6 SCL
5,1V
5 SDA
5,1V
SDA
100K
P70|TXD
P67|PWM11
P66|PWM10
ION_FAN
3877
SCL
GNDA
GNDA
I888 3882
3873
2,5V
2 OSCO OSCILLATOR
4,8V
F803
7 INT_
0V
3 RESET
I874
RESET
5,1V
330R
I887
22K
10K
18p
2815
10n
2814
I882 3883
2817
SYNC 3
5
3888
P71|RXD
P44|AIN7
PC0|AIN11
B
0V
10n
1u
2816
5,1V
8
VDD
I872
2818
I885
GND
1
P72|CTS_
VCC
110 I842
GNDD
1 OSCI
DT-38
32K768
6
SYNC
SEPA
V.SEPA
GNDD
1802
PHASE
COMP
330R
I871
3876
7
VCC
8
2 HD
4
P43|AIN6
P47|AIN10
GNDD
3874
5SW
1n
H
H.OSC
GNDD
I870
100n
2812
1
P73|SDA0
7803-B
VGNSTBY
GNDD
SDA
119 I841
3898
10K
7810
GNDA
BA7046F
P74|SCL0
P42|AIN5
P45|AIN8
12STBY
IPOR
GNDD
F804
GNDD
P41|AIN4
35
GNDD
5SW
I886
33
34
P75|SO0
I861
I898
10K
3861
GNDD
F812
5STBY2
3872
G
1n
2810
not used
4906
PDTA124EU
7807
7809
BC847BW
22K
31
GNDD
2K2
3857
I896
3862
I970
32
I897
I899
10K
3896
5SW
100n
2827
220K
3895
5SW
30
P77|SCK0
P40|AIN3
P46|AIN9
5STBY2
5STBY
5STBY2
5STBY
26
47K
FLYB
I
3830
3860
3866
5NSTBY
5SW
F_MODE
I903
24
PB3|SCK1
PB2|SO1|SI1
120 F800
100R
for SW contr. (FACO) only 3916
23
5SW
6K8
3859
100K
100K
3858
8SW
16_SC2
8SW
3915 I945
I983
22
I859
4K7
GNDA
5NSTBY
5,2V
for SW contr. (FACO) only 3917
21
I974
100R
3894
GNDA
GNDD
A
8
I852
10K
I973
not used
5SW
14
5STBY2
I853
20
I866
1
P95|TPG13
I839
2
P94|TPG04
10K
3891 not used
4K7
IPFAIL
F
GNDD
3828
13
AIO1
100R
GNDD
3
P93|TPG03
3893
3845
10K
3849
7805
BC847BW
100K
F8004
100R
P76|SI0
P92|TPG02
19
25
GNDA
F8002
3826
P57|TI0|AIN2
P91|TPG01
I838
4
P56|TI4|AIN1
3867
5STBY2
3892
KIR
E
100R
3871
17
18
5
P90|TPG12
I971
10K
GNDD
GNDD
3856
100K
10K
3835
4K7
3820
3839
10K
10K
16
I976
10K
I894 3855
27K
3801
GNDD
GNDD
15
I972
I975 3851
4K7
3852
14
3850
100K
3853
10
I977
4u7
3843
5STBY
100K
9
I979
10K
KIL
GNDA 5NSTBY BC857BW
7806
I893
I980
P54|INT0
P55|TI5|AIN0
6
100R
47K
I891
2822
8
I978
3848
5STBY2
to EPG
12
5STBY2 5STBY2
I981
5STBY
5SW
GNDD
GNDD
3824
5SW
11
6K8
I982
7
10K
BC857BW
I890 7804
3808
10K
3825
470n
3821
4u7
I810 3831
GNDD
GNDD
10
GNDD
10K
2821
GNDD
I807
7801
BC847BW
220R
3812 I835
3800
680K
MCL4148
11 12STBY
220p
2803
I818
I817
I819
I821
I815
I837
I836
470n
680K
4K7
2802
GNDD
2807
9
GNDD
P50
IS1
IS2
WSRO
WSFI
WSRI
VD
WU
100n
47u
6803
1K
3854
100K
7800-C
TL074
8
7817
BC847BW
GNDD
GNDD
3813
GNDD GNDD
4
470n
1%
11
3832
2832
2831
GNDD
7800-B
TL074
2820 I809
7 I808
10
9
3803
BAS385 I823
33K
I804 3809
4K7
6
D
GNDD
3838
470n
C
3811
3810
100K
MCL4148
11 12STBY
10K
4
8
5STBY2
5NSTBY
GNDD
F802 2806 I806 5
7
GNDD
7816
BC847BW
I801
3837
B
13
6
6801
7800-D
TL074
14 6802
3842
GNDD
ARADC
2K7 1%
3822
100K
3815
11
4
470n
100K
A
2K7 1%
2
7800-A
TL074
2819
I803 12
1 I802
3807
4
470n
1K 1%
F801 2800 I800 3
12STBY
3829
ALADC
5
I820
All In One 1
4
AFC
3
AGC_MUTE
2
I816
1
14
I
1802 H4
1980 A10
1981 D13
1982 H14
1987 D14
2800 A1
2801 A8
2802 A4
2803 A7
2804 A9
2805 A9
2806 B1
2807 B4
2808 D12
2809 D12
2810 F3
2811 G6
2812 G1
2813 G6
2814 H4
2815 H5
2816 H3
2817 H3
2818 I6
2819 A2
2820 B2
2821 B4
2822 C4
2823 D14
2827 F2
2831 A3
2832 A4
3800 B4
3801 A7
3802 A8
3803 A8
3804 A9
3805 A9
3807 A2
3808 A7
3809 B4
3810 A2
3811 A4
3812 B6
3813 A4
3814 I13
3815 A2
3816 B8
3817 B9
3818 B9
3819 B9
3820 B6
3821 B5
3822 A1
3823 B10
3824 C4
3825 C5
3826 A10
3828 A10
3829 B2
3830 E6
3831 C4
3832 C1
3833 B12
3834 B12
3835 B6
3836 B11
3837 B2
3838 B4
3839 C6
3840 C10
3841 C11
3842 B4
3843 D5
3844 D10
3845 D5
3846 D11
3847 D10
3848 D3
3849 D4
3850 D2
3851 D4
3852 D1
3853 D1
3854 C2
3855 E3
3856 B7
3857 F4
3858 E1
3859 E2
3860 E6
3861 G5
3862 F3
3863 F10
3864 F10
3865 E10
3866 E5
3867 G8
3868 G9
3869 G9
3870 G9
3871 B8
3872 G5
3873 G6
3874 G7
3875 H13
3876 H3
3877 H5
3878 I4
3879 F6
3880 H8
3881 I5
3882 I1
3883 H3
3884 G7
3885 G9
3886 I4
3887 I2
3888 I1
3889 D11
3890 G11
3891 D6
3892 D6
3893 D5
3894 E1
3895 F2
3896 F6
3897 G8
3898 G2
3899 D11
3914 C14
3915 C13
3916 F11
3917 F11
4801 D13
4906 G2
6801 A7
6802 A3
6803 B3
6805 F6
6807 F13
7800-A A2
7800-B B2
7800-C B3
7800-D A3
7801 A7
7803-B D8
7804 D1
7805 D3
7806 E2
7807 F5
7809 F4
7810 H1
7811 H7
7812 I3
7813 I5
7815 B13
7816 A3
7817 B3
F800 C10
F8001 A10
F8002 A10
F8003 A11
F8004 A11
F8005 A11
F8006 A11
F8007 A11
F8008 A11
F801 A1
F802 B1
F803 H5
F804 G5
F808 I10
F810 A9
F8101 D13
F8102 E13
F8103 E13
F8104 E13
F8105 E13
F8106 E13
F8107 E13
F8108 E13
F8109 F13
F811 A9
F8110 F13
F8111 F13
F8112 D13
F812 F6
F8201 H13
F8202 H13
F8203 H13
F8204 H13
F8205 H13
F8206 H13
F8207 H13
F8208 I13
F8209 I13
F8210 I13
I800 A1
I801 A3
I802 A2
I803 A2
I804 B3
I806 B1
I807 C3
I808 B2
I809 B2
I810 C3
I813 I11
I815 A5
I816 A5
I817 A6
I818 A6
I819 A6
I820 A5
I821 A5
I822 I9
I823 A7
I829 B8
I830 B8
I831 B9
I832 B9
I833 B9
I835 A6
I836 A5
I837 A5
I838 D6
I839 D6
I841 C10
I842 C10
I843 C10
I844 C10
I845 C10
I846 C10
I848 D10
I849 D10
I852 F10
I853 F10
I854 G9
I855 G9
I856 G9
I857 G8
I858 G8
I859 D7
I861 G8
I862 D10
I863 D10
I864 D10
I865 D10
I866 D6
I867 E10
I870 G5
I871 H4
I872 H5
I874 H5
I875 H5
I876 H5
I877 I6
I878 I5
I880 I4
I881 I4
I882 H3
I885 H2
I886 G1
I887 I1
I888 I1
I890 D1
I891 D2
I892 F14
I893 E2
I894 D2
I896 F3
I897 F4
I898 F5
I899 F2
I903 F11
I945 B13
I946 C14
I948 D10
I970 E7
I971 D6
I972 C6
I973 E6
I974 D6
I975 D3
I976 D6
I977 C6
I978 C6
I979 C6
I980 C6
I981 C6
I982 A7
I983 F11
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 109
Analog Board: All in One 2
1
2
3
4
5
6
9
11
10
12
13
14
1994 I3
2900 A2
2901 B14
2902 B13
2903 B14
2904 H14
2905 H14
2906 H14
2907 D14
AIO2
Pos. 3920, 3921,3922, 7902,7903, 7904 are for "ON-BOARD-PROGRAMMING"
FL_READY
TS
SAWS
SB1
PSS
IPOR
All In One 2
8
7
5STBY2
5STBY2
5STBY2
3902
10n
4K7
10K
47K
3900
4K7
5
RESET
VS
RESETQ_ SENSE
RESIN_
I942 1 REF
CT
A
8
7
2
3
I943
2901
2900
6
47u
GNDD
10K
3911
A
3901
7900
TL7705
3918
I905
B
GNDD
GNDD
F942
F943
F926
10n
7909
PDTC124EU
C
GNDD
PDTA124EU
7908
BSH111
7902
2913
not used
GNDD
10K
3919
1K
3905
1K
1K
3904
3903
3920
220K
4901
not used
F937
2903
5STBY2
12STBY
not used
100n
2902
12STBY
B
4
220n
GND
I902
C
7901
PMBT2369
I847 3912
5,1V
GNDD
GNDD
WE
0V
F902
10K
45
F935
44
D0
F936
43
D2
D1
D0
H
59
13
3925
F901
117
0,2V
F919
F920
F921
F922
F923
VSS1
VSS2
A11
34
A10
32
30
A9
A8
44
D7
A7
A6
D6
42
D5
40
38
D4
A5
A4
D3
35
A3
D2
33
A2
D1
31
A1
D0
29
A0
DQ12
A12
DQ11
A11
DQ10
A10
DQ9
A9
DQ8
A8
A7
DQ7
DQ6
DQ5
DQ4
DQ3
4
5
6
A2
8
A3
7
A4
6
A9
A5
5
18
A8
A6
4
A7
A6
21
A5
A4
A7
3
A12
2
A14
22
A4
A13
23
A3
A8
A3
A2
1
A9
24
A11
23
A10
OE_
CE_
28
22
4
20
25
23
A9
26
A8
A7
I|O6
A6
A5
I|O5
A2
I|O4
I|O3
I|O2
A1
I|O1
A0
VCC I|O0
21
7905
28
27
D7
I|O7
F941
2918
27
WE_
A10
A3
A1
3
A11
A4
A2
37
A12
25
25
31
A13
26
24
A1
2
14
A14 GND
not used
2909
10n
2907
3913
33K
A12
5STBY_F
116
0,1V
3906
9
8
A5
A0
A0
A1
A11
20
VCC
GNDD
10
A13
7
19
DQ1
DQ0
A14
A6
DQ2
7906
I915
I914
NC
DVCC2
ADREF
AM8|16_
DVCC3
113 2,2V 112
2,1V
114
F918
36
A13
A15
3
19
18
D6
6
D5
17
D4
16
D3
15
D2
13
D1
12
5
7
8
9
10
11
D0
12
11
5STBY_uP
5,1V
NC
GND
A16
A15
A14
WE_
A13
OE_
A12
CE1_
A11
CE2
29
F
24
22
5STBY_uP
30
A10
A9
A8
A7
I|O7
A6
I|O6
A5
A4
A3
I|O5
I|O4
I|O3
A2
I|O2
A1
I|O1
A0
VCC I|O0
21
D7
20
D6
19
D5
18
D4
17
D3
15
D2
14
D1
13
D0
G
5STBY2
5STBY_uP
5STBY
F900
I947
32
7907
GNDD
100n
GNDD
GNDD
5903
5901
100MHZ
100MHZ
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
F940
I
220K
not used
C900
5904
100MHZ
3924
4903
7904
BSH111
12STBY
100n
33p
27p
2910
I
2911
AT-49
20M00
GNDD
1994
GNDD
H
100n
F934
D1
D3
F917
A12
DQ13
A16
2
1
47u
D2
D4
F916
39
A14
16
GNDD
2906
46
F914
F915
A13
A15
DQ14
A17
1
5STBY2
47
F933
F913
A14
41
DQ15|A-1
A18
48
2905
F932
D3
D5
F912
43
17
5STBY
D4
D6
F911
45
A15
A16
1u
48
D7
F910
A16
RB_
2904
49
D8
F909
A17
15
A17
GNDD
A19
100n
F931
50
D9
F908
A18
E
F925
16
2917
D5
F930
D10
F906
26
E_
A18
2916
D6
F929
D11
F905
G_
100n
D7
TMP93C071
F904
A19
F924
28
100n
51
13
11
W_
2915
52
14
12
RP_
100n
53
I936
F903
220K
2914
54
GNDD
D12
9
D
GNDD
GNDD
not used
CY62128
55
D13
I934
12STBY
47
CY62256
56
D14
81 0V
P25|A21
5,1V
80
P24|A20
0V
79
A19
78
A18
77
A17
76
A16
75
A15
74
A14
73
A13
72
A12
71
A11
70
A10
69
A9
68
A8
67
A7
66
A6
65
A5
64
A4
63
A3
62
A2
61
A1
60
A0
BYTE_
10
GNDD
F
7803-A
D15
I935
GNDD
57
RD_
I938
82 0,1V
P26|A22
PB0|XT1
58
PB1|XT2
103
83 5,1V
P27|A23
7903
BSH111
F939 3921
not used
46 27
11
PA4|WR_
X1
100R
DVCC1
EA_
I904
12
104
P60|PWM4|CS0_
X2
3907
105
22R
F928
90
111
DGND1
I984
92
DGND2|ADGND
F927
115
RESET_
94
P62|PWM6|CS2_
5,1V
I901 93
P61|PWM5|CS1_
DGND3
100R
3909
E
5,1V
5,1V
I900
GNDD
M29F800AT
1K
not used
3910
3908
100R
4907
GNDD
118
G
GNDD GNDD
5STBY_uP
4902
D
100K
5,1V
F938
not used
5STBY 5STBY2
5STBY2
GNDD
CL 16532145_130.eps
121201
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2909 H6
2910 I3
2911 I3
2913 C7
2914 H12
2915 H13
2916 H13
2917 H13
2918 I6
3900 A13
3901 A12
3902 A3
3903 B4
3904 B5
3905 B5
3906 E9
3907 E1
3908 D1
3909 E1
3910 D1
3911 A12
3912 C13
3913 D13
3918 A6
3919 B8
3920 B3
3921 D11
3924 I7
3925 H3
4901 B3
4902 D10
4903 I8
4907 D1
5901 H14
5903 H13
5904 I6
7803-A F3
7900 A14
7901 C13
7902 C3
7903 D11
7904 I7
7905 H9
7906 H7
7907 H11
7908 B7
7909 C7
C900 I14
F900 H14
F901 H2
F902 C2
F903 E4
F904 E4
F905 E4
F906 F4
F908 F4
F909 F4
F910 F4
F911 F4
F912 F4
F913 F4
F914 G4
F915 G4
F916 G4
F917 G4
F918 G4
F919 G4
F920 G4
F921 H4
F922 H4
F923 H4
F924 E8
F925 E11
F926 C3
F927 E1
F928 F1
F929 G1
F930 G1
F931 G1
F932 G1
F933 G1
F934 H1
F935 H1
F936 H1
F937 B3
F938 D10
F939 D11
F940 I7
F941 H8
F942 C13
F943 C12
I847 C13
I900 E1
I901 E1
I902 B2
I904 F1
I905 B7
I914 I3
I915 I3
I934 E4
I935 E4
I936 E4
I938 E4
I942 B13
I943 B14
I947 H14
I984 E1
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 110
Analog Board: Tuner / Demodulator
1700 B5
1701 C5
1702 D5
1703 E10
1705 B2
2705 A9
2706 A7
2707 A10
2708 A10
2709 A8
2700 A3
2701 A4
2702 A4
2703 A7
2704 A7
2715 D7
2716 A3
2717 A1
2718 E8
3700 A3
2710 A8
2711 C3
2712 D3
2713 A1
2714 D7
1
3711 A1
3712 D4
3713 D5
3714 C4
3715 D10
3706 A8
3707 A7
3708 A4
3709 A9
3710 D10
3701 A6
3702 A9
3703 A2
3704 A4
3705 A9
2
3
4701 C4
4702 E5
5009 E9
5700 A2
5701 A10
3726 D9
3727 E8
3728 E8
3729 E5
3730 E5
3721 E10
3722 E9
3723 E7
3724 D7
3725 E9
3716 C1
3717 E8
3718 E4
3719 C2
3720 B1
4
5707 E10
6700 B4
6701 C4
6702 E4
6703 E6
5702 A5
5703 B9
5704 E3
5705 A1
5706 A3
5
7700 A10
7701 B5
7702 C5
7703 B7
7704 D10
7705 E7
7706 E9
7707 E4
7708 D2
7709 E9
6
F704 B5
F705 A4
I701 A6
I703 A4
I704 B4
F303 B10
F700 C3
F701 C3
F702 C2
F703 B6
I706 C5
I707 C6
I708 C6
I709 A7
I710 B7
7
I711 A7
I712 B8
I713 A8
I714 B8
I717 A9
I718 A10
I719 E7
I720 A4
I730 E10
I731 E10
8
I732 E9
I733 E10
I734 D10
I735 E8
I736 D9
9
I760 A1
I761 A1
I762 A3
I763 A3
I764 D3
I753 E4
I756 B1
I757 B1
I758 B1
I759 A1
I737 D10
I739 D7
I741 D7
I751 E4
I752 D4
10
Tuner/Demod.
TU
5
SDA1
100R
I706 1
6u8
5701
18K
3705
F303
5V
21
I708
3
5SW
2,8V 5
5,2V 3
1
2V 12
9
13
10
5
6
7
5K6
3726
SB1
680R
6u8
5009
3725
1K
3717
47u
2718
100R
4K7
3724
I735
15u
1703
330R
3
2 TPS
GNDFV
GNDFV
GNDFV
8
GNDFV
9
E
3721
I731 270R
3K3
2K7
3728
3727
1
7706
BC857BW
I730
I733
5707
7709
BC847BW
3722
1n
2715
I719
GNDFV
VFV
SB1
MCL4148
GNDFV
I732
SIF1
6703
AGC_MUTE
5K6
3730
5K6
GNDFV
4
GNDFV
PSS
3729
7707
BC847BW
D
BC857BW
7704
3715
GNDFV
7705
BC847C
GNDFV
3
2u2
2714
GNDFV
GNDFV
GNDFV
5SW
5SW
100K
4702
GND
3
3723
1u
1SS356
GNDFV
3710
100R I737
2
5
11
I734
I739
6K8
3713
3712
6702 I751
GNDFV
2
1702
OFWK9656M
not used
L
H
H
L
I753
4K7
L
L
H
L
1
4
3718
SEC L'
H
L
H
L
5704
SEC L
H
L
L
H
I752
SAWS
PAL I
PAL D/K
SEC D/K
PSS
SB1
SAWS
TS
PAL B/G
SEC B/G
E
2K2
I741
1n
GNDFV
10u
FM-PLL DEMODULATOR
I736
2712
C
8
QSS MIXER
INTERCARRIER MIXER
AM DEMODULATOR
SIF
AMPLIFIER
3,2V 24
2V
VIDEO DEMODULATOR
AND AMPLIFIER
SIF INTERCARRIER
AGC MODE SWITCH
5SW
7708
PDTC124EU
B
VOLTAGE
REFERENCE
GNDFV
I764
20
16
VCO
TWD
FPLL
VIF
AMPLIFIER
3,3V 2
GNDFV
D
10n
2708
2707
18K
2705
3709
100n
17
TUNER VIF
AGC
AGC
3,3V 1
I707
5
GNDFV
GNDFV
3V
2,7V
18
GNDFV
2,7V
19
GNDFV
3,5V
7
GNDFV
220n
I714
3706
330R
2,5V
2u2 low leakage
100n 2703
I711
22K
6
3,2V 23
4K7
3714
4701
not used
1SS356
6701
4K7
3719
4
GNDFV GNDFV
AFC
DETECTOR
4
2
1n
F701
14
1701
OFWG3956M
7702
PDTC124EU
F700
15
5703
GNDFV
GNDFV
5SW
22
A
AFC
3
7KMY
N750
7700
PDTC124EU
GNDFV
1
4
8p2
SB1
7
2
2710
I718
0V
5SW
TDA9818
3
F703
7701
PDTC124EU
2711
7703
5 3,3V
2
8
6
3,1V
11
5SW
AFC-ADJUST
0,9V
1700
OFWK3953M
I704
8
4 3,3V
1
F702
GNDFV
2706
I710
GNDFV
12 13 14 15
C
3707
4K7
3708
7
470p
8
F704
6
GND
1
I709
NC
SDA
3716 I757
6
GNDFV
10
SCL
AGC-ADJUST
5K6
0,7V
NC|ADC
5702
3
2
2702
1SS356
4
AS
GNDFV GNDFV
GNDFV
TS
100R
3
IF
7KMY
4
120p
220p
6700
GNDFV
3720 I756
TU
2701 I720
I717
3702
2704
I703
3704
6u8
5706
I762
100u
2716
2
B
7
9
VCC +33V
I701
I712 2709 I713
680R
100R
33K
22u
3700
3703
150K
2700
5700
Bead
1705
UV1316K 1
AGC
GNDFV
SCL1
5SW
I763
I758
GNDFV
3701
40,4-ADJUST
47n
2u2
2717
GNDFV GNDFV
I759
3711
I760
2713
A
5SW
10u
5705 I761
33STBY
F705
CL 16532095_011.eps
070801
10
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 111
Analog Board: In / Out 1
KIL
from AIO1
KIL
3534 I523
68R
100R
2
3
100R
7512
BC847BW
I522
3551
6500
V
2546
GNDA
GNDA GNDA
470p
RCOUT
16A
17A
GNDV
18A
GNDV
19A
20A
6506
GNDV
1K
F534
0350808190
1950-3
MT1
GNDV
MT2
GNDA GNDV
3555
6508
1K
3553
GNDV
H
3552
150R
VD
to AIO1
10K
I
GNDV
GNDV
3554
75R
C570
GNDA
21A
GNDV
6505
DF3A6.8FU
GNDV
I521
GNDV
from / to IO4
GNDV
CL 16532095_012.eps
080801
11
12
G
GNDV
F531
F530
3549
3547
AROUT_SC2
ARIN_SC2
ALOUT_SC2
ALIN_SC2
FBIN_SC2
8_SC2
GIN_SC2
BIN_SC2
RCIN_SC2
YCVBSOUT_SC2
YCVBSIN_SC2
BC_KILL_DC
from IO4
COUT_SC2
GNDV
15A
GNDV
GNDV
100n
7513
BC847BW
I507
I512
SC1YC_H
from AIO1
GNDV
14A
FBOUT
GNDV
AFEL
from AP
D_CVBS
AFER
from AP
to IO3
D_Y
to IO3
to IO3
D_C
13A
F527
5STBY
100R
10
F
12A
F525
3550
10u 16
2539
GNDV
I508 3545
6504
5STBY
2534
9
P50
GNDV
1K
3546
GNDV
GNDV
8
10A
11A
2540
GNDV
I520
7
GNDV
F515
1n
100n
7510
BC847BW
I505
I510
I511
I513
21 F5421
22 F5422
D_B
GNDV
6
9A
BZM55-C6V8
GNDV
10u 16
2535
V
3530
100K
3529
6507
5STBY
68R
FMN
5
8A
F524
BZM55-C6V8
10n
2551
P50
I524 3536
2527
3543
1u
2549
1u
1u
2538
1u
2537
D_G
GNDV
D_R
D_C
GNDV
GNDV
D_Y
GNDV
D_CVBS
GNDV
GNDV
GNDV
A_YCVBS
A_C
A_G
GNDV
A_B
GNDV
4
ALIN
7A
GOUT
BC817-25W(COL) I551
GNDV
7511
I552
3544
2550
GNDA
GNDV
from / to Digital Board
6A
GNDV
F536
8SC1
GNDV
20 F5420
19
GNDV
18 F5418
16 F5416
15
17
GNDV
GNDV
14 F5414
13
12 F5412
11
10 F5410
9 F5409
8
7 F5407
6
5 F5405
4
3 F5403
2 F5402
1 F5401
GNDV GNDVGNDV GNDV
1954
A_R
from YUV _CON
from YUV _CON
A_R
A_B
from YUV _CON
A_G
CFIN
to IO2
YFIN
to IO2
YFIN
CFIN
GNDV
8SW
GNDV
AFCLI
CVBSFIN
1
GNDV
F5309
9
8
F5306
F5307
7
6
F5304
5
4
F5303
3
F5301
1
2
GNDA
from Front A/V Board
delete for HDR
GNDV
GNDV
GNDV
1953
PH-B
AFCRI
I
GNDV
GNDV
E
GNDA
F521
68R
GNDA
ALOUT
4A
GNDA
F519
68R
I554 3548 I506
4401
BZM55-C6V8
470p
2545
3519
100K
GNDV
7508
BC847BW
3A
5A
GNDV
3537
I553
GNDV
not used
8SW
10u 16
10u 16
2533
2532
V
3508
470p
2547
1K
3514
100K
3515
3526
100K
2523
7509
BC847BW
AROUT
2A
ARIN
GNDV
68R
4400
not used
D
1A
F518
6503
470R
BC817-25W(COL)
7515
I555
GNDA
GNDA
I587
1u
2524
1u
V
SCART 1
F516
BZM55-C6V8
3535
5STBY
100R
2525
V
BZM55-C6V8
I550
100n
2529
I537
I535
I534
I536
I533
2536
100n
3523
GNDA
2530
2531
3562
100R
GNDA
6502
100n
50 I549
3532
470R
5STBY
4K7
G
3520
F513
GNDA
GNDV
1u 10
BZM55-C6V8
I548
I543
47K
470R
2518
I542
3533
100n
I556
1u
GNDA
GNDA
50
6501
GNDA
I540
I538
I557
I532
3542
3531
51
470R
470R I531
I530
100n
3541
2526
GNDV
2514
I539
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
2528
I547
54
49
V
F517
BZM55-C15
LIN-VCR
100R
4u7
470R
52
3517
I541
1u
BIN-AUX
YCVBSIN-VCR
3528
I586
GNDA
2515
1K
VREF
C
3563
1950-1
GNDA
55
53
CVBS
6 YKC21-4157
1952-C
GNDV
7505
BC817-25W(COL)
7506
BC817-25W(COL)
4K7
5
I582
I584
KIL
3538
YCVBSIN-TV
GIN-AUX
56
3522
82R
GNDV1
57
3516
GNDA
470R
3527 I504
GNDV
LIN-TV
25
58
3540
CIN-TV
RCIN-AUX
59
1K
SLB-VCR
8STBY
H
GNDA
GNDV
4K7
47u
3539
VCCA
60
4K7
YIN-AUX
SLB-AUX
100n
2507
I568
RCOUT-TV
LOUT-TV
YCVBSOUT-TV
RIN-TV
F
1u
8 YKC21-4159
1951-C
3511
50
470p
P50
2502
50
4u7
2548
KIR
from AIO1
P50
from AIO1
YCVBSIN_SC1
to FOME
from DAC
from DAC
ARDAC
2K7
3501
I569
I571
I570
LOUT-AUX
COUT-VCR
ROUT-AUX
I574
YCVBSOUT-VCR
AOUT-RF
VOUT-RF
GNDV3
I572
I573
100n
2506
VCCV3
FILTER
COUT-AUX
GNDV2
SLB-TV
1u
YCVBSIN
from IO2
CIN
from IO2
A
2nd REAR_OUT
470R
3518 I583
I544 GNDA
2510
10K
3568
32
AR
F511
3513
75R
KIR
50
I585
61
3567
I529
GNDA
I545
I509
2509
25
62
100n
2522
31
YCVBSIN-AUX
63
10
I528
1u
9
B
GNDV
4u7
100u
29
30
LOUT-CINCH
I546
2521
I527
GNDV
1u
2519
28
ROUT-TV
64
2520
I526
AL
GNDA
100n
7504
BC847BW
I502
GNDA
47u
CIN-VCR
27
2517
VFV
from TU
3512
2508
GOUT-TV
RIN-VCR
GNDV
1
ROUT-CINCH
BIN-ENC
26
2
VCC12
LIN-ENC
I525
GNDV
3
SDA
GIN-ENC
25
GNDV
4
BOUT-TV
RIN-ENC
24
5
ROUT-VCR
RCIN-ENC
I516
100n
2513
47p
2512
47p
2511
23
6
SCL
LIN-STB
22
100R
7
ADD
CIN-ENC
I515
3525
1u
GNDA
GNDA
GNDA
LOUT-VCR
RIN-STB
21
8
FBIN-ENC
RIN-AUX
20
FBIN-AUX
YCVBSIN-ENC
I514
GNDV
19
2516
I575
I576
100n
18
GNDV
E
YCVBSOUT-AUX
1K
FBOUT-TV
LIN-AUX
17
CVBSIN-STB
100R
3521
I518
7
100R
7503
BC817-25W(COL)
4K7
100R
GNDV
GNDV
7507
STV6410A 16 15 14 13 12 11 10 9
BAS385
2544
100K
3570
3524 GNDV
3565
I503
GNDV
VCCV2
6509
16_SC2
to AIO1
SCL
from AIO1
SDA
from AIO1
100n
2505
12STBY
I517
470R
3510 I501
GNDA
F510
GNDA
I581
8STBY
3K3
3561
3560
470K
GNDV
GNDV GNDV
D
8STBY
5NSTBY
3K9
100n
3559
2541
GNDV
C
3509
GNDV
22K
WU
to AIO1
7502
BC817-25W(COL)
2504
8STBY
3558
I558
F509
3564
100R
I560
I559
7517
BC857BW
2nd REAR_OUT
I580
BZM55-C6V8
2542
100n
I/O 1
not used
5STBY
YIN-ENC
I563
7514
BC857BW
14
GNDV
BC847BW 47K
VCCV1
B
13
GNDA
GNDV
KIR
47K
3557
7516
GNDV
2503
3556
I561
12
4K7
COUT_SC2
5STBY
YCVBSIN_SC1
5STBY
YCVBSIN_SC2
GNDV
5STBY
11
7501
BC857BW
2K2
GNDV
I566
2K2
3504
12STBY
2K7
3500
5STBY
8SW
10
470R
3507 I500
4u7
I564
BC857BW
7500
8STBY
9
3502
A
5NSTBY
100n
GNDV
ALDAC
GNDV
ARADC
to ADC, AIO1
100n
5STBY
2501
2500
8
ALADC
to ADC, AIO1
5STBY
7
3506
A_YCVBS
BIN_SC2
GIN_SC2
RCIN_SC2
from PS
from PS
from PS
from PS
from PS
to YUV_CON
6
3505
In / Out 1
5
220R
4
3503
3
220R
2
to AIO1, VPS
1
13
14
1950-1 E14
1950-3 H14
1951-C A14
1952-C C14
1953 I1
1954 I3
2500 A5
2501 A6
2502 A8
2503 B8
2504 B13
2505 C4
2506 C5
2507 C9
2508 C11
2509 C11
2510 D11
2511 E2
2512 E2
2513 E3
2514 E9
2515 E12
2516 E2
2517 E2
2518 E9
2519 E2
2520 F7
2521 F8
2522 F2
2523 F9
2524 H5
2525 H2
2526 F4
2527 F12
2528 G2
2529 G6
2530 G2
2531 G2
2532 H1
2533 H1
2534 H12
2535 H7
2536 G6
2537 G6
2538 G6
2539 H7
2540 I14
2541 C1
2542 B3
2544 D2
2545 D13
2546 D14
2547 A13
2548 B13
2549 G7
2550 G9
2551 G10
3500 A5
3501 A6
3502 A11
3503 A5
3504 A6
3505 A6
3506 A7
3507 A12
3508 A13
3509 A11
3510 A12
3511 B14
3512 B12
3513 B13
3514 C13
3515 C12
3516 C13
3517 C14
3518 C12
3519 D12
3520 D14
3521 D3
3522 D12
3523 D14
3524 D2
3525 D2
3526 D11
3527 D12
3528 E9
3529 E13
3530 E13
3531 E8
3532 E11
3533 F12
3534 F11
3535 F9
3536 F12
3537 F10
3538 F12
3539 F9
3540 F10
3541 G5
3542 G5
3543 G11
3544 G9
3545 G13
3546 G12
3547 I12
3548 H11
3549 H12
3550 H12
3551 H11
3552 H13
3553 I12
3554 I14
3555 H14
3556 B4
3557 B4
3558 C2
3559 C2
3560 B2
3561 B3
3562 D13
3563 C14
3564 A13
3565 A13
3567 F8
3568 F8
3570 D2
4400 H3
4401 H3
6500 C13
6501 F12
6502 F13
6503 F13
6504 G13
6505 H14
6506 H13
6507 E12
6508 I13
6509 D2
7500 A5
7501 A7
7502 A12
7503 B12
7504 B13
7505 D13
7506 D12
7507 C4
7508 F12
7509 F9
7510 G12
7511 F10
7512 H12
7513 H12
7514 B2
7515 F9
7516 B3
7517 B2
C570 I13
F509 A13
F510 A13
F511 B14
F513 E14
F515 F14
F516 E14
F517 E14
F518 E14
F519 E13
F521 F14
F524 F13
F525 G14
F527 G14
F530 H13
F5301 I1
F5303 I1
F5304 I1
F5306 I1
F5307 I1
F5309 I2
F531 G13
F534 I13
F536 E14
F5401 I3
F5402 I3
F5403 I3
F5405 I4
F5407 I4
F5409 I4
F5410 I4
F5412 I5
F5414 I5
F5416 I5
F5418 I6
F5420 I6
F5421 I6
F5422 I6
I500 A12
I501 A12
I502 B12
I503 C13
I504 D12
I505 G11
I506 H11
I507 H11
I508 G13
I509 C12
I510 H7
I511 H7
I512 I7
I513 I7
I514 D4
I515 D4
I516 E4
I517 D2
I518 D3
I520 I11
I521 H13
I522 H12
I523 F11
I524 F12
I525 E4
I526 E4
I527 E4
I528 F4
I529 F4
I530 F5
I531 F5
I532 F5
I533 G6
I534 G6
I535 G6
I536 G6
I537 G6
I538 F6
I539 E7
I540 E7
I541 E9
I542 E9
I543 E11
I544 D11
I545 D9
I546 D9
I547 E7
I548 E7
I549 F7
I550 F7
I551 F10
I552 G10
I553 F10
I554 H11
I555 G8
I556 F8
I557 F6
I558 C1
I559 B2
I560 B3
I561 B3
I563 B2
I564 A6
I566 A6
I568 C6
I569 C6
I570 C6
I571 C6
I572 C6
I573 C6
I574 C6
I575 C5
I576 C4
I580 A12
I581 A12
I582 C13
I583 C13
I584 D12
I585 D7
I586 E7
I587 F9
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 112
Analog Board: In / Out 2
4
5
6
IS2
from AIO1
10n
5SW
8
5SW
5SW
1B
3B
4B
F5503
3403
F5504
3404
100R
I404
2400
10n
1 IN1
GND 8
2 CTLA
OUT 7
6402
DF3A6.8FU
GNDV
100n
75R
3406
2401
75R
3405
GNDV
6403
DF3A6.8FU
5SW
7400
BA7652AF
100R
2B
B
I402
10u
5400
3419
100K
3418
100K
GNDV
Y
C
10
A
1955-B
TCX0310
Y/C IN
9
100K
A
3402
REAR_IN
S-CONN
GNDV
2410
7
5SW
from PS
3
IS1
from AIO1
2
WSRI
to AIO1
1
3 IN2
B
I417
YCVBSIN
to IO1
VCC 6
REAR_IN
100R
2404
I406
GNDV
C
GNDV
GNDV
10n
6405
DF3A6.8FU
4
47u
I416
2403
IN3 5
2405
YFIN
from IO1
10n
75R
YKC21-4158
1959-A
I407
3407
F5202
CVBS
4 CTLB
GNDV
2
3408
C
GNDV
100n
GNDV
GNDV
2402
LOGIC
5SW
2
D
GNDV
4
YKC21-4157
1952-A
GNDV
D
7401
BA7652AF
GNDV
not used
5SW
GND 8
2 CTLA
OUT 7
I410
3 IN2
VCC 6
1n
5SW
E
LOGIC
I412
1
GNDV
2408
GNDV
1
2
3
10n
4
5
6
7
8
9
GNDV
2411
GNDV
WSFI
to AIO1
GNDA
ARCRI
to AP
GNDA
3414
100K
V
GNDA
CFIN
from IO1
1n
ARCLI
to AP
not used
3417
F
2
3416
YKC21-4159
1951-A
CTLA CTLB OUT
IN1
L
L
H
L
IN2
L
H
IN3
MUTE
H
H
10K
3
3415
IN3 5
4 CTLB
100K
GNDA
I411
10K
GNDA
CIN
to IO1
3413
GNDA
10K
YKC21-3620
1958-A
2406
I414
100n
I409
2
GNDV
2407
100K
3411
3
V
F5103
10K
3409
1
3412
E
1 IN1
F5101
3410
REAR_IN
AL /
MONO
AR
CL 26532011_002.eps
150102
10
F
1951-A F1
1952-A D1
1955-B A1
1958-A E1
1959-A C1
2400 B5
2401 B2
2402 C9
2403 C9
2404 C4
2405 C9
2406 E4
2407 E8
2408 E9
2410 A4
2411 F10
3402 A3
3403 B4
3404 B4
3405 B2
3406 B2
3407 C3
3408 C2
3409 E5
3410 E2
3411 E2
3412 E5
3413 E9
3414 F9
3415 F9
3416 F2
3417 F2
3418 A5
3419 A6
5400 A8
6402 B4
6403 B3
6405 C2
7400 B6
7401 D6
F5101 D2
F5103 E2
F5202 C2
F5503 B2
F5504 B2
I402 B5
I404 B5
I406 C5
I407 C4
I409 E4
I410 E5
I411 E8
I412 E8
I414 E9
I416 C8
I417 B10
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 113
Analog Board: In / Out 3
2
In / Out 3
3
4
5SWS
5SW
5
6
7
8
9
REAR_OUT I/O 3
5SW
1955-A
TCX0310
I432
3423
100n
82K
D_C
from IO1
10u
5430
6dB
I436
OB2 12
6dB
8 GND3
100K
3435
2440
22u
100u
2441 I439
I440
1955-C
TCX0310
5
2438
100n
GNDV
1
3 YKC21-4158
1959-B
F336
3436
GNDV
6432
CVBS
GNDV
8STBY
5SW
5SW
2
I450
47K
1K5
F9203
3448
10R
10R
not used
5
2
4
I453
3447 I449
F9202
3454
I451 3444
6437
BAV99W
SATCONTROL
BC327-40
7432
8
2450
5NSTBY
100n
GNDA
F340 1
7434-B
MC33078 GNDA
7
2K2
7431
BC817-25W(COL)
4K7
1
2
3
GNDA
7
5NSTBY
F331
4
AL
F334
5
AR
4
KIR
6
from AIO1
from AIO1
KIL
GNDA
DF3A6.8FU
470p
7433
BC817-25W(COL)
2447
3451 I457
GNDA
100R
I456
6440
470R
3450
from DAC
from DAC
ALDAC
ARDAC
5
3446
4
AL
6
AR
5
GNDA
GNDA
YKC21-4159
1951-B
not used
GNDA
GNDA
CL 16532095_014.eps
080801
7
8
E
6 YKC21-3620
1958-B
GNDA
GNDA
3445
4K7
from AIO1
BZM55-C6V8
4904
delete for HDR
GNDD
GNDD
I446
10u
SATCO
GNDD
2443
to AIO1
GNDD
GNDA
1K
NC
6
GNDA
RC
for RC only
6438
YKC21-3478
1991
1n
3
2445
2
RC IN
I459
100K
3453
6439
3441
3442 I455
470p
GNDD
VCC_HA
5
D
3440
100R
470R
10u
for SATCONTROL only
I454
3439
DF3A6.8FU
I445
2446
2442
HPL
4
EH-B
100K
3452
100u
2444
5NSTBY
F330
I458
5STBY
1
GNDD
F341 3
4406
GNDA
HPR
GNDA
8STBY
4
1956
2
4405
6
3
1992
YKB21-5130 GNDD
GNDV
GNDV
7434-A GNDA
8
MC33078
1
3
6436
BAV99W
GNDD
3 YKC21-4157
1952-B not used
100n
I452
C
1
DF3A6.8FU
F
B
from AIO1
2449
E
7
WSRO
GNDV
D
6
GNDV
DF3A6.8FU
6431 GNDV
75R
C
A
S_CONN
68R
GNDV
I438
OC2 9
3433
22u
not used
OC1 10
75E
10n
47u
2436
22u
7 INC
Y
C
DF3A6.8FU
6430 GNDV
GNDV
100u
2448
I437
NC2
1
2432
2431
I435
OB1 13
75E
5 GND2
6 NC1
470K
GNDV
2437
4 INB
4A
GNDV
I441
OA2 14
F337
4K7
5SWS
3 GND1
75R
GNDV
GNDV
2434
3431
GNDV
82K
I431
3424
82K
from IO1
GNDV
22u
OA1 15
75E
3A
10n
D_CVBS
3437
B
GNDV
2439
3434
5SWS
22u
3425
from IO1
6dB
F338
2A
2430
D_Y
2 INA
I433
I434
3438
I430
VCC 16
3432
100K
2433
470K
from AIO1
4404
1 MUTE
VMUTE
1A
not used
3455
100K
5SW
5STBY2 5STBY
7430
BA7660FS
470K
5SWS
3426
5SW
from PS
A
5STBY
from PS
5STBY2
from AIO2
GNDV
to headphone
1
9
F
1951-B F9
1952-B C9
1955-A A9
1955-C B9
1956 D9
1958-B E9
1959-B C9
1991 F1
1992 E1
2430 B6
2431 A4
2432 A5
2433 A1
2434 A4
2436 B5
2437 C1
2438 C5
2439 B1
2440 B4
2441 B5
2442 E5
2443 F5
2444 E3
2445 F2
2446 E7
2447 F8
2448 B4
2449 C7
2450 D7
3423 C1
3424 B1
3425 B1
3426 A1
3431 B6
3432 A7
3433 B7
3434 B1
3435 A6
3436 C7
3437 B1
3438 B5
3439 E6
3440 E8
3441 E5
3442 E6
3444 D3
3445 F6
3446 F8
3447 D2
3448 D2
3450 F5
3451 F6
3452 E4
3453 E3
3454 D3
3455 A2
4404 A4
4405 D9
4406 D9
4904 F4
5430 A4
6430 A8
6431 B8
6432 C8
6436 D4
6437 D1
6438 F2
6439 E8
6440 F8
7430 A2
7431 E7
7432 D3
7433 F7
7434-A D7
7434-B D8
F330 E2
F331 E9
F334 E9
F336 C9
F337 A9
F338 A9
F340 D9
F341 D9
F9202 D2
F9203 D2
I430 A2
I431 B2
I432 C2
I433 A4
I434 A4
I435 B4
I436 B4
I437 B4
I438 C4
I439 B5
I440 B6
I441 B5
I445 E6
I446 F6
I449 D2
I450 D3
I451 D3
I452 D3
I453 D4
I454 E7
I455 E6
I456 F7
I457 F7
I458 D9
I459 E3
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 114
Analog Board: In / Out 4
5
I479
3460
GNDA
4u7
GNDA
3466
I480
100R
I473
3467
7461
BC817-25W(COL)
3470
100K
GNDA
GNDV
10B
F5011
D
11B
GNDV
6462
12B
13B
GNDV
14B
GNDV
GNDV
F5015
15B
16B
4
5
GNDV
BZM55-C6V8
6463
6465
75R
75R
3481
F5021
6
7
21B
GNDV
GNDV
F
GNDV
YCVBSIN_SC2
to IO1
YCVBSOUT_SC2
from IO1
FBIN_SC2
to IO1, AIO1
RCIN_SC2
to IO1
GIN_SC2
to IO1
8_SC2
to IO1
BIN_SC2
to IO1
SC2RGB_H
from AIO1
3
DF3A6.8FU
6466
GNDV
GNDV
GNDV
20B
YCVBSIN
3483
68R
F
YCVBSOUT
I476 3484
GNDV
I478
E
19B
F5020
GNDV
150R
7464
BC847BW
GNDV
GNDV
18B
F5019
I471 3486
3482 I477
GNDV
GNDV
FBIN
17B
GNDV
BZM55-C6V8
1u
2469
MCL4148
6468
GNDV
BZM55-C6V8
6464
75R
2465
390R
3457
GNDV
3485
1K
BC_KILL_DC
to IO1
8SC2
9B
GNDV
F5010
not used
BIN/COUT
RCIN
GNDV 100n
2
4403
8B
F5016
100R
COUT_SC2
from IO1
75R
GNDV
3480
2466
GNDA
7463
BC817-25W(COL)
1K5
3458
3478
GNDV
5STBY
GNDV
7B
GIN
I483
1
GNDV
ALIN
10n
4K7
5NSTBY
C
6B
F5007
BZM55-C6V8
I460
ALOUT
4B
5B
GNDA
P50
to I/O 1
not used
3479
ARIN
GNDA
GNDA
BZM55-C15
6461
47K
3477
470R
AROUT
3B
F5008
GNDA
I482
2B
F5004
3474
BZM55-C6V8
3476
1K
1%
6460
68R
GNDV
GNDV
GNDA F5006
F5003
3473
I461
4K7
10K
3459
3475
7466
BC817-25W(COL)
E
GNDA
GNDV
I463
3489
GNDA
50
7462
BC847BW
470R
D
GNDA
1B
F5002
GNDV
I462
I481
2463
4u7
82R
3472
100n
2464
I465
1950-2
F5001
3471
5STBY
SCART 2
100K
3469
4K7
470p
25
2468
470R
47u
B
GNDA
3488
V
I474
3468
2462
3465
3464
100K
50
B
GNDA
GNDA
V
GNDA
V
2461
100K
3463
I469
A
V
7460
BC817-25W(COL)
3462
I472
3461
470p
100R
2467
25
5NSTBY
C
9
3487
470R
47u
5NSTBY
from PS
5STBY
from PS
I464
4K7
5STBY
8
I/O 4
2460
A
7
6
AROUT_SC2
from IO1
KIR
from AIO1
ARIN_SC2
to IO1
ALIN_SC2
In / Out 4
4
ALOUT_SC2
from IO1
3
KIL
from AIO1
2
to IO1
1
CL 16532095_015.eps
080801
8
9
1950-2 C9
2460 A5
2461 B5
2462 B5
2463 C5
2464 C2
2465 E6
2466 E2
2467 A7
2468 B7
2469 E2
3457 E6
3458 E2
3459 D1
3460 A6
3461 A6
3462 A8
3463 A5
3464 B7
3465 B8
3466 B6
3467 B6
3468 B8
3469 C5
3470 C6
3471 C8
3472 C1
3473 D3
3474 D5
3475 D2
3476 D3
3477 D5
3478 D7
3479 E2
3480 E6
3481 E7
3482 F5
3483 F7
3484 F8
3485 F6
3486 F8
3487 A8
3488 B8
3489 D1
4403 D8
6460 D3
6461 D5
6462 D8
6463 E7
6464 E7
6465 F7
6466 F9
6468 E1
7460 A7
7461 B7
7462 C2
7463 E3
7464 F6
7466 D1
F5001 C9
F5002 C9
F5003 C9
F5004 C9
F5006 C8
F5007 D9
F5008 D9
F5010 D9
F5011 D9
F5015 E9
F5016 E9
F5019 E9
F5020 E9
F5021 F9
I460 D2
I461 D3
I462 C1
I463 D2
I464 A6
I465 C5
I469 A5
I471 F8
I472 A7
I473 B7
I474 B6
I476 F8
I477 E5
I478 F6
I479 A7
I480 B7
I481 D1
I482 D2
I483 E2
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 115
Analog Board: Sound Processing
1
2
3
4
5
6
7
8
9
Sound Processing
AP
8SW
GNDA
GNDD
100n
2603
10u
RESETQ
17 I2S_DA_IN1
22
10n
I620
56p
2609
I619
SIF1
S1...4
FM1
FM2
NICAM A
NICAM B
3 ANA_INDEMODULATOR
2 ANA_IN+
I2SL/R
I2SL/R
DACM_R
D/A
LOUDSPEAKER R
2608
GNDA
C
I622
B
GNDD
I606
21 I2S_DA_IN2
2607
4K7
3602
10n
10u
I605
6600
19
26
10u
16 I2S_DA_OUT
DVSUP
MCL4148
7600
MSP3415G
11
2606
GNDD
STBYQ
15 I2S_WS
2604
5600
34
10u
2602
10u
10n
33
CAPL_M
QFP44
14 I2S_CL
B
10K
2605
100R
42
AHVSUP
13 I2C_DA
3603
4
9
VREFTOP
I623
D_CTR_IO1
12 I2C_CL
100R
8
ADR_SEL
I624
ADR_CL
3601
A
3600
GNDA
18 10
SCL1
I604
I603
GNDD
TESTEN
5SW
I601
D_CTR_IO0
8SW
2601
C670
GNDA
2600
4601
I600
8SW
5SW
A
SDA1
I602
5SW
GNDD
LOUDSPEAKER
DACM_L
LOUDSPEAKER L
27
D/A
GNDD
56p
C
2610
2u2
EH-B
3606
41 SC1_IN_R
1K
3607
40 SC1_IN_L
A/D
SCART-R
HEADPHONE L
38 SC2_IN_R
31
29
35
39
GNDA
DVSS
44
NC
23 24 28 32
20
GNDD
1
5
7
I611
25
AVSS
1K
ASG
3605
AHVSS
SCART Switching Facilities
ARCLI
2u2
SC1_OUT_L
5SW
10u
2622
GNDA
2
3
AFEL
4
5
E
GNDA
GNDA
6
1600
I609
HC-49/U
18M432
F
10n
10u
100u
2623
F
2620
5601 I613 5602 I612
1
AFER
D/A
37 SC2_IN_L
1K
VREF1
2615 I615
SCART-L
VREF2
2u2
E
30
2616
ARCRI
I614
SC1_OUT_R
D/A
AVSUP
3604
I617
D
GNDA
SCART-R
1K
2614 I616
4u7
1n
2625
HEADPHONE R
2617
DVAL
F6004
SCART-L
2612
I607
3p3
4
A/D
2621
3
GND
2u2
36
XTAL_OUT
F6002
AGNDC
XTAL_IN
2
2624
3p3
F6001
10n
DFP
TP
GND
1
GNDA
D
from DV - Board
DVAR
IDENT
1n
IDENT
43 MONO_IN
1960
GNDD
GNDA
6
CL 16532095_016.eps
080801
GNDD
7
8
9
1600 F7
1960 D1
2600 A6
2601 A6
2602 A7
2603 A7
2604 A9
2605 B8
2606 B8
2607 C2
2608 C9
2609 C2
2610 C8
2612 D8
2614 E1
2615 E1
2616 E8
2617 E8
2620 F7
2621 F7
2622 F5
2623 F6
2624 D2
2625 D2
3600 A8
3601 B1
3602 B9
3603 B2
3604 E2
3605 E2
3606 D2
3607 D2
4601 A5
5600 A8
5601 F5
5602 F6
6600 B9
7600 B6
C670 A3
F6001 D1
F6002 D1
F6004 D1
I600 A4
I601 A6
I602 A7
I603 A7
I604 A8
I605 B7
I606 B7
I607 D8
I609 F7
I611 F7
I612 F6
I613 F5
I614 E2
I615 E2
I616 E2
I617 E2
I619 C2
I620 C1
I622 C2
I623 B2
I624 B2
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 116
Analog Board: Follow Me
Analog Board: VPS
2
I951 B2
I952 B2
I953 C2
I954 C3
7950 D4
7951 B2
7952 B3
F950 A3
I963 E1
3994 E1
3995 E3
5990 A4
5991 A3
7990 B1
I987 E3
2
GNDV
5SW
5SW
5
1 CVBS
6
2
4
33K
DISPLAY
3993 I988 16 SCL
3994 I989 17 SDA
47u
2991
100n
2990
CTRL
Data
Address
R 8
D
G9
INTERFACE
I2C BUS
B 10
INTERFACE
100R
E
BLAN 12
CTRL
TIME BASE
Address
GNDV
SDA1
GNDV
25 VSSO
100R
GNDV
GNDV
3966
I961
SCL1
7
E
GNDV
26
GNDV
11
Y 15
14
13
E
3995
10K
GNDV
1
VFV
YCVBSIN_SC1
I963
CL 16532095_018.eps
080801
CL 16532095_017.eps
080801
2
3
4
1
C
FREQUENCY
33K
3964
3963
180p
2957
D
I999
TEST2
MEMORY
SYNTHETIZER
I998
47K
27
8 PAGES
OSCILLATOR
23 XTO
47K
I992 3991
COR_
GNDV
8
GNDV
9
2955
10M
1u
33K
2956
I959
3960
33K
3962
3965
I960
2n2
GNDV
E
33K
180p
I958
33K
10M
GNDV
2954
2953
24 XTI
TEST1
20
3990
1u
I957
3961
5SW
2n2
3959
4
GNDV
2952
5SW
I956
5
11
10
D
21 VCR_|TV
RGBREF
2996
22p
D
DATA EXTRACTION
I987
22p
HC-49/U
13M875
7950-C
LM339D
7950-A
LM339D
DV_ 19 I991
DATA
PROCESSING
ODD_|EVEN
2995
GNDV
7950-D
LM339D
I997
14
2
13
3958
4K7
DATA DECODING
SYNCHRONIZING
Data
GNDV
1990
I955
I990
Data
VSSD
2K2
3
100n
C
B
22
Clock
VSSA
C
28 CBLK
I996
I954
4K7
3955 I962
5SW
5SW
2994 I995
100n
18
CLAMPING
GNDV
VDDA
3992
7990
STV5348
I993
B
GNDV
GNDV
L23
B
2992
GNDV
GNDV
MA_|SL
10u
FFB
GNDV
BC847BW
7951
7952
BC847BW
2951
2993
15K
GNDV
VDDD
GNDV
6
3953
I952
I953
10u
5990
A
5SW
47K
12
A
I994
2K2
4
5SW
22K
3957
I997 C1
I998 D1
I999 D1
I994 B1
I995 C1
I996 C1
3
GNDV
3954
3956
I991 C4
I992 C4
I993 B2
5991
I951
3952
C
I988 D1
I989 D1
I990 B4
VPS
A
100K
3951
1
7
3
5SW
7950-B
LM339D
4K7
3991 C4
3992 B2
3993 D1
FOME
4K7
B
2995 C1
2996 D1
3990 C4
1
4
3950
A
2992 A3
2993 B1
2994 C1
1990 D1
2990 A4
2991 A4
F950
GNDV
100n
I959 D3
I960 E1
I961 E3
I962 C2
STTV
Follow Me
2950
I955 C1
I956 D1
I957 D1
I958 D3
3
FOME
1
3966 E4
7950 A2
7950 D2
7950 D2
3962 E2
3963 E3
3964 E3
3965 E2
POL
3958 C3
3959 D1
3960 D3
3961 E1
3954 B1
3955 C2
3956 C1
3957 C1
A_YCVBS
3950 A1
3951 A3
3952 B1
3953 B3
100n
2954 D2
2955 D4
2956 E1
2957 E3
5SW
2950 A1
2951 B3
2952 D2
2953 D4
2
3
4
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 117
Analog Board: Power Supply
1
2
3
4
6
5
7
8
9
PS
5M
Power Supply
12STBY
A
A
1
8STBY
GNDA
GNDA
GNDA
100u
2325
2
not used
OUT
100n
2331
GND
330n
2324
47u
GNDA
GNDA
220K
3321
3338
3339
220K
5STBY
I340
100u
7324
PDTC124EU
GNDA
GNDA
I341
GNDA
7330
7331
BC847BW
BC847BW
1324
2
3
4
5NSTBY
to AIO1, DAC_ADC,YUV,
IO1, IO3, IO4
to AIO1
VGNSTBY
to TU
33STBY
to AIO1
IPFAIL
F
FLYB
E
5
not used
5STBY
5.2V / 0V
7322
BC847BW
I326
0V / 5.3V
10K
3336
47R
I325 3322
GNDA
GNDA
to DAC_ADC,AIO1
GNDA
F9333
5STBY
470n
2329
3340
220K
GNDA
F9332
1A
PSC
5SW
1
100u
D
12.3V / 0V
F9330
E
2328
GNDA
I339
D
GNDA
F9341
10K
F3207
3326
7
100K
F3206
220K
6
100n
F3205
C
F9342
5SW
500mA
PSC
3337
5
1325
F9338
F9347
47n
4
F3204
2SK2839
2322
3
F9343
5.3V / 0V
3325
GNDA
F3202
F3203
2323
FLYB
100n
2SK2839
2321
7321
33STBY
2
7323
VGNSTBY
17.9V / 0V
250mA
5NSTBY
F9346
not used
12V
F3201
1996
1
5V
GNDA
I324
1932
4320
C
2332
33STBY
1A
PSC
1326
8SW
220K
EH-B
B
F9336
500mA
PSC
1327
2330
not used
delete for HDR
B
I345
3
IN
F9345
F9340
F9344
7332
I337 0V / 5.3V
3323
10K
I338
7329
BC847BW
GNDA
3335
ISTBY
4K7
GNDA
CL 16532095_019.eps
080801
6
7
8
9
F
1324 E8
1325 C8
1326 B2
1327 B2
1932 C1
1996 D4
2321 C6
2322 D6
2323 D6
2324 B3
2325 B4
2328 C8
2329 E2
2330 B3
2331 B4
2332 B8
3321 C7
3322 E6
3323 F6
3325 D6
3326 D7
3335 F9
3336 F8
3337 D6
3338 D3
3339 D2
3340 E2
4320 D4
7321 C5
7322 F6
7323 D5
7324 D7
7329 F8
7330 E2
7331 E3
7332 A4
F3201 C1
F3202 C1
F3203 C1
F3204 C1
F3205 C1
F3206 D1
F3207 D1
F9330 E8
F9332 E9
F9333 E9
F9336 B6
F9338 C8
F9340 B2
F9341 C9
F9342 C9
F9343 C8
F9344 A3
F9345 B3
F9346 C2
F9347 C2
I324 C6
I325 F6
I326 F6
I337 F8
I338 F8
I339 D6
I340 E2
I341 D3
I345 A4
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 118
Analog Board: Audio Converter
22n
I034
11 WS
F014
I035
12 DI12
13 DI34
14 DI56
22R
F0005
F0003
7005
LF33CV
IN
D
7
GNDD
6
A_DAT
5
GNDD
4
2027
OUT
22R
GNDA GNDA
GNDA
1R5
3010
5K1
GNDA
1R5
GNDA
I011
4K7
3V3DD
4K7
3V3DD
1
2
1R5
1R5
3019
GNDD
1%
D
8STBY
1%
GNDA
I027
100n
VREF 2
47u
ADC
2012
1 VINL
8
4
I018
12 WS
GNDA
DC-CANCEL
FILTER
DIGITAL DATAO 13
INTERFACE
6 SFOR
VSSD VSSA
10
15
I023
100n
GNDA
GNDA
GNDA
5NSTBY
3032
3022
I014
5K1
47u
11 BCK
1%
F
2018
220p
I020
3
GNDD
GNDA
GNDD GNDA
GNDA
CL 16532095_020.eps
080801
4
E
2014
100n
2017
I019
ADC
ALDAC
to IO1, IO3
6
I022
3 VINR
GNDA
7002-B
MC33078
F011
7
GNDA
VREFP 5
VREFN 4
2011
47K
CLOCK
CONTROL
4R7
2016
47p
3018
47K
3023
47p
I016
7 PWON
47p
GNDD
16
9 100n
VDDA VDDD
3028
1n
GNDD
I026
2019
DECIMATION
FILTER
not used
1%
3013
F
12K
2007
3012
I013
100n
8 SYSCLK
3024
I017
3021
1%
5
1%
not used 2021
47u
3020
12K
I039
7004 GNDA
UDA1360TS
14 FSEL
not used 2020
ARADC
from IO1
47u
2015
I038
I037
3029
GNDA
3011
I012
2009
I015
8STBY
3009
not used
3V3DD
GNDD
GNDD
22R
ALADC
from IO1
22R
22R
GNDA
2013
2001
5001
1
Bead
E
3015
GNDD
GNDD
F0002
F0001
not used 2022
3
2
1%
3008
A_WCLK
A_BCLK
C
4K7
VREFA
30
I030
GNDD GNDD GNDD
GNDD
3014
1%
3V3DD
220p
GNDA
3016
47p
A_PCMCLK
GND
4K7
ARDAC
to IO1, IO3
2
100n
F0007
VSSA
3
I025
3006
VO4 2
VO6 5
VDDA
6
I029
GNDD
not used2023
8
DAC'S
1%
2010
GNDD
GNDD
4K7
4 VO5
D_BCLK
9
I010
1%
GNDD
F0009
GNDD
10
VO2N 31
7002-A
MC33078
1 F010
3
4K7
F0011
GNDD
GNDD
29 VO1N
I024
3017
F0012
D_WCLK
11
3005
330p
22R
GNDD
2003
12
I009
10u
D_DATA0
3030
2028
13
F0014
100n
GNDD
GNDD
14
VO2P 32
1 VO3
not used 2029
GNDD
15
D_PCMCLK
C
F0016
16
GNDD
2030
17
D_IKILL
28 VO1P
3007
GNDD
B
GNDD
DS 26
2002
10u
3VD
TST2 22
VOL/MUTE/DEEMPH
NC INTERPOL FILTER
15
NOISE SHAPER
2008
5002
L3MODE 17
8
100u
5003
18 F0017 5004
GNDD
7
47p
19
5VD
5NSTBY
L3DATA 19
16 SYSCLK
DAINOPT
8STBY
L3CLK 18
47u
20
GNDD
DEEM0 25
100n
2006
21
DAINCOAX
DEEM1 24
GNDD
3V3DD I036
3003
B
5VDD
Bead
to DIGIO
22
DAOUT
27 TST1
GNDD
5000
10K
3027
1900 FMN
22R
3025
GNDD
I031
MUTE 23
2005
DAOUT
A
10K
F013
DAC_ADC
STATIC 9
3002
2000
GNDD
CONTROL
INTERFACE
I033
9
I032
330p
3V3DD
10K
3004
47p
not used
2026
47p
2025
MCL4148
to DIGIO
GNDD
8
100K
BC857BW
7000
GNDD
20
VSSD
DIGITAL
INTERFACE
from DIGIO
7
3001
7001
UDA1328T 21
VDDD
10 BCK
22n
2004
from DIGIO
DAINCOAX
6
I028
47u
F012
22R
I001
DAINOPT
GNDD
GNDD
GNDD
47p
2024
GNDD
not used
4K7
3026
A
5
3000
6000
IPFAIL
from AIO1
4
5NSTBY
Audio
Converter
3
from PS
2
from PS
1
5
6
7
8
9
1900 B1
2000 A4
2001 E1
2002 C7
2003 C4
2004 C4
2005 D5
2006 D5
2007 D8
2008 D7
2009 D4
2010 E8
2011 E6
2012 E6
2013 E1
2014 E8
2015 F1
2016 F5
2017 F6
2018 F8
2019 E5
2020 F2
2021 F2
2022 E3
2023 D3
2024 A2
2025 A3
2026 A3
2027 D3
2028 D4
2029 C3
2030 C3
3000 A2
3001 A7
3002 A6
3003 B4
3004 A3
3005 B7
3006 C7
3007 C7
3008 C6
3009 C8
3010 C6
3011 D7
3012 D7
3013 F2
3014 D2
3015 E2
3016 D2
3017 D7
3018 E6
3019 E6
3020 E2
3021 F2
3022 F8
3023 E3
3024 E3
3025 B2
3026 A2
3027 B2
3028 F5
3029 C8
3030 C3
3032 F8
5000 B3
5001 E1
5002 B3
5003 B1
5004 B1
6000 A1
7000 A6
7001 A4
7002-A B8
7002-B E8
7004 E4
7005 C3
F0001 E1
F0002 E2
F0003 D2
F0005 D2
F0007 D2
F0009 D2
F0011 C2
F0012 C2
F0014 C2
F0016 C2
F0017 B1
F010 C9
F011 E9
F012 A1
F013 A1
F014 A1
I001 A1
I009 B6
I010 C6
I011 D6
I012 D6
I013 D5
I014 F6
I015 E3
I016 E3
I017 F3
I018 F3
I019 F3
I020 F3
I022 E8
I023 F5
I024 B8
I025 C8
I026 D8
I027 E8
I028 A4
I029 C4
I030 C5
I031 A6
I032 A7
I033 A4
I034 A4
I035 A4
I036 B4
I037 E3
I038 E1
I039 F1
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 119
Analog Board: Digital In / Out
4
I496 100n
5VDD
3204
B
I208
3205
not used for SA7118
15K
3206
2480
10n
3
C
C
DAOUT
from DAC_ADC
3490
4470
7470-A
PC74HCU04D
1
A
Y
I490
2
A
5
I489
2K2
A
A
6
3218
I225
100R
3224
1K5 1%
3222
3220
1K2
4K7 1%
1K
4201
delete for
HDR
Y
to I/O 1
A_B
GNDD
5VDD
GNDD
1
OPTICAL
OUT
VIN
GND
GNDD
not used
5VDD
E
1
1942
GP1FA550RZ
VCC
DAINOPT
to DAC_ADC
1K
F4205
3
OUT
GND
2
GNDD
CL 16532095_021.eps
080801
4
D
VCC
to I/O 1
1%
OPTICAL
IN
CL 16532095_022.eps
080801
1
2
C
5
GNDD
1943
GP1FA550TZ
3
3498
3
GNDD
F488
1941-B
YKC21-3600
2
100R
GNDD
E
12
F4204
3497
DAOUT
from DAC_ADC
A_R
100R
A
3429
560R
4
2
to I/O 1
100R
3225
1K5 1%
I226
3221
2
10
I486
D
A_G
Y` = R - V x 1,402
U = B/2 - 0,169R - 0,331G
V = R/2 - 0,419G - 0,081B
1
D
3223
I224
3219
4202
I216
GNDV
E
4203
7200-B
TSH95
7
2481
750R 1%
1K 1%
4K7 1%
3215
3213
3214
4K7 1%
Y
2470
6
7470-F
PC74HCU04D
1K5 1%
3212
GIN_SC2
from IO1
Y
I492
100n
7470-E
PC74HCU04D
13
I215
4
7470-C
PC74HCU04D
I213
D
Y
1
GNDD
10u
7470-B
PC74HCU04D
3
470R
3495
5
GNDD
2479
4471
GNDD
8
B
1948
YKC21-3416
not used
not used
GNDV
I214
GNDD
GNDD GNDD
11
3211
1
GNDD
47R
I212
6RG
DIGITAL
OUT
2
750R 1%
3210
5K62 1%
6K8 1%
6
3443
2
75R
BZX284-C6V8
3209
150p
100n
I211
3208
3494 F4202 2
2477
3
2473 I487
2484
7200-A
TSH95
1
1K5 1%
Ground not connected
to the rear plane
1945
F4203 3 YKC21-3479
33p
3207
RCIN_SC2
from IO1
1
A
GNDD
100n
750R 1%
I210
GNDD
I497
3496
I209
5VD1
3456
1K 1%
B
4
2
not used
100K
GNDV
GNDV
5470
3
DIGITAL
IN
GNDD
GNDD
I485
not used
DAINCOAX
to DAC_ADC
GNDD
1
5
2474
GNDV
5STBY 5NSTBY
B
10K
7201
PDTC124EU
9
GNDD
3491
YUV_ON
from AIO1
I205
2486
11
I204
100K
12
15K
3203
3202
7200-C
TSH95
10
F4102
1941-A
YKC21-3600
100n
100K
3492
GNDD
3
75R
100R
3493
3427
2471
A
F4103
not used
2485
Vss
BZX284-C6V8
Y
7470-D
PC74HCU04D
14
3428
Vcc
9
GNDD
not used
GNDD
I206
3201
1K 1%
BIN_SC2
from IO1
4
DIGIO
5VD1
7
I203
I207
C
3
330R
3499
GNDV
I495
1u
22K
3200
47u
2203
22n
GNDV
A
8
2483
GNDV
A
5VD1
5VDD
from DAC_ADC
13
750R 1%
5NSTBY
from PS
5STBY
2202
15
GNDV
from PS
7200-D
TSH95
16
4
47u
22n
2201
2200
14
I490 C2
I492 C3
I495 A1
I496 A2
I497 B1
F4204 D3
F4205 E4
F488 D4
I485 A2
I486 D3
I487 B3
I489 C1
Digital In / Out
I202
I201
GNDV
YUV_CON
7470-D A1
7470-E C2
7470-F D2
F4102 A4
F4103 A4
F4202 B4
F4203 A4
4471 C2
5470 B2
6470 A3
6471 C3
7470-A C2
7470-B C2
7470-C C2
3494 B3
3495 C2
3496 C1
3497 D2
3498 E3
3499 A1
4470 C1
2
5VDD
5STBY
A
1
5STBY
5NSTBY
3429 D3
3443 D4
3456 B1
3490 C1
3491 A1
3492 A2
3493 A3
2481 E2
2483 A1
2484 D3
2485 B4
2486 B1
3427 A2
3428 A2
1n
RGB-YUV-Conv.
2471 A3
2472 A3
2473 B3
2474 B3
2477 D3
2479 C3
2480 B1
1941-A A4
1941-B C4
1942 E4
1943 D4
1945 A4
1948 B4
2470 C3
100n
3
I226 E2
I213 D1
I214 D2
I215 D1
I216 D3
I224 E2
I225 E2
not used
6471
2
I207 A1
I208 B3
I209 C2
I210 C2
I211 C1
I212 C2
150p
6470
1
I201 A2
I202 A3
I203 A4
I204 A4
I205 A3
I206 A2
4203 D4
7200-A C3
7200-B D3
7200-C A3
7200-D A2
7201 B4
2472
3222 E2
3223 D4
3224 E4
3225 E4
4201 D4
4202 D4
3214 D2
3215 E2
3218 E1
3219 E2
3220 E3
3221 E1
100K
3208 C1
3209 C1
3210 C2
3211 D1
3212 D1
3213 D1
3202 B2
3203 B2
3204 B3
3205 B3
3206 B3
3207 C1
not used
Analog Board: RGB-YUV-Converter
2200 A1
2201 A1
2202 A3
2203 A3
3200 A4
3201 A1
3
4
E
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 120
Analog Board: Fan Control
3974 F1
3975 F2
3976 F3
3977 A2
3978 B5
3979 B4
3980 D3
3981 F4
3948 D2
3967 A3
3968 A3
3969 A4
3970 E2
3971 E1
3972 C3
3973 F2
2985 B3
3940 C4
3941 D4
3942 B1
3943 C1
3944 C1
3946 B1
3947 B4
1
3982 E3
3983 F3
3984 E5
3985 D1
3986 E1
3987 C4
3988 E1
3989 D5
7970-C E3
7970-D D2
7971 B5
7972 D5
7973 B1
7974 C2
7975 C2
F805 B5
3996 A4
3997 A5
4905 C5
6970 C3
6971 C4
6972 C3
7970-A E4
7970-B B3
2
3
F806 C5
F807 F1
F813 B5
F814 C5
I920 B2
I921 B3
I922 B4
I923 E2
4
5
10R
for SW contr. only
7
7970-B
LM324D
BSH111
C
3980
7970-D
4 LM324D
10K
I928
3940
3941
33K
F814 F806
GNDD
EH-B
7972
BC847BW
I931 3989
22K
delete for
SW contr.
10K
13
1n
2984
3970 I923
12STBY
220K
GNDD GNDD
1
56K
3975
t
not used
3974
GNDA
18K
GNDD
2
39K
15K
TEMP
to AIO1
CL 16532095_023.eps
080801
I924
3
F
3981
GNDD
3976
GNDD
BE_FAN
to AIO1
1K
2
11
9
11
1K
E
7970-A
LM324D
4
1 I930 3984
I933
56K
I926
3973
7970-C
LM324D
8
4
3982
10
3983
33K
27K
3971
3988
3
F
from AIO1
GNDD
GNDD
12STBY
12STBY
F807
D
ION_FAN
from AIO1
SW_BE_FAN
11
TEMP_SENSE
from AIO1
C
MOT
2
GNDD
10n
12
I929
2983
I927
3986
1K
for SW contr. only
GNDD
14
E
3987
470R
3972
3948
delete for SW contr.
5K6
3985
12STBY
GNDD
MCL4148
10u
10K
1
I925
2970
3943
ION_FAN
from AIO1
B
1984
12STBY
6972
7974
BC847BW
F813
125mA
MP13
MCL4148
220K
D
2982
12STBY
6971
6970
4K7
7975
3944
F805
not used
4
5
GNDD
A
12STBY
BC636
7971
1K
100u
for SW contr. only
5SW
1983
5SW
I922
3979
I921
4905
6
for SW contr. only
7973
BC847BW
10K
3947
10n
11
I920
MCL4148
GNDD
12STBY
10R
10R
3997
10R
10R
10R
3978
3996
100n
100u
2981
3969
2985
22K
SW_CAB_FAN
3968
3942
2K2
B
2980
GNDD
I932
from AIO1
22K
3977
A
3967
from PS
FACO
12STBY
5SW
Fan Control
12STBY 3946
Personal Notes:
I932 B1
I933 E3
I924 F3
I925 C3
I926 F2
I927 D1
I928 D1
I929 D4
I930 E4
I931 D5
12STBY
from PS
1983 C5
1984 C5
2970 C2
2980 A2
2981 A3
2982 C3
2983 D4
2984 E1
4
5
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 121
Layout Analog Board (Overview Top View)
1323
1324
1326
1327
1600
1700
1701
1702
1703
1703
1802
1900
1910
1911
1932
1941
1942
1943
1943
1948
1950
1951
1952
1953
C8
C9
C9
C6
C7
C9
B9
B9
B8
A9
A3
B1
C3
C3
C9
A3
A3
A4
A3
A3
A7
A5
A9
C7
1954
1955
1956
1958
1959
1960
1980
1981
1982
1983
1984
1987
1990
1991
1992
1994
1996
2000
2003
2004
2006
2007
2010
2011
B4
A8
B4
A5
A9
C7
B3
C5
B3
A1
B1
C6
C6
A1
A2
B2
C9
A3
A4
A4
A4
A5
A5
A5
2012
2013
2015
2017
2018
2020
2021
2022
2023
2024
2025
2026
2028
2029
2030
2201
2203
2328
2330
2331
2332
2336
2400
2403
A5
A5
B4
A5
A5
B1
B1
B1
B1
B1
B1
B1
A4
B1
A3
A5
B5
C8
A4
A5
C8
B6
A8
A8
2405
2406
2407
2408
2430
2431
2433
2434
2436
2437
2438
2439
2440
2441
2442
2443
2444
2446
2448
2449
2450
2460
2461
2462
A8
A8
A8
A8
A9
A9
A9
A9
A9
A9
A9
A9
A9
A9
A3
A6
A2
A5
A9
B4
B4
A6
A6
A6
2463
2464
2466
2469
2470
2471
2479
2480
2483
2484
2486
2500
2501
2502
2503
2508
2509
2510
2512
2513
2514
2517
2520
2521
A5
A7
A7
A7
A3
A3
A3
A2
A3
A2
A3
B7
B7
A5
A5
A6
A6
A6
B6
A6
A7
B6
B7
B6
2522
2523
2523
2528
2529
2530
2530
2532
2533
2533
2537
2538
2539
2541
2542
2544
2547
2600
2602
2603
2608
2612
2614
2615
B6
A7
C6
B6
B6
B6
A7
C6
C7
B7
B6
B6
B7
B7
B7
B3
A6
B7
B7
B8
B8
B7
C7
C7
2622
2624
2625
2700
2703
2708
2714
2716
2717
2718
2800
2801
2803
2804
2806
2810
2811
2812
2813
2816
2817
2818
2820
2831
C8
C7
C7
A9
C9
A8
B8
B9
B9
B8
A4
B3
B3
B3
A4
B4
A3
B4
A3
B3
B3
A3
A3
A4
2901
2903
2918
2950
2951
2952
2953
2956
2957
2970
2980
2982
2983
2984
2985
2991
3000
3001
3005
3006
3008
3009
3010
3011
B1
A3
A1
C5
C5
B5
B5
B6
B5
A1
A4
A1
A2
A2
A1
C6
A5
A5
A5
A5
A4
A5
A4
A5
3012
3018
3021
3022
3028
3029
3032
3110
3201
3202
3203
3207
3208
3210
3211
3214
3402
3403
3404
3409
3412
3413
3414
3415
A5
A5
A5
A5
A4
A5
A5
C4
B5
B5
B5
B5
B5
B5
B5
B5
A8
A8
A8
A8
A8
A8
A8
A8
3418
3419
3423
3427
3428
3429
3431
3432
3433
3434
3435
3437
3439
3440
3441
3442
3455
3456
3457
3458
3459
3464
3465
3470
B3
B3
A9
A3
A3
A2
A9
A8
A9
A9
A8
A9
A5
A5
A5
A5
A9
A2
A7
A7
A7
A6
A6
A6
3471
3472
3473
3474
3475
3477
3479
3489
3490
3491
3492
3496
3499
3500
3501
3502
3503
3503
3504
3506
3507
3517
3521
3523
A6
A7
A7
A7
A7
A7
A7
A7
A2
A3
A3
A2
A3
B7
B7
A6
B7
B7
B7
B7
A6
A6
B3
A7
3523
3526
3528
3531
3532
3533
3533
3536
3537
3537
3538
3539
3539
3541
3542
3560
3561
3564
3568
3570
3600
3600
3601
3603
B6
A6
B6
B6
A6
A6
A7
B7
A7
B7
B7
A7
B7
B6
B6
B7
B7
A6
A7
B3
C8
B8
C8
C8
3604
3605
3707
3725
3801
3802
3803
3804
3807
3808
3812
3814
3815
3817
3818
3819
3821
3822
3829
3830
3832
3837
3839
3840
C7
C7
A9
B8
B3
B3
B3
B3
A4
B3
B3
B3
A4
B3
B3
C6
B3
A3
A3
A3
A4
A3
B3
B2
3841
3844
3847
3848
3850
3852
3853
3854
3855
3856
3857
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3872
B2
B2
B2
B3
A5
A5
A6
A3
A5
B3
B4
A5
B5
B4
B4
A2
A2
B2
B3
A2
A2
A2
A2
A3
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3890
3891
3892
3896
3897
3898
3901
3903
3904
A3
B3
B4
A3
A3
A3
A2
A3
B4
B3
A3
A2
B3
B4
B4
B2
A3
A3
B3
A2
B4
B1
B2
B2
3905
3906
3908
3910
3911
3912
3916
3917
3918
3920
3921
3922
3930
3940
3941
3942
3943
3944
3946
3947
3948
3951
3952
3953
B2
A1
B2
B2
B1
B1
B2
B2
B1
A2
A1
A1
C5
A2
A2
A1
A1
A1
A1
A1
A2
C5
C5
C5
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3975
3976
3977
3979
3980
3981
3982
3983
3984
3985
3986
B5
B5
B5
B5
B5
B5
A2
A2
A2
A2
A2
A2
A2
A2
A2
A1
A1
A2
A1
A1
A1
A2
A2
A2
3987
3988
3989
3993
3994
3996
3997
4202
4405
4406
4470
4471
4801
4901
4902
4903
4906
5000
5002
5003
5009
5400
5430
5470
A2
A2
A2
C6
C6
A2
A2
B3
B4
B4
A2
A2
C5
A1
A1
A1
B4
A4
A3
B2
B8
A8
A8
A3
5601
5602
5701
5702
5703
5703
5704
5706
5707
5902
5990
6000
6304
6309
6461
6463
6468
6471
6801
6803
6807
6970
6971
6972
C8
C7
B9
C9
B9
C9
B9
B9
A8
B2
C6
A5
A7
B3
A7
A7
A7
A3
B3
A3
B2
A1
A1
A1
7000
7001
7002
7003
7004
7200
7315
7316
7317
7321
7323
7332
7400
7401
7430
7431
7432
7434
7462
7466
7470
7500
7501
7502
A5
A4
A5
A4
A4
B5
A7
B7
B7
C8
C8
A4
A8
A8
A9
A5
A1
B4
A7
A7
A2
B7
B7
A6
7507
7509
7514
7600
7705
7709
7800
7801
7803
7804
7805
7806
7807
7809
7810
7811
7812
7813
7815
7900
7901
7902
7903
7904
B6
A7
B7
B7
C9
B8
A4
B3
B2
A3
B3
A5
B4
B4
B4
A3
B3
A3
B2
B1
B1
A2
A1
A1
7906
7950
7970
7971
7972
7973
7974
7975
7990
A1
C5
A1
A1
A2
A1
A1
A1
C6
Part 2
CL 26532011_01b.eps
Part 1
CL 26532011_01a.eps
CL 26532011_001.eps
170102
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 122
Layout Analog Board (Part 1 Top View)
CL 26532011_01a.eps
170102
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 123
Layout Analog Board (Part 2 Top View)
CL 26532011_01b.eps
170102
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 124
Layout Analog Board (Overview Bottom View)
2001
2002
2005
2008
2009
2014
2016
2019
2027
2100
2101
2102
2103
2104
2105
2106
2200
2202
2321
2322
2323
2324
2325
A6
A5
A6
A5
A6
A5
A5
A6
A6
C7
C7
C7
C7
C7
C7
C6
A5
B5
C2
C2
C2
A6
A6
2329
2401
2402
2404
2410
2411
2432
2445
2447
2465
2467
2468
2472
2473
2474
2477
2481
2485
2504
2505
2506
2507
2511
C1
A1
A2
A1
A2
A2
A1
A9
A5
A2
A3
A3
A8
A7
A7
A7
A6
A7
A1
B4
A4
B4
B5
2513
2516
2518
2519
2524
2526
2527
2531
2534
2540
2545
2546
2548
2549
2551
2601
2603
2604
2606
2607
2609
2610
2616
B4
B4
B4
B5
B6
B4
A3
B4
A2
A2
A3
A4
A4
B4
A3
C3
B3
B2
B2
B2
C3
B3
B3
2617
2620
2621
2623
2701
2702
2704
2705
2706
2707
2709
2710
2711
2712
2713
2715
2802
2805
2807
2808
2809
2814
2815
B3
B3
B3
C3
C1
C1
A1
B2
B2
B1
B2
B1
C1
B1
A1
B1
B6
B7
A7
B8
B8
A7
A7
2819
2821
2822
2823
2827
2832
2900
2902
2903
2904
2906
2907
2908
2909
2910
2911
2912
2914
2915
2916
2917
2954
2955
A6
A7
B7
A7
C1
A6
B8
B9
B9
A9
B5
B8
B8
A9
B8
B8
B9
B8
B8
B7
B8
B5
B5
2981
2990
2992
2993
2994
2995
2996
3002
3005
3004
3007
3015
3014
3015
3016
3017
3019
3020
3023
3024
3025
3026
3027
A8
C4
C4
C4
C4
C4
C4
A6
A6
A6
A5
B9
B9
B9
B9
A5
A6
A5
A6
A6
B9
B9
B9
3030
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3111
3112
3113
3200
3204
3205
3206
3209
3212
3213
3215
3218
B9
C7
C7
C7
C7
C7
C7
C7
C7
C7
C6
C6
C6
C6
A5
B5
B5
B5
B5
B5
B5
B5
B5
3219
3220
3221
3222
3223
3224
3225
3321
3322
3323
3325
3326
3335
3336
3337
3338
3339
3340
3405
3406
3407
3408
3410
B5
B5
B5
B5
B5
B5
B5
C1
C1
C1
C2
C2
C2
C1
C2
C1
C1
C1
A2
A1
A1
A1
A5
Part 1
CL 26532011_03a.eps
3411
3416
3417
3424
3425
3426
3436
3438
3443
3444
3445
3446
3447
3448
3450
3451
3452
3453
3454
3460
3461
3462
3463
A5
A5
A5
A1
A1
A1
A1
A1
A7
A8
A5
A5
A8
A8
A5
A5
A9
A9
A8
A4
A4
A4
A4
3466
3467
3468
3469
3476
3478
3480
3481
3482
3483
3484
3485
3486
3487
3488
3493
3494
3495
3497
3498
3508
3509
3510
A3
A3
A3
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
A4
A3
A8
A7
A8
A6
A7
A4
A4
A4
3511
3512
3513
3514
3515
3516
3518
3519
3520
3522
3524
3527
3529
3530
3534
3536
3538
3540
3543
3544
3545
3546
3547
A4
A1
A1
A1
A4
A4
A4
A4
A3
A4
B4
A4
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A2
3548
2549
3550
3551
3552
3553
5554
3555
3562
3565
3565
3567
3602
3606
3607
3700
3701
3702
3703
3704
3705
3706
3708
A3
A3
A3
A2
A2
A2
A2
A2
A3
A4
A4
A3
B2
B3
B3
B1
A1
B1
A1
C1
B2
B2
C1
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3726
3727
3728
3729
3730
3800
3805
B2
C2
A1
B1
B1
C1
B2
A1
B2
B1
B1
A1
B2
B2
C2
B1
B2
B2
B2
B1
B1
B6
B7
3809
3810
3811
3813
3816
3820
3823
3824
3825
3826
3828
3831
3833
3834
3835
3836
3838
3843
3843
3845
3846
3849
3851
A6
A6
A6
B6
B7
B7
B7
B7
B7
B7
B7
B7
B8
B8
B7
B7
A7
A7
A7
A7
B8
A7
A7
3858
3871
3873
3889
3893
3894
3895
3899
3900
3902
3909
3913
3914
3915
3919
3925
3954
3955
3956
3957
3958
3959
3960
A5
B7
A7
B8
A7
C1
C1
B8
B8
B8
B8
B9
B8
B8
B9
B8
C5
C5
C5
C5
C5
B5
B5
3974
3978
3990
3991
3992
3995
4101
4102
4201
4203
4520
4400
4401
4403
4404
4601
4701
4702
4904
4905
4907
4999
5001
A5
A9
C4
C4
C4
C4
C7
C7
B5
B5
C1
B3
B3
A3
A1
B3
C1
B1
A7
A9
B8
A9
A6
5004
5700
5901
5903
5904
5991
6100
6101
6102
6103
6104
6402
6403
6405
6430
6431
6432
6436
6437
6438
6439
6440
6460
B9
A1
B5
B8
A9
C4
C7
C7
C6
C6
C6
A2
A2
A1
A2
A2
A1
A9
A8
A9
A5
A5
A3
6462
6464
6465
6466
6470
6500
6501
6502
6503
6505
6506
6507
6508
6600
6700
6701
6702
6703
6802
6803
7100
7101
7201
A3
A3
A3
A2
A8
A1
A3
A3
A3
A2
A3
A3
A2
B2
C1
C1
B1
C1
A6
A7
C7
C7
B5
7322
7324
7329
7330
7331
7433
7460
7461
7463
7464
7505
7504
7505
7506
7508
7510
7511
7512
7513
7700
7701
7702
7703
C2
C2
C2
C1
C1
A5
A4
A3
A3
A2
A4
A1
A4
A4
A3
A3
A3
A3
A2
B1
B1
C1
B1
7704
7706
7707
7708
7816
7817
7905
7907
7908
7909
7951
7952
B2
B2
B1
B1
A6
A6
B8
B8
B9
B9
C5
C5
Part 2
CL 26532011_03b.eps
CL 26532011_003.eps
170102
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 125
Layout Analog Board (Part 1 Bottom View)
CL 26532011_03a.eps
190201
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 126
Layout Analog Board (Part 2 Bottom View)
CL 26532011_03b.eps
170102
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 127
Layout Analog Board (Testlands Top View)
CL 16532095_051.eps
100801
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 128
Layout Analog Board (Testlands Bottom View)
RCVBSIn
RCVBSOut
Gout_SC1
RSVHSCIn
RSVHSYIn
RSVHSCOut
AGC
GNDFV
RSVHSYOut
8_SC1
YCVBSOut_SC1
P50_SC1
BC_SC1
RCOut_SC1
AROut_SC1
ARIn_SC1
YCVBSIN_SC1 FBOut_SC1 GNDV
GNDV
ALOut_SC1
YCVBSIN_SC2 FBin_SC2
RCin_SC2
RCAROut
RCALOut
ALIn_SC1
DIG OUT H
ARCLI
GNDA
OPT OUT
ARCRI
DIG OUT L
FAN_IN
8_SC2 ALOut_SC2 AROut_SC2
Gin_SC2
BC_SC2
GNDA
FAN_OUT
ARIn_SC2
DAINCOAX
ALDAC
INT Clock
ARIn_SC2
SYNC
ARDAC
IF
5SW
8SW
5STBY2
SDA1
GNDD
SCL1
D_PCMCLK
A_WCKL
DAOUT
GNDFV
IF-In
40.4
ADATA
GNDV
A_V
A_U
A_Y
FB
BE_FAN
ION
IRESET_DIG
A_RDY
D_RDY
SCL
D_BCLK
IReset
3VD
D_DATA
12STBY
A_YCVBS
D_CVBS
D_Y
D_C
D_WCLK
A_DAT
GNDD
A_C
GNDA
A_PCMCLK
D_DATAO
D_KILL
A_BCLK
DAINOPT
D_R
D_G
DVAR
FLYB
33STBY
VGNSTBY
5NSTBY
AFCRI
AFCLI
CVBSFIN
8SW
GNDA
DVAL
CFIN
5V
12V
YFIN
D_B
SDA
INT
SCL
5M
5STB
IPOR1
RC
5M
VGNSTBY
CL 16532095_050.eps
100801
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 129
DVIO Front Board
0002 C3
0003 D3
1000 B1
1001 B2
Layout DVIO Front Board
1002 A1
2000 A2
2001 A1
2002 D2
2003 D2
3000 D2
1
5000 B2
5001 C2
6000 A2
6001 C2
2
3
0002
0003
1000
1001
1002
2000
2001
2002
2003
2004
2005
3000
5000
5001
6000
6001
DVIO FRONT BOARD
2005
1n
A
2004
1n
4n7
2001
2
4n7
1
2000
A
6000
1002
PH-S
TLMH3100
5V
GND GND1394
GND GND1394
B
B
1000
54030
1001
1318141 5
1
5000
DLW31S
2
6 7 8
GND1394
4
3
3
4
5001
2
C
6
5
1
DLW31S
6001
GND1394
C
310412124452
0002
SM6T
4n7
CL 16532095_033.eps
080801
2003
4n7
GND1394
2002
D
EARTH SPRING
0003
1M
D
3000
GND1394
GND
GND
CL 16532095_032.eps
080801
1
2
3
C1
A2
C1
B2
C2
B1
B1
B2
A1
C1
C2
B2
B2
B2
B1
A1
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 130
DVIO Board: 1394 Interface
4
34 TPB0-
60 XO
5K1
3177
270p
2163
F123
XTAL OSC.
3116
F185
45
1R
46
F102
D2 8
F116
3176 10R
F103
D3 9
F142
3105 10R
F153
D4 10
F149
3107 10R
F154
D5 11
F152
3108 10R
F156
D6 12
F157
3117 10R
F158
D7 13
F109
3191 10R
F107
PC0 20
3188
F104
PC1 21
3190 47R
F106
F108
28 29
10K
PHYD1
80
PHYD2
79
PHYD3
76
PHYD4
75
PHYD5
74
PHYD6
73
PHYD7
86
PHYCTL0
85
PHYCTL1
12KB BUFFER
MEMORY
LINK
CORE
AV1D5 115
50 49 48 39 33 32
AV1D7 117
AV1CLK 99
AV1VALID 102
AV1FSYNC 100
AV1ENDPCK 98
AV1ERR0 96
AV1ERR1 97
AV1SY 101
F133
F134
F135
F136
3103
F143
F144
3106
F192
LINKON
93
ISON
48
88
PD
SCLK
55
CLK50
47
1394MODE
PHY_CNA
AV2D0 133
AV2D1 134
AV2D2 135
AV2D3 136
AV2D4 139
AV2D5 140
AV2D6 141
AV2D7 142
AV2READY 143
AV2CLK 124
AV2SYNC 128
AV2VALID 127
AV2FSYNC 125
AV2ENDPCK 123
AV2ERR0|LTLEND 121
AV2ERR1|DATAINV 122
AV2SY 126
F163
F165
F166
F167
F168
F169
F170
F171
F172
F161
F184
F186
F187
F188
F190
F191
F189
PHY
F117
63 TESTPIN1
64 TESTPIN2
HIFD8 10
HIFD9 9
TESTPIN3
HIFD10 8
HIFD11 7
INTERFACE
8-BIT
59 RESERVED5
65 RESERVED6
66 RESERVED7
67 RESERVED8
68 RESERVED9
71 RESERVED10
F
LINK_CSn
G
3115
+3V3_LINK
100n
2178
100n
LINK_INTn
1K
4100
2177
F
F174
43
34
23
17
11
5
94
106
100MHZ
112
137
+3V3_IEEE_A
PAD(0)
PAD(1)
PAD(2)
PAD(3)
PAD(4)
PAD(5)
PAD(6)
PAD(7)
F198
HIFWAIT 41
HIFINTN 38
47K
47K
47K
47K
47K
47K
47K
47K
E
+3V3_LINK
PWRn
PALE
PRDn
HIFALE 39
HIFRDN 40
HIFMUX 46
HIFCSN 36
GND
F139
5109
119
10K
3113
CONTROL
AND
STATUS
REGISTERS
131
2174
10u
100n
42 RESET_
1394_RSTn
HIF16BIT 45
HIFWRN 37
ASYNC
TRANSMITTER
AND
RECEIVER
100MHZ
89
83
77
69
60
53
+3V3_IEEE_PLL
HIFAD0 22
HIFAD1 21
HIFAD6 14
HIFAD7 13
144 RESERVED16
RESERVED17
F138
HIFD14 2
HIFD15 1
3124
3125
3126
3127
3128
3130
3131
3132
HIFAD4 16
HIFAD5 15
129 RESERVED14
130 RESERVED15
5106
HIFD12 4
HIFD13 3
D
PA(0)
PA(1)
PA(2)
PA(3)
PA(4)
PA(5)
PA(6)
PA(7)
PA(8)
HIFAD2 20
HIFAD3 19
72 RESERVED11
104 RESERVED12
105 RESERVED13
100n
C
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
47K
22K
22K
47K
HIFA8 25
62
52 RESERVED3
58 RESERVED4
2176
3192
3197
3198
3199
3100
3101
3104
3109
3110
3118
3119
3120
3121
3122
3133
3134
3123
HIFA4 29
HIFA5 28
+3V3
50 RESERVED1
51 RESERVED2
10u
10K
10K
92
49
2175
LINK_AVCLK
LINK_AVSYNC
LINK_AVVALID
LINK_AVFSYNC
HIFA2 31
HIFA3 30
58 57
64 63 18 17
LINK_AVREADY
4103
AV1READY 118
AV1SYNC 103
B
F197
HIFA6 27
HIFA7 26
1R
2173
AV1D6 116
LINKFIFO_DQ(0)
LINKFIFO_DQ(1)
LINKFIFO_DQ(2)
LINKFIFO_DQ(3)
LINKFIFO_DQ(4)
LINKFIFO_DQ(5)
LINKFIFO_DQ(6)
LINKFIFO_DQ(7)
87 LREQ
+3V3_LINK
F193
G
+3V3_LINK
AV1D4 114
F124
F125
F127
F128
F129
F130
F131
F132
3102 10K
6
12
18
24
35
44
54
61
70
78
84
90
95
107
113
120
132
138
9K1
OPTION
PHYD0
81
AV1D3 111
PLLGND
DGND
3111
3136
LPS
CYCLEIN
82
AV1D2 110
HIFA0 33
HIFA1 32
AGND
F137
E
91
56
4101
55
100n
CYCLEOUT
47R
CNA 3
PD 14
100n
F101
F175
TEST1
2105
57
F105
10R
RESET_ 53
OPTION
F126
AV1 LAYER
3174 10R
PC2 22
NC
3141
D1 7
F115
54
2104
3140
3138
F114
47
12p
2171
12p
2170
D
F146
TEST0
1102
CX-11F
24M576
3139
F100
D0 6
3171 10R
3172 10R
TRANSMIT
DATA
ENCODER
44
10K
3189
F113
43
F162
1R
F112
CTL1 5
PLL
CLOCK
16
AV1D0 108
AV1D1 109
F602
3193
OPTION
56R
3178
3173
59 XI
VDD
OPTION
CTL0 4
ARBITR’N
AND
CONTROL
STATE
MACHINE
LOGIC
56R
F121
7103
PDI1394
TRANSMITTER/RECEIVER
ISOCHRONOUS
LREQ 1
F111
35 TPB0+
1
3179
F110
+3V3_LINK
AV1 LAYER
LINK
INTERFACE
SYSCLK 2
1R
OPTION
3166
2
+3V3_IEEE_D
F194
C|LKON 19
A
OPTION
F120
+3V3_IEEE_D
F601
ISO_ 23
F119
3
14
LINK
TRANSMITTER/RECEIVER
ISOCHRONOUS
37 TPA0+
36 TPA0-
F118
4
FROM FRONT
DV INPUT PCB
56R
1101
C
56R
3165
3164
8 7 6 5
CPS 24
2K2
F122
13
F195
3137
LPS 15
BIAS
VOLTAGE
38 TPBIAS0
AND
CURRENT
GENERATOR
1u
B
7101
PDI1394
56
PLLVDD
RECEIVED
DATA
DECODER/
TIMER
41 R1
12
{LINK_AVCLK,LINK_AVSYNC,LINK_AVVALID,LINK_AVFSYNC,LINK_CSn,LINK_INTn,LINK_AVREADY}
2K2
2158
DVDD
40 R0
F150
11
LINKFIFO_DQ(7:0)
OPTION
F148
6K34
F199
TESTM
10K
10
+3V3_LINK
52 51 42 31 30 27 62 61 26 25
AVDD
9
+3V3_IEEE_D
+3V3_IEEE_D
3147
3148
8
+3V3_IEEE_PLL
+3V3_IEEE_D
OPTION
A
7
10K
+3V3_IEEE_A
6
OPTION
1394 INTERFACE
5
10K
3
10K
2
3180
1
+3V3_LINK
4102
OPTION
H
H
F140
5110
+3V3
+3V3_IEEE_D
100n
2187
100n
2184
100n
2183
10u
2182
100u
2181
100MHZ
PA(0:15)
5103
PAD(7:0)
100n
100n
2197
100n
2196
100n
2195
100n
2194
100n
2193
100n
2192
100n
2157
100n
2156
100n
2155
100n
2154
100n
2153
100n
2152
100n
2151
100n
2150
100n
2149
+3V3_LINK
100n
2148
100MHZ
F141
100n
2147
+3V3
2146
I
{SRAMCE0n,SRAMRDn,PINT0n,PINT1n,PALE,PWRn,PRDn,PRSTn}
CL 16532145_014.eps
221101
1
2
3
4
5
6
7
8
9
10
11
12
13
14
I
1101
1102
2104
2105
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2163
2170
2171
2173
2174
2175
2176
2177
2178
2181
2182
2183
2184
2187
2192
2193
2194
2195
2196
2197
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3113
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3130
3131
3132
3133
3134
3136
3137
3138
3139
3140
3141
3147
3148
3164
3165
3166
3171
3172
3173
3174
3176
3177
3178
3179
B1
D1
D3
D3
I5
I5
I6
I6
I6
I6
I6
I7
I7
I7
I7
I8
B2
C2
D1
D1
G3
G4
H3
H3
H3
H4
I2
I3
I3
I3
I4
I8
I8
I8
I8
I9
I9
C13
D13
B13
C12
D13
C7
C12
C7
C7
D13
D13
E8
G9
G14
D2
C7
D13
D13
D13
D13
D13
D13
E12
E12
E12
E12
F12
F12
F12
F12
D13
D13
E3
A8
A7
A7
A8
A8
A3
A3
B2
B2
D8
B7
B7
C2
C7
C7
C2
C2
A7
3180
3188
3189
3190
3191
3192
3193
3197
3198
3199
4100
4101
4102
4103
5103
5106
5109
5110
7101
7103
F100
F101
F102
F103
F104
F105
F106
F107
F108
F109
F110
F111
F112
F113
F114
F115
F116
F117
F118
F119
F120
F121
F122
F123
F124
F125
F126
F127
F128
F129
F130
F131
F132
F133
F134
F135
F136
F137
F138
F139
F140
F141
F142
F143
F144
F146
F148
F149
F150
F152
F153
F154
F156
F157
F158
F161
F162
F163
F165
F166
F167
F168
F169
F170
F171
F172
F174
F175
B7
D7
B7
D7
C7
C13
B7
C13
C13
C13
H12
D7
H12
B13
I5
G2
G2
H2
A5
B12
B8
B8
C8
C8
D8
B8
D8
C8
D7
C6
B6
B6
B6
B6
B6
C6
C6
E7
B2
B2
C2
C2
B2
C2
B12
B12
B9
B12
B12
B12
B12
B12
B12
B12
C12
C12
C12
E4
G4
G4
H4
I9
C6
C12
C12
D1
A3
C6
B3
C6
C8
C8
C8
C6
C8
D12
D1
C12
C12
C12
C12
C12
D12
D12
D12
D12
G12
D8
F184
F185
F186
F187
F188
F189
F190
F191
F192
F193
F194
F195
F197
F198
F199
F601
F602
D12
D2
D12
D12
D12
D12
D12
D12
E3
E3
B6
A8
B13
G12
B1
A6
B9
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 131
DVIO Board: Microprocessor
1
2
3
4
5
6
7
8
9
11
10
12
13
14
MICROPROCESSOR
PAD(0:7)
PAD(0:7)
A
A
SRAM
+5V_PROC
Micro processor
+5V_PROC
DSX840GA
11M05
2200
1200
12p
F202
3205 F223
F201 3201 F232 20
PA(0)
PA(1)
44
VCC
XTAL1
AD0
XTAL2
AD1
47R
AD2
10
1K
47K
3206
10K
3204
47K
21
F214
3203
7202
BC847B
2206
PRSTn
F200
12p
35
+5V_PROC
100p
3202
10K
2205
B
7203
P89C51
32
PALE F204
3225 F209
33
PORT0
+5V_PROC
RST
EA_VPP
AD3
AD4
PSEN_
AD5
ALE
AD6
10R
AD7
+5V_PROC
13
TXD
PINT0n
7208
74HCT1G04 5
7204
BST82
2
ISPn
4
F213
3
NC
1
14
15
F203
16
RTSn
D
F211
PINT1n
PWRn
PRDn
4206
Option
F230
17
18
19
RXD
T2
TXD
T2EX
INT0_
INT1_
T0
ECI
PORT1
11
RXD
PORT3
C
CEX0
CEX1
T1
CEX2
WR_
CEX3
RD_
CEX4
A8
+5V_PROC
A9
7209
PDTC144EU
NC
12
23
E
PORT2
1
10K
F220
3226
A10
A11
A12
A13
34
A14
VSS
A15
43
PAD(0)
PA(2)
42
PAD(1)
PA(3)
41
PAD(2)
PA(4)
40
PAD(3)
PA(5)
39
PAD(4)
PA(6)
38
PAD(5)
PA(7)
37
PAD(6)
PA(8)
36
PAD(7)
PA(9)
2
PA(10)
3
PA(11)
PORT1_1
4
F205
5
F206
6
F207
7
F208
1K
3214
PA(12)
3215
PA(13)
1K
3216
1K
Board ID
PA(14)
3217
1K
8
9
OPTION
24
CTSn
PA(8)
25
PA(9)
26
PA(10)
27
PA(11)
28
PA(12)
29
PA(13)
30
PA(14)
31
PA(15)
7201
CY62256 28
21
VCC I|O0
A0
23
A1
I|O1
24
A2
I|O2
25
A3
I|O3
26
A4
I|O4
1
A5
I|O5
2
A6
I|O6
3
A7
I|O7
4
A8
5
A9
6
A10
CE_
7
A11
OE_
8
A12
WE_
9
A13
10
A14 GND
14
11
PAD(0)
12
PAD(1)
13
PAD(2)
15
PAD(3)
16
PAD(4)
17
PAD(5)
18
PAD(6)
19
PAD(7)
20
SRAMCE0n
22
SRAMRDn
27
PWRn
B
C
D
E
22
OPTION
{SRAMCE0n,SRAMRDn,PINT0n,PINT1n,PALE,PWRn,PRDn,PRSTn}
PA(0:15)
F212
5200
100n
2204
100n
2203
100n
2202
3224
+5V_PROC
100MHZ
330R
+5V
F
PA(0:15)
+5V
F219
F
F221
G
G
2207
3223
F222
7207
BC847B
4K7
100n
6200
TLMH3100
Option
1201
F216
1
F210
2
PH-S
To front DV input PCB
H
H
I
I
CL 16532145_015.eps
221101
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1200
1201
2200
2202
2203
2204
2205
2206
2207
3201
3202
3203
3204
3205
3206
3214
3215
3216
3217
3223
3224
3225
3226
4206
5200
6200
7201
7202
7203
7204
7207
7208
7209
F200
F201
F202
F203
F204
F205
F206
F207
F208
F209
F210
F211
F212
F213
F214
F216
F219
F220
F221
F222
F223
F230
F232
B4
G10
B4
G2
G2
G3
B4
C3
G10
B5
B2
B3
C1
B2
C2
C8
C8
D8
D8
G8
G9
C4
E2
D4
F2
H9
A10
B2
B5
C3
G9
C2
E2
B4
B4
B3
D3
C4
C6
C6
D6
D6
C5
G9
C5
F3
D3
B4
G9
F8
E2
G9
G9
B2
D5
B5
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 132
DVIO Board: Fifo & Control
1
2
3
4
5
7
6
8
9
10
11
13
12
14
{TDI,TCK,TDO,TDO_CONF,TMS}
TDO_CONF
FIFO & CONTROL
DATA 1 F328 4301
+3V3_FPGA
PA(9)
PA(8)
+5V_PROC
10R
7
CLKA 1
F329 3317 F305
PINT0n
PINT1n
PALE
CLKB 5
F321 3318 F307
CLKC 6
F323 3319 F308
+3V3_FPGA
CLK27M
CLK27M_DV
CLK27M_CON
33R
GND
IO1
2
LINK_CSn
PLL VIDEO
{LINK_CYCLEOUT,LINK_AVCLK,LINK_AVSYNC,LINK_AVVALID,LINK_AVFSYNC,LINK_AVERR1,LINK_AVERR0,LINK_CSn,LINK_INTn,LINK_AVREADY}
CLOCKGENVID
PROGRAMn
F320 3314 10K
PAD(7:0)
10K
6300
LD1117
IN
OUT
2
CLK27M
F335
+3V3_FPGA
8 24
VCC
CE_ WE_
SRAM
FIFOA_A(5)
FIFOA_A(10)
FIFOA_A(6)
FIFOA_A(9)
FIFOA_A(7)
FIFOA_A(8)
+3V3_FPGA
OE_
FIFOA_A(0)
1
FIFOA_A(1)
2
FIFOA_A(2)
3
FIFOA_A(3)
4
FIFOA_A(4)
13
FIFOA_A(5)
14
FIFOA_A(6)
15
FIFOA_A(7)
16
FIFOA_A(8)
17
FIFOA_A(9)
18
FIFOA_A(10)
19
FIFOA_A(11)
20
FIFOA_A(12)
21
FIFOA_A(13)
29
FIFOA_A(14)
30
FIFOA_A(15)
31
FIFOA_A(16)
32
12
28
FIFOA_WEn
FIFOA_OEn
A1
A2
A3
I|O7
27
FIFOA_D(7)
A4
I|O6
26
FIFOA_D(6)
A5
I|O5
23
FIFOA_D(5)
22
FIFOA_D(4)
11
FIFOA_D(3)
10
FIFOA_D(2)
A6
I|O4
A7
I|O3
A8
I|O2
A9
I|O1 7
FIFOA_D(1)
6
FIFOA_D(0)
A10 I|O0
G
H
A11
A12
A13
A14
A15
A16
GND
9 25
I
{AUD_BCLK,AUD_WS_OUT,AUD_WS_701,AUD_MUTE,AUD_SDI,AUD_SDO_DAC,AUD_SDO_CON}
5
6
7
8
9
10
5304
+3V3_FPGA
+3V3
100n
100n
2312
100n
2311
100n
2309
100n
2308
100n
2307
2306
47u
100MHZ
2314
+3V3
100n
2313
F311
5302
4
F
A0
+3V3_PLL
47u
1
OPTION
3
7301
CY7C1019BV33-10VC
5
F325
2302
100n
2301
2
+3V3_SRAM
FIFOA_WEn
FIFOA_A(12)
FIFOA_A(4)
FIFOA_A(11)
FIFOA_A(16:0)
GND
1
FIFOA_D(7:0)
FIFOA_D(5)
FIFOA_D(3)
FIFOA_D(4)
BUFENn_VID
BUFENn_AUD
PA(8:15)
3
INITn
+3V3_FPGA
+3V3
F318 3313
+5V
F306 3322
47R
{SRAMCE0n,SRAMRDn,PINT0n,PINT1n,PALE,PWRn,PRDn,PRSTn}
I
DV_RSTn
DV_RWn
DV_DSUn
DV_DSLn
DV_LCn
DV_ERRn
DV_DRQn
DV_DTACKn
AUD_SDI
AUD_WS_701
LINKFIFO_DQ(0:7)
100n
2310
H
E
11
100MHZ
F313
+3V3_SRAM
12
100n
EPROM
2
VDD
FIFOA_D(0)
FIFOA_D(7)
FIFOA_D(1)
FIFOA_D(6)
FIFOA_D(2)
2324
PLL
BLOCK
FIFOA_A(3)
FIFOA_A(13)
FIFOA_OEn
100n
2325
G
8 OE|FS
PAD(2)
PAD(1)
PAD(0)
+3V3_FPGA
10K
+3V3
CLK27M_OSC
D
DONE
FIFOA_A(0)
FIFOA_A(16)
FIFOA_A(1)
FIFOA_A(15)
FIFOA_A(2)
FIFOA_A(14)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
4 XTO
OSC
3312 F300
GND
CONFIGURABLE
MULTIPLEXER
AND DIVIDE
LOGIC
3 XTI
3
FPGA / EPLD
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
3329
100n
OUT
DONE
GND9
I|O56-GCK4
I|O55
I|O54
I|O53
I|O52
I|O51
GND8
I|O50
I|O49
I|O48
I|O47
I|O46
I|O45
I|O44
I|O43
GND7
VCC3
I|O42-INIT_
I|O41
I|O40
I|O39
I|O38
I|O37
I|O36
I|O35
GND6
I|O34-LDC_
I|O33
I|O32
I|O31
I|O30-HDC
I|O29-GCK3
PWRDWN_
VCC2
10K
100MHZ
2305
2303
O-TDO
GND13
I|O85
I|O86-GCK7
I|O87
I|O88
I|O89-CS1
I|O90
I|O91
GND14
I|O92
I|O93
I|O94
I|O95
I|O96
I|O97
I|O98
I|O99
GND15
VCC7
I|O100
I|O101
I|O102
I|O103
I|O104
I|O105
I|O106
I|O107
GND16
I|O108
I|O109
I|O110
I|O111
I|O112
I|O113-GCK8
VCC8
3328
F317
7304
FXO-31FT 4
VDD
1
TS
OSC
PAD(7)
PAD(6)
PAD(5)
PAD(4)
PAD(3)
PRSTn
100n
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
CLK27M_OSC
+3V3_FPGA
EPROM
CELL
MATRIX
GND NC
5 6
CLOCKGENVID
F330
F304
PA(15)
PA(14)
PA(13)
PA(12)
PA(11)
PA(10)
ADDR
COUNTER
CONFIG ROM
7308
CY2071AS
47R
47R
47R
PWRn
PRDn
E
5301
47R
AUD_BCLK
3321
AUD_WS_OUT
3325
CLOCKGENAUD 3320
SRAMCE0n
SRAMRDn
VCC
F310
7303
XCS30XL
1K
7
F309 3331
C
3303
AUD_SDO_DAC
3 RESET|OE_
+3V3_PLL
2
33R
TDO
B
+3V3_FPGA
1K
GND
F303 3315
100n
8
CLKB 5
CLKC 6
PLL AUDIO
100n
2318
7300
XC17S30XL
CLKA 1 F315
3301
F333
2319
2 CLK
DATA
F336 CCLK
DATA
DONE
+3V3_FPGA_CONF
VDD
PLL
BLOCK
LINKFIFO_DQ(1)
LINKFIFO_DQ(0)
1394_RSTn
PHY_CNA
INITn
DONE
INITn
CCLK
DATA
CCLK
PROGRAMn
{DATA,CCLK,DONE,INITn,PROGRAMn}
7
EPROM
8 OE|FS
D
F
OSC
CLOCKGENAUD XTI
3
4 XTO
OPTION
4 CE_
100n
7307
CY2071AS
11
11
100MHZ
+3V3_FPGA
12
+3V3_PLL
3300
10R
+3V3_FPGA
LINK_AVSYNC
LINK_AVVALID
LINKFIFO_DQ(7)
LINKFIFO_DQ(6)
LINKFIFO_DQ(5)
LINKFIFO_DQ(4)
LINKFIFO_DQ(3)
LINKFIFO_DQ(2)
C
CONFIG FLASH
12
47R
9
10
10
F314 2304
5300
13
IO10
9
14
LINK_AVREADY
LINK_INTn
LINK_AVFSYNC
LINK_AVCLK
13
AUD_MUTE
AUD_SDO_CON
F301
8
15
3330
14
RESETn
15
7
F302
47R
6
16
TDO_CONF
TCK
TMS
1K
8
16
F326
17
17
5
100n
18
DOUT
6
7
3307
18
4
5
F322
TCK
3
100n
2332
19
+3V3_FPGA
F319
TMS
19
IO3
IO4
4
2
20
108
VCC6
107
CCLK
106
I|O84-GCK6-DOUT
105
I|O83-D0-DIN
104
I|O82
103
I|O81
102
I|O80
101
I|O79-D1
100
GND12
99
I|O78
98
I|O77
97
I|O76
96
I|O75-D2
95
I|O74
94
I|O73
93
I|O72
92
I|O71-D3
91
GND11
90
VCC5
89
I|O70
88
I|O69-D4
87
I|O68
86
I|O67
85
I|O66
84
I|O65-D5
83
I|O64
82
I|O63
81
GND10
80
I|O62
79
I|O61-D6
78
I|O60
77
I|O59
76
I|O58-GCK5
75
I|O57-D7
74
PROGRAM_
73
VCC4
3
F316
TDI
20
GND1
I|O1-GCK1
I|O2
I|O3
I|O4
I|O5-TDI
I|O6-TCK
GND2
I|O7
I|O8
I|O9-TMS
I|O10
I|O11
I|O12
I|O13
I|O14
GND3
VCC1
I|O15
I|O16
I|O17
I|O18
I|O19
I|O20
I|O21
I|O22
GND4
I|O23
I|O24
I|O25
I|O26
I|O27
I|O28-GCK2
M1
GND5
M0
4300
2
1
CONFIGURABLE
MULTIPLEXER
AND DIVIDE
LOGIC
1K
1K
3305
3306
B
100n
2331
7309
XC18V01
1
HAD(3)
HAD(2)
HAD(1)
HAD(0)
HAD(7)
HAD(6)
HAD(5)
HAD(4)
2330
+3V3_FPGA_CONF
F324
A
{DV_LCn,DV_ERRn,DV_DRQn,DV_DTACKn,DV_ASn,DV_PDn,DV_DSUn,DV_RWn,DV_VS,DV_HS_IN,DV_RSTn,DV_HS_OUT,DV_DSLn}
DV_ASn
DV_HS_OUT
DV_HS_IN
+3V3_FPGA_CONF
F331
F312
100MHZ
HAD(7:0)
F332 3327
5303
+3V3
+3V3_FPGA_CONF
A
+3V3_FPGA_CONF
+3V3_FPGA_CONF
4302
CL 16532145_016.eps
221101
13
14
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2318
2319
2324
2325
2330
2331
2332
3300
3301
3303
3305
3306
3307
3312
3313
3314
3315
3317
3318
3319
3320
3321
3322
3325
3327
3328
3329
3330
3331
4300
4301
4302
5300
5301
5302
5303
5304
6300
7300
7301
7303
7304
7307
7308
7309
F300
F301
F302
F303
F304
F305
F306
F307
F308
F309
F310
F311
F312
F313
F314
F315
F316
F317
F318
F319
F320
F321
F322
F323
F324
F325
F326
F328
F329
I3
I4
F4
C8
F3
I9
I9
I9
I9
I9
I10
I10
I10
I8
D3
D3
I12
I12
A4
B4
B4
G9
B11
E12
B1
B1
C1
F5
H9
H9
D7
G3
G3
G3
D7
D7
C10
D7
C9
G10
G11
C8
D7
B1
E4
A2
C7
F2
I8
A1
I12
I3
D2
F13
D10
F4
C7
F2
A2
F5
C8
C8
D7
D7
G3
C10
G3
G3
D7
D7
I10
A2
I12
C7
C8
B2
F2
H9
B2
H9
G3
B2
G3
B2
I4
B3
E4
G3
F330
F331
F332
F333
F335
F336
D7
C8
C8
E12
B10
B8
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 133
DVIO Board: DVCODEC
1
A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DVCODEC
A
+3V3_DV
+3V3_DV
AUD_WS_701
AUD_BCLK
AUD_SDI
F401
3405
F403
47R
F402
IO(11)
IO(14)
IO(13)
IO(12)
IO(15)
+3V3_DV
+35V_DV_EDO
IO(18)
IO(17)
IO(16)
IO(19)
IO(22)
IO(21)
IO(20)
IO(23)
+35V_DV_EDO
IO(26)
IO(25)
IO(24)
IO(27)
+35V_DV_EDO
IO(30)
IO(29)
IO(28)
VIDEO BUS
C
+VCC_DV_RAM
Φ
A(0)
A(1)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
IO(3)
+35V_DV_EDO
IO(2)
IO(1)
IO(0)
A(8)
+3V3_DV
A(7)
A(6)
A(5)
17
18
19
20
23
24
25
26
27
28
RASn
LCASn
UCASn
WEn
A(4)
+3V3_DV
14
31
30
13
29
A(3)
A(2)
A(1)
15
16
0
1
2
3
4
5
6
7
8
9
EDO RAM
1Mx16
ADR
DATA
RAS
LCAS
HCAS
WE
OE
NC
WEn
LCASn
UCASn
21
Φ
2
3
4
5
7
8
9
10
33
34
35
36
38
39
40
41
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IO(0)
IO(1)
IO(2)
IO(3)
IO(4)
IO(5)
IO(6)
IO(7)
IO(8)
IO(9)
IO(10)
IO(11)
IO(12)
IO(13)
IO(14)
IO(15)
A(0)
A(1)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
RASn
LCASn
UCASn
WEn
11
12
32
NC
A(0)
+3V3_DV
7403
MT4LC1M16E5
1
7402
MT4LC1M16E5
IO(6)
IO(5)
IO(4)
21
IO(7)
+35V_DV_EDO
+VCC_DV_RAM
6
IO(10)
IO(9)
IO(8)
6
+35V_DV_EDO
1
GENERAL
PURPOSE I/O
VSS26
HOST-RST_
HOST-CS_
HOST-R|W_
HOST-DSU_
HOST-DSL_
HOST-PD_
HOST-AS_
VSS25
DRAM-D31
VCC3.3-25
DRAM-D30
DRAM-D29
DRAM-D28
VSS24
DRAM-D27
VCC3.3-24
DRAM-D26
DRAM-D25
DRAM-D24
VSS23
DRAM-D23
VCC3.3-23
DRAM-D22
DRAM-D21
DRAM-D20
VSS22
DRAM-D19
VCC3.3-22
DRAM-D18
DRAM-D17
DRAM-D16
VSS21
DRAM-D15
VCC3.3-21
DRAM-D14
DRAM-D13
DRAM-D12
VSS20
DRAM-D11
AUDIO
INTERFACE
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
17
18
19
20
23
24
25
26
27
28
EDO RAM
1Mx16
0
1
2
3
4
5
6
7
8
9
14
31
30
13
29
ADR
DATA
RAS
LCAS
HCAS
WE
OE
15
16
NC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NC
2
3
4
5
7
8
9
10
33
34
35
36
38
39
40
41
IO(16)
IO(17)
IO(18)
IO(19)
IO(20)
IO(21)
IO(22)
IO(23)
IO(24)
IO(25)
IO(26)
IO(27)
IO(28)
IO(29)
IO(30)
IO(31)
D
11
12
32
E
22
37
42
E
DV Decoder
VCC3.3-20
DRAM-D10
DRAM-D9
DRAM-D8
VSS19
DRAM-D7
VCC3.3-19
DRAM-D6
DRAM-D5
DRAM-D4
VSS18
DRAM-D3
VCC3.3-18
DRAM-D2
DRAM-D1
DRAM-D0
VSS17
DRAM-A8
VCC3.3-17
DRAM-A7
DRAM-A6
DRAM-A5
VSS16
DRAM-A4
VCC3.3-16
DRAM-A3
DRAM-A2
DRAM-A1
VSS15
DRAM-A0
VCC3.3-15
DRAM-WE_
DRAM-LCAS_
DRAM-UCAS_
VSS14
DRAM-RAS_
VCC3.3-14
VID-RDY
VID-DTACK_
VID-OE_
22
37
42
+3V3_DV
DRAM ADDRESS BUS
HAD(5)
HAD(6)
HAD(7)
DRAM CTRL
+3V3_DV
HAD(4)
SYNCHRONOUS
VIDEO INTERFACE
HAD(1)
HAD(2)
HAD(3)
D
DRAM DATA [ 0...31] BUS
VIDEO BUS CLOCK INPUTS
+3V3_DV
HAD(0)
VCC3.3-1
HOST-16|8_
GPIO0
GPIO1
GPIO2
GPIO3
VSS1
HOST-DTAC_
HOST-DRQ_
HOST-ERR_
HOST-LC_
VCC3.3-2
HOST-AD0
VSS2
HOST-AD1
HOST-AD2
HOST-AD3
VCC3.3-3
HOST-AD4
VSS3
HOST-AD5
HOST-AD6
HOST-AD7
VCC3.3-4
HOST-AD8
VSS4
HOST-AD9
HOST-AD10
HOST-AD11
VCC3.3-5
HOST-AD12
VSS5
HOST-AD13
HOST-AD14
HOST-AD15
VCC3.3-6
AUD-WS
VSS6
AUD-BCLK
AUD-SDO
HOST AD BUS [ 0....15 ]
DV_DTACKn
DV_DRQn
DV_ERRn
DV_LCn
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
B
RASn
+3V3_DV
CRTL{RASn,LCASn,UCASn,WEn}
VCC3.3-7
AUD-SDI
RES1
VSS7
RES2
RES3
RES4
VCC3.3-8
RES5
VSS8
RES6
RES7
RES8
VCC3.3-9
VID-D0
VSS9
VID-D1
VID-D2
VID-D3
VCC3.3-10
VID-D4
VSS10
VID-D5
VID-D6
VID-D7
VCC3.3-11
TEST
VSS11
VID-CLK1
VID-CLK0
RES9
VCC3.3-12
VID-VS
VSS12
VID-HS
VID-FLD
RES10
VCC3.3-13
RES11
VSS13
+3V3_DV
A(0:8)
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
10K
3400
7404
NW700LQ
C
+3V3_DV
F400
B
IO(31)
DV_RSTn
DV_RWn
DV_DSUn
DV_DSLn
DV_PDn
DV_ASn
IO(31:0)
F426
F
+3V3_DV
F405
F418
F404 +3V3_DV
F422 47R
47R
3404
DV_HS_IN
DV_VS
F421
HAD(7:0)
1Mx16 devices are used as 256kx16
G
3403
CLK27M_DV
YUV(5) 3402-C
YUV(6)
YUV(7) 3402-A
F420
3401-A
F409
YUV(4)
H
YUV(1)
YUV(2)
YUV(3)
YUV(0)
3401-C
47R
G
F407
3401-B
F408
47R
F419
47R 3402-D
+3V3_DV
F411
47R
F410
F412
47R
3402-B
F413
47R
F414
47R
+3V3_DV
+3V3_DV
47R
F406
3401-D
+3V3_DV
+3V3_DV
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
F
YUV(7:0)
H
{DV_LCn,DV_ERRn,DV_DRQn,DV_DTACKn,DV_ASn,DV_PDn,DV_DSUn,DV_RWn,DV_VS,DV_HS_IN,DV_RSTn,DV_HS_OUT,DV_DSLn}
+VCC_DV_RAM
100n
100n
2420
100n
2419
100n
2418
100n
2417
100n
100n
2415
100n
2414
100n
2413
100n
2412
100n
F417
100MHZ
2416
+35V_DV_EDO +3V3
2411
100MHZ
5404
F425
100MHZ
100n
2409
100n
2408
100n
2407
100n
2406
100n
2405
100n
2404
100n
2403
100n
2402
100n
2401
100n
+3V3
2410
+3V3_DV
2400
I
5403
F416
100n
5402
100MHZ
5401
+5V
100MHZ
2421
5400
+5V
{AUD_BCLK,AUD_WS_OUT,AUD_WS_701,AUD_MUTE,AUD_SDI,AUD_SDO_DAC,AUD_SDO_CON}
+3V3
OPTION
OPTION
{DV_LCn,DV_ERRn,DV_DRQn,DV_DTACKn,DV_ASn,DV_PDn,DV_DSUn,DV_RWn,DV_VS,DV_HS_IN,DV_RSTn,DV_HS_OUT,DV_DSLn}
I
CL 16532145_017.eps
221101
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
3400
3401-A
3401-B
3401-C
3401-D
3402-A
3402-B
3402-C
3402-D
3403
3404
3405
5400
5401
5402
5403
5404
7402
7403
7404
F400
F401
F402
F403
F404
F405
F406
F407
F408
F409
F410
F411
F412
F413
F414
F416
F417
F418
F419
F420
F421
F422
F425
F426
I6
I6
I6
I7
I7
I7
I8
I8
I8
I8
I10
I10
I11
I11
I11
I12
I13
I13
I14
I14
I14
I15
B4
H5
G5
H5
G5
H6
G6
H6
G6
G6
G7
F3
H10
H13
I5
I10
I13
C9
C11
C4
B4
F3
F4
F3
G6
G7
F5
F5
F5
H6
G6
F6
F6
F6
F6
I9
I15
G7
F6
H6
H6
H7
I12
F4
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 134
DVIO Board: Audio & Video Output
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AUDIO & VIDEO OUTPUT
{SRAMCE0n,SRAMRDn,PINT0n,PINT1n,PALE,PWRn,PRDn,PRSTn}
{LINK_AVCLK,LINK_AVSYNC,LINK_AVVALID,LINK_AVFSYNC,LINK_CSn,LINK_INTn,LINK_AVREADY}
1508
PINT0n
4506
1
PINT1n
4507
2
LINK_AVVALID 4508
3
LINK_AVFSYNC 4509
4
A
Clock delay
3
7
B
4
5
7
7
8 F501
10 9
IO1
7
7
+3V3
5501
100n
2501
C
F510
IO3
F506
IO4
7
F509
F507
7
33R 5 3504-D
4
3505-B 2 33R
33R
F504
5
3505-D
2502 100n
4
4510
6
4511
7
4512
8
4513
10
4514
11
B
9
3504-B 2
F508
100MHZ
+3V3_dly
100MHZ
2500
OPTION
DOUT
IO10
5500
+3V3
F500 11
4500
6
A
5
14
14
47R
2
14
+3V3_dly
7500-D
74LVC04A
3512
14
4501
1
CLK27M_CON
+3V3_dly
7500-E
74LVC04A
47R
14
+3V3_dly
7500-C
74LVC04A
OPTION
+3V3_dly
7500-B
74LVC04A
3510 F502
+3V3_dly
7500-A
74LVC04A
PH-S
12
OPTION
F505
F503
C
33R
100n 2503
2504 100n
1500
179161
14
15
16
F521 17
18
19
20
21
22
23
24
25
26
27
28
F534 29
30
F559
17
4
RTSN
19
20
27
22
26
23
F533
3525
F554
33R
F555
Buffer
F531
+3V3
F558
3526
33R
F556
F
F532
2505
E
47u
2506
+3V3
7506
UDA1334ATS
31
32
F535 33
34
AUD_WS_OUT
2 WS
35
36
AUD_SDO_DAC
3 DATAI
37
38
F557
3527
2507
47u
2508
100n
100n
13
VDDA
1 BCK
AUD_BCLK
4
VDDD
DIGITAL
INTERFACE
PLL
PLL0 10
F
SFOR0 11
33R
F536
+5V
F537
RESETn
F538
ISPN
G
F546
TXD
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DE-EMPHASIS
SFOR1 7
6 SYSCLK|PLL1
+5V
INTERPOLATION FILTER
8 MUTE
AUD_MUTE
NOISE SHAPER
9 DEEM|CLKO
F539
2514
3518 F540
CTSN
100R
F547
RXD
14 VOL
VOR 16
F544
47u F545
VSSA
15
VSSD
VREF-DAC
5
12
F548
2515 F541
3519 F542
F543 2
100R
47u
PH-S
1501
1
3
TCK
H
YUV(7:0)
58
TDO
60
F552
TMS
100n
59
2519
57
F551
47u
TDI
F550
2518
4
F549
To analog PCB
32
F528
F530
10n
14
16
1
33R
13
DAC
2517
3
33
F523
+3V3
3521
1
3506
+3V3
5502
12
F518 13
F525
11
F517
33R
9
12
29
F516
33R
8
37
30
3524 2
D
220K
DV_HS_OUT
DV_VS
AUD_BCLK
AUD_SDO_CON
AUD_WS_OUT
2
11
35
1
3502
6
1
38
36
10
DAC
40
9
5503
41
F515
F526
5
8
33R
DAC
44
1
3520
3
43
F527
33R
F529
2
6
220K
1
46
5
7
10n
1
3504-A
F513
F514
6
2516
E
47
8
F512
4
47u
F524
33R
1
3504-C 3
2
3
100n
2511
34
39
3505-A
33R
F522
28
45
YUV(0)
YUV(1)
YUV(2)
YUV(3)
YUV(4)
YUV(5)
YUV(6)
YUV(7)
8
21
F511
47u
24
BUFENn_AUD
F520
15
EN1
EN2
EN3
EN4
3505-C 3
100n
25
6
2509
48
10
GND
1
BUFENn_VID
D
F519
4
VC
1
2512
7 18 31 42
4505
7505
74LVC16244AD
2510
100n
F553
To digital PCB
G
H
{DV_LCn,DV_ERRn,DV_DRQn,DV_DTACKn,DV_ASn,DV_PDn,DV_DSUn,DV_RWn,DV_VS,DV_HS_IN,DV_RSTn,DV_HS_OUT,DV_DSLn}
{TDI,TCK,TDO,TDO_CONF,TMS}
{AUD_BCLK,AUD_WS_OUT,AUDIO_WS_701,AUD_MUTE,AUD_SDI,AUD_SDO_DAC,AUD_SDO_CON}
Shielding connection on mounting holes
Hole 4.0 mm with Cu
0001
1507
1506
1505
1503
Hole 4.0 mm with Cu
1502
+3V3_dly
7500-F
74LVC04A
14
13
12
1504
I
0002
0003
I
Hole 3.6 mm
Hole 4.9mm
0004
0005
0007
0006
7
OPTION
CL 16532145_018.eps
221101
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0001
0002
0003
0004
0005
0006
0007
1500
1501
1502
1503
1504
1505
1506
1507
1508
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2514
2515
2516
2517
2518
2519
3502
3504-A
3504-B
3504-C
3504-D
3505-A
3505-B
3505-C
3505-D
3506
3510
3511
3512
3518
3519
3520
3521
3524
3525
3526
3527
4500
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
5500
5501
5502
5503
7500-A
7500-B
7500-C
7500-D
7500-E
7500-F
7505
7506
F500
F501
F502
F503
F504
F505
F506
F507
F508
I4
I5
I6
I6
I7
I8
I8
C7
G14
I2
I2
I2
I2
I3
I3
A14
C1
C3
C3
C3
C3
E12
E12
E11
E11
E6
F8
F8
G8
G11
G13
G10
G13
H12
H12
D5
D5
C5
D5
C5
D5
C5
D5
C5
E5
B3
B4
B5
G10
G13
G10
G13
D5
E5
F5
F5
B4
E6
A13
A13
A13
A13
B13
B13
B13
B13
B13
B1
C3
E12
E12
B2
B2
B3
B4
B4
I1
D3
F11
B4
B5
B3
C6
C5
C6
C5
C6
C5
F509
F510
F511
F512
F513
F514
F515
F516
F517
F518
F519
F520
F521
F522
F523
F524
F525
F526
F527
F528
F529
F530
F531
F532
F533
F534
F535
F536
F537
F538
F539
F540
F541
F542
F543
F544
F545
F546
F547
F548
F549
F550
F551
F552
F553
F554
F555
F556
F557
F558
F559
C6
C5
D6
D6
D7
D6
D6
D6
D6
D7
D5
D5
E7
D5
E6
D5
E12
E12
E2
E6
D5
E4
E7
E8
E4
F7
F7
F7
G7
G7
G8
G10
G13
G13
G14
G12
G11
G7
G8
G12
H7
H8
H7
H8
H13
E4
F4
F4
F6
F6
E6
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 135
Layout DVIO Board (Overview Top View)
PART 1
CL 16532145_19a.eps
PART 2
CL 16532145_19b.eps
CL 16532145_019.eps
201101
1101
1102
1200
1201
1500
1501
1508
2104
2105
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2163
2170
2171
2173
2174
2175
2176
2177
2178
2181
2182
2183
2184
2187
2192
2193
2194
2195
2196
2197
2200
2202
2203
2204
2205
2206
2207
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2318
2319
2324
2325
2330
2331
A2
B1
B5
A6
C6
A4
G2
B1
C1
D2
D2
D2
D2
D2
C2
C2
C1
C1
D1
D1
D1
A1
B2
B1
B1
C1
B1
B1
B1
B1
B2
A1
B2
B2
B2
B1
D1
D1
E1
E1
E2
E2
B4
C4
C4
C3
B5
C5
A6
G4
G4
E2
D4
D4
E3
E3
E4
E4
D4
D3
D3
E3
F2
E4
E4
E3
F3
E4
F4
2332
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2514
2515
2516
2517
2518
2519
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3113
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
F4
D6
D5
D5
D5
D5
D5
D5
D5
E5
E5
E5
E5
E6
E6
D6
D6
F4
F5
F6
E4
E5
E6
A5
B5
B5
B6
C5
B4
B4
B5
B4
C6
B6
C5
C5
A4
A5
A4
A4
B4
B4
E2
E2
E1
D1
E2
C1
D1
C2
C2
E2
E2
C2
C2
C2
B1
C2
E2
E2
E2
E2
E2
E2
D2
D2
D2
D2
D2
3130
3131
3132
3133
3134
3136
3137
3138
3139
3140
3141
3147
3148
3164
3165
3166
3171
3172
3173
3174
3176
3177
3178
3179
3180
3188
3189
3190
3191
3192
3193
3197
3198
3199
3201
3202
3203
3204
3205
3206
3214
3215
3216
3217
3223
3224
3225
3226
3300
3301
3303
3305
3306
3307
3312
3313
3314
3315
3317
3318
3319
3320
3321
3322
3325
3327
3328
3329
3330
D2
E2
E2
E1
E1
B2
C2
B2
C2
D1
D1
B1
B1
B2
B2
C3
C1
C1
B2
C1
C1
B2
B2
C2
C2
C1
C1
C1
C2
E2
D1
E2
E2
E2
B5
C5
C5
C5
C5
C5
C5
C5
C5
C5
A6
B6
C4
C4
E3
E4
E3
F4
F4
F4
E3
E3
E3
D4
E4
D4
D4
D3
D4
E4
D4
E4
E3
E3
D4
3331
3400
3401
3402
3403
3404
3405
3502
3504
3505
3506
3510
3512
3518
3519
3520
3521
3524
3525
3526
3527
4100
4101
4102
4103
4206
4300
4301
4302
4500
4501
4505
5103
5106
5109
5110
5200
5300
5301
5302
5303
5304
5400
5401
5402
5403
5404
5500
5501
5502
5503
6300
7101
7103
7201
7202
7203
7204
7207
7208
7209
7300
7301
7303
7304
7307
7308
7309
7402
D4
D6
D5
D5
E5
E4
D4
B6
B6
B6
B6
B5
B5
A4
A4
A4
A4
B6
C5
B6
B6
C2
C2
C2
E1
B5
E4
E4
E4
B5
B5
B5
C2
C1
B1
B2
C5
D4
D4
E2
F4
F3
E6
F6
E5
E6
F6
A5
A5
B4
B4
G4
B1
D2
C3
C5
C4
C4
A6
C4
C4
E4
F3
E3
E2
D4
D4
F4
F5
7403
7404
7500
7505
7506
F5
D5
B5
B5
B4
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 136
Layout DVIO Board (Part 1 Top View)
PART 1
CL 16532145_19a.eps
211101
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 137
Layout DVIO Board (Part 2 Top View)
PART 2
CL 16532145_019b.eps
211101
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 138
Layout DVIO Board (Testlands Bottom View)
CLK27M_con
+3V3
uP_CLK
PSEN
+3V3_IEEE_A
+3V3_IEEE_D
+3V3_IEEE_PLL
+5V
RESET
+3V3_LINK
+5V_PROC
+3V3_FPGA
CLK27M_DV
+3V3_DV
+35V_DV_EDO
CLOCKAUDTMP
+Vcc_DV_RAM
CL 16532145_021.eps
221101
CLK27M
+3V3_PLL
+3V3_FPGA_CONF
+3V3_SRAM
F100
F100
F101
F101
F102
F102
F103
F103
F104
F104
F105
F105
F106
F106
F107
F107
F108
F108
F109
F109
F110
F110
F111
F111
F112
F112
F113
F113
F114
F114
F115
F115
F116
F116
F117
F117
F118
F118
F119
F119
F120
F120
F121
F121
F122
F122
F123
F123
F124
F124
F125
F125
F126
F126
F127
F127
F128
F128
F129
F129
F130
F130
F131
F131
F132
F132
F133
F133
F134
F134
F135
F135
F136
F136
F137
F137
F138
F138
F139
F139
F140
F140
F141
F141
F142
F142
F143
F143
F144
C6
C6
C6
C6
C6
C6
C5
C5
C6
C6
C6
C6
C6
C6
C5
C5
B5
B5
C5
C5
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C6
C5
C5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
B5
E4
E4
E4
E4
D5
D5
E6
E6
E4
E4
E6
E6
E4
E4
E6
E6
E6
E6
E5
E5
E5
E5
D6
D6
D6
D6
A6
A6
C6
C6
B6
B6
B5
B5
C5
C5
C6
C6
D6
D6
D6
F144
F146
F146
F148
F148
F149
F149
F150
F150
F152
F152
F153
F153
F154
F154
F156
F156
F157
F157
F158
F158
F161
F161
F162
F162
F163
F163
F165
F165
F166
F166
F167
F167
F168
F168
F169
F169
F170
F170
F171
F171
F172
F172
F174
F174
F175
F175
F184
F184
F185
F185
F186
F186
F187
F187
F188
F188
F189
F189
F190
F190
F191
F191
F192
F192
F193
F193
F194
F194
F195
F195
F197
F197
F198
F198
F199
F199
F200
F200
F201
F201
F202
F202
F203
F203
F204
F204
F205
F205
D6
B6
B6
B6
B6
C5
C5
B6
B6
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
D6
D6
B6
B6
D5
D5
E5
E5
D5
D5
D5
D5
E5
E5
E5
E5
D5
D5
D5
D5
E5
E5
D5
D5
C4
C4
D5
D5
B6
B6
D5
D5
D5
D5
D6
D6
D5
D5
E6
E6
D6
D6
B5
B5
B5
B5
C5
C5
C5
C5
E6
E6
D5
D5
B5
B5
B3
B3
B2
B2
C2
C2
C3
C3
D4
D4
C2
C2
F206
F206
F207
F207
F208
F208
F209
F209
F210
F210
F211
F211
F212
F212
F213
F213
F214
F214
F216
F216
F219
F219
F220
F220
F221
F221
F222
F222
F223
F223
F230
F230
F232
F232
F300
F300
F301
F301
F302
F302
F303
F303
F304
F304
F305
F305
F306
F306
F307
F307
F308
F308
F309
F309
F310
F310
F311
F311
F312
F312
F313
F313
F314
F314
F315
F315
F316
F316
F317
F317
F318
F318
F319
F319
F320
F320
F321
F321
F322
F322
F323
F323
F324
F324
F325
F325
F326
F326
F328
C2
C2
C2
C2
C2
C2
C3
C3
A1
A1
C2
C2
C3
C3
C3
C3
C2
C2
A2
A2
B2
B2
C1
C1
B1
B1
A1
A1
C2
C2
B2
B2
B2
B2
E4
E4
D3
D3
E4
E4
D3
D3
D4
D4
E3
E3
E3
E3
D3
D3
B2
B2
B3
B3
D3
D3
D4
D4
F3
F3
E4
E4
D3
D3
D3
D3
F3
F3
D3
D3
E4
E4
F3
F3
D4
D4
D3
D3
F3
F3
D3
D3
E3
E3
G3
G3
E3
E3
E3
F328
F329
F329
F330
F330
F331
F331
F332
F332
F333
F333
F335
F335
F336
F336
F400
F400
F401
F401
F402
F402
F403
F403
F404
F404
F405
F405
F406
F406
F407
F407
F408
F408
F409
F409
F410
F410
F411
F411
F412
F412
F413
F413
F414
F414
F416
F416
F417
F417
F418
F418
F419
F419
F420
F420
F421
F421
F422
F422
F425
F425
F426
F426
F500
F500
F501
F501
F502
F502
F503
F503
F504
F504
F505
F505
F506
F506
F507
F507
F508
F508
F509
F509
F510
F510
F511
F511
F512
F512
E3
D3
D3
D4
D4
E3
E3
E3
E3
E4
E4
E3
E3
D3
D3
E3
E3
D2
D2
E5
E5
E4
E4
E2
E2
E3
E3
D2
D2
D3
D3
D2
D2
B2
B2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
E1
E1
E2
E2
E2
E2
D2
D2
B2
B2
E2
E2
E4
E4
E2
E2
D2
D2
B2
B2
B2
B2
B2
B2
B1
B1
B2
B2
B1
B1
B2
B2
B1
B1
B2
B2
B1
B1
B2
B2
B1
B1
B1
B1
F513
F513
F514
F514
F515
F515
F516
F516
F517
F517
F518
F518
F519
F519
F520
F520
F521
F521
F522
F522
F523
F523
F524
F524
F525
F525
F526
F526
F527
F527
F528
F528
F529
F529
F530
F530
F531
F531
F532
F532
F533
F533
F534
F534
F535
F535
F536
F536
F537
F537
F538
F538
F539
F539
F540
F540
F541
F541
F542
F542
F543
F543
F544
F544
F545
F545
F546
F546
F547
F547
F548
F548
F549
F549
F550
F550
F551
F551
F552
F552
F553
F553
F554
F554
F555
F555
F556
F556
F557
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B3
B3
B2
B2
B2
B2
C1
C1
B2
B2
B1
B1
C2
C2
B3
B3
B3
B3
B2
B2
B1
B1
B2
B2
B2
B2
A2
B2
C1
C1
B1
B1
C1
C1
C1
C1
C1
C1
C1
C1
C3
C3
C1
C1
A3
A3
A3
A3
A3
A3
A3
A3
B3
B3
B3
B3
C1
C1
C1
C1
B3
B3
C1
C1
C1
C1
C1
C1
C1
C1
A3
A3
B2
B2
B2
B2
B1
B1
C1
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 139
Digital Board: VSM, Buffer Memory and Bit Engine Interface
1100
1101
2100
2101
2102
2103
2104
2105
C1
H1
A4
A5
A5
A5
A5
A5
2106
2107
2108
2109
2110
2111
2112
2113
A5
A5
A5
A5
A5
A5
A5
A5
2114
2115
2116
2117
2118
2119
2120
2121
1
A5
A6
A6
A6
A6
A4
B15
B15
2
2122
2123
2124
2125
2126
2127
2128
2129
B14
B14
B13
B13
B12
B12
B3
G13
3
2130
2131
2132
2134
2135
2136
2137
2138
4
G15
H15
B1
D1
G13
F1
G4
G1
2139
2140
2141
2142
2143
2144
2145
2146
G13
G2
G2
G2
H1
H1
H1
A4
2147
2148
2149
2150
2151
2152
3100
3101
6
5
D1
E1
E1
E1
F1
G1
D11
F10
3102
3103
3104
3105
3106
3107
3108
3109
8
7
E3
D11
C2
D2
F2
C3
F3
F3
3110
3111
3112
3113
3114
3115
3116
3117
F3
B3
B3
B3
B2
E3
E3
D11
9
3118
3119
3120
3121
3122
3123
3124
3125
D11
F10
G15
G12
H12
H12
H12
G14
10
3126
3127
3128
3129
3130
3131
3132
3133
H12
G3
G2
H2
H12
D2
E2
E2
11
3134
3135
3136
3137
3138
4100
4101
4102
12
E2
E2
G1
B2
B2
C15
H4
F6
4103
4104
4105
5100
5101
5102
5103
7100
13
F7
G6
G7
A4
A12
B1
F13
B4
7101
7102
7103
7104
14
VERSATILE STREAM MANAGER (VSM), BUFFER MEMORY & BITENGINE INTERFACE
B14
G13
C1
H4
15
DIGITAL VIDEO(CCIR656)
MPEG2 VIDEO
100n
100n
100n
100n
VSM_M_A(13:0)
VCC3_VSM_MEM
48 DQ12
50 DQ13
AE_BCLK_VSM
AE_WCLK_VSM
AE_DATAO
51 DQ14
53 DQ15
JTAG3_TCK
I158
I160
I162
I164
I166
47R
3129
47R
1
I188
2
2K2
2K2
3101
10p
2144
22p
2145
10p
2143
3
5103 I130
I149
GNDD
100n
2120
100n
100n
ACC_ACLK_OSC
3
14
3121
2129
I107 6
68p
I108
3122 12K
3123 1R I182 3124
2K
3130
3K
I109
I110
I122
7
11
12
15
9
5
4100
Encoding
Audio PLL
VCC
COMPI PC1O|PCPO
SIGI
PC2O
12
13
I105
3120 I106
15K
C1A
PLL
2130
C1B
R1
2u2
R2
DEMO
RB
VCOO
10
4
I124
VCOI
2154
10n
OPTION
INH
OPTION
GNDD
1
GNDD
11
G
2
GND
3126 220K
10
F
7102
16
74HCT9046AD
4108
NTH5G16P
9
2121
2122
6
VCC5_4046
4u7
+5V
OPTION
3
8
E
VSSQ
52 46 12
100n
3125
BE_LOADN
7
A7 32
JTAG_CHAIN3
SYSTEM_CONTROL
6
A6 31
22R
SYSTEM ADDRESS BUS
5
A5 30
GNDD
t
4
A4 29
AUDIO ENCODER DATA STREAM BUS
OPTION
2
D
A3 26
A8 33
13
GNDD
8
4101
GNDD
100n
DECODE
COMMAND
VSS
54 41 28
GNDD
1
A2 25
A9 34
SDRAM
GNDD
OPTION
A1 24
A10 22
NC
NC
1
A0 23
BANK
CTRL
LOGIC
COLUMN
DEDCODER
GNDD
H
BA1 21
COLUMN
ADDR
COUNTER/
LATCH
SYSTEM DATA BUS
4
COUNTER
REFRESH
I/O GATING
DQM DATA LOGIC
READ DATA LATCH
WRITE DRIVERS
40 36
4107
7104
5 74HC1G04GW
GNDD
C
GNDD
100n
BE_FAN
VSM_M_RASn
A11 35
JTAG3_TD_VSM_TO_VIP
JTAG3_TMS
JTAG3_TRSTn
VIP_FID_FF
3128
RAS_ 18 I140
ADDRESS REGISTER
22R
3118
22R
GNDD
VSM_M_CASn
BA0 20
ROW
ADDR
MUX
DATA INPUT REGISTER
I153
I154
I155
47 DQ11
VSM_M_WEn
CAS_ 17 I175
2153
3
2123
100n
100n
2124
DATA OUTPUT REGISTER
ACLK_EMP
AE_ACLK
VCC3_VSM
10K
3117
3100
4110
45 DQ10
WE_ 16 I174
17
HO_D15
206
HO_D14
207 HO_D13
1 HO_D12
2 HO_D11
3 HO_D10
4
HO_D9
6
HO_D8
7
HO_D7
8
HO_D6
9
HO_D5
11
HO_D4
12
HO_D3
13
HO_D2
14 HO_D1
16
HO_D0
100n
2125
2127
98
96
93
91
88
86
83
81
82
84
87
89
92
94
97
99
M_D15
M_D14
M_D13
M_D12
M_D11
M_D10
M_D9
M_D8
M_D7
M_D6
M_D5
M_D4
M_D3
M_D2
M_D1
M_D0
68
65
69
63
66
64
61
59
56
54
53
55
58
60
M_A13
M_A12
M_A11
M_A10
M_A9
M_A8
M_A7
M_A6
M_A5
M_A4
M_A3
M_A2
M_A1
M_A0
74
70
76
75
79
72
71
M_CLKOUT
M_CLKEN
25
VDD_181
181
VDD_129
129
VDD_77
77
VDD_25
M_CASn
M_RASn
M_Wen
M_UDQM
M_LDQM
HO_A22
HO_A21
HO_A20
HO_A19
HO_A18
HO_A17
HO_A16
HO_A15
HO_A14
HO_A13
HO_A12
HO_A11
HO_A10
HO_A9
HO_A8
HO_A7
HO_A6
HO_A5
HO_A4
HO_A3
HO_A2
HO_A1
10K
CS_ 19 I173
SENSE AMPLIFIERS
44 DQ9
VSM_M_CLKEN
CLK 38 I171VSM_M_CLKOUT
REG MODE
DQMH DQML
RESETn_BE
2
1101
FMN
I152
CKE 37 I167
CTRL
LOGIC
42 DQ8
OPTION
B
GNDD
22u
GNDD
I126
174
3103
1
2131
I181
4
11 DQ6
OPTION
4104
47p
10p
2141
10p
2142
10p
6
5
10 DQ5
ACC_ACLK_PLL
I147
I132
+3V3
27 14
VDD
2139
47R
OPTION
2140
7
GNDD
47R
2138
OPTION
1R
2152
3136
8
8 DQ4
2135
3127
7 DQ3
13 DQ7
GNDD
4105
I180
5 DQ2
100MHZ
BE_IRQn
3
BANK0
MEMORY
ARRAY
(4,096x256x16)
4106
47R
4 DQ1
4109
47R
3110
9
BANK0
ROWADDR
LATCH &
DECODER
2 DQ0
GNDD
3109
I179
VIP_ERROR
VE_DTACKn
VE_DSn
GNDD
GNDD
I178
11
I168
49 43
VSM_M_UDQMI172 39 DQMH
I102
I103
I104
7101
MT48LC4M16A2TG-7E
GNDD
VSM_M_LDQM I169 15 DQML
I142
I184
I143
162
163
164
165
166
172
173
GNDD
GNDD
3108
179
180
184
185
186
187
188
189
190
191
193
194
195
196
197
198
199
200
202
203
204
205
47R
GNDD
47p
VIP_ICLK
VDDQ
4103
VIP_INT
BE_SERIAL
3106
TCK
TDI
TDO
TMS
TRSTn
TEST0
TEST1
EXT_INT3
BE_WCLK
12
10
171
EXT_INT0
170
EXT_INT1
168
EXT_INT2
167
OPTION
3135
I159
I161
I163
I165
HO_BEN1
HO_BEN0
5508_odd_even
BE_V4
9
10K
CPUINT0
CPUINT1
27
28
3102
50
49
HO_RWn
EMPRESS_IRQn
VCC3_VSM
1R
OPTION
2136
I177
BE_DATA_RD
I156
I157
I101
160
51
158
159
143
157
176
I145
I170
14
3134
142
128
127
109
110
111
112
113
114
115
117
118
119
120
121
122
123
124
125
AE_BCLK
177
AE_WCLK
178
AE_DATA
19
18
OPTION
10p
I176
15
I137
1R
2151 GNDD
1
CPUINT0
CPUINT1
BE_BCLK
AE_CS
VSS_182
10p
3133
1R
OPTION
2150 GNDD
3
2
10K
10K
I186
I187
182
VSS_130
130
VSS_78
78
VSS_26
26
OPTION
10p
VCC3_VSM
VCC3_VSM
BE_FLAG
1R
2149 GNDD
4
3132
3115
3116
VSS_208
VSS_192
VSS_175
VSS_161
VSS_150
VSS_135
VSS_116
VSS_100
VSS_90
VSS_80
VSS_67
VSS_57
VSS_46
VSS_36
VSS_21
VSS_10
5
D_PAR_DVALID
D_PAR_SYNC
D_PAR_STR
208
192
175
161
150
135
116
100
90
80
67
57
46
36
21
10
OPTION
10p
BE_SYNC
1R
2148 GNDD
6
3131
ACC_ACLK_DAI
ACC_ACLK_DEC
ACC_ACLK_OSC
ACC_ACLK_PLL
ACC_FID
ACC_PWM
24
10p
7
G
OPTION
VSM
D_PAR_REQ
D_PAR_D0
D_PAR_D1
D_PAR_D2
D_PAR_D3
D_PAR_D4
D_PAR_D5
D_PAR_D6
D_PAR_D7
D_PAR_DVALID
D_PAR_SYNC
D_PAR_STR
D_V4
D_WCLK
I134
I138 155
I133 154
I136 132
8
13
BE_DATA_WR
30
33
34
39
40
42
43
35
37
38
29
32
45
44
100n 2137
10p
2147 GNDD
10p
TO BITENGINE
10
9
F
3105
2134 GNDD 47R
11
DVDR VERSATILE STREAM MANAGER
VSS_155
VSS_154
VSS_132
VSS_24
I111
BE_BCLK
BE_WCLK
BE_DATI
BE_DATO
BE_SYNC
BE_FLAG
BE_V4
HO_WAIT
HO_PROCCLK
13
12
101
102
103
104
105
106
107
D_PAR_REQ
D_PAR_D(7:0)
14
D
UART2_RTSn
20
3107
I128
VE_VIP_ERROR
VE_DTACKn
VE_DSn
VE_D0
VE_D1
VE_D2
VE_D3
VE_D4
VE_D5
VE_D6
VE_D7
VE_D8
VE_D9
VE_D10
VE_D11
VE_D12
VE_D13
VE_D14
VE_D15
131
133
134
136
137
138
139
140
141
3119
149
UART2_RX
151
UART2_TX
153
UART2_CTSn
152
HO_CSLn
HO_CSHn
10R
201
183
169
156
144
126
108
95
85
73
62
52
41
31
15
5
I116
I117
I118
I119
UART1_CTSn
22
23
GNDD
I120
I121
I123
I125
I127
I129
I131
VDD_201
VDD_183
VDD_169
VDD_156
VDD_144
VDD_126
VDD_108
VDD_95
VDD_85
VDD_73
VDD_62
VDD_52
VDD_41
VDD_31
VDD_15
VDD_5
4K7
4K7
4K7
4K7
3111
3112
3113
145
UART1_RX
146
UART1_TX
147
UART1_RTSn
148
VBI_ICLK
VBI_IPD0
VBI_IPD1
VBI_IPD2
VBI_IPD3
VBI_IPD4
VBI_IPD5
VBI_IPD6
VBI_IPD7
4102
GND
2
15
3114
BE_BCLK_VSM
BE_WCLK
BE_DATA_RD
BE_DATA_WR
BE_SYNC
BE_FLAG
BE_V4
47R
SYSCLK
RESETn
OPTION
3104
4
47
48
2128
1n
GNDD I112
I113
I114
I115
VSM_UART2_RX
VSM_UART2_TX
VSM_UART2_CTSn
VSM_UART2_RTSn
3
GNDD
3138
3137
2132
100n
GNDD
7103
NC7SZ58 5
6
VCC
BCLK_CTL_SERVICE
1
1100
FMN
RESETn
VSM_UART1_RX
VSM_UART1_TX
VSM_UART1_RTSn
VSM_UART1_CTSn
I183
5102
+3V3
E
7100
SAA7333HL
SYSCLK_VSM_5508
UART2
C
4K7
4K7
UART1
B
100MHZ
100MHZ I100
+5V +5V +5V +5V +5V +5V
I141
5101
+3V3
VCC3_VSM
4u7
2126
5100
+3V3
A
VSM_M_D(15:0)
2115
2116
2117
2118
2119
GNDD
A
4u7
2146 100n
2100 100n
2101 100n
2102 100n
2103 100n
2104 100n
2105 100n
2106 100n
2107 100n
2108 100n
2109 100n
2110 100n
2111 100n
2112 100n
2113 100n
2114 100n
{VSM_M_LDQM,VSM_M_UDQM,VSM_M_WEn,VSM_M_RASn,VSM_M_CASn,VSM_M_CLKEN,VSM_M_CLKOUT}
GNDD
14
CL 16532145_022.eps
211101
15
H
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 140
Digital Board: AV Decoder STI5508
10
11
F265
AV decoder : STI5508
GNDD
VDD_STI
GNDD
5210
100MHZ
5212
A
OPTION
1
5202
VDD_RGB
10K
5201
VDD_YCC
7203
LF25C
5203
VDD_PLL
5204
22n
GNDD
4u7
2230
100n
AUDIO_OUT
14
2
AE_ACLK
3 AD_ACLK
7
127
126
125
IRQ0
IRQ1
TDO
TMS
TRST
C
VDD_125
7202-A
74HCT125D
10K
I200
F249
F214
F247
F248
+3V3
VDD_STI
10K
3202
GNDD
113
112
111
110
109
TCK
TDI
PIO4-4
PIO4-5
PIO4-6
PIO4-7
100MHZ
B
100n 2208
2205
2206
100n
2209
CPUINT0
33R
33R
33R
33R
33R
33R
33R
33R
IN
10K
3225
5
6
7
8
5
6
7
8
4
3
2
1
4
3
2
1
39
40
41
42
43
44
45
46
PIO4-0
PIO4-1
PIO4-2
PIO4-3
GND
GNDD
3224
3236-D
3236-C
3236-B
3236-A
3237-D
3237-C
3237-B
3237-A
6
7
8
9
10
11
12
13
PIO3-0
PIO3-1
PIO3-2
PIO3-3
PIO3-4
5205
I266
OUT
I267
2210
3219
10K
10K
FMN
1200
3215
10K
10K
5209
VDD_CORE
VDD_PCM
PIO3-5
PIO3-6
PIO3-7
+5V
2
3220
3244 10K
3245 10K
VDD_STI
VDD_STI
P_SCAN_YUV(7:0)
3242 10K
10K
3240
3241 10K
3243 10K
3238
OPTION
D_PAR_D(7:0)
BCLK_CTL_SERVICE
I264
3
GNDD
I243
I241
I242
10K
3226
TRIGGER-IN
TRIGGER-OUT
I207
I237
I238
I235
I234
VDD_CORE
4
100n
204
205
206
207
208
1
2
3
VDD_STI
100R
100R
VDD_STI
2K2
3218
3217
I268
I269
194
195
196
197
200
201
202
203
PIO1-0
PIO1-1
PIO1-2
PIO1-3
PIO1-4
PIO1-5
PIO0-7
GNDD
I201
I203
I204
I205
I206
I208
I209
I236
3213
131
F264
124
RESET
CPU-WAIT
115
PWM1
CPU-ADR20
CPU-ADR21
173
174
175
176
177
178
179
180
181
182
183
CPU-ADR11
CPU-ADR12
CPU-ADR13
CPU-ADR14
CPU-ADR15
CPU-ADR16
CPU-ADR17
CPU-ADR18
CPU-ADR19
161
162
163
164
165
166
167
168
169
170
CPU-ADR1
CPU-ADR2
CPU-ADR3
CPU-ADR4
CPU-ADR5
CPU-ADR6
CPU-ADR7
CPU-ADR8
CPU-ADR9
CPU-ADR10
D
CPU-DATA13
CPU-DATA14
CPU-DATA15
CPU-DATA8
CPU-DATA9
CPU-DATA10
CPU-DATA11
CPU-DATA12
151
152
153
154
155
156
157
158
7200
STI5508
186
187
188
189
190
191
192
193
2200
3200
GNDD
PIO0-0
PIO0-1
PIO0-2
PIO0-3
PIO0-4
PIO0-5
PIO0-6
GNDD
10K
GNDD
SYSTEM ADDRESS BUS
SYSTEM DATA BUS
10K
GNDD
3214
NVRAM
RESETn
100R
4
EMI_WAIT
3221
10K
3222
10K
ANA_WE_LV
BE_LOADN
LOAD_DVN
Flash_Oen
RESETn_VE
AE_ACLK_OEn
SEL_ACLK1
MUTEN_LV
3223
VSS
1n
WC_
GNDD
10K
OPTION
GNDD
3233
3239
10K
OPTION
3206
I215
10K
+3V3
I240
VDD_STI
VDD_STI
100R
3216
SCL
VDD_STI
GNDD GNDD
5
3K3
GNDD
SDA
3205
33p
B
E2
I229
2207
6
I239 7
E1
3209
33p
3
GNDD
HW version
control
14
5
2231
PIO2-0
PIO2-1
PIO2-2
PIO2-3
PIO2-4
PIO2-5
VCC
E0
2
100n
8
{BCLK_CTL_SERVICE,TX1P,RX1P,RTS1P,CTS1P}
2202
M24C64
1
1K5
7201
3212
100MHZ
1K5
I265
3201
5207
2204
+3V3
C
RSTN_DVIO
EMPRESS_BOOT
RSTN_BE
I2C BUS
13
DCU
connector
7
6
PIO2-6
PIO2-7
A
12
5211
9
100n
8
100n
7
2228
6
100n
5
CPUINT1
4
AE_ACLK_OEn
IRQ2
3
2K2
2201
2
F250
3211
1
VDD-PCM
48
VSS-PCM
49
1
GNDD
I251
VDD_PCM
D
GNDD
E
SYSTEM CONTROL
I270
F
3208
148
147
146
145
144
143
142
141
CPU-DATA7
CPU-DATA6
CPU-DATA5
CPU-DATA4
CPU-DATA3
CPU-DATA2
CPU-DATA1
138
130
128
129
139
140
134
133
132
CPU-RAS1
135
117
118
SYSTEM
USE
MEMORY interface
PORT 0 I/O
PORT 1 I/O
PORT 2 I/O
PORT 3 I/O
PORT 4 I/O
IRQ
JTAG
VDD-PLL
122
VSS-PLL
123
I252
VDD_PLL
I202
GNDD
DAC-PCMOUT1
53
DAC-PCMOUT2
54
I218
CPU-DATA0
CPU-RW
CPU-BE0
CPU-BE1
CPU-CAS0
CPU-CAS1
CPU-CE1
CPU-CE2
CPU-CE3
AC3
LPCM
MPEG1/2
uP ST20cpu
AUDIO
DECODER
I211
I254
I255
I256
I257
I258
DAC-SCLK
DAC-PCMOUT0
DAC-PCMCLK
DAC-LRCLK
SPDIF-OUT
51
52
55
56
57
ADC-SCLK
ADC-LRCLK
ADC-DATA
ADC-PCMCLK
103
104
105
106
E
3227
3203
3228
22R
22R
22R
3204
100R
CSn
CPU-CE0
CPU-OE
CPU-PROCLK
KARAOKE
22R
I210
I212
I213
I217
5
6
7
8
3234-D 4
3234-C 3
3234-B 2
3234-A 1
4K7
4K7
4K7
4K7
GNDD
A/V/Sub
MPEG
DECODER
Video
demultiplexer
R-OUT
G-OUT
B-OUT
VIDEO
ENCODER
C-OUT
CV-OUT
Y-OUT
OPTION
1
2
3
4
5
6
7
8
PWM2
PWM0
PIX-CLK
V-REF-YC
V-REF-RG
I-REF-YC
I-REF-RG
120
35
28
36
29
ANA_WE
H
I227
1%
100n
13K
3K9
1%
100MHZ
2229
3230
3231
I226
I223
13K
+5V
3K9
GNDD
7202-B
74HCT125D
1%
14
5
3207
MUTEN_LV
10K
I225
VDD_125
5208
3229
SYSCLK_VSM_5508
5508_HS
5508_odd_even
VDD_YCC
11
13
6
MUTEN
7
4
GNDD GNDD
GNDD
GNDD
9
14
12
7
3232
VSS-YCC
31
116
VSS-RGB
24
114
I222
VDD-YCC
I219
1%
VDD_RGB
ANA_WE_LV
GNDD GNDD
I221
VDD-RGB
30
VSS15
23
VDD2-58
199
171
VSS13
2226
100n
GNDD
GNDD
4u7
VDD_CORE
OUT
2218
GND
100n
IN
198
VSS11
VDD2-57
150
2225
100n
GNDD
2224
100n
GNDD
2223
100n
GNDD
2222
100n
GNDD
2221
100n
GNDD
100MHZ
2219
+3V3
7204
LF25C
2227
100n
GNDD
I220
VDD2-56
149
172
VSS9
121
VSS7
96
VDD2-55
94
119
VSS5
VDD2-54
65
VSS3
VDD2-53
64
VDD2-52
37
38
VSS2
15
2220
100n
GNDD
4u7
GNDD
SDRAM Interface
I230
I228
I232
I245
I246
I253
I259
I231
3235
2217
100n
GNDD
2216
100n
GNDD
2215
100n
GNDD
2214
100n
GNDD
2213
100n
GNDD
2212
100n
GNDD
2211
100n
GNDD
1R
VDD2-51
SMI-CS0
SMI-CS1
SMI-CAS
SMI-RAS
SMI-WE
SMI-CLKIN
SMI-CLKOUT
SMI-DQML
SMI-DQMU
74
75
77
76
78
82
95
79
80
14
SMI-DATA6
SMI-DATA7
SMI-DATA8
SMI-DATA9
SMI-DATA10
SMI-DATA11
SMI-DATA12
SMI-DATA13
SMI-DATA14
SMI-DATA15
SMI-DATA0
SMI-DATA1
SMI-DATA2
SMI-DATA3
SMI-DATA4
SMI-DATA5
7202-D
74HCT125D
5206 I271
VDD_STI
I
G
VDD_125
84
85
86
87
88
89
90
91
92
93
97
98
99
100
101
102
SMI-ADR9
SMI-ADR10
SMI-ADR11
SMI-ADR12
SMI-ADR13
185
SMI-ADR0
SMI-ADR1
SMI-ADR2
SMI-ADR3
SMI-ADR4
SMI-ADR5
SMI-ADR6
SMI-ADR7
SMI-ADR8
VSS14
184
69
68
67
66
58
59
60
61
62
63
70
71
72
73
VSS12
VDD3-37
160
VSS10
VDD3-36
159
136
137
VSS8
VDD3-35
108
VSS6
83
VDD3-34
VDD3-33
81
107
VDD3-32
VSS4
50
VSS1
ADDRESS
100MHZ
2203
+3V3
I244
I260
I261
I262
I263
I216
I224
27
26
25
33
34
32
SDRAM CONTROLLER
DATA
H
5200
VIDEO_OUT
Subpicture
decoder
Subpicture
2
IS
47
Audio / Video
decoder
VDD3-31
B-DATA
B-WCLK
B-BCLK
B-FLAG
B-SYNC
B-V4
NRSS-OUT
5
I233
16
20
17
18
19
21
22
4
BE_DATA_RD
BE_WCLK
BE_BCLK
BE_FLAG
BE_SYNC
BE_V4
FRONT-END
Interface
BE_SERIAL
G
F
Audio
10
11
12
13
CL 16532145_023.eps
211101
14
I
1200
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234-A
3234-B
3234-C
3234-D
3235
3236-A
3236-B
3236-C
3236-D
3237-A
3237-B
3237-C
3237-D
3238
3239
3240
3241
3242
3243
3244
3245
5200
5201
5202
5203
5204
5205
5206
A11
C5
C11
A3
I2
B4
B13
B13
B5
B13
B12
B14
H3
H3
H3
H3
H4
H4
H4
I10
I9
H8
H9
H9
H9
H10
H10
H10
H10
B12
H13
B13
A10
C5
A4
C12
E13
E13
B4
B4
I13
F1
A8
C11
A5
C6
C6
B10
B8
C7
C7
B11
B10
B6
B6
C7
C12
C12
C8
E13
E13
H12
H12
I12
I12
B6
F13
F13
F13
F13
H8
C10
C10
C10
C10
C10
C10
C10
C10
B9
C9
B9
C9
B9
C9
B9
C9
H2
A13
A13
B13
B13
B14
I9
5207
5208
5209
5210
5211
5212
7200
7201
7202-A
7202-B
7202-D
7203
7204
F214
F247
F248
F249
F250
F264
F265
A2
H13
A13
A14
A13
A13
C2
A2
C13
I14
G14
B14
I9
C11
C10
C10
C11
C11
C6
A11
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 141
Digital Board: AV Decoder Memory
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GNDD
I301
5302
4u7
19 CS_
2304
4u7
2305
38 CLK
100MHZ
16 WE_
B
17 CAS_
2306
GNDD
18 RAS_
2307
GNDD
REFRESH
COUNTER
+3V3
100MHZ
MODE REG
NC
E
VDD_FLASH_L
VSS1
VSS1
F
ROMH_CEn
VSS2
ROML_CEn
VDD_FLASH_H
27 46
FLASH 1
20 BA0
24 A1
BANK
CTRL
LOGIC
31 A6
32 A7
ADDRESS REGISTER
25 A2
30 A5
33 A8
100n
100n
100n
2302
2300
2301
2303
2310
DQML 15
DQMH 39
B
DQ0 2
BANK0
MEMORY
ARRAY
(4,096x256x16)
SENSE AMPLIFIERS
23 A0
29 A4
VDDQ
ROW
ADDR
MUX
21 BA1
26 A3
GNDD
DQML DQMH
I/O GATING
DQM DATA LOGIC
READ DATA LATCH
WRITE DRIVERS
DQ1 4
DQ2 5
DQ3 7
DQ4 8
DQ5 10
DQ6 11
C
DQ7 13
DQ8 42
COLUMN
ADDR
COUNTER/
LATCH
DQ9 44
COLUMN
DEDCODER
34 A9
22 A10
DQ10 45
DQ11 47
DQ12 48
DQ13 50
D
DQ14 51
DQ15 53
35 A11
VSSQ
6
12 46 52
VSS
28 41 54
NC
36 40
GNDD
SDRAM
E
NC
D
100n
7301
GNDD
M29W160DT 37
29
25
VCC
DQ0
A0
31
24
DQ1
A1
23
33
A2
DQ2
35
22
DQ3
A3
38
21
DQ4
A4
40
20
DQ5
A5
42
19
DQ6
A6
44
18
DQ7
A7
30
8
DQ8
A8
32
7
DQ9
A9
34
6
DQ10
A10
36
5
DQ11
A11
39
4
DQ12
A12
41
3
DQ13
A13
43
2
DQ14
A14
45
1
DQ15|A-1
A15
48
A16
17
A17
16
A18
14
9
A19
15
13
RB_
26
E_
10
I303 28
G_
11
W_
12
RP_
47
BYTE_
43 49
27 46
FLASH 2
GNDD
F
VSS2
C
100n
7302
GNDD
M29W160DT
37
25
29
VCC
A0
DQ0
24
31
A1
DQ1
23
33
A2
DQ2
22
35
A3
DQ3
21
38
A4
DQ4
40
20
A5
DQ5
42
19
DQ6
A6
44
18
DQ7
A7
30
8
DQ8
A8
32
7
DQ9
A9
6
34
A10
DQ10
5
36
A11
DQ11
4
39
A12
DQ12
3
41
A13
DQ13
2
43
A14
DQ14
1
45
A15
DQ15|A-1
48
A16
17
A17
16
A18
14
9
A19
15
13
RB_
26
E_
10
I302 28
G_
11
W_
I304 12
RP_
47
BYTE_
9
BANK0
ROWADDR
LATCH &
DECODER
CTRL
LOGIC
COMMAND
DECODE
5300
+3V3
3
VDD
37 CKE
VDD_STI
14 27
DATA OUTPUT REGISTER
VDD_FLASH_H
VDD_FLASH_L
2309
2308
A
7300
MT48LC4M16A2TG-7E 1
DATA INPUT REGISTER
SYSTEM ADDRESS BUS
4u7
2311
VDD_STI
A
G
100n
I300
100n
SYSTEM DATA BUS
100n
AV Decoder Memory
100n
SDRAM Interface
GNDD
G
SYSTEM CONTROL
{EMI_RWn,FLASH_OEN,EMI_CE2n,EMI_CE3n}
7303-A
74LVC00AD
1
2312
7303-B
74LVC00AD
4
14
3
H
I306
VDD_FLASH_L
VDD_FLASH_L
100n
4300
GNDD
14
6
2
OPTION
I307
H
3300
ROMH_CEn
5
47R
7
I305
I308
7
GNDD
GNDD
VDD_FLASH_L
VDD_FLASH_L
7303-C
74LVC00AD
9
7303-D
74LVC00AD
12
14
11
8
I
4301
14
OPTION
I309
3301
ROML_CEn
13
I
47R
10
7
7
GNDD
GNDD
CL 16532145024.eps
221101
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
3300
3301
4300
4301
5300
5302
7300
7301
7302
7303-A
7303-B
7303-C
7303-D
A14
A14
A14
A13
B8
B6
B6
B9
A13
A13
A13
A11
H7
H8
I8
H9
I9
B5
B8
A11
B8
B6
H6
H7
I6
I7
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 142
Digital Board: Video Encoder, Empress
1
2
3
4
5
7
6
8
9
10
11
12
13
14
D_EMPRESS(15:0)
Video Encoder Empress
SMA(17:0)
SMD(15:0)
4u7
2410
100n
2411
100n
100n
2409
100n
100n
2406
2408
100n
VDD_EMP
2407
VDD_EMP_CORE
2404
GNDD
100n
4u7
GNDD
14
15
16
29
30
31
D
32
35
36
37
38
A1
IO5
A2
IO6
A3
IO7
A4
IO8
A5
IO9
A6
IO10
A7
IO11
A8
IO12
A9
IO13
A10
IO14
A11
IO15
A12
IO16
A13
A14
E
28
NC
A15
A16
GNDD
A17
1
2
3
4
5
18
19
50
52
55
58
60
63
65
68
66
64
61
59
56
54
51
48
104
107
110
112
115
117
120
122
121
118
116
113
111
108
106
103
20
21
22
23
24
25
26
27
42
43
44
VSS
SRAM
F
34 12
GNDD
SD-A0
SD-A1
SD-A2
SD-A3
SD-A4
SD-A5
SD-A6
SD-A7
SD-A8
SD-A9
SD-A10
SD-A11
SD-A12
SD-A13
SD-DQ0
SD-DQ1
SD-DQ2
SD-DQ3
SD-DQ4
SD-DQ5
SD-DQ6
SD-DQ7
SD-DQ8
SD-DQ9
SD-DQ10
SD-DQ11
SD-DQ12
SD-DQ13
SD-DQ14
SD-DQ15
SD-DQ16
SD-DQ17
SD-DQ18
SD-DQ19
SD-DQ20
SD-DQ21
SD-DQ22
SD-DQ23
SD-DQ24
SD-DQ25
SD-DQ26
SD-DQ27
SD-DQ28
SD-DQ29
SD-DQ30
SD-DQ31
SD-CSN
SD-CKE
SD-CLK
SD-CASN
SD-RASN
SD-WEN
SD-DQM0
SD-DQM1
SD-DQM2
SD-DQM3
YUV0
YUV1
YUV2
YUV3
YUV4
YUV5
YUV6
YUV7
MPEG2 VIDEO
3K3
VDD_EMP
3405
36
37
38
40
41
42
43
45
VE_DATA(0)
VE_DATA(1)
VE_DATA(2)
VE_DATA(3)
VE_DATA(4)
VE_DATA(5)
VE_DATA(6)
VE_DATA(7)
35
46
31
32
33
VE_DTACKn
G
I404
I405
VE_DSn
I406
156
10K
3403
EMPRESS_IRQn
I407
EMPRESS_BOOT
VDD_EMP
PDO0
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
IDQ
HSYNC
VSYNC
FID
VCLK1
VCLK2
VDD_EMP_CORE
H-IRF
152
TXD
151
RXD
150
CTSN
149
RTSN
5 DQ2
7 DQ3
8 DQ4
10 DQ5
11 DQ6
13 DQ7
45 DQ10
47 DQ11
48 DQ12
50 DQ13
82
76
74
73
75
71
70
69
102
100
51 DQ14
53 DQ15
EXTCLK
RESETN
1R
WE_ 16
CAS_ 17
VSSCO1
VSSCO2
VSSCO3
VSSCO4
VSSCO5
VSSCO6
BA1 21
A0 23
A1 24
BANK
CTRL
LOGIC
A2 25
COLUMN
ADDR
COUNTER/
LATCH
COLUMN
DEDCODER
D
A3 26
A4 29
A5 30
A6 31
A7 32
A8 33
A9 34
E
A10 22
VSS
NC
40 36
I400
I401
I409 54 41 28
SDRAM
VSSQ
52 46 12
6
GNDD
A_EMPRESS(13:0)
{SD_CLKE,SD_CLK,SD_CSN,SD_WEN,SD_CASN,SD_RASN,SD_DQM0,SD_DQM1}
F
DIGITAL VIDEO(CCIR656)
11
21
22
23
24
30
VIP_IDQ
I414
I415
4406
VIP_HS
VIP_VS
VIP_FID_FF
VIP_ICLK
I2C BUS
I402
3400
3401
SCL
SDA
100R
100R
3408
3409
3410
22R
22R
22R
G
3402
VDD_EMP
10K
AE_DATAI
AE_BCLK
AE_WCLK
AE_DATAO
AE_BCLK_VSM
AE_WCLK_VSM
ACLK_EMP
GNDD
3406
I403
123
3407
147
180R
OPTION
AUDIO ENCODER DATA STREAM BUS
SYSCLK_EMPRESS
H
47R
GNDD
RESETn_VE
2446
JTAG3_TD_VIP_TO_VE
JTAG3_TMS
JTAG3_TCK
JTAG3_TRSTn
1n
GNDD
JTAG_CHAIN3
5404
+3V3
VDD_EMP
VDD_EMP
100MHZ
2431
25
26
77
78
129
130
VSSP1
VSSP2
VSSP3
VSSP4
VSSP5
VSSP6
VSSP7
VSSP8
VSSP9
VSSP10
VSSP11
VSSP12
VSSP13
VSSP14
VSSP15
VSSP16
VSSP17
VSSP18
VSSP19
VSSP20
C
RAS_ 18
A11 35
12
13
14
15
16
17
18
19
134
TDI
135
TMS
136
TCLK
139
TRSTN
TDO
22p
3404
CS_ 19
BA0 20
ROW
ADDR
MUX
I/O GATING
DQM DATA LOGIC
READ DATA LATCH
WRITE DRIVERS
CLK 38
REG MODE
SENSE AMPLIFIERS
DQMH DQML
44 DQ9
127
XTALO
126
XTALI
MPEG2 / AC-3 encoder
GNDD
BANK0
MEMORY
ARRAY
(4,096x256x16)
42 DQ8
6
SDATA2
7
SCLK2
8
SWS2
9
ACLK
1
10
20
34
44
53
62
72
86
96
105
114
124
138
148
157
166
176
190
200
100n
100n
2432
100n
100n
2433
100n
2435
2434
100n
2436
100n
100n
2437
100n
2439
2438
137
CKE 37
CTRL
LOGIC
I416
VDD_EMP_CORE
OUT
4u7
GND
2440
100n
I
IN
2441
100MHZ
2442
+3V3
I408
7404
LF25C
4 DQ1
94
97
99
98
95
93
90
88
85
84
92
87
89
83
2
SDATA1
3
SCLK1
4
SWS1
141
TEST0
142
TEST1
144
TEST2
140
CLKOUT
5403
2 DQ0
146
SCL
145
SDA
47
I2CADDRSEL
PDOVAL
PDIOCLK
PDOAV
PDIDS
PDOSYNC
VDD_EMP
H
39 DQMH
GNDD
2
3
4
5
6
7
8
9
10
11
I
CL 16532145_025.eps
221101
GNDD
1
B
GNDD
OPTION
BANK0
ROWADDR
LATCH &
DECODER
15 DQML
+3V3
2443
205
195
185
171
161
153
143
133
119
109
101
91
81
67
57
49
39
29
5
EMPRESS
206
203
201
199
198
169
167
164
162
159
160
163
165
168
170
202
204
207
1
VDD
DECODE
COMMAND
A0
IO4
27 14
ADDRESS REGISTER
13
IO3
3
COUNTER
REFRESH
C
UB_
40
SM-A0
SM-A1
SM-A2
SM-A3
SM-A4
SM-A5
SM-A6
SM-A7
SM-A8
SM-A9
SM-A10
SM-A11
SM-A12
SM-A13
SM-A14
SM-A15
SM-A16
SM-A17
DATA OUTPUT REGISTER
9
10
IO2
39
9
VDDQ
DATA INPUT REGISTER
8
41
49 43
100MHZ
7402
MT48LC4M16A2TG-7E
4u7
2430
100n
2429
100n
2428
100n
2427
100n
2426
100n
2425
100n
2424
100n
2423
100n
2422
100n
2421
100n
2420
100n
2419
100n
2418
100n
2417
100n
2416
100n
2415
100n
2414
100n
2413
100n
2412
100n
7
LB_
SM-D0
SM-D1
SM-D2
SM-D3
SM-D4
SM-D5
SM-D6
SM-D7
SM-D8
SM-D9
SM-D10
SM-D11
SM-D12
SM-D13
SM-D14
SM-D15
SM-WEN
SM-OEN
SM-CS0_
SM-CS3N
SM-UB_
SM-LB_
182
VSSCO8
125
VSSAOSC
181
VSSCO7
OE_
IO1
194
192
189
187
180
178
175
173
174
177
179
186
188
191
193
196
172
158
208
197
155
154
6
7403
SAA6752HS
VDDP19
VDDP18
VDDP17
VDDP16
VDDP15
VDDP14
VDDP13
VDDP12
VDDP11
VDDP10
VDDP9
VDDP8
VDDP7
VDDP6
VDDP5
VDDP4
VDDP3
VDDP2
VDDP1
CS_
17
183
132
131
80
79
28
27
WE_
5400
I413
VDDCO7
VDDCO6
VDDCO5
VDDCO4
VDDCO3
VDDCO2
VDDCO1
VCC
VDDAOSC
128
VDDCO8
184
B
I412
7401
K6R4016V1CT
33 11
4409
100n
2403
100n
2444
A
+3V3
100MHZ
2402
A
{SM_WEN,SM_OEN,SM_CS0N,SM_CS3N,SM_UBN,SM_LBN}
5402
2405
I410
12
13
14
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2446
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
4406
4409
5400
5402
5403
5404
7401
7402
7403
7404
A1
A1
B11
B11
B11
B11
B11
B11
B11
A12
I13
I13
I13
I12
I12
I12
I12
I12
I12
I12
I11
I11
I11
I11
I11
I11
I11
I10
I10
I10
I3
I3
I3
I3
I3
I3
I3
I2
I2
I2
I2
B13
A1
H9
G9
G9
G13
G4
B13
G4
H10
H9
G8
G8
G8
F13
G12
B12
A2
H1
I10
B2
B12
B8
H2
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 143
Digital Board: VIP CVBS Y/C Video Input
4
5
4u7
100n
VIDEO FIFO
VERTICAL SCALING
HORIZONTAL FINE(PHASE-) SCALING
LINE FIFO BUFFER
TDO
TDI
TRSTN
TCK
TMS
A5
B5
C6
B6
D6
D14
E11
E13
E12
E14
F13
F14
G13
HPD0
HPD1
HPD2
HPD3
HPD4
HPD5
HPD6
HPD7
JTAG3_TD_VIP_TO_VE
2541
4u7
GNDD
+3V3
5
3
IGP1
IGP0
IGPV
IGPH
IDP0
IDP1
IDP2
IDP3
IDP4
IDP5
IDP6
IDP7
ICLK
IDQ
ITRDY
ITRI
K13
L14
K14
K12
G14
G12
H11
H14
H13
J14
J13
K11
M14
L13
N12
L12
ASCLK
ALRCLK
AMCLK
AMXCLK
N11
P12
P11
M12
VSSI
VIP_IGP1
VIP_VS
7502-B
74HC74D 14
2
1
10
6
DIGITAL VIDEO(CCIR656)
VIP_VS
VIP_HS
7
9
D
VIP_FID_FF
11
VIP_VS
12
GNDD
13
+3V3
8
7
GNDD
I551 3505 22R
I525
I527
I530
I531
E
VIP_ICLK
VIP_IDQ
VDD_LVC32
I526
5504
+3V3
100MHZ
GNDD
14
Video Input
processor
7501-A
74LVC32AD
1
3
F
GNDD
2
7
JTAG3_TD_VSM_TO_VIP
JTAG3_TRSTn
JTAG3_TCK
JTAG3_TMS
DV_IN_HS
DV_IN_VS
DV_IN_CLK
GNDD
GNDD
G
JTAG_CHAIN3
10K
3508
I538
DV_IN_DATA(0:7)
2540
100n
100n
100n
100n
100n
100n
B3
E2
G2
J1
L1
M3
K4
H4
F4
D4
C5
C9
D12
H12
M4
M8
M11
C8
C10
F12
J12
M5
SDA M9
SCL P10
INT_A N9
P9
VXDD
VDDA4A
VDDA3A
VDDA2A
VDDA1A
B2
B13
B14
C3
C4
C12
C13
N1
N2
N3
N13
N14
P2
XRDY
XPD0
XPD1
XPD2
XPD3
XPD4
XPD5
XPD6
XPD7
XCLK
XDQ
XRH
XRV
XTRI
A6
A8
B8
A9
B9
A10
B10
A11
C11
A7
B7
C7
D8
B11
DV_IN_DATA(0)
DV_IN_DATA(1)
DV_IN_DATA(2)
DV_IN_DATA(3)
DV_IN_DATA(4)
DV_IN_DATA(5)
DV_IN_DATA(6)
DV_IN_DATA(7)
XTAL
XTALI
XTOUT
A3
B4
A2
I536
I533
GNDD
I552
VDD_LVC32
VDD_LVC32
VIP_RTS1
7501-D
74LVC32AD
12
14
I529
DV_IN_HS
11
14
8
10
13
7
H
7
2K2
VIP_IGP1
7501-C
74LVC32AD
9
3506
VDDE_7118
18p
CX-11F
24M576
I555
1500
18p
2510
3
4
OPTION
2511
1R
3515
I553
GNDD
VSSE
GNDD
1M
100n
VIDEO/TEXT
ARBITER
BOUNDARY
SCAN
H-PORT
4K7
3507
I505
I535
I537
VIP_RTS1
vip_error
5509
3509
2
P3
CBCR
X-PORT
XTAL
GPO
P4
N5
M10
N10
L10
VSSA
2545
GND
EXMCLR
SYNC
VIDEO
CLK
+3V3
OUT
VBI DATA
SLICER
CBCR
S
AOUT
+3V3
+3V3
TEXT
FIFO
RAW
100n
7502-A
74HC74D 14
VIP_INT
100n
S
I501
2512
Y
YCBCR
4501
C
2544
SCL
VDDI
AUDIO
CLK
LUM
PROC
S
100R
+3V3
I2C BUS
D5
D9
D11
G11
L4
L8
L11
D7
D10
F11
J11
L5
L9
Y
S
VDDE
1ST TASK IIC REG MAP SCALER
2ST TASK IIC REG MAP SCALER
BCS-SCALER
CR
COMB
FIL
FIR-PREFILTER
PRESCALER
CB
4u7
100n
100n
100n
100n
100n
100n
100n
2536
2526
2524
2522
2529
2533
2537
VDDI_7118
I504 3501
SCALER EVENT CONTROLLER
YCBCR
CR
CHROM
PROC
C
G
H
Y
CB
COMP
PROC
RAW
GNDD
7503
FXO-31FT 4
VDD
1
TS
OSC
DECODER OUTPUT CONTROL
ANALOG INPUT CONTROL
R
G
B
VDDA
IIC REGISTER MAP
FAST
SWITCH
DELAY
+3V3
100MHZ
GNDD
I507
RES1
RES2
RES3
RES4
RES5
RES6
RES7
RES8
RES9
RES10
RES11
RES12
RES13
N4
P5
P13
D13
C14
A13
B12
A12
CONTROL
C2
L2
A4
M2
J4
H3
E4
C1
I532
M1
AGND
AGNDA
VXSS
VIP ANALOG VIDEO INPUT
GNDD
FSW
A|11
A|12
A|13
A|14
A|1D
A|21
A|22
A|23
A|24
A|2D
A|31
A|32
A|33
A|34
A|3D
A|41
A|42
A|43
A|44
A|4D
ANALOG1 ANALOG1 ANALOG1 ANALOG1
+ ADC1
+ ADC1
+ ADC1
+ ADC1
M13
CVBS_Y_IN_A
J2
K1
CVBS_OUT_B_VIP
CVBS_Y_IN_B
K2
CVBS_Y_IN_C
L3
2501 100n I516 K3
GNDD
C_IN_VIP
G4
2502 100n I517 G3
GNDD
G_IN_VIP
H2
Y_IN_VIP
J3
2503 100n I519 H1
2504 100n I520 E3
GNDD
2505 100n I521 F2
B_IN_VIP
F3
U_IN_VIP
G1
2506 100n I522 F1
2507 100n I523 B1
GNDD
2508 100n I524 D2
R_IN_VIP
D1
V_IN_VIP
E1
2509 100n I528 D3
F
CE
RESON
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
N6
N8
P8
M7
L7
P7
N7
L6
M6
P6
ADP0
ADP1
ADP2
ADP3
ADP4
ADP5
ADP6
ADP7
ADP8
CLKEXT
3503
1K
AD-PORT
5505
100R I500 SDA
I503 3500
GNDD
GNDD
7500
SAA7118E
YCBCRS
4500
I512
E
VDDX_7118
2K2
GNDD
D
GNDD
3502
VDDE_7118
I502
VIP_FB
2542
1n
LLC
LLC2
RST0
RST1
RTCO
3513
680R
150p
2565
RESETn
OPTION
I515
I518
100MHZ
2500
+3V3
100MHZ
2535
2525
2523
2521
2528
2532
5508
+3V3
I506
100n
2520
VDDA4A_7118
GNDD
13
B
GNDD
2515
2519
I543
12
5506
GNDD
4u7
100MHZ
GNDD
GNDD
C
4u7
4u7
100n
GNDD
I514
VDDA3A_7118
2530
5503
+3V3
100n
7
4u7
BAT54 COL
6500
5
VIP_IGP1
7504
BC847B
GNDD
2516
100MHZ
6
B
I511
I513
5502
2513
14
11
A
VDDA2A_7118
2518
3504
680R
7501-B
74LVC32AD
4
I540
GNDD
100MHZ
+3V3
10
+3V3
OUTPUT FORMATTER I-PORT
5501
+3V3
VDD_LVC32
9
5507
100MHZ
2539
2517
I509
+3V3
I510
8
VDDA1A_7118
100n
100n
100n
100n
100n
100MHZ
2514
A
7
I508
5500
+3V3
VDDA_7118
VIP CVBS Y/C Video Input
6
2531
2534
2538
2527
2543
3
100n
2
4u7
1
GNDD
GNDD
GNDD
OPTION
1
GNDD
GNDD
GNDD
CL 16532145_026.eps
221101
2
3
4
5
6
7
8
9
10
11
12
13
1500
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2565
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3513
3515
4500
4501
5500
5501
5502
5503
5504
5505
5506
5507
5508
5509
6500
7500
7501-A
7501-B
7501-C
7501-D
7502-A
7502-B
7503
7504
H3
C4
D2
D2
E2
E2
E2
E2
E2
E2
E2
H3
H4
F11
B3
A5
C3
B5
A4
B3
B3
B4
C7
B7
C7
B7
C7
B7
A6
C7
B7
C5
A6
C8
B7
A6
C7
B7
B7
A6
A6
B7
B8
C4
A6
C11
G2
C1
C7
C7
C3
C1
A1
E8
H7
F3
G5
G3
C2
H3
C2
C7
A4
A3
A4
B3
E11
B8
A8
A6
C4
G2
B1
C3
F11
B2
H7
H6
C10
D11
H2
B1
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 144
Digital Board: Analog Board Cons. Video In / Output
4
5
Analog Board Cons.
Video In / Output
2618 I660
100n
2609
I653
100n
2629
3629
I650
2613
3605
100n
1R
CVBS_Y_IN
180R
I642
3615
CVBS_OUT_B
AE_ACLK
I661
I662
AD_WCLK
I655
2633
3631
100n
1R
3634
2K2
I656
C_IN_VIP
2628
I647
U_IN
AD_DATAO
I666
I638
13
100R
I639
12
11
3637
OPTION
AD_ACLK
I667
10
I640
100R
9
3604
V_IN_VIP
I627
MUTEN
2635 I668
R_IN_VIP
I633
3610
100n
1R
3614
GNDD
2619
+3V3
7
+5V
6
5
I611
4
I613
OPTION
100n
8
I609
100R
GNDD
3633
560R
14
3635
C_IN
180R
100n
C
3630
15
I637
3625
2603
3638
B_IN_VIP
75R
GNDD
16
100R
2614 I663
75R
I644
17
I635
3623
100R
AD_BCLK
I654
19
18
OPTION
AUDIO OUT
100R
-5V_Buffer
GNDD
20
I603
Y_IN
GNDD
U_IN_VIP
21
1p
I652
G_IN_VIP
I645
22
I671
1p
2604
2608
14
I664
AE_WCLK
AE_DATAI
22p
2631
I651
180R
3619
I649
100n
CVBS_OUT_B_VIP
22n
AUDIO ENCODER
DATA STREAM BUS
100n
3636
13
22p
2624
CVBS_Y_IN_C
2632
560R
B
I643
2634
12
22p
2623
+5V_Buffer
100n
GNDD
7602
BC847B
I665
11
100n
CVBS_Y_IN_B
GNDD
10
AE_BCLK
560R
4u7
9
Y_IN_VIP
4u7
+5V
2630
A
8
75R
I629
7
VIP ANALOG VIDEO INPUT
CVBS_Y_IN_A
5606
6
ANALOG BOARD INTERFACE AUDIO IN/OUT
3
3609
2
3632
1
3
V_IN
GNDD
GNDD
GNDD
GNDD
GNDD
A
B
C
2
OPTION
1
1602
VDD_125
VIDEO_OUT
7202-C
74HCT125D
14
GNDD
AD_SPDIF33
9
8
I669
3600
GNDD
I641
{V_IN,U_IN,Y_IN,C_IN,CVBS_Y_IN}
D
56R
7
D
10
GNDD GNDD
+5V_Buffer
1601
+5V_Buffer
I600
V_IN
22
DIVIO
3611
3608
560R
47p
3607
2607
47p
2606
560R
3606
1K
1K
1
-5V_Buffer
UART1
-5V_Buffer
2636
IRESET_DIG
+5V_Buffer
9
2625
VSM_UART1_TX
8
100n
VSM_UART1_CTSn
GNDD
GNDD
100n
7
GNDD
59
7605
BC847B
47p
2621
3621
12u
1%
GNDD
1%
12u
C_OUT_B
1%
GNDD
GNDD
GNDD
1%
IOn
ANA_WE
R_OUT_B
3
4
5
4
3
2
GNDD
GNDD
GNDD
GNDD
GNDD
6
5
I619
VIP_FB
CL 16532145_027.eps
221101
-5V_Buffer
2
6
BE_FAN
-5V_Buffer
1
I616
I617
1
GNDD
GNDD
7604
BC847B
1K
5602
VSM_UART1_RTSn
I625
5604
R_OUT
I626
10
VSM_UART1_RX
2620
VSM_UART2_RX
1600
FMN
I615
4u7
+5V_Buffer
560R
60
I670
5607
-5V
-5V_Buffer
LOAD_DVN
2
I614
B_OUT_B
G
GNDD
GNDD
RESETn_DVIO
C_OUT
I
GNDD
4
I612
G_OUT_B
3
3628
57
GNDD
G_OUT_B
F
GNDD
560R
55
58
GNDD
GNDD
3627
56
I659
GNDD
47p
53
GNDD
2627
54
1%
+12V
47p
51
1%
1%
1%
2626
49
52
+5V
Y_OUT_B
3626
50
3603
AE_WCLK
560R
VSM_UART2_TX
7603
BC847B
12u
5
7601
BC847B
12u
3616
OPTION
I624
5603
Y_OUT
I623
5601
G_OUT
6
I610
R_OUT_B
E
1K
47
7
100n
3613
48
8
I608
C_OUT_B
100n
1K
VSM_UART2_RTSn
9
AE_BCLK
4602
10
GNDD
3624
UART2
Y_OUT_B
GNDD
AE_WCLK_DV
H
12
I607
2615
2610
+3V3
560R
45
560R
+3V3
AE_BCLK_DV
43
13
I606
CVBS_OUT_B
7
8
9
ANALOG BOARD
INTERFACE CONTROL
33
46
14
1K
34
44
15
I605
{R_OUT_B,G_OUT_B,B_OUT_B,C_OUT_B,CVBS_OUT_B,Y_OUT_B}
3618
4601
41
16
+5V_Buffer
VSM_UART2_CTSn
560R
4600
42
C_IN
-5V_Buffer
3617
31
+5V
17
I604
CVBS_Y_IN
GNDD
47p
OPTION
32
+5V
GNDD
2617
OPTION
39
GNDD
4u7
29
40
GNDD
47p
30
37
GNDD
1%
2616
27
35
1%
560R
28
38
CVBS_OUT_B
B_OUT_B
11
25
36
12u
19
18
7606
BC847B
+5V_Buffer
26
AE_DATAI_DV
20
I602
DV_IN_HS
23
+3V3
GNDD
I622
5605
-5V_Buffer
21
+3V3
GNDD
560R
19
47p
20
3602
17
GNDD
3612
18
I646
1%
3622
15
2602
16
1%
47p
13
47p
14
I634
2601
11
24
DV_IN_VS
+3V3
AE_DATAI
12
22
GNDD
G
9
21
I601
U_IN
GNDD
B_OUT
7600
BC847B
12u
2612
I658
7
I631
47p
I657
8
10
I621
5600
2622
3620
F
2K2
DV_IN_CLK
5
100n
Y_IN
47p
I636
6
2605
100n
I628
2611
I632
3
3601
I630
4
2600
GNDD
560R
E
1
560R
I618
1603
84816
2
ANALOG BOARD INTERFACE VIDEO IN/OUT
DV_IN_DATA(0:7)
10
11
12
13
14
H
I
1600
1601
1602
1603
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
4600
4601
4602
5600
5601
5602
5603
5604
5605
5606
5607
H14
D14
C14
E2
E6
E5
E5
C12
C13
E10
E9
E9
A6
A6
G6
G5
G5
A9
B9
F10
G9
G9
A9
C9
H6
I5
I5
C12
C12
H10
I9
I9
C6
A6
A2
C12
A2
B9
B2
C9
H9
D13
E5
E6
F6
B12
A10
E8
E9
F10
A9
C10
G5
G6
H6
C9
B3
G8
G9
G10
B2
F1
I5
I6
A12
I6
A12
I8
I9
I10
A6
C6
B10
B6
C6
B9
B12
B2
B12
B3
G3
G1
G3
E5
G9
I5
G5
I9
E9
A2
H9
7202-C
7600
7601
7602
7603
7604
7605
7606
D12
E6
G10
B3
G6
I10
I6
E10
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 145
Digital Board: Progressive Scan
1
2
3
4
5
6
7
8
9
10
11
12
13
Progressive Scan
A
A
I712
OPTION
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
2719
2717
2712
2711
2727
2710
2709
2706
2705
2704
2703
2702
2700
47u
GNDD
4u7
2720
I705
I704
113
112
TESTO2
TESTO1
41
50
109
111
167
151
144
137
123
114
105
95
84
73
63
51
TEST3
TEST2
TEST1
TEST0
VDD33-13
VDD33-12
VDD33-11
VDD33-10
VDD33-9
VDD33-8
VDD33-7
VDD33-6
VDD33-5
VDD33-4
1
158
33
VDD33-3
VDD33-2
VDD33-1
54
42
16
107
VDD25-4
VDD25-3
TEST4
OUTPUT SIGNALS
DADDR0
DADDR1
MODE
SIGNALS
DATA0
DATA1
SDA
SCL
PIXCLK
DATA2
POWER GND
DATA3
N|P|IN|OUT
NOMEM
DATA4
Cr_OUT(0)
Cr_OUT(1)
Cr_OUT(2)
Cr_OUT(3)
Cr_OUT(4)
Cr_OUT(5)
Cr_OUT(6)
Cr_OUT(7)
Cr_OUT(8)
Cr_OUT(9)
88
87
86
83
82
81
80
79
78
77
C
Yy_OUT(0)
Yy_OUT(1)
Yy_OUT(2)
Yy_OUT(3)
Yy_OUT(4)
Yy_OUT(5)
Yy_OUT(6)
Yy_OUT(7)
Yy_OUT(8)
Yy_OUT(9)
76
75
72
71
70
69
68
67
66
65
Yy_OUT(9:0)
D
Cb_OUT(0)
Cb_OUT(1)
Cb_OUT(2)
Cb_OUT(3)
Cb_OUT(4)
Cb_OUT(5)
Cb_OUT(6)
Cb_OUT(7)
Cb_OUT(8)
Cb_OUT(9)
104
103
102
101
100
99
98
97
94
93
116
Cb_OUT(9:0)
E
I703
117
89
90
91
92
108
I708
I707
110
VSOUT
HSOUT
49
53
58
57
56
61
60
59
I717
I719
I718
I725
I722
I721
I720
3702-B 7
3701-A 8
3702-D 5
3702-C 6
3701-D 5
3701-C 6
3701-B 7
I723
I724
3705
3706
2
1
4
3
4
3
2
4K7
4K7
4K7
4K7
4K7
4K7
4K7
45
RESETn
+3V3_FLI
+3V3_FLI
+3V3_FLI
+3V3_FLI
+3V3_FLI
GNDD
+3V3_FLI
2714
1n
GNDD
47
48
100R
100R
40
GNDD
SDA
SCL
I2C BUS
SYSCLK_PROGSCAN
62
I716
52
3702-A 8
1 4K7
+3V3_FLI
VSS17
+3V3_FLI
G
+3V3_FLI
3714
4K7
4K7
I727
3708
4K7
I726
4K7
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
GNDD
3715-D
3715-C
3715-B
3715-A
3716-D
3716-C
3716-B
3716-A
3717-D
3717-C
3717-B
3717-A
3718-D
3718-C
3718-B
3718-A
3719-D
3719-C
3719-B
3719-A
H
3700
I713
BA
3707
43
DATA9
VSS16
DATA8
AVSS
DATA7
CAS
OPTION
H
OPTION
GNDD
D_DATA(10)
D_DATA(11)
D_DATA(12)
D_DATA(13)
D_DATA(14)
D_DATA(15)
D_DATA(16)
D_DATA(17)
D_DATA(18)
D_DATA(19)
D_DATA(20)
D_DATA(21)
D_DATA(22)
D_DATA(23)
D_DATA(24)
D_DATA(25)
D_DATA(26)
D_DATA(27)
D_DATA(28)
D_DATA(29)
GNDD
DATA BUS
I
CL 16532145_028.eps
221101
1
2
3
4
5
6
F
44
46
DATA6
RAS
I
Cr_OUT(9:0)
DATA5
168
150
BSEL
159
149
CASN
OFORMAT2
152
148
RASN
OFORMAT1
VSS15
147
IFORMAT2
OFORMAT0
VSS14
146
IFORMAT1
CONTROL
SIGNALS
INTERFACE
WEN
VSS13
143
ADDR10
MEMCLKO
VSS12
142
OE
IFORMAT0
145
141
RESETB
ADDR9
138
140
ADDR8
132
122
139
SDRAM
ADDR7
VSS11
121
ADDR6
124
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
FILM
VSS10
2
1
4
3
2
1
4
3
2
1
B|CBOUT7
ADDR5
VSS9
7
8
5
6
7
8
5
6
7
8
120
B|CBOUT6
FSYNC
VSS8
3710-B
3710-A
3711-D
3711-C
3711-B
3711-A
3713-D
3713-C
3713-B
3713-A
119
B|CBOUT5
ADDR4
96
33R
33R
33R
33R
B|CBOUT4
HREFO
85
4
3
2
1
B|CBOUT3
B|CBOUT9
115
5
6
7
8
B|CBOUT2
H|CSYNCO
153
WE
118
3703-D
3703-C
3703-B
3703-A
B|CBOUT1
B|CBOUT8
106
GNDD
126
B|CBOUT0
VSYNC|CREFO
VSS7
G
10p
OPTION
2707
33R
127
G|YOUT9
ADDR3
VSS6
D_DATA(0)
D_DATA(1)
D_DATA(2)
D_DATA(3)
D_DATA(4)
D_DATA(5)
D_DATA(6)
D_DATA(7)
D_DATA(8)
D_DATA(9)
128
125
33R
I714
129
G|YOUT8
ADDR2
74
3712
130
G|YOUT7
ADDR1
64
I715
CLK4
131
VSS5
CONTROL BUS
133
G|YOUT6
YCLKO
VSS4
ADDRESS BUS
F
134
G|YOUT5
VREFO
VSS3
GNDD
135
G|YOUT4
ADDR0
34
GNDD
7
136
VSS2
GNDD
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
G|YOUT3
CCLKO
2
4702
3
4
1
2
3
4
1
2
3
4
G|YOUT2
FIELDIN
17
I702
3710-C 6
3710-D 5
3709-A 8
3709-B 7
3709-C 6
3709-D 5
3704-A 8
3704-B 7
3704-C 6
3704-D 5
3720
VSYNCREFI
VSS1
6
D_ADDR(0)
D_ADDR(1)
D_ADDR(2)
D_ADDR(3)
D_ADDR(4)
D_ADDR(5)
D_ADDR(6)
D_ADDR(7)
D_ADDR(8)
D_ADDR(9)
D_ADDR(10)
G|YOUT1
LINE DOUBLER
HSYNCREFI
176
5
OPTION
1
4
B|CBIN9
DATA29
VS_IN
B|CBIN8
DATA28
3
I701
B|CBIN7
175
3
B|CBIN6
DATA27
GNDD
14
DEINTERLACER
B|CBIN5
174
+3V3
15
7
2
5508_odd_even
GNDD
2
5
3
5508_HS
14
B|CBIN4
DATA26
+3V3
4
13
B|CBIN3
173
E
12
100n
7702-A
100n
74LVC86ADB
1
14
GNDD
B|CBIN2
DATA25
2721
B|CBIN1
DATA24
2722
+3V3
7701-A
74HC74D
11
B|CBIN0
DATA23
9
10
G|YIN9
172
8
+3V3
G|YIN8
171
7
G|YIN7
170
6
G|YIN6
169
27
G|YIN5
DATA22
26
G|YIN3
G|YIN4
G|YOUT0
DATA19
25
G|YIN2
R|CROUT9
DATA21
24
R|CROUT8
DATA20
22
23
G|YIN1
164
21
G|YIN0
163
D
20
R|CROUT7
166
GNDD
GNDD
19
R|CRIN9
165
GNDD
GNDD
I728
I729
I730
I731
I732
I733
I734
I735
R|CROUT6
DATA18
P_SCAN_YUV(0)
P_SCAN_YUV(1)
P_SCAN_YUV(2)
P_SCAN_YUV(3)
P_SCAN_YUV(4)
P_SCAN_YUV(5)
P_SCAN_YUV(6)
P_SCAN_YUV(7)
R|CROUT5
DATA17
GNDD
7
P_SCAN_YUV(7:0)
R|CROUT4
162
18
7
8
R|CROUT3
R|CRIN8
161
13
+3V3
AVDD
GNDD
R|CROUT2
R|CRIN7
INPUT SIGNALS
12
TEST
OUTPUT
R|CRIN6
DATA16
39
DATA15
38
R|CRIN5
DATA14
37
TEST
INPUT
POWER
SUPPLY
R|CRIN4
DATA13
36
11
13
R|CROUT1
R|CRIN3
160
14
11
R|CROUT0
R|CRIN2
DATA12
9
35
GNDD
R|CRIN1
157
10
+3V3
7702-D
74LVC86ADB
12
32
DATA11
14
R|CRIN0
156
31
DATA10
C
30
155
29
+3V3
154
28
VDD25-2
GNDD
+3V3
VDD25-1
FLI2200
GNDD
B
GNDD
7700
7701-B
74HC74D
5700
+3V3
I706
100n
GNDD
GNDD
47u
GNDD
2716
GNDD
GNDD
2715
4u7
B
I700
+3V3_FLI
+2V5_FLI
5702 I710
+2V5_PLL
55
2723
100n
+3V3
+2V5_FLI
OUT
2
100n
2724
4701
GND
I711
5701
3
IN
2726
1
4u7
I709
100n
100n
100n
100n
7703
LF25C
2725
+5V
2718
2713
2708
2701
+2V5_PLL
4700
7
8
9
10
11
12
13
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
3700
3701-A
3701-B
3701-C
3701-D
3702-A
3702-B
3702-C
3702-D
3703-A
3703-B
3703-C
3703-D
3704-A
3704-B
3704-C
3704-D
3705
3706
3707
3708
3709-A
3709-B
3709-C
3709-D
3710-A
3710-B
3710-C
3710-D
3711-A
3711-B
3711-C
3711-D
3712
3713-A
3713-B
3713-C
3713-D
3714
3715-A
3715-B
3715-C
3715-D
3716-A
3716-B
3716-C
3716-D
3717-A
3717-B
3717-C
3717-D
3718-A
3718-B
3718-C
3718-D
B9
B8
B9
B9
B9
B8
B8
G3
B8
B8
B8
B8
B8
B8
F13
B6
B7
B8
B8
B8
B11
E2
E3
B3
B2
B2
B3
B8
G11
F11
F11
F11
F11
G11
F11
F11
F11
F6
F6
F6
F6
F6
F6
F6
F6
G11
G11
H11
H11
E6
E6
F6
F6
G6
G6
E6
E6
G6
G6
G6
G6
F3
G6
G6
G6
G6
G11
H7
H7
H7
H7
H8
H8
H8
H7
H8
H8
H8
H8
H8
H8
H8
H8
3719-A
3719-B
3719-C
3719-D
3720
4700
4701
4702
5700
5701
5702
7700
7701-A
7701-B
7702-A
7702-D
7703
H9
H8
H8
H8
F6
A1
B1
E2
B11
A3
B6
B7
E1
C1
E3
C3
A2
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 146
Digital Board: Progressive Scan
1800
2800
2802
2803
2804
2805
D15
B14
B2
B2
B2
B2
2806
2807
2808
2809
2810
2811
B3
B3
B2
B3
B3
B3
1
2812
2813
2814
2815
2816
2817
B3
B3
C11
C12
C12
F12
2
2818
2819
2820
2821
2822
2823
3
C7
C8
C9
C14
C9
C9
2824
2826
2827
2828
2829
2831
4
C14
D11
D12
D12
D14
E11
2832
2833
2834
2835
2836
2837
5
E12
E12
F14
F10
G10
B8
3800
3801
3802
3803
3804
3805
6
G4
C14
B8
C13
C13
C8
3806
3807
3808
3809
3810
3811
7
B8
C14
C14
D10
D6
D11
3812
3813
3814
3815
3816
3817
8
D14
D13
D13
E10
D14
E11
9
3818
3819
3820
3821
3822
3823
E14
E14
E10
E13
E13
F11
10
3824
3825
3826
3827
3828
5800
F14
F14
F11
F11
G4
B12
11
5801
5802
5803
5804
5805
5806
B12
B12
D12
D12
D12
E12
12
5807
5808
5809
5810
7800
7801
13
E12
E12
F12
B8
B1
C6
7802
B14
7803-A D14
7803-B E14
14
15
Progressive Scan
A
A
D_ADDR(7)
64
D_ADDR(8)
65
D_ADDR(9)
66
D_ADDR(10)
24
14
21
30
57
69
70
73
DQ18
A5
DQ19
A6
DQ20
A7
DQ21
DQ22
A8
A9
DQ23
A10
DQ24
DQ25
NC1
DQ26
NC2
DQ27
NC3
DQ28
NC4
DQ29
NC5
DQ30
NC6
DQ31
Cr_OUT(9:0)
40 D_DATA(28)
I830
6 Y4
Yy_OUT(5)
I831
7 Y5
Yy_OUT(6)
I832
8 Y6
I833
9 Y7
Yy_OUT(8)
I834
10 Y8
&
Yy_OUT(9)
I835
11 Y9
GAMMA
Cr_OUT(0)
I846
14 CR0
45 D_DATA(21)
Cr_OUT(1)
I803
15 CR1
Cr_OUT(2)
I805
16 CR2
47 D_DATA(20)
Cr_OUT(3)
I815
17 CR3
48 D_DATA(19)
50 D_DATA(18)
Cr_OUT(4)
I816
18 CR4
Cr_OUT(5)
I817
19 CR5
Cr_OUT(6)
I847
20 CR6
Cr_OUT(7)
I848
21 CR7
Cr_OUT(8)
I849
22 CR8
Cr_OUT(9)
I850
23 CR9
51 D_DATA(17)
53 D_DATA(16)
I851
I852
11-BIT
SYNC
DAC
2821
GNDD
1800
FMN
3
8
11-BIT
DAC
2X
INTERPOLATION
DELAY
CHROMA
4:2:2 TO 4:4:4
( 99AF )
DAC-A|Y 34
3815
GNDD
GNDD
GNDD
I809
3817
GNDD
I880
1K2
3816
1K
3818
3820
1K2
3823
CHROMA
4:2:2 TO 4:4:4
( 99AF )
VREF 39
RSET 38
I883
I813
COMP 37
6
7
5806
5807
5808
6u8
10u
2u2
GNDD
1K2
+5V
I881
I810
5
8
2835 GNDD
I811
75R
3824
GNDD
+3V3_ANA
GNDD
5809
GNDD
I818
GNDD
GNDD
3827
2K2
270R
OPTION
F
GNDD
GNDD
GNDD
GNDD
I884
2836
+3V3_ANA
100n
GND
13 52
Cb_OUT(9)I845
Cb_OUT(8)I844
Cb_OUT(7)I843
Cb_OUT(6)I842
Cb_OUT(5)I841
Cb_OUT(4)I840
Cb_OUT(3)I839
Cb_OUT(2)I838
Cb_OUT(1)I837
Cb_OUT(0)I820
Cb_OUT(9:0)
G
AGND
26 33
GNDD GNDD GNDD GNDD
DENC
H
CL 16532145_029.eps
221101
1
2
3
4
5
6
E
I823
1K
+3V3
100n
3826
1K
3825
D
3819
4
I882
GNDD
GNDD
GNDD
7803-B
AD8062
7
6
GNDD
1K2
DAC
CTRL
BLOCK
5
OPTION
DAC-C 32
I812
3
4
4
GNDD
2
1K
GNDD
11-BIT
DAC
I822
3812
2
I808
DAC-B 36
I807
75R
I879
GNDD
1
220p
2u2
7803-A
AD8062
1
1K2
GNDD
H
GNDD
2829
10u
GNDD
CGMS
MACROVISION
CORRECTION
220p
1K2
1K2
3803
3804
18p
2816
22p
8p2
2814
100n
2820
2822 100n
100n
4K7
2819
3805
I875
2815
+3V3_ANA
4u7
2837
SDA
100R
3802
I874
I873
+3V3_ANA
6u8
I806
GNDD
LUMA
99 AF
PATTERN
GENERATOR
&
GNDD
1K2
TEST-
Yy_OUT(7)
42 D_DATA(29)
3811
5 Y3
Yy_OUT(4)
39 D_DATA(27)
GNDD
5805
3814
Yy_OUT(3)
SHARPNESS
FILTER CTRL
&
ADAPTIVE
FILTER CTRL
51 50 49 48 47 46 45 44 43 42
GNDD
3809
5804
1K2
4 Y2
I829
1K
GNDD
5803
18p
3 Y1
37 D_DATA(26)
VSS
100R
3806
SCL
36 D_DATA(25)
12 32 38 46 52 78 84 44 58 72 86
1n
2818
I827
33 D_DATA(23)
NC7
6
2824
C
OPTION
100n
SYNC
GEN
2 Y0
I828
D_DATA(8)
34 D_DATA(24)
I826
Yy_OUT(2)
31 D_DATA(22)
56
1K
3808
TIMING
GENERATOR
25 CLKIN
Yy_OUT(1)
D_DATA(9)
54
3807
+5V
ANALOG BOARD
A4
VSSQ
G
DQ17
GNDD
GNDD
220p
63
DQ16
I878
75R
2834
62
SDRAM
I877
GNDD
I821
3801
2
1K2
61
D_ADDR(5)
A3
GNDD
3822
D_ADDR(4)
A2
GNDD
3813
60
DQ15
GNDD
VAA
VDD
1K2
D_ADDR(3)
A1
Yy_OUT(0)
82 D_DATA(10)
85
SDA ALSB
GNDD
7802
AD8061
I802
1
4
1K2
80 D_DATA(11)
83
SCL
5
2
I C MPU PORT
3821
27
DQ14
3
GNDD
GNDD
24 35
12
1
2828
D_ADDR(2)
DQ13
A0
31
18p
26
GNDD
41
30
2833
25
D_ADDR(1)
10K
SYSCLK_PROGSCAN
79 D_DATA(12)
I801
47u
D_ADDR(0)
DQ12
Yy_OUT(9:0) +3V3_DD
77 D_DATA(13)
2u2
22p
I814 23
BA1
GNDD
D_ADDR(6)
F
DQ11
BA0
27 DV|CLKOUT
10u
2817
E
GNDD
22
3810
6u8
2827
ADDRESS BUS
I836
28 VSYNC_|TSYNC_
5802
22p
DQ10
BA
D
I825
VSOUT
76 D_DATA(14)
29 HSYNC_|SYNC_
5801
2832
DQM3
RESET
I824
HSOUT
74 D_DATA(15)
5800
8p2
DQ9
D_DATA(7)
GNDD
2826
DQM2
13
40
I800
I876
8p2
DQ8
D_DATA(6)
B
2800
I872
100n
2831
DQ7
DQM1
11
7801
ADV7196A
CB|CR9
DQM0
D_DATA(5)
CB|CR8
DQ6
D_DATA(4)
10
I871
GNDD
2823 100n
2813 100n
2811 100n
2812 100n
2810 100n
2809 100n
DQ5
RAS_
8
CB|CR7
59
DQ4
D_DATA(3)
CB|CR6
28
DQ3
D_DATA(2)
7
CB|CR5
71
WE_
CAS_
5
CB|CR4
16
DQ2
RESETn
CB|CR3
19
CS_
D_DATA(1)
CB|CR2
RAS I870
DQ1
D_DATA(0)
4
CB|CR1
18
CLK
2
CB|CR0
CAS I869
DQ0
10K
17
VSS
10K
20
WE I868
VDDQ
CKE
+5V
+3V3_DD
I2C BUS
GNDD
3800
C
68
I819
5810
+3V3
3828
GNDD
67
2806 100n
43 29 15 1
CONTROL BUS
+3V3_FLI
CLK4
2805 100n
3
2808 100n
81 75 55 49 41 35 9
2802 100n
2804 100n
GNDD
7800
MT48LC2M32B2TG
2807 100n
B
2803 100n
DATA BUS
+3V3_FLI
7
8
9
10
11
12
13
14
15
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 147
Digital Board: Power, Clock, and Reset Audio Clock
2
3
4
5
6
7
8
9
11
10
12
Power, Clock and Reset - AudioClock
I900
VDD5_MK2703
100n 2908
3
4
OUTPUT CLK 5
BUFFER
CLK SYNTHESIS
AND CTRL CIRC.
3
7901
BC847B
2
CRYSTAL
OSC
8 X2
I907
I901
3901 I902
GND
OUTPUT 27M 4
BUFFER
7902
NCP303
acc_aclk_pll
6900
22R
I909
I904
BAT54 COL
2916
3
2
4
I932
INP
OUTP 1 I912
NC RESET
100n
5901
GNDD
+5V
7
I906
9
100MHZ
10
2903
CD GND
5
8
BLM31
IOn
RESETn
GNDD
3
-5V
11
I908
100n
GNDD
B
12
GNDD
100n
GNDD
+3V3
GNDD
I913
7702-B
74LVC86ADB
4
RSTN_BE
C
6
3914
C
RESETn_BE
47R
7
7904-E
74LVC04A
14
11
VCC3_CLK_BUF
14
5
VCC3_CLK_BUF
10
GNDD
GNDD
7
7904-A
74LVC04A
14
1
GNDD
GNDD
2
+3V3
D
7
GNDD
A
2904
22n
GNDD
6
2902
IRESET_DIG
1 X1
1
5
100n
GNDD
4K7
PLL
6 S1
I903
2
VDD
3925
7 S0
47K
3902
2
+12V
7900
MK2703S
1K5
3900
+3V3
100K
3903
1
2901
GNDD
GNDD
7702-C
74LVC86ADB
9
VCC3_CLK_BUF
7904-C
74LVC04A
6
SYSCLK_VSM_5508
GNDD
GNDD
14
OPTION
12
13
RESETn_DVIO
47R
7
47R
7
7904-F
74LVC04A
3906
3915
GNDD
E
1K
5
10
I917
3907
I915
VCC3_CLK_BUF
I916
14
8
RSTN_DVIO
14
E
I905
100n
GNDD
GNDD
D
BLM31
+3V3
GNDD
I911
5900
1900
PH
100MHZ
2900
GNDD
10K
4u7 2907
100n
+3V3
SEL_ACLK1
B
+3V3
2906
100MHZ
+5V
A
I931
3924
5903
13
POWER SUPPLY
1
7
GNDD
GNDD
GNDD
VCC3_CLK_BUF
PH-S
7904-B
74LVC04A
14
4
3
I930
VCC3_CLK_BUF
3908
I920
+5V
SYSCLK_PROGSCAN
OPTION
+5V
+5V
7905-E
74HCT14D
7905-F
74HCT14D
11
12
I921
2
13
7
GNDD
GNDD
1n5
I922
5
10K
+5V
9
8
22R
7
GND
GNDD
2
GNDD
GNDD
I923
3917
I926
14
3
I927
4
8
I
1903
1904
1905
1902
GNDD
GNDD
GNDD
GNDD
I928
3921 F935
10K
7
4
GNDD
1901-6
3922
3923
-5V
GNDD
GNDD
2912
1n5
9
1907
Hole 4.0 mm with Cu
1901-4
F934
7905-D
74HCT14D
GNDD
1906
Hole 4.0 mm with Cu
3919
100R
+5V
14
OPTION
3
GNDD
100K
GNDD
SYSCLK_EMPRESS
22R
6K8
7905-B
74HCT14D
7
I924
1K
3920
3
14
3912
OUT
3918
7904-D
74LVC04A
I933
100n
2911
H
VCC3_CLK_BUF
7906
FXO-31FT 4
VDD
1
TS
OSC
100K
+5V
3913
3916
-5V
1
GNDD
1901-3
3911 F933
7
VDD5_OSC
2909
100R
14
6
22R
3904
GNDD
5
GNDD
1901-1
F932
7905-C
74HCT14D
GNDD
GNDD
3910
+5V
7
G
F
2
1901-5
14
1
GNDD
7
I925
7
1901-2
7905-A
74HCT14D
14
10
GNDD
5905
F931
+5V
GNDD
14
+5V
1901-7
100MHZ
{BCLK_CTL_SERVICE,TX1P,RX1P,RTS1P,CTS1P}
22R
7
100n 2915
4u7 2914
100MHZ
I919
1K
5907
3909
+3V3
I918
6K8
SERVICE CONNECTOR
F
5904
2
3
4
5
6
7
H
6
GNDD
100K
I
GNDD
GNDD
CL 16532145_030.eps
221101
1
G
8
9
10
11
12
13
1900
1901-1
1901-2
1901-3
1901-4
1901-5
1901-6
1901-7
1902
1903
1904
1905
1906
1907
2900
2901
2902
2903
2904
2906
2907
2908
2909
2911
2912
2914
2915
2916
3900
3901
3902
3903
3904
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
5900
5901
5903
5904
5905
5907
6900
7702-B
7702-C
7900
7901
7902
7904-A
7904-B
7904-C
7904-D
7904-E
7904-F
7905-A
7905-B
7905-C
7905-D
7905-E
7905-F
7906
F931
F932
F933
F934
F935
A13
G13
F13
G13
H13
F13
H13
F13
I7
I6
I6
I7
I7
I8
A12
A12
A12
B12
B12
A3
A1
A1
G13
H1
H13
F1
F1
B6
A2
B4
B1
B1
G2
E4
E4
F4
F4
G13
G13
I4
G13
C10
D10
G12
H4
H10
H13
H2
H13
I13
I12
A6
B7
A12
B12
A1
F13
H1
F1
B6
C9
D9
A2
B2
B7
D1
F3
D3
H3
C3
E1
G10
H10
G11
H11
G8
G9
H1
F13
G13
G13
H13
H13
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 148
Layout Digital Board (Overview Top View)
PART 1
CL 16532145_32a.eps
PART 2
CL 16532145_32b.eps
CL 16532145_032.eps
231101
1100
1101
1200
1500
1600
1601
1602
1603
1800
1900
1901
2100
2101
2102
2103
2109
2110
2111
2112
2113
2114
2116
2117
2118
2119
2127
2129
2130
2131
2132
2134
2135
2136
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2200
2201
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2215
2216
2217
2218
2219
2220
2221
2222
2223
2225
2226
2227
2228
2230
2231
2304
2305
A4
A3
A4
C2
A1
A1
C1
C2
B1
A2
A1
B2
B3
B3
B3
A3
A3
A3
A3
A3
A3
A2
A2
A2
A2
A3
B3
B2
B2
A4
A4
B3
A3
A3
B3
A3
A3
A3
A3
A3
A3
A2
A4
A4
A4
A4
A4
A3
B2
B2
A4
A4
A4
B4
A4
A5
B4
A4
A5
A4
A5
A5
A4
A4
B4
B4
B5
B5
A5
A5
A4
A4
A4
B4
B4
A5
A4
A3
B4
B4
2311
2403
2411
2412
2413
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2437
2438
2439
2440
2441
2442
2444
2512
2513
2514
2515
2516
2517
2518
2519
2520
2530
2539
2540
2541
2542
2545
2600
2601
2602
2603
2604
2608
2609
2610
2611
2612
2613
2614
2618
2619
2620
2621
2622
2623
2624
2628
2629
2630
2631
2632
2633
2634
2635
2636
2700
2701
2702
2703
2704
2705
2706
A5
A1
A2
B1
B1
A2
A2
B2
A1
A1
A1
A1
B1
A2
B2
A2
A2
A2
A1
A1
A2
A2
A2
A2
A2
A1
A1
A2
A2
A1
C1
C1
C1
C2
C1
B1
B1
B2
B1
C2
C1
C1
C1
B2
C2
A5
A5
A5
C1
C1
B1
B1
A5
A5
A5
B1
B2
B1
B2
A5
A5
A5
C1
C1
A1
B1
A1
C1
A1
B2
A1
B2
A5
B4
B4
B4
C4
C4
C4
C4
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2719
2720
2723
2724
2725
2726
2727
2800
2817
2821
2824
2829
2834
2837
2903
2904
2907
2908
2909
2912
2914
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3200
3202
3203
3204
3208
3209
3211
3213
3214
3215
3216
3217
3218
3219
3220
C4
C4
C4
C4
C4
B4
B4
B4
B3
B4
B4
B4
C4
C4
C5
C4
C4
C4
C3
C4
B1
C3
B1
B1
C3
A2
A2
B3
B2
A2
A1
B3
B3
B3
B3
B2
A4
A4
A3
A2
A3
A3
A3
A3
B1
B2
B3
B3
B3
B3
B3
B2
B3
A3
A3
A3
B3
A4
A4
A4
A4
A4
A3
B2
B2
A4
A3
A5
A4
A3
B5
A4
B4
B4
A4
B4
B4
B4
A4
A4
3221
3222
3223
3224
3225
3226
3227
3228
3233
3234
3235
3236
3237
3242
3243
3244
3245
3400
3401
3403
3408
3409
3410
3500
3501
3601
3602
3603
3604
3605
3609
3610
3611
3612
3613
3614
3615
3619
3620
3621
3622
3623
3624
3625
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3700
3701
3702
3704
3707
3708
3709
3711
3712
3713
3714
3715
3716
3717
3718
3719
3801
3807
3808
3812
3816
3818
3819
3824
3825
3907
B4
B4
B4
A3
A3
B4
A5
A4
B4
A4
A4
A5
A5
B4
B4
A5
A5
A1
A1
A1
B1
B1
B1
C1
C1
A5
A5
A5
B1
B1
B1
B2
A5
A5
A5
B2
A1
A1
C2
A5
A5
C1
A5
C1
B1
A1
B2
B1
A1
B2
C1
A1
C1
A1
B4
B3
B3
C4
B4
B4
C4
C4
C4
C5
B4
B5
B5
B5
B4
B4
C3
C3
C3
C3
C3
C3
C3
C3
C3
A3
3909
4102
4103
4104
4105
4108
4109
4110
4501
4600
4601
4602
4700
4701
5100
5101
5102
5103
5200
5201
5202
5203
5205
5206
5209
5210
5212
5300
5302
5400
5402
5403
5404
5500
5501
5502
5503
5504
5505
5506
5507
5508
5509
5600
5602
5603
5606
5607
5700
5701
5702
5809
5810
5903
5904
5907
7100
7102
7103
7200
7203
7204
7403
7404
7500
7501
7503
7600
7602
7603
7605
7700
7703
7802
7803
B4
A3
B3
A3
B3
B2
B2
B2
C1
C1
C1
C1
C5
C5
A2
A3
A4
B3
A4
A5
A5
A4
A4
B5
A4
A4
A4
B4
B4
A2
A1
A2
A2
B1
B1
B1
B2
C1
C1
C1
C1
B2
C2
A5
A5
A5
A1
A1
C4
C4
B3
C4
B3
B3
A1
B3
A3
B3
A4
A4
A4
B5
A2
A2
C2
C1
C2
A5
A1
A5
A5
B4
C5
C3
C3
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 149
Layout Digital Board (Part 1 Top View)
PART 1
CL 16532145_32a.eps
231101
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 150
Layout Digital Board (Part 2 Top View)
PART 2
CL 16532145_32b.eps
231101
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 151
Layout Digital Board (Overview Bottom View)
PART 1
CL 16532145_33a.eps
PART 2
CL 16532145_33b.eps
CL 16532145_033.eps
231101
2104
2105
2106
2107
2108
2115
2120
2121
2122
2123
2124
2125
2126
2128
2137
2202
2214
2224
2229
2300
2301
2302
2303
2306
2307
2308
2309
2310
2312
2402
2404
2405
2406
2407
2408
2409
2410
2414
2415
2416
2435
2436
2443
2446
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2521
2522
2523
2524
2525
2526
2527
2528
2529
2531
2532
2533
2534
2535
2536
2537
2538
2543
2544
2565
2605
2606
2607
2615
2616
2617
2625
2626
2627
2718
2721
2722
A3
A3
A3
A3
A3
B3
A4
A3
A3
A3
A3
A3
A3
A3
A3
B5
A2
A2
B3
A2
A2
A2
A1
A2
A2
A2
A2
A2
B3
A5
A4
B4
B4
B4
A4
A4
B4
B4
B4
B4
B4
B4
A4
A5
C5
C5
C5
C5
C4
C4
C4
C4
C4
C4
C4
C4
C5
C4
C4
C5
C5
C4
C4
C4
C4
C5
C4
C5
C5
C5
C5
C5
C4
C5
C4
C5
A1
A1
A1
A1
A1
A1
A1
A1
A1
B2
B1
B1
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2818
2819
2820
2822
2823
2826
2827
2828
2831
2832
2833
2835
2836
2900
2901
2902
2906
2911
2915
2916
3111
3112
3113
3114
3115
3116
3201
3205
3206
3207
3212
3229
3230
3231
3232
3238
3239
3240
3241
3300
3301
3402
3404
3405
3406
3407
3502
3503
3504
3505
3506
3507
3508
3509
3513
3515
3600
3606
3607
3608
3616
3617
3618
3626
3627
3628
3703
3705
3706
3710
3720
3800
3802
B2
C2
C2
B2
B2
B2
C2
C2
B1
B1
C1
C1
C2
C2
C3
C2
B3
B2
C3
C2
C2
C2
C3
C2
C2
C3
C2
C2
A4
A4
A4
B4
B3
B3
B2
B5
B5
B4
B4
A3
A3
B5
B5
B5
B4
B5
A2
A1
A1
A2
A1
A1
A1
A1
B2
B3
B4
A4
B4
A4
A4
C5
C5
C5
C5
C5
C5
C4
C4
C5
C4
B4
A1
A1
A1
A1
A1
A1
A1
A1
A1
C2
B2
B2
C2
C2
B1
B2
3803
3804
3805
3806
3809
3810
3811
3813
3814
3815
3817
3820
3821
3822
3823
3826
3827
3828
3900
3901
3902
3903
3904
3906
3908
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
4100
4101
4106
4107
4300
4301
4406
4409
4500
4702
5204
5207
5208
5211
5601
5604
5605
5800
5801
5802
5803
5804
5805
5806
5807
5808
5900
5901
5905
6500
6900
7101
7104
7201
7202
7300
7301
7302
7303
7401
7402
7502
7504
7601
7604
7606
7701
C3
C3
C2
B2
C2
B2
C2
C3
C3
C2
C2
C2
C3
C3
C2
C2
C2
B1
B3
B4
B4
B4
B3
B3
B3
A5
A5
A4
A5
B1
B1
A5
B3
A5
A5
B3
A5
A5
A5
B2
B2
A3
A3
B4
B3
B2
B3
B5
B4
C5
B1
A1
B5
B3
A1
A1
A1
A1
C2
C3
C3
C2
C3
C3
C2
C3
C3
A3
A4
B3
C5
B2
A3
A3
B5
B4
A2
A2
B2
B3
A5
A4
C4
C5
A1
A1
A1
B1
7702
7800
7801
7900
7901
7902
7904
7905
7906
B1
B1
C2
B4
B4
B2
B3
A5
B3
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 152
Layout Digital Board (Part 1 Bottom View)
PART 1
CL 16532145_33a.eps
231101
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 153
Layout Digital Board (Part 2 Bottom View)
PART 2
CL 16532145_33b.eps
231101
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 154
Layout Digital Board (Testlands Bottom View)
Resetn_BE
+3V3
Resetn
+3V3 +3V3 +12V +3V3 +5V
Resetn_VE
-5V
+3V3
+3V3
Sysclk_Empress
EMI_PROCCLK
Sysclk_ProgScan
AE_DATAO
ACC_ACLK_OSC
Sysclk_VSM_5508
+3V3
VSYNC
VE_DSn
VE_DTACKn
HSYNC
+3V3
ACC_ACLK_PLL
+3V3
+3V3
Mute
VIP_ICLK
+3V3
VSOUT
HSOUT
DAC-A/Y
DAC-B
DAC-C
Cr
Cb
Y
+5V
Reset_DVIO
+5V
+3V3 +3V3
+3V3
+3V3
+3V3
+3V3
+3V3
CL 16532145_034.eps
101201
Electrical Diagrams and Print-Layouts
DVDR980-985 /0X1
7.
EN 155
Layout Digital Board (Mapping Testlands )
F214
F247
F248
F249
F250
F264
F265
F931
F932
F933
F934
F935
I100
I101
I102
I103
I104
I105
I106
I107
I108
I109
I110
I111
I112
I113
I114
I115
I116
I117
I118
I119
I120
I121
I122
I123
I124
I125
I126
I127
I128
I129
I130
I131
I132
I133
I134
I136
I137
I138
I140
I141
I142
I143
I145
I147
I149
I152
I153
I154
I155
I156
I157
I158
I159
I160
I161
I162
I163
I164
I165
I166
I167
I168
I169
I170
I171
I172
I173
I174
A3
A2
A2
A2
A2
A2
A3
A4
A4
A5
A4
A4
A4
C5
C5
B4
B4
B3
B3
B3
B3
B4
B3
A2
B5
B5
B5
B5
C3
C3
C4
C4
A4
A3
B3
A2
B4
A2
A3
A2
A4
A2
B3
A3
B1
A3
A3
A3
A2
A3
A3
A4
A3
B4
A3
B4
B3
B3
B5
B3
B3
A3
A3
B4
A5
B3
B3
C4
A3
B4
A3
B4
A3
C5
A3
A3
A3
A3
A3
A3
I175
I176
I177
I178
I179
I180
I181
I182
I183
I184
I186
I187
I188
I200
I201
I202
I203
I204
I205
I206
I207
I208
I209
I210
I211
I212
I213
I215
I216
I217
I218
I219
I220
I221
I222
I223
I224
I225
I226
I227
I228
I229
I230
I231
I232
I233
I234
I235
I236
I237
I238
I239
I240
I241
I242
I243
I244
I245
I246
I251
I252
I253
I254
I255
I256
I257
I258
I259
I260
I261
I262
I263
I264
I265
I266
I267
I268
I269
I270
I271
A3
A3
A3
A3
A3
A3
A3
B3
A2
A3
A3
A3
A3
A2
B3
A5
A3
C3
A2
A4
A2
B3
B4
A2
A2
A2
A2
B5
A1
A2
A2
A1
A1
B2
B2
A2
A1
A2
A2
A2
A2
B5
A2
A2
A2
A2
A4
A4
B4
A2
A2
B5
A4
B2
B1
B1
A2
A1
A2
A1
A2
A2
A1
A1
A2
C5
A2
A2
A1
A1
A1
A1
A2
B5
A2
A2
B2
B2
A2
B1
I300
I301
I302
I303
I304
I305
I306
I307
I308
I309
I400
I401
I402
I403
I404
I405
I406
I407
I408
I409
I410
I412
I413
I414
I415
I416
I500
I501
I502
I503
I504
I505
I506
I507
I508
I509
I510
I511
I512
I513
I514
I515
I516
I517
I518
I519
I520
I521
I522
I523
I524
I525
I526
I527
I528
I529
I530
I531
I532
I533
I535
I536
I537
I538
I540
I543
I551
I552
I553
I555
I600
I601
I602
I603
I604
I605
I606
I607
I608
I609
A2
A2
A2
B2
B3
B3
A3
B3
A3
B3
A4
A4
B4
A4
B4
B4
B4
A4
A5
A4
A4
B4
A4
B4
B4
B4
C5
C5
C5
C5
C5
C5
C5
C5
C5
C5
B5
C4
C5
B5
B4
C5
C5
C5
C4
C5
C4
C4
C4
C4
C4
C5
C5
C5
C4
C5
C5
C5
C5
C4
C5
C4
C5
C4
C5
C5
C5
C4
C4
C4
A5
A5
A5
C5
A5
A5
A5
A5
A5
B5
I610
I611
I612
I613
I614
I615
I616
I617
I618
I619
I621
I622
I623
I624
I625
I626
I627
I628
I629
I630
I631
I632
I633
I634
I635
I636
I637
I638
I639
I640
I641
I642
I643
I644
I645
I646
I647
I649
I650
I651
I652
I653
I654
I655
I656
I657
I658
I659
I660
I661
I662
I663
I664
I665
I666
I667
I668
I669
I670
I671
I700
I701
I702
I703
I704
I705
I706
I707
I708
I709
I710
I711
I712
I713
I714
I715
I716
I717
I718
I719
A5
B5
A5
B5
A5
B5
A5
A5
C4
A5
A1
A1
A1
A1
A1
A1
B4
C4
A5
C4
C4
C4
B4
C4
C5
C4
C5
C5
C5
C5
B5
A5
A5
A5
B5
C4
A5
C5
B4
B5
B5
B5
B4
B4
B5
C4
C4
C3
B5
B5
C5
B4
B5
C4
C5
B5
B4
B4
A5
B5
B2
B1
B1
C2
C2
C2
C2
C2
C2
C1
B3
C2
C2
A1
C2
C2
B3
B3
B3
B3
I720 B3
I880 C3
I721 B2
I881 C3
I722 B3
I882 C3
I723 B2
I883 C2
I724 B2
I884 C2
I725 B3
I900 B4
I726 B2
I901 B4
I727 B2
I902 B4
I728 A1
I903 B4
I729 A1
I904 B2
I730 A1
I905 A4
I731 A1
I906 A4
I732 B2
I907 A4
I733 B2
I908 A5
I734 B1
I909 B4
I735 B1
I911 B3
I800 C4
I912 A3
I801 C3
I913 B3
I802 C3
I915 B3
I803 C3
I916 B3
I805 C3
I917 B3
I806 C3
I918 A5
I807 C3
I919 B3
I808 C2
I920 B3
I809 C2
I921 A5
I810 C3
I922 A5
I811 C3
I923 B3
I812 C2
I924 A4
I813 C2
I925 B3
I814 C1
I926 A5
I815 B2
I927 A5
I816 B2
I928 A5
I817 B2
I930 B3
I818 C2
I931 A5
I819 C3
I932 B2
I820 C3
I933 B3
I821 C3
I822 C3
I823 C3
I824 B2
I825 B2
I826 C3
I827 C3
I828 C3
I829 C3
I830 C3
I831 C3
I832 C3
I833 C3
I834 B3
I835 B3
I836 B2
I837 C3
I838 C3
I839 C3
I840 C3
I841 C3
I842 C3
I843 C2
I844 C2
I845 C2
I846 B3
I847 B2
I848 B2
I849 B2
I850 B2
I851 B1
I852 B1
I868 C2
I869 C2
I870 B2
I871 C3
I872 C3
I873 B2
I874 C2
I875 C2
I876 C3
I877 C2
I878 C3
I879 C3
CL 16532145-34m.eps
101201
Personal Notes:
Electrical Diagrams and Print-Layouts
Personal Notes:
DVDR980-985 /0X1
7.
EN 156
Personal Notes:
Alignments
DVDR980-985 /0X1
8.
8. Alignments
8.1
Alignment Instructions Analogue Board
Alignments Analog PCB Eur
Test equipment:
2 HF - AGC adjustment [3707]:
1. Dual-trace oscilloscope
Voltage range
: 0.001 ~ 50 V/div
Frequency
: DC ~ 50 MHz
Probe
: 10:1, 1:1
Service tasks after replacement of IC 7703:
Purpose: Set amplifier control.
Symptom, if incorrectly set:
Picture jitter if input level is too low and picture distortion
if input level is too high.
2. DVM (Digital voltmeter)
3. Frequency counter
TP
4. Sinus generator
Sinus
: 0 ~ 50 MHz
Tuner
1705
Pin 11
(F700,
IF-out)
5. Test pattern generator
How to read the adjustment procedures:
ADJ.
R3707
DISC
DVDR mode:
Example using:
DVDR TUNER
Connecting point
(Test Point) of
Adjustment
component
INPUT
5mV(74dBµV)
on aerial input
PAL white picture,
audio IF on,
no modulation
Set tuned to
channel 25
503.25 MHz
MEAS.EQ.
SPEC.
Oscilloscope
Video Pattern
Generator
500mVpp +/-0.5dB
(use a 10:1 probe )
3 Attenuating the 40.4 MHz [5702]:
(SECAM only)
Test signal
required for the
adjustment and
feed in point
measuring
equipment
MODE
Service tasks after replacement of coil 5702:
Purpose: To attenuate the band I carrier rests.
TP
ADJ.
MODE
Pin 2 of
Con.1911
(FMRV)
R3054
TUNER
DISC
MEAS.EQ.
FrequencyCounter
Disc
Measuring
equipment
Disc needed for
adjustment
Symptom, if incorrectly set:
Bad picture quality when the filter attenuates the picture
carrier (38.9MHz).
INPUT
SPEC.
TP
3,800MHz
±10kHz
ADJ.
OFW
1700
Pin 1
(F704)
Adjustment
L5702
DISC
Specification
Front End (FV)
MODE
TUNER
INPUT
40.4 MHz, 200mVrms
at Tuner 1705, Pin 11
(F700, IF-out)
MEAS.EQ.
SPEC.
Oscilloscope,
Sinus Generator,
Counter
adjust minimum
amplitude
Service tasks after replacement of IC 7703, coil L5702 and L5703:
If the adjustment is correct the signal at pin 1 of OFW [1700] must be
smaller than the input signal amplitude by at least 6 dB.
1 AFC Adjustment:
Purpose: Correct adjustment of demodulator AFC - circuit
Symptom, if incorrectly set:
Bad or disturbed TV channel reception.
PAL - AFC adjustment [5703]:
TP
IC 7703
Pin 17
(I976)
ADJ.
L5703
DISC
MODE
INPUT
TUNER
38,9MHz 500mVpp
at Tuner 1705, Pin 11
(F700, IF-out)
MEAS.EQ.
SPEC.
DC Voltmeter
Frequ. Generator
2,5V ±0,1V
Storage in NVRAM via command mode interface of DSW:
After adjustment, the AFC reference value has to be stored in the NVRAM.
This reference value is 256 * measured voltage/Ucc. Ucc is 5.0V.
Store the reference value via command 732 , followed by the ref. value.
Example: DD:> 732 128
Figure 8-1
CL 16532145_061.eps
041201
EN 157
EN 158
8.2
8.
DVDR980-985 /0X1
Alignments
Reprogramming Procedure of NVM on the
Analogue PCB
8.2.4
The slash version is stored with command 715 followed by the
slash version as parameter.
The slash versions used in DVDR1000 and DVDR1500 are the
following:
• DVDR980/00X:
2
• DVDR980/02X:
2
• DVDR980/05X:
4
• DVDR985/00X:
5
• DVDR985/02X:
5
• DVDR985/05X:
6
Example:
DD:>715 1
The NVM, item 7815, on the Analogue board contains the
following factory settings:
1. Bargraph 0dB correction factor
2. Clock correction factor
3. AFC reference value
4. Slash version
The settings 1,2 and 3 are stored in the NVM during the
production of the analogue board.
The slash version is stored at the end of the production line of
the set.
In case of failure, the NVM must be replaced by an empty
device. By way of commands via the Diagnostic Software or via
ComPair, the factory settings must be restored in the NVM.
8.2.1
8.2.2
8.3
Rework Procedure IEEE Unique Number
8.3.1
Scope:
The procedure describes how to upgrade sets with a unique
number after repair. This unique number is stored in the
NVRAM (item 7201) of the digital board at the end of the
production line.
This procedure is only valid or necessary when:
• The digital board is replaced
• NVRAM on the digital board is replaced
• NVRAM is cleared
In all other cases the repaired set retains its unique number.
The procedure defines several means to re-assure the unique
number depending on the possibilities of repair or the state the
faulty set is in.
Clock Correction Adjustment
To guarantee an exact function of the real time clock, an
adjustment of the clock frequency is possibe and stored in the
NVM.
Procedure:
• Connect a pull up resistor of 10k between pin 7 an 8 of the
clock IC PCF8593T, item 7811, on the analogue PCB
• put the set in service command mode
• execute command 722 to initiate that a 1 Hz signal is
available on pin 7 of the clock IC
DD:>722
• measure the frequency of the Clock Crystal with an
accuracy of ±1(s. Normally the measured frequency must
be between 999902 (s and 1000097 (s. If the frequency is
outside this range, the clock IC must be replaced.
• Execute command 721 with the measured frequency as an
input parameter
example:
DD:>721 1000023
8.2.3
Reset of Slash Version
Use command 729 to reset the analogue board to the default
setting.
Procedure:
• Put the set in DSW command mode
• Execute command 729 with the following parameters:
DD:> 729 w 0xA0 3 0x07 0xD0 0x00
• Leave the DSW command mode and start up the set in
application mode No background is visible on the TV
screen. The analogue board is ready to accept the
appropriate slash version.
Bargraph 0db Alignment
For an exact functionality of the bar graph in the display, a
correction factor for the left and the right channel is stored in the
NVM.
Procedure:
• Put the set in DSW command mode
• route Audio path from Audio front connectors to digital with
the following command:
DD:> 713 01
• apply a sine wave of 1 kHz, 1.65 Vrms (0 dB) to the front
connectors, audio left and right
• store 0 dB bar graph level with command 720
DD:>720
AFC Reference Voltage Tuner
This function stores the reference voltage for the tuner in the
NVM. Before this value can be stored, the AFC adjustment,
described in the adjustment instructions of the analogue board,
must be carried out.
Procedure:
• Adjust AFC circuit
• Calculate the reference value
• Execute command 732 and use the calculated reference
value as parameter
example:
DD:>732 128
Slash Version
8.3.2
Handling:
State of Original (Defective) Board:
1. The digital board starts up in Diagnostics Mode: follow
procedure A to retrieve the valid unique number
2. The digital board does NOT start up in Diagnostics Mode:
follow procedure B.
8.3.3
Procedure A
1. Connect defective digital board to PC via serial cable (3122
785 90017)
2. start up hyper terminal or any other serial terminal via the
correct settings (DSW command mode interface)
3. read out existing unique number via nucleus 403
example:
DD:> 403
40300: DV Unique ID = 00D7A1FC6C
Test OK @
4. note read out
5. program new digital board via nucleus 410
example: DD:> 410 00D7A1FC6C
41000:
Test OK @
The set has now the original unique number
Alignments
8.3.4
Procedure B
1. Note the serial number of the set example:
AH050136130156
–
AH = production centre Hasselt. According to UAW500: A=1 and H=8
–
05 = change code (this is not used for this calculation)
–
01 = YEAR
–
36 = Production WEEK
–
130156 = Lot and SERIAL number
2. Calculate the unique number: this number always exists
out of 10 hexadecimal numbers.
3. First 5 numbers: First we calculate a decimal number
according to the formula below: 35828*YEAR + 676*
WEEK + 26*A + H + 8788 The figures are fixed, YEAR +
WEEK + factory code ( A + H) are variable
Example: 35828*01+676*36+26*1+8+8788 = 68986
(decimal) Then we translate the decimal number to a
hexadecimal number.
example: 68986 (decimal)= 10D7A (hex)
4. Last 5 numbers: The last 5 numbers exist out of the Lot
and SERIAL number. We have to translate the decimal
number to the next 5 hexadecimal numbers:
Example: 130156 (decimal) = 1FC6C (hex)
5. Program new digital board via nucleus 410 Therefore we
use the 10 hexadecimal numbers we calculated above:
example:
DD:> 410 10D7A1FC6C
41000:
Test OK @
The set has now its original unique numbe
DVDR980-985 /0X1
8.
EN 159
EN 160
9.
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9. Circuit-, IC Descriptions and List of Abbreviations
9.1
Multi-Mode SOPS 50PS203
9.1.1
Why Multi-Mode SOPS?
Using ordinary SOPS results in a decrease of the efficiency at
low output loads due to the increase of the switching frequency.
The Multi-Mode SOPS will reduce the switching frequency at
low loads but still preserves valley switching.
9.1.2
Block Diagram
Rectifier
Lightning
Protection
Vi
6200
5131
33Vstby
EMI
FILTER
MAINS
4
6201
6211
2260
6210
2125
+12Vstby
2210
6215
+ Vb
Overvoltage
protection
Overload
protection
7142
7141
2140
+12Vreg
2
6140
7125
Power
switch
3141
2141
+3V9
2214
6221
FLYB
2146
feed forward
7140
2211
7220
6220
7143
-5Nstby
2220
Rsense
Control
-Vreg
2222
6230
6142
-Vgnstby
2220
8
2151
6144
6143
6231
2235
6240
7
5.2Vstby
2240
2241
7200
7251
Regulation
+12Vreg
CL 16532095_111.eps
150801
Figure 9-1
9.1.3
Circuit Description
Input Circuit
The input circuit consists of a lightning protection circuit and an
EMI filter.
The lightning protection comprises R3120, sparkgaps 1124
and 1125. D6128, 6129, C2127 and R3129 are optional.
L5110, L5115, C2120 and L5120 form the EMI filter. It prevents
inflow of noises into the mains.
Primary Rectifier/smoothing Circuit
The AC input is rectified by diodes 6151,6152, 6153, 6154 and
smoothed into C2125. The voltage over C2125 is
approximately 300V. It can vary from 200V to 390V.
Start Circuit
This circuit is formed by R3125, 3126, R3141, C2140 and
R3132.
When the power plug is connected to the mains voltage, the
MOSFET 7125 will start conducting as soon as the gate
voltage reaches a treshold value. A current starts to flow in
primary winding 2-4. The MOSFET will be fed forward via
winding 7-8, R3150 and C2146.
+Vb Supply and Negative Regulation Voltage
The positive part of the voltage over winding 7-8 will be rectified
via R3150, D6140 and charged via R3140 into C2140. The
voltage over C2140 has a value of +30 till +40V. This value
depends on the value of the mains voltage Vi and the load.
The negative part of the voltage over winding 7-8 will be
rectified via R3150, D6142 and charged into C2151. The
voltage over C2151 has a value of -15V and is used as
regulation voltage.
Control Circuit
The control circuit exists of T7140, D6141, C2144 and 2145,
C2147, R3147 and 3148.
This circuit is fed by supply voltage +Vb via R 3141. This circuit
controls the conduction time and the switching frequency of the
power switch circuit. It switches off the MOSFET as soon as the
voltage over Rsense reaches a certain value. This value
Circuit-, IC Descriptions and List of Abbreviations
depends on the error voltage at the emittor of T7140, which can
be positive or negative (+/- 0,66V). The voltage fed back by the
regulation circuit defines this error voltage.
Regulation Circuit
The regulation circuit comprises opto-coupler 7200, which
isolates the base voltage of transistor 7140 at the primary side
from a reference component 7251 at the secondary side. The
TL431(7251) can be represented by two components:
• a very stable and accurate reference diode
• a high gain amplifier
K
R
2.5V
A
CL 96532065_071.eps
130799
Figure 9-2
9.2
Display Board
9.2.1
Operation Unit DC (DC Part)
9.2.2
Evaluation of the Keyboard Matrix
There are 15 different keys on the display board. A resistor
network is used to generate a specific direct voltage value,
depending on the key pressed, via the resistors 3145, 3171,
3183 and 3194 on the analog/digital (A/D) ports (7156 Pin 17,
18, 19, 20). Pressing keys simultaneously may lead to
undesired functions!
9.2.3
Secondary Rectifier/Smoothing Circuit
There are 6 rectifier/smoothing circuits on the secondary side.
Each voltage depends on the number of windings of the
transformer.
From these circuits a lot of voltages are derived and fed to 3
connectors. The following voltages are present at the output:
Connector 209
Functional use: to Digital board + Dvio board
1. +3V3(for dig pcb + DVio)
2. +3V3(for dig pcb + DVio)
3. +3V3(for dig pcb + DVio)
EN 161
The core element of the operation unit DC is the microcontroller
TMP88CU77ZF [7156]. The TMP88CU77ZF is an 8 bit
microcontroller fitted with 96kB ROM and 3kB RAM and is
responsible for following functions:
• Integrated VFD driver
• Timer
• Evaluation of the keyboard matrix
• Decoding the remote control commands from the infra-red
receiver pos. 6170
• Activation of the display
• Motor driver
The system clock is generated with the 12MHz quartz (Pos.
1153).
Overload Protection Circuit
This circuit consists of R3145, C2143, a thyristor circuit formed
by T7141 and T7143, R3143 and R3142. When the output is
shortened, the thyristor circuit will start to conduct and switch
off the supply voltage over C2140. This results in a switching of
f of the drain current of the MOSFET 7125 and the output will
be disabled. The start circuit will try to start up the power supply
again. If the circuit is still shortened, the complete start and stop
sequence will repeat. The power supply comes in a hiccup
mode (is ticking).
Overvoltage Protection Circuit
This circuit consists of R3149, D6144, 6143, R3144, C2142
and T7142.
When the regulation circuit is interrupted due to an error in the
control loop, the regulated output voltage will increase
(overvoltage). This overvoltage is sensed on the primary
winding 7-8.
When an overvoltage is detected, the circuit will start up the
thyristor circuit T7141-7143. The power supply will come in a
hiccup mode as long as the error in the control loop is present.
9.
4. +3V3(for dig pcb + DVio)
5. GND(for dig pcb + DVio)
6. +12V(for dig pcb + DVio)
7. GND(for dig pcb + DVio)
8. GND(for dig pcb + DVio)
9. +5V(for dig pcb + DVio)
10. STBY control(for dig pcb + DVio)
11. GND(for dig pcb + DVio)
12. -5V(for dig pcb + DVio)
The +12V is switched off by the STBY_ctrl signal.
When the +12V is switched off, also the +3V3, +5V and -5V are
switched off. All these voltages are low drop regulated.
Connector 0205
Functional use: to analogue board + display board + flap motor
‘STBY‘ indicates that the voltage will not be switched off in the
standby situation.
1. +12VSTBY(= +12V Standby, for display heating, 8Vstby)
2. +5VSTBY(= +5V Standby; general use)
3. -5NSTBY(= -5V Standby; neg. voltage for drivers)
4. VGNSTBY(= -32V Standby; for display grids)
5. +33STBY(= +33V Standby; for tuner)
6. FLYB(flyback pulse for power fail + measurement)
7. GNDA(Ground for the analogue board)
Connector 0207
Functional use: to engine
1. +3V3(for engine servo board)
2. +5V(for engine servo board)
3. GND(for engine servo board)
4. +4V6E(for engine analog part)
5. GND(for engine servo board)
6. -5V(for engine servo board)
7. GND(for engine motor currents)
8. +12V(for engine motor currents)
Power Switch Circuit
This circuit comprises MOSFET 7125, Rsense formed by
R3133, 3134, 3135, 3136 and 3137, R3131, R3132, D6146.
Diodes 6130, 6131 and 6132 protect the control circuit in case
of failure of the MOSFET.
TL431 will conduct from cathode to anode when the reference
is higher than the internal reference voltage of about 2.5V. If the
reference voltage is lower, the cathode current is almost zero.
The cathode current flows through the LED of the opto-coupler.
The collector current of the opto-coupler will adjust the
feedback level of the error voltage at the emittor of T7140.
DVDR980-985 /0X1
IR Receiver and Signal Evaluation
The IR receiver [7140] contains a selectively controlled
amplifier as well as a photo-diode. The photo-diode changes
the received transmission (approx. 940nm) in electrical pulses,
which are then amplified and demodulated. On the output of
the IR receiver [7140], a pulse sequence with TTL-level, which
corresponds to the envelope curve of the received IR remote
control command, can be measured. This pulse sequence is
input into the controller for further signal evaluation via input
IRR [7156, pin 2].
EN 162
9.2.4
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
• A/D converters
• composite sync input
• I2C bus interface
Following connection to the mains, a positive pulse on the reset
input on the P is generated by the reset-IC TL7705 (Pos.7900).
The system clock is generated with the 20MHz quartz (Pos.
1994).
Motor Driver Flap
The flap-motor is controlled via the 2 Port-Pins (MD1, MD2) of
the P (7156, Pin 12, Pin 100). The motor driver part is
constructed as a bridged dual power operational amplifier.
Between the IC outputs (7120, Pin1, Pin3) and a Boucherot
circuit (2121, 3126) suppresses a spurious 3MHz oscillation
from the output stage. The two ports-pins (MD1, MD2) of the P
are PWM-outputs and are controlled in the following way:
9.3.2
Flap Motor:
off
MD1
MD2
H
L
open
H
PWM(H)
close
L
PWM(L)
The communication between the P and the other functional
groups is via the I2C-bus (SDA, SCL). The clock rate is approx.
95kHz.
Functional groups on the I2C bus:
• E2PROM ST24E16 (Pos. 7815)
• Tuner (Pos. 1705)
• Matrix-switch STV6410 (Pos. 7507)
• Audio IC / MSP (Pos. 7600)
• Display board (Pos. 1987)
• VPS-IC (Pos. 7990).
Duty Cycle 50% for OPEN and CLOSE
9.3.3
9.3.4
Duty Cycle app. 10% for OPEN
Figure 9-3
9.3.5
For the detection of the end-positions of the flap there are two
switches (1178, 1179) installed and the information is
evaluated from the P via the signals SW_1178 and SW_1179.
Flap Switches:
SW2
L
H
closed
H
L
moving
H
H
error
L
L
Colour of STBY
LED
Status of the Set
red
STBY
green
ON
9.3
Analogue Board Europe
9.3.1
Microprocessor TMP93C071F
The microcontroller „AIO“ TMP93C071F is a 16bit
microcontroller with internal ROM and 8kB RAM. It includes the
following functions:
Fan Control
The fan control circuit is necessary to control the speed of the
cabinet fan (Pos. 1984) according to the requirements in
temperature and noise. The temperature is measured via an
NTC on the display board (Pos. 3145). When the temperature
is lower than 25° C the fan-voltage is approx. 5V and will reach
approx. 10V at a temperature of 40° C. It is also possible to
switch off the fan via the control line ION_FAN. The circuit
generates also two control-signals: TEMP goes to the P and
BE_FAN is the control-line for the basic engine fan.
Bi-Color LED (Standby and ON)
The STBY-LED is a red/green bi-color-LED and is controlled
via the STBYLED-signal of the P (7156 Pin 10) in the following
way:
FOME
The FOME-circuit compares the video signal coming from the
tuner and the one coming from the Scart-plug 1. If the videosignals are identical the output of the FOME-circuit is low.
9.3.6
SW1
VPS, PDC, Teletext (Europe Only)
The STV5348 (Pos. 7990) is a VPS, PDC, and Teletext
Decoder with an external 13,875Mhz quartz.
The following data formats are identified:
• VPS (Timer data and station name)
• PDC Format 2 (Timer data and station name)
• PDC Format 1 (station name and time)
• TXT header line (time for „time download“)
CL 16532095_112.eps
150801
9.2.5
E2PROM
The E2PROM ST24E16 (Pos. 7815) is an electric erasable and
programmable, non-volatile memory. The E2PROM stores data
specific to the device, such as the AFC-reference value, clockcorrection-factor, etc. The data is accessed by the P via the
I2C-bus.
Duty Cycle app. 10% for CLOSE
open
Bus Systems
9.3.7
Power Supply
The 5SW and 8SW supply are switched off in case of standby
from the P via the ISTBY-line. This is possible for power-save.
The ISTBY-line must be low in case of STBY. There is also a
„power fail“ circuit on the PS-schematic which is necessary to
mute AUDIO when IPFAIL is low.
9.3.8
Front End (TU, AP Part)
The Front End Comprises the Following Parts:
• Tuner [1705]
• IF amplifier & video demodulator IC TDA 9818 [7703]
• Sound processor MSP3415G [7600]
Circuit-, IC Descriptions and List of Abbreviations
IF Selection
The IF frequency of the video carrier is 38.9 MHz for all
systems except SECAM L' (33.9 MHz).
A quasi-split audio system is used. Separate surface-wave
filters (SAW) are required. [1700], [1701] for video, [1702] for
audio. [1700] Is switched into the signal path for DK/I-SECAM
L/L' reception, if the signal SAWS is “high”. In this case the
switches [7701], [7702] are open and the diode [6700] is
conducting. [1701] Is switched into the signal path for BG
reception, if the signal SAWS is “low”. Then the switch [7708]
is open and the diode [6701] is conducting. For DK/I-SECAM L/
L' reception, an additional circuit for suppressing the adjacent
channel audio carrier is provided, which is set using coil [5702]
to maximum suppression at 40.4MHz.
IF Demodulator
TDA 9818
The IF signal from the tuner is processed by the demodulator
IC TDA 9818 [7703]. The signal PSS to pin3 switches between
demodulation of positive SECAM or negative PAL modulated
video carriers. A QSS-audio-IF signal SIF1 is generated for
demodulation in the sound processor [7600]. The audio-IF
carrier is selected in the audio SAW filter [1702]. This filter is
switched for SECAM L’. If the signal SB1 is “high”, the switch
[7707] is closed and the diode [6702] is not conducting. For all
other standards the diode [6702] is conducting and the switch
[7707] is open. The output signal from this SAW filter is first
processed in the TDA 9818. Audio carriers are converted from
the tuner IF level into the audio IF position and further
processed in the audio demodulator [7600]. The AFC coil
[5703] on the TDA 9818 is adjusted so that when a frequency
of 38.90 MHz is supplied to the IF output of the tuner, the AFC
voltage on pin 17 of the TDA 9818 is 2.5V. The setting of the
picture carrier frequency for SECAM L in the TDA 9818 is
achieved by connecting pin 7 of the IC via a resistor [3702] to
earth. The switch [7700] and the signal SB1 "high" do this. The
HF-AGC is set using the AGC controller [3707] so that, with a
sufficiently large antenna input signal (74 dBV), the voltage at
the IF output of the tuner [1705] pin 11 is 500 mVpp. This
setting must be carried out, when the audio carrier is switched
off. The demodulated video signal appears on pin 16 [7703].
The demodulator AGC voltage at pin4 is used to determine the
antenna signal strength after a buffer [7705] with the signal
AGC_MUTE. In the opposite direction this line may be used to
mute the demodulator to avoid cross talk in all cases, where the
tuner signal is not needed. In this case a „high“ signal is sent
via AGC_MUTE and the conducting diode [6703] to pin4. The
video trap [1703] reduces adjacent channel video and sound
carrier remainders in the video for BG standards. For all other
standards the switch [7704] and signal TS "low" bypass this
trap. In this cases the selectivity of the SAW filter [1700] is
sufficient. A frequency response correction is achieved by the
inductance [5009] for not BG standards. This correction is not
preferred for SECAM L' and therefore shorts circuited by
[7709], if the signal SB1 is “high”. The demodulated video
signal VFV is available after the buffer and limiting stage for
noise peaks [7706]. The FM-PLL demodulator function of TDA
9818 is not used and deactivated by the resistor [3726].
Audio Demodulator
Sound processor MSP 3415G
The MSP 3415G [7600] is a multistandard sound processor
which can demodulate FM Mono/Stereo, NICAM and AM
signals. The incoming signal is first controlled and then
digitised. The digital signal is then demodulated in 2 separate
channels. In the first MSP channel, FM and NICAM (B/G/I/D/K)
are demodulated, whereas in the second MSP channel, FM
and are demodulated again (NICAM L corresponds to NICAM
B/G). These demodulated signals are selected digitally in the I/
O and switched to the D/A converter on the outputs. Amplitude
and bandwidth of the demodulated audio signals can be
determined in the MSP using the corresponding commands via
DVDR980-985 /0X1
9.
EN 163
the I2C bus. The audio signal from the tuner is available at the
pins 30 AFER and 31 AFEL.
9.3.9
Input/Output Video-Routing (Europe-Version)
General Description:
The complete Video- I/O-switching is basically realised by the
I/O switch STV6410A. It is controlled via IIC-Bus-0 (SDA/SCL)
by the all in one C on the analogue board. The STV 6410 has
three YCVBS switches, three chroma switches and one RGB
switch. All switches have 6-dB amplification on the outputs.
The YCVBS inputs have bottom clamp, the chroma inputs have
average clamp, and the RGB inputs have bottom clamp circuits
at the inputs. The R/C inputs can be switched to average clamp
for chroma signals via I2C bus.
The IC has also one slow blanking monitor and one fast
blanking switch for fast RGB insertion (see detailed description
in chapter 1.5). Two pre-selectors BA 7652 are additionally
used: One for switching between Rear CVBS, Y- Rear and
Front, the second for switching between Chroma- Rear and
Front signal. Both pre-selectors are controlled via IS1 and IS2
from the analogue board C.
CVBS Signals:
There are four CVBS input connection possibilities: Front
chinch (E6), Rear Chinch (E4), Scart 1 (E1) and Scart 2 (E2).
Rear Chinch In is routed via the pre selector BA 7652; the other
signals are connected direct to the STV 6410. The selected
CVBS signal is routed to Rear Chinch Out (via BA 7660, 6dB
amplification, 75 Ohm driver) and to Scart 1. Independent of
the input signal quality (CVBS, S-Video or RGB) the digital
board supplies also S-Video and RGB signals to the
corresponding socket.
S-Video Signals:
There are also four S-Video input connection possibilities:
Front In (E5), Rear In (E3), Scart 1 and Scart 2. For S-Video
from Scart this option has to be switched on in the OSD menu.
The pre-selectors and the STV 6410 do the signal selection (for
detailed routing see overview). Also the video quality will be SVideo, the digital board supplies also CVBS to the
corresponding sockets. The S-Video signal that is coming from
the digital board is routed via BA 7660 (6-dB amplification and
75-Ohm driver) to the S-Video Rear Out socket.
RGB Signals:
The Scart 2 RGB input signal (Decoder socket) is connected to
the RGB switch of STV 6410 and to the digital board in parallel.
The RGB from Scart 2 is routed to Scart 1 in low power standby
mode. The direct connection (not via STV 6410) is for loop
through and REC. The RGB signal, which is coming from the
digital board, is connected to the RGB encoder input of the STV
6410 and is routed to Scart 1 in all other modes.
As the Scart-connection can carry either RGB- or Y/C-signals
it is necessary to define the available and selected signalproperty. While Pin15 of Scart (Red or Chroma-upstream) is
fully handled via STV6410A the Pin7 (Blue or Chromadownstream) has to be extra set.
• Scart1: Pin42 of C (SC1YC_H-line):
–
Low ( Blue-Out on SC1
–
High ( Chroma-In on SC1
• Scart2: Pin41 of C (SC2RGB_H-line):
–
Low ( Chroma-Out on SC2
–
High ( Blue-In on SC2
Detection of Status-Information
Pin-8 (Slow-Blank):
Level-detection of Pin-8 (Scart-1 and -2) is realised by using
STV6410A. It can be readout via IIC-Bus by the CC-C. To
obtain the status of Scart1-Pin8, Bit 0 & 1 of register 06h must
be set to 0 (Input-mode). The corresponding bits for verification
of Scart2-Pin8-status are set to input-mode as default.
EN 164
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Meaning of Read-Register-Bits:
• Bit 7 & 6: not used
• Bit 5 & 4: Status Scart-2/Pin8:
–
0 1 Low-level
–
1 0 Medium-level (16:9)
–
1 1 High-level (4:3)
• Bit 3 &2: not used
• Bit 1 & 0: Status Scart-1/Pin8:
–
0 1 Low-level
–
1 0 Medium-level (16:9)
–
1 1 High-level (4:3)
(OPV) the signals are delivered back to the STV 6410 and also
direct to the 2nd rear out Cinch. The other outputs (Scart,
Cinch) are supported by the STV 6410.
Pin-16 (Fast Blank):
Only the status/level of Scart-2/Pin16 must be detected; this is
realised by using PortC3/AIN14 (Pin25) of the CC-C as an
Analogue-input.
• ADC-value lower or equal 24h ( Pin16 low (no RGBsignals)
• ADC-value greater 24h ( Pin16 high (RGB present on
Scart-2)
To avoid misdetection a “software-integration” (result is first
valid if it was 3-times the same) must be implemented,
determination has to be done approx. every 47msec (no
multiple of V-sync).
Detailed Description UDA 1360:
The UDA 1360TS is a stereo Analog-to-Digital Converter
employing bitstream conversion techniques.
The UDA supports the I2S-bus data format and the MSBjustified data format with word lengths of up to 20 bits. The IC
supports also 2Vrms input signals and is designed for 3V3
supply voltage.
The device is able to handle system clocks of 256fs and 384fs.
Typical THD+N at 0dB is -85dB and a S/N performance up to
97dB is possible.
WSS on Y/C-Plug:
Picture-Ratio-Information (16:9 or 4:3) on SVHS-connections
is coded via the average DC-level of the Chroma-signal-line,
detection is realised by using an analogue-input-port of the CCC.
• ADC- value lower or equal 40h ( 4:3-picture-ratio delivered
• ADC-value greater 40h ( 16:9-picture-ratio available on
plug
Y/C-Rear is determined via Port40/AIN3 (Pin14) of CC (WSRIline) and Port41/AIN4 (Pin15) is used for Y/C-Front (WSFIline).
Generation of Status-Information
Pin-8 (Slow Blank):
Only on Scart-1 the Slow-Blank-Status (Level of Pin8) must be
created, which is done via IIC-Bus-register 06h (Bits 0 & 1) of
the STV6410A.
Pin-16 (Fast Blank):
Only the status/level of Pin16-Scart1 must be controlled; this is
realised by using the FB-switch-capabilities of the STV6410A,
which are set via IIC-Bus-register 04h (bits 4 & 5).
WSS on Y/C-Plug:
The appropriate DC-level on Chroma-signal-line for Y/C-RearOut is produced via Port57 (Pin10) of the CC-C (WSRO-line).
• 4:3 - Picture-ratio supported on Y/C-Plug: Port57 set to 0
• 16:9 - Picture-ratio supported on Y/C-Plug: Port57 set to 1
9.3.10 Audio Routing Analogue board (Europe / Nafta)
General Description:
The Audio- I/O switching is realised by the STV6410 I/O switch.
By I2C Bus (SDA-0/SCL-0) it is possible to control all the Audio
in- and outputs (for detailed Information we refer to the
STV6410 routing overview).
Analog audio coming from DV-Board and second rear Cinch
input is routed via MSP3415 to the STV 6410. After selecting
the audio source via STV 6410, the signal must be transformed
into the digital domain. For this, the UDA 1360TS (ADC) is
responsible. An input-voltage of up to 2Vrms can be handled
from the IC´s. For further processing, the UDA 1360TS (ADC)
delivers the data-in I2S format to the digital-board. After a
certain delay the (processed) data come back from the digital
board to the UDA 1328 (DAC). The UDA 1328 (DAC)
transforms the I2S data back into the analog domain and feeds
the signals direct to the MC33078 (OPV). From the MC33078
Detailed Description STV 6410:
The STV 6410 is an I2C bus controlled audio and video switch
matrix, which is able to handle audio input signals up to 2 Vrms.
The used outputs are equipped with internal level adjustment
possibility. Low distortion and very good channel separation is
a typical peculiarity of this IC. The output resistance is very low
and the frequency bandwidth is up to 50 kHz.
Detailed Description UDA 1328:
The UDA1328 is a 6 channel DAC employing bitstream
conversion techniques, which can be used either in L3
microcontroller mode or in static pin mode.
The UDA 1328 supports the I2S-bus data format with word
lengths of up to 24 bits.
Digital sound features can be controlled with the L3 interface.
System clock can be set to 256fs or 384fs.
The Device also provides 2 high quality differential outputs.
Typical THD+N at 0dB is -95dB and a S/N of up to 106dB is
possible.
Supply voltage is 3V3.
Detailed Description MC 33078:
The MC33078 is a dual operational amplifier for audio
applications.
It offers low voltage noise (4,5nV/√Hz) and high frequency
performances (15MHz Gain Bandwidth product, 7V/s slew
rate).
In addition the MC33078 has a very low distortion (0,002%).
Figure 9-4
6
1959
Rear Cinch In (E4)
CVBS
5
CVBS
Rear Cinch Out
IS2
IS1
1953 CVBSFIN
Front Cinch In (E6 CVBS)
VFV
1959
7
FRONT
END
TU
6
7
7
BA7660
6
6
6
D_R
D_G
D_Y
FROM FRONT
A/V BOARD
4
1954
D_B
C
7
D_C
D_CVBS
4
FOME
3
Y
1955
Y/C Rear Out
FROM DIGITAL BOARD
6
SC2RGB_H
WSRO
4
2
5
1
5
7400
WU to
AIO1
7430
20
7
C
1955
5
7401
16 8
WSRI
11
4
5
2
Y/C Front In
(E5 SVID)
1953
WSFI
4
CFIN
BA7652
3
FROM FRONT
A/V BOARD
YFIN
3
6
4
34
I2 C
1
SDA 22
SCL 21
RIN_AUX 37
RIN_VCR 47
RIN_TV 56
RIN_STB 39
RIN_ENC 43
LIN_AUX 35
LIN_VCR 49
LIN_TV 53
LIN_STB 41
LIN_ENC 45
YIN_ENC 38
YIN_AUX 26
YCVBSIN_TV 52
CVBSIN_STB
YCVBSIN_VCR 50
YCVBSIN_ENC 36
CIN_TV 54
YCVBSIN_AUX 24
CIN_VCR 48
CIN_ENC 40
RCIN_AUX 28
RCIN_ENC 42
GIN_AUX 30
GIN_ENC 44
BIN_AUX 32
BIN_ENC 46
FBIN_AUX 18
FBIN_ENC 19
1
R/C G B/C BL SW AudInL AudOutL AudInR AudOutR
1950-2
C SWITCH
RGB SWITCH
FB SWITCH
C SWITCH
C SWITCH
6dB
6dB
6dB
6dB
6dB
L_ENC
L_STB
L_VCR
L_AUX
R_AUX
R_VCR
R_STB
R_ENC
MUTE
L_ENC
L_STB
L_TV
L_AUX
R_ENC
R_STB
R_AUX
R_TV
MUTE
L_ENC
L_STB
L_TV
L_VCR
R_VCR
R_TV
R_STB
R_ENC
MUTE
L_ENC
L_STB
L_TV
L_VCR
L_AUX
R_ENC
R_STB
R_TV
R_VCR
R_AUX
MUTE
TV SWITCH
VCR SWITCH
AUX SWITCH
CINCHSWITCH
6dB
0/6dB
-14dB
-14dB
-14dB
0/6dB
0/6dB
STEREO/
MONO
STEREO/
MONO
STEREO/
MONO
0/6dB
SLOW BLANK,
I/O MONITOR
64 ROUT_TV
2 LOUT_TV
8 AOUT_RF
60 ROUT_VCR
62 LOUT_VCR
4 ROUT_AUX
6 LOUT_AUX
58 ROUT_CINCH
59 LOUT_CINCH
31 SLB_AUX
27 SLB_VCR
25 SLB_TV
7 YCVBSOUT_VCR
5 COUT_VCR
15 YCVBSOUT_AUX
13 COUT_AUX
3 YCVBS/OUT_TV
11 FILTER
9 VOUT_RF
1 RCOUT_TV
61 BOUT_TV
63 GOUT_TV
TRAP
7507
17 FBOUT_TV
6dB
STV6410
FOME
6dB
-14dB
Y/CVBS SWITCH
CVBS_STB
CVBS/Y_ENC
CVBS/Y_AUX
CVBS/Y_TV
6dB
Y_AUX
Y_ENC
MUTE
R/C_ENC
C_ENC
C_TV
C_AUX
MUTE
Y/CVBS SWITCH
CVBS/Y_ENC
CVBS/Y_VCR
CVBS_STB
CVBS/Y_TV
Y_ENC
MUTE
R/C_ENC
C_ENC
C_VCR
C_TV
MUTE
Y/CVBS SWITCH
CVBS/Y_AUX
CVBS/Y_ENC
CVBS/Y_VCR
CVBS_STB
Y_AUX
Y_ENC
MUTE
R/C_AUX
R/C_ENC
C_ENC
C_VCR
MUTE
B_ENC
B_AUX
G_ENC
G_AUX
R/C_ENC
R/C_AUX
MUTE
4V
0V
AIO 1
4
20
(Y/CVBS)
VideoIn
19
15
1950-1
VD to
AIO1
7
16
8
6
3
1
1954
A_YCVBS
A_C
A_ B
A_G
A_R
to VIP
SAA7718
CL 16532095_113.eps
150801
4
SC1YC_H
2
R/C G B/C BL SW AudInL AudOutL AudInR AudOutR
11
VPS
(Y/CVBS)
VideoOut
SCART 1 UP TO TV / MONITOR
DVDR980-985 /0X1
Y/C Rear In
(E3)
5
BA7652
Wake
up
15
(Y/CVBS)
VideoOut
19
3
Y
(Y/CVBS)
VideoIn
SCART 2 DOWN TO VCR / SAT / DVD / DECODER
TO DIGITAL BOARD
BLOCK DIAGRAM VIDEO IN/OUT EUROPE-VERSION
Circuit-, IC Descriptions and List of Abbreviations
9.
EN 165
6410-02.EPS
I2C BUS
DECODER
AL
Figure 9-5
4
6
1900
I2S
AFCRI
AFCLI
AR
AL
Rear Cinch
1958
out
FROM
DIGITAL
BOARD
1953
Front Cinch in
FRONT
END
FROM
FRONT
A/V BOARD
3
DAC
UDA1328
12
SIF1
DVAR
DVAL
ARCLI
ARCLI
7001
41
40
38
37
15
7
7002
11
MC33078
12
2
MSP3415
8
19
ALDAC
ARDAC
30 AFER
6
3
2
4
1
I2C
1
AudInL AudOutL AudInR AudOutR
31 AFEL
8
SW
7600
16
4
CIN_VCR 48
CIN_ENC 40
RCIN_AUX 28
RCIN_ENC 42
GIN_ENC 44
CIN_TV 54
34
SDA 22
SCL 21
RIN_AUX 37
RIN_VCR 47
RIN_TV 56
RIN_STB 39
RIN_ENC 43
LIN_AUX 35
LIN_VCR 49
LIN_TV 53
LIN_STB 41
LIN_ENC 45
YIN_ENC 38
YIN_AUX 26
YCVBSIN_TV 52
CVBSIN_STB
YCVBSIN_VCR 50
YCVBSIN_ENC 36
4V
0V
C SWITCH
RGB SWITCH
FB SWITCH
C SWITCH
6dB
6dB
6dB
6dB
6dB
L_ENC
L_STB
L_VCR
L_AUX
R_AUX
R_VCR
R_STB
R_ENC
MUTE
L_ENC
L_STB
L_TV
L_AUX
R_ENC
R_STB
R_AUX
R_TV
MUTE
L_ENC
L_STB
L_TV
L_VCR
R_VCR
R_TV
R_STB
R_ENC
MUTE
L_ENC
L_STB
L_TV
L_VCR
L_AUX
R_ENC
R_STB
R_TV
R_VCR
R_AUX
MUTE
TV SWITCH
VCR SWITCH
AUX SWITCH
CINCHSWITCH
6dB
0/6dB
-14dB
-14dB
-14dB
0/6dB
0/6dB
0/6dB
STEREO/
MONO
STEREO/
MONO
STEREO/
MONO
SLOW BLANK,
I/O MONITOR
64 ROUT_TV
2 LOUT_TV
8 AOUT_RF
60 ROUT_VCR
62 LOUT_VCR
4 ROUT_AUX
6 LOUT_AUX
58 ROUT_CINCH
59 LOUT_CINCH
31 SLB_AUX
27 SLB_VCR
25 SLB_TV
7 YCVBSOUT_VCR
5 COUT_VCR
15 YCVBSOUT_AUX
13 COUT_AUX
3 YCVBS/OUT_TV
11 FILTER
9 VOUT_RF
1 RCOUT_TV
61 BOUT_TV
17 FBOUT_TV
19
63 GOUT_TV
STV6410
7507
20
(Y/CVBS) (Y/CVBS)
VideoIn VideoOut
6dB
TRAP
4
6dB
-14dB
Y/CVBS SWITCH
CVBS_STB
CVBS/Y_ENC
CVBS/Y_AUX
CVBS/Y_TV
6dB
Y_AUX
Y_ENC
MUTE
R/C_ENC
C_ENC
C_TV
C_AUX
MUTE
Y/CVBS SWITCH
CVBS/Y_ENC
CVBS/Y_VCR
CVBS_STB
CVBS/Y_TV
Y_ENC
MUTE
R/C_ENC
C_ENC
C_VCR
C_TV
MUTE
C SWITCH
Y/CVBS SWITCH
CVBS/Y_AUX
CVBS/Y_ENC
CVBS/Y_VCR
CVBS_STB
Y_AUX
Y_ENC
MUTE
R/C_AUX
R/C_ENC
C_ENC
C_VCR
MUTE
GIN_AUX 30
BIN_AUX 32
B_ENC
B_AUX
G_ENC
G_AUX
R/C_ENC
R/C_AUX
MUTE
I2C BUS
DECODER
BIN_ENC 46
FBIN_AUX 18
FBIN_ENC 19
YCVBSIN_AUX 24
1950-2
15
11
7
8
SW
6
3
2
1
ADC
7004
I2S
1900
TO
DIGITAL
BOARD
CL 16532095_114.eps
150801
UDA1360
12
1950-1
AudInL AudOutL AudInR AudOutR
to AudioLevel meter
16
R/C G B/C BL
SCART 1 UP TO TV/ MONITOR
DVDR980-985 /0X1
1705 7703
DV-Audio in
1960
FROM
AR
DVIO
BOARD
8
5
20
R/C G B/C BL
SCART 2 DOWN TO VCR/ SAT/ DVD/ DECODER
(Y/CVBS) (Y/CVBS)
VideoIn VideoOut
9.
1958
Rear Cinch in
7
BLOCK DIAGRAM AUDIO IN/OUT EUROPE-VERSION
6410-02.EPS
EN 166
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
9.4
Analog Board Nafta version
9.4.1
Microprocessor TMP93C071F
TDA 9817
The IF signal from the tuner is processed by the demodulator
IC TDA 9817 [7703]. A QSS-audio-IF signal SIF1 is generated
for demodulation in the sound processor [7600]. Audio carriers
are converted from the tuner IF level into the audio IF position
and further processed in the audio demodulator [7600]. The
AFC coil [5703] on the TDA 9817 is adjusted so that when a
frequency of 45.75 MHz is supplied to the IF output of the tuner,
the AFC voltage on pin 17 of the TDA 9817 is 2.5V. The HFAGC is set using the AGC controller [3707] so that, with a
sufficiently large antenna input signal (74 dBV) the voltage at
the IF output of the tuner [1705] pin 11 is 500 mVpp. This
setting must be carried out, when the audio carrier is switched
off. The demodulated video signal appears on pin 16 [7703].
The demodulator AGC voltage at pin4 is used to determine the
antenna signal strength after a buffer [7705] with the signal
AGC_MUTE. In the opposite direction this line may be used to
mute the demodulator to avoid crosstalk in all cases, where the
tuner signal is not needed. In this case a „high“ signal is sent
via AGC_MUTE and the conducting diode [6703] to pin4. The
video trap [1703] reduces adjacent channel video and sound
carrier remainders in the video. The demodulated video signal
VFV is available after the buffer and limiter stage for noise
peaks [7706]. The FM-PLL demodulator function of TDA 9817
is not used and deactivated by the resistor [3726].
Bus Systems
E2PROM
The E2PROM ST24E16 (Pos. 7815) is an electric erasable and
writeable, non-volatile memory. The E2PROM stores data
specific to the device, such as the AFC-reference value, clockcorrection-factor, etc. The data is accessed by the P via the
I2C-bus.
9.4.4
9.4.5
Fan Control
The fan control circuit is necessary to control the speed of the
cabinet fan (Pos. 1984) according to the requirements in
temperature and noise. The temperature is measured via an
NTC on the display board (Pos. 3145). When the temperature
is lower than 25° C the fan-voltage is approx. 5V and will reach
approx. 10V at a temperature of 40° C. It is also possible to
switch off the fan via the control line ION_FAN. The circuit
generates also two control-signals: TEMP goes to the P and
BE_FAN is the control-line for the basic engine fan.
9.4.6
Power Supply
The 5SW and 8SW supply are switched off in case of Stby from
the P via the ISTBY-line. This is possible for power-save. The
ISTBY-line must be low in case of STBY. There is also a „power
fail“ circuit on the PS-schematic which is necessary to mute
AUDIO when IPFAIL is low.
9.4.7
Audio Demodulator
Sound processor MSP 3445G
The MSP 3445G [7600] is a NTSC sound processor. Amplitude
and bandwidth of the demodulated audio signals can be
determined in the MSP using the corresponding commands via
the I2C bus. The audio signal from the tuner is available at the
pins 30 AFER and 31 AFEL.
FOME
The FOME (Follow Me) -circuit compares the video signal
coming from the tuner and the one coming from the Scart-plug
1. If the video-signals are identical the output of the FOMEcircuit is low.
Front End (TU, AP Part)
The front end comprises the following parts:
• Tuner [1705]
• IF amplifier & video demodulator IC TDA 9817 [7703]
• Sound processor MSP3445G [7600]
EN 167
IF Demodulator
The communication between the P and the other functional
groups is via the I2C-bus (SDA, SCL). The clock rate is approx.
95kHz.
Functional groups on the I2C bus:
• E2PROM ST24E16 (Pos. 7815)
• Tuner (Pos. 1705)
• Matrix-switch STV6410 (Pos. 7507)
• Audio IC / MSP (Pos. 7600)
• Display board (Pos. 1987)
9.4.3
9.
IF Selection
The IF frequency of the video carrier is 45.75 MHz. A quasi-split
audio system is used. Separate surface-wave filters (SAW) are
required. [1701] for video, [1702] for audio.
The microcontroller „AIO“ TMP93C071F is a 16bit
microcontroller with internal ROM and 8kB RAM. It includes the
following functions:
• A/D converters
• composite sync input
• I2C bus interface
The following connection to the mains, a positive pulse on the
reset input on the P is generated by the reset-IC TL7705
(Pos.7900).
The system clock is generated with the 20MHz quartz (Pos.
1994).
9.4.2
DVDR980-985 /0X1
9.4.8
Video-Routing (Nafta Version)
General Description:
The complete Video- I/O-switching is basically realised by the
I/O switch STV6410A, which is controlled via IIC-Bus-0 (SDA/
SCL) by the all in one C on the analogue board. The STV 6410
has three YCVBS, three chroma, and one RGB switch which is
not used in the Nafta I/O. All switches have 6-dB amplification
on the outputs. The YCVBS inputs have bottom clamp, the
chroma inputs have average clamp, and the RGB switch has
bottom clamp circuits at the inputs. The R/C inputs can be
switched to average clamp for chroma signals via I2C bus.
Two pre-selectors BA 7652 are additionally used: One for
switching between Y- Rear and Front, the second for switching
between Chroma- Rear and Front signal. Both pre-selectors
are controlled via IS1 and IS2 from the analogue board C.
CVBS Signals:
There are two CVBS input connection possibilities: Front
chinch (E5) and Rear Chinch In (E3). Both CVBS sources are
connected direct to the STV 6410 and routed to Rear Out 1 and
Rear Out 2 via the 75-Ohm driver BA 7623. Both CVBS output
sockets are connected to BA 7623 in parallel.
Independent of the input signal quality (CVBS, S-Video or Y/
UV) the digital board supplies also S-Video and Y/UV signals
to the corresponding sockets.
S-Video Signals:
There are also two S-Video input connection possibilities: Front
(E4) and Rear (E2) S-Video In which are connected to the preselector IC's BA 7652. One is used for Y, the other for Chroma
EN 168
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
switching. The output of the pre-selector switches is connected
to the STV 6410, and then the signal is routed via the 75-Ohm
driver BA 7623 to the Rear Out S-Video socket.
Also the video quality will be S-Video, the digital board supplies
also CVBS and Y/UV to the corresponding sockets.
Y/UV Signals:
The Y/UV In signal is routed direct to the digital board, there is
no Y/UV IN -> Y/UV Out loop through in low power standby. As
the digital board supplies only RGB signals, a RGB Y/UV
matrix is used. This matrix consists of the operational amplifier
TSH95 which generates the U and V signals according the
formulas: 2U=B-0,338R-0,661G, 2V=R-0,838G-0,161B. Then
the signals are routed to the UV Output sockets via the 75-Ohm
driver BA 7623. The corresponding Y signal is coming from the
digital board via the STV 6410. The 75 Ohm Y socket is driven
by the 75-Ohm driver BA 7623 and finally connected to the of
the Y/UV Output.
Detection of Status-Information
WSS on Y/C-Plug:
• Picture-Ratio-Information (16:9 or 4:3) on SVHSconnections is coded via the average DC-level of the
Chroma-signal-line, detection is realised by using an
analogue-input-port of the CC-C.
• ADC- value lower or equal 40h ( 4:3-picture-ratio delivered
• ADC-value greater 40h ( 16:9-picture-ratio available on
plug
• Y/C-Rear is determined via Port40/AIN3 (Pin14) of CC
(WSRI-line) and Port41/AIN4 (Pin15) is used for Y/C-Front
(WSFI-line).
Generation of Status-Information
WSS on Y/C-Plug:
The appropriate DC-level on Chroma-signal-line for Y/C-RearOut is produced via Port57 (Pin10) of the CC-C (WSRO-line).
• 4:3 - Picture-ratio supported on Y/C-Plug: Port57 set to 0
• 16:9 - Picture-ratio supported on Y/C-Plug: Port57 set to 1
9.4.9
Audio routing Analogue board (Europe / Nafta)
General Description:
The Audio- I/O switching is realised by the STV6410 I/O switch.
By I2C Bus (SDA-0/SCL-0) it is possible to control all the Audio
in- and outputs (for detailed Information we refer to the
STV6410 routing overview).
Analog audio coming from DV-Board and second rear Cinch
input is routed via MSP3415 to the STV 6410. After selecting
the audio source via STV 6410, the signal must be transformed
into the digital domain. For this, the UDA 1360TS (ADC) is
responsible. An input-voltage of up to 2Vrms can be handled
from the IC´s. For further processing, the UDA 1360TS (ADC)
delivers the data-in I2S format to the digital-board. After a
certain delay the (processed) data come back from the digital
board to the UDA 1328 (DAC). The UDA 1328 (DAC)
transforms the I2S data back into the analog domain and feeds
the signals direct to the MC33078 (OPV). From the MC33078
(OPV) the signals are delivered back to the STV 6410 and also
direct to the 2nd rear out Cinch. The other outputs (Scart,
Cinch) are supported by the STV 6410.
Detailed Description STV 6410:
The STV 6410 is an I2C bus controlled audio and video switch
matrix, which is able to handle audio input signals up to 2 Vrms.
The used outputs are equipped with internal level adjustment
possibility. Low distortion and very good channel separation is
a typical peculiarity of this IC. The output resistance is very low
and the frequency bandwidth is up to 50 kHz.
Detailed Description UDA 1360:
The UDA 1360TS is a stereo Analog-to-Digital Converter
employing bitstream conversion techniques.
The UDA supports the I2S-bus data format and the MSBjustified data format with word lengths of up to 20 bits. The IC
supports also 2Vrms input signals and is designed for 3V3
supply voltage.
The device is able to handle system clocks of 256fs and 384fs.
Typical THD+N at 0dB is -85dB and a S/N performance up to
97dB is possible.
Detailed Description UDA 1328:
The UDA1328 is a 6 channel DAC employing bitstream
conversion techniques, which can be used either in L3
microcontroller mode or in static pin mode.
The UDA 1328 supports the I2S-bus data format with word
lengths of up to 24 bits.
Digital sound features can be controlled with the L3 interface.
System clock can be set to 256fs or 384fs.
The Device also provides 2 high quality differential outputs.
Typical THD+N at 0dB is -95dB and a S/N of up to 106dB is
possible.
Supply voltage is 3V3.
Detailed Description MC 33078:
The MC33078 is a dual operational amplifier for audio
applications.
It offers low voltage noise (4,5nV/√Hz) and high frequency
performances (15MHz Gain Bandwidth product, 7V/s slew
rate).
In addition the MC33078 has a very low distortion (0,002%).
Figure 9-6
1
1997
D_B
D_G
D_R
1954
4
IS2
IS1
1953
Front Cinch In
FRONT
END
D_CVBS
D_C
D_Y
4
CVBS
CVBSFIN
VFV
V
U
10 7200
Matrix
Rear Cinch In
FROM FRONT
A/V BOARD
3
From Digital Board
5
4
2
5
5
1
1955
Y/C Rear In
WSRI
C
5
BA7652
1955
Y
YUV In
Y
3
7
YS_IN
V
4
5
U
Y/C Front In
FROM FRONT
A/V BOARD
1953
WSFI
4
5
BA7652
CFIN
7
1955
4
CIN_VCR 48
CIN_ENC 40
RCIN_AUX 28
RCIN_ENC 42
CIN_TV 54
34
SDA 22
SCL 21
RIN_AUX 37
RIN_VCR 47
RIN_TV 56
RIN_STB 39
RIN_ENC 43
LIN_AUX 35
LIN_VCR 49
LIN_TV 53
LIN_STB 41
LIN_ENC 45
YIN_ENC 38
YIN_AUX 26
YCVBSIN_TV 52
CVBSIN_STB
YCVBSIN_VCR 50
4V
0V
C SWITCH
RGB SWITCH
FB SWITCH
C SWITCH
6dB
6dB
6dB
6dB
6dB
L_ENC
L_STB
L_VCR
L_AUX
R_AUX
R_VCR
R_STB
R_ENC
MUTE
L_ENC
L_STB
L_TV
L_AUX
R_ENC
R_STB
R_AUX
R_TV
MUTE
L_ENC
L_STB
L_TV
L_VCR
R_VCR
R_TV
R_STB
R_ENC
MUTE
L_ENC
L_STB
L_TV
L_VCR
L_AUX
R_ENC
R_STB
R_TV
R_VCR
R_AUX
MUTE
TV SWITCH
VCR SWITCH
AUX SWITCH
CINCHSWITCH
0/6dB
-14dB
-14dB
-14dB
0/6dB
0/6dB
0/6dB
7 YCVBSOUT_VCR
6 LOUT_AUX
58 ROUT_CINCH
59 LOUT_CINCH
31 SLB_AUX
27 SLB_VCR
25 SLB_TV
STEREO/
MONO
STEREO/
MONO
64 ROUT_TV
2 LOUT_TV
8 AOUT_RF
60 ROUT_VCR
62 LOUT_VCR
STEREO/
MONO 4
ROUT_AUX
SLOW BLANK,
I/O MONITOR
5 COUT_VCR
15 YCVBSOUT_AUX
13 COUT_AUX
3 YCVBS/OUT_TV
11 FILTER
9 VOUT_RF
1 RCOUT_TV
63 GOUT_TV
6dB
6dB
TRAP
1955
17 FBOUT_TV
61 BOUT_TV
STV6410
6dB
-14dB
Y/CVBS SWITCH
CVBS_STB
CVBS/Y_ENC
CVBS/Y_AUX
CVBS/Y_TV
6dB
Y_AUX
Y_ENC
MUTE
R/C_ENC
C_ENC
C_TV
C_AUX
MUTE
Y/CVBS SWITCH
CVBS/Y_ENC
CVBS/Y_VCR
CVBS_STB
CVBS/Y_TV
Y_ENC
MUTE
R/C_ENC
C_ENC
C_VCR
C_TV
MUTE
C SWITCH
Y/CVBS SWITCH
CVBS/Y_AUX
CVBS/Y_ENC
CVBS/Y_VCR
CVBS_STB
Y_AUX
Y_ENC
MUTE
R/C_AUX
R/C_ENC
C_ENC
C_VCR
MUTE
GIN_AUX 30
GIN_ENC 44
BIN_AUX 32
B_ENC
B_AUX
G_ENC
G_AUX
R/C_ENC
R/C_AUX
MUTE
YCVBSIN_ENC 36
1
7516
I2C BUS
DECODER
BIN_ENC 46
FBIN_AUX 18
FBIN_ENC 19
7
7
7
BA7623
YCVBSIN_AUX 24
I2C
4
5
V_CON
U_CON
YFIN
3
C_IN
1956
4
U
6
7
7
7
1
6
7430
V
1957
FOME
BA7623
Y
YUV Out / Monitor
6
Y
1997
C
1
WSRO
A_YCVBS
A_C
A_U
A_Y
A_V
CL 16532095_115.eps
150801
1955
1997
to VIP
4
1
AIO,VD
CVBS
Rear Out 2
CVBS
Rear Out 1
Y/C Rear Out
6
to Digital Board
BLOCK DIAGRAM VIDEO IN/OUT NAFTA-VERSION
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 169
6410-02.EPS
Figure 9-7
9
I2S
1953
1959
AFCRI
DAC
UDA1328
9
AR1_IN
AL1_IN
1958
AR2_IN
AL2_IN
AFCLI
Front Cinch in
1900
FROM
FRONT
A/V BOARD
4
FROM
DIGITAL
BOARD
AR
AL
Rear Cinch in 1
AR
AL
Rear Cinch in 2
SIF1
40
7001
41
7002
MC33078
9
2
ARDAC
ALDAC
7600
30 AFER
31 AFEL
1
CIN_VCR 48
CIN_ENC 40
RCIN_AUX 28
RCIN_ENC 42
34
SDA 22
SCL 21
RIN_AUX 37
RIN_VCR 47
RIN_TV 56
RIN_STB 39
RIN_ENC 43
LIN_AUX 35
LIN_VCR 49
LIN_TV 53
LIN_STB 41
LIN_ENC 45
YIN_ENC 38
YIN_AUX 26
YCVBSIN_TV 52
CVBSIN_STB
YCVBSIN_VCR 50
YCVBSIN_ENC 36
CIN_TV 54
YCVBSIN_AUX 24
I2C
4
GIN_AUX 30
4V
0V
C SWITCH
RGB SWITCH
FB SWITCH
C SWITCH
C SWITCH
6dB
6dB
6dB
6dB
6dB
L_ENC
L_STB
L_VCR
L_AUX
R_AUX
R_VCR
R_STB
R_ENC
MUTE
L_ENC
L_STB
L_TV
L_AUX
R_ENC
R_STB
R_AUX
R_TV
MUTE
L_ENC
L_STB
L_TV
L_VCR
R_VCR
R_TV
R_STB
R_ENC
MUTE
L_ENC
L_STB
L_TV
L_VCR
L_AUX
R_ENC
R_STB
R_TV
R_VCR
R_AUX
MUTE
TV SWITCH
VCR SWITCH
AUX SWITCH
CINCHSWITCH
6dB
0/6dB
TRAP
-14dB
-14dB
-14dB
0/6dB
0/6dB
0/6dB
STEREO/
MONO
STEREO/
MONO
STEREO/
MONO
SLOW BLANK,
I/O MONITOR
64 ROUT_TV
2 LOUT_TV
8 AOUT_RF
60 ROUT_VCR
62 LOUT_VCR
4 ROUT_AUX
6 LOUT_AUX
58 ROUT_CINCH
59 LOUT_CINCH
31 SLB_AUX
27 SLB_VCR
25 SLB_TV
7 YCVBSOUT_VCR
5 COUT_VCR
15 YCVBSOUT_AUX
13 COUT_AUX
3 YCVBS/OUT_TV
11 FILTER
9 VOUT_RF
1 RCOUT_TV
61 BOUT_TV
63 GOUT_TV
6dB
17 FBOUT_TV
7507
STV6410
6dB
-14dB
Y/CVBS SWITCH
CVBS_STB
CVBS/Y_ENC
CVBS/Y_AUX
CVBS/Y_TV
6dB
Y_AUX
Y_ENC
MUTE
R/C_ENC
C_ENC
C_TV
C_AUX
MUTE
Y/CVBS SWITCH
CVBS/Y_ENC
CVBS/Y_VCR
CVBS_STB
CVBS/Y_TV
Y_ENC
MUTE
R/C_ENC
C_ENC
C_VCR
C_TV
MUTE
Y/CVBS SWITCH
CVBS/Y_AUX
CVBS/Y_ENC
CVBS/Y_VCR
CVBS_STB
Y_AUX
Y_ENC
MUTE
R/C_AUX
R/C_ENC
C_ENC
C_VCR
MUTE
GIN_ENC 44
BIN_AUX 32
B_ENC
B_AUX
G_ENC
G_AUX
R/C_ENC
R/C_AUX
MUTE
I2C BUS
DECODER
BIN_ENC 46
FBIN_AUX 18
FBIN_ENC 19
4
to AudioLevel meter
9
7004
1900
TO
DIGITAL
BOARD
CL 16532095_116.eps
150801
I2S
AR
AL
Rear Cinch
out 2 1958
AR
AL
Rear Cinch
out 1 1959
UDA1360
ADC
4
4
DVDR980-985 /0X1
5
5
FRONT
END
1705 7703
DVAR
DVAL
MSP3435
7
9.
3
AL
AR
1960
DV-Audio in
FROM
DVIO
BOARD
7
BLOCK DIAGRAM AUDIO IN/OUT NAFTA-VERSION
EN 170
Circuit-, IC Descriptions and List of Abbreviations
6410-02.EPS
Circuit-, IC Descriptions and List of Abbreviations
9.5
Digital Board
9.5.1
Record Mode
Video Part
Analog Video input signals CVBS, YC and UV(RGB for EURO
and YUV for USA) are routed via the analog board to connector
1601 and sent to IC7500 SAA7118 (Video Input Processor).
Digital video input signals (DV_IN_DATA(7:0)) are sent from
the DIVIO board through the connector 1603 and further also
to IC7500.
IC7500 (VIP) encodes the analog video to digital video and
processes the digital video to a digital video stream (CCIR656
format). This output stream (VIP_YUV[7:0]) goes to IC7403
SAA6752H (EMPRESS) and to IC7100 Versatile Stream
Manager. The latter uses the data for VBI (vertical blanking
interval) extraction.
IC7403 (EMPRESS) encodes the digital video stream into a
MPEG2 video stream that is fed to IC7100 (VSM).
Loop-Through
The multiplexed audio and video stream in the VSM is fed back
via the parallel front-end interface to IC7200 (Sti5508). This IC
decodes the MPEG stream into analog video and I2S audio.
The video and audio signals are routed to the analog board via
connectors 1601 and 1602. During recording, the recorded
signal is present at the outputs of the analog board.
9.5.2
Playback Mode
During playback, the serial data from the Basic Engine is going
directly to the Sti5505 via the serial front-end I2S interface.
The Sti5508 is a MPEG & Audio/video decoder and has the
following outputs:
• To the analog board:
–
analog video RGB, YC, CVBS
–
I2S audio (PCM format)
–
SPDIF audio (digital audio output)
• To the Progressive scan board:
–
digital video YC(7:0).
9.5.3
S2B Interface
The S2B interface between the VSM (IC7100) and the Servo
processor MACE3 controls the Basic Engine during record and
playback mode.
9.5.4
System Clock
System clocks(27MHz) of VSM, Sti5508, EMPRESS and
Progressive Scan are generated by oscillator 7906
9.5.5
Audio Clock
During record mode, the audio clock ACC_ACLK_OSC is
generated by IC7102 (PLL) because then, the audio clock must
be sychronized with the incoming video (VIP_FID) from the
VIP.
9.
EN 171
During playback mode, the audio clock ACC_ACLK_PLL is
generated by the clock synthesizer IC7900 (MK2703S).
Both ACC_ACLK_OSC(also goes to the EMPRESS as
ACLK_EMP) and ACC_ACLK_PLL are fed to the VSM. This IC
selects the appropriate clock to the STI5508. The EMPRESS
IC derives from the incoming ACLK_EMP the I2S audio
encoder clocks AE_BCLK and AE_WCLK which are sent to the
VSM.
9.5.6
On/Off
The digital board is not powered in standby mode. Control
signal ION, coming from the analog board, will enable the PSU
and power the digital board.
• ION = High: the digital board is in powered down standby
mode
• ION = Low: the power supply to the digital board is enabled
9.5.7
Audio Part
I2S audio are sent from the analog board to IC7403 EMPRESS
via connector 1602. The EMPRESS compresses I2S audio
data into an AC3 audio stream which is fed to IC7100 (VSM).
Front-End I2S
IC7100 (VSM) interfaces directly to the different hardware
modules such as Basic Engine, EMPRESS IC7403, MPEG
decoder IC7200 (Sti5508) and buffers the data streams that
are coming from or going to these hardware modules.
In IC7100 (VSM), the video MPEG2 stream and the audio AC3
stream are multiplexed into a I2S packetized stream. The serial
data are sent to the Basic Engine to be recorded.
DVDR980-985 /0X1
Reset
Control signal IRESET_DIG, controlled by the microprocessor
on the analog board is sent to the RESET LOGIC circuit.
• IRESET_DIG = Low in standby mode
• IRESET_DIG = High: the whole system is reset and the
Digital board is waked up.
9.5.8
I2C Bus
Sti5508 is master of the I2C bus. The following IC's are
controlled by the I2C bus:
• IC7201 NVRAM
• IC7403 EMPRESS
• IC7500 VIP
• IC7700 FLI2200 Video Deinterlacer Line Doubler
• IC7801 ADV7196 Video Denc
9.5.9
EMI Bus
The following IC's are connected to the External Memory
Interface bus (EMI) which functions as system bus:
• IC7301 and 7302: Flash memories which contain the
application and diagnostic software
• IC7100: VSM
• IC7200: MPEG AV Decoder
Figure 9-8
SERVO BOARD
SERVO BOARD
1100
3
1
FRONT-END I2S
PLL
74HCT9046AD
ACC_PWM VIP_FID
BE_LOADN 2
RESETn_BE 9
EMI_D(15:0)
EMI_A(21:1)
EMI_CTRL
5
7102
VIP_FID
ACC_PWM
2M*16
FLASH
4
4
7100
I2C
7301
7302
9
P_SCAN_YUV(7:0)
AD_BCLK
AD_DATAO
AD_WCLK
AD_SPDIF
R_OUT
G_OUT
B_OUT
C_OUT
CVBS_OUT
Y_OUT
7200
AD_ACLK
(playback)
AE_ACLK
(record)
4M*16
SDRAM
7300
5508_HS
5508_ODD_EVEN
HD_M_AD(13:0)
HD_M_DQ(15:0)
HD_M_CTRL
STi5508
EMI BUS
EMI_D(15:0)
EMI_A(21:1)
EMI_CONTROL
BE_LOADN
6
ANA_WE
1
6
RSTN_BE
LOAD_DVN
RSTN_DVIO
MPEG
AV
DECODER
AD_ACLK
ACLK_EMPRESS
AE_DATAI
ANALOG VIDEO
I2C BUS
SCL
SDA
AE_BCLK
AE_WCLK
5
DIGITAL VIDEO
AUDIO PCM I2S & SPDIF
6
6
7403
7401
VIP_HS
VIP_VS
VIP_ICLK
ACLK_EMP
SAA6752H
EMPRESS
SMD(15:0)
SMA(17:0)
SM_CTRL
256K*16
SRAM
VIP_YUV(7:0)
I2S AUDIO
AC3
A_EMPRESS(13:0)
D_EMPRESS(15:0)
SD_CTRL
7402
OPTION
DIGITAL VIDEO(CCIR656)
SCL
SDA
D_PAR_D(7:0)
D_PAR_CTRL
SCL
SDA
7201
CTRL
4M*16
SDRAM
9 SYSCLK_EMPRESS
2
VIDEO MPEG2
9
MUTEN
NVRAM
5
9
9
6
2
AD_ACLK
ACC_ACLK_OSC
VIP_YUV(7:0)
AE_BCLK_VSM
AE_WCL_VSM
AE_DATAO
DSn
DTACKn
VE_DATA(7:0)
UART1
UART2
SYSCLK_VSM
VIP_ICLK
D_PAR_D(7:0)
D_PAR_CTRL
VERSATILE
STREAM
MANAGER
VSM_M_A(13:0)
VSM_M_D(15:0)
VSM_M_CTRL
BE_BCLK
BE_WCLK
BE_DATA_RD
BE_DATA_WR
BE_SYNC
BE_FLAG
BE_V4
UART3
BE_FAN 6
S2B
4M*16
SDRAM
7101
4
SYSCLK_VSM_5508
VIP_ICLK
VIP_FID
7701-7702
VS
EXTRACTOR
I2C
7
CLOCK & SYNC
1
5
8
9
ADDRESS
1
7900
8
7
4
2
7700
5
7501
CLK_27MHZ
HSOUT
VSOUT
V_OUT(9:0)
U_OUT(9:0)
SYSCLK_PROGSCAN
SYSCLK_VSM_5508
7904
CLOCK
BUFFER
9
7801
7906
I2C
27MHz
OSC
SCL
SDA
DAC_C
DAC_B
DAC_A
RESETn_DVIO
RESETn_BE
RESETn
LOW
PASS
LOW
PASS
LOW
PASS
9
7902
Cb
Cr
Y
1603
5
1
BE_FAN
VIP_FB
RESET
LOGIC
7702
2
2
6
RSTN_DVIO
RSTN_BE
IRESET_DIG
VIDEO
FILTER
2
2
MUTEN
AE_BCLK
AE_WCLK
AE_DATAI
8
-5V
+5V
+12V
+3V3
ION
1900
1901
1800
1602
1601
1600
cl 26532011_025.eps
160102
6
2 AE_ACLK
2 AD_ACLK
8
ION
IRESET_DIG
ANA_WE
RS232 GATEWAY TO ANALOG BOARD
RESET
7803
7803
7802
I 2 S AUDIO IN
9
RESETN_DIVIO
ANALOG VIDEO
2
LOAD_DVN
VIDEO
FILTERS AMPLIFIER
+5V +3V3 +12V
ADV7196
VIDEO DENC
Y_OUT(9:0)
6
VIP_FB
SYSCLK_PROGSCAN
2
SYSCLK_EMPRESS
MK2703S
1
ACC_ACLK_PLL
CLK_27MHZ
FRAME_IN
VS_IN
HS_IN
YUV_IN(7:0)
SCL
SDA
7800
CTRL
FLI2200
VIDEO
DEINTERLACER
LINE DOUBLER
DATA
7500
V_IN_7118
R_IN_7118
U_IN_7118
B_IN_7118
Y_IN_7118
G_IN_7118
C_IN_7118
CVBS_Y_IN_7118_A
CVBS_Y_IN_7118_B
CVBS_Y_IN_7118_C
SDRAM
64M*32
SAA7118
VIP
DV_IN_DATA(7:0)
DV_IN_VS
DV_IN _HS
DV_IN_CLK
SYSCLK_PROGSCAN
I2C
SCL
SDA
VIP_YUV(7:0)
VIP_HS
VIP_FID
VIP_VS
VIP_ICLK
24M576
RS232 DIVIO GATEWAY
6
DVIO BOARD
ANALOG
BOARD
ANALOG
BOARD
ANALOG
BOARD
ANALOG
BOARD
DVDR980-985 /0X1
SERVICE
INTERFACE
9.
POWER SUPPLY
EN 172
Circuit-, IC Descriptions and List of Abbreviations
Block Diagram Digital Board
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 173
Description DIVIO Module
Description
The progressive scan part is integrated in the Digital Board and
built around the SAGE Fli2200 de-interlacer / line doubler
(7701). This I2C controlled de-interlacer uses a 64Mbit SDRAM
(32bit x 2M) to perform high quality deinterlacing (meshing).
The de-interlacer gets his digital YUV input data from the
STi5508 (7200). The format of the digital YUV input to the
SAGE is CCIR656 with separated Hsync, Vsync and odd/even
signal running on 27Mhz.
Because the STi5508 doesn't have a Vsync output the odd/
even output of this IC has to be translated to a Vsync signal.
Some glue logic has been added to extract the vertical sync.
The glue logic circuit consists of Flip-Flop IC 74HC74D (7701)
and EXOR 74LVC86 (7702). The next diagram shows how the
vertical sync is extracted.
ADC (analog PCB)
Analog
audio L+R
LED
IEEE1394
camcorder
Front DV PCB
9.5.10 Progressive Scan
Audio
Encoder
(dig. PCB)
On/Off
DVIO Module
Digital video
CCIR656
IEEE1394
Control Misc.
HS_IN
VS_IN
CL 16532095_123.eps
150801
Figure 9-9
The output of the de-interlacer (4:4:4 progressive video) is fed
to the Analog Devices ADV71967 MacroVision compliant
DENC (7801).
The YUV current output of the DENC is fed via a low pass filter
to the single supply output opamps AD8061/8062 (7802-7803).
The analog video is fed via a 7 poled flex to the analog board
where the YUV 2FH cinch connectors are located.
9.6
Divio Board
9.6.1
Short Description of the Module:
The DVIO Module is a decoder for DV streams. The module is
intended for the Philips DVDR1000/002 en DVDR1000/172
DVD+RW recorders. Input is a stream from a DV-camcorder
IEEE1394. Outputs are CCIR656 Video and Analog audio
(L+R). A serial control interface is present.
The following picture shows the location of the DVIO Module
inside the DVDR set.
Control RS232
CL 16532095_118.eps
150801
Figure 9-10
pin 6 IC7102
Video
Encoder
(dig. PCB)
Host decoder STi5505
(dig. PCB)
Vertical Sync
FRAME_IN
(odd/even)
Digital
Audio I2S
Figure 9-11
LED
INPUT
1101
PDI1394
P25
PHY
11.05 MHz
RXD
TXD
RTSN
CTSN
Microprocessor
P89C51RD
2 MICROPROCESSOR
24.576 MHz
4
Isolated domain
SERIAL INTERFACE
7203
7101
uP BUS
PDI1394
L21
LINK
SRAM
7103
7201
9
LINK DATA
CLOCKGENAUD
CLKAUDTMP
LINK CONTROLE
7300
ROM
27 MHz
7304
7303
AUD_SDO
AUD_SDI
AUD_SDI
2
DIGITAL
VIDEO AUD_BCLK
STREAM AUD_WS
DV DECODER
NW700
FPGA/EPLD
CLOCK27M
(SYSTEM CLOCK)
HOST
AD
BUS
CLK27M_DV
7404
DV_HS_OUT
DV_VS
SRAM
2
7301
YUV(7:0)
AUDIO DAC
UDA1334ATS
AUD_SDI
AUD_BCLK
AUD_WS
CLOCK DELAY
7500
5 AUDIO & VIDEO OUTPUT
2
7506
ANALOG AUDIO RIGHT
ANALOG AUDIO LEFT
TRISTATE BUFFER
7505
DV_HS_OUT
DV_VS
CL 16532145_020.eps
211101
SERIAL INTERFACE
AUD_SDI
AUD_BCLK
AUD_WS
YUV(7:0)
CLK27M
1501
1500
DVDR980-985 /0X1
1 1394 INTERFACE
7307
CLOCKGENVID
CLK27M_CON
DRAM
7402 - 7403
9.
Tuneable audio clock
(+/- 256 x fs)
Tuneable clock
(+/- 27Mhz)
7308
4 DV CODEC
9.6.2
3 FIFO & CONTROL
EN 174
Circuit-, IC Descriptions and List of Abbreviations
Block Diagram
Block Diagram DVIO
Circuit-, IC Descriptions and List of Abbreviations
The DVIO module consists of the following blocks (see
blockdiagram):
1. IEEE1394 Interface
• PDI1394P25(7101)
• PDI1394L40(7103)
2. Micro-controller
• 89C51RD2(7203)
• 32kb SRAM(7201)
3. FIFO and Control
• FPGA/EPLD(7303)
• SRAM(7301)
• Clock generation(7307, 7308)
–
Independently tuneable audio and video clock,
implemented with FPGA and PLL
4. DV-Decoder
• NW700(7404)
• EDO DRAM(7402, 7403)
5. Audio & Video output
• Audio DAC UDA1334ATS(7602)
• Clock delay(7500)
• Tristate buffer(7505)
9.
EN 175
Reset
The FPGA controls the reset signals on the board. This has the
advantage that it is possible to reset the board both from
software and hardware.
Reset
SOFTWARE RESET
89C51RD+
NRESET
FPGA
PDI1394L21
DVIO BOARD
Functional Description
DIGITAL BOARD
9.6.3
DVDR980-985 /0X1
NW701
CL 16532095_120.eps
150801
IEEE1394 Interface
The 1394 interface consists of a PDI1394P25 physical layer
and a PDI1394L40 link layer.
It has the following features:
• S200 operation (200 megabit per second)
• One i.Link port (4 pin)
• AV link port
Micro-Controller
The 89C51RD2 processor has a 8051 cpu with the following
extra features:
• 64 kilobyte of flash memory as program memory
• 1 kilobyte of internal data memory
• watchdog timer
• PCA outputs
• Power control modes
• Speed allowed up to 33 MHz but used at 11.0592 MHz
• On board ISP(In Circuit Programming) functionality
ISP
By use of In Circuit Programming, it is possible to update the
software of the DVIO board that is in the 89C51RD2. ISP can
be made active by resetting the processor and keeping the
ISPN pin low during reset. During ISP, the ISPN signal on the
board has to be kept low. A programming voltage of 5V is
always present at the Vpp pin. When the ISP mode is active,
the new program can be sent to the microprocessor through
the serial port.
Figure 9-12
The board reset NRESET will reset the whole board, and the
software reset can reset everything except the microprocessor
itself. Power-on reset is implemented by adding pull-ups and
pull-downs to the reset inputs of the devices. Since the FPGA
will tri-state all the pins during configuration, reset is active
during configuration time. After configuration of the FPGA, the
reset signals are driven inactive. The NRESET signal is used
to reset the DVIO board. After reset, the tri-state buffers to
connector 1500 are disabled.
Clock Circuit
There are 2 clocks to consider in the system, this is the video
clock and the audio clock. These two clocks do not have a
relation, so these clocks must be considered independently.
The video clock is approximately 27 MHz. When data is flowing
from an external source that is supposed to have the same
frequency, it does not have exactly the same clock. Because of
this, buffers may under-run of over-run. Since the clock can not
be directly recovered from the 1394 interface, there has to be
another solution. This solution is a tuneable clock that is
adjusted to the required frequency to process at the rate of the
incoming data.
The hardware implementation of such a tuneable clock is as
follows:
Clock Circuit
Fifo and Control
In decode mode, an isochronous AV-stream is flowing through
the IEEE1394 Interface into the FPGA. The FPGA stores the
data in a FIFO buffer (ping-pong buffer type, i.e. 2 buffers that
can hold one whole frame each).
ClockGen
Raw clock
PLL
(CY2071)
regular clock
slowloopfilter
(FPGA)
CL 16532095_121.eps
150801
Figure 9-13
The same can be applied for the audio clock. For this clock, a
frequency of 8.192 MHz, 11.2896 MHz or 12.228 MHz is
required. This depends on the sample-rate frequency(32kHZ,
44.1kHZ or 48kHZ)of the audio signal.
EN 176
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
DV Decoder
The AV-data will go from the FIFO to the NW700. The NW700
decodes the stream into video data in 656 format and audio
data in I2S format.
The microprocessor has the ability to read the status registers
of the NW700 through the FPGA. By reading these registers,
extra data from the DV stream, that is not decoded into audio
or video, can be sent to the digital board using pin TXD of the
serial interface. This data includes time stamp and some more.
Audio & Video Output
The audio I2S data are sent to audio DAC UDA1334. Analog
audio left and right signals are connected to the analog board.
The tristate buffer enables the digital video stream to the Video
Input Processor on the digital board when the DV source is
selected.
The clock delay synchronizes the AV clock with the AV data at
the output.
Circuit-, IC Descriptions and List of Abbreviations
9.7
IC’s Analog Board
9.7.1
IC7001: UDA1328T
DVDR980-985 /0X1
Multi-channel filter DAC
1
1.1
9.
EN 177
UDA1328T
FEATURES
General
• 2.7 to 3.6 V power supply
• 5 V tolerant TTL compatible inputs
• Selectable control via L3 microcontroller interface or via
static pin control
• Multi-channel integrated digital filter plus non-inverting
Digital-to-Analog Converter (DAC)
• Supports sample frequencies between 5 and 100 kHz
2
• Digital silence detection (output)
This multi-channel DAC is eminently suitable for DVD-like
applications in which 5.1 channel encoded signals are
used.
• Slave mode only applications
APPLICATIONS
• No analog post filtering required for DAC
• Easy application.
1.2
3
Multiple format input interface
• I2S-bus, MSB-justified and LSB-justified format
compatible (in L3 mode)
• I2S-bus and LSB-justified format compatible
• 1fs input format data rate.
1.3
Multi-channel DAC
• 6-channel DAC with power on/off control
• Digital logarithmic volume control via L3; volume can be
set for each of the channels individually
• Digital de-emphasis for 32, 44.1, 48 and 96 kHz fs via
L3 and, for 32, 44.1 and 48 kHz in static mode
• Soft or quick mute via L3
• Output signal polarity control via L3 microcontroller
interface.
1.4
GENERAL DESCRIPTION
The UDA1328 is a single-chip 6-channel DAC employing
bitstream conversion techniques, which can be used either
in L3 microcontroller mode or in static pin mode.
The UDA1328 supports the I2S-bus data format with word
lengths of up to 24 bits, the MSB-justified data format with
word lengths of up to 24 bits and the LSB-justified serial
data format with word lengths of 16, 18, 20 and 24 bits.
All digital sound processing features can be controlled with
the L3 interface e.g. volume control, selecting digital
silence type, output polarity control and mute. Also system
features such as power control, digital silence detection
mode and output polarity control.
Under static pin control, via static pins, the system clock
can be set to either 256fs or 384fs support, digital
de-emphasis can be set, there is digital mute and the
digital input formats can also be set.
Advanced audio conÞguration
• 6-channel line output (under L3 volume control)
• A stereo differential output (channel 1 and channel 2) for
improved performance
• High linearity, wide dynamic range, low distortion.
4
ORDERING INFORMATION
TYPE
NUMBER
UDA1328T
PACKAGE
NAME
SO32
DESCRIPTION
plastic small outline package; 32 leads; body width 7.5 mm
VERSION
SOT287-1
EN 178
9.
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
Multi-channel filter DAC
6
UDA1328T
BLOCK DIAGRAM
handbook, full pagewidth
VDDD
VSSD
21
20
9
UDA1328T
23
BCK
WS
DATAI12
DATAI34
DATAI56
10
24
11
12
CONTROL
INTERFACE
DIGITAL
INTERFACE
13
25
18
19
17
14
26
VOLUME/MUTE/DE-EMPHASIS
STATIC
MUTE
DEEM1
DEEM0
L3CLOCK
L3DATA
L3MODE
DS
INTERPOLATION FILTER
TEST1
SYSCLK
VOUT1P
VOUT1N
27
8
16
22
6-CHANNEL NOISE SHAPER
DAC
28
DAC
31
DAC
VOUT3
1
2
5
7, 15
3
30
MGR979
VDDA
VOUT2P
VOUT2N
n.c.
VOUT4
DAC
4
6
TEST2
DAC
DAC
VOUT5
32
29
TEST3
VSSA
Vref
VOUT6
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
Multi-channel filter DAC
7
9.
UDA1328T
PINNING
SYMBOL
PIN
EN 179
DESCRIPTION
VOUT3
1
channel 3 analog output
VOUT4
2
channel 4 analog output
VSSA
3
analog ground
VOUT5
4
channel 5 analog output
VOUT6
5
channel 6 analog output
VDDA
6
analog supply voltage
n.c.
7
not connected (reserved)
TEST3
8
test output 3
VOUT3 1
32 VOUT2P
STATIC
9
static mode/L3 mode switch input
VOUT4 2
31 VOUT2N
BCK
10
bit clock input
WS
11
word select input
DATAI12
12
data input channel 1 and 2
DATAI34
13
data input channel 3 and 4
DATAI56
14
data input channel 5 and 6
n.c.
15
not connected (reserved)
SYSCLK
16
system clock: 256fs, 384fs,
512fs and 768fs
L3MODE
17
L3 mode selection input
L3CLOCK
18
L3 clock input
L3DATA
19
L3 data input
VSSD
20
digital ground
VDDD
21
TEST2
handbook, halfpage
VSSA 3
30 Vref
VOUT5 4
29 VOUT1N
VOUT6 5
28 VOUT1P
VDDA 6
27 TEST1
n.c. 7
26 DS
TEST3 8
25 DEEM0
UDA1328T
STATIC 9
24 DEEM1
BCK 10
23 MUTE
WS 11
22 TEST2
DATAI12 12
21 VDDD
digital supply voltage
DATAI34 13
20 VSSD
22
test output 2
DATAI56 14
19 L3DATA
MUTE
23
static mute control input
DEEM1
24
DEEM control 1 input
(static mode)
DEEM0
25
L3 address select
(L3 mode)/DEEM control 0 input
(static mode)
DS
26
digital silence detect output
TEST1
27
test input 1
VOUT1P
28
channel 1 analog output P
VOUT1N
29
channel 1 analog output N
Vref
30
DAC reference voltage
VOUT2N
31
channel 2 analog output N
VOUT2P
32
channel 2 analog output P
n.c. 15
18 L3CLOCK
SYSCLK 16
17 L3MODE
MGR980
Fig.2 Pin configuration.
EN 180
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Multi-channel Þlter DAC
8
UDA1328T
8.4
FUNCTIONAL DESCRIPTION
8.1
System clock
The UDA1328 operates in slave mode only, this means
that in all applications the system must provide the system
clock. The system frequency is selectable. The options are
256fs, 384fs, 512fs and 768fs for the L3 mode and 256fs or
384fs for the static mode. The system clock must be
frequency-locked to the digital interface signals.
It should be noted that the UDA1328 can operate from
5 to 100 kHz sampling frequency (fs). However in 768fs
mode the sampling frequency must be limited to 55 kHz.
8.2
Application modes
Operating mode can be set with the STATIC pin, either to
L3 mode (STATIC = LOW) or to the static mode
(STATIC = HIGH). See Table 1 for pin functions in the
static mode.
Table 1
Mode selection in the static mode
PIN
L3 MODE
STATIC MODE
L3CLOCK
L3CLOCK
clock select
L3MODE
L3MODE
SF1(1)
L3DATA
SF0(1)
MUTE
X(2)
MUTE
DEEM1
X(2)
DEEM1
DEEM0
L3ADR
DEEM0
L3DATA
Notes
1. SF1 and SF0 are the Serial Format inputs (2-bit).
2. X means that the pin has no function in this mode and
can best be connected to ground.
8.3
Interpolation Þlter (DAC)
The digital filter interpolates from 1 to 128fs by cascading
a half-band filter and a FIR filter, see Table 2. The overall
filter characteristic of the digital filters is illustrated in Fig.3,
and the pass-band ripple is illustrated in Fig.4. Both figures
are with a 44.1 kHz sampling frequency.
Table 2
Interpolation Þlter characteristics
ITEM
CONDITION
VALUE (dB)
Pass-band ripple
0 to 0.45fs
±0.02
>0.55fs
−55
0 to 0.45fs
>114
−
−3.5
Stop band
Dynamic range
DC gain
Digital silence detection
The UDA1328 can detect digital silence conditions in
channels 1 to 6, and report this via the output pin DS. This
function is implemented to allow for external manipulation
of the audio signal in the absence of program material,
such as muting or recorder control.
An active LOW output is produced at the DS pin if the
channels selected via L3 or for all channels in static mode,
carries all zeroes for at least 9600 consecutive audio
samples (equals 200 ms for fs = 48 kHz). The DS pin is
also active LOW when the output is digitally muted either
via the L3 interface or via the STATIC pin.
In static mode all channels participate in the digital silence
detection. In L3 mode control each channel can be set,
either to participate in the digital silence detection or not.
8.5
Noise shaper
The 3rd-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a Filter
Stream DAC (FSDAC).
8.6
Filter stream DAC
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. No post-filter is needed due to
the inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally
with the power supply voltage.
8.7
Static mode
The UDA1328 is set to static mode by setting the STATIC
pin HIGH. The function of 6 pins of the device now get
another function as can be seen in Table 1.
8.7.1
SYSTEM CLOCK SETTING
In static mode pin 18 (L3CLOCK) is used to select the
system clock setting. When pin 18 is LOW, the device is in
256fs mode, when pin 18 is HIGH the device is in 384fs
mode.
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
Multi-channel filter DAC
8.7.2
8.8
In static pin mode the pins DEEM0 and DEEM1 control the
de-emphasis mode; see Table 3.
DEEM1
DEEM0
No de-emphasis
0
0
32 kHz de-emphasis
0
1
44.1 kHz de-emphasis
1
0
48 kHz de-emphasis
1
1
DIGITAL INTERFACE FORMATS
In static pin mode the digital audio interface formats can be
selected via pin 17 (SF1) and 19 (SF0). The following
interface formats can be selected (see also Table 4):
• I2S-bus with data word length of up to 24 bits
• LSB-justified format with data word length of
16, 20 or 24 bits.
Table 4
L3 mode
The device is set to L3 mode by setting the STATIC pin to
LOW. The device can then be controlled via the L3
microcontroller interface (see Chapter 9).
De-emphasis control
DEEM MODE
8.7.3
EN 181
UDA1328T
DE-EMPHASIS CONTROL
Table 3
9.
Input format selection in the static mode
SF1
SF0
I2S-bus
INPUT FORMAT
0
0
LSB-justiÞed 16 bits
0
1
LSB-justiÞed 20 bits
1
0
LSB-justiÞed 24 bits
1
1
It should be noted that the digital audio interface holds that
the BCK frequency can be 64 times the WS maximum
frequency, or fBCK ≤ 64 × fWS
8.8.1
DIGITAL INTERFACE FORMATS
The following interface formats can be selected in the
L3 mode:
• I2S-bus with data word length of up to 24 bits
• MSB-justified with data word length of up to 24 bits
• LSB-justified format with data word length of 16, 18,
20 or 24 bits.
8.8.2
L3 ADDRESS
The UDA1328 can be addressed via the L3 microcontroller
interface using one of two addresses. This is done in order
to individually control the UDA1328 and other Philips
DACs or CODECs via the same L3 bus.
The address can be selected using pin 25 (DEEM0) in
L3 mode. When pin 25 is set LOW, the address is 000100.
When pin 25 is set HIGH the address is 000101.
EN 182
9.7.2
9.
DVDR980-985 /0X1
IC7004: UDA1360TS
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 183
EN 184
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 185
EN 186
9.7.3
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
IC7430: BA7660FS
3-channel 75Ω driver
BA7660FS
The BA7660FS is a 75Ω driver with a 6dB amplifier and three internal circuits, and provides 75Ω drive of composite
Y signals and C signals, as well as RGB signals. Each load is capable of driving two circuits, and a sag correction
function reduces the capacitance of the output coupling capacitor.
The input voltage is within a range of 0V to 1.5V, enabling direct connection of ordinary D / A converter output. An
internal power-saving circuit is also included which provides simultaneous muting on all three channels, and output
pin shorting protection.
Applications
•DVDs,
set top boxes and other digital video devices
•1)Features
Can be coupled directly to D / A converter output.
6) An internal sag correction function makes it possible
to reduce the capacitance of the output coupling
capacitor.
7) Each load is capable of driving two circuits.
8) The compact 16-pin SSOP-A package is used.
2) Operates at a low power consumption (115mW typ.).
3) Internal output muting circuit.
4) Internal power-saving circuit.
5) Internal output protection circuit.
•Absolute maximum ratings (Ta = 25C)
Parameter
Symbol
Power supply voltage
Vcc
8
V
Power dissipation
Pd
650
mW
Topr
– 25 ~ + 75
°C
Tstg
– 55 ~ + 125
°C
Operating temperature
Storage temperature
Limits
Unit
•Recommended operating conditions (Ta = 25C)
Parameter
Operating power supply voltage
Symbol
Min.
Typ.
Max.
Unit
Vcc
4.5
5.0
5.5
V
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
•Block diagram
MUTE 1
16 VCC
15 OUTA1
INA
2
GND
3
INB
4
GND
5
12 OUTB2
N.C.
6
11 N.C.
INC
7
GND
8
6dB
75Ω
14 OUTA2
6dB
6dB
75Ω
75Ω
13 OUTB1
10 OUTC1
9 OUTC2
MUTE (1pin)
H
3ch MUTE
L
NORMAL
9.
EN 187
EN 188
9.
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
•Pin descriptions and input / output circuits
Pin. No
Pin name
IN
OUT
Reference
voltage
Equivalent circuit
Function
Muting control
1
MUTE
—
15k
—
If MUTE (pin 1) is set to HIGH, muting
is carried out simultaneously on all
three channels.
8k
Signal input
2
4
7
INA
INB
INC
3
5
8
GND
14
12
9
OUTA2
OUTB2
OUTC2
15
13
10
OUTA1
OUTB1
OUTC1
16
VCC
—
—
—
Input
video
RGB,
within
(typ.).
—
0V
signals consist of composite
signals, Y signals, C signals,
and others. The input level is
a range of 0 to 1.3 (min.) to 1.5
Ground
GND
0.9V
Signal output
14pin
12pin
9pin
The signal output level is (0.9 + 2 ×
input voltage [V]). Pins 9, 12, and 14
are the pins for sag correction. If pins
10, 13, and 15 are set to 0.2V or less,
the protective circuit is triggered and
the power-saving mode is accessed.
—
0.95V
15pin
13pin
10pin
Vcc
—
—
5.0V
Power supply
Circuit-, IC Descriptions and List of Abbreviations
9.7.4
DVDR980-985 /0X1
9.
EN 189
IC7507: STV6410
STV6410
AUDIO/VIDEO SWITCH MATRIX
..
.
..
..
..
.
..
.
..
.
I2C BUS CONTROL
STANDBY MODE
VIDEO SECTION
5 CVBS INPUTS, 4 CVBS OUTPUTS (ONE
WITH SELECTABLE CHROMA TRAP FILTER)
5 Y/C INPUTS, 3 Y/C OUTPUTS
6dB GAIN ON ALL CVBS/Y AND C OUTPUTS
1 Y/C ADDER
2 RGB/FB INPUTS, 1 RGB/FB OUTPUT WITH
6dB ADJUSTABLE GAIN
VIDEO MUTING ON ALL THE OUTPUTS
3 SLOW BLANKING INPUTS/OUTPUTS
SYNC BOTTOM CLAMP ON ALL CVBS/Y
AND RGB INPUTS, AVERAGE ON C INPUTS
BANDWIDTH : 15MHz
CROSSTALK : 60dB Typ.
AUDIO SECTION
5 STEREO INPUTS, 4 STEREO OUTPUTS
(TWO WITH LEVEL ADJUSTMENT)
MONO SOUND OUTPUT
MONO SOUND CAPABILITY ON TV OUTPUTS
AUDIO MUTING ON ALL THE OUTPUTS
TQFP64
(Plastic Quad Flat Pack)
ORDER CODE : STV6410D
DESCRIPTION
The STV6410 is a highly integrated I2C bus-controlled audio and video switch matrix, optimized for
use in digital set-top box applications. It provides
all the audio and video routings required in a full
three scart set-top box design. It is also fully pin
compatible with STV6411, the two scart version.
December 1997
1
EN 190
9.
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
STV6410
FILTER
GNDV3
VOUT_RF
AOUT_RF
YCVBSOUT_VCR
LOUT_AUX
COUT_VCR
ROUT_AUX
YCVBSOUT_TV
LOUT_TV
RCOUT_TV
11
10
9
8
7
6
5
4
3
2
1
FBOUT_TV
17
64
ROUT_TV
FBIN_AUX
18
63
GOUT_TV
FBIN_ENC
19
62
LOUT_VCR
ADD
20
61
BOUT_TV
SCL
21
60
ROUT_VCR
SDA
22
59
LOUT_CINCH
VCC12
23
58
ROUT_CINCH
YCVBSIN_AUX
24
57
GNDA
43
44
45
46
47
48
GIN_ENC
LIN_ENC
BIN_ENC
RIN_VCR
CIN_VCR
LIN_VCR
RIN_ENC
YCVBSIN_VCR
49
42
50
32
RCIN_ENC
31
BIN_AUX
41
SLB_AUX
LIN_STB
V REF
40
51
CIN_ENC
30
39
YCVBSIN_TV
GIN_AUX
RIN_STB
52
38
29
YIN_ENC
LIN_TV
GNDV1
37
53
RIN_AUX
28
36
CIN_TV
RCIN_AUX
YCVBSIN_ENC
54
35
27
LIN_AUX
V CCA
SLB_VCR
34
RIN_TV
55
33
56
26
VCC1
25
CVBSIN_STB
SLB_TV
YIN_AUX
6410-01.EPS
COUT_AUX
VCC3
GNDV2
14
12
YCVBSOUT_AUX
15
13
VCC2
16
PIN CONNECTIONS
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
Symbol
RCOUT_TV
LOUT_TV
YCVBSOUT_TV
ROUT_AUX
COUT_VCR
LOUT_AUX
YCVBSOUT_VCR
AOUT_RF
VOUT_RF
GNDV3
FILTER
VCCV3
COUT_AUX
GNDV2
YCVBSOUT_AUX
Description
Red/chroma Output, to TV Scart
Audio Left Output, to TV Scart
Y/CVBS Output, to TV scart
Audio Right Output, to AUX Scart
Chroma Output, to VCR Scart
Audio Left Output, to AUX Scart
Y/CVBS Output, to VCR Scart
Audio (L+R) Output to RF Modulator
Video (CVBS) Output to RF Modulator
Video Switches Ground 3
Chroma Trap Filter
Video Switches Supply 3 (8V)
Chroma Output, to AUX Scart
Video Switches Ground 2
Y/CVBS Output, to AUX Scart
6410-01.TBL
PIN LIST
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 191
STV6410
PIN LIST (continued)
Pin Number
Symbol
16
17
18
19
20
V CCV2
FBOUT_TV
FBIN_AUX
FBIN_ENC
ADD
Description
21
22
SCL
SDA
23
24
25
VCC12
YCVBSIN_AUX
SLB_TV
26
27
YIN_AUX
SLB_VCR
Y Input, from AUX Scart
Slow Blanking Input/Ouput from VCR
28
29
30
31
32
33
RCIN_AUX
GNDV1
GIN_AUX
SLB_AUX
BIN_AUX
V CCV1
Red/Chroma Input, from AUX Scart
Video Switches Ground 1
Green Input, from AUX Scart
Slow Blanking Input/Ouput from AUX
Blue Input, from AUX Scart
Video Switches Supply 1 (8V)
34
35
36
CVBSIN_STB
LIN_AUX
YCVBSIN_ENC
37
38
39
40
RIN_AUX
YIN_ENC
RIN_STB
CIN_ENC
Audio Right Input, from AUX Scart
Y Input, from Encoder
Audio Right Input, from STB
Chroma Input, from Encoder
41
42
43
LIN_STB
RCIN_ENC
RIN_ENC
Audio Left Input, from STB
Red/Chroma Input, from Encoder
Audio Right Input, from Encoder
44
45
46
47
48
49
50
51
GIN_ENC
LIN_ENC
BIN_ENC
RIN_VCR
CIN_VCR
LIN_VCR
YCVBSIN_VCR
V REF
Green Input, from Encoder
Audio Left Input, from Encoder
Blue Input, from Encoder
Audio Right Input, from VCR Scart
Chroma Input, from VCR Scart
Audio Left Input, from VCR
Y/CVBS Input from VCR Scart
Voltage Reference Decoupling
52
53
YCVBSIN_TV
LIN_TV
54
55
56
57
CIN_TV
V CCA
RIN_TV
GNDA
58
59
60
61
62
63
64
ROUT_CINCH
LOUT_CINCH
ROUT_VCR
BOUT_TV
LOUT_VCR
GOUT_TV
ROUT_TV
Video Switches Supply 2 (8V)
Fast Blanking Output, to TV Scart
Fast Blanking Input, from AUX Scart
Fast Blanking Input, from Encoder
I2C Bus IC Address Programmation
I2C Bus Clock
I2C Bus Data
Slow Blanking Power Supply (12V)
Y/CVBS Input from AUX Scart
Slow Blanking Input/Ouput from TV
CVBS Input from STB
Audio Left Input, from AUX Scart
Y/CVBS Input from Encoder
Y/CVBS Input, from TV Scart
Audio Left Input, from TV Scart
Chroma Input, from TV Scart
Audio Switches Supply (8V)
Audio right input, from TV Scart
Audio Switches Ground
6410-01.TBL
Audio Right Output, to CINCH
Audio Left Output, to CINCH
Audio Right Output, to VCR sCart
Blue Output, to TV Scart
Audio Left Output, to VCR Scart
Green Output, to TV Scart
Audio Right Output, to TV Scart
3
EN 192
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
STV6410
BLOCK DIAGRAM
STV6410
FB SWITCH
FBIN_ENC 19
4V
0V
17 FBOUT_TV
FBIN_AUX 18
RGB SWITCH
B_ENC
B_AUX
G_ENC
G_AUX
R/C_ENC
R/C_AUX
MUTE
BIN_ENC 46
BIN_AUX 32
GIN_ENC 44
6dB
61 BOUT_TV
6dB
63 GOUT_TV
6dB
1 RCOUT_TV
C SWITCH
R/C_AUX
R/C_ENC
C_ENC
C_VCR
MUTE
GIN_AUX 30
RCIN_ENC 42
RCIN_AUX 28
Y/CVBS SWITCH
CVBS/Y_AUX
CVBS/Y_ENC
CVBS/Y_VCR
CVBS_STB
Y_AUX
Y_ENC
MUTE
CIN_ENC 40
CIN_VCR 48
YCVBSIN_AUX 24
TRAP
11 FILTER
3 YCVBS/OUT_TV
6dB
C SWITCH
R/C_ENC
C_ENC
C_VCR
C_TV
MUTE
CIN_TV 54
Y/CVBS SWITCH
CVBS/Y_ENC
CVBS/Y_VCR
CVBS_STB
CVBS/Y_TV
Y_ENC
MUTE
YCVBSIN_ENC 36
YCVBSIN_VCR 50
CVBSIN_STB
9 VOUT_RF
6dB
34
6dB
13 COUT_AUX
6dB
15 YCVBSOUT_AUX
C SWITCH
R/C_ENC
C_ENC
C_TV
C_AUX
MUTE
5 COUT_VCR
6dB
Y/CVBS SWITCH
CVBS_STB
CVBS/Y_ENC
CVBS/Y_AUX
CVBS/Y_TV
6dB
Y_AUX
Y_ENC
MUTE
YCVBSIN_TV 52
YIN_AUX 26
YIN_ENC 38
7 YCVBSOUT_VCR
25 SLB_TV
SLOW BLANK,
I/O MONITOR
CINCHSWITCH
L_ENC
L_STB
L_TV
L_VCR
L_AUX
R_ENC
R_STB
R_TV
R_VCR
R_AUX
MUTE
LIN_ENC 45
LIN_STB 41
LIN_TV 53
LIN_VCR 49
-14dB
-14dB
0/6dB
27 SLB_VCR
31 SLB_AUX
59 LOUT_CINCH
0/6dB
58 ROUT_CINCH
AUX SWITCH
L_ENC
L_STB
L_TV
L_VCR
R_VCR
R_TV
R_STB
R_ENC
MUTE
LIN_AUX 35
RIN_ENC 43
RIN_STB 39
6 LOUT_AUX
4 ROUT_AUX
VCR SWITCH
L_ENC
L_STB
L_TV
L_AUX
R_ENC
R_STB
R_AUX
R_TV
MUTE
RIN_VCR 47
SCL 21
SDA 22
4
I2C BUS
DECODER
RIN_AUX 37
62 LOUT_VCR
60 ROUT_VCR
8 AOUT_RF
TV SWITCH
L_ENC
L_STB
L_VCR
L_AUX
R_AUX
R_VCR
R_STB
R_ENC
MUTE
-14dB
0/6dB
-14dB
0/6dB
STEREO/
MONO
2 LOUT_TV
64 ROUT_TV
6410-02.EPS
RIN_TV 56
Circuit-, IC Descriptions and List of Abbreviations
9.7.5
IC7600: MSP3415D
DVDR980-985 /0X1
9.
EN 193
EN 194
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 195
EN 196
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 197
EN 198
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 199
EN 200
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 201
EN 202
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
9.7.6
IC7703: TDA9818
DVDR980-985 /0X1
9.
EN 203
EN 204
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 205
EN 206
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 207
EN 208
9.7.7
9.
DVDR980-985 /0X1
IC7803: TMP93C071
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 209
EN 210
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 211
EN 212
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 213
EN 214
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 215
EN 216
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
9.7.8
DVDR980-985 /0X1
9.
EN 217
IC7990: STV5348
STV5348
.
.
.
.
.
..
.
.
..
.
COMPLETE TELETEXT AND VPS DECODER
INCLUDING AN 8 PAGE MEMORY ON A SINGLE CHIP
UPWARD SOFTWARE COMPATIBLE WITH
PREVIOUS SGS-THOMSON's MULTICHIP
SOLUTIONS (SAA5231, SDA5243, STV5345)
PERFORM PDC SYSTEM A (VPS) AND PDC
SYSTEM B (8/30/2) DATA STORAGE SEPARATLY
DEDICATED "ERROR FREE" OUTPUT FOR
VALID PDC DATA
INDICATION OF LINE 23 FOR EXTERNAL
USE
SINGLE +5V SUPPLY VOLTAGE
SINGLE 13.875MHz CRYSTAL
REDUCED SET OF EXTERNAL COMPONENTS, NO EXTERNAL ADJUSTMENT
OPTIMIZED NUMBER OF DIGITAL SIGNALS
REDUCING EMC RADIATION
HIGH DENSITY CMOS TECHNOLOGY
DIGITAL DATA SLICER AND DISPLAY
CLOCK PHASE LOCK LOOP
28 PIN DIP & SO PACKAGE
DESCRIPTION
The STV5348 decoder is a computer-controlled
teletext device including an 8 page internal memory. Data slicing and capturing extracts the teletext
information embedded in the composite video signal. Control is accomplished via a two wire serial
I2C bus . Chip address is 22h. Internal ROM provides a character set suitable to display text using
up to seven national languages. Hardware and
software features allow selectable master/slave
synchronization configurations. The STV5348 also
supports facilities for reception and display of current level protocol data.
DIP28
(Plastic Package)
ORDER CODE :
STV5348 West European
STV5348/H East European
STV5348/T Turkish & European
SO28
(Plastic Package)
ORDER CODE :
STV5348D West European
STV5348D/H East European
STV5348D/T Turkish & European
PIN CONNECTIONS
CVBS
1
28
CBLK
MA/SL
2
27
TEST
VDDA
3
26
VSSA
POL
4
25
VSSO
STTV/LFB
5
24
XTI
FFB
6
23
XTO
VSSD
7
22
VDDD
R
8
21
VCR/TV
G
9
20
RESERVED
B
10
19
DV
RGB REF
11
18
L23
BLAN
12
17
SDA
COR
13
16
SCL
ODD/EVEN
14
15
Y
EN 218
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
CVBS
MA/SL
VDDA
POL
STTV/LFB
FFB
VSSD
R
G
B
RGBREF
BLAN
COR
ODD/EVEN
Y
SCL
SDA
L23
DV
RESERVED
VCR/TV
VDDD
XTO
XTI
VSSO
VSSA
TEST
CBLK
BLOCK DIAGRAM
Function
Input
Input
Analog Supply
Input
Output / Input
Input
Ground
Output
Output
Output
Supply
Output
Output
Output
Output
Input
Input/ Output
Output
Output
Test
Input
Digital Supply
Crystal Output
Crystal Input
Ground
Ground
Test
Input / Output
Description
Composite Video Signal Input through Coupling Capacitor
Master/Slave Selection Mode
+5V
STTV / LFB / FFB Polarity Selection
Composite Sync Output, Line Flyback Input
Field Flyback Input
Digital Ground
Video Red Signal
Video Green Signal
Video Blue Signal
DC Voltage to define RGB High Level
Fast Blanking Output TTL Level
Open Drain Contrast Reduction Output
25Hz Output Field synchronized for non-interlaced display
Open Drain Foreground Information Output
Serial Clock Input
Serial Data Input/Output
Line 23 Identification
VPS Data Valid
To be connected to VSSD through a resistor
PLL Time Constant Selection
+5V
Oscillator Output 13.875MHz
Oscillator Input 13.875MHz
Oscillator Ground
Analog Ground
Grounded to VSSA
To connect Black Level Storage Capacitor
Figure
9
11
12
15
12
13
13
13
13
15
15
15
15
16
17
15
15
15
15
14
14
11
28
5348-01.TBL
PIN DESCRIPTION
Circuit-, IC Descriptions and List of Abbreviations
9.7.9
DVDR980-985 /0X1
9.
EN 219
Tuner1705: UV1316K
VHF/UHF television tuner
UV1336K MK3
FEATURES
Member of UV1300 MK3 family of small-sized
UHF/VHF tuners
Integrated with passive splitter
Covers systems M, N
2
Digitally-controlled (PLL) tuning via I C-bus
2
Fast 400kHz I C bus protocol compatible with
3.3V and 5V micro controllers
181 channels coverage ( Off-air and full cable )
World standardized mechanical dimensions and
pinning. Horizontal mounting is optionally
available.
DESCRIPTION
MARKING
The UV1336K MK3 splitter - tuner belongs to the
UV1300 family of WSP tuners, which are designed to
meet a wide range of TV applications. It is a full band
tuner suitable for NTSC M, N and PAL M, N. The low
IF output impedance is designed for direct drive of a
wide variety of SAW filters with sufficient suppression
of triple transient.
The following items of information are
printed on a sticker that is on the top
cover of the tuner:
Type number
Code number
The UV1336K MK3 incorporates internal wideband2
AGC with selectable TOP adjustment via I C.
Origin letter of factory
Change code
This tuner complies with the requirements of
radiation, conforming with:
FCC Part 15, Subpart B
Year and week code
BETS 7
CISPR13
ORDERING INFORMATION
TYPE
UV1336K/A F G S-3
DESCRIPTION
F connector, wideband AGC, switchable FM trap
ORDER NUMBERS
3139 147 17011
EN 220
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
VHF/UHF television tuner
UV1336K MK3
BLOCK DIAGRAM
RF i/p
Gain
controllable
Pre-amplifiers
Tracking
filters
Prefiltering
Tracking
filters
Mix-Osc
IF amp
RF o/p
11
TV IF o/p
AGC
Detector
PLL
1
2
9
Vt
(monitor)
AGC
7
33V
Vcc
3
PINNING
PIN
DESCRIPTION
AGC
1
Gain Control Voltage
TU
2
Tuning voltage
AS
3
I C-Bus Address Select
SCL
4
I C-Bus Serial Clock
SDA
5
I C-Bus Serial Data
n.c.
6
Not Connected
Vs
7
PLL Supply Voltage +5V
n.c
8
Not Connected
VST
9
Fixed tuning Supply Voltage +33V
n.c
10
Not connected
IF1
11
Asymmetrical IF Output
GND
2
2
2
M1,M2,M3,M4 Mounting Tags (Ground)
5
8
AS SCL SDA ADC**
** ADC option not available in NTSC versions
SYMBOL
4
Circuit-, IC Descriptions and List of Abbreviations
9.8
IC’s Digital Board
9.8.1
IC7100: VSM
VERSATILE STREAM MANAGER
DVDR980-985 /0X1
9.
EN 221
EN 222
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 223
EN 224
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
9.8.2
IC7101; IC7306: IC 7402 SDRAM
DVDR980-985 /0X1
9.
EN 225
EN 226
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
9.
EN 227
IC7200: STi5508
STi5508
DVD HOST PROCESSOR WITH ENHANCED AUDIO
FEATURES
■ Integrated 32-bit host CPU @ 60MHz
• 2 Kbytes of Icache, 2 Kbytes of Dcache, and
4Kbytes of SRAM configurable as Dcache.
■ Audio decoder
• 5.1 channel Dolby Digital® /MPEG-2 multi-channel
decoding, 3 X 2-channel PCM outputs
• IEC60958 -IEC61937 digital output
• SRS® /TruSurround®
• DTS digital out and MP3 decoding
■ Karaoke processor
• Echo, pitch shift, microphone inputs, voice
cancellation and multiple other effects
■ Video decoder
• Supports MPEG-2 MP@ML
• Fully programmable zoom-in and zoom-out
• PAL to NTSC and NTSC to PAL conversion
■ DVD and SVCD subpicture decoder
■ High performance on-screen display
• 2 to 8 bits per pixel OSD options
• Anti-flicker, anti-flutter and anti-aliasing filters
■ PAL/NTSC/SECAM encoder
• RGB, CVBS, Y/C and YUV outputs with 10-bit DACs
• Macrovision® 7.01/6.1 compatible
■ Shared SDRAM memory interface
• Supports 1 or 2x16Mbit, or 1x64Mbit 125MHZ
SDRAM
■ Programmable CPU memory interface for SDRAM,
ROM, peripherals...
■ Front-end interface
• DVD, VCD, SVCD and CD-DA compatible
• Serial, parallel and ATAPI interfaces
• Hardware sector filtering
• Integrated CSS decryption and track buffer
■ Integrated peripherals
• 2 UARTS, 2 SmartCards, I2C controller, 3 PWM
outputs, 3 capture timers
• Modem support
• 38 bits of programmable I/O
■ Professional toolset support
• ANSI C compiler and libraries
■ 208 pin PQFP package
The STi5508 provides a highly integrated back-end
solution for DVD applications. A host CPU handles both
the general application (the user interface, and the DVD,
CD-DA, VCD, SVCD navigation) and the drivers of the
different embedded peripheral (audio/video, karaoke,
sub-picture decoders, OSD, PAL/NTSC encoder...).
Because of its memory savings, increased number of
internal peripherals, improved development platform and
reference design, the STi5508 offers a cost-effective
solution to DVD applications, with rapid time-to-market.
DMA
channels
arbitrator
Front-end interface
(sector processor
& DVD decryption)
ST20 CPU
9.8.3
DVDR980-985 /0X1
2K
instruction
cache
2K data
cache and
4K SRAM
Programmable
CPU memory
interface
MPEG-2 multichannel
Dolby Digital®
MP3
MPEG2 video
Sub-picture
OSD & background
2 UART,
2 SmartCard,
PIO, 3PWM,
MAFE interface
PAL/NTSC
& SECAM
Diagnostics
controller and
system services
Karaoke
EN 228
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
STi5508
1 Architecture overview
1
Architecture overview
1.1
Introduction
The figure below shows the architecture of the STi5508. This device has the same global architecture as the STi5505,
with the addition of new features such as karaoke, a shared SDRAM memory interface and extra display planes.
Because of this increased performance, the STi5508 and STi5505 are not pin compatible. This chapter gives a brief
overview of each of the functional blocks of the STi5508.
DVD
Internal peripherals
Central
command port
CPU
(C2+)
CACHE SUBSYSTEM
Front-end &
link interface
CLOCK
GENERATION
DMAs
MPEG
MPEG
DMA
ICACHE
SRAM
Refill
control
Programmable
CPU interface
(EMI)
CPU arbiter
Analog/digital
video output
SDRAM
BLOCK MOVE
Shared SDRAM
interface (SMI)
DENC
JTAG
debugging
interface
ST20 arbiter & memory controller
I/F
16, 32 or
64 Mbit
SDRAM
DCACHE
Diagnostic
controller
Communications
arbiter
Ext peripherals:
Flash, additional
DRAM SDRAM
TAP
RID
DEBUG
BLOCK MOVE
2 UART &
2 SmartCards
I2C
CD FIFOs
Command I/F
SDRAM arbiter (LMC)
OSD, SP
decoder
and mixing
Video
filtering
Video
decoder
Audio
decoder
Figure 1 Functional block diagram
Karaoke
processor
Audio in/out
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
1 Architecture overview
1.2
9.
EN 229
STi5508
Central processor
The STi5508 Central Processing Unit is a ST20C2+ 32-bit processor core. It contains instruction processing logic,
instruction and data pointers, and an operand register. It directly accesses the high-speed on-chip SRAM, which can
store data or programs and uses the cache to reduce access time to off-chip program and data memory.
The processor can access memory via the Programmable CPU Interface (often referred to as the EMI) or the Shared
Memory Interface (SMI), which is shared with the video, audio, sub-picture and OSD decoders.
1.3
MPEG video decoder
This is a real-time video compression processor supporting the MPEG-1 and MPEG-2 standards at video rates up to
720 x 480 x 60 Hz and 720 x 576 x 50 Hz. Picture format conversion for display is performed by vertical and horizontal
filters. User-defined bitmaps can be super-imposed on the display picture by using the on-screen display function.
The display unit is part of the MPEG video decoder, it overlays the four display planes shown in the figure below. The
display planes are normally overlaid in the order illustrated, with the background color at the back and the sub-picture
at the front (used as a cursor plane). The sub-picture plane can alternatively be positioned between the OSD and
MPEG video planes where it can be used as a second on-screen display plane.
Background color
08:23pm
MPEG video
Replay
Score
Stats
08:23pm
Replay Score
Stats
On-screen display
08:23pm
Replay Score
Stats
Overlaid planes
Sub-picture plane
Figure 2 Display planes
EN 230
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
STi5508
1.4
1 Architecture overview
Audio decoder
The audio decoder accepts: Dolby Digital, MPEG-1 layers I and II, MPEG-2 layer II 6-channel, PCM, CDDA data
formats; MPEG2 PES streams for MPEG-2, MPEG-1, Dolby Digital, MP3, and Linear PCM (LPCM). The audio decoder
supports DTS digital out (DVD DTS and CDDA DTS).
S/PDIF input data (IEC-60958 or IEC-61937 standards) is accepted if an external circuitry extracts the PCM clock from
the stream.
Skip frame, repeat blocks and soft mute frame features can be used to synchronize audio and video data. PTS audio
extraction is also supported.
The device outputs up to 6 channels of PCM data and appropriate clocks for external digital-to-analog converters.
Programmable downmix enables 1,2,3 or 4 channel outputs. Data can be output in either I²S format or Sony format. The
decoder can format output data according to IEC-60958 standard (for non compressed data: L/R channels, 16, 18, 20
and 24-bits) or IEC-61937 standard (for compressed data), for FS = 96kHz, 48kHz, 44.1kHz or 32kHz.
Sampling frequencies of 96kHz, 48kHz, 44.1kHz, 32kHz and half sampling frequencies are supported. A
downsampling filter (96kHz/48kHz) is available.
The decoder supports dual mode for MPEG and Dolby Digital. It is karaoke aware and capable in Dolby Digital and
MPEG formats according to DVD specifications. It includes a Dolby surround compatible downmix and a ProLogic
decoder.
A pink noise generator enables the accurate positioning of speakers for optimal surround sound setup.
In global mute mode, the decoder decodes the incoming bitstream normally but the PCM and SPDIF outputs are
softmuted. This mode is used to prepare a period of decoding mode, to synchronize audio and video data without
hearing the audio.
Slow-forward and fast-forward trick modes are available for compressed and non-compressed data.
The control interface of the decoder is activated via memory mapped registers in the ST20 address space.
1.5
Karaoke
The karaoke processor is a post-processing module which supports the following features: 2 micro PCM input, pitch
shift, echo effect, reverberation, chorus, voice cancellation, level-sensitive vocal cancelling, vocal partnering,
independant volume control on music and vocal channels.
1.6
Modem analog front-end interface
The Modem Analog Front-end interface is used to transfer transmit and receive DAC and ADC samples between the
memory and an external modem analog front-end (MAFE), using a synchronous serial protocol. DMA is used to
transfer the sample data between memory buffers and the MAFE interface module, with separate transmit and receive
buffers and double buffering of the buffer pointers. FIFOs are used to take into account the access latency to memory,
in a worst case system and to allow the use of bursts for memory bandwidth efficiency improvement. The V22 bis
standard is supported.
1.7
Memory subsystem
On-chip
The on-chip memory includes 2Kbytes of instruction cache, 2Kbytes of data cache and 4Kbytes of SRAM that can be
optionally configured as data cache. The subsystem provides 240M/bytes of internal bandwidth, supporting pipelined 2cycle internal memory access.
Circuit-, IC Descriptions and List of Abbreviations
1 Architecture overview
DVDR980-985 /0X1
9.
STi5508
The instruction and data caches are direct-mapped, with a write-back system for the data-cache. The caches support
burst accesses to the external memories for refill and write-back. Burst access increases the performance of pagemode DRAM memories.
Off-chip
There are two off-chip memory interfaces:
• The external memory interface (EMI) accessed by the ST20 is used for the transfer of data and programs between
the STi5508 and external peripherals, flash and additional SDRAM and DRAM.
• Shared memory interface (SMI) controls the movement of data between the STi5508 and 16, 32 or 64 Mbits of
SDRAM. This external SDRAM stores the display data generated by the MPEG decoder and CPU and the C2+
code data.
The EMI uses minimal external support logic to support memory subsystems, and accesses a 32 Mbytes of physical
address space (greater if SDRAM or DRAM is used) in four general purpose memory banks of 8 or 16 bits wide, 21 or
22 address lines, and byte select. For applications requiring extra memory, the EMI supports this extra memory with
zero external support logic, even for 16-bit SDRAM devices. The EMI can be configured for a wide variety of timing and
decode functions by the configuration registers. The timing of each of the four memory banks can be set separately,
with different device types being placed in each bank with no need for external hardware.
1.8
Serial communication
Asynchronous serial controllers
The Asynchronous Serial Controller (ASC), also referred to as the UART interface, provides serial communication
between the STi5508 and other microcontrollers, microprocessors or external peripherals. The STi5508 has four ASCs,
two of which are generally used by the SmartCard controllers.
Eight or nine bit data transfer, parity generation, and the number of stop bits are programmable. Parity, framing, and
overrun error detection increase data transfer reliability. Transmission and reception of data can be double-buffered, or
16-deep FIFOs can be used. A mechanism to distinguish the address from the data bytes is included for multiprocessor
communication. Testing is supported by a loop-back option. A 16-bit baud-rate generator provides the ASC with a
separate serial clock signal.
Each ASC supports full-duplex asynchronous communication where both the transmitter and the receiver use the same
data frame format and the same baud-rate. Each ASC can be set to operate in SmartCard mode for use when
interfacing to a SmartCard.
Synchronous serial control
The Synchronous Serial Controller (SSC) provides a high-speed interface to a wide variety of serial memories, remote
control receivers and other microcontrollers. The SSC supports all of the features of the Serial Peripheral Interface bus
(SPI) and the I2C bus. The SSC can be programmed to interface to other serial bus standards. The SSC shares pins
with the parallel input/output (PIO) ports, and support full-duplex and half-duplex synchronous communication when
used in conjunction with the PIO configuration.
1.9
Front-end interface
The STi5508 can be connected to a front-end through the following interfaces:
• I2S interface;
• multi-format serial interface;
• multi-format parallel interface;
EN 231
EN 232
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
STi5508
1 Architecture overview
• ATAPI interface (for DVD-ROMs)
1.10 On-chip PLL
The on-chip PLL accepts 27 MHz input and generates all the internal high-frequency clocks needed for the CPU,
MPEG and audio subsystems.
1.11 Diagnostic controller (DCU)
The ST20 Diagnostic Controller Unit (DCU) is used to boot the CPU and to control and monitor the chip systems via the
standard IEEE 1194.1 Test Access Port. The DCU includes on-chip hardware with ICE (In Circuit Emulation) and LSA
(Logic State Analyzer) features to facilitate verification and debugging of software running on the on-chip CPU in real
time. It is an independent hardware module with a private link from the host to support real-time diagnostics.
1.12 Interrupt subsystem
The interrupt system allows an on-chip module or external interrupt pin to interrupt an active process so that an
interrupt handling process can be run. An interrupt can be signalled by one of the following: a signal on an external
interrupt pin, a signal from an internal peripheral or subsystem, software asserting an interrupt in the pending register.
Interrupts are implemented by an on-chip interrupt controller and an on-chip interrupt-level controller. The interrupt
controller supports eight prioritized interrupts as inputs and manages the pending interrupts. This allows the nesting of
pre-emptive interrupts for real-time system design. Each interrupt can be programmed to be at a lower or higher priority
than the high priority process queue.
1.13 PAL/NTSC/SECAM encoder
The integrated digital encoder converts a multiplexed 4:2:2 or 4:4:4 YCbCr stream into a standard analog baseband
PAL/NTSC or SECAM signal and into RGB, YUV, Yc and CVBS components. The encoder can perform closed-caption,
CGMS encoding, and allows MacrovisionTM 7.01/6.1 copy protection.
1.14 SmartCard interfaces
Two SmartCard interfaces support SmartCards compliant with ISO7816-3. Each interface is has a UART (ASC), a
dedicated programmable clock generator, and eight bits of parallel IO port.
1.15 PWM and counter module
The PWM and counter module provides three PWM encoder outputs, three PWM decoder (capture) inputs and four
programmable timers. Each capture input can be programmed to detect rising edge, falling edge, both edges or neither
edge (disabled). These facilities are clocked by two independent clocks, one for PWM outputs and one for capture
inputs/timers. The PWM counter is 8-bit, with 8-bit registers to set the output-high time. The capture/compare counter
and the compare and capture registers are 32-bit. The module generates a single interrupt signal.
1.16 Parallel I/O module
38 bits of parallel I/O are configured in 5 ports, and each bit is programmable as output or input. The output can be
configured as a totem-pole or open-drain driver. The input compare logic can generate an interrupt on any change of
any input bit. Many parallel IO have alternate functions and can be connected to an internal peripheral signal such as a
UART or SSC.
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
PIO2[5]
PIO2[6]
PIO2[7]
VDD3_3
VSS
PIO3[0]
PIO3[1]
PIO3[2]
PIO3[3]
PIO3[4]
PIO3[5]
PIO3[6]
PIO3[7]
VDD2_5
VSS
B_DATA
B_BCLK
B_FLAG
B_SYNC
B_WCLK
B_V4
NRSS_OUT
VDD_RGB
VSS_RGB
B_OUT
G_OUT
R_OUT
V_REF_RG
I_REF_RG
VDD_YCC
VSS_YCC
Y_OUT
C_OUT
CV_OUT
V_REF_YC
I_REF_YC
VDD2_5
VSS
PIO4[0]
PIO4[1]
PIO4[2]
PIO4[3]
PIO4[4]
PIO4[5]
PIO4[6]
PIO4[7]
VDD3_3
VDD_PCM
VSS_PCM
VSS
DAC_SCLK
DAC_PCMOUT0
DAC_PCMOUT1
DAC_PCMOUT2
DAC_PCMCLK
DAC_LRCLK
SPDIF_OUT
SMI_ADR[4]
SMI_ADR[5]
SMI_ADR[6]
SMI_ADR[7]
SMI_ADR[8]
SMI_ADR[9]
VDD2_5
VSS
SMI_ADR[3]
SMI_ADR[2]
SMI_ADR[1]
SMI_ADR[0]
SMI_ADR[10]
SMI_ADR[11]
SMI_ADR[12]
SMI_ADR[13]
SMI_CS[0]
SMI_CS[1]
SMI_RAS
SMI_CAS
SMI_WE
SMI_DQML
SMI_DQMU
VDD3_3
SMI_CLKIN
VSS
SMI_DATA[0]
SMI_DATA[1]
SMI_DATA[2]
SMI_DATA[3]
SMI_DATA[4]
SMI_DATA[5]
SMI_DATA[6]
SMI_DATA[7]
SMI_DATA[8]
SMI_DATA[9]
VDD2_5
SMI_CLKOUT
VSS
SMI_DATA[10]
SMI_DATA[11]
SMI_DATA[12]
SMI_DATA[13]
SMI_DATA[14]
SMI_DATA[15]
ADC_SCLK
ADC_LRCLK
PIO2[4]
PIO2[3]
PIO2[2]
PIO2[1]
PIO2[0]
TRIGGER_OUT
TRIGGER_IN
PIO1[5]
PIO1[4]
VSS
VDD2_5
PIO1[3]
PIO1[2]
PIO1[1]
PIO1[0]
PIO0[7]
PIO0[6]
PIO0[5]
PIO0[4]
PIO0[3]
PIO0[2]
PIO0[1]
PIO0[0]
VSS
VDD3_3
CPU_ADR[21]
CPU_ADR[20]
CPU_ADR[19]
CPU_ADR[18]
CPU_ADR[17]
CPU_ADR[16]
CPU_ADR[15]
CPU_ADR[14]
CPU_ADR[13]
CPU_ADR[12]
CPU_ADR[11]
VSS
VDD2_5
CPU_ADR[10]
CPU_ADR[9]
CPU_ADR[8]
CPU_ADR[7]
CPU_ADR[6]
CPU_ADR[5]
CPU_ADR[4]
CPU_ADR[3]
CPU_ADR[2]
CPU_ADR[1]
VSS
VDD3_3
CPU_DATA[15]
CPU_DATA[14]
Circuit-, IC Descriptions and List of Abbreviations
2
Pin data
2.1
Pin out
DVDR980-985 /0X1
2 Pin data
STi5508
PQFP 208
(rev F)
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
9.
EN 233
STi5508
CPU_DATA[13]
CPU_DATA[12]
CPU_DATA[11]
CPU_DATA[10]
CPU_DATA[9]
CPU_DATA[8]
VSS
VDD2_5
CPU_DATA[7]
CPU_DATA[6]
CPU_DATA[5]
CPU_DATA[4]
CPU_DATA[3]
CPU_DATA[2]
CPU_DATA[1]
CPU_DATA[0]
CPU_CAS1
CPU_CAS0
CPU_RAS1
VSS
VDD3_3
CPU_CE[0]
CPU_CE[1]
CPU_CE[2]
CPU_CE[3]
CPU_WAIT
CPU_RW
CPU_BE[1]
CPU_BE[0]
IRQ[0]
IRQ[1]
IRQ[2]
RESET
VSS_PLL
VDD_PLL
VSS
PIX_CLK
VDD2_5
CPU_PROCLK
CPU_OE
PWM0
PWM1
PWM2
TCK
TDI
TDO
TMS
TRST
VSS
VDD3_3
ADC_PCMCLK
ADC_DATA
EN 234
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
STi5508
2.2
2 Pin data
Pin list sorted by function
Alternate functions printed in Italic show a suggested use of the PIO; alternate functions not printed in Italic are
multiplexed with a specific hardware.
Alternate function
Pin number
Pin name
Main function
Type
Input
Output
Audio DAC
51
DAC_SCLK
OVER SAMPLING CLK
EXT_AUD_CLK
O
52
DAC_PCMOUT0
PCM_OUT0
53
DAC_PCMOUT1
PCM_OUT1
EXT_AUD_DATA
O
54
DAC_PCMOUT2
PCM_OUT2
55
DAC_PCMCLK
PCM_CLOCK
56
DAC_LRCLK
LEFT/RIGHT CLK
57
SPDIF_OUT
SPDIF_OUT
O
48
VDD_PCM
VDD FREQ SYNTHE=2.5V
PWR
2.5V
49
VSS_PCM
VSS FREQ SYNTHE=GND
PWR
EXT_AUD_REQ
I/O
O
I/O
EXT_AUD_WCLK
O
Audio ADC input
104
ADC_LRCLK
Left/Right Clock
I/O
106
ADC_PCMCLK
PCM CLOCK
I/O
105
ADC_DATA
DATA
I
103
ADC_SCLK
SAMPLING CLK
I/O
124
RESET
CHIP RESET
I
122
VDD_PLL
VDD PLL=2.5V
PWR
2.5V
123
VSS_PLL
GND PLL=GND
PWR
120
PIX _CLK
27 MHz main clock
I
Clock & reset
PIOs and communication
UART0_DATA (SC0_DATA)
I/O
186
PIO0[0]
PIO0[0]
187
PIO0[1]
PIO0[1]
ATAPI_RD
I/O
188
PIO0[2]
PIO0[2]
ATAPI_WR
I/O
189
PIO0[3]
PIO0[3]
SC0_CLOCK
I/O
190
PIO0[4]
PIO0[4]
SC0_RST
I/O
191
PIO0[5]
PIO0[5]
SC0_CMD_VCC
I/O
192
PIO0[6]
PIO0[6]
193
PIO0[7]
PIO0[7]
SC0_DETECT
I/O
194
PIO1[0]
PIO1[0]
SSC0_DATA (MTSROut/MRSTin)
I/O
195
PIO1[1]
PIO1[1]
SSC0_CLOCK
I/O
196
PIO1[2]
PIO1[2]
SC EXTERNAL
CLOCK
197
PIO1[3]
PIO1[3]
200
PIO1[4]
PIO1[4]
SC0_DATA_DIR
PARA_DVALID
UART2_TXD
UART2_RXD
Table 1 Pins sorted by function
I/O
I/O
I/O
I/O
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
2 Pin data
9.
STi5508
Alternate function
Pin number
EN 235
Pin name
Main function
Type
Input
Output
PARA_SYNC
UART1_TXD
201
PIO1[5]
PIO1[5]
202
TRIGGER_IN
TRIGGER_IN for DCU
I/O
I/O
203
TRIGGER_OUT
TRIGGER_OUT for DCU
I/O
204
PIO2[0]
PIO2[0]
UART3_DATA (SC1_DATA)
I/O
205
PIO2[1]
PIO2[1]
UART1_RXD
MAFEIF_DOUT
PARA_REQ
I/O
206
PIO2[2]
PIO2[2]
PARA_STROBE
MAFEIF_HC1
I/O
207
PIO2[3]
PIO2[3]
SC1_CLOCK
I/O
208
PIO2[4]
PIO2[4]
SC1_RST
I/O
1
PIO2[5]
PIO2[5]
SC1_CMD_VCC
I/O
2
PIO2[6]
PIO2[6]
SC1_DATA_DIR
I/O
3
PIO2[7]
PIO2[7]
SC1_DETECT
I/O
6
PIO3[0]
PIO3[0]
MAFEIF_SCLK
PARA_DATA{0]
I/O
7
PIO3[1]
PIO3[1]
MAFEIF_DIN
PARA_DATA[1]
I/O
8
PIO3[2]
PIO3[2]
MAFEIF_FSI
PARA_DATA[2]
I/O
9
PIO3[3]
PIO3[3]
CAPTURE_IN0
PARA_DATA[3]
I/O
10
PIO3[4]
PIO3[4]
CAPTURE_IN1
PARA_DATA[4]
I/O
11
PIO3[5]
PIO3[5]
CAPTURE_IN2
PARA_DATA[5]
I/O
12
PIO3[6]
PIO3[6]
PARA_DATA[6]
COMP_OUT1
I/O
13
PIO3[7]
PIO3[7]
PARA_DATA[7]
COMP_OUT0
I/O
39-46
PIO4[0:7]
PIO4[0:7]
YC[0:7]
I/O
SSC1_DATA/
NRSS_CLOCK1
SSC1_CLOCK
SDAV_CLK/ P1394_Clk2
SDAV_DATA2
SDAV_DIR / P1394_P_CLK2
OSC_IN_CLK2
EMI Interface
161-170
CPU_ADR[1:10]
ADR[1:10]
O
173-183
CPU_ADR[11:21]
ADR[11:21]
O
141-148
CPU_DATA[0:7]
DATA[0:7]
I/O
151-158
CPU_DATA[8:15]
DATA[8:15]
I/O
138
CPU_RAS1
DRAM RAS
131
CPU_WAIT
WAIT STATE
Table 1 Pins sorted by function
NOT_SDRAM_CS1
I/O
I
EN 236
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
STi5508
2 Pin data
Alternate function
Pin number
Pin name
Main function
Type
Input
Output
130
CPU_RW
READ-NOT WRITE
NOT_SDRAM_WE
O
128
CPU_BE[0]
BYTE 0 ENABLE
DQM[0]
O
129
CPU_BE[1]
BYTE 1 ENABLE
DQM[1]
O
139
CPU_CAS0
DRAM CAS0
SDRAM_CAS/
CPU_ADR[22]
O
O
140
CPU_CAS1
DRAM
NOT_SDRAM_CS0
135
CPU_CE[0]
DRAM_RAS0
SDRAM_RAS
134
CPU_CE[1]
CHIP SEL. BANK 1
133
CPU_CE[2]
CHIP SEL. BANK 2
132
CPU_CE[3]
CHIP SEL. BANK 3
118
CPU_RAM_CLK
SDRAM CLOCK
O
117
CPU_OE
OUTPUT ENABLE
I/O
127
IRQ[0]
IRQ[0] (SERVO_IRQ)
I
126
IRQ[1]
IRQ[1] (ATAPI IRQ)
I
125
IRQ[2]
IRQ[2] (MD_IRQ)
I
116
PWM0
Pulse Width Modula 0
115
PWM1
Pulse Width Modula1
BOOT FROM ROM
114
PWM2
Pulse Width Modula 2
VSYNC
113
TCK
TEST CLOCK
I
112
TDI
TEST DATA IN
I
111
TDO
TEST DATA OUT
O
110
TMS
TEST MODE SELECT
I
109
TRST4
TEST RESET
I
16
B_DATA
I2S DATA
SER_DATA
I
17
B_BCLK
I2S BIT CLOCK
SER_BCLK
I
18
B_FLAG
I2S ERROR FLAG DVD
SER_VALID
I
19
B_SYNC
I2S SECTOR/ABS TIME
SER_SYNC
20
B_WCLK
I2S WORD CLOCK
21
B_V4
I2S VERSATILE INPUT PIN NRSS_IN
I
22
NRSS_OUT
NRSS OUT
O
O
O
O
CS_SUB_BANK3
O
Interrupt
Timers
HSYNC
O
I/O
3
O
JTAG
Front-end
I
NRSS CLOCK
I/O
Video DAC
27, 26, 25
R_OUT, G_OUT, B_OUT R_OUT, G_OUT, B_OUT
O
32, 33, 34
Y_OUT, C_OUT,
CV_OUT
Y_OUT, C_OUT, CV_OUT
O
29
I_REF_RGB
I_REF_DAC_RGB
I
28
V_REF_RGB
V_REF_DAC_RGB
I
36
I_REF_YCC
I_REF_DAC_YCC
I
Table 1 Pins sorted by function
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
2 Pin data
9.
STi5508
Alternate function
Pin number
Pin name
Main function
Type
Input
Output
35
V_REF_YCC
V_REF_DAC_YCC
I
23
VDD_RGB
VDDA_RGB=2.5V
PWR
2.5V
24
VSS_RGB
VSSA_RGB=GND
PWR
30
VDD_YCC
VDDA_YCC=2.5V
PWR
2.5V
31
VSS_YCC
VSSA_YCC=GND
PWR
Shared memory interface
69-66
SMI_ADR[0:3]
Address bus SDRAM
O
58-63
SMI_ADR[4:9]
Address bus SDRAM
O
70-73
SMI_ADR [10:13]
Address bus SDRAM
O
84-93, 97-102
SMI_DATA[0:15]
Data bus SDRAM
I/O
74, 75
SMI_CS[0,1]
Chip select bank 0,1
O
76
SMI_RAS
RAS SDRAM
O
77
SMI_CAS
CAS SDRAM
O
78
SMI_WE
SDRAM write enable
O
79, 80
SMI_DQML, U
DQ MASK EN LOW, UP
O
82
SMI_CLKIN
SDRAM CLOCK IN
I
95
SMI_CLKOUT
SDRAM CLOCK OUT
O
4, 47, 81, 107,
136, 159, 184
VDD3_3
3.3 V POWER SUPPLY
PWR
14, 37, 64, 94,
119, 149, 171,
198
VDD2_5
2.5V POWER SUPPLY
PWR
GROUND
PWR
Power supply
5, 15, 38, 50, 65, VSS
83, 96, 108, 121,
137, 150, 160,
172, 185, 199
Table 1 Pins sorted by function
1. FEI_CFG bits 8 and 9 must be programmed according to the required NRSS configuration.
2. Register LNK_SDAV_CONF bit 22 (SDE) must be set to 1 to validate the output path.
3. BOOTFROMROM is active during reset.
4. Tie low whenever JTAG is not used.
EN 237
EN 238
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
STi5508
2.3
2 Pin data
Pins sorted by pin number
Alternate function
Pin N°
Pin name
Main function
Dir func.
Input
Output
Left Side
1
PIO2[5]
PIO2[5]
2
PIO2[6]
PIO2[6]
3
PIO2[7]
PIO2[7]
4
VDD3_3
3.3 V POWER SUPPLY
5
VSS
GROUND
6
PIO3[0]
PIO3[0]
MAFEIF_SCLK
PARA_DATA{0]
I/O
7
PIO3[1]
PIO3[1]
MAFEIF_DIN
PARA_DATA[1]
I/O
8
PIO3[2]
PIO3[2]
MAFEIF_FSI
PARA_DATA[2]
I/O
9
PIO3[3]
PIO3[3]
CAPTURE_IN0
PARA_DATA[3]
I/O
10
PIO3[4]
PIO3[4]
CAPTURE_IN1
PARA_DATA[4]
I/O
11
PIO3[5]
PIO3[5]
CAPTURE_IN2
PARA_DATA[5]
I/O
12
PIO3[6]
PIO3[6]
PARA_DATA[6]
COMP_OUT1
I/O
13
PIO3[7]
PIO3[7]
PARA_DATA[7]
COMP_OUT0
I/O
SC1_CMD_VCC
SC1_DATA_DIR
I/O
I/O
I/O
SC1_DETECT
POWER
POWER
14
VDD2_5
2.5V POWER SUPPLY
POWER
15
VSS
GROUND
POWER
16
B_DATA
I2S DATA
SER_DATA
I
17
B_BCLK
I2S BIT CLOCK
SER_BCLK
I
18
B_FLAG
I2S ERROR FLAG DVD
SER_VALID
I
19
B_SYNC
I2S SECTOR/ABS TIME
SER_SYNC
I
SSC1_DATA/ NRSS_CLOCK1
SSC1_CLOCK
SDAV_CLK/ P1394_CLK2
20
B_WCLK
I2S WORD CLOCK
21
B_V4
I2S VERSATILE INPUT
NRSS CLOCK
22
NRSS_OUT
NRSS OUT
23
VDD_RGB
VDDA_RGB=2.5V
POWER
24
VSS_RGB
VSSA_RGB=GND
POWER
25
B_OUT
B_OUT
O
26
G_OUT
G_OUT
O
27
R_OUT
R_OUT
O
28
V_REF_RGB
V_REF_DAC_RGB
I
NRSS_IN
Table 2 Pins sorted by number
I/O
I
O
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
2 Pin data
STi5508
Alternate function
Pin N°
Pin name
Main function
Dir func.
Input
Output
29
I_REF_RGB
I_REF_DAC_RGB
30
VDD_YCC
VDDA_YCC=2.5V
I
POWER
31
VSS_YCC
VSSA_YCC=GND
POWER
32
Y_OUT
Y_OUT
O
33
C_OUT
C_OUT
O
34
CV_OUT
CV_OUT
O
35
V_REF_YCC
V_REF_DAC_YCC
I
36
I_REF_YCC
I_REF_DAC_YCC
I
37
VDD2_5
2.5V POWER SUPPLY
POWER
38
VSS
GROUND
39
PIO4[0]
PIO4[0]
YC[0]
I/O
40
PIO4[1]
PIO4[1]
YC[1]
I/O
41
PIO4[2]
PIO4[2]
YC[2]
I/O
42
PIO4[3]
PIO4[3]
YC[3]
I/O
43
PIO4[4]
PIO4[4]
YC[4]
I/O
44
PIO4[5]
PIO4[5]
YC[5]
I/O
45
PIO4[6]
PIO4[6]
YC[6]
I/O
46
PIO4[7]
PIO4[7]
YC[7]
I/O
POWER
47
VDD3_3
3.3 V POWER SUPPLY
POWER
48
VDD_PCM
VDD FREQ SYNTH=2.5V
POWER
49
VSS_PCM
VSS FREQ SYNTH=GND
POWER
50
VSS
GROUND
51
DAC_SCLK
SAMPLING CLK
EXT_AUD_CLK
O
52
DAC_PCMOUT0
PCM_OUT0
EXT_AUD_DATA
O
53
DAC_PCMOUT1
PCM_OUT1
54
DAC_PCMOUT2
PCM_OUT2
55
DAC_PCMCLK
PCM_CLOCK
56
DAC_LRCLK
LEFT/RIGHT CLK
57
SPDIF_OUT
SPDIF_OUT
O
58
SMI_ADR[4]
Adress bus SDRAM
O
59
SMI_ADR[5]
Adress bus SDRAM
O
60
SMI_ADR[6]
Adress bus SDRAM
O
61
SMI_ADR[7]
Adress bus SDRAM
O
62
SMI_ADR[8]
Adress bus SDRAM
O
63
SMI_ADR[9]
Adress bus SDRAM
O
POWER
Bottom side
EXT_AUD_REQ
I/O
O
I/O
EXT_AUD_WCLK
O
64
VDD2_5
2.5V POWER SUPPLY
POWER
65
VSS
GROUND
POWER
66
SMI_ADR[3]
Adress bus SDRAM
O
67
SMI_ADR[2]
Adress bus SDRAM
O
Table 2 Pins sorted by number
EN 239
EN 240
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
STi5508
2 Pin data
Alternate function
Pin N°
Pin name
Main function
Dir func.
Input
Output
68
SMI_ADR[1]
Adress bus SDRAM
O
69
SMI_ADR[0]
Adress bus SDRAM
O
70
SMI_ADR[10]
Adress bus SDRAM
O
71
SMI_ADR[11]
Adress bus SDRAM
O
72
SMI_ADR[12]
Adress bus SDRAM
O
73
SMI_ADR[13]
Adress bus SDRAM
O
74
SMI_CS[0]
Chip select bank 0
O
75
SMI_CS[1]
Chip select bank 1
O
76
SMI_RAS
RAS SDRAM
O
77
SMI_CAS
CAS SDRAM
O
78
SMI_WE
SDRAM write enable
O
79
SMI_DQML
DQ MASK EN LOW
O
80
SMI_DQMU
DQ MASK EN UP
O
81
VDD3_3
3.3 V POWER SUPPLY
POWER
82
SMI_CLKIN
SDRAM CLOCK IN
I
83
VSS
GROUND
POWER
84
SMI_DATA[0]
Data bus SDRAM
I/O
85
SMI_DATA[1]
Data bus SDRAM
I/O
86
SMI_DATA[2]
Data bus SDRAM
I/O
87
SMI_DATA[3]
Data bus SDRAM
I/O
88
SMI_DATA[4]
Data bus SDRAM
I/O
89
SMI_DATA[5]
Data bus SDRAM
I/O
90
SMI_DATA[6]
Data bus SDRAM
I/O
91
SMI_DATA[7]
Data bus SDRAM
I/O
92
SMI_DATA[8]
Data bus SDRAM
I/O
93
SMI_DATA[9]
Data bus SDRAM
I/O
POWER
94
VDD2_5
2.5V POWER SUPPLY
95
SMI_CLKOUT
SDRAM CLOCK OUT
O
96
VSS
GROUND
POWER
97
SMI_DATA[10]
Data bus SDRAM
I/O
98
SMI_DATA[11]
Data bus SDRAM
I/O
99
SMI_DATA[12]
Data bus SDRAM
I/O
100
SMI_DATA[13]
Data bus SDRAM
I/O
101
SMI_DATA[14]
Data bus SDRAM
I/O
102
SMI_DATA[15]
Data bus SDRAM
I/O
103
ADC_SCLK
SAMPLING CLK
I/O
104
ADC_LRCLK
Left/Right Clock
I/O
SDAV_DATA2
Sdav_dir / P1394_P_CLK2
Right side
Table 2 Pins sorted by number
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
2 Pin data
STi5508
Alternate function
Pin N°
EN 241
Pin name
Main function
Dir func.
Input
105
ADC_DATA
DATA
106
ADC_PCMCLK
PCM CLOCK
Output
I
I/O
OSC_IN_CLK2
107
VDD3_3
3.3 V POWER SUPPLY
108
VSS
GROUND
POWER
POWER
TEST RESET
I
I
109
TRST
110
TMS
TEST MODE SELECT
111
TDO
TEST DATA OUT
O
112
TDI
TEST DATA IN
I
113
TCK
TEST CLOCK
I
114
PWM2
Pulse Width Modul 2
115
PWM1
Pulse Width Modul 1
BOOT_FROM_ROM
I/O
116
PWM0
Pulse Width Modul 0
HSYNC
O
117
CPU_OE
OUTPUT ENABLE
I/O
118
CPU_RAM_CLK
SDRAM CLOCK
O
119
VDD2_5
2.5V POWER SUPPLY
POWER
3
VSYNC
O
4
120
PIX _CLK
27 MHz main clock
I
121
VSS
GROUND
POWER
122
VDD_PLL
VDD PLL=2.5V
POWER
123
VSS_PLL
GND PLL=GND
POWER
124
RESET
CHIP RESET
I
125
IRQ[2]
IRQ[2] (MD_IRQ)
I
126
IRQ[1]
IRQ[1] (ATAPI IRQ)
I
127
IRQ[0]
IRQ[0] (SERVO_IRQ)
128
CPU_BE[0]
BYTE 0 ENABLE
DQM[0]
129
CPU_BE[1]
BYTE 1 ENABLE
DQM[1]
O
130
CPU_RW
READ-NOT WRITE
NOT_SDRAM_WE
O
131
CPU_WAIT
WAIT STATE
I
O
I
132
CPU_CE[3]
CHIP SEL. BANK 3
133
CPU_CE[2]
CHIP SEL. BANK 2
134
CPU_CE[1]
CHIP SEL. BANK 1
135
CPU_CE[0]
DRAM_RAS0
136
VDD3_3
3.3 V POWER SUPPLY
137
VSS
GROUND
138
CPU_RAS1
DRAM RAS
NOT_SDRAM_CS1
I/O
139
CPU_CAS0
DRAM CAS0
SDRAM_CAS/
CPU_ADR[22]
O
140
CPU_CAS1
DRAM
NOT_SDRAM_CS0
O
141
CPU_DATA[0]
DATA[0]
I/O
142
CPU_DATA[1]
DATA[1]
I/O
Table 2 Pins sorted by number
CS_SUB_BANK3
O
O
O
SDRAM_RAS
O
POWER
POWER
EN 242
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
STi5508
2 Pin data
Alternate function
Pin N°
Pin name
Main function
Dir func.
Input
Output
143
CPU_DATA[2]
DATA[2]
I/O
144
CPU_DATA[3]
DATA[3]
I/O
145
CPU_DATA[4]
DATA[4]
I/O
146
CPU_DATA[5]
DATA[5]
I/O
147
CPU_DATA[6]
DATA[6]
I/O
148
CPU_DATA[7]
DATA[7]
I/O
149
VDD2_5
2.5V POWER SUPPLY
POWER
150
VSS
GROUND
POWER
151
CPU_DATA[8]
DATA[8]
I/O
152
CPU_DATA[9]
DATA[9]
I/O
153
CPU_DATA[10]
DATA[10]
I/O
154
CPU_DATA[11]
DATA[11]
I/O
155
CPU_DATA[12]
DATA[12]
I/O
156
CPU_DATA[13]
DATA[13]
I/O
157
CPU_DATA[14]
DATA[14]
I/O
158
CPU_DATA[15]
DATA[15]
I/O
159
VDD3_3
3.3 V POWER SUPPLY
POWER
160
VSS
GROUND
POWER
161
CPU_ADR[1]
ADR[1]
O
162
CPU_ADR[2]
ADR[2]
O
163
CPU_ADR[3]
ADR[3]
O
164
CPU_ADR[4]
ADR[4]
O
165
CPU_ADR[5]
ADR[5]
O
166
CPU_ADR[6]
ADR[6]
O
167
CPU_ADR[7]
ADR[7]
O
168
CPU_ADR[8]
ADR[8]
O
169
CPU_ADR[9]
ADR[9]
O
170
CPU_ADR[10]
ADR[10]
O
171
VDD2_5
2.5V POWER SUPPLY
POWER
172
VSS
GROUND
POWER
173
CPU_ADR[11]
ADR[11]
O
174
CPU_ADR[12]
ADR[12]
O
175
CPU_ADR[13]
ADR[13]
O
176
CPU_ADR[14]
ADR[14]
O
177
CPU_ADR[15]
ADR[15]
O
178
CPU_ADR[16]
ADR[16]
O
179
CPU_ADR[17]
ADR[17]
O
180
CPU_ADR[18]
ADR[18]
O
181
CPU_ADR[19]
ADR[19]
Top side
O
Table 2 Pins sorted by number
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
2 Pin data
STi5508
Alternate function
Pin N°
EN 243
Pin name
Main function
Dir func.
Input
Output
182
CPU_ADR[20]
ADR[20]
O
183
CPU_ADR[21]
ADR[21]
O
184
VDD3_3
3.3 V POWER SUPPLY
POWER
185
VSS
GROUND
POWER
186
PIO0[0]
PIO0[0]
187
PIO0[1]
PIO0[1]
ATAPI_RD
I/O
188
PIO0[2]
PIO0[2]
ATAPI_WR
I/O
189
PIO0[3]
PIO0[3]
SC0_CLOCK
I/O
190
PIO0[4]
PIO0[4]
SC0_RST
I/O
191
PIO0[5]
PIO0[5]
SC0_CMD_VCC
I/O
192
PIO0[6]
PIO0[6]
SC0_DATA_DIR
I/O
I/O
UART0_DATA
(SC0_DATA)
I/O
193
PIO0[7]
PIO0[7]
SC0_DETECT
194
PIO1[0]
PIO1[0]
SSC0_DATA
I/O
195
PIO1[1]
PIO1[1]
SSC0_CLOCK
I/O
196
PIO1[2]
PIO1[2]
SC EXTERNAL CLOCK PARA_DVALID
197
PIO1[3]
PIO1[3]
198
VDD2_5
2.5V POWER SUPPLY
199
VSS
GROUND
200
PIO1[4]
PIO1[4]
UART2_RXD
201
PIO1[5]
PIO1[5]
PARA_SYNC
202
TRIGGER_IN
TRIGGER_IN for DCU
203
TRIGGER_OUT
TRIGGER_OUT for DCU
204
PIO2[0]
PIO2[0]
UART3_DATA (SC1_DATA)
I/O
205
PIO2[1]
PIO2[1]
UART1_RXD
MAFEIF_DOUT
PARA_REQ
I/O
206
PIO2[2]
PIO2[2]
PARA_STROBE
MAFEIF_HC1
I/O
207
PIO2[3]
PIO2[3]
SC1_CLOCK
I/O
208
PIO2[4]
PIO2[4]
SC1_RST
I/O
UART2_TXD
POWER
POWER
I/O
UART1_TXD
I/O
2. Register LNK_SDAV_CONF bit 22 (SDE) must be set to 1 to validate the output path.
4. BOOTFROMROM is active during reset.
I/O
I/O
Table 2 Pins sorted by number
1. FEI_CFG bits 8 and 9 must be programmed according to the required NRSS configuration.
3. Tie low whenever JTAG is not used
I/O
I/O
EN 244
9.8.4
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
IC7201: NVRAM
M24C64
M24C32
64/32 Kbit Serial I²C Bus EEPROM
■
Compatible with I2C Extended Addressing
■
Two Wire I2C Serial Interface
Supports 400 kHz Protocol
■
Single Supply Voltage:
– 4.5V to 5.5V for M24Cxx
14
8
– 2.5V to 5.5V for M24Cxx-W
– 1.8V to 3.6V for M24Cxx-R
■
Hardware Write Control
■
BYTE and PAGE WRITE (up to 32 Bytes)
■
RANDOM and SEQUENTIAL READ Modes
■
Self-Timed Programming Cycle
■
Automatic Address Incrementing
■
Enhanced ESD/Latch-Up Behavior
■
1 Million Erase/Write Cycles (minimum)
■
40 Year Data Retention (minimum)
DESCRIPTION
These I 2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 8192x8 bits (M24C64) and 4096x8 bits
(M24C32), and operate down to 2.5 V (for the -W
version of each device), and down to 1.8 V (for the
-R version of each device).
The M24C64 and M24C32 are available in Plastic
Dual-in-Line, Plastic Small Outline and Thin Shrink
Small Outline packages.
1
1
PSDIP8 (BN)
0.25 mm frame
TSSOP14 (DL)
169 mil width
8
8
1
1
SO8 (MN)
150 mil width
SO8 (MW)
200 mil width
Figure 1. Logic Diagram
VCC
3
Table 1. Signal Names
E0, E1, E2
Chip Enable Inputs
SDA
Serial Data/Address Input/
Output
SCL
Serial Clock
WC
Write Control
VCC
Supply Voltage
VSS
Ground
E0-E2
SCL
SDA
M24C64
M24C32
WC
VSS
AI01844B
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 245
M24C64, M24C32
Figure 2C. TSSOP Connections
Figure 2A. DIP Connections
M24C64
M24C32
M24C64
M24C32
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
E0
E1
NC
NC
NC
E2
VSS
VCC
WC
SCL
SDA
AI01845B
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
WC
NC
NC
NC
SCL
SDA
AI02129
Note: 1. NC = Not Connected
Figure 2B. SO Connections
These memory devices are compatible with the
I2C extended memory standard. This is a two wire
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4bit unique Device Type Identifier code (1010) in
accordance with the I2C bus definition.
The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time,
following the bus master's 8-bit transmission.
M24C64
M24C32
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
VCC
WC
SCL
SDA
AI01846B
Table 2. Absolute Maximum Ratings 1
Symbol
Value
Unit
Ambient Operating Temperature
-40 to 125
˚C
TSTG
Storage Temperature
-65 to 150
˚C
TLEAD
Lead Temperature during Soldering
260
215
t.b.c.
˚C
TA
Parameter
PSDIP8: 10 sec
SO8: 40 sec
TSSOP14: t.b.c.
VIO
Input or Output range
-0.6 to 6.5
V
VCC
Supply Voltage
-0.3 to 6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model) 2
4000
V
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
EN 246
9.8.5
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
IC7301; IC7302: FLASH
M29W160DT
M29W160DB
16 Mbit (2Mb x8 or 1Mb x16, Boot Block)
3V Supply Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
■ SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
■
ACCESS TIME: 70ns
■
PROGRAMMING TIME
Figure 1. Packages
44
– 10µs per Byte/Word typical
■
35 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 32 Main Blocks
■
PROGRAM/ERASE CONTROLLER
1
TSOP48 (N)
12 x 20mm
SO44 (M)
– Embedded Program and Erase algorithms
■
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■
UNLOCK BYPASS PROGRAM COMMAND
FBGA
LFBGA48 (ZA)
8 x 6 solder balls
– Faster Production/Batch Programming
■
TEMPORARY BLOCK UNPROTECTION
MODE
■
SECURITY MEMORY BLOCK
■
LOW POWER CONSUMPTION
– Standby and Automatic Standby
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
■
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29W160DT: 22C4h
– Bottom Device Code M29W160DB: 2249h
January 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/29
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 247
M29W160DT, M29W160DB
SUMMARY DESCRIPTION
The M29W160D is a 16 Mbit (2Mb x8 or 1Mb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are written to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
The blocks in the memory are asymmetrically arranged, see Tables 2 and 3, Block Addresses. The
first or last 64 Kbytes have been divided into four
additional blocks. The 16 Kbyte Boot Block can be
used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can
be used for parameter storage and the remaining
32K is a small Main Block where the application
may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm),
SO44 and LFBGA48 (0.8mm pitch) packages and
it is supplied with all the bits erased (set to ’1’).
Figure 2. Logic Diagram
Table 1. Signal Names
VCC
20
15
A0-A19
DQ0-DQ14
W
E
DQ15A–1
M29W160DT
M29W160DB
G
BYTE
RB
RP
VSS
AI03843
A0-A19
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
DQ8-DQ14
Data Inputs/Outputs
DQ15A–1
Data Input/Output or Address Input
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
RB
Ready/Busy Output
(Not available on SO44 package)
BYTE
Byte/Word Organization Select
VCC
Supply Voltage
VSS
Ground
NC
Not Connected Internally
DU
Don’t Use as internally connected
Note: RB not available on SO44 package.
5/29
EN 248
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
M29W160DT, M29W160DB
Figure 3. TSOP Connections
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
W
RP
NC
NC
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
Figure 4. SO Connections
48
12 M29W160DT 37
13 M29W160DB 36
24
25
AI03844
6/29
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
RP
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11 M29W160DT 34
12 M29W160DB 33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
24
21
22
23
AI03845
W
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
Circuit-, IC Descriptions and List of Abbreviations
9.8.6
DVDR980-985 /0X1
9.
EN 249
IC7403: SAA6752H (EMPRESS)
MPEG-2 video and MPEG-audio/AC-3 audio
encoder with multiplexer
1
1.1
SAA6752HS
FEATURES
Video input and preprocessing
• Digital YUV input according to “ITU-R BT.656” (8 bits at
27 MHz) and “ITU-R BT.601”
• Support of enhanced “ITU-R BT.656” input format
containing decoded VBI data readable via I2C-bus;
Closed Caption (CC), Wide Screen Signalling (WSS)
and copyright information [Copy Generation
Management System (CGMS)]
• Audio clock generation: 256/384 × fs (48 kHz) locked to
video frame rate (if video is present)
• Sample rate conversion to 48 kHz (locked to video
frame rate) for slave mode operation in all modes except
Digital Versatile Disc (DVD) compliant bypass.
• Processing of non broadcast video signals from analog
VCR according to IEC 756
1.4
• Two video clock input pins for switching two digital video
sources
• Dolby(1) Digital Consumer Encoding (DDCE) also
known as AC-3(2) 2 channel audio encoding at
256 kbit/s or 384 kbit/s (only for SAA6752HS/01)
• “ITU-R BT.601” format conversion to 1/2D1, 2/3D1 and
Standard Interchange Format (SIF)
• MPEG-1 layer 2 audio encoding at 256 kbit/s or
384 kbit/s
• 4 : 2 : 2 to 4 : 2 : 0 colour format conversion
• Decimation filtering for all format conversions
• Input data bypass for Linear Pulse Code Modulation
(LPCM) and compressed audio data [MPEG-1,
MPEG-2, Dolby Digital (DD) and Digital Theatre
System (DTS)] according to IEC 61937
• Adaptive median filter and motion compensated filter for
input noise reduction.
1.2
Audio compression
Video compression
• Preamble Pc, Preamble Pd and bit stream information
captured for identification of modes during bypass of
compressed audio data for MPEG-1, MPEG-2, DD and
DTS according to IEC 61937
• Real time MPEG-2 encoding compliant to Main Profile at
Main Level (MP@ML) for 625 and 525 interlaced line
systems
• Supported resolutions: D1, 2/3D1, 1/2D1 and SIF
• Audio mute via I2C-bus control for all modes except
DVD-compliant bypass.
• IPB frame, IP frame and I frame only encoding
supported at all modes
1.5
• Supported bit rates: up to 25 Mbit/s I-only encoding;
up to 15 Mbit/s IP-only or IBP encoding.
Stream multiplexer
• Multiplexing of video and audio streams according to the
MPEG-2 systems standard (“ISO 13818-1” )
• Variable video bit rate mode for constant picture quality
and constant bit rate mode to gain optimum picture
quality from a fixed channel transfer rate
• Generation and output of MPEG-2 Transport Streams
(TS), MPEG-2 Program Streams (PS), Packetized
Elementary Streams (PES) and Elementary Streams
(ES) compliant to the DVD, D-VHS and DVB standards
• Access to bit rate control parameters whilst encoding to
support external real-time control algorithms (e.g.
constrained variable bit rate control)
• Programmable Group Of Pictures (GOP) structure
• MPEG time stamp (PTS/DTS/SCR/PCR) generation
and insertion (synchronization)
• Innovative motion estimation with wide search range
• Insertion of metadata
• Adaptive quantization
• Optional generation of empty time slots for subsequent
insertion of application specific data packets
• Motion compensated noise filter.
1.3
• Optional insertion of user data in the GOP header and in
the picture header.
Audio input
• Audio inputs: I2S format or EIAJ format (16, 18 or
20 bits), master or slave mode at 32, 44.1 and 48 kHz
(1) Dolby is a registered trademark of Dolby Laboratories
Licensing Corporation.
(2) AC-3 is a registered trademark of Dolby Laboratories
Licensing Corporation.
• Two digital I2S input ports for selection between two
digital audio sources
2001 Aug 01
3
EN 250
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
MPEG-2 video and MPEG-audio/AC-3 audio
encoder with multiplexer
1.6
Output interface
The SAA6752HS/02 is intended for customers whose
application does not require the DDCE function.
• Parallel interface 8-bit master/slave output
The SAA6752HS gives significant advantages to
customers developing digital recording applications:
• 3-state output port
• Glueless interfacing with IEEE 1394 chip sets (for
example, PDI 1394 L11)
• Fast time-to-market and low development
resources: By adding a simple external video input
processor IC, audio analog-to-digital converter, and an
external SDRAM, analog video and audio sources are
compressed into high quality MPEG-2 video and
MPEG-1 layer 2 or AC-3 audio streams, multiplexed into
a single program or transport stream for simple
connection to various storage media or broadcast
media. Hence, making design effort for our customers a
minimum, as well as removing the need for in-depth
experience in MPEG encoding.
• Data Expansion Bus Interface (DEBI) interface.
1.7
Control domain
• All control done via I2C-bus
• I2C-bus slave transceiver up to 400 kHz
• I2C-bus slave address select pin
• Host interrupt flag pin.
1.8
Other features
• Low system host resources: All video and audio
encoding algorithms and software are run on an internal
MIPS(1) processor. The SAA6752HS only requires
small amount of communication from system host
processor to set up and control required encoding
parameters via I2C-bus.
• Single external clock or single crystal 27 MHz
• Separate 27 MHz system clock output
• Interface voltage 3.3 V
• TTL compatible digital outputs
• Power supply voltage 3.3 and 2.5 V
2.2
• Boundary Scan Test (BST) supported
2.2.1
• Power-down mode
• Single SDRAM system memory (16 Mbit@16 bit or
64 Mbit@16 bit).
2
2.1
Application ?elds
DVD BASED OPTICAL DISC RECORDERS (DVD+RW,
DVD-RW, DVD-RAM)
Emerging optical disc based recording systems target to
replace the existing consumer recording (VCR) and
playback (DVD and VCD) products. The first generation
recordable DVD based products will want to maximise
recording times for the 4.7 Gbyte storage capacity. For
these systems the SAA6752HS is critical, with its superior
noise filtering and motion estimation, in enabling high
quality at low bit rates.
GENERAL DESCRIPTION
General
Philips Semiconductors' second generation real time
MPEG-2 encoder, the SAA6752HS, is a highly integrated
single chip audio and video encoding solution with very
flexible multiplexing functionality. With our expertise in two
critical areas for consumer video encoding, noise filtering
and motion estimation, we have pushed the boundaries for
video quality even further, providing enhanced quality for
low bit rates and enabling increased recording times for a
given storage capacity. The SAA6752HS will also enable
a key driver for new consumer digital recording
applications; system cost reduction. By integrating all
audio encoding and multiplexing functionality we will be
moving from a three chip to a one chip system, with cost
efficient design and process technology, thus providing a
truly low cost, high quality encoding system.
2001 Aug 01
SAA6752HS
Playback compatibility with existing DVD decoding
solutions will also be important, which is why the
SAA6752HS provides Dolby digital consumer (AC-3)
audio encoding to allow playback through existing players
implementing DDCE (AC-3) decoding dominant in current
DVD platforms.
The DVD stream is based on MPEG Program Stream
(PS). The SAA6752HS directly outputs MPEG PS
compliant to the DVD standard.
(1) MIPS is a registered trademark of MIPS Technologies.
4
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
MPEG-2 video and MPEG-audio/AC-3 audio
encoder with multiplexer
2.2.2
HDD BASED TIME SHIFT RECORDING
SAA6752HS
A DVHS player records streams based on MPEG
Transport Streams (TS) packed in logical tape tracks. The
SAA6752HS output streams are compliant with DVHS
standard requirements.
2.2.4
VIDEO EDITING/TRANSMISSION/SURVEILLANCE/
CONFERENCING
The SAA6752HS can operate as a stand-alone device in
all above applications. The SAA6752HS' full features and
flexibility allows customers to tailor functionality and
performance to specific application requirements. All
required control settings such as GOP size and bit rate
modes can be selected via I2C-bus.
Since HDD recorders are closed systems, the recording
format stream can be proprietary. SAA6752HS flexible
multiplexing formats, support a number of recording
stream formats for HDD including MPEG Transport
Stream (TS) or MPEG Packetized Elementary Stream
(PES).
3
EN 251
DIGITAL VCR (DVHS) RECORDING
2.2.3
Hard Disc Drive (HDD) based time-shift systems enable
Personalized TV (PTV) functionality, providing consumers
with new powers of control over what and when to watch
broadcast content. With the audio and video content
recorded digitally, identification, search and retrieval
becomes a `no brainer' task as compared to traditional
VCR functionality. Combine this with electronic program
guides and intelligent control, and the PTV can also
analyse the viewers watching habits to search for
programs likely to be of interest and automatically
recorded in anticipation of the viewers preferences.
9.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDDP
digital supply voltage (pad cells)
3.0
3.3
3.6
V
VDDCO
digital supply voltage (core)
2.3
2.5
2.7
V
VDDA
analog supply voltage (oscillator and PLL)
2.3
2.5
2.7
V
IDD(tot)
analog + digital supply current
407
453
525
mA
Ptot
total power dissipation
1.2
1.4
1.9
W
fDCXO
quartz frequency (digital controlled tuning)
27 × (1 − 200 × 10−6)
27
27 × (1 + 200 × 10−6)
MHz
fSDRAM
SDRAM clock frequency
−
108
−
MHz
fSCL
I2C-bus input clock frequency
100
−
400
kHz
B
output bit-rate
1.5
−
25
Mbit/s
VIH
HIGH-level digital input voltage
1.7
−
3.6
V
VIL
LOW-level digital input voltage
−0.5
−
+0.7
V
VOH
HIGH-level digital output voltage
VDDP − 0.4
−
VDDP
V
VOL
LOW-level digital output voltage
0
−
0.4
V
Tamb
ambient temperature
0
−
70
°C
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA6752HS/01(1)
SAA6752HS/02(2)
DESCRIPTION
SQFP208 plastic shrink quad ?at package; 208 leads (lead length 1.3 mm);
body 28 × 28 × 3.4 mm; high stand-off height
Notes
1. MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer.
2. MPEG-2 video and MPEG-audio encoder with multiplexer, but without AC-3 audio encoder.
2001 Aug 01
5
VERSION
SOT316-1
2001 Aug 01
digital
6
GPIO
host interrupt
I2C
I2C-bus
AUDIO
INTER
FACE
ROM
RAM
Fig.1 Block diagram.
MIPS
CPU
PI-bus
VIDEO
COMPRESSION
ROM
boundary scan
TAP
DEBUG
ONLY
STATIC
MEM
STREAM
MULTIPLEXER
OUTPUT
INTER
FACE
output
MPEG
external
clock
27 MHz
MPEG-2 video and MPEG-audio/AC-3 audio
encoder with multiplexer
reset
RESET
CONTROL
AUDIO
COMPRESSION
RAM
CLOCK
audio clock
DVDR980-985 /0X1
digital
audio
input
video
input
VIDEO
FRONT-END
SDRAM-INTERFACE
STREAM DOMAIN SCHEDULER
SYSTEM
CLOCK
REFERENCE
System Clock
Output
9.
system
clock
reference
SAA6752HS
SDRAM
5
16 bit 16 Mbit or 16 bit 64 Mbit
EN 252
Circuit-, IC Descriptions and List of Abbreviations
SAA6752HS
BLOCK DIAGRAM
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
MPEG-2 video and MPEG-audio/AC-3 audio
encoder with multiplexer
6
9.
EN 253
SAA6752HS
PINNING
SYMBOL
PIN
INPUT/OUTPUT(1)
Imax
(mA)
DESCRIPTION
VSSP
1
ground
−
pad ground
SDATA1
2
input
−
I2S-bus serial data input port 1 with internal pull-down resistor
SCLK1
3
input/output
4
I2S-bus serial clock port 1 with internal pull-down resistor
SWS1
4
input/output
4
I2S-bus word select port 1 with internal pull-down resistor
VDDP
5
supply
−
pad ring supply voltage (3.3 V)
SDATA2
6
input/output
4
I2S-bus serial data port 2 with internal pull-down resistor
SCLK2
7
input/output
4
I2S-bus serial clock port 2 with internal pull-down resistor
SWS2
8
input/output
4
I2S-bus word select port 2 with internal pull-down resistor
ACLK
9
output
4
audio clock output (256 × fs or 384 × fs)
VSSP
10
ground
−
pad ground
IDQ
11
input
−
reserved (recommended connect to pin VSSP) with internal
pull-down resistor
YUV0
12
input
−
video input signal bit 0 (LSB)
YUV1
13
input
−
video input signal bit 1
YUV2
14
input
−
video input signal bit 2
YUV3
15
input
−
video input signal bit 3
YUV4
16
input
−
video input signal bit 4
YUV5
17
input
−
video input signal bit 5
YUV6
18
input
−
video input signal bit 6
YUV7
19
input
−
video input signal bit 7 (MSB)
VSSP
20
ground
−
pad ground
HSYNC
21
input
−
horizontal sync input (video) with internal pull-down resistor
VSYNC
22
input
−
vertical sync input (video) with internal pull-down resistor
FID
23
input
−
video ?eld identi?cation input (odd/even ?eld) with internal
pull-down resistor
VCLK1
24
input
−
video clock input 1 (27 MHz) with internal pull-down resistor
VSSCO
25
ground
−
core ground
VSSCO
26
ground
−
core ground
VDDCO
27
supply
−
core supply voltage (2.5 V)
VDDCO
28
supply
−
core supply voltage (2.5 V)
VDDP
29
supply
−
pad ring supply voltage (3.3 V)
VCLK2
30
input
−
video clock input 2 (27 MHz) with internal pull-down resistor
PDOAV
31
3-state output
4
parallel stream data output for audio/video identi?er
PDIDS
32
input
−
parallel stream data input for data strobe (request for packet in
Data Expansion Bus Interface (DEBI) slave mode) with internal
pull-up resistor
PDOSYNC
33
3-state output
4
parallel stream data output for packet sync
VSSP
34
ground
−
pad ground
PDOVAL
35
3-state output
4
parallel stream data valid output with internal pull-up resistor
PDO0
36
3-state output
4
parallel stream data output bit 0 (LSB)
2001 Aug 01
7
EN 254
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
MPEG-2 video and MPEG-audio/AC-3 audio
encoder with multiplexer
SYMBOL
PIN
INPUT/OUTPUT(1)
Imax
(mA)
SAA6752HS
DESCRIPTION
PDO1
37
3-state output
4
parallel stream data output bit 1
PDO2
38
3-state output
4
parallel stream data output bit 2
VDDP
39
supply
−
pad ring supply voltage (3.3 V)
PDO3
40
3-state output
4
parallel stream data output bit 3
PDO4
41
3-state output
4
parallel stream data output bit 4
PDO5
42
3-state output
4
parallel stream data output bit 5
PDO6
43
3-state output
4
parallel stream data output bit 6
VSSP
44
ground
−
pad ground
PDO7
45
3-state output
4
parallel stream data output bit 7 (MSB)
PDIOCLK
46
input/output
4
parallel stream clock input/output
I2CADDRSEL
47
input
−
I2C-bus address select input with internal pull-up resistor
SD_DQ15
48
input/output
8
SDRAM data input/output bit 15 (MSB)
VDDP
49
supply
−
pad ring supply voltage (3.3 V)
SD_DQ0
50
input/output
8
SDRAM data input/output bit 0 (LSB)
SD_DQ14
51
input/output
8
SDRAM data input/output bit 14
SD_DQ1
52
input/output
8
SDRAM data input/output bit 1
VSSP
53
ground
−
pad ground
SD_DQ13
54
input/output
8
SDRAM data input/output bit 13
SD_DQ2
55
input/output
8
SDRAM data input/output bit 2
SD_DQ12
56
input/output
8
SDRAM data input/output bit 12
VDDP
57
supply
−
pad ring supply voltage (3.3 V)
SD_DQ3
58
input/output
8
SDRAM data input/output bit 3
SD_DQ11
59
input/output
8
SDRAM data input/output bit 11
SD_DQ4
60
input/output
8
SDRAM data input/output bit 4
SD_DQ10
61
input/output
8
SDRAM data input/output bit 10
VSSP
62
ground
−
pad ground
SD_DQ5
63
input/output
8
SDRAM data input/output bit 5
SD_DQ9
64
input/output
8
SDRAM data input/output bit 9
SD_DQ6
65
input/output
8
SDRAM data input/output bit 6
SD_DQ8
66
input/output
8
SDRAM data input/output bit 8
VDDP
67
supply
−
pad ring supply voltage (3.3 V)
SD_DQ7
68
input/output
8
SDRAM data input/output bit 7
SD_DQM1
69
output
8
SDRAM data mask enable output bit 1
SD_DQM0
70
output
8
SDRAM data mask enable output bit 0 (LSB)
SD_WE
71
output
8
SDRAM write enable output (active LOW)
VSSP
72
ground
−
pad ground
SD_CAS
73
output
8
SDRAM column address strobe output (active LOW)
SD_CLK
74
output
8
SDRAM clock output
SD_RAS
75
output
8
SDRAM row address strobe output (active LOW)
SD_CKE
76
output
8
SDRAM clock enable output
2001 Aug 01
8
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
MPEG-2 video and MPEG-audio/AC-3 audio
encoder with multiplexer
SYMBOL
PIN
INPUT/OUTPUT(1)
Imax
(mA)
9.
EN 255
SAA6752HS
DESCRIPTION
VSSCO
77
ground
−
core ground
VSSCO
78
ground
−
core and substrate ground
VDDCO
79
supply
−
core supply voltage (2.5 V)
VDDCO
80
supply
−
core supply voltage (2.5 V)
VDDP
81
supply
−
pad ring supply voltage (3.3 V)
SD_CS
82
output
8
SDRAM chip select output (active LOW)
SD_A13
83
output
8
SDRAM address output bit 13 (bank selection for 64 Mbit)
SD_A9
84
output
8
SDRAM address output bit 9
SD_A8
85
output
8
SDRAM address output bit 8
VSSP
86
ground
−
pad ground
SD_A11
87
output
8
SDRAM address output bit 11 (bank selection for 16 Mbit)
SD_A7
88
output
8
SDRAM address output bit 7
SD_A12
89
output
8
SDRAM address output bit 12 (bank selection for 64 Mbit)
SD_A6
90
output
8
SDRAM address output bit 6
VDDP
91
supply
−
pad ring supply voltage (3.3 V)
SD_A10
92
output
8
SDRAM address output bit 10
SD_A5
93
output
8
SDRAM address output bit 5
SD_A0
94
output
8
SDRAM address output bit 0 (LSB)
SD_A4
95
output
8
SDRAM address output bit 4
VSSP
96
ground
−
pad ground
SD_A1
97
output
8
SDRAM address output bit 1
SD_A3
98
output
8
SDRAM address output bit 3
SD_A2
99
output
8
SDRAM address output bit 2
SD_DQM3
100
output
8
reserved (do not connect)
VDDP
101
supply
−
pad ring supply voltage (3.3 V)
SD_DQM2
102
output
8
reserved (do not connect)
SD_DQ31
103
input/output
8
reserved (do not connect)
SD_DQ16
104
input/output
8
reserved (do not connect)
VSSP
105
ground
−
pad ground
SD_DQ30
106
input/output
8
reserved (do not connect)
SD_DQ17
107
input/output
8
reserved (do not connect)
SD_DQ29
108
input/output
8
reserved (do not connect)
VDDP
109
supply
−
pad ring supply voltage (3.3 V)
SD_DQ18
110
input/output
8
reserved (do not connect)
SD_DQ28
111
input/output
8
reserved (do not connect)
SD_DQ19
112
input/output
8
reserved (do not connect)
SD_DQ27
113
input/output
8
reserved (do not connect)
VSSP
114
ground
−
pad ground
SD_DQ20
115
input/output
8
reserved (do not connect)
SD_DQ26
116
input/output
8
reserved (do not connect)
2001 Aug 01
9
EN 256
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
MPEG-2 video and MPEG-audio/AC-3 audio
encoder with multiplexer
SYMBOL
PIN
INPUT/OUTPUT(1)
Imax
(mA)
SAA6752HS
DESCRIPTION
VSSCO
77
ground
−
core ground
VSSCO
78
ground
−
core and substrate ground
VDDCO
79
supply
−
core supply voltage (2.5 V)
VDDCO
80
supply
−
core supply voltage (2.5 V)
VDDP
81
supply
−
pad ring supply voltage (3.3 V)
SD_CS
82
output
8
SDRAM chip select output (active LOW)
SD_A13
83
output
8
SDRAM address output bit 13 (bank selection for 64 Mbit)
SD_A9
84
output
8
SDRAM address output bit 9
SD_A8
85
output
8
SDRAM address output bit 8
VSSP
86
ground
−
pad ground
SD_A11
87
output
8
SDRAM address output bit 11 (bank selection for 16 Mbit)
SD_A7
88
output
8
SDRAM address output bit 7
SD_A12
89
output
8
SDRAM address output bit 12 (bank selection for 64 Mbit)
SD_A6
90
output
8
SDRAM address output bit 6
VDDP
91
supply
−
pad ring supply voltage (3.3 V)
SD_A10
92
output
8
SDRAM address output bit 10
SD_A5
93
output
8
SDRAM address output bit 5
SD_A0
94
output
8
SDRAM address output bit 0 (LSB)
SD_A4
95
output
8
SDRAM address output bit 4
VSSP
96
ground
−
pad ground
SD_A1
97
output
8
SDRAM address output bit 1
SD_A3
98
output
8
SDRAM address output bit 3
SD_A2
99
output
8
SDRAM address output bit 2
SD_DQM3
100
output
8
reserved (do not connect)
VDDP
101
supply
−
pad ring supply voltage (3.3 V)
SD_DQM2
102
output
8
reserved (do not connect)
SD_DQ31
103
input/output
8
reserved (do not connect)
SD_DQ16
104
input/output
8
reserved (do not connect)
VSSP
105
ground
−
pad ground
SD_DQ30
106
input/output
8
reserved (do not connect)
SD_DQ17
107
input/output
8
reserved (do not connect)
SD_DQ29
108
input/output
8
reserved (do not connect)
VDDP
109
supply
−
pad ring supply voltage (3.3 V)
SD_DQ18
110
input/output
8
reserved (do not connect)
SD_DQ28
111
input/output
8
reserved (do not connect)
SD_DQ19
112
input/output
8
reserved (do not connect)
SD_DQ27
113
input/output
8
reserved (do not connect)
VSSP
114
ground
−
pad ground
SD_DQ20
115
input/output
8
reserved (do not connect)
SD_DQ26
116
input/output
8
reserved (do not connect)
2001 Aug 01
9
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
MPEG-2 video and MPEG-audio/AC-3 audio
encoder with multiplexer
SYMBOL
PIN
INPUT/OUTPUT(1)
Imax
(mA)
9.
EN 257
SAA6752HS
DESCRIPTION
SD_DQ21
117
input/output
8
reserved (do not connect)
SD_DQ25
118
input/output
8
reserved (do not connect)
VDDP
119
supply
−
pad ring supply voltage (3.3 V)
SD_DQ22
120
input/output
8
reserved (do not connect)
SD_DQ24
121
input/output
8
reserved (do not connect)
SD_DQ23
122
input/output
8
reserved (do not connect)
EXTCLK
123
input
−
27 MHz external clock input with internal pull-up resistor
VSSP
124
ground
−
pad ground
VSSA
125
ground
−
oscillator analog ground
XTALI
126
analog input
−
crystal oscillator input (27 MHz); note 2
XTALO
127
analog output
−
crystal oscillator output (27 MHz)
VDDA
128
supply
−
oscillator analog supply voltage (2.5 V)
VSSCO
129
ground
−
core ground
VSSCO
130
ground
−
core ground
VDDCO
131
supply
−
core supply voltage (2.5 V)
VDDCO
132
supply
−
core supply voltage (2.5 V)
VDDP
133
supply
−
pad ring supply voltage (3.3 V)
TDI
134
input
−
boundary scan test data input; pin must ?oat or set to HIGH
during normal operating; with internal pull-up resistor; note 3
TMS
135
input
−
boundary scan test mode select; pin must ?oat or set to HIGH
during normal operating; with internal pull-up resistor; note 3
TCK
136
input
−
boundary scan test clock; pin must be set to LOW during
normal operating; with internal pull-up resistor; note 3
TDO
137
3-state output
4
boundary scan test data output; pin not active during normal
operating; with 3-state output; note 3
VSSP
138
ground
−
pad ground
TRST
139
input
−
test reset input (active LOW), for boundary scan test (with
internal pull-up); notes 3 and 4
CLKOUT
140
output
4
27 MHz system clock output
TEST0
141
input/output
4
reserved (do not connect)
TEST1
142
input/output
4
reserved (do not connect)
VDDP
143
supply
−
pad ring supply voltage (3.3 V)
TEST2
144
input/output
4
reserved (do not connect)
SDA
145
input/open-drain
output
−
serial data input/output (I2C-bus)
SCL
146
input/open-drain
output
−
serial clock input/output (I2C-bus)
RESET
147
input
−
reset input (active LOW); with internal pull-up resistor
VSSP
148
ground
−
pad ground
RTS
149
output
4
reserved (do not connect); Universal Asynchronous
Receiver/Transmitter (UART) request to send output (active
LOW)
2001 Aug 01
10
EN 258
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
MPEG-2 video and MPEG-audio/AC-3 audio
encoder with multiplexer
SYMBOL
PIN
INPUT/OUTPUT(1)
Imax
(mA)
SAA6752HS
DESCRIPTION
CTS
150
input
−
reserved (recommended connect to pin VDDP); UART clear to
send input; external static memory select input (active LOW);
with internal pull-up resistor
RXD
151
input
−
reserved (recommended connect to pin VDDP); UART receive
data; internal boot select input; with internal pull-up resistor
TXD
152
output
4
reserved (do not connect); UART transmit data
VDDP
153
supply
−
pad ring supply voltage (3.3 V)
SM_LB
154
input/output
4
reserved (do not connect)
SM_UB
155
input/output
4
reserved (do not connect)
H_IRF
156
3-state output
4
host interrupt ?ag output; with internal pull-up resistor
VSSP
157
ground
−
pad ground
SM_OE
158
output
4
reserved (do not connect), static memory output enable output
(active LOW)
SM_A9
159
output
4
reserved (do not connect), static memory address output bit 9
SM_A10
160
output
4
reserved (do not connect), static memory address output bit 10
VDDP
161
supply
−
pad ring supply voltage (3.3 V)
SM_A8
162
output
4
reserved (do not connect), static memory address output bit 8
SM_A11
163
output
4
reserved (do not connect), static memory address output bit 11
SM_A7
164
output
4
reserved (do not connect), static memory address output bit 7
SM_A12
165
output
4
reserved (do not connect), static memory address output bit 12
VSSP
166
ground
−
pad ground
SM_A6
167
output
4
reserved (do not connect), static memory address output bit 6
SM_A13
168
output
4
reserved (do not connect), static memory address output bit 13
SM_A5
169
output
4
reserved (do not connect), static memory address output bit 5
SM_A14
170
output
4
reserved (do not connect), static memory address output bit 14
VDDP
171
supply
−
pad ring supply voltage (3.3 V)
SM_WE
172
output
4
reserved (do not connect), static memory write enable output
(active LOW)
SM_D7
173
input/output
4
reserved (do not connect), static memory data input/output
bit 7 with internal pull-down resistor
SM_D8
174
input/output
4
reserved (do not connect), static memory data input/output
bit 8 with internal pull-down resistor
SM_D6
175
input/output
4
reserved (do not connect), static memory data input/output
bit 6 with internal pull-down resistor
VSSP
176
ground
−
pad ground
SM_D9
177
input/output
4
reserved (do not connect), static memory data input/output
bit 9 with internal pull-down resistor
SM_D5
178
input/output
4
reserved (do not connect), static memory data input/output
bit 5 with internal pull-down resistor
SM_D10
179
input/output
4
reserved (do not connect), static memory data input/output
bit 10 with internal pull-down resistor
2001 Aug 01
11
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
MPEG-2 video and MPEG-audio/AC-3 audio
encoder with multiplexer
SYMBOL
PIN
INPUT/OUTPUT(1)
Imax
(mA)
9.
EN 259
SAA6752HS
DESCRIPTION
SM_D4
180
input/output
4
reserved (do not connect), static memory data input/output
bit 4 with internal pull-down resistor
VSSCO
181
ground
−
internal pre-driver and substrate ground
VSSCO
182
ground
−
core ground
VDDCO
183
supply
−
core supply voltage (2.5 V)
VDDCO
184
supply
−
internal pre-driver supply voltage (2.5 V)
VDDP
185
supply
−
pad ring supply voltage (3.3 V)
SM_D11
186
input/output
4
reserved (do not connect), static memory data input/output
bit 11 with internal pull-down resistor
SM_D3
187
input/output
4
reserved (do not connect), static memory data input/output
bit 3 with internal pull-down resistor
SM_D12
188
input/output
4
reserved (do not connect), static memory data input/output
bit 12 with internal pull-down resistor
SM_D2
189
input/output
4
reserved (do not connect), static memory data input/output
bit 2 with internal pull-down resistor
VSSP
190
ground
−
pad ground
SM_D13
191
input/output
4
reserved (do not connect), static memory data input/output
bit 13 with internal pull-down resistor
SM_D1
192
input/output
4
reserved (do not connect), static memory data input/output
bit 1 with internal pull-down resistor
SM_D14
193
input/output
4
reserved (do not connect), static memory data input/output
bit 14 with internal pull-down resistor
SM_D0
194
input/output
4
reserved (do not connect), static memory data input/output
bit 0 (LSB) with internal pull-down resistor
VDDP
195
supply
−
pad ring supply voltage (3.3 V)
SM_D15
196
input/output
4
reserved (do not connect), static memory data input/output
bit 15 (MSB) with internal pull-down resistor
SM_CS3
197
output
4
reserved (do not connect), static memory chip select output for
external ROM or RAM (active LOW)
SM_A4
198
output
4
reserved (do not connect), static memory address output bit 4
SM_A3
199
output
4
reserved (do not connect), static memory address output bit 3
VSSP
200
ground
−
pad ground
SM_A2
201
output
4
reserved (do not connect), static memory address output bit 2
SM_A15
202
output
4
reserved (do not connect), static memory address output bit 15
SM_A1
203
output
4
reserved (do not connect), static memory address output bit 1
SM_A16
204
output
4
reserved (do not connect), static memory address output bit 16
VDDP
205
supply
−
pad ring supply voltage (3.3 V)
SM_A0
206
output
4
reserved (do not connect), static memory address output bit 0
(LSB)
SM_A17
207
output
4
reserved (do not connect), static memory address output bit 17
(MSB)
SM_CS0
208
output
4
reserved (do not connect)
2001 Aug 01
12
EN 260
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
MPEG-2 video and MPEG-audio/AC-3 audio
encoder with multiplexer
SAA6752HS
Notes
1. All input pins, input/output pins (in input mode), output pins (in 3-state mode) and open-drain output pins are limited
to 3.3 V.
2. If used with external clock source the input voltage has to be limited to 2.5 V.
3. In accordance with the “IEEE 1149.1” standard.
4. Special function of pin TRST:
a) For board designs without boundary scan implementation, pin TRST must be connected to ground.
handbook, halfpage
157
208
b) Pin TRST provides easy initialization of the internal BST circuit. By applying a LOW it can be used to force the
internal Test Access Port (TAP) controller to the Test-Logic-Reset state (normal operating) at once.
156
1
SAA6752HS
104
105
53
52
Fig.2 Pin configuration.
2001 Aug 01
13
Circuit-, IC Descriptions and List of Abbreviations
9.8.7
DVDR980-985 /0X1
EN 261
IC7500: SAA7118 (VIP)
PAL/NTSC/SECAM Video Decoder with Adaptive Comb Filter,
Component Video Input, VBI-Data Slicer and High Performance Scaler
1
9.
FEATURES
The SAA7118 is a video capture device for application at
the image port of VGA controller, with following feature
high lights:
Video Acquisition/ Clock
Up to sixteen analog CVBS, split as desired (All of the
CVBS inputs optionally can be used to convert VSB
signals)
Up to eight analog Y+C inputs, split as desired
Up to four analog component inputs, with embedded or
separate sync, split as desired
Four on-chip anti-aliasing filters in front of the ADC’s
Automatic Clamp Control (ACC) for CVBS, Y and C (or
VSB) and component signal
Switchable white Peak Control
Four 9 Bit Low Noise CMOS analog-to-digital converters
at two-fold ITU-656 oversampling (27 MHz)
Digitized CVBS or Y+C-signals are available on the
expansion port
Fully programmable static gain or automatic gain
control, matching to the particular signal properties
On-Chip Line Locked Clock Generation according
ITU601
Requires only one crystal (32.11 or 24.576 MHz) for all
standards
Horizontal and vertical Sync Detection
Video Decoder
Digital PLL for Synchronization and Clock Generation
from all Standards and Non- Standard Video Sources
e.g. consumer grade VTR
Digital PLL for Synchronization and Clock Generation
from all Standards and Non- Standard Video Sources
e.g. consumer grade VTR
Automatic detection of any supported colour standard
Luminance and chrominance signal processing for PAL
BGDHIN, Combination-PAL N, PAL M, NTSC M,
NTSC-Japan, NTSC 4.43 and SECAM
Adaptive 2/4-line comb filter for two dimensional
chrominance/luminance-separation, also with VTR
signals
– Increased Luminance and Chrominance Bandwidth
for all PAL and NTSC-standards
– Reduced cross colour and cross luminance artefacts
PAL delay line for correcting PAL phase errors
SAA7118
Brightness Contrast Saturation (BCS)- adjustment,
separately for composite and baseband signals
User programmable sharpness control
Fast Blanking between component inputs and a CVBS
input through a dedicated pin
Detection of copy-protected signals acc. to the
Macrovision standard, indicating level of protection
Independent Gain and Offset - adjustment for raw data
path
Component Video Processing
Synchronous Component Video (RGB) input via fast
blanking, YCbCr input
Digital matrix
Video Scaler
Horizontal and Vertical Down-Scaling and Up-Scaling to
randomly sized windows
Horizontal and Vertical Scaling range: variable zoom to
1/64 (icon)
(Note: H and V zoom are restricted by the transfer data
rates)
Anti-Alias- and Accumulating Filter for Horizontal
Scaling
Vertical Scaling with Linear Phase Interpolation and
Accumulating Filter for Anti-Aliasing (6 bit phase
accuracy)
Horizontal Phase Correct Up- and Down-Scaling for
improved signal quality of scaled data, especially for
compression and video phone applications, with 6 bit
phase accuracy (1.2 nsec step width)
Two independent programming sets for scaler part, to
define two “ranges” per field or sequences over frames
Fieldwise switching between Decoder-part and
Expansion port (X-port) input
Brightness, contrast and saturation controls for scaled
outputs
VBI-Data Decoder and Slicer
versatile VBI-data decoder, slicer, clock regeneration
and byte synchronization
e.g. for WST, NABST, Close Caption, WSS, etc.
Audio Clock Generation
Generation of a field locked Audio Master Clock to
support a constant number of audio clocks per video
field
EN 262
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
PAL/NTSC/SECAM Video Decoder with Adaptive Comb Filter,
Component Video Input, VBI-Data Slicer and High Performance Scaler
Generation of an audio serial and left/right (channel)
clock signal
Digital I/O Interfaces
Real Time signal port (R - port), incl. continuous line
locked reference clock and real time status information
supporting RTC level 3.1 (refer to external document
“RTC Functional Specification” for details)
Bidirectional Expansion Port (X - port) with half duplex
functionality (D1), 8-bit YCbCr
– output from Decoder part, real time and unscaled, or
– input to Scaler part, e.g. video from MPEG-decoder
(extension to 16 bit possible)
Video Image port (I - port) configurable for 8 - bit data
(extension to 16 bit possible) in Master Mode (own
clock), or Slave Mode (external clock), with auxiliary
timing and hand shake signals
Discontinuous data streams supported
32-word * 4 Byte FIFO register for video output data
28-word * 4 Byte FIFO register for decoded VBI output
data
Scaled 4:2:2, 4:1:1, 4:2:0, 4:1:0 YCbCr output
Scaled 8-bit luminance only and raw CVBS data output
sliced, decoded VBI data output
Miscellaneous
Power On Control
5 V tolerant digital inputs and I/O ports
Software controlled power saving stand-by modes
supported
Programming via serial I2C-bus, full read-back ability by
an external controller, bit rate up to 400 kbit/s
Boundary Scan Test circuit complies to the IEEE Std.
1149.b1 -1994
BGA156 package
2
APPLICATIONS
Multimedia
Digital Television
Image Processing
Video Phone
PC- Editing cards
PC- Tuner cards
3
SAA7118
GENERAL DESCRIPTION
Philips X-VIP is a new Multistandard Comb Filter Video
Decoder chip with additional component processing,
providing high quality, optionally scaled, video.
The SAA7118 is a combination of a four channel analog
preprocessing circuit including source selection,
anti-aliasing filter and A/D-converter, an automatic clamp
and gain control, a Clock Generation Circuit (CGC), a
Digital
Multi
Standard
Decoder
containing
two-dimensional chrominance/luminance separation by an
adaptive comb filter and a high performance scaler,
including variable horizontal and vertical up and down
scaling and a Brightness- Contrast- Saturation- Control
circuit.
It is a highly integrated circuit for Desktop Video and
similar applications. The decoder is based on the principle
of line-locked clock decoding and is able to decode the
colour of PAL, SECAM and NTSC signals into ITU-601
compatible colour component values. The SAA7118
accepts as analog inputs CVBS or S-Video (Y+C) from TV
or VCR sources, including weak and distorted signals, as
well as baseband component signals YCbCr or RGB. An
expansion port (X-port) for digital video (bi-directional half
duplex, D1 compatible) is also supported to connect to
MPEG or video phone codec. At the so called image port
(I-port) the 7118 supports 8 (16) bit wide output data with
auxiliary reference data for interfacing to VGA controllers.
The target application for SAA7118 is to capture and
optionally scale video images, to be provided as digital
video stream through the image port of a VGA controller,
for capture to system memory, or just to provide digital
baseband video to any picture improvement processing.
SAA7118 also provides means for capturing the serially
coded data in the vertical blanking interval (VBI-data). Two
principal functions are available:
- to capture raw video samples, after interpolation to the
required output data rate, via the scaler and
- a versatile data slicer (data recovery) unit.
SAA7118 incorporates also a field locked audio clock
generation. This function ensures that there is always the
same number of audio samples associated with a field, or
a set of fields. This prevents the loss of sychronization
between video and audio, during capture or playback.
All of the A/D- converters may be used to digitize a VSB
signal for further for further decoding; a dedicated output
port and a selectable VSB clock input is provided.
The circuit is controlled via I2C-bus (full write / read
capability for all programming registers, bit rate up to 400
kbits/s)
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
PAL/NTSC/SECAM Video Decoder with Adaptive Comb Filter,
Component Video Input, VBI-Data Slicer and High Performance Scaler
4
9.
EN 263
SAA7118
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VDDx
digital supply voltage
3.0
3.3
3.6
V
VDDCx
digital core supply voltage
3.0
3.3
3.6
V
VDDA
analog supply voltage
3.1
3.3
3.5
V
Tamb
ambient temperature
0
-
70
°C
PA+D
analog and digital power dissipation(1)
-
t.b.d.
-
W
Note
1. Power consumption is measured in CVBS-input mode (only one ADC active) and 8 bit image port output mode,
expansion port is tristated
5
ORDERING AND PACKAGE INFORMATION
PACKAGE
EXTENDED TYPE
NUMBER
PINS
PIN POSITION
MATERIAL
CODE
SAA7118
156
BGA156
Plastic
SOT 472-1(BB3)
EN 264
9.
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
PAL/NTSC/SECAM Video Decoder with Adaptive Comb Filter,
Component Video Input, VBI-Data Slicer and High Performance Scaler
Video/Text Arbiter
O utput F orm atter I-P ort
Text
F IFO
Vertical S caling
H orizontal Fine(Phase-) Scaling
Audio
C lock
C bC r
H -Port
C bC r
X-Port
Y C bC rS
H P D (7:0)
XDQ
X C LK
XRDY
XTAL
X TALI
X TAL
RTC O
RTS1
Video
C lock
RTS0
LLC 2
LLC
Pow er-O n C ontrol
Pow er Supply
GPO
S
S ynchronization
S
Processing
V XD D
V XS S
VDDE
V SS E
VDDI
V SS I
VDDA
V SS A
AGNDA
AO U T
AI44
AI4D
AI43
AI42
Analog4
+
AD C 4
Fig.1 Blockdiagram SAA7118
AI41
AI3D
AI34
AI33
Analog3
+
AD C 3
AI32
AI31
XRH
S
Lum inance
Y
C O M B Filter
C
AI24
AI2D
AI23
A M C LK
X TO U T
Y
Cr
Cb
R AW
Analog2
+
AD C 2
AI22
AI21
AI14
AI1D
AI13
A LR C LK
X PD (7:0)
S
R AW
YC bCr
C hrom inance
Processing
Cr
Processing
B
Y
Cb
C om ponents
R
G
F ast Sw itch D elay
A nalog1
+
AD C 1
A I11
AI12
TD I
TD O
X RV
YC bC r
S
IIC R egister M A P
C ontrol
TR S TN
X TR I
Analog Input C ontrol
FSW
C LKE XT
TC K
A M XC LK
D ecoder O utput C ontrol
AD -Port
AD P(8:0)
VBI D ata S licer
Line F IFO Buffer
CE
TM S
A SC LK
F IR -P refilter
Prescaler
BC S-Scaler
TE ST
R ES O N
Video FIFO
Scaler Event C ontroller
2nd Task IIC R egister M ap Scaler
1st Task IIC R egister M ap Scaler
SDA
AG ND
IN T_A
SCL
B oundary Scan
ITR I
ITR D Y
ID Q
IC LK
IPD (7:0)
IG P H
IG P V
IG P 0
IG P 1
SYSTEM BLOCK DIAGRAM
B lockdiagram S A A 7118
6
SAA7118
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
PAL/NTSC/SECAM Video Decoder with Adaptive Comb Filter,
Component Video Input, VBI-Data Slicer and High Performance Scaler
7
PINNING AND CONFIGURATION
MXXxxx
handbook, halfpage
P
N
M
L
K
J
H
G
F
E
D
C
B
A
SAA7118
SAA7108E
SAA7109E
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Bottom View
Fig.2 Package/Pinning SAA7118
7.1
Pinning List
Table 1
Pinning List SAA7118
PIN
NAME
TYPE
A02
XTOUT
O
Crystal oscillator output signal
DESCRIPTION
A03
XTAL
O
Connect output pin for quartz
A04
VXSS
P
Ground for crystal oscillator
A05
TDO
O
Test Data Output for Boundary Scan Test (2)
A06
XRDY
O
Status flag or ready signal from scaler
A07
XCLK
I/O
Clock I/O expansion port
A08
XPD0
I/O
LSB of expansion port bus
A09
XPD2
I/O
MSB-5 of expansion port bus
A10
XPD4
I/O
MSB-3 of expansion port bus
A11
XPD6
I/O
MSB-1 of expansion port bus
A12
TEST5
I/pu
Scan test input; do not connect
A13
TEST3
I/pu
Scan test input; do not connect
B01
AI41
I
Analog input #41
B02
RES1
O
Reserved pin for future extensions or testing, do not connect
B03
VXDD
P
Supply for crystal oscillator
9.
EN 265
SAA7118
EN 266
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
PAL/NTSC/SECAM Video Decoder with Adaptive Comb Filter,
Component Video Input, VBI-Data Slicer and High Performance Scaler
SAA7118
PIN
NAME
TYPE
DESCRIPTION
B04
XTALI
I
B05
TDI
I/pu
Test Data Input for Boundary Scan Test (with internal pull-up) (2)
B06
TCK
I/pu
Test Clock for Boundary Scan Test (with internal pull-up) (2)
B07
XDQ
I/O
Data qualifier for expansion port
B08
XPD1
I/O
MSB-6 of expansion port bus
B09
XPD3
I/O
MSB-4 of expansion port bus
B10
XPD5
I/O
MSB-2 of expansion port bus
B11
XTRI
I
B12
TEST4
O
B13
RES2
NC
Reserved pin for future extensions or testing, do not connect
B14
RES3
NC
Reserved pin for future extensions or testing, do not connect
C01
VSSA4
P
Ground for analog input AI4x
C02
AGND
P
Analog Signal Ground
C03
RES4
NC
Reserved pin for future extensions or testing, do not connect
C04
RES5
NC
Reserved pin for future extensions or testing, do not connect
C05
VDDE1
P
C06
TRSTN
I/pu
Test ReSeT Not for Boundary Scan Test (with internal pull-up) (1)
C07
XRH
I/O
Horizontal reference expansion-port
Connect input pin for quartz
X-port output control signal; effects (XPD[7:0], XRH, XRV, XDQ and XCLK)
Scan test output; do not connect
Digital supply peripheral cells
C08
VDDI1
P
Digital supply core
C09
VDDE2
P
Digital supply peripheral cells
C10
VDDI2
P
Digital supply core
C11
XPD7
I/O
MSB of expansion port bus
C12
RES6
NC
Reserved pin for future extensions or testing, do not connect
C13
RES7
NC
Reserved pin for future extensions or testing, do not connect
C14
TEST2
I/pu
Scan test input; do not connect
D01
AI43
I
Analog input #43
D02
AI42
I
Analog input #42
D03
AI4D
I/O
D04
VDDA4
P
Supply for analog input AI4x
D05
VSSE1
P
Digital ground peripheral cells
D06
TMS
I/pu
D07
VSSI1
P
D08
XRV
I/O
D09
VSSE2
P
Differential input for AI4x
Test Mode Select for Boundary Scan Test or Scan Test (with internal pull-up) (2)
Digital ground core (Substrate connection)
Vertical reference for expansion-port
Digital ground peripheral cells
D10
VSSI2
P
Digital ground core
D11
VSSE3
P
Digital ground peripheral cells
D12
VDDE3
P
Digital supply peripheral cells
D13
TEST1
I/pu
Scan test input; do not connect
D14
HPD0
I/O
LSB of H-port bus, extended CbCr input for X-port, extended CbCr output for
I-port
E01
AI44
I
Analog input #44
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
PAL/NTSC/SECAM Video Decoder with Adaptive Comb Filter,
Component Video Input, VBI-Data Slicer and High Performance Scaler
9.
EN 267
SAA7118
PIN
NAME
TYPE
DESCRIPTION
E02
VDDA4A
P
Supply for analog input AI4x
E03
AI31
I
Analog input #31
E04
VSSA3
P
Ground for analog input AI3x
E11
HPD1
I/O
MSB-6 of H-port bus, extended CbCr input for X-port, extended CbCr output for
I-port
E12
HPD3
I/O
MSB-4 of H-port bus, extended CbCr input for X-port, extended CbCr output for
I-port
E13
HPD2
I/O
MSB-5 of H-port bus, extended CbCr input for X-port, extended CbCr output for
I-port
E14
HPD4
I/O
MSB-3 of H-port bus, extended CbCr input for X-port, extended CbCr output for
I-port
F01
AI3D
I/O
Differential input for AI3x
F02
AI32
I
Analog input #32
F03
AI33
I
Analog input #33
F04
VDDA3
P
Supply for analog input AI3x
F11
VSSI3
P
Digital ground core
F12
VDDI3
P
Digital supply core
F13
HPD5
I/O
MSB-2 of H-port bus, extended CbCr input for X-port, extended CbCr output for
I-port
F14
HPD6
I/O
MSB-1 of H-port bus, extended CbCr input for X-port, extended CbCr output for
I-port
G01
AI34
I
Analog input #34
G02
VDDA3A
P
Supply for analog input AI3x
G03
AI22
I
Analog input #22
G04
AI21
I
Analog input #21
G11
VSSE4
P
Digital ground peripheral cells
G12
IPD1
O
MSB-6 of Image port bus
G13
HPD7
I/O
MSB of H-port bus, extended CbCr input for X-port, extended CbCr output for
I-port
G14
IPD0
O
LSB of Image port bus
H01
AI2D
I/O
Differential input for AI2x
H02
AI23
I
Analog input #23
H03
VSSA2
P
Ground for analog input AI2x
H04
VDDA2
P
Supply for analog input AI2x
H11
IPD2
O
MSB-5 of Image port bus
H12
VDDE4
P
Digital supply peripheral cells
H13
IPD4
O
MSB-3 of Image port bus
H14
IPD3
O
MSB-4 of Image port bus
J01
VDDA2A
P
Supply for analog input AI2x
J02
AI11
I
Analog input #11
J03
AI24
I
Analog input #24
J04
VSSA1
P
Ground for analog input AI1x
EN 268
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
PAL/NTSC/SECAM Video Decoder with Adaptive Comb Filter,
Component Video Input, VBI-Data Slicer and High Performance Scaler
PIN
NAME
TYPE
DESCRIPTION
J11
VSSI4
P
Digital ground core
J12
VDDI4
P
Digital supply core
J13
IPD6
O
MSB-1 of Image port bus
J14
IPD5
O
MSB-2 of Image port bus
K01
AI12
I
Analog input #12
Analog input #13
K02
AI13
I
K03
AI1D
I/O
K04
VDDA1
P
Supply for analog input AI1x
K11
IPD7
O
MSB of Image port bus
K12
IGPH
O
Multi purpose horizontal reference signal
K13
IGP1
O
General purpose signal #1
K14
IGPV
O
Multi purpose vertical reference signal
L01
VDDA1A
P
Supply for analog input AI1x
L02
AGNDA
P
Analog signal ground connection
L03
AI14
I
Analog input #14
L04
VSSE5
P
Digital ground peripheral cells
L05
VSSI5
P
Digital ground core
L06
ADP6
O
MSB-2 of Direct A/D-converted output bus (VSB)
L07
ADP3
O
MSB-5 of Direct A/D-converted output bus (VSB)
L08
VSSE6
P
Digital ground peripheral cells
L09
VSSI6
P
Digital ground core
L10
RTCO
L11
VSSE7
P
L12
ITRI
I/O
Image-port control signal, effects all Image port pins
L13
IDQ
O
Data qualifier for image port
L14
IGP0
O
General purpose signal #0
M01
AOUT
O
Analog test output (not for use in application)
Differential input for AI1x
O/st/pd RTC output;
strap to LOW (4k7) for first I2C slave address 42h
(3)
strap to HIGH (4k7) for second I2C slave address 40h
Digital ground peripheral cells
M02
VSSA0
P
Ground for internal clock generator
M03
VDDA0
P
Supply for internal clock generator
M04
VDDE5
P
Digital supply peripheral cells
M05
VDDI5
P
Digital supply core
M06
ADP7
O
MSB-1 of Direct A/D-converted output bus (VSB)
M07
ADP2
O
MSB-6 of Direct A/D-converted output bus (VSB)
M08
VDDE6
P
Digital supply peripheral cells
M09
VDDI6
P
Digital supply core
M10
RTS0
O
Real time status or sync information
M11
VDDE7
P
Digital supply peripheral cells
M12
AMXCLK
I
Audio Master External clock input
SAA7118
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
PAL/NTSC/SECAM Video Decoder with Adaptive Comb Filter,
Component Video Input, VBI-Data Slicer and High Performance Scaler
9.
EN 269
SAA7118
PIN
NAME
TYPE
M13
FSW
I/pd
Fast Switch (Blanking), with internal pull-down,
inserts component inputs into CVBS signal
M14
ICLK
I/O
Clock output signal for image-port, LCLK of LPB image port mode, or optional
asynchronous backend clock input
N01
RES8
NC
Reserved pin for future extensions or testing, do not connect
N02
RES9
I/pu
Reserved pin for future extensions or testing, do not connect
N03
RES10
I/pd
Reserved pin for future extensions or testing, do not connect
N04
CE
I/pu
N05
LLC2
O
Line-locked clock at half frequency (13.5 MHz nominal)
N06
CLKEXT
I
External clock input intended for A/D-conversion of VSB signals (36 MHz)
N07
ADP5
O
MSB-3 of Direct A/D-converted output bus (VSB)
N08
ADP0
O
LSB of Direct A/D-converted output bus (VSB)
N09
SCL
I
I2C Serial Clock
N10
RTS1
O
Real time status or sync information
N11
ASCLK
O
Audio serial clock
N12
ITRDY
I
Target Ready for image port bus
N13
RES11
NC
Reserved pin for future extensions or testing, do not connect
N14
RES12
NC
Reserved pin for future extensions or testing, do not connect
P02
RES13
I/O
Reserved pin for future extensions or testing, do not connect
P03
EXMCLR
I/pd
External Mode Clear, with internal pull-down
P04
LLC
O
Line-locked clock (27 MHz nominal)
P05
RESON
O
Reset Output Not signal
P06
ADP8
O
MSB of Direct A/D-converted output bus (VSB)
P07
ADP4
O
MSB-4 of Direct A/D-converted output bus (VSB)
P08
ADP1
O
MSB-7 of Direct A/D-converted output bus (VSB)
P09
INT_A
O/od
I2C interrupt flag (Low if any enabled status bit has changed)
P10
SDA
I/O/od
I2C Serial Data
P11
AMCLK
O
P12
ALRCLK
P13
TEST0
DESCRIPTION
Chip Enable or Reset with internal pull-up
Audio Master clock, must be less than half the crystal clock frequency
O/st/pd Audio left/right clock,
strap to LOW (4k7) for 24.576 MHz crystal
strap to HIGH (4k7) for 32.11 MHz crystal (3)
I/pu
Scan test input; do not connect
TYPE description:
I=input, O=output, P=power, NC=not connected, st=strapping, pu=pull-up, pd=pull-down, od=open drain
Notes
1. This pin provides easy initialization of BST circuitry. TRSTN can be used to force the TAP (Test Access Port)
controller to the Test-Logic-Reset state (normal operation) at once
2. According to the IEEE1149.b1-1994 standard the pads TDI and TMS are input pads with a internal pull-up transistor
and TDO a tri-state output pad. TCK, TRSTN are also built with internal pile-up
3. Strapping remark: If the strapping pin is unused, the internal pull-down resistor is sufficient for strap function.
If pin is used in an application, an external strapping resistor (4,7k) is necessary to get a certain strap function.
EN 270
9.8.8
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
FLI2200
FLI2200
Description
The FLI2200 is a single chip implementation of Faroudja
Laboratories’ award winning deinterlacing and postprocessing algorithms that produce the highest quality
progressive video output from a variety of interlaced video
inputs including 525/60 (NTSC) or 625/50 (PAL or SECAM).
It uses patented and patent pending motion-adaptive
deinterlacing that selects the optimal filtering on a per-pixel
basis. This includes detection and proper interleaving of 3:2
and 2:2 pulldown for film-base sources, including continuous
monitoring and compensation for bad edits that occur
frequently in broadcast material due to poor scene cuts or
insertion of commercials. Video material is processed by a
set of content-sensitive spatio-temporal filters that adapt to
the appropriate direction for smoothest interpolation using
the patented Faroudja DCDi™ algorithm. The FLI2200 also
includes motion-adaptive cross-color suppression that
removes highly objectionable coloration artifacts produced
by commonly used video decoders. Its internal processing
uses 10 bits per channel to maintain the highest quality. Its
inputs and outputs are 10 bits/channel for best quality but
also supports 8 bits/channel for more cost-sensitive
applications. The FLI2200 requires 4 MB of low cost SDRAM
for best quality deinterlacing, but it can also be operated in
an optimized intra-field mode without memory for more costsensitive applications. This makes possible the use of a
single design for both high-end and low-end applications.
The FLI2200 integrates a number of functions to provide
maximum flexibility in a low cost configuration. This includes
an on-chip clock generator, SDRAM controller, display
controller, input and output color-space converters. It uses
a standard 2-wire serial control interface for easy control
and access to the registers.
The FLI2200 can be connected without glue logic to the
FLI2000 video decoder and FLI2220 Enhancer and OSD
Generator to produce the highest quality video pipeline for
premium applications. It is also fully compatible with other
decoders having a ITU-R BT 656 output format.
Applications
Flat panel TV – LCD, PDP
Progressive scan TVs
Multimedia front/rear projectors
Home Theater
Scan Converters
Multimedia PCs/Workstations
DCDi™ is a Faroudja trademark
Features
Motion-adaptive cross-color suppression removes
artifacts produced by improper Y/C separation in lowcost video decoders
Motion-adaptive video deinterlacing selects optimal
filtering on a per-pixel basis
Film-mode for proper handling of 3:2 and 2:2
pulldown material
Bad-edit detection/correction compensates for poor
scene cuts and insertions common in broadcast
material
Motion-weighted interpolation for video sources
produces maximum resolution without introducing
motion artifacts
Directional Correlational Deinterlacing (DCDi™)
minimizes jaggies on angled lines
8/10-bit Y/Cb/Cr (D1) (ITU-R BT 656), 16/20-bit Y Cb/Cr
(ITU-R BT 601), 24/30-bit RGB or YCbCr/YPbPr
interlaced input options
Supports 525/60 (NTSC), 625/50 (PAL/SECAM)
Accepts up to 1100 pixels/line
8/10-bit, 16/20-bit YUV, 24/30-bit RGB or YCbCr/YPbPr
progressive output options
Supports 8- or 10-bit inputs and outputs
10-bit internal processing for highest quality
Includes color-space converters at input and output
for maximum flexibility
Auto-detection of NTSC/PAL/SECAM inputs
High-order filtering produces smooth chroma output in
4:2:2 to 4:4:4 or 4:4:4 to 4:2:2 conversions
Resolution recovery maximizes output signal-to-noise
ratio and dynamic range
Can be operated without glue logic with FLI2000 Video
Decoder and FLI2220 Enhancer and OSD Generator ICs
to produce highest quality video pipeline
Glue-less interface to most standard video decoders
Built-in display timing generator
On-chip clock generator eliminates external PLLs
On-chip SDRAM controller
Uses low cost SDRAM as field memory – 4 MB
Optimized intra-field operation allows memory-less
configuration for lowest cost applications with same
design and layout as for high-end applications
2-wire serial control interface for easy control
176-pin TQFP package
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
Simplified Block Diagram
Ext. Syncs
PIXCLK
10
DADDR
SDA
SCL
10
Deinterlacer Core with DCDi™,
RGB /YUV/
YCrCb/D1
Input
Signal
Formatter
2
Sync
Out
Sync
Generator
PLL/Clock
Generator
Output
Signal
Formatter
Motion Compensation,Film
Mode Detection
and Bad Edit Correction
YU V/
RGB/
YCrCb
Control
Interface and
Registers
140
150
160
1
130
10
120
20
110
30
100
80
70
60
50
40
90
DADDR0
MODE
SDA
SCL
RESETB
TEST3
TEST2
NOMEM
OE
VDD25
VSS
IFORMAT2
IFORMAT1
IFORMAT0
OFORMAT2
OFORMAT1
OFORMAT0
N/P/IN/OUT
VDD33
VSS
G/YOUT9
G/YOUT8
G/YOUT7
G/YOUT6
G/YOUT5
G/YOUT4
G/YOUT3
G/YOUT2
VDD33
VSS
G/YOUT1
G/YOUT0
R/CrOUT9
R/CrOUT8
R/CrOUT7
R/CrOUT6
R/CrOUT5
R/CrOUT4
R/CrOUT3
VDD33
VSS
R/CrOUT2
R/CrOUT1
R/CrOUT0
VDD33
VSS
HSYNCREFI
VSYNCREFI
FIELDIN
B/CbIN0
B/CbIN1
B/CbIN2
B/CbIN3
B/CbIN4
B/CbIN5
B/CbIN6
B/CbIN7
B/CbIN8
B/CbIN9
VDD25
VSS
G/YIN0
G/YIN1
G/YIN2
G/YIN3
G/YIN4
G/YIN5
G/YIN6
G/YIN7
G/YIN8
G/YIN9
R/CrIN0
R/CrIN1
R/CrIN2
R/CrIN3
R/CrIN4
VDD33
VSS
R/CrIN5
R/CrIN6
R/CrIN7
R/CrIN8
R/CrIN9
PIXCLK
TEST4
AVDD
AVSS
DADDR1
170
DATA29
DATA28
DATA27
DATA26
DATA25
DATA24
DATA23
DATA22
VSS
VDD33
DATA21
DATA20
DATA19
DATA18
DATA17
DATA16
DATA15
VSS
VDD25
DATA14
DATA13
DATA12
DATA11
DATA10
VSS
VDD33
DATA9
DATA8
DATA7
DATA6
DATA5
VSS
VDD33
DATA4
DATA3
DATA2
DATA1
DATA0
VSS
VDD33
ADDR0
ADDR1
ADDR2
ADDR3
Pin description
VSS
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
VSS
VDD33
BSEL
CASN
RASN
WEN
MEMCLKO
YCLKO
CCLKO
VSS
VDD33
TESTO0
TESTO1
TEST0
FILM
TEST1
FSYNC
VDD25
VSS
VDD33
B/CbOUT0
B/CbOUT1
B/CbOUT2
B/CbOUT3
B/CbOUT4
B/CbOUT5
B/CbOUT6
B/CbOUT7
VSS
VDD33
B/CbOUT8
B/CbOUT9
H/CSYNCO
VSYNC/CREFO
HREFO
VREFO
EN 271
EN 272
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Pin Connections and Functions
Pin #
Name
Description
Power Supply Connections (not shown on Block diagram)
See list
VSS
Ground connections. Connect to the digital ground plane. Pins: 2, 17, 34, 55, 64, 74, 85,
96, 106, 115, 124, 132, 138, 145, 152, 159, 168
See list
VDD33
Pad Ring digital power connections. Connect to the digital 3.3 volt power supply and
decouple to the digital ground plane. Pins: 1, 33, 63, 73, 84, 95, 105, 114, 123, 137, 144,
151, 167
See list
VDD25
Core Logic digital power connections. Connect to the digital 2.5 volt power supply and
decouple to the digital ground plane. Pins: 16, 54, 107, 158
43
AVSS
Ground connection for the clock PLL circuits. Connect to the digital ground plane
42
AVDD
Analog power connections for the clock PLL circuit. Connect to a separately decoupled 2.5
volt power supply and decouple directly to the AVSS pin..
Control Signals
49
RESETB
Reset. When this input is set low it will reset all the internal registers to the default states.
Refer to the section on the control registers for details of these states. The device must be
reset after it is powered-up.
53
OE
When this pin is set high the outputs of the FLI2200 will be enabled; when it is set low the
outputs will be set into a high-impedance state.
56-58
IFORMAT2-0 Input signal format control. The settings of these pins set the format of the input signal.
This can be overridden by the IFmtOvr bit, bit 3 in register 00 H, allowing this function to be
set or changed via the I2C bus. Please refer to the description of register 00 H for details.
59-61
OFORMAT2-0 Output signal format control. The settings of these pins set the format of the output signal.
This can be overridden by the OFmtOvr bit, bit 3 in register 07 H, allowing this function to be
set or changed via the I2C bus. Please refer to the description of register 07H for details.
44-45
DADDR1-0
The settings of DADDR1-0 allow the device address of the control bus to be programmed to
prevent conflict with the other devices connected to the bus. DADDR 1-0 allow the device
address to be set to any of the following values: C0/C1H, C2/C3H, E0/E1H, E2/E3H. Please refer
to the section “Control Bus Operation and Protocol” for further information.
46
MODE
When this pin is set low the control bus will operate in the slave mode; allowing the device to
programmed from an external controller. When it is set high the FLI2200 will self-program from
an external I2C memory connected to the bus. Please refer to the “Control Bus Operation and
Control Protocol” section for more details.
47
SDA
2-wire serial control bus data. Data can be written to the control registers via this pin when it
is in the input mode and data can be read from the status registers when it is in the output
mode. Refer to the section on the serial port for timing and format details and to the section on
the registers for programming information.
48
SCL
2-wire serial control bus clock. When the control port operates in slave mode this pin will be
an input and when it operates in the self programming mode it will be an output.
40
PIXCLK
Pixel clock input. This clock is used to drive all the circuits in the FLI2200. An internal PLL is
used to upconvert this clock to provide the master clock signal and other clocks used
internally. Note that when the FLI2200 is used in the D1 input mode the PIXCLK input
should run at the rate of two cycles per pixel (one for luma and one for chroma).
62
N/P/IN/OUT NTSC/PAL input or output. The default function of this pin is NTSC/PAL signal indicator
output. When the input video signal is a 525 line signal this pin will be set high and when it
is a 625 line signal the pin is set low. This function of this pin can be programmed to be an
input according to the setting of this pin if the NPOp1-0 bits, bits 5-4 in register 03H, are set
to 00H, overriding the internal line counter. i.e., it will treat the signal as a 525 line signal
when it is set high and a 625 line signal when it is set low.
Circuit-, IC Descriptions and List of Abbreviations
Pin #
Name
DVDR980-985 /0X1
9.
EN 273
Description
Control Signals (contd.)
52
NOMEM
No Memory Mode control input. This pin controls the operation of the FLI2200 as follows:
When this pin is set low the device is used with external field memories and operates in the full
set of deinterlacing modes, i.e., motion adaptive video deinterlacing and full frame film source
deinterlacing using 3:2 pulldown detection (2:2 pulldown for 625/50 sources). When this pin is
set high the FLI2200 is forced into the intra-field only deinterlacing mode, which requires no
external memories, allowing the FLI2200 to be used in low-cost applications where the ultimate
video quality is not a requirement. To ensure proper startup of the SDRAMs this pin should be
set high during the power-up sequence. This can be overridden by the NMOvr bit, bit 1 in
register 05H, allowing this function to be set or changed via the I 2C bus. Please refer to the
description of register 05H for details.
Input Signals
27-18
G/YIN9-0
10-bit green or luminance signal input bus. The mode is set by the IFORMAT2-0 pins. This can
be overridden by the IFmtOvr bit, bit 3 in register 00H, allowing this function to be set or
changed via the I2C bus. Please refer to the description of register 00 H for details. This
signal is sampled on the rising edge of PIXCLK.
15-6
B/CbIN9-0
10-bit blue or Cb chroma signal input bus. The mode is set by the IFORMAT2-0 pins.
This can be overridden by the IFmtOvr bit, bit 3 in register 00 H, allowing this function to be
set or changed via the I2C bus. Please refer to the description of register 00H for details. Bits 6,
4 and 3 in register 08H specify the busses used in the multiplexed modes. In all cases the
signals are sampled on the rising edges of PIXCLK. In the Y Cb Cr and Y Pb Pr modes the Cb or
Pb signal is sampled on alternate rising edges of PIXCLK in 4:2:2 mode. The frequency of
PIXCLK will be 27 MHz in the multiplexed Y/Cb/Cr mode and 13.5 MHz in all other modes.
These pins should be tied low when not used.
39-35
32-28
R/CrIN9-0
10-bit red or Cr chroma signal input bus. The mode is set by the IFORMAT2-0 pins.
This can be overridden by the IFmtOvr bit, bit 3 in register 00H, allowing this function to be
set or changed via the I2C bus. Please refer to the description of register 00H for details. Bits 6,
4 and 3 in register 08H specify the busses used in the multiplexed modes. In all cases the
signals are sampled on the rising edges of PIXCLK. In the Y Cb Cr mode the Cr signal is
sampled on alternate rising edges of PIXCLK in 4:2:2 mode. The frequency of PIXCLK will
be 27 MHz in the multiplexed Y/Cb/Cr mode and 13.5 MHz in all other modes. These pins
should be tied low when not used.
3
HSYNCREFI
Horizontal sync or reference. The horizontal sync or reference of the input signal should be
connected to this pin. The function is programmed with bit 4 in register 00H. The polarity
and position of the sync or reference pulse relative to the start of active video are both
programmable within a small range. When the FLI2200 is used in the ITU-R BT 601/D1 input
mode with embedded syncs (IFormat = 110) this input is not used and should be tied low; in
this case all sync information will be derived from the signal.
4
VSYNCREFI
Vertical sync or reference. The vertical sync or reference of the input signal should be
connected to this pin. The function is programmed with bit 4 in register 00H. The polarity
and position of the sync or reference pulse relative to the start of active video are both
programmable within a small range. When the FLI2200 is used in the ITU-R BT 601/D1 input
mode with embedded syncs (IFormat = 110) this input is not used and should be tied low; in
this case all sync information will be derived from the signal.
5
FLDIN
Field identifier input. The field identifier output of the source signal should be connected to
this pin. A low setting signifies an even field and a high level signifies an odd field. When
bit 4 in register 00H is set low, the input timing is based on HREF and VREF and this signal
is required. When this bit is set high the input timing is based on HSYNC and VSYNC and this
signal is generated internally and is not required. When bit 5 in register 06 is set high this
signal is also used as the frame boundary identifier for 30 Hz film sources.
EN 274
Pin #
9.
DVDR980-985 /0X1
Name
Circuit-, IC Descriptions and List of Abbreviations
Description
Output Signals
65-72
75-76
G/YOUT9-0
Green or luminance output bus. In the RGB mode this output is the Green signal and in the
YCbCr mode it is the Y signal. The mode is set by the OFORMAT2-0 pins. This can be
overridden by the OFmtOvr bit, bit 3 in register 07 H, allowing this function to be set or
changed via the I2C bus. Please refer to the description of register 07H for details. The signal
is clocked out on the falling edge of YCLKO.
93-94
97-104
B/CbOUT9-0
Blue or Cb chrominance output bus. In the RGB mode this output is the Blue signal, in the
Y Cb Cr mode it is the Cb signal. The mode is set by the OFORMAT2-0 pins. This can be
overridden by the OFmtOvr bit, bit 3 in register 07 H, allowing this function to be set or
changed via the I2C bus. Please refer to the description of register 07H for details. The busses
used in the multiplexed modes are set by means of bit 5 in register 08H. The signal is clocked
out on the falling edge of YCLKO in the RGB and YUV 4:4:4 modes, on the falling edge of
YCLKO prior to the next rising edge of CCLKO in the YUV 4:2:2 mode, and on the rising edge of
MEMCLKO in the multiplexed YCbCr (pseudo D1) mode.
77-83
86-88
R/CrOUT9-0
Red or Cr chrominance output bus. In the RGB mode this output is the Red signal, in the
YCbCr mode it is the Cr signal. The mode is set by the OFORMAT 2-0 pins. This can be
overridden by the OFmtOvr bit, bit 3 in register 07 H, allowing this function to be set or
changed via the I2C bus. Please refer to the description of register 07H for details. The busses
used in the multiplexed modes are set by means of bit 5 in register 08H. The signal is clocked
out on the falling edge of YCLKO in the RGB and YUV 4:4:4 modes, on the falling edge of
YCLKO prior to the next rising edge of CCLKO in the YUV 4:2:2 mode, and on the rising edge of
MEMCLKO in the multiplexed YCbCr (pseudo D1) mode.
116
CCLKO
Chroma output sampling clock. This clock is derived from PIXCLK and will be at half the
frequency of YCLKO. In 30-bit 4:2:2 output mode the chroma output signals will change on
the falling edge of YCLKO prior to the next rising edge this clock.
117
YCLKO
Luma output sampling clock. This clock is derived from PIXCLK and is double the
frequency of PIXCLK. In 30-bit and 20-bit output modes the output signals will change on the
falling edge of this clock.
89
VREFO
Start of active field or frame indicator. This signal goes high to indicate the first active line
in each field or frame and goes low during the vertical blanking interval. The polarity and timing
of this signal are programmable.
90
HREFO
Start of active line indicator output. This signal goes high to indicate the first active pixel in
each line and goes low during the horizontal blanking interval. The polarity and timing of
this signal are programmable.
91
VSYNC/
CREFO
Vertical sync output. This signal provides the vertical sync function for the outputs. Its
polarity is programmable to be active high or active low. It can also be programmed to be a
composite reference for applications requiring this instead of sync.
92
H/CSYNCO
Horizontal or composite sync output. This signal provides the horizontal sync function for
the outputs. Its polarity is programmable to be active high or active low. This signal can also
be programmed to be the composite sync output, CSYNC.
108
FSYNC
Film mode sync output. When film mode is detected this pin will toggle in sync with the 3:2
(NTSC) or 2:2 (PAL and 30 Hz film in NTSC) pulldown sequence detected in the source.
110
FILM
Film mode detector output. This pin will be set high when the FLI2200 detects that the video
input was converted from 24 fps film with a teleciné machine. If film mode is not detected this
pin will be set low.
Circuit-, IC Descriptions and List of Abbreviations
Pin #
Name
DVDR980-985 /0X1
9.
EN 275
Description
SDRAM Interface Signals
125-131
133-136
ADDR10-0
SDRAM Address bus. This signal bus is used to address the external SDRAM(s) used for
field memories. It should be connected to the A10-0 bus of the memory chip(s). Please refer
to the Applications section of this data sheet for further details.
176-169 DATA29-0
166-160
157-153
150-146
143-139
SDRAM Data bus. This signal bus is used to transfer the data to and from the external
SDRAM(s) used for field memories. It should be connected to the DQ29-0 bus of the memory
chip when using a 64 Mbit SDRAM. When using two 16 Mbit SDRAMs this 30-bit bus may
be connected to the two 16-bit data busses of the memories in two ways: either connect 16
lines to one chip and 14 to the other, or connect 15 to both. In all cases the two unused data
lines on the memory chip(s) should be connected to ground via 22 k resistors. Please refer
to the Applications section of this data sheet for further details.
118
MEMCLKO
SDRAM clock and 2x output sampling clock. This clock is derived from PIXCLK and will be at
double the frequency of YCLKO. This active signal should be connected to the CLK pin(s) on
the SDRAM(s). When the 10-bit output mode selected the output signals will also change at
this clock rate and this should then be used as the output clock..
119
WEN
SDRAM Write Enable. This active low signal should be connected to the WE pin(s) on the
SDRAM(s).
120
RASN
SDRAM Row Address Select. This active low signal should be connected to the RAS pin(s)
on the SDRAM(s).
121
CASN
SDRAM Column Address Select. This active low signal should be connected to the CAS
pin(s) on the SDRAM(s).
122
BSEL
SDRAM Bank Select. When using two 16 Mbit SDRAMs this signal should be connected to
the BA (also called BS or A11) pin on both SDRAMs. When using a 64 Mbit SDRAM this
signal should be connected to the BA0 (also called BS0 or A11) pin on the SDRAM and BA1/
BS1 (also called BA when BA0 is referred to as A11) should be tied low.
Test Inputs
41, 50, TEST4-0
51, 109,
111
These pins are used for test purposes only and should always be tied low for normal operation.
Test Outputs
112, 113 TESTO1-0
These pins are test outputs and should be left unconnected in normal operation.
EN 276
9.8.9
9.
ADV7196
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 277
EN 278
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 279
EN 280
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
9.8.10 ADV7196
SHARPNESS
FILTER CONTROL
&
ADAPTIVE
FILTER CONTROL
CGMS
MACROV ISION
Y0-Y9
Cr0-9
Cb 0-9
TESTPA TTERN
GENERATOR
&
DELAY
&
GAMMA
CORRECTION
LUMA
SSAF
CHROMA
4:2:2 to 4:4:4
(SSAF)
2XINTERPOLATION
11-BIT +
SYNC
DAC
DAC A (Y)
11-BIT
DAC
DAC B
11-BIT
DAC
DAC C
CHROMA
4:2:2 to 4:4:4
(SSAF)
VREF
DAC CONTROL
BLOCK
CLK IN
RSET
COMP
HORIZ ONTALSYNC
VERTICA L SYNC
TIM ING
GENERATOR
SYNC
GENERATOR
BLA NKING
RESET
I2 C MPU PORT
Cb/Cr[9]
ALSB
RESET
44
DVDR980-985 /0X1
Cb/Cr[8]
52 51 50 49 48 47 46 45
Cb/Cr[7]
Cb/Cr[6]
Cb/Cr[5]
Cb/Cr[4]
Cb/Cr[1]
Cb/Cr[2]
Cb/Cr[3]
Cb/Cr[0]
GND
Circuit-, IC Descriptions and List of Abbreviations
43
42
41
40
39
VREF
2
38
RSET
Y[1]
3
37
COMP
Y[2]
4
36
DAC B
Y[3]
5
35
VAA
Y[4]
6
Y[5]
7
Y[6]
VDD
Y[0]
1
Pin Id
34
ADV7196 A
9.
DAC A / Y output
33
AGND
8
32
DAC C
Y[7]
9
31
Y[8]
Y[9]
10
30
SDA
SCL
11
29
HSYNC/SYNC
VDD
12
28
GND
13
27
VSYNC/TSYNC
DV
CLKI N
AGND
VA A
26
Cr[9]
21 22 23 24 25
Cr[8]
20
Cr[7]
Cr[4]
Cr[3]
Cr[2]
Cr[1]
Cr[0]
19
Cr[6]
15 16 17 18
Cr[5]
14
EN 281
EN 282
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
µ
Circuit-, IC Descriptions and List of Abbreviations
9.9
IC’s Divio
9.9.1
IC7101: 58PDI1394P25PHY
DVDR980-985 /0X1
9.
EN 283
PDI1394P25
1.0 FEATURES
• Fully supports provisions of IEEE 1394±1995 Standard for high
performance serial bus and the P1394a±2000 Standard1
• Fully interoperable with Firewire?
and i.LINK? implementations of
the IEEE 1394 Standard.2
• Supports extended bias-handshake time for enhanced
interoperability with camcorders
• Interface to link-layer controller supports both low-cost bus-holder
isolation and optional Annex J electrical isolation
• Full P1394a support includes:
• Data interface to link-layer controller through 2/4/8 parallel lines at
49.152 MHz
± Connection debounce
• Low-cost 24.576 MHz crystal provides transmit, receive data at
± Arbitrated short reset
100/200/400 Mbps, and link-layer controller clock at 49.152 MHz
± Multispeed concatenation
• Does not require external filter capacitors for PLL
• Interoperable with link-layer controllers using 3.3 V and 5 V
± Arbitration acceleration
± Fly-by concatenation
± Port disable/suspend/resume
• Provides one 1394a fully-compliant cable port at
100/200/400 Mbps. Can be used as a one port PHY without the
use of any extra external components
• Fully compliant with Open HCI requirements
• Cable ports monitor line conditions for active connection to remote
node.
• Power down features to conserve energy in battery-powered
applications include:
± Automatic device power down during suspend
supplies
• Interoperable with other Physical Layers (PHYs) using 3.3 V and
5 V supplies
• Node power class information signaling for system power
management
• Cable power presence monitoring
• Separate cable bias (TPBIAS) for each port
• Register bits give software control of contender bit, power class
bits, link active bit, and 1394a features
• Function and pin compatible with the Texas Instruments
± Device power down terminal
± Link interface disable via LPS
TSB41LV01? 400 Mbps Phy
± Inactive ports powered-down
• Logic performs system initialization and arbitration functions
• Encode and decode functions included for data-strobe bit level
encoding
• Incoming data resynchronized to local clock
• Single 3.3 volt supply operation
• Minimum VDD of 2.7 V for end-of-wire power-consuming devices
• While unpowered and connected to the bus, will not drive TPBIAS
2.0 DESCRIPTION
The PDI1394P25 provides the digital and analog transceiver functions
needed to implement a one port node in a cable-based IEEE
1394±1995 and/or 1394a network. Each cable port incorporates two
differential line transceivers. The transceivers include circuitry to
monitor the line conditions as needed for determining connection
status, for initialization and arbitration, and for packet reception and
transmission. The PDI1394P25 is designed to interface with a Link
Layer Controller (LLC), such as the PDI1394L11 or PDI1394L21.
on a connected port, even if receiving incoming bias voltage on
that port
3.0 ORDERING INFORMATION
PACKAGE
64-pin plastic LQFP
TEMPERATURE RANGE
ORDER CODE
PKG. DWG. #
0 to +70°C
PDI1394P25BD
SOT314-2
EN 284
9.
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
DGND
DGND
DVDD
DVDD
XO
XI
PLLGND
PLLGND
PLLV DD
NC
NC
RESET
AV DD
AV DD
AGND
AGND
4.0 PIN CONFIGURATION
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48 AGND
LREQ 1
SYSCLK 2
47 NC
CNA 3
46 NC
CTL0 4
45 NC
CTL1 5
44 NC
D0 6
43 NC
D1 7
42 AVDD
D2 8
41 R1
PDI1394P25
D3 9
40 R0
D4 10
39 AGND
24
25
26
27
28
29
30
31
AVDD
23
32
AGND
22
AVDD
21
TEST0
20
TEST1
19
TESTM
18
DVDD
DGND
17
DVDD
33 AGND
CPS
34 TPB0±
NC 16
ISO
LPS 15
PC2
35 TPB0+
PC1
36 TPA0±
PD 14
PC0
D7 13
DGND
38 TPBIAS0
37 TPA0+
C/LKON
D5 11
D6 12
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 285
5.0 PIN DESCRIPTION
Pin Type
Pin Numbers
I/O
Description
AGND
Name
Supply
32, 33, 39, 48, 49,
50
Ð
Analog circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
AVDD
Supply
30, 31, 42, 51, 52
Ð
Analog circuit power terminals. A combination of high frequency
decoupling capacitors on each side are suggested, such as paralleled
0.1 µF and 0.001 µF. These supply terminals are separated from
PLLVDD and DVDD internal to the device to provide noise isolation. They
should be tied at a low impedance point on the circuit board.
19
I/O
Bus Manager Contender programming input and link-on output. On
hardware reset, this terminal is used to set the default value of the
contender status indicated during self-ID. Programming is done by tying
the terminal through a 10-kΩ resistor to a high (contender) or low (not
contender). The resistor allows the link-on output to override the input.
C/LKON
CMOS 5 V tol
If this pin is connected to a LLC driver pin for setting Bus Manager/IRM
contender status, then a 10-kΩ series resistor should be placed on this
line between the PHY and the LLC to prevent possible contention. In this
case. the pull-high or pull-low resistors mentioned in the previous
paragraph should not be used. Refer to Figure 9.
Following hardware reset, this terminal is the link-on output, which is
used to notify the LLC to power-up and become active. The link-on
output is a square-wave signal with a period of approximately 163 ns (8
SYSCLK cycles) when active. The link-on output is otherwise driven low,
except during hardware reset when it is high impedance.
The link-on output is activated if the LLC is inactive (LPS inactive or the
LCtrl bit cleared) and when:
a) the PHY receives a link-on PHY packet addressed to this node,
b) the PEI (port-event interrupt) register bit is 1, or
c) any of the CTOI (configuration-timeout interrupt), CPSI
(cable-power-status interrupt), or STOI (state-timeout interrupt)
register bits are 1 and the RPIE (resuming-port interrupt enable)
register bit is also 1.
Once activated, the link-on output will continue active until the LLC
becomes active (both LPS active and the LCtrl bit set). The PHY also
deasserts the link-on output when a bus-reset occurs unless the link-on
output would otherwise be active because one of the interrupt bits is set
(i.e., the link-on output is active due solely to the reception of a link-on
PHY packet).
NOTE: If an interrupt condition exists which would otherwise cause the
link-on output to be activated if the LLC were inactive, the link-on output
will be activated when the LLC subsequently becomes inactive.
CNA
CMOS
3
O
Cable Not Active output. This terminal is asserted high when there are
no ports receiving incoming bias voltage.
CPS
CMOS
24
I
Cable Power Status input. This terminal is normally connected to cable
power through a 390 kΩ resistor. This circuit drives an internal
comparator that is used to detect the presence of cable power.
CTL0,
CTL1
CMOS 5 V tol
4, 5
I/O
Control I/Os. These bi-directional signals control communication
between the PDI1394P25 and the LLC. Bus holders are built into
these terminals.
D0±D7
CMOS 5 V tol
6, 7, 8, 9, 10, 11,
12, 13
I/O
Data I/Os. These are bi-directional data signals between the
PDI1394P25 and the LLC. Bus holders are built into these terminals.
Unused Dn pins should be pulled to ground through 10 kΩ resistors.
DGND
Supply
17, 18, 63, 64
Ð
Digital circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
DVDD
Supply
25, 26, 61, 62
Ð
Digital circuit power terminals. A combination of high frequency
decoupling capacitors near each side of the IC package are suggested,
such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering
capacitors are also recommended. These supply terminals are
separated from PLLVDD and AVDD internal to the device to provide noise
isolation. They should be tied at a low impedance point on the circuit
board.
EN 286
9.
Name
DVDR980-985 /0X1
Pin Type
Circuit-, IC Descriptions and List of Abbreviations
Pin Numbers
I/O
Description
ISO
CMOS
23
I
Link interface isolation control input. This terminal controls the operation
of output differentiation logic on the CTL and D terminals. If an optional
isolation barrier of the type described in Annex J of IEEE Std 1394±1395
is implemented between the PDI1394P25 and LLC, the ISO terminal
should be tied low to enable the differentiation logic. If no isolation
barrier is implemented (direct connection), or bus holder isolation is
implemented, the ISO terminal should be tied high to disable the
differentiation logic.
LPS
CMOS 5 V tol
15
I
Link Power Status input. This terminal is used to monitor the
active/power status of the link layer controller and to control the state of
the PHY-LLC interface. This terminal should be connected to either the
VDD supplying the LLC through a 10 kΩ resistor, or to a pulsed output
which is active when the LLC is powered. A pulsed signal should be
used when an isolation barrier exists between the LLC and PHY. (See
Figure 8)
The LPS input is considered inactive if it is sampled low by the PHY for
more than 2.6 µs (128 SYSCLK cycles), and is considered active
otherwise (i.e., asserted steady high or an oscillating signal with a low
time less than 2.6 µs). The LPS input must be high for at least 21 ns in
order to be guaranteed to be observed as high by the PHY.
When the PDI1394P25 detects that LPS is inactive, it will place the
PHY-LLC interface into a low-power reset state. In the reset state, the
CTL and D outputs are held in the logic zero state and the LREQ input is
ignored; however, the SYSCLK output remains active. If the LPS input
remains low for more than 26 µs (1280 SYSCLK cycles), the PHY-LLC
interface is put into a low-power disabled state in which the SYSCLK
output is also held inactive. The PHY-LLC interface is placed into the
disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the
LCtrl register bit is set to 1, and is considered inactive if either the LPS
input is inactive or the LCtrl register bit is cleared to 0.
LREQ
CMOS 5 V tol
1
I
LLC Request input. The LLC uses this input to initiate a service request
to the PDI1394P25. Bus holder is built into this terminal.
NC
No connect
54, 55
Ð
These pins are not internally connected and consequently are ªdon't
caresº. Other vendors' pin compatible chips may require
connections and external circuitry on these pins.
NC
No connect
16, 43, 44, 45, 46,
47
Ð
No connect.
PC0, PC1,
PC2
CMOS 5 V tol
20, 21, 22
I
Power Class programming inputs. On hardware reset, these inputs set
the default value of the power class indicated during self-ID.
Programming is done by tying the terminals high or low. Refer to
Table 21 for encoding.
PD
CMOS 5 V tol
14
I
Power Down input. A logic high on this terminal turns off all internal
circuitry except the cable-active monitor circuits which control the CNA
output. For more information, refer to Section 17.2
PLLGND
Supply
57, 58
Ð
PLL circuit ground terminals. These terminals should be tied together to
the low impedance circuit board ground plane.
PLLVDD
Supply
56
Ð
PLL circuit power terminals. A combination of high frequency decoupling
capacitors near each terminal are suggested, such as paralleled 0.1 µF
and 0.001 µF. These supply terminals are separated from DVDD and
AVDD internal to the device to provide noise isolation. They should be
tied at a low impedance point on the circuit board.
RESET
CMOS 5 V tol
53
I
Logic reset input. Asserting this terminal low resets the internal logic. An
internal pull-up resistor to VDD is provided so only an external
delay capacitor is required for proper power-up operation. For more
information, refer to Section 17.2. This input is otherwise a standard
Schmitt logic input, and can also be driven by an open-drain type driver.
R0, R1
Bias
Ð
Current setting resistor pins These pins are connected to an external
resistance to set the internal operating currents and cable driver output
currents. A resistance of 6.34 kΩ ±1% is required to meet the IEEE
1394±1995 Std. output voltage limits.
40, 41
Circuit-, IC Descriptions and List of Abbreviations
Name
Pin Type
SYSCLK
CMOS
TEST0
Pin Numbers
DVDR980-985 /0X1
9.
EN 287
I/O
Description
2
O
System clock output. Provides a 49.152 MHz clock signal, synchronized
with data transfers, to the LLC.
CMOS
29
I
Test control input. This input is used in manufacturing tests of the
PDI1394P25. For normal use, this terminal should be tied to GND.
TEST1
CMOS
28
I
Test control input. This input is used in manufacturing tests of the
PDI1394P25. For normal use, this terminal should be tied to GND.
Other vendors' pin compatible chips may require connections and
external circuitry on this pin.
TESTM
CMOS
27
I
Test control input. This input is used in manufacturing tests of the
PDI1394P25. For normal use, this terminal should be tied to VDD.
TPA0+
Cable
37
I/O
TPA0±
Cable
36
I/O
TPB0+
Cable
35
I/O
TPB0±
Cable
34
I/O
TPBIAS0
Cable
38
I/O
Twisted-pair bias output. This provides the 1.86 V nominal bias voltage
needed for proper operation of the twisted-pair cable drivers and
receivers, and for signaling to the remote nodes that there is an active
cable connection. These terminals must be decoupled with a
0.3 µF±1 µF capacitor to ground.
XO, XI
Crystal
59, 60
Ð
Crystal oscillator inputs. These terminals connect to a 24.576 MHz
parallel resonant fundamental mode crystal. The optimum values for the
external shunt capacitors are dependent on the specifications of the
crystal used. Can also be driven by an external clock generator (leave
XO unconnected in this case and start supplying the external clock
before resetting the PDI1394P25). For more information, refer to
Section 17.5
Twisted-pair cable A differential signal terminals. Board traces from each
pair of positive and negative
differential signal
terminals should be kept
g
g
matched and as short as possible to the external load resistors and to
the cable connector.
Twisted-pair cable B differential signal terminals. Board traces from each
pair of positive and negative
g
differential signal
g
terminals should be kept
matched and as short as possible to the external load resistors and to
the cable connector.
EN 288
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
6.0 BLOCK DIAGRAM
LPS
RECEIVED DATA
DECODER/
RETIMER
/ISO
CABLE POWER
DETECTOR
CPS
C/LKON
SYSCLK
LREQ
CTL0
CTL1
D0
CABLE PORT 0
LINK
INTERFACE
I/O
TPA0+
TPA0±
D1
D2
D3
D4
D5
D6
D7
ARBITRATION
AND CONTROL
STATE MACHINE
LOGIC
TPB0+
TPB0±
PC0
PC1
PC2
CNA
R0
R1
TPBIAS0
BIAS VOLTAGE
AND
CURRENT
GENERATOR
CRYSTAL
OSCILLATOR,
PLL SYSTEM,
AND CLOCK
GENERATOR
PD
/RESET
XI
XO
TRANSMIT
DATA
ENCODER
SV01829
7.0 FUNCTIONAL SPECIFICATION
The PDI1394P25 requires only an external 24.576 MHz crystal as a
reference. An external clock can be connected to XI instead of a
crystal. An internal oscillator drives an internal phase-locked loop
(PLL), which generates the required 393.216 MHz reference signal.
This reference signal is internally divided to provide the clock signals
used to control transmission of the outbound encoded Strobe and
Data information. A 49.152 MHz clock signal, supplied to the
associated LLC for synchronization of the two chips, is used for
resynchronization of the received data. The Power Down (PD)
function, when enabled by asserting the PD terminal high, stops
operation of the PLL and disables all circuits except the cable bias
detectors at the TPB terminals. The port transmitter circuitry and the
receiver circuitry are also disabled when the port is disabled,
suspended, or disconnected.
The PDI1394P25 supports an optional isolation barrier between
itself and its LLC. When the ISO input terminal is tied high, the
LLC interface outputs behave normally. When the ISO terminal is
tied low, internal differentiating logic is enabled, and the outputs are
driven such that they can be coupled through a capacitive or
transformer galvanic isolation barrier as described in IEEE 1394a
section 5.9.4. To operate with single capacitor (bus holder) isolation,
the ISO on the PHY terminal must be tied high. For more details on
using single capacitor isolation, please refer to the Philips Isolation
Application Note AN2452.
Data bits to be transmitted through the cable ports are received from
the LLC on two, four or eight parallel paths (depending on the
requested transmission speed). They are latched internally in the
PDI1394P25 in synchronization with the 49.152 MHz system clock.
These bits are combined serially, encoded, and transmitted at
98.304/196.608/392.216 Mbps (referred to as S100, S200, and
S400 speed, respectively) as the outbound data-strobe information
stream. During transmission, the encoded data information is
transmitted differentially on the TPB cable pair(s), and the encoded
strobe information is transmitted differentially on the TPA cable
pair(s).
During packet reception the TPA and TPB transmitters of the
receiving cable port are disabled, and the receivers for that port are
enabled. The encoded data information is received on the TPA cable
pair, and the encoded strobe information is received on the TPB
cable pair. The received data-strobe information is decoded to
recover the receive clock signal and the serial data bits. The serial
Circuit-, IC Descriptions and List of Abbreviations
data bits are split into two-, four- or eight-bit parallel streams
(depending upon the indicated receive speed), resynchronized to
the local 49.152 MHz system clock and sent to the associated LLC.
Both the TPA and TPB cable interfaces incorporate differential
comparators to monitor the line states during initialization and
arbitration. The outputs of these comparators are used by the
internal logic to determine the arbitration status. The TPA channel
monitors the incoming cable common-mode voltage. The value of
this common-mode voltage is used during arbitration to set the
speed of the next packet transmission (speed signaling). In addition,
the TPB channel monitors the incoming cable common-mode
voltage on the TPB pair for the presence of the remotely supplied
twisted-pair bias voltage (cable bias detection).
The PDI1394P25 provides a 1.86 V nominal bias voltage at the
TPBIAS terminal for port termination. The PHY contains two
independent TPBIAS circuits. This bias voltage, when seen through
a cable by a remote receiver, indicates the presence of an active
connection. This bias voltage source must be stabilized by an
external filter capacitor of 0.3 µF±1 µF.
The line drivers in the PDI1394P25 operate in a high-impedance
current mode, and are designed to work with external 112 Ω
line-termination resistor networks in order to match the 110 Ω cable
impedance. One network is provided at each end of all twisted-pair
cable connections. Each network is composed of a pair of
series-connected 56 Ω resistors. The midpoint of the pair of resistors
that is directly connected to the twisted-pair A terminals is connected
to its corresponding TPBIAS voltage terminal. The midpoint of the pair
of resistors that is directly connected to the twisted-pair B terminals is
coupled to ground through a parallel R-C network with recommended
values of 5 kΩ and 220 pF. The values of the external line termination
resistors are designed to meet the standard specifications when
connected in parallel with the internal receiver circuits. An external
resistor connected between the R0 and R1 terminals sets the driver
output current, along with other internal operating currents. This
current setting resistor has a value of 6.34 kΩ ±1%.
When the power supply of the PDI1394P25 is removed while the
twisted-pair cables are connected, the PDI1394P25 transmitter and
receiver circuitry presents a high impedance to the cable in order to
not load the TPBIAS voltage on the other end of the cable.
The TEST0 and TEST1 terminals are used to set up various
manufacturing test conditions. For normal operation, they should be
connected to ground. TEST1 can also be tied through a 1 kΩ
resistor to ground to accommodate other vendors' pin compatible
chips.
The TESTM terminal is used to set up various manufacturing test
conditions. For normal operation it should be tied to VDD.
Four package terminals, used as inputs to set the default value for
four configuration status bits in the self-ID packet, should be
hard-wired high or low as a function of the equipment design. The
PC0±PC2 terminals are used to indicate the default power-class
status for the node (the need for power from the cable or the ability
to supply power to the cable). See Table 21 for power class
encoding. The C/LKON terminal is used as an input to indicate that
the node is a contender for bus manager.
The PHY supports suspend/resume as defined in the IEEE 1394a
specification. The suspend mechanism allows pairs of directly
connected ports to be placed into a low power state while
maintaining a port-to-port connection between 1394 bus segments.
While in a low power state, a port is unable to transmit or receive
data transaction packets. However, a port in a low power state is
DVDR980-985 /0X1
9.
EN 289
capable of detecting connection status changes and detecting
incoming TPBIAS. When the PDI1394P25's port is suspended, all
circuits except the bias-detection circuits are powered down,
resulting in significant power savings. The TPBIAS circuit monitors
the value of incoming TPA pair common-mode voltage when local
TPBIAS is inactive. Because this circuit has an internal current
source and the connected node has a current sink, the monitored
value indicates the cable connection status. This monitor is called
connect-detect.
Both the cable bias-detect monitor and TPBIAS connect-detect
monitor are used in suspend/resume signaling and cable connection
detection. For additional details of suspend/resume operation, refer
to the 1394a specification. The use of suspend/resume is
recommended for new designs.
The port transmitter and receiver circuitry is disabled during power
down (when the PD input terminal is asserted high), during reset
(when the RESET input terminal is asserted low), when no active
cable is connected to the port, or when controlled by the internal
arbitration logic. The port twisted-pair bias voltage circuitry is
disabled during power down, during reset, or when the port is
disabled as commanded by the LLC.
The CNA (cable-not-active) terminal provides a high when the
twisted-pair cable port is not receiving incoming bias (i.e., it is either
disconnected or suspended), and can be used along with LPS to
determine when to power-down the PDI1394P25. The CNA output is
not debounced. When the PD terminal is asserted high, the CNA
detection circuitry is enabled (regardless of the previous state of the
ports) and a pull-down is activated on the RESET terminal so as to
force a reset of the PDI1394P25 internal logic.
The LPS (link power status) terminal works with the C/LKON
terminal to manage the power usage in the node. The LPS signal
from the LLC is used in conjunction with the LCtrl bit (see Table 1
and Table 2) to indicate the active/power status of the LLC. The LPS
signal is also used to reset, disable, and initialize the PHY-LLC
interface (the state of the PHY-LCC interface is controlled solely by
the LPS input regardless of the state of the LCtrl bit).
The LPS input is considered inactive if it remains low for more than
2.6 µs and is considered active otherwise. When the PDI1394P25
detects that LPS is inactive, it will place the PHY-LLC interface into a
low-power reset state in which the CTL and D outputs are held in the
logic zero state and the LREQ input is ignored; however, the
SYSCLK output remains active. If the LPS input remains low for
more than 26 µs, the PHY-LLC interface is put into a low-power
disabled state in which the SYSCLK output is also held inactive. The
PHY-LLC interface is also held in the disabled state during hardware
reset. The PDI1394P25 will continue the necessary repeater
functions required for normal network operation regardless of the
state of the PHY-LLC interface. When the interface is in the reset or
disabled state and LPS is again observed active, the PHY will
initialize the interface and return it to normal operation.
The PHY uses the C/LKON terminal to notify the LLC to power up
and become active. When activated, the C/LKON signal is a square
wave of approximately 163 ns period. The PHY activates the
C/LKON output when the LLC is inactive and a wake-up event
occurs. The LLC is considered inactive when either the LPS input is
inactive, as described above, or the LCtrI bit is cleared to 0. A
wake-up event occurs when a link-on PHY packet addressed to this
node is received, or conditionally when a PHY interrupt occurs. The
PHY deasserts the C/LKON output when the LLC becomes active
(both LPS active and the LCtrl bit set to 1). The PHY also deasserts
EN 290
9.9.2
9.
DVDR980-985 /0X1
IC7103: PDI1394L40
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 291
EN 292
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 293
EN 294
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 295
EN 296
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 297
EN 298
9.9.3
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
IC7203: P89C51RD
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
DESCRIPTION
The P89C51RB2/RC2/RD2 device contains a non-volatile
16kB/32kB/64kB Flash program memory that is both parallel
programmable and serial In-System and In-Application
Programmable. In-System Programming (ISP) allows the user to
download new code while the microcontroller sits in the application.
In-Application Programming (IAP) means that the microcontroller
fetches new program code and reprograms itself while in the
system. This allows for remote programming over a modem link.
A default serial loader (boot loader) program in ROM allows serial
In-System programming of the Flash memory via the UART without
the need for a loader in the Flash code. For In-Application
Programming, the user program erases and reprograms the Flash
memory by use of standard routines contained in ROM.
This device executes one machine cycle in 6 clock cycles, hence
providing twice the speed of a conventional 80C51. An OTP
configuration bit lets the user select conventional 12 clock timing
if desired.
P89C51RB2/P89C51RC2/
P89C51RD2
FEATURES
80C51 Central Processing Unit
On-chip Flash Program Memory with In-System Programming
(ISP) and In-Application Programming (IAP) capability
Boot ROM contains low level Flash programming routines for
downloading via the UART
Can be programmed by the end-user application (IAP)
6 clocks per machine cycle operation (standard)
12 clocks per machine cycle operation (optional)
Speed up to 20 MHz with 6 clock cycles per machine cycle
(40 MHz equivalent performance); up to 33 MHz with 12 clocks
per machine cycle
Fully static operation
RAM expandable externally to 64 kB
This device is a Single-Chip 8-Bit Microcontroller manufactured in
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The instruction set is 100% compatible with
the 80C51 instruction set.
4 level priority interrupt
The device also has four 8-bit I/O ports, three 16-bit timer/event
counters, a multi-source, four-priority-level, nested interrupt structure,
an enhanced UART and on-chip oscillator and timing circuits.
Full-duplex enhanced UART
The added features of the P89C51RB2/RC2/RD2 makes it a
powerful microcontroller for applications that require pulse width
modulation, high-speed I/O and up/down counting capabilities such
as motor control.
7 interrupt sources
Four 8-bit I/O ports
± Framing error detection
± Automatic address recognition
Power control modes
± Clock can be stopped and resumed
± Idle mode
± Power down mode
Programmable clock out
Second DPTR register
Asynchronous port reset
Low EMI (inhibit ALE)
Programmable Counter Array (PCA)
± PWM
± Capture/compare
Circuit-, IC Descriptions and List of Abbreviations
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
DVDR980-985 /0X1
9.
EN 299
P89C51RB2/P89C51RC2/
P89C51RD2
BLOCK DIAGRAM
P0.0±P0.7
P2.0±P2.7
PORT 0
DRIVERS
PORT 2
DRIVERS
VCC
VSS
RAM ADDR
REGISTER
PORT 0
LATCH
RAM
PORT 2
LATCH
FLASH
8
B
REGISTER
STACK
POINTER
ACC
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
BUFFER
ALU
SFRs
TIMERS
PSW
PC
INCREMENTER
P.C.A.
8
16
PSEN
ALE
EAVPP
TIMING
AND
CONTROL
RST
INSTRUCTION
REGISTER
PROGRAM
COUNTER
PD
DPTR'S
MULTIPLE
PORT 1
LATCH
PORT 3
LATCH
PORT 1
DRIVERS
PORT 3
DRIVERS
P1.0±P1.7
P3.0±P3.7
OSCILLATOR
XTAL1
XTAL2
SU01065
EN 300
9.
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
80C51 8-bit Flash microcontroller family
P89C51RB2/P89C51RC2/
P89C51RD2
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
LOGIC SYMBOL
Plastic Leaded Chip Carrier
VCC
6
VSS
XTAL1
7
PORT 0
LCC
17
PORT 1
RST
EA/VPP
PSEN
29
18
PORT 2
ALE/PROG
PORT 3
39
DATA BUS
T2
T2EX
SECONDARY FUNCTIONS
40
ADDRESS AND
XTAL2
RxD
TxD
INT0
INT1
T0
T1
WR
RD
1
ADDRESS BUS
SU01302
PINNING
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function
NIC*
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3
P1.7/CEX4
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
28
Function
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
NIC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
* NO INTERNAL CONNECTION
Function
P2.7/A15
PSEN
ALE/PROG
NIC*
EA/VPP
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VCC
SU00023
Plastic Dual In-Line Package
Plastic Quad Flat Pack
T2/P1.0 1
40 VCC
T2EX/P1.1 2
39 P0.0/AD0
ECI/P1.2 3
38 P0.1/AD1
CEX0/P1.3 4
37 P0.2/AD2
CEX1/P1.4 5
36 P0.3/AD3
CEX2/P1.5 6
35 P0.4/AD4
CEX3/P1.6 7
34 P0.5/AD5
CEX4/P1.7 8
33 P0.6/AD6
TxD/P3.1 11
DUAL
IN-LINE
PACKAGE
31 EA/VPP
30 ALE/PROG
INT0/P3.2 12
29 PSEN
INT1/P3.3 13
28 P2.7/A15
T0/P3.4 14
27 P2.6/A14
T1/P3.5 15
26 P2.5/A13
WR/P3.6 16
25 P2.4/A12
RD/P3.7 17
24 P2.3/A11
XTAL2 18
23 P2.2/A10
XTAL1 19
22 P2.1/A9
VSS 20
21 P2.0/A8
33
LQFP
11
23
12
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function
P1.5/CEX2
P1.6/CEX3
P1.7/CEX4
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
* NO INTERNAL CONNECTION
SU00021
34
1
32 P0.7/AD7
RST 9
RxD/P3.0 10
44
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
22
Function
VSS
NIC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE/PROG
NIC*
EA/VPP
P0.7/AD7
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VCC
NIC*
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3/CEX0
P1.4/CEX1
SU01400
Circuit-, IC Descriptions and List of Abbreviations
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
DVDR980-985 /0X1
9.
EN 301
P89C51RB2/P89C51RC2/
P89C51RD2
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
TYPE
NAME AND FUNCTION
PDIP
PLCC
LQFP
VSS
20
22
16
I
Ground: 0 V reference.
VCC
40
44
38
I
Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
39±32
43±36
37±30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during accesses to external program
and data memory. In this application, it uses strong internal pull-ups when emitting 1s.
1±8
2±9
40±44,
1±3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins
except P1.6 and P1.7 which are open drain. Port 1 pins that have 1s written to them
are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1
pins that are externally pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: IIL).
1
2
40
I/O
2
3
4
5
6
7
8
3
4
5
6
7
8
9
41
42
43
44
1
2
3
I
I
I/O
I/O
I/O
I/O
I/O
P2.0±P2.7
21±28
24±31
18±25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 2 pins that are externally being pulled low will source current
because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2
emits the high-order address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s.
During accesses to external data memory that use 8-bit addresses (MOV @Ri),
port 2 emits the contents of the P2 special function register.
P3.0±P3.7
10±17
11,
13±19
5, 7±13
I/O
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
I
O
I
I
I
I
O
O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 3 pins that are externally being pulled low will source current
because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves
the special features of the 89C51RB2/RC2/RD2, as listed below:
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
RST
9
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal resistor to VSS permits a power-on reset using only
an external capacitor to VCC.
ALE
30
33
27
O
Address Latch Enable: Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted twice
every machine cycle, and can be used for external timing or clocking. Note that one
ALE pulse is skipped during each access to external data memory. ALE can be
disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a
MOVX instruction.
P0.0±0.7
P1.0±P1.7
Alternate functions for 89C51RB2/RC2/RD2 Port 1 include:
T2 (P1.0): Timer/Counter 2 external count input/Clockout (see Programmable
Clock-Out)
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
ECI (P1.2): External Clock Input to the PCA
CEX0 (P1.3): Capture/Compare External I/O for PCA module 0
CEX1 (P1.4): Capture/Compare External I/O for PCA module 1
CEX2 (P1.5): Capture/Compare External I/O for PCA module 2
CEX3 (P1.6): Capture/Compare External I/O for PCA module 3
CEX4 (P1.7): Capture/Compare External I/O for PCA module 4
P2.7 must be a ªIº to program and erase the device.
EN 302
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM
PIN NUMBER
MNEMONIC
TYPE
P89C51RB2/P89C51RC2/
P89C51RD2
NAME AND FUNCTION
PDIP
PLCC
LQFP
PSEN
29
32
26
O
Program Store Enable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
EA/VPP
31
35
29
I
External Access Enable/Programming Supply Voltage: EA must be externally
held low to enable the device to fetch code from external program memory
locations. If EA is held high, the device executes from internal program memory.
The value on the EA pin is latched when RST is released and any subsequent
changes have no effect. This pin also receives the programming supply voltage
(VPP) during Flash programming.
XTAL1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
XTAL2
18
20
14
O
Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
To avoid ªlatch-upº effect at power-on, the voltage on any pin (other than VPP) must not be higher than VCC + 0.5 V or less than VSS ± 0.5 V.
Circuit-, IC Descriptions and List of Abbreviations
9.9.4
DVDR980-985 /0X1
9.
EN 303
IC7303: FPGA/EPLD
0
Spartan and Spartan-XL Families
Field Programmable Gate Arrays
R
DS060 (v1.6) September 19, 2001
0
0
Introduction
Product Specification
•
Spartan™
The
and the Spartan-XL families are a high-volume production FPGA solution that delivers all the key
requirements for ASIC replacement up to 40,000 gates.
These requirements include high performance, on-chip
RAM, core solutions and prices that, in high volume,
approach and in many cases are equivalent to mask programmed ASIC devices.
The Spartan series is the result of more than 14 years of
FPGA design experience and feedback from thousands of
customers. By streamlining the Spartan series feature set,
leveraging advanced process technologies and focusing on
total cost management, the Spartan series delivers the key
features required by ASIC and other high-volume logic
users while avoiding the initial cost, long development
cycles and inherent risk of conventional ASICs. The Spartan and Spartan-XL families in the Spartan series have ten
members, as shown in Table 1.
•
System level features
- Available in both 5V and 3.3V versions
- On-chip SelectRAM™ memory
- Fully PCI compliant
- Full readback capability for program verification
and internal node observability
- Dedicated high-speed carry logic
- Internal 3-state bus capability
- Eight global low-skew clock or signal networks
- IEEE 1149.1-compatible Boundary Scan logic
- Low cost plastic packages available in all densities
- Footprint compatibility in common packages
Fully supported by powerful Xilinx development system
- Foundation Series: Integrated, shrink-wrap
software
- Alliance Series: Dozens of PC and workstation
third party development systems supported
- Fully automatic mapping, placement and routing
Spartan and Spartan-XL Features
Additional Spartan-XL Features
Note: The Spartan series devices described in this data
sheet include the 5V Spartan family and the 3.3V
Spartan-XL family. See the separate data sheet for the 2.5V
Spartan-II family.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
First ASIC replacement FPGA for high-volume
production with on-chip RAM
Density up to 1862 logic cells or 40,000 system gates
Streamlined feature set based on XC4000 architecture
System performance beyond 80 MHz
Broad set of AllianceCORE™ and LogiCORE™
predefined solutions available
Unlimited reprogrammability
Low cost
3.3V supply for low power with 5V tolerant I/Os
Power down input
Higher performance
Faster carry logic
More flexible high-speed clock network
Latch capability in Configurable Logic Blocks
Input fast capture latch
Optional mux or 2-input function generator on outputs
12 mA or 24 mA output drive
5V and 3.3V PCI compliant
Enhanced Boundary Scan
Express Mode configuration
Chip scale packaging
Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays
Logic
Max
System
Gates
Typical
Gate Range
(Logic and RAM)(1)
CLB
Matrix
Total
CLBs
Max.
Total
No. of
Avail. Distributed
Flip-flops User I/O RAM Bits
Device
Cells
XCS05 and XCS05XL
238
5,000
2,000-5,000
10 x 10
100
360
77
XCS10 and XCS10XL
466
10,000
3,000-10,000
14 x 14
196
616
112
6,272
XCS20 and XCS20XL
950
20,000
7,000-20,000
20 x 20
400
1,120
160
12,800
XCS30 and XCS30XL
1368
30,000
10,000-30,000
24 x 24
576
1,536
192
18,432
XCS40 and XCS40XL
1862
40,000
13,000-40,000
28 x 28
784
2,016
224
25,088
3,200
Notes:
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
1
EN 304
9.
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
IOB
IOB
IOB
IOB
IOB
BSCAN
IOB
The devices are customized by loading configuration data
into internal static memory cells. Re-programming is possible an unlimited number of times. The values stored in these
Spartan series FPGAs can be used where hardware must
be adapted to different user applications. FPGAs are ideal
for shortening design and development cycles, and also
offer a cost-effective solution for production rates well
beyond 50,000 systems per month.
IOB
Spartan series FPGAs are implemented with a regular, flexible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources (routing channels), and surrounded by a perimeter of programmable Input/Output
Blocks (IOBs), as seen in Figure 1. They have generous
routing resources to accommodate the most complex interconnect patterns.
memory cells determine the logic functions and interconnections implemented in the FPGA. The FPGA can either
actively read its configuration data from an external serial
PROM (Master Serial mode), or the configuration data can
be written into the FPGA from an external device (Slave
Serial mode).
IOB
General Overview
IOB
OSC
IOB
CLB
CLB
CLB
CLB
IOB
IOB
IOB
IOB
CLB
CLB
CLB
CLB
IOB
IOB
Routing Channels
IOB
IOB
CLB
CLB
CLB
CLB
IOB
IOB
IOB
IOB
CLB
CLB
CLB
CLB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
RDBK
IOB
IOB
START
-UP
VersaRing Routing Channels
DS060_01_081100
Figure 1: Basic FPGA Block Diagram
2
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Product Specification
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 305
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Pin Descriptions
There are three types of pins in the Spartan/XL devices:
•
•
•
Permanently dedicated pins
User I/O pins that can have special functions
Unrestricted user-programmable I/O pins.
Before and during configuration, all outputs not used for the
configuration process are 3-stated with the I/O pull-up resistor network activated. After configuration, if an IOB is
unused it is configured as an input with the I/O pull-up resistor network remaining activated.
Any user I/O can be configured to drive the Global
Set/Reset net GSR or the global three-state net GTS. See
Global Signals: GSR and GTS, page 20 for more information.
Device pins for Spartan/XL devices are described in
Table 18.
Table 18: Pin Descriptions
Pin Name
I/O
During
Config.
I/O After
Config.
Pin Description
Permanently Dedicated Pins
VCC
X
X
Eight or more (depending on package) connections to the nominal +5V supply
voltage (+3.3V for Spartan-XL devices). All must be connected, and each must be
decoupled with a 0.01 –0.1 µF capacitor to Ground.
GND
X
X
Eight or more (depending on package type) connections to Ground. All must be
connected.
CCLK
I or O
I
During configuration, Configuration Clock (CCLK) is an output in Master mode and
is an input in Slave mode. After configuration, CCLK has a weak pull-up resistor
and can be selected as the Readback Clock. There is no CCLK High or Low time
restriction on Spartan/XL devices, except during Readback. See Violating the
Maximum High and Low Time Specification for the Readback Clock, page 39
for an explanation of this exception.
DONE
I/O
O
DONE is a bidirectional signal with an optional internal pull-up resistor. As an
open-drain output, it indicates the completion of the configuration process. As an
input, a Low level on DONE can be configured to delay the global logic initialization
and the enabling of outputs.
The optional pull-up resistor is selected as an option in the program that creates
the configuration bitstream. The resistor is included by default.
PROGRAM
I
I
PROGRAM is an active Low input that forces the FPGA to clear its configuration
memory. It is used to initiate a configuration cycle. When PROGRAM goes High,
the FPGA finishes the current clear cycle and executes another complete clear
cycle, before it goes into a WAIT state and releases INIT.
The PROGRAM pin has a permanent weak pull-up, so it need not be externally
pulled up to VCC.
MODE
(Spartan)
M0, M1
(Spartan-XL)
62
I
X
The Mode input(s) are sampled after INIT goes High to determine the
configuration mode to be used.
During configuration, these pins have a weak pull-up resistor. For the most popular
configuration mode, Slave Serial, the mode pins can be left unconnected. For
Master Serial mode, connect the Mode/M0 pin directly to system ground.
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Product Specification
EN 306
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Table 18: Pin Descriptions (Continued)
Pin Name
I/O
During
Config.
I/O After
Config.
PWRDWN
I
I
Pin Description
PWRDWN is an active Low input that forces the FPGA into the Power Down state
and reduces power consumption. When PWRDWN is Low, the FPGA disables all
I/O and initializes all flip-flops. All inputs are interpreted as Low independent of
their actual level. VCC must be maintained, and the configuration data is
maintained. PWRDWN halts configuration if asserted before or during
configuration, and re-starts configuration when removed. When PWRDWN returns
High, the FPGA becomes operational by first enabling the inputs and flip-flops and
then enabling the outputs. PWRDWN has a default internal pull-up resistor.
User I/O Pins That Can Have Special Functions
TDO
O
O
If boundary scan is used, this pin is the Test Data Output. If boundary scan is not
used, this pin is a 3-state output without a register, after configuration is
completed.
To use this pin, place the library component TDO instead of the usual pad symbol.
An output buffer must still be used.
TDI, TCK,
TMS
I
I/O
or I
(JTAG)
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode
Select inputs respectively. They come directly from the pads, bypassing the IOBs.
These pins can also be used as inputs to the CLB logic after configuration is
completed.
If the BSCAN symbol is not placed in the design, all boundary scan functions are
inhibited once configuration is completed, and these pins become
user-programmable I/O. In this case, they must be called out by special library
elements. To use these pins, place the library components TDI, TCK, and TMS
instead of the usual pad symbols. Input or output buffers must still be used.
HDC
O
I/O
High During Configuration (HDC) is driven High until the I/O go active. It is
available as a control output indicating that configuration is not yet completed.
After configuration, HDC is a user-programmable I/O pin.
LDC
O
I/O
Low During Configuration (LDC) is driven Low until the I/O go active. It is available
as a control output indicating that configuration is not yet completed. After
configuration, LDC is a user-programmable I/O pin.
INIT
I/O
I/O
Before and during configuration, INIT is a bidirectional signal. A 1 kΩ to 10 kΩ
external pull-up resistor is recommended.
As an active Low open-drain output, INIT is held Low during the power stabilization
and internal clearing of the configuration memory. As an active Low input, it can
be used to hold the FPGA in the internal WAIT state before the start of
configuration. Master mode devices stay in a WAIT state an additional 30 to
300 µs after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error
has occurred. After the I/O go active, INIT is a user-programmable I/O pin.
PGCK1 PGCK4
(Spartan)
Weak
Pull-up
I or I/O
Four Primary Global inputs each drive a dedicated internal global net with short
delay and minimal skew. If not used to drive a global buffer, any of these pins is a
user-programmable I/O.
The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad
symbol connected directly to the input of a BUFGP symbol is automatically placed
on one of these pins.
DS060 (v1.6) September 19, 2001
Product Specification
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63
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 307
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Table 18: Pin Descriptions (Continued)
Pin Name
SGCK1 SGCK4
(Spartan)
I/O
During
Config.
I/O After
Config.
Pin Description
Weak
Pull-up
(except
SGCK4
is DOUT)
I or I/O
Weak
Pull-up
(except
GCK6 is
DOUT)
I or I/O
CS1
(Spartan-XL)
I
I/O
During Express configuration, CS1 is used as a serial-enable signal for
daisy-chaining.
D0-D7
(Spartan-XL)
I
I/O
During Express configuration, these eight input pins receive configuration data.
After configuration, they are user-programmable I/O pins.
DIN
I
I/O
During Slave Serial or Master Serial configuration, DIN is the serial configuration
data input receiving data on the rising edge of CCLK. After configuration, DIN is a
user-programmable I/O pin.
DOUT
O
I/O
During Slave Serial or Master Serial configuration, DOUT is the serial
configuration data output that can drive the DIN of daisy-chained slave FPGAs.
DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods
after it was received at the DIN input.
GCK1 GCK8
(Spartan-XL)
Four Secondary Global inputs each drive a dedicated internal global net with short
delay and minimal skew. These internal global nets can also be driven from
internal logic. If not used to drive a global net, any of these pins is a
user-programmable I/O pin.
The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global
Buffers. Any input pad symbol connected directly to the input of a BUFGS symbol
is automatically placed on one of these pins.
Eight Global inputs each drive a dedicated internal global net with short delay and
minimal skew. These internal global nets can also be driven from internal logic. If
not used to drive a global net, any of these pins is a user-programmable I/O pin.
The GCK1-GCK8 pins provide the shortest path to the eight Global Low-Skew
Buffers. Any input pad symbol connected directly to the input of a BUFGLS symbol
is automatically placed on one of these pins.
In Spartan-XL Express mode, DOUT is the status output that can drive the CS1 of
daisy-chained FPGAs, to enable and disable downstream devices.
After configuration, DOUT is a user-programmable I/O pin.
Unrestricted User-Programmable I/O Pins
I/O
64
Weak
Pull-up
I/O
These pins can be configured to be input and/or output after configuration is
completed. Before configuration is completed, these pins have an internal
high-value pull-up resistor network that defines the logic level as High.
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DS060 (v1.6) September 19, 2001
Product Specification
EN 308
9.9.5
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
IC7307; IC7308: CY2071AS
CY2071A
EPROM Programmable Clock Generator
Features
Benefits
Single phase-locked loop architecture
Generates a custom frequency from an external source
EPROM programmability
Easy customization and fast turnaround
Factory-programmable (CY2071A, CY2071AI) or field- Programming support available for all opportunities
programmable (CY2071AF, CY2071AFI) device options
Up to three configurable outputs
Generates three related frequencies from a single device
Low-skew, low-jitter, high-accuracy outputs
Meets critical industry standard timing requirements
Internal loop filter
Alleviates the need for external components
Power management (OE)
Supports low-power applications
Frequency select options
3 outputs with 2 user selectable frequencies
Configurable 5V or 3.3V operation
Supports industry standard design platforms
8-pin 150-mil SOIC package
Industry-standard packaging saves on board space
i
Selector Guide
Part Number
Outputs
Input Frequency Range
CY2071A
3
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
500 kHz–130 MHz (5V)
500 kHz–100 MHz (3.3V)
Output Frequency Range
Factory Programmable
Commercial Temperature
CY2071AI
3
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
500 kHz–100 MHz (5V)
500 kHz–80 MHz (3.3V)
Factory Programmable
Industrial Temperature
CY2071AF
3
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
500 kHz–100 MHz (5V)
500 kHz–80 MHz (3.3V)
Field Programmable
Commercial Temperature
CY2071AFI
3
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
500 kHz–90 MHz (5V)
500 kHz–66.6 MHz (3.3V)
Field Programmable
Industrial Temperature
Logic Block Diagram for CY2071A
XTALIN
REFERENCE
OSCILLATOR
CLKA
EPROMConfigurable
Multiplexer
and Divide
Logic
XTALOUT
PLL
Block
CLKB
CLKC
OE / FS
Pin Configuration
8-pin SOIC
Top View
CLKA
GND
XTALIN
XTALOUT
1
2
3
4
8
7
6
5
OE/FS
VDD
CLKC
CLKB
Specifics
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 309
Pin Summary
Name
Number
Description
CLKA
1
Configurable Clock Output
GND
2
Ground
XTALIN
3
Reference Crystal Input or External Reference Clock Input
XTALOUT
4
Reference Crystal Feedback
CLKB
5
Configurable Clock Output
CLKC
6
Configurable Clock Output
VDD
7
Voltage Supply
OE / FS
8
Output Control Pin, either Output Enable or Frequency Select Input
(Active-HIGH, internal pull-up resistor to VDD)
Notes:
1. For best accuracy, use a parallel-resonant crystal, CL = 17 pF.
2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to an external crystal).
Functional Description
The CY2071A is a general-purpose clock synthesizer designed for use in applications such as modems, disk drives,
CD-ROM drives, video CD players, games, set-top boxes, and
data/telecommunications. The device offers up to three configurable clock outputs in an 8-pin, 150-mil SOIC package and
can operate off either a 3.3V or 5V power supply. The on-chip
reference oscillator is designed for 10-MHz to 25-MHz crystals. Alternatively, an external reference clock of frequency between 1 MHz and 30 MHz can be used.
The CY2071A has one PLL and outputs three factory-EPROM
configurable clocks: CLKA, CLKB, and CLKC. The output
clocks can originate either from the PLL or the reference, or
selected dividers thereof. Additionally, pin 8 can be configured
to be an Output Enable or a Select input.
The CY2071A can replace multiple Metal Can Oscillators
(MCO) in a synchronous system, providing cost and board
space savings to the manufacturer. Hence, these devices are
ideally suited for applications that require multiple, accurate,
and stable clocks synthesized from low-cost generators in
small packages. A hard-disk drive is an example of such an
application. In this case, CLKA drives the PLL in the Read
Controller, while CLKB and CLKC drive the MCU and associated sequencers.
CyClocks™
Software
CyClocks is an easy-to-use software application that allows
you to configure any one of the EPROM-Programmable Clocks
offered by Cypress. You may specify the input frequency, PLL
and output frequencies, and different functional options.
Please note the output frequency ranges in this data sheet
when specifying them in CyClocks to ensure that you stay within the limits. You can download a copy of CyClocks free on the
Cypress Semiconductor website at www.cypress.com.
Consider using the CY2081 for applications that require unrelated output frequencies. Consider using the CY2291,
CY2292, or CY2907 for applications that require more than
three output clocks.
Cypress FTG Programmer
The Cypress Frequency Timing Generator (FTG) Programmer
is a portable programmer designed to custom program our
family of EPROM Field Programmable Clock Devices. The
FTG programmers connect to a PC serial port and allow users
of CyClocks software to quickly and easily program any of the
CY2291F, CY2292F, CY2071AF, and CY2907F devices. The
ordering code for the Cypress FTG Programmer is CY3670.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage................................................–0.5V to +7.0V
DC Input Voltage ..................................... –0.5V to VDD+0.5V
Storage Temperature ................................. –65˚C to +150˚C
Max. Soldering Temperature (10 sec) ..........................260˚C
Junction Temperature ...................................................150˚C
Static Discharge Voltage ........................................... >2000V
(per MIL-STD-883, Method 3015)
EN 310
9.9.6
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
IC7402; IC7403: EDORAM
EDO DRAM
FEATURES
• JEDEC- and industry-standard x16 timing,
functions, pinouts, and packages
• High-performance CMOS silicon-gate process
• Single power supply (+3.3V ±0.3V or 5V ±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR), HIDDEN; optional self refresh (S)
• BYTE WRITE access cycles
• 1,024-cycle refresh (10 row, 10 column addresses)
• Extended Data-Out (EDO) PAGE MODE access
• 5V-tolerant inputs and I/Os on 3.3V devices
OPTIONS
MARKING
• Voltages 1
3.3V
5V
LC
C
• Refresh Addressing
1,024 (1K) rows
E5
• Packages
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
DJ
TG
• Timing
50ns access
60ns access
-5
-6
• Refresh Rates
Standard Refresh (16ms period)
Self Refresh (128ms period)
None
S2
• Operating Temperature Range
Commercial (0oC to +70oC)
Extended (-20oC to +80oC)
None
ET
Part Number Example:
44/50-Pin TSOP
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
VCC
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
VSS
42-Pin SOJ
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
VSS
NOTE: The "#" symbol indicates signal is active LOW.
1 MEG x 16 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC1M16E5DJ-x
MT4LC1M16E5DJ-x S
MT4LC1M16E5TG-x
MT4LC1M16E5TG-x S
MT4C1M16E5DJ-x
MT4C1M16E5TG-x
Vcc REFRESH PACKAGE REFRESH
3.3V
1K
400-SOJ Standard
3.3V
1K
400-SOJ
Self
3.3V
1K
400-TSOP Standard
3.3V
1K
400-TSOP
Self
5V
1K
400-SOJ Standard
5V
1K
400-TSOP Standard
NOTE: “-x” indicates speed grade marking under timing
options.
GENERAL DESCRIPTION
MT4LC1M16E5TG-6
NOTE: 1. The third field distinguishes the low voltage offering: LC designates Vcc = 3.3V and C designates Vcc = 5V.
2. Available only on MT4LC1M16E5 (3.3V)
KEY TIMING PARAMETERS
SPEED
-5
-6
PIN ASSIGNMENT (Top View)
tRC
tRAC
tPC
tAA
tCAC
tCAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
15ns
17ns
8ns
10ns
The 1 Meg x 16 is a randomly accessed, solid-state
memory containing 16,777,216 bits organized in a x16
configuration. The 1 Meg x 16 has both BYTE WRITE
and WORD WRITE access cycles via two CAS# pins
(CASL# and CASH#). These function like a single CAS#
found on other DRAMs in that either CASL# or CASH#
will generate an internal CAS#.
The CAS# function and timing are determined by
the first CAS# (CASL# or CASH#) to transition LOW and
the last CAS# to transition back HIGH. Using only one
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 311
GENERAL DESCRIPTION (continued)
of the two signals results in a BYTE WRITE cycle. CASL#
transitioning LOW selects an access cycle for the lower
byte (DQ0-DQ7), and CASH# transitioning LOW selects an access cycle for the upper byte (DQ8-DQ15).
Each bit is uniquely addressed through the 20 address bits during READ or WRITE cycles. These are
entered 10 bits (A0-A9) at a time. RAS# is used to latch
the first 10 bits and CAS#, the latter 10 bits. The CAS#
function also determines whether the cycle will be a
refresh cycle (RAS# ONLY) or an active cycle (READ,
WRITE or READ-WRITE) once RAS# goes LOW.
The CASL# and CASH# inputs internally generate a
CAS# signal that functions like the single CAS# input
on other DRAMs. The key difference is each CAS# input
(CASL# and CASH#) controls its corresponding eight
DQ inputs during WRITE accesses. CASL# controls
DQ0-DQ7, and CASH# controls DQ8-DQ15. The two
CAS# controls give the 1 Meg x 16 both BYTE READ and
BYTE WRITE cycle capabilities.
RAS#
CASL#/CASH#
ADDR
V IH
V IL
V IH
V IL
V IH
V IL
DQ V IOH
V IOL
ROW
COLUMN (A)
OPEN
COLUMN (B)
VALID DATA (A)
VALID DATA (A)
tOD
V IH
V IL
COLUMN (C)
VALID DATA (B)
tOD
tOES
OE#
A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE or
CAS# (CASL# or CASH#), whichever occurs last. An
EARLY WRITE occurs when WE is taken LOW prior to
either CAS# falling. A LATE WRITE or READ-MODIFYWRITE occurs when WE falls after CAS# (CASL# or
CASH#) was taken LOW. During EARLY WRITE cycles,
the data outputs (Q) will remain High-Z, regardless of
the state of OE#. During LATE WRITE or READMODIFY-WRITE cycles, OE# must be taken HIGH to
disable the data outputs prior to applying input data.
If a LATE WRITE or READ-MODIFY-WRITE is attempted
while keeping OE# LOW, no WRITE will occur, and the
data outputs will drive read data from the accessed
location.
The 16 data inputs and 16 data outputs are routed
through 16 pins using common I/O. Pin direction is
controlled by OE# and WE#.
The 1 Meg x 16 DRAM must be refreshed periodically in order to retain stored data.
COLUMN (D)
VALID DATA (C)
VALID DATA (D)
tOD
tOEHC
tOE
tOEP
The DQs go back to
Low-Z if tOES is met.
The DQs remain High-Z
until the next CAS# cycle
if tOEHC is met.
The DQs remain High-Z
until the next CAS# cycle
if tOEP is met.
DON'T CARE
UNDEFINED
Figure 1
OE# Control of DQs
EN 312
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
FUNCTIONAL BLOCK DIAGRAM
WE#
CASL#
DATA-IN BUFFER
CAS#
CASH#
DQ0
16
NO. 2 CLOCK
GENERATOR
10
DQ15
DATA-OUT
BUFFER
COLUMNADDRESS
BUFFER
10
COLUMN
DECODER
OE#
16
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
16
SENSE AMPLIFIERS
I/O GATING
REFRESH
COUNTER
1,024 x 16
ROWADDRESS
BUFFERS (10)
NO. 1 CLOCK
GENERATOR
10
ROW
DECODER
10
10
RAS#
1,024
REFRESH
CONTROLLER
1,024
1,024 x 1,024 x 16
MEMORY
ARRAY
VDD
VSS
Circuit-, IC Descriptions and List of Abbreviations
9.9.7
IC7404: NW700
DVDR980-985 /0X1
9.
EN 313
EN 314
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
9.9.8
IC7506: UDA1334ATS
DVDR980-985 /0X1
9.
EN 315
EN 316
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 317
EN 318
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 319
EN 320
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
Circuit-, IC Descriptions and List of Abbreviations
DVDR980-985 /0X1
9.
EN 321
EN 322
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
9.10 List of Abbreviations
Digital Board
+12V
+12V Power Supply
+2V5_FLI
+2V5 Power Supply for FLI
+2V5_PLL
+2V5 Power Supply for PLL
+3V3
+3V3 Power Supply
+3V3_ANA
+3V3 Power Supply Analogue
+3V3_DD
+3V3 Power Supply Digital
+3V3_FLI
+3V3 Power Supply for FLI
+5V
+5V Power Supply
+5V_BUFFER
+5V Power Supply for Video Filters
5508_HS
Horizontal Synchronisation from Host Decoder to Progressive
Scan
5508_ODD_EVEN
Odd - Even control from Host Decoder to Progressive Scan
-5V
-5V Power Supply
-5V_BUFFER
-5V Power Supply for Video Filters
A_EMPRESS(13:0)
EMPRESS address output to SDRAM
ACC_ACLK_OSC
Audio Clock PLL output sync with incoming video for record
ACC_ACLK_PLL
Audio Clock PLL output for play back
ACLK_EMP
EMPRESS audio clock output
AD_ACLK
Audio Decoder Clock
AD_BCLK
Audio Decoder I2S bit clock
AD_DATAO
Audio Decoder Output data (PCM)
AD_SPDIF33
Audio digital output to the analog board
AD_WCLK
Audio Decoder I2S word clock
AE_ACLK
Audio Encoder Clock
AE_ACLK_OEN
Audio Encoder Clock Output Enable
AE_BCLK
Audio Encoder I2S bit clock
AE_BCLK_DV
Audio Encoder I2S bit clock to DVIO
AE_BCLK_VSM
Audio Encoder I2S bit clock to VSM
AE_DATAI
Audio Encoder Input data (PCM)
AE_DATAI_DV
Audio Encoder Input data (PCM) from DVIO
AE_DATAO
Audio Encoder Output data (PCM)
AE_WCLK
Audio Encoder I2S word clock
AE_WCLK_DV
Audio Encoder I2S word clock to DVIO
AE_WCLK_VSM
Audio Encoder I2S word clock to VSM
ANA_WE
Analogue write enable
ANA_WE_LV
Analogue write enable Low Voltage
B_IN_VIP
Video blue input to Video Input Processor
B_OUT
Video blue output from Host Decoder
B_OUT_B
Filtered blue video output
BA
Bank Address
BCLK_CTL_SERVICE
Bitclock control Service Interface
BE_BCLK
Basic Engine I2S bit clock
BE_BCLK_VSM
Basic Engine I2S bit clock to VSM
BE_CPR
Basic Engine Control Processor ready to accept data
BE_DATA_RD
Basic Engine Data read
BE_DATA_WR
Basic Engine Data write
BE_FAN
Basic Engine FAN
BE_FLAG
Basic Engine error flag
BE_IRQN
Basic Engine interrupt request
BE_LOADN
Basic Engine LOAD(LOW active)
BE_RXD
Basic Engine S2B received data
BE_SUR
Basic Engine servo unit ready to accept data (S2B)
BE_SYNC
Basic Engine sector/abs time sync
BE_TXD
Basic Engine S2B transmitted data
BE_V4
Basic Engine versatile input pin
BE_WCLK
Basic Engine I2S word clock
C_IN
Video Chrominance input
C_IN_VIP
Chrominance input to Video Input Processor
C_OUT
Chrominance output from Host Decoder
C_OUT_B
Filtered Chrominance output
CAS
Column Address strobe
CB_OUT(9:0)
Chrominance Blue out
CLK4
SDRAM clock
CPUINT0
Control processor unit interrupt
CPUINT1
Control processor unit interrupt
CR_OUT(9:0)
Chrominance Red out
CTS1P
Clear to send (Service Interface)
CVBS_OUT
Composite video output out of the Host Decoder
CVBS_OUT_B
Filtered Composite video output
CVBS_OUT_B_VIP
Composite video output to Video Input Processor(digital board
video loop)
CVBS_Y_IN
Composite video/Luminance input
CVBS_Y_IN_A
Composite video/Luminance input to Video Input Processor
CVBS_Y_IN_B
Composite video/Luminance input to Video Input Processor
Circuit-, IC Descriptions and List of Abbreviations
CVBS_Y_IN_C
Composite video/Luminance input to Video Input Processor
D_ADDR(10:0)
Address bus
D_DATA(29:0)
Data bus
D_EMPRESS(15:0)
SDRAM data input/output of EMPRESS
D_PAR_D(7:0)
Front-end parallel interface data (record)
D_PAR_DVALID
Front-end parallel interface data valid
D_PAR_REQ
Front-end parallel interface request
D_PAR_STR
Front-end parallel interface strobe
D_PAR_SYNC
Front-end parallel interface sync
DV_IN_CLK
Digital Video in clock from DVIO board
DV_IN_DATA(7:0)
Digital Video in data bus from DVIO board
DV_IN_HS
Digital Video in horizontal synchronisation from DVIO board
DV_IN_VS
Digital Video in vertical synchronisation from DVIO board
EMI_A(21:1)
External Memory Interface Address Bus(Host Decoder)
EMI_BE0N
External Memory Interface Lower byte enable(Host Decoder)
EMI_BE1N
External Memory Interface Upper byte enable(Host Decoder)
EMI_CAS0N
External Memory Interface SDRAM column address
strobe(Host Decoder)
EMI_CE1N
External Memory Interface VSM Lower bank enable
EMI_CE2N
External Memory Interface VSM Higher bank enable
EMI_CE3N
External Memory Interface flash IC's enable
EMI_D(15:0)
External Memory Interface Data Bus(Host Decoder)
EMI_PROCCLK
External Memory Interface Processor Clock(Host Decoder)
EMI_RWN
External Memory Interface Read/Write control signal(Host
Decoder)
EMI_WAIT
External Memory Interface Wait state request(Host Decoder)
EMPRESS_BOOT
EMPRESS BOOT select input
EMPRESS_IRQN
EMPRESS Interrupt request output
FLASH_OEN
FLASH output enable control signal
G_IN_VIP
Video green input to Video Input Processor
G_OUT
Video green output from Host Decoder
G_OUT_B
Filtered green video output from Host Decoder
GNDD
Digital Ground
HD_M_AD(13:0)
Host Decoder SDRAM address bus
HD_M_CASN
Host Decoder SDRAM column address strobe
HD_M_CLK
Host Decoder SDRAM clock
HD_M_CS0N
Host Decoder SDRAM chip select
HD_M_DQ(15:0)
Host Decoder SDRAM data bus
HD_M_DQML
DVDR980-985 /0X1
9.
EN 323
Host Decoder SDRAM data mask enable(Lower)
HD_M_DQMU
Host Decoder SDRAM data mask enable(Upper)
HD_M_RASN
Host Decoder SDRAM row address strobe
HD_M_WEN
Host Decoder SDRAM write enable
HSOUT
Horizontal synchronisation OUT
ION
Inverted ON: Enable the power supply for the digital board
when LOW
IRESET_DIG
Initialisation of the digital board, HIGH when power ON
JTAG3_TCK
JTAG Test Clock
JTAG3_TD_VIP_TO_VE
JTAG Transmitted Data Video Input Processor to Video
Encoder
JTAG3_TD_VSM_TO_VIP
JTAG Transmitted Data Versatile Stream Manager to Video
Input Processor
JTAG3_TMS
JTAG Test Mode Select
JTAG3_TRSTN
JTAG Test part ResetN
LOAD_DVN
LOAD Digital Video(LOW active)
MUTEN
Mute enable
MUTEN_LV
Mute enable Low Voltage
P_SCAN_YUV(7:0)
Progressive Scan digital video bus
R_IN_VIP
Video Red input to Video Input Processor
R_OUT
Video Red output from Host Decoder
R_OUT_B
Filtered Red Video output from Host Decoder
RAS
Row Address Strobe
RESETN
Reset Host Decoder
RESETN_BE
System reset basic engine (buffered)
RESETN_DVIO
System reset Digital Video Input Output (buffered)
RESETN_VE
System reset Video Encoder
ROMH_CEN
Flash 2 chip enable
ROML_CEN
Flash 1 chip enable
RSTN_BE
Reset control of basic engine
RSTN_DVIO
Reset control of DVIO
RTS1P
Ready To Send data to service serial interface
RX1P
Receive data from service serial interface
SCL
I2C bus clock
SD_CASN
SDRAM Column Address strobe output (active LOW)
SD_CLK
SDRAM clock output
SD_CLKE
SDRAM clock enable output
SD_CSN
SDRAM
SD_DQM(1:0)
SDRAM data mask enable output
SD_RASN
EN 324
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
SDRAM row address strobe output
SD_WEN
SDRAM write enable output
SDA
I2C bus data
SEL_ACLK1
Select audio clock(playback)
SM_CS3N
SRAM chip select
SM_LBN
SRAM lower bank
SM_OEN
SRAM output enable
SM_UBN
SRAM upper bank
SM_WEN
SRAM write enable
SMA(17:0)
SRAM address output
SMD(15:0)
SRAM data input/output
SYSCLK_EMPRESS
System clock EMPRESS
SYSCLK_PROGSCAN
System clock Progressive Scan
SYSCLK_VSM_5508
System clock VSM and Host decoder
TX1P
Transmit data to service serial interface
U_IN
Video U input
U_IN_VIP
Video U input to Video Input Processor
V_IN
Video V input
V_IN_VIP
Video V input to Video Input Processor
VCC3_CLK_BUF
Power supply 3V3 clock buffer
VCC3_VSM
Power supply 3V3 Versatile Stream Manager
VCC3_VSM_MEM
Power supply 3V3 Versatile Stream Manager Memory
VCC5_4046
Power supply 5V to PLL IC
VDD_125
Power supply 5V to buffer 7202
VDD_CORE
Sti5508 Core supply voltage 2.5V
VDD_EMP
Empress supply voltage 3.3V
VDD_EMP_CORE
Empress Core supply voltage 2.5V
VDD_FLASH_H
Flash 7301 supply voltage
VDD_FLASH_L
Flash 7302 supply voltage
VDD_LVC32
Power supply LVC32
VDD_PCM
Power supply Audio decoder of Sti5508
VDD_PLL
Power supply PLL audio decoder of Sti5508
VDD_RGB
Power supply video encoder of Sti5508
VDD_STI
Power supply of Sti5508
VDD_YCC
Power supply video encoder of Sti5508
VDD5_MK2703
Power supply MK2703
VDD5_OSC
Power supply Oscillator
VDDA1A_7118
Power supply for analog input of VIP
VDDA2A_7118
Power supply for analog input of VIP
VDDA3A_7118
Power supply for analog input of VIP
VDDA4A_7118
Power supply for analog input of VIP
VDDE_7118
Power supply digital for peripheral cells of VIP
VDDI_7118
Power supply digital for core of VIP
VDDX_7118
Power supply for crystal oscillator of VIP
VE_DATA(7:0)
Video Encoder data Bus
VE_DSN
Video Encoder Data Strobe
VE_DTACKN
Video Encoder Data Transfer acknowledge
VIP_ERROR
Video Input Processor error
VIP_FB
Video Input Processor Fast Blanking
VIP_FID_FF
Video Input Processor field indentifier to Flip Flop
VIP_HS
Video Input Processor horizontal synchronisation
VIP_ICLK
Video Input Processor input Clock
VIP_IDQ
Video Input Processor output data qualifier
VIP_IGP1
Video Input Processor input general purpose 1
VIP_INT
Video Input Processor interrupt
VIP_RTS1
Video Input Processor ready to send
VIP_VS
Video Input Processor vertical synchronisation
VIP_YUV(7:0)
Video Input Processor digital video(CCIR 656)
VS_IN
Vertical synchronisation IN
VSM_M_A(13:0)
Versatile Stream Manager SDRAM address bus
VSM_M_CASN
Versatile Stream Manager SDRAM column address strobe
VSM_M_CLKEN
Versatile Stream Manager SDRAM clock enable
VSM_M_CLKOUT
Versatile Stream Manager SDRAM clock out
VSM_M_D(15:0)
Versatile Stream Manager SDRAM data bus
VSM_M_LDQM
Versatile Stream Manager SDRAM lower data mask enable
VSM_M_RASN
Versatile Stream Manager SDRAM row address strobe
VSM_M_UDQM
Versatile Stream Manager SDRAM upper data mask enable
VSM_M_WEN
Versatile Stream Manager SDRAM write enable
VSM_UART1_CTSN
Versatile Stream Manager UART1 clear to send to analog
board (UART1 is gateway to analog board)
VSM_UART1_RTSN
Versatile Stream Manager UART2 clear to send to DVIO board
(UART2 is gateway to DIVIO board)
VSM_UART1_RX
Versatile Stream Manager UART1 ready to send to analog
board
VSM_UART1_TX
Versatile Stream Manager UART2 ready to send to DVIO
board
VSM_UART2_CTSN
Versatile Stream Manager UART1 received data to analog
board
Circuit-, IC Descriptions and List of Abbreviations
VSM_UART2_RTSN
Versatile Stream Manager UART2 received data to DVIO
board
VSM_UART2_RX
Versatile Stream Manager UART1 transmitted data to analog
board
VSM_UART2_TX
Versatile Stream Manager UART2 transmitted data to DVIO
board
VSOUT
Vertical synchronisation OUT
WE
Write Enable
Y_IN
Luminance input from analog board
Y_OUT
Luminance output from Host Decoder
Y_OUT_B
Filtered luminance output
YY_OUT(9:0)
Luminance output from FLI
Divio Board
+35V_DV_EDO
+3V3 Power supply EDO Bus IC7404
+3V3
+3V3 Power supply
+3V3_DLY
+3V3 Power supply for IC7500
+3V3_DV
+3V3 Power supply for IC7404
+3V3_FPGA
+3V3 Internal Power supply for IC7303
+3V3_FPGA_CONF
+3V3 Power supply for IC 7300
+3V3_IEEE_A
+3V3 Analogue Power supply for PHY IC 7101
+3V3_IEEE_D
+3V3 Digital Power supply for PHY IC 7101
+3V3_IEEE_PLL
+3V3 PLL Power supply for PHY IC 7101
+3V3_LINK
+3V3 Power supply IC7103
+3V3_PLL
+3V3 Power supply IC7307 & IC7308
+3V3_SRAM
+3V3 Power supply IC7301, IC7302, IC7305 & IC7306
+5V
+5V Power supply
+5V_PROC
+5V Power supply IC7200, IC7201, IC7203 & IC7208
+VCC_DV_RAM
+3V3 Power supply for DV_RAM (IC7400--> IC7404)
1394_RSTN
Reset of LINK IC (7103) and PHY IC (7101)
A(0:8)
Address lines
AUD_BCLK
Audio Bit Clock
AUD_MUTE
Audio Mute
AUD_SDI
Audio Serial Data Input
AUD_SDO_CON
Audio Serial Data Output to buffer IC 7505
AUD_SDO_DAC
Audio Serial Data Output to DAC IC 7506
AUD_WS_701
Audio Word Select to DV CODEC IC 7404
AUD_WS_OUT
Audio Word Select to buffer IC 7505
BUFENN_AUD
Buffer Enable Audio
BUFENN_VID
Buffer Enable Video
CCLK
DVDR980-985 /0X1
9.
EN 325
Configuration Clock
CLK27M
27MHz Clock
CLK27M_CON
27MHz Clock to Digital Board
CLK27M_DV
27MHz Clock Digital Video Codec
CLK27M_OSC
27MHz Clock IC7304
CLOCKGENAUD
Clock generator Audio
CLOCKGENVID
Clock generator Video
CTSN
Clear to Send
DATA
Data from config ROM
DONE
Indication of the completion of the configuration process
DOUT
Serial configuration data output
DV_ASN
DVCODEC Address Strobe
DV_DRQN
DVCODEC Data Request Interrupt
DV_DSLN
DVCODEC Data Strobe Lower 8 bits
DV_DSUN
DVCODEC Data Strobe Upper 8 Bits
DV_DTACKN
DVCODEC Data Transfer Acknowledge
DV_ERRN
DVCODEC Error Interrupt
DV_HS_IN
DVCODEC Horizontal synchronisation In
DV_HS_OUT
DVCODEC Horizontal synchronisation Out
DV_LCN
DVCODEC Last Code Interrupt
DV_PDN
DVCODEC Power Down
DV_RSTN
DVCODEC System Reset for NW701
DV_RWN
DVCODEC Read/Write control signal
DV_VS
DVCODEC Vertical synchronisation
FIFOA_A(0:15)
FIFO buffer A Address bus
FIFOA_OEN
FIFO buffer A Output enable
FIFOA_WEN
FIFO buffer A Write enable
HAD(0:7)
Host Address/Data bus for register settings of IC7404
INITN
Initiate Configuration
IO(0:30)
Data bus of IC7404
ISPN
In System Program Line (used for programming IC7203)
LCASN
Lower Column Address strobe for IC7404 DRAMS
LINK_AVCLK
LINK IC Audio/Video Interface Clock
LINK_AVFSYNC
LINK IC Audio/Video frame sync
LINK_AVREADY
LINK IC Audio/Video data ready to send
LINK_AVSYNC
LINK IC Audio/Video packet sync
LINK_AVVALID
LINK IC Audio/Video data valid
LINK_CSN
LINK IC chip select
EN 326
9.
DVDR980-985 /0X1
Circuit-, IC Descriptions and List of Abbreviations
LINK_INTN
LINK IC interrupt
LINKFIFO_DQ(0:7)
Audio Video data interface
PA(0:15)
SRAM processor address
PAD(0:7)
SRAM processor data
PALE
Processor Address Latch Enable
PHY_CNA
PHY 1394 cable not active
PHY_LPS
LINK IC power status
PINT0N
Processor interrupt 0
PINT1N
Processor interrupt 1
PRDN
Processor read
PROGRAMN
Low active input to initiate a configuration cycle
PRSTN
Processor reset
PWRN
Processor write
RASN
Row address strobe
RESETN
DVIO board reset
RTSN
System Reset
RXD
Receive Data
SRAMCE0N
SRAM processor chip enable 0
SRAMRDN
SRAM processor output enable
TCK
Boundary scan Test Clock
TDI
Boundary scan Test Data Input
TDO
Boundary scan Test Data Output
TDO_CONF
Boundary scan Test Data Output from IC 7309
TMS
Boundary scan Test Mode Select
TXD
Transmitted Data
UCASN
Upper column address strobe
WEN
Write Enable control signal to SRAM
YUV(0:7)
Digital Video
Spare Parts List
DVDR980-985 /0X1
10.
EN 327
10. Spare Parts List
Mechanical DVDR980 /001 /021
Various
0060
0065
0081
0081
0151
0191
0197
0198
0199
0251
0252
0253
0254
0309
0370
1001
1002
1003
8001
8002
8003
8004
3104 127 13280 CONNECTOR FRONT
ASSY (EU)
3104 127 13450 TRAY FRONT ASSY
COMPLETE
VAE8010/02
VAE8015/01
3104 127 13320 COVER ASSY
3104 124 07455 FILTER AIR INLED
BOTTOM
3104 123 30002 DUST FILTER
3104 124 07733 FILTER AIR INLET COVER
3104 128 93031 DC BRUSHLESS FAN
3104 127 10740 FOOT SILVER ASSY
3104 127 10740 FOOT SILVER ASSY
3104 127 10740 FOOT SILVER ASSY
3104 127 10740 FOOT SILVER ASSY
3104 125 24250 USER MANUAL DVDR980/
EUR
9307 002 60006 DVDRW/006 PHILIPS DISC
EUROPE
3104 128 07750 DVDR DIG. BOARD 1.5
EMPRESS/EU
3122 427 22711 PSU DVDR1000-2 EURO
50PS203
3103 608 50290 DVDR ANALOG BOARD
EUR GEN 1.5
3104 157 11641 CWAS FLEX DVD 22 70 32S
3104 157 11641 CWAS FLEX DVD 22 70 32S
3104 157 11790 CWAS SPLIT FLEX 30 100
32S
3104 157 11531 CWAS FLEX DVD 10 110
32S
Mechanical DVDR980 /051
Various
0060
0065
0081
0081
0151
0191
0197
0198
0199
0251
0252
0253
0254
0309
0370
1001
1002
1003
8001
8002
8003
8004
3104 127 13420 CONNECTOR FRONT
ASSY (UK)
3104 127 13450 TRAY FRONT ASSY
COMPLETE
VAE8010/02
VAE8015/01
3104 127 13320 COVER ASSY
3104 124 07455 FILTER AIR INLED
BOTTOM
3104 123 30002 DUST FILTER
3104 124 07733 FILTER AIR INLET COVER
3104 128 93031 DC BRUSHLESS FAN
3104 127 10740 FOOT SILVER ASSY
3104 127 10740 FOOT SILVER ASSY
3104 127 10740 FOOT SILVER ASSY
3104 127 10740 FOOT SILVER ASSY
3104 125 24270 USER MANUAL DVDR980
UK
9307 002 60006 DVDRW/006 PHILIPS DISC
EUROPE
3104 128 07750 DVDR DIG. BOARD 1.5
EMPRESS/EU
3122 427 22711 PSU DVDR1000-2 EURO
50PS203
3103 608 50290 DVDR ANALOG BOARD
EUR GEN 1.5
3104 157 11641 CWAS FLEX DVD 22 70 32S
3104 157 11641 CWAS FLEX DVD 22 70 32S
3104 157 11790 CWAS SPLIT FLEX 30 100
32S
3104 157 11531 CWAS FLEX DVD 10 110
32S
Mechanical DVD985 /001 /021
Various
0060
0065
0081
0151
0191
3104 127 13600 CONNECTOR FRONT
ASSY 985/EUR
3104 127 13450 TRAY FRONT ASSY
COMPLETE
VAE8015/01
3104 127 13320 COVER ASSY
3104 124 07455 FILTER AIR INLED
BOTTOM
0197
0198
0199
0251
0252
0253
0254
0309
3104 123 30002
3104 124 07733
3104 128 93031
3104 127 10740
3104 127 10740
3104 127 10740
3104 127 10740
4822 736 16493
0370
9307 002 60006
1001 3104 128 07750
1002 3122 427 22711
1003 3103 608 50290
1005
3104 128 07900
8001
8002
8003
3104 157 11641
3104 157 11641
3104 157 11790
8004
3104 157 11531
8013
8015
3104 128 92921
3104 157 12191
DUST FILTER
FILTER AIR INLET COVER
DC BRUSHLESS FAN
FOOT SILVER ASSY
FOOT SILVER ASSY
FOOT SILVER ASSY
FOOT SILVER ASSY
EN-FR-ES-BR.PORTTRAD.CHIN
DVDRW/006 PHILIPS DISC
EUROPE
DVDR DIG. BOARD 1.5
EMPRESS/EU
PSU DVDR1000-2 EURO
50PS203
DVDR ANALOG BOARD
EUR GEN 1.5
PB DVDR1000 DVIO
GEN.1.5 ASSY
CWAS FLEX DVD 22 70 32S
CWAS FLEX DVD 22 70 32S
CWAS SPLIT FLEX 30 100
32S
CWAS FLEX DVD 10 110
32S
CABLE IEEE-1394 4P AMP
CWAS FLEX DVDR 7 360
32S
Accessorieskit DVDR980 /001 /021
0005
0011
0012
0013
0014
0015
1001
3139 244 00761 LIGHT GUIDE DVD STEP 2K
3104 127 13240 BUTTON STANDBY ASSY
3104 127 13250 BUTTON PLAY/STOP/
RECORD ASSY
3104 127 13260 BUTTON OPENCLOSE/
RECVOLUM ASSY
3104 127 13270 BUTTON DISPLAY ASSY
3104 127 13530 IR LENS ASSY
3104 128 08270 DISPLAYPANEL 4330 ASSY
DVDR980
Front assy DVD985 /001 /021
Various
0001
0002
0003
0004
0005
0011
0012
3104 127 13580
3104 127 13220
3104 127 13230
3104 124 08470
3139 244 00761
3104 127 13240
3104 127 13250
0013
3104 127 13260
0014
0015
1001
3104 127 13270
3104 127 13530
3104 128 08270
1006
3104 128 07610
FRONT ASSY
SIDE PLATE LEFT ASSY
SIDE PLATE RIGHT ASSY
WINDOW
LIGHT GUIDE DVD STEP 2K
BUTTON STANDBY ASSY
BUTTON PLAY/STOP/
RECORD ASSY
BUTTON OPENCLOSE/
RECVOLUM ASSY
BUTTON DISPLAY ASSY
IR LENS ASSY
DISPLAYPANEL 4330 ASSY
DVDR980
PCB ASSY 4319 DVIOFRONT
Various
0318
0320
0321
0322
0323
0324
0370
0371
3128 147 13670 RC2056/01 IRT PROD ASSY
4822 321 22611
3104 128 92490 VIDEO CORD SET GOLD
PLATED
2422 070 98133 MAINSCORD EUR 1M5 BK
B
4822 321 61847 SCART
3111 170 21592 CORDON ANT. L.1,50M
3104 128 93041 S-VHS CABLE 1.5M
9307 002 60006 DVDRW/006 PHILIPS DISC
EUROPE
Display PWB
Various
1140
1150
1153
1156
1159
1160
1162
1163
Accessories DVDR980 /051
1167
1168
1169
Various
1170
0318 3128 147 13670 RC2056/01 IRT PROD ASSY 1171
0320 4822 321 22611
1174
0321 3104 128 92490 VIDEO CORD SET GOLD
PLATED
0322 4622 001 60590 CORDSET UK (WITH COIL)
0323 4822 321 61847 SCART
2140
0324 3111 170 21592 CORDON ANT. L.1,50M
2150
0370 3104 128 93041 S-VHS CABLE 1.5M
2151
0371 9307 002 60006 DVDRW/006 PHILIPS DISC
2152
EUROPE
2154
2155
2156
Accessories DVDR985 /051
2157
2158
2159
Various
2160
0318 3128 147 13670 RC2056/01 IRT PROD ASSY 2161
0320 4822 321 22611
2165
0321 3104 128 92490 VIDEO CORD SET GOLD
2167
PLATED
2168
0322 4622 001 60590 CORDSET UK (WITH COIL) 2169
0323 4822 321 61847 SCART
2170
0324 3111 170 21592 CORDON ANT. L.1,50M
2171
0370 3104 128 93041 S-VHS CABLE 1.5M
2173
0371 9307 002 60006 DVDRW/006 PHILIPS DISC 2174
EUROPE
2175
2177
2179
2180
Front complete
3104 127 13470
3104 127 13220
3104 127 13230
3104 124 08470
4822 124 11946
4822 124 80231
4822 126 14305
4822 121 43526
4822 124 40849
4822 126 14305
2238 586 59812
5322 126 11583
4822 126 14305
2238 586 59812
4822 126 14305
4822 126 14305
5322 126 11583
4822 126 13881
4822 122 31765
5322 126 11583
5322 126 11583
4822 126 13879
5322 126 11583
4822 126 14305
3198 017 41050
5322 126 11583
5322 126 11583
4822 126 14305
22µF 20% 16V
47µF 20% 16V
100nF 10% 16V 0603
47nF 5% 250V
330µF 20% 16V
100nF 10% 16V 0603
0603 50V 100NP80M
10nF 10% 50V 0603
100nF 10% 16V 0603
0603 50V 100NP80M
100nF 10% 16V 0603
100nF 10% 16V 0603
10nF 10% 50V 0603
470pF 5% 50V
100pF 2% 63V 1206
10nF 10% 50V 0603
10nF 10% 50V 0603
220nF 20% 16V
10nF 10% 50V 0603
100nF 10% 16V 0603
0603 10V 1µF COL R
10nF 10% 50V 0603
10nF 10% 50V 0603
100nF 10% 16V 0603
4822 117 12063
4822 051 30472
4822 051 30472
4822 051 30103
NTC DC 5W 10k 5%
4k7 5% 0.062W
4k7 5% 0.062W
10k 5% 0.062W
Various
0001
0002
0003
0004
4822 276 13732 SWITCH TACT PUSH
2422 086 10947 PROT DEV 65V 250MA PSC
A
5322 242 73686 CST12,00MTW-TF01
2422 527 00513 BUZZER PIEZO CB13PA-X5
4822 276 13732 SWITCH TACT PUSH
4822 276 13732 SWITCH TACT PUSH
4822 276 13732 SWITCH TACT PUSH
4822 276 13732 SWITCH TACT PUSH
4822 276 13732 SWITCH TACT PUSH
4822 276 13732 SWITCH TACT PUSH
4822 276 13732 SWITCH TACT PUSH
4822 276 13732 SWITCH TACT PUSH
4822 276 13732 SWITCH TACT PUSH
4822 276 13732 SWITCH TACT PUSH
FRONT ASSY
SIDE PLATE LEFT ASSY
SIDE PLATE RIGHT ASSY
WINDOW
3135
3136
3137
3138
EN 328
10.
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
4822 051 30391
4822 051 30221
4822 051 30472
4822 117 12925
4822 051 30103
4822 051 30391
4822 051 30103
4822 051 30103
4822 051 30103
4822 051 30222
4822 051 30472
4822 051 30562
3151
3152
3153
4822 051 30102
4822 116 52257
2322 704 65608
3154
3155
3156
3157
3158
3159
4822 050 21003
4822 051 30222
4822 050 21003
4822 116 83884
4822 051 30223
4822 051 30562
3160
2322 704 65608
3161
3162
3163
3164
3165
3166
3167
3168
3169
3171
3172
3173
3174
3177
3178
3180
3182
3183
3186
3187
3188
3189
3190
3192
3193
3194
3197
3999
4822 051 30683
4822 051 30683
4822 051 30103
4822 050 21003
4822 051 30222
4822 116 83876
4822 116 83876
4822 116 52175
4822 051 30103
4822 051 30222
4822 051 30472
4822 051 30103
4822 051 30475
4822 051 30102
4822 051 30222
4822 051 30103
4822 051 30152
4822 051 30222
4822 051 30102
4822 051 30222
4822 051 30472
4822 051 30103
4822 117 12925
4822 051 30102
4822 051 30103
4822 051 30222
4822 051 30472
4822 117 12842
Spare Parts List
DVDR980-985 /0X1
390Ω 5% 0.062W
220Ω 5% 0.062W
4k7 5% 0.062W
47k 1% 0.063W 0603
10k 5% 0.062W
390Ω 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
2k2 5% 0.062W
4k7 5% 0.062W
5k6 5% 0.063W 0603 RC21
RST SM
1k 5% 0.062W
22k 5% 0.5W
RST SM 603 RC22H 5Ω6
PM1
10k 1% 0.6W
2k2 5% 0.062W
10k 1% 0.6W
47k 5% 0.5W
22k 5% 0.062W
5k6 5% 0.063W 0603 RC21
RST SM
RST SM 603 RC22H 5Ω6
PM1
68k 5% 0.062W
68k 5% 0.062W
10k 5% 0.062W
10k 1% 0.6W
2k2 5% 0.062W
270Ω 5% 0.5W
270Ω 5% 0.5W
100Ω 5% 0.5W
10k 5% 0.062W
2k2 5% 0.062W
4k7 5% 0.062W
10k 5% 0.062W
4M7 5% 0.062W
1k 5% 0.062W
2k2 5% 0.062W
10k 5% 0.062W
1k5 5% 0.062W
2k2 5% 0.062W
1k 5% 0.062W
2k2 5% 0.062W
4k7 5% 0.062W
10k 5% 0.062W
47k 1% 0.063W 0603
1k 5% 0.062W
10k 5% 0.062W
2k2 5% 0.062W
4k7 5% 0.062W
6170
6171
6172
6173
6174
6175
6176
6177
6178
6179
6180
6181
6182
6183
6184
6185
6186
6187
6188
6189
6190
6191
6192
6193
6194
6195
6196
6197
6198
7140
7141
7142
7143
7144
7145
7150
7151
7152
7153
7155
5150
5151
5153
4822 157 51462 10µH 10% 4X9.8MM
LAL04T100K
4822 157 51462 10µH 10% 4X9.8MM
LAL04T100K
2422 531 02423 TRANSFORMER HEATER
6140
6150
6151
6152
6154
6155
6156
6157
6158
6159
6160
6161
6164
6165
6166
6167
6168
6169
7156
7157
7160
7164
7165
7166
9322 140 17676 LED VS LTL-14CHJ(LITO)A
9322 129 38685 DIO REG SM BZM55-C6V8
(TEG0)
4822 130 83757 MCL4148
9340 260 20115 DIO SIG SM
BAW56W(PHSE) R
9322 102 64685 DIO REG SM UDZ2.7B
(RHM0) R
9340 260 20115 DIO SIG SM
BAW56W(PHSE) R
4822 130 83757 MCL4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
9340 260 20115 DIO SIG SM
BAW56W(PHSE) R
9340 260 20115 DIO SIG SM
BAW56W(PHSE) R
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
9340 260 20115 DIO SIG SM
BAW56W(PHSE) R
9340 260 20115 DIO SIG SM
BAW56W(PHSE) R
9340 260 20115 DIO SIG SM
BAW56W(PHSE) R
9340 260 20115 DIO SIG SM
BAW56W(PHSE) R
9340 260 20115 DIO SIG SM
BAW56W(PHSE) R
9340 260 20115 DIO SIG SM
BAW56W(PHSE) R
9340 260 20115 DIO SIG SM
BAW56W(PHSE) R
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 30621 1N4148
4822 130 83757 MCL4148
9322 155 22667 REMOTE RECEIVER
TSOP2236ZC1
4822 130 61553 DTC124EU
9340 217 70115 TRA SIG SM BC847BW
(PHSE) R
9340 218 50115 TRA SIG SM BC857BW
(PHSE) R
9340 218 50115 TRA SIG SM BC857BW
(PHSE) R
9340 217 70115 TRA SIG SM BC847BW
(PHSE) R
2722 171 07721 VFD BJ-801GNK 120X32
9340 217 70115 TRA SIG SM BC847BW
(PHSE) R
9322 148 79668 FET POW SM
STN3NE06(ST00)
9340 217 70115 TRA SIG SM BC847BW
(PHSE) R
9340 217 70115 TRA SIG SM BC847BW
(PHSE) R
3103 178 56451 OTPROM ASSY DDCP1-1U
9340 217 70115 TRA SIG SM BC847BW
(PHSE) R
5322 209 11147 HEF4093BT
9340 217 70115 TRA SIG SM BC847BW
(PHSE) R
4822 130 61553 DTC124EU
9340 217 70115 TRA SIG SM BC847BW
(PHSE) R
Front con PWB
Various
1910
1911
2422 033 00355 YKC22-0489
2422 025 10185 CON BM H 9P M 2.00 PH B
2102
2105
2106
4822 126 14241 0603 50V 330P COL R
4822 126 14241 0603 50V 330P COL R
4822 126 14305 100nF 10% 16V 0603
3101
3102
3106
3107
3110
3111
3112
3113
4822 051 30102
4822 051 30105
4822 051 30102
4822 051 30105
4822 051 30151
4822 051 30759
4822 051 30759
4822 051 30759
1k 5% 0.062W
1M 5% 0.062W
1k 5% 0.062W
1M 5% 0.062W
150Ω 5% 0.062W
75Ω 5% 0.062W
75Ω 5% 0.062W
75Ω 5% 0.062W
6100
6101
6102
6103
6104
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
Analog PWB
Various
1324
1325
1326
1327
1600
2422 086 10954
2422 086 10951
2422 086 10954
2422 086 10951
4822 242 10434
2412 020 00724
2422 025 10772
4822 242 73552
4822 242 10956
PROT DEV 65V 1A PSC
PROT DEV 65V 500MA PSC
PROT DEV 65V 1A PSC
PROT DEV 65V 500MA PSC
L1101-952630E1(18,432MHz )
OFWK3953M
OFWG3956M
FIL SAW 38MHz 9
OFWK9656M
TPS5,5MB-TF20
TUNER UV1316MK3(NON
EURO)
TA252E00 (32,768KHZ)
52030-2210 (22P)
YKC22-0489
CON BM H 9P M 2.00 PH B
CON BM V 07P M 2.50 EH B
OPT FIB CON GP1FA550TZ
(SRPJ)L
CON BM CINCH H 1P F BK B
CON BM EURO H 42P F BK
GRND-L
CON BMT 9P VERT PH-B
52030-2210 (22P)
CON BM MDIN 8P F
TCX0310B
CON BM CINCH 4P F
2*WHRD
CON BM CINCH H 2P F
YEYE
4P
10P. FEM. V
PROT DEV 65V 125MA
MP13
CON BM V 2P M 2.50 EH B
CON BM V 12P M 2.00 PH B
13,875 000 MHz
20MHz 20P AT-49
1700
1701
1702
4822 242 81436
4822 242 10307
2422 549 44341
1703
1705
4822 242 72586
3139 147 17001
1802
1900
1910
1911
1932
1943
4822 242 70938
4822 265 11154
2422 033 00355
2422 025 10185
2422 025 11244
9322 155 28667
1945
1950
2422 026 05197
2422 033 00334
1953
1954
1955
2422 025 10769
4822 265 11154
2422 026 05046
1958
2422 026 05093
1959
2422 026 05096
4822 126 14494
4822 126 14241
4822 126 14494
4822 124 40433
4822 126 14305
4822 124 40433
4822 126 13883
4822 126 14241
4822 126 14305
4822 126 14305
4822 124 40433
4822 126 14305
4822 124 80151
4822 126 14305
4822 124 40433
4822 126 14305
4822 124 80151
4822 126 13883
4822 126 14305
4822 122 33777
4822 124 41584
4822 126 14241
4822 126 14241
4822 126 14305
4822 126 14305
4822 126 14305
3198 017 34730
2020 552 96327
4822 126 14305
4822 124 41584
3198 017 44740
22nF 10% 25V 0603
0603 50V 330P COL R
22nF 10% 25V 0603
47µF 20% 25V
100nF 10% 16V 0603
47µF 20% 25V
220pF 5% 50V
0603 50V 330P COL R
100nF 10% 16V 0603
100nF 10% 16V 0603
47µF 20% 25V
100nF 10% 16V 0603
47µF 16V
100nF 10% 16V 0603
47µF 20% 25V
100nF 10% 16V 0603
47µF 16V
220pF 5% 50V
100nF 10% 16V 0603
47pF 5% 63V
100µF 20% 10V
0603 50V 330P COL R
0603 50V 330P COL R
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
0603 16V 47nF COL
16V 330nF PM10
100nF 10% 16V 0603
100µF 20% 10V
0603 10V 470nF COL
1960 4822 267 10565
1982 4822 267 11031
1983 2422 086 10919
1984
1987
1990
1994
2000
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2024
2030
2102
2105
2106
2321
2322
2323
2324
2325
2328
2329
Spare Parts List
2331
2332
2400
2401
2402
2403
2404
2405
2406
2407
2408
2410
2411
2430
2431
2432
2433
2434
2436
2437
2438
2439
2440
2441
2442
2443
2446
2447
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2473
2474
2477
2481
2483
2484
2500
2501
2502
2503
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2544
2545
2546
2549
2550
2551
2600
4822 124 40196
4822 124 12095
5322 126 11583
4822 126 14305
4822 126 14305
4822 124 40433
5322 126 11583
5322 126 11583
5322 126 11578
4822 126 14305
5322 126 11578
5322 126 11583
5322 126 11583
5322 126 11583
4822 124 40433
5322 126 11583
4822 124 81151
4822 124 40207
5322 124 41945
4822 126 14305
4822 126 14305
4822 124 81151
4822 124 40207
4822 124 81151
4822 124 11947
4822 124 11947
4822 126 13881
4822 126 13881
4822 124 40433
4822 124 40769
4822 124 40433
4822 124 40769
4822 126 14305
4822 126 14305
5322 126 11583
4822 126 13881
4822 126 13881
3198 017 41050
4822 126 14305
4822 122 33753
4822 126 14305
4822 126 14305
2222 867 15339
3198 017 41050
5322 126 11578
4822 126 14305
4822 126 14305
4822 124 40769
4822 124 40769
4822 126 14305
4822 126 14305
4822 126 14305
4822 124 40433
4822 124 40769
4822 124 40433
4822 122 33777
4822 122 33777
4822 126 14305
4822 126 14305
4822 124 40769
3198 017 41050
3198 017 41050
3198 017 41050
3198 017 41050
4822 124 41584
4822 126 14305
3198 017 41050
4822 126 14305
3198 017 41050
3198 017 41050
4822 126 14305
4822 126 14305
3198 017 41050
4822 126 14305
3198 017 41050
4822 126 14305
4822 124 11947
4822 124 11947
4822 126 14305
4822 124 11947
3198 017 41050
3198 017 41050
3198 017 41050
4822 124 11947
5322 126 11578
4822 126 14305
4822 126 13879
4822 126 14305
4822 126 13881
4822 126 13881
3198 017 41050
3198 017 41050
5322 126 11583
4822 124 40248
220µF 20% 16V
100µF 20% 16V
10nF 10% 50V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
47µF 20% 25V
10nF 10% 50V 0603
10nF 10% 50V 0603
1nF 10% 50V 0603
100nF 10% 16V 0603
1nF 10% 50V 0603
10nF 10% 50V 0603
10nF 10% 50V 0603
10nF 10% 50V 0603
47µF 20% 25V
10nF 10% 50V 0603
22µF 50V
100µF 20% 25V
22µF 20% 35V
100nF 10% 16V 0603
100nF 10% 16V 0603
22µF 50V
100µF 20% 25V
22µF 50V
10µF 20% 16V
10µF 20% 16V
470pF 5% 50V
470pF 5% 50V
47µF 20% 25V
4.7µF 20% 100V
47µF 20% 25V
4.7µF 20% 100V
100nF 10% 16V 0603
100nF 10% 16V 0603
10nF 10% 50V 0603
470pF 5% 50V
470pF 5% 50V
0603 10V 1µF COL R
100nF 10% 16V 0603
150pF 5% 50V
100nF 10% 16V 0603
100nF 10% 16V 0603
0603 50V 33P PM5
0603 10V 1µF COL R
1nF 10% 50V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
4.7µF 20% 100V
4.7µF 20% 100V
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
47µF 20% 25V
4.7µF 20% 100V
47µF 20% 25V
47pF 5% 63V
47pF 5% 63V
100nF 10% 16V 0603
100nF 10% 16V 0603
4.7µF 20% 100V
0603 10V 1µF COL R
0603 10V 1µF COL R
0603 10V 1µF COL R
0603 10V 1µF COL R
100µF 20% 10V
100nF 10% 16V 0603
0603 10V 1µF COL R
100nF 10% 16V 0603
0603 10V 1µF COL R
0603 10V 1µF COL R
100nF 10% 16V 0603
100nF 10% 16V 0603
0603 10V 1µF COL R
100nF 10% 16V 0603
0603 10V 1µF COL R
100nF 10% 16V 0603
10µF 20% 16V
10µF 20% 16V
100nF 10% 16V 0603
10µF 20% 16V
0603 10V 1µF COL R
0603 10V 1µF COL R
0603 10V 1µF COL R
10µF 20% 16V
1nF 10% 50V 0603
100nF 10% 16V 0603
220nF 20% 16V
100nF 10% 16V 0603
470pF 5% 50V
470pF 5% 50V
0603 10V 1µF COL R
0603 10V 1µF COL R
10nF 10% 50V 0603
10µF 20% 63V
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2612
2614
5322 126 11583
4822 124 40248
4822 126 14305
5322 126 11583
4822 124 23002
5322 126 11583
4822 126 14225
4822 124 40248
4822 126 14225
5322 126 11583
4822 124 40769
3198 030 82280
2615
3198 030 82280
2620
2621
2622
2623
2624
3198 016 33380
3198 016 33380
4822 124 40248
5322 126 11583
3198 030 82280
2625
3198 030 82280
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2800
2801
2802
2803
2806
2807
2810
2811
2812
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2831
2832
2900
2901
2902
2903
2904
2905
2906
2907
2909
2910
2911
2914
2915
2916
2917
2918
2950
2951
2952
2953
2954
2955
2956
2957
2970
2980
2981
2982
2983
2984
2990
4822 124 81151
5322 122 33861
4822 126 13883
5322 124 41379
4822 126 13881
4822 126 14305
4822 126 14305
5322 126 11583
4822 124 40248
4822 126 13879
2020 552 94523
5322 126 11578
5322 126 11578
3198 024 44730
4822 124 22652
5322 126 11578
4822 124 41584
4822 124 22652
4822 124 40433
3198 017 44740
4822 126 14238
4822 126 13482
4822 126 13883
3198 017 44740
4822 126 13482
5322 126 11578
4822 124 11968
4822 126 14305
5322 126 11583
4822 126 14507
3198 017 41050
5322 126 11578
5322 126 11583
3198 017 44740
3198 017 44740
2020 552 96305
2020 552 96305
4822 126 14305
4822 124 40433
4822 126 14305
5322 126 11583
4822 124 80151
4822 126 14305
4822 126 13879
3198 017 41050
4822 124 40433
4822 126 14305
5322 126 11583
4822 126 14305
4822 126 11669
2222 867 15339
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 124 40248
4822 126 14238
4822 126 14238
4822 126 14508
4822 126 14508
3198 017 41050
3198 017 41050
4822 124 11947
4822 124 40207
4822 126 14305
4822 124 40207
5322 126 11583
3198 016 31020
4822 126 14305
10nF 10% 50V 0603
10µF 20% 63V
100nF 10% 16V 0603
10nF 10% 50V 0603
10µF 16V
10nF 10% 50V 0603
56pF 5% 50V 0603
10µF 20% 63V
56pF 5% 50V 0603
10nF 10% 50V 0603
4.7µF 20% 100V
EL SM 50V 2U2 PM20 COL
R
EL SM 50V 2U2 PM20 COL
R
0603 50V 3P3 COL
0603 50V 3P3 COL
10µF 20% 63V
10nF 10% 50V 0603
EL SM 50V 2U2 PM20 COL
R
EL SM 50V 2U2 PM20 COL
R
22µF 50V
120pF 10% 50V
220pF 5% 50V
2.2µF 20% 50V
470pF 5% 50V
100nF 10% 16V 0603
100nF 10% 16V 0603
10nF 10% 50V 0603
10µF 20% 63V
220nF 20% 16V
0603 50V 8P2 PM0P5
1nF 10% 50V 0603
1nF 10% 50V 0603
47nF 50V 0603
2.2µF 20% 50V
1nF 10% 50V 0603
100µF 20% 10V
2.2µF 20% 50V
47µF 20% 25V
0603 10V 470nF COL
0603 50V 2N2 COL R
470nF 80/20% 16V
220pF 5% 50V
0603 10V 470nF COL
470nF 80/20% 16V
1nF 10% 50V 0603
220mF 20% 5.5V
100nF 10% 16V 0603
10nF 10% 50V 0603
18pF 5% 50V 0603
0603 10V 1µF COL R
1nF 10% 50V 0603
10nF 10% 50V 0603
0603 10V 470nF COL
0603 10V 470nF COL
4U7 20% 10V
4U7 20% 10V
100nF 10% 16V 0603
47µF 20% 25V
100nF 10% 16V 0603
10nF 10% 50V 0603
47µF 16V
100nF 10% 16V 0603
220nF 20% 16V
0603 10V 1µF COL R
47µF 20% 25V
100nF 10% 16V 0603
10nF 10% 50V 0603
100nF 10% 16V 0603
27pF
0603 50V 33P PM5
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
10µF 20% 63V
0603 50V 2N2 COL R
0603 50V 2N2 COL R
180pF 5% 50V 0603
180pF 5% 50V 0603
0603 10V 1µF COL R
0603 10V 1µF COL R
10µF 20% 16V
100µF 20% 25V
100nF 10% 16V 0603
100µF 20% 25V
10nF 10% 50V 0603
0603 25V 1nF
100nF 10% 16V 0603
DVDR980-985 /0X1
2991
2992
2993
2994
2995
2996
10.
EN 329
4822 124 40433
4822 126 14305
4822 126 14305
4822 126 14305
4822 122 33761
4822 122 33761
47µF 20% 25V
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
22pF 5% 50V
22pF 5% 50V
3000
3001
3002
3003
3004
3005
3006
3007
3008
4822 051 30472
4822 117 13632
4822 051 30103
4822 051 30103
4822 051 30103
5322 117 13026
5322 117 13026
5322 117 13026
2120 108 94006
3009
2322 704 65102
3010
2120 108 94006
3011
3012
3013
3014
3015
3016
3017
3018
5322 117 13026
5322 117 13026
4822 117 12139
4822 117 12139
4822 117 12139
4822 117 12139
5322 117 13026
2120 108 94006
3019
2120 108 94006
3020
3021
3022
5322 117 13028
5322 117 13028
2322 704 65102
3023
3024
3025
3026
3027
3028
3029
3030
3032
3101
3102
3106
3107
3110
3111
3112
3113
3321
3325
3326
3335
3336
3337
3338
3339
3340
3402
3403
3404
3405
3406
3407
3408
3409
3410
4822 117 12925
4822 117 12925
4822 117 12139
4822 117 12139
4822 117 12139
4822 117 13608
4822 051 30008
4822 117 12139
4822 051 30008
4822 051 30102
4822 051 30105
4822 051 30102
4822 051 30105
4822 051 30151
4822 051 30759
4822 051 30759
4822 051 30759
4822 117 12891
4822 117 12891
4822 051 30103
4822 051 30472
4822 051 30103
4822 117 13632
4822 117 12891
4822 117 12891
4822 117 12891
4822 117 13632
4822 051 30101
4822 051 30101
4822 051 30759
4822 051 30759
4822 051 30101
4822 051 30759
4822 051 30103
2322 574 10402
3411
3412
3413
3414
3415
3416
4822 117 13632
4822 051 30103
4822 051 30103
4822 051 30103
4822 117 13632
2322 574 10402
3417
3418
3419
3423
3424
3425
3426
3428
3429
3431
3432
4822 117 13632
4822 117 13632
4822 117 13632
4822 117 12864
4822 051 30474
4822 051 30474
4822 051 30474
4822 051 30101
4822 051 30561
4822 051 30472
4822 051 30759
4k7 5% 0.062W
100k 1% 0603 0.62W
10k 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
4k7 1% 0.063W 0603 RC22H
4k7 1% 0.063W 0603 RC22H
4k7 1% 0.063W 0603 RC22H
RST SM 0603 ERJ3G 1Ω5
PM5
RST SM 0603 RC22H 5k1
PM1
RST SM 0603 ERJ3G 1Ω5
PM5
4k7 1% 0.063W 0603 RC22H
4k7 1% 0.063W 0603 RC22H
22Ω 5% 0.062W
22Ω 5% 0.062W
22Ω 5% 0.062W
22Ω 5% 0.062W
4k7 1% 0.063W 0603 RC22H
RST SM 0603 ERJ3G 1Ω5
PM5
RST SM 0603 ERJ3G 1Ω5
PM5
12k 1% 0.063W 0603 RC22H
12k 1% 0.063W 0603 RC22H
RST SM 0603 RC22H 5k1
PM1
47k 1% 0.063W 0603
47k 1% 0.063W 0603
22Ω 5% 0.062W
22Ω 5% 0.062W
22Ω 5% 0.062W
4.7Ω 5% 0603 0.0016W
0Ω jumper
22Ω 5% 0.062W
0Ω jumper
1k 5% 0.062W
1M 5% 0.062W
1k 5% 0.062W
1M 5% 0.062W
150Ω 5% 0.062W
75Ω 5% 0.062W
75Ω 5% 0.062W
75Ω 5% 0.062W
220k 1% ERJ3Ω
220k 1% ERJ3Ω
10k 5% 0.062W
4k7 5% 0.062W
10k 5% 0.062W
100k 1% 0603 0.62W
220k 1% ERJ3Ω
220k 1% ERJ3Ω
220k 1% ERJ3Ω
100k 1% 0603 0.62W
100Ω 5% 0.062W
100Ω 5% 0.062W
75Ω 5% 0.062W
75Ω 5% 0.062W
100Ω 5% 0.062W
75Ω 5% 0.062W
10k 5% 0.062W
VDR 0805 1M A/6V4 MAX
21VR
100k 1% 0603 0.62W
10k 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
100k 1% 0603 0.62W
VDR 0805 1M A/6V4 MAX
21VR
100k 1% 0603 0.62W
100k 1% 0603 0.62W
100k 1% 0603 0.62W
82k 5% 0.6W
470k 5% 0.062W
470k 5% 0.062W
470k 5% 0.062W
100Ω 5% 0.062W
560Ω 5% 0.062W
4k7 5% 0.062W
75Ω 5% 0.062W
EN 330
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3445
3446
3450
3451
3455
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3492
3494
3495
3497
3499
3500
3501
3503
3504
3505
3506
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
10.
DVDR980-985 /0X1
4822 051 30689 68Ω 5% 0.063W 0603 RC21
RST SM
4822 117 12864 82k 5% 0.6W
4822 117 13632 100k 1% 0603 0.62W
4822 051 30759 75Ω 5% 0.062W
4822 117 12864 82k 5% 0.6W
4822 117 13632 100k 1% 0603 0.62W
4822 051 30471 470Ω 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 117 13632 100k 1% 0603 0.62W
4822 051 30472 4k7 5% 0.062W
4822 051 30479 47Ω 5% 0.062W
4822 051 30471 470Ω 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 117 13632 100k 1% 0603 0.62W
4822 051 30472 4k7 5% 0.062W
4822 117 13632 100k 1% 0603 0.62W
4822 051 30152 1k5 5% 0.062W
4822 051 30472 4k7 5% 0.062W
4822 051 30471 470Ω 5% 0.062W
4822 051 30472 4k7 5% 0.062W
2322 574 10402 VDR 0805 1M A/6V4 MAX
21VR
4822 117 13632 100k 1% 0603 0.62W
4822 117 13632 100k 1% 0603 0.62W
2322 574 10402 VDR 0805 1M A/6V4 MAX
21VR
4822 051 30471 470Ω 5% 0.062W
4822 051 30472 4k7 5% 0.062W
2322 574 10402 VDR 0805 1M A/6V4 MAX
21VR
4822 117 13632 100k 1% 0603 0.62W
4822 117 13632 100k 1% 0603 0.62W
2322 574 10402 VDR 0805 1M A/6V4 MAX
21VR
4822 051 30471 470Ω 5% 0.062W
4822 051 30689 68Ω 5% 0.063W 0603 RC21
RST SM
4822 051 30471 470Ω 5% 0.062W
4822 051 30102 1k 5% 0.062W
5322 117 13068 82Ω 1% 0.063W 0603
RC22H
4822 117 12925 47k 1% 0.063W 0603
4822 051 30759 75Ω 5% 0.062W
4822 051 30472 4k7 5% 0.062W
4822 051 30759 75Ω 5% 0.062W
4822 051 30759 75Ω 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 051 30689 68Ω 5% 0.063W 0603 RC21
RST SM
4822 051 30759 75Ω 5% 0.062W
4822 051 30102 1k 5% 0.062W
4822 051 30151 150Ω 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 051 30103 10k 5% 0.062W
4822 051 30471 470Ω 5% 0.062W
4822 117 13632 100k 1% 0603 0.62W
4822 051 30759 75Ω 5% 0.062W
4822 051 30222 2k2 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 051 30331 330Ω 5% 0.062W
4822 051 30272 2k7 5% 0.062W
4822 051 30272 2k7 5% 0.062W
4822 051 30221 220Ω 5% 0.062W
4822 051 30222 2k2 5% 0.062W
4822 051 30222 2k2 5% 0.062W
4822 051 30221 220Ω 5% 0.062W
4822 117 13632 100k 1% 0603 0.62W
4822 051 30471 470Ω 5% 0.062W
2322 574 10402 VDR 0805 1M A/6V4 MAX
21VR
4822 051 30472 4k7 5% 0.062W
4822 117 13632 100k 1% 0603 0.62W
2322 574 10402 VDR 0805 1M A/6V4 MAX
21VR
4822 051 30102 1k 5% 0.062W
4822 051 30471 470Ω 5% 0.062W
2322 574 10402 VDR 0805 1M A/6V4 MAX
21VR
4822 051 30101 100Ω 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 117 13632 100k 1% 0603 0.62W
4822 051 30472 4k7 5% 0.062W
4822 051 30471 470Ω 5% 0.062W
4822 117 13632 100k 1% 0603 0.62W
2322 574 10402 VDR 0805 1M A/6V4 MAX
21VR
4822 051 30471 470Ω 5% 0.062W
4822 051 30471 470Ω 5% 0.062W
4822 117 12925 47k 1% 0.063W 0603
4822 051 30101 100Ω 5% 0.062W
4822 051 30471 470Ω 5% 0.062W
Spare Parts List
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3567
3568
3570
3600
3601
3602
3603
3604
3605
3606
3607
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3800
3801
3803
3804
3805
3807
3808
3809
3810
3811
3812
3813
3814
3815
4822 051 30689 68Ω 5% 0.063W 0603 RC21
RST SM
4822 051 30689 68Ω 5% 0.063W 0603 RC21
RST SM
4822 051 30102 1k 5% 0.062W
4822 051 30102 1k 5% 0.062W
5322 117 13068 82Ω 1% 0.063W 0603
RC22H
4822 051 30471 470Ω 5% 0.062W
4822 051 30471 470Ω 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 051 30472 4k7 5% 0.062W
4822 051 30689 68Ω 5% 0.063W 0603 RC21
RST SM
4822 051 30102 1k 5% 0.062W
4822 051 30151 150Ω 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 051 30689 68Ω 5% 0.063W 0603 RC21
RST SM
4822 051 30102 1k 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 051 30689 68Ω 5% 0.063W 0603 RC21
RST SM
4822 051 30102 1k 5% 0.062W
4822 051 30759 75Ω 5% 0.062W
4822 051 30103 10k 5% 0.062W
4822 117 12925 47k 1% 0.063W 0603
4822 117 12925 47k 1% 0.063W 0603
4822 051 30223 22k 5% 0.062W
4822 051 30392 3k9 5% 0.063W 0603
4822 117 12891 220k 1% ERJ3Ω
4822 051 30332 3k3 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 051 30103 10k 5% 0.062W
4822 051 30472 4k7 5% 0.062W
4822 117 13632 100k 1% 0603 0.62W
4822 051 30103 10k 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 051 30472 4k7 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 051 30102 1k 5% 0.062W
4822 051 30102 1k 5% 0.062W
4822 051 30102 1k 5% 0.062W
4822 051 30102 1k 5% 0.062W
4822 051 30333 33k 5% 0.062W
4822 051 30681 680Ω 5% 0.062W
4822 051 30562 5k6 5% 0.063W 0603 RC21
RST SM
4822 051 30154 150k 5% 0.062W
4822 051 30472 4k7 5% 0.062W
4822 051 30183 18k 5% 0.062W
4822 051 30331 330Ω 5% 0.062W
4822 100 12158 22k 30%
4822 051 30101 100Ω 5% 0.062W
4822 051 30183 18k 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 051 30008 0Ω jumper
4822 051 30222 2k2 5% 0.062W
4822 051 30682 6k8 5% 0.062W
4822 051 30472 4k7 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 051 30102 1k 5% 0.062W
4822 051 30472 4k7 5% 0.062W
4822 051 30472 4k7 5% 0.062W
4822 051 30101 100Ω 5% 0.062W
4822 051 30271 270Ω 5% 0.062W
4822 051 30332 3k3 5% 0.062W
4822 117 13632 100k 1% 0603 0.62W
4822 051 30681 680Ω 5% 0.062W
4822 051 30472 4k7 5% 0.062W
4822 051 30562 5k6 5% 0.063W 0603 RC21
RST SM
4822 051 30272 2k7 5% 0.062W
4822 051 30331 330Ω 5% 0.062W
4822 051 30562 5k6 5% 0.063W 0603 RC21
RST SM
4822 051 30562 5k6 5% 0.063W 0603 RC21
RST SM
4822 051 30103 10k 5% 0.062W
4822 051 30273 27k 5% 0.062W
4822 051 30682 6k8 5% 0.062W
4822 051 30222 2k2 5% 0.062W
4822 051 30222 2k2 5% 0.062W
4822 051 30008 0Ω jumper
4822 051 30333 33k 5% 0.062W
4822 051 30103 10k 5% 0.062W
4822 117 13632 100k 1% 0603 0.62W
4822 051 30472 4k7 5% 0.062W
4822 051 30221 220Ω 5% 0.062W
4822 051 30684 680k 5% 0.062W
4822 051 30008 0Ω jumper
5322 117 13018 1k0 1% 0.063W 0603 RC22H
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3829
3830
3831
3832
3833
3834
3835
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3885
3886
3887
3888
3889
3890
3892
3893
3896
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3918
3919
3920
3925
4822 051 30101
4822 051 30102
4822 051 30101
4822 051 30101
4822 051 30472
4822 051 30103
4822 117 13632
4822 051 30103
4822 051 30103
4822 051 30103
4822 051 30008
4822 051 30472
4822 051 30103
4822 117 13632
4822 051 30222
4822 051 30222
4822 051 30103
4822 117 13632
4822 051 30472
4822 051 30103
4822 051 30101
4822 051 30101
4822 051 30684
4822 051 30103
4822 051 30102
4822 051 30472
4822 051 30102
4822 051 30332
4822 117 12925
4822 051 30103
4822 051 30472
4822 051 30103
4822 051 30223
4822 117 13632
5322 117 13018
4822 051 30472
4822 117 13632
4822 051 30222
4822 117 13632
4822 051 30223
4822 051 30682
4822 051 30103
4822 051 30223
4822 051 30101
4822 051 30101
4822 051 30101
4822 117 12925
4822 051 30101
4822 051 30103
4822 051 30332
4822 051 30101
4822 051 30103
4822 051 30103
4822 051 30123
4822 051 30102
4822 051 30331
4822 051 30101
4822 051 30101
4822 051 30103
4822 051 30103
4822 051 30103
4822 117 13632
4822 051 30331
4822 051 30222
4822 051 30479
4822 051 30474
4822 051 30223
4822 051 30102
4822 051 30101
4822 051 30103
4822 051 30103
4822 051 30103
4822 051 30103
4822 051 30103
4822 051 30103
4822 117 12925
4822 051 30472
4822 051 30102
4822 051 30102
4822 051 30102
4822 051 30333
4822 051 30101
4822 051 30101
4822 051 30101
4822 051 30102
4822 051 30472
4822 051 30103
4822 117 13632
4822 051 30101
4822 051 30101
4822 051 30103
4822 051 30103
4822 117 12891
4822 117 12139
100Ω 5% 0.062W
1k 5% 0.062W
100Ω 5% 0.062W
100Ω 5% 0.062W
4k7 5% 0.062W
10k 5% 0.062W
100k 1% 0603 0.62W
10k 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
0Ω jumper
4k7 5% 0.062W
10k 5% 0.062W
100k 1% 0603 0.62W
2k2 5% 0.062W
2k2 5% 0.062W
10k 5% 0.062W
100k 1% 0603 0.62W
4k7 5% 0.062W
10k 5% 0.062W
100Ω 5% 0.062W
100Ω 5% 0.062W
680k 5% 0.062W
10k 5% 0.062W
1k 5% 0.062W
4k7 5% 0.062W
1k 5% 0.062W
3k3 5% 0.062W
47k 1% 0.063W 0603
10k 5% 0.062W
4k7 5% 0.062W
10k 5% 0.062W
22k 5% 0.062W
100k 1% 0603 0.62W
1k0 1% 0.063W 0603 RC22H
4k7 5% 0.062W
100k 1% 0603 0.62W
2k2 5% 0.062W
100k 1% 0603 0.62W
22k 5% 0.062W
6k8 5% 0.062W
10k 5% 0.062W
22k 5% 0.062W
100Ω 5% 0.062W
100Ω 5% 0.062W
100Ω 5% 0.062W
47k 1% 0.063W 0603
100Ω 5% 0.062W
10k 5% 0.062W
3k3 5% 0.062W
100Ω 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
12k 5% 0.062W
1k 5% 0.062W
330Ω 5% 0.062W
100Ω 5% 0.062W
100Ω 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
100k 1% 0603 0.62W
330Ω 5% 0.062W
2k2 5% 0.062W
47Ω 5% 0.062W
470k 5% 0.062W
22k 5% 0.062W
1k 5% 0.062W
100Ω 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
47k 1% 0.063W 0603
4k7 5% 0.062W
1k 5% 0.062W
1k 5% 0.062W
1k 5% 0.062W
33k 5% 0.062W
100Ω 5% 0.062W
100Ω 5% 0.062W
100Ω 5% 0.062W
1k 5% 0.062W
4k7 5% 0.062W
10k 5% 0.062W
100k 1% 0603 0.62W
100Ω 5% 0.062W
100Ω 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
220k 1% ERJ3Ω
22Ω 5% 0.062W
Spare Parts List
3943
3944
3947
3948
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
4822 051 30103
4822 117 12891
4822 051 30103
4822 051 30008
4822 051 30472
4822 117 13632
4822 051 30223
4822 051 30153
4822 051 30472
4822 051 30472
4822 051 30222
4822 051 30222
4822 051 30472
3198 021 31060
3960
3198 021 31060
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
4822 051 30333
4822 051 30333
4822 051 30333
4822 051 30333
4822 051 30333
4822 051 30333
4822 051 30109
4822 051 30109
4822 051 30109
4822 117 12891
5322 117 13024
4822 051 30471
4822 051 30102
4822 051 30563
4822 051 30393
4822 051 30223
4822 051 30109
4822 051 30102
4822 051 30333
4822 051 30153
4822 051 30183
4822 051 30563
4822 051 30102
4822 051 30562
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
4822 051 30103
4822 051 30102
4822 051 30273
4822 051 30103
4822 117 12925
4822 117 12925
4822 117 12925
4822 051 30101
4822 051 30101
4822 051 30103
4822 051 30109
4822 051 30109
5000
5001
5002
5003
5004
5009
5400
5430
5470
4822 157 11074
4822 157 11074
4822 157 11299
4822 157 11499
4822 157 11499
4822 157 11775
4822 157 11299
4822 157 11299
2422 536 00019
5600
5601
4822 157 11299
2422 535 94279
5602
5700
5701
5702
5703
5705
5706
5707
5901
5903
5904
5990
5991
4822 157 11299
4822 157 11074
4822 157 11775
2422 549 44162
2422 549 44162
4822 157 11299
4822 157 11775
4822 157 11302
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11299
4822 157 11074
10k 5% 0.062W
220k 1% ERJ3Ω
10k 5% 0.062W
0Ω jumper
4k7 5% 0.062W
100k 1% 0603 0.62W
22k 5% 0.062W
15k 5% 0.062W
4k7 5% 0.062W
4k7 5% 0.062W
2k2 5% 0.062W
2k2 5% 0.062W
4k7 5% 0.062W
RST SM 0603 10M PM5COL
R
RST SM 0603 10M PM5COL
R
33k 5% 0.062W
33k 5% 0.062W
33k 5% 0.062W
33k 5% 0.062W
33k 5% 0.062W
33k 5% 0.062W
10Ω 5% 0.062W
10Ω 5% 0.062W
10Ω 5% 0.062W
220k 1% ERJ3Ω
33k 1% 0.063W 0603 RC22H
470Ω 5% 0.062W
1k 5% 0.062W
56k 5% 0.062W
39k 5% 0.062W
22k 5% 0.062W
10Ω 5% 0.062W
1k 5% 0.062W
33k 5% 0.062W
15k 5% 0.062W
18k 5% 0.062W
56k 5% 0.062W
1k 5% 0.062W
5k6 5% 0.063W 0603 RC21
RST SM
10k 5% 0.062W
1k 5% 0.062W
27k 5% 0.062W
10k 5% 0.062W
47k 1% 0.063W 0603
47k 1% 0.063W 0603
47k 1% 0.063W 0603
100Ω 5% 0.062W
100Ω 5% 0.062W
10k 5% 0.062W
10Ω 5% 0.062W
10Ω 5% 0.062W
100µH
100µH
EL0305RA-100J
BLM11P600SPT
BLM11P600SPT
6.8µH 5% 5X3
EL0305RA-100J
EL0305RA-100J
TRANSFORMER 6RG
(SAGA) B
EL0305RA-100J
IND FXD EL0305 S 100U
PM5 A
EL0305RA-100J
100µH
6.8µH 5% 5X3
IND VAR 7MM Y 77M8 B
IND VAR 7MM Y 77M8 B
EL0305RA-100J
6.8µH 5% 5X3
EL0305RA-150J
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
EL0305RA-100J
100µH
6000
6100
6101
4822 130 83757 MCL4148
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
6102
6103
6104
6402
6403
6405
6430
6431
6432
6439
6440
6460
6461
6462
6463
6464
6465
6466
6468
6501
6502
6503
6504
6505
6506
6507
6508
6509
6600
6700
6701
6702
6703
6801
6802
6803
6805
6807
6970
6971
6972
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 129 38685 DIO REG SM BZM55-C6V8
(TEG0)
9322 129 42685 DIO REG SM BZM55-C15
(TEG0) R
9322 129 38685 DIO REG SM BZM55-C6V8
(TEG0)
9322 129 38685 DIO REG SM BZM55-C6V8
(TEG0)
9322 129 38685 DIO REG SM BZM55-C6V8
(TEG0)
9322 129 38685 DIO REG SM BZM55-C6V8
(TEG0)
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
4822 130 83757 MCL4148
9322 129 42685 DIO REG SM BZM55-C15
(TEG0) R
9322 129 38685 DIO REG SM BZM55-C6V8
(TEG0)
9322 129 38685 DIO REG SM BZM55-C6V8
(TEG0)
9322 129 38685 DIO REG SM BZM55-C6V8
(TEG0)
9322 146 61685 DIO REG SM DF3A6.8FU
TOSJ
9322 129 38685 DIO REG SM BZM55-C6V8
(TEG0)
9322 129 38685 DIO REG SM BZM55-C6V8
(TEG0)
9322 129 38685 DIO REG SM BZM55-C6V8
(TEG0)
9322 150 38685 DIO SIG SM
BAS385(VISH)R
4822 130 83757 MCL4148
4822 130 11525 1SS356
4822 130 11525 1SS356
4822 130 11525 1SS356
4822 130 83757 MCL4148
9322 150 38685 DIO SIG SM
BAS385(VISH)R
4822 130 83757 MCL4148
4822 130 83757 MCL4148
9322 150 38685 DIO SIG SM
BAS385(VISH)R
4822 130 83757 MCL4148
4822 130 83757 MCL4148
4822 130 83757 MCL4148
4822 130 83757 MCL4148
7000
7001
7002
7004
7321
7323
7324
7329
7330
7331
7332
7400
7401
7430
7431
7433
9340 218 50115 TRA SIG SM BC857BW
(PHSE) R
4822 209 17423 UAD1328T
4822 209 62312 MC33078D
9352 615 37118 IC SM UDA1360TS/N1
(PHSE) R
9322 147 95668 FET SIG SM 2SK2839
(TOSJ)
9322 147 95668 FET SIG SM 2SK2839
(TOSJ)
4822 130 61553 DTC124EU
3198 010 42310 BC847BW
3198 010 42310 BC847BW
3198 010 42310 BC847BW
4822 209 33665 L78M08CV
9322 143 92668 IC SM BA7652AF (RHM0) R
9322 143 92668 IC SM BA7652AF (RHM0) R
9965 000 04716 IC BA7660FS-E2
4822 130 42804 BC817-25
4822 130 42804 BC817-25
DVDR980-985 /0X1
10.
EN 331
7460
7461
7462
7463
7464
7466
7470
7500
4822 130 42804
4822 130 42804
3198 010 42310
4822 130 42804
3198 010 42310
4822 130 42804
5322 209 11517
9340 218 50115
7501
9340 218 50115
7505
7506
7507
7508
7509
7510
7511
7512
7513
7514
4822 130 42804
4822 130 42804
9322 135 58671
3198 010 42310
3198 010 42310
3198 010 42310
4822 130 42804
3198 010 42310
3198 010 42310
9340 218 50115
7515
7516
7517
4822 130 42804
3198 010 42310
9340 218 50115
7600
9322 167 63668
7700
7701
7702
7703
4822 130 61553
4822 130 61553
4822 130 61553
9352 606 11118
7704
9340 218 50115
7705
7706
5322 130 42755
9340 218 50115
7707
7708
7709
7800
7801
7803
7804
3198 010 42310
4822 130 61553
3198 010 42310
9322 015 84668
3198 010 42310
4822 209 16884
9340 218 50115 TRA SIG SM BC857BW
(PHSE) R
3198 010 42310 BC847BW
9340 218 50115 TRA SIG SM BC857BW
(PHSE) R
4822 130 60854 DTA124EU-W
3198 010 42310 BC847BW
4822 209 63604 BA7046F
4822 209 15139 PCF8593T
9340 218 50115 TRA SIG SM BC857BW
(PHSE) R
3198 010 42310 BC847BW
4822 209 16954 ST24E16M6
3198 010 42310 BC847BW
3198 010 42310 BC847BW
4822 209 16778 TL7705ACD1013TRA
4822 209 73852 PMBT2369
9340 560 36235 BSH111
9322 152 30668 ICSM M29F800AT70N1(ST00)
9322 161 94668 IC SM CY6212870SC(CYPR)R
4822 130 61553 DTC124EU
4822 209 60177 LM339D
3198 010 42310 BC847BW
3198 010 42310 BC847BW
4822 209 63709 LM324D
4822 130 41087 BC638
3198 010 42310 BC847BW
3198 010 42310 BC847BW
9340 560 36235 BSH111
4822 209 17505 STV5348D
7805
7806
7807
7809
7810
7811
7812
7813
7815
7816
7817
7900
7901
7902
7906
7907
7909
7950
7951
7952
7970
7971
7972
7974
7975
7990
BC817-25
BC817-25
BC847BW
BC817-25
BC847BW
BC817-25
PC74HCU04T
TRA SIG SM BC857BW
(PHSE) R
TRA SIG SM BC857BW
(PHSE) R
BC817-25
BC817-25
IC SM STV6410AD (ST00) Y
BC847BW
BC847BW
BC847BW
BC817-25
BC847BW
BC847BW
TRA SIG SM BC857BW
(PHSE) R
BC817-25
BC847BW
TRA SIG SM BC857BW
(PHSE) R
IC SM MSP3415G-QG-B8
(MIAS) R
DTC124EU
DTC124EU
DTC124EU
IC SM TDA9818T/V1(PHSE)
R
TRA SIG SM BC857BW
(PHSE) R
BC847C
TRA SIG SM BC857BW
(PHSE) R
BC847BW
DTC124EU
BC847BW
IC SM TL074CD (ST00) R
BC847BW
Tray Front
Various
0002
3104 120 00272 RW BADGE
PSU PWB
Various
0010
0021
0025
4822 492 63066
4822 492 63066
4822 492 63524 FIX. TRANSISTOR
EN 332
0040
0060
0090
0101
0120
1120
1520
10.
DVDR980-985 /0X1
4822 492 63066
4822 492 63066
4822 492 63066
4822 265 31015
4822 265 11253 FUSE HOLDER 2P
4822 253 30383 19181 (2,5A)
4822 252 11144 19398E1(3,150A)
2119 2020 554 90186 CERSAF KX 250V S 1nF
PM20 A
2120 4822 121 10697 220nF 20% 275V
2125 2222 151 90053 EL 151 400V S 68µF PM20
2129 4822 121 70162 10nF 5% 400V
2130 4822 126 14525 47pF 5% 1KV
2131 2020 554 90186 CERSAF KX 250V S 1nF
PM20 A
2136 4822 126 12263 220pF 10%) 1KV
2139 2222 580 15649 100nF 10% 50V
2140 2222 580 15649 100nF 10% 50V
2141 4822 126 13881 470pF 5% 50V
2142 4822 122 33575 220pF 5% 63V CASE
2143 4822 126 14305 100nF 10% 16V 0603
2144 4822 126 14583 470nF 10% 16V XTR
2145 4822 126 14583 470nF 10% 16V XTR
2146 5322 122 34099 470pF 10% 63V
2147 4822 124 40248 10µF 20% 63V
2151 2222 580 15649 100nF 10% 50V
2152 4822 126 14241 0603 50V 330P COL R
2153 4822 126 13694 68pF 1% 63V
2200 4822 124 11566 47µF 20% 50V
2201 2222 580 15649 100nF 10% 50V
2210 2020 021 91657 EL YXG 16V S 680µF PM20
B
2211 4822 124 40255 100µF 20% 63V
2214 4822 124 12285 2200µF 20% 16V YXG EL
2220 4822 124 80144 220µF 20% 25V
2221 4822 124 40255 100µF 20% 63V
2223 2222 580 15649 100nF 10% 50V
2230 4822 124 40255 100µF 20% 63V
2235 2020 012 93762 EL YK 50V S 330µF PM20 B
2240 2020 021 91664 EL YXG 16V S 1000µF PM20
B
2241 4822 124 40255 100µF 20% 63V
2251 4822 126 14494 22nF 10% 25V 0603
2501 4822 126 14494 22nF 10% 25V 0603
2502 4822 124 40255 100µF 20% 63V
2506 4822 124 40255 100µF 20% 63V
2511 4822 126 14305 100nF 10% 16V 0603
2512 4822 124 40255 100µF 20% 63V
2513 2222 580 15649 100nF 10% 50V
2515 4822 124 40255 100µF 20% 63V
2520 4822 126 14494 22nF 10% 25V 0603
2521 4822 124 40255 100µF 20% 63V
3120 2122 550 00147 VDR DC 1M A/423V S MAX
775V B
3122 4822 053 21684 680k 5% 0.5W
3125 4822 116 83866 1M 5% 0.5W
3126 4822 116 83866 1M 5% 0.5W
3127 4822 116 83874 220k 5% 0.5W
3128 4822 116 83874 220k 5% 0.5W
3131 4822 116 52195 47Ω 5% 0.5W
3132 4822 116 52195 47Ω 5% 0.5W
3133 4822 116 80676 1Ω5 5% 0.5W
3134 4822 116 80676 1Ω5 5% 0.5W
3135 4822 116 80676 1Ω5 5% 0.5W
3139 4822 117 13632 100k 1% 0603 0.62W
3140 4822 051 30272 2k7 5% 0.062W
3141 4822 116 52257 22k 5% 0.5W
3142 4822 051 30221 220Ω 5% 0.062W
3143 4822 051 30102 1k 5% 0.062W
3144 4822 051 30102 1k 5% 0.062W
3145 4822 051 20223 22k 5% 0.1W
3146 4822 116 52175 100Ω 5% 0.5W
3147 4822 051 30222 2k2 5% 0.062W
3148 4822 116 52256 2k2 5% 0.5W
3149 4822 116 52256 2k2 5% 0.5W
3150 4822 053 10689 68Ω 5% 1W
3151 4822 117 13632 100k 1% 0603 0.62W
3152 4822 116 52261 24k 5% 0.5W
3200 4822 116 52263 2k7 5% 0.5W
3201 4822 051 20333 33k 5% 0.1W
3220 4822 051 30222 2k2 5% 0.062W
3221 4822 051 30223 22k 5% 0.062W
3222 4822 051 30472 4k7 5% 0.062W
3223 4822 116 52283 4k7 5% 0.5W
3230 4822 052 10479 47Ω 5% 0.33W
3233 4822 117 10833 10k 1% 0.1W
Spare Parts List
3234
3250
3253
3254
3255
3256
3501
3502
3503
3504
3511
3512
3513
3514
3515
3516
3520
3521
3522
3523
3524
3525
4822 117 10833
4822 116 83883
4822 117 12925
4822 116 83883
5322 117 13026
5322 117 13026
4822 116 52256
5322 117 13026
4822 051 30681
5322 117 13026
4822 051 30103
4822 051 20472
4822 117 12925
4822 050 21003
4822 117 10833
4822 051 30103
4822 051 20511
4822 051 30102
4822 117 11449
4822 051 30681
4822 051 20332
5322 117 13036
10k 1% 0.1W
470Ω 5% 0.5W
47k 1% 0.063W 0603
470Ω 5% 0.5W
4k7 1% 0.063W 0603 RC22H
4k7 1% 0.063W 0603 RC22H
2k2 5% 0.5W
4k7 1% 0.063W 0603 RC22H
680Ω 5% 0.062W
4k7 1% 0.063W 0603 RC22H
10k 5% 0.062W
4k7 5% 0.1W
47k 1% 0.063W 0603
10k 1% 0.6W
10k 1% 0.1W
10k 5% 0.062W
510Ω 5% 0.1W
1k 5% 0.062W
2k2 5% 0.1W 0805
680Ω 5% 0.062W
3k3 5% 0.1W
1k2 1% 0.063W 0603 RC22H
7502
7511
7512
7515
7520
7521
Dig 1.5 PWB
Various
1100
1101
1200
1500
1600
1601
5110
5115
5120
5125
5131
5210
5240
5501
5505
5511
5515
5520
2422 535 94634 IND FXD LHL08 S 2U2 PM20
A
2422 535 94634 IND FXD LHL08 S 2U2 PM20
A
4822 157 11846
4822 157 70826 2.4µH
4822 146 10402 TRAFO CT395FANF/PVF
2422 535 94639 IND FXD LHL08 S 10U PM20
2422 535 94632 IND FXD LHL08 S 1U PM30
A
2422 535 94634 IND FXD LHL08 S 2U2 PM20
A
2422 535 94639 IND FXD LHL08 S 10U PM20
2422 535 94639 IND FXD LHL08 S 10U PM20
2422 535 94639 IND FXD LHL08 S 10U PM20
2422 535 94634 IND FXD LHL08 S 2U2 PM20
A
6125
6130
6131
6132
6140
6141
6142
6143
6144
4822 130 42606
5322 130 34574
5322 130 34574
5322 130 34574
4822 130 30842
4822 130 83757
4822 130 30842
4822 130 30842
9340 387 30115
6145
6146
6151
6152
6153
6154
6200
6201
6210
6211
6215
4822 130 83757
4822 130 83757
4822 130 31603
4822 130 31603
4822 130 31603
4822 130 31603
4822 130 42606
4822 130 34142
4822 130 11596
5322 130 34574
9322 161 46687
6220
6221
6230
6231
6240
6505
6511
6512
6515
6520
5322 130 31938
4822 130 30842
4822 130 42606
4822 130 34142
4822 130 11596
4822 130 32245
4822 130 11666
5322 130 34574
4822 130 34278
4822 130 83757
BYD33J
1N4004G
1N4004G
1N4004G
BAV21
MCL4148
BAV21
BAV21
DIO REG SM BZX284-C16
(PHSE) R
MCL4148
MCL4148
1N4006
1N4006
1N4006
1N4006
BYD33J
BZX79-B33
BYW29EX-200
1N4004G
DIO REC STPS745FP
(ST00) L
BYV27-200
BAV21
BYD33J
BZX79-B33
BYW29EX-200
BYV10-40
BZX284-C8V2
1N4004G
BZX79-B6V8
MCL4148
7125
7140
7141
7142
7143
7200
9322 126 65687
5322 130 60159
4822 130 60373
5322 130 60159
5322 130 60159
9322 149 04682
7220
7241
7251
7501
4822 209 72684
4822 130 60373
4822 209 81397
9322 163 53685
STP5NB60FP
BC846B
BC856B
BC846B
BC846B
OPT CP TCET1102(G)
(VISH) L
L7905CV
BC856B
TL431CLPST
FET POW SM IRLML2502
(INR0) R
4822 209 81397 TL431CLPST
9322 163 53685 FET POW SM IRLML2502
(INR0) R
5322 130 60159 BC846B
9322 163 53685 FET POW SM IRLML2502
(INR0) R
4822 130 11336 STP16NE06FP
4822 209 81397 TL431CLPST
1602
1603
2422 025 17018 CON BM V 15P F 1.00 FFC
0.3 R
2422 025 17018 CON BM V 15P F 1.00 FFC
0.3 R
2422 025 16794 CON BM V 7P F 1.00 FFC
0.3 R
2422 543 01115 RES XTL SM 24M576 12P
CX-11F R
2422 025 16729 CON BM V 10P F 1.00 FFC
0.3 R
2422 025 16389 CON BM V 22P F 1.00 FFC
0.3 R
2422 025 16389 CON BM V 22P F 1.00 FFC
0.3 R
2422 025 16939 CON BM V 60P F 0.80 84616
R
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
3198 030 74780
2120
2121
2122
2123
2124
2125
2126
2127
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
3198 030 74780
2128
2129
2130
3198 016 31020
4822 126 13956
3198 030 82280
2131
2132
2135
5322 124 41945
4822 126 14305
3198 030 74780
2136
2137
2139
2141
2146
2200
2201
2202
2203
4822 122 33777
4822 126 14305
4822 126 14305
4822 122 33777
4822 126 14305
3198 016 31020
4822 126 14494
4822 126 14305
3198 030 74780
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2222 867 15339
4822 126 14305
4822 126 14305
2222 867 15339
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
0603 25V 1nF
68pF 5% 63V CASE 0603
EL SM 50V 2U2 PM20 COL
R
22µF 20% 35V
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
47pF 5% 63V
100nF 10% 16V 0603
100nF 10% 16V 0603
47pF 5% 63V
100nF 10% 16V 0603
0603 25V 1nF
22nF 10% 25V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
0603 50V 33P PM5
100nF 10% 16V 0603
100nF 10% 16V 0603
0603 50V 33P PM5
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
Spare Parts List
2215
2216
2217
2218
4822 126 14305
4822 126 14305
4822 126 14305
3198 030 74780
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
3198 030 74780
2231
2300
2301
2302
2303
2304
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
3198 030 74780
2305
3198 030 74780
2306
2307
2308
2309
2310
2311
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
3198 030 74780
2312
2402
2403
4822 126 14305
4822 126 14305
3198 030 74780
2404
2405
2406
2407
2408
2409
2410
2411
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
3198 030 74780
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
3198 030 74780
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
3198 030 74780
2442
2444
2446
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
4822 126 14305
4822 126 14305
3198 016 31020
3198 016 31020
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14507
4822 126 14507
4822 126 14305
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
EL SM 35V 4U7 PM20 COL
R
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
100nF 10% 16V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
100nF 10% 16V 0603
100nF 10% 16V 0603
0603 25V 1nF
0603 25V 1nF
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
18pF 5% 50V 0603
18pF 5% 50V 0603
100nF 10% 16V 0603
2513
2514
2515
2516
2517
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
3198 030 74780
2518
3198 030 74780
2519
3198 030 74780
2520
3198 030 74780
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
3198 030 74780
2540
3198 030 74780
2541
3198 030 74780
2542
3198 030 74780
2543
2544
2565
2600
2601
2602
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2625
2626
2627
2628
2629
2630
4822 126 14305
4822 126 14305
4822 122 33753
4822 126 14305
4822 122 33777
4822 122 33777
4822 126 14305
4822 122 33777
4822 122 33777
4822 126 14305
4822 126 14305
4822 126 14305
4822 122 33777
4822 122 33777
4822 126 14305
4822 126 14305
4822 126 14305
4822 122 33777
4822 122 33777
4822 126 14305
4822 126 14305
4822 126 14305
4822 122 33777
4822 122 33777
4822 126 14305
4822 122 33777
4822 122 33777
4822 126 14305
4822 126 14305
3198 030 74780
2632
2633
2634
2635
2636
4822 126 14305
4822 126 14305
4822 126 14494
4822 126 14305
3198 030 74780
2722
2900
2901
2902
2903
2904
2906
2907
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
3198 030 74780
2908
2909
2911
2912
2914
4822 126 14305
4822 126 14247
4822 126 14305
4822 126 14247
3198 030 74780
2915
2916
4822 126 14305
4822 126 14494
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
EL SM 35V 4U7 PM20 COL
R
EL SM 35V 4U7 PM20 COL
R
EL SM 35V 4U7 PM20 COL
R
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
EL SM 35V 4U7 PM20 COL
R
EL SM 35V 4U7 PM20 COL
R
EL SM 35V 4U7 PM20 COL
R
100nF 10% 16V 0603
100nF 10% 16V 0603
150pF 5% 50V
100nF 10% 16V 0603
47pF 5% 63V
47pF 5% 63V
100nF 10% 16V 0603
47pF 5% 63V
47pF 5% 63V
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
47pF 5% 63V
47pF 5% 63V
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
47pF 5% 63V
47pF 5% 63V
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
47pF 5% 63V
47pF 5% 63V
100nF 10% 16V 0603
47pF 5% 63V
47pF 5% 63V
100nF 10% 16V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
100nF 10% 16V 0603
100nF 10% 16V 0603
22nF 10% 25V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
EL SM 35V 4U7 PM20 COL
R
100nF 10% 16V 0603
0603 50V 1N5 COL R
100nF 10% 16V 0603
0603 50V 1N5 COL R
EL SM 35V 4U7 PM20 COL
R
100nF 10% 16V 0603
22nF 10% 25V 0603
DVDR980-985 /0X1
10.
EN 333
3100
3101
3102
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
4822 051 30103
4822 051 30222
4822 051 30103
4822 051 30479
4822 051 30479
4822 051 30479
4822 051 30109
4822 051 30479
4822 051 30479
4822 051 30479
4822 051 30472
4822 051 30472
4822 051 30472
4822 051 30472
4822 051 30103
4822 051 30103
4822 117 12139
4822 117 12139
4822 051 30222
4822 051 30153
4822 117 12917
4822 051 30123
2322 704 62002
3124
2322 704 63002
3125
3126
3127
3128
3129
3130
4822 117 12139
4822 117 12891
4822 051 30479
4822 051 30479
4822 051 30479
2120 611 00019
3131
3132
3133
3134
3135
3136
3137
3138
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
4822 117 12917
4822 117 12917
4822 117 12917
4822 117 12917
4822 117 12917
4822 117 12917
4822 051 30472
4822 051 30472
4822 051 30332
4822 051 30152
4822 051 30103
4822 117 12139
4822 051 30101
4822 051 30101
4822 051 30101
4822 051 30103
4822 117 12139
4822 051 30103
4822 051 30222
4822 051 30152
4822 051 30103
4822 051 30103
4822 051 30103
4822 051 30103
4822 051 30101
4822 051 30101
4822 051 30103
4822 051 30103
4822 051 30103
4822 051 30103
4822 051 30222
4822 051 30103
4822 051 30103
4822 051 30103
4822 117 12139
4822 117 12139
2322 704 61303
3230
2322 704 61303
3231
3232
3234
5322 117 13042
5322 117 13042
3198 031 14720
3235
3236
3237
3300
3301
3400
3401
3403
3404
3404
3405
3406
3407
4822 117 12917
4822 117 13576
4822 117 13576
4822 051 30479
4822 051 30479
4822 051 30101
4822 051 30101
4822 051 30103
4822 051 30008
4822 117 12917
4822 051 30332
4822 051 30479
4822 051 30181
10k 5% 0.062W
2k2 5% 0.062W
10k 5% 0.062W
47Ω 5% 0.062W
47Ω 5% 0.062W
47Ω 5% 0.062W
10Ω 5% 0.062W
47Ω 5% 0.062W
47Ω 5% 0.062W
47Ω 5% 0.062W
4k7 5% 0.062W
4k7 5% 0.062W
4k7 5% 0.062W
4k7 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
22Ω 5% 0.062W
22Ω 5% 0.062W
2k2 5% 0.062W
15k 5% 0.062W
1Ω 5% 0.062W CASE0603
12k 5% 0.062W
RST SM 0603 RC22H 2k
PM1 R
RST SM 0603 RC22H 3k
PM1 R
22Ω 5% 0.062W
220k 1% ERJ3Ω
47Ω 5% 0.062W
47Ω 5% 0.062W
47Ω 5% 0.062W
NTC SM 0603 0W1 4k7 PM5
R
1Ω 5% 0.062W CASE0603
1Ω 5% 0.062W CASE0603
1Ω 5% 0.062W CASE0603
1Ω 5% 0.062W CASE0603
1Ω 5% 0.062W CASE0603
1Ω 5% 0.062W CASE0603
4k7 5% 0.062W
4k7 5% 0.062W
3k3 5% 0.062W
1k5 5% 0.062W
10k 5% 0.062W
22Ω 5% 0.062W
100Ω 5% 0.062W
100Ω 5% 0.062W
100Ω 5% 0.062W
10k 5% 0.062W
22Ω 5% 0.062W
10k 5% 0.062W
2k2 5% 0.062W
1k5 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
100Ω 5% 0.062W
100Ω 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
2k2 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
22Ω 5% 0.062W
22Ω 5% 0.062W
RST SM 0603 RC22H 13k
PM1 R
RST SM 0603 RC22H 13k
PM1 R
3k9 1% 0.063W 0603 RC22H
3k9 1% 0.063W 0603 RC22H
RST NETW 1206 4X4k7 PM5
COL R
1Ω 5% 0.062W CASE0603
NETW 4 X 33Ω 5% 1206
NETW 4 X 33Ω 5% 1206
47Ω 5% 0.062W
47Ω 5% 0.062W
100Ω 5% 0.062W
100Ω 5% 0.062W
10k 5% 0.062W
0Ω jumper
1Ω 5% 0.062W CASE0603
3k3 5% 0.062W
47Ω 5% 0.062W
180Ω 5% 0.062W
EN 334
10.
3408
3409
3410
3500
3501
3502
3503
3503
3504
3505
3506
3507
3508
3513
3515
3600
4822 117 12139
4822 117 12139
4822 117 12139
4822 051 30101
4822 051 30101
4822 051 30222
4822 051 30102
4822 051 30759
4822 051 30681
4822 117 12139
4822 051 30222
4822 051 30472
4822 051 30103
4822 051 30681
4822 117 12917
2322 704 65609
3601
5322 117 13059
3602
5322 117 13059
3603
3604
3604
3605
3606
4822 051 30102
4822 051 30101
4822 117 12139
4822 117 12917
5322 117 13059
3607
5322 117 13059
3608
3610
3611
4822 051 30102
4822 117 12917
5322 117 13059
3612
5322 117 13059
3613
3615
3616
4822 051 30102
4822 051 30101
5322 117 13059
3617
5322 117 13059
3618
3619
3620
3621
4822 051 30102
4822 051 30561
4822 051 30222
5322 117 13059
3622
5322 117 13059
3623
3623
3624
3625
3625
3626
4822 051 30101
4822 117 12139
4822 051 30102
4822 051 30101
4822 117 12139
5322 117 13059
3627
5322 117 13059
3628
3629
3630
3631
3632
3633
3635
3635
3636
3637
3637
3638
3900
3901
3902
3903
3904
3906
3908
3910
3911
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
4822 051 30102
4822 051 30181
4822 051 30181
4822 117 12917
4822 051 30561
4822 051 30561
4822 051 30101
4822 117 12139
4822 051 30181
4822 051 30101
4822 117 12139
4822 051 30222
4822 051 30103
4822 117 12139
4822 117 12925
4822 117 13632
4822 117 12139
4822 051 30479
4822 117 12139
4822 051 30101
4822 051 30103
4822 051 30682
4822 051 30479
4822 051 30479
4822 117 13632
4822 117 12139
4822 117 13632
4822 051 30101
4822 117 12139
4822 051 30103
4822 051 30682
4822 117 13632
4822 051 30152
4822 051 30472
DVDR980-985 /0X1
22Ω 5% 0.062W
22Ω 5% 0.062W
22Ω 5% 0.062W
100Ω 5% 0.062W
100Ω 5% 0.062W
2k2 5% 0.062W
1k 5% 0.062W
75Ω 5% 0.062W
680Ω 5% 0.062W
22Ω 5% 0.062W
2k2 5% 0.062W
4k7 5% 0.062W
10k 5% 0.062W
680Ω 5% 0.062W
1Ω 5% 0.062W CASE0603
RST SM 0603 RC22H 56Ω
PM1 R
560Ω 1% 0.063W 0603
RC22H
560Ω 1% 0.063W 0603
RC22H
1k 5% 0.062W
100Ω 5% 0.062W
22Ω 5% 0.062W
1Ω 5% 0.062W CASE0603
560Ω 1% 0.063W 0603
RC22H
560Ω 1% 0.063W 0603
RC22H
1k 5% 0.062W
1Ω 5% 0.062W CASE0603
560Ω 1% 0.063W 0603
RC22H
560Ω 1% 0.063W 0603
RC22H
1k 5% 0.062W
100Ω 5% 0.062W
560Ω 1% 0.063W 0603
RC22H
560Ω 1% 0.063W 0603
RC22H
1k 5% 0.062W
560Ω 5% 0.062W
2k2 5% 0.062W
560Ω 1% 0.063W 0603
RC22H
560Ω 1% 0.063W 0603
RC22H
100Ω 5% 0.062W
22Ω 5% 0.062W
1k 5% 0.062W
100Ω 5% 0.062W
22Ω 5% 0.062W
560Ω 1% 0.063W 0603
RC22H
560Ω 1% 0.063W 0603
RC22H
1k 5% 0.062W
180Ω 5% 0.062W
180Ω 5% 0.062W
1Ω 5% 0.062W CASE0603
560Ω 5% 0.062W
560Ω 5% 0.062W
100Ω 5% 0.062W
22Ω 5% 0.062W
180Ω 5% 0.062W
100Ω 5% 0.062W
22Ω 5% 0.062W
2k2 5% 0.062W
10k 5% 0.062W
22Ω 5% 0.062W
47k 1% 0.063W 0603
100k 1% 0603 0.62W
22Ω 5% 0.062W
47Ω 5% 0.062W
22Ω 5% 0.062W
100Ω 5% 0.062W
10k 5% 0.062W
6k8 5% 0.062W
47Ω 5% 0.062W
47Ω 5% 0.062W
100k 1% 0603 0.62W
22Ω 5% 0.062W
100k 1% 0603 0.62W
100Ω 5% 0.062W
22Ω 5% 0.062W
10k 5% 0.062W
6k8 5% 0.062W
100k 1% 0603 0.62W
1k5 5% 0.062W
4k7 5% 0.062W
Spare Parts List
7901
7902
5100
5101
5102
5103
5200
5201
5202
5203
5204
5205
5207
5208
5209
5300
5302
5400
5402
5403
5404
5500
5501
5502
5503
5504
5505
5506
5507
5508
5600
5601
5602
5603
5604
5605
5606
5607
5900
5901
5903
5904
5905
5907
4822 157 11717
4822 157 11717
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 70651
4822 157 70651
4822 157 70651
4822 157 70651
4822 157 70651
4822 157 70651
4822 157 70649
4822 157 70649
4822 157 11717
4822 157 11717
4822 157 11499
4822 157 11717
4822 157 11499
4822 157 11499
BLM31P500SPT
BLM31P500SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
12µH (NL322522T-120J)
12µH (NL322522T-120J)
12µH (NL322522T-120J)
12µH (NL322522T-120J)
12µH (NL322522T-120J)
12µH (NL322522T-120J)
4.7µH (NL322522T-4R7J)
4.7µH (NL322522T-4R7J)
BLM31P500SPT
BLM31P500SPT
BLM11P600SPT
BLM31P500SPT
BLM11P600SPT
BLM11P600SPT
4822 130 11528
4822 130 80622
4822 130 11528
4822 130 80622
1PS76SB10
BAT54
1PS76SB10
BAT54
7904
7905
7906
DIVIO front DVD985 /001 /021
Various
1000
1001
2000
2001
2002
2002
2003
2003
2004
2005
2204
2205
4822 051 20105 1M 5% 0.1W
5000
2422 549 44768 IND FXD SM EMI 100mH z
90R R
2422 549 44768 IND FXD SM EMI 100mH z
90R R
5001
6000
6001
Various
1200
7202
7203
7300
7303
7402
7403
7404
7500
7501
7502
7504
7600
7601
7602
7603
7604
7605
7606
7702
7900
4822 130 11395 TLMH3100
9322 172 97668 DIO SUP SM6T39CA (ST00)
R
DIVIO PWB DVD985 /001 /021
7100
7102
7103
7104
7200
7201
1nF 5% 50V
1nF 5% 50V
250V 4N7 PM10 R
50V 330nF P8020 R
250V 4N7 PM10 R
50V 330nF P8020 R
250V 4N7 PM10 R
250V 4N7 PM10 R
0603 50V 33P PM5
0603 50V 33P PM5
3000
1101
1102
7101
5322 126 10511
5322 126 10511
2020 557 90732
2222 580 19815
2020 557 90732
2222 580 19815
2020 557 90732
2020 557 90732
2222 867 15339
2222 867 15339
9352 692 48557 IC SM SAA7333HL/M1
(PHSE) Y
9322 166 67668 IC SM MT48LC4M16A2TG7E(MRN0)R
5322 209 16384 PC74HCT9046AD
9322 170 16685 IC SM NC7SZ58 (FSC0) R
9352 456 50115 HC1G04
9322 169 81671 IC SM STI5508EVB (ST00) Y
9322 130 41668 IC SM M24C64-WMN6
(ST00) R
4822 209 30212 PC74HCT125T
9322 142 88668 IC SM LF25CDT (ST00) R
9322 166 67668 IC SM MT48LC4M16A2TG7E(MRN0)R
9352 499 60118 IC SM 74LVC00AD (PHSE)
R
9322 166 67668 IC SM MT48LC4M16A2TG7E(MRN0)R
9352 701 80557 IC SM SAA6752HS/V101
(PHSE) Y
9322 142 88668 IC SM LF25CDT (ST00) R
9352 673 95518 IC SM SAA7118E/V1 (PHSE)
R
9352 500 60118 IC SM 74LVC32AD (PHSE)
R
5322 209 71589 74HC74D
4822 130 60511 BC847B
4822 130 60511 BC847B
4822 130 60511 BC847B
4822 130 60511 BC847B
4822 130 60511 BC847B
4822 130 60511 BC847B
4822 130 60511 BC847B
4822 130 60511 BC847B
9352 501 00118 IC SM 74LVC86ADB (PHSE)
R
9322 151 71668 IC SM MK2703STR (MICL) R
2422 033 00363 CON BM H 4P F 0.8 B
2422 025 17106 CON BM H 4P F 0.8 IEEE R
6500
6500
6900
6900
4822 130 60511 BC847B
9322 165 15685 IC SM NCP303LSN30
(ONSE) R
4822 209 16399 74LVC04AD
5322 209 71568 PC74HCT14T
4822 242 10838 27MHZ 120P FX0-31FT
1500
2422 025 17106 CON BM H 4P F 0.8 IEEE R
2422 543 01115 RES XTL SM 24M576 12P
CX-11F R
2422 543 01159 RES XTL SM 11M0592 20P
DSX840
2422 025 17084 CON BM V 60P F 0.80
179161 R
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2163
2170
2171
2173
2174
2175
2176
2177
2178
2181
2182
2183
2184
2187
2192
2193
2194
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
3198 017 41050
4822 126 14506
4822 126 11663
4822 126 11663
4822 124 23002
4822 126 14305
4822 124 23002
4822 126 14305
4822 126 14305
4822 126 14305
4822 124 12095
4822 124 23002
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
0603 10V 1µF COL R
270pF 5% 50V 0603
12pF
12pF
10µF 16V
100nF 10% 16V 0603
10µF 16V
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100µF 20% 16V
10µF 16V
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
Spare Parts List
2195
2196
2197
2200
2202
2203
2204
2205
2206
2207
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2318
2319
2324
2325
2330
2331
2332
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2514
2515
2516
2517
2518
2519
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 11663
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 11663
4822 122 31765
4822 126 14305
4822 126 14305
4822 124 80151
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 124 80151
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 126 14305
4822 124 80151
4822 126 14305
4822 124 80151
4822 126 14305
4822 126 14305
4822 126 14305
4822 124 80151
4822 124 80151
4822 124 80151
4822 124 80151
5322 126 11583
5322 126 11583
4822 124 80151
4822 126 14305
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
12pF
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
12pF
100pF 2% 63V 1206
100nF 10% 16V 0603
100nF 10% 16V 0603
47µF 16V
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
47µF 16V
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
47µF 16V
100nF 10% 16V 0603
47µF 16V
100nF 10% 16V 0603
100nF 10% 16V 0603
100nF 10% 16V 0603
47µF 16V
47µF 16V
47µF 16V
47µF 16V
10nF 10% 50V 0603
10nF 10% 50V 0603
47µF 16V
100nF 10% 16V 0603
4822 117 12925
4822 117 12925
4822 051 30103
4822 051 30103
4822 117 12925
4822 051 30109
4822 051 30103
4822 051 30109
4822 051 30109
4822 117 12925
4822 117 12925
4822 051 30103
4822 051 30102
4822 117 12917
4822 051 30109
4822 117 12925
4822 117 12925
4822 117 12925
47k 1% 0.063W 0603
47k 1% 0.063W 0603
10k 5% 0.062W
10k 5% 0.062W
47k 1% 0.063W 0603
10Ω 5% 0.062W
10k 5% 0.062W
10Ω 5% 0.062W
10Ω 5% 0.062W
47k 1% 0.063W 0603
47k 1% 0.063W 0603
10k 5% 0.062W
1k 5% 0.062W
1Ω 5% 0.062W CASE0603
10Ω 5% 0.062W
47k 1% 0.063W 0603
47k 1% 0.063W 0603
47k 1% 0.063W 0603
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3113
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3130
3131
3132
3133
3134
3136
3138
3140
3148
4822 117 12925
4822 117 12925
4822 117 12925
4822 117 12925
4822 117 12925
4822 117 12925
4822 117 12925
4822 117 12925
4822 117 12925
4822 117 12925
4822 117 12925
4822 051 30223
4822 051 30223
4822 117 12917
4822 051 30103
4822 051 30103
2322 704 66342
3163
3164
4822 051 30008
2322 734 65609
3165
2322 734 65609
3171
3172
3173
4822 051 30109
4822 051 30109
2322 734 65609
3174
3176
3177
4822 051 30109
4822 051 30109
2322 704 65102
3178
2322 734 65609
3179
3188
3189
3190
3191
3192
3197
3198
3199
3201
3202
3203
3204
3205
3206
3223
3224
3225
3300
3301
3303
3305
3306
3307
3312
3313
3314
3315
3317
3318
3319
3320
3321
3322
3325
3327
3328
3329
3330
3331
3400
3401
3402
3403
3404
3405
3502
3504
3505
3506
3510
3511
3518
3519
3520
3521
3524
3525
3526
3527
4822 051 30103
4822 051 30479
4822 051 30109
4822 051 30479
4822 051 30109
4822 117 12925
4822 117 12925
4822 117 12925
4822 117 12925
4822 051 30479
4822 051 30103
4822 051 30102
4822 051 30103
4822 117 12925
4822 117 12925
4822 051 30472
4822 051 30331
4822 051 30109
4822 051 30109
4822 051 30102
4822 051 30102
4822 051 30102
4822 051 30102
4822 051 30102
4822 051 30109
4822 051 30103
4822 051 30103
4822 051 30339
4822 051 30339
4822 051 30339
4822 051 30339
4822 051 30479
4822 051 30479
4822 051 30479
4822 051 30479
4822 051 30479
4822 051 30103
4822 051 30103
4822 051 30479
4822 051 30479
4822 051 30103
4822 117 13573
4822 117 13573
4822 051 30479
4822 051 30479
4822 051 30479
4822 051 30339
4822 117 13576
4822 117 13576
4822 051 30339
4822 051 30479
4822 051 30008
4822 051 30101
4822 051 30101
4822 117 12891
4822 117 12891
4822 051 30339
4822 051 30339
4822 051 30339
4822 051 30339
47k 1% 0.063W 0603
47k 1% 0.063W 0603
47k 1% 0.063W 0603
47k 1% 0.063W 0603
47k 1% 0.063W 0603
47k 1% 0.063W 0603
47k 1% 0.063W 0603
47k 1% 0.063W 0603
47k 1% 0.063W 0603
47k 1% 0.063W 0603
47k 1% 0.063W 0603
22k 5% 0.062W
22k 5% 0.062W
1Ω 5% 0.062W CASE0603
10k 5% 0.062W
10k 5% 0.062W
RST SM 0603 RC22H 6k34
PM1 R
0Ω jumper
RST SM 0805 RC12H 56Ω
PM1 R
RST SM 0805 RC12H 56Ω
PM1 R
10Ω 5% 0.062W
10Ω 5% 0.062W
RST SM 0805 RC12H 56Ω
PM1 R
10Ω 5% 0.062W
10Ω 5% 0.062W
RST SM 0603 RC22H 5k1
PM1
RST SM 0805 RC12H 56Ω
PM1 R
10k 5% 0.062W
47Ω 5% 0.062W
10Ω 5% 0.062W
47Ω 5% 0.062W
10Ω 5% 0.062W
47k 1% 0.063W 0603
47k 1% 0.063W 0603
47k 1% 0.063W 0603
47k 1% 0.063W 0603
47Ω 5% 0.062W
10k 5% 0.062W
1k 5% 0.062W
10k 5% 0.062W
47k 1% 0.063W 0603
47k 1% 0.063W 0603
4k7 5% 0.062W
330Ω 5% 0.062W
10Ω 5% 0.062W
10Ω 5% 0.062W
1k 5% 0.062W
1k 5% 0.062W
1k 5% 0.062W
1k 5% 0.062W
1k 5% 0.062W
10Ω 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
33Ω 5% 0.062W
33Ω 5% 0.062W
33Ω 5% 0.062W
33Ω 5% 0.062W
47Ω 5% 0.062W
47Ω 5% 0.062W
47Ω 5% 0.062W
47Ω 5% 0.062W
47Ω 5% 0.062W
10k 5% 0.062W
10k 5% 0.062W
47Ω 5% 0.062W
47Ω 5% 0.062W
10k 5% 0.062W
NETW 4 X 47Ω 5% MNR14
NETW 4 X 47Ω 5% MNR14
47Ω 5% 0.062W
47Ω 5% 0.062W
47Ω 5% 0.062W
33Ω 5% 0.062W
NETW 4 X 33Ω 5% 1206
NETW 4 X 33Ω 5% 1206
33Ω 5% 0.062W
47Ω 5% 0.062W
0Ω jumper
100Ω 5% 0.062W
100Ω 5% 0.062W
220k 1% ERJ3Ω
220k 1% ERJ3Ω
33Ω 5% 0.062W
33Ω 5% 0.062W
33Ω 5% 0.062W
33Ω 5% 0.062W
DVDR980-985 /0X1
5103
5106
5109
5110
5200
5300
5301
5302
5303
5304
5402
5403
5404
5500
5501
5502
5503
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
4822 157 11499
10.
EN 335
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
BLM11P600SPT
6300
4822 209 17398 LD1117DT33
7101
7103
7201
7202
7204
7207
7208
7300
7301
7303
7304
7307
7308
7309
7402
7402
7403
7403
7404
7404
7500
7505
7506
9352 683 02157 IC SM PDI1394P25BD
(PHSE) Y
9352 682 52557 IC SM PDI1394L40 (PHSE)
Y
4822 209 91023 UM62256EM-70LL
4822 130 60511 BC847B
9337 331 10215 FET SIG SM BST82 (PHSE)
R
4822 130 60511 BC847B
9352 456 40115 IC SM 74HCT1G04GW
(PHSE) R
3104 123 96640 IC ROM XC17S30XL DVIO
1.5
9322 166 64668 IC SM CY7C1019BV3310VC(CYPR)R
9322 169 90671 IC SM XCS30XL-4TQ144C
(XILI) Y
4822 242 10838 27MHZ 120P FX0-31FT
3104 123 96620 IC FLASH PLL CY2071A
DVIO 1.5
3104 123 96620 IC FLASH PLL CY2071A
DVIO 1.5
3104 123 96630 IC FLASH XC18V01 DVIO
1.5
8204 056 07210 IC SM MT4LC1M16E5DJ-6
9322 178 74668 MT4LC1M16E5DJ-6
8204 056 07210 IC SM MT4LC1M16E5DJ-6
9322 178 74668 MT4LC1M16E5DJ-6
8204 056 07160 IC SM NW700LQ TQFP160
9322 179 31671 IC SM NW700
9352 424 20118 IC SM 74LVC04APW
(PHSE) R
9352 351 50118 IC SM 74LVC16244ADGG
(PHSE) R
9352 668 39118 IC SM UDA1334ATS/N2
(PHSE) R
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.4 Linearized : Yes Encryption : Standard V1.2 (40-bit) User Access : Print, Annotate, Fill forms, Extract, Assemble, Print high-res Modify Date : 2005:03:07 13:20:45+01:00 Create Date : 2002:01:17 15:04:26Z Page Count : 335 About : uuid:3a5706af-8eef-11d9-8b4e-00805f652af6 Producer : Acrobat Distiller 4.05 for Windows Creation Date : 2002:01:17 15:04:26Z Mod Date : 2005:03:07 13:20:45+01:00 Author : nly92116 Metadata Date : 2005:03:07 13:20:45+01:00 Creator Tool : FrameMaker+SGML 5.5.6p145 Document ID : uuid:3a5706ac-8eef-11d9-8b4e-00805f652af6 Format : application/pdf Creator : nly92116 Title : Acrobat Distiller, Job 9 Page Mode : UseOutlines Page Layout : SinglePageEXIF Metadata provided by EXIF.tools