La 4102p_dis_1008 HP DV4 CQ40 CQ45 INTEL DISCRETE COMPAL 4102P REV 0.1
1HP DV4 CQ40 CQ45 - INTEL DISCRETE - COMPAL LA-4102P - REV 0.1
HP DV4 CQ40 CQ45 - INTEL DISCRETE - COMPAL LA-4102P - REV 0.1
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A B C D E 1 1 Compal confidential Schematics Document Mobile Penryn uFCPGA with Intel Cantiga_PM+ICH9-M core logic 2 2 2007-09-16 3 4 4 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. Cover Sheet Size Document Number Custom Montevina Consumer Date: discrete ai 2007/09/26 Deciphered Date Sheet Friday, October 05, 2007 E he x 2007/09/26 nf @ ho tm Compal Secret Data Security Classification Issued Date ai l.c om 3 1 of Rev 0.1 51 A B C D Montevina Consumer Discrete Compal confidential CK505 1 Thermal Sensor EMC1402 VRAM DDR2 128/512MB P6,7, 8 64bits Dock connecter P6 H_A#(3..35) Discrete Nvidia NB9M-GE FSB 667/800/1066 MHz 1.05V H_D#(0..63) DDR2 667MHz 1.8V P20,21,22 Intel Cantiga MCH DDR2 SO-DIMM X2 BANK 0, 1, 2, 3 CRT 2 P40 Dual Channel USB conn x3 2 DMI X4 Support V1.3 BT Conn C-Link USB Camera New Card WLAN & Robson P30 P31 P19 Azalia Intel ICH9-M Mini-Card*2 P36 P42 PCI-E BUS*5 Mavell 88E8072(Gbe) P36 P18 USB2.0 X12 HDMI P15, 16 FCBGA 1329 P19 P9, 10, 11, 12, 13, 14 CRT 1 P17 uFCPGA-478 CPU P6 Fan conn LVDS Panel Interface 72QFN Clock Generator SLG8SP553V Mobile Penryn page 23,24 TV out E SATA Master-1 SATA Slave mBGA-676 Flash Memory Card Controller SATA Slave Audio CKT AMP & Audio Jack Codec_IDT9271B7 TPA6017A2 P25,26,27,28 P33 P35 P31 JMB385 MDC P32 RJ45/11 CONN LPC BUS P30 3 P34 SATA HDD Connector 3 P29 LED 5 in1 Slot P39 ENE KB926 P32 RTC CKT. SATA ODD Connector P29 P38 P26 FPR Conn e-SATA Connector With 3'th USB Int.KBD Touch Pad CONN. P39 Dock P29 P40 P38 SPI SPI ROM 25LF080A Power On/Off CKT. CIR Conn P35 P37 Capsense switch Conn 4 4 P39 DC/DC Interface CKT. Touch Screen Conn Compal Secret Data Security Classification P41 2007/09/26 Issued Date 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. Block Diagram Size Document Number Custom Montevina Consumer Date: Rev 0.1 Discrete Sheet Friday, October 05, 2007 E 2 of 51 A Voltage Rails X MEANS OFF O MEANS ON Symbol Note : : means Digital Ground +5VS +3VS power plane : means Analog Ground +1.5VS +0.9V +5VALW +B @ : means just reserve , no build DEBUG@ : means just reserve for debug. +VCCP +1.8V +CPU_CORE +3VALW +2.5VS +1.8VS +NVVDD State +PCIE USB assignment: USB-0 Right side USB-1 Right side S0 O O O O S1 O O O O S3 O O O X S5 S4/AC O O X X S5 S4/ Battery only O X X X S5 S4/AC & Battery don't exist X X X X USB-2 Left side(with ESATA) USB-3 Dock USB-4 Camera USB-5 WLAN USB-6 Bluetooth USB-7 Finger Printer USB-8 MiniCard(WWAN/TV) USB-9 Express card USB-10 X USB-11 X PCIe assignment: 1 1 PCIe-1 TV tuner/WWAN/Robeson PCIe-2 X PCIe-3 WLAN SMBUS Control Table SOURCE SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 SMB_CK_CLK1 SMB_CK_DAT1 INVERTER BATT SERIAL EEPROM Thermal Sensor PCIe-4 New Card NB9M SODIMM CLK CHIP MINI CARD Sensor board Thermal Sensor PCIe-5 Card reader NB9M KB926 X V V X X X X X X X KB926 X X X V X X X V V V ICH9 X X X X V V V X X X PCIe-6 GLAN (Marvell) NB9M SMBUS Control Table SOURCE LVDS CRT V X X NB9M X V X NB9M X X V DDC2_DATA DDC2_CLK 3VDDCDA 3VDDCCL HDMIDAT_VGA HDMICLK_VGA NB9M HDMI A0 10100000 DDR SO-DIMM 1 A4 10100100 CLOCK GENERATOR (EXT.) D2 11010010 ai DDR SO-DIMM 0 Compal Secret Data Security Classification 2007/09/26 Issued Date Deciphered Date 2007/09/26 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A Title Compal Electronics, Inc. Notes List Size Document Number Custom Montevina Consumer Date: nf @ ho tm ADDRESS Friday, October 05, 2007 Discrete Rev 0.1 ai HEX he x DEVICE l.c om I2C / SMBUS ADDRESSING Sheet 3 of 51 5 4 3 2 1 50mA 50mA 177mA 1A D +V_BATTERY ICH9 Dock con AC 1A +3VALW_EC 10mA VIN 1.7A 2A 1A +3VAUX_BT 20mA LVDS CON 35mA LAN 60mA INVPWR_B+ 278mA SPI ROM 5.89A +3VALW 5.39A 550mA B++ +3VS 1.5A 657mA C +1.5VS ICH_VCC1_5 ICH9 2.2A 1.56A +5VALW MDC 1.5 New card Mini card (WLAN) ICH9 +LCDVDD LVDS CON +3VS_CK505 C 390mA NB9M (VGA) ICH9 1A 0.58A +3VS_DVDD ALC268 JMB385 250mA 0.3A PC Camera D 300mA 0.3A 25mA Finger printer 35mA 1.3A +5VS Mini card (TV tu/WWAN/Robeson) +VDDA IDT 9271B7 B+ 7A 10mA 360mA 1.8A NB9M (VGA) +5VAMP ODD B B 3.7A 3.7 X 3=11.1V DC 700mA MCH SATA BATT 1.9A B+++ 12.11A 8 A +1.8V DDR2 50mA 800Mhz 1.05V_B+ 1.26A +VCCP 2.3A 2A CPU_B+ 10mA +VCC_CORE 34A/1.025V Muti Bay +0.9V 1.17A 4.7A 1.8A 4G x2 ICH9 MCH CPU CPU A A 0.27A 0.19A 2.725A +NVVDDP +NVVDD +1.1V_PCIE +PCIE NB9M (VGA) 2A/1.1V Compal Secret Data Security Classification NB9M (VGA) Issued Date 2007/09/26 Deciphered Date 2007/09/26 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Power delivery Size C Date: Document Number Rev 0.1 Montevina Consumer UMA Friday, October 05, 2007 Sheet 1 4 of 51 A 1 Compal Secret Data Deciphered Date 2007/09/26 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A Title Compal Electronics, Inc. Notes List Size Document Number Custom Montevina Consumer Date: Friday, October 05, 2007 UMA Rev 0.1 ai 2007/09/26 Issued Date he x Security Classification nf @ ho tm ai l.c om 1 Sheet 5 of 51 5 4 3 2 1 +3VS ITP-XDP Connector @ R1 1 XDP_DBRESET#_R 2 1K_0402_5% +VCCP Change value in 5/02 JP1 XDP_BPM#5 XDP_BPM#4 D XDP_BPM#3 XDP_BPM#2 XDP_BPM#1 XDP_BPM#0 JCPU1A 9 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#[17..35] 26 26 26 26 H_STPCLK# H_INTR H_NMI H_SMI# H_A20M# H_FERR# H_IGNNE# A6 A5 C4 H_STPCLK# H_INTR H_NMI H_SMI# D5 C6 B4 A3 M4 N5 T2 V3 B2 D2 D22 D3 F6 B DEFER# DRDY# DBSY# CONTROL BR0# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# H1 E2 G5 H_ADS# H_BNR# H_BPRI# H5 F21 E1 H_DEFER# H_DRDY# H_DBSY# F1 H_BR0# D20 B3 H_IERR# H_INIT# H4 H_LOCK# PROCHOT# THERMDA THERMDC THERMTRIP# 9 9 9 H_BR0# 7,26 9 H_INIT# H_HIT# H_HITM# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET# H_THERMDA_R H_THERMDC_R C7 H_THERMTRIP# A22 A21 CLK_CPU_BCLK CLK_CPU_BCLK# 2 C1 Place TP with a 0.1" away 9GND H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# 9 9 9 9 9 H_HIT# H_HITM# H_PROCHOT# +VCCP 26 H_LOCK# R9 1K_0402_5% 2 1H_PWRGOOD_R XDP_HOOK1 H_PWRGOOD T1 G6 E4 D21 A24 B25 9 9 9 H_DEFER# H_DRDY# H_DBSY# H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# H CLK BCLK[0] BCLK[1] H_ADS# H_BNR# H_BPRI# C1 F3 F4 G3 G2 THERMAL STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] LOCK# HIT# HITM# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# A20M# FERR# IGNNE# IERR# INIT# RESET# RS[0]# RS[1]# RS[2]# TRDY# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# ICH H_A20M# H_FERR# H_IGNNE# Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 ADS# BNR# BPRI# ADDR GROUP_1 H_ADSTB#1 26 26 26 K3 H2 K2 J3 L1 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1 C 9 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# 1 0.1U_0402_16V4Z Removed at 5/30.(Follow Chimay) XDP_TCK GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 R2 1 2 54.9_0402_1% XDP_TMS R3 1 2 54.9_0402_1% XDP_TDO R4 1 2 54.9_0402_1% XDP_BPM#5 R5 1 2 54.9_0402_1% XDP_HOOK1 R6 1 2 @ 54.9_0402_1% XDP_TRST# R7 1 2 54.9_0402_1% XDP_TCK R8 1 2 54.9_0402_1% D This shall place near CPU CLK_CPU_XDP CLK_CPU_XDP# CONN@SAMTE_BSH-030-01-L-D-A CLK_CPU_XDP CLK_CPU_XDP# +VCCP H_RESET#_R XDP_DBRESET#_R R10 R11 XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_PRE R12 0_0402_5% 2 1 1 2 2 1K_0402_1% 1 200_0402_1% 17 17 H_RESET# XDP_DBRESET# Place R191 within 200ps (~1") to CPU 9 9 C +3VS XDP_DBRESET# R13 R14 R15 2 49.9_0402_1% 1 2 100_0402_5% 2 100_0402_5% 1 1 H_THERMTRIP# CLK_CPU_BCLK CLK_CPU_BCLK# 0.1U_0402_16V4Z 9 9 9 9 9 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 XDP/ITP SIGNALS H_ADSTB#0 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0 ADDR GROUP_0 9 H_A#[3..16] 27 +VCCP H_THERMDA H_THERMDC C3 1 9,26 +3VS 17 17 1 C2 U1 2 1 H_THERMDA 2 H_THERMDC 2 2200P_0402_50V7K THERM# 3 For Merom, R1798 and R1799 are 0ohm For Penryn, R1798 and R1799 are 100ohm. VDD 4 R16 1 2 10K_0402_5% SMCLK DP SMDATA DN ALERT# THERM# GND 8 SMB_EC_CK2 7 SMB_EC_DA2 SMB_EC_CK2 21,38 SMB_EC_DA2 21,38 6 5 EMC1402-1-ACZL-TR_MSOP8 Address:100_1100 H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil RESERVED 9 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 XDP_TDI B PWM Fan Control circuit +5VS Penryn JP2 1 D1 RB751V_SOD323 C4 4.7U_0805_10V4Z 2 @ R17 56_0402_5% 1 C5 0.1U_0402_16V4Z 1 2 G1 G2 ACES_85204-02001 2 2 1 1 2 3 4 1 +VCCP D Q2 E OCP# @ D2 G 27 38 RLZ5.1B_LL34 3 FAN_PWM S SI3456BDV-T1-E3_TSOP6 4 C OCP# 3 1 @ Q1 MMBT3904_NL_SOT23-3 2 H_PROCHOT# 1 B 1 2 5 6 2 2 +FAN +VCCP A A 2 ZZZ1 R18 56_0402_5% 1 PCB Compal Secret Data Security Classification H_IERR# 2007/09/26 Issued Date 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Penryn(1/3)-AGTL+/ITP-XDP Size Document Number Custom Montevina Consumer Date: Rev 0.1 Discrete Sheet Friday, October 05, 2007 1 6 of 51 4 3 2 1 +VCC_CORE 2 1K_0402_5% 2 1K_0402_5% T2 T3 T4 T5 T6 17 17 17 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2] MISC DATA GRP 2 +V_CPU_GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 COMP[0] COMP[1] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 R26 U26 AA1 Y1 COMP0 COMP1 COMP2 COMP3 E5 B5 D24 D6 D7 AE6 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI# Penryn * Route the TEST3 and TEST5 signals through a ground referenced Zo = 55-ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection. B CPU_BSEL CPU_BSEL2 CPU_BSEL1 0 1 1 200 0 1 0 266 0 0 0 9 9 9 9 H_DSTBN#3 H_DSTBP#3 H_DINV#3 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI# 9 9 9 9,26,49 26 9 6,26 9 49 R23 R24 R25 R26 Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils. CPU_BSEL0 166 H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_D#[48..63] JCPU1C A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] D +VCCP R19 G21 +VCCPA +VCCPB V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] 1 1 2 2 0_0402_5% 0_0402_5% C R20 1 + C6 330U_D2E_2.5VM_R7 2 B26 C26 VCCA[01] VCCA[02] +1.5VS AD6 AF5 AE5 AF4 AE3 AF3 AE2 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 49 49 49 49 49 49 49 AF7 VCCSENSE VCCSENSE 49 AE7 VSSSENSE VSSSENSE 49 1 C7 2 0.01U_0402_16V7K 1 1 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# +VCC_CORE 9 27.4_0402_1% 2 1 @ R21 @ R22 H_DSTBN#1 H_DSTBP#1 H_DINV#1 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2 54.9_0402_1% 2 1 9 9 9 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 DATA GRP 1 C H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 27.4_0402_1% 2 1 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[16..31] E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 DATA GRP 0 D 9 9 9 9 H_D#[32..47] JCPU1B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 54.9_0402_1% 2 1 H_D#[0..15] DATA GRP 3 9 10U_0805_6.3V6M 5 1 C8 2 Near pin B26 B Penryn . Length match within 25 mils. The trace width/space/other is 20/7/25. 1 +VCCP R27 1K_0402_1% 2 +VCC_CORE 1 +V_CPU_GTLREF R28 1 2 100_0402_1% VCCSENSE R30 1 2 100_0402_1% VSSSENSE 2 R29 2K_0402_1% Close to CPU pin within 500mils. Close to CPU pin AD26 within 500mils. A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Penryn(2/3)-AGTL+/ITP-XDP Size Document Number Custom Montevina Consumer Date: Discrete ai 2007/09/26 Deciphered Date Sheet Monday, October 08, 2007 1 he x 2007/09/26 nf @ ho tm Compal Secret Data Security Classification Issued Date ai l.c om A 7 of Rev 0.1 51 5 4 3 2 1 +VCC_CORE 5 1 Place these capacitors on L8 (North side,Secondary Layer) 2 1 C9 10U_0805_6.3V6M 2 1 C10 10U_0805_6.3V6M 2 1 C11 10U_0805_6.3V6M 2 1 C12 10U_0805_6.3V6M 2 1 C13 10U_0805_6.3V6M 2 C14 10U_0805_6.3V6M 1 2 1 C15 10U_0805_6.3V6M 2 C16 10U_0805_6.3V6M D D +VCC_CORE JCPU1D C B A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] 5 P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] 1 Place these capacitors on L8 (North side,Secondary Layer) 2 1 C17 10U_0805_6.3V6M 2 1 C18 10U_0805_6.3V6M 2 1 C19 10U_0805_6.3V6M 2 1 C20 10U_0805_6.3V6M 2 1 C21 10U_0805_6.3V6M 2 C22 10U_0805_6.3V6M 1 2 1 C23 10U_0805_6.3V6M 2 C24 10U_0805_6.3V6M +VCC_CORE 5 1 Place these capacitors on L8 (North side,Secondary Layer) 2 1 C25 10U_0805_6.3V6M 2 1 C26 10U_0805_6.3V6M 2 1 C27 10U_0805_6.3V6M 2 1 C28 10U_0805_6.3V6M 2 1 C29 10U_0805_6.3V6M 2 C30 10U_0805_6.3V6M 1 2 1 C31 10U_0805_6.3V6M 2 C32 10U_0805_6.3V6M +VCC_CORE 5 1 Place these capacitors on L8 (North side,Secondary Layer) 2 1 C33 10U_0805_6.3V6M 2 1 C34 10U_0805_6.3V6M 2 1 C35 10U_0805_6.3V6M 2 1 C36 10U_0805_6.3V6M 2 1 C37 10U_0805_6.3V6M 2 C38 10U_0805_6.3V6M 1 2 1 C39 10U_0805_6.3V6M 2 C40 10U_0805_6.3V6M C Mid Frequence Decoupling ESR <= 1.5m ohm Capacitor > 1980uF Near CPU CORE regulator +VCC_CORE 330U_D2E_2.5VM_R7 1 C41 330U_D2E_2.5VM_R7 1 + C42 2 + 1 + @ C43 2 + 2 330U_D2E_2.5VM_R7 +VCCP 1 C44 2 B 330U_D2E_2.5VM_R7 Inside CPU center cavity in 2 rows 5 1 2 C45 0.1U_0402_10V6K 1 2 C46 0.1U_0402_10V6K 1 2 1 C47 0.1U_0402_10V6K 2 1 C48 0.1U_0402_10V6K 2 1 C49 0.1U_0402_10V6K 2 C50 0.1U_0402_10V6K Penryn . A A Compal Secret Data Security Classification 2007/09/26 Issued Date 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Penryn(3/3)-AGTL+/ITP-XDP Size Document Number Custom Montevina Consumer Date: Rev 0.1 Discrete Sheet Monday, October 08, 2007 1 8 of 51 PM_EXTTS#1 R39 1 2 10K_0402_5% CLKREQ#_7 R40 1 2 10K_0402_5% 6 6 6 PLT_RST# PLT_RST# H_THERMTRIP# DPRSLPVR 27 7,26,49 15 16 27,38 R41 R42 1 1 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_PWROK 2 2 100_0402_5% 0_0402_5% Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20. PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_PWROK THERMTRIP# DPRSLPVR 1 @ C55 2 +1.8V 1 2 1 V_DDR_MCH_REF R55 1 C59 1 2 R48 1K_0402_1% C57 2 221_0603_1% 2 1 V_DDR_MCH_REF +H_SWNG 2 R29 B7 N33 P32 AT40 AT11 T20 R32 BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47 PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4 GFX_VR_EN CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF BG22 BH21 SMRCOMP SMRCOMP# BF28 BH28 SMRCOMP_VOH SMRCOMP_VOL AV42 AR36 BF17 BC36 V_DDR_MCH_REF SM_PWROK SM_REXT TP_SM_DRAMRST# 15 15 16 16 M_ODT0 M_ODT1 M_ODT2 M_ODT3 R34 R35 15 15 16 16 +1.8V 2 80.6_0402_1% 2 80.6_0402_1% 1 1 Follow Design Guide For Cantiga: 80.6ohm R36 R37 2 0_0402_5% 2 499_0402_1% 1 1 T29 PAD B38 A38 E41 F41 F43 E43 CLK_MCH_3GPLL CLK_MCH_3GPLL# AE41 AE37 AE47 AH39 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 AE40 AE38 AE48 AH40 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 AE35 AE43 AE46 AH42 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 AD35 AE44 AF46 AH43 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 CLK_MCH_3GPLL CLK_MCH_3GPLL# 17 17 B33 B32 G33 F33 E33 T30 T31 T32 T33 T34 C34 T35 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 27 27 27 27 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 27 27 27 27 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 27 27 27 27 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 27 27 27 27 B +VCCP AH37 AH36 AN36 AJ35 AH34 CL_CLK0 CL_DATA0 M_PWROK CL_RST# +CL_VREF CL_CLK0 CL_DATA0 M_PWROK CL_RST# 27 27 27,38 27 0621 add CLK and DAT for DVI DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# TSATN# HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC N28 M28 G36 E36 K36 H36 CLKREQ#_7 MCH_ICH_SYNC# B12 TSATN# T36 T37 R43 1K_0402_1% 1 C56 0.1U_0402_16V4Z R44 499_0402_1% 2 CLKREQ#_7 MCH_ICH_SYNC# TSATN# 17 27 *R37*Follow Intel feedback 38 B28 B30 B29 C29 A28 A CANTIGA ES_FCBGA1329 Near B3 pin 2007/09/26 Issued Date 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 M_ODT0 M_ODT1 M_ODT2 M_ODT3 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# C DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 BD17 AY17 BF15 AY13 Compal Secret Data Security Classification within 100 mils from NB PEG_CLK PEG_CLK# DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# D ai 2 R54 15,16 0.1U_0402_16V4Z C58 R47 0.1U_0402_16V4Z 1 H_RCOMP 100_0402_1% 2 1 R52 0.1U_0402_16V4Z 1 2K_0402_1% 2 A +H_VREF 24.9_0402_1% 2 1 1K_0402_1% 1 2 R46 R45 1K_0402_1% T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28 NC +VCCP +VCCP DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 6 6 6 6 6 H_RS#0 H_RS#1 H_RS#2 SM_VREF SM_PWROK SM_REXT SM_DRAMRST# DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 0.1U_0402_16V4Z Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20 2 10K_0402_5% PM Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces 1 SM_RCOMP_VOH SM_RCOMP_VOL BA17 AY16 AV16 AR13 15 15 16 16 om 7 7 7 7 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 R38 SM_RCOMP SM_RCOMP# CLK 17 17 CANTIGA ES_FCBGA1329 20,25,30,31,32 6,26 27,49 1 +3VS PM_EXTTS#0 SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 DMI H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 RESERVED RESERVED RESERVED RESERVED SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB l.c 2 RESERVED R33 1K_0402_1% 17 17 17 7 7 7 7 T25 T26 T27 T28 BG23 BF23 BH18 BF18 DDR CLK/ CONTROL/COMPENSATION 2 2 7 7 7 7 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 AY21 2 1 1 2 1 H_AVREF H_DVREF Layout note: 1 C52 H_RS#0 H_RS#1 H_RS#2 0.01U_0402_25V7K B6 F12 C8 2.2U_0603_6.3V4Z C51 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 T24 RESERVED RESERVED RESERVED DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB 15 15 16 16 1 A11 B11 B15 K13 F13 B13 B14 H_ADS# 6 H_ADSTB#0 6 H_ADSTB#1 6 H_BNR# 6 H_BPRI# 6 H_BR0# 6 H_DEFER# 6 H_DBSY# 6 CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# 7 H_DRDY# 6 H_HIT# 6 H_HITM# 6 H_LOCK# 6 H_TRDY# 6 T21 T22 T23 BC28 AY28 AY36 BB36 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 2 +H_VREF H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 SMRCOMP_VOL M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 15 15 16 16 1 B L9 M8 AA6 AE5 20% of 1.8V VCC_SM B31 B2 M1 AR24 AR21 AU24 AV20 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 2 H_RS#_0 H_RS#_1 H_RS#_2 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 R32 3.01K_0402_1% SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 4 3 2 Title Compal Electronics, Inc. nf @ ho tm H_CPURST# H_CPUSLP# L10 M7 AA5 AE6 80% of 1.8V VCC_SM SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 AP24 AT21 AV24 AU20 Cantiga(1/6)-AGTL/DMI/DDR Size Document Number Custom Montevina Consumer Date: Discrete ai H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 2 SMRCOMP_VOH SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 Sheet Monday, October 08, 2007 1 he x H_SWING H_RCOMP J8 L3 Y13 Y1 2 R31 1K_0402_1% RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GRAPHICS VID C12 E11 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# 1 M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 ME H_RESET# H_CPUSLP# H_RESET# H_CPUSLP# H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9 1 +1.8V T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 MISC 6 C5 E3 H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 CFG +H_SWNG H_RCOMP H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 1 HDA C H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 C54 D F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 RSVD H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 2 U2B 6 2.2U_0603_6.3V4Z C53 U2A H_D#[0..63] 7 3 H_A#[3..35] HOST 7 4 0.01U_0402_25V7K 5 9 of Rev 0.1 51 5 4 3 2 1 D D B DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 BB20 BD20 AY20 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 15 15 15 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# 15 15 15 DDR_A_DM[0..7] SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 DDR_A_DQS[0..7] 15 15 DDR_A_DQS#[0..7] DDR_A_MA[0..14] DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 15 15 CANTIGA ES_FCBGA1329 AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_WE# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 B SA_RAS# SA_CAS# SA_WE# BD21 BG18 AT25 U2E MEMORY SA_BS_0 SA_BS_1 SA_BS_2 A SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 MEMORY C AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12 SYSTEM DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D[0..63] SYSTEM 16 U2D SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 DDR DDR_A_D[0..63] DDR 15 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 BC16 BB17 BB33 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AU17 BG16 BF14 DDR_B_RAS# DDR_B_CAS# DDR_B_WE# AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 16 16 16 DDR_B_RAS# DDR_B_CAS# DDR_B_WE# 16 16 16 DDR_B_DM[0..7] 16 DDR_B_DQS[0..7] 16 DDR_B_DQS#[0..7] 16 DDR_B_MA[0..14] C 16 B CANTIGA ES_FCBGA1329 A A Compal Secret Data Security Classification 2007/09/26 Issued Date 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Cantiga(2/6)-DDR2 A/B CH Size Document Number Custom Montevina Consumer Date: Rev 0.1 Discrete Sheet Friday, October 05, 2007 1 10 of 51 4 3 2 1 U2C H47 E46 G40 A40 H48 D45 F40 B40 A41 H38 G37 J37 B42 G38 F37 K37 C H24 C31 E32 E28 G28 G29 H32 J32 J29 E29 L29 L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3 TVA_DAC TVB_DAC TVC_DAC TV_RTN TV_DCONSEL_0 TV_DCONSEL_1 CRT_BLUE CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC VGA J28 L_CTRL_DATA L_DDC_CLK L_DDC_DATA TV F25 H25 K25 PEG_COMPI PEG_COMPO LVDS M29 C44 B43 E37 E38 C41 C40 B37 A37 D L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK GRAPHICS M33 K33 J33 Strap Pin Table PCI-EXPRESS L32 G32 M32 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 +VCC_PEG R57 1 2 49.9_0402_1% T37 T36 PEGCOMP trace width and spacing is 20/25 mils. H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 C1289 C1290 C1291 C1292 C1293 C1294 C1295 C1296 C1297 C1298 C1299 C1300 C1301 C1302 C1303 C1304 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z PEG_M_TXN0 PEG_M_TXN1 PEG_M_TXN2 PEG_M_TXN3 PEG_M_TXN4 PEG_M_TXN5 PEG_M_TXN6 PEG_M_TXN7 PEG_M_TXN8 PEG_M_TXN9 PEG_M_TXN10 PEG_M_TXN11 PEG_M_TXN12 PEG_M_TXN13 PEG_M_TXN14 PEG_M_TXN15 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46 PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15 C1305 C1306 C1307 C1308 C1309 C1310 C1311 C1312 C1313 C1314 C1315 C1316 C1317 C1318 C1319 C1320 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z PEG_M_TXP0 PEG_M_TXP1 PEG_M_TXP2 PEG_M_TXP3 PEG_M_TXP4 PEG_M_TXP5 PEG_M_TXP6 PEG_M_TXP7 PEG_M_TXP8 PEG_M_TXP9 PEG_M_TXP10 PEG_M_TXP11 PEG_M_TXP12 PEG_M_TXP13 PEG_M_TXP14 PEG_M_TXP15 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved CFG[2:0] FSB Freq select CFG[4:3] Reserved CFG5 (DMI select) 0 = DMI x 2 1 = DMI x 4 D * 0 = The iTPM Host Interface is enable CFG6 1 = The iTPM Host Interface is disable CFG7 (Intel Management Engine Crypto strap) * 0 =(TLS)chiper suite with no confidentiality 1 =(TLS)chiper suite with confidentiality CFG8 Reserved CFG9 (PCIE Graphics Lane Reversal) 0 = Reverse Lane,15->0, 14->1 CFG10 (PCIE Lookback enable) CFG11 0 = Enable 1 = Normal Operation,Lane Number in order 1 = Disable * * * Reserved CFG[13:12] (XOR/ALLZ) 00 01 10 11 = Reserved = XOR Mode Enabled = All Z Mode Enabled = Normal Operation CFG[15:14] Reserved CFG16 (FSB Dynamic ODT) 0 = Disabled 1 = Enabled CFG[18:17] Reserved CFG19 (DMI Lane Reversal) 0 = Normal Operation (Lane number in Order) (Default) * C * * 1 = Reverse Lane 0 = Only PCIE or SDVO is operational. CFG20 (PCIE/SDVO concurrent) 1 = PCIE/SDVO are operating simu. * +3VS 1 5 +3VS R71 4.02K_0402_1% CANTIGA ES_FCBGA1329 B CFG5 CFG5 9 CFG16 9 CFG19 1 9 2 B 9 CFG20 9 CFG11 1 2 4.02K_0402_1% @ R73 1 2 4.02K_0402_1% @R75 @ R75 1 2 4.02K_0402_1% @R76 @ R76 1 2 2.21K_0402_1% R77 1 2 2.21K_0402_1% 2 @ R74 2.21K_0402_1% R72 CFG6 9 CFG7 9 CFG8 9 CFG9 9 CFG10 @R79 @ R79 R81 1 2 2.21K_0402_1% 1 2 2.21K_0402_1% CFG12 9 CFG13 9 CFG14 9 CFG15 1 2 2.21K_0402_1% 9 CFG17 1 2 2.21K_0402_1% 9 CFG18 @R83 @ R83 1 2 2.21K_0402_1% @R84 @ R84 @R86 @ R86 R78 1 2 2.21K_0402_1% @R80 @ R80 1 2 2.21K_0402_1% @R82 @ R82 1 2 2.21K_0402_1% @R85 @ R85 1 2 2.21K_0402_1% @R87 @ R87 1 2 2.21K_0402_1% A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Cantiga(3/6)-VGA/LVDS/TV Size Document Number Custom Montevina Consumer Date: Discrete ai 2007/09/26 Deciphered Date Sheet Monday, October 08, 2007 1 he x 2007/09/26 nf @ ho tm Compal Secret Data Security Classification Issued Date ai l.c om A 9 9 11 of Rev 0.1 51 5 4 3 2 1 +VCCP +VCCP +V1.05VS_AXF U2H R93 C82 C81 VTT C80 CRT PLL A LVDS AXF SM CK A CK 60.31mA PEG DMI 1 2 +1.8V_SM_CK 2 + C100 2 10U_0805_10V4Z +1.05VS_PEGPLL K47 1 2 +1.05VS_DMI +VCCP L1 +3VS_HV C35 B35 A35 V48 U48 V47 U47 U46 +VCC_PEG AH48 AF48 AH47 AG47 +1.05VS_DMI 1 2 1 2 1 +VCCP R104 1 2 1 BLM18PG121SN1D_0603 2 0_0603_5% 1 2 2 B +VCCP_D 456mA VTTLF VTTLF VTTLF D3 A8 L1 AB2 +VCCP 2 R105 1 R106 1 2 1 10_0402_5% 2 +3VS_HV 0_0402_5% CH751H-40PT_SOD323-2 2 1 2 0.47U_0603_10V7K C112 1 0.47U_0603_10V7K C111 0.47U_0603_10V7K C110 CANTIGA ES_FCBGA1329 VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_DMI VCC_DMI VCC_DMI VCC_DMI VTTLF 50mA VCCD_LVDS VCCD_LVDS VCC_HV VCC_HV VCC_HV HV TV HDA 157.2mA BF21 BH20 BG20 BF20 1 1 118.8mA VCC_TX_LVDS D TV/CRT 48.363mA VCCD_PEG_PLL VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK 1732mA LVDSM38 L37 VCCD_HPLL C99 124mA 2 0_0805_5% 2 MBK2012121YZF_0805 0.1U_0402_16V4Z C109 AA47 VCCD_QDAC R102 1 1 +V1.05VS_AXF 0.1U_0402_16V4Z 105.3mA 58.67mA B22 B21 A21 C108 +1.05VS_PEGPLL AF1 VCC_AXF VCC_AXF VCC_AXF 10U_0805_10V4Z +1.05VS_HPLL VCCD_TVDAC +VCCP +VCCP C106 L28 B 50mA 2 +VCC_PEG 0.1U_0402_16V4Z M25 VCC_HDA 1 R101 C107 +1.5VS_TVDAC A32 2 +1.05VS_MPLL 0.1U_0402_16V4Z +1.5VS 1 C TVA 24.15mA TVB 39.48mA TVX 24.15mA VCCA_TV_DAC VCCA_TV_DAC 2 2 0_0805_5% 10U_0805_10V4Z B24 A24 1 1 0.1U_0402_16V4Z 2 1 2 VCCA_SM_CK VCCA_SM_CK 26mA VCCA_SM_CK VCCA_SM_CK 26mA VCCA_SM_CK VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF +1.5VS C101 2 1 2 R99 C98 2 1 C105 2 1 C104 1 C103 1U_0603_10V4Z +1.05VS_A_SM_CK 10U_0805_10V4Z C102 POWER 321.35mA AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23 1 +1.5VS_TVDAC +VCCP 2 MBK2012121YZF_0805 2 0.1U_0402_16V4Z 2 0_0603_5% 2 720mA C97 1U_0603_10V4Z 1U_0603_10V4Z 1 4.7U_0805_10V4Z 1 2 0_0805_5% R98 1 220U_D2_4VM R103 2 1 C96 2 C93 2 1 2 1 C92 C95 C94 + 1 10U_0805_10V4Z 2 0_0805_5% 1 10U_0805_10V4Z 1 C VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM +1.05VS_HPLL C91 +1.05VS_A_SM R100 VCCA_PEG_PLL C90 +VCCP AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16 @ 0.022U_0402_16V7K 0.1U_0402_16V4Z AA48 A SM +1.05VS_PEGPLL C89 0.1U_0402_16V4Z 2 220U_D2_4VM A PEG 50mA 1 +1.8V R95 1 C85 2 0_0603_5% 2 +1.8V_SM_CK VCCA_PEG_BG R97 1 +1.5VS 2 0.1U_0402_16V4Z AD48 +1.5VS_PEG_BG 0_0603_5% 1 C79 2 0_0603_5% 1U_0603_10V4Z VSSA_LVDS 414uA 1 +3VS VCCA_LVDS 2 1 10U_0805_10V4Z J47 @ R96 2 2 C84 139.2mA VCCA_MPLL 13.2mA J48 1 C78 VCCA_HPLL 1 10U_0805_10V4Z 24mA C83 AE1 64.8mA 1 2 D 10U_0805_10V4Z +1.05VS_MPLL VCCA_DPLLB 2 2.2U_0805_16V4Z AD1 64.8mA 1 4.7U_0805_10V4Z L48 +1.05VS_HPLL VCCA_DPLLA 2 0.47U_0603_10V7K F47 + C72 D VCCA_DAC_BG VSSA_DAC_BG 1 4.7U_0805_10V4Z 2.68mA A25 B25 U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1 C71 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VCCA_CRT_DAC VCCA_CRT_DAC 220U_D2_4VM 852mA 73mA B27 A26 1 +3VS 1 2 A A Compal Secret Data Security Classification 2007/09/26 Issued Date 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Cantiga(4/6)-PWR Size Document Number Custom Montevina Consumer Date: Rev 0.1 Discrete Friday, October 05, 2007 Sheet 1 12 of 51 5 4 3 2 1 U2G 3000mA AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23 VCC SM POWER VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC 6326.84mA Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14 VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG CANTIGA ES_FCBGA1329 1 1 2 1 2 1U_0603_10V4Z 2 1U_0603_10V4Z 2 C145 1 0.47U_0402_6.3V6K 2 C144 1 C143 2 0.22U_0603_10V7K A 1 0.22U_0603_10V7K 2 C142 1 C141 AV44 VCCSM_LF1 BA37 VCCSM_LF2 AM40 VCCSM_LF3 AV21 VCCSM_LF4 AY5 VCCSM_LF5 AM10 VCCSM_LF6 BB13 VCCSM_LF7 0.1U_0402_16V4Z VCC_AXG_SENSE VSS_AXG_SENSE VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF 0.1U_0402_16V4Z AJ14 AH14 C C140 T42 T43 D C139 PAD PAD W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16 B VCC SM LF B VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF 1 VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC GFX NCTF VCC 2 BA36 BB24 BD16 BB21 AW16 AW13 AT13 +VCCP VCC NCTF T32 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 2 0317 change value POWER AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23 2 1 VCC CORE 2 2 1 C123 1 + 0.01U_0402_16V7K C130 2 1 10U_0805_10V4Z C122 1 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 10U_0805_10V4Z C126 2 C125 C 1 0.1U_0402_16V4Z C133 A 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Cantiga(5/6)-PWR/GND Size Document Number Custom Montevina Consumer Date: Discrete ai 2007/09/26 nf @ ho tm Compal Secret Data Security Classification Issued Date ai l.c om CANTIGA ES_FCBGA1329 Sheet Monday, October 08, 2007 1 he x 2 0.22U_0402_10V4Z C132 1 0.22U_0402_10V4Z C124 + 2 10U_0805_10V4Z C131 220U_D2_4VM 1 AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33 330U_D2E_2.5VM_R7 +VCCP D +1.8V U2F AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29 VCC GFX Extnal Graphic: 1210.34mA integrated Graphic: 1930.4mA 13 of Rev 0.1 51 5 4 3 2 1 U2J C B VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6 BA16 AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13 AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11 Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NCTF D VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SCB AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36 BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17 NC U2I VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4 D BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1 C U24 U28 U25 U29 AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17 B BH48 BH1 A48 C1 A3 E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48 CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329 A A Compal Secret Data Security Classification 2007/09/26 Issued Date 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Cantiga(6/6)-PWR/GND Size Document Number Custom Montevina Consumer Date: Rev 0.1 Discrete Sheet Friday, October 05, 2007 1 14 of 51 5 4 3 2 1 +1.8V 10 DDR_A_DQS#[0..7] 10 DDR_A_D[0..63] DDR_A_DQS#2 DDR_A_DQS2 2 DDR_A_D18 DDR_A_D19 DDR_A_D29 DDR_A_D24 DDR_A_DM3 DDR_A_D26 DDR_A_D27 Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS 9 DDR_CKE0_DIMMA 10 DDR_A_BS2 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 5 2 1 2 1 2 10 10 1 DDR_A_BS0 DDR_A_WE# 10 9 DDR_A_CAS# DDR_CS1_DIMMA# 9 DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_CS1_DIMMA# M_ODT1 M_ODT1 2 DDR_A_D37 DDR_A_D36 C170 C169 C168 C167 C166 C165 C164 C163 C162 C161 C160 C159 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 2 10 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z C158 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 +0.9V 1 DDR_CKE0_DIMMA DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D39 DDR_A_D38 DDR_A_D45 DDR_A_D44 B DDR_A_DM5 +0.9V 56_0404_4P2R_5% DDR_A_MA8 DDR_A_MA5 1 2 RP1 56_0404_4P2R_5% DDR_A_MA1 DDR_A_MA3 1 2 RP2 4 3 4 3 4 3 4 3 RP3 56_0404_4P2R_5% DDR_A_RAS# DDR_CS0_DIMMA# 1 2 56_0404_4P2R_5% DDR_A_BS0 DDR_A_MA10 1 2 RP4 RP5 4 3 4 3 4 3 4 3 Layout Note: Place these resistor closely JP3,all trace length Max=1.5" 56_0404_4P2R_5% 1 DDR_A_BS2 2 DDR_CKE0_DIMMA DDR_A_D47 DDR_A_D46 DDR_A_D49 DDR_A_D48 56_0404_4P2R_5% 1 DDR_A_MA7 2 DDR_A_MA6 RP6 56_0404_4P2R_5% 1 DDR_A_MA12 2 DDR_A_MA9 RP8 56_0404_4P2R_5% 1 DDR_A_MA4 2 DDR_A_MA2 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D54 DDR_A_D50 DDR_A_D61 DDR_A_D60 RP7 DDR_A_DM7 DDR_A_D59 DDR_A_D58 RP9 56_0404_4P2R_5% DDR_CS1_DIMMA# M_ODT1 2 1 RP10 4 3 4 3 3 4 4 3 RP11 RP12 RP13 DDR_A_MA11 1 R117 2 4 3 56_0404_4P2R_5% 1 DDR_A_MA0 2 DDR_A_BS1 16,17 16,17 CLK_SMBDATA CLK_SMBCLK +3VS 56_0404_4P2R_5% 1 M_ODT0 2 DDR_A_MA13 CLK_SMBDATA CLK_SMBCLK 56_0404_4P2R_5% 1 DDR_CKE1_DIMMA 2 DDR_A_MA14 56_0402_5% 1 1 C171 2 2 VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 M_CLK_DDR0 M_CLK_DDR#0 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 FOX_ASOA426-M4R-TR SO-DIMM A 2007/09/26 4 3 9 9 DDR_A_D20 DDR_A_D21 PM_EXTTS#0 DDR_A_DM2 9 DDR_A_D23 DDR_A_D22 DDR_A_D28 DDR_A_D25 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D31 DDR_A_D30 DDR_CKE1_DIMMA DDR_CKE1_DIMMA C 9 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 DDR_A_MA13 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 10 10 9 9 DDR_A_D32 DDR_A_D33 DDR_A_DM4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 B DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D43 DDR_A_D42 DDR_A_D52 DDR_A_D53 M_CLK_DDR1 M_CLK_DDR#1 M_CLK_DDR1 M_CLK_DDR#1 9 9 DDR_A_DM6 DDR_A_D51 DDR_A_D55 DDR_A_D57 DDR_A_D56 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 M_CLK_DDR0 M_CLK_DDR#0 DDR_A_D15 DDR_A_D14 A Compal Secret Data Security Classification Issued Date C172 0.1U_0402_16V4Z 1 2 2.2U_0603_6.3V4Z A 56_0404_4P2R_5% DDR_A_CAS# DDR_A_WE# VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD DDR_A_DM1 l.c 2 + 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DDR_A_D16 DDR_A_D17 1 C150 C157 2 1 330U_D2E_2.5VM_R7 0.1U_0402_16V4Z 1 C149 2 0.1U_0402_16V4Z 2 1 C148 C156 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 1 C155 C154 2 1 2.2U_0805_16V4Z 2.2U_0805_16V4Z 1 C153 2 2.2U_0805_16V4Z C147 2.2U_0805_16V4Z C152 2.2U_0805_16V4Z 1 D DDR_A_D13 DDR_A_D12 om +1.8V 2 ai DDR_A_D11 DDR_A_D10 2 1 2 Title Compal Electronics, Inc. nf @ ho tm DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D6 DDR_A_D7 1 DDRII-SODIMM SLOT1 Size Document Number Custom Montevina Consumer Date: Discrete ai DDR_A_D8 DDR_A_D9 DDR_A_DM0 Sheet Monday, October 08, 2007 1 he x Layout Note: Place near JP3 C 9,16 R116 10K_0402_5% 2 1 DDR_A_D2 DDR_A_D3 D DDR_A_D5 DDR_A_D0 R115 10K_0402_5% 2 1 DDR_A_DQS#0 DDR_A_DQS0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 C151 DDR_A_MA[0..14] VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS C146 10 DDR_A_D4 DDR_A_D1 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS 0.1U_0402_16V4Z DDR_A_DQS[0..7] 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2.2U_0805_16V4Z DDR_A_DM[0..7] 10 2 V_DDR_MCH_REF JDIMM1 10 1 +1.8V V_DDR_MCH_REF 15 of Rev 0.1 51 5 4 3 2 1 +1.8V +1.8V DDR_B_D[0..63] V_DDR_MCH_REF 10 DDR_B_DM[0..7] JDIMM2 DDR_B_MA[0..14] DDR_B_D0 DDR_B_D1 DDR_B_DQS#0 DDR_B_DQS0 D DDR_B_D2 DDR_B_D3 Layout Note: Place near JP10 DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11 +1.8V V_DDR_MCH_REF 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS DDR_B_D5 DDR_B_D4 DDR_B_DM0 DDR_B_D6 DDR_B_D7 1 2 9,15 1 2 C182 DDR_B_DQS[0..7] 10 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS C173 10 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 0.1U_0402_16V4Z DDR_B_DQS#[0..7] 10 2.2U_0805_16V4Z 10 D DDR_B_D12 DDR_B_D13 DDR_B_DM1 M_CLK_DDR2 M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#2 9 9 DDR_B_D14 DDR_B_D15 5 DDR_B_DQS#2 DDR_B_DQS2 2 DDR_B_D19 DDR_B_D18 DDR_B_D28 DDR_B_D25 DDR_B_DM3 C DDR_B_D30 DDR_B_D31 Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS 9 DDR_CKE2_DIMMB DDR_CKE2_DIMMB 10 DDR_B_BS2 DDR_B_BS2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 +0.9V 5 2 1 2 1 10 10 DDR_B_BS0 DDR_B_WE# 10 DDR_B_CAS# DDR_CS3_DIMMB# 9 DDR_B_MA10 DDR_B_BS0 DDR_B_WE# DDR_B_CAS# DDR_CS3_DIMMB# 2 9 C196 C195 C194 C193 C192 C191 C190 C189 C188 C187 C186 C185 C184 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 10 M_ODT3 M_ODT3 DDR_B_D32 DDR_B_D37 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35 B +0.9V 56_0404_4P2R_5% DDR_B_MA3 DDR_B_MA1 RP14 1 2 56_0404_4P2R_5% DDR_B_BS0 DDR_B_MA10 1 2 RP15 4 3 4 3 4 3 4 3 RP16 56_0404_4P2R_5% DDR_B_MA0 DDR_B_BS1 1 2 56_0404_4P2R_5% DDR_CS2_DIMMB# DDR_B_RAS# 1 2 RP17 RP18 4 3 4 3 4 3 4 3 56_0404_4P2R_5% DDR_B_MA12 1 DDR_B_MA9 2 DDR_B_D40 DDR_B_D41 Layout Note: Place these resistor closely JP3,all trace length Max=1.5" DDR_B_DM5 DDR_B_D42 DDR_B_D43 DDR_B_D55 DDR_B_D50 56_0404_4P2R_5% DDR_B_MA11 1 DDR_B_MA14 2 RP19 56_0404_4P2R_5% DDR_B_MA5 1 DDR_B_MA8 2 RP21 56_0404_4P2R_5% DDR_B_MA6 1 DDR_B_MA7 2 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D52 DDR_B_D53 DDR_B_D60 DDR_B_D61 RP20 DDR_B_DM7 DDR_B_D63 DDR_B_D58 RP24 2 1 RP25 3 4 4 3 RP26 DDR_CKE3_DIMMB 1 R120 2 56_0402_5% 4 3 56_0404_4P2R_5% DDR_B_MA2 1 DDR_B_MA4 2 15,17 15,17 CLK_SMBDATA CLK_SMBCLK CLK_SMBDATA CLK_SMBCLK +3VS 56_0404_4P2R_5% DDR_B_MA13 1 M_ODT2 2 56_0404_4P2R_5% DDR_CKE2_DIMMB 1 DDR_B_BS2 2 1 1 C197 2 2 2007/09/26 DDR_B_D29 DDR_B_D24 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D26 DDR_B_D27 C DDR_CKE3_DIMMB 4 3 DDR_CKE3_DIMMB 0612 add DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB# DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 DDR_B_MA13 M_ODT2 10 10 9 9 DDR_B_D36 DDR_B_D33 DDR_B_DM4 DDR_B_D39 DDR_B_D38 DDR_B_D44 DDR_B_D45 B DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D51 DDR_B_D54 M_CLK_DDR3 M_CLK_DDR#3 M_CLK_DDR3 M_CLK_DDR#3 9 9 DDR_B_DM6 DDR_B_D49 DDR_B_D48 DDR_B_D56 DDR_B_D57 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D59 DDR_B_D62 SO-DIMM B 2007/09/26 2 9 DDR_B_MA14 FOX_AS0A426-N8RN-7F Deciphered Date 9 DDR_B_D22 DDR_B_D23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 PM_EXTTS#1 DDR_B_DM2 R118 1 2 +3VS 10K_0402_5% A Compal Secret Data Security Classification Issued Date C198 0.1U_0402_16V4Z 4 3 DDR_B_D16 DDR_B_D17 R119 56_0404_4P2R_5% DDR_CS3_DIMMB# M_ODT3 RP23 4 3 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1 10K_0402_5% A RP22 1 2 2.2U_0603_6.3V4Z 56_0404_4P2R_5% DDR_B_CAS# DDR_B_WE# VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD 1 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DDR_B_D21 DDR_B_D20 2 2 1 C181 C180 2 1 0.1U_0402_16V4Z C179 2 1 0.1U_0402_16V4Z C178 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 1 C177 C183 2 1 2.2U_0805_16V4Z 2.2U_0805_16V4Z 1 C176 2 2.2U_0805_16V4Z 2 1 C175 C174 2.2U_0805_16V4Z 2.2U_0805_16V4Z 1 Title Compal Electronics, Inc. DDRII-SODIMM SLOT2 Size Document Number Rev 0.1 Montevina Consumer Discrete Date: Friday, October 05, 2007 Sheet 1 16 of 51 5 4 FSC FSB FSA CLKSEL2 CLKSEL1 CLKSEL0 CPU MHz SRC MHz PCI MHz REF MHz DOT_96 MHz 3 +3VS USB MHz R121 1 0 100 266 0 33.3 14.318 96.0 1 10U_0805_10V4Z 2 D 0 1 133 100 33.3 14.318 96.0 48.0 0 1 0 200 100 33.3 14.318 96.0 48.0 0 1 166 1 33.3 100 2 Routing the trace at least 10mil 0.1U_0402_16V4Z 0 333 0 33.3 100 CLK_XTAL_IN 48.0 96.0 14.318 1 0 1 100 100 33.3 14.318 96.0 48.0 1 1 0 400 100 33.3 14.318 96.0 48.0 1 1 1 2 1 C201 0.1U_0402_16V4Z 2 1 C202 0.1U_0402_16V4Z 2 1 C203 0.1U_0402_16V4Z 2 1 C204 0.1U_0402_16V4Z 2 C205 0.1U_0402_16V4Z +1.05VS_CK505 +VCCP 2 Place close to U51 R122 1 2 0_0805_5% Y1 1 1 C200 CLK_XTAL_OUT 48.0 96.0 14.318 1 C199 48.0 0 1 2 0_0805_5% 0 2 +3VS_CK505 1 14.31818MHZ_16P 1 0.1U_0402_16V4Z 1 C206 C207 2 10U_0805_10V4Z C213 18P_0402_50V8J Reserved 2 2 1 1 2 1 D 10U_0805_10V4Z 0.1U_0402_16V4Z 1 1 1 C209 C210 C211 C208 2 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 2 1 C212 2 0.1U_0402_16V4Z C214 18P_0402_50V8J Vendor suggests 22pF 1 2 1 2 R129 1K_0402_5% 9 MCH_CLKSEL0 9 9 6 6 NB 9 CPU R126 R130 R132 R134 R136 CLKREQ#_7 CLK_MCH_BCLK# CLK_MCH_BCLK CLK_CPU_BCLK# CLK_CPU_BCLK 1 1 1 1 1 2 2 2 2 2 475_0402_1% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% U3 +3VS_CK505 2 2 +VCCP 49 27 @ R143 1K_0402_5% 1 CPU_BSEL1 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 1 1 1 MCH_CLKSEL1 15,16 15,16 CLK_14M_ICH 1 R169 R155 R158 DEBUG@ DEBUG@ 1 2 33_0402_1% 1 2 33_0402_1% 1 2 33_0402_1% Mini card debug port31 24pin debug port 37 @ R157 0_0402_5% 38 CLK_DEBUG_PORT_1 CLK_DEBUG_PORT_0 CLK_PCI_EC CLK_PCI_ICH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 R161 1 2 33_0402_1% FSC REF1 CLK_SMBDATA CLK_SMBCLK PCI2_1 PCI2_2 27_SEL PCI_CLK3 ITP_EN 2 25 2 33_0402_1% T44 CLK_SMBDATA CLK_SMBCLK 9 R_CKPWRGD FSB CLK_XTAL_OUT CLK_XTAL_IN R147 1 27 7 @ R141 @ R142 R140 VGATE CLK_ENABLE# CK_PWRGD No Debug port anymore 1 2 R150 1K_0402_5% R154 1 2 0_0402_5% 1 7 CPU_BSEL2 +3VS_CK505 2 FSC @ R163 1K_0402_5% 1 2 R165 1K_0402_5% MCH_CLKSEL2 9 27 CLK_48M_ICH XDP/ITP CLK_CPU_XDP 6 CLK_CPU_XDP# 6 CLK_MCH_3GPLL 9 CLK_MCH_3GPLL# 9 3G_PLL CLKREQ#_6 31 CLK_PCIE_MCARD2 31 MiniCard_WLAN CLK_PCIE_MCARD2# 31 R167 1 2 33_0402_1% R173 R175 1 1 2 0_0402_5% 2 0_0402_5% 20 VGA 20 CLK_PCIE_VGA CLK_PCIE_VGA# 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 H_STP_PCI# H_STP_CPU# H_STP_PCI# H_STP_CPU# 27 27 R_CLK_PCIE_MCARD0# R_CLK_PCIE_MCARD0 R_CLKREQ#_10 R_CLK_SRC11 R_CLK_SRC11# R144 R145 R146 R725 R726 1 1 1 1 1 2 2 2 2 2 R_CLK_PCIE_LAN# R_CLK_PCIE_LAN R_CLKREQ#_9 R152 R153 R738 1 1 1 2 0_0402_5% 2 0_0402_5% 2 475_0402_1% CLK_PCIE_LAN# CLK_PCIE_LAN CLKREQ#_9 R_CLKREQ#_4 R_CLK_PCIE_NCARD# R_CLK_PCIE_NCARD R156 R159 R160 1 1 1 2 475_0402_1% 2 0_0402_5% 2 0_0402_5% CLKREQ#_4 31 CLK_PCIE_NCARD# CLK_PCIE_NCARD R_CLKREQ#_C R162 1 2 475_0402_1% CLKREQ#_C 0_0402_5% 0_0402_5% 475_0402_1% 0_0402_5% 0_0402_5% CLK_PCIE_MCARD0# CLK_PCIE_MCARD0 CLKREQ#_10 31 CLK_SRC11 32 CLK_SRC11# 32 31 MiniCard_WWAN 31 Card reader 30 30 GLAN 30 31 31 New Card 27 FSA R_PCIE_SATA# R_PCIE_SATA R166 R168 1 1 2 2 0_0402_5% 0_0402_5% R_PCIE_ICH# R_PCIE_ICH R170 R172 1 1 2 2 0_0402_5% 0_0402_5% R176 R177 1 1 2 2 0_0402_5% 0_0402_5% CLK_PCIE_SATA# CLK_PCIE_SATA B 26 26 SATA CLK_PCIE_ICH# CLK_PCIE_ICH 27 27 ICH +1.05VS_CK505 R_CLK_PCIE_VGA R_CLK_PCIE_VGA# SSCDREFCLK# SSCDREFCLK 27M_SSC 27M_CLK 21 VGA 21 2 @ R174 0_0402_5% PCI_STOP# CPU_STOP# VDD_SRC_IO SRC_10# SRC_10 CLKREQ_10# SRC_11 SRC_11# CLKREQ_11# SRC_9# SRC_9 CLKREQ_9# VSS_SRC CLKREQ_4# SRC_4# SRC_4 VDD_SRC_IO CLKREQ_3# SLG8SP553VTR_QFN72_10x10 +1.05VS_CK505 1 R164 1 2 10K_0402_5% R171 1 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 475_0402_1% 0_0402_5% 0_0402_5% 2 2 2 2 2 2 2 C CKPWRGD/PD# FS_B/TEST_MODE VSS_REF XTAL_OUT XTAL_IN VDD_REF REF_0/FS_C/TEST_ REF_1 SDA SCL NC VDD_PCI PCI_1 PCI_2 PCI_3 PCI_4/SEL_LCDCL PCIF_5/ITP_EN VSS_PCI +VCCP B 1 1 1 1 1 1 1 +1.05VS_CK505 VDD_48 USB_0/FS_A USB_1/CLKREQ_A# VSS_48 VDD_IO SRC_0/DOT_96 SRC_0#/DOT_96# VSS_IO VDD_PLL3 LCDCLK/27M LCDCLK#/27M_SS VSS_PLL3 VDD_PLL3_IO SRC_2 SRC_2# VSS_SRC SRC_3 SRC_3# 27,49 FSB R124 R125 R127 R131 R133 R135 R137 +3VS_CK505 @ R139 1K_0402_5% C R_CPU_XDP R_CPU_XDP# R_MCH_3GPLL R_MCH_3GPLL# R_CLKREQ#_6 R_CLK_PCIE_MCARD2 R_CLK_PCIE_MCARD2# R_CLKREQ#_7 R_MCH_BCLK# R_MCH_BCLK R_CPU_BCLK# R_CPU_BCLK 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 CPU_BSEL0 56_0402_5% CLRP1 NO SHORT PADS VDD_CPU CPU_0 CPU_0# VSS_CPU CPU_1 CPU_1# VDD_CPU_IO CLKREQ_7# SRC_8/CPU_ITP SRC_8#/CPU_ITP# VDD_SRC_IO SRC_7 SRC_7# VSS_SRC CLKREQ_6# SRC_6 SRC_6# VDD_SRC 7 +VCCP 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 FSA 2 1 R128 1 2 2.2K_0402_5% R138 1 2 0_0402_5% +1.05VS_CK505 +3VS_CK505 R123 1 +3VS +3VS R178 2.2K_0402_5% 21,27,31,37 +3VS 1 ICH_SMBDATA 1 21,27,31,37 R181 10K_0402_5% 3 2N7002_SOT23-3 Q3 CLK_SMBCLK CLK_48M_ICH 1 CLK_14M_ICH 2 1 CLK_PCI_ICH 2 1 CLK_PCI_EC om l.c ai 2007/09/26 Title 4 3 2 Compal Electronics, Inc. Clock Generator CK505 2 Deciphered Date Size Document Number Rev 0.1 Montevina Consumer Discrete Date: ai 2007/09/26 nf @ ho tm Compal Secret Data Security Classification Friday, October 05, 2007 Sheet 1 he x @ R183 10K_0402_5% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 1 2 A Issued Date 2 CLK_SMBDATA 3 2 PCI_CLK3 1 1 ITP_EN @ C215 5P_0402_50V8C @ C216 4.7P_0402_50V8C @ C217 4.7P_0402_50V8C @ C218 4.7P_0402_50V8C 2N7002_SOT23-3 Q4 2 2 A @ R182 10K_0402_5% ICH_SMBCLK 1 D 1 SB, MINI PCI R180 10K_0402_5% 2.2K_0402_5% 2 G V R179 S +3VS +3VS V D = SRC8/SRC8# = ITP/ITP# = Enable DOT96 & SRC1(UMA) = Enable SRC0 & 27MHz(DIS) 2 G PCI_CLK3 0 1 0 1 S ITP_EN 17 of 51 C D 40 40 GREEN 40 40 D_HSYNC BLUE 40 +5VS RED RED GREEN BLUE D_VSYNC +5VS C221 0.1U_0402_16V4Z 1 2 C222 0.1U_0402_16V4Z 1 2 @ D5 1 2 2 1 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 Place close to JCRT @ D6 @ D7 3 0.1U_0402_16V4Z C220 JCRT1 DAN217T146_SC59-3 1.1A_6VDC_FUSE 2 1 1 RB491D_SC59-3 BLUE GREEN RED W=40mils 2 3 1 DAN217T146_SC59-3 2 +CRTVDD F1 1 2 +RCRT_VCC D4 1 +5VS CRT Connector E 3 B DAN217T146_SC59-3 A 1 +5VS CONN@ SUYIN_070546FR015S263ZR 16 17 +3VS D_DDCDATA R191 51K_0402_5% 5P_0402_50V8C 2 1 1 1 1 @ C224 3 2N7002_SOT23-3 Q5 5P_0402_50V8C D_DDCCLK 1 D 2 2 2 D_VSYNC 1 @ C223 3VDDCDA 3VDDCDA 21 3VDDCCL 3 3VDDCCL 21 2 2 2 2 R188 2.2K_0402_5% 2 G 2 0_0603_5% R187 2.2K_0402_5% 2 G R186 2.2K_0402_5% S 4 Y U5 SN74AHCT1G125GW_SOT353-5 1 1 R185 2.2K_0402_5% S A 3 1 1 D_HSYNC +3VS D 2 R190 51K_0402_5% VSYNC_G_A R189 1 2 0_0603_5% 5 1 3 CRT_VSYNC CRT_VSYNC G 20 HSYNC_G_A +CRTVDD 2 A R184 1 2 2 P OE# CRT_HSYNC CRT_HSYNC G 20 P OE# 5 1 +CRTVDD U4 SN74AHCT1G125GW_SOT353-5 4 Y 2N7002_SOT23-3 Q6 D_DDCDATA D_DDCCLK CRT Termination/EMI Filter 40 40 Note: CRT / TV-out should route to JP30 first then to the JP1 & JP2 on system side. 3 3 RED C_GRN L3 1 2 HLC0603CSCCR11JT_0603 GREEN L4 1 2 HLC0603CSCCR11JT_0603 BLUE 1 1 1 2 150_0402_1% 150_0402_1% R196 150_0402_1% R195 150_0402_1% 150_0402_1% 150_0402_1% 2 1 M_BLUE 1 C_BLU 2 20 1 2 HLC0603CSCCR11JT_0603 1 2 M_GREEN L2 1 20 C_RED 2 M_RED 2 20 10P_0402_50V8J 2 C228 1 C229 2 1 2 C230 10P_0402_50V8J R197 R239 R238 R237 10P_0402_50V8J 4 4 Compal Secret Data Security Classification 2007/09/26 Issued Date 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. CRT Connector Size Document Number Rev 0.1 Montevina Consumer Discrete Date: Friday, October 05, 2007 Sheet E 18 of 51 4 3 2 1 +LCDVDD +3VS +5VALW Q7 SI2301BDS-T1-E3_SOT23-3 2 1 3 D S +LCDVDD 1 +LCDVDD +LCDVDD INVPWR_B+ 0.1U_0402_16V4Z 2 2 R198 100_0402_5% R199 47K_0402_5% 1 C232 0.1U_0402_16V4Z C233 4.7U_0805_10V4Z 1 2 G 1 1 +3VS 1 2 C231 2 C234 1 2 D D C235 C236 Q8 2N7002_SOT23-3 C237 R200 2 2 G 3 LVDS_BCLK+ LVDS_BCLK- 20 20 20 20 20 20 LVDS_B0+ LVDS_B0LVDS_B1+ LVDS_B1LVDS_B2+ LVDS_B2- LVDS_BCLK+ LVDS_BCLKLVDS_B0+ LVDS_B0LVDS_B1+ LVDS_B1LVDS_B2+ LVDS_B2- C DMIC_DAT DMIC_CLK +3V_LOGO INV_PWM BKOFF# DAC_BRIG DDC2_CLK DDC2_DATA R727 1 470_0402_5% 2 DMIC_DAT DMIC_CLK +5VS INV_PWM BKOFF# DAC_BRIG 20 20 20 20 20 20 ENAVDD C239 R201 100K_0402_5% 1 2 20 20 1 2 2 Q9 2N7002_SOT23-3 +3VS 38 38 38 B+ 21 21 R202 2.2K_0402_5% INVPWR_B+ @ L5 R203 2.2K_0402_5% 1 2 0_0805_5% C L6 1 2 FBMA-L11-201209-221LMA30T_0805 1 1 DDC2_CLK DDC2_DATA 1 S Avoid Panel display garbage after power on. 33 33 ACES_88242-4001 C435 680P_0402_50V7K D 2 G USB_CAM DDC2_CLK DDC2_DATA 1 21 LVDS_A2LVDS_A2+ LVDS_A1LVDS_A1+ LVDS_A0LVDS_A0+ LVDS_ACLKLVDS_ACLK+ 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 GND LVDS_A2LVDS_A2+ LVDS_A1LVDS_A1+ LVDS_A0LVDS_A0+ LVDS_ACLKLVDS_ACLK+ 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 2 USB20_P4 USB20_N4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 3 Limited Current < 1A JLVDS +3VS 20 20 0.047U_0402_16V7K 2 1 2 680P_0402_50V7K 680P_0402_50V7K 1 2 680P_0402_50V7K USB20_P4 USB20_N4 C238 LVDS CONN WITH Camera and Digi MIC 0.22U_0603_10V7K 27 27 2 D 1 100K_0402_5% S 1 4.7U_0805_10V4Z 5 0308_Reserve L10 and install L11. C434 680P_0402_50V7K 0308_Install all cap for EMI request. B B +5VALW USB_CAM 3.9K_0402_1% 1 1 U42 1 SHDN# OUTPUT GND R1091 2 4 2 2 5 SET C1391 1 VIN 2 G913E-SOT23-5 10U_1206_6.3V6M R1093 2 1 3 1K_0402_1% 2 C1392 10U_1206_6.3V6M 1 PJP604 PAD-OPEN 2x2m USB_VCCA is +3.6VS, R892:1K; R891:3.9Kohm USB_VCCA is +4VS, R892:1K; R891:4.22Kohm A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. LCD CONN. Size Document Number Rev 0.1 Montevina Consumer Discrete Date: ai 2007/09/26 Deciphered Date Friday, October 05, 2007 Sheet 1 he x 2007/09/26 nf @ ho tm Compal Secret Data Security Classification Issued Date ai l.c om A 19 of 51 A B C D LVDS & DAC Interface E PEG Interface U17F NB9M-GS_BGA_533P COMMON 6/13 IFPAB IFPAB_PLLVDD IFPAB_RSET 4700P_0402_25V7K 4.7U_0603_6.3V6K C257 2 1 IFPAB_PLLVDD IFPAB_RSET C246 2 19 19 LVDS_A1LVDS_A1+ 19 19 IFPA_TXD2 IFPA_TXD2 Y4 W4 LVDS_A2LVDS_A2+ 19 19 C247 1 R205 1K_0402_1% @ C248 IFPA_TXD3 IFPA_TXD3 AB5 AB4 IFPB_TXD4 IFPB_TXD4 V1 W1 LVDS_B0LVDS_B0+ 1/13 PCI_EXPRESS PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD 19 19 IFPB_TXD5 IFPB_TXD5 W2 W3 LVDS_B1LVDS_B1+ 19 19 IFPB_TXD6 IFPB_TXD6 AA3 AA2 LVDS_B2LVDS_B2+ 19 19 IFPB_TXD7 IFPB_TXD7 AA1 AB1 AE9 B 100 mA 4700P_0402_25V7K 1 470P_0402_50V7K 1 2 2 C266 1 C267 IFPA_IOVDD V3 IFPA_IOVDD IFPB_IOVDD V2 IFPB_IOVDD C251 2 9,25,30,31,32 17 17 11 11 4.7U_0603_6.3V6K A IFPA_TXC IFPA_TXC AD4 AC4 IFPB_TXC IFPB_TXC AB2 AB3 LVDS_ACLKLVDS_ACLK+ 19 19 LVDS_BCLKLVDS_BCLK+ 19 19 11 11 CLOCK 4700P_0402_25V7K 470P_0402_50V7K 1 B 2 11 11 11 11 2 C279 1 C280 11 11 11 11 2 11 U17D 2 W5 10K_0402_5% 11 11 5/13 DACC DACC_VDD R6 DACC_VREF V6 DACC_RSET 11 11 DAC C DACC_HSYNC DACC_VSYNC U6 U4 DACC_RED T5 DACC_GREEN T4 DACC_BLUE R4 11 11 11 11 11 11 11 11 11 11 3 11 11 U17C BLM18PG181SN1D_0603 NB9M-GS_BGA_533P COMMON 150 mA 11 11 CRT 11 11 3/13 DACA +3VS 2 470P_0402_50V7K 1 DACA_VDD AG2 1 DACA_VREF 1 AF1 DACA_VREF AE1 DACA_RSET 2 2 2 4700P_0402_25V7K C320 2 11 11 DAC A 1 R207 C319 DACA_HSYNC DACA_VSYNC AD2 AD1 DACA_RED AE2 DACA_GREEN AE3 DACA_BLUE AD3 C321 CRT_HSYNC CRT_VSYNC M_RED 18 18 11 11 11 11 18 0.1U_0402_16V4Z 124_0402_1% M_GREEN M_BLUE 18 11 11 11 11 U17E NB9M-GS_BGA_533P COMMON BLM18PG181SN1D_0603 +3VS 1 1U_0402_6.3V4Z DACB_VDD 470P_0402_50V7K D7 TV-OUT 11 11 11 11 4/13 DACB DACB_VDD L11 DACB_VREF G6 DACB_VREF DACB_RSET F8 DACB_RSET 1 C333 1 C334 1 1 1 4 C335 2 2 C336 R210 2 2 2 4700P_0402_25V7K 0.1U_0402_16V4Z 11 11 124_0402_1% DAC B DACB_CSYNC D6 DACB_RED F7 TV_CRMA DACB_GREEN E7 TV_LUMA DACB_BLUE E6 TV_COMPS TV_CRMA 40 TV_LUMA 40 TV_COMPS 2 PEX_TX0 PEX_TX0 AE12 AF12 PEX_RX0 PEX_RX0 C270 1 C271 1 2 0.1U_0402_16V4Z PEX_TXP1 AD12 2 0.1U_0402_16V4Z PEX_TXN1 AC12 PEX_TX1 PEX_TX1 AG12 AG13 PEX_RX1 PEX_RX1 2 0.1U_0402_16V4Z PEX_TXP2 AB11 2 0.1U_0402_16V4Z PEX_TXN2 AB12 PEX_TX2 PEX_TX2 AF13 AE13 PEX_RX2 PEX_RX2 2 0.1U_0402_16V4Z PEX_TXP3 AD13 2 0.1U_0402_16V4Z PEX_TXN3 AD14 PEX_TX3 PEX_TX3 2 C252 1 1 C258 1 C254 2 C255 4.7U_0603_6.3V6K +PCIE 1.920 Amps 2 C249 C259 2 2 1 0.1U_0402_16V4Z 1U_0603_10V4Z 4.7U_0603_6.3V6K 1 C262 1 C263 C264 2 2 10U_0805_6.3V6M C281 1 C282 1 PEG_RXP2 PEG_RXN2 C283 1 C284 1 C291 1 C292 1 PEG_RXP4 PEG_RXN4 AE15 AF15 PEX_RX3 PEX_RX3 2 0.1U_0402_16V4Z PEX_TXP4 AD15 2 0.1U_0402_16V4Z PEX_TXN4 AC15 PEX_TX4 PEX_TX4 AG15 AG16 PEX_RX4 PEX_RX4 2 0.1U_0402_16V4Z PEX_TXP5 AB14 2 0.1U_0402_16V4Z PEX_TXN5 AB15 PEX_TX5 PEX_TX5 AF16 AE16 PEX_RX5 PEX_RX5 C301 1 C302 1 2 0.1U_0402_16V4Z PEX_TXP6 AC16 2 0.1U_0402_16V4Z PEX_TXN6 AD16 PEX_TX6 PEX_TX6 AE18 AF18 PEX_RX6 PEX_RX6 C303 1 C304 1 2 0.1U_0402_16V4Z PEX_TXP7 AD17 2 0.1U_0402_16V4Z PEX_TXN7 AD18 PEX_TX7 PEX_TX7 AG18 AG19 PEX_RX7 PEX_RX7 C305 1 C306 1 2 0.1U_0402_16V4Z PEX_TXP8 AC18 2 0.1U_0402_16V4Z PEX_TXN8 AB18 PEX_TX8 PEX_TX8 AF19 AE19 PEX_RX8 PEX_RX8 AB19 AB20 PEX_TX9 PEX_TX9 AE21 AF21 PEX_RX9 PEX_RX9 AD19 AD20 PEX_TX10 PEX_TX10 AG21 AG22 PEX_RX10 PEX_RX10 C315 1 C316 1 2 0.1U_0402_16V4Z PEX_TX11 AD21 2 0.1U_0402_16V4Z PEX_TX11* AC21 PEX_TX11 PEX_TX11 AF22 AE22 PEX_RX11 PEX_RX11 C322 1 C323 1 2 0.1U_0402_16V4Z PEX_TX12 AB21 2 0.1U_0402_16V4Z PEX_TX12* AB22 PEX_TX12 PEX_TX12 AE24 AF24 PEX_RX12 PEX_RX12 2 0.1U_0402_16V4Z PEX_TX13 AC22 2 0.1U_0402_16V4Z PEX_TX13* AD22 PEX_TX13 PEX_TX13 AG24 AF25 PEX_RX13 PEX_RX13 PEG_M_TXP4 PEG_M_TXN4 C293 1 C294 1 PEG_RXP5 PEG_RXN5 PEG_M_TXP5 PEG_M_TXN5 PEG_RXP6 PEG_RXN6 PEG_M_TXP6 PEG_M_TXN6 PEG_RXP7 PEG_RXN7 PEG_M_TXP7 PEG_M_TXN7 PEG_RXP8 PEG_RXN8 PEG_M_TXP8 PEG_M_TXN8 C307 1 C308 1 PEG_RXP9 PEG_RXN9 2 0.1U_0402_16V4Z PEX_TX9 2 0.1U_0402_16V4Z PEX_TX9* PEG_M_TXP9 PEG_M_TXN9 C309 1 C310 1 PEG_RXP10 PEG_RXN10 PEG_M_TXP10 PEG_M_TXN10 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TX10 PEX_TX10* VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD J10 J12 J13 J9 L9 M11 M17 M9 N11 N12 N13 N14 N15 N16 N17 N19 N9 P11 P12 P13 P14 P15 P16 P17 R11 R12 R13 R14 R15 R16 R17 R9 T11 T17 T9 U19 U9 W10 W12 W13 W18 W19 W9 VDD_SENSE GND_SENSE W15 W16 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 A12 B12 C12 D12 E12 F12 PEX_PLLVDD AF9 0.1U_0402_16V4Z PEG_RXP11 PEG_RXN11 PEG_M_TXP11 PEG_M_TXN11 PEG_RXP12 PEG_RXN12 PEG_M_TXP12 PEG_M_TXN12 C324 1 C326 1 PEG_RXP13 PEG_RXN13 1 C273 C328 1 C329 1 PEG_M_TXP14 PEG_M_TXN14 C330 1 C331 1 PEG_RXP15 PEG_RXN15 PEG_M_TXP15 PEG_M_TXN15 2 0.1U_0402_16V4Z PEX_TX14 AD23 2 0.1U_0402_16V4Z PEX_TX14* AD24 PEX_TX14 PEX_TX14 AG25 AG26 PEX_RX14 PEX_RX14 2 0.1U_0402_16V4Z PEX_TXP15 AE25 2 0.1U_0402_16V4Z PEX_TXN15AE26 PEX_TX15 PEX_TX15 AF27 AE27 PEX_RX15 PEX_RX15 0.1U_0402_16V4Z 1 C274 2 1 C275 2 +NVVDD 1 C276 2 1 C277 2 0.1U_0402_16V4Z C278 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 4.7U_0603_6.3V6K 1 1 C285 1 C287 2 470P_0402_50V7K 1 C295 1 C296 2 0.1u X 7 C289 2 2 4.7U_0603_6.3V6K 470P_0402_50V7K 1 0.47u X 7 1 C288 2 470P_0402_50V7K 4.7u X 3 4.7U_0603_6.3V6K 1 C286 2 470P_0402_50V7K 1 C297 2 1 C298 2 2 470P_0402_50V7K 1 C299 C300 2 470P_0402_50V7K 2 470P_0402_50V7K +NVVDD_SENSE R392 0_0402_5% 2 1 3 +3VS 110 mA 1 C1476 2 120mA 2 RFU C314 2 1 C311 2 2 1 C327 PEX_TERMP 1 4.7U_0603_6.3V6M 1 PEX_TSTCLK_OUT PEX_TSTCLK_OUT VDD33 PEX_PLLDVDD AF10 AE10 1 1 C325 2 0.1U_0402_16V4Z PEG_RXP14 PEG_RXN14 0.1U_0402_16V4Z 1 1 C446 2 1 L10 BLM18PG181SN1D_0603 +PCIE C447 2 0.01U_0402_25V7K 1U_0402_6.3V4Z R208 200_0402_1% 2 AG9 AG10 1 2 4 R209 2.49K_0402_1% 40 Issued Date Compal Secret Data 2006/02/13 Deciphered Date 2006/03/10 T HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIET ARY PROPERT Y OF COM PAL ELECT RONICS, INC. AND CONT AINS CONFIDENT IAL AND T RADE SECRET INFORM AT ION. T HIS SHEET M AY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COM PET ENT DIVISION OF R&D DEPART M ENT EXCEPT AS AUT HORIZED BY COM PAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORM AT ION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B 2 470P_0402_50V7K AB13 AB16 AB17 AB7 AB8 AB9 AC13 AC7 AD6 AE6 AF6 AG6 1 Security Classification A 1 C253 1 1U_0603_10V4Z 2 2 0.1U_0402_16V4Z PEX_TXP0 AD10 2 0.1U_0402_16V4Z PEX_TXN0 AD11 PEG_M_TXP13 PEG_M_TXN13 11 11 C244 0.1U_0402_16V4Z PEX_REFCLK PEX_REFCLK C265 1 C268 1 PEG_M_TXP2 PEG_M_TXN2 18 11 11 2 AB10 AC10 PEX_RST 2 C317 1U_0402_6.3V4Z 1 PEX_REFCLKP PEX_REFCLKN AD9 1 1 2 DACA_VDD L9 1 PEX_RST# PEG_M_TXP1 PEG_M_TXN1 PEG_M_TXP3 PEG_M_TXN3 11 11 NB9M-GS_BGA_533P COMMON 1 PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ RFU 1 AC9 AD7 AD8 AE7 AF7 AG7 10U_0805_6.3V6M 1U_0603_10V4Z PEG_RXP1 PEG_RXN1 11 11 11 11 2 PEG_M_TXP0 PEG_M_TXN0 PEG_RXP3 PEG_RXN3 11 11 CLK_PCIE_VGA CLK_PCIE_VGA# PEG_RXP0 PEG_RXN0 11 11 11 R206 R204 0_0402_5% 1 PLT_RST# 600 mA 0.1U_0402_16V4Z NB9M-GS_BGA_533P COMMON DATA +1.8VS 2 +PCIE U17A A 470P_0402_50V7K 1 L8 BLM18PG181SN1D_0603 LVDS_A0LVDS_A0+ AA4 AA5 2 2 1 2 AD5 AB6 1 1 V4 V5 IFPA_TXD1 IFPA_TXD1 1U_0603_10V4Z 2 1 4.7U_0603_6.3V6K L7 BLM18PG181SN1D_0603 1 IFPA_TXD0 IFPA_TXD0 0.1U_0402_16V4Z 100mA 0.1U_0402_16V4Z +1.8VS C D Title Compal Electronics, Inc. PEG & LVDS & DAC Size Docum ent Num ber Cus tom Montevina Consumer Date: E Rev 0.1 Discrete Friday, October 05, 2007 Sheet 20 of 51 5 4 3 2 1 U17H +3VS 9/21 change C341 form 220p to 470p 1 U17L for nvidia 7/13 IFPC +1.8VS BLM18PG181SN1D_0603 R211 10K_0402_5% 2 160 mA IFPC_PLLVDD IFPC_RSET 470P_0402_50V7K 1 L12 D C7 B9 A9 STRAP0 STRAP1 STRAP2 R214 40.2K_0402_1% 1 2 F11 STRAP_REF_3V3 1 STRAP_REF_MIOB 2 F10 4.7U_0603_6.3V6K C337 ROM_CS B10 ROM_CS# ROM_SI ROM_SO ROM_SCLK A10 C10 C9 ROM_SI ROM_SO ROM_SCLK 10K_0402_5%@ R213 1 2 +3VS HDCP_SCL HDCP_SDA 2 1 +3VS 10K_0402_5% R215 I2CH_SCL I2CH_SDA A3 A4 1 C338 2 1 1 1 2 2 C340 2 C341 40.2K_0402_1% R216 BUFRST F9 SPDIF 4.7U_0603_6.3V6K +PCIE C 4700P_0402_25V7K 385 mA BLM18PG181SN1D_0603 2 4700P_0402_25V7K IFPC_IOVDD 1 J5 RFU F6 C342 4.7U_0603_6.3V6K 1 1 2 2 J6 IFPC_IOVDD TESTMODE C15 D15 G5 G4 TXD0 TXD0 IFPC_L3 IFPC_L3 J4 H4 HDMI_C_CLK- C1474 HDMI_C_CLK+ C1475 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z HDMI_CLKHDMI_CLK+ 42 42 TXD1 TXD1 TXD2 TXD2 IFPC_L2 IFPC_L2 K4 L4 HDMI_C_TX0- C1468 HDMI_C_TX0+ C1469 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z HDMI_TX0HDMI_TX0+ 42 42 TXD2 TXD2 TXD1 TXD1 IFPC_L1 IFPC_L1 M4 M5 HDMI_C_TX1- C1470 HDMI_C_TX1+ C1471 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z HDMI_TX1HDMI_TX1+ 42 42 2 C347 TXC TXC TXC TXC IFPC_L0 IFPC_L0 N4 P4 HDMI_C_TX2- C1472 HDMI_C_TX2+ C1473 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z HDMI_TX2HDMI_TX2+ 42 42 D 470P_0402_50V7K U17G 2 RFU_GND AC6 NB9M-GS_BGA_533P COMMON 8/13 IFPE 2 2 VGA Thermal Sensor ADM1032ARMZ +3VS N6 M6 1 1 10K_0402_5% R218 10K_0402_5% R220 @ 0.01U_0402_25V7K IFPC_AUX IFPC_AUX TXD0 TXD0 AD25 RFU RFU SPDIF_IN 2 DP 1 C349 1 1 2 C346 4.7U_0603_6.3V6K 10K_0402_5% R217 @ SPDIF_OUT 1 C343 1 SPDIF 33,40 N5 RFU DVI R212 1K_0402_1% L13 +3VS MXM IFPC_PLLVDD IFPC_RSET 2 11/13 MISC STRAP0 STRAP1 STRAP2 P6 R5 1 2 NB9M-GS_BGA_533P COMMON NB9M-GS_BGA_533P COMMON MXM DVI DP IFPE_AUX IFPE_AUX D4 D3 TXD0 TXD0 TXD0 TXD0 IFPE_L3 IFPE_L3 B4 B3 TXD1 TXD1 TXD2 TXD2 IFPE_L2 IFPE_L2 C4 C3 TXD2 TXD2 TXD1 TXD1 IFPE_L1 IFPE_L1 D5 E4 TXC TXC TXC TXC IFPE_L0 IFPE_L0 F4 F5 IFPE_PLLVDD IFPE_RSET R234 10K_0402_5% 2 Closed to VGA 2 @ C348 +3VS 0.1U_0402_16V4Z 2 1 10K_0402_5% R221 @ @ C350 1 2 2 U7 HDCP_WP 8 7 6 5 HDCP_WP HDCP_SCL HDCP_SDA VGA_THERMDA 2 VGA_THERMDC 3 VDD HDCP_SCL 2200P_0402_50V7K THERM#_VGA 4 SCLK D+ SDATA D- ALERT# THERM# GND 8 VGA_SM_CLK 7 VGA_SM_DA 6 THERM_SCI# E @ R219 10K_0402_5% H6 THERM_SCI# 27,38 IFPE_IOVDD R236 10K_0402_5% 5 C 2 1 VCC WP SCL SDA 10K_0402_5% R223 2 AT88SC0808 10K_0402_5% R224 R222 +3VS 1 @ ADM1032ARMZ REEL_MSOP8 2 R1129 VGA_SM_CLK 2 VGA_SM_DA 2 @ 10K_0402_5% 2 A0 A1 A2 GND 1 1 2 3 4 U6 1 0.1U_0402_16V4Z C351 1 C 1 1 HDCP ROM 1 +3VS 2 0_0402_5% 1 1 SMB_EC_CK2 SMB_EC_DA2 6,38 6,38 R1130 0_0402_5% +3VS 9/21 follow 17" U17K NB9M-GS_BGA_533P COMMON 36 mA 12/13 XTAL_PLL C355 VID_PLLVDD L6 SP_PLLVDD GPIO I/O ACTIVE GPIO0 IN N/A Primary DVI Hot-plug GPIO1 IN N/A 2nd DVI Hot-plug D11 XTAL_OUTBUFF E9 1 XTAL_SSIN GPIO2 OUT H Panel Back-Light PWM 2 @ C357 18P_0402_50V8J R233 0_0402_5% 1 2 XTALIN 1 27M_CLK E10XTALOUT R229 10K_0402_5% 1 @ C356 18P_0402_50V8J B 17 XTAL_OUT 2 @ XTAL_IN GPIO3 OUT H Panel Power Enable @ GPIO4 OUT 9/13 I2C_GPIO_THERM_JTAG Panel Back-Light Enable H Straps MULTI LEVEL STRAPS 2 GPIO5 OUT N/A NVVDD VID0 GPIO6 OUT N/A NVVDD VID1 GPIO7 OUT N/A FBVDD VID0 GPIO8 IN L Thermal Alert GPIO9 OUT L FAN PWM GPIO10 OUT N/A FBVref Select GPIO11 OUT N/A SLI SYNCO GPIO12 IN N/A AC Detect GPIO13 OUT L PS Control or HDMI_CEC GPIO14 OUT H PS Control T47 T48 T49 T50 T51 VGA_THERMDC D8 THERMDN VGA_THERMDA D9 THERMDP JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST AF3 AF4 AG4 AE4 AG3 JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST @ R960 R961 499_0402_1% @ 2 R962 R963 R964 R965 R966 1 1 1 R249 2 5.1K_0402_5% 1 R251 2 5.1K_0402_5% 1 R252 2 15K_0402_5% T1 T2 I2CB_SCL I2CB_SDA I2CC_SCL I2CC_SDA A2 B1 DDC2_CLK DDC2_DATA I2CD_SCL I2CD_SDA N2 N3 I2CE_SCL I2CE_SDA Y6 W6 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 I2CS_SCL I2CS_SDA 3VDDCCL 3VDDCDA 18 18 CRT LVDS DDC2_CLK DDC2_DATA 19 19 HDMICLK_VGA HDMIDAT_VGA 42 42 HDMI_DETECT 42 HDMI B I2CE_SCL I2CE_SDA N1 G1 C1 M2 ENVDD M3 K3 K2 J2 C2 THERMAL ALERT 1 M1 SINN_GPIO9 0_0402_5% 1 D2 0_0402_5% D1 J3 J1 K1 F3 G3 G2 F1 F2 ENAVDD ENBKL GPU_VID 19 38 47 THERM#_VGA 2 2R396 THERM_SCI# R395 9/21 GPU_VID High: +NVVDDP 1.0V Low: +NVVDDP 0.9V HDA_BCLK A7 HDA_SYNC HDA_SDI HDA_SDO HDA_RST B7 A6 B6 C6 HDA_BITCLK_VGA HDA_SDIN2_R R399 33_0402_5% 1 2 4 3 26,33 HDA_SYNC_VGA HDA_SDIN2 HDA_SDOUT_VGA HDA_RST#_VGA A 26,33 26 26 26,33 9/21 R329 near GPU R967 9/21 R237, R238, R240, R241 near ICH 499_0402_1% 499_0402_1% 499_0402_1% 499_0402_1% 499_0402_1% 499_0402_1% 499_0402_1% 1 R253 2 5.1K_0402_5% HD AUDIO Compal Secret Data Security Classification Issued Date 2006/02/13 Deciphered Date 2006/03/10 T HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIET ARY PROPERT Y OF COM PAL ELECT RONICS, INC. AND CONT AINS CONFIDENT IAL AND T RADE SECRET INFORM AT ION. T HIS SHEET M AY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COM PET ENT DIVISION OF R&D DEPART M ENT EXCEPT AS AUT HORIZED BY COM PAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORM AT ION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 R2 R3 2 1 R248 20K_0402_1% 1 1 R250 2 5.1K_0402_5% 1 @ VGA_SM_CLK VGA_SM_DA @ 2 1 R247 2 5.1K_0402_5% 1 1 R246 2 5.1K_0402_5% A 2 @ R225 1 1 R226 R1 T3 I2CB_SCL I2CB_SDA 10/13 HDAUDIO 1 1 R245 2 @ 5.1K_0402_5% @ I2CA_SCL I2CA_SDA U17I 2 1 R244 2 10K_0402_1% 0_0402_5% 2 2 0_0402_5% ICH_SMBCLK ICH_SMBDATA NB9M-GS_BGA_533P COMMON 2 1 R243 2 45.3K_0402_1% 17,27,31,37 17,27,31,37 HDMI_CLKHDMI_CLK+ HDMI_TX0HDMI_TX0+ HDMI_TX1HDMI_TX1+ HDMI_TX2HDMI_TX2+ 1 1 R242 2 5.1K_0402_5% R248 20 Kohms 10 Kohms 45 Kohms 30 Kohms 1 @ Locating 16MX16 Hynix 16MX16 Samsung 32MX16 Hynix 32MX16 Samsung 2 +3VS Resistor Value 2 STRAP0 STRAP1 STRAP2 ROM_SI ROM_SO ROM_SCLK DDR2 2 R231 2 R232 NB9M-GS_BGA_533P COMMON 2 @ R235 10K_0402_5% 2 XTALIN D10 1 R228 10K_0402_5% 2K_0402_5% 1 2K_0402_5% 1 U17M 0.1U_0402_16V4Z 27M_SSC I2CB_SCL I2CB_SDA USAGE Title Compal Electronics, Inc. Straps & HDMI Size Docum ent Num ber Cus tom Montevina Consumer Date: Rev 0.1 Discrete Sheet Monday, October 08, 2007 2 21 1 om 2 PLLVDD K6 l.c 1U_0402_6.3V4Z 17 2 C354 2 K5 ai C353 2 1 nf @ ho tm C352 2 GPU_PLLVDD 1 2 R227 2 R230 ai 1 2K_0402_5% 1 2K_0402_5% 1 he x 1 1 C497 0.1U_0402_16V4Z 1U_0402_6.3V4Z BLM18PG181SN1D_0603 2 1 L14 1 1U_0402_6.3V4Z +PCIE I2CE_SCL I2CE_SDA of 51 A VRAM Interface R1124 1 +VDD_MEM18 0_1206_5% 2 1 R1125 23 MDA[15..0] 23 MDA[31..16] 24 MDA[47..32] 24 MDA[63..48] +1.8VS 2 0_1206_5% MDA[15..0] U17B MDA[31..16] U17J NB9M-GS_BGA_533P COMMON MDA[47..32] MDA[63..48] D21 C22 B22 A22 C24 B25 A25 A26 D22 E22 E24 D24 D26 D27 C27 B27 D16 E16 D17 F18 D20 F20 E21 F21 C16 B18 C18 D18 C19 C21 B21 A21 P22 P24 R23 R24 T23 U24 V23 V24 N25 N26 R25 R26 T25 V26 V25 V27 V22 W22 W23 W24 AA22 AB23 AB24 AC24 W25 W26 W27 AA25 AB25 AB26 AD26 AD27 2/13 FRAME_BUFFER FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7 D23 C26 D19 B19 T24 T26 AA23 AB27 FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 A24 C25 E19 A19 T22 T27 AA24 AA26 FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 QSA#0 QSA#1 QSA#2 QSA#3 QSA#4 QSA#5 QSA#6 QSA#7 B24 D25 E18 A18 R22 R27 Y24 AA27 FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7 MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63 1 23 QSA[3..0] 24 QSA[7..4] 23 QSA#[3..0] 24 QSA#[7..4] FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ A13 B13 C13 D13 D14 E13 F13 F14 F15 F16 F17 F19 F22 H23 H26 J15 J16 J18 J19 L19 L23 L26 M19 N22 U22 Y22 1 C358 0.1U_0402_16V4Z 1 C366 2 C361 C369 1 1 F24 F23 N24 N23 FB_CAL_PD_VDDQ B15 FB_CAL_PU_GND A15 FB_CAL_TERM_GND 0.1U_0402_16V4Z C363 1 C364 2 2 C365 2 1U_0402_6.3V4Z C373 1 0.022U_0402_16V7K 1 1 C375 2 2 2 C372 2 0.1U_0402_16V4Z 2 C374 1U_0402_6.3V4Z 23,24 9/18 add R for nvidia CLKA0 CLKA0# CLKA1 CLKA1# CMDA12 R1131 10K_0402_5% 1 2 CMDA11 R394 10K_0402_5% 1 2 23 23 24 24 R254 30_0402_1% 2 +VDD_MEM18 1 1 2 R255 30_0402_1% B16 @1 @ 2 R256 40.2_0402_1% AC11 AC14 AC17 AC2 AC20 AC23 AC26 AC5 AC8 AF11 AF14 AF17 AF2 AF20 AF23 AF26 AF5 AF8 B11 B14 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND B17 B2 B20 B23 B26 B5 B8 E11 E14 E17 E2 E20 E23 E26 E5 E8 H2 H5 J11 J14 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND J17 K19 K9 L11 L12 L13 L14 L15 L16 L17 L2 L5 M12 M13 M14 M15 M16 P19 P2 P23 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND P26 P5 P9 T12 T13 T14 T15 T16 U11 U12 U13 U14 U15 U16 U17 U2 U23 U26 U5 V19 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND V9 W11 W14 W17 Y2 Y23 Y26 Y5 GND GND GND GND GND GND GND GND NC NC NC NC AA6 AC19 E15 T6 0.1U_0402_16V4Z C371 2 F26 CMDA0 J24 CMDA1 F25 CMDA2 M23 CMDA3 N27 CMDA4 M27 CMDA5 K26 CMDA6 J25 CMDA7 J27 CMDA8 G23 CMDA9 G26 CMDA10 J23 CMDA11 M25 CMDA12 K27 CMDA13 G25 CMDA14 L24 CMDA15 K23 CMDA16 K24 CMDA17 G22 CMDA18 K25 CMDA19 H22 CMDA20 M26 CMDA21 H24 CMDA22 F27 CMDA23 J26 CMDA24 G24 CMDA25 G27 CMDA26 M24 CMDA27 K22 CMDA28 J22 CMDA29 L22 CMDA30 FBA_CLK0 FBA_CLK0 FBA_CLK1 FBA_CLK1 2 1 4700P_0402_25V7K 4700P_0402_25V7K C370 1 2 CMDA[30..0] FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 RFU RFU 2 C368 4.7U_0603_6.3V6K C362 2 1 C367 2 1 4700P_0402_25V7K 1 0.022U_0402_16V7K 1 2 C360 2 13/13 GND_NC 4.7U_0603_6.3V6K 1 0.022U_0402_16V7K 4700P_0402_25V7K 1 1 C359 2 0.022U_0402_16V7K 4700P_0402_25V7K 1 R257 FBA_DEBUG M22 1 2 10K_0402_5% +VDD_MEM18 @ +VDD_MEM18 FB_PLLAVDD R19 0.1U_0402_16V4Z FB_DLLAVDD T19 1 DQMA[7..4] 1 Rt @ R258 1K_0402_1% 2 1 C376 2 2 24 0.022U_0402_16V7K 1 A16 2 1 +PCIE L15 BLM18PG181SN1D_0603 C377 1U_0402_6.3V4Z FB_VREF 1 DQMA[3..0] 1 @ R259 1K_0402_1% 2 23 NB9M-GS_BGA_533P COMMON +VDD_MEM18 Rb C378 2 @ 0.1U_0402_16V4Z 1 1 C379 2 BLM18PG181SN1D_0603 2 1 +PCIE L16 C380 1U_0402_6.3V4Z 2 0.01U_0402_25V7K Compal Secret Data Security Classification Issued Date 2005/03/10 Deciphered Date 2006/03/10 T HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIET ARY PROPERT Y OF COM PAL ELECT RONICS, INC. AND CONT AINS CONFIDENT IAL AND T RADE SECRET INFORM AT ION. T HIS SHEET M AY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COM PET ENT DIVISION OF R&D DEPART M ENT EXCEPT AS AUT HORIZED BY COM PAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORM AT ION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A Title Compal Electronics, Inc. VRAM / GND Size Docum ent Num ber Cus tom Montevina Consumer Date: Rev 0.1 Discrete Friday, October 05, 2007 Sheet 22 of 51 5 4 3 2 1 DATA Bus D VRAM DDR2 chips (256MB & 128MB) Address CMD0 A3 32Mx16 DDR2 400MHz *4==>256MB 16Mx16 DDR2 400MHz*4==>128MB CMD1 A0 CMD2 A2 CMD3 A1 22,24 QSA[7..0] 22,24 QSA#[7..0] 22,24 22,24 22,24 DQMA[7..0] MDA[63..0] CMDA[30..0] 0..31 32..63 A0 A1 CMD4 A3 QSA[7..0] CMD5 A4 QSA#[7..0] CMD6 A5 DQMA[7..0] CMD7 D MDA[63..0] CMD8 CS# CS# CMDA[30..0] CMD9 WE# WE# CMD10 BA0 BA0 CMD11 CKE CKE CMD12 ODT ODT CMD13 CMDA14 CMDA16 CMDA17 CMDA20 CMDA19 CMDA23 CMDA21 CMDA22 CMDA24 CMDA0 CMDA2 CMDA3 CMDA1 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 CLKA0# CLKA0 K8 J8 CMDA11 K2 CMDA8 L8 CMDA9 K3 CMDA15 K7 CMDA25 L7 DQMA2 DQMA0 F3 B3 CMDA12 +VDD_MEM18 K9 QSA2 QSA#2 F7 E8 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CK CK VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 CKE CS WE RAS VDD1 VDD2 VDD3 VDD4 VDD5 CAS LDM UDM VDDL VSSDL QSA0 QSA#0 B7 A8 MEM_VREF0 J2 1 2 R260 1K_0402_1% A2 E2 L1 R3 R7 R8 1 R262 1K_0402_1% 2 2 C385 0.1U_0402_16V4Z MDA7 MDA0 MDA5 MDA2 MDA3 MDA4 MDA1 MDA6 MDA23 MDA18 MDA20 MDA16 MDA17 MDA21 MDA19 MDA22 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 A1 E1 J9 M9 R1 UDQS UDQS VREF NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8 VSS1 VSS2 VSS3 VSS4 VSS5 CMDA14 CMDA16 CMDA17 CMDA20 CMDA19 CMDA23 CMDA21 CMDA22 CMDA24 CMDA0 CMDA2 CMDA3 CMDA1 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 K8 J8 K2 CMDA8 L8 CMDA9 K3 CMDA15 K7 CMDA25 0.1U_0402_16V4Z 1 J1 J7 2 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 L2 L3 CMDA11 1 C383 LDQS LDQS CMDA10 CMDA18 CLKA0# CLKA0 +VDD_MEM18 ODT 1 B U9 BA0 BA1 2 L7 DQMA1 DQMA3 F3 B3 CMDA12 K9 C384 4.7U_0805_6.3V6K QSA1 QSA#1 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 F7 E8 QSA3 QSA#3 B7 A8 MEM_VREF0 J2 A2 E2 L1 R3 R7 R8 A3 E3 J3 N1 P9 BA0 BA1 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CK CK VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 CKE CS WE RAS VDD1 VDD2 VDD3 VDD4 VDD5 CAS LDM UDM VDDL VSSDL MDA27 MDA28 MDA24 MDA31 MDA30 MDA25 MDA29 MDA26 MDA15 MDA9 MDA12 MDA8 MDA11 MDA13 MDA10 MDA14 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 +VDD_MEM18 VREF NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8 VSS1 VSS2 VSS3 VSS4 VSS5 A11 CMD17 A10 A10 CMD18 BA1 BA1 CMD19 A8 A8 CMD20 A9 A9 CMD21 A6 A6 CMD22 A5 C A7 CMD23 A7 CMD24 A4 CMD25 CAS# CAS# CMD26 A13 A13 CMD27 BA2 BA2 CMD30 A1 E1 J9 M9 R1 0.1U_0402_16V4Z 1 J1 J7 2 UDQS UDQS A11 CMD29 1 C381 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 RAS# CMD16 CMD28 ODT LDQS LDQS A12 C382 4.7U_0805_6.3V6K 2 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 B 22 CLKA0 CLKA0 1 C L2 L3 A12 RAS# R261 475_0402_1% A3 E3 J3 N1 P9 2 U8 CMDA10 CMDA18 CMD14 CMD15 22 CLKA0# CLKA0# (SSTL-1.8) VREF = .5*VDDQ HY5PS561621F-25 HY5PS561621F-25 DDR BGA MEMORY DDR2 BGA MEMORY +VDD_MEM18 0.01U_0402_16V7K 1 C396 2 C397 2 C398 2 1 C399 2 0.1U_0402_16V4Z 1 C400 2 1 C401 2 0.01U_0402_16V7K 1 C402 2 2 0.1U_0402_16V4Z 1 C386 1000P_0402_50V7K 1 C387 1 C388 4.7U_0805_6.3V6K 1 C389 1 C390 0.01U_0402_16V7K 1 C391 1 C392 1 C393 A 2 0.01U_0402_16V7K 2 2 0.01U_0402_16V7K 2 2 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 2 0.01U_0402_16V7K 2005/05/05 2006/05/05 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. nf @ ho tm Compal Secret Data Security Classification Issued Date ai l.c 0.01U_0402_16V7K 1 LS-2821 ATI_M56-P VGA Board Size Document Number Rev 0.1 CHANNEL A EXT. 256M_1 Date: Monday, October 08, 2007 ai C395 1000P_0402_50V7K 1 0.1U_0402_16V4Z he x A 1 4.7U_0805_6.3V6K om +VDD_MEM18 1 Sheet 7 of 16 5 4 3 2 1 DATA Bus VRAM DDR2 chips (256MB & 128MB) Address 32Mx16 DDR2 400MHz *4==>256MB 16Mx16 DDR2 400MHz*4==>128MB D 22,23 22,23 CMDA[30..0] 22,23 QSA#[7..0] 22,23 QSA[7..0] 22,23 DQMA[7..0] DQMA[7..0] MDA[63..0] 32..63 0..31 CMD0 A3 CMD1 A0 CMD2 A2 CMD3 A1 A0 A1 CMD4 A3 CMD5 A4 CMDA[30..0] CMD6 A5 QSA#[7..0] CMD7 QSA[7..0] CMD8 CS# CS# MDA[63..0] CMD9 WE# WE# CMD10 BA0 BA0 CMD11 CKE CKE CMD12 ODT ODT D CMD13 CMDA14 CMDA16 CMDA17 CMDA20 CMDA19 CMDA23 CMDA21 CMDA6 CMDA5 CMDA4 CMDA13 CMDA3 CMDA1 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 CLKA1# CLKA1 K8 J8 CMDA11 K2 CMDA8 L8 CMDA9 K3 CMDA15 K7 CMDA25 L7 DQMA5 DQMA4 B F3 B3 CMDA12 K9 U11 BA0 BA1 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CK CK A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 CKE CS WE RAS LDM UDM J1 J7 VDDL VSSDL 0.1U_0402_16V4Z 1 ODT +VDD_MEM18 F7 E8 QSA4 QSA#4 B7 A8 2 LDQS LDQS UDQS UDQS 2 R266 1K_0402_1% 1 MEM_VREF1 C407 0.1U_0402_16V4Z 2 2 J2 A2 E2 L1 R3 R7 R8 1 R268 1K_0402_1% VREF NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8 CMDA14 CMDA16 CMDA17 CMDA20 CMDA19 CMDA23 CMDA21 CMDA6 CMDA5 CMDA4 CMDA13 CMDA3 CMDA1 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 K8 J8 CMDA11 K2 CMDA8 L8 CMDA9 K3 CMDA15 K7 CMDA25 L7 DQMA6 DQMA7 F3 B3 CMDA12 K9 QSA6 QSA#6 F7 E8 QSA7 QSA#7 B7 A8 MEM_VREF1 A3 E3 J3 N1 P9 VSS1 VSS2 VSS3 VSS4 VSS5 L2 L3 C406 2 4.7U_0805_6.3V6K A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 1 QSA5 QSA#5 1 C405 CMDA10 CMDA18 CLKA1# CLKA1 +VDD_MEM18 A1 E1 J9 M9 R1 VDD1 VDD2 VDD3 VDD4 VDD5 CAS MDA39 MDA32 MDA38 MDA34 MDA33 MDA37 MDA35 MDA36 MDA44 MDA43 MDA47 MDA40 MDA41 MDA46 MDA42 MDA45 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 J2 A2 E2 L1 R3 R7 R8 (SSTL-1.8) VREF = .5*VDDQ HY5PS561621F-25 0.01U_0402_16V7K 1 A C417 1000P_0402_50V7K 1 C418 2 1 C419 2 0.01U_0402_16V7K C420 2 0.1U_0402_16V4Z 1 C421 2 0.1U_0402_16V4Z A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CK CK A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 CKE CS WE RAS LDM UDM J1 J7 VDDL VSSDL 0.1U_0402_16V4Z 1 1 C422 2 1 C423 2 0.1U_0402_16V4Z 0.01U_0402_16V7K 1 C424 2 2 0.01U_0402_16V7K 1 C408 1000P_0402_50V7K 1 C409 2 1 C410 2 0.01U_0402_16V7K 2 A8 A8 CMD20 A9 A9 CMD21 A6 A6 CMD22 A5 CMD23 A7 CMD24 A4 CMD25 CAS# CAS# CMD26 A13 A13 CMD27 BA2 BA2 C A7 B C404 4.7U_0805_6.3V6K 22 CLKA1 CLKA1 R267 475_0402_1% A3 E3 J3 N1 P9 VSS1 VSS2 VSS3 VSS4 VSS5 22 Issued Date 4.7U_0805_6.3V6K 1 C411 2 1 C412 2 CLKA1# CLKA1# 0.01U_0402_16V7K 1 C413 2 0.1U_0402_16V4Z 1 C414 2 1 A C415 2 0.1U_0402_16V4Z 2 0.01U_0402_16V7K Compal Secret Data Security Classification 2005/05/05 2006/05/05 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 BA1 CMD19 CMD28 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8 BA1 1 2 VREF A10 CMD18 CMD30 C403 UDQS UDQS A11 A10 CMD29 ODT LDQS LDQS A11 CMD17 A1 E1 J9 M9 R1 VDD1 VDD2 VDD3 VDD4 VDD5 CAS +VDD_MEM18 CMD16 DDR BGA MEMORY +VDD_MEM18 4.7U_0805_6.3V6K 1 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 RAS# HY5PS561621F-25 DDR2 BGA MEMORY +VDD_MEM18 BA0 BA1 MDA59 MDA60 MDA58 MDA62 MDA63 MDA56 MDA61 MDA57 MDA51 MDA53 MDA48 MDA55 MDA52 MDA49 MDA54 MDA50 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 A12 RAS# 1 C L2 L3 A12 CMD15 2 U10 CMDA10 CMDA18 CMD14 4 3 2 Title Compal Electronics, Inc. LS-2821 ATI_M56-P VGA Board Size Document Number Rev 0.1 CHANNEL A EXT. 256M_2 Date: Monday, October 08, 2007 Sheet 1 8 of 16 5 4 3 2 1 +3VS PCI_DEVSEL# 2 8.2K_0402_5% PCI_STOP# R274 1 2 8.2K_0402_5% PCI_TRDY# R275 1 2 8.2K_0402_5% PCI_FRAME# R276 1 2 8.2K_0402_5% PCI_PLOCK# R277 1 2 8.2K_0402_5% U12B D11 C8 D9 E12 E9 C9 E10 B7 C7 C5 G11 F8 F11 E7 A3 D2 F10 D5 D10 B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3 PCI_IRDY# R278 1 2 8.2K_0402_5% PCI_SERR# R279 1 2 8.2K_0402_5% PCI_PERR# +3VS R281 1 2 8.2K_0402_5% PCI_PIRQA# R282 1 2 8.2K_0402_5% PCI_PIRQB# R283 1 2 8.2K_0402_5% PCI_PIRQC# R284 1 2 8.2K_0402_5% PCI_PIRQD# R285 1 2 8.2K_0402_5% PCI_PIRQE# R286 1 2 8.2K_0402_5% PCI_PIRQF# R287 1 2 8.2K_0402_5% PCI_PIRQG# R288 2 1 8.2K_0402_5% PCI_PIRQH# R289 1 2 8.2K_0402_5% PCI_REQ0# R290 1 2 8.2K_0402_5% PCI_REQ1# R292 1 2 8.2K_0402_5% PCI_REQ2# AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C R293 1 2 8.2K_0402_5% PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_GNT3# PCI_GNT3# IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# PLTRST# PCICLK PME# PCI_REQ0# PCI_GNT0# PCI_REQ1# D PCI_REQ2# PCI_REQ3# PCI_GNT3# D8 B4 D6 A5 Place closely pin D4 CLK_PCI_ICH D3 E3 R1 C6 E4 C2 J4 A4 F5 D7 C14 D4 R2 PCI_IRDY# PCI_RST# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME# PCI_RST# 37,38 PCI_SERR# @ R280 10_0402_5% 38 1 2 PLT_RST# CLK_PCI_ICH PCI_PME# PLT_RST# CLK_PCI_ICH PCI_PME# @ C425 8.2P_0402_50V 9,20,30,31,32 17 38 3/28 PCI_PME# Remvoe 8.2k pull high +3VALW resistance. C Interrupt I/F PIRQA# PIRQB# PIRQC# PIRQD# ICH9-M ES_FCBGA676 PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5 H4 K6 F2 G2 PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# PCI_REQ3# 1 R291 2 0_0402_5% ACCEL_INT 37 Boot BIOS Strap Low= A16 swap override Enble High= Default * @R294 @R294 1 C/BE0# C/BE1# C/BE2# C/BE3# F1 G4 B6 A7 F13 F12 E6 F6 08/25 Follow Abita A16 swap override Strap B J5 E1 J6 C4 REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 PCI 1 2 8.2K_0402_5% R273 1 2 D R272 1 PCI_GNT0# B Boot BIOS Location SPI_CS#1 0 1 SPI 1 0 PCI 1 1 LPC 2 1K_0402_5% * +3VALW 27 SPI_CS1#_R SPI_CS1#_R @ R295 1 PCI_GNT0# @ R296 1 2 1K_0402_5% 2 1K_0402_5% A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. ICH9(1/4)-PCI/INT Size Document Number Rev 0.1 Montevina Consumer Discrete Date: ai 2007/09/26 Deciphered Date Friday, October 05, 2007 Sheet 1 he x 2007/09/26 nf @ ho tm Compal Secret Data Security Classification Issued Date ai l.c om A 25 of 51 5 4 R302 ICH8M LAN100 SLP Strap (Internal VR for VccLAN1.05 and VccCL1.05) ICH_SRTCRST# D C426 0.1U_0402_16V4Z 1 2 @ R303 @ R304 LPC_AD[0..3] A25 F20 C22 ICH_INTVRMEN LAN100_SLP B22 A22 R312 R313 R324 33_0402_5% 33_0402_5% 33_0402_5% 1 1 1 2 2 2 HDA_BITCLK R314 R316 R397 33_0402_5% 33_0402_5% 33_0402_5% 1 1 1 2 2 2 HDA_SYNC F14 G13 D14 D13 D12 E13 +1.5VS R317 R318 R398 33_0402_5% 33_0402_5% 33_0402_5% 33 34 21 HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 34 33 21 HDA_SDOUT_MDC HDA_SDOUT_CODEC HDA_SDOUT_VGA 1 1 1 2 2 2 HDARST# R311 1 2 GLAN_COMP 24.9_0402_1% HDA_BITCLK HDA_SYNC R320 R321 R323 33_0402_5% 33_0402_5% 33_0402_5% 1 1 1 2 2 2 T55 T56 PAD PAD B28 B27 AF6 AH4 HDARST# AE7 HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 AF4 AG4 AH3 AE5 HDA_SDOUT AG5 AG7 AE8 SATA_LED# HDD Multi bay 39 SATA_LED# 29 29 29 29 SATA_RXN0_C SATA_RXP0_C SATA_TXN0 SATA_TXP0 29 29 29 29 SATA_RXN1_C SATA_RXP1_C SATA_TXN1 SATA_TXP1 SATA_TXN0 SATA_TXP0 0.01U_0402_50V7K C431 1 2 C433 1 2 SATA_TXN1 SATA_TXP1 0.01U_0402_50V7K 0.01U_0402_50V7K C820 1 2 C821 1 2 AG8 SATA_TXN0_C SATA_TXP0_C AJ16 AH16 AF17 AG17 SATA_TXN1_C SATA_TXP1_C AH13 AJ13 AG14 AF14 GLAN_CLK FWH4/LFRAME# LDRQ0# LDRQ1#/GPIO23 A20GATE A20M# LAN_RSTSYNC DPRSTP# DPSLP# LAN_RXD0 LAN_RXD1 LAN_RXD2 FERR# LAN_TXD_0 LAN_TXD_1 LAN_TXD_2 GPIO56 GLAN_COMPI GLAN_COMPO CPUPWRGD IGNNE# CPU E25 B10 HDA_RST#_CODEC HDA_RST#_MDC HDA_RST#_VGA INTVRMEN LAN100_SLP LAN / GLAN C HDA_SYNC_MDC HDA_SYNC_CODEC HDA_SYNC_VGA RTCRST# SRTCRST# INTRUDER# INIT# INTR RCIN# NMI SMI# HDA_BIT_CLK HDA_SYNC STPCLK# HDA_RST# THRMTRIP# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 TP12 IHDA 2 C13 HDA_BITCLK_CODEC HDA_BITCLK_MDC HDA_BITCLK_VGA FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 K5 K4 L6 K2 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 K3 LPC_FRAME# HDA_SDOUT SATA4RXN SATA4RXP SATA4TXN SATA4TXP HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 @ R305 1 2 56_0402_5% H_DPSLP# @ R306 1 2 56_0402_5% 31,37,38 LPC_FRAME# 31,37,38 +VCCP J3 J1 T54 PAD N7 AJ27 GATEA20 H_A20M# AJ25 AE23 H_DPRSTP_R# H_DPSLP# R309 1 H_DPRSTP# 2 0_0402_5% AJ26 R_H_FERR# R310 1 H_FERR# 2 56_0402_5% AD22 H_PWRGOOD AF25 H_IGNNE# AE22 AG25 L3 H_INIT# H_INTR KB_RST# AF23 AF24 H_NMI H_SMI# AH27 H_STPCLK# AG26 THRMTRIP_ICH# GATEA20 H_A20M# 38 6 H_PWRGOOD R308 56_0402_5% 6,7 H_IGNNE# H_DPRSTP# H_DPSLP# H_FERR# 6 within 2" from R379 6 6 +VCCP C 38 H_NMI H_SMI# 6 6 R315 56_0402_5% H_STPCLK# R319 6 2 54.9_0402_1% 1 H_THERMTRIP# 6,9 placed within 2" from ICH9M AG27 AH11 AJ11 AG12 AF12 7 3/28 add 56ohm 6 H_INIT# H_INTR KB_RST# 7,9,49 0.01U_0402_50V7K 2 1 C428 2 1 C429 SATA_TXN4_C SATA_TXP4_C SATA_TXN4 SATA_TXP4 SATA_RXN4_C SATA_RXP4_C SATA_TXN4 SATA_TXP4 29 29 29 29 SATA_RXN5_C SATA_RXP5_C SATA_TXN5 SATA_TXP5 36 36 36 36 De-feature disable ODD 0.01U_0402_50V7K SATALED# SATA5RXN SATA5RXP SATA5TXN SATA5TXP SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS 0.01U_0402_50V7K AH9 AJ9 AE10 AF10 AH18 AJ18 AJ7 AH7 SATA_TXN5_C SATA_TXP5_C 2 2 0.01U_0402_50V7K SATA_TXN5 1 C430 SATA_TXP5 1 C432 0.01U_0402_50V7K CLK_PCIE_SATA# CLK_PCIE_SATA R322 e-SATA CLK_PCIE_SATA# CLK_PCIE_SATA 17 17 1 2 24.9_0402_1% Within 500 mils ICH9-M ES_FCBGA676 B H_DPRSTP# 1 ICH_RTCRST# ICH_SRTCRST# SM_INTRUDER# RTCX1 RTCX2 LPC 1 CLRP2 SHORT PADS C23 C24 SATA 1U_0603_10V4Z 1 ICH_RTCX1 ICH_RTCX2 2 C427 21,33 34 34 R301 1 2 10K_0402_5% D Low = Internal VR Disabled High = Internal VR Enabled(Default) RTC R307 1 2 20K_0402_5% +RTCVCC 34 21,33 21,33 KB_RST# +VCCP ICH_LAN100_SLP U12A 21,33 34 34 GATEA20 ICH_INTVRMEN 2 1 LAN100_SLP +3VS R298 1 2 10K_0402_5% 1 R300 1 2 1 0_0402_5% 2 1 1 R299 SM_INTRUDER# 0_0402_5% 2 1 R297 2 1M_0402_5% 2 330K_0402_5% 2 330K_0402_5% 2 180K_0402_5% 2 ICH8M Internal VR Enable Strap (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5) ICH_INTVRMEN Low = Internal VR Disabled High = Internal VR Enabled(Default) +RTCVCC 1 3 B XOR CHAIN ENTRANCE STRAP:RSVD +3VS @ R326 1 2 1K_0402_5% HDA_SDOUT_CODEC 2 1K_0402_5% ICH_RSVD ICH_RSVD +RTCVCC 0821 Change C528 and C516 to 15PF 27 ICH_RTCX1 R328 1 HDA_SDOUT_CODEC C436 15P_0402_50V8J A 0 0 0 1 1 0 1 1 D8 R329 1 2 1 2 2 2 C437 1 15P_0402_50V8J 2 @ C439 10P_0402_25V8K 2 3 W=20mils R330 1 JBATT1 2 1 2 3 4 W=20mils 1K_0402_5% DAN202U_SC70 C438 2.2U_0603_6.3V4Z 1 2 GND GND ACES_85205-02001 CONN@ Place near ICH9 A Y2 1 4 2 3 32.768KHZ_12.5P_MC-146 Compal Secret Data Security Classification 2007/09/26 Issued Date 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 2 1 0_0402_5% 1 1 W=20mils W=20mils 10M_0402_5% ICH_RSVD BATT1.1 @ R327 10_0402_5% ICH_RTCX2 2 +3VL HDA_BITCLK 1 @ R325 1 4 3 2 Title Compal Electronics, Inc. ICH9(2/4)_LAN,HD,IDE,LPC Size Document Number Custom Montevina Consumer Date: Rev 0.1 Discrete Sheet Monday, October 08, 2007 1 26 of 51 4 2 1 2 2.2K_0402_5% 2 2.2K_0402_5% Place closely pin AF3 U12C R345 30,31 38 21,38 GPIO19 GPIO20 17,49 R353 1 2 100K_0402_5% GPIO22 6 GPIO36 38 38 GPIO37 R373 R380 B R381 LINKALERT# SB_SPKR XDP_DBRESET# TV 31 31 31 Tuner/WWAN/Robeson 31 EC_LID_OUT# PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1 C445 1 C444 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PCIE_RXN1 PCIE_RXP1 PCIE_C_TXN1 PCIE_C_TXP1 N29 N28 P27 P26 WLAN 31 31 31 31 PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3 C448 1 C449 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PCIE_RXN3 PCIE_RXP3 PCIE_C_TXN3 PCIE_C_TXP3 New Card 31 31 31 31 PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4 C450 1 C451 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PCIE_RXN4 G29 PCIE_RXP4 G28 PCIE_C_TXN4 H27 PCIE_C_TXP4 H26 32 32 reader 32 32 PCIE_RXN5 PCIE_RXP5 PCIE_TXN5 PCIE_TXP5 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PCIE_RXN5 PCIE_RXP5 PCIE_C_TXN5 PCIE_C_TXP5 E29 E28 F27 F26 30 30 30 30 GLAN_RXN GLAN_RXP GLAN_TXN GLAN_TXP GLAN_RXN GLAN_RXP 0.1U_0402_16V4Z GLAN_TXN_C 0.1U_0402_16V4Z GLAN_TXP_C C29 C28 D27 D26 EC_SMI# GPIO14 Card 1 R747 @ 10K_0402_5% C501 1 C500 1 C452 1 C453 1 2 2 GLAN 17/14 17" High 25 2 2 PAD PAD T61 T62 PAD PAD T63 T64 SPI_CS1#_R SPI_CS1#_R 14" Low 1 1 R748 10K_0402_5% UMA" Low RP27 5 6 7 8 36 BT_OFF 31 WXMIT_OFF# R383 1 2 0_0402_5% +3VALW 10K_1206_8P4R_5% RP28 5 6 7 8 USB_OC#0 USB_OC#1 USB_OC#2 WXMIT_OFF# USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11 USBRBIAS 1 4 3 2 1 J29 J28 K27 K26 D23 D24 F23 D25 E23 Dis" High 4 3 2 1 RSMRST# CLPWROK SLP_M# CL_CLK0 CL_CLK1 CL_DATA0 CL_DATA1 CL_VREF0 CL_VREF1 CL_RST0# CL_RST1# MEM_LED/GPIO24 GPIO10/SUS_PWR_ACK GPIO14/AC_PRESENT WOL_EN/GPIO9 PM_PWROK M2 R348 1 B13 ICH_LOW_BAT# R3 PWRBTN_OUT# 1 2 SATA GPIO LAN_RST# S4_STATE# G20 38 D 38 2 R346 9,38 1 DPRSLPVR PM_PWROK 2 0_0402_5% 1 @ C441 PWRBTN_OUT# 4.7P_0402_50V8C 2 4.7P_0402_50V8C 10K_0402_5% 2 9,49 38 D20 D22 R_EC_RSMRST# R5 CK_PWRGD R6 M_PWROK R354 1 2 100_0402_5% R355 1 2 10K_0402_5% CK_PWRGD 17 M_PWROK EC_RSMRST# 38 9,38 +3VS B16 F24 B19 CL_CLK0 F22 C19 CL_DATA0 C25 A19 CL_VREF0_ICH CL_VREF1_ICH F21 D18 CL_RST# A16 C18 C11 C20 XMIT_OFF GPIO10 GPIO14 LAN_WOL_EN CL_CLK0 9 0.1U_0402_16V4Z R360 2 3.24K_0402_1% CL_DATA0 1 9 1 C442 2 CL_RST# R363 453_0402_1% NA lead free +3VALW 9 XMIT_OFF 0.1U_0402_16V4Z R370 2 31 1 1 +3VALW 1 100K_0402_5% C443 C R367 2 3.24K_0402_1% R368 453_0402_1% 2 ICH9-M ES_FCBGA676 L29 L28 M27 M26 GPIO10 R746 @ 10K_0402_5% BATLOW# PWRBTN# CK_PWRGD SPKR MCH_SYNC# TP3 TP8 TP9 TP10 ME_EC_DATA1 DIS/UMA 10K_1206_8P4R_5% Within 500 mils N4 N5 N6 P6 M1 N2 M4 M3 N3 N1 P5 P3 AG2 AG1 PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5 DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP DMI_CLKN DMI_CLKP DMI_ZCOMP DMI_IRCOMP PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP SPI_CLK SPI_CS0# SPI_CS1#GPIO58/CLGPIO6 SPI SPI_MOSI SPI_MISO OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8#/GPIO44 OC9#/GPIO45 OC10#/GPIO46 OC11#/GPIO47 USB USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P V27 V26 U29 U28 DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 9 9 9 9 Y27 Y26 W29 W28 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 9 9 9 9 AB27 AB26 AA29 AA28 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 9 9 9 9 AD27 AD26 AC29 AC28 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 9 9 9 9 T26 T25 CLK_PCIE_ICH# CLK_PCIE_ICH AF29 AF28 DMI_IRCOMP AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2 CLK_PCIE_ICH# CLK_PCIE_ICH R382 1 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9 24.9_0402_1% 2 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9 B 17 17 Within 500 mils +1.5VS 36 USB-0 Right side 36 36 USB-1 Right side 36 36 USB-2 Left side(with ESATA) 36 40 USB-3 Dock 40 19 USB-4 Camera 19 31 USB-5 WLAN 31 36 USB-6 Bluetooth 36 36 USB-7 Finger Printer 36 31 USB-8 MiniCard(WWAN/TV) 31 31 USB-9 Express card 31 A USBRBIAS USBRBIAS# ICH9-M ES_FCBGA676 R384 22.6_0402_1% 2 RP29 WXMIT_OFF# USB_OC#5 USB_OC#10 USB_OC#11 M7 AJ24 B21 AH20 AJ20 AJ21 ME_EC_CLK1 Board ID USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#0 GPIO1 GPIO6 GPIO7 GPIO8 GPIO12 GPIO13 GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 GPIO27 GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5 S4_STATE# R745 10K_0402_5% A TP11 AG19 AH21 AG21 A21 C12 C21 AE18 K1 AF8 AJ22 A9 D19 L1 AE19 AG22 AF21 AH24 A8 DPRSLPVR/GPIO16 C10 SLP_S3# T60 PAD SLP_S5# U12D ICH_RI# +3VS USB_OC#6 USB_OC#1 USB_OC#2 USB_OC#4 VRMPWRGD ICH_PCIE_WAKE# 2 2 CLKREQ#_C 8.2K_0402_5% 17 CLKREQ#_C GPIO38 2 R393 1 2 0_0402_5% GPIO39 GPIO48 GPIO49 @ GPIO57 R366 1K_0402_5% 1 2 +3VS SB_SPKR MCH_ICH_SYNC# 9 MCH_ICH_SYNC# ICH_RSVD 26 ICH_RSVD R424 Low -->default High -->No boot ICH_LOW_BAT# +3VS 1 EC_SCI# EC_SMI# GPIO57 1 D21 PWROK 10_0402_5% 1 @ C440 om R379 OCP# GPIO6 EC_SCI# EC_SMI# GPIO48 R364 +3VS EXP_CPPE# WAKE# SERIRQ THRM# A20 T59 OCP# 17/14 GPIO18 GPIO20 GPIO22 DIS/UMA 31 CLKRUN# S4_STATE#/GPIO26 T58 PAD @ R343 l.c R378 L4 STP_PCI# STP_CPU# SLP_S3# SLP_S4# SLP_S5# 10_0402_5% ai R377 PM_CLKRUN# SMBALERT#/GPIO11 C16 E16 G17 @ R342 4 3 2 1 5 6 7 8 2007/09/26 Issued Date 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 10K_1206_8P4R_5% 5 Compal Secret Data Security Classification 4 3 2 Title Compal Electronics, Inc. nf @ ho tm R376 A14 E19 ICH_SUSCLK 17 17 ICH9(3/4)_DMI,USB,GPIO,PCIE Size Document Number Custom Montevina Consumer Date: Discrete ai R375 H_STP_PCI# R_STP_CPU# P1 CLK_14M_ICH CLK_48M_ICH CLK_14M_ICH Sheet Monday, October 08, 2007 1 he x R374 PAD GPIO39 33 R372 A17 VGATE GPIO21 1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 1K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% EC_LID_OUT# SLP_S3# SLP_S4# SLP_S5# PMSYNC#/GPIO0 ICH_PCIE_WAKE# E20 SIRQ M5 THERM_SCI# AJ23 ICH_PCIE_WAKE# SIRQ THERM_SCI# VGATE +3VALW R371 2 0_0402_5% 1 M6 SUSCLK CLK_14M_ICH CLK_48M_ICH 1 1 H_STP_PCI# H_STP_CPU# @ R369 EC_LID_OUT# PM_BMBUSY# SUS_STAT#/LPCPD# SYS_RESET# H1 AF3 Place closely pin H1 CLK_48M_ICH 2 R361 PM_BMBUSY# clocks RI# GPIO21 GPIO19 GPIO36 GPIO37 1 R359 R4 G19 CLK14 CLK48 AH23 AF19 AE21 AD20 2 R358 SUS_STAT# XDP_DBRESET# SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37 Direct Media Interface GPIO49 R357 XDP_DBRESET# 38 17 17 T57 SYS / GPIO 1 2 10K_0402_5% R356 6 @ R340 9 10K_0402_5% EC_SCI# R365 R352 @ R339 10K_0402_5% PM_BMBUSY# R362 R351 C PAD CLKREQ#_C GPIO18 R350 F19 SMB THERM_SCI# 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% 1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% R349 ICH_RI# SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1 Power MGT @ R338 +3VS 1 @ R337 D OCP# 2 @ R336 PM_CLKRUN# 2 R335 ICH_SMBCLK ICH_SMBDATA MISC GPIO Controller Link 1 2 8.2K_0402_5% GPIO6 R344 R334 17,21,31,37 17,21,31,37 G16 A13 E17 C17 B18 PCI - Express SIRQ R341 1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 10K_0402_5% 1 2 8.2K_0402_5% 1 2 8.2K_0402_5% R333 ICH_SMBCLK ICH_SMBDATA LINKALERT# ME_EC_CLK1 ME_EC_DATA1 1 R331 1 R332 1 +3VALW +3VS 3 2 5 27 of Rev 0.1 51 5 4 3 +RTCVCC 2 1 +VCCP U12E U12F 1 2 R386 2 ICH_V5REF_SUS AE1 10U_0805_10V4Z 1 C459 2 C460 2 1 C456 2 10U_0805_10V4Z 1 2 2.2U_0603_6.3V4Z D9 1 2 ICH_V5REF_RUN 1 2 20 mils C465 0.1U_0402_10V6K 2 1 1 2 C478 1U_0603_10V4Z 1 2 2 G10 G9 C483 C484 2 0.1U_0402_16V4Z 1 VCC1_5_A[21] VCC1_5_A[22] 11mA 11mA VCC1_5_A[23] VCC1_5_A[24] VCC1_5_A[25] VCCUSBPLL T69 T70 VCC_LAN1_05_INT_ICH_1 VCC_LAN1_05_INT_ICH_2 VCC1_5_A[26] VCC1_5_A[27] VCC1_5_A[28] VCC1_5_A[29] VCC1_5_A[30] A10 A11 VCCLAN1_05[1] VCCLAN1_05[2] 23mA 1 R390 1 CHB1608U301_0603 2 +1.5VS 1 2 C487 2.2U_0603_6.3V4Z 2 10U_0805_10V4Z C485 A27 4.7U_0805_10V4Z 2 D28 +1.5VS D29 CHB1608U301_0603 E26 1 C488 E27 1 VCCGLANPLL R391 1 2 C489 0316 change design +3VS 2 80mA VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] 1mA A26 VCCGLAN3_3 ICH9-M ES_FCBGA676 VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCCL1_05 VCCCL1_5 VCCLAN3_3[1] 19/78/78mA VCCLAN3_3[2] GLAN POWER 0.1U_0402_16V4Z A12 B12 A USB CORE AA7 AB6 AB7 AC6 AC7 +3VS +3VS 2 1 2 1 2 2 (DMI) C473 1 0.1U_0402_16V4Z AJ3 1 1 AC8 F17 T65 T66 AD8 VCCSUS1_5_ICH_1 A18 D16 D17 E22 2 2 2 AJ4 F18 1 1 0.1U_0402_16V4Z R741 2 0_0402_5% R740 2 0_0402_5% 0.1U_0402_16V4Z 1 C474 +3VALW C475 +3VS 2 2 T67 VCCSUS1_5_ICH_2 T68 0.1U_0402_16V4Z 1 2 VCCSUS3_3[05] VCC1_5_A[20] AJ5 2 212mA VCCSUS3_3[01] VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04] VCC1_5_A[18] VCC1_5_A[19] AC12 AC13 AC14 +1.5VS 0.1U_0402_16V4Z B9 F9 G3 G6 J2 J7 K7 1 1 +3VALW 1 2 AF1 VCC1_5_A[17] AC21 1 AD19 AF20 AG24 AC20 1 1342mA AC9 AC18 AC19 +1.5VS VCCSUS1_5[2] +VCCP 0.1U_0402_16V4Z C480 1 VCCSUS1_5[1] 2 +3VS AG29 AJ6 AC10 C479 C481 B VCC1_5_A[09] VCC1_5_A[10] VCC1_5_A[11] VCC1_5_A[12] VCC1_5_A[13] VCC1_5_A[14] VCC1_5_A[15] VCC1_5_A[16] VCCSUS1_05[1] VCCSUS1_05[2] ATX AC11 AD11 AE11 AF11 AG10 AG11 AH10 AJ10 +1.5VS 1U_0603_10V4Z VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05] VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08] VCCPSUS 2 VCCSUSHDA C464 AB23 AC23 VCCSATAPLL AC16 AD15 AD16 AE15 AF15 AG15 AH15 AJ15 +1.5VS VCCPUSB 1 ARX 2 C477 1 10U_0805_10V4Z 0316 change design AJ19 1U_0603_10V4Z C476 +1.5VS 11mA VCCHDA +VCCP 1 C468 R389 1 2 CHB1608U301_0603 W23 Y23 10U_0805_10V4Z C467 11mA 47mA R29 C463 0.1U_0402_16V4Z 0.1U_0402_10V6K 2 +1.5VS C466 2 C472 C461 2 308mA VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] VCC3_3[14] 1 0.1U_0402_16V4Z 1 VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06] 1 C471 20 mils VCC3_3[01] VCC3_3[02] VCC3_3[07] 2mA R385 1 2 CHB1608U301_0603 0.01U_0402_16V7K 0.1U_0402_16V4Z ICH_V5REF_SUS 48mA V_CPU_IO[1] V_CPU_IO[2] 2 C470 CH751H-40_SC76 VCCDMIPLL 23mA VCC_DMI[1] VCC_DMI[2] 2 T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7 G22 G23 +3VALW 1 2 VCCCL1_05_ICH C482 4.7U_0603_6.3V6M T71 4 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12] 19/73/73mA VCCCL3_3[1] VCCCL3_3[2] A24 B24 1 @ C486 1U_0603_10V4Z +3VS H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25 D C B A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29 ICH9-M ES_FCBGA676 A 2 Compal Secret Data Security Classification 2007/09/26 Issued Date 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 AA26 AA27 AA3 AA6 AB1 AA23 AB28 AB29 AB4 AB5 AC17 AC26 AC27 AC3 AD1 AD10 AD12 AD13 AD14 AD17 AD18 AD21 AD28 AD29 AD4 AD5 AD6 AD7 AD9 AE12 AE13 AE14 AE16 AE17 AE2 AE20 AE24 AE3 AE4 AE6 AE9 AF13 AF16 AF18 AF22 AH26 AF26 AF27 AF5 AF7 AF9 AG13 AG16 AG18 AG20 AG23 AG3 AG6 AG9 AH12 AH14 AH17 AH19 AH2 AH22 AH25 AH28 AH5 AH8 AJ12 AJ14 AJ17 AJ8 B11 B14 B17 B2 B20 B23 B5 B8 C26 C27 E11 E14 E18 E2 E21 E24 E5 E8 F16 F28 F29 G12 G14 G18 G21 G24 G26 G27 G8 H2 H23 H28 H29 0.1U_0402_16V4Z 1 C455 C469 10_0402_5% C 646mA 0.1U_0402_16V4Z 1 C457 0.1U_0402_16V4Z D10 2mA VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] VCC1_5_B[47] VCC1_5_B[48] VCC1_5_B[49] A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 0.1U_0402_16V4Z R388 V5REF_SUS VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26] 4.7U_0603_6.3V6M +5VALW +3VALW 1634mA 2mA 22U_0805_6.3VAM CH751H-40_SC76 G3: 6uA VCCA3GP 100_0402_5% V5REF AA24 AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE25 AE26 AE27 AE28 AE29 F25 G25 H24 H25 J24 J25 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T24 T27 T28 T29 U24 U25 V24 V25 U23 W24 W25 K23 Y24 Y25 1 + VCCRTC CORE 1 A6 VCCP_CORE +3VS 2 40 mils C458 220U_D2_4VM +5VS 1 A23 ICH_V5REF_RUN PCI R387 1 2 CHB1608U301_0603 +1.5VS D C454 0.1U_0402_16V4Z C462 0.1U_0402_16V4Z 20 mils 3 2 Title Compal Electronics, Inc. ICH9(4/4)_POWER&GND Size Document Number Custom Montevina Consumer Date: Rev 0.1 Discrete Sheet Friday, October 05, 2007 1 28 of 51 5 4 3 2 1 HDD Connector JP3 D Pleace near HD CONN 1 1 1 C491 2 1 C492 2 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 1 2 3 4 5 6 7 GND A+ AGND BB+ GND C493 0.1U_0402_16V4Z C490 10U_0805_10V4Z +5VS SATA_TXP0 SATA_TXN0 0.01U_0402_16V7K SATA_RXN0 2 SATA_RXP0 2 0.01U_0402_16V7K SATA_TXP0 SATA_TXN0 1 C494 SATA_RXN0_C 1 C495 SATA_RXP0_C 26 26 SATA_RXN0_C SATA_RXP0_C 26 26 D Near CONN side. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12 +3VS +5VS SUYIN_127072FR022G523_RV CONN@ CD-ROM Connector +5VS C 2 10U_0805_10V4Z 1 C514 2 1U_0603_10V4Z 2 1 C513 C512 0.1U_0402_16V4Z 1 JP5 Placea caps. near ODD CONN. GND A+ AGND BB+ GND 1 2 C515 10U_0805_10V4Z DP V5 V5 MD GND GND 13 12 11 10 9 8 7 SATA_TXP4 SATA_TXN4 0.01U_0402_16V7K SATA_RXN4 2 SATA_RXP4 2 0.01U_0402_16V7K SATA_TXP4 SATA_TXN4 1 C510 SATA_RXN4_C 1 C511 SATA_RXP4_C SATA_RXN4_C SATA_RXP4_C C 26 26 26 26 Near CONN side. 6 5 4 3 2 1 +5VS SUYIN_127382FR013GX09ZR CONN@ Multi Bay Connector JP12 +5VS B Placea caps. near ODD CONN. C519 MultiBay@ 1 2 10U_0805_10V4Z 2 1U_0603_10V4Z 1 C518 C517 2 0.1U_0402_16V4Z 1 GND TX+ TXGND RXRX+ GND GND GND GND VCC3 VCC3 VCC3 VCC5 VCC5 VCC5 1 2 C516 10U_0805_10V4Z MultiBay@ MultiBay@ MultiBay@ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 B SATA_TXP1 SATA_TXN1 SATA_TXP1 SATA_TXN1 SATA_RXN1 C822 2 SATA_RXP1 C823 2 26 26 1 0.01U_0402_16V7K 1 0.01U_0402_16V7K MultiBay@ MultiBay@ SATA_RXN1_C SATA_RXP1_C SATA_RXN1_C SATA_RXP1_C 26 26 Near CONN side. +5VS JAE_WM2M016JPA CONN@ A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. HDD & CDROM Size Document Number Custom Montevina Consumer Date: Discrete ai 2007/09/26 Deciphered Date Sheet Monday, October 08, 2007 1 he x 2007/09/26 nf @ ho tm Compal Secret Data Security Classification Issued Date ai l.c om A 29 of Rev 0.1 51 5 4 3 2 1 +3V_LAN C1403 +3V_LAN U43 1 2 3 4 D A0 A1 NC GND VCC WP SCL SDA 8 7 6 5 AP2305GN Turn off power when S3. 06/14 Q106 1 3 S 10K_0402_5% CLKREQ#_9 1 10K_0402_5% ICH_PCIE_WAKE# 1 10K_0402_5% LAN_LOM_DIS 1 +3VALW R1106 0_1206_5% 1 2 @ D R1107 2 R1110 2 R1111 2 R1108 1K_0402_5% 2 1 0.1U_0402_16V4Z LAN_EE_CLK LAN_EE_DATA 38 CAT24C08WI-GT3 SO 8P D 2 G +3V_LAN 1 R1109 1K_0402_5% 2 1 2 LAN_POWER_OFF +3V_LAN U44 17 27 27 27 27 27,31 17 17 9,20,25,31,32 CLKREQ#_9 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 42 1 C1404PCIE_RXP2_LAN 49 1 C1405PCIE_RXN2_LAN 50 54 53 ICH_PCIE_WAKE# 6 55 R1112 0_0402_5% 56 1 2 5 CLKREQ#_9 GLAN_RXP GLAN_RXN GLAN_TXP GLAN_TXN ICH_PCIE_WAKE# CLK_PCIE_LAN CLK_PCIE_LAN# PLT_RST# LAN_MDI0+ LAN_MDI0LAN_MDI1+ LAN_MDI1LAN_MDI2+ LAN_MDI2LAN_MDI3+ LAN_MDI3- 17 18 20 21 26 27 30 31 LAN_EE_CLK LAN_EE_DATA 38 41 34 35 37 36 C +3VS LAN_X1 LAN_X2 +3V_LAN 15 14 LAN_LOM_DIS +3V_LAN C1425 1 3 4.7U_0805_10V4Z 2 R1113 R1114 2 10 12 11 47 9 16 4 3 4.99K_0402_1% CTRL18 CTRL12 4.7K_0402_5% 1 LED CLKREQn TX_P TX_N RX_P RX_N WAKEn REFCLKP REFCLKN PERSTn PCI-E LED_ACTn LED_LINK10/100n LED_LINK1000n LED_DUPLEXn TEST TESTMODE AVDDH AVDD AVDD AVDD AVDD POWER MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3 Media VPD_CLK VPD_DATA EEPROM SPI_DO SPI_DI SPI_CLK SPI_CS FLASH MEMORY XTALI XTALO CLOCK & LOM_DISABLEn VAUX_AVLBL SWITCH_VCC VMAIN_AVLBL SWITCH_VAUX RSET Analog CTRL18 CTRL12 GROUND VDDO_TTL VDDO_TTL VDDO_TTL VDDO_TTL VDD VDD VDD VDD VDD VDD VDD VDD VSS No Connect NC NC NC NC NC Reserved Reserved Reserved Reserved 1 LAN_ACT# 59 60 62 63 2 LANLINK_STATUS# 46 1 C1406 0.1U_0402_16V4Z 2 1 C1407 0.1U_0402_16V4Z 2 1 C1408 0.1U_0402_16V4Z 2 1 C1409 0.1U_0402_16V4Z 2 C1410 0.1U_0402_16V4Z +3V_LAN 8 V1.8_LAN 19 22 23 28 V1.8_LAN 0.1U_0402_16V4Z +3V_LAN 1 1 C1411 1 40 45 61 2 2 1 C1412 0.1U_0402_16V4Z 2 1 C1413 0.1U_0402_16V4Z 2 1 C1414 0.1U_0402_16V4Z 2 1 C1415 0.1U_0402_16V4Z 2 1 C1416 0.1U_0402_16V4Z 2 1 C1417 0.1U_0402_16V4Z 2 C1418 0.1U_0402_16V4Z V1.2_LAN 2 7 13 33 39 44 48 58 65 V1.2_LAN 1 2 V1.8_LAN 1 C1419 0.1U_0402_16V4Z 2 1 C1420 0.1U_0402_16V4Z 2 1 C1421 0.1U_0402_16V4Z 2 1 C1422 0.1U_0402_16V4Z 32 51 52 57 64 2 C C1424 0.1U_0402_16V4Z V1.2_LAN for power saving 24 25 29 43 2 1 C1423 0.1U_0402_16V4Z 1 2 Q107 1 C1426 0.1U_0402_16V4Z 2 1 C1427 0.1U_0402_16V4Z 2 C1428 0.1U_0402_16V4Z 88E8072_QFN64 CTRL12 1 2SB1188T100R_SC62-3 +3V_LAN B 7/31 R1116 2 4.7K_0402_5% 1 2 1 300_0402_5% LAN_X1 LAN_X2 C1433 27P_0402_50V8J 1 2 CTRL18 C1434 1 13 40 RJ45_MIDI3- 40 RJ45_MIDI3+ RJ45_MIDI3+ 7 40 RJ45_MIDI1- RJ45_MIDI1- 6 40 RJ45_MIDI2- RJ45_MIDI2- 5 40 RJ45_MIDI2+ RJ45_MIDI2+ 4 RJ45_MIDI1+ 8 RJ45_MIDI1+ RJ45_MIDI0- RJ45_MIDI0- 2 RJ45_MIDI0+ RJ45_MIDI0+ 1 +3V_LAN R1117 2 Yellow LEDSHLD1 PR4DETECT PIN1 1 300_0402_5% LANLINK_STATUS# 9 PR2B PR3PR3+ PR2+ PR1DETCET PIN2 PR1+ SHLD1 11 10 15 Green LED+ 12 V1.8_LAN 16 PR4+ 3 40 40 40 Yellow LED+ 14 RJ45_MIDI3- 2 2SB1188T100R_SC62-3 4.7U_0805_6.3V6K R1115 2 LAN_ACT# Q108 1 V1.8_LAN +3V_LAN Y6 25MHZ_20P_1BG25000CK1A 1 C1432 1 3 4.7U_0805_10V4Z 2 CONN@ JRJ45 C1431 27P_0402_50V8J 1 2 C1430 1 2 2 22U_0805_6.3VAM 2 V1.2_LAN Green LEDFOX_JM36113-P1122-7F T72 A 2 1 C1435 0.1U_0402_16V4Z TRM_CT LAN_MDI3+ LAN_MDI3- 2 1 C1436 0.1U_0402_16V4Z TRM_CT LAN_MDI2+ LAN_MDI2- 4 5 6 2 1 C1439 0.1U_0402_16V4Z TRM_CT LAN_MDI1+ LAN_MDI1- 7 8 9 2 1 C1440 0.1U_0402_16V4Z TRM_CT LAN_MDI0+ LAN_MDI0- 10 11 12 1 2 3 TCT1 TD1+ TD1- MCT1 MX1+ MX1- TCT2 TD2+ TD2- MCT2 MX2+ MX2- TCT3 TD3+ TD3- MCT3 MX3+ MX3- TCT4 TD4+ TD4- MCT4 MX4+ MX4- 24 23 22 RJ45_MIDI3+ RJ45_MIDI3- 21 20 19 RJ45_MIDI2+ RJ45_MIDI2- 18 17 16 RJ45_MIDI1+ RJ45_MIDI1- 15 14 13 RJ45_MIDI0+ RJ45_MIDI0- 2 R1118 1 75_0402_1% LAN_ACT# 2 2 R1119 1 75_0402_1% 1 LANLINK_STATUS# 2 @ C1437 300p_0402_25V 1 @ C1438 300p_0402_25V 2 R1120 1 75_0402_1% 2 R1121 1 75_0402_1% C1441 1 2 A 1000P_1808_3KV7K 1115 EMI REQUEST 0.5u_GST5009 Compal Secret Data Security Classification 2007/09/26 Issued Date 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. LAN-88E8072 Size Document Number Rev 0.1 LA-3821P Date: Friday, October 05, 2007 Sheet 1 30 of 51 B C D Mini Card 2---WLAN Mini Card 0--TV tuner/WWAN/Robson SIM card Connector 0.01U_0402_16V7K +3VS_WWAN CONN@ JP6 ICH_PCIE_WAKE# CH_DATA CH_CLK CLKREQ#_10 CLKREQ#_10 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 CLK_PCIE_MCARD0# CLK_PCIE_MCARD0 1 R419 1 R421 PCIE_RXN1 PCIE_RXP1 0_0402_5% 2 PCIE_C_RXN1 2 PCIE_C_RXP1 0_0402_5% PCIE_TXN1 PCIE_TXP1 PCIE_TXN1 PCIE_TXP1 +3VS_WWAN R427 1 1 R428 0_0603_5% 2 2 0_0603_5% 2 53 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 +1.5VS_WLAN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND1 WXMIT_OFF# 2 36 36 17 17 ICH_SMBCLK ICH_SMBDATA USB20_N8 USB20_P8 17 27 27 CLK_PCIE_MCARD2# CLK_PCIE_MCARD2 CLK_PCIE_MCARD2# CLK_PCIE_MCARD2 R704 1 0_0402_5% R423 1 2 R425 1 2 0_0402_5% CLK_DEBUG_PORT_1 +3VALW +3VS_WWAN ICH_PCIE_WAKE# CH_DATA CH_CLK CLKREQ#_6 CH_DATA CH_CLK CLKREQ#_6 17 2 0_0402_5% 2 0_0402_5% +1.5VS_WLAN PCIE_RXN3 PCIE_RXP3 27 27 27 27 PLT_RST# 2 0_0402_5% DEBUG@ PCIE_C_RXN3 PCIE_C_RXP3 PCIE_TXN3 PCIE_TXP3 PCIE_TXN3 PCIE_TXP3 +3VS_WLAN +3VS_WWAN +1.5VS_WLAN +3VS_WWAN @ R440 @ R441 +3VS_WWAN 47K_0402_5% 147K_0402_5% 2 1 2 UIM_PWR UIM_DATA 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 +1.5VS R431 1 +3VS R432 1 2 0_1206_5% +1.5VS_WLAN R418 1 2 0_1206_5% CH751H-40_SC76 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 GND1 +3VS_WLAN R699 R700 R701 R702 R703 2 0_1206_5% XMIT_OFF# PLT_RST# R424 1 @ R426 1 WWAN_POWER_OFF C579 1 2 0.1U_0402_16V4Z C580 1 2 0.1U_0402_16V4Z 17 +3VALW 9,20,25,30,32 PLT_RST# 38,39,41,47,50 SYSON 33,38,41,44,46,47,48 SUSP# +3VALW 27 EXP_CPPE# 2 4 PLT_RST# 6 SYSON 20 SUSP# 1 R439 1 2 100K_0402_5% EXP_CPPE# 10 9 18 S 3.3Vin 3.3Vin 3.3Vout 3.3Vout AUX_OUT OC# SHDN# PERST# STBY# NC CPPE# 2 +3VS_WLAN +3VALW @ R434 100K_0402_5% @ R433 10K_0402_5% XMIT_OFF# D S 2 G XMIT_OFF @ Q10 2N7002_SOT23-3 +3VS_PEC 1.5Vout 1.5Vout SYSRST# 39 Near to Express Card slot. 1.5Vin 1.5Vin AUX_IN 27 27 R435 1 2 0_0402_5% U16 12 14 26,37,38 26,37,38 26,37,38 26,37,38 26,37,38 +3VALW +3VS +1.5VS_WLAN WL_LED# 2 Express Card Power Switch +3VS LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 +1.5VS_WLAN C585 +1.5VS GND 11 13 +1.5VS_PEC 3 5 +3VS_PEC 15 +3V_PEC 27 27 27,30 19 8 R436 R437 USB20_N9 USB20_P9 17,21,27,37 17,21,27,37 Close to JEXP 2 0_0402_5% 1 2 0_0402_5% 1 CONN@ JEXP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 USB10USB10+ CPUSB# ICH_SMBCLK ICH_SMBDATA ICH_SMBCLK ICH_SMBDATA R438 1 2 0_0402_5% ICH_PCIE_WAKE# +1.5VS_PEC +1.5VS_PEC +3V_PEC PERST# PCIE_PME#_R PERST# +3VS_PEC 16 17 7 17 17 CLKREQ#_4 CPUSB# CLKREQ#_4 CLK_PCIE_NCARD# CLK_PCIE_NCARD CPUSB# RCLKEN R5538D001-TR-F_QFN20_4X4~D internal pull high to 3.3Vaux-in EC need setting at Hi-Z & output Low 27 27 PCIE_RXN4 PCIE_RXP4 27 27 PCIE_TXN4 PCIE_TXP4 27 28 3 4.7U_0805_10V4Z GND USB_DUSB_D+ CPUSB# RSV RSV SMB_CLK SMB_DATA +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PERn0 PERp0 GND PETn0 PETp0 GND GND GND 1 1 C577 C578 2 2 0.1U_0402_16V4Z +1.5VS_PEC 1 4.7U_0805_10V4Z 1 C581 C582 2 2 0.1U_0402_16V4Z +3V_PEC 4.7U_0805_10V4Z 1 1 C583 2 0.1U_0402_16V4Z 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. WLAN, WWAN, New Card Size Document Number Rev 0.1 Montevina Consumer Discrete Date: ai 2007/09/26 nf @ ho tm Compal Secret Data Security Classification Issued Date ai l.c SANTA_131851-A_LT 4 C584 2 Friday, October 05, 2007 Sheet E he x 4 2 0_0402_5% 2 0_0402_5% New Card C576 1 2 0.1U_0402_16V4Z DEBUG@ DEBUG@ DEBUG@ DEBUG@ DEBUG@ USB20_N5 USB20_P5 @ 3 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% ICH_SMBCLK ICH_SMBDATA 54 GND2 +3VS_WLAN 27 3 D +1.5VS_WLAN 1 2 1 2 1 2 1 2 1 2 2 G 38 1 C571 2 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 18P_0402_50V8J Q115 2 0.1U_0402_16V4Z UIM_CLK AP2305GN @ 1 1 C570 FOX_AS0B226-S40N-7F +3VALW M_WXMIT_OFF# 2 1 CONN@ JP7 UIM_PWR UIM_DATA UIM_CLK UIM_RST UIM_VPP M_WXMIT_OFF# PLT_RST# @R420 @ R420 1 R422 1 2 C569 8 9 G1 G2 53 0811 Pins 37 and 43 connect to GND and remove +1.5VS 2 2 4.7U_0805_10V4Z FOX_AS0B226-S40N-7F 0821 Change +3VS to +3VS_WWAN D11 1 1 2 3 4 5 6 7 ACES_88266-07001 54 GND2 1 2 3 4 5 6 7 1 C568 om 0.1U_0402_16V4Z 27 27 27 UIM_PWR UIM_DATA UIM_CLK UIM_RST UIM_VPP 1 1 C575 2 C567 2 1 C574 2 1 C566 1 27 27 1 2 17 17 17 C573 JP4 C572 2 1 3 1 4.7U_0805_10V4Z 0.1U_0402_16V4Z +3VS_WWAN 1 0.1U_0402_16V4Z 1 1 4.7U_0805_10V4Z +3VALW 2 0.01U_0402_16V7K +1.5VS_WLAN +3VS_WLAN +3VS_WWAN +3VALW E 0.1U_0402_16V4Z A 31 of 51 5 4 3 2 1 +1.8VS_CR +3VS XDCD0#_SDCD# XDCD1#_MSCD# C1326 10U_0805_10V4Z +VCC_4IN1 2 1 2 C1327 0.1U_0402_16V4Z 1 2 C1328 2 +VCC_OUT C1329 0.1U_0402_16V4Z +VCC_4IN1 @ 1000P_0402_50V7K R1128 0_0603_5% 1 +3VS 2 +3VS 1 10K_0402_5% 1 10K_0402_5% 2 2 XDWP#_SDWP# XD_RB# U36 17 17 27 27 +3VS XD_CLE 2 200K_0603_5% XD_RE# XD_ALE R1046 R1048 27 27 C1321 2 C1322 2 PCIE_RXN5 PCIE_RXP5 1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z PCIE_C_RXN5 PCIE_C_RXP5 +3VS R1047 2 1 10K_0402_5% PREXT R972 1 2 10K_0402_5% 11 12 PCIES_EN PCIES 19 XDCE# 2 1 2 @ R706 100_0402_5% SDCLK 1 2 1 9,20,25,30,31 @ C788 100P_0402_25V8K 1 @ R707 100_0402_5% 2 XRSTN XTEST 13 14 @ C789 100P_0402_25V8K JMB385 REG_CTRL 1 2 PLT_RST# DV33 DV33 DV18 DV18 APREXT 38 39 +3VS TAV33 APTXN APTXP 7 XIN APVDD APV18 APRXN APRXP 2 200K_0402_5% 2 200K_0402_5% 1 1 1 APCLKN APCLKP 9 8 PCIE_TXN5 PCIE_TXP5 R709 1 3 4 CLK_SRC11# CLK_SRC11 SEEDAT SEECLK MDIO0 MDIO1 MDIO2 MDIO3 MDIO4 MDIO5 MDIO6 MDIO7 MDIO8 MDIO9 MDIO10 MDIO11 MDIO12 MDIO13 MDIO14 C MSCLK 1 2 1 @ R708 100_0402_5% XDCD1#_MSCD# XDCD0#_SDCD# 2 @ C790 100P_0402_25V8K 15 16 use for PWR_EN# R710 R711 R712 SDCLK_MSCLK_XDCE# 1 1 1 2 22_0402_5% 2 22_0402_5% 2 22_0402_5% SDCLK MSCLK XDCE# CR_LED# NC NC NC CR1_CD1N CR1_CD0N APGND 17 +VCC_OUT CR1_PCTLN 21 GND GND GND GND CR1_LEDN 8mA sink current C1324 10U_0805_10V4Z 5 10 2 C1336 0.1U_0402_16V4Z 1 C1334 0.1U_0402_16V4Z 30 20 44 18 37 1 2 2 XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 SDCMD_MSBS_XDWE# SDCLK_MSCLK_XDCE# XDWP#_SDWP# XD_CLE XD_D4 XD_D5 XD_D6 XD_D7 XD_RE# XD_RB# XD_ALE C1332 0.1U_0402_16V4Z 2 C1325 0.1U_0805_50V7M C1335 0.1U_0402_16V4Z Use 0603 type and over 20 mils trace width on both side +1.8VS_CR 48 47 46 45 43 42 41 40 29 28 27 26 25 23 22 D 1 1 1 2 2 C1333 0.1U_0402_16V4Z +VCC_4IN1 +VCC_OUT 40mil +3VS 34 35 36 3 4 6 1 C1330 0.1U_0402_16V4Z 24 31 32 33 C U37 2 VIN VOUT VIN/CE VOUT 1 5 1 R1044 R1043 1 GND RT9701CB_SOT25 2 C1331 2 1U_0603_10V4Z 2 D 1 1 2 4.7K_0402_5% 2 4.7K_0402_5% 2 1 R1042 1 R1041 1 @ R1050 150K_0402_5% JMB385-LGEZ0A_LQFP48_7X7 reserved power circuit Layout must add a thermal pad pin49 D42 XDCD1#_MSCD# 2 XDCD0#_SDCD# 3 1 DAN202U_SC70 1 2 XD_CD# C1047 270P_0402_50V7K +1.8VS_CR +1.8VS Card Reader Connector U35 B White LED: VF=3V, IF = 5mA, Res = 56ohm 1 +5VALW_LED 2 2 R719 56_0402_5% D15 S1-023459_AQUA-WHITE_0603 +VCC_4IN1 33 XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 XD_D4 XD_D5 XD_D6 XD_D7 8 9 26 27 28 30 31 32 SDCMD_MSBS_XDWE# XDWP#_SDWP# XD_ALE XD_CD# XD_RB# XD_RE# XDCE# XD_CLE 6 7 5 34 1 2 3 4 3 1 13 22 47K XD-VCC XD-D0 XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7 SD-VCC MS-VCC 4 IN 1 CONN XD-WE XD-WP XD-ALE XD-CD XD-R/B XD-RE XD-CE XD-CLE SD_CLK SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-CMD SD-CD-SW SD-WP-SW MS-SCLK MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 MS-INS MS-BS 4IN1 GND 4IN1 GND 23 14 R705 +VCC_4IN1 1 2 0_0805_5% B 24 25 29 10 11 12 36 SDCLK XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 SDCMD_MSBS_XDWE# XDCD0#_SDCD# 35 XDWP#_SDWP# 15 19 20 18 16 17 21 MSCLK XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 XDCD1#_MSCD# SDCMD_MSBS_XDWE# Q103 10K 2 CR_LED# 37 38 DTA114YKAT146_SOT23-3 4IN1 GND 4IN1 GND 1 TAITW_R015-312-LM CONN@ A A Compal Secret Data Security Classification Issued Date 2007/09/26 Deciphered Date 2007/09/26 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. USB CardReader&CONN Size Document Number Custom Montevina Consumer Date: Rev 0.1 Discrtet Friday, October 05, 2007 Sheet 1 32 of 51 A B C D E CODEC POWER 0212_Change to +5VALW. +3VS_HDA +3VS 2 1 2 C1341 +VDDA_CODEC 1 +VDDA_CODEC +5VALW W=40Mil R1053 1 2 0_0603_5% 1 2 1 31,38,41,44,46,47,48 (4.75V) 300mA U39 2 0.1U_0402_16V4Z 3 SUSP# 2 VIN OUT 5 1 GND SHDN# BP C1343 1 C1340 1U_0603_10V4Z +VDDA_CODEC_R C1339 0.1U_0402_16V4Z 2 C1338 0.1U_0402_16V4Z 2 C1337 1U_0603_10V4Z C1342 1 +3VS 0.1U_0402_16V4Z 1 +3VDD_CODEC R1052 1 2 BLM18BD601SN1D_0603 1 4 GMT_G9191-475T1U_SOT23-5 1 2 2.2U_0805_16V4Z R1051 1 2 BLM18BD601SN1D_0603 1 C1344 0208_Change SLP_S3# to SUSP#. 2 0.1U_0402_16V4Z U38 9 +3VDD_CODEC 1 25 +VDDA_CODEC_R 38 DVDD_CORE* EAPD/ SPDIF OUT 0 or 1 / GPIO 0 DVDD_CORE VOL_UP/DMIC_0/GPIO 1 VOL_DN/DMIC_1/GPIO 2 AVDD1* GPIO 3 AVDD2** VREFOUT-E / GPIO 4 3 +3VS_HDA 32 1 26 @ R1054 47_0402_5% 26 HDA_SDOUT_CODEC @ C1345 33P_0402_50V8K 1 21,26 2 HDA_RST#_CODEC 19 27 SB_SPKR @ C1358 1 2 0.1U_0402_16V4Z 5 2 2 10K_0402_5% HDA_RST#_CODEC 11 47K_0402_5% C1347 1 C1348 22_0402_5% 2 33 2 1 1U_0603_10V4Z MONO_INR 12 2 0.1U_0402_16V4Z 40 40 +VDDA_CODEC_R SENSE_B# R1062 1 R1063 1 2 5.1K_0402_1% 2 39.2K_0402_1% SENSEB# 37 C1353 0.1U_0402_16V4Z 18 2 19 20 @ C1361 1 2 0.1U_0402_16V4Z R1065 1 R1066 1 C1355 10U_0805_10V4Z 1 2 GPIO 6 SPDIF OUT1 / GPIO 7 BITCLK SPDIF OUT0 VC_REFA 27 42 7 2 0_1206_5% SDI_CODEC VREFOUT-B SYNC VREFOUT-C GNDA 4 30 31 43 44 45 2 48 SPDIF_OUT 28 VREFOUT_B SPDIF_OUT 21,40 SENSE_A PORTA_R PCBEEP PORTA_L 35 +VDDA_CODEC_R R1056 R1057 R1059 R683 C1346 13 SENSE 41 HP_OUTR 39 HP_OUTL 22 MIC_EXTR 21 MIC_EXTL DMIC_CLK CAP2 VREFOUT_B 29 RESET# PORTB_R NC / OTP PORTB_L 1 1 1 1 1 2 HP_OUTR 2 5.1K_0402_1% 2 20K_0402_1% 2 39.2K_0402_1% 2 10K_0402_1% 0.1U_0402_16V4Z EXTMIC_DET# JACK_DET# INTMIC_DET# 35 35,40 35 35 HP Jack & Dock HP_OUTL SENSE_B / NC NC PORTC_R NC PORTC_L NC PORTD_R NC VREFFILT PORTE_R AVSS1* PORTE_L AVSS2** PORTF_R DVSS** PORTF_L 2 0_1206_5% 38 19 SDO PORTD_L 26 2 0_1206_5% 35 1 C1350 1 C1351 2 1U_0603_10V6K 2 1U_0603_10V6K 24 MIC_INR 23 MIC_INL 36 LINE_OUT_R 35 LINE_OUT_L 15 DOCK_MICR 14 DOCK_MICL 1 C1352 2 1U_0603_10V6K MIC_EXT_R 35 MIC_EXT_L MIC_IN_R 35 35 MIC_IN_L 35 Jack MIC @ R1064 0_0603_5% LINE_OUT_R 35 LINE_OUT_L Internal 35 1 C1356 1 C1357 C1354 1 Internal MIC 1U_0603_10V6K 2 SPKR. 3 2 DOCK_MIC_R 1U_0603_10V6K 2 40 DOCK MIC DOCK_MIC_L 1U_0603_10V6K 40 17 16 92HD71B7X5NLGXA1X8_QFN48_7X7 35,40 GNDA SENSE A SENSE B Resistor Port Resistor A 39.2K E 39.2K B 20K F 20K C 10K G 10K 4 H A 5.11K 2007/09/26 Deciphered Date C Title Codec_IDT9271B7 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B nf @ ho tm 5.11K D Size Document Number Custom Date: Rev 0.1 Montevina Consumer UMA ai 2007/09/26 Sheet Friday, October 05, 2007 E he x D Compal Secret Data Security Classification Issued Date ai l.c Port om GND 4 34 1 @ C1360 1 2 0.1U_0402_16V4Z R1067 1 46 MONO_OUT DMIC_DAT 2 0.1U_0402_16V4Z @ C1359 1 2 0.1U_0402_16V4Z 3 8 10 R1058 1 R1061 1 1 2 33_0402_5% HDA_SYNC_CODEC DMIC_CLK R1060 1 C1349 HDA_SDOUT_CODEC R1055 1 HDA_SDIN0 HDA_SYNC_CODEC 2 21,26 HDA_BITCLK_CODEC 6 EAPD_CODEC 1 21,26 HDA_BITCLK_CODEC HDA_BITCLK_CODEC GPIO 5 EAPD_CODEC 2 2 2 DVDD_IO 47 33 of 51 5 4 3 2 1 MDC 1.5 Conn. D 13 14 15 16 17 18 1 R475 @1 R476 2 0_0603_5% 2 0_0603_5% +1.5VS +3VS +3VS +3VS HDA_BITCLK_MDC 2 @ R478 10_0402_5% 1 1 2 @ C618 10P_0402_25V8K ACES_88018-124G 26 1 2 Connector for MDC Rev1.5 1 2 @C621 @ C621 2 4 6 8 10 12 1 2 4.7U_0805_10V4Z 1 R477 RES0 RES1 3.3V GND3 GND4 IAC_BITCLK C620 HDA_SYNC_MDC HDA_SDIN1 HDA_RST#_MDC HDA_SYNC_MDC 2 HDA_SDIN1_MDC 33_0402_5% GND1 IAC_SDATA_OUT GND2 IAC_SYNC IAC_SDATA_IN IAC_RESET# GND GND GND GND GND GND 26 26 26 HDA_SDOUT_MDC HDA_SDOUT_MDC C619 26 0.1U_0402_16V4Z JP8 1 3 5 7 9 11 1000P_0402_50V7K D C C B B A A Compal Secret Data Security Classification 2007/09/26 Issued Date 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. MDC 1.5 & Robson Size Document Number Rev 0.1 Montevina Consumer Discrete Date: Friday, October 05, 2007 Sheet 1 34 of 51 B C +5VAMP D R1133 1 2 0_1206_5% JP60 10 dB 1 2 LINE_OUT_R C1482 1 GAIN1 20K_0402_5% C1483 C1484 1 1 C1485 RINROUT+ 2 0.47U_0603_16V7K 2 47P_0402_50V8J 9 2 0.47U_0603_16V7K 2 47P_0402_50V8J 5 ROUT- 2 LINE_OUT_L C1486 1 20K_0402_5% 1 1 C1487 LINLOUT- SHUTDOWN 20 13 11 1 GND1 GND2 GND3 GND4 EC_MUTE# 1 @ D55 PSOT24C_SOT23-3 D56 @ PSOT24C_SOT23-3 3 18 SPKR+ 14 SPKR- 4 SPKL+ 8 SPKL- @ R1137 R1138 100K_0402_5% 8/31EMI request BYPASS 12 Keep 10 mil width 10 Audio/B & CIR 1 C1488 2 10U_0805_10V4Z 2 JP49 MIC_EXT_R MIC_EXT_L 21 38 2 THERMAL PAD NC 19 1 ACES_85204-04001 CONN@ 100K_0402_5% LOUT+ EC_MUTE# 2 2 LIN+ R1139 33 2 1 C1378 1 17 R1136 33 2 2 0.47U_0603_16V7K 2 47P_0402_50V8J GAIN0 1 1 1 C1481 RIN+ 2 1 C1377 1 2 3 4 G1 G2 2 7 2 2 0.47U_0603_16V7K 2 47P_0402_50V8J 1 1 1 2 @ R1135 100K_0402_5% 2 C1480 R1134 100K_0402_5% 1 C1376 1 2 3 4 5 6 1 VDD PVDD1 PVDD2 1 16 15 6 C1375 0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5% 2 2 2 2 2 0.1U_0402_16V4Z 1 1 1 1 1 3 +5VS R1102 R1103 R1104 R1105 2 SPKL+ SPKLSPKR+ SPKR- 2 3 C1479 2 SPEAKER SP02000D000 S W-CONN ACES 85204-04001 4P P1.25 1 100P_0402_50V8J C1478 2 1 100P_0402_50V8J C1477 10U_0805_10V4Z 1 100P_0402_50V8J 0.1U_0402_16V4Z U40 E +5VS 9/21 follow 14" AMD 100P_0402_50V8J A TPA6017A2_TSSOP20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 HP_OUT_R HP_OUT_L 33 EXTMIC_DET# HP_DET# EXTMIC_DET# 38,40 CIR_IN CIR_IN +5VL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ACES_87213-1400G CONN@ 33,40 JACK_DET# B+ S 1 1 Q49 D 2N7002_SOT23-3 3 2 +3VALW R678 330K_0402_5% 2 G 1 2 R676 10K_0402_5% 3 40 S DOCK_LOUT_L 38 R684 2 1 0_0402_5% VREFOUT_B C787 1 1 33 + R685 1 2 + 2 1U_0603_10V4Z 33 100U_D2_6.3VM 2 G 2 G S S 2 2N7002_SOT23-3 Q109 2N7002_SOT23-3 GND1 GND2 ACES_88231-04001 CONN@ D D Q110 1 2 3 4 HP OUT For M/B 33 MIC_EXT_R MIC_EXT_R 33 MIC_EXT_L MIC_EXT_L EXTMIC IN 4 2007/09/26 Deciphered Date A B C Title AMP & Audio Jack D Size Document Number Custom Date: Montevina Consumer Discrete ai THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Sheet Friday, October 05, 2007 E he x 2007/09/26 nf @ ho tm Compal Secret Data Security Classification Issued Date ai l.c om 4 2 INTMIC_DET# 4.7K_0402_5% 2 HP_OUT_L 5 6 2 R686 4.7K_0402_5% 1 1 10K_0402_5% ANA_MIC_DET HP_OUT_R 100U_D2_6.3VM C786 2 R681 +3VS 40 1 D DOCK_LOUT_L JP51 1 2 3 4 MIC_IN_L MIC_IN_R 1 3 Q48 2N7002_SOT23-3 C785 2 1 DOCK_LOUT_R 33 33 HP OUT For Docking 1 R951 10K_0402_5% R1079 4.7K_0402_5% 2 DOCK_LOUT_R INTMIC IN 3 HP_OUTL S 33 3 D HP_OUTR 2 G 33 1 R1078 4.7K_0402_5% HP OUT Q47 2N7002_SOT23-3 1 1 S 2 G Q114 Q50 D 2N7002_SOT23-3 2 G 1 2N7002_SOT23-3 1 S 2 G 3 1 D 3 HP_DET# +VDDA_CODEC C1379 1U_0603_10V4Z 1 2 R1077 0_0402_5% 2 1 +VDDA_CODEC 3 3 35 of 51 Rev 0.1 5 4 3 2 1 Left side ESATA/USB combination Connector +5VALW USB_VCCC U41 USB_VCCC W=60mils 8 7 6 5 TPS2061IDGNR_MSOP8 2 USB_EN# 1 + 2 4.7U_0805_10V4Z R1083 JP53 1 2 C1383 1000P_0402_50V7K 1 C1381 OUT OUT OUT OC# C1382 0.1U_0402_16V4Z D GND IN IN EN# C1380 150U_D_6.3VM 1 2 3 4 1 1 2 3 4 USB20_N2 USB20_P2 2 2 10K_0402_5% 1 27 27 26 26 26 26 SATA_RXN5_C SATA_RXP5_C 5 6 7 8 9 10 11 SATA_TXP5 SATA_TXN5 SATA_TXP5 SATA_TXN5 C1385 2 C1384 2 1 0.01U_0402_16V7K SATA_RXN5 1 0.01U_0402_16V7K SATA_RXP5 +5VALW B_VCC B_DB_D+ B_GND D USB GND A+ ESATA AGND BB+ GND TYCO_1759576-1 CONN@ D46 20070921 remove invter 4 +5VALW SATA_TXN5 3 VIN IO1 IO2 GND SATA_TXP5 2 1 @ PRTR5V0U2X_SOT143-4 USB cable connector for Right side C C JP55 1 2 3 4 5 6 7 8 9 10 +5VALW USB_EN# 27 27 USB20_N0 USB20_P0 27 27 USB20_N1 USB20_P1 11 12 1 2 3 4 5 6 7 8 9 10 GND1 GND2 ACES_87213-1000G BT Connector Need change to New version JP57 1 2 3 4 5 6 7 8 GND1 GND2 B Finger printer 1 2 3 4 5 6 7 8 9 10 +3VAUX_BT USB20_P6_R USB20_N6_R R1084 R1085 @ R1086 1 @ R1087 1 1 0_0402_5% 1 0_0402_5% 2 2 USB20_P6 USB20_N6 BT_LED CH_DATA CH_CLK 1K_0402_5% 1K_0402_5% 2 2 B 27 27 39 31 31 0612 no install D47 ACES_88231-08001 4 +5VALW USB20_N6_R 3 VIN IO1 IO2 GND 2 USB20_P6_R 1 @ PRTR5V0U2X_SOT143-4 3 R634 1 R635 1 2 0_0402_5% 2 0_0402_5% 3 2 USB20_N7 USB20_P7 JP24 USB20_N7_R USB20_P7_R 1 2 3 4 5 6 D30 @ PACDN042_SOT23-3~D 2 C1386 R1090 1U_0603_10V4Z 100K_0402_5% ACES_88231-04001 27 2007/09/26 Issued Date BT_OFF R1092 1 2 47K_0402_5% 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 1 C1387 2 1 C1388 2 1 C1389 2 3 2 4.7U_0805_10V4Z C1390 1 2 0.1U_0402_16V4Z Compal Secret Data Security Classification 5 0.1U_0402_16V4Z 0.01U_0402_16V7K GND1 GND2 1 A 1 1 2 3 4 SI2301BDS_SOT23 1 2 2 C756 0.1U_0402_16V4Z 2 G USB_EN# +3VAUX_BT Q105 D G 27 27 +3VALW 2 0_0603_5% S 1 38 +3VS @ R628 1 1 D 3 20070209 Add for FPR 1 2 0_0603_5% SI2301BDS_SOT23 S +3VALW 1 @ Q31 2 R627 Title A Compal Electronics, Inc. USB, BT, eSATA Size Document Number Rev 0.1 Montevina Consumer Discrete Date: Friday, October 05, 2007 Sheet 1 36 of 51 5 4 +3VL 0.1U_0402_16V4Z 38,43 D 38,43 1 R552 100K_0402_5% 2 U28 8 7 6 5 SMB_EC_CK1 SMB_EC_DA1 VCC WP SCL SDA C712 0.1U_0402_16V4Z A0 A1 A2 GND 1 2 3 4 8 3 AT24C16AN-10SI-2.7_SO8 FSEL# 38 SPI_CLK 38 FWR# 1 R553 1 R554 1 R556 SPI_FSEL# 2 0_0402_5% SPI_CLK_R 2 0_0402_5% SPI_FWR# 2 0_0402_5% VSS Removed +3VS. 6/13 B+ HOLD 1 CONN@ JP18 S 6 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 C 5 D Q 2 SPI_SO 1 R555 17 FRD# 2 0_0402_5% FRD# 26,31,38 SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH WIESO_G6179-100000_8P 2 CLK_DEBUG_PORT_0 38 WIESON G6179 8P SPI R557 100K_0402_5% Change from +3VL to +3VS. 6/9 4 W 7 2 38 VCC 1 1 LPC Debug Port CONN@ U27 20mils 2 C711 2 SPI ROM +3VL 1 +3VL 3 &U1 LPC_FRAME# 25,38 PCI_RST# 26,31,38 26,31,38 26,31,38 26,31,38 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 ON/OFFBTNLED# 45level 45@ SST25LF080B_SO8-200mil Connect pin3 & 23 together and pin 24 to GND in 6/29. VCC1PWRGD SPI_CLK_JP52 SPI_CS#_JP52 SPI_SI_JP52 SPI_SO_JP52 SPI_HOLD#_0 D Ground LPC_PCI_CLK Ground LPC_FRAME# +V3S LPC_RESET# +V3S LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 VCC_3VA PWR_LED# CAPS_LED# NUM_LED# VCC1_PWRGD SPI_CLK SPI_CS# SPI_SI SPI_SO SPI_HOLD# Reserved Reserved Reserved ACES_87216-2404_24P C C SPI_CLK 1 R558 2 0_0402_5% SPI_CLK_JP52 DEBUG@ 1 R559 2 0_0402_5% SPI_CS#_JP52 DEBUG@ 2 0_0402_5% SPI_SI_JP52 DEBUG@ 1 R560 HOLD# 2 3.3K_0402_5% DEBUG@ 1 R562 2 0_0402_5% SPI_HOLD#_0 FSEL# +3VALW Acceleromter R561 1 +3VS +3VS_ACL D23 2 1 +3VS_ACL_IO FRD# R564 0_0603_5% 1 2 38,39 CH751H-40PT_SOD323-2 38 1 ACCEL_INT 2 1 R563 2 0_0402_5% SPI_SO_JP52 DEBUG@ ON/OFFBTN_LED# ON/OFFBTN_LED# DEBUG@ 1 R565 2 0_0402_5% ON/OFFBTNLED# VCC1_PWRGD VCC1_PWRGD DEBUG@ 1 R566 2 0_0402_5% VCC1PWRGD +3VS_ACL U29 25 FWR# INT/RDY GND SDD RES SDA/SDI/SPC GND VDD_IO VDD 16 15 R567 0_0402_5% 1 2 B B ICH_SMBCLK +3VS_ACL 6 1 10K_0402_5% 2 R569 7 RES CS VDD NC RES CK GND R568 0_0402_5% 1 2 11 10 R570 0_0402_5% 1 2 9 1 +3VS_ACL_IO 2 1 2 1 8 SCL/SPC +3VS_ACL 13 12 C714 17,21,27,31 5 2 R571 0_0402_5% 10U_0805_6.3V6M 4 +3VS_ACL_IO 14 C713 3 ICH_SMBDATA 0.1U_0402_16V4Z 17,21,27,31 LIS3LV02DL-TR _LGA16 L Must be placed in the center of the system. A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. BIOS ROM Size Document Number Rev 0.1 Montevina Consumer Discrete Date: ai 2007/09/26 Deciphered Date Friday, October 05, 2007 Sheet 1 he x 2007/09/26 nf @ ho tm Compal Secret Data Security Classification Issued Date ai l.c om A 37 of 51 +3VL_EC 1000P_0402_50V7K 1 +3VL +3VL_EC R572 1 +5VL 2 0_0805_5% +3VS U30 1 1 1 1 1 2 2 2 2 2 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 8.2K_0402_5% @ C722 1 26 26 27 @ R576 1 2 26,31,37 26,31,37 2 26,31,37 33_0402_5%26,31,37 26,31,37 15P_0402_50V8J 17 R578 1 C721 1 2 3 4 5 7 8 10 PCI_RST# CLK_PCI_EC PCI_RST# ECRST# EC_SCI# CLKRUN# 12 13 37 20 38 GATEA20 KB_RST# SIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 1 0.1U_0402_16V4Z 27 2 2 2 47K_0402_5% 25,37 +3VL PCI_RST# JOPEN +3VL 2 1 R713 100K_0402_5% R721 4.7K_0402_5% R583 @ 10K_0402_5% 2 1 2 2 R581 100K_0402_5% LID_SW# TP_BTN# +3VL 37,43 37,43 6,21 6,21 2 GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 77 78 79 80 AD PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 PS2 Interface 9 TSATN# 40 31 R592 1 DOCK_SLP_BTN# WWAN_POWER_OFF 39 R593 1 +3VL ON/OFFBTN 41 39 PWRBTN_OUT# 2 0_0402_5% 4.7K_0402_5% 2 DIM_LED NUM_LED# C723 15P_0402_50V8J 1 2 SM Bus 2 EC DEBUG port CRY2 122 123 PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A NC OUT NC IN 1 32.768KHZ_12.5P_1TJS125DJ2A073 EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 GPI XCLK1 XCLK0 V18R @ R595 20M_0402_5% 4 SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS# CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 GPO 1 Y5 3 UTX URX ON/OFFBTN DIM_LED NUM_LED# PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F SPI Flash ROM GND GND GND GND GND 1 EC_PME# 2 0_0402_5% CRY1 +3VL_EC C725 15P_0402_50V8J L30 0_0603_5% 2 +EC_AVCC DAC_BRIG VCTRL IREF AC_SET 83 84 85 86 87 88 EC_MUTE# USB_EN# I2C_INT MUTE_LED TP_CLK TP_DATA 1 C726 19 R582 1 DOCK_VOL_UP# DOCK_VOL_DWN# 35 36 39 40 R579 1 R580 1 119 120 126 128 FRD# FWR# SPI_CLK FSEL# 2 4.7K_0402_5% DOCK_VOL_UP# DOCK_VOL_DWN# 73 74 89 90 91 92 93 95 121 127 FRD# FWR# SPI_CLK FSEL# R720 CIR_IN VCC1_PWRGD FSTCHG STD_ADP CAPS_LED# BAT_LED# ON/OFFBTN_LED# SYSON VR_ON AC_IN 2 0.1U_0402_16V4Z 1 2 10K_0402_5% 2 10K_0402_5% 39 39 R586 EC_RSMRST# 100 101 R588 1 2 EC_ON 0_0402_5% 102 WL_BLUE_LED# 103 PM_PWROK 104 BKOFF# 105 M_PWROK 106 TP_LED# 107 HDDHALT_LED# 108 110 112 114 115 116 117 118 DOCK_PWRON ENBKL EAPD_CODEC THERM_SCI# SUSP# PWRBTN_OUT# NMI_DBG# L31 1 100P_0402_50V8J 1 100P_0402_50V8J KSO3 1 100P_0402_50V8J KSO7 1 100P_0402_50V8J KSO8 1 @ 40 100P_0402_50V8J @ C1456 1 2 100P_0402_50V8J @ C1459 1 2 37 37 KSO5 100P_0402_50V8J @ C1458 1 2 100P_0402_50V8J 1 100P_0402_50V8J 1 100P_0402_50V8J KSO1 1 100P_0402_50V8J KSO2 1 @ 100P_0402_50V8J 1 100P_0402_50V8J 1 100P_0402_50V8J 1 100P_0402_50V8J 1 @ KSI3 KSI2 KSI5 KSI1 9/21 add R for nvidia KSI4 ENBKL 1 10K_0402_5% 2 1 10K_0402_5% R1132 KSI6 EC_RSMRST# 27 EC_LID_OUT# 27 EC_ON 45 WL_BLUE_LED# 39 PM_PWROK 9,27 BKOFF# 19 M_PWROK 9,27 TP_LED# 39 HDDHALT_LED# 39 DOCK_PWRON 40 ENBKL 21 EAPD_CODEC 33 THERM_SCI# 21,27 SUSP# 31,33,41,44,46,47,48 PWRBTN_OUT# 27 C724 4.7U_0603_6.3V6K JP19 D16 1 2 ADP_ID CH751H-40PT_SOD323-2 R714 10K_0402_5% NMI_DBG# AC_IN 2 D14 1 PCI_SERR# PCI_SERR# CH751H-40PT_SOD323-2 R715 10K_0402_5% 2 D13 1 ACIN ACIN 44,45 25 KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1 CH751H-40PT_SOD323-2 1 C791 39 39 ESB_CLK ESB_DAT @ R729 @ R730 1 1 2 0_0402_5% 2 0_0402_5% SMB_EC_CK2 SMB_EC_DA2 Cypress R731 R732 1 1 2 0_0402_5% 2 0_0402_5% ESB_CLK_R ESB_DAT_R ENE C1464 2 C1465 2 @ C1466 2 @ C1467 2 @ +3VL +3VL +3VL C1460 2 C1461 2 @ C1462 2 @ C1463 2 @ 14" INT_KBD CONN.( TYPE "D" KB) 1 2 0_0603_5% C1452 2 C1453 2 @ C1454 2 @ C1455 2 @ 40 124 2 C1448 2 C1449 2 @ C1450 2 @ C1451 2 @ KSO0 KSO4 Select SPI ROM or LPC ROM 37 37 +3VL @ 2 10K_0402_5% CIR_IN 35,40 VCC1_PWRGD 37 FSTCHG 44 STD_ADP 44 CAPS_LED# 39 BAT_LED# 39 ON/OFFBTN_LED# 37,39 SYSON 31,39,41,47,50 VR_ON 49 2 @ KSO6 TP_CLK TP_DATA 97 98 99 109 100P_0402_50V8J 1 100P_0402_50V8J KSO10 1 100P_0402_50V8J KSO11 1 100P_0402_50V8J KSO12 1 KSO9 44 44 44 EC_MUTE# USB_EN# I2C_INT MUTE_LED 1 2 DAC_BRIG VCTRL IREF AC_SET ECAGND 1 +5VL 68 70 71 72 100P_0402_50V8J @ C1444 1 2 100P_0402_50V8J @ C1445 1 2 100P_0402_50V8J @ C1446 KSO15 1 2 KSO14 BATT_TEMP 43 BATT_OVP 43 ADP_I 44 ADP_ID 43 TP_BTN# 39 ANA_MIC_DET 35 For C Revision 1 URX UTX BATT_TEMP BATT_OVP ADP_I ADP_ID TP_BTN# ANA_MIC_DET KB926QFB0_LQFP128_14X14 JP20 1 1 2 2 3 3 4 4 ACES_85205-0400 CONN@ 63 64 65 66 75 76 100P_0402_50V8J @ C1442 1 2 100P_0402_50V8J @ C1443 1 2 KSO13 INV_PWM 19 FAN_PWM 6 LAN_POWER_OFF 30 ACOFF 44 0.01U_0402_16V7K C720 ECAGND 1 2 SPI Device Interface 11 24 35 94 113 PCI_PME# 27 27 27 39 DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0 GPIO SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 2 25 R589 1 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 INV_PWM FAN_PWM LAN_POWER_OFF ACOFF +5V R585 10K_0402_5% SLP_S3# SLP_S3# SLP_S5# SLP_S5# EC_SMI# EC_SMI# LID_SW# LID_SW# ESB_CLK_R ESB_DAT_R EC_PME# 1 @ R591 2 0_0603_5% CONA# CONA# KSI0 21 23 26 27 PWM Output MISC DA Output KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSI7 INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 J1 1 SUSP# 1 GATEA20 KB_RST# SIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 CLK_PCI_EC +3VL For EMI VCC VCC VCC VCC VCC VCC R573 R577 R574 R575 R724 1 SMB_EC_DA1 SMB_EC_CK1 SMB_EC_DA2 SMB_EC_CK2 CLKRUN# +EC_AVCC 1 2 2 C719 2 2 1000P_0402_50V7K 2 C718 67 C717 AVCC 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 AGND C716 69 C715 9 22 33 96 111 125 0.1U_0402_16V4Z 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ACES_85201-2405 CONN@ 2 100P_0402_50V8J Vendor Recommend Compal Secret Data Security Classification Issued Date 2007/09/26 Deciphered Date 2007/09/26 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Compal Electronics, Inc. EC KB926/KB Conn. Size Document Number Rev 0.1 Montevina Consumer Discrete Date: Monday, October 08, 2007 Sheet 38 of 51 A B System LED C D Keyboard backlight Conn White E Mini card LED S1-023459_AQUA-WHITE_0603 R1095 1 2 +5VALW_LED 470_0402_5% Cap lock +3VS WL_BLUE_LED# White JP9 1 2 Battery Charge LED +5VALW 470_0402_5% S1-023462_AQUA-WHITE/AMBER White 26 38 1 SATA_LED# 2 3 HDDHALT_LED# R1098 470_0402_5% 1 2 4 1 2 R728 470_0402_5% AMBER 5 6 G1 G2 1 2 3 4 1 2 3 4 +5VALW_LED 36 31 2 WL_LED# BT_LED 10K R1126 100K_0402_5% +5VALW_LED 1 ACES_85201-04051 Q111 DTA114YKAT146_SOT23-3 +5VALW_LED WL_LED D S Q113 2N7002_SOT23-3 2 G HDD LED +5VALW_LED S 1 2 38 2 1 D 1 D52 BAT_LED# 47K 1 R1097 38 1 Q112 2N7002_SOT23-3 2 G 3 S1-023459_AQUA-WHITE_0603 1 2 3 1 1 D50 CAPS_LED# 3 38 R1127 100K_0402_5% D53 2 White S1-023459_AQUA-WHITE_0603 D17 1 2 1 2 System Power LED +5VALW_LED 470_0402_5% TouchPAD ON/OFF LED +5VALW_LED R1100 1 10K_0402_5% R1101 1 2 4 3 1 1 R611 10K_0402_5% @ On (TP_LED#=L)-> White Off (TP_LED#=H)-> Amber 2 1 2 3 4 5 6 7 8 9 10 GND GND 3 SW1 SMT1-05-A_4P 1 4 2 TP_BTN# TP_BTN# 38 Q25 2 G 2N7002_SOT23-3 1 5 6 TP_LED#_LIGHT 1 NUM_LED# ESB_CLK ESB_DAT I2C_INT ON/OFFBTN_LED# ON/OFFBTN 38 2 D54 S1-023462_AQUA-WHITE/AMBER D D S S Q26 TP_LED# 2 G 2N7002_SOT23-3 3 37,38 2 2 38 38 38 1 2 3 4 5 6 7 8 9 10 11 12 +5V AMBER R613 10K_0402_5% JP59 38 White 1 R1099 4.7K_0402_5% +5VS 1 1 4.7K_0402_5% TP ON/OFF R610 820_0402_5% 2 R609 200_0402_5% 3 2 +3VL 2 +5VALW_LED 1 Capacitor Sensor Conn 2 R980 ON/OFFBTN_LED# TP_LED# 38 2 ACES_85201-1005N CONN@ T/P Board T/P Power +5VALW +5V +5V Q23 SI2301BDS-T1-E3_SOT23-3 S 3 ON/OFFBTN ON/OFFBTN_LED# 1 2 3 4 1 2 5 3 G1 6 4 G2 ACES_85201-04051 CONN@ G1 G2 2 1 2 3 4 TP_CLK TP_DATA ACES_85201-04051 CONN@ @ C730 100P_0402_50V8J 1 2 1 2 31,38,41,47,50 @ C731 100P_0402_50V8J 38 38 SYSON SYSON 1 5 6 JP10 D 3 +3VALW R612 10K_0402_5% 0.1U_0402_16V4Z 1 2 3 4 3 1 G 2 JP23 1 1 @ C729 2 ON/OFF Button Connector D 3 S Q24 2N7002_SOT23-3 2 G 2 3 TP_DATA TP_CLK D28 PSOT24C_SOT23-3 @ 1 Reed Switch Connector +3VALW 4 4 JP11 1 2 3 1 2 3 G1 G2 4 5 om LID_SW# l.c 38 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. LED, TP,KBL,Cab sensor boar Size Document Number Rev 0.1 Montevina Consumer Discrete Date: ai 2007/09/26 Deciphered Date Monday, October 08, 2007 Sheet E he x 2007/09/26 nf @ ho tm Compal Secret Data Security Classification Issued Date ai ACES_85204-03001 CONN@ 39 of 51 Atlas/ Saturn Dock +DOCKVIN 43 44 18 18 18 18 18 18 18 27 27 RED GREEN BLUE D_DDCDATA D_DDCCLK D_HSYNC D_VSYNC USB20_N3 USB20_P3 30 30 30 30 30 30 30 30 RJ45_MIDI3RJ45_MIDI3+ RJ45_MIDI2RJ45_MIDI2+ RJ45_MIDI1RJ45_MIDI1+ RJ45_MIDI0RJ45_MIDI0+ R1069 2 1 0_0402_5% JDOCK1 RED GREEN BLUE D_DDCDATA D_DDCCLK D_HSYNC D_VSYNC USB20_N3 USB20_P3 NB_GND RJ45_MIDI3RJ45_MIDI3+ RJ45_MIDI2RJ45_MIDI2+ RJ45_MIDI1RJ45_MIDI1+ RJ45_MIDI0RJ45_MIDI0+ 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 +V_BATTERY R1068 2 1 0_0402_5% 43 44 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 NB_GND TV_LUMA TV_CRMA TV_COMPS VGA_GND CIR_IN DOCK_PWRON MUTE_LED DOCK_SLP_BTN# JACK_DET# R_VOL_UP# R_VOL_DWN# SPDIFO_L AUDIO_OGND DOCK_LOUT_R DOCK_LOUT_L DOCK_MIC_R_C DOCK_MIC_L_C AUDIO_IGND DOCK_PRESENT B+ +3VALW 1 CIR_IN 35,38 DOCK_PWRON MUTE_LED 38 DOCK_SLP_BTN# R617 1 R618 1 38 38 JACK_DET# 33,35 DOCK_VOL_UP# 38 DOCK_VOL_DWN# 38 2 200_0402_5% 2 200_0402_5% DOC_GNDA DOCK_LOUT_R DOCK_LOUT_L 35 35 DOC_GNDA 1 PJP3 DOC_GNDA DOC_GNDA 2 41 42 R620 2K_0402_5% 41 42 2 2 PAD-OPEN 2x2m +3VS_HDA FOX_QL1122L-H212AR-7F R621 10K_0402_5% 2 need change to reverse type connector 1 R1140 33_0402_5% 1 1 CONA# 1 C DOCK_PRESENT 3 1 C741 C740 2 2 SPDIFO_L R_VOL_UP# 220P_0402_25V8J R1143 110_0402_5% 2 C744 1000P_0402_50V7K 2 C745 1000P_0402_50V7K Need 600 Ohm 500 mA R631 33 DOCK_MIC_R 33 DOCK_MIC_L +DOCKVIN L36 FBM-11-160808-601-T_0603 DOCK_MIC_R_C 1 2 C746 1U_0603_10V6K 1 2 1 C753 2 DOCK_MIC_L_C 1 2 L37 FBM-11-160808-601-T_0603 1U_0603_10V6K 1 1 C755 C754 220P_0402_50V7K 2 2 220P_0402_50V7K +3VS 1 C734 1000P_0402_50V7K DOC_GNDA DOC_GNDA 10K_0402_5% SENSE_B# 2 2 1 1 S 1 2 B C 3 E Q32 2 B Q29 2N7002_SOT23-3 2 G C 1 MMBT3904_NL_SOT23-3 R632 1 2 10K_0402_5% D 3 2 R626 10K_0402_5% DOCK_MIC_L_C 33 R625 1 R630 2 1 Q30 MMBT3904_NL_SOT23-3 E 2 3 R629 150_0402_1% 2 1 TV_COMPS 1 2 TV_CRMA 150_0402_1% 2 1 TV_COMPS 1 C1489 2 R1142 0_0603_5% MIC_Dock R_VOL_DWN# TV_LUMA 150_0402_1% 2 1 20 1 2 220P_0402_50V7K 1 DOC_GNDA DOC_GNDA TV_LUMA TV_CRMA 21,33 1 DOCK_LOUT_R DOCK_LOUT_L 1 0720 Add dock_present_gnd TV-out 20 SPDIF_OUT 3 NB_GND 220P_0402_50V7K R623 2K_0402_5% 0815 change dock_present_gnd to NB_GND 20 R1141 1 2 220_0402_5% 2 G S 1 2 Q116 2N7002_SOT23-3 E 2 C739 100N_0402_50V7M D Q27 MMBT3904_NL_SOT23-3 2 B C757 R633 47K_0402_5% 1 1 38 1U_0603_10V6K Compal Secret Data Security Classification Issued Date 2007/09/26 Deciphered Date 2007/09/26 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Compal Electronics, Inc. DOCK CONN. Size Document Number Custom Montevina Consumer Date: Friday, October 05, 2007 Rev 0.1 Discrete Sheet 40 of 51 5 4 3 +5VALW to +5VS Transfer 2 +3VALW to +3VS Transfer 1 DIM LED +5VALW +5VALW +5VS +3VALW +5VALW_LED Q33 +3VS SI2301BDS-T1-E3_SOT23-3 1 C761 C762 330K_0402_5% 2 D D D D 1 1 C763 C764 2 3 1 1 Q45 2N7002_SOT23-3 2 Q34 2N7002_SOT23-3 S 1 @ 2 R648 470_0402_5% D 2 G 3 D 2 G SUSP D 0.1U_0402_16V4Z 2 1 1 SUSP 0.1U_0402_16V4Z R638 470_0402_5% C758 0.1U_0402_16V4Z 2 2 RUNON_3VS RUNON @ 1 1 R637 10K_0402_5% AO4466_SO8 2 2 2 3 2 330K_0402_5% 10U_0805_10V4Z 1 2 3 4 S S S G S 1 C765 2 0.01U_0402_16V7K 38 DIM_LED DIM_LED 1 1 AO4466_SO8 8 7 6 5 10U_0805_10V4Z C759 2 1 1 R649 2 1 10U_0805_10V4Z 1 2 3 4 D S S S G G 2 U33 D D D D S R636 8 7 6 5 10U_0805_10V4Z C760 1 U32 1 D 3 B+ D B+ S Q35 2N7002_SOT23-3 2 G C769 0.01U_0402_16V7K +1.8V to +1.8VS Transfer +1.8V +1.8VS +3VL U34 1 C767 SYSON# 48 SYSON# 1 31,38,39,47,50 SYSON D D S S 2 G SUSP# 2 G Q36 2N7002_SOT23-3 SUSP 48 SUSP# 31,33,38,44,46,47,48 Q37 2N7002_SOT23-3 2 Q46 2N7002_SOT23-3 SYSON SUSP C770 1U_0402_6.3V6K R646 R647 470_0402_5% 470_0402_5% H11 HOLEA SUSP S 2N7002_SOT23-3 D 1 Q42 SUSP 2 G S 2N7002_SOT23-3 H12 HOLEA H13 HOLEA H14 HOLEA H15 HOLEA H16 HOLEA H10 HOLEA 1 H9 HOLEA 1 1 1 H17 HOLEA D Q43 SUSP 2 G S 2N7002_SOT23-3 D S H18 HOLEA H19 HOLEC B H20 HOLEC 1 1 1 1 1 1 2N7002_SOT23-3 Q41 1 2N7002_SOT23-3 S D 2 G 3 S Q40 SUSP 2 G 1 D 1 1 SYSON# 3 2N7002_SOT23-3 Q39 H8 HOLEA 2 2 470_0402_5% 3 S D 2 G 3 SUSP 3 1 Q38 3 1 D 2 G 3 SUSP H7 HOLEA 1 1 1 R645 470_0402_5% 2 2 2 R644 470_0402_5% 2 R643 470_0402_5% 2 R642 1 1 1 1 R641 470_0402_5% H6 HOLEA 1 +1.8VS H5 HOLEA 1 +0.9V H4 HOLEA 1 +VCCP +1.5VS H3 HOLEA 1 +1.8V +3VS 1 +5VS B H2 HOLEA 1 H1 HOLEA 1 Discharge circuit 1 2 1 1 1 1 3 0.1U_0402_16V4Z R650 10K_0402_5% 100K_0402_5% 2 2 2 S R640 100K_0402_5% 2 2 G C R639 C768 RUNON_1.8VS SUSP 1 1 1 AO4466_SO8 330K_0402_5% D +3VL 10U_0805_10V4Z 1 2 3 4 1 2 S S S G 3 R651 D D D D 2 1 C 8 7 C766 6 5 10U_0805_10V4Z 1 1 3 B+ Q44 2 G 2N7002_SOT23-3 FM1 1 FM2 1 FM3 1 FM4 1 A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. DC/DC Interface Size Document Number Rev 0.1 Montevina Consumer Discrete Date: ai 2007/09/26 Deciphered Date Friday, October 05, 2007 Sheet 1 he x 2007/09/26 nf @ ho tm Compal Secret Data Security Classification Issued Date ai l.c om A 41 of 51 5 4 3 +3VS 2 1 +5VS_HDMI R1039 2.2K_0402_5% D @ @ +3VS R1033 2.2K_0402_5% Q101 @ R1034 6.8K_0402_5% D R1040 6.8K_0402_5% 2N7002_SOT23-3 3 HDMIDAT 1 D HDMIDAT_VGA S 21 1 2 G 2 2 1 @ 1 0_0402_5% 2 R1023 @ G 2 +3VS 3 2N7002_SOT23-3 Q102 1 HDMICLK D HDMICLK_VGA S 21 1 0_0402_5% 2 R1024 @ C C L70 HDMI_CLK- 21 HDMI_CLK+ HDMI_CLK- 1 HDMI_CLK+ 4 1 2 4 3 2 HDMI_R_CLK- 3 HDMI_R_CLK+ WCM-2012-900T_0805 D41 +5VS RB411D T146 _SOT23-3 HDMI Connector 2 21 1 9/21 change R1036 and R1035 from 10K to 2.2K for nvidia L71 HDMI_TX0- HDMI_TX0- 1 1 2 2 3 3 HDMI_R_TX0+ Need to check A51 team circuit WCM-2012-900T_0805 HDMI_DETECT HDMI_DETECT 1 21 D40 SKS10-04AT_TSMA HDMI_TX1- 21 HDMI_TX1+ HDMI_TX1- 1 HDMI_TX1+ 4 1 2 4 3 2 HDMI_R_TX1- 3 HDMI_R_TX1+ L74 1 2 FBML10160808121LMT_0603 R1038 10K_0402_1% 2 L72 21 R1037 1 2 1K_0402_1% 2 4 1 HDMIDAT HDMICLK C1248 2 330P_0402_50V7K HDMI_R_CLKHDMI_R_CLK+ HDMI_R_TX0- WCM-2012-900T_0805 HDMI_R_TX0+ HDMI_R_TX1HDMI_R_TX1+ HDMI_R_TX2- 9/21 remove ESD Cap. HDMI_R_TX2+ L73 A 21 HDMI_TX2- 21 HDMI_TX2+ HDMI_TX2- 1 HDMI_TX2+ 4 1 R1035 1 4 1 HDMI_TX0+ 2 HDMI_TX0+ 2.2K_0402_5% 1 2 R1036 21 +5VS_HDMI HDMI_R_TX0- B 2.2K_0402_5% 21 +5VS_HDMI 2 B 0.1U_0402_16V4Z C1247 @ JP48 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ 20 21 22 23 CONN@SUYIN_100042MR019SX53ZL 1 2 4 3 2 HDMI_R_TX2- 3 HDMI_R_TX2+ HDMI ESD A WCM-2012-900T_0805 Compal Secret Data Security Classification 2007/09/26 Issued Date 2007/09/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. HDMI LS & Conn. Size Document Number Custom Montevina Consumer Date: Rev 0.1 Discrete Sheet Friday, October 05, 2007 1 42 of 51 A B C D +3VALW 3 PQ3 TP0610K-T1-E3_SOT23-3 BATT AC_LED 47 1 340K_0402_1% PR1 1 2 PR3 @10K_0402_5% 2 2 2 1 1 2 PC5 1000P_0402_50V7K 1 2 PC4 100P_0402_50V8J 1 PC3 1000P_0402_50V7K 2 1 2 1 PJSOT24C_SOT23-3 PC2 100P_0402_50V8J 3 2 PJP1 2 105K_0402_1% PR6 1 2 1 PL2 SMB3025500YA_2P 1 ADPIN PD1 1 3 PL1 SMB3025500YA_2P 2 5 4 3 2 1 8 +DOCKVIN + PR5 10K_0402_5% P VIN 2 0.01U_0402_25V7K PC6 5 4 3 2 1 1 0 - 2 1 1 BATT_OVP <40> G ADP_SIGNAL 4 ACES_88334-057N 2 1 PR2 10K_0402_5% 2 PR8 100_0402_5% 499K_0402_1% PR4 1 2 1 2 1 ADP_ID 41 +5VALW 0.01U_0402_25V7K PC1 2 1 PU1A LM358ADT_SO8 2 VMB 1 EC_SMD EC_SMC 2 PL4 HCB2012KF-121T50_0805 PD2 @SM05_SOT23 1 PH1 under CPU botten side : CPU thermal protection at 90 +-3 degree C Recovery at 47 +-3 degree C 2 1 3 1 1 2 3 4 5 6 7 8 9 10 1 2 PC8 1000P_0402_50V7K PC9 0.01U_0402_50V4Z PR7 47K_0402_1% +5VS 2 2 2 3 1 2 3 4 5 6 7 8 GND GND 1 CPU SUYIN_200275MR008GXOLZR 2 3 1 1 1 1 3 BATT PL3 HCB2012KF-121T50_0805 PJP2 PR14 100_0402_5% PR13 1 S D S P 0 - 1 PR15 150K_0402_1% 2 2 2 + 3 2 0.22U_0603_10V7K 6 PR11 150K_0402_1% 1 1 1 +3VL 5 2 PR12 2.55K_0402_1% PC10 PR16 6.49K_0402_1% 2 1 3 <46> 1 G +5VALW PQ1 SSM3K7002FU_SC70-3 2 7 G PU1B 4 <39,40> LM358ADT_SO8 1 SMB_EC_CK1 D PC11 1000P_0402_50V7K 2 SMB_EC_CK1 8 PR10 15K_0402_1% <39,40> 1 SMB_EC_DA1 2 PR9 10K_0402_5% BAT_ID ENTRIP1 <47> 2 SMB_EC_DA1 1 1 2 +3VL PH1 10K_TH11-3H103FT_0603_1% 2 100_0402_5% PD3 @SM24.TC_SOT23-3 ENTRIP2 <47> PR17 1K_0402_5% PQ2 SSM3K7002FU_SC70-3 2 2 G BATT_TEMP 4 Deciphered Date 2008/05/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title Compal Electronics, Inc. nf @ ho tm Compal Secret Data 2007/05/29 DC Connector/CPU_OTP Size Document Number Rev 0.1 Montevina Consumer Discrete ai Issued Date Date: Friday, October 05, 2007 he x Security Classification ai l.c om 4 Sheet D 43 of 51 A B C P4 D B+ BATT VIN P2 PQ102 AM4835EP-T1-PF_SO8 2 24 REGN 23 DL_CHG LODRV 1 2 1 2 2 20 19 18 1 2 1 3 2 1 BQ24740VREF 1 @47K_0402_5% PR119 2 BAT_ID <45> G IREF <40> 2 PR121 200K_0402_1% PC122 @0.1U_0603_25V7K 1 1 1 PR120 133K_0402_1% PR122 681K_0402_1% 1 2 2 1 3 S 2 17 21 2 D PQ111 SSM3K7002FU_SC70-3 BATT 2 PC118 0.1U_0402_10V7K PR117 100K_0402_5% 2 PR123 1M_0402_5% 3 5 6 7 8 3 2 1 1U_0603_10V6K 1 2 3 P2 BQ24740VREF PR124 1K_0402_5% VIN 1 VIN 2 PACIN LM393DG_SO8 1 7 O 4 PR133 10K_0603_0.1% PU102B 1 8 P - 1 1 + G PR134 10K_0402_5% PD103 RLZ4.3B_LL34 2 2 1 6 <40,47> S FSTCHG# 1 <40> 1.24VREF 5 2 PQ112 SSM3K7002FU_SC70-3 G 2 2 D 2 ACIN PR127 10K_0402_1% 2 1 2 PR132 100K_0402_5% 1 G O PU102A LM393DG_SO8 3 P - PC126 0.047U_0402_16V7K 2 1 1 1 CHGEN# 2 PR135 10K_0603_0.1% + 4 1 2 PR130 2.15K_0402_1% 1 2 PR128 10K_0402_5% 1 +3VL 2 1 2 PR126 100K_0402_1% 8 2 PC125 0.1U_0603_25V7K PR129 10K_0402_1% 2 1 PR131 133K_0402_1% 3 1 +3VL PR125 47_1206_5% VIN PQ106 DTC115EUA_SC70-3 5 6 7 8 1 DPMDET CELLS SRP SRN BAT PC119 BATT 1 2 PC120 0.22U_0603_10V7K 2 PC121 100P_0402_50V8J 1 ADP_I SRSET IADAPT 15 PR118 10K_0402_5% PC123 0.1U_0402_10V7K 1 PQ110 AO4466_SO8 22 IADAPT 2 2 PR116 39K_0402_5% <40> PGND 1 ISYNSET 1 2 1 1 14 PR115 100K_0402_1% 2 EXTPWR 4 Charge Detector 3 1 RLS4148_LL34-2 13 2 PC117 1U_0603_10V6K 2 PR112 0.015_1206_1% 1 2 1 REGN PL102 10U_LF919AS-100M-P3_4.5A_20% 1 2 VADJ 16 1 VCTRL 12 1 PD101 RLS4148_LL34-2 VADJ 2 3 PR114 @0_0402_5% <40> PC116 4.7U_0805_25V6-K LX_CHG PC115 4.7U_0805_25V6-K PH 1 VDAC 2 DH_CHG 25 4 1 26 2 3 2 1 HIDRV 1 2 PU101 BQ24740RHDR_QFN28_5X5 VREF 27 ACOFF PQ108 AO4466_SO8 PD102 PR113 143K_0402_1% S 1 PC111 0.1U_0402_10V7K 2 2 10 S PQ114 SSM3K7002FU_SC70-3 2 1 1 BTST 2 D 2 G +3VL 11 SSM3K7002FU_SC70-3 AGND 1 BST_CHG G 2 2 PC110 1U_0805_25V6K 28 2 PACIN PC114 4.7U_0805_25V6-K PVCC VIN PR139 100K_0402_5% +3VLP 1 29 1 ACOFF# 2 1U_0603_6.3V6M PQ109 2 PC105 4.7U_0805_25V6-K 4 1 ACN CHGEN 2 3 ACP 5 4 LPMD 6 IADSLP TP 2 1 2 1 AC_LED 2 PC124 0.1U_0603_25V7K 3 1 2 CHG_B+ 1 2 PR105 10K_0402_5% ACOFF# PC113 4.7U_0805_25V6-K 8 BQ24740VREF PC112 1 PACIN 1 PR103 47K_0402_5% 1 PR108 10_1206_5% 2 2 ACDET LPREF 7 1 SUSP# 9 D PC104 4.7U_0805_25V6-K 1 2 1 1 PC109 @0.1U_0603_25V7K PC103 4.7U_0805_25V6-K 2 2 1 PR110 0_0402_5% S PR111 3K_0402_1% 8 7 6 5 CHG_B+ CHGEN# ACSET 2 PC107 @0.01U_0402_16V7K PR109<32,34,40,43,48,49,50> 150K_0402_5% G 1 PC102 1U_0603_6.3V6M 2 ACSET 2 1 1 D 2 ACDET PC108 0.1U_0603_25V7K 4 1 AC_SET 1 PQ105 DTC115EUA_SC70-3 1 2 3 PL101 HCB2012KF-121T50_0805 2 1 PR106 200K_0402_5% 1 1 PQ104 DTA144EUA_SC70-3 2 PC106 0.22U_0603_16V7K 3 1 2 1 PQ107 SSM3K7002FU_SC70-3 1 PR104 0_0402_5% <40> 2 3 2 PR102 0.012_2512_1% 8 7 6 5 2 PR107 47K_0402_1% 1 1 2 3 4 PR101 47K_0402_5% 1 PQ103 AM4835EP-T1-PF_SO8 1 2 3 2 PC101 47P_0402_50V8J 8 7 6 5 2 PQ101 AM4835EP-T1-PF_SO8 1 FSTCHG 1 2 P2 PQ113 SSM3K7002FU_SC70-3 3 G STD_ADP <40> PR136 49.9K_0402_1% D 2 S PU104 ACDET 2 2 2 5 ANODE NC 3 1.24VREF 2 4 1 LMV431ACM5X_SOT23-5 Compal Secret Data Security Classification Issued Date 2007/05/29 Deciphered Date 2008/05/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A CATHODE NC 22P_0402_50V8J 100K_0402_1% PR138 4 1 PC127 PR137 20K_0402_1% REF 1 4 1 B C Title Compal Electronics, Inc. Charger Size Document Number Rev 0.1 Montevina Consumer Discrete Date: Friday, October 05, 2007 D Sheet 44 of 51 A B C D E S G 3 5 6 7 8 1 2 10U_1206_25V6M PC305 PC317 @0.1U_0402_25V4K 1 2 LG_5V 3 2 1 UG1_5V 1 2 +5VALWP TPS51125RGER_QFN24_4X4 1 + 4 1 2 PC311 10U_0805_10V6K 1 2 PR312 @0_0402_5% PR318 1 2 0_1206_5% 3 2 1 PC315 @680P_0603_50V7K 1 2 PC310 220U_6.3VM_R15 19 PL303 4.7UH_SIL1045R-4R7PF_6.3A_30% 5 6 7 8 LX_5V 1 ENTRIP1 2 PC304 2200P_0402_50V7K 20 18 VCLK 21 PR308 PC308 0_0402_5% 0.1U_0402_10V7K BST_5V 1 PR310 2 1 2 0_0402_5% UG_5V 1 2 2 2 PR311 620K_0402_5% 1 PQ306 SSM3K7002FU_SC70-3 2 S 22 VL 2 1 3 1 2 G VREG5 EN0 13 VIN DRVL1 1 DRVL2 23 2 12 LL1 2VREF_51125 D 1 DRVH1 LL2 ENTRIP2 D ENTRIP1 3 4 DRVH2 B++ PQ305 SSM3K7002FU_SC70-3 VFB1 VREF VFB2 TONSEL VBST1 1 <45> PGOOD VBST2 2 PQ304 FDS6690AS_NL_SO8 3 PC312 0.1U_0603_25V7K ENTRIP1 VREG3 PQ302 AO4466_SO8 4 24 2 2 1 1 2 3 4 3 <45> 10 11 PC314 @680P_0603_50V7K PR315 @4.7_1206_5% PC309 220U_6.3VM_R15 2 PQ303 AO4466_SO8 UG_3V LG_3V 1 + 9 17 8 7 6 5 1 0_0402_5% PC307 0.1U_0402_10V7K LX_3V BST_3V 16 2 2 GND 1 2 3 2 +3VALWP 1 2 1 VO1 SKIPSEL UG1_3V 8 PR307 1 5 VO2 4 2 PR316 @4.7_1206_5% 7 PL302 4.7UH_SIQB74B-4R7PF_4A_20% ENTRIP2 P PAD PR306 133K_0402_1% 1 15 1 PU301 25 PQ301 AO4466_SO8 PR309 0_0402_5% 6 2 2 PC306 10U_0805_6.3V6M 8 7 6 5 1 PC303 4.7U_0805_25V6-K 2 1 2 1 PC301 2200P_0402_50V7K 2 1 B++ 2 1 PR304 24K_0402_1% 1 2 2 PR303 20K_0402_1% PR305 137K_0402_1% 2 2 1 +3VLP 2 PC316 @0.1U_0402_25V4K 1 PR302 37.4K_0402_1% 1 2 ENTRIP2 PL301 HCB2012KF-121T50_0805 PR301 13.7K_0402_1% 1 14 B++ B+ 1 2 1 1 PC302 0.22U_0603_10V7K 2VREF_51125 +5VL VL PJP304 2 PJP302 +3VALWP EC_ON <40> G SSM3K7002FU_SC70-3 1 +3VL +3VLP PJP301 2 2 +3VALW (3A,120mils ,Via NO.= 6) PAD-OPEN 2x2m PAD-OPEN 4x4m 4 om 100K_0402_5% PR314 Security Classification Compal Secret Data 2007/05/29 Issued Date Deciphered Date 2008/05/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A 1 l.c 3 (4.5A,180mils ,Via NO.= 9) PAD-OPEN 4x4m PJP303 2 3 +5VALW B C Compal Electronics, Inc. ai 1 PC318 0.022U_0603_25V7K 2 4 PR313 100K_0402_5% PQ307 PAD-OPEN 2x2m 2 D Title nf @ ho tm S 1 3.3VALWP/5VALWP Size Document Number Rev 0.1 Montevina Consumer Discrete Date: Friday, October 05, 2007 ai S 2 G PR317 604K_0402_1% +5VALWP he x D VL 1 2 D 2 2 1 <40,46> ACIN 1 PQ308 SSM3K7002FU_SC70-3 1 1 1 Sheet E 45 of 51 A B C D 1 1 PR401 0_0402_5% 1 2 PL401 HCB1608KF-121T30_0603 1 2 1 2 2200P_0402_50V7K PC405 1 2 @4.7U_0805_25V6-K PC404 1 2 1 2 4 PQ401 AO4466_SO8 LX_1.05V 2 PL402 2.2UH_PCMC063T-2R2MN_8A_20% 1 1 V5DRV PGOOD DRVL 1 +5VALW 10 2 2 PR406 15K_0402_1% 1 + 9 DL_1.05V 2 4 TPS51117RGYR_QFN14_3.5x3.5 +1.05V_VCCP PC412 @680P_0603_50V7K 2 3 2 1 10.5K_0402_1% 1 PR407 @4.7_1206_5% 2 2 VFB 11 5 6 7 8 TRIP 7 +1.05V_VCCP PR408 V5FILT PC411 @0.1U_0402_10V7K 2 1 PR411 1 6 2 1 5 PC409 1U_0603_10V6K PC406 @680P_0402_50V7K 2 12 1 0_0402_5% 1 LL DH_1.05V 1 VOUT 13 PC410 @0.1U_0402_10V7K DRVH PGND 4 B+ 14 VBST TP 1 PC402 0.1U_0402_10V7K 2 2 3 2 4.7U_0805_25V6-K PC403 BST1_1.05V1 1 PC408 220U_6.3VM_R15 1 0_0402_5% TON 8 2 2 GND +1.05V_VCCP 2 15 1 PR404 255K_0402_1% 1 PR405 2 PR402 0_0402_5% PU401 2 2 PC415 4.7U_0805_10V6K EN_PSV PR403 316_0402_1% 2 1 BST_1.05V 1 @0.1U_0402_25V4K PC414 +5VALW 5 6 7 8 PC401 @1000P_0402_50V7K 3 2 1 1 1.05V_B+ 2 PR410 @10K_0402_5% 2 1 SUSP# PQ402 AO4466_SO8 2 1 PC413 @10P_0402_50V8J 2 PR409 25.5K_0402_1% 3 3 PJP401 +1.05V_VCCP 1 2 +VCCP (6A,240mils ,Via NO.=12) PAD-OPEN 4x4m 4 4 Security Classification Issued Date Compal Secret Data 2007/05/29 Deciphered Date 2008/05/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title Compal Electronics, Inc. 1.05V_VCCP Size Document Number Rev 0.1 Montevina Consumer Discrete Date: Friday, October 05, 2007 Sheet D 46 of 51 5 4 3 2 1 PR521 200K_0402_1% +NVVDDP1 2 1 PR519 10_0402_5% PR518 2 B+++ 2 0_0402_5% 9 10 PR508 11 12 LL2 LL1 DR VL2 DR VL1 22 BST_VGA 21 UG_VGA 20 LX_VGA 19 LG_VGA 2 1 1 2 2 5 6 7 8 1 2 1 2 UG1_VGA 1 +NVVDDP PL501 1UH_PCMC063T-1R0MN_11A_20% PR509 0_0402_5% 1 2 1 1 PGND1 PC510 4.7U_0805_6.3V6K 2 1 2 4 2 PC518 @680P_0603_50V7K PC519 @680P_0603_50V7K 3 2 1 PR511 12.4K_0402_1% 2 PR510 16.5K_0402_1% 2 PQ503 FDS6670AS_NL_SO8 2 2 1 1 + 330U_D2_2.5VY_R9M TPS51124RGER_QFN24_4x4 PC508 2 TRIP1 1 PR516 @4.7_1206_5% 18 17 V5IN 16 TRIP2 V5FILT 15 PGND2 13 1 2 PC509 4.7U_0805_6.3V6K 14 PR515 @4.7_1206_5% 1 2 2 220U_B2_2.5VM PC517 1 PC504 4.7U_0805_25V6-K +NVVDDP +NVVDD_SENSE 2 1 VO1 VFB1 3 5 4 DR VH1 C 5 6 7 8 LX_1.5V LG_1.5V VBST1 DR VH2 4 PC507 0.1U_0402_10V7K PR507 0_0402_5% 23 1 1 VBST2 24 1 UG_1.5V 1 EN1 PC525 @0.1U_0402_10V7K BST_1.5V 1 2 PGOOD1 EN2 2 1 2 UG1_1.5V PGOOD2 PQ501 AO4466_SO8 PC524 @0.1U_0402_10V7K 2 PL503 3.3UH_PCMC063T-3R3MN_6A_20% 8 +NVVDD_SENSE 1 +1.5VSP PR506 0_0402_5% 1 3 2 1 7 PC506 0.1U_0402_10V7K P PAD GND 25 VFB2 8 7 6 5 TONSEL PU501 1G 1S/2D 1S/2D 1S/2D SP8K10S-FD5_SO8 2 6 1 C D1 D1 G2 S2 VO2 PQ502 1 2 3 4 + B+ PL502 HCB2012KF-121T50_0805 0_0402_5% 2 1 PR505 0_0402_5% 1 2 PC516 @0.1U_0402_10V7K 2 1 2 PC521 @0.1U_0402_25V4K 1 D 1 2 PR504 15K_0402_1% 2 1 PR503 75K_0402_1% 2200P_0402_50V7K PC505 PC511 4.7U_0805_25V6-K 2 High: +NVVDDP 1.0V Low: +NVVDDP 0.9V 2 1 PR502 75K_0402_1% 2 @0.1U_0402_25V4K PC520 1 2 2200P_0402_50V7K PC502 1 2 PC501 4.7U_0805_25V6-K +1.5VSP 2 D PR501 73.2K_0402_1% 1 1 1 S B+++ GPU_VID <32,40,41,43,52> PC522 0.01U_0402_16V7K 1 3 D PR520 105K_0402_1% 2 2 PQ504 SSM3K7002FU_SC70-3 1 G 2 1 PR513 0_0402_5% 2 <32,34,40,43,46,48,50> SUSP# PR512 0_0402_5% 1 1 B 1 2 2 SYSON <32,40,41,43,52> +5VALW B 1 PR517 @100K_0402_5% PC512 @0.1U_0402_16V7K 2 PC515 4.7U_0805_10V6K 2 1 2 2 PC513 @0.1U_0402_10V7K 1 PC514 1U_0603_10V6K 2 1 1 PR514 3.3_0402_5% PJP501 1 +1.5VSP 2 +1.5VS (4A,160mils ,Via NO.=8) +NVVDD (12A,480mils ,Via NO.= 24) PAD-OPEN 4x4m PJP502 1 +NVVDDP 2 PAD-OPEN 4x4m PJP503 1 2 PAD-OPEN 4x4m A l.c om A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 Compal Electronics, Inc. ai 2008/05/29 2 Title 1.5VSP/VGA_CORE Size Document Number Rev 0.1 Montevina Consumer Discrete Date: Friday, October 05, 2007 ai Deciphered Date nf @ ho tm Compal Secret Data 2007/05/29 Issued Date he x Security Classification Sheet 1 47 of 51 5 4 3 2 1 D D +1.8V PU601 VIN VCNTL GND NC VREF NC VOUT NC 6 +5VALW 5 3 PR601 1K_0402_1% 7 8 2 4 1 1 2 2 1 2 PC602 @10U_0805_10V4Z 1 PC601 10U_0805_10V4Z 2 1 TP PC603 1U_0603_16V6K 9 G2992F1U_SO8 2 C +0.9VP 1 2 S 2 G 2 2 PR603 1K_0402_1% 2 1 PR604 0_0402_5% 1 <43> SUSP D 1 PQ601 SSM3K7002FU_SC70-3 1 1 PR602 @0_0402_5% PC604 0.1U_0402_16V7K 1 3 <42,43> SYSON# PC605 10U_0805_6.3V6M C 2 PC606 @0.1U_0402_16V7K 2 1 +5VALWP POK 1 PU603 7 VIN VIN 1 2 +PCIE PC611 @0.01U_0402_16V7K (2A,80mils ,Via NO.= 4) VOUT 3 +1.1V_PCIE 4 1 1 EN PC610 10U_0805_10V6K FB 2 PC612 22U_0805_6.3V6M B 1 +1.1V_PCIE 8 9 1 PJP603 B 2 PR606 0_0402_5% 2 1 SUSP# GND VOUT <32,34,40,43,46,48,49> 5 2 (2A,80mils ,Via NO.= 4) 2 +0.9V 1 2 PAD-OPEN 3x3m PR607 40.2K_0402_1% PAD-OPEN 3x3m PC613 47P_0402_50V8J 1 2 APL5913-KAC-TRL_SO8 2 1 VCNTL +0.9VP +1.5VS PC609 1U_0603_6.3V6M 6 PJP601 2 PR608 105K_0402_1% A A Compal Secret Data Security Classification Issued Date 2006/11/23 Deciphered Date 2007/11/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. 0.9VP/1.1V_PCIE Size Document Number Rev 0.1 Montevina Consumer Discrete Date: Friday, October 05, 2007 Sheet 1 48 of 51 5 4 3 2 1 2 5 4 470P_0402_50V7K PC222 2 220P_0402_50V7K 255_0402_1% 1 2 1 2 1 1 B 1 3 2 1 3 2 1 1 2 PC208 1000P_0402_50V7K 2 2 1 PC237 @0.1U_0402_25V4K 1 PC207 2200P_0402_50V7K 1 1 2 1 2 1 1 2 2 1 1 1 1 1 2 PC223 1 2 0.22U_0603_10V7K VCC_PRM ISEN2 CPU_B+ B 2 VSUM 1 PC228 0.01U_0603_50V7K 1 PR243 1K_0402_1% 1 2 PR244 3.57K_0402_1% PC230 0.1U_0402_16V7K VCC_PRM 1 2 2 10KB_0603_5%_ERTJ1VR103J PH201 1 1 2 2 1 PR242 PC229 180P_0402_50V8J 11K_0402_1% VSSSENSE 2 2 PC227 @0.022U_0603_50V7K PR241 1 1 2 5 1 VSUM 2 PC226 820P_0603_50V7K VCCSENSE 2 @0_0603_5% PC225 0.1U_0603_25V7K 2 PR240 1K_0402_1% 5 PQ206 AO4456_SO8 PR239 10_0603_5% PC224 1000P_0402_50V7K PR238 1 +5VS 1_0402_5% PR233 2.61K_0402_1% 1 2 PR234 1_0603_5% PC221 1U_0402_6.3V6K PR232 2 4 PQ205 AO4456_SO8 1 PL203 2 PU201 1 1 1 2 2 2 PR237 1 1K_0402_1% PC220 2 2 2 PC217 0.22U_0603_10V7K ISEN1 ISEN2 1 PR236 2 @0_0402_5% 1 1 0.36UH_PCMC104T-R36MN1R17_30A_20% 2 1 1 PR230 3.65K_0805_1% 25 2 PC218 1000P_0402_50V7K PR235 97.6K_0402_1% 2 UGATE_CPU2-2 2 0_0603_5% PC238 @0.1U_0402_25V4K PR225 1 C PC236 4.7U_0805_25V6-K BOOT_CPU2 1 PR227 0_0603_5% PR231 10K_0402_1% UGATE_CPU2-1 26 PC213 4.7U_0805_25V6-K PHASE_CPU2 PC212 4.7U_0805_25V6-K D D D D G S S S 28 27 PC219 @680P_0603_50V7K ISEN1 NC 24 ISEN2 23 22 VDD GND 21 VIN 20 VSUM 19 VO 18 13 2 DFB 2 1 17 FB2 DROOP 1 12 16 1000P_0402_50V7K PC216 PR228 6.81K_0402_1% RTN 2 BOOT2 15 1 UGATE2 FB 2 1 CPU_B+ 1 2 11 COMP 29 PR229 @4.7_1206_5% 10 2 PHASE2 VSEN 13K_0402_1% 1 PGND2 VW LGATE_CPU2 2 9 VDIFF PR226 2 14 1 LGATE2 ISL6262ACRZ-T_QFN48_7X7 OCSET PC215 30 PQ204 SI4684DY-T1-E3_SO8 4 3 2 1 SOFT 8 0.022U_0603_25V7K 31 2 PR220 10K_0402_1% 2 PR219 3.65K_0805_1% VCC_PRM 2 LGATE_CPU1 32 5 6 7 8 7 PVCC 2 ISEN1 0.22U_0603_10V7K 1 PQ203 AO4456_SO8 1 2 PR218 @4.7_1206_5% 3 2 1 PHASE_CPU1 2 PC211 1 5 6 7 8 LGATE1 34 33 1 VSUM 2 PGND1 PQ202 AO4456_SO8 UGATE_CPU1-1 +VCC_CORE PR224 @0_0603_5% PC235 4.7U_0805_25V6-K PHASE1 RBIAS 36 35 1 PR223 1_0402_5% PC214 2200P_0402_50V7K PMON 4 1 5 6 7 8 2 2 4 BOOT1 NTC PC206 4.7U_0805_25V6-K 1 PC205 4.7U_0805_25V6-K G S S S 4 3 2 1 37 2 5 6 7 8 6 D PL202 0.36UH_PCMC104T-R36MN1R17_30A_20% 0_0603_5% PR217 VID0 38 VID1 39 VID2 40 VID3 41 VID4 42 VID5 43 VID6 45 44 VR_ON 46 47 1 UGATE1 VR_TT# 2 2 1 PC234 4.7U_0805_25V6-K 5 6 7 8 D D D D PC233 4.7U_0805_25V6-K PC204 68U_25V_M_R0.44 1 2 2 2 5 C 1 1 1 PR213 1 2 0_0402_5% PR205 2 1 PR212 1 2 0_0402_5% PR211 1 0_0402_5% 0_0402_5% 2 0_0402_5% 2 1 5 6 7 8 5 CPU_VID0 5 5 5 5 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 PR210 2 1 PR209 0_0402_5% 2 1 PR208 PR207 1 2 PQ201 SI4684DY-T1-E3_SO8 1 4 VR_TT# 48 PSI# 3 2 + PC210 @680P_0603_50V7K 1 1 0.22U_0603_10V7K UGATE_CPU1-2 PC209 1 3 2 1 1 PR221 2 @0_0402_5% PR222 147K_0402_1% PC203 2.2U_0603_6.3V6K 2 49 PGOOD 2 DPRSLPVR H_PSI# DPRSTP# VGATE 5 1 1 2 PC201 1U_0603_6.3V6M 1 15,20 0_0603_5% PR214 BOOT_CPU1 GND 2 2 1 1.91K_0402_1% PR216 2 1 +3VS PR215 2 0_0402_5% 1 3V3 PR206 0_0402_5% 1 CLK_ENABLE# +3VS @499_0402_1% 2 0_0402_5% 0_0402_5% PR204 2 1 H_DPRSTP# PC202 0.022U_0402_16V7K 0_0402_5% CLK_EN# 5,7,19 CPU_VID5 2 PR203 PL201 SMB3025500YA_2P 2 499_0402_1% 1 7,20 DPRSLPVR B+ CPU_B+ PR202 1_0603_5% 2 PR201 D CPU_VID6 VR_ON 5 32 +5VS 2 PC232 0.22U_0402_6.3V6K PC231 0.22U_0603_10V7K 2 1 2 1 A nf @ ho tm ai l.c om A Compal Electronics, Inc. Title +CPU_CORE 5 4 3 2 Date: Friday, October 05, 2007 Rev 0.1 ai Size Document Number Custom he x THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Sheet 1 49 of 51 A B C D 1 1 PR701 0_0402_5% 2 1 PL701 HCB1608KF-121T30_0603 1 3 TON 4 1 B+ 2 1 2 2200P_0402_50V7K PC706 1 2 4.7U_0805_25V6-K PC705 2 1 4.7U_0805_25V6-K PC704 PC703 0.1U_0402_10V7K 2 PC707 @680P_0402_50V7K TP 14 15 2 2 BST1_1.8V 1 1 2 DRVH VOUT LL 13 DH_1.8V 12 LX_1.8V 1 PR711 2 PQ701 AO4466_SO8 PL702 2.2UH_PCMC063T-2R2MN_8A_20% 0_0402_5% 1 2 +1.8VP PC713 @680P_0603_50V7K 2 2 PQ702 FDS6690AS_NL_SO8 1 3 2 1 28K_0603_0.1% + 1 5 6 7 8 4 TPS51117RGYR_QFN14_3.5x3.5 1 2 PC717 4.7U_0805_6.3V6K 1 DL_1.8V 2 +5VALW 9 PR707 @4.7_1206_5% 2 10 2 PR706 17.8K_0402_1% 2 2 DRVL 1 PC712 @0.1U_0402_10V7K PR708 PGOOD V5DRV 11 PC711 @0.1U_0402_10V7K 1 VFB 7 +1.8VP TRIP 1 6 2 1 5 PC710 1U_0603_10V6K V5FILT PGND 4 PC709 330U_D2_2VY_R15M 1 0_0402_5% 8 PR705 2 GND 2 2 VBST 2 1 +1.8VP 1 PU701 PR704 255K_0402_1% EN_PSV 2 1 PR703 316_0402_1% 2 2 PR702 0_0402_5% 3 2 1 1 BST_1.8V1 PC716 4.7U_0805_10V6K 1 5 6 7 8 +5VALW @0.1U_0402_25V4K PC701 1.8V_B+ 2 PC702 @1000P_0402_50V7K 1 1 SYSON 2 PR709 19.6K_0603_0.1% 3 3 PJP701 +1.8VP 1 2 +1.8V (7A,280mils ,Via NO.= 14) PAD-OPEN 4x4m PJP702 1 2 PAD-OPEN 4x4m 4 4 Security Classification Issued Date Compal Secret Data 2007/05/29 Deciphered Date 2008/05/29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title Compal Electronics, Inc. 1.8VP Size Document Number Rev 0.1 Montevina Consumer Discrete Date: Friday, October 05, 2007 Sheet D 50 of 51 5 Item Fixed Issue 4 Reason for change 3 PAGE 2 1 Modify List Note D C C B B A A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. PIR Size Document Number Rev 0.1 Montevina Consumer Discrete Date: ai 2007/09/26 Deciphered Date Friday, October 05, 2007 Sheet 1 he x 2007/09/26 nf @ ho tm Compal Secret Data Security Classification Issued Date ai l.c om D 51 of 51
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