II Computer Graphics Service Manual

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Model IIComputer Graphics
Upgrade K i t
Catalog Number 26-4104

‘

CUSTOM MANUFACTURED IN U S A . BY RADIO SHACK, A DIVISION OF TANDY CORPORATION

‘

TRS-BD ®

Contents

l / S p e c i fi c a t i o n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2/Installation I n s t r u c t i o n s

3 / l e k Diagram

O

O

O

O

O

...... . . . . . . . . . . . . . . . . . . . . . . . . . . 5

0.00.0.0...U...IIOOOOICCOOOOOOIQOCOIIIll

4 / Tr o u b l e s h o o t i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . l 3
S/Timing Crlart.O...OI.D0..OO..O'...II.O'COOOOOICOCCOOIIOOOlS

6/Printed C i r c u i t Board L a y o u t . . . . . . . . . . . . . . . . . . . . . . . . . . . . l 6

7/Parts L i s t

........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

B/mharatic Diagrm.‘II.I000...0.....00.000DOCOOCCICOIIOOZl
9/Theory o f O p e r a t i o n . . . . . . . .

....... . . . . . . . . . . . . . . . . . . . . . . 2 3

Radlo Ihael?

TRS-BD ®

'IRS‐Bfl" Graphics Board Service m n u a l : Copyright" 1982
Tandy Corporation, F o r t Worth, Te x a s 761162 U. S. A.
A l l R i g h t s Reserved.

Reproduction or u s e , w i t h o u t express w r i t t e n permission f r o m
Tandy Corporation, of any p o r t i o n of t h i s manual is
‑
p r o h i b i t e d . While reasonable e f f o r t s have been taken i n t h e
preparation of t h i s nanual to a s s u r e i t s a c c u r a c y, Tandy
Corporation assumes no l i a b i l i t y r e s u l t i n g from any e r r o r s
or omissions in t h i s manual, or f r o m t h e u s e of t h e
i n f o r m t i o n obtained herein.

Radlo1'hack”

Graphics Board

TRS‐BO ®

Service Manual

1/8pecifications
Power Requirements

(Supplied by Model

I I )

5V at 659! mA
+12V at 15¢ mA
-12V at lSmA

Operating Conditions

Same as Model II

I/O Requirements

16 Contiguous Z8IJ Hardware
I/O P o r t s , u s e r selectable

Time r e q u i r e d to w r i t e a
data word

1 . 3 Microseconds (Minimum)
65.5 Microseconds (Maximum)

Radio lhaelf’

Graphics Board

Service Manual

Tns-Bo ®

2/Insta11ation I n s t r u c t i o n s
Installation
Before t h e Graphics Board can be installed, t h e CPU board of
the Model II must be fi t t e d w i t h t h e DMA WAIT Modification.
This modification consists of a ROM IC and a series of c u t s
and jumps which is a l s o used f o r t h e Hard Disk system.
Look at t h e CPU Board.

REV A, B, and C Boards trust be

modified. REV D Boards do n o t need to be modified. If t h e
Model II is fi t t e d w i t h t h i s modification, proceed to t h e
next section.
Modifying t h e CPU Board
F o l l o w t h e procedure below c a r e f u l l y :

1.

Disconnect t h e cables connecting t h e CPU Board and
remove t h e board.

2.

Remove and discard U11. I n s t a l l t h e new Boot ROM in i t s
p l a c e . B e s u r e t o p o s i t i o n t h e ROM c o r r e c t l y ( m a r k e d

end toward U 1 2 ) .
3.

C u t t h e f o l l o w i n g traces o n t h e CPU Board and add t h e

f o l l o w i n g jumper w i r e s .

.
.

R e f e r t o Figures 1 , 2 , and 3 .

C u t t h e f o i l t o i s o l a t e U13 P i n 6 .
C u t t h e f o i l t o i s o l a t e U 4 P i n 12.

J ImIperS

IC

Pin

U21
U21
U21
U21
U15
U15
U24

IC

Pin

1
6
4
5

024
U4
J”
U15

8
12
48
ll

12
l3

UZIJ
U24

l3
4

3

U215

14

‐ ‐ - ‐ ‐ - ‐ . ~ ‐ - - - . _

to

-

.

.

_

-

_

_

‐

‐

-

-

‐

‐

_

‐

‐

_ _ _ _ _ _ - _ _ _ _ ‐ ‐ ‐ ‐ ‐ _ _ _ - - _ ‐ . _ . . ‐ ‑

Radio lhael?

Graphics Board

Service Manual

TRS-BO ®

DMA E X T '

BUSRO' (BUS)

0

BAO (DMA CHIP)

‘-

U3
-

'08

FROM EIOUT
(U24, p i n 3 )

“ESE.”

K.

U21,P11

" “ A

3

U13

'

74LS74

.

3
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5

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8

‐9

ADD THIS

READ“

CUT TRACE HERE

U22

j»

‘2

.

SELECT'

Figure l. I n t e r r u p t Modification f o r CPU Board

BUSAK‘I

CEDMA“

DMA

P15

TP

1

'‐_.

TP13

U31 8 1 U32

CUT EXISTING TRACE

CE/WAIT
U20, P16

WAIT’ J0. P48

BUSAK‘r U20, P14
B A O ’ U20. P13

Figure 2. DMA Modification to CPU Board

Radio .l'llalek®

U315.1U32

Graphics Board

TRS-BO

®

Service bhnual

I n s t a l l i n g t h e C i r c u i t Board
Once t h e Nbdel II is working normally w i t h t h e WAIT
m o d i fi c a t i o n i n s t a l l e d , s e t t h e Power Switch t o t h e OFF
p o s i t i o n . Then:

1.

Remove t h e Video/Keyboard c a r d from t h e Model I I . Be
sure to remove t h e t w o cables ( v i d e o and keyboard).

2.

CAREFULLY renove t h e m6845 VDG IC ( U 11 ) and t h e
character generator ROM ( U 9 ) f r o m t h e i r sockets on t h e

Video/Keyboard c a r d .
3.

I n s e r t those two I C ' s i n t o t h e sockets on t h e Graphics
board. The VDG goes in U38, t h e ROM in U25. NOTE THAT

'I‘HEROMISREVERSEDFWTHEO‘I‘HERCHIPS.

4.

I n s t a l l t h e two r i b b o n cables. The cables g o between t h e
headers on t h e Graphics Board and t h e now empty IC
sockets on t h e Video Board. See t h e drawing below f o r
d e t a i l s . N o t e t h a t t h e 24 conductor cable is t w i s t e d to
a l l o w t h e r e t a i n e r bar t o h o l d t h e cards i n p l a c e . The
pins i n t h e cable a r e f r a g i l e s o b e c a r e f u l when
i n s e r t i n g them i n t h e sockets.

\ \ ‘

BLUE CONDUCTOR

GRAPHICS BOARD

E

‘

‘

llllllllllllllHlWlIH|||l
VIDEO BOARD

D 4‘17‐

6845 SOCKET
CHAR. ROM SOCKET

Figure 4 . Cable I n s t a l l a t i o n

5. Check to see t h a t t h e DIP switch on t h e Graphics Board is
s e t to 89H (OFF,ON,ON,ON). See Figure 5.

Radio Ihaek®

Graphics Board

S e r v i c e Manual

TRS-BD ®

1

2

3

4

ON

OFF

F i g u r e 5 . DIP Switch S e t t i n g s

6. I n s e r t t h e two boards in adjacent s l o t s in t h e Model II
motherboard. Replace t h e two cables on t h e Video Board.

7. R u n t h e Graphics Board Te s t HIRES.
t h e D i a g n o s t i c s D i s k e t t e AXX‐2fl34.

This is

contained on

8. If the t e s t r e s u l t s a r e positive, replace the retainer
b a r and c o v e r. If t h e t e s t f a i l s , recheck a l l cables a n d
b e s u r e t h a t t h e I C ' s a r e c o r r e c t l y i n s t a l l e d . Check
a l s o t o see t h a t a p i n i s n ' t f o l d e d under a n I C . R e f e r
t o 3 / Tr o u b l e s h o o t i n g f o r more h e l p .

Radio Ihaek®

Graphics Board

®

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Graphics Board

Tns-Bo ®

Service Manual

4/Troubleshooting
F i r s t i s o l a t e t h e problem to t h e Graphics Board. Then r u n
t h e Graphic Board Te s t HIRES, contained on t h e Diagnostic
Diskette AXX‐29134.

Some s p e c i fi c symptoms a n d suggestions.

Computer "hangs u p " , w o n ' t respond to 
(DNA has seized t h e b u s . )

.

I n s u r e " w a i t mod" i s i n s t a l l e d o n CPU board.

.

Check t h e M1* Mod

(cuts

and junps o n Rev "A" b o a r d s )

Won't r e a d or w r i t e to Screen
( U 2 8 n o t r e c e i v i n g p r o p e r commands)
.

Check address decoding (U22,U23,DIP S w i t c h )

Check s i g n a l s o n U28

Places dots e r r a t i c a l l y o n t h e screen.
( L i n e a r Address Generator m a l f u n c t i o n )

.

X and Y ROMS reversed, or malfunctioning

.

Check shorts and opens near X and Y mMS

Writes b u t w o n ' t r e a d
(U18 and r e l a t e d c i r c u i t r y )
.

Check f o r proper s i g n a l s a t p i n s 1 and 11 o f U18

A f t e r board warms u p , dots seem t o fade i n and o u t , o r wont
erase .
(RAM P r o b l e m s )

Radio Illael?

- 1 3 ‑

Graphics Board
.

TRS-BO

®

Service Manual

Some dynamic RAMs ( n a r k e d M K 4 3 1 5 ) my need to be replaced

(he

to t h i s problem.

Radio .I'haek®
_ 1 4 ‑

Graphics Board

Service Manual

TRS-BO ®

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Graphics Board

6/Printed C i r c u i t

Service Manual

TRS-BD ®
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Radlo .rllaek®
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Graphics

Service Manual

Board

'TFRES-EBCD ®

7/Parts L i s t
Electrical Parts
Capacitors

lUF SWVDIWD AXIAL

837-4lfl4

l U F 5¢V MONO AXIAL
$.1UF SWVIWNWD AXIAL
lflUF 25V ELEUTR. RADIAL
fl.lUF 5¢V MONO AXIAL

837-4lfl4
837-4lfi4
832-6lfl2

fl.lUF 5¢V MONO AXIAL
lflUF 25V ELECTR. RADIAL
fl.lUF 5W IVDNO AXIAL

837‐4lfl4
832-61fl2
837-4lfl4

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1¢UF 25v ELaaTR. RADIAL

837-4lfl4

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C8
C9

837‐4lfl4

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C34
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C52
C53
C54
C55
C56
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fl.lUF 5¢v MONO AXIAL

832-6lfl2
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837-4lfl4
837‐4lfl4
83l-7lfi7
837-4lfl4

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837-4lfl4

1¢UF 25v ELEUTR. RADIAL
1¢¢UF 16v ELECTR. AXIAL

to

C76

Resistors

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to

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829‐n¢27
829-fl21g

829-fl21fi

Integrated Circuit

Radio Ihael?

_ 18 _

Graphics Board

U1

Service Manual

Tns-ao ®

4116 16K X 1 DYNAMIC RAM 21mm 1 6 ‑P I N

8134-21516

4116 16K X l DYNAMIC RAM 213616 1 6 ‑P I N
SN74ISZ73NDS OCTAL FLIP-FIDP " 2¢-PIN
SN74LS374NDS OCTAL FLIP-FIDP " 2fl-PIN
SN74ISZ73NDS OCTAL FLIP-FIOP " ZU-PIN
SN74LSBI\DS QUAD 2 - I N EXCLUSIVE OR " l 4 ‐ P I N
AM83¢3B OCTAL INVERT TRANSCEIVER AMD za-PIN
N74885NB 4-BIT MAGNITUDE COMP. l 6 ‑P I N
SN74L8155NDS DECODER
SN74LSBDDS QUAD Z‐IN E ( C L U S I V E OR " l4-PIN

8134-2616

to

U16
Ul7
U18
U19
U21]
U21
U22
023
U24
U24
U27
U28
U29

03¢
U31
U32
U33
U34
U35
U38
U39
U413

U41
U42
U43

SN74LSZ4JJNDS OCTAL BUS INVERTER " ZIJ-PIN
SN74ISZ73NDS OCTAL FLIPFIDP " 2fl-PIN
16R4 PAL CHIP NMI l 6 - P I N
SN74LSl91NDS UP/mWN BINARY CNTR" 16-PIN
SN74LSl91NDS UP/IDWN BINARY CNTR" 16-PIN
N74Sfl4NB HEX INVERTER " l 4 - P I N

N74832NB QUAD 2 - I N OR " 14-PIN
N74fl7NB HEX HJFFER OPEN-C
SN7415191NDS UP/mWN BINARY CNTR" l 6 - P I N
SN74LSl91NDS UP/mWN BINARY CNTR" 16 -PIN
N74SHQ'NB QUAD 2 - I N NAND
SN74LSlS3bDS HJAL DATA SELECIUR " 16 -PIN
SN74L8153NDS DUAL DATA SELECTOR " 16 -PIN
8117418153st DUAL DATA SELECTOR " 16 -PIN
SN74L9153NDS DUAL DATA SELECTOR " 16-PIN

962-6273
962 41374
9fi2-flZ73

9fll-flfi86

98fl-611391
9151-11685

962-6155

9131-6686

9fl2-flZ4E
9,02-fl273
9152-16191
91252‐125191
9161-1615154

9a¢~1¢32

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915241191
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9fll‐WW

9132‐15153
9152‐16153
91212-15153
9912-16153

ROM

U36
U37

'I‘BP28L22 256K X 8 "Y" ROM 6 l e Zfi-PIN
TBPZSLZZ 256K X 8 "X" ROM 6MB 2¢-PIN

9214-1251622

9134-1622

Vo l t a g e Regulator
REGULATOR

79Lfl5 ACP

8155-19155

Mechanical P a r t s
ASSY. CABLE, ( C H R . G E N . ) 5.6" AMP
ASSY. CABLE, ( V D G " ) 8 . 5 " AMP # 6

J1
J2

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U1

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ZH-POS.

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#3-435668-4 8‐PIN

16-PIN

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87fi-9274
.87IJ-9273
851-9134
851-9135
8513-65515
8551-92163

Graphics Board

TFIS-BD ®

Service Nanual

to

U16
U25
U28
U36
U37
U38

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SOCKET, l 6 - P I N
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SOCKET, 2fl-PIN
SOCKET, 2fl-PIN
SOCKET, Zfl-PIN
SOCKET, 4fl-PIN

85fl‐9flfil
85fi-9flfi9
85fi‐9flfl9
85g‐9flfl9

85fl‐9flfl2

879-2fl44

DISKEI‘TE, SYSTEM
MANUAL, SERVICE/INSTALLATION
NENUAL, OPERATIONS

874-9326

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Radlo thaol?
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Graphics Board

Service Manual

TRS-BD ®

9/Theory o f O p e r a t i o n

Introduction
G r a p h i c s B o a r d p r o v i d e s 640 h o r i z o n t a l d o t s a n d
240 v e r t i c a l d o t s o n t h e v i d e o s c r e e n f o r h i g h ‐ r e s o l u t i o n
g r a p h i c s . T h i s i s t h e same number o f d o t s u s e d b y t h e
c h a r a c t e r g e n e r a t o r : 8 0 c h a r a c t e r s e a c h u s i n g 8 d o t s o r 640
d o t s p e r l i n e . Each c h a r a c t e r i s 1 0 d o t s v e r t i c a l l y , s o 2 4
l i n e s u s e s 240 d o t s . The g r a p h i c s d o t s a r e a c c e s s e d t h r o u g h
t h e I / O p o r t s p e c i fi e d b y t h e D I P s w i t c h s e t t i n g .

The M o d e l I I

The G r a p h i c s B o a r d a t t a c h e s t o t h e V i d e o / K e y b o a r d c a r d u s i n g
two r i b b o n c a b l e s .
Theory of Operation

R e f e r to t h e Block D i a g r a m a n d Schematic D i a g r a m
f o l l o w i n g discussion.

f o r the

Bus I n t e r f a c e and Address Decoding

The G r a p h i c s B o a r d i s f u l l y b u f f e r e d f r o m t h e C P U . T h e l o w e r
e i g h t a d d r e s s l i n e s ( A 0 ‐ A 7 ) a r e b u f f e r e d b y U 2 6 , a n d t h e Z80
c o n t r o l l i n e s b y U 3 3 . S i n c e U33 i s a n o p e n c o l l e c t o r d e v i c e ,
RP4 p u l l s t h e o u t p u t s u p . T h e M o d e l I I d a t a b u s i s i n v e r t e d
o n t h e motherboard s o a n i n v e r t i n g b i ‐ d i r e c t i o n a l b u f f e r
( 0 2 1 ) i s used o n t h e d a t a l i n e s . T h i s b u f f e r has two c o n t r o l
l i n e s , D I R ( d i r e c t i o n , p i n 1 1 ) a n d a T R I ‐ S TAT E c o n t r o l
( D I S a b l e , p i n 9 ) . The D I R l i n e i s c o n n e c t e d t o BWR* ( b u f f e r e d
w r i t e ) which t e l l s t h e b u f f e r i f w e wish t o r e a d f r o m o r
w r i t e t o t h e d a t a b u s . When BWR* i s LOW, w e a r e w r i t i n g t o
t h e Graphics Board.
The d i s a b l e l i n e i s c o n t r o l l e d b y BSEL* ( b o a r d s e l e c t ) . W i t h
any access to t h e Graphics board I/O p o r t , t h i s l i n e goes
LOW w h i c h t u r n s t h e b u f f e r o n . When t h e b o a r d i s n o t b e i n g
accessed, t h i s l i n e is HIGH and t h e b u f f e r is o f f .

I / O d e c o d i n g i s d o n e b y h i g h s p e e d 4 - b i t c o m p a r a t o r U22 a n d
d u a l d e c o d e r U 2 3 . T h e c o m p a r a t o r s c a n s a d d r e s s l i n e s A4-A7
a n d t h e s e t t i n g o f t h e D I P s w i t c h 8 1 . When t h e t w o a r e e q u a l
AND a n I / O i n s t r u c t i o n i s r e q u e s t e d ( s i g n i fi e d b y BIOCYC*

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going 1 0 W ) t h e n BSEL* w i l l go LOW. The equals o u t p u t of t h e
74885 t u r n s on decoder U23 which uses t h e lower two address
l i n e s (AG and A l ) , BMR", and BRD* to produce t h e proper
strobes f o r t h e r e g i s t e r s .
The CR g a t e on BIOCYC* is s h u t o f f when Ml is a c t i v e ,
preventing Graphic Board access when e x t e r n a l devices a r e
acknowledging i n t e r r u p t s . M1 is inverted and ANDed w i t h t h e
I/O c y c l e to disable t h e board on I n t e r r u p t Acknowledge.

Since o n l y t h e lower two address l i n e s a r e 'being used, t h e
Graphics Board is "mirrored" f o u r times w i t h i n t h e 16 b y t e
boundary d e fi n e d by t h e DIP switch s e t t i n g . A l s o , t h e same
address i s used f o r reads and w r i t e s t o t h e d a t a r e g i s t e r .
Table 1 shows how t h e addresses a r e decoded:

ADDRESS

8¢H
81H

82H
83H
84H
etc

FUMION

X Register Write
Y Register Write
Video Data Wr i t e or Read
Options Write
X Register Write
etc

‐_...__‐.‐____._‐‐‐.-___‐_____.___‐‐‐___..__

Ta b l e 2. Address Decoding

I f a s t a r t i n g address o t h e r t h a n 8¢H i s desired, any 1 6
b y t e boundary from MJH to FIJH may be s e l e c t e d using 81.
However, a l l Radio Shack software is compatible w i t h t h e 8flH
I/O p o r t address. When t h e switch is ON, t h e b i t in t h e
boundary d e fi n i t i o n w i l l b e 16. F o r exaxrple, t o s e l e c t I/O
p o r t boundary 39H, t h e switches w i l l be ON, ON, OFF, OFF
( fl fl l l ) .

Registers (X Address, Y Address, D a t a , and Options)
Since t h e Graphics Board is asynchronous w i t h t h e Model II
( t h i s is explained in d e t a i l l a t e r ) t h e a r e several o c t a l
r e g i s t e r s which h o l d d a t a u n t i l t h e Graphics Board i s ready
to use i t .

The two address r e g i s t e r s a r e a c t u a l l y b i ‐ d i r e c t i o n a l b i n a r y
counters. U29 and U35 a r e f o r t h e X address, and U34 and U35

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a r e f o r t h e Y address. Each p a i r of counters has t h r e e
c o n t r o l l i n e s ; w r i t e (XREEWR*, YREGWR*) , c o u n t d i r e c t i o n
(XREG DEXZ/INC*, YREK; DEC/INC*), and count c l o c k (XCLK*,
Y C L K * ) . The w r i t e strobes a r e generated by t h e address
decoding c i r c u i t r y . A negative p u l s e w i l l l o a d t h e r e g i s t e r s
w i t h t h e d a t a o n t h e bus.
The two o t h e r s i g n a l s a r e generated from t h e custom l o g i c
a r r a y ( c a l l e d t h e "Mallory C o n t r o l l e r " ) U28. The c o u n t
c o n t r o l l i n e s a r e used to automatically increment or
decrement t h e address r e g i s t e r s a f t e r a r e a d or w r i t e . This
g r e a t l y speeds u p t h e software i n many a p p l i c a t i o n s .
The Options r e g i s t e r U27 i s used t o s e l e c t t h e u s e r
p r o g r a m a b l e o p t i o n s . These a r e described below. See Table

2.
,0

GRAPHICS/ALPHA*

Tu r n s o n and o f f t h e g r a p h i c s . A " 1 " w i l l t u r n graphics ON.

1

WAITS ON/OFF*

If WAITS a r e ON t h e screen w i l l n o t "hash" when reading or
w r i t i n g t o g r a p h i c s . A " l " s e l e c t s WAITS.

2

mm DEC/INC"

S e l e c t s whether t h e X r e g i s t e r w i l l decrement or increment.

" 1 " w i l l s e l e c t decrement.

3

YREG

DEC/INC*

S e l e c t s whether t h e Y r e g i s t e r w i l l decrement or increment.
" 1 " w i l l s e l e c t decrement.
4

X C L K RD*

I f address c l o c k i n g d e s i r e d , a "£5" w i l l c l o c k t h e x address
up or down AFTER a r e a d depending on t h e s t a t u s of B I T 2.
5

Y C L K RD*

I f address c l o c k i n g desired, a "[5" w i l l clock t h e Y address
up or down AFTER a r e a d depending on t h e s t a t u s of B I T 2.
6

X C L K V\R*

A

"fl" w i l l clock

AFTER a w r i t e .

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7

Y C L K WR*

A "16" w i l l c l o c k AFTER a w r i t e .
m

m

m

_

‐

I5

_

fl

Graph/Alpha
Wait/No Wait

l
2
3

x Dec/Inc
y Dec/Inc

4
5
6
7

x Read Set/Run
y Read Set/Run
x Write Set/Run
y Wr i t e Set/Run
Table 3 Options Progranming

If c l o c k i n g of t h e addresses is n o t needed, t h e upper f o u r
b i t s w i l l then a l l b e 1 ' s ( F x h e x ) .

There a r e two separate d a t a r e g i s t e r s ; one f o r w r i t i n g data
to t h e graphics memory ( U 1 7 ) and one f o r reading d a t a f r o m
t h e graphics memory ( 0 1 8 ) . Both a r e accessed t h r o u g h t h e
same I/O p o r t . A Z‐Sfl OUT w i l l w r i t e d a t a , and a n I N w i l l
r e a d data.
The w r i t e r e g i s t e r i s clocked o n each f a l l i n g edge o f t h e
system 4 MHz c l o c k . This is to guarantee t h a t t h e data w i l l
always b e v a l i d when t h e Merrory C o n t r o l l e r I C begins a w r i t e
to RAM.

The r e a d r e g i s t e r is an o c t a l l a t c h w i t h 'IRI‐STATE o u t p u t s .
M e n t h e Memory C o n t r o l l e r detects a r e a d c y c l e , i t w i l l
fi r s t l a t c h t h e RAM d a t a using t h e R D LATCH c o n t r o l l i n e .
When t h e *WAIT l i n e f r o m t h e Memory C o n t r o l l e r i s released
t h e Z‐8fl executes t h e I N i n s t r u c t i o n and reads t h e data.
CRl'C and Address Tr a n s l a t i o n

The 6845 is a Video Display Generator (VDG) which n o r m a l l y
provides monitor sync s i g n a l s and addresses to scan a
character generator ROM. These addresses a r e r e f e r r e d to as
"Line" and "Column" addresses, corresponding to t h e
h o r i z o n t a l l i n e s o n t h e CRT and t h e v e r t i c a l columns o f t h e
characters. Since t h e s e addresses a r e s e a m i n g a ROM which
is s e t up f o r a c e r t a i n character s i z e ( i n t h i s case 8 X
l fl ) , t h e y do n o t map to t h e g r a p h i c coordinates d i r e c t l y.

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The Graphics B o a r d uses two v e r y f a s t (613 n s ) b i p o l a r PROMS
(U36 and U 3 7 ) to t r a n s l a t e t h e 'Line‐Column" addresses to
" A b s o l u t e X-Y" addresses. A f t e r t h e addresses emerge f r o m
t h e PROMS, t h e y w i l l map to t h e addresses in t h e X and Y
registers.

Graphics M a m r y
The m a t r o r y s e c t i o n of t h e Graphics Board is t h e most
complex, and t h e H o s t l i k e l y t o n a l f u n c t i o n . I t consists o f
f o u r p a r t s : t h e Menory C o n t r o l l e r I C , t h e address
m u l t i p l e x e r s , menory t i m i n g , and t h e h o l d i n g r e g i s t e r .
Sixteen Zfifl ns 16K dynamic memories a r e used to s t o r e t h e
graphics d a t a , p r o v i d i n g a t o t a l o f 32K, although o n l y 19.2K
(8,05 X 24¢) is used.
To understand how t h e memory s e c t i o n works, r e f e r to t h e
system t i m i n g diagram.

It is important to n o t e t h a t t h e graphics memory is
asynchronous w i t h r e s p e c t to t h e CPU. In o r d e r to sync up ,
t h e Memory C o n t r o l l e r I C uses t h e WAIT* l i n e o n t h e Z‐8fl.
T h i s is n o t to be confused w i t h t h e WAIT option of t h e
Options r e g i s t e r , which uses t h e DISPEN s i g n a l f r o m t h e 6845
to suspend memory access u n t i l t h e beam of t h e CRT is b e i n g
blanked. R e f e r to t h e Model II Technical Reference Manual
f o r more d e t a i l s .
The b r a i n o f t h e memory s e c t i o n i s t h e Menory C o n t r o l l e r,
U28. This is a custom IC whose functions a r e :

Monitor t h e V I D RAM RD* and V I D RAM WR* l i n e s to d e t e c t a
g r a p h i c s memory access.

.
.

Monitor t h e Options r e g i s t e r and send t h e p r o p e r s i g n a l s
t o t h e X and Y r e g i s t e r s .
Sync t h e Graphics board to t h e Nbdel II u s i n g t h e WAIT*

line.
.

G e n e r a t e t h e signals t o r e a d and w r i t e t o t h e graphics
RAM.

The memory I C s have multiplexed address l i n e s , and must be
provided t h e proper t i m i n g s i g n a l s ( R A S * and C A S * ) and make
s u r e t h e addresses a r e at t h e RAMS at t h e p r o p e r t i m e . T h i s

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is accomplished by t a k i n g t h e c h a r a c t e r c l o c k ( C C L K ) from
t h e VDG and u s i n g a d i g i t a l d e l a y l i n e ( U 4 4 ) t o derive t h e
timing signals.

The VDG addresses a r e stable 16¢ as a f t e r t h e f a l l i n g edge
of CCLK. OCLK is inverted by U31 producing RAS*. RAS* is
delayed 11” ns and inverted to f o r m MUX. The MUX s i g n a l is
used to switch between t h e upper and lower RAM addresses.
The inverse o f MUX, MUX*, i s used b y t h e M a e r C o n t r o l l e r
a s a t i m i n g r e f e r e n c e . MUX i s t h e n delayed 15% n s t o f o r m
CAS*.

There a r e two ways to address graphics RAM:

.

Use t h e X and Y r e g i s t e r s t o r e a d and w r i t e d o t s .

.

Use t h e VDG to scan memory and d i s p l a y t h e contents on
t h e CRT.

C e r t a i n l y, t h e VDG has c o n t r o l most o f t h e time. The VDG
scanning time is used to r e f r e s h t h e dynamic memories.
The contention p r o b l e m is s o l v e d by u s i n g two s e t s of
addresses, t h e XREGDJJ-XREGD6 and YREGDfl‐YREGD7 s e t f o r t h e
r e g i s t e r s and t h e XROMDIJ-XROMD6 and YROMDfl‐YROMD7 s e t f o r
t h e VDG. N o r m a l l y, t h e VDG has c o n t r o l o f t h e RAM and these
addresses a r e incremented in a l i n e a r fashion (fl-79 o u t of
the XROM and 15‐239 o u t of t h e YROM) each CCLK c y c l e .
The Memory C o n t r o l l e r assumes t h e VDG has t h e RAM addresses
and keeps t h e XY/VDG* l i n e LOW. This s e l e c t s t h e VDG '
addresses i n t h e f o u r d u a l 4 : 1 m u l t i p l e x e r s U4IJ‐43. The
o t h e r multiplexer c o n t r o l l i n e is connected to MUX, so t h e
addresses switch between RAS* and CAS*.

Since t h e r e a r e two RAM banks, Y address l i n e D7 s p l i t s t h e
screen i n t o two halves at t h e 1 2 8 t h l i n e . The t o p h a l f of
screen RAM is in RAMS Ul‐U8 w h i l e t h e lower h a l f of t h e
screen is contained in RAMS U9‐U16. High speed NAND g a t e U34
is used to s e l e c t between t h e two banks of RAM.
The 4116 RAMS used d o n o t have a s e p a r a t e c h i p s e l e c t i n p u t
so a technique c a l l e d "gated CAS*" is used to t u r n on each
RAM bank. A M u l t i p l e x e r c o n s i s t i n g o f a 748m] NAND g a t e
( w h i c h d o e s n ' t use t h e MUX as t h e o t h e r multiplexers d o ) and
a p a i r of ORgates ( U 3 2 ) gate CAS* to t h e RAMS.

The RAMS p r o v i d e TRI‐STA'IE outputs and have on-chip l a t c h e s
f o r t h e o u t p u t s , which a r e c o n fi g u r e d i n p a r a l l e l . The
outputs g o t o a holding r e g i s t e r t o delay the graphic data
one CCLK p e r i o d f r o m r e a c h i n g t h e Video Board. This i s done

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b y o c t a l l a t c h U19. The c l e a r i n p u t o f t h e l a t c h t u r n s t h e
graphics on and o f f and t h e GRAPHIC/ALPHA* l i n e f r o m t h e
options r e g i s t e r is connected h e r e .

It is important to n o t e t h a t w h i l e t h e VDG is scanning t h e
graphics RAM, it is simultaneously seaming t h e r e g u l a r
screen RAM on t h e Video Board. This means t h a t t h e Graphics
Board mast b e a b l e t o d o a memory access i n one CCLK p e r i o d ,
which is 641 ms. The t i m e f o r a memory access is
approximately:
VDG address s t a b l e + ROM d e l a y + Mux d e l a y + RAM d e l a y =

Access time.

16¢ns
57¢ns

+ 1 2 fl n s

+3¢ns

+26¢ns

=

which is p l e n t y of time. This does n o t t a k e i n t o account t h e
time t h e 2-813 i s i n a WAIT s t a t e , which a t worst case i s 64¢
ns w i t h the M I T option o f f and 64.6 uS w i t h t h e WAIT ( p t i o n
on.

B y u s i n g t h e h o l d i n g r e g i s t e r , t h e graphics d a t a i s
a v a i l a b l e a t t h e same t i m e a s t h e video d a t a ( f r o m t h e
character generator U 2 5 ) . The separate data is EXCLUSIVE
OR-ed together by U213 and U24 to form t h e composite video
d a t a s e n t t o t h e Video Board t o b e S h i f t e d o u t t o t h e CRT.

Radio Ihaek®
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RADIO SHACK, A DIVISION OF TANDY CORPORATION
U.S.A.: FORT WORTH, TEXAS 76102
CANADA: BARBIE, ONTARIO L4M 4W5

TANDY CORPORATION
AUSTRALIA

BELGIUM

u. K.

280-316 VICTORIA ROAD
RYDALMERE, N.S.W. 2116

PARC INDUSTRIEL DE NANINNE

BILSTON ROAD WEDNESBURY
WEST MIDLANDS ws1o 7JN

8749326

5140 NANINNE

PRINTED IN U.S.A.



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