N1 Manual
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N1 Manual Dirk Heisswolf January 23, 2019 Revision History Date January 23, 2019 Change Pre-release 1 CONTENTS CONTENTS Contents 1 Glossary 5 2 Overview 7 3 Instruction Set 3.1 Return from a Call (;) . . . 3.2 Jump Instructions . . . . . 3.3 Call Instructions . . . . . . 3.4 Conditional Branches . . . . 3.5 Literals . . . . . . . . . . . 3.6 ALU Instructions . . . . . . 3.7 Stack Instructions . . . . . 3.8 Memory Access Instructions 3.9 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 9 9 9 9 9 11 14 14 4 ANS Forth Words 15 5 Stacks 5.1 Parameter Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Return Stack Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 17 2 LIST OF FIGURES LIST OF FIGURES List of Figures 3-1 Instruction encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Transition encoding of stack instructions . . . . . . . . . . . . . . . . . 5-1 Stack Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 11 16 LIST OF TABLES LIST OF TABLES List of Tables 3-1 3-2 3-2 3-2 3-3 4-1 ALU operations . . . . . . Common stack operations Common stack operations Common stack operations Control instructions . . . ALU operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 13 14 14 15 Glossary 1 Glossary ; End of a word definition in Forth. ALU Arithmetic Logic Unit. byte An 8-bit data entity. call A change of the program flow, where a return address is kept on the return stack. cell A data entity within a stack. conditional branch A change of the program flow without return option, only if a certain (non-zero) argument value is given. Forth Forth is a extensible stack-based programming language. intermediate stack The section of the stack, which serves as a buffer between the lower stack and the upper stack. See Section 5 “Stacks“. IST A bit field in the stack instruction which contols data movement on the intermediate parameter stack or return stack. The mnemonic stands for “Iintermediate Stack Transition”. jump A change of the program flow without return option. literal A fixed numerical value within the program code. lower stack The section of the stack which stored in RAM. See Section 5 “Stacks“. opcode Encoding of a machine instruction. Short for “operation code”. parameter stack A LIFO storage mainly for keeping call parameters and return values. 5 Glossary Glossary RAM Random access memory. return stack A LIFO storage mainly for maintaining return addresses of calls. stack A LIFO storage. upper stack The section of the stack, which contains the TOS. It supports reordering of its storage cell. See Section 5 “Stacks“. UST A bit field in the stack instruction which contols data movement between two neighboring cells in the upper parameter stack or return stack. The mnemonic stands for “Upper Stack Transition”. word The term word is used in two different contexts throughout this document. It refers to either a 16-bit data entity or a callable code sequence in Forth terminology. 6 2 2 OVERVIEW Overview The N1 is a snall stack machine, inspired by the J1 Forth CPU[1]. Just like its paragon, the N1 is a 16-bit processor wich implements basic Forth words directly in hardware. However the N1 parts from the J1’s simplistic design approach in in two ways: • The N1 support a larger code space of up to 32KB. Therefore it has its own instruction set (see Section 3 “Instruction Set“. • The N1 implements its parameter and return stacks as shallow register stacks, which overflow into RAM. The overall depth of each stack is determined by the available RAM. (see Section 5 “Stacks“. 7 3 3 INSTRUCTION SET Instruction Set The intent of the N1’s instruction set is to map most of the essential Forth words to single cycle instructions. Figure 3-1 illustrates the basic structure of the instructuion encoding. End of Word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 1 1 15 14 11 10 9 8 7 6 5 4 3 2 1 0 Jump (–) 14-bit absolute word address < 0x3FFF 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 0 1 15 14 11 10 9 8 7 6 5 4 3 2 1 12 11 10 9 8 7 6 5 4 3 2 Call ( – ) (R: – addr ) 1 15 14 13 12 11 15 14 13 10 9 14 13 12 11 10 9 14 13 12 11 10 9 14 13 12 11 10 9 12 14 13 12 11 10 9 14 13 11 10 12 11 10 8 8 8 9 14 13 12 7 6 5 11 10 7 6 5 3 2 1 4 3 2 4 7 6 5 7 6 4 Conditional branch ( flag – ) 1 0 Literals (–n) 8 7 6 9 8 7 6 3 2 1 3 2 1 4 3 2 1 ALU operation (x–x) 0 4 3 2 1 ALU operation (x–xx) 4 3 2 1 8 7 6 5 4 3 2 Stack operation 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 14 13 12 11 10 9 8 7 15 14 13 12 11 10 9 8 6 5 4 3 2 1 6 5 4 3 2 1 Word read (–x) 0 ; 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 14 13 12 11 10 9 8 7 15 14 13 12 11 10 9 8 6 5 15 14 13 12 11 10 9 8 3 2 1 7 6 5 4 3 2 1 Word write (x–) 0 Comtrol instruction (–) Instruction 7 6 5 4 3 Reserved Word write ( x addr – ) 0 8-bit word address < 0xFE ; 0 0 0 0 0 0 1 ; 0 0 0 0 0 0 1 4 Byte write ( x c-addr – ) 2 1 0 Reserved Figure 3-1: Instruction encoding 8 Memory Access Instructions 0 ; 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 ; 0 0 0 0 0 1 1 Word read ( addr – x ) 0 8-bit word address < 0xFE 7 Byte read ( c-addr – x ) 0 ; 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 ; 0 0 0 0 0 1 1 Stack Instructions 0 ; 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 15 ALU operation (xx–xx) 0 Stack transition pattern 9 ALU Instructions 0 0 0 0 0 0 5 ALU operation (xx–x) 0 Operand 6= 0 5 Literals 0 0 0 0 0 0 5 Conditional branch ( flag addr – ) 0 Operand 6= 0 Operator ; 0 0 0 0 1 15 4 Operator ; 0 0 0 1 0 15 8 Operator ; 0 0 0 1 0 15 5 Operator ; 0 0 0 1 1 15 6 12-bit signed integer ; 0 0 0 1 1 15 7 13-bit relative word address < 0x1FFF ; 0 0 1 15 8 Change of Flow Instructions 0 ; 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ; 0 1 Call ( addr0 – ) (R: – addr1 ) 0 14-bit absolute word address < 0x3FFF 13 Jump ( addr – ) Control Instructions 3.1 3.1 Return from a Call (;) 3 INSTRUCTION SET Return from a Call (;) Rather than providing a dedicated instruction to end the execution of word in Forth and to return the program flow to its caller, the N1 allows to perform this operation in parallel to the execution of any of its instructions. Each opcode contains a bit (bit 15) to indicate, that the current instruction in the last operation in the current word. If this bit is set, the program flow will resume at the calling word as soon as the operationis performed. As shown in Figure 3-1, bit 15 is also used to distinguish jump and call. Considering that the last call in a word definition can be optimized to a jump to the first instruction of the called word, bit 15 can ber regarded as termination bit for these instructions as well. For a Forth compiler, this means that the semi-colon (;) always translates to setting bit 15 of the last instruction. 3.2 Jump Instructions Jump instructions transfer the program flow to any word location within the supported 64KB program space. Jump instructions consume an absolute destination address, which can be either placed on the top of the Parameter stack or encoded into the opcode of the instruction (only for destination addresses < 0x3FFF). 3.3 Call Instructions Call instructions temporarily transfer the program flow to any word location within the supported 64KB program space, while pushing a return address onto the return stack. Call instructions consume an absolute destination address, which can be either placed on the top of the Parameter stack or encoded into the opcode of the instruction (only for destination addresses < 0x3FFF). 3.4 Conditional Branches Conditional branches invoke a change of program flow depending on an argument on the parameter stack. The branch destination cab be either an absolute address placed on the the top of the Parameter stack or relative relative address, encoded into the opcode of the instruction (only for destination addresses < 0x1FFF). 3.5 Literals Signed integer literals of 12-bit length can be pushed onto the parameter stack within a single instruction. For larger integers a supplemental TBD call is required. 3.6 ALU Instructions ALU instructions perform an operation on two cell values, resulting in a new double cell value. The reult can be either placed entirely onto the parameter stack, or truncated, discarding the most significant cell. The first operand is always taken from the Parameter stack. The second operand can be either taken from the Parameter stack or encoded into the opcode of the instruction. In the latter case, the interpretation of the embedded 5-bit value depends on the operation. It is either regarded as an unsigned (uimm), a sign extended (simm), or an offsetted (oimm) integer value: 9 3.6 ALU Instructions 3 INSTRUCTION SET uimm = opcode[4:0] ( opcode[4:0], if opcode[4:0] < 16 simm = opcode[4:0] − 32, if opcode[4:0] ≥ 16 oimm = opcode[4:0] − 16 Table 3-1 lists the supported ALU operations. Table 3-1: ALU operations Encoding 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11100 11100 11100 Operation ( x1 – d ) ( x1 x2 – d ) Sum x1 + uimm x1 + x2 Sum oimm + x1 x2 + x1 Difference x1 − uimm x1 − x2 Difference oimm − x1 x2 − x1 Unsigned lower-than comparison x1 < uimm? x1 < x2? Signed greater-than comparison oimm < x1? x2 < x1? Unsigned greater-than comparison x1 > uimm? x1 > x2? Signed lower-than comparison oimm > x1? x2 > x1? Equals comparison x1 = uimm? x1 = x2? Equals comparison oimm = x1? x2 = x1? Not-equals comparison x1 6= uimm? x1 6= x2? Not-equals comparison oimm 6= x1? x2 6= x1? Unsigned product x1 ∗ uimm x1 ∗ x2 Unsigned product x1 ∗ simm x1 ∗ x2 Signed product x1 ∗ uimm x1 ∗ x2 Signed product x1 ∗ simm x1 ∗ x2 Logic AND x1 ∧ simm x1 ∧ x2 Logic OR x1 ∨ uimm x1 ∨ x2 Logic XOR x1 ⊕ simm x1 ⊕ x2 Reserved Logic right shift x1 uimm x2 x1 Logic left shift x1 uimm x2 x1 Arithmetic right shift x1 uimm x2 x1 Reserved Set upper bits of an immediate value simm, x1[11:0] simm, x2[11:0] Reserved Reserved Reserved Current interrupt vector vector address Current error code throw code Parameter stack status IPS:UPS Return stack status IPS:UPS 10 3.7 Stack Instructions 3.7 3 INSTRUCTION SET Stack Instructions The N1’s stack instruction aims at efficiently implementing the essential stack operations in Forth only using the data pathes which needed for the stack’s push and pull operations. The opcode of the stack instruction contains a 10-bit wide field to specify a transition pattern of the upper cells of the parameter stack and the return stack. The structure transition patter is shown in Figure 3-2. IST 0: 1: 15 14 13 12 11 UST 00: 01: 10: 11: or 10 ; 0 0 0 0 1 9 IST 8 7 6 UST 5 UST 4 3 UST 2 1 UST 0 IST Stack Instruction TOS Parameter stack TOS Return stack Figure 3-2: Transition encoding of stack instructions The stack instruction contains four UST fields which control the data transfer within the upper four cells of the parameter stack and the top of the return stack. Each UST field determines the direction of data transfer between two neighboring stack cells. Four options are selectable: • No data transfer • Data transfer upwards (or towards the return stack) • Data transfer downwards (or towards the parameter stack) • Data exchange between two stack cells It is possible to put the UST fields into a combination which would trigger a data transfer of two source cells to a single desination cell. In these cases, the resulting data in the desination cell is undefined. The two remaining IST fields in the stack instruction control the data movement of the lower stacks. Two options are selectable: • No data transfer • Data shift throughout the entire intermediate stack. The direction is determined by the data movement of the lowest cell of the upper stack. Table 3-2 shows how stack operations in Forth are mapped N1 instructions. 11 3.7 Stack Instructions 3 INSTRUCTION SET Table 3-2: Common stack operations Word Description DROP (x–) TOS TOS 0x06A8 DUP (x–xx) TOS TOS 0x0750 SWAP ( x1 x2 – x2 x1 ) TOS TOS 0x0418 OVER ( x1 x2 – x1 x2 x1 ) TOS TOS 0x0758 NIP ( x1 x2 – x2 ) TOS TOS 0x06A0 TOS TOS TUCK ( x1 x2 – x2 x1 x2 ) TOS TOS 0x0750 0x0460 TOS TOS TOS TOS TOS TOS TOS TOS 0x0418 0x0460 TOS TOS 0x0001 TOS TOS TOS TOS 0x0007 0x0006 TOS TOS 0x06AB TOS TOS 0x0754 TOS TOS 0x0755 TOS TOS TOS TOS 0x06A8 0x06A8 TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS ROT -ROT ( x1 x2 x3 – x3 x1 x2 ) ( R: x – ) RDUP ( R: x – x x ) R@ R> 2DROP 2DUP 2SWAP 2OVER 2NIP Opcode ( x1 x2 x3 – x2 x3 x1 ) RDROP >R Transitions (x–) ( R: – x ) (–x) ( R: x – x ) (–x) ( R: x – ) ( x1 x2 – ) ( x1 x2 – x1 x2 x1 x2 ) ( x1 x2 x3 x4 – x4 x3 x1 x2 ) ( x1 x2 x3 x4 – x1 x2 x3 x4 x1 x2 ) ( x1 x2 x3 x4 – x3 x4 ) 0x0460 0x0418 0x0758 0x0758 0x0460 0x0598 0x0460 0x0780 0x0460 0x0798 0x0460 0x06A0 0x06A0 ...continued 12 3.7 Stack Instructions 3 INSTRUCTION SET Table 3-2: Common stack operations Word 2TUCK 2ROT -2ROT 2RDROP 2RDUP 2>R Description Transitions Opcode TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS TOS ( x1 x2 x3 x4 – x3 x4 x1 x2 x3 x4 ) ( x1 x2 x3 x4 x5 x6 – x3 x4 x5 x6 x1 x2 ) ( x1 x2 x3 x4 x5 x6 – x5 x6 x1 x2 x3 x4 ) ( R: x1 x2 – ) ( R: x1 x2 – x1 x1 x1 x2 ) ( x1 x2 – ) ( R: – x1 x2 ) 0x046B 0x0487 0x0418 0x0460 0x0755 0x0755 0x06AB 0x0580 0x06AB 0x0598 0x0755 0x0598 0x0755 0x0598 0x0460 0x0460 0x0598 0x06AB 0x0598 0x06AB 0x0598 0x0755 0x0018 0x0755 0x0001 0x0001 0x0755 0x0757 0x06AB 0x06AB 0x0000 0x0000 ...continued 13 3.9 Control Instructions 3 INSTRUCTION SET Table 3-2: Common stack operations Word Description ( – x1 x2 ) ( R: x1 x2 – x1 x2 ) TOS TOS 2R@ TOS TOS ( – x1 x2 ) ( R: x1 x2 – ) TOS TOS TOS TOS 2R> 3.8 Transitions Opcode Memory Access Instructions Memory access instruction perform read or write acesses to the system’s 64-Kbyte address space. Data can be accessed in word or byte entities. Misaligned word accesses are not supported. Word accesses to a 510-Kbyte subset of the address space can be done through an immediate addressing. This will offer faster access to frequently used system variables. 3.9 Control Instructions The N1 implements of set of instrictions to controls some of its internal components. None of these instructions consume input arguments from the parameter stack, nor do they produce a return value. The encoding of these instructions is shown in Table 3-3. Multiple control instructions can be combined to one. Table 3-3: Control instructions Encoding xxxxxx11 xxxxxx10 xxxxx1xx xxxx1xxx Instruction Enable interrupts Disable interrupts Reset parameter stack Reset return stack 14 0x0000 0x0000 0x0000 0x0000 4 4 ANS FORTH WORDS ANS Forth Words Table 4-1 provides a list of standard ANS Forth words (see [?]) which directly map to hardware instructions of the N1 processor. Table 4-1: ALU operations Word ! * + - Stack ( x a-addr – ) ( n1|u1 n2|u2 – n3|u3) ( n1|u1 n2|u2 – n3|u3) ( n1|u1 n2|u2 – n3|u3) Description Store cell Multiply two cells Add two cells Subtract a cell from another. 15 Opcode 0000 0000 0000 0000 5 5 STACKS Stacks The N1 operates with two stacks: the parameter stack to perform data transactions and the return stack to manage the program flow. As illustrated in Figure 5-1, each of these stacks consists of three hardware components: the upper stack, the intermediate stack, and the lower stack. Lower Stack Intermediate Stack Upper Stack Parameter Stack Return Stack TOS TOS RAM Controller RAM Controller RAM RAM Figure 5-1: Stack Architecture 5.1 Parameter Stack The upper stack of the parameter stack contains is four cells deep and contains the most recent data entries. It’s purpose is to perform stack and ALU operations (see Section 3.7 “Stack Instructions“ and Section 3.6 “ALU Instructions“). When the capacity of the upper stack is exceeded, older data entries are transferred to the intermediate stack. The intermediate stack serves as a buffer between the upper stack and the lower stack which resides in RAM. The purpose of the intermediate stack is to minimize RAM traffic to and from the lower stack. Push operation to the intermediate stack are only propagated to the lower stack, when the buffer capacity is exceeded. Pull operations are onle propagated, when the intermediate stack is empty. Stack fluctuations within the buffer capacity are not visible to the lower stack. The lower stack is a region of the RAM, which is managed by the memory controller of the intermediate stack. 16 5.2 5.2 Return Stack Stack 5 STACKS Return Stack Stack The upper stack of the parameter stack has the capacity of one cell. The intermediate stack and lower stack are similar to the ones of the parameter stack. 17 REFERENCES REFERENCES References [1] Menlo Park James Bowman, Willow Garage. J1: a small forth cpu core for fpgas. http://www.excamera.com/files/j1.pdf, 2010. 18
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