QM_XC7A35T_SDRAM_User_Manual(DaughterBoard) QM DB User Manual

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QM_XC7A35T SDRAM DB
USER MANUAL

Preface
The QMTech® XC7A35T SDRAM Development Kit uses Xilinx Artix®-7 devices to demonstrate the highest
performance-per-watt fabric, transceiver line rates, DSP processing, and AMS integration in a costoptimized FPGA. Featuring the MicroBlaze™ soft processor and 1,066Mb/s DDR3 support, the family is the
best value for a variety of cost and power-sensitive applications including software-defined radio, machine
vision cameras, and low-end wireless backhaul.

QM_XC7A35T_SDRAM Daughter Board(User Manual)

Table of Contents
1.

QM_XC7A35T_SDRAM DB INTRODUCTION........................................ 3
1.1
1.2

KIT OVERVIEW ............................................................................. 3
DAUGHTER BOARD TOP VIEW ......................................................... 3

EXPERIMENT (1): USB TO SERIAL PORT .............................................. 4

EXPERIMENT (2): VGA DISPLAY .......................................................... 7

EXPERIMENT (3): CY7C68013A USB 2.0 SLAVE FIFO ......................... 10

REFERENCE ...................................................................................... 17

REVISION ......................................................................................... 18

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QM_XC7A35T_SDRAM DB Introduction

1.1

Kit Overview
QM_XC7A35T_SDRAM Daughter Board provides several user interfaces to meet different customer

needs. Below section lists the detailed info of these user interfaces:

1.2



USB to UART Serial Port, by using Silicon Labs’ CP2102-GMR chip.



24bit(RGB888) VGA display interface, by using Analog Device’s ADV7123-KSTZ140 chip;



High speed USB 2.0 peripheral controller, by using Cypress’ CY7C68013A-56LTXC chip;



Reserved CMOS/CCD camera interface, by using 18pin female header;



Extended 40 pin male header to provide 34 user IOs, which could be used to connect customized
modules, e.g. ADC/DAC module, Ethernet module, Audio module;

Daughter Board Top View
Below figure shows the daughter board of QM_XC7A35T_SDRAM development kit. The daughter board’s
dimension is 81.28mm x 108.71mm. All the functional chips’ power supply is injected from the 64P female
connector, detailed connection refer to the hardware schematic.
CY7C68013，USB
2.0 HS

ADV7123，24bit
VGA

CP2102, USB to
Serial Port

CMOS Camera
Interface

40Pin Header
for User IOs

Figure 1-1. Top View of QM_XC7A35T_SDRAM Daughter Board

QM_XC7A35T_SDRAM Daughter Board

User Manual-V01

Experiment (1): USB to Serial Port
The CP2102-GMR is a USB 2.0 to serial port bridge chip designed by Silicon Labs. The CP2102-GMR
includes a USB 2.0 full-speed function controller, USB transceiver, oscillator, UART and eliminates the
need for other external USB components are required for development. Below figure shows the hardware
design of CP2102-GMR on the QM_XC7A35T_SDRAM daughter board.
R34

22
21
20
19
18
NC11
NC10
NC9
NC8
NC7

U5
6

4.7K

VDD

C35

RST

100nF
3
29

GND
GND_TP

CTS
RTS
TXD
RXD

GND
DNP

8
7
6

G4
Vcc
G3
DD+
G2
ID
GND
G1

C36
4.7uF
1
2
3
4
5

8
7
5
4

VBUS
REGIN
DD+

DTR
SUSPEND
SUSPEND
RI
DCD
DSR

NC1
NC2
NC3
NC4
NC5
NC6

J4
9

GND
USB_5V_IN

MINI_USB

10
13
14
15
16
17

23
24
26
25

BANK35_D4
BANK35_C4

28
12
11
2
1
27

CP2102-GM

GND

Figure 2-1. CP2102 Hardware Design
Before start to test the CP2102-GMR’s USB to UART serial communication function, make sure all the
hardware connections of the development kit are correctly connected. Xilinx USB platform cable’s VREF,
GND, TDI, TMS, TCK, TDO pins shall be connected to QM_XC7A35T_SDRAM core board’s JTAG
interface. Then power on the development kit with 5V DC power source. Xilinx USB platform cable’s
indicator LED’s color will turn from brown into green. At the same time, the Mini-USB cable shall also be
plugged in the board, below figure shows an example hardware setup:

JTAG Cable

5V DC Source
Mini-USB Cable

QM_XC7A35T_SDRAM Daughter Board

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All the test examples are developed in the Xilinx Vivado 2016.4 environment. Open the CP2102 test
project located in this release folder: /Software/Test06_project_usb_uart. Below figure shows the example
project of uart_top:

Figure 2-2. CP2102 UART Communication Test Example
In this example project, the default communication parameters are: 9600bps, 8 data bit, No Parity Check,
1 stop bit. If users want to test other communication parameters, change the source code accordingly.

QM_XC7A35T_SDRAM Daughter Board

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After the CP2102 communication test project correctly synthesized, implemented and generated bit file,
users could use Xilinx program tool to program the generated bit file into FPGA. Below image shows the
FPGA program status with program tool.

Figure 2-3. Program the FPGA
The CP2102 example test project’s main functionality is performing an UART loopback communication.
The FPGA program will send the received UART data back to the PC. Below figure shows user
employees some PC based UART test tool to send data to FPGA: http://www.cmsoft.cn QQ:10865600.
After a short while the PC UART test tool will receive the same data stream from FPGA, which means the
CP2102 loopback test program is running correctly.

Figure 2-4. UART Loopback Test

QM_XC7A35T_SDRAM Daughter Board

User Manual-V01

Experiment (2): VGA Display
The ADV7123 is a triple high speed, digital-to-analog converter on a single monolithic chip. It consists of
three high speed, 10-bit, video DACs with complementary outputs, a standard TTL input interface, and a
high impedance, analog output current source. The QM_XC7A35T_SDRAM daughter board provides
24bit(RGB888) VGA display function by using ADV7123-KSTZ140. Below figure shows the hardware
design of the ADV7123 chip, the lowest two bits of each color channel are directly connected to GND:
ANA_3V3

3V3

ANA_3V3

BANK14_N6
BANK14_R5
BANK14_M6
BANK14_R6
BANK14_T5
BANK14_R7
BANK14_T7
BANK14_R8

14
15
16
17
18
19
20
21
22
23

BANK14_T8

BANK14_P6

12
11

R40

GND

ANA_3V3

4.7K
4.7K

VAA1
VAA2
VAA3

R0
R1
R2
R3
R4
R5
R6
R7
R8
R9

13
29
30

G0
G1
G2
G3
G4
G5
G6
G7
G8
G9

IOR
IOR
IOG
IOG
IOB
IOB

B0
B1
B2
B3
B4
B5
B6
B7
B8
B9

VREF

CLOCK

RSET

34
33
32
31
28
27

GND

BANK35_B7
BANK35_A7

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

10
15

BANK34_R1
BANK34_R2
BANK34_T2
BANK34_R3
BANK34_T3
BANK34_T4
BANK34_P5
BANK34_L5

1
2
3
4
5
6
7
8
9
10

COMP

BANK34_M1
BANK34_M2
BANK34_P1
BANK34_N1
BANK34_P3
BANK34_P4
BANK34_N4
BANK34_M5

39
40
41
42
43
44
45
46
47
48

GND

R62

R37
R38
R39

100nF

R35

75R
75R
75R

C37

CONN_VGA

ANA_3V3

SY NC
BLANK

GND1
GND2

C38

100nF

R36

560R

C39
100nF
GND

GND

26
25

PSAVE
AD7123
GND

Figure 3-1. ADV7123 Hardware Design
Before start to test the VGA display function, make sure all the hardware connections of the development
kit are correctly connected. Xilinx USB platform cable’s VREF, GND, TDI, TMS, TCK, TDO pins shall be
connected to QM_XC7A35T_SDRAM core board’s JTAG interface. Then power on the development kit
with 5V DC power source. Xilinx USB platform cable’s indicator LED’s color will turn from brown into
green. At the same time, the VGA cable shall also be plugged in the board, below figure shows an
example hardware setup:

JTAG Cable
VGA Cable
5V DC Source

QM_XC7A35T_SDRAM Daughter Board

User Manual-V01

All the test examples are developed in the Xilinx Vivado 2016.4 environment. Open the VGA test project
located in this release folder: /Software/Test07_project_vga_adv7123. Below figure shows the example
project of VGA_test:

Figure 3-2. VGA Display Function Test
In this example project, the default VGA output resolution parameter is 1280x1024@60Hz. If users want
to test other display parameters, change the source code accordingly.

Figure 3-3. VGA Display Parameters
After the VGA display test project correctly synthesized, implemented and generated bit file, users could
use Xilinx program tool to program the generated bit file into FPGA. Below image shows the FPGA
program status with program tool.

QM_XC7A35T_SDRAM Daughter Board

User Manual-V01

Figure 3-4. Program FPGA
After the FPGA correctly loaded the VGA_Test bit file, the VGA monitor will display the color bar output
from development kit’s VGA port. Below image shows the example color bar pattern.

Figure 3-5. VGA Display Test

QM_XC7A35T_SDRAM Daughter Board

User Manual-V01

Experiment (3): CY7C68013A USB 2.0 Slave FIFO
Cypress’s EZ-USB® FX2LP CY7C68013A is a low-power version of the EZ-USB FX2(CY7C68013),
which is a highly integrated, low-power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver,
serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in
a single chip, Cypress has created a cost-effective solution that provides superior time-to-market
advantages with low power to enable bus-powered applications. The QM_XC7A35T_SDRAM daughter
board provides slave FIFO interface by using CY7C68013A. Below figure shows the hardware design of
the CY7C68013A chip:
3V3

3V3
C40 C41 C42
R1
4.7K

GND

9
C3
22PF

C16
22PF
2

7
6

3V3

27
11
17
32
43
55

XTALIN

CTL0/FLAGA
CTL1/FLAGB
CTL2/FLAGC
PA7/FLAGD/SLCS#
RDY 1/SLWR
RDY 0/SLRD
PA2/SLOE
PA6/PKTEND
PA4/FIFOADR0
PA5/FIFOADR1

XTALOUT

J5
G4
Vcc
DD+
G2
ID
GND
G1

1
2
3
4
5

9
8

DMINUS
DPLUS

PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
PB4/FD4
PB5/FD5
PB6/FD6
PB7/FD7
PD0/FD8
PD1/FD9
PD2/FD10
PD3/FD11
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15

MINI_USB
GND

GND
GND

VCC
7

GND

3V3

8
4

WAKEUP
C13
100NF

AT24C128

GND
3V3 3V3

GND
3V3

R66
4.7K

SCL
SDA

44
14

WAKEUP
RESERVED

Thermal
GND
GND
GND
GND
GND
GND

SCL
SDA

15
16

6
5

57
12
26
28
53
56
41

A0
A1
NC

GND
SCL
SDA

AGND
AGND

1
2
3

MN1

6
10

GND
R5
4.7K

R65
4.7K

CLKOUT/PE1
IFCLK/PE0

Y1
24.000 MHz

RESET#

GND

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
AVCC

3
7

100nF
100nF
100nF

C2
0.1uF

PA3/WU2
PA1/INT1#
PA0/INT0#

54
13

BANK14_N14
BANK14_R10

29
30
31

BANK14_K12
BANK14_P13
BANK14_N12

40
2
1
35
39
37
38

BANK14_P14
BANK14_M16
BANK14_N13
BANK14_R12
BANK14_T13
BANK14_T12
BANK14_R13

18
19
20
21
22
23
24
25
45
46
47
48
49
50
51
52

BANK14_T9
BANK14_R11
BANK14_T10
BANK14_P9
BANK14_N9
BANK14_P11
BANK14_P10
BANK14_K13
BANK14_M12
BANK14_T15
BANK14_T14
BANK14_R16
BANK14_R15
BANK14_P16
BANK14_P15
BANK14_N16

36
34
33

R70

4.7K

PA1
PA0

CY 7C68013A_56LTXC
GND

3V3 3V3

R67
4.7K

R69
4.7K

R68
4.7K
GND

SCL
SDA

WAKEUP

PA1
PA0

Figure 4-1. CY7C68013A-56LTXC Hardware Design
Before start to test the USB slave FIFO function, make sure all the hardware connections of the
development kit are correctly connected. Xilinx USB platform cable’s VREF, GND, TDI, TMS, TCK, TDO
pins shall be connected to QM_XC7A35T_SDRAM core board’s JTAG interface. Then power on the
development kit with 5V DC power source. Xilinx USB platform cable’s indicator LED’s color will turn from
brown into green. At the same time, the Mini-USB cable shall also be plugged in the board, below figure
shows an example hardware setup:

QM_XC7A35T_SDRAM Daughter Board

User Manual-V01

JTAG Cable

5V DC Source

Mini-USB Cable

Figure 4-2. Hardware Connections
Users also need to install the PC based USB driver and test software provided by Cypress. These driver
and test suite could be retrieved by installing the CySuiteUSB_3_4_7_B204.exe. KeilC51V9.00 is also
suggested to be installed to compile the CY7C68013A firmware. All of those software packages could be
found in the Release folder: /Software/Test04-CY7C68013_USB_2.0_HS.

Figure 4-3. USB 2.0 Test Software Package
The windows device manager will inform users to install USB driver, after the Mini-USB cable connected
to the PC’s USB host connector. The CY7C68013A USB driver could be found in below folder: cy3684kit_
RC8-> Drivers->Win7->x86. The cy3684kit_RC8.iso could be downloaded from Cypress official site.

QM_XC7A35T_SDRAM Daughter Board

User Manual-V01

Figure 4-4. CY7C68013 USB Driver
After the CY7C68013 USB driver is correctly installed, the device manager will display the enumerated
USB device: ”Cypress FX2LP No EEPROM Device”.

Figure 4-5. Cypress FX2LP No EEPROM Device
Use Vivado 2016.4 to open the Slave FIFO test project located in Release folder: /Software/Test04CY7C68013_USB_ 2.0_HS/Test04-project_CY7C68013. Below figure shows the example project of
USB_FPGA:

QM_XC7A35T_SDRAM Daughter Board

User Manual-V01

After the Slave FIFO test project correctly synthesized, implemented and generated bit file, users could
use Xilinx program tool to program the generated bit file into FPGA. Below image shows the FPGA
program status with program tool.

Figure 4-6. FPGA Program
Then, users need to download Slave FIFO firmware into CY7C68013A’s internal RAM or external
EEPROM. First step: Windows Start->Cypress->Cypress Suite USB 3.4.7->CyConsole:

Figure 4-7. Open CyConsole Software

QM_XC7A35T_SDRAM Daughter Board

User Manual-V01

Click menu Options, select EZ-USB Interface:

Figure 4-8. Choose EZ-USB Interface
The EZ-USB Interface displays the Device information: Cypress FX2LP No EEPROM Device:

QM_XC7A35T_SDRAM Daughter Board

User Manual-V01

Click Download button and select Slave.hex. The Slave.hex is located in Release folder: \software\
Test04-CY7C68013_USB_FIRMWARE\USB_SLAVE_FIFO\USB_FIRMWARE\slave_sync。Notice: if
users want to download firmware into external EEPROM, click Lg EEPROM and select Slave.iic.

Figure 4-9. Program Slave.hex
After the Slave FIFO firmware successfully downloaded, the EZ-USB Interface will display new
enumerated device: QinMou-X16。And then users could send 512 bytes of hex value 0x55 into USB
Endpoint 2 OUT by clicking Bulk Trans button:

Figure 4-10. New QinMou-X16 Device and Send Test Datas

QM_XC7A35T_SDRAM Daughter Board

User Manual-V01

Then, change the Pipe selection into Endpoint 6 IN. After click the Bulk Trans button, the log window
will display all the received data from USB Endpoint 6 IN. From below image, users could see all the 512
bytes of hex value 0x55 are correctly read back from Slave FIFO.

Figure 4-11. Receive Test Data

QM_XC7A35T_SDRAM Daughter Board

User Manual-V01

Reference
[1]
[2]
[3]
[4]
[5]
[6]

ug380-Configuration.pdf
ug385-Package.pdf
ug394-Power Managment.pdf
M25P80.pdf
LPC-Link-II_Rev_C.pdf
Xc7a35t-sdram-v02.pdf

QM_XC7A35T_SDRAM Daughter Board

User Manual-V01

Revision
Doc. Rev.

Date

Comments

0.1

11/07/2017

Initial Version.

1.0

11/18/2017

V1.0 Formal Release.

QM_XC7A35T_SDRAM Daughter Board

User Manual-V01

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.5
Linearized                      : No
Page Count                      : 18
Language                        : zh-CN
Tagged PDF                      : Yes
Title                           : QM_XC7A35T_SDRAM_User_Manual(DaughterBoard)
Author                          : QMTECH
Subject                         : 8-bit Atmel Microcontrollers
Creator                         : Microsoft® Word 2013
Create Date                     : 2017:11:19 11:05:55+08:00
Modify Date                     : 2017:11:19 11:05:55+08:00
Producer                        : Microsoft® Word 2013

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QM_XC7A35T_SDRAM_User_Manual(DaughterBoard) QM DB User Manual

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