STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx Advanced Arm® Based 32 Bit MCUs Reference Manual STM32L4
STM32L4%20Reference%20manual
reference-manual-RM0394
reference-manual-RM0394
User Manual:
Open the PDF directly: View PDF
Page Count: 1600 [warning: Documents this large are best viewed by clicking the View PDF Link!]
- 1 Documentation conventions
- 2 System and memory overview
- 3 Embedded Flash memory (FLASH)
- 3.1 Introduction
- 3.2 FLASH main features
- 3.3 FLASH functional description
- 3.4 FLASH option bytes
- 3.5 FLASH memory protection
- 3.6 FLASH interrupts
- 3.7 FLASH registers
- 3.7.1 Flash access control register (FLASH_ACR)
- 3.7.2 Flash Power-down key register (FLASH_PDKEYR)
- 3.7.3 Flash key register (FLASH_KEYR)
- 3.7.4 Flash option key register (FLASH_OPTKEYR)
- 3.7.5 Flash status register (FLASH_SR)
- 3.7.6 Flash control register (FLASH_CR)
- 3.7.7 Flash ECC register (FLASH_ECCR)
- 3.7.8 Flash option register (FLASH_OPTR)
- 3.7.9 Flash PCROP Start address register (FLASH_PCROP1SR)
- 3.7.10 Flash PCROP End address register (FLASH_PCROP1ER)
- 3.7.11 Flash WRP area A address register (FLASH_WRP1AR)
- 3.7.12 Flash WRP area B address register (FLASH_WRP1BR)
- 3.7.13 FLASH register map
- 4 Firewall (FW)
- 4.1 Introduction
- 4.2 Firewall main features
- 4.3 Firewall functional description
- 4.4 Firewall registers
- 4.4.1 Code segment start address (FW_CSSA)
- 4.4.2 Code segment length (FW_CSL)
- 4.4.3 Non-volatile data segment start address (FW_NVDSSA)
- 4.4.4 Non-volatile data segment length (FW_NVDSL)
- 4.4.5 Volatile data segment start address (FW_VDSSA)
- 4.4.6 Volatile data segment length (FW_VDSL)
- 4.4.7 Configuration register (FW_CR)
- 4.4.8 Firewall register map
- 5 Power control (PWR)
- 5.1 Power supplies
- 5.2 Power supply supervisor
- 5.3 Low-power modes
- Figure 11. Low-power modes possible transitions
- Table 20. Low-power mode summary
- Table 21. Functionalities depending on the working mode
- 5.3.1 Run mode
- 5.3.2 Low-power run mode (LP run)
- 5.3.3 Low power modes
- 5.3.4 Sleep mode
- 5.3.5 Low-power sleep mode (LP sleep)
- 5.3.6 Stop 0 mode
- 5.3.7 Stop 1 mode
- 5.3.8 Stop 2 mode
- 5.3.9 Standby mode
- 5.3.10 Shutdown mode
- 5.3.11 Auto-wakeup from low-power mode
- 5.4 PWR registers
- 5.4.1 Power control register 1 (PWR_CR1)
- 5.4.2 Power control register 2 (PWR_CR2)
- 5.4.3 Power control register 3 (PWR_CR3)
- 5.4.4 Power control register 4 (PWR_CR4)
- 5.4.5 Power status register 1 (PWR_SR1)
- 5.4.6 Power status register 2 (PWR_SR2)
- 5.4.7 Power status clear register (PWR_SCR)
- 5.4.8 Power Port A pull-up control register (PWR_PUCRA)
- 5.4.9 Power Port A pull-down control register (PWR_PDCRA)
- 5.4.10 Power Port B pull-up control register (PWR_PUCRB)
- 5.4.11 Power Port B pull-down control register (PWR_PDCRB)
- 5.4.12 Power Port C pull-up control register (PWR_PUCRC)
- 5.4.13 Power Port C pull-down control register (PWR_PDCRC)
- 5.4.14 Power Port D pull-up control register (PWR_PUCRD)
- 5.4.15 Power Port D pull-down control register (PWR_PDCRD)
- 5.4.16 Power Port E pull-up control register (PWR_PUCRE)
- 5.4.17 Power Port E pull-down control register (PWR_PDCRE)
- 5.4.18 Power Port H pull-up control register (PWR_PUCRH)
- 5.4.19 Power Port H pull-down control register (PWR_PDCRH)
- 5.4.20 PWR register map and reset value table
- 6 Reset and clock control (RCC)
- 6.1 Reset
- 6.2 Clocks
- Figure 13. Clock tree
- 6.2.1 HSE clock
- 6.2.2 HSI16 clock
- 6.2.3 MSI clock
- 6.2.4 HSI48 clock
- 6.2.5 PLL
- 6.2.6 LSE clock
- 6.2.7 LSI clock
- 6.2.8 System clock (SYSCLK) selection
- 6.2.9 Clock source frequency versus voltage scaling
- 6.2.10 Clock security system (CSS)
- 6.2.11 Clock security system on LSE
- 6.2.12 ADC clock
- 6.2.13 RTC clock
- 6.2.14 Timer clock
- 6.2.15 Watchdog clock
- 6.2.16 Clock-out capability
- 6.2.17 Internal/external clock measurement with TIM15/TIM16
- 6.2.18 Peripheral clock enable register (RCC_AHBxENR, RCC_APBxENRy)
- 6.3 Low-power modes
- 6.4 RCC registers
- 6.4.1 Clock control register (RCC_CR)
- 6.4.2 Internal clock sources calibration register (RCC_ICSCR)
- 6.4.3 Clock configuration register (RCC_CFGR)
- 6.4.4 PLL configuration register (RCC_PLLCFGR)
- 6.4.5 PLLSAI1 configuration register (RCC_PLLSAI1CFGR)
- 6.4.6 Clock interrupt enable register (RCC_CIER)
- 6.4.7 Clock interrupt flag register (RCC_CIFR)
- 6.4.8 Clock interrupt clear register (RCC_CICR)
- 6.4.9 AHB1 peripheral reset register (RCC_AHB1RSTR)
- 6.4.10 AHB2 peripheral reset register (RCC_AHB2RSTR)
- 6.4.11 AHB3 peripheral reset register (RCC_AHB3RSTR)
- 6.4.12 APB1 peripheral reset register 1 (RCC_APB1RSTR1)
- 6.4.13 APB1 peripheral reset register 2 (RCC_APB1RSTR2)
- 6.4.14 APB2 peripheral reset register (RCC_APB2RSTR)
- 6.4.15 AHB1 peripheral clock enable register (RCC_AHB1ENR)
- 6.4.16 AHB2 peripheral clock enable register (RCC_AHB2ENR)
- 6.4.17 AHB3 peripheral clock enable register(RCC_AHB3ENR)
- 6.4.18 APB1 peripheral clock enable register 1 (RCC_APB1ENR1)
- 6.4.19 APB1 peripheral clock enable register 2 (RCC_APB1ENR2)
- 6.4.20 APB2 peripheral clock enable register (RCC_APB2ENR)
- 6.4.21 AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR)
- 6.4.22 AHB2 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB2SMENR)
- 6.4.23 AHB3 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB3SMENR)
- 6.4.24 APB1 peripheral clocks enable in Sleep and Stop modes register 1 (RCC_APB1SMENR1)
- 6.4.25 APB1 peripheral clocks enable in Sleep and Stop modes register 2 (RCC_APB1SMENR2)
- 6.4.26 APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR)
- 6.4.27 Peripherals independent clock configuration register (RCC_CCIPR)
- 6.4.28 Backup domain control register (RCC_BDCR)
- 6.4.29 Control/status register (RCC_CSR)
- 6.4.30 Clock recovery RC register (RCC_CRRCR)
- 6.4.31 Peripherals independent clock configuration register (RCC_CCIPR2)
- 6.4.32 RCC register map
- 7 Clock recovery system (CRS)
- 8 General-purpose I/Os (GPIO)
- 8.1 Introduction
- 8.2 GPIO main features
- 8.3 GPIO functional description
- Figure 19. Basic structure of an I/O port bit
- Figure 20. Basic structure of a 5-Volt tolerant I/O port bit
- Table 36. Port bit configuration table
- 8.3.1 General-purpose I/O (GPIO)
- 8.3.2 I/O pin alternate function multiplexer and mapping
- 8.3.3 I/O port control registers
- 8.3.4 I/O port data registers
- 8.3.5 I/O data bitwise handling
- 8.3.6 GPIO locking mechanism
- 8.3.7 I/O alternate function input/output
- 8.3.8 External interrupt/wakeup lines
- 8.3.9 Input configuration
- 8.3.10 Output configuration
- 8.3.11 Alternate function configuration
- 8.3.12 Analog configuration
- 8.3.13 Using the HSE or LSE oscillator pins as GPIOs
- 8.3.14 Using the GPIO pins in the RTC supply domain
- 8.3.15 Using PH3 as GPIO
- 8.4 GPIO registers
- 8.4.1 GPIO port mode register (GPIOx_MODER) (x =A to E and H)
- 8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A to E and H)
- 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A to E and H)
- 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to E and H)
- 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A to E and H)
- 8.4.6 GPIO port output data register (GPIOx_ODR) (x = A to E and H)
- 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A to E and H)
- 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A to E and H)
- 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A to E and H)
- 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A to E and H)
- 8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to E and H)
- 8.4.12 GPIO register map
- 9 System configuration controller (SYSCFG)
- 9.1 SYSCFG main features
- 9.2 SYSCFG registers
- 9.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)
- 9.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1)
- 9.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)
- 9.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
- 9.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
- 9.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)
- 9.2.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR)
- 9.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2)
- 9.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR)
- 9.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR)
- 9.2.11 SYSCFG register map
- 10 Peripherals interconnect matrix
- 10.1 Introduction
- 10.2 Connection summary
- 10.3 Interconnection details
- 10.3.1 From timer (TIM1/TIM2/TIM15/TIM16) to timer (TIM1/TIM2/TIM15/TIM16)
- 10.3.2 From timer (TIM1/TIM2/TIM6/TIM15) and EXTI to ADC (ADC1)
- 10.3.3 From ADC (ADC1) to timer (TIM1)
- 10.3.4 From timer (TIM2/TIM6/TIM7) and EXTI to DAC (DAC1/DAC2)
- 10.3.5 From HSE, LSE, LSI, MSI, MCO, RTC to timer (TIM2/TIM15/TIM16)
- 10.3.6 From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2)
- 10.3.7 From timer (TIM1/TIM2/TIM15) to comparators (COMP1/COMP2)
- 10.3.8 From ADC (ADC1) to ADC (ADC2)
- 10.3.9 From USB to timer (TIM2)
- 10.3.10 From internal analog source to ADC (ADC1) and OPAMP (OPAMP1)
- 10.3.11 From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM15/TIM16)
- 10.3.12 From system errors to timers (TIM1/TIM15/TIM16)
- 10.3.13 From timers (TIM16) to IRTIM
- 11 Direct memory access controller (DMA)
- 11.1 Introduction
- 11.2 DMA main features
- 11.3 DMA implementation
- 11.4 DMA functional description
- 11.5 DMA interrupts
- 11.6 DMA registers
- 11.6.1 DMA interrupt status register (DMA_ISR)
- 11.6.2 DMA interrupt flag clear register (DMA_IFCR)
- 11.6.3 DMA channel x configuration register (DMA_CCRx)
- 11.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx)
- 11.6.5 DMA channel x peripheral address register (DMA_CPARx)
- 11.6.6 DMA channel x memory address register (DMA_CMARx)
- 11.6.7 DMA channel selection register (DMA_CSELR)
- 11.6.8 DMA register map and reset values
- 12 Nested vectored interrupt controller (NVIC)
- 13 Extended interrupts and events controller (EXTI)
- 13.1 Introduction
- 13.2 EXTI main features
- 13.3 EXTI functional description
- 13.4 EXTI interrupt/event line mapping
- 13.5 EXTI registers
- 13.5.1 Interrupt mask register 1 (EXTI_IMR1)
- 13.5.2 Event mask register 1 (EXTI_EMR1)
- 13.5.3 Rising trigger selection register 1 (EXTI_RTSR1)
- 13.5.4 Falling trigger selection register 1 (EXTI_FTSR1)
- 13.5.5 Software interrupt event register 1 (EXTI_SWIER1)
- 13.5.6 Pending register 1 (EXTI_PR1)
- 13.5.7 Interrupt mask register 2 (EXTI_IMR2)
- 13.5.8 Event mask register 2 (EXTI_EMR2)
- 13.5.9 Rising trigger selection register 2 (EXTI_RTSR2)
- 13.5.10 Falling trigger selection register 2 (EXTI_FTSR2)
- 13.5.11 Software interrupt event register 2 (EXTI_SWIER2)
- 13.5.12 Pending register 2 (EXTI_PR2)
- 13.5.13 EXTI register map
- 14 Cyclic redundancy check calculation unit (CRC)
- 15 Quad-SPI interface (QUADSPI)
- 15.1 Introduction
- 15.2 QUADSPI main features
- 15.3 QUADSPI functional description
- 15.3.1 QUADSPI block diagram
- 15.3.2 QUADSPI pins
- 15.3.3 QUADSPI command sequence
- 15.3.4 QUADSPI signal interface protocol modes
- 15.3.5 QUADSPI indirect mode
- 15.3.6 QUADSPI status flag polling mode
- 15.3.7 QUADSPI memory-mapped mode
- 15.3.8 QUADSPI Flash memory configuration
- 15.3.9 QUADSPI delayed data sampling
- 15.3.10 QUADSPI configuration
- 15.3.11 QUADSPI usage
- 15.3.12 Sending the instruction only once
- 15.3.13 QUADSPI error management
- 15.3.14 QUADSPI busy bit and abort functionality
- 15.3.15 nCS behavior
- 15.4 QUADSPI interrupts
- 15.5 QUADSPI registers
- 15.5.1 QUADSPI control register (QUADSPI_CR)
- 15.5.2 QUADSPI device configuration register (QUADSPI_DCR)
- 15.5.3 QUADSPI status register (QUADSPI_SR)
- 15.5.4 QUADSPI flag clear register (QUADSPI_FCR)
- 15.5.5 QUADSPI data length register (QUADSPI_DLR)
- 15.5.6 QUADSPI communication configuration register (QUADSPI_CCR)
- 15.5.7 QUADSPI address register (QUADSPI_AR)
- 15.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR)
- 15.5.9 QUADSPI data register (QUADSPI_DR)
- 15.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR)
- 15.5.11 QUADSPI polling status match register (QUADSPI _PSMAR)
- 15.5.12 QUADSPI polling interval register (QUADSPI _PIR)
- 15.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR)
- 15.5.14 QUADSPI register map
- 16 Analog-to-digital converters (ADC)
- 16.1 Introduction
- 16.2 ADC main features
- 16.3 ADC implementation
- 16.4 ADC functional description
- 16.4.1 ADC block diagram
- 16.4.2 ADC pins and internal signals
- 16.4.3 Clocks
- 16.4.4 ADC1/2 connectivity
- 16.4.5 Slave AHB interface
- 16.4.6 ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN)
- 16.4.7 Single-ended and differential input channels
- 16.4.8 Calibration (ADCAL, ADCALDIF, ADC_CALFACT)
- 16.4.9 ADC on-off control (ADEN, ADDIS, ADRDY)
- 16.4.10 Constraints when writing the ADC control bits
- 16.4.11 Channel selection (SQRx, JSQRx)
- 16.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2)
- 16.4.13 Single conversion mode (CONT=0)
- 16.4.14 Continuous conversion mode (CONT=1)
- 16.4.15 Starting conversions (ADSTART, JADSTART)
- 16.4.16 ADC timing
- 16.4.17 Stopping an ongoing conversion (ADSTP, JADSTP)
- 16.4.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN,JEXTSEL, JEXTEN)
- Table 57. Configuring the trigger polarity for regular external triggers
- Table 58. Configuring the trigger polarity for injected external triggers
- Figure 50. Triggers sharing between ADC master and ADC slave
- Table 59. ADC1 and ADC2 - External triggers for regular channels
- Table 60. ADC1 and ADC2 - External trigger for injected channels
- 16.4.19 Injected channel management
- 16.4.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN)
- 16.4.21 Queue of context for injected conversions
- Figure 52. Example of JSQR queue of context (sequence change)
- Figure 53. Example of JSQR queue of context (trigger change)
- Figure 54. Example of JSQR queue of context with overflow before conversion
- Figure 55. Example of JSQR queue of context with overflow during conversion
- Figure 56. Example of JSQR queue of context with empty queue (case JQM=0)
- Figure 57. Example of JSQR queue of context with empty queue (case JQM=1)
- Figure 58. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion.
- Figure 59. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion and a new trigger occurs.
- Figure 60. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs outside an ongoing conversion
- Figure 61. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1)
- Figure 62. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0)
- Figure 63. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1)
- 16.4.22 Programmable resolution (RES) - fast conversion mode
- 16.4.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP)
- 16.4.24 End of conversion sequence (EOS, JEOS)
- 16.4.25 Timing diagrams example (single/continuous modes, hardware/software triggers)
- 16.4.26 Data management
- Table 62. Offset computation versus data resolution
- Figure 68. Right alignment (offset disabled, unsigned value)
- Figure 69. Right alignment (offset enabled, signed value)
- Figure 70. Left alignment (offset disabled, unsigned value)
- Figure 71. Left alignment (offset enabled, signed value)
- Figure 72. Example of overrun (OVR)
- 16.4.27 Managing conversions using the DFSDM
- 16.4.28 Dynamic low-power features
- Figure 73. AUTODLY=1, regular conversion in continuous mode, software trigger
- Figure 74. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0; JDISCEN=0)
- Figure 75. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=1, JDISCEN=1)
- Figure 76. AUTODLY=1, regular continuous conversions interrupted by injected conversions
- Figure 77. AUTODLY=1 in auto- injected mode (JAUTO=1)
- 16.4.29 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
- Figure 78. Analog watchdog guarded area
- Table 63. Analog watchdog channel selection
- Table 64. Analog watchdog 1 comparison
- Table 65. Analog watchdog 2 and 3 comparison
- Figure 79. ADCy_AWDx_OUT signal generation (on all regular channels)
- Figure 80. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by software)
- Figure 81. ADCy_AWDx_OUT signal generation (on a single regular channel)
- Figure 82. ADCy_AWDx_OUT signal generation (on all injected channels)
- 16.4.30 Oversampler
- Figure 83. 20-bit to 16-bit result truncation
- Figure 84. Numerical example with 5-bit shift and rounding
- Table 66. Maximum output results versus N and M (gray cells indicate truncation)
- Figure 85. Triggered regular oversampling mode (TROVS bit = 1)
- Figure 86. Regular oversampling modes (4x ratio)
- Figure 87. Regular and injected oversampling modes used simultaneously
- Figure 88. Triggered regular oversampling with injection
- Figure 89. Oversampling in auto-injected mode
- Table 67. Oversampler operating modes summary
- 16.4.31 Dual ADC modes
- Figure 90. Dual ADC block diagram(1)
- Figure 91. Injected simultaneous mode on 4 channels: dual ADC mode
- Figure 92. Regular simultaneous mode on 16 channels: dual ADC mode
- Figure 93. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode
- Figure 94. Interleaved mode on 1 channel in single conversion mode: dual ADC mode
- Figure 95. Interleaved conversion with injection
- Figure 96. Alternate trigger: injected group of each ADC
- Figure 97. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode
- Figure 98. Alternate + regular simultaneous
- Figure 99. Case of trigger occurring during injected conversion
- Figure 100. Interleaved single channel CH0 with injected sequence CH11, CH12
- Figure 101. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 1: Master interrupted first
- Figure 102. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 2: Slave interrupted first
- Figure 103. DMA Requests in regular simultaneous mode when MDMA=0b00
- Figure 104. DMA requests in regular simultaneous mode when MDMA=0b10
- Figure 105. DMA requests in interleaved mode when MDMA=0b10
- 16.4.32 Temperature sensor
- 16.4.33 VBAT supply monitoring
- 16.4.34 Monitoring the internal voltage reference
- 16.5 ADC interrupts
- 16.6 ADC registers (for each ADC)
- 16.6.1 ADC interrupt and status register (ADC_ISR)
- 16.6.2 ADC interrupt enable register (ADC_IER)
- 16.6.3 ADC control register (ADC_CR)
- 16.6.4 ADC configuration register (ADC_CFGR)
- 16.6.5 ADC configuration register 2 (ADC_CFGR2)
- 16.6.6 ADC sample time register 1 (ADC_SMPR1)
- 16.6.7 ADC sample time register 2 (ADC_SMPR2)
- 16.6.8 ADC watchdog threshold register 1 (ADC_TR1)
- 16.6.9 ADC watchdog threshold register 2 (ADC_TR2)
- 16.6.10 ADC watchdog threshold register 3 (ADC_TR3)
- 16.6.11 ADC regular sequence register 1 (ADC_SQR1)
- 16.6.12 ADC regular sequence register 2 (ADC_SQR2)
- 16.6.13 ADC regular sequence register 3 (ADC_SQR3)
- 16.6.14 ADC regular sequence register 4 (ADC_SQR4)
- 16.6.15 ADC regular data register (ADC_DR)
- 16.6.16 ADC injected sequence register (ADC_JSQR)
- 16.6.17 ADC offset y register (ADC_OFRy)
- 16.6.18 ADC injected channel y data register (ADC_JDRy)
- 16.6.19 ADC Analog Watchdog 2 Configuration Register (ADC_AWD2CR)
- 16.6.20 ADC Analog Watchdog 3 Configuration Register (ADC_AWD3CR)
- 16.6.21 ADC Differential mode Selection Register (ADC_DIFSEL)
- 16.6.22 ADC Calibration Factors (ADC_CALFACT)
- 16.7 ADC common registers
- 17 Digital-to-analog converter (DAC)
- 17.1 Introduction
- 17.2 DAC main features
- 17.3 DAC implementation
- 17.4 DAC functional description
- 17.4.1 DAC block diagram
- 17.4.2 DAC channel enable
- 17.4.3 DAC data format
- 17.4.4 DAC conversion
- 17.4.5 DAC output voltage
- 17.4.6 DAC trigger selection
- 17.4.7 DMA requests
- 17.4.8 Noise generation
- 17.4.9 Triangle-wave generation
- 17.4.10 DAC channel modes
- 17.4.11 DAC channel buffer calibration
- 17.4.12 Dual DAC channel conversion (if available)
- 17.5 DAC low-power modes
- 17.6 DAC interrupts
- 17.7 DAC registers
- 17.7.1 DAC control register (DAC_CR)
- 17.7.2 DAC software trigger register (DAC_SWTRGR)
- 17.7.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)
- 17.7.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
- 17.7.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
- 17.7.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
- 17.7.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
- 17.7.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
- 17.7.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD)
- 17.7.10 Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD)
- 17.7.11 Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD)
- 17.7.12 DAC channel1 data output register (DAC_DOR1)
- 17.7.13 DAC channel2 data output register (DAC_DOR2)
- 17.7.14 DAC status register (DAC_SR)
- 17.7.15 DAC calibration control register (DAC_CCR)
- 17.7.16 DAC mode control register (DAC_MCR)
- 17.7.17 DAC channel 1 sample and hold sample time register (DAC_SHSR1)
- 17.7.18 DAC channel 2 sample and hold sample time register (DAC_SHSR2)
- 17.7.19 DAC sample and hold time register (DAC_SHHR)
- 17.7.20 DAC sample and hold refresh time register (DAC_SHRR)
- 17.7.21 DAC register map
- 18 Voltage reference buffer (VREFBUF)
- 19 Comparator (COMP)
- 19.1 Introduction
- 19.2 COMP main features
- 19.3 COMP functional description
- 19.4 COMP low-power modes
- 19.5 COMP interrupts
- 19.6 COMP registers
- 20 Operational amplifiers (OPAMP)
- 21 Digital filter for sigma delta modulators (DFSDM)
- 21.1 Introduction
- 21.2 DFSDM main features
- 21.3 DFSDM implementation
- 21.4 DFSDM functional description
- 21.4.1 DFSDM block diagram
- 21.4.2 DFSDM pins and internal signals
- 21.4.3 DFSDM reset and clocks
- 21.4.4 Serial channel transceivers
- 21.4.5 Configuring the input serial interface
- 21.4.6 Parallel data inputs
- 21.4.7 Channel selection
- 21.4.8 Digital filter configuration
- 21.4.9 Integrator unit
- 21.4.10 Analog watchdog
- 21.4.11 Short-circuit detector
- 21.4.12 Extreme detector
- 21.4.13 Data unit block
- 21.4.14 Signed data format
- 21.4.15 Launching conversions
- 21.4.16 Continuous and fast continuous modes
- 21.4.17 Request precedence
- 21.4.18 Power optimization in run mode
- 21.5 DFSDM interrupts
- 21.6 DFSDM DMA transfer
- 21.7 DFSDM channel y registers (y=0..3)
- 21.7.1 DFSDM channel y configuration register (DFSDM_CHyCFGR1)
- 21.7.2 DFSDM channel y configuration register (DFSDM_CHyCFGR2)
- 21.7.3 DFSDM channel y analog watchdog and short-circuit detector register (DFSDM_CHyAWSCDR)
- 21.7.4 DFSDM channel y watchdog filter data register (DFSDM_CHyWDATR)
- 21.7.5 DFSDM channel y data input register (DFSDM_CHyDATINR)
- 21.8 DFSDM filter x module registers (x=0..1)
- 21.8.1 DFSDM filter x control register 1 (DFSDM_FLTxCR1)
- 21.8.2 DFSDM filter x control register 2 (DFSDM_FLTxCR2)
- 21.8.3 DFSDM filter x interrupt and status register (DFSDM_FLTxISR)
- 21.8.4 DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR)
- 21.8.5 DFSDM filter x injected channel group selection register (DFSDM_FLTxJCHGR)
- 21.8.6 DFSDM filter x control register (DFSDM_FLTxFCR)
- 21.8.7 DFSDM filter x data register for injected group (DFSDM_FLTxJDATAR)
- 21.8.8 DFSDM filter x data register for the regular channel (DFSDM_FLTxRDATAR)
- 21.8.9 DFSDM filter x analog watchdog high threshold register (DFSDM_FLTxAWHTR)
- 21.8.10 DFSDM filter x analog watchdog low threshold register (DFSDM_FLTxAWLTR)
- 21.8.11 DFSDM filter x analog watchdog status register (DFSDM_FLTxAWSR)
- 21.8.12 DFSDM filter x analog watchdog clear flag register (DFSDM_FLTxAWCFR)
- 21.8.13 DFSDM filter x extremes detector maximum register (DFSDM_FLTxEXMAX)
- 21.8.14 DFSDM filter x extremes detector minimum register (DFSDM_FLTxEXMIN)
- 21.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR)
- 21.8.16 DFSDM register map
- 22 Liquid crystal display controller (LCD)
- 22.1 Introduction
- 22.2 LCD main features
- 22.3 LCD functional description
- 22.4 LCD low-power modes
- 22.5 LCD interrupts
- 22.6 LCD registers
- 23 Touch sensing controller (TSC)
- 23.1 Introduction
- 23.2 TSC main features
- 23.3 TSC functional description
- 23.3.1 TSC block diagram
- 23.3.2 Surface charge transfer acquisition overview
- 23.3.3 Reset and clocks
- 23.3.4 Charge transfer acquisition sequence
- 23.3.5 Spread spectrum feature
- 23.3.6 Max count error
- 23.3.7 Sampling capacitor I/O and channel I/O mode selection
- 23.3.8 Acquisition mode
- 23.3.9 I/O hysteresis and analog switch control
- 23.4 TSC low-power modes
- 23.5 TSC interrupts
- 23.6 TSC registers
- 23.6.1 TSC control register (TSC_CR)
- 23.6.2 TSC interrupt enable register (TSC_IER)
- 23.6.3 TSC interrupt clear register (TSC_ICR)
- 23.6.4 TSC interrupt status register (TSC_ISR)
- 23.6.5 TSC I/O hysteresis control register (TSC_IOHCR)
- 23.6.6 TSC I/O analog switch control register (TSC_IOASCR)
- 23.6.7 TSC I/O sampling control register (TSC_IOSCR)
- 23.6.8 TSC I/O channel control register (TSC_IOCCR)
- 23.6.9 TSC I/O group control status register (TSC_IOGCSR)
- 23.6.10 TSC I/O group x counter register (TSC_IOGxCR)
- 23.6.11 TSC register map
- 24 True random number generator (RNG)
- 25 AES hardware accelerator (AES)
- 25.1 Introduction
- 25.2 AES main features
- 25.3 AES implementation
- 25.4 AES functional description
- 25.4.1 AES block diagram
- 25.4.2 AES internal signals
- 25.4.3 AES cryptographic core
- Figure 154. ECB encryption and decryption principle
- Figure 155. CBC encryption and decryption principle
- Figure 156. CTR encryption and decryption principle
- Figure 157. GCM encryption and authentication principle
- Figure 158. GMAC authentication principle
- Figure 159. CCM encryption and authentication principle
- 25.4.4 AES procedure to perform a cipher operation
- 25.4.5 AES decryption key preparation
- 25.4.6 AES ciphertext stealing and data padding
- 25.4.7 AES task suspend and resume
- 25.4.8 AES basic chaining modes (ECB, CBC)
- 25.4.9 AES counter (CTR) mode
- 25.4.10 AES Galois/counter mode (GCM)
- 25.4.11 AES Galois message authentication code (GMAC)
- 25.4.12 AES counter with CBC-MAC (CCM)
- 25.4.13 .AES data registers and data swapping
- 25.4.14 AES key registers
- 25.4.15 AES initialization vector registers
- 25.4.16 AES DMA interface
- 25.4.17 AES error management
- 25.5 AES interrupts
- 25.6 AES processing latency
- 25.7 AES registers
- 25.7.1 AES control register (AES_CR)
- 25.7.2 AES status register (AES_SR)
- 25.7.3 AES data input register (AES_DINR)
- 25.7.4 AES data output register (AES_DOUTR)
- 25.7.5 AES key register 0 (AES_KEYR0)
- 25.7.6 AES key register 1 (AES_KEYR1)
- 25.7.7 AES key register 2 (AES_KEYR2)
- 25.7.8 AES key register 3 (AES_KEYR3)
- 25.7.9 AES initialization vector register 0 (AES_IVR0)
- 25.7.10 AES initialization vector register 1 (AES_IVR1)
- 25.7.11 AES initialization vector register 2 (AES_IVR2)
- 25.7.12 AES initialization vector register 3 (AES_IVR3)
- 25.7.13 AES key register 4 (AES_KEYR4)
- 25.7.14 AES key register 5 (AES_KEYR5)
- 25.7.15 AES key register 6 (AES_KEYR6)
- 25.7.16 AES key register 7 (AES_KEYR7)
- 25.7.17 AES suspend registers (AES_SUSPxR)
- 25.7.18 AES register map
- 26 Advanced-control timers (TIM1)
- 26.1 TIM1 introduction
- 26.2 TIM1 main features
- 26.3 TIM1 functional description
- 26.3.1 Time-base unit
- 26.3.2 Counter modes
- Figure 186. Counter timing diagram, internal clock divided by 1
- Figure 187. Counter timing diagram, internal clock divided by 2
- Figure 188. Counter timing diagram, internal clock divided by 4
- Figure 189. Counter timing diagram, internal clock divided by N
- Figure 190. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 191. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- Figure 192. Counter timing diagram, internal clock divided by 1
- Figure 193. Counter timing diagram, internal clock divided by 2
- Figure 194. Counter timing diagram, internal clock divided by 4
- Figure 195. Counter timing diagram, internal clock divided by N
- Figure 196. Counter timing diagram, update event when repetition counter is not used
- Figure 197. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
- Figure 198. Counter timing diagram, internal clock divided by 2
- Figure 199. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
- Figure 200. Counter timing diagram, internal clock divided by N
- Figure 201. Counter timing diagram, update event with ARPE=1 (counter underflow)
- Figure 202. Counter timing diagram, Update event with ARPE=1 (counter overflow)
- 26.3.3 Repetition counter
- 26.3.4 External trigger input
- 26.3.5 Clock selection
- 26.3.6 Capture/compare channels
- Figure 211. Capture/compare channel (example: channel 1 input stage)
- Figure 212. Capture/compare channel 1 main circuit
- Figure 213. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3)
- Figure 214. Output stage of capture/compare channel (channel 4)
- Figure 215. Output stage of capture/compare channel (channel 5, idem ch. 6)
- 26.3.7 Input capture mode
- 26.3.8 PWM input mode
- 26.3.9 Forced output mode
- 26.3.10 Output compare mode
- 26.3.11 PWM mode
- 26.3.12 Asymmetric PWM mode
- 26.3.13 Combined PWM mode
- 26.3.14 Combined 3-phase PWM mode
- 26.3.15 Complementary outputs and dead-time insertion
- 26.3.16 Using the break function
- Figure 226. Break and Break2 circuitry overview
- Figure 227. Various output behavior in response to a break event on BRK (OSSI = 1)
- Table 130. Behavior of timer outputs versus BRK/BRK2 inputs
- Figure 228. PWM output state following BRK and BRK2 pins assertion (OSSI=1)
- Figure 229. PWM output state following BRK assertion (OSSI=0)
- 26.3.17 Bidirectional break inputs
- 26.3.18 Clearing the OCxREF signal on an external event
- 26.3.19 6-step PWM generation
- 26.3.20 One-pulse mode
- 26.3.21 Retriggerable one pulse mode (OPM)
- 26.3.22 Encoder interface mode
- 26.3.23 UIF bit remapping
- 26.3.24 Timer input XOR function
- 26.3.25 Interfacing with Hall sensors
- 26.3.26 Timer synchronization
- 26.3.27 ADC synchronization
- 26.3.28 DMA burst mode
- 26.3.29 Debug mode
- 26.4 TIM1 registers
- 26.4.1 TIM1 control register 1 (TIM1_CR1)
- 26.4.2 TIM1 control register 2 (TIM1_CR2)
- 26.4.3 TIM1 slave mode control register (TIM1_SMCR)
- 26.4.4 TIM1 DMA/interrupt enable register (TIM1_DIER)
- 26.4.5 TIM1 status register (TIM1_SR)
- 26.4.6 TIM1 event generation register (TIM1_EGR)
- 26.4.7 TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1)
- 26.4.8 TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1)
- 26.4.9 TIM1 capture/compare mode register 2 [alternate] (TIM1_CCMR2)
- 26.4.10 TIM1 capture/compare mode register 2 [alternate] (TIM1_CCMR2)
- 26.4.11 TIM1 capture/compare enable register (TIM1_CCER)
- 26.4.12 TIM1 counter (TIM1_CNT)
- 26.4.13 TIM1 prescaler (TIM1_PSC)
- 26.4.14 TIM1 auto-reload register (TIM1_ARR)
- 26.4.15 TIM1 repetition counter register (TIM1_RCR)
- 26.4.16 TIM1 capture/compare register 1 (TIM1_CCR1)
- 26.4.17 TIM1 capture/compare register 2 (TIM1_CCR2)
- 26.4.18 TIM1 capture/compare register 3 (TIM1_CCR3)
- 26.4.19 TIM1 capture/compare register 4 (TIM1_CCR4)
- 26.4.20 TIM1 break and dead-time register (TIM1_BDTR)
- 26.4.21 TIM1 DMA control register (TIM1_DCR)
- 26.4.22 TIM1 DMA address for full transfer (TIM1_DMAR)
- 26.4.23 TIM1 option register 1 (TIM1_OR1)
- 26.4.24 TIM1 capture/compare mode register 3 (TIM1_CCMR3)
- 26.4.25 TIM1 capture/compare register 5 (TIM1_CCR5)
- 26.4.26 TIM1 capture/compare register 6 (TIM1_CCR6)
- 26.4.27 TIM1 option register 2 (TIM1_OR2)
- 26.4.28 TIM1 option register 3 (TIM1_OR3)
- 26.4.29 TIM1 register map
- 27 General-purpose timers (TIM2/TIM3)
- 27.1 TIM2/TIM3 introduction
- 27.2 TIM2/TIM3 main features
- 27.3 TIM2/TIM3 functional description
- 27.3.1 Time-base unit
- 27.3.2 Counter modes
- Figure 246. Counter timing diagram, internal clock divided by 1
- Figure 247. Counter timing diagram, internal clock divided by 2
- Figure 248. Counter timing diagram, internal clock divided by 4
- Figure 249. Counter timing diagram, internal clock divided by N
- Figure 250. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 251. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)
- Figure 252. Counter timing diagram, internal clock divided by 1
- Figure 253. Counter timing diagram, internal clock divided by 2
- Figure 254. Counter timing diagram, internal clock divided by 4
- Figure 255. Counter timing diagram, internal clock divided by N
- Figure 256. Counter timing diagram, Update event when repetition counter is not used
- Figure 257. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
- Figure 258. Counter timing diagram, internal clock divided by 2
- Figure 259. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
- Figure 260. Counter timing diagram, internal clock divided by N
- Figure 261. Counter timing diagram, Update event with ARPE=1 (counter underflow)
- Figure 262. Counter timing diagram, Update event with ARPE=1 (counter overflow)
- 27.3.3 Clock selection
- 27.3.4 Capture/Compare channels
- 27.3.5 Input capture mode
- 27.3.6 PWM input mode
- 27.3.7 Forced output mode
- 27.3.8 Output compare mode
- 27.3.9 PWM mode
- 27.3.10 Asymmetric PWM mode
- 27.3.11 Combined PWM mode
- 27.3.12 Clearing the OCxREF signal on an external event
- 27.3.13 One-pulse mode
- 27.3.14 Retriggerable one pulse mode (OPM)
- 27.3.15 Encoder interface mode
- 27.3.16 UIF bit remapping
- 27.3.17 Timer input XOR function
- 27.3.18 Timers and external trigger synchronization
- 27.3.19 Timer synchronization
- 27.3.20 DMA burst mode
- 27.3.21 Debug mode
- 27.4 TIM2/TIM3 registers
- 27.4.1 TIMx control register 1 (TIMx_CR1)(x = 2 to 3)
- 27.4.2 TIMx control register 2 (TIMx_CR2)(x = 2 to 3)
- 27.4.3 TIMx slave mode control register (TIMx_SMCR)(x = 2 to 3)
- 27.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 3)
- 27.4.5 TIMx status register (TIMx_SR)(x = 2 to 3)
- 27.4.6 TIMx event generation register (TIMx_EGR)(x = 2 to 3)
- 27.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 3)
- 27.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 3)
- 27.4.9 TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 3)
- 27.4.10 TIMx counter (TIMx_CNT)(x = 2 to 3)
- 27.4.11 TIMx prescaler (TIMx_PSC)(x = 2 to 3)
- 27.4.12 TIMx auto-reload register (TIMx_ARR)(x = 2 to 3)
- 27.4.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 3)
- 27.4.14 TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 3)
- 27.4.15 TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 3)
- 27.4.16 TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 3)
- 27.4.17 TIMx DMA control register (TIMx_DCR)(x = 2 to 3)
- 27.4.18 TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 3)
- 27.4.19 TIM2 option register 1 (TIM2_OR1)
- 27.4.20 TIM2 option register 2 (TIM2_OR2)
- 27.4.21 TIMx register map
- 28 General-purpose timers (TIM15/TIM16)
- 28.1 TIM15/TIM16 introduction
- 28.2 TIM15 main features
- 28.3 TIM16 main features
- 28.4 Implementation
- 28.5 TIM15/TIM16 functional description
- 28.5.1 Time-base unit
- 28.5.2 Counter modes
- Figure 296. Counter timing diagram, internal clock divided by 1
- Figure 297. Counter timing diagram, internal clock divided by 2
- Figure 298. Counter timing diagram, internal clock divided by 4
- Figure 299. Counter timing diagram, internal clock divided by N
- Figure 300. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
- Figure 301. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 28.5.3 Repetition counter
- 28.5.4 Clock selection
- 28.5.5 Capture/compare channels
- 28.5.6 Input capture mode
- 28.5.7 PWM input mode (only for TIM15)
- 28.5.8 Forced output mode
- 28.5.9 Output compare mode
- 28.5.10 PWM mode
- 28.5.11 Combined PWM mode (TIM15 only)
- 28.5.12 Complementary outputs and dead-time insertion
- 28.5.13 Using the break function
- 28.5.14 One-pulse mode
- 28.5.15 Retriggerable one pulse mode (OPM) (TIM15 only)
- 28.5.16 UIF bit remapping
- 28.5.17 Timer input XOR function (TIM15 only)
- 28.5.18 External trigger synchronization (TIM15 only)
- 28.5.19 Slave mode – combined reset + trigger mode
- 28.5.20 DMA burst mode
- 28.5.21 Timer synchronization (TIM15)
- 28.5.22 Debug mode
- 28.6 TIM15 registers
- 28.6.1 TIM15 control register 1 (TIM15_CR1)
- 28.6.2 TIM15 control register 2 (TIM15_CR2)
- 28.6.3 TIM15 slave mode control register (TIM15_SMCR)
- 28.6.4 TIM15 DMA/interrupt enable register (TIM15_DIER)
- 28.6.5 TIM15 status register (TIM15_SR)
- 28.6.6 TIM15 event generation register (TIM15_EGR)
- 28.6.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1)
- 28.6.8 TIM15 capture/compare enable register (TIM15_CCER)
- 28.6.9 TIM15 counter (TIM15_CNT)
- 28.6.10 TIM15 prescaler (TIM15_PSC)
- 28.6.11 TIM15 auto-reload register (TIM15_ARR)
- 28.6.12 TIM15 repetition counter register (TIM15_RCR)
- 28.6.13 TIM15 capture/compare register 1 (TIM15_CCR1)
- 28.6.14 TIM15 capture/compare register 2 (TIM15_CCR2)
- 28.6.15 TIM15 break and dead-time register (TIM15_BDTR)
- 28.6.16 TIM15 DMA control register (TIM15_DCR)
- 28.6.17 TIM15 DMA address for full transfer (TIM15_DMAR)
- 28.6.18 TIM15 option register 1 (TIM15_OR1)
- 28.6.19 TIM15 option register 2 (TIM15_OR2)
- 28.6.20 TIM15 register map
- 28.7 TIM16 registers
- 28.7.1 TIM16 control register 1 (TIM16_CR1)
- 28.7.2 TIM16 control register 2 (TIM16_CR2)
- 28.7.3 TIM16 DMA/interrupt enable register (TIM16_DIER)
- 28.7.4 TIM16 status register (TIM16_SR)
- 28.7.5 TIM16 event generation register (TIM16_EGR)
- 28.7.6 TIM16 capture/compare mode register 1 (TIM16_CCMR1)
- 28.7.7 TIM16 capture/compare enable register (TIM16_CCER)
- 28.7.8 TIM16 counter (TIM16_CNT)
- 28.7.9 TIM16 prescaler (TIM16_PSC)
- 28.7.10 TIM16 auto-reload register (TIM16_ARR)
- 28.7.11 TIM16 repetition counter register (TIM16_RCR)
- 28.7.12 TIM16 capture/compare register 1 (TIM16_CCR1)
- 28.7.13 TIM16 break and dead-time register (TIM16_BDTR)
- 28.7.14 TIM16 DMA control register (TIM16_DCR)
- 28.7.15 TIM16 DMA address for full transfer (TIM16_DMAR)
- 28.7.16 TIM16 option register 1 (TIM16_OR1)
- 28.7.17 TIM16 option register 2 (TIM16_OR2)
- 28.7.18 TIM16 register map
- 29 Basic timers (TIM6/TIM7)
- 29.1 TIM6/TIM7 introduction
- 29.2 TIM6/TIM7 main features
- 29.3 TIM6/TIM7 functional description
- 29.3.1 Time-base unit
- 29.3.2 Counting mode
- Figure 328. Counter timing diagram, internal clock divided by 1
- Figure 329. Counter timing diagram, internal clock divided by 2
- Figure 330. Counter timing diagram, internal clock divided by 4
- Figure 331. Counter timing diagram, internal clock divided by N
- Figure 332. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded)
- Figure 333. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
- 29.3.3 UIF bit remapping
- 29.3.4 Clock source
- 29.3.5 Debug mode
- 29.4 TIM6/TIM7 registers
- 29.4.1 TIM6/TIM7 control register 1 (TIMx_CR1)
- 29.4.2 TIM6/TIM7 control register 2 (TIMx_CR2)
- 29.4.3 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER)
- 29.4.4 TIM6/TIM7 status register (TIMx_SR)
- 29.4.5 TIM6/TIM7 event generation register (TIMx_EGR)
- 29.4.6 TIM6/TIM7 counter (TIMx_CNT)
- 29.4.7 TIM6/TIM7 prescaler (TIMx_PSC)
- 29.4.8 TIM6/TIM7 auto-reload register (TIMx_ARR)
- 29.4.9 TIM6/TIM7 register map
- 30 Low-power timer (LPTIM)
- 30.1 Introduction
- 30.2 LPTIM main features
- 30.3 LPTIM implementation
- 30.4 LPTIM functional description
- 30.4.1 LPTIM block diagram
- 30.4.2 LPTIM trigger mapping
- 30.4.3 LPTIM reset and clocks
- 30.4.4 Glitch filter
- 30.4.5 Prescaler
- 30.4.6 Trigger multiplexer
- 30.4.7 Operating mode
- Figure 338. LPTIM output waveform, single counting mode configuration
- Figure 339. LPTIM output waveform, single counting mode configuration when repetition register content is different than zero (with PRELOAD = 1)
- Figure 340. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set)
- Figure 341. LPTIM output waveform, Continuous counting mode configuration
- 30.4.8 Timeout function
- 30.4.9 Waveform generation
- 30.4.10 Register update
- 30.4.11 Counter mode
- 30.4.12 Timer enable
- 30.4.13 Timer counter reset
- 30.4.14 Encoder mode
- 30.4.15 Repetition Counter
- 30.4.16 Debug mode
- 30.5 LPTIM low-power modes
- 30.6 LPTIM interrupts
- 30.7 LPTIM registers
- 30.7.1 LPTIM interrupt and status register (LPTIM_ISR)
- 30.7.2 LPTIM interrupt clear register (LPTIM_ICR)
- 30.7.3 LPTIM interrupt enable register (LPTIM_IER)
- 30.7.4 LPTIM configuration register (LPTIM_CFGR)
- 30.7.5 LPTIM control register (LPTIM_CR)
- 30.7.6 LPTIM compare register (LPTIM_CMP)
- 30.7.7 LPTIM autoreload register (LPTIM_ARR)
- 30.7.8 LPTIM counter register (LPTIM_CNT)
- 30.7.9 LPTIM1 option register (LPTIM1_OR)
- 30.7.10 LPTIM2 option register (LPTIM2_OR)
- 30.7.11 LPTIM configuration register 2 (LPTIM_CFGR2)
- 30.7.12 LPTIM repetition register (LPTIM_RCR)
- 30.7.13 LPTIM register map
- 31 Infrared interface (IRTIM)
- 32 Independent watchdog (IWDG)
- 33 System window watchdog (WWDG)
- 34 Real-time clock (RTC) applied to STM32L41xxx and STM32L42xxx devices only
- 34.1 Introduction
- 34.2 RTC main features
- 34.3 RTC functional description
- 34.3.1 RTC block diagram
- 34.3.2 RTC pins and internal signals
- 34.3.3 GPIOs controlled by the RTC and TAMP
- 34.3.4 Clock and prescalers
- 34.3.5 Real-time clock and calendar
- 34.3.6 Calendar ultra-low power mode
- 34.3.7 Programmable alarms
- 34.3.8 Periodic auto-wakeup
- 34.3.9 RTC initialization and configuration
- 34.3.10 Reading the calendar
- 34.3.11 Resetting the RTC
- 34.3.12 RTC synchronization
- 34.3.13 RTC reference clock detection
- 34.3.14 RTC smooth digital calibration
- 34.3.15 Timestamp function
- 34.3.16 Calibration clock output
- 34.3.17 Tamper and alarm output
- 34.4 RTC low-power modes
- 34.5 RTC interrupts
- 34.6 RTC registers
- 34.6.1 RTC time register (RTC_TR)
- 34.6.2 RTC date register (RTC_DR)
- 34.6.3 RTC sub second register (RTC_SSR)
- 34.6.4 RTC initialization control and status register (RTC_ICSR)
- 34.6.5 RTC prescaler register (RTC_PRER)
- 34.6.6 RTC wakeup timer register (RTC_WUTR)
- 34.6.7 RTC control register (RTC_CR)
- 34.6.8 RTC write protection register (RTC_WPR)
- 34.6.9 RTC calibration register (RTC_CALR)
- 34.6.10 RTC shift control register (RTC_SHIFTR)
- 34.6.11 RTC timestamp time register (RTC_TSTR)
- 34.6.12 RTC timestamp date register (RTC_TSDR)
- 34.6.13 RTC timestamp sub second register (RTC_TSSSR)
- 34.6.14 RTC alarm A register (RTC_ALRMAR)
- 34.6.15 RTC alarm A sub second register (RTC_ALRMASSR)
- 34.6.16 RTC alarm B register (RTC_ALRMBR)
- 34.6.17 RTC alarm B sub second register (RTC_ALRMBSSR)
- 34.6.18 RTC status register (RTC_SR)
- 34.6.19 RTC masked interrupt status register (RTC_MISR)
- 34.6.20 RTC status clear register (RTC_SCR)
- 34.6.21 RTC register map
- 35 Tamper and backup registers (TAMP)
- 35.1 Introduction
- 35.2 TAMP main features
- 35.3 TAMP functional description
- 35.4 TAMP low-power modes
- 35.5 TAMP interrupts
- 35.6 TAMP registers
- 35.6.1 TAMP control register 1 (TAMP_CR1)
- 35.6.2 TAMP control register 2 (TAMP_CR2)
- 35.6.3 TAMP filter control register (TAMP_FLTCR)
- 35.6.4 TAMP interrupt enable register (TAMP_IER)
- 35.6.5 TAMP status register (TAMP_SR)
- 35.6.6 TAMP masked interrupt status register (TAMP_MISR)
- 35.6.7 TAMP status clear register (TAMP_SCR)
- 35.6.8 TAMP backup x register (TAMP_BKPxR)
- 35.6.9 TAMP register map
- 36 Real-time clock (RTC) applied to STM32L43x/44x/45x/46x devices only
- 36.1 Introduction
- 36.2 RTC main features
- 36.3 RTC functional description
- 36.3.1 RTC block diagram
- 36.3.2 GPIOs controlled by the RTC
- 36.3.3 Clock and prescalers
- 36.3.4 Real-time clock and calendar
- 36.3.5 Programmable alarms
- 36.3.6 Periodic auto-wakeup
- 36.3.7 RTC initialization and configuration
- 36.3.8 Reading the calendar
- 36.3.9 Resetting the RTC
- 36.3.10 RTC synchronization
- 36.3.11 RTC reference clock detection
- 36.3.12 RTC smooth digital calibration
- 36.3.13 Time-stamp function
- 36.3.14 Tamper detection
- 36.3.15 Calibration clock output
- 36.3.16 Alarm output
- 36.4 RTC low-power modes
- 36.5 RTC interrupts
- 36.6 RTC registers
- 36.6.1 RTC time register (RTC_TR)
- 36.6.2 RTC date register (RTC_DR)
- 36.6.3 RTC control register (RTC_CR)
- 36.6.4 RTC initialization and status register (RTC_ISR)
- 36.6.5 RTC prescaler register (RTC_PRER)
- 36.6.6 RTC wakeup timer register (RTC_WUTR)
- 36.6.7 RTC alarm A register (RTC_ALRMAR)
- 36.6.8 RTC alarm B register (RTC_ALRMBR)
- 36.6.9 RTC write protection register (RTC_WPR)
- 36.6.10 RTC sub second register (RTC_SSR)
- 36.6.11 RTC shift control register (RTC_SHIFTR)
- 36.6.12 RTC timestamp time register (RTC_TSTR)
- 36.6.13 RTC timestamp date register (RTC_TSDR)
- 36.6.14 RTC time-stamp sub second register (RTC_TSSSR)
- 36.6.15 RTC calibration register (RTC_CALR)
- 36.6.16 RTC tamper configuration register (RTC_TAMPCR)
- 36.6.17 RTC alarm A sub second register (RTC_ALRMASSR)
- 36.6.18 RTC alarm B sub second register (RTC_ALRMBSSR)
- 36.6.19 RTC option register (RTC_OR)
- 36.6.20 RTC backup registers (RTC_BKPxR)
- 36.6.21 RTC register map
- 37 Inter-integrated circuit (I2C) interface
- 37.1 Introduction
- 37.2 I2C main features
- 37.3 I2C implementation
- 37.4 I2C functional description
- 37.4.1 I2C block diagram
- 37.4.2 I2C clock requirements
- 37.4.3 Mode selection
- 37.4.4 I2C initialization
- 37.4.5 Software reset
- 37.4.6 Data transfer
- 37.4.7 I2C slave mode
- Figure 358. Slave initialization flowchart
- Figure 359. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0
- Figure 360. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1
- Figure 361. Transfer bus diagrams for I2C slave transmitter
- Figure 362. Transfer sequence flowchart for slave receiver with NOSTRETCH=0
- Figure 363. Transfer sequence flowchart for slave receiver with NOSTRETCH=1
- Figure 364. Transfer bus diagrams for I2C slave receiver
- 37.4.8 I2C master mode
- Figure 365. Master clock generation
- Table 180. I2C-SMBUS specification clock timings
- Figure 366. Master initialization flowchart
- Figure 367. 10-bit address read access with HEAD10R=0
- Figure 368. 10-bit address read access with HEAD10R=1
- Figure 369. Transfer sequence flowchart for I2C master transmitter for N≤255 bytes
- Figure 370. Transfer sequence flowchart for I2C master transmitter for N>255 bytes
- Figure 371. Transfer bus diagrams for I2C master transmitter
- Figure 372. Transfer sequence flowchart for I2C master receiver for N≤255 bytes
- Figure 373. Transfer sequence flowchart for I2C master receiver for N >255 bytes
- Figure 374. Transfer bus diagrams for I2C master receiver
- 37.4.9 I2C_TIMINGR register configuration examples
- 37.4.10 SMBus specific features
- 37.4.11 SMBus initialization
- 37.4.12 SMBus: I2C_TIMEOUTR register configuration examples
- 37.4.13 SMBus slave mode
- Figure 376. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC
- Figure 377. Transfer bus diagrams for SMBus slave transmitter (SBC=1)
- Figure 378. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC
- Figure 379. Bus transfer diagrams for SMBus slave receiver (SBC=1)
- Figure 380. Bus transfer diagrams for SMBus master transmitter
- Figure 381. Bus transfer diagrams for SMBus master receiver
- 37.4.14 Wakeup from Stop mode on address match
- 37.4.15 Error conditions
- 37.4.16 DMA requests
- 37.4.17 Debug mode
- 37.5 I2C low-power modes
- 37.6 I2C interrupts
- 37.7 I2C registers
- 37.7.1 I2C control register 1 (I2C_CR1)
- 37.7.2 I2C control register 2 (I2C_CR2)
- 37.7.3 I2C own address 1 register (I2C_OAR1)
- 37.7.4 I2C own address 2 register (I2C_OAR2)
- 37.7.5 I2C timing register (I2C_TIMINGR)
- 37.7.6 I2C timeout register (I2C_TIMEOUTR)
- 37.7.7 I2C interrupt and status register (I2C_ISR)
- 37.7.8 I2C interrupt clear register (I2C_ICR)(
- 37.7.9 I2C PEC register (I2C_PECR)
- 37.7.10 I2C receive data register (I2C_RXDR)
- 37.7.11 I2C transmit data register (I2C_TXDR)
- 37.7.12 I2C register map
- 38 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmitter (UART)
- 38.1 Introduction
- 38.2 USART main features
- 38.3 USART extended features
- 38.4 USART implementation
- 38.5 USART functional description
- Figure 382. USART block diagram
- 38.5.1 USART character description
- 38.5.2 USART transmitter
- 38.5.3 USART receiver
- 38.5.4 USART baud rate generation
- 38.5.5 Tolerance of the USART receiver to clock deviation
- 38.5.6 USART auto baud rate detection
- 38.5.7 Multiprocessor communication using USART
- 38.5.8 Modbus communication using USART
- 38.5.9 USART parity control
- 38.5.10 USART LIN (local interconnection network) mode
- 38.5.11 USART synchronous mode
- 38.5.12 USART Single-wire Half-duplex communication
- 38.5.13 USART Smartcard mode
- 38.5.14 USART IrDA SIR ENDEC block
- 38.5.15 USART continuous communication in DMA mode
- 38.5.16 RS232 hardware flow control and RS485 driver enable using USART
- 38.5.17 Wakeup from Stop mode using USART
- 38.6 USART low-power modes
- 38.7 USART interrupts
- 38.8 USART registers
- 38.8.1 Control register 1 (USART_CR1)
- 38.8.2 Control register 2 (USART_CR2)
- 38.8.3 Control register 3 (USART_CR3)
- 38.8.4 Baud rate register (USART_BRR)
- 38.8.5 Guard time and prescaler register (USART_GTPR)
- 38.8.6 Receiver timeout register (USART_RTOR)
- 38.8.7 Request register (USART_RQR)
- 38.8.8 Interrupt and status register (USART_ISR)
- 38.8.9 Interrupt flag clear register (USART_ICR)
- 38.8.10 Receive data register (USART_RDR)
- 38.8.11 Transmit data register (USART_TDR)
- 38.8.12 USART register map
- 39 Low-power universal asynchronous receiver transmitter (LPUART)
- 39.1 Introduction
- 39.2 LPUART main features
- 39.3 LPUART implementation
- 39.4 LPUART functional description
- Figure 407. LPUART block diagram
- 39.4.1 LPUART character description
- 39.4.2 LPUART transmitter
- 39.4.3 LPUART receiver
- 39.4.4 LPUART baud rate generation
- 39.4.5 Tolerance of the LPUART receiver to clock deviation
- 39.4.6 Multiprocessor communication using LPUART
- 39.4.7 LPUART parity control
- 39.4.8 Single-wire Half-duplex communication using LPUART
- 39.4.9 Continuous communication in DMA mode using LPUART
- 39.4.10 RS232 Hardware flow control and RS485 Driver Enable using LPUART
- 39.4.11 Wakeup from Stop mode using LPUART
- 39.5 LPUART low-power mode
- 39.6 LPUART interrupts
- 39.7 LPUART registers
- 39.7.1 Control register 1 (LPUART_CR1)
- 39.7.2 Control register 2 (LPUART_CR2)
- 39.7.3 Control register 3 (LPUART_CR3)
- 39.7.4 Baud rate register (LPUART_BRR)
- 39.7.5 Request register (LPUART_RQR)
- 39.7.6 Interrupt & status register (LPUART_ISR)
- 39.7.7 Interrupt flag clear register (LPUART_ICR)
- 39.7.8 Receive data register (LPUART_RDR)
- 39.7.9 Transmit data register (LPUART_TDR)
- 39.7.10 LPUART register map
- 40 Serial peripheral interface (SPI)
- 40.1 Introduction
- 40.2 SPI main features
- 40.3 SPI implementation
- 40.4 SPI functional description
- 40.4.1 General description
- 40.4.2 Communications between one master and one slave
- 40.4.3 Standard multi-slave communication
- 40.4.4 Multi-master communication
- 40.4.5 Slave select (NSS) pin management
- 40.4.6 Communication formats
- 40.4.7 Configuration of SPI
- 40.4.8 Procedure for enabling SPI
- 40.4.9 Data transmission and reception procedures
- 40.4.10 SPI status flags
- 40.4.11 SPI error flags
- 40.4.12 NSS pulse mode
- 40.4.13 TI mode
- 40.4.14 CRC calculation
- 40.5 SPI interrupts
- 40.6 SPI registers
- 40.6.1 SPI control register 1 (SPIx_CR1)
- 40.6.2 SPI control register 2 (SPIx_CR2)
- 40.6.3 SPI status register (SPIx_SR)
- 40.6.4 SPI data register (SPIx_DR)
- 40.6.5 SPI CRC polynomial register (SPIx_CRCPR)
- 40.6.6 SPI Rx CRC register (SPIx_RXCRCR)
- 40.6.7 SPI Tx CRC register (SPIx_TXCRCR)
- 40.6.8 SPI register map
- 41 Serial audio interface (SAI)
- 41.1 Introduction
- 41.2 SAI main features
- 41.3 SAI implementation
- 41.4 SAI functional description
- 41.4.1 SAI block diagram
- 41.4.2 SAI pins and internal signals
- 41.4.3 Main SAI modes
- 41.4.4 SAI synchronization mode
- 41.4.5 Audio data size
- 41.4.6 Frame synchronization
- 41.4.7 Slot configuration
- 41.4.8 SAI clock generator
- 41.4.9 Internal FIFOs
- 41.4.10 AC’97 link controller
- 41.4.11 SPDIF output
- 41.4.12 Specific features
- 41.4.13 Error flags
- 41.4.14 Disabling the SAI
- 41.4.15 SAI DMA interface
- 41.5 SAI interrupts
- 41.6 SAI registers
- 41.6.1 Configuration register 1 (SAI_ACR1)
- 41.6.2 Configuration register 1 (SAI_BCR1)
- 41.6.3 Configuration register 2 (SAI_ACR2)
- 41.6.4 Configuration register 2 (SAI_BCR2)
- 41.6.5 Frame configuration register (SAI_AFRCR)
- 41.6.6 Frame configuration register (SAI_BFRCR)
- 41.6.7 Slot register (SAI_ASLOTR)
- 41.6.8 Slot register (SAI_BSLOTR)
- 41.6.9 Interrupt mask register (SAI_AIM)
- 41.6.10 Interrupt mask register (SAI_BIM)
- 41.6.11 Status register (SAI_ASR)
- 41.6.12 Status register (SAI_BSR)
- 41.6.13 Clear flag register (SAI_ACLRFR)
- 41.6.14 Clear flag register (SAI_BCLRFR)
- 41.6.15 Data register (SAI_ADR)
- 41.6.16 Data register (SAI_BDR)
- 41.6.17 SAI register map
- 42 Single Wire Protocol Master Interface (SWPMI)
- 42.1 Introduction
- 42.2 SWPMI main features
- 42.3 SWPMI functional description
- 42.4 SWPMI low-power modes
- 42.5 SWPMI interrupts
- 42.6 SWPMI registers
- 42.6.1 SWPMI Configuration/Control register (SWPMI_CR)
- 42.6.2 SWPMI Bitrate register (SWPMI_BRR)
- 42.6.3 SWPMI Interrupt and Status register (SWPMI_ISR)
- 42.6.4 SWPMI Interrupt Flag Clear register (SWPMI_ICR)
- 42.6.5 SWPMI Interrupt Enable register (SMPMI_IER)
- 42.6.6 SWPMI Receive Frame Length register (SWPMI_RFL)
- 42.6.7 SWPMI Transmit data register (SWPMI_TDR)
- 42.6.8 SWPMI Receive data register (SWPMI_RDR)
- 42.6.9 SWPMI Option register (SWPMI_OR)
- 42.6.10 SWPMI register map and reset value table
- 43 SD/SDIO/MMC card host interface (SDMMC)
- 43.1 SDMMC main features
- 43.2 SDMMC bus topology
- 43.3 SDMMC functional description
- Figure 467. SDMMC block diagram
- Table 226. SDMMC I/O definitions
- 43.3.1 SDMMC adapter
- Figure 468. SDMMC adapter
- Figure 469. Control unit
- Figure 470. SDMMC_CK clock dephasing (BYPASS = 0)
- Figure 471. SDMMC adapter command path
- Figure 472. Command path state machine (SDMMC)
- Figure 473. SDMMC command transfer
- Table 227. Command format
- Table 228. Short response format
- Table 229. Long response format
- Table 230. Command path status flags
- Figure 474. Data path
- Figure 475. Data path state machine (DPSM)
- Table 231. Data token format
- Table 232. DPSM flags
- Table 233. Transmit FIFO status flags
- Table 234. Receive FIFO status flags
- 43.3.2 SDMMC APB2 interface
- 43.4 Card functional description
- 43.4.1 Card identification mode
- 43.4.2 Card reset
- 43.4.3 Operating voltage range validation
- 43.4.4 Card identification process
- 43.4.5 Block write
- 43.4.6 Block read
- 43.4.7 Stream access, stream write and stream read (MultiMediaCard only)
- 43.4.8 Erase: group erase and sector erase
- 43.4.9 Wide bus selection or deselection
- 43.4.10 Protection management
- 43.4.11 Card status register
- 43.4.12 SD status register
- 43.4.13 SD I/O mode
- 43.4.14 Commands and responses
- 43.5 Response formats
- 43.6 SDIO I/O card-specific operations
- 43.7 HW flow control
- 43.8 SDMMC registers
- 43.8.1 SDMMC power control register (SDMMC_POWER)
- 43.8.2 SDMMC clock control register (SDMMC_CLKCR)
- 43.8.3 SDMMC argument register (SDMMC_ARG)
- 43.8.4 SDMMC command register (SDMMC_CMD)
- 43.8.5 SDMMC command response register (SDMMC_RESPCMD)
- 43.8.6 SDMMC response 1..4 register (SDMMC_RESPx)
- 43.8.7 SDMMC data timer register (SDMMC_DTIMER)
- 43.8.8 SDMMC data length register (SDMMC_DLEN)
- 43.8.9 SDMMC data control register (SDMMC_DCTRL)
- 43.8.10 SDMMC data counter register (SDMMC_DCOUNT)
- 43.8.11 SDMMC status register (SDMMC_STA)
- 43.8.12 SDMMC interrupt clear register (SDMMC_ICR)
- 43.8.13 SDMMC mask register (SDMMC_MASK)
- 43.8.14 SDMMC FIFO counter register (SDMMC_FIFOCNT)
- 43.8.15 SDMMC data FIFO register (SDMMC_FIFO)
- 43.8.16 SDMMC register map
- 44 Controller area network (bxCAN)
- 44.1 Introduction
- 44.2 bxCAN main features
- 44.3 bxCAN general description
- 44.4 bxCAN operating modes
- 44.5 Test mode
- 44.6 Behavior in debug mode
- 44.7 bxCAN functional description
- 44.8 bxCAN interrupts
- 44.9 CAN registers
- 45 Universal serial bus full-speed device interface (USB)
- 45.1 Introduction
- 45.2 USB main features
- 45.3 USB implementation
- 45.4 USB functional description
- 45.5 Programming considerations
- 45.6 USB and USB SRAM registers
- 46 Debug support (DBG)
- 46.1 Overview
- 46.2 Reference Arm® documentation
- 46.3 SWJ debug port (serial wire and JTAG)
- 46.4 Pinout and debug port pins
- 46.5 STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx JTAG TAP connection
- 46.6 ID codes and locking mechanism
- 46.7 JTAG debug port
- 46.8 SW debug port
- 46.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP
- 46.10 Core debug
- 46.11 Capability of the debugger host to connect under system reset
- 46.12 FPB (Flash patch breakpoint)
- 46.13 DWT (data watchpoint trigger)
- 46.14 ITM (instrumentation trace macrocell)
- 46.15 ETM (Embedded trace macrocell)
- 46.16 MCU debug component (DBGMCU)
- 46.16.1 Debug support for low-power modes
- 46.16.2 Debug support for timers, RTC, watchdog, bxCAN and I2C
- 46.16.3 Debug MCU configuration register (DBGMCU_CR)
- 46.16.4 Debug MCU APB1 freeze register1(DBGMCU_APB1FZR1)
- 46.16.5 Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)
- 46.16.6 Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
- 46.17 TPIU (trace port interface unit)
- 46.17.1 Introduction
- 46.17.2 TRACE pin assignment
- 46.17.3 TPUI formatter
- 46.17.4 TPUI frame synchronization packets
- 46.17.5 Transmission of the synchronization frame packet
- 46.17.6 Synchronous mode
- 46.17.7 Asynchronous mode
- 46.17.8 TRACECLKIN connection inside the STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx
- 46.17.9 TPIU registers
- 46.17.10 Example of configuration
- 46.18 DBG register map
- 47 Device electronic signature
- 48 Revision history