STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx Advanced Arm® Based 32 Bit MCUs Reference Manual STM32L4
STM32L4%20Reference%20manual
reference-manual-RM0394
reference-manual-RM0394
User Manual:
Open the PDF directly: View PDF .
Page Count: 1600
Download | ![]() |
Open PDF In Browser | View PDF |
RM0394 Reference manual STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx advanced Arm®-based 32-bit MCUs Introduction This reference manual targets application developers. It provides complete information on how to use the STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx microcontroller memory and peripherals. The STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx is a family of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets. For information on the Arm® Cortex®-M4 core, please refer to the Cortex®-M4 Technical Reference Manual. Related documents • Cortex®-M4 Technical Reference Manual, available from: http://infocenter.arm.com • STM32L412xx, STM32L422xx, STM32L431xx, STM32L432xx, STM32L433xx, STM32L442xx, STM32L443xx, STM32L451xx, STM32L452xx, STM32L462xx datasheets • STM32F3, STM32F4, STM32L4 and STM32L4+ Series Cortex®-M4 (PM0214) October 2018 RM0394 Rev 4 1/1600 www.st.com 1 Contents RM0394 Contents 1 2 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.4 Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.5 Product specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.1 2.2 3 2/1600 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.1.1 S0: I-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.1.2 S1: D-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.1.3 S2: S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.1.4 S3, S4: DMA-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.1.5 BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.2.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 67 2.3 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.4.1 SRAM2 parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.4.2 SRAM2 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.4.3 SRAM2 Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.4.4 SRAM2 Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.5 Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.6 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Embedded Flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.2 FLASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.3 FLASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.3.1 Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.3.2 Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.3.3 Read access latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 RM0394 Rev 4 RM0394 Contents 3.4 3.5 4 3.3.4 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 80 3.3.5 Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.3.6 Flash main memory erase sequences . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.3.7 Flash main memory programming sequences . . . . . . . . . . . . . . . . . . . . 84 FLASH option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.4.1 Option bytes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.4.2 Option bytes programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 FLASH memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.5.1 Read protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.5.2 Proprietary code readout protection (PCROP) . . . . . . . . . . . . . . . . . . . 97 3.5.3 Write protection (WRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.6 FLASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.7 FLASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.7.1 Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . 100 3.7.2 Flash Power-down key register (FLASH_PDKEYR) . . . . . . . . . . . . . . 101 3.7.3 Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.7.4 Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . 102 3.7.5 Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.7.6 Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.7.7 Flash ECC register (FLASH_ECCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.7.8 Flash option register (FLASH_OPTR) . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.7.9 Flash PCROP Start address register (FLASH_PCROP1SR) . . . . . . . 109 3.7.10 Flash PCROP End address register (FLASH_PCROP1ER) . . . . . . . . 109 3.7.11 Flash WRP area A address register (FLASH_WRP1AR) . . . . . . . . . . 110 3.7.12 Flash WRP area B address register (FLASH_WRP1BR) . . . . . . . . . . 110 3.7.13 FLASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Firewall (FW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 4.2 Firewall main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 4.3 Firewall functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 4.3.1 Firewall AMBA bus snoop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.3.2 Functional requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.3.3 Firewall segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.3.4 Segment accesses and properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.3.5 Firewall initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 RM0394 Rev 4 3/1600 43 Contents RM0394 4.3.6 4.4 5 Firewall registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.4.1 Code segment start address (FW_CSSA) . . . . . . . . . . . . . . . . . . . . . . 121 4.4.2 Code segment length (FW_CSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.4.3 Non-volatile data segment start address (FW_NVDSSA) . . . . . . . . . . 122 4.4.4 Non-volatile data segment length (FW_NVDSL) . . . . . . . . . . . . . . . . . 122 4.4.5 Volatile data segment start address (FW_VDSSA) . . . . . . . . . . . . . . . 123 4.4.6 Volatile data segment length (FW_VDSL) . . . . . . . . . . . . . . . . . . . . . . 123 4.4.7 Configuration register (FW_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.4.8 Firewall register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.1 5.2 5.3 4/1600 Firewall states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.1.1 Independent analog peripherals supply . . . . . . . . . . . . . . . . . . . . . . . . 128 5.1.2 Independent USB transceivers supply . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.1.3 Independent LCD supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.1.4 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.1.5 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.1.6 VDD12 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.1.7 Dynamic voltage scaling management . . . . . . . . . . . . . . . . . . . . . . . . 133 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.2.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 135 5.2.3 Peripheral Voltage Monitoring (PVM) . . . . . . . . . . . . . . . . . . . . . . . . . 136 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.3.1 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 5.3.2 Low-power run mode (LP run) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 5.3.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5.3.4 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.3.5 Low-power sleep mode (LP sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.3.6 Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.3.7 Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 5.3.8 Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.3.9 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 5.3.10 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 5.3.11 Auto-wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . 157 RM0394 Rev 4 RM0394 Contents 5.4 6 PWR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.4.1 Power control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.4.2 Power control register 2 (PWR_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.4.3 Power control register 3 (PWR_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . 160 5.4.4 Power control register 4 (PWR_CR4) . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.4.5 Power status register 1 (PWR_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.4.6 Power status register 2 (PWR_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.4.7 Power status clear register (PWR_SCR) . . . . . . . . . . . . . . . . . . . . . . . 165 5.4.8 Power Port A pull-up control register (PWR_PUCRA) . . . . . . . . . . . . . 166 5.4.9 Power Port A pull-down control register (PWR_PDCRA) . . . . . . . . . . 166 5.4.10 Power Port B pull-up control register (PWR_PUCRB) . . . . . . . . . . . . . 167 5.4.11 Power Port B pull-down control register (PWR_PDCRB) . . . . . . . . . . 167 5.4.12 Power Port C pull-up control register (PWR_PUCRC) . . . . . . . . . . . . 168 5.4.13 Power Port C pull-down control register (PWR_PDCRC) . . . . . . . . . . 168 5.4.14 Power Port D pull-up control register (PWR_PUCRD) . . . . . . . . . . . . 169 5.4.15 Power Port D pull-down control register (PWR_PDCRD) . . . . . . . . . . 169 5.4.16 Power Port E pull-up control register (PWR_PUCRE) . . . . . . . . . . . . . 170 5.4.17 Power Port E pull-down control register (PWR_PDCRE) . . . . . . . . . . 170 5.4.18 Power Port H pull-up control register (PWR_PUCRH) . . . . . . . . . . . . 171 5.4.19 Power Port H pull-down control register (PWR_PDCRH) . . . . . . . . . . 171 5.4.20 PWR register map and reset value table . . . . . . . . . . . . . . . . . . . . . . . 173 Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.1 6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.1.1 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.1.2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 6.2.2 HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 6.2.3 MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 6.2.4 HSI48 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 6.2.5 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 6.2.6 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.2.7 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.2.8 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.2.9 Clock source frequency versus voltage scaling . . . . . . . . . . . . . . . . . . 186 RM0394 Rev 4 5/1600 43 Contents 6/1600 RM0394 6.2.10 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 6.2.11 Clock security system on LSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.2.12 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.2.13 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.2.14 Timer clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6.2.15 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6.2.16 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 6.2.17 Internal/external clock measurement with TIM15/TIM16 . . . . . . . . . . . 189 6.2.18 Peripheral clock enable register (RCC_AHBxENR, RCC_APBxENRy) . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.4 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.4.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.4.2 Internal clock sources calibration register (RCC_ICSCR) . . . . . . . . . . 196 6.4.3 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 196 6.4.4 PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . . . . . 198 6.4.5 PLLSAI1 configuration register (RCC_PLLSAI1CFGR) . . . . . . . . . . . 201 6.4.6 Clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . . . . . 204 6.4.7 Clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . . . . . 206 6.4.8 Clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . . . . . 207 6.4.9 AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . . . . . 208 6.4.10 AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . . . . . 209 6.4.11 AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . . . . . 211 6.4.12 APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . . . . . . . . . 211 6.4.13 APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . . . . . . . . . 214 6.4.14 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 215 6.4.15 AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . . . . . 216 6.4.16 AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . . . . . 218 6.4.17 AHB3 peripheral clock enable register(RCC_AHB3ENR) . . . . . . . . . . 219 6.4.18 APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . . . . 220 6.4.19 APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . . . . 222 6.4.20 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 224 6.4.21 AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 6.4.22 AHB2 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 6.4.23 AHB3 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 RM0394 Rev 4 RM0394 7 8 Contents 6.4.24 APB1 peripheral clocks enable in Sleep and Stop modes register 1 (RCC_APB1SMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 6.4.25 APB1 peripheral clocks enable in Sleep and Stop modes register 2 (RCC_APB1SMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 6.4.26 APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 6.4.27 Peripherals independent clock configuration register (RCC_CCIPR) . 234 6.4.28 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 237 6.4.29 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 6.4.30 Clock recovery RC register (RCC_CRRCR) . . . . . . . . . . . . . . . . . . . . 241 6.4.31 Peripherals independent clock configuration register (RCC_CCIPR2) 242 6.4.32 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 7.2 CRS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 7.3 CRS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 7.3.1 CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 7.3.2 Synchronization input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 7.3.3 Frequency error measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 7.3.4 Frequency error evaluation and automatic trimming . . . . . . . . . . . . . . 250 7.3.5 CRS initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 7.4 CRS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 7.5 CRS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 7.6 CRS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 7.6.1 CRS control register (CRS_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 7.6.2 CRS configuration register (CRS_CFGR) . . . . . . . . . . . . . . . . . . . . . . 253 7.6.3 CRS interrupt and status register (CRS_ISR) . . . . . . . . . . . . . . . . . . . 254 7.6.4 CRS interrupt flag clear register (CRS_ICR) . . . . . . . . . . . . . . . . . . . . 256 7.6.5 CRS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 8.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 8.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 8.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 8.3.2 I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 261 RM0394 Rev 4 7/1600 43 Contents RM0394 8.4 9 8/1600 8.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 8.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 8.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 8.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 8.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 8.3.8 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 8.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 8.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 8.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 8.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 8.3.13 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 266 8.3.14 Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 266 8.3.15 Using PH3 as GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 8.4.1 GPIO port mode register (GPIOx_MODER) (x =A to E and H) . . . . . . 267 8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A to E and H) 268 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A to E and H) . . . . . . 269 8.4.6 GPIO port output data register (GPIOx_ODR) (x = A to E and H) . . . . 269 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A to E and H) . . 270 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to E and H) . . . . . . 273 8.4.12 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 276 9.1 SYSCFG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.2 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . . . . . . 276 9.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 277 9.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 RM0394 Rev 4 RM0394 10 Contents 9.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 9.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 9.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 9.2.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR) . . . . 284 9.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 285 9.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR) . . . . . . 286 9.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . . . . . . . . . . . . . . 286 9.2.11 SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 10.2 Connection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 10.3 Interconnection details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 10.3.1 From timer (TIM1/TIM2/TIM15/TIM16) to timer (TIM1/TIM2/TIM15/TIM16) 289 10.3.2 From timer (TIM1/TIM2/TIM6/TIM15) and EXTI to ADC (ADC1) . . . . . 290 10.3.3 From ADC (ADC1) to timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 10.3.4 From timer (TIM2/TIM6/TIM7) and EXTI to DAC (DAC1/DAC2) . . . . . 290 10.3.5 From HSE, LSE, LSI, MSI, MCO, RTC to timer (TIM2/TIM15/TIM16) . 291 10.3.6 From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2) . . 291 10.3.7 From timer (TIM1/TIM2/TIM15) to comparators (COMP1/COMP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.3.8 From ADC (ADC1) to ADC (ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.3.9 From USB to timer (TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.3.10 From internal analog source to ADC (ADC1) and OPAMP (OPAMP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 10.3.11 From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM15/TIM16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 10.3.12 From system errors to timers (TIM1/TIM15/TIM16) . . . . . . . . . . . . . . . 294 10.3.13 From timers (TIM16) to IRTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 295 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 11.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 11.3 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 11.3.1 DMA1 and DMA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 RM0394 Rev 4 9/1600 43 Contents RM0394 11.3.2 11.4 12 13 10/1600 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 11.4.1 DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 11.4.2 DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 11.4.3 DMA arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 11.4.4 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 11.4.5 DMA data width, alignment and endianness . . . . . . . . . . . . . . . . . . . . 306 11.4.6 DMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 11.5 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 11.6 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 11.6.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 308 11.6.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 311 11.6.3 DMA channel x configuration register (DMA_CCRx) . . . . . . . . . . . . . . 312 11.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx) . 315 11.6.5 DMA channel x peripheral address register (DMA_CPARx) . . . . . . . . 315 11.6.6 DMA channel x memory address register (DMA_CMARx) . . . . . . . . . 316 11.6.7 DMA channel selection register (DMA_CSELR) . . . . . . . . . . . . . . . . . 317 11.6.8 DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 320 12.1 NVIC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 12.2 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 12.3 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . 325 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 13.2 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 13.3 EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 13.3.1 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 13.3.2 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 13.3.3 Peripherals asynchronous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.3.4 Hardware interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.3.5 Hardware event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.3.6 Software interrupt/event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.4 EXTI interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.5 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 RM0394 Rev 4 RM0394 Contents 13.5.1 Interrupt mask register 1 (EXTI_IMR1) . . . . . . . . . . . . . . . . . . . . . . . . 330 13.5.2 Event mask register 1 (EXTI_EMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 330 13.5.3 Rising trigger selection register 1 (EXTI_RTSR1) . . . . . . . . . . . . . . . . 331 13.5.4 Falling trigger selection register 1 (EXTI_FTSR1) . . . . . . . . . . . . . . . . 331 13.5.5 Software interrupt event register 1 (EXTI_SWIER1) . . . . . . . . . . . . . . 332 13.5.6 Pending register 1 (EXTI_PR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 13.5.7 Interrupt mask register 2 (EXTI_IMR2) . . . . . . . . . . . . . . . . . . . . . . . . 333 13.5.8 Event mask register 2 (EXTI_EMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 334 13.5.9 Rising trigger selection register 2 (EXTI_RTSR2) . . . . . . . . . . . . . . . . 334 13.5.10 Falling trigger selection register 2 (EXTI_FTSR2) . . . . . . . . . . . . . . . . 335 13.5.11 Software interrupt event register 2 (EXTI_SWIER2) . . . . . . . . . . . . . . 335 13.5.12 Pending register 2 (EXTI_PR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 13.5.13 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 14 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 338 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 14.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 14.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 14.4 15 14.3.1 CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 14.3.2 CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 14.3.3 CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 14.4.1 Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 14.4.2 Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . 341 14.4.3 Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 14.4.4 Initial CRC value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 14.4.5 CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 14.4.6 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 Quad-SPI interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 15.2 QUADSPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 15.3 QUADSPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 15.3.1 QUADSPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 15.3.2 QUADSPI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 15.3.3 QUADSPI command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 RM0394 Rev 4 11/1600 43 Contents RM0394 15.3.4 QUADSPI signal interface protocol modes . . . . . . . . . . . . . . . . . . . . . 348 15.3.5 QUADSPI indirect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 15.3.6 QUADSPI status flag polling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 15.3.7 QUADSPI memory-mapped mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 15.3.8 QUADSPI Flash memory configuration . . . . . . . . . . . . . . . . . . . . . . . . 353 15.3.9 QUADSPI delayed data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 15.3.10 QUADSPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 15.3.11 QUADSPI usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 15.3.12 Sending the instruction only once . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 15.3.13 QUADSPI error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 15.3.14 QUADSPI busy bit and abort functionality . . . . . . . . . . . . . . . . . . . . . . 357 15.3.15 nCS behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 15.4 QUADSPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 15.5 QUADSPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 15.5.1 QUADSPI control register (QUADSPI_CR) . . . . . . . . . . . . . . . . . . . . . 360 15.5.2 QUADSPI device configuration register (QUADSPI_DCR) . . . . . . . . . 363 15.5.3 QUADSPI status register (QUADSPI_SR) . . . . . . . . . . . . . . . . . . . . . 364 15.5.4 QUADSPI flag clear register (QUADSPI_FCR) . . . . . . . . . . . . . . . . . . 365 15.5.5 QUADSPI data length register (QUADSPI_DLR) . . . . . . . . . . . . . . . . 365 15.5.6 QUADSPI communication configuration register (QUADSPI_CCR) . . 366 15.5.7 QUADSPI address register (QUADSPI_AR) . . . . . . . . . . . . . . . . . . . . 368 15.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR) . . . . . . . . . . . . 369 15.5.9 QUADSPI data register (QUADSPI_DR) . . . . . . . . . . . . . . . . . . . . . . . 369 15.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR) . . . . . . . 370 15.5.11 QUADSPI polling status match register (QUADSPI _PSMAR) . . . . . . 370 15.5.12 QUADSPI polling interval register (QUADSPI _PIR) . . . . . . . . . . . . . . 371 15.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR) . . . . . . . . . . 371 15.5.14 QUADSPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 16 12/1600 Analog-to-digital converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 16.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 16.3 ADC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 16.4 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 16.4.1 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 16.4.2 ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 RM0394 Rev 4 RM0394 Contents 16.4.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 16.4.4 ADC1/2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 16.4.5 Slave AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 16.4.6 ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 16.4.7 Single-ended and differential input channels . . . . . . . . . . . . . . . . . . . . 383 16.4.8 Calibration (ADCAL, ADCALDIF, ADC_CALFACT) . . . . . . . . . . . . . . . 383 16.4.9 ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . 386 16.4.10 Constraints when writing the ADC control bits . . . . . . . . . . . . . . . . . . . 387 16.4.11 Channel selection (SQRx, JSQRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 16.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . . 389 16.4.13 Single conversion mode (CONT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 16.4.14 Continuous conversion mode (CONT=1) . . . . . . . . . . . . . . . . . . . . . . . 390 16.4.15 Starting conversions (ADSTART, JADSTART) . . . . . . . . . . . . . . . . . . . 391 16.4.16 ADC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 16.4.17 Stopping an ongoing conversion (ADSTP, JADSTP) . . . . . . . . . . . . . . 392 16.4.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN,JEXTSEL, JEXTEN) . . . . . . . . . . . . . . . . . . . . . . . 394 16.4.19 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 16.4.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . . . . . . . . . 398 16.4.21 Queue of context for injected conversions . . . . . . . . . . . . . . . . . . . . . . 399 16.4.22 Programmable resolution (RES) - fast conversion mode . . . . . . . . . . 407 16.4.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . 408 16.4.24 End of conversion sequence (EOS, JEOS) . . . . . . . . . . . . . . . . . . . . . 408 16.4.25 Timing diagrams example (single/continuous modes, hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 16.4.26 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 16.4.27 Managing conversions using the DFSDM . . . . . . . . . . . . . . . . . . . . . . 416 16.4.28 Dynamic low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 16.4.29 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . 422 16.4.30 Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 16.4.31 Dual ADC modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 16.4.32 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 16.4.33 VBAT supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 16.4.34 Monitoring the internal voltage reference . . . . . . . . . . . . . . . . . . . . . . 448 16.5 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 16.6 ADC registers (for each ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 RM0394 Rev 4 13/1600 43 Contents RM0394 16.6.1 ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . 451 16.6.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 453 16.6.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 16.6.4 ADC configuration register (ADC_CFGR) . . . . . . . . . . . . . . . . . . . . . . 458 16.6.5 ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . . 462 16.6.6 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 464 16.6.7 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 465 16.6.8 ADC watchdog threshold register 1 (ADC_TR1) . . . . . . . . . . . . . . . . . 465 16.6.9 ADC watchdog threshold register 2 (ADC_TR2) . . . . . . . . . . . . . . . . . 466 16.6.10 ADC watchdog threshold register 3 (ADC_TR3) . . . . . . . . . . . . . . . . . 467 16.6.11 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 468 16.6.12 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 469 16.6.13 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 470 16.6.14 ADC regular sequence register 4 (ADC_SQR4) . . . . . . . . . . . . . . . . . 471 16.6.15 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 471 16.6.16 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 472 16.6.17 ADC offset y register (ADC_OFRy) . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 16.6.18 ADC injected channel y data register (ADC_JDRy) . . . . . . . . . . . . . . . 474 16.6.19 ADC Analog Watchdog 2 Configuration Register (ADC_AWD2CR) . . 475 16.6.20 ADC Analog Watchdog 3 Configuration Register (ADC_AWD3CR) . . 475 16.6.21 ADC Differential mode Selection Register (ADC_DIFSEL) . . . . . . . . . 476 16.6.22 ADC Calibration Factors (ADC_CALFACT) . . . . . . . . . . . . . . . . . . . . . 476 16.7 17 14/1600 ADC common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 16.7.1 ADC common status register (ADC_CSR) . . . . . . . . . . . . . . . . . . . . . 477 16.7.2 ADC common control register (ADC_CCR) . . . . . . . . . . . . . . . . . . . . 479 16.7.3 Common regular data register for dual mode (ADC_CDR) . . . . . . . . . 482 16.7.4 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 17.2 DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 17.3 DAC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 17.4 DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 17.4.1 DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 17.4.2 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 17.4.3 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 17.4.4 DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 RM0394 Rev 4 RM0394 Contents 17.4.5 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 17.4.6 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 17.4.7 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 17.4.8 Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 17.4.9 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 17.4.10 DAC channel modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 17.4.11 DAC channel buffer calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 17.4.12 Dual DAC channel conversion (if available) . . . . . . . . . . . . . . . . . . . . 499 17.5 DAC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 17.6 DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 17.7 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 17.7.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 17.7.2 DAC software trigger register (DAC_SWTRGR) . . . . . . . . . . . . . . . . . 508 17.7.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 17.7.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 17.7.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 17.7.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 17.7.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 17.7.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 17.7.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 17.7.10 Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 17.7.11 Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 17.7.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 512 17.7.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 513 17.7.14 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 17.7.15 DAC calibration control register (DAC_CCR) . . . . . . . . . . . . . . . . . . . 515 17.7.16 DAC mode control register (DAC_MCR) . . . . . . . . . . . . . . . . . . . . . . . 515 17.7.17 DAC channel 1 sample and hold sample time register (DAC_SHSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 17.7.18 DAC channel 2 sample and hold sample time register (DAC_SHSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 RM0394 Rev 4 15/1600 43 Contents RM0394 17.7.19 DAC sample and hold time register (DAC_SHHR) . . . . . . . . . . . . . . . 518 17.7.20 DAC sample and hold refresh time register (DAC_SHRR) . . . . . . . . . 518 17.7.21 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 18 19 20 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . 522 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 18.2 VREFBUF functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 18.3 VREFBUF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 18.3.1 VREFBUF control and status register (VREFBUF_CSR) . . . . . . . . . . 523 18.3.2 VREFBUF calibration control register (VREFBUF_CCR) . . . . . . . . . . 524 18.3.3 VREFBUF register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 19.2 COMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 19.3 COMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 19.3.1 COMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 19.3.2 COMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 19.3.3 COMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 19.3.4 Comparator LOCK mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 19.3.5 Window comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 19.3.6 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 19.3.7 Comparator output blanking function . . . . . . . . . . . . . . . . . . . . . . . . . . 530 19.3.8 COMP power and speed modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 19.4 COMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 19.5 COMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 19.6 COMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 19.6.1 Comparator 1 control and status register (COMP1_CSR) . . . . . . . . . . 532 19.6.2 Comparator 2 control and status register (COMP2_CSR) . . . . . . . . . . 534 19.6.3 COMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 20.2 OPAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 20.3 OPAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 20.3.1 16/1600 OPAMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 RM0394 Rev 4 RM0394 21 Contents 20.3.2 Initial configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 20.3.3 Signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 20.3.4 OPAMP modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 20.3.5 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 20.4 OPAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 20.5 OPAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 20.5.1 OPAMP1 control/status register (OPAMP1_CSR) . . . . . . . . . . . . . . . . 546 20.5.2 OPAMP1 offset trimming register in normal mode (OPAMP1_OTR) . . 547 20.5.3 OPAMP1 offset trimming register in low-power mode (OPAMP1_LPOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 20.5.4 OPAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 Digital filter for sigma delta modulators (DFSDM) . . . . . . . . . . . . . . . 549 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 21.2 DFSDM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 21.3 DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 21.4 DFSDM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 21.4.1 DFSDM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 21.4.2 DFSDM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 21.4.3 DFSDM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 21.4.4 Serial channel transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 21.4.5 Configuring the input serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . 564 21.4.6 Parallel data inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 21.4.7 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 21.4.8 Digital filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 21.4.9 Integrator unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 21.4.10 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 21.4.11 Short-circuit detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 21.4.12 Extreme detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 21.4.13 Data unit block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 21.4.14 Signed data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 21.4.15 Launching conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 21.4.16 Continuous and fast continuous modes . . . . . . . . . . . . . . . . . . . . . . . . 574 21.4.17 Request precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 21.4.18 Power optimization in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 21.5 DFSDM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 RM0394 Rev 4 17/1600 43 Contents RM0394 21.6 DFSDM DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 21.7 DFSDM channel y registers (y=0..3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 21.8 21.7.1 DFSDM channel y configuration register (DFSDM_CHyCFGR1) . . . . 577 21.7.2 DFSDM channel y configuration register (DFSDM_CHyCFGR2) . . . . 580 21.7.3 DFSDM channel y analog watchdog and short-circuit detector register (DFSDM_CHyAWSCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 21.7.4 DFSDM channel y watchdog filter data register (DFSDM_CHyWDATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 21.7.5 DFSDM channel y data input register (DFSDM_CHyDATINR) . . . . . . 582 DFSDM filter x module registers (x=0..1) . . . . . . . . . . . . . . . . . . . . . . . . 583 21.8.1 DFSDM filter x control register 1 (DFSDM_FLTxCR1) . . . . . . . . . . . . 583 21.8.2 DFSDM filter x control register 2 (DFSDM_FLTxCR2) . . . . . . . . . . . . 585 21.8.3 DFSDM filter x interrupt and status register (DFSDM_FLTxISR) . . . . . 587 21.8.4 DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) . . . . . 588 21.8.5 DFSDM filter x injected channel group selection register (DFSDM_FLTxJCHGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 21.8.6 DFSDM filter x control register (DFSDM_FLTxFCR) . . . . . . . . . . . . . . 590 21.8.7 DFSDM filter x data register for injected group (DFSDM_FLTxJDATAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 21.8.8 DFSDM filter x data register for the regular channel (DFSDM_FLTxRDATAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 21.8.9 DFSDM filter x analog watchdog high threshold register (DFSDM_FLTxAWHTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 21.8.10 DFSDM filter x analog watchdog low threshold register (DFSDM_FLTxAWLTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 21.8.11 DFSDM filter x analog watchdog status register (DFSDM_FLTxAWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 21.8.12 DFSDM filter x analog watchdog clear flag register (DFSDM_FLTxAWCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 21.8.13 DFSDM filter x extremes detector maximum register (DFSDM_FLTxEXMAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 21.8.14 DFSDM filter x extremes detector minimum register (DFSDM_FLTxEXMIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 21.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . . 596 21.8.16 DFSDM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 22 18/1600 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . 602 22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 22.2 LCD main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 22.3 LCD functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 RM0394 Rev 4 RM0394 23 Contents 22.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 22.3.2 Frequency generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 22.3.3 Common driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 22.3.4 Segment driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 22.3.5 Voltage generator and contrast control . . . . . . . . . . . . . . . . . . . . . . . . 613 22.3.6 Double buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 22.3.7 COM and SEG multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 22.3.8 Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 22.4 LCD low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 22.5 LCD interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 22.6 LCD registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 22.6.1 LCD control register (LCD_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 22.6.2 LCD frame control register (LCD_FCR) . . . . . . . . . . . . . . . . . . . . . . . . 626 22.6.3 LCD status register (LCD_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 22.6.4 LCD clear register (LCD_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 22.6.5 LCD display memory (LCD_RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 22.6.6 LCD register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 23.2 TSC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 23.3 TSC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 23.3.1 TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 23.3.2 Surface charge transfer acquisition overview . . . . . . . . . . . . . . . . . . . 635 23.3.3 Reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 23.3.4 Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . 638 23.3.5 Spread spectrum feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 23.3.6 Max count error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 23.3.7 Sampling capacitor I/O and channel I/O mode selection . . . . . . . . . . . 640 23.3.8 Acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 23.3.9 I/O hysteresis and analog switch control . . . . . . . . . . . . . . . . . . . . . . . 641 23.4 TSC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 23.5 TSC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 23.6 TSC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 23.6.1 TSC control register (TSC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 23.6.2 TSC interrupt enable register (TSC_IER) . . . . . . . . . . . . . . . . . . . . . . 645 RM0394 Rev 4 19/1600 43 Contents RM0394 23.6.3 TSC interrupt clear register (TSC_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 646 23.6.4 TSC interrupt status register (TSC_ISR) . . . . . . . . . . . . . . . . . . . . . . . 647 23.6.5 TSC I/O hysteresis control register (TSC_IOHCR) . . . . . . . . . . . . . . . 647 23.6.6 TSC I/O analog switch control register (TSC_IOASCR) . . . . . . . . . . . 648 23.6.7 TSC I/O sampling control register (TSC_IOSCR) . . . . . . . . . . . . . . . . 648 23.6.8 TSC I/O channel control register (TSC_IOCCR) . . . . . . . . . . . . . . . . . 649 23.6.9 TSC I/O group control status register (TSC_IOGCSR) . . . . . . . . . . . . 649 23.6.10 TSC I/O group x counter register (TSC_IOGxCR) . . . . . . . . . . . . . . . . 650 23.6.11 TSC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 24 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . 653 24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 24.2 RNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 24.3 RNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 20/1600 RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 24.3.2 RNG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 24.3.3 Random number generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 24.3.4 RNG initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 24.3.5 RNG operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 24.3.6 RNG clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 24.3.7 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 24.4 RNG low-power usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 24.5 RNG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 24.6 RNG processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 24.7 Entropy source validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 24.8 25 24.3.1 24.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 24.7.2 Validation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 RNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 24.8.1 RNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 24.8.2 RNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 24.8.3 RNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 24.8.4 RNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 AES hardware accelerator (AES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 25.2 AES main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 RM0394 Rev 4 RM0394 Contents 25.3 AES implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 25.4 AES functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 25.4.1 AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 25.4.2 AES internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 25.4.3 AES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 25.4.4 AES procedure to perform a cipher operation . . . . . . . . . . . . . . . . . . . 672 25.4.5 AES decryption key preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 25.4.6 AES ciphertext stealing and data padding . . . . . . . . . . . . . . . . . . . . . . 677 25.4.7 AES task suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 25.4.8 AES basic chaining modes (ECB, CBC) . . . . . . . . . . . . . . . . . . . . . . . 679 25.4.9 AES counter (CTR) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 25.4.10 AES Galois/counter mode (GCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 25.4.11 AES Galois message authentication code (GMAC) . . . . . . . . . . . . . . 691 25.4.12 AES counter with CBC-MAC (CCM) . . . . . . . . . . . . . . . . . . . . . . . . . . 693 25.4.13 .AES data registers and data swapping . . . . . . . . . . . . . . . . . . . . . . . . 698 25.4.14 AES key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 25.4.15 AES initialization vector registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 25.4.16 AES DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 25.4.17 AES error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 25.5 AES interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 25.6 AES processing latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 25.7 AES registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 25.7.1 AES control register (AES_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 25.7.2 AES status register (AES_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 25.7.3 AES data input register (AES_DINR) . . . . . . . . . . . . . . . . . . . . . . . . . 709 25.7.4 AES data output register (AES_DOUTR) . . . . . . . . . . . . . . . . . . . . . . 710 25.7.5 AES key register 0 (AES_KEYR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710 25.7.6 AES key register 1 (AES_KEYR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 25.7.7 AES key register 2 (AES_KEYR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 25.7.8 AES key register 3 (AES_KEYR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 25.7.9 AES initialization vector register 0 (AES_IVR0) . . . . . . . . . . . . . . . . . . 712 25.7.10 AES initialization vector register 1 (AES_IVR1) . . . . . . . . . . . . . . . . . . 712 25.7.11 AES initialization vector register 2 (AES_IVR2) . . . . . . . . . . . . . . . . . . 713 25.7.12 AES initialization vector register 3 (AES_IVR3) . . . . . . . . . . . . . . . . . . 713 25.7.13 AES key register 4 (AES_KEYR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 25.7.14 AES key register 5 (AES_KEYR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 RM0394 Rev 4 21/1600 43 Contents RM0394 25.7.15 AES key register 6 (AES_KEYR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 25.7.16 AES key register 7 (AES_KEYR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 25.7.17 AES suspend registers (AES_SUSPxR) . . . . . . . . . . . . . . . . . . . . . . . 715 25.7.18 AES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 26 Advanced-control timers (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 26.1 TIM1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 26.2 TIM1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 26.3 TIM1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 26.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 26.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 26.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 26.3.4 External trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 26.3.5 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 26.3.6 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 26.3.7 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 26.3.8 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 26.3.9 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 26.3.10 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 26.3.11 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 26.3.12 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 26.3.13 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 26.3.14 Combined 3-phase PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 26.3.15 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 754 26.3.16 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756 26.3.17 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 26.3.18 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 763 26.3.19 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 26.3.20 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 26.3.21 Retriggerable one pulse mode (OPM) . . . . . . . . . . . . . . . . . . . . . . . . . 766 26.3.22 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 26.3.23 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 26.3.24 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 26.3.25 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 26.3.26 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 26.3.27 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 26.3.28 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 22/1600 RM0394 Rev 4 RM0394 Contents 26.3.29 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 26.4 TIM1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 26.4.1 TIM1 control register 1 (TIM1_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 779 26.4.2 TIM1 control register 2 (TIM1_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 780 26.4.3 TIM1 slave mode control register (TIM1_SMCR) . . . . . . . . . . . . . . . . 783 26.4.4 TIM1 DMA/interrupt enable register (TIM1_DIER) . . . . . . . . . . . . . . . 785 26.4.5 TIM1 status register (TIM1_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 26.4.6 TIM1 event generation register (TIM1_EGR) . . . . . . . . . . . . . . . . . . . 789 26.4.7 TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 26.4.8 TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791 26.4.9 TIM1 capture/compare mode register 2 [alternate] (TIM1_CCMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 26.4.10 TIM1 capture/compare mode register 2 [alternate] (TIM1_CCMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 26.4.11 TIM1 capture/compare enable register (TIM1_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 26.4.12 TIM1 counter (TIM1_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 26.4.13 TIM1 prescaler (TIM1_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 26.4.14 TIM1 auto-reload register (TIM1_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 800 26.4.15 TIM1 repetition counter register (TIM1_RCR) . . . . . . . . . . . . . . . . . . . 801 26.4.16 TIM1 capture/compare register 1 (TIM1_CCR1) . . . . . . . . . . . . . . . . . 801 26.4.17 TIM1 capture/compare register 2 (TIM1_CCR2) . . . . . . . . . . . . . . . . . 802 26.4.18 TIM1 capture/compare register 3 (TIM1_CCR3) . . . . . . . . . . . . . . . . . 802 26.4.19 TIM1 capture/compare register 4 (TIM1_CCR4) . . . . . . . . . . . . . . . . . 803 26.4.20 TIM1 break and dead-time register (TIM1_BDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 26.4.21 TIM1 DMA control register (TIM1_DCR) . . . . . . . . . . . . . . . . . . . . . . . 806 26.4.22 TIM1 DMA address for full transfer (TIM1_DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 26.4.23 TIM1 option register 1 (TIM1_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 26.4.24 TIM1 capture/compare mode register 3 (TIM1_CCMR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 26.4.25 TIM1 capture/compare register 5 (TIM1_CCR5) . . . . . . . . . . . . . . . . . 809 26.4.26 TIM1 capture/compare register 6 (TIM1_CCR6) . . . . . . . . . . . . . . . . . 810 26.4.27 TIM1 option register 2 (TIM1_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 26.4.28 TIM1 option register 3 (TIM1_OR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 812 26.4.29 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 RM0394 Rev 4 23/1600 43 Contents 27 RM0394 General-purpose timers (TIM2/TIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . 817 27.1 TIM2/TIM3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 27.2 TIM2/TIM3 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 27.3 TIM2/TIM3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 27.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 27.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 27.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 27.3.4 Capture/Compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 27.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 27.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 27.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 27.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 27.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 27.3.10 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 27.3.11 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 27.3.12 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 846 27.3.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 27.3.14 Retriggerable one pulse mode (OPM) . . . . . . . . . . . . . . . . . . . . . . . . . 849 27.3.15 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 27.3.16 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 27.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 27.3.18 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 853 27.3.19 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856 27.3.20 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 27.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 27.4 TIM2/TIM3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 27.4.1 TIMx control register 1 (TIMx_CR1)(x = 2 to 3) . . . . . . . . . . . . . . . . . . 862 27.4.2 TIMx control register 2 (TIMx_CR2)(x = 2 to 3) . . . . . . . . . . . . . . . . . . 863 27.4.3 TIMx slave mode control register (TIMx_SMCR)(x = 2 to 3) . . . . . . . . 865 27.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 3) . . . . . . . 868 27.4.5 TIMx status register (TIMx_SR)(x = 2 to 3) . . . . . . . . . . . . . . . . . . . . . 869 27.4.6 TIMx event generation register (TIMx_EGR)(x = 2 to 3) . . . . . . . . . . . 870 27.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 3) . . 871 27.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 3) . . 875 27.4.9 TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 3) . . . . 877 27.4.10 TIMx counter (TIMx_CNT)(x = 2 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . 878 24/1600 RM0394 Rev 4 RM0394 Contents 27.4.11 TIMx prescaler (TIMx_PSC)(x = 2 to 3) . . . . . . . . . . . . . . . . . . . . . . . . 879 27.4.12 TIMx auto-reload register (TIMx_ARR)(x = 2 to 3) . . . . . . . . . . . . . . . 879 27.4.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 3) . . . . . . . . 880 27.4.14 TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 3) . . . . . . . . 880 27.4.15 TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 3) . . . . . . . . 881 27.4.16 TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 3) . . . . . . . . 881 27.4.17 TIMx DMA control register (TIMx_DCR)(x = 2 to 3) . . . . . . . . . . . . . . . 882 27.4.18 TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 3) . . . . . . . 882 27.4.19 TIM2 option register 1 (TIM2_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 27.4.20 TIM2 option register 2 (TIM2_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 27.4.21 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884 28 General-purpose timers (TIM15/TIM16) . . . . . . . . . . . . . . . . . . . . . . . . 887 28.1 TIM15/TIM16 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887 28.2 TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887 28.3 TIM16 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888 28.4 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890 28.5 TIM15/TIM16 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891 28.5.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891 28.5.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 28.5.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897 28.5.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898 28.5.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 28.5.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902 28.5.7 PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903 28.5.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 28.5.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905 28.5.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906 28.5.11 Combined PWM mode (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . . . 907 28.5.12 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 908 28.5.13 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910 28.5.14 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915 28.5.15 Retriggerable one pulse mode (OPM) (TIM15 only) . . . . . . . . . . . . . . 916 28.5.16 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917 28.5.17 Timer input XOR function (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . 918 28.5.18 External trigger synchronization (TIM15 only) . . . . . . . . . . . . . . . . . . . 919 28.5.19 Slave mode – combined reset + trigger mode . . . . . . . . . . . . . . . . . . . 921 RM0394 Rev 4 25/1600 43 Contents RM0394 28.5.20 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921 28.5.21 Timer synchronization (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 28.5.22 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 28.6 TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924 28.6.1 TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 924 28.6.2 TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 925 28.6.3 TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . . 927 28.6.4 TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . . 928 28.6.5 TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 28.6.6 TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . . 931 28.6.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . . . . . 932 28.6.8 TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . . 936 28.6.9 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 28.6.10 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 28.6.11 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . . 939 28.6.12 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . . 940 28.6.13 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . . 940 28.6.14 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . . 941 28.6.15 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . . 941 28.6.16 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . . 943 28.6.17 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . . 944 28.6.18 TIM15 option register 1 (TIM15_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . 944 28.6.19 TIM15 option register 2 (TIM15_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . 945 28.6.20 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946 28.7 TIM16 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949 28.7.1 TIM16 control register 1 (TIM16_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 949 28.7.2 TIM16 control register 2 (TIM16_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 950 28.7.3 TIM16 DMA/interrupt enable register (TIM16_DIER) . . . . . . . . . . . . . 951 28.7.4 TIM16 status register (TIM16_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 952 28.7.5 TIM16 event generation register (TIM16_EGR) . . . . . . . . . . . . . . . . . 953 28.7.6 TIM16 capture/compare mode register 1 (TIM16_CCMR1) . . . . . . . . 954 28.7.7 TIM16 capture/compare enable register (TIM16_CCER) . . . . . . . . . . 956 28.7.8 TIM16 counter (TIM16_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 28.7.9 TIM16 prescaler (TIM16_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959 28.7.10 TIM16 auto-reload register (TIM16_ARR) . . . . . . . . . . . . . . . . . . . . . . 959 28.7.11 TIM16 repetition counter register (TIM16_RCR) . . . . . . . . . . . . . . . . . 960 28.7.12 TIM16 capture/compare register 1 (TIM16_CCR1) . . . . . . . . . . . . . . . 960 26/1600 RM0394 Rev 4 RM0394 Contents 28.7.13 TIM16 break and dead-time register (TIM16_BDTR) . . . . . . . . . . . . . 961 28.7.14 TIM16 DMA control register (TIM16_DCR) . . . . . . . . . . . . . . . . . . . . . 963 28.7.15 TIM16 DMA address for full transfer (TIM16_DMAR) . . . . . . . . . . . . . 963 28.7.16 TIM16 option register 1 (TIM16_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . 964 28.7.17 TIM16 option register 2 (TIM16_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . 964 28.7.18 TIM16 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966 29 Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968 29.1 TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968 29.2 TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968 29.3 TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 29.4 30 29.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 29.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 29.3.3 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974 29.3.4 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974 29.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 29.4.1 TIM6/TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . 975 29.4.2 TIM6/TIM7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . 977 29.4.3 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . 977 29.4.4 TIM6/TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 978 29.4.5 TIM6/TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . 978 29.4.6 TIM6/TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978 29.4.7 TIM6/TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979 29.4.8 TIM6/TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 979 29.4.9 TIM6/TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980 Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 30.2 LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 30.3 LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 30.4 LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982 30.4.1 LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982 30.4.2 LPTIM trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 30.4.3 LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984 30.4.4 Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984 RM0394 Rev 4 27/1600 43 Contents RM0394 30.4.5 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 30.4.6 Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 30.4.7 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986 30.4.8 Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988 30.4.9 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989 30.4.10 Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990 30.4.11 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991 30.4.12 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991 30.4.13 Timer counter reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992 30.4.14 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992 30.4.15 Repetition Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994 30.4.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995 30.5 LPTIM low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996 30.6 LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996 30.7 LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997 30.7.1 LPTIM interrupt and status register (LPTIM_ISR) . . . . . . . . . . . . . . . . 997 30.7.2 LPTIM interrupt clear register (LPTIM_ICR) . . . . . . . . . . . . . . . . . . . . 999 30.7.3 LPTIM interrupt enable register (LPTIM_IER) . . . . . . . . . . . . . . . . . . 1000 30.7.4 LPTIM configuration register (LPTIM_CFGR) . . . . . . . . . . . . . . . . . . 1002 30.7.5 LPTIM control register (LPTIM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 1004 30.7.6 LPTIM compare register (LPTIM_CMP) . . . . . . . . . . . . . . . . . . . . . . 1006 30.7.7 LPTIM autoreload register (LPTIM_ARR) . . . . . . . . . . . . . . . . . . . . . 1006 30.7.8 LPTIM counter register (LPTIM_CNT) . . . . . . . . . . . . . . . . . . . . . . . . 1007 30.7.9 LPTIM1 option register (LPTIM1_OR) . . . . . . . . . . . . . . . . . . . . . . . . 1007 30.7.10 LPTIM2 option register (LPTIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . 1008 30.7.11 LPTIM configuration register 2 (LPTIM_CFGR2) . . . . . . . . . . . . . . . 1008 30.7.12 LPTIM repetition register (LPTIM_RCR) . . . . . . . . . . . . . . . . . . . . . . 1009 30.7.13 LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010 31 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012 32 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 28/1600 32.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 32.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 32.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 32.3.1 IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 32.3.2 Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014 RM0394 Rev 4 RM0394 Contents 32.4 33 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015 32.3.4 Low-power freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015 32.3.5 Behavior in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . 1015 32.3.6 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015 32.3.7 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 32.4.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 32.4.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 32.4.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018 32.4.4 Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019 32.4.5 Window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020 32.4.6 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . 1022 33.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 33.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 33.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 33.4 34 32.3.3 33.3.1 WWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 33.3.2 Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 33.3.3 Controlling the downcounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 33.3.4 Advanced watchdog interrupt feature . . . . . . . . . . . . . . . . . . . . . . . . 1023 33.3.5 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . 1024 33.3.6 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026 33.4.1 Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026 33.4.2 Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . 1026 33.4.3 Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027 33.4.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028 Real-time clock (RTC) applied to STM32L41xxx and STM32L42xxx devices only . . . . . . . . . . . . . . . . 1029 34.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029 34.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029 34.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030 34.3.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030 34.3.2 RTC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032 RM0394 Rev 4 29/1600 43 Contents RM0394 34.3.3 GPIOs controlled by the RTC and TAMP . . . . . . . . . . . . . . . . . . . . . . 1033 34.3.4 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035 34.3.5 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036 34.3.6 Calendar ultra-low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036 34.3.7 Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036 34.3.8 Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037 34.3.9 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 1038 34.3.10 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 34.3.11 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 34.3.12 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 34.3.13 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 34.3.14 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042 34.3.15 Timestamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044 34.3.16 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045 34.3.17 Tamper and alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046 34.4 RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046 34.5 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 34.6 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 34.6.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 34.6.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049 34.6.3 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . 1050 34.6.4 RTC initialization control and status register (RTC_ICSR) . . . . . . . . 1050 34.6.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . 1052 34.6.6 RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 1052 34.6.7 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053 34.6.8 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . 1056 34.6.9 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . 1057 34.6.10 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . 1058 34.6.11 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 1059 34.6.12 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . 1059 34.6.13 RTC timestamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . 1060 34.6.14 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . 1060 34.6.15 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . 1061 34.6.16 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . 1062 34.6.17 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . 1063 34.6.18 RTC status register (RTC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064 34.6.19 RTC masked interrupt status register (RTC_MISR) . . . . . . . . . . . . . 1065 30/1600 RM0394 Rev 4 RM0394 Contents 34.6.20 RTC status clear register (RTC_SCR) . . . . . . . . . . . . . . . . . . . . . . . . 1066 34.6.21 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067 35 36 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . 1069 35.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 35.2 TAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 35.3 TAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 35.3.1 TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 35.3.2 TAMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 35.3.3 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071 35.4 TAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073 35.5 TAMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073 35.6 TAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 35.6.1 TAMP control register 1 (TAMP_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 1074 35.6.2 TAMP control register 2 (TAMP_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 1075 35.6.3 TAMP filter control register (TAMP_FLTCR) . . . . . . . . . . . . . . . . . . . 1076 35.6.4 TAMP interrupt enable register (TAMP_IER) . . . . . . . . . . . . . . . . . . . 1077 35.6.5 TAMP status register (TAMP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 35.6.6 TAMP masked interrupt status register (TAMP_MISR) . . . . . . . . . . . 1079 35.6.7 TAMP status clear register (TAMP_SCR) . . . . . . . . . . . . . . . . . . . . . 1079 35.6.8 TAMP backup x register (TAMP_BKPxR) . . . . . . . . . . . . . . . . . . . . . 1080 35.6.9 TAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081 Real-time clock (RTC) applied to STM32L43x/44x/45x/46x devices only . . . . . . . . . . . . . . . . . . . . . . . . 1082 36.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082 36.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083 36.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084 36.3.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084 36.3.2 GPIOs controlled by the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085 36.3.3 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087 36.3.4 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088 36.3.5 Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088 36.3.6 Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088 36.3.7 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 1089 36.3.8 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091 RM0394 Rev 4 31/1600 43 Contents RM0394 36.3.9 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092 36.3.10 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092 36.3.11 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093 36.3.12 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094 36.3.13 Time-stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096 36.3.14 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096 36.3.15 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098 36.3.16 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099 36.4 RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099 36.5 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1100 36.6 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1101 36.6.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101 36.6.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1102 36.6.3 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103 36.6.4 RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . 1106 36.6.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . 1109 36.6.6 RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 1110 36.6.7 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . 1111 36.6.8 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . 1112 36.6.9 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . 1113 36.6.10 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . 1113 36.6.11 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . 1114 36.6.12 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 1115 36.6.13 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . 1116 36.6.14 RTC time-stamp sub second register (RTC_TSSSR) . . . . . . . . . . . . 1117 36.6.15 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . 1118 36.6.16 RTC tamper configuration register (RTC_TAMPCR) . . . . . . . . . . . . . 1119 36.6.17 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . 1122 36.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . 1123 36.6.19 RTC option register (RTC_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124 36.6.20 RTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . 1124 36.6.21 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125 37 32/1600 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . 1127 37.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1127 37.2 I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1127 RM0394 Rev 4 RM0394 Contents 37.3 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1128 37.4 I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1128 37.4.1 I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129 37.4.2 I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130 37.4.3 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130 37.4.4 I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131 37.4.5 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135 37.4.6 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136 37.4.7 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138 37.4.8 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 37.4.9 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . 1159 37.4.10 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160 37.4.11 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163 37.4.12 SMBus: I2C_TIMEOUTR register configuration examples . . . . . . . . 1165 37.4.13 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165 37.4.14 Wakeup from Stop mode on address match . . . . . . . . . . . . . . . . . . . 1173 37.4.15 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173 37.4.16 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175 37.4.17 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176 37.5 I2C low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1176 37.6 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1177 37.7 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1177 37.7.1 I2C control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177 37.7.2 I2C control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180 37.7.3 I2C own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . 1183 37.7.4 I2C own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . 1184 37.7.5 I2C timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1185 37.7.6 I2C timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . 1186 37.7.7 I2C interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . 1187 37.7.8 I2C interrupt clear register (I2C_ICR)( . . . . . . . . . . . . . . . . . . . . . . . . 1189 37.7.9 I2C PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190 37.7.10 I2C receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . 1191 37.7.11 I2C transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . 1191 37.7.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 38 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmitter (UART) . . . . . . . . . . 1194 RM0394 Rev 4 33/1600 43 Contents RM0394 38.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1194 38.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1194 38.3 USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1195 38.4 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1196 38.5 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1196 38.5.1 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199 38.5.2 USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201 38.5.3 USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203 38.5.4 USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210 38.5.5 Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . 1212 38.5.6 USART auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213 38.5.7 Multiprocessor communication using USART . . . . . . . . . . . . . . . . . . 1214 38.5.8 Modbus communication using USART . . . . . . . . . . . . . . . . . . . . . . . 1216 38.5.9 USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217 38.5.10 USART LIN (local interconnection network) mode . . . . . . . . . . . . . . 1218 38.5.11 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220 38.5.12 USART Single-wire Half-duplex communication . . . . . . . . . . . . . . . . 1223 38.5.13 USART Smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223 38.5.14 USART IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228 38.5.15 USART continuous communication in DMA mode . . . . . . . . . . . . . . 1230 38.5.16 RS232 hardware flow control and RS485 driver enable using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232 38.5.17 Wakeup from Stop mode using USART . . . . . . . . . . . . . . . . . . . . . . . 1234 38.6 USART low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236 38.7 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236 38.8 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238 38.8.1 Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238 38.8.2 Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241 38.8.3 Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245 38.8.4 Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249 38.8.5 Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . 1249 38.8.6 Receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . . . . . . . 1251 38.8.7 Request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252 38.8.8 Interrupt and status register (USART_ISR) . . . . . . . . . . . . . . . . . . . . 1253 38.8.9 Interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . . . . . . . . 1257 38.8.10 Receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . . . . . . . 1259 34/1600 RM0394 Rev 4 RM0394 Contents 38.8.11 Transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . . . . . . . 1259 38.8.12 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260 39 Low-power universal asynchronous receiver transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262 39.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262 39.2 LPUART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263 39.3 LPUART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263 39.4 LPUART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264 39.4.1 LPUART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266 39.4.2 LPUART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268 39.4.3 LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270 39.4.4 LPUART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273 39.4.5 Tolerance of the LPUART receiver to clock deviation . . . . . . . . . . . . 1275 39.4.6 Multiprocessor communication using LPUART . . . . . . . . . . . . . . . . . 1276 39.4.7 LPUART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278 39.4.8 Single-wire Half-duplex communication using LPUART . . . . . . . . . . 1279 39.4.9 Continuous communication in DMA mode using LPUART . . . . . . . . 1279 39.4.10 RS232 Hardware flow control and RS485 Driver Enable using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282 39.4.11 Wakeup from Stop mode using LPUART . . . . . . . . . . . . . . . . . . . . . . 1285 39.5 LPUART low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286 39.6 LPUART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287 39.7 LPUART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289 39.7.1 Control register 1 (LPUART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289 39.7.2 Control register 2 (LPUART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291 39.7.3 Control register 3 (LPUART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294 39.7.4 Baud rate register (LPUART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1296 39.7.5 Request register (LPUART_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296 39.7.6 Interrupt & status register (LPUART_ISR) . . . . . . . . . . . . . . . . . . . . . 1297 39.7.7 Interrupt flag clear register (LPUART_ICR) . . . . . . . . . . . . . . . . . . . . 1300 39.7.8 Receive data register (LPUART_RDR) . . . . . . . . . . . . . . . . . . . . . . . 1301 39.7.9 Transmit data register (LPUART_TDR) . . . . . . . . . . . . . . . . . . . . . . . 1301 39.7.10 LPUART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303 40 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304 40.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304 RM0394 Rev 4 35/1600 43 Contents RM0394 40.2 SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304 40.3 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304 40.4 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305 40.4.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305 40.4.2 Communications between one master and one slave . . . . . . . . . . . . 1306 40.4.3 Standard multi-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . 1308 40.4.4 Multi-master communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309 40.4.5 Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . 1310 40.4.6 Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311 40.4.7 Configuration of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313 40.4.8 Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1314 40.4.9 Data transmission and reception procedures . . . . . . . . . . . . . . . . . . 1314 40.4.10 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1324 40.4.11 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1325 40.4.12 NSS pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326 40.4.13 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326 40.4.14 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327 41 36/1600 40.5 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1329 40.6 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330 40.6.1 SPI control register 1 (SPIx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330 40.6.2 SPI control register 2 (SPIx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332 40.6.3 SPI status register (SPIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1334 40.6.4 SPI data register (SPIx_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1335 40.6.5 SPI CRC polynomial register (SPIx_CRCPR) . . . . . . . . . . . . . . . . . . 1336 40.6.6 SPI Rx CRC register (SPIx_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1336 40.6.7 SPI Tx CRC register (SPIx_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1336 40.6.8 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1338 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1339 41.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1339 41.2 SAI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1339 41.3 SAI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1340 41.4 SAI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341 41.4.1 SAI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341 41.4.2 SAI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342 41.4.3 Main SAI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342 RM0394 Rev 4 RM0394 Contents 41.4.4 SAI synchronization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343 41.4.5 Audio data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344 41.4.6 Frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344 41.4.7 Slot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347 41.4.8 SAI clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349 41.4.9 Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351 41.4.10 AC’97 link controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353 41.4.11 SPDIF output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354 41.4.12 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357 41.4.13 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361 41.4.14 Disabling the SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364 41.4.15 SAI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364 41.5 SAI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365 41.6 SAI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366 41.6.1 Configuration register 1 (SAI_ACR1) . . . . . . . . . . . . . . . . . . . . . . . . . 1366 41.6.2 Configuration register 1 (SAI_BCR1) . . . . . . . . . . . . . . . . . . . . . . . . . 1368 41.6.3 Configuration register 2 (SAI_ACR2) . . . . . . . . . . . . . . . . . . . . . . . . . 1370 41.6.4 Configuration register 2 (SAI_BCR2) . . . . . . . . . . . . . . . . . . . . . . . . . 1372 41.6.5 Frame configuration register (SAI_AFRCR) . . . . . . . . . . . . . . . . . . . 1374 41.6.6 Frame configuration register (SAI_BFRCR) . . . . . . . . . . . . . . . . . . . 1375 41.6.7 Slot register (SAI_ASLOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377 41.6.8 Slot register (SAI_BSLOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378 41.6.9 Interrupt mask register (SAI_AIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379 41.6.10 Interrupt mask register (SAI_BIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1380 41.6.11 Status register (SAI_ASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381 41.6.12 Status register (SAI_BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383 41.6.13 Clear flag register (SAI_ACLRFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385 41.6.14 Clear flag register (SAI_BCLRFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386 41.6.15 Data register (SAI_ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387 41.6.16 Data register (SAI_BDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388 41.6.17 SAI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389 42 Single Wire Protocol Master Interface (SWPMI) . . . . . . . . . . . . . . . . 1390 42.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1390 42.2 SWPMI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1391 42.3 SWPMI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392 42.3.1 SWPMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392 RM0394 Rev 4 37/1600 43 Contents RM0394 42.3.2 SWP initialization and activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392 42.3.3 SWP bus states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1393 42.3.4 SWPMI_IO (internal transceiver) bypass . . . . . . . . . . . . . . . . . . . . . . 1394 42.3.5 SWPMI Bit rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394 42.3.6 SWPMI frame handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395 42.3.7 Transmission procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395 42.3.8 Reception procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400 42.3.9 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404 42.3.10 Loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406 42.4 SWPMI low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406 42.5 SWPMI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407 42.6 SWPMI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408 42.6.1 SWPMI Configuration/Control register (SWPMI_CR) . . . . . . . . . . . . 1408 42.6.2 SWPMI Bitrate register (SWPMI_BRR) . . . . . . . . . . . . . . . . . . . . . . . 1409 42.6.3 SWPMI Interrupt and Status register (SWPMI_ISR) . . . . . . . . . . . . . 1410 42.6.4 SWPMI Interrupt Flag Clear register (SWPMI_ICR) . . . . . . . . . . . . . 1411 42.6.5 SWPMI Interrupt Enable register (SMPMI_IER) . . . . . . . . . . . . . . . . 1412 42.6.6 SWPMI Receive Frame Length register (SWPMI_RFL) . . . . . . . . . . 1413 42.6.7 SWPMI Transmit data register (SWPMI_TDR) . . . . . . . . . . . . . . . . . 1414 42.6.8 SWPMI Receive data register (SWPMI_RDR) . . . . . . . . . . . . . . . . . 1414 42.6.9 SWPMI Option register (SWPMI_OR) . . . . . . . . . . . . . . . . . . . . . . . . 1414 42.6.10 SWPMI register map and reset value table . . . . . . . . . . . . . . . . . . . . 1416 43 SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . 1417 43.1 SDMMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417 43.2 SDMMC bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417 43.3 SDMMC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419 43.4 38/1600 43.3.1 SDMMC adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421 43.3.2 SDMMC APB2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1432 Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433 43.4.1 Card identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433 43.4.2 Card reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433 43.4.3 Operating voltage range validation . . . . . . . . . . . . . . . . . . . . . . . . . . 1434 43.4.4 Card identification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434 43.4.5 Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1435 43.4.6 Block read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436 RM0394 Rev 4 RM0394 Contents 43.4.7 Stream access, stream write and stream read (MultiMediaCard only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436 43.4.8 Erase: group erase and sector erase . . . . . . . . . . . . . . . . . . . . . . . . 1438 43.4.9 Wide bus selection or deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438 43.4.10 Protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438 43.4.11 Card status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1442 43.4.12 SD status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1445 43.4.13 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449 43.4.14 Commands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1450 43.5 43.6 Response formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453 43.5.1 R1 (normal response command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454 43.5.2 R1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454 43.5.3 R2 (CID, CSD register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454 43.5.4 R3 (OCR register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455 43.5.5 R4 (Fast I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455 43.5.6 R4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455 43.5.7 R5 (interrupt request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456 43.5.8 R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456 SDIO I/O card-specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457 43.6.1 SDIO I/O read wait operation by SDMMC_D2 signalling . . . . . . . . . . 1457 43.6.2 SDIO read wait operation by stopping SDMMC_CK . . . . . . . . . . . . . 1458 43.6.3 SDIO suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458 43.6.4 SDIO interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458 43.7 HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458 43.8 SDMMC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1459 43.8.1 SDMMC power control register (SDMMC_POWER) . . . . . . . . . . . . . 1459 43.8.2 SDMMC clock control register (SDMMC_CLKCR) . . . . . . . . . . . . . . 1459 43.8.3 SDMMC argument register (SDMMC_ARG) . . . . . . . . . . . . . . . . . . . 1461 43.8.4 SDMMC command register (SDMMC_CMD) . . . . . . . . . . . . . . . . . . 1461 43.8.5 SDMMC command response register (SDMMC_RESPCMD) . . . . . . 1462 43.8.6 SDMMC response 1..4 register (SDMMC_RESPx) . . . . . . . . . . . . . . 1462 43.8.7 SDMMC data timer register (SDMMC_DTIMER) . . . . . . . . . . . . . . . . 1463 43.8.8 SDMMC data length register (SDMMC_DLEN) . . . . . . . . . . . . . . . . . 1464 43.8.9 SDMMC data control register (SDMMC_DCTRL) . . . . . . . . . . . . . . . 1464 43.8.10 SDMMC data counter register (SDMMC_DCOUNT) . . . . . . . . . . . . . 1467 43.8.11 SDMMC status register (SDMMC_STA) . . . . . . . . . . . . . . . . . . . . . . 1467 43.8.12 SDMMC interrupt clear register (SDMMC_ICR) . . . . . . . . . . . . . . . . 1468 RM0394 Rev 4 39/1600 43 Contents RM0394 43.8.13 SDMMC mask register (SDMMC_MASK) . . . . . . . . . . . . . . . . . . . . . 1470 43.8.14 SDMMC FIFO counter register (SDMMC_FIFOCNT) . . . . . . . . . . . . 1472 43.8.15 SDMMC data FIFO register (SDMMC_FIFO) . . . . . . . . . . . . . . . . . . 1473 43.8.16 SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474 44 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476 44.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476 44.2 bxCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476 44.3 bxCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477 44.4 44.5 40/1600 44.3.1 CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477 44.3.2 Control, status and configuration registers . . . . . . . . . . . . . . . . . . . . 1477 44.3.3 Tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477 44.3.4 Acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478 bxCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478 44.4.1 Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478 44.4.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479 44.4.3 Sleep mode (low-power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480 44.5.1 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480 44.5.2 Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481 44.5.3 Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . 1481 44.6 Behavior in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482 44.7 bxCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482 44.7.1 Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482 44.7.2 Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 1484 44.7.3 Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484 44.7.4 Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1485 44.7.5 Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489 44.7.6 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491 44.7.7 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491 44.8 bxCAN interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494 44.9 CAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495 44.9.1 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495 44.9.2 CAN control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495 44.9.3 CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505 44.9.4 CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1512 RM0394 Rev 4 RM0394 Contents 44.9.5 45 Universal serial bus full-speed device interface (USB) . . . . . . . . . . 1520 45.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520 45.2 USB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520 45.3 USB implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520 45.4 USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521 45.4.1 45.5 45.6 46 bxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516 Description of USB blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523 45.5.1 Generic USB device programming . . . . . . . . . . . . . . . . . . . . . . . . . . 1523 45.5.2 System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524 45.5.3 Double-buffered endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529 45.5.4 Isochronous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531 45.5.5 Suspend/Resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532 USB and USB SRAM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535 45.6.1 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535 45.6.2 Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548 45.6.3 USB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553 46.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553 46.2 Reference Arm® documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1554 46.3 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . 1554 46.3.1 46.4 Mechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . 1555 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555 46.4.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556 46.4.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556 46.4.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . 1557 46.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . 1558 46.5 STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx JTAG TAP connection 1558 46.6 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559 46.7 46.6.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560 46.6.2 Boundary scan TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560 46.6.3 Cortex®-M4 TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560 46.6.4 Cortex®-M4 JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561 JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561 RM0394 Rev 4 41/1600 43 Contents RM0394 46.8 46.9 SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563 46.8.1 SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563 46.8.2 SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563 46.8.3 SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . 1564 46.8.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564 46.8.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565 46.8.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566 46.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567 46.11 Capability of the debugger host to connect under system reset . . . . . 1567 46.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568 46.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568 46.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . 1569 46.14.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1569 46.14.2 Time stamp packets, synchronization and overflow packets . . . . . . . 1569 46.15 ETM (Embedded trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571 46.15.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571 46.15.2 Signal protocol, packet types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571 46.15.3 Main ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571 46.15.4 Configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572 46.16 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . 1572 46.16.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 1572 46.16.2 Debug support for timers, RTC, watchdog, bxCAN and I2C . . . . . . . 1573 46.16.3 Debug MCU configuration register (DBGMCU_CR) . . . . . . . . . . . . . 1573 46.16.4 Debug MCU APB1 freeze register1(DBGMCU_APB1FZR1) . . . . . . 1574 46.16.5 Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2) . . . . . 1575 46.16.6 Debug MCU APB2 freeze register (DBGMCU_APB2FZR) . . . . . . . . 1576 46.17 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577 46.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577 46.17.2 TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577 46.17.3 TPUI formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1579 46.17.4 TPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . 1580 46.17.5 Transmission of the synchronization frame packet . . . . . . . . . . . . . . 1580 46.17.6 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1580 46.17.7 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1581 42/1600 RM0394 Rev 4 RM0394 Contents 46.17.8 TRACECLKIN connection inside the STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx . . . . . . . . . . . . . . . . 1581 46.17.9 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1582 46.17.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1583 46.18 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1584 47 48 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585 47.1 Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585 47.2 Flash size data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1586 47.3 Package data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1587 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588 RM0394 Rev 4 43/1600 43 List of tables RM0394 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. 44/1600 Product specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx memory map and peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 SRAM2 organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SRAM2 organization (continuation for STM32L43x/44x/45x/46x devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SRAM2 organization (continuation for STM32L45x and STM32L46x devices only) . . . . . . . . . . . . . . . . . . . . . . 72 Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Memory mapping vs. Boot mode/Physical remap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Flash module - single bank organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Number of wait states according to CPU clock (HCLK) frequency . . . . . . . . . . . . . . . . . . . 79 Option byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Option byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Flash memory read protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Access status versus protection level and execution modes . . . . . . . . . . . . . . . . . . . . . . . 96 Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Flash interface - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Segment accesses according to the Firewall state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Segment granularity and area ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Firewall register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 PVM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Low-power run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Low-power sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Clock source frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Effect of low-power modes on CRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 CRS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx peripherals interconnect matrix . . . . . . 288 DMA1 and DMA2 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 DMA1 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 DMA2 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . . . . . . . 306 DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 RM0394 Rev 4 RM0394 Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. List of tables STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table . . . . . . . . . . . . . . . . . . . . . . 321 EXTI lines connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Extended interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . 337 CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 QUADSPI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 QUADSPI interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 QUADSPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 Main ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 ADC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 ADC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Configuring the trigger polarity for regular external triggers . . . . . . . . . . . . . . . . . . . . . . . 394 Configuring the trigger polarity for injected external triggers . . . . . . . . . . . . . . . . . . . . . . 394 ADC1 and ADC2 - External triggers for regular channels. . . . . . . . . . . . . . . . . . . . . . . . . 395 ADC1 and ADC2 - External trigger for injected channels . . . . . . . . . . . . . . . . . . . . . . . . . 396 TSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 Offset computation versus data resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 Analog watchdog 1 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 Analog watchdog 2 and 3 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 Maximum output results versus N and M (gray cells indicate truncation). . . . . . . . . . . . . 427 Oversampler operating modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 ADC interrupts per each ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 DELAY bits versus ADC resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 ADC global register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 ADC register map and reset values (master and slave ADC common registers) offset = 0x300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 DAC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 DAC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 Sample and refresh timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Channel output modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 Effect of low-power modes on DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 DAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 VREF buffer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 VREFBUF register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 COMP1 input plus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 COMP1 input minus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 COMP2 input plus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 COMP2 input minus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 Comparator behavior in the low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 COMP register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 Operational amplifier possible connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 Operating modes and calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 Effect of low-power modes on the OPAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 OPAMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 DFSDM1 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 DFSDM external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 RM0394 Rev 4 45/1600 49 List of tables Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. 46/1600 RM0394 DFSDM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 DFSDM triggers connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 DFSDM break connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 Filter maximum output resolution (peak data values from filter output) for some FOSR values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 Integrator maximum output resolution (peak data values from integrator output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . . 568 DFSDM interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 DFSDM register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 Example of frame rate calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 Blink frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 Remapping capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 LCD behavior in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 LCD interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 LCD register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 Acquisition sequence summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 Spread spectrum deviation versus AHB clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . 639 I/O state depending on its mode and IODEF bit value . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 Effect of low-power modes on TSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 TSC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 RNG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 RNG interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 RNG register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 AES internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 CTR mode initialization vector definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 GCM last block definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 GCM mode IVI bitfield initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 Initialization of AES_IVRx registers in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . . . . . . . . . . . 700 DMA channel configuration for memory-to-AES data transfer . . . . . . . . . . . . . . . . . . . . . 701 DMA channel configuration for AES-to-memory data transfer . . . . . . . . . . . . . . . . . . . . . 702 AES interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 Processing latency (in clock cycle) for ECB, CBC and CTR. . . . . . . . . . . . . . . . . . . . . . . 704 Processing latency for GCM and CCM (in clock cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . 704 AES register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 Behavior of timer outputs versus BRK/BRK2 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 TIM1 internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785 Output control bits for complementary OCx and OCxN channels with break feature . . . . 799 TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878 TIM2/TIM3 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884 TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928 Output control bits for complementary OCx and OCxN channels with break feature (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938 TIM15 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946 Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 TIM16 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966 RM0394 Rev 4 RM0394 Table 144. Table 145. Table 146. Table 147. Table 148. Table 149. Table 150. Table 151. Table 152. Table 153. Table 154. Table 155. Table 156. Table 157. Table 158. Table 159. Table 160. Table 161. Table 162. Table 163. Table 164. Table 165. Table 166. Table 167. Table 168. Table 169. Table 170. Table 171. Table 172. Table 173. Table 174. Table 175. Table 176. Table 177. Table 178. Table 179. Table 180. Table 181. Table 182. Table 183. Table 184. Table 185. Table 186. Table 187. Table 188. Table 189. Table 190. Table 191. Table 192. Table 193. List of tables TIM6/TIM7 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980 STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx LPTIM features . . . . . . . . . . . . . . . . . . . 982 LPTIM1 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 LPTIM2 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993 Effect of low-power modes on the LPTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996 Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996 LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010 IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021 WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028 RTC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032 RTC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032 RTC interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032 PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033 RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035 Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046 RTC pins functionality over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067 TAMP input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 TAMP internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071 TAMP interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071 Effect of low-power modes on TAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073 Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 TAMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081 RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085 RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086 RTC functions over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087 Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099 Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100 RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128 Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131 I2C-SMBUS specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134 I2C configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138 I2C-SMBUS specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149 Examples of timing settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159 Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159 Examples of timings settings for fI2CCLK = 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160 SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162 SMBUS with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164 Examples of TIMEOUTA settings for various I2CCLK frequencies (max tTIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165 Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . 1165 Examples of TIMEOUTA settings for various I2CCLK frequencies (max tIDLE = 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165 Effect of low-power modes on the I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176 I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177 I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 USART/LPUART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196 Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 RM0394 Rev 4 47/1600 49 List of tables RM0394 Table 194. Error calculation for programmed baud rates at fCK = 72MHz in both cases of oversampling by 16 or by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211 Table 195. Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . 1213 Table 196. Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . . . . . . . . 1213 Table 197. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217 Table 198. Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236 Table 199. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236 Table 200. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260 Table 201. USART/LPUART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264 Table 202. Error calculation for programmed baud rates at fck = 32,768 KHz. . . . . . . . . . . . . . . . . 1274 Table 203. Error calculation for programmed baud rates at fck = 80 MHz . . . . . . . . . . . . . . . . . . . . 1274 Table 204. Tolerance of the LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275 Table 205. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278 Table 206. Effect of low-power modes on the LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286 Table 207. LPUART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287 Table 208. LPUART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303 Table 209. SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305 Table 210. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1329 Table 211. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1338 Table 212. STM32L43xxx/44xxx/45xxx/46xxx SAI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1340 Table 213. SAI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342 Table 214. SAI input/output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342 Table 215. External synchronization selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344 Table 216. Example of possible audio frequency sampling range . . . . . . . . . . . . . . . . . . . . . . . . . . 1350 Table 217. SOPD pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355 Table 218. Parity bit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355 Table 219. Audio sampling frequency versus symbol rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356 Table 220. SAI interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365 Table 221. SAI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389 Table 222. Effect of low-power modes on SWPMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406 Table 223. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407 Table 224. Buffer modes selection for transmission/reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1409 Table 225. SWPMI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1416 Table 226. SDMMC I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420 Table 227. Command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425 Table 228. Short response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1426 Table 229. Long response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1426 Table 230. Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1426 Table 231. Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1429 Table 232. DPSM flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1430 Table 233. Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1431 Table 234. Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1431 Table 235. Card status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1442 Table 236. SD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1445 Table 237. Speed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446 Table 238. Performance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447 Table 239. AU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447 Table 240. Maximum AU size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447 Table 241. Erase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448 Table 242. Erase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448 Table 243. Erase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448 Table 244. Block-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1451 48/1600 RM0394 Rev 4 RM0394 Table 245. Table 246. Table 247. Table 248. Table 249. Table 250. Table 251. Table 252. Table 253. Table 254. Table 255. Table 256. Table 257. Table 258. Table 259. Table 260. Table 261. Table 262. Table 263. Table 264. Table 265. Table 266. Table 267. Table 268. Table 269. Table 270. Table 271. Table 272. Table 273. Table 274. Table 275. Table 276. Table 277. Table 278. Table 279. Table 280. Table 281. Table 282. Table 283. Table 284. Table 285. Table 286. Table 287. Table 288. Table 289. Table 290. List of tables Block-oriented write protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1452 Erase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1452 I/O mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1452 Lock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453 Application-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453 R1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454 R2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454 R3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455 R4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455 R4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455 R5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456 R6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457 Response type and SDMMC_RESPx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463 SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474 Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490 Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490 bxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516 STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx USB implementation . . . . . . . . . . . . . . 1520 Double-buffering buffer flag definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530 Bulk double-buffering memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530 Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532 Resume event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1534 Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1546 Endpoint type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547 Endpoint kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547 Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547 Definition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1550 USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556 JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . 1562 Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563 ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564 DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565 Cortex®-M4 AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566 Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567 Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1569 Main ETM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571 Asynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577 Synchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1578 Flexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1578 Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1582 DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1584 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588 RM0394 Rev 4 49/1600 49 List of figures RM0394 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 50/1600 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Sequential 16-bit instructions execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Changing the Read protection (RDP) level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx firewall connection schematics . . . . . . . 115 Firewall functional states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Internal main regulator overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Brown-out reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Low-power modes possible transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Frequency measurement with TIM15 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Frequency measurement with TIM16 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 190 CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 CRS counter behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Basic structure of a 5-Volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 DMA1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 DMA2 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Configurable interrupt/event block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 QUADSPI block diagram when dual-flash mode is disabled . . . . . . . . . . . . . . . . . . . . . . 344 QUADSPI block diagram when dual-flash mode is enabled . . . . . . . . . . . . . . . . . . . . . . 345 An example of a read command in quad mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 An example of a DDR command in quad mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 nCS when CKMODE = 0 (T = CLK period). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 nCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 357 nCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 358 nCS when CKMODE = 1 with an abort (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . . 358 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 ADC1 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 ADC2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 Updating the ADC calibration factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Mixing single-ended and differential channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Enabling / Disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 Stopping ongoing regular conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 RM0394 Rev 4 RM0394 Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. List of figures Stopping ongoing regular and injected conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 Triggers sharing between ADC master and ADC slave . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Example of JSQR queue of context (sequence change) . . . . . . . . . . . . . . . . . . . . . . . . . 401 Example of JSQR queue of context (trigger change) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 Example of JSQR queue of context with overflow before conversion . . . . . . . . . . . . . . . 402 Example of JSQR queue of context with overflow during conversion . . . . . . . . . . . . . . . 402 Example of JSQR queue of context with empty queue (case JQM=0). . . . . . . . . . . . . . . 403 Example of JSQR queue of context with empty queue (case JQM=1). . . . . . . . . . . . . . . 404 Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion. . . . . . . . . . . . . . . . . . . . . . . 404 Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion and a new trigger occurs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs outside an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . 405 Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . . . . . . . . . . . . . . . 406 Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . . . . . . . . . . . . . . . . . 406 Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . . . . . . . . . . . . . . . . . 407 Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 409 Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 410 Right alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Right alignment (offset enabled, signed value). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Left alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Left alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 AUTODLY=1, regular conversion in continuous mode, software trigger . . . . . . . . . . . . . 418 AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0; JDISCEN=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 AUTODLY=1, regular HW conversions interrupted by injected conversions . . . . . . . . . . . . . (DISCEN=1, JDISCEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 AUTODLY=1, regular continuous conversions interrupted by injected conversions . . . . 421 AUTODLY=1 in auto- injected mode (JAUTO=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 ADCy_AWDx_OUT signal generation (on all regular channels). . . . . . . . . . . . . . . . . . . . 424 ADCy_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . . . . . . . 425 ADCy_AWDx_OUT signal generation (on a single regular channel) . . . . . . . . . . . . . . . . 425 ADCy_AWDx_OUT signal generation (on all injected channels) . . . . . . . . . . . . . . . . . . . 425 20-bit to 16-bit result truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 Numerical example with 5-bit shift and rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 Triggered regular oversampling mode (TROVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 428 Regular oversampling modes (4x ratio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 Regular and injected oversampling modes used simultaneously . . . . . . . . . . . . . . . . . . . 430 Triggered regular oversampling with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 Oversampling in auto-injected mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 Dual ADC block diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Injected simultaneous mode on 4 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . . 434 Regular simultaneous mode on 16 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . 436 Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . . . 437 Interleaved mode on 1 channel in single conversion mode: dual ADC mode. . . . . . . . . . 438 RM0394 Rev 4 51/1600 59 List of figures Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. Figure 110. Figure 111. Figure 112. Figure 113. Figure 114. Figure 115. Figure 116. Figure 117. Figure 118. Figure 119. Figure 120. Figure 121. Figure 122. Figure 123. Figure 124. Figure 125. Figure 126. Figure 127. Figure 128. Figure 129. Figure 130. Figure 131. Figure 132. Figure 133. Figure 134. Figure 135. Figure 136. Figure 137. Figure 138. Figure 139. Figure 140. Figure 141. Figure 142. Figure 143. 52/1600 RM0394 Interleaved conversion with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 Alternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . . . . . . . . . 440 Alternate + regular simultaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . . . . . . . . . . . . 442 Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 1: Master interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 2: Slave interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 DMA Requests in regular simultaneous mode when MDMA=0b00 . . . . . . . . . . . . . . . . . 443 DMA requests in regular simultaneous mode when MDMA=0b10 . . . . . . . . . . . . . . . . . . 444 DMA requests in interleaved mode when MDMA=0b10 . . . . . . . . . . . . . . . . . . . . . . . . . . 444 Temperature sensor channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 VBAT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 Dual-channel DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 491 DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 DAC conversion (SW trigger enabled) with LFSR wave generation . . . . . . . . . . . . . . . . 493 DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 494 DAC Sample and Hold mode phase diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 Comparators block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 Window mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 Comparator hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 Comparator output blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 Standalone mode: external gain setting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 Follower configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . . . . . . . . . 542 PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 Single DFSDM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 Input channel pins redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 Clock absence timing diagram for SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 Clock absence timing diagram for Manchester coding . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 First conversion for Manchester coding (Manchester synchronization) . . . . . . . . . . . . . . 562 DFSDM_CHyDATINR registers operation modes and assignment . . . . . . . . . . . . . . . . . 565 Example: Sinc3 filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 LCD controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 1/3 bias, 1/4 duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 Static duty case 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 Static duty case 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 1/2 duty, 1/2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 1/3 duty, 1/3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 1/4 duty, 1/3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 1/8 duty, 1/4 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 LCD voltage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 Deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 RM0394 Rev 4 RM0394 Figure 144. Figure 145. Figure 146. Figure 147. Figure 148. Figure 149. Figure 150. Figure 151. Figure 152. Figure 153. Figure 154. Figure 155. Figure 156. Figure 157. Figure 158. Figure 159. Figure 160. Figure 161. Figure 162. Figure 163. Figure 164. Figure 165. Figure 166. Figure 167. Figure 168. Figure 169. Figure 170. Figure 171. Figure 172. Figure 173. Figure 174. Figure 175. Figure 176. Figure 177. Figure 178. Figure 179. Figure 180. Figure 181. Figure 182. Figure 183. Figure 184. Figure 185. Figure 186. Figure 187. Figure 188. Figure 189. Figure 190. Figure 191. Figure 192. Figure 193. Figure 194. Figure 195. List of figures SEG/COM mux feature example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 Flowchart example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 Surface charge transfer analog I/O group structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 Sampling capacitor voltage variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 Spread spectrum variation principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 Entropy source model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 ECB encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 CBC encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 CTR encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 GCM encryption and authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 GMAC authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 CCM encryption and authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 STM32 cryptolib AES flowchart examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 STM32 cryptolib AES flowchart examples (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 Encryption key derivation for ECB/CBC decryption (Mode 2). . . . . . . . . . . . . . . . . . . . . . 677 Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 ECB encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 ECB decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 CBC encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 CBC decryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 ECB/CBC encryption (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 ECB/CBC decryption (Mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 Message construction in CTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 CTR encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 CTR decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 Message construction in GCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 GCM authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 Message construction in GMAC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 GMAC authentication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 Message construction in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 CCM mode authenticated decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 128-bit block construction with respect to data swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 DMA transfer of a 128-bit data block during input phase . . . . . . . . . . . . . . . . . . . . . . . . . 701 DMA transfer of a 128-bit data block during output phase . . . . . . . . . . . . . . . . . . . . . . . . 702 AES interrupt signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 722 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 722 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 726 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 726 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 RM0394 Rev 4 53/1600 59 List of figures Figure 196. Figure 197. Figure 198. Figure 199. Figure 200. Figure 201. Figure 202. Figure 203. Figure 204. Figure 205. Figure 206. Figure 207. Figure 208. Figure 209. Figure 210. Figure 211. Figure 212. Figure 213. Figure 214. Figure 215. Figure 216. Figure 217. Figure 218. Figure 219. Figure 220. Figure 221. Figure 222. Figure 223. Figure 224. Figure 225. Figure 226. Figure 227. Figure 228. Figure 229. Figure 230. Figure 231. Figure 232. Figure 233. Figure 234. Figure 235. Figure 236. Figure 237. Figure 238. Figure 239. Figure 240. Figure 241. Figure 242. Figure 243. Figure 244. Figure 245. Figure 246. Figure 247. 54/1600 RM0394 Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 730 Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 731 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 732 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 733 Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 734 Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 735 External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 TIM1 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 737 TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 741 Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . . 743 Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 743 Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . . 744 PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 752 Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . . 754 Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . . 755 Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 756 Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 Various output behavior in response to a break event on BRK (OSSI = 1) . . . . . . . . . . . 760 PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . . . . . . . . . . . . 761 PWM output state following BRK assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 768 Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 769 Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 776 General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 820 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 820 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822 RM0394 Rev 4 RM0394 Figure 248. Figure 249. Figure 250. Figure 251. Figure 252. Figure 253. Figure 254. Figure 255. Figure 256. Figure 257. Figure 258. Figure 259. Figure 260. Figure 261. Figure 262. Figure 263. Figure 264. Figure 265. Figure 266. Figure 267. Figure 268. Figure 269. Figure 270. Figure 271. Figure 272. Figure 273. Figure 274. Figure 275. Figure 276. Figure 277. Figure 278. Figure 279. Figure 280. Figure 281. Figure 282. Figure 283. Figure 284. Figure 285. Figure 286. Figure 287. Figure 288. Figure 289. Figure 290. Figure 291. Figure 292. Figure 293. Figure 294. Figure 295. Figure 296. Figure 297. Figure 298. List of figures Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823 Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 823 Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 824 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 828 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 829 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 830 Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 831 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 832 TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 Capture/Compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 836 Capture/Compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 Output stage of Capture/Compare channel (channel 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 837 PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843 Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 844 Combined PWM mode on channels 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 851 Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 852 Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853 Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855 Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 856 Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856 Gating TIMz with OC1REF of TIMy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 Gating TIMz with Enable of TIMy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 Triggering TIMz with update of TIMy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 Triggering TIMz with Enable of TIMy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 Triggering TIMy3 and TIMz2 with TIMy3 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889 TIM16 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 892 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 892 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895 RM0394 Rev 4 55/1600 59 List of figures RM0394 Figure 299. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895 Figure 300. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896 Figure 301. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896 Figure 302. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 898 Figure 303. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 899 Figure 304. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899 Figure 305. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 Figure 306. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 901 Figure 307. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901 Figure 308. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 902 Figure 309. Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . . 902 Figure 310. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 Figure 311. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906 Figure 312. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907 Figure 313. Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908 Figure 314. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909 Figure 315. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 909 Figure 316. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 910 Figure 317. Break circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912 Figure 318. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914 Figure 319. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915 Figure 320. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917 Figure 321. Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918 Figure 322. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919 Figure 323. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920 Figure 324. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921 Figure 325. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968 Figure 326. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 970 Figure 327. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 970 Figure 328. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 Figure 329. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972 Figure 330. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972 Figure 331. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973 Figure 332. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973 Figure 333. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974 Figure 334. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 975 Figure 335. Low-power timer block diagram for STM32L43xxx/44xxx/45xxx/46xxx . . . . . . . . . . . . . . 982 Figure 336. Low-power timer block diagram for STM32L41xxx/42xxx . . . . . . . . . . . . . . . . . . . . . . . . 983 Figure 337. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 Figure 338. LPTIM output waveform, single counting mode configuration . . . . . . . . . . . . . . . . . . . . . 986 Figure 339. LPTIM output waveform, single counting mode configuration when repetition register content is different than zero (with PRELOAD = 1) . . . . . . . . . . 987 Figure 340. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987 Figure 341. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . . 988 Figure 342. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990 Figure 343. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994 Figure 344. Continuous counting mode when repetition register LPTIM_RCR 56/1600 RM0394 Rev 4 RM0394 Figure 345. Figure 346. Figure 347. Figure 348. Figure 349. Figure 350. Figure 351. Figure 352. Figure 353. Figure 354. Figure 355. Figure 356. Figure 357. Figure 358. Figure 359. Figure 360. Figure 361. Figure 362. Figure 363. Figure 364. Figure 365. Figure 366. Figure 367. Figure 368. Figure 369. Figure 370. Figure 371. Figure 372. Figure 373. Figure 374. Figure 375. Figure 376. Figure 377. Figure 378. Figure 379. Figure 380. Figure 381. Figure 382. Figure 383. Figure 384. Figure 385. Figure 386. Figure 387. Figure 388. Figure 389. Figure 390. Figure 391. Figure 392. Figure 393. Figure 394. Figure 395. List of figures different from zero (with PRELOAD = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995 IRTIM internal hardware connections with TIM15 and TIM16 . . . . . . . . . . . . . . . . . . 1012 Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031 TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084 I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131 Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132 I2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135 Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136 Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137 Slave initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140 Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0. . . . . . . . . . . . 1142 Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1. . . . . . . . . . . . 1143 Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144 Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . 1145 Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . 1146 Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146 Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148 Master initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150 10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150 10-bit address read access with HEAD10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151 Transfer sequence flowchart for I2C master transmitter for N≤255 bytes . . . . . . . . . . . 1152 Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . . . . . . . . 1153 Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154 Transfer sequence flowchart for I2C master receiver for N≤255 bytes. . . . . . . . . . . . . . 1156 Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . . . . . . . . . . 1157 Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1158 Timeout intervals for tLOW:SEXT, tLOW:MEXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162 Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . 1166 Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . 1167 Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . 1168 Bus transfer diagrams for SMBus slave receiver (SBC=1). . . . . . . . . . . . . . . . . . . . . . . 1169 Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170 Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172 USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198 Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200 Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202 TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203 Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204 Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215 Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216 Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . 1219 Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . 1220 USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221 USART data clock timing diagram (M bits = 00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221 USART data clock timing diagram (M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222 RM0394 Rev 4 57/1600 59 List of figures Figure 396. Figure 397. Figure 398. Figure 399. Figure 400. Figure 401. Figure 402. Figure 403. Figure 404. Figure 405. Figure 406. Figure 407. Figure 408. Figure 409. Figure 410. Figure 411. Figure 412. Figure 413. Figure 414. Figure 415. Figure 416. Figure 417. Figure 418. Figure 419. Figure 420. Figure 421. Figure 422. Figure 423. Figure 424. Figure 425. Figure 426. Figure 427. Figure 428. Figure 429. Figure 430. Figure 431. Figure 432. Figure 433. Figure 434. Figure 435. Figure 436. Figure 437. Figure 438. Figure 439. Figure 440. Figure 441. Figure 442. Figure 443. Figure 444. Figure 445. Figure 446. 58/1600 RM0394 RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222 ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224 Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225 IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229 IrDA data modulation (3/16) -Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230 Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231 Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232 Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232 RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233 RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234 USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237 LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265 Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267 Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268 TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270 Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277 Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278 Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281 Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282 Hardware flow control between 2 LPUARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282 RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283 RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284 LPUART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288 SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305 Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306 Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307 Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308 Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309 Multi-master application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310 Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311 Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312 Data alignment when data length is not equal to 8-bit or 16-bit . . . . . . . . . . . . . . . . . . . 1313 Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . 1317 Master full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1320 Slave full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1321 Master full-duplex communication with CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1322 Master full-duplex communication in packed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1323 NSSP pulse generation in Motorola SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1326 TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327 SAI functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341 Audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344 FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . . . . . . . 1346 FS role is start of frame (FSDEF = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347 Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . . . . . . . . . . . . . . . . . . . . . 1348 First bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348 Audio block clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349 AC’97 audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353 SPDIF format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354 SAI_xDR register ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355 Data companding hardware in an audio block in the SAI . . . . . . . . . . . . . . . . . . . . . . . . 1359 Tristate strategy on SD output line on an inactive slot . . . . . . . . . . . . . . . . . . . . . . . . . . 1360 RM0394 Rev 4 RM0394 Figure 447. Figure 448. Figure 449. Figure 450. Figure 451. Figure 452. Figure 453. Figure 454. Figure 455. Figure 456. Figure 457. Figure 458. Figure 459. Figure 460. Figure 461. Figure 462. Figure 463. Figure 464. Figure 465. Figure 466. Figure 467. Figure 468. Figure 469. Figure 470. Figure 471. Figure 472. Figure 473. Figure 474. Figure 475. Figure 476. Figure 477. Figure 478. Figure 479. Figure 480. Figure 481. Figure 482. Figure 483. Figure 484. Figure 485. Figure 486. Figure 487. Figure 488. Figure 489. Figure 490. Figure 491. Figure 492. Figure 493. Figure 494. Figure 495. Figure 496. Figure 497. List of figures Tristate on output data line in a protocol like I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361 Overrun detection error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362 FIFO underrun event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362 S1 signal coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1390 S2 signal coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1391 SWPMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392 SWP bus states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394 SWP frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395 SWPMI No software buffer mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396 SWPMI No software buffer mode transmission, consecutive frames . . . . . . . . . . . . . . . 1397 SWPMI Multi software buffer mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399 SWPMI No software buffer mode reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401 SWPMI single software buffer mode reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402 SWPMI Multi software buffer mode reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404 SWPMI single buffer mode reception with CRC error. . . . . . . . . . . . . . . . . . . . . . . . . . . 1405 “No response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418 (Multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418 (Multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418 Sequential read operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419 Sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419 SDMMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419 SDMMC adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421 Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422 SDMMC_CK clock dephasing (BYPASS = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423 SDMMC adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423 Command path state machine (SDMMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424 SDMMC command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425 Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1427 Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1428 CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477 Single-CAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478 bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480 bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481 bxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481 bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482 Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483 Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484 Filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . 1487 Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488 Filtering mechanism - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489 CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492 CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493 Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494 CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506 USB peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521 Packet buffer areas with examples of buffer description table locations . . . . . . . . . . . . 1525 Block diagram of STM32 MCU and Cortex®-M4-level debug support . . . . . . . . . . . . . . 1553 SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555 JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559 TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577 RM0394 Rev 4 59/1600 59 Documentation conventions RM0394 1 Documentation conventions 1.1 General information The STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx devices have an Arm®(a) Cortex®-M4 core 1.2 List of abbreviations for registers The following abbreviations(b) are used in register descriptions: read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit. write-only (w) Software can only write to this bit. Reading this bit returns the reset value. read/clear write0 (rc_w0) Software can read as well as clear this bit by writing 0. Writing 1 has no effect on the bit value. read/clear write1 (rc_w1) Software can read as well as clear this bit by writing 1. Writing 0 has no effect on the bit value. read/clear write (rc_w) Software can read as well as clear this bit by writing to the register. The value written to this bit is not important. read/clear by read (rc_r) Software can read this bit. Reading this bit automatically clears it to 0. Writing this bit has no effect on the bit value. read/set by read (rs_r) Software can read this bit. Reading this bit automatically sets it to 1. Writing this bit has no effect on the bit value. read/set (rs) Software can read as well as set this bit. Writing 0 has no effect on the bit value. read/write once (rwo) Software can only write once to this bit and can also read it at any time. Only a reset can return the bit to its reset value. toggle (t) The software can toggle this bit by writing 1. Writing 0 has no effect. read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on the bit value. Reserved (Res.) Reserved bit, must be kept at reset value. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. b. This is an exhaustive list of all abbreviations applicable to STM microcontrollers, some of them may not be used in the current document. 60/1600 RM0394 Rev 4 RM0394 1.3 Documentation conventions Glossary This section gives a brief definition of acronyms and abbreviations used in this document: • 1.4 Word: data of 32-bit length. • Half-word: data of 16-bit length. • Byte: data of 8-bit length. • IAP (in-application programming): IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running. • ICP (in-circuit programming): ICP is the ability to program the Flash memory of a microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the device is mounted on the user application board. • Option bytes: product configuration bits stored in the Flash memory. • OBL: option byte loader. • AHB: advanced high-performance bus. • APB: advanced peripheral bus. Availability of peripherals For availability of peripherals and their number across all sales types, refer to the particular device datasheet. 1.5 Product specific features Table 1. Product specific features STM32 L412xx STM32 L422xx STM32 L431xx STM32 L432xx STM32 L433xx STM32 L442xx STM32 L443xx STM32 L451xx STM32 L452xx STM32 L462xx ADC ADC1 ADC2 ADC1 ADC2 ADC1 - ADC1 - ADC1 - ADC1 - ADC1 - ADC1 - ADC1 - ADC1 - DAC - - DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 COMP COMP1 - COMP1 - COMP1 COMP2 COMP1 COMP2 COMP1 COMP2 COMP1 COMP2 COMP1 COMP2 COMP1 COMP2 COMP1 COMP2 COMP1 COMP2 DFSDM - - - - - - - LCD - - - - LCD - LCD Feature DFSDM1 DFSDM1 DFSDM1 - - - AES - AES - - - AES AES - - AES TIM TIM1 TIM2 TIM6 TIM15 TIM16 TIM1 TIM2 TIM6 TIM15 TIM16 TIM1 TIM2 TIM6 TIM7 TIM15 TIM16 TIM1 TIM2 TIM6 TIM7 TIM15 TIM16 TIM1 TIM2 TIM6 TIM7 TIM15 TIM16 TIM1 TIM2 TIM6 TIM7 TIM15 TIM16 TIM1 TIM2 TIM6 TIM7 TIM15 TIM16 TIM1 TIM2 TIM3 TIM6 TIM15 TIM16 TIM1 TIM2 TIM3 TIM6 TIM15 TIM16 TIM1 TIM2 TIM3 TIM6 TIM15 TIM16 I2C I2C1 I2C2 I2C3 - I2C1 I2C2 I2C3 - I2C1 I2C2 I2C3 - I2C1 I2C3 - I2C1 I2C2 I2C3 - I2C1 I2C3 - I2C1 I2C2 I2C3 - I2C1 I2C2 I2C3 I2C4 I2C1 I2C2 I2C3 I2C4 I2C1 I2C2 I2C3 I2C4 RM0394 Rev 4 61/1600 62 Documentation conventions RM0394 Table 1. Product specific features (continued) Feature USART STM32 L412xx STM32 L422xx STM32 L431xx STM32 L432xx STM32 L433xx STM32 L442xx STM32 L443xx STM32 L451xx STM32 L452xx STM32 L462xx USART1 USART1 USART1 USART1 USART1 USART1 USART1 USART1 USART1 USART1 USART2 USART2 USART2 USART2 USART2 USART2 USART2 USART2 USART2 USART2 USART3 USART3 USART3 USART3 USART3 USART3 USART3 USART3 UART4 UART4 UART4 LPUART LPUART1 LPUART1 LPUART1 LPUART1 LPUART1 LPUART1 LPUART1 LPUART1 LPUART1 LPUART1 SPI SPI1 SPI2 - SPI1 SPI2 - SPI1 SPI2 SPI3 SPI1 SPI3 SPI1 SPI2 SPI3 SPI1 SPI3 SPI1 SPI2 SPI3 SPI1 SPI2 SPI3 SPI1 SPI2 SPI3 SPI1 SPI2 SPI3 SAI - - SAI SAI SAI SAI SAI SAI SAI SAI SWPMI - - SWPMI1 SWPMI1 SWPMI1 SWPMI1 SWPMI1 - - - SDMMC USB CAN1 62/1600 - - SDMMC - SDMMC - USB FS USB FS - USB FS USB FS USB FS USB FS - USB FS USB FS - - CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 CAN1 RM0394 Rev 4 SDMMC SDMMC SDMMC SDMMC RM0394 System and memory overview 2 System and memory overview 2.1 System architecture The main system consists of 32-bit multilayer AHB bus matrix that interconnects: • • Five masters: – Cortex®-M4 with FPU core I-bus – Cortex®-M4 with FPU core D-bus – Cortex®-M4 with FPU core S-bus – DMA1 – DMA2 Seven slaves: – Internal Flash memory on the ICode bus – Internal Flash memory on DCode bus – Internal SRAM1 – Internal SRAM2 – AHB1 peripherals including AHB to APB bridges and APB peripherals (connected to APB1 and APB2) – AHB2 peripherals – The external memory controller (QUADSPI) The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. This architecture is shown in Figure 1: RM0394 Rev 4 63/1600 65 System and memory overview RM0394 Figure 1. System architecture $50 &257(;0ZLWK)38 6 6 6 '0$ '0$ 6 6 0 ,&RGH $&&(/ )/$6+ 0 '&RGH 0 65$0 0 65$0 0 $+% SHULSKHUDOV 0 $+% SHULSKHUDOV 0 48$'63, %XV0DWUL[6 06Y9 2.1.1 S0: I-bus This bus connects the instruction bus of the Cortex®-M4 core to the BusMatrix. This bus is used by the core to fetch instructions. The targets of this bus are the internal Flash memory, SRAM1, SRAM2 and external memories through QUADSPI. 2.1.2 S1: D-bus This bus connects the data bus of the Cortex®-M4 core to the BusMatrix. This bus is used by the core for literal load and debug access. The targets of this bus are the internal Flash memory, SRAM1, SRAM2 and external memories through QUADSPI. 64/1600 RM0394 Rev 4 RM0394 2.1.3 System and memory overview S2: S-bus This bus connects the system bus of the Cortex®-M4 core to the BusMatrix. This bus is used by the core to access data located in a peripheral or SRAM area. The targets of this bus are the SRAM1, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the external memories through the QUADSPI. 2.1.4 S3, S4: DMA-bus This bus connects the AHB master interface of the DMA to the BusMatrix.The targets of this bus are the SRAM1 and SRAM2, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the external memories through the QUADSPI. 2.1.5 BusMatrix The BusMatrix manages the access arbitration between masters. The arbitration uses a Round Robin algorithm. The BusMatrix is composedof five masters (CPU AHB, system bus, DCode bus, ICode bus, DMA1 and DMA2 bus) and seven slaves (FLASH, SRAM1, SRAM2, AHB1 (including APB1 and APB2), AHB2 and QUADSPI). AHB/APB bridges The two AHB/APB bridges provide full synchronous connections between the AHB and the two APB buses, allowing flexible selection of the peripheral frequency. Refer to Section 2.2.2: Memory map and register boundary addresses on page 67 for the address mapping of the peripherals connected to this bridge. After each device reset, all peripheral clocks are disabled (except for the SRAM1/2 and Flash memory interface). Before using a peripheral you have to enable its clock in the RCC_AHBxENR and the RCC_APBxENR registers. Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector. RM0394 Rev 4 65/1600 65 RM0394 2.2 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant. The addressable memory space is divided into eight main blocks, of 512 Mbytes each. 66/1600 RM0394 Rev 4 RM0394 2.2.2 Memory map and register boundary addresses Figure 2. Memory map [%))))))) [)))))))) &RUWH[0 ZLWK)38 LQWHUQDO SHULSKHUDOV [$ [$ [( [))))))) [& [ [ [& [ 48$'63, UHJLVWHUV [ [$ [ [$ [ 48$'63, )ODVKEDQN [ [ [ 5HVHUYHG 48$'63,UHJLVWHUV 5HVHUYHG $+% 5HVHUYHG $+% 5HVHUYHG $3% 5HVHUYHG $3% [))))))) 5HVHUYHG [ [))) [))) [))) [ 3HULSKHUDOV [))) [))) [ 65$0 65$0 [ [ &RGH [ [ [ [ 5HVHUYHG 2SWLRQE\WHV 5HVHUYHG 273DUHD 6\VWHPPHPRU\ 5HVHUYHG 65$0 5HVHUYHG )ODVKPHPRU\ 5HVHUYHG )ODVKV\VWHPPHPRU\ RU65$0GHSHQGLQJ RQ%227FRQILJXUDWLRQ 06Y9 1. 0x2000 8000 for STM32L41xxx and STM32L42xxx devices 0x2000 C000 for STM32L43xxx and STM32L44xxx devices 0x2002 0000 for STM32L45xxx and STM32L46xxx devices 2. 0x1000 2000 for STM32L41xxx and STM32L42xxx devices 0x1000 4000 for STM32L43xxx and STM32L44xxx devices 0x1000 8000 for STM32L45xxx and STM32L46xxx devices It is forbidden to access QUADSPI Flash bank area before having properly configured and enabled the QUADSPI peripheral. All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to the following table. RM0394 Rev 4 67/1600 76 RM0394 The following table gives the boundary addresses of the peripherals available in the devices. Table 2. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx memory map and peripheral register boundary addresses Bus AHB2 Boundary address Size (bytes) Peripheral 0x5006 0800 - 0x5006 0BFF 1 KB RNG 0x5006 0400 - 0x5006 07FF 1 KB Reserved AES Peripheral register map Section 24.8.4: RNG register map (1) Section 25.7.18: AES register map 0x5006 0000 - 0x5006 03FF 1 KB 0x5004 0400 - 0x5005 FFFF 127 KB 0x5004 0000 - 0x5004 03FF 1 KB ADC 0x5000 0000 - 0x5003 FFFF 16 KB Reserved - 0x4800 2000 - 0x4FFF FFFF ~127 MB Reserved - 0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH 0x4800 1400 - 0x4800 1BFF 2 KB Reserved Reserved Section 16.7.4: ADC register map on page 482 (2) (3) Section 8.4.12: GPIO register map Section 8.4.12: GPIO register map 0x4800 1000 - 0x4800 13FF 1 KB GPIOE 0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD(2) Section 8.4.12: GPIO register map 0x4800 0800 - 0x4800 0BFF 1 KB GPIOC Section 8.4.12: GPIO register map 0x4800 0400 - 0x4800 07FF 1 KB GPIOB Section 8.4.12: GPIO register map 0x4800 0000 - 0x4800 03FF 1 KB GPIOA Section 8.4.12: GPIO register map 0x4002 4400 - 0x47FF FFFF ~127 MB 0x4002 4000 - 0x4002 43FF 1 KB TSC 0x4002 3400 - 0x4002 3FFF 1 KB Reserved 0x4002 3000 - 0x4002 33FF 1 KB CRC 0x4002 2400 - 0x4002 2FFF 3 KB Reserved 0x4002 2000 - 0x4002 23FF 1 KB FLASH registers AHB1 0x4002 1400 - 0x4002 1FFF 3 KB Reserved 0x4002 1000 - 0x4002 13FF 1 KB RCC 0x4002 0800 - 0x4002 0FFF 2 KB Reserved 0x4002 0400 - 0x4002 07FF 1 KB DMA2 Section 11.6.8: DMA register map and reset values 0x4002 0000 - 0x4002 03FF 1 KB DMA1 Section 11.6.8: DMA register map and reset values 0x4001 6400 - 0x4001 FFFF 39 KB Reserved APB2 0x4001 6000 - 0x4001 63FF 1 KB DFSDM1(3) 0x4001 5800 - 0x4001 5FFF 2 kB Reserved 68/1600 Reserved RM0394 Rev 4 Section 23.6.11: TSC register map Section 14.4.6: CRC register map Section 3.7.13: FLASH register map Section 6.4.32: RCC register map - Section 21.8.16: DFSDM register map - RM0394 Table 2. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx memory map and peripheral register boundary addresses (continued) Bus Boundary address Size (bytes) Peripheral (3) Peripheral register map Section 41.6.17: SAI register map 0x4001 5400 - 0x4001 57FF 1 KB SAI1 0x4001 4400 - 0x4000 53FF 2 KB Reserved 0x4001 4400 - 0x4001 47FF 1 KB TIM16 Section 28.7.18: TIM16 register map 0x4001 4000 - 0x4001 43FF 1 KB TIM15 Section 28.6.20: TIM15 register map 0x4001 3C00 - 0x4001 3FFF 1 KB Reserved 0x4001 3800 - 0x4001 3BFF 1 KB USART1 0x4001 3400 - 0x4001 37FF 1 KB Reserved 0x4001 3000 - 0x4001 33FF 1 KB SPI1 Section 40.6.8: SPI register map APB2 0x4001 2C00 - 0x4001 2FFF 1 KB TIM1 Section 26.4.29: TIM1 register map 0x4001 2800 - 0x4001 2BFF 1 KB SDMMC(2) (3) Section 43.8.16: SDMMC register map 0x4001 2000 - 0x4001 27FF 2 KB Reserved 0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL 0x4001 0800- 0x4001 1BFF 5 KB Reserved 0x4001 0400 - 0x4001 07FF 1 KB EXTI 0x4001 0200 - 0x4001 03FF 0x4001 0030 - 0x4001 01FF Section 38.8.12: USART register map - - 1 KB Section 4.4.8: Firewall register map Section 13.5.13: EXTI register map COMP 0x4001 0000 - 0x4001 002F APB1 - VREFBUF Section 19.6.3: COMP register map (3) SYSCFG Section 18.3.3: VREFBUF register map Section 9.2.11: SYSCFG register map 0x4000 9800 - 0x4000 FFFF 26 KB Reserved 0x4000 9400 - 0x4000 97FF 1 KB LPTIM2 0x4000 8C00 - 0x4000 93FF 2 KB Reserved 0x4000 8800 - 0x4000 8BFF 1 KB SWPMI1(4) Section 42.6.10: SWPMI register map and reset value table 0x4000 8400 - 0x4000 87FF 1 KB I2C4(5) Section 37.7.12: I2C register map 0x4000 8000 - 0x4000 83FF 1 KB LPUART1 Section 39.7.10: LPUART register map 0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1 Section 30.7.13: LPTIM register map 0x4000 7800 - 0x4000 7BFF 1 KB OPAMP Section 20.5.4: OPAMP register map 0x4000 7400 - 0x4000 77FF 1 KB DAC1 (3) 0x4000 7000 - 0x4000 73FF 1 KB PWR 0x4000 6C00 - 0x4000 6FFF 1 KB USB SRAM(6) 0x4000 6800 - 0x4000 6BFF 1 KB USB FS(6) 0x4000 6400 - 0x4000 67FF 1 KB CAN1(3) Section 44.9: CAN registers 0x4000 6000 - 0x4000 63FF 1 KB CRS Section 7.6.5: CRS register map 0x4000 5C00- 0x4000 5FFF 1 KB I2C3 Section 37.7.12: I2C register map 0x4000 5800 - 0x4000 5BFF 1 KB I2C2 Section 37.7.12: I2C register map RM0394 Rev 4 Section 30.7.13: LPTIM register map - Section 17.7.21: DAC register map Section 5.4.20: PWR register map and reset value table Section 45.6.3: USB register map 69/1600 76 RM0394 Table 2. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx memory map and peripheral register boundary addresses (continued) Bus Boundary address Size (bytes) Peripheral 0x4000 5400 - 0x4000 57FF 1 KB I2C1 0x4000 5000 - 0x4000 53FF 1 KB Reserved Peripheral register map Section 37.7.12: I2C register map (5) Section 38.8.12: USART register map 0x4000 4C00 - 0x4000 4FFF 1 KB USART4 0x4000 4800 - 0x4000 4BFF 1 KB USART3 Section 38.8.12: USART register map 0x4000 4400 - 0x4000 47FF 1 KB USART2 Section 38.8.12: USART register map 0x4000 4000 - 0x4000 43FF 1 KB Reserved (3) Section 40.6.8: SPI register map 0x4000 3C00 - 0x4000 3FFF 1 KB SPI3 0x4000 3800 - 0x4000 3BFF 1 KB SPI2 0x4000 3400 - 0x4000 37FF 1 KB Reserved APB1 0x4000 3000 - 0x4000 33FF 1 KB IWDG Section 32.4.6: IWDG register map 0x4000 2C00 - 0x4000 2FFF 1 KB WWDG Section 33.4.4: WWDG register map 0x4000 2800 - 0x4000 2BFF 1 KB RTC Section 36.6.21: RTC register map 0x4000 2400 - 0x4000 27FF 1 KB LCD(7) Section 22.6.6: LCD register map 0x4000 1800 - 0x4000 2400 3 KB Reserved 0x4000 1400 - 0x4000 17FF 1 KB TIM7 (3) (8) 0x4000 1000 - 0x4000 13FF 1 KB TIM6 0x4000 0800 - 0x4000 0FFF 2 KB Reserved 0x4000 0400 - 0x4000 07FF 1 KB TIM3(5) Section 27.4.21: TIMx register map 0x4000 0000 - 0x4000 03FF 1 KB TIM2 Section 27.4.21: TIMx register map Section 40.6.8: SPI register map - Section 29.4.9: TIM6/TIM7 register map Section 29.4.9: TIM6/TIM7 register map - 1. Available on STM32L44xxx and STM32L46xxx devices only. 2. Not available on STM32L42xxx, STM32L432xx and STM32L442xx devices. 3. Not available on STM32L41xxx and STM32L42xxx devices. 4. Available on STM32L43xxx and STM32L44xxx devices only. 5. Available on STM32L45xxx and STM32L46xxx devices only. 6. Available on STM32L4x2xx and STM32L4x3xx devices only. 7. Available on STM32L4x3xx devices only. 8. Not available on STM32L45xxx and STM32L46xxx devices. 2.3 Bit banding The Cortex®-M4 memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region. In the STM32L43xxx/44xxx/45xxx/46xxx devices both the peripheral registers and the SRAM1 are mapped to a bit-band region, so that single bit-band write and read operations are allowed. The operations are only available for Cortex®-M4 accesses, and not from other bus masters (e.g. DMA). 70/1600 RM0394 Rev 4 RM0394 A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4) where: – bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit – bit_band_base is the starting address of the alias region – byte_offset is the number of the byte in the bit-band region that contains the targeted bit – bit_number is the bit position (0-7) of the targeted bit Example The following example shows how to map bit 2 of the byte located at SRAM1 address 0x20000300 to the alias region: 0x22006008 = 0x22000000 + (0x300*32) + (2*4) Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit 2 of the byte at SRAM1 address 0x20000300. Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM1 address 0x20000300 (0x01: bit set; 0x00: bit reset). For more information on bit-banding, refer to the Cortex®-M4 programming manual (see Related documents on page 1). 2.4 Embedded SRAM The STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx devices feature up to 196 Kbytes SRAM: • Up to 128 Kbytes SRAM1 • Up to 32 Kbyte SRAM2. These SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). These memories can be addressed at maximum system clock frequency without wait state and thus by both CPU and DMA. The CPU can access the SRAM1 through the system bus or through the ICode/DCode buses when boot from SRAM1 is selected or when physical remap is selected (Section 9.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller). To get the maximum performance on SRAM1 execution, physical remap should be selected (boot or software selection). Execution can be performed from CCM SRAM with maximum performance without any remap thanks to access through ICode bus. 2.4.1 SRAM2 parity check The user can enable the SRAM2 parity check using the option bit SRAM2_PE in the user option byte (refer to Section 3.4.1: Option bytes description). The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in order to increase memory robustness, as required for instance by Class B or SIL norms. RM0394 Rev 4 71/1600 76 RM0394 The parity bits are computed and stored when writing into the SRAM2. Then, they are automatically checked when reading. If one bit fails, an NMI is generated. The same error can also be linked to the BRK_IN Break input of TIM1/TIM15/TIM16, with the SPL control bit in the SYSCFG configuration register 2 (SYSCFG_CFGR2). The SRAM2 Parity Error flag (SPF) is available in the SYSCFG configuration register 2 (SYSCFG_CFGR2). Note: When enabling the RAM parity check, it is advised to initialize by software the whole RAM memory at the beginning of the code, to avoid getting parity errors when reading noninitialized locations. 2.4.2 SRAM2 Write protection The SRAM2 can be write protected with a page granularity of 1 Kbyte. Table 3. SRAM2 organization Page number Start address End address Page 0 0x1000 0000 0x1000 03FF Page 1 0x1000 0400 0x1000 07FF Page 2 0x1000 0800 0x1000 0BFF Page 3 0x1000 0C00 0x1000 0FFF Page 4 0x1000 1000 0x1000 13FF Page 5 0x1000 1400 0x1000 17FF Page 6 0x1000 1800 0x1000 1BFF Page 7 0x1000 1C00 0x1000 1FFF Table 4. SRAM2 organization (continuation for STM32L43x/44x/45x/46x devices only) Page number Start address End address Page 8 0x1000 2000 0x1000 23FF Page 9 0x1000 2400 0x1000 27FF Page 10 0x1000 2800 0x1000 2BFF Page 11 0x1000 2C00 0x1000 2FFF Page 12 0x1000 3000 0x1000 33FF Page 13 0x1000 3400 0x1000 37FF Page 14 0x1000 3800 0x1000 3BFF Page 15 0x1000 3C00 0x1000 3FFF Table 5. SRAM2 organization (continuation for STM32L45x and STM32L46x devices only) 72/1600 Page number Start address End address Page 16 0x1000 4000 0x1000 43FF Page 17 0x1000 4400 0x1000 47FF RM0394 Rev 4 RM0394 Table 5. SRAM2 organization (continuation for STM32L45x and STM32L46x devices only) (continued) Page number Start address End address Page 18 0x1000 4800 0x1000 4BFF Page 19 0x1000 4C00 0x1000 4FFF Page 20 0x1000 5000 0x1000 53FF Page 21 0x1000 5400 0x1000 57FF Page 22 0x1000 5800 0x1000 5BFF Page 23 0x1000 5C00 0x1000 5FFF Page 24 0x1000 6000 0x1000 63FF Page 25 0x1000 6400 0x1000 67FF Page 26 0x1000 6800 0x1000 6BFF Page 27 0x1000 6C00 0x1000 6FFF Page 28 0x1000 7000 0x1000 73FF Page 29 0x1000 7400 0x1000 77FF Page 30 0x1000 7800 0x1000 7BFF Page 31 0x1000 7C00 0x1000 7FFF The write protection can be enabled in SYSCFG SRAM2 write protection register (SYSCFG_SWPR) in the SYSCFG block. This is a register with write ‘1’ once mechanism, which means by writing ‘1’ on a bit it will setup the write protection for that page of SRAM and it can be removed/cleared by a system reset only. 2.4.3 SRAM2 Read protection The SRAM2 is protected with the Read protection (RDP). Refer to Section 3.5.1: Read protection (RDP) for more details. 2.4.4 SRAM2 Erase The SRAM2 can be erased with a system reset using the option bit SRAM2_RST in the user option byte (refer to Section 3.4.1: Option bytes description). The SRAM2 erase can also be requested by software by setting the bit SRAM2ER in the SYSCFG SRAM2 control and status register (SYSCFG_SCSR). RM0394 Rev 4 73/1600 76 RM0394 2.5 Flash memory overview The Flash memory is composed of two distinct physical areas: • The main Flash memory block. It contains the application program and user data if necessary. • The information block. It is composed of three parts: – Option bytes for hardware and memory protection user configuration. – System memory that contains the ST proprietary code. – OTP (one-time programmable) area The Flash interface implements instruction access and data access based on the AHB protocol. It also implements the logic necessary to carry out the Flash memory operations (program/erase) controlled through the Flash registers Refer to Section 3: Embedded Flash memory (FLASH) for more details. 2.6 Boot configuration In the STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx, three different boot modes can be selected through the BOOT0 pin or the nBOOT0 bit into the FLASH_OPTR register (if the nSWBOOT0 bit is cleared into the FLASH_OPTR register), and nBOOT1 bit in the FLASH_OPTR register, as shown in the following table. Table 6. Boot modes nBOOT1 nBOOT0 BOOT0 nSWBOOT0 FLASH_OPTR[23] FLASH_OPTR[27] pin PH3 FLASH_OPTR[26] Main Flash empty(1) X X 0 1 0 Main Flash memory is selected as boot area X X 0 1 1 System memory is selected as boot area X 1 X 0 X Main Flash memory is selected as boot area 0 X 1 1 X Embedded SRAM1 is selected as boot area 0 0 X 0 X Embedded SRAM1 is selected as boot area 1 X 1 1 X System memory is selected as boot area 1 0 X 0 X System memory is selected as boot area Boot Memory Space Alias 1. A Flash empty check mechanism is implemented to force the boot from system Flash if the first Flash memory location is not programmed (0xFFFF FFFF) and if the boot selection was configured to boot from the main Flash. The values on both BOOT0 (coming from the pin or the option bit) and nBOOT1 bit are latched on the 4th edge of the internal startup clock source after reset release. It is up to the user to set nBOOT1 and BOOT0 to select the required boot mode. 74/1600 RM0394 Rev 4 RM0394 The BOOT0 pin or user option bit (depending on the nSWBOOT0 bit value in the FLASH_OPTR register), and nBOOT1 bit are also re-sampled when exiting from Standby mode. Consequently they must be kept in the required Boot mode configuration in Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory at 0x0000 0004. Depending on the selected boot mode, main Flash memory, system memory or SRAM1 is accessible as follows: • Boot from main Flash memory: the main Flash memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x0800 0000). In other words, the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000. • Boot from system memory: the system memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x1FFF 0000). • Boot from the embedded SRAM1: the SRAM1 is aliased in the boot memory space (0x0000 0000), but it is still accessible from its original memory space (0x2000 0000). PH3/BOOT0 GPIO is configured in: Note: • Input mode during the complete reset phase if the option bit nSWBOOT0 is set into the FLASH_OPTR register and then switches automatically in analog mode after reset is released (BOOT0 pin). • Input mode from the reset phase to the completion of the option byte loading if the bit nSWBOOT0 is cleared into the FLASH_OPTR register (BOOT0 value coming from the option bit). It switches then automatically to the analog mode even if the reset phase is not complete. When the device boots from SRAM, in the application initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and the offset register. Physical remap Once the boot mode is selected, the application software can modify the memory accessible in the code area (in this way the code can be executed through the ICode bus in place of the System bus). This modification is performed by programming the SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller. The following memories can thus be remapped: • Main Flash memory • System memory • Embedded SRAM1 • Quad-SPI memory Table 7. Memory mapping vs. Boot mode/Physical remap Addresses Boot/Remap in main Flash memory Boot/Remap in embedded SRAM1 Boot/Remap in Remap in QUADSystem memory SPI 0x2000 0000 - 0x2001 7FFFF(1) SRAM1 SRAM1 SRAM1 SRAM1 0x1FFF 0000 - 0x1FFF FFFF System memory/OTP/Options bytes System memory/OTP/Options bytes System memory/OTP/Options bytes System memory/OTP/Options bytes RM0394 Rev 4 75/1600 76 RM0394 Table 7. Memory mapping vs. Boot mode/Physical remap (continued) Boot/Remap in main Flash memory Addresses 0x1008 0000(1) - 0x1FFE FFFF Boot/Remap in embedded SRAM1 Boot/Remap in Remap in QUADSystem memory SPI Reserved Reserved Reserved Reserved SRAM2 SRAM2 SRAM2 SRAM2 Reserved Reserved Reserved Reserved 0x0800 0000 - 0x0807 FFFF(1) Flash memory Flash memory Flash memory Flash memory 0x0400 0000 - 0x07FF FFFF Reserved Reserved Reserved QUADSPI bank (128 MB) Aliased 0x0010 0000 - 0x03FF FFFF Reserved Reserved Reserved QUADSPI bank (128 MB) Aliased SRAM1 Aliased System memory Aliased QUADSPI bank (128 MB) Aliased 0x1000 0000 - 0x1007 FFFF (1) 0x0808 0000 (1) - 0x0FFF FFFF 0x0000 0000 - 0x000F FFFF(2) (3) Flash Aliased 1. Address depends on the memory size available on given device. 2. When the QUADSPI is remapped at address 0x0000 0000, only 128 MB are remapped. In remap mode, the CPU can access the external memory via ICode bus instead of System bus which boosts up the performance. 3. Even when aliased in the boot memory space, the related memory is still accessible at its original memory space. Embedded boot loader The embedded boot loader is located in the System memory, programmed by ST during production. Refer to AN2606 STM32 microcontroller system memory boot mode. 76/1600 RM0394 Rev 4 RM0394 Embedded Flash memory (FLASH) 3 Embedded Flash memory (FLASH) 3.1 Introduction The Flash memory interface manages CPU AHB ICode and DCode accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines. 3.2 FLASH main features • 72-bit wide data read (64 bits plus 8 ECC bits) • 72-bit wide data write (64 bits plus 8 ECC bits) • Page erase (2 Kbyte) and mass erase Flash memory interface features: • Flash memory read operations • Flash memory program/erase operations • Read protection activated by option (RDP) • Prefetch on ICODE • Instruction Cache: 32 cache lines of 4 x 64 bits on ICode (1 KB RAM) • Data Cache: 8 cache lines of 4 x 64 bits on DCode (256B RAM) • Error Code Correction (ECC): 8 bits for 64-bit double-word • Option byte loader • Low-power mode 3.3 FLASH functional description 3.3.1 Flash memory organization The Flash memory is organized as 72-bit wide memory cells (64 bits plus 8 ECC bits) that can be used for storing both code and data constants. The Flash memory is organized as follows: • An Information block containing: – System memory from which the device boots in System memory boot mode. The area is reserved for use by STMicroelectronics and contains the boot loader that is used to reprogram the Flash memory through one of the following interfaces: USART1, USART2, USART3, USB (DFU), I2C1, I2C2, I2C3, SPI1, SPI2, SPI3. It is programmed by STMicroelectronics when the device is manufactured, and protected against spurious write/erase operations. For further details, please refer to the AN2606 available from www.st.com. – 1 Kbyte (128 double word) OTP (one-time programmable) bytes for user data. The OTP data cannot be erased and can be written only once. If only one bit is at 0, RM0394 Rev 4 77/1600 113 Embedded Flash memory (FLASH) RM0394 the entire double word cannot be written anymore, even with the value 0x0000 0000 0000 0000. – Option bytes for user configuration. The memory organization is based on a main area and an information block as shown in Table 8. Table 8. Flash module - single bank organization Flash memory addresses Size (bytes) Name 0x0800 0000 - 0x0800 07FF 2K Page 0 0x0800 0800 - 0x0800 0FFF 2K Page 1 0x0800 1000 - 0x0800 17FF 2K Page 2 0x0800 1800 - 0x0800 1FFF 2K Page 3 - - - 0x0801 F800 - 0x0801 FFFF 2K Page 63(1) - - - 0x0803 F800 - 0x0803 FFFF 2K Page 127(2) - - - 0x0807 F800 - 0x0807 FFFF 2K Page 255(3) 0x1FFF 0000 - 0x1FFF 6FFF 28 K System memory 0x1FFF 7000 - 0x1FFF 73FF 1K OTP area 0x1FFF 7800 - 0x1FFF 780F 16 Option bytes Flash area Main memory Information block 1. Main Flash memory space of 128K devices is limited to page 63. 2. Main Flash memory space of 256K devices is limited to page 127. 3. Main Flash memory space of 512K devices is limited to page 255. 3.3.2 Error code correction (ECC) Data in Flash memory are 72-bits words: 8 bits are added per double word (64 bits). The ECC mechanism supports: • One error detection and correction • Two errors detection When one error is detected and corrected, the flag ECCC (ECC correction) is set in Flash ECC register (FLASH_ECCR). If ECCCIE is set, an interrupt is generated. When two errors are detected, a flag ECCD (ECC detection) is set in FLASH_ECCR register. In this case, a NMI is generated. When an ECC error is detected, the address of the failing double word saved in ADDR_ECC[20:0] in the FLASH_ECCR register. ADDR_ECC[2:0] are always cleared. When ECCC or ECCD is set, ADDR_ECC not updated if a new ECC error occurs. FLASH_ECCR is updated only when ECC flags are cleared. 78/1600 RM0394 Rev 4 RM0394 Note: Embedded Flash memory (FLASH) For a virgin data: 0xFF FFFF FFFF FFFF FFFF, one error is detected and corrected but two errors detection is not supported. When an ECC error is reported, a new read at the failing address may not generate an ECC error if the data is still present in the current buffer, even if ECCC and ECCD are cleared. 3.3.3 Read access latency To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed in the Flash access control register (FLASH_ACR) according to the frequency of the CPU clock (HCLK) and the internal voltage range of the device VCORE. Refer to Section 5.1.7: Dynamic voltage scaling management. Table 9 shows the correspondence between wait states and CPU clock frequency. Table 9. Number of wait states according to CPU clock (HCLK) frequency HCLK (MHz) Wait states (WS) (LATENCY) VCORE Range 1(1) VCORE Range 2(2) 0 WS (1 CPU cycles) ≤ 16 ≤6 1 WS (2 CPU cycles) ≤ 32 ≤ 12 2 WS (3 CPU cycles) ≤ 48 ≤ 18 3 WS (4 CPU cycles) ≤ 64 ≤ 26 4 WS (5 CPU cycles) ≤ 80 ≤ 26 1. Also for SMPS Range1 or SMPS Range2 high. 2. Also for SMPS Range2 low. After reset, the CPU clock frequency is 4 MHz and 0 wait state (WS) is configured in the FLASH_ACR register. When changing the CPU frequency, the following software sequences must be applied in order to tune the number of wait states needed to access the Flash memory: Increasing the CPU frequency: 1. Program the new number of wait states to the LATENCY bits in the Flash access control register (FLASH_ACR). 2. Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register. 3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register. 4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR. 5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register. RM0394 Rev 4 79/1600 113 Embedded Flash memory (FLASH) RM0394 Decreasing the CPU frequency: 3.3.4 1. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register. 2. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR. 3. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register. 4. Program the new number of wait states to the LATENCY bits in Flash access control register (FLASH_ACR). 5. Check that the new number of wait states is used to access the Flash memory by reading the FLASH_ACR register. Adaptive real-time memory accelerator (ART Accelerator™) The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32 industry-standard Arm® Cortex®-M4 with FPU processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher operating frequencies. To release the processor full performance, the accelerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 64bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 80 MHz. Instruction prefetch The Cortex®-M4 fetches the instruction over the ICode bus and the literal pool (constant/data) over the DCode bus. The prefetch block aims at increasing the efficiency of ICode bus accesses. Each Flash memory read operation provides 64 bits from either two instructions of 32 bits or four instructions of 16 bits according to the program launched. This 64-bits current instruction line is saved in a current buffer. So, in case of sequential code, at least two CPU cycles are needed to execute the previous read instruction line. Prefetch on the ICode bus can be used to read the next sequential instruction line from the Flash memory while the current instruction line is being requested by the CPU. Prefetch is enabled by setting the PRFTEN bit in the Flash access control register (FLASH_ACR). This feature is useful if at least one wait state is needed to access the Flash memory. Figure 3 shows the execution of sequential 16-bit instructions with and without prefetch when 3 WS are needed to access the Flash memory. 80/1600 RM0394 Rev 4 RM0394 Embedded Flash memory (FLASH) Figure 3. Sequential 16-bit instructions execution # :$,7 ) # ' ( ) ' ( # ) ' ( # ) ' :,7+28735()(7&+ # ( ) :$,7 # LQV LQV LQV LQV IHWFK IHWFK IHWFK IHWFK 5HDGLQV # :$,7 # *LYHVLQV ) ' ( ) ' ( # ) ' # ) LQV LQV LQV LQV IHWFK IHWFK IHWFK IHWFK 5HDGLQV *LYHVLQV ' ( ) ' ( # ) ' ( # ) ' ( # ) ' ( # ) ' ( # ) ' # ) :,7+35()(7&+ LQV LQV LQV LQV LQV LQV LQV LQV IHWFK IHWFK IHWFK IHWFK IHWFK IHWFK IHWFK IHWFK 5HDGLQV *LYHVLQV *LYHVLQV 5HDGLQV &RUWH[0SLSHOLQH # ) ' ( $+%SURWRFRO #DGGUHVVUHTXHVWHG ))HWFKVWDJH ''HFRGHVWDJH (([HFXWHVWDJH 5HDGLQV 069 When the code is not sequential (branch), the instruction may not be present in the currently used instruction line or in the prefetched instruction line. In this case (miss), the penalty in terms of number of cycles is at least equal to the number of wait states. RM0394 Rev 4 81/1600 113 Embedded Flash memory (FLASH) RM0394 If a loop is present in the current buffer, no new flash access is performed. Instruction cache memory (I-Cache) To limit the time lost due to jumps, it is possible to retain 32 lines of 4*64 bits in an instruction cache memory.This feature can be enabled by setting the instruction cache enable (ICEN) bit in the Flash access control register (FLASH_ACR). Each time a miss occurs (requested data not present in the currently used instruction line, in the prefetched instruction line or in the instruction cache memory), the line read is copied into the instruction cache memory. If some data contained in the instruction cache memory are requested by the CPU, they are provided without inserting any delay. Once all the instruction cache memory lines have been filled, the LRU (least recently used) policy is used to determine the line to replace in the instruction memory cache. This feature is particularly useful in case of code containing loops. The Instruction cache memory is enable after system reset. Data cache memory (D-Cache) Literal pools are fetched from Flash memory through the DCode bus during the execution stage of the CPU pipeline. Each DCode bus read access fetches 64 bits which are saved in a current buffer. The CPU pipeline is consequently stalled until the requested literal pool is provided. To limit the time lost due to literal pools, accesses through the AHB databus DCode have priority over accesses through the AHB instruction bus ICode. If some literal pools are frequently used, the data cache memory can be enabled by setting the data cache enable (DCEN) bit in the Flash access control register (FLASH_ACR). This feature works like the instruction cache memory, but the retained data size is limited to 8 rows of 4*64 bits. The Data cache memory is enable after system reset. Note: The D-Cache is active only when data is requested by the CPU (not by DMA1 and DMA2). Data in option bytes block are not cacheable. 3.3.5 Flash program and erase operations The STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx embedded Flash memory can be programmed using in-circuit programming or in-application programming. The in-circuit programming (ICP) method is used to update the entire contents of the Flash memory, using the JTAG, SWD protocol or the boot loader to load the user application into the microcontroller. ICP offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. In contrast to the ICP method, in-application programming (IAP) can use any communication interface supported by the microcontroller (I/Os, USB, CAN, UART, I2C, SPI, etc.) to download programming data into memory. IAP allows the user to re-program the Flash memory while the application is running. Nevertheless, part of the application has to have been previously programmed in the Flash memory using ICP. The contents of the Flash memory are not guaranteed if a device reset occurs during a Flash memory operation. During a program/erase operation to the Flash memory, any attempt to read the Flash memory will stall the bus. The read operation will proceed correctly once the program/erase operation has completed. 82/1600 RM0394 Rev 4 RM0394 Embedded Flash memory (FLASH) Unlocking the Flash memory After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the Flash memory against possible unwanted operations due, for example, to electric disturbances. The following sequence is used to unlock this register: 1. Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR) 2. Write KEY2 = 0xCDEF89AB in the FLASH_KEYR register. Any wrong sequence will lock up the FLASH_CR register until the next system reset. In the case of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is generated. The FLASH_CR register can be locked again by software by setting the LOCK bit in the FLASH_CR register. Note: The FLASH_CR register cannot be written when the BSY bit in the Flash status register (FLASH_SR) is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall until the BSY bit is cleared. 3.3.6 Flash main memory erase sequences The Flash memory erase operation can be performed at page level or on the whole Flash memory (Mass Erase). Mass Erase does not affect the Information block (system flash, OTP and option bytes). Page erase To erase a page (2 Kbyte), follow the procedure below: Note: 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR). 2. Check and clear all error programming flags due to a previous programming. If not, PGSERR is set. 3. Set the PER bit and select the page you wish to erase (PNB) in the Flash control register (FLASH_CR). 4. Set the STRT bit in the FLASH_CR register. 5. Wait for the BSY bit to be cleared in the FLASH_SR register. The internal oscillator HSI16 (16 MHz) is enabled automatically when STRT bit is set, and disabled automatically when STRT bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register. If the page erase is part of write-protected area (by WRP or PCROP), WRPERR is set and the page erase request is aborted. Mass erase To perform a Mass Erase, follow the procedure below: RM0394 Rev 4 83/1600 113 Embedded Flash memory (FLASH) Note: RM0394 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register. 2. Check and clear all error programming flags due to a previous programming. If not, PGSERR is set. 3. Set the MER1 bit in the Flash control register (FLASH_CR). 4. Set the STRT bit in the FLASH_CR register. 5. Wait for the BSY bit to be cleared in the Flash control register (FLASH_CR). The internal oscillator HSI16 (16 MHz) is enabled automatically when STRT bit is set, and disabled automatically when STRT bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register. If the Flash memory contains a write-protected area (by WRP or PCROP), WRPERR is set and the mass erase request is aborted. 3.3.7 Flash main memory programming sequences The Flash memory is programmed 72 bits at a time (64 bits + 8 bits ECC). Programming in a previously programmed address is not allowed except if the data to write is full zero, and any attempt will set PROGERR flag in the Flash status register (FLASH_SR). It is only possible to program double word (2 x 32-bit data). • Any attempt to write byte or half-word will set SIZERR flag in the FLASH_SR register. • Any attempt to write a double word which is not aligned with a double word address will set PGAERR flag in the FLASH_SR register. Standard programming The Flash memory programming sequence in standard mode is as follows: Note: 84/1600 1. Check that no Flash main memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR). 2. Check and clear all error programming flags due to a previous programming. If not, PGSERR is set. 3. Set the PG bit in the Flash control register (FLASH_CR). 4. Perform the data write operation at the desired memory address, inside main memory block or OTP area. Only double word can be programmed. – Write a first word in an address aligned with double word – Write the second word 5. Wait until the BSY bit is cleared in the FLASH_SR register. 6. Check that EOP flag is set in the FLASH_SR register (meaning that the programming operation has succeed), and clear it by software. 7. Clear the PG bit in the FLASH_CR register if there no more programming request anymore. When the flash interface has received a good sequence (a double word), programming is automatically launched and BSY bit is set. The internal oscillator HSI16 (16 MHz) is enabled RM0394 Rev 4 RM0394 Embedded Flash memory (FLASH) automatically when PG bit is set, and disabled automatically when PG bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register. If the user needs to program only one word, double word must be completed with the erase value 0xFFFF FFFF to launch automatically the programming. ECC is calculated from the double word to program. Fast programming This mode allows to program a row (32 double word) and to reduce the page programming time by eliminating the need for verifying the flash locations before they are programmed and to avoid rising and falling time of high voltage for each double word. During fast programming, the CPU clock frequency (HCLK) must be at least 8 MHz. Only the main memory can be programmed in Fast programming mode. The Flash main memory programming sequence in standard mode is as follows: 1. Perform a mass erase of the bank to program. If not, PGSERR is set. 2. Check that no Flash main memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR). 3. Check and clear all error programming flag due to a previous programming. 4. Set the FSTPG bit in Flash control register (FLASH_CR). 5. Note: Write the 32 double words to program a row. Only double words can be programmed: – Write a first word in an address aligned with double word – Write the second word. 6. Wait until the BSY bit is cleared in the FLASH_SR register. 7. Check that EOP flag is set in the FLASH_SR register (meaning that the programming operation has succeed), and clear it by software. 8. Clear the FSTPG bit in the FLASH_CR register if there no more programming request anymore. If the flash is attempted to be written in Fast programming mode while a read operation is on going in the same bank, the programming is aborted without any system notification (no error flag is set). When the Flash interface has received the first double word, programming is automatically launched. The BSY bit is set when the high voltage is applied for the first double word, and it is cleared when the last double word has been programmed or in case of error. The internal oscillator HSI16 (16 MHz) is enabled automatically when FSTPG bit is set, and disabled automatically when FSTPG bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register. The 32 double word must be written successively. The high voltage is kept on the flash for all the programming. Maximum time between two double words write requests is the time programming (around 20us). If a second double word arrives after this time programming, fast programming is interrupted and MISSERR is set. High voltage mustn’t exceed 8 ms for a full row between 2 erases. This is guaranteed by the sequence of 32 double words successively written with a clock system greater or equal to 8MHz. An internal time-out counter counts 7ms when Fast programming is set and stops the programming when time-out is over. In this case the FASTERR bit is set. If an error occurs, high voltage is stopped and next double word to programmed is not programmed. Anyway, all previous double words have been properly programmed. RM0394 Rev 4 85/1600 113 Embedded Flash memory (FLASH) RM0394 Programming errors Several kind of errors can be detected. In case of error, the Flash operation (programming or erasing) is aborted. • PROGERR: Programming Error In standard programming: PROGERR is set if the word to write is not previously erased (except if the value to program is full zero). • SIZERR: Size Programming Error In standard programming or in fast programming: only double word can be programmed and only 32-bit data can be written. SIZERR is set if a byte or an halfword is written. • PGAERR: Alignment Programming error PGAERR is set if one of the following conditions occurs: • – In standard programming: the first word to be programmed is not aligned with a double word address, or the second word doesn’t belong to the same double word address. – In fast programming: the data to program doesn’t belong to the same row than the previous programmed double words, or the address to program is not greater than the previous one. PGSERR: Programming Sequence Error PGSERR is set if one of the following conditions occurs: • – In the standard programming sequence or the fast programming sequence: a data is written when PG and FSTPG are cleared. – In the standard programming sequence or the fast programming sequence: MER1 and PER are not cleared when PG or FSTPG is set. – In the fast programming sequence: the Mass erase is not performed before setting FSTPG bit. – In the mass erase sequence: PG, FSTPG, and PER are not cleared when MER1 is set. – PGSERR is set also if PROGERR, SIZERR, PGAERR, MISSERR, FASTERR or PGSERR is set due to a previous programming error. WRPERR: Write Protection Error WRPERR is set if one of the following conditions occurs: • – Attempt to program or erase in a write protected area (WRP) or in a PCROP area. – Attempt to perform a erase when one page or more is protected by WRP or PCROP. – The debug features are connected or the boot is executed from SRAM or from System flash when the read protection (RDP) is set to Level 1. – Attempt to modify the option bytes when the read protection (RDP) is set to Level 2. MISSERR: Fast Programming Data Miss Error In fast programming: all the data must be written successively. MISSERR is set if the previous data programmation is finished and the next data to program is not written yet. • FASTERR: Fast Programming Error In fast programming: FASTERR is set if one of the following conditions occurs: – 86/1600 When FSTPG bit is set for more than 7ms which generates a time-out detection. RM0394 Rev 4 RM0394 Embedded Flash memory (FLASH) – When the row fast programming has been interrupted by a MISSERR, PGAERR, WRPERR or SIZERR. If an error occurs during a program or erase operation, one of the following error flags is set in the FLASH_SR register: PROGERR, SIZERR, PGAERR, PGSERR, MISSERR (Program error flags), WRPERR (Protection error flag) In this case, if the error interrupt enable bit ERRIE is set in the Flash status register (FLASH_SR), an interrupt is generated and the operation error flag OPERR is set in the FLASH_SR register. Note: If several successive errors are detected (for example, in case of DMA transfer to the Flash memory), the error flags cannot be cleared until the end of the successive write requests. Programming and caches If a Flash memory write access concerns some data in the data cache, the Flash write access modifies the data in the Flash memory and the data in the cache. If an erase operation in Flash memory also concerns data in the data or instruction cache, you have to make sure that these data are rewritten before they are accessed during code execution. If this cannot be done safely, it is recommended to flush the caches by setting the DCRST and ICRST bits in the Flash access control register (FLASH_ACR). Note: The I/D cache should be flushed only when it is disabled (I/DCEN = 0). RM0394 Rev 4 87/1600 113 Embedded Flash memory (FLASH) RM0394 3.4 FLASH option bytes 3.4.1 Option bytes description The option bytes are configured by the end user depending on the application requirements. As a configuration example, the watchdog may be selected in hardware or software mode (refer to Section 3.4.2: Option bytes programming). A double word is split up as follows in the option bytes: Table 10. Option byte format 63-24 23-16 15 -8 7-0 Complemented Complemented Complemented Complemented option byte 3 option byte 2 option byte 1 option byte 0 31-24 23-16 15 -8 7-0 Option byte 3 Option byte 2 Option byte 1 Option byte 0 The organization of these bytes inside the information block is as shown in Table 11: Option byte organization. The option bytes can be read from the memory locations listed in Table 11: Option byte organization or from the Option byte registers: • Flash option register (FLASH_OPTR) • Flash PCROP Start address register (FLASH_PCROP1SR) • Flash PCROP End address register (FLASH_PCROP1ER) • Flash WRP area A address register (FLASH_WRP1AR) • Flash WRP area B address register (FLASH_WRP1BR) Table 11. Option byte organization 63 [62:56] 0x1FFF 7800 [47:40] [39:32] USER OPT Unused PCROP_RDP 0x1FFF 7808 0x1FFF 7810 [55:48] Unused 31 [30:24] RDP Unused PCROP1_STRT PCROP1_END [23:16] [15:8] USER OPT PCROP_RDP Address Unused [7:0] RDP PCROP1_STRT PCROP1_END 0x1FFF 7818 Unused WRP1A _END Unused WRP1A _STRT Unused WRP1A_ END Unused WRP1A _STRT 0x1FFF 7820 Unused WRP1B _END Unused WRP1B _STRT Unused WRP1B_ END Unused WRP1B _STRT User and read protection option bytes Flash memory address: 0x1FFF 7800 ST production value: 0xFFEF F8AA 88/1600 RM0394 Rev 4 RM0394 Embedded Flash memory (FLASH) 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. 27 nRST_ nRST_ nRST_ SHDW STDBY STOP r r r 26 25 24 23 n nSW SRAM2 SRAM2 n BOOT0 BOOT0 _RST _PE BOOT1 r r r r r 11 10 9 8 7 Res. 22 21 20 Res. Res. Res. 6 5 4 BOR_LEV[2:0] r r 19 18 17 16 WWDG IWGD_ IWDG_ IWDG_ _SW STDBY STOP SW r r r r 3 2 1 0 r r r RDP[7:0] r r r r r r Bits 31:28 Reserved, must be kept at reset value. Bit 27 nBOOT0: nBOOT0 option bit 0: nBOOT0 = 0 1: nBOOT0 = 1 Bit 26 nSWBOOT0: Software BOOT0 0: BOOT0 taken from the option bit nBOOT0 1: BOOT0 taken from PH3/BOOT0 pin Bit 25 SRAM2_RST: SRAM2 Erase when system reset 0: SRAM2 erased when a system reset occurs 1: SRAM2 is not erased when a system reset occurs Bit 24 SRAM2_PE: SRAM2 parity check enable 0: SRAM2 parity check enable 1: SRAM2 parity check disable Bit 23 nBOOT1: Boot configuration Together with the BOOT0 pin, this bit selects boot mode from the Flash main memory, SRAM1 or the System memory. Refer to Section 2.6: Boot configuration. Bits 22:20 Reserved, must be kept at reset value. Bit 19 WWDG_SW: Window watchdog selection 0: Hardware window watchdog 1: Software window watchdog Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode 0: Independent watchdog counter is frozen in Standby mode 1: Independent watchdog counter is running in Standby mode Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode 0: Independent watchdog counter is frozen in Stop mode 1: Independent watchdog counter is running in Stop mode Bit 16 IDWG_SW: Independent watchdog selection 0: Hardware independent watchdog 1: Software independent watchdog Bit 15 Reserved, must be kept at reset value. Bit 14 nRST_SHDW 0: Reset generated when entering the Shutdown mode 1: No reset generated when entering the Shutdown mode Bit 13 nRST_STDBY 0: Reset generated when entering the Standby mode 1: No reset generate when entering the Standby mode RM0394 Rev 4 89/1600 113 Embedded Flash memory (FLASH) RM0394 Bit 12 nRST_STOP 0: Reset generated when entering the Stop mode 1: No reset generated when entering the Stop mode Bit 11 Reserved, must be kept at reset value. Bits10:8 BOR_LEV: BOR reset Level These bits contain the VDD supply level threshold that activates/releases the reset. 000: BOR Level 0. Reset level threshold is around 1.7 V 001: BOR Level 1. Reset level threshold is around 2.0 V 010: BOR Level 2. Reset level threshold is around 2.2 V 011: BOR Level 3. Reset level threshold is around 2.5 V 100: BOR Level 4. Reset level threshold is around 2.8 V Bits 7:0 RDP: Read protection level 0xAA: Level 0, read protection not active 0xCC: Level 2, chip read protection active Others: Level 1, memories read protection active PCROP Start address option bytes Flash memory address: 0x1FFF 7808 ST production value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r PCROP1_STRT[15:0] r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PCROP1_STRT: PCROP area start offset PCROP1_STRT contains the first double-word of the PCROP area. PCROP End address option bytes Flash memory address: 0x1FFF 7810 ST production value: 0xFFFF 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PCROP _RDP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r 15 PCROP1_END[15:0] r 90/1600 r r r r r r r r RM0394 Rev 4 RM0394 Embedded Flash memory (FLASH) Bit 31 PCROP_RDP: PCROP area preserved when RDP level decreased This bit is set only. It is reset after a full mass erase due to a change of RDP from Level 1 to Level 0. 0: PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0. 1: PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase). Bits 30:16 Reserved, must be kept at reset value. Bits 15:0 PCROP1_END: Bank 1 PCROP area end offset PCROP1_END contains the last double-word of the bank 1 PCROP area. WRP Area A address option bytes Flash memory address: 0x1FFF 7818 ST production value: 0xFF00 FFFF 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 WRP1A_END[7:0] r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r 18 17 16 WRP1A_STRT[7:0] r r Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 WRP1A_END: WRP first area “A” end offset WRPA1_END contains the last page of the WRP first area. Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 WRP1A_STRT: WRP first area “A” start offset WRPA1_STRT contains the first page of the WRP first area. WRP Area B address option bytes Flash memory address: 0x1FFF 7820 ST production value: 0xFF00 FFFF 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 WRP1B_END[7:0] r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r WRP1B_STRT[7:0] r r Bits 31:24 Reserved, must be kept at reset value. RM0394 Rev 4 91/1600 113 Embedded Flash memory (FLASH) RM0394 Bits 23:16 WRP1B_END: WRP first area “B” end offset WRPB1_END contains the last page of the WRP second area. Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 WRP1B_STRT: WRP first area “B” start offset WRPB1_STRT contains the first page of the WRP second area. 3.4.2 Option bytes programming After reset, the options related bits in the Flash control register (FLASH_CR) are writeprotected. To run any operation on the option bytes page, the option lock bit OPTLOCK in the Flash control register (FLASH_CR) must be cleared. The following sequence is used to unlock this register: 1. Unlock the FLASH_CR with the LOCK clearing sequence (refer to Unlocking the Flash memory). 2. Write OPTKEY1 = 0x08192A3B in the Flash option key register (FLASH_OPTKEYR). 3. Write OPTKEY2 = 0x4C5D6E7F in the FLASH_OPTKEYR register. The user options can be protected against unwanted erase/program operations by setting the OPTLOCK bit by software. Note: If LOCK is set by software, OPTLOCK is automatically set too. Modifying user options The option bytes are programmed differently from a main memory user address. To modify the user options value, follow the procedure below: Note: 1. Check that no Flash memory operation is on going by checking the BSY bit in the Flash status register (FLASH_SR). 2. Clear OPTLOCK option lock bit with the clearing sequence described above. 3. Write the desired options value in the options registers: Flash option register (FLASH_OPTR), Flash PCROP Start address register (FLASH_PCROP1SR), Flash PCROP End address register (FLASH_PCROP1ER), Flash WRP area A address register (FLASH_WRP1AR), Flash WRP area B address register (FLASH_WRP1BR). 4. Set the Options Start bit OPTSTRT in the Flash control register (FLASH_CR). 5. Wait for the BSY bit to be cleared. Any modification of the value of one option is automatically performed by erasing user option bytes pages first and then programming all the option bytes with the values contained in the flash option registers. Option byte loading After the BSY bit is cleared, all new options are updated into the flash but they are not applied to the system. They will have effect on the system when they are loaded. Option bytes loading (OBL) is performed in two cases: – when OBL_LAUNCH bit is set in the Flash control register (FLASH_CR). – after a power reset (BOR reset or exit from Standby/Shutdown modes). Option byte loader performs a read of the options block and stores the data into internal option registers. These internal registers configure the system and cannot be read with by 92/1600 RM0394 Rev 4 RM0394 Embedded Flash memory (FLASH) software. Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset. Each option bit has also its complement in the same double word. During option loading, a verification of the option bit and its complement allows to check the loading has correctly taken place. During option byte loading, the options are read by double word with ECC. If the word and its complement are matching, the option word/byte is copied into the option register. If the comparison between the word and its complement fails, a status bit OPTVERR is set. Mismatch values are forced into the option registers: – For USR OPT option, the value of mismatch is all options at ‘1’, except for BOR_LEV which is “000” (lowest threshold) – For WRP option, the value of mismatch is the default value “No protection” – For RDP option, the value of mismatch is the default value “Level 1” – For PCROP, the value of mismatch is “all memory protected” On system reset rising, internal option registers are copied into option registers which can be read and written by software (FLASH_OPTR, FLASH_PCROP1SR, FLASH_PCROP1ER, FLASH_WRP1AR, FLASH_WRP1BR). These registers are also used to modify options. If these registers are not modified by user, they reflects the options states of the system. See Section : Modifying user options for more details. RM0394 Rev 4 93/1600 113 Embedded Flash memory (FLASH) 3.5 RM0394 FLASH memory protection The Flash main memory can be protected against external accesses with the Read protection (RDP). The pages of the Flash memory can also be protected against unwanted write due to loss of program counter contexts. The write-protection (WRP) granularity is one page (2 KByte). Apart of the flash memory can also be protected against read and write from third parties (PCROP). The PCROP granularity is double word (64-bit). 3.5.1 Read protection (RDP) The read protection is activated by setting the RDP option byte and then, by applying a system reset to reload the new RDP option byte. The read protection protects to the Flash main memory, the option bytes, the backup registers (RTC_BKPxR in the RTC) and the SRAM2. Note: If the read protection is set while the debugger is still connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset. There are three levels of read protection from no protection (level 0) to maximum protection or no debug (level 2). The Flash memory is protected when the RDP option byte and its complement contain the pair of values shown in Table 12. Table 12. Flash memory read protection status RDP byte value RDP complement value Read protection level 0xAA 0x55 Level 0 Any value except 0xAA or 0xCC Any value (not necessarily complementary) except 0x55 and 0x33 Level 1 (default) 0xCC 0x33 Level 2 The System memory area is read accessible whatever the protection level. It is never accessible for program/erase operation. Level 0: no protection Read, program and erase operations into the Flash main memory area are possible. The option bytes, the SRAM2 and the backup registers are also accessible by all operations. 94/1600 RM0394 Rev 4 RM0394 Embedded Flash memory (FLASH) Level 1: Read protection This is the default protection level when RDP option byte is erased. It is defined as well when RDP value is at any value different from 0xAA and 0xCC, or even if the complement is not correct. • Caution: User mode: Code executing in user mode (Boot Flash) can access Flash main memory, option bytes, SRAM2 and backup registers with all operations. In case the Level 1 is configured and no PCROP area is defined, it is mandatory to set PCROP_RDP bit to 1 (full mass erase when the RDP level is decreased from Level 1 to Level 0). In case the Level 1 is configured and a PCROP area is defined, if user code needs to be protected by RDP but not by PCROP, it must not be placed in a page containing a PCROP area. Level 2: No debug In this level, the protection level 1 is guaranteed. In addition, the Cortex®-M4 debug port, the boot from RAM (boot RAM mode) and the boot from System memory (boot loader mode) are no more available. In user execution mode (boot FLASH mode), all operations are allowed on the Flash Main memory. On the contrary, only read operations can be performed on the option bytes. Option bytes cannot be programmed nor erased. Thus, the level 2 cannot be removed at all: it is an irreversible operation. When attempting to modify the options bytes, the protection error flag WRPERR is set in the Flash_SR register and an interrupt can be generated. Note: The debug feature is also disabled under reset. STMicroelectronics is not able to perform analysis on defective parts on which the level 2 protection has been set. Changing the Read protection level It is easy to move from level 0 to level 1 by changing the value of the RDP byte to any value (except 0xCC). By programming the 0xCC value in the RDP byte, it is possible to go to level 2 either directly from level 0 or from level 1. Once in level 2, it is no more possible to modify the Read protection level. When the RDP is reprogrammed to the value 0xAA to move from Level 1 to Level 0, a mass erase of the Flash main memory is performed if PCROP_RDP is set in the Flash PCROP End address register (FLASH_PCROP1ER). The backup registers (RTC_BKPxR in the RTC) and the SRAM2 are also erased. The user options except PCROP protection are set to their previous values copied from FLASH_OPTR, FLASH_WRPxyR (x=1 and y =A or B). PCROP is disable. The OTP area is not affected by mass erase and remains unchanged. If the bit PCROP_RDP is cleared in the FLASH_PCROP1ER, the full mass erase is replaced by a partial mass erase that is successive page erases in the bank where PCROP is active, except for the pages protected by PCROP. This is done in order to keep the PCROP code. Only when the Flash memory is erased, options are re-programmed with their previous values. This is also true for FLASH_PCROPxSR and FLASH_PCROPxER registers (x=1). Note: Full Mass Erase or Partial Mass Erase is performed only when Level 1 is active and Level 0 requested. When the protection level is increased (0->1, 1->2, 0->2) there is no mass erase. To validate the protection level change, the option bytes must be reloaded through the OBL_LAUNCH bit in Flash control register. RM0394 Rev 4 95/1600 113 Embedded Flash memory (FLASH) RM0394 Figure 4. Changing the Read protection (RDP) level 5'3[$$DQG5'3[&& 2WKHUVRSWLRQVPRGLILHG /HYHO 5'3[$$ 5'3[&& GHIDXOW :ULWHRSWLRQV,QFOXGLQJ 5'3 [&& :ULWHRSWLRQVLQFOXGLQJ 5'3[&&DQG5'3[$$ /HYHO 5'3 [&& :ULWHRSWLRQVLQFOXGLQJ 5'3 [$$ /HYHO 5'3 [$$ :ULWHRSWLRQVLQFOXGLQJ 5'3 [&& 5'3 [$$ 2WKHU V RSWLRQ V PRGLILHG 2SWLRQVZULWH 5'3OHYHOLQFUHDVH LQFOXGHV 2SWLRQVSDJHHUDVH 1HZRSWLRQVSURJUDP 2SWLRQVZULWH 5'3OHYHOGHFUHDVH LQFOXGHV )XOO0DVVHUDVHRU3DUWLDO0DVVHUDVHWRQRW HUDVH3&523SDJHVLI3&523B5'3LVFOHDUHG %DFNXSUHJLVWHUVDQG&&065$0HUDVH 2SWLRQVSDJHHUDVH 1HZRSWLRQVSURJUDP 2SWLRQVZULWH 5'3OHYHOLGHQWLFDO LQFOXGHV 2SWLRQVSDJHHUDVH 1HZRSWLRQVSURJUDP 069 Table 13. Access status versus protection level and execution modes Area Flash main memory System memory (2) Protection level Debug/ BootFromRam/ BootFromLoader(1) User execution (BootFromFlash) Read Write Erase Read Write Erase 1 Yes Yes Yes No No No(3) 2 Yes Yes Yes N/A N/A N/A 1 Yes No No Yes No No 2 Yes No No N/A N/A N/A 1 Yes Yes(3) Yes Yes Yes(3) Yes 2 Yes No No N/A N/A N/A 1 Yes Yes(4) N/A No No N/A 2 Yes Yes(4) N/A N/A N/A N/A 1 Yes Yes N/A No No No(5) 2 Yes Yes N/A N/A N/A N/A Option bytes OTP Backup registers 96/1600 RM0394 Rev 4 RM0394 Embedded Flash memory (FLASH) Table 13. Access status versus protection level and execution modes (continued) Protection level Area Debug/ BootFromRam/ BootFromLoader(1) User execution (BootFromFlash) Read Write Erase Read Write Erase 1 Yes Yes N/A No No No(6) 2 Yes Yes N/A N/A N/A N/A SRAM2 1. When the protection level 2 is active, the Debug port, the boot from RAM and the boot from system memory are disabled. 2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode. 3. The Flash main memory is erased when the RDP option byte is programmed with all level protections disabled (0xAA). 4. OTP can only be written once. 5. The backup registers are erased when RDP changes from level 1 to level 0. 6. The SRAM2 is erased when RDP changes from level 1 to level 0. 3.5.2 Proprietary code readout protection (PCROP) Apart of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. The PCROP area has a double word (64-bit) granularity. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0 (refer to Changing the Read protection level). The PCROP area is defined by a start page offset and an end page offset. These offsets are defined in the PCROP address registers Flash PCROP Start address register (FLASH_PCROP1SR), Flash PCROP End address register (FLASH_PCROP1ER). The PCROP area is defined from the address: Flash memory Base address + [PCROP1_STRT x 0x8] (included) to the address: Flash memory Base address + [(PCROP1_END+1) x 0x8] (excluded). The minimum PCROP area size is two double-words (128 bits). For example, to protect by PCROP from the address 0x0806 2F80 (included) to the address 0x0807 0004 (included): • if boot in flash is selected, FLASH_PCROP1SR and FLASH_PCROP1ER registers must be programmed with: – PCROP1_STRT = 0xC5F0. – PCROP1_END = 0xE000. Any read access performed through the D-bus to a PCROP protected area will trigger RDERR flag error. Any PCROP protected address is also write protected and any write access to one of these addresses will trigger WRPERR. Any PCROP area is also erase protected. Consequently, any erase to a page in this zone is impossible (including the page containing the start address and the end address of this zone). Moreover, a software mass erase cannot be performed if one zone is PCROP protected. RM0394 Rev 4 97/1600 113 Embedded Flash memory (FLASH) RM0394 For previous example, due to erase by page, all pages from page 0xC5 to 0xE0 are protected in case of page erase. (All addresses from 0x0806 2800 to 0x0807 07FF can’t be erased). Deactivation of PCROP can only occurs when the RDP is changing from level 1 to level 0. If the user options modification tries to clear PCROP or to decrease the PCROP area, the options programming is launched but PCROP area stays unchanged. On the contrary, it is possible to increase the PCROP area. When option bit PCROP_RDP is cleared, when the RDP is changing from level 1 to level 0, Full Mass Erase is replaced by Partial Mass Erase in order to keep the PCROP area (refer to Changing the Read protection level). In this case, PCROP1_STRT and PCROP1_END are also not erased. Note: It is recommended to align PCROP area with page granularity when using PCROP_RDP, or to leave free the rest of the page where PCROP zone starts or ends. 3.5.3 Write protection (WRP) The user area in Flash memory can be protected against unwanted write operations. Two write-protected (WRP) areas can be defined, with page (2 KByte) granularity. The area is defined by a start page offset and an end page offset related to the physical Flash memory base address. These offsets are defined in the WRP address registers: Flash WRP area A address register (FLASH_WRP1AR), Flash WRP area B address register (FLASH_WRP1BR). The WRP “y” area (y=A,B) is defined from the address: Flash memory Base address + [WRP1y_STRT x 0x800] (included) to the address: Flash memory Base address + [(WRP1y_END+1) x 0x800] (excluded). For example, to protect by WRP from the address 0x0806 2800 (included) to the address 0x0807 07FF (included): • if boot in flash is selected, FLASH_WRP1AR register must be programmed with: – WRP1A_STRT = 0xC5. – WRP1A_END = 0xE0. WRP1B_STRT and WRP1B_END in FLASH_WRP1BR can be used instead (area “B” in Flash memory). When WRP is active, it cannot be erased or programmed. Consequently, a software mass erase cannot be performed if one area is write-protected. If an erase/program operation to a write-protected part of the Flash memory is attempted, the write protection error flag (WRPERR) is set in the FLASH_SR register. This flag is also set for any write access to: Note: 98/1600 – OTP area – part of the Flash memory that can never be written like the ICP – PCROP area. When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase Flash memory if the CPU debug features are connected (JTAG or single wire) or boot code is being executed from RAM or System flash, even if WRP is not activated. RM0394 Rev 4 RM0394 Embedded Flash memory (FLASH) Note: To validate the WRP options, the option bytes must be reloaded through the OBL_LAUNCH bit in Flash control register. 3.6 FLASH interrupts Table 14. Flash interrupt request Interrupt event Event flag Event flag/interrupt clearing method Interrupt enable control bit End of operation EOP(1) Write EOP=1 EOPIE Operation error OPERR(2) Write OPERR=1 ERRIE RDERR Write RDERR=1 RDERRIE ECCC Write ECCC=1 ECCCIE Read error ECC correction 1. EOP is set only if EOPIE is set. 2. OPERR is set only if ERRIE is set. RM0394 Rev 4 99/1600 113 Embedded Flash memory (FLASH) RM0394 3.7 FLASH registers 3.7.1 Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0600 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. SLEEP _PD DCEN ICEN PRFTEN Res. Res. Res. Res. Res. rw rw rw RUN_ DCRST ICRST PD rw rw rw rw LATENCY[2:0] rw rw rw -- Bits 31:15 Reserved, must be kept at reset value. Bit 14 SLEEP_PD: Flash Power-down mode during Sleep or Low-power sleep mode This bit determines whether the flash memory is in Power-down mode or Idle mode when the device is in Sleep or Low-power sleep mode. 0: Flash in Idle mode during Sleep and Low-power sleep modes 1: Flash in Power-down mode during Sleep and Low-power sleep modes Caution: The flash must not be put in power-down while a program or an erase operation is on-going. Bit 13 RUN_PD: Flash Power-down mode during Run or Low-power run mode This bit is write-protected with FLASH_PDKEYR. This bit determines whether the flash memory is in Power-down mode or Idle mode when the device is in Run or Low-power run mode. The flash memory can be put in power-down mode only when the code is executed from RAM. The Flash must not be accessed when RUN_PD is set. 0: Flash in Idle mode 1: Flash in Power-down mode Caution: The flash must not be put in power-down while a program or an erase operation is on-going. Bit 12 DCRST: Data cache reset 0: Data cache is not reset 1: Data cache is reset This bit can be written only when the data cache is disabled. Bit 11 ICRST: Instruction cache reset 0: Instruction cache is not reset 1: Instruction cache is reset This bit can be written only when the instruction cache is disabled. Bit 10 DCEN: Data cache enable 0: Data cache is disabled 1: Data cache is enabled 100/1600 RM0394 Rev 4 RM0394 Embedded Flash memory (FLASH) Bit 9 ICEN: Instruction cache enable 0: Instruction cache is disabled 1: Instruction cache is enabled Bit 8 PRFTEN: Prefetch enable 0: Prefetch disabled 1: Prefetch enabled Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 LATENCY[2:0]: Latency These bits represent the period to the Flash access time. 000: Zero wait state 001: One wait state 010: Two wait states 011: Three wait states 100: Four wait states others: Reserved 3.7.2 Flash Power-down key register (FLASH_PDKEYR) Address offset: 0x04 Reset value: 0x0000 0000 Access: no wait state, word access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PDKEYR[31:16] w w w w w w w 15 14 13 12 11 10 9 w w w w w w w w w 8 7 6 5 4 3 2 1 0 w w w w w w w PDKEYR[15:0] w w w w w w w w w Bits 31:0 PDKEYR: Power-down in Run mode Flash key The following values must be written consecutively to unlock the RUN_PD bit in FLASH_ACR: PDKEY1: 0x0415 2637 PDKEY2: 0xFAFB FCFD 3.7.3 Flash key register (FLASH_KEYR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEYR[31:16] w w w w w w w 15 14 13 12 11 10 9 w w w w w w w w w 8 7 6 5 4 3 2 1 0 w w w w w w w KEYR[15:0] w w w w w w w w w RM0394 Rev 4 101/1600 113 Embedded Flash memory (FLASH) RM0394 Bits 31:0 KEYR: Flash key The following values must be written consecutively to unlock the FLASH_CR register allowing flash programming/erasing operations: KEY1: 0x4567 0123 KEY2: 0xCDEF 89AB 3.7.4 Flash option key register (FLASH_OPTKEYR) Address offset: 0x0C Reset value: 0x0000 0000 Access: no wait state, word access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OPTKEYR[31:16] w w w w w w w 15 14 13 12 11 10 9 w w w w w w w w w 8 7 6 5 4 3 2 1 0 w w w w w w w OPTKEYR[15:0] w w w w w w w w w Bits 31:0 OPTKEYR: Option byte key The following values must be written consecutively to unlock the FLASH_OPTR register allowing option byte programming/erasing operations: KEY1: 0x0819 2A3B KEY2: 0x4C5D 6E7F 3.7.5 Flash status register (FLASH_SR) Address offset: 0x10 Reset value: Access: no wait state, word, half-word and byte access 31 Res. 30 Res. 15 14 OPTV ERR RD ERR rc_w1 rc_w1 102/1600 29 Res. 13 Res. 28 Res. 12 Res. 27 Res. 11 Res. 26 Res. 25 Res. 24 Res. 23 Res. 22 Res. 21 Res. 20 Res. 19 Res. 10 9 8 7 6 5 4 3 Res. FAST ERR MISS ERR PGS ERR SIZ ERR PGA ERR WRP ERR PROG ERR rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 RM0394 Rev 4 18 17 16 Res. PEMPT Y BSY rs r 2 1 0 Res. OP ERR EOP rc_w1 rc_w1 RM0394 Embedded Flash memory (FLASH) Bits 31:18 Reserved, must be kept at reset value. Bit 17 PEMPTY: Program EMPTY Set by hardware on power-on reset or after OBL_LAUNCH command execution if the Flash is not programmed and the user intends to boot from the main Flash. Cleared by hardware on power-on reset or after OBL_LAUNCH command execution if the Flash is programmed and the user intends to boot from main Flash. This bit can also be set and cleared by software. 1: The bit value is toggling 0: No effect This bit can be set to clear the Program Empty bit if an OBL_LAUNCH is done by software after Flash programming (boot in main flash selected). It finally forces the boot in the main flash, without loosing the debugger connection. Bit 16 BSY: Busy This indicates that a Flash operation is in progress. This is set on the beginning of a Flash operation and reset when the operation finishes or when an error occurs. Bit 15 OPTVERR: Option validity error Set by hardware when the options read may not be the one configured by the user. If option haven’t been properly loaded, OPTVERR is set again after each system reset. Cleared by writing 1. Bit 14 RDERR: PCROP read error Set by hardware when an address to be read through the D-bus belongs to a read protected area of the flash (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR. Cleared by writing 1. Bits 13:10 Reserved, must be kept at reset value. Bit 9 FASTERR: Fast programming error Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time. Cleared by writing 1. Bit 8 MISERR: Fast programming data miss error In Fast programming mode, 32 double words must be sent to flash successively, and the new data must be sent to the flash logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time. Cleared by writing 1. Bit 7 PGSERR: Programming sequence error Set by hardware when a write access to the Flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, MISSERR or FASTERR is set due to a previous programming error. Cleared by writing 1. RM0394 Rev 4 103/1600 113 Embedded Flash memory (FLASH) RM0394 Bit 6 SIZERR: Size error Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access). Cleared by writing 1. Bit 5 PGAERR: Programming alignment error Set by hardware when the data to program cannot be contained in the same 64bit Flash memory row in case of standard programming, or if there is a change of page during fast programming. Cleared by writing 1. Bit 4 WRPERR: Write protection error Set by hardware when an address to be erased/programmed belongs to a writeprotected part (by WRP, PCROP or RDP level 1) of the Flash memory. Cleared by writing 1. Bit 3 PROGERR: Programming error Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'. Cleared by writing 1. Bit 2 Reserved, must be kept at reset value. Bit 1 OPERR: Operation error Set by hardware when a Flash memory operation (program / erase) completes unsuccessfully. This bit is set only if error interrupts are enabled (ERRIE = 1). Cleared by writing ‘1’. Bit 0 EOP: End of operation Set by hardware when one or more Flash memory operation (programming / erase) has been completed successfully. This bit is set only if the end of operation interrupts are enabled (EOPIE = 1). Cleared by writing 1. 3.7.6 Flash control register (FLASH_CR) Address offset: 0x14 Reset value: 0xC000 0000 Access: no wait state when no Flash memory operation is on going, word, half-word and byte access 31 30 LOCK OPT LOCK 29 28 27 26 25 24 Res. Res. OBL_ LAUNCH RD ERRIE ERR IE EOP IE rs rs rc_w1 rw rw rw 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. 22 21 20 19 Res. Res. Res. Res. Res. 7 6 5 4 3 PNB[7:0] rw 104/1600 23 rw rw rw RM0394 Rev 4 rw rw rw rw 18 17 16 FSTPG OPT STRT STRT rw rs rs 2 1 0 MER1 PER PG rw rw rw RM0394 Embedded Flash memory (FLASH) Bit 31 LOCK: FLASH_CR Lock This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. Bit 30 OPTLOCK: Options Lock This bit is set only. When set, all bits concerning user option in FLASH_CR register and so option page are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset. Bits 29:28 Reserved, must be kept at reset value. Bit 27 OBL_LAUNCH: Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set. 0: Option byte loading complete 1: Option byte loading requested Bit 26 RDERRIE: PCROP read error interrupt enable This bit enables the interrupt generation when the RDERR bit in the FLASH_SR is set to 1. 0: PCROP read error interrupt disabled 1: PCROP read error interrupt enabled Bit 25 ERRIE: Error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_SR is set to 1. 0: OPERR error interrupt disabled 1: OPERR error interrupt enabled Bit 24 EOPIE: End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SR is set to 1. 0: EOP Interrupt disabled 1: EOP Interrupt enabled Bits 23:19 Reserved, must be kept at reset value Bit 18 FSTPG: Fast programming 0: Fast programming disabled 1: Fast programming enabled Bit 17 OPTSTRT: Options modification start This bit triggers an options operation when set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_SR. Bit 16 STRT: Start This bit triggers an erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, an unpredictable behavior may occur without generating any error flag. This condition should be forbidden. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_SR. Bits 15:11 Reserved, must be kept at reset value. RM0394 Rev 4 105/1600 113 Embedded Flash memory (FLASH) RM0394 Bits 10:3 PNB[7:0]: Page number selection These bits select the page to erase: 00000000: page 0 00000001: page 1 ... 11111111: page 255 Note: Bit 10 is used on STM32L45x and STM32L46x devices only. Bit 2 MER1: Mass erase This bit triggers the mass erase (all user pages) when set. Bit 1 PER: Page erase 0: page erase disabled 1: page erase enabled Bit 0 PG: Programming 0: Flash programming disabled 1: Flash programming enabled 3.7.7 Flash ECC register (FLASH_ECCR) Address offset: 0x18 Reset value: 0x0000 0000 Access: no wait state when no Flash memory operation is on going, word, half-word and byte access 31 30 ECCD ECCC rc_w1 rc_w1 15 r 29 28 27 26 25 24 ECCC IE Res. Res. Res. Res. Res. 14 13 12 11 10 9 r r r r r r 23 22 21 20 19 Res. 17 16 Res. Res. Res. r r r 7 6 5 4 3 2 1 0 r r r r r r r rw 8 18 SYSF_ ECC r ADDR_ECC[18:16] ADDR_ECC[15:0] r r Bit 31 ECCD: ECC detection Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is generated Cleared by writing 1. Bit 30 ECCC: ECC correction Set by hardware when one ECC error has been detected and corrected. An interrupt is generated if ECCIE is set. Cleared by writing 1. Bits 29:25 Reserved, must be kept at reset value. Bit 24 ECCIE: ECC correction interrupt enable 0: ECCC interrupt disabled 1: ECCC interrupt enabled. Bits 23:21 Reserved, must be kept at reset value. 106/1600 RM0394 Rev 4 RM0394 Embedded Flash memory (FLASH) Bit 20 SYSF_ECC: System Flash ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the System Flash. Bit 19 Reserved, must be kept at reset value. Bits 18:0 ADDR_ECC: ECC fail address This bit indicates which address in the bank is concerned by the ECC error correction or by the double ECC error detection. 3.7.8 Flash option register (FLASH_OPTR) Address offset: 0x20 Reset value: 0xXXXX XXXX. Register bits 0 to 31 are loaded with values from Flash memory at OBL. Access: no wait state when no Flash memory operation is on going; word, half-word and byte access 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. nRST_ nRST_ nRST_ SHDW STDBY STOP rw rw rw 27 26 25 24 23 n nSW SRAM2 SRAM2 nBOOT BOOT0 BOOT0 _RST _PE 1 rw rw rw rw rw 11 10 9 8 7 Res. 22 21 Res. Res. Res. 6 5 4 BOR_LEV[2:0] rw rw 20 19 18 17 16 WWDG IWGD_ IWDG_ IWDG_ _SW STDBY StOP SW rw rw rw rw 3 2 1 0 rw rw rw RDP[7:0] rw rw rw rw rw rw Bits 31:28 Reserved, must be kept at reset value. Bit 27 nBOOT0: nBOOT0 option bit 0: nBOOT0 = 0 1: nBOOT0 = 1 Bit 26 nSWBOOT0: Software BOOT0 0: BOOT0 taken from the option bit nBOOT0 1: BOOT0 taken from PH3/BOOT0 pin Bit 25 SRAM2_RST: SRAM2 Erase when system reset 0: SRAM2 erased when a system reset occurs 1: SRAM2 is not erased when a system reset occurs Bit 24 SRAM2_PE: SRAM2 parity check enable 0: SRAM2 parity check enable 1: SRAM2 parity check disable Bit 23 nBOOT1: Boot configuration Together with the BOOT0 pin, this bit selects boot mode from the Flash main memory, SRAM1 or the System memory. Refer to Section 2.6: Boot configuration. Bits 22:20 Reserved, must be kept at reset value. Bit 19 WWDG_SW: Window watchdog selection 0: Hardware window watchdog 1: Software window watchdog RM0394 Rev 4 107/1600 113 Embedded Flash memory (FLASH) RM0394 Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode 0: Independent watchdog counter is frozen in Standby mode 1: Independent watchdog counter is running in Standby mode Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode 0: Independent watchdog counter is frozen in Stop mode 1: Independent watchdog counter is running in Stop mode Bit 16 IDWG_SW: Independent watchdog selection 0: Hardware independent watchdog 1: Software independent watchdog Bit 15 Reserved, must be kept at reset value Bit 14 nRST_SHDW 0: Reset generated when entering the Shutdown mode 1: No reset generated when entering the Shutdown mode Bit 13 nRST_STDBY 0: Reset generated when entering the Standby mode 1: No reset generate when entering the Standby mode Bit 12 nRST_STOP 0: Reset generated when entering the Stop mode 1: No reset generated when entering the Stop mode Bit 11 Reserved, must be kept at reset value Bits10:8 BOR_LEV: BOR reset Level These bits contain the VDD supply level threshold that activates/releases the reset. 000: BOR Level 0. Reset level threshold is around 1.7 V 001: BOR Level 1. Reset level threshold is around 2.0 V 010: BOR Level 2. Reset level threshold is around 2.2 V 011: BOR Level 3. Reset level threshold is around 2.5 V 100: BOR Level 4. Reset level threshold is around 2.8 V Bits 7:0 RDP: Read protection level 0xAA: Level 0, read protection not active 0xCC: Level 2, chip read protection active Others: Level 1, memories read protection active Note: Take care about PCROP_RDP configuration in Level 1. Refer to Section : Level 1: Read protection for more details. 108/1600 RM0394 Rev 4 RM0394 Embedded Flash memory (FLASH) 3.7.9 Flash PCROP Start address register (FLASH_PCROP1SR) Address offset: 0x24 Reset value: 0xFFFF XXXX. Register bits are loaded with values from Flash memory at OBL. Reserved bits are read as “1”. Access: no wait state when no Flash memory operation is on going; word, half-word access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PCROP1_STRT[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value Bits 15:0 PCROP1_STRT: PCROP area start offset PCROP1_STRT contains the first double-word of the PCROP area. 3.7.10 Flash PCROP End address register (FLASH_PCROP1ER) Address offset: 0x28 Reset value: 0xXFFF XXXX. Register bits are loaded with values from Flash memory at OBL. Reserved bits are read as “1”. Access: no wait state when no Flash memory operation is on going; word, half-word access. PCROP_RDP bit can be accessed with byte access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PCROP _RDP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rs PCROP1_END[15:0] rw rw Bit 31 PCROP_RDP: PCROP area preserved when RDP level decreased This bit is set only. It is reset after a full mass erase due to a change of RDP from Level 1 to Level 0. 0: PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0. 1: PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase). Bits 30:16 Reserved, must be kept at reset value Bits 15:0 PCROP1_END: PCROP area end offset PCROP1_END contains the last double-word of the PCROP area. RM0394 Rev 4 109/1600 113 Embedded Flash memory (FLASH) 3.7.11 RM0394 Flash WRP area A address register (FLASH_WRP1AR) Address offset: 0x2C Reset value: 0xFFXX FFXX. Register bits are loaded with values from Flash memory at OBL. Reserved bits are read as “1”. Access: no wait state when no Flash memory operation is on going; word, half-word and byte access 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 WRP1A_END[7:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw WRP1A_STRT[7:0] rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value Bits 23:16 WRP1A_END: WRP first area “A” end offset WRP1A_END contains the last page of the WRP first area. Note: Number of used bits depends on the size of Flash memory available on given device. Bits 15:8 Reserved, must be kept at reset value Bits 7:0 WRP1A_STRT: WRP first area “A” start offset WRP1A_STRT contains the first page of the WRP first area. Note: Number of used bits depends on the size of Flash memory available on given device. 3.7.12 Flash WRP area B address register (FLASH_WRP1BR) Address offset: 0x30 Reset value: 0xFFXX FFXX. Register bits are loaded with values from Flash memory at OBL. Reserved bits are read at “1”. Access: no wait state when no Flash memory operation is on going; word, half-word and byte access 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 rw rw rw rw 7 6 5 4 19 18 17 16 rw rw rw rw 3 2 1 0 rw rw rw WRP1B_END[7:0] WRP1B_STRT[7:0] rw 110/1600 20 RM0394 Rev 4 rw rw rw rw RM0394 Embedded Flash memory (FLASH) Bits 31:24 Reserved, must be kept at reset value Bits 23:16 WRP1B_END: WRP second area “B” end offset WRP1B_END contains the last page of the WRP second area. Note: Number of used bits depends on the size of Flash memory available on given device. Bits 15:8 Reserved, must be kept at reset value Bits 7:0 WRP1B_STRT: WRP second area “B” start offset WRP1B_STRT contains the first page of the WRP second area. Note: Number of used bits depends on the size of Flash memory available on given device. RM0394 Rev 4 111/1600 113 Embedded Flash memory (FLASH) 3.7.13 RM0394 FLASH register map ICEN PRFTEN 1 1 0 FLASH_ PDKEYR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_OPT KEYR 0 0 0 0 0 0 0 0 0 0 0 112/1600 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 X 0 0 0 0 0 0 Res. Res. Res. 0 IWDG_SW Res. nRST_SHDW nRST_STDBY nRST_STOP Res. Res. Res. IWDG_STOP Res. Res. nBOOT1 Res. Res. SRAM2_PE Res. Res. nSWBOOT0 SRAM2_RST FLASH_ PCROP1SR Res. X nBOOT0 X X Res. X X X X X X X RM0394 Rev 4 X X X X X Res. X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDP[7:0] X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Res. Res. Res. Res. Res. PCROP1_END[15:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1A_END[7:0] X 0 0 PCROP1_STRT[15:0] X Res. 0 X X Res. 0 X X Res. 0 X X PCROP_RDP. 0 X X X 0 X X FLASH_ WRP1AR 0 X X X 0 IWDG_STBY 0 Res. 0 WWDG_SW 0 Res. 0 X X Reset value 0 BOR_ LEV[2:0] Reset value 0 0 ADDR_ECC[18:0] 0 FLASH_OPTR FLASH_ PCROP1ER 0 Res. 0 0 0 PNB[7:0] 0 Res. SYSF_ECC Res. Res. 0 EOP Res. Res. Res. 0 PG Res. EOPIE Res. ECCCIE 0 PER Res. ERRIE Res. 0 Res. OPERR Res. RDERRIE Res. 0 MER1 Res. 0 0 PROGERR Res. Res. OBL_LAUNCH 0 Res. 0 0 Res. ECCC 0 0 Res. ECCD Reset value Res. OPTLOCK FLASH_ECCR Res. 1 Res. 1 Res. LOCK Reset value Res. FLASH_CR 0 WRPERR FLASH_SR 0 PGAERR 0 SIZERR 0 PGSERR 0 MISERR 0 Res. FASTERR 0 Res. 0 Res. 0 Reset value 0 Res. 0 Res. 0 Res. 0 RDERR 0 Res. 0x2C 0 OPTVERR 0 Reset value 0x28 0 BSY 0 Res. 0x24 0 STRT 0 Res. 0x20 0 OPTSTRT Reset value Res. 0x18 0 OPTKEYR[31:0] Reset value 0x14 0 Res. Reset value 0 KEYR[31:0] Res. 0x10 0 Res. 0x0C 0 Res. 0x08 0 FLASH_KEYR Res. Reset value LATENCY [2:0] PDKEYR[31:0] Res. FSTPG 0x04 Res. DCEN 0 Res. ICRST 0 Res. DCRST 0 Res. RUN_PD 0 Reset value Res. Res. SLEEP_PD Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLASH_ACR Res. 0x00 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 15. Flash interface - register map and reset values X X X WRP1A_STRT[7:0] X X X X X X X X RM0394 Embedded Flash memory (FLASH) Reset value X X X X X X X Res. Res. Res. Res. Res. Res. WRP1B_END[7:0] Res. Res. Res. Res. Res. Res. Res. Res. FLASH_ WRP1BR Res. 0x30 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 15. Flash interface - register map and reset values (continued) X WRP1B_STRT[7:0] X X X X X X X X Refer to Section 2.2.2 on page 67 for the register boundary addresses. RM0394 Rev 4 113/1600 113 Firewall (FW) RM0394 4 Firewall (FW) 4.1 Introduction The Firewall is made to protect a specific part of code or data into the Non-Volatile Memory, and/or to protect the Volatile data into the SRAM 1 from the rest of the code executed outside the protected area. 4.2 Firewall main features • • The code to protect by the Firewall (Code Segment) may be located in: – The Flash memory map – The SRAM 1 memory, if declared as an executable protected area during the Firewall configuration step. The data to protect can be located either – in the Flash memory (non-volatile data segment) – in the SRAM 1 memory (volatile data segment) The software can access these protected areas once the Firewall is opened. The Firewall can be opened or closed using a mechanism based on “call gate” (Refer to Opening the Firewall). The start address of each segment and its respective length must be configured before enabling the Firewall (Refer to Section 4.3.5: Firewall initialization). Each illegal access into these protected segments (if the Firewall is enabled) generates a reset which immediately kills the detected intrusion. Any DMA access to protected segments is forbidden whatever the Firewall state (opened or closed). It is considered as an illegal access and generates a reset. 114/1600 RM0394 Rev 4 RM0394 Firewall (FW) 4.3 Firewall functional description 4.3.1 Firewall AMBA bus snoop The Firewall peripheral is snooping the AMBA buses on which the memories (volatile and non-volatile) are connected. A global architecture view is illustrated in Figure 5. Figure 5. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx firewall connection schematics $+%6ODYH $+%0DVWHU &257(;0 $+%0DVWHU '0$ % 8 6 0 $ 7 5 , ; , 1 7 ( 5 ) $ & ( )/$6+ ),5(:$// 65$0 $+%6ODYH 0V99 4.3.2 Functional requirements There are several requirements to guaranty the highest security level by the application code/data which needs to be protected by the Firewall and to avoid unwanted Firewall alarm (reset generation). Debug consideration In debug mode, if the Firewall is opened, the accesses by the debugger to the protected segments are not blocked. For this reason, the Read out level 2 protection must be active in conjunction with the Firewall implementation. If the debug is needed, it is possible to proceed in the following way: • A dummy code having the same API as the protected code may be developed during the development phase of the final user code. This dummy code may send back coherent answers (in terms of function and potentially timing if needed), as the protected code should do in production phase. • In the development phase, the protected code can be given to the customer-end under NDA agreement and its software can be developed in level 0 protection. The customer- RM0394 Rev 4 115/1600 125 Firewall (FW) RM0394 end code needs to embed an IAP located in a write protected segment in order to allow future code updates when the production parts will be Level 2 ROP. Write protection In order to offer a maximum security level, the following points need to be respected: • It is mandatory to keep a write protection on the part of the code enabling the Firewall. This activation code should be located outside the segments protected by the Firewall. • The write protection is also mandatory on the code segment protected by the Firewall. • The page including the reset vector must be write-protected. Interrupts management The code protected by the Firewall must not be interruptible. It is up to the user code to disable any interrupt source before executing the code protected by the Firewall. If this constraint is not respected, if an interruption comes while the protected code is executed (Firewall opened), the Firewall will be closed as soon as the interrupt subroutine is executed. When the code returns back to the protected code area, a Firewall alarm will raise since the “call gate” sequence will not be applied and a reset will be generated. Concerning the interrupt vectors and the first user page in the Flash memory: • If the first user page (including the reset vector) is protected by the Firewall, the NVIC vector should be reprogrammed outside the protected segment. • If the first user page is not protected by the Firewall, the interrupt vectors may be kept at this location. There is no interrupt generated by the Firewall. 4.3.3 Firewall segments The Firewall has been designed to protect three different segment areas: Code segment This segment is located into the Flash memory. It should contain the code to execute which requires the Firewall protection. The segment must be reached using the “call gate” entry sequence to open the Firewall. A system reset is generated if the “call gate” entry sequence is not respected (refer to Opening the Firewall) and if the Firewall is enabled using the FWDIS bit in the system configuration register. The length of the segment and the segment base address must be configured before enabling the Firewall (refer to Section 4.3.5: Firewall initialization). Non-volatile data segment This segment contains non-volatile data used by the protected code which must be protected by the Firewall. The access to this segment is defined into Section 4.3.4: Segment accesses and properties. The Firewall must be opened before accessing the data in this area. The Non-Volatile data segment should be located into the Flash memory. The segment length and the base address of the segment must be configured before enabling the Firewall (refer to Section 4.3.5: Firewall initialization). 116/1600 RM0394 Rev 4 RM0394 Firewall (FW) Volatile data segment Volatile data used by the protected code located into the code segment must be defined into the SRAM 1 memory. The access to this segment is defined into the Section 4.3.4: Segment accesses and properties. Depending on the Volatile data segment configuration, the Firewall must be opened or not before accessing this segment area. The segment length and the base address of the segment as well as the segment options must be configured before enabling the Firewall (refer to Section 4.3.5: Firewall initialization). The Volatile data segment can also be defined as executable (for the code execution) or shared using two bit of the Firewall configuration register (bit VDS for the volatile data sharing option and bit VDE for the volatile data execution capability). For more details, refer to Table 16. 4.3.4 Segment accesses and properties All DMA accesses to the protected segments are forbidden, whatever the Firewall state, and generate a system reset. Segment access depending on the Firewall state Each of the three segments has specific properties which are presented in Table 16. Table 16. Segment accesses according to the Firewall state Segment Code segment Non-volatile data segment Volatile data segment Firewall opened access allowed Read and execute Read and write Read and Write Execute if VDE = 1 and VDS = 0 into the Firewall configuration register Firewall closed access allowed Firewall disabled access allowed No access allowed. Any access to the segment (except the “call gate” entry) generates a system reset All accesses are allowed (according to the Flash page protection properties in which the code is located) No access allowed All accesses are allowed (according to the Flash page protection properties in which the code is located) No access allowed if VDS = 0 and VDE = 0 into the Firewall configuration register Read/write/execute accesses allowed if VDS = 1 (whatever VDE bit value) Execute if VDE = 1 and VDS = 0 but with a “call gate” entry to open the Firewall at first. All accesses are allowed RM0394 Rev 4 117/1600 125 Firewall (FW) RM0394 The Volatile data segment is a bit different from the two others. The segment can be: • Shared (VDS bit in the register) It means that the area and the data located into this segment can be shared between the protected code and the user code executed in a non-protected area. The access is allowed whether the Firewall is opened or closed or disabled. The VDS bit gets priority over the VDE bit, this last bit value being ignored in such a case. It means that the Volatile data segment can execute parts of code located there without any need to open the Firewall before executing the code. • Execute The VDE bit is considered as soon as the VDS bit = 0 in the FW_CR register. If the VDS bit = 1, refer to the description above on the Volatile data segment sharing. If VDS = 0 and VDE = 1, the Volatile data segment is executable. To avoid a system reset generation from the Firewall, the “call gate” sequence should be applied on the Volatile data segment to open the Firewall as an entry point for the code execution. Segments properties Each segment has a specific length register to define the segment size to be protected by the Firewall: CSL register for the Code segment length register, NVDSL for the Non-volatile data segment length register, and VDSL register for the Volatile data segment length register. Granularity and area ranges for each of the segments are presented in Table 17. Table 17. Segment granularity and area ranges Segment Granularity Code segment Non-volatile data segment Area range 256 byte 1024 Kbytes - 256 bytes 256 byte 1024 Kbytes - 256 bytes Volatile data segment (1) 64 byte 96 Kbytes - 64 bytes Volatile data segment (2) 64 byte 128 Kbyte - 64 byte 1. Applicable to STM32L43xxx and STM32L44xxx devices only. 2. Applicable to STM32L45xxx and STM32L46xxx devices only. 4.3.5 Firewall initialization The initialization phase should take place at the beginning of the user code execution (refer to the Write protection). The initialization phase consists of setting up the addresses and the lengths of each segment which needs to be protected by the Firewall. It must be done before enabling the Firewall, because the enabling bit can be written once. Thus, when the Firewall is enabled, it cannot be disabled anymore until the next system reset. Once the Firewall is enabled, the accesses to the address and length segments are no longer possible. All write attempts are discarded. A segment defined with a length equal to 0 is not considered as protected by the Firewall. As a consequence, there is no reset generation from the Firewall when an access to the base address of this segment is performed. After a reset, the Firewall is disabled by default (FWDIS bit in the SYSCFG register is set). It has to be cleared to enable the Firewall feature. 118/1600 RM0394 Rev 4 RM0394 Firewall (FW) Below is the initialization procedure to follow: 1. Configure the RCC to enable the clock to the Firewall module 2. Configure the RCC to enable the clock of the system configuration registers 3. Set the base address and length of each segment (CSSA, CSL, NVDSSA, NVDSL, VDSSA, VDSL registers) 4. Set the configuration register of the Firewall (FW_CR register) 5. Enable the Firewall clearing the FWDIS bit in the system configuration register. The Firewall configuration register (FW_CR register) is the only one which can be managed in a dynamic way even if the Firewall is enabled: 4.3.6 • when the Non-Volatile data segment is undefined (meaning the NVDSL register is equal to 0), the accesses to this register are possible whatever the Firewall state (opened or closed). • when the Non-Volatile data segment is defined (meaning the NVDSL register is different from 0), the accesses to this register are only possible when the Firewall is opened. Firewall states The Firewall has three different states as shown in Figure 6: • Disabled: The FWDIS bit is set by default after the reset. The Firewall is not active. • Closed: The Firewall protects the accesses to the three segments (Code, Non-volatile data, and Volatile data segments). • Opened: The Firewall allows access to the protected segments as defined in Section 4.3.4: Segment accesses and properties. Figure 6. Firewall functional states )LUHZDOOGLVDEOH UHVHW ,OOHJDODFFHVVHVWR WKHSURWHFWHG VHJPHQWV (QDEOHWKHILUHZDOO ):',6 3URWHFWHGFRGHMXPSV WRDQXQSURWHFWHG VHJPHQWDQG)3$ µµFDOOJDWH¶¶HQWU\ )LUHZDOO FORVHG )LUHZDOO RSHQHG &RGHSURWHFWHGMXPSV WRXQSURWHFWHG VHJPHQWV 069 RM0394 Rev 4 119/1600 125 Firewall (FW) RM0394 Opening the Firewall As soon as the Firewall is enabled, it is closed. It means that most of the accesses to the protected segments are forbidden (refer to Section 4.3.4: Segment accesses and properties). In order to open the Firewall to interact with the protected segments, it is mandatory to apply the “call gate” sequence described hereafter. “call gate” sequence The “call gate” is composed of 3 words located on the first three 32-bit addresses of the base address of the code segment and of the Volatile data segment if it is declared as not shared (VDS = 0) and executable (VDE = 1). – 1st word: Dummy 32-bit words always closed in order to protect the “call gate” opening from an access due to a prefetch buffer. – 2nd and 3rd words: 2 specific 32-bit words called “call gate” and always opened. To open the Firewall, the code currently executed must jump to the 2nd word of the “call gate” and execute the code from this point. The 2nd word and 3rd word execution must not be interrupted by any intermediate instruction fetch; otherwise, the Firewall is not considered open and comes back to a close state. Then, executing the 3rd word after receiving the intermediate instruction fetch would generate a system reset as a consequence. As soon as the Firewall is opened, the protected segments can be accessed as described in Section 4.3.4: Segment accesses and properties. Closing the Firewall The Firewall is closed immediately after it is enabled (clearing the FWDIS bit in the system configuration register). To close the Firewall, the protected code must: • Write the correct value in the Firewall Pre Arm Flag into the FW_CR register. • Jump to any executable location outside the Firewall segments. If the Firewall Pre Arm Flag is not set when the protected code jumps to a non protected segment, a reset is generated. This control bit is an additional protection to avoid an undesired attempt to close the Firewall with the private information not yet cleaned (see the note below). For security reasons, following the application for which the Firewall is used, it is advised to clean all private information from CPU registers and hardware cells. 120/1600 RM0394 Rev 4 RM0394 Firewall (FW) 4.4 Firewall registers 4.4.1 Code segment start address (FW_CSSA) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 ADD[23:16] rw 15 14 13 12 11 10 9 8 ADD[15:8] 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:8 ADD[23:8]: code segment start address The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a 256-byte granularity. Note: These bits can be written only before enabling the Firewall. Refer to Section 4.3.5: Firewall initialization. Bits 7:0 Reserved, must be kept at the reset value. 4.4.2 Code segment length (FW_CSL) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21 20 19 18 17 16 LENG[21:16] rw 15 14 13 12 11 LENG15:8] 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:22 Reserved, must be kept at the reset value. Bits 21:8 LENG[21:8]: code segment length LENG[21:8] selects the size of the code segment expressed in bytes but is a multiple of 256 bytes. The segment area is defined from {ADD[23:8],0x00} to {ADD[23:8]+LENG[21:8], 0x00} - 0x01 Note: If LENG[21:8] = 0 after enabling the Firewall, this segment is not defined, thus not protected by the Firewall. These bits can only be written before enabling the Firewall. Refer to Section 4.3.5: Firewall initialization. Bits 7:0 Reserved, must be kept at the reset value. RM0394 Rev 4 121/1600 125 Firewall (FW) 4.4.3 RM0394 Non-volatile data segment start address (FW_NVDSSA) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 ADD[23:16] rw 15 14 13 12 11 10 9 8 ADD[15:8] 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:24 Reserved, must be kept at the reset value. Bits 23:8 ADD[23:8]: Non-volatile data segment start address The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a 256-byte granularity. Note: These bits can only be written before enabling the Firewall. Refer to Section 4.3.5: Firewall initialization. Bits 7:0 Reserved, must be kept at the reset value. 4.4.4 Non-volatile data segment length (FW_NVDSL) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21 20 19 18 17 16 LENG[21:16] rw 15 14 13 12 11 LENG[15:8] 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:22 Reserved, must be kept at the reset value. Bits 21:8 LENG[21:8]: Non-volatile data segment length LENG[21:8] selects the size of the Non-volatile data segment expressed in bytes but is a multiple of 256 bytes. The segment area is defined from {ADD[23:8],0x00} to {ADD[23:8]+LENG[21:8], 0x00} - 0x01 Note: If LENG[21:8] = 0 after enabling the Firewall, this segment is not defined, thus not protected by the Firewall. These bits can only be written before enabling the Firewall. Refer to Section 4.3.5: Firewall initialization. Bits 7:0 Reserved, must be kept at the reset value. 122/1600 RM0394 Rev 4 RM0394 Firewall (FW) 4.4.5 Volatile data segment start address (FW_VDSSA) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADD [16] rw 15 14 13 12 11 10 9 8 7 6 ADD[15:6] 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. rw Bits 31:17 Reserved, must be kept at the reset value. Bits 16:6 ADD[16:6]: Volatile data segment start address The LSB bits of the start address (bit 5:0) are reserved and forced to 0 in order to allow a 64-byte granularity. Note: These bits can only be written before enabling the Firewall. Refer to Section 4.3.5: Firewall initialization Bits 5:0 Reserved, must be kept at the reset value. 4.4.6 Volatile data segment length (FW_VDSL) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LENG [16] rw 15 14 13 12 11 10 9 8 7 LENG[15:6] 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. rw Bits 31:17 Reserved, must be kept at the reset value. Bits 16:6 LENG[16:6]: volatile data segment length LENG[16:6] selects the size of the volatile data segment expressed in bytes but is a multiple of 64 bytes. The segment area is defined from {ADD[16:6],0x00} to {ADD[16:6]+LENG[16:6], 0x00} - 0x01 Note: If LENG[16:6] = 0 after enabling the Firewall, this segment is not defined, thus not protected by the Firewall. These bits can only be written before enabling the Firewall. Refer to Section 4.3.5: Firewall initialization. Bits 5:0 Reserved, must be kept at the reset value. RM0394 Rev 4 123/1600 125 Firewall (FW) 4.4.7 RM0394 Configuration register (FW_CR) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VDE VDS FPA rw rw rw Bits 31:3 Reserved, must be kept at the reset value. Bit 2 VDE: Volatile data execution 0: Volatile data segment cannot be executed if VDS = 0 1: Volatile data segment is declared executable whatever VDS bit value When VDS = 1, this bit has no meaning. The Volatile data segment can be executed whatever the VDE bit value. If VDS = 1, the code can be executed whatever the Firewall state (opened or closed) If VDS = 0, the code can only be executed if the Firewall is opened or applying the “call gate” entry sequence if the Firewall is closed. Refer to Segment access depending on the Firewall state. Bit 1 VDS: Volatile data shared 0: Volatile data segment is not shared and cannot be hit by a non protected executable code when the Firewall is closed. If it is accessed in such a condition, a system reset will be generated by the Firewall. 1: Volatile data segment is shared with non protected application code. It can be accessed whatever the Firewall state (opened or closed). Refer to Segment access depending on the Firewall state. Bit 0 FPA: Firewall prearm 0: any code executed outside the protected segment when the Firewall is opened will generate a system reset. 1: any code executed outside the protected segment will close the Firewall. Refer to Closing the Firewall. This register is protected in the same way as the Non-volatile data segment (refer to Section 4.3.5: Firewall initialization). 124/1600 RM0394 Rev 4 0x20 0x18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VDE VDS FPA Reset Value Res. FW_CR Res. Reset Value Res. 0x1C Res. Reset Value Res. 0 0 0 RM0394 Rev 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 0 Res. 0 0 Res. LENG 0 Res. ADD 0 Res. LENG 0 Res. ADD Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FW_CSSA Res. Res. Res. Res. Res. Res. Res. Res. Register Res. Res. Res. Res. Res. Res. Res. Res. ADD Res. Res. Res. Res. Res. Res. Res. Res. LENG 0 0 Res. 0 0 Res. Reset Value 0 0 Res. 0 0 Res. Reset Value 0 0 Res. 0 0 0 0 Res. 0 0 0 Res. 0 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 0 Res. 0 Res. 0 Res. 0 Res. 0 0 Res. Reset Value 0 Res. 0 Res. Reset Value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset Value Res. Res. Res. Res. Res. Res. Res. Res. Reset Value Res. Res. Res. Res. Res. Res. Res. FW_VDSL Res. FW_VDSSA Res. 0x14 FW_NVDSL Res. 0x10 FW_NVDSSA Res. 0xC FW_CSL Res. 0x8 Res. 0x4 Res. 0x0 Res. Offset Res. 4.4.8 Res. RM0394 Firewall (FW) Firewall register map The table below provides the Firewall register map and reset values. Table 18. Firewall register map and reset values Refer to Section 2.2.2 on page 67 for the register boundary addresses. 125/1600 125 Power control (PWR) RM0394 5 Power control (PWR) 5.1 Power supplies The STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx devices require a 1.71 V to 3.6 V operating supply voltage (VDD). Several peripherals are supplied through independent power domains: VDDA, VDDUSB, VLCD. Those supplies must not be provided without a valid operating supply on the VDD pin. • VDD = 1.71 V to 3.6 V VDD is the external power supply for the I/Os, the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins. • Note: VDD12 = 1.05 V to 1.32 V External power supply, connected to VCORE, bypassing internal regulator when connected to an external SMPS. It is provided externally through VDD12 pins and only available on packages with the external SMPS supply option. On STM32L412xx and STM32L422xx devices, VDD12 range is extended down to 1.00 V for better efficiency. • VDDA = 1.62 V (ADCs/COMPs) / 1.8 V (DACs/OPAMPs) / 2.4 V (VREFBUF) to 3.6 V VDDA is the external analog power supply for A/D converters, D/A converters, voltage reference buffer, operational amplifiers and comparators. The VDDA voltage level is independent from the VDD voltage. VDDA should be preferably connected to VDD when these peripherals are not used. • VDDUSB = 3.0 V to 3.6 V (available on STM32L4x2xx and STM32L4x3xx devices only) VDDUSB is the external independent power supply for USB transceivers. The VDDUSB voltage level is independent from the VDD voltage. VDDUSB should be preferably connected to VDD when the USB is not used. On small packages, VDDUSB power supply may not be present as a dedicated pin and is internally bonded to VDD. For such devices, VDD has to respect the VDDUSB supply range when USB is used. • VLCD = 2.5 V to 3.6 V (available on STM32L4x3xx devices only) The LCD controller can be powered either externally through VLCD pin, or internally from an internal voltage generated by the embedded step-up converter. VLCD is multiplexed with PC3 which can be used as GPIO when the LCD is not used. • VBAT = 1.55 V to 3.6 V VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. VBAT is internally bonded to VDD for small packages without dedicated pin. VBAT is internally bonded to VDD for small packages without dedicated pin. • VREF-, VREF+ VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage reference buffer when enabled. When VDDA < 2 V, VREF+ must be equal to VDDA. 126/1600 RM0394 Rev 4 RM0394 Power control (PWR) When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA. VREF+ can be grounded when ADC and DAC are not active. The internal voltage reference buffer supports two output voltages, which are configured with VRS bit in the VREFBUF_CSR register: – VREF+ around 2.048 V. This requires VDDA equal to or higher than 2.4 V. – VREF+ around 2.5 V. This requires VDDA equal to or higher than 2.8 V. VREF- and VREF+ pins are not available on all packages. When not available on the package, they are bonded to VSSA and VDDA, respectively. When the VREF+ is double-bonded with VDDA in a package, the internal voltage reference buffer is not available and must be kept disable (refer to related device datasheet for packages pinout description). Internal voltage reference buffer is not supported on STM32L41xxx and STM32L42xxx devices, regardless the presence of VREF+ pin. VREF- must always be equal to VSSA. An embedded linear voltage regulator is used to supply the internal digital power VCORE. VCORE is the power supply for digital peripherals and memories. RM0394 Rev 4 127/1600 174 Power control (PWR) RM0394 Figure 7. Power supply overview 9''$GRPDLQ 9''$ 966$ $'FRQYHUWHUV &RPSDUDWRUV '$FRQYHUWHUV 2SHUDWLRQDODPSOLILHUV 9ROWDJHUHIHUHQFHEXIIHU 9/&' 9''86% 966 /&' 86%WUDQVFHLYHUV 9''GRPDLQ 9'' 9'',2 ,2ULQJ 5HVHWEORFN 7HPSVHQVRU 3//+6,06,+6, 966 6WDQGE\FLUFXLWU\ :DNHXSORJLF,:'* 9ROWDJHUHJXODWRU 9&25( 9&25(GRPDLQ &RUH 0HPRULHV 'LJLWDOSHULSKHUDOV 9'' /RZYROWDJHGHWHFWRU %DFNXSGRPDLQ 9%$7 /6(FU\VWDO.RVF %.3UHJLVWHUV 5&&%'&5UHJLVWHU 57& 06Y9 1. Available on STM32L4x3xx devices only. 2. Available on STM32L4x2xx and STM32L4x3xx devices only. 5.1.1 Independent analog peripherals supply To improve ADC and DAC conversion accuracy and to extend the supply flexibility, the analog peripherals have an independent power supply which can be separately filtered and shielded from noise on the PCB. • The analog peripherals voltage supply input is available on a separate VDDA pin. • An isolated supply ground connection is provided on VSSA pin. The VDDA supply voltage can be different from VDD. The presence of VDDA must be checked before enabling any of the analog peripherals supplied by VDDA (A/D converter, D/A converter, comparators, operational amplifier, voltage reference buffer). The VDDA supply can be monitored by the Peripheral Voltage Monitoring, and compared with two thresholds (1.65 V for PVM3 or 1.8 V for PVM4), refer to Section 5.2.3: Peripheral Voltage Monitoring (PVM) for more details. 128/1600 RM0394 Rev 4 RM0394 Power control (PWR) When a single supply is used, VDDA can be externally connected to VDD through the external filtering circuit in order to ensure a noise-free VDDA reference voltage. ADC and DAC reference voltage To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to VREF+ a separate reference voltage lower than VDDA. VREF+ is the highest voltage, represented by the full scale value, for an analog input (ADC) or output (DAC) signal. VREF+ can be provided either by an external reference or by an internal buffered voltage reference (VREFBUF), except STM32L41xxx and STM32L42xxx devices, which does not support VREFBUF. The internal voltage reference is enabled by setting the ENVR bit in the Section 18.3.1: VREFBUF control and status register (VREFBUF_CSR). The voltage reference is set to 2.5 V when the VRS bit is set and to 2.048 V when the VRS bit is cleared. The internal voltage reference can also provide the voltage to external components through VREF+ pin. Refer to the device datasheet and to Section 18: Voltage reference buffer (VREFBUF) for further information. 5.1.2 Independent USB transceivers supply This section is applicable to STM32L4x2xx and STM32L4x3xx devices only. The USB transceivers are supplied from a separate VDDUSB power supply pin. VDDUSB range is from 3.0 V to 3.6 V and is completely independent from VDD or VDDA. On small packages, VDDUSB power supply may not be present as a dedicated pin, but internally bonded to VDD. For such devices, VDD has to respect the VDDUSB supply range when USB is used. After reset, the USB features supplied by VDDUSB are logically and electrically isolated and therefore are not available. The isolation must be removed before using the USB FS peripheral, by setting the USV bit in the PWR_CR2 register, once the VDDUSB supply is present. The VDDUSB supply is monitored by the Peripheral Voltage Monitoring (PVM1) and compared with the internal reference voltage (VREFINT, around 1.2 V), refer to Section 5.2.3: Peripheral Voltage Monitoring (PVM) for more details. 5.1.3 Independent LCD supply This section is applicable to STM32L4x3xx devices only. The VLCD pin is provided to control the contrast of the glass LCD. This pin can be used in two ways: • It can receive from an external circuitry the desired maximum voltage that is provided on segment and common lines to the glass LCD by the microcontroller. • It can also be used to connect an external capacitor that is used by the microcontroller for its voltage step-up converter. This step-up converter is controlled by software to provide the desired voltage to segment and common lines of the glass LCD. The voltage provided to segment and common lines defines the contrast of the glass LCD pixels. This contrast can be reduced when you configure the dead time between frames. • When an external power supply is provided to the VLCD pin, it should range from 2.5 V RM0394 Rev 4 129/1600 174 Power control (PWR) RM0394 to 3.6 V. It does not depend on VDD. • 5.1.4 When the LCD is based on the internal step-up converter, the VLCD pin should be connected to a capacitor (see the product datasheet for further information). Battery backup domain To retain the content of the Backup registers and supply the RTC function when VDD is turned off, the VBAT pin can be connected to an optional backup voltage supplied by a battery or by another source. VBAT pin is not available on low pin-count packages, VBAT is internally connected to VDD. The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 I/Os, allowing the RTC to operate even when the main power supply is turned off. The switch to the VBAT supply is controlled by the power-down reset embedded in the Reset block. Warning: During tRSTTEMPO (temporization at VDD startup) or after a PDR has been detected, the power switch between VBAT and VDD remains connected to VBAT. During the startup phase, if VDD is established in less than tRSTTEMPO (refer to the datasheet for the value of tRSTTEMPO) and VDD > VBAT + 0.6 V, a current may be injected into VBAT through an internal diode connected between VDD and the power switch (VBAT). If the power supply/battery connected to the VBAT pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the VBAT pin. If no external battery is used in the application, it is recommended to connect VBAT externally to VDD with a 100 nF external ceramic decoupling capacitor. When the backup domain is supplied by VDD (analog switch connected to VDD), the following pins are available: Note: • PC13, PC14 and PC15, which can be used as GPIO pins • PC13, PC14 and PC15, which can be configured by RTC or LSE (refer to Section 36.3: RTC functional description on page 1084) • PA0/RTC_TAMP2 and PE6/RTC_TAMP3 when they are configured by the RTC as tamper pins Due to the fact that the analog switch can transfer only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive a LED). When the backup domain is supplied by VBAT (analog switch connected to VBAT because VDD is not present), the following functions are available: 130/1600 • PC13, PC14 and PC15 can be controlled only by RTC or LSE (refer to Section 36.3: RTC functional description) • PA0/RTC_TAMP2 and PE6/RTC_TAMP3 when they are configured by the RTC as tamper pins RM0394 Rev 4 RM0394 Power control (PWR) Backup domain access After a system reset, the backup domain (RTC registers and backup registers) is protected against possible unwanted write accesses. To enable access to the backup domain, proceed as follows: 1. Enable the power interface clock by setting the PWREN bits in the Section 6.4.18: APB1 peripheral clock enable register 1 (RCC_APB1ENR1) 2. Set the DBP bit in the Power control register 1 (PWR_CR1) to enable access to the backup domain 3. Select the RTC clock source in the Backup domain control register (RCC_BDCR). 4. Enable the RTC clock by setting the RTCEN [15] bit in the Backup domain control register (RCC_BDCR). VBAT battery charging When VDD is present, It is possible to charge the external battery on VBAT through an internal resistance. The VBAT charging is done either through a 5 kOhm resistor or through a 1.5 kOhm resistor depending on the VBRS bit value in the PWR_CR4 register. The battery charging is enabled by setting VBE bit in the PWR_CR4 register. It is automatically disabled in VBAT mode. 5.1.5 Voltage regulator Two embedded linear voltage regulators supply all the digital circuitries, except for the Standby circuitry and the backup domain. The main regulator output voltage (VCORE) can be programmed by software to two different power ranges (Range 1 and Range 2) in order to optimize the consumption depending on the system’s maximum operating frequency (refer to Section 6.2.9: Clock source frequency versus voltage scaling and to Section 3.3.3: Read access latency. The voltage regulators are always enabled after a reset. Depending on the application modes, the VCORE supply is provided either by the main regulator (MR) or by the low-power regulator (LPR). • In Run, Sleep and Stop 0 modes, both regulators are enabled and the main regulator (MR) supplies full power to the VCORE domain (core, memories and digital peripherals). • In low-power run and low-power sleep modes, the main regulator is off and the lowpower regulator (LPR) supplies low power to the VCORE domain, preserving the contents of the registers, SRAM1 and SRAM2. • In Stop 1 and Stop 2 modes, the main regulator is off and the low-power regulator (LPR) supplies low power to the VCORE domain, preserving the contents of the registers, SRAM1 and SRAM2. • In Standby mode with SRAM2 content preserved (RRS bit is set in the PWR_CR3 register), the main regulator (MR) is off and the low-power regulator (LPR) provides the supply to SRAM2 only. The core, digital peripherals (except Standby circuitry and backup domain) and SRAM1 are powered off. • In Standby mode, both regulators are powered off. The contents of the registers, SRAM1 and SRAM2 is lost except for the Standby circuitry and the backup domain. • In Shutdown mode, both regulators are powered off. When exiting from Shutdown mode, a power-on reset is generated. Consequently, the contents of the registers, RM0394 Rev 4 131/1600 174 Power control (PWR) RM0394 SRAM1 and SRAM2 is lost, except for the backup domain. 5.1.6 VDD12 domain VDD12 is intended to be connected with external SMPS (Switched-mode Power Supply) to generate the VCORE logic supply in Run, Sleep and Stop 0 modes only. VDD12 pins correspond to the internal VCORE powering the digital part of Core, memories and peripherals. This improves significantly power consumption gain by 50% or more depending of the SMPS performances. The main benefit occurs in Run and Sleep modes whereas in Stop 0 mode, the gain is less significant. The Figure 8 shows a schematic to understand how the internal regulator stops supplying VCORE when an external voltage VDD12 is provided. As VDD12 shares the same pin as output of the internal regulator, applying a slightly higher voltage (typically +50 mV) on the VDD12 blocks the PMOS and the regulator consumption is negligible. Figure 8. Internal main regulator overview 9'' 9'' 9&25( 3026 6ZLWFK 96036 9ROWDJHUHJXODWRU 5HI 966 06Y9 A switch, controlled by chosen GPIO, is inserted between the SMPS output and VDD12. There are two possible states: • Connected: Switch is closed so SMPS powers VDD12 • Disconnected: Switch is open and VDD12 is disconnected from SMPS output Proper software management through GPIOs to enable/disable SMPS and connect/disconnect SMPS through the switch, is required to conform with the rules described below. (See also Section 5.1.7: Dynamic voltage scaling management) It is mandatory to respect the following rules to avoid any damage or instability on either digital parts or internal regulators: • In Run, Sleep and Stop 0 modes, VDD12 can be connected and should respect – VDD12 < 1.32 V – VDD12 ≥ VCORE + 50mV giving for Main Regulator Range 1, VCORE = 1.2 V so VDD12 should be greater than 1.25 V 132/1600 RM0394 Rev 4 RM0394 Power control (PWR) Range 2, VCORE = 1.0 V so VDD12 should be greater than 1.05 V – • In all other modes, ie LPRun, LPSleep, Stop 1, Stop 2, Standby and Shutdown modes, VDD12 must be disconnected from SMPS output, ie pin must be connected to an high impedance output: – • VDD12 ≥ 1.08 V in Range 2 when SYSCLK frequency ≥ 26 MHz VDD12 connected to HiZ (voltage is provided by internal regulators) Transitions of VDD12 from connected to disconnected is only allowed when SYSCLK frequency ≤ 26 MHz to avoid to big voltage drop on main regulator side. Note: In case of reset while having the VDD12 ≤ 1.25 V, VDD12 should switch to HiZ in less than regulator switching time from Range 2 to Range 1 (~1 us). Note: On STM32L412xx and STM32L422xx devices, VDD12 Range 2 is extended down to 1.00 V for better efficiency, thus following formula applies when bit EXT_SMPS_ON in the Power control register 4 (PWR_CR4) is set: Range 2, VCORE = 1.0 V so VDD12 should be greater than 1.00 V Note: For more details on VDD12 management, refer to AN4978 "Design recommendations for STM32L4xxxx with external SMPS, for ultra-low-power applications with high performance 5.1.7 Dynamic voltage scaling management The dynamic voltage scaling is a power management technique which consists in increasing or decreasing the voltage used for the digital peripherals (VCORE), according to the application performance and power consumption needs. Dynamic voltage scaling to increase VCORE is known as over-volting. It allows to improve the device performance. Dynamic voltage scaling to decrease VCORE is known as under-volting. It is performed to save power, particularly in laptop and other mobile devices where the energy comes from a battery and is thus limited. • Range 1: High-performance range. The main regulator provides a typical output voltage at 1.2 V. The system clock frequency can be up to 80 MHz. The Flash access time for read access is minimum, write and erase operations are possible. • Range 2: Low-power range. The main regulator provides a typical output voltage at 1.0 V. The system clock frequency can be up to 26 MHz.The Flash access time for a read access is increased as compared to Range 1; write and erase operations are possible. Voltage scaling is selected through the VOS bit in the PWR_CR1 register. The sequence to go from Range 1 to Range 2 is: 1.Reduce the system frequency to a value lower than 26 MHz 2. Adjust number of wait states according new frequency target in Range 2 (LATENCY bits in the FLASH_ACR). 3. Program the VOS bits to “10” in the PWR_CR1 register. The sequence to go from Range 2 to Range 1 is: RM0394 Rev 4 133/1600 174 Power control (PWR) RM0394 1. Program the VOS bits to “01” in the PWR_CR1 register. 2. Wait until the VOSF flag is cleared in the PWR_SR2 register. 3. Adjust number of wait states according new frequency target in Range 1 (LATENCY bits in the FLASH_ACR). 4. Increase the system frequency. When supplying VDD12 with an external SMPS, we are defining 3 new states: • “SMPS range 1”: main regulator is in Range 1 and VCORE is supplied by external SMPS with VDD12 higher than 1.25 V • “SMPS range 2 High”: main regulator is in Range 2 and VCORE is supplied by external SMPS with VDD12 higher than 1.08 V • “SMPS range 2 Low”: main regulator is in Range 2 and VCORE is supplied by external SMPS with VDD12 higher than 1.05 V(a) In order to match the upper rules described in Section 5.1.6: VDD12 domain, the transition sequences can only be one of the following: • Range 1 to “SMPS Range 1”: 1. Start SMPS converter (if not always enabled by HW). 2. Check that SMPS converter output is at the correct level i.e. 1.25 V ≤ VDD12 < 1.32 V. 3. Connect VDD12 to external SMPS converter through the switch. • Range 2 to “SMPS Range 2 Low & High”: 1. Start SMPS (if not always enabled by HW). 2. Check that SMPS output is at the correct level ie 1.05 V(a) ≤ VDD12 < 1.32 V. 3. Connect VDD12 to external SMPS converter through the switch. If 1.08 V ≤ VDD12 (ie SMPS Range 2 High), then the following steps can be applied: 4. Adjust the number of wait states in the FLASH_ACR (up to max frequency of Range 1 refer to Section 3.3.3: Read access latency). 5. Increase the system frequency up to the maximum allowed value for Voltage Range 1 (ie 80 MHz). • “SMPS Range 1” to Range 1: or • SMPS Range 2 Low & High” to Range 2: 1. If in Range 1, reduce the system frequency to a value lower or equal to 26 MHz. 2. Adjust number of wait states according new frequency target corresponding to Voltage Range (LATENCY bits in the FLASH_ACR). 3. Disconnect VDD12 by opening the switch. 4. Stop SMPS (if required and not kept always enabled). If in Range 1, then the following step can be applied: 5. Increase the system frequency if needed. a. On STM32L412xx and STM32L422xx devices, minimum limit of 1.00 V applies when bit EXT_SMPS_ON in the Power control register 4 (PWR_CR4) is set. 134/1600 RM0394 Rev 4 RM0394 Power control (PWR) 5.2 Power supply supervisor 5.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) The device has an integrated power-on reset (POR) / power-down reset (PDR), coupled with a brown-out reset (BOR) circuitry. The BOR is active in all power modes except Shutdown mode, and cannot be disabled. Five BOR thresholds can be selected through option bytes. During power-on, the BOR keeps the device under reset until the supply voltage VDD reaches the specified VBORx threshold. When VDD drops below the selected threshold, a device reset is generated. When VDD is above the VBORx upper limit, the device reset is released and the system can start. For more details on the brown-out reset thresholds, refer to the electrical characteristics section in the datasheet. On STM32L412xx and STM32L422xx devices, continuous monitoring of the power supply might be changed to periodical sampling to reduce power consumption in Stop2, Standby and Shutdown modes by setting ENULP bit in Power control register 3 (PWR_CR3). When sampling mode will be selected, fast supply drop between two samples will not be detected. Figure 9. Brown-out reset waveform 9'' 9%25 ULVLQJHGJH K\VWHUHVLV 9%25 IDOOLQJHGJH 7HPSRUL]DWLRQ W5677(032 5HVHW 069 1. The reset temporization tRSTTEMPO is present only for the BOR lowest threshold (VBOR0). 5.2.2 Programmable voltage detector (PVD) You can use the PVD to monitor the VDD power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register 2 (PWR_CR2). The PVD is enabled by setting the PVDE bit. A PVDO flag is available, in the Power status register 2 (PWR_SR2), to indicate if VDD is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The rising/falling edge sensitivity of the EXTI Line16 should be configured according to PVD output behavior i.e. if the EXTI line 16 is configured to rising edge sensitivity, the interrupt will be generated when VDD drops below the PVD threshold. As an example the service routine could perform emergency shutdown tasks. RM0394 Rev 4 135/1600 174 Power control (PWR) RM0394 Figure 10. PVD thresholds 9 '' 9WKUHVKROG 39' P9 K\VWHUHVLV 39'RXWSXW 069 5.2.3 Peripheral Voltage Monitoring (PVM) Only VDD is monitored by default, as it is the only supply required for all system-related functions. The other supplies (VDDA and VDDUSB) can be independent from VDD and can be monitored with four Peripheral Voltage Monitoring (PVM). Each of the three PVMx (x=1, 3, 4) is a comparator between a fixed threshold VPVMx and the selected power supply. PVMOx flags indicate if the independent power supply is higher or lower than the PVMx threshold: PVMOx flag is cleared when the supply voltage is above the PVMx threshold, and is set when the supply voltage is below the PVMx threshold. Each PVM output is connected to an EXTI line and can generate an interrupt if enabled through the EXTI registers. The PVMx output interrupt is generated when the independent power supply drops below the PVMx threshold and/or when it rises above the PVMx threshold, depending on EXTI line rising/falling edge configuration. Each PVM can remain active in Stop 0, Stop 1 and Stop 2 modes, and the PVM interrupt can wake up from the Stop mode. Table 19. PVM features PVM Power supply PVM threshold EXTI line PVM1(1) VDDUSB VPVM1 (around 1.2 V) 35 PVM3 VDDA VPVM3 (around 1.65 V) 37 PVM4 VDDA VPVM4 (around 1.8 V) 38 1. Available on STM32L4x2xx and STM32L4x3xx devices only. The independent supplies (VDDA and VDDUSB) are not considered as present by default, and a logical and electrical isolation is applied to ignore any information coming from the peripherals supplied by these dedicated supplies. 136/1600 • If these supplies are shorted externally to VDD, the application should assume they are available without enabling any Peripheral Voltage Monitoring. • If these supplies are independent from VDD, the Peripheral Voltage Monitoring (PVM) RM0394 Rev 4 RM0394 Power control (PWR) can be enabled to confirm whether the supply is present or not. The following sequence must be done before using the USB FS peripheral on STM32L4x2xx and STM32L4x3xx devices: 1. 2. If VDDUSB is independent from VDD: a) Enable the PVM1 by setting PVME1 bit in the Power control register 2 (PWR_CR2). b) Wait for the PVM1 wakeup time c) Wait until PVMO1 bit is cleared in the Power status register 2 (PWR_SR2). d) Optional: Disable the PVM1 for consumption saving. Set the USV bit in the Power control register 2 (PWR_CR2) to remove the VDDUSB power isolation. The following sequence must be done before using any of these analog peripherals: analog to digital converters, digital to analog converters, comparators, operational amplifiers, voltage reference buffer: 1. 2. 5.3 If VDDA is independent from VDD: a) Enable the PVM3 (or PVM4) by setting PVME3 (or PVME4) bit in the Power control register 2 (PWR_CR2). b) Wait for the PVM3 (or PVM4) wakeup time c) Wait until PVMO3 (or PVMO4) bit is cleared in the Power status register 2 (PWR_SR2). d) Optional: Disable the PVM3 (or PVM4) for consumption saving. Enable the analog peripheral, which automatically removes the VDDA isolation. Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. Several lowpower modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources. The device features seven low-power modes: • Sleep mode: CPU clock off, all peripherals including Cortex®-M4 core peripherals such as NVIC, SysTick, etc. can run and wake up the CPU when an interrupt or an event occurs. Refer to Section 5.3.4: Sleep mode. • Low-power run mode: This mode is achieved when the system clock frequency is reduced below 2 MHz. The code is executed from the SRAM or the Flash memory. The regulator is in low-power mode to minimize the regulator's operating current. Refer to Section 5.3.2: Low-power run mode (LP run). • Low-power sleep mode: This mode is entered from the Low-power run mode: Cortex®M4 is off. Refer to Section 5.3.5: Low-power sleep mode (LP sleep). • Stop 0, Stop 1 and Stop 2 modes: SRAM1, SRAM2 and all registers content are retained. All clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16 and the HSE are disabled. The LSI and the LSE can be kept running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with the wakeup capability can enable the HSI16 RC during the Stop RM0394 Rev 4 137/1600 174 Power control (PWR) RM0394 mode to detect their wakeup condition. In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode. Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, which allows the fastest wakeup time but with much higher consumption. The active peripherals and wakeup sources are the same as in Stop 1 mode. The system clock, when exiting from Stop 0, Stop 1 or Stop 2 mode, can be either MSI up to 48 MHz or HSI16, depending on the software configuration. Refer to Section 5.3.6: Stop 0 mode and Section 5.3.8: Stop 2 mode. • Standby mode: VCORE domain is powered off. However, it is possible to preserve the SRAM2 contents: – Standby mode with SRAM2 retention when the bit RRS is set in PWR_CR3 register. In this case, SRAM2 is supplied by the low-power regulator. – Standby mode when the bit RRS is cleared in PWR_CR3 register. In this case the main regulator and the low-power regulator are powered off. All clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16 and the HSE are disabled. The LSI and the LSE can be kept running. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The system clock, when exiting Standby modes, is MSI from 1 MHz up to 8 MHz. Refer to Section 5.3.9: Standby mode. • Shutdown mode: VCORE domain is powered off. All clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16, the LSI and the HSE are disabled. The LSE can be kept running. The system clock, when exiting the Shutdown mode, is MSI at 4 MHz. In this mode, the supply voltage monitoring is disabled and the product behavior is not guaranteed in case of a power voltage drop. Refer to Section 5.3.10: Shutdown mode. In addition, the power consumption in Run mode can be reduced by one of the following means: 138/1600 • Slowing down the system clocks • Gating the clocks to the APB and AHB peripherals when they are unused. RM0394 Rev 4 RM0394 Power control (PWR) Figure 11. Low-power modes possible transitions /RZSRZHUVOHHSPRGH 6OHHSPRGH /RZSRZHUUXQPRGH 6KXWGRZQPRGH 6WRSPRGH 5XQPRGH 6WDQGE\PRGH 6WRSPRGH 6WRSPRGH 069 RM0394 Rev 4 139/1600 174 Power control (PWR) RM0394 Table 20. Low-power mode summary Mode name Entry WFI or Return Sleep (Sleep-now or from ISR Sleep-on-exit) WFE Low-power run Low-power sleep Stop 0 Stop 1 Stop 2 Wakeup Wakeup source(1) system clock Any interrupt Wakeup event Set LPR bit Clear LPR bit Set LPR bit + WFI or Return from ISR Any interrupt Set LPR bit + WFE Wakeup event LPR Same as before entering Sleep mode CPU clock OFF no effect on other clocks ON or analog clock sources ON Same as Lowpower run clock None OFF ON Same as before entering Lowpower sleep mode OFF CPU clock OFF no effect on other clocks or analog clock sources OFF ON ON ON HSI16 when Any EXTI line STOPWUCK=1 in (configured in the RCC_CFGR LPMS=”001” + SLEEPDEEP bit EXTI registers) MSI with the + WFI or Return Specific frequency before from ISR or WFE peripherals entering the Stop events mode when LPMS=”010” + STOPWUCK=0. SLEEPDEEP bit + WFI or Return All clocks OFF except LSI and LSE from ISR or WFE WKUP pin edge, RTC event, external reset in NRST pin, IWDG reset Standby LPMS=”011” + Clear RRS bit + SLEEPDEEP bit + WFI or Return from ISR or WFE WKUP pin edge, RTC event, external reset in NRST pin, IWDG reset Shutdown LPMS=”1--” + SLEEPDEEP bit + WFI or Return from ISR or WFE WKUP pin edge, RTC event, external reset in NRST pin ON OFF MSI from 1 MHz up to 8 MHz MSI 4 MHz 1. Refer to Table 21: Functionalities depending on the working mode. 140/1600 MR LPMS=”000” + SLEEPDEEP bit + WFI or Return from ISR or WFE LPMS=”011”+ Set RRS bit + SLEEPDEEP bit + WFI or Return from ISR or WFE Standby with SRAM2 Effect on clocks Voltage regulators RM0394 Rev 4 All clocks OFF except LSE OFF OFF OFF OFF RM0394 Power control (PWR) Table 21. Functionalities depending on the working mode(1) - Wakeup capability - Wakeup capability - CPU Y - Y - - - - - - - - - - Flash memory (2) O (2) (2) O (2) - - - - - - - - - Y Y(3) Y Y(3) Y - Y - - - - - - SRAM2 Y (3) Y (3) Y - Y - (4) O - - - - QUADSPI O O O O - - - - - - - - - Backup Registers Y Y Y Y Y - Y - Y - Y - Y Brown-out reset (BOR) Y Y Y Y Y Y Y Y Y Y - - - Programmable Voltage Detector (PVD) O O O O O O O O - - - - - Peripheral Voltage Monitor (PVMx; x=1,3,4) O O O O O O O O - - - - - DMA O O O O - - - - - - - - - - (5) - - - - - - Peripheral SRAM1 Run O Sleep Y O Y - Wakeup capability Wakeup capability Standby Shutdown Low-power sleep Stop 2 Low-power run Stop 0/1 VBAT Oscillator HSI16 O O O O (5) Oscillator HSI48 O O - - - - - - - - - - - High Speed External (HSE) O O O O - - - - - - - - - Low Speed Internal (LSI) O O O O O - O - O - - - - Low Speed External (LSE) O O O O O - O - O - O - O Multi-Speed Internal (MSI) O O O O - - - - - - - - - Clock Security System (CSS) O O O O - - - - - - - - - Clock Security System on LSE O O O O O O O O O O - - - RTC / Auto wakeup O O O O O O O O O O O O O Number of RTC Tamper pins 3 3 3 3 3 O 3 O 3 O 3 O 3 LCD(6) O O O O O O O O - - - - - O(15) O(15) - - - O - - - - - - - O O O O (10) - - - - - - - USB FS (7) USARTx (x=1,2,3(8),4(9)) O RM0394 Rev 4 O (10) 141/1600 174 Power control (PWR) RM0394 Table 21. Functionalities depending on the working mode(1) (continued) O O (10) I2Cx (x=1,2,4(9)) O O O O (11) I2C3 O O O O (11) (11) (11) SPIx (x=1,2(8),3) O O O O - - CAN O O O O - SDMMC1(8)(12) O O O O SWPMI1 O O O SAIx (x=1)(12) O O DFSDM1(9) O 0) (10) - - - - - - - - - - - - (11) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - O - O - - - - - - - O O - - - - - - - - - O O O - - - - - - - - - O O O O - - - - - - - - - DACx (x=1 O O O O O - - - - - - - - VREFBUF(19) O O O O O - - - - - - - - O O O O O - - - - - - - - COMPx (x=1,2 O O O O O O O O - - - - - Temperature sensor O O O O - - - - - - - - - Timers (TIMx) O O O O - - - - - - - - - Low-power timer 1 (LPTIM1) O O O O O O O O - - - - - Low-power timer 2 (LPTIM2) O O O O O O (14) O - - - - - Independent watchdog (IWDG) O O O O O O O O O O - - - Window watchdog (WWDG) O O O O - - - - - - - - - SysTick timer O O O O - - - - - - - - - Touch sensing controller (TSC) O O O O - - - - - - - - - O(15) O(15) - - - - - - - - - - - (12) (14)) ADCx (x=1,2 (12),2(13)) OPAMPx (x=1) (19)) Random number generator (RNG) 142/1600 - O O O RM0394 Rev 4 O O(1 (10) O (11) O O O O O - Wakeup capability O Wakeup capability O Sleep Wakeup capability Low-power UART (LPUART1) Run - Standby Shutdown - Peripheral Wakeup capability Low-power sleep Stop 2 Low-power run Stop 0/1 VBAT RM0394 Power control (PWR) Table 21. Functionalities depending on the working mode(1) (continued) - Wakeup capability - Wakeup capability - AES hardware accelerator(16) O O O O - - - - - - - - - CRC calculation unit O O O O - - - - - - - - - O (17) up to 5 pins (19) up to 5 pins Peripheral GPIOs Run Sleep O O O O - O O O (18) Wakeup capability Wakeup capability Standby Shutdown Low-power sleep Stop 2 Low-power run Stop 0/1 VBAT - (18) 1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available. 2. The Flash can be configured in power-down mode. By default, it is not in power-down mode. 3. The SRAM clock can be gated on or off. 4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register. 5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore. 6. Available on STM32L4x3xx devices only. 7. Available on STM32L4x2xx and STM32L4x3xx devices only. 8. Not available on STM32L432xx and STM32L442xx devices. 9. Available on STM32L45xxx and STM32L46xxx devices only. 10. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 11. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 12. Not available on STM32L41xxx and STM32L42xxx devices. 13. Available on STM32L43xxx/44xxx devices only. 14. Available on STM32L41xxx and STM32L42xxx devices only. 15. Voltage scaling Range 1, SMPS Range 1 or SMPS Range 2 High only. 16. Available on STM32L42xxx, STM32L44xxx and STM32L46xxx devices only. 17. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode. 18. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 19. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. Debug mode By default, the debug connection is lost if the application puts the MCU in Stop 0, Stop1, Stop 2, Standby or Shutdown mode while the debug features are used. This is due to the fact that the Cortex®-M4 core is no longer clocked. However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to Section 46.16.1: Debug support for low-power modes. RM0394 Rev 4 143/1600 174 Power control (PWR) 5.3.1 RM0394 Run mode Slowing down system clocks In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down the peripherals before entering the Sleep mode. For more details, refer to Section 6.4.3: Clock configuration register (RCC_CFGR). Peripheral clock gating In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped at any time to reduce the power consumption. To further reduce the power consumption in Sleep mode, the peripheral clocks can be disabled prior to executing the WFI or WFE instructions. The peripheral clock gating is controlled by the RCC_AHBxENR and RCC_APBxENR registers. Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in the RCC_AHBxSMENR and RCC_APBxSMENR registers. 5.3.2 Low-power run mode (LP run) To further reduce the consumption when the system is in Run mode, the regulator can be configured in low-power mode. In this mode, the system frequency should not exceed 2 MHz. Please refer to the product datasheet for more details on voltage regulator and peripherals operating conditions. I/O states in Low-power run mode In Low-power run mode, all I/O pins keep the same state as in Run mode. Entering the Low-power run mode To enter the Low-power run mode, proceed as follows: 1. Optional: Jump into the SRAM and power-down the Flash by setting the RUN_PD bit in the Flash access control register (FLASH_ACR). 2. Decrease the system clock frequency below 2 MHz. 3. Force the regulator in low-power mode by setting the LPR bit in the PWR_CR1 register. Refer to Table 22: Low-power run on how to enter the Low-power run mode. Exiting the Low-power run mode To exit the Low-power run mode, proceed as follows: 1. Force the regulator in main mode by clearing the LPR bit in the PWR_CR1 register. 2. Wait until REGLPF bit is cleared in the PWR_SR2 register. 3. Increase the system clock frequency. Refer to Table 22: Low-power run on how to exit the Low-power run mode. 144/1600 RM0394 Rev 4 RM0394 Power control (PWR) Table 22. Low-power run Low-power run mode 5.3.3 Description Mode entry Decrease the system clock frequency below 2 MHz LPR = 1 Mode exit LPR = 0 Wait until REGLPF = 0 Increase the system clock frequency Wakeup latency Regulator wakeup time from low-power mode Low power modes Entering low power mode Low power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M4 System Control register is set on Return from ISR. Entering Low-power mode through WFI or WFE will be executed only if no interrupt is pending or no event is pending. Exiting low power mode From Sleep modes, and Stop modes the MCU exit low power mode depending on the way the low power mode was entered: • If the WFI instruction or Return from ISR was used to enter the low power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device. • If the WFE instruction is used to enter the low power mode, the MCU exits the low power mode as soon as an event occurs. The wakeup event can be generated either by: – NVIC IRQ interrupt. - When SEVONPEND = 0 in the Cortex®-M4 System Control register. By enabling an interrupt in the peripheral control register and in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU. - When SEVONPEND = 1 in the Cortex®-M4 System Control register. By enabling an interrupt in the peripheral control register and optionally in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and RM0394 Rev 4 145/1600 174 Power control (PWR) RM0394 when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. All NVIC interrupts will wakeup the MCU, even the disabled ones. Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU. – Event Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set. It may be necessary to clear the interrupt flag in the peripheral. From Standby modes, and Shutdown modes the MCU exit low power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs (see Figure 351: RTC block diagrams). After waking up from Standby or Shutdown mode, program execution restarts in the same way as after a Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.). 5.3.4 Sleep mode I/O states in Sleep mode In Sleep mode, all I/O pins keep the same state as in Run mode. Entering the Sleep mode The Sleep mode is entered according Section : Entering low power mode, when the SLEEPDEEP bit in the Cortex®-M4 System Control register is clear. Refer to Table 23: Sleep for details on how to enter the Sleep mode. Exiting the Sleep mode The Sleep mode is exit according Section : Exiting low power mode. Refer to Table 23: Sleep for more details on how to exit the Sleep mode. Table 23. Sleep Sleep-now mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 – No interrupt (for WFI) or event (for WFE) is pending Refer to the Cortex®-M4 System Control register. Mode entry 146/1600 On return from ISR while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 1 – No interrupt is pending Refer to the Cortex®-M4 System Control register. RM0394 Rev 4 RM0394 Power control (PWR) Table 23. Sleep (continued) Sleep-now mode Description If WFI or return from ISR was used for entry Interrupt: refer to Table 46: STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table Mode exit If WFE was used for entry and SEVONPEND = 0: Wakeup event: refer to Section 13.3.2: Wakeup event management If WFE was used for entry and SEVONPEND = 1: Interrupt even when disabled in NVIC: refer to Table 46: STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table or Wakeup event: refer to Section 13.3.2: Wakeup event management Wakeup latency 5.3.5 None Low-power sleep mode (LP sleep) Please refer to the product datasheet for more details on voltage regulator and peripherals operating conditions. I/O states in Low-power sleep mode In Low-power sleep mode, all I/O pins keep the same state as in Run mode. Entering the Low-power sleep mode The Low-power sleep mode is entered from low-power run mode according Section : Entering low power mode, when the SLEEPDEEP bit in the Cortex®-M4 System Control register is clear. Refer to Table 24: Low-power sleep for details on how to enter the Low-power sleep mode. Exiting the Low-power sleep mode The low-power Sleep mode is exit according Section : Exiting low power mode. When exiting the Low-power sleep mode by issuing an interrupt or an event, the MCU is in Lowpower run mode. Refer to Table 24: Low-power sleep for details on how to exit the Low-power sleep mode. RM0394 Rev 4 147/1600 174 Power control (PWR) RM0394 Table 24. Low-power sleep Low-power sleep-now mode Description Low-power sleep mode is entered from the Low-power run mode. WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 – No interrupt (for WFI) or event (for WFE) is pending Refer to the Cortex®-M4 System Control register. Mode entry Low-power sleep mode is entered from the Low-power run mode. On return from ISR while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 1 – No interrupt is pending Refer to the Cortex®-M4 System Control register. If WFI or Return from ISR was used for entry Interrupt: refer to Table 46: STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table If WFE was used for entry and SEVONPEND = 0: Wakeup event: refer to Section 13.3.2: Wakeup event management 5.3.6 Mode exit If WFE was used for entry and SEVONPEND = 1: Interrupt even when disabled in NVIC: refer to Table 46: STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table Wakeup event: refer to Section 13.3.2: Wakeup event management After exiting the Low-power sleep mode, the MCU is in Low-power run mode. Wakeup latency None Stop 0 mode The Stop 0 mode is based on the Cortex®-M4 deepsleep mode combined with the peripheral clock gating. The voltage regulator is configured in main regulator mode. In Stop 0 mode, all clocks in the VCORE domain are stopped; the PLL, the MSI, the HSI16 and the HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx (x=1,2,3), U(S)ARTx(x=1,2,3) and LPUART) can switch on the HSI16 to receive a frame, and switch off the HSI16 after receiving the frame if it is not a wakeup frame. In this case, the HSI16 clock is propagated only to the peripheral requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is always available in Stop 0 mode. The consumption is increased when thresholds higher than VBOR0 are used. I/O states in Stop 0 mode In the Stop 0 mode, all I/O pins keep the same state as in the Run mode. Entering the Stop 0 mode The Stop 0 mode is entered according Section : Entering low power mode, when the SLEEPDEEP bit in the Cortex®-M4 System Control register is set. 148/1600 RM0394 Rev 4 RM0394 Power control (PWR) Refer to Table 25: Stop 0 mode for details on how to enter the Stop 0 mode. If Flash memory programming is ongoing, the Stop 0 mode entry is delayed until the memory access is finished. If an access to the APB domain is ongoing, The Stop 0 mode entry is delayed until the APB access is finished. In Stop 0 mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started, it cannot be stopped except by a Reset. See Section 32.3: IWDG functional description. • real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) • Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status register (RCC_CSR). • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR). Several peripherals can be used in Stop 0 mode and can add consumption if they are enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LCD, LPTIM1, LPTIM2, I2Cx (x=1,2,3,4) U(S)ARTx(x=1,2,3,4), LPUART. The DACx (x=1,2), the OPAMP and the comparators can be used in Stop 0 mode, the PVMx (x=1,3,4) and the PVD as well. If they are not needed, they must be disabled by software to save their power consumptions. The ADCx (x=1), temperature sensor and VREFBUF buffer can consume power during the Stop 0 mode, unless they are disabled before entering this mode. Exiting the Stop 0 mode The Stop 0 mode is exit according Section : Entering low power mode. Refer to Table 25: Stop 0 mode for details on how to exit Stop 0 mode. When exiting Stop 0 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is selected as system clock if the bit STOPWUCK is set in Clock configuration register (RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The MSI selection allows wakeup at higher frequency, up to 48 MHz. When exiting the Stop 0 mode, the MCU is either in Run mode Range 1 or Run Mode Range 2 depending on VOS bit in PWR_CR1. RM0394 Rev 4 149/1600 174 Power control (PWR) RM0394 Table 25. Stop 0 mode Stop 0 mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register – No interrupt (for WFI) or event (for WFE) is pending – LPMS = “000” in PWR_CR1 Mode entry On Return from ISR while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register – SLEEPONEXIT = 1 – No interrupt is pending – LPMS = “000” in PWR_CR1 Note: To enter Stop 0 mode, all EXTI Line pending bits (in Pending register 1 (EXTI_PR1)), and the peripheral flags generating wakeup interrupts must be cleared. Otherwise, the Stop 0 mode entry procedure is ignored and program execution continues. Mode exit If WFI or Return from ISR was used for entry Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 46: STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table. If WFE was used for entry and SEVONPEND = 0: Any EXTI Line configured in event mode. Refer to Section 13.3.2: Wakeup event management. If WFE was used for entry and SEVONPEND = 1: Any EXTI Line configured in Interrupt mode (even if the corresponding EXTI Interrupt vector is disabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer toTable 46: STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table. Wakeup event: refer to Section 13.3.2: Wakeup event management Wakeup latency 5.3.7 Longest wakeup time between: MSI or HSI16 wakeup time and Flash wakeup time from Stop 0 mode. Stop 1 mode The Stop 1 mode is the same as Stop 0 mode except that the main regulator is OFF, and only the low-power regulator is ON. Stop 1 mode can be entered from Run mode and from Low-power run mode. Refer to Table 26: Stop 1 mode for details on how to enter and exit Stop 1 mode. 150/1600 RM0394 Rev 4 RM0394 Power control (PWR) Table 26. Stop 1 mode Stop 1 mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register – No interrupt (for WFI) or event (for WFE) is pending – LPMS = “001” in PWR_CR1 Mode entry On Return from ISR while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register – SLEEPONEXIT = 1 – No interrupt is pending – LPMS = “001” in PWR_CR1 Note: To enter Stop 1 mode, all EXTI Line pending bits (in Pending register 1 (EXTI_PR1)), and the peripheral flags generating wakeup interrupts must be cleared. Otherwise, the Stop 1 mode entry procedure is ignored and program execution continues. Mode exit If WFI or Return from ISR was used for entry Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 46: STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table. If WFE was used for entry and SEVONPEND = 0: Any EXTI Line configured in event mode. Refer to Section 13.3.2: Wakeup event management. If WFE was used for entry and SEVONPEND = 1: Any EXTI Line configured in Interrupt mode (even if the corresponding EXTI Interrupt vector is disabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer toTable 46: STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table. Wakeup event: refer to Section 13.3.2: Wakeup event management Wakeup latency 5.3.8 Longest wakeup time between: MSI or HSI16 wakeup time and regulator wakeup time from Low-power mode + Flash wakeup time from Stop 1 mode. Stop 2 mode The Stop 2 mode is based on the Cortex®-M4 deepsleep mode combined with peripheral clock gating. In Stop 2 mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16 and the HSE oscillators are disabled. Some peripherals with wakeup capability (I2C3 and LPUART) can switch on the HSI16 to receive a frame, and switch off the HSI16 after receiving the frame if it is not a wakeup frame. In this case the HSI16 clock is propagated only to the peripheral requesting it. SRAM1, SRAM2 and register contents are preserved. The BOR is always available in Stop 2 mode. The consumption is increased when thresholds higher than VBOR0 are used. Note: The comparators outputs, the LPUART outputs and the LPTIM1 outputs are forced to low speed (OSPEEDy=00) during the Stop 2 mode. RM0394 Rev 4 151/1600 174 Power control (PWR) RM0394 I/O states in Stop 2 mode In the Stop 2 mode, all I/O pins keep the same state as in the Run mode. Entering Stop 2 mode The Stop 2 mode is entered according Section : Entering low power mode, when the SLEEPDEEP bit in the Cortex®-M4 System Control register is set. Refer to Table 27: Stop 2 mode for details on how to enter the Stop 2 mode. Stop 2 mode can only be entered from Run mode. It is not possible to enter Stop 2 mode from the Low-power run mode. If Flash memory programming is ongoing, the Stop 2 mode entry is delayed until the memory access is finished. If an access to the APB domain is ongoing, The Stop 2 mode entry is delayed until the APB access is finished. In Stop 2 mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See Section 32.3: IWDG functional description in Section 32: Independent watchdog (IWDG). • Real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) • Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status register (RCC_CSR). • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR). Several peripherals can be used in Stop 2 mode and can add consumption if they are enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LCD, LPTIM1, I2C3, LPUART. The comparators can be used in Stop 2 mode, the PVMx (x=1,3,4) and the PVD as well. If they are not needed, they must be disabled by software to save their power consumptions. The ADCx, OPAMPx, DACx, temperature sensor and VREFBUF buffer can consume power during Stop 2 mode, unless they are disabled before entering this mode. All the peripherals which cannot be enabled in Stop 2 mode must be either disabled by clearing the Enable bit in the peripheral itself, or put under reset state by setting the corresponding bit in the AHB1 peripheral reset register (RCC_AHB1RSTR), AHB2 peripheral reset register (RCC_AHB2RSTR), AHB3 peripheral reset register (RCC_AHB3RSTR), APB1 peripheral reset register 1 (RCC_APB1RSTR1), APB1 peripheral reset register 2 (RCC_APB1RSTR2), APB2 peripheral reset register (RCC_APB2RSTR). Exiting Stop 2 mode The Stop 2 mode is exit according Section : Exiting low power mode. Refer to Table 27: Stop 2 mode for details on how to exit Stop 2 mode. 152/1600 RM0394 Rev 4 RM0394 Power control (PWR) When exiting Stop 2 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is selected as system clock if the bit STOPWUCK is set in Clock configuration register (RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The MSI selection allows wakeup at higher frequency, up to 48 MHz. When exiting the Stop 2 mode, the MCU is in Run mode (Range 1 or Range 2 depending on VOS bit in PWR_CR1). Table 27. Stop 2 mode Stop 2 mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register – No interrupt (for WFI) or event (for WFE) is pending – LPMS = “010” in PWR_CR1 Mode entry On return from ISR while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register – SLEEPONEXIT = 1 – No interrupt is pending – LPMS = “010” in PWR_CR1 Note: To enter Stop 2 mode, all EXTI Line pending bits (in Pending register 1 (EXTI_PR1)), and the peripheral flags generating wakeup interrupts must be cleared. Otherwise, the Stop mode entry procedure is ignored and program execution continues. Mode exit If WFI or Return from ISR was used for entry: Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 46: STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table. If WFE was used for entry and SEVONPEND = 0: Any EXTI Line configured in event mode. Refer to Section 13.3.2: Wakeup event management. If WFE was used for entry and SEVONPEND = 1: Any EXTI Line configured in Interrupt mode (even if the corresponding EXTI Interrupt vector is disabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 46: STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table. Any EXTI Line configured in event mode. Refer to Section 13.3.2: Wakeup event management. Wakeup latency 5.3.9 Longest wakeup time between: MSI or HSI16 wakeup time and regulator wakeup time from Low-power mode + Flash wakeup time from Stop 2 mode. Standby mode The Standby mode allows to achieve the lowest power consumption with BOR. It is based on the Cortex®-M4 deepsleep mode, with the voltage regulators disabled (except when SRAM2 content is preserved). The PLL, the HSI16, the MSI and the HSE oscillators are also switched off. RM0394 Rev 4 153/1600 174 Power control (PWR) RM0394 SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry (see Figure 7). SRAM2 content can be preserved if the bit RRS is set in the PWR_CR3 register. In this case the Low-power regulator is ON and provides the supply to SRAM2 only. The BOR is always available in Standby mode. The consumption is increased when thresholds higher than VBOR0 are used. I/O states in Standby mode In the Standby mode, the IO’s are by default in floating state. If the APC bit of PWR_CR3 register has been set, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx registers (x=A,B,C,D,E,F,G,H)), or with a pull-down (refer to PWR_PDCRx registers (x=A,B,C,D,E,F,G,H)), or can be kept in analog state if none of the PWR_PUCRx or PWR_PDCRx register has been set. The pull-down configuration has highest priority over pull-up configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same IO. Some I/Os (listed in Section 8.3.1: General-purpose I/O (GPIO)) are used for JTAG/SW debug and can only be configured to their respective reset pull-up or pull-down state during Standby mode setting their respective bit in the PWR_PUCRx or PWR_PDCRx registers to ‘1’, or will be configured to floating state if the bit is kept at ‘0’. The RTC outputs on PC13 are functional in Standby mode. PC14 and PC15 used for LSE are also functional. 5 wakeup pins (WKUPx, x=1,2...5) and the 3 RTC tampers are available. Entering Standby mode The Standby mode is entered according Section : Entering low power mode, when the SLEEPDEEP bit in the Cortex®-M4 System Control register is set. Refer to Table 28: Standby mode for details on how to enter Standby mode. In Standby mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See Section 32.3: IWDG functional description in Section 32: Independent watchdog (IWDG). • real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) • Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status register (RCC_CSR). • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR) Exiting Standby mode The Standby mode is exited according Section : Entering low power mode. The SBF status flag in the Power control register 3 (PWR_CR3) indicates that the MCU was in Standby mode. All registers are reset after wakeup from Standby except for Power control register 3 (PWR_CR3). Refer to Table 28: Standby mode for more details on how to exit Standby mode. 154/1600 RM0394 Rev 4 RM0394 Power control (PWR) When exiting Standby mode, I/O’s that were configured with pull-up or pull-down during Standby through registers PWR_PUCRx or PWR_PDCRx will keep this configuration upon exiting Standby mode until the bit APC of PWR_CR3 register has been cleared. Once the bit APC is cleared, they will be either configured to their reset values or to the pull-up/pull-down state according the GPIOx_PUPDR registers. The content of the PWR_PUCRx or PWR_PDCRx registers however is not lost and can be re-used for a sub-sequent entering into Standby mode. Some I/Os (listed in Section 8.3.1: General-purpose I/O (GPIO)) are used for JTAG/SW debug and have internal pull-up or pull-down activated after reset so will be configured at this reset value as well when exiting Standby mode. For IO’s, with a pull-up or pull-down pre-defined after reset (some JTAG/SW IO’s) or with GPIOx_PUPDR programming done after exiting from Standby, in case those programming is different from the PWR_PUCRx or PWR_PDCRx programmed value during Standby, both a pull-down and pull-up will be applied until the bit APC is cleared, releasing the PWR_PUCRx or PWR_PDCRx programmed value. Table 28. Standby mode Standby mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register – No interrupt (for WFI) or event (for WFE) is pending – LPMS = “011” in PWR_CR1 – WUFx bits are cleared in power status register 1 (PWR_SR1) Mode entry On return from ISR while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register – SLEEPONEXIT = 1 – No interrupt is pending – LPMS = “011” in PWR_CR1 and – WUFx bits are cleared in power status register 1 (PWR_SR1) – The RTC flag corresponding to the chosen wakeup source (RTC Alarm A, RTC Alarm B, RTC wakeup, tamper or timestamp flags) is cleared Mode exit WKUPx pin edge, RTC event, external Reset in NRST pin, IWDG Reset, BOR reset Wakeup latency Reset phase RM0394 Rev 4 155/1600 174 Power control (PWR) 5.3.10 RM0394 Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. It is based on the deepsleep mode, with the voltage regulator disabled. The VCORE domain is consequently powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off. SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain. The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported. I/O states in Shutdown mode In the Shutdown mode, are by default in floating state. If the APC bit of PWR_CR3 register has been set, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx registers (x=A,B,C,D,E,F,G,H), or with a pull-down (refer to PWR_PDCRx registers (x=A,B,C,D,E,F,G,H)), or can be kept in analog state if none of the PWR_PUCRx or PWR_PDCRx register has been set. The pull-down configuration has highest priority over pull-up configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same IO. However this configuration is lost when exiting the Shutdown mode due to the power-on reset. Some I/Os (listed in Section 8.3.1: General-purpose I/O (GPIO)) are used for JTAG/SW debug and can only be configured to their respective reset pull-up or pull-down state during Standby mode setting their respective bit in the PWR_PUCRx or PWR_PDCRx registers to ‘1’, or will be configured to floating state if the bit is kept at ‘0’. The RTC outputs on PC13 are functional in Shutdown mode. PC14 and PC15 used for LSE are also functional. 5 wakeup pins (WKUPx, x=1,2...5) and the 3 RTC tampers are available. Entering Shutdown mode The Shutdown mode is entered according Entering low power mode, when the SLEEPDEEP bit in the Cortex®-M4 System Control register is set. Refer to Table 29: Shutdown mode for details on how to enter Shutdown mode. In Shutdown mode, the following features can be selected by programming individual control bits: • real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR). Caution: in case of VDD power-down the RTC content will be lost. • external 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR) Exiting Shutdown mode The Shutdown mode is exit according Section : Exiting low power mode. A power-on reset occurs when exiting from Shutdown mode. All registers (except for the ones in the Backup domain) are reset after wakeup from Shutdown. Refer to Table 29: Shutdown mode for more details on how to exit Shutdown mode. When exiting Shutdown mode, I/Os that were configured with pull-up or pull-down during Shutdown through registers PWR_PUCRx or PWR_PDCRx will lose their configuration and will be configured in floating state or to their pull-up pull-down reset value (for some I/Os 156/1600 RM0394 Rev 4 RM0394 Power control (PWR) listed in Section 8.3.1: General-purpose I/O (GPIO)). Table 29. Shutdown mode Shutdown mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register – No interrupt (for WFI) or event (for WFE) is pending – LPMS = “1XX” in PWR_CR1 – WUFx bits are cleared in power status register 1 (PWR_SR1) Mode entry 5.3.11 On return from ISR while: – SLEEPDEEP bit is set in Cortex®-M4 System Control register – SLEEPONEXT = 1 – No interrupt is pending – LPMS = “1XX” in PWR_CR1 and – WUFx bits are cleared in power status register 1 (PWR_SR1) – The RTC flag corresponding to the chosen wakeup source (RTC Alarm A, RTC Alarm B, RTC wakeup, tamper or timestamp flags) is cleared Mode exit WKUPx pin edge, RTC event, external Reset in NRST pin Wakeup latency Reset phase Auto-wakeup from low-power mode The RTC can be used to wakeup the MCU from low-power mode without depending on an external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for waking up from Stop (0, 1 or 2) or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR): • Low-power 32.768 kHz external crystal oscillator (LSE OSC) This clock source provides a precise time base with very low-power consumption. • Low-power internal RC Oscillator (LSI) This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC Oscillator is designed to add minimum power consumption. To wakeup from Stop mode with an RTC alarm event, it is necessary to: • Configure the EXTI Line 18 to be sensitive to rising edge • Configure the RTC to generate the RTC alarm To wakeup from Standby mode, there is no need to configure the EXTI Line 18. To wakeup from Stop mode with an RTC wakeup event, it is necessary to: • Configure the EXTI Line 20 to be sensitive to rising edge • Configure the RTC to generate the RTC alarm To wakeup from Standby mode, there is no need to configure the EXTI Line 20. The LCD Start of frame interrupt can also be used as a periodic wakeup from Stop (0, 1 or 2) mode. The LCD is not available in Standby mode. The LCD clock is derived from the RTC clock selected by RTCSEL[1:0]. RM0394 Rev 4 157/1600 174 Power control (PWR) 5.4 RM0394 PWR registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 5.4.1 Power control register 1 (PWR_CR1) Address offset: 0x00 Reset value: 0x0000 0200. This register is reset after wakeup from Standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. LPR Res. Res. Res. DBP Res. Res. Res. Res. Res. rw VOS[1:0] rw rw rw LPMS[2:0] rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 LPR: Low-power run When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead. Bits 13:11 Reserved, must be kept at reset value. Bits 10:9 VOS: Voltage scaling range selection 00: Cannot be written (forbidden by hardware) 01: Range 1 10: Range 2 11: Cannot be written (forbidden by hardware) Bit 8 DBP: Disable backup domain write protection In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: Access to RTC and Backup registers disabled 1: Access to RTC and Backup registers enabled Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 LPMS[2:0]: Low-power mode selection These bits select the low-power mode entered when CPU enters the deepsleep mode. 000: Stop 0 mode 001: Stop 1 mode 010: Stop 2 mode 011: Standby mode 1xx: Shutdown mode Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered instead of Stop 2. In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3. 158/1600 RM0394 Rev 4 RM0394 Power control (PWR) 5.4.2 Power control register 2 (PWR_CR2) Address offset: 0x04 Reset value: 0x0000 0000. This register is reset when exiting the Standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. USV(1) Res. Res. PVME4 PVME3 rw rw rw Res. PVME1 PLS[2:0] (1) rw rw rw PVDE rw rw 1. Available on STM32L4x2xx and STM32L4x3xx devices only. Bits 31:11 Reserved, must be kept at reset value. Bit 10 USV(1): VDDUSB USB supply valid This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USB FS peripheral. If VDDUSB is not always present in the application, the PVM can be used to determine whether this supply is ready or not. 0: VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply. 1: VDDUSB is valid. Bits 9:8 Reserved, must be kept at reset value. Bit 7 PVME4: Peripheral voltage monitoring 4 enable: VDDA vs. 1.8 V 0: PVM4 (VDDA monitoring vs. 1.8 V threshold) disable. 1: PVM4 (VDDA monitoring vs. 1.8 V threshold) enable. Bit 6 PVME3: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62 V 0: PVM3 (VDDA monitoring vs. 1.62 V threshold) disable. 1: PVM3 (VDDA monitoring vs. 1.62 V threshold) enable. Bit 5 Reserved, must be kept at reset value. RM0394 Rev 4 159/1600 174 Power control (PWR) RM0394 Bit 4 PVME1(1): Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2 V 0: PVM1 (VDDUSB monitoring vs. 1.2 V threshold) disable. 1: PVM1 (VDDUSB monitoring vs. 1.2 V threshold) enable. Bits 3:1 PLS[2:0]: Power voltage detector level selection. These bits select the voltage threshold detected by the power voltage detector: 000: VPVD0 around 2.0 V 001: VPVD1 around 2.2 V 010: VPVD2 around 2.4 V 011: VPVD3 around 2.5 V 100: VPVD4 around 2.6 V 101: VPVD5 around 2.8 V 110: VPVD6 around 2.9 V 111: External input analog voltage PVD_IN (compared internally to VREFINT) Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. These bits are reset only by a system reset. Bit 0 PVDE: Power voltage detector enable 0: Power voltage detector disable. 1: Power voltage detector enable. Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. This bit is reset only by a system reset. 1. Available on STM32L4x2xx and STM32L4x3xx devices only. 5.4.3 Power control register 3 (PWR_CR3) Address offset: 0x08 Reset value: 0x0000 8000. This register is not reset when exiting Standby modes and with the PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EIWUL Res. Res. Res. (1) APC Res. RRS Res. Res. Res. EWUP 5 EWUP 4 EWUP 3 EWUP 2 EWUP 1 rw rw rw rw rw rw rw rw ENULP rw 1. This bit is available on STM32L412xx and STM32L422xx devices only. Bits 31:16 Reserved, must be kept at reset value. Bit 15 EIWUL: Enable internal wakeup line 0: Internal wakeup line disable. 1: Internal wakeup line enable. Bits 14:12 Reserved, must be kept at reset value. 160/1600 RM0394 Rev 4 RM0394 Power control (PWR) Bit 11 ENULP: Enable ULP sampling When this bit is set, the BORL, BORH and PVD are periodically sampled instead continuous monitoring to reduce power consumption. Fast supply drop between two sample/compare phases will not be detected in this mode. This bit has impact only on STOP2, Standby and shutdown low power modes.(1) Bit 10 APC: Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os, instead the I/Os will be in floating mode during Standby or configured according GPIO controller GPIOx_PUPDR register during RUN mode. Bit 9 Reserved, must be kept at reset value. Bit 8 RRS: SRAM2 retention in Standby mode 0: SRAM2 is powered off in Standby mode (SRAM2 content is lost). 1: SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept). Bits 7:5 Reserved, must be kept at reset value. Bit 4 EWUP5: Enable Wakeup pin WKUP5 When this bit is set, the external wakeup pin WKUP5 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register. Bit 3 EWUP4: Enable Wakeup pin WKUP4 When this bit is set, the external wakeup pin WKUP4 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register. Bit 2 EWUP3: Enable Wakeup pin WKUP3 When this bit is set, the external wakeup pin WKUP3 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register. Bit 1 EWUP2: Enable Wakeup pin WKUP2 When this bit is set, the external wakeup pin WKUP2 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register. Bit 0 EWUP1: Enable Wakeup pin WKUP1 When this bit is set, the external wakeup pin WKUP1 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register. 1. This bit is available on STM32L12x and STM3L422xx devices only. 5.4.4 Power control register 4 (PWR_CR4) Address offset: 0x0C Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with the PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). RM0394 Rev 4 161/1600 174 Power control (PWR) RM0394 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. EXT_S MPS_O N(1) Res. Res. Res. VBRS VBE Res. Res. Res. WP5 WP4 WP3 WP2 WP1 rw rw rw rw rw rw rw Res. rw 1. This bit is available on STM32L412xx and STM32L422xx devices only. Bits 31:14 Reserved, must be kept at reset value. Bit 13 EXT_SMPS_ON: External SMPS On(1) This bit informs the internal regulator about external SMPS switch status to decrease regulator output to 0.95 V in Range 2, allowing the external SMPS output down to 1.00 V. 0: the external SMPS switch is open 1: the external SMPS switch is closed, internal regulator output is set to 0.95 V Bits 12:10 Reserved, must be kept at reset value. Bit 9 VBRS: VBAT battery charging resistor selection 0: Charge VBAT through a 5 kOhms resistor 1: Charge VBAT through a 1.5 kOhms resistor Bit 8 VBE: VBAT battery charging enable 0: VBAT battery charging disable 1: VBAT battery charging enable Bits 7:5 Reserved, must be kept at reset value. Bit 4 WP5: Wakeup pin WKUP5 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP5 0: Detection on high level (rising edge) 1: Detection on low level (falling edge) Bit 3 WP4: Wakeup pin WKUP4 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP4 0: Detection on high level (rising edge) 1: Detection on low level (falling edge) Bit 2 WP3: Wakeup pin WKUP3 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP3 0: Detection on high level (rising edge) 1: Detection on low level (falling edge) Bit 1 WP2: Wakeup pin WKUP2 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP2 0: Detection on high level (rising edge) 1: Detection on low level (falling edge) Bit 0 WP1: Wakeup pin WKUP1 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP1 0: Detection on high level (rising edge) 1: Detection on low level (falling edge) 1. This bit is available on STM32L412xx and STM32L422xx devices only. 162/1600 RM0394 Rev 4 RM0394 Power control (PWR) 5.4.5 Power status register 1 (PWR_SR1) Address offset: 0x10 Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with the PWRRST bit in the RCC_APB1RSTR1 register. Access: 2 additional APB cycles are needed to read this register vs. a standard APB read. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WUFI Res. EXT_S MPS_R DY(1) Res. Res. Res. Res. SBF Res. Res. Res. WUF5 WUF4 WUF3 WUF2 WUF1 r r r r r r r r 1. This bit is available on STM32L412xx and STM32L422xx devices only. Bits 31:16 Reserved, must be kept at reset value. Bit 15 WUFI: Wakeup flag internal This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared. Bit 14 Reserved, must be kept at reset value. Bit 13 EXT_SMPS_RDY: External SMPS Ready(1) This bit informs the state of regulator transition from Range 1 to Range 2.. 0: Internal regulator not ready in Range 2, the external SMPS cannot be connected 1: Internal regulator ready in Range 2, the external SMPS can be connected Bits 12:9 Reserved, must be kept at reset value. Bit 8 SBF: Standby flag This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset. 0: The device did not enter the Standby mode 1: The device entered the Standby mode Bits 7:5 Reserved, must be kept at reset value. Bit 4 WUF5: Wakeup flag 5 This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by writing ‘1’ in the CWUF5 bit of the PWR_SCR register. Bit 3 WUF4: Wakeup flag 4 This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by writing ‘1’ in the CWUF4 bit of the PWR_SCR register. RM0394 Rev 4 163/1600 174 Power control (PWR) RM0394 Bit 2 WUF3: Wakeup flag 3 This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by writing ‘1’ in the CWUF3 bit of the PWR_SCR register. Bit 1 WUF2: Wakeup flag 2 This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by writing ‘1’ in the CWUF2 bit of the PWR_SCR register. Bit 0 WUF1: Wakeup flag 1 This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by writing ‘1’ in the CWUF1 bit of the PWR_SCR register. 1. This bit is available on STM32L412xx and STM32L422xx devices only. 5.4.6 Power status register 2 (PWR_SR2) Address offset: 0x14 Reset value: 0x0000 0000. This register is partially reset when exiting Standby/Shutdown modes. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. PVMO4 PVMO3 r r Res. PVMO1 (1) PVDO VOSF r r r REGLP REGLP F S r r 1. Available on STM32L4x2xx and STM32L4x3xx devices only. Bits 31:16 Reserved, must be kept at reset value. Bit 15 PVMO4: Peripheral voltage monitoring output: VDDA vs. 1.8 V 0: VDDA voltage is above PVM4 threshold (around 1.8 V). 1: VDDA voltage is below PVM4 threshold (around 1.8 V). Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the PVM4 output is valid after the PVM4 wakeup time. Bit 14 PVMO3: Peripheral voltage monitoring output: VDDA vs. 1.62 V 0: VDDA voltage is above PVM3 threshold (around 1.62 V). 1: VDDA voltage is below PVM3 threshold (around 1.62 V). Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the PVM3 output is valid after the PVM3 wakeup time. Bit 13 Reserved, must be kept at reset value. Bit 12 PVMO1(1): Peripheral voltage monitoring output: VDDUSB vs. 1.2 V 0: VDDUSB voltage is above PVM1 threshold (around 1.2 V). 1: VDDUSB voltage is below PVM1 threshold (around 1.2 V). Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wakeup time. Bit 11 PVDO: Power voltage detector output 0: VDD is above the selected PVD threshold 1: VDD is below the selected PVD threshold 164/1600 RM0394 Rev 4 RM0394 Power control (PWR) Bit 10 VOSF: Voltage scaling flag A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register. 0: The regulator is ready in the selected voltage range 1: The regulator output voltage is changing to the required voltage level Bit 9 REGLPF: Low-power regulator flag This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. This bit is cleared by hardware when the regulator is ready. 0: The regulator is ready in main mode (MR) 1: The regulator is in low-power mode (LPR) Bit 8 REGLPS: Low-power regulator started This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wakeup from Standby mode time may be increased. 0: The low-power regulator is not ready 1: The low-power regulator is ready Bits 7:0 Reserved, must be kept at reset value. 1. Available on STM32L4x2xx and STM32L4x3xx devices only. 5.4.7 Power status clear register (PWR_SCR) Address offset: 0x18 Reset value: 0x0000 0000. Access: 3 additional APB cycles are needed to write this register vs. a standard APB write. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. CWUF 5 CWUF 4 CWUF 3 CWUF 2 CWUF 1 w w w w w Res. Res. Res. Res. Res. Res. Res. CSBF Res. w Res. Bits 31:9 Reserved, must be kept at reset value. Bit 8 CSBF: Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register. Bits 7:5 Reserved, must be kept at reset value. Bit 4 CWUF5: Clear wakeup flag 5 Setting this bit clears the WUF5 flag in the PWR_SR1 register. Bit 3 CWUF4: Clear wakeup flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register. RM0394 Rev 4 165/1600 174 Power control (PWR) RM0394 Bit 2 CWUF3: Clear wakeup flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register. Bit 1 CWUF2: Clear wakeup flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register. Bit 0 CWUF1: Clear wakeup flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register. 5.4.8 Power Port A pull-up control register (PWR_PUCRA) Address offset: 0x20. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PU15 Res. PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bit 15 PU15: Port A pull-up bit 15 When set, this bit activates the pull-up on PA[15] when APC bit is set in PWR_CR3 register. If the corresponding PD15 bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. Bit 14 Reserved, must be kept at reset value. Bits 13:0 PUy: Port A pull-up bit y (y=0..13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. 5.4.9 Power Port A pull-down control register (PWR_PDCRA) Address offset: 0x24. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 166/1600 RM0394 Rev 4 RM0394 Power control (PWR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. PD14 Res. PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 PD14: Port A pull-down bit 14 When set, this bit activates the pull-down on PA[14] when APC bit is set in PWR_CR3 register. Bit 13 Reserved, must be kept at reset value. Bits 12:0 PDy: Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register. 5.4.10 Power Port B pull-up control register (PWR_PUCRB) Address offset: 0x28. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. 5.4.11 Power Port B pull-down control register (PWR_PDCRB) Address offset: 0x2C. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). RM0394 Rev 4 167/1600 174 Power control (PWR) RM0394 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 Res. PD3 PD2 PD1 PD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:5 PDy: Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. Bit 4 Reserved, must be kept at reset value. Bits 3:0 PDy: Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register. 5.4.12 Power Port C pull-up control register (PWR_PUCRC) Address offset: 0x30. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. 5.4.13 Power Port C pull-down control register (PWR_PDCRC) Address offset: 0x34. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 168/1600 RM0394 Rev 4 RM0394 Power control (PWR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PDy: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register. 5.4.14 Power Port D pull-up control register (PWR_PUCRD) Not available on STM32L432xx and STM32L442xx devices. Address offset: 0x38. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. 5.4.15 Power Port D pull-down control register (PWR_PDCRD) Not available on STM32L432xx and STM32L442xx devices. Address offset: 0x3C. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). RM0394 Rev 4 169/1600 174 Power control (PWR) RM0394 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PDy: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register. 5.4.16 Power Port E pull-up control register (PWR_PUCRE) Not available on STM32L432xx and STM32L442xx devices. Address offset: 0x20. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. 5.4.17 Power Port E pull-down control register (PWR_PDCRE) Not available on STM32L432xx and STM32L442xx devices. Address offset: 0x44. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 170/1600 RM0394 Rev 4 RM0394 Power control (PWR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PDy: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register. 5.4.18 Power Port H pull-up control register (PWR_PUCRH) Address offset: 0x58. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU3 Res. PU1 PU0 rw rw rw Bits 31:4 Reserved, must be kept at reset value. Bit 3 PU3: Port H pull-up bit 3 When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. Bit 2 Reserved, must be kept at reset value. Bits 1:0 PUy: Port H pull-up bit y (y=0..1) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority. 5.4.19 Power Port H pull-down control register (PWR_PDCRH) Address offset: 0x5C. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). RM0394 Rev 4 171/1600 174 Power control (PWR) RM0394 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PD3 Res. PD1 PD0 rw rw rw Bits 31:4 Reserved, must be kept at reset value. Bit 3 PD3: Port H pull-down bit 3 When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. Bit 2 Reserved, must be kept at reset value. Bits 1:0 PDy: Port H pull-down bit y (y=0..1) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 172/1600 RM0394 Rev 4 0x040 PWR_PUCRE RM0394 Rev 4 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 Reset value PU13 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 Reset value PU14 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Reset value PD14 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 Reset value PU14 PU1 PU0 PU1 PU0 0 0 PD0 0 PD1 PU2 0 PD2 PU3 Reset value Res. Res. Res. Res. Res. Res. Res. CWUF5 CWUF4 CWUF3 CWUF2 CWUF1 0 Res. 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 WP4 WP3 WP2 WP1 0 0 0 0 0 WUF4 WUF3 WUF2 WUF1 0 WP5 EWUP5 EWUP4 EWUP3 EWUP2 EWUP1 0 WUF5 0 0 0 0 PLS [2:0] PVDE PVME1 Res. PVME3 Res. Res. PVME4 Res. Res. Res. 0 Res. Res. Res. RRS USV Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 Res. 0 Res. VBE APC Res. VBRS Reset value SBF ENULP Res. Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. EIWUL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. REGLPF REGLPS 0 Res. Res. 0 CSBF PVDO VOSF PVMO1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD0 PU2 PU4 0 PD3 0 0 Res. Res. PVMO3 Res. WUFI Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 PD1 PU3 PU5 0 PD4 PU6 0 PD5 PU7 0 PD6 PU8 0 PD7 PU9 0 PD8 0 PD9 PU10 0 PD10 PU11 0 PD11 0 PD12 PU12 0 PU13 PVMO4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. PU15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 PD2 PU4 0 Res. Reset value PD14 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. LPR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DBP VOS [1:0] PD3 PU5 PD5 PU6 PD6 PU7 PD7 PU8 PD8 PU9 PD9 PU10 PD10 PU11 PD11 PU12 PD12 PU13 PD13 PU14 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PD14 Reset value PD15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value PU15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value PD15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value PU15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value PD15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value PU15 Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PWR_PDCRD Res. 0x03C PWR_PUCRD Res. 0x038 PWR_PDCRC Res. 0x034 PWR_PUCRC Res. 0x030 PWR_PDCRB Res. 0x02C PWR_PUCRB Res. 0x028 PWR_PDCRA Res. 0x024 PWR_PUCRA Res. 0x020 PWR_SCR Res. 0x018 PWR_SR2 Res. 0x014 PWR_SR1 Res. 0x010 PWR_CR4 Res. 0x00C PWR_CR3 Res. 0x008 PWR_CR2 Res. 0x004 PWR_CR1 Res. 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 5.4.20 Res. RM0394 Power control (PWR) PWR register map and reset value table Table 30. PWR register map and reset values LPMS [2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 173/1600 174 0x05C 174/1600 PWR_PDCRH Reset value RM0394 Rev 4 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer toSection 2.2.2: Memory map and register boundary addresses for the register boundary addresses. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU3 Res. PU0 PD12 0 0 0 PD0 PD13 0 PU1 PD14 0 PD1 Res. Reset value PD3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PD15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PWR_PUCRH Res. 0x058 PWR_PDCRE Res. 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. Power control (PWR) RM0394 Table 30. PWR register map and reset values (continued) 0 0 RM0394 Reset and clock control (RCC) 6 Reset and clock control (RCC) 6.1 Reset There are three types of reset, defined as system reset, power reset and backup domain reset. 6.1.1 Power reset A power reset is generated when one of the following events occurs: 1. a Brown-out reset (BOR). 2. when exiting from Standby mode. 3. when exiting from Shutdown mode. A Brown-out reset, including power-on or power-down reset (POR/PDR), sets all registers to their reset values except the Backup domain. When exiting Standby mode, all registers in the VCORE domain are set to their reset value. Registers outside the VCORE domain (RTC, WKUP, IWDG, and Standby/Shutdown modes control) are not impacted. When exiting Shutdown mode, a Brown-out reset is generated, resetting all registers except those in the Backup domain. 6.1.2 System reset A system reset sets all registers to their reset values unless specified otherwise in the register description. A system reset is generated when one of the following events occurs: 1. A low level on the NRST pin (external reset) 2. Window watchdog event (WWDG reset) 3. Independent watchdog event (IWDG reset) 4. A firewall event (FIREWALL reset) 5. A software reset (SW reset) (see Software reset) 6. Low-power mode security reset (see Low-power mode security reset) 7. Option byte loader reset (see Option byte loader reset) 8. A Brown-out reset The reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR (see Section 6.4.29: Control/status register (RCC_CSR)). These sources act on the NRST pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at address 0x0000_0004 in the memory map. The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted low. In case on an internal reset, the internal pull-up RPU is deactivated in order to save the power consumption through the pull-up resistor. RM0394 Rev 4 175/1600 246 Reset and clock control (RCC) RM0394 Figure 12. Simplified diagram of the reset circuit s sͬs ZWh ^LJƐƚĞŵƌĞƐĞƚ ZWh džƚĞƌŶĂů ƌĞƐĞƚ EZ^d )LOWHU 3XOVH JHQHUDWRU PLQȝV ^LJƐƚĞŵƌĞƐĞƚ tt'ƌĞƐĞƚ /t'ƌĞƐĞƚ &ŝƌĞǁĂůůƌĞƐĞƚ ^ŽĨƚǁĂƌĞƌĞƐĞƚ >ŽǁͲƉŽǁĞƌŵĂŶĂŐĞƌƌĞƐĞƚ KƉƚŝŽŶďLJƚĞůŽĂĚĞƌƌĞƐĞƚ KZƌĞƐĞƚ 06Y9 069 Software reset The SYSRESETREQ bit in Cortex®-M4 Application Interrupt and Reset Control Register must be set to force a software reset on the device (refer to the STM32F3, STM32F4, STM32L4 and STM32L4+ Series Cortex®-M4 (PM0214)). Low-power mode security reset To prevent that critical applications mistakenly enter a low-power mode, two low-power mode security resets are available. If enabled in option bytes, the resets are generated in the following conditions: 1. Entering Standby mode: this type of reset is enabled by resetting nRST_STDBY bit in User option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode. 2. Entering Stop mode: this type of reset is enabled by resetting nRST_STOP bit in User option bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode. 3. Entering Shutdown mode: this type of reset is enabled by resetting nRST_SHDW bit in User option bytes. In this case, whenever a Shutdown mode entry sequence is successfully executed, the device is reset instead of entering Shutdown mode. For further information on the User Option Bytes, refer to Section 3.4.1: Option bytes description. Option byte loader reset The option byte loader reset is generated when the OBL_LAUNCH bit (bit 27) is set in the FLASH_CR register. This bit is used to launch the option byte loading by software. 6.1.3 Backup domain reset The backup domain has two specific resets. A backup domain reset is generated when one of the following events occurs: 176/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) 1. Software reset, triggered by setting the BDRST bit in the Backup domain control register (RCC_BDCR). 2. VDD or VBAT power on, if both supplies have previously been powered off. A backup domain reset only affects the LSE oscillator, the RTC, the Backup registers and the RCC Backup domain control register. 6.2 Clocks Four different clock sources can be used to drive the system clock (SYSCLK): • HSI16 (high speed internal)16 MHz RC oscillator clock • MSI (multispeed internal) RC oscillator clock • HSE oscillator clock, from 4 to 48 MHz • PLL clock The MSI is used as system clock source after startup from Reset, configured at 4 MHz. The devices have the following additional clock sources: • 32 kHz low speed internal RC (LSI RC) which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop and Standby modes. • 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the realtime clock (RTCCLK). • RC 48 MHz internal clock sources (HSI48) to potentially drive the USB FS, the SDMMC and the RNG. Each clock source can be switched on or off independently when it is not used, to optimize power consumption. Several prescalers can be used to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB, the APB1 and the APB2 domains is 80 MHz. RM0394 Rev 4 177/1600 246 Reset and clock control (RCC) RM0394 All the peripheral clocks are derived from their bus clock (HCLK, PCLK1 or PCLK2) except: • The 48 MHz clock, used for USB FS, SDMMC and RNG. This clock is derived (selected by software) from one of the four following sources: – main PLL VCO (PLL48M1CLK) – PLLSAI1 VCO (PLL48M2CLK) – MSI clock – HSI48 internal oscillator When the MSI clock is auto-trimmed with the LSE, it can be used by the USB FS device. • • The ADCs clock which is derived (selected by software) from one of the following sources: – system clock (SYSCLK) – PLLSAI1 VCO (PLLADC1CLK)(not available on STM3L41xxx and STM32L42xxx devices) The U(S)ARTs clocks which are derived (selected by software) from one of the four following sources: – system clock (SYSCLK) – HSI16 clock – LSE clock – APB1 or APB2 clock (PCLK1 or PCLK2 depending on which APB is mapped the U(S)ART) The wakeup from Stop mode is supported only when the clock is HSI16 or LSE. • The I2Cs clocks which are derived (selected by software) from one of the three following sources: – system clock (SYSCLK) – HSI16 clock – APB1 clock (PCLK1) The wakeup from Stop mode is supported only when the clock is HSI16. • • The SAI1 clock which derived (selected by software) from one of the following sources: – an external clock mapped on SAI1_EXTCLK for SAI1 – PLLSAI1 VCO (PLLSAICLK) – main PLL VCO (PLLSAICLK) – HSI16 clock The SWPMI1 clock which is derived (selected by software) from one of the two following sources: – HSI16 clock – APB1 clock (PCLK1) The wakeup from Stop mode is supported only when the clock is HSI16. • • 178/1600 The DFSDM1 clock (only applicable for STM32L45x/46x) which is derived (selected by software) from one of the two following sources: – system clock (SYSCLK) – APB2 clock (PCLK2) The low-power timers (LPTIMx) clock which are derived (selected by software) from RM0394 Rev 4 RM0394 Reset and clock control (RCC) one of the five following sources: – LSI clock – LSE clock – HSI16 clock – APB1 clock (PCLK1) – External clock mapped on LPTIMx_IN1 The functionality in Stop mode (including wakeup) is supported only when the clock is LSI or LSE, or in external clock mode. • The RTC and LCD clock which is derived (selected by software) from one of the three following sources: – LSE clock – LSI clock – HSE clock divided by 32 The functionality in Stop mode (including wakeup) is supported only when the clock is LSI or LSE. • The IWDG clock which is always the LSI clock. The RCC feeds the Cortex® System Timer (SysTick) external clock with the AHB clock (HCLK) divided by 8. The SysTick can work either with this clock or directly with the Cortex® clock (HCLK), configurable in the SysTick Control and Status Register. FCLK acts as Cortex®-M4 free-running clock. For more details refer to the STM32F3, STM32F4, STM32L4 and STM32L4+ Series Cortex®-M4 programming manual (PM0214). RM0394 Rev 4 179/1600 246 Reset and clock control (RCC) RM0394 Figure 13. Clock tree WR,:'* /6,5&N+] /6&2 WR57&DQG/&' 26&B287 /6(26& N+] 26&B,1 /6( /6, +6( WR3:5 6<6&/. 0&2 ĺ 06, +6, 26&B287 +6(26& 0+] 26&B,1 WR$+%EXVFRUHPHPRU\DQG'0$ &ORFN VRXUFH FRQWURO 5& $+% 35(6& +6( &ORFN GHWHFWRU +&/. )&/.&RUWH[IUHHUXQQLQJFORFN 06, +6, 6<6&/. $3% 35(6& WR&RUWH[V\VWHPWLPHU 3&/. WR$3%SHULSKHUDOV [RU[ +6,5& 0+] /6( +6, 6<6&/. WR86$57[ [ WR/38$57 +6, 6<6&/. 06,5& N+]±0+] WR,&[ [ /6, /6( +6, WR/37,0[ [ +6, 06, 0 9&2 3 3//6$,&/. [1 4 3//0&/. 5 3//&/. +6, $3% 35(6& +6( WR7,0[ [ WR6:30, 3&/. WR$3%SHULSKHUDOV [RU[ WR7,0[ [ 3// 9&2 3 3//6$,&/. [1 4 3//0&/. 5 3//$'&&/. /6( +6, 6<6&/. 0+]FORFNWR86% 51*6'00& 06, 3//6$, WR 86$57 6<6&/. WR$'&[ [ +6, +6,5& 0+] WR6$, +6, &56 WR')6'0 6<6&/. 6$,B(;7&/. 2QO\6<6&/.FRXGEHVHOHFWHGRQ670/[[[DQG670/[[[GHYLFHV 3//6$,QRWDYDLODEOHRQ670/[[[DQG670/[[[GHYLFHV 180/1600 RM0394 Rev 4 069 RM0394 Reset and clock control (RCC) 1. For full details about the internal and external clock source characteristics, please refer to the “Electrical characteristics” section in your device datasheet. 2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). When the programmable factor is ‘1’, the AHB prescaler must be equal to ‘1’. 6.2.1 HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: • HSE external crystal/ceramic resonator • HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. Figure 14. HSE/ LSE clock sources Clock source Hardware configuration OSC_IN OSC_OUT External clock GPIO External source External clock (available on some package, please refer to the corresponding datasheet) CK_IN GPIO External source OSC_IN OSC_OUT Crystal/Ceramic resonators CL1 RM0394 Rev 4 Load capacitors CL2 181/1600 246 Reset and clock control (RCC) RM0394 External crystal/ceramic resonator (HSE crystal) The 4 to 48 MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 14. Refer to the electrical characteristics section of the datasheet for more details. The HSERDY flag in the Clock control register (RCC_CR) indicates if the HSE oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER). The HSE Crystal can be switched on and off using the HSEON bit in the Clock control register (RCC_CR). External source (HSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 48 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control register (RCC_CR). The external clock signal (square, sinus or triangle) with ~40-60 % duty cycle depending on the frequency (refer to the datasheet) has to drive the OSC_IN pin while the OSC_OUT pin can be used a GPIO. See Figure 14. 6.2.2 HSI16 clock The HSI16 clock signal is generated from an internal 16 MHz RC Oscillator. The HSI16 RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator. The HSI16 clock can be selected as system clock after wakeup from Stop modes (Stop 0, Stop 1 or Stop 2). Refer to Section 6.3: Low-power modes. It can also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 6.2.10: Clock security system (CSS). Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1 % accuracy at TA=25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Internal clock sources calibration register (RCC_ICSCR). If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. You can trim the HSI16 frequency in the application using the HSITRIM[6:0] bits in the Internal clock sources calibration register (RCC_ICSCR). For more details on how to measure the HSI16 frequency variation, refer to Section 6.2.17: Internal/external clock measurement with TIM15/TIM16. The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI16 RC is stable or not. At startup, the HSI16 RC output clock is not released until this bit is set by hardware. The HSI16 RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR). 182/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) The HSI16 signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 6.2.10: Clock security system (CSS) on page 186. 6.2.3 MSI clock The MSI clock signal is generated from an internal RC oscillator. Its frequency range can be adjusted by software by using the MSIRANGE[3:0] bits in the Clock control register (RCC_CR). Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, 1 MHz, 2 MHz, 4 MHz (default value), 8 MHz, 16 MHz, 24 MHz, 32 MHz and 48 MHz. The MSI clock is used as system clock after restart from Reset, wakeup from Standby and Shutdown low-power modes. After restart from Reset, the MSI frequency is set to its default value 4 MHz. Refer to Section 6.3: Low-power modes. The MSI clock can be selected as system clock after a wakeup from Stop mode (Stop 0, Stop 1 or Stop 2). Refer to Section 6.3: Low-power modes. It can also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 6.2.10: Clock security system (CSS). The MSI RC oscillator has the advantage of providing a low-cost (no external components) low-power clock source. In addition, when used in PLL-mode with the LSE, it provides a very accurate clock source which can be used by the USB FS device, and feed the main PLL to run the system at the maximum speed 80 MHz. The MSIRDY flag in the Clock control register (RCC_CR) indicates wether the MSI RC is stable or not. At startup, the MSI RC output clock is not released until this bit is set by hardware. The MSI RC can be switched on and off by using the MSION bit in the Clock control register (RCC_CR). Hardware auto calibration with LSE (PLL-mode) When a 32.768 kHz external oscillator is present in the application, it is possible to configure the MSI in a PLL-mode by setting the MSIPLLEN bit in the Clock control register (RCC_CR). When configured in PLL-mode, the MSI automatically calibrates itself thanks to the LSE. This mode is available for all MSI frequency ranges. At 48 MHz, the MSI in PLL-mode can be used for the USB FS device, saving the need of an external high-speed crystal. Software calibration The MSI RC oscillator frequency can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1 % accuracy at an ambient temperature, TA, of 25 °C. After reset, the factory calibration value is loaded in the MSICAL[7:0] bits in the Internal clock sources calibration register (RCC_ICSCR). If the application is subject to voltage or temperature variations, this may affect the RC oscillator speed. You can trim the MSI frequency in the application by using the MSITRIM[7:0] bits in the RCC_ICSCR register. For more details on how to measure the MSI frequency variation please refer to Section 6.2.17: Internal/external clock measurement with TIM15/TIM16. 6.2.4 HSI48 clock The HSI48 clock signal is generated from an internal 48 MHz RC oscillator and can be used directly for USB and for random number generator (RNG) as well as SDMMC. The internal 48 MHz RC oscillator is mainly dedicated to provide a high precision clock to the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. The CRS can use the USB SOF signal, the LSE or an external signal to automatically and quickly RM0394 Rev 4 183/1600 246 Reset and clock control (RCC) RM0394 adjust the oscillator frequency on-fly. It is disabled as soon as the system enters Stop or Standby mode. When the CRS is not used, the HSI48 RC oscillator runs on its default frequency which is subject to manufacturing process variations. For more details on how to configure and use the CRS peripheral please refer to Section 7: Clock recovery system (CRS). The HSI48RDY flag in the Clock recovery RC register (RCC_CRRCR) indicates whether the HSI48 RC oscillator is stable or not. At startup, the HSI48 RC oscillator output clock is not released until this bit is set by hardware. The HSI48 can be switched on and off using the HSI48ON bit in the Clock recovery RC register (RCC_CRRCR). 6.2.5 PLL The device embeds PLLs: PLL, PLLSAI1. Each PLL provides up to three independent outputs. The internal PLLs can be used to multiply the HSI16, HSE or MSI output clock frequency. The PLLs input frequency must be between 4 and 16 MHz. The selected clock source is divided by a programmable factor PLLM from 1 to 8 to provide a clock frequency in the requested input range. Refer to Figure 13: Clock treeand PLL configuration register (RCC_PLLCFGR). The PLLs configuration (selection of the input clock and multiplication factor) must be done before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed. To modify the PLL configuration, proceed as follows: 1. Disable the PLL by setting PLLON to 0 in Clock control register (RCC_CR). 2. Wait until PLLRDY is cleared. The PLL is now fully stopped. 3. Change the desired parameter. 4. Enable the PLL again by setting PLLON to 1. 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN in PLL configuration register (RCC_PLLCFGR). An interrupt can be generated when the PLL is ready, if enabled in the Clock interrupt enable register (RCC_CIER). The same procedure is applied for changing the configuration of the PLLSAI1: 1. Disable the PLLSAI1/PLLSAI2 by setting PLLSAI1ON to 0 in Clock control register (RCC_CR). 2. Wait until PLLSAI1RDY is cleared. The PLLSAI1 is now fully stopped. 3. Change the desired parameter. 4. Enable the PLLSAI1 again by setting PLLSAI1ON to 1. 5. Enable the desired PLL outputs by configuring PLLSAI1PEN, PLLSAI1QEN, PLLSAI1REN in PLLSAI1 configuration register (RCC_PLLSAI1CFGR). The PLL output frequency must not exceed 80 MHz. The enable bit of each PLL output clock (PLLPEN, PLLQEN, PLLREN, PLLSAI1PEN, PLLSAI1QEN, PLLSAI1REN) can be modified at any time without stopping the corresponding PLL. PLLREN cannot be cleared if PLLCLK is used as system clock. 184/1600 RM0394 Rev 4 RM0394 6.2.6 Reset and clock control (RCC) LSE clock The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage of providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions. The LSE crystal is switched on and off using the LSEON bit in Backup domain control register (RCC_BDCR). The crystal oscillator driving strength can be changed at runtime using the LSEDRV[1:0] bits in the Backup domain control register (RCC_BDCR) to obtain the best compromise between robustness and short start-up time on one side and lowpower-consumption on the other side. The LSE drive can be decreased to the lower drive capability (LSEDRV=00) when the LSE is ON. However, once LSEDRV is selected, the drive capability can not be increased if LSEON=1. The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER). Distribution of the external 32 kHz clock (LSE) outside the RTC block could be disabled by setting LSESYSDIS bit in Backup domain control register (RCC_BDCR) to reduce power consumption. Propagation will be stoped regardless the use of LSE by other IP's. This feature is present on STM32L412xx and STM32L422xx devices only. External source (LSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR). The external clock signal (square, sinus or triangle) with ~50 % duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin can be used as GPIO. See Figure 14. 6.2.7 LSI clock The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby mode for the independent watchdog (IWDG), RTC and LCD. The clock frequency is 32 kHz. For more details, refer to the electrical characteristics section of the datasheets. The LSI RC can be switched on and off using the LSION bit in the Control/status register (RCC_CSR). The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the LSI oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER). 6.2.8 System clock (SYSCLK) selection Four different clock sources can be used to drive the system clock (SYSCLK): • MSI oscillator • HSI16 oscillator • HSE oscillator • PLL RM0394 Rev 4 185/1600 246 Reset and clock control (RCC) RM0394 The system clock maximum frequency is 80 MHz. After a system reset, the MSI oscillator, at 4 MHz, is selected as system clock. When a clock source is used directly or through the PLL as a system clock, it is not possible to stop it. A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source becomes ready. Status bits in the Internal clock sources calibration register (RCC_ICSCR) indicate which clock(s) is (are) ready and which clock is currently used as a system clock. 6.2.9 Clock source frequency versus voltage scaling The following table gives the different clock source frequencies depending on the product voltage range. Table 31. Clock source frequency Clock frequency Product voltage range MSI HSI16 HSE PLL/PLLSAI1 Range 1 (1) 48 MHz 16 MHz 48 MHz 80 MHz (VCO max = 344 MHz) Range 2(2) 24 MHz range 16 MHz 26 MHz 26 MHz (VCO max = 128 MHz) 1. Also for SMPS Range1 and SMPS Range2 High 2. Also for SMPS Range2 Low 6.2.10 Clock security system (CSS) Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock failure event is sent to the break input of the advanced-control timers (TIM1 and TIM15/16) and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex®-M4 NMI (Non-Maskable Interrupt) exception vector. Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and a NMI is automatically generated. The NMI will be executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the Clock interrupt clear register (RCC_CICR). If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the MSI or the HSI16 oscillator depending on the STOPWUCK configuration in the Clock configuration register (RCC_CFGR), and the disabling of the HSE oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too. 186/1600 RM0394 Rev 4 RM0394 6.2.11 Reset and clock control (RCC) Clock security system on LSE A Clock Security System on LSE can be activated by software writing the LSECSSON bit in the Backup domain control register (RCC_BDCR). This bit can be disabled only by a hardware reset or RTC software reset, or after a failure detection on LSE. LSECSSON must be written after LSE and LSI are enabled (LSEON and LSION enabled) and ready (LSERDY and LSIRDY set by hardware), and after the RTC clock has been selected by RTCSEL. The CSS on LSE is working in all modes except VBAT. It is working also under system reset (excluding power on reset). If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied to the RTC but no hardware action is made to the registers. If the MSI was in PLL-mode, this mode is disabled. In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup the software (see Clock interrupt enable register (RCC_CIER), Clock interrupt flag register (RCC_CIFR), Clock interrupt clear register (RCC_CICR)). The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator (disabling LSEON), and change the RTC clock source (no clock or LSI or HSE, with RTCSEL), or take any required action to secure the application. The frequency of LSE oscillator have to be higher than 30 kHz to avoid false positive CSS detection. 6.2.12 ADC clock The ADC clock is derived from the system clock, or from the PLLSAI1 output(a). It can reach 80 MHz and can be divided by the following prescalers values: 1,2,4,6,8,10,12,16,32,64,128 or 256 by configuring the ADC1_CCR register. It is asynchronous to the AHB clock. Alternatively, the ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). This programmable factor is configured using the CKMODE bit fields in the ADC1_CCR. If the programmed factor is ‘1’, the AHB prescaler must be set to ‘1’. 6.2.13 RTC clock The RTCCLK clock source can be either the HSE/32, LSE or LSI clock. It is selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR). This selection cannot be modified without resetting the Backup domain. The system must always be configured so as to get a PCLK frequency greater then or equal to the RTCCLK frequency for a proper operation of the RTC. a. Except STM32L41xxx/42xxx devices RM0394 Rev 4 187/1600 246 Reset and clock control (RCC) RM0394 The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently: • If LSE is selected as RTC clock: – • If LSI is selected as the RTC clock: – • The RTC continues to work even if the VDD supply is switched off, provided the VBAT supply is maintained. The RTC state is not guaranteed if the VDD supply is powered off. If the HSE clock divided by a prescaler is used as the RTC clock: – The RTC state is not guaranteed if the VDD supply is powered off or if the internal voltage regulator is powered off (removing power from the VCORE domain). When the RTC clock is LSE or LSI, the RTC remains clocked and functional under system reset. 6.2.14 Timer clock The timer clock frequencies are automatically defined by hardware. There are two cases: 6.2.15 1. If the APB prescaler equals 1, the timer clock frequencies are set to the same frequency as that of the APB domain. 2. Otherwise, they are set to twice (×2) the frequency of the APB domain. Watchdog clock If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG. 6.2.16 Clock-out capability • MCO The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. One of eight clock signals can be selected as the MCO clock. – LSI – LSE – SYSCLK – HSI16 – HSI48 – HSE – PLLCLK – MSI The selection is controlled by the MCOSEL[:0] bits of the Clock configuration register (RCC_CFGR). The selected clock can be divided with the MCOPRE[2:0] field of the 188/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) Clock configuration register (RCC_CFGR). • LSCO Another output (LSCO) allows a low speed clock to be output onto the external LSCO pin: – LSI – LSE This output remains available in Stop (Stop 0, Stop 1 and Stop 2) and Standby modes. The selection is controlled by the LSCOSEL, and enabled with the LSCOEN in the Backup domain control register (RCC_BDCR). The MCO clock output requires the corresponding alternate function selected on the MCO pin, the LSCO pin should be left in default POR state. 6.2.17 Internal/external clock measurement with TIM15/TIM16 It is possible to indirectly measure the frequency of all on-board clock sources by mean of the TIM15 or TIM16 channel 1 input capture, as represented on Figure 15 and Figure 16 Figure 15. Frequency measurement with TIM15 in capture mode 7,0 7,B503 *3,2 7, /6( 069 The input capture channel of the Timer 15 can be a GPIO line or an internal clock of the MCU. This selection is performed through the TI1_RMP bit in the TIM15_OR register. The possibilities are the following ones: • TIM15 Channel1 is connected to the GPIO. Refer to the alternate function mapping in the device datasheets. • TIM15 Channel1 is connected to the LSE. Figure 16. Frequency measurement with TIM16 in capture mode 7,0 7,B503>@ *3,2 7, /6, /6( 57&ZDNHXSLQWHUUXSW 069 RM0394 Rev 4 189/1600 246 Reset and clock control (RCC) RM0394 The input capture channel of the Timer 16 can be a GPIO line or an internal clock of the MCU. This selection is performed through the TI1_RMP[1:0] bits in the TIM16_OR register. The possibilities are the following ones: • TIM16 Channel1 is connected to the GPIO. Refer to the alternate function mapping in the device datasheets. • TIM16 Channel1 is connected to the LSI clock. • TIM16 Channel1 is connected to the LSE clock. • TIM16 Channel1 is connected to the RTC wakeup interrupt signal. In this case the RTC interrupt should be enabled. Calibration of the HSI16 and the MSI For TIM15 and TIM16, the primary purpose of connecting the LSE to the channel 1 input capture is to be able to precisely measure the HSI16 and MSI system clocks (for this, either the HSI16 or MSI should be used as the system clock source). The number of HSI16 (MSI, respectively) clock counts between consecutive edges of the LSE signal provides a measure of the internal clock period. Taking advantage of the high precision of LSE crystals (typically a few tens of ppm’s), it is possible to determine the internal clock frequency with the same resolution, and trim the source to compensate for manufacturing, process, temperature and/or voltage related frequency deviations. The MSI and HSI16 oscillator both have dedicated user-accessible calibration bits for this purpose. The basic concept consists in providing a relative measurement (e.g. the HSI16/LSE ratio): the precision is therefore closely related to the ratio between the two clock sources. The higher the ratio is, the better the measurement will be. If LSE is not available, HSE/32 will be the better option in order to reach the most precise calibration possible. It is however not possible to have a good enough resolution when the MSI clock is low (typically below 1 MHz). In this case, it is advised to: • accumulate the results of several captures in a row • use the timer’s input capture prescaler (up to 1 capture every 8 periods) • use the RTC wakeup interrupt signal (when the RTC is clocked by the LSE) as the input for the channel1 input capture. This improves the measurement precision. For this purpose the RTC wakeup interrupt must be enable. Calibration of the LSI The calibration of the LSI will follow the same pattern that for the HSI16, but changing the reference clock. It will be necessary to connect LSI clock to the channel 1 input capture of the TIM16. Then define the HSE as system clock source, the number of his clock counts between consecutive edges of the LSI signal provides a measure of the internal low speed clock period. The basic concept consists in providing a relative measurement (e.g. the HSE/LSI ratio): the precision is therefore closely related to the ratio between the two clock sources. The higher the ratio is, the better the measurement will be. 190/1600 RM0394 Rev 4 RM0394 6.2.18 Reset and clock control (RCC) Peripheral clock enable register (RCC_AHBxENR, RCC_APBxENRy) Each peripheral clock can be enabled by the xxxxEN bit of the RCC_AHBxENR, RCC_APBxENRy registers. When the peripheral clock is not active, the peripheral registers read or write accesses are not supported. The enable bit has a synchronization mechanism to create a glitch free clock for the peripheral. After the enable bit is set, there is a 2 clock cycles delay before the clock be active. Caution: Just after enabling the clock for a peripheral, software must wait for a delay before accessing the peripheral registers. 6.3 Low-power modes • AHB and APB peripheral clocks, including DMA clock, can be disabled by software. • Sleep and Low Power Sleep modes stops the CPU clock. The memory interface clocks (Flash and SRAM1 and SRAM2 interfaces) can be stopped by software during sleep mode. The AHB to APB bridge clocks are disabled by hardware during Sleep mode when all the clocks of the peripherals connected to them are disabled. • Stop modes (Stop 0, Stop 1 and Stop 2) stops all the clocks in the VCORE domain and disables the PLL, the HSI16, the MSI and the HSE oscillators. All U(S)ARTs, LPUARTs and I2Cs have the capability to enable the HSI16 oscillator even when the MCU is in Stop mode (if HSI16 is selected as the clock source for that peripheral). All U(S)ARTs and LPUARTs can also be driven by the LSE oscillator when the system is in Stop mode (if LSE is selected as clock source for that peripheral) and the LSE oscillator is enabled (LSEON). In that case the LSE remains always ON in Stop mode (they do not have the capability to turn on the LSE oscillator). • Standby and Shutdown modes stops all the clocks in the VCORE domain and disables the PLL, the HSI16, the MSI and the HSE oscillators. The CPU’s deepsleep mode can be overridden for debugging by setting the DBG_STOP or DBG_STANDBY bits in the DBGMCU_CR register. When leaving the Stop modes (Stop 0, Stop 1 or Stop 2), the system clock is either MSI or HSI16, depending on the software configuration of the STOPWUCK bit in the RCC_CFGR register. The frequency (range and user trim) of the MSI oscillator is the one configured before entering Stop mode. The user trim of HSI16 is kept. If the MSI was in PLL-mode before entering Stop mode, the PLL-mode stabilization time must be waited for after wakeup even if the LSE was kept ON during the Stop mode. When leaving the Standby and Shutdown modes, the system clock is MSI. The MSI frequency at wakeup from Standby mode is configured with the MSISRANGE is the RCC_CSR register, from 1 to 8 MHz. The MSI frequency at wakeup from Shutdown mode is 4 MHz. The user trim is lost. If a Flash memory programming operation is on going, Stop, Standby and Shutdown modes entry is delayed until the Flash memory interface access is finished. If an access to the APB domain is ongoing, Stop, Standby and Shutdown modes entry is delayed until the APB access is finished. RM0394 Rev 4 191/1600 246 Reset and clock control (RCC) RM0394 6.4 RCC registers 6.4.1 Clock control register (RCC_CR) Address offset: 0x00 Access: no wait state, word, half-word and byte access 31 Res. 30 Res. 15 Res. 29 14 Res. 13 Res. Res. 28 27 26 Res. PLL SAI1 PLL SAI1 RDY(1) ON(1) r rw 12 11 10 Res. HSI ASFS HSI RDY rw r 25 24 23 22 21 20 19 18 17 16 PLL RDY PLLON Res. Res. Res. Res. CSS ON HSE BYP HSE RDY HSE ON r rw rs rw r rw 9 8 3 2 7 HSI HSION KERON rw rw 6 5 4 MSI MSI RGSEL PLLEN MSIRANGE[3:0] rw rw rw rw rs rw 1 0 MSI RDY MSION r rw 1. Not available on STM3L41xxx and STM32L42xxx devices Bits 31: Reserved, must be kept at reset value. Bit 27 PLLSAI1RDY: SAI1 PLL clock ready flag Set by hardware to indicate that the PLLSAI1 is locked. 0: PLLSAI1 unlocked 1: PLLSAI1 locked Bit 26 PLLSAI1ON: SAI1 PLL enable Set and cleared by software to enable PLLSAI1. Cleared by hardware when entering Stop, Standby or Shutdown mode. 0: PLLSAI1 OFF 1: PLLSAI1 ON Bit 25 PLLRDY: Main PLL clock ready flag Set by hardware to indicate that the main PLL is locked. 0: PLL unlocked 1: PLL locked Bit 24 PLLON: Main PLL enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock. 0: PLL OFF 1: PLL ON Bits 23:20 Reserved, must be kept at reset value. Bit 19 CSSON: Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. 0: Clock security system OFF (clock detector OFF) 1: Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not). 192/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) Bit 18 HSEBYP: HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. 0: HSE crystal oscillator not bypassed 1: HSE crystal oscillator bypassed with external clock Bit 17 HSERDY: HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. 0: HSE oscillator not ready 1: HSE oscillator ready Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles. Bit 16 HSEON: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON Bits 15:12 Reserved, must be kept at reset value. Bit 11 HSIASFS: HSI16 automatic start from Stop Set and cleared by software. When the system wakeup clock is MSI, this bit is used to wakeup the HSI16 is parallel of the system wakeup. 0: HSI16 oscillator is not enabled by hardware when exiting Stop mode with MSI as wakeup clock. 1: HSI16 oscillator is enabled by hardware when exiting Stop mode with MSI as wakeup clock. Bit 10 HSIRDY: HSI16 clock ready flag Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION. 0: HSI16 oscillator not ready 1: HSI16 oscillator ready Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles. Bit 9 HSIKERON: HSI16 always enable for peripheral kernels. Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only feed USARTs and I2Cs peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode allows to avoid slowing down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value. 0: No effect on HSI16 oscillator. 1: HSI16 oscillator is forced ON even in Stop mode. Bit 8 HSION: HSI16 clock enable Set and cleared by software. Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the HSI16 oscillator ON when STOPWUCK=1 or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI16 is used directly or indirectly as system clock. 0: HSI16 oscillator OFF 1: HSI16 oscillator ON RM0394 Rev 4 193/1600 246 Reset and clock control (RCC) RM0394 Bit 18 HSEBYP: HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. 0: HSE crystal oscillator not bypassed 1: HSE crystal oscillator bypassed with external clock Bit 17 HSERDY: HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. 0: HSE oscillator not ready 1: HSE oscillator ready Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles. Bit 16 HSEON: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON Bits 15:12 Reserved, must be kept at reset value. Bit 11 HSIASFS: HSI16 automatic start from Stop Set and cleared by software. When the system wakeup clock is MSI, this bit is used to wakeup the HSI16 is parallel of the system wakeup. 0: HSI16 oscillator is not enabled by hardware when exiting Stop mode with MSI as wakeup clock. 1: HSI16 oscillator is enabled by hardware when exiting Stop mode with MSI as wakeup clock. Bit 10 HSIRDY: HSI16 clock ready flag Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION. 0: HSI16 oscillator not ready 1: HSI16 oscillator ready Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles. Bit 9 HSIKERON: HSI16 always enable for peripheral kernels. Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only feed USARTs and I2Cs peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode allows to avoid slowing down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value. 0: No effect on HSI16 oscillator. 1: HSI16 oscillator is forced ON even in Stop mode. Bit 8 HSION: HSI16 clock enable Set and cleared by software. Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the HSI16 oscillator ON when STOPWUCK=1 or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI16 is used directly or indirectly as system clock. 0: HSI16 oscillator OFF 1: HSI16 oscillator ON 194/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) Bits 7:4 MSIRANGE[3:0]: MSI clock ranges These bits are configured by software to choose the frequency range of MSI when MSIRGSEL is set.12 frequency ranges are available: 0000: range 0 around 100 kHz 0001: range 1 around 200 kHz 0010: range 2 around 400 kHz 0011: range 3 around 800 kHz 0100: range 4 around 1M Hz 0101: range 5 around 2 MHz 0110: range 6 around 4 MHz (reset value) 0111: range 7 around 8 MHz 1000: range 8 around 16 MHz 1001: range 9 around 24 MHz 1010: range 10 around 32 MHz 1011: range 11 around 48 MHz others: not allowed (hardware write protection) Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready (MSIRDY=1). MSIRANGE must NOT be modified when MSI is ON and NOT ready (MSION=1 and MSIRDY=0) Bit 3 MSIRGSEL: MSI clock range selection Set by software to select the MSI clock range with MSIRANGE[3:0]. Write 0 has no effect. After a standby or a reset MSIRGSEL is at 0 and the MSI range value is provided by MSISRANGE in CSR register. 0: MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register 1: MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register Bit 2 MSIPLLEN: MSI clock PLL enable Set and cleared by software to enable/ disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware).There is a hardware protection to avoid enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock Security System on LSE detects a LSE failure (refer to RCC_CSR register). 0: MSI PLL OFF 1: MSI PLL ON Bit 1 MSIRDY: MSI clock ready flag This bit is set by hardware to indicate that the MSI oscillator is stable. 0: MSI oscillator not ready 1: MSI oscillator ready Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles. Bit 0 MSION: MSI clock enable This bit is set and cleared by software. Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop modes, or in case of a failure of the HSE oscillator Set by hardware when used directly or indirectly as system clock. 0: MSI oscillator OFF 1: MSI oscillator ON RM0394 Rev 4 195/1600 246 Reset and clock control (RCC) 6.4.2 RM0394 Internal clock sources calibration register (RCC_ICSCR) Address offset: 0x04 Reset value: 0x40XX 00XX where X is factory-programmed. Access: no wait state, word, half-word and byte access 31 30 29 28 Res. 27 26 25 24 23 22 21 HSITRIM[6:0] 20 19 18 17 16 HSICAL[7:0] rw rw rw rw rw rw rw r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rwr rw rw r r r r r r MSITRIM[7:0] rw rw MSICAL[7:0] r r Bit 31 Reserved, must be kept at reset value. Bits 30:24 HSITRIM[6:0]: HSI16 clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI16. The default value is 64 when added to the HSICAL value, trim the HSI16 to 16 MHz ± 1 %. Bits 23:16 HSICAL[7:0]: HSI16 clock calibration These bits are initialized at startup with the factory-programmed HSI16 calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. Bits 15:8 MSITRIM[7:0]: MSI clock trimming These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI. Bits 7:0 MSICAL[7:0]: MSI clock calibration These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value. 6.4.3 Clock configuration register (RCC_CFGR) Address offset: 0x08 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. From 0 to 15 wait states inserted if the access occurs when the APB or AHB prescalers values update is on going. 196/1600 RM0394 Rev 4 RM0394 31 Reset and clock control (RCC) 30 Res. 29 28 27 MCOPRE[2:0] 26 25 24 MCOSEL[3:0] rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 STOP WUCK Res. rw PPRE2[2:0] rw rw 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 PPRE1[2:0] rw rw rw HPRE[3:0] rw rw rw rw SWS[1:0] rw r r SW[1:0] rw rw Bit 31 Reserved, must be kept at reset value. Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler These bits are set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. 000: MCO is divided by 1 001: MCO is divided by 2 010: MCO is divided by 4 011: MCO is divided by 8 100: MCO is divided by 16 Others: not allowed Bits 27:24 MCOSEL[3:0]: Microcontroller clock output Set and cleared by software. 0000: MCO output disabled, no clock on MCO 0001: SYSCLK system clock selected 0010: MSI clock selected. 0011: HSI16 clock selected. 0100: HSE clock selected 0101: Main PLL clock selected 0110: LSI clock selected 0111: LSE clock selected 1000: Internal HSI48 clock selected Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Bits 23:16 Reserved, must be kept at reset value. Bit 15 STOPWUCK: Wakeup from Stop and CSS backup clock selection Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the Clock Security System on HSE. Warning: STOPWUCK must not be modified when the Clock Security System is enabled by HSECSSON in RCC_CR register and the system clock is HSE (SWS=”10”) or a switch on HSE is requested (SW=”10”). 0: MSI oscillator selected as wakeup from stop clock and CSS backup clock. 1: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock Bit 14 Reserved, must be kept at reset value. Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2) Set and cleared by software to control the division factor of the APB2 clock (PCLK2). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 RM0394 Rev 4 197/1600 246 Reset and clock control (RCC) RM0394 Bits 10:8 PPRE1[2:0]:APB low-speed prescaler (APB1) Set and cleared by software to control the division factor of the APB1 clock (PCLK1). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Bits 7:4 HPRE[3:0]: AHB prescaler Set and cleared by software to control the division factor of the AHB clock. Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details please refer to Section 5.1.7: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account. 0xxx: SYSCLK not divided 1000: SYSCLK divided by 2 1001: SYSCLK divided by 4 1010: SYSCLK divided by 8 1011: SYSCLK divided by 16 1100: SYSCLK divided by 64 1101: SYSCLK divided by 128 1110: SYSCLK divided by 256 1111: SYSCLK divided by 512 Bits 3:2 SWS[1:0]: System clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. 00: MSI oscillator used as system clock 01: HSI16 oscillator used as system clock 10: HSE used as system clock 11: PLL used as system clock Bits 1:0 SW[1:0]: System clock switch Set and cleared by software to select system clock source (SYSCLK). Configured by HW to force MSI oscillator selection when exiting Standby or Shutdown mode. Configured by HW to force MSI or HSI16 oscillator selection when exiting Stop mode or in case of failure of the HSE oscillator, depending on STOPWUCK value. 00: MSI selected as system clock 01: HSI16 selected as system clock 10: HSE selected as system clock 11: PLL selected as system clock 6.4.4 PLL configuration register (RCC_PLLCFGR) Address offset: 0x0C Reset value: 0x0000 1000 Access: no wait state, word, half-word and byte access This register is used to configure the PLL clock outputs according to the formulas: • f(VCO clock) = f(PLL clock input) × (PLLN / PLLM) 198/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) • f(PLL_P) = f(VCO clock) / PLLP • f(PLL_Q) = f(VCO clock) / PLLQ • f(PLL_R) = f(VCO clock) / PLLR 31 30 29 28 27 PLLPDIV[4:0] 26 25 PLLR[1:0] 24 PLL REN rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 Res. PLLN[7:0] rw rw rw rw 23 Res. 7 22 PLLQ[1:0] rw rw 20 PLL QEN rw rw rw 6 5 4 Res. rw 21 PLLM[2:0] rw rw rw 19 18 Res. Res. 3 2 Res. Res. 17 16 PLLP PLL PEN rw rw 1 0 PLLSRC[1:0] rw rw Bits 31:27 PLLPDIV[4:0]: Main PLL division factor for PLLSAI2CLK Set and cleared by software to control the SAI1 clock frequency. PLLSAICLK output clock frequency = VCO frequency / PLLPDIV. 00000: PLLSAICLK is controlled by the bit PLLP 00001: Reserved. 00010: PLLSAICLK = VCO / 2 .... 11111: PLLSAICLK = VCO / 31 Bits 26:25 PLLR[1:0]: Main PLL division factor for PLLCLK (system clock) Set and cleared by software to control the frequency of the main PLL output clock PLLCLK. This output can be selected as system clock. These bits can be written only if PLL is disabled. PLLCLK output clock frequency = VCO frequency / PLLR with PLLR = 2, 4, 6, or 8 00: PLLR = 2 01: PLLR = 4 10: PLLR = 6 11: PLLR = 8 Caution: The software has to set these bits correctly not to exceed 80 MHz on this domain. Bit 24 PLLREN: Main PLL PLLCLK output enable Set and reset by software to enable the PLLCLK output of the main PLL (used as system clock). This bit cannot be written when PLLCLK output of the PLL is used as System Clock. In order to save power, when the PLLCLK output of the PLL is not used, the value of PLLREN should be 0. 0: PLLCLK output disable 1: PLLCLK output enable Bit 23 Reserved, must be kept at reset value. RM0394 Rev 4 199/1600 246 Reset and clock control (RCC) RM0394 Bits 22:21 PLLQ[1:0]: Main PLL division factor for PLL48M1CLK (48 MHz clock). Set and cleared by software to control the frequency of the main PLL output clock PLL48M1CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These bits can be written only if PLL is disabled. PLL48M1CLK output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 4, 6, or 8 00: PLLQ = 2 01: PLLQ = 4 10: PLLQ = 6 11: PLLQ = 8 Caution: The software has to set these bits correctly not to exceed 80 MHz on this domain. Bit 20 PLLQEN: Main PLL PLL48M1CLK output enable Set and reset by software to enable the PLL48M1CLK output of the main PLL. In order to save power, when the PLL48M1CLK output of the PLL is not used, the value of PLLQEN should be 0. 0: PLL48M1CLK output disable 1: PLL48M1CLK output enable Bits 19:18 Reserved, must be kept at reset value. Bit 17 PLLP: Main PLL division factor for PLLSAICLK (SAI1 clock). Set and cleared by software to control the frequency of the main PLL output clock PLLSAICLK. This output can be selected for SAI1. These bits can be written only if PLL is disabled. When the PLLPDIV[4:0] is set to “00000”PLLSAICLK output clock frequency = VCO frequency / PLLP with PLLP =7, or 17 0: PLLP = 7 1: PLLP = 17 Caution: The software has to set these bits correctly not to exceed 80 MHz on this domain. Bit 16 PLLPEN: Main PLL PLLSAICLK output enable Set and reset by software to enable the PLLSAICLK output of the main PLL. In order to save power, when the PLLSAICLK output of the PLL is not used, the value of PLLPEN should be 0. 0: PLLSAICLK output disable 1: PLLSAICLK output enable Bit 15 Reserved, must be kept at reset value. 200/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) Bits 14:8 PLLN[6:0]: Main PLL multiplication factor for VCO Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled. VCO output frequency = VCO input frequency x PLLN with 8 =< PLLN =< 86 0000000: PLLN = 0 wrong configuration 0000001: PLLN = 1 wrong configuration ... 0000111: PLLN = 7 wrong configuration 0001000: PLLN = 8 0001001: PLLN = 9 ... 1010101: PLLN = 85 1010110: PLLN = 86 1010111: PLLN = 87 wrong configuration ... 1111111: PLLN = 127 wrong configuration Caution: The software has to set correctly these bits to assure that the VCO output frequency is between 64 and 344 MHz. Bit 7 Reserved, must be kept at reset value. Bits 6:4 PLLM: Division factor for the main PLL and audio PLL (PLLSAI1) input clock Set and cleared by software to divide the PLL PLLSAI1 input clock before the VCO. These bits can be written only when all PLLs are disabled. VCO input frequency = PLL input clock frequency / PLLM with 1 <= PLLM <= 8 000: PLLM = 1 001: PLLM = 2 010: PLLM = 3 011: PLLM = 4 100: PLLM = 5 101: PLLM = 6 110: PLLM = 7 111: PLLM = 8 Caution: The software has to set these bits correctly to ensure that the VCO input frequency ranges from 4 to 16 MHz. Bits 3:2 Reserved, must be kept at reset value. Bits 1:0 PLLSRC: Main PLL PLLSAI1 entry clock source Set and cleared by software to select PLL PLLSAI1 clock source. These bits can be written only when PLL PLLSAI1 are disabled. In order to save power, when no PLL is used, the value of PLLSRC should be 00. 00: No clock sent to PLL PLLSAI1 01: MSI clock selected as PLL PLLSAI1 clock entry 10: HSI16 clock selected as PLL PLLSAI1 clock entry 11: HSE clock selected as PLL PLLSAI1 clock entry 6.4.5 PLLSAI1 configuration register (RCC_PLLSAI1CFGR)(a) Address offset: 0x10 Reset value: 0x0000 1000 Access: no wait state, word, half-word and byte access RM0394 Rev 4 201/1600 246 Reset and clock control (RCC) RM0394 This register is used to configure the PLLSAI1 clock outputs according to the formulas: • f(VCOSAI1 clock) = f(PLL clock input) × (PLLSAI1N / PLLM) • f(PLLSAI1_P) = f(VCOSAI1 clock) / PLLSAI1P • f(PLLSAI1_Q) = f(VCOSAI1 clock) / PLLSAI1Q • f(PLLSAI1_R) = f(VCOSAI1 clock) / PLLSAI1R 31 30 29 28 27 PLLSAI1PDIV[4:0] 26 25 PLLSAI1R[1:0] 24 PLL SAI1 REN rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 Res. PLLSAI1N[6:0] rw rw rw rw rw rw 23 Res. 22 21 PLLSAI1Q[1:0] 20 PLL SAI1 QEN 19 18 Res. Res. 17 16 PLL SAI1P PLL SAI1 PEN rw rw rw rw rw 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:27 PLLSAI1PDIV[4:0]: PLLSAI1 division factor for PLLSAI1CLK Set and cleared by software to control the SAI1 clock frequency. PLLSAI1CLK output clock frequency = VCOSAI1 frequency / PLLPDIV. 00000: PLLSAI1CLK is controlled by the bit PLLP 00001: Reserved. 00010: PLLSAI1CLK = VCOSAI1 / 2 .... 11111: PLLSAI1CLK = VCOSAI1 / 31 Bits 26:25 PLLSAI1R[1:0]: PLLSAI1 division factor for PLLADC1CLK (ADC clock) Set and cleared by software to control the frequency of the PLLSAI1 output clock PLLADC1CLK. This output can be selected as ADC clock. These bits can be written only if PLLSAI1 is disabled. PLLADC1CLK output clock frequency = VCOSAI1 frequency / PLLSAI1R with PLLSAI1R = 2, 4, 6, or 8 00: PLLSAI1R = 2 01: PLLSAI1R = 4 10: PLLSAI1R = 6 11: PLLSAI1R = 8 Bit 24 PLLSAI1REN: PLLSAI1 PLLADC1CLK output enable Set and reset by software to enable the PLLADC1CLK output of the PLLSAI1 (used as clock for ADC). In order to save power, when the PLLADC1CLK output of the PLLSAI1 is not used, the value of PLLSAI1REN should be 0. 0: PLLADC1CLK output disable 1: PLLADC1CLK output enable Bit 23 Reserved, must be kept at reset value. a. Not available on STM3L41xxx and STM32L42xxx devices. 202/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) Bits 22:21 PLLSAI1Q[1:0]: PLLSAI1 division factor for PLL48M2CLK (48 MHz clock) Set and cleared by software to control the frequency of the PLLSAI1 output clock PLL48M2CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These bits can be written only if PLLSAI1 is disabled. PLL48M2CLK output clock frequency = VCOSAI1 frequency / PLLQ with PLLQ = 2, 4, 6, or 8 00: PLLQ = 2 01: PLLQ = 4 10: PLLQ = 6 11: PLLQ = 8 Caution: The software has to set these bits correctly not to exceed 80 MHz on this domain. Bit 20 PLLSAI1QEN: PLLSAI1 PLL48M2CLK output enable Set and reset by software to enable the PLL48M2CLK output of the PLLSAI1. In order to save power, when the PLL48M2CLK output of the PLLSAI1 is not used, the value of PLLSAI1QEN should be 0. 0: PLL48M2CLK output disable 1: PLL48M2CLK output enable Bits 19:18 Reserved, must be kept at reset value. Bit 17 PLLSAI1P: PLLSAI1 division factor for PLLSAI1CLK (SAI1 clock). Set and cleared by software to control the frequency of the PLLSAI1 output clock PLLSAI1CLK. This output can be selected for SAI1. These bits can be written only if PLLSAI1 is disabled. When the PLLSAI1PDIV[4:0] is set to “00000”,PLLSAI1CLK output clock frequency = VCOSAI1 frequency / PLLSAI1P with PLLSAI1P =7, or 17 0: PLLSAI1P = 7 1: PLLSAI1P = 17 Bit 16 PLLSAI1PEN: PLLSAI1 PLLSAI1CLK output enable Set and reset by software to enable the PLLSAI1CLK output of the PLLSAI1. In order to save power, when the PLLSAI1CLK output of the PLLSAI1 is not used, the value of PLLSAI1PEN should be 0. 0: PLLSAI1CLK output disable 1: PLLSAI1CLK output enable RM0394 Rev 4 203/1600 246 Reset and clock control (RCC) RM0394 Bit 15 Reserved, must be kept at reset value. Bits 14:8 PLLSAI1N[6:0]: PLLSAI1 multiplication factor for VCO Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLLSAI1 is disabled. VCOSAI1 output frequency = VCOSAI1 input frequency x PLLSAI1N with 8 =< PLLSAI1N =< 86 0000000: PLLSAI1N = 0 wrong configuration 0000001: PLLSAI1N = 1 wrong configuration ... 0000111: PLLSAI1N = 7 wrong configuration 0001000: PLLSAI1N = 8 0001001: PLLSAI1N = 9 ... 1010101: PLLSAI1N = 85 1010110: PLLSAI1N = 86 1010111: PLLSAI1N = 87 wrong configuration ... 1111111: PLLSAI1N = 127 wrong configuration Caution: The software has to set correctly these bits to ensure that the VCO output frequency is between 64 and 344 MHz. Bits 7:0 Reserved, must be kept at reset value. 6.4.6 Clock interrupt enable register (RCC_CIER) Address offset: 0x18 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. PLL SAI1 RDYIE PLL RDYIE HSE RDYIE HSI RDYIE MSI RDYIE LSE RDYIE LSI RDYIE rw rw rw rw rw rw Res. Res. Res. Res. Res. HSI48 RDYIE LSE CSSIE rw rw Res. (1) rw 1. Not available on STM3L41xxx and STM32L42xxx devices 204/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) Bits 31:11 Reserved, must be kept at reset value. Bit 10 HSI48RDYIE: HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator. 0: HSI48 ready interrupt disabled 1: HSI48 ready interrupt enabled Bit 9 LSECSSIE: LSE clock security system interrupt enable Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE. 0: Clock security interrupt caused by LSE clock failure disabled 1: Clock security interrupt caused by LSE clock failure enabled Bits 8:7 Reserved, must be kept at reset value. Bit 6 PLLSAI1RDYIE: PLLSAI1 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLSAI1L lock. 0: PLLSAI1 lock interrupt disabled 1: PLLSAI1 lock interrupt enabled Bit 5 PLLRDYIE: PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock. 0: PLL lock interrupt disabled 1: PLL lock interrupt enabled Bit 4 HSERDYIE: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. 0: HSE ready interrupt disabled 1: HSE ready interrupt enabled Bit 3 HSIRDYIE: HSI16 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization. 0: HSI16 ready interrupt disabled 1: HSI16 ready interrupt enabled Bit 2 MSIRDYIE: MSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization. 0: MSI ready interrupt disabled 1: MSI ready interrupt enabled Bit 1 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. 0: LSE ready interrupt disabled 1: LSE ready interrupt enabled Bit 0 LSIRDYIE: LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization. 0: LSI ready interrupt disabled 1: LSI ready interrupt enabled RM0394 Rev 4 205/1600 246 Reset and clock control (RCC) 6.4.7 RM0394 Clock interrupt flag register (RCC_CIFR) Address offset: 0x1C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. PLLSAI 1RDYF (1) PLL RDYF HSE RDYF HSI RDYF MSI RDYF LSE RDYF LSI RDYF r r r r r r r Res. Res. Res. Res. Res. HSI48 RDYF LSE CSSF CSSF r r 1. Not available on STM3L41xxx and STM32L42xxx devices Bits 31:11 Reserved, must be kept at reset value. Bit 10 HSI48RDYF: HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to Clock recovery RC register (RCC_CRRCR)). Cleared by software setting the HSI48RDYC bit. 0: No clock ready interrupt caused by the HSI48 oscillator 1: Clock ready interrupt caused by the HSI48 oscillator Bit 9 LSECSSF: LSE Clock security system interrupt flag Set by hardware when a failure is detected in the LSE oscillator. Cleared by software setting the LSECSSC bit. 0: No clock security interrupt caused by LSE clock failure 1: Clock security interrupt caused by LSE clock failure Bit 8 CSSF: Clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit. 0: No clock security interrupt caused by HSE clock failure 1: Clock security interrupt caused by HSE clock failure Bit 7 Reserved, must be kept at reset value. Bit 6 PLLSAI1RDYF: PLLSAI1 ready interrupt flag Set by hardware when the PLLSAI1 locks and PLLSAI1RDYDIE is set. Cleared by software setting the PLLSAI1RDYC bit. 0: No clock ready interrupt caused by PLLSAI1 lock 1: Clock ready interrupt caused by PLLSAI1 lock Bit 5 PLLRDYF: PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYDIE is set. Cleared by software setting the PLLRDYC bit. 0: No clock ready interrupt caused by PLL lock 1: Clock ready interrupt caused by PLL lock 206/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) Bit 4 HSERDYF: HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYDIE is set. Cleared by software setting the HSERDYC bit. 0: No clock ready interrupt caused by the HSE oscillator 1: Clock ready interrupt caused by the HSE oscillator Bit 3 HSIRDYF: HSI16 ready interrupt flag Set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit. 0: No clock ready interrupt caused by the HSI16 oscillator 1: Clock ready interrupt caused by the HSI16 oscillator Bit 2 MSIRDYF: MSI ready interrupt flag Set by hardware when the MSI clock becomes stable and MSIRDYDIE is set. Cleared by software setting the MSIRDYC bit. 0: No clock ready interrupt caused by the MSI oscillator 1: Clock ready interrupt caused by the MSI oscillator Bit 1 LSERDYF: LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. 0: No clock ready interrupt caused by the LSE oscillator 1: Clock ready interrupt caused by the LSE oscillator Bit 0 LSIRDYF: LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. 0: No clock ready interrupt caused by the LSI oscillator 1: Clock ready interrupt caused by the LSI oscillator 6.4.8 Clock interrupt clear register (RCC_CICR) Address offset: 0x20 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. PLL SAI1 RDYC PLL RDYC HSE RDYC HSI RDYC MSI RDYC LSE RDYC LSI RDYC w w w w w w Res. Res. Res. Res. Res. HSI48 RDYC LSE CSSC CSSC w w (1) w 1. Not available on STM3L41xxx and STM32L42xxx devices RM0394 Rev 4 207/1600 246 Reset and clock control (RCC) RM0394 Bits 31:11 Reserved, must be kept at reset value. Bit 10 HSI48RDYC: HSI48 oscillator ready interrupt clear This bit is set by software to clear the HSI48RDYF flag. 0: No effect 1: Clear the HSI48RDYC flag Bit 9 LSECSSC: LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag. 0: No effect 1: Clear LSECSSF flag Bit 8 CSSC: Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 0: No effect 1: Clear CSSF flag Bit 7 Reserved, must be kept at reset value. Bit 6 PLLSAI1RDYC: PLLSAI1 ready interrupt clear This bit is set by software to clear the PLLSAI1RDYF flag. 0: No effect 1: Clear PLLSAI1RDYF flag Bit 5 PLLRDYC: PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag. 0: No effect 1: Clear PLLRDYF flag Bit 4 HSERDYC: HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. 0: No effect 1: Clear HSERDYF flag Bit 3 HSIRDYC: HSI16 ready interrupt clear This bit is set software to clear the HSIRDYF flag. 0: No effect 1: Clear HSIRDYF flag Bit 2 MSIRDYC: MSI ready interrupt clear This bit is set by software to clear the MSIRDYF flag. 0: No effect 1: MSIRDYF cleared Bit 1 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 0: No effect 1: LSERDYF cleared Bit 0 LSIRDYC: LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. 0: No effect 1: LSIRDYF cleared 6.4.9 AHB1 peripheral reset register (RCC_AHB1RSTR) Address offset: 0x28 208/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSC RST 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. CRC RST Res. Res. Res. FLASH RST Res. Res. Res. Res. Res. Res. DMA2 RST DMA1 RST rw rw rw rw rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 TSCRST: Touch Sensing Controller reset Set and cleared by software. 0: No effect 1: Reset TSC Bits 15:13 Reserved, must be kept at reset value. Bit 12 CRCRST: CRC reset Set and cleared by software. 0: No effect 1: Reset CRC Bits 11:9 Reserved, must be kept at reset value. Bit 8 FLASHRST: Flash memory interface reset Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode. 0: No effect 1: Reset Flash memory interface Bits 7:2 Reserved, must be kept at reset value. Bit 1 DMA2RST: DMA2 reset Set and cleared by software. 0: No effect 1: Reset DMA2 Bit 0 DMA1RST: DMA1 reset Set and cleared by software. 0: No effect 1: Reset DMA1 6.4.10 AHB2 peripheral reset register (RCC_AHB2RSTR) Address offset: 0x2C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access RM0394 Rev 4 209/1600 246 Reset and clock control (RCC) RM0394 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RNG RST Res. rw 15 Res. 14 13 Res. ADC RST 12 Res. rw rw 11 Res. 10 Res. 9 Res. 8 7 Res. GPIOH RST 6 Res. rw 5 Res. 4 rw 2. Not available on STM32L41xxx, STM32L42xxx, STM32L432xx and STM32L442xx devices. Bit 18 RNGRST: Random number generator reset Set and cleared by software. 0: No effect 1: Reset RNG Bit 17 Reserved, must be kept at reset value. Bit 16 AESRST: AES hardware accelerator reset Set and cleared by software. 0: No effect 1: Reset AES Bits 15:14 Reserved, must be kept at reset value. Bit 13 ADCRST: ADC reset Set and cleared by software. 0: No effect 1: Reset ADC interface Bits 12:8 Reserved, must be kept at reset value. Bit 7 GPIOHRST: IO port H reset Set and cleared by software. 0: No effect 1: Reset IO port H Bits 6:5 Reserved, must be kept at reset value. Bit 4 GPIOERST: IO port E reset Set and cleared by software. 0: No effect 1: Reset IO port E Bit 3 GPIODRST: IO port D reset Set and cleared by software. 0: No effect 1: Reset IO port D 210/1600 RM0394 Rev 4 2 AES RST(1) rw 1 0 GPIOE GPIOD GPIOC GPIOB GPIOA RST RST RST RST(2) RST(2) 1. Available on STM32L42xxx, STM32L44xxx and STM32L46xxx devices only. Bits 31:19 Reserved, must be kept at reset value. 3 16 rw rw rw rw RM0394 Reset and clock control (RCC) Bit 2 GPIOCRST: IO port C reset Set and cleared by software. 0: No effect 1: Reset IO port C Bit 1 GPIOBRST: IO port B reset Set and cleared by software. 0: No effect 1: Reset IO port B Bit 0 GPIOARST: IO port A reset Set and cleared by software. 0: No effect 1: Reset IO port A 6.4.11 AHB3 peripheral reset register (RCC_AHB3RSTR) Address offset: 0x30 Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. QSPI RST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:9 Reserved, must be kept at reset value. Bit 8 QSPIRST: QUADSPI1 memory interface reset Set and cleared by software. 0: No effect 1: Reset QUADSPI Bits 7:0 Reserved, must be kept at reset value. 6.4.12 APB1 peripheral reset register 1 (RCC_APB1RSTR1) Address offset: 0x38 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access RM0394 Rev 4 211/1600 246 Reset and clock control (RCC) 31 30 29 LPTIM1 OPAMP DAC1 RST RST RST(1) rw 28 27 PWR RST Res. rw rw rw 15 14 13 12 SPI3 RST(1) SPI2 RST rw rw Res. Res. 11 Res. RM0394 26 25 USBFS CAN1 RST(2) RST(1) rw rw 10 9 Res. LCD RST(5) 24 23 22 21 20 I2C2 RST(3) I2C1 RST Res. rw rw rw 7 6 CRSRS I2C3R T ST 8 Res. Res. rw 1. Not available on STM3L41xxx and STM32L42xxx devices 2. Available on STM32L4x2xx and STM32L4x3xx devices only. 3. Not available on STM32L432xx and STM32L442xx devices. 4. Available on STM32L45xxx and STM32L46xxx devices only. 5. Available on STM32L4x3xx devices only. 6. Available on STM32L43xxx and STM32L44xxx devices only. Bit 31 LPTIM1RST: Low Power Timer 1 reset Set and cleared by software. 0: No effect 1: Reset LPTIM1 Bit 30 OPAMPRST: OPAMP interface reset Set and cleared by software. 0: No effect 1: Reset OPAMP interface Bit 29 DAC1RST: DAC1 interface reset Set and cleared by software. 0: No effect 1: Reset DAC1 interface Bit 28 PWRRST: Power interface reset Set and cleared by software. 0: No effect 1: Reset PWR Bit 27 Reserved, must be kept at reset value. Bit 26 USBFSRST: USB FS reset Set and cleared by software. 0: No effect 1: Reset the USB FS Bit 25 CAN1RST: CAN1 reset Set and reset by software. 0: No effect 1: Reset the CAN1 Bit 24 CRSRST: CRS reset Set and cleared by software. 0: No effect 1: Reset the CRS 212/1600 RM0394 Rev 4 Res. 5 4 TIM7 RST(6) TIM6 RST rw rw 19 18 17 UART4 USART3 USART2 RST RST(4) RST(3) rw rw 3 2 Res. Res. 16 Res. rw 1 0 TIM3 RST(4) TIM2 RST rw rw RM0394 Reset and clock control (RCC) Bit 23 I2C3RST: I2C3 reset Set and reset by software. 0: No effect 1: Reset I2C3 Bit 22 I2C2RST: I2C2 reset Set and cleared by software. 0: No effect 1: Reset I2C2 Bit 21 I2C1RST: I2C1 reset Set and cleared by software. 0: No effect 1: Reset I2C1 Bit 20 Reserved, must be kept at reset value. Bit 19 UART4RST: UART4 reset Set and cleared by software. 0: No effect 1: Reset UART4 Bit 18 USART3RST: USART3 reset Set and cleared by software. 0: No effect 1: Reset USART3 Bit 17 USART2RST: USART2 reset Set and cleared by software. 0: No effect 1: Reset USART2 Bit 16 Reserved, must be kept at reset value. Bit 15 SPI3RST: SPI3 reset Set and cleared by software. 0: No effect 1: Reset SPI3 Bit 14 SPI2RST: SPI2 reset Set and cleared by software. 0: No effect 1: Reset SPI2 Bits 13:10 Reserved, must be kept at reset value. Bit 9 LCDRST: LCD interface reset Set and cleared by software. 0: No effect 1: Reset LCD Bits 8:6 Reserved, must be kept at reset value. Bit 5 TIM7RST: TIM7 timer reset Set and cleared by software. 0: No effect 1: Reset TIM7 RM0394 Rev 4 213/1600 246 Reset and clock control (RCC) RM0394 Bit 4 TIM6RST: TIM6 timer reset Set and cleared by software. 0: No effect 1: Reset TIM6 Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM3RST: TIM3 timer reset Set and cleared by software. 0: No effect 1: Reset TIM3 Bit 0 TIM2RST: TIM2 timer reset Set and cleared by software. 0: No effect 1: Reset TIM2 6.4.13 APB1 peripheral reset register 2 (RCC_APB1RSTR2) Address offset: 0x3C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPTIM2 RST Res. Res. SWP MI1 RST(1) I2C4 RST (2) LP UART1 RST rw rw rw rw 1. Not available on STM32L41xxx and STM32L42xxx devices. 2. Available on STM32L45xxx and STM32L46xxx devices only. Bits 31:6 Reserved, must be kept at reset value. Bit 5 LPTIM2RST: Low-power timer 2 reset Set and cleared by software. 0: No effect 1: Reset LPTIM2 Bits 4:3 Reserved, must be kept at reset value. 214/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) Bit 2 SWPMI1RST: Single wire protocol reset Set and cleared by software. 0: No effect 1: Reset SWPMI1 Bit 1 I2C4RST: I2C4 reset Set and cleared by software 0: No effect 1: Reset I2C4 Bit 0 LPUART1RST: Low-power UART 1 reset Set and cleared by software. 0: No effect 1: Reset LPUART1 6.4.14 APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x40 Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 :Res. 25 24 23 22 21 20 19 18 17 16 Res. DFSD M1 RST(1) Res. Res. SAI1 RST(2) Res. Res. Res. TIM16 RST TIM15 RST rw rw rw 15 14 Res. USART 1 RST rw 13 Res. 12 11 10 SPI1 RST TIM1 RST SD MMC1 RST(3) rw rw rw 9 Res. rw 8 Res. 7 Res. 6 Res. 5 Res. 4 Res. 3 Res. 2 Res. 1 0 Res. SYS CFG RST rw 1. Available on STM32L45xxx and STM32L46xxx devices only. 2. Not available on STM3L41xxx and STM32L42xxx devices. 3. Not available on STM3L41xxx and STM32L42xxx, STM32L432 and STM32L442 devices. Bits 31:25 Reserved, must be kept at reset value. Bit 24 DFSDM1RST: Digital filters for sigma-delta modulators (DFSDM1) reset Set and cleared by software. 0: No effect 1: Reset DFSDM1 Bit 23 Reserved, must be kept at reset value. Bit 21 SAI1RST: Serial audio interface 1 (SAI1) reset Set and cleared by software. 0: No effect 1: Reset SAI1 Bits 20:18 Reserved, must be kept at reset value. RM0394 Rev 4 215/1600 246 Reset and clock control (RCC) RM0394 Bit 17 TIM16RST: TIM16 timer reset Set and cleared by software. 0: No effect 1: Reset TIM16 timer Bit 16 TIM15RST: TIM15 timer reset Set and cleared by software. 0: No effect 1: Reset TIM15 timer Bit 15 Reserved, must be kept at reset value. Bit 14 USART1RST: USART1 reset Set and cleared by software. 0: No effect 1: Reset USART1 Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1RST: SPI1 reset Set and cleared by software. 0: No effect 1: Reset SPI1 Bit 11 TIM1RST: TIM1 timer reset Set and cleared by software. 0: No effect 1: Reset TIM1 timer Bit 10 SDMMC1RST: SDMMC reset Set and cleared by software. 0: No effect 1: Reset SDMMC Bits 9:1 Reserved, must be kept at reset value. Bit 0 SYSCFGRST: SYSCFG + COMP + VREFBUF reset 0: No effect 1: Reset SYSCFG + COMP + VREFBUF 6.4.15 AHB1 peripheral clock enable register (RCC_AHB1ENR) Address offset: 0x48 Reset value: 0x0000 0100 Access: no wait state, word, half-word and byte access Note: 216/1600 When the peripheral clock is not active, the peripheral registers read or write access is not supported. RM0394 Rev 4 RM0394 Reset and clock control (RCC) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSC EN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. CRCEN Res. Res. Res. FLASH EN Res. Res. Res. Res. Res. Res. DMA2 EN DMA1 EN rw rw rw rw rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 TSCEN: Touch Sensing Controller clock enable Set and cleared by software. 0: TSC clock disable 1: TSC clock enable Bits 15:13 Reserved, must be kept at reset value. Bit 12 CRCEN: CRC clock enable Set and cleared by software. 0: CRC clock disable 1: CRC clock enable Bits 11:9 Reserved, must be kept at reset value. Bit 8 FLASHEN: Flash memory interface clock enable Set and cleared by software. This bit can be disabled only when the Flash is in power down mode. 0: Flash memory interface clock disable 1: Flash memory interface clock enable Bits 7:2 Reserved, must be kept at reset value. Bit 1 DMA2EN: DMA2 clock enable Set and cleared by software. 0: DMA2 clock disable 1: DMA2 clock enable Bit 0 DMA1EN: DMA1 clock enable Set and cleared by software. 0: DMA1 clock disable 1: DMA1 clock enable RM0394 Rev 4 217/1600 246 Reset and clock control (RCC) 6.4.16 RM0394 AHB2 peripheral clock enable register (RCC_AHB2ENR) Address offset: 0x4C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported. 31 Res. 30 29 Res. Res. 28 Res. 27 Res. 26 Res. 25 24 Res. Res. 23 Res. 22 Res. 21 Res. 20 Res. 19 18 Res. RNG EN 17 res. rw 15 Res. 14 res. 13 ADCEN 12 res. 11 Res. 10 Res. 9 Res. 8 7 res. GPIOH EN rw 6 res. rw 1. Available on STM32L42xxx, STM32L44xxx and STM32L46xxx devices only. Bits 31:19 Reserved, must be kept at reset value. Bit 18 RNGEN: Random Number Generator clock enable Set and cleared by software. 0: Random Number Generator clock disabled 1: Random Number Generator clock enabled Bit 17 Reserved, must be kept at reset value. Bit 16 AESEN: AES accelerator clock enable Set and cleared by software. 0: AES clock disabled 1: AES clock enabled Bits 15:14 Reserved, must be kept at reset value. Bit 13 ADCEN: ADC clock enable Set and cleared by software. 0: ADC clock disabled 1: ADC clock enabled Bits 12:8 Reserved, must be kept at reset value. Bit 7 GPIOHEN: IO port H clock enable Set and cleared by software. 0: IO port H clock disabled 1: IO port H clock enabled Bits 6:5 Reserved, must be kept at reset value. Bit 4 GPIOEEN: IO port E clock enable Set and cleared by software. 0: IO port E clock disabled 1: IO port E clock enabled 218/1600 RM0394 Rev 4 5 res. 4 3 2 16 AESEN (1) rw 1 0 GPIOE GPIOD GPIOC GPIOB GPIOA EN EN EN EN EN rw rw rw rw rw RM0394 Reset and clock control (RCC) Bit 3 GPIODEN: IO port D clock enable Set and cleared by software. 0: IO port D clock disabled 1: IO port D clock enabled Bit 2 GPIOCEN: IO port C clock enable Set and cleared by software. 0: IO port C clock disabled 1: IO port C clock enabled Bit 1 GPIOBEN: IO port B clock enable Set and cleared by software. 0: IO port B clock disabled 1: IO port B clock enabled Bit 0 GPIOAEN: IO port A clock enable Set and cleared by software. 0: IO port A clock disabled 1: IO port A clock enabled 6.4.17 AHB3 peripheral clock enable register(RCC_AHB3ENR) Address offset: 0x50 Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. QSPI EN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:9 Reserved, must be kept at reset value. Bit 8 QSPIEN: Quad SPI memory interface clock enable Set and cleared by software. 0: QUADSPI clock disable 1: QUADSPI clock enable Bits 7:0 Reserved, must be kept at reset value. RM0394 Rev 4 219/1600 246 Reset and clock control (RCC) 6.4.18 RM0394 APB1 peripheral clock enable register 1 (RCC_APB1ENR1) Address: 0x58 Reset value: 0x0000 0400 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported. 31 30 29 LPTIM1 OPAMP DAC1 EN EN EN(1) rw 28 PWR EN 27 26 Res. USB FSEN 25 24 23 22 21 20 19 (2) CAN1 EN(1) CRSEN I2C3 EN I2C2 EN(3) I2C1 EN Res. UART4 EN(4) rw rw rw rw rw rw 8 7 6 5 Res. TIM7 EN(6) TIM6EN rw rw rw rw rw 13 12 11 10 9 Res. WWD GEN RTCA PBEN LCD EN(5) rs rw rw 15 14 SPI3 EN(1) SPI2 EN(3) rw rw Res. Res. Res. 1. Not available on STM32L41xxx and STM32L42xxx devices 2. Available on STM32L4x2xx and STM32L4x3xx devices only. 3. Not available on STM32L432xx and STM32L442xx devices. 4. Available on STM32L45xxx and STM32L46xxx devices only. 5. Available on STM32L4x3xx devices only. 6. Available on STM32L43xxx and STM32L44xxx devices only. Bit 31 LPTIM1EN: Low power timer 1 clock enable Set and cleared by software. 0: LPTIM1 clock disabled 1: LPTIM1 clock enabled Bit 30 OPAMPEN: OPAMP interface clock enable Set and cleared by software. 0: OPAMP interface clock disabled 1: OPAMP interface clock enabled Bit 29 DAC1EN: DAC1 interface clock enable Set and cleared by software. 0: DAC1 interface clock disabled 1: DAC1 interface clock enabled Bit 28 PWREN: Power interface clock enable Set and cleared by software. 0: Power interface clock disabled 1: Power interface clock enabled Bit 27 Reserved, must be kept at reset value. Bit 26 USBFSEN: USB FS clock enable Set and cleared by software. 0: USB FS clock disabled 1: USB FS clock enabled 220/1600 RM0394 Rev 4 4 18 USART3 USART2 EN EN(3) rw rw 3 2 Res. 17 Res. 16 Res. rw 1 0 TIM3EN (1) TIM2 EN rw rw RM0394 Reset and clock control (RCC) Bit 25 CAN1EN: CAN1 clock enable Set and cleared by software. 0: CAN1 clock disabled 1: CAN1 clock enabled Bit 24 CRSEN: CRS clock enable Set and cleared by software. 0: CRS clock disabled 1: CRS clock enabled Bit 23 I2C3EN: I2C3 clock enable Set and cleared by software. 0: I2C3 clock disabled 1: I2C3 clock enabled Bit 22 I2C2EN: I2C2 clock enable Set and cleared by software. 0: I2C2 clock disabled 1: I2C2 clock enabled Bit 21 I2C1EN: I2C1 clock enable Set and cleared by software. 0: I2C1 clock disabled 1: I2C1 clock enabled Bit 20 Reserved, must be kept at reset value. Bit 19 UART4EN: UART4 clock enable Set and cleared by software. 0: UART4 clock disabled 1: UART4 clock enabled Bit 18 USART3EN: USART3 clock enable Set and cleared by software. 0: USART3 clock disabled 1: USART3 clock enabled Bit 17 USART2EN: USART2 clock enable Set and cleared by software. 0: USART2 clock disabled 1: USART2 clock enabled Bit 16 Reserved, must be kept at reset value. Bit 15 SPI3EN: SPI3 clock enable Set and cleared by software. 0: SPI3 clock disabled 1: SPI3 clock enabled Bit 14 SPI2EN: SPI2 clock enable Set and cleared by software. 0: SPI2 clock disabled 1: SPI2 clock enabled Bits 13:12 Reserved, must be kept at reset value. RM0394 Rev 4 221/1600 246 Reset and clock control (RCC) RM0394 Bit 11 WWDGEN: Window watchdog clock enable Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. 0: Window watchdog clock disabled 1: Window watchdog clock enabled Bit 10 RTCAPBEN: RTC APB clock enable Set and cleared by software 0: RTC APB clock disabled 1: RTC APB clock enabled Bit 9 LCDEN: LCD clock enable Set and cleared by software. 0: LCD clock disabled 1: LCD clock enabled Bits 8:6 Reserved, must be kept at reset value. Bit 5 TIM7EN: TIM7 timer clock enable Set and cleared by software. 0: TIM7 clock disabled 1: TIM7 clock enabled Bit 4 TIM6EN: TIM6 timer clock enable Set and cleared by software. 0: TIM6 clock disabled 1: TIM6 clock enabled Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM3EN: TIM3 timer clock enable Set and cleared by software. 0: TIM3 clock disabled 1: TIM3 clock enabled Bit 0 TIM2EN: TIM2 timer clock enable Set and cleared by software. 0: TIM2 clock disabled 1: TIM2 clock enabled 6.4.19 APB1 peripheral clock enable register 2 (RCC_APB1ENR2) Address offset: 0x5C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access Note: 222/1600 When the peripheral clock is not active, the peripheral registers read or write access is not supported. RM0394 Rev 4 RM0394 Reset and clock control (RCC) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. SWP MI1 I2C4EN (2) LP UART1 EN rw rw Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPTIM2 EN Res. EN (1) rw 1. Available on STM32L43xxx and STM32L44xxx devices only. 2. Available on STM32L45xxx and STM32L46xxx devices only. Bits 31:6 Reserved, must be kept at reset value. Bit 5 LPTIM2EN Low power timer 2 clock enable Set and cleared by software. 0: LPTIM2 clock disable 1: LPTIM2 clock enable Bits 4:3 Reserved, must be kept at reset value. Bit 2 SWPMI1EN: Single wire protocol clock enable Set and cleared by software. 0: SWPMI1 clock disable 1: SWPMI1 clock enable Bit 1 I2C4EN: I2C4 clock enable Set and cleared by software 0: I2C4 clock disabled 1: I2C4 clock enabled Bit 0 LPUART1EN: Low power UART 1 clock enable Set and cleared by software. 0: LPUART1 clock disable 1: LPUART1 clock enable RM0394 Rev 4 223/1600 246 Reset and clock control (RCC) 6.4.20 RM0394 APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x60 Reset value: 0x0000 0000 Access: word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported. 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 24 23 22 21 20 19 18 17 16 Res. DFSD M1 EN(1) Res. Res. SAI1 EN(2) Res. Res. Res. TIM16 EN TIM15 EN rw rw rw 15 14 Res. USART 1 EN rw 13 Res. 12 rw 11 10 9 8 7 6 5 4 3 2 1 0 SPI1 EN TIM1 EN SD MMC1 EN(3) Res. Res. FW EN Res. Res. Res. Res. Res. Res. SYS CFGEN rw rw rw rs 1. Available on STM32L45xxx and STM32L46xxx devices only. 2. Not available on STM32L41xxx/42xxx devices. 3. Not available on STM3L41xxx and STM32L42xxx, STM32L432 and STM32L442 devices. Bits 31:25 Reserved, must be kept at reset value. Bit 24 DFSDM1EN: DFSDM1 timer clock enable Set and cleared by software. 0: DFSDM1 clock disabled 1: DFSDM1 clock enabled Bits 23:22 Reserved, must be kept at reset value. Bit 21 SAI1EN: SAI1 clock enable Set and cleared by software. 0: SAI1 clock disabled 1: SAI1 clock enabled Bits 20:18 Reserved, must be kept at reset value. Bit 17 TIM16EN: TIM16 timer clock enable Set and cleared by software. 0: TIM16 timer clock disabled 1: TIM16 timer clock enabled Bit 16 TIM15EN: TIM15 timer clock enable Set and cleared by software. 0: TIM15 timer clock disabled 1: TIM15 timer clock enabled Bit 15 Reserved, must be kept at reset value. Bit 14 USART1EN: USART1clock enable Set and cleared by software. 0: USART1clock disabled 1: USART1clock enabled Bit 13 Reserved, must be kept at reset value. 224/1600 RM0394 Rev 4 rw RM0394 Reset and clock control (RCC) Bit 12 SPI1EN: SPI1 clock enable Set and cleared by software. 0: SPI1 clock disabled 1: SPI1 clock enabled Bit 11 TIM1EN: TIM1 timer clock enable Set and cleared by software. 0: TIM1 timer clock disabled 1: TIM1P timer clock enabled Bit 10 SDMMC1EN: SDMMC clock enable Set and cleared by software. 0: SDMMC clock disabled 1: SDMMC clock enabled Bits 9:8 Reserved, must be kept at reset value. Bit 7 FWEN: Firewall clock enable Set by software, reset by hardware. Software can only write 1. A write at 0 has no effect. 0: Firewall clock disabled 1: Firewall clock enabled Bits 6:1 Reserved, must be kept at reset value. Bit 0 SYSCFGEN: SYSCFG + COMP + VREFBUF clock enable Set and cleared by software. 0: SYSCFG + COMP + VREFBUF clock disabled 1: SYSCFG + COMP + VREFBUF clock enabled(1) 1. Not available on STM3L41xxx and STM32L42xxx. 6.4.21 AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR) Address offset: 0x68 Reset value: Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSC SMEN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. CRCSMEN Res. Res. Res. Res. Res. Res. Res. Res. DMA2 SMEN DMA1 SMEN rw rw rw rw SRAM1 FLASH SMEN SMEN rw rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 TSCSMEN: Touch Sensing Controller clocks enable during Sleep and Stop modes Set and cleared by software. 0: TSC clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TSC clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 15:13 Reserved, must be kept at reset value. RM0394 Rev 4 225/1600 246 Reset and clock control (RCC) RM0394 Bit 12 CRCSMEN: CRC clocks enable during Sleep and Stop modes Set and cleared by software. 0: CRC clocks disabled by the clock gating(1) during Sleep and Stop modes 1: CRC clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 11:10 Reserved, must be kept at reset value. Bit 9 SRAM1SMEN: SRAM1 interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: SRAM1 interface clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SRAM1 interface clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 8 FLASHSMEN: Flash memory interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: Flash memory interface clocks disabled by the clock gating(1) during Sleep and Stop modes 1: Flash memory interface clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 7:2 Reserved, must be kept at reset value. Bit 1 DMA2SMEN: DMA2 clocks enable during Sleep and Stop modes Set and cleared by software during Sleep mode. 0: DMA2 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: DMA2 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 0 DMA1SMEN: DMA1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: DMA1 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: DMA1 clocks enabled by the clock gating(1) during Sleep and Stop modes 1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode. 6.4.22 AHB2 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB2SMENR) Address offset: 0x6C Reset value: 0x0005 229F Access: no wait state, word, half-word and byte access 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 Res. 24 Res. 23 Res. 22 Res. 21 Res. 20 Res. 19 Res. 18 RNG SMEN 17 16 Res. AES SMEN (1) rw 15 14 13 12 11 10 9 8 7 6 5 Res. Res. ADC SMEN Res. Res. Res. SRAM2 SMEN Res. GPIOH SMEN Res. Res. rw rw rw 1. Available on STM32L44xxx and STM32L46xxx devices only. 2. Not available on STM32L432xx and STM32L442xx devices. 3. Not available on STM3L41xxx and STM32L42xxx. 226/1600 RM0394 Rev 4 4 3 2 rw 1 0 GPIOE SMEN GPIOD GPIOC GPIOB GPIOA SMEN SMEN SMEN SMEN (2) (3) rw rw rw rw rw RM0394 Reset and clock control (RCC) Bits 31:19 Reserved, must be kept at reset value. Bit 18 RNGSMEN: Random Number Generator clocks enable during Sleep and Stop modes Set and cleared by software. 0: Random Number Generator clocks disabled by the clock gating during Sleep and Stop modes 1: Random Number Generator clocks enabled by the clock gating during Sleep and Stop modes Bit 17 Reserved, must be kept at reset value. Bit 16 AESSMEN: AES accelerator clocks enable during Sleep and Stop modes Set and cleared by software. 0: AES clocks disabled by the clock gating(1) during Sleep and Stop modes 1: AES clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 15:14 Reserved, must be kept at reset value. Bit 13 ADCSMEN: ADC clocks enable during Sleep and Stop modes Set and cleared by software. 0: ADC clocks disabled by the clock gating(1) during Sleep and Stop modes 1: ADC clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 12:10 Reserved, must be kept at reset value. Bit 9 SRAM2SMEN: SRAM2 interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: SRAM2 interface clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SRAM2 interface clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 8 Reserved, must be kept at reset value. Bit 7 GPIOHSMEN: IO port H clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port H clocks disabled by the clock gating(1) during Sleep and Stop modes 1: IO port H clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 6:5 Reserved, must be kept at reset value. Bit 4 GPIOESMEN: IO port E clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port E clocks disabled by the clock gating(1) during Sleep and Stop modes 1: IO port E clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 3 GPIODSMEN: IO port D clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port D clocks disabled by the clock gating(1) during Sleep and Stop modes 1: IO port D clocks enabled by the clock gating(1) during Sleep and Stop modes RM0394 Rev 4 227/1600 246 Reset and clock control (RCC) RM0394 Bit 2 GPIOCSMEN: IO port C clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port C clocks disabled by the clock gating(1) during Sleep and Stop modes 1: IO port C clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 1 GPIOBSMEN: IO port B clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port B clocks disabled by the clock gating(1) during Sleep and Stop modes 1: IO port B clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 0 GPIOASMEN: IO port A clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port A clocks disabled by the clock gating(1) during Sleep and Stop modes 1: IO port A clocks enabled by the clock gating(1) during Sleep and Stop modes 6.4.23 AHB3 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB3SMENR) Address offset: 0x70 Reset value: 0x000 0100 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. QSPI SMEN Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:9 Reserved, must be kept at reset value. Bit 8 QSPISMEN Quad SPI memory interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: QUADSPI clocks disabled by the clock gating(1) during Sleep and Stop modes 1: QUADSPI clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 7:0 Reserved, must be kept at reset value. 1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode. 6.4.24 APB1 peripheral clocks enable in Sleep and Stop modes register 1 (RCC_APB1SMENR1) Address: 0x78 Reset value: 0xF7E6 CE31 Access: no wait state, word, half-word and byte access 228/1600 RM0394 Rev 4 RM0394 31 Reset and clock control (RCC) 30 29 28 DAC1 LPTIM1 OPAMP SMEN PWR SMEN SMEN SMEN (1) rw rw rw rw 15 14 13 12 (1) SPI2 SMEN Res. Res. rw rw SPI3 SMEN 27 26 25 24 23 Res. USB FSSM EN(2) CAN1 SMEN (1) CRSS MEN I2C3 SMEN 11 rw rw rw 10 9 8 LCD SMEN Res. RTCA WWDG PBSM SMEN EN rw rw (5) 22 21 20 (3) I2C1 SMEN Res. rw rw rw rw rw rw 7 6 5 4 3 2 1 Res. Res. TIM7 SMEN TIM6 SMEN Res. Res. TIM3 SMEN rw rw I2C2 SMEN rw 19 18 17 16 UART4 USART3 USART2 SMEN(4) SMEN(3) SMEN Res. 0 (1) TIM2 SMEN rw rw 1. Not available on STM3L41xxx and STM32L42xxx. 2. Available on STM32L4x2xx and STM32L4x3xx devices only. 3. Not available on STM32L432xx and STM32L442xx devices. 4. Available on STM32L45xxx and STM32L46xxx devices only. 5. Available on STM32L4x3xx devices only. Bit 31 LPTIM1SMEN: Low power timer 1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: LPTIM1 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: LPTIM1 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 30 OPAMPSMEN: OPAMP interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: OPAMP interface clocks disabled by the clock gating(1) during Sleep and Stop modes 1: OPAMP interface clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 29 DAC1SMEN: DAC1 interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: DAC1 interface clocks disabled by the clock gating(1) during Sleep and Stop modes 1: DAC1 interface clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 28 PWRSMEN: Power interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: Power interface clocks disabled by the clock gating(1) during Sleep and Stop modes 1: Power interface clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 27 Reserved, must be kept at reset value. Bit 26 USBFSSMEN: USB FS clock enable during Sleep and Stop modes Set and cleared by software. 0: USB FS clock disabled by the clock gating(1) during Sleep and Stop modes 1: USB FS clock enabled by the clock gating(1) during Sleep and Stop modes Bit 25 CAN1SMEN: CAN1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: CAN1 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: CAN1 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 24 CRSSMEN: CRS clock enable during Sleep and Stop modes Set and cleared by software. 0: CRS clocks disabled by the clock gating(1) during Sleep and Stop modes 1: CRS clocks enabled by the clock gating(1) during Sleep and Stop modes RM0394 Rev 4 229/1600 246 Reset and clock control (RCC) RM0394 Bit 23 I2C3SMEN: I2C3 clocks enable during Sleep and Stop modes Set and cleared by software. 0: I2C3 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: I2C3 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 22 I2C2SMEN: I2C2 clocks enable during Sleep and Stop modes Set and cleared by software. 0: I2C2 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: I2C2 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 21 I2C1SMEN: I2C1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: I2C1 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: I2C1 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 20 Reserved, must be kept at reset value. Bit 19 UART4SMEN: UART4 clocks enable during Sleep and Stop modes Set and cleared by software. 0: UART4 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: UART4 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 18 USART3SMEN: USART3 clocks enable during Sleep and Stop modes Set and cleared by software. 0: USART3 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: USART3 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 17 USART2SMEN: USART2 clocks enable during Sleep and Stop modes Set and cleared by software. 0: USART2 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: USART2 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 16 Reserved, must be kept at reset value. Bit 15 SPI3SMEN: SPI3 clocks enable during Sleep and Stop modes Set and cleared by software. 0: SPI3 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SPI3 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 14 SPI2SMEN: SPI2 clocks enable during Sleep and Stop modes Set and cleared by software. 0: SPI2 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SPI2 clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGSMEN: Window watchdog clocks enable during Sleep and Stop modes Set and cleared by software. This bit is forced to ‘1’ by hardware when the hardware WWDG option is activated. 0: Window watchdog clocks disabled by the clock gating(1) during Sleep and Stop modes 1: Window watchdog clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 10 RTCAPBSMEN: RTC APB clock enable during Sleep and Stop modes Set and cleared by software 0: RTC APB clock disabled by the clock gating(1) during Sleep and Stop modes 1: RTC APB clock enabled by the clock gating(1) during Sleep and Stop modes 230/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) Bit 9 LCDSMEN: LCD clocks enable during Sleep and Stop modes Set and cleared by software. 0: LCD clocks disabled by the clock gating(1) during Sleep and Stop modes 1: LCD clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 8:6 Reserved, must be kept at reset value. Bit 5 TIM7SMEN: TIM7 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM7 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM7 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 4 TIM6SMEN: TIM6 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM6 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM6 clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM3SMEN: TIM3 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM3 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM3 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 0 TIM2SMEN: TIM2 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM2 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM2 clocks enabled by the clock gating(1) during Sleep and Stop modes 1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode. 6.4.25 APB1 peripheral clocks enable in Sleep and Stop modes register 2 (RCC_APB1SMENR2) Address offset: 0x7C Reset value: 0x0000 0025 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. SWP MI1 SMEN Res. (1) LP UART1 SMEN rw rw Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPTIM 2SMEN rw Res. 1. Available on STM32L43xxx and STM32L44xxx devices only. RM0394 Rev 4 231/1600 246 Reset and clock control (RCC) RM0394 Bits 31:6 Reserved, must be kept at reset value. Bit 5 LPTIM2SMEN Low power timer 2 clocks enable during Sleep and Stop modes Set and cleared by software. 0: LPTIM2 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: LPTIM2 clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 4:3 Reserved, must be kept at reset value. Bit 2 SWPMI1SMEN: Single wire protocol clocks enable during Sleep and Stop modes Set and cleared by software. 0: SWPMI1 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SWPMI1 clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 1 Reserved, must be kept at reset value. Bit 0 LPUART1SMEN: Low power UART 1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: LPUART1 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: LPUART1 clocks enabled by the clock gating(1) during Sleep and Stop modes 1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode. 232/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) 6.4.26 APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) Address: 0x80 Reset value: 0x0235 7C01 Access: word, half-word and byte access 31 Res. 30 29 Res. Res. 28 Res. 27 Res. 26 Res. 25 Res. 24 Res. 23 Res. 22 21 20 19 18 17 16 Res. SAI1 SMEN Res. Res. Res. TIM16 SMEN TIM15 SMEN rw rw (1) rw 15 Res. 14 13 USART1 SMEN rw Res. 12 11 10 9 8 7 6 5 4 3 2 1 0 SPI1 SMEN TIM1 SMEN SD MMC1 SMEN Res. Res. Res. Res. Res. Res. Res. Res. Res. (1) SYS CFG SMEN rw rw rw rw 1. Not available on STM3L41xxx and STM32L42xxx. Bits 31:22 Reserved, must be kept at reset value. Bit 21 SAI1SMEN: SAI1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: SAI1 clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SAI1 clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 20:18 Reserved, must be kept at reset value. Bit 17 TIM16SMEN: TIM16 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM16 timer clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM16 timer clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 16 TIM15SMEN: TIM15 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM15 timer clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM15 timer clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 15 Reserved, must be kept at reset value. Bit 14 USART1SMEN: USART1clocks enable during Sleep and Stop modes Set and cleared by software. 0: USART1clocks disabled by the clock gating(1) during Sleep and Stop modes 1: USART1clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1SMEN: SPI1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: SPI1 clocks disabled by the clock gating during(1) Sleep and Stop modes 1: SPI1 clocks enabled by the clock gating during(1) Sleep and Stop modes RM0394 Rev 4 233/1600 246 Reset and clock control (RCC) RM0394 Bit 11 TIM1SMEN: TIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM1 timer clocks disabled by the clock gating(1) during Sleep and Stop modes 1: TIM1P timer clocks enabled by the clock gating(1) during Sleep and Stop modes Bit 10 SDMMC1SMEN: SDMMC clocks enable during Sleep and Stop modes Set and cleared by software. 0: SDMMC clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SDMMC clocks enabled by the clock gating(1) during Sleep and Stop modes Bits 9:1 Reserved, must be kept at reset value. Bit 0 SYSCFGSMEN: SYSCFG + COMP + VREFBUF clocks enable during Sleep and Stop modes Set and cleared by software. 0: SYSCFG + COMP + VREFBUF clocks disabled by the clock gating(1) during Sleep and Stop modes 1: SYSCFG + COMP + VREFBUF clocks enabled by the clock gating(1) during Sleep and Stop modes(2) 1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode. 2. Not available on STM3L41xxx and STM32L42xxx. 6.4.27 Peripherals independent clock configuration register (RCC_CCIPR) Address: 0x88 Reset value: 0x0000 0000 Access: no wait states, word, half-word and byte access 31 30 Res. SWP MI1 SEL 15 (1) 28 ADCSEL[1:0](2) 27 26 CLK48SEL[1:0] rw rw rw rw rw 14 13 12 11 10 I2C2SEL[1:0](3) rw 29 rw I2C1SEL[1:0] rw rw LPUART1SEL [1:0] rw 25 24 Res. Res. 9 8 Res. Res. rw 23 22 SAI1SEL[1:0] (2) 20 LPTIM2SEL[1:0] 19 18 LPTIM1SEL[1:0 17 16 I2C3SEL[1:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 UART4SEL USART3SEL [1:0](4) [1:0](3) rw 1. Available on STM32L43x and STM32L44x devices only. 2. Not available on STM3L41xxx and STM32L42xxx. 3. Not available on STM32L432xx and STM32L442xx devices. 4. Available on STM32L45xxx and STM32L46xxx devices only. 234/1600 21 RM0394 Rev 4 rw rw rw USART2SEL [1:0] rw rw USART1SEL [1:0] rw rw RM0394 Reset and clock control (RCC) Bit 31 Reserved, must be kept at reset value. Bit 30 SWPMI1SEL: SWPMI1 clock source selection This bit is set and cleared by software to select the SWPMI1 clock source. 0: APB1 (PCLK1) selected as SWPMI1 clock 1: HSI16 clock selected as SWPMI1 clock Bits 29:28 ADCSEL[1:0]: ADCs clock source selection These bits are set and cleared by software to select the clock source used by the ADC interface. 00: No clock selected 01: PLLSAI1 “R” clock (PLLADC1CLK) selected as ADCs clock(1) 11: System clock selected as ADCs clock Bits 27:26 CLK48SEL[1:0]: 48 MHz clock source selection These bits are set and cleared by software to select the 48 MHz clock source used by USB FS, RNG and SDMMC. 00: HSI48 clock selected as 48 MHz clock 01: PLLSAI1 “Q” clock (PLL48M2CLK) selected as 48 MHz clock 10: PLL “Q” clock (PLL48M1CLK) selected as 48 MHz clock 11: MSI clock selected as 48 MHz clock Bits 25:24 Reserved, must be kept at reset value. Bits 23:22 SAI1SEL[1:0]: SAI1 clock source selection(1) These bits are set and cleared by software to select the SAI1 clock source. 00: PLLSAI1 “P” clock (PLLSAI1CLK) selected as SAI1 clock 01: Reserved Note: When there is no PLL enabled, the HSI16 clock source is connected automatically to the SAI1 to allow audio detection without the need to turn on the PLL source. 10: PLL “P” clock (PLLSAI3CLK) selected as SAI1 clock 11: External input SAI1_EXTCLK selected as SAI1 clock Caution: If the selected clock is the external clock, it is not possible to switch to another clock if the external clock is not present. Bits 21:20 LPTIM2SEL[1:0]: Low power timer 2 clock source selection These bits are set and cleared by software to select the LPTIM2 clock source. 00: PCLK selected as LPTIM2 clock 01: LSI clock selected as LPTIM2 clock 10: HSI16 clock selected as LPTIM2 clock 11: LSE clock selected as LPTIM2 clock Bits 19:18 LPTIM1SEL[1:0]: Low power timer 1 clock source selection These bits are set and cleared by software to select the LPTIM1 clock source. 00: PCLK selected as LPTIM1 clock 01: LSI clock selected as LPTIM1 clock 10: HSI16 clock selected as LPTIM1 clock 11: LSE clock selected as LPTIM1 clock Bits 17:16 I2C3SEL[1:0]: I2C3 clock source selection These bits are set and cleared by software to select the I2C3 clock source. 00: PCLK selected as I2C3 clock 01: System clock (SYSCLK) selected as I2C3 clock 10: HSI16 clock selected as I2C3 clock 11: Reserved RM0394 Rev 4 235/1600 246 Reset and clock control (RCC) RM0394 Bits 15:14 I2C2SEL[1:0]: I2C2 clock source selection These bits are set and cleared by software to select the I2C2 clock source. 00: PCLK selected as I2C2 clock 01: System clock (SYSCLK) selected as I2C2 clock 10: HSI16 clock selected as I2C2 clock 11: Reserved Bits 13:12 I2C1SEL[1:0]: I2C1 clock source selection These bits are set and cleared by software to select the I2C1 clock source. 00: PCLK selected as I2C1 clock 01: System clock (SYSCLK) selected as I2C1 clock 10: HSI16 clock selected as I2C1 clock 11: Reserved Bits 11:10 LPUART1SEL[1:0]: LPUART1 clock source selection These bits are set and cleared by software to select the LPUART1 clock source. 00: PCLK selected as LPUART1 clock 01: System clock (SYSCLK) selected as LPUART1 clock 10: HSI16 clock selected as LPUART1 clock 11: LSE clock selected as LPUART1 clock Bits 9:8 Reserved, must be kept at reset value. Bits 7:6 UART4SEL[1:0]: UART4 clock source selection This bit is set and cleared by software to select the UART4 clock source. 00: PCLK selected as UART4 clock 01: System clock (SYSCLK) selected as UART4 clock 10: HSI16 clock selected as UART4 clock 11: LSE clock selected as UART4 clock Bits 5:4 USART3SEL[1:0]: USART3 clock source selection This bit is set and cleared by software to select the USART3 clock source. 00: PCLK selected as USART3 clock 01: System clock (SYSCLK) selected as USART3 clock 10: HSI16 clock selected as USART3 clock 11: LSE clock selected as USART3 clock Bits 3:2 USART2SEL[1:0]: USART2 clock source selection This bit is set and cleared by software to select the USART2 clock source. 00: PCLK selected as USART2 clock 01: System clock (SYSCLK) selected as USART2 clock 10: HSI16 clock selected as USART2 clock 11: LSE clock selected as USART2 clock Bits 1:0 USART1SEL[1:0]: USART1 clock source selection This bit is set and cleared by software to select the USART1 clock source. 00: PCLK selected as USART1 clock 01: System clock (SYSCLK) selected as USART1 clock 10: HSI16 clock selected as USART1 clock 11: LSE clock selected as USART1 clock 1. Not available on STM3L41xxx and STM32L42xxx. 236/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) 6.4.28 Backup domain control register (RCC_BDCR) Address offset: 0x90 Reset value: 0x0000 0000, reset by Backup domain Reset, except LSCOSEL, LSCOEN and BDRST which are reset only by Backup domain power-on reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. Note: 31 Res. 15 RTC EN rw The bits of the Backup domain control register (RCC_BDCR) are outside of the VCORE domain. As a result, after Reset, these bits are write-protected and the DBP bit in the Section 5.4.1: Power control register 1 (PWR_CR1) has to be set before these can be modified. Refer to Section 5.1.4: Battery backup domain on page 130 for further information. These bits (except LSCOSEL, LSCOEN and BDRST) are only reset after a Backup domain Reset (see Section 6.1.3: Backup domain reset). Any internal or external Reset will not have any effect on these bits. 30 Res. 14 Res. 29 Res. 13 Res. 28 Res. 12 Res. 27 Res. 11 Res. 26 25 24 23 22 21 20 19 18 17 16 Res. LSCO SEL LSCO EN Res. Res. Res. Res. Res. Res. Res. BDRST rw rw 9 8 10 Res. RTCSEL[1:0] rw rw 7 LSESY SDIS(1) rw 6 5 LSE LSE CSSD CSSON rw r rw 4 3 LSEDRV[1:0] rw rw 2 1 0 LSE BYP LSE RDY LSEON rw r rw 1. This bit is available on STM32L412xx and STM32L422xx devices only. Bits 31:26 Reserved, must be kept at reset value. Bit 25 LSCOSEL: Low speed clock output selection Set and cleared by software. 0: LSI clock selected 1: LSE clock selected Bit 24 LSCOEN: Low speed clock output enable Set and cleared by software. 0: Low speed clock output (LSCO) disable 1: Low speed clock output (LSCO) enable Bits 23:17 Reserved, must be kept at reset value. Bit 16 BDRST: Backup domain software reset Set and cleared by software. 0: Reset not activated 1: Reset the entire Backup domain Bit 15 RTCEN: RTC clock enable Set and cleared by software. 0: RTC clock disabled 1: RTC clock enabled Bits 14:10 Reserved, must be kept at reset value. RM0394 Rev 4 237/1600 246 Reset and clock control (RCC) RM0394 Bits 9:8 RTCSEL[1:0]: RTC clock source selection Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them. 00: No clock 01: LSE oscillator clock used as RTC clock 10: LSI oscillator clock used as RTC clock 11: HSE oscillator clock divided by 32 used as RTC clock Bit 7 LSESYSDIS: Disable the Clock LSE propagation to the system.(1) Set by software to disable the Clock LSE propagation to the system. Only RTC will be clocked by LSE when this bit is set. 1: No clock LSE propagation 0: Clock LSE propagation enabled Bit 6 LSECSSD CSS on LSE failure Detection Set by hardware to indicate when a failure has been detected by the Clock Security System on the external 32 kHz oscillator (LSE). 0: No failure detected on LSE (32 kHz oscillator) 1: Failure detected on LSE (32 kHz oscillator) Bit 5 LSECSSON CSS on LSE enable Set by software to enable the Clock Security System on LSE (32 kHz oscillator). LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software MUST disable the LSECSSON bit. 0: CSS on LSE (32 kHz external oscillator) OFF 1: CSS on LSE (32 kHz external oscillator) ON Bits 4:3 LSEDRV[1:0] LSE oscillator drive capability Set by software to modulate the LSE oscillator’s drive capability. 00: ‘Xtal mode’ lower driving capability 01: ‘Xtal mode’ medium low driving capability 10: ‘Xtal mode’ medium high driving capability 11: ‘Xtal mode’ higher driving capability The oscillator is in Xtal mode when it is not in bypass mode. 238/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) Bit 2 LSEBYP: LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0). 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. 0: LSE oscillator not ready 1: LSE oscillator ready Bit 0 LSEON: LSE oscillator enable Set and cleared by software. 0: LSE oscillator OFF 1: LSE oscillator ON 1. This bit is available on STM32L412xx and STM32L422xx devices only. 6.4.29 Control/status register (RCC_CSR) Address: 0x94 Reset value: 0x0C00 0600, reset by system Reset, except reset flags by power Reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LPWR RSTF WWDG RSTF IWWG RSTF SFT RSTF BOR RSTF PIN RSTF OBL RSTF FW RSTF RMVF Res. Res. Res. Res. Res. Res. Res. 6 5 4 3 2 1 0 Res. LSIPR EDIV(1) Res. Res. LSI RDY LSION r rw r r r r r r r r rw 15 14 13 12 11 10 9 8 7 Res. Res. Res. Res. MSISRANGE[3:0] rw rw rw Res. rw Res. rw 1. This bit is available on STM32L412xx and STM32L422xx devices only. RM0394 Rev 4 239/1600 246 Reset and clock control (RCC) RM0394 Bit 31 LPWRRSTF: Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry. Cleared by writing to the RMVF bit. 0: No illegal mode reset occurred 1: Illegal mode reset occurred Bit 30 WWDGRSTF: Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit. 0: No window watchdog reset occurred 1: Window watchdog reset occurred Bit 29 IWDGRSTF: Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by writing to the RMVF bit. 0: No independent watchdog reset occurred 1: Independent watchdog reset occurred Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 BORRSTF: BOR flag Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit. 0: No BOR occurred 1: BOR occurred Bit 26 PINRSTF: Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit. 0: No reset from NRST pin occurred 1: Reset from NRST pin occurred Bit 25 OBLRSTF: Option byte loader reset flag Set by hardware when a reset from the Option Byte loading occurs. Cleared by writing to the RMVF bit. 0: No reset from Option Byte loading occurred 1: Reset from Option Byte loading occurred Bit 24 FWRSTF: Firewall reset flag Set by hardware when a reset from the firewall occurs. Cleared by writing to the RMVF bit. 0: No reset from the firewall occurred 1: Reset from the firewall occurred Bit 23 RMVF: Remove reset flag Set by software to clear the reset flags. 0: No effect 1: Clear the reset flags Bits 22:12 Reserved, must be kept at reset value. 240/1600 RM0394 Rev 4 RM0394 Reset and clock control (RCC) Bits 11:8 MSISRANGE[3:1] MSI range after Standby mode Set by software to chose the MSI frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a pad or a power-on reset, the range is always 4 MHz. MSISRANGE can be written only when MSIRGSEL = ‘1’. 0100: Range 4 around 1 MHz 0101: Range 5 around 2 MHz 0101: Range 6 around 4 MHz (reset value) 0111: Range 7 around 8 MHz others: Reserved Note: Changing the MSISRANGE does not change the current MSI frequency. Bits 7:25 Reserved, must be kept at reset value. Bit 4 LSIPREDIV: Internal Low Speed oscillator pre-divided by 128 Set and reset by hardware to indicate when the Low Speed Internal RC oscillator has to be divided by 128. The software has to switch off the LSI before to change this bit. 0: LSI RC oscillator is not divided 1: LSI RC oscillator divided by 128 Bits 3:2 Reserved, must be kept at reset value. Bit 1 LSIRDY: LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC. 0: LSI oscillator not ready 1: LSI oscillator ready Bit 0 LSION: LSI oscillator enable Set and cleared by software. 0: LSI oscillator OFF 1: LSI oscillator ON 6.4.30 Clock recovery RC register (RCC_CRRCR) Address: 0x98 Reset value: 0x0000 XXX0 where X is factory-programmed. Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. HSI48 RDY HSI48 ON r rw HSI48CAL[8:0] r r r r r Res. r r r r RM0394 Rev 4 Res. Res. Res. 241/1600 246 Reset and clock control (RCC) RM0394 Bits 31:16 Reserved, must be kept at reset value Bits 15:7 HSI48CAL[8:0]: HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. They are ready only. Bits 6:2 Reserved, must be kept at reset value Bit 1 HSI48RDY: HSI48 clock ready flag Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON. 0: HSI48 oscillator not ready 1: HSI48 oscillator ready Bit 0 HSI48ON: HSI48 clock enable Set and cleared by software. Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes. 0: HSI48 oscillator OFF 1: HSI48 oscillator ON 6.4.31 Peripherals independent clock configuration register (RCC_CCIPR2) Address: 0x9C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. I2C4SEL[1:0] r Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 I2C4SEL[1:0]: I2C4 clock source selection These bits are set and cleared by software to select the I2C4 clock source. 00: PCLK selected as I2C4 clock 01: System clock (SYSCLK) selected as I2C4 clock 10: HSI16 clock selected as I2C4 clock 11: reserved 6.4.32 RCC register map The following table gives the RCC register map and the reset values. 242/1600 RM0394 Rev 4 rw Reset value 0x10 0x18 0x1C 0x20 RCC_ PLLSAI1 CFGR RCC_CIFR RCC_CICR PLLPDIV[4:0] PLLR [1:0] 0 0 0 0 0 0 0 0 PLL PLLSAI1PDI SAI1 V R [4:0] [1:0] PLL Q [1:0] PLL SAI1 Q [1:0] PLLQEN Res. Res. PLLP PLLPEN Res. Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCC_CR HSICAL[7:0] 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 RCC_CIER 0 0 0 0 0 0 0 Reset value Reset value Reset value RM0394 Rev 4 PLLN [6:0] 0 0 1 0 0 0 0 PLLSAI1N [6:0] 0 0 0 0 0 0 0 0 Res. Res. Res. Res. PLLSAI1RDY PLLSAI1ON PLLRDY PLLON Res. Res. Res. Res. CSSON HSEBYP HSERDY HSEON Res. Res. Res. Res. HSIASFS HSIRDY HSIKERON HSION MSITRIM[7:0] PLLM [2:0] 0 0 0 MSIRGSEL MSIPLLEN MSIRDY MSION MSIRANG E [3:0] Res. Res. 0 0 0 0 Res. Reset value 1 0 0 0 0 0 0 x x x x x x x x 0 0 0 0 0 0 0 0 x x x x x x x x RCC_CFGR MCOP MCOSEL RE [3:0] [2:0] Res. Res. Res. Res. Res. Res. Res. Res. STOPWUCK Res. 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. 0x0C RCC_PLL CFGR HSITRIM[6:0] PLLSAI1QEN Res. Res. PLLSAI1P PLLSAI1PEN Res. Reset value PLLREN Res. 0x08 Res. RCC_ICSCR Res. Reset value PLLSAI1REN Res. 0x04 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HSI48RDYIE LSECSSIE. Res. Res. PLLSAI1RDYIE PLLRDYIE HSERDYIE HSIRDYIE MSIRDYIE LSERDYIE LSIRDYIE 0x00 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HSI48RDYF LSECSSF CSSF Res. PLLSAI1RDYF PLLRDYF HSERDYF HSIRDYF MSIRDYF LSERDYF LSIRDYF Offset Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HSI48RDYC LSECSSC CSSC Res. PLLSAI1RDYC PLLRDYC HSERDYC HSIRDYC MSIRDYC LSERDYC LSIRDYC RM0394 Reset and clock control (RCC) Table 32. RCC register map and reset values 0 0 0 0 0 1 1 0 0 0 1 1 MSICAL[7:0] PPRE2 PPRE1 SWS SW HPRE[3:0] [2:0] [2:0] [1:0] [1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL SRC [1:0] 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 243/1600 246 RCC_ 0x38 APB1RSTR1 Reset value RCC_ 0x3C APB1RSTR2 0x48 0x4C RCC_ APB2RSTR Reset value RCC_AHB1 ENR RCC_AHB2 ENR Reset value 244/1600 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. QSPIRST Res. Res. Res. Res. Res. Res. Res. Res. 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 RM0394 Rev 4 0 0 0 Reset value 0 0 0 0 0 0 GPIOHRST Res. Res. GPIOERST GPIODRST GPIOCRST GPIOBRST GPIOARST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RNGRST. Res. AESRST. Res. Res. ADCRST. Res. Res. Res. Res. Reset value Res. Res. Res. Res. GPIOHEN Res. Res. GPIOEEN GPIODEN GPIOCEN GPIOBEN GPIOAEN 0x40 RCC_ AHB3RSTR LPTIM1RST OPAMPRST DAC1RST PWRRST Res. USBFSRST CAN1RST CRSRST I2C3RST I2C2RST I2C1RST Res. UART4RST USART3RST USART2RST Res. SPI3RST SPI2RST Res. Res. Res. Res. LCDRST Res. Res. Res. TIM7RST TIM6RST Res. Res. TIM3RST TIM2RST 0x30 RCC_ AHB2RSTR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPTIM2RST Res. Res. SWPMI1RST I2C4RST LPUART1RST 0x2C Res. Res. Res. Res. Res. Res. Res. DFSDM1RST Res. Res. SAI1RST Res. Res. Res. TIM16RST TIM15RST Res. USART1RST Res. SPI1RST TIM1RST SDMMC1RST Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSCFGRST Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCC_ AHB1RSTR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSCRST. Res. Res. Res. CRCRST. Res. Res. Res. FLASHRST. Res. Res. Res. Res. Res. Res. DMA2RST DMA1RST 0x28 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSCEN. Res. Res. Res. CRCEN Res. Res. Res. FLASHEN Res. Res. Res. Res. Res. Res. DMA2EN DMA1EN Offset Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RNGEN Res. AESEN Res. Res. ADCEN Reset and clock control (RCC) RM0394 Table 32. RCC register map and reset values (continued) 0 0 0 0 0 0 Reset value 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x78 Reset value RCC_ 0x68 AHB1SMENR RCC_ 0x6C AHB2SMENR RCC_ AHB3SMENR 0x70 RCC_ APB1SM ENR1 Reset value 0 1 1 1 1 1 0 Reset value 1 1 1 SPI1EN TIM1EN SDMMC1EN Res. Res. FWEN Res. Res. Res. Res. Res. Res. SYSCFGEN LPTIM1EN OPAMPEN DAC1EN PWREN Res. USBFSEN CAN1EN CRSEN I2C3EN I2C2EN I2C1EN Res. UART4EN USART3EN USART2EN Res. SP3EN SPI2EN Res. Res. WWDGEN RTCAPBEN LCDEN Res. Res. Res. TIM7EN TIM6EN Res. Res. TIM3EN TIM2EN Reset value 0 0 0 0 RCC_ APB1ENR2 0 0 0 0 0 0 TIM16EN TIM15EN Res. USART1EN SAI1EN Res. Res. RCC_ APB1ENR1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPTIM2EN Res. Res. SWPMI1EN I2C4EN LPUART1EN Reset value 0 0 0 Reset value 1 1 1 1 RM0394 Rev 4 0 0 0 0 0 0 0 0 1 1 1 1 Reset value 1 1 1 1 GPIOHSMEN Res. Res. GPIOESMEN GPIODSMEN GPIOCSMEN GPIOBSMEN GPIOASMEN 0x60 RCC_ APB2ENR Res. Res. Res. Res. Res. Res. Res. DFSDM1EN Res. 0x5C Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSCSMEN. Res. Res. Res. CRCSMEN Res. Res. SRAM1SMEN FLASHSMEN Res. Res. Res. Res. Res. Res. DMA2SMEN DMA1SMEN 0x58 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. QSPIEN Res. Res. Res. Res. Res. Res. Res. RCC_AHB3 ENR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RNGSMEN Res. AESSMEN Res. Res. ADCFSSMEN Res. Res. Res. SRAM2SMEN 0x50 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. QSPISMEN Res. Res. Res. Res. Res. Res. Res. Res. Offset LPTIM1SMEN OPAMPSMEN DAC1SMEN PWRSMEN Res. USBFSSMEN CAN1SMEN CRSSMEN I2C3SMEN I2C2SMEN I2C1SMEN Res. UART4SMEN USART3SMEN USART2SMEN Res. SP3SMEN SPI2SMEN Res. Res. WWDGSMEN RTCAPBSMEN LCDSMEN Res. Res. Res. TIM7SMEN TIM6SMEN Res. Res. TIM3SMEN TIM2SMEN RM0394 Reset and clock control (RCC) Table 32. RCC register map and reset values (continued) 0 0 1 0 0 0 Reset value 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 245/1600 246 0x94 0x98 0x9C RCC_BDCR Reset value RCC_CRRCR RCC_CCIPR2 246/1600 0 0 Reset value Reset value RM0394 Rev 4 0 0 RCC_CSR Reset value 0 0 0 0 0 0 0 0 0 RTC SEL [1:0] MSIS RANGE [3:0] 0 1 1 0 HSI48CAL[8:0] 1 1 1 1 LSE DRV [1:0] 0 x x x x x x x x x USART1SEL USART2SEL USART3SEL Res. Res. Res. Res. Res. Res. Res. DFSDM1SMEN Res. Res. SAI1SMEN Res. Res. Res. TIM16SMEN TIM15SMEN Res. USART1SMEN Res. SPI1SMEN TIM1SMEN SDMMC1SMEN Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSCFGSMEN Reset value LSEBYP LSERDY LSEON 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART4SEL Res. Res. 1 LPUART1SEL 1 1 I2C1SEL I2C2SEL I2C3SEL LPTIM1SEL LPTIM2SEL 1 LSESYSDIS LSECSSD LSECSSON 0 0 0 0 0 SAI1SEL Res. Res. CLK48SEL 1 Res. Res. Res. LSIPREDIV Res. Res. LSIRDY LSION Reset value ADCSEL Reset value Res. Res. Res. Res. Res. HSI48RDY HSI48ON 0x90 RCC_CCIPR DFSDM1SEL SWPMI1SEL RCC_ 0x80 APB2SMENR Res. Res. Res. Res. Res. Res. LSCOSEL LSCOEN Res. Res. Res. Res. Res. Res. Res. BDRST RTCEN Res. Res. Res. Res. Res. 0x88 LPWRRSTF WWDGRSTF IWDGRSTF SFTRSTF BORRSTF PINRSTF OBLRSTF FIREWALLRSTF RMVF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCC_ APB1SM ENR2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPTIM2SMEN Res. Res. SWPMI1SMEN I2C4SMEN LPUART1SMEN 0x7C Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Offset Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset and clock control (RCC) RM0394 Table 32. RCC register map and reset values (continued) 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C4 SEL [1:0] 0 0 RM0394 Clock recovery system (CRS) 7 Clock recovery system (CRS) 7.1 Introduction The clock recovery system (CRS) is an advanced digital controller acting on the internal fine-granularity trimmable RC oscillator HSI48. The CRS provides powerful means for oscillator output frequency evaluation, based on comparison with a selectable synchronization signal. It is capable of doing automatic adjustment of oscillator trimming based on the measured frequency error value, while keeping the possibility of a manual trimming. The CRS is ideally suited to provide a precise clock to the USB peripheral. In such case, the synchronization signal can be derived from the start-of-frame (SOF) packet signalization on the USB bus, which is sent by a USB host at precise 1-ms intervals. The synchronization signal can also be derived from the LSE oscillator output or it can be generated by user software. 7.2 CRS main features • Selectable synchronization source with programmable prescaler and polarity: – External pin – LSE oscillator output – USB SOF packet reception • Possibility to generate synchronization pulses by software • Automatic oscillator trimming capability with no need of CPU action • Manual control option for faster start-up convergence • 16-bit frequency error counter with automatic error value capture and reload • Programmable limit for automatic frequency error value evaluation and status reporting • Maskable interrupts/events: – Expected synchronization (ESYNC) – Synchronization OK (SYNCOK) – Synchronization warning (SYNCWARN) – Synchronization or trimming error (ERR) RM0394 Rev 4 247/1600 257 Clock recovery system (CRS) RM0394 7.3 CRS functional description 7.3.1 CRS block diagram Figure 17. CRS block diagram &56B6<1& *3,2 6<1&65& 6:6<1& 26&B,1 6<1&GLYLGHU « /6( 26&B287 6<1& 86%B'3 )(/,0 86% 86%B'0 75,0 5&& )(',5 5&0+] )(&$3 ELWFRXQWHU 5(/2$' +6, 7R86% 7R51* 06Y9 7.3.2 Synchronization input The CRS synchronization (SYNC) source, selectable through the CRS_CFGR register, can be the signal from the LSE clock or the USB SOF signal. For a better robustness of the SYNC input, a simple digital filter (2 out of 3 majority votes, sampled by the HSI48 clock) is implemented to filter out any glitches. This source signal also has a configurable polarity and can then be divided by a programmable binary prescaler to obtain a synchronization signal in a suitable frequency range (usually around 1 kHz). For more information on the CRS synchronization source configuration, refer to Section 7.6.2: CRS configuration register (CRS_CFGR). It is also possible to generate a synchronization event by software, by setting the SWSYNC bit in the CRS_CR register. 248/1600 RM0394 Rev 4 RM0394 7.3.3 Clock recovery system (CRS) Frequency error measurement The frequency error counter is a 16-bit down/up counter which is reloaded with the RELOAD value on each SYNC event. It starts counting down till it reaches the zero value, where the ESYNC (expected synchronization) event is generated. Then it starts counting up to the OUTRANGE limit where it eventually stops (if no SYNC event is received) and generates a SYNCMISS event. The OUTRANGE limit is defined as the frequency error limit (FELIM field of the CRS_CFGR register) multiplied by 128. When the SYNC event is detected, the actual value of the frequency error counter and its counting direction are stored in the FECAP (frequency error capture) field and in the FEDIR (frequency error direction) bit of the CRS_ISR register. When the SYNC event is detected during the downcounting phase (before reaching the zero value), it means that the actual frequency is lower than the target (and so, that the TRIM value should be incremented), while when it is detected during the upcounting phase it means that the actual frequency is higher (and that the TRIM value should be decremented). Figure 18. CRS counter behavior &56FRXQWHUYDOXH 5(/2$' (6<1& 'RZQ 8S )UHTXHQF\ HUURUFRXQWHU VWRSSHG 2875$1*( [)(/,0 :$51,1*/,0,7 [)(/,0 72/(5$1&(/,0,7 )(/,0 7ULPPLQJDFWLRQ &56HYHQW 6<1&(55 6<1&:$51 6<1&2. 6<1&:$51 6<1&0,66 06Y9 RM0394 Rev 4 249/1600 257 Clock recovery system (CRS) 7.3.4 RM0394 Frequency error evaluation and automatic trimming The measured frequency error is evaluated by comparing its value with a set of limits: – TOLERANCE LIMIT, given directly in the FELIM field of the CRS_CFGR register – WARNING LIMIT, defined as 3 * FELIM value – OUTRANGE (error limit), defined as 128 * FELIM value The result of this comparison is used to generate the status indication and also to control the automatic trimming which is enabled by setting the AUTOTRIMEN bit in the CRS_CR register: • • • • Note: When the frequency error is below the tolerance limit, it means that the actual trimming value in the TRIM field is the optimal one and that then, no trimming action is necessary. – SYNCOK status indicated – TRIM value not changed in AUTOTRIM mode When the frequency error is below the warning limit but above or equal to the tolerance limit, it means that some trimming action is necessary but that adjustment by one trimming step is enough to reach the optimal TRIM value. – SYNCOK status indicated – TRIM value adjusted by one trimming step in AUTOTRIM mode When the frequency error is above or equal to the warning limit but below the error limit, it means that a stronger trimming action is necessary, and there is a risk that the optimal TRIM value will not be reached for the next period. – SYNCWARN status indicated – TRIM value adjusted by two trimming steps in AUTOTRIM mode When the frequency error is above or equal to the error limit, it means that the frequency is out of the trimming range. This can also happen when the SYNC input is not clean or when some SYNC pulse is missing (for example when one USB SOF is corrupted). – SYNCERR or SYNCMISS status indicated – TRIM value not changed in AUTOTRIM mode If the actual value of the TRIM field is so close to its limits that the automatic trimming would force it to overflow or underflow, then the TRIM value is set just to the limit and the TRIMOVF status is indicated. In AUTOTRIM mode (AUTOTRIMEN bit set in the CRS_CR register), the TRIM field of CRS_CR is adjusted by hardware and is read-only. 7.3.5 CRS initialization and configuration RELOAD value The RELOAD value should be selected according to the ratio between the target frequency and the frequency of the synchronization source after prescaling. It is then decreased by one in order to reach the expected synchronization on the zero value. The formula is the following: RELOAD = (fTARGET / fSYNC) - 1 The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). 250/1600 RM0394 Rev 4 RM0394 Clock recovery system (CRS) FELIM value The selection of the FELIM value is closely coupled with the HSI48 oscillator characteristics and its typical trimming step size. The optimal value corresponds to half of the trimming step size, expressed as a number of HSI48 oscillator clock ticks. The following formula can be used: FELIM = (fTARGET / fSYNC) * STEP[%] / 100% / 2 The result should be always rounded up to the nearest integer value in order to obtain the best trimming response. If frequent trimming actions are not wanted in the application, the trimming hysteresis can be increased by increasing slightly the FELIM value. The reset value of the FELIM field corresponds to (fTARGET / fSYNC) = 48000 and to a typical trimming step size of 0.14%. Caution: There is no hardware protection from a wrong configuration of the RELOAD and FELIM fields which can lead to an erratic trimming response. The expected operational mode requires proper setup of the RELOAD value (according to the synchronization source frequency), which is also greater than 128 * FELIM value (OUTRANGE limit). 7.4 CRS low-power modes Table 33. Effect of low-power modes on CRS Mode Sleep Description No effect. CRS interrupts cause the device to exit the Sleep mode. Stop CRS registers are frozen. The CRS stops operating until the Stop or Standby mode is exited and the HSI48 oscillator Standby restarted. 7.5 CRS interrupts Table 34. Interrupt control bits Interrupt event Event flag Enable control bit Clear flag bit Expected synchronization ESYNCF ESYNCIE ESYNCC Synchronization OK SYNCOKF SYNCOKIE SYNCOKC Synchronization warning SYNCWARNF SYNCWARNIE SYNCWARNC Synchronization or trimming error (TRIMOVF, SYNCMISS, SYNCERR) ERRF ERRIE ERRC RM0394 Rev 4 251/1600 257 Clock recovery system (CRS) 7.6 RM0394 CRS registers Refer to Section 1.2 on page 60 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 7.6.1 CRS control register (CRS_CR) Address offset: 0x00 Reset value: 0x0000 2000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 5 4 3 2 1 Res. ESYNC IE Res. Res. TRIM[5:0] rw rw rw rw rw rw 7 6 SW SYNC AUTO TRIMEN CEN rt_w1 rw rw rw SYNC ERRIE WARNIE rw 0 SYNC OKIE rw rw Bits 31:14 Reserved, must be kept at reset value. Bits 13:8 TRIM[5:0]: HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48 oscillator. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is specified in the product datasheet. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only. Bit 7 SWSYNC: Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. 0: No action 1: A software SYNC event is generated. Bit 6 AUTOTRIMEN: Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section 7.3.4: Frequency error evaluation and automatic trimming for more details. 0: Automatic trimming disabled, TRIM bits can be adjusted by the user. 1: Automatic trimming enabled, TRIM bits are read-only and under hardware control. Bit 5 CEN: Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. 0: Frequency error counter disabled 1: Frequency error counter enabled When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. Bit 4 Reserved, must be kept at reset value. 252/1600 RM0394 Rev 4 RM0394 Clock recovery system (CRS) Bit 3 ESYNCIE: Expected SYNC interrupt enable 0: Expected SYNC (ESYNCF) interrupt disabled 1: Expected SYNC (ESYNCF) interrupt enabled Bit 2 ERRIE: Synchronization or trimming error interrupt enable 0: Synchronization or trimming error (ERRF) interrupt disabled 1: Synchronization or trimming error (ERRF) interrupt enabled Bit 1 SYNCWARNIE: SYNC warning interrupt enable 0: SYNC warning (SYNCWARNF) interrupt disabled 1: SYNC warning (SYNCWARNF) interrupt enabled Bit 0 SYNCOKIE: SYNC event OK interrupt enable 0: SYNC event OK (SYNCOKF) interrupt disabled 1: SYNC event OK (SYNCOKF) interrupt enabled 7.6.2 CRS configuration register (CRS_CFGR) This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected. Address offset: 0x04 Reset value: 0x2022 BB7F 31 30 SYNCPOL Res. rw 29 28 SYNCSRC[1:0] 27 26 Res. 25 24 23 22 21 SYNCDIV[2:0] 20 19 18 17 16 FELIM[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw RELOAD[15:0] rw rw Bit 31 SYNCPOL: SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source. 0: SYNC active on rising edge (default) 1: SYNC active on falling edge Bit 30 Reserved, must be kept at reset value. Bits 29:28 SYNCSRC[1:0]: SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. 00: GPIO selected as SYNC signal source 01: LSE selected as SYNC signal source 10: USB SOF selected as SYNC signal source (default). Supported on STM32L4x2xx and STM32L4x3xx devices only. 11: Reserved Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 oscillator on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal. Bit 27 Reserved, must be kept at reset value. RM0394 Rev 4 253/1600 257 Clock recovery system (CRS) RM0394 Bits 26:24 SYNCDIV[2:0]: SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. 000: SYNC not divided (default) 001: SYNC divided by 2 010: SYNC divided by 4 011: SYNC divided by 8 100: SYNC divided by 16 101: SYNC divided by 32 110: SYNC divided by 64 111: SYNC divided by 128 Bits 23:16 FELIM[7:0]: Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section 7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation. Bits 15:0 RELOAD[15:0]: Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section 7.3.3: Frequency error measurement for more details about counter behavior. 7.6.3 CRS interrupt and status register (CRS_ISR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r FECAP[15:0] r r r r r 15 14 13 12 11 10 Res. TRIM OVF r r r FEDIR Res. r Res. Res. r r r r r r r r r 9 8 7 6 5 4 3 2 1 0 SYNC MISS SYNC ERR ESYNCF ERRF SYNC WARNF SYNC OKF r r r r Res. Res. Res. Res. Bits 31:16 FECAP[15:0]: Frequency error capture FECAP is the frequency error counter value latched in the time of the last SYNC event. Refer to Section 7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage. Bit 15 FEDIR: Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. 0: Upcounting direction, the actual frequency is above the target. 1: Downcounting direction, the actual frequency is below the target. Bits 14:11 Reserved, must be kept at reset value. Bit 10 TRIMOVF: Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 0: No trimming error signalized 1: Trimming error signalized 254/1600 RM0394 Rev 4 RM0394 Clock recovery system (CRS) Bit 9 SYNCMISS: SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 0: No SYNC missed error signalized 1: SYNC missed error signalized Bit 8 SYNCERR: SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 0: No SYNC error signalized 1: SYNC error signalized Bits 7:4 Reserved, must be kept at reset value. Bit 3 ESYNCF: Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. 0: No expected SYNC signalized 1: Expected SYNC signalized Bit 2 ERRF: Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. 0: No synchronization or trimming error signalized 1: Synchronization or trimming error signalized Bit 1 SYNCWARNF: SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. 0: No SYNC warning signalized 1: SYNC warning signalized Bit 0 SYNCOKF: SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. 0: No SYNC event OK signalized 1: SYNC event OK signalized RM0394 Rev 4 255/1600 257 Clock recovery system (CRS) 7.6.4 RM0394 CRS interrupt flag clear register (CRS_ICR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ESYNCC ERRC SYNC WARNC SYNC OKC rw rw rw rw Bits 31:4 Reserved, must be kept at reset value. Bit 3 ESYNCC: Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register. Bit 2 ERRC: Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register. Bit 1 SYNCWARNC: SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register. Bit 0 SYNCOKC: SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register. 256/1600 RM0394 Rev 4 RM0394 7.6.5 Clock recovery system (CRS) CRS register map SWSYNC CEN Res. ESYNCIE ERRIE SYNCWARNIE SYNCOKIE 0 0 0 0 0 0 0 0 0 0 0 CRS_ICR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 Reset value SYNCOKF 0 0 0 0 0 SYNCOKC 0 ERRF 0 1 SYNCWARNF 0 1 ERRC 0 1 SYNCWARNC 0 1 ESYNCF 0 1 ESYNCC 0 1 Res. 0 1 Res. 0 0 Res. 0 1 SYNCERR 0 1 Res. 0 0 SYNCMISS 0 1 Res. 0 Res. 1 Res. 1 Res. 0 Res. FECAP[15:0] 1 Res. 0 Res. 1 TRIMOVF 0 Reset value 0x0C 0 Res. 0 Res. 0 Res. 1 Res. 0 Res. 0 Res. 0 Res. CRS_ISR 0 0 RELOAD[15:0] Res. 0 0 FELIM[7:0] Res. 0 0 FEDIR 1 SYNC DIV [2:0] Res. 0 Res. Reset value SYNC SRC [1:0] Res. 0x08 CRS_CFGR Res. 0x04 1 SYNCPOL Reset value TRIM[5:0] AUTOTRIMEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CRS_CR Res. 0x00 Res. Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 35. CRS register map and reset values 0 0 0 0 Refer to Section 2.2.2 on page 67 for the register boundary addresses. RM0394 Rev 4 257/1600 257 General-purpose I/Os (GPIO) RM0394 8 General-purpose I/Os (GPIO) 8.1 Introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL). 8.2 8.3 GPIO main features • Output states: push-pull or open drain + pull-up/down • Output data from output data register (GPIOx_ODR) or peripheral (alternate function output) • Speed selection for each I/O • Input states: floating, pull-up/down, analog • Input data to input data register (GPIOx_IDR) or peripheral (alternate function input) • Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR • Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations • Analog function • Alternate function selection registers • Fast toggle capable of changing every two clock cycles • Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral functions GPIO functional description Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes: • Input floating • Input pull-up • Input-pull-down • Analog • Output open-drain with pull-up or pull-down capability • Output push-pull with pull-up or pull-down capability • Alternate function push-pull with pull-up or pull-down capability • Alternate function open-drain with pull-up or pull-down capability Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring between the read and the modify access. 258/1600 RM0394 Rev 4 RM0394 General-purpose I/Os (GPIO) Figure 19 and Figure 20 show the basic structures of a standard and a 5-Volt tolerant I/O port bit, respectively. Table 36 gives the possible port bit configurations. Figure 19. Basic structure of an I/O port bit $QDORJ 7RRQFKLS SHULSKHUDO $OWHUQDWHIXQFWLRQLQSXW ,QSXWGDWDUHJLVWHU RQRII 9'',2[9'',2[ WULJJHU RQRII ,2SLQ 2XWSXWGULYHU 9'',2[ RQRII 3URWHFWLRQ GLRGH 3XOO GRZQ 3026 966 2XWSXW FRQWURO 966 1026 5HDGZULWH )URPRQFKLS SHULSKHUDO 3URWHFWLRQ GLRGH 3XOO XS ,QSXWGULYHU 2XWSXWGDWDUHJLVWHU :ULWH %LWVHWUHVHWUHJLVWHUV 5HDG 966 $OWHUQDWHIXQFWLRQRXWSXW 3XVKSXOO RSHQGUDLQRU GLVDEOHG $QDORJ 069 Figure 20. Basic structure of a 5-Volt tolerant I/O port bit 7RRQFKLS SHULSKHUDO ,QSXWGDWDUHJLVWHU $OWHUQDWHIXQFWLRQLQSXW 5HDGZULWH )URPRQFKLS SHULSKHUDO 2XWSXWGDWDUHJLVWHU :ULWH %LWVHWUHVHWUHJLVWHUV 5HDG RQRII 9'',2[ 9''B)7 77/6FKPLWW WULJJHU RQRII 3XOO XS 3URWHFWLRQ GLRGH ,QSXWGULYHU ,2SLQ 2XWSXWGULYHU 9'',2[ RQRII 3026 2XWSXW FRQWURO 3XOO GRZQ 966 3URWHFWLRQ GLRGH 966 1026 966 $OWHUQDWHIXQFWLRQRXWSXW 3XVKSXOO RSHQGUDLQRU GLVDEOHG DLG 1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD. RM0394 Rev 4 259/1600 275 General-purpose I/Os (GPIO) RM0394 Table 36. Port bit configuration table(1) MODE(i) [1:0] 01 10 00 11 OTYPER(i) OSPEED(i) [1:0] PUPD(i) [1:0] I/O configuration 0 0 0 GP output PP 0 0 1 GP output PP + PU 0 1 0 GP output PP + PD 1 1 Reserved 0 0 GP output OD 1 0 1 GP output OD + PU 1 1 0 GP output OD + PD 1 1 1 Reserved (GP output OD) 0 0 0 AF PP 0 0 1 AF PP + PU 0 1 0 AF PP + PD 1 1 Reserved 0 0 AF OD 1 0 1 AF OD + PU 1 1 0 AF OD + PD 1 1 1 Reserved 0 SPEED [1:0] 1 0 SPEED [1:0] 1 x x x 0 0 Input Floating x x x 0 1 Input PU x x x 1 0 Input PD x x x 1 1 Reserved (input floating) x x x 0 0 Input/output x x x 0 1 x x x 1 0 x x x 1 1 Analog Reserved 1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate function. 260/1600 RM0394 Rev 4 RM0394 8.3.1 General-purpose I/Os (GPIO) General-purpose I/O (GPIO) During and just after reset, the alternate functions are not active and most of the I/O ports are configured in analog mode. The debug pins are in AF pull-up/pull-down after reset: • PA15: JTDI in pull-up • PA14: JTCK/SWCLK in pull-down • PA13: JTMS/SWDAT in pull-up • PB4: NJTRST in pull-up • PB3: JTDO in floating state no pull-up/pull-down PH3/BOOT0 is in input mode during the reset until at least the end of the option byte loading phase. See Section 8.3.15: Using PH3 as GPIO. When the pin is configured as output, the value written to the output data register (GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode (only the low level is driven, high level is HI-Z). The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB clock cycle. All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the GPIOx_PUPDR register. 8.3.2 I/O pin alternate function multiplexer and mapping The device I/O pins are connected to on-board peripherals/modules through a multiplexer that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals available on the same I/O pin. Each I/O pin (except PH3) has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers: • After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are configured in alternate function mode through GPIOx_MODER register. • The specific alternate function assignments for each pin are detailed in the device datasheet. In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages. To use an I/O in a given configuration, the user has to proceed as follows: • Debug function: after each device reset these pins are assigned as alternate function pins immediately usable by the debugger host • GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER register. • Peripheral alternate function: – Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH register. – Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER, GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively. RM0394 Rev 4 261/1600 275 General-purpose I/Os (GPIO) – • RM0394 Configure the desired I/O as an alternate function in the GPIOx_MODER register. Additional functions: – For the ADC, DAC, OPAMP, and COMP, configure the desired I/O in analog mode in the GPIOx_MODER register and configure the required function in the ADC, DAC, OPAMP, and COMP registers. – For the additional functions like RTC, WKUPx and oscillators, configure the required function in the related RTC, PWR and RCC registers. These functions have priority over the configuration in the standard GPIO registers. Refer to the “Alternate function mapping” table in the device datasheet for the detailed mapping of the alternate function I/O pins. 8.3.3 I/O port control registers Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (pushpull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pullup/pull-down whatever the I/O direction. 8.3.4 I/O port data registers Each GPIO has two 16-bit memory-mapped data registers: input and output data registers (GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write accessible. The data input through the I/O are stored into the input data register (GPIOx_IDR), a read-only register. See Section 8.4.5: GPIO port input data register (GPIOx_IDR) (x = A to E and H) and Section 8.4.6: GPIO port output data register (GPIOx_ODR) (x = A to E and H) for the register descriptions. 8.3.5 I/O data bitwise handling The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset register has twice the size of GPIOx_ODR. To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i). When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i) resets the ODR(i) corresponding bit. Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set action takes priority. Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a “one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be accessed directly. The GPIOx_BSRR register provides a way of performing atomic bitwise handling. There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify one or more bits in a single atomic AHB write access. 262/1600 RM0394 Rev 4 RM0394 8.3.6 General-purpose I/Os (GPIO) GPIO locking mechanism It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same). When the LOCK sequence has been applied to a port bit, the value of the port bit can no longer be modified until the next MCU reset or peripheral reset. Each GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. The LOCK sequence (refer to Section 8.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A to E and H)) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits. For more details refer to LCKR register description in Section 8.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A to E and H). 8.3.7 I/O alternate function input/output Two registers are provided to select one of the alternate function inputs/outputs available for each I/O. With these registers, the user can connect an alternate function to some other pin as required by the application. This means that a number of possible peripheral functions are multiplexed on each GPIO using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can thus select any one of the possible functions for each I/O. The AF selection signal being common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of a given I/O. To know which functions are multiplexed on each GPIO pin, refer to the device datasheet. No alternate function is mapped on PH3. 8.3.8 External interrupt/wakeup lines All ports have external interrupt capability. To use external interrupt lines, the port can be configured in input, output or alternate function mode (the port must not be configured in analog mode). Refer to Section 13: Extended interrupts and events controller (EXTI) and toSection 13.3.2: Wakeup event management. RM0394 Rev 4 263/1600 275 General-purpose I/Os (GPIO) 8.3.9 RM0394 Input configuration When the I/O port is programmed as input: • The output buffer is disabled • The Schmitt trigger input is activated • The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register • The data present on the I/O pin are sampled into the input data register every AHB clock cycle • A read access to the input data register provides the I/O state Figure 21 shows the input configuration of the I/O port bit. ,QSXWGDWDUHJLVWHU Figure 21. Input floating/pull up/pull down configurations 5HDGZULWH 2XWSXWGDWDUHJLVWHU :ULWH %LWVHWUHVHWUHJLVWHUV 5HDG RQ 77/6FKPLWW WULJJHU LQSXWGULYHU 9'',2[ 9'',2[ RQRII SURWHFWLRQ GLRGH SXOO XS ,2SLQ RQRII RXWSXWGULYHU SXOO GRZQ 966 SURWHFWLRQ GLRGH 966 069 8.3.10 Output configuration When the I/O port is programmed as output: • The output buffer is enabled: – Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated) – Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register activates the P-MOS • The Schmitt trigger input is activated • The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register • The data present on the I/O pin are sampled into the input data register every AHB clock cycle • A read access to the input data register gets the I/O state • A read access to the output data register gets the last written value Figure 22 shows the output configuration of the I/O port bit. 264/1600 RM0394 Rev 4 RM0394 General-purpose I/Os (GPIO) ,QSXWGDWDUHJLVWHU Figure 22. Output configuration RQ 5HDGZULWH 9'',2[ 9'',2[ 77/6FKPLWW WULJJHU RQRII ,QSXWGULYHU 2XWSXWGDWDUHJLVWHU :ULWH %LWVHWUHVHWUHJLVWHUV 5HDG SURWHFWLRQ GLRGH SXOO XS 2XWSXWGULYHU 9'',2[ ,2SLQ RQRII 3026 SURWHFWLRQ GLRGH SXOO GRZQ 2XWSXW FRQWURO 966 1026 3XVKSXOORU 966 2SHQGUDLQ 966 069 8.3.11 Alternate function configuration When the I/O port is programmed as alternate function: The output buffer can be configured in open-drain or push-pull mode • The output buffer is driven by the signals coming from the peripheral (transmitter enable and data) • The Schmitt trigger input is activated • The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register • The data present on the I/O pin are sampled into the input data register every AHB clock cycle • A read access to the input data register gets the I/O state The alternate function configuration described above is not applied when the selected alternate function is an LCD function or a SWPMI_IO. In this case, the I/O, programmed as an alternate function output, is configured as described in the analog configuration. Figure 23 shows the Alternate function configuration of the I/O port bit. Figure 23. Alternate function configuration $OWHUQDWH IXQFWLRQ LQSXW 5HDG 5HDGZULWH )URP RQFKLS SHULSKHUDO 9'',2[9'',2[ 77/ 6FKPLWW WULJJHU RQRII SURWHFWLRQ GLRGH 3XOO XS ,QSXW GULYHU 2XWSXW GDWD UHJLVWHU :ULWH RQ ,QSXW GDWD UHJLVWHU 7R RQFKLS SHULSKHUDO %LW VHWUHVHW UHJLVWHUV Note: • ,2 SLQ 2XWSXW GULYHU RQRII 9'' 3026 2XWSXW FRQWURO SURWHFWLRQ GLRGH 3XOO GRZQ 966 966 1026 966 SXVKSXOO RU RSHQGUDLQ $OWHUQDWH IXQFWLRQ RXWSXW 06Y9 RM0394 Rev 4 265/1600 275 General-purpose I/Os (GPIO) 8.3.12 RM0394 Analog configuration When the I/O port is programmed as analog configuration: • The output buffer is disabled • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). • The weak pull-up and pull-down resistors are disabled by hardware • Read access to the input data register gets the value “0” Figure 24 shows the high-impedance, analog-input configuration of the I/O port bits. Figure 24. High impedance-analog configuration ,QSXWGDWDUHJLVWHU $QDORJ 7RRQFKLS SHULSKHUDO 5HDGZULWH )URPRQFKLS SHULSKHUDO 8.3.13 2XWSXWGDWDUHJLVWHU :ULWH %LWVHWUHVHWUHJLVWHUV 5HDG RII 9'',2[ 77/6FKPLWW WULJJHU SURWHFWLRQ GLRGH ,QSXWGULYHU ,2SLQ SURWHFWLRQ GLRGH 966 $QDORJ 069 Using the HSE or LSE oscillator pins as GPIOs When the HSE or LSE oscillator is switched OFF (default state after reset), the related oscillator pins can be used as normal GPIOs. When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the RCC_CSR register) the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect. When the oscillator is configured in a user external clock mode, only the pin is reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be used as normal GPIO. 8.3.14 Using the GPIO pins in the RTC supply domain The PC13/PC14/PC15 GPIO functionality is lost when the core supply domain is powered off (when the device enters Standby mode). In this case, if their GPIO configuration is not bypassed by the RTC configuration, these pins are set in an analog input mode. For details about I/O control by the RTC, refer to Section 36.3: RTC functional description. 266/1600 RM0394 Rev 4 RM0394 General-purpose I/Os (GPIO) 8.3.15 Using PH3 as GPIO PH3 may be used as boot pin (BOOT0) or as a GPIO. Depending on the nSWBOOT0 bit in the user option byte, it switches from the input mode to the analog input mode: 8.4 • After the option byte loading phase if nSWBOOT0 = 1. • After reset if nSWBOOT0 = 0. GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table 37. The peripheral registers can be written in word, half word or byte mode. 8.4.1 GPIO port mode register (GPIOx_MODER) (x =A to E and H) Address offset:0x00 Reset value: 31 30 • 0xABFF FFFF (for port A) • 0xFFFF FEBF (for port B) • 0xFFFF FFFF for ports C..E • 0x0000 000F (for port H) 29 MODE15[1:0] 28 MODE14[1:0] 27 26 MODE13[1:0] 25 24 MODE12[1:0] 23 22 MODE11[1:0] 21 20 MODE10[1:0] 19 18 17 16 MODE9[1:0] MODE8[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODE7[1:0] MODE6[1:0] MODE5[1:0] MODE4[1:0] MODE3[1:0] MODE2[1:0] MODE1[1:0] MODE0[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 MODE[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0) These bits are written by software to configure the I/O mode. 00: Input mode 01: General purpose output mode 10: Alternate function mode 11: Analog mode (reset state) RM0394 Rev 4 267/1600 275 General-purpose I/Os (GPIO) 8.4.2 RM0394 GPIO port output type register (GPIOx_OTYPER) (x = A to E and H) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OT15 OT14 OT13 OT12 OT11 OT10 OT9 OT8 OT7 OT6 OT5 OT4 OT3 OT2 OT1 OT0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 OT[15:0]: Port x configuration I/O pin y (y = 15 to 0) These bits are written by software to configure the I/O output type. 0: Output push-pull (reset state) 1: Output open-drain 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A to E and H) Address offset: 0x08 Reset value: 0x0C00 0000 (for port A) Reset value: 0x0000 0000 (for the other ports) 31 30 OSPEED15 [1:0] 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OSPEED14 [1:0] OSPEED13 [1:0] OSPEED12 [1:0] OSPEED11 [1:0] OSPEED10 [1:0] OSPEED9 [1:0] OSPEED8 [1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSPEED7 [1:0] OSPEED6 [1:0] OSPEED5 [1:0] OSPEED4 [1:0] OSPEED3 [1:0] OSPEED2 [1:0] OSPEED1 [1:0] OSPEED0 [1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 OSPEED[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0) These bits are written by software to configure the I/O output speed. 00: Low speed 01: Medium speed 10: High speed 11: Very high speed Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to E and H) Address offset: 0x0C Reset value: 0x6400 0000 (for port A) 268/1600 RM0394 Rev 4 RM0394 General-purpose I/Os (GPIO) Reset value: 0x0000 0100 (for port B) Reset value: 0x0000 0000 (for other ports) 31 30 29 PUPD15[1:0] 28 PUPD14[1:0] 27 26 25 PUPD13[1:0] 24 23 22 21 20 19 18 17 16 PUPD12[1:0] PUPD11[1:0] PUPD10[1:0] PUPD9[1:0] PUPD8[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PUPD7[1:0] PUPD6[1:0] PUPD5[1:0] PUPD4[1:0] PUPD3[1:0] PUPD2[1:0] PUPD1[1:0] PUPD0[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 PUPD[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down 00: No pull-up, pull-down 01: Pull-up 10: Pull-down 11: Reserved 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A to E and H) Address offset: 0x10 Reset value: 0x0000 XXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 r r r r r r r r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ID[15:0]: Port x input data I/O pin y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port. 8.4.6 GPIO port output data register (GPIOx_ODR) (x = A to E and H) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RM0394 Rev 4 269/1600 275 General-purpose I/Os (GPIO) RM0394 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 OD[15:0]: Port output data I/O pin y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F). 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A to E and H) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0 w w w w w w w w w w w w w w w w Bits 31:16 BR[15:0]: Port x reset I/O pin y (y = 15 to 0) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODx bit 1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority. Bits 15:0 BS[15:0]: Port x set I/O pin y (y = 15 to 0) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODx bit 1: Sets the corresponding ODx bit 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A to E and H) This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKK rw 270/1600 RM0394 Rev 4 RM0394 General-purpose I/Os (GPIO) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. LOCK key write sequence: WR LCKR[16] = ‘1’ + LCKR[15:0] WR LCKR[16] = ‘0’ + LCKR[15:0] WR LCKR[16] = ‘1’ + LCKR[15:0] RD LCKR RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return ‘1’ until the next MCU reset or peripheral reset. Bits 15:0 LCK[15:0]: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is ‘0. 0: Port configuration not locked 1: Port configuration locked 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A to E and H) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 AFSEL7[3:0] 26 25 24 23 AFSEL6[3:0] 22 21 20 19 AFSEL5[3:0] 18 17 16 AFSEL4[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw AFSEL3[3:0] rw rw rw AFSEL2[3:0] rw rw AFSEL1[3:0] RM0394 Rev 4 rw rw AFSEL0[3:0] rw rw rw 271/1600 275 General-purpose I/Os (GPIO) RM0394 Bits 31:0 AFSEL[7:0][3:0]: Alternate function selection for port x I/O pin y (y = 7 to 0) These bits are written by software to configure alternate function I/Os. 0000: AF0 0001: AF1 0010: AF2 0011: AF3 0100: AF4 0101: AF5 0110: AF6 0111: AF7 1000: AF8 1001: AF9 1010: AF10 1011: AF11 1100: AF12 1101: AF13 1110: AF14 1111: AF15 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A to E and H) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 AFSEL15[3:0] 26 25 24 23 AFSEL14[3:0] 22 21 20 19 AFSEL13[3:0] 18 17 16 AFSEL12[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw AFSEL11[3:0] rw rw rw AFSEL10[3:0] rw rw AFSEL9[3:0] rw rw AFSEL8[3:0] rw Bits 31:0 AFSEL[15:8][3:0]: Alternate function selection for port x I/O pin y (y = 15 to 8) These bits are written by software to configure alternate function I/Os. 0000: AF0 0001: AF1 0010: AF2 0011: AF3 0100: AF4 0101: AF5 0110: AF6 0111: AF7 1000: AF8 1001: AF9 1010: AF10 1011: AF11 1100: AF12 1101: AF13 1110: AF14 1111: AF15 272/1600 RM0394 Rev 4 rw rw RM0394 General-purpose I/Os (GPIO) 8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to E and H) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 BR[15:0]: Port x reset IO pin y (y = 15 to 0) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODx bit 1: Reset the corresponding ODx bit RM0394 Rev 4 273/1600 275 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 GPIOx_IDR (where x = A..E,H) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 274/1600 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0394 Rev 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GPIOx_OTYPER (where x = A..E,H) Reset value 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OT1 OT0 MODE0[1:0] MODE0[1:0] 1 0 0 0 0 0 0 0 0 0 0 0 0 OSPEED0[1:0] MODE1[1:0] 1 OSPEED0[1:0] MODE1[1:0] 1 PUPD0[1:0] OT2 1 PUPD0[1:0] OT3 1 OSPEED1[1:0] MODE2[1:0] 0 OSPEED1[1:0] MODE2[1:0] 1 PUPD1[1:0] OT4 1 PUPD1[1:0] OT5 1 OSPEED2[1:0] MODE3[1:0] 0 OSPEED2[1:0] MODE3[1:0] 1 PUPD2[1:0] OT6 1 PUPD2[1:0] OT7 1 OSPEED3[1:0] MODE4[1:0] 1 OSPEED3[1:0] MODE4[1:0] 1 PUPD3[1:0] OT8 1 PUPD3[1:0] OT9 1 OSPEED4[1:0] 1 OSPEED4[1:0] MODE5[1:0] 1 PUPD4[1:0] MODE5[1:0] 1 PUPD4[1:0] OT11 OT10 1 OSPEED5[1:0] MODE6[1:0] 1 OSPEED5[1:0] MODE6[1:0] 1 PUPD5[1:0] OT12 1 PUPD5[1:0] OT13 1 OSPEED6[1:0] 1 OSPEED6[1:0] MODE7[1:0] MODE8[1:0] MODE9[1:0] MODE10[1:0] MODE11[1:0] MODE12[1:0] MODE13[1:0] MODE14[1:0] 1 PUPD6[1:0] MODE7[1:0] MODE8[1:0] MODE9[1:0] MODE10[1:0] MODE11[1:0] MODE12[1:0] MODE13[1:0] MODE14[1:0] 1 PUPD6[1:0] OT14 OSPEED7[1:0] 1 OT15 OSPEED7[1:0] 1 Res. 1 PUPD7[1:0] OSPEED8[1:0] OSPEED9[1:0] OSPEED10[1:0] OSPEED11[1:0] OSPEED12[1:0] OSPEED13[1:0] OSPEED14[1:0] MODE15[1:0] 1 PUPD7[1:0] OSPEED8[1:0] 0 PUPD8[1:0] 0 PUPD8[1:0] OSPEED9[1:0] 0 PUPD9[1:0] 0 PUPD9[1:0] OSPEED10[1:0] 0 PUPD10[1:0] 0 PUPD10[1:0] 0 0 1 1 x x x x x x x x x x x x x x x x PUPD0[1:0] 0 0 0 1 1 PUPD1[1:0] 0 OSPEED11[1:0] 0 PUPD11[1:0] 1 PUPD11[1:0] 0 0 1 1 PUPD2[1:0] 0 OSPEED12[1:0] 0 PUPD12[1:0] OSPEED13[1:0] 0 PUPD12[1:0] PUPD13[1:0] 0 PUPD13[1:0] 0 0 0 0 1 1 PUPD3[1:0] 0 1 0 0 1 1 PUPD4[1:0] Reset value 1 0 1 1 1 PUPD5[1:0] GPIOB_PUPDR 0 1 1 1 PUPD6[1:0] 0x0C 0 0 0 1 1 PUPD7[1:0] Reset value 0 1 1 PUPD8[1:0] GPIOA_PUPDR 0 1 0 PUPD9[1:0] 0x0C 0 1 1 PUPD10[1:0] Reset value 1 0 PUPD11[1:0] GPIOx_OSPEEDR (where x = B..E,H) 0 1 PUPD12[1:0] Reset value 0 PUPD13[1:0] GPIOA_OSPEEDR OSPEED14[1:0] GPIOx_MODER (where x = C..E,H) 1 PUPD14[1:0] Reset value PUPD14[1:0] 0x08 GPIOB_MODER MODE15[1:0] 0x00 1 PUPD14[1:0] 0x08 1 Res. 0x04 Reset value Res. Reset value OSPEED15[1:0] 0x00 MODE0[1:0] MODE1[1:0] MODE2[1:0] MODE3[1:0] MODE4[1:0] MODE5[1:0] MODE6[1:0] MODE7[1:0] MODE8[1:0] MODE9[1:0] MODE10[1:0] MODE11[1:0] MODE12[1:0] MODE13[1:0] MODE14[1:0] MODE15[1:0] GPIOA_MODER OSPEED15[1:0] 0x00 PUPD15[1:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Register name PUPD15[1:0] 8.4.12 PUPD15[1:0] GPIOx_PUPDR (where x = C..E and H) Res. Reset value 0x0C Res. General-purpose I/Os (GPIO) RM0394 GPIO register map The following table gives the GPIO register map and reset values. Table 37. GPIO register map and reset values 1 1 1 1 1 1 0 0 0 0 RM0394 General-purpose I/Os (GPIO) LCK3 LCK2 LCK1 LCK0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x28 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. OD0 LCK4 0 OD1 LCK5 0 BS0 LCK6 0 OD2 LCK7 0 0 BS1 LCK8 0 OD3 LCK9 0 0 BS2 LCK10 0 OD4 LCK11 0 0 BS3 LCK12 Reset value GPIOx_BRR (where x = A..E,H) OD5 LCK13 0x24 GPIOx_AFRH (where x = A..E,H) 0 BS4 LCK14 0x20 OD6 LCK15 0 0 BS5 LCKK 0 OD7 Res. 0 0 BS6 Res. 0 OD8 Res. 0 0 BS7 Res. 0 OD9 Res. 0 0 BS8 Res. 0 0 BS9 Res. 0 OD11 Res. 0 OD10 Res. 0 0 BS10 Res. 0 OD12 Res. 0 0 BS11 Res. 0 OD13 Res. 0 0 BS12 Res. 0 OD14 Res. 0 GPIOx_AFRL (where x = A..E,H) 0 BS13 0x1C 0 BS14 0 OD15 BR1 0 0 BS15 BR2 0 Res. BR3 0 0 BR0 BR4 0 Res. BR5 0 Res. BR6 0 Res. BR7 0 Res. BR8 0 Res. BR9 0 Res. BR10 0 Res. BR11 0 Res. BR12 0 Res. BR13 0 Res. BR14 0 Res. BR15 Reset value GPIOx_LCKR (where x = A..E,H) Res. 0x18 GPIOx_BSRR (where x = A..E,H) Res. GPIOx_ODR (where x = A..E,H) Res. 0x14 Res. Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 37. GPIO register map and reset values (continued) Reset value Reset value Reset value AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFSEL15[3:0 AFSEL14[3:0 AFSEL13[3:0 AFSEL12[3:0 AFSEL11[3:0 AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0] ] ] ] ] ] Reset value Refer to Section 2.2 for the register boundary addresses. RM0394 Rev 4 275/1600 275 System configuration controller (SYSCFG) RM0394 9 System configuration controller (SYSCFG) 9.1 SYSCFG main features The STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx devices feature a set of configuration registers. The main purposes of the system configuration controller are the following: • Remapping memory areas • Managing the external interrupt line connection to the GPIOs • Managing robustness feature • Setting SRAM2 write protection and software erase • Configuring FPU interrupts • Enabling the firewall • Enabling /disabling I2C Fast-mode Plus driving capability on some I/Os and voltage booster for I/Os analog switches. 9.2 SYSCFG registers 9.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP) This register is used for specific configurations on memory remap. Address offset: 0x00 Reset value: 0x0000 000X (X is the memory mode selected by the BOOT0 pin and BOOT1 option bit) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res MEM_MODE rw rw rw Bits 31:3 Reserved, must be kept at reset value. Bits 2:0 MEM_MODE: Memory mapping selection These bits control the memory internal mapping at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the BOOT mode setting. After reset these bits take the value selected by BOOT0 (pin or option bit depending on nSWBOOT0 option bit) and BOOT1 option bit. 000: Main Flash memory mapped at 0x00000000. 001: System Flash memory mapped at 0x00000000. 010: Reserved 011: SRAM1 mapped at 0x00000000. 100: Reserved 101: Reserved 110: QUADSPI memory mapped at 0x00000000. 111: Reserved 276/1600 RM0394 Rev 4 RM0394 System configuration controller (SYSCFG) Note: In remap mode, the CPU can access the external memory via ICode bus instead of System bus which boosts up the performance. 9.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1) Address offset: 0x04 Reset value: 0x7C00 0001 31 30 29 28 27 26 FPU_IE[5..0] rw rw rw rw rw rw 15 14 13 12 11 10 Res Res Res Res Res Res 25 24 Res Res 9 8 Res BOOST EN 23 22 21 20 19 18 17 16 I2C_ PB8_ FMP I2C_ PB7_ FMP I2C_ PB6_ FMP I2C4_ FMP I2C3_ FMP I2C2_ FMP I2C1_ FMP I2C_ PB9_ FMP rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res FWDIS rw rc_w0 Bits 31:26 FPU_IE[5..0]: Floating Point Unit interrupts enable bits FPU_IE[5]: Inexact interrupt enable FPU_IE[4]: Input denormal interrupt enable FPU_IE[3]: Overflow interrupt enable FPU_IE[2]: underflow interrupt enable FPU_IE[1]: Divide-by-zero interrupt enable FPU_IE[0]: Invalid operation interrupt enable Bits 25:24 Reserved, must be kept at reset value. Bit 23 I2C4_FMP: Fast-mode Plus driving capability activation This bit enables the Fm+ driving mode on I2C4 pins selected through AF selection bits. 0: Fm+ mode is not enabled on I2C4 pins selected through AF selection bits 1: Fm+ mode is enabled on I2C4 pins selected through AF selection bits. Bit 22 I2C3_FMP: I2C3 Fast-mode Plus driving capability activation This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits. 0: Fm+ mode is not enabled on I2C3 pins selected through AF selection bits 1: Fm+ mode is enabled on I2C3 pins selected through AF selection bits. Bit 21 I2C2_FMP: I2C2 Fast-mode Plus driving capability activation This bit enables the Fm+ driving mode on I2C2 pins selected through AF selection bits. 0: Fm+ mode is not enabled on I2C2 pins selected through AF selection bits 1: Fm+ mode is enabled on I2C2 pins selected through AF selection bits. Bit 20 I2C1_FMP: I2C1 Fast-mode Plus driving capability activation This bit enables the Fm+ driving mode on I2C1 pins selected through AF selection bits. 0: Fm+ mode is not enabled on I2C1 pins selected through AF selection bits 1: Fm+ mode is enabled on I2C1 pins selected through AF selection bits. Bit 19 I2C_PB9_FMP: Fast-mode Plus (Fm+) driving capability activation on PB9 This bit enables the Fm+ driving mode for PB9. 0: PB9 pin operates in standard mode. 1: Fm+ mode enabled on PB9 pin, and the Speed control is bypassed. RM0394 Rev 4 277/1600 287 System configuration controller (SYSCFG) RM0394 Bit 18 I2C_PB8_FMP: Fast-mode Plus (Fm+) driving capability activation on PB8 This bit enables the Fm+ driving mode for PB8. 0: PB8 pin operates in standard mode. 1: Fm+ mode enabled on PB8 pin, and the Speed control is bypassed. Bit 17 I2C_PB7_FMP: Fast-mode Plus (Fm+) driving capability activation on PB7 This bit enables the Fm+ driving mode for PB7. 0: PB7 pin operates in standard mode. 1: Fm+ mode enabled on PB7 pin, and the Speed control is bypassed. Bit 16 I2C_PB6_FMP: Fast-mode Plus (Fm+) driving capability activation on PB6 This bit enables the Fm+ driving mode for PB6. 0: PB6 pin operates in standard mode. 1: Fm+ mode enabled on PB6 pin, and the Speed control is bypassed. Bits 15:9 Reserved, must be kept at reset value. Bit 8 BOOSTEN: I/O analog switch voltage booster enable 0: I/O analog switches are supplied by VDDA voltage. This is the recommended configuration when using the ADC in high VDDA voltage operation. 1: I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD). This is the recommended configuration when using the ADC in low VDDA voltage operation. Bits 7:1 Reserved, must be kept at reset value. Bit 0 FWDIS: Firewall disable This bit is cleared by software to protect the access to the memory segments according to the Firewall configuration. Once enabled, the firewall cannot be disabled by software. Only a system reset set the bit. 0 : Firewall protection enabled 1 : Firewall protection disabled 9.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res EXTI3[2:0] rw 278/1600 rw Res rw EXTI2[2:0] rw rw Res rw RM0394 Rev 4 EXTI1[2:0] rw rw Res rw EXTI0[2:0] rw rw rw RM0394 System configuration controller (SYSCFG) Bits 31:15 Reserved, must be kept at reset value. Bits 14:12 EXTI3[2:0]: EXTI 3 configuration bits These bits are written by software to select the source input for the EXTI3 external interrupt. 000: PA[3] pin 001: PB[3] pin 010: PC[3] pin 011: PD[3] pin 100: PE[3] pin 101: Reserved 110: Reserved 111: PH[3] pin Bit 11 Reserved, must be kept at reset value. Bits 10:8 EXTI2[2:0]: EXTI 2 configuration bits These bits are written by software to select the source input for the EXTI2 external interrupt. 000: PA[2] pin 001: PB[2] pin 010: PC[2] pin 011: PD[2] pin 100: PE[2] pin 101: Reserved 110: Reserved 111: Reserved Bit 7 Reserved, must be kept at reset value. Bits 6:4 EXTI1[2:0]: EXTI 1 configuration bits These bits are written by software to select the source input for the EXTI1 external interrupt. 000: PA[1] pin 001: PB[1] pin 010: PC[1] pin 011: PD[1] pin 100: PE[1] pin 101: Reserved 110: Reserved 111: PH[1] pin Bit 3 Reserved, must be kept at reset value. Bits 2:0 EXTI0[2:0]: EXTI 0 configuration bits These bits are written by software to select the source input for the EXTI0 external interrupt. 000: PA[0] pin 001: PB[0] pin 010: PC[0] pin 011: PD[0] pin 100: PE[0] pin 101: Reserved 110: Reserved 111: PH[0] pin RM0394 Rev 4 279/1600 287 System configuration controller (SYSCFG) 9.2.4 RM0394 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res EXTI7[2:0] rw rw Res rw EXTI6[2:0] rw rw Res rw EXTI5[2:0] rw rw Res rw EXTI4[2:0] rw rw Bits 31:15 Reserved, must be kept at reset value. Bits 14:12 EXTI7[2:0]: EXTI 7 configuration bits These bits are written by software to select the source input for the EXTI7 external interrupt. 000: PA[7] pin 001: PB[7] pin 010: PC[7] pin 011: PD[7] pin 100: PE[7] pin 101: Reserved 110: Reserved 111: Reserved Bit 11 Reserved, must be kept at reset value. Bits 10:8 EXTI6[2:0]: EXTI 6 configuration bits These bits are written by software to select the source input for the EXTI6 external interrupt. 000: PA[6] pin 001: PB[6] pin 010: PC[6] pin 011: PD[6] pin 100: PE[6] pin 101: Reserved 110: Reserved 111: Reserved Bit 7 Reserved, must be kept at reset value. 280/1600 RM0394 Rev 4 rw RM0394 System configuration controller (SYSCFG) Bits 6:4 EXTI5[2:0]: EXTI 5 configuration bits These bits are written by software to select the source input for the EXTI5 external interrupt. 000: PA[5] pin 001: PB[5] pin 010: PC[5] pin 011: PD[5] pin 100: PE[5] pin 101: Reserved 110: Reserved 111: Reserved Bit 3 Reserved, must be kept at reset value. Bits 2:0 EXTI4[2:0]: EXTI 4 configuration bits These bits are written by software to select the source input for the EXTI4 external interrupt. 000: PA[4] pin 001: PB[4] pin 010: PC[4] pin 011: PD[4] pin 100: PE[4] pin 101: Reserved 110: Reserved 111: Reserved Note: Some of the I/O pins mentioned in the above register may not be available on small packages. 9.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res EXTI11[2:0] rw rw Res rw EXTI10[2:0] rw rw Res rw RM0394 Rev 4 EXTI9[2:0] rw rw Res rw EXTI8[2:0] rw rw rw 281/1600 287 System configuration controller (SYSCFG) RM0394 Bits 31:15 Reserved, must be kept at reset value. Bits 14:12 EXTI11[2:0]: EXTI 11 configuration bits These bits are written by software to select the source input for the EXTI11 external interrupt. 000: PA[11] pin 001: PB[11] pin 010: PC[11] pin 011: PD[11] pin 100: PE[11] pin 101: Reserved 110: Reserved 111: Reserved Bit 11 Reserved, must be kept at reset value. Bits 10:8 EXTI10[2:0]: EXTI 10 configuration bits These bits are written by software to select the source input for the EXTI10 external interrupt. 000: PA[10] pin 001: PB[10] pin 010: PC[10] pin 011: PD[10] pin 100: PE[10] pin 101: Reserved 110: Reserved 111: Reserved Bit 7 Reserved, must be kept at reset value. Bits 6:4 EXTI9[2:0]: EXTI 9 configuration bits These bits are written by software to select the source input for the EXTI9 external interrupt. 000: PA[9] pin 001: PB[9] pin 010: PC[9] pin 011: PD[9] pin 100: PE[9] pin 101: Reserved 110: Reserved 111: Reserved Bit 3 Reserved, must be kept at reset value. Bits 2:0 EXTI8[2:0]: EXTI 8 configuration bits These bits are written by software to select the source input for the EXTI8 external interrupt. 000: PA[8] pin 001: PB[8] pin 010: PC[8] pin 011: PD[8] pin 100: PE[8] pin 101: Reserved 110: Reserved 111: Reserved Note: 282/1600 Some of the I/O pins mentioned in the above register may not be available on small packages. RM0394 Rev 4 RM0394 System configuration controller (SYSCFG) 9.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res EXTI15[2:0] rw rw Res rw EXTI14[2:0] rw rw Res rw EXTI13[2:0] rw rw Res rw EXTI12[2:0] rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bits 14:12 EXTI15[2:0]: EXTI15 configuration bits These bits are written by software to select the source input for the EXTI15 external interrupt. 000: PA[15] pin 001: PB[15] pin 010: PC[15] pin 011: PD[15] pin 100: PE[15] pin 101: Reserved 110: Reserved 111: Reserved Bit 11 Reserved, must be kept at reset value. Bits 10:8 EXTI14[2:0]: EXTI14 configuration bits These bits are written by software to select the source input for the EXTI14 external interrupt. 000: PA[14] pin 001: PB[14] pin 010: PC[14] pin 011: PD[14] pin 100: PE[14] pin 101: Reserved 110: Reserved 111: Reserved Bit 7 Reserved, must be kept at reset value. RM0394 Rev 4 283/1600 287 System configuration controller (SYSCFG) RM0394 Bits 6:4 EXTI13[2:0]: EXTI13 configuration bits These bits are written by software to select the source input for the EXTI13 external interrupt. 000: PA[13] pin 001: PB[13] pin 010: PC[13] pin 011: PD[13] pin 100: PE[13] pin 101: Reserved 110: Reserved 111: Reserved Bit 3 Reserved, must be kept at reset value. Bits 2:0 EXTI12[2:0]: EXTI12 configuration bits These bits are written by software to select the source input for the EXTI12 external interrupt. 000: PA[12] pin 001: PB[12] pin 010: PC[12] pin 011: PD[12] pin 100: PE[12] pin 101: Reserved 110: Reserved 111: Reserved Note: Some of the I/O pins mentioned in the above register may not be available on small packages. 9.2.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR) Address offset: 0x18 System reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res Res Res Res Res Res Res SRAM2 SRAM2 BSY ER r rw Bits 31:2 Reserved, must be kept at reset value Bit 1 SRAM2BSY: SRAM2 busy by erase operation 0: No SRAM2 erase operation is on going. 1: SRAM2 erase operation is on going. Bit 0 SRAM2ER: SRAM2 Erase Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at the end of the SRAM2 erase operation. Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register. 284/1600 RM0394 Rev 4 RM0394 System configuration controller (SYSCFG) 9.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2) Address offset: 0x1C System reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res SPF Res Res Res Res ECCL PVDL SPL CLL rs rs rs rs rc_w1 Bits 31:9 Reserved, must be kept at reset value Bit 8 SPF: SRAM2 parity error flag This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing ‘1’. 0: No SRAM2 parity error detected 1: SRAM2 parity error detected Bits 7:4 Reserved, must be kept at reset value Bit 3 ECCL: ECC Lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Flash ECC error connection to TIM1/15/16 Break input. 0: ECC error disconnected from TIM1/15/16 Break input. 1: ECC error connected to TIM1/15/16 Break input. Bit 2 PVDL: PVD lock enable bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. 0: PVD interrupt disconnected from TIM1/15/16 Break input. PVDE and PLS[2:0] bits can be programmed by the application. 1: PVD interrupt connected to TIM1/15/16 Break input, PVDE and PLS[2:0] bits are read only. Bit 1 SPL: SRAM2 parity lock bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/15/16 Break inputs. 0: SRAM2 parity error signal disconnected from TIM1/15/16 Break inputs 1: SRAM2 parity error signal connected to TIM1/15/16 Break inputs Bit 0 CLL: Cortex®-M4 LOCKUP (Hardfault) output enable bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of Cortex®-M4 LOCKUP (Hardfault) output to TIM1/15/16 Break input 0: Cortex®-M4 LOCKUP output disconnected from TIM1/15/16 Break inputs 1: Cortex®-M4 LOCKUP output connected to TIM1/15/16 Break inputs RM0394 Rev 4 285/1600 287 System configuration controller (SYSCFG) 9.2.9 RM0394 SYSCFG SRAM2 write protection register (SYSCFG_SWPR) Address offset: 0x20 System reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P31WP P30WP P29WP P28WP P27WP P26WP P25WP P24WP P23WP P22WP P21WP P20WP P19WP P18WP P17WP P16WP rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P9WP P8WP P7WP P6WP P5WP P4WP P3WP P2WP P1WP P0WP rs rs rs rs rs rs rs rs rs rs P15WP P14WP P13WP P12WP P11WP P10WP rs rs rs rs rs rs Bits 31:0 PxWP (x = 0 to 31): SRAM2 page x write protection These bits are set by software and cleared only by a system reset. 0: Write protection of SRAM2 page x is disabled. 1: Write protection of SRAM2 page x is enabled. Note: PxWP (x = 16 to 31) available on STM32L45x and STM32L46x devices only. 9.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR) Address offset: 0x24 System reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res w w w w w w w KEY[7:0] w Bits 31:8 Reserved, must be kept at reset value Bits 7:0 KEY[7:0]: SRAM2 write protection key for software erase The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register. 1. Write "0xCA” into Key[7:0] 2. Write "0x53” into Key[7:0] Writing a wrong key reactivates the write protection. 286/1600 RM0394 Rev 4 P27WP P26WP P25WP P24WP P23WP P22WP P21WP P20WP P19WP P18WP P17WP P16WP P15WP P14WP P13WP P12WP P11WP P10WP P9WP P8WP P7WP P6WP P5WP P4WP Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFG_SKR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x24 SYSCFG_SWPR Res. 0x20 P28WP RM0394 Rev 4 Reset value 0 0 0 0 0 0 CLL 0 SPL 0 0 0 0 0 KEY 0 0 0 0 0 0 0 0 0 0 0 Reset value SRAM2ER 0 SRAM2BSY EXTI13 [2:0] P0WP Res. Res. Res. I2C_PB8_FMP I2C_PB7_FMP I2C_PB6_FMP x x x Res. Res. Res. FWDIS Res. Res. Res. Res. BOOSTEN Res. Res. Res. Res. Res. Res. Reset value Res. 0 Res. EXTI9 [2:0] Res. 0 0 Res. 0 Res. Res. EXTI5 [2:0] PVDL 0 EXTI1 [2:0] ECCL 0 0 0 Res. 0 Res. EXTI14 [2:0] Res. Res. I2C_PB9_FMP 0 P1WP Reset value 0 Res. 0 Res. EXTI10 [2:0] Res. 0 Res. Res. EXTI6 [2:0] 0 Res. 0 0 0 0 Res. 0 EXTI2 [2:0] Res. 0 0 0 SPF 0 Res. EXTI15 [2:0] 0 Res. 0 Res. 0 Res. EXTI11 [2:0] Res. EXTI7 [2:0] Res. 0 0 0 Res. Reset value EXTI3 [2:0] Res. Reset value Res. 0 0 Res. Reset value Res. 0 Res. Reset value Res. I2C1_FMP 0 Res. I2C2_FMP 0 Res. I2C3_FMP 0 Res. Res. Res. Res. Res. Res. Res. Res. I2C4_FMP Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 P2WP SYSCFG_CFGR2 1 Res. SYSCFG_SCSR 1 Res. SYSCFG_EXTICR4 1 Res. SYSCFG_EXTICR3 0 Res. SYSCFG_EXTICR2 Res. SYSCFG_EXTICR1 FPU_IE[5..0] P3WP 0x1C P29WP 0x18 Res. 0x14 Res. 0x10 SYSCFG_CFGR1 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SYSCFG_ MEMRMP Res. 0x00 Res. Register Res. Offset Res. 0x0C P30WP 0x08 P31WP 0x04 Res. 9.2.11 Res. RM0394 System configuration controller (SYSCFG) SYSCFG register map The following table gives the SYSCFG register map and the reset values. Table 38. SYSCFG register map and reset values MEM_ MODE 0 0 0 1 EXTI0 [2:0] 0 0 0 0 EXTI4 [2:0] 0 EXTI8 [2:0] 0 EXTI12 [2:0] 0 0 0 0 0 0 Refer to Section 2.2.2 on page 67 for the register boundary addresses. 287/1600 287 Peripherals interconnect matrix RM0394 10 Peripherals interconnect matrix 10.1 Introduction Several peripherals have direct connections between them. This allows autonomous communication and or synchronization between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections remove software latency and allow design of predictable system. Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes. 10.2 Connection summary Table 39. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx peripherals interconnect matrix(1) (2) TIM1 TIM2 TIM6 TIM7 TIM15 TIM16 LPTIM1 LPTIM2 ADC1 ADC2 OPAMP1 DAC1 DAC2 COMP1 COMP2 IRTIM Destination TIM1 - 1 - - 1 - - - 2 2 - - - 7 - - TIM2 1 - - - - - - - 2 2 - 4 4 7 - - TIM6 - - - - - - - - 2 2 - 4 4 - - - TIM7 - - - - - - - - - - - 4 4 - - - TIM15 1 - - - - - - - 2 2 - 4 4 - 7 12 TIM16 - - - - 1 - - - - - - - - - - 12 LPTIM1 - - - - - - - - - - - - - - - - LPTIM2 - - - - - - - - - - - - - - - - ADC1 3 - - - - - - - - - - - - - - - T. Sensor - - - - - - - - 9 - - - - - - - VBAT - - - - - - - - 9 - - - - - - - VREFINT - - - - - - - - 9 - - - - - - - OPAMP1 - - - - - - - - 9 9 - - - - - - DAC1 - - - - - - - - 9 - 9 - - - - - DAC2 - - - - - - - - 9 - - - - - - - HSE - - - - - 5 - - - - - - - - - - LSE - 5 - - 5 5 - - - - - - - - - - MSI - - - - - 5 - - - - - - - - - - LSI - - - - - 5 - - - - - - - - - - Source - 288/1865 RM0394 Rev 4 RM0394 Peripherals interconnect matrix Table 39. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx peripherals interconnect matrix(1) (2) TIM1 TIM2 TIM6 TIM7 TIM15 TIM16 LPTIM1 LPTIM2 ADC1 ADC2 OPAMP1 DAC1 DAC2 COMP1 COMP2 IRTIM Destination MCO - - - - - 5 - - - - - - - - - - EXTI - - - - - - - - 2 2 - 4 4 - - - RTC - - - - - 5 6 6 - - - - - - - - COMP1 10 10 - - 10 10 6 6 - - - - - - - - COMP2 10 10 - - 10 10 6 6 - - - - - - - - SYST ERR 11 - - - 11 11 - - - - - - - - - - USB(3) - 8 - - - - - - - - - - - - - - Source - 1. Numbers in table are links to corresponding detailed sub-section in Section 10.3: Interconnection details. 2. The “-” symbol in grayed cells means no interconnect. 3. Not available for STM32L431xx devices. 10.3 Interconnection details 10.3.1 From timer (TIM1/TIM2/TIM15/TIM16) to timer (TIM1/TIM2/TIM15/TIM16) Purpose Some of the TIMx timers are linked together internally for timer synchronization or chaining. When one timer is configured in Master Mode, it can reset, start, stop or clock the counter of another timer configured in Slave Mode. A description of the feature is provided in: Section 27.3.19: Timer synchronization. The modes of synchronization are detailed in: • Section 27.3.19: Timer synchronization for advanced-control timers (TIM1) • Section 27.3.18: Timers and external trigger synchronization for general-purpose timers (TIM2) • Section 28.5.18: External trigger synchronization (TIM15 only) for general-purpose timer (TIM15) Triggering signals The output (from Master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1) following a configurable timer event. The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3 The input and output signals for TIM1 are shown in Figure 183: Advanced-control timer block diagram. The possible master/slave connections are given in: • Table 132: TIM1 internal trigger connection RM0394 Rev 4 289/1865 294 Peripherals interconnect matrix RM0394 Active power mode Run, Sleep, Low-power run, Low-power sleep. 10.3.2 From timer (TIM1/TIM2/TIM6/TIM15) and EXTI to ADC (ADC1) Purpose General-purpose timers (TIM2), basic timer (TIM6), advanced-control timer (TIM1), generalpurpose timer (TIM15) and EXTI can be used to generate an ADC triggering event. TIMx synchronization is described in: Section 26.3.5: Clock selection (TIM1). ADC synchronization is described in: Section 16.4.18: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN,JEXTSEL, JEXTEN). Triggering signals The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event. The input (to ADC) is on signal EXT[15:0], JEXT[15:0]. The connection between timers and ADC is provided in: • Table 59: ADC1 and ADC2 - External triggers for regular channels • Table 60: ADC1 and ADC2 - External trigger for injected channels Active power mode Run, Sleep, Low-power run, Low-power sleep. 10.3.3 From ADC (ADC1) to timer (TIM1) Purpose ADC1 can provide trigger event through watchdog signals to advanced-control timers (TIM1). A description of the ADC analog watchdog setting is provided in: Section 16.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx). Trigger settings on the timer are provided in: Section 26.3.4: External trigger input. Triggering signals The output (from ADC) is on signals ADCn_AWDx_OUT n = 1, 2, 3 (for ADC1) x = 1, 2, 3 (3 watchdog per ADC) and the input (to timer) on signal TIMx_ETR (external trigger). Active power mode Run, Sleep, Low-power run, Low-power sleep. 10.3.4 From timer (TIM2/TIM6/TIM7) and EXTI to DAC (DAC1/DAC2) Purpose General-purpose timer (TIM2), basic timers (TIM6, TIM7), and EXTI can be used as triggering event to start a DAC conversion. 290/1865 RM0394 Rev 4 RM0394 Peripherals interconnect matrix Triggering signals The output (from timer) is on signal TIMx_TRGO directly connected to corresponding DAC inputs. Selection of input triggers on DAC is provided in Section 17.4.6: DAC trigger selection (single and dual mode). Active power mode Run, Sleep, Low-power run, Low-power sleep. 10.3.5 From HSE, LSE, LSI, MSI, MCO, RTC to timer (TIM2/TIM15/TIM16) Purpose External clocks (HSE, LSE), internal clocks (LSI, MSI), microcontroller output clock (MCO), GPIO and RTC wakeup interrupt can be used as input to general-purpose timer (TIM15/16) channel 1. This allows to calibrate the HSI16/MSI system clocks (with TIM15/TIM16 and LSE) or LSI (with TIM16 and HSE). This is also used to precisely measure LSI (with TIM16 and HSI16) or MSI (with and HSI16) oscillator frequency. When Low Speed External (LSE) oscillator is used, no additional hardware connections are required. This feature is described in Section 6.2.17: Internal/external clock measurement with TIM15/TIM16. External clock LSE can be used as input to general-purpose timers (TIM2) on TIM2_ETR pin, see Section 27.4.19: TIM2 option register 1 (TIM2_OR1). Active power mode Run, Sleep, Low-power run, Low-power sleep. 10.3.6 From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2) Purpose RTC alarm A/B, RTC_TAMP1/2/3 input detection, COMP1/2_OUT can be used as trigger to start LPTIM counters (LPTIM1/2). Triggering signals This trigger feature is described in Section 30.4.6: Trigger multiplexer (and following sections). The input selection is described in Table 146: LPTIM1 external trigger connection. Active power mode Run, Sleep, Low-power run, Low-power sleep, Stop 0, Stop 1, Stop 2 (LPTIM1 only). RM0394 Rev 4 291/1865 294 Peripherals interconnect matrix 10.3.7 RM0394 From timer (TIM1/TIM2/TIM15) to comparators (COMP1/COMP2) Purpose Advanced-control timer (TIM1), general-purpose timer (TIM2) and general-purpose timer (TIM15) can be used as blanking window input to COMP1/COMP2 The blanking function is described in Section 19.3.7: Comparator output blanking function. The blanking sources are given in: • Section 19.6.1: Comparator 1 control and status register (COMP1_CSR) bits 20:18 BLANKING[2:0] • Section 19.6.2: Comparator 2 control and status register (COMP2_CSR) bits 20:18 BLANKING[2:0] Triggering signals Timer output signal TIMx_Ocx are the inputs to blanking source of COMP1/COMP2. Active power mode Run, Sleep, Low-power run, Low-power sleep. 10.3.8 From ADC (ADC1) to ADC (ADC2) Purpose ADC1 can be used as a “master” to trigger ADC2 “slave” start of conversion. In dual ADC mode, the converted data of the master and slave ADCs can be read in parallel. A description of dual ADC mode is provided in: Section 16.4.31: Dual ADC modes. Triggering signals Internal to the ADCs. Active power mode Run, Sleep, Low-power run, Low-power sleep. 10.3.9 From USB to timer (TIM2) Purpose USB (FS SOF) can generate a trigger to general-purpose timer (TIM2). Connection of USB to TIM2 is described in . Triggering signals Internal signal generated by USB FS Start Of Frame. Active power mode Run, Sleep. 292/1865 RM0394 Rev 4 RM0394 10.3.10 Peripherals interconnect matrix From internal analog source to ADC (ADC1) and OPAMP (OPAMP1) Purpose Internal temperature sensor (VTS) and VBAT monitoring channel are connected to ADC1 input channels. Internal reference voltage (VREFINT) is connected to ADC1 input channels. OPAMP1 output can be connected to ADC1 input channel through the GPIO. DAC1_OUT1 and DAC1_OUT2 outputs can be connected to input channel. DAC1_OUT1 can be connected to OPAMP1_VINP. This is according: • Section 16.2: ADC main features • Section 16.4.11: Channel selection (SQRx, JSQRx) • Figure 41: ADC1 connectivity • Table 90: Operational amplifier possible connections Active power mode Run, Sleep, Low-power run, Low-power sleep. 10.3.11 From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM15/TIM16) Purpose Comparators (COMP1/COMP2) output values can be connected to timers (TIM1/TIM2/TIM15/TIM16) input captures or TIMx_ETR signals. The connection to ETR is described in Section 26.3.4: External trigger input. Comparators (COMP1/COMP2) output values can also generate break input signals for timers (TIM1) on input pins TIMx_BKIN or TIMx_BKIN2 through GPIO alternate function selection using open drain connection of IO, see Section 26.3.17: Bidirectional break inputs. The possible connections are given in: • Section 26.4.23: TIM1 option register 1 (TIM1_OR1) • Section 26.4.27: TIM1 option register 2 (TIM1_OR2) • Section 27.4.19: TIM2 option register 1 (TIM2_OR1) • Section 27.4.20: TIM2 option register 2 (TIM2_OR2) • Section 28.3: TIM16 main features Active power mode Run, Sleep, Low-power run, Low-power sleep. RM0394 Rev 4 293/1865 294 Peripherals interconnect matrix 10.3.12 RM0394 From system errors to timers (TIM1/TIM15/TIM16) Purpose CSS, CPU hardfault, RAM parity error, FLASH ECC double error detection, PVD can generate system errors in the form of timer break toward timers (TIM1/TIM15/TIM16). The purpose of the break function is to protect power switches driven by PWM signals generated by the timers. List of possible source of break are described in: • Section 26.3.16: Using the break function (TIM1) • Section 28.5.13: Using the break function (TIM15/TIM16) • Figure 292: TIM15 block diagram • Figure 293: TIM16 block diagram Active power mode Run, Sleep, Low-power run, Low-power sleep. 10.3.13 From timers (TIM16) to IRTIM Purpose General-purpose timer (TIM16) output channel TIMx_OC1 are used to generate the waveform of infrared signal output. The functionality is described in Section 31: Infrared interface (IRTIM). Active power mode Run, Sleep, Low-power run, Low-power sleep. 294/1865 RM0394 Rev 4 RM0394 Direct memory access controller (DMA) 11 Direct memory access controller (DMA) 11.1 Introduction The direct memory access (DMA) controller is a bus master and system peripheral. The DMA is used to perform programmable data transfers between memory-mapped peripherals and/or memories, upon the control of an off-loaded CPU. The DMA controller features a single AHB master architecture. There are two instances of DMA, DMA1 and DMA2. Each channel is dedicated to managing memory access requests from one or more peripherals. Each DMA includes an arbiter for handling the priority between DMA requests. 11.2 DMA main features • Single AHB master • Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-toperipheral data transfers • Access, as source and destination, to on-chip memory-mapped devices such as Flash memory, SRAM, and AHB and APB peripherals • All DMA channels independently configurable: • – Each channel is associated either with a DMA request signal coming from a peripheral, or with a software trigger in memory-to-memory transfers. This configuration is done by software. – Priority between the requests is programmable by software (4 levels per channel: very high, high, medium, low) and by hardware in case of equality (such as request to channel 1 has priority over request to channel 2). – Transfer size of source and destination are independent (byte, half-word, word), emulating packing and unpacking. Source and destination addresses must be aligned on the data size. – Support of transfers from/to peripherals to/from memory with circular buffer management – Programmable number of data to be transferred: 0 to 216 - 1 Generation of an interrupt request per channel. Each interrupt request is caused from any of the three DMA events: transfer complete, half transfer, or transfer error. RM0394 Rev 4 295/1600 319 Direct memory access controller (DMA) 11.3 DMA implementation 11.3.1 DMA1 and DMA2 RM0394 DMA1 and DMA2 are implemented with the hardware configuration parameters shown in Table 40. Table 40. DMA1 and DMA2 implementation Feature DMA1 DMA2 7 7 Number of channels 11.3.2 DMA request mapping DMA controller The hardware requests from the peripherals (TIM1/2/3/6/7/15/16, ADC1, DAC_CH1/2, SPI1/2/3, I2C1/2/3/4, SDMMC1, QUADSPI, SWPMI1, SAI1, AES, USART1/2/3, UART4 and LPUART1) are mapped to the DMA channels through the DMA_CSELR channel selection registers (see Figure 25 and Figure 26). The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral. Table 41 show the list of DMA requests for each channel. 296/1600 RM0394 Rev 4 RM0394 Direct memory access controller (DMA) Figure 25. DMA1 request mapping 3HULSKHUDOUHTXHVWVLJQDOV '0$FKDQQHO &KDQQHO $'&7,0B&+ 6:WULJJHU 0(00(0ELW &KDQQHO &6 63,B7;86$57B5;,&B5; 7,0B&+7,0B837,0B83 '$&B&+7,0B&+7,0B&+ 7,0B83 6:WULJJHU 0(00(0ELW &KDQQHO &6 63,B5;86$57B7;,&B7; 7,0B83'$&B&+7,0B&+ 7,0B75,*7,0B&20')6'0B)/7 6:WULJJHU 0(00(0ELW &KDQQHO &KDQQHO &6 86$57B5;,&B7;7,0B&+ 7,0B837,0B837,0B&+ 7,0B75,* 6:WULJJHU 0(00(0ELW ,QWHUQDO'0$ UHTXHVW &6 63,B7;86$57B5;,&B5; 7,0B&+48$'63,7,0B&+ 7,0B837,0B75,*7,0B&20 ')6'0B)/7 6:WULJJHU 0(00(0ELW +LJKSULRULW\ &6 63,B5;86$57B7;,&B7; 7,0B837,0B&+7,0B&+ 6:WULJJHU 0(00(0ELW )L[HGKDUGZDUHSULRULW\ &KDQQHO &6 86$57B7;,&B5;7,0B&+ 7,0B&+7,0B&+ &KDQQHO /RZSULRULW\ 6:WULJJHU 0(00(0ELW &6 '0$B&6(/5 06Y9 RM0394 Rev 4 297/1600 319 Direct memory access controller (DMA) RM0394 Figure 26. DMA2 request mapping 3HULSKHUDOUHTXHVWVLJQDOV )L[HGKDUGZDUHSULRULW\ '0$FKDQQHO 6$,B$63,B5;6:30,B5;$(6B,1 ,&B5; +LJKSULRULW\ &KDQQHO 6:WULJJHU 0(00(0ELW &6 6$,B%63,B7;6:30,B7;$(6B287 ,&B7; &KDQQHO 6:WULJJHU 0(00(0ELW &6 &KDQQHO $'&63,B5;$(6B2878$57B7; 6:WULJJHU 0(00(0ELW &6 $'&7,0B83'$&B&+63,B7; 6'00&8$57B5; &KDQQHO 6:WULJJHU 0(00(0ELW ,QWHUQDO'0$ UHTXHVW &6 $'&7,0B83'$&B&+ $(6B,16'00& &KDQQHO 6:WULJJHU 0(00(0ELW &6 6$,B$86$57B7;/38$57B7; ,&B5; &KDQQHO 6:WULJJHU 0(00(0ELW &6 6$,B%86$57B5;48$'63, /38$57B5;,&B7; &KDQQHO /RZSULRULW\ 6:WULJJHU 0(00(0ELW &6 '0$B&6(/5 06Y9 Table 41. DMA1 requests for each channel CxS[3:0] Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 0000 ADC1 ADC2(1) - - DFSDM1_ FLT0(2) DFSDM1_ FLT1(2) - 0001 - SPI1_RX SPI1_TX SPI2_RX(3) SPI2_TX(3) SAI2_A(4) SAI2_B(4) 298/1600 RM0394 Rev 4 RM0394 Direct memory access controller (DMA) Table 41. DMA1 requests for each channel (continued) CxS[3:0] Channel 1 0010 - 0011 Channel 2 Channel 3 USART3_TX USART3_RX Channel 4 Channel 5 Channel 6 Channel 7 USART1_TX USART1_RX USART2_RX USART2_TX (3) (3) - I2C3_TX I2C3_RX I2C2_TX(3) I2C2_RX(3) I2C1_TX I2C1_RX 0100 TIM2_CH3 TIM2_UP TIM16_CH1 TIM16_UP - TIM2_CH1 TIM16_CH1 TIM16_UP TIM2_CH2 TIM2_CH4 0101 - TIM3_CH3(2) QUADSPI TIM3_CH1(2) TIM3_TRIG - 0110 - - 0111 - TIM1_CH1 TIM3_CH4(2) TIM7_UP. TIM3_UP(2) DAC_CH2(5) (2) TIM6_UP DAC_CH1 - - - - TIM1_CH2 TIM1_CH4 TIM1_TRIG TIM1_COM TIM15_CH1 TIM15_UP TIM15_TRIG TIM15_COM TIM1_UP TIM1_CH3 1. Available on STM32L412xx and STM32L422xx devices only. 2. Available on STM32L45xxx and STM32L46xxx devices only. 3. Not available on STM32L432xx and STM32L442xx devices. 4. Not available on STM32L412xx and STM32L422xx devices. 5. Available on STM32L43xx and STM32L44xx devices only. Table 42. DMA2 requests for each channel CxS[3:0] Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 0000 I2C4_RX(1) I2C4_TX(1) ADC1 ADC2(2) - - - 0001 SAI1_A SAI1_B - - - SAI1_A SAI1_B 0010 - - 0011 SPI3_RX SPI3_TX 0100 0101 0110 0111 AES_IN - (4) UART4_RX (1) - - TIM6_UP DAC_CH1 TIM7_UP DAC_CH2(3) - QUADSPI (3) SPI1_RX SPI1_TX - LPUART1_ TX LPUART1_ RX - - - - I2C1_RX I2C1_TX AES_OUT(4) AES_OUT(4) - AES_IN(4) - - - - SDMMC1(5) SDMMC1(5) - - SWPMI1_RX SWPMI1_TX (3) UART4_TX (1) USART1_TX USART1_RX 1. Available on STM32L45xxx and STM32L46xxx devices only. 2. Available on STM32L41xxx and STM32L42xxx devices only. 3. Available on STM32L43xxx and STM32L44xxx devices only. 4. Available on STM32L44xxx and STM32L46xxx devices only 5. Not available on STM32L432xx and STM32L442xx devices. 11.4 DMA functional description RM0394 Rev 4 299/1600 319 Direct memory access controller (DMA) 11.4.1 RM0394 DMA block diagram The DMA block diagram is shown in Figure 27. Figure 27. DMA block diagram ,EXV ,&RGH 'EXV '&RGH )ODVKLQWHUIDFH &RUWH[0ZLWK)38 6EXV %XVPDWUL[ 65$0 '0$ 65$0 )0&DQG4XDG63, &K &K $+%SHULSKHUDOV ZLWK'0$FDSDELOLW\ '0$ &K $'&$'&$'& $+% &5& '0$ &K &K 76& '0$ 5HVHW FORFNFRQWURO 5&& &K $3%SHULSKHUDOV ZLWK'0$FDSDELOLW\ %ULGJH $3% ')6'06$,6$,7,0 7,07,07,07,0 86$5763,6'00& $3%SHULSKHUDOV ZLWK'0$FDSDELOLW\ %ULGJH $3% '0$UHTXHVWV 6:30,/38$57 '$&B&+'$&B&+,& ,&,&86$5786$57 8$578$5763,63, 7,07,07,07,07,0 7,0 06Y9 The DMA controller performs direct memory transfer by sharing the AHB system bus with other system masters. The bus matrix implements round-robin scheduling. DMA requests may stop the CPU access to the system bus for a number of bus cycles, when CPU and DMA target the same destination (memory or peripheral). According to its configuration through the AHB slave interface, the DMA controller arbitrates between the DMA channels and their associated received requests. The DMA controller also schedules the DMA data transfers over the single AHB port master. The DMA controller generates an interrupt per channel to the interrupt controller. 300/1600 RM0394 Rev 4 RM0394 11.4.2 Direct memory access controller (DMA) DMA transfers The software configures the DMA controller at channel level, in order to perform a block transfer, composed of a sequence of AHB bus transfers. A DMA block transfer may be requested from a peripheral, or triggered by the software in case of memory-to-memory transfer. After an event, the following steps of a single DMA transfer occur: 1. The peripheral sends a single DMA request signal to the DMA controller. 2. The DMA controller serves the request, depending on the priority of the channel associated to this peripheral request. 3. As soon as the DMA controller grants the peripheral, an acknowledge is sent to the peripheral by the DMA controller. 4. The peripheral releases its request as soon as it gets the acknowledge from the DMA controller. 5. Once the request is de-asserted by the peripheral, the DMA controller releases the acknowledge. The peripheral may order a further single request and initiate another single DMA transfer. The request/acknowledge protocol is used when a peripheral is either the source or the destination of the transfer. For example, in case of memory-to-peripheral transfer, the peripheral initiates the transfer by driving its single request signal to the DMA controller. The DMA controller reads then a single data in the memory and writes this data to the peripheral. For a given channel x, a DMA block transfer consists of a repeated sequence of: • • a single DMA transfer, encapsulating two AHB transfers of a single data, over the DMA AHB bus master: – a single data read (byte, half-word or word) from the peripheral data register or a location in the memory, addressed through an internal current peripheral/memory address register. The start address used for the first single transfer is the base address of the peripheral or memory, and is programmed in the DMA_CPARx or DMA_CMARx register. – a single data write (byte, half-word or word) to the peripheral data register or a location in the memory, addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base address of the peripheral or memory, and is programmed in the DMA_CPARx or DMA_CMARx register. post-decrementing of the programmed DMA_CNDTRx register This register contains the remaining number of data items to transfer (number of AHB ‘read followed by write’ transfers). This sequence is repeated until DMA_CNDTRx is null. Note: The AHB master bus source/destination address must be aligned with the programmed size of the transferred single data to the source/destination. 11.4.3 DMA arbitration The DMA arbiter manages the priority between the different channels. RM0394 Rev 4 301/1600 319 Direct memory access controller (DMA) RM0394 When an active channel x is granted by the arbiter (hardware requested or software triggered), a single DMA transfer is issued (such as a AHB ‘read followed by write’ transfer of a single data). Then, the arbiter considers again the set of active channels and selects the one with the highest priority. The priorities are managed in two stages: • • software: priority of each channel is configured in the DMA_CCRx register, to one of the four different levels: – very high – high – medium – low hardware: if two requests have the same software priority level, the channel with the lowest index gets priority. For example, channel 2 gets priority over channel 4. When a channel x is programmed for a block transfer in memory-to-memory mode, re arbitration is considered between each single DMA transfer of this channel x. Whenever there is another concurrent active requested channel, the DMA arbiter automatically alternates and grants the other highest-priority requested channel, which may be of lower priority than the memory-to-memory channel. 11.4.4 DMA channels Each channel may handle a DMA transfer between a peripheral register located at a fixed address, and a memory address. The amount of data items to transfer is programmable. The register that contains the amount of data items to transfer is decremented after each transfer. A DMA channel is programmed at block transfer level. Programmable data sizes The transfer sizes of a single data (byte, half-word, or word) to the peripheral and memory are programmable through, respectively, the PSIZE[1:0] and MSIZE[1:0] fields of the DMA_CCRx register. Pointer incrementation The peripheral and memory pointers may be automatically incremented after each transfer, depending on the PINC and MINC bits of the DMA_CCRx register. If the incremented mode is enabled (PINC or MINC set to 1), the address of the next transfer is the address of the previous one incremented by 1, 2 or 4, depending on the data size defined in PSIZE[1:0] or MSIZE[1:0]. The first transfer address is the one programmed in the DMA_CPARx or DMA_CMARx register. During transfers, these registers keep the initially programmed value. The current transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel x is configured in non-circular mode, no DMA request is served after the last data transfer (once the number of single data to transfer reaches zero). The DMA channel must be disabled in order to reload a new number of data items into the DMA_CNDTRx register. 302/1600 RM0394 Rev 4 RM0394 Note: Direct memory access controller (DMA) If the channel x is disabled, the DMA registers are not reset. The DMA channel registers (DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during the channel configuration phase. In circular mode, after the last data transfer, the DMA_CNDTRx register is automatically reloaded with the initially programmed value. The current internal address registers are reloaded with the base address values from the DMA_CPARx and DMA_CMARx registers. Channel configuration procedure The following sequence is needed to configure a DMA channel x: 1. Set the peripheral register address in the DMA_CPARx register. The data is moved from/to this address to/from the memory after the peripheral event, or after the channel is enabled in memory-to-memory mode. 2. Set the memory address in the DMA_CMARx register. The data is written to/read from the memory after the peripheral event or after the channel is enabled in memory-to-memory mode. 3. Configure the total number of data to transfer in the DMA_CNDTRx register. After each data transfer, this value is decremented. 4. Configure the parameters listed below in the DMA_CCRx register: 5. – the channel priority – the data transfer direction – the circular mode – the peripheral and memory incremented mode – the peripheral and memory data size – the interrupt enable at half and/or full transfer and/or transfer error Activate the channel by setting the EN bit in the DMA_CCRx register. A channel, as soon as enabled, may serve any DMA request from the peripheral connected to this channel, or may start a memory-to-memory block transfer. Note: The two last steps of the channel configuration procedure may be merged into a single access to the DMA_CCRx register, to configure and enable the channel. When a channel is enabled and still active (not completed), the software must perform two separate write accesses to the DMA_CCRx register, to disable the channel, then to reprogram the channel for another next block transfer. Some fields of the DMA_CCRx register are read-only when the EN bit is set to 1. Stop and resume a channel Once the software activates a channel, it waits for the completion of the programmed transfer. The DMA controller is not able to resume an aborted active channel with a possible suspended bus transfer. To correctly stop and disable a channel, the software clears the EN bit of the DMA_CCRx register. The software secures that no pending request from the peripheral is served by the DMA controller before the transfer completion. The software waits for the transfer complete or transfer error interrupt. When a channel transfer error occurs, the EN bit of the DMA_CCRx register is cleared by hardware. This EN bit can not be set again by software to re-activate the channel x, until the TEIFx bit of the DMA_ISR register is set. RM0394 Rev 4 303/1600 319 Direct memory access controller (DMA) RM0394 Circular mode (in memory-to-peripheral/peripheral-to-memory transfers) The circular mode is available to handle circular buffers and continuous data flows (such as ADC scan mode). This feature is enabled using the CIRC bit in the DMA_CCRx register. Note: The circular mode must not be used in memory-to-memory mode. Before enabling a channel in circular mode (CIRC = 1), the software must clear the MEM2MEM bit of the DMA_CCRx register. When the circular mode is activated, the amount of data to transfer is automatically reloaded with the initial value programmed during the channel configuration phase, and the DMA requests continue to be served. In order to stop a circular transfer, the software needs to stop the peripheral from generating DMA requests (such as quit the ADC scan mode), before disabling the DMA channel. The software must explicitly program the DMA_CNDTRx value before starting/enabling a transfer, and after having stopped a circular transfer. Memory-to-memory mode The DMA channels may operate without being triggered by a request from a peripheral. This mode is called memory-to-memory mode, and is initiated by software. If the MEM2MEM bit in the DMA_CCRx register is set, the channel, if enabled, initiates transfers. The transfer stops once the DMA_CNDTRx register reaches zero. Note: The memory-to-memory mode must not be used in circular mode. Before enabling a channel in memory-to-memory mode (MEM2MEM = 1), the software must clear the CIRC bit of the DMA_CCRx register. Peripheral-to-peripheral mode Any DMA channel can operate in peripheral-to-peripheral mode: • when the hardware request from a peripheral is selected to trigger the DMA channel This peripheral is the DMA initiator and paces the data transfer from/to this peripheral to/from a register belonging to another memory-mapped peripheral (this one being not configured in DMA mode). • when no peripheral request is selected and connected to the DMA channel The software configures a register-to-register transfer by setting the MEM2MEM bit of the DMA_CCRx register. Programming transfer direction, assigning source/destination The value of the DIR bit of the DMA_CCRx register sets the direction of the transfer, and consequently, it identifies the source and the destination, regardless the source/destination type (peripheral or memory): • 304/1600 DIR = 1 defines typically a memory-to-peripheral transfer. More generally, if DIR = 1: – The source attributes are defined by the DMA_MARx register, the MSIZE[1:0] field and MINC bit of the DMA_CCRx register. Regardless of their usual naming, these ‘memory’ register, field and bit are used to define the source peripheral in peripheral-to-peripheral mode. – The destination attributes are defined by the DMA_PARx register, the PSIZE[1:0] field and PINC bit of the DMA_CCRx register. RM0394 Rev 4 RM0394 Direct memory access controller (DMA) Regardless of their usual naming, these ‘peripheral’ register, field and bit are used to define the destination memory in memory-to-memory mode. • DIR = 0 defines typically a peripheral-to-memory transfer. More generally, if DIR = 0: – The source attributes are defined by the DMA_PARx register, the PSIZE[1:0] field and PINC bit of the DMA_CCRx register. Regardless of their usual naming, these ‘peripheral’ register, field and bit are used to define the source memory in memory-to-memory mode – The destination attributes are defined by the DMA_MARx register, the MSIZE[1:0] field and MINC bit of the DMA_CCRx register. Regardless of their usual naming, these ‘memory’ register, field and bit are used to define the destination peripheral in peripheral-to-peripheral mode. RM0394 Rev 4 305/1600 319 Direct memory access controller (DMA) 11.4.5 RM0394 DMA data width, alignment and endianness When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data alignments as described in Table 43. Table 43. Programmable data width and endian behavior (when PINC = MINC = 1) Source port width (MSIZE if DIR = 1, else PSIZE) Destinat ion port Number width of data (PSIZE items to if transfer DIR = 1, (NDT) else MSIZE) Source content: address / data (DMA_CMARx if DIR = 1, else DMA_CPARx) DMA transfers Destination content: address / data (DMA_CPARx if DIR = 1, else DMA_CMARx) 8 8 8 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: read B0[7:0] @0x0 then write B0[7:0] @0x0 2: read B1[7:0] @0x1 then write B1[7:0] @0x1 3: read B2[7:0] @0x2 then write B2[7:0] @0x2 4: read B3[7:0] @0x3 then write B3[7:0] @0x3 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 8 16 4 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: read B0[7:0] @0x0 then write 00B0[15:0] @0x0 2: read B1[7:0] @0x1 then write 00B1[15:0] @0x2 3: read B2[7:0] @0x2 then write 00B2[15:0] @0x4 4: read B3[7:0] @0x3 then write 00B3[15:0] @0x6 @0x0 / 00B0 @0x2 / 00B1 @0x4 / 00B2 @0x6 / 00B3 8 32 4 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: read B0[7:0] @0x0 then write 000000B0[31:0] @0x0 2: read B1[7:0] @0x1 then write 000000B1[31:0] @0x4 3: read B2[7:0] @0x2 then write 000000B2[31:0] @0x8 4: read B3[7:0] @0x3 then write 000000B3[31:0] @0xC @0x0 / 000000B0 @0x4 / 000000B1 @0x8 / 000000B2 @0xC / 000000B3 16 8 4 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: read B1B0[15:0] @0x0 then write B0[7:0] @0x0 2: read B3B2[15:0] @0x2 then write B2[7:0] @0x1 3: read B5B4[15:0] @0x4 then write B4[7:0] @0x2 4: read B7B6[15:0] @0x6 then write B6[7:0] @0x3 @0x0 / B0 @0x1 / B2 @0x2 / B4 @0x3 / B6 16 16 4 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: read B1B0[15:0] @0x0 then write B1B0[15:0] @0x0 2: read B3B2[15:0] @0x2 then write B3B2[15:0] @0x2 3: read B5B4[15:0] @0x4 then write B5B4[15:0] @0x4 4: read B7B6[15:0] @0x6 then write B7B6[15:0] @0x6 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 16 32 4 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: read B1B0[15:0] @0x0 then write 0000B1B0[31:0] @0x0 2: read B3B2[15:0] @0x2 then write 0000B3B2[31:0] @0x4 3: read B5B4[15:0] @0x4 then write 0000B5B4[31:0] @0x8 4: read B7B6[15:0] @0x6 then write 0000B7B6[31:0] @0xC @0x0 / 0000B1B0 @0x4 / 0000B3B2 @0x8 / 0000B5B4 @0xC / 0000B7B6 32 8 4 @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC 1: read B3B2B1B0[31:0] @0x0 then write B0[7:0] @0x0 2: read B7B6B5B4[31:0] @0x4 then write B4[7:0] @0x1 3: read BBBAB9B8[31:0] @0x8 then write B8[7:0] @0x2 4: read BFBEBDBC[31:0] @0xC then write BC[7:0] @0x3 @0x0 / B0 @0x1 / B4 @0x2 / B8 @0x3 / BC 32 16 4 @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC 1: read B3B2B1B0[31:0] @0x0 then write B1B0[15:0] @0x0 2: read B7B6B5B4[31:0] @0x4 then write B5B4[15:0] @0x2 3: read BBBAB9B8[31:0] @0x8 then write B9B8[15:0] @0x4 4: read BFBEBDBC[31:0] @0xC then write BDBC[15:0] @0x6 @0x0 / B1B0 @0x2 / B5B4 @0x4 / B9B8 @0x6 / BDBC 32 32 4 @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC 1: read B3B2B1B0[31:0] @0x0 then write B3B2B1B0[31:0] @0x0 2: read B7B6B5B4[31:0] @0x4 then write B7B6B5B4[31:0] @0x4 3: read BBBAB9B8[31:0] @0x8 then write BBBAB9B8[31:0] @0x8 4: read BFBEBDBC[31:0] @0xC then write BFBEBDBC[31:0] @0xC @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC 306/1600 RM0394 Rev 4 RM0394 Direct memory access controller (DMA) Addressing AHB peripherals not supporting byte/half-word write transfers When the DMA controller initiates an AHB byte or half-word write transfer, the data are duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]). When the AHB slave peripheral does not support byte or half-word write transfers and does not generate any error, the DMA controller writes the 32 HWDATA bits as shown in the two examples below: • To write the half-word 0xABCD, the DMA controller sets the HWDATA bus to 0xABCDABCD with a half-word data size (HSIZE = HalfWord in AHB master bus). • To write the byte 0xAB, the DMA controller sets the HWDATA bus to 0xABABABAB with a byte data size (HSIZE = Byte in the AHB master bus). Assuming the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take into account the HSIZE data, any AHB byte or half-word transfer is changed into a 32-bit APB transfer as described below: 11.4.6 • An AHB byte write transfer of 0xB0 to one of the 0x0, 0x1, 0x2 or 0x3 addresses, is converted to an APB word write transfer of 0xB0B0B0B0 to the 0x0 address. • An AHB half-word write transfer of 0xB1B0 to the 0x0 or 0x2 addresses, is converted to an APB word write transfer of 0xB1B0B1B0 to the 0x0 address. DMA error management A DMA transfer error is generated when reading from or writing to a reserved address space. When a DMA transfer error occurs during a DMA read or write access, the faulty channel x is automatically disabled through a hardware clear of its EN bit in the corresponding DMA_CCRx register. The TEIFx bit of the DMA_ISR register is set. An interrupt is then generated if the TEIE bit of the DMA_CCRx register is set. The EN bit of the DMA_CCRx register can not be set again by software (channel x reactivated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). When the software is notified with a transfer error over a channel which involves a peripheral, the software has first to stop this peripheral in DMA mode, in order to disable any pending or future DMA request. Then software may normally reconfigure both DMA and the peripheral in DMA mode for a new transfer. RM0394 Rev 4 307/1600 319 Direct memory access controller (DMA) 11.5 RM0394 DMA interrupts An interrupt can be generated on a half transfer, transfer complete or transfer error for each DMA channel x. Separate interrupt enable bits are available for flexibility. Table 44. DMA interrupt requests Event flag Interrupt enable bit Half transfer on channel x HTIFx HTIEx Transfer complete on channel x TCIFx TCIEx Transfer error on channel x TEIFx TEIEx Half transfer or transfer complete or transfer error on channel x GIFx - Interrupt request Channel x interrupt 11.6 Interrupt event DMA registers Refer to Section 1.2 for a list of abbreviations used in register descriptions. The DMA registers have to be accessed by words (32-bit). 11.6.1 DMA interrupt status register (DMA_ISR) Address offset: 0x00 Reset value: 0x0000 0000 Every status bit is cleared by hardware when the software sets the corresponding clear bit or the corresponding global clear bit CGIFx, in the DMA_IFCR register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5 r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1 r r r r r r r r r r r r r r r r Bits 31:28 Reserved, must be kept at reset value. Bit 27 TEIF7: transfer error (TE) flag for channel 7 0: no TE event 1: a TE event occurred Bit 26 HTIF7: half transfer (HT) flag for channel 7 0: no HT event 1: a HT event occurred Bit 25 TCIF7: transfer complete (TC) flag for channel 7 0: no TC event 1: a TC event occurred Bit 24 GIF7: global interrupt flag for channel 7 0: no TE, HT or TC event 1: a TE, HT or TC event occurred 308/1600 RM0394 Rev 4 RM0394 Direct memory access controller (DMA) Bit 23 TEIF6: transfer error (TE) flag for channel 6 0: no TE event 1: a TE event occurred Bit 22 HTIF6: half transfer (HT) flag for channel 6 0: no HT event 1: a HT event occurred Bit 21 TCIF6: transfer complete (TC) flag for channel 6 0: no TC event 1: a TC event occurred Bit 20 GIF6: global interrupt flag for channel 6 0: no TE, HT or TC event 1: a TE, HT or TC event occurred Bit 19 TEIF5: transfer error (TE) flag for channel 5 0: no TE event 1: a TE event occurred Bit 18 HTIF5: half transfer (HT) flag for channel 5 0: no HT event 1: a HT event occurred Bit 17 TCIF5: transfer complete (TC) flag for channel 5 0: no TC event 1: a TC event occurred Bit 16 GIF5: global interrupt flag for channel 5 0: no TE, HT or TC event 1: a TE, HT or TC event occurred Bit 15 TEIF4: transfer error (TE) flag for channel 4 0: no TE event 1: a TE event occurred Bit 14 HTIF4: half transfer (HT) flag for channel 4 0: no HT event 1: a HT event occurred Bit 13 TCIF4: transfer complete (TC) flag for channel 4 0: no TC event 1: a TC event occurred Bit 12 GIF4: global interrupt flag for channel 4 0: no TE, HT or TC event 1: a TE, HT or TC event occurred Bit 11 TEIF3: transfer error (TE) flag for channel 3 0: no TE event 1: a TE event occurred Bit 10 HTIF3: half transfer (HT) flag for channel 3 0: no HT event 1: a HT event occurred Bit 9 TCIF3: transfer complete (TC) flag for channel 3 0: no TC event 1: a TC event occurred RM0394 Rev 4 309/1600 319 Direct memory access controller (DMA) RM0394 Bit 8 GIF3: global interrupt flag for channel 3 0: no TE, HT or TC event 1: a TE, HT or TC event occurred Bit 7 TEIF2: transfer error (TE) flag for channel 2 0: no TE event 1: a TE event occurred Bit 6 HTIF2: half transfer (HT) flag for channel 2 0: no HT event 1: a HT event occurred Bit 5 TCIF2: transfer complete (TC) flag for channel 2 0: no TC event 1: a TC event occurred Bit 4 GIF2: global interrupt flag for channel 2 0: no TE, HT or TC event 1: a TE, HT or TC event occurred Bit 3 TEIF1: transfer error (TE) flag for channel 1 0: no TE event 1: a TE event occurred Bit 2 HTIF1: half transfer (HT) flag for channel 1 0: no HT event 1: a HT event occurred Bit 1 TCIF1: transfer complete (TC) flag for channel 1 0: no TC event 1: a TC event occurred Bit 0 GIF1: global interrupt flag for channel 1 0: no TE, HT or TC event 1: a TE, HT or TC event occurred 310/1600 RM0394 Rev 4 RM0394 Direct memory access controller (DMA) 11.6.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register, causes the DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx, HTIFx, TCIFx, in the DMA_ISR register. Setting any individual clear bit among CTEIFx, CHTIFx, CTCIFx in this DMA_IFCR register, causes the DMA hardware to clear the corresponding individual flag and the global flag GIFx in the DMA_ISR register, provided that none of the two other individual flags is set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. CTEIF7 CHTIF7 CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5 w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1 Writing 0 into any flag clear bit has no effect. w w w w w w w w w w w w w w w w Bits 31:28 Reserved, must be kept at reset value. Bit 27 CTEIF7: transfer error flag clear for channel 7 Bit 26 CHTIF7: half transfer flag clear for channel 7 Bit 25 CTCIF7: transfer complete flag clear for channel 7 Bit 24 CGIF7: global interrupt flag clear for channel 7 Bit 23 CTEIF6: transfer error flag clear for channel 6 Bit 22 CHTIF6: half transfer flag clear for channel 6 Bit 21 CTCIF6: transfer complete flag clear for channel 6 Bit 20 CGIF6: global interrupt flag clear for channel 6 Bit 19 CTEIF5: transfer error flag clear for channel 5 Bit 18 CHTIF5: half transfer flag clear for channel 5 Bit 17 CTCIF5: transfer complete flag clear for channel 5 Bit 16 CGIF5: global interrupt flag clear for channel 5 Bit 15 CTEIF4: transfer error flag clear for channel 4 Bit 14 CHTIF4: half transfer flag clear for channel 4 Bit 13 CTCIF4: transfer complete flag clear for channel 4 Bit 12 CGIF4: global interrupt flag clear for channel 4 Bit 11 CTEIF3: transfer error flag clear for channel 3 Bit 10 CHTIF3: half transfer flag clear for channel 3 Bit 9 CTCIF3: transfer complete flag clear for channel 3 RM0394 Rev 4 311/1600 319 Direct memory access controller (DMA) RM0394 Bit 8 CGIF3: global interrupt flag clear for channel 3 Bit 7 CTEIF2: transfer error flag clear for channel 2 Bit 6 CHTIF2: half transfer flag clear for channel 2 Bit 5 CTCIF2: transfer complete flag clear for channel 2 Bit 4 CGIF2: global interrupt flag clear for channel 2 Bit 3 CTEIF1: transfer error flag clear for channel 1 Bit 2 CHTIF1: half transfer flag clear for channel 1 Bit 1 CTCIF1: transfer complete flag clear for channel 1 Bit 0 CGIF1: global interrupt flag clear for channel 1 11.6.3 DMA channel x configuration register (DMA_CCRx) Address offset: 0x08 + 0x14 * (x - 1), (x = 1 to 7) Reset value: 0x0000 0000 The register fields/bits MEM2MEM, PL[1:0], MSIZE[1:0], PSIZE[1:0], MINC, PINC, and DIR are read-only when EN = 1. The states of MEM2MEM and CIRC bits must not be both high at the same time. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. MEM2 MEM MINC PINC CIRC DIR TEIE HTIE TCIE EN rw rw rw rw rw rw rw rw rw PL[1:0] rw rw MSIZE[1:0] PSIZE[1:0] rw rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 MEM2MEM: memory-to-memory mode 0: disabled 1: enabled Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). Bits 13:12 PL[1:0]: priority level 00: low 01: medium 10: high 11: very high Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 312/1600 RM0394 Rev 4 RM0394 Direct memory access controller (DMA) Bits 11:10 MSIZE[1:0]: memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). Bits 9:8 PSIZE[1:0]: peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). Bit 7 MINC: memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). Bit 6 PINC: peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). RM0394 Rev 4 313/1600 319 Direct memory access controller (DMA) RM0394 Bit 5 CIRC: circular mode 0: disabled 1: enabled Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). Bit 4 DIR: data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral – Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. – Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory – Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. – Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). Bit 3 TEIE: transfer error interrupt enable 0: disabled 1: enabled Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). Bit 2 HTIE: half transfer interrupt enable 0: disabled 1: enabled Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). Bit 1 TCIE: transfer complete interrupt enable 0: disabled 1: enabled Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). Bit 0 EN: channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). 0: disabled 1: enabled Note: this bit is set and cleared by software. 314/1600 RM0394 Rev 4 RM0394 Direct memory access controller (DMA) 11.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx) Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 7) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw NDT[15:0] rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 NDT[15:0]: number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’ transfer, indicating the remaining amount of data items to transfer. – It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). – It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 11.6.5 DMA channel x peripheral address register (DMA_CPARx) Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 7) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PA[31:16] rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 PA[15:0] rw rw rw rw rw rw rw rw rw RM0394 Rev 4 315/1600 319 Direct memory access controller (DMA) RM0394 Bits 31:0 PA[31:0]: peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 11.6.6 DMA channel x memory address register (DMA_CMARx) Address offset: 0x14 + 0x14 * (x - 1), (x = 1 to 7) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MA[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw MA[15:0] rw Bits 31:0 MA[31:0]: peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 316/1600 RM0394 Rev 4 RM0394 Direct memory access controller (DMA) 11.6.7 DMA channel selection register (DMA_CSELR) Address offset: 0xA8 Reset value: 0x0000 0000 This register is used to manage the mapping of DMA channels as detailed in Section 11.3.2: DMA request mapping. 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 27 26 rw rw 24 23 22 20 19 18 17 16 C5S[3:0] rw rw rw rw rw rw rw rw rw rw rw 11 10 9 8 7 6 5 4 3 2 1 0 C3S[3:0] rw 21 C6S[3:0] rw C4S[3:0] rw 25 C7S[3:0] rw rw C2S[3:0] rw rw rw rw C1S[3:0] rw rw rw rw rw rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 C7S[3:0]: DMA channel 7 selection Details available in Section 11.3.2: DMA request mapping Bits 23:20 C6S[3:0]: DMA channel 6 selection Details available in Section 11.3.2: DMA request mapping Bits 19:16 C5S[3:0]: DMA channel 5 selection Details available in Section 11.3.2: DMA request mapping Bits 15:12 C4S[3:0]: DMA channel 4 selection Details available in Section 11.3.2: DMA request mapping Bits 11:8 C3S[3:0]: DMA channel 3 selection Details available in Section 11.3.2: DMA request mapping Bits 7:4 C2S[3:0]: DMA channel 2 selection Details available in Section 11.3.2: DMA request mapping Bits 3:0 C1S[3:0]: DMA channel 1 selection Details available in Section 11.3.2: DMA request mapping 11.6.8 DMA register map and reset values Table 45 gives the DMA register map and reset values. TCIF1 GIF1 CGIF1 0 0 0 0 0 0 0 EN HTIF1 CTCIF1 0 CHTIF1 0 0 TCIE 0 0 HTIE GIF2 TEIF1 0 CTEIF1 0 TEIE TCIF2 RM0394 Rev 4 0 0 0 CGIF2 0 0 DIR HTIF2 Reset value 0 CTCIF2 0 CHTIF2 0 PINC 0 CIRC GIF3 TEIF2 0 CTEIF2 0 MINC TCIF3 0 0 0 0 0 0 0 0 0 PSIZE[1:0] 0 CGIF3 HTIF3 0 CTCIF3 0 MSIZE[1:0] 0 CHTIF3 GIF4 TEIF3 0 CTEIF3 TCIF4 0 PL[1:0] 0 CGIF4 HTIF4 0 CTCIF4 0 CHTIF4 0 MEM2MEM GIF5 TEIF4 0 CTEIF4 0 Res. TCIF5 0 CGIF5 0 Res. HTIF5 0 CTCIF5 0 CHTIF5 0 Res. 0 Res. GIF6 TEIF5 0 CTEIF5 0 Res. TCIF6 0 CGIF6 0 Res. HTIF6 0 CTCIF6 0 CHTIF6 0 Res. 0 Res. GIF7 TEIF6 0 CTEIF6 0 Res. TCIF7 0 CGIF7 0 Res. HTIF7 0 CTCIF7 0 CHTIF7 0 Res. 0 Res. Res. 0 CTEIF7 Res. Res. DMA_CCR1 Res. 0x008 Res. Reset value 0 Res. Res. Res. DMA_IFCR Res. 0x004 Res. Reset value TEIF7 DMA_ISR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 Register Res. Offset Res. Table 45. DMA register map and reset values 0 317/1600 319 Direct memory access controller (DMA) RM0394 Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 318/1600 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PINC DIR TEIE HTIE TCIE EN 0 CIRC PSIZE[1:0] MSIZE[1:0] PL[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSIZE[1:0] PL[1:0] PSIZE[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIRC DIR TEIE HTIE TCIE EN PSIZE[1:0] MSIZE[1:0] PL[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 PINC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIRC DIR TEIE HTIE TCIE EN MSIZE[1:0] PSIZE[1:0] 0 PINC 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 PL[1:0] MEM2MEM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reserved. 0 0 0 0 0 0 0 NDTR[15:0] 0 DMA_CPAR5 Reset value 0 MEM2MEM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Reset value 0x060 0 MA[31:0] Res. 0x05C 0 MINC 0 Reset value DMA_CNDTR5 0 PA[31:0] Reserved DMA_CCR5 0 NDTR[15:0] 0 Res. 0x058 0 Reserved. DMA_CMAR4 Reset value 0 EN 0 Res. 0x054 0 TCIE 0 Res. 0x050 0 HTIE 0 DMA_CPAR4 Reset value 0 DIR 0 Reset value 0x04C 0 MA[31:0] Res. DMA_CNDTR4 0 TEIE 0 Reset value 0x048 0 CIRC 0 Reserved DMA_CCR4 0 PINC 0 Res. Reset value 0 MINC 0 Res. 0x044 0 DMA_CMAR3 Res. 0x040 0 PA[31:0] Res. 0x03C 0 NDTR[15:0] 0 DMA_CPAR3 Reset value 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0x038 0 MEM2MEM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CNDTR3 Res. Reset value 0x034 0 Reserved. Res. Reserved DMA_CCR3 0 MA[31:0] Res. Reset value 0 MINC 0 Res. 0x030 0 DMA_CMAR2 Res. 0x02C 0 PA[31:0] Res. 0x028 0 NDTR[15:0] 0 DMA_CPAR2 Reset value 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0x024 0 MEM2MEM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x020 0 0 Res. Reset value DMA_CNDTR2 0 Reserved. Res. Reserved DMA_CCR2 0 Res. Reset value 0 MA[31:0] Res. 0x01C 0 DMA_CMAR1 Res. 0x018 Reset value 0 PA[31:0] Res. 0x014 0 DMA_CPAR1 Res. 0x010 NDTR[15:0] MINC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CNDTR1 Res. 0x00C Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 45. DMA register map and reset values (continued) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0394 Rev 4 0 0 0 RM0394 Direct memory access controller (DMA) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value PSIZE[1:0] MSIZE[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIRC DIR TEIE HTIE TCIE EN 0 PINC PSIZE[1:0] MSIZE[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PL[1:0] MEM2MEM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 NDTR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved. Res. Reserved DMA_CSELR 0 0 0 PA[31:0] Res. 0x0A8 0 0 0 DMA_CMAR7 Reset value 0 Reserved. Res. 0x090 to 0x0A4 0 EN 0 Res. 0x08C 0 TCIE 0 DMA_CPAR7 Reset value 0 HTIE 0 Reset value 0x088 0 MA[31:0] Res. 0x084 0 DIR 0 Reset value DMA_CNDTR7 0 TEIE 0 Reserved DMA_CCR7 0 PINC 0 Res. Reset value 0 CIRC 0 Res. 0x080 0 DMA_CMAR6 Res. 0x07C 0 PA[31:0] Res. 0x078 0 NDTR[15:0] 0 DMA_CPAR6 Reset value 0 MINC Reset value 0x074 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CNDTR6 Res. Reset value 0x070 0 PL[1:0] Res. MEM2MEM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CCR6 0 Reserved. Res. Reserved MINC MA[31:0] 0 Res. 0x06C Reset value Res. 0x068 DMA_CMAR5 Res. 0x064 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 45. DMA register map and reset values (continued) C7S[3:0] 0 0 0 C6S[3:0] 0 0 0 0 C5S[3:0] 0 0 0 0 C4S[3:0] 0 0 0 0 C3S[3:0] 0 0 C2S[3:0] 0 0 C1S[3:0] 0 0 0 Refer to Section 2.2.2 for register boundary addresses. RM0394 Rev 4 319/1600 319 Nested vectored interrupt controller (NVIC) 12 Nested vectored interrupt controller (NVIC) 12.1 NVIC main features RM0394 • 67 maskable interrupt channels (not including the sixteen Cortex®-M4 with FPU interrupt lines) • 16 programmable priority levels (4 bits of interrupt priority are used) • Low-latency exception and interrupt handling • Power management control • Implementation of System Control Registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to the PM0214 programming manual for CortexTM-M4 products. 12.2 SysTick calibration value register The SysTick calibration value is set to 0x4000270F, which gives a reference time base of 1 ms with the SysTick clock set to 10 MHz (max fHCLK/8). 320/1600 RM0394 Rev 4 RM0394 Nested vectored interrupt controller (NVIC) 12.3 Interrupt and exception vectors The grey rows in Table 46 describe the vectors without specific position. Refer to device datasheet for availability of each peripheral. Position Priority Table 46. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table Type of priority - - - - -3 fixed - -2 - Acronym - Description Address Reserved 0x0000 0000 Reset Reset 0x0000 0004 fixed NMI Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector. 0x0000 0008 -1 fixed HardFault All classes of fault 0x0000 000C - 0 settable MemManage Memory management 0x0000 0010 - 1 settable BusFault Pre-fetch fault, memory access fault 0x0000 0014 - 2 settable UsageFault Undefined instruction or illegal state 0x0000 0018 - - - - 3 settable SVCall System service call via SWI instruction 0x0000 002C - 4 settable Debug Monitor 0x0000 0030 - - - Reserved 0x0000 0034 - 5 settable PendSV Pendable request for system service 0x0000 0038 - 6 settable SysTick System tick timer 0x0000 003C 0 7 settable WWDG Window Watchdog interrupt 0x0000 0040 1 8 settable PVD_PVM PVD/PVM1/PVM2(1)/PVM3/PVM4 through EXTI lines 16/35/36/37/38 interrupts 0x0000 0044 2 9 settable RTC_TAMP_STAMP RTC Tamper or TimeStamp /CSS on LSE /CSS_LSE through EXTI line 19 interrupts 3 10 settable RTC_WKUP RTC Wakeup timer through EXTI line 20 interrupt 0x0000 004C 4 11 settable FLASH Flash global interrupt 0x0000 0050 5 12 settable RCC RCC global interrupt 0x0000 005C 6 13 settable EXTI0 EXTI Line0 interrupt 0x0000 005C 7 14 settable EXTI1 EXTI Line1 interrupt 0x0000 005C 8 15 settable EXTI2 EXTI Line2 interrupt 0x0000 0060 9 16 settable EXTI3 EXTI Line3 interrupt 0x0000 0064 10 17 settable EXTI4 EXTI Line4 interrupt 0x0000 0068 - - Reserved RM0394 Rev 4 0x0000 001C 0x0000 0028 0x0000 0048 321/1600 337 Nested vectored interrupt controller (NVIC) RM0394 Position Priority Table 46. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table (continued) Type of priority 11 18 settable DMA1_CH1 DMA1 channel 1 interrupt 0x0000 006C 12 19 settable DMA1_CH2 DMA1 channel 2 interrupt 0x0000 0070 13 20 settable DMA1_CH3 DMA1 channel 3 interrupt 0x0000 0074 14 21 settable DMA1_CH4 DMA1 channel 4 interrupt 0x0000 0078 15 22 settable DMA1_CH5 DMA1 channel 5 interrupt 0x0000 007C 16 23 settable DMA1_CH6 DMA1 channel 6 interrupt 0x0000 0080 17 24 settable DMA1_CH7 DMA1 channel 7 interrupt 0x0000 0084 18 25 settable Acronym ADC1_2 ADC1 and ADC2 global interrupt 0x0000 0088 0x0000 008C CAN1_RX0(1) CAN1_RX0 interrupts 0x0000 0090 settable CAN1_RX1(1) CAN1_RX1 interrupt 0x0000 0094 (1) CAN1_SCE interrupt 0x0000 0098 26 settable CAN1_TX 20 27 settable 28 (1) (2) Address CAN1_TX interrupts 19 21 Description 22 29 settable CAN1_SCE 23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000 009C 24 31 settable TIM1_BRK/TIM15 TIM1 Break/TIM15 global interrupts 0x0000 00A0 25 32 settable TIM1_UP/TIM16 TIM1 Update/TIM16 global interrupts 0x0000 00A4 26 33 settable TIM1_TRG_COM TIM1 trigger and commutation interrupt 0x0000 00A8 27 34 settable TIM1_CC TIM1 capture compare interrupt 0x0000 00AC 28 35 settable TIM2 TIM2 global interrupt 0x0000 00B0 TIM3 global interrupt 0x0000 00B4 Reserved 0x0000 00B8 29 36 settable 30 37 settable 31 38 settable I2C1_EV I2C1 event interrupt 0x0000 00BC 32 39 settable I2C1_ER I2C1 error interrupt 0x0000 00C0 settable I2C2_EV(4) I2C2 event interrupt 0x0000 00C4 (4) I2C2 error interrupt 0x0000 00C8 33 40 TIM3 (3) - 34 41 settable I2C2_ER 35 42 settable SPI1 SPI1 global interrupt 0x0000 00CC 36 43 settable SPI2(4) SPI2 global interrupt 0x0000 00D0 37 44 settable USART1 USART1 global interrupt 0x0000 00D4 38 45 settable USART2 USART2 global interrupt 0x0000 00D8 (4) 39 46 settable USART3 USART3 global interrupt 0x0000 00DC 40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000 00E0 41 48 settable RTC_ALARM RTC alarms through EXTI line 18 interrupts 0x0000 00E4 42 49 settable - Reserved 0x0000 00E8 43 50 settable - Reserved 0x0000 00EC 322/1600 RM0394 Rev 4 RM0394 Nested vectored interrupt controller (NVIC) Position Priority Table 46. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table (continued) Type of priority 44 51 settable - Reserved 0x0000 00F0 45 52 settable - Reserved 0x0000 00F4 46 53 settable - Reserved 0x0000 00F8 47 54 settable - Reserved 0x0000 00FC 48 55 settable - Reserved 0x0000 0100 49 56 settable SDMMC1 global interrupt 0x0000 0104 50 57 settable Reserved 0x0000 0108 51 58 settable SPI3 global interrupt 0x0000 010C UART4 global interrupt 0x0000 0110 Reserved 0x0000 0114 52 59 settable 53 60 settable 54 61 settable Acronym Description SDMMC1(4)(1) SPI3 UART4 (3) TIM6_DACUNDER (5) DAC1(1) TIM6 global and underrun interrupts Address 0x0000 0118 TIM7 global interrupt 0x0000 011C DMA2_CH1 DMA2 channel 1 interrupt 0x0000 0120 settable DMA2_CH2 DMA2 channel 2 interrupt 0x0000 0124 65 settable DMA2_CH3 DMA2 channel 3 interrupt 0x0000 0128 59 66 settable DMA2_CH4 DMA2 channel 4 interrupt 0x0000 012C 60 67 settable DMA2_CH5 DMA2 channel 5 interrupt 0x0000 0130 61 68 settable DFSDM1_FLT0(3) DFSDM1_FLT0 global interrupt 0x0000 0134 (3) DFSDM1_FLT1 global interrupt 0x0000 0138 Reserved 0x0000 013C 55 62 settable TIM7 56 63 settable 57 64 58 62 69 settable 63 70 settable DFSDM1_FLT1 - (1) through EXTI lines 21/22 64 71 settable COMP COMP1/COMP2 interrupts 65 72 settable LPTIM1 LPTIM1 global interrupt 0x0000 0144 66 73 settable LPTIM2 LPTIM2 global interrupt 0x0000 0148 USB event interrupt through EXTI line 17 0x0000 014C (6) 0x0000 0140 67 74 settable USB_FS 68 75 settable DMA2_CH6 DMA2 channel 6 interrupt 0x0000 0150 69 76 settable DMA2_CH7 DMA2 channel 7 interrupt 0x0000 0154 70 77 settable LPUART1 LPUART1 global interrupt 0x0000 0158 71 78 settable QUADSPI QUADSPI global interrupt 0x0000 015C 72 79 settable I2C3_EV I2C3 event interrupt 0x0000 0160 73 80 settable I2C3_ER I2C3 error interrupt 0x0000 0164 74 81 settable SAI1(1) SAI1 global interrupt 0x0000 0168 75 74 settable Reserved 0x0000 016C - RM0394 Rev 4 323/1600 337 Nested vectored interrupt controller (NVIC) RM0394 Position Priority Table 46. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table (continued) Type of priority 76 75 settable SWPMI1(5) SWPMI1 global interrupt 0x0000 0170 77 76 settable TSC TSC global interrupt 0x0000 0174 settable LCD(7) LCD global interrupt 0x0000 0178 (8) AES global interrupt 0x0000 017C 78 77 Acronym Description Address 79 78 settable AES 80 79 settable RNG RNG global interrupt 0x0000 0180 81 88 settable FPU Floating point interrupt 0x0000 0184 82 89 settable CRS CRS interrupt 0x0000 0188 83 90 settable I2C4_EV(3) I2C4 event interrupt, wakeup through EXTI line 40 0x0000 018C 84 91 settable I2C4_ER(3) I2C4 error interrupt 0x0000 0190 1. Not available on STM32L41xxx and STM32L42xxx devices. 2. Available on STM32L41xxx and ST32L42xxx devices only. 3. Available on STM32L45xxx and STM32L46xxx devices only. 4. Not available on STM32L432xx and STM32L442xx devices. 5. Available on STM32L43xxx and STM32L44xxx devices only. 6. Available on STM32L4x2xx and STM32L4x3xx devices only. 7. Available on STM32L4x3xx devices only. 8. Available on STM32L42xx, STM32L44xxx and STM32L46xxx devices only. 324/1600 RM0394 Rev 4 RM0394 Extended interrupts and events controller (EXTI) 13 Extended interrupts and events controller (EXTI) 13.1 Introduction The EXTI main features are as follows: • 13.2 Generation of up to 37 event/interrupt requests – 25 configurable lines – 12 direct lines • Independent mask on each event/interrupt line • Configurable rising or falling edge (configurable lines only) • Dedicated status bit (configurable lines only) • Emulation of event/interrupt requests (configurable lines only) EXTI main features The extended interrupts and events controller (EXTI) manages the external and internal asynchronous events/interrupts and generates the event request to the CPU/Interrupt Controller and a wake-up request to the Power Controller. The EXTI allows the management of up to 38 event lines which can wake up from the Stop 0 and Stop 1 modes. Not all events can wake up from the Stop 2 mode (refer to Table 47: EXTI lines connections). The lines are either configurable or direct: • The lines are configurable: the active edge can be chosen independently, and a status flag indicates the source of the interrupt. The configurable lines are used by the I/Os external interrupts, and by few peripherals. • The lines are direct: they are used by some peripherals to generate a wakeup from Stop event or interrupt. The status flag is provided by the peripheral. Each line can be masked independently for an interrupt or an event generation. This controller also allows to emulate events or interrupts by software, multiplexed with the corresponding hardware event line, by writing to a dedicated register. 13.3 EXTI functional description For the configurable interrupt lines, the interrupt line should be configured and enabled in order to generate an interrupt. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register. When the selected edge occurs on the interrupt line, an interrupt request is generated. The pending bit corresponding to the interrupt line is also set. This request is cleared by writing a ‘1’ in the pending register. For the direct interrupt lines, the interrupt is enabled by default in the interrupt mask register and there is no corresponding pending bit in the pending register. To generate an event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’ to the corresponding bit in the event mask register. When the RM0394 Rev 4 325/1600 337 Extended interrupts and events controller (EXTI) RM0394 selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set. For the configurable lines, an interrupt/event request can also be generated by software by writing a ‘1’ in the software interrupt/event register. Note: The interrupts or events associated to the direct lines are triggered only when the system is in Stop mode. If the system is still running, no interrupt/event is generated by the EXTI. 13.3.1 EXTI block diagram The extended interrupt/event block diagram is shown on Figure 28. Figure 28. Configurable interrupt/event block diagram $3%EXV 3&/. 3HULSKHUDOLQWHUIDFH )DOOLQJ WULJJHU VHOHFWLRQ UHJLVWHU 5LVLQJ WULJJHU VHOHFWLRQ UHJLVWHU 6RIWZDUH LQWHUUXSW HYHQW UHJLVWHU (YHQW PDVN UHJLVWHU ,QWHUUXSW PDVN UHJLVWHU 3HQGLQJ UHTXHVW UHJLVWHU ,QWHUUXSWV &RQILJXUDEOH HYHQWV (GJHGHWHFW FLUFXLW (YHQWV 6WRSPRGH 'LUHFWHYHQWV 3JTJOH FEHF EFUFDU :DNHXS 069 13.3.2 Wakeup event management The STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx is able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated either by: 326/1600 • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the CortexTM-M4 System Control register. When the MCU resumes from WFE, the EXTI peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared • or by configuring an EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set. RM0394 Rev 4 RM0394 13.3.3 Extended interrupts and events controller (EXTI) Peripherals asynchronous Interrupts Some peripherals are able to generate events when the system is in run mode and also when the system is in Stop mode, allowing to wake up the system from Stop mode. To accomplish this, the peripheral generates both a synchronized (to the system clock, e.g. APB clock) and an asynchronous version of the event. This asynchronous event is connected to an EXTI direct line. Note: Few peripherals with wakeup from Stop capability are connected to an EXTI configurable line. In this case, the EXTI configuration is necessary to allow the wakeup from Stop mode. 13.3.4 Hardware interrupt selection To configure a line as an interrupt source, use the following procedure: 1. Configure the corresponding mask bit in the EXTI_IMR register. 2. Configure the Trigger Selection bits of the Interrupt line (EXTI_RTSR and EXTI_FTSR). 3. Configure the enable and mask bits that control the NVIC IRQ channel mapped to the EXTI so that an interrupt coming from one of the EXTI lines can be correctly acknowledged. Note: The direct lines do not require any EXTI configuration. 13.3.5 Hardware event selection To configure a line as an event source, use the following procedure: 13.3.6 1. Configure the corresponding mask bit in the EXTI_EMR register. 2. Configure the Trigger Selection bits of the Event line (EXTI_RTSR and EXTI_FTSR). Software interrupt/event selection Any of the configurable lines can be configured as a software interrupt/event line. The procedure to generate a software interrupt is as follows: 13.4 1. Configure the corresponding mask bit (EXTI_IMR, EXTI_EMR). 2. Set the required bit of the software interrupt register (EXTI_SWIER). EXTI interrupt/event line mapping In the STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx, 38 interrupt/event lines are available. The GPIOs are connected to 16 configurable interrupt/event lines (see Figure 29). RM0394 Rev 4 327/1600 337 Extended interrupts and events controller (EXTI) RM0394 Figure 29. External interrupt/event GPIO mapping (;7,>@ELWVLQWKH6<6&)*B(;7,&5UHJLVWHU 3$ 3% 3& 3' 3( (;7, (;7,>@ELWVLQWKH6<6&)*B(;7,&5UHJLVWHU 3$ 3% 3& 3' 3( (;7, (;7,>@ELWVLQWKH6<6&)*B(;7,&5UHJLVWHU 3$ 3% 3& 3' 3( (;7, 06Y9 The 38 lines are connected as shown in Table 47: EXTI lines connections. Table 47. EXTI lines connections EXTI line Line source(1) Line type 0-15 GPIO configurable 16 PVD 17 328/1600 USB FS wakeup event configurable (3)(2) direct 18 RTC alarms configurable 19 RTC tamper or timestamp or CSS_LSE configurable 20 RTC wakeup timer configurable 21 COMP1 output configurable 22 COMP2 output configurable 23 I2C1 wakeup(3) direct RM0394 Rev 4 RM0394 Extended interrupts and events controller (EXTI) Table 47. EXTI lines connections (continued) Line source(1) EXTI line 24 I2C2 wakeup 25 26 27 28 I2C3 wakeup USART1 USART3 direct direct wakeup(3) direct (3) direct USART2 wakeup 30 29 Line type (3)(4) wakeup(3)(4) - direct - UART4 wakeup (3)(5) direct 31 LPUART1 wakeup direct 32 LPTIM1 direct 33 LPTIM2 (6) direct 34 SWPMI1 wakeup(3)(7) direct 35 PVM1 wakeup configurable 36 - - 37 PVM3 wakeup configurable 38 PVM4 wakeup configurable 39 (8) direct (5) direct LCD wakeup 40 I2C4 wakeup 1. All the lines can wake up from the Stop 0 and Stop 1 modes. All the lines, except the ones mentioned above, can wake up from the Stop 2 mode. 2. Not available for STM32L431xx devices. 3. This line source cannot wake up from the Stop 2 mode. 4. Not available on STM32L432xx and STM32L442xx devices. 5. Available on STM32L45xxx and STM32L46xxx devices only. 6. This line can wake up from Stop 2 mode on STM32L41xxx and STM32L42xx devices only. 7. Available on STM32L43xxx and STM32L44xxx devices only. 8. Available on STM32L4x3 devices only. RM0394 Rev 4 329/1600 337 Extended interrupts and events controller (EXTI) 13.5 RM0394 EXTI registers Refer to Section 1.2 on page 60 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 13.5.1 Interrupt mask register 1 (EXTI_IMR1) Address offset: 0x00 Reset value: 0xFF82 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IM31 Res. Res. IM28 IM27 IM26 IM25 IM24 IM23 IM22 IM21 IM20 IM19 IM18 IM17 IM16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 IM31: Interrupt Mask on line 31 0: Interrupt request from Line 31 is masked 1: Interrupt request from Line 31 is not masked Bits 30:29 Reserved, must be kept at reset value. Bits 28:0 IMx: Interrupt Mask on line x (x = 28 to 0) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is not masked Note: The reset value for the direct lines (line 17, lines from 23 to 34, line 39) is set to ‘1’ in order to enable the interrupt by default. 13.5.2 Event mask register 1 (EXTI_EMR1) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EM31 Res. Res. EM28 EM27 EM26 EM25 EM24 EM23 EM22 EM21 EM20 EM19 EM18 EM17 EM16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EM15 EM14 EM13 EM12 EM11 EM10 EM9 EM8 EM7 EM6 EM5 EM4 EM3 EM2 EM1 EM0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 330/1600 RM0394 Rev 4 RM0394 Extended interrupts and events controller (EXTI) Bit 31 EM31: Event mask on line 31 0: Event request from line 31 is masked 1: Event request from line 31 is not masked Bits 30:29 Reserved, must be kept at reset value. Bits 28:0 EMx: Event mask on line x (x = 28 to 0) 0: Event request from line x is masked 1: Event request from line x is not masked 13.5.3 Rising trigger selection register 1 (EXTI_RTSR1) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. RT22 RT21 RT20 RT19 RT18 Res. RT16 rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:23 Reserved, must be kept at reset value. Bits 22:18 RTx: Rising trigger event configuration bit of line x (x = 22 to 18) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line Bit 17 Reserved, must be kept at reset value. Bits 16:0 RTx: Rising trigger event configuration bit of line x (x = 16 to 0) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition. 13.5.4 Falling trigger selection register 1 (EXTI_FTSR1) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. FT22 FT21 FT20 FT19 FT18 Res. FT16 rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FT15 FT14 FT13 FT12 FT11 FT10 FT9 FT8 FT7 FT6 FT5 FT4 FT3 FT2 FT1 FT0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RM0394 Rev 4 rw 331/1600 337 Extended interrupts and events controller (EXTI) RM0394 Bits 31:23 Reserved, must be kept at reset value. Bits 22:18 FTx: Falling trigger event configuration bit of line x (x = 22 to 18) 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line Bit 17 Reserved, must be kept at reset value. Bits 16:0 FTx: Falling trigger event configuration bit of line x (x = 16 to 0) 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a falling edge on a configurable interrupt line occurs during a write operation to the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition. 13.5.5 Software interrupt event register 1 (EXTI_SWIER1) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 SWI 22 SWI 21 SWI 20 SWI 19 SWI 18 17 16 Res. SWI 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWI 15 SWI 14 SWI 13 SWI 12 SWI 11 SWI 10 SWI 9 SWI 8 SWI 7 SWI 6 SWI 5 SWI 4 SWI 3 SWI 2 SWI 1 SWI 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:23 Reserved, must be kept at reset value. Bits 22: 18 SWIx: Software interrupt on line x (x = 22 o 18) If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in the EXTI_PR register (by writing a ‘1’ into the bit). Bit 17 Reserved, must be kept at reset value. Bits 16:0 SWIx: Software interrupt on line x (x = 16 to 0) If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a ‘1’ into the bit). 332/1600 RM0394 Rev 4 RM0394 Extended interrupts and events controller (EXTI) 13.5.6 Pending register 1 (EXTI_PR1) Address offset: 0x14 Reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. PIF22 PIF21 PIF20 PIF19 PIF18 Res. PIF16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIF15 PIF14 PIF13 PIF12 PIF11 PIF10 PIF9 PIF8 PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:23 Reserved, must be kept at reset value. Bits 22:18 PIFx: Pending interrupt flag on line x (x = 22 to 18) 0: No trigger request occurred 1: Selected trigger request occurred This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a ‘1’ to the bit. Bit 17 Reserved, must be kept at reset value. Bits 16:0 PIFx: Pending interrupt flag on line x (x = 16 to 0) 0: No trigger request occurred 1: Selected trigger request occurred This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a ‘1’ to the bit. 13.5.7 Interrupt mask register 2 (EXTI_IMR2) Address offset: 0x20 Reset value: 0x0000 0087 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res IM39 IM38 IM37 IM36 IM35 IM34 IM33 IM32 rw rw rw rw rw rw rw rw Bits 31:8 Reserved, must be kept at reset value Bits 7:0 IMx: Interrupt mask on line x (x = 39 to 32) 0: Interrupt request from line x is masked 1: Interrupt request from line x is not masked Note: The reset value for the direct lines (line 17, lines from 23 to 34, line 39,) is set to ‘1’ in order to enable the interrupt by default. RM0394 Rev 4 333/1600 337 Extended interrupts and events controller (EXTI) 13.5.8 RM0394 Event mask register 2 (EXTI_EMR2) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res EM39 EM38 EM37 EM36 EM35 EM34 EM33 EM32 rw rw rw rw rw rw rw rw Bits 31:8 Reserved, must be kept at reset value Bits 7:0 EMx: Event mask on line x (x = 39 to 32) 0: Event request from line x is masked 1: Event request from line x is not masked 13.5.9 Rising trigger selection register 2 (EXTI_RTSR2) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. RT38 RT37 RT36 RT35 Res. Res. Res. rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:3 RTx: Rising trigger event configuration bit of line x (x = 35 to 38) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line Bits 2:0 Reserved, must be kept at reset value. Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation to the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition. 334/1600 RM0394 Rev 4 RM0394 Extended interrupts and events controller (EXTI) 13.5.10 Falling trigger selection register 2 (EXTI_FTSR2) Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. FT38 FT37 FT36 FT35 Res. Res. Res. rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:3 FTx: Falling trigger event configuration bit of line x (x = 35 to 38) 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line Bits 2:0 Reserved, must be kept at reset value. Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a falling edge on a configurable interrupt line occurs during a write operation to the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition. 13.5.11 Software interrupt event register 2 (EXTI_SWIER2) Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. SWI 38 SWI 37 SWI 36 SWI 35 Res. Res. Res. rw rw rw rw Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:8 Reserved, must be kept at reset value. Bit 7 SWIx: Software interrupt on line x (x = 35 to 38) If the interrupt is enabled on this line in EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit of EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a ‘1’ to the bit). Bits 2:0 Reserved, must be kept at reset value. RM0394 Rev 4 335/1600 337 Extended interrupts and events controller (EXTI) 13.5.12 RM0394 Pending register 2 (EXTI_PR2) Address offset: 0x34 Reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. PIF38 PIF37 PIF36 PIF35 Res. Res. Res. rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:8 Reserved, must be kept at reset value. Bit 7 PIFx: Pending interrupt flag on line x (x = 35 to 38) 0: No trigger request occurred 1: Selected trigger request occurred This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a ‘1’ into the bit. Bits 2:0 Reserved, must be kept at reset value. 336/1600 RM0394 Rev 4 0x34 EXTI_PR2 RM0394 Rev 4 EM32 PIF0 0 0 IM32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RT0 0 FT0 0 SWI0 0 EM1 EM0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0 IM3 IM2 IM1 IM0 0 0 0 0 0 0 Res. 0 RT1 0 FT1 0 EM2 0 EM3 IM6 0 RT2 IM7 0 RT3 IM8 0 IM5 IM4 IM9 0 RT5 RT4 IM11 IM10 0 FT2 EM6 RT6 IM12 0 EM5 EM4 EM7 RT7 IM13 0 FT3 FT6 EM8 RT8 IM14 0 FT5 FT4 FT7 EM9 RT9 IM15 0 SWI1 SWI6 FT8 IM16 0 SWI2 SWI7 FT9 RT10 IM17 1 SWI3 SWI8 EM10 0 RT11 IM18 0 SWI5 SWI4 SWI9 EM11 0 RT12 IM19 0 Res. PIF1 0 IM33 0 Res. FT10 EM12 0 RT13 IM20 0 Res. EM33 PIF2 0 Res. SWI10 FT11 EM13 0 RT14 IM21 0 Res. PIF3 0 IM34 PIF5 PIF4 0 IM35 PIF6 0 Res. SWI11 FT12 EM14 0 RT15 IM22 0 Res. EM34 PIF7 0 Res. SWI12 FT13 EM15 0 RT16 IM23 1 Res. PIF8 0 Res. SWI13 FT14 EM16 0 Res. IM24 1 Res. EM35 0 RT35 PIF9 0 IM36 PIF10 0 Res. SWI14 FT15 EM17 0 Res. IM25 1 Res. FT35 EM36 0 RT36 PIF11 0 IM37 PIF12 0 Res. SWI15 EM18 0 Res. IM26 1 Res. SWI35 0 PIF35 FT36 EM37 0 RT37 PIF13 0 IM38 PIF14 0 IM39 PIF15 0 Res. FT16 EM19 0 Res. IM27 1 Res. SWI36 0 PIF36 FT37 EM38 0 RT38 EM39 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. SWI16 EM20 0 RT18 EM21 0 RT19 EM22 0 RT20 EM23 0 RT21 EM24 0 Res. Res. IM28 1 Res. SWI37 Reset value PIF37 Reset value FT38 Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value SWI38 Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value PIF38 Reset value PIF16 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. FT18 0 Res. SWI18 FT19 0 Res. PIF18 0 Res. SWI19 FT20 0 Res. PIF19 0 Res. SWI20 FT21 0 Res. PIF20 0 Res. SWI21 0 Res. PIF21 0 Res. EM25 0 0 Res. Res. Res. Res. Res. EM26 0 RT22 EM27 0 Res. Res. EM28 0 Res. Res. 0 0 Res. Res. Res. Res. Res. FT22 Res. Res. Res. Res. Res. Res. Res. Res. IM31 Res. EM31 Res. Res. 0 0 Res. Res. Res. Res. Res. SWI22 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. Res. Res. Res. Res. PIF22 Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. EXTI_SWIER2 Res. EXTI_FTSR2 Res. EXTI_RTSR2 Res. EXTI_EMR2 Res. EXTI_IMR2 Res. EXTI_PR1 Res. 0x30 EXTI_RTSR1 Res. 0x2C 0 Res. 0x28 Reset value Res. 0x24 EXTI_EMR1 Res. 0x20 EXTI_SWIER1 Res. 0x14 1 Res. 0x10 EXTI_FTSR1 Res. 0x0C Reset value Res. 0x08 Res. 0x04 EXTI_IMR1 Res. 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 13.5.13 Res. RM0394 Extended interrupts and events controller (EXTI) EXTI register map Table 48 gives the EXTI register map and the reset values. Table 48. Extended interrupt/event controller register map and reset values 1 0 0 0 0 1 1 1 337/1600 337 Cyclic redundancy check calculation unit (CRC) 14 Cyclic redundancy check calculation unit (CRC) 14.1 Introduction RM0394 The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16or 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the functional safety standards, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location. 14.2 CRC main features • Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7 X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1 338/1600 • Alternatively, uses fully programmable polynomial with programmable size (7, 8, 16, 32 bits) • Handles 8-,16-, 32-bit data size • Programmable CRC initial value • Single input/output 32-bit data register • Input buffer to avoid bus stall during calculation • CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size • General-purpose 8-bit register (can be used for temporary storage) • Reversibility option on I/O data RM0394 Rev 4 RM0394 Cyclic redundancy check calculation unit (CRC) 14.3 CRC functional description 14.3.1 CRC block diagram Figure 30. CRC calculation unit block diagram ELW$+%EXV ELW UHDGDFFHVV 'DWDUHJLVWHU RXWSXW FUFBKFON &5&FRPSXWDWLRQ ELW ZULWHDFFHVV 'DWDUHJLVWHU LQSXW D^ϭϵϴϴϮsϮ 14.3.2 CRC internal signals Table 49. CRC internal input/output signals 14.3.3 Signal name Signal type crc_hclk Digital input Description AHB clock CRC operation The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to input new data (write access), and holds the result of the previous CRC calculation (read access). Each write operation to the data register creates a combination of the previous CRC value (stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data word or byte by byte depending on the format of the data being written. The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned byte. For the other registers only 32-bit access is allowed. The duration of the computation depends on data width: • 4 AHB clock cycles for 32-bit • 2 AHB clock cycles for 16-bit • 1 AHB clock cycles for 8-bit An input buffer allows to immediately write a second data without waiting for any wait states due to the previous CRC calculation. The data size can be dynamically adjusted to minimize the number of write accesses for a given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write followed by a byte write. RM0394 Rev 4 339/1600 343 Cyclic redundancy check calculation unit (CRC) RM0394 The input data can be reversed, to manage the various endianness schemes. The reversing operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits in the CRC_CR register. For example: input data 0x1A2B3C4D is used for CRC calculation as: • 0x58D43CB2 with bit-reversal done by byte • 0xD458B23C with bit-reversal done by half-word • 0xB23CD458 with bit-reversal done on the full word The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register. The operation is done at bit level: for example, output data 0x11223344 is converted into 0x22CC4488. The CRC calculator can be initialized to a programmable value using the RESET control bit in the CRC_CR register (the default value is 0xFFFFFFFF). The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR register is automatically initialized upon CRC_INIT register write access. The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It is not affected by the RESET bit in the CRC_CR register. Polynomial programmability The polynomial coefficients are fully programmable through the CRC_POL register, and the polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported. If the CRC data is less than 32-bit, its value can be read from the least significant bits of the CRC_DR register. To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the application must either reset it or perform a CRC_DR read before changing the polynomial. The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7. 340/1600 RM0394 Rev 4 RM0394 Cyclic redundancy check calculation unit (CRC) 14.4 CRC registers 14.4.1 Data register (CRC_DR) Address offset: 0x00 Reset value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DR[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DR[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 DR[31:0]: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. 14.4.2 Independent data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. IDR[7:0] rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 IDR[7:0]: General-purpose 8-bit data register bits These bits can be used as a temporary storage location for one byte. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register RM0394 Rev 4 341/1600 343 Cyclic redundancy check calculation unit (CRC) 14.4.3 RM0394 Control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. REV_ OUT Res. Res. RESET Res. Res. Res. Res. Res. Res. Res. rw REV_IN[1:0] rw rw POLYSIZE[1:0] rw rw rs Bits 31:8 Reserved, must be kept at reset value. Bit 7 REV_OUT: Reverse output data This bit controls the reversal of the bit order of the output data. 0: Bit order not affected 1: Bit-reversed output format Bits 6:5 REV_IN[1:0]: Reverse input data These bits control the reversal of the bit order of the input data 00: Bit order not affected 01: Bit reversal done by byte 10: Bit reversal done by half-word 11: Bit reversal done by word Bits 4:3 POLYSIZE[1:0]: Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial Bits 2:1 Reserved, must be kept at reset value. Bit 0 RESET: RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware 14.4.4 Initial CRC value (CRC_INIT) Address offset: 0x10 Reset value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CRC_INIT[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CRC_INIT[15:0] rw 342/1600 rw rw rw rw rw rw rw rw RM0394 Rev 4 RM0394 Cyclic redundancy check calculation unit (CRC) Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value This register is used to write the CRC initial value. 14.4.5 CRC polynomial (CRC_POL) Address offset: 0x14 Reset value: 0x04C1 1DB7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 POL[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw POL[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 POL[31:0]: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. 14.4.6 CRC register map Offset Register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 50. CRC register map and reset values CRC_DR DR[31:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_IDR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. CRC_CR 0x08 Reset value 0x10 CRC_INIT Reset value 0x14 1 1 1 1 1 1 1 0 0 0 IDR[7:0] REV_OUT 0x04 1 Res. 1 RESET 1 0 0 0 0 Res. 1 POLYSIZE[1:0] 1 REV_IN[1:0] Reset value Res. 0x00 0 0 0 0 0 1 1 1 1 1 0 CRC_INIT[31:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_POL Polynomial coefficients Reset value 0x04C11DB7 1 1 1 1 1 1 1 1 Refer to Section 2.2.2 on page 67 for the register boundary addresses. RM0394 Rev 4 343/1600 343 Quad-SPI interface (QUADSPI) RM0394 15 Quad-SPI interface (QUADSPI) 15.1 Introduction The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes: • indirect mode: all the operations are performed using the QUADSPI registers • status polling mode: the external Flash memory status register is periodically read and an interrupt can be generated in case of flag setting • memory-mapped mode: the external Flash memory is mapped to the device address space and is seen by the system as if it was an internal memory Both throughput and capacity can be increased two-fold using dual-flash mode, where two Quad-SPI Flash memories are accessed simultaneously. 15.2 QUADSPI main features • Three functional modes: indirect, status-polling, and memory-mapped • Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two Flash memories in parallel. • SDR and DDR support • Fully programmable opcode for both indirect and memory mapped mode • Fully programmable frame format for both indirect and memory mapped mode • Integrated FIFO for reception and transmission • 8, 16, and 32-bit data accesses are allowed • DMA channel for indirect mode operations • Interrupt generation on FIFO threshold, timeout, operation complete, and access error 15.3 QUADSPI functional description 15.3.1 QUADSPI block diagram Figure 31. QUADSPI block diagram when dual-flash mode is disabled 48$'63, 5HJLVWHUV FRQWURO &ORFN PDQDJHPHQW $+% ),)2 6KLIWUHJLVWHU 63,)/$6+ &/. %.B,262 %.B,26, %.B,2 %.B,2 %.BQ&6 &/. 46, 462 4:3 4+2/' &6 069 344/1600 RM0394 Rev 4 RM0394 Quad-SPI interface (QUADSPI) Figure 32. QUADSPI block diagram when dual-flash mode is enabled 48$'63, 5HJLVWHUV FRQWURO &ORFN PDQDJHPHQW 63,)/$6+ &/. %.B,262 %.B,26, %.B,2 %.B,2 %.BQ&6 $+% ),)2 &/. 46, 462 4:3 4+2/' &6 63,)/$6+ 6KLIWUHJLVWHU &/. 46, 462 4:3 4+2/' &6 %.B,262 %.B,26, %.B,2 %.B,2 %.BQ&6 069 15.3.2 QUADSPI pins Table 51 lists the QUADSPI pins, six for interfacing with a single Flash memory, or 10 to 11 for interfacing with two Flash memories (FLASH 1 and FLASH 2) in dual-flash mode. Table 51. QUADSPI pins Signal name Signal type Description CLK Digital output Clock to FLASH 1 and FLASH 2 BK1_IO0/SO Digital input/output Bidirectional IO in dual/quad modes or serial output in single mode, for FLASH 1 BK1_IO1/SI Digital input/output Bidirectional IO in dual/quad modes or serial input in single mode, for FLASH 1 BK1_IO2 Digital input/output Bidirectional IO in quad mode, for FLASH 1 BK1_IO3 Digital input/output Bidirectional IO in quad mode, for FLASH 1 BK2_IO0/SO Digital input/output Bidirectional IO in dual/quad modes or serial output in single mode, for FLASH 2 BK2_IO1/SI Digital input/output Bidirectional IO in dual/quad modes or serial input in single mode, for FLASH 2 BK2_IO2 Digital input/output Bidirectional IO in quad mode, for FLASH 2 BK2_IO3 Digital input/output Bidirectional IO in quad mode, for FLASH 2 BK1_nCS Digital output Chip select (active low) for FLASH 1. Can also be used for FLASH 2 if QUADSPI is always used in dual-flash mode. BK2_nCS Digital output Chip select (active low) for FLASH 2. Can also be used for FLASH 1 if QUADSPI is always used in dual-flash mode. RM0394 Rev 4 345/1600 372 Quad-SPI interface (QUADSPI) 15.3.3 RM0394 QUADSPI command sequence The QUADSPI communicates with the Flash memory using commands. Each command can include 5 phases: instruction, address, alternate byte, dummy, data. Any of these phases can be configured to be skipped, but at least one of the instruction, address, alternate byte, or data phase must be present. nCS falls before the start of each command and rises again after each command finishes. Figure 33. An example of a read command in quad mode ,QVWUXFWLRQ $GGUHVV $OW 'XPP\ 'DWD Q&6 6&/. ,2 ,2 ,2 ,2 $ $ $ 0 %\WH ,2VZLWFKIURP RXWSXWWRLQSXW %\WH 069 Instruction phase During this phase, an 8-bit instruction, configured in INSTRUCTION field of QUADSPI_CCR[7:0] register, is sent to the Flash memory, specifying the type of operation to be performed. Though most Flash memories can receive instructions only one bit at a time from the IO0/SO signal (single SPI mode), the instruction phase can optionally send 2 bits at a time (over IO0/IO1 in dual SPI mode) or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the IMODE[1:0] field of QUADSPI_CCR[9:8] register. When IMODE = 00, the instruction phase is skipped, and the command sequence starts with the address phase, if present. Address phase In the address phase, 1-4 bytes are sent to the Flash memory to indicate the address of the operation. The number of address bytes to be sent is configured in the ADSIZE[1:0] field of QUADSPI_CCR[13:12] register. In indirect and automatic-polling modes, the address bytes to be sent are specified in the ADDRESS[31:0] field of QUADSPI_AR register, while in memory-mapped mode the address is given directly via the AHB (from the Cortex® or from a DMA). The address phase can send 1 bit at a time (over SO in single SPI mode), 2 bits at a time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the ADMODE[1:0] field of QUADSPI_CCR[11:10] register. When ADMODE = 00, the address phase is skipped, and the command sequence proceeds directly to the next phase, if any. 346/1600 RM0394 Rev 4 RM0394 Quad-SPI interface (QUADSPI) Alternate-bytes phase In the alternate-bytes phase, 1-4 bytes are sent to the Flash memory, generally to control the mode of operation. The number of alternate bytes to be sent is configured in the ABSIZE[1:0] field of QUADSPI_CCR[17:16] register. The bytes to be sent are specified in the QUADSPI_ABR register. The alternate-bytes phase can send 1 bit at a time (over SO in single SPI mode), 2 bits at a time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14] register. When ABMODE = 00, the alternate-bytes phase is skipped, and the command sequence proceeds directly to the next phase, if any. There may be times when only a single nibble needs to be sent during the alternate-byte phase rather than a full byte, such as when dual-mode is used and only two cycles are used for the alternate bytes. In this case, firmware can use quad-mode (ABMODE = 11) and send a byte with bits 7 and 3 of ALTERNATE set to ‘1’ (keeping the IO3 line high), and bits 6 and 2 set to ‘0’ (keeping the IO2 line low). In this case the upper two bits of the nibble to be sent are placed in bits 4:3 of ALTERNATE while the lower two bits are placed in bits 1 and 0. For example, if the nibble 2 (0010) is to be sent over IO0/IO1, then ALTERNATE should be set to 0x8A (1000_1010). Dummy-cycles phase In the dummy-cycles phase, 1-31 cycles are given without any data being sent or received, in order to allow the Flash memory the time to prepare for the data phase when higher clock frequencies are used. The number of cycles given during this phase is specified in the DCYC[4:0] field of QUADSPI_CCR[22:18] register. In both SDR and DDR modes, the duration is specified as a number of full CLK cycles. When DCYC is zero, the dummy-cycles phase is skipped, and the command sequence proceeds directly to the data phase, if present. The operating mode of the dummy-cycles phase is determined by DMODE. In order to assure enough “turn-around” time for changing the data signals from output mode to input mode, there must be at least one dummy cycle when using dual or quad mode to receive data from the Flash memory. Data phase During the data phase, any number of bytes can be sent to, or received from the Flash memory. In indirect and automatic-polling modes, the number of bytes to be sent/received is specified in the QUADSPI_DLR register. In indirect write mode the data to be sent to the Flash memory must be written to the QUADSPI_DR register, while in indirect read mode the data received from the Flash memory is obtained by reading from the QUADSPI_DR register. In memory-mapped mode, the data which is read is sent back directly over the AHB to the Cortex or to a DMA. The data phase can send/receive 1 bit at a time (over SO/SI in single SPI mode), 2 bits at a time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI RM0394 Rev 4 347/1600 372 Quad-SPI interface (QUADSPI) RM0394 mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14] register. When DMODE = 00, the data phase is skipped, and the command sequence finishes immediately by raising nCS. This configuration must only be used in only indirect write mode. 15.3.4 QUADSPI signal interface protocol modes Single SPI mode Legacy SPI mode allows just a single bit to be sent/received serially. In this mode, data is sent to the Flash memory over the SO signal (whose I/O shared with IO0). Data received from the Flash memory arrives via SI (whose I/O shared with IO1). The different phases can each be configured separately to use this single bit mode by setting the IMODE/ADMODE/ABMODE/DMODE fields (in QUADSPI_CCR) to 01. In each phase which is configured in single mode: • IO0 (SO) is in output mode • IO1 (SI) is in input mode (high impedance) • IO2 is in output mode and forced to ‘0’ (to deactivate the “write protect” function) • IO3 is in output mode and forced to ‘1’ (to deactivate the “hold” function) This is the case even for the dummy phase if DMODE = 01. Dual SPI mode In dual SPI mode, two bits are sent/received simultaneously over the IO0/IO1 signals. The different phases can each be configured separately to use dual SPI mode by setting the IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 10. In each phase which is configured in dual mode: • IO0/IO1 are at high-impedance (input) during the data phase for read operations, and outputs in all other cases • IO2 is in output mode and forced to ‘0’ • IO3 is in output mode and forced to ‘1’ In the dummy phase when DMODE = 01, IO0/IO1 are always high-impedance. Quad SPI mode In quad SPI mode, four bits are sent/received simultaneously over the IO0/IO1/IO2/IO3 signals. The different phases can each be configured separately to use quad SPI mode by setting the IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 11. In each phase which is configured in quad mode, IO0/IO1/IO2/IO3 are all are at highimpedance (input) during the data phase for read operations, and outputs in all other cases. In the dummy phase when DMODE = 11, IO0/IO1/IO2/IO3 are all high-impedance. IO2 and IO3 are used only in Quad SPI mode. If none of the phases are configured to use Quad SPI mode, then the pins corresponding to IO2 and IO3 can be used for other functions even while QUADSPI is active. 348/1600 RM0394 Rev 4 RM0394 Quad-SPI interface (QUADSPI) SDR mode By default, the DDRM bit (QUADSPI_CCR[31]) is 0 and the QUADSPI operates in single data rate (SDR) mode. In SDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals, these signals transition only with the falling edge of CLK. When receiving data in SDR mode, the QUADSPI assumes that the Flash memories also send the data using CLK’s falling edge. By default (when SSHIFT = 0), the signals are sampled using the following (rising) edge of CLK. DDR mode When the DDRM bit (QUADSPI_CCR[31]) is set to 1, the QUADSPI operates in double data rate (DDR) mode. In DDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals in the address/alternate-byte/data phases, a bit is sent on each of the falling and rising edges of CLK. The instruction phase is not affected by DDRM. The instruction is always sent using CLK’s falling edge. When receiving data in DDR mode, the QUADSPI assumes that the Flash memories also send the data using both rising and falling CLK edges. When DDRM = 1, firmware must clear SSHIFT bit (bit 4 of QUADSPI_CR). Thus, the signals are sampled one half of a CLK cycle later (on the following, opposite edge). Figure 34. An example of a DDR command in quad mode ,QVWUXFWLRQ $GGUHVV $OW 'XPP\ 'DWD Q&6 6&/. ,2 ,2 ,2 ,2 $$ $ 0 %\WH%\WH ,2VZLWFKIURP RXWSXWWRLQSXW 069 Dual-flash mode When the DFM bit (bit 6 of QUADSPI_CR) is 1, the QUADSPI is in dual-flash mode, where two external quad SPI Flash memories (FLASH 1 and FLASH 2) are used in order to send/receive 8 bits (or 16 bits in DDR mode) every cycle, effectively doubling the throughput as well as the capacity. Each of the Flash memories use the same CLK and optionally the same nCS signals, but each have separate IO0, IO1, IO2, and IO3 signals. Dual-flash mode can be used in conjunction with single-bit, dual-bit, and quad-bit modes, as well as with either SDR or DDR mode. RM0394 Rev 4 349/1600 372 Quad-SPI interface (QUADSPI) RM0394 The Flash memory size, as specified in FSIZE[4:0] (QUADSPI_DCR[20:16]), should reflect the total Flash memory capacity, which is double the size of one individual component. If address X is even, then the byte which the QUADSPI gives for address X is the byte at the address X/2 of FLASH 1, and the byte which the QUADSPI gives for address X+1 is the byte at the address X/2 of FLASH 2. In other words, bytes at even addresses are all stored in FLASH 1 and bytes at odd addresses are all stored in FLASH 2. When reading the Flash memories status registers in dual-flash mode, twice as many bytes should be read compared to doing the same read in single-flash mode. This means that if each Flash memory gives 8 valid bits after the instruction for fetching the status register, then the QUADSPI must be configured with a data length of 2 bytes (16 bits), and the QUADSPI will receive one byte from each Flash memory. If each Flash memory gives a status of 16 bits, then the QUADSPI must be configured to read 4 bytes to get all the status bits of both Flash memories in dual-flash mode. The least-significant byte of the result (in the data register) is the least-significant byte of FLASH 1 status register, while the next byte is the least-significant byte of FLASH 2 status register. Then, the third byte of the data register is FLASH 1 second byte, while the forth byte is FLASH 2 second byte (in the case that the Flash memories have 16-bit status registers). An even number of bytes must always be accessed in dual-flash mode. For this reason, bit 0 of the data length field (QUADSPI_DLR[0]) is stuck at 1 when DRM = 1. In dual-flash mode, the behavior of FLASH 1 interface signals are basically the same as in normal mode. FLASH 2 interface signals have exactly the same waveforms as FLASH 1 during the instruction, address, alternate-byte, and dummy-cycles phases. In other words, each Flash memory always receives the same instruction and the same address. Then, during the data phase, the BK1_IOx and BK2_IOx buses are both transferring data in parallel, but the data that are sent to (or received from) FLASH 1 are distinct from those of FLASH 2. 15.3.5 QUADSPI indirect mode When in indirect mode, commands are started by writing to QUADSPI registers and data is transferred by writing or reading the data register, in the same way as for other communication peripherals. When FMODE = 00 (QUADSPI_CCR[27:26]), the QUADSPI is in indirect write mode, where bytes are sent to the Flash memory during the data phase. Data are provided by writing to the data register (QUADSPI_DR). When FMODE = 01, the QUADSPI is in indirect read mode, where bytes are received from the Flash memory during the data phase. Data are recovered by reading QUADSPI_DR. The number of bytes to be read/written is specified in the data length register (QUADSPI_DLR). If QUADSPI_DLR = 0xFFFF_FFFF (all 1’s), then the data length is considered undefined and the QUADSPI simply continues to transfer data until the end of Flash memory (as defined by FSIZE) is reached. If no bytes are to be transferred, DMODE (QUADSPI_CCR[25:24]) should be set to 00. If QUADSPI_DLR = 0xFFFF_FFFF and FSIZE = 0x1F (max value indicating a 4GB Flash memory), then in this special case the transfers continue indefinitely, stopping only after an abort request or after the QUADSPI is disabled. After the last memory address is read (at address 0xFFFF_FFFF), reading continues with address = 0x0000_0000. When the programmed number of bytes to be transmitted or received is reached, TCF is set and an interrupt is generated if TCIE = 1. In the case of undefined number of data, the TCF 350/1600 RM0394 Rev 4 RM0394 Quad-SPI interface (QUADSPI) is set when the limit of the external SPI memory is reached according to the Flash memory size defined in the QUADSPI_CR. Triggering the start of a command Essentially, a command starts as soon as firmware gives the last information that is necessary for this command. Depending on the QUADSPI configuration, there are three different ways to trigger the start of a command in indirect mode. The commands starts immediately after: 1. a write is performed to INSTRUCTION[7:0] (QUADSPI_CCR), if no address is necessary (when ADMODE = 00) and if no data needs to be provided by the firmware (when FMODE = 01 or DMODE = 00) 2. a write is performed to ADDRESS[31:0] (QUADSPI_AR), if an address is necessary (when ADMODE != 00) and if no data needs to be provided by the firmware (when FMODE = 01 or DMODE = 00) 3. a write is performed to DATA[31:0] (QUADSPI_DR), if an address is necessary (when ADMODE != 00) and if data needs to be provided by the firmware (when FMODE = 00 and DMODE != 00) Writes to the alternate byte register (QUADSPI_ABR) never trigger the communication start. If alternate bytes are required, they must be programmed before. As soon as a command is started, the BUSY bit (bit 5 of QUADSPI_SR) is automatically set. FIFO and data management In indirect mode, data go through a 16-byte FIFO which is internal to the QUADSPI. FLEVEL[4:0] (QUADSPI_SR[12:8]) indicates how many bytes are currently being held in the FIFO. In indirect write mode (FMODE = 00), firmware adds data to the FIFO when it writes QUADSPI_DR. Word writes add 4 bytes to the FIFO, halfword writes add 2 bytes, and byte writes add only 1 byte. If firmware adds too many bytes to the FIFO (more than is indicated by DL[31:0]), the extra bytes are flushed from the FIFO at the end of the write operation (when TCF is set). Byte/halfword accesses to QUADSPI_DR must be done only to the least significant byte/halfword of the 32-bit register. FTHRES[3:0] is used to define a FIFO threshold. When the threshold is reached, the FTF (FIFO threshold flag) is set. In indirect read mode, FTF is set when the number of valid bytes to be read from the FIFO is above the threshold. FTF is also set if there are data in the FIFO after the last byte is read from the Flash memory, regardless of the FTHRES setting. In indirect write mode, FTF is set when the number of empty bytes in the FIFO is above the threshold. If FTIE = 1, there is an interrupt when FTF is set. If DMAEN = 1, a DMA transfer is initiated when FTF is set. FTF is cleared by HW as soon as the threshold condition is no longer true (after enough data has been transferred by the CPU or DMA). In indirect read mode when the FIFO becomes full, the QUADSPI temporarily stops reading bytes from the Flash memory to avoid an overrun. Note that the reading of the Flash memory does not restart until 4 bytes become vacant in the FIFO (when FLEVEL ≤ 11). Thus, when FTHRES ≥ 13, the application must take care to read enough bytes to assure that the QUADSPI starts retrieving data from the Flash memory again. Otherwise, the FTF flag stays at '0' as long as 11 < FLEVEL < FTHRES. RM0394 Rev 4 351/1600 372 Quad-SPI interface (QUADSPI) 15.3.6 RM0394 QUADSPI status flag polling mode In automatic-polling mode, the QUADSPI periodically starts a command to read a defined number of status bytes (up to 4). The received bytes can be masked to isolate some status bits and an interrupt can be generated when the selected bits have a defined value. The accesses to the Flash memory begin in the same way as in indirect read mode: if no address is required (AMODE = 00), accesses begin as soon as the QUADSPI_CCR is written. Otherwise, if an address is required, the first access begins when QUADSPI_AR is written. BUSY goes high at this point and stays high even between the periodic accesses. The contents of MASK[31:0] (QUADSPI_PSMAR) are used to mask the data from the Flash memory in automatic-polling mode. If the MASK[n] = 0, then bit n of the result is masked and not considered. If MASK[n] = 1, and the content of bit[n] is the same as MATCH[n] (QUADSPI_PSMAR), then there is a match for bit n. If the polling match mode bit (PMM, bit 23 of QUADSPI_CR) is 0, then “AND” match mode is activated. This means status match flag (SMF) is set only when there is a match on all of the unmasked bits. If PMM = 1, then “OR” match mode is activated. This means SMF is set if there is a match on any of the unmasked bits. An interrupt is called when SMF is set if SMIE = 1. If the automatic-polling-mode-stop (APMS) bit is set, operation stops and BUSY goes to 0 as soon as a match is detected. Otherwise, BUSY stays at ‘1’ and the periodic accesses continue until there is an abort or the QUADSPI is disabled (EN = 0). The data register (QUADSPI_DR) contains the latest received status bytes (the FIFO is deactivated). The content of the data register is not affected by the masking used in the matching logic. The FTF status bit is set as soon as a new reading of the status is complete, and FTF is cleared as soon as the data is read. 15.3.7 QUADSPI memory-mapped mode When configured in memory-mapped mode, the external SPI device is seen as an internal memory. It is forbidden to access QUADSPI Flash bank area before having properly configured and enabled the QUADSPI peripheral. No more than 256MB can addressed even if the Flash memory capacity is larger. If an access is made to an address outside of the range defined by FSIZE but still within the 256MB range, then a bus error is given. The effect of this error depends on the bus master that attempted the access: • If it is the Cortex® CPU, bus fault exception is generated when enabled (or a hard fault exception when bus fault is disabled) • If it is a DMA, a DMA transfer error is generated and the corresponding DMA channel is automatically disabled. Byte, halfword, and word access types are all supported. Support for execute in place (XIP) operation is implemented, where the QUADSPI anticipates the next access and load in advance the byte at the following address. If the subsequent access is indeed made at a continuous address, the access will be completed faster since the value is already prefetched. 352/1600 RM0394 Rev 4 RM0394 Quad-SPI interface (QUADSPI) By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with nCS maintained low, even if no access to the Flash memory occurs for a long time. Since Flash memories tend to consume more when nCS is held low, the application might want to activate the timeout counter (TCEN = 1, bit 3 of QUADSPI_CR) so that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without any access since when the FIFO becomes full with prefetch data. BUSY goes high as soon as the first memory-mapped access occurs. Because of the prefetch operations, BUSY does not fall until there is a timeout, there is an abort, or the peripheral is disabled. 15.3.8 QUADSPI Flash memory configuration The device configuration register (QUADSPI_DCR) can be used to specify the characteristics of the external SPI Flash memory. The FSIZE[4:0] field defines the size of external memory using the following formula: Number of bytes in Flash memory = 2[FSIZE+1] FSIZE+1 is effectively the number of address bits required to address the Flash memory. The Flash memory capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB. If DFM = 1, FSIZE indicates the total capacity of the two Flash memories together. When the QUADSPI executes two commands, one immediately after the other, it raises the chip select signal (nCS) high between the two commands for only one CLK cycle by default. If the Flash memory requires more time between commands, the chip select high time (CSHT) field can be used to specify the minimum number of CLK cycles (up to 8) that nCS must remain high. The clock mode (CKMODE) bit indicates the CLK signal logic level in between commands (when nCS = 1). 15.3.9 QUADSPI delayed data sampling By default, the QUADSPI samples the data driven by the Flash memory one half of a CLK cycle after the Flash memory drives the signal. In case of external signal delays, it may be beneficial to sample the data later. Using the SSHIFT bit (bit 4 of QUADSPI_CR), the sampling of the data can be shifted by half of a CLK cycle. Clock shifting is not supported in DDR mode: the SSHIFT bit must be clear when DDRM bit is set. 15.3.10 QUADSPI configuration The QUADSPI configuration is done in two phases: • QUADSPI IP configuration • QUADSPI Flash memory configuration Once configured and enabled, the QUADSPI can be used in one of its three operating modes: indirect mode, status-polling mode, or memory-mapped mode. QUADSPI IP configuration RM0394 Rev 4 353/1600 372 Quad-SPI interface (QUADSPI) RM0394 The QUADSPI IP is configured using the QUADSPI_CR. The user shall configure the clock prescaler division factor and the sample shifting settings for the incoming data. DDR mode can be set through the DDRM bit. Once enabled, the address and the alternate bytes are sent on both clock edges and the data are sent/received on both clock edges. Regardless of the DDRM bit setting, instructions are always sent in SDR mode. The DMA requests are enabled setting the DMAEN bit. In case of interrupt usage, their respective enable bit can be also set during this phase. FIFO level for either DMA request generation or interrupt generation is programmed in the FTHRES bits. If timeout counter is needed, the TCEN bit can be set and the timeout value programmed in the QUADSPI_LPTR register. Dual-flash mode can be activated by setting DFM to 1. QUADSPI Flash memory configuration The parameters related to the targeted external Flash memory are configured through the QUADSPI_DCR register.The user shall program the Flash memory size in the FSIZE bits, the Chip Select minimum high time in the CSHT bits, and the functional mode (Mode 0 or Mode 3) in the MODE bit. 15.3.11 QUADSPI usage The operating mode is selected using FMODE[1:0] (QUADSPI_CCR[27:26]). Indirect mode procedure When FMODE is programmed to 00, indirect write mode is selected and data can be sent to the Flash memory. With FMODE = 01, indirect read mode is selected where data can be read from the Flash memory. When the QUADSPI is used in indirect mode, the frames are constructed in the following way: 1. 354/1600 Specify a number of data bytes to read or write in the QUADSPI_DLR. 2. Specify the frame format, mode and instruction code in the QUADSPI_CCR. 3. Specify optional alternate byte to be sent right after the address phase in the QUADSPI_ABR. 4. Specify the operating mode in the QUADSPI_CR. If FMODE = 00 (indirect write mode) and DMAEN = 1, then QUADSPI_AR should be specified before QUADSPI_CR, because otherwise QUADSPI_DR might be written by the DMA before QUADSPI_AR is updated (if the DMA controller has already been enabled) 5. Specify the targeted address in the QUADSPI_AR. 6. Read/Write the data from/to the FIFO through the QUADSPI_DR. RM0394 Rev 4 RM0394 Quad-SPI interface (QUADSPI) When writing the control register (QUADSPI_CR) the user specifies the following settings: • The enable bit (EN) set to ‘1’ • The DMA enable bit (DMAEN) for transferring data to/from RAM • Timeout counter enable bit (TCEN) • Sample shift setting (SSHIFT) • FIFO threshold level (FTRHES) to indicate when the FTF flag should be set • Interrupt enables • Automatic polling mode parameters: match mode and stop mode (valid when FMODE = 11) • Clock prescaler When writing the communication configuration register (QUADSPI_CCR) the user specifies the following parameters: • The instruction byte through the INSTRUCTION bits • The way the instruction has to be sent through the IMODE bits (1/2/4 lines) • The way the address has to be sent through the ADMODE bits (None/1/2/4 lines) • The address size (8/16/24/32-bit) through the ADSIZE bits • The way the alternate bytes have to be sent through the ABMODE (None/1/2/4 lines) • The alternate bytes number (1/2/3/4) through the ABSIZE bits • The presence or not of dummy bytes through the DBMODE bit • The number of dummy bytes through the DCYC bits • The way the data have to be sent/received (None/1/2/4 lines) through the DMODE bits If neither the address register (QUADSPI_AR) nor the data register (QUADSPI_DR) need to be updated for a particular command, then the command sequence starts as soon as QUADSPI_CCR is written. This is the case when both ADMODE and DMODE are 00, or if just ADMODE = 00 when in indirect read mode (FMODE = 01). When an address is required (ADMODE is not 00) and the data register does not need to be written (when FMODE = 01 or DMODE = 00), the command sequence starts as soon as the address is updated with a write to QUADSPI_AR. In case of data transmission (FMODE = 00 and DMODE! = 00), the communication start is triggered by a write in the FIFO through QUADSPI_DR. Status flag polling mode The status flag polling mode is enabled setting the FMODE field (QUADSPI_CCR[27:26]) to 10. In this mode, the programmed frame will be sent and the data retrieved periodically. The maximum amount of data read in each frame is 4 bytes. If more data is requested in QUADSPI_DLR, it will be ignored and only 4 bytes will be read. The periodicity is specified in the QUADSPI_PISR register. Once the status data has been retrieved, it can internally be processed i order to: • set the status match flag and generate an interrupt if enabled • stop automatically the periodic retrieving of the status bytes The received value can be masked with the value stored in the QUADSPI_PSMKR and ORed or ANDed with the value stored in the QUADSPI_PSMAR. RM0394 Rev 4 355/1600 372 Quad-SPI interface (QUADSPI) RM0394 In case of match, the status match flag is set and an interrupt is generated if enabled, and the QUADSPI can be automatically stopped if the AMPS bit is set. In any case, the latest retrieved value is available in the QUADSPI_DR. Memory-mapped mode In memory-mapped mode, the external Flash memory is seen as internal memory but with some latency during accesses. Only read operations are allowed to the external Flash memory in this mode. Memory-mapped mode is entered by setting the FMODE to 11 in the QUADSPI_CCR register. The programmed instruction and frame is sent when a master is accessing the memory mapped space. The FIFO is used as a prefetch buffer to anticipate linear reads. Any access to QUADSPI_DR in this mode returns zero. The data length register (QUADSPI_DLR) has no meaning in memory-mapped mode. 15.3.12 Sending the instruction only once Some Flash memories (e.g. Winbound) might provide a mode where an instruction must be sent only with the first command sequence, while subsequent commands start directly with the address. One can take advantage of such a feature using the SIOO bit (QUADSPI_CCR[28]). SIOO is valid for all functional modes (indirect, automatic polling, and memory-mapped). If the SIOO bit is set, the instruction is sent only for the first command following a write to QUADSPI_CCR. Subsequent command sequences skip the instruction phase, until there is a write to QUADSPI_CCR. SIOO has no effect when IMODE = 00 (no instruction). 15.3.13 QUADSPI error management An error can be generated in the following case: 356/1600 • In indirect mode or status flag polling mode when a wrong address has been programmed in the QUADSPI_AR (according to the Flash memory size defined by FSIZE[4:0] in the QUADSPI_DCR): this will set the TEF and an interrupt is generated if enabled. • Also in indirect mode, if the address plus the data length exceeds the Flash memory size, TEF will be set as soon as the access is triggered. • In memory-mapped mode, when an out of range access is done by a master or when the QUADSPI is disabled: this will generate a bus error as a response to the faulty bus master request. • When a master is accessing the memory mapped space while the memory mapped mode is disabled: this will generate a bus error as a response to the faulty bus master request. RM0394 Rev 4 RM0394 15.3.14 Quad-SPI interface (QUADSPI) QUADSPI busy bit and abort functionality Once the QUADSPI starts an operation with the Flash memory, the BUSY bit is automatically set in the QUADSPI_SR. In indirect mode, the BUSY bit is reset once the QUADSPI has completed the requested command sequence and the FIFO is empty. In automatic-polling mode, BUSY goes low only after the last periodic access is complete, due to a match when APMS = 1, or due to an abort. After the first access in memory-mapped mode, BUSY goes low only on a timeout event or on an abort. Any operation can be aborted by setting the ABORT bit in the QUADSPI_CR. Once the abort is completed, the BUSY bit and the ABORT bit are automatically reset, and the FIFO is flushed. Note: Some Flash memories might misbehave if a write operation to a status registers is aborted. 15.3.15 nCS behavior By default, nCS is high, deselecting the external Flash memory. nCS falls before an operation begins and rises as soon as it finishes. When CKMODE = 0 (“mode0”, where CLK stays low when no operation is in progress) nCS falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final rising CLK edge, as shown in Figure 35. Figure 35. nCS when CKMODE = 0 (T = CLK period) 7 7 Q&6 6&/. 069 When CKMODE=1 (“mode3”, where CLK goes high when no operation is in progress) and DDRM=0 (SDR mode), nCS still falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final rising CLK edge, as shown in Figure 36. Figure 36. nCS when CKMODE = 1 in SDR mode (T = CLK period) 7 7 Q&6 6&/. 069 RM0394 Rev 4 357/1600 372 Quad-SPI interface (QUADSPI) RM0394 When CKMODE = 1 (“mode3”) and DDRM = 1 (DDR mode), nCS falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final active rising CLK edge, as shown in Figure 37. Because DDR operations must finish with a falling edge, CLK is low when nCS rises, and CLK rises back up one half of a CLK cycle afterwards. Figure 37. nCS when CKMODE = 1 in DDR mode (T = CLK period) 7 7 7 Q&6 6&/. 069 When the FIFO stays full in a read operation or if the FIFO stays empty in a write operation, the operation stalls and CLK stays low until firmware services the FIFO. If an abort occurs when an operation is stalled, nCS rises just after the abort is requested and then CLK rises one half of a CLK cycle later, as shown in Figure 38. Figure 38. nCS when CKMODE = 1 with an abort (T = CLK period) 7 &ORFNVWDOOHG 7 Q&6 6&/. $ERUW 069 When not in dual-flash mode (DFM = 0), only FLASH 1 is accessed and thus the BK2_nCS stays high. In dual-flash mode, BK2_nCS behaves exactly the same as BK1_nCS. Thus, if there is a FLASH 2 and if the application always stays in dual-flash mode, then FLASH 2 may use BK1_nCS and the pin outputting BK2_nCS can be used for other functions. 358/1600 RM0394 Rev 4 RM0394 15.4 Quad-SPI interface (QUADSPI) QUADSPI interrupts An interrupt can be produced on the following events: • Timeout • Status match • FIFO threshold • Transfer complete • Transfer error Separate interrupt enable bits are available for flexibility. Table 52. QUADSPI interrupt requests Interrupt event Event flag Enable control bit Timeout TOF TOIE Status match SMF SMIE FIFO threshold FTF FTIE Transfer complete TCF TCIE Transfer error TEF TEIE RM0394 Rev 4 359/1600 372 Quad-SPI interface (QUADSPI) RM0394 15.5 QUADSPI registers 15.5.1 QUADSPI control register (QUADSPI_CR) Address offset: 0x0000 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 PRESCALER[7:0] 23 22 21 20 19 18 17 16 PMM APMS Res. TOIE SMIE FTIE TCIE TEIE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. FSEL DFM Res. SSHIFT TCEN rw rw rw rw FTHRES[3:0] rw rw rw rw DMAEN ABORT rw rw EN rw Bits 31:24 PRESCALER[7:0]: Clock prescaler This field defines the scaler factor for generating CLK based on the AHB clock (value+1). 0: FCLK = FAHB, AHB clock used directly as QUADSPI CLK (prescaler bypassed) 1: FCLK = FAHB/2 2: FCLK = FAHB/3 ... 255: FCLK = FAHB/256 For odd clock division factors, CLK’s duty cycle is not 50%. The clock signal remains low one cycle longer than it stays high. This field can be modified only when BUSY = 0. Bit 23 PMM: Polling match mode This bit indicates which method should be used for determining a “match” during automatic polling mode. 0: AND match mode. SMF is set if all the unmasked bits received from the Flash memory match the corresponding bits in the match register. 1: OR match mode. SMF is set if any one of the unmasked bits received from the Flash memory matches its corresponding bit in the match register. This bit can be modified only when BUSY = 0. Bit 22 APMS: Automatic poll mode stop This bit determines if automatic polling is stopped after a match. 0: Automatic polling mode is stopped only by abort or by disabling the QUADSPI. 1: Automatic polling mode stops as soon as there is a match. This bit can be modified only when BUSY = 0. Bit 21 Reserved, must be kept at reset value. Bit 20 TOIE: TimeOut interrupt enable This bit enables the TimeOut interrupt. 0: Interrupt disable 1: Interrupt enabled Bit 19 SMIE: Status match interrupt enable This bit enables the status match interrupt. 0: Interrupt disable 1: Interrupt enabled 360/1600 RM0394 Rev 4 RM0394 Quad-SPI interface (QUADSPI) Bit 18 FTIE: FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 17 TCIE: Transfer complete interrupt enable This bit enables the transfer complete interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 16 TEIE: Transfer error interrupt enable This bit enables the transfer error interrupt. 0: Interrupt disable 1: Interrupt enabled Bits 15:12 Reserved, must be kept at reset value. Bits 11:8 FTHRES[3:0]: FIFO threshold level Defines, in indirect mode, the threshold number of bytes in the FIFO that will cause the FIFO threshold flag (FTF, QUADSPI_SR[2]) to be set. In indirect write mode (FMODE = 00): 0: FTF is set if there are 1 or more free bytes available to be written to in the FIFO 1: FTF is set if there are 2 or more free bytes available to be written to in the FIFO ... 15: FTF is set if there are 16 free bytes available to be written to in the FIFO In indirect read mode (FMODE = 01): 0: FTF is set if there are 1 or more valid bytes that can be read from the FIFO 1: FTF is set if there are 2 or more valid bytes that can be read from the FIFO ... 15: FTF is set if there are 16 valid bytes that can be read from the FIFO If DMAEN = 1, then the DMA controller for the corresponding channel must be disabled before changing the FTHRES value. Bit 7 FSEL: Flash memory selection This bit selects the Flash memory to be addressed in single flash mode (when DFM = 0). 0: FLASH 1 selected 1: FLASH 2 selected This bit can be modified only when BUSY = 0. This bit is ignored when DFM = 1. Bit 6 DFM: Dual-flash mode This bit activates dual-flash mode, where two external Flash memories are used simultaneously to double throughput and capacity. 0: Dual-flash mode disabled 1: Dual-flash mode enabled This bit can be modified only when BUSY = 0. Bit 5 Reserved, must be kept at reset value. RM0394 Rev 4 361/1600 372 Quad-SPI interface (QUADSPI) RM0394 Bit 4 SSHIFT: Sample shift By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the Flash memory. This bit allows the data is to be sampled later in order to account for external signal delays. 0: No shift 1: 1/2 cycle shift Firmware must assure that SSHIFT = 0 when in DDR mode (when DDRM = 1). This field can be modified only when BUSY = 0. Bit 3 TCEN: Timeout counter enable This bit is valid only when memory-mapped mode (FMODE = 11) is selected. Activating this bit causes the chip select (nCS) to be released (and thus reduces consumption) if there has not been an access after a certain amount of time, where this time is defined by TIMEOUT[15:0] (QUADSPI_LPTR). Enable the timeout counter. By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with nCS maintained low, even if no access to the Flash memory occurs for a long time. Since Flash memories tend to consume more when nCS is held low, the application might want to activate the timeout counter (TCEN = 1, bit 3 of QUADSPI_CR) so that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without an access since when the FIFO becomes full with prefetch data. 0: Timeout counter is disabled, and thus the chip select (nCS) remains active indefinitely after an access in memory-mapped mode. 1: Timeout counter is enabled, and thus the chip select is released in memory-mapped mode after TIMEOUT[15:0] cycles of Flash memory inactivity. This bit can be modified only when BUSY = 0. Bit 2 DMAEN: DMA enable In indirect mode, DMA can be used to input or output data via the QUADSPI_DR register. DMA transfers are initiated when the FIFO threshold flag, FTF, is set. 0: DMA is disabled for indirect mode 1: DMA is enabled for indirect mode Bit 1 ABORT: Abort request This bit aborts the on-going command sequence. It is automatically reset once the abort is complete. This bit stops the current transfer. In polling mode or memory-mapped mode, this bit also reset the APM bit or the DM bit. 0: No abort requested 1: Abort requested Bit 0 EN: Enable Enable the QUADSPI. 0: QUADSPI is disabled 1: QUADSPI is enabled 362/1600 RM0394 Rev 4 RM0394 Quad-SPI interface (QUADSPI) 15.5.2 QUADSPI device configuration register (QUADSPI_DCR) Address offset: 0x0004 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. Res. Res. CSHT[2:0] rw rw Res. Res. rw Res. 20 19 18 17 16 rw FSIZE[4:0] rw rw rw rw 4 3 2 1 0 Res. CK MODE Res. Res. Res. rw Bits 31:21 Reserved, must be kept at reset value. Bits 20:16 FSIZE[4:0]: Flash memory size This field defines the size of external memory using the following formula: Number of bytes in Flash memory = 2[FSIZE+1] FSIZE+1 is effectively the number of address bits required to address the Flash memory. The Flash memory capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB. If DFM = 1, FSIZE indicates the total capacity of the two Flash memories together. This field can be modified only when BUSY = 0. Bits 15:11 Reserved, must be kept at reset value. Bits 10:8 CSHT[2:0]: Chip select high time CSHT+1 defines the minimum number of CLK cycles which the chip select (nCS) must remain high between commands issued to the Flash memory. 0: nCS stays high for at least 1 cycle between Flash memory commands 1: nCS stays high for at least 2 cycles between Flash memory commands ... 7: nCS stays high for at least 8 cycles between Flash memory commands This field can be modified only when BUSY = 0. Bits 7:1 Reserved, must be kept at reset value. Bit 0 CKMODE: Mode 0 / mode 3 This bit indicates the level that CLK takes between commands (when nCS = 1). 0: CLK must stay low while nCS is high (chip select released). This is referred to as mode 0. 1: CLK must stay high while nCS is high (chip select released). This is referred to as mode 3. This field can be modified only when BUSY = 0. RM0394 Rev 4 363/1600 372 Quad-SPI interface (QUADSPI) 15.5.3 RM0394 QUADSPI status register (QUADSPI_SR) Address offset: 0x0008 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. BUSY TOF SMF FTF TCF TEF r r r r r r FLEVEL[4:0] r r r r r Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 FLEVEL[4:0]: FIFO level This field gives the number of valid bytes which are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 16 when it is full. In memory-mapped mode and in automatic status polling mode, FLEVEL is zero. Bits 7:6 Reserved, must be kept at reset value. Bit 5 BUSY: Busy This bit is set when an operation is on going. This bit clears automatically when the operation with the Flash memory is finished and the FIFO is empty. Bit 4 TOF: Timeout flag This bit is set when timeout occurs. It is cleared by writing 1 to CTOF. Bit 3 SMF: Status match flag This bit is set in automatic polling mode when the unmasked received data matches the corresponding bits in the match register (QUADSPI_PSMAR). It is cleared by writing 1 to CSMF. Bit 2 FTF: FIFO threshold flag In indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after reads from the Flash memory are complete. It is cleared automatically as soon as threshold condition is no longer true. In automatic polling mode this bit is set every time the status register is read, and the bit is cleared when the data register is read. Bit 1 TCF: Transfer complete flag This bit is set in indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF. Bit 0 TEF: Transfer error flag This bit is set in indirect mode when an invalid address is being accessed in indirect mode. It is cleared by writing 1 to CTEF. 364/1600 RM0394 Rev 4 RM0394 Quad-SPI interface (QUADSPI) 15.5.4 QUADSPI flag clear register (QUADSPI_FCR) Address offset: 0x000C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTOF CSMF Res. CTCF CTEF w w w w Bits 31:5 Reserved, must be kept at reset value. Bit 4 CTOF: Clear timeout flag Writing 1 clears the TOF flag in the QUADSPI_SR register Bit 3 CSMF: Clear status match flag Writing 1 clears the SMF flag in the QUADSPI_SR register Bit 2 Reserved, must be kept at reset value. Bit 1 CTCF: Clear transfer complete flag Writing 1 clears the TCF flag in the QUADSPI_SR register Bit 0 CTEF: Clear transfer error flag Writing 1 clears the TEF flag in the QUADSPI_SR register 15.5.5 QUADSPI data length register (QUADSPI_DLR) Address offset: 0x0010 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DL[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DL[15:0] rw rw rw rw rw rw rw rw rw RM0394 Rev 4 365/1600 372 Quad-SPI interface (QUADSPI) RM0394 Bits 31:0 DL[31:0]: Data length Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode. All 1s in indirect mode means undefined length, where QUADSPI will continue until the end of memory, as defined by FSIZE. 0x0000_0000: 1 byte is to be transferred 0x0000_0001: 2 bytes are to be transferred 0x0000_0002: 3 bytes are to be transferred 0x0000_0003: 4 bytes are to be transferred ... 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred 0xFFFF_FFFF: undefined length -- all bytes until the end of Flash memory (as defined by FSIZE) are to be transferred. Continue reading indefinitely if FSIZE = 0x1F. DL[0] is stuck at ‘1’ in dual-flash mode (DFM = 1) even when ‘0’ is written to this bit, thus assuring that each access transfers an even number of bytes. This field has no effect when in memory-mapped mode (FMODE = 10). This field can be written only when BUSY = 0. 15.5.6 QUADSPI communication configuration register (QUADSPI_CCR) Address offset: 0x0014 Reset value: 0x0000 0000 31 30 29 28 DDRM DHHC Res. SIOO 13 rw rw 15 14 ABMODE[1:0] rw rw 26 25 24 FMODE[1:0] DMODE[1:0] rw rw rw rw rw 12 11 10 9 8 ADSIZE[1:0] rw 27 rw ADMODE[1:0] rw rw 23 22 21 Res. 7 rw 19 18 DCYC[4:0] 17 ABSIZE[1:0] rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw rw INSTRUCTION[7:0] rw rw rw rw rw Bit 31 DDRM: Double data rate mode This bit sets the DDR mode for the address, alternate byte and data phase: 0: DDR Mode disabled 1: DDR Mode enabled This field can be written only when BUSY = 0. Bit 30 DHHC: DDR hold Delay the data output by 1/4 of the QUADSPI output clock cycle in DDR mode: 0: Delay the data output using analog delay 1: Delay the data output by 1/4 of a QUADSPI output clock cycle. This feature is only active in DDR mode. This field can be written only when BUSY = 0. Bit 29 Reserved, must be kept at reset value. 366/1600 16 rw IMODE[1:0] rw 20 RM0394 Rev 4 RM0394 Quad-SPI interface (QUADSPI) Bit 28 SIOO: Send instruction only once mode See Section 15.3.12: Sending the instruction only once on page 356. This bit has no effect when IMODE = 00. 0: Send instruction on every transaction 1: Send instruction only for the first command This field can be written only when BUSY = 0. Bits 27:26 FMODE[1:0]: Functional mode This field defines the QUADSPI functional mode of operation. 00: Indirect write mode 01: Indirect read mode 10: Automatic polling mode 11: Memory-mapped mode If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE value. This field can be written only when BUSY = 0. Bits 25:24 DMODE[1:0]: Data mode This field defines the data phase’s mode of operation: 00: No data 01: Data on a single line 10: Data on two lines 11: Data on four lines This field also determines the dummy phase mode of operation. This field can be written only when BUSY = 0. Bit 23 Reserved, must be kept at reset value. Bits 22:18 DCYC[4:0]: Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DDR modes, it specifies a number of CLK cycles (0-31). This field can be written only when BUSY = 0. Bits 17:16 ABSIZE[1:0]: Alternate bytes size This bit defines alternate bytes size: 00: 8-bit alternate byte 01: 16-bit alternate bytes 10: 24-bit alternate bytes 11: 32-bit alternate bytes This field can be written only when BUSY = 0. Bits 15:14 ABMODE[1:0]: Alternate bytes mode This field defines the alternate-bytes phase mode of operation: 00: No alternate bytes 01: Alternate bytes on a single line 10: Alternate bytes on two lines 11: Alternate bytes on four lines This field can be written only when BUSY = 0. RM0394 Rev 4 367/1600 372 Quad-SPI interface (QUADSPI) RM0394 Bits 13:12 ADSIZE[1:0]: Address size This bit defines address size: 00: 8-bit address 01: 16-bit address 10: 24-bit address 11: 32-bit address This field can be written only when BUSY = 0. Bits 11:10 ADMODE[1:0]: Address mode This field defines the address phase mode of operation: 00: No address 01: Address on a single line 10: Address on two lines 11: Address on four lines This field can be written only when BUSY = 0. Bits 9:8 IMODE[1:0]: Instruction mode This field defines the instruction phase mode of operation: 00: No instruction 01: Instruction on a single line 10: Instruction on two lines 11: Instruction on four lines This field can be written only when BUSY = 0. Bits 7:0 INSTRUCTION[7:0]: Instruction Instruction to be send to the external SPI device. This field can be written only when BUSY = 0. 15.5.7 QUADSPI address register (QUADSPI_AR) Address offset: 0x0018 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDRESS[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ADDRESS[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 ADDRESS[31:0]: Address Address to be send to the external Flash memory Writes to this field are ignored when BUSY = 0 or when FMODE = 11 (memory-mapped mode). In dual flash mode, ADDRESS[0] is automatically stuck to ‘0’ as the address should always be even 368/1600 RM0394 Rev 4 RM0394 Quad-SPI interface (QUADSPI) 15.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR) Address offset: 0x001C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ALTERNATE[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ALTERNATE[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 ALTERNATE[31:0]: Alternate Bytes Optional data to be send to the external SPI device right after the address. This field can be written only when BUSY = 0. 15.5.9 QUADSPI data register (QUADSPI_DR) Address offset: 0x0020 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DATA[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 DATA[31:0]: Data Data to be sent/received to/from the external SPI device. In indirect write mode, data written to this register is stored on the FIFO before it is sent to the Flash memory during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In indirect read mode, reading this register gives (via the FIFO) the data which was received from the Flash memory. If the FIFO does not have as many bytes as requested by the read operation and if BUSY=1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In automatic polling mode, this register contains the last data read from the Flash memory (without masking). Word, halfword, and byte accesses to this register are supported. In indirect write mode, a byte write adds 1 byte to the FIFO, a halfword write 2, and a word write 4. Similarly, in indirect read mode, a byte read removes 1 byte from the FIFO, a halfword read 2, and a word read 4. Accesses in indirect mode must be aligned to the bottom of this register: a byte read must read DATA[7:0] and a halfword read must read DATA[15:0]. RM0394 Rev 4 369/1600 372 Quad-SPI interface (QUADSPI) 15.5.10 RM0394 QUADSPI polling status mask register (QUADSPI _PSMKR) Address offset: 0x0024 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MASK[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MASK[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 MASK[31:0]: Status mask Mask to be applied to the status bytes received in polling mode. For bit n: 0: Bit n of the data received in automatic polling mode is masked and its value is not considered in the matching logic 1: Bit n of the data received in automatic polling mode is unmasked and its value is considered in the matching logic This field can be written only when BUSY = 0. 15.5.11 QUADSPI polling status match register (QUADSPI _PSMAR) Address offset: 0x0028 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MATCH[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw MATCH[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 MATCH[31:0]: Status match Value to be compared with the masked status register to get a match. This field can be written only when BUSY = 0. 370/1600 RM0394 Rev 4 RM0394 Quad-SPI interface (QUADSPI) 15.5.12 QUADSPI polling interval register (QUADSPI _PIR) Address offset: 0x002C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw INTERVAL[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 INTERVAL[15:0]: Polling interval Number of CLK cycles between to read during automatic polling phases. This field can be written only when BUSY = 0. 15.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR) Address offset: 0x0030 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw TIMEOUT[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 TIMEOUT[15:0]: Timeout period After each access in memory-mapped mode, the QUADSPI prefetches the subsequent bytes and holds these bytes in the FIFO. This field indicates how many CLK cycles the QUADSPI waits after the FIFO becomes full until it raises nCS, putting the Flash memory in a lower-consumption state. This field can be written only when BUSY = 0. RM0394 Rev 4 371/1600 372 Quad-SPI interface (QUADSPI) 15.5.14 RM0394 QUADSPI register map 0x001C Reset value 0 0 0 0 0 0 0 0 0 0 0x0020 0x0024 0 0 0 DCYC[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ABORT EN Res. TEF Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTRUCTION[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QUADSPI_PIR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MATCH[31:0] 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 INTERVAL[15:0] 0 Reset value 0 0 0 RM0394 Rev 4 0 0 TIMEOUT[15:0] 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 67 for the register boundary addresses. 372/1600 0 MASK[31:0] Reset value QUADSPI_ LPTR CKMODE TCF 0 DATA[31:0] Reset value 0x0030 TCEN 0 ALTERNATE[31:0] QUADSPI_ PSMAR 0x002C DMAEN FTF 0 ADDRESS[31:0] 0 Res. 0x0028 0 QUADSPI_ PSMKR Reset value Res. SMF 0 CTEF 0 QUADSPI_DR Reset value Res. Res. 0 CTCF 0 IMODE[1:0] 0 QUADSPI_ABR Reset value SSHIFT Res. Res. 0 CSMF 0 TOF 0 CTOF 0 BUSY 0 Res. 0 ADMODE[1:0] 0 QUADSPI_AR 0x0018 0 0 Res. 0 ADSIZE[1:0] 0 0 ABMODE[1:0] 0 0 ABSIZE[1:0] 0 0 Res. 0 0 DMODE[1:0] DHHC Reset value 0 FMODE[1:0] QUADSPI_CCR 0 Res. 0 SIOO 0 0x0014 0 DL[31:0] Reset value DDRM QUADSPI_DLR 0 0 Reset value 0x0010 0 0 Res. DFM Res. Res. FSEL 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. QUADSPI_FCR 0 FLEVEL[5:0] Reset value 0x000C Res. 0 Res. 0 CSHT Res. 0 0 Res. 0 0 Res. 0 0 Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. FSIZE[4:0] FTHRES [3:0] Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. TEIE Res. Res. Res. 0 Res. Res. Res. QUADSPI_SR Res. Reset value 0x0008 0 Res. QUADSPI_DCR 0x0004 0 Res. 0 FTIE 0 TCIE 0 Res. 0 SMIE 0 Res. 0 Res. 0 Res. 0 TOIE 0 PRESCALER[7:0] Res. 0 QUADSPI_CR 0x0000 Res. PMM APMS Reset value Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 53. QUADSPI register map and reset values Register name 0 0 RM0394 Analog-to-digital converters (ADC) 16 Analog-to-digital converters (ADC) 16.1 Introduction This section describes the implementation of up to 2 ADCs: • ADC1 and ADC2 are tightly coupled and can operate in dual mode (ADC1 is master). Each ADC consists of a 12-bit successive approximation analog-to-digital converter. Each ADC has up to 19 multiplexed channels. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register. The ADCs are mapped on the AHB bus to allow fast data handling. The analog watchdog features allow the application to detect if the input voltage goes outside the user-defined high or low thresholds. A built-in hardware oversampler allows to improve analog performances while off-loading the related computational burden from the CPU. An efficient low-power mode is implemented to allow very low consumption at low frequency. RM0394 Rev 4 373/1600 485 Analog-to-digital converters (ADC) 16.2 RM0394 ADC main features • High-performance features – Up to 2 ADCs which can operate in dual mode: ADC1 is connected to 16 external channels + 3 internal channels ADC2 is connected to 16 external channels – 12, 10, 8 or 6-bit configurable resolution – ADC conversion time: Fast channels: 0.188 µs for 12-bit resolution (5.33 Ms/s) Slow channels: 0.238 µs for 12-bit resolution (4.21 Ms/s) • 374/1600 – ADC conversion time is independent from the AHB bus clock frequency – Faster conversion time by lowering resolution: 0.16 µs for 10-bit resolution – Manage single-ended or differential inputs – AHB slave bus interface to allow fast data handling – Self-calibration – Channel-wise programmable sampling time – Up to four injected channels (analog inputs assignment to regular or injected channels is fully configurable) – Hardware assistant to prepare the context of the injected channels to allow fast context switching – Data alignment with in-built data coherency – Data can be managed by DMA for regular channel conversions – Data can be routed to DFSDM for post processing – 4 dedicated data registers for the injected channels Oversampler – 16-bit data register – Oversampling ratio adjustable from 2 to 256x – Programmable data shift up to 8-bit RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) • • • • • Low-power features – Speed adaptive low-power mode to reduce ADC consumption when operating at low frequency – Allows slow bus frequency application while keeping optimum ADC performance (0.188 µs conversion time for fast channels can be kept whatever the AHB bus clock frequency) – Provides automatic control to avoid ADC overrun in low AHB bus clock frequency application (auto-delayed mode) Several external analog input channel per ADC – Up to 5 fast channels from GPIO pads – Up to 11 slow channels from GPIO pads In addition, there are several internal dedicated channels – The internal reference voltage (VREFINT), connected to ADC1 – The internal temperature sensor (VTS), connected to ADC1 – The VBAT monitoring channel (VBAT/3), connected to ADC1 – DAC1 internal channels, connected to ADC1 Start-of-conversion can be initiated: – by software for both regular and injected conversions – by hardware triggers with configurable polarity (internal timers events or GPIO input events) for both regular and injected conversions Conversion modes – Each ADC can convert a single channel or can scan a sequence of channels – Single mode converts selected inputs once per trigger – Continuous mode converts selected inputs continuously – Discontinuous mode • Dual ADC mode for ADC1 and 2 • Interrupt generation at ADC ready, the end of sampling, the end of conversion (regular or injected), end of sequence conversion (regular or injected), analog watchdog 1, 2 or 3 or overrun events • 3 analog watchdogs per ADC • ADC input range: VREF– ≤ VIN ≤ VREF+ Figure 39 shows the block diagram of one ADC. 16.3 ADC implementation Table 54. Main ADC features References Dual mode DFSDM interface(1) SMPPLUS control(2) ADC1 ADC2(2) X(2) X X - - X 1. Available only on STM32L451xx/452xx/462xx. 2. Available only on STM32L412xx/422xx. RM0394 Rev 4 375/1600 485 Analog-to-digital converters (ADC) RM0394 16.4 ADC functional description 16.4.1 ADC block diagram Figure 39 shows the ADC block diagram and Table 56 gives the ADC pin description. Figure 39. ADC block diagram 95() WR9 $QDORJ6XSSO\ 9''$ 9WR9 $'&B645[ &217 VLQJOHFRQW 976 GDFBRXW 95(),17 9%$7 GDFBRXW $'&B,13>@ $'&B,11>@ 95() $'(1$'',6 $'&B-645[ -'$7$>@ -'$7$>@ -'$7$>@ -'$7$>@ ,54 VODYH PDVWHU PDVWHU '0$ $+% LQWHUIDFH '0$UHTXHVW %LDV 5HI $'&$/ VHOIFDOLEUDWLRQ 9,13>@ ,QSXW 9,1 9,11>@ VHOHFWLRQ VFDQFRQWURO DQDORJLQSXW FKDQQHOV 603[>@ VDPSOLQJWLPH ')6'0 '0$&)* '0$(1 2YHUVDPSOHU 6$5$'& 52960 &219(57(' '$7$ VWDUW 75296 2966>@ 6WDUW 6WRS &RQWURO $87'/< DXWRGHOD\HG &RUWH[ 0ZLWK )38 $'&,QWHUUXSW $+% 5'$7$>@ -$872 $5($'< (2603 (2& (26 295 -(26 -429) $:'[ 2965>@ 29502' RYHUUXQPRGH 6:WULJJHU $'673 VWRSFRQY -296( $/,*1 OHIWULJKW 5296( 5(6>@ ELWV 2YHUVDPSOLQJ RSWLRQV -2))6(7[>@ (;7 (;7 (;7 (;7 (;7 (;7 -2))6(7[B&+>@ KZ WULJJHU (;7(1>@ WULJJHUHQDEOH DQGHGJHVHOHFWLRQ (;7LPDSSHG DWSURGXFWOHYHO ',6&(1 ',6&18>@ $QDORJZDWFKGRJ 'LVFRQWLQXRXV PRGH $:' $:' $:' (;76(/>@ WULJJHUVHOHFWLRQ $:'B287 $:'B287 $:'B287 7,0(5V (75 - 6:WULJJHU $:'(1 -(;7 -(;7 -(;7 -(;7 -(;7 -(;7 -$:'(1 +: WULJJHU -(;7(1>@ WULJJHUHQDEOH DQGHGJHVHOHFWLRQ -(;7LPDSSHG DWSURGXFWOHYHO $:'6*/ -',6&(1 -',6&180>@ $:'&+>@ /7>@ +7>@ -40 ,QMFHG&RQWH[W $:'&+>@ 4XHXH0RGH /7>@ $:'&+>@ +7>@ -(;76(/>@ WULJJHUVHOHFWLRQ +7>@ /7>@ 06Y9 376/1600 RM0394 Rev 4 RM0394 16.4.2 Analog-to-digital converters (ADC) ADC pins and internal signals Table 55. ADC internal input/output signals Signal type Description Inputs Up to 16 external trigger inputs for the regular conversions (can be connected to on-chip timers). These inputs are shared between the ADC master and the ADC slave. JEXT[15:0] Inputs Up to 16 external trigger inputs for the injected conversions (can be connected to on-chip timers). These inputs are shared between the ADC master and the ADC slave. ADC_AWDx_OUT Output Internal analog watchdog output signal connected to on-chip timers. (x = Analog watchdog number 1,2,3) Internal signal name EXT[15:0] VTS Input Output voltage from internal temperature sensor dac_out1 Input DAC internal channel 1 VREFINT Input Output voltage from internal reference voltage dac_out2 Input DAC internal channel 2 VBAT Input supply External battery voltage supply Table 56. ADC input/output pins Pin name Signal type Comments VREF+ Input, analog reference positive The higher/positive reference voltage for the ADC, 1.62 V ≤ VREF+ ≤ VDDA VDDA Input, analog supply Analog power supply equal VDDA: 1.62 V ≤ VDDA ≤ 3.6 V VREF− Input, analog reference negative The lower/negative reference voltage for the ADC. VREF− is internally connected to VSSA VSSA Input, analog supply ground Ground for analog power supply. On device package which do not have a dedicated VSSA pin, VSSA is internally connected to VSS. VINP[18:0] Positive analog input channels for each ADC Connected either to external channels: ADCx_INPi or internal channels. VINN[18:0] Negative analog input channels for each ADC Connected to VREF− or external channels: ADCx_INNi and ADCx_INP[i+1] ADCx_INN[16:1] External analog input signals Up to 16 analog input channels (x = ADC number = 1 or 2): – 5 fast channels (ADCx_INN1 to INN5) – Up to 11 slow channels (ADCx_INN6 to INN16) ADCx_INP[16:1] External analog input signals Up to 16 analog input channels (x = ADC number = 1 or 2): – 5 fast channels (ADCx_INP1 to INP5) – Up to 11 slow channels (ADCx_INP6 to INP16) RM0394 Rev 4 377/1600 485 Analog-to-digital converters (ADC) 16.4.3 RM0394 Clocks Dual clock domain architecture The dual clock-domain architecture means that the ADC clock is independent from the AHB bus clock. The input clock is the same for the three ADCs and can be selected between two different clock sources (see Figure 40: ADC clock scheme): 1. The ADC clock can be a specific clock source. It can be derived from the following clock sources: – The system clock – PLLSAI1 (single ADC implementation) Refer to RCC Section for more information on how to generate ADC dedicated clock. To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be reset. 2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). In this mode, a programmable divider factor can be selected (/1, 2 or 4 according to bits CKMODE[1:0]). To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be different from “00”. Note: For option 2), a prescaling factor of 1 (CKMODE[1:0]=01) can be used only if the AHB prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register). Option 1) has the advantage of reaching the maximum ADC clock frequency whatever the AHB clock scheme selected. The ADC clock can eventually be divided by the following ratio: 1, 2, 4, 6, 8, 12, 16, 32, 64, 128, 256; using the prescaler configured with bits PRESC[3:0] in the ADCx_CCR register. Option 2) has the advantage of bypassing the clock domain resynchronizations. This can be useful when the ADC is triggered by a timer and if the application requires that the ADC is precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is added by the resynchronizations between the two clock domains). 378/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Figure 40. ADC clock scheme 5&& 5HVHWDQG FORFN FRQWUROOHU $'&DQG$'& +&/. $+%LQWHUIDFH %LWV&.02'(>@ RI$'&[B&&5 $QDORJ$'& PDVWHU RURU $'&B&. %LWV35(&>@ RI$'&[B&&5 2WKHUV $QDORJ$'& VODYH %LWV&.02'(>@ RI$'&[B&&5 06Y9 Clock ratio constraint between ADC clock and AHB clock There are generally no constraints to be respected for the ratio between the ADC clock and the AHB clock except if some injected channels are programmed. In this case, it is mandatory to respect the following ratio: • FHCLK >= FADC / 4 if the resolution of all channels are 12-bit or 10-bit • FHCLK >= FADC / 3 if there are some channels with resolutions equal to 8-bit (and none with lower resolutions) • FHCLK >= FADC / 2 if there are some channels with resolutions equal to 6-bit RM0394 Rev 4 379/1600 485 Analog-to-digital converters (ADC) 16.4.4 RM0394 ADC1/2 connectivity ADC1 and ADC2 are tightly coupled and share some external channels as described in the below figures. Figure 41. ADC1 connectivity 670/[[[[[[[[[[[[ 670/[[[[[[[[ ϭ s,13>@ s5(),17 s,11>@ 95()í s,13>@ s,11>@ s,13>@ s,11>@ s,13>@ s,11>@ s,13>@ s,11>@ s,13>@ s,11>@ s,13>@ s,11>@ s,13>@ s,11>@ s,13>@ s,11>@ s,13>@ s,11>@ s,13>@ s,11>@ s,13>@ s,11>@ s,13>@ s,11>@ s,13>@ s,11>@ s,13>@ s,11>@ $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 GDFBRXW 976 GDFBRXW s%$7 s,13>@ s,11>@ s,13>@ s,11>@ 95()í s,13>@ s,11>@ 95()í s,13>@ s,11>@ 95()í ŚĂŶŶĞůƐĞůĞĐƚŝŽŶ &ĂƐƚĐŚĂŶŶĞů &ĂƐƚĐŚĂŶŶĞů &ĂƐƚĐŚĂŶŶĞů &ĂƐƚĐŚĂŶŶĞů &ĂƐƚĐŚĂŶŶĞů &ĂƐƚĐŚĂŶŶĞů ^ůŽǁĐŚĂŶŶĞů s5() ^ůŽǁĐŚĂŶŶĞů s,13 ^ůŽǁĐŚĂŶŶĞů ^ůŽǁĐŚĂŶŶĞů s,11 ^Z $'& ^ůŽǁĐŚĂŶŶĞů 95()í ^ůŽǁĐŚĂŶŶĞů ^ůŽǁĐŚĂŶŶĞů ^ůŽǁĐŚĂŶŶĞů ^ůŽǁĐŚĂŶŶĞů ^ůŽǁĐŚĂŶŶĞů ^ůŽǁĐŚĂŶŶĞů ^ůŽǁĐŚĂŶŶĞů ^ůŽǁĐŚĂŶŶĞů 06Y9 380/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Figure 42. ADC2 connectivity 670/[[[[ $'& $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 $'&B,11 $'&B,13 9,13>@ 95()í 9,11>@ 95()í 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ $'&B,11 $'&B,13 $'&B,11 $'&B,13 95()í 95()í 95()í 95()í 95()í 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ 9,13>@ 9,11>@ &KDQQHOVHOHFWLRQ )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO )DVWFKDQQHO 6ORZFKDQQHO 95() 6ORZFKDQQHO 9,13 6ORZFKDQQHO 6ORZFKDQQHO 9,11 6$5 $'& 6ORZFKDQQHO 95()í 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 6ORZFKDQQHO 06Y9 RM0394 Rev 4 381/1600 485 Analog-to-digital converters (ADC) 16.4.5 RM0394 Slave AHB interface The ADCs implement an AHB slave port for control/status register and data access. The features of the AHB interface are listed below: • Word (32-bit) accesses • Single cycle response • Response to all read/write accesses to the registers with zero wait states. The AHB slave interface does not support split/retry requests, and never generates AHB errors. 16.4.6 ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) By default, the ADC is in Deep-power-down mode where its supply is internally switched off to reduce the leakage currents (the reset state of bit DEEPPWD is 1 in the ADC_CR register). To start ADC operations, it is first needed to exit Deep-power-down mode by setting bit DEEPPWD=0. Then, it is mandatory to enable the ADC internal voltage regulator by setting the bit ADVREGEN=1 into ADC_CR register. The software must wait for the startup time of the ADC voltage regulator (TADCVREG_STUP) before launching a calibration or enabling the ADC. This delay must be implemented by software. For the startup time of the ADC voltage regulator, refer to device datasheet for TADCVREG_STUP parameter. After ADC operations are complete, the ADC can be disabled (ADEN=0). It is possible to save power by also disabling the ADC voltage regulator. This is done by writing bit ADVREGEN=0. Then, to save more power by reducing the leakage currents, it is also possible to re-enter in ADC Deep-power-down mode by setting bit DEEPPWD=1 into ADC_CR register. This is particularly interesting before entering STOP mode. Note: Writing DEEPPWD=1 automatically disables the ADC voltage regulator and bit ADVREGEN is automatically cleared. When the internal voltage regulator is disabled (ADVREGEN=0), the internal analog calibration is kept. In ADC Deep-power-down mode (DEEPPWD=1), the internal analog calibration is lost and it is necessary to either relaunch a calibration or re-apply the calibration factor which was previously saved (refer to Section 16.4.8: Calibration (ADCAL, ADCALDIF, ADC_CALFACT)). 382/1600 RM0394 Rev 4 RM0394 16.4.7 Analog-to-digital converters (ADC) Single-ended and differential input channels Channels can be configured to be either single-ended input or differential input by writing into bits DIFSEL[15:1] in the ADC_DIFSEL register. This configuration must be written while the ADC is disabled (ADEN=0). Note that DIFSEL[18:16,0] are fixed to single ended channels and are always read as 0. In single-ended input mode, the analog voltage to be converted for channel “i” is the difference between the external voltage VINP[i] (positive input) and VREF− (negative input). In differential input mode, the analog voltage to be converted for channel “i” is the difference between the external voltage VINP[i] (positive input) and VINN[i] (negative input). When ADC is configured as differential mode, both inputs should be biased at (VREF+) / 2 voltage. The input signal are supposed to be differential (common mode voltage should be fixed). For a complete description of how the input channels are connected for each ADC, refer to Section 16.4.4: ADC1/2 connectivity. Caution: When configuring the channel “i” in differential input mode, its negative input voltage VINN[i] is connected to VINP[i+1]. As a consequence, channel “i+1” is no longer usable in singleended mode or in differential mode and must never be configured to be converted. Some channels are shared between ADC1/ADC2: this can make the channel on the other ADC unusable. Only exception is interleaved mode for ADC master and the slave. Note: ADC channels 0, 16, 17, 18 are forced to single-ended configuration (corresponding bits DIFSEL[i] is always zero), either because connected to a single-ended external analog input or connected to an internal channel. 16.4.8 Calibration (ADCAL, ADCALDIF, ADC_CALFACT) Each ADC provides an automatic calibration procedure which drives all the calibration sequence including the power-on/off sequence of the ADC. During the procedure, the ADC calculates a calibration factor which is 7-bit wide and which is applied internally to the ADC until the next ADC power-off. During the calibration procedure, the application must not use the ADC and must wait until calibration is complete. Calibration is preliminary to any ADC operation. It removes the offset error which may vary from chip to chip due to process or bandgap variation. The calibration factor to be applied for single-ended input conversions is different from the factor to be applied for differential input conversions: • Write ADCALDIF=0 before launching a calibration which will be applied for singleended input conversions. • Write ADCALDIF=1 before launching a calibration which will be applied for differential input conversions. The calibration is then initiated by software by setting bit ADCAL=1. Calibration can only be initiated when the ADC is disabled (when ADEN=0). ADCAL bit stays at 1 during all the calibration sequence. It is then cleared by hardware as soon the calibration completes. At this time, the associated calibration factor is stored internally in the analog ADC and also in the bits CALFACT_S[6:0] or CALFACT_D[6:0] of ADC_CALFACT register (depending on single-ended or differential input calibration) RM0394 Rev 4 383/1600 485 Analog-to-digital converters (ADC) RM0394 The internal analog calibration is kept if the ADC is disabled (ADEN=0). However, if the ADC is disabled for extended periods, then it is recommended that a new calibration cycle is run before re-enabling the ADC. The internal analog calibration is lost each time the power of the ADC is removed (example, when the product enters in STANDBY or VBAT mode). In this case, to avoid spending time recalibrating the ADC, it is possible to re-write the calibration factor into the ADC_CALFACT register without recalibrating, supposing that the software has previously saved the calibration factor delivered during the previous calibration. The calibration factor can be written if the ADC is enabled but not converting (ADEN=1 and ADSTART=0 and JADSTART=0). Then, at the next start of conversion, the calibration factor will automatically be injected into the analog ADC. This loading is transparent and does not add any cycle latency to the start of the conversion. It is recommended to recalibrate when VREF+ voltage changed more than 10%. Software procedure to calibrate the ADC 1. Ensure DEEPPWD=0, ADVREGEN=1 and that ADC voltage regulator startup time has elapsed. 2. Ensure that ADEN=0. 3. Select the input mode for this calibration by setting ADCALDIF=0 (single-ended input) or ADCALDIF=1 (differential input). 4. Set ADCAL=1. 5. Wait until ADCAL=0. 6. The calibration factor can be read from ADC_CALFACT register. Figure 43. ADC calibration $'&$/',) 6LQJOHHQGHGLQSXW'LIIHUHQWLDOLQSXW W&$% $'&$/ $'&6WDWH 2)) 6WDUWXS [ &$/)$&7B[>@ E\6: &DOLEUDWH E\+: 2)) &DOLEUDWLRQIDFWRU ,QGLFDWLYHWLPLQJV 06Y9 Software procedure to re-inject a calibration factor into the ADC 1. 384/1600 Ensure ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing). 2. Write CALFACT_S and CALFACT_D with the new calibration factors. 3. When a conversion is launched, the calibration factor will be injected into the analog ADC only if the internal analog calibration factor differs from the one stored in bits CALFACT_S for single-ended input channel or bits CALFACT_D for differential input channel. RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Figure 44. Updating the ADC calibration factor 5HDG\ QRWFRQYHUWLQJ $'&VWDWH &RQYHUWLQJFKDQQHO 6LQJOHHQGHG 5HDG\ &RQYHUWLQJFKDQQHO 6LQJOHHQGHG 8SGDWLQJFDOLEUDWLRQ ,QWHUQDO FDOLEUDWLRQIDFWRU>@ ) ) 6WDUWFRQYHUVLRQ KDUGZDUHRUVRIZDUH :5,7($'&B&$/)$&7 &$/)$&7B6>@ E\VZ ) E\KZ 06Y9 Converting single-ended and differential analog inputs with a single ADC If the ADC is supposed to convert both differential and single-ended inputs, two calibrations must be performed, one with ADCALDIF=0 and one with ADCALDIF=1. The procedure is the following: 1. Disable the ADC. 2. Calibrate the ADC in single-ended input mode (with ADCALDIF=0). This updates the register CALFACT_S[6:0]. 3. Calibrate the ADC in differential input modes (with ADCALDIF=1). This updates the register CALFACT_D[6:0]. 4. Enable the ADC, configure the channels and launch the conversions. Each time there is a switch from a single-ended to a differential inputs channel (and vice-versa), the calibration will automatically be injected into the analog ADC. Figure 45. Mixing single-ended and differential channels 7ULJJHUHYHQW $'&VWDWH 5'< &219&+ 5'< &219&+ 5'< &219&+ 5'< 6LQJOHHQGHG LQSXWVFKDQQHO ,QWHUQDO FDOLEUDWLRQIDFWRU>@ ) &$/)$&7B6>@ ) &$/)$&7B'>@ ) 'LIIHUHQWLDO LQSXWVFKDQQHO ) 'LIIHUHQWLDO LQSXWVFKDQQHO &219&+ 6LQJOHLQSXWV FKDQQHO ) 06Y9 RM0394 Rev 4 385/1600 485 Analog-to-digital converters (ADC) 16.4.9 RM0394 ADC on-off control (ADEN, ADDIS, ADRDY) First of all, follow the procedure explained in Section 16.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN)). Once DEEPPWD=0 and ADVREGEN=1, the ADC can be enabled and the ADC needs a stabilization time of tSTAB before it starts converting accurately, as shown in Figure 46. Two control bits enable or disable the ADC: • ADEN=1 enables the ADC. The flag ADRDY will be set once the ADC is ready for operation. • ADDIS=1 disables the ADC. ADEN and ADDIS are then automatically cleared by hardware as soon as the analog ADC is effectively disabled. Regular conversion can then start either by setting ADSTART=1 (refer to Section 16.4.18: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN,JEXTSEL, JEXTEN)) or when an external trigger event occurs, if triggers are enabled. Injected conversions start by setting JADSTART=1 or when an external injected trigger event occurs, if injected triggers are enabled. Software procedure to enable the ADC Caution: 1. Clear the ADRDY bit in the ADC_ISR register by writing ‘1’. 2. Set ADEN=1. 3. Wait until ADRDY=1 (ADRDY is set after the ADC startup time). This can be done using the associated interrupt (setting ADRDYIE=1). 4. Clear the ADRDY bit in the ADC_ISR register by writing ‘1’ (optional). ADEN bit cannot be set during ADCAL=1 and 4 ADC clock cycle after the ADCAL bit is cleared by hardware (end of the calibration). Software procedure to disable the ADC 386/1600 1. Check that both ADSTART=0 and JADSTART=0 to ensure that no conversion is ongoing. If required, stop any regular and injected conversion ongoing by setting ADSTP=1 and JADSTP=1 and then wait until ADSTP=0 and JADSTP=0. 2. Set ADDIS=1. 3. If required by the application, wait until ADEN=0, until the analog ADC is effectively disabled (ADDIS will automatically be reset once ADEN=0). RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Figure 46. Enabling / Disabling the ADC $'(1 W67$% $'5'< $'',6 $'& VWDWH E\6: 16.4.10 2)) 6WDUWXS 5'< &RQYHUWLQJ&+ E\+: 5'< 5(4 2) 2)) 06Y9 Constraints when writing the ADC control bits The software is allowed to write the RCC control bits to configure and enable the ADC clock (refer to RCC Section), the control bits DIFSEL in the ADC_DIFSEL register and the control bits ADCAL and ADEN in the ADC_CR register, only if the ADC is disabled (ADEN must be equal to 0). The software is then allowed to write the control bits ADSTART, JADSTART and ADDIS of the ADC_CR register only if the ADC is enabled and there is no pending request to disable the ADC (ADEN must be equal to 1 and ADDIS to 0). For all the other control bits of the ADC_CFGR, ADC_SMPRx, ADC_SQRy, ADC_JDRy, ADC_OFRy, ADC_OFCHRy and ADC_IER registers: • For control bits related to configuration of regular conversions, the software is allowed to write them only if the ADC is enabled (ADEN=1) and if there is no regular conversion ongoing (ADSTART must be equal to 0). • For control bits related to configuration of injected conversions, the software is allowed to write them only if the ADC is enabled (ADEN=1) and if there is no injected conversion ongoing (JADSTART must be equal to 0). The software is allowed to write the ADSTP or JADSTP control bits of the ADC_CR register only if the ADC is enabled, possibly converting, and if there is no pending request to disable the ADC (ADSTART or JADSTART must be equal to 1 and ADDIS to 0). The software can write the register ADC_JSQR at any time, when the ADC is enabled (ADEN=1). Refer to Section 16.6.16: ADC injected sequence register (ADC_JSQR) for additional details. Note: There is no hardware protection to prevent these forbidden write accesses and ADC behavior may become in an unknown state. To recover from this situation, the ADC must be disabled (clear ADEN=0 as well as all the bits of ADC_CR register). RM0394 Rev 4 387/1600 485 Analog-to-digital converters (ADC) 16.4.11 RM0394 Channel selection (SQRx, JSQRx) There are up to 19 multiplexed channels per ADC: Note: • 5 fast analog inputs coming from GPIO pads (ADCx_INP/INN[1..5]) • Up to 11 slow analog inputs coming from GPIO pads (ADCx_INP/INN[6..16]). Depending on the products, not all of them are available on GPIO pads. • The ADCs are connected to the following internal analog inputs: – the internal reference voltage (VREFINT) is connected to ADC1_INP0/INN0. – the internal temperature sensor (VTS) is connected to ADC1_INP17/INN17. – the VBAT monitoring channel (VBAT/3) is connected to ADC1_INP18/INN18. – the DAC1 internal channel is connected to ADC1_INP/INN17. To convert one of the internal analog channels, the corresponding analog sources must first be enabled by programming bits VREFEN, CH17SEL or CH18SEL in the ADCx_CCR registers. It is possible to organize the conversions in two groups: regular and injected. A group consists of a sequence of conversions that can be done on any channel and in any order. For instance, it is possible to implement the conversion sequence in the following order: ADCx_INP/INN3, ADCx_INP/INN8, ADCx_INP/INN2, ADCx/INN2, ADCx_INP/INN0, ADCx_INP/INN2, ADCx_INP/INN2, ADCx_INP/INN15. • A regular group is composed of up to 16 conversions. The regular channels and their order in the conversion sequence must be selected in the ADC_SQRy registers. The total number of conversions in the regular group must be written in the L[3:0] bits in the ADC_SQR1 register. • An injected group is composed of up to 4 conversions. The injected channels and their order in the conversion sequence must be selected in the ADC_JSQR register. The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register. ADC_SQRy registers must not be modified while regular conversions can occur. For this, the ADC regular conversions must be first stopped by writing ADSTP=1 (refer to Section 16.4.17: Stopping an ongoing conversion (ADSTP, JADSTP)). The software is allowed to modify on-the-fly the ADC_JSQR register when JADSTART is set to 1 (injected conversions ongoing) only when the context queue is enabled (JQDIS=0 in ADC_CFGR register). Refer to Section 16.4.21: Queue of context for injected conversions 388/1600 RM0394 Rev 4 RM0394 16.4.12 Analog-to-digital converters (ADC) Channel-wise programmable sampling time (SMPR1, SMPR2) Before starting a conversion, the ADC must establish a direct connection between the voltage source under measurement and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the embedded capacitor to the input voltage level. Each channel can be sampled with a different sampling time which is programmable using the SMP[2:0] bits in the ADC_SMPR1 and ADC registers. It is therefore possible to select among the following sampling time values: • SMP = 000: 2.5 ADC clock cycles • SMP = 001: 6.5 ADC clock cycles • SMP = 010: 12.5 ADC clock cycles • SMP = 011: 24.5 ADC clock cycles • SMP = 100: 47.5 ADC clock cycles • SMP = 101: 92.5 ADC clock cycles • SMP = 110: 247.5 ADC clock cycles • SMP = 111: 640.5 ADC clock cycles The total conversion time is calculated as follows: TCONV = Sampling time + 12.5 ADC clock cycles Example: With FADC_CLK = 80 MHz and a sampling time of 2.5 ADC clock cycles: TCONV = (2.5 + 12.5) ADC clock cycles = 15 ADC clock cycles = 187.5 ns (for fast channels) The ADC notifies the end of the sampling phase by setting the status bit EOSMP (only for regular conversion). Constraints on the sampling time for fast and slow channels For each channel, SMP[2:0] bits must be programmed to respect a minimum sampling time as specified in the ADC characteristics section of the datasheets. I/O analog switches voltage booster The I/O analog switches resistance increases when the VDDA voltage is too low. This requires to have the sampling time adapted accordingly (cf datasheet for electrical characteristics). This resistance can be minimized at low VDDA by enabling an internal voltage booster with BOOSTEN bit in the SYSCFG_CFGR1 register. 16.4.13 Single conversion mode (CONT=0) In Single conversion mode, the ADC performs once all the conversions of the channels. This mode is started with the CONT bit at 0 by either: • Setting the ADSTART bit in the ADC_CR register (for a regular channel) • Setting the JADSTART bit in the ADC_CR register (for an injected channel) • External hardware trigger event (for a regular or injected channel) RM0394 Rev 4 389/1600 485 Analog-to-digital converters (ADC) RM0394 Inside the regular sequence, after each conversion is complete: • The converted data are stored into the 16-bit ADC_DR register • The EOC (end of regular conversion) flag is set • An interrupt is generated if the EOCIE bit is set Inside the injected sequence, after each conversion is complete: • The converted data are stored into one of the four 16-bit ADC_JDRy registers • The JEOC (end of injected conversion) flag is set • An interrupt is generated if the JEOCIE bit is set After the regular sequence is complete: • The EOS (end of regular sequence) flag is set • An interrupt is generated if the EOSIE bit is set After the injected sequence is complete: • The JEOS (end of injected sequence) flag is set • An interrupt is generated if the JEOSIE bit is set Then the ADC stops until a new external regular or injected trigger occurs or until bit ADSTART or JADSTART is set again. Note: To convert a single channel, program a sequence with a length of 1. 16.4.14 Continuous conversion mode (CONT=1) This mode applies to regular channels only. In continuous conversion mode, when a software or hardware regular trigger event occurs, the ADC performs once all the regular conversions of the channels and then automatically restarts and continuously converts each conversions of the sequence. This mode is started with the CONT bit at 1 either by external trigger or by setting the ADSTART bit in the ADC_CR register. Inside the regular sequence, after each conversion is complete: • The converted data are stored into the 16-bit ADC_DR register • The EOC (end of conversion) flag is set • An interrupt is generated if the EOCIE bit is set After the sequence of conversions is complete: • The EOS (end of sequence) flag is set • An interrupt is generated if the EOSIE bit is set Then, a new sequence restarts immediately and the ADC continuously repeats the conversion sequence. Note: To convert a single channel, program a sequence with a length of 1. It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. Injected channels cannot be converted continuously. The only exception is when an injected channel is configured to be converted automatically after regular channels in continuous mode (using JAUTO bit), refer to Auto-injection mode section). 390/1600 RM0394 Rev 4 RM0394 16.4.15 Analog-to-digital converters (ADC) Starting conversions (ADSTART, JADSTART) Software starts ADC regular conversions by setting ADSTART=1. When ADSTART is set, the conversion starts: • Immediately: if EXTEN = 0x0 (software trigger) • At the next active edge of the selected regular hardware trigger: if EXTEN /= 0x0 Software starts ADC injected conversions by setting JADSTART=1. When JADSTART is set, the conversion starts: Note: • Immediately, if JEXTEN = 0x0 (software trigger) • At the next active edge of the selected injected hardware trigger: if JEXTEN /= 0x0 In auto-injection mode (JAUTO=1), use ADSTART bit to start the regular conversions followed by the auto-injected conversions (JADSTART must be kept cleared). ADSTART and JADSTART also provide information on whether any ADC operation is currently ongoing. It is possible to re-configure the ADC while ADSTART=0 and JADSTART=0 are both true, indicating that the ADC is idle. ADSTART is cleared by hardware: • In single mode with software regular trigger (CONT=0, EXTSEL=0x0) – • In all cases (CONT=x, EXTSEL=x) – Note: at any end of regular conversion sequence (EOS assertion) or at any end of subgroup processing if DISCEN = 1 after execution of the ADSTP procedure asserted by the software. In continuous mode (CONT=1), ADSTART is not cleared by hardware with the assertion of EOS because the sequence is automatically relaunched. When a hardware trigger is selected in single mode (CONT=0 and EXTSEL /=0x00), ADSTART is not cleared by hardware with the assertion of EOS to help the software which does not need to reset ADSTART again for the next hardware trigger event. This ensures that no further hardware triggers are missed. JADSTART is cleared by hardware: • in single mode with software injected trigger (JEXTSEL=0x0) – • in all cases (JEXTSEL=x) – Note: at any end of injected conversion sequence (JEOS assertion) or at any end of subgroup processing if JDISCEN = 1 after execution of the JADSTP procedure asserted by the software. When the software trigger is selected, ADSTART bit should not be set if the EOC flag is still high. RM0394 Rev 4 391/1600 485 Analog-to-digital converters (ADC) 16.4.16 RM0394 ADC timing The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution: TCONV= TSMPL + TSAR = [ 2.5 |min + 12.5 |12bit ] x TADC_CLK TCONV = TSMPL + TSAR = 31.25 ns |min + 156.25 ns |12bit = 187.5 ns (for FADC_CLK = 80 MHz) Figure 47. Analog to digital conversion time $'&VWDWH 5'< 6DPSOLQJ&K 1 $QDORJFKDQQHO &K 1 &K 1 ,QWHUQDO6+ $'67$57 6DPSOLQJ&K 1 &RQYHUWLQJ&K 1 6HW E\6: (2603 +ROG$,1 1 W6$5 6DPSOH$,1 1 W603/ 6HW E\+: &OHDUHG E\6: 6HW E\+: (2& $'&B'5 6DPSOH$,1 1 'DWD1 &OHDUHG E\6: 'DWD1 ,QGLFDWLYHWLPLQJV 069 1. TSMPL depends on SMP[2:0] 2. TSAR depends on RES[2:0] 16.4.17 Stopping an ongoing conversion (ADSTP, JADSTP) The software can decide to stop regular conversions ongoing by setting ADSTP=1 and injected conversions ongoing by setting JADSTP=1. Stopping conversions will reset the ongoing ADC operation. Then the ADC can be reconfigured (ex: changing the channel selection or the trigger) ready for a new operation. Note that it is possible to stop injected conversions while regular conversions are still operating and vice-versa. This allows, for instance, re-configuration of the injected conversion sequence and triggers while regular conversions are still operating (and viceversa). When the ADSTP bit is set by software, any ongoing regular conversion is aborted with partial result discarded (ADC_DR register is not updated with the current conversion). When the JADSTP bit is set by software, any ongoing injected conversion is aborted with partial result discarded (ADC_JDRy register is not updated with the current conversion). The scan sequence is also aborted and reset (meaning that relaunching the ADC would restart a new sequence). Once this procedure is complete, bits ADSTP/ADSTART (in case of regular conversion), or JADSTP/JADSTART (in case of injected conversion) are cleared by hardware and the software must poll ADSTART (or JADSTART) until the bit is reset before assuming the ADC is completely stopped. 392/1600 RM0394 Rev 4 RM0394 Note: Analog-to-digital converters (ADC) In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (JADSTP must not be used). Figure 48. Stopping ongoing regular conversions 7ULJJHU 7ULJJHU $'&VWDWH 6DPSOH &K 1 5'< &RQYHUW &K 1 5'< 6DPSOH & &K 1 5'< -$'67$57 $'67$57 &OHDUHGE\ +: &OHDUHGE\ +: 5(*8/$5&219(56,216RQJRLQJ VRIWZDUHLVQRWDOORZHGWRFRQILJXUHUHJXODUFRQYHUVLRQVVHOHFWLRQDQGWULJJHUV 6HWE\ 6: $'673 $'&B'5 &OHDUHGE\ +: 'DWD1 'DWD1 06Y9 Figure 49. Stopping ongoing regular and injected conversions 2EGULAR TRIGGER $'&VWDWH 2$9 3AMPLE #H. )NJECTED TRIGGER #ONVERT #H. 2$9 2EGULAR TRIGGER 3AMPLE #H- # 2$9 3AMPL 2$9 #LEARED 3ET *!$34!24 BY 37 BY (7 ).*%#4%$ #/.6%23)/.3 ONGOING SOFTWARE IS NOT ALLOWED TO CONFIGURE INJECTED CONVERSIONS SELECTION AND TRIGGERS 3ET BY 37 *!$340 !$#?*$2 #LEARED BY (7 $!4! - 3ET BY 37 !$34!24 !$340 !$#?$2 #LEARED BY (7 2%'5,!2 #/.6%23)/.3 ONGOING SOFTWARE IS NOT ALLOWED TO CONFIGURE REGULAR CONVERSIONS SELECTION AND TRIGGERS 3ET BY 37 $!4! . #LEARED BY (7 $!4! . 069 RM0394 Rev 4 393/1600 485 Analog-to-digital converters (ADC) 16.4.18 RM0394 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN,JEXTSEL, JEXTEN) A conversion or a sequence of conversions can be triggered either by software or by an external event (e.g. timer capture, input pins). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then external events are able to trigger a conversion with the selected polarity. When the Injected Queue is enabled (bit JQDIS=0), injected software triggers are not possible. The regular trigger selection is effective once software has set bit ADSTART=1 and the injected trigger selection is effective once software has set bit JADSTART=1. Any hardware triggers which occur while a conversion is ongoing are ignored. • If bit ADSTART=0, any regular hardware triggers which occur are ignored. • If bit JADSTART=0, any injected hardware triggers which occur are ignored. Table 57 provides the correspondence between the EXTEN[1:0] and JEXTEN[1:0] values and the trigger polarity. Table 57. Configuring the trigger polarity for regular external triggers EXTEN[1:0] Note: Source 00 Hardware Trigger detection disabled, software trigger detection enabled 01 Hardware Trigger with detection on the rising edge 10 Hardware Trigger with detection on the falling edge 11 Hardware Trigger with detection on both the rising and falling edges The polarity of the regular trigger cannot be changed on-the-fly. Table 58. Configuring the trigger polarity for injected external triggers Note: JEXTEN[1:0] Source 00 – If JQDIS=1 (Queue disabled): Hardware trigger detection disabled, software trigger detection enabled – If JQDIS=0 (Queue enabled), Hardware and software trigger detection disabled 01 Hardware Trigger with detection on the rising edge 10 Hardware Trigger with detection on the falling edge 11 Hardware Trigger with detection on both the rising and falling edges The polarity of the injected trigger can be anticipated and changed on-the-fly when the queue is enabled (JQDIS=0). Refer to Section 16.4.21: Queue of context for injected conversions. The EXTSEL and JEXTSEL control bits select which out of 16 possible events can trigger conversion for the regular and injected groups. A regular group conversion can be interrupted by an injected trigger. 394/1600 RM0394 Rev 4 RM0394 Note: Analog-to-digital converters (ADC) The regular trigger selection cannot be changed on-the-fly. The injected trigger selection can be anticipated and changed on-the-fly. Refer to Section 16.4.21: Queue of context for injected conversions on page 399 Each ADC master shares the same input triggers with its ADC slave as described in Figure 50. Figure 50. Triggers sharing between ADC master and ADC slave $'&0$67(5 5HJXODU VHTXHQFHU WULJJHUV (;7 (;7 ([WHUQDOUHJXODUWULJJHU (;7 (;76(/>@ ([WHUQDOLQMHFWHGWULJJHU -(;76(/>@ $'&6/$9( ([WHUQDOUHJXODUWULJJHU (;76(/>@ ,QMHFWHG VHTXHQFHU WULJJHUV -(;7 -(;7 -(;7 ([WHUQDOLQMHFWHGWULJJHU -(;76(/>@ 069 Table 59 toTable 60 give all the possible external triggers of the three ADCs for regular and injected conversion. Table 59. ADC1 and ADC2 - External triggers for regular channels Name Source Type EXTSEL[3:0] EXT0 TIM1_CH1 Internal signal from on-chip timers 0000 EXT1 TIM1_CH2 Internal signal from on-chip timers 0001 EXT2 TIM1_CH3 Internal signal from on-chip timers 0010 EXT3 TIM2_CH2 Internal signal from on-chip timers 0011 EXT4 TIM3_TRGO(1) Internal signal from on-chip timers 0100 EXT5 - - 0101 EXT6 EXTI line 11 External pin 0110 EXT9 TIM1_TRGO Internal signal from on-chip timers 1001 EXT10 TIM1_TRGO2 Internal signal from on-chip timers 1010 EXT11 TIM2_TRGO Internal signal from on-chip timers 1011 RM0394 Rev 4 395/1600 485 Analog-to-digital converters (ADC) RM0394 Table 59. ADC1 and ADC2 - External triggers for regular channels (continued) Name Source Type EXTSEL[3:0] EXT13 TIM6_TRGO Internal signal from on-chip timers 1101 EXT14 TIM15_TRGO Internal signal from on-chip timers 1110 1. Available only on STM32L451xx/452xx/462xx. Table 60. ADC1 and ADC2 - External trigger for injected channels Name Source Type JEXTSEL[3..0] JEXT0 TIM1_TRGO Internal signal from on-chip timers 0000 JEXT1 TIM1_CH4 Internal signal from on-chip timers 0001 JEXT2 TIM2_TRGO Internal signal from on-chip timers 0010 JEXT3 TIM2_CH1 Internal signal from on-chip timers 0011 Internal signal from on-chip timers 0100 (1) JEXT4 TIM3_CH4 JEXT5 - - 0101 JEXT6 EXTI line 15 External pin 0110 JEXT8 TIM1_TRGO2 Internal signal from on-chip timers 1000 JEXT14 TIM6_TRGO Internal signal from on-chip timers 1110 JEXT15 TIM15_TRGO Internal signal from on-chip timers 1111 1. Available only on STM32L451xx/452xx/462xx. 16.4.19 Injected channel management Triggered injection mode To use triggered injection, the JAUTO bit in the ADC_CFGR register must be cleared. Note: 396/1600 1. Start the conversion of a group of regular channels either by an external trigger or by setting the ADSTART bit in the ADC_CR register. 2. If an external injected trigger occurs, or if the JADSTART bit in the ADC_CR register is set during the conversion of a regular group of channels, the current conversion is reset and the injected channel sequence switches are launched (all the injected channels are converted once). 3. Then, the regular conversion of the regular group of channels is resumed from the last interrupted regular conversion. 4. If a regular event occurs during an injected conversion, the injected conversion is not interrupted but the regular sequence is executed at the end of the injected sequence. Figure 51 shows the corresponding timing diagram. When using triggered injection, one must ensure that the interval between trigger events is longer than the injection sequence. For instance, if the sequence length is 28 ADC clock cycles (that is two conversions with a sampling time of 1.5 clock periods), the minimum interval between triggers must be 29 ADC clock cycles. RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Auto-injection mode If the JAUTO bit in the ADC_CFGR register is set, then the channels in the injected group are automatically converted after the regular group of channels. This can be used to convert a sequence of up to 20 conversions programmed in the ADC_SQRy and ADC_JSQR registers. In this mode, the ADSTART bit in the ADC_CR register must be set to start regular conversions, followed by injected conversions (JADSTART must be kept cleared). Setting the ADSTP bit aborts both regular and injected conversions (JADSTP bit must not be used). In this mode, external trigger on injected channels must be disabled. If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected channels are continuously converted. Note: It is not possible to use both the auto-injected and discontinuous modes simultaneously. When the DMA is used for exporting regular sequencer’s data in JAUTO mode, it is necessary to program it in circular mode (CIRC bit set in DMA_CCRx register). If the CIRC bit is reset (single-shot mode), the JAUTO sequence will be stopped upon DMA Transfer Complete event. Figure 51. Injected conversion latency !$##,+ ,QMHFWLRQHYHQW 5HVHW$'& PD[ODWHQF\ 62& AIB 1. The maximum latency value can be found in the electrical characteristics of the STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx datasheet. RM0394 Rev 4 397/1600 485 Analog-to-digital converters (ADC) 16.4.20 RM0394 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) Regular group mode This mode is enabled by setting the DISCEN bit in the ADC_CFGR register. It is used to convert a short sequence (subgroup) of n conversions (n ≤ 8) that is part of the sequence of conversions selected in the ADC_SQRy registers. The value of n is specified by writing to the DISCNUM[2:0] bits in the ADC_CFGR register. When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRy registers until all the conversions in the sequence are done. The total sequence length is defined by the L[3:0] bits in the ADC_SQR1 register. Example: • • Note: DISCEN=1, n=3, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10, 11 – 1st trigger: channels converted are 1, 2, 3 (an EOC event is generated at each conversion). – 2nd trigger: channels converted are 6, 7, 8 (an EOC event is generated at each conversion). – 3rd trigger: channels converted are 9, 10, 11 (an EOC event is generated at each conversion) and an EOS event is generated after the conversion of channel 11. – 4th trigger: channels converted are 1, 2, 3 (an EOC event is generated at each conversion). – ... DISCEN=0, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10,11 – 1st trigger: the complete sequence is converted: channel 1, then 2, 3, 6, 7, 8, 9, 10 and 11. Each conversion generates an EOC event and the last one also generates an EOS event. – all the next trigger events will relaunch the complete sequence. When a regular group is converted in discontinuous mode, no rollover occurs (the last subgroup of the sequence can have less than n conversions). When all subgroups are converted, the next trigger starts the conversion of the first subgroup. In the example above, the 4th trigger reconverts the channels 1, 2 and 3 in the 1st subgroup. It is not possible to have both discontinuous mode and continuous mode enabled. In this case (if DISCEN=1, CONT=1), the ADC behaves as if continuous mode was disabled. 398/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Injected group mode This mode is enabled by setting the JDISCEN bit in the ADC_CFGR register. It converts the sequence selected in the ADC_JSQR register, channel by channel, after an external injected trigger event. This is equivalent to discontinuous mode for regular channels where ‘n’ is fixed to 1. When an external trigger occurs, it starts the next channel conversions selected in the ADC_JSQR registers until all the conversions in the sequence are done. The total sequence length is defined by the JL[1:0] bits in the ADC_JSQR register. Example: • Note: JDISCEN=1, channels to be converted = 1, 2, 3 – 1st trigger: channel 1 converted (a JEOC event is generated) – 2nd trigger: channel 2 converted (a JEOC event is generated) – 3rd trigger: channel 3 converted and a JEOC event + a JEOS event are generated – ... When all injected channels have been converted, the next trigger starts the conversion of the first injected channel. In the example above, the 4th trigger reconverts the 1st injected channel 1. It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. 16.4.21 Queue of context for injected conversions A queue of context is implemented to anticipate up to 2 contexts for the next injected sequence of conversions. JQDIS bit of ADC_CFGR register must be reset to enable this feature. Only hardware-triggered conversions are possible when the context queue is enabled. This context consists of: • Configuration of the injected triggers (bits JEXTEN[1:0] and JEXTSEL bits in ADC_JSQR register) • Definition of the injected sequence (bits JSQx[4:0] and JL[1:0] in ADC_JSQR register) All the parameters of the context are defined into a single register ADC_JSQR and this register implements a queue of 2 buffers, allowing the bufferization of up to 2 sets of parameters: • The JSQR register can be written at any moment even when injected conversions are ongoing. • Each data written into the JSQR register is stored into the Queue of context. • At the beginning, the Queue is empty and the first write access into the JSQR register immediately changes the context and the ADC is ready to receive injected triggers. • Once an injected sequence is complete, the Queue is consumed and the context changes according to the next JSQR parameters stored in the Queue. This new context is applied for the next injected sequence of conversions. RM0394 Rev 4 399/1600 485 Analog-to-digital converters (ADC) Note: • A Queue overflow occurs when writing into register JSQR while the Queue is full. This overflow is signaled by the assertion of the flag JQOVF. When an overflow occurs, the write access of JSQR register which has created the overflow is ignored and the queue of context is unchanged. An interrupt can be generated if bit JQOVFIE is set. • Two possible behaviors are possible when the Queue becomes empty, depending on the value of the control bit JQM of register ADC_CFGR: – If JQM=0, the Queue is empty just after enabling the ADC, but then it can never be empty during run operations: the Queue always maintains the last active context and any further valid start of injected sequence will be served according to the last active context. – If JQM=1, the Queue can be empty after the end of an injected sequence or if the Queue is flushed. When this occurs, there is no more context in the queue and hardware triggers are disabled. Therefore, any further hardware injected triggers are ignored until the software re-writes a new injected context into JSQR register. • Reading JSQR register returns the current JSQR context which is active at that moment. When the JSQR context is empty, JSQR is read as 0x0000. • The Queue is flushed when stopping injected conversions by setting JADSTP=1 or when disabling the ADC by setting ADDIS=1: – If JQM=0, the Queue is maintained with the last active context. – If JQM=1, the Queue becomes empty and triggers are ignored. When configured in discontinuous mode (bit JDISCEN=1), only the last trigger of the injected sequence changes the context and consumes the Queue.The 1st trigger only consumes the queue but others are still valid triggers as shown by the discontinuous mode example below (length = 3 for both contexts): • • • • • • 400/1600 RM0394 1st trigger, discontinuous. Sequence 1: context 1 consumed, 1st conversion carried out 2nd trigger, disc. Sequence 1: 2nd conversion. 3rd trigger, discontinuous. Sequence 1: 3rd conversion. 4th trigger, discontinuous. Sequence 2: context 2 consumed, 1st conversion carried out. 5th trigger, discontinuous. Sequence 2: 2nd conversion. 6th trigger, discontinuous. Sequence 2: 3rd conversion. RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Behavior when changing the trigger or sequence context The Figure 52 and Figure 53 show the behavior of the context Queue when changing the sequence or the triggers. Figure 52. Example of JSQR queue of context (sequence change) 3 3 3 :ULWH-645 -645TXHXH (037< 3 (037< 3 33 3 3 33 7ULJJHU $'&-FRQWH[W UHWXUQHGE\UHDGLQJ -465 $'&VWDWH 3 5'< &RQYHUVLRQ &RQYHUVLRQ 3 5'< &RQYHUVLRQ &RQYHUVLRQ 5'< 069 1. Parameters: P1: sequence of 3 conversions, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 4 conversions, hardware trigger 1 Figure 53. Example of JSQR queue of context (trigger change) 3 3 3 :ULWH-645 -645TXHXH (037< 3 33 3 3 33 ,JQRUHG 7ULJJHU ,JQRUHG 7ULJJHU $'&-FRQWH[W UHWXUQHGE\UHDGLQJ -465 $'&VWDWH (037< 3 5'< 3 &RQYHUVLRQ &RQYHUVLRQ 3 5'< &RQYHUVLRQ 5'< 069 1. Parameters: P1: sequence of 2 conversions, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 2 P3: sequence of 4 conversions, hardware trigger 1 RM0394 Rev 4 401/1600 485 Analog-to-digital converters (ADC) RM0394 Queue of context: Behavior when a queue overflow occurs The Figure 54 and Figure 55 show the behavior of the context Queue if an overflow occurs before or during a conversion. Figure 54. Example of JSQR queue of context with overflow before conversion 3 3 3 :ULWH-645 -645 (037< TXHXH 3 3 !2YHUIORZ LJQRUHG 33 3 33 &OHDUHGE\6: -429) 7ULJJHU 7ULJJHU $'& -FRQWH[W (037< UHWXUQHGE\ UHDGLQJ-465 $'&VWDWH 3 3 5'< &RQYHUVLRQ &RQYHUVLRQ 5'< &RQYHUVLRQ -(26 069 1. Parameters: P1: sequence of 2 conversions, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 2 P3: sequence of 3 conversions, hardware trigger 1 P4: sequence of 4 conversions, hardware trigger 1 Figure 55. Example of JSQR queue of context with overflow during conversion 3 3 3 :ULWH-645 -645 (037< TXHXH 3 3 !2YHUIORZ LJQRUHG 33 3 33 &OHDUHGE\6: -429) 7ULJJHU 7ULJJHU $'& -FRQWH[W UHWXUQHGE\ (037< UHDGLQJ-465 $'&VWDWH 3 3 5'< &RQYHUVLRQ &RQYHUVLRQ 5'< &RQYHUVLRQ -(26 069 1. Parameters: P1: sequence of 2 conversions, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 2 P3: sequence of 3 conversions, hardware trigger 1 P4: sequence of 4 conversions, hardware trigger 1 402/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) It is recommended to manage the queue overflows as described below: • After each P context write into JSQR register, flag JQOVF shows if the write has been ignored or not (an interrupt can be generated). • Avoid Queue overflows by writing the third context (P3) only once the flag JEOS of the previous context P2 has been set. This ensures that the previous context has been consumed and that the queue is not full. Queue of context: Behavior when the queue becomes empty Figure 56 and Figure 57 show the behavior of the context Queue when the Queue becomes empty in both cases JQM=0 or 1. Figure 56. Example of JSQR queue of context with empty queue (case JQM=0) 3 7KHTXHXHLVQRWHPSW\ DQGPDLQWDLQV3EHFDXVH-40 3 4XHXHQRWHPSW\ 3PDLQWDLQHG 3 :ULWH-645 (037< 3 $'&-FRQWH[W UHWXUQHGE\ (037< UHDGLQJ-465 3 -645TXHXH 33 3 3 7ULJJHU $'&VWDWH 5'< 3 #ONVERSION 5'< 3 #ONVERSION 5'< #ONVERSION 5'< #ONVERSION 5'< #ONV 069 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Note: When writing P3, the context changes immediately. However, because of internal resynchronization, there is a latency and if a trigger occurs just after or before writing P3, it can happen that the conversion is launched considering the context P2. To avoid this situation, the user must ensure that there is no ADC trigger happening when writing a new context that applies immediately. RM0394 Rev 4 403/1600 485 Analog-to-digital converters (ADC) RM0394 Figure 57. Example of JSQR queue of context with empty queue (case JQM=1) 3 1UEUE BECOMES EMPTY AND TRIGGERS ARE IGNORED BECAUSE *1- 3 3 :ULWH-645 -645 TXHXH (037< 3 33 3 (037< )GNORED )GNORED 7ULJJHU $'& 3 -FRQWH[W (037< UHWXUQHGE\UHDGLQJ-465 $'&VWDWH 3 (037< 3 5'< &RQYHUVLRQ 5'< (037< [ &RQYHUVLRQ 5'< 3 (037< &RQYHUVLRQ 5'< -36 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Flushing the queue of context The figures below show the behavior of the context Queue in various situations when the queue is flushed. Figure 58. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion. 3 3 4XHXHLVIOXVKHGDQGPDLQWDLQV WKHODVWDFWLYHFRQWH[W 3LVORVW 3 :ULWH-645 -645TXHXH (037< 3 33 3 6HW E\6: -$'673 3 5HVHW E\+: -$'67$57 5HVHW E\+: 6HW E\6: 7ULJJHU $'&-FRQWH[W (037< 3 3 UHWXUQHGE\UHDGLQJ-645 $'&VWDWH 5'< 673 5'< &RQYHUVLRQ 5'< 069 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 404/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Figure 59. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion and a new trigger occurs. 0 1UEUE IS FLUSHED AND MAINTAINS THE LAST ACTIVE CONTEXT 0 0 IS LOST 0 7RITE *312 *312 QUEUE %-049 0 0 0 0 *!$340 0 0 0 2ESET BY (7 3ET BY 37 *!$34!24 2ESET BY (7 3ET BY 37 4RIGGER !$# * %-049 0 CONTEXT RETURNED BY READING *312 !$# STATE 0 2$9 #ONV 340 !BORTED 2$9 #ONVERSION 2$9 #ONVERSION 2$9 -36 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Figure 60. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs outside an ongoing conversion 3 3 :ULWH-645 -645TXHXH (037< 3 WKHODVWDFWLYHFRQWH[W 3LVORVW 3 33 6HW E\6: -$'673 3 3 5HVHW E\+: -$'67$57 5HVHW E\+: 6HW E\6: 7ULJJHU $'&-FRQWH[W (037< 3 UHWXUQHGE\UHDGLQJ-645 $'&VWDWH 3 5'< 673 5'< &RQYHUVLRQ 5'< 069 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 RM0394 Rev 4 405/1600 485 Analog-to-digital converters (ADC) RM0394 Figure 61. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) 0 1UEUE IS FLUSHED AND BECOMES EMPTY 0 IS LOST 0 0 7RITE *312 *312 QUEUE %-049 0 0 0 %-049 %-049 0 %-049 2ESET BY (7 3ET BY 37 *!$340 *!$34!24 0 2ESET BY (7 3ET BY 37 )GNORED 4RIGGER !$# * CONTEXT %-049 0 RETURNED BY READING *312 !$# STATE 2$9 %-049 X #ONV 340 #ONVERSION 2$9 !BORTED 2$9 -36 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Figure 62. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0) 1UEUE IS FLUSHED AND MAINTAINS THE LAST ACTIVE CONTEXT 0 WHICH WAS NOT CONSUMED IS LOST *312 QUEUE 0 0 0 3ET BY 37 !$$)3 2ESET BY (7 0 !$# * CONTEXT RETURNED BY READING *312 !$# STATE 2$9 2%1 /&& /&& -36 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 406/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Figure 63. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1) 1UEUE IS FLUSHED AND BEOMES EMPTY *312 IS READ AS X *312 QUEUE 0 0 %-049 2ESET BY (7 3ET BY 37 !$$)3 0 !$# * CONTEXT RETURNED BY READING *312 !$# STATE 2$9 %-049 X 2%1 /&& /&& -36 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Queue of context: Starting the ADC with an empty queue The following procedure must be followed to start ADC operation with an empty queue, in case the first context is not known at the time the ADC is initialized. This procedure is only applicable when JQM bit is reset: 5. Write a dummy JSQR with JEXTEN not equal to 0 (otherwise triggering a software conversion) 6. Set JADSTART 7. Set JADSTP 8. Wait until JADSTART is reset 9. Set JADSTART. Disabling the queue It is possible to disable the queue by setting bit JQDIS=1 into the ADC_CFGR register. 16.4.22 Programmable resolution (RES) - fast conversion mode It is possible to perform faster conversion by reducing the ADC resolution. The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the control bits RES[1:0]. Figure 68, Figure 69, Figure 70 and Figure 71 show the conversion result format with respect to the resolution as well as to the data alignment. Lower resolution allows faster conversion time for applications where high-data precision is not required. It reduces the conversion time spent by the successive approximation steps according to Table 61. RM0394 Rev 4 407/1600 485 Analog-to-digital converters (ADC) RM0394 Table 61. TSAR timings depending on resolution RES (bits) 16.4.23 TSAR (ADC clock cycles) TSAR (ns) at FADC=80 MHz TCONV (ADC clock cycles) (with Sampling Time= 2.5 ADC clock cycles) TCONV (ns) at FADC=80 MHz 12 12.5 ADC clock cycles 156.25 ns 15 ADC clock cycles 187.5 ns 10 10.5 ADC clock cycles 131.25 ns 13 ADC clock cycles 162.5 ns 8 8.5 ADC clock cycles 106.25 ns 11 ADC clock cycles 137.5 ns 6 6.5 ADC clock cycles 81.25 ns 9 ADC clock cycles 112.5 ns End of conversion, end of sampling phase (EOC, JEOC, EOSMP) The ADC notifies the application for each end of regular conversion (EOC) event and each injected conversion (JEOC) event. The ADC sets the EOC flag as soon as a new regular conversion data is available in the ADC_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared by the software either by writing 1 to it or by reading ADC_DR. The ADC sets the JEOC flag as soon as a new injected conversion data is available in one of the ADC_JDRy register. An interrupt can be generated if bit JEOCIE is set. JEOC flag is cleared by the software either by writing 1 to it or by reading the corresponding ADC_JDRy register. The ADC also notifies the end of Sampling phase by setting the status bit EOSMP (for regular conversions only). EOSMP flag is cleared by software by writing 1 to it. An interrupt can be generated if bit EOSMPIE is set. 16.4.24 End of conversion sequence (EOS, JEOS) The ADC notifies the application for each end of regular sequence (EOS) and for each end of injected sequence (JEOS) event. The ADC sets the EOS flag as soon as the last data of the regular conversion sequence is available in the ADC_DR register. An interrupt can be generated if bit EOSIE is set. EOS flag is cleared by the software either by writing 1 to it. The ADC sets the JEOS flag as soon as the last data of the injected conversion sequence is complete. An interrupt can be generated if bit JEOSIE is set. JEOS flag is cleared by the software either by writing 1 to it. 408/1600 RM0394 Rev 4 RM0394 16.4.25 Analog-to-digital converters (ADC) Timing diagrams example (single/continuous modes, hardware/software triggers) Figure 64. Single conversions of a sequence, software trigger $'67$57 (2& (26 $'&VWDWH 5'< &+ &+ &+ &+ ' ' ' $'&B'5 E\VZ 5'< &+ ' &+ &+ &+ 5'< ' ' ' ' E\KZ ,QGLFDWLYHWLPLQJV 069 1. EXTEN=0x0, CONT=0 2. Channels selected = 1,9, 10, 17; AUTDLY=0. Figure 65. Continuous conversion of a sequence, software trigger $'67$57 (2& (26 $'673 $'&VWDWH 5($'< &+ $'&B'5 E\VZ &+ &+ &+ &+ &+ ' ' ' ' ' &+ 673 5($'< &+ ' &+ ' ,QGLFDWLYHWLPLQJV E\KZ -36 1. EXTEN=0x0, CONT=1 2. Channels selected = 1,9, 10, 17; AUTDLY=0. RM0394 Rev 4 409/1600 485 Analog-to-digital converters (ADC) RM0394 Figure 66. Single conversions of a sequence, hardware trigger $'67$57 (2& (26 75*; $'&VWDWH &+ 5'< $'&B'5 E\VZ E\KZ &+ &+ &+ ' ' ' WULJJHUHG 5($'< &+ ' &+ &+ &+ 5'< ' ' ' ' ,QGLFDWLYHWLPLQJV LJQRUHG 069 1. TRGx (over-frequency) is selected as trigger source, EXTEN = 01, CONT = 0 2. Channels selected = 1, 2, 3, 4; AUTDLY=0. Figure 67. Continuous conversions of a sequence, hardware trigger $'67$57 (2& (26 $'673 75*[ $'& 5'< &+ &+ &+ ' $'&B'5 E\VZ E\KZ ' &+ &+ &+ &+ &+ &+ ' ' ' ' ' ' WULJJHUHG LJQRUHG 6723 5'< 1RWLQVFDOHWLPLQJV 069 1. TRGx is selected as trigger source, EXTEN = 10, CONT = 1 2. Channels selected = 1, 2, 3, 4; AUTDLY=0. 16.4.26 Data management Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN) Data and alignment At the end of each regular conversion channel (when EOC event occurs), the result of the converted data is stored into the ADC_DR data register which is 16 bits wide. At the end of each injected conversion channel (when JEOC event occurs), the result of the converted data is stored into the corresponding ADC_JDRy data register which is 16 bits wide. The ALIGN bit in the ADC_CFGR register selects the alignment of the data stored after conversion. Data can be right- or left-aligned as shown in Figure 68, Figure 69, Figure 70 410/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) and Figure 71. Special case: when left-aligned, the data are aligned on a half-word basis except when the resolution is set to 6-bit. In that case, the data are aligned on a byte basis as shown in Figure 70 and Figure 71. Note: Left-alignment is not supported in oversampling mode. When ROVSE and/or JOVSE bit is set, the ALIGN bit value is ignored and the ADC only provides right-aligned data. Offset An offset y (y=1,2,3,4) can be applied to a channel by setting the bit OFFSETy_EN=1 into ADC_OFRy register. The channel to which the offset will be applied is programmed into the bits OFFSETy_CH[4:0] of ADC_OFRy register. In this case, the converted value is decreased by the user-defined offset written in the bits OFFSETy[11:0]. The result may be a negative value so the read data is signed and the SEXT bit represents the extended sign value. Note: Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is set, the value of the OFFSETy_EN bit in ADC_OFRy register is ignored (considered as reset). Table 64 describes how the comparison is performed for all the possible resolutions for analog watchdog 1. Table 62. Offset computation versus data resolution Resolution (bits RES[1:0]) Subtraction between raw converted data and offset Raw converted Data, left aligned Result Comments Offset 00: 12-bit DATA[11:0] OFFSET[11:0] Signed 12-bit data - 01: 10-bit DATA[11:2],00 OFFSET[11:0] Signed 10-bit data The user must configure OFFSET[1:0] to “00” 10: 8-bit DATA[11:4],00 00 OFFSET[11:0] Signed 8-bit data The user must configure OFFSET[3:0] to “0000” 11: 6-bit DATA[11:6],00 0000 OFFSET[11:0] Signed 6-bit data The user must configure OFFSET[5:0] to “000000” When reading data from ADC_DR (regular channel) or from ADC_JDRy (injected channel, y=1,2,3,4) corresponding to the channel “i”: • If one of the offsets is enabled (bit OFFSETy_EN=1) for the corresponding channel, the read data is signed. • If none of the four offsets is enabled for this channel, the read data is not signed. Figure 68, Figure 69, Figure 70 and Figure 71 show alignments for signed and unsigned data. RM0394 Rev 4 411/1600 485 Analog-to-digital converters (ADC) RM0394 Figure 68. Right alignment (offset disabled, unsigned value) ELWGDWD ELW ELW ' ' ' ' ' ' ELWGDWD ELW ' ' ' ' ' ' ' ' ' ' ' ' ' ' ELW ' ' ' ' ' ' ELW ' ELW ELW ELWGDWD ELW ELW ' ELW ELWGDWD ELW ' ' ELW ' ' ' ' ' ' 069 Figure 69. Right alignment (offset enabled, signed value) ELWGDWD ELW 6(;7 6(;7 6(;7 6(;7 ' ELW ' ' ' ELWGDWD ELW ' ELW ' ' ' ' ' ' ELW 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 ' ' ELWGDWD ELW ' ELW ' ' ' ' ' ' ELW 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 ' ELWGDWD ELW ' ' ELW ' ' ' ' ' ' ELW 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 ' ELW ' ' ' ' ' ' 069 412/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Figure 70. Left alignment (offset disabled, unsigned value) ELWGDWD ELW ' ' ELW ' ' ' ' ' ' ELWGDWD ELW ' ' ' ' ' ' ' ' ' ' ' ' ELW ' ELW ' ' ' ' ' ' ELWGDWD ELW ' ELW ELWGDWD ELW ' ' ELW ELW ELW ' ELW ' ' ' ' ' 069 Figure 71. Left alignment (offset enabled, signed value) ELWGDWD ELW 6(;7 ' ELW ' ' ' ' ' ' ELWGDWD ELW 6(;7 ' ' ' ' ' ' ELW ' ' ' ' ' ' ELWGDWD ELW 6(;7 ' ELW ' ELW ' ' ELW ' ' ' ' ' ' ELWGDWD ELW ' ELW ELW 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 6(;7 ' ELW ' ' ' ' ' 069 RM0394 Rev 4 413/1600 485 Analog-to-digital converters (ADC) RM0394 ADC overrun (OVR, OVRMOD) The overrun flag (OVR) notifies of a buffer overrun event, when the regular converted data was not read (by the CPU or the DMA) before new converted data became available. The OVR flag is set if the EOC flag is still 1 at the time when a new conversion completes. An interrupt can be generated if bit OVRIE=1. When an overrun condition occurs, the ADC is still operating and can continue to convert unless the software decides to stop and reset the sequence by setting bit ADSTP=1. OVR flag is cleared by software by writing 1 to it. It is possible to configure if data is preserved or overwritten when an overrun event occurs by programming the control bit OVRMOD: • OVRMOD=0: The overrun event preserves the data register from being overrun: the old data is maintained and the new conversion is discarded and lost. If OVR remains at 1, any further conversions will occur but the result data will be also discarded. • OVRMOD=1: The data register is overwritten with the last conversion result and the previous unread data is lost. If OVR remains at 1, any further conversions will operate normally and the ADC_DR register will always contain the latest converted data. Figure 72. Example of overrun (OVR) $'67$57 (2& (26 295 $'673 75*[ $'&VWDWH 5'< &+ &+ &+ &+ &+ $'&B'5UHDGDFFHVV $'&B'5 29502' ' ' ' ' $'&B'5 29502' ' ' ' ' E\VZ &+ &+ ' ' 6723 5'< 2YHUXQ E\KZ WULJJHUHG ,QGLFDWLYHWLPLQJV -36 Note: There is no overrun detection on the injected channels since there is a dedicated data register for each of the four injected channels. Managing a sequence of conversion without using the DMA If the conversions are slow enough, the conversion sequence can be handled by the software. In this case the software must use the EOC flag and its associated interrupt to handle each data. Each time a conversion is complete, EOC is set and the ADC_DR register can be read. OVRMOD should be configured to 0 to manage overrun events as an error. 414/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Managing conversions without using the DMA and without overrun It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). In this case, the OVRMOD bit must be configured to 1 and OVR flag should be ignored by the software. An overrun event will not prevent the ADC from continuing to convert and the ADC_DR register will always contain the latest conversion. Managing conversions using the DMA Since converted channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one channel. This avoids the loss of the data already stored in the ADC_DR register. When the DMA mode is enabled (DMAEN bit set to 1 in the ADC_CFGR register in single ADC mode or MDMA different from 0b00 in dual ADC mode), a DMA request is generated after each conversion of a channel. This allows the transfer of the converted data from the ADC_DR register to the destination location selected by the software. Despite this, if an overrun occurs (OVR=1) because the DMA could not serve the DMA transfer request in time, the ADC stops generating DMA requests and the data corresponding to the new conversion is not transferred by the DMA. Which means that all the data transferred to the RAM can be considered as valid. Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten (refer to Section : ADC overrun (OVR, OVRMOD)). The DMA transfer requests are blocked until the software clears the OVR bit. Two different DMA modes are proposed depending on the application use and are configured with bit DMACFG of the ADC_CFGR register in single ADC mode, or with bit DMACFG of the ADC_CCR register in dual ADC mode: • DMA one shot mode (DMACFG=0). This mode is suitable when the DMA is programmed to transfer a fixed number of data. • DMA circular mode (DMACFG=1) This mode is suitable when programming the DMA in circular mode. DMA one shot mode (DMACFG=0) In this mode, the ADC generates a DMA transfer request each time a new conversion data is available and stops generating DMA requests once the DMA has reached the last DMA transfer (when DMA_EOT interrupt occurs - refer to DMA paragraph) even if a conversion has been started again. When the DMA transfer is complete (all the transfers configured in the DMA controller have been done): • The content of the ADC data register is frozen. • Any ongoing conversion is aborted with partial result discarded. • No new DMA request is issued to the DMA controller. This avoids generating an overrun error if there are still conversions which are started. • Scan sequence is stopped and reset. • The DMA is stopped. RM0394 Rev 4 415/1600 485 Analog-to-digital converters (ADC) RM0394 DMA circular mode (DMACFG=1) In this mode, the ADC generates a DMA transfer request each time a new conversion data is available in the data register, even if the DMA has reached the last DMA transfer. This allows configuring the DMA in circular mode to handle a continuous analog input data stream. 16.4.27 Managing conversions using the DFSDM The ADC conversion results can be transferred directly to the Digital filter for sigma delta modulators (DFSDM). In this case, the DFSDMCFG bit must be set to 1 and DMAEN bit must be cleared to 0. The ADC transfers all the 16 bits of the regular data register data to the DFSDM and resets the EOC flag once the transfer is complete. The data format must be 16-bit signed: ADC_DR[15:12] = sign extended ADC_DR[11] = sign ADC_DR[11:0] = data To obtain 16-bit signed format in 12-bit ADC mode, the software needs to configure the OFFSETy[11:0] to 0x800 after having set OFFSETy_EN to 1. Only right aligned data format is available for the DFSDM interface (see Figure 69: Right alignment (offset enabled, signed value)). 16.4.28 Dynamic low-power features Auto-delayed conversion mode (AUTDLY) The ADC implements an auto-delayed conversion mode controlled by the AUTDLY configuration bit. Auto-delayed conversions are useful to simplify the software as well as to optimize performance of an application clocked at low frequency where there would be risk of encountering an ADC overrun. When AUTDLY=1, a new conversion can start only if all the previous data of the same group has been treated: • For a regular conversion: once the ADC_DR register has been read or if the EOC bit has been cleared (see Figure 73). • For an injected conversion: when the JEOS bit has been cleared (see Figure 74). This is a way to automatically adapt the speed of the ADC to the speed of the system which will read the data. The delay is inserted after each regular conversion (whatever DISCEN=0 or 1) and after each sequence of injected conversions (whatever JDISCEN=0 or 1). Note: There is no delay inserted between each conversions of the injected sequence, except after the last one. During a conversion, a hardware trigger event (for the same group of conversions) occurring during this delay is ignored. 416/1600 RM0394 Rev 4 RM0394 Note: Analog-to-digital converters (ADC) This is not true for software triggers where it remains possible during this delay to set the bits ADSTART or JADSTART to restart a conversion: it is up to the software to read the data before launching a new conversion. No delay is inserted between conversions of different groups (a regular conversion followed by an injected conversion or conversely): • If an injected trigger occurs during the automatic delay of a regular conversion, the injected conversion starts immediately (see Figure 74). • Once the injected sequence is complete, the ADC waits for the delay (if not ended) of the previous regular conversion before launching a new regular conversion (see Figure 76). The behavior is slightly different in auto-injected mode (JAUTO=1) where a new regular conversion can start only when the automatic delay of the previous injected sequence of conversion has ended (when JEOS has been cleared). This is to ensure that the software can read all the data of a given sequence before starting a new sequence (see Figure 77). To stop a conversion in continuous auto-injection mode combined with autodelay mode (JAUTO=1, CONT=1 and AUTDLY=1), follow the following procedure: 1. Wait until JEOS=1 (no more conversions are restarted) 2. Clear JEOS, 3. Set ADSTP=1 4. Read the regular data. If this procedure is not respected, a new regular sequence can restart if JEOS is cleared after ADSTP has been set. In AUTDLY mode, a hardware regular trigger event is ignored if it occurs during an already ongoing regular sequence or during the delay that follows the last regular conversion of the sequence. It is however considered pending if it occurs after this delay, even if it occurs during an injected sequence of the delay that follows it. The conversion then starts at the end of the delay of the injected sequence. In AUTDLY mode, a hardware injected trigger event is ignored if it occurs during an already ongoing injected sequence or during the delay that follows the last injected conversion of the sequence. RM0394 Rev 4 417/1600 485 Analog-to-digital converters (ADC) RM0394 Figure 73. AUTODLY=1, regular conversion in continuous mode, software trigger $'67$57 (2& (26 $'673 $'&B'5UHDGDFFHVV $'&VWDWH &+ 5'< '/< $'&B'5 &+ ' E\VZ '/< '/< &+ ' &+ '/< 6723 ' 5'< ' E\KZ ,QGLFDWLYHWLPLQJV 069 1. AUTDLY=1 2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, CHANNELS = 1,2,3 3. Injected configuration DISABLED Figure 74. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0; JDISCEN=0) 1RWLJQRUHG RFFXUVGXULQJLQMHFWHGVHTXHQFH ,JQRUHG 5HJXODU WULJJHU $'&VWDWH 5'< &+ '/< &+ '/< &+ UHJXODU UHJXODU '/< &+ &+ &+ LQMHFWHG UHJXODU '/< &+ &+ '/< '/< &+ UHJXODU UHJXODU LQMHFWHG '/< &+ '/< &+ (2& (26 $'&B'5 UHDGDFFHVV ' $'&B'5 ' ' ' ,JQRUHG ,QMHFWHG WULJJHU '/< LQM -(26 ' $'&B-'5 ' $'&B-'5 E\VZ E\KZ ,QGLFDWLYHWLPLQJV 069 1. AUTDLY=1 2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=0, CHANNELS = 1, 2, 3 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=0, CHANNELS = 5,6 418/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Figure 75. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=1, JDISCEN=1) 1RWLJQRUHG RFFXUVGXULQJLQMHFWHGVHTXHQFH ,JQRUHG 5HJXODU WULJJHU $'& VWDWH 5'< &+ UHJXODU &+ '/< 5'< &+ '/< 5'< &+ 5'< &+ '/< 5'< &+ '/< 5'<&+ UHJXODU UHJXODU LQMHFWHG LQMHFWHG UHJXODU UHJXODU '/< &+ '/< &+ '/< &+ '/< &+ (2& (26 $'&B'5UHDGDFFHVV $'&B'5 ' ' ,JQRUHG ,QMHFWHG WULJJHU ' ' ,JQRUHG '/< LQM -(26 $'&B-'5 ' ' $'&B-'5 E\VZ ,QGLFDWLYHWLPLQJV E\KZ 069 1. AUTDLY=1 2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=1, DISCNUM=1, CHANNELS = 1, 2, 3. 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=1, CHANNELS = 5,6 RM0394 Rev 4 419/1600 485 Analog-to-digital converters (ADC) RM0394 Figure 76. AUTODLY=1, regular continuous conversions interrupted by injected conversions $'67$57 $'& VWDWH 5'< &+ &+ '/< UHJXODU '/< UHJXODU &+ &+ LQMHFWHG LQMHFWHG '/< &+ '/< &+ '/< &+ UHJXODU '/< &+ UHJXODU '/< &+ (2& (26 $'&B'5UHDGDFFHVV ' $'&B'5 ' ' ,JQRUHG ,QMHFWHG WULJJHU '/< LQM -(26 $'&B-'5 ' $'&B-'5 ' E\VZ E\KZ ,QGLFDWLYHWLPLQJV 069 1. AUTDLY=1 2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2, 3 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=0, CHANNELS = 5,6 Figure 77. AUTODLY=1 in auto- injected mode (JAUTO=1) ^dZd;ϭͿ ƐƚĂƚĞ EŽĚĞůĂLJ Zz ,ϭ >z;,ϭͿ ,Ϯ ƌĞŐƵůĂƌ ƌĞŐƵůĂƌ ,ϱ ŝŶũĞĐƚĞĚ ,ϲ >z;ŝŶũͿ >z;,ϮͿ ,ϯ ƌĞŐƵůĂƌ ŝŶũĞĐƚĞĚ >z ,ϭ ƌĞŐƵůĂƌ K K^ ͺZƌĞĂĚĂĐĐĞƐƐ ͺZ ϭ Ϯ ϯ :K^ ͺ:Zϭ ϱ ϲ ͺ:ZϮ ďLJƐͬǁ ďLJŚͬǁ /ŶĚŝĐĂƚŝǀĞƚŝŵŝŶŐƐ D^ϯϭϬϮϰsϯ 1. AUTDLY=1 2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2 3. Injected configuration: JAUTO=1, CHANNELS = 5,6 420/1600 RM0394 Rev 4 RM0394 16.4.29 Analog-to-digital converters (ADC) Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) The three AWD analog watchdogs monitor whether some channels remain within a configured voltage range (window). Figure 78. Analog watchdog guarded area $QDORJYROWDJH +LJKHUWKUHVKROG +75 *XDUGHGDUHD /RZHUWKUHVKROG /75 DL AWDx flag and interrupt An interrupt can be enabled for each of the 3 analog watchdogs by setting AWDxIE in the ADC_IER register (x=1,2,3). AWDx (x=1,2,3) flag is cleared by software by writing 1 to it. The ADC conversion result is compared to the lower and higher thresholds before alignment. Description of analog watchdog 1 The AWD analog watchdog 1 is enabled by setting the AWD1EN bit in the ADC_CFGR register. This watchdog monitors whether either one selected channel or all enabled channels(1) remain within a configured voltage range (window). Table 63 shows how the ADC_CFGR registers should be configured to enable the analog watchdog on one or more channels. Table 63. Analog watchdog channel selection Channels guarded by the analog watchdog AWD1SGL bit AWD1EN bit JAWD1EN bit None x 0 0 All injected channels 0 0 1 All regular channels 0 1 0 All regular and injected channels 0 1 1 1 0 1 1 1 0 1 1 1 (1) Single injected channel Single(1) regular channel (1) Single regular or injected channel 1. Selected by the AWD1CH[4:0] bits. The channels must also be programmed to be converted in the appropriate regular or injected sequence. The AWD1 analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold. RM0394 Rev 4 421/1600 485 Analog-to-digital converters (ADC) RM0394 These thresholds are programmed in bits HT1[11:0] and LT1[11:0] of the ADC_TR1 register for the analog watchdog 1. When converting data with a resolution of less than 12 bits (according to bits RES[1:0]), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned). Table 64 describes how the comparison is performed for all the possible resolutions for analog watchdog 1. Table 64. Analog watchdog 1 comparison Resolution (bit RES[1:0]) Analog watchdog comparison between: Comments Raw converted data, (1) left aligned Thresholds 00: 12-bit DATA[11:0] LT1[11:0] and HT1[11:0] - 01: 10-bit DATA[11:2],00 LT1[11:0] and HT1[11:0] User must configure LT1[1:0] and HT1[1:0] to 00 10: 8-bit DATA[11:4],0000 LT1[11:0] and HT1[11:0] User must configure LT1[3:0] and HT1[3:0] to 0000 11: 6-bit DATA[11:6],0000 LT1[11:0] and 00 HT1[11:0] User must configure LT1[5:0] and HT1[5:0] to 000000 1. The watchdog comparison is performed on the raw converted data before any alignment calculation and before applying any offsets (the data which is compared is not signed). Description of analog watchdog 2 and 3 The second and third analog watchdogs are more flexible and can guard several selected channels by programming the corresponding bits in AWDCHx[19:0] (x=2,3). The corresponding watchdog is enabled when any bit of AWDCHx[19:0] (x=2,3) is set. They are limited to a resolution of 8 bits and only the 8 MSBs of the thresholds can be programmed into HTx[7:0] and LTx[7:0]. Table 65 describes how the comparison is performed for all the possible resolutions. Table 65. Analog watchdog 2 and 3 comparison Analog watchdog comparison between: Resolution (bits RES[1:0]) Raw converted data, left aligned(1) Comments Thresholds 00: 12-bit DATA[11:4] LTx[7:0] and HTx[7:0] DATA[3:0] are not relevant for the comparison 01: 10-bit DATA[11:4] LTx[7:0] and HTx[7:0] DATA[3:2] are not relevant for the comparison 10: 8-bit DATA[11:4] LTx[7:0] and HTx[7:0] - 11: 6-bit DATA[11:6],00 LTx[7:0] and HTx[7:0] User must configure LTx[1:0] and HTx[1:0] to 00 1. The watchdog comparison is performed on the raw converted data before any alignment calculation and before applying any offsets (the data which is compared is not signed). 422/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) ADCy_AWDx_OUT signal output generation Each analog watchdog is associated to an internal hardware signal ADCy_AWDx_OUT (y=ADC number, x=watchdog number) which is directly connected to the ETR input (external trigger) of some on-chip timers. Refer to the on-chip timers section to understand how to select the ADCy_AWDx_OUT signal as ETR. ADCy_AWDx_OUT is activated when the associated analog watchdog is enabled: Note: • ADCy_AWDx_OUT is set when a guarded conversion is outside the programmed thresholds. • ADCy_AWDx_OUT is reset after the end of the next guarded conversion which is inside the programmed thresholds (It remains at 1 if the next guarded conversions are still outside the programmed thresholds). • ADCy_AWDx_OUT is also reset when disabling the ADC (when setting ADDIS=1). Note that stopping regular or injected conversions (setting ADSTP=1 or JADSTP=1) has no influence on the generation of ADCy_AWDx_OUT. AWDx flag is set by hardware and reset by software: AWDx flag has no influence on the generation of ADCy_AWDx_OUT (ex: ADCy_AWDx_OUT can toggle while AWDx flag remains at 1 if the software did not clear the flag). Figure 79. ADCy_AWDx_OUT signal generation (on all regular channels) $'& 67$7( 5'< &RQYHUVLRQ LQVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ LQVLGH &RQYHUVLRQ &RQYHUVLRQ RXWVLGH RXWVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ LQVLGH (2&)/$* $:'[)/$* FOHDUHG E\6: FOHDUHG E\6: FOHDUHG E\6: FOHDUHG E\6: $'&\B$:'[B287 &RQYHUWLQJUHJXODUFKDQQHOV 5HJXODUFKDQQHOVDUHDOOJXDUGHG 069 RM0394 Rev 4 423/1600 485 Analog-to-digital converters (ADC) RM0394 Figure 80. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by software) $'& 67$7( 5'< &RQYHUVLRQ &RQYHUVLRQ LQVLGH &RQYHUVLRQ RXWVLGH LQVLGH &RQYHUVLRQ &RQYHUVLRQ RXWVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ RXWVLGH LQVLGH (2&)/$* QRWFOHDUHG E\6: $:'[)/$* $'&\B$:'[B287 &RQYHUWLQJUHJXODUFKDQQHOV 5HJXODUFKDQQHOVDUHDOOJXDUGHG 069 Figure 81. ADCy_AWDx_OUT signal generation (on a single regular channel) $'& &RQYHUVLRQ 67$7( RXWVLGH &RQYHUVLRQ &RQYHUVLRQ &RQYHUVLRQ &RQYHUVLRQ LQVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ &RQYHUVLRQ RXWVLGH (2&)/$* (26)/$* FOHDUHG E\6: $:'[)/$* FOHDUHG E\6: $'&\B$:'[B287 &RQYHUWLQJUHJXODUFKDQQHOVDQG 2QO\FKDQQHOLVJXDUGHG 069 Figure 82. ADCy_AWDx_OUT signal generation (on all injected channels) $'& 67$7( 5'< &RQYHUVLRQ LQVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ &RQYHUVLRQ LQVLGH RXWVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ RXWVLGH &RQYHUVLRQ LQVLGH -(26)/$* $:'[)/$* FOHDUHG E\6: FOHDUHG E\6: FOHDUHG E\6: FOHDUHG E\6: $'&\B$:'[B287 &RQYHUWLQJWKHLQMHFWHGFKDQQHOV $OOLQMHFWHGFKDQQHOVDUHJXDUGHG 069 424/1600 RM0394 Rev 4 RM0394 16.4.30 Analog-to-digital converters (ADC) Oversampler The oversampling unit performs data pre-processing to offload the CPU. It is able to handle multiple conversions and average them into a single data with increased data width, up to 16-bit. It provides a result with the following form, where N and M can be adjusted: n = N–1 1 Result = ----- × M ∑ Conversion(t n) n=0 It allows to perform by hardware the following functions: averaging, data rate reduction, SNR improvement, basic filtering. The oversampling ratio N is defined using the OVFS[2:0] bits in the ADC_CFGR2 register, and can range from 2x to 256x. The division coefficient M consists of a right bit shift up to 8 bits, and is defined using the OVSS[3:0] bits in the ADC_CFGR2 register. The summation unit can yield a result up to 20 bits (256x 12-bit results), which is first shifted right. It is then truncated to the 16 least significant bits, rounded to the nearest value using the least significant bits left apart by the shifting, before being finally transferred into the ADC_DR data register. Note: If the intermediary result after the shifting exceeds 16-bit, the result is truncated as is, without saturation. Figure 83. 20-bit to 16-bit result truncation 5DZELWGDWD 6KLIWLQJ 7UXQFDWLRQDQGURXQGLQJ 069 The Figure 84 gives a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result. Figure 84. Numerical example with 5-bit shift and rounding 5DZELWGDWD )LQDOUHVXOWDIWHUELWVKLIW DQGURXQGLQJWRQHDUHVW % ' ' % ) 069 Table 66 gives the data format for the various N and M combinations, for a raw conversion data equal to 0xFFF. RM0394 Rev 4 425/1600 485 Analog-to-digital converters (ADC) RM0394 Table 66. Maximum output results versus N and M (gray cells indicate truncation) Over Max sampling Raw data ratio No-shift OVSS = 0000 1-bit shift OVSS = 0001 2-bit shift OVSS = 0010 3-bit shift OVSS = 0011 4-bit shift OVSS = 0100 5-bit shift OVSS = 0101 6-bit shift OVSS = 0110 7-bit shift OVSS = 0111 8-bit shift OVSS = 1000 2x 0x1FFE 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x020 4x 0x3FFC 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 8x 0x7FF8 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 16x 0xFFF0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 32x 0x1FFE0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 64x 0x3FFC0 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 128x 0x7FF80 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 256x 0xFFF00 0xFF00 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF There are no changes for conversion timings in oversampled mode: the sample time is maintained equal during the whole oversampling sequence. A new data is provided every N conversions, with an equivalent delay equal to N x TCONV = N x (tSMPL + tSAR). The flags are set as follow: • the end of the sampling phase (EOSMP) is set after each sampling phase • the end of conversion (EOC) occurs once every N conversions, when the oversampled result is available • the end of sequence (EOS) occurs once the sequence of oversampled data is completed (i.e. after N x sequence length conversions total) ADC operating modes supported when oversampling (single ADC mode) In oversampling mode, most of the ADC operating modes are maintained: Note: • Single or continuous mode conversions • ADC conversions start either by software or with triggers • ADC stop during a conversion (abort) • Data read via CPU or DMA with overrun detection • Low-power modes (AUTDLY) • Programmable resolution: in this case, the reduced conversion values (as per RES[1:0] bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the same way as 12-bit conversions are The alignment mode is not available when working with oversampled data. The ALIGN bit in ADC_CFGR1 is ignored and the data are always provided right-aligned. Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is set, the value of the OFFSETy_EN bit in ADC_OFRy register is ignored (considered as reset). 426/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Analog watchdog The analog watchdog functionality is maintained (AWDSGL and AWDEN bits), with the following difference: Note: – the RES[1:0] bits are ignored, comparison is always done on using the full 12-bit values HT[11:0] and LT[11:0] – the comparison is performed on the most significant 12-bit of the 16-bit oversampled results ADC_DR[15:4] Care must be taken when using high shifting values, this will reduce the comparison range. For instance, if the oversampled result is shifted by 4 bits, thus yielding a 12-bit data rightaligned, the effective analog watchdog comparison can only be performed on 8 bits. The comparison is done between ADC_DR[11:4] and HT[0:7] / LT[[0:7], and HT[11:8] / LT[11:8] must be kept reset. Triggered mode The averager can also be used for basic filtering purpose. Although not a very powerful filter (slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject constant parasitic frequencies (typically coming from the mains or from a switched mode power supply). For this purpose, a specific discontinuous mode can be enabled with TROVS bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a user and independent from the conversion time itself. The Figure 85 below shows how conversions are started in response to triggers during discontinuous mode. If the TROVS bit is set, the content of the DISCEN bit is ignored and considered as 1. Figure 85. Triggered regular oversampling mode (TROVS bit = 1) &217 ',6&(1 75296 7ULJJHU &K 1 7ULJJHU &K 1 &K 1 &K 1 &K 1 &K 1 &K 1 &K 1 (2&IODJVHW &217 ',6&(1 75296 7ULJJHU &K 1 7ULJJHU &K 1 7ULJJHU &K 1 7ULJJHU &K 1 7ULJJHU &K 1 7ULJJHU &K 1 7ULJJHU &K 1 (2&IODJVHW 069 Injected and regular sequencer management when oversampling In oversampling mode, it is possible to have differentiated behavior for injected and regular sequencers. The oversampling can be enabled for both sequencers with some limitations if they have to be used simultaneously (this is related to a unique accumulation unit). RM0394 Rev 4 427/1600 485 Analog-to-digital converters (ADC) RM0394 Oversampling regular channels only The regular oversampling mode bit ROVSM defines how the regular oversampling sequence is resumed if it is interrupted by injected conversion: • in continued mode, the accumulation restarts from the last valid data (prior to the conversion abort request due to the injected trigger). This ensures that oversampling will be completed whatever the injection frequency (providing at least one regular conversion can be completed between triggers); • in resumed mode, the accumulation restarts from 0 (previous conversions results are ignored). This mode allows to guarantee that all data used for oversampling were converted back-to-back within a single timeslot. Care must be taken to have a injection trigger period above the oversampling period length. If this condition is not respected, the oversampling cannot be completed and the regular sequencer will be blocked. The Figure 86 gives examples for a 4x oversampling ratio. Figure 86. Regular oversampling modes (4x ratio) 2YHUVDPSOLQJ VWRSSHG 5HJXODUFKDQQHOV &K 1 &K 1 &K 1 &K 1 &K 0 7ULJJHU 2YHUVDPSOLQJ FRQWLQXHG &K 0 $ERUW ,QMHFWHGFKDQQHOV &K - &K 0 &K 0 &K 0 &K 2 &K 0 &K 0 &K . -(2& &RQWLQXHGPRGH5296( -296( 52960 75296 ; 2YHUVDPSOLQJ DERUWHG 5HJXODUFKDQQHOV &K 1 &K 1 &K 1 &K 1 &K 0 7ULJJHU 2YHUVDPSOLQJ UHVXPHG &K 0 $ERUW ,QMHFWHGFKDQQHOV &K - &K 0 &K 0 &K . -(2& 5HVXPHGPRGH5296( -296( 52960 75296 ; 069 Oversampling Injected channels only The Injected oversampling mode bit JOVSE enables oversampling solely for conversions in the injected sequencer. 428/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Oversampling regular and Injected channels It is possible to have both ROVSE and JOVSE bits set. In this case, the regular oversampling mode is forced to resumed mode (ROVSM bit ignored), as represented on Figure 87 below. Figure 87. Regular and injected oversampling modes used simultaneously 2YHUVDPSOLQJ DERUWHG 5HJXODUFKDQQHOV &K 1 &K 1 &K 1 &K 1 &K 0 7ULJJHU 2YHUVDPSOLQJ UHVXPHG &K 0 $ERUW ,QMHFWHGFKDQQHOV &K - &K 0 &K - &K - &K - &K 0 -(2& 5296( -296( 52960 ;75296 069 Triggered regular oversampling with injected conversions It is possible to have triggered regular mode with injected conversions. In this case, the injected mode oversampling mode must be disabled, and the ROVSM bit is ignored (resumed mode is forced). The JOVSE bit must be reset. The behavior is represented on Figure 88 below. Figure 88. Triggered regular oversampling with injection 2YHUVDPSOLQJ UHVXPHG 7ULJJHU 5HJXODUFKDQQHOV &K 1 7ULJJHU &K 1 7ULJJHU 7ULJJHU 7ULJJHU &K 1 $ERUW ,QMHFWHGFKDQQHOV &K - 7ULJJHU &K 1 &K . 5296( -296( 52960 ;75296 069 RM0394 Rev 4 429/1600 485 Analog-to-digital converters (ADC) RM0394 Auto-injected mode It is possible to oversample auto-injected sequences and have all conversions results stored in registers to save a DMA resource. This mode is available only with both regular and injected oversampling active: JAUTO = 1, ROVSE = 1 and JOVSE = 1, other combinations are not supported. The ROVSM bit is ignored in auto-injected mode. The Figure 89 below shows how the conversions are sequenced. Figure 89. Oversampling in auto-injected mode 5HJXODUFKDQQHOV 1 1 1 1 1 1 1 1 ,QMHFWHGFKDQQHOV , , , , - - - - . . . . / / / / -$872 5296( -296( 52960 ;75296 069 It is possible to have also the triggered mode enabled, using the TROVS bit. In this case, the ADC must be configured as following: JAUTO = 1, DISCEN = 0, JDISCEN = 0, ROVSE = 1, JOVSE = 1 and TROVSE = 1. Dual ADC modes supported when oversampling It is possible to have oversampling enabled when working in dual ADC configuration, for the injected simultaneous mode and regular simultaneous mode. In this case, the two ADCs must be programmed with the very same settings (including oversampling). All other dual ADC modes are not supported when either regular or injected oversampling is enabled (ROVSE = 1 or JOVSE = 1). Combined modes summary The Table 67 below summarizes all combinations, including modes not supported. Table 67. Oversampler operating modes summary Regular Injected Oversampling Oversampling ROVSE JOVSE Oversampler mode ROVSM Triggered Regular mode 0 = continued TROVS Comment 1 = resumed 430/1600 1 0 0 0 Regular continued mode 1 0 0 1 Not supported 1 0 1 0 Regular resumed mode 1 0 1 1 Triggered regular resumed mode 1 1 0 X Not supported 1 1 1 0 Injected and regular resumed mode 1 1 1 1 Not supported 0 1 X X Injected oversampling RM0394 Rev 4 RM0394 16.4.31 Analog-to-digital converters (ADC) Dual ADC modes Dual ADC modes can be used in devices with two ADCs or more (see Figure 90). In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADCx master to the ADC slave, depending on the mode selected by the bits DUAL[4:0] in the ADCx_CCR register. Four possible modes are implemented: • Injected simultaneous mode • Regular simultaneous mode • Interleaved mode • Alternate trigger mode It is also possible to use these modes combined in the following ways: • Injected simultaneous mode + Regular simultaneous mode • Regular simultaneous mode + Alternate trigger mode • Injected simultaneous mode + Interleaved mode In dual ADC mode (when bits DUAL[4:0] in ADCx_CCR register are not equal to zero), the bits CONT, AUTDLY, DISCEN, DISCNUM[2:0], JDISCEN, JQM, JAUTO of the ADC_CFGR register are shared between the master and slave ADC: the bits in the slave ADC are always equal to the corresponding bits of the master ADC. To start a conversion in dual mode, the user must program the bits EXTEN, EXTSEL, JEXTEN, JEXTSEL of the master ADC only, to configure a software or hardware trigger, and a regular or injected trigger. (the bits EXTEN[1:0] and JEXTEN[1:0] of the slave ADC are don’t care). In regular simultaneous or interleaved modes: once the user sets bit ADSTART or bit ADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically set. However, bit ADSTART or bit ADSTP of the slave ADC is not necessary cleared at the same time as the master ADC bit. In injected simultaneous or alternate trigger modes: once the user sets bit JADSTART or bit JADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically set. However, bit JADSTART or bit JADSTP of the slave ADC is not necessary cleared at the same time as the master ADC bit. In dual ADC mode, the converted data of the master and slave ADC can be read in parallel, by reading the ADC common data register (ADCx_CDR). The status bits can be also read in parallel by reading the dual-mode status register (ADCx_CSR). RM0394 Rev 4 431/1600 485 Analog-to-digital converters (ADC) RM0394 Figure 90. Dual ADC block diagram(1) ZĞŐƵůĂƌĚĂƚĂƌĞŐŝƐƚĞƌ;ϭϲͲ ďŝƚƐͿ /ŶũĞĐƚĞĚĚĂƚĂƌĞŐŝƐƚĞƌƐ;ϰ džϭϲͲďŝƚƐͿ ,QWHUQDODQDORJLQSXWV $'&[B,11 $'&[B,13 $'&[B,11 $'&[B,13 ĚĚƌĞƐƐͬĚĂƚĂďƵƐ ZĞŐƵůĂƌ ĐŚĂŶŶĞůƐ 6ODYH$'& /ŶũĞĐƚĞĚ ĐŚĂŶŶĞůƐ ,QWHUQDOWULJJHUV ZĞŐƵůĂƌĚĂƚĂƌĞŐŝƐƚĞƌ;ϭϲͲ ďŝƚƐͿ $'&[B,11 $'&[B,13 /ŶũĞĐƚĞĚĚĂƚĂƌĞŐŝƐƚĞƌƐ;ϰ džϭϲͲďŝƚƐͿ ,QWHUQDODQDORJLQSXWV ZĞŐƵůĂƌ ĐŚĂŶŶĞůƐ /ŶũĞĐƚĞĚ ĐŚĂŶŶĞůƐ ƵĂůŵŽĚĞ ĐŽŶƚƌŽů 6WDUWWULJJHUPX[ UHJXODUJURXS 0DVWHU$'& 6WDUWWULJJHUPX[ LQMHFWHGJURXS 06Y9 432/1600 1. External triggers also exist on slave ADC but are not shown for the purposes of this diagram. 2. The ADC common data register (ADCx_CDR) contains both the master and slave ADC regular converted data. RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Injected simultaneous mode This mode is selected by programming bits DUAL[4:0]=00101 This mode converts an injected group of channels. The external trigger source comes from the injected group multiplexer of the master ADC (selected by the JEXTSEL bits in the ADC_JSQR register). Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel). In simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the longer of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. Regular conversions can be performed on one or all ADCs. In that case, they are independent of each other and are interrupted when an injected event occurs. They are resumed at the end of the injected conversion group. • At the end of injected sequence of conversion event (JEOS) on the master ADC, the converted data is stored into the master ADC_JDRy registers and a JEOS interrupt is generated (if enabled) • At the end of injected sequence of conversion event (JEOS) on the slave ADC, the converted data is stored into the slave ADC_JDRy registers and a JEOS interrupt is generated (if enabled) • If the duration of the master injected sequence is equal to the duration of the slave injected one (like in Figure 91), it is possible for the software to enable only one of the two JEOS interrupt (ex: master JEOS) and read both converted data (from master ADC_JDRy and slave ADC_JDRy registers). Figure 91. Injected simultaneous mode on 4 channels: dual ADC mode 0$67(5$'& &+ &+ &+ &+ 6/$9($'& &+ &+ &+ &+ 7ULJJHU 6DPSOLQJ (QGRILQMHFWHGVHTXHQFHRQ 0$67(5DQG6/$9($'& &RQYHUVLRQ 069 If JDISCEN=1, each simultaneous conversion of the injected sequence requires an injected trigger event to occur. This mode can be combined with AUTDLY mode: • Once a simultaneous injected sequence of conversions has ended, a new injected trigger event is accepted only if both JEOS bits of the master and the slave ADC have been cleared (delay phase). Any new injected trigger events occurring during the ongoing injected sequence and the associated delay phase are ignored. • Once a regular sequence of conversions of the master ADC has ended, a new regular trigger event of the master ADC is accepted only if the master data register (ADC_DR) has been read. Any new regular trigger events occurring for the master ADC during the RM0394 Rev 4 433/1600 485 Analog-to-digital converters (ADC) RM0394 ongoing regular sequence and the associated delay phases are ignored. There is the same behavior for regular sequences occurring on the slave ADC. Regular simultaneous mode with independent injected This mode is selected by programming bits DUAL[4:0] = 00110. This mode is performed on a regular group of channels. The external trigger source comes from the regular group multiplexer of the master ADC (selected by the EXTSEL bits in the ADC_CFGR register). A simultaneous trigger is provided to the slave ADC. In this mode, independent injected conversions are supported. An injection request (either on master or on the slave) will abort the current simultaneous conversions, which are restarted once the injected conversion is completed. Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel). In regular simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the longer conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. Software is notified by interrupts when it can read the data: • At the end of each conversion event (EOC) on the master ADC, a master EOC interrupt is generated (if EOCIE is enabled) and software can read the ADC_DR of the master ADC. • At the end of each conversion event (EOC) on the slave ADC, a slave EOC interrupt is generated (if EOCIE is enabled) and software can read the ADC_DR of the slave ADC. • If the duration of the master regular sequence is equal to the duration of the slave one (like in Figure 92), it is possible for the software to enable only one of the two EOC interrupt (ex: master EOC) and read both converted data from the Common Data register (ADCx_CDR). It is also possible to read the regular data using the DMA. Two methods are possible: • • Note: 434/1600 Using two DMA channels (one for the master and one for the slave). In this case bits MDMA[1:0] must be kept cleared. – Configure the DMA master ADC channel to read ADC_DR from the master. DMA requests are generated at each EOC event of the master ADC. – Configure the DMA slave ADC channel to read ADC_DR from the slave. DMA requests are generated at each EOC event of the slave ADC. Using MDMA mode, which leaves one DMA channel free for other uses: – Configure MDMA[1:0]=0b10 or 0b11 (depending on resolution). – A single DMA channel is used (the one of the master). Configure the DMA master ADC channel to read the common ADC register (ADCx_CDR) – A single DMA request is generated each time both master and slave EOC events have occurred. At that time, the slave ADC converted data is available in the upper half-word of the ADCx_CDR 32-bit register and the master ADC converted data is available in the lower half-word of ADCx_CCR register. – both EOC flags are cleared when the DMA reads the ADCx_CCR register. In MDMA mode (MDMA[1:0]=0b10 or 0b11), the user must program the same number of conversions in the master’s sequence as in the slave’s sequence. Otherwise, the remaining conversions will not generate a DMA request. RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Figure 92. Regular simultaneous mode on 16 channels: dual ADC mode 0$67(5$'& 6/$9($'& &+ &+ &+ &+ &+ &+ &+ &+ &+ &+ 7ULJJHU 6DPSOLQJ (QGRIUHJXODUVHTXHQFHRQ 0$67(5DQG6/$9($'& &RQYHUVLRQ DLE If DISCEN=1 then each “n” simultaneous conversions of the regular sequence require a regular trigger event to occur (“n” is defined by DISCNUM). This mode can be combined with AUTDLY mode: • Once a simultaneous conversion of the sequence has ended, the next conversion in the sequence is started only if the common data register, ADCx_CDR (or the regular data register of the master ADC) has been read (delay phase). • Once a simultaneous regular sequence of conversions has ended, a new regular trigger event is accepted only if the common data register (ADCx_CDR) has been read (delay phase). Any new regular trigger events occurring during the ongoing regular sequence and the associated delay phases are ignored. It is possible to use the DMA to handle data in regular simultaneous mode combined with AUTDLY mode, assuming that multi-DMA mode is used: bits MDMA must be set to 0b10 or 0b11. When regular simultaneous mode is combined with AUTDLY mode, it is mandatory for the user to ensure that: Note: • The number of conversions in the master’s sequence is equal to the number of conversions in the slave’s. • For each simultaneous conversions of the sequence, the length of the conversion of the slave ADC is inferior to the length of the conversion of the master ADC. Note that the length of the sequence depends on the number of channels to convert and the sampling time and the resolution of each channels. This combination of regular simultaneous mode and AUTDLY mode is restricted to the use case when only regular channels are programmed: it is forbidden to program injected channels in this combined mode. Interleaved mode with independent injected This mode is selected by programming bits DUAL[4:0] = 00111. This mode can be started only on a regular group (usually one channel). The external trigger source comes from the regular channel multiplexer of the master ADC. After an external trigger occurs: • The master ADC starts immediately. • The slave ADC starts after a delay of several ADC clock cycles after the sampling phase of the master ADC has complete. The minimum delay which separates 2 conversions in interleaved mode is configured in the DELAY bits in the ADCx_CCR register. This delay starts to count after the end of the sampling phase of the master conversion. This way, an ADC cannot start a conversion if the RM0394 Rev 4 435/1600 485 Analog-to-digital converters (ADC) RM0394 complementary ADC is still sampling its input (only one ADC can sample the input signal at a given time). • The minimum possible DELAY is 1 to ensure that there is at least one cycle time between the opening of the analog switch of the master ADC sampling phase and the closing of the analog switch of the slave ADC sampling phase. • The maximum DELAY is equal to the number of cycles corresponding to the selected resolution. However the user must properly calculate this delay to ensure that an ADC does not start a conversion while the other ADC is still sampling its input. If the CONT bit is set on both master and slave ADCs, the selected regular channels of both ADCs are continuously converted. The software is notified by interrupts when it can read the data at the end of each conversion event (EOC) on the slave ADC. A slave and master EOC interrupts are generated (if EOCIE is enabled) and the software can read the ADC_DR of the slave/master ADC. Note: It is possible to enable only the EOC interrupt of the slave and read the common data register (ADCx_CDR). But in this case, the user must ensure that the duration of the conversions are compatible to ensure that inside the sequence, a master conversion is always followed by a slave conversion before a new master conversion restarts. It is recommended to use the MDMA mode. It is also possible to have the regular data transferred by DMA. In this case, individual DMA requests on each ADC cannot be used and it is mandatory to use the MDMA mode, as following: • Configure MDMA[1:0]=0b10 or 0b11 (depending on resolution). • A single DMA channel is used (the one of the master). Configure the DMA master ADC channel to read the common ADC register (ADCx_CDR). • A single DMA request is generated each time both master and slave EOC events have occurred. At that time, the slave ADC converted data is available in the upper half-word of the ADCx_CDR 32-bit register and the master ADC converted data is available in the lower half-word of ADCx_CCR register. • Both EOC flags are cleared when the DMA reads the ADCx_CCR register. Figure 93. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode 0$67(5$'& &+ &+ 6/$9($'& 7ULJJHU &+ $'&&/. F\FOHV $'&&/. F\FOHV &+ (QGRIFRQYHUVLRQRQPDVWHUDQG VODYH$'& 6DPSOLQJ &RQYHUVLRQ 06Y9 436/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Figure 94. Interleaved mode on 1 channel in single conversion mode: dual ADC mode 0$67(5$'& &+ &+ 6/$9($'& 7ULJJHU &+ &+ $'&&/. F\FOHV (QGRIFRQYHUVLRQRQ PDVWHUDQGVODYH$'& $'&&/. F\FOHV (QGRIFRQYHUVLRQRQ PDVWHUDQGVODYH$'& 6DPSOLQJ &RQYHUVLRQ 06Y9 If DISCEN=1, each “n” simultaneous conversions (“n” is defined by DISCNUM) of the regular sequence require a regular trigger event to occur. In this mode, injected conversions are supported. When injection is done (either on master or on slave), both the master and the slave regular conversions are aborted and the sequence is restarted from the master (see Figure 95 below). Figure 95. Interleaved conversion with injection ,QMHFWHGWULJJHU 5HVXPH DOZD\VRQPDVWHU &+ $'& PDVWHU &+ $'& VODYH &+ &+ &+ UHDG &'5 /HJHQG 6DPSOLQJ &+ &+ &+ UHDG &'5 &+ &+ FRQYHUVLRQV DERUWHG &+ &+ UHDG &'5 &+ UHDG &'5 &RQYHUVLRQ 069 Alternate trigger mode This mode is selected by programming bits DUAL[4:0] = 01001. This mode can be started only on an injected group. The source of external trigger comes from the injected group multiplexer of the master ADC. This mode is only possible when selecting hardware triggers: JEXTEN must not be 0x0. Injected discontinuous mode disabled (JDISCEN=0 for both ADC) 1. When the 1st trigger occurs, all injected master ADC channels in the group are converted. 2. When the 2nd trigger occurs, all injected slave ADC channels in the group are converted. 3. And so on. RM0394 Rev 4 437/1600 485 Analog-to-digital converters (ADC) RM0394 A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in the group have been converted. A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the group have been converted. JEOC interrupts, if enabled, can also be generated after each injected conversion. If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts by converting the injected channels of the master ADC in the group. Figure 96. Alternate trigger: injected group of each ADC -(2&RQ PDVWHU$'& VWWULJJHU -(2&RQ PDVWHU$'& -(2&-(26RQ PDVWHU$'& 0$67(5$'& 6/$9($'& QGWULJJHU -(2&RQ VODYH$'& UGWULJJHU -(2&RQ VODYH$'& -(2&-(26RQ VODYH$'& -(2&RQ PDVWHU$'& -(2&RQ PDVWHU$'& -(2&-(26RQ PDVWHU$'& 0$67(5$'& 6/$9($'& WKWULJJHU -(2&RQ VODYH$'& -(2&RQ VODYH$'& -(2&-(26RQ VODYH$'& 6DPSOLQJ &RQYHUVLRQ DLP Note: Regular conversions can be enabled on one or all ADCs. In this case the regular conversions are independent of each other. A regular conversion is interrupted when the ADC has to perform an injected conversion. It is resumed when the injected conversion is finished. The time interval between 2 trigger events must be greater than or equal to 1 ADC clock period. The minimum time interval between 2 trigger events that start conversions on the same ADC is the same as in the single ADC mode. Injected discontinuous mode enabled (JDISCEN=1 for both ADC) If the injected discontinuous mode is enabled for both master and slave ADCs: • When the 1st trigger occurs, the first injected channel of the master ADC is converted. • When the 2nd trigger occurs, the first injected channel of the slave ADC is converted. • And so on. A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in the group have been converted. 438/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the group have been converted. JEOC interrupts, if enabled, can also be generated after each injected conversions. If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts. Figure 97. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode VWWULJJHU UGWULJJHU WKWULJJHU WKWULJJHU -(2&-(26RQ -(2&RQ -(2&RQ -(2&RQ PDVWHU$'& PDVWHU$'& PDVWHU$'& PDVWHU$'& 0$67(5$'& 6/$9($'& -(2&RQ PDVWHU$'& QGWULJJHU -(2&RQ PDVWHU$'& WKWULJJHU -(2&RQ PDVWHU$'& WKWULJJHU WKWULJJHU -(2&-(26RQ PDVWHU$'& 6DPSOLQJ &RQYHUVLRQ DL9P Combined regular/injected simultaneous mode This mode is selected by programming bits DUAL[4:0] = 00001. It is possible to interrupt the simultaneous conversion of a regular group to start the simultaneous conversion of an injected group. Note: In combined regular/injected simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the long conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. Combined regular simultaneous + alternate trigger mode This mode is selected by programming bits DUAL[4:0]=00010. It is possible to interrupt the simultaneous conversion of a regular group to start the alternate trigger conversion of an injected group. Figure 98 shows the behavior of an alternate trigger interrupting a simultaneous regular conversion. The injected alternate conversion is immediately started after the injected event. If a regular conversion is already running, in order to ensure synchronization after the injected conversion, the regular conversion of all (master/slave) ADCs is stopped and resumed synchronously at the end of the injected conversion. Note: In combined regular simultaneous + alternate trigger mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the long conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions. RM0394 Rev 4 439/1600 485 Analog-to-digital converters (ADC) RM0394 Figure 98. Alternate + regular simultaneous VWWULJJHU $'&0$67(5UHJ &+ &+ &+ &+ &+ &+ &+ &+ &+ &+ &+ $'&0$67(5LQM $'&6/$9(UHJ &+ &+ &+ &+ &+ $'&6/$9(LQM V\QFKURQRWORVW QGWULJJHU DL9P If a trigger occurs during an injected conversion that has interrupted a regular conversion, the alternate trigger is served. Figure 99 shows the behavior in this case (note that the 6th trigger is ignored because the associated alternate conversion is not complete). Figure 99. Case of trigger occurring during injected conversion VWWULJJHU $'&0$67(5UHJ &+ &+ &+ &+ $'&0$67(5LQM $'&6/$9(UHJ $'&6/$9(LQM UGWULJJHU &+ &+ &+ &+ &+ &+ &+ &+ WKWULJJHU &+ &+ &+ &+ &+ &+ &+ &+ &+ &+ WKWULJJHU QGWULJJHU &+ WKWULJJHU LJQRUHG DL9 Combined injected simultaneous plus interleaved This mode is selected by programming bits DUAL[4:0]=00011 It is possible to interrupt an interleaved conversion with a simultaneous injected event. Caution: 440/1600 In this case the interleaved conversion is interrupted immediately and the simultaneous injected conversion starts. At the end of the injected sequence the interleaved conversion is resumed. When the interleaved regular conversion resumes, the first regular conversion which is performed is alway the master’s one. Figure 100, Figure 101 and Figure 102 show the behavior using an example. In this mode, it is mandatory to use the Common Data Register to read the regular data with a single read access. On the contrary, master-slave data coherency is not guaranteed. RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Figure 100. Interleaved single channel CH0 with injected sequence CH11, CH12 $'& PDVWHU &+ &+ $'& VODYH &+ &+ &RQYHUVLRQV DERUWHG &+ UHDG &'5 &+ &+ UHDG &'5 &+ &+ &+ &+ &+ &+ &+ &+ UHDG &'5 &+ UHDG &'5 /HJHQG ,QMHFWHGWULJJHU 6DPSOLQJ 5HVXPH DOZD\VUHVWDUWZLWKWKHPDVWHU &RQYHUVLRQ 069 Figure 101. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 1: Master interrupted first $'& PDVWHU &+ &+ $'& VODYH &+ &+ &RQYHUVLRQV DERUWHG &+ UHDG &'5 &+ &+ UHDG &'5 &+ &+ &+ &+ &+ &+ &+ &+ UHDG &'5 &+ UHDG &'5 /HJHQG ,QMHFWHGWULJJHU 6DPSOLQJ 5HVXPH DOZD\VUHVWDUWZLWKWKHPDVWHU &RQYHUVLRQ 069 Figure 102. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 2: Slave interrupted first $'& PDVWHU &+ $'& VODYH &+ &+ &+ &+ UHDG &'5 &RQYHUVLRQV DERUWHG &+ UHDG &'5 &+ &+ &+ &+ &+ &+ &+ &+ &+ UHDG &'5 &+ UHDG &'5 /HJHQG ,QMHFWHGWULJJHU 6DPSOLQJ &RQYHUVLRQ 5HVXPH DOZD\VUHVWDUWZLWKWKHPDVWHU 069 RM0394 Rev 4 441/1600 485 Analog-to-digital converters (ADC) RM0394 DMA requests in dual ADC mode In all dual ADC modes, it is possible to use two DMA channels (one for the master, one for the slave) to transfer the data, like in single mode (refer to Figure 103: DMA Requests in regular simultaneous mode when MDMA=0b00). Figure 103. DMA Requests in regular simultaneous mode when MDMA=0b00 7ULJJHU $'&0DVWHUUHJXODU 7ULJJHU &+ &+ $'&0DVWHU(2& $'&6ODYHUHJXODU &+ &+ $'&6ODYH(2& '0$UHTXHVWIURP$'&0DVWHU '0$UHDGV0DVWHU $'&B'5 '0$UHDGV0DWHU $'&B'5 '0$UHTXHVWIURP$'&6ODYH '0$UHDGV6ODYH $'&B'5 '0$UHDGV6ODYH $'&B'5 &RQILJXUDWLRQZKHUHHDFKVHTXHQFHFRQWDLQVRQO\RQHFRQYHUVLRQ 06Y9 In simultaneous regular and interleaved modes, it is also possible to save one DMA channel and transfer both data using a single DMA channel. For this MDMA bits must be configured in the ADCx_CCR register: • MDMA=0b10: A single DMA request is generated each time both master and slave EOC events have occurred. At that time, two data items are available and the 32-bit register ADCx_CDR contains the two half-words representing two ADC-converted data items. The slave ADC data take the upper half-word and the master ADC data take the lower half-word. This mode is used in interleaved mode and in regular simultaneous mode when resolution is 10-bit or 12-bit. Example: Interleaved dual mode: a DMA request is generated each time 2 data items are available: 1st DMA request: ADCx_CDR[31:0] = SLV_ADC_DR[15:0] | MST_ADC_DR[15:0] 2nd DMA request: ADCx_CDR[31:0] = SLV_ADC_DR[15:0] | MST_ADC_DR[15:0] 442/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Figure 104. DMA requests in regular simultaneous mode when MDMA=0b10 7ULJJHU 7ULJJHU &+ $'&0DVWHUUHJXODU 7ULJJHU &+ 7ULJJHU &+ &+ $'&6ODYH(2& &+ &+ &+ $'&6ODYHUHJXODU &+ $'&6ODYH(2& '0$UHTXHVWIURP $'&0DVWHU '0$UHTXHVWIURP $'&6ODYH &RQILJXUDWLRQZKHUHHDFKVHTXHQFHFRQWDLQVRQO\RQHFRQYHUVLRQ 06Y9 Figure 105. DMA requests in interleaved mode when MDMA=0b10 7ULJJHU $'&0DVWHUUHJXODU $'&0DVWHU(2& $'&6ODYHUHJXODU 7ULJJHU &+ &+ &+ &+ &+ 'HOD\ 'HOD\ 'HOD\ 'HOD\ &+ 7ULJJHU 7ULJJHU 7ULJJHU &+ &+ 'HOD\ &+ &+ $'&6ODYH(2& '0$UHTXHVWIURP $'&0DVWHU '0$UHTXHVWIURP $'&6ODYH &RQILJXUDWLRQZKHUHHDFKVHTXHQFHFRQWDLQVRQO\RQHFRQYHUVLRQ 06Y9 RM0394 Rev 4 443/1600 485 Analog-to-digital converters (ADC) Note: RM0394 When using MDMA mode, the user must take care to configure properly the duration of the master and slave conversions so that a DMA request is generated and served for reading both data (master + slave) before a new conversion is available. • MDMA=0b11: This mode is similar to the MDMA=0b10. The only differences are that on each DMA request (two data items are available), two bytes representing two ADC converted data items are transferred as a half-word. This mode is used in interleaved and regular simultaneous mode when resolution is 6bit or when resolution is 8-bit and data is not signed (offsets must be disabled for all the involved channels). Example: Interleaved dual mode: a DMA request is generated each time 2 data items are available: 1st DMA request: ADCx_CDR[15:0] = SLV_ADC_DR[7:0] | MST_ADC_DR[7:0] 2nd DMA request: ADCx_CDR[15:0] = SLV_ADC_DR[7:0] | MST_ADC_DR[7:0] Overrun detection In dual ADC mode (when DUAL[4:0] is not equal to b00000), if an overrun is detected on one of the ADCs, the DMA requests are no longer issued to ensure that all the data transferred to the RAM are valid (this behavior occurs whatever the MDMA configuration). It may happen that the EOC bit corresponding to one ADC remains set because the data register of this ADC contains valid data. DMA one shot mode/ DMA circular mode when MDMA mode is selected When MDMA mode is selected (0b10 or 0b11), bit DMACFG of the ADCx_CCR register must also be configured to select between DMA one shot mode and circular mode, as explained in section Section : Managing conversions using the DMA (bits DMACFG of master and slave ADC_CFGR are not relevant). Stopping the conversions in dual ADC modes The user must set the control bits ADSTP/JADSTP of the master ADC to stop the conversions of both ADC in dual ADC mode. The other ADSTP control bit of the slave ADC has no effect in dual ADC mode. Once both ADC are effectively stopped, the bits ADSTART/JADSTART of the master and slave ADCs are both cleared by hardware. 16.4.32 Temperature sensor The temperature sensor can be used to measure the junction temperature (Tj) of the device. The temperature sensor is internally connected to the ADC input channels which are used to convert the sensor output voltage to a digital value. When not in use, the sensor can be put in power down mode. It support the temperature range –40 to 125 °C. Figure 106 shows the block diagram of connections between the temperature sensor and the ADC. The temperature sensor output voltage changes linearly with temperature. The offset of this line varies from chip to chip due to process variation (up to 45 °C from one chip to another). 444/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) The uncalibrated internal temperature sensor is more suited for applications that detect temperature variations instead of absolute temperatures. To improve the accuracy of the temperature sensor measurement, calibration values are stored in system memory for each device by ST during production. During the manufacturing process, the calibration data of the temperature sensor and the internal voltage reference are stored in the system memory area. The user application can then read them and use them to improve the accuracy of the temperature sensor or the internal reference (refer to the datasheet for additional information). The temperature sensor is internally connected to the ADC input channel which is used to convert the sensor’s output voltage to a digital value. Refer to the electrical characteristics section of the device datasheet for the sampling time value to be applied when converting the internal temperature sensor. When not in use, the sensor can be put in power-down mode. Figure 106 shows the block diagram of the temperature sensor. The dac_out1 signal and the temperature sensor share the same input. Figure 106. Temperature sensor channel block diagram &RQYHUWHG GDWD &+6(/FRQWUROELW 7HPSHUDWXUH VHQVRU 976 $'&[ $'&&+ LQSXW $GGUHVVGDWDEXV GDFBRXW 06Y9 Reading the temperature To use the sensor: 1. Select the ADC input channels which is connected to VTS. 2. Program with the appropriate sampling time (refer to electrical characteristics section of the device datasheet). 3. Set the CH17SEL bit in the ADCx_CCR register to wake up the temperature sensor from power-down mode. 4. Start the ADC conversion. 5. Read the resulting VTS data in the ADC data register. 6. Calculate the actual temperature using the following formula: RM0394 Rev 4 445/1600 485 Analog-to-digital converters (ADC) RM0394 TS_CAL2_TEMP – TS_CAL1_TEMP Temperature ( in °C ) = -------------------------------------------------------------------------------------------------- × ( TS_DATA – TS_CAL1 ) + 30 °C TS_CAL2 – TS_CAL1 Where: • TS_CAL2 is the temperature sensor calibration value acquired at TS_CAL2_TEMP. • TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP. • TS_DATA is the actual temperature sensor output value converted by ADC. Refer to the device datasheet for more information about TS_CAL1 and TS_CAL2 calibration points. Note: The sensor has a startup time after waking from power-down mode before it can output VTS at the correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADEN and CH17SEL bits should be set at the same time. 16.4.33 VBAT supply monitoring The CH18SEL bit in the ADCx_CCR register is used to switch to the battery voltage. As the VBAT voltage could be higher than VDDA, to ensure the correct operation of the ADC, the VBAT pin is internally connected to a bridge divider by 3. This bridge is automatically enabled when CH18SEL is set, to connect VBAT/3 to the ADC input channels. As a consequence, the converted digital value is one third of the VBAT voltage. To prevent any unwanted consumption on the battery, it is recommended to enable the bridge divider only when needed, for ADC conversion. Refer to the electrical characteristics of the device datasheet for the sampling time value to be applied when converting the VBAT/3 voltage. The figure below shows the block diagram of the VBAT sensing feature. The dac_out2 signal and VBAT sensing input share the same input. 446/1600 RM0394 Rev 4 RM0394 Analog-to-digital converters (ADC) Figure 107. VBAT channel block diagram GDFBRXW &+6(/ $'&[ 9%$7 $GGUHVVGDWDEXV 9%$7 $'&LQSXW 06Y9 1. The CH18SEL bit must be set to enable the conversion of internal channel for VBAT/3. 16.4.34 Monitoring the internal voltage reference It is possible to monitor the internal voltage reference (VREFINT) to have a reference point for evaluating the ADC VREF+ voltage level. The internal voltage reference is internally connected to the input channel 0 of the ADC1 (ADC1_INP0). Refer to the electrical characteristics section of the product datasheet for the sampling time value to be applied when converting the internal voltage reference voltage. Figure 108 shows the block diagram of the VREFINT sensing feature. Figure 108. VREFINT channel block diagram 95()(1FRQWUROELW $'&[ ,QWHUQDO SRZHUEORFN 95(),17 $'&LQSXW 06Y9 1. The VREFEN bit into ADCx_CCR register must be set to enable the conversion of internal channels (VREFINT). RM0394 Rev 4 447/1600 485 Analog-to-digital converters (ADC) RM0394 Calculating the actual VDDA voltage using the internal reference voltage The VDDA power supply voltage applied to the microcontroller may be subject to variation or not precisely known. The embedded internal voltage reference (VREFINT) and its calibration data acquired by the ADC during the manufacturing process at VDDA = 3.0 V can be used to evaluate the actual VDDA voltage level. The following formula gives the actual VDDA voltage supplying the device: VDDA = 3.0 V x VREFINT_CAL / VREFINT_DATA where: • VREFINT_CAL is the VREFINT calibration value • VREFINT_DATA is the actual VREFINT output value converted by ADC Converting a supply-relative ADC measurement to an absolute voltage value The ADC is designed to deliver a digital value corresponding to the ratio between the analog power supply and the voltage applied on the converted channel. For most application use cases, it is necessary to convert this ratio into a voltage independent of VDDA. For applications where VDDA is known and ADC converted values are right-aligned you can use the following formula to get this absolute value: V DDA V CHANNELx = ------------------------------------- × ADCx_DATA FULL_SCALE For applications where VDDA value is not known, you must use the internal voltage reference and VDDA can be replaced by the expression provided in Calculating the actual VDDA voltage using the internal reference voltage, resulting in the following formula: 3.0 V × VREFINT_CAL × ADCx_DATA V CHANNELx = -------------------------------------------------------------------------------------------------------VREFINT_DATA × FULL_SCALE Where: Note: 448/1600 • VREFINT_CAL is the VREFINT calibration value • ADC_DATA is the value measured by the ADC on channel x (right-aligned) • VREFINT_DATA is the actual VREFINT output value converted by the ADC • FULL_SCALE is the maximum digital value of the ADC output. For example with 12-bit resolution, it will be 212 − 1 = 4095 or with 8-bit resolution, 28 − 1 = 255. If ADC measurements are done using an output format other than 12 bit right-aligned, all the parameters must first be converted to a compatible format before the calculation is done. RM0394 Rev 4 RM0394 16.5 Analog-to-digital converters (ADC) ADC interrupts For each ADC, an interrupt can be generated: • after ADC power-up, when the ADC is ready (flag ADRDY) • on the end of any conversion for regular groups (flag EOC) • on the end of a sequence of conversion for regular groups (flag EOS) • on the end of any conversion for injected groups (flag JEOC) • on the end of a sequence of conversion for injected groups (flag JEOS) • when an analog watchdog detection occurs (flag AWD1, AWD2 and AWD3) • when the end of sampling phase occurs (flag EOSMP) • when the data overrun occurs (flag OVR) • when the injected sequence context queue overflows (flag JQOVF) Separate interrupt enable bits are available for flexibility. Table 68. ADC interrupts per each ADC Interrupt event Event flag Enable control bit ADRDY ADRDYIE End of conversion of a regular group EOC EOCIE End of sequence of conversions of a regular group EOS EOSIE End of conversion of a injected group JEOC JEOCIE End of sequence of conversions of an injected group JEOS JEOSIE Analog watchdog 1 status bit is set AWD1 AWD1IE Analog watchdog 2 status bit is set AWD2 AWD2IE Analog watchdog 3 status bit is set AWD3 AWD3IE EOSMP EOSMPIE OVR OVRIE JQOVF JQOVFIE ADC ready End of sampling phase Overrun Injected context queue overflows RM0394 Rev 4 449/1600 485 Analog-to-digital converters (ADC) 16.6 RM0394 ADC registers (for each ADC) Refer to Section 1.2 on page 60 for a list of abbreviations used in register descriptions. 16.6.1 ADC interrupt and status register (ADC_ISR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. AWD2 AWD1 JEOS JEOC OVR EOS EOC rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 JQOVF AWD3 rc_w1 rc_w1 EOSMP ADRDY rc_w1 rc_w1 Bits 31:11 Reserved, must be kept at reset value. Bit 10 JQOVF: Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to Section 16.4.21: Queue of context for injected conversions for more information. 0: No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software) 1: Injected context queue overflow has occurred Bit 9 AWD3: Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT3[7:0] and HT3[7:0] of ADC_TR3 register. It is cleared by software writing 1 to it. 0: No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software) 1: Analog watchdog 3 event occurred Bit 8 AWD2: Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT2[7:0] and HT2[7:0] of ADC_TR2 register. It is cleared by software writing 1 to it. 0: No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software) 1: Analog watchdog 2 event occurred Bit 7 AWD1: Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT1[11:0] and HT1[11:0] of ADC_TR1 register. It is cleared by software. writing 1 to it. 0: No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software) 1: Analog watchdog 1 event occurred Bit 6 JEOS: Injected