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COMPAL CONFIDENTIAL
MODEL NAME : 888L2(SOLANO2-M)
Date: 01/11/01
Version: 2.0

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

Cover Sheet
Size

Document Number

Rev
2.0

888L2 Main Board
Date:

T h ursday, January 11, 2001

Sheet

1

of

42

MODEL NAME : 888L2 (SOLANO2-M)
UPGA2
Socket

Decoupling
CapacitorS
PAGE 4,5,6

FSB BUS

PAGE 13

CRT CONN.

PAGE 12

LCD/INV. CONN.

PAGE 6

GMCH2-M
IDSEL: AD11

LVDS

VCH

DISPLAY CACHE CONN. & ITP

PAGE 12

HOST-HUB BRIDGE

DVO/Vlink

IDSEL: AD13

PAGE 13

CLOCK
CIRCUIT

SODIMM 0
SODIMM 1

MEMORY BUS

INTERNAL GFX
PAGE 7,8,9

PAGE 10

HUB_ILNK

PCI BUS

PAGE 11

CARD-BUS
CONTROLLER
OZ 6933T
IDSEL: AD19
PIRQA#, PIRQC#

ICH2-M

MINI_PCI CONN

AC_LINK1/LAN

MODEM/LAN
PIRQB#, PIRQD#

PAGE 17

HUB, LPC, IDE, USB, SMBUS,
AC'97

IDSEL: AD27, AD28

PAGE 19

HDD CONN.

BUS#0, DEV#30, DEV#31:

PAGE 29

DC/DC
CIRCUIT

SECOND MODULE
CONN. PAGE 17

BUS#1, DEV#8:

INTERNAL LAN CONTROLLER
PAGE 14,15,16

PCCARD
POWER
PAGE 20

CARDBUS
SLOT 1/2

RJ11

PAGE 20

CD-ROM
CONN. PAGE 17

RJ45

PAGE 30-34

Sub board

USB CONN.

PAGE 18

FWH
PAGE 14

AC_LINK0

AMP & AC97
CODECPAGE 27

LPC BUS
KB BIOS
PAGE 22

PAGE 25

NS PC87570EXT
KBD

RTC BATT &
ON/OFF BTN

X Bus

NS PC87393
LPC-TO-X Bus
& S/IO

PAGE 22

INT KBD

Head
Phone

Line in

Mic

PAGE 28

PAGE 28

PAGE 28

PAGE 21

PAGE 23

PS/2
KEYBOARD&
MOUSECONN.
PAGE 25

T-PAD
CONN.

SUSPEND
CKT

PAGE 23

PAGE 26

SIO

PIO

FDD.

PAGE 24

PAGE 24

PAGE 17

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

System Block Diagram
Size

Document Number

Rev
2.0

888L2 Main Board
Date:

T h ursday, January 11, 2001

Sheet

2

of

42

Revision History
#

Date

1

2000/7/21

First Release

Description
(EVT-SST)

Version
0.1

2

2000/9/20

Second Release

(DVT1-PT1)

0.2A

3

2000/11/3

Third Release

(DVT2-PT2)

0.2C1

4

2000/12/27 Fouth Release

(ST)

1B

5

2001/01/11 fifth release

(QT)

2.0

Chip information

EVT

GMCH2-M FW82815EM

GMCH2-M
ICH2-M
VCH

QA38ES (A0)
Q967ES (B0)
Q989ES (A0)

DVT1 (PT1)
GMCH2-M
ICH2-M
VCH

DVT2
(PT2)
QA75ES (A1)
QA57ES (B2)
Q076ES (A1)

ST
GMCH2-M
ICH2-M
VCH

A1
B2
A2

Version

S-spec.

A0
A1

Q-spec.
QA38

SL4MP

QA75

ICH2-M FW82801BAM
Version

S-spec.

A0

Q-spec.
Q908, Q909, Q910, Q911, Q912

B0

SL45HQ

Q967, Q968

B1

SL4HN

QA36, QA37

B2

(SST)

QT same as ST

QA56, QA57

VCH FW82807AA
Version
A0

S-spec.

Q-spec.
Q989

A1

QA76

A2

QB41ES

Compal Electronics, Inc.
Title

Revision History
Size

Document Number

Rev
2.0

888L2 Main Board
Date:

T h ursday, January 11, 2001

Sheet

3

of

42

D

HD[0..63]

HD#[0..63]

E

<7>

CPU_VID[0..4]

U5A

<7>
<7>
<7>
<7>
<7>

+CPU_IO

2

3

T2
V4
V2
W3
W5
W2

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

R26
10K_0402

AB2

<7> ADS#

AA1
AB1
Y2
E6
V21
AD9

1

BSEL0

+CPU_IO

2

10_0402 2

R105
@10K_0402

1

<7> HIT#
<7> HITM#
<7> DEFER#

2

<7> HTRDY#
<7> RS#0
<7> RS#1
<7> RS#2

2
R210
1
2
3
4
R100 2
R101 2

+2_5V_CLK

RP32
+CPU_IO

<14> A20M#
<14> FERR#
<14> IGNNE#
<14> CPU_PWRGD
<14> SMI#
1
1.5K
8 8P4R-1.5K
7
6
5
1 1.5K
1 56.2_1%

<14> INTR
<14> NMI
<14> STPCLK#

C6
U4
T4
R1

AA21
Y21
W21
W19
U2
U1
AA2
W1
Y1

R104
100_0402

2

R217

V1
Y4
U3

1

BSEL1

1

<7> BPRI#
<7> BNR#
<7> HLOCK#

FERR#

ITP_TDO
ITP_TDI
ITP_TMS
ITP_TRST#
ITP_TCK
ITP_PREQ#
GTL_PRDY#
BSEL0
BSEL1

AD10
AC12
AC13
V5
AB10
AC15
AD13
AD14
AA14
AA11
AB20
W20
AA12
AB15

RCPUSLP#

AB18
AC19
AC11
AB12

THERMDA
THERMDC

AA15
AB16

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
RP#
ADS#

AERR#
AP0#
AP1#
BERR#
BINIT#
IERR#

ERROR
SIGNALS

BREQ0#
BPRI#
BNR#
LOCK#

ARBITRATION
PHASE
SIGNALS

HIT#
HITM#
DEFER#

SNOOP PHASE

BP2#
BP3#
BPM0#
BPM1#
TRDY#
RS0#
RS1#
RS2#
RSP#

RESPONSE
PHASE
SIGNALS

A20M#
FERR#
IGNNE#
PWRGOOD
SMI#

PC
C O MPATIBILITY
SIGNALS

TDO
TDI
TMS
TRST#
TCK
PREQ#
PRDY#
BSEL0
BSEL1

DIAGNOSTIC
& TEST
SIGNALS

INTR/LINT0
NMI/LINT1
STPCLK#
SLP#

EXECUTION
CONTROL
SIGNALS

THERMDA
THERMDC

THERMAL DIODE

SIGNALS

DATA
PHASE
SIGNALS

DEP0#
DEP1#
DEP2#
DEP3#
DEP4#
DEP5#
DEP6#
DEP7#
DBSY#
DRDY#

INIT#
FLUSH#
RESET#
BCLK
EDGCTRLN

R_VID0
R_VID1
R_VID2
R_VID3
R_VID4

4
8
14
18
22
1
13

R19
1K_0402

BE#

VCC

BX

GND

5
9
15
19
23
24

DBSY#
DRDY#

AA18
Y20
AB21

PICD1_CPU
PICD0_CPU

AA10
AC9
A6

FLUSH#
CPURST#

1
@33_0402

.1UF

R103
R99

M3

2
2

CPU VCC

00000
00001
00010
00011

2.00
1.95
1.90
1.85

10000
10001
10010
10011

1.275
1.250
1.225
1.200

* 850MHZ

00100
00101
00110
00111
01000

1.80
1.75
1.70
1.65
1.60

10100
10101
10110
10111
11000

1.175
1.150
1.125
1.100
1.075

*

01001
01010
01011
01100
01101

1.55
1.50
1.45
1.40
1.35

11001
11010
11011
11100
11101

1.050
1.025
1.000
0.975
0.950

01110
01111

1.30
NO CPU

11110
11111

0.925
NO CPU

3

2

+3VS

0_0402
0_0402

PICD1
PICD0

C L K_APIC_CPU
PICD1 <14>
PICD0 <14>

<11>

INIT# <14>
CPURST#

<15,30>

VID[4:0]

2
@15PF

1
1

VR_HI/LO#

CPU VCC

<7>
<7>

1
C97

C22

VID[4:0]

* 900MHZ

AA3
T1

+5VS

12

VR_HI/LO#

<7,13>

CLK_HOST_CPU

<11>

C312
2200PF

R214
@33_0402

+3VS

R261
110_1%

1
R245

2
10K_0402

C310
MAX1617A
16
13 NC
9 NC
5 NC
1 NC
NC
THERMDA
3
DXP

.1UF

THERMDC

4

DXN

R246 1K_0402
1
2
1
2
R258
1K_0402

U20

SMBC
SMBD
ALERT#

14
12
11

SMB_EC_CK1
SMB_EC_DA1

<12,22,23,31>
<12,22,23,31>

Address: 1001_110x

11

COPPERMINE

D0
D1
D2
D3
D4

SN74CBT3383

V20
T21
U21
R21
V18
P21
P20
U19

AA16

B0
B1
B2
B3
B4

VID0
VID1
VID2
VID3
VID4

R24
1K_0402

R18
R27
@1K_0402 R22
1K_0402
1K_0402

2
R102
PICCLK
PICD1
PICD0

8
7
6
5
2
R429
@0_0402

2
6
10
16
20

1

REQUEST
PHASE
SIGNALS

4

VCH_VID[0..4]
<12>
VID[0..4]
<30>

2

RCPUSLP#

1
2
3
4
1

C0
C1
C2
C3
C4

2

1.5K

RP42
8P4R-0
VCH_VID0
VCH_VID1
VCH_VID2
VCH_VID3
VCH_VID4

A0
A1
A2
A3
A4

GND
GND

1

CPU_VID4

8
7

R293 2

2
1K

15

FERR#

<5>

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3

VCC

1.5K

2

1

2

3
7
11
17
21

1

R44

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4

1

PICD1_CPU

2

150

1
R20

+3VS

2

2

2

PICD0_CPU

R106 1

8
7
6
5

1

FLUSH#

150

2

1.5K

2

1

2

1
2
3
4

2
@10K

CPU_VID[0..4]

RP41
8P4R-1K

U4

2

1

R107 1

+3VS

VCH_VID[0..4]
VID[0..4]

1

CPURST#

+3VS

RP40
8P4R-10K
8
7
6
5

1
R30

2

56.2_1%

1
2
3
4

1

R42

2

COPPERMINE

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

1

R243 1

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#

D10
D11
C7
C8
B9
A9
C10
B11
C12
B13
A14
B12
E12
B16
A13
D13
D15
D12
B14
E14
C13
A19
B17
A18
C17
D17
C18
B19
D18
B20
A20
B21
D19
C21
E18
C20
F19
D20
D21
H18
F18
J18
F21
E20
H19
E21
J20
H21
L18
G20
P18
G21
K18
K21
M18
L21
R19
K19
T20
J21
L20
M19
U18
R18

2

+CPU_IO
4

L3
K3
J2
L4
L1
K5
K1
J1
J3
K4
G1
H1
E4
F1
F4
F2
E1
C4
D3
D1
E2
D5
D4
C3
C1
B3
A3
B2
C2
A4
A5
B4
C5

2

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

STBY#

<7> HA#[3..31]

C

ADD0
ADD1

B

HA#[3..31]

10
6

A

1

1

1

C209

*

S T S E M BUS FREQUENCY

00

66MHZ

01

100MHZ

10

RESERVED

11

133MHZ

<13> ITP_TDO
<13> ITP_TDI
<13> ITP_TMS
<13> ITP_TRST#
<13> ITP_TCK
<13> ITP_PREQ#
<13> GTL_PRDY#

ITP_TDO
ITP_TDI
ITP_TMS
ITP_TRST#
ITP_TCK
ITP_PREQ#
GTL_PRDY#

@15PF
2

BSEL[1:0]

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

COPPERMINE-A
Size

B

C

D

Rev
2.0

888L2 Main Board
Date:

A

Document Number

T h ursday, January 11, 2001

Sheet
E

4

of

42

A

B

C35

.1UF
+VCCT_VSSA

L2
M2

2

2

2

1

E5
E16
E17
F5
F17
U5
Y17
Y18

C263

.1UF

.1UF
2

C250

.1UF
2

C339
2

2

1

1

1

C336
.1UF

4

H8
H10
H12
H14
H16
J7
J9
J11
J13
J15
K8
K10
K12
K14
K16
L7
L9
L11
L13
L15
M8
M10
M12
M14
M16
N7
N9
N11
N13
N15
P8
P10
P12
P14
P16
R7
R9
R11
R13
R15
T8
T10
T12
T14
T16
U7
U9
U11
U13
U15

+CPU_CORE

3

+2_5V_CLK

C34
.1UF

2

C194
.1UF

2

+2_5V_CLK

R209
1.5K_1%

R25

1

VCCA
VSSA

P L L ANALOG VOLTAGE

VREF0
VREF1
VREF2
VREF3
VREF4
VREF5
VREF6
VREF7

COPPERMINE

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49

POWER,
GROUND,
RESERVED
SIGNALS

R28

C217

C205
AB19

2K_1%

.1UF
+CLKREF

P2

1

1

2

.1UF
2

2

.1UF

1

2
1

1

2

1

2K_1%

C208

1K_1%
2

E

U5B

C202

22UF_10V_1206

+GTLREF

R215

D

1

1
C32

10UF_10V_1206

+GTLREF

C

+VCCT_VCCA
1

1
2
L47
Murata LQG21N4R7K10

+CPU_IO

+CMOSREF

R2
AD19

<15> I S T_CPU_PERF#

R2622

+CPU_IO

AA9
AD18

1

+TESTHI

AD17

RSVD
CLKREF

CMOSREF1
CMOSREF2

GHI#
RTTIMPEDP

TESTHI

1.5K

1

1

TESTLO2
R29

56.2_1%

TESTP1
TESTP2
TESTP3
TESTP4

R23

1K_0402 1K_0402
1

R96

1

AD20
H4
AA17
G4

TESTLO1
TESTLO2

2

2

2

TESTLO1

Y5
N5

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101

A2
A7
A8
A12
A21
B1
B5
B6
B7
B8
B10
B15
B18
C9
C11
C15
C16
C19
D2
D6
D7
D9
E3
E7
E8
E9
E10
E11
E13
E19
F3
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F20
G3
G19
H2
H7
H9
H11
H13
H15
H20
J4
J8
J10
J12
J14
J16
J19
K2
K7
K9
K11
K13
K15
K20
L5
L8
L10
L12
L14
L16
L19
M7
M9
M11
M13
M15
M20
N2
N3
N4
N8
N10
N12
N14
N16
N18
N19
N20
P5
P7
P9
P11
P13
P15
P19
R3
R4
R5
R8
R10

U5C
+CPU_IO

+CPU_CORE

<4>
<4>
<4>
<4>
<4>

G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
H6
H17
J6
J17
K6
K17
L6
L17
M6
M17
N6
N17
P1
P6
P17
R6
R17
T6
T17
U6
U17
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
Y6
Y7
Y8
AA6
AA7
AA8
AB6
AB7
AB8
AC6
AC7
AC8
AD6
AD7
AD8

AD2
AD3
AD4
AC4
AB4

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4

VCCT0
VCCT1
VCCT2
VCCT3
VCCT4
VCCT5
VCCT6
VCCT7
VCCT8
VCCT9
VCCT10
VCCT11
VCCT12
VCCT13
VCCT14
VCCT15
VCCT16
VCCT17
VCCT18
VCCT19
VCCT20
VCCT21
VCCT22
VCCT23
VCCT24
VCCT25
VCCT26
VCCT27
VCCT28
VCCT29
VCCT30
VCCT31
VCCT32
VCCT33
VCCT34
VCCT35
VCCT36
VCCT37
VCCT38
VCCT39
VCCT40
VCCT41
VCCT42
VCCT43
VCCT44
VCCT45
VCCT46
VCCT47
VCCT48
VCCT49
VCCT50
VCCT51
VCCT52
VCCT53
VCCT54
VCCT55
VCCT56
VCCT57
VCCT58
VCCT59
VCCT60
VCCT61
VCCT62
VCCT63
VCCT64
VCCT65
VCCT66
VCCT67
VCCT68
VCCT69
VCCT70
VCCT71

VID0
VID1
VID2
VID3
VID4

COPPERMINE

P O W E R , GROUND AND NC

VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155

VSS159
VSS160
VSS161
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24

R12
R14
R16
R20
T3
T5
T7
T9
T11
T13
T15
T18
T19
U8
U10
U12
U14
U16
U20
V3
V19
W4
W18
Y3
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y19
AA4
AA13
AA20
AB3

4

3

AB5
AB9
AB11
AB13
AB14
AB17
AC1
AC2
AC5
AC10
AC14
AC16
AC18
AC21
AD1

AD5
AD16
AD21
A15
A16
A17
C14
D8
D14
D16
E15
G2
G5
G18
H3
H5
J5
M4
M5
P3
P4
AA5
AA19
AC3
AC17
AC20
AD15

2

COPPERMINE

uPGA2 and uBGA2 PIN P1:
f o r low voltage Cumine CPU: connect to +CPU_CORE, only uBGA2 package.
for normal Cumine CPU: connect to +CPU_IO.

1

Compal Electronics, Inc.

COPPERMINE
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

COPPERMINE-B
Size

B

C

D

Rev
2.0

888L2 Main Board
Date:

A

Document Number

T h ursday, January 11, 2001

Sheet
E

5

of

42

A

B

C

D

E

4

4

1

1
C386
220UF_D_4V
6.3V

+

C406
220UF_D_4V
6.3V

+

C184
220UF_D_4V
6.3V

+

C173
220UF_D_4V
6.3V

2

C409
220UF_D_4V
6.3V

+

2
+

2

2

C321
220UF_D_4V
6.3V

1

1

1

1

1

1

+CPU_CORE

1

1
2

C185
220UF_D_4V
6.3V

+

C427
220UF_D_4V
6.3V

+

C183
220UF_D_4V
6.3V

+

C296
220UF_D_4V
6.3V

+

C420
220UF_D_4V
6.3V

3

2

.1UF
2

1

+

C103

.1UF
2

2

C279

C33
220UF_D_4V
6.3V

2

C102

.1UF

2

2

.1UF

+

2

C244

1

1

1
C423

.1UF

1

1

1

1
C271
220UF_D_4V
6.3V

2

C36

1UF
2

2

2

2

1UF

+

2

C237

1

1

1
C391

1UF

C105
220UF_D_4V
6.3V

2

C345

1UF

+

+CPU_CORE

+

3

C113
220UF_D_4V
6.3V

2

C392

1

+CPU_CORE

1

1

+CPU_CORE

+

2

2

C110
220UF_D_4V
6.3V

2

.1UF
2

.1UF
2

.1UF
2

.1UF
2

.1UF
2

10PF
2

10PF
2

2

2

10PF

2

C101

+
10PF

+CPU_CORE

1

C99

1

C31

1

C100

1

C422

1

C381

+CPU_CORE

1

1

C353

1

C332

1

C334

+CPU_CORE

1

1

+CPU_CORE

+CPU_CORE

C342

C343

1

C311

1

1

C285

1

C309

1

C273

1

C300

1

C286

1

1

1

C251

C344

.1UF_0402
.1UF_0402

.1UF_0402
2

.1UF_0402
2

.1UF_0402
2

.1UF_0402
2

.1UF_0402

2

.1UF_0402
2

.1UF_0402
2

.1UF_0402
2

2

.1UF_0402
2

.1UF_0402

C289

2

.1UF_0402

C290

1

1

C291

2

1

.1UF_0402
2

.1UF_0402

C292

2

1

.1UF_0402

2

.1UF_0402

C276

2

C277

1

1

.1UF_0402

2

.1UF_0402
2

2

.1UF_0402

C278

2

C268

1

1

1

+CPU_IO

C267

+CPU_CORE

C256

C272

C249

C55

1

1

1

1
C192

C182

.1UF_0402

+
.1UF_0402

.1UF_0402

.1UF_0402

1UF

1UF

C188
220UF_D_4V

2

.1UF_0402

2

2

2

.1UF_0402

2

2

2

2

.1UF_0402

2

2

2

C337

1

C304

.1UF_0402

1

C302

.1UF_0402

2

2

.1UF_0402

2

C301

1

1

1
C269

.1UF_0402
2

.1UF_0402

2

.1UF_0402
2

.1UF_0402

2

2

2

.1UF_0402

1

C266

C299
.1UF_0402

2

C265

1

1

1
C293

1

C303

1

C305

1

1

C275

1

1

+CPU_IO

C98

1
C421

.1UF

C329

.1UF

.1UF_0402
2

.1UF_0402
2

1

1
C318

.1UF_0402

2

C315

.1UF_0402

2

C330

.1UF_0402

1

1

1

1
C328

.1UF_0402

2

2

2

2

C319

.1UF_0402

2

C320

.1UF_0402

2

C316

1

1

1

+CPU_CORE

C504

1

1

+CPU_CORE

C505
1UF

2

2

1UF

1

1

Compal Electronics, Inc.
Title

CPU BYPASS
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Size

Document Number

Rev
2.0

888L2 Main Board
Date:

T h ursday, January 11, 2001

Sheet
E

6

of

42

5

4

3

2

1

DVO_D[0..11]

DVO_D[0..11]

<12>

U7C
DVO_CLKOUT

B

CPURST#
HLOCK#
DEFER#
ADS#
BNR#
BPRI#
DBSY#
DRDY#
HIT#
HITM#
HTRDY#

HOST

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

AA7

CLK_HOST_GMCH

H3

PCIRST#

AA5
L4
M3
G1
N4
M5
J3
J1
K1
L3
K3
R4
P1
T2
R3
N5
P5
R1
U1
P2
T1
T3
P3
T5
R5
V5
Y2
V3
W1
U4
V2
W3
W4
U5
Y5
Y3
U3
Y1
W5
V1

@18PF
<11>

<12,14,19,21,29>

CPURST# <4,13>
HLOCK# <4>
DEFER# <4>
ADS# <4>
BNR# <4>
BPRI# <4>
DBSY# <4>
DRDY# <4>
HIT# <4>
HITM# <4>
HTRDY# <4>
<13> VGA_LCKE

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

<13> VGA_LCAS#
<13> VGA_LTCLK1

+3VS
1
R195
1
R204

<13> VGA_LTCLK0

2
LTVDA
10K_0402
2
LTVCL
10K_0402

<13> VGA_LRAS#

<13> VGA_LCS#

+3VS
1
R255

2
4.7K_0402

<12> GMBSDA

<12> GMBSCL

H23
N21
T25
Y26

VGA_LMA10
VGA_LMD11
VGA_LMD12
VGA_LMA7
VGA_LCS#
VGA_LMA6
VGA_LMD27
VGA_LMD24

R26
P26
P23
P21
P25
R24
AE26
AD25
AC26

AGP_ADSTB0
AGP_ADSTB#0
AGP_ADSTB1
AGP_ADSTB#1
AGP_SBSTB
AGP_SBSTB#

M22
L23
U22
V23
Y23
AA24

VGA_LMD30

AD26
AB24

VSYNC
HSYNC
RED
GREEN
BLUE

G_C/BE#0/LMA3
G_C/BE#1/LMD10
G_C/BE#2/LMD13
G_C/BE#3/LRAS#
G_FRAME#/LMA10
G_DEVSEL#/LMD11
G_IRDY#/LMD12
G_TRDY#/LMA7
G_STOP#/LCS#
G_PAR/LMA6
G_REQ#/LMD27
G_GNT#
PIPE#/LMD24

HUB

AD_STB0
AD_STB#0
AD_STB1
AD_STB#1
SB_STB
SB_STB#

RS#0
RS#1
RS#2

M1
N1
M2
L5
N3

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

K2
L1
H1

RS#0
RS#1
RS#2

1
R79
HREQ#[0..4]

HREQ#[0..4]

RS#[0..2]

RS#[0..2]

2
4.7K_0402
1
R73

<4>

+AGPREF_2GMCH
2
GRCOMP
36.5_1%
10_0402
R265 1
2

<4>

Place 10 ohm within 0.5" of
GMCH ball 'R22' and route
trace 1.5" to ball 'P22'

J24
J26
G10
R22
P22

C62

D

@10PF

DVO_BL# <12>
DVO_CLKOUT <12>
DVO_CLK# <12>
DVO_CLK <12>
DVO_VSYNC
<12>
DVO_HSYNC <12>
LTVDA <12>
LTVCL <12>

DVO_VSYNC
DVO_HSYNC
LTVDA
LTVCL

AB18
AA18
AE24
Y20
AD23

CLK_DOT_GMCH

AF22
AF23
AD22
AE22
AE23

CRT_VSYNC
CRT_HSYNC
CRT_R
CRT_G
CRT_B

R92

3VDDCCL <13>
MODIFY ON
3VDDCDA <13>
CLK_DOT_GMCH <11>
1

2

6/11

174_1%

CRT_VSYNC <13>
CRT_HSYNC <13>
CRT_R <13>
CRT_G <13>
CRT_B <13>

F22
CLK_HUB_GMCH
H24
HL0
H26
HL1
HL2
H25
G24
HL3
F24
HL4
E26
HL5
E25
HL6
D26
HL7
D25
HL8
D24
HL9
C26
HL10
H21
HL_STB
G25
F26
HL_STB#
H20 +GMCH_HLCOMP 1
R71

C

+1_8VS

R72
300_1%_0402

+HUBREF_GMCH
HL_STB <14>
HL_STB# <14>
2
+1_8VS
36.5_1%

R70
C355
.01UF

SBA0/LMD31
SBA1/LMD25
SBA2/LDQM2
SBA3/LMD26
SBA4/LMD23
SBA5/LWE#
SBA6/LMD22
SBA7/LGM_FRQ_SEL

+3VS
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HLCLK
HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HLREF
HLPSTRB
HLPSTRB#
HLZCOMP

2

VGA_LMA3
VGA_LMD10
VGA_LMD13
VGA_LRAS#

DDCK
DDDA
DCLKREF
IWASTE
IREF

R47
@33_0402

1

RSTIN#

@33_0402
1
2
R296
C408

+GTLREF

DVO_D0
DVO_D1
DVO_D2
DVO_D3
DVO_D4
DVO_D5
DVO_D6
DVO_D7
DVO_D8
DVO_D9
DVO_D10
DVO_D11
DVO_BL#
DVO_CLKOUT

2

HCLKIN

U6
AA10

AD16
AF17
AE17
AD17
AF18
AD18
AF20
AD20
AC20
AF21
AE21
AD21
AB19
AC18
AE19
AF19
AC16
AB17
AA20
AB21

1 1

GTLREFA
GTLREFB

LTVD0
LTVD1
LTVD2
LTVD3
LTVD4
LTVD5
LTVD6
LTVD7
LTVD8
LTVD9
LTVD10
LTVD11
BLANK#
TVCLKIN/STALL
CLKOUT0
CLKOUT1
LTVVSYNC
LTVHSYNC
LTVDA
LTVCK

1

C

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

G_AD0/LDQM0
G_AD1/LMD4
G_AD2/LMD7
G_AD3/LMD3
G_AD4/LMD6
G_AD5/LMD2
G_AD6/LMD5
G_AD7/LMD1
G_AD8/LMD0
G_AD9/LMA4
G_AD10/LDQM1
G_AD11/LMA2
G_AD12/LMD8
G_AD13/LMA5
G_AD14/LMD9
G_AD15/MA1
G_AD16/LMA8
G_AD17/LMD14
G_AD18/LMA11/LBA
G_AD19/LMD15
G_AD20/LMA9
G_AD21/LMD16
G_AD22/LMA0
G_AD23/LMD17
G_AD24/LCKE
G_AD25/LMD18
G_AD26/LCAS#
G_AD27/LMD19
G_AD28/LTCLK1
G_AD29/LMD20
G_AD30/LTCLK0
G_AD31/LMD21

RBF#/LMD30
WBF#
AGPREF
GRCOMP
NC

ST0/LMD28
ST1/LDQM3
ST2/LMD29

LOCLK
LRCLK

AB22
AB25
AB23
AB26
AA22
AA26
Y22
Y25

VGA_LMD31
VGA_LMD25
VGA_LDQM2
VGA_LMD26
VGA_LMD23
VGA_LWE#
VGA_LMD22
VGA_LFSEL

AD24
AC24
AC23

VGA_LMD28
VGA_LDQM3
VGA_LMD29

2

D

AA1
AB2
AF2
AD4
AB1
AB3
AA3
AC4
AC1
AF3
AD1
AE3
AD2
AD3
AF1
AA4
AD6
AC3
AE1
AB6
AF4
AE5
AC8
AB5
AF5
AC6
AF6
AD11
AF8
AD8
AD5
AB7
AF7
AD7
AB8
AE7
AE9
AB9
AF9
AD10
AF12
AB11
AB10
AD9
AC10
AF10
AD14
AD12
AB12
AE11
AE15
AF11
AF13
AB14
AF14
AB13
AB15
AE13
AC14
AD13
AD15
AF16
AF15
AC12

K26
J22
K25
J21
L24
J20
L26
K23
K22
M25
M24
M26
M21
N24
N22
N26
T26
T22
U24
T23
U26
T24
V24
U21
V25
V21
V26
W21
W24
W22
W26
Y21

2

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

VGA_LDQM0
VGA_LMD4
VGA_LMD7
VGA_LMD3
VGA_LMD6
VGA_LMD2
VGA_LMD5
VGA_LMD1
VGA_LMD0
VGA_LMA4
VGA_LDQM1
VGA_LMA2
VGA_LMD8
VGA_LMA5
VGA_LMD9
VGA_LMA1
VGA_LMA8
VGA_LMD14
VGA_LMA11
VGA_LMD15
VGA_LMA9
VGA_LMD16
VGA_LMA0
VGA_LMD17
VGA_LCKE
VGA_LMD18
VGA_LCAS#
VGA_LMD19
VGA_LTCLK1
VGA_LMD20
VGA_LTCLK0
VGA_LMD21

1

<4>

2

HA#[3..31]

DVO

HA#[3..31]
U7A

AGP

HD#[0..63]

<4> HD#[0..63]

300_1%_0402
VGA_LWE#

<13>

VGA_LFSEL

<8,13>

B

C356

HL[0..10]

GMCH2v0

HL[0..10]

<14>

@22PF

GMCH2v0

For external AGP bus pull up/down resistors.

VGA_LCS#
VGA_LMA10
VGA_LMD24
VGA_LMD27

1

AGP_ADSTB1

A

AGP_SBSTB

VGA_LMA6

CLK_HUB_GMCH

<11>

R267
@33_0402

R263
@33_0402
12

2
8.2K_0402
2
8.2K_0402
2
8.2K_0402
2
100K_0402

CLK_HUB_GMCH

+AGPREF_2GMCH

R74
200_1%_0402

R75
82_0402

C370

C317
@22PF
2

AGP_SBSTB#

1
R392
1
R394
1
R396
1
R398

0.4VDDQ

1

2
AGP_ADSTB#1

1

AGP_ADSTB#0

CLK_DOT_GMCH
R77
82_0402

2

2

VGA_LMD29
AGP_ADSTB0

2
8.2K_0402
2
8.2K_0402
2
8.2K_0402
2
8.2K_0402
2
8.2K_0402
2
8.2K_0402

1

1
R391
1
R393
1
R395
1
R397
1
R399
1
R400

VGA_LDQM3

R76
300_1%_0402

@18PF

A

2

VGA_LMD28
C400
.1UF

.1UF

3.3V

2

1

C424

AGP-REF
0.5VDDQ

C76
470PF_0402

+3VS
R314
2K_1%

+VDDQ
1.5V

+3VS

10P8R-8.2K

+GTLREF

TYPEDET#
0

1

10
9
8
7
6

2

R299
1K_1%

1
2
3
4
5

1

1

VGA_LMA7
VGA_LMD11
VGA_LMD12
VGA_LMD30

VGA_LMA[0..11]
VGA_LMD[0..31]
VGA_LDQM[0..3]

<13> VGA_LMA[0..11]
<13> VGA_LMD[0..31]
<13> VGA_LDQM[0..3]

+3VS
RP38

1

+3VS

C75

2

+CPU_IO

470PF_0402

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

GMCH2-M - 1/3
Size

4

3

2

Rev
2.0

888L2 Main Board
Date:

5

Document Number

T h ursday, January 11, 2001

Sheet
1

7

of

42

5

4

Power-Up Strap Options
Pin Name
Strap Description
SCAS#

Configuration

Host Freq.

3

Interface

Internal

"H" : 133MHz (Default)
"L" : 100MHz

System
Memory

PULL_UP

Host Freq.

"H" : 100MHz (Default)
"L" : 66MHz

System
Memory

SMAA11

IOQ Depth

"H" : 4 (Default)
"L" : 1
"H" : Normal
"L" : All Z
"H" : Enabled (Default)

System
Memory
System
Memory
System

"L" : Disabled (Cumine)
"H" : Enabled (Default)
"L" : Disabled
"L" : Enabled (Default)
(Quick Start Mode)
"H" : Disabled
(Stop Grant Mode)

Memory
System
Memory
System
Memory

PULL_UP

D

SMAA10

ALL Z

SMAA9

FSB P-MOS Kicker Enable

SMAC6#

*

Enable VCH Serial
Programming Mode

SMAC5#

Enable Quick Start
Support

VGA_LFSEL#

L o cal Memory Freq. Select

"H" : 133MHz (Default)
"L" : 100MHz

AGP/LM

PULL_UP
PULL_UP
PULL_UP
PULL_UP

PULL_UP

i815/i815-m

C

B

A

MD32
MD33
MD34
MD35

RP2
5
6
7
8

MD36
MD37
MD38
MD39

5
6
7
8

8P4R-10
4 MMD32
3 MMD33
2 MMD34
1 MMD35
4
3
2
1

MMD36
MMD37
MMD38
MMD39

MD3
MD2
MD1
MD0

RP27
5
6
7
8

MD7
MD6
MD5
MD4

5
6
7
8

RP3

8P4R-10

RP28

MD43
MD42
MD41
MD40

RP4
4
3
2
1

8P4R-10
5 MMD43
6 MMD42
7 MMD41
8 MMD40

MD8
MD9
MD10
MD11

RP29
4
3
2
1

MD47
MD46
MD45
MD44

4
3
2
1

MD15
MD14
MD13
MD12

4
3
2
1

5
6
7
8

MMD47
MMD46
MMD45
MMD44

RP5

8P4R-10

MD20
MD21
MD22
MD23

RP10
1
2
3
4

8P4R-10
8 MMD20
7 MMD21
6 MMD22
5 MMD23

MD16
MD17
MD18
MD19

1
2
3
4

8
7
6
5

MMD16
MMD17
MMD18
MMD19

8P4R-10
4 MMD3
3 MMD2
2 MMD1
1 MMD0
4
3
2
1

MMD7
MMD6
MMD5
MMD4

8P4R-10
8P4R-10
5 MMD8
6 MMD9
7 MMD10
8 MMD11
5
6
7
8

8P4R-10

MD60
MD61
MD62
MD63

RP33
1
2
3
4

8P4R-10
8 MMD60
7 MMD61
6 MMD62
5 MMD63

MD59
MD58
MD57
MD56

1
2
3
4

8P4R-10

RP34

8P4R-10

MD28
MD29
MD30
MD31

RP15
1
2
3
4

8P4R-10
8 MMD28
7 MMD29
6 MMD30
5 MMD31

MD52
MD53
MD54
MD55

RP11
1
2
3
4

8P4R-10
8 MMD52
7 MMD53
6 MMD54
5 MMD55

MD24
MD25
MD26
MD27

1
2
3
4

MD48
MD49
MD50
MD51

1
2
3
4

RP13

MMD24
MMD25
MMD26
MMD27

8P4R-10

RP12

8
7
6
5

SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6
SMD7
SMD8
SMD9
SMD10
SMD11
SMD12
SMD13
SMD14
SMD15
SMD16
SMD17
SMD18
SMD19
SMD20
SMD21
SMD22
SMD23
SMD24
SMD25
SMD26
SMD27
SMD28
SMD29
SMD30
SMD31
SMD32
SMD33
SMD34
SMD35
SMD36
SMD37
SMD38
SMD39
SMD40
SMD41
SMD42
SMD43
SMD44
SMD45
SMD46
SMD47
SMD48
SMD49
SMD50
SMD51
SMD52
SMD53
SMD54
SMD55
SMD56
SMD57
SMD58
SMD59
SMD60
SMD61
SMD62
SMD63

SMAA0
SMAA1
SMAA2
SMAA3
SMAA4
SMAA5
SMAA6
SMAA7
SMAA8
SMAA9
SMAA10
SMAA11
SMAA12
SMAB#4
SMAB#5
SMAB#6
SMAB#7
SMAC#4
SMAC#5
SMAC#6
SMAC#7
SBS0
SBS1
SCSA#0
SCSA#1
SCSA#2
SCSA#3
SCSA#4
SCSA#5
SCSB#0
SCSB#1
SCSB#2
SCSB#3
SCSB#4
SCSB#5
SRAS#
SCAS#
SWE#
SCKE0
SCKE1
SCKE2
SCKE3
SCKE4
SCKE5
SCLK
SDQM0
SDQM1
SDQM2
SDQM3
SDQM4
SDQM5
SDQM6
SDQM7
SRCOMP

D13
B16
F12
A16
B12
A12
C11
A11
D12
C13
E11
A13
B7

MMA0
MMA1
MMA2
MMA3

B15
A15
C14
A14

MAB#4_R
MAB#5_R
MAB#6_R
MAB#7_R

MAB#6_R
MAB#7_R
MAB#4_R
MAB#5_R

B10
A10
C10
A9

SMAC#4
SMAC#5
SMAC#6
SMAC#7

SMAC#6
SMAC#7
SMAC#4
SMAC#5

B13
D11

SBS0
SBS1

D15
A17
D14
E14
E13
B17

CSA#2
CSA#3
CSA#4
CSA#5

<10>
<10>
<10>
<10>

MMA8
MMA9
MMA10
MMA11
MMA12

<10>
<10>
<10>
<10>
<10>

MAB#6
MAB#7
MAB#4
MAB#5

<10>
<10>
<10>
<10>

MAC#6
MAC#7
MAC#4
MAC#5

<10>
<10>
<10>
<10>

D

MMA8
MMA9
MMA10
MMA11
MMA12

SBS0
SBS1

1
2
3
4
RP8
1
2
3
4
RP9

8 MAB#6
7 MAB#7
6 MAB#4
5 MAB#5
8P4R-10
8 MAC#6
7 MAC#7
6 MAC#4
5 MAC#5
8P4R-10

<10>
<10>

CSA#2
CSA#3
CSA#4
CSA#5

<10>
<10>
<10>
<10>

F9
F8
D10
D9
B9
A8

C

C16
D18
E16

SRASA#
SCASA#
RMWEA#

D8
E8
E9
D7
C8
C7

CKE2
CKE3

SRASA#
<10>
SCASA#
<10>
RMWEA# <10>

CKE2
CKE3
CKE4
CKE5

<10>
<10>

<10>
<10>

1
R315

2
@33_0402
C410

F7

@22PF

CLK_MEM_GMCH

D16
F15
A7
A6
A18
C17
B6
A5

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

G7

SRCOMP

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
R297

1

<7,13>

RMWEA#
SCASA#
SBS0
MMA9
MAC#5
MAC#6
CSA#4
VGA_LFSEL#

VGA_LFSEL

R285
R281
R292
R301
R305
R307
R290
R68

1
1
1
1
1
1
1
2

2
2
2
2
2
2
2
1

<11>

<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
2

36.5_1%

+3V

B

@10K_0402
10K_0402
10K_0402
10K_0402
10K_0402
@10K_0402
@10K_0402
@10K_0402

MD[0..63]
<10> MD[0..63]
A

MMD48
MMD49
MMD50
MMD51

Compal Electronics, Inc.

8P4R-10

Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

GMCH2-M - 2/3
Size

4

3

2

Document Number

Rev
2.0

888L2 Main Board
Date:

5

MMA0
MMA1
MMA2
MMA3

GMCH2v0

MMD59
MMD58
MMD57
MMD56

RP31

8
7
6
5

D23
C23
D22
F21
E21
G20
F20
D20
F19
E19
D19
E18
B18
F18
G18
D17
A3
A1
C1
F2
G3
D6
C5
B4
D4
C2
D3
E4
F5
G4
J6
K5
A26
A25
B24
A24
B23
A23
C22
A22
D21
B21
A21
C20
B20
A20
C19
A19
A4
A2
B1
E1
G2
E6
D5
C4
B3
D2
E3
F4
F6
G5
H4
J4

MMD15
MMD14
MMD13
MMD12

RP7

8
7
6
5

1

U7B
MMD0
MMD1
MMD2
MMD3
MMD4
MMD5
MMD6
MMD7
MMD8
MMD9
MMD10
MMD11
MMD12
MMD13
MMD14
MMD15
MMD16
MMD17
MMD18
MMD19
MMD20
MMD21
MMD22
MMD23
MMD24
MMD25
MMD26
MMD27
MMD28
MMD29
MMD30
MMD31
MMD32
MMD33
MMD34
MMD35
MMD36
MMD37
MMD38
MMD39
MMD40
MMD41
MMD42
MMD43
MMD44
MMD45
MMD46
MMD47
MMD48
MMD49
MMD50
MMD51
MMD52
MMD53
MMD54
MMD55
MMD56
MMD57
MMD58
MMD59
MMD60
MMD61
MMD62
MMD63

MEMORY

SWE#

2

T h ursday, January 11, 2001

Sheet
1

8

of

42

5

4

3

+1_8VS

2

1

+1_8VS
U7D

A

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

POWER/GND

B

VSUS_3.3_1
VSUS_3.3_2
VSUS_3.3_3
VSUS_3.3_4
VSUS_3.3_5
VSUS_3.3_6
VSUS_3.3_7
VSUS_3.3_8
VSUS_3.3_9
VSUS_3.3_10
VSUS_3.3_11
VSUS_3.3_12
VSUS_3.3_13
VSUS_3.3_14
VSUS_3.3_15
VSUS_3.3_16
VSUS_3.3_17
VSUS_3.3_18

INTRPT#
AGPBUSY#
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

+3VS

+3V
D

C119

22UF_6.3V_1210_X5R

22UF_6.3V_1210_X5R
C104
1
+

+

C482
L16
68nH

C120

150UF_6.3V_E
C432

2

.01UF

22UF_6.3V_1210_X5R
C393

1

150UF_6.3V_E
C371
.1UF

.01UF
C398

.1UF

C109

.1UF

C417

82PF

C415

.1UF

C416

.1UF

C414

82PF

C413

.1UF

C404

C358
1

C407

1

1

+VCCDA

2

+

1

+

+

C274

2

R319
0_0402

C399

.1UF

22UF_10V_1206
2

2

82PF

.1UF

C367
10UF_10V_1206
+3V

B2
B5
B8
B11
B14
B19
B22
B25
E2
F10
F14
F17
G6
G8
G19
H2
H5
H7

+1_8VS

+1_8VS

2

W6
G26
M6
P6
Y9
Y18
AA8
AA11
AA13
AA15
AA17
AA19
AB16
AB20
AC22
AD19
C25
E24
F23
G22
K6
Y7
AA21
E23
AF26
AF25
AA6
V7
T6

C431

C325

.01UF

.1UF

C394

C359

.01UF

.1UF

C428

C326

82PF

.1UF

C126

C324

.01UF

82PF

C433
.01UF

C357

C

C419

82PF

82PF
C354

C372

.1UF

C383

82PF

C377

.1UF

C346

.1UF

1
C483

2
.1UF_0402

1
C484

2
.1UF_0402

C333

82PF

.01UF
C352

+3VS

.01UF
K20
Y24
L21
M23
U25
N25
R21
U20
U23
W20
Y17
E7
M14
M15
M16
N2
N6
N11
N12
N13
N14
N15
N16
N23
P4
AA23
F16
F25
G9
G17
G21
G23
P24
H6
H22
J2
J5
J23
J25
K4
K21
L2
L6
L11
L12
L13
L14
AA25
W7

+3VS

1

C

GND/VSSDACA1
GND/VSSDACA2
GND/VSSBA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCCDA/(VCC1_8)
VCCBA/(VCC1_8)
VCCDACA1/(VCC1_8)
VCCDACA2/(VCC1_8)
HCLK#
VCC1_8
VCC1_8

R280
10K_0402

2

.1UF
2

D

C418

VCC1_8/VCCDPLL
GND/VSSDPLL

1

C118

22UF_6.3V_1210_X5R

J7
K7
AE25
AF24
E22
Y8
AB4
M13
AC2
AC5
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC25
AE2
AE4
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
B26
C3
C6
C9
C12
C15
C18
C21
C24
D1
E5
E10
E12
E15
E17
E20
F1
F3
F11
F13
T21
U2
U7
K24
V4
V6
V20
V22
W2
W23
W25
Y4
Y6
Y10
Y19
AA2
AA9
AA12
AA14
AA16
P11
P12
P13
P14
P15
P16
R2
R6
R11
R12
R13
R14
R15
R16
R23
R25
T4
T11
T12
T13
T14
T15
T16
L15
L16
L22
L25
M4
M11
M12

2

+

1

+VCCDPLL

R112 1

2

0_0402

A G P_BUSY#

<15>

B

PIN#

DT_GMCH

GMCH2-M

E7

VSS (GND)

AGPBUSY# (OUTPUT)

AA6

V_1.8 (1.8V)

RESERVED (1.8V)

VSS (GND)

INTRPT# (INPUT)

Y17
AC18

LTVCLKIN (INPUT)

LTVCLKIN/STALL (INPUT)

A

GMCH2v0

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

GMCH2-M - 3/3
Size

4

3

2

Rev
2.0

888L2 Main Board
Date:

5

Document Number

T h ursday, January 11, 2001

Sheet
1

9

of

42

1

2

3

4

5

6

7

8

+3V
+3V
+3V

+3V

MD39
MD38
MD37
MD36
C

MD35
MD34
MD33
MD32
<11> SMB_ICH_DAT_M0

<8>

<11> CLK_MEM4

SCASA# <8>
CKE3 <8>
MMA12 <8>

MMA12
MMA13

<8> SRASA#
<8> RMWEA#
<8> CSA#4
<8> CSA#5
CLK_MEM3

RMWEA#

<11>

MD15
MD14
MD13
MD12

R84
6.8_0402

MD15
MD14
MD13
MD12

MD11
MD10
MD9
MD8

C84

MD11
MD10
MD9
MD8

5PF

MAB#7
SBS0

MAB#7 <8>
SBS0 <8>

SBS1
MMA11

MAC#6
MMA8

<8> MAC#6
<8> MMA8

SBS1 <8>
MMA11 <8>

MMA9
MMA10

<8> MMA9
<8> MMA10

DQMA#1
DQMA#0

DQMA#1
DQMA#0

MD7
MD6
MD5
MD4

MD7
MD6
MD5
MD4

MD3
MD2
MD1
MD0

MD3
MD2
MD1
MD0
SMB_ICH_CLK_M

<11>

<11> SMB_ICH_DAT_M1

SMB_ICH_DAT_M1

61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

SO-DIMM144_R

RFU/CLK0
VCC
RFU
WE#
RE0#
RE1#
OE#/RESVD
VSS
RESVD/DQ66
RESVD/DQ67
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10
VCC
CE2#/RESVD
CE3#/RESVD
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC

RFU/CKE0
VCC
RFU
RFU/CKE1
RFU
RFU
RFU/CLK1
VSS
RESVD/DQ70
RESVD/DQ71
VCC
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
DQ53
DQ54
DQ55
VCC
A7
A11/BA0
VSS
A12/BA1
A13/A11
VCC
CE6#/RESVD
CE7#/RESVD
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC

DIMM1

MD47
MD46
MD45
MD44

R85
6.8_0402

MD43
MD42
MD41
MD40

C85
5PF

MAC#7
SBS0

MAC#7 <8>
SBS0 <8>

SBS1
MMA11

SBS1 <8>
MMA11 <8>

DQMA#5
DQMA#4
MD39
MD38
MD37
MD36
C

MD35
MD34
MD33
MD32
SMB_ICH_CLK_M

1000PF

2

1

C61

1000PF

C56
.1UF

C92
.1UF

C91
.1UF

C96
.1UF

C106

C93

C108

1000PF

.1UF

.1UF

C74
1000PF

C436
10UF_10V_1206

1

1

2
.1UF

C48
.1UF

C77

C95

C437

.1UF

1000PF

10UF_10V_1206
2

.1UF

1

.1UF

C67

2

.1UF

C51

2

.1UF

1

1000PF

C94

2

.1UF

1

1000PF

1

C90

2

C66

2

C58
2

C50
2

C40
2

C107

2

1

1

1

1

1

<11>

+3V

2

C39

1

+3V

+3V

1

1

+3V

2

B

CLK_MEM5

H=5.2mm

1000PF
1

MMA12
MMA13

DQMA#[0..7]

2

<8> DQMA#[0..7]

MD[0..63]

+3V

2

<8>

SCASA#
<8>
CKE5 <8>
MMA12 <8>

DIMM2
<8> MD[0..63]

H=4.0mm

D

CKE4

SO-DIMM144

REVERSE

+3V

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

1

1
2
CKE2

1 2

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

MD19
MD18
MD17
MD16

1

DQMA#5
DQMA#4

2
6.8_0402

MD23
MD22
MD21
MD20

2

MMA9
MMA10

2 1
R89
5PF

MMA3 <8>
MAC#4 <8>
MAC#5 <8>

1

<8> MMA9
<8> MMA10

MAB#6
MMA8

C81
1

MMA3
MAC#4
MAC#5

2

<8> MAB#6
<8> MMA8

MD59
MD58
MD57
MD56

DQMA#3
DQMA#2

1

MD43
MD42
MD41
MD40

RFU/CKE0
VCC
RFU
RFU/CKE1
RFU
RFU
RFU/CLK1
VSS
RESVD/DQ70
RESVD/DQ71
VCC
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
DQ53
DQ54
DQ55
VCC
A7
A11/BA0
VSS
A12/BA1
A13/A11
VCC
CE6#/RESVD
CE7#/RESVD
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC

MD59
MD58
MD57
MD56

A

2

MD47
MD46
MD45
MD44

RFU/CLK0
VCC
RFU
WE#
RE0#
RE1#
OE#/RESVD
VSS
RESVD/DQ66
RESVD/DQ67
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10
VCC
CE2#/RESVD
CE3#/RESVD
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC

MD63
MD62
MD61
MD60

MD27
MD26
MD25
MD24

1

RMWEA#

MD63
MD62
MD61
MD60

MD31
MD30
MD29
MD28

2

B

<8> SRASA#
<8> RMWEA#
<8> CSA#2
<8> CSA#3

<8> MMA0
<8> MMA1
<8> MMA2

1

61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

<11> CLK_MEM2

MMA3 <8>
MAB#4 <8>
MAB#5 <8>

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

2

2

MMA0
MMA1
MMA2

1

R93
6.8_0402
2 1

DQMA#6
DQMA#7

MMA3
MAB#4
MAB#5

1

5PF
1
C86

DQMA#6
DQMA#7

2

MD19
MD18
MD17
MD16

MD51
MD50
MD49
MD48

1K_0402

VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
CE4#
CE5#
VCC
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
VSS
RESVD/DQ68
RESVD/DQ69

2

MD23
MD22
MD21
MD20

R86

VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
CE0#
CE1#
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
RESVD/DQ64
RESVD/DQ65

1

<8> MMA0
<8> MMA1
<8> MMA2

MMA13

MD51
MD50
MD49
MD48

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

MD55
MD54
MD53
MD52

2

MMA0
MMA1
MMA2

MD55
MD54
MD53
MD52

1

DQMA#3
DQMA#2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

1 2

A

VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
CE4#
CE5#
VCC
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
VSS
RESVD/DQ68
RESVD/DQ69

2

MD27
MD26
MD25
MD24

JP16

VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
CE0#
CE1#
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
RESVD/DQ64
RESVD/DQ65

2

JP17
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

MD31
MD30
MD29
MD28

D

For SO-DIMM2
For SO-DIMM1

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

P10-SODIMM0/1.SCH
Size
B
Date:

1

2

3

4

5

6

Document Number

Rev
2.0

888L2 Main Board
T h ursday, January 11, 2001
7

Sheet

10

of
8

42

A

B

C

D

E

+3V_CLK

C68

1

C64

1

C57

1

C63

1

C65

1

+3V_CLK
C72

1

2
1

L14
1
BLM21A601SPT

1

+3VS

C73

C80

L15
2
1
BLM21A601SPT

+2_5V_CLKS
.1UF

+2_5V_CLK

2

2

.1UF

4

1

C83

C82
4.7UF_10V_0805

.1UF

4

2

C79

1

1

2

.1UF
2

.1UF
2

.1UF
2

.1UF
2

.1UF
2

2

.1UF
2

4.7UF_10V_0805

2M

14.318MHZ
CK133-XOUT 4

2

1

R81

<21> CLK_14M_SIO

2

1

2

1

33_0402

SEL0
SEL1
CLK_14M

33_0402

<15> PCI_STP#
<14> CLK_PCI_ICH
<19> CLK_PCI_PCM
<14> CLK_PCI_FWH
<21> CLK_PCI_SIO
<29> CLK_PCI_MINI

R62

1

2

33_0402

R61
R59
R55

1
1
1

2
2
2

33_0402
@33_0402
33_0402

PCISTP#
CLK_ICH
CLK_PCI1
CLK_FWH
CLK_SIO

R53

1

2

22_0402

CLK_MDM

R51
R49

<15> CLK_USB_ICH
<7> CLK_DOT_GMCH

3

R46

1

X2

18PF

2

1
1

2
2

33_0402
33_0402

11
12
13
15
16
18
19
20

CLK_USB
CLK_DOT
1

+3V_CLK

0_0402

28
29
1

<15,22> SLP_S1#

25
26
2

33
32

8.2K_0402R50
30
31

PCI_STP#/(VCC3)
PCI_F(PCI0_ICH)
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6

SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VCH_CLK/(SDRAM7)

3V66_AGP
3V66_1
3V66_0

USB(48M)
DOT(48M)
TEST#/(VCC3)
PWR_DWN#
SDATA
SCLK

1
+3V_CLK

51
53
CPU0
CPU1
CPU2(ITP)

DCLK/(VCC3)
CPU_STP#(DCLK)

5
6
14
21
24
41
47
48
56

<15> SMB_ICH_DAT
<15> SMB_ICH_CLK

SEL0
SEL1(TRIST#)
REF0/(SEL1)

APIC0
APIC1

55
54

R88
R87

1
1

2
2

33_0402
47_0402

HCLK1
HCLK2

R83
R69

1
1

2
2

33_0402
33_0402

46
45
43
42
40
39

SDRAM2
SDRAM3
SDRAM4
SDRAM5

R58
R60
R56
R57

1
1
1
1

2
2
2
2

10_0402
10_0402
10_0402
10_0402

36

OSCVCH

R52

1

2

33_0402

9
8
7

CLK_3V66_1
CLK_3V66_0

R64
R67

1
1

2
2

33_0402
33_0402

DCLK

R54

1

2

33_0402

52
50
49

38
34

APIC0
APIC1

CLK_APIC_CPU
CLK_APIC_ICH

<4>
<14>

CLK_HOST_CPU
<4>
CLK_HOST_GMCH <7>

CLK_MEM2
CLK_MEM3
CLK_MEM4
CLK_MEM5

<10>
<10>
<10>
<10>

CLK_OSC_VCH

<12>

CLK_HUB_GMCH <7>
CLK_HUB_ICH <15>
CLK_MEM_GMCH
CPU_STP# <15>

3

<8>

GND
GND
GND
GND
GND
GND
GND
GND
GND

R82

<15> CLK_14M_ICH

X1

U6

VCC2
VCC2

23
3

2

C71

Y1

VDDA
VCC3
VCC3
VCC3
VCC3/(SDRAM6)
VCC3
VCC3
VCC3

R65

GNDA

18PF

2

CK133-XIN

1

1

1

2

22
17
2
10
37
27
44
35

C78

CK133-SOLANO2-M

R45

2

10K_0402

SEL1 SEL0

*

1

+3V_CLK

R41

<15> SEL_DIMM0

+3V

10K_0402

2

1

Pin #
R32
10K_0402

2

2

Q8
2N7002

SMB_ICH_DAT_M0

<10>

SMB_ICH_DAT_M1

<10>

2

2

G

2

1

2

2

1

1

1
2

3

R35
10K_0402

D

R37
10K_0402

S

R38
4.7K_0402

R33
10K_0402

G

R43
@1K_0402

1

+3VS

1

2

<15> SEL_DIMM1
SEL0

1

S

D

Q9
3
2N7002

<15> SMB_ICH_DAT

+5VS

1

G

2

+3V_CLK

1
D

Q10
2N7002

SMB_ICH_CLK_M

<10>

SDRAM

0

66

100

0

1

100

100

1

0

133

133

1

1

133

100

CK-Solano
W218
C9815

2

CK-Solano2-m
W224
C9835

1
11
29

REF0/SEL1
VCC3
Tristate#

REF/SEL1 REF
VCC3
PCI_STP#
Tristate# SEL1

REF
PCI_STP#
SEL1

33
34
36
37
38

VCC3
DCLK
SDRAM7
SDRAM6
VCC3

VCC3
DCLK
SDRAM7
SDRAM6
VCC3

TEST#
CPU_STP#
VCH_CLK
VCC3
DCLK

TEST#
CPU_STP#
VCH_CLK
VCC3
DCLK

SEL1

2

2

3

<15> SMB_ICH_CLK

S

R40
@10K_0402

PSB

0

R39
1K_0402

1

1

1

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

Clock Synthesizer
Size

B

C

D

Rev
2.0

888L2 Main Board
Date:

A

Document Number

T h ursday, January 11, 2001

Sheet
E

11

of

42

5

4

3

2

1

U15A

1

R234
2K_1%

C240
2

<13,23>

2

ENABKL

ENVDD

CLK_OSC_VCH

D14
C12
C14
B14

VCH_VID4
VCH_VID3

N9

TV_ZCOM

2
R431

1
R34

2
36.5_1%

C41

C220

C37

C206

C46

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

C47

C176

C45

C38

C53

C197

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

.1UF

R420
6.8K_0402

INV_PWR

6.8K_0402
R421
2
C30

1
.01UF

Q49
2N7002

2
C29

1
.1UF

2
C28

1
.1UF

3

SMB_EC_DA1

1

<4,22,23,31>

3

SMB_EC_CK1

+5V
+5VALW

Q50
2N7002

SMB_INV_DA
SMB_INV_CK

1
<13> DISPOFF#

PID3
PID2
PID1
PID0
C25

C26

C27

LCDVDD

.1UF_0402
.1UF_0402
.1UF_0402

+3V
<7> LTVCL
<7> LTVDA

C201
10UF_10V_1206

PID2

INV_PWR

+12VALW

1
R16

470

100K_0402

L10
1
2
FBM-11-451616-800A

+3VS

+3VS

Q19
SI2302DS

2

2

4

C

1
R10
C16
150K

S
.01UF
2

1

3
75K

1

1
2
G
Q3
2N7002

S

2

R190

D

3

2N7002
2
G

1

FDS4435:PCHANNAL

1

2

2

Q21
D

LCD5
LCD4

PID0
4.7K_0402
1
2
R186
1
2
R187
4.7K_0402
1
2
R188
4.7K_0402
1
2
R189
4.7K_0402

FDS4435
100K_0402

SI2302DS: NCHANNEL
VGS:4.5V, RDS:85mOHM
VGS:2.5V, RDS:115mOHM
Id(MAX): 2.8A
VGS(MAX): +/-8V

LCD7
LCD6
LCD11
LCD10
LCD13
LCD12
LCD15
LCD14
LCD17
LCD16

LCDVDD

Q18

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

B

LCD CONN
1

2

+5V

1

LCD3
LCD2

PID1

2

2

R183
.1UF

3

100K_0402

R175

G

1

1

R11
8
7
6
5

D

Q24
1
2
3

LCDVCC

S

1

LCDVDD

LCDVDD

1

+12VALW

C169

LTVCL
LTVDA
LCD1
LCD0

PID3

B+

2
1
C24
.1UF_0402

10UF_10V_1206

VCH

C

JP7
<4,22,23,31>

2

2

2

2

2

2

2

2

2

2

2

2

+5VALW

R426
0_0402

1

1

1

1

1

1

C42
C172

<13>

+3VS

+1_8VS

.1UF_0402

1

1

1

1

1

1

C52

.1UF

M_SEN#

1
10K_0402

PID3
PID2
PID1
PID0

+3VS

C44

M_SEN#
2
R432

C23
+1_8VS

2

<7,14,19,21,29>

1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

H5
H6
H7
H8
H9
H10
J5
J6
J7
J8
J9
J10
K5
K6
K7
K8
K9
K10
L4
N14
P1
P14

VCH

2

PCIRST#

1
0_0402

<11>

1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

+1_8VS

PLL_VSS
LVDSPLL_VSS
DC_CKT_VSS

@18PF

2

+1_8VS
2
150
2
150

2 C54
@33_0402

2

1
2

LCD16
LCD17

1

PLL_VCC
LVDSPLL_VCC
DC_CKT_CKT

C5
D5
D10
E8
E11
F4
G11
H11
J11
K11
L5
L7
L8
L9
N13

DVOrZCOM

1
R36

+3VALW
A1
A14
B1
C4
D11
E5
E6
E7
E9
E10
F5
F6
F7
F8
F9
F10
G5
G6
G7
G8
G9
G10

R235
2K_1%

1

VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8

C2
C3
D1

PCIRST
GPIO0
GPIO1
TESTIN

D

2

<7> DVO_HSYNC
<7> DVO_VSYNC

DVOCLKIN0
DVOCLKIN1
DVOBLK
DVOCLKOUT
DVOHSYNC
DVOVSYNC
LCDVREF

VCH_VID1

<7>
<7>

2

<7> DVO_CLK#
<7> DVO_CLK
<7> DVO_BL#

2

GPIO7
OSC

E14
M12

GMBSDA
GMBSCL

+1_8VS

1

ENABKL
ENAVDD
ENEXBUF

<4>

1

1
R185
1
R184

LCD6
LCD7
LCD10
LCD11
LCD12
LCD13
LCD14
LCD15

M8
N8
N11
P12
P11
N12
P13

.1UF

VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3

VCH_VID[0..4]

2

D8
D7

33_0402
1
R48

<7> DVO_CLKOUT

2

L11
C11
C8

B

LCD0
LCD1
LCD2
LCD3
LCD4
LCD5

GMBSDA
GMBSCL
GPIO5
GPIO4
GPIO6
GPIO3
GPIO2
GPIO8

GMBSDA
GMBSCL
PID3
PID2
VCH_VID2
PID1
PID0
VCH_VID0

D

L10
C10
C7

A3
B3
A4
B4
A5
B5
A7
B7
A6
B6
A8
B8
A9
B9
A10
B10
A11
B11
A12
B12

DVODATA0
DVODATA1
DVODATA2
DVODATA3
DVODATA4
DVODATA5
DVODATA6
DVODATA7
DVODATA8
DVODATA9
DVODATA10
DVODATA11

D13
D12
E13
E12
F12
C13
B13
F13

S

+1_8VS

VCH_VID[0..4]
U15B
M11
P10
N10
M10
P9
M9
P8
P7
N7
M7
P6
N6

G

A2
A13
C9
D4
D6
D9
E4
F11
G4
H4
J4
K4
L6
C6

DVO_D[0..11]

<7> DVO_D[0..11]

D

+3VS

2
2.4K

S

VREF_HI
VREF_LO

1
R377

1

YA0P
YA0M
YA1P
YA1M
YA2P
YA2M
YA3P
YA3M
CLKAP
CLKAM
YB0P
YB0M
YB1P
YB1M
YB2P
YB2M
YB3P
YB3M
CLKBP
CLKBM

G14
G13
G12
F14
J13
J12
H14
H13
H12
J14
K14
K13
K12
L14
L13
L12
M14
M13

1

C

DVOrVSYNC
DVOrHSYNC
DVOrBLANK#
DVOrCLKIN
DVOrCLKOUT0
DVOrCLKOUT1
DVOrDATA0
DVOrDATA1
DVOrDATA2
DVOrDATA3
DVOrDATA4
DVOrDATA5
DVOrDATA6
DVOrDATA7
DVOrDATA8
DVOrDATA9
DVOrDATA10
DVOrDATA11

2

D

P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
FLM
LP
DE
SHFCLK

G

E3
E2
E1
F3
F2
F1
G3
G2
G1
H3
H2
H1
J3
J2
J1
K3
K2
K1
L3
L2
L1
M3
M2
M1
N1
N2
P2
N3
P3
M4
N4
P4
M5
N5
P5
M6
C1
B2
D2
D3

D

ENVDD
Q28
2N7002

2
G

2

22K
B
E
22K

A

.1UF

DTC124EK
3

3

S

C164
C165
10UF_10V_1206

2

1

A

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

VCH
Size

4

3

2

Rev
2.0

888L2 Main Board
Date:

5

Document Number

T h ursday, January 11, 2001

Sheet
1

12

of

42

5

4

3

DISPLAY CACHE INTERFACE

VGA_LMD27

C231

2
4
6
8
10
GND
14
16
18
20
22
24
26
28
30
GND
34
36
38
40
42
44
46
48
GND
52
54
56
58
60
62
64
66
68
GND
72
74
76
78
80

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80

VGA_LMD3
VGA_LMD2
VGA_LMD1
VGA_LMD0

D

VGA_LMA[0..11]
VGA_LMD[0..31]
VGA_LDQM[0..3]

<7> VGA_LMA[0..11]
<7> VGA_LMD[0..31]
<7> VGA_LDQM[0..3]

+3VS

1

1
3
5
7
9
GND
13
15
17
19
21
23
25
27
29
GND
33
35
37
39
41
43
45
47
GND
51
53
55
57
59
61
63
65
67
GND
71
73
75
77
79

VGA_LDQM0
VGA_LMA3
VGA_LMA2
VGA_LMA1
VGA_LMA0
VGA_LCS#
VGA_LMA8
VGA_LMA9
VGA_LMA10

R179
4.7K_0402

VGA_LCS#

<7>

<22> BKOFF#

<12,23>

VGA_LMA11
VGA_LCKE
VGA_LCAS#
VGA_LRAS#
VGA_LWE#
VGA_LFSEL
DSCACHE#
VGA_LTCLK0

VGA_LCKE <7>
VGA_LCAS#
<7>
VGA_LRAS#
<7>
VGA_LWE# <7>
VGA_LFSEL
<7,8>
DSCACHE#
<15>

1
R251

2
10_0402

1
C243

1
R250

2
10_0402

2

1
D16
RB751V

2

1
R416

2
100_0402

DISPOFF#

<12>

2
10PF

VGA_LTCLK1
VGA_LMD31
VGA_LMD30
VGA_LMD29
VGA_LMD28

ENABKL

1
D9
RB751V

1
C242

VGA_LTCLK0

<7>

VGA_LTCLK1

<7>

2
10PF
C

VR_POK <30>
ITP_VR_POK
<25>
ITP_TDI <4>
ITP_TDO <4>
ITP_TRST# <4>
ITP_PREQ# <4>
GTL_PRDY# <4>
+CPU_IO

CRTVCC

+3VS

+3VS

CONN 2X40

R423
10K_0402

R3
0_0402

R172
2K_0402
1

2

1

1

1

R422
10K_0402

1

R324
0_0402

R2
2K_0402

2

2

.1UF

2

2

1

<4> ITP_TCK
<4> ITP_TMS
<4,7> CPURST#

Display cache no exist

2
.1UF

2

VGA_LMD20
VGA_LMD21
VGA_LMD22
VGA_LMD23
VGA_LDQM2
VGA_LDQM3
VGA_LMD24
VGA_LMD25
VGA_LMD26

Display cache exist

1

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79

VGA_LMD12
VGA_LMD13
VGA_LMD14
VGA_LMD15
VGA_LMD16
VGA_LMD17
VGA_LMD18
VGA_LMD19

C

1
C60

JP9

VGA_LMA4
VGA_LMA5
VGA_LMA6
VGA_LMA7
VGA_LDQM1
VGA_LMD8
VGA_LMD9
VGA_LMD10
VGA_LMD11

0
+3VS

2
.1UF

VGA_LMD4
VGA_LMD5
VGA_LMD6
VGA_LMD7

D

Status

2

1
C59

DSCACHE#

1

2

+3VS

2

1

3

3VDDCDA

3

2

3

2

3

2

D

1

3

3VDDCCL

S

Q1
2N7002

2

.1UF

<7>

2
G

C162

S

D2 @DAN217

D

D3 @DAN217

1

D1 @DAN217

1

1

1

Q15
2N7002

SI2301DS: P CHANNEL
VGS: -4.5V, RDS: 130mOHM
VGS: -2.5V, RDS:190mOHM
Id(MAX): 2.3A
VGS(MAX): +-8V

B

2
G

CRTVCC

<7>

B

+1_8VS
JP4

3

R6
75

R5
75

R4
75

C3

5

CRT CONN.
CRT CONN.

2

4

L36
1
2
FBM-11-160808-121

DDC2_MONID2

27PF

100PF

100PF

C4

1

C7

1

1

C2

C8

100PF

100PF
2

.1UF

C160

A

<7> CRT_VSYNC

1

5

1

1

2

2

2

27PF

2

C161

R167
4.7K_0402

1

2

2
1

R170
4.7K_0402

1
2
FBM-11-160808-121

2

3

L35

1

74AHCT1G125GW
U34

CRTVCC

A

18PF

2

2

G

C5

18PF

2

2

2
10K_0402

C503

C6

18PF

<7> CRT_HSYNC

1

CRTB

2

1
Q62
SI2301DS
1
R433

<7> CRT_B

S

1

D

CRTG

2

<7> CRT_G
CRTVCC

+5VS

1

1

L6
1
2
FCM2012C-800(0805)
L7
1
2
FCM2012C-800(0805)
L8
1
2
FCM2012C-800(0805)
1

SI2301DS
D

M_SEN#
CRTR

1

M_SEN#
<7> CRT_R

1

DDC_MONID0 <12>

1

G

2

2

2

3

1

S

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

CRTVCC

2

4
74AHCT1G125GW
U35
3

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

CRT CONN
Size

4

3

2

Rev
2.0

888L2 Main Board
Date:

5

Document Number

T h ursday, January 11, 2001

Sheet
1

13

of

42

5

4

3

2

1

FWH

+3VS

2

2

@0_0402
<7,12,19,21,29>

RX2

C190
@.1UF

+VPP_R
PCIRST#

PCIRST#

5
6
7
8

2

CLK_PCI_FWH

FWH_GPI3
FWH_GPI2
FWH_GPI4

4
3
2
1

2
R202

CLK_PCI_FWH

U19

1

R220 1
R224 1

2
2
1
R227

@0_0402
@0_0402

IDE_SATA66DET
IDE_PATA66DET
FWP#
TBL#

5
6
7
8
9
10
11
12
13

2
@4.7K_0402
LAD0

LAD0

FGPI1
FGPI0
WP#
TBL#
ID3
ID2
ID1
ID0
FWH0

IC
GNDA
VCCA
GND
VCC
INIT#
FWH4
RFU22
RFU21

@10K_0402
FWH_IC
2
1
R203

29
28
27
26
25
24
23
22
21

+3VS

LFRAME#

LFRAME#

FWH1
FWH2
GND
FWH3
RFU18
RFU19
RFU20

<15,21>

D

C

+3VS
R352 1
R355 1
R345 1

2
2
2

8.2K_0402
8.2K_0402
8.2K_0402

PME# has internal PU

<16,19,29> DEVSEL#
<16,19,29> FRAME#
<16,19,29> IRDY#
<16,19,29> TRDY#
<16,19,29> STOP#
<19,29> PAR
<7,12,19,21,29>
PCIRST#
<16,19> PLOCK#
<16,19,29> SERR#
<16,19,29> PERR#
REQA#
GNTA#

REQA#
GNTA#

W11

<11> CLK_PCI_ICH
1
C457
@22PF

2

AB7
V3
W8
V4
W1
W2
AA15
AA7
W7
Y7
Y15
M3
L2

1
R361

2
@33_0402

A

<16>
<16,29>
<16,29>
<16,19>
<16>

<29> MPCIACT#
1

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
1
R384

R2
R3
T1
AB10
P4
L3
2
0_0402

C/BE0#
C/BE1#
C/BE2#
C/BE3#
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PCIRST#
PLOCK#
SERR#
PERR#
PME#
GPIO0/REQA#
GPIO16/GNTA#
PCICLK
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
GPIO1/REQB#/REQ5#

A20M#

FERR#
IGNNE#
INIT#
INTR
NMI
SMI#
STPCLK#
KBRST#
GATEA20
CPU_PWRGD

IRQ

PIRQA#
PIRQB#
PIRQC#
PIRQD#

IRQ14
IRQ15
APICCLK
APICD0
APICD1
SERIRQ
GPIO2/PIRQE#
GPIO3/PIRQF#
GPIO4/PIRQG#
GPIO5/PIRQH#

GNT0#
GNT1#
GNT2#
GNT3#
GNT4#
GPIO17/GNTB#/GNT5#

P1
P2
P3
N4

SIRQ

N3
N2
N1
M4

GPI2
BD_ID0
BD_ID1
GPI5

M2
M1
R4
T2
R1
L4

LAD3

HL[0..10]

HL[0..10]

1
22
B

LAD2

<15,21>

C

LAD3

FERR# <4>
IGNNE# <4>
INIT# <4>
INTR <4>
NMI <4>
SMI# <4>
STPCLK# <4>
KBRST# <22>
GATEA20 <22>
CPU_PWRGD <4>

1
Q29

3
@3904

ATA Mode

Stuff

ATA33

RX

ATA66

RY

INIT#

<4>

<7>

Default

None; Driver side
detection

1

+1_8VS

R340 1

2

@10K_0402

HL_STB <7>
HL_STB# <7>

PIRQA#
PIRQB#
PIRQC#
PIRQD#

F21
C16
N20
P22
N19
N21

<15,21>

PIRQA#
PIRQB#
PIRQC#
PIRQD#

R113
300_1%

+1_8VS

+3VS
1
R115

2
36.5_1%

<16,19>
<16,29>
<16,19>
<16,29>

RP36

+1_8VS

2

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HL11
HL_STB
HL_STB#
+ICH_HLCOMP

<4>

+HUBREF_ICH

C121
+3VS

.01UF

R114
300_1%

<16,19,21>

PIN N3, M4 can not use GPIO.
GNT#0
GNT#1
GNT#2
GNT#3
GNT#4

GNT#0
GNT#1
GNT#2
GNT#3
GNT#4

<16>
<16,29>
<16,29>
<16,19>
<16>

MODRST#

1
R349
<17>

C122
.1UF

B

8
7
6
5

GPI2
BD_ID0
BD_ID1
GPI5

8P4R-100K
R339 1
R338 1

2
2

10K_0402
10K_0402
IRQ14 <17>
IRQ15 <17>
CLK_APIC_ICH
PICD0 <4>
PICD1 <4>

SIRQ

1
2
3
4

1

PCI

A4
B5
A5
B6
B7
A8
B8
A9
C8
C6
C7
C5
A6
A7
A3
B4

A20M#

2

HUB

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
HL11
HL_STB
HL_STB#
HLCOMP
HUBREF

D11
A12
R22
A11
C12
C11
B11
B12
C10
B13
C13
A13

1

AA3
AB6
Y8
AA9

C/BE#0
C/BE#1
C/BE#2
C/BE#3

CPU

A20M#
CPUSLP#
FERR#
IGNNE#
INIT#
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE
CPUPWRGD

2

<19,29>
<19,29>
<19,29>
<19,29>

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

1

B

AA4
AB4
Y4
W5
W4
Y5
AB3
AA5
AB5
Y3
W6
W3
Y6
Y2
AA6
Y1
V2
AA8
V1
AB8
U4
W9
U3
Y9
U2
AB9
U1
W10
T4
Y10
T3
AA10

@1.5K

LAD2

2

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

LAD1

R222
@10K_0402

C

(FW82801BAM)

LAD1

2

<15,21>
U10A

R236
1

@FWH-PLCC

14
15
16
17
18
19
20

ICH-2M
AD[0..31]

+CPU_IO

+3VS

AD[0..31]

<15,21>

E

1

RY2

<15> FWH_WPTBL#

<19,29>

<11>

2
@22PF

4
3
2
1
32
31
30

@4.7K_0402
2

R218 1

1
C177

@33_0402

@8P4R-10K
R208
@10K_0402

1

FGPI2
FGPI3
RST#
VPP
VCC
CLK
FGPI4

2

R216
@10K_0402

RY1

2

C189
@.1UF
2

1

IDE_PATA66DET
IDE_SATA66DET

1

RP25
1

D

R199
R211
@10K_0402

1

R213
@10K_0402

RX1

1

C207
.1UF
2

2

C218
.1UF

2

C211
.1UF

1

1

1

1
2

C191
.1UF

+3VS

+3VS
2

+3VS

1
R413
1
R415

<11>

2
R350
2
R354
1
R356
1
R353

2
0_0402

1
@0_0402
1
@0_0402
2
@0_0402
1
2
C454
10PF

2 BD_ID1
@10K_0402
2 BD_ID0
@10K_0402

11: SigmaTel ST9700
01: AD1881A

+3VS
2
8.2K_0402

A

ICH-2M

Compal Electronics,Inc.

R348
@1K_0402

2

Title

GNTA# Strapping for "A16 swap override" : "0" -> Enable

T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

ICH2-m-A (FW82801BAM) & FWH
Size

4

3

2

Rev
2.0

888L2 Main Board
Date:

5

Document Number

T h ursday, January 11, 2001

Sheet
1

14

of

42

5

4

3

2

1

1

+3VALW

R363
10K_0402
2

U10B

2 2

1

<11> SMB_ICH_DAT
<11> SMB_ICH_CLK
10K_0402
<22,31> ACIN
R360 1
2
1
2
R147
10K_0402

2

1UF

R162
2

+R_VBAIS

1K_0402

1

2

C153
.047UF

1
1

R163

R156

2

10M
X1

2

C

32.768KHZ
C146 C147

1

1

10M

2

12PF

2

12PF

1
R153
1
R155
1
R127
1
R368
1
R366
1
R141

LID_OUT#
IAC_BITCLK
SDATA_IN0
SDATA_IN1
SPKR

2
10K_0402
2
10K_0402
2
10K_0402
2
10K_0402
2
10K_0402
2
@1K_0402

1
R364

2 0_0402
SMLINK0
SMLINK1

+RTCRST#
+VBIAS
RTCX1
RTCX2
AC_SDOUT Strapping: "1" -> Safe Mode Boot
R143 1
2 @10K_0402
+3VS
<27,29> AC97_RST#
ICH_AC_SYNC
IAC_BITCLK
<27,29> IAC_BITCLK
ICH_AC_SDOUT
SDATA_IN0
<27> SDATA_IN0
SDATA_IN1
<29> SDATA_IN1
SPKR
<28> SPKR
<21,22> EC_SMI#
<13> DSCACHE#
<22> SCI#
<23> LID_OUT#
<17> PIDERST#
<11> SEL_DIMM0
<11> SEL_DIMM1

+3VS
DSCACHE#

2
10K_0402

+3VALW

1K_0402 JOPEN

1

1
R160

<14,21> LAD0
<14,21> LAD1
<14,21> LAD2
<14,21> LAD3
<21> LDRQ#0
+3VS
<14,21> LFRAME#

B

T20
T21
U22
T22

V22
P19
R19
P21
Y22
W22
N22
Y14
AA11
W14
AB15
L1
AB14
AA14

DSCACHE#
LID_OUT#
1
R140

AA16
AB16
AB17
U19
V20

2
0_0402

LAD0
LAD1
LAD2
LAD3
LDRQ#0
LDRQ1#
1
2
R369
@10K_0402 LFRAME#
1
2
R158
@10K_0402
USBP0+
USBP0USBP1+
USBP1USBP2+
USBP2USBP3+
USBP3-

Y12
W12
AB13
AB12
Y13
W13
AB11
AA12
W17
Y18
AB19
AA19
W18
Y19
AB20
AA20

SPKR Strapping: "0" -> No Reboot
+3V
1
R365

2
10K_0402

<18> OVCUR#0
<16> OVCUR#1
<18> OVCUR#2

OVCUR#3

W19
Y20
Y21
W20

PDREQ
PDDACK#
PDIOR#
PDIOW#
PIORDY

SMBDATA
SMBCLK
SMBALERT#/GPIO11
SMLINK0
SMLINK1
RTCRST#
VBIAS
RTCX1
RTCX2

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

IDE

AC_RST#
AC_SYNC
AC_BIT_CLK
AC_SDOUT
AC_SDIN0
AC_SDIN1
SPKR

AC97

GPIO8
GPIO7
GPIO12
GPIO13
C3_STAT#/GPIO21
GPIO27
GPIO28

GPIO

LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ0#
LDRQ1#
LFRAME#/FWH4
FSO
USBP0+
USBP0USBP1+
USBP1USBP2+
USBP2USBP3+
USBP3-

SDA0
SDA1
SDA2
SDCS1#
SDCS3#

LPC

SDDREQ
SDDACK#
SDIOR#
SDIOW#
SIORDY

USB

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

OC0#
OC1#
OC2#
OC3#

D

G22
F22
G19
G21
G20

PDDREQ
PDDACK#
PDIOR#
PDIOW#
PDIORDY

H19
H22
J19
J22
K21
L20
M21
M22
L22
L21
K22
K20
J21
J20
H21
H20

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

A16
D16
B16
C15
D15

SDA0
SDA1
SDA2
SDCS1#
SDCS3#

B18
B17
D17
C17
A17

SDDREQ
SDDACK#
SDIOR#
SDIOW#
SDIORDY

D18
B19
D19
A20
C20
C21
D22
E20
D21
C22
D20
B20
C19
A19
C18
A18

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

PDA0 <17>
PDA1 <17>
PDA2 <17>
PDCS1# <17>
PDCS3# <17>

R358
R357
@33_0402 @33_0402

PDDREQ <17>
PDDACK# <17>
PDIOR# <17>
PDIOW# <17>
PDIORDY <17>

C456
@10PF

PDD[0..15]

PDD[0..15]

<11>
<11>
<11>

1

PDA0
PDA1
PDA2
PDCS1#
PDCS3#

1

CLK_USB_ICH
CLK_14M_ICH
CLK_HUB_ICH

F20
F19
E22
E21
E19

R344
@33_0402

2

1

1

C149

J5

P20
M19
D4

C455

1

R286

BATTLOW# <23>
I S T_CPU_PERF# <5>
VR_HI/LO# <4,30>
V_GATE <30>

@10PF

C453
@10PF

2

2
15K

0_0402
0_0402

2

1

PDA0
PDA1
PDA2
PDCS1#
PDCS3#

SYSTEM

2
2

1

<11> PCI_STP#
<11> CPU_STP#
<16,19,21,29> CLKRUN#
<21> SUS_STAT#
+RTCVCC

1
1

2

<9> A G P_BUSY#
R161

CLK48
CLK14
CLK66

R359
R117

1

1

RSMRST#

BATLOW#
CPUPERF#
SSMUXSEL#
VGATE/VRMPWRGD

2

2
R151
10K_0402

+RTCVCC

THRM#
SLP_S1#
SLP_S3#
SLP_S5#
PWROK
PWRBTN#
RI#
RSMRST#
GPIO25
SUSCLK
AGPBUSY#
STP_PCI#
STP_CPU#
CLKRUN#
SUSSTAT#
INTRUDER#

U20
B14
A14
B15

1

<22> THRM#
<11,22> SLP_S1#
<22> SLP_S3#
<22> SLP_S5#
<16,25> SYS_PWROK
<23> PWRBTN_OUT#
<23> SWI#
<25> RSMRST#
<14> FWH_WPTBL#
<19,20> RTCCLK

+3VS

AA13
D14
W16
AB18
R20
W21
AA17
R21
W15
AA18
Y11
A15
C14
V21
Y17
T19

2

D

THRM#
SLP_S1#
SLP_S3#
SLP_S5#
SYS_PWROK

<17>

C

SDA0 <17>
SDA1 <17>
SDA2 <17>
SDCS1# <17>
SDCS3# <17>
SDDREQ <17>
SDDACK# <17>
SDIOR# <17>
SDIOW# <17>
SDIORDY <17>

B

SDD[0..15]

SDD[0..15]

<17>

ICH-2M

1

C486

1
C152

RP19
USBP3+
USBP3USBP1+
USBP1-

27PF

4
3
2
1

USBP2+
USBP2USBP0+
USBP0-

5
6
7
8

2
5PF

8
7
6
5
8P4R-15

USB2_D+ <18>
USB2_D- <18>
USB0_D+ <18>
USB0_D- <18>

CP7
8P4C-33PF

RP22
8P4R-15K

1
2
3
4

RP20
8P4R-15K

Placement close to ICH2-M (U10)
Modify on ST 11/3/2000

1
2
3
4

4
3
2
1

1
2

27PF

2

C485

2 ICH_AC_SYNC
22_0402
2 ICH_AC_SDOUT
22_0402

1
C151

2
5PF

5
6
7
8

1
R427
1
R428

IAC_SYNC

IAC_SDATAO

8
7
6
5

<27,29>
<27,29>

A

A

CLOSE TO ICH2-M(< 1 inch)

Compal Electronics,Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

ICH2-m-B (FW82801BAM)
Size

4

3

2

Rev
2.0

888L2 Main Board
Date:

5

Document Number

T h ursday, January 11, 2001

Sheet
1

15

of

42

5

4

3

2

PCI

1

+3VS

+1_8VS
U10C
RP18

+3VS
PIRQC# <14,19>
PIRQD# <14,29>
SIRQ <14,19,21>
PLOCK# <14,19>

+3VS
10P8R-8.2K

RP37
<14>
<14,29>
<14,29>
<14,19>

REQ#0
REQ#1
REQ#2
REQ#3

REQ#0
REQ#1
REQ#2
REQ#3

1
2
3
4
5

+3VS

10
9
8
7
6

+3VS

GNT#0
GNT#1
GNT#2
GNT#3

GNT#0
GNT#1
GNT#2
GNT#3

<14>
<14,29>
<14,29>
<14,19>

10P8R-8.2K

C

+3VS

C448

C443

C449

1000PF

1000PF
2

.1UF

2

.1UF

1

1

C470

.1UF

+3VS

1

C447

2

.1UF

1

C446

.1UF

<15,19,21,29>

2

1

C462

2

2

2

.1UF

1

1

C463

4.7UF_10V_0805

B

2

1

C466
+

CLKRUN#

2

10K_0402
2

1

R148
1

.1UF

1

1

C116

C450
1000PF

C139
1000PF

2

.1UF

2

C458

2

2

2

.1UF

1

C461

2

10UF_10V_1206

2

.1UF

2

C452

1

1

C135
+

1

1

1

+1_8VS

C467
10UF_10V_1206

V5REF1
V5REF2
VCCSUS1_8_1
VCCSUS1_8_2
VCCSUS1_8_3
VCCSUS3_3_1
VCCSUS3_3_2
VCCLAN1_8_1
VCCLAN1_8_2
VCCLAN3_3_1
VCCLAN3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
V_CPU_IO_1
V_CPU_IO_2
VCC1_8_7
VCCRTC
V5REF_SUS

EEPROM
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

K2
M20

+5VS

R118
1K_0402

D4
1SS355
+VCC5REF

V14
V15
V16

C134

C125

+1_8VALW

.1UF
1UF

T18
U18
H5
J5

1
R367

2
0_0402

+1_8VALW

F5
G5

1
R145

2
0_0402

+3VALW

+3VALW

V17
V18

C

+CPU_IO

D12
D13

+1_8VS

D2
U21

1
2
1K_0402 R159

V19

+3VALW

1
C150

K4
J3
J4
K3

G3
G2
G1
H1
F3
F2
F1
H2
Y16

+RTCVCC

2
.1UF
LAN_EECS <29>
LAN_EECLK <29>
LAN_EEDO <29>
LAN_EEDI <29>

1
R347

LAN
LAN_CLK
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
LAN_RSTSYNC
LAN_PWROK

+3VS

1

10
9
8
7
6

D

2

RP21
1
2
3
4
5

<14,19,29> IRDY#
<14,19,29> TRDY#
<14,19,29> DEVSEL#
<14,19,29> FRAME#

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
GND70
GND71

E14
E15
E16
E17
E18
F18
G18
H18
J18
P18
R18
R5
T5
U5
V5
V6
V7
V8

2

A1
A2
A10
B1
B2
B3
B9
B10
C2
C3
C4
C9
D5
D6
D7
D8
D9
E6
E7
E8
E9
J10
J11
J12
J13
J14
J9
K10
K11
K12
K13
K14
K9
L10
L11
L12
L13
L14
L9
M10
M11
M12
M13
M14
M9
N10
N11
N12
P9
P14
P13
P12
P11
P10
N9
N14
N13
A21
A22
B21
B22
AA1
AA2
AA21
AA22
AB1
AB2
AB21
AB22
K1
D3

VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCC3_3_7
VCC3_3_8
VCC3_3_9
VCC3_3_10
VCC3_3_11
VCC3_3_12
VCC3_3_13
VCC3_3_14
VCC3_3_15
VCC3_3_16
VCC3_3_17
VCC3_3_18

1

10P8R-8.2K

VCC1_8_1
VCC1_8_2
VCC1_8_3
VCC1_8_4
VCC1_8_5
VCC1_8_6

1

PIRQA#
<14,19>
PIRQB#
<14,29>
REQ#4 <14>
GNT#4 <14>

2

D10
E5
K19
L19
P5
V9

+3VS

1

+3VS
D

10
9
8
7
6

2

1
2
3
4
5

<14,19,29> PERR#
<15> OVCUR#1
<14,19,29> STOP#
<14,19,29> SERR#

R146

1

2
@10K_0402

2

LAN_PHYCLK <29>
LAN_RXD0 <29>
LAN_RXD1 <29>
LAN_RXD2 <29>
LAN_TXD0 <29>
LAN_TXD1 <29>
LAN_TXD2 <29>
LAN_PHYRST
<29>
SYS_PWROK
<15,25>

B

0_0402

1
C115
.1UF

A

2

C459
.1UF
2

C460
.1UF

.1UF
2

2

+CPU_IO

1

C465

.1UF

A

+3VALW

2

C464

1

1

+1_8VALW

1

ICH-2M

Compal Electronics,Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

ICH2-m-C (FW82801BAM)
Size

4

3

2

Rev
2.0

888L2 Main Board
Date:

5

Document Number

T h ursday, January 11, 2001

Sheet
1

16

of

42

1

2

3

4

5

6

7

8

IDE,CD-ROM & FDD Module CONN.
+5VS
+5VS

R343
100K_0402

+5VS
R346
100K_0402

3

PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

1

2

2
R342
100K_0402

5

2

1

D14
HDD_LED#

1
3

SIDEACT#

Q43
U30
4

ACTLED#

DTA114YKA
A

2

10K
C

RB717F
TC7S08F

1

DRV0#
MASTER
1
R362

2
470

1
R173
+5VS

ATA66S/PDIAG#
PDA2
PDCS3#

PDA2 <15>
PDCS3# <15>

+5VS

2
470

ACTLED

<18>

+5VS

2

PCSEL

R336
10K_0402

+3VALW

R335
10K_0402

<22> S I DE_CS_M#/S

U29D
74LVC14

9

8

IDE_CSEL_M#

2
G

Q42
2N7002

JP8

IDE_CSEL_S

D

1

14

1

1

HDD

Q41
2N7002
S

IDE_CSEL_M#

1
R334

2
470

1
R337

2
470
B

A T A66P/PDIAG

PDDREQ

+5VS
PDD7

2 RPDDACK#
22_0402
2 RIRQ14
22_0402
2
@5.6K_0402
2
33PF
1
@10K_0402

+5VS

+5VS

HEADER 2X25

PDIORDY

1
R351

C441

4.7UF_10V_0805

C440

1

2
0

1
R144
1
R142
1
R149
1
C143
2
R150

.1UF

C502
22UF_10V_1206

2

CD_PDIAG 1
SDA2
R31
SDCS3#

IRQ14

<14> IRQ14

1

PDDACK#

<15> PDDACK#

SDDACK#

2

+5VS

<27>

SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
SDDREQ
SDIOR#

1

SDIOW#
SDIORDY
RIRQ15
SDA1
SDA0
SDCS1#
SIDEACT#

INT_CD_R

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

MODRST#
SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0

D

2
G

S
3

<27> INT_CD_L
<27> INT_CD_GND

E

2

HDD 44P

+5VS

B

47K

B

1

2

3

PDDREQ
PDIOW#
PDIOR#
PDIORDY
RPDDACK#
RIRQ14
PDA1
PDA0
PDCS1#
HDD_LED#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

3

<15> PDA1
<15> PDA0
<15> PDCS1#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

2

<15> PDDREQ
<15> PDIOW#
<15> PDIOR#
<15> PDIORDY

PIDERST#
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0

1

A

JP13

1

<15> PDD[0..15]
<15> PIDERST#

+5VS

PDD[0..15]

HDD CAP.

2
1K_0402

CDROM/DVD
RP17

C

1
2
3
4
5

+5VSMOD

<21> TRK0#
<21> 1.6M_EN#
<23> MODPRES#
<15> SDA2
D

<15> SDIOR#

TRK0#
MODPRES#
RSDDACK#
SDD14
SDD11
SDD8

Q40
SI3456DV
6
5
2
1

<27>

DISKCHG#
INDEX#
WRPRT#
TRK0#

2
G
Q44
2N7002

<22> MODEN#

DRV0# <21>
DIR# <21>
SDA1

1

CDROM/DVD CAP.

1
100K_0402

A T A66P/PDIAG
IDE_CSEL_S
SDD2
SDD5
MODRST#

8
7
6
5
8P4R-1K

2

SDIORDY <15>
SDDREQ <15>

DRV0#
DIR#
SIDEACT#

1
2
3
4

R341

MTR0# <21>
STEP# <21>

SDIORDY
SDDREQ
SDD13
SDD10

<15> SDDACK#
<14> IRQ15

D

SDDACK#
IRQ15
SDDREQ

C445
.01UF

S

SDD7

1
R131
1
R129
1
R132
1
C117
1
R133

+5VSMOD

2 RSDDACK#
22_0402
2 RIRQ15
22_0402
2
@5.6K_0402
2
33PF
2
@10K_0402

MODRST#

+5VS

SI3456DV: NCHANNEL
VGS: 4.5V, RDS: 65mOHM
Id(MAX): 5.1A

<14>

SDIORDY 2
R130

C444
.1UF

D

SECOND MODULE CAP.

1
1K_0402

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

MODULE
FDD/CDROM/DVD

IDE/FDD MODULE
Size

3

4

5

6

Document Number

Rev
2.0

888L2 Main Board
Date:

2

C442

10UF_10V_1206

<15>

COMBO-60P

1

C49
.1UF

10UF_10V_1206

RP16
4

+12VALW

MTR0#
STEP#

C43

+5VS

+5VSMOD

1

INT_CD_GND

SDD1
SDD4
SDD7

+5VS

2

MOD_CD_L <27>
WGATE# <21>
CD/FDD# <23>
SDA0 <15>

2

MOD_CD_L
WGATE#

2

SDD0
SDD3
SDD6

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

1

RIRQ15

C

+5VS

2

DISKCHG#
WRDATA#

+5VS

10P8R-1K
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

1

SDD15
SDD12
SDD9

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

STEP#
MTR0#
DRV0#
RDATA#

3

WRPRT#

JP11
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

2

<21> DISKCHG#
<21> WRDATA#
<21> INDEX#
<15> SDCS1#

MOD_CD_R
H1SEL#
RDATA#

1

<27> MOD_CD_R
<21> H1SEL#
<21> RDATA#
<15> SDCS3#
<21> WRPRT#
<15> SDIOW#

3

<15> SDD[0..15]

+5VS

SDD[0..15]

10
9
8
7
6

1

WRDATA#
WGATE#
H1SEL#
DIR#

T h ursday, January 11, 2001
7

Sheet

17

of
8

42

A

B

C

D

E

+3VS

USB&LED INTERFACE

1

USB_AS USB_BS

R386
100K_0402

3

1

+3VALW
R385
100K_0402

U33
OC1#
OUT1
OUT2
OC2#

B
1
R388

2
47K_0402

OVCUR#0

<15>

47K

E

DTA114YKA
4

2

<23> PWR_LED#

10K
C

1
R389

2
47K_0402

OVCUR#2
C479

TPS2042

C480

USB_A
L11
1
2
FBM-11-451616-800A

1
R174

2

.1UF

2

.1UF

USB_AS

<15>
1

GND
IN
EN1#
EN2#

8
7
6
5

1

1
2
3
4

1

4

2

2

Q20
+5VS

USB_BS
L9
1
2
FBM-11-451616-800A

2
470

PWR_LED

USB_B

+3VALW

1
C17

2
22PF

JP6

.1UF

150UF_E_10V .1UF

1

C9
+

<17> ACTLED

3

2
2

R14
R13

USB0_DDUSB0_DD+
GND_USBA

VCC VCC
D0- D1D0+ D1+
VSS VSS

USB2_DDUSB2_DD+
GND_USBB

0 1
0 1

R15
R12

USB2_DUSB2_D+

<15>
<15>

11
12

.1UF
2

FBM-11-451616-800A

C19

G3
G4

G1
G2

9
10

C18

2

.1UF

2

Molex-67300

+3VS

L12
FBM-11-451616-800A
2

L13

2
2

1

1

1

1
1

5
6
7
8

1

0
0

1
2
3
4

PWR_LED

<22> CAP_LED#
<22> NUM_LED#
<22> SRL_LED#

JP5
<15> USB0_D<15> USB0_D+

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

2

C15

2

150UF_E_10V

<23> BAT1_LED#
<23> BAT2_LED#

C20

1

C170
+

INT_MIC

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

<28>

VDDA
ON/OFFBTN

<25>

KSO17 <22>
KSI0 <22,23>
KSI1 <22,23>
KSI2 <22,23>
KSI3 <22,23>
KSI4 <22,23>
KSI5 <22,23>
+5VS

3

+5V

SWITCH_CONN

M15
S T A NDOFF_SUPPORT_TB
C315D177

PAD25
2.2x3 PAD

PAD26
2.2x3 PAD

PAD27
2.2x3 PAD

PAD28
2.2x3 PAD

PAD29
2.2x3 PAD

PAD30
2.2x3 PAD

PAD31
2.2x3 PAD

PAD32
2.2x3 PAD

1

M3
PDH
C276D169

M7
PDH
C276D169

M6
PDH
C276D169

CFD15
FIDUCIAL

M4
PDH
C276D128

CFD16
FIDUCIAL

2

1

1

GND7
PDH
SMD197X197

GND8
GND9
PDH
PDH
SMD197X197 SMD197X197

GND1
PDH
SMD197

GND2
PDH
SMD197

GND3
PDH
SMD197

GND4
PDH
SMD197

GND10
PDH
SMD197X225

GND11
PDH
SMDO280X118

GND12
PDH
SMDO280X118

1

1

1

1

1

1

1

1

1

GND5
GND6
PDH
PDH
SMD197X225 SMD197X197

1

M12
PDH
C276D128

1

M11
PDH
C236D118

1

M16
PDH
T394B304D128

1

M8
PDH
T394B295D128

1

M5
PDH
C295D147

1

1

M1
PDH
C276D128

1

M23
S T D F_SUPPORT_VGA_CACHE
C315D177

1

M9
S T D F _SUPPORT_VGA_CACHE
C315D177

1

1

M10
S T A N DOFF_SUPPORT_KB
C315D177

1

1

1

1
1

M2
PDH
C276D169

CFD7
FIDUCIAL

1

PAD24
2.2x3 PAD

M22
NON-PDH
O177X98D177X98N

CFD4
FIDUCIAL

1

PAD23
2.2x3 PAD

M21
NON-PDH
O177X98D177X98N

CFD9
FIDUCIAL

1

PAD22
2.2x3 PAD

M20
NON-PDH
O211X67D211X67N

CFD5
FIDUCIAL

1

PAD21
2.2x3 PAD

CFD13
FIDUCIAL

1

PAD20
2.2x3 PAD

CFD10
FIDUCIAL

1

PAD19
2.2x3 PAD

CFD6
FIDUCIAL

1

PAD18
2.2x3 PAD

M19
NON-PDH
O211X67D211X67N

CFD11
FIDUCIAL

1

PAD17
2.2x3 PAD

M18
NON-PDH
O211X67D211X67N

CFD8
FIDUCIAL

1

M17
NON-PDH
O211X67D211X67N

CFD3
FIDUCIAL

1

PAD16
2.2x3 PAD

CFD2
FIDUCIAL

1

PAD15
2.2x3 PAD

CFD1
FIDUCIAL

1

PAD14
2.2x3 PAD

CFD14
FIDUCIAL

1

PAD13
2.2x3 PAD

CFD12
FIDUCIAL

1

PAD12
2.2x3 PAD

FD3
FIDUCIAL

1

PAD11
2.2x3 PAD

FD4
FIDUCIAL

1

PAD10
2.2x3 PAD

FD1
FIDUCIAL

1

FD6
FIDUCIAL

1

PAD9
2.2x3 PAD

2

FD2
FIDUCIAL

1

FD5
FIDUCIAL

1

PAD8
2.2x3 PAD

1

PAD7
2.2x3 PAD

1

PAD6
2.2x3 PAD

1

PAD5
2.2x3 PAD

1

PAD4
2.2x3 PAD

1

PAD3
2.2x3 PAD

1

PAD2
2.2x3 PAD

1

PAD1
2.2x3 PAD

1

1

PAD33
CLIP
SMD87X134

PAD34
CLIP
SMD87X134

PAD35
CLIP
SMD87X134

PAD36
CLIP
SMD87X134

PAD37
CLIP
SMD87X134

PAD38
5x5 PAD
SMD197X197

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

USB & FRONT PANEL I/F
Size

B

C

D

Rev
2.0

888L2 Main Board
Date:

A

Document Number

T h ursday, January 11, 2001

Sheet
E

18

of

42

8

7

6

5

4

S1_A[0..25]
S1_D[0..15]

+3VS

<20>

S1_D[0..15]

<20>

S1_IOWR#
S1_IORD#
S1_OE#
S1_CE2#

2

+3VS
PCMRST#

2

CLK_PCI_PCM

R289
@33_0402

<14,29>
<14,29>
<14,29>
<14,29>

13
25
36
47

C/BE#3
C/BE#2
C/BE#1
C/BE#0

R287
100_0402
1
2
CLK_PCI_PCM

AD19

1

<11> CLK_PCI_PCM
<14,16,29> DEVSEL#
<14,16,29> FRAME#
<14,16,29> IRDY#
<14,16,29> TRDY#
<14,16,29> STOP#
<14,29> PAR
<14,16,29> PERR#
<14,16,29> SERR#
<14,16> REQ#3
<14,16> GNT#3
<14,16> PIRQA#
<14,16> PIRQC#
<14,16> PLOCK#
<7,12,14,21,29>
PCIRST#

C384
@10PF

B

<23> PCM_PME#
<15,16,21,29> CLKRUN#
<24> PCM_RI#
<28> PCM_SPK#

SIRQ

LEDO
IRQ11

163
208
72
128
133
193

IRQ7

205
206

IRQ5/SERIRQ#
IRQ7/SIN#/B_VPP_PGM

79
134
180

124
122
121
120
119
116
113
111
109
107
105
103
102
100
99
83
81
80
78
77
75
74
73
71
68
67
66
65
64
63
62
59
A_D10/CAD31
A_D9/CAD30
A_D1/CAD29
A_D8/CAD28
A_D0/CAD27
A_A0/CAD26
A_A1/CAD25
A_A2/CAD24
A_A3/CAD23
A_A4/CAD22
A_A5/CAD21
A_A6/CAD20
A_A25/CAD19
A_A7/CAD18
A_A24/CAD17
A_A17/CAD16
A_IOWR/CAD15
A_A9/CAD14
A_IORD#/CAD13
A_A11/CAD12
A_OE#/CAD11
A_CE2#/CAD10
A_A10/CAD9
A_D15/CAD8
A_D7/CAD7
A_D13/CAD6
A_D6/CAD5
A_D12/CAD4
A_D5/CAD3
A_D11/CAD2
A_D4/CAD1
A_D3/CAD0

C239
GRST#
A_SKT_VCC
A_SKT_VCC
A_REG#/CCBE3#
A_A12/CCBE2#
A_A8/CCBE1#
A_CE1#/CCBE0#

B_CE1#/CCBE0#
B_A8/CCBE1#
B_A12/CCBE2#
B_REG#/CCBE3#
B_SKT_VCC
B_SKT_VCC
B_SKT_VCC
OZ6933TQFP

S2_D10
S2_D9
S2_D1
S2_D8
S2_D0
S2_A0
S2_A1
S2_A2
S2_A3
S2_A4
S2_A5
S2_A6
S2_A25
S2_A7
S2_A24
S2_A17
S2_IOWR#
S2_A9
S2_IORD#
S2_A11
S2_OE#
S2_CE2#
S2_A10
S2_D15
S2_D7
S2_D13
S2_D6
S2_D12
S2_D5
S2_D11
S2_D4
S2_D3

14
26
28
44
57
101
129
177
+3VS
1

CORE_VCC
CORE_VCC
CORE_VCC

PCI_VCC
PCI_VCC
PCI_VCC
PCI_VCC

AUX_VCC

IRQ12/PME#
IRQ14/CLKRUN#
IRQ15/RI_OUT#
SPKR_OUT#
LEDO#/SKTA_ACTV
IRQ11/SKTB_ACTV

D

U24

B_BVD1/CSTCHG
B_BVD2/CAUDIO
B_CD2#/CCD2#
B_CD1#/CCD1#
B_VS2/CVS2
B_VS1/CVS1
B_R2_A18/RFU
B_R2_D14/RFU
B_R2_D2/RFU
B_RST/CRST#
B_WP/CCLKRUN#
B_A19/CBLOCK#
B_RDY_IRQ#/CINT#
B_WE#/CGNT#
B_INPACK#/CREQ#
B_WAIT#/CSERR#
B_A14/CPERR#
B_A13/CPAR
B_A20/CSTOP#
B_A21/CDEVSEL#
B_A22/CTRDY#
B_A15/CIRDY#
B_A23/CFRAME#
B_A16/CCLK

IDSEL
PCI_CLK
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PERR#
SERR#
PCI_REQ#
PCI_GNT#
IRQ9/INTA#
IRQ4/INTB#/A_VPP_PGM
LOCK#
RST#

GND
GND
GND
GND
GND
GND
GND
GND

<14,16,21>

15
1
31
27
29
30
32
35
33
34
3
2
203
204
58
207

C/BE3#
C/BE2#
C/BE1#
C/BE0#

B_D10/CAD31
B_D9/CAD30
B_D1/CAD29
B_D8/CAD28
B_D0/CAD27
B_A0/CAD26
B_A1/CAD25
B_A2/CAD24
B_A3/CAD23
B_A4/CAD22
B_A5/CAD21
B_A6/CAD20
B_A25/CAD19
B_A7/CAD18
B_A24/CAD17
B_A17/CAD16
B_IOWR#/CAD15
B_A9/CAD14
B_IORD#/CAD13
B_A11/CAD12
B_OE#/CAD11
B_CE2#/CAD10
B_A10/CAD9
B_D15/CAD8
B_D7/CAD7
B_D13/CAD6
B_D6/CAD5
B_D12/CAD4
B_D5/CAD3
B_D11/CAD2
B_D4/CAD1
B_D3/CAD0

C

O 2 MICRO CORP.
CARDBUS CONTROLLER
OZ6933T (TQFP)

<20,22>
S1_VCC

A_A16/CCLK
A_A23/CFRAME#
A_A15/CIRDY#
A_A22/CTRDY#
A_A21/CDEVSEL#
A_A20/CSTOP#
A_A13/CPAR
A_A14/CPERR#
A_WAIT#/CSERR#
A_INPACK#/CREQ#
A_WE#/CGNT#
A_RDY_IRQ#/CINT#
A_A19/CBLOCK#
A_WP/CCLKRUN#
A_RST/CRST#
A_R2_D2/RFU
A_R2_D14/RFU
A_R2_A18/RFU
A_VS1/CVS1
A_VS2/CVS2
A_CD1#/CCD1#
A_CD2#/CCD2#
A_BVD2/CAUDIO
A_BVD1/CSTSCHG

199
197
196
195
194
191
189
187
185
183
181
178
176
175
174
158
156
155
154
153
151
150
149
148
144
142
141
140
139
138
137
135

AD[0..31]

IRQ3/A_VCC_3#
SCLK/A_VCC_5#
SDATA/B_VCC_3#
SLATCH/SMBCLK/B_VCC_5#
IRQ9/A_VPP_VCC_PGM
IRQ10/B_VPP_VCC_PGM

AD[0..31]

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

87
132
131
130
115
146

<14,29>

4
5
7
8
9
10
11
12
16
17
18
19
20
22
23
24
38
39
40
41
42
43
45
46
48
49
51
52
53
54
55
56

6
21
37
50

127

D

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

1

S1_IOWR# <20>
S1_IORD# <20>
S1_OE# <20>
S1_CE2# <20>

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

+3VALW

S1_A[0..25]

3

117
98
60
112
97
82
70
93
96
95
94
92
90
84
86
108
110
89
91
88
125
106
123
69
85
76
104
61
126
114
118
192
190
202
136
179
152
161
145
198
182
201
164
167
165
186
184
162
159
166
168
170
171
172
169
147
157
173
188

C368

.1UF

S1_A12
S1_A8

R2481
S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A13
S1_A14

332

C351

.1UF

.1UF

S1_REG#

<20>

S1_CE1#

<20>

S1_A16

S1_WAIT# <20>
S1_INPACK#
<20>
S1_WE# <20>
S1_RDY#
<20>

S1_A19

S1_WP <20>
S1_RST <20>

S1_D2
S1_D14
S1_A18

C

S1_VS1 <20>
S1_VS2 <20>
S1_CD1# <20>
S1_CD2# <20>
S1_BVD2 <20>
S1_BVD1 <20>
S2_BVD1 <20>
S2_BVD2 <20>
S2_CD2# <20>
S2_CD1# <20>
S2_VS2 <20>
S2_VS1 <20>

S2_A18
S2_D14
S2_D2

S2_RST <20>
S2_WP <20>

S2_A19

S2_RDY#
<20>
S2_WE# <20>
S2_INPACK#
<20>
S2_WAIT# <20>

S2_A14
S2_A13
S2_A20
S2_A21
S2_A22
S2_A15
S2_A23
R2471

B

332

S2_A8
S2_A12

143
160
200

S2_A16
S2_CE1#

<20>

S2_REG#

<20>

S2_VCC

C223

C348

C360

.1UF

.1UF

.1UF

C380

2

4.7UF_10V_0805

S2_A[0..25]
C389

C387

C298

.1UF

.1UF

.1UF

SLATCH <20>
SLDATA <20>
RTCCLK <15,20>
+3VALW

A

S2_IOWR#
S2_IORD#
S2_OE#
S2_CE2#

S2_D[0..15]

S2_IOWR# <20>
S2_IORD# <20>
S2_OE# <20>
S2_CE2# <20>

S2_A[0..25]

<20>

S2_D[0..15]

<20>
A

+3VS
C385

C224

C226

C225

C227

.1UF

.1UF

.1UF

.1UF

.1UF

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

O2Micro OZ6933 Cardbus Controller
Size

7

6

5

4

3

Rev
2.0

888L2 Main Board
Date:

8

Document Number

T h ursday, January 11, 2001
2

Sheet

19

of
1

42

PCMCIA POWER CTRL.

CARDBUS SOCKET
S1_VPP

1
1
1
1

15
16
17
3
5
4
13
19
18

1

5V
5V
5V

BVPP
BVCC
BVCC
BVCC

3.3V
3.3V
3.3V

RESET
RESET#

DATA
LATCH
CLOCK

NC
NC
NC
NC

APWR_GOOD#
BPWR_GOOD#
OC#

GND

TPS2216

23
20
21
22

J1
C388
1000PF

S2_VPP

S1_D3
S1_CD1#
S1_D4
S1_D11
S1_D5
S1_D12

S2_VCC
<19> S1_CD1#

C175

6
14
26
27
28
29

4.7UF_10V_0805

12

PCMRST#

S1_D6
S1_D13
S1_D7
S1_D14
S1_CE1#
S1_D15

<19,22>
<19> S1_CE1#

S1_A10
S1_CE2#
S1_OE#
S1_VS1
S1_A11

<19> S1_CE2#
<19> S1_OE#
<19> S1_VS1
<19> S1_IORD#
<19> S1_IOWR#

C322

C347

10UF_10V_1206
2

.1UF
2

2

.1UF

C234
4.7UF_25V_1206
25V

1

S1_VCC
+

1

1

S1_VPP
C238

<19> S1_WE#
<19> S1_RDY#
S1_VCC
S1_VPP

S2_VPP

.1UF

1
R276
S2_A23
1
R252

2
S2_VCC
22K_0402
2
S2_VCC
22K_0402

<19> S1_RST
<19> S1_WAIT#

<19> S1_INPACK#
2

S1_VCC

<19> S1_REG#

S1_VCC
22K_0402

<19> S1_BVD2

22K_0402
2

<19> S1_BVD1

<19> S1_WP
<19> S1_CD2#

S1_A3
S1_INPACK#
S1_A2
S1_REG#
S1_A1
S1_BVD2
S1_A0
S1_BVD1
S1_D0
S1_D8
S1_D1
S1_D9
S1_D2
S1_D10
S1_WP
S1_CD2#
1

1

R244
S1_WP
1
R225

S1_A25
S1_A6
S1_VS2
S1_A5
S1_RST
S1_A4
S1_WAIT#

C204
1000PF
2

S1_A23

S1_A13
S1_A18
S1_A14
S1_A19
S1_WE#
S1_A20
S1_RDY#
S1_A21
S1_VCC
S1_VCC
S1_VPP
S1_VPP
S1_A16
S1_A22
S1_A15
S1_A23
S1_A12
S1_A24
S1_A7

10UF_10V_1206

<19> S1_VS2
S2_WP

S1_IORD#
S1_A9
S1_IOWR#
S1_A8
S1_A17

C307

2

2

C264
4.7UF_25V_1206
25V

C288

1

1
+

.1UF

2

1

S2_VCC
C282

2

2
S2_VPP

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
80
81

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77

80
81

78
79

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77

C390
1000PF
1

1
2
30

+3VALW

4.7UF_10V_0805

S2_D3
S2_CD1#
S2_D4
S2_D11
S2_D5
S2_D12

S2_CD1#

S2_D6
S2_D13
S2_D7
S2_D14
S2_CE1#
S2_D15

S2_CE1#

S2_A10
S2_CE2#
S2_OE#
S2_VS1
S2_A11

<19>

<19>

S2_CE2# <19>
S2_OE# <19>
S2_VS1 <19>

S2_IORD#
S2_A9
S2_IOWR#
S2_A8
S2_A17
S2_A13
S2_A18
S2_A14
S2_A19
S2_WE#
S2_A20
S2_RDY#
S2_A21
S2_VCC
S2_VCC
S2_VPP
S2_VPP
S2_A16

S2_IORD#

<19>

S2_IOWR#

S2_WE#
S2_RDY#

<19>

<19>
<19>

S2_VCC
S2_VPP

S2_A22
S2_A15
S2_A23
S2_A12
S2_A24
S2_A7
S2_A25
S2_A6
S2_VS2
S2_A5
S2_RST
S2_A4
S2_WAIT#

S2_VS2

<19>

S2_RST

<19>

S2_WAIT#

S2_A3
S2_INPACK#
S2_A2
S2_REG#
S2_A1
S2_BVD2
S2_A0
S2_BVD1
S2_D0
S2_D8
S2_D1
S2_D9
S2_D2
S2_D10
S2_WP
S2_CD2#

<19>

S2_INPACK#

<19>

S2_REG#

<19>

S2_BVD2

<19>

S2_BVD1

<19>

S2_WP <19>
S2_CD2# <19>

1

1

12V
12V

C221

78
79

C203
1000PF
2

1

7
24

8
9
10
11

2

2 C174
1UF
2 C214
.1UF
2 C187
.1UF
2 C213
.1UF
2 C181
.1UF
2 C215
<19> SLDATA
.1UF
<19> SLATCH
2 C180
<15,19> RTCCLK
.1UF

AVPP
AVCC
AVCC
AVCC

1

1

VCC_5V

S1_A[0..25]
S1_D[0..15]
S2_A[0..25]
S2_D[0..15]

<19> S1_A[0..25]
<19> S1_D[0..15]
<19> S2_A[0..25]
<19> S2_D[0..15]

2

25

+5VALW

S1_VPP
S1_VCC

U18

1

+12VALW

P C MCIA CONN P154
J5
PCMCIA CONN P154
BERG62183-001T

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

FOXCONN Cardbus CONN .154PIN
Size

Document Number

Rev
2.0

888L2 Main Board
Date:

T h ursday, January 11, 2001

Sheet

20

of

42

5

4

3

2

1

+3VS

+3VS

<14,15>
<14,15>
<14,15>
<14,15>

2

2

4.7UF_10V_0805
+3VS

1

D

R137
4.7K_0402

LAD0
LAD1
LAD2
LAD3

2

<11> CLK_PCI_SIO
<7,12,14,19,29> PCIRST#
<14,15> LFRAME#
<15> LDRQ#0

<15> SUS_STAT#
<15,16,19,29> CLKRUN#
<14,16,19> SIRQ
<15,22> EC_SMI#
CLK_14M_SIO

<11> CLK_14M_SIO
+3VS

1

1

CLK_PCI_SIO

2

@33_0402

1

@33_0402
2

R136

1

R135

C133

<17> DISKCHG#
<17> H1SEL#
<17> RDATA#
<17> WRPRT#
<17> TRK0#
<17> WGATE#
<17> WRDATA#
<17> STEP#
<17> DIR#
<17> DRV0#
<17> MTR0#
<17> INDEX#
<17> 1.6M_EN#

C132

2

@15PF

2

@15PF

+3VS

U11

2
10K_0402

LAD0
LAD1
LAD2
LAD3

15
16
17
18

CLK_PCI_SIO
PCIRST#
LFRAME#
LDRQ#0

8
9
12
11
7
6
10
19

CLKRUN#
SIRQ
1
2 LPCSMI#
R138
@0_0402
CLK_14M_SIO
1
2
R139
@10K_0402
DISKCHG#
H1SEL#
RDATA#
WRPRT#
TRK0#
WGATE#
WRDATA#
STEP#
DIR#
DRV0#
MTR0#
INDEX#
1.6M_EN#

20

21
22
23
24
25
26
27
28
29
30
31
32
33
34

14
39
63
88

1
R152

C148

1000PF

2

.1UF

2

.1UF

C144

VDD
VDD
VDD
VDD

C112

1

1

C124

1

1

+3VS

LAD0
LAD1
LAD2
LAD3
LCLK
LRESET#
LFRAME#
LDRQ#
LPCPD#
CLKRUN#/GPIO36
SERIRQ
SMI#/GPIO35

PC87393

CLKIN

DSKCHG#
HDSEL#
RDATA#
WP#
TRK0#
WGATE#
WDATA#
SETP#
DIR#
DR0#
MTR0#
INDEX#
DENSEL
DRATE0/IRSL2

5
6
7
8
4
3
2
1

RP14
8P4R-10K

XA0
XA1
XA2
XA3
XSTB0#
XCNF2

<22> IRQ1

IRQ8

<22> IRQ11
<22> IRQ12

XIOR#
XIOW#
XA12
XA13
XA14
XA15
XA16
XA17
XA18

XA0/GPIO20
XA1/GPIO21
XA2/GPIO22
XA3/GPIO23
XA4/GPIO24/XSTB0#
XA5/XSTB1#/XCNF2
XA6/GPIO26/PRIQA/XSTB2#
XA7/GPIO27/PIRQB
XA8/GPIO30/PIRQC
XA9/GPIO31/MTR1#/PIRQD
XA10/GPIO32/XIORD#/MDRX
XA11/GPIO33/XIOWR#/MDTX
XA12/GPIO10/JOYABTN1/RI2#
XA13/GPIO11/JOYBBTN1/DTR2#_BOUT2
XA14/GPIO12/JOYAY/CTS2#
XA15/GPIO13/JOYBY/SOUT2
XA16/GPIO14/JOYBX/RTS2#
XA17/GPIO15/JOYAX/SIN2
XA18/GPIO16/JOYBBTN0/DSR2#
XA19/DCD2#/JOYABTN0/GPIO17

PC87393

B

IRTX
IRRX1
IRRX2_IRSL0
IRSL1
IRSL3/PWUREQ#

XD0/GPIO00/JOYABTN1
XD1/GPIO01/JOYBBTN1
XD2/GPIO02/JOYAY
XD3/GPIO03/JOYBY
XD4/GPIO04/JOYBX
XD5/GPIO05/JOYAX
XD6/GPIO06/JOYBBTN0
XD7/GPIO07/JOYABTN0
XWR#/XCNF1
XRD#/GPIO34/WDO#
XIOWR#/XCS1#/MTR1#/DRATE0
XIORD#/GPIO37/IRSL2/DR1#
XCS0#/DR1#/XDRY/GPIO25

52
50
48
46
45
44
43
42

LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

35
36
37
40
41
47
49
51
53
54

LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTSLCTIN#
LPTINIT#
LPTERR#
LPTAFD#
LPTSTB#

55
56
57
58
59
60
61
62

DCDA#
DSRA#
RXDA
RTSA#
TXDA
CTSA#
DTRA#
RIA#

LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

<24>
<24>
<24>
<24>
<24>
<24>
<24>
<24>

D

LPTSLCT <24>
LPTPE <24>
LPTBUSY <24>
LPTACK# <24>
LPTSLCTIN# <24>
LPTINIT# <24>
LPTERR# <24>
LPTAFD# <24>
LPTSTB# <24>

DCDA# <24>
DSRA# <24>
RXDA <24>
RTSA# <24>
TXDA <24>
CTSA# <24>
DTRA# <24>
RIA# <24>

70
69
68
67
66

C

3
2
1
100
99
98
97
96

XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7

4
5
73
71
72

XMEMW#
XMEMR#

XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7

XIOCHRDY

2
10K_0402

<22>
<22>
<22>
<22>
<22>
<22>
<22>
<22>

XMEMW# <22>
XMEMR# <22>
EC_FLASH#
XIOCHRDY

1
R108

<22>
<22>

+3VS

13
38
64
89

VSS
VSS
VSS
VSS

<22> XIOR#
<22> XIOW#
<22> XA12
<22> XA13
<22> XA14
<22> XA15
<22> XA16
<22> XA17
<22> XA18

95
94
93
92
91
90
87
86
85
84
83
82
81
80
79
78
77
76
75
74

PNF/XRDY
SLCT/WGATE#
PE/WDATA#
BUSY_WAIT#/MTR1#
ACK#/DR1#
SLIN#_ASTRB#/STEP#
INIT#/DIR#
ERR#/HDSEL#
AFD#_DSTRB#/DENSEL
STB#_WRITE#

DCD1#
DSR1#
SIN1
RTS1#/TEST
SOUT1/XCNF0
CTS1#
DTR1#_BOUT1/BADDR
RI1#

C

<22> XA0
<22> XA1
<22> XA2
<22> XA3
<22> XSTB0#

PD0/INDEX#
PD1/TRK0#
PD2/WP#
PD3/RDATA#
PD4/DSKCHG#
PD5/MSEN0
PD6/DRATE0
PD7/MSEN1

B

Signal

Pin #

Description

BADDR

61

BASE Address Selection
"0": 2E~2F (Default)
"1": 4E~4F

TEST

58

"0": Normal (Default)

+3VS

BADDR PULL-UP :4E
BADDR PULL-DOWN:2E
(DEFAULT)
+3VS

"1": Test Mode
XCNF[2:0]

90, 4, 59

(default)

2

1

0

Function

x

0

0

No BIOS

x

0

1

Normal Mode. XRDY disabled

0

1

0

Latch Mode. XA12-19, XRDY enabled

1

1

0

Latch Mode. GPIO10~17,XRDY enabled

0

1

1

Latch Mode. XA12-19, XRDY disabled

1

1

1

Latch Mode. GPIO10~17,XRDY disabled

* 1 ROM SOLUTION

TXDA
XCNF0

1
R311

2
@10K_0402

XMEMW#
XCNF1

1
R318

2
10K_0402

XCNF2

1
R312

2
@10K_0402

XBUS RESET CONFIGURATION

DTRA#

1
R109

2
@10K_0402

Pin # 61
BASE ADDRESS CONFIGURATION

A

A

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

SUPER I/O PC87393 CHIP
Size

4

3

2

Rev
2.0

888L2 Main Board
Date:

5

Document Number

T h ursday, January 11, 2001

Sheet
1

21

of

42

4

3

+3VALW
2
R308

1
10K_0402

PFAIL#
51RST

79
164
165

<25> EC_HPOWON

<33> POK

2
10K_0402

1
R110

2
@0_0402

1
R111

2
.01UF

A_BATT_PRE#

81
82
83
84
85
86
93
94

<15> SLP_S5#
<15> SLP_S3#
<11,15> SLP_S1#

B

1
C88

95
96
97
98

<25> FAN_L_H#
<32> IREF
<32> ADPREF
DAC_BRIG

<31> A_BATT_PRE#

IREF: Charger current control
ADPREF: Adapter current control

A_BATT_PRE#

51RST

ECAGND

<25> FAN0_TACH
<25> FAN1_TACH

SUSP#

61
62
63
64
65
68

<24> RING#
<4,12,23,31> SMB_EC_CK1
<4,12,23,31> SMB_EC_DA1
INVT_PWM
<19,20> PCMRST#
<14> GATEA20
<14> KBRST#
<25> ON/OFF

71
72
73
74
75
76
77
78

<18> SRL_LED#
<18> NUM_LED#
<18> CAP_LED#
<24,26,30,33>

PAD_LED#

SMB_EC_CK1
SMB_EC_DA1

GATEA20
KBRST#

1UF
C130
+RTCVCC

1

28

2
CRY1

1

R329

2

PB0/RING#
PB1/SCL
PB2/SDA
PB3/TA
PB4/TB/EXINT10
PB5/GA20
PB6/HRSTO#
PB7/SWIN

VBAT

32KX1/32CLKIN
32KX2

1

1

51K
33PF

PC87570-176PIN

2

92
AGND
KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15

PSDAT1
PSCLK1
PSDAT2
PSCLK2
PSDAT3/PC7
PSCLK3/PC6
PG4/WR1#
PG3/SEL1#
PG2/CLK
PG0/SELIO

PH0/BST0/ENV0
PH1/BST1/ENV1
PH2/BST2/TRIS
PH3/PFS
PH4/PLI
PH5/ISE#

D8/PF0
D9/PF1
D10/PF2
D11/PF3
D12/PF4
D13/PF5
D14/PF6
D15/PF7

1

KBA18

+3VALW

R242
0_0402

+ C241

32

VCC

2

1

2

1

D

C255

2

.1UF
1

10UF_10V_1206
CE#
OE#
WE#

16

GND

+3VALW

2

+3VALW
C402

1
R288
100K_0402

.1UF
36
35
34
33
32
31
30
29

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

56
55
54
53
52
51
50
49
48
47
42
41
40
39
38
37

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

57
58
59
60
69
70

KBD_DATA
KBD_CLK
PS2_DATA
PS2_CLK
TP_DATA
TP_CLK

113
106
107
110

THRM#

14
12
FWE#

13
7

ACOFF
EC_SMI#
EC_ON

145
146
147
148
149
150
151
152

2
100K_0402

1

3

FWR#

+5VS

EC_FLASH#

<21>

Q33
2N7002

RP6

U25D
74LVC32

FSEL#
KBA18
KBA15
KBA17

1
2
3
4

8
7
6
5
8P4R-10K

+3VS

RP35
10
9
8
7
6

+5VS

R122
10K_0402

R116
10K_0402

PS2_DATA
PS2_CLK

KBD_DATA
KBD_CLK
TP_DATA
TP_CLK
+5VS

10P8R-10K
+3VALW
RP30
1
2
3
4

FRD#
SELIO#
BKOFF#
KBD_DATA <25>
KBD_CLK <25>
PS2_DATA <25>
PS2_CLK <25>
TP_DATA <23>
TP_CLK <23>

8
7
6
5

B

8P4R-10K

+3VALW

<17>
R310
4.7K_0402

KSO16 <23>
KSO17 <18>
ACOFF <32>
EC_SMI# <15,21>
EC_ON <25>
SCI# <15>

EN_FAN0# <25>
EN_FAN1# <25>
VR_ON <26,30>
FSTCHG <32>
MUTE <27>
SYSON <26,31>
ACIN <15,31>
BKOFF# <13>

1
2
3
4
5

R124
10K_0402

GATEA20
KBRST#
THRM#

THRM# <15>
S I DE_CS_M#/S
MODEN# <17>
SELIO# <23>

104
103
102
101
100
99

11

C

R294

1

2
G

2

R316
4.7K_0402

SMB_EC_DA1
SMB_EC_CK1

ADB[0..7]
EC_SMI#

1
R98

2
10K_0402

KBA[0..17]
KSI[0..7]
KSO[0..15]

Title

ADB[0..7]
KBA[0..17]
KSI[0..7]
KSO[0..15]

<23>
<23>
A

<18,23>
<23>

Compal Electronics, Inc.
KBC/EC PC87570EXT

2

1
2

PC0
PC1
PC2
PC3/EXINT0
PC4/EXINT11
PC5/EXINT15

R330
C435
2

32.768KHZ

PD0/AD0
PD1/AD1
PD2/AD2
PD3/AD3
PD4/AD4
PD5/AD5
PD6/AD6
PD7/AD7

CRY2

22M
X2

C434
10PF

DA0
DA1
DA2
DA3

GND
GND
GND
GND
GND

A

25
27

PFAIL#
HMR
HPWRON

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

1

D

<21> IRQ11
<21> IRQ12

IRQ1
IRQ8#
IRQ11
IRQ12

VPP

13
14
15
17
18
19
20
21

2

1

S

156
155
154
153

<21> IRQ1

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

111
112
105

FRD#
FWR#
FSEL#

22
24
31

D0
D1
D2
D3
D4
D5
D6
D7

1

3

2
1K_0402

RD/HDEN
WR0#
HRMS/SEL0#

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17

2

G

2

D

S

Q38
2N7002

<21> XMEMW#

HMEMR#
HMEMW#

HAEN
HIOCHRDY
HIOR#
HIOW#
HMEMCS#/PA0
HMEMRD#/PA1
HMEMWR#/PA2

137
138
139
140
141
142
143
144

12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30

S

1

D0
D1
D2
D3
D4
D5
D6
D7

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18

D

2

G

Q37 3
2N7002

<21> XMEMR#

HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7

114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
135
136

1

13
14
158
159
R321
1
157
162
163

2

<21> XIOCHRDY
<21> XIOR#
<21> XIOW#

PC87570

U21
39F040

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13/BE0
A14/BE1
A15/PG1/CBRD
A16/PA5/FXBUSEN
A17/PA6
A18/PE1/SHBM#

1

+5VS

100K_0402

C

Pin 130 PU for
Zero Latch

2

2

15
16
17
18
19
20
21
22

.1UF

1

R328
1

XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7

HA0
HA1
HA2
HA3
HA4
HA5
HA6
HA7
HA8
HA9
HA10
HA11
HA12
HA13
HA14
HA15
PA3/HA16
PA4/HA17
PE0/HA18

2

24
26
66
109
160

R331
10K_0402

166
167
168
169
170
171
172
173
174
3
4
5
6
7
8
9
10
11
12

1

2

1

<21> XSTB0#

XA0
XA1
XA2
XA3
XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7
XA12
XA13
XA14
XA15
XA16
XA17
XA18

N C : 1 , 2 ,43,44,45,46,87,88,89,90,131,132,133,134,175,176

<21> XA0
<21> XA1
<21> XA2
<21> XA3
<21> XD0
<21> XD1
<21> XD2
<21> XD3
<21> XD4
<21> XD5
<21> XD6
<21> XD7
<21> XA12
<21> XA13
<21> XA14
<21> XA15
<21> XA16
<21> XA17
<21> XA18

ECAGND

1

2
91
80

VCC
VCC
VCC
VCC

D

2

BLM11A20
U9

AVCC
VREF

.1UF

2

2

2

2

.1UF

1

R97
10K_0402

L18

C89
C87
1000PF
161
108
67
23

C111

.1UF 1000PF

2

C129

1

1

C426

1

1

1

KB_VCC
C128

+3VALW

L19
@BLM11A20 L17
1
2
BLM11A20

1

T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P ARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

2

1

+3VALW

2

+3VALW

+5VALW

1

5

Size

Document Number

Rev
2.0

888L2 Main Board
Date:
5

4

3

2

T h ursday, January 11, 2001

Sheet
1

22

of

42

2

3

ADB[0..7]

5

6

INPUT

KBA[0..17]
+3VS
8P4R-100K
8
7
6
5

+3VALW

1

C373
2
20

.1UF

U25B
74LVC32

14
4

KBA1

6
SELIO#

<22> SELIO#

1G
2G

C403
1

2

+3VALW

.1UF

KBA3

U25A
74LVC32

14
1

3
SELIO#

2
7

AA
LARST#

11
1

+3VALW

CC

1
R317

5
7

2
1
20K_0402

2
5
6
9
12
15
16
19

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

PWR_LED# <18>
BAT2_LED# <18>
SWI# <15>
LID_OUT# <15>
PWRBTN_OUT# <15>

VLBA#

A

1

BAT1_LED# <18>
BEEP# <28>

2
D12

BATTLOW#

<15>

1SS355

CLK
CLR

74LVC273

C425
2

1UF
+3VALW

PCM_PME#
MINI_PME#

N M 2 4 C 1 6 4 A d dress definition: 1 A2 A1# A0 B2 B1 B0 R/W#

R279
100K_0402

1

R119
100K_0402

1

1

R120
100K_0402

2

2

2

+3V

B

D0
D1
D2
D3
D4
D5
D6
D7

74LVC244

10

+3VALW

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

18
16
14
12
9
7
5
3

U28

10

1
19

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

3
4
7
8
13
14
17
18

2

<19> PCM_PME#
<12,13> ENABKL
<31> AIR_ADP#

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

GND

MINI_PME#
LID_SW#
PCM_PME#

VCC

2
4
6
8
11
13
15
17

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

VCC

20

.1UF

<17> MODPRES#
<17> CD/FDD#
<29> MINI_PME#

C411
2

1

U26
A

8

OUTPUT

+3VALW

RP26
1
2
3
4

7

R278
100K_0402

1

<22> ADB[0..7]
<22> KBA[0..17]

4

GND

1

AA
CC

B

+3VALW

1

+3VALW
1
C412

2
.1UF

R300
100K_0402

<4,12,22,31>
<4,12,22,31>

SMB_EC_CK1
SMB_EC_DA1

VCC
WC
SCL
SDA

A0
A1
A2
GND

1
2
3
4

2

U27
8
7
6
5

NM24C16

EC I2C Bus Address:
24C164: 1011xxx R/W#
24C16: 1010xxx R/W#

CP8

JP10

<22> KSO[0..16]
<18,22>

KSI[0..7]

KSO4
KSO5
KSO16
KSO0
KSO3
KSO2
KSI3
KSO1
KSI5
KSI6
KSI0
KSO8
KSO12
KSI7
KSO10
KSO14
KSI4
KSI2
KSI1
KSO6
KSO7
KSO9
KSO13
KSO15
KSO11

KSO[0..16]
KSI[0..7]

25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

CP9
KSO3
KSO2
KSO1
KSO8

32

8
7
6
5

1
2
3
4

<27>
<27,28>
<27>
<27,28>

@8P4C-10PF
CP10
KSO12
KSO10
KSO14
KSO6

30
29
28
27
26

8
7
6
5

1
2
3
4

KSO11

1
C487

31

1
3
5
7
9
11
13
15
17
19
21
23
25

2
4
6
8
10
12
14
16
18
20
22
24

2
4
6
8
10
12
14
16
18
20
22
24

TP_CLK
TP_DATA

<22>
<22>

1
2
+5VS
L22 FBM-11-451616-800A

RBAT

C145

LID_SW#

LID_CL+

.1UF

TO TOUCH PAD

CP11
8
7
6
5

INTSPK_LINTSPK_L+
INTSPK_RINTSPK_R+

1
3
5
7
9
11
13
15
17
19
21
23
25

JP 25PIN

@8P4C-10PF

KSO7
KSO9
KSO13
KSO15

C

JP12

@8P4C-10PF

1
2
3
4
@8P4C-10PF

int. kb

D

1
2
3
4

1

C

8
7
6
5

2

KSO4
KSO5
KSO16
KSO0

2
@10PF

D

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

EC Extended I/O Port
Size

2

3

4

5

6

Rev
2.0

888L2 Main Board
Date:

1

Document Number

T h ursday, January 11, 2001
7

Sheet

23

of
8

42

1

2

3

4

5

6

7

8

SERIAL & PARALLEL

SERIAL / PARALLEL PORT

+5V
A

1

A

C13
.1UF

C1

28
24

1

2

C11

1

.1UF
2
14
13
12

<21> TXDA
<21> RTSA#
<21> DTRA#

4
5
6
7
8
22
23

SUSP#

VCC

C1V+

26

27

1

C2+
C2-

V-

T1IN
T2IN
T3IN

T1OUT
T2OUT
T3OUT

R1IN
R2IN
R3IN
R4IN
R5IN

R2OUTB
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT

FORCEOFF
FORCEON

INVILID
GND

3

1

9
10
11

TXD1
RTS1#
DTR1#

20
19
18
17
16
15

COM_RI

2

C12

.1UF

1

2 C14
.1UF

1

2
L43 68
2
L41 68

1

JP2
2

L40 68
1
2
L44 68
1
2
L42 68

DCDA# <21>
RIA# <21>
RXDA <21>
CTSA# <21>
DSRA# <21>

1
2
L39
68
1
2
L38
68
1
2
L37 68

21
25

5
9
4
8
3
7
2
6
1

RI0F
DTR0F
CTS0F
TXD0F#
RTS0F
RXD0F#
DSR0F
DCD0F

DSUB-9
FOXCONN
4
3
2
1

<22,26,30,33>

C1+

4
3
2
1

2
.1UF

2

U3
1

MAX3243/MAX3243E
CP4

CP3

5
6
7
8

PARALLEL

B

+5V_PRN

D8
+5VS

2

1
1

1SS355
+3VALW

R168
2.7K_0402

LPD[0..7]

R313
20K_0402

<21> LPTSTB#

LPTSTB#

R169

1

2

33_0402

2

2

<21> LPD[0..7]

SERIAL

8P4C-47PF
5
6
7
8

8P4C-47PF

B

1

2 C158
47PF

+5VS_JP5

1

D13
1
<29> MINI_RI#

3

RING#

2

<19> PCM_RI#
C

1

RB717F

COM_RI

<22>

<21> LPTAFD#
68
<21> LPTERR#
68
<21> LPTINIT#
68
<21> LPTSLCTIN#
68

D

2
G

Q36
2N7002
3

S

2
LPD0
1
2
L3 LPD1
1
2
L25 LPD2
1
2
L5 LPD3
L1

1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13

AFD/3M#

1

1

2
L2

68

L4

68

1

FD0
ERR#
FD1

2

1

PRNINIT#
2
2

FD2
SLCTIN#
FD3

2

FD4

2

FD5

2

FD6

2

FD7

L26 68
1
L24 68

LPD4

1

LPD5

1

L23 68
L31 68
LPD6

1
L30 68

+5V_PRN

+5V_PRN

CP5
FD7
FD6
FD5
FD4

8
7
6
5

SLCT
PE
BUSY
ACK#

1
2
3
4

LPD7

CP6
8
7
6
5

1
2
3
4

<21> LPTACK#
<21> LPTBUSY
<21> LPTPE

8P4C-47PF

RP23

L29 68
2

ACK#

1
L28
68
1
2
L27
68
1
2
L34
68
1
2
L33 68

BUSY
PE
SLCT

JP3
LPTCN-25

RP24

6
7
8
9
10

10P8R-2.7K

6
7
8
9
10

10P8R-2.7K

D

<21> LPTSLCT

5
4
3
2
1

5
4
3
2
1

8P4C-47PF

1

C

+5V_PRN
FD3
SLCTIN#
FD2
PRNINIT#

CP2
1
2
3
4

8P4C-47PF

D

+5V_PRN

FD1
ERR#
FD0
AFD/3M#

8
7
6
5

CP1
1
2
3
4

8P4C-47PF
8
7
6
5

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

Serial/parallel ports
Size

2

3

4

5

6

Rev
2.0

888L2 Main Board
Date:

1

Document Number

T h ursday, January 11, 2001
7

Sheet

24

of
8

42

1

2

3

4

5

+12VALW

R205
1M

R191
33.2K_1%

1

6

-

R193
64.9K_1%

MOLEX 53398-0290

7

2
G
Q5
2N7002

1

<22> FAN_L_H#
+3VS

A

1
1

2
3

JP15
1
2
3

D

MOLEX 53398-0290
+3VS

C171
4.7UF_10V_0805

S

2
2
G
Q4
2N7002

<22> EN_FAN0#

S

D

1

1
R181
10K_0402

R177
10K_0402
S
2

2

3

1

1

D

3

2
G
Q6
2N7002

+5VALW

2SC2411K
Q26

1K_0402
R196
2

2

3

LM358

1
1

D

C168
4.7UF_10V_0805

8
+

3

1
2
3

S

1

1

5

JP14

1
1

1
2

4

1

U14B

+5VALW

2SC2411K
Q27

1

-

1K_0402
R182
2

4

+

2

LM358

+12VALW

2

2

3

R197
64.9K_1%

<22> EN_FAN1#

8

R192
1M

3

8

1

1

U14A
A

2
G
Q7
2N7002

2

2

2

R198
33.2K_1%

<22> FAN_L_H#

7

+5VALW

2

+5VALW

6

FAN1_TACH

<22>

FAN0_TACH

<22>

B

B

RTC BATT

+3VALW

BATT1
+3VALW

-

1

+3VALW
R333
47K_0402

14

U29B
74LVC14

1

2

3

4

+3V POWER

RTCBATT
RSMRST#

<15>

<13> ITP_VR_POK

+3V POWER

R325
2

100_0402
1

R326
2

100_0402
1

SYS_PWROK

D15

<22>
+RTCVCC

<15,16>

2

3

C438
.1UF

EC_HPOWON

1

14

U29A
74LVC14

2

330K

1

1

1

PWR ON CKT

2

R327
2

+

2

CHGRTC

HSM126S

PS2 CONN.

+3VALW

POWER BTN

U2

C

6
5
4

R123
100K_0402
D5

KBMF01SC6

1

F3
1
2
L32
FBM-11-451616-800A

W=40mils

4
2
1
3

1

W=40mils

C159
1UF

6

<22>

EC_ON#

<32>

DAN202U

R125
4.7K_0402
5

2

P O LYSWITCH_1.1A
4516

+3VALW

JP1
KBD/PS2_6

ON/OFF

<22> EC_ON

2

R126
1
22K_0402

EC_ON

C127

D6

1000PF

RLZ20A

2

KB_AS

1

PS2KB_VCC

2

1

+5VS

ON/OFF

3

<18> ON/OFFBTN

1

DATA OUT
VCC
CLK OUT

2

PS2_CLK

<22> PS2_CLK

DATA IN
GND
CLK IN

1

1
2
3

2

PS2_DATA

<22> PS2_DATA

1

C

2

2

22K
22K

3

Q11
DTC124EK
U1
<22> KBD_DATA
<22> KBD_CLK

KBD_DATA
KBD_CLK

1
2
3

DATA IN
GND
CLK IN

DATA OUT
VCC
CLK OUT

6
5
4

WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V

KBMF01SC6
D

D

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

PS/2/RTC/RST CKT
Size

2

3

4

5

6

Rev
2.0

888L2 Main Board
Date:

1

Document Number

T h ursday, January 11, 2001
7

Sheet

25

of
8

42

1

2

3

4

5

6

7

8

RESET & SUSPEND CKT

+12VALW
+5V
1
A

+5VS

JP19
3MM

+5VALW TO +5V Transfer

R372
100K_0402

1

2

A

2

.01UF
1M_0402

+3V

10UF_10V_1206

.1UF

1

+12VALW
2

R370
470

R298
10K_0402

12

SUSON

+3VS

JP20
3MM

1
C469

C468

2

2

3

S

+5V

1
2
3
4

1

R371

S
S
S
G

2

1

SYSON#

D
D
D
D

1

1
1
2
G
Q46
2N7002

8
7
6
5

C471

1

SI4800

U31
D

D

S
3

SUSP

<27> SUSP

SYSON#

1

2
G

2

2

+5VALW

<22,24,30,33>

Q45
2N7002

SUSP#

SUSP#

D

2
G

Q32
2N7002
3

S

+3VALW TO +3V Transfer
+3VALW

1
R121
470

+12VALW
+CPU_IO

1

B

1

D

2
G

2

2
G

Q39
@2N7002

<22,31>
S
3

3

S

SYSON#

SYSON#

D

1

VR_ON

<22,30> VR_ON

100K_0402

Q2
@2N7002

+5VALW

D
Q35
2N7002

2
G

SYSON

S
3

2

3

Q17
@2N7002
1

3

S

2
G
S

1

2

SUSON

2 SYSON#
G
Q12
2N7002

2

VR_ON#

D
22UF_10V_1206

R284

1

10UF_10V_1206

D

R1
@330_0603

1

1
12

2

.1UF
2

C131

C114

R171
@330_0603

2

R332
@100K_0402

1
C123

2

B

1
2
3
4

S
S
S
G

1

D
D
D
D

1

8
7
6
5
1

+CPU_CORE
+3VALW

+3V
SI4800

U8

1

Q63
@SMO5

+5VALW TO +5VS Transfer
+5VALW

+5VS

1
C476

C474

2

2

2

.01UF

2

S

C

22UF_10V_1206

RUNON
R375
1M_0402

R373
470

C473

1

1

D

3

2
G
Q47
2N7002

S
S
S
G

1
2
3
4

1

2

D
D
D
D

C

SUSP

SI4800

2

U32
8
7
6
5

1

R374
100K_0402

1

1

2

C472
4.7UF_10V_0805

3

+12VALW

Q48
.1UF

1

D

2
G

SUSP

3

S

+1_8VALW TO +1_8VS Transfer

2N7002
+1_8VALW

+1_8VS

2
RUNON

1

C167

R178
470

2

.1UF

2

C163
10UF_10V_1206

1

C166

2

1
2
3
4

22UF_10V_1206

D

RUNON

Q22
2N7002
2
G

Q13
2N7002
2 SUSP
G

SUSP

S
3

D

S
S
S
G

1

2

2
22UF_10V_1206

D
D
D
D

1
R134
470

.1UF

1

2

C136

1

C140

C138
10UF_10V_1206

D

8
7
6
5

+3VALW TO +3VS Transfer
1

S
S
S
G

1

D
D
D
D

1
2
3
4

2

+3VS

U12 SI4800
8
7
6
5

1

+3VALW

1

U13 SI4800

D

3

S

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

DC/DC INTERFACE
Size

2

3

4

5

6

Rev
2.0

888L2 Main Board
Date:

1

Document Number

T h ursday, January 11, 2001
7

Sheet

26

of
8

42

1

2

3

4

5

6

7

8

VDDA
+5VS

RLINEIN
ROUT-

LOUT+

5

LOUT-

INTSPK_R-

3

INTSPK_L+

10

INTSPK_L-

9

MUTEOUT

<23,28>

INTSPK_R-

<23>

INTSPK_L+

<23,28>

INTSPK_L-

1
2
1

8
4

A

S

1

LM358

3

1

1

R271

R273
5.1K

2 1
442_1%

<23>

1
68PF

R270

1

2

1
R272

2
5.11K_0.5%

5.11K_0.5%
0_0402
1
2 2
R277
C365

1
220PF

VDDA
C364

2

6
+3VS
19
B

C478
.1UF

1

1

W=25mils

C363
.1UF

C369
4.7UF_10V_0805

C270

23
24
18
20
19
21

<28> EXTMICIN

22
MD_SPK

1
C341
1
C361

<29> MD_SPK
1
R266
47K_0402

2
1

2

MONO_IN

R268
4.7K_0402

C350

<28> PC_BEEP
<15,29> AC97_RST#
<15,29>

IAC_SYNC

1

2

2700PF

2
.1UF
2
1UF

<15,29>

IAC_SDATAO

PHONE

13
12

11
10
5
45
46
47

R256
2
3.3K

1
C294

2

INT_CD_AGND

48

1UF
4
7

2

1

R254
3.3K

9

1
VCC

VCC

38

MONO_OUT

VIDEO_R

HP_OUT_L

LIN_IN_L

HP_OUT_R

LIN_IN_R
BIT_CLK
CD_L
SDATA_IN
CD_R
XTL_IN

35
36

RIGHT

37

MONO_OUT

39
41

1000PF

270PF

C259

1000PF

270PF

1
C327
1
C340

1
C297

2
1000PF

C501

Depop

1UF

1
C308

2
1UF

2
@1000PF
2
@1000PF

6

BIT_CLK_R

8

SDATA_IN_R

MD_MIC

MD_MIC

1
R259
1
C375

1
R274
1
R275

2

2
22
2
47
XTL_IN

3

XTL_OUT

<29>

2
100K_NC
EMI Solution 3/1/2000
ADD 15PF(EMI Request)

2
15PF

IAC_BITCLK
SDATA_IN0

CD_GNA

C

<15,29>
<15>

2

2
2.2UF_0805
2
2.2UF_0805
CD_L_IN
2
1UF
2
CD_R_IN
1UF
INT_CD_AGND

VIDEO_L

C260

Y2

C374

MIC1

22PF

MIC2

XTL_OUT

PHONE

AFLT1

PC_BEEP

AFLT2
VREFOUT

RESET#
REFFLT
SYNC
CAP2

29

AFTL1

C260 1

2

1000PF

1
2
C382
22PF
C261 1
2 .1UF

30

AFTL2

C259 1

2

1000PF

C247 1

28

VREFOUT

27

REFFLT

32

FLT3D

31
33
34
43
44

BPCFG 1
FLT1
FLT0

24.576 MHz

ID0#
ID1#

NC

EAPD

NC

SPDF
NC
AGND
AGND

GND
GND

40
26
42

<28>

CAP2

2

C501
@1UF

1UF

C257
1000PF

C262
.1UF

C248
1UF

C500
.047UF
D

STAC9700

1

U22

VREFOUT

C258

NC
NC
NC
NC
NC

1UF

W=15mils

SDATA_OUT
NC
NC

2

1

1
C253
1
C254
1
C306
1
C284

LINE_OUT_R

4.7UF_10V_0805

1

17

AUX_R

1UF

2

16

LINE_OUT_L

2

15

AUX_L

1

1
R257
1
R253
1
R249
1
R260

14

2
1000PF
2
1000PF

2

<28> LINE_IN_R

1
1UF
1
1UF

1
C287
1
C283
LEFT

1

<28> LINE_IN_L

25

2
6.8K
2
6.8K
2
6.8K
2
6.8K

<17> MOD_CD_R

2
C331
2
C335

AVCC

1
R238
1
R241
1
R239
1
R240
2
6.8K
2
6.8K
2
6.8K
2
6.8K

<17> MOD_CD_L

AVCC

2
6.8K
2
6.8K
2
6.8K
2
6.8K

4.7UF_10V_0805
2

1
R95
1
R94
1
R91
1
R90

2

.1UF

AD1881A

C248

2

C314

2

@4.7UF_10V_0805

1

1

C376

STAC9700

VDD_AC97
W=25mils

1

4.7UF_10V_0805

R282
0_1206

1

C193
TPA0202

2

24
13
12
1

.1UF

1

GND/HS
GND/HS
GND/HS
GND/HS

LBYPASS
RBYPASS

2
17
23

2

NC
NC
NC

1

SE/BTL#
SHUTDW
MUTEIN

2

2

-

SUSP <26>

2
C366

VDDA

<17> INT_CD_GND

2
2
G
Q34
2N7002

Q30
SI2306DS

HO/LINE#

14
8
11

D

.1UF
D

2
G

1

MUTEOUT

1

1

INTSPK_R+

3

15

2

INTSPK_R+

+5VS

<28> MONO_IN

D

C378

+
1

RHPIN

16

<17> INT_CD_R

100K_0402
C379
.1UF

3

LHPIN

20

<17> INT_CD_L

2

2

U23A

2

21

22

2
@0_1206

C

1

S

LLINEIN

B

4.7UF_10V_0805

2

.1UF

ROUT+

MUTEOUT

1
R269
C349

R306

1

4

<22> MUTE

VDDA

GND
D11
AS2431L

HP_SENSE

<28> HP_SENSE

GNDA

U17

2

RIGHT

.1UF
2
C405

1

3

A

LEFT

+12VALW

+5VALW

C199

LVDD
RVDD

2

.1UF

2
R226
2
R233
2
R200
2
R201
2
R232
2
R231
2
R206
2
R207

+5VALW

L55
2
1
BLM21A601SPT

R309
2.4K

C235

4.7UF_10V_0805

INTSPK_L+ 1
150K
C246 1UF
1
75K
INTSPK_R+ 1
150K
C178 1UF
1
75K
INTSPK_L+ 1
75K
C245 1UF
1
75K
INTSPK_R+ 1
75K
C179 1UF
1
75K

1

Note: direct connect GNDA to GND.

2

C198

+5VAU

2
0_1206
2
@0_1206

7
18

1

1
R229
1
R194

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

AUDIO CODEC & AMP
Size

2

3

4

5

6

Rev
2.0

888L2 Main Board
Date:

1

Document Number

T h ursday, January 11, 2001
7

Sheet

27

of
8

42

A

B

C

D

E

AUDIO JACK
+3VALW

+5VS

R320
100K_0402

R295
100K_0402

5

6

.1UF

R291
1

2

1
C401

VDDA

2
1UF

R264
100K_0402

2K_0402

1

C439

1

2
R322
10K_0402

4

VDDA
2

14

U29C
74LVC14

+3V POWER

R237
100K_0402

2

1

1

8
10
7

2

<23> BEEP#

U25C
74LVC32
1

14
9

1

2

+3VALW
+3VALW
4

2

EXT. LINE_OUT
J3

<27> HP_SENSE
<27>

INTSPK_R+

<23,27>

INTSPK_L+

C233
150UF_6.3V_E
1
2

1

1

1
2
C281
150UF_6.3V_E

L50 BLM11A121S
2

2
L51
BLM11A121S

3
6
2
1
1

<23,27>

C280

1

C252

C230

C236
47PF

47PF

47PF

2

D10

2

2
C395

Q31
2SC2411K

47PF
2

1
1UF

3

1

2
R302

2

2

2
C397

1

1
1UF

1

1
2K_0402

<15> SPKR

2
R304

JA6333L-100

4

1
1
2K_0402

<19> PCM_SPK#

+

MONO_IN

+

C362
1UF

5

1SS355
3

1
10K_0402

<29> MOD_MON

2
R303

2

2

3

1
1UF

2
C396

PC_BEEP

<27>

1
C219

2
4.7UF_10V_0805

1
C212

2
.1UF

VDDA

R387
2K_0402

2
1K_0402

EXT. MIC

1

1

R424
@2K_0402

1

1
R212
1

R430
4.7K_0402

J4

R223
2K_0402

JA6333L-100

5

2

1

C338

C295
47PF

47PF

2

47PF

2

1

C323

C210

@10UF_10V_1206

@.1UF

2

-

@.1UF

2

4

2

C229

@2K_0402
2
R219

1
2

2

@APA2308

+

1

1

C195

2

@4.7UF_10V_0805

2

1

1

C313

1

8
3

<27> VREFOUT

@2K_0402
1
2
R221

U16A

3
6
2
1
1

L53

2

EXT_MIC

1
2
BLM11A121S
1
2
BLM11A121S
1

<18> INT_MIC

VDDA

2

2

4

L52

C196
2

@.1UF
VDDA
8

U16B

7

5

-

6

1
C200

2
@1UF

EXT. LINE IN
1
R228

2 1
33_0402

2

C232

EXT_MIC

J2

0.47UF

JA6333L-100

5

4

<27> EXTMICIN

@APA2308

+

4
1
R230
1
@220PF

2

L46

0_0402

<27> LINE_IN_R

2
C228

<27> LINE_IN_L

LINE_IN_R

1

LINE_IN_L

1

BLM11A121S
2

3
6
2
1

2
L49
1

C186

C216
47PF

47PF
2

2

47PF

2

C222

1

1

BLM11A121S

1

1

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

MONO_IN
Size

B

C

D

Rev
2.0

888L2 Main Board
Date:

A

Document Number

T h ursday, January 11, 2001

Sheet
E

28

of

42

A

3

4

5

For Compal private Mini-PCI combo card - Mini-PCI type IIIc
pin 21. LAN REQ#
pin 22. LAN GNT#
pin 36. LAN PME#
pin 43. LAN IDSEL

6

7

8

+3V_MINIPCI

C477
10UF_10V_1206
2

2

C154
.1UF

2

C155
.1UF

1

1

1

1
C141
.1UF
2

C142
.1UF
2

C451
1000PF

2

C475
.1UF

1

1

+3V_MINIPCI

1

2

2

1

A

MINI_PCI CONNECTOR

<16> LAN_RXD2
<16> LAN_RXD1
<16> LAN_RXD0
+3V

1

2

2
2
2
2

1
1
1
1

0_0402
0_0402
0_0402
0_0402

LAN_EECS_R

JP18

LAN_EEDI_R
LAN_EEDO_R
LAN_EECLK_R
LAN_RXD2_R

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

LAN_RXD1_R
LAN_RXD0_R

<14,16>

L21

0

<14,16>

PIRQB#

2
R378

REQ#2

+3V_MINIPCI

1
@0_0402

<11> CLK_PCI_MINI

B

<14,16>

REQ#1

REQ#1

AD31
AD29
@100_0402
1
2
R157

AD28

<14,19>

AD27
AD25

C/BE#3

AD23
AD21
AD19
AD17

<14,19> C/BE#2
<14,16,19> IRDY#
<15,16,19,21>

CLKRUN#

CLKRUN#

<14,16,19>

SERR#

<14,16,19>
<14,19>

PERR#
C/BE#1

AD14
AD12
AD10

2

CLK_PCI_MINI

R164

C

AD8
AD7

33_0402
1

AD5
2

AD3
+5VS

AD1

1

C156
22PF
<15,27> IAC_SYNC
<15> SDATA_IN1
<15,27> IAC_BITCLK

2

IAC_BITCLK

IAC_BITCLK

+3VAUX
<28> MOD_MON

AC_CODEC_ID1#
R409
@33_0402

MOD_MON

1

<27> MD_MIC
2
1
R381
@0_0402
2
FBM-11-160808-121

2

<24> MINI_RI#
+5VS

C481
@22PF

1
L56

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

LAN_EECS_R
LAN_PHYRST_R
LAN_TXD2_R

R401
R402
R417
R404
R406
R408

LAN_TXD1_R
LAN_TXD0_R

2
2
2
2
2
2

1
1
1
1
1
1

0_0402
0_0402
0_0402
0_0402
0_0402
0_0402

LAN_PHYRST
<16>
LAN_TXD2 <16>
LAN_TXD1
LAN_TXD0

<16>
<16>
LAN_PHYCLK

+5VS

+3VAUX

2
R379

PCIRST#
GNT#1

AD30
AD28
AD26
AD24
1
R154
AD22
AD20

0

GNT#1 <14,16>
2
R380

2
R166

PIRQD# <14,16>
GNT#2 <14,16>

1
@0_0402

MINI_PME#

1
@0_0402

1
@33_0402

2
C157

<16>
1
@22PF

<7,12,14,19,21>
1
2 L57 +3V

B

+3V_MINIPCI
<23>

+5VS
1

R403
R418
R405
R407

8P4R-0
8
7
6
5

AD27
2
100_0402

C137
.1UF

2

RP39
1
2
3
4

<16> LAN_EECS
<16> LAN_EEDI
<16> LAN_EEDO
<16> LAN_EECLK

AD18
AD16

PAR

<14,19>

FRAME# <14,16,19>
TRDY# <14,16,19>
STOP# <14,16,19>
DEVSEL#

<14,16,19>

AD15
AD13
AD11
AD9
C/BE#0

C

<14,19>

AD6
AD4
AD2
AD0

1
R419

2
1K_0402

IAC_SDATAO

AC_CODEC_ID0#

<15,27>

AC97_RST#
MD_SPK

MD_SPK

Connection

<15,27>

SDATA_IN1

AC_CODEC_ID1#

AC_CODEC_ID0#

0

1

<27>

MPCIACT#

<14>

+3VAUX
+3VAUX

+3VALW

+3V

1

MINI_PCI CONN.
+5VS_MINIPCI
1

1
R165
1
R323

MOD_MON

D

2
R128

1

2

C430
.1UF

2
@0
2
0

1 MD_SPK
@0_0402

C429

D

<14,19>

AD[0..31]

2

.1UF
AD[0..31]

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

Mini-PCI Connector
Size

2

3

4

5

6

Rev
2.0

888L2 Main Board
Date:

1

Document Number

T h ursday, January 11, 2001
7

Sheet

29

of
8

42

A

B

C

D

E

B+CPU_CORE

0

2
12

<15> V_GATE

15

+5VALWP

5
2

2VREF

9

2

SHDN

DL

PGOOD

V+

VDD

VCC

CC

FB

REF

FBS

ILIM

GNDS

GND

TON

PR8
150K_1%

1
2

PC5
0 . 1UF_0805_25V

@4.7UF_1210_25V
2
1

1
PC97

4

PR6
VCCORE

2

3
4
11
8

2

1

PC8
220UF_D_4V

1
PD2
EC10QS04

5
6
7
8

1
4

1
7

2

1

PC4
4.7UF_1210_25V

2

2

PC2

1

PC1
4.7UF_1210_25V

5
6
7
8
5
6
7
8

DLCORE

20

1

+

PC10
2200PF
PR7
0

1

2

PR99

+5VALWP
2

2

PQ29
@

4
13

1

10

PGND

0

1

FBCORE

1
PR9
1M_1%

PR100
PR10

2

PC14

0.22UF_0805_16V

PC13
220PF

PC12
1UF_0805_25V

6

D0

PQ4
SI4404DY
FDS7764A

14

2

2

PQ3
SI4404DY
FDS7764A

BSTCORE

2

2

DHCORE

22

0.003_2512_1%
2
1

PD21
EC31QS04

PR5

24

2

2

VR_ON

0

BST

1

2

<22,26>

1

DH

D1

LXCORE

3
2
1

<4> VID0

100K
1

20

D2

23

+CPU_CORE
PR3

3
2
1

19

LX

0.003_2512_1%
2
1

2
PL2
0.9UH/20A_LPI

3
2
1

18

<4> VID1

SKIP

D3

PR98
2.2

<4> VID2

PR4

D4

1

PR101

PL1
@1UH
1

1

17

21

PC11
0.22UF_0805_16V

<4> VID3

2

+3VALWP

1

PJP11
@3MM

BSTCORE1

PU1
MAX1711
16

2

3
2
1

2

PR2
100K

<4> VID4

4

PC6
0.1UF_0805_25V

1

SUSP#

1

<22,24,26,33>

4

SI4884DY
IRF7811A

B+

1

PR1

PQ2

PQ1
SI4884DY
IRF7811A

3
2
1

1

5
6
7
8

5
6
7
8
2

RB751V

@0

1

2

VR_HI/LO#

PD1

<4,15>

PC3
4.7UF_1210_25V

+5VALWP
PR106

4 . 7UF_1210_25V
2
1

PL9
FBM-L11-322513-121AT
2
1

@
2

1

2VREF

1

10K_1%

1

2
PR12
0

2

2
1
PC18
220PF

1

2

100K_1%
1

PR21
5.1K
1

2

PQ8
DTC115EK

2

100K

2

1

Delay time (ms)
264 156 108

2VREF
+5VALWP

PR20
100K

2

1

3

-

1

+

PC20
68PF

1

1

2

PC79
1UF_0805_16V

PR19
300K_0.5%

2

1
PR18
200K_1%

4

1

2

3

LM358
PR17
100K_1%

3

PR16

2

S

CPU_IOP Detector
Low 1.43 1.35 1.29
High 1.08 1.03 0.99

0.1UF_16V

1
PU2A

PC98
1000PF

PR11
5.1K

G

1SS355

2

PC19
0.01UF

-

6

1

7

PC15
150UF_D_6.3V_KO

1

5

2

+

2

2
G

PD23

2.5VREF

8

1

PQ7
2N7002

PR14
100K_1%

PR15
243K_1%

+

2

PU2B
LM358
D

+CPU_IOP
+5VALWP

PC17

1
<13> VR_POK
3

4

3

2
1

1

1

100K

PC16
4 . 7UF_1206_25V

PR13
1.2M_1%

S

RB751V

2
PD22

+1_8VALWP
+CPU_IOP

1

2
PR92

6
5
2
1

D

PQ6
SI3442DV

+3VALWP

PQ9
DTC115EK

100K
PQ10
2SB1132

+2_5V_CLKP
3

+3VALWP

100K

SOT-89
3

2

2

VR_ON

<22,26>

100K

<22,24,26,33>

SUSP#

1

2

<22,26>

VR_ON

1

VIN

ON/OFF#

VOUT

3

5

4

Compal Electronics, Inc

2

Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

0
PR23

A

PC22
22UF_B_6.3V

2

@0
PR22

3

EXT

4

4

1

+
PU3
S-816A25

1

+

VSS

PC21
22UF_B_6.3V

B

C

D

CORE/IO/CLK
Size

Document Number
888L2 Main Board

Date:

T h ursday, January 11, 2001

Rev
2.0
Sheet
E

30

of

42

PJP10
@3MM
+3VALWP

1

2

1

BATT+

BATT++

PR24
47K

PL8
1

2

2
3

2

3

2

3

2

1
2

1
2

PQ11
DTC115EK

100K

2

PC82
0.1UF_0805_25V

<23>

1

AIR_ADP#

PC83
0.1UF_0805_25V

2

+3VALWP
FBM-L11-322513-121AT

PR25
47K

3

1

100K

PCN2
PR34-8R-3PDLA
3

PL3
OC9080-D601
ADPIN

BP02078-H1

VIN

2

BATT+
CLK_SMB
DAT_SMB
BATT_PRS#
SYS_PRES#
REMOTE-SNS
GND

3

VIN
1

GND

PC24
2

PC23

1

4

PC28
@

1

1

1
2

100PF_50V

1000PF_50V
2

PC27

100PF_50V
2

2

1

PC26

1000UF_50V

2

4
5
6
7

1

PR109
10_1206
1

2

1

1

PD5

@BAS40-04

@BAS40-04

A_BATT_PRE#

<22>

PR27
100

1
2
3
4
5
6
7

1

2

1

2
PR28
100

1

SMB_EC_CK1

<4,12,22,23>

SMB_EC_DA1

<4,12,22,23>

2
PR26
100

PC25
@

2

AIR_ADP

1

1

PD4

1

PD3
@BAS40-04

PCN1

2

PZD5
RLZ24B

ADPGND

Precharge detector while AC adaptor
High 16.5 15.8 15.1
Low 13.9 13.2 12.5

PR29
100K
1

+5VP

PR30
1M_1%
2

2

1
B+

1

Vin Detector
High 18.7 17.9 17.1
Low 18.0 17.3 16.5

PR31

PZD1
RLZ3.6B

<32>

PR42
47K
2

PQ12
2N7002

2

2

PQ13

2

2

RTCVREF

1

PACIN

PR41
10K

2

1

2

2

1

<15,22>

100K
2

PC93
1000PF

1
ACIN

3

1

-

1

1

1

PR37
499K_1%

2

1
2

2

PACIN

4

PR36
249K_1%

PR38
10K

RTCVREF

1

1

PC30
1000PF

1

2

PC33
0.1UF_16V

6

1

+

2

1

DTC115EK

PR43
10K

SYSON

<22,26>

100K
3

1

PR40
20K_1%

2

PC32
1000PF

LM393A

3

5

-

1

2

1

PU4A

8

2

PR39
22K
1

PR35
10K

2

2

78.7K_1%

PR34
10K

+

PC31
0.1UF_16V

1
1

1

PC29
0.01UF

<32> ACON

7

2

PD7
RB751V

VS
2

PR33

1
1

VS

VIN

2

2

<33> SHDN#

2

2

PD6
RB751V

PR32
1M_1%
1

499K_1%

PU4B
LM393A

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

Detector
Size

Document Number

Rev
2.0

888L2 Main Board
Date:

T h ursday, January 11, 2001

Sheet

31

of

42

P2

P3

PQ16
SI4835DY
1
2
3

8
7
6
5
PR46
47K

4

PC85
2200PF

1

PC84
0.1UF_0805_25V

3
2
1

2

1

PC36
4.7UF_1210_25V

2

4.7UF_1210_25V

PC35

1

2

VIN

1

1

2

2

2

Iadp = 0~3.33A
Iadp = 0.964*ADPREF

1

1

4

PR45
200K

2

4.7UF_1210_25V

8
7
6
5

1

1
2
3

4

B+

PC34

1
2
3

B++

PR44
0.02_2512_1%

1

8
7
6
5

VIN

B+

PQ15
SI4835DY

2

PQ14
SI4835DY

3

OUTC2

GND

+INE2

CS

-INE2

VCC(o)

23

PQ17

PC37
2200PF

22

1

21

1

1

2

PR49
100K

FDS4435

2
PQ28

2

7

PR54
1K

8

VREF

VH

FB1

VCC

-INE1

RT

+INE1

-INE3

20

19

2
PR60
69.8K_1%

1

10

PR58
10K

FB3

OUTD

CTL

-INC1

+INC1

PC39
0.1UF_16V
1
2

LXCHRG

18

17

PC92
0.1UF_0805_25V
2

1

1

FSTCHG

2

16

PR56
66.5K_1%

15

1

PL4
22UH_SPC-1205PA
1
2

<22>

2 1

PR57
0.02_2512_1%
1
2

PD8
1SS355

2

PD10
PR59
330K

14

PC43
1500PF

CC = 0~2.7A
Ich = 0.808*IREF
CV = 17.47V

EA60QC04

+

BATT+

2

1

2

11

OUTC1

3

OUT

2

PC40
2200PF

1
1

<22>

PC46
4.7UF_1210_25V
2
1

2 1

FB2

PC45
4 . 7UF_1210_25V
2
1

6

9

PC94
@

ACOFF

PC44
4.7UF_1210_25V
2
1

2

PR93
@30.1K_1%

5

PC42
33UF_EC_25V
2
1

1

2
PR52
10K

3

2
1

1

2 1

PC38
4700PF

2

2

PC41
0.1UF_16V

2

100K
1

PR55
100K_1%
1
2

100K

@DTC115EK

2
PC86
0.1UF_0805_25V

2

PR53
69.8K_1%

PC96
@

<31> ACON

4
PR51
@20K_1%

1

1

3

1

S

<22> IREF

24

5
6
7
8

1

PQ18
2N7002

2
G

+INC2

2

D

2

1

2

-INC2

ACOFF#
PR97
75K_1%

2
1

PR50
47K
1

<31> PACIN

2

1

1
1

<22> ADPREF

@47K

1

2

PR96

4

2

PR47
150K

@1SS355
1

ACOFF#

PR48
0

PU5
MB3878

PD26

13

PC100
22PF
1
2

PR61
10K

2

12

CSH

VS

2

PD11

2

1

2

PR63
47.5K_1%
1

VS1

RLS4148
2

1

PC95
@22PF

PR65
150K_1%
1

PC99
22PF
2
1

PR70
1K_1206
PQ19
TP0610T

3

2

1

1
PR74
1K_1206

2

2

2

2

2

PC49
0.1UF_16V

B+

1

2

PR69
150K

PZD3
RLZ5.1B
2

PC48
0.1UF_0805_25V

2

1

<25> EC_ON#

PR73
1K_1206

2

1
2

2

PR68
100K

1

1

PZD2
RLZ4.3B

1

2

1

PC47
0.22UF_1206_25V
2

PR66
200_0805

2

1

1

PR72
1K_1206

+5VP
PR67
10K

2

PR71
1K_1206

1

1

1

2

BATT+

1

PD13
RLS4148

1

1

2

VIN

PD12

PR62
100_1206
1
2

RLS4148

1

PR75
22K
RTCVREF

PU6
S-81235SG

3

1

PR76
200_0805
2

CHGRTC

PC51
4.7UF_1206_25V

1

GND
PC50
1UF_0805_25V

Compal Electronics, Inc.

2

2

PZD4
RLZ16B

OUT

1

IN

2

2
1

1

CHGRTCP

Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

Charger
Size

Document Number

Rev
2.0

888L2 Main Board
Date:

T h ursday, January 11, 2001

Sheet

32

of

42

B++

PL10
FBM-L11-322513-121AT
2
1
B+
PJP12
@3MM
2

PQ26

PD16
RB751V

VS

BST51

1
2
1

3

PR94
0

PC60
4.7UF_1210_25V

1
2

1
2

1
2

6
5

1

1

PC90
0.1UF_0805_25V

2

VL

0

1

@0

1

PC65
1000PF

1
2

8

1

PR83
PR104

PQ21
SI4834DY

CSH5
2.5VREF

TIME/ON5
RUN/ON3

2

2

1

PR84
0

PR108
@0

2

1

2

PR82
0.015_2512_1%

PR103
@0
2

1

+5VALWP

2

SHDN#

<31>

1

2

1
PC73

2

PC72
150UF_D_6.3V_KO

1

POK <22>

1

1

2

PD25
RB751V

PR85
10K
+5VP

PR95
100K

1

SUSP#

+

PC74
0.047UF_16V
2

<22,24,26,30>

+

2

1
+

2

+3VALWP

PC71
150UF_D_6.3V_KO

PD18
BYS10-45

2

2

0

2

1

1

2

PR105

@ 1 5 0 U F _D_6.3V_KO

PU7
MAX1632

DL5

1

1

7

4

1

28

0

VDD
BST5
DH5
LX5

2

2

1

PD17
BYS10-45

1 5 0 U F _D_6.3V_KO
2
1

PC70

PC69

150UF_D_6.3V_KO
2
1

1 5 0 U F _D_6.3V_KO
2
1

PC68

2

2

2

PR102
@0

+3VALWP

CSH3
CSL3
FB3
SKIP#
SHDN#

4
5
18
16
17
19
20
14
13
12
15
9
6
11

1

1

1

1

2
LX3
DL3

12OUT
VDD
BST5
DH5
LX5
DL5
PGND
CSH5
CSL5
FB5
SEQ
REF
SYNC
RST#

2

2

1
2
3
10
23

PR107
@0

PR81
0.012_2512_1%

PC67

4

3
7
8

GND

CSH3

150UF_D_6.3V_KO
2
1

FLYBACK

PT1
SDT-1205P-100-120

21

DH3

2

26
24

BST3

PR80

PC66
4.7UF_1206_25V

27

VL

25

V+

1

BST3

PL6
10UH_SPC-1205P

2

PC63
4.7UF_1210_25V

1
22

2

1
PC91

0.1UF_0805_25V

PC61
1000PF

2

1
2
3

1

DL3

2

PC64

1
2

PD24
EC10QS04

4

4.7UF_1210_25V

PQ27

PC59
4.7UF_1210_25V

+12VALWP
PC89
0.1UF_0805_25V

2

PC87
0.1UF_16V

1
2

1

8
7
6
5

2

LX3

SI4800DY

+

1

B++

1

PR79

2

1
2
3

10_1206

1

DH3

PC62
4.7UF_1206_25V

2
4

0

+

SNB

PD14
EC11FS2

PR77
22_1206
2

PC56
0.1UF_0805_25V
1
2

PC88
2200PF

SI4800DY

PR78

+

1

VL
2

PC53
470PF_0805_100V
1
2

1

PC54

BST31

8
7
6
5

2

1

1

PC58
4.7UF_1210_25V

2

1

PC57
4.7UF_1210_25V

PC81
2200PF

2

2

1

PC80
0.1UF_0805_25V

1

RB751V

2

PD15

PC55
0.1UF_0805_25V

+

PC52
2.2UF_1206_25V
1
2

SNB1

1
1UF_0805_25V

2

PL5
1UH_BLM3216
1

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

3.3V/5V/12V
Size

Document Number

Rev
2.0

888L2 Main Board
Date:

T h ursday, January 11, 2001

Sheet

33

of

42

4

3

PL11
5UH_SPC_06703
D

2

2

+CPU_IO

1
1

PJP5
+

PC75
150UF_D_6.3V_KO

2MM
+2_5V_CLKP

1

2

3

PR89
@10K

1

+2_5V_CLK

PJP6
3MM
1

+5VALWP

2

+5VALW

2

PC77
2200PF
2

2

2

PR86
10K

2

PR87
10K

2

+CPU_IOP

1

1

2

3

1
1

2

1

PQ23
2SC2411K

PD19
RB051L-40

2
1

1
2

LX18

G

PR88
1K

D

PJP4
3MM

@4.7UH_SLF7045T
2
1

D

S

PD20
RB751V

+1.8V+-5%

1

PL7
6
5
2
1

4

PC76
4.7UF_1206_25V

1

+1_8VALWP

PQ22
SI3445DV

+5VALWP

2

1

5

PJP7
3MM
VS

PQ24
2SA1036K 1

C

2

1

+

3

-

2

1

+3VALWP

PU8A
LM393A

8
3

PR90
38.3K_1%
2
1

2

+3VALW

PJP8
C

2MM

2.5VREF

1

2

+12VALW

PR91
100K_1%

PJP9
3MM

2

2

PC78
0.01UF

1

4

1

+12VALWP

+1_8VALWP

1

2

+1_8VALW

B

B

A

A

Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

+1_8VS
Size

4

3

2

Rev
2.0

888L2 Main Board
Date:

5

Document Number

T h ursday, January 11, 2001

Sheet
1

34

of

42

www.s-manuals.com



---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.6
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Create Date                     : 2001:02:02 18:26:25Z
Creator Tool                    : 888l2
Modify Date                     : 2014:10:13 21:23:20+03:00
Metadata Date                   : 2014:10:13 21:23:20+03:00
Format                          : application/pdf
Creator                         : 
Title                           : Compal 888L2 - Schematics. www.s-manuals.com.
Subject                         : Compal 888L2 - Schematics. www.s-manuals.com.
Producer                        : Acrobat PDFWriter 4.0 for Windows
Document ID                     : uuid:b592fefa-4bf0-474a-982b-c1db3d24b65d
Instance ID                     : uuid:778d8caa-d8c0-4b5e-84e4-f4dd0a6ac10e
Has XFA                         : No
Page Count                      : 35
Keywords                        : Compal, 888L2, -, Schematics., www.s-manuals.com.

EXIF Metadata provided by EXIF.tools