Compal LA 2171 Schematics. Www.s Manuals.com. R0.2 Schematics
User Manual: Motherboard Compal LA-2171 Sullivan - Schematics. Free.
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5
4
3
2
1
SULLIVAN
D
D
REV : X01
@ : Depop Component for All
C
C
B
B
Dothan Schematic with Capture CIS and Function field
uFCPGA Dothan
02-11-2004
REV: 0.2
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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Cover Sheet
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
1
of
50
5
4
3
2
1
Block Diagram
Compal confidential
GUARDIAN
EMC6N300
D
Dothan
Clock Generator
uFCPGA CPU
page 15
page 7,8,9
HA#(3..31)
CRT CONN.
& TV-OUT
VGA
Board
System Bus
HD#(0..63)
Alviso
VGA CONN.
Fan Control
Memory
BUS(DDRII)
1.8V 400 / 533MHz
GMCH-M
1257 FC-BGA
PCI-E 16X
page 15
SO-DIMM X2
BANK 0, 1, 2, 3
LED/B
page 16,17
page 37
page 10,11,12,13,14
page 18
C
page 6
400 / 533MHz
page 19
C
DMI
MINI PCI
MDC
1.5V
100MHz
PCI BUS
IDSEL:AD17
(PIRQA/B#,GNT#2,REQ#2)
3.3V 33MHz
CardBus Controller
LAN
BCM4401
1394 CONN.
page31
3.3V or 5V SATA
page 20,21,22,23
ATA100
Slot 0
page 30
page32
SATA
AC97 CODEC
SATA to PATA Bridge
Marvell 88SA8040
CDROM
Transformer
& RJ45
BATT IN/+2.5V
page 42
609 BGA
page 29
page 31,32
page32
page 41
AC-LINK
3.3V 24.576MHz
ICH6
RICHO R5C841
SDIO CONN.
DC IN
page 27
page 33
B
D
CK410M
B
5V/3.3V/15V
page 44
HDD
3.3V 33MHz
page 43
page 25
page 24
page 24
LPC BUS
1.5V/1.05V(+VCCP)
STAC9751
AMP &
page 24
Phone Jack
Subwoofer
page 27
1.8V / 0.9V
page 26
page 45
Macallan III
GPIO
LPC to X-BUS
& Super I/O
X BUS
48MHz / 480Mb
USB2.0
SST39VF080
USBPORT 2
USBPORT 3
USBPORT 4
USBPORT 5
page 36
A
USBPORT 1
page 34,35
LCM CONN.
page36
USBPORT 0
Touch Pad
Multi-media
Board
page 36
Int.KBD
USBPORT 6
page 36
page 28
USBPORT 7
JUSB1 U
VCORE
JUSB1 D
Blue Tooth
NEW CARD
CHARGER
JUSB2 U
page 47
JUSB2 D
A
JUSB3 U
JUSB3 D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
Size
Date:
5
4
3
page 46
2
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Block Diagram
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
2
of
50
5
4
3
2
1
D
D
PM TABLE
+5VRUN
C
+3VRUN +0.9V_DDR_VTT
power
plane
+3VALW
+3VSUS
+2.5VRUN
+5VALW
+5VSUS
+1.8VRUN
+1.8VSUS
+1.5VRUN
+1.5VSUS
+VCC_CORE
State
PCI DEVICE
+VCCP
+15V
B
S0
ON
ON
ON
S1
ON
ON
ON
S3
ON
ON
OFF
S5 S4/AC
ON
OFF
OFF
S5 S4/AC don't exist
OFF
OFF
OFF
USB TABLE
PCI TABLE
IDSEL
REQ#/GNT#
USB PORT#
PIRQ
CARD BUS
AD17
1
D,C
MINI PCI
AD19
3
D,B
LAN
AD16
4
C
C
0
1
2
3
4
5
6
7
DESTINATION
JUSB1 (Top)
JUSB1 (Bottom)
Blue Tooth
NEW CARD
JUSB2 (Top)
JUSB2 (Bottom)
JUSB3 (Top)
JUSB3 (Bottom)
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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Index and Config.
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
3
of
50
5
4
3
2
1
D
D
+5VALW
PWR_SRC
ADAPTER
+3VALW
BATTERY
+15V
VDDA
SUSPWROK_5V
SUSPWROK_5V
RUNPWROK
SUSPWROK_1.5V
SUS_ON
+3VRUN V3P3LAN +3VSUS +2.5VRUN
PJP11,PJP12
RUN_ON
RUN_ON_D
SUSPWROK_5V
(Option)
RUN_ON
+VCC_CORE +1.5VSUS +VCCP +1.8VSUSP +0.9V_DDR_VTT
+1.5VRUN
B
+1.8VSUS
RUN_ON
+5VHDD +5VMOD +5VRUN
PL9
RUN_ON
+3VSRC
AUDIO_AVDD_ON
+5VSUS
B
RUNPWROK
C
SUS_ON
C
L10
+1.8VRUN
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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Power Rail
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
4
of
50
5
4
ICH_SMBCLK
D
ICH6
ICH_SMBDATA
3
2
CK_SCLK
7002
+3VSUS
1
+3VRUN
CLK GEN.
CK_SDATA
7002
DIMM0
D
DIMM1
CLK_SMB
+3VALW
DAT_SMB
GUARDIAN
C
C
24C04
SIO
Macallan III
SMBCLK_VGA
SMBDAT_VGA
+5VALW
ICH6-SMBus
VGA
B
EC-SMBus
PBAT_SMBCLK
PBAT_SMBDAT
+5VALW
BATTERY
Device
Address
DIM0
A0h
DIM1
A2h
CLK GEN.
D2h
GUARDIAN
5Eh
24C04
A2h
VGA
58h
Battery
16h
Charger
12h
B
CHARGER
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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SMBUS TOPOLOGY
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
5
of
50
5
4
3
+3VRUN
CK_SDATA
CK_SDATA
<16,17>
1
2
L20
BLM21PG600SN1D_0805~D
1
2
C42
D
1
1
1
1
2
G
1
1
2
2
0 0 1 for Dothan-A 533Mhz
1 0 1 for Dothan-A 400Mhz
FSB
FSA
CLKSEL1
CLKSEL2
0
0
0
C
*
CPU
MHz
SRC
MHz
PCI
MHz
266
100
33.3
0
0
1
133
100
33.3
0
1
0
200
100
33.3
0
1
1
166
100
33.3
1
2
2
1
C83
@ 33P_0402_50V8J~D
2
1
2
C77
@ 33P_0402_50V8J~D
2
1
<22> CK_48M_ICH
21
28
34
1
7
42
2CK_VDD_REF
48
R119
1_0402_5%~D
1
2CK_VDD_4811
R113
2.2_0402_5%~D
50
1
X2
14.31818MHz_20P_1BX14318CC1A~D
CK_XTAL_OUT
R84
49
1 33_0402_5%~D
2
CLKSEL2
12
CLKSEL1
16
CLKSEL0
53
VDD_SRC0
VDD_SRC1
VDD_SRC2
VDD_A
VSS_A
VDD_PCI0
VDD_PCI1
1
0
1
0
0
333
1
100
100
33.3
100
33.3
<31> CK_33M_CBPCI
<34> CK_33M_SIOPCI
<33> CK_33M_MINIPCI
1
1
0
1
1
0
400
100
33.3
RESERVED
<29> CK_33M_LANPCI
<20> CK_33M_ICHPCI
2
R93
2
R95
2
R106
2
R123
2
R83
CK_33M_SIOPCI
CK_33M_MINIPCI
CK_33M_LANPCI
CK_33M_ICHPCI
Table : ICS 954201 / Cypress CY28411
+3VRUN
1
33_0402_5%~D
1
33_0402_5%~D
1
33_0402_5%~D
1
33_0402_5%~D
1
33_0402_5%~D
R85
10K_0402_5%~D
1
2
+VCCP
Dothan-A 400MHz, Install R390, No pop. R394, R395
Dothan-A 533MHz, Install R394, No pop. R390, R395
2
B
1
R385
PCICLK5
5
PCICLK4
4
PCICLK3
3
PCICLK2
56
PCICLKF1
9
CPU1
VDD_48
CPU1#
8
CK_SCLK
46
CK_SDATA
47
CLKIREF
2
475_0603_1%~D
39
XTAL_OUT
38
55
H_STP_PCI#
54
H_STP_CPU#
41
CK_CPU1
40
CK_CPU1#
44
CK_CPU0
43
CK_CPU0#
36
CK_CPU2
35
CK_CPU2#
2
CPU0#
FSC/TEST_SEL
CPU_2_ITP/SRC_7
PCI4
SRC6
PCI3
SRC6#
PCI2
SRC5
PCIF1
PCIF0/ITP_EN
SCLOCK
SDATA
SRC4
SRC4#
SRC3
SRC3#
SRC1
13
+3VRUN
R394
0_0402_5%~D
1
R81
1
R76
CK_BCLK
2
33_0402_5%~D
CK_BCLK
<7>
CK_BCLK#
2
33_0402_5%~D
CK_BCLK#
<7>
1
R59
1
R54
CK_ITP
2
33_0402_5%~D
CK_ITP#
2
33_0402_5%~D
CK_ITP
<7>
CK_ITP#
<7>
1
R47
1
R41
CLK_MCH_3GPLL
2
33_0402_5%~D
CLK_MCH_3GPLL#
2
33_0402_5%~D
1
R48
1
R42
CLK_PCIE_SATA
2
33_0402_5%~D
CLK_PCIE_SATA#
2
33_0402_5%~D
1
R551
1
R552
CLK_PCIE_TV
2
33_0402_5%~D
CLK_PCIE_TV#
2
33_0402_5%~D
1
R67
1
R63
CLK_PCIE_VGA
2
33_0402_5%~D
CLK_PCIE_VGA#
2
33_0402_5%~D
1
R55
1
R50
CLK_PCIE_ICH
2
33_0402_5%~D
CLK_PCIE_ICH#
2
33_0402_5%~D
CLK_MCH_BCLK <10>
CLK_MCH_BCLK# <10>
32
31
SCR5
30
SRC5#
26
SRC4
27
SRC4#
24
SRC3
25
SRC3#
CLK_MCH_3GPLL <12>
CLK_MCH_3GPLL# <12>
CLK_PCIE_SATA <21>
CLK_PCIE_SATA# <21>
CLK_PCIE_TV <37>
CLK_PCIE_TV# <37>
23
SRC1#
19
SRC1
20
SRC1#
17
SRC2
18
SRC2#
VSS_48
45
51
1
1
R86
10K_0402_5%~D
VSS_SRC
SRC0
VSS_PCI0
SRC0#
CLKSEL2
2
6
VSS_CPU
VSS_REF
DOT96
DOT96#
CLK_PCIE_ICH#
<22>
<22>
VSS_PCI1
1
VTT_PWRGD#/PD
REF
10
52
CLK_ENABLE#
CLKREF
MCH_CLKSEL1 <10>
R392
1K_0402_5%~D
CY28411ZCT_TSSOP56~D
2
2
R396
@ 0_0402_5%~D
2
CLK_PCIE_VGA# <18>
CLK_PCIE_ICH
R94
10K_0402_5%~D
@
2
1
CLK_PCIE_VGA <18>
14
15
1
CLKSEL1
CLK_ENABLE# <46>
1
R116
CK_14M_ICH
2
12.1_0402_1%~D
CK_14M_ICH
<22>
1
R112
CK_14M_SIO
2
12.1_0402_1%~D
CK_14M_SIO
<34>
1
R122
CK_14M_CODEC
2
12.1_0402_1%~D
CK_14M_CODEC <25>
R393
0_0402_5%~D
A
DELL CONFIDENTIAL/PROPRIETARY
1
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
B
22
2
29
R389
1K_0402_5%~D
@
1
CLK_MCH_BCLK
2
33_0402_5%~D
CLK_MCH_BCLK#
2
33_0402_5%~D
33
IREF
R391
1K_0402_5%~D
2
+VCCP
CPU_BSEL1
1
R71
1
R66
PCI5
MCH_CLKSEL0 <10>
2
<8>
<22>
H_STP_CPU# <22,46>
1
1
R395
@ 0_0402_5%~D
A
H_STP_PCI#
FSB/TEST_MODE
SRC2
2
1
37
C
CPU0
SRC2#
CLKSEL0
CPU_BSEL0
R56 2
1
49.9_0402_1%~D
R51 2
1
49.9_0402_1%~D
CLK_MCH_3GPLL 1
R46 2
49.9_0402_1%~D
CLK_MCH_3GPLL# 1
R40 2
49.9_0402_1%~D
CLK_PCIE_VGA
R68 2
1
49.9_0402_1%~D
CLK_PCIE_VGA#
R64 2
1
49.9_0402_1%~D
CLK_PCIE_TV
1 R553
2
49.9_0402_1%~D
CLK_PCIE_TV#
1 R554
2
49.9_0402_1%~D
CLK_PCIE_ICH#
FSA/USB_48
R390
@ 1K_0402_5%~D
<8>
CLK_PCIE_ICH
XTAL_IN
SRC5#
PCICLKF0
D
VDD_CPU
VDD_REF
CPU_2_ITP/SRC7#
CK_33M_CBPCI
Place near CK410M
1
CPU_STOP#
CK_XTAL_IN
CK_48M_ICH
1
PCI_STOP#
Place crystal within
500 mils of CK410
1
FSC
CLKSEL0
1
C94
C78
C89
10U_0805_10V4M~D 0.047U_0402_10V7K~D 0.047U_0402_10V7K~D
1
2
2
R376
2.2_0402_5%~D
CK_VDD_A
1
2
U7
C72
0.047U_0402_10V7K~D
2N7002
1
2
CK_VDD_REF
2
S
2
L21
BLM21PG600SN1D_0805~D
<16,17>
CK_VDD_48
C405
4.7U_0805_6.3V6K~D
C401
4.7U_0805_6.3V6K~D
1
C57
0.047U_0402_10V7K~D
CK_VDD_A
3
CK_SCLK
S
D
D
G 2
CK_SCLK
C69
0.047U_0402_10V7K~D
Q10
3 2N7002_SOT23~D
1
2 R70
1
49.9_0402_1%~D
2 R65
1
49.9_0402_1%~D
CK_BCLK
2 R80
1
49.9_0402_1%~D
CK_BCLK#
2 R75
1
49.9_0402_1%~D
CK_ITP
2 R58
1
49.9_0402_1%~D
CK_ITP#
2 R53
1
49.9_0402_1%~D
CLK_PCIE_SATA
R49 2
1
49.9_0402_1%~D
CLK_PCIE_SATA# 1
R43 2
49.9_0402_1%~D
CLK_MCH_BCLK#
Place near each pin
W>40 mil
CK_VDD_MAIN2
ICH_SMBCLK
CLK_MCH_BCLK
C53
0.047U_0402_10V7K~D
2
+3VRUN
<22> ICH_SMBCLK
1
C49
C62
C44
10U_0805_10V4M~D 0.047U_0402_10V7K~D 0.047U_0402_10V7K~D 0.047U_0402_10V7K~D
1
2
2
2
2
2
G
1
C100
0.1U_0402_16V4Z~D
R118
100K_0402_5%~D
2
1
S
Q9
3 2N7002_SOT23~D
D
ICH_SMBDATA
<22> ICH_SMBDATA
R117
100K_0402_5%~D
2
1
+3VRUN
2
CK_VDD_MAIN
4
3
2
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Clock Generator
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
6
of
50
<10> H_REQ#[0..4]
RN2
0_0404_4P2R_5%~D
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
1
2
H_ADSTB#0
H_ADSTB#1
4
3
<10> H_ADSTB#0
<10> H_ADSTB#1
P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
AA3
Y3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
R2
P3
T2
P1
T1
U3
AE5
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
Dothan
ADDR GROUP
DATA GROUP
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
ADSTB0#
ADSTB1#
C
<6>
<6>
CK_ITP
CK_ITP#
CK_ITP
CK_ITP#
RN3
1
0_0404_4P2R_5%~D 2
@
<6> CK_BCLK
<6> CK_BCLK#
+VCCP
R92
56_0402_5%~D
1
2
<10>
H_ADS#
<10>
H_BNR#
<10> H_BPRI#
<10>
H_BR0#
<10> H_DEFER#
<10> H_DRDY#
<10>
H_HIT#
<10>
H_HITM#
<10> H_LOCK#
<10> H_RESET#
<10> H_RS#[0..2]
<10> H_TRDY#
B
<39> ITP_DBRESET#
<10>
H_DBSY#
<21> H_DPSLP#
<21> H_DPRSLP#
<10> H_DPWR#
<35> H_PROCHOT#
<21> H_PWRGOOD
<10,21> H_CPUSLP#
T2 PAD~D
T21 PAD~D
<15> H_THERMDA
<15> H_THERMDC
<15> H_THERMTRIP#
4CPU_CK_ITP A16
3CPU_CK_ITP# A15
CK_BCLK
CK_BCLK#
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
B15
B14
N2
L1
J3
N4
L4
H2
K3
K4
A4
J2
B11
H1
K1
L2
M3
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
C8
B8
A9
C9
ITP_DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSLP#
A7
M2
B7
G1
C19
A10
B10
B17
ITP_BPM#4
ITP_BPM#5
H_PROCHOT#
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
H_THERMDA
H_THERMDC
E4
A6
A13
C12
A12
C5
F23
C11
B13
ITP_CLK0
ITP_CLK1
BCLK0
BCLK1
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#
HOST CLK
CONTROL GROUP
RS0#
RS1#
RS2#
TRDY#
DINV0#
DINV1#
DINV2#
DINV3#
BPM0#
BPM1#
BPM2#
BPM3#
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
MISC
PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
THERMAL
B18
A18
C17
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
THERMDA DIODE
THERMDC
THERMTRIP#
A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
D25
J26
T24
AD20
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
C2
D3
A3
B5
D1
D4
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
C6
B4
H_STPCLK#
H_SMI#
LEGACY CPU
STPCLK#
SMI#
+3VSUS
<10>
R11
150_0402_5%~D
ITP_DBRESET#
1
2
+VCCP
JITP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ITP_DBRESET#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
H_RESET#
R20
22.6_0603_1%~D
1
2
ITP_TDO
R31
22.6_0603_1%~D
1
2
ITP_BPM#5
ITP_TCK
CK_ITP_R
CK_ITP_R#
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
+VCCP
VTT1
VTT0
VTAP
DBR#
DBA#
BPM0#
GND5
BPM1#
GND4
BPM2#
GND3
BPM3#
GND2
BPM4#
GND1
BPM5#
RESET#
FBO
GND0
BCLKP
BCLKN
TDO
NC2
TCK
NC1
TRST#
TMS
TDI
R36
54.9_0603_1%~D
ITP_TDO
1
2
R19
54.9_0603_1%~D
1
2
+VCCP
D
H_RESET#
R61
39.2_0603_1%~D
ITP_TMS
1
2
R62
150_0402_5%~D
ITP_TDI
1
2
This shall place near CPU
R45
680_0402_5%~D
ITP_TRST#
1
2
R44
27.4_0603_1%~D
ITP_TCK
1
2
@
MOLEX_52435-2891_28P~D
+VCCP
C
1
2
C20
0.1U_0402_10V7K~D
Check ITP connector.
Place near JITP
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
C23
K24
W25
AE24
C22
L24
W24
AE25
1
30
D
CK_ITP_R#
CK_ITP_R
H_D#[0..63]
JCPUA
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
2
29
<10> H_A#[3..31]
3
GND6
4
GND7
5
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
<10>
<10>
<10>
<10>
<21>
<21>
<21>
<21>
<21>
<21>
H_STPCLK# <21>
H_SMI# <21>
H_DSTBN#[0..3]
<10>
H_DSTBP#[0..3]
<10>
+VCCP
+VCCP
B
R397
75_0402_5%~D
1
2 H_THERMTRIP#
R405
200_0402_5%~D
1
2 H_PWRGOOD
Add pullups for PWRGOOD and THERMTRIP per INTEL
AMP_1473129-1_Dothan~D
A
A
R99
TEST1
1
2
DELL CONFIDENTIAL/PROPRIETARY
@ 1K_0402_5%~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
Dothan Processor(1/2)
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
7
of
50
5
4
3
2
1
+VCC_CORE
JCPUC
+VCCA_PROC
PJP5
+1.8VRUN
2
1
R379
2
1
0_0402_5%~D
H_VID5
R378
2
1
0_0402_5%~D
@
1
OPEN
@
@
B_VID3
OPEN~D
OPEN
B_VID2
OPEN~D
OPEN
@
C122
10U_1206_6.3V6M~D
1
B_VID4
OPEN~D
1
2
OPEN
2
1
B_VID5
OPEN~D
1
1
1
2
2
B_VID6
OPEN~D
2
H_VID4
2
VID0
<46>
VID1
<46>
VID2
<46>
VID3
<46>
VID4
<46>
VID5
<46>
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L5
L21
M6
M22
N5
N21
P6
P22
R5
R21
T6
T22
U21
1
2
B_VID1
OPEN~D
+VCC_CORE
D6
D8
D18
D20
D22
E5
E7
E9
E17
E19
E21
F6
F8
F18
2
0_0402_5%~D
1
P23
W4
1
1
1
2
2
R380
2
H_VID3
1
0_0402_5%~D
1
1
2
2
2
R381
1
H_VID2
1
0_0402_5%~D
2
0_0402_5%~D
1
2
1
2
2
4
3
2
1
2
R382
R38
R383
H_VID1
10K_0402_5%~D
R37
H_VID0
10K_0402_5%~D
5
6
7
8
SHORT
RN1
2
+VCCP
1
PAD-OPEN 2x2m~D
+VCCP
10K_1206_8P4R_5%~D
1
2
C117
0.01U_0402_16V7K~D
CPU Voltage ID
C
PJP3
+1.5VRUN
OPEN
@
OPEN
@
<46>
H_PSI#
Layout Note:
500 mil max length
1
B
R_A
<6>
<6>
CPU_BSEL0
CPU_BSEL1
E2
F2
F3
G3
G4
H4
AD26
C16
C14
COMP0
COMP1
COMP2
COMP3
P25
P26
AB2
AB1
R426
27.4_0603_1%~D
1
2
R427
54.9_0603_1%~D
2
1
R416
54.9_0603_1%~D
1
2
2
R203
2K_0603_1%~D
R417
27.4_0603_1%~D
1
R_B
2
2
1
E1
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
CPU_BSEL0
CPU_BSEL1
R201
1K_0603_1%~D
V_CPU_GTLREF
H_PSI#
V_CPU_GTLREF
+VCCP
Layout close CPU
AE7
AF6
F26
B1
N1
AC26
@ PAD-OPEN 2x2m~D
D
For test only ,Cmos output
JCPUB
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.
T42
T43
T44
T45
PAD~D
PAD~D
PAD~D
PAD~D
B2
C3
E26
AF7
AC1
VCCSENSE
VSSSENSE
VCCA0
VCCA1
VCCA2
VCCA3
VCCQ0
VCCQ1
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Dothan
POWER, GROUNG, RESERVED SIGNALS AND NC
OPEN
R208
@ 54.9_0603_1%~D
1
2 VCCSENSE
1
2 VSSSENSE
R207
@ 54.9_0603_1%~D
PSI#
VID0
VID1
VID2
VID3
VID4
VID5
GTLREF
BSEL0
BSEL1
COMP0
COMP1
COMP2
COMP3
RSVD
RSVD
RSVD
RSVD
RSVD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F20
F22
G5
G21
H6
H22
J5
J21
K22
U5
V6
V22
W5
W21
Y6
Y22
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC9
AC11
AC13
AC15
AC17
AC19
AD8
AD10
AD12
AD14
AD16
AD18
AE9
AE11
AE13
AE15
AE17
AE19
AF8
AF10
AF12
AF14
AF16
AF18
A2
A5
A8
A11
A14
A17
A20
A23
A26
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Dothan
POWER, GROUND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
D
C
B
AMP_1473129-1_Dothan~D
AMP_1473129-1_Dothan~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
Dothan Processor(2/2)
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
8
of
50
5
4
3
+VCC_CORE
2
1
+VCC_CORE
1
1
2
C213
10U_1206_6.3V6M~D
2
1
C138
10U_1206_6.3V6M~D
1
C128
10U_1206_6.3V6M~D
2
1
C139
10U_1206_6.3V6M~D
2
1
1
2
C167
10U_1206_6.3V6M~D
2
C212
10U_1206_6.3V6M~D
2
1
C526
10U_1206_6.3V6M~D
1
C528
10U_1206_6.3V6M~D
2
1
C530
10U_1206_6.3V6M~D
2
C529
10U_1206_6.3V6M~D
2
D
D
+VCC_CORE
+VCC_CORE
1
1
2
C463
10U_1206_6.3V6M~D
2
1
C464
10U_1206_6.3V6M~D
1
C208
10U_1206_6.3V6M~D
1
C163
10U_1206_6.3V6M~D
1
1
2
C443
10U_1206_6.3V6M~D
2
C168
10U_1206_6.3V6M~D
2
2
2
1
1
1
+VCC_CORE
1
C532
10U_1206_6.3V6M~D
1
C527
10U_1206_6.3V6M~D
2
1
C440
10U_1206_6.3V6M~D
2
C207
10U_1206_6.3V6M~D
2
+VCC_CORE
1
1
2
C165
10U_1206_6.3V6M~D
2
C127
10U_1206_6.3V6M~D
C166
10U_1206_6.3V6M~D
2
C215
10U_1206_6.3V6M~D
2
1
1
2
C144
10U_1206_6.3V6M~D
2
C211
10U_1206_6.3V6M~D
2
1
C441
10U_1206_6.3V6M~D
1
C531
10U_1206_6.3V6M~D
2
1
C525
10U_1206_6.3V6M~D
2
C444
10U_1206_6.3V6M~D
2
+VCC_CORE
X7R
C
1
1
2
C214
10U_1206_6.3V6M~D
2
1
C465
10U_1206_6.3V6M~D
1
C209
10U_1206_6.3V6M~D
2
1
C466
10U_1206_6.3V6M~D
2
High Frequence Decoupling
10uF 1206 X5R -> 85 degree
C210
10U_1206_6.3V6M~D
2
C
Near VCORE regulator.
+VCC_CORE
2
1
C665
+
+
2
ESR <= 3m ohm
220U_D2_2VM~D
2
1
220U_D2_2VM~D
+
C85
2
1
C408
+
@ 220U_D2_2VM~D
2
1
C407
+
@ 220U_D2_2VM~D
2
C416
B
1
220U_D2_2VM~D
C415
+
220U_D2_2VM~D
1
NOTE:Place close to CPU south side
Capacitor > 880 uF
B
+VCCP
1
1
+
2
C160
150U _D2_6.3VM~D
1
C446
0.1U_0402_10V7K~D
2
1
C447
0.1U_0402_10V7K~D
2
1
C448
0.1U_0402_10V7K~D
2
1
C457
0.1U_0402_10V7K~D
2
1
C452
0.1U_0402_10V7K~D
2
1
1
C437
0.1U_0402_10V7K~D
2
C436
0.1U_0402_10V7K~D
2
1
C432
0.1U_0402_10V7K~D
2
1
C435
0.1U_0402_10V7K~D
2
C445
0.1U_0402_10V7K~D
2
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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Dothan Bypass
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
9
of
50
5
4
3
2
1
U15B
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
T3
PAD~D
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
<7>
<7>
<7>
<7>
<7>
<7>
<7>
H_ADS#
H_TRDY#
H10
F8
B5
G6
H_DRDY#
F7
H_DEFER#
E6
TP_H_EDRDY# F6
H_HITM#
D6
H_HIT#
D4
H_LOCK#
B3
H_BR0#
E7
H_BNR#
A5
H_BPRI#
D5
H_DBSY#
C6
H_R_CPUSLP#
G8
H_RS#0
A4
H_RS#1
C5
H_RS#2
B4
HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HEDRDY#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HSLPCPU#
HRS0#
HRS1#
HRS2#
J11
C1
C2
T1
L1
D1
P1
HVREF
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING
<7> H_RS#[0..2]
ALVISO_BGA1257~D
H_CPUSLP#
R97
0_0402_5%~D
1
2
<17>
<17>
<16>
<16>
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
2
AM33
AL1
AE11
AJ34
AF6
AC10
M_CLK_DDR3
M_CLK_DDR4
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#3
M_CLK_DDR#4
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
AP21
AM21
AH21
AK21
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
AN16
AM14
AH15
AG16
80.6_0603_1%~D
SMRCOMPN
SMRCOMPP
<16,17,45> V_DDR_MCH_REF
+VCCP
R457
80.6_0603_1%~D
H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1
+VCCP
1
2
AN33
AK1
AE10
AJ33
AF5
AD10
1
2
1
AF22
AF16
AP14
AL15
AM11
AN10
AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10
CFG/RSVD
M_CLK_DDR0
M_CLK_DDR1
DMI
Y33
AA37
AB33
AC37
M_OCDOCMP0
M_OCDOCMP1
M_ODT0
M_ODT0
M_ODT1
M_ODT1
M_ODT2
M_ODT2
M_ODT3
M_ODT3
<17>
<17>
<16>
<16>
R458 1
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
DDR MUXING
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
+1.8VSUS
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT
2
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
CFG0
MCH_CLKSEL1
MCH_CLKSEL0
PAD~D T19
PAD~D T20
CFG5
CFG6
CFG7
CFG0
<12>
MCH_CLKSEL1 <6>
MCH_CLKSEL0 <6>
D
CFG5
CFG6
CFG7
<12>
<12>
<12>
CFG9
CFG9
<12>
CFG12
CFG13
CFG12
CFG13
<12>
<12>
CFG16
CFG16
<12>
CFG18
CFG19
CFG18
CFG19
<12>
<12>
THERMTRIP_MCH# 1
R114
75_0402_5%~D
2
+VCCP
C
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PWROK
RSTIN#
DREF_CLKN
DREF_CLKP
DREF_SSCLKP
DREF_SSCLKN
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
J23
J21
H22
F5
AD30
AE29
PM_EXTTS#0
PM_EXTTS#1
THERMTRIP_MCH#
PLTRST_R#
A24
A23
D37
C37
1
R200
PM_BMBUSY# <22>
THERMTRIP_MCH# <15>
IMVP_PWRGD <22,39,46>
2
PLTRST_MCH# <20>
100_0603_1%~D
+1.5VRUN
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
ALVISO_BGA1257~D
B
Layout Note:
Rote as short
as possible
PM_EXTTS#0
R413
10K_0402_5%~D
2
1
PM_EXTTS#1
R398
10K_0402_5%~D
2
1
+2.5VRUN
M_OCDOCMP0
M_OCDOCMP1
H_R_CPUSLP#
Note:
"Do not install R97 for Dothan-A,
Install R97 for Dothan-B"
A
<17>
<17>
<16>
<16>
AA33
AB37
AC33
AD37
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
PM
R157
221_0603_1%~D
2
1
R132
100_0603_1%~D
2
1
R131
221_0603_1%~D
2
1
<16> M_CLK_DDR#3
<16> M_CLK_DDR#4
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
CLK
C146
0.1U_0402_16V4Z~D
R176
100_0603_1%~D
2
1
<17> M_CLK_DDR#0
<17> M_CLK_DDR#1
R455
40.2_0603_1%~D
2
1
@
<7,21> H_CPUSLP#
<16> M_CLK_DDR3
<16> M_CLK_DDR4
Y31
AA35
AB31
AC35
C484
0.1U_0402_16V4Z~D
<7>
<7>
<7>
<7>
<7>
H_RESET#
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
C490
0.1U_0402_16V4Z~D
H_RESET#
2
<22>
<22>
<22>
<22>
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
1
<7>
1
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
<17> M_CLK_DDR0
<17> M_CLK_DDR1
+VCCP
H_SWNG0
<22>
<22>
<22>
<22>
2
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HDINV#0
HDINV#1
HDINV#2
HDINV#3
2
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
AA31
AB35
AC31
AD35
R456
40.2_0603_1%~D
2
1
B
<7>
<7>
<7>
<7>
G4
K1
R3
V3
G5
K2
R2
W4
H8
K3
T7
U5
1
<22>
<22>
<22>
<22>
R143
100_0603_1%~D
2
1
Layout Guide will show
these signals routed
differentially.
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
HCLKN
HCLKIN
Layout Guide
will show these
signals routed
differentially.
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
R142
200_0603_1%~D
2
1
<7> H_DSTBP#[0..3]
AB1
AB2
H_SWNG1
C124
0.1U_0402_10V7K~D
<6> CLK_MCH_BCLK#
<6> CLK_MCH_BCLK
<7> H_DSTBN#[0..3]
HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HADSTB#0
HADSTB#1
+VCCP
R156
54.9_0603_1%~D
2
1
<7> H_ADSTB#0
<7> H_ADSTB#1
A11
A7
D7
B8
C7
A8
B9
E13
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
<7>
C112
0.1U_0402_16V4Z~D
C
TP_H_PCREQ#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
R121
54.9_0603_1%~D
2
1
PAD~D
<7> H_REQ#[0..4]
Alviso
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
R125
24.9_0603_1%~D
2
1
T1
G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13
R180
24.9_0603_1%~D
2
1
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
HOST
D
H_D#[0..63]
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
NC
U15A
<7> H_A#[3..31]
<22>
<22>
<22>
<22>
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
Alviso(1 of 5)
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
10
of
50
5
4
3
2
1
D
D
This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
<17> DDR_A_DQS#[0..7]
differentially.
C
<17> DDR_A_MA[0..13]
T25 PAD~D
T24 PAD~D
<17> DDR_A_CAS#
<17> DDR_A_RAS#
<17> DDR_A_WE#
AK15
AK16
AL21
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
AJ37
AP35
AL29
AP24
AP9
AP4
AJ2
AD3
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
AK36
AP33
AN29
AP23
AM8
AM4
AJ1
AE5
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15
DDR_A_CAS#
DDR_A_RAS#
TP_MA_RCVENIN#
TP_MA_RCVENOUT#
DDR_A_WE#
AN15
AP16
AF29
AF28
AP15
SA_BS0#
SA_BS1#
SA_BS2#
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
DDR MEMORY SYSTEM A
<17> DDR_A_DQS[0..7]
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
B
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_D[0..63]
U15D
<17>
<16> DDR_B_BS#0
<16> DDR_B_BS#1
<16> DDR_B_BS#2
<16> DDR_B_DM[0..7]
This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.
<16> DDR_B_DQS[0..7]
<16> DDR_B_DQS#[0..7]
<16> DDR_B_MA[0..13]
T22 PAD~D
T23 PAD~D
<16> DDR_B_CAS#
<16> DDR_B_RAS#
<16> DDR_B_WE#
ALVISO_BGA1257~D
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
AJ15
AG17
AG21
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7
DDR_B_DQS0 AF34
DDR_B_DQS1 AK32
DDR_B_DQS2 AJ28
DDR_B_DQS3 AK23
DDR_B_DQS4 AM10
DDR_B_DQS5
AH6
DDR_B_DQS6
AF8
DDR_B_DQS7
AB4
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15
DDR_B_CAS#
DDR_B_RAS#
TP_MB_RCVENIN#
TP_MB_RCVENOUT#
DDR_B_WE#
AH14
AK14
AF15
AF14
AH16
SB_BS0#
SB_BS1#
SB_BS2#
SD_DM0
SD_DM1
SD_DM2
SD_DM3
SD_DM4
SD_DM5
SD_DM6
SD_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
DDR SYSTEM MEMORY B
U15C
<17> DDR_A_BS#0
<17> DDR_A_BS#1
<17> DDR_A_BS#2
<17> DDR_A_DM[0..7]
SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
DDR_B_D[0..63]
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
<16>
C
B
ALVISO_BGA1257~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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Alviso(2 of 5)
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
11
of
50
5
4
3
2
1
+1.5VRUN_PCIE
U15G
MISC
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
C
B30
B29
C25
C24
B34
B33
B32
A34
A33
B31
C29
D28
C27
B
C28
D27
C26
LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
LACLKN
LACLKP
LBCLKN
LBCLKP
LVDS
E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
LADATAN0
LADATAN1
LADATAN2
PCI - EXPRESS GRAPHICS
+VCCP
E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
J20
EXP_COMPI
EXP_ICOMPO
TV
A15
C16
A17
J18
B15
B16
B17
SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP
VGA
H24
H25
AB29
AC29
<6> CLK_MCH_3GPLL#
<6> CLK_MCH_3GPLL
D
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
D36
D34
PEGCOMP
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
R129
24.9_0603_1%~D
1
2
PEG_RXN[0..15]
LADATAP0
LADATAP1
LADATAP2
LBDATAN0
LBDATAN1
LBDATAN2
LBDATAP0
LBDATAP1
LBDATAP2
<18>
CFG[2:0]
CFG5
CFG6
CFG7
PEG_RXP[0..15]
PEG_RXP[0..15] <18>
This Symbol as same
as Intel CRB
schematic, So Layout
Guide will show these
signals routed
differentially.
PEG_TXN[0..15]
PEG_TXP[0..15]
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
PEG_RXN[0..15]
PEG_TXN[0..15] <18>
CFG9
CFG[13:12]
CFG16
(FSB Dynamic
ODT)
CFG18
(VCC Select)
CFG19
(VTT Select)
+VCCP
Refer to sheet 6 for FSB
frequency select
D
<10>
Low = DMI x 2
*
High = DMI x 4
*
Low = DDR-II
High = DDR-I
Low = DT/Transportable CPU
High = Mobile CPU
Low = Reverse Lane
*
*
High = Normal Operation
00
01
10
11
= Reserved
= XOR Mode Enabled
= All Z Mode Enabled
= Normal Operation (Default)
CFG0
<10>
CFG5
<10>
CFG6
<10>
CFG7
<10>
CFG9
<10>
CFG12
<10>
CFG13
<10>
CFG16
R415
2
1
10K_0402_5%~D
R408
1
2 @ 2.2K_0402_5%~D
R404
1
2
R108
1
2 @ 2.2K_0402_5%~D
R401
1
2 @ 2.2K_0402_5%~D
R402
1
2 @ 2.2K_0402_5%~D
R411
1
2 @ 2.2K_0402_5%~D
R412
1
2 @ 2.2K_0402_5%~D
2.2K_0402_5%~D
CFG[17:3] have internal pull-up
*
Low = Disabled
High = Enabled
+2.5VRUN
*
Low = 1.05V (Default)
High = 1.5V
Low = 1.05V (Default)
High = 1.2V
*
<10>
<10>
CFG18
CFG19
*
R406
2 @ 1K_0402_5%~D
2
@ 1K_0402_5%~D
1
1
R407
C
CFG[19:18] have internal pull-down
PEG_TXP[0..15] <18>
B
ALVISO_BGA1257~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
Alviso(3 of 5)
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
12
of
50
5
4
3
2
1
U15F
C449
0.22U_0603_10V7K~D
1
2
1
2
1
+
2
AC2
AC1
B23
C35
AA1
AA2
+1.5VRUN
+1.5VRUN_DPLLA
+1.5VRUN_DPLLB
+1.5VRUN_HPLL
+1.5VRUN_MPLL
V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3
VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2
VCCA_3GBG
VSSA_3GBG
VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCC_SYNC
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
+2.5VRUN
B22
B21
A21
+2.5VRUN
B28
A28
A27
2
+2.5VRUN
+1.5VRUN_DDRDLL
AF20
AP19
AF19
AF18
AE37
W37
U37
R37
N37
L37
J37
1
2
1
+1.5VRUN
L34
BLM18PG600SN1_0603
2
1
+1.5VRUN_PCIE
2
1
+
2
+1.5VRUN
L32
BLM18PG600SN1_0603
2
1
+
1
2
+1.5VRUN_3GPLL
1
2
Y29
Y28
Y27
1
2
+1.5VRUN
R422
L78
0.5_0805_1%~D
BLM18PG600SN1_0603
1
23GRLL_R 2
1
1
2
F37
G37
1
1
2
2
C
2
+2.5VRUN_3GBG
+2.5VRUN
L24
BLM11A601S_0603~D
2
1
1
1
C119
0.1U_0402_16V4Z~D
H20
F19
E19
G19
1
C231
0.1U_0402_16V4Z~D
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
A35
2
C186
0.1U_0402_16V4Z~D
VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3
+1.5VRUN
C497
0.1U_0402_16V4Z~D
+1.8VSUS
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
B26
B25
A25
1
C479
10U_1206_6.3V6M~D
C515
0.1U_0402_10V7K~D
C504
0.1U_0402_10V7K~D
C523
0.1U_0402_10V7K~D
Note: Place near chip.
VCCHV0
VCCHV1
VCCHV2
1
C462
0.1U_0402_16V4Z~D
2
VCCA_LVDS
D19
H17
C126
10U_1206_6.3V6M~D
2
1
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
D
H18
G18
C173
10U_1206_6.3V6M~D
2
1
VCCD_TVDAC
VCCDQ_TVDAC
+1.5VRUN
C510
220U_D2_4VM
1
VCCA_TVBG
VSSA_TVBG
Close B26,B25,A25
C237
100U_D2_6.3VM_R45~D
V1.8_DDR_CAP6
V1.8_DDR_CAP4
V1.8_DDR_CAP3
POWER
F17
E17
D18
C18
F18
E18
C520
0.1U_0402_16V4Z~D
C460
4.7U_0805_6.3V6K~D
C422
0.47U_0603_16V7K~D
C453
2.2U_0805_10V6K~D
C423
0.47U_0603_16V7K~D
Note : All VCCSM pin
shorted internally.
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
10U_1206_6.3V6M~D
2
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
C418
0.1U_0402_16V4Z~D
2
1
0.1U_0402_10V7K~D
2
1
2
@ 330U_D2E_2.5VM~D
1
2
1
C519
0.1U_0402_10V7K~D
2
V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5
1
U15E
T29
R29
N29
M29
K29
J29
V28
U28
T28
R28
P28
N28
M28
L28
K28
J28
H28
G28
V27
U27
T27
R27
P27
N27
M27
L27
K27
J27
H27
K26
H26
K25
J25
K24
K23
K22
K21
W20
U20
T20
K20
V19
U19
K19
W18
V18
T18
K18
K17
+VCCP
C513
0.1U_0402_10V7K~D
1
W=20 mils
C238
10U_1206_6.3V6M~D
2
2
V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5
C233
10U_1206_6.3V6M~D
1
2
1
AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8
AM1
AE1
C495
C
1
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64
C638
+VCCP
POWER
C118
0.22U_0603_10V7K~D
D
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
C232
K13
J13
K12
W11
V11
U11
T11
R11
P11
N11
M11
L11
K11
W10
V10
U10
T10
R10
P10
N10
M10
K10
J10
Y9
W9
U9
R9
P9
N9
M9
L9
J9
N8
M8
N7
M7
N6
M6
A6
N5
M5
N4
M4
N3
M3
N2
M2
B2
V1
N1
M1
G1
C120
0.1U_0402_16V4Z~D
2
+VCCP
2
Route VSSA3GBG gnd from GMCH to
decoupling cap ground lead and
then connect to the gnd plane.
ALVISO_BGA1257~D
ALVISO_BGA1257~D
+1.8VSUS
2
A
1
2
1
+
2
2
1
2
1
2
1
2
1
2
C428
0.1U_0402_16V4Z~D
2
1
C426
0.1U_0402_16V4Z~D
2
1
C427
0.01U_0402_16V7K~D
2
1
C90
4.7U_0805_6.3V6K~D
2
1
C79
4.7U_0805_6.3V6K~D
2
1
C425
10U_1206_6.3V6M~D
1
C456
0.1U_0402_16V4Z~D
2
+2.5VRUN
W=20 mils
C450
0.1U_0402_16V4Z~D
1
C459
10U_1206_6.3V6M~D
+1.5VRUN
+1.5VRUN_MPLL
L30
BLM11A601S_0603~D
1
2
C461
0.1U_0402_16V4Z~D
+
0.1U_0402_16V4Z~D
C485
2
1
C477
470U_D2_2.5VM~D
1
+1.5VRUN_HPLL
L29
BLM11A601S_0603~D
1
2
0.1U_0402_16V4Z~D
C430
C429
2
0.1U_0402_16V4Z~D
1
+1.5VRUN_DPLLB
L19
BLM11A601S_0603~D
1
2
+1.5VRUN
C481
470U_D2_2.5VM~D
+1.5VRUN
+1.5VRUN_DPLLA
L15
BLM11A601S_0603~D
1
2
+1.5VRUN
C455
10U_1206_6.3V6M~D
+VCCP
C451
0.1U_0402_16V4Z~D
2
B
C454
10U_1206_6.3V6M~D
2
1
0.1U_0402_16V4Z~D
2
1
C644
0.1U_0402_16V4Z~D
2
1
C643
0.1U_0402_16V4Z~D
2
1
C642
0.1U_0402_16V4Z~D
C639
2
1
C641
0.1U_0402_16V4Z~D
1
C640
0.1U_0402_16V4Z~D
B
1
2
1
2
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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Alviso(4 of 5)
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
13
of
50
5
C
B
A
Y12
AA12
Y13
AA13
L14
M14
N14
P14
R14
T14
U14
V14
W14
Y14
AA14
AB14
L15
M15
N15
P15
R15
T15
U15
V15
W15
Y15
AA15
AB15
L16
M16
N16
P16
R16
T16
U16
V16
W16
Y16
AA16
AB16
R17
Y17
AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20
R21
Y21
AA21
AB21
Y22
AA22
AB22
Y23
AA23
AB23
Y24
AA24
AB24
Y25
AA25
AB25
Y26
AA26
AB26
V25
W25
L26
M26
N26
P26
R26
T26
U26
V26
W26
VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0
VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0
VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0
3
2
1
+1.8VSUS
U15H
L12
M12
N12
P12
R12
T12
U12
V12
W12
L13
M13
N13
P13
R13
T13
U13
V13
W13
VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10
VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0
NCTF
+VCCP
D
4
VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11
D
AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26
L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25
U15I
Y1
D2
G2
J2
L2
P2
T2
V2
AD2
AE2
AH2
AL2
AN2
A3
C3
AA3
AB3
AC3
AJ3
C4
H4
L4
P4
U4
Y4
AF4
AN4
E5
W5
AL5
AP5
B6
J6
L6
P6
T6
AA6
AC6
AE6
AJ6
G7
V7
AA7
AG7
AK7
AN7
C8
E8
L8
P8
Y8
AL8
A9
H9
K9
T9
V9
AA9
AC9
AE9
AH9
AN9
D10
L10
Y10
AA10
F11
H11
Y11
+VCCP
VSS271
VSS270
VSS269
VSS268
VSS260
VSS259
VSS258
VSS257
VSS256
VSS255
VSS254
VSS253
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196
U15J
VSSALVDS
VSS
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
AL24
AN24
A26
E26
G26
J26
B27
E27
G27
W27
AA27
AB27
AF27
AG27
AJ27
AL27
AN27
E28
W28
AA28
AB28
AC28
A29
D29
E29
F29
G29
H29
L29
P29
U29
V29
W29
AA29
AD29
AG29
AJ29
AM29
C30
Y30
AA30
AB30
AC30
AE30
AP30
D31
E31
F31
G31
H31
J31
K31
L31
M31
N31
P31
R31
T31
U31
V31
W31
AD31
AG31
AL31
A32
C32
Y32
AA32
AB32
B36
AA11
AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24
ALVISO_BGA1257~D
VSS267
VSS266
VSS265
VSS264
VSS263
VSS262
VSS261
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0
VSS
C
B
ALVISO_BGA1257~D
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
ALVISO_BGA1257~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37
4
3
2
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Alviso(5 of 5)
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
14
of
50
5
4
3
8
R104
100K_0402_5%~D
1
2
FAN1_VFB
2
IN-
U4A
LM358M_SO8~D
FAN1_ON
1
O
C
FAN1 Control and Tachometer
D Q47
G
SI3456DV-T1_TSOP6~D
S
1
B
+3VRUN
3
E
2
3
4
1
4
1
IN+
P
3
2222
R476
10K_0402_5%~D
2
SYMBOL(SOT23-NEW)
D
2
C583
@ 2200P_0402_50V7K~D
1
2
FAN1_TACH
1
R481
100K_0402_5%~D
2
1
<35>
C559
JFAN1
FAN1_VOUT
+
D18
RB751V_SOD323~D
2
2
1
2
+15V
1
2
3
C560
1000P_0402_50V7K~D
C257
47U_D_16VM_R70~D
1
1
R483
150K_0402_5%~D
1
2
D
+5VRUN
G
FAN1VREF
C75
1U_0603_10V4Z~D
<35> FAN1_PWM
1
1
2
5
6
+15V
2
2
0.47U_0603_16V7K~D
E&T_3801-03-1~D
FAN1
2
6
IN-
G
3
S
SI3456DV-T1_TSOP6~D
+3VRUN
C
4
1
IN+
P
5
FAN2_VFB
D Q7
G
FAN2VREF
1
2
R57
10K_0402_5%~D
2
C74
@ 2200P_0402_50V7K~D
1
2
FAN2_TACH
R82
100K_0402_5%~D
2
1
1
JFAN2
FAN2_5V
D5
RB751V_SOD323~D
2
2
1
2
1
2
3
C64
1000P_0402_50V7K~D
+
C65
47U_D_16VM_R70~D
1
1
R96
150K_0402_5%~D
1
2
C
FAN2 Control and Tachometer
U4B
LM358M_SO8~D
FAN2_ON
7
O
4
C84
1U_0603_10V4Z~D
<35> FAN2_PWM
8
R111
100K_0402_5%~D
1
2
1
2
5
6
1
C51
0.1U_0603_25V7K~D
@
+5VRUN
2
<35>
C54
0.47U_0603_16V7K~D
E&T_3801-03-1~D
FAN2
@
+3VSUS
<7> H_THERMDA
ATF_INT#
<34>
2
1
R430
2
8.2K_0402_5%~D
THERMATRIP1#
6
THERMATRIP2#
7
THERMATRIP_VGA#
8
22
14
3
2
2
1
2
R418
12.1K_0603_1%~D
1
1
A
C478
2200P_0402_50V7K~D
R452
1K_0402_5%~D
R421
30.1K_0603_1%~D
RESSERVED
16
2
1
3
1
C489
2 2200P_0402_50V7K~D
2
2
G
5V_CAL_SIO#
<34>
S
3
+RTC_PWR3V
C95
0.1U_0402_16V4Z~D
2
+3VSUS
+3V_PWROK
THERMTRIP1
REM_DIODE1_N
REM_DIODE1_P
THERMTRIP3
REN_DIODE_N
REN_DIODE_P
19
20
THERMTRIP2
1
+3VALW
THERMTRIP_SIO
THERM_STP
VSET
HW_LOCK
VSS
EMC6N300_SSOP24~D
INTRUDER
15
24
1
Trace width = 10mil
POWER_SW
R386
8.2K_0402_5%~D
2
C503
2 2200P_0402_50V7K~D
+VCCP
Q40
MMBT3904_SOT23~D
R388
2.2K_0402_5%~D
2
2
Q37 B
MMBT3904_SOT23~D
R451
100K_0402_5%~D
12
2
21
1
2
5
Q46
2N7002_SOT23~D
3
2
1K_0402_5%~D
1
THERMATRIP2#
1
1
+3VSUS
1
1
1
R433
C
E
<7> H_THERMTRIP#
D
1
+3VSUS
VSUS_PWRGD
1
<18> THERMATRIP_VGA#
R450
10K_0402_5%~D
23
1
4
2
11
1K_0402_5%~D
10
<35,37> POWER_SW#
2
10KB_0603_1%_TSM1A103F34D3R~D
THERMATRIP1#
C
1
1
C406
0.1U_0402_16V4Z~D
E
2
2
C508
<39> ICH_PWRGD#
0.1U_0402_16V4Z~D
VCP
R120
2.2K_0402_5%~D
1
2
2
Q8 B
MMBT3904_SOT23~D
R475
R424
2.21K_0603_1%~D
REM_DIODE2_P
REM_DIODE2_N
+VCCP
B
+3VSUS_R
1
R444
+RTC_CELL
1
ATF_INT
SMBADDRSEL
2
2
13
1K_0402_5%~D
18
17
2
<22,39> SUSPWROK
C483
0.1U_0402_16V4Z~D
B
+5VSUS
9
2
1
R453
THDAT_SMB
THCLK_SMB
E
C496
0.1U_0402_16V4Z~D
1
2
<35,36> DAT_SMB
<35,36> CLK_SMB
C
R428
49.9_0603_1%~D
1
2
1
+3VSUS
R124
8.2K_0402_5%~D
+5VSUS
U25
3
<7> H_THERMDC
1
C505
2200P_0402_50V7K~D
B
1
1
THERMTRIP_SIO
<35>
THERM_STP#
<44>
INTRUDER#
<21>
<10> THERMTRIP_MCH#
A
DELL CONFIDENTIAL/PROPRIETARY
2
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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Thermal sensor and Fan
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
15
of
50
5
4
3
2
+1.8VSUS
<11> DDR_B_DQS#[0..7]
V_DDR_MCH_REF
DDR_B_D2
DDR_B_D3
+1.8VSUS
DDR_B_D8
DDR_B_D9
@
1
10P_0402_50V8J~D
10P_0402_50V8J~D
2
DDR_B_DQS#1
DDR_B_DQS1
@
M_CLK_DDR3
C287
2
M_CLK_DDR#3
M_CLK_DDR4
1
DDR_B_D10
DDR_B_D11
C289
2
M_CLK_DDR#4
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
C294
1
1
C311
C317
2
2.2U_0805_10V6K~D
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
1
1
C292
C291
2
C318
0.1U_0402_16V4Z~D
2
1
1
2.2U_0805_10V6K~D
2
C293
0.1U_0402_16V4Z~D
1
C310
2
1
2.2U_0805_10V6K~D
2.2U_0805_10V6K~D
C312
2.2U_0805_10V6K~D
1
DDR_B_D18
DDR_B_D19
2
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
<10> DDR_CKE2_DIMMB
C
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
DDR_B_BS#2
<11> DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
<11> DDR_B_BS#0
<11> DDR_B_WE#
+0.9V_DDR_VTT
DDR_B_CAS#
DDR_CS3_DIMMB#
<11> DDR_B_CAS#
<10> DDR_CS3_DIMMB#
2
1
2
M_ODT3
M_ODT3
1
DDR_B_D32
DDR_B_D33
2
DDR_B_DQS#4
DDR_B_DQS4
C296
C302
C301
C299
C300
C297
C579
C577
C582
C298
C578
C581
C580
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
1
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
<10>
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
B
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
+0.9V_DDR_VTT
DDR_B_MA1
1
DDR_B_MA3
2
56_0404_4P2R_5%~D
4
3
RN13
4
3
4
3
4
3
4
3
DDR_B_MA5
1
DDR_B_MA8
2
56_0404_4P2R_5%~D
RN23
RN26
DDR_B_D56
DDR_B_D57
Layout Note:
Place these resistor
closely JDIM1,all
trace length<750 mil
DDR_B_MA7
1
DDR_B_MA6
2
56_0404_4P2R_5%~D
DDR_B_D58
DDR_B_D59
CK_SDATA
CK_SCLK
+3VRUN
56_0404_4P2R_5%~D
4
3
DDR_B_BS#2
1
DDR_CKE2_DIMMB
2
56_0404_4P2R_5%~D
Layout Note:
Place these resistor
closely JDIM1,all
trace length
Max=1.3"
2
1
2
4
2
DDR_B_D12
DDR_B_D13
D
DDR_B_DM1
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR3 <10>
M_CLK_DDR#3 <10>
DDR_B_D14
DDR_B_D15
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB <10>
C
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
DDR_B_MA13
DDR_B_BS#1 <11>
DDR_B_RAS# <11>
DDR_CS2_DIMMB# <10>
M_ODT2
<10>
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
B
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR4
M_CLK_DDR#4
M_CLK_DDR4 <10>
M_CLK_DDR#4 <10>
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
+3VRUN
R271
1
DIMMA
STANDARD
2
10K_0402_5%~D
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
1
R272
3
4
DDR_B_D6
DDR_B_D7
10K_0402_5%~D
RN15
RN9
DDR_CS3_DIMMB# 2
M_ODT3
1
2
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
DDR_B_DM0
FOX_AS0A426-M2S-TR~D
1
C313
M_ODT2
1
DDR_B_MA13
2
56_0404_4P2R_5%~D
4
3
1
C319
RN27
2.2U_0805_10V6K~D
DDR_B_MA4
1
DDR_B_MA2
2
56_0404_4P2R_5%~D
4
3
0.1U_0402_16V4Z~D
4
3
A
DDR_B_DM7
<6,17> CK_SDATA
<6,17> CK_SCLK
RN24
RN10
DDR_B_CAS#
1
DDR_B_WE#
2
56_0404_4P2R_5%~D
DDR_CKE3_DIMMB
1
DDR_B_MA11
2
56_0404_4P2R_5%~D
4
3
RN25
DDR_B_RAS#
1
DDR_CS2_DIMMB# 2
56_0404_4P2R_5%~D
DDR_B_D50
DDR_B_D51
RN22
4
3
DDR_B_MA0
1
DDR_B_BS#1
2
56_0404_4P2R_5%~D
DDR_B_MA9
1
DDR_B_MA12
2
56_0404_4P2R_5%~D
4
3
RN11
DDR_B_BS#0
1
DDR_B_MA10
2
56_0404_4P2R_5%~D
DDR_B_DQS#6
DDR_B_DQS6
RN14
RN12
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
DDR_B_D4
DDR_B_D5
1
DDR_B_DQS#0
DDR_B_DQS0
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
2
<11> DDR_B_MA[0..13]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
<10,17,45>
C320
DDR_B_D0
DDR_B_D1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
C308
<11> DDR_B_DQS[0..7]
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
0.1U_0402_16V4Z~D
JDIM1
Layout Note:
Place near JDIM1
<11> DDR_B_DM[0..7]
V_DDR_MCH_REF
2.2U_0805_10V6K~D
<11> DDR_B_D[0..63]
D
1
+1.8VSUS
3
2
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DDRII-SODIMM SLOT1
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
16
of
50
5
4
3
2
1
+1.8VSUS
+1.8VSUS
V_DDR_MCH_REF
<11> DDR_A_DQS#[0..7]
DDR_A_DQS#1
DDR_A_DQS1
@
@
M_CLK_DDR0
1
10P_0402_50V8J~D
2
C328
2
M_CLK_DDR#0
M_CLK_DDR1
1
C329
M_CLK_DDR#1
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
2
DDR_A_DM3
DDR_A_D26
DDR_A_D27
<10> DDR_CKE0_DIMMA
C
<11> DDR_A_BS#2
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<11> DDR_A_BS#0
<11> DDR_A_WE#
<11> DDR_A_CAS#
<10> DDR_CS1_DIMMA#
+0.9V_DDR_VTT
<10>
M_ODT1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D32
DDR_A_D33
2
1
2
1
2
1
DDR_A_D34
DDR_A_D35
2
DDR_A_D40
DDR_A_D41
C604
C603
C602
C334
C332
C333
C331
C330
C335
C608
C607
C606
C605
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
1
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
1
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
B
1
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
+0.9V_DDR_VTT
RN32
DDR_A_MA5
1
DDR_A_MA8
2
56_0404_4P2R_5%~D
RN30
4
3
RN33
DDR_A_MA1
1
DDR_A_MA3
2
56_0404_4P2R_5%~D
RN20
4
3
RN31
+3VRUN
0.1U_0402_16V4Z~D
A
RN18
1 DDR_A_MA0
2 DDR_A_BS#1
56_0404_4P2R_5%~D
RN16
1 M_ODT0
2 DDR_A_MA13
56_0404_4P2R_5%~D
4
3
RN21
RN36
DDR_CS1_DIMMA# 2
M_ODT1
1
56_0404_4P2R_5%~D
3
4
4
3
1 DDR_CKE1_DIMMA
2 DDR_A_MA11
56_0404_4P2R_5%~D
CK_SDATA
CK_SCLK
Layout Note:
Place these resistor
closely JDIM2,all
trace length Max=1.3"
1
2
1
2
FOX_AS0A426-M2R-TR~D
DIMMB
REVERSE
M_CLK_DDR0 <10>
M_CLK_DDR#0 <10>
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_CKE1_DIMMA <10>
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_BS#1 <11>
DDR_A_RAS# <11>
DDR_CS0_DIMMA# <10>
M_ODT0
DDR_A_MA13
M_ODT0
4
<10>
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
B
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 <10>
M_CLK_DDR#1 <10>
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
C
R286
4
3
RN35
DDR_A_CAS#
1
DDR_A_WE#
2
56_0404_4P2R_5%~D
<6,16> CK_SDATA
<6,16> CK_SCLK
1 DDR_A_MA4
2 DDR_A_MA2
56_0404_4P2R_5%~D
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
M_CLK_DDR0
M_CLK_DDR#0
R282
4
3
RN19
DDR_A_D58
DDR_A_D59
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
D
DDR_A_DM1
10K_0402_5%~D
4
3
DDR_A_DM7
C345
4
3
1 DDR_A_MA9
2 DDR_A_MA12
56_0404_4P2R_5%~D
DDR_A_D56
DDR_A_D57
C336
4
3
DDR_A_D50
DDR_A_D51
Layout Note:
Place these resistor
closely JDIM2,all
trace length<750 mil
2.2U_0805_10V6K~D
4
3
RN34
DDR_A_BS#0
1
DDR_A_MA10
2
56_0404_4P2R_5%~D
1 DDR_A_MA7
2 DDR_A_MA6
56_0404_4P2R_5%~D
4
3
RN17
DDR_A_RAS#
1
DDR_CS0_DIMMA# 2
56_0404_4P2R_5%~D
1 DDR_A_BS#2
2 DDR_CKE0_DIMMA
56_0404_4P2R_5%~D
4
3
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
2
DDR_A_D12
DDR_A_D13
10K_0402_5%~D
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_A_D16
DDR_A_D17
2
C344
0.1U_0402_16V4Z~D
2
1
1
10P_0402_50V8J~D
2
C325
C340
2.2U_0805_10V6K~D
1
1
C343
C342
2
2.2U_0805_10V6K~D
2
0.1U_0402_16V4Z~D
C323
2
1
1
C326
2.2U_0805_10V6K~D
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C324
C341
2
2.2U_0805_10V6K~D
2.2U_0805_10V6K~D
1
DDR_A_D10
DDR_A_D11
2
1
2
+1.8VSUS
DDR_A_D6
DDR_A_D7
1
1
DDR_A_D8
DDR_A_D9
DDR_A_DM0
1
DDR_A_D2
DDR_A_D3
D
DDR_A_D4
DDR_A_D5
2
DDR_A_DQS#0
DDR_A_DQS0
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
<10,16,45>
C337
<11> DDR_A_MA[0..13]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
C346
DDR_A_D0
DDR_A_D1
Layout Note:
Place near JDIM2
<11> DDR_A_DQS[0..7]
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
0.1U_0402_16V4Z~D
<11> DDR_A_DM[0..7]
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
V_DDR_MCH_REF
2.2U_0805_10V6K~D
JDIM2
<11> DDR_A_D[0..63]
3
2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
DDRII-SODIMM SLOT2
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
17
of
50
5
4
3
2
1
JVID
L11
2
+5VRUN
1
B
C170 1
2 0.1U_0402_16V4Z~D
C174 1
2 0.1U_0402_16V4Z~D
PEG_A_TXP_10
PEG_A_TXN_10
PEG_TXP11
PEG_TXN11
C175 1
2 0.1U_0402_16V4Z~D
C181 1
2 0.1U_0402_16V4Z~D
PEG_A_TXP_11
PEG_A_TXN_11
PEG_TXP12
PEG_TXN12
C182 1
2 0.1U_0402_16V4Z~D
C183 1
2 0.1U_0402_16V4Z~D
PEG_A_TXP_12
PEG_A_TXN_12
PEG_TXP13
PEG_TXN13
C184 1
2 0.1U_0402_16V4Z~D
C185 1
2 0.1U_0402_16V4Z~D
PEG_A_TXP_13
PEG_A_TXN_13
PEG_TXP14
PEG_TXN14
C187 1
2 0.1U_0402_16V4Z~D
C189 1
2 0.1U_0402_16V4Z~D
PEG_A_TXP_14
PEG_A_TXN_14
PEG_TXP15
PEG_TXN15
C191 1
2 0.1U_0402_16V4Z~D
C199 1
2 0.1U_0402_16V4Z~D
PEG_A_TXP_15
PEG_A_TXN_15
+3VSUS
+1.8VSUS
<12> PEG_TXP[0..15]
VDDM
PEG_TXP[0..15]
+15V
<35,39,43,46> RUNPWROK
RUNPWROK
+2.5VRUN
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
A
1
3
PEG_RXP7
PEG_RXN7
DVI_SCLK_L
PEG_RXP8
PEG_RXN8
DVI_SDAT_L
Q59
L87
PEG_RXP9
PEG_RXN9
3
1
1
2N7002_SOT23~D
PEG_RXP[0..15]
PEG_RXP12
PEG_RXN12
1
C67
220P_0402_50V7K~D
2
220P_0402_50V7K~D
PEG_RXP14
PEG_RXN14
PEG_RXP15
PEG_RXN15
+1.5VRUN
THERMATRIP_VGA#
GC_BL_SUSPEND
ICH_PCIE_WAKE#
THERMATRIP_VGA# <15>
+5VRUN
GC_BL_SUSPEND <34>
2
1
2
1
ICH_PCIE_WAKE#
G_PWR_SRC
@
2
1
1
<22,34>
G_PWR_SRC
Q42
1
2
3
2
1
2
1
2
PEG_RXN[0..15]
PEG_RXN[0..15]
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
8
7
6
5
B
SI4435DY_SO8~D
R462
100K_0402_5%~D
<12>
<34,38,39,42,44,45>
RUN_ON
D
S
Q44
2N7002_SOT23~D
2
G
JAE_WB3M200VD1~D
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
C659
PEG_RXP[0..15] <12>
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_RXP13
PEG_RXN13
1
DVI_SDAT
2
BLM11A121S_0603~D
PWR_SRC
PEG_RXP11
PEG_RXN11
2
1
2
PEG_RXP10
PEG_RXN10
C647
PEG_TXN[0..15]
220P_0402_50V7K~D
PEG_RXP6
PEG_RXN6
10U_1210_25V6K~D
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
<12> PEG_TXN[0..15]
PJP11
PAD-OPEN 4x4m
1
2
C658
4
PEG_TXP10
PEG_TXN10
2
GPWR_SRC_ON
PEG_A_TXP_9
PEG_A_TXN_9
220P_0402_50V7K~D
1
PEG_A_TXP_8
PEG_A_TXN_8
2 0.1U_0402_16V4Z~D
C169 1
2 0.1U_0402_16V4Z~D
C66
2
2 0.1U_0402_16V4Z~D
C161 1
2 0.1U_0402_16V4Z~D
C162 1
2
1
C
DVI_SCLK
2
PEG_PWRON#
C155 1
PEG_TXP9
PEG_TXN9
2N7002_SOT23~D
1
1
PEG_TXP8
PEG_TXN8
1
BLM11A121S_0603~D
3
PEG_A_TXP_7
PEG_A_TXN_7
L86
1
1
2 0.1U_0402_16V4Z~D
C154 1
2 0.1U_0402_16V4Z~D
Q58
3
2
C151 1
1
PEG_TXP7
PEG_TXN7
PEG_RXP5
PEG_RXN5
2
PEG_A_TXP_6
PEG_A_TXN_6
PEG_RXP4
PEG_RXN4
R463
100K_0402_5%~D
1
2
2 0.1U_0402_16V4Z~D
C150 1
2 0.1U_0402_16V4Z~D
1
RB751V_SOD323~D
PEG_RXP3
PEG_RXN3
C518
0.1U_0603_25V7K~D
C149 1
2
+5VRUN
25
28
30
32
G2
G4
G6
NC2
D22
PEG_RXP2
PEG_RXN2
DVI_CLK+
DVI_CLK-
+5VRUN
C512
0.1U_0603_25V7K~D
PEG_TXP6
PEG_TXN6
PEG_RXP1
PEG_RXN1
D
C3
C4
C5
CRT_B
CRT_HSYNC
GND
G1
G3
G5
NC1
2
JAE_DV2R029NDA
2
PEG_A_TXP_5
PEG_A_TXN_5
CLK_PCIE_VGA <6>
CLK_PCIE_VGA# <6>
PEG_RXP0
PEG_RXN0
2
2 0.1U_0402_16V4Z~D
C148 1
2 0.1U_0402_16V4Z~D
CRT_R
CRT_G
26
27
29
31
1
C147 1
C1
C2
MMBT3904_SOT23~D
2
PEG_TXP5
PEG_TXN5
C
DVI_DETECT
1
DVI_DETECT
DVI_TX0DVI_TX0+
5.6K_0402_5%~D
PEG_A_TXP_4
PEG_A_TXN_4
2
100K_0402_5%~D
E
PLTRST_VGA# <20>
CLK_PCIE_VGA
CLK_PCIE_VGA#
1
R547
2 0.1U_0402_16V4Z~D
C145 1
2 0.1U_0402_16V4Z~D
R134
2
B
CLK_DDC2
<19>
DAT_DDC2 <19>
DVI_SCLK_L
DVI_SDAT_L
PLTRST_VGA#
Q57
C
R546
C143 1
<19>
13
14
15
16
17
18
19
20
21
22
23
24
DATA2#
DATA3
DATA2
VCC5
SHIELD24
GND5
DATA4#
HPDET
DATA4
DATA0#
DDCCLK
DATA0
DDCDATA
SHIELD5
DATA1#
DATA5#
DATA1
DATA5
SHIELD13
SHIELDCLK
DATA3#
CLK
CRT_VSYNC
CLK#
5.6K_0402_5%~D
PEG_TXP4
PEG_TXN4
VGA_RED
+3VRUN
D
PEG_A_TXP_3
PEG_A_TXN_3
<19>
D
PEG_A_TXP_2
PEG_A_TXN_2
2 0.1U_0402_16V4Z~D
C142 1
2 0.1U_0402_16V4Z~D
<19>
VGA_GRN
S
2 0.1U_0402_16V4Z~D
C140 1
2 0.1U_0402_16V4Z~D
C141 1
VGA_BLU
1
2
3
4
5
6
7
9
10
11
12
8
DVI_SCLK
DVI_SDAT
DVI_TX1DVI_TX1+
G
C134 1
PEG_TXP3
PEG_TXN3
<19>
<19>
S
PEG_TXP2
PEG_TXN2
CLK_DDC2
DAT_DDC2
VSYNC
HSYNC
G
PEG_A_TXP_1
PEG_A_TXN_1
VGA_RED
<19>
R548
PEG_A_TXP_0
PEG_A_TXN_0
2 0.1U_0402_16V4Z~D
C129 1
2 0.1U_0402_16V4Z~D
VGA_GRN
TV_C
DVI_TX2DVI_TX2+
1K_0402_5%~D
2 0.1U_0402_16V4Z~D
C123 1
20.1U_0402_16V4Z~D
C125 1
VGA_BLU
<19>
R545
C121 1
PEG_TXP1
PEG_TXN1
VSYNC
HSYNC
<19>
TV_CVBS
10K_0402_5%~D
PEG_TXP0
PEG_TXN0
TV_C
TV_Y
1
DVI_CLK+
DVI_CLK-
TV_CVBS
2
JDVI
2
DVI_TX2+
DVI_TX2-
TV_Y
C543
0.1U_0603_25V7K~D
DVI_TX1+
DVI_TX1-
+5VALW
SMBCLK_VGA <35>
SMBDAT_VGA <35>
SMBCLK_VGA
SMBDAT_VGA
C535
0.1U_0603_25V7K~D
DVI_TX0+
DVI_TX0-
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
C540
0.1U_0603_25V7K~D
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
C537
0.1U_0603_25V7K~D
2
C414
0.047U_0402_16V4Z~D
C417
0.047U_0402_16V4Z~D
C409
0.047U_0402_16V4Z~D
2
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
C17
D
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
10U_0805_10V4M~D
1
+3VRUN
C18
0.1U_0402_16V4Z~D
BLM31A260SPT_1206~D
4
3
2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
VGA and DVI connector
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
18
of
50
1
3
2
3
2
FOX_MH11777-WRUR6~D
Overlap R8,R1 & L6 for Pop Option
2
SPDIF_SHDN
R8
A
U1
3
C11
0.01U_0402_16V7K~D
2
1
R7
SP_DIF 2
4
Y
1
SP_DIFB
220_0603_1%~D
SP_DIF_C
SN74AHCT1G125DCKR_SC70-5~D
4
5
1
8
SP_DIF_D
SP_DIF_E
L6
@ TA08F010_4P~D
1
1
2
2
0_0805_5%~D
R2
110_0603_1%~D
2
1
SPDIF
SPDIF
<25,34>
1
P
<25>
SPDIF_SHDN
1
G
2
1
1
2
1
2
1
2
1
C383
2
@
82P_0402_50V8J~D
C391
R362
75_0402_5%~D
1
D
+5VRUN
82P_0402_50V8J~D
@
JSVID
SVIDEO_Y
L67
1.8UH_MDF1608A1R8K_10%_0603~D
1
2
TV_Y
D15
DA204U_SOT323~D
@
2
4
6
7
5
3
1
8
9
1
2
D14
DA204U_SOT323~D
@
SVIDEO_C
SVIDEO_CVBS
5
1
C382
2
82P_0402_50V8J~D
C389
R364
1
D16
DA204U_SOT323~D
@
1
+3VSUS
82P_0402_50V8J~D
@
75_0402_5%~D
1
2
L66
1.8UH_MDF1608A1R8K_10%_0603~D
1
2
@
2
1
C384
82P_0402_50V8J~D
C390
75_0402_5%~D
R363
2
CLOSE TO JSVID
82P_0402_50V8J~D
@
1
TV_CVBS
D
<18>
2
OE#
TV_C
@
<18>
3
C23
0.1U_0402_16V4Z~D
<18>
4
L68
1.8UH_MDF1608A1R8K_10%_0603~D
1
2
3
5
C1
R1
0_0805_5%~D
2
@ 300P_1808_3000V8K~D 2
D3
DA204U_SOT323~D
@
1
D2
DA204U_SOT323~D
@
1
1
C
C
D4
DA204U_SOT323~D
@
3
2
3
2
3
2
+3VRUN
+5VRUN
1
1
2
2
@
1
1
C2
10P_0402_50V8J~D
2
CRT_VCC
1
C6
10P_0402_50V8J~D
2
1
C3
10P_0402_50V8J~D
C4
C10
C9
2
@
22P_0402_50V8J~D
1
22P_0402_50V8J~D
2
@
22P_0402_50V8J~D
B
1
C8
R6
R5
2
@
75_0402_5%~D
1
@
75_0402_5%~D
R4
75_0402_5%~D
2
@
1
VGA_BLU
2
VGA_BLU
VGA_GRN
1
<18>
VGA_RED
2
2
T18
PAD~D
0.01U_0402_16V7K~D
VGA_GRN
RB751V_SOD323~D
VGA_RED
<18>
D1
<18>
L3
BLM18BB600SN1D_0603~D
1
2
L5
BLM18BB600SN1D_0603~D
1
2
L4
BLM18BB600SN1D_0603~D
1
2
JVGA
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
RED
DAT_DDC2
GREEN
CRT_VCC
<18>
DAT_DDC2
<18> CLK_DDC2
VSYNC
1
2
1
2
1
2
C386
22P_0402_50V8J~D
K2
<18>
R3
2.2K_0402_5%~D
1
2
R356
2.2K_0402_5%~D
1
2
JVGA_VS
M_ID2#
CLK_DDC2
1
18
19
FOX_DZ11A91-L8
C5
0.1U_0402_16V4Z~D
2
L71
BLM11A121S_0603~D
1
2
L70
BLM11A121S_0603~D
1
2
C385
22P_0402_50V8J~D
A
A1
HSYNC
C392
33P_0402_50V8J~D
K1 A2
<18>
C393
33P_0402_50V8J~D
DDA204U
R358
1K_0402_5%~D
@
2
1
Evaluate Package
R357
1K_0402_5%~D
@
2
1
JVGA_HS
BLUE
B
1
2
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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TV_OUT and CRT connector
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
19
of
50
5
U16B
+3VRUN
RN6
8.2K_1206_8P4R_5%~D
PCI_IRDY#
8
PCI_PLOCK#
7
PCI_DEVSEL#
6
PCI_PERR#
5
1
2
3
4
RN4
8.2K_1206_8P4R_5%~D
PCI_PIRQD#
8
PCI_PIRQB#
7
ICH_GPIO5_PIRQH#
6
PCI_PIRQC#
5
8.2K_0402_5%~D
8.2K_0402_5%~D
8.2K_0402_5%~D
8.2K_0402_5%~D
+3VRUN
8.2K_0402_5%~D
8.2K_0402_5%~D
8.2K_0402_5%~D
8.2K_0402_5%~D
C
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
R461
R254
R255
R454
R459
R480
R251
R468
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
PCI_PIRQA#
PCI_REQ0#
PCI_REQ1#
PCI_REQ3#
PCI_REQ4#
<29,31,33> PCI_FRAME#
<31,33> PCI_PIRQB#
<29,31> PCI_PIRQC#
<31,33> PCI_PIRQD#
+3VRUN
8.2K_0402_5%~D 1
8.2K_0402_5%~D 1
8.2K_0402_5%~D 1
2 R460
2 R466
2 R253
E2
E5
C2
F5
F3
E9
F2
D6
E6
D3
A2
D2
D5
H3
B4
J5
K2
K5
D4
L6
G3
H4
H2
H5
B3
M6
B2
K6
K3
A5
L1
K4
PCI_FRAME#
J3
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
N2
L2
M1
L3
AC5
AD5
AF4
AG4
AC9
AD9
AF8
AG8
U3
PCI_REQ2#
PCI_REQ5#
PCI_REQB#
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
AD[8]
AD[9]
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]
PCI
REQ[0]#
GNT[0]#
REQ[1]#
GNT[1]#
REQ[2]#
GNT[2]#
REQ[3]#
GNT[3]#
REQ[4]#/GPI[40]
GNT[4]#/GPO[48]
REQ[5]#/GPI[1]
GNT[5]#/GPO[17]
REQ[6]#/GPI[0]
GNT[6]#/GPO[16]
C/BE[0]#
C/BE[1]#
C/BE[2]#
C/BE[3]#
PCI_REQ0#
J6
H6
G4
G2
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#
PCI_REQ1#
PCI_GNT1#
<31>
<31>
PCI_REQ3#
PCI_GNT3#
PCI_REQ4#
PCI_GNT4#
<33>
<33>
<29>
<29>
C116
0.1U_0402_16V4Z~D
2
1
+3VSUS
PCI_REQ3#
PCI_GNT3#
PCI_REQ4#
PCI_GNT4#
PCI_REQ5#
PCI_GNT5#
PCI_REQB#
PLTRST#
1
2
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
<29,31,33>
<29,31,33>
<29,31,33>
<29,31,33>
PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
A3
E1
R2
C3
E3
C5
G5
J1
J2
PCI_IRDY# <29,31,33>
PCI_PAR <29,31,33>
Interrupt
I/F
PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]
PIRQ[G]#GPI[4]
PIRQ[H]#/GPI[5]
IN2
PLTRST#
CK_33M_ICHPCI
ICH_PME#
D9
C7
C6
M3
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#
PCI_SERR# <29,31,33>
PCI_STOP# <29,31,33>
PCI_TRDY# <29,31,33>
PCIRSTB1#
D
1
R152
33_0402_5%~D
2
PLTRST_LOM# <29>
1
R154
33_0402_5%~D
2
PLTRST_SIO#
74VHC08MTC_TSSOP14~D
IN1
OUT
6
PCIRSTB2#
IN2
R153
33_0402_5%~D
1
2
U13D
13
PLTRST#
<22,24,37>
CK_33M_ICHPCI <6>
ICH_PME#
<34>
IN1
<34>
PLTRST_MCH# <10>
OUT
11
1
R151
33_0402_5%~D
2
PLTRST_VGA# <18>
IN2
74VHC08MTC_TSSOP14~D
C
U13C
PCI_PCIRST#
RESERVED
10
9
SATA[1]RXN/RSVD[1]
SATA[1]RXP/RSVD[2]
SATA[1]TXN/RSVD[3]
SATA[1]TXP/RSVD[4]
SATA[3]RXN/RSVD[5]
SATA[3]RXP/RSVD[6]
SATA[3]TXN/RSVD[7]
SATA[3]TXP/RSVD[8]
TP[3]/RSVD[9]
3
74VHC08MTC_TSSOP14~D
12
R5
G6
P6
U13A
OUT
PCI_DEVSEL# <29,31,33>
PCI_PERR# <29,31,33>
<22,37> PLTRST_DELAY#
PLTRST#
PCICLK
PME#
IN1
U13B
4
5
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PIRQ[A]#
PIRQ[B]#
PIRQ[C]#
PIRQ[D]#
L5
C1
B5
B6
M5
F1
B8
C8
F7
E7
E8
F6
B7
D8
14
1
2
3
4
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
P
+3VRUN
1
RN5
8.2K_1206_8P4R_5%~D
PCI_SERR#
8
PCI_FRAME#
7
PCI_TRDY#
6
PCI_STOP#
5
<29,31,33> PCI_AD[0..31]
D
2
G
1
2
3
4
3
7
+3VRUN
4
IN1
OUT
8
PCIRSTB3#
R133
33_0402_5%~D
1
2
PCIRST_CB#
<31,33>
IN2
74VHC08MTC_TSSOP14~D
Internal Pull-up.
Sample high destination is LPC.
PCI_GNT5#
CK_33M_ICHPCI
1
ICH6_BGA609~D
2
R470
@ 0_0402_5%~D
CLK_ICH_TERM
1
2
R469
10_0402_5%~D
@
B
B
COINCELL
1
1
R509
1K_0402_5%~D
@
C547
8.2P_0402_50V8J~D
COINCELL_R
2
2
2
3
+3.3VX
D20
BAT54C_SOT23~D
1
+RTC_CELL
1
C596
2 1U_0603_10V4Z~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
ICH6(1/4)
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
20
of
50
5
4
C188
12P_0603_50V8J~D
2
1
R204
10M_0402_5%~D
2
1
AA3
AA5
CMOS_CLR
SHORT PADS~D
INTRUDER#
1
1
2
2
F12
B11
E12
E11
C13
C172
0.1U_0402_16V4Z~D
1
2
C12
C11
E13
<25> ICH_AC_BITCLK
2
<27> ICH_RST_MDC#
2
R250
2
R249
<25> ICH_AC_SDIN0
<27> ICH_AC_SDIN1
ICH_AC_SYNC_R
ICH_AC_RST_R#
A10
ICH_AC_SDIN0
ICH_AC_SDIN1
F11
F10
B10
R252
<27> ICH_SDOUT_MDC
1
ICH_AC_SDOUT_R
2
C9
SATA_ACT#
AC19
SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C
<24> SATA_RXN0_C
<24> SATA_RXP0_C
AE3
AD3
AG2
AF2
AD7
AC7
AF6
AG6
C571
10P_0402_50V8J~D
@
CLK_PCIE_SATA# AC2
CLK_PCIE_SATA AC1
<6> CLK_PCIE_SATA#
<6> CLK_PCIE_SATA
1
B
1
R266
33_0402_5%~D
2 ICH_AC_SDOUT_R
<25> ICH_SYNC_AUDIO
1
R265
33_0402_5%~D
2 ICH_AC_SYNC_R
<25> ICH_RST_AUDIO#
1
R248
33_0402_5%~D
2 ICH_AC_RST_R#
<25> ICH_SDOUT_AUDIO
LAN_CLK
LAN_RSTSYNC
AG11
AF11
2
R177
24.9_0603_1%~D
IDE_DIORDY
IDE_IRQ
IDE_DDACK#
IDE_DIOW#
IDE_DIOR#
<24> IDE_DIORDY
<24> IDE_IRQ
<24> IDE_DDACK#
<24> IDE_DIOW#
<24> IDE_DIOR#
AF16
AB16
AB15
AC14
AE16
A20GATE
A20M#
CPUSLP#
DPRSLP#/TP[4]
DPSLP#/TP[2]
LANRXD[0]
LANRXD[1]
LANRXD[2]
FERR#
CPUPWRGD/GPO[49]
LANTXD[0]
LANTXD[1]
LANTXD[2]
ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN[0]
ACZ_SDIN[1]
ACZ_SDIN[2]
ACZ_SDO
33_0402_5%~D
<37> SATA_ACT#
2
1
LFRAME#/FWH[4]
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
IGNNE#
INIT3_3V#
INIT#
INTR
RCIN#
NMI
SMI#
STPCLK#
THRMTRIP#
DA[0]
DA[1]
DA[2]
SATALED#
SATA[0]RXN
SATA[0]RXP
SATA[0]TXN
SATA[0]TXP
SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP
DCS1#
DCS3#
SATA
ICH_AC_BITCLK_TERM 1
R473
10_0402_5%~D
@
1
33_0402_5%~D
1
33_0402_5%~D
LDRQ[0]#
LDRQ[1]#/GPI[41]
AC-97/AZALIA
<27> ICH_SYNC_MDC
C
C10
B9
INTRUDER#
INTVRMEN
LAN
D12
B12
D11
F13
RTCRST#
LAD[0]/FWH[0]
LAD[1]/FWH[1]
LAD[2]/FWH[2]
LAD[3]/FWH[3]
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#
DD[0]
DD[1]
DD[2]
DD[3]
DD[4]
DD[5]
DD[6]
DD[7]
DD[8]
DD[9]
DD[10]
DD[11]
DD[12]
DD[13]
DD[14]
DD[15]
DDREQ
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
N6
P4
LPC_LDRQ0#
LPC_LDRQ1#
P3
LPC_LFRAME#
AF22
AF23
SIO_A20GATE
A20M#
R170
2
1 0_0402_5%~D
AE27
CPUSLP#
R423
2
1
0_0402_5%~D
H_CPUSLP#
AE24
AD27
DPRSLP#
DPSLP#
R169
R425
2
2
1 @ 0_0402_5%~D
1 0_0402_5%~D
H_DPRSLP#
H_DPSLP#
AF24
FERR#
R168
2
1 56_0402_5%~D
AG25
H_PWRGOOD
AG26
AE22
AF27
AG24
IGNNE#
R158
2
1 0_0402_5%~D
H_IGNNE#
ICH4_INIT#
INTR
R419
R159
2
2
1 0_0402_5%~D
1 0_0402_5%~D
H_INIT#
H_INTR
AD23
SIO_RCIN#
AF25
AG27
NMI
SMI#
R167
R166
2
2
1 0_0402_5%~D
1 0_0402_5%~D
H_NMI
H_SMI#
AE26
STPCLK#
R420
2
1 0_0402_5%~D
H_STPCLK#
AE23
THRMTRIP_ICH#
AC16
AB17
AC17
IDE_DA0
IDE_DA1
IDE_DA2
AD16
AE17
IDE_DCS1#
IDE_DCS3#
AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13
IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
AB14
IDE_DDREQ
H_FERR#
Note : R169 Do not populate for
Dothan-A, Populte for Dothan-B.
LPC_LFRAME# <34>
R164 1
SATA_TXP0_C
C476
SIO_A20GATE <35>
H_A20M#
<7>
H_A20M#
2 75_0402_5%~D
IDE_DA0
IDE_DA1
IDE_DA2
<24>
<24>
<24>
IDE_DCS1#
IDE_DCS3#
<24>
<24>
IDE_DD[0..15]
H_CPUSLP#
<7,10>
H_DPRSLP#
H_DPSLP#
<7>
<7>
H_FERR#
<7>
H_PWRGOOD
<7>
H_IGNNE#
<7>
H_INIT#
H_INTR
<7>
<7>
SIO_RCIN#
<34>
H_NMI
H_SMI#
<7>
<7>
H_STPCLK#
<7>
Note : R423 must be stuff for
Dothan-A, no-stuff for Dothan-B.
Note : R168 populate 56 ohm for
Dothan-A, Populte zero ohm for
Dothan-B.
C
+VCCP
<24>
B
RDDREQ
1
2
R435
0_0402_5%~D
1
2
SATA_TXN0
0.01U_0402_16V7K~D
SATA_TXN0
<24>
1
2
SATA_TXP0
0.01U_0402_16V7K~D
SATA_TXP0
<24>
C467
H_DPRSLP#
D
R161
@ 56_0402_5%~D
2
1
LPC_LDRQ0# <34>
LPC_LDRQ1# <34>
ICH6_BGA609~D
SATA_TXN0_C
R160
56_0402_5%~D
2
1
<34>
P2
N3
N5
N4
C506
33P_0402_50V8J~D
AA2
INTRUDER#
RTCX1
RTCX2
LPC
1
R182
100K_0402_5%~D
ICH_RTCRST#
LPC_LAD[0..3]
CPU
Y1
Y2
1
2
R184
180K_0402_5%~D
+RTC_CELL
<15> INTRUDER#
1
U16A
RTC
+RTC_CELL
1
+VCCP
32.768KHZ_12.5P_MC-306~D
C203
12P_0603_50V8J~D
ICH_RTCX2
2
1
IDE
2
Package
9.6X4.06 mm
D
2
ICH_RTCX1
X3
2
3
RDDREQ
<24>
2
1
Near ICH6 side.
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
ICH6(2/4)
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
21
of
50
5
4
3
2
1
R448
10K_0402_5%~D
2
1
PAD~D
W3
SYS_RESET#
U2
PM_BMBUSY#
<10> PM_BMBUSY#
R1631
+3VRUN
<34> SIO_EXT_SMI#
AD19
2 10K_0402_5%~D
SIO_EXT_SMI#
AE19
R1
USB2P0_SMI#
R91
0_0402_5%~D
SIO_EXT_WAK#
1
2 GPI12
<34> SIO_EXT_WAK#
SIO_EXT_SCI#
<34> SIO_EXT_SCI#
<6> H_STP_PCI#
W6
M2
R6
H_STP_PCI#
AC21
H_STP_CPU#
AD22
AB21
<6,46> H_STP_CPU#
SMBCLK
SMBDATA
LINKALERT#
SMLINK[0]
SMLINK[1]
MCH_SYNC#
SPKR
SUS_STAT#/LPCPD#
SYS_RESET#
GPI[7]
GPI[8]
SMBALERT#/GPI[11]
GPI[12]
GPI[13]
STP_PCI#/GPO[18]
GPO[19]
STP_CPU#/GPO[20]
P5
R3
T3
AF19
AF20
AC18
CLKRUN#
<29,31,33,34> CLKRUN#
U5
<18,34> ICH_PCIE_WAKE#
<31,34> IRQ_SERIRQ
<34> SIO_THRM#
<10,39,46> IMVP_PWRGD
+3VRUN
<34> SIO_SLP_S5#
<39> ICH_PWRGD
<46> DPRSLPVR
<34> SIO_PWRBTN#
<20,24,37> PLTRST#
<15,39> SUSPWROK
CK_14M_ICH
CK_48M_ICH
<6> CK_48M_ICH
2
1
2
R474
10_0402_5%~D
1
CK_48M_ICH_TERM
@
2
1
R432
10K_0402_5%~D
2
LINKALERT#
+3VSUS
1
+3VSUS
R445
10K_0402_5%~D
1
2
SYS_RESET#
+3VSUS
R440
10K_0402_5%~D
1
2
USB2P0_SMI#
+3VSUS
R442
10K_0402_5%~D
1
2
+3VSUS
R443
680_0402_5%~D
1
2
@
C567
4.7P_0402_50V8C~D
May need pulldown for DPRSLPVR in case
the ICH6m does not set this value in time
for boot.
@
10_0402_5%~D
2
@
4.7P_0402_50V8C~D
R471
DPRSLPVR
KAPALUA system can't boot issue
1
@
CK_14M_ICH_TERM
1K_0402_5%~D
2
+3VRUN
@
AC20
IMVP_PWRGD
AF21
E10
CK_48M_ICH
A27
ICH_SUSCLK
V6
SIO_SLP_S3#
SIO_SLP_S5#
T28
T4
T5
T6
PAD~D
ICH_PWRGD
AA1
DPRSLPVR
AE20
ICH_BATLOW#
V2
SIO_PWRBTN#
U1
PLTRST#
V5
SUSPWROK
Y3
2
1
R197
10K_0402_5%~D
2
<34> SIO_SLP_S3#
<6> CK_14M_ICH
SIO_THRM#
R198
10K_0402_5%~D
2
1
T27
PAD~D
R173
10K_0402_5%~D
CLKRUN#
AB20
CK_14M_ICH
1
(PCI Express Wake Event)
IRQ_SERIRQ
GPO[21]
GPO[23]
GPIO[24]
GPIO[25]
GPIO[27]
GPIO[28]
CLKRUN#/GPIO[32]
GPIO[33]
GPIO[34]
WAKE#
DMI[0]RXN
DMI[0]RXP
DMI[0]TXN
DMI[0]TXP
DMI[1]RXN
DMI[1]RXP
DMI[1]TXN
DMI[1]TXP
DMI[2]RXN
DMI[2]RXP
DMI[2]TXN
DMI[2]TXP
DMI[3]RXN
DMI[3]RXP
DMI[3]TXN
DMI[3]TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
THRM#
OC[0]#
OC[1]#
OC[2]#
OC[3]#
VRMPWRGD
CLK14
CLK48
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
DPRSLPVR/TP[1]
BATLOW#/TP[0]
PWRBTN#
LAN_RST#
USBP[0]N
USBP[0]P
USBP[1]N
USBP[1]P
USBP[2]N
USBP[2]P
USBP[3]N
USBP[3]P
USBP[4]N
USBP[4]P
USBP[5]N
USBP[5]P
USBP[6]N
USBP[6]P
USBP[7]N
USBP[7]P
USBRBIAS#
USBRBIAS
RSMRST#
H25
H24
G27
G26
PCIE_RXN1_C
PCIE_RXP1_C
PCIE_TXN1_C
PCIE_TXP1_C
R441
8.2K_0402_5%~D
2
PCIE_RXN1_C <37>
PCIE_RXP1_C <37>
D
K25
K24
J27
J26
M25
M24
L27
L26
PCIE_TXN1_C
C661
1
2
0.1U_0402_10V7K~D
PCIE_TXN1
PCIE_TXP1_C
C662
1
2
0.1U_0402_10V7K~D
PCIE_TXP1
T25
T24
R27
R26
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
V25
V24
U27
U26
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
Y25
Y24
W27
W26
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
AB24
AB23
AA27
AA26
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
AD25
AC25
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
<10>
<10>
<10>
<10>
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
<10>
<10>
<10>
<10>
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
<10>
<10>
<10>
<10>
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
<10>
<10>
<10>
<10>
<37>
PCIE_TXP1
<37>
CLK_PCIE_ICH#
CLK_PCIE_ICH
C
CLK_PCIE_ICH# <6>
CLK_PCIE_ICH <6>
F24
F23
DMI_IRCOMP
C23
D23
C25
C24
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
C27
B27
B26
C26
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
C21
D21
A20
B20
D19
C19
A18
B18
E17
D17
B16
A16
C15
D15
A14
B14
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
A22
B22
USBRBIAS
R467
1
24.9_0603_1%~D
2
+1.5VRUN
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
<28>
<28>
<28>
<28>
USB_OC0#
USB_OC1#
<28>
<28>
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
1
RN7
10K_1206_8P4R_5%~D
<28>
<28>
<28>
<28>
<28>
<28>
<31>
<31>
<28>
<28>
<28>
<28>
<28>
<28>
<28>
<28>
USB_OC0#
USB_OC3#
USB_OC1#
USB_OC2#
USB_OC6#
USB_OC7#
USB_OC4#
USB_OC5#
4
3
2
1
5
6
7
8
+3VSUS
RN8
10K_1206_8P4R_5%~D
4
5
3
6
2
7
1
8
B
2
R479
22.6_0603_1%~D
SIO_THRM#
+3VRUN
R171
10K_0402_5%~D
1
2
MCH_SYNC#
+3VRUN
1
R434
10K_0402_5%~D
2
IRQ_SERIRQ
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
PCIE_TXN1
P24
P23
N27
N26
ICH6_BGA609~D
1
ICH_PCIE_WAKE#
PERn[4]
PERp[4]
PETn[4]
PETp[4]
OC[4]#/GPI[9]
OC[5]#/GPI[10]
OC[6]#/GPI[14]
OC[7]#/GPI[15]
SERIRQ
+3VRUN
ICH_BATLOW#
PERn[3]
PERp[3]
PETn[3]
PETp[3]
DMI_IRCOMP
USB
V3
CLOCK
AD20
AD21
POWER MGT
LCD_BIST_EN
R549
0_0402_5%~D
1
2
R90
@ 0_0402_5%~D
SIO_EXT_WAK# 1
2 GPIO24
1
2
@ 10K_0402_5%~D
+3VSUS
PERn[2]
PERp[2]
PETn[2]
PETp[2]
BM_BUSY#/GPI[6]
R172
<20,37> PLTRST_DELAY#
PERn[1]
PERp[1]
PETn[1]
PETp[1]
SATA[0]GP/GPI[26]
SATA[1]GP/GPI[29]
SATA[2]GP/GPI[30]
SATA[3]GP/GPI[31]
PCI-EXPRESS
R437
10K_0402_5%~D
2
1
<6> ICH_SMBDATA
<6> ICH_SMBCLK
Y4
W5
Y5
W4
U6
AG21
F8
RI#
DIRECT MEDIA INTERFACE
AF17
AE18
AF18
AG18
GPIO
R446
10K_0402_5%~D
2
1
R429
10K_0402_5%~D
2
1
R431
10K_0402_5%~D
2
1
T2
33_0402_5%~D
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
MCH_SYNC#
SPKR
T26
C558
A
2
<25> SPKR
ICH_SMBDATA
ICH_SMBCLK
ICH_SMLINK0
ICH_SMLINK1
R178
B
1
+3VSUS
+3VSUS
1
C
U16C
ICH_RI#
R174
R165
100K_0402_5%~D
2
1
D
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
+3VSUS
4
3
2
ICH6(3/4)
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
22
of
50
5
4
3
2
1
+1.5VRUN
C502
0.1U_0402_16V4Z~D
1
2
Near PIN F27(C968),
P27(C949), AB27(C950)
+1.5VRUN
C550
0.1U_0402_16V4Z~D
1
2
ICH_V5REF_RUN
Near PIN AG9
2
1
R162
10_0402_5%~D
ICH6_VCCPLL AC27
E26
+3VRUN
2
ICH_V5REF_SUS
R478
10_0402_5%~D
2
+1.5VRUN
C475
0.1U_0402_16V4Z~D
1
+5VALW
C557
0.1U_0402_16V4Z~D
B
AA7
AA8
AA9
AB8
AC8
AD8
AE8
AE9
AF9
AG9
1
Near PIN
E26, E27
2
+3VRUN
+3VRUN
1
+3VSUS
C501
0.1U_0402_16V4Z~D
1_0402_5%~D
A
A11
U4
V1
V7
W2
Y7
A17
B17
C17
F18
G17
G18
VCCSATAPLL
VCC3_3[22]
2
1
CORE
2
VCCSUS1_5[1]
VCC1_5[78]
VCC1_5[77]
VCC1_5[76]
VCC1_5[75]
VCC1_5[74]
VCC1_5[73]
VCC1_5[72]
VCC1_5[71]
VCC1_5[70]
VCC1_5[69]
VCC1_5[68]
VCC1_5[67]
PCI/IDE RBP
VCC2_5[4]
VCC2_5[2]
V5REF[2]
V5REF[1]
V5REF_SUS
VCCUSBPLL
VCCLAN3_3/VCCSUS3_3[1]
VCCSUS3_3[20]
VCCLAN3_3/VCCSUS3_3[2]
VCCLAN3_3/VCCSUS3_3[3]
VCCRTC
VCCLAN3_3/VCCSUS3_3[4]
VCCLAN1_5/VCCSUS1_5[2]
VCCSUS3_3[1]
VCCLAN1_5/VCCSUS1_5[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
V_CPU_IO[3]
VCCSUS3_3[4]
V_CPU_IO[2]
VCCSUS3_3[5]
V_CPU_IO[1]
VCCSUS3_3[6]
VCCSUS3_3[19]
VCCSUS3_3[7]
VCCSUS3_3[18]
VCCSUS3_3[8]
VCCSUS3_3[17]
VCCSUS3_3[9]
VCCSUS3_3[16]
VCCSUS3_3[10]
VCCSUS3_3[15]
VCCSUS3_3[11]
VCCSUS3_3[14]
VCCSUS3_3[12]
VCCSUS3_3[13]
+3VRUN
0.1U_0402_16V4Z~D
1
0.1U_0402_16V4Z~D
C471
0.1U_0402_16V4Z~D
C474
1
2
G19
G20
F20
E24
E23
E22
E21
E20
D27
D26
D25
D24
+1.5VSUS
1
2
2
1
C522
0.1U_0402_16V4Z~D
1
2
C536
0.1U_0402_16V4Z~D
1
2
1
C566
0.01U_0402_16V7K~D
1
2
Near PIN A25
Near PIN
A2-A6, D1-H1
U7
R7
1
2
C499
0.01U_0402_16V7K~D
1
2
Near PIN AA19
+1.5VSUS
Near PIN U7
+1.5VRUN
+2.5VRUN
G8
AB18
P7
AA18
A8
ICH_V5REF_RUN
F21
ICH_V5REF_SUS
A25
A24
1
2
+1.5VRUN
+3VSUS
AB3
+RTC_CELL
G11
G10
+1.5VRUN
AG23
AD26
AB22
G16
G15
F16
F15
E16
D16
C16
+VCCP
1
2
Near PIN AB18
Near PIN AG23
+3VSUS
C565
0.1U_0402_16V4Z~D
1
2
VSS[172]
VSS[171]
VSS[170]
VSS[169]
VSS[168]
VSS[167]
VSS[166]
VSS[165]
VSS[164]
VSS[163]
VSS[162]
VSS[161]
VSS[160]
VSS[159]
VSS[158]
VSS[157]
VSS[156]
VSS[155]
VSS[154]
VSS[153]
VSS[152]
VSS[151]
VSS[150]
VSS[149]
VSS[148]
VSS[147]
VSS[146]
VSS[145]
VSS[144]
VSS[143]
VSS[142]
VSS[141]
VSS[140]
VSS[139]
VSS[138]
VSS[137]
VSS[136]
VSS[135]
VSS[134]
VSS[133]
VSS[132]
VSS[131]
VSS[130]
VSS[129]
VSS[128]
VSS[127]
VSS[126]
VSS[125]
VSS[124]
VSS[123]
VSS[122]
VSS[121]
VSS[120]
VSS[119]
VSS[118]
VSS[117]
VSS[116]
VSS[115]
VSS[114]
VSS[113]
VSS[112]
VSS[111]
VSS[110]
VSS[109]
VSS[108]
VSS[107]
VSS[106]
VSS[105]
VSS[104]
VSS[103]
VSS[102]
VSS[101]
VSS[100]
VSS[99]
VSS[98]
VSS[97]
VSS[96]
VSS[95]
VSS[94]
VSS[93]
VSS[92]
VSS[91]
VSS[90]
VSS[89]
VSS[88]
VSS[87]
0.1U_0402_16V4Z~D
D
C
B
C554
0.1U_0402_16V4Z~D
1
2
C553
0.1U_0402_16V4Z~D
1
2
Near PIN A24
1
Near PIN AG10
2
1
1
2
2
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Near PIN
AC27
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
F4
F22
F19
F17
E25
E19
E18
E15
E14
D7
D22
D20
D18
D14
D13
D10
D1
C4
C22
C20
C18
C14
B25
B24
B23
B21
B19
B15
B13
AG7
AG3
AG22
AG20
AG17
AG14
AG12
AG1
AF7
AF3
AF26
AF12
AF10
AF1
AE7
AE6
AE25
AE21
AE2
AE12
AE11
AE10
AD6
AD24
AD2
AD18
AD15
AD10
AD1
AC6
AC3
AC26
AC24
AC23
AC22
AC12
AC10
AB9
AB7
AB2
AB19
AB10
AB1
AA4
AA16
AA13
AA11
A9
A7
A4
A26
A23
A21
A19
A15
A12
A1
+RTC_CELL
+3VRUN
C472
1
2
VSS[86]
VSS[85]
VSS[84]
VSS[83]
VSS[82]
VSS[81]
VSS[80]
VSS[79]
VSS[78]
VSS[77]
VSS[76]
VSS[75]
VSS[74]
VSS[73]
VSS[72]
VSS[71]
VSS[70]
VSS[69]
VSS[68]
VSS[67]
VSS[66]
VSS[65]
VSS[64]
VSS[63]
VSS[62]
VSS[61]
VSS[60]
VSS[59]
VSS[58]
VSS[57]
VSS[56]
VSS[55]
VSS[54]
VSS[53]
VSS[52]
VSS[51]
VSS[50]
VSS[49]
VSS[48]
VSS[47]
VSS[46]
VSS[45]
VSS[44]
VSS[43]
VSS[42]
VSS[41]
VSS[40]
VSS[39]
VSS[38]
VSS[37]
VSS[36]
VSS[35]
VSS[34]
VSS[33]
VSS[32]
VSS[31]
VSS[30]
VSS[29]
VSS[28]
VSS[27]
VSS[26]
VSS[25]
VSS[24]
VSS[23]
VSS[22]
VSS[21]
VSS[20]
VSS[19]
VSS[18]
VSS[17]
VSS[16]
VSS[15]
VSS[14]
VSS[13]
VSS[12]
VSS[11]
VSS[10]
VSS[9]
VSS[8]
VSS[7]
VSS[6]
VSS[5]
VSS[4]
VSS[3]
VSS[2]
VSS[1]
ICH6_BGA609~D
C552
0.1U_0402_16V4Z~D
1
2
C473 @
0.1U_0402_16V4Z~D
1
2
ICH6_BGA609~D
ICH6_VCCPLL
C491
0.01U_0402_16V7K~D
+1.5VRUN
2
1
A13
F14
G13
G14
VCCDMIPLL
VCC3_3[1]
2
Near PIN
AG13, AG16
Near PIN A17
L80
BLM11A601S_0603~D
1
2
R438
1
1
2
0.1U_0402_16V4Z~D
C569
2
C562
+3VSUS
0.1U_0402_16V4Z~D
Near PIN AE1
AE1
AG10
VCC1_5[56]
VCC1_5[57]
VCC1_5[58]
VCC1_5[59]
VCC1_5[60]
VCC1_5[61]
VCC1_5[62]
VCC1_5[63]
VCC1_5[64]
VCC1_5[65]
P1
M7
L7
L4
J7
H7
H1
E4
B1
A6
1
C521
0.1U_0402_16V4Z~D
1
2
+3VRUN
U16D
E27
Y6
Y27
Y26
Y23
W7
W25
W24
W23
W1
V4
V27
V26
V23
U25
U24
U23
U15
U13
T7
T27
T26
T23
T16
T15
T14
T13
T12
T1
R4
R25
R24
R23
R17
R16
R15
R14
R13
R12
R11
P22
P16
P15
P14
P13
P12
N7
N17
N16
N15
N14
N13
N12
N11
N1
M4
M27
M26
M23
M16
M15
M14
M13
M12
L25
L24
L23
L15
L13
K7
K27
K26
K23
K1
J4
J25
J24
J23
H27
H26
H23
G9
G7
G21
G12
G1
C492
0.1U_0402_16V4Z~D
2
C468
1
+5VSUS
+1.5VRUN
VCCSUS1_5[3]
VCCSUS1_5[2]
1
2
C511
0.1U_0402_16V4Z~D
C480
Note: Intel will update design guide.
1
0.1U_0402_16V4Z~D
Near PIN AG5
Replacing by this circuit?
0.1U_0402_16V4Z~D
2
VCC1_5[46]
VCC1_5[47]
VCC1_5[48]
VCC1_5[49]
VCC1_5[50]
VCC1_5[51]
VCC1_5[52]
VCC1_5[53]
VCC1_5[54]
VCC1_5[55]
SATA
AA6
AB4
AB5
AB6
AC4
AD4
AE4
AE5
AF5
AG5
+1.5VRUN
2
C487
0.1U_0402_16V4Z~D
1
AA10
AG19
AG16
AG13
AD17
AC15
AA17
AA15
AA14
AA12
0.1U_0402_16V4Z~D
C568
C549
0.1U_0402_16V4Z~D
C555
0.1U_0402_16V4Z~D
1
2
C524
1
2
C556
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
C538
1U_0603_10V4Z~D
VCC3_3[11]
VCC3_3[10]
VCC3_3[9]
VCC3_3[8]
VCC3_3[7]
VCC3_3[6]
VCC3_3[5]
VCC3_3[4]
VCC3_3[3]
VCC3_3[2]
C498
0.1U_0402_16V4Z~D
1
2
C546
2
1
ICH_V5REF_SUS
2
VCC3_3[21]
VCC3_3[20]
VCC3_3[19]
VCC3_3[18]
VCC3_3[17]
VCC3_3[16]
VCC3_3[15]
VCC3_3[14]
VCC3_3[13]
VCC3_3[12]
C494
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
C564
1
D17
@ RB751V_SOD323~D
1
R472
@ 10_0402_5%~D
C
C570
0.1U_0402_16V4Z~D
C548
0.1U_0402_16V4Z~D
1
2
C469
0.1U_0402_16V4Z~D
1
2
+3VSUS
2
+5VSUS
C561
0.1U_0402_16V4Z~D
F9
U17
U16
U14
U12
U11
T17
T11
P17
P11
M17
M11
L17
L16
L14
L12
L11
AA21
AA20
AA19
C551
0.1U_0402_16V4Z~D
1
2
PCIE
C574
1U_0603_10V4Z~D
IDE
ICH_V5REF_RUN
2
VCC1_5[98]
VCC1_5[97]
VCC1_5[96]
VCC1_5[95]
VCC1_5[94]
VCC1_5[93]
VCC1_5[92]
VCC1_5[91]
VCC1_5[90]
VCC1_5[89]
VCC1_5[88]
VCC1_5[87]
VCC1_5[86]
VCC1_5[85]
VCC1_5[84]
VCC1_5[83]
VCC1_5[82]
VCC1_5[81]
VCC1_5[80]
VCC1_5[79]
PCI
1
D19
RB751V_SOD323~D
@
1
R477
@ 1K_0402_5%~D
VCC1_5[1]
VCC1_5[2]
VCC1_5[3]
VCC1_5[4]
VCC1_5[5]
VCC1_5[6]
VCC1_5[7]
VCC1_5[8]
VCC1_5[9]
VCC1_5[10]
VCC1_5[11]
VCC1_5[12]
VCC1_5[13]
VCC1_5[14]
VCC1_5[15]
VCC1_5[16]
VCC1_5[17]
VCC1_5[18]
VCC1_5[19]
VCC1_5[20]
VCC1_5[21]
VCC1_5[22]
VCC1_5[23]
VCC1_5[24]
VCC1_5[25]
VCC1_5[26]
VCC1_5[27]
VCC1_5[28]
VCC1_5[29]
VCC1_5[30]
VCC1_5[31]
VCC1_5[32]
VCC1_5[33]
VCC1_5[34]
VCC1_5[35]
VCC1_5[36]
VCC1_5[37]
VCC1_5[38]
VCC1_5[39]
VCC1_5[40]
VCC1_5[41]
VCC1_5[42]
VCC1_5[43]
VCC1_5[44]
VCC1_5[45]
USB
1
AA22
AA23
AA24
AA25
AB25
AB26
AB27
F25
F26
F27
G22
G23
G24
G25
H21
H22
J21
J22
K21
K22
L21
L22
M21
M22
N21
N22
N23
N24
N25
P21
P25
P26
P27
R21
R22
T21
T22
U21
U22
V21
V22
W21
W22
Y21
Y22
USB CORE
1
2
2
+3VRUN
2
+5VRUN
1
2
0.1U_0402_16V4Z~D
2
D
2
0.1U_0402_16V4Z~D
C516
C514
+
C488
1
BLM21PG600SN1D_0805~D
0.1U_0402_16V4Z~D
C542
+1.5VRUN_L
220U_D2_4VM
2
C493
0.1U_0402_16V4Z~D
U16E
L82
1
+1.5VRUN
4
3
2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
ICH6(4/4)
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
23
of
50
E
2
@ 10K_0402_5%~D
2
1
R284
R281
2
VSS_SATA
R279
HDD Connector
33P_0402_50V8J~D
1
C592
2
1M_0402_5%~D
C593
33P_0402_50V8J~D
1
2
10K_0402_5%~D
1
T4
0
0
1
1
*
T3
0
1
0
1
Pin Name
20MHz
25MHz
30MHz
40MHz
Int. PU/PD
Settings
SATATEST0
33
PD
NC
SATATEST1
34
PU
NC
SATATEST2
35
PD
NC
SATATEST3
36
PD
1
SATATEST4
37
PD
NC
SATATEST5
38
PU
0
SATATEST6
39
PD
1
SATATEST7
40
PD
NC
CFG0
20
PD
NC
CFG1
19
PU
0
CFG2
18
PD
NC
U28
JHDD
R296 1
2
IDE_HDA2
IDE_HCS1#
R291
@ 10K_0402_5%~D
+5VHDD
1
2
1
FOX_HH99223-SA_REVERS~D
+3VRUN
2 10K_0402_5%~D
2
1
SATA_RXP0_C <21>
0.01U_0402_16V7K~D
2
Layout Notes:
Place close to 88SA8040
R275
2
VSS_SATA
12.1K_0603_1%~D
1
+3VRUN
+1.8VRUN
+1.8VRUN
1
2
1
2
1
2
1
2
1
2
C586
2
1
2
0.1U_0402_16V4Z~D
2
1
C595
2
1
0.1U_0402_16V4Z~D
88SA8040_TQFP64~D
2
1
C588
2
1
C309
1
+3VRUN
4.7U_0805_10V4Z~D
VSS_SATA
0.1U_0402_16V4Z~D
+3VRUN
L45
1
2
BLM31A260SPT_1206~D
+3VRUN_SATA
C587
1
SATA_RXN0_C <21>
0.1U_0402_16V4Z~D
2
1
C486
SATA_RXP0
XTLIN
XTLOUT
CD-ROM Connector
3
2 10K_0402_5%~D
2 10K_0402_5%~D
2
0.01U_0402_16V7K~D
C594
UART
25
30
8
42
57
1
1
SATA_RXN0
CNFG2
CNFG1
CNFG0
ATAIOSEL
22
23
26
4
44
9
41
56
24
29
2
2
2
2
0.1U_0402_16V4Z~D
UAO
UAI
VSS1
VSS2
GND_0
GND_1
GND_2
R485
R496
C482
@ 10K_0402_5%~D
@ 10K_0402_5%~D
@ 10K_0402_5%~D
10K_0402_5%~D
1
1
1
1
C295
45
43
Power
ISET
VDDIO_0
VDDIO_1
VDD_0
VDD_1
VDD_2
VAA1
VAA2
R489
R488
R487
R486
4.7U_0805_10V4Z~D
T40 PAD~D
T41 PAD~D
HIOCS16#
HINTRQ
HDMACK#
HIORDY
HDIOR#
HDIOW#
HDMARQ
HRESET#
HPDIAG#
1
Place near 88SA8040
<21>
<21>
+3VRUN
<20,22,37>
2.2U_0805_10V6K~D
52
53
54
55
58
59
60
16
46
XTLIN/OSC
XTLOUT
SATA_TXP0
SATA_TXN0
PLTRST#
C316
1000P_0402_50V7K~D
IDE_HIOCS16#
IDE_HINTRQ
IDE_HDMACK#
IDE_HIORDY
IDE_HDIOR#
IDE_HDIOW#
IDE_HDREQ
33_0402_5%~D
HDA0
HDA1
HDA2
HCS0#
HCS1#
RST#
T0
T1
T2
T3
T4
T5
T6
T7
CNFG2
CNFG1
CNFG0
ATAIOSEL
17
33
34
35
36
37
38
39
40
20
19
18
21
Pin No.
SATA_RXP0
SATA_RXN0
32
31
27
28
C305
R484
10K_0402_5%~D
IDE_HRESET#
50
51
49
48
47
TX_P
TX_M
RX_P
RX_M
C304
0.1U_0402_16V4Z~D
2
IDE_HDA0
IDE_HDA1
IDE_HDA2
IDE_HCS0#
IDE_HCS1#
SATA
HDD0
HDD1
HDD2
HDD3
HDD4
HDD5
HDD6
HDD7
HDD8
HDD9
HDD10
HDD11
HDD12
HDD13
HDD14
HDD15
C314
0.01U_0402_16V7K~D
R499 1
62
64
2
5
7
11
13
15
14
12
10
6
3
1
63
61
Config & Debug
2 470_0402_5%~D
IDE_HDD0
IDE_HDD1
IDE_HDD2
IDE_HDD3
IDE_HDD4
IDE_HDD5
IDE_HDD6
IDE_HDD7
IDE_HDD8
IDE_HDD9
IDE_HDD10
IDE_HDD11
IDE_HDD12
IDE_HDD13
IDE_HDD14
IDE_HDD15
Parallel ATA
R306 1
2
2
IDE_HDD8
IDE_HDD9
IDE_HDD10
IDE_HDD11
IDE_HDD12
IDE_HDD13
IDE_HDD14
IDE_HDD15
C322
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
4.7U_0805_10V4Z~D
C306
2
0.1U_0402_16V4Z~D
1
0.1U_0402_16V4Z~D
C307
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
R273
+5VHDD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
10K_0402_5%~D
R285
2
IDE_HDREQ
IDE_HDIOW#
IDE_HDIOR#
IDE_HIORDY
IDE_HDMACK#
IDE_HINTRQ
IDE_HDA1
IDE_HDA0
IDE_HCS0#
@ 510_0402_5%~D
1
+5VHDD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
1
IDE_HRESET#
IDE_HDD7
IDE_HDD6
IDE_HDD5
IDE_HDD4
IDE_HDD3
IDE_HDD2
IDE_HDD1
IDE_HDD0
H
PU / PD is internal pull-up or pull-down 100Kohm
@ 10K_0402_5%~D
1
@ 10K_0402_5%~D
R494
1
1
5.6K_0402_5%~D
CNFG2
CNFG1
CNFG0
R283
ATAIOSEL
R280
R278
2
IDE_HDREQ
2
R493
1
1
0_0402_5%~D
R317
R276
2
XTLOUT
2
25MHz_20P_1BX25000CK1A~D
1
1
2
XTLIN
10K_0402_5%~D
@ 10K_0402_5%~D
IDE_HINTRQ
2
IDE_HIORDY
G
Reference clock configuration
+3VRUN
@ 10K_0402_5%~D
1
1
@ 10K_0402_5%~D
R303
2
4.7K_0402_5%~D
+3VRUN
2
+3VRUN
X7
R298
2
SATA to PATA Bridge
+3VRUN
F
1
D
1
C
2
B
1
A
+3VRUN
3
R436
2
IDE_IRQ
1
8.2K_0402_5%~D
1
C350
2
R175
JMOD
47P_0402_50V8J~D
<34> IDE_RST_MOD
1
R520
100K_0402_5%~D
2
+5VMOD
<21>
<21>
<21>
<21>
<21>
<21>
IDE_DIOW#
IDE_DIORDY
IDE_IRQ
IDE_DA1
IDE_DA0
IDE_DCS1#
IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
IDE_DD1
IDE_DD0
CDROM_ACT#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
IDE_DIORDY
2
4.7K_0402_5%~D
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
R325
1
<21> IDE_DDACK#
RPDDACK#
2
22_0402_5%~D
RDDREQ
IDE_DIOR#
<21>
<21>
Layout Note: Place close to CD-ROM CONN.
+5VMOD
RPDDACK#
PDIAG# R523 1
2 100K_0402_5%~D
IDE_DA2
IDE_DCS3#
+5VMOD
<21>
<21>
2
1
2
IDE_DD[0..15]
<21>
IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
10U_0805_10V4M~D
2
1
C363
2
1
C365
Layout Note: W=80 mils
SUYIN_80095AR-050G1T~D
R524
C370
0.1U_0402_16V4Z~D
1
1U_0603_10V4Z~D
+5VMOD
C367
1
2
0.1U_0402_16V4Z~D
2
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
C368
4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
1000P_0402_50V7K~D
+5VMOD
SEC_CSEL
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
4
DELL CONFIDENTIAL/PROPRIETARY
1
470_0402_5%~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
SATA to PATA BRIDGE & CD-ROM CONN.
Size
Document Number
,
Date:
A
B
C
D
E
F
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Rev
0.2
LA-2171
G
12, 2004
Sheet
24
H
of
50
5
4
3
2
1
VDDA
1
1
Z2401
1
2
<34>
BEEP
2
1A
1Y
1B
7
SN74LVC2G86DCTR_SSOP8~D
Z2402 6
CBS_SPK
2A
U8B
2Y
2B
R115
10K_0402_5%~D
1
2
Z2403
3
C252
0.1U_0402_16V4Z~D
1
2
Z2404
PC_BEEP
2
SN74LVC2G86DCTR_SSOP8~D
R105
@ 8.2K_0402_5%~D
W=30 mil
+3VRUN
3
single gate TTL
2
5
<31>
2
D
C81
0.1U_0402_16V4Z~D
1
2
1
SPKR
8
<22>
1
U8A
P
2
8
1
P
2
G
1
4
2
2
1
2
ICH_SDOUT_AUDIO
C247
@ 10P_0402_50V8J~D
1
2
1
1
4
BLM31A260SPT_1206~D
G
ICH_SYNC_AUDIO
C248
@ 10P_0402_50V8J~D
1
2
TPS793333_BYPASS
5
L16
BLM11A121S_0603~D
4
ICH_RST_AUDIO#
C249
@ 10P_0402_50V8J~D
1
2
4
EN BYPASS
TPS793333DBVR_SOT23-5~D
C101
0.047U_0402_16V4Z~D
3
@
1
C96
0.1U_0402_16V4Z~D
AUDIO_AVDD_ON
<35> AUDIO_AVDD_ON
1
GND
C93
2.2U_0805_10V6K~D
2
5
OUT
C98
0.1U_0402_16V4Z~D
2
IN
C92
@ 0.1U_0402_16V4Z~D
1
C97
@1U_0603_10V4Z~D
2
C99
@ 0.01U_0402_16V7K~D
C115
@ 0.1U_0402_16V4Z~D
D
1
2
L25
VDDA=3.3V
U9
1
+3VRUN
2
VDDA
+5VSUS
C251
1000P_0402_50V7K~D
@
2
1
2
1
C541
2.2U_0805_10V6K~D
C544
0.1U_0402_16V4Z~D
C545
0.1U_0402_16V4Z~D
VDDA
2
1
<21> ICH_AC_BITCLK
2
2
C268
C267
@
1
@
1
2
R_ICH_AC_BITCLK
6
R_ICH_AC_SDIN0
8
2
1
C195
1U_0603_10V4Z~D
C194
0.1U_0402_16V4Z~D
C190
2.2U_0805_10V6K~D
1
820P_0603_50V7K~D
AFLT1
2
820P_0603_50V7K~D
AFLT2
2
0.1U_0402_16V4Z~D
VREFOUT
2
29
30
28
27
2
1
<26,27> SPK_SHUTDOWN#
<19,34> SPDIF_SHDN
CAP2
32
SPK_SHUTDOWN#
43
SPDIF_SHDN
25
38
STAC9751
AFLT1
AUX_L
AFLT2
AUX_R
VREFOUT
MIC1
VREF
44
SPDIF
48
CAP2
VIDEO_L
GPIO0/NC
VIDEO_R
GPIO1/NC
PHONE
CK_14M_CODEC
SPDIF
<26>
EAPD
EAPD
47
C
24
18
SPDIF
PC_BEEP
19
20
14
1
2
31
CNB_MICIN
21
22
R219
@ 33_0402_5%~D
1
2
ICH_AC_SDOUT_TERM
CK_14M_CODEC_TERM
NC/BPCFG
HP_OUT_L
22P for
Crystal Only
@
C246
1
2
2
XTL_24M-
22P_0402_50V8J~D
1
HP_COMM
2 C205
0.1U_0402_16V4Z~D
<26>
17
13
9750_PHONE
12
PC_BEEP
39
HP_OUT_L
40
HP_COMM
B
HP_OUT_L
<26>
C244
@ 22P_0402_50V8J~D
R214
@ 1K_0402_5%~D
1
2
1
2
R212
@ 1K_0402_5%~D
34
46
45
3
1
HP_OUT_R
<26>
2
R210
0_0402_5%~D
MONO_OUT
HP_OUT_R
41
37
AUD_MONO_OUT
35
AUD_LINE_OUT_L
<27>
NC/FLTOUT
TRACE>15 mil
CID1
CID0
LOUT_L
<26>
2
XTL_OUT
X5
24.576 MHz_20P_1BX24576CC1A~D
@
1
2
XTL_IN
1
XTL_24M-
LOUT_R
36
AUD_LINE_OUT_R
<26>
2
STAC9751TG_TQFP48~D
1
Pin45
CID0
0_0402_5%~D
14.318 MHz
OPEN
OPEN
GND
27 MHz
OPEN
1K
GND
48 MHz
1K
OPEN
GND
24.576 MHz
1K
1K
GND
A
C192
1000P_0402_50V7K~D
DELL CONFIDENTIAL/PROPRIETARY
R221
0_0402_5%~D
2
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
Pin3
XTL_OUT
1
<6> CK_14M_CODEC
R220
2
4
7
22P_0402_50V8J~D
A
AVSS1
AVSS2
XTL_24M+
26
42
C245
1
2
Pin46
CID1
CLOCK SOURCE
C193
1000P_0402_50V7K~D
PACKAGE : 8X4.5X1.5mm
@
DVSS1
DVSS2
2
1
NB_MICIN
16
NC/FLTIN
HP_OUT_R
1
2
C258
22P_0402_50V8J~D
@
2 C217
0.1U_0402_16V4Z~D
R215
10K_0402_5%~D
33
1
1
EAPD
2
R222
@47_0402_5%~D
C222
0.33U_0603_10V7K~D
1
2
15
1
ICH_SDOUT_AUDIO
SDATA_IN
MIC2
<19>
B
CD_L
23
BIT_CLK
CD_R
C197
1
C196
1
C198
1
@
AC97VREFI
2
LINE_IN_L
CD_GND
27P_0603_50V8J~D
@
1
RESET#
SYNC
SDATA_OUT
LINE_IN_R
R235
33_0402_5%~D
1
2
27P_0603_50V8J~D
C266
<21> ICH_AC_SDIN0
27P_0603_50V8J~D
<27> MDC_AC_BITCLK
11
10
5
<21> ICH_RST_AUDIO#
<21> ICH_SYNC_AUDIO
<21> ICH_SDOUT_AUDIO
R233
33_0402_5%~D
1
2
R234
33_0402_5%~D
1
2
DVDD1
DVDD2
U19
C
AVDD1
AVDD2
1
9
@
4
3
2
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AC97 CODEC
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
25
of
50
5
4
3
2
1
+5VRUN
1
+3VRUN
+3VRUN
R465
1.33K_0603_1%~D
SGND
PGND
SVss
1
2
1
C534
4.7U_0805_10V4Z~D
D
C517
2
L83
JMIC
R449
1
<25> NB_MICIN
L81
2
100_0402_5%~D
2
1
2
INT_SPK_L1
INT_SPK_L2
INT_SPK_R1
INT_SPK_R2
MAX4411ETP-T_TQFN20~D
EMICIN
1
2
6
3
BLM11A121S_0603~D
1
2
1
4
5
2
FOX_JA6333L-1ST-TR
1
@
1
1
1
D11
D10
D13
D12
DA204U_SOT323~D DA204U_SOT323~D DA204U_SOT323~D DA204U_SOT323~D
1
@
@
@
60mil single end
connection near JACK
3
2
3
2
3
2
3
2
Gain Setting
JCOIN
COINCELL
COINCELL
TRACE>15 mil
+5VRUN
C
1
2
R231
@ 10K_0402_5%~D
2
2
R218
10K_0402_5%~D
1
2
E&T_3801-02~D
1
1
1
100P_0402_50V8J~D
BLM11A121S_0603~D
20
NC-20
R464
2K_0402_5%
2
2
C458
FOX_JA6333L-1ST-TR
C533
100P_0402_50V8J~D
2
+5VRUN
1
5
1
C204
1U_0603_10V4Z~D
17
5
2
2
C1N
7
3
C221
1U_0603_10V4Z~D
1
2
16
NC-16
PVss
C1P
2
12
AUD_GAIN0
AUD_GAIN1
1
Place close to connector
JSPK
INT_SPK_R1
INT_SPK_R2
INT_SPK_L1
INT_SPK_L2
R236
10K_0402_5%~D
2
R223
@ 10K_0402_5%~D
16
15
6
2
C264
2
7
RIN+
GAIN0
0.01U_0402_16V7K~D
GAIN1
C260
2
1
<25> AUD_LINE_OUT_R
17
RIN-
0.01U_0402_16V7K~D
ROUT+
C271
1
2
9
ROUT-
5
LIN-
0.01U_0402_16V7K~D
+3VRUN
2
LOUT+
C563
2
1
LOUT-
1
NC
2
2
2
B
AUD_GAIN0
3
AUD_GAIN1
18
INT_SPK_R1
14
INT_SPK_R2
4
INT_SPK_L1
8
INT_SPK_L2
Added new
Amplifier, same as
Nimitz
GAIN0
GAIN1
AV(inv)
INPUT
IMPEDANCE
S
Q43
2N7002_SOT23~D
2
G
1
<34>
S
NB_MUTE
Q41
2N7002_SOT23~D
BYPASS
D
2
G
S
12
10
BYPASS
0
0
6dB
90K ohm
0
1
10dB
70K ohm
1
0
15.6dB
45K ohm
1
1
21.6dB
25K ohm
SHUTDOWN
20
13
11
1
HP_NB_SENSE
2
G
D
3
1
D
3
1
2
1
GND1
GND2
GND3
GND4
19
3
2
2
R447
100K_0402_5%~D
EAPD
2
C572
0.1U_0402_16V4Z~D
@
1
LIN+
0.01U_0402_16V7K~D
<25> AUD_LINE_OUT_L
1
C272
0.1U_0402_16V4Z~D
@
1
VDD
PVDD1
PVDD2
U21
1
C269
10U_0805_10V4M~D
@
1
0.1U_0402_16V4Z~D
1
C573
0.1U_0402_16V4Z~D
1
1
C633
0.1U_0402_16V4Z~D
1
2
@
E&T_3801-04
+5VRUN
BLM21AF121SN1D_0805~D
+5VAMPVCC
C632
0.1U_0402_16V4Z~D
2
INT_SPK_L2
INT_SPK_L1
INT_SPK_R2
INT_SPK_R1
4
3
2
1
C631
0.1U_0402_16V4Z~D
<25>
4
3
2
1
L84
1
W=40mils
<25,27> SPK_SHUTDOWN#
A
2
8
NC-8
NC-12
1
LINE OUT
1
C539
100P_0402_50V8J~D
INL
1
4
1 HP_SPK_L2
L77
BLM11A121S_0603~D
6
NC-6
13
HP_SPK_L1 2
C507
100P_0402_50V8J~D
10
INR
C216
1U_0603_10V4Z~D
9
4
NC-4
15
AUD_LINE_IN_L
2
OUTL
100P_0402_50V8J~D
1
<25> HP_OUT_L
SHDNL#
11
1
2
6
3
C500
C223
1U_0603_10V4Z~D
AUD_LINE_IN_R
1
2
OUTR
L79
BLM11A121S_0603~D
HP_SPK_R1 2
1 HP_SPK_R2
100P_0402_50V8J~D
18
<25> HP_OUT_R
19
SHDNR#
JAUDO
<34> HP_NB_SENSE
SVDD
14
PVDD
2
U18
C630
B
2
HP_NB_SENSE
1
C
C229
1U_0603_10V4Z~D
R216
10K_0402_5%~D
2
D
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1
1
TPA6017A2PWPR_TSSOP20~D
2
*
1
C276
0.47U_0603_16V7K~D
2
A
C283
@ 0.1U_0402_16V4Z~D
DELL CONFIDENTIAL/PROPRIETARY
Q45
2N7002_SOT23~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
Amplifier and Phone Jack
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
26
of
50
3
1
2
3
4
5
6
7
8
9
10
COEX3
USBP2_DUSBP2_D+
USBP2_DUSBP2_D+
Place near BT
R202
1
<21> ICH_AC_SDIN1
12
<21> ICH_SYNC_MDC
2
33_0402_5%~D
MDC_SDIN
<21> ICH_RST_MDC#
GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK
2
4
6
8
10
12
MDC_AC_BITCLK <25>
E&T_3702-10-1~D
13
14
15
16
17
18
19
20
<28>
<28>
13
14
15
16
17
18
19
20
T17
PAD~D
JMDC
1
3
5
7
9
11
<21> ICH_SDOUT_MDC
TYCO_1-179397-2~D
1
2
1
C201
@ 10P_0402_50V8J~D
HW_RADIO_DIS#
<33,35> HW_RADIO_DIS#
COEX1_BT_ACTIVE
<33> COEX1_BT_ACTIVE
R345
10K_0402_5%~D
2
1
D
11
C219
0.1U_0402_16V4Z~D
<37> BT_ACTIVE
COEX2_WLAN_ACTIVE
<33> COEX2_WLAN_ACTIVE
2
Connector for MDC Rev1.5
2
1
2
1
+3VSUS
W=20 mil
ICH_AC_SDOUT_MDCTERM
ICH_RST_MDC#
C280
@ 10P_0402_50V8J~D
1
2
JBT
2
C281
@ 10P_0402_50V8J~D
1
2
1
ICH_SYNC_MDC
0.1U_0402_16V4Z~D
ICH_SDOUT_MDC
MDC_AC_BITCLK
R213
@ 10_0402_5%~D
C273
@ 10P_0402_50V8J~D
1
2
C235
@ 10P_0402_50V8J~D
ICH_SDOUT_MDC
1
R205
@ 10_0402_5%~D
C379
1
2
2
MDC_AC_BITCLK_TERM
4
+3VRUN
C224
4.7U_0805_10V4Z~D
5
D
2
1
+3VRUN
JWOFR
1
2
C635
1000P_0402_50V7K~D
1
2
+
2
5
P
G
3
1
2
1
D
S
1
2
5
C629
1
2
1
0.22U_0603_10V7K~D
2
SUB_GAIN0
3
SUB_GAIN1
4
C626
1
2
7
R539
2
C623
11
OUT1A
OUT1B
IN1+
2
18
OUT2A
OUT2B
1
PGND2
PGND1
SGND
L64
D6
2
1
1
SUB_OUT1
2
NC1
NC2
NC3
NC4
NC5
NC6
NC7
1U_0805_25V4Z~D
B130-13_SMA~D
BLM21PG600SN1D_0805~D
MODE
1
VCLAMP
C624
VREF
BYPASS
OUTP
OUTP
ROSC
PVCC
BSP
AGND
17
MODE
5
1
15
2
2
1U_0805_25V4Z~D
16
1
1
B130-13_SMA~D
R531
17
L65
D7
14
1
2
C378
1000P_0402_50V7K~D
SUB_OUT2_P
12
13
SUB_OUT1_N
SVRR
@ TDA1517ATW_HTSSOP20~D
BLM21PG600SN1D_0805~D
B
+15V
@
51_0603_1%~D 0.22U_1206_25V7M~D
TPA3001D1PWP_TSSOP24~D
2
1
1
8
P
R541
1
1
2
3
1
1
@ DTC144EKA_SOT23~D
3
2
3
2
A
R346
SUBOUT1
1
R536
@ 100K_0402_5%~D
2
SUB_OUT1
+15V
DELL CONFIDENTIAL/PROPRIETARY
2
0_0805_5%~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
2
@ 1K_0402_5%~D
@ SN74LVC3G14DCTR_SSOP8~D
2
D9
DA204U_SOT323~D
@
@
C380
@ 1000P_0402_50V7K~D
2
2
2
Q51
A
R538
@ 100K_0402_5%~D
U10C
1
SUBOUT2
SUB_GAIN0
1
5
C381
@ 1000P_0402_50V7K~D
D8
DA204U_SOT323~D
SUB_GAIN1
G
0_0805_5%~D
1
2
2
SUBOUT1
4
1
1
2
R535
100K_0402_5%~D
SUB_OUT2
Y
C645
R537
100K_0402_5%~D
2
A
@
1U_0805_25V4Z~D
1
3
R514
SUB_SHUTDOWN#
R349
MODE
@
15K_0402_5%
Gain Setting
SUBOUT2
SUBOUT1
2 SUB_OUT2
+15V
1
SUBOUT2
2
1
2
6
7
14
19
20
+3VRUN
SUB_VREF
1
11
10
4
C622
1
2
2
R12
@ 0_0805_5%~D
1
2
R79
@ 0_0805_5%~D
1
AGND
COSC
PGND
20
1
8
9
IN2-
51_0603_1%~D 0.22U_1206_25V7M~D
2
10
2
VP1
VP2
@ 0.47U_0603_16V7K~D
9
1
19
1
R534
120K_0402_5%~D
2
+
R521
2
C627
220P_0402_50V7K~D
1
1
4.7K_0402_5%~D
2
C628
1U_0805_25V4Z~D
21
1
2
3
C377
1000P_0402_50V7K~D
PGND
23
1
C636
1U_0805_25V4Z~D
1
<25> AUD_MONO_OUT
C621
1
2
2
+
U31
GAIN1
18
1U_0805_25V4Z~D
2
1
1
2
22
B
OUTN
8
GAIN0
13
SUB_VREF
OUTN
INP
PGND
2
1.21K_0603_1%~D
BSN
PVCC
INN
6
1
0.056U_0603_10V7K~D
R532
SHDN
2
C616
VCC
12
C637
1
2
<25> AUD_MONO_OUT
24
+
15
16
+15V
SUB_SHUTDOWN#
1
2N7002_SOT23~D
U33
C634
0.22U_0603_10V7K~D
1
2
+
Q12
2
G
<34> SUB_DETECT#
TC7SH08FU_SSOP5~D
C
1
C625
C
1
3
2
SUB_SHUTDOWN#
@ 0.1U_0603_25V7K~D
33K ohm
4
O
A
C619
36dB
R144
1
U11
10K_0402_5%~D
1
B
+15V
10K_0402_5%~D
104K ohm
2
+3VRUN
R155
168K ohm
23.6dB
150U_4B_16VM~D
18dB
0
C646
10U_1210_25V6K~D
1
1
<25,26> SPK_SHUTDOWN#
E&T_3801-04
C615
1U_0805_25V4Z~D
0
1
C617
@ 150U_4B_16VM~D
241K ohm
+15V
4
3
2
1
C353
@ 150U_4B_16VM~D
12dB
4
3
2
1
C354
@ 150U_4B_16VM~D
0
SUBOUT1
SUBOUT2
SUB_DETECT#
INPUT
IMPEDANCE
C372
@ 150U_4B_16VM~D
0
Amplifier gain(db)
1
GAIN1
2
GAIN0
4
3
2
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SUBWOOFER,BT PORT and MDC
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
27
of
50
L41
D
<22>
USBP1+
1
USBP1-
4
3
R361
0_0402_5%~D
1
2
R360
0_0402_5%~D
1
2
@
1
USBP0_D+
USBP0_D-
3
1
2
PLACE CHOKE
NEAR
CONNECTOR
L36
BLM21PG600SN1D_0805~D
1
2
USBP6_PWR
1
C277
47P_0402_50V8J~D
@
2
C265
47P_0402_50V8J~D
@
L39
BLM21PG600SN1D_0805~D
1
2
DLW21SN900SQ2_0805~D
2
2
USB PORT#
1
+
2
USBP2+
4
1
4
L38
<31> CBS_CAD15
1
<31> CBS_CAD13
4
C
L72
<22>
USBP4-
1
<22>
USBP4+
4
3
R341
0_0402_5%~D
1
2
R342
0_0402_5%~D
1
2
@
1
4
USBP2_DUSBP2_D+
3
1
2
2
C394
47P_0402_50V8J~D
@
DLW21SN900SQ2_0805~D
2
2
3
R237
0_0402_5%~D
1
2
R238
0_0402_5%~D
1
2
CBS_CAD15_L
CBS_CAD13_L
3
1
2
2
4
3
2
1
C275
47P_0402_50V8J~D
@
USBP4_PWR
CBS_CAD15_L <32>
CBS_CAD13_L <32>
L10
BLM21PG600SN1D_0805~D
1
2
USBP5_PWR
1
1
C14
47P_0402_50V8J~D
@
2
C13
47P_0402_50V8J~D
@
10
9
1
JST_SM8B-SRSS~D
2
USBP0_PWR
1
+
2
JUSB2
2
1
+
2
USBP4_VCC
USBP4_DUSBP4_D+
USBP4_GND
A1
A2
A3
A4
USBP5_VCC
USBP5_DUSBP5_D+
USBP5_GND
B1
B2
B3
B4
9
10
11
12
1
2
A_VCC
A_DA_D+
A_GND
L2
BLM21PG600SN1D_0805~D
1
2
B_VCC
B_DB_D+
B_GND
JUSB1 (Top)
JUSB1 (Bottom)
BlueTooth
NEW CARD
JUSB2 (Top)
JUSB2 (Bottom)
JUSB3 (Top)
JUSB3 (Bottom)
D
L1
BLM21PG600SN1D_0805~D
1
2
1
1
2
L12
BLM21PG600SN1D_0805~D
USBP4_D+
1
+
2
10
9
4
3
2
1
L9
BLM21PG600SN1D_0805~D
1
2
USBP4_D-
3
2
USBP7_VCC
USBP7_DUSBP7_D+
USBP7_GND
8
7
6
5
USBP2_D+ <27>
1
C274
47P_0402_50V8J~D
@
@ DLW21SN900SQ2_0805~D
2
2
3
R366
0_0402_5%~D
1
2
R365
0_0402_5%~D
1
2
8
7
6
5
1
2
L44
BLM21PG600SN1D_0805~D
USBP2_D- <27>
1
C395
47P_0402_50V8J~D
@
1
C576
0.1U_0402_16V4Z~D
@ DLW21SN900SQ2_0805~D
2
2
1
4
2
C286
47P_0402_50V8J~D
@
C15
0.1U_0402_16V4Z~D
1
2
1
C282
47P_0402_50V8J~D
@
C16
0.1U_0402_16V4Z~D
<22>
USBP2-
1
C21
150U _D2_6.3VM~D
L59
<22>
3
R245
0_0402_5%~D
1
2
R246
0_0402_5%~D
1
2
2
L42
BLM21PG600SN1D_0805~D
USBP7_PWR
C19
150U _D2_6.3VM~D
4
USBP1_D-
C278
150U _D2_6.3VM~D
1
<22>
JUSB3
USBP6_VCC
USBP6_DUSBP6_D+
USBP6_GND
USBP1_D+
3
0
1
2
3
4
5
6
7
1
2
DESTINATION
USBP1_PWR
1
+
2
C7
0.1U_0402_16V4Z~D
4
@ DLW21SN900SQ2_0805~D
2
2
1
2
1
2
L14
BLM21PG600SN1D_0805~D
G1
G2
G3
G4
FOX_UB11123-8Z4-HT~D
2
1
L7
BLM21PG600SN1D_0805~D
1
+
2
C87
0.1U_0402_16V4Z~D
4
1
1
C12
150U _D2_6.3VM~D
USBP0-
1
2
C88
150U _D2_6.3VM~D
<22>
USBP0+
3
C575
0.1U_0402_16V4Z~D
L69
<22>
4
C250
150U _D2_6.3VM~D
5
JUSB1
USBP0_VCC
USBP0_DUSBP0_D+
USBP0_GND
A1
A2
A3
A4
USBP1_VCC
USBP1_DUSBP1_D+
USBP1_GND
B1
B2
B3
B4
A_VCC
A_DA_D+
A_GND
C
B_VCC
B_DB_D+
B_GND
9
10
11
12
1
2
G1
G2
G3
G4
FOX_UB11123-8Z4-HT~D
2
L17
BLM21PG600SN1D_0805~D
+5VSUS
U20
L8
<22>
USBP5-
1
1
@ DLW21SN900SQ2_0805~D
2
2
USBP5_D<34> USB_BACK_EN#
<22>
USBP5+
4
B
4
L40
<22>
USBP6-
1
<22>
USBP6+
4
1
4
3
R10
0_0402_5%~D
1
2
R9
0_0402_5%~D
1
2
L43
<22>
USBP7-
1
USBP7+
4
1
4
@
2
1
C374
47P_0402_50V8J~D
@
2
OC1#
OUT1
OUT2
OC2#
8
7
6
5
USB_OC6#
USB_OC6#
USBP6_PWR
USBP7_PWR
USB_OC7#
USB_OC7#
<22>
C375
47P_0402_50V8J~D
@
C261
0.1U_0402_16V4Z~D
1
1
<22>
2
2
C259
10U_1206_16V4Z~D
B
USBP6_DUSBP6_D+
3
+5VSUS
U2
1
2
1
C262
47P_0402_50V8J~D
@
2
DLW21SN900SQ2_0805~D
2
2
3
R268
0_0402_5%~D
1
2
R269
0_0402_5%~D
1
2
GND
IN
EN1#
EN2#
TPS2062DR_SO8~D
1
C263
47P_0402_50V8J~D
@
<34> USB_SIDE_EN#
C47
0.1U_0402_16V4Z~D
<22>
1
2
3
4
USBP5_D+
3
@ DLW21SN900SQ2_0805~D
2
2
3
R243
0_0402_5%~D
1
2
R247
0_0402_5%~D
1
2
USB_BACK_EN#
USBP7_D-
1
1
2
2
USB_SIDE_EN#
1
2
3
4
GND
IN
EN1#
EN2#
OC1#
OUT1
OUT2
OC2#
8
7
6
5
USB_OC4#
8
7
6
5
USB_OC0#
USB_OC5#
USB_OC4#
USBP4_PWR
USBP5_PWR
USB_OC5#
<22>
USB_OC0#
USBP0_PWR
USB_OC1#
USBP1_PWR
<22>
<22>
TPS2062DR_SO8~D
C41
10U_1206_16V4Z~D
USBP7_D+
3
1
2
1
C388
47P_0402_50V8J~D
@
2
+5VSUS
C387
47P_0402_50V8J~D
@
U22
<34> USB_SIDE_EN#
C279
0.1U_0402_16V4Z~D
A
1
1
2
2
USB_SIDE_EN#
1
2
3
4
GND
IN
EN1#
EN2#
OC1#
OUT1
OUT2
OC2#
USB_OC1#
<22>
TPS2062DR_SO8~D
C285
10U_1206_16V4Z~D
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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USB 2.0 PORT
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
28
of
50
5
4
3
2
V_2P5_LAN
1
1
1
1
V_2P5_LAN
For 5705M only
3
P1
G2
A1
+3V_LOM_PCI
P10 LAN_EEDATA_SPROM_CS
M10 LAN_EECLK_SPROM_CLK
H12
K13
J13
LAN_EEPROM_W
V_3P3_LAN
H14
P7
C12
D12
B12
A12
D11
LAN_ACT#
LINK_10#
LINK_100#
<30>
<30>
LAN_ACT#
<30>
V_1P2_PLLVDD_PHY
1
2
1
LINK_10#
LINK_100#
2
G13
H13
G12
G14
+3V_LOM_PCI
R135
4.7K_0603_1%~D
LAN_TRST# 2
1
2
Note: Place these components
as closeto the chip as possible.
1
XTALO
XTALI
V_2P5_LAN
G11
E10
E11
H11
C25
27P_0402_50V8J
1
1
2
25MHz_20P_1BX25000CK1A~D
C26
27P_0402_50V8J
1
<22,31,33,34> CLKRUN#
BIASVDD
RDAC
A14
D10
LAN_BIAS
LAN_RDAC
A10
C9
R136
C114
1
2
for 4401 :1.27K
for 5705M:1.24K
@ 8.2P_0402_50V8J~D
L22
BLM11A601S_0603~D
1
2
R136
1.27K_0603_1%~D
2
1
VAUXPRSNT
M66EN
PME
2
1
C109
1000P_0402_50V7K~D
V_3P3_LAN
R77
0_0402_5%~D
1
2 5705M_CLOCKRUN
V_2P5_LAN
A11
F11
K12
L12
C8
H4
H10
J4
K4
J11
K11
L7
L8
VDDP_K14
VDDP_L13
VDDP_P11
AVDDL_F12
AVDDL_F13
AVDD_F14
AVDD_A13
VDDIO_A11
VDDIO_F11
VDDIO_K12
VDDIO_L12
Note: Place these components BCM4401KFB_FBGA196~D
as closeto the chip as possible.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
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CS
SK
DI
DO
VCC
NC
ORG
GND
L18
BLM11A601S_0603~D
1
2
AVDD1P2
AVDD2P5
1
R540 2
1
2
8
7
6
5
Z2702
1
V_1P2_LAN
2 L23
V_2P5_LAN
BLM11A601S_0603~D
@
R32
R34
1
1
2
2
2
1
@
R29
@ 0_0402_5%~D
1
2
5705M_LOWPWR
NC_LAN_N9
NC_LAN_P9
2
1
0_0402_5%~D
A
LAN_LOW_PWR <35>
0_0402_5%~D
0_0402_5%~D
LAN_SPROM_DOUT
LAN_SPROM_DIN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
Size
Date:
5
1
2
3
4
AT93C46-10SI-2.7_SO8~D
F12
F13
F14
A13
L11
L14
M8
M9
M11
N8
N9
P9
1
V_3P3_LAN
U3
LAN_EEDATA_SPROM_CS
LAN_EECLK_SPROM_CLK
LAN_SPROM_DOUT
LAN_SPROM_DIN
For 4401 only
NC_L11
NC_L14
NC_M8
NC_M9
LOW_POWER
NC_N8
NC_N9
NC_P9
2
R72
10K_0402_5%~D
2
1
B
R540
CSTSCHG
CLKRUN
NC_H10
NC_J4
NC_K4
NC_J11
NC_K11
NC_L7
NC_L8
1
2
3
4
A0
A1
NC
GND
@ AT24C256_SO8~D
C102
SO
SI
SCLK
CS
2
VDDIO-PCI_A7
VDDIO-PCI_B3
VDDIO-PCI_C5
VDDIO-PCI_E1
VDDIO-PCI_E4
VDDIO-PCI_G1
VDDIO-PCI_K3
VDDIO-PCI_L4
VDDIO-PCI_N6
VDDIO-PCI_P2
VCC
WP
SCL
SDA
C24
X1
2
K14
L13
P11
BCM4401
U6
8
7
6
5
LAN_EEPROM_W
LAN_EECLK_SPROM_CLK
LAN_EEDATA_SPROM_CS
0.01U_0402_16V7K~D
J14
N10
N11
R30
0_0402_5%~D
1
2
A7
B3
C5
E1
E4
G1
K3
L4
N6
P2
VSS_B7
VSS_D4
VSS_D5
VSS_D6
VSS_D7
VSS_D8
VSS_D9
VSS_E2
VSS_E5
VSS_E6
VSS_E7
VSS_E8
VSS_E9
VSS_F5
VSS_F6
VSS_F7
VSS_F8
VSS_F9
VSS_F10
VSS_G4
VSS_G5
VSS_G6
VSS_G7
VSS_G8
VSS_G9
VSS_G10
VSS_H9
VSS_K2
VSS_L6
VSS_L9
VSS_M6
VSS_M12
VSS_M13
VSS_N1
VSS_N12
VSS_N13
1
R33
10K_0402_5%~D
XTALVDD
XTALO
XTALI
INTA
PCI_RST
GNT
REQ
J12
F4
A6
+3VRUN
VDDC_E12
VDDC_H5
VDDC_H6
VDDC_H7
VDDC_H8
VDDC_J5
VDDC_J6
VDDC_J7
VDDC_J8
VDDC_J9
VDDC_J10
VDDC_K5
VDDC_K6
VDDC_K7
VDDC_K8
VDDC_K9
VDDC_K10
VDDC_L5
VDDC_L10
VDDC_M14
VDDC_N14
VDDC_P8
VDDC_P12
VDDC_P13
VDDC_P14
R69
@ 4.7K_0402_5%~D
2
1
V_2P5_LAN
B7
D4
D5
D6
D7
D8
D9
E2
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
F10
G4
G5
G6
G7
G8
G9
G10
H9
K2
L6
L9
M6
M12
M13
N1
N12
N13
0.1U_0402_16V4Z~D
@ 10_0402_5%~D
CLK_82540_TERM
V_3P3_LAN
E12
H5
H6
H7
H8
J5
J6
J7
J8
J9
J10
K5
K6
K7
K8
K9
K10
L5
L10
M14
N14
P8
P12
P13
P14
1U_0603_10V4Z~D
C86
1
B11
C11 LAN_CTRL_2P5V
C10
V_2P5_LAN
BCM4401KFB_FBGA196~D
R130
U5B
V_1P2_LAN
C58
TCK
TDI
TDO
TMS
TRST
SMB_CLK
SMB_DATA
2
V_2P5_LAN
LAN_CTRL_1P2V
2
1
PLLVDD2
NC
SYS_PME#
<31,33,34> SYS_PME#
@
10U_0805_10V4M~D
LAN_AUXPWR
R39
4.7K_0402_5%~D
2
1
V_1P2_LAN
@
LINKLEDB
SPD100LEDB
SPD1000LEDB
TRAFFICLEDB
IDSEL
FRAME
IRDY
TRDY
DEVSEL
STOP
PERR
SERR
PAR
PCI_CLK
H2
C2
J3
C3
C
@
C52
GPIO0
GPIO1
GPIO2
<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>
L26
R35
@ 1K_0402_5%~D
1
2
PCI_PIRQC#
PLTRST_LOM#
PCI_GNT4#
PCI_REQ4#
EEDATA
EECLK
LAN_TX3+
LAN_TX3LAN_TX2+
LAN_TX2LAN_TX1+
LAN_TX1LAN_TX0+
LAN_TX0-
0.1U_0402_16V4Z~D
BCM4401
VESD1
VESD2
VESD3
B9
B10
A9
LAN_TX3+
LAN_TX3LAN_TX2+
LAN_TX2LAN_TX1+
LAN_TX1LAN_TX0+
LAN_TX0-
R60
REGSUP25
REGCTL25
REGSEN25
E13
E14
D13
D14
C13
C14
B13
B14
1K_0402_5%~D
REGSUP12
REGCTL12
REGSEN12
CBE3
CBE2
CBE1
CBE0
A4
F2
F1
G3
H3
H1
J2
A2
J1
A3
1
V_3P3_LAN
TRD3+
TRD3TRD2+
TRD2TRD1+
TRD1TRD0+
TRD0-
L27
C4
F3
L3
M4
1
2
2
4
1
@
2
BLM11A601S_0603~D
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
1
2
0.1U_0402_16V4Z~D
1
2
C35
0.1U_0402_16V4Z~D
1
2
C34
0.1U_0402_16V4Z~D
1
2
C50
0.1U_0402_16V4Z~D
2
C32
0.1U_0402_16V4Z~D
1
C30
0.1U_0402_16V4Z~D
1
2
C91
0.1U_0402_16V4Z~D
1
2
C31
0.1U_0402_16V4Z~D
1
2
C43
0.1U_0402_16V4Z~D
1
2
C29
0.1U_0402_16V4Z~D
2
C105
0.1U_0402_16V4Z~D
1
C37
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
2
C68
0.1U_0402_16V4Z~D
1
@
C61
0.1U_0402_16V4Z~D
1
@
2
BLM11A601S_0603~D
<20,31> PCI_PIRQC#
<20> PLTRST_LOM#
<20> PCI_GNT4#
<20> PCI_REQ4#
CK_33M_LANPCI
@
2
C33
4.7U_0805_10V4Z~D
C60
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
R128
100_0402_5%~D
PCI_AD16
1
2 LAN_IDSEL
PCI_FRAME#
<20,31,33> PCI_FRAME#
PCI_IRDY#
<20,31,33> PCI_IRDY#
PCI_TRDY#
<20,31,33> PCI_TRDY#
PCI_DEVSEL#
<20,31,33> PCI_DEVSEL#
PCI_STOP#
<20,31,33> PCI_STOP#
PCI_PERR#
<20,31,33> PCI_PERR#
PCI_SERR#
<20,31,33> PCI_SERR#
PCI_PAR
<20,31,33> PCI_PAR
CK_33M_LANPCI
<6> CK_33M_LANPCI
A
1
2
C36
0.1U_0402_16V4Z~D
@
2
C22
10U_0805_10V4M~D
B8
A8
C7
C6
B6
B5
A5
B4
B2
B1
C1
D3
D2
D1
E3
K1
L2
L1
M3
M2
M1
N2
N3
P3
N4
P4
M5
N5
P5
P6
M7
N7
B
V_3P3_LAN
1
2
U5A
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
C
<20,31,33>
<20,31,33>
<20,31,33>
<20,31,33>
V_1P2_LAN
C46
0.1U_0402_16V4Z~D
@ BCP69_SOT223~D
1
<20,31,33> PCI_AD[0..31]
2
C48
10U_0805_10V4M~D
Q38
1
1
C27
10U_0805_10V4M~D
C45
1
1
2
0.1U_0402_16V4Z~D
C421
1
LAN_CTRL_2P5V
2
C411
10U_0805_10V4M~D
1
2
0.1U_0402_16V4Z~D
1
2
C73
0.1U_0402_16V4Z~D
1
2
C108
0.1U_0402_16V4Z~D
2
C63
0.1U_0402_16V4Z~D
1
C80
C71
1
2
1
D
2
+3V_LOM_PCI
0.1U_0402_16V4Z~D
C70
2
2.2U_0805_10V6K~D
1
2
BLM11A601S_0603~D
Q36
V_3P3_LAN
V_1P2_PLLVDD_PHY
1
1
@ BCP69_SOT223~D
L13
V_1P2_LAN
LAN_CTRL_1P2V
2
S
3
E
3
2
4
D
G
3
2
C
4
2
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
1
2
C82
0.1U_0402_16V4Z~D
1
2
C104
0.1U_0402_16V4Z~D
1
2
C56
0.1U_0402_16V4Z~D
Note: Place these components
as closeto the chip as possible.
2
C59
0.1U_0402_16V4Z~D
1
D
2
C103
0.1U_0402_16V4Z~D
2
C76
4.7U_0805_10V4Z~D
C113
SI3456DV-T1_TSOP6~D
<38> ENAB_3VLAN
B
1
2
C402
4.7U_0805_10V4Z~D
V_3P3_LAN
C404
L28
VAUX_LAN 1
2
BLM31A260SPT_1206~D
4
Q13
C55
10U_0805_10V4M~D
6
5
2
1
@
@
BCP69
C
2
+3VSRC
1
LAN Controller (BCM4401)
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
29
of
50
5
4
3
2
1
2
1
2
200_0402_5%~D
R52
V_2P5_LAN
R377
200_0402_5%~D
Layout Notice : Place
termination as close as
chip as possible
1
V_3P3_LAN
LAN_ACTLED_YEL#
JLOM
13
D
14
11
LAN_TX0+
12
LAN_TX0-
<29>
LAN_TX1+
10
4
6
<29>
LAN_TX1-
<29>
LAN_TX2+
5
3
1
<29>
LAN_TX2-
2
<29>
LAN_TX3+
8
7
<29>
9
LAN_TX3-
16
@
@
@
COMMON0
1CT:1CT
TRCT1
TRP1N
TRD1N
1CT:1CT
TRCT2
TRP2N
TRD2N
1CT:1CT
TRD3P
TRP3N
TRD3N
1CT:1CT
TRD4P
TRP4N
TRD4N
COMMON1
2
SHIELD0
SHIELD1
1
TYCO_1368398-1~D
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
V_3P3_LAN
2
LAN_ACTLED_YEL#
<29>
10K_0402_5%~D
R351
1
LINK_10#
0_0402_5%~D
R355
1
1
10K_0402_5%~D
1
R350
R353
B
2
2
2
V_3P3_LAN
10K_0402_5%~D
1
1000pF 2KV
Place these caps as close
to the center tap pins
of the mag/connector.
R352
LAN_ACT#
C
18
19
1
0.01U_0402_16V7K~D
2
0.01U_0402_16V7K~D
1
GREEN
ORANGE
C396
2
0.01U_0402_16V7K~D
1
C397
C398
0.01U_0402_16V7K~D
<29>
17
15
C399
1
49.9_0603_1%~D
C38
1
V_3P3_LAN
B
TRP4P
TRCT4
4 X 75 OHMS
LED_10_GRN#
LED_100_ORG#
0.1U_0402_16V4Z~D
2
R26
49.9_0603_1%~D
R25
49.9_0603_1%~D
C28
1
0.1U_0402_16V4Z~D
C39
1
2
R27
49.9_0603_1%~D
R28
49.9_0603_1%~D
@
2
TRP3P
TRCT3
@
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C40
1
R22
49.9_0603_1%~D
R21
49.9_0603_1%~D
R23
49.9_0603_1%~D
R24
@
TRP2P
TRD2P
C
2
TRP1P
TRD1P
20
21
<29>
D
20
21
<29>
YELLOW
2
LED_10_GRN#
<29>
LINK_100#
0_0402_5%~D
R354
1
2
LED_100_ORG#
0_0402_5%~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
Create PDF with GO2PDF for free, if you wish to remove this line, click here to buy Virtual PDF Printer
LAN Transfomer and RJ45
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
30
of
50
5
4
1
2
1
2
1
2
1
2
CK33M_CBS_TERM
2
6
7
2
1
CBS_CCD1#_INTERNAL
CBS_CCD2#_INTERNAL
CBS_CVS1
CBS_CVS1 <32>
CBS_CVS2
CBS_CVS2 <32>
W18
C19
N16
CBS_RSVD/D14
CBS_RSVD/D2
CBS_RSVD/A18
1
2
2
V13
W13
<32>
<32>
VCC5EN#
VCC3EN#
R13
T13
1
VPPEN0
VPPEN1
2
<32>
CBS_CCD2#
CBS_CCD1#
<32>
<32>
R7
1
CBS_CAUDIO
T14
D15
R16
H16
<32>
<32>
2
F19
2
CBS_CRST#
1
H19
V14
W14
USBP3+
USBP3-
Layout Note: Shield GND for
CBS_CCLK_INTERNAL and CBS_CCLK
CBS_CCLK
TPBIAS0
TPBIAS1
<32>
<32>
<32>
<32>
<32>
2
SD_CMD
SD_DATA0
SD_DATA1
SD_DATA2
SD_DATA3
D
R73
0_0402_5%~D
SD_CLK
<32>
VREF
REXT
USBDP
USBDM
VPPEN0
VPPEN1
VCC5EN#
VCC3EN#
C
REGEN#
R5C841_PBGA208~D
CBS_CAUDIO <32>
2
CBS_CRST# <32>
R217
0_0402_5%~D
+3VSUS
@
CBS_RSVD/D14 <32>
CBS_RSVD/D2 <32>
CBS_RSVD/A18 <32>
2
1
U34
3
4
SD_EN
@
2
1
2
VIN
VOUT
VIN/CE VOUT
1
5
+SD_VCC
GND
RT9701-CB_SOT23-5
1
2
For RICHO R5C841 Review Control
5
4
6
7
3
2
8
1
4
1
1
1
1
2
2
2
2
REV.
Date
0.1
12/18/03
J1394
3
2
TPA0+
TPA0TPB0+
TPB0-
1
4
3
2
1
5
6
SUYIN_020115FR004S502ZL~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Layout Note: Shield GND for
IEEE1394_TPA and TPB
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Size
Date:
5
<32>
1
TPBP1
TPBN1
SD_WP
CBS_CINT# <32>
@ 857CM-0009~D
R227
R232
R240
R242
5.1K_0603_1%~D
1
1
2
56.2_0603_1%~D
Z3008
R261
C284
1
270P_0402_50V7K~D
2
R244
R241
C657
2
CBS_CINT#
1
TPAP1
TPAN1
<32>
Layout Note: Shield GND for SD_CLK
<22>
<22>
L37
5
8
56.2_0603_1%~D
1U_0603_10V4Z~D
C171
1
4.7P_0402_50V8C~D
2
M18
CBS_CFRAME# <32>
CBS_CTRDY# <32>
CBS_CIRDY# <32>
CBS_CSTOP# <32>
CBS_CDEVSEL# <32>
CBS_CBLOCK# <32>
CBS_CPERR# <32>
CBS_CSERR# <32>
CBS_CREQ# <32>
CBS_CGNT# <32>
CBS_CSTSCHNG <32>
CBS_CCLKRUN# <32>
2
1
R230
47_0402_5%~D
C400
2
1
0.33U_0603_10V7K~D
1
C290
0.01U_0402_16V7K~D
IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0
C243
56.2_0603_1%~D
R239
R186
@
CBS_CFRAME#
CBS_CTRDY#
CBS_CIRDY#
CBS_CSTOP#
CBS_CDEVSEL#
CBS_CBLOCK#
CBS_CPERR#
CBS_CSERR#
CBS_CREQ#
CBS_CGNT#
CBS_CSTSCHNG
CBS_CCLKRUN#
CBS_CCLK_INTERNAL
Layout Note: Place close to 1394 CONN.
R229
100K_0402_5%~D
R196
10_0402_5%~D
A
K16
L16
K15
M16
L18
N19
N18
G16
G19
M15
E18
A18
L19
2
CBS_CPAR <32>
D13
B14
TPBP0
TPBN0
SD_EN
SD_DET#
B
CBS_GRST#
1
CBS_CPAR
<32>
<32>
<32>
<32>
R5C841_PBGA208~D
56.2_0603_1%~D
+3VSUS
N15
CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#
D12
D10
TPAP0
TPAN0
B1
A2
A3
B3
B4
A5
B5
D5
A6
B6
D6
E6
A7
B7
D7
E7
A8
B8
D8
E8
CBS_CRST#
IEEE1394_TPBIAS0
@
CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#
RI_OUT#/PME#
SPKROUT
HWSPND#
TEST
Layout Note: Place close to R5C841
CK_33M_CBPCI
F16
K18
P15
V19
IEEE1394_TPBIAS0
MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
R5C841
XI
XO
FIL0
R543
2 100K_0402_5%~D
RESERVED/CDATA14
RESERVED/CDATA2
RESERVED/CADR18
B11
A11
CPS
10K_0402_5%~D
R193 1
UDIO0/SERIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5
B13
A13
0.01U_0402_16V7K~D
+3VSUS
G4
F1
F2
F4
CBS_SPK
CCD1#/CD1#
CCD2#/CD2#
CVS1/VS1#
CVS2/VS2#
B12
A12
IEEE1394_TPBP0
IEEE1394_TPBN0
B10
A10
Layout Note: Shield GND
for USBP3+ and USBP3-
C236
<29,33,34> SYS_PME#
<25> CBS_SPK
<34> CB_HWSPND#
CAUDIO/BVD2(SPKR#/LED)
INTA#
INTB#
INTC#
IEEE1394_TPAP0
IEEE1394_TPAN0
270P_0402_50V7K~D
2 10K_0402_5%~D
B
CRST#/RESET
2
Layout Note: Place close to R5C841
and Shield GND for these signals
C218
R333 1
2 10K_0402_5%~D
2 10K_0402_5%~D
PCICLK
PCIRST#
GBRST#
CLKRUN#
1
Layout Note: Shield GND for
CBS_CAD13 and CBS_CAD15
270P_0402_50V7K~D
<22,34> IRQ_SERIRQ
R194 1
R190 1
+3VSUS
J4
H1
H2
H4
H5
G1
CINT#/RDY(IREQ#)
C234
A16
B16
A14
1
J2
K4
K2
<20,33> PCI_PIRQD#
<20,29> PCI_PIRQC#
<20,33> PCI_PIRQB#
REQ#
GNT#
U17B
D11
R5C841XI
R5C841XO
0.01U_0402_16V7K~D
2
10K_0402_5%~D
2
2 @ 10K_0402_5%~D
@ 0_0402_5%~D
2
PERR#
SERR#
+3V_PHY
R5C841XO
1
1
PCIRST_CB#
CBS_GRST#
K1
L4
G2
L5
CFRAME#/CADR23
CTRDY#/CADR22
CIRDY#/CADR15
CSTOP#/CADR20
CDEVSEL#/CADR21
RESERVED/CADR19
CPERR#/CADR14
CSERR#/WAIT#
CREQ#/INPACK#
CGNT#/WE#
CSTSCHG/BVD1(STSCHG#/RI#)
CCLKRUN#/WP(IOIS16#)
CCLK/CADR16
2
22P_0402_50V8J~D
R211
M4
M5
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
24.576MHz_16P_1BG24576CKIA~D
C256
0_0402_5%~D
PCI_REQ1#
PCI_GNT1#
CPAR/CADR13
Layout Note: Place close to R5C841
and Shield GND for SD_CLK
X4
100K_0402_5%~D
<6> CK_33M_CBPCI
<20,33> PCIRST_CB#
W5
T6
PAR
R5C841XI
1
R188
<20> PCI_REQ1#
<20> PCI_GNT1#
PCI_PERR#
PCI_SERR#
CC/BE3#/REG#
CC/BE2#/CADR12
CC/BE1#/CADR8
CC/BE0#/CE1#
2
22P_0402_50V8J~D
R195
100K_0402_5%~D
<20,29,33> PCI_PERR#
<20,29,33> PCI_SERR#
+3VSUS
1
C255
CBS_CAD31 <32>
CBS_CAD30 <32>
CBS_CAD29 <32>
CBS_CAD28 <32>
CBS_CAD27 <32>
CBS_CAD26 <32>
CBS_CAD25 <32>
CBS_CAD24 <32>
CBS_CAD23 <32>
CBS_CAD22 <32>
CBS_CAD21 <32>
CBS_CAD20 <32>
CBS_CAD19 <32>
CBS_CAD18 <32>
CBS_CAD17 <32>
CBS_CAD16 <32>
CBS_CAD15 <28>
CBS_CAD14 <32>
CBS_CAD13 <28>
CBS_CAD12 <32>
CBS_CAD11 <32>
CBS_CAD10 <32>
CBS_CAD9 <32>
CBS_CAD8 <32>
CBS_CAD7 <32>
CBS_CAD6 <32>
CBS_CAD5 <32>
CBS_CAD4 <32>
CBS_CAD3 <32>
CBS_CAD2 <32>
CBS_CAD1 <32>
CBS_CAD0 <32>
2
V6
C/BE3#
C/BE2#
C/BE1#
C/BE0#
B19
C18
D19
D18
E19
E16
F18
F15
G18
G15
H18
H15
J18
J16
J15
P16
P19
R19
P18
R18
T19
T18
U19
U18
W17
V17
W16
V16
W15
V15
T15
R14
R191
PCI_PAR
R5C841
CAD31/CDATA10
CAD30/CDATA9
CAD29/CDATA1
CAD28/CDATA8
CAD27/CDATA0
CAD26/CADR0
CAD25/CADR1
CAD24/CADR2
CAD23/CADR3
CAD22/CADR4
CAD21/CADR5
CAD20/CADR6
CAD19/CADR25
CAD18/CADR7
CAD17/CADR24
CAD16/CADR17
CAD15/IOWR#
CAD14/CADR9
CAD13/IORD#
CAD12/CADR11
CAD11/OE#
CAD10/CE2#
CAD9/CADR10
CAD8/CDATA15
CAD7/CDATA7
CAD6/CDATA13
CAD5/CDATA6
CAD4/CDATA12
CAD3/CDATA5
CAD2/CDATA11
CAD1/CDATA4
CAD0/CDATA3
10K_0603_1%~D
P2
W2
W6
T9
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C253
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_AD17
1
2
100_0402_5%~D
R192
+3VRUN
<22,29,33,34> CLKRUN#
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
PCI_FRAME#
V3
PCI_TRDY#
W4
PCI_IRDY#
V4
PCI_STOP#
V5
PCI_DEVSEL# T5
CBS_IDSEL
P1
<20,29,33>
<20,29,33>
<20,29,33>
<20,29,33>
<20,29,33>
R74 1
R185 1
R183 1
M2
M1
N5
N4
N2
N1
P5
P4
R4
R2
R1
T2
T1
U2
U1
V1
T7
V7
W7
R8
T8
V8
W8
R9
V9
W9
T11
V11
W11
T12
V12
W12
0.01U_0402_16V7K~D
PCI_C_BE3#
PCI_C_BE2#
PCI_C_BE1#
PCI_C_BE0#
<20,29,33> PCI_PAR
C
2
1
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
D
<20,29,33>
<20,29,33>
<20,29,33>
<20,29,33>
3
U17A
<20,29,33> PCI_AD[0..31]
4
3
2
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CardBus Controller(R5C841)
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
31
of
50
5
4
3
2
1
+3VSUS
1
2
1
2
D
VCC_RIN1
VCC_RIN2
L1
E14
VCC_ROUT1
VCC_ROUT2
E10
E11
A17
B17
AVCC_PHY1
AVCC_PHY2
AVCC_PHY3
AVCC_PHY4
Place close to JCBUS
AGND1
AGND2
AGND3
AGND4
AGND5
AGND6
C
2
1
C413
2
1
C412
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
2
10U_0805_10V4M~D
1
C410
J1
J5
K5
E9
R10
T10
V10
W10
L15
M19
CBS_VCC
CBS_VPP
0.01U_0402_16V7K~D
A9
B9
D9
D14
A15
B15
0.01U_0402_16V7K~D
2
2
1
1000P_0402_50V7K~D
2
1
2
1
VCC_MD3V
R6
E13
0.47U_0603_16V7K~D
1
C653
0.47U_0603_16V7K~D
C650
2
C652
0.01U_0402_16V7K~D
C651
0.01U_0402_16V7K~D
1
2
1
C656
1000P_0402_50V7K~D
C
2
+
C655
0.1U_0402_16V4Z~D
2
1
0.01U_0402_16V7K~D
2
1
C220
0.01U_0402_16V7K~D
1
C241
0.1U_0402_16V4Z~D
C164
10U_0805_10V4M~D
C227
2
1
2
VCC_PCI3V1
VCC_PCI3V2
VCC_PCI3V3
A4
+3V_PHY
R5C841
L2
C1
D1
E1
C2
D2
E2
E4
E12
C179
0.1U_0402_16V4Z~D
+3VSUS
1
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
C654
2
0.01U_0402_16V7K~D
C178
10U_0805_10V4M~D
C200
1
2
BLM21A601SPT_0805~D
VCC_3V1
VCC_3V2
VCC_3V3
VCC_3V4
+3VSUS
1
1
U17C
F5
G5
J19
K19
W3
R11
R12
2
1
2
+3V_PHY
L31
+3VSUS
C177
22U_D2_6.3VM~D
2
1
0.01U_0402_16V7K~D
2
2
C254
0.01U_0402_16V7K~D
1
2
1
C649
0.01U_0402_16V7K~D
2
0.01U_0402_16V7K~D
2
1
C228
0.01U_0402_16V7K~D
1
C225
0.01U_0402_16V7K~D
C240
2
C239
10U_0805_10V4M~D
1
1
C206
0.01U_0402_16V7K~D
2
+3VRUN
D
C202
10U_0805_10V4M~D
C176
1
R5C841_PBGA208~D
JCBUS
+3VSUS
U14
11
2
1
5
16
<31>
<31>
VPPEN0
VPPEN1
<31>
<31>
VCC3EN#
VCC5EN#
VCC5IN
VCC5IN
EN0
EN1
CBS_VPP
VPPOUT
1
2
FLG
GND
NC
NC
NC
1
2
8
VCC3_EN
VCC5_EN
CBS_CAD7
CBS_CC/BE0#
CBS_CAD9
CBS_CAD11
<31> CBS_CC/BE0#
7
6
10
0.1U_0402_16V4Z~D
2
3
4
9
14
12
C355
C156
1
VCCOUT
VCCOUT
VCCOUT
0.1U_0402_16V4Z~D
13
15
0.1U_0402_16V4Z~D
2
VCC3IN
+5VSUS
CBS_VCC
C351
C509
B
0.1U_0402_16V4Z~D
1
CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5
CBS_CAD12
CBS_CAD14
CBS_CC/BE1#
CBS_CPAR
<31> CBS_CC/BE1#
<31> CBS_CPAR
CBS_CPERR#
CBS_CGNT#
CBS_CINT#
<31> CBS_CPERR#
<31> CBS_CGNT#
<31> CBS_CINT#
CBS_VCC
CBS_VPP
<31> CBS_CCLK
<31> CBS_CIRDY#
<31> CBS_CC/BE2#
CBS_CCLK
CBS_CIRDY#
CBS_CC/BE2#
CBS_CAD18
CBS_CAD20
CBS_CAD21
CBS_CAD22
R5331V002-E2-FA_SSOP16~D
CBS_CAD23
CBS_CAD24
CBS_CAD25
CBS_CAD26
+SD_VCC
Layout Note: Place close to SD CONN.
JSD
1
2
3
4
5
6
7
8
9
<31> SD_DATA3
<31> SD_CMD
<31> SD_CLK
+SD_VCC
<31> SD_DATA0
<31> SD_DATA1
<31> SD_DATA2
A
11
12
<31> SD_WP
R78
+SD_VCC
33K_0402_5%~D
2
2
10
<31> SD_DET#
1
1
0.1U_0402_16V4Z~D
C648
2
C660
1U_0603_10V4Z~D
1
CD/DAT3
CMD
VSS1
VDD
CLK
VSS2
DAT0
DAT1
DAT2
GND1
GND2
GND3
GND4
13
14
15
16
CBS_CAD27
CBS_CAD29
CBS_RSVD/D2
CBS_CCLKRUN#
<31> CBS_RSVD/D2
<31> CBS_CCLKRUN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
A_CAD0
A_CAD1
A_CAD3
A_CAD5
GND0
A_CAD7
A_PCI_C/BE0#
A_CAD9
A_CAD11
GND1
A_CAD12
A_CAD14
A_PCI_C/BE1#
A_CPAR
GND2
A_CPERR#
A_CGNT#
A_CINT#
+AVCC0
GND3
+AVPP0
A_CCLK
A_CIRDY
A_PCI_C/BE2#
GND4
A_CAD18
A_CAD20
A_CAD21
A_CAD22
GND5
A_CAD23
A_CAD24
A_CAD25
A_CAD26
GND6
A_CAD27
A_CAD29
CB_A_D2
A_CCLKRUN#
GND7
GND15
A_CCD1#
A_CAD2
A_CAD4
A_CAD6
GND14
CB_A_D14
A_CAD8
A_CAD10
A_CVS1
GND13
A_CAD13
A_CAD15
A_CAD16
CB_A_A18
GND12
A_CBLOCK#
A_CSTOP#
A_CDEVSEL#
+AVCC1
GND11
+AVPP1
A_CTRDY#
A_CFRAME#
A_CAD17
GND10
A_CAD19
A_CVS2
A_CRST#
A_CSERR#
GND9
A_CREQ#
A_PCI_C/BE3#
A_CAUDIO
A_CSTSCHG
GND8
A_CAD28
A_CAD30
A_CAD31
A_CCD2#
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_RSVD/D14
CBS_CAD8
CBS_CAD10
CBS_CVS1
CBS_CAD13_L
CBS_CAD15_L
CBS_CAD16
CBS_RSVD/A18
CBS_CBLOCK#
CBS_CSTOP#
CBS_CDEVSEL#
CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17
CBS_CAD19
CBS_CVS2
CBS_CRST#
CBS_CSERR#
CBS_CREQ#
CBS_CC/BE3#
CBS_CAUDIO
CBS_CSTSCHNG
CBS_CAD28
CBS_CAD30
CBS_CAD31
CBS_CCD2#
CBS_CCD1# <31>
CBS_CVS1 <31>
CBS_CAD13_L <28>
CBS_CAD15_L <28>
CBS_RSVD/A18 <31>
CBS_CBLOCK# <31>
CBS_CSTOP# <31>
CBS_CDEVSEL# <31>
CBS_VCC
CBS_VPP
CBS_CTRDY# <31>
CBS_CFRAME# <31>
CBS_CVS2 <31>
CBS_CRST# <31>
CBS_CSERR# <31>
CBS_CREQ# <31>
CBS_CC/BE3# <31>
CBS_CAUDIO <31>
CBS_CSTSCHNG <31>
A
DETECT#
WP_VSS
WP
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
B
CBS_CCD2# <31>
Molex_SD-67840-0002~D
4
CBS_CAD31 <31>
CBS_CAD30 <31>
CBS_CAD29 <31>
CBS_CAD28 <31>
CBS_CAD27 <31>
CBS_CAD26 <31>
CBS_CAD25 <31>
CBS_CAD24 <31>
CBS_CAD23 <31>
CBS_CAD22 <31>
CBS_CAD21 <31>
CBS_CAD20 <31>
CBS_CAD19 <31>
CBS_CAD18 <31>
CBS_CAD17 <31>
CBS_CAD16 <31>
CBS_CAD14 <31>
CBS_CAD12 <31>
CBS_CAD11 <31>
CBS_CAD10 <31>
CBS_CAD9 <31>
CBS_CAD8 <31>
CBS_CAD7 <31>
CBS_CAD6 <31>
CBS_CAD5 <31>
CBS_CAD4 <31>
CBS_CAD3 <31>
CBS_CAD2 <31>
CBS_CAD1 <31>
CBS_CAD0 <31>
FOX_QT600806-7121_LT~D
Title
Size
Date:
5
CBS_CAD31
CBS_CAD30
CBS_CAD29
CBS_CAD28
CBS_CAD27
CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD19
CBS_CAD18
CBS_CAD17
CBS_CAD16
CBS_CAD14
CBS_CAD12
CBS_CAD11
CBS_CAD10
CBS_CAD9
CBS_CAD8
CBS_CAD7
CBS_CAD6
CBS_CAD5
CBS_CAD4
CBS_CAD3
CBS_CAD2
CBS_CAD1
CBS_CAD0
CBS_RSVD/D14 <31>
2
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CardBus/SD card Socket
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
32
of
50
5
4
3
2
1
+3VRUN
+3VRUN
JPCI
<27,35> HW_RADIO_DIS#
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
HW_RADIO_DIS#
PCI_PIRQD#
<20,31> PCI_PIRQD#
CK_33M_MINIPCI
<6> CK_33M_MINIPCI
PCI_REQ3#
<20> PCI_REQ3#
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
R181
0_0402_5%~D
<27> COEX2_WLAN_ACTIVE
<20,29,31> PCI_C_BE3#
1
2
PCI_C_BE3#
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
PCI_C_BE2#
PCI_IRDY#
<20,29,31> PCI_C_BE2#
<20,29,31> PCI_IRDY#
CLKRUN#
PCI_SERR#
<22,29,31,34> CLKRUN#
<20,29,31> PCI_SERR#
2
CK_33M_MINIPCI
PCI_PERR#
PCI_C_BE1#
PCI_AD14
<20,29,31> PCI_PERR#
<20,29,31> PCI_C_BE1#
R179
@10_0402_5%~D
C
1
PCI_AD12
PCI_AD10
CK_33M_MINPCI_TERM
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
+5VRUN
PCI_AD1
2
1
TIP
RING
2
2
C157
@4.7P_0402_50V8C~D
R139
+3VALW
2
1 10K_0402_5%~D
<34> DEBUG_ENABLE
8PMJ-3
8PMJ-6
8PMJ-7
8PMJ-8
LED1_GRNP
LED1_GRNN
CHSGND
INTB#
3.3V
RESERVED
GROUND
CLK
GROUND
REQ#
3.3V
AD31
AD29
GROUND
AD27
AD25
RESERVED
C/BE3#
AD23
GROUND
AD21
AD19
GROUND
AD17
C/BE2#
IRDY#
3.3V
CLKRUN#
SERR#
GROUND
PERR#
C/BE1#
AD14
GROUND
AD12
AD10
GROUND
AD8
AD7
3.3V
AD5
RESERVED
AD3
5V
AD1
GROUND
AC_SYNC
AC_SDATA_IN
AC_BIT_CLK
AC_CODEC_ID1#
MOD_AUDIO_MON
AUDIO_GND
SYS_AUDIO_OUT
SYS_AUDIO_OUT GND
AUDIO_GND
RESERVED
VCC5A
8PMJ-1
8PMJ-2
8PMJ-4
8PMJ-5
LED2_YELP
LED2_YELN
RESERVED
5V
INTA#
RESERVED
3.3VAUX
RST#
3.3V
GNT#
GROUND
PME#
RESERVED
AD30
3.3V
AD28
AD26
AD24
IDSEL
GROUND
AD22
AD20
PAR
AD18
AD16
GROUND
FRAME#
TRDY#
STOP#
3.3V
DEVSEL#
GROUND
AD15
AD13
AD11
GROUND
AD9
C/BE0#
3.3V
AD6
AD4
AD2
AD0
RESERVED
RESERVED
GROUND
M66EN
AC_SDATA_OUT
AC_CODEC_ID0#
AC_RESET#
RESERVED
GROUND
SYS_AUDIO_IN
SYS_AUDIO_IN GND
AUDIO_GND
MCPIACT#
3.3VAUX
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
LED_WLAN24
LED_WLAN5
R149
R148
INB
O
4 R138
2 200_0402_5%~D
1
LED_WLAN_OUT <37>
INA
TC7SH32FU_SSOP5~D
2 100K_0402_5%~D
2 100K_0402_5%~D
1
1
D
+5VRUN
PCI_PIRQB#
PCI_PIRQB#
<20,31>
PCIRST_CB#
<20,31>
PCI_GNT3#
<20>
V_3P3_LAN
PCIRST_CB#
PCI_GNT3#
R146
U12
P
1
LED_WLAN5
3
1
LED_WLAN24
G
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
D
+3VRUN
5
<20,29,31> PCI_AD[0..31]
2
SYS_PME#
SYS_PME# <29,31,34>
1
2 0_0402_5%~D
COEX1_BT_ACTIVE <27>
PCI_AD30
@ R147
10K_0402_5%~D
PCI_AD28
2
1
PCI_AD26
PCI_AD24
MINIDSEL
PCI_AD19
1
2
PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16
2
C135
0.1U_0402_16V4Z~D
1
C136
0.1U_0402_16V4Z~D
1
R145
100_0402_5%~D
PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_STOP#
<20,29,31>
PCI_FRAME# <20,29,31>
PCI_TRDY# <20,29,31>
PCI_STOP# <20,29,31>
PCI_DEVSEL#
PCI_DEVSEL# <20,29,31>
PCI_AD15
PCI_AD13
PCI_AD11
C
PCI_AD9
PCI_C_BE0#
PCI_C_BE0# <20,29,31>
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
DEBUG_OUT
DEBUG_OUT
<34>
R150
MPCIACT#
1
V_3P3_LAN
2
+3VSUS
10K_0402_5%~D
AMP_1318644-1~D
2
C137
0.1U_0402_16V4Z~D
1
B
B
+3VRUN
2
1
C158
0.047U_0402_16V4Z~D
2
1
C133
0.047U_0402_16V4Z~D
2
1
2
C470
0.047U_0402_16V4Z~D
1
C159
0.047U_0402_16V4Z~D
2
1
2
C153
0.047U_0402_16V4Z~D
1
C132
0.047U_0402_16V4Z~D
2
1
C130
0.047U_0402_16V4Z~D
2
1
2
C131
0.047U_0402_16V4Z~D
1
C152
0.047U_0402_16V4Z~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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MINIPCI
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
33
of
50
5
4
3
2
1
R320
10K_0402_5%~D
2
1
R321
10K_0402_5%~D
2
1
R330
10K_0402_5%~D
2
1
+3VALW
ATF_INT#
SYS_PME#
DEBUG_ENABLE
U24A
8051
GPIO
LPC INTERFACE
LFRAME#
LRESET#
T5
N6
L6
R6
T6
L7
P7
N7
SIO_SLP_S3#
SYS_PME#
ATF_INT#
SIO_SLP_S5#
SPDIF_SHDN
LID_CL_SIO#
T32 PAD~D
SIO_PWRBTN#
RUN_ON
ICH_PME#
SIO_THRM#
SUS_ON
ICH_PCIE_WAKE#
<22> SIO_PWRBTN#
<18,38,39,42,44,45> RUN_ON
<20> ICH_PME#
<22> SIO_THRM#
<38,39,44> SUS_ON
<18,22> ICH_PCIE_WAKE#
T38 PAD~D
<15> 5V_CAL_SIO#
C
IDE_RST_MOD
GC_BL_SUSPEND
USB_SIDE_EN#
MODC_EN#
HDDC_EN#
CK_33M_SIOPCI
CK_14M_SIO
<6> CK_33M_SIOPCI
<6> CK_14M_SIO
T6 PAD~D
+3.3VX
2
L3
L4
B2
254VCC0
1
R501
0_0402_5%~D
B12
A12
C11
D11
E11
A11
F10
C10
E2
2
1
C599
0.1U_0402_16V4Z~D +3VALW
M7
B11
R13
H12
E14
B7
A1
L11
B
G2
P4
J2
M2
+3VRUN
+3VRUN
L46
BLM11A121S_0603~D
1
2
KPLLVCC
R5
2
IR
P6
J1
H2
H1
H3
H4
H5
H6
H8
GPIOC0/PD0
GPIOC1/PD1
GPIOC2/PD2
GPIOC3/PD3
GPIOC4/PD4
GPIOC5/PD5
GPIOC6/PD6
GPIOC7/PD7
CLOCK
LPT
VCCO/BAT
VCC1_1
VCC1_2
VCC1_3
VCC1_4
VCC1_5
VCC1_6
VCC1_7
VCC1_8
VCC
VCC2_5/PLL
256 - LBGA
VSS13/PLL
R290 1
TXD0
R289 1
2 10K_0402_5%~D
F3
AGND
R288 1
2 10K_0402_5%~D
R517 1
R300 1
2 10K_0402_5%~D
2 10K_0402_5%~D
2
1
4
PAD~D T13
C
+3VALW
R324
100K_0402_5%~D
R329
10_0402_5%~D
2
1
LID_CL_SIO#
1
LID_CL#
LID_CL#
<36>
C362
0.047U_0402_10V7K~D
2
B
CK_33M_SIOPCI
CK_14M_SIO
KAGND
1
2
L85
BLM11A121S_0603~D
C597
@ 4.7P_0402_50V8C~D
2
C349
0.1U_0402_16V4Z~D
2
1
OUT Y
+3VRUN
+3VRUN
C600
0.1U_0402_16V4Z~D
2
1
C373
0.1U_0402_16V4Z~D
1
C614
0.1U_0402_16V4Z~D
2
C601
0.1U_0402_16V4Z~D
C364
0.1U_0402_16V4Z~D
1
GND
2 10K_0402_5%~D
LPC47N354_LBGA256~D
+3VALW
IN A
@ TC7SH04FU_SSOP5~D
C2
G4
N5
R15
B15
G9
J3
N1
T10
J11
G14
B6
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
GND
VCC
5
K7
J7
GPIOB0/STROBE
GPIOB3/ALF
VCC2_1
VCC2_2
VCC2_3
VCC2_4
NC
2
F1
G5
G1
H7
J6
OUTD0/SLCT
OUTD1/PE
OUTD2/BUSY
OUTD3/ACK
OUTD4/ERROR
C352
0.1U_0402_16V4Z~D
1
J4
J5
GPIOB2/SLCTIN
GPIOB1/INIT
PCI_CLK
CLOCKI
GPIO83/32KHZ_OUT
+5VSUS
U36
1
3
H15
K14
M4
GPIO10/WK_SE14/IRMODE/IRRX3B
IRRX
IRTX
LGPIO70
LGPIO71
LGPIO72
LGPIO73
LGPIO74
LGPIO75
LGPIO76
LGPIO77
<21>
<21>
LPC_LFRAME# <21>
PLTRST_SIO# <20>
TXD0
R338
<38>
<38>
5V_CAL_SIO#
T34 PAD~D
IDE_RST_MOD
GC_BL_SUSPEND
USB_SIDE_EN#
T14 PAD~D
T35 PAD~D
MODC_EN#
HDDC_EN#
LPC
GPIO
K1
K5
K2
K4
K3
K6
B10
L1
RXD1
TXD1
DSR
RTS
CTS
DTR
RI
DCD
COM1
LGPIO60/SPCLK
LGPIO61/SPDOUT
LGPIO62/SPDIN
LGPIO63
LGPIO64
LGPIO65
LGPIO66
LGPIO67
LPC_LDRQ0#
LPC_LDRQ1#
10K_0402_5%~D
<24>
<18>
<28>
A15
D13
A14
C12
B13
A13
D12
F11
LPC_LFRAME#
PLTRST_SIO#
R2
T2
R4
T3
DLDRQ1#
DLFRAME#
DSER_IRQ
DCLKRUN#
LGPIO50
LGPIO51
LGPIO52
LGPIO53
LGPIO54
LGPIO55
LGPIO56
LGPIO57
N4
L2
2
T31 PAD~D
SIO_SLP_S3#
SYS_PME#
ATF_INT#
SIO_SLP_S5#
SPDIF_SHDN
LPC_LDRQ0#
LPC_LDRQ1#
1
<22>
<29,31,33>
<15>
<22>
<19,25>
M6
R3
N2
P1
P2
N3
DLAD0
DLAD1
DLAD2
DLAD3
@ 1.5mm SMT~D
<33> DEBUG_OUT
LDRQ0#
LDRQ1#
<21>
1
SGPIO40
SGPIO41
SGPIO42
SGPIO43
SGPIO44
SGPIO45
SGPIO46
SGPIO47
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
Note: For system debug
pin4 connect to serial port pin3
2
C16
B16
C15
A16
D14
C14
C13
B14
M3
R1
T1
P3
IRQ_SERIRQ
<22,31>
CLKRUN# <22,29,31,33>
LPC_LAD[0..3]
2
1
A
2
1
1
0_0402_5%~D
SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_EXT_WAK#
SIO_RCIN#
NB_MUTE
BEEP
DEBUG_ENABLE
DEBUG_OUT
LAD0
LAD1
LAD2
LAD3
MACALLEN III
IRQ_SERIRQ
CLKRUN#
2
J1397
1
1
2
2
3
3
R340
SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_EXT_WAK#
SIO_RCIN#
NB_MUTE
BEEP
LPC47N354
D
J12
T4
P5
R503
@ 10_0402_5%~D
<33> DEBUG_ENABLE
2
EC_SCI/SPDIN
SER_IRQ
CLKRUN#
1
<22>
<22>
<22>
<21>
<26>
<25>
1
SGPIO30
SGPIO31
SGPIO32
SGPIO33
SGPIO34
SGPIO35
SGPIO36
SGPIO37
2
<28> USB_BACK_EN#
T16 PAD~D
<27> SUB_DETECT#
VAUX_EN
KSO17
USB_BACK_EN#
C598
@ 4.7P_0402_50V8C~D
CK_33M_SIOPCI_TERM
KSO_17
F13
F14
E16
E15
E12
E13
D16
D15
R502
@ 10_0402_5%~D
<36>
CB_HWSPND#
HP_NB_SENSE
<31> CB_HWSPND#
<26> HP_NB_SENSE
T46 PAD~D
<38> VAUX_EN
D21
RB751V_SOD323~D
KSO_17 2
1
CK_14M_SIO_TERM
D
2
A
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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SIO LPC47N354(1/2)
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
34
of
50
5
4
3
2
1
+3VALW
R322
2
IN2
1
Level shifter
R491
1K_0402_5%~D
2
1
+5VALW
+3VALW
H_PROCHOT_SIO#
1
4.7K_0402_5%~D
2
+3VALW
U24B
<42> PBAT_PRES#
T36 PAD~D
T33 PAD~D
<36> KSO16
<37> CAP_LED#
<37> NUM_LED#
<37> SRL_LED#
T15 PAD~D
<41>
NB_PSID
PBAT_ALARM#
R326
10K_0402_5%~D
2
1
FPVCC
C
THERMTRIP_SIO
H_PROCHOT_SIO#
<15> THERMTRIP_SIO
IN6
IN5
<41> PS_ID_DISABLE#
T11 PAD~D
T8 PAD~D
T7 PAD~D
T9 PAD~D
T10 PAD~D
Note: SMSC errata
LPC47N354 A Rev Anomaly Touch Pad IMCLK and IMDAT signals are inverted
<36>
<36>
2 100K_0402_5%~D
2 100K_0402_5%~D
IN2
FPVCC
IN5
IN6
PBAT_PRES#
KSO16
CAP_LED#
NUM_LED#
SRL_LED#
NB_PSID
BID0
BID1
BID2
BID3
PS_ID_DISABLE#
PAD~D
T39
PAD~D
SIO_MSCLK
SIO_MSDAT
CLK_SM2
DAT_SM2
G6
G3
CLK_SM2
DAT_SM2
B3
C4
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
R301
4.7K_0402_5%~D
2
1
R297
4.7K_0402_5%~D
2
1
B
R299
4.7K_0402_5%~D
1
2
R500
4.7K_0402_5%~D
1
2
+5VRUN
<36>
KSI[0..7]
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
DAT_KBD
CLK_KBD
C338
22P_0402_50V8J~D
CLK_SM1
DAT_SM1
CLK_32KX2
2
1
1
GPIO84
GPIO85
GPIO86
GPIO87
GPIO90
GPIO91
GPIO92
GPIO93
GPIO96
GPIO97
@
GPIO
2
XOSEL
SYSOPT0/GPIO80
SYSOPT1/GPIO81
BAT_LED
PWR_LED
GPIOA3/WINDMON
TESTA
VCC1RST#
RESET_OUT
PWRGD
ACAV_IN
POWER_SW_IN#
ALWON
MISC
EMCLK
EMDAT
GPIO94/IMCLK
GPIO95/IMDAT
M1
M5
KCLK
KDAT
G15
G12
G16
R7
T7
K8
J8
L8
M8
N8
P8
T8
R8
R9
T9
P9
N9
GPIO6 (WK_SE11)/IRMODE/IRRX3A
GPIO5 (WK_SE10)/KSO15
GPIO4 (WK_SE07)/KSO14
KSO13/GPIO18(WK_SE27)
KSO12/OUT8/KBRST
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
K/B
M9
L9
K9
K10
M10
R10
N10
P10
OUT0
OUT1/IRQ8
OUT2/FRD
OUT3/FWR
OUT4
OUT5/KBRST
OUT6
OUT7/SMI
OUT8/KBRST
OUT9/PWM2
OUT10/PWM0
OUT11/PWM1
AB1A_CLK
AB1B_DATA
AB1B_CLK
AB1A_DATA
GPIO11 (WK_SE15)/AB2A_DATA
GPIO12 (WK_SE16)/AB2A_CLK
GPIO13 (WK_SE17)/AB2B_DATA
GPIO14 (WK_SE20)/AB2B_CLK
GPIO15 (WK_SE21)/FAN_TACH1
GPIO16 (WK_SE22)/FAN_TACH2
GPIO82/FAN_TACH3
GPIO19 (WK_SE24)
MSCLK/SPCLK
MSDATA/SPDOUT
FA0
FA1
FA2
FA3
FA4
FA5
FA6
FA7
FA8
FA9
FA10
FA11
FA12
FA13
FA14
FA15
FA16
FA17
FA18
FA19
FA20
FA21
FA22
FRD
FWR
FCS
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
FLASH
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
E1
3.8X12.1mm
XTAL1
256 - LBGA
XTAL2
L10
SIO_KAH_PGM
E4
K15
K16
J9
J10
E3
F2
XOSEL
SYSOPT0
SYSOPT1
BAT1_LED#
BAT2_LED#
D2
L5
K13
VCC1RST#
RESET_OUT#
RUNPWROK
F4
F5
F6
ACAV_IN
POWER_SW_IN#
ALWON
D7
C7
F7
A6
E6
D6
C6
E7
A7
G7
G8
F8
EEPROM_WC
C9
F9
E9
D9
H16
H14
J15
J13
A10
H9
A5
F16
CLK_SMB
SMBUS_DATA
SMBUS_CLK
DAT_SMB
SMBDAT_VGA
SMBCLK_VGA
PBAT_SMBDAT
PBAT_SMBCLK
FAN1_TACH
FAN2_TACH
N12
T13
P12
T14
T15
R16
N13
P16
M14
N15
N16
M13
L12
M15
M16
L14
L13
L15
L16
K11
R14
T16
P13
P14
N14
P15
M12
R12
T12
P11
N11
M11
R11
T11
R508 2
R334 1
R335 1
BAT1_LED#
BAT2_LED#
HW_RADIO_DIS#
LAN_LOW_PWR
CHG_PBATT
1
H_PROCHOT#
1 10K_0402_5%~D
2 10K_0402_5%~D
2 10K_0402_5%~D
+3VALW
<37>
<37>
VCC1RST#
RESET_OUT#
RUNPWROK
<36>
<39>
<18,39,43,46>
ACAV_IN
ALWON
<47>
1
R505
<44>
EEPROM_WC
<36>
2 POWER_SW#
0_0402_5%~D
POWER_SW#
AUDIO_AVDD_ON
FAN2_PWM
BREATH_LED
FAN1_PWM
FAN2_PWM
BREATH_LED
FAN1_PWM
R516
10K_0402_5%~D
1
2
CLK_SMB
R515
10K_0402_5%~D
1
2
POWER_SW_IN#
R504
10K_0402_5%~D
1
2
<15,37>
+3.3VX
<25>
1
C
C609
0.1U_0402_16V4Z~D
<15>
<37>
<15>
2
CLK_SMB <15,36>
+5VALW
DAT_SMB <15,36>
SMBDAT_VGA <18>
SMBCLK_VGA <18>
PBAT_SMBDAT <42,47>
PBAT_SMBCLK <42,47>
FAN1_TACH
<15>
FAN2_TACH
<15>
SIO_A20GATE
SMBDAT_VGA
R337
22K_0402_5%~D
1
2
SMBCLK_VGA
R525
22K_0402_5%~D
1
2
PBAT_SMBDAT
R336
8.2K_0402_5%~D
1
2
PBAT_SMBCLK
R526
8.2K_0402_5%~D
1
2
SMBUS_DATA
R519
10K_0402_5%~D
1
2
SMBUS_CLK
R518
10K_0402_5%~D
1
2
SIO_A20GATE <21>
SIO_FA0
SIO_FA1
SIO_FA2
SIO_FA3
SIO_FA4
SIO_FA5
SIO_FA6
SIO_FA7
SIO_FA8
SIO_FA9
SIO_FA10
SIO_FA11
SIO_FA12
SIO_FA13
SIO_FA14
SIO_FA15
SIO_FA16
SIO_FA17
SIO_FA18
SIO_FA19
FRD#
FWR#
FCS#
SIO_FD7
SIO_FD6
SIO_FD5
SIO_FD4
SIO_FD3
SIO_FD2
SIO_FD1
SIO_FD0
DAT_SMB
HW_RADIO_DIS# <27,33>
LAN_LOW_PWR <29>
CHG_PBATT
<47>
AUDIO_AVDD_ON
<7>
+3VALW
SIO_FA[0..19]
<36>
FRD#
FWR#
FCS#
<36>
<36>
<36>
B
+3VALW
<36>
@
CLK_32KX1
LAN_LOW_PWR
CHG_PBATT
2
@
BID0
R319
1
2 @ 10K_0402_5%~D
BID1
R506
1
2
10K_0402_5%~D
BID2
R510
1
2
10K_0402_5%~D
BID3
R312
1
2
10K_0402_5%~D
0
0
0
0
X00
0
0
0
1
X01
R304
100K_0402_5%~D
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
+VCCP
D
K12
SIO_FD[0..7]
LPC47N354_LBGA256~D
E
BID3 BID2 BID1 BID0 REV
R318
10K_0402_5%~D
1
2
R507
10K_0402_5%~D
1
2
R511
10K_0402_5%~D
1
2
R311
10K_0402_5%~D
1
2
@
MACALLEN III
X6
32.768KHZ_12.5P_MC-306~D
+3VRUN
A
LPC47N354
GPIOA0
GPIOA1
GPIOA2
D1
C339
22P_0402_50V8J~D
1
2
FPGM
TEST_PIN
GPIO0 (WK_SE02)
GPIO1 (WK_SE03)
GPIO2 (WK_SE04)
GPIO3 (TRIGGER)
GPIO7 (WK_SE06)
GPIO8 (WK_SE12)/IRRX2
GPIO9 (WK_SE13)/IRTX2
GPIO17 (WK_SE23)/A20M
GPIO20 (WK_SE25)/PS2CLK/8051RX
GPIO21 (WK_SE26)/PS2DAT/8051TX
B5
E5
D5
A4
B4
C5
A3
A2
C3
D3
CLK_SM1
DAT_SM1
CLK_SM2
DAT_SM2
CLK_SM2
DAT_SM2
H13
H11
H10
G10
G13
J14
J16
G11
F15
F12
D10
E10
CLK_KBD
DAT_KBD
PBAT_ALARM#
<42> PBAT_ALARM#
<36> KSO[0..15]
<36>
<36>
IN0 (WK_EE4)
IN1 (WK_EE2)
IN2 (WK_EE3)
IN3 (GPWKUP)
IN5 (WK_SE01)
IN6 (WK_SE05)
IN7 (WK_EE1)
B1
D4
C1
<36> M_LED_C
<36> M_LED_B
<36> M_LED_A
T37
A9
B9
B8
A8
C8
D8
E8
+VCCP
R410
56_0402_5%~D
1
2
PROCHOT_SFTON 1
2Q39
B MMBT3904_SOT23~D
R323
10K_0402_5%~D
2
1
R327 1
R331 1
R409
56_0402_5%~D
2
C
1
R339
4.7K_0402_5%~D
1
2
+3VALW
R512
10K_0402_5%~D
1
2
+3VALW
R513
4.7K_0402_5%~D
1
2
+3VALW
R528
1K_0402_5%~D
@
R527
10K_0402_5%~D
2
1
3
D
4
3
2
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SIO LPC47N354(2/2)
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
35
of
50
5
4
3
2
1
Note: SMSC errata
LPC47N354 A Rev Anomaly - Touch Pad IMCLK and IMDAT signals are inverted
+3VALW
+3VALW
1
+5VRUN
1
R495
0_0402_5%~D
DAT_SM2
2
L47
BLM11A601S_0603~D
1
2
C590
0.1U_0402_16V4Z~D
2
NC
A1
A2
VSS
VCC
WP
SCL
SDA
1
8
7
6
5
EEPROM_WC
CLK_SMB
DAT_SMB
EEPROM_WC
CLK_SMB
DAT_SMB
<35>
<15,35>
<15,35>
AT24C04N-10SI-2.7_SO8~D
TP_DATA
SUB_6782U
CLK_SM2
D
U27
1
2
3
4
TP_CLK
2
SMbus address A2
1
2
1
2
1
2
C359
10P_0402_50V8J~D
L48
BLM11A601S_0603~D
C358
10P_0402_50V8J~D
CLK_SM2
C357
10P_0402_50V8J~D
DAT_SM2
<35>
C356
10P_0402_50V8J~D
<35>
R316
4.7K_0402_5%~D
2
1
R315
4.7K_0402_5%~D
2
1
D
1
2
LCM & Direct play SW & T PAD
JLCM
<34> KSO_17
<35> M_LED_A
<35> M_LED_B
<35> M_LED_C
C
BLM15AG221PN1D_0402~D
BLM15AG221PN1D_0402~D
BLM15AG221PN1D_0402~D
BLM15AG221PN1D_0402~D
2
2
2
2
<34> LID_CL#
L57
L61
L63
L60
1
1
1
1
TP_CLK
TP_DATA
+3VALW
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
2
4
6
8
10
12
14
16
18
20
L56
L52
L55
L51
L54
L50
L53
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
0.1U_0402_16V4Z~D
1
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
BLM15AG221PN1D_0402~D
BLM15AG221PN1D_0402~D
BLM15AG221PN1D_0402~D
BLM15AG221PN1D_0402~D
BLM15AG221PN1D_0402~D
BLM15AG221PN1D_0402~D
BLM15AG221PN1D_0402~D
1
ACES_87216-2012
C369
2
0.1U_0402_16V4Z~D
C376
1
1
3
5
7
9
11
13
15
17
19
2
C
+5VRUN
L58
BLM31A260SPT_1206~D
JKYBD
<35>
@
@
@
@
CN2
100P_1206_8P4C_50V8~D
4
5
3
6
2
7
1
8
@
CN3
100P_1206_8P4C_50V8~D
4
5
3
6
2
7
1
8
A
+3VALW
31
32
33
34
1
2
FCS#
FRD#
FWR#
21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37
FCS#
FRD#
FWR#
22
24
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
CE#
OE#
WE#
VCC
VCC
VPP
D0
D1
D2
D3
D4
D5
D6
D7
31
30
11
C366
100P_0402_50V8J~D
@
1
2
1
2
SIO_FD[0..7]
RP#/RESET#
WP#/RY/BY#
NC
NC
GND
GND
10
12
29
38
FWH_RST
2
1
VCC1RST#
VCC1RST#
<35>
<35>
R533
0_0402_5%~D
23
39
FWH_RST
+3VALW
R302
@10K_0402_5%~D
1
2
SST39VF080-70-4C-EI_TSOP40~D
A
@
KSI[0..7]
DELL CONFIDENTIAL/PROPRIETARY
KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
SIO_FD0
SIO_FD1
SIO_FD2
SIO_FD3
SIO_FD4
SIO_FD5
SIO_FD6
SIO_FD7
25
26
27
28
32
33
34
35
C361
0.1U_0402_16V4Z~D
SIO_FA0
SIO_FA1
SIO_FA2
SIO_FA3
SIO_FA4
SIO_FA5
SIO_FA6
SIO_FA7
SIO_FA8
SIO_FA9
SIO_FA10
SIO_FA11
SIO_FA12
SIO_FA13
SIO_FA14
SIO_FA15
SIO_FA16
SIO_FA17
SIO_FA18
SIO_FA19
C360
0.1U_0402_16V4Z~D
30
29
28
27
26
<35>
<35>
<35>
B
U32
<35> SIO_FA[0..19]
JAE_FK2S030W11~D
CN4
100P_1206_8P4C_50V8~D
4
5
3
6
2
7
1
8
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0
CN5
100P_1206_8P4C_50V8~D
4
5
3
6
2
7
1
8
<35> KSO[0..15]
KSO16
CN6
100P_1206_8P4C_50V8~D
4
5
3
6
2
7
1
8
<35>
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CN1
100P_1206_8P4C_50V8~D
4
5
3
6
2
7
1
8
B
KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
4
3
2
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INT KB
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
36
of
50
5
4
3
2
1
+3VRUN
IN
1
47K
+5VALW
3
<21> SATA_ACT#
2
10K
DTA114YKA
1
D
R_PIDEACT
Q3
DTA114YKA_SC59~D
2
<35> CAP_LED#
10K
2
1
3
10K
1
3
10K
1
1
2
R15
470_0402_5%~D
2
1
R_SRL
SRL_LED
Chroma_Pb
3
1
2
BAT1_LED
10K
1
2
L88
1.8UH_MDF1608A1R8K_10%_0603~D
1
2
Audio_L
2
+3VALW
2
B
JTUNR
R371
150_0402_5%~D
1
<6> CLK_PCIE_TV#
<6> CLK_PCIE_TV
CLK_PCIE_TV#
CLK_PCIE_TV
9
C
Q33
MMBT3904_SOT23~D
2
B
JTV2
9
1
R373
10K_0402_5%~D
1
2 BREATH_LED_B
1
3
5
7
9
11
13
15
17
19
+3VRUN
Z3901
<35> BREATH_LED
C
FOX_MH11777-WRUR6~D
2
B
1
C442
1
1
9
10
11
33P_0402_50V8J~D
C610
BAT2_LED
33P_0402_50V8J~D
R_BAT2_LED
TV_CVBS_Y
TV_Chroma_Pb
TV_Chroma_Pb
TV_Audio_L
@
R17
470_0402_5%~D
2
1
JTV1
2
4
6
7
5
3
1
8
TV_Audio_R
TV_Luma_Pr
TV_Audio_L
TV_Audio_R
C438
3
1
TV_Luma_Pr
33P_0402_50V8J~D
2
C420
C439
<35> BAT2_LED#
R_BAT1_LED
Q1
DTA114YKA_SC59~D
2
@
10K
33P_0402_50V8J~D
47K
1
L76
1.8UH_MDF1608A1R8K_10%_0603~D
1
2
Audio_R
R16
470_0402_5%~D
2
1
D
13
22P_0402_50V8J~D
C424
2
<35> BAT1_LED#
2
@
22P_0402_50V8J~D
1
+5VALW
Q6
DTA114YKA_SC59~D
2
L74
1.8UH_MDF1608A1R8K_10%_0603~D
1
2
C
47K
1
C419
2
14
E&T_3801-12-1~D
TV_CVBS_Y
@
NUM_LED
C433
<35> SRL_LED#
2
22P_0402_50V8J~D
R_NUM
Q5
DTA114YKA_SC59~D
22P_0402_50V8J~D
47K
1
L75
1.8UH_MDF1608A1R8K_10%_0603~D
1
2
CVBS_Y
R14
470_0402_5%~D
2
1
CLOSE TO JSVID
C431
CAP_LED
Q4
DTA114YKA_SC59~D
2
<35> NUM_LED#
R375
@ 0_0402_5%~D
22P_0402_50V8J~D
C434
R_CAP
1
22P_0402_50V8J~D
R13
470_0402_5%~D
2
1
2
12
11
10
9
8
7
6
5
4
3
2
1
L73
1.8UH_MDF1608A1R8K_10%_0603~D
1
2
Luma_Pr
@
47K
<33> LED_WLAN_OUT
<15,35> POWER_SW#
1
R18
470_0402_5%~D
ACTLED
2
1
3
47K
R_BT_MPCI_ACT
BAT1_LED
BAT2_LED
R_BREATH_LED
ACTLED
CAP_LED
NUM_LED
SRL_LED
LED_WLAN_OUT
POWER_SW#
POWER_SW_EMI
Q2
DTA114YKA_SC59~D
GND
2
+3VRUN
3
JLED
OUT
3
E
+3VALW
CVBS_Y
2
4
6
8
10
12
14
16
18
20
+5VRUN
TUNR_PLTRST#
PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1
R556
0_0402_5%~D
1
2
1
2
R555
@ 0_0402_5%~D
PCIE_TXN1
PCIE_TXP1
PLTRST_DELAY# <20,22>
PLTRST#
<20,22,24>
<22>
<22>
SUYIN_800160FA020S200ZR~D
Luma_Pr
Chroma_Pb
Audio_L
Audio_R
PCIE_RXN1
C663
1
2
0.1U_0402_10V7K~D
PCIE_RXN1_C
PCIE_RXP1
C664
1
2
0.1U_0402_10V7K~D
PCIE_RXP1_C
PCIE_RXN1_C <22>
2
E&T_3801-08-1~D
1
2
3
4
5
6
7
8
10
10
R_BREATH_LED
1
2
3
4
5
6
7
8
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
R372
150_0402_5%~D
PCIE_RXP1_C <22>
JWIRE
1
JPHON
Z3902
1
2
<27> BT_ACTIVE
BT_ACTIVE
R370
10K_0402_5%~D
1
2
E&T_3802-02-1~D
1
A
C
BT_MPCI_ACTIVE
Q32
MMBT3904_SOT23~D
2
B
RJ_TIP
RJ_RING
RJ_TIP
RJ_RING
1
2
3
4
1
2
A
GND1
GND2
DELL CONFIDENTIAL/PROPRIETARY
SUYIN_100002FR006G202ZU~D
3
E
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R_BT_MPCI_ACT
Title
Size
Date:
5
4
3
2
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JLED
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
37
of
50
2
Z4010
2
R307
@ 47_0805_5%~D
Z4009
2
G
2
G
Q25
D @ 2N7002_SOT23~D
S
D
2
G
S
3
S
3
S
3
S
2
G
3
3
2
G
2
1
Q26
D @ 2N7002_SOT23~D
1
2
Q11
D @ 2N7002_SOT23~D
1
2
Q27
D @ 2N7002_SOT23~D
1
2
Q22
D @ 2N7002_SOT23~D
3
2
Z4008
2
Z4007
1
1
1
1
1
2
1
R308
@ 22_0805_5%~D
2
S
D
S
1
1
+1.8VSUS
R88
@ 22_0805_5%~D
4
Q35
1
@ SI3456DV-T1_TSOP6~D
Z40182
2
R87
@ 22_0805_5%~D
Z40152
R89
@ 100K_0402_5%~D
D
Q31
@ 2N7002_SOT23~D
2
G
3
+1.5VRUN Source
1
1
+1.5VSUS
1
+5VALW
D
3
R522
10K_0402_5%~D
@
2
2
C618
4.7U_0805_10V4Z~D
G
3
1
G
S
6
5
2
1
3
Q23
2N7002_SOT23~D
3
RUN_ON
+1.5VSUS
D
2
S
4
S
3
Q24
2N7002_SOT23~D
D
2
G
R127
@ 22_0805_5%~D
+5VRUN
6
5
2
1
C348
4700P_0402_25V7K~D
1
2
G
R309
@ 22_0805_5%~D
+1.8VRUN
1
Q14
D @ 2N7002_SOT23~D
2
G
Q52
SI3456DV-T1_TSOP6~D
2
1
1
D
RUN_ON_5V#
+VCCP
1
2
2
+5VRUN Source
+1.5VRUN
1
R313
@ 22_0805_5%~D
1
R277
10K_0402_5%~D
@
2
+3VRUN
Z4006
2
1
1
1
R225
@ 47_0805_5%~D
1
C321
4.7U_0805_10V4Z~D
4
+5VSUS
S
Q34
@ 2N7002_SOT23~D
2
G
S
+1.5VSUS
+5VSUS
SUSPWROK_5V#
+1.5VRUN
1
2
2
3
DTC144EKA_SOT23~D
1
R274
100K_0402_5%~D
4
1
2
2
C347
4.7U_0805_10V4Z~D
1
R305
10K_0402_5%~D
@
2
1
2
5
6
1
2
<34> HDDC_EN#
0.01U_0402_25V7K~D
3
1
SUSPWROK_5V <44,45>
SI3456DV-T1_TSOP6~D
+5VHDD
S
C315
4.7U_1206_16V6K~D
D
1
3
1
2
D Q19
G
HDD_EN
2
<29>
1
1
Q29
2N7002_SOT23~D
B
R343
470K_0402_5%~D
2
S
+5VSUS
+15V
2
MOD_EN 3
<34> MODC_EN#
1
2
Q53
DTC144EKA_SOT23~D
1
2
1
1
C303
4.7U_0805_10V4Z~D
SI3456DV-T1_TSOP6~D
+5VMOD
S
R529
100K_0402_5%~D
2
2
4
C288
0.1U_0402_16V4Z~D
3
S
R270
470K_0402_5%~D
2
1
D
Q16
2N7002_SOT23~D
S
R267
200K_0402_5%~D
2
1
1
2
2
1
D
2
G
+3VSUS Source
2
2
G
D Q28
G
2
1
R262
200K_0402_5%~D
Q15
2N7002_SOT23~D
SUS_ON
+3VSUS
1
2
3
4
1
8
7
6
5
C620
4.7U_1206_16V6K~D
1
R258
470K_0402_5%~D
R530
100K_0402_5%~D
C371
0.01U_0402_25V7K~D
1
Q17
SI4810DY_SO8~D
1
<34,39,44> SUS_ON
+5VMOD Source
+3VSRC
1
PWR_SRC
3
PWR_SRC
1
2
5
6
1
S
D
2
G
3
D
2
G
R344
200K_0402_5%~D
2
1
1
+5VHDD Source
S
G
3
1
1
2
R347
100K_0402_5%~D
ENAB_3VLAN
VAUX_EN
R287
100K_0402_5%~D
S
Q20
4
PWR_SRC
1
N21917830
<34>
C
Q48
@ 2N7002_SOT23~D
+1.8VRUN
6
5
2
1
R348
100K_0402_5%~D
R384
10K_0402_5%~D
@
2
+1.8VRUN Source
Q21
SI3456DV-T1_TSOP6~D
PWR_SRC
1
SUSPWROK_5V 2
G
C327
+1.8VSUS
1
+15V
D
2
C403
4.7U_0805_10V4Z~D
1
2
3
4
8
7
6
5
1
Q55
SI4800DY-T1_SO8~D
3
A
1
1
RUN_ON_5V#
Q30
2N7002_SOT23~D
B
1
2
3
RUN_ENABLE
<18,34,39,42,44,45>
C
8
7
6
5
R314
100K_0402_5%~D
2
R310
100K_0402_5%~D
+0.9V_DDR_VTT
1
+3VRUN
+5VALW
3
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Q18
SI4810DY_SO8~D
D
+VCC_CORE
+3VRUN Source
+3VSRC
+15V
2
Z4005
Run Planes Enable
3
1
4
1
5
2
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
POWER CONTROL
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
38
of
50
5
4
3
U29B
74VHC08MTC_TSSOP14~D
+3VSUS
1
+3VSUS
1
<22>
A
Y
8
7
6
SN74LVC3G14DCTR_SSOP8~D
Y
+3VSUS
2
1
2
U30C
RUN_ON
10
R292
IN1
8
OUT
9
IN2
1
IN1
OUT
IN2
3
7
<42> 2P5V_PWRGD
<18,34,38,42,44,45>
D
U29A
74VHC08MTC_TSSOP14~D
P
G
1
74VHC08MTC_TSSOP14~D
R497
0_0402_5%~D
1
2
C585
0.1U_0402_16V4Z~D
2
SN74LVC3G14DCTR_SSOP8~D
14
C591
0.1U_0402_16V4Z~D
U26B
A
4
14
P
2
3
OUT
IN2
1
1
G
5VRUNRC
U30A
7
<35> RESET_OUT#
IN1
2
U26A
G
ICH_PWRGD
IN2
74VHC08MTC_TSSOP14~D
1
+3VSUS
8
R498
0_0402_5%~D
2
P
OUT
1
G
5
6
4
+3VSUS
U30B
P
IN2
+3VSUS
4
IN1
RUNPWROK
C589
0.1U_0402_16V4Z~D
2
R492
100K_0402_5%~D
2
+3VSUS
0_0402_5%~D
74VHC08MTC_TSSOP14~D
@
R293
1
U29D
74VHC08MTC_TSSOP14~D
2
@ 0_0402_5%~D
13
12
U30D
13
12
IN1
OUT
IN1
OUT
11
RUNPWROK
RUNPWROK
<18,35,43,46>
IN2
11
IN2
74VHC08MTC_TSSOP14~D
1.5VSUS_PWRGD
SUS_ON
9
IN1
OUT
8
SUSPWROK <15,22>
IN2
1
<34,38,44> SUS_ON
C
+3VSUS
10
+3VSUS
R550
100K_0402_5%~D
U29C
2
74VHC08MTC_TSSOP14~D
1
D
3
ICH_PWRGD
ICH_PWRGD#
S
ICH_PWRGD#
<15>
Q60
2N7002_SOT23~D
2
G
B
+3VALW
2
U26C
Y
5
1.5VSUS_PWRGD
G
1
A
4
Q50
MMBT3904_SOT23~D
SN74LVC3G14DCTR_SSOP8~D
E
3
1
3
C
2
B
C584
0.1U_0402_16V4Z~D
8
1
R490
R482
10K_0402_5%~D
+3VSUS
P
1
+1.5VSUS
100K_0402_5%~D
A
OUT
1
+3VRUN
6
2
B
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C
IN1
5
<7> ITP_DBRESET#
D
4
2
IMVP_PWRGD
<10,22,46> IMVP_PWRGD
2
2
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
Power Good
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
39
of
50
5
4
3
2
1
Fiducial Mark
FD1
FD2
1
1
@ SMD40M80
CLP4
@ EMI_CLIP~D
D
CLP10
@ EMI_CLIP~D
1
FD10
CLP13
@ EMI_CLIP~D
GND
GND
@ SMD40M80
FD4
1
@ SMD40M80
1
@ SMD40M80
FD5
1
@ SMD40M80
FD11
1
GND
1
FD3
FD17
1
FD18
@ SMD40M80
FD7
1
@ SMD40M80
1
@ SMD40M80
FD14
1
@ SMD40M80
FD15
1
@ FIDUCAL
FD9
1
@ SMD40M80
FD13
1
@ FIDUCAL
FD8
1
@ SMD40M80
FD12
1
@ SMD40M80
FD6
1
@ SMD40M80
FD16
1
@ FIDUCAL
D
FD21
1
@ FIDUCAL
1
@ FIDUCAL
@ FIDUCAL
CLP11
@ EMI_CLIP~D
1
1
GND
CLP18
@ EMI_CLIP~D
1
GND
MY1
@ MYLAR_CARDBUS~D
MY6
@ MYLAR_DOCK_FRAME~D
MYLAR(ZZZ)
1
NC
TPAD1
@ THERMAL_PAD_MCH~D
THERM PAD
MYLAR(ZZZ)
1
1
NC
CAGE1
FCI_57996-001(W/SC)~D
CARDBUS CAGE
1
NC
NC
C
C
MY2
@ MYLAR_HDD~D
H2
H3
H4
H5
H6
H7
H8
H9
H10
H12
@ C315D126 @ C276D126 @ C315D126 @ C276D126 @ C315D126 @ C276D126 @ C315D126 @ C315D126 @ C315D126 @ C236D110
MYLAR(ZZZ)
NC
MY3
@ MYLAR_DIMMA~D
NC
MY4
@ MYLAR_DIMMB~D
MY8
@ MYLAR_MCH_BOTTOM~D
BARE PCB
1
NC
NC
NC
TPAD3
@ THERMAL_PAD_VRAM~D
THERM PAD
MYLAR(ZZZ)
1
1
NC
NC
MY9
@ MYLAR_BATTERY~D
MYLAR(ZZZ)
1
1
1
1
1
1
1
H26
H27
H28
H29
H32
H30
H31
@ C236D110 @ C236D110 @ C276D110 @ C276D126 @ C276D110 @ C134D134N@ O181X134D181X134N
1
1
1
1
H25
@ C315D91
1
NC
PCB
DAQ20_LA-2171 _REV0 _M/B~D
THERM PAD
MYLAR(ZZZ)
1
MYLAR(ZZZ)
1
1
1
1
1
1
1
1
1
1
1
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
@ C236D110 @ C236D110 @ C315D209 @ C315D110 @ C315D110 @ C315D209 @ C315D110 @ C236D110 @ C236D110 @ C315D91
H24
@ C315D91
TPAD2
@ THERMAL_PAD_VGA~D
1
1
1
1
1
1
1
1
1
1
1
H23
@ C315D91
MY7
@ MYLAR_MCH_TOP~D
MYLAR(ZZZ)
1
NC
MY5
@ MYLAR_MINIPCI~D
B
B
MYLAR(ZZZ)
1
NC
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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PAD and Standoff
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
40
of
50
A
+3VALW
2
+3.3VRTC
PWR_SRC
1
Source
PQ12
2N7002_SOT23~D
PS_ID
PR75
0_0402_5%~D
1
2
2
1
1
2
D
RTC_SHDN#
PR57
0_0402_5%~D
EC10QS04_SOD106~D
2
NB_PSID
<35>
+3.3VX
G
2
S
3
D
1
1
PD9
@ DA204U_SOT323~D
1
2
PR78
2.2K_0402_5%~D
3
PD8
+5VALW
PU2
1
IN
3
1
2
GND
PC33
10U_1206_6.3V7K~D
MAX1615EUK_SOT23-5~D
4
5/3+
2
1
<35>
#SHDN
1
1
PS_ID_DISABLE#
5
2
PC34
0.1U_0805_50V7M~D
2
1
PR68
100K_0402_1%~D
2
OUT
PR69
100K_0402_5%~D
C
2
B
PQ10
MMBT3904_SOT23~D
1
2
3
E
C
DC_IN+ Source
PL15
BLM11A121S_0603~D
6
GND_2
DC-_1
GND_1
DC-_2
4
3
1
4
5
PL1
@ FBM-L18-453215-900LMA90T_1812~D
DCIN-
1
2
1
1
4
1
2
1
PQ_G
B
2
2
2
DCIN+
2
3
PC1
10U_1210_25V7K~D
7
PL3
OC8070-A301~D
2
PC45
0.1U_0805_50V7M~D
DC+_2
PC48
0.01U_0402_25V7K~D
DC+_1
GND_3
2
GND_4
+DC_IN
8
7
6
5
DC_IN
2
1
PR16
150K_0402_5%~D
Low_PWR
1
1
8
1
2
3
PL2
@ FBM-L18-453215-900LMA90T_1812~D
PJDC1
HRS_HR33-DL-7~D
9
PQ1 SI4825DY_SO8~D
PS_ID
1
1
2
Z-series AC Adaptor
Connctor
2
PR11
100K_0402_5%~D
PWR_ID
PC3
0.47U_1812_50V7M~D
B
3
+5VALW
PR62
15K_0402_1%~D
C
4
MH1
MH2
D
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5
THE POINT
NOTE: "THE POINT LOCATED
AT PS MODULE
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
+DCIN
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
41
of
50
5
4
3
2
1
D
D
+3VALW
ESD Diodes
2
3
2
3
2
3
2
3
9
8
+3VALW
PD21
@ DA204U_SOT323~D
PBATT+
C
PC40
2200P_0402_50V7K~D
2
1
PJBAT
BATT1+
BATT2+
SMB_CLK
SMB_DAT
BATT_PRES#
SYSPRES#
BATT_VOLT
GND
BATT1GND
BATT2-
10
11
1
2
3
4
5
6
7
8
9
PR164
100_0402_5%~D
1
2
Z4304
Z4305
Z4306
PR161
100_0402_5%~D
1
2
PR155
100_0402_5%~D
PR162
1
2
100_0402_5%~D
1
2
PBAT_SMBCLK <35,47>
PBAT_SMBDAT <35,47>
7
+VCHGR
PL13
FBM-L18-453215-900LMA90T_1812~D
1
2
6
5
PR156
10K_0402_5%~D
2
1
1
1
PD17
@ DA204U_SOT323~D
1
1
Primary Battery Connector
PD20
@ DA204U_SOT323~D
PC41
0.1U_0805_50V7M~D
1
2
EMI team suggest
PD19
@ DA204U_SOT323~D
4
3
2
1
PBAT_PRES#
<35>
C
PBAT_ALARM# <35>
SUYIN_20175A-09G1
TOP view
SUYIN_200275MR009G516ZL~D
B
B
+2.5VRUN
R1=R2* (Vo/ 0.8 -1), R2:25K~100K.
PU1
OUT
POK
SET
8
7
6
5
9
SHDN# GND1
GND2
MAX1806EUA25_8UMAX~D
2P5V_PWRGD
PR166
<18,34,38,39,44,45>
1
NC_TEST6
2
10K_0402_1%~D
A
2
PAD-OPEN 4x4m
2
A
1
RUN_ON
+2.5VRUN
PJP4
PR32
@ 0_0603_5%~D
1
2
1
+2.5VRUNP
+2.5VRUNP
PC13
0.1U_0805_25V7K~D
2
1
4
OUT
IN
PC14
10U_1206_6.3V7K~D
2
1
3
IN
PR31
30.9K_0402_1%~D
2
1
<39> 2P5V_PWRGD
PC16
1U_0805_10V7K~D
2
1
PC15
0.1U_0805_25V7K~D
2
1
PR33
10K_0402_5%~D
2
1
+3VSUS
2
PR30
66.5K_0402_1%
2
1
1
+3VSRC
PC130
0.1U_0402_10V6K~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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Battery Conn./+2.5V
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
42
of
50
A
B
C
D
4
@
+3VSUS
8
MAX1845_VCC
<46> VCCP_PWRGD
PC50
10U_1206_25V6M~D
PC51
10U_1206_25V6M~D
PC7
0.1U_0603_25V7K~D
2
1
PC49
2200P_0402_50V7K~D
2
1
1
2
5
6
7
8
3
2
1
Design current 5A for +VCCP_1P05VP
Peak current 7.124A for +VCCP_1P05VP
2
+VCCP_1P05VP
PL4
1.8U +-30% DC104C-919AS-1R8N 9.5A~D
1
2
5
6
7
8
PC52
0.1U_0805_50V7M~D
2
1
PD10
RB751V-40_SOD323~D
1
2
1.05V_BST2
PC67
4.7U_0805_6.3V6K~D
1
2
VDD
21
MAX1845_VCC 1
22
VCC
OUT1
2
1
ON1
ON2
SKIP
TON
OVP
ILIM1
UVP
ILIM2
10
MAX1845_REF
@
5
3
13
MAX1845EEI_QSOP28~D
+
2
1
+
2
1
1
2
4
PD12
EP10QY03~D
1.05V_FB
PC10
330U_D2E_2.5VM~D
2
PQ16
FDS6676S_SO8~D
PC11
330U_D2E_2.5VM~D
REF
PGOOD
1.05V_OUT
PC69
0.1U_0805_25V7K~D
2
1
FB2
1.05V_DL
1
PR97
1K_0402_1%~D
2
1
FB1
24
3
2
1
OUT2
28
@
PR87
@ 0_0603_5%~D
1
2
NC_TEST2
3
SUSPWROK_1P8V
1
<45> SUSPWROK_1P8V
9
DL2
1
PR96
20K_0402_1%~D
2
1
6
DL1
PR98
90.9K_0402_1%~D
2
1
12
CS2
PQ15
IRF7811A_SO8~D
4
PR99
280K_0402_1%~D
2
1
11
CS1
PR90
150K_0402_1%~D
2
1
7
LX1
LX2
27
PR89
90.9K_0402_1%~D
2
1
14
DH2
26
PR94
0_0402_5%~D
2
1.5V_FB
DH1
PR86
0_0603_5%~D
1.05V_BST
1
2
PR80
1.05V_DH
1
2
0_0603_5%~D
1.05V_LX
1
15
BST1
25
PC66
1U_0603_10V6K~D
2
1
1.5V_OUT
BST2
GND
20
V+
23
PR108
10K_0402_1%~D
2
1
PR107
@ 0_0603_5%~D
1
2
<18,35,39,46> RUNPWROK
1.5V_DL
VCCP_PWRGD
PR101
0_0402_5%~D
2
1
PR91
100K_0402_5%~D
2
1
NC_TEST1
PU4
1.5V_V+
PR100
4
0_0603_5%~D
2
11.5V_BST 19
PR24
1.5V_DH 18
1
2
0_0603_5%~D
1.5V_LX
17
16
PD11
RB751V-40_SOD323~D
2
1
2
PR109
20K_0402_1%~D
2
1
+
PC73
0.1U_0805_25V7K~D
2
1
PJP1
+1.5VSUSP
1
2
+1.5VSUS
2
1
PC12
220U_D_2.5VM~D
2
PD5
EP10QY03~D
3
1
PQ2
SI4814DY_SO8~D
8
1
G1
D1
7
2
S1/D2 D1
6
3
S1/D2 G2
5
4
S1/D2 S2
PR104
0_0402_5%~D
2
1
PL5
3U_SPC-07040-3R0_5A_30%~D
1
2
+1.5VSUSP
PC70
1000P_0402_50V7K~D
2
1
2
PC65
1U_0603_6.3V6M~D
2
1
PC68
0.1U_0805_50V7M~D
2
1
Design current 3A for +1.5VSUSP
Peak current 4.034A for +1.5VSUSP
PR92
20_0603_1%~D
2
+5VSUS
PD13
RB751V-40_SOD323~D
1.5V_BST2
1
2
2
PC9
2200P_0402_50V7K~D
2
1
1
PC53
0.1U_0603_25V7K~D
1
2
PL14
FBM-L11-322513-151LMAT_1210~D
PWR_SRC
1
2
PC8
10U_1206_25V6M~D
1
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+1.5VSUSP / +VCCP_1P05VP
PC129
1000P_0402_50V7K~D
PAD-OPEN 4x4m
PJP2
+VCCP
1
2
+VCCP_1P05VP
PAD-OPEN 4x4m
4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
A
B
C
+1.5VSUSP /+VCCP_1P05VP
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
D
43
of
50
5
4
3
2
1
2
2
1
PC113
2200P_0402_50V7K~D
2
5
6
7
8
1
PC26
1U_0603_10V6K~D
2
1
PC28
4.7U_1206_25V6K~D
1
3
2
PD7
RB717F_SOT323~D
1
2
PC91
1U_0603_10V6K~D
PQ32
SI4800DY-T1_SO8~D
Design current 4A for +5VSUS
Peak current 5.7A for +5VSUSP
4
BST_5
PL9
3
2
1
1
1
2
2
PR123
0_0402_5%~D
PC27
330U_D3L_6.3VM_R25~D
1
PC121
0.1U_0805_50V7M~D
2
PR120
0_0402_5%~D
5
6
7
8
ILIM3
<18,34,38,39,42,45>
2
1
2
PR58
0_0402_5%~D
@
RUN_ON
1
PRO#
@
2
1
PR149
0_0402_5%~D
2
1
Adding SKIP control
PR59
0_0402_5%~D
PR137
0_0402_5%~D
ILIM5
1
TON
2
1
VCC_MAX1999
PR138
0_0402_5%~D
2
@
<38,45>
2
2
1
PR60
240K_0402_5%~D
1
NC_TEST4
2
VCC_MAX1999
SUSPWROK_5V
@
2
PC38
1000P_0402_50V7K~D
1
<34,38,39> SUS_ON
1
PR143
0_0402_5%~D
PR61
2K_0402_1%~D
PR55
@ 0_0603_5%~D
+3VSRCP
PR136
0_0402_5%~D
2
+
2
C
1
MAX1999_SKIP#
1
+3VALW
2
PC94
10U_1206_6.3V7K~D
SUS_ON
ILIM5
ILIM3
REF
TON
1
REF
12
MAX1999EEI_QSOP28~D
NC_TEST3
FB5
PRO#
2
LDO3
FB3
11
5
8
13
23
2
ILIM5
ILIM3
REF
TON
GND
PGOOD
1
ON3
ON5
@
2
25
21
1
9
10
OUT3
FB3
PQ27
SI4810DY_SO8~D
4
1
3
4
DL5
2
7
19
2
2
DL3
SKIP
2
22
PR126
0_0603_5%~D
PR141
30.1K_0402_1%~D
OUT5
N.C.
FB5
PRO
1
LX5
1
LX3
DH5
15
PR146
147K_0402_1%~D
24
DL5
1
1
DL3
DH3
16
PR142
57.6K_0402_1%~D
27
LX5
PR148
147K_0402_1%~D
LX3
DH5
BST3
+5VSUSP
2
3
2
1
26
SHDN
5.6U_CEP125-5R6MC_8.8A_20%~D
2
2
DH3
1
6
28
PC31
0.1U_0603_25V7K~D
1
1
2
2
PR49
0_0603_5%~D
2BST3
1
BST5
PR56
0_0603_5%~D
BST5
1
2
PR140
100K_0402_5%~D
1
VCC
14
1
2
18
LDO5
2
PC29
0.1U_0603_25V7K~D
1
2
3
4
D1
D1
G2
S2
V+
PC120
1U_0805_10V7K~D
17
PR124
0_0603_5%~D
<34,38,39> SUS_ON
D
PU6
1
PR145
0_0402_5%~D
1
BST_3
@
2
PR144
0_0402_5%~D
1
G1
S1/D2
S1/D2
S1/D2
PC107
0.1U_0805_50V7M~D
2
1
PR121
4.7_1206_5%~D
1
1
2
2
PC93
0.1U_0603_25V7K~D
PC95
4.7U_1206_25V6K~D
PC97
10U_1206_25V6M~D
2
1
1
PR48
47_0603_5%~D
20
8
7
6
5
2
+5VALW
1
1
PR54
@ 0_0603_5%~D
2
PC119
0.1U_0805_50V7M~D
PC39
330U_D3L_6.3VM_R25~D
1
2
VCC_MAX1999
@
B
PR147
1K_0402_5%~D
<35> ALWON
1
2
Note: check the power consumption of +15V plane
PC96
@ 1000P_0603_50V8J~D
<15> THERM_STP#
2
1
+15VP
PR122
30.9K_0402_1%~D
2
PL11
2
PJP13
+3VSRC
(4A,160mils ,Via NO.= 8)
1
PAD-OPEN 4x4m
D
G
S
4
1
2
2
PQ30
SI3442DV_TSOP6~D
3
PC110
0.1U_0603_25V7K~D
2
8
7
6
5
2
1
PR157
150_0603_1%~D
+3VSRCP
FB
OSC
GND
OUT
PJ3800CS_SO8~D
1
PJP9
2
(6A,240mils ,Via NO.= 12)
PC116
0.1U_0603_25V7K~D
+5VSUS
-IN
SCP
VCC
BR/CTL
1
2
5
6
1
2
3
4
2
2
PAD-OPEN 4x4m
1
1
PR125
1.07K_0402_1%~D
PJP8
1
PC90
22U_1206_6.3VAM~D
1
EC31QS04~D
PU8
PAD-OPEN 4x4m
+5VSUSP
2
PR135
3.01K_0402_1%~D
+15V
PD15
1
22U_SPC_06704_22R0_1.5A_30%~D
(150mA,Via NO.= 2)
1
2
1
1
2
+15VP
1
+
2
PC128
10U_1206_25V6M~D
1
PC92
15U_D2_25M_R90~D
+5VSUSP
PC111
270P_0402_25V8K~D
A
PL10
10U_SPC-1204P-100_4.5A_20%~D
+
2
PQ29
SI4814DY_SO8~D
+3VSRCP
1
1
2
B
2
2
Place these CAPs
close to FETs
1
2
PC98
10U_1206_25V6M~D
2
PC106
0.1U_0805_50V7M~D
1
PWR_SRC
Design current 3.4A for +3.3VSRC
Peak current 4.758A for +3VSRCP
C
Place these CAPs
close to FETs
PL20
FBM-L11-322513-151LMAT_1210~D
PC99
2200P_0402_50V7K~D
D
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DC/DC +3V/ +5V/ +15V
1
1
2
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
+3.3V/+5V/+15V
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
44
of
50
4
A
1
DDR2 Termination
1
D
+5VSUS
2
POK2
2
1
2
PR34
470K_0402_5%~D
1
1
2
1
6
PR45
0_0402_5%~D
27
2
1
SUSPWROK_1P8V
<43>
+0.9V_PWRGD
1
3
+0.9V_DDR_VTTP
9
10
SS
8
2
1
PC19
1
1
12
MAX8550ETI_TQFN28~D
1000P_0402_50V7K~D
SKIP
GND
24
4
ILIM
VTTR
25
2
REF
G
<18,34,38,39,42,44>
S
1
+
2
1
2
1
2
1
2
@
1
TON
2
2
PR38
150K_0402_1%~D
2
1
1
PC74
0.22U_0603_16V7K~D
11
RUN_ON
Design current 1.05A for +0.9V_DDR_VTTP
Peak current 1.5A for +0.9V_DDR_VTTP
2
VTT
2
2
2
PGND2
FB
1
2
NC_TEST5
PR41
100K_0402_1%~D
PR117
@ 0_0603_5%~D
3
2
PC131
10U_1206_6.3V7K~D
1
1
PC82
0.1U_0603_25V7K~D
PC21
22U_1206_6.3VAM~D
15
14
PQ23
2N7002_SOT23~D
PC20
22U_1206_6.3VAM~D
1
REFIN
VOUT
D
+1.8VSUS
PC17
22U_1206_6.3VAM~D
0_0402_5%~D
2
PR40
20_0603_1%~D
1
1
2
3
1.8V_FB
PR36
C
13
PC75
10U_1206_6.3V7K~D
VTTI
PGND1
4
16
<38,44>
0_0402_5%~D
7
PC86
150U _D2_6.3VM~D
23
PR42
STBY
DL
1
21
SUSPWROK_5V
2
1.8V_DL
LX
PC87
0.1U_0603_25V7K~D
19
SHDNA
VTTS
PR118
17.4K_0402_1%~D
5
2
POK1
DH
2
PC18
1U_0603_6.3V6M~D
26
28
2
22
VDD
+5VSUS
VIN
@
V_DDR_MCH_REF
<10,16,17>
2
PQ24
FDS6676S_SO8~D
1.8V_LX
1.8V_REF
1
PR46
470K_0402_5%~D
2
1
PR35
10_0402_5%~D
2
18
BST
1
2
1
20
1
1.8V_DH
2
1
PR116
27.4K_0603_1%~D
2
2
+
PC25
0.1U_0603_25V7K~D
PC23
330U_D2E_2.5VM~D
PC24
330U_D2E_2.5VM~D
2
1
2
1.8V_0.9V_PWR_SRC
17
PR37
100K_0402_5%~D
1
AVDD
1
SHDNB
2
OVP/ UVP
4
PU5
PR113
0_0603_5%~D
8
7
6
5
1
PC83
0.1U_0603_25V7K~D
1
2
3
PL8
2.2U_SPC-1205P-2R2B_13A_30%~D
+
1
8
7
6
5
PQ25
IRF7811A_SO8~D
+1.8VSUSP
1
AVDD
1
2
PC22
4.7U_0805_6.3V6K~D
+5VSUS
PD14
RB751V-40_SOD323~D
2
PC81
2200P_0402_50V7K~D
2
1
2
1
1
1.8V_0.9V_PWR_SRC
1
PC78
0.1U_0805_50V7M~D
2
FBM-L11-322513-151LMAT_1210~D
PC76
10U_1206_25V6M~D
PWR_SRC
PC80
1U_0603_10V6K~D
B
2
PL17
Design current 7A for +1.8V_SUSP
Peak current 10.1A for +1.8VSUSP
C
3
+1.8VSUSP/ +0.9V_DDR_VTT
PC79
10U_1206_25V6M~D
D
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5
B
PJP6
PAD-OPEN 4x4m
1
2
PJP7
PAD-OPEN 4x4m
+1.8VSUSP
1
+0.9V_DDR_VTTP
1
2
+1.8VSUS
2
+0.9V_DDR_VTT
(8A,320mils ,Via NO.=16)
PJP12
PAD-OPEN 4x4m
A
(3A,200mils ,Via NO.=6)
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Size
Date:
5
4
3
2
+1.8VSUSP/ +0.9V_DDR_VT
Document Number
Board Number LA2111
,
Rev
0.1
12, 2004
Sheet
1
45
of
50
8
7
V I D
1.484
0
1
1
0
1
0
1
1
1
1
1
1
1
0
1
1.308
1
0
0
B
PL16
FBM-L18-453215-900LMA90T_1812~D
1
FB
18
CCV
D
<6> CLK_ENABLE#
2
1
1
D
S
1
2
G
PQ18
@ 2N7002_SOT23~D
2
G
1
D
D
D
D
G
S
S
S
G
S
S
S
4
3
2
1
4
3
2
1
G
S
S
S
2
4
3
2
1
PD2
RB751V-40_SOD323~D
1
PC71
0.01U_0402_25V7K~D
D
PR29
0.001_2512_5%~D
2
1
+VCC_CORE
2
C
2
@
+5VRUN
S
B
DELL CONFIDENTIAL/PROPRIETARY
PR22/PQ8/PQ17/PQ7/PQ18/PR20/PR26/PR23 and PR19 are only for YONAH CPU.
A
Compal Electronics, Inc.
TRANSITION TIMING:
(a): START-UP and SHUTDOWN(SUS=LOW,RUNPWROK=LOW):2mV/us
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
(b): ENTER SUSPEND (SUS=HIGH,RUNPWROK=HIGH): 8.6mV/us
(c): EXIT SUSPEND (SUS=LOW, RUNPWROK=HIGH): 24.7mV/us
Size
Date:
8
2
PC54
10U_1210_25V7K~D
PC57
10U_1210_25V7K~D
1
2
PC56
10U_1210_25V7K~D
1
2
PQ3
IRF7832_SO8~D
Change PR82:30.1k. Delete PR22/PQ8/PQ17/PQ7/PQ18/PR20/PR26/PR23
and PR19 for BANIAS and DOTHAN
A
2
1
2
PQ4
IRF7832_SO8~D
1
1
2
1
5
6
7
8
31
MAX1987ETM_TQFN48~D
2
1
PL6
0.7U_ETQP2H0R7BFL_29A_20%~D
D
D
D
D
13
2
PR21
2.2_0603_5%~D
16
DD0#
37
2
1
PQ17
@ 2N7002_SOT23~D
2
PR27
100K_0402_1%~D
NEG
POS
PR5
1.24K_0603_1%~D
15
1
2
PR82
30.1K_0402_1%~D
1
PR19
36K_0402_5%
GND
1
PR23
@ 100K_0402_1%~D
+3VRUN
@
TIME
PQ8
@ 2N7002_SOT23~D
3
2
<6> CLK_ENABLE#
1
1
1
S
G
PQ20
IRF7821_S08~D
2
D
2
PR25
@ 0_0402_5%~D
39
40
38
41
TON
PR6
100K_0402_1%~D
1
1
3
2
1
@
DPRSLPVR
DHS
LXS
DLS
BSTS
ILIM
PQ7
@ 2N7002_SOT23~D
G
<22>
2
1
2
PR20
15K_0402_1%~D
1
2
PR3
100K_0402_1%~D
1
S
2
PR26
0_0402_5%~D
REF
2
1
2
1
1
+3VRUN
D
3
PBOOT voltage seeting up on 1.212V
@
@
PR22
@ 100K_0402_1%~D
2
1
PQ19
PR95
0_0603_5%~D
PGND
1
PC47
100P_0402_50V8K~D
PR7
20.5K_0402_1%~D
11
2
2
1
2
1
2
2
@
1
1
2
@
@
PR72
0_0402_5%~D
1
PR13
0_0402_5%~D
PR74
0_0402_5%~D
1
2
2
PC2
0.22U_0603_16V7K~D
1
PC42
270P_0402_25V8K~D
2
PR15
0_0402_5%~D
10
PD3
EC31QS04~D
CPU_PWR_SRC
PC72
0.01U_0402_25V7K~D
2
PC58
10U_1210_25V7K~D
1
2
PR105
1K_0402_1%~D
PC59
10U_1210_25V7K~D
SHDN#
1
1
2
2
1
PR2
1M_0402_1%~D
PC55
10U_1210_25V7K~D
17
PD4
EC31QS04~D
CCI
SUS
1
DPSLP#
2
PR103
1K_0402_1%~D
PC6
0.1U_0603_25V7K~D
MAX1987_REF
1
D
D
D
D
G
S
S
S
4
3
2
1
19
PC43
470P_0402_50V7K~D
0_0402_5%~D
14
PR18
0_0402_5%~D
@
5
6
7
8
5
6
7
8
5
6
7
8
D
D
D
D
1
2
E
OAINPSI#
1
PR4
2
PR106
1K_0402_1%~D
2
<18,35,39,43> RUNPWROK
1
1
2
20
IRF7821_S08~D
@
4
3
2
1
2
2
PR10
2.2_0603_5%~D
1
4
3
2
1
OAIN+
B2
B1
B0
2
0_0402_5%~D
2
PC64
2200P_0402_50V7K~D
PR84
9
1
PC61
0.1U_0603_25V7K~D
DPRSLPVR
1
+VCC_CORE
5
6
7
8
2
1
2
1
<22>
43
0_0402_5%~D
PR110
2
F
PR102
1K_0402_1%~D
2
44
1
PR83
2
1
PR12
0_0402_5%~D
PR14
0_0402_5%~D
2
@
2
<6,22> H_STP_CPU#
+VCC_CORE
2
5
6
7
8
21
PR85
0_0402_5%~D
@
S2
S1
S0
1
3.01K_0402_1%~D
48
47
D
D
D
D
1
PR1 @ 0_0402_5%~D
45
46
Remote Vcore sense
CSP
CSN
PR28
0.001_2512_5%~D
1
@
G
S
S
S
2
H_PSI#
CMP
CMN
D5
D4
D3
D2
D1
D0
1
<8>
MAX1987_VCC
2
G
S
S
S
D
D
D
D
4
3
2
1
G
S
S
S
5
4
3
PQ6
IRF7832_SO8~D
4
3
2
1
PR71
0_0402_5%~D
CLKEN#
2
1
PQ5
IRF7832_SO8~D
5
6
7
8
25
26
27
28
29
30
8
7
6
1
2
2
D
D
D
D
VID5
VID4
VID3
VID2
VID1
VID0
VID5
VID4
VID3
VID2
VID1
VID0
1
PR17
0_0402_5%~D
PR93
0_0603_5%~D
1
PR67
3.01K_0402_1%~D
24
<6> CLK_ENABLE#
<8>
<8>
<8>
<8>
<8>
<8>
2
1
36
IMVPOK
CPU_PWR_SRC
42
32
34
33
35
1
G
G
S
S
S
23
V+
BSTM
DHM
LXM
DLM
SYSOK
2
PL7
0.7U_ETQP2H0R7BFL_29A_20%~D
PC4
0.1U_0603_25V7K~D
<10,22,39> IMVP_PWRGD
VDD
12
VCC
22
1
Output Capatitors in H/W, ESR=3m ohms
1
<43> VCCP_PWRGD
2
PWR_SRC
2
2
1
1
2
2
1
2
PR88
10K_0402_1%~D
PU3
PQ21
IRF7821_S08~D
1
1
PD1
RB751V-40_SOD323~D
1
2
PR8
0_0402_5%~D
PR65
10K_0402_1%~D
1
2
@
PR66
1.91K_0603_1%~D
PR64
10K_0402_5%~D
2
The C4 Mode voltage
is 0.748V, S2 open
PC44
1U_0603_10V6K~D
1
+3VRUN
PC5
10U_1206_6.3V7K~D
MAX1987_VCC
MAX1987_VCC
PQ22
IRF7821_S08~D
D
D
D
D
5
6
7
8
1
2
PR63
10_0805_5%~D
+5VRUN
PC63
2200P_0402_50V7K~D
PC60
0.1U_0603_25V7K~D
2
+5VRUN
PR9
@ 0_0402_5%~D
H
CPU_PWR_SRC
0.956
0.748
1
0
2
1
2
1
1
1
3
C
2
2
1
MAX1987_REF
D
3
0.1U_0603_25V7K~D
PC62
1
PR79
0_0402_5%~D
E
4
V
0
1
F
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G
5
Vcore
VID 5 VID 4 VID 3 VID 2 VID 1 VID 0
H
6
7
6
5
4
3
2
+VCORE
Document Number
Rev
0.2
LA-2171
,
12, 2004
46
Sheet
1
of
50
5
4
3
2
1
+DC_IN discharge path
+SDC_IN
A
1
8
7
6
5
1
2
1
2
PC101
10U_1210_25V7K~D
PC100
10U_1210_25V7K~D
4
D
1
PDL
2
1
PR77
@ 0_0402_5%~D
PC102
10U_1210_25V7K~D
S
PC88
0.1U_0805_50V7M~D
1
2
PQ11
2N7002_SOT23~D
2
PQ13
2
PC89
2200P_0402_50V7K~D
2
1
S
SI4825DY_SO8~D
1
2
3
PR150
0_0402_5%~D
1
2
PR139
0_0402_5%~D
1
2
PR81
100K_0402_5%~D
2
1
D
2
G
PQ9
PL19
FBM-L18-453215-900LMA90T_1812~D
PR73
10K_0402_5%~D
2
1
4
PR70
10K_0402_5%~D
1
2
2
G
3
ACAV_IN
PWR_SRC
PR76
0.01_2512_1%~D
1
2
1
2
3
D
1
1
<35>
3
PC46
10U_1210_25V7K~D
2
TM
13
PC122
1500P_0402_50V7K~D
1
2
PR153
10K_0402_1%~D
1
2
Connect GND side of PC150, PC151, PC152 to GND through 1 via.
PR151
59K_0402_1%~D
1
2
PC118
1U_0805_10V7K~D
1
2
12
16
PDL
30
17
2
REF
BATT
PGND
22
@
PQ31
FDS6670S_SO8~D
@
VDD
THM
CSIP
CSIN
INT
SCL
PDL
SDA
VMAX
15
PBAT_SMBCLK <35,42>
14
PBAT_SMBDAT <35,42>
9
2
MAX1535AX_QFN32~D
PR130
280K_0402_1%~D
2
1CHVREF
Adress : 12H
PR159
0_0402_5%~D
1
2
CSIP
CSIN
21
20
TH
PQ33
2
1
2
PC37
10U_1210_25V7K~D
4
1
PC36
10U_1210_25V7K~D
5
6
7
8
5
6
7
8
DLO
23
PC35
10U_1210_25V7K~D
DLO
DAC
PC30
0.1U_0603_25V7K~D
1
2
CCV
26
PD16
EC31QS04~D
1
DHI
I.C.
3
2
1
3
2
1
1
PR127
10K_0402_1%~D
1
2
PR160
2
0_0805_5%~D
CCI
PL12
5.6U_CEP125-5R6MC_8.8A_20%~D
1CHVREF
PR131
102K_0402_1%~D
PC125
0.1U_0603_25V7K~D
1
2
PC109
1U_0805_10V7K~D
2
1
4
19
+VCHGR
PC126
0.1U_0603_25V7K~D
2
1
PR50
0.01_2512_1%~D
1
2
2
11
1
PC127
0.1U_0603_25V7K~D
1
2
8
MAX1535_DAC
24 DLOV
2
+VCHGR
2CHG_CS
1
1
2
3
2
1
MAX1535_CCV
PR163
DLOV
PC115
1000P_0402_50V7K~D
1
2
7
ACOK
CCS
4
MAX1535_LX
PR129
182K_0402_1%~D
1
2
MAX1535_CCI
2
IMAX
6
C
@ SI4835DY_SO8~D
PC108
1U_0603_6.3V6M~D
1
2
ACIN
10
1
32
MAX1535_CCS
CHVREF
+5VALW
PC114
0.1U_0603_25V7K~D
2
1
PC103
PR132
1000P_0402_50V7K~D 10K_0402_5%~D
2
1
2
1
2
PR133
0_0402_5%~D
1
ACAV_IN
PQ26
PQ28
SI4835DY_SO8~D
4
25
DCIN
GND
681K_0402_1%~D
LDO
PZD1
RLZ4.3B_LL34~D
5
6
7
8
SRC
GND
3
5
AC_IN
18
1
PR53
PC124
1U_0805_25V4Z~D
2
1
2
28
DHIV
33_0402_5%~D
27
PDS
Reserver H-side MOSFET
ACAV_IN
1
31
CSSN
PU7
PDS
29
@
2
PC32
0.01U_0402_25V7K~D
1
2
0.1U_0603_25V7M~D
PC123
1
CSSP
PC112
1U_1206_25V7K~D
1
2
PR52
20K_0603_1%~D
2
1
CSSN
@
1
Vin Detector
High 17.859 V
Low 16.988 V
CSSP
2
1
PR51
150K_0603_1%~D
2
PC117
0.1U_0603_25V7M~D
PDS
PC104
0.01U_0402_25V7K~D
2
1
@
@
PR158
0_0402_5%~D
1
2
B
PR128
182K_0402_1%~D
1
2
S
2
G
1
RB751V-40_SOD323~D
D
PR152
10K_0402_1%~D
1
2
1
2
2
1
PD18
<35> CHG_PBATT
3
2N7002_SOT23~D
100K_0402_5%~D
PR154
B
1
2N7002_SOT23~D
PR134
0_0402_5%~D
2
1
C
+DC_IN
PC105
0.01U_0402_25V7K~D
2
1
D
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PQ14 SI4825DY_SO8~D
8
7
6
5
VMAX=2.625V
Maximum charger voltage=13.12V
IMAX=1.6135V
Maximum charger current=8A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
Charger
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
47
of
50
1
DELL CONFIDENTIA
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
1
A
Issue Description
Solution Description
Rev.
Cardbus
10/15/03
Dell
Change cardbus controller to TI PCI4515.
Change U162
M00
18
VGA/B &
DVI CONN.
10/16/03
Dell
Add DVI connector.
Add JDVI
M00
3
25
SATA Bridge
10/16/03
Dell
Add SATA to PATA circuit.
Add page 25
M00
4
28
Subwoofer
10/16/03
Dell
Add subwoofer circuit.
Add page 28
M00
5
40
LED/B
10/16/03
Dell
Removed IR circuit.
Delete U52
M00
10/17/03
Dell
Removed internal MIC circuit.
7
B
Date
2
6
C
31&32
Request
Owner
Title
Amplifier &
Phone JACK
27
31&32
8
33
9
1
10
40
11
22
12
37
13
40
14
32
15
10
16
6
17
7&10
18
36
19
1
20
21
LOM
10/17/03
Dell
Cardbus
10/17/03
Dell
Cover page
10/17/03
Dell
PAD & ME &
spare parts
01/07/04
ICH6(3/4)
01/08/04
01/08/04
LED/B &
TV TUNER
PAD & ME &
spare parts
Compal
X00
Change LAN controller (U164) from 5751M to 4401.
Add pop option for the 5705 like Kapalua/Lindbergh board.
Depop 1394 choke, L142 and pop bypass
resistors, R1025, R1026, R1027, R1028
X00
X00
Change schematic revision from M00 to X00.
X00
For EMI requirement.
Pop CLP4,5,10,11,13 and depop CLP18
X01
Dell
Connected PCIE channel 1 to TV-Tuner connector.
Delete T4,T5,T29,T30 and add C661,C662
X01
Dell
Connected TV tuner signals.
Add C663,C664
X01
Pop H12,H13,H14,H17,H20,H21,H26,H27
X01
01/08/04
Compal
Added ME standoff.
CardBus(2/2)
01/28/04
Compal
Fixed SD card issue.
Alviso(1/5)
01/28/04
Dell
From Intel Message.
Clock Generator
01/28/04
Dell
Per Intel and ICS recommendation.
Connect the SATA clock to SRC4 and connect the VGA clock to SRC1.
X01
01/28/04
Dell
Per the Intel Check list 1.301
Change R397 and R114 to 75 ohm.
X01
Delete JDBUG.
X01
Dothan(1/2)
&Alviso(1/5)
Internal K/B
& LCM CONN.
The pin11 of JSD need to be connected to GND
and pin 12 need to be connected to U17 pin b3.
Change C124 from 220pF to 0.1uF and move capacitor
as close as possible to the HVREF pin (pin J11 of U15).
X01
Compal
The BIOS debug connector is for bring up only.
Cover page
01/29/04
Compal
Change schematic revision from X00 to X01.
35
Macallen(2/2)
01/29/04
Compal
Board ID X01.
Pop R318 and depop R319.
X01
34
Macallen(1/2)
01/29/04
Compal
Reserved a inverter for serial port debug.
Add U36 and T13.
X01
01/30/04
Compal
This clip have interferenced with screw hole.
Delete CLP5 and add H32
X01
02/02/04
Compal
The indicative LED of HDD doesn't work well.
Remove R12 and connect the pin3 of Q2 to +3VRUN.
X01
02/04/04
Dell
Changed JTUNR pin definitions
Added PCIRST#, CLK_PCIE_TV/TV# signals
X01
02/04/04
Dell
Added PCIE clock connection to JTUNR
Added R551, R552, R553, R554
X01
22
40
23
37
24
37
25
6
Clock Generator
C
X01
01/29/04
PAD & ME &
spare parts
LED/B &
TV TUNER
LED/B &
TV TUNER
D
B
X01
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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Changed-List History
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
48
of
50
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
Request
Owner
Issue Description
Solution Description
Rev.
37
LED/B &
TV TUNER
02/05/04
Dell
Changed JTUNR PCIRST# to PLTRST# or PLTRST_DELY# Pop Option
Added R555, R556
X01
27
35
Macallen(2/2)
02/05/04
Dell
Improves the rise time of the SMBUS signals. Allbatteryvendors and
Compal agree to the change per Youseff Dauo.
Change battery SMBUS pullups, R336 and R526, from 22K to 8.2k.
X01
28
5
SMBus Diagram
02/05/04
Dell
Add a SMbus device address table in the Schematic.
13&23
Alviso(4/5)
&ICH6(4/4)
02/05/04
38
Power control
02/06/04
18
VGA/B &
DVI CONN.
02/06/04
30
31
B
Date
26
29
C
Title
Compal
X01
Panasonic has phase out SGA2022114L.
Change C510,C514 from SGA2022114L to SGA2022110L.
X01
Dell
SUSPWROK_5V no longer controls the switching FET for +3VSUS.
Removed R256 and R257.
X01
Dell
Add bulk capacitor to G_PWR_SRC.
Add C647, but nopop.
X01
Add R12,R79 for pop options.
X01
32
27
Subwoofer
02/06/04
Dell
33
37
LED/B &
TV TUNER
Add 0 ohm pop options to make it easier to
switch between both subwoofer amps.
02/06/04
Dell
TV tuner solution for X01 gerber.
Change JTV1,JTV2 and JTUNR pin definitions.
JTV1 is a 8pin MINI DIN CONN.
X01
34
28
02/06/04
Dell
Change the single USB port in the back to dual stack.
Add L14,L17,C88,C87 and change the P/N of JUSB1.
X01
35
39
02/09/04
Dell
Delays 1.5VSUS power good so that it comes up after 1.5VSUS
is completely up.
Change R482 from 330ohm to 10K. Change R490 from 10k to 100K.
X01
36
37
02/09/04
Dell
Add EMI pi-filters for 5 AV signals.
Add L73,L74,L75,L76,L88,C438,C442,C419,C420,C431,C433,C434,C424
,C439,C610
X01
37
38
02/10/04
Dell
Decrease Rdson for +1.5SUS to +1.5RUN switching FET.
Add Q55 and nopop Q35.
X01
Delete RN28 and RN29.
X01
Added R90, R91 (0 ohm pop option)
X01
Added R87~R89, Q31, Q34, Q48
X01
Change the P/N of JDVI
X01
38
35
39
22
40
USB 2.0 PORT
Power
Sequence
LED/B &
TV TUNER
Power control
Macallen(2/2)
Backout workaround for SMSC errata item. Connect
CLK_SM2 and DAT_SM2 appropriately.
SIO_EXT_WAK# signal leakage to +3VRUN via GPI12 of
ICH6M when system is into S3 status.
Add drain FETs for +1.5VSUS and +1.8VSUS. FETs to drain power
plane when system is turned off.
ME team decided to use JAE DVI-I connector (with shielding) instead of
Suyin DVI-D connector (without shielding) for EA/SST build this time.
02/11/04
Dell
ICH6(3/4)
02/11/04
Dell
38
Power control
02/11/04
Dell
41
18
VGA/B &
DVI CONN.
02/11/04
Dell
42
35
Macallen(2/2)
02/11/04
Compal
System auto power on issue.
Change C609 from 1uF to 0.1uF and R504 from 100K to 10K ohm.
X01
02/11/04
Compal
Reduce the pad width by compal's DFX requirement.
Change the footprint of Q13,Q19,Q21,Q28,Q35,Q47,Q52,Q7
X01
43
D
C
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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Changed-List History
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
49
of
50
5
4
3
2
1
Version Change List ( P. I. R. List ) for Power Circuit
Item Page#
D
C
1
49
Title
Charger selector
Date
2003/10/14
Request
Owner
Compal
Issue Description
Modify charger selector circuit.
Solution Description
Rev.
Need to discuss.
0.0
Add ESD solution on PSID, and limit RTC charge current.
0.0
X00
2
42
PSID & +3VX
2003/10/15
Compal
Modify PSID circuit same as Nimitas. And add current limit resistor on
RTC charger.
3
44
+15VP
2003/11/4
Compal
+15VP current rating is not enough for subwoofer
Use MB3800 Boost IC to genearte +15VP from +5VSUSP
That has leakage current from battery goes through PQ22 and PQ44 to
DC_IN.
Test +15VP on Demon board.The output ripple voltage is large
and improve efficiency.
Move Adaptor current sense PR144 after PQ24 and before PWR_SRC.
That is same as Nimitaz.
Add PC128 10U_1206_25V,change PQ30 from SI2302DS to SI3442DV,
change PR157 form 392_0603_1% to 150_0603_1%, no-pop PC96.
4
47
Charger
2003/11/5
Compal
5
44
+15VP
2003/12/11
Compal
6
45
+1.8VSUSP
2004/2/1
DELL
Change DDRII DC-DC solution for cost down.
Using MAXIM MAX8550 .
X01
2004/2/1
Compal
VCCP_1p05VP has two 330uF caps on it(PC10, PC11), Laguna
only has one. Do we need two?
Can de-populate PC11,and test is OK.
X01
X00
M00
7
43
8
45
+1.8VSUSP
2004/2/5
Compal
Voltage divider setting is error, the FB regulate on 0.7V.
Change PR116 from 45.3K_0402_1% to 27.4K_0603_1%.
Change PC22 from 1U_0603_6.3V to 4.7U_0805_6.3V
X01
9
46
+VCC_CORE
2004/2/5
Compal
Choke height is over mechnical height limitation
Change PL6 and PL7 from 0.6U_HK_AE26A0R6 to 0.7U_ETQP2H0R7BFL.
X01
10
46
+VCC_CORE
2004/2/6
Compal
EMI broad band test is over 1~2 db
Change PR10 and PR21 from 0_0603_5% to 2.2_0603_5%.
X01
11
41
PS_ID
2004/2/11
DELL
Open issue #60 Change PS_ID pullup resistor, PR78, from 1.5K to 2.2K
Change PR78 from 1.5K_0603_1% to 2.2K_0402_5%.
X01
DELL
Open issue#63 Please add a 10uf, 1206 package capacitor at the output
Add and reserve PC131 10U_1206_6.3V7K.
of PU5 pin 12, +0.9V_DDR_VTTP.
12
45
+VCCP_1P05VP
+0.9V_DDR_VTTP
2004/2/11
D
C
X01
13
14
15
16
B
17
B
18
19
20
21
22
23
24
A
25
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size
Date:
5
4
3
2
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Power-Changed-List History
Document Number
Rev
0.2
LA-2171
,
12, 2004
Sheet
1
50
of
50
www.s-manuals.com
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