Compal LA 4231P Schematics. Www.s Manuals.com. R0.2 Schematics
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A B C D E 1 1 Compal Confidential 2 2 Schematic Document Crestline + ICH8 2007 / 11 / 14 Rev:0.2 3 3 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/1/15 2008/1/15 Deciphered Date Title Cover Sheet THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: A B C D Sheet Thursday, January 10, 2008 E 1 of 49 A B C D E SMB 13.3 Compal confidential File Name : LA-4231P ZZZ1 1 Thermal Sensor ADM1032ARMZ PCB Mobile Merom 1 uFCPGA-478 CPU P.4 P.4,5,6 CRT TSSOP-64 CK505 P.15 Fan conn P.4 H_A#(3..35) Clock Generator ICS 9LPRS365 FSB H_D#(0..63) 667/800MHz 1.05V LVDS Panel Interface DDR2 667MHz 1.8V P.15 Intel Crestline MCH nVidia NB8M-GS VRAM x 2 BANK 0, 1, 2, 3 P.13,14 Dual Channel FCBGA 1299 P.34,35,36,37 P.38 P.16 DDR2-SO-DIMM X2 USB conn x 4 P.7,8,9,10,11,12 P.32 2 2 PCI CardBus Controller O2MICRO OZ129 DMI X4 FingerPrinter C-Link Felica Conn P.40 USB2.0 1394 Intel ICH8 Media Card mBGA-676 PCI-E BUS Azalia Mini-Card-1 (WLAN) Mini-Card-2 P.24 BT Conn SATA Slave P.32 Camera Express Card P.24 P.32 SATA Master P.17,18,19,20 10/100/1000 LAN REALTEK P.22 RTL8111C-GR P.32 Mic P.32 Express Card P.28 P.28 3 3 Mini-Card-2 P.24 RJ45/11 CONN LPC BUS Audio CKT ALC268 AMP & Audio Jack P.25 P.26 ENE KB926 TPM CONN P.29 SATA HDD Connector P.29 Touch Pad CONN. Power On/Off CKT. P.31 Int.KBD P.31 P.21 BIOS(System/EC) P.29 CDROM Conn. P.21 4 DC/DC Interface CKT. 4 RTC CKT. P.18 Compal Secret Data Security Classification Power Circuit DC/DC Power OK CKT. 2007/1/15 Issued Date 2008/1/15 Deciphered Date Title Compal Electronics, Inc. Block diagram THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: A B C D Sheet Thursday, January 10, 2008 E 2 of 49 A Voltage Rails B O MEANS ON C D X MEANS OFF SIGNAL STATE +3VS +1.8VS +B 1 +1.5VS +5VALW +3V +3VALW +1.8V CLOCK +1.25VS +CPU_CORE State +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Full ON +5VS power plane SLP_S1# SLP_S3# SLP_S4# SLP_S5# E 1 +VCCP Board ID Table for AD channel S0 O O O O O S3 O O O X O S5 S4/AC O O X X O S5 S4/ Battery only O X X X X S5 S4/AC & Battery don't exist X X X X X Vcc Ra / Rc Board ID 0 1 2 3 4 5 6 7 3.3V +/- 5% 100K +/- 5% Rb / Rd 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V 2 2 BOARD ID Table O MEANS ON S3 : STR S4 : STD S5 : SOFT OFF X MEANS OFF External PCI Devices 3 Device IDSEL# CardBus AD21 REQ#/GNT# 0 EC SM Bus1 address Interrupts PIRQE/PIRQF/PIRQG Board ID 0 1 2 3 4 5 6 7 PCB Revision 0.1 0.2 BTO Option Table BTO Item BOM Structure EC SM Bus2 address Device Address Device Address Smart Battery 0001 011X b? ADM1032 4D 3 EEPROM(24C16/02) 1010 000X b? (24C04) 1011 000Xb? ICH7 SM Bus address Device Address Clock Generator (ICS ICS9LPR310) 1101 001Xb? DDRII DIMM0 1001 000Xb? DDRII DIMM2 1001 010Xb? 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/1/15 2008/1/15 Deciphered Date Title Notes THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: A B C D Sheet Thursday, January 10, 2008 E 3 of 49 5 4 3 2 1 XDP Reserve H_A#[3..16] JP2A H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#[17..35] H_ADSTB#1 18 18 18 H_A20M# H_FERR# H_IGNNE# 18 18 18 18 H_STPCLK# H_INTR H_NMI H_SMI# K3 H2 K2 J3 L1 REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 A20M# FERR# IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# D5 C6 B4 A3 STPCLK# LINT0 LINT1 SMI# M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] H_DEFER# H_DRDY# H_DBSY# F1 H_BR0# IERR# INIT# D20 B3 H_IERR# H_INIT# LOCK# H4 H_LOCK# RESET# RS[0]# RS[1]# RS[2]# TRDY# C1 F3 F4 G3 G2 H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# HIT# HITM# G6 E4 H_HIT# H_HITM# BR0# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# H_A20M# H_FERR# H_IGNNE# H5 F21 E1 DEFER# DRDY# DBSY# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# PROCHOT# THERMDA THERMDC THERMTRIP# H_PROCHOT# H_THERMDA H_THERMDC C7 H_THERMTRIP# A22 A21 CLK_CPU_BCLK CLK_CPU_BCLK# +VCCP H_DEFER# 7 H_DRDY# 7 H_DBSY# 7 H_BR0# D21 A24 B25 H CLK BCLK[0] BCLK[1] H_ADS# 7 H_BNR# 7 H_BPRI# 7 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 THERMAL ICH 7 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADS# H_BNR# H_BPRI# CONTROL 7 7 7 7 7 7 H1 E2 G5 ADS# BNR# BPRI# XDP/ITP SIGNALS H_ADSTB#0 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# ADDR GROUP 1 C 7 J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 ADDR GROUP 0 D H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0 H_INIT# 7 R89 56_0402_5% 2 1 2 150_0402_1% R171 1 2 39_0402_1% XDP_BPM#5 R362 1 2 54.9_0402_1% @ XDP_TRST# R182 1 2 560_0402_5% XDP_TCK R170 1 2 27_0402_5% D +VCCP 18 H_RESET# 7 H_RS#0 7 H_RS#1 7 H_RS#2 7 H_TRDY# 7 H_HIT# 7 H_HITM# 7 T28 T27 T48 T29 T47 T33 XDP_DBRESET# 19 2 R114 1 56_0402_5% +VCCP C FAN1 Control and Tachometer H_THERMTRIP# 7,18 CLK_CPU_BCLK 16 CLK_CPU_BCLK# 16 C76 10U_1206_16V4Z~N 2 1 +5VS C69 1000P_0402_50V7K~N 2 1 1 1 2 3 4 FAN1_POWER 29 EN_DFAN1 EN_DFAN1 +3VS @ 56_0402_5% 1 2 2 B E 19 VEN VIN VO VSET GND GND GND GND 8 7 6 5 40mil R61 10K_0402_5% H_RESET# JFAN1 B 1 2 3 1 2 3 4 5 GND GND 2 C OCP# 2 10U_1206_16V4Z~N RT9027BPS SO 8P +VCCP @ R41 54.9_0402_1% 1 2 1 U3 Merom Ball-out Rev 1a conn@ 3 1 OCP# @ Q11 MMBT3904_SOT23 C77 Add on 1003 R108 H_PROCHOT# R172 1 XDP_TMS H_LOCK# 7 H_THRMTRIP# should connect to ICH8 and GMCH without T-ing (No stub) +VCCP B XDP_TDI H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil RESERVED 7 29 FAN_SPEED1 C94 0.01U_0402_16V7K 2 ACES_85205-03001 conn@ 1 FAN1 Thermal Sensor EMC1402-1-ACZL-TR +3VS 2 1 C424 0.1U_0402_16V4Z~N R354 @ 10K_0402_5% 1 1 VDD 8 EC_SMB_CK2 H_THERMDA 2 D+ SDATA 7 EC_SMB_DA2 H_THERMDC 3 D- ALERT# 6 THERM_SCI# 2200P_0402_50V7K~N THERM# 4 THERM# GND 5 C423 1 2 A SCLK 2 U2 @ 2 1 R355 0_0402_5% EC_THERM# 19,29 A R350 +3VS 1 2 10K_0402_5% EMC1402-2-ACZL-TR MSOP 8P Address:100_1100 29,31,35 EC_SMB_CK2 29,31,35 EC_SMB_DA2 EC_SMB_CK2 EC_SMB_DA2 2007/1/15 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/1/15 Deciphered Date Title Merom(1/3)-AGTL+/XDP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Rev 0.1 Sheet Thursday, January 10, 2008 1 4 of 49 4 3 2 1 +CPU_CORE 2 @ 1K_0402_5% 2 @ 1K_0402_5% T14 T13 T49 T15 1 1 AD26 C23 D25 C24 AF26 AF1 A26 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 16 16 16 B22 B23 C21 BSEL[0] BSEL[1] BSEL[2] CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 COMP[0] COMP[1] COMP[2] COMP[3] R26 U26 AA1 Y1 COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI# MISC Merom Ball-out Rev 1a conn@ layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs B CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 166 0 1 1 200 0 1 0 H_DSTBN#3 7 H_DSTBP#3 7 H_DINV#3 7 H_DPRSTP# 7,18,49 H_DPSLP# 18 H_DPWR# 7 H_PWRGOOD 18 H_CPUSLP# 7 H_PSI# 49 Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils. VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCA[01] VCCA[02] B26 C26 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] AD6 AF5 AE5 AF4 AE3 AF3 AE2 VCCSENSE AF7 VCCSENSE VCCSENSE 49 VSSSENSE AE7 VSSSENSE VSSSENSE 49 Merom Ball-out Rev 1a conn@ D +VCCP C 1 C140 + 2 330U_V_2.5VM CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 49 49 49 49 49 49 49 1 2 1 2 +1.5VS 0.01U_0402_16V7K~N R91 R90 H_DSTBN#1 H_DSTBP#1 H_DINV#1 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 H_DSTBN#2 7 H_DSTBP#2 7 H_DINV#2 7 H_D#[48..63] 7 A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 C412 7 7 7 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 JP2C R88 27.4_0402_1% 2 1 V_CPU_GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 C D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# +CPU_CORE 7 R87 54.9_0402_1% 2 1 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2 R173 27.4_0402_1% 2 1 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 DATA GRP 2 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[16..31] DATA GRP 1 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# DATA GRP 0 E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 D 7 7 7 7 H_D#[32..47] JP2B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 R174 54.9_0402_1% 2 1 H_D#[0..15] DATA GRP 3 7 10U_0805_10V4Z~N C409 5 Near pin B26 B . Length match within 25 mils. The trace width/space/other is 20/7/25. 1 +VCCP R86 1K_0402_1% 2 +CPU_CORE R359 100_0402_1% 2 VCCSENSE R360 100_0402_1% 1 2 VSSSENSE 1 1 V_CPU_GTLREF 2 R85 2K_0402_1% Close to CPU pin AD26 within 500mils. Close to CPU pin within 500mils. A A 2007/1/15 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/1/15 Deciphered Date Title Merom(2/3)-AGTL+/PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Sheet Thursday, January 10, 2008 1 5 of 49 5 4 3 2 1 High Frequence Decoupling 10uF 0805 X5R -> 85 degree. Place these caps inside the CPU socket. +CPU_CORE Place these caps inside the CPU socket cavity. 1 ( Left side on Top ). 2 1 C1150 10U_0805_6.3V6M 1 C1151 10U_0805_6.3V6M 2 1 C1152 10U_0805_6.3V6M 2 1 C1153 10U_0805_6.3V6M 2 1 C1154 10U_0805_6.3V6M 2 2 1 C1155 10U_0805_6.3V6M 2 1 C1156 10U_0805_6.3V6M 2 1 C1157 10U_0805_6.3V6M 2 1 C1158 10U_0805_6.3V6M ( Left side on Top ). C1159 10U_0805_6.3V6M 2 D D JP2D C B A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] Merom Ball-out Rev 1a conn@ 1 ( Right side on Top side). 2 1 C1160 10U_0805_6.3V6M 1 C1161 10U_0805_6.3V6M 2 1 C1162 10U_0805_6.3V6M 2 1 C1163 10U_0805_6.3V6M 2 1 C1164 10U_0805_6.3V6M 2 2 1 C1165 10U_0805_6.3V6M 2 1 C1166 10U_0805_6.3V6M 2 1 C1167 10U_0805_6.3V6M 2 1 C1168 10U_0805_6.3V6M ( Right side on Top ). 2 C1169 10U_0805_6.3V6M +CPU_CORE Place these caps inside the CPU socket cavity. 1 ( Left side on Bottom ). 2 1 C1170 10U_0805_6.3V6M 1 C1171 10U_0805_6.3V6M 2 1 C1172 10U_0805_6.3V6M 2 1 C1173 10U_0805_6.3V6M 2 1 C1174 10U_0805_6.3V6M 2 2 C1175 10U_0805_6.3V6M C +CPU_CORE Place these caps inside the CPU socket cavity. 1 ( Right side on Bottom ). 2 1 C1176 10U_0805_6.3V6M 1 C1177 10U_0805_6.3V6M 2 1 C1178 10U_0805_6.3V6M 2 1 C1179 10U_0805_6.3V6M 2 1 C1180 10U_0805_6.3V6M 2 2 C1181 10U_0805_6.3V6M ESR <= 1.5m ohm Capacitor > 1980uF Near CPU CORE regulator +CPU_CORE B 1 C190 1 + C429 @ 2 + 1 C207 2 1 + C426 2 + 2 330U_V_2.5VM330U_V_2.5VM330U_V_2.5VM 330U_V_2.5VM Place these inside socket cavity on L8 (North side Secondary) +VCCP 1 . 1 + 2 220U_D2_4VY_R15M C212 A Place these caps inside the CPU socket. +CPU_CORE Place these caps inside the CPU socket cavity. 2 1 C210 0.1U_0402_10V6K 2 C209 0.1U_0402_10V6K 1 2 C208 0.1U_0402_10V6K 1 2 1 C185 0.1U_0402_10V6K 2 1 C183 0.1U_0402_10V6K 2 C184 0.1U_0402_10V6K A 2007/1/15 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/1/15 Deciphered Date Title Merom(3/3)-GND&Bypass THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Rev 0.1 Sheet Thursday, January 10, 2008 1 6 of 49 H_VREF M14 E13 A11 H13 B12 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#_0 H_RS#_1 H_RS#_2 E12 D7 D8 H_RS#0 H_RS#1 H_RS#2 1 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 R82 PM_EXTTS#0 5 5 5 5 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 5 5 5 5 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 4 4 4 4 4 H_RS#0 H_RS#1 H_RS#2 4 4 4 R83 PM_EXTTS#1 2 1 10K_0402_5% 16 MCH_CLKSEL0 16 MCH_CLKSEL1 16 MCH_CLKSEL2 PAD PAD 9 CFG5 PAD 9 CFG7 9 CFG8 9 CFG9 PAD PAD 9 CFG12 9 CFG13 PAD PAD 9 CFG16 PAD PAD 9 CFG19 9 CFG20 MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 T8 T9 CFG5 T37 CFG7 CFG9 T38 T40 CFG12 CFG13 T10 T4 CFG16 T5 T39 CFG19 CFG20 PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_POK_R PLT_RST#_R THERMTRIP# DPRSLPVR 19 PM_BMBUSY# 5,18,49 H_DPRSTP# 13 PM_EXTTS#0 14 PM_EXTTS#1 R56 0_0402_5% 2 1 19,49 DPRSLPVR +1.8V 1 2 0.1U_0402_16V4Z~N C386 2 1 R43 1K_0402_1% 1 2 2 C66 0.1U_0402_16V4Z~N 1 1 R323 2 221_0603_1% 2 R322 within 100 mils from NB H_SWNG 100_0402_1% 2 H_RCOMP R324 24.9_0402_1% 2 1 1 C391 1 R45 1K_0402_1% 2 1 R46 2 2K_0402_1% +DDR_MCH_REF G41 L39 L36 J36 AW49 AV20 N20 G36 19,29,49 VGATE BG20 BK16 BG16 BE13 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 BH18 BJ15 BJ14 BE16 M_ODT0 M_ODT1 M_ODT2 M_ODT3 SM_RCOMP SM_RCOMP# BL15 BK14 SMRCOMP SMRCOMP# SM_RCOMP_VOH SM_RCOMP_VOL BK31 BL31 SMRCOMP_VOH SMRCOMP_VOL SM_VREF_0 SM_VREF_1 AR49 AW4 MUXING CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC R42 1K_0402_1% +VCCP P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35 BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2 1 Layout Note: +DDR_MCH_REF trace width and spacing is 20/20. 1 10K_0402_5% 5 5 5 5 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 2 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 DDR 1K_0402_1% +3VS Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces A SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 CRESTLINE_1p0 2 1 @ R101 0_0402_5% 17,19,22,24,28,29,34 PLT_RST# PLT_RST# 1 R111 2007/1/15 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# 13 13 14 14 R329 D 13 13 14 14 +1.8V 1 20_0402_1% 1 20_0402_1% 2 2 +DDR_MCH_REF CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK# PEG_CLK PEG_CLK# K44 K45 CLK_MCH_3GPLL CLK_MCH_3GPLL# DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 AN47 AJ38 AN42 AN46 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 AM47 AJ39 AN41 AN45 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 AJ46 AJ41 AM40 AM44 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 AJ47 AJ42 AM39 AM43 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 CLK_MCH_DREFCLK 16 CLK_MCH_DREFCLK# 16 MCH_SSCDREFCLK 16 MCH_SSCDREFCLK# 16 CLK_MCH_3GPLL 16 CLK_MCH_3GPLL# 16 C GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VR_EN E35 A39 C38 B39 E36 T12 T42 T41 T16 T11 PAD PAD PAD PAD PAD DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 19 19 19 19 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 19 19 19 19 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 19 19 19 19 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 19 19 19 19 R678 CLK_MCH_DREFCLK 2 R679 CLK_MCH_DREFCLK# 2 R680 MCH_SSCDREFCLK 2 R681 MCH_SSCDREFCLK# 2 0_0402_5% VGA@ 1 0_0402_5% VGA@ 1 0_0402_5% VGA@ 1 0_0402_5% VGA@ 1 CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF AM49 AK50 AT43 AN49 AM50 CL_CLK0 CL_DATA0 M_PWROK CL_RST# CL_VREF R100 CL_CLK0 19 CL_DATA0 19 M_PWROK 19 CL_RST# 19 1K_0402_1% CL_VREF C181 0.1U_0402_16V4Z~N 12 mil SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# H35 K36 G39 G40 TEST_1 TEST_2 A37 R32 1 R99 392_0402_1% 2 CLKMCHREQ# MCH_ICH_SYNC# UMA@ R77 PM_POK_R 1 0_0402_5% CLKMCHREQ# 16 MCH_ICH_SYNC# 19 R84 0_0402_5% A 2 PLT_RST#_R 100_0402_5% Compal Electronics, Inc. 2008/1/15 Deciphered Date Title CRESTLINE(1/6)-AGTL+/DMI/DDR2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 B +1.25VM_AXD Compal Secret Data Security Classification Issued Date 2 R102 13 13 14 14 R328 20K_0402_5% 19,29 PM_PWROK 13 13 14 14 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB M_ODT0 M_ODT1 M_ODT2 M_ODT3 B42 C42 H48 H47 close to NB Near B3 pin M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# CLK H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPRI# 4 H_BR0# 4 H_DEFER# 4 H_DBSY# 4 CLK_MCH_BCLK 16 CLK_MCH_BCLK# 16 H_DPWR# 5 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4 4,18 H_THERMTRIP# 0.1U_0402_16V4Z~N H_VREF DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB DMI 1 R333 13 DDR_A_MA14 14 DDR_B_MA14 UMA@ +VCCP BE29 AY32 BD39 BG37 2 2 H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BJ29 BE24 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34 2 2 1 C404 1 0.01U_0402_25V7K~N SMRCOMP_VOL layout note: Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20 SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4 R332 3.01K_0402_1% NA lead free H_AVREF H_DVREF CRESTLINE_1p0 1 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 2 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 C400 L7 K2 AC2 AJ10 2.2U_0603_106K C398 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 PM B9 A9 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 AW30 BA23 AW25 AW23 13 13 14 14 1 B H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 M7 K3 AD2 AH11 SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 2 H_CPURST# H_CPUSLP# H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 1 B6 E5 K5 L2 AD13 AE13 AV29 BB23 BA25 AV23 2 H_RESET# H_CPUSLP# H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 1K_0402_1% SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4 1 H_SCOMP H_SCOMP# H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# 1 SMRCOMP_VOH R331 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 1 W1 W2 G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7 1 2 +1.8V 2 H_SWING H_RCOMP H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# 2 P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20 2 H_RESET# H_CPUSLP# B3 C2 H_SCOMP H_SCOMP# H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 GRAPHICS VID R326 54.9_0402_1% 2 1 H_SWNG H_RCOMP J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19 CFG R325 54.9_0402_1% 2 1 +VCCP H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 ME C H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 2.2U_0603_106K C403 D E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13 1 For Crestline: 20ohm For Calero: 80.6ohm RSVD H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 2 U4B 0.01U_0402_25V7K~N U4A H_D#[0..63] 4 5 3 H_A#[3..35] 4 HOST 5 4 MISC 5 2 Sheet Thursday, January 10, 2008 1 7 of 49 5 4 3 2 1 D D 14 DDR_B_D[0..63] B DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 SA_CAS# BL17 DDR_A_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 SA_RAS# SA_RCVEN# BE18 AY20 DDR_A_RAS# SA_RCVEN# SA_WE# BA19 DDR_A_WE# DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDR_A_BS#0 13 DDR_A_BS#1 13 DDR_A_BS#2 13 DDR_A_CAS# 13 DDR_A_DM[0..7] 13 DDR_A_DQS[0..7] DDR_A_DQS#[0..7] DDR_A_MA[0..13] 13 13 13 DDR_A_RAS# 13 T6 DDR_A_WE# 13 CRESTLINE_1p0 AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 SB_BS_0 SB_BS_1 SB_BS_2 B BB19 BK19 BF29 MEMORY A SA_BS_0 SA_BS_1 SA_BS_2 MEMORY SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SYSTEM C AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11 DDR DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 U4E SYSTEM U4D DDR 13 DDR_A_D[0..63] AY17 BG18 BG36 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 SB_CAS# BE17 DDR_B_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 SB_RAS# SB_RCVEN# AV16 AY18 DDR_B_RAS# SB_RCVEN# SB_WE# BC17 DDR_B_WE# DDR_B_BS#0 14 DDR_B_BS#1 14 DDR_B_BS#2 14 DDR_B_CAS# 14 DDR_B_DM[0..7] 14 DDR_B_DQS[0..7] 14 DDR_B_DQS#[0..7] 14 C DDR_B_MA[0..13] 14 DDR_B_RAS# 14 T7 DDR_B_WE# 14 B CRESTLINE_1p0 A A 2007/1/15 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/1/15 Deciphered Date Title CRESTLINE((2/6)-DDR2 A/B CH THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Sheet Thursday, January 10, 2008 1 8 of 49 5 4 3 2 For Crestline:2.4kohm For Calero: 1.5Kohm PEGCOMP trace width and spacing is 20/25 mils. U4C 2 R94 1 2.4K_0402_1% D GMCH_LVDSACGMCH_LVDSAC+ 15 GMCH_LVDSAC15 GMCH_LVDSAC+ GMCH_LVDSA0GMCH_LVDSA1GMCH_LVDSA2- 15 GMCH_LVDSA0+ 15 GMCH_LVDSA1+ 15 GMCH_LVDSA2+ GMCH_LVDSA0+ GMCH_LVDSA1+ GMCH_LVDSA2+ G44 B47 B45 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 E44 A47 A45 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 E27 G27 K27 2 2 R65 2 R67 R68 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 TVA_DAC TVB_DAC TVC_DAC F27 J27 L27 TVA_RTN TVB_RTN TVC_RTN M35 P33 TV_DCONSEL_0 TV_DCONSEL_1 3VDDCCL 3VDDCDA CRT_HSYNC 3VDDCCL 3VDDCDA CRT_HSYNC CRT_VSYNC CRT_VSYNC R75 1 2 150_0402_1% UMA@ R76 1 2 150_0402_1% UMA@ CRT_B CRT_G CRT_R H32 G32 K29 J29 F29 E29 CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# K33 G35 F33 C32 E33 CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC 0_0402_5% R675 VGA@ R334 2 2 1 B 1 0_0402_5% R676 VGA@ 1.3K_0402_1% 2 1 15 LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 VGA 15 15 15 G51 E51 F49 CRT_B CRT_G CRT_R R74 1 2 150_0402_1% UMA@ 15 15 15 LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK TV 1 75_0402_1% 1 75_0402_1% 1 75_0402_1% C L41 L43 N41 N40 D46 C45 D44 E42 G50 E50 F48 PEGCOMP R95 24.9_0402_1% 1 2 +VCCP PEG_COMPI PEG_COMPO N43 M43 PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41 PEG_NRX_GTX_N0 PEG_NRX_GTX_N1 PEG_NRX_GTX_N2 PEG_NRX_GTX_N3 PEG_NRX_GTX_N4 PEG_NRX_GTX_N5 PEG_NRX_GTX_N6 PEG_NRX_GTX_N7 PEG_NRX_GTX_N8 PEG_NRX_GTX_N9 PEG_NRX_GTX_N10 PEG_NRX_GTX_N11 PEG_NRX_GTX_N12 PEG_NRX_GTX_N13 PEG_NRX_GTX_N14 PEG_NRX_GTX_N15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42 PEG_NRX_GTX_P0 PEG_NRX_GTX_P1 PEG_NRX_GTX_P2 PEG_NRX_GTX_P3 PEG_NRX_GTX_P4 PEG_NRX_GTX_P5 PEG_NRX_GTX_P6 PEG_NRX_GTX_P7 PEG_NRX_GTX_P8 PEG_NRX_GTX_P9 PEG_NRX_GTX_P10 PEG_NRX_GTX_P11 PEG_NRX_GTX_P12 PEG_NRX_GTX_P13 PEG_NRX_GTX_P14 PEG_NRX_GTX_P15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44 PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 C568 C537 C538 C539 C540 C541 C542 C543 C544 C545 C546 C547 C548 C549 C550 C551 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N0 PEG_NTX_GRX_N1 PEG_NTX_GRX_N2 PEG_NTX_GRX_N3 PEG_NTX_GRX_N4 PEG_NTX_GRX_N5 PEG_NTX_GRX_N6 PEG_NTX_GRX_N7 PEG_NTX_GRX_N8 PEG_NTX_GRX_N9 PEG_NTX_GRX_N10 PEG_NTX_GRX_N11 PEG_NTX_GRX_N12 PEG_NTX_GRX_N13 PEG_NTX_GRX_N14 PEG_NTX_GRX_N15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43 PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15 C552 C553 C554 C555 C556 C557 C558 C559 C560 C561 C562 C563 C564 C565 C566 C567 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P0 PEG_NTX_GRX_P1 PEG_NTX_GRX_P2 PEG_NTX_GRX_P3 PEG_NTX_GRX_P4 PEG_NTX_GRX_P5 PEG_NTX_GRX_P6 PEG_NTX_GRX_P7 PEG_NTX_GRX_P8 PEG_NTX_GRX_P9 PEG_NTX_GRX_P10 PEG_NTX_GRX_P11 PEG_NTX_GRX_P12 PEG_NTX_GRX_P13 PEG_NTX_GRX_P14 PEG_NTX_GRX_P15 Strap Pin Table 010 = FSB 800MHz PEG_NRX_GTX_N[0..15] 34 LVDS 15 GMCH_LVDSA015 GMCH_LVDSA115 GMCH_LVDSA2- L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN GRAPHICS 1 1 15 GMCH_EDID_CLK_LCD 15 GMCH_EDID_DAT_LCD 15 GMCH_LVDDEN J40 H39 CTRL_CLK E39 CTRL_DATA E40 C37 D35 K40 PCI-EXPRESS 15 BIA_PWM 15 GMCH_ENBKL R81 +3VS R80 BIA_PWM GMCH_ENBKL 210K_0402_5% UMA@ 210K_0402_5% UMA@ GMCH_EDID_CLK_LCD GMCH_EDID_DAT_LCD GMCH_LVDDEN 1 Others = Reserved D 1 = DMI x 4 CFG6 * Reserved CFG7 (CPU Strap) 0 = Reserved 1 = Mobile CPU PEG_NRX_GTX_P[0..15] 34 1 = Low Power mode 1 = Normal Operation (PCIE Graphics Lane Reversal) CFG[11:10] = Reserved = XOR Mode Enabled = All Z Mode Enabled = Normal Operation(Default) * C Reserved CFG16 (FSB Dynamic ODT) 0 = Disabled 1 = Enabled CFG[18:17] * Reserved 0 = No SDVO Device Present SDVO_CTRLDATA 1 = SDVO Device Present 0 = Normal Operation (Lane number in Order) CFG19 (DMI Lane Reversal) * * 1 = Reverse Lane 0 = Only PCIE or SDVO is operational. CFG20 (PCIE/SDVO concurrent) 7 CTRL_CLK 1 = PCIE/SDVO are operating simu. CFG5 7 CFG7 7 CFG8 7 CFG9 7 CFG12 7 CFG13 7 R76 00 01 10 11 CFG[13:12] (XOR/ALLZ) +3VS R74 * Reserved CFG[15:14] PEG_NTX_GRX_P[0..15] 34 * 0 = Reverse Lane CFG9 PEG_NTX_GRX_N[0..15] 34 * 0 = Normal mode CFG8 (Low power PCIE) CRESTLINE_1p0 CTRL_DATA 0 = DMI x 2 CFG5 (DMI select) For Crestline:1.3kohm For Calero: 255ohm R483 UMA@ 1 2 GMCH_EDID_CLK_LCD 011 = FSB 667MHz CFG[2:0] FSB Freq select CFG16 * R66 1 2 @ 4.02K_0402_1% R58 1 2 @ 4.02K_0402_1% R59 1 2 @ 4.02K_0402_1% R55 1 2 @ 4.02K_0402_1% R57 1 2 @ 4.02K_0402_1% R63 1 2 @ 4.02K_0402_1% R70 1 2 @ 4.02K_0402_1% B R75 2.2K_0402_5% CFG[17:3] have internal pull up CFG[19:18] have internal pull down 2 2 0_0402_5% R677 VGA@ 0_0402_5% R684 VGA@ 1 2 1 0_0402_5% R682 VGA@ 1 2 2.2K_0402_5% 1 R484 UMA@ 1 2 GMCH_EDID_DAT_LCD 0_0402_5% R683 VGA@ 0_0402_5% 0_0402_5% VGA@ VGA@ +3VS 0_0402_5% VGA@ 7 7 CFG19 CFG20 R72 1 2 @ 4.02K_0402_1% R73 1 2 @ 4.02K_0402_1% A A Note: CRT / TV-out should route to JP30 first then to the JP1 & JP2 on system side. 2007/1/15 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/1/15 Deciphered Date Title CRESTLINE((3/6)-VGA/LVDS/TV THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Sheet Thursday, January 10, 2008 1 9 of 49 5 4 +3VS BLM18PG181SN1D_0603 2 1 L10 UMA@ 1 2 AXD AXF SM CK C384 C56 C373 C383 VTT CRT PLL A LVDS A PEG A SM A CK HV VTTLF DMI PEG TV D TV/CRT 2 C 2 +1.25VS 2 1 MBK2012121YZF_0805 +1.25VS 10U_FLC-453232-100K_0.25A_10% UMA@ C380 0.1U_0402_16V4Z~N 1 1 2 2 C381 10U_0805_10V4Z~N 0.1U_0402_16V4Z~N +VCCP +1.25VM_MPLL L9 +1.25VS 2 1 MBK2012121YZF_0805 1 1 2 1 2 + 1 2 1 2 1 2 10U_0805_10V4Z~N LVDS 1 2 A7 F2 AH1 2 1 0_0603_5% UMA@ 1 +VCC_PEG 20mils UMA@ 2 +1.5VS R64 1 2 0_0805_5% L29 UMA@ 2 10U_0805_10V4Z~N 0.1U_0402_16V4Z~N UMA@ UMA@ C402 C401 0.022U_0402_16V7K~N 2 2 220U_D2_4VY_R15M CRESTLINE_1p0 1 UMA@ C416 +3VS UMA@ C417 VCCD_LVDS_1 VCCD_LVDS_2 VTTLF1 VTTLF2 VTTLF3 1 2 0.47U_0603_10V7K C65 VCCD_PEG_PLL J41 H42 AH50 AH51 +VCC_PEG 0.47U_0603_10V7K C385 +1.25VS_PEGPLL U48 VCCD_HPLL 1 + VCC_RXR_DMI_1 VCC_RXR_DMI_2 2 +1.25VM_HPLL L13 1 +3VS_HV AD51 W50 W51 V49 V50 1 +1.5VS_TVDAC 2 +1.8V_TXLVDS VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5 2 1 +1.25VS_DPLLA 0.47U_0603_10V7K C382 +1.25VM_HPLL R54 1 VCCD_QDAC C40 B40 2 1 C182 N28 AN2 +1.8V_LVDS +3VS_TVDACA VCCD_CRT VCCD_TVDAC VCC_HV_1 VCC_HV_2 1 C173 2VGA@ R6741 0_0402_5% M32 2 1 R673 0_0402_5% UMA@ L29 VCC_TX_LVDS A43 220U_D2_4VY_R15M +3VS_TVDACC VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2 +1.8V_SM_CK +1.25VS L12 BLM18PG121SN1D_0603 2 1 C191 +3VS_TVDACB +1.5VS_QDAC B VCCA_SM_CK_1 VCCA_SM_CK_2 C25 B25 C27 B27 B28 A28 +3VS_TVDACA BK24 BK23 BJ24 BJ23 +1.25VS_PEGPLL 0.1U_0402_16V4Z~N 2 BC29 BB29 VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4 C410 +1.5VS_TVDAC C123 2 1 0.1U_0402_16V4Z~N @ C122 2 1 1U_0603_10V4Z C104 C103 2 1 22U_0805_6.3V4Z @ 1 1U_0402_6.3V4Z 2 1 0_0603_5% 2 1U_0603_10V4Z +1.25VS_DMI 1 0.1U_0402_16V4Z~N +1.25VM_A_SM_CK AJ50 +1.8V R327 1 2 0_0805_5% C399 C72 2 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2 VCC_DMI 2 C115 C83 4.7U_0805_6.3V6K AT22 AT21 AT19 AT18 AT17 AR17 AR16 +V1.25VS_AXF D C114 0.022U_0402_16V7K~N 2 1 POWER B23 B21 A21 VCC_AXF_1 VCC_AXF_2 VCC_AXF_3 1 C179 C82 22U_0805_6.3V4Z 1 VCC_AXD_NCTF 2 +1.25VS 10U_0805_10V4Z~N 2 R71 1 + VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 2 R103 0_0603_5% C176 C68 150U_B2_6.3VM_R45M VCCA_PEG_PLL AW18 AV19 AU19 AU18 AU17 AR29 2 1 0.1U_0402_16V4Z~N 1 2 0_0805_5% 1 +1.25VS U51 R60 1 2 0_0805_5% 1 10U_0805_10V4Z~N +1.25VM_A_SM 0317 change value VSSA_PEG_BG AT23 AU28 AU24 AT29 AT25 AT30 C88 20 mils K49 VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6 C87 C +1.25VS_PEGPLL VCCA_PEG_BG 2 +1.25VM_AXD 1U_0603_10V4Z 1 K50 1 R330 0_0603_5% 1 0.1U_0402_16V4Z~N UMA@ 2 C175 0.1U_0402_16V4Z~N 2 R50 VSSA_LVDS 2 2 C397 +3VS_PEG_BG R97 1 2 0_0805_5% +3VS VCCA_LVDS 2 1U_0603_10V4Z A41 1 C413 1000P_0402_50V7K~N B41 +1.8V_TXLVDS 2 2 C395 VCCA_MPLL 1 C394 VCCA_HPLL AM2 2 C396 AL2 +1.25VM_MPLL 1 +1.8V_SM_CK +1.25VS 1 10U_0603_6.3V6M +1.25VM_HPLL 1 10U_0805_10V4Z~N C411 2 1 22U_0805_6.3V4Z VCCA_DPLLB 2 UMA@ +1.25VS_DMI 1 +1.25VS L14 10U_FLC-453232-100K_0.25A_10% C178 VCCA_DPLLA H49 2 2 1 0.1U_0402_16V4Z~N C180 B49 +1.25VS_DPLLB C174 +1.25VS_DPLLA 1 2 2 1 22U_0805_6.3VAM VSSA_DAC_BG 1 + UMA@ 1 2.2U_0805_16V4Z B32 1 C370 4.7U_0805_10V4Z~N VCCA_DAC_BG 330U_V_2.5VM U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1 4.7U_0805_10V4Z~N A30 +3VS_DAC_BG +3VS VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 0.47U_0603_10V7K VCCA_CRT_DAC_1 VCCA_CRT_DAC_2 +3VS_DAC_CRT UMA@ 2 A33 B33 BLM18PG181SN1D_0603 2 1 L11 UMA@ 0.1U_0402_16V4Z~N C407 UMA@ 0.022U_0402_16V7K~N 1 UMA@ U4H VCCSYNC +1.25VS +V1.25VS_AXF +VCCP J32 +3VS_DAC_CRT 1 +1.25VS_DPLLB C141 UMA@ 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N 2 2 1 C408 2 R92 UMA@ 2 1 0_0603_5% UMA@ 1 4.7U_0805_10V4Z~N C405 UMA@ 2 0.1U_0402_16V4Z~N C406 0.022U_0402_16V7K~N UMA@ D 1 3 VCCSYNC +3VS +3VS_DAC_BG C63 Take off 0ohm 0805 because Layout 0.1U_0402_16V4Z~N 1 1 2 2 C62 10U_0805_10V4Z~N B +VCCP_D 2 D7 +VCCP 2 R79 2 1 10_0402_5% 1 R93 2 1 0_0402_5% +3VS_HV CH751H-40PT_SOD323-2 +3VS +1.5VS_QDAC +3VS_TVDACB +1.5VS R69 +3VS R62 2 2 40 mils 1 C98 C96 2 1 2 1 0_0603_5% UMA@ 0.1U_0402_16V4Z~N UMA@ 1 UMA@ C97 0.022U_0402_16V7K~N 2 +3VS +1.8V_LVDS 1 2 1 0_0603_5% UMA@ 1 2 UMA@ 2 C186 1U_0603_10V4Z 2 R109 UMA@ C187 10U_0805_10V4Z~N 1 C95 2 0.1U_0402_16V4Z~N UMA@ UMA@ C113 0.022U_0402_16V7K~N 1 C402 C95 C186 C413 U4 VGA@ 0_0402_5% 0_0402_5% 0_0402_5% 0_0603_5% 0_0402_5% CRESTLINE_1p0 C407 C96 C98 C174 C141 C173 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% +1.8V 1 C414 R53 2 1 0_0603_5% UMA@ 2 1 0_0603_5% UMA@ +1.8V 1 2 + 2 VGA@ 220U_D2_4VY_R15M +3VS_TVDACC C406 R349 UMA@ A +1.8V_TXLVDS 1000P_0402_50V7K~N C418 0.1U_0402_16V4Z~N UMA@ UMA@ C116 0.022U_0402_16V7K~N 1 2 1 0_0603_5% UMA@ VGA@ VGA@ VGA@ VGA@ UMA@ A VGA@ VGA@ VGA@ 2007/1/15 VGA@ VGA@ Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date VGA@ 2008/1/15 Deciphered Date Title CRESTLINE(4/6)-PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Thursday, January 10, 2008 Sheet 1 10 of 49 5 4 3 2 1 +VCCP +VCCP 2 2 1 VSS NCTF VSS SCB VCC AXM NCTF VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7 AT33 AT31 AK29 AK24 AK23 AJ26 AJ23 +VCCP +VCCP 10U_0805_10V4Z~N 0.1U_0402_16V4Z~N 1 1 C78 1U_0603_10V4Z C57 2 UMA@ + C100 2 UMA@ 330U_V_2.5VM 1 C79 2 UMA@ 1 1 C80 2 UMA@ 2 UMA@ 10U_0805_10V4Z~N UMA@ 2 0.47U_0603_10V7K 1 C99 UMA@ 1 C86 C101 D UMA@ 2 0.22U_0402_10V4Z~N C B 1 2 1 2 1 2 C163 1U_0603_10V4Z 2 C145 1U_0603_10V4Z UMA@ 1 0.22U_0603_10V7K~N 0.1U_0402_16V4Z~N 2 C146 0.47U_0402_6.3V6K 1 0.22U_0603_10V7K~N 2 C81 1 C67 2007/1/15 Issued Date UMA@ 2 A Compal Electronics, Inc. Compal Secret Data Security Classification 1 AW45 VCCSM_LF1 BC39 VCCSM_LF2 BE39 VCCSM_LF3 BD17 VCCSM_LF4 BD4 VCCSM_LF5 AW8 VCCSM_LF6 AT6 VCCSM_LF7 1 A CRESTLINE_1p0 0.1U_0402_16V4Z~N C71 VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7 370mil 0.1U_0402_16V4Z~N VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31 C70 R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14 VCC SM LF 2 1 VCC GFX NCTF 2 1 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 VCC SM 330U_V_2.5VM + AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30 VCC GFX 1 2 1 2 CRESTLINE_1p0 1 C148 C164 VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19 A3 B2 C1 BL1 BL51 A51 VCC_13 POWER 160mil 0.01U_0402_16V7K~N C147 AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33 VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6 R30 +1.8V 22U_0805_6.3V4Z C165 2 C102 0.1U_0402_16V4Z~N 2 1 2 C121 1 C117 0.1U_0402_16V4Z~N 2 C142 0.1U_0402_16V4Z~N 0.22U_0402_10V4Z~N C144 0.22U_0402_10V4Z~N C161 1 2 10U_0805_10V4Z~N C162 10U_0805_10V4Z~N B 1 R78 1 2 0_0603_5% POWER +VCCP 1 T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28 22U_0805_6.3V4Z C VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VCC AXM 2 VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50 VCC NCTF 1 2 2 1 AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37 C120 2 0.1U_0402_16V4Z~N C119 1 0.22U_0402_10V4Z~N C143 C374 2 0.22U_0402_10V4Z~N C118 + 22U_0805_6.3V4Z 220U_D2_4VY_R15M 1 1 U4F VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83 2 +VCCP D VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC CORE U4G AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32 2008/1/15 Deciphered Date Title CRESTLINE((5/6)-PWR/GND THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Sheet Thursday, January 10, 2008 1 11 of 49 5 4 3 2 1 U4I A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16 D C B VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS CRESTLINE_1p0 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41 U4J C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50 D C VSS B CRESTLINE_1p0 UMA@ UMA@ A A 2007/1/15 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/1/15 Deciphered Date Title CRESTLINE((6/6)-PWR/GND THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Sheet Thursday, January 10, 2008 1 12 of 49 5 4 3 2 1 Close to VREF pins of SO-DIMM +1.8V close to connector R144 1K_0402_1% 1 DDR_A_D8 DDR_A_D14 DDR_A_DQS#1 DDR_A_DQS1 2 Layout Note: Place near JDIM1 DDR_A_D2 DDR_A_D3 1 C206 0.1U_0402_16V4Z~N 14 +DDR_MCH_REF1 D DDR_A_DQS#0 DDR_A_DQS0 2 +DDR_MCH_REF1 2 DDR_A_D9 DDR_A_D15 +1.8V DDR_A_D16 DDR_A_D17 330U 2.5V Y D2 2 DDR_A_DQS#2 DDR_A_DQS2 1 + C84 1 C108 2 0.1U_0402_16V4Z 2 1 C130 C131 2 1 0.1U_0402_16V4Z C154 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 C169 2 2.2U_0603_6.3V6K 2 1 C166 C149 2 1 2.2U_0603_6.3V6K C124 2 1 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K C105 2.2U_0603_6.3V6K 1 DDR_A_D18 DDR_A_D19 @ 2 DDR_A_D29 DDR_A_D24 DDR_A_DM3 DDR_A_D26 DDR_A_D27 C Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V DDR_CKE0_DIMMA 7 DDR_CKE0_DIMMA 8 DDR_A_BS#2 DDR_A_BS#2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 8 8 +0.9VS 2 1 2 1 2 7 M_ODT1 M_ODT1 1 DDR_A_D37 DDR_A_D36 2 DDR_A_DQS#4 DDR_A_DQS4 C168 C153 C152 C129 C128 C107 C167 C151 C150 C127 C126 C125 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z C106 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 1 DDR_A_CAS# DDR_CS1_DIMMA# 8 DDR_A_CAS# 7 DDR_CS1_DIMMA# DDR_A_V 1 DDR_A_MA10 DDR_A_BS#0 DDR_A_WE# DDR_A_BS#0 DDR_A_WE# DDR_A_D35 DDR_A_D34 DDR_A_D40 DDR_A_D44 B DDR_A_DM5 DDR_A_D41 DDR_A_D46 Layout Note: Place these resistor closely JP41,all trace length Max=1.5" DDR_A_D49 DDR_A_D48 DDR_A_V DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D54 DDR_A_D50 DDR_A_MA5 DDR_A_MA8 RP14 1 2 DDR_A_MA1 DDR_A_MA3 RP13 56_0404_4P2R_5% RP17 56_0404_4P2R_5% 1 4 4 1 DDR_A_MA7 2 3 3 2 DDR_A_MA6 4 3 4 3 DDR_A_D61 DDR_A_D60 RP22 56_0404_4P2R_5% 1 DDR_A_MA12 2 DDR_CKE0_DIMMA DDR_A_DM7 DDR_A_D59 DDR_A_D58 RP7 56_0404_4P2R_5% RP15 56_0404_4P2R_5% DDR_A_RAS# 1 4 4 1 DDR_A_MA9 DDR_CS0_DIMMA# 2 3 3 2 DDR_A_BS#2 RP6 A DDR_A_BS#0 DDR_A_MA10 1 2 RP5 56_0404_4P2R_5% RP16 56_0404_4P2R_5% 4 4 1 DDR_A_MA4 3 3 2 DDR_A_MA2 56_0404_4P2R_5% RP8 1 4 4 2 3 3 56_0404_4P2R_5% 1 DDR_A_MA0 2 DDR_A_BS#1 RP1 56_0404_4P2R_5% RP2 DDR_CS1_DIMMA# 2 3 4 M_ODT1 1 4 3 56_0404_4P2R_5% 1 M_ODT0 2 DDR_A_MA13 DDR_A_CAS# DDR_A_WE# ICH_SM_DA ICH_SM_CLK 14,16,19,24 ICH_SM_DA 14,16,19,24 ICH_SM_CLK +3VS C58 0.1U_0402_16V4Z 1 1 2 2 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 C59 2.2U_0603_6.3V6K VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 FOX_ASOA426-M2RN-7F SO-DIMM A REVERSE DDR_A_D6 DDR_A_D0 DDR_A_DM0 DDR_A_D5 DDR_A_D7 1 2 1 2 DDR_A_D13 DDR_A_D12 D DDR_A_DM1 M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR0 7 M_CLK_DDR#0 7 DDR_A_D11 DDR_A_D10 DDR_A_D20 DDR_A_D21 DDR_A_DM2 PM_EXTTS#0 7 DDR_A_D23 DDR_A_D22 DDR_A_D28 DDR_A_D25 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D31 DDR_A_D30 DDR_CKE1_DIMMA DDR_A_MA14 DDR_CKE1_DIMMA 7 C DDR_A_MA14 7 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 DDR_A_MA13 DDR_A_BS#1 8 DDR_A_RAS# 8 DDR_CS0_DIMMA# 7 M_ODT0 7 DDR_A_D32 DDR_A_D33 DDR_A_DM4 DDR_A_D39 DDR_A_D38 DDR_A_D45 DDR_A_D43 B DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D47 DDR_A_D42 DDR_A_D52 DDR_A_D53 M_CLK_DDR1 M_CLK_DDR#1 M_CLK_DDR1 7 M_CLK_DDR#1 7 DDR_A_DM6 DDR_A_D51 DDR_A_D55 DDR_A_D57 DDR_A_D56 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 R32 10K_0402_5% 2 1 1 R143 1K_0402_1% 8 DDR_A_MA[0..13] 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 DDR_A_D4 DDR_A_D1 C220 8 DDR_A_DQS[0..7] C201 8 DDR_A_DM[0..7] +DDR_MCH_REF1 JDIM2 +1.8V 0.1U_0402_16V4Z 8 DDR_A_D[0..63] 2.2U_0805_16V4Z Layout Note: +DDR_MCH_REF trace width and spacing is 20/20. R31 10K_0402_5% 2 1 8 DDR_A_DQS#[0..7] A Bottom side Issued Date 56_0404_4P2R_5% RP23 56_0404_4P2R_5% DDR_CKE1_DIMMA 1 2 4 1 DDR_A_MA14 R96 56_0402_5% 3 2 DDR_A_MA11 Compal Electronics, Inc. Compal Secret Data Security Classification 2007/1/15 Deciphered Date 2008/1/15 Title DDR2 SO-DIMM I THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Thursday, January 10, 2008 Sheet 1 13 of 49 5 4 3 2 1 Close to VREF pins of SO-DIMM 8 DDR_B_DQS#[0..7] +1.8V 8 DDR_B_D[0..63] +DDR_MCH_REF1 8 DDR_B_DM[0..7] DDR_B_D10 DDR_B_D11 +1.8V 330U 2.5V Y D2 2 DDR_B_D17 DDR_B_D20 1 + 2 C189 2 1 C155 C133 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 C132 2 0.1U_0402_16V4Z 2 1 C109 C177 2 1 0.1U_0402_16V4Z C138 2 1 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 1 C160 2 2.2U_0603_6.3V6K 2 1 C139 2.2U_0603_6.3V6K C112 2.2U_0603_6.3V6K 1 DDR_B_DQS#2 DDR_B_DQS2 @ DDR_B_D18 DDR_B_D19 DDR_B_D28 DDR_B_D25 DDR_B_DM3 C Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS DDR_B_D30 DDR_B_D31 7 DDR_CKE2_DIMMB 8 DDR_B_BS#2 DDR_CKE2_DIMMB DDR_B_BS#2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 +0.9VS 8 8 DDR_B_V 2 1 2 1 2 8 DDR_B_CAS# 7 DDR_CS3_DIMMB# 1 7 M_ODT3 DDR_B_MA10 DDR_B_BS#0 DDR_B_WE# DDR_B_CAS# DDR_CS3_DIMMB# M_ODT3 DDR_B_D32 DDR_B_D33 2 C159 C172 C137 C158 C136 C111 C171 C170 C157 C156 C135 C134 C110 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 DDR_B_BS#0 DDR_B_WE# DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35 DDR_B_D40 DDR_B_D41 B DDR_B_DM5 Layout Note: Place these resistor closely JP42,all trace length Max=1.5" DDR_B_V RP18 1 2 DDR_B_BS#0 DDR_B_MA10 RP10 56_0404_4P2R_5% RP26 56_0404_4P2R_5% DDR_B_MA14 1 4 4 1 DDR_B_MA11 2 3 3 2 DDR_B_MA0 DDR_B_BS#1 RP12 56_0404_4P2R_5% RP19 56_0404_4P2R_5% DDR_B_MA5 1 4 4 1 DDR_B_MA8 2 3 3 2 4 3 DDR_B_D51 DDR_B_D50 RP24 56_0404_4P2R_5% DDR_B_MA12 1 DDR_B_MA9 2 DDR_B_D56 DDR_B_D61 DDR_B_DM7 DDR_B_D59 DDR_B_D58 13,16,19,24 ICH_SM_DA 13,16,19,24 ICH_SM_CLK RP3 1 2 DDR_CS3_DIMMB# 2 M_ODT3 1 +3VS C61 56_0404_4P2R_5% RP20 56_0404_4P2R_5% DDR_B_MA4 4 4 1 DDR_B_MA2 3 3 2 56_0404_4P2R_5% RP4 3 4 4 3 56_0404_4P2R_5% RP25 4 3 DDR_CKE3_DIMMB 1 2 R335 56_0402_5% 0.1U_0402_16V4Z 1 1 2 2 56_0404_4P2R_5% DDR_B_MA13 1 M_ODT2 2 DDR_B_DM1 M_CLK_DDR2 M_CLK_DDR#2 M_CLK_DDR2 7 M_CLK_DDR#2 7 DDR_B_D14 DDR_B_D15 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DDR_B_D21 DDR_B_D16 PM_EXTTS#1 7 DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D26 DDR_B_D24 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D29 DDR_B_D27 DDR_CKE3_DIMMB C DDR_CKE3_DIMMB 7 DDR_B_MA14 DDR_B_MA14 7 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_BS#1 DDR_B_RAS# DDR_CS2_DIMMB# DDR_B_BS#1 8 DDR_B_RAS# 8 DDR_CS2_DIMMB# 7 M_ODT2 DDR_B_MA13 M_ODT2 7 DDR_B_D36 DDR_B_D37 DDR_B_DM4 DDR_B_D39 DDR_B_D38 DDR_B_D44 DDR_B_D45 B DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 M_CLK_DDR3 M_CLK_DDR#3 M_CLK_DDR3 7 M_CLK_DDR#3 7 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D57 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 R33 1 FOX_AS0A426-NARN-7F~N 2.2U_0603_6.3V6K 2 D SO-DIMM B REVERSE 2 +3VS 10K_0402_5% A Bottom side DDR_B_BS#2 DDR_CKE2_DIMMB Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 1 2 C60 VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 2 1 R34 RP9 DDR_B_CAS# DDR_B_WE# ICH_SM_DA ICH_SM_CLK VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD 1 DDR_B_D12 DDR_B_D13 10K_0402_5% RP11 56_0404_4P2R_5% RP21 56_0404_4P2R_5% DDR_B_RAS# DDR_B_MA7 1 4 4 1 DDR_CS2_DIMMB# 2 DDR_B_MA6 3 3 2 A DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_MA3 DDR_B_MA1 4 3 DDR_B_D42 DDR_B_D43 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DDR_B_D6 DDR_B_D7 1 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DM0 2 DDR_B_D8 DDR_B_D9 DDR_B_D5 DDR_B_D4 C222 DDR_B_D2 DDR_B_D3 Layout Note: Place near JDIM2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 C221 DDR_B_DQS#0 DDR_B_DQS0 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS 0.1U_0402_16V4Z DDR_B_D0 DDR_B_D1 8 DDR_B_MA[0..13] VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS 2.2U_0805_16V4Z 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 8 DDR_B_DQS[0..7] D +DDR_MCH_REF1 13 JDIM1 2007/1/15 Deciphered Date 2008/1/15 Title DDR2 SO-DIMM II THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 56_0404_4P2R_5% Rev 0.1 LA-4231P Date: 5 4 3 2 Thursday, January 10, 2008 Sheet 1 14 of 49 B C 2 W=40mils 1 1 1 C1 2 L25 2 0.1U_0402_16V4Z 2 R319 CRT_VSYNC CRT_VSYNC 1 0_0402_5% +CRT_VCC C17 1 2 0.1U_0402_16V4Z UMA@ 1 2CRT_VSYNC_B R337 30_0402_5% 5 1 1 0_0402_5% 2 A 3 9 C348 2 Close to GMCH Y 4 2 1 C347 2 C349 C7 2 原本為10K 1 UMA@ 9 3VDDCDA 2 1 R628 0_0402_5% BSS138_NL_SOT23 1 3 UMA@ 9 3VDDCCL 2 1 R629 0_0402_5% Q1 BSS138_NL_SOT23 34 2 R624 2 R625 VGA@ VGA_DDCDATA Q3 1 0_0402_5% VGA@ 1 0_0402_5% 34 2 VGA_DDCCLK 1 C4 2 D_CRT_VSYNC R6 0_0805_5% 2 1 CRT_GND R314 0_0805_5% 2 1 2 6 IN 3 EN C372 0.1U_0402_16V7K~N 5 GND OUT 1 NC 4 GND 2 AOZ1320CI-04_SOT23-6 1 1 UMA@ 1 VGA@ R15 10K_0402_5% 2 R662 1 0_0402_5% EC_ENBKL 1 29 +LCDVDD W=60mils U53 R21 +LCDVDD 1 2 C363 C369 0.1U_0402_16V7K~N W=60mils EC_ENBKL 1 29 2 BKOFF# BKOFF# @ 9 GMCH_ENBKL 34 G7X_ENBKL 2 R655 1 UMA@ 0_0402_5% EC_ENBKL 2 R651 1 VGA@ 0_0402_5% R652 2.2K_0402_5% VGA@ D26 CH751H-40_SC76 1 2 D25 CH751H-40_SC76 1 2 LVDSAC+ UMA@ R508 LVDSAC- UMA@ R510 1 1 2 2 0_0402_5% 0_0402_5% GMCH_LVDSAC+ GMCH_LVDSAC- LVDSA0+ LVDSA0- UMA@ R544 UMA@ R570 1 1 2 2 0_0402_5% 0_0402_5% GMCH_LVDSA0+ GMCH_LVDSA0- LVDSA1+ LVDSA1- UMA@ R595 UMA@ R596 1 1 2 2 0_0402_5% 0_0402_5% GMCH_LVDSA1+ GMCH_LVDSA1- LVDSA2+ LVDSA2- UMA@ R597 UMA@ R598 1 1 2 2 0_0402_5% 0_0402_5% GMCH_LVDSA2+ GMCH_LVDSA2- UMA@ R599 UMA@ R600 1 1 2 2 0_0402_5% GMCH_EDID_CLK_LCD 0_0402_5% GMCH_EDID_DAT_LCD 4.7K_0402_5% DISPOFF# EDID_CLK_LCD EDID_DAT_LCD GMCH_LVDSAC+ 9 GMCH_LVDSAC- 9 GMCH_LVDSA0+ 9 GMCH_LVDSA0- 9 GMCH_LVDSA1+ 9 GMCH_LVDSA1- 9 GMCH_LVDSA2+ 9 GMCH_LVDSA2- 9 GMCH_EDID_CLK_LCD GMCH_EDID_DAT_LCD 9 9 R652 2 LCD_VCC_TEST_EN 3 R10 VGA_DDC_CLK_C U6 74AHCT1G125GW_SOT353-5 4.7U_0805_6.3V6K~N 2 D9 GMCH_LVDDEN 2 CH751H-40PT_SOD323-2 D8 VGA_LVDDEN 2 CH751H-40PT_SOD323-2 1 VGA_DDC_CLK_C +3VS 1 29 LCD_VCC_TEST_EN VGA_DDC_DATA_C R14 R13 Close to VGA +3VS 34 VGA_LVDDEN 16 17 R9 VGA_DDC_DATA_C 1 LCD 9 GMCH_LVDDEN +3VS SUYIN_070549FR015S208CR CONN@ 2 2 1 U5 74AHCT1G125GW_SOT353-5 G 34 VGA_VSYNC Y 2 1 VSYNC_L D_CRT_HSYNC 4 1 C345 HSYNC_L 1 2 0_0603_5% L24 P OE# 2 R631 VGA@ 2 R632 34 VGA_HSYNC A 3 VGA@ 2 P OE# CRT_HSYNC UMA@ 1 2CRT_HSYNC_B R336 30_0402_5% G 9 CRT_HSYNC CRT_GND 4.7P_0402_50V8C 1 2 0_0603_5% 1 10K_0402_5% 5 1 1 2 4.7P_0402_50V8C +CRT_VCC C18 C3 2 4.7P_0402_50V8C 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 DDC_MD2 1 C2 100P_0402_50V8J For EMI 2 100P_0402_50V8J @ C6 2 100P_0402_50V8J 1 100P_0402_50V8J @ C8 2 CRT_GND 15P_0402_50V8J 1 1 2 CRT_R_L L2 BK1608LL121-T 0603 1 2 CRT_G_L L3 BK1608LL121-T 0603 1 2 CRT_B_L L4 1 BK1608LL121-T 0603 15P_0402_50V8J @ C9 22P_0402_50V8J CRT_B_C 22P_0402_50V8J CRT_B CRT_G_C 22P_0402_50V8J CRT_G 9 R2 150_0402_1% 2 1 9 CRT_R_C 2 1 R619 0_0402_5% UMA@ 2 1 R620 0_0402_5% UMA@ 2 1 R621 0_0402_5% R8 150_0402_1% 2 1 CRT_R +3VS 1 2.2K_0402_5% R12 JCRT1 R7 150_0402_1% 2 1 9 +3VS 2 原本為4.7K UMA@ 1 +CRT_VCC +CRT_VCC @ 1 2.2K_0402_5% 2 2 G 2 MSEN# S 29 1 2.2K_0402_5% 2 1 G 1 0_0402_5% 1 S C344 0.1U_0402_16V4Z 1 0_0402_5% D 1 0_0402_5% 2 RB411DT146 SOT23 D 1.1A_6VDC_FUSE 1 2 2K_0402_5% 34 VGA_CRT_B 2 1 2 2K_0402_5% 2 R613 VGA@ 2 R614 VGA@ 2 R615 34 VGA_CRT_G W=40mils D17 F7 1 VGA@ E +CRT_VCC C346 CRT 34 VGA_CRT_R D +5VS 0.1U_0402_16V4Z A 100K_0402_5% UMA@ 3 9 BIA_PWM BIA_PWM 2 @ R20 35 VGA_LVDSAC+ 35 VGA_LVDSAC- INVT_PWM 1 10_0402_5% 1 2 C36 @ 1U_0603_10V4Z 3 35 VGA_LVDSA0+ 35 VGA_LVDSA0- JP4 LCD_CBL_DET# 29 LCD_CBL_DET# +3VS +LCDVDD 1 2 +3VS C38 @ 0.1U_0402_16V4Z 29 25 25 MIC_DIAG +3VS MIC_SIG MIC_CLK MIC_DIAG +3VS MIC_SIG MIC_CLK +5VS USB20_N8 USB20_P8 1 2 19 19 EDID_CLK_LCD EDID_DAT_LCD 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 LCD_TST LCD_TST 29 35 VGA_LVDSA1+ 35 VGA_LVDSA1- LVDSAC+ LVDSAC- 35 VGA_LVDSA2+ 35 VGA_LVDSA2- LVDSA0+ LVDSA0- VGA_LVDSAC+ VGA_LVDSAC- R630 R633 1 1 2 2 0_0402_5% VGA@ LVDSAC+ 0_0402_5% VGA@ LVDSAC- VGA_LVDSA0+ VGA_LVDSA0- R634 R635 1 1 2 2 0_0402_5% VGA@LVDSA0+ 0_0402_5% VGA@ LVDSA0- VGA_LVDSA1+ VGA_LVDSA1- R601 R602 1 1 2 2 0_0402_5% VGA@ LVDSA1+ 0_0402_5% VGA@ LVDSA1- VGA_LVDSA2+ VGA_LVDSA2- R603 R604 1 1 2 2 0_0402_5% VGA@ LVDSA2+ 0_0402_5% VGA@ LVDSA2- LVDSA1+ LVDSA1LVDSA2+ LVDSA2- 34 VGA_CLK_LCD 34 VGA_DAT_LCD DISPOFF# DAC_BRIG INVT_PWM R644 1 R645 1 0_0402_5% VGA@ EDID_CLK_LCD 0_0402_5% VGA@ EDID_DAT_LCD 2 2 DAC_BRIG 29 INVT_PWM 29 INVPWR_B+ 1 L5 C32 ACES_88242-4001~N C195 220P_0402_50V7K VGA_CLK_LCD VGA_DAT_LCD 0.1U_0603_50V4Z 2 2 C34 1 1 2 B+ FBMA-L11-201209-221LMA30T_0805 0.1U_0603_50V4Z 4 220P_0402_50V7K 1 C251 2 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/1/15 Deciphered Date 2008/1/15 Title CRT CONN/LCD CONN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: A B C D Thursday, January 10, 2008 Sheet E 15 of 49 5 4 FSLC FSLB FSLA CLKSEL2 CLKSEL1 CLKSEL0 CPU MHz SRC MHz PCI MHz 0 1 0 200 100 33.3 +3VS 1 R397 2 0_1206_5% 1 2 0 1 1 166 100 33.3 R1135 R1083 3 1 C479 10U_0805_10V4Z~N 2 1 C480 0.1U_0402_16V4Z~N 2 CPU Driven 0.1U_0402_16V4Z~N *(Default) No Stuff 2 1 C476 0.1U_0402_16V4Z~N 2 1 C464 0.1U_0402_16V4Z~N +1.25VS R1107 Stuff 1 C478 FSB Frequency Selet: D 2 R1074 R1086 667MHz R1139 R1135 No Stuff R1083 R1107 R1128 R1113 R1098 R1135 R1139 R1083 R1086 R1098 R1074 R1107 R1113 Stuff 800MHz No Stuff R1113 R1128 R1139 1 5 1 R410 0_0402_5% CPU_BSEL0 R1139 0.1U_0402_16V4Z~N 1 1 C459 R1135 2 22U_0805_6.3V4Z +3VM_CK505 R1128 1 2 MCH_CLKSEL0 7 R411 1K_0402_5% 2 +3VS R379 VDDPCI VDD48 VDDPLL3 VDDREF 39 55 VDDSRC VDDCPU 12 20 26 VDD96_IO VDDPLL3_IO VDDSRC_IO 36 49 VDDSRC_IO VDDCPU_IO +3VS 2 1 10K_0402_5% R235 2 1 10K_0402_5% R234 R200 10K_0402_5% 2 1 1 @ R184 0_0402_5% CPU_BSEL2 2 1 2 R237 SATA_REQ1 PCI0/CR#_A 475_0402_1% 1 2 R233 MCH_REQ 3 PCI1/CR#_B 40 CLK_PCI_CB 29 CLK_PCI_TPM 24 CLK_DEBUG_PORT 33_0402_5% 1 12_0402_5% 2 12_0402_5% 1 2 R257 1 R239 2 R258 PCI2_TME 4 PCI2/TME 29 CLK_PCI_EC 33_0402_5% 1 2 R259 27_SEL 6 PCI4/27_Select 17 CLK_PCI_ICH 33_0402_5% 1 2 R260 ITP_EN 7 PCI_F5/ITP_EN 19 CLKSATAREQ# MCH_CLKSEL1 7 7 R377 1K_0402_5% 2 1 2 CLKMCHREQ# MCH_CLKSEL2 7 PCI_CLK3 5 22U_0805_6.3V4Z 1 C474 C461 2 2 0.1U_0402_16V4Z~N NC 48 SCLK SDATA 64 63 PCI_STOP# CPU_STOP# 38 37 2 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N 1 1 C475 C477 2 2 0.1U_0402_16V4Z~N 60 X1 CLK_XTAL_OUT 59 X2 2 0_0402_5% 19 CLK_48M_ICH 19 CLK_14M_ICH 33_0402_5% 1 2 R401 33_0402_1% 1 2 R201 FSA 10 USB_48MHZ/FSLA FSB 57 FSLB/TEST_MODE FSC 62 REF0/FSLC/TEST_SEL +1.25VM_CK505 1 = Enable SRC0 & 27MHz For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed R_CPU_BCLK R_CPU_BCLK# CPU1_F CPU1#_F 51 50 R_MCH_BCLK R_MCH_BCLK# SRC8/CPU2_ITP SRC8#/CPU2_ITP# 47 46 R_PCIE_LAN R_PCIE_LAN# SRC10 SRC10# 34 35 R_PCIE_EXPR R_PCIE_EXPR# R202 1 1 R203 2 2 0_0402_5% 0_0402_5% R204 1 1 R205 R208 1 1 R209 2 2 0_0402_5% 0_0402_5% 2 2 0_0402_5% 0_0402_5% R213 1 1 R212 2 2 0_0402_5% 0_0402_5% SRC11/CR#_H SRC11#/CR#_G 33 32 R_CLKREQ#_H R_CLKREQ#_G R396 2 2 R375 1 1 SRC9 SRC9# 30 31 R251 R_CLK_PCIE_MCard 1 R_CLK_PCIE_MCard# 1 R252 2 2 SRC7/CR#_F SRC7#/CR#_E 44 43 R_CLKREQ#_F R_CLKREQ#_E R398 2 2 R386 1 1 SRC6 SRC6# 41 40 R_CLK_Rob R_CLK_Rob# R210 1 1 R211 2 2 SRC4 SRC4# 27 28 R_MCH_3GPLL R_MCH_3GPLL# 45 VDDSRC_IO SRC3/CR#_C SRC3#/CR#_D 24 25 R_PCIE_ICH R_PCIE_ICH# 42 GNDSRC SRC2/SATA SRC2#/SATA# 21 22 R_PCIE_SATA R_PCIE_SATA# 8 GNDPCI 11 GND48 SRC1/SE1/27MHz_NonSS SRC1#/SE2/27MHz_SS 17 18 SSCDREFCLK SSCDREFCLK# 15 GND CLK_XTAL_OUT GNDSRC C257 18P_0402_50V8J~N 1 R240 10K_0402_5% 1 58 27_SEL SRC0/DOT96 SRC0#/DOT96# CK_PWRGD/PD# GNDREF 13 14 CLK_PCIE_LAN 22 CLK_PCIE_LAN# 22 CLK_PCIE_EXPR 28 CLK_PCIE_EXPR# 28 1 2 +3VS R374 10K_0402_5% 475_0402_1% EXPR_CARD_REQ# 28 475_0402_1% MCARD_REQ#G 24 1 2 +3VS R395 10K_0402_5% 0_0402_5% CLK_PCIE_MCARD 24 0_0402_5% CLK_PCIE_MCARD# 24 1 2 +3VS R385 10K_0402_5% 475_0402_1% MCARD_REQ#F 22 475_0402_1% MCARD_REQ#E 24 1 2 +3VS R399 10K_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 2 2 CLK_PCIE_ICH 19 CLK_PCIE_ICH# 19 CLK_PCIE_SATA 18 CLK_PCIE_SATA# 18 R243 1 1 R244 R241 R_MCH_DREFCLK 1 R_MCH_DREFCLK# 1 R242 R344 1 R493 1 2UMA@ 0_0402_5% 2UMA@ 0_0402_5% MCH_SSCDREFCLK 7 MCH_SSCDREFCLK# 7 2UMA@ 0_0402_5% 2UMA@ 0_0402_5% CLK_MCH_DREFCLK 7 CLK_MCH_DREFCLK# 7 2VGA@ 0_0402_5% 2VGA@ 0_0402_5% CLK_PCIE_VGA 34 CLK_PCIE_VGA# 34 56 CK_PWRGD 19 2 0_0402_5% A CLK_EN# 49 PCI2_TME R268 10K_0402_5% UMA@ R238 10K_0402_5% @ 2007/1/15 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/1/15 Deciphered Date Title Clock generator THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Routing the trace at least 10mil Rev 0.1 LA-4231P Date: 5 B CLK_PCIE_Rob 24 CLK_PCIE_Rob# 24 CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7 R247 1 1 R248 1 @ R376 ICS9LPRS365BGLFT_TSSOP64 CLK_MCH_BCLK 7 CLK_MCH_BCLK# 7 2 1 GNDSRC 29 R236 10K_0402_5% CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4 1 C265 18P_0402_50V8J~N 1 ITP_EN 2 2 1 2 Placed within 500 mils of CK505M 1 1 R492 10K_0402_5% VGA@ 2 Y3 GNDCPU 23 2 14.31818MHZ_16P 2 GND 52 +3VM_CK505 CLK_XTAL_IN A 19 +3VM_CK505 2 1 = Overclocking of CPU and SRC NOT allowed C473 H_STP_PCI# 19 H_STP_CPU# 19 54 53 For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# For 27_SEL, 0 = Enable DOT96 & SRC1, 1 2 0.1U_0402_16V4Z~N R199 B D ICH_SM_CLK 13,14,19,24 ICH_SM_DA 13,14,19,24 CPU0 CPU0# PCI3 CLK_XTAL_IN R185 1K_0402_5% 2 C460 1 5 1 1 @ R378 0_0402_5% FSC 475_0402_1% 1 FSB CPU_BSEL1 2 C 1K_0402_5% 5 0.1U_0402_16V4Z~N U7 2 9 16 61 +VCCP 2 C R1074 +1.25VM_CK505 R402 2.2K_0402_5% FSA 2 1 1 C463 +1.25VM_CK505 0_1206_5% 2 C462 R1086 2 Place close to U7 R261 1 R1098 Stuff 1 +3VM_CK505 4 3 2 Thursday, January 10, 2008 Sheet 1 16 of 49 5 4 3 2 1 +3VS D 1 R190 1 R191 1 R221 1 R192 1 R218 1 R220 1 R166 1 R219 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% PCI_DEVSEL# 1 R165 1 R217 1 R216 1 R389 1 R164 1 R167 1 R168 2 R214 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 1 8.2K_0402_5% PCI_PIRQA# 1 R215 1 R178 1 R193 1 R388 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% 2 8.2K_0402_5% PCI_REQ0# PCI_STOP# PCI_TRDY# 40 PCI_AD[0..31] U8B PCI_FRAME# PCI_PLOCK# PCI_IRDY# PCI_SERR# PCI_PERR# +3VS C PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# PCI_REQ1# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 D20 E19 D19 A20 D17 A21 A19 C19 A18 B16 A12 E16 A14 G16 A15 B6 C11 A9 D11 B12 C12 D10 C7 F13 E11 E13 E12 D8 A6 E8 D6 A3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# F9 B5 C5 A10 PIRQA# PIRQB# PIRQC# PIRQD# PCI_REQ2# PCI REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 A4 D7 E18 C18 B19 F18 A11 C10 PCI_REQ0# PCI_GNT0# PCI_REQ1# C/BE0# C/BE1# C/BE2# C/BE3# C17 E15 F16 E17 PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3 IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# C8 D9 G6 D16 A7 B7 F10 C16 C9 A17 PCI_IRDY# PCI_PAR PCI_PCIRST# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME# PLTRST# PCICLK PME# AG24 B10 G7 PCI_PLTRST# CLK_PCI_ICH EC_PME# F8 G11 F12 B3 PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# Interrupt I/F PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5 PCI_REQ0# 40 PCI_GNT0# 40 D PCI_REQ2# PCI_REQ3# PCI_GNT3# PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3 40 40 40 40 PCI_IRDY# 40 PCI_PAR 40 PCI_DEVSEL# 40 PCI_PERR# PCI_SERR# PCI_STOP# 40 PCI_TRDY# 40 PCI_FRAME# 40 CLK_PCI_ICH 16 EC_PME# 29 C PCI_PIRQF# PCI_PIRQG# 40 ICH8M REV 1.0 PCI_REQ3# PCI_GNT3# 1 Check if use LPC? 2 R189 @ 1K_0402_5% Boot BIOS Strap B B +3VALW 2 B 1 A A16 swap override Strap PCI 2 R187 0_0402_5% 1 * 5 2 R390 2 B 1 A 1 PCI_RST# 21,40 R186 100K_0402_5% 2 @ U10 Y 3 @ R179 1K_0402_5% 2 @ R188 1K_0402_5% 2 CLK_PCI_ICH PCI_PLTRST# P SPI_CS1#_R 1 SPI_CS1#_R 1 Place closely pin B10 19 PCI_RST# +3VALW G PCI_GNT0# 4 4 PLT_RST# PLT_RST# 7,19,22,24,28,29,34 1 LPC 1 1 Y MC74VHC1G08DFT2G SC70 5P MC74VHC1G08DFT2G SC70 5P R122 0_0402_5% 1 R112 100K_0402_5% 2 0 1 Low= A16 swap override Enble High= Default* PCI_GNT3# @ U9 2 PCI_PCIRST# SPI 1 0 P 5 Boot BIOS Location G SPI_CS#1 3 PCI_GNT0# 1 @ 10_0402_5% A C470 @ 8.2P_0402_50V A 1 2 2007/1/15 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/1/15 Deciphered Date Title ICH8(1/4)-PCI/INT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Sheet Thursday, January 10, 2008 1 17 of 49 5 4 3 2 1 +3VS R127 GATEA20 2 1 10K_0402_5% R163 KB_RST# D R139 1 330K_0402_1% 2 LAN100_SLP R140 1 1M_0402_5% 2 SM_INTRUDER# R141 1 330K_0402_1% 2 ICH_INTVRMEN +VCCP R156 H_FERR# AF23 RTCRST# JOPEN1 @ 2 10M_0402_5% 1 1 2 Y2 32.768KHZ_12.5PF_1TJS125BJ4A421P NC +3VS 2 24.9_0402_1% GLAN_COMP R181 1 +1.5VS 25 ACZ_BITCLK 25 ACZ_SYNC R346 33_0402_5% 1 R353 33_0402_5% 1 25 ACZ_RST# R110 33_0402_5% 1 GLAN_CLK D22 LAN_RSTSYNC C21 B21 C22 LAN_RXD0 LAN_RXD1 LAN_RXD2 D21 E20 C20 LAN_TXD0 LAN_TXD1 LAN_TXD2 1 R135 2 21 PSATA_ITX_DRX_N0 PSATA_ITX_DRX_N0 1 C193 PSATA_ITX_DRX_N0_C 2 3900P_0402_50V7K 21 PSATA_ITX_DRX_P0 PSATA_ITX_DRX_P0 1 C192 PSATA_ITX_DRX_P0_C 2 3900P_0402_50V7K R356 33_0402_5% 1 AJ16 AJ15 HDA_BIT_CLK HDA_SYNC 2 HDA_RST_R# AE14 HDA_RST# ADC_ACZ_SDIN0 AJ17 AH17 AH15 AD13 HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 AE13 HDA_SDOUT AE10 AG14 HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 AF10 SATALED# AF6 AF5 AH5 AH6 SATA0RXN SATA0RXP SATA0TXN SATA0TXP AG3 AG4 AJ4 AJ3 SATA1RXN SATA1RXP SATA1TXN SATA1TXP AF2 AF1 AE4 AE3 SATA2RXN SATA2RXP SATA2TXN SATA2TXP AB7 AC6 SATA_CLKN SATA_CLKP AG1 AG2 SATARBIAS# SATARBIAS 2 HDA_SDOUT_R PAD T19 31 SATA_LED# 21 PSATA_IRX_DTX_N0_C 21 PSATA_IRX_DTX_P0_C SATA_LED# PSATA_IRX_DTX_N0_C PSATA_IRX_DTX_P0_C PSATA_ITX_DRX_N0_C PSATA_ITX_DRX_P0_C close ICH8 ODD_ITX_DRX_N0 ODD_ITX_DRX_N0 ODD_ITX_DRX_P0 ODD_ITX_DRX_P0 1 C323 1 C325 @ ODD_ITX_DRX_N0_C 2 3900P_0402_50V7K @ ODD_ITX_DRX_P0_C 2 3900P_0402_50V7K 21 ODD_IRX_DTX_N0_C 21 ODD_IRX_DTX_P0_C 16 CLK_PCIE_SATA# 16 CLK_PCIE_SATA close ICH8 GLAN_COMPI GLAN_COMPO 2 2 SATA_LED# 25 ACZ_SDOUT D25 C25 GLAN_DOCK#/GPIO13 HDA_BITCLK_R HDA_SYNC_R 25 ADC_ACZ_SDIN0 10K_0402_5% INTVRMEN LAN100_SLP B24 AH21 3 2 NC C OUT IN 1 4 2 C419 10P_0402_50V8J~N INTRUDER# ODD_IRX_DTX_N0_C ODD_IRX_DTX_P0_C ODD_ITX_DRX_N0_C ODD_ITX_DRX_P0_C CLK_PCIE_SATA# CLK_PCIE_SATA R358 1 2 FWH4/LFRAME# C4 LPC_FRAME# LDRQ0# LDRQ1#/GPIO23 G9 E6 LPC_DRQ0# AF13 AG26 GATEA20 H_A20M# DPRSTP# DPSLP# AF26 AE26 H_DPRSTP_R# FERR# AD24 H_FERR# CPUPWRGD/GPIO49 AG29 H_PWRGOOD IGNNE# AF27 H_IGNNE# INIT# INTR RCIN# AE24 AC20 AH14 H_INIT# H_INTR KB_RST# NMI SMI# AD23 AG28 H_NMI H_SMI# 24.9_0402_1% 24,29 PAD PAD GATEA20 29 H_A20M# 4 H_DPRSTP# 1 0_0402_5% 2 R129 H_PWRGOOD 5 H_IGNNE# 4 within 2" from R1557 H_INIT# 4 H_INTR 4 KB_RST# 29 +VCCP C H_NMI 4 H_SMI# 4 STPCLK# AA24 H_STPCLK# AE27 THRMTRIP_ICH# TP8 AA23 R131 56_0402_5% H_STPCLK# 4 1 2 R130 IDE_DD[0..15] V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6 IDE_DD0 IDE_DD1 IDE_DD2 IDE_DD3 IDE_DD4 IDE_DD5 IDE_DD6 IDE_DD7 IDE_DD8 IDE_DD9 IDE_DD10 IDE_DD11 IDE_DD12 IDE_DD13 IDE_DD14 IDE_DD15 DA0 DA1 DA2 AA4 AA1 AB3 IDE_DA0 IDE_DA1 IDE_DA2 DCS1# DCS3# Y6 Y5 IDE_DCS1# IDE_DCS3# DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ W4 W3 Y2 Y3 Y1 W5 IDE_DIOR# IDE_DIOW# IDE_DDACK# IDE_IRQ IDE_DIORDY IDE_DDREQ H_DPRSTP# 5,7,49 H_DPSLP# 5 H_FERR# 4 THRMTRIP# DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 56_0402_5% LPC_FRAME# 24,29 T36 T35 A20GATE A20M# IHDA C188 1U_0603_10V6K ICH_RTCX2 2 1 ICH_RTCX1 R341 1 1 AF25 AD21 RTC LPC 2 ICH_INTVRMEN LAN100_SLP LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 1 1 ICH_RTCRST# E5 F5 G8 F6 FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 2 2 RTCX1 RTCX2 LAN / GLAN CPU 2 AG25 AF24 IDE R124 1 20K_0402_5% ICH_RTCX1 ICH_RTCX2 SM_INTRUDER# AD22 C415 10P_0402_50V8J~N LPC_AD[0..3] U8A +RTCVCC B 1 10K_0402_5% +RTCVCC SATA D 2 24_0402_1% H_THERMTRIP# 4,7 21 placed within 2" from ICH8M +3VS IDE_DIORDY R145 1 IDE_IRQ R146 1 IDE_DA0 IDE_DA1 IDE_DA2 2 4.7K_0402_5% 2 8.2K_0402_5% 21 21 21 B IDE_DCS1# 21 IDE_DCS3# 21 IDE_DIOR# 21 IDE_DIOW# 21 IDE_DDACK# 21 IDE_IRQ 21 IDE_DIORDY 21 IDE_DDREQ 21 ICH8M REV 1.0 Within 500 mils XOR CHAIN ENTRANCE STRAP:RSVD +3VS @ R357 1K_0402_5% 1 ACZ_SDOUT 2 2 1 ICH_RSVD @ R352 1K_0402_5% ICH_RSVD 19 XOR Chain Entrance Strap A ICH RSVD HDA SDOUT Description 0 0 RSVD 0 1 Enter XOR Chain 1 0 Normal Operation (Default) A 2007/1/15 Issued Date 1 1 Set PCIE port config bit 1 Compal Electronics, Inc. Compal Secret Data Security Classification 2008/1/15 Deciphered Date Title ICH8(2/4)_LAN,HD,IDE,LPC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Sheet Thursday, January 10, 2008 1 18 of 49 R119 R150 R121 @ R132 7 PM_BMBUSY# 2ICH_PCIE_WAKE# 1K_0402_5% 1 29 EC_LID_OUT# 2ICH_RI# 10K_0402_5% 1 16 H_STP_PCI# 16 H_STP_CPU# 2XDP_DBRESET# 10K_0402_5% 1 2 EC_LID_OUT# 10K_0402_5% 1 7,29,49 High -->No boot RP27 +3VALW 5 6 7 8 4 3 2 1 25 RP28 4 3 2 1 AE20 AG18 STP_PCI#/GPIO15 STP_CPU#/GPIO25 AH11 CLKRUN#/GPIO32 PAD T17 PAD T18 ICH_RSVD 18 ICH_RSVD VRMPWRGD AJ22 TP7 AJ8 AJ9 AH9 AE16 AC19 AG8 AH12 AE11 AG10 AH25 AD16 AG13 AF9 AJ11 AD10 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 GPIO12 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 AD9 AJ21 SATA GPIO WAKE# SERIRQ THRM# AJ20 MCH_ICH_SYNC# AJ13 7 MCH_ICH_SYNC# USB_OC#5 USB_OC#8 USB_OC#9 USB_OC#0 10K_1206_8P4R_5% CLKSATAREQ# SB_SPKR SB_SPKR SMB H_STP_PCI# H_STP_CPU# EC_SMI# EC_SCI# PAD T20 16 CLKSATAREQ# USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 10K_1206_8P4R_5% 5 6 7 8 SMBALERT#/GPIO11 OCP# 29 EC_SMI# 29 EC_SCI# low-->default C AG22 1 2 VRMPWRGD R345 0_0402_5% SST_CTL PAD T45 4 OCP# +3VS EC_LID_OUT# VGATE VGATE 2SB_SPKR @ 10K_0402_5% 1 R134 BMBUSY#/GPIO0 ICH_PCIE_WAKE# AE17 SERIRQ AF12 EC_THERM# AC13 24,28 ICH_PCIE_WAKE# 29 SERIRQ 4,29 EC_THERM# SUS_STAT#/LPCPD# SYS_RESET# AG12 29,40 PCI_CLKRUN# 2 CL_RST#1 10K_0402_5% 1 RI# PM_BMBUSY# SPKR MCH_SYNC# TP3 ICH8M REV 1.0 AJ12 AJ10 AF11 AG11 1 AG9 G5 CLK_14M_ICH CLK_48M_ICH SUSCLK D3 ICH_SUSCLK SLP_S3# SLP_S4# SLP_S5# AG23 AF21 AD18 SLP_S3# SLP_S4# SLP_S5# CLK14 CLK48 CLK_14M_ICH 16 CLK_48M_ICH 16 1 R125 @ 10_0402_5% @ 10_0402_5% 2 1 C229 @ 4.7P_0402_50V8C 2 C196 D @ 4.7P_0402_50V8C T34 PAD SLP_S3# SLP_S4# SLP_S5# 29 29 29 S4_STATE#/GPIO26 AH27 PWROK AE23 DPRSLPVR/GPIO16 AJ14 T46 PAD R123 0_0402_5% M_PWROK 1 2 PM_PWROK 7,29 1 DPRSLPVR DPRSLPVR 7,49 PM_PWROK BATLOW# AE21 ICH_LOW_BAT# PWRBTN# C2 PBTN_OUT# LAN_RST# AH20 RSMRST# AG27 PM_RSMRST# CK_PWRGD E1 CLPWROK E3 CK_PWRGD_R 1 R176 M_PWROK 2 R128 10K_0402_5% PBTN_OUT# 29 PLT_RST# 7,17,22,24,28,29,34 1 2 R158 10K_0402_5% SLP_M# AJ25 CL_CLK0 CL_CLK1 F23 AE18 CL_CLK0 CL_DATA0 CL_DATA1 F22 AF19 CL_DATA0 CL_VREF0 CL_VREF1 D24 AH23 CL_VREF0_ICH CL_VREF1_ICH CL_RST# AJ23 MEM_LED/GPIO24 ME_EC_ALERT/GPIO10 EC_ME_ALERT/GPIO14 WOL_EN/GPIO9 R175 2 SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37 Clocks 1ICH_LOW_BAT# 8.2K_0402_5% 2 F4 XDP_DBRESET# AD15 SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1 2 CK_PWRGD 0_0402_5% CK_PWRGD 16 RSMRST# -> CLPWROK -> PWROK M_PWROK 7 T43 PAD CL_CLK0 7 CL_DATA0 7 T44 PAD CL_RST# 7 AJ27 AJ24 2 AF22 0_0402_5% AG19 C R195 3.24K_0402_1% 1 2 +3VS 1 R339 ACIN 29,43,44 LAN_WOL_EN 29 1 R151 PAD T30 4 XDP_DBRESET# AF17 1 U8C ICH_SMB_CLK AJ26 ICH_SMB_DATA AD19 CL_RST#1 AG21 ME_SMB_CK AC17 ME_SMB_DA AE19 SYS GPIO 1 28 ICH_SMB_CLK 28 ICH_SMB_DATA CLK_14M_ICH 1 R347 8.2K_0402_5% ICH_RI# R138 2 R107 2.2K_0402_5% Place closely pin AG9 1 C234 R180 453_0402_1% 2 2 R106 2.2K_0402_5% D +3VALW CLK_48M_ICH 10K_0402_5% 1 10K_0402_5% +3VS 0.1U_0402_16V4Z~N R137 Power MGT 2OCP# 8.2K_0402_5% 1 Place closely pin G5 1 1 2 MISC GPIO Controller Link R115 1 1 2EC_THERM# 8.2K_0402_5% 2 2PCI_CLKRUN# 8.2K_0402_5% 2 1 R136 @ R149 3 +3VALW 2 R348 2SERIRQ 10K_0402_5% 2 R148 4 +3VALW 1 2 5 +3VS 1 USB_OC#7 10K_0402_5% 2 R118 U8D 1 28 28 28 28 PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 0.1U_0402_16V7K~N2 0.1U_0402_16V7K~N2 PCIE_RXN2 M27 PCIE_RXP2 M26 1 C435 PCIE_C_TXN2 L29 C436 PCIE_C_TXP2 L28 1 PERN2 PERP2 PETN2 PETP2 24 24 24 PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3 0.1U_0402_16V7K~N2 0.1U_0402_16V7K~N2 PCIE_RXN3 PCIE_RXP3 1 C437 PCIE_C_TXN3 1 C450 PCIE_C_TXP3 K27 K26 J29 J28 PERN3 PERP3 PETN3 PETP3 WLAN 24 24 24 24 PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4 0.1U_0402_16V7K~N2 0.1U_0402_16V7K~N2 PCIE_RXN4 PCIE_RXP4 1 C451 PCIE_C_TXN4 1 C452 PCIE_C_TXP4 H27 H26 G29 G28 PERN4 PERP4 PETN4 PETP4 GLAN 22 22 22 22 GLAN_RXN GLAN_RXP GLAN_TXN GLAN_TXP 0.1U_0402_16V7K~N2 0.1U_0402_16V7K~N2 GLAN_RXN F27 GLAN_RXP F26 1 C455GLAN_TXN_C E29 C454 GLAN_TXP_C E28 1 PERN5 PERP5 PETN5 PETP5 Express Card DPRSLPVR 2 @ R117 499_0402_1% 100K_0402_5% 1 2 VRMPWRGD R342 PERN1 PERP1 PETN1 PETP1 Robson 24 B D27 D26 C29 C28 17 SPI_CS1#_R 32 32 32 32 USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 29 EC_SWI# A 1 1 +3VS 3 13,14,16,24 ICH_SM_DA DMI1RXN DMI1RXP DMI1TXN DMI1TXP Y27 Y26 W29 W28 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 DMI_RXN1 7 DMI_RXP1 7 DMI_TXN1 7 DMI_TXP1 7 DMI2RXN DMI2RXP DMI2TXN DMI2TXP AB26 AB25 AA29 AA28 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 DMI_RXN2 7 DMI_RXP2 7 DMI_TXN2 7 DMI_TXP2 7 DMI3RXN DMI3RXP DMI3TXN DMI3TXP AD27 AD26 AC29 AC28 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 DMI_RXN3 7 DMI_RXP3 7 DMI_TXN3 7 DMI_TXP3 7 DMI_CLKN DMI_CLKP T26 T25 CLK_PCIE_ICH# CLK_PCIE_ICH DMI_ZCOMP DMI_IRCOMP Y23 Y24 DMI_IRCOMP USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9 SPI_CLK SPI_CS0# SPI_CS1# D23 F21 SPI_MOSI SPI_MISO OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9# USBRBIAS# USBRBIAS F2 F3 USBRBIAS USB 2 G G 2 2007/1/15 Issued Date CLK_PCIE_ICH# 16 CLK_PCIE_ICH 16 R152 24.9_0402_1%Within 500 1 2 +1.5VS USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9 32 32 32 32 32 32 32 32 24 24 28 28 32 32 32 32 15 15 32 32 mils ESATA+USB USB0 USB1 USB2 Mini Card0 Express Card 29 EC_RSMRST# EC_RSMRST# R157 0_0402_5% 1 2 PM_RSMRST# FingerPrinter BlueTooth Camera Felica A 1 2 R177 22.6_0402_1% Compal Electronics, Inc. Compal Secret Data Security Classification Q10 SSM3K7002FU_SC70-3 B Within 500 mils D S +5VS DMI_RXN0 7 DMI_RXP0 7 DMI_TXN0 7 DMI_TXP0 7 ICH8M REV 1.0 1ICH_SMB_CLK 3 13,14,16,24 ICH_SM_CLK DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP C23 B23 E22 AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18 V27 V26 U29 U28 D 2 Q9 SSM3K7002FU_SC70-3 ICH_SMB_DATA 1 S 2 2.2K_0402_5% R104 2.2K_0402_5% R105 USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 EC_SWI# USB_OC#7 USB_OC#8 USB_OC#9 DMI0RXN DMI0RXP DMI0TXN DMI0TXP PCI-Express Direct Media Interface 100K_0402_5% 1 2 LAN_WOL_EN R120 P27 P26 N29 N28 SPI modify follow intel check list-1003 2008/1/15 Deciphered Date Title ICH8(3/4)_PM,USB,GPIO THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Sheet Thursday, January 10, 2008 1 19 of 49 5 4 3 2 1 V5REF[1] V5REF[2] ICH_V5REF_SUS 10U_0805_6.3V6M G4 1 CHB1608U301_0603 + 2 +3VS 1 C430 220U_D2_4VY_R15M C219 +5VS A16 T7 C200 2 1 2 1 10U_0805_6.3V6M R159 D10 2 2.2U_0603_6.3V4Z~N CH751H-40PT_SOD323-2 20 mils 1 2 100_0402_5% C427 2 1 ICH_V5REF_RUN 1 C224 2 1 1 2 20 mils 1 C438 0.1U_0402_16V4Z~N 2 2 1U_0603_10V4Z C422 B C428 1U_0603_10V4Z 1 2 VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05] AC1 AC2 AC3 AC4 AC5 VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08] VCC1_5_A[09] VCC1_5_A[10] AC10 AC9 VCC1_5_A[11] VCC1_5_A[12] AA5 AA6 VCC1_5_A[13] VCC1_5_A[14] G12 G17 H7 VCC1_5_A[15] VCC1_5_A[16] VCC1_5_A[17] AC7 AD7 0.1U_0402_16V4Z~N 1 W23 VCC1_5_A[25] F17 G18 VCCLAN1_05[1] VCCLAN1_05[2] F19 G20 VCCLAN3_3[1] VCCLAN3_3[2] A24 4.7U_0805_10V4Z~N @ L32 A26 2 1 +1.5VS 1 A27 1 CHB1608U301_0603 B26 C261 B27 2 @ C457 B28 2 VCCGLANPLL 1 0.1U_0402_16V4Z~N 2 2 +1.5VS 0.1U_0402_16V4Z~N 1 1 2 +1.5VS L17 C252 A VCC_LAN1_05_INT_ICH_1 VCC_LAN1_05_INT_ICH_2 CHB1608U301_0603 2 1 2 2.2U_0603_106K C230 T31 T32 0316 change design 10U_0805_6.3V6M +3VS +3VS VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] VCCGLAN1_5[5] B25 GLAN POWER VCC1_5_A[20] VCC1_5_A[21] VCC1_5_A[22] VCC1_5_A[23] VCC1_5_A[24] C226 USB CORE VCCUSBPLL F1 L6 L7 M6 M7 +1.5VS C231 VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06] AC8 AD8 AE8 AF8 VCC3_3[07] VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] AA3 U7 V7 W1 W6 W7 Y7 VCC3_3[14] VCC3_3[15] VCC3_3[16] VCC3_3[17] VCC3_3[18] VCC3_3[19] VCC3_3[20] VCC3_3[21] VCC3_3[22] VCC3_3[23] VCC3_3[24] A8 B15 B18 B4 B9 C15 D13 D5 E10 E7 F11 VCCHDA AC12 VCCSUSHDA AD11 VCCSUS1_05[1] VCCSUS1_05[2] VCC1_5_A[18] VCC1_5_A[19] D1 +1.5VS ATX +1.5VS 2 VCCSATAPLL AD2 C431 2 2 +1.25VS 2 +VCCP 0.1U_0402_16V4Z~N +3VS 1 0.1U_0402_16V4Z~N +3VS C197 (SATA) 1 +3VS 2 2 +3VS 1 (DMI) 1 2 1 2 1 2 C213 0.1U_0402_16V4Z~N 2 +3VS 0.1U_0402_16V4Z~N 1 2 1 2 1 2 C233 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N +3VS 1 +3VALW TP_VCCSUS1.05_INT_ICH1 J6 AF20 TP_VCCSUS1.05_INT_ICH2 T25 T21 AC16 VCCSUS1_5_ICH_1 T22 VCCSUS1_5[2] J7 VCCSUS1_5_ICH_2 T24 VCCSUS3_3[01] C3 VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04] VCCSUS3_3[05] VCCSUS3_3[06] AC18 AC21 AC22 AG20 AH28 VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] P6 P7 C1 N7 P1 P2 P3 P4 P5 R1 R3 R5 R6 0.1U_0402_16V4Z~N 1 A22 VCCCL3_3[1] VCCCL3_3[2] F20 G21 C216 2 2 0.1U_0402_16V4Z~N +3VALW 1 C202 C194 2 2 0.1U_0402_16V4Z~N +3VALW 1 C258 2 G22 VCCCL1_05_ICH VCCCL1_5 C199 1 VCCSUS1_5[1] VCCCL1_05 1 C232 2 C420 1 AJ6 AE7 AF7 AG7 AH7 AJ7 VCC3_3[02] L16 0.01U_0402_16V7K~N 1 2 +1.5VS CHB1608U301_0603 1 1 C225 10U_0805_6.3V6M C214 2 1 +1.5VS ARX 1 10U_0805_6.3V6M 1 CHB1608U301_0603 C421 +1.5VS 1U_0603_10V4Z L30 VCC3_3[01] 2 C204 ICH_V5REF_SUS AF29 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N C203 CH751H-40PT_SOD323-2 AC23 AC24 2 1 C217 10_0402_5% VCC_DMI[1] VCC_DMI[2] V_CPU_IO[1] V_CPU_IO[2] C227 0.1U_0402_16V4Z~N C R29 AE28 AE29 1 4.7U_0603_6.3V6M D18 VCCDMIPLL C215 A23 A5 AA2 AA7 A25 AB1 AB24 AC11 AC14 AC25 AC26 AC27 AD17 AD20 AD28 AD29 AD3 AD4 AD6 AE1 AE12 AE2 AE22 AD1 AE25 AE5 AE6 AE9 AF14 AF16 AF18 AF3 AF4 AG5 AG6 AH10 AH13 AH16 AH19 AH2 AF28 AH22 AH24 AH26 AH3 AH4 AH8 AJ5 B11 B14 B17 B2 B20 B22 B8 C24 C26 C27 C6 D12 D15 D18 D2 D4 E21 E24 E4 E9 F15 E23 F28 F29 F7 G1 E2 G10 G13 G19 G23 G25 G26 G27 H25 H28 H29 H3 H6 J1 J25 J26 J27 J4 J5 K23 K28 K29 K3 K6 +VCCP C425 R361 VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] VCCA3GP +5VALW +3VALW AA25 AA26 AA27 AB27 AB28 AB29 D28 D29 E25 E26 E27 F24 F25 G24 H23 H24 J23 J24 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25 W25 Y25 0.1U_0402_16V7K~N A13 B13 C13 C14 D14 E14 F14 G14 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 22U_0805_6.3V4Z 0.1U_0402_16V4Z~N 2 V5REF_SUS VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26] VCC1_05[27] VCC1_05[28] C198 40 mils 2 ICH_V5REF_RUN CORE 1 +1.5VS VCCRTC VCCP_CORE L15 D U8E U8F AD25 IDE 2 PCI 2 20 mils VCCPSUS 1 VCCPUSB 1 C218 0.1U_0402_16V4Z~N C205 0.1U_0402_16V4Z~N +RTCVCC 0.47U_0603_10V7K VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] K7 L1 L13 L15 L26 L27 L4 L5 M12 M13 M14 M15 M16 M17 M23 M28 M29 M3 N1 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 N4 N5 N6 P12 P13 P14 P15 P16 P17 P23 P28 P29 R11 R12 R13 R14 R15 R16 R17 R18 R28 R4 T12 T13 T14 T15 T16 T17 T2 U12 U13 U14 U15 U16 U17 U23 U26 U27 U3 U5 V13 V15 V28 V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5 AB6 AD5 U4 W24 VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12] A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29 D C B ICH8M REV 1.0 T26 1 +3VS 2 A @C458 1U_0603_10V4Z VCCGLAN3_3 ICH8M REV 1.0 2007/1/15 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/1/15 Deciphered Date Title ICH8(4/4)_POWER&GND THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Sheet Thursday, January 10, 2008 1 20 of 49 5 4 3 IDE_DD[0..15] 2 18 CDROM CONN +5VS 10U_0805_10V4Z C520 2 1 1 47P_0402_50V8J 1 0.1U_0402_16V4Z 1 2 JODD1 1 1 C503 C506 C498 2 2 C499 2 D D PCI_RST# 1 +5VS 2 R429 100K_0402_5% C 31 ODD_ACT_LED# PCI_RST# 1 R448 2 0_0402_5% 18 IDE_DDREQ 18 18 IDE_DIOR# IDE_DIOW# IDE_DD8 IDE_DD7 IDE_DD9 IDE_DD6 IDE_DD10 IDE_DD5 IDE_DD11 IDE_DD4 IDE_DD12 IDE_DD3 IDE_DD13 IDE_DD2 IDE_DD14 IDE_DD1 IDE_DD15 IDE_DD0 18 IDE_DIORDY 18 IDE_DDACK# 18 IDE_IRQ 18 IDE_DA1 @ 2 R428 1 +5VS 10K_0402_5% 18 IDE_DA0 18 IDE_DA2 18 IDE_DCS1# 18 IDE_DCS3# ODD_ACT_LED# PDIAG# +5VS 80mils If CDROM is Slave then SD_CSEL= Floating else SD_CSEL= Low 1 470_0402_5% 2 R286 SD_CSEL 1000P_0402_50V7K~N 1U_0603_10V4Z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 GND GND Close to ODD Conn +5VS 0.1U_0402_16V7K~N 1 1 C575 C574 150U_B2_6.3VM_R45M 2 2 1 + 10U_0805_10V4Z~N 17,40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 1 C296 C377 2 C 1 C376 2 0.1U_0402_16V7K~N 2 1000P_0402_50V7K~N Close to SATA HDD ACES_88512-4541 SATA HDD CONN RESERVE(SATA ODD NET) JSATA1 B 18 PSATA_ITX_DRX_P0 18 PSATA_ITX_DRX_N0 18 PSATA_IRX_DTX_N0_C 18 PSATA_IRX_DTX_P0_C PSATA_ITX_DRX_P0 PSATA_ITX_DRX_N0 C393 3900P_0402_50V7K 2 1 2 1 1 2 3 4 5 6 7 B GND A+ AGND BB+ GND 18 ODD_IRX_DTX_N0_C 1 C326 C392 3900P_0402_50V7K +5VS 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 18 ODD_IRX_DTX_P0_C VCC3.3 VCC3.3 VCC3.3 GND GND GND VCC5 VCC5 VCC5 GND RESERVED GND VCC12 VCC12 GND VCC12 GND ODD_ITX_DRX_P0 ODD_ITX_DRX_N0 18 ODD_ITX_DRX_P0 18 ODD_ITX_DRX_N0 1 C327 ODD_IRX_DTX_N0 2 3900P_0402_50V7K ODD_IRX_DTX_P0 @ 2 3900P_0402_50V7K @ close JODD1 23 24 SUYIN_127043FB022G345ZR_NR CONN@ A A Compal Secret Data Security Classification Issued Date 2007/1/15 2008/1/15 Deciphered Date Title HDD/CDROM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Sheet Thursday, January 10, 2008 1 21 of 49 5 4 3 2 1 +3VALW +LAN_IO L46 FBMA-L11-322513-201LMA40T_1210 D Q59 2 HSIP HSIN 33 CLKREQB 16 CLK_PCIE_LAN 26 REFCLK_P 16 CLK_PCIE_LAN# 27 REFCLK_N 20 PERSTB GLAN_TXN GLAN_TXN PLT_RST# L92 1 2 4.7UH_1098AS-4R7M_1.3A_20% 2 2 1 SROUT12 +LAN_VDD 5 FB12 +LAN_IO 62 ENSR 64 RSET 60mil C778 1 R497 29 R498 +3VS 1 2 2.49K_0402_1% 19 PCIE_PME# ISOLATEB 1K_0402_5% R499 15K_0402_5% ISOLATEB LAN_XTAL1 60 CKTAL1 LAN_XTAL2 61 CKTAL2 65 EXPOSE_PAD Y6 1 2 C791 15P_0402_50V8J 2 25MHZ_12P_X8A025000FC1H-H 1 25 EGND 31 EGND 2 15 17 18 34 35 39 40 41 42 C805 1 15P_0402_50V8J B NC NC NC NC NC NC NC NC NC 45 47 48 44 LED3 LED2 LED1 LED0 54 55 56 57 MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3 3 4 6 7 9 10 12 13 DVDD12 DVDD12 DVDD12 DVDD12 DVDD12 DVDD12 21 32 38 43 49 52 EVDD12 EVDD12 22 28 VDD33 VDD33 VDD33 VDD33 16 37 46 53 VDDSR 63 AVDD33 AVDD33 2 59 AVDD12 AVDD12 AVDD12 AVDD12 8 11 14 58 IGPIO OGPIO 50 51 1 L92, C788, C778 close to U28(Pin 1) <200mil LANWAKEB 36 2 2 1 22U_1206_6.3V6M 0.1U_0402_10V7K~N 1 HSON 24 GLAN_TXP 19 60mil C788 30 EEDO EEDI/AUX EESK EECS 23 19 16 MCARD_REQ#F C HSOP 0.1U_0402_10V7K~N LAN_EEDO LAN_EEDI LAN_EECLK LAN_EECS DO DI SK CS GND NC NC VCC 5 6 7 8 1 R495 2 0_0402_5% @ 1 @ 2 2 1 1 2 2 0.1U_0402_10V7K~N C700 2 1 0.1U_0402_10V7K~N C779 1 0.1U_0402_10V7K~N C780 1 0.1U_0402_10V7K~N C782 2 0.1U_0402_10V7K~N C698 2 1 0.1U_0402_10V7K~N C572 U43 4 3 2 1 2 0.1U_0402_10V7K~N C803 3.6K_0402_5% 2 1 1 D 2 C801 0.1U_0402_16V7K~N +LAN_IO 2 AT93C46-10SU-2.7 SO 8P @ LAN_LED3 LAN_LED2 LAN_LED1 LAN_LED0 LAN_MDIP0 LAN_MDIN0 LAN_MDIP1 LAN_MDIN1 LAN_MDIP2 LAN_MDIN2 LAN_MDIP3 LAN_MDIN3 C +LAN_VDD +LAN_IO C783 L56 FBML10160808121LMT_0603 2 1 30mil 1 C637 1 C793 +LAN_IO +LAN_VDD 2 0.1U_0402_16V7K~N 2 0.1U_0402_16V7K~N 1 1 C792 2 2 0.1U_0402_10V7K~N GLAN_RXN R494 1 29 1 2 U28 2 1 GLAN_RXP_C C569 0.1U_0402_16V7K~N 2 1 GLAN_RXN_C C570 0.1U_0402_16V7K~N GLAN_TXP GLAN_RXP 19 7,17,19,24,28,29,34 LAN_DVDD15 1 22U_1206_6.3V6M 19 +LAN_VDD 2 +LAN_VDD C804 +LAN_IO R906 1.5M_0402_5% 1 3 S 2 1 C802 0.1U_0402_10V7K~N C810 @ EN_WOL# 29 2 1 C781 0.1U_0402_10V7K~N C798 2 G 1 0.1U_0402_10V7K~N 2 1 D Q58 SSM3K7002FU_SC70-3 2 C787 0.1U_0402_10V7K~N 1 EN_WOL C777 0.1U_0402_10V7K~N R496 470K_0402_5% D 2 1 22U_1206_6.3V6M 2 2 C812 @ 22U_1206_6.3V6M SI3456BDV-T1-E3_TSOP6 1 0.1U_0402_10V7K~N C800 S 1 1 2 B+_BIAS 1.5A 4 G 1 3 C790 1U_0603_10V6K 6 5 2 1 C966,C967 close to U28(PIN63) L55 FBML10160808121LMT_0603 2 1 +LAN_IO +LAN_IO LAN_AVDD33 1 C571 1 C789 +LAN_VDD 2 0.1U_0402_16V7K~N 2 0.1U_0402_16V7K~N RTL8111C-GR_QFN64_9X9 R315 1 2 0_0402_5% R316 1 2 0_0402_5% R317 1 2 0_0402_5% R318 1 2 0_0402_5% B JLAN2 LAN_LED0 T51 +LAN_IO RP38 C573 1 C784 1 0.01U_0402_16V7K 2 0.01U_0402_16V7K 2 V_DAC LAN_MDIN3 LAN_MDIP3 V_DAC LAN_MDIN2 LAN_MDIP2 C807 1 2 0.01U_0402_16V7K V_DAC LAN_MDIN1 LAN_MDIP1 C799 1 2 0.01U_0402_16V7K V_DAC LAN_MDIN0 LAN_MDIP0 1 2 3 TCT1 TD1+ TD1- MCT1 MX1+ MX1- 24 23 22 4 5 6 TCT2 TD2+ TD2- MCT2 MX2+ MX2- 21 20 19 RJ45_TX2RJ45_TX2+ 7 8 9 TCT3 TD3+ TD3- MCT3 MX3+ MX3- 18 17 16 RJ45_RX1RJ45_RX1+ 10 11 12 TCT4 TD4+ TD4- 15 14 13 MCT4 MX4+ MX4- RJ45_TX3RJ45_TX3+ 8 7 6 5 1 R968 2 LAN_ACTIVITY# 220_0402_5% 1 2 3 4 C794 1000P_1206_2KV7K D41 2 LAN_LED2 1 1 2 PR4- RJ45_TX3+ 7 PR4+ RJ45_RX1- 6 PR2- RJ45_TX2- 5 PR3- RJ45_TX2+ 4 PR3+ RJ45_RX1+ 3 PR2+ RJ45_TX0- 2 PR1- RJ45_TX0+ 1 PR1+ LED2_LED3 2 CH751H-40PT_SOD323-2 RJ45_TX0RJ45_TX0+ D43 LAN_LED1 1 2 LED1_LED3 CH751H-40PT_SOD323-2 BOTH_GST5009-LF D44 LAN_LED3 1 A 2 Yellow LED+ 8 D42 LAN_LED3 1 Yellow LED- 12 RJ45_TX3- CH751H-40PT_SOD323-2 75_1206_8P4R_5% 13 LED2_LED3 1 R969 2 LINK_10_1000# 220_0402_5% LED1_LED3 1 R970 2 LINK_100_1000# 220_0402_5% 11 Green LED- 9 Orange LED- 10 +LAN_IO GND 15 GND 14 Green-Orange LED+ A CH751H-40PT_SOD323-2 C-1775553 CONN@ 2007/1/15 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/1/15 Deciphered Date Title Broadcom BCM5787M THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Sheet Thursday, January 10, 2008 1 22 of 49 A B C D Mini-Express Card---WLAN Roboson +3VS +1.5VS 0.01U_0402_16V7K~N C294 1 2 E 0.01U_0402_16V7K~N C321 1 C298 2 4.7U_0805_10V4Z~N 1 4.7U_0805_10V4Z~N 1 C312 2 C320 2 1 2 0.1U_0402_16V4Z~N 1 1 +1.5VS +3VS +1.5VS +3VS JMINI1 JMINI2 ICH_PCIE_WAKE# 19,28 ICH_PCIE_WAKE# 32 32 CH_DATA @ R380 1 0_0402_5% 2 MINI_PIN3 CH_DATA CH_CLK CH_CLK @ R381 1 0_0402_5% 2 MINI_PIN4 MCARD_REQ#G 16 MCARD_REQ#G 16 CLK_PCIE_MCARD# 16 CLK_PCIE_MCARD 29,32 2 WL_OFF# WL_OFF# 7,17,19,22,28,29,34 PLT_RST# 19 PCIE_RXN4 +3VALW 19 PCIE_RXP4 PCIE_RXN4 1 R4032 PCIE_RXP4 R4061 R404 PCIE_C_RXN4 2 10_0402_5% 20_0402_5% PCIE_C_RXP4 0_0402_5% +1.5VS 13,14,16,19 ICH_SM_CLK 19 PCIE_TXN4 13,14,16,19 ICH_SM_DA 19 PCIE_TXP4 19 USB20_N4 19 USB20_P4 +3VS PCIE_TXN4 PCIE_TXP4 2 R373 2 R343 1 0_0402_5% 1 0_0402_5% USB20_N4 USB20_P4 PAD T61 31 LED_WLAN# LED_WWAN# LED_WLAN# +1.5VS +3VS 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 GND1 GND2 FOX_AS0B246-S50U-7F 16 MCARD_REQ#E 16 CLK_PCIE_Rob# 16 CLK_PCIE_Rob 16 CLK_DEBUG_PORT 19 19 PCIE_RXN3 PCIE_RXP3 19 19 PCIE_TXN3 PCIE_TXP3 1 R279 CLK_PCIE_Rob# CLK_PCIE_Rob 2 ROB_REQE# 0_0402_5% PLT_RST# 1 2 R444 0_0402_5% R288 0_0402_5% PCIE_RXN3 1 2PCIE_C_RXN3 PCIE_RXP3 1 2PCIE_C_RXP3 R290 0_0402_5% PCIE_TXN3 PCIE_TXP3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 GND1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND2 54 R280 R282 R281 R283 R287 1 1 1 1 1 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% LPC_FRAME# 18,29 LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 LPC_AD[0..3] PLT_RST# 7,17,19,22,28,29,34 DISK_BUSY T23 PAD 2 FOX_AS0B226-S52N-7F~N Power status(Left) LED1 12-21-BHC-ZL1M2RY-2C BLUE 29,31 PWR_BLUE_LED# +3VS PWR_BLUE_LED# 2 1 1 R472 +5VALW 2 200_0603_5% 0.01U_0402_16V7K~N C500 1 4.7U_0805_10V4Z~N C489 2 1 C456 2 1 +5VALW LED2 2 29 BATT_LOW_LED# 0.1U_0402_16V4Z~N 29 BATT_CHG_LED# +1.5VS BATT_LOW_LED# 3 Y BATT_CHG_LED# 2 1 R471 1 2 3 200_0603_5% B 12-22/Y2BHC-A30/2C_Y/B~D 0.01U_0402_16V7K~N 1 2 C488 C485 1 2 0.01U_0402_16V7K~N 4 4 2007/1/15 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/1/15 Deciphered Date Title Mini-Card/LED THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: A B C D Sheet Thursday, January 10, 2008 E 24 of 49 18,29 5 4 3 HD Audio Codec +VDDA C860 10U_1206_16V4Z 1 40mil 20mil 2 0_0603_5% 1 2 R877 +3VS 0.1U_0402_16V4Z C862 1 C861 2 1 For EMI +AVDD_AC97 40mil 0.1U_0402_16V4Z 1 1 L94 1 2 FBM-L11-160808-800LMT_0603 2 1 C863 2 0.1U_0402_16V4Z 2 1 C864 2 2 C865 10U_1206_16V4Z 0.1U_0402_16V4Z SPK_SEL HIGH: HARMAN LOW: NO-BRAND HP_JD LINE_OUT_R 36 LINER 16 MIC2_L HP_OUT_L 39 HP_LOUT 17 MIC2_R HP_OUT_R 41 HP_ROUT 23 LINE1_L NC 45 C872 24 LINE1_R DMIC_CLK 46 C873 18 CD_L NC 43 20 CD_R NC 44 1 R415 2 220P_0402_50V7K 19 CD_GND MIC_JD 26 EAPD EAPD MIC1_R PCBEEP ACZ_RST# 11 RESET# ACZ_SYNC 10 SYNC 5 2MIC_SIG_R 2 0_0402_5% 3 SENSE_A 13 34 R894 2 1 0_0402_5% R505,R504 close to PIN13 6 SDATA_IN 8 MONO_OUT 37 LINE1_VREFO 29 GPIO1 31 MIC1_VREFO_L 28 MIC1_VREFO_R 32 MIC2_VREFO 30 VREF 27 GPIO0 GPIO3 SENSE A SENSE B 47 EAPD 48 SPDIFO 4 7 DVSS1 DVSS2 JDREF 33 AVSS1 AVSS2 26 42 AMP_RIGHT 26 +VDDA 26 1 HP_LEFT HP_RIGHT 26 R370 10K_0402_5% 1 1U_0603_10V4Z R367 10K_0402_5% EC Beep C302 1 2 ACZ_BITCLK 18 29 2 0_0402_5% 1 ADC_ACZ_SDIN0 BEEP R369 1 18 1U_0603_10V4Z 1 R368 2 1 C 2 B MONO_IN 2 E C 1U_0603_10V4Z 1 2 Q21 R384 2SC2411K_SC59 2.4K_0402_5% ICH Beep +MIC1_VREFO_L +MIC1_VREFO_R AC97_VREF C308 560_0402_5% 2 47K_0402_5% 10mil 10mil 2 1 MIC_CLK 15 R889 2 @ 1 2 @ 10_0402_5% C875 10P_0402_50V8J~N 1 2 R890 0_0402_5% R891 C301 2 MIC_CLK 2 0_0402_5% 19 C305 1 2 SB_SPKR R363 1 10mil 1 40 NC AMP_LEFT 26 1000P_0402_50V7K~N @ BIT_CLK SDATA_OUT 1 C526 2 6.8K_0603_5% 2 6.8K_0603_5% 1 2 R885 0_0603_5% 1 2 R886 0_0603_5% 1000P_0402_50V7K~N 2 MIC1_L 22 1 R881 1 R884 1 21 12 ACZ_SDOUT 9 NC 18 MIC_SIG1 R412 1 15 18 18 39.2K _0402_1% 2 151 MIC_SIG R892 1 2 R893 20K_0402_1% DVDD LINEL 3 MIC2 DVDD_IO 38 35 2 1U_0603_10V4Z 2 1 R364 2 560_0402_5% 1 MIC1 26 C 26 LINE_OUT_L D22 CH751H-40PT SOD323 R371 10K_0402_5% 47K_0402_5% C879 10U_0805_10V4Z 2 26 C_MIC1 1 2 C876 2.2U_0603_10V6K C_MIC2 1 2 C877 2.2U_0603_10V6K MONO_IN 1000P_0402_50V7K~N NC 1 1 1000P_0402_50V7K~N C869 14 2 C527 220P_0402_50V7K C867 2 @ D 1 MIC_SIG_R AVDD2 AVDD1 U49 25 D R895 20K_0402_1% 2 ALC268-GR_LQFP48 close to CODEC DGND 2 R309 B AGND Sense Pin 1 0_0402_5% Impedance Codec Signals B 39.2K PORT-A (PIN 39, 41) 20K PORT-B (PIN 21, 22) 10K PORT-C (PIN 23, 24) HP_JD 5.1K PORT-D (PIN 35, 36) Q68 SSM3K7002FU_SC70-3 @ 39.2K PORT-E (PIN 14, 15) +3VS SENSE B S Q69 SSM3K7002FU_SC70-3 @ 20K PORT-F (PIN 16, 17) 10K PORT-G (PIN 43, 44) 5.1K PORT-H (PIN 45, 46) C881 U50 2 10K_0603_1% 1 VIN 2 GND 3 C882 SHDN# VOUT 5 BP 4 +VDDA RT9198-4GPBG SOT-23 5P 4.75V 1 2 Moat Bridge A 1 R902 1 R903 1 R904 1 R905 2 0_0603_1% 2 0_0603_1% 2 0_0603_1% 2 0_0603_1% 2006/08/05 Issued Date 2007/08/05 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 A Compal Electronics, Inc. Compal Secret Data Security Classification 1 0.1U_0402_16V7K~N 1 PLUG_IN 3 26 S D 2 G R900 1 C884 2 G C883 1 PLUG_IN# PLUG_IN# 3 26 Adjustable Output +5VS D 0.1U_0402_16V7K~N @ 1 @ 1 100K_0402_5% 4.7U_0805_10V4Z~N R897 R898 100K_0402_5% Regulator for CODEC 4.7U_0805_10V4Z 2 2 SENSE A 2 HD Audio Codec_ALC268 Document Number Rev 1.0 LA-4231P Thursday, January 10, 2008 Sheet 1 25 of 49 A B C D E Speaker Connector R293 W=40Mil 2 C521 1 0.47U_0603_10V7K 25 AMP_RIGHT 25 C522 1 0.47U_0603_10V7K AMP_LEFT 7 2 2 2 AMP_R 17 RIN+ 2 10K_0402_5% 5 2 R461 1 2 10K_0402_5% @ R459 1 2 10K_0402_5% GAIN1 3 ROUT+ 18 ROUT- 14 LOUT+ 4 RIN- SPK_1 1 R457 INTSPK_1 2 0_0603_5% 1 R456 INTSPK_2 2 0_0603_5% MIC2 25 MIC1 2 R310 2 R311 NC 12 10 4 MIC-2 1 1 2 0_0402_5% L34 CHB2012U170_0805 1 1 2 0_0402_5% L35 CHB2012U170_0805 10 9 8 7 3 6 2 1 MIC-1 8 BYPASS 5 +MIC1_VREFO_R +MIC1_VREFO_L MIC_JD 25 25 4 FOX_JA6333L-B3S0-7F~N R463 R464 1 1 C525 220P_0402_50V7K 1 JMIC1 C524 2 2 220P_0402_50V7K D16 SM05T1G_SOT23-3~D @ SHUTDOWN GND1 GND2 GND3 GND4 2 1 C333 0.47U_0603_16V4Z HEADPHONE OUT JACK 20 13 11 1 P3017THF B0 TSSOP 20P 1 21 +3VS 3K_0402_5% 3K_0402_5% 2 2 1 LIN- GNDA 19 SPK_2 LIN+ LOUT- 2 10K_0402_5% 3 4 G1 G2 MICROPHONE IN JACK GAIN0 AMP_L 9 R298 1 2 10K_0402_5% 2 C331 1 0.47U_0603_10V7K R458 1 1 2 ACES_88266-0200 SM05T1G_SOT23-3~D @ U20 @ R460 1 1 2 1 4 3 +5VS VDD PVDD1 PVDD2 2 0_0402_5% INTSPK_1 INTSPK_2 1 1 C518 10U_0805_10V4Z JSPK2 2 3 C318 0.1U_0402_16V4Z 1 +5VS 16 15 6 1 D12 2 FOX_JA6333L-B3S0-7F~N R450 100K_0402_5% @ GAIN1 GAIN HP_OUTL R300 1 1 2.7K_0402_5% @ @ 0 0 6dB R299 @ 1K_0402_5% * 0 1 4 R305 @ 1K_0402_5% 10 9 8 7 3 6 2 1 C330 470P_0402_50V7K 2 2 1 1 C329 JHP1 470P_0402_50V7K 3 GAIN0 PLUG_IN HPR 2 47_0402_5%HP_R 1 2 L23 CHB2012U170_0805 HPL 2 47_0402_5%HP_L 1 2 L22 CHB2012U170_0805 2 PLUG_IN R301 1 2 1 R449 2 HP_OUTR 10dB D23 @ SM05T1G_SOT23-3~D 1 0 15.6dB 1 1 21.6dB 1 2 1K_0402_1% C519 1 2 3 S 1 Q43 SSM3K7002FU_SC70-3 @ R451 EAPD 1 2 G 100P_0402_50V8J EC_MUTE D CH751H-40_SC76 1 1 2 25 D14 2 29 3 5 PLUG_IN 2 3 +3VS 1 R307 1 2.2K_0402_5% 2 HPINR 1 2 15 INR 13 OUTR 11 HP_OUTR OUTL 9 HP_OUTL NC-4 4 NC-6 6 INL NC-8 8 NC-12 12 NC-16 16 NC-20 20 2.2K_0402_5% 1 C1P 3 C1N 1 5 2 C317 1U_0603_10V4Z SGND R306 HPINL SHDNL# PGND 2 HP_INR 2.2U_0603_6.3V6K 2 HP_INL 2.2U_0603_6.3V6K SHDNR# 18 2 HP_LEFT 1 C339 1 C338 14 17 25 HP_RIGHT HP_MUTE# 1 0_0402_5% PVss 25 2 R302 2 1U_0603_10V4Z 2 U22 EC_MUTE 1 C523 2 MC74VHC1G08DFT2G SC70 5P @ 19 2 Reserve the 0 ohm resistor. for voltage filtering R462 0_0603_5% 10 HP_MUTE# 4 Y SVDD A PVDD B 1 SVss 2 EAPD 7 PLUG_IN# G PLUG_IN# 3 25 U21 P 5 25 +3VS EAPD Change to 100p from 0.01u for EMI -1012 S IC TPA4411MRTJR QFN 20P 1 1 2 Issued Date 2007/1/15 1 Compal Electronics, Inc. Compal Secret Data Security Classification C316 1U_0603_10V4Z 2008/1/15 Deciphered Date Title AMP/Audio Jack THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: A B C D Sheet Thursday, January 10, 2008 E 26 of 49 5 4 3 2 1 Express card D +1.5VS C91 2 1 0.1U_0402_16V4Z~N 2 1 0.1U_0402_16V4Z~N U11 12 14 +3VS C74 C85 7,17,19,22,24,29,34 2 PLT_RST# 29,41,46 SYSON +3VALW 1 0.1U_0402_16V4Z~N PLT_RST# SYSON CPUSB# 4.7U_0805_10V4Z~N 1 +1.5VS_PEC 1.5Vout 1.5Vout 11 13 3.3Vout 3.3Vout 3 5 C90 0.1U_0402_16V4Z~N 17 6 3.3Vin 3.3Vin AUX_IN AUX_OUT 15 OC# 19 SYSRST# 20 SHDN# PERST# 1 STBY# NC 10 CPPE# GND EXPR_CPUSB# 9 18 2 2 8 +3V_PEC +3V_PEC 4.7U_0805_10V4Z~N PERST# 1 16 C92 0.1U_0402_16V4Z~N 7 1 C93 2 2 CPUSB# RCLKEN +3VS_PEC 4.7U_0805_10V4Z~N P2231NF_QFN20 C 1 C89 +3VS_PEC 2 4 SUSP# 29,41,46,47,48 SUSP# 1.5Vin 1.5Vin JEXP1 +1.5VS_PEC Express Card Power Switch 1 USB20_N5 R48 1 2 0_0402_5% USB20_N5_R2 19 USB20_N5 USB20_P5 R47 1 2 0_0402_5% USB20_P5_R 3 19 USB20_P5 EXPR_CPUSB# 4 5 6 ICH_SMB_CLK 7 19 ICH_SMB_CLK ICH_SMB_DATA 8 19 ICH_SMB_DATA 9 +1.5VS_PEC 10 +1.5VS_PEC PCIE_PME#_R 1 R37 2 11 19,24 ICH_PCIE_WAKE# 0_0402_5% 12 +3V_PEC PERST# 13 14 +3VS_PEC 15 EXPR_CARD_REQ# 16 16 EXPR_CARD_REQ# CPUSB# 17 CLK_PCIE_EXPR# 18 16 CLK_PCIE_EXPR# CLK_PCIE_EXPR 19 16 CLK_PCIE_EXPR 20 PCIE_RXN2 21 19 PCIE_RXN2 PCIE_RXP2 22 19 PCIE_RXP2 23 PCIE_TXN2 24 19 PCIE_TXN2 PCIE_TXP2 25 19 PCIE_TXP2 26 +1.5V_CARD Max. 650mA, Average 500mA +3V_CARD Max. 1300mA, Average 1000mA 1 C75 0.1U_0402_16V4Z~N 27 28 29 30 1 C73 2 2 D GND USB_DUSB_D+ CPUSB# RSV RSV SMB_CLK SMB_DATA +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PERn0 PERp0 GND PETn0 PETp0 GND C GND GND GND GND FOX_1CH4312C-TB_LB CONN@ B B A A Compal Electronics, Inc. Compal Secret Data Security Classification 2007/1/15 Issued Date Deciphered Date 2008/1/15 Title EXPRESS CARD THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Thursday, January 10, 2008 Sheet 1 28 of 49 +3VALW PCIE_PME# 1 R413 2 0_0402_5% 18 18 19 18,24 18,24 18,24 18,24 18,24 CLK_PCI_EC 16 CLK_PCI_EC 7,17,19,22,24,28,34 PLT_RST# R228 1 +3VALW 1 2 19 EC_SCI# 19,40 PCI_CLKRUN# 47K_0402_5% R272 C268 @ 10_0402_5% 2 2 0.1U_0402_16V4Z 1 @ C282 GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 1 31 KSI[0..7] 31 KSO[0..15] +5VALW R263 2 1 4.7K_0402_5% EC_SMB_CK1 R262 2 1 4.7K_0402_5% +3VS EC_SMB_DA2 R264 2 1 4.7K_0402_5% R265 2 1 4.7K_0402_5% R269 2 1 4.7K_0402_5% LCD_CBL_DET# R276 2 1 4.7K_0402_5% MIC_DIAG R308 1 2 10K_0402_5% EC_FB_SDATA_R R303 2 1 4.7K_0402_5% EC_FB_SCLK_R R304 2 1 4.7K_0402_5% EC_SMB_CK2 LCD_TST @ BT_OFF# 50 50 4,31,35 4,31,35 1 2 3 4 5 7 8 10 CLK_PCI_EC PLT_RST# EC_RST# EC_SCI# PCI_CLKRUN# 12 13 37 20 38 2 21 23 26 27 BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 63 64 65 66 75 76 C273 1 BATT_TEMP BATT_OVP ADP_I AD_BID MIC_DIAG VGA_THER DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F 68 70 71 72 DAC_BRIG DAC_BRIG 15 EN_DFAN1 EN_DFAN1 4 IREF IREF 44 M_PWROK_EC 1 2 R256 0_0402_5% PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F 83 84 85 86 87 88 EC_MUTE LCD_TST VGA_ON LCD_CBL_DET# TP_CLK TP_DATA SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0 97 98 99 109 SPI_PULLDOWN 2 R274 1 4.7K_0402_5% EN_WOL# EN_WOL# 22 SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS# 119 120 126 128 FRD#SPI_SO FWR#SPI_SI SPI_CLK FSEL#SPICS# CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 73 74 89 90 91 92 93 95 121 127 TOUCHKEY_TINT MSEN# FSTCHG BATT_CHG_LED# CAPSLED# BATT_LOW_LED# SCRLED# SYSON VR_ON ACIN EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 100 101 102 103 104 105 106 107 108 EC_RSMRST# EC_LID_OUT# EC_ON EC_SWI# ICH_PWROK BKOFF# WL_OFF# LCD_VCC_TEST_EN PSID_DISABLE# PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 110 112 114 115 116 117 118 SLP_S4# EC_ENBKL USB_EN EC_THERM# SUSP# PBTN_OUT# PS_ID PWM Output PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D DA Output 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 77 78 79 80 SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 AD_BID 1 PS2 Interface SPI Flash ROM SM Bus INVT_PWM 15 BEEP 25 W_DISABLE# 32 ACOFF 44 2 0.01U_0402_16V7K BATT_TEMP 50 BATT_OVP 50 ADP_I 44 VGATE M/B rev:0.1; 0.2; 0.3; 1.0 Voltage:0.0; 0.4; 0.8; 1.0 ECAGND SPI Flash connect JBIOS1 SPI_CS# 1 SPI_SO 3 5 +3VALW 7 MIC_DIAG 15 VGA_THER 34 1 3 5 7 2 4 6 8 2 4 6 8 +3VALW SPI_CLK_R SPI_SI E&T_2941-G08N-00E~D ME@ CHGVADJ 44 EC_MUTE 26 LCD_TST 15 VGA_ON 47 LCD_CBL_DET# 15 TP_CLK 31 TP_DATA 31 VGATE SPI Device Interface GPIO R231 C272 15K_0402_5% 0.1U_0402_16V4Z 2 Rb R266 0_0402_5% 1 2 BEEP W_DISABLE# ACOFF INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 AD KSI0 KSO[0..15] KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 BT_OFF# EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 2 1 GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC KSI[0..7] 15P_0402_50V8J EC_SMB_DA1 GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 2007-09-19 change Brd ID R232 47K_0402_5% 1 22 VCC VCC VCC VCC VCC VCC CB_PME# +3VALW Ra R414 @ 0_0402_5% 1 2 40 2 2 Board ID 1 67 U29 1 +EC_AVCC AVCC 2 L18 2 1 +3VALW 2 FBM-11-160808-601-T_0603 C481 C482 1000P_0402_50V7K~N 0.1U_0402_16V4Z~N 1 ECAGND2 2 1 FBM-11-160808-601-T_0603 L19 9 22 33 96 111 125 2 1 2 1 C291 1000P_0402_50V7K~N 2 1 C269 1000P_0402_50V7K~N 2 1 C493 0.1U_0402_16V4Z~N EC_PME# 2 1 C277 0.1U_0402_16V4Z~N R405 10K_0402_5% C285 0.1U_0402_16V4Z~N C281 0.1U_0402_16V4Z~N +3VALW 1 +EC_AVCC SPI Flash (8Mb*1) @ C507 1 2SPI_CLK_R 7,19,49 0.1U_0402_16V4Z~N +3VALW C314 1 2 20mils 0.1U_0402_16V4Z~N 2 R437 1 10K_0402_5% U37 FSEL#SPICS# 2 1SPI_CS# R439 15_0402_5% FRD#SPI_SO 1 2SPI_SO 15_0402_5% R275 TOUCHKEY_TINT 31 MSEN# 15 FSTCHG 44 BATT_CHG_LED# 24 CAPSLED# 31 BATT_LOW_LED# 24 SCRLED# 31 SYSON 28,41,46 VR_ON 49 ACIN 19,43,44 1 2 3 4 CS# DO WP# GND VCC HOLD# CLK DIO 8 7 6 5 W25X80-VSSI-G_SO8 SPI_CLK_R 1 15_0402_5% SPI_SI 1 15_0402_5% SPI_CLK 2 R420 2 FWR#SPI_SI R438 For ENE R416 1 R417 1 31 EC_FB_SCLK 31 EC_FB_SDATA +3VALW EC_MUTE PAD T56 PAD T57 31 ON_OFF 24,31 PWR_BLUE_LED# 31 NUMLED# 1 2 10K_0402_5% R277 XCLKI XCLKO 122 123 GPI XCLK1 XCLK0 V18R C270 2 BKOFF# 15 WL_OFF# 24,32 LCD_VCC_TEST_EN 15 PSID_DISABLE# 43 SLP_S4# 19 EC_ENBKL 15 USB_EN 32 EC_THERM# 4,19 SUSP# 28,41,46,47,48 PBTN_OUT# 19 PS_ID 43 4.7U_0603_6.3V 2 0.1U_0402_16V4Z 1 TPM 1.2 Conn 69 11 24 35 94 113 1 KB926QFA1_LQFP128 15P_0402_50V8J OUT IN NC 2 NC 15P_0402_50V8J C297 124 C322 1 EC_RSMRST# 19 EC_LID_OUT# 19 EC_ON 31 EC_SWI# 19 JTPM1 LPC_FRAME# ECAGND 7,17,19,22,24,28,34 PLT_RST# X2 ICH_PWROK VGATE 1 R408 1 @ R407 2 0_0402_5% 2 0_0402_5% 12mA 1 3 5 7 9 11 GND1 RES0 IAC_SDATA_OUT RES1 GND2 3.3V IAC_SYNC GND3 IAC_SDATA_IN GND4 IAC_RESET# IAC_BITCLK PM_PWROK 7,19 13 14 15 16 17 18 32.768KHZ_12.5P_1TJS125BJ2A251 SERIRQ PCI_CLKRUN# +3VS +3VALW 3 C292 4 GND GND GND GND GND XCLKO 1 R278 2 XCLKI @ 20M_0603_5% PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A 3 VOUT VDD LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 CLK_PCI_TPM 16 ACES_88018-124L +3VALW 2 Issued Date REED Switch Compal 0.5A per each pinElectronics, Compal Secret Data Security Classification 1 LID_SW# GND U1 APX9132ATI-TRL_SOT23-3 2 4 6 8 10 12 GND GND GND GND GND GND TP_DATA TP_CLK 6 14 15 16 17 18 19 25 28 29 EC_TX_P80_DATA 30 EC_RX_P80_CLK 31 ON_OFF 32 PWR_BLUE_LED# 34 NUMLED# 36 AGND SLP_S3# SLP_S5# EC_SMI# LID_SW# 0_0402_5% EC_FB_SCLK_R 2 EC_FB_SDATA_R 2 0_0402_5% EC_PME# 17 EC_PME# LAN_WOL_EN 19 LAN_WOL_EN FAN_SPEED1 4 FAN_SPEED1 19 SLP_S3# 19 SLP_S5# 19 EC_SMI# +5VS R271 10K_0402_5% 1 2 1 2 10K_0402_5% R270 2007/1/15 Deciphered Date 2008/1/15 Inc. Title BIOS & EC I/O Port THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: Thursday, January 10, 2008 Sheet 29 of 49 A B C D INT_KBD CONN. +3VALW 1 R297 100K_0402_5% 2 Power Button D15 PWR_ON-OFF_BTN# 2 1 51ON# 3 1 ON_OFF 29 51ON# 43 29 KSI[0..7] 29 KSO[0..15] JKB1 KSI[0..7] KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO[0..15] CHN202UPT SC-70 1 +3VALW 2 2 R296 4.7K_0402_5% 1 EC_ON 3 29 D Q26 S SSM3K7002FU_SC70-3 1 @ EC_ON D13 RLZ20A_LL34 2 1 C313 1000P_0402_50V7K~N 1 R291 0_0402_5% 2 2 G E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 GND1 GND2 KSO8 C449 100P_0402_25V8K KSI7 C235 100P_0402_25V8K KSI3 C239 100P_0402_25V8K KSI6 C236 100P_0402_25V8K KSO9 C249 100P_0402_25V8K KSI5 C237 100P_0402_25V8K KSI2 C240 100P_0402_25V8K KSO0 C441 100P_0402_25V8K KSI1 C241 100P_0402_25V8K KSO1 C442 100P_0402_25V8K KSO10 C248 100P_0402_25V8K KSO2 C443 100P_0402_25V8K KSO11 C247 100P_0402_25V8K KSI4 C238 100P_0402_25V8K KSI0 C242 100P_0402_25V8K KSO3 C444 100P_0402_25V8K KSO12 C246 100P_0402_25V8K KSO4 C445 100P_0402_25V8K KSO13 C245 100P_0402_25V8K KSO5 C446 100P_0402_25V8K KSO14 C244 100P_0402_25V8K KSO6 C447 100P_0402_25V8K KSO15 C243 100P_0402_25V8K KSO7 C448 100P_0402_25V8K 1 For EMI ACES_88514-2601 Function/B CONN. For ENE 2 1 R611 1 R612 29 EC_FB_SDATA Regulator for ENE sensor 29 EC_FB_SCLK C324 1 0_0603_5% @ 1 2 R880 10K_0603_1% SHDN# 2 GND 1 VIN BP 4 VOUT 5 1 @ R617 1 R618 @ 4,29,35 EC_SMB_DA2 4,29,35 EC_SMB_CK2 +3VS_FUN PWR_ON-OFF_BTN# LED_WLAN# FB_SDATA FN_SCLK 24 LED_WLAN# 2 0_0402_5% 2 0_0402_5% BLUETOOTH_LED# 32 BLUETOOTH_LED# For Cypress PWR_BLUE_LED# TOUCHKEY_TINT 1 NUMLED# R606 CAPSLED# SCRLED# 24,29 PWR_BLUE_LED# 29 TOUCHKEY_TINT 29 NUMLED# 29 CAPSLED# 29 SCRLED# U54 SATA_LED# 2 ODD_ACT_LED# 1 B A 3 1 @ 4 2 U33 Y 3 21 ODD_ACT_LED# SATA_LED# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND GND ACES_88512-1641 @ IDE_ACT_LED# G 18 @ C55 2 1 0.1U_0402_16V4Z P 5 +3VS C286 680P_0603_50V8J C250 2 1U_0402_6.3V4Z 1 3 1 2 3 4 5 6 7 8 9 10 11 12 2 0_0402_5% 13 14 15 16 17 18 IDE_ACT_LED# +3VALW RT9198-33PBR SOT-23 5P 2 JFN1 C287 680P_0603_50V8J 2 1 R901 1 2 +3VS Adjustable Output +5VS 2 4.7U_0603_6.3V +3VS_FUN 2 0_0402_5% 2 0_0402_5% 1 R622 MC74VHC1G08DFT2G SC70 5P 3 2 0_0402_5% @ Touch PAD/B CONN. TP/B TO M/B ACES_88514-0441 +5VS TP_CLK TP_DATA 100P_0402_25V8K 4 1 2 2007/1/15 3 @ D24 SM05T1G_SOT23-3~D @ 4 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 2 @ 2 1 2 G2 G1 4 3 2 1 JP1 1 TP_CLK TP_DATA C309 C300 0.01U_0402_16V7K 29 29 100P_0402_25V8K C310 1 6 5 4 3 2 1 2008/1/15 Deciphered Date Title PWR_OK/BTN/TP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: A B C D Sheet Thursday, January 10, 2008 E 31 of 49 +5VALW +USB_AS 0.1U_0402_16V4Z C228 1 2 3 4 USB_EN# GND IN IN EN# 8 7 6 5 OUT OUT OUT OC# 2 C434 1 + C223 R155 30K_0402_5% 150U_B2_6.3VM_R45M 1 2 80 mils 1 1 U12 RT9711PS SO 8P 2 SUSP 19 USB20_N0 USB20_N0 @ L1 WCM2012F2S-900T04_0805 1 1 2 2 4 4 R1 Q14 SSM3K7002FU_SC70-3 3 USB_OC#0 19 USB20_P0 D 2 G 1 0.1U_0402_16V4Z USB20_P0 19 R3 3 2 2 USB_P0 USB_N0 3 1 0_0402_5% 1 0_0402_5% JUSBP2 +USB_AS W=60mils S GND D+ DVCC 5 6 7 8 GND1 GND2 GND3 GND4 2 R154 100K_0402_5% @ 1 2 3 4 ALLTO_C10797-10403-L +USB_CS +5VALW U14 C253 1 2 3 4 USB_EN# 1 GND IN IN EN# 8 7 6 5 OUT OUT OUT OC# 1 80 mils R38 30K_0402_5% RT9711PS SO 8P 2 2 0.1U_0402_16V4Z USB_OC#3 19 2 0_0402_5% USB_OC#2 19 40,41,48 SUSP SUSP 1 1 D 3 R44 S Q13 SSM3K7002FU_SC70-3 2 G +USB_BS +5VALW U13 USB_EN# 1 C64 1 2 3 4 GND IN IN EN# OUT OUT OUT OC# 8 7 6 5 RT9711PS SO 8P 0.1U_0402_16V4Z CM1293-04SO_SOT23-6 1 80 mils R36 30K_0402_5% 2 CH1 2 Vn 3 CH2 CH4 4 Vp 5 CH3 6 USB_P0 2 USB_OC#1 19 1 +USB_AS CM1293-04SO_SOT23-6 CH1 Daughter board on right side CH4 4 Vp 5 CH3 6 USB20_N6 1 1 SUSP 3 Fingerprint JFP1 19 19 1 2 3 4 5 6 7 8 USB20_N6 USB20_P6 +3VS Vn CH2 +3VS Q8 SSM3K7002FU_SC70-3 2 G 3 2 D @ D21 W=60mils USB20_P7 USB20_N7 PAD T62 24 CH_CLK BT_OFF# 24 CH_DATA +3VS 31 BLUETOOTH_LED# BT_ACTIVE BT_OFF# +5VALW 19 19 USB20_N2 USB20_P2 19 19 USB20_N3 USB20_P3 12 11 10 9 8 7 6 5 4 3 2 1 12 11 10 9 8 7 6 5 4 3 2 1 JP3 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 GND GND 2 ACES_88460-1001 R222 10K_0402_5% 1 C315 10U_0805_10V4Z 2 29 USB_EN USB_EN USB_EN# 1 1 GND GND 6 5 4 3 2 1 JFE1 D 3 LEC TP1 8 7 6 5 4 3 2 1 GND2 GND1 JBT1 ACES_88512-0641 USB20_N9 USB20_P9 USB20_N1 USB20_P1 29 W_DISABLE# Bluetooth Felica Conn 19 19 19 19 +USB_BS 19 19 USB20_N9 USB20_P9 14 13 W=80mils ACES_88512-0641 +5VS +USB_CS @ D19 S USB20_P6 1 2 3 4 5 6 GND GND CONN@ ACES_87213-1200G USB_N0 S Q4 SSM3K7002FU_SC70-3 2 G Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/1/15 Deciphered Date 2008/1/15 Title USB/BlueTooth/FP/Felcia THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: Thursday, January 10, 2008 Sheet 32 of 49 5 4 C581 C582 C583 C584 C585 C586 C587 C588 C589 C590 C591 C592 C593 C594 C595 C596 C598 C599 C600 C601 C602 C603 C604 C605 C606 C607 C608 C609 C610 C611 C612 C613 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1 2 VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K VGA@ 0.1U_0402_16V7K 16 CLK_PCIE_VGA 16 CLK_PCIE_VGA# 7,17,19,22,24,28,29 PLT_RST# PEG_NRX_C_GTX_P0 PEG_NRX_C_GTX_N0 PEG_NRX_C_GTX_P1 PEG_NRX_C_GTX_N1 PEG_NRX_C_GTX_P2 PEG_NRX_C_GTX_N2 PEG_NRX_C_GTX_P3 PEG_NRX_C_GTX_N3 PEG_NRX_C_GTX_P4 PEG_NRX_C_GTX_N4 PEG_NRX_C_GTX_P5 PEG_NRX_C_GTX_N5 PEG_NRX_C_GTX_P6 PEG_NRX_C_GTX_N6 PEG_NRX_C_GTX_P7 PEG_NRX_C_GTX_N7 PEG_NRX_C_GTX_P8 PEG_NRX_C_GTX_N8 PEG_NRX_C_GTX_P9 PEG_NRX_C_GTX_N9 PEG_NRX_C_GTX_P10 PEG_NRX_C_GTX_N10 PEG_NRX_C_GTX_P11 PEG_NRX_C_GTX_N11 PEG_NRX_C_GTX_P12 PEG_NRX_C_GTX_N12 PEG_NRX_C_GTX_P13 PEG_NRX_C_GTX_N13 PEG_NRX_C_GTX_P14 PEG_NRX_C_GTX_N14 PEG_NRX_C_GTX_P15 PEG_NRX_C_GTX_N15 PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 CLK_PCIE_VGA CLK_PCIE_VGA# AE3 AE4 PEX_REFCLK PEX_REFCLK_N PLT_RST# AC6 PEX_RST_N G2 G3 J2 J1 K4 K1 M2 M1 N1 N2 N3 R3 MIOB_HSYNC MIOB_VSYNC MIOB_DE MIOB_CTL3 G4 F1 G1 F2 MIOB_CLKIN MIOB_CLKOUT MIOB_CLKOUT_N R2 K2 K3 MIOB_VREF J4 XTALOUT C2 XTALOUT C3 XTALOUTBUFF C1 XTALSSIN Y5 3 IN GND 2 1 G72M_BGA533 18P_0402_50V8J 2 VGA@ 2 2 VGA@ R550 VGA@2 1 22_0402_5% 2 2K_0402_5% RAM_CFG0 RAM_CFG1 PCI_IOBAR RAM_CFG2 RAM_CFG3 D PCI_DEVID2 37 PCI_DEVID0 37 PCI_DEVID1 37 R535 1 @ 2.2K_0402_5% 2 RAM_CFG2 37 RAM_CFG3 37 PCI_DEVID3 PCI_DEVID3 37 PEX_CFG3 PEX_CFG3 37 VGA termination, close chip PCI_DEVID4 R537 2 PCI_DEVID4 37 1 10K_0402_5% VGA@ VGA_CRT_R VGA_CRT_G VGA_CRT_B R539 1 R540 1 R541 1 VGA_HSYNC VGA_VSYNC VGA_CRT_R VGA_CRT_B VGA_CRT_G DACA_RSET DACA_VREF AB4 DACAVREF R538 1 2 124_0603_1% VGA@ 1 2 C597 0.01U_0402_16V7K VGA@ E6 F5 F4 D5 E4 L9 D6 R656 2 R648 2 1 10K_0402_5% VGA@ 1 10K_0402_5% VGA@ DACB_VREF E7 R649 2 1 10K_0402_5% VGA@ 15 15 15 15 15 +3VS VGA_CLK_LCD VGA_DDCCLK VGA_DDCDATA I2CB_SCL I2CB_SDA VGA_CLK_LCD VGA_DAT_LCD BAR2_SIZE R142 VGA@ 1 2 NB8M C 0 32Mb(Default) R273 VGA@ 1 2 1 16Mb R284 2.2K_0402_5% VGA@ I2CB_SCL 1 2 VGA_DDCCLK 15 VGA_DDCDATA 15 VGA_CLK_LCD 15 VGA_DAT_LCD 15 IFPAB_VPROBE 2 0.01U_0402_16V7K IFPCD_VPROBE 2 0.01U_0402_16V7K N6 M5 AF13 AF14 Enable(Default) 2.2K_0402_5% VGA_DAT_LCD I2CB_SDA 1 2 2.2K_0402_5% R285 VGA@ <---CRT <---LVDS +3VS PAD TP56 PAD TP55 PAD TP54 PAD TP53 PAD TP52 10K_0402_5% VGA@ 2 1 C614 @ 1 C615 @ 1 External Spread Spectrum C618 1 2 0.1U_0402_16V4Z VGA@ U42 7 VDD REF 5 HDCP PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N Disable +3VS D10 E10 F9 F10 E9 D8 C7 B7 AE27 AD27 AE26 AD26 AD25 D7 NB8M 0 2.2K_0402_5% DACB_HSYNC DACB_VSYNC DACB_RED DACB_BLUE DACB_GREEN DACB_IDUMP DACB_RSET JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N TESTMODE PCI_IOBAR 2 VGA@ 150_0402_1% 2 VGA@ 150_0402_1% 2 VGA@ 150_0402_1% 1 VGA_HSYNC VGA_VSYNC VGA_CRT_R VGA_CRT_B VGA_CRT_G I2CA_SCL I2CA_SDA I2CB_SCL I2CB_SDA I2CC_SCL I2CC_SDA I2CH_SCL I2CH_SDA +3VS RAM_CFG0 37 RAM_CFG1 37 PCI_DEVID2 PCI_DEVID0 PCI_DEVID1 OSC_OUT 1 XIN MODOUT 4 8 XOUT NC 3 2 VSS PD# 6 VGA@ 1 R554 B 2 OSC_SPREAD 22_0402_5% ASM3P1819N-SR_SO8 VGA@ R549 R616 1 @ 27MHZ_16PF_X7T027000BG1H-V~D VGA@ 1 C617 1 C616 OUT VGA@ R534 1 For Internal Thermal THER_ALERT# THER_ALERT# Sensor VGA_THER VGA_THER 29 R542 2 1 +3VS VGA@ 10K_0402_5% 2 200_0402_5% VGA@ OSC_SPREAD OSC_OUT 1 1 GND R552 R553 10K_0402_5% @ 10K_0402_5% 2 4 PAD T52 VGA_LVDDEN 15 G7X_ENBKL 15 AD4 AC4 AE1 AD2 AD1 U9 AD3 XTALIN TEST B1 CLK XTALIN NV_INVTPWM VGA_LVDDEN G7X_ENBKL DACA_HSYNC DACA_VSYNC DACA_RED DACA_BLUE DACA_GREEN DACA_IDUMP DACA_RSET IFPAB_VPROBE IFPCD_VPROBE B A9 D9 A10 B10 C10 C12 B12 A12 A13 B13 B15 A15 B16 MIOBD0 MIOBD1 MIOBD2 MIOBD3 MIOBD4 MIOBD5 MIOBD6 MIOBD7 MIOBD8 MIOBD9 MIOBD10 MIOBD11 DVO / GPIO AD5 AD6 AE6 AE7 AD7 AC7 AE9 AE10 AD10 AC10 AE12 AE13 AD13 AC13 AC15 AD15 AE15 AE16 AC18 AD18 AE18 AE19 AC21 AD21 AE21 AE22 AD22 AD23 AF25 AE25 AE24 AD24 HDMI Part 1 of 5 DACs D PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N I2C PEG_NTX_GRX_N[0..15] 9 PEG_NTX_GRX_N[0..15] AF1 AG2 AG3 AG4 AF4 AF5 AG6 AG7 AF7 AF8 AG9 AG10 AF10 AF11 AG12 AG13 AG15 AG16 AF16 AF17 AG18 AG19 AF19 AF20 AG21 AG22 AF22 AF23 AG24 AG25 AG26 AF27 PCI EXPRESS PEG_NTX_GRX_P0 PEG_NTX_GRX_N0 PEG_NTX_GRX_P1 PEG_NTX_GRX_N1 PEG_NTX_GRX_P2 PEG_NTX_GRX_N2 PEG_NTX_GRX_P3 PEG_NTX_GRX_N3 PEG_NTX_GRX_P4 PEG_NTX_GRX_N4 PEG_NTX_GRX_P5 PEG_NTX_GRX_N5 PEG_NTX_GRX_P6 PEG_NTX_GRX_N6 PEG_NTX_GRX_P7 PEG_NTX_GRX_N7 PEG_NTX_GRX_P8 PEG_NTX_GRX_N8 PEG_NTX_GRX_P9 PEG_NTX_GRX_N9 PEG_NTX_GRX_P10 PEG_NTX_GRX_N10 PEG_NTX_GRX_P11 PEG_NTX_GRX_N11 PEG_NTX_GRX_P12 PEG_NTX_GRX_N12 PEG_NTX_GRX_P13 PEG_NTX_GRX_N13 PEG_NTX_GRX_P14 PEG_NTX_GRX_N14 PEG_NTX_GRX_P15 PEG_NTX_GRX_N15 PEG_NTX_GRX_P[0..15] 9 PEG_NTX_GRX_P[0..15] 18P_0402_50V8J 1 U38A PEG_NRX_GTX_N[0..15] 9 PEG_NRX_GTX_N[0..15] C 2 PEG_NRX_GTX_P[0..15] 9 PEG_NRX_GTX_P[0..15] PEG_NRX_GTX_P0 PEG_NRX_GTX_N0 PEG_NRX_GTX_P1 PEG_NRX_GTX_N1 PEG_NRX_GTX_P2 PEG_NRX_GTX_N2 PEG_NRX_GTX_P3 PEG_NRX_GTX_N3 PEG_NRX_GTX_P4 PEG_NRX_GTX_N4 PEG_NRX_GTX_P5 PEG_NRX_GTX_N5 PEG_NRX_GTX_P6 PEG_NRX_GTX_N6 PEG_NRX_GTX_P7 PEG_NRX_GTX_N7 PEG_NRX_GTX_P8 PEG_NRX_GTX_N8 PEG_NRX_GTX_P9 PEG_NRX_GTX_N9 PEG_NRX_GTX_P10 PEG_NRX_GTX_N10 PEG_NRX_GTX_P11 PEG_NRX_GTX_N11 PEG_NRX_GTX_P12 PEG_NRX_GTX_N12 PEG_NRX_GTX_P13 PEG_NRX_GTX_N13 PEG_NRX_GTX_P14 PEG_NRX_GTX_N14 PEG_NRX_GTX_P15 PEG_NRX_GTX_N15 3 @ If External Spread Spectrum not stuff than stuff resistor A A 2006/07/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/07/10 Deciphered Date Title NB8M-GS Main THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Rev 0.1 Sheet Thursday, January 10, 2008 1 34 of 49 5 4 FBAD[0..63] 3 2 1 FBAD[0..63] 38 FBAA[0..11] FBAA[0..11] 38 D D FBBA[2..5] FBBA[2..5] 38 FBADQS[0..7] FBADQS[0..7] FBADQS#[0..7] FBADQS#[0..7] FBADQM#[0..7] 38 38 FBADQM#[0..7] 38 U38B G72M_BGA533 D21 F22 F20 A21 V27 W22 V22 V24 FBADQS_RN0 FBADQS_RN1 FBADQS_RN2 FBADQS_RN3 FBADQS_RN4 FBADQS_RN5 FBADQS_RN6 FBADQS_RN7 A22 E22 F21 B21 V26 W23 V23 W27 FBADQS#0 FBADQS#1 FBADQS#2 FBADQS#3 FBADQS#4 FBADQS#5 FBADQS#6 FBADQS#7 FBADQS_WP0 FBADQS_WP1 FBADQS_WP2 FBADQS_WP3 FBADQS_WP4 FBADQS_WP5 FBADQS_WP6 FBADQS_WP7 B22 D22 E21 C21 V25 W24 U24 W26 FBADQS0 FBADQS1 FBADQS2 FBADQS3 FBADQS4 FBADQS5 FBADQS6 FBADQS7 FB_VREF A16 FB_VREF1 FBA_CLK0 FBA_CLK0_N FBA_CLK1 FBA_CLK1_N FBA_CMD27 NC FBA_DEBUG L24 K23 M22 N22 M23 M24 K22 FBA_CKE 38 FBA_RST 38 R571 10K_0402_5% VGA@ PAD T54 FBARAS# 38 R562 10K_0402_5% VGA@ FBA_BA1 38 R564 1 2 @ 1K_0402_5% HDMI FBACAS# 38 R565 1 2 @ 1K_0402_5% IFPA_TXC IFPA_TXC_N IFPA_TXD0 IFPA_TXD0_N IFPA_TXD1 IFPA_TXD1_N IFPA_TXD2 IFPA_TXD2_N IFPA_TXD3 IFPA_TXD3_N IFPB_TXC IFPB_TXC_N IFPB_TXD4 IFPB_TXD4_N IFPB_TXD5 IFPB_TXD5_N IFPB_TXD6 IFPB_TXD6_N IFPB_TXD7 IFPB_TXD7_N U6 IFPAB_RSET V1 W1 T1 R1 T3 T2 V2 V3 IFPC_TXC IFPC_TXC_N IFPC_TXD0 IFPC_TXD0_N IFPC_TXD1 IFPC_TXD1_N IFPC_TXD2 IFPC_TXD2_N J3 IFPCD_RSET Part 3 of 5 NC 2 FBA_RST VGA@ 0_0402_5% T4 U4 N4 N5 R5 R4 T5 T6 R6 P6 W5 W6 W3 W2 AA2 AA3 AB1 AA1 AB3 AB2 LVDS/TMDS 38 38 38 38 1 FBA_BA2 FBACS0# FBAWE# FBA_BA0 VGA_LVDSAC+ VGA_LVDSACVGA_LVDSA0+ VGA_LVDSA0VGA_LVDSA1+ VGA_LVDSA1VGA_LVDSA2+ VGA_LVDSA2- GENERAL FBADQM0 FBADQM1 FBADQM2 FBADQM3 FBADQM4 FBADQM5 FBADQM6 FBADQM7 FBADQM#0 FBADQM#1 FBADQM#2 FBADQM#3 FBADQM#4 FBADQM#5 FBADQM#6 FBADQM#7 U38C 15 VGA_LVDSAC+ 15 VGA_LVDSAC15 VGA_LVDSA0+ 15 VGA_LVDSA015 VGA_LVDSA1+ 15 VGA_LVDSA115 VGA_LVDSA2+ 15 VGA_LVDSA2- 2 FBAA3 G27 FBAA0 D25 FBAA2 F26 FBAA1 F25 FBBA3 G25 FBBA4 J25 FBBA5 J27 FBA_BA2 M26 FBACS0# C27 FBAWE# C25 FBA_BA0 D24 FBA_CKE N27 FBA_RST_R R560 1 G24 FBBA2 J26 CMD14 M27 FBARAS# C26 FBAA11 M25 FBAA10 D26 FBA_BA1 D27 FBAA8 K26 FBAA9 K25 FBAA6 K24 FBAA5 F27 FBAA7 K27 FBAA4 G26 FBACAS# B27 N24 MIO_A_D0 MIO_A_D1 MIO_A_D2 MIO_A_D3 MIO_A_D4 MIO_A_D5 MIO_A_D6 MIO_A_D7 MIO_A_D8 MIO_A_D9 MIO_A_D10 MIO_A_HSYNC I2CS_SDA I2CS_SCL NC_2 GPIO14 GPIO13 MIO_A_VDDQ_0 MIO_A_VDDQ_1 MIO_A_VDDQ_2 F6 G6 J6 BUFRST_N A6 STEREO F7 1 2 PEX_PLL_TERM 37 SUB_VENDOR 37 PEX_CFG0 37 PEX_CFG1 37 PEX_CFG2 37 2 VGA@ 2K_0402_5% EC_SMB_DA2 4,29,31 EC_SMB_CK2 4,29,31 C C621 VGA@ 0.1U_0402_16V4Z +3VS SWAPRDY THERMDN THERMDP A7 C9 B9 ROM_SCLK ROM_SI ROM_SO ROMCS_N D2 F3 D3 D1 SERIAL G72M_BGA533 PEX_PLL_TERM A2 SUB_VENDOR B3 A3 D4 A4 B4 PEX_CFG0 B6 P4 PEX_CFG1 C6 PEX_CFG2 G5 V4 SLOT_CLOCK_CFG R5611 C4 EC_SMB_DA2 F11 F12 EC_SMB_CK2 D12 E12 +3VS C13 VGA@ 1 R572 2 10K_0402_5% VGA@ SLOT_CLOCK_CFG SHARE REFERENCE CLOCK +1.8VS 0 Disable 1 Enable(Default) 1 B R566 1K_0402_1% @ 2 FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 1 15mil 1 Part 2 of 5 2 FBAD0 FBAD1 FBAD2 FBAD3 FBAD4 FBAD5 FBAD6 FBAD7 FBAD8 FBAD9 FBAD10 FBAD11 FBAD12 FBAD13 FBAD14 FBAD15 FBAD16 FBAD17 FBAD18 FBAD19 FBAD20 FBAD21 FBAD22 FBAD23 FBAD24 FBAD25 FBAD26 FBAD27 FBAD28 FBAD29 FBAD30 FBAD31 FBAD32 FBAD33 FBAD34 FBAD35 FBAD36 FBAD37 FBAD38 FBAD39 FBAD40 FBAD41 FBAD42 FBAD43 FBAD44 FBAD45 FBAD46 FBAD47 FBAD48 FBAD49 FBAD50 FBAD51 FBAD52 FBAD53 FBAD54 FBAD55 FBAD56 FBAD57 FBAD58 FBAD59 FBAD60 FBAD61 FBAD62 FBAD63 FBACLK0 FBACLK0# FBACLK1 FBACLK1# 38 38 38 38 R568 FBA_DEBUG 1 C622 @ 0.1U_0402_16V4Z 1 R567 1K_0402_1% @ 2 2 B A26 C24 B24 A24 C22 A25 B25 D23 G22 J23 E24 F23 J24 F24 G23 H24 D16 E16 D17 F18 E19 E18 D20 D19 A18 B18 A19 B19 D18 C19 C16 C18 N26 N25 R25 R26 R27 T25 T27 T26 AB23 Y24 AB24 AB22 AC24 AC22 AA23 AA22 T24 T23 R24 R23 R22 T22 N23 P24 AA24 AA27 AA26 AB25 AB26 AB27 AA25 W25 MEMORY INTERFACE C FBAD0 FBAD1 FBAD2 FBAD3 FBAD4 FBAD5 FBAD6 FBAD7 FBAD8 FBAD9 FBAD10 FBAD11 FBAD12 FBAD13 FBAD14 FBAD15 FBAD16 FBAD17 FBAD18 FBAD19 FBAD20 FBAD21 FBAD22 FBAD23 FBAD24 FBAD25 FBAD26 FBAD27 FBAD28 FBAD29 FBAD30 FBAD31 FBAD32 FBAD33 FBAD34 FBAD35 FBAD36 FBAD37 FBAD38 FBAD39 FBAD40 FBAD41 FBAD42 FBAD43 FBAD44 FBAD45 FBAD46 FBAD47 FBAD48 FBAD49 FBAD50 FBAD51 FBAD52 FBAD53 FBAD54 FBAD55 FBAD56 FBAD57 FBAD58 FBAD59 FBAD60 FBAD61 FBAD62 FBAD63 2 FBA_RST 0_0402_5% @ VGA@ FB_VREF1=0.5 x FBVDD A A 2006/07/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/07/10 Deciphered Date Title NB8M-GS Memory THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Rev 0.1 Sheet Thursday, January 10, 2008 1 35 of 49 5 4 3 2 1 +VGA_CORE +1.2VS +VGA_CORE U38D D C623 VGA@ 1 C624 VGA@ 2 0.1U_0402_16V4Z 1 2 C625 VGA@ 1 2 0.1U_0402_16V4Z C626 VGA@ 0.1U_0402_16V4Z 1 2 C627 VGA@ 1 C628 VGA@ 2 0.1U_0402_16V4Z 1 2 0.1U_0402_16V4Z +NV_PLLVDD 0.47U_0402_6.3V6K C649 1 VGA@ 2 0.47U_0402_6.3V6K C650 VGA@ 1 2 1 C651 VGA@ 2 1 C652 VGA@ 2 0.1U_0402_16V4Z C635 VGA@ 1 C636 VGA@ 2 1 2 0.47U_0402_6.3V6K 0.47U_0402_6.3V6K 0.1U_0402_16V4Z +VGA_CORE 0.47U_0402_6.3V6K 1 1 1 C656 C657 C658 1U_0805_10V7K VGA@ 2 0.47U_0402_6.3V6K 1 C659 1 VGA@ VGA@ VGA@ 2 2 2 0.47U_0402_6.3V6K C 2 C660 1U_0805_10V7K VGA@ Average to place around +VGA_CORE plane. +3VS +3VS C666 1 C667 VGA@ 1U_0603_10V4Z 2 1 1 VGA@ 2 0.1U_0402_16V4Z R574 2 0_0603_5% VGA@ W9 W10 W11 W12 VDD_LP_0 VDD_LP_1 VDD_LP_2 VDD_LP_3 Part 4 of 5 PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 PEX_IOVDD_6 PEX_IOVDD_7 PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14 PEX_IOVDDQ_15 PEX_IOVDDQ_16 PEX_IOVDDQ_17 PEX_IOVDDQ_18 Y6 AA5 MIOB_VDDQ_0 MIOB_VDDQ_1 MIOB_VDDQ_2 K5 K6 L6 MIOBCAL_PD_VDDQ J5 IFPA_IOVDD IFPB_IOVDD IFPC_IOVDD IFPAB_PLLVDD IFPCD_PLLVDD VDD33_0 VDD33_1 VDD33_2 VDD33_3 VDD33_4 VDD33_5 DACA_VDD DACB_VDD PLLVDD FBA_PLLAVDD E15 F15 F16 J17 J18 L19 N19 R19 U19 W19 FBVTT_0 FBVTT_1 FBVTT_2 FBVTT_3 FBVTT_4 FBVTT_5 FBVTT_6 FBVTT_7 FBVTT_8 FBVTT_9 D11 NC +NV_PLLVDD 8mA G72M_BGA533 W4 Y4 L4 1 C629 VGA@ C630 VGA@ 2 1 VGA@ 2 0.1U_0402_16V4Z 1 C640 VGA@ 1U_0402_6.3V4K C631 1 2 VGA@ VGA@ 1 2 4.7U_0603_6.3V C646 VGA@ H4 VGA@ 2 0.1U_0402_16V4Z 2 1U_0402_6.3V4K 1 C643 VGA@ 2 D14 D15 D 2 4.7U_0603_6.3V 1 C647 VGA@ 2 1U_0402_6.3V4K +1.2VS +PEX_PLLAVDD +PEX_PLLDVDD 0.1U_0402_16V4Z +3VS 1 C662 VGA@ 2 L37 VGA@ +PEX_PLLAVDD_L 1 2 MBK1608121YZF_0603 1 C655 VGA@ 4.7U_0805_10V4Z 2 +PEX_PLLAVDD 1 1 C653 C654 VGA@ VGA@ 2 2 0.01U_0402_16V7K 0.1U_0402_16V4Z C +IFPA_IOVDD +PEX_PLLDVDD 40mA VGA@ D13 40mA H_PLLVDD 1 1U_0402_6.3V4K 0.1U_0402_16V4Z 1 1 C641 C642 2 C632 1 R113 2 VGA@ 10K_0402_5% +IFPAB_PLLVDD V5 M4 1 R116 2 10K_0402_5% VGA@ +DACA_VDD AE2 F8 2 1 R292 10K_0402_5% FBCAL_PD_VDDQ FBVDDQ_0 FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 0.1U_0402_16V4Z W17 W18 AB10 AB11 AB14 AB15 AB20 AB21 AA4 AB5 AB6 AB7 AB8 AB9 AB12 AB13 AB16 AB17 AB18 AB19 AC9 AC11 AC12 AC16 AC17 AC19 AC20 PEX_PLLAVDD PEX_PLLDVDD +1.8VS VGA@ VGA@ 2 2 0.47U_0402_6.3V6K +VGA_CORE 1 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 F13 F14 J12 J13 J15 J16 0.022U_0402_16V7K 1 C669 C670 1400mA J9 J10 J11 L12 L13 L15 L16 M9 M11 M12 M13 M14 M15 M16 M17 N9 N11 N17 R9 R11 R17 T9 T11 T12 T13 T14 T15 T16 T17 U12 U13 U15 U16 W13 W15 W16 POWER 1U_0805_10V7K 1 C664 VGA@ VGA@ 2 2 0.01U_0402_16V7K 0.1U_0402_16V4Z +PLLVDD +1.8VS +FBA_PLLAVDD L39 VGA@ +1.8VS +H_PLLVDD VGA@ 1 C663 +IFPA_IOVDD 4700P_0402_25V7K 4700P_0402_25V7K R573 2 1 45.3_0402_1%~D F17 4700P_0402_25V7K 1U_0402_6.3V4Z 1U_0402_6.3V4Z F19 1 1 1 1 1 1 C674 C675 C676 C677 C678 C679 J19 J22 VGA@ VGA@ VGA@ VGA@ VGA@ L22 2 2 2 2 2 2 VGA@ M19 P22 4700P_0402_25V7K 4700P_0402_25V7K 22U_0805_6.3V4Z T19 U22 Y22 VGA@ B +PLLVDD 1 +1.8VS 2 1 C680 VGA@ 2 470P_0402_50V7K 1 C681 VGA@ 1 C671 2 VGA@ VGA@ 2 1 2 MBK1608121YZF_0603 1 C672 2 4.7U_0603_6.3V VGA@ C673 470P_0402_50V7K +1.8VS L40 +IFPAB_PLLVDD 4700P_0402_25V7K 1 2 MBK1608121YZF_0603 1 1 1 VGA@ 4.7U_0603_6.3V C687 C688 VGA@ C689 VGA@ VGA@ 2 2 2 470P_0402_50V7K B L43 +1.2VS MBK1608121YZF_0603 VGA@ 2 1 4700P_0402_25V7K 30mA 1 1 VGA@ 0.1U_0402_16V4Z 2 2 C693 L47 +1.2VS MBK1608121YZF_0603 VGA@ 2 1 +H_PLLVDD 1 1 VGA@ 0.1U_0402_16V4Z 2 2 C699 1 C701 VGA@ 2 L42 +3VS MBK1608121YZF_0603 VGA@ 2 1 +DACA_VDD 4700P_0402_25V7K 1 C702 VGA@ 4.7U_0805_10V4Z +FBA_PLLAVDD 470P_0402_50V7K 1 4.7U_0603_6.3V VGA@ C695 2 C694 VGA@ 1 A L48 +1.2VS MBK1608121YZF_0603 VGA@ 2 1 1 C703 VGA@ 2 C690 VGA@ 2 1 C691 VGA@ 2 1 2 4.7U_0603_6.3V VGA@ C692 470P_0402_50V7K C704 VGA@ A 2 2.2U_0603_6.3V6K 4700P_0402_25V7K 2006/07/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/07/10 Deciphered Date Title NB8M-GS Power THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Rev 0.1 Sheet Thursday, January 10, 2008 1 36 of 49 5 4 3 2 STRAPS 1 PIN DESCRIPTION Value Value U38E U17 U23 U26 V9 V19 W14 Y2 Y5 Y23 Y26 AC2 AC8 AC14 AC23 AC26 AD8 AD9 AD11 AD12 AD14 AD16 AD17 AD19 AD20 AC5 AF2 AF3 AF6 AF9 AF12 AF15 AF18 AF21 AF24 AF26 SUB_VENDOR MIO_A_D1 VBIOS on card (pull high) VBIOS with system BIOS (pull down) PEX_PLL_TERM MIO_A_D0 PCI-E PEX_CFG[3:0] MIOAD [9,8,6] Recommended for G8x 0001 0001 ---> Qimonda 16Mx32 0010 ---> Hynix 16Mx32 0011 ---> Samsung 16Mx32 0011 PLL termination 0 0---->Enable (Default) 1---->Disable D 0 MIOBD_HSYNC 35 SUB_VENDOR SUB_VENDOR R575 1 2 2K_0402_5% RAM_CFG[3:0] MIOAD0 VGA@ MIOAD1 MIOAD8 SUB_VENDOR MIOAD9 0 N0 VIDEO BIOS ROM 1 BIOS ROM is present(Default) PCI_DEVID[3:0] VIPD[5:3] MIOA_HSYNC G73M-xxxx8 G72M-0x01D8 NB8M-GS : 0X0427 NB8M-SE : 0X0428 0111 G72MV-0x01D7 TBD/TBD 0111 1000 C PAD T53 H5 FBA_PLLGND C15 FBCAL_PU_GND FBCAL_TERM_GND E13 H22 R576 24.9_0402_1% 2 1 40.2_0402_1% R605 VGA@1 VGA@2 +3VS 1 1 1 R588 R589 R590 @ @ @ 2 R587 @ 2 VGA@ 2 R586 @ 2 R585 @ 2 R584 VGA@ 2 R583 VGA@ 2 R582 VGA@ 2 R581 2 1 1 1 1 1 1 1 R580 @ 2 R579 @ RAM_CFG0 RAM_CFG1 RAM_CFG2 RAM_CFG3 PCI_DEVID0 PCI_DEVID1 PCI_DEVID2 PCI_DEVID3 PCI_DEVID4 PEX_CFG0 PEX_CFG1 PEX_CFG2 PEX_CFG3 PEX_PLL_TERM R593 VGA@ R594 VGA@ 2 R592 @ 2 2 R591 @ 1 B 1 RAM_CFG0 RAM_CFG1 RAM_CFG2 RAM_CFG3 PCI_DEVID0 PCI_DEVID1 PCI_DEVID2 PCI_DEVID3 PCI_DEVID4 PEX_CFG0 PEX_CFG1 PEX_CFG2 PEX_CFG3 PEX_PLL_TERM 1 34 34 34 34 34 34 34 34 34 35 35 35 34 35 B R578 VGA@ 2 2 R577 VGA@ 1 10K_0402_5% 10K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 10K_0402_5% 10K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% G72M_BGA533 VGA@ 1 PLLGND M3 AA6 2 PEX_PLLGND 1 MIOBCAL_PU_GND 2 IFPAB_PLLGND IFPCD_PLLGND V6 M6 1 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 2 H2 H6 H23 H26 J14 K9 K19 L2 L5 L11 L14 L17 L23 L26 N12 N13 N14 N15 N16 P2 P5 P9 P11 P12 P13 P14 P15 P16 P17 P19 P23 P26 R12 R13 R14 R15 R16 U2 U5 U11 U14 Part 5 of 5 1 C GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND D B2 B5 B8 B11 B14 B17 B20 B23 B26 E2 E5 E8 E11 E14 E17 E20 E23 E26 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% A Bandwidth RAM Type Vendor FULL R17 32M R11 Samsung R20, R19 (10*12.5) Infineon GDDR2(400): SA00000S800 (HYB18T256161AFL-25) Infineon GDDR2(350): SA00000T700 (HYB18T256161AF-28) HALF R12 16M R16 Hynix R18, R19 (11*13) Samsung GDDR2 (400): SA00000FG10 (K4N56163QF-ZC25) Samsung GDDR2 (350): SA00000TB00 (K4N56163QF-ZC2A) Infineon R18, R21 (8*13) Hynix GDDR2 (400): SA00000FF10 (HY5PS561621AFP-25) Hynix GDDR2 (350): SA00000TJ00 (HY5PS561621AFP-28) Package 2006/07/10 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/07/10 Deciphered Date Title NB8M-GS GND & STRAP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 A 2 Rev 0.1 Sheet Thursday, January 10, 2008 1 37 of 49 5 4 3 2 1 35 +1.8VS FBAD[0..63] FBAD[0..63] FBADQS#[0..7] 1 +1.8VS R917 1.05K_0402_1% VGA@ 2 +VREFA3 K4 H2 K3 M4 K9 H11 K10 L9 K11 M9 K2 L4 G4 G9 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 BA0 BA1 FBADQM#0 FBADQM#2 FBADQM#3 FBADQM#1 E3 E10 N10 N3 DM0 DM1 DM2 DM3 FBADQS0 FBADQS2 FBADQS3 FBADQS1 D2 D11 P11 P2 WDQS0 WDQS1 WDQS2 WDQS3 +VREFA0 +VREFA1 H1 H12 J2 J3 VREF VREF RFU1 RFU2 FBARAS# FBACAS# FBAWE# FBACS0# H3 F4 H9 F9 RAS# CAS# WE# CS# FBA_CKE FBACLK0 FBACLK0# H4 J11 J10 CKE CK CK# FBADQS#0 FBADQS#2 FBADQS#3 FBADQS#1 D3 D10 P10 P3 RDQS0 RDQS1 RDQS2 RDQS3 A2 A11 F1 F12 M1 M12 V2 V11 VDD VDD VDD VDD VDD VDD VDD VDD V4 V9 H10 SEN RESET BA2 J1 J12 VSSA VSSA 1 +VREFA1 1 2 C887 0.01U_0402_16V7K VGA@ 2 R918 2.49K_0402_1% VGA@ C 35 35 35 35 FBARAS# FBACAS# FBAWE# FBACS0# 35 FBA_CKE A4 A9 1 2 R919 243_0402_1% VGA@ +1.8VS FBA_RST FBA_BA2 FBA_RST VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A1 A12 C1 C4 C9 C12 E1 E4 E9 E12 J4 J9 N1 N4 N9 N12 R1 R4 R9 R12 V1 V12 VDDA VDDA K1 K12 FBAD1 FBAD3 FBAD2 FBAD5 FBAD7 FBAD4 FBAD0 FBAD6 FBAD16 FBAD17 FBAD18 FBAD19 FBAD20 FBAD21 FBAD22 FBAD23 FBAD27 FBAD25 FBAD24 FBAD26 FBAD31 FBAD28 FBAD30 FBAD29 FBAD10 FBAD12 FBAD9 FBAD15 FBAD8 FBAD13 FBAD11 FBAD14 +1.8VS FBAA0 FBAA1 FBBA2 FBBA3 FBBA4 FBBA5 FBAA6 FBAA7 FBAA8 FBAA9 FBAA10 FBAA11 FBA_BA0 FBA_BA1 K4 H2 K3 M4 K9 H11 K10 L9 K11 M9 K2 L4 G4 G9 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 BA0 BA1 FBADQM#5 FBADQM#4 FBADQM#6 FBADQM#7 E3 E10 N10 N3 DM0 DM1 DM2 DM3 FBADQS5 FBADQS4 FBADQS6 FBADQS7 D2 D11 P11 P2 WDQS0 WDQS1 WDQS2 WDQS3 +VREFA2 +VREFA3 H1 H12 J2 J3 VREF VREF RFU1 RFU2 FBARAS# FBACAS# FBAWE# FBACS0# H3 F4 H9 F9 RAS# CAS# WE# CS# FBA_CKE FBACLK1 FBACLK1# H4 J11 J10 CKE CK CK# FBADQS#5 FBADQS#4 FBADQS#6 FBADQS#7 D3 D10 P10 P3 RDQS0 RDQS1 RDQS2 RDQS3 A2 A11 F1 F12 M1 M12 V2 V11 VDD VDD VDD VDD VDD VDD VDD VDD V4 V9 H10 SEN RESET BA2 J1 J12 VSSA VSSA A4 A9 1 2 R920 243_0402_1% VGA@ +1.8VS +1.8VS FBA_RST FBA_BA2 1 C889 0.1U_0402_16V4Z VGA@2 K4J52324QE-BC14_FBGA136~D VGA@ ZQ MF 1 C890 0.1U_0402_16V4Z 2 VGA@ A3 A10 G1 G12 L1 L12 V3 V10 35 ZQ MF DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 B2 B3 C2 C3 E2 F3 F2 G3 B11 B10 C11 C10 E11 F10 F11 G10 M11 L10 N11 M10 R11 R10 T11 T10 M2 L3 N2 M3 R2 R3 T2 T3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 B2 B3 C2 C3 E2 F3 F2 G3 B11 B10 C11 C10 E11 F10 F11 G10 M11 L10 N11 M10 R11 R10 T11 T10 M2 L3 N2 M3 R2 R3 T2 T3 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A1 A12 C1 C4 C9 C12 E1 E4 E9 E12 J4 J9 N1 N4 N9 N12 R1 R4 R9 R12 V1 V12 VDDA VDDA K1 K12 FBAD40 FBAD41 FBAD42 FBAD43 FBAD44 FBAD45 FBAD46 FBAD47 FBAD35 FBAD34 FBAD32 FBAD33 FBAD39 FBAD36 FBAD37 FBAD38 FBAD51 FBAD48 FBAD53 FBAD50 FBAD52 FBAD49 FBAD54 FBAD55 FBAD59 FBAD57 FBAD61 FBAD62 FBAD60 FBAD63 FBAD56 FBAD58 DQMA#[0..7] 35 FBAA[0..11] 35 FBBA[2..5] 35 FBA_BA0 35 FBA_BA1 35 FBA_BA2 FBAA[0..11] FBBA[2..5] FBA_BA0 D FBA_BA1 FBA_BA2 +1.8VS C +1.8VS 1 1 C891 0.1U_0402_16V4Z VGA@2 K4J52324QE-BC14_FBGA136~D VGA@ 2 VSS VSS VSS VSS VSS VSS VSS VSS 2 C886 0.01U_0402_16V7K VGA@ 2 D 1 FBAA0 FBAA1 FBAA2 FBAA3 FBAA4 FBAA5 FBAA6 FBAA7 FBAA8 FBAA9 FBAA10 FBAA11 FBA_BA0 FBA_BA1 FBADQS[0..7] 35 FBADQM#[0..7] C892 0.1U_0402_16V4Z VGA@ A3 A10 G1 G12 L1 L12 V3 V10 1 +VREFA0 R912 2.49K_0402_1% VGA@ B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2 L11 P1 P4 P9 P12 T1 T4 T9 T12 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 2 +VREFA2 U52 35 FBADQS[0..7] VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ U51 VSS VSS VSS VSS VSS VSS VSS VSS R908 1.05K_0402_1% VGA@ B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2 L11 P1 P4 P9 P12 T1 T4 T9 T12 1 35 FBADQS#[0..7] B B GDDR3 BGA MEMORY +1.8VS VGA@ 2 2 1000P_0402_50V7K VGA@ VGA@ VGA@ VGA@ 2 2 2 0.01U_0402_16V7K 0.1U_0402_16V4Z 2 VGA@ GDDR3 BGA MEMORY +1.8VS 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1 1 1 1 1 1 1 1 C894 C895 C896 C897 C898 C899 C900 C901 VGA@ 2 0.1U_0402_16V4Z 2 VGA@ 10U_0805_10V4Z 1 1 C902 C903 VGA@ 2 1U_0402_6.3V4Z 1 0.01U_0402_16V7K 0.1U_0402_16V4Z 1 1 1 1 C905 C906 C907 C908 C904 VGA@ VGA@ 2 2 22U_0805_6.3V6M VGA@ 2 2 1000P_0402_50V7K VGA@ 2 2 0.01U_0402_16V7K VGA@ 0.1U_0402_16V4Z 1 C909 C910 VGA@ 2 0.1U_0402_16V4Z 2 VGA@ 1 1U_0402_6.3V4Z 1 C912 C911 VGA@ 2 0.1U_0402_16V4Z 2 VGA@ 1 10U_0805_10V4Z 1 C914 C913 VGA@ 2 1U_0402_6.3V4Z 1 C915 VGA@ VGA@ 2 2 22U_0805_6.3V6M FBACLK1 FBACLK1 1 35 VGA@ 1 R610 243_0402_1% VGA@ FBACLK0 2 FBACLK0 1 35 A R607 243_0402_1% VGA@ FBACLK1# A FBACLK1# 2 35 35 FBACLK0# FBACLK0# Compal Secret Data Security Classification Issued Date 2007/02/12 2008/02/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Compal Electronics, Inc. VRAM GDDR3 A Document Number Rev 0.1 LA-4231P Thursday, January 10, 2008 Sheet 1 38 of 49 5 4 3 2 Q35 1 +3VS @ R850 2 R693 1 106 2 0_0402_5%~D 67 73 79 81 4 113 111 112 107 108 110 117 114 MC_3V# SDCLK_MSCLK SDD3 SDD2 SDD1 SDD0 SD_CMD SD_WP SDCD# MS_D1/XD_D7 XD_D6 XD_D5 XD_D4 MS_BS/XD_D3 MS_D0/XD_D2 MS_D2/XD_D1 MS_D3/XD_D0 XD_CE# XD_RB# XD_CLE XD_ALE XD_WE# XD_RE# XD_WPO# MS_CD# XD_CD# 95 93 89 87 88 90 94 96 119 100 118 109 105 101 98 99 97 XDD7_MSD1 XD_D6 XD_D5 XD_D4 XDD3_MSBS XDD2_MSD0 XDD1_MSD2 XDD0_MSD3 XDCE# XDRB# XDCLE XDALE XDWE# XDRE# XDWP# MSCD# XDCD# +3VS 1 2 1 2 C821 2 IEEE1394_TPBN0 TPA+ TPATPB+ TPB- GND GND GND GND OZ129XO +3VS_CR +3VS SDCLK 1 1 85 86 MC_3V# 1 C878 1U 10V Z Y5V 0603 1 1 2 2 2 1 5.1K_0402_1% 1 270P_0402_50V7K 2 C824 56.2_0402_1% 56.2_0402_1% R833 Q82 2 MC_3V# G S SSM3K7002FU_SC70-3 1 2 2 2 C1188 1U 10V Z Y5V 0603 MSCLK 1 C1149 10P_0402_50V8J @ 2 82 80 77 70 69 65 +3VS_CR B JSD1 0_0603_5% 1 2 R879 3 XD-VCC XDD0_MSD3 XDD1_MSD2 XDD2_MSD0 XDD3_MSBS XD_D4 XD_D5 XD_D6 XDD7_MSD1 R873 R874 R938 R948 R957 R964 R941 R951 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D XDD0 XDD1 XDD2 XDD3 XDD4 XDD5 XDD6 XDD7 32 10 9 8 7 6 5 4 XD-D0 XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7 XDWE# XDWP# XDALE XDCD# XDRB# XDRE# XDCE# XDCLE R960 R967 R945 R955 R952 R961 R936 R946 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D XDWE XDWP XD_ALE XDCD XDRB XDRE XDCE XD_CLE 34 33 35 40 39 38 37 36 XD-WE XD-WP XD-ALE XD-CD XD-R/B XD-RE XD-CE XD-CLE 11 31 41 42 7in1-GND 7in1-GND 7in1-GND 7in1-GND 5 6 7 8 7 IN 1 CONN SD-VCC MS-VCC 21 28 SD_CLK SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-DAT4 SD-DAT5 SD-DAT6 SD-DAT7 20 14 12 30 29 27 23 18 16 SDCLK SDDAT0 SDDAT1 SDDAT2 SDDAT3 SDDAT4 SDDAT5 SDDAT6 SDDAT7 R713 R940 R950 R959 R966 R944 R953 R962 R937 SD-CD SD-WP SD-CMD 1 2 25 SDCD SDWP SDCMD R947 1 R956 1 R963 1 2 0_0402_5%~D 2 0_0402_5%~D 2 0_0402_5%~D SDCD# SD_WP SD_CMD MS-SCLK MS-BS MS-INS 26 13 22 MSCLK MSBS MSINS R714 1 R939 1 R949 1 2 22_0402_5% 2 0_0402_5%~D 2 0_0402_5%~D SDCLK_MSCLK XDD3_MSBS MSCD# MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 17 15 19 24 MSDATA0 MSDATA1 MSDATA2 MSDATA3 R958 R965 R943 R954 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 22_0402_5% 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D SDCLK_MSCLK SDD0 SDD1 SDD2 SDD3 MMCD4 MMCD5 MMCD6 MMCD7 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D XDD2_MSD0 XDD7_MSD1 XDD1_MSD2 XDD0_MSD3 TAITW_R015-A10-LM R834 A R835 Compal Secret Data Security Classification Issued Date Layout Note: Place close to OZ129 Chipset. 2007/09/01 2008/09/01 Deciphered Date Title 4 Compal Electronics, Inc. OZ129_Card Reader / 1394 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4131P Date: 5 1 2 +3VS_CR OZ129TN_LQFP128_14X14 SUYIN_020204FR004S506ZL~D conn@ A C1187 1U 10V Z Y5V 0603 D MMCD4 MMCD5 MMCD6 MMCD7 C1146 10P_0402_50V8J @ R932 470_0402_5% Q81 AO3413_SOT23-3 2 +3VS_CR 1 2 8 9 10 13 126 127 128 24.576MHz_16P_1BG24576CKIA~D C J139A1 4 3 2 1 OZ129XI 15P_0402_50V8J 3 MEDIA_LED IEEE1394_TPAP0 IEEE1394_TPAN0 IEEE1394_TPBP0 C819 2 1 15P_0402_50V8J X3 1U_0603_10V4Z 56.2_0402_1% 56.2_0402_1% 1 R831 Layout Note: Place close to OZ129 and Shield GND. C822 2 1 IEEE1394_TPBIAS0 R830 R942 22K_0402_5% 2 7 102 103 122 MC_3V# SD_CLK/MS_CLK SD_D3 SD_D2 SD_D1 SD_D0 SD_CMD SD_WP SD_CD# NC NC NC NC NC NC NC NC 12 16 33 66 68 104 115 116 121 123 124 LED behave: Idel ---------> low Accress data --> always high B IEEE1394_TPBIAS0 IEEE1394_TPAP0 IEEE1394_TPAN0 IEEE1394_TPBP0 IEEE1394_TPBN0 PHY_TEST0 PHY_TEST1 GND GND GND GND GND GND GND GND GND GND GND 19,29 PCI_CLKRUN# 1 100K_0402_5% 76 75 74 72 71 1 16 CLK_PCI_CB 17 PCI_DEVSEL# 17 PCI_FRAME# 17 PCI_IRDY# 17 PCI_TRDY# 17 PCI_STOP# 17 PCI_PAR 17 PCI_REQ0# 17 PCI_GNT0# 17,21 PCI_RST# 17 PCI_PIRQG# 29 CB_PME# TPBIAS TPA+ TPATPB+ TPB- D AGND AGND AGND AGND AGND AGND 2 OZ129XI OZ129XO 2 3 IDSEL PCI_CLK DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PCI_REQ# PCI_GNT# PCI_RST# INTA# PME# CLKRUN# 15 14 91 92 120 125 2 1 100_0402_5% 83 84 2 1 2 5 45 42 39 40 41 43 44 17 18 1 11 3 6 R691 PCI_AD21 AVCC AVCC AVCC AVCC CBS_IDSEL CLK_PCI_CB PCI_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_PAR PCI_REQ0# PCI_GNT0# PCI_RST# PCI_PIRQG# CB_PME# VCC3.3 VCC3.3 VCC3.3 VCC3.3 C/BE3# C/BE2# C/BE1# C/BE0# VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 26 56 PCI_VCC PCI_VCC 28 38 46 55 78 XI XO OZ129 5.9K_0402_1% 2 1 1 2 PCI_CBE#3 PCI_CBE#2 PCI_CBE#1 PCI_CBE#0 REF R520 1 G AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 1 C925 19 20 21 22 23 24 25 27 29 30 31 32 34 35 36 37 47 48 49 50 51 52 53 54 57 58 59 60 61 62 63 64 +3VS_PHY 0_0603_5% 1 2 R878 +3VS 4.7U_0805_10V4Z PCI_CBE#3 PCI_CBE#2 PCI_CBE#1 PCI_CBE#0 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 2 0.1U_0402_10V6K 17 17 17 17 U46 1 C922 C +3VS_PHY C926 0.1U_0402_10V6K 4.7P_0402_50V8C 2 10_0402_5%~D 1 C823 @ 2 C1139 CLK_PCI_CB 1 0.1U_0402_10V6K 17 PCI_AD[0..31] R832 @ C1142 4.7U_0805_10V4Z 2 C1141 2 1 0.1U_0402_10V6K 1 C1138 0.1U_0402_10V6K C1186 D 2 C1136 1 C1137 4.7U_0805_10V4Z R666 1 2 100K_0402_5% G SUSP 0.01U_0402_25V7K~N 32,41,48 0.1U_0402_10V6K C1140 4.7U_0805_10V4Z +1.8VS_CB D S 3 D AO3413_SOT23 S +1.8V 1 +3VS 3 2 Thursday, January 10, 2008 Sheet 1 40 of 40 A B +3VALW to +3VS Transfer +3VALW C +5VALW to +5VS Transfer D +1.8V to +1.8VS Transfer +3VS B+_BIAS +5VALW +5VS +1.8V SI4800DY_SO8 2 10U_0805_10V4Z~N 2 1 SUSP 1 2 R197 1 100K_0402_5% D 3 RUNON Q18 S SSM3K7002FU_SC70-3 2 2 G C465 2 1 1 C256 C278 S S S G 2 D D D D 1 2 3 4 1 SI4800DY_SO8 2 10U_0805_10V4Z~N 2 C284 1 VGA@ C283 10U_0805_10V4Z~N 2 2 0.1U_0402_16V4Z~N 3VS_GATE RUNON 1 2 1 5VS_GATE R267 C279 47K_0402_5% 0.01U_0402_25V7K~N 2 0.1U_0402_16V4Z~N C264 0.01U_0402_25V7K~N 1 1 1 8 7 6 5 4.7A U41 1 C271 S S S G U39 VGA_PWGOD# SUSP 1 C211 +CPU_CORE R559 47K_0402_5% 1 D D D D 10U_0805_10V4Z~N 1 2 3 4 2 G 1 R665 2 @ 0_0402_5% 2 +VCCP 0.1U_0402_16V4Z~N 3 1 R198 8 7 6 5 +1.8VS B+_BIAS U40 330K_0402_5% E 8 7 6 5 1 D D D D 10U_0805_10V4Z~N 1 2 3 4 S S S G C727 SI4800DY_SO8 2 10U_0805_10V4Z~N VGA@ VGA@ 1 1 C728 0.1U_0402_16V4Z~N 2 VGA@ 2 C697 VGA@ 1 1.8VS ON 1 1.8VS_GATE 2 R608 1 100K_0402_5% C696 VGA@ D 0.01U_0402_25V7K~N 2 VGA@ Q48 S SSM3K7002FU_SC70-3 VGA@ +3VALW 2 1 2 R409 SYSON D S Q42 SSM3K7002FU_SC70-3 2 G 2 28,29,46 1 SYSON# SYSON 3 2 100K_0402_5% 1 R365 10K_0402_5% +5VALW +VGA_CORE +1.8VS 1 1 100K_0402_5% 1 R609 470_0402_5% 470_0402_5% +1.8V 2 G S Q61 VGA@ SSM3K7002FU_SC70-3 +1.25VS D VGA_PWGOD# 3 3 2 G 2 2 SUSP R338 10K_0402_5% Discharge circuit-1 D VGA@ +5VS D S Q65 VGA@ SSM3K7002FU_SC70-3 2 G S Q62 VGA@ SSM3K7002FU_SC70-3 +0.9VS VGA@ 1 SUSP S VGA@ 1 1 2 470_0402_5% Q32 SSM3K7002FU_SC70-3 3 VGA Discharge circuit D 2 G 3 2 28,29,46,47,48 SUSP# SUSP# 3 R647 R646 2 SUSP SUSP 1 32,40,48 1 1 +1.2VS R340 3 +1.5VS +3VS VGA_PWGOD 1 1 1 1 R391 R383 R382 470_0402_5% 2 470_0402_5% 2 470_0402_5% 2 1 470_0402_5% 2 R351 470_0402_5% Q49 SSM3K7002FU_SC70-3 S Q34 SSM3K7002FU_SC70-3 S Q33 SSM3K7002FU_SC70-3 D SUSP 2 G D SUSP 2 G S Q39 SSM3K7002FU_SC70-3 1 SUSP 1 1 1 D 2 G 3 3 S Q12 SSM3K7002FU_SC70-3 D SUSP 2 G 3 SUSP 3 D 2 G D 3 S SYSON# Q50 SSM3K7002FU_SC70-3 1 1 D 2 G VGA@ S D 2 G 3 SUSP S Q37 SSM3K7002FU_SC70-3 2 G S Q38 SSM3K7002FU_SC70-3 4 3 47 VGA_PWGOD R372 470_0402_5% 2 1 1 VGA_PWGOD# 3 2 100K_0402_5% 4 R668 VGA@ 100K_0402_5% 2 1 R551 R133 2 R536 470_0402_5% 2 +3VALW 1 +5VALW 1 1 +1.8VS_CB SYSON -> SUSP# -> VGA_ON->VGA_PWGOD 2007/1/15 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/1/15 Deciphered Date Title DC/DC Circuits THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: A B C D Sheet Thursday, January 10, 2008 E 41 of 49 5 4 3 2 1 D D FD6 FIDUCAL FD7 FIDUCAL FD8 FIDUCAL @ 1 1 @ @ 1 FD5 FIDUCAL @ 1 FD4 FIDUCAL @ 1 1 1 FD3 FIDUCAL @ H7 @ HOLEA H2 @ HOLEA H3 @ HOLEA H25 @ HOLEA H5 @ HOLEA H6 @ HOLEA H10 @ HOLEA H21 @ HOLEA 1 H1 @ HOLEA 1 1 H_2P5 FD2 FIDUCAL @ 1 FD1 FIDUCAL @ 1 1 1 1 1 1 H_2P8 H9 @ HOLEA H11 @ HOLEA H14 @ HOLEA H8 @ HOLEA H23 @ HOLEA 1 H12 @ HOLEA 1 C 1 C H13 @ HOLEA H26 @ HOLEA H_3P8 H4 @ HOLEA 1 1 1 H19 @ HOLEA 1 H22 @ HOLEA 1 H_3P3 1 1 H_2P8 1 1 H24 @ HOLEA B B H15 @ HOLEA H18 @ HOLEA H16 @ HOLEA H17 @ HOLEA 1 1 1 1 H_4P3 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/1/15 2008/1/15 Deciphered Date Title Screws THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Sheet Thursday, January 10, 2008 1 42 of 49 5 4 3 ADPIN 2 1 VIN PL17 FBMA-L11-322513-151LMA50T_1210 PC156 2200P_0402_50V7K~D 2 2 PR188 @ 56K_0402_5%~D 1 2 PR189 1M_0402_1%~N 1 2 D VIN 3 + N35 2 - 1 3.3V P 8 - 4 C PD3 PD4 BATT+ 2 1 1 1 PJP1 @ JUMP_43X118 1 1 2 2 CH751H-40PT_SOD323-2 19,29,44 RTCVREF PU12B O 2 6 + ACIN 7 G 5 PR192 1K_0402_5%~D 2 PR195 10K_0402_5%~D PD1 RLZ4.3B_LL34 PR198 10K_0402_5%~D 1 2 VIN 1 LM393DR_SO8 2 PC163 1000P_0402_50V7K~D 1 1 O PR191 10K_0402_5%~D 1 1 8 PU12A N40 P 1 PR194 19.6K_0402_1%~D 2 1 1 2 PC162 0.1U_0402_16V7K~D N41 PR193 22K_0402_1%~D 2 2 PL16 FBM-L11-160808-601LMT 0603~D 2 1 DOCK_PSID G 2 PR190 82.5K_0402_1%~D 2 PC161 2 1 1 VS 2 VIN 0.01U_0402_25V7K~D PC159 1000P_0402_50V7K~D 2 1 PC160 100P_0402_50V8J~D 2 1 1000P_0402_50V7K~D 1 PC157 2 1 2 PC158 100P_0402_50V8J~D 1 1000P_0402_50V7K~D @ 2 2 ACES_88299-0600 PC287 1 4 1 1 D 1 2 3 4 5 6 7 8 PC286 100P_0402_50V8J~D 1 2 3 4 5 6 GND GND @ PJPDC1 LM393DR_SO8 Vin Detector L-->H H-->L typ. 17.841 17.210 Min. 17.449 16.813 2 PR203 33_1206_5% VS C Max. 18.234 17.597 RLS4148_LL34-2 51ON# 1 2 PJP7 @ JUMP_43X118 1 1 2 2 +1.8VP PJP9 @ JUMP_43X118 1 1 2 2 A +1.25VSP +VCCPP S D PJP6 @ JUMP_43X118 1 1 2 2 +0.9VS PJP8 @ JUMP_43X118 1 1 2 2 +VCCP 2 3 2 G @ PD7 SM24_SOT23 @ PR216 1 @ PSID_DISABLE# 29 2 10K_0402_1%~D +VGA_COREP A PJP12 @ JUMP_43X118 1 1 2 2 +VGA_CORE Compal Secret Data Security Classification Issued Date PJP14 @ JUMP_43X118 1 1 2 2 2006/10/1 2007/5/01 Deciphered Date TitleDCIN / Precharge THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D JAL80 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 PD6 DA204U_SOT323~D 1 1 PQ54 MMST3904-7-F_SOT323~D E PR214 10K_0402_1%~D +1.5VS C 2 B 2 PJP4 @ JUMP_43X118 1 1 2 2 +5VALW +5VALW PJP10 @ JUMP_43X118 1 1 2 2 +1.8V +1.25VS 29 1 +1.5VSP +0.9VSP +3VALW PS_ID 3 +1.2VS PR215 PR213 15K_0402_1%~D 100K_0402_1%~D 1 2 1 2 PJP2 @ JUMP_43X118 1 1 2 2 2 +5VALW 3 B RHU002N06_SOT323-3 +1.2VSP PJP11 @ JUMP_43X118 1 1 2 2 PJP13 @ JUMP_43X118 1 1 2 2 1 PR212 33_0402_5%~D 1 2 PQ53 PC167 1U_0805_25V4Z~D 3 1 PJP5 @ JUMP_43X118 1 1 2 2 +3VALWP DOCK_PSID 2 1 IN GND 1 PJP3 @ JUMP_43X118 1 1 2 2 OUT 2 PC166 2 1 +5VALWP 4.7U_0805_6.3V6K~N 3 2 PU14G920AT24U_SOT89-3 PR208 1 2 0_0402_5%~D PR209 2.2K_0402_5%~D 1 2 PR207 200_0805_5% +3VALW 1 @ 1 RTCVREF B PD5 DA204U_SOT323~D +5VALW 2 31 PC165 0.1U_0603_25V7K~D 3 2 PR206 22K_0402_5%~D 1 2 32.8 2 PR205 100K_0402_5%~D PQ50 TP0610K-T1-E3_SOT23-3 1 3 0.22U_1206_25V7K PC164 2 1 1 CHGRTCP 4 3 2 Rev 0.2 Sheet Thursday, January 10, 2008 1 43 of 9 B LX_CHG PD8 2 1 PGND 22 LEARN 21 1 4 3 2 1 2 3 1 4 2 23 2 2 1 G S S S 1 FDS6690AS_NL_SO8 PC183 1U_0603_10V6K~D 2 2 2 LODRV 4 DL_CHG 1 CP setting BATT+ 1 5 6 7 8 24 1 PR226 340K_0402_1%~D Icharge=(Vsrset/Vvdac)*(0.1/PR222)=3.3A 7 ACOP 2 PC184 0.47U_0603_16V7K~N PR222 0.02_2512_1% 2 REGN PR225 100K_0402_1%~D 2 ACSET 1 1 1 PC182 0.01U_0402_25V7K~D @ 2 PQ59 1 VREF 6 1 RLS4148_LL34-2 PC179 0.1U_0603_25V7K~D REGN 2 ACSET PR224 56.2K_0402_1% 1 2 1 PL18 10UH_SIL1045RA-100PF_4.5A_30% 1 2 PQ58 FDS4435BZ_SO8 PC181 10U_1206_25V6M~D PH ACDRV ACDET 1 D D D D DH_CHG PC173 26 25 PC293 2 HIDRV 4 /BATDRV PR218 100K_0402_1%~D 5 6 7 8 ACN ACP 27 1 2 3 BTST PQ57 FDS8884_SO8 4.7U_1206_25V6K~D PC176 @0.1U_0603_25V7K~D PR220 2.2_0603_5%~D 1 2 PC168 3 2 1 2 2 PC178 0.1U_0603_25V7K~D ACDET 90W adapter 8 9 AGND 2 29 VREF 20 CELLS PC187 @0.1U_0603_25V7K~D 3 Cell VREF 4 Cell VDAC 12 VADJ 1 11 SRP 19 SRN 18 BAT 17 TP 29 SRSET 16 IADAPT 15 VADJ 2 ACSET 2 1 PC189 0.1U_0603_25V7K~D 1 1 PR229 100K_0402_1%~D 2 CELLS 13 2 3cell/4cell# 50 G PQ61 SSM3K7002F_SC59-3 ICHG setting ACGOOD 14 BATDRV RTCVREF PR231 2 1 49.9K_0402_1%~D IREF 29 CHGVADJ 2 PR233 10_0603_5%~D PC191 @0.01U_0402_25V7K~D 1 2 2 ACIN 1 BQ24751ARHDR_QFN28_5X5 1 2 PR53 4.32K_0402_1%~D 1 2 VADJ 29 ACGOOD# ADP_I 1 1 29 PR51 @ 0_0402_5%~D PR54 10K_0402_1%~D IREF 3 2 G S Current 2 2 PC192 100P_0402_50V8J~D 19,29,43 D PQ62 @ SSM3K7002F_SC59-3 3 3 PR234 100K_0402_1%~D 1 Cells selector VREF @ PR230 PR232 100K_0402_1%~D 100K_0402_1%~D 1 /BATDRV 2 3 S REGN 1 1 ACGOOD# D PC190 0.1U_0603_25V7K~D 2 GND PC188 1U_0603_10V6K~D 1 2 CELLS PR228 100K_0402_1%~D 1 2 VREF 1 VREF 10 2 PQ60 SI2301BDS-T1-E3_SOT23-3 3 1 CELLS PC186 0.1U_0603_25V7K~D 2 PR227 54.9K_0402_1% Fsw : 300KHz ACOFF 1 2 Input UVP : 16.98V PC185 0.1U_0402_16V7K~D 1 2 OVPSET 1 OVPSET Input OVP : 22.3V 2 Iadapter=(Vacset/Vvdac)*(0.1/PR217)=3.65A 2 28 PC172 PVCC 5 6 7 8 CHGEN# CHGEN 4 5 PR223 54.9K_0402_1% CHG_B+ 1 1 PC177 0.1U_0805_25V7K 1 2 PU15 1 1 1 PC175 0.1U_0402_16V7K~D 1 2 PR221 340K_0402_1%~D PC169 2.2U_0805_25V6K 2 JUMP_43X118 4.7U_1206_25V6K~D 2 1 @ 1000P_0402_50V7K~D 1 3 PC180 10U_1206_25V6M~D 2 2 2 4 0.01U_0402_25V7K~D PJP15 1 PC292 2 8 7 6 5 D D D D PR219 100K_0402_1%~D 2 1 2 S S S G B+ PR217 0.015_2512_1% 1000P_0402_50V7K~D 1 1 2 3 4 E PC171 1 2 3 4 PC174 0.01U_0402_25V7K~D 2 1 S S S G 2 1 1 PR272 PR339 1_1210_5%~D1_1210_5%~D 1 2 1 D D D D PQ56 FDS4435BZ_SO8 PC170 0.01U_0603_50V7K~D 2 2 8 7 6 5 D 4.7U_1206_25V6K~D 2 1 PQ55 FDS4435BZ_SO8 VIN 1 C 3 2 1 A 2.968V +COINCELL PR235 COIN RTC Battery 1 B+_BIAS 2 2 1 Z4012 PR237 100K_0402_1%~D RHU002N06_SOT323-3 PD2 BAT54CW_SOT323~D 1 1 2 G1 G2 27.4 29 FSTCHG 1 S 1 2 3 4 1 PQ64 2 G PJP24 +COINCELL D 3 3 CHGEN# +RTCVCC D VREF PR1 1K_0402_5%~D RTC_VREF 2 0.1U_0805_25V7M~N 2 2 1 PC193 220K_0402_5% PR239 2 32.8 32.8 1 2 1SS355_SOD323-2 1 1 2 PD9 1 2 PR238 1 PC194 0.1U_0603_25V7K~D 2 1 4 220K_0402_5% PR236 +5VALW PQ63 TP0610K-T1-E3_SOT23-3 1 3 3 2 100_0805_5%~D 470K_0402_5%~D 1 B+ 3A S PQ65 SSM3K7002F_SC59-3 2 G ACES_85204-02001 4 PC1 1U_0603_10V4Z~D 2 Move to power schematic 2006/10/1 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/5/01 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D Charger Document Number JAL80 Rev 0.2 **** Sheet Thursday, January 10, 2008 E 44 of 9 5 4 3 2 1 ISL6237_B+ ISL6237_B+ B+ PHASE1 16 PC208 0.1U_0603_25V7K~D LX5 LGATE1 18 DL5 PGND 22 OUT1 10 FB1 11 BYP 9 SKIP 29 DH5 PR245 BST5A 2 1 0_0603_5%~D PQ69 AO4712_SO8 DL3 23 PHASE2 FB3 30 32 VL @ LGATE2 2 1 @ OUT2 REFIN2 2VREF_ISL6237 1 PC200 2200P_0402_50V7K~D 2 1 4 3 2 1 25 PR246 61.9K_0402_1%~D 1 2 LX3 PC199 4.7U_1206_25V6K~D 2 1 PC198 4.7U_1206_25V6K~D 2 1 3 2 1 BOOT1 17 5 6 7 8 4.7U_0805_6.3V6K~N PC203 2 1 1U_0603_10V6K~D 7 LDO 3 VCC VIN 19 15 PC205 0.1U_0603_25V7K~D +5VALWP 1 + PC210 330U_D3L_6.3VM_R25M 2 PR248 10K_0402_1%~D 1 2 2 1 PR247 10K_0402_1%~D PVCC UGATE1 BOOT2 D PL21 2 1 4.7UH_SIL104R-4R7PF_5.7A_30% PC209 24 @ C UGATE2 1 1 4 PR243 1 BST3A 0_0603_5%~D TP 26 PC207 1U_0603_10V6K~D 1 2 @ PR242 4.7_1206_5%~D 2 1 2 2 PQ68 AO4712_SO8 33 PQ67 AO4466_SO8 4 2 8 7 6 5 DH3 1 2 3 2 PC206 @ PR241 680P_0603_50V7K~D 4.7_1206_5%~D 2 1 2 1 2 + 1 PC204 330U_D3L_6.3VM_R25M PR244 0_0402_5%~D 1 PU16 6 1 2 3 1 PC201 0.1U_0603_25V7K~D PC202 1 2 2 8 7 6 5 PQ66 AO4466_SO8 4 PL20 1 2 4.7UH_SIL104R-4R7PF_5.7A_30% +3VALWP 5 6 7 8 VL 680P_0603_50V7K~D 2 1 PC197 2200P_0402_50V7K~D 2 1 D PC196 4.7U_1206_25V6K~D 2 1 PR240 0_0805_5% 1 2 PC195 4.7U_1206_25V6K~D 2 1 PJP20 @ JUMP_43X118 1 1 2 2 FB5 C REF PC211 0.22U_0603_10V7K~D 8 LDOREFIN Rds(on) = 15m ohm(max) ; Rds(on) = 12m ohm(typical) @ PR249 2 PR250 1 20 PR251 100K_0402_1%~D 1 2 EN_LDO POK1 13 14 EN1 27 EN2 POK PR253 ILIM1 12 ILM1 2 ILIM2 31 ILIM2 2 255K_0402_1% 1 GND 21 NC TON 2 5 B ISL6237IRZ-T_QFN32_5X5 1 1 PR258 @ 2 PC285 2VREF_ISL6237 2 2 1 255K_0402_1% Rds(on) = 15m ohm(max) ; Rds(on) = 12m ohm(typical) 1U_0603_10V6K~D PC213 0.047U_0603_16V7K~D 1 2 2 PQ79 TP0610K-T1-E3_SOT23-3 2 1 1 2VREF_ISL6237 1 1 PR260 @ 47K_0402_5%~D 0_0402_5%~D 3 28 PR256 0_0402_5%~D @ PR254 0_0402_5%~D 806K_0603_1% 2 PR257 1 PR259 2 1 POK2 VL 0_0402_5%~D 2 PR255 VL 50 MAINPWON NC 2 B PC212 0.22U_0603_25V7-K PC214 0.047U_0402_16V7K~N 2 1 Iocp=9A 4 2 PD10 RLZ5.1B_LL34 1 2 1 VS PR252 200K_0402_5%~D 1 2 3.3VALWP Imax=6A 0_0402_5%~D 1 5VALWP Imax=6A 0_0402_5%~D Iocp=9A @ PD16 1 2 1SS355TE-17_SOD323-2 A A Compal Electronics, Inc. Compal Secret Data Security Classification 2006/10/1 Issued Date Deciphered Date 2007/05/30 Title +3VALWP, +5VALWP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Thursday, January 10, 2008 Date: Rev 0.2 JAL80 5 4 3 2 Sheet 1 45 of 9 3 2 1 PC240 1U_0402_6.3V6K~D 2 2 PC239 1U_0402_6.3V6K~D 1 4 1 5 PGOOD1 PGOOD2 串1K電組 上@ PR288 2 +5VALWP PR289 1 1 2 D 1 ISL6228_B+ 2 2 2 2 10_0603_1% 1 2 1 2 1 1 PC244 1000P_0402_50V7K~D PR294 18.2K_0402_1%~D PR293 PC243 22K_0402_1%~D 1000P_0402_50V7K~D PR295 90.9K_0402_1%~N 8 2 1 FB1 GND_T 29 PGOOD2 28 2 FSET2 3 2 VIN2 VCC1 VCC2 4 5 VIN1 6 FSET1 7 PGOOD1 68K_0402_1% PR298 2 PR299 22.6K_0402_1% ISL6228_B+ VO2 1 26 1 EN2 24 PR307 0_0402_5%~D 1 2 2 SYSON 0_0603_5%~D 8 7 6 5 0.022U_0402_16V7K~D UGATE1 PHASE2 2 UG_VCCPP 13 ISL6228_B+ 2 PQ76 AO4466_SO8 23 4 22 UG_1.8V 1 2 PC259 PQ77 AO4712_SO8 2 0_0603_5%~D PC258 1U_0402_6.3V6K~D 1 2 4 0.1U_0402_16V7K~D 3 2 1 1 2 1 PC257 1U_0402_6.3V6K~D 2 2 +5VALWP BST_1.8V 1 +5VALWP 1 PR313 Iocp=11.59A PC254 2 PR309 24K_0402_1%~D PL27 1 PR312 4.7_1206_5%~D 5 6 7 8 BOOT2 LX_1.8V 21 PVCC2 20 LGATE2 19 PGND2 18 15 PVCC1 UGATE2 PGND1 BOOT1 17 14 1BST_VCCPP LGATE1 1 2 16 2 PR310 PC256 0_0603_5%~D 0.1U_0402_16V7K~D 1 1 PR311 0_0603_5%~D 1 2 4 1 2 3 2 1 2 DCR 15m ohm(max) VCCPP Imax=7A 28,29,41 PC252 5 6 7 8 PHASE1 1 12 1 PQ75 AO4712_SO8 2 2 1.5UH_MPL73-1R5_9A_20% 1 + DCR 15m ohm(max) 1.8VP Imax=9A PC260 220U_D2_4VM 25 2 OCSET2 PC250 4.7U_1206_25V6K~D PU18 PC261 680P_0603_50V8J~D EN1 1 11 @ 0.01U_0402_25V7K~D + 2 2 8 7 6 5 OCSET1 ISL6228HRTZ-T_QFN28_4X4 1 2 3 1 PR308 4.7_1206_5%~D PC255 680P_0603_50V8J~D PC251 1 C VCCPP_EN LX_VCCPP 1.5UH_MPL73-1R5_9A_20% 220U_D2_4VM PR302 27 24K_0402_1%~D PR306 2 1 FB2 PR300 3.3K_0402_5%~D 1000P_0402_25V8J 34K_0402_1% PR301 PC246 2 1 1 2 PR303 10 PQ74 AO4466_SO8 4 1 PL26 1 +VCCPP VO1 PC253 4.7U_1206_25V6K~D 2 1 PR305 22.6K_0402_1% +5VALWP 68K_0402_1% PC247 4.7U_1206_25V6K~D 1 2 2 C PC249 4.7U_1206_25V6K~D 2 1 9 PC248 0.033U_0402_16V7K~D 1 2 1 1K_0402_1%~D @ 3 2 1 1 PC242 0.1U_0603_25V7K~D 2 PR292 1 10_0603_1% PR297 1 2 +5VALWP 1 1 2 PR291 ISL6228_B+ 2 1 2 PR296 PC245 2 1 1 PR290 1K_0402_1%~D @ 3.3K_0402_5%~D 1000P_0402_25V8J 2 PC241 0.1U_0603_25V7K~D ISL6228_B+ PC291 680P_0402_50K X7R~D 1 2 PC290 470P_0402_50V8J~D B+ 1 +5VALWP PJP21 @ JUMP_43X118 1 1 2 2 D 2 2.2_0603_1%~D 1 2.2_0603_1%~D +1.8VP 2 Iocp=12.31A LG_VCCPP B B PR314 0_0402_5%~D 2 1 VCCPP_EN 2 1 SUSP# PC262 0.01U_0402_25V7K~D 28,29,41,47,48 LG_1.8V @ A A Compal Secret Data Security Classification Issued Date 2006/10/1 Deciphered Date 2007/5/01 Title +1.8VP/+VCCPP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Document Number Rev 0.2 JAL80 Thursday, January 10, 2008 1 Sheet 46 of 9 PGOOD1 PGOOD2 串1K電組 上@ 1 PC215 1U_0402_6.3V6K~D 2 3 1 4 2 5 PR262 1 1 2.2_0603_1%~D 2 +5VALWP 2.2_0603_1%~D VGA@ 1 1 +5VALWP 2 1 PR263 2 PR264 ISL6228_B++ 1K_0402_1%~D @ 2 PC217 0.1U_0603_25V7K~D ISL6228_B++ PC218 0.1U_0603_25V7K~D VGA@ 2 PR265 1 10_0603_1% 2 2 1 PC220 1000P_0402_50V7K~D PR267 18.2K_0402_1%~D VGA@ 2 1 PR266 22K_0402_1%~D VGA@ 2 1 GND_T 29 2 2 VIN2 3 VCC2 4 VCC1 6 5 VIN1 FSET2 PR271 FSET1 7 PGOOD1 68K_0402_1% 8 FB1 PGOOD2 28 9 VO1 FB2 27 VGA_PWGOD 41 1 17.8K_0402_1%~D PR273 3.3K_0402_5%~D 1000P_0402_25V8J 78.7K_0402_1%~D PR274 PC222 VGA@ VGA@ VGA@ 2 1 1 2 8 7 6 5 1 UGATE2 22 2 4 PR284 0_0603_5%~D 1 2 VGA@ LX_VGA AO4466_SO8 VGA@ VGA@ 2 1 LG_1.5V B PL24 1 1 2 1.5UH_MPL73-1R5_9A_20% VGA@ 1 2 4 0.1U_0402_16V7K~D VGA@ PQ73 AO4712_SO8 VGA@ 1 + DCR 15m ohm(max) +VGA (1.15V) Imax=9A +VGA_COREP 2 VGA@ VGA@ Iocp=12.31A LG_VGA B PR287 0_0402_5%~D 2 1 1.5V_EN 2 1 SUSP# 2 PC230 0.022U_0402_16V7K~D PC238 0.01U_0402_25V7K~D 28,29,41,46,48 2.2_0603_5%~D VGA@ PC236 1U_0402_6.3V6K~D VGA@ 1 3 2 1 2 1 PC235 1U_0402_6.3V6K~D 1 2 +5VALWP BST_VGA 2 +5VALWP C VGA@ PR282 24K_0402_1%~D VGA@ 2 PC234 PR286 Iocp=9.13A 1 VGA@ PR285 VGA@ 4.7_1206_5%~D 5 6 7 8 BOOT2 UG_VGA 21 PVCC2 20 LGATE2 19 PGND2 18 PVCC1 PC232 PR283 0.1U_0402_16V7K~D 0_0603_5%~D PGND1 BOOT1 17 1BST_1.5V 14 LGATE1 1 2 16 2 15 DCR 15m ohm(max) 1.5VP Imax=5A PQ72 4 1 2 3 2 1 @ PC231 680P_0603_50V8J~D 2 13 PR277 10_0402_5%~D VGA@ 1 23 VGA@ 0.01U_0402_25V7K~D UG_1.5V PQ71 AO4712_SO8 2 PHASE2 PR281 4.7_1206_5%~D + 2 ISL6228_B++ 1 UGATE1 8 7 6 5 @ VGA_ON 29 PC228 1 2 1 12 1 24 2 0_0603_5%~D 2 EN2 PR280 0_0402_5%~D 1 2 VGA@ PC226 4.7U_1206_25V6K~D PHASE1 PU17 PC237 680P_0603_50V8J~D 25 1 OCSET2 EN1 PC229 4.7U_1206_25V6K~D 11 ISL6228HRTZ-T_QFN28_4X4 1 2 3 1 26 5 6 7 8 1.5V_EN LX_1.5V 2 PC227 VO2 PR276 24K_0402_1%~D VGA@ PR279 1.5UH_MPL73-1R5_9A_20% 220U_6.3V_M OCSET1 PC233 220U_D2_4VM 10 PQ70 AO4466_SO8 4 2 1 2 71.5K_0402_1%~D VGA@ 1 PL23 1 +1.5VSP 1 3 2 1 PR278 17.8K_0402_1%~D PR275 PC223 4.7U_1206_25V6K~D 1 2 C 2 PC224 0.033U_0402_16V7K~D 1 2 PC225 4.7U_1206_25V6K~D 2 1 ISL6228_B++ 2 1 2 PC219 1000P_0402_50V7K~D PR270 1 2 ISL6228_B++ 1 1 1 2 2 PR269 PC221 2 1 PR268 45.3K_0402_1%~D 1 10_0603_1% VGA@ 2 3.3K_0402_5%~D 1000P_0402_25V8J D 1 PJP22 @ JUMP_43X118 1 1 2 2 B+ D 1 PC216 1U_0402_6.3V6K~D VGA@ PR261 2 +5VALWP 2 @ A A Compal Secret Data Security Classification Issued Date 2006/10/1 Deciphered Date 2007/5/01 Title +1.5VP/+VGA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Document Number Rev 0.2 JAL80 Thursday, January 10, 2008 1 Sheet 47 of 9 5 4 +5VALW 3 2 1 +1.5VS PJP16 9 2 2 1 1 1 1 1 2 VIN PJP17 @ JUMP_43X118 VCNTL 6 GND NC 5 3 VREF NC 7 4 VOUT NC 8 TP 9 +3VALW PC268 2 1 1 2 APL5331KAC-TRL_SO8~N 1 1 PQ78 PR320 PC270 S PC271 1U_0603_10V6K~D C D 2 G 2 PC272 @ 0.1U_0402_16V7K~D +0.9VSP 1 0_0402_5%~D 1 2 2 SUSP 2 32,40,41 3 VGA@ 1 PR318 1 1 2 VIN 2 1 PR317 1K_0402_1%~D VGA@ PC269 0.1U_0402_16V7K~D @ 1 4.7U_0805_6.3V6K~N 0.01U_0402_25V7K~D 2 1 2 PC265 VGA@ PU20 PC267 1U_0603_10V6K~D APL5913-KAC-TRL_SO8~N VGA@ 1 +1.2VSP 2 1 1 VGA@ D 2 2 PC264 1U_0603_10V6K~D FB VGA@ PC266 1U_0603_10V6K~D 0_0402_5%~D 2 4 +1.8V 2 EN 3 VOUT @ JUMP_43X118 PR319 2K_0402_1%~D 8 5 VGA@ 1 VIN VOUT PR316 1K_0402_1%~D 2 1 28,29,41,46,47 SUSP# PR315 2 POK GND 7 VCNTL PU19 6 2 2 D PC263 1U_0603_10V6K~D 1 VGA@ C RHU002N06_SOT323-3 0.1U_0402_16V7K~D 1K_0402_1%~D +5VALW +1.5VS 1 1 2 2 9 APL5913-KAC-TRL_SO8~N 1 PC275 0.01U_0402_25V7K~D 2 FB VIN +1.25VSP 1 4 PC276 1U_0603_10V6K~D 1 3 VOUT B 2 1 PC277 0.1U_0402_16V7K~D @ PR323 2.05K_0402_1%~D 2 1 B 5 2 VCNTL EN 0_0402_5%~D VIN VOUT PR322 1.15K_0402_1% 2 1 8 POK GND 1 28,29,41,46,47 SUSP# PR321 2 6 PU21 7 PC274 1U_0603_10V6K~D 1 2 PC273 1U_0603_10V6K~D 2 1 2 PJP18 @ JUMP_43X118 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2005/10/1 2007/05/30 Deciphered Date Title +1.25VSP / +0.9VSP/ +1.2VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Thursday, January 10, 2008 Date: Rev 0.2 JAL80 5 4 3 2 Sheet 1 48 of 9 5 4 3 2 1 PR175 97.6K_0402_1%~D PC134 470P_0402_50V7K~D 1 2 2 1 2 1 1 2 2 PC113 100U_25V_M PC116 10U_1206_25V6M~D 2 1 PC115 10U_1206_25V6M~D 2 1 PC114 10U_1206_25V6M~D 2 1 5 1 PC120 1U_0603_10V6K~D 2 0.01U_0402_25V7K~D PC119 2 1 PC155 100U_25V_M PR160 10K_0402_1%~D 2 1 1 2 1 3.65K_1206_1% PR159 2 PC123 2 1 2 4 3 2 1 G S S S D D D D PR158 1 5 6 7 8 3 2 1 1 1 2 1 B FDS6676AS_SO8 +CPU_B+ 2.61K_0402_1%~D 1 2 1 11K_0402_1%~D 1 PR185 2 2 PH3 PR186 1K_0402_1%~D PR187 3.57K_0402_1%~D 10KB_0603_ERTJ1VR103J PC144 0.068U_0603_50V7K~N 1 2 PC145 0.22U_0603_16V7K~D 2 1 1 VCC_PRM PC135 1 2 ISEN2 2 PR182 1 PC142 0.022U_0603_25V7K 1 2 PR183 0_0402_5%~D PC143 180P_0402_50V8J~D 1 2 1 PR173 @ 0_0402_5%~D 1 2 0.1U_0603_25V7K~D 2 PC141 @0.022U_0603_25V7K VSSSENSE 1_0402_5%~D VSUM 1 0_0402_5%~D 2 PR180 PR172 PC139 10_0603_5%~D PC140 0.022U_0603_25V7K 1 2 2 1 0.22U_0603_16V7K~D PR178 1K_0402_1%~D 1 PL15 VCC_PRM PC138 1000P_0402_50V7K~D 2 1 2 255_0402_1%~D 1 2 PR179 PC133 680P_0603_50V8J~D VSUM FDS6676AS_SO8 2 220P_0402_50V7K~D PQ48 PR174 1_0603_5%~D PC136 1U_0603_10V6K~D 2 PR176 1K_0402_1%~D PR168 4.7_1206_5%~D +5VS 2 1 1 1 1 2 PQ47 29.1 ISEN1 ISEN2 2 @ 2 ISEN1 PC132 1000P_0402_50V7K~D C +CPU_B+ P_0.36H_ETQP4LR36WFC_24A_20% 2.2_0603_5%~D 0.22U_0603_10V7K~D PU11 24 ISEN2 VDD 23 22 GND 21 VIN 20 VSUM 19 VO 18 DFB 17 VDIFF 2 PC127 10U_1206_25V6M~D 25 2 NC PC126 10U_1206_25V6M~D 26 PR161 1_0402_5%~D PR170 10K_0402_1%~D 2 1 BOOT2 PHASE_CPU2 UGATE_CPU2 PR167 PC130 BOOT_CPU2 1 2 1 2 1 27 PR171 28 UGATE2 PQ46 SI7686DP-T1-E3_SO8 4 +CPU_CORE PR162 @ 0_0402_5%~D 1 2 PC124 1 2 VCC_PRM ISEN1 0.22U_0603_16V7K~D VSUM 2 PHASE2 COMP LGATE_CPU2 D D D D VW 13 1 D PL14 1 FB2 29 1 2 12 PC131 1 2 1000P_0402_50V7K~D PR169 6.81K_0402_1%~D 1 2 30 PGND2 2 FB 2 B+ 3 2 1 11 9 + LGATE_CPU1 5 6 7 8 10 1 P_0.36H_ETQP4LR36WFC_24A_20% 2 1 3.65K_1206_1% 31 LGATE2 ISL6262ACRZ-T_QFN48_7X7 2 PC125 10U_1206_25V6M~D 2 1 PVCC FDS6676AS_SO8 4.7_1206_5%~D 680P_0603_50V8J~D 32 D D D D PR166 11.5K_0402_1%~D 1 2 A 1 33 G S S S OCSET 5 PC118 1U_0603_10V6K~D 2 1 D D D D PGND1 LGATE1 4 3 2 1 PHASE_CPU1 PQ45 4 3 2 1 8 VCCSENSE 5 UGATE_CPU1 34 G S S S SOFT 5 5 37 VID0 35 PHASE1 5 6 7 8 NTC 7 PR177 1 36 BOOT1 UGATE1 4 3 2 1 6 DROOP 2 @ 100K_0603_1%_TH11-4H104FT 1 2 @ 0.015U_0402_16V7K PC128 0.068U_0603_50V7K~N PC129 1 2 16 2 1 PC137 5 5 CPU_VID2 5 CPU_VID1 5 CPU_VID0 5 38 VID1 VID2 39 40 42 43 45 44 46 41 VID3 VR_TT# VID4 RBIAS 5 VID5 4 VID6 PMON VR_ON 3 DPRSLPVR PSI# CLK_EN# PGOOD 2 DPRSTP# 47 48 1 PQ44 FDS6676AS_SO8 5 PH2 3V3 49 PR164 147K_0402_1%~D 1 2 B 1 5 6 7 8 1 10K_0402_1%~D 2 RTN PR165 VR_TT# @ 4.22K_0402_1% 1 PR181 2 1 VSEN C PC147 1 15 POW_MON 1U_0603_10V6K~D + PQ43 SI7686DP-T1-E3_SO8 0.22U_0603_10V7K~D 2 1 2 2.2_0603_5%~D H_PSI# @ 1 PC122 BOOT_CPU1 VGATE PL13 FBMA-L18-453215-900LMA90T_1812 1 2 4 PR155 14 5 0_0402_5%~D 2 GND 2 1 7,19,29 0_0402_5%~D 2 2 1 PR156 2 499_0402_1%~D 1.91K_0402_1%~D PC121 1U_0603_10V6K~D +3VS 0_0402_5%~D 2 G S S S PR154 1 +3VS PR157 PR145 1 CLK_EN# PC117 0.01U_0402_25V7K~D 2 1 PR144 1 5,7,18 H_DPRSTP# 16 499_0402_1%~D 2 1 +CPU_B+ PR142 1_0603_5%~D 2 1 PR1460_0402_5%~D 2 1 PR1470_0402_5%~D 2 1 PR1480_0402_5%~D 2 1 PR1490_0402_5%~D 2 1 PR1500_0402_5%~D 2 1 PR1510_0402_5%~D 2 1 PR1520_0402_5%~D PR143 7,19 DPRSLPVR 29 CPU_VID3 5600P_0402_25V7K PR153 0_0402_5%~D 2 1 D CPU_VID4 @ CPU_VID5 1 VR_ON PC112 2 CPU_VID6 2 +5VS PC146 0.22U_0603_10V7K~D 2 1 A Compal Secret Data Security Classification 2007/1/15 Issued Date Deciphered Date 2008/1/15 Title Compal Electronics, Inc. +CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4121P Date: 5 4 3 2 Thursday, January 10, 2008 Sheet 1 49 of 9 5 4 3 2 1 C 1.BAT+ 2.BAT+ 3.ID 4.B/I 5.TS 6.SMD 7.SMC 8.GND 9.GND 10 11 1 1 2 1 2 BATT_TEMP BATT_TEMP 29 PR325 1K_0402_5%~D 2 1 1 2 3 4 5 6 7 8 9 GND GND 3 PD15 DA204U_SOT323~D 2 3 1 PD14 DA204U_SOT323~D 2 3 Place clsoe to EC pin 1 PR326 1 2 3 4 5 6 7 8 9 3cell/4cell# PC280 0.1U_0402_16V7K~D @ PJP19 @ Battery Connect/OTP @ 2 PR324 47K_0402_5%~D PJPB1 battery connector SMART Battery: D +3VALWP PC279 1000P_0402_50V7K~D 2 PC278 0.01U_0402_25V7K~D 2 1 1 BATT++ PC289 100P_0402_50V8J~D BATT+ @ PL28 HCB4532KF-800T90_1812 1 2 2 1 2 PC288 100P_0402_50V8J~D @ 1 2 3 1 BATT++ PD13 DA204U_SOT323~D @ BATT+ D PD12 DA204U_SOT323~D +3VALWP 1K_0402_5%~D 2 1 3cell/4cell# 44 1 2 +3VALWP PR327 6.49K_0402_1%~D SUYIN_200275MR009G186ZL 1 2 EC_SMB_DA1 29 C PR328 100_0402_5%~D CPU 1 2 PH1 under CPU botten side : CPU thermal protection at 90 +-3 degree C Recovery at 50 +-3 degree C EC_SMB_CK1 29 PR329 100_0402_5%~D VL VS 2 1 BATT+ 2 1 2 2 1 PR334 205K_0402_1%~D 2 8 + 2 - PD11 P 3 0 1 4 1 2 MAINPWON 45 1SS355_SOD323-2 PU22A LM358ADR_SO8 1 PR338 150K_0402_1%~D 2 PH4 100K_0603_1%_TH11-4H104FT 1 PC283 1000P_0402_50V7K~D PR336 150K_0402_1%~D 2 2 PR337 86.6K_0402_1% 2 1 1 6 1 G VL B 1 2 5 2 PU22B VL PR333 147K_0402_1%~D 1 2 PR335 61.9K_0402_1%~D 1 2 1 BATT_OVP - PC281 0.1U_0603_25V7K~D PR331 10.7K_0402_1%~D PR332 499K_0402_1%~D LM358ADR_SO8 + 0 G 29 CPU 4 7 PC282 0.01U_0402_25V7K~D 1 P 8 2 B 1 PR330 453K_0402_1%~D VS PC284 1U_0603_10V6K~D LI-3S :13.5V----BATT-OVP=1.5V BATT-OVP=0.111*BATT+ A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2005/10/1 2007/05/30 Deciphered Date Title BATTERY CONN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Thursday, January 10, 2008 Date: Rev 0.2 JAL80 5 4 3 2 Sheet 1 50 of 9 5 4 3 2 Version Change List ( P. I. R. List ) Item Page# D Title Date Request Owner 1 Page 1/1 Issue Description Solution Description Rev. 1 29 P29-EC KB926/REED SW/TPM1.2 07/10/30 compal board rev update to 0.2 R231 change to 15K & R232 pop 0.2 2 40 P40-OZ129_Card Reader/1394 07/10/30 compal CardBus vendor change CardBus R5C833 change to OZ129 0.2 3 29 P29-EC KB926/REED SW/TPM1.2 07/10/30 compal Change pull up resistance Change EC pin17,18 pull up to 4.7Kohm 0.2 4 29 P29-EC KB926/REED SW/TPM1.2 07/10/30 compal Need pull up NET MIC_DIAG pull up R to 10Kohm 3VS 0.2 5 13,14 DDR2 SODIMM-I,II Socket 07/10/30 compal Change Capacitance Change C84,C189 to SGA00002680 0.2 6 29 P29-EC KB926/REED SW/TPM1.2 07/10/30 compal EC update rev EC change to 926C 7 28 P28-Express card 07/10/30 compal Express card can't detect POWER IC(U11) ADD PIN10 CPUSB# 8 32 P32-USB/ BlueTooth/ FP/ Felica 07/10/30 compal Bluetooth can't detect BLUETOOTH CONN USB+- change 0.2 0.2 330U D 0.2 PIN9 EXPR_CPUSB#S 0.2 9 42 P42-Screws 07/10/30 compal FIDUCAL no enough ADD FIDUCAL*4 10 41 P41-DC/DC Interface 07/10/30 compal Need pull down SYSON pull down 10K ohm 0.2 11 41 P41-DC/DC Interface 07/11/12 compal USB can't detect SUSP change to 5VALW(Q32) 0.2 12 06 P06-Merom(3/3)-GND/Bypass 07/11/12 compal Change CPU High Frequence Decoupling Capacitance C195 change to C1150~C1181 13 41 P41-DC/DC Interface 07/11/13 compal +1.8VS Discharge error +1.8VS Discharge circuit 14 41 P41-DC/DC Interface 07/11/16 compal Delete Remove SIM card connector 0.2 15 42 P42-Screws 07/11/16 compal Change Holea size Change Holea size 2.5 to 2.8, change 3.5 to 3.8 0.2 16 31 P31-PWR_OK/ BTN/ KB / TouchPad 07/11/21 compal Change Touch PAD/B connector Touch PAD/B connector change net 0.2 17 15 P15-CRT Conn.& LCD Conn. 07/11/21 compal Add LCD control pin Add LCD control pin LCD_CBL_DET# & LCD_TST & LCD_VCC_TEST_EN 0.2 0.2 C C Q65 net change to VGA_PWGOD# 0.2 18 19 20 21 22 B B 23 24 25 26 27 28 29 30 31 32 A A 2007/1/15 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/1/15 Deciphered Date Title EE PIR-1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-4231P Date: 5 4 3 2 Sheet Thursday, January 10, 2008 1 51 of 49 5 4 3 2 Version Change List ( P. I. R. List ) Item Page# D Title Date Request Owner Issue Description 1 Page 1/1 Solution Description 1 41 +3VALWP/+5VALWP 07/11/19 COMPAL When in the DC-mode , shut down the system ,5valwp output not turn off ADD PQ79 to turn off 5VALWP 2 44 Charge 07/12/26 COMPAL change charge voltage can to adjust Change PR53 from 15K to 4.3K 3 49 CPU_CORE 07/12/26 COMPAL Increase Resistor 0ohm on CPU_CORE high side gate for EMI request ADD PR163 PR184 4 45 +3VALWP/+5VALWP 07/12/26 COMPAL The schematic location is wrong Rev. wehn shut down the system in the DC-mode D DEL PL19 5 6 7 8 9 10 11 12 C C 13 14 15 16 17 18 19 20 21 22 B B 23 24 4 25 26 27 28 29 30 31 32 A A 2007/1/15 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/1/15 Deciphered Date Title PW PIR-1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 0.1 LA-3682P Date: 5 4 3 2 Sheet Thursday, January 10, 2008 1 52 of 9 www.s-manuals.com </pre><hr>Source Exif Data: <br /><pre>File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Producer : Acrobat Distiller 6.0.1 (Windows) Modify Date : 2013:12:03 09:55:31+02:00 Create Date : 2008:01:11 12:06:06+08:00 Metadata Date : 2013:12:03 09:55:31+02:00 Document ID : uuid:647bd634-edde-45f9-8a19-743633c2f4c6 Instance ID : uuid:0e5dbfd3-6db9-4db6-9684-645a3fff00a0 Format : application/pdf Title : Compal LA-4231P - Schematics. www.s-manuals.com. Creator : Subject : Compal LA-4231P - Schematics. www.s-manuals.com. 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