Compal LA 5051P Schematics. Www.s Manuals.com. R0.3 Schematics
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A B C D E 1 1 Compal Confidential 2 2 KBYF0 Schematics Document AMD Griffin Processor with RS780M+SB700 (With ATI MXM/B) 2009-01-22 3 3 REV:0.3 ZZZ1 PCB DA60000B600-* 4 4 2008/11/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Cover Page Size B Date: Document Number Rev 0.3 KBYF0 LA-5051P Sheet Tuesday, February 03, 2009 E 1 of 46 A B C D E Compal Confidential Model Name : KBYF0 File Name: LA-5051P Clock Generator ICS9LPRS488B Thermal Sensor ADM1032 page 15 page 5 AMD S1G2 Processor Memory BUS(DDRII) Dual Channel 1 uPGA-638 Package Fan Control page 36 HDMI Conn. LCD Conn. page 17 1 page 8,9 BANK 0, 1, 2, 3 page 4,5,6,7 CRT Conn. Hyper Transport Link 16 x 16 page 18 page 16 200pin DDRII-SO-DIMM X2 1.8V DDRII 667/800 ATI RS780M PCI-Express 16x MXM III VGA/B BGA-528 page 14 PCI-Express 1x 2 port 1,2 MINI Card x2 TV-Tuner WLAN USB Conn x4 page 10,11,12,13 port 3 page 28 page 29 A link Express2 LAN(GbE) B5 784M page 26 C MOS Camera USB port 0,1,2,6 page 16 USB port 3 3.3V 48MHz USB 3.3V 24MHz HD Audio Bluetooth Conn Card Reader RTS5159 page 29 page 25 USB port 12 2 5 in 1 Socket page 25 USB port4 ATI SB700 RJ45 page 27 BGA-528 SPI page 19,20,21,22,23 BIOS ROM RTC CKT. 3 S-ATA LPC BUS SATA HDD Second SATA Conn.page 24 HDD Conn. page 24 BTN/B Conn. page 31 Power On/Off CKT. ENE KB926 page 32 LED/B Conn. page 31 port 0 page 37 Touch Pad port1 Audio AMP TPA6017 3 Mono AMP (for Woofer) page 34 Phone Jack x2 page 31 CIR page 31 page 34 EC ROM page 32 page 31 4 USB/B Conn. USB port 0,1,2,6 page 28 2008/11/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A page 33 page 34 Int.KBD page 31 FUN/B Conn. page 39,40,41 42,43,44,45 Int. MIC port 2 Media/B Conn. page 31 Power Circuit DC/DC HDA Codec ALC272 page 33 Digital/Analog MIC. SATA ODD Conn.page 24 page 30 DC/DC Interface CKT. 4 MDC 1.5 Conn page 32 page 21 page 19 B C D Title Block Diagrams Size B Date: Document Number Rev 0.3 KBKC0 LA-5051P Sheet Tuesday, February 03, 2009 E 2 of 46 A B C 2 Description S1 S3 S5 VIN Adapter power supply (19V) N/A N/A N/A B+ AC or battery power rail for power circuit. N/A N/A N/A +CPU_CORE_0 Core voltage for CPU ON OFF OFF +CPU_CORE_1 Core voltage for CPU ON OFF OFF +CPU_CORE_NB Core voltage for CPU ON OFF OFF +0.9V 0.9V switched power rail for DDR terminator ON ON OFF +1.1VS 1.05V switched power rail ON OFF OFF +1.2V_HT 1.25V switched power rail ON OFF OFF +NB_CORE 1.0V~1.1V switched power rail for NB VDDC ON OFF OFF +1.5VS 1.5V power rail for PCIE Card ON OFF OFF +1.8V 1.8V power rail for CPU VDDIO and DDR ON ON OFF +1.8VS 1.8V switched power rail ON OFF OFF +2.5VS 2.5V for CPU_VDDA and MXM/B ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* +3V_LAN 3.3V power rail for LAN ON ON ON +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON EC SM Bus1 address HIGH HIGH HIGH ON ON ON ON HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Device Address Smart Battery 0001 011X b ADI ADM1032 1001 100X b EEPROM(24C16/02) 1010 000X b CPU SB 1001 101X b MXM GMT G781-1 1001 101X b SB700 SM Bus 0 address Vcc Ra/Rc/Re Board ID 0 1 2 3 4 5 6 7 Address Clock Generator (ICS9LPRS365) 1101 001Xb DDR DIMM0 1001 000Xb DDR DIMM2 1001 010Xb V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BTO Option Table PCB Revision 0.1 0.2 0.3 0.4 1.0 BTO Item Discrete UMA BOM Structure VGA@ UMA@ PROJECT ID Table Address Device 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC 2 Board ID 0 1 2 3 4 5 6 7 SB700 SM Bus 1 address Device 1 Board ID / SKU ID Table for AD channel Board ID 0 1 * 2 3 4 5 6 7 EC SM Bus2 address Clock LOW Interrupts Device +VS HIGH No PCI device 3 +V S1(Power On Suspend) External PCI Devices REQ#/GNT# +VALW BOARD ID Table Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. IDSEL# E SLP_S1# SLP_S3# SLP_S4# SLP_S5# Full ON Power Plane Device SIGNAL STATE Voltage Rails 1 D 3 PROJECT KBKC0 (SJM70) KBYF0 (SJV70) Address Lan Minicard 4 4 Minicard 2008/11/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Notes List Size B Date: Document Number Rev 0.3 KBYF0 LA-5051P Sheet Tuesday, February 03, 2009 E 3 of 46 A B C D E 1 1 VLDT CAP. +1.2V_HT 250 mil 1 <10> H_CADIP[0..15] <10> H_CADIN[0..15] H_CADIP[0..15] H_CADOP[0..15] H_CADIN[0..15] H_CADON[0..15] H_CADOP[0..15] <10> 2 H_CADON[0..15] <10> C535 4.7U_0805_10V4Z 1 1 C534 4.7U_0805_10V4Z 2 C520 0.22U_0603_16V4Z 2 1 C518 0.22U_0603_16V4Z 2 1 C516 180P_0402_50V8J 2 1 C517 180P_0402_50V8J 2 Near CPU Socket +1.2V_HT +1.2V_HT JCPU1A 2 VLDT=500mA 3 <10> <10> <10> <10> H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 <10> <10> <10> <10> H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1 HT LINK D1 D2 D3 D4 VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3 H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15 E3 E2 E1 F1 G3 G2 G1 H1 J1 K1 L3 L2 L1 M1 N3 N2 E5 F5 F3 F4 G5 H5 H3 H4 K3 K4 L5 M5 M3 M4 N5 P5 L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15 H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 J3 J2 J5 K5 L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1 H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1 N1 P1 P3 P4 L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1 VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3 AE2 AE3 AE4 AE5 1 C533 L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15 AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3 H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15 L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CLKOUT_H1 L0_CLKOUT_L1 Y1 W1 Y4 Y3 H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 L0_CTLOUT_H0 L0_CTLOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1 R2 R3 T5 R5 H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 2 2 4.7U_0805_10V4Z 3 H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 <10> <10> <10> <10> H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 <10> <10> <10> <10> 6090022100G_B Athlon 64 S1 Processor Socket CONN@ 4 4 Compal Secret Data Security Classification 2008/11/03 Issued Date 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. AMD CPU S1G2 HT I/F Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Sheet Tuesday, February 03, 2009 E 4 of 46 A B C D E Processor DDR2 Memory Interface PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH +1.8V 2 1 R79 1K_0402_1% DDRA_CLK0# 2 C244 1.5P_0402_50V9C 1 DDRA_CLK1 1 R78 1K_0402_1% 1 2 C189 1000P_0402_50V7K 1 C181 0.1U_0402_16V4Z 2 +MCH_REF 1 2 DDRA_CLK1# 2 C178 1.5P_0402_50V9C DDRB_CLK0 1 DDRB_CLK0# 2 C509 1.5P_0402_50V9C DDRB_CLK1 1 DDRB_CLK1# 2 C447 1.5P_0402_50V9C +0.9V +0.9V JCPU1B 2 D10 C10 B10 AD10 Place them close to CPU within 1" +1.8V R343 39.2_0402_1% 1 2 1 2 R352 39.2_0402_1% T5 <8> DDRA_ODT0 <8> DDRA_ODT1 <8> DDRA_SCS0# <8> DDRA_SCS1# <8> DDRA_CKE0 <8> DDRA_CKE1 <8> <8> <8> <8> 3 DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# <8> DDRA_SMA[15..0] <8> DDRA_SBS0# <8> DDRA_SBS1# <8> DDRA_SBS2# <8> DDRA_SRAS# <8> DDRA_SCAS# <8> DDRA_SWE# MBMZP AF10 MBMZN AE10 PAD @ DDRA_ODT0 DDRA_ODT1 DDRA_SCS0# DDRA_SCS1# DDRA_CKE0 DDRA_CKE1 VTT1 VTT2 VTT3 VTT4 MEM:CMD/CTRL/CLK VTT5 VTT6 VTT7 VTT8 VTT9 MEMZP MEMZN H16 RSVD_M1 T19 V22 U21 V19 MA0_ODT0 MA0_ODT1 MA1_ODT0 MA1_ODT1 T20 U19 U20 V20 MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1 J22 J20 MA_CKE0 MA_CKE1 W10 AC10 AB10 AA10 A10 VTT_SENSE Y10 MEMVREF W17 @ VTT_SENSE PAD T2 +MCH_REF @ RSVD_M2 B18 MB0_ODT0 MB0_ODT1 MB1_ODT0 W26 W23 Y26 DDRB_ODT0 DDRB_ODT1 MB0_CS_L0 MB0_CS_L1 MB1_CS_L0 V26 W25 U22 DDRB_SCS0# DDRB_SCS1# MB_CKE0 MB_CKE1 J25 H26 DDRB_CKE0 DDRB_CKE1 DDRB_CLK0 DDRB_CLK0# DDRB_CLK1 DDRB_CLK1# PAD N19 N20 E16 F16 Y16 AA16 P19 P20 MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1 MA_CLK_H2 MA_CLK_L2 MA_CLK_H3 MA_CLK_L3 MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1 MB_CLK_H2 MB_CLK_L2 MB_CLK_H3 MB_CLK_L3 P22 R22 A17 A18 AF18 AF17 R26 R25 DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 DDRA_SMA14 DDRA_SMA15 N21 M20 N22 M19 M22 L20 M24 L21 L19 K22 R21 L22 K20 V24 K24 K19 MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15 MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15 P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24 DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 DDRB_SMA14 DDRB_SMA15 DDRA_SBS0# DDRA_SBS1# DDRA_SBS2# R20 R23 J21 MA_BANK0 MA_BANK1 MA_BANK2 MB_BANK0 MB_BANK1 MB_BANK2 R24 U26 J26 DDRB_SBS0# DDRB_SBS1# DDRB_SBS2# DDRA_SRAS# DDRA_SCAS# DDRA_SWE# R19 T22 T24 MA_RAS_L MA_CAS_L MA_WE_L MB_RAS_L MB_CAS_L MB_WE_L U25 U24 U23 DDRB_SRAS# DDRB_SCAS# DDRB_SWE# DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# JCPU1C <9> DDRB_SDQ[63..0] DDRA_CLK0 1 T17 DDRB_ODT0 <9> DDRB_ODT1 <9> DDRB_SCS0# <9> DDRB_SCS1# <9> DDRB_CKE0 <9> DDRB_CKE1 <9> DDRB_CLK0 <9> DDRB_CLK0# <9> DDRB_CLK1 <9> DDRB_CLK1# <9> <9> DDRB_SDM[7..0] DDRB_SMA[15..0] <9> DDRB_SBS0# <9> DDRB_SBS1# <9> DDRB_SBS2# <9> DDRB_SRAS# <9> DDRB_SCAS# <9> DDRB_SWE# <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS3 DDRB_SDQS3# DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS5 DDRB_SDQS5# DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS7 DDRB_SDQS7# Athlon 64 S1 Processor Socket MEM:DATA DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15 DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31 DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63 C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11 Y11 AE14 AF14 AF11 AD11 MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63 DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7 A12 B16 A22 E25 AB26 AE22 AC16 AD12 MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7 DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS3 DDRB_SDQS3# DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS5 DDRB_SDQS5# DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS7 DDRB_SDQS7# C12 B12 D16 C16 A24 A23 F26 E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12 DDRA_SDQ[63..0] <8> MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63 G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12 DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63 MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7 E12 C15 E19 F24 AC24 Y19 AB16 Y13 DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7 MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7 MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7 G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13 DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS7 DDRA_SDQS7# 6090022100G_B Athlon 64 S1 Processor Socket 1 2 DDRA_SDM[7..0] <8> 3 DDRA_SDQS0 <8> DDRA_SDQS0# <8> DDRA_SDQS1 <8> DDRA_SDQS1# <8> DDRA_SDQS2 <8> DDRA_SDQS2# <8> DDRA_SDQS3 <8> DDRA_SDQS3# <8> DDRA_SDQS4 <8> DDRA_SDQS4# <8> DDRA_SDQS5 <8> DDRA_SDQS5# <8> DDRA_SDQS6 <8> DDRA_SDQS6# <8> DDRA_SDQS7 <8> DDRA_SDQS7# <8> CONN@ CONN@ 4 4 Compal Secret Data Security Classification 2008/11/03 Issued Date 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. AMD CPU S1G2 DDRII I/F Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Sheet Tuesday, February 03, 2009 E 5 of 46 B C 2 1 2 FBM_L11_201209_300L_0805 1 + 1 C282 1 C255 2 2 CPU_THERMTRIP#_R C261 0.22U_0603_16V4Z 21 2 3900P_0402_50V7K Address:100_1100 +1.8VS +1.8V Place close to CPU wihtin 1.5" 2 R82 R86 +1.2V_HT 1 R420 300_0402_5% +CPU_CORE_0 R92 LDT_RST# <19> LDT_RST# 1 2 C554 0.01U_0402_16V7K @ R95 1 1 +CPU_CORE_1 R80 2 +1.8VS R81 H_PWRGD R6 P6 HT_REF0 HT_REF1 F6 E6 CPU_VDD1_FB_H Y6 CPU_VDD1_FB_L AB6 T21 T22 T23 T24 T25 T26 +1.8VS R108 300_0402_5% @ @ 1 2 C553 0.01U_0402_16V7K @ CPU_VDD0_FB_H CPU_VDD0_FB_L TEST25_H 1 2 VDDNB_FB_H VDDNB_FB_L H6 G6 TEST18 TEST19 PAD PAD PAD PAD PAD PAD @ @ @ @ @ @ E9 E8 CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1 CPU_TEST22_SCANSHIFTEN CPU_TEST12_SCANSHIFTENB CPU_TEST27_SINGLECHAIN 1 R418 2 0_0402_5% TEST25_L 2 2 2 1 <11,19> LDT_STOP# 3 VDD1_FB_H VDD1_FB_L TEST23 R107 300_0402_5% R98 300_0402_5% @ @ W9 Y9 CPU_TEST18_PLLTEST1 H10 CPU_TEST19_PLLTEST0 G9 R105 300_0402_5% DBREQ_L TDO C2 AA6 TEST9 TEST6 A3 A5 B3 B5 C1 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 THERMDC_CPU THERMDA_CPU T30 T29 @ 1 2 H_PROCHOT# <19> +1.2V_HT +CPU_CORE_NB CPU_VDDNB_FB_H CPU_VDDNB_FB_L R101 10_0402_5% CPU_VDDNB_FB_H 1 2 CPU_VDDNB_FB_L 1 2 R106 10_0402_5% CPU_VDDNB_FB_H <44> CPU_VDDNB_FB_L <44> R337 0_0402_5% @ Close to CPU E10 CPU_DBREQ# AE9 CPU_TDO CPU_TEST10 CPU_TEST28_H_PLLCHRZ_P CPU_TEST28_L_PLLCHRZ_N TEST17 TEST16 TEST15 TEST14 D7 E7 F7 C7 CPU_TEST17_BP3 CPU_TEST16_BP2 CPU_TEST15_BP1 CPU_TEST14_BP0 TEST7 TEST10 C3 K8 CPU_TEST10 TEST8 C4 TEST29_H TEST29_L C9 C8 @ @ @ @ @ @ PAD PAD PAD PAD PAD PAD 2 route as differential as short as possible testpoint under package T3 T4 T16 T7 T6 T9 +1.8V 0718 AMD --> 1K ohm CPU_SVC CPU_SVD RSVD10 RSVD9 RSVD8 RSVD7 RSVD6 CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N @ @ PAD PAD 1 R415 1 R416 2 1K_0402_5% 2 1K_0402_5% CPU_TEST20_SCANCLK2 CPU_TEST21_SCANEN R537 CPU_TEST24_SCANCLK1R538 CPU_TEST23_TSTUPD R539 R535 T8 T15 H18 H19 AA7 D5 C5 1 1 1 1 2 2 300_0402_5% 2 300_0402_5% 2 300_0402_5% 300_0402_5% @ CPU internal thermal sensor 2 1 R531 1 R532 1 R533 R360 @ 1 2 3 4 5 6 7 8 9 10 11 12 CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO 1 1 2 R370 2 0_0402_5% 1 @ CPU_TEST18_PLLTEST1 CPU_TEST19_PLLTEST0 CPU_TEST22_SCANSHIFTEN @ 1 20K_0402_5% H_P ROCHOT# +1.8V @ PAD @ PAD 2 @ 300_0402_5% 2 @ 300_0402_5% 2 @ 300_0402_5% HDT_RST# C436 0.1U_0402_16V4Z +3VS 1 JP29 LDT_STOP# R351 R353 2 J7 H8 TEST28_H TEST28_L TEST25_H TEST25_L TEST21 TEST20 TEST24 TEST22 TEST12 TEST27 2 300_0402_5% 300_0402_5% 6090022100G_B C245 0.01U_0402_16V7K @ H_THERMTRIP# <20> +1.8V sense no support DBRDY TMS TCK TRST_L TDI AB8 AF7 AE7 AE8 AC8 AF8 1 R357 +1.8V VDDIO_FB_H VDDIO_FB_L AD7 CPU_SVC <44> CPU_SVD <44> AF6 CPU_THERMTRIP#_R AC7 H_PROCHOT# AA8 CPU_MEMHOT#_1.8V VDD0_FB_H VDD0_FB_L CPU_TEST23_TSTUPD @ PAD @ PAD THERMTRIP_L PROCHOT_L MEMHOT_L CPU_SVC CPU_SVD A6 A4 W7 W8 G10 AA9 AC9 AD9 AF9 +1.8VS R113 300_0402_5% MAINPWON <38,39> H_THERMTRIP# M11 W18 THERMDC THERMDA CPU_ DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI TEST25_H TEST25_L 2 1 +1.8VS 2 <19> H_PWRGD T27 T28 SVC SVD SIC SID ALERT_L 10_0402_5% 1 1 R419 300_0402_5% 10_0402_5% 1 2CPU_VDD1_FB_H 1 2CPU_VDD1_FB_L @ KEY1 KEY2 AF4 AF5 AE6 <44> CPU_VDD1_FB_H <44> CPU_VDD1_FB_L T10 PAD CLKIN_H CLKIN_L CPU_SIC CPU_SID @ 1 2 R356 1K_0402_5% 2 44.2_0402_1% CPU_HTREF0 2 44.2_0402_1% CPU_HTREF1 Close to CPU 2 VDDA1 VDDA2 A9 A8 RESET_L PWROK LDTSTOP_L LDTREQ_L <44> CPU_VDD0_FB_H <44> CPU_VDD0_FB_L 10_0402_5% 1 2CPU_VDD0_FB_H 1 2CPU_VDD0_FB_L 10_0402_5% MAINPWON 1 B7 A7 F10 C6 <11> CPU_LDT_REQ# 2 1 C532 F8 F9 LDT_RST# H_PWRGD LDT_STOP# CPU_LDT_REQ# R409 169_0402_1% <15> CLK_CPU_BCLK# R335 2 @ 0_0402_5% R334 2 0_0402_5% JCPU1D CPU_CLKIN_SC_P CPU_CLKIN_SC_N 2 3900P_0402_50V7K 1 C531 1 MMBT3904_NL_SOT23-3 1 <15> CLK_CPU_BCLK 1 Q32 1 3 C 2 1 C264 E 4.7U_0805_10V4Z 150U_D2_6.3VM 2 10K_0402_5% 2 300_0402_5% B A:Need to re-Link "SGN00000200" 1 R364 1 R358 +1.8V VDDA=300mA 3300P_0402_50V7K E 1 +2.5VDDA L33 +2.5VS D 2 A 1 34.8K_0402_1%~N 2.09V for Gate 1 2 3 4 5 6 7 8 9 10 GND GND 3 ACES_85201-1005N @ R361 G +1.8V 1 Q30 @ @ 2 0_0402_5% EC_SMB_CK1 <14,30,38> CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO FDV301N_NL_SOT23-3 FDV301N, the Vgs is: min = 0.65V Typ = 0.85V Max = 1.5V EC is PU to 5VALW 0.1U_0402_16V4Z 1 R569 1 C446 @ @ @ HDT Connector JP1 1 3 5 7 9 11 13 15 17 19 21 23 @ 2 NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY. U27 1 THERMDA_CPU 2 C449 THERMDC_CPU 3 1 2 2200P_0402_50V7K 4 2200p change to 1000p for ADT7421 VDD SCLK 8 EC_SMB_CK2 EC_SMB_DA2 D+ SDATA 7 D- ALERT# 6 GND 5 THERM# EC_SMB_CK2 <30> R93 1 2 0_0402_5% +3VS U8 HDT_RST# 4 B 2 A 1 Y SAMTEC_ASP-68200-07 LDT_RST# SB_PWRGD <20,32> @ NC7SZ08P5X_NL_SC70-5 EC_SMB_DA2 <30> Compal Secret Data Security Classification 2008/11/03 Issued Date ADM1032ARMZ_MSOP8 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Address:100_1101 A @ 2 4 6 8 10 12 14 16 18 20 22 24 26 5 3 D C449 3300p for tigris 2CPU_SIC 0_0402_5% @ S 4 G 1 R565 <20> CPU_SIC_SB +3VS EC_SMB_DA1 <14,30,38> 2 R365 2 1 390_0402_5% +1.8V 2 0_0402_5% P 1 R567 @ FDV301N_NL_SOT23-3 G 1 3 3 Q31 @ 2 1 220_0402_5%R112 2 1 220_0402_5%R115 2 1 220_0402_5%R118 2 1 220_0402_5%R119 2 1 300_0402_5%R129 @ D 2CPU_SID 0_0402_5% S 1 R564 2 2 1 390_0402_5% +1.8V <20> CPU_SID_SB B C D Title Compal Electronics, Inc. AMD CPU S1G2 CTRL Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Sheet Tuesday, February 03, 2009 E 6 of 46 4 A B C D E JCPU1F VDD(+CPU_CORE) decoupling. +CPU_CORE_0 +CPU_CORE_1 1 1 + 1 + C80 330U_X_2VM_R6M 1 2 + C79 330U_X_2VM_R6M 2 1 C77 330U_X_2VM_R6M 2 + C78 330U_X_2VM_R6M 2 Near CPU Socket +CPU_CORE_0 +CPU_CORE_1 +CPU_CORE_NB 1 C214 22U_0805_6.3V6M 2 1 C225 22U_0805_6.3V6M 2 1 C221 22U_0805_6.3V6M 2 1 C224 22U_0805_6.3V6M 1 2 1 C196 22U_0805_6.3V6M 2 C200 22U_0805_6.3V6M 2 +CPU_CORE_0 1 1 C186 22U_0805_6.3V6M 2 1 C201 22U_0805_6.3V6M 2 +1.8V +CPU_CORE_1 C220 0.22U_0603_16V4Z 2 1 C217 0.01U_0402_25V4Z 2 1 JCPU1E +CPU_CORE_0 1 C219 180P_0402_50V8J 2 C195 0.22U_0603_16V4Z 2 1 C184 0.01U_0402_25V4Z 2 1 C179 180P_0402_50V8J 2 Under CPU Socket 2 G4 H2 J9 J11 J13 J15 K6 K10 K12 K14 L4 L7 L9 L11 L13 L15 M2 M6 M8 M10 N7 N9 N11 VDD0_1 VDD0_2 VDD0_3 VDD0_4 VDD0_5 VDD0_6 VDD0_7 VDD0_8 VDD0_9 VDD0_10 VDD0_11 VDD0_12 VDD0_13 VDD0_14 VDD0_15 VDD0_16 VDD0_17 VDD0_18 VDD0_19 VDD0_20 VDD0_21 VDD0_22 VDD0_23 K16 M16 P16 T16 V16 VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5 H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 AA4 AA11 AA13 AA15 AA17 AA19 AB2 AB7 AB9 AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21 AD6 AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23 B4 B6 B8 B9 B11 B13 B15 B17 B19 B21 B23 B25 D6 D8 D9 D11 D13 D15 D17 D19 D21 D23 D25 E4 F2 F11 F13 F15 F17 F19 F21 F23 F25 H7 H9 H21 H23 J4 +CPU_CORE_1 VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8 VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26 P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2 VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13 Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18 +1.8V 6090022100G_B Athlon 64 S1 Processor Socket VDDIO decoupling. +CPU_CORE_NB decoupling. +1.8V +CPU_CORE_NB 1 C206 22U_0805_6.3V6M 2 1 C226 22U_0805_6.3V6M 1 1 C216 C230 1 1 C191 C182 1 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J 2 2 2 2 2 C198 22U_0805_6.3V6M 2 1 C207 22U_0805_6.3V6M 2 1 C223 22U_0805_6.3V6M 2 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6 1 2 6090022100G_B Under CPU Socket Athlon 64 S1 Processor Socket Between CPU Socket and DIMM +1.8V +0.9V 3 1 C235 0.22U_0603_16V4Z 2 1 C234 0.22U_0603_16V4Z 2 C165 0.22U_0603_16V4Z 2 +1.8V 1 1 C162 0.01U_0402_25V4Z 2 1 C163 0.01U_0402_25V4Z 2 C166 0.22U_0603_16V4Z 1 C164 180P_0402_50V8J 2 1 C237 180P_0402_50V8J 2 C273 22U_0805_6.3V6M C238 180P_0402_50V8J 2 2 +0.9V 1 2 C239 1 180P_0402_50V8J C141 4.7U_0805_10V4Z 2 A: Add C165 and C176 to follow AMD Layout review recommand for EMI +1.8V C: Change to NBO CAP 1 2 180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch> 3 Near Power Supply 1 + C281 220U_D2_4VM_R15 2 +1.8V 1 1 VTT decoupling. 1 C146 4.7U_0805_10V4Z 2 1 C144 0.22U_0603_16V4Z 2 1 C148 0.22U_0603_16V4Z 2 1 C174 1000P_0402_50V7K 2 1 C173 1000P_0402_50V7K 2 1 C172 180P_0402_50V8J 2 1 C175 180P_0402_50V8J 2 Near CPU Socket Right side. +0.9V 1 1 2 1 C167 4.7U_0805_10V4Z 2 1 C168 4.7U_0805_10V4Z 2 1 C169 4.7U_0805_10V4Z 2 1 + C233 C170 4.7U_0805_10V4Z 2 + C218 220U_D2_4VM_R15 220U_D2_4VM_R15 2 @ 1 2 4 C541 4.7U_0805_10V4Z 1 C530 4.7U_0805_10V4Z 2 1 C514 0.22U_0603_16V4Z 2 1 C515 0.22U_0603_16V4Z 2 1 C528 1000P_0402_50V7K 2 1 C537 1000P_0402_50V7K 2 1 C540 180P_0402_50V8J 2 1 C543 180P_0402_50V8J 2 4 C: Change to NBO CAP Near CPU Socket Left side. Compal Secret Data Security Classification 2008/11/03 Issued Date 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. AMD CPU S1G2 PWR & GND Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Sheet Tuesday, February 03, 2009 E 7 of 46 A B +1.8V C D E +1.8V RESERVE +V_DDR_MCH_REF BUFFER CIRCUIT JDIMM1 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQS2# DDRA_SDQS2 <5> DDRA_SDQS2# <5> DDRA_SDQS2 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDM3 DDRA_SDQ26 DDRA_SDQ27 2 DDRA_CKE0 <5> DDRA_CKE0 DDRA_SBS2# <5> DDRA_SBS2# DDRA_SMA12 DDRA_SMA9 DDRA_SMA8 DDRA_SMA5 DDRA_SMA3 DDRA_SMA1 DDRA_SMA10 DDRA_SBS0# DDRA_SWE# <5> DDRA_SBS0# <5> DDRA_SWE# DDRA_SCAS# DDRA_SCS1# <5> DDRA_SCAS# <5> DDRA_SCS1# DDRA_ODT1 <5> DDRA_ODT1 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQS4# DDRA_SDQS4 <5> DDRA_SDQS4# <5> DDRA_SDQS4 DDRA_SDQ34 DDRA_SDQ35 3 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDM5 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQS6# DDRA_SDQS6 <5> DDRA_SDQS6# <5> DDRA_SDQS6 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDM7 DDRA_SDQ58 DDRA_SDQ59 ICH_SMBDATA0 ICH_SMBCLK0 <9,15,20,28> ICH_SMBDATA0 <9,15,20,28> ICH_SMBCLK0 +3VS 4 1 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 GND DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ[63..0] <5> DDRA_SDQ12 DDRA_SDQ13 DDRA_SMA[15..0] DDRA_SDM[7..0] <5> 1 DDRA_SMA[15..0] <5> DDRA_SDM1 DDRA_SMA6 DDRA_SMA7 DDRA_SMA11 DDRA_SMA15 DDRA_CLK0 <5> DDRA_CLK0# <5> DDRA_SDQ14 DDRA_SDQ15 +1.8V 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204 C414 1 DDRA_SDQ20 DDRA_SDQ21 +V_DDR_MCH_REF DDRA_SDQ22 DDRA_SDQ23 1 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQS3# DDRA_SDQS3 2 DDRA_SDQS3# <5> DDRA_SDQS3 <5> DDRA_SDQ30 DDRA_SDQ31 DDRA_CKE1 DDRA_CKE0 DDRA_SBS2# DDRA_SMA14 DDRA_CKE1 R148 1K_0402_1% DDRA_SDM2 1 2 DDRA_SBS1# DDRA_SMA0 DDRA_SMA2 DDRA_SMA4 +V_DDR_MCH_REF R141 1K_0402_1% DDRA_SMA5 DDRA_SMA8 DDRA_SMA9 DDRA_SMA12 DDRA_CKE1 <5> DDRA_SMA15 DDRA_SMA14 DDRA_SMA4 DDRA_SMA2 DDRA_SMA0 DDRA_SBS1# DDRA_SRAS# DDRA_SCS0# DDRA_ODT0 DDRA_SMA13 +1.8V DDRA_SBS1# <5> DDRA_SRAS# <5> DDRA_SCS0# <5> 1 0.1U_0402_16V4Z 1 C155 DDRA_ODT0 <5> 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 C151 C128 C124 2 2 0.1U_0402_16V4Z 1 2 3 4 8 7 6 5 47_0804_8P4R_5% RP23 8 1 7 2 6 3 5 4 47_0804_8P4R_5% RP17 1 8 2 7 3 6 4 5 47_0804_8P4R_5% RP18 8 1 7 2 6 3 5 4 1 C187 1 C213 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 C194 1 C222 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 C157 1 C152 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 C190 1 C211 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 DDRA_SBS0# DDRA_SMA10 DDRA_SMA1 DDRA_SMA3 47_0804_8P4R_5% RP15 8 1 7 2 6 3 5 4 1 C180 1 C199 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z DDRA_SCS1# DDRA_ODT1 DDRA_SWE# DDRA_SCAS# 47_0804_8P4R_5% RP9 8 1 7 2 6 3 5 4 1 C161 1 C156 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z DDRA_SMA13 DDRA_ODT0 DDRA_SCS0# DDRA_SRAS# 47_0804_8P4R_5% RP12 1 8 2 7 3 6 4 5 1 C159 1 C154 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z DDRA_SMA11 DDRA_SMA7 DDRA_SMA6 47_0804_8P4R_5% DDRA_SDQ36 DDRA_SDQ37 DDRA_SDM4 +0.9V DDRA_SDQ38 DDRA_SDQ39 3 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQS5# DDRA_SDQS5 1 DDRA_SDQS5# <5> DDRA_SDQS5 <5> 0.1U_0402_16V4Z 1 C113 2 2 0.1U_0402_16V4Z DDRA_SDQ46 DDRA_SDQ47 C119 0.1U_0402_16V4Z 1 1 C55 C197 2 2 0.1U_0402_16V4Z DDRA_SDQ52 DDRA_SDQ53 DDRA_CLK1 DDRA_CLK1# DDRA_CLK1 <5> DDRA_CLK1# <5> DDRA_SDM6 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQS7# DDRA_SDQS7 DDRA_SDQS7# <5> DDRA_SDQS7 <5> DDRA_SDQ62 DDRA_SDQ63 R314 1 R315 1 DIMM1 REV H:5.2mm (BOT) 0.1U_0402_16V4Z 2 2 4.7U_0805_10V4Z 2 10K_0402_5% 2 10K_0402_5% 4 Compal Secret Data Security Classification 2008/11/03 Issued Date 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A +1.8V +0.9V RP20 DDRA_CLK0 DDRA_CLK0# FOX_AS0A426-M2RN-7F CONN@ +3VS C413 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 203 DDRA_SDQ[63..0] DDRA_SDM[7..0] 2 DDRA_SDQS1# DDRA_SDQS1 <5> DDRA_SDQS1# <5> DDRA_SDQS1 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDM0 1 DDRA_SDQ8 DDRA_SDQ9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 DDRA_SDQ2 DDRA_SDQ3 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS 1 1 DDRA_SDQS0# DDRA_SDQS0 <5> DDRA_SDQS0# <5> DDRA_SDQS0 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS C257 1U_0402_6.3V4Z DDRA_SDQ0 DDRA_SDQ1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 C256 1000P_0402_50V7K +V_DDR_MCH_REF B C D Title Compal Electronics, Inc. DDRII SO-DIMM 0 Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Sheet Tuesday, February 03, 2009 E 8 of 46 A B +1.8V C D +1.8V DDRB_SDQ[63..0] JDIMM2 +V_DDR_MCH_REF DDRB_SDQ0 DDRB_SDQ1 1 <5> DDRB_SDQS0# <5> DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS0 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ8 DDRB_SDQ9 <5> DDRB_SDQS1# <5> DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS1 DDRB_SDQ10 DDRB_SDQ11 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 DDRB_SDQ[63..0] <5> DDRB_SDM[7..0] DDRB_SDQ4 DDRB_SDQ5 DDRB_SDM[7..0] <5> DDRB_SMA[15..0] DDRB_SRAS# DDRB_SMA0 DDRB_SMA2 DDRB_SMA4 DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDM3 2 DDRB_SDQ26 DDRB_SDQ27 <5> DDRB_CKE0 <5> DDRB_SBS2# DDRB_CKE0 DDRB_SBS2# DDRB_SMA12 DDRB_SMA9 DDRB_SMA8 DDRB_SMA5 DDRB_SMA3 DDRB_SMA1 <5> DDRB_SBS0# <5> DDRB_SWE# <5> DDRB_SCAS# <5> DDRB_SCS1# <5> DDRB_ODT1 DDRB_SMA10 DDRB_SBS0# DDRB_SWE# DDRB_SCAS# DDRB_SCS1# DDRB_ODT1 DDRB_SDQ32 DDRB_SDQ33 <5> DDRB_SDQS4# <5> DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS4 DDRB_SDQ34 DDRB_SDQ35 3 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDM5 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ48 DDRB_SDQ49 <5> DDRB_SDQS6# <5> DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS6 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDM7 DDRB_SDQ58 DDRB_SDQ59 <8,15,20,28> ICH_SMBDATA0 <8,15,20,28> ICH_SMBCLK0 ICH_SMBDATA0 ICH_SMBCLK0 +3VS 4 VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 GND 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 8 7 6 5 2 C185 1 C176 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 C188 1 C193 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 C203 1 C215 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 C205 1 C210 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 C204 1 C209 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 C171 1 C153 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 C158 1 C160 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 RP19 DDRB_SDM1 DDRB_CLK0 DDRB_CLK0# DDRB_SMA6 DDRB_SMA7 DDRB_SMA11 DDRB_SMA14 DDRB_CLK0 <5> DDRB_CLK0# <5> DDRB_SDQ14 DDRB_SDQ15 1 2 3 4 8 7 6 5 47_0804_8P4R_5% RP22 DDRB_SDQ20 DDRB_SDQ21 DDRB_CKE0 DDRB_SBS2# DDRB_SMA15 DDRB_CKE1 +V_DDR_MCH_REF 1 DDRB_SDM2 DDRB_SDQ22 DDRB_SDQ23 2 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQS3# DDRB_SDQS3 1 2 C292 0.1U_0402_16V4Z DDRB_SDQS2# DDRB_SDQS2 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND 1 2 3 4 47_0804_8P4R_5% C202 1000P_0402_25V8J <5> DDRB_SDQS2# <5> DDRB_SDQS2 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 +1.8V +0.9V RP14 DDRB_SMA[15..0] <5> DDRB_SDM0 +V_DDR_MCH_REF DDRB_SDQ16 DDRB_SDQ17 E 1 2 3 4 47_0804_8P4R_5% 1 2 C3388 22U_0805_6.3V6M @ RP21 DDRB_SMA8 DDRB_SMA5 DDRB_SMA12 DDRB_SMA9 8 7 6 5 1 2 3 4 47_0804_8P4R_5% RP16 DDRB_SDQS3# <5> DDRB_SDQS3 <5> DDRB_SBS0# DDRB_SMA10 DDRB_SMA3 DDRB_SMA1 DDRB_SDQ30 DDRB_SDQ31 DDRB_CKE1 8 7 6 5 8 7 6 5 1 2 3 4 2 47_0804_8P4R_5% DDRB_CKE1 <5> DDRB_SMA15 DDRB_SMA14 RP10 DDRB_ODT1 DDRB_SCS1# DDRB_SWE# DDRB_SCAS# DDRB_SMA11 DDRB_SMA7 DDRB_SMA6 8 7 6 5 1 2 3 4 47_0804_8P4R_5% DDRB_SMA4 DDRB_SMA2 DDRB_SMA0 DDRB_SBS1# DDRB_SRAS# DDRB_SCS0# DDRB_ODT0 DDRB_SMA13 RP11 DDRB_SMA13 DDRB_ODT0 DDRB_SCS0# DDRB_SBS1# DDRB_SBS1# <5> DDRB_SRAS# <5> DDRB_SCS0# <5> 1 2 3 4 8 7 6 5 47_0804_8P4R_5% DDRB_ODT0 <5> DDRB_SDQ36 DDRB_SDQ37 DDRB_SDM4 DDRB_SDQ38 DDRB_SDQ39 3 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQS5# DDRB_SDQS5 DDRB_SDQS5# <5> DDRB_SDQS5 <5> DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ52 DDRB_SDQ53 DDRB_CLK1 DDRB_CLK1# DDRB_CLK1 <5> DDRB_CLK1# <5> DDRB_SDM6 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQS7# DDRB_SDQS7 DDRB_SDQS7# <5> DDRB_SDQS7 <5> DDRB_SDQ62 DDRB_SDQ63 R331 1 R327 1 2 10K_0402_5% 2 10K_0402_5% +3VS 4 FOX_AS0A426-MARG-7F CONN@ DIMM1 REV H:9.2mm (BOT) Compal Secret Data Security Classification 2008/11/03 Issued Date 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. DDRII SO-DIMM 1 Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Tuesday, February 03, 2009 Sheet E 9 of 46 A B C <14> PCIE_GTX_C_MRX_P[0..15] <14> PCIE_GTX_C_MRX_N[0..15] D E PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15] PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P[0..15] <14> PCIE_MTX_C_GRX_N[0..15] <14> U25B C683 1 C685 1 C687 1 C689 1 C691 1 C693 1 C695 1 C697 1 C699 1 C701 1 C703 1 C705 1 C707 1 C709 1 C711 1 C680 1 2 VGA@ 0.1U_0402_16V7K C682 1 2 VGA@ 0.1U_0402_16V7K C684 1 2 VGA@ 0.1U_0402_16V7K C686 1 2 VGA@ 0.1U_0402_16V7K C688 1 2 VGA@ 0.1U_0402_16V7K C690 1 VGA@ 0.1U_0402_16V7K 2 C692 1 2 VGA@ 0.1U_0402_16V7K C694 1 2 VGA@ 0.1U_0402_16V7K C696 1 2 VGA@ 0.1U_0402_16V7K C698 1 VGA@ 0.1U_0402_16V7K 2 C700 1 2 VGA@ 0.1U_0402_16V7K C702 1 2 VGA@ 0.1U_0402_16V7K C704 1 2 VGA@ 0.1U_0402_16V7K C706 1 2 VGA@ 0.1U_0402_16V7K C708 1 2 VGA@ 0.1U_0402_16V7K C710 1 2 VGA@ 0.1U_0402_16V7K <28> <28> <28> <28> <26> <26> 2 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_MRX_P0 D4 PCIE_GTX_MRX_N0 C4 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_MRX_P1 A3 PCIE_GTX_MRX_N1 B3 VGA@ 0.1U_0402_16V7K PCIE_GTX_MRX_P2 C2 2 PCIE_GTX_MRX_N2 C1 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_MRX_P3 E5 PCIE_GTX_MRX_N3 F5 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_MRX_P4 G5 PCIE_GTX_MRX_N4 G6 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_MRX_P5 H5 PCIE_GTX_MRX_N5 H6 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_MRX_P6 J6 PCIE_GTX_MRX_N6 J5 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_MRX_P7 J7 PCIE_GTX_MRX_N7 J8 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_MRX_P8 L5 PCIE_GTX_MRX_N8 L6 PCIE_GTX_MRX_P9 M8 VGA@ 0.1U_0402_16V7K 2 PCIE_GTX_MRX_N9 L8 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_MRX_P10 P7 PCIE_GTX_MRX_N10M7 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_MRX_P11 P5 PCIE_GTX_MRX_N11M5 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_MRX_P12 R8 PCIE_GTX_MRX_N12P8 PCIE_GTX_MRX_P13 R6 VGA@ 0.1U_0402_16V7K 2 PCIE_GTX_MRX_N13R5 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_MRX_P14 P4 PCIE_GTX_MRX_N14P3 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_MRX_P15 T4 PCIE_GTX_MRX_N15 T3 PCIE_PTX_C_IRX_P1 PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_P2 PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P3 PCIE_PTX_C_IRX_N3 <19> <19> <19> <19> <19> <19> <19> <19> SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N PCIE_PTX_C_IRX_P1 PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_P2 PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P3 PCIE_PTX_C_IRX_N3 SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N AE3 AD4 AE2 AD3 AD1 AD2 V5 W6 U5 U6 U8 U7 AA8 Y8 AA7 Y7 AA5 AA6 W5 Y5 GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N GPP_RX4P GPP_RX4N GPP_RX5P GPP_RX5N SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N PART 2 OF 6 GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2 GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2 SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5 PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN) AC8 AB8 PCIE I/F PCIE I/F SB PCIE_MTX_GRX_P0 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_P15 PCIE_MTX_GRX_N15 PCIE_ITX_PRX_P1 PCIE_ITX_PRX_N1 PCIE_ITX_PRX_P2 PCIE_ITX_PRX_N2 PCIE_ITX_PRX_P3 PCIE_ITX_PRX_N3 C451 1 2 VGA@0.1U_0402_16V7K C467 1 2 VGA@0.1U_0402_16V7K C453 1 2 VGA@0.1U_0402_16V7K C469 1 2 VGA@0.1U_0402_16V7K C455 1 2VGA@ 0.1U_0402_16V7K C471 1 VGA@ 0.1U_0402_16V7K 2 C457 1 2VGA@ 0.1U_0402_16V7K C473 1 2VGA@ 0.1U_0402_16V7K C459 1 2VGA@ 0.1U_0402_16V7K C475 1 VGA@ 0.1U_0402_16V7K 2 C461 1 2VGA@ 0.1U_0402_16V7K C477 1 2VGA@ 0.1U_0402_16V7K C463 1 2VGA@ 0.1U_0402_16V7K C479 1 2VGA@ 0.1U_0402_16V7K C465 1 2VGA@ 0.1U_0402_16V7K C481 1 2VGA@ 0.1U_0402_16V7K C450 1 C466 1 C452 1 C468 1 C454 1 C470 1 C456 1 C472 1 C458 1 C474 1 C460 1 C476 1 C462 1 C478 1 C464 1 C480 1 C31 C30 C21 C20 C23 C22 1 2 2 1 1 2 2 1 2 VGA@0.1U_0402_16V7K 2 VGA@0.1U_0402_16V7K 2 VGA@0.1U_0402_16V7K 2VGA@ 0.1U_0402_16V7K 2VGA@ 0.1U_0402_16V7K 2VGA@ 0.1U_0402_16V7K 2VGA@ 0.1U_0402_16V7K 2VGA@ 0.1U_0402_16V7K 2VGA@ 0.1U_0402_16V7K 2VGA@ 0.1U_0402_16V7K 2VGA@ 0.1U_0402_16V7K 2VGA@ 0.1U_0402_16V7K 2VGA@ 0.1U_0402_16V7K 2VGA@ 0.1U_0402_16V7K 2VGA@ 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 2 1 1 2 VGA@0.1U_0402_16V7K 2 R33 R31 C271 C268 C290 C295 C263 C265 C262 C260 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 1.27K_0402_1% 2K_0402_1% SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N GFX_TX0,TX1,TX2 and TX3 AUX0 and HPD0 GFX_TX4,TX5,TX6 and TX7 DP1 AUX1 and HPD1 C897 1 2 UMA@ 0.1U_0402_10V7K HDMI_TX2+_UMA HDMI_TX2+_UMA <17> C898 1 2 UMA@ 0.1U_0402_10V7K HDMI_TX2-_UMA HDMI_TX2-_UMA <17> PCIE_MTX_GRX_P1 C899 1 2 UMA@ 0.1U_0402_10V7K HDMI_TX1+_UMA HDMI_TX1+_UMA <17> PCIE_MTX_GRX_N1 C900 1 2 UMA@ 0.1U_0402_10V7K HDMI_TX1-_UMA HDMI_TX1-_UMA <17> PCIE_MTX_GRX_P2 C901 1 2 UMA@ 0.1U_0402_10V7K HDMI_TX0+_UMA HDMI_TX0+_UMA <17> PCIE_MTX_GRX_N2 C902 1 2 UMA@ 0.1U_0402_10V7K HDMI_TX0-_UMA HDMI_TX0-_UMA <17> PCIE_MTX_GRX_P3 C903 1 2 UMA@ 0.1U_0402_10V7K HDMI_CLK+_UMA HDMI_CLK+_UMA <17> PCIE_MTX_GRX_N3 C904 1 2 UMA@ 0.1U_0402_10V7K HDMI_CLK-_UMA HDMI_CLK-_UMA <17> <4> <4> <4> <4> H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 <4> <4> <4> <4> H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 1 4 GLAN <19> <19> <19> <19> <19> <19> <19> <19> H_CADOP[0..15] H_CADON[0..15] 2008/11/03 H_CADIN[0..15] <4> R75 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15 AC24 AC25 AB25 AB24 AA24 AA25 Y22 Y23 W21 W20 V21 V20 U20 U21 U19 U18 HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 T22 T23 AB23 AA22 HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 M22 M23 R21 R20 C23 A24 2 HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22 H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15 HT_TXCLK0P HT_TXCLK0N HT_TXCLK1P HT_TXCLK1N H24 H25 L21 L20 H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N M24 M25 P19 R18 H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1 HT_RXCALP HT_RXCALN HT_TXCALP HT_TXCALN B24 B25 HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N PART 1 OF 6 RS780M_FCBGA528 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C H_CADIP[0..15] <4> H_CADIN[0..15] D 1 3 R76 H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 <4> <4> <4> <4> H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1 <4> <4> <4> <4> 2 4 301_0402_1% 0718 Place within 1" layout 1:2 Compal Secret Data Security Classification Issued Date H_CADIP[0..15] Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25 0718 Place within 1" layout 1:2 B 2 WLAN H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 301_0402_1% A TV Tuner U25A +1.1VS DP0 PCIE_MTX_GRX_N0 <28> <28> <28> <28> <26> <26> <4> H_CADON[0..15] SB_TX0P_C SB_TX0N_C SB_TX1P_C SB_TX1N_C SB_TX2P_C SB_TX2N_C SB_TX3P_C SB_TX3N_C RS780M Display Port Support (muxed on GFX) PCIE_MTX_GRX_P0 PCIE_ITX_C_PRX_P1 PCIE_ITX_C_PRX_N1 PCIE_ITX_C_PRX_P2 PCIE_ITX_C_PRX_N2 PCIE_ITX_C_PRX_P3 PCIE_ITX_C_PRX_N3 1 <4> H_CADOP[0..15] RS780M_FCBGA528 3 PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15 HYPER TRANSPORT CPU I/F C681 1 PCIE I/F GFX 1 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P15 PCIE_GTX_C_MRX_N15 Title Compal Electronics, Inc. RS780-HT/PCIE Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Sheet Tuesday, February 03, 2009 E 10 of 46 A B C L7 +AVDD1 1 2 FBM-L11-201209-300LMA30T_0805 1 For RS780M A13 GMCH_CRT_R 2 133_0402_1% GMCH_CRT_G 2 150_0402_1% GMCH_CRT_B 2 150_0402_1% C65 22U_0805_6.3V6M 2 AVDD=100mA 1 C75 22U_0805_6.3V6M 2 +1.8VS 1 L14 1 2 FBM-L11-201209-300LMA30T_0805 1 U25C C118 2.2U_0603_6.3V4Z GMCH_CRT_HSYNC A11 GMCH_CRT_VSYNC B11 GMCH_CRT_CLK F8 GMCH_CRT_DATA E8 <13,18> GMCH_CRT_HSYNC <13,18> GMCH_CRT_VSYNC <18> GMCH_CRT_CLK <18> GMCH_CRT_DATA 2 R59 2 2 715_0402_1% DAC_RSET G14 1 +NB_PLLVDD +NB_HTPVDD +NB_PLLVDD +NB_HTPVDD A12 D14 B12 2 +1.8VS +VDDA18PCIEPLL L6 1 2 MBK2012221YZF 0805 1 C69 2.2U_0603_6.3V4Z 2 D7 E7 VDDA18PCIEPLL1 VDDA18PCIEPLL2 D8 A10 C10 C12 SYSRESETb POWERGOOD LDTSTOPb ALLOW_LDTSTOP CLK_NBHT CLK_NBHT# C25 C24 HT_REFCLKP HT_REFCLKN NB_OSC_14.318M E11 F11 REFCLK_P/OSCIN(OSCIN) REFCLK_N(PWM_GPIO3) <15> NB_OSC_14.318M +1.1VS 1 2 R40 4.7K_0402_5% 1 2 R34 4.7K_0402_5% 3 CLK_NBGFX CLK_NBGFX# <15> CLK_NBGFX <15> CLK_NBGFX# CLK_SBLINK_BCLK CLK_SBLINK_BCLK# <15> CLK_SBLINK_BCLK <15> CLK_SBLINK_BCLK# +3VS 1 R325 1 R329 GMCH_LCD_CLK 2 4.7K_0402_5% GMCH_LCD_DATA 2 4.7K_0402_5% 1 R3181 @ R323 @ GMCH_DDC_CLK 2 GMCH_DDC_DATA 4.7K_0402_5% 2 4.7K_0402_5% <16> <16> <17> <17> Strap pin R530 2.2K_0402_5% 2 1 GMCH_CRT_CLK 2 4.7K_0402_5% GMCH_CRT_DATA 2 4.7K_0402_5% 1 R5111 R512 2 R41 1 10K_0402_5% POWER_SEL <41> POWER_SEL +3VS +5VS 1 2 R847 0_0402_5% 1 2 R846 @ 0_0402_5% GMCH_LCD_CLK GMCH_LCD_DATA GMCH_DDC_DATA GMCH_DDC_CLK GMCH_LCD_CLK GMCH_LCD_DATA GMCH_DDC_DATA GMCH_DDC_CLK +3VS PLLVDD(NC) PLLVDD18(NC) PLLVSS(NC) +VDDA18PCIEPLL <15> CLK_NBHT <15> CLK_NBHT# AUX_CAL <13> AUX_CAL VDDA18HTPLL T2 T1 GFX_REFCLKP GFX_REFCLKN U1 U2 GPP_REFCLKP GPP_REFCLKN V4 V3 GPPSB_REFCLKP(SB_REFCLKP) GPPSB_REFCLKN(SB_REFCLKN) B9 A9 B8 A8 B7 A7 I2C_CLK I2C_DATA DDC_DATA0/AUX0N(NC) DDC_CLK0/AUX0P(NC) DDC_CLK1/AUX1P(NC) DDC_DATA1/AUX1N(NC) B10 STRP_DATA G11 RSVD C8 +1.8VS 2 R540 1k for RS880M A13 B13 VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC) A15 B15 A14 B14 VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS) C14 D15 C16 C18 C20 E20 C22 LVDS_DIGON(PCE_TCALRP) LVDS_BLON(PCE_RCALRP) LVDS_ENA_BL(PWM_GPIO2) E9 F7 G12 SUS_STAT#(PWM_GPIO5) D12 THERMALDIODE_P THERMALDIODE_N AE8 AD8 TESTMODE D13 1 C442 0.1U_0402_16V4Z R26 1 D9 D10 L46 1 2 MBC1608121YZF_0603 +VDDLT18 +VDDLT18 UMA@ TMDS_HPD(NC) HPD(NC) <16> <16> <16> <16> +VDDLTP18 R328 1.27K_0402_1% MIS. 2 1 R347 @ R313 1.27K_0402_1% @ 2 0_0402_5% 1 R350 @ 1 2 2 +1.8VS R330 0_0402_5% 1 UMA@ 2 GMCH_ENVDD 1 2 ENBKL UMA@ R317 0_0402_5% GMCH_ENVDD <16> ENBKL <14,30> BKOFF# <16,30> UMA_PNL_PWM <16> 2 0_0402_5% UMA@ 10K_0402_5% 2 UMA_HPD UMA_HPD <17> R316 0_0402_5% 1 2SUS_STAT# SUS_STAT_R# NB_THERMAL_DA NB_THERMAL_DC SUS_STAT# <20> SUS_STAT_R# <13> NB_THERMAL_DA <21> NB_THERMAL_DC <21> Strap pin 3 NB temp to SB 1 2 R359 1.8K_0402_5% 1 NB_PWRGD_R R338 300_0402_5% @ @ R534 4.7K_0402_5% D S FDV301N_NL_SOT23-3 3 D NB_ALLOW_LDTSTOP FDV301N_NL_SOT23-3 Q56 @ 2 2 R324 4.7K_0402_5% @ R571 G 2 0_0402_5% 1 S <19> ALLOW_LDTSTOP +3VS +1.8VS R332 1 1 3 1 D S <6,19> LDT_STOP# NB_LDTSTOP# 4 2 0_0402_5% FDV301N_NL_SOT23-3 Q28 @ Compal Secret Data Security Classification R570 1 2 2008/11/03 Issued Date 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 0_0402_5% A 2 C443 4.7U_0805_10V4Z +3VS 2 G 0_0402_5% 1 2 R414 1 2 G <6> CPU_LDT_REQ# @ 4 +1.8VS R540 300_0402_5% Q29 1 VDDLTP18(NC) VSSLTP18(NC) GMCH_TXCLK+ GMCH_TXCLKGMCH_TZCLK+ GMCH_TZCLK- <16> <16> <16> <16> <16> <16> +1.8VS C439 2.2U_0603_6.3V4Z RS780M_FCBGA528 Strap pin R333 300_0402_5% 1 GMCH_TXCLK+ GMCH_TXCLKGMCH_TZCLK+ GMCH_TZCLK- AUX_CAL(NC) +1.8VS 3 B16 A16 D16 D17 GMCH_TZOUT0+ GMCH_TZOUT0GMCH_TZOUT1+ GMCH_TZOUT1GMCH_TZOUT2+ GMCH_TZOUT2- L42 1 2 1 MBC1608121YZF_0603 +VDDLTP18 @ +1.8VS <20> NB_PWRGD TXCLK_LP(DBG_GPIO1) TXCLK_LN(DBG_GPIO3) TXCLK_UP(PCIE_RESET_GPIO4) TXCLK_UN(PCIE_RESET_GPIO1) DAC_RSET(PWM_GPIO1) +VDDA18HTPLL NB_RESET# NB_PWRGD_R NB_LDTSTOP# NB_ALLOW_LDTSTOP B18 A18 A17 B17 D20 D21 D18 D19 DAC_HSYNC(PWM_GPIO4) DAC_VSYNC(PWM_GPIO6) DAC_SCL(PCE_RCALRN) DAC_SDA(PCE_TCALRN) H17 R319 PLT_RST# 1 2 0_0402_5% <13,19,26,28,30> PLT_RST# TXOUT_U0P(NC) TXOUT_U0N(NC) TXOUT_U1P(PCIE_RESET_GPIO3) TXOUT_U1N(PCIE_RESET_GPIO2) TXOUT_U2P(NC) TXOUT_U2N(NC) TXOUT_U3P(PCIE_RESET_GPIO5) TXOUT_U3N(NC) 2 L17 1 2 MBK2012221YZF 0805 1 GMCH_CRT_B <18> GMCH_CRT_B RED(DFT_GPIO0) REDb(NC) GREEN(DFT_GPIO1) GREENb(NC) BLUE(DFT_GPIO3) BLUEb(NC) 2 C433 2.2U_0603_6.3V4Z G18 G17 E18 F18 E19 F19 GMCH_TZOUT0+ GMCH_TZOUT0GMCH_TZOUT1+ GMCH_TZOUT1GMCH_TZOUT2+ GMCH_TZOUT2- 1 <18> GMCH_CRT_G 1 2 MBK2012221YZF 0805 1 +VDDA18HTPLL GMCH_CRT_G C_Pr(DFT_GPIO5) Y(DFT_GPIO2) COMP_Pb(DFT_GPIO4) 1 +NB_PLLVDD L41 +1.8VS GMCH_CRT_R <18> GMCH_CRT_R +1.1VS E17 F17 F15 <16> <16> <16> <16> <16> <16> 2 2 2 GMCH_TXOUT0+ GMCH_TXOUT0GMCH_TXOUT1+ GMCH_TXOUT1GMCH_TXOUT2+ GMCH_TXOUT2- 1 C84 2.2U_0603_6.3V4Z +AVDDQ 1 GMCH_TXOUT0+ GMCH_TXOUT0GMCH_TXOUT1+ GMCH_TXOUT1GMCH_TXOUT2+ GMCH_TXOUT2- TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC) TXOUT_L2N(DBG_GPIO0) TXOUT_L3P(NC) TXOUT_L3N(DBG_GPIO2) PM 1 2 FBM-L11-201209-300LMA30T_0805 C99 2.2U_0603_6.3V4Z +NB_HTPVDD L10 1 2 MBK2012221YZF 0805 1 A22 B22 A21 B21 B20 A20 A19 B19 PART 3 OF 6 21 +1.8VS AVDD1(NC) AVDD2(NC) AVDDDI(NC) AVSSDI(NC) AVDDQ(NC) AVSSQ(NC) CRT/TVOUT L12 F12 E12 F14 G15 H15 H14 PLL PWR LVTM 2 CLOCKs C106 2.2U_0603_6.3V4Z +1.8VS +AVDD2 2 1 E +3VS 140 1 R64 1 R63 1 R71 D B C D Title Compal Electronics, Inc. RS780 VEDIO/CLK GEN Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Sheet Tuesday, February 03, 2009 E 11 of 46 A B C D E U25F shape add FBMA-L11-201209-221LMA30T_0805 C33 + 2 2 2 22U_0805_6.3V6M L9 2A 2 1 FBMA-L11-201209-221LMA30T_0805 1 C72 22U_0805_6.3V6M C88 22U_0805_6.3V6M 1 C123 2 1 C136 1 C135 2 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE 1 C92 2 1 C134 1 C87 2 1 C91 2 1 C93 2 2 0.1U_0402_16V4Z 1 J10 P10 K10 M10 L10 W9 H9 T10 R10 Y9 AA9 AB9 AD9 AE9 U10 0.6A C89 2 0.1U_0402_16V4Z 22U_0805_6.3V6M 0.64A F9 G9 AE11 AD11 +1.8VS +1.8VS C432 1U_0402_6.3V4Z 1 1 2 2 3 VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13 VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15 VDD18_1 VDD18_2 VDD18_MEM1(NC) VDD18_MEM2(NC) VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC) VDD33_1(NC) VDD33_2(NC) +NB_CORE K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16 +1.1VS VDD_CORE=5A 7.6A 1 2 2 0_0805_5% 2 0_0805_5% 1 L4 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 1 2 1 + 2 1 + 2 L12 M14 N13 P12 P15 R11 R14 T12 U14 U11 U15 V12 W11 W15 AC12 AA14 Y18 AB11 AB15 AB17 AB19 AE20 AB21 K11 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8 VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2 1 2 AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15 RS780M_FCBGA528 AE10 AA11 Y11 AD10 AB10 AC10 H11 H12 +3VS 1 RS780M_FCBGA528 C431 1U_0402_6.3V4Z @ 1 L3 330U_D2E_2.5VM 2 1 C130 AE25 AD24 AC23 AB22 AA21 Y20 W19 V18 U17 T17 R17 P17 M17 C32 330U_D2E_2.5VM 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX 2 20.1U_0402_16V4Z 0.1U_0402_16V4Z C29 +1.8VS 2A 1 1 PART 6/6 C95 0.1U_0402_16V4Z 1 C96 2 2 U25D 0.1U_0402_16V4Z PAR 4 OF 6 AB12 AE16 V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14 Y14 MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC) AD16 AE17 AD17 MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC) W12 Y12 AD18 AB13 AB18 V14 MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC) V15 W14 MEM_CKP(NC) MEM_CKN(NC) AE12 AD12 SBD_MEM/DVO_I/F 1 C73 C82 C38 1 330U_D2E_2.5VM 2 VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7 C36 L21 +1.2V_HT H18 G19 F20 E21 D22 B23 A23 22U_0805_6.3V6M 2 0.1U_0402_16V4Z 2 2 2 2 C103 C139 2 2 2 2 22U_0805_6.3V6M 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 1 1 1 0.1U_0402_16V4Z C147 0.68A 1 22U_0805_6.3V6M C127 1 C97 C131 1 C110 C150 1 C74 C85 C81 C86 0.1U_0402_16V4Z 1 +1.1VS 22U_0805_6.3V6M 22U_0805_6.3V6M C35 C34 1.1A C112 2A 2 0_0805_5% +VDDA11PCIE A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9 0.1U_0402_16V4Z 1 FBMA-L11-201209-221LMA30T_0805 PART 5/6 VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8 VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z +VDDHTRX 0.1U_0402_16V4Z VDDHT_1 VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7 C94 L25 J17 K16 L16 M16 P16 R16 T16 1 L5 VDDA_12=2.5A U25E 2 0.1U_0402_16V4Z C104 2 2 2 0.1U_0402_16V4Z C102 1 C114 0.1U_0402_16V4Z 1 C121 0.1U_0402_16V4Z 2 22U_0805_6.3V6M 1 C117 C107 1 C116 0.1U_0402_16V4Z 1 C109 C101 FBMA-L11-201209-221LMA30T_0805 0.68A VSSAHT1 VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27 GROUND 0.1U_0402_16V4Z +VDDHT 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z L16 2A +1.1VS POWER 1 A25 D23 E22 G22 G24 G25 H19 J22 L17 L22 L24 L25 M20 N22 P20 R19 R22 R24 R25 H20 U22 V19 W22 W24 W25 Y21 AD25 MEM_COMPP(NC) MEM_COMPN(NC) MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC) MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC) MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC) MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC) MEM_DQ12(NC) MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC) AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21 MEM_DQS0P/DVO_IDCKP(NC) MEM_DQS0N/DVO_IDCKN(NC) MEM_DQS1P(NC) MEM_DQS1N(NC) Y17 W18 AD20 AE21 MEM_DM0(NC) MEM_DM1/DVO_D8(NC) W17 AE19 IOPLLVDD18(NC) IOPLLVDD(NC) AE23 AE24 IOPLLVSS(NC) AD23 MEM_VREF(NC) AE18 3 +1.8VS +1.1VS RS780M_FCBGA528 4 4 Compal Secret Data Security Classification 2008/11/03 Issued Date 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. RS780 PWR/GND Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Sheet Tuesday, February 03, 2009 E 12 of 46 A B C D E DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb 2 R46 2 R45 <11,18> GMCH_CRT_VSYNC 1 @ 1 3K_0402_5% 1 3K_0402_5% Enables the Test Debug Bus using GPIO. (VSYNC) 1 : Disable (RS780) 0 : Enable (Rs780) +3VS 1 DFT_GPIO1: LOAD_EEPROM_STRAPS 1 2 @ R320 150_0402_1% D17 @ CH751H-40_SC76 2 1 <11> AUX_CAL RS780 DFT_GPIO1 <11> SUS_STAT_R# Selects Loading of STRAPS from EPROM 1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected RS740/RX780: DFT_GPIO1 RS780:SUS_STAT PLT_RST# <11,19,26,28,30> 2 2 RS780 use HSYNC to enable SIDE PORT RS780 use HSYNC to enable SIDE PORT 2 R340 @ 2 R339 <11,18> GMCH_CRT_HSYNC 1 3K_0402_5% 1 3K_0402_5% +3VS RS740/RS780: Enables Side port memory ( RS780 use HSYNC#) 0. Enable (RS780) 1 : Disable(RS780) 3 3 4 4 Compal Secret Data Security Classification 2008/11/03 Issued Date 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. RS780 STRAPS Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Sheet Tuesday, February 03, 2009 E 13 of 46 5 4 3 +MXM_B+ PCIE_MTX_C_GRX_N[0..15] PCIE_GTX_C_MRX_N[0..15] I2CC_SDA I2CC_SCL <16> I2CC_SDA <16> I2CC_SCL LVDS DDC Module have 4.7K Pull-UP PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_P1 B PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P11 A PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P12 1 2 C183 VGA@ 0.1U_0402_16V4Z JMXM2B PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P14 +5VS PCIE_GTX_C_MRX_N15 PCIE_GTX_C_MRX_P15 C912 @ 0.1U_0402_16V4Z 1 CLK_PCIE_VGA# CLK_PCIE_VGA <15> CLK_PCIE_VGA# <15> CLK_PCIE_VGA 2 VGA_TZCLKVGA_TZCLK+ <16> VGA_TZCLK<16> VGA_TZCLK+ VGA_PRSNT_R VGA_WAKE# VGA_PWRGD VGA_ON VGA_PRSNT_R <21> VGA_PWRGD <30> VGA_ON <32> <16> VGA_TZOUT2<16> VGA_TZOUT2+ VGA_PWRGD/TH_OVERT# Connect to EC AC_BATT# TH_OVERT# R291 1 0_0402_5% 2 VGA@ VGA_TZOUT2VGA_TZOUT2+ VGA_TZOUT1VGA_TZOUT1+ <16> VGA_TZOUT1<16> VGA_TZOUT1+ TH_OVERT# <30> +3VS VGA_TZOUT0VGA_TZOUT0+ <16> VGA_TZOUT0<16> VGA_TZOUT0+ +3VS +3VS D_EC_SMB_DA1 D_EC_SMB_CK1 1 VGA_HDMI_CEC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC E2 PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC GND GND GND GND GND E4 GND GND GND GND GND PRSNT_R# WAKE# PWR_GOOD PWR_EN RSVD RSVD RSVD RSVD PWR_LEVEL TH_OVERT# TH_ALERT# TH_PWM GPIO0 GPIO1 GPIO2 SMB_DAT SMB_CLK GND OEM OEM OEM OEM GND PEX_TX15# PEX_TX15 GND PEX_TX14# PEX_TX14 GND PEX_TX13# PEX_TX13 GND PEX_TX12# PEX_TX12 GND PEX_TX11# PEX_TX11 GND PEX_TX10# PEX_TX10 GND PEX_TX9# PEX_TX9 GND PEX_TX8# PEX_TX8 GND PEX_TX7# PEX_TX7 GND PEX_TX6# PEX_TX6 GND PEX_TX5# PEX_TX5 GND PEX_TX4# PEX_TX4 GND PEX_TX3# PEX_TX3 GND 1 C399 VGA@ 10U_0805_6.3V6M 2 D +MXM_B+ 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 C418 VGA@ 4.7U_0805_10V4Z 10K_0402_5% 10K_0402_5% 10K_0402_5% (Reserved) 10K_0402_5% (Reserved) 10K_0402_5% (Reserved) R322 @ 4.7K_0402_5% SYSTEM 2 VGA_DISABLE# ENVDD <16> ENVDD <11,30> ENBKL <16> VGA_PNL_PWM 2 2 2 2 2 <6,30,38> EC_SMB_DA1 1 3 Q69 2N7002_SOT23 VGA@ PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P3 D_EC_SMB_DA1 +3VS 1 R305 0_0402_5% 1 @ 2 VGA@ VGA@ @ @ @ R336 @ 4.7K_0402_5% 2 100mil(2.5A, 5VIA) PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC E1 PWR_SRC PWR_SRC PWR_SRC PWR_SRC GND GND GND GND GND E3 GND GND GND GND GND 5V 5V 5V 5V 5V GND GND GND GND PEX_STD_SW# VGA_DISABLE# PNL_PWR_EN PNL_BL_EN PNL_BL_PWM HDMI_CEC DVI_HPD LVDS_DDC_DAT LVDS_DDC_CLK GND OEM OEM OEM OEM GND PEX_RX15# PEX_RX15 GND PEX_RX14# PEX_RX14 GND PEX_RX13# PEX_RX13 GND PEX_RX12# PEX_RX12 GND PEX_RX11# PEX_RX11 GND PEX_RX10# PEX_RX10 GND PEX_RX9# PEX_RX9 GND PEX_RX8# PEX_RX8 GND PEX_RX7# PEX_RX7 GND PEX_RX6# PEX_RX6 GND PEX_RX5# PEX_RX5 GND PEX_RX4# PEX_RX4 GND PEX_RX3# PEX_RX3 GND R1141 R96 1 R1281 R97 1 R1421 2 G +5VS C TH_OVERT# VGA_PWRGD VGA_HDMI_CEC VGA_DISABLE# VGA_WAKE# JMXM2A 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 2 +3VS <6,30,38> EC_SMB_CK1 1 3 S +MXM_B+ 1 Increase the rise time Ps. Module have 4.7K Pull-UP 1 0.1U_0603_25V7K EC_ACIN <30> R292 0_0402_5% @ 1 VGA@ 2 4.3K_0402_5% 1 VGA@ 2 4.3K_0402_5% VGA@ +3VS D27 VGA@ CH751H-40PT_SOD323-2 2 1 R23 R22 <16> I2CC_SDA <16> I2CC_SCL 2 2 G 2 1 C910 C911 VGA@ VGA@ 680P_0603_50V7K 68P_0402_50V8J 2 2 VGA@1 R245 1K_0402_5% 1 2 AC_BATT# 1 +5VS +3VS B+ VGA@1 C909 2 L74 FBMA-L11-201209-221LMA30T_0805 PCIE_GTX_C_MRX_P[0..15] <10> PCIE_GTX_C_MRX_P[0..15] 160mil(4A) D <10> PCIE_GTX_C_MRX_N[0..15] D L75 1 2 FBMA-L11-201209-221LMA30T_0805 S PCIE_MTX_C_GRX_P[0..15] <10> PCIE_MTX_C_GRX_P[0..15] VGA@ 160mil(4A) 1 +3VS D <10> PCIE_MTX_C_GRX_N[0..15] 2 D_EC_SMB_CK1 Q70 2N7002_SOT23 VGA@ PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_P5 <17> HDMI_TX2-_VGA <17> HDMI_TX2+_VGA PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P6 <17> HDMI_TX1-_VGA <17> HDMI_TX1+_VGA PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P7 <17> HDMI_TX0-_VGA <17> HDMI_TX0+_VGA PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_P8 <17> HDMI_CLK-_VGA <17> HDMI_CLK+_VGA PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P9 <17> VGA_HDMI_SDATA <17> VGA_HDMI_SCLK <21> VGA_PRSNT_L PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P10 HDMI_TX2-_VGA HDMI_TX2+_VGA HDMI_TX1-_VGA HDMI_TX1+_VGA HDMI_TX0-_VGA HDMI_TX0+_VGA HDMI_CLK-_VGA HDMI_CLK+_VGA VGA_HDMI_SDATA VGA_HDMI_SCLK VGA_PRSNT_L (Pull-UP 10K at PCH) PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_P11 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231 233 235 237 239 241 243 245 247 249 251 253 255 257 259 261 263 265 267 269 271 273 275 277 279 281 283 285 287 289 291 293 295 297 299 301 303 305 307 309 311 313 314 GND GND PEX_RX2# PEX_TX2# PEX_RX2 PEX_TX2 GND GND PEX_RX1# PEX_TX1# PEX_RX1 PEX_TX1 GND GND PEX_RX0# PEX_TX0# PEX_RX0 PEX_TX0 GND GND PEX_REFCLK# PEX_CLK_REQ# PEX_REFCLK PEX_RST# GND VGA_DDC_DAT RSVD VGA_DDC_CLK RSVD VGA_VSYNC RSVD VGA_HSYNC RSVD GND RSVD VGA_RED LVDS_UCLK# VGA_GREEN LVDS_UCLK VGA_BLUE GND GND LVDS_UTX3# LVDS_LCLK# LVDS_UTX3 LVDS_LCLK GND GND LVDS_UTX2# LVDS_LTX3# LVDS_UTX2 LVDS_LTX3 GND GND LVDS_UTX1# LVDS_LTX2# LVDS_UTX1 LVDS_LTX2 GND GND LVDS_UTX0# LVDS_LTX1# LVDS_UTX0 LVDS_LTX1 GND GND DP_C_L0# LVDS_LTX0# DP_C_L0 LVDS_LTX0 GND GND DP_C_L1# DP_D_L0# DP_C_L1 DP_D_L0 GND GND DP_C_L2# DP_D_L1# DP_C_L2 DP_D_L1 GND GND DP_C_L3# DP_D_L2# DP_C_L3 DP_D_L2 GND GND DP_C_AUX# DP_D_L3# DP_C_AUX DP_D_L3 RSVD GND RSVD DP_D_AUX# RSVD DP_D_AUX RSVD DP_C_HPD RSVD DP_D_HPD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GND RSVD DP_B_L0# RSVD DP_B_L0 RSVD GND GND DP_B_L1# DP_A_L0# DP_B_L1 DP_A_L0 GND GND DP_B_L2# DP_A_L1# DP_B_L2 DP_A_L1 GND GND DP_B_L3# DP_A_L2# DP_B_L3 DP_A_L2 GND GND DP_B_AUX# DP_A_L3# DP_B_AUX DP_A_L3 DP_B_HPD GND DP_A_HPD DP_A_AUX# 3V3 DP_A_AUX 3V3 PRSNT_L# 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262 264 266 268 270 272 274 276 278 280 282 284 286 288 290 292 294 296 298 300 302 304 306 308 310 312 315 GND 316 GND PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N15 PCIE_MTX_C_GRX_P15 VGA_RST# VGA_DDC_DATA VGA_DDC_CLK VGA_CRT_VSYNC VGA_CRT_HSYNC VGA_RST# <19> VGA_DDC_DATA <18> VGA_DDC_CLK <18> VGA_CRT_VSYNC <18> VGA_CRT_HSYNC <18> VGA_CRT_R VGA_CRT_G VGA_CRT_B VGA_CRT_R <18> VGA_CRT_G <18> VGA_CRT_B <18> VGA_TXCLKVGA_TXCLK+ VGA_TXCLK- <16> VGA_TXCLK+ <16> VGA_TXOUT2VGA_TXOUT2+ C VGA_TXOUT2- <16> VGA_TXOUT2+ <16> VGA_TXOUT1VGA_TXOUT1+ VGA_TXOUT1- <16> VGA_TXOUT1+ <16> VGA_TXOUT0VGA_TXOUT0+ VGA_TXOUT0- <16> VGA_TXOUT0+ <16> B VGA_HPD VGA_HPD <17> +3VS 40mil(1A) JAE_MM70-314-310B1-1 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P12 A JAE_MM70-314-310B1-1 Compal Electronics, Inc. Compal Secret Data Security Classification 2008/11/03 Issued Date Deciphered Date 2009/11/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title MXM Connector Size B Date: Document Number Rev 0.3 KBYF0 LA-5051P Tuesday, February 03, 2009 Sheet 1 14 of 46 5 4 3 2 1 +3VS_CLK R230 1 2 +3VS FBMA-L11-201209-601LMT10805 C348 +VDDCLK_IO +1.2V_HT 2 1 C324 0.1U_0402_16V4Z 1 C344 22U_0805_10V4Z 2 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 1 C363 1 C364 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 C319 C339 2 0.1U_0402_16V4Z 2 1 C326 0.1U_0402_16V4Z 1 C325 2 0.1U_0402_16V4Z 1 2 1 C362 2 0.1U_0402_16V4Z 2 C350 1U_0402_6.3V4Z R192 1 0.1U_0402_16V4Z 1 C316 2 FBMA-L11-201209-601LMT 0805 1 C313 1 0.1U_0402_16V4Z 1 C365 0.1U_0402_16V4Z 1 C323 1 C361 C346 0.1U_0402_16V4Z 1 C322 1U CLOSE PIN 69 D D 2 2 22U_0805_10V4Z 2 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 2 2 R190 +CLK_VDDA FBMA-L11-201209-601LMT 0805 CLK_XTAL_OUT 22U_0805_10V4Z 1 1 C311 2 2 U20 C321 0.1U_0402_16V4Z CLK_XTAL_IN NEW CARD SRC 2 MINI2 SRC 3 MINI1 +3VS_CLK 1 2 LAN SRC 1 R197 8.2K_0402_5% ICS 9LPRS488 49 48 VDDA GNDA 62 66 VDDREF GNDREF 12 18 28 37 53 VDDSRC_IO VDDSRC_IO VDDATIG_IO VDDSB_SRC_IO VDDCPU_IO 3 17 29 38 44 54 61 69 VDDDOT VDDSRC VDDATIG VDDSB_SRC VDDSATA VDDCPU VDDHTT VDD48 1 2 ICH_SMBCLK0 ICH_SMBDATA0 SB_SRC_SLOW# 41 SRC_SLOW CPUKG0T_LPRS CPUKG0C_LPRS 56 55 CLK_CPU CLK_CPU# HTT0T_LPRS / 66 M HTT0C_LPRS / 66 M 60 59 CLK_HTT CLK_HTT# SB_SRC0T_LPRS SB_SRC0C_LPRS 40 39 SB_SRC1T_LPRS SB_SRC1C_LPRS 35 34 ATIG0T_LPRS ATIG0C_LPRS 33 32 CLK_ATIG0 CLK_ATIG0# 1 R223 1 R226 ATIG1T_LPRS ATIG1C_LPRS 31 30 CLK_ATIG1 CLK_ATIG1# 1 VGA@ 2 R227 1 2 0_0402_5% R229VGA@ 0_0402_5% CLK_PCIE_VGA CLK_PCIE_VGA# ATIG2T_LPRS ATIG2C_LPRS 26 25 SRC0T_LPRS SRC0C_LPRS 23 22 CLK_SRC0 CLK_SRC0# 1 R239 1 R240 2 2 0_0402_5% 0_0402_5% CLK_PCIE_LAN CLK_PCIE_LAN# SRC1T_LPRS SRC1C_LPRS 21 20 SRC2T_LPRS SRC2C_LPRS 16 15 CLK_SRC2 CLK_SRC2# 1 R256 1 R255 2 2 0_0402_5% 0_0402_5% CLK_PCIE_MINI1 CLK_PCIE_MINI1# SRC3T_LPRS SRC3C_LPRS 14 13 CLK_SRC3 CLK_SRC3# 1 R263 1 R262 2 2 0_0402_5% 0_0402_5% CLK_PCIE_MINI2 CLK_PCIE_MINI2# SRC4T_LPRS SRC4C_LPRS 10 9 CLK_SB_SRC0 CLK_SB_SRC0# 1 R199 1 R200 2 2 0_0402_5% 0_0402_5% CLK_SBLINK_BCLK CLK_SBLINK_BCLK# SRC5T_LPRS SRC5C_LPRS 8 7 CLK_SB_SRC1 CLK_SB_SRC1# 1 R213 1 R218 2 2 0_0402_5% 0_0402_5% CLK_SBSRC_BCLK CLK_SBSRC_BCLK# SMBCLK SMBDAT ICH_SMBCLK0 <8,9,20,28> ICH_SMBDATA0 <8,9,20,28> 2 1 +3VS_CLK SRC 0 2 22P_0402_50V8J +3VS_CLK R205 8.2K_0402_5% 1 2 C REQ0# FOR SRC1 REQ2# FOR SRC2 <28> MINI1_CLKREQ# REQ3# FOR SRC3 <28> MINI2_CLKREQ# <19> SB_14M_OSC R503 1 2 FBMA-L11-160808-601LMT 0603 24 MINI2_CLKREQ# <11> NB_OSC_14.318M <30> CLK_14M_SIO +3VS_CLK MINI1_CLKREQ# 1 R231 B @ CLK_14M_SIO SB_14M_OSC External 14MHz CLK for SB710 <25> CLK_SD_48M <20> CLK_48M_USB CLKREQ1# 50 CLKREQ2# 43 CLKREQ3# 42 CLKREQ4# 2 100_0402_5% NB_OSC_14.318M 2 1 R522 33_0402_5% 2 1 R251 33_0402_5% @ 2SEL_27 200_0402_1% 1 R232 SEL_SATA SEL_HT66 63 REF2/SEL_27 64 REF1/SEL_SATA 65 REF0/SEL_HTT66 1 R225 1 R222 2 2 0_0402_5% 0_0402_5% 2 2 0_0402_5% 0_0402_5% 1 R214 261_0402_1% CLK_CPU_BCLK <6> CPU CLK_CPU_BCLK# R210 8.2K_0402_5% @ CLK_CPU_BCLK# <6> CLK_NBHT CLK_NBHT# CLK_NBHT <11> CLK_NBHT# <11> C CLKREQ0 # 51 1 R215 1 R206 CLK_CPU_BCLK 2 1 22P_0402_50V8J 2 1 0.1U_0402_16V4Z +VDDCLK_IO R201 8.2K_0402_5% 1 2 C368 2 C343 1 14.31818MHZ_20P_6X1430004201 1 C360 2 2 1 SRC_SLOW +3VS_CLK Y4 2 2 0_0402_5% 0_0402_5% CLK_NBGFX CLK_NBGFX# CLK_NBGFX <11> CLK_NBGFX# <11> NB GFX CLK_PCIE_VGA <14> CLK_PCIE_VGA# <14> VGA chip(Dis) CLK_PCIE_LAN <26> CLK_PCIE_LAN# <26> GLAN CLK_PCIE_MINI1 <28> CLK_PCIE_MINI1# <28> MiniCard_1 B CLK_SD_48M R244 CLK_48M_USB R243 CLK_SD_48M_R 71 48MHz_0 70 48MHz_1 CLK_XTAL_IN 67 X1 CLK_XTAL_OUT 68 X2 6 11 19 27 36 47 52 58 72 73 GNDDOT GNDSRC GNDSRC GNDATIG GNDSB_SRC GNDSATA GNDCPU GNDHTT GND48 GNDPAD 2 1 33_0402_5% 2 1 CLK_48M_USB_R 33_0402_5% CLK_PCIE_MINI2 <28> CLK_PCIE_MINI2# <28> MiniCard_2 CLK_SBLINK_BCLK <11> CLK_SBLINK_BCLK# <11> NB A LINK CLK_SBSRC_BCLK <19> CLK_SBSRC_BCLK# <19> SB RCLK R234 8.2K_0402_5% 2 2 +3VS_CLK R237 @ @ NB CLOCK INPUT TABLE NB CLOCKS PD# 57 2 R220 ICS9LPRS488AKLFT_MLF72_10x10 1 2 2 1 8.2K_0402_5% +3VS_CLK RS740 RS780 NC 100M DIFF 100M DIFF 100M DIFF 100M DIFF REFCLK_N 14M SE (3.3V) NC 14M SE (1.8V) NC 14M SE (1.1V) vref GFX_REFCLK 100M DIFF 100M DIFF 100M DIFF(IN/OUT)* GPP_REFCLK NC 100M DIFF NC 100M DIFF 100M DIFF HT_REFCLKN C669 @ REFCLK_P 2 R238 8.2K_0402_5% RX780 HT_REFCLKP 1U_0603_10V6K A 1 R235 8.2K_0402_5% 1 5 4 66M SE(SINGLE END) SEL_SATA SEL_HT66 A SRC7T_LPRS/27MHz_SS SRC7C_LPRS/27MHz_NS 46 45 1 1 8.2K_0402_5% SRC6T/SATAT_LPRS SRC6C/SATAC_LPRS GPPSB_REFCLK 100M DIFF 1 configure as single-ended 66MHz output 0* configure as differential 100MHz output 1 configure as 27M and 27M_SS output 0* configure as SRC_7 output NB_OSC_14.318M SEL_HTT66 1* 100M SATA SRC6 output 0 SPREAD 100M SATA SRC6 output 2008/11/03 Issued Date 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SEL_SATA * default 5 Compal Secret Data Security Classification 4 3 2 Title Compal Electronics, Inc. Clock generator Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Sheet Tuesday, February 03, 2009 1 15 of 46 4 3 2 TXOUT0+ TXOUT0- 1 2 RP31 1 2 RP30 1 2 RP29 1 2 RP28 2 1 RP27 2 1 RP26 2 1 RP25 2 1 RP24 VGA_TXOUT0+ 4 VGA_TXOUT03 VGA@ 0_0404_4P2R_5% VGA_TXOUT1+ 4 VGA_TXOUT13 VGA@ 0_0404_4P2R_5% VGA_TXOUT2+ 4 VGA_TXOUT23 VGA@ 0_0404_4P2R_5% VGA_TXCLK+ 4 VGA_TXCLK3 VGA@ 0_0404_4P2R_5% VGA_TZOUT0+ 3 VGA_TZOUT04 VGA@ 0_0404_4P2R_5% VGA_TZOUT1+ 3 VGA_TZOUT14 VGA@ 0_0404_4P2R_5% VGA_TZOUT2+ 3 VGA_TZOUT24 VGA@ 0_0404_4P2R_5% VGA_TZCLK+ 3 VGA_TZCLK4 VGA@ 0_0404_4P2R_5% I2CC_SCL I2CC_SDA 1 2 RP13 GMCH_LCD_CLK 4 GMCH_LCD_DATA 3 UMA@ 0_0404_4P2R_5% +3VS TXOUT0TXOUT0+ TXOUT1TXOUT1+ 1 2 RP1 1 2 RP2 1 2 RP3 1 2 RP4 2 1 RP5 2 1 RP6 2 1 RP7 2 1 RP8 GMCH_TXOUT04 GMCH_TXOUT0+ 3 UMA@ 0_0404_4P2R_5% GMCH_TXOUT14 GMCH_TXOUT1+ 3 UMA@ 0_0404_4P2R_5% GMCH_TXOUT24 GMCH_TXOUT2+ 3 UMA@ 0_0404_4P2R_5% GMCH_TXCLK4 GMCH_TXCLK+ 3 UMA@ 0_0404_4P2R_5% GMCH_TZOUT03 GMCH_TZOUT0+ 4 UMA@ 0_0404_4P2R_5% GMCH_TZOUT13 GMCH_TZOUT1+ 4 UMA@ 0_0404_4P2R_5% GMCH_TZOUT23 GMCH_TZOUT2+ 4 UMA@ 0_0404_4P2R_5% GMCH_TZCLK3 GMCH_TZCLK+ 4 UMA@ 0_0404_4P2R_5% LCD POWER CIRCUIT +LCDVDD TXOUT1+ TXOUT1- +3VS 1 +3VALW W=60mils TXOUT2+ TXOUT2- 1 R5 300_0603_5% 1 2 R9 100K_0402_5% 6 D TXCLK+ TXCLK- C2 TZOUT0+ TZOUT0- 4.7U_0805_10V4Z 1 0.047U_0402_16V7K 2N7002DW-T/R7_SOT363-6 2 Q2B 5 TZOUT2+ TZOUT2- +LCDVDD W=60mils 1 1 C5 4.7U_0805_10V4Z 2 2 TZCLK+ TZCLK- R8 @ 4.7K_0402_5% C BKOFF# <11,30> BKOFF# 2 0_0402_5% D2 2 RB751V_SOD323 1 C11 INVT_PWM 2 R612 1 DAC_BRIG C9 DISPOFF# DISPOFF# C8 1 2 1 2 1 2 TXOUT2TXOUT2+ 220P_0402_50V7K TXCLKTXCLK+ 220P_0402_50V7K 220P_0402_50V7K TZOUT0TZOUT0+ TZOUT1TZOUT1+ R610 1 @ <11> UMA_PNL_PWM 1 @ R611 2 0_0402_5% INVT_PWM 2 0_0402_5% INVT_PWM VGA_TXOUT1+ <14> VGA_TXOUT1- <14> VGA_TXOUT2+ <14> VGA_TXOUT2- <14> VGA_TXCLK+ <14> VGA_TXCLK- <14> D VGA_TZOUT0+ <14> VGA_TZOUT0- <14> VGA_TZOUT1+ <14> VGA_TZOUT1- <14> VGA_TZOUT2+ <14> VGA_TZOUT2- <14> VGA_TZCLK+ <14> VGA_TZCLK- <14> 0.1U_0402_16V4Z @ <14> VGA_PNL_PWM VGA_TXOUT0+ <14> VGA_TXOUT0- <14> C6 2 R7 VGA@ 100K_0402_5% TZOUT1+ TZOUT1- AO3413_SOT23-3 Q1 2 4 <14> ENVDD R6 1 UMA@ 2 0_0402_5% R4 1 VGA@ 2 0_0402_5% 1 ENVDD 1 1K_0402_5% 1 C3 3 1 GMCH_ENVDD 2 G R3 D 2 S 3 2 2 2N7002DW-T/R7_SOT363-6 Q2A <11> GMCH_ENVDD 1 1 5 TZOUT2TZOUT2+ TZCLKTZCLK+ GMCH_LCD_CLK <11> GMCH_LCD_DATA <11> GMCH_TXOUT0- <11> GMCH_TXOUT0+ <11> GMCH_TXOUT1- <11> GMCH_TXOUT1+ <11> GMCH_TXOUT2- <11> GMCH_TXOUT2+ <11> GMCH_TXCLK- <11> GMCH_TXCLK+ <11> C GMCH_TZOUT0- <11> GMCH_TZOUT0+ <11> GMCH_TZOUT1- <11> GMCH_TZOUT1+ <11> GMCH_TZOUT2- <11> GMCH_TZOUT2+ <11> GMCH_TZCLK- <11> GMCH_TZCLK+ <11> LCD/PANEL BD. Conn. JLVDS +INVPWR_B+ +3VS <14> I2CC_SCL <14> I2CC_SDA I2CC_SCL I2CC_SDA TZOUT0TZOUT0+ TZOUT1+ TZOUT1TZOUT2+ TZOUT2- B TZCLKTZCLK+ R1 0_0402_5% 1 @ 2 1 @ 2 USB20_N3 USB20_P3 <20> USB20_N3 <20> USB20_P3 USB20_CMOS_N3 USB20_CMOS_P3 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 GND GMD 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 DAC_BRIG INVT_PWM DISPOFF# W=60mils TXOUT0TXOUT0+ TXOUT1TXOUT1+ TXCLKTXCLK+ R574 1 R575 1 ACES_87242-4001-09 CONN@ L22 1 USB20_N3 4 1 4 2 2 USB20_CMOS_P3 3 3 USB20_CMOS_N3 B TXOUT2+ TXOUT2- R2 0_0402_5% USB20_P3 DAC_BRIG <30> INVT_PWM <30> +LCDVDD 2 0_0603_5% 2 0_0603_5% @ +3VS +3VALW 1 C10 2 0.1U_0402_16V4Z WCM2012F2S-900T04_0805 <> +INVPWR_B+ L1 2 1 KC FBM-L11-201209-221LMAT_0805 W=40mils +LCDVDD B+ L2 2 1 KC FBM-L11-201209-221LMAT_0805 C12 A 1 1 1 C4 1 C7 C13 2 680P_0402_50V7K 68P_0402_50V8J 2 2 10U_0805_10V4Z 2 0.1U_0402_16V4Z A 2008/11/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title LVDS & DVI Connector Size B Date: Document Number Rev 0.3 KBYF0 LA-5051P Sheet Tuesday, February 03, 2009 1 16 of 46 5 4 3 2 1 +3VS reserve HDMI I2C ESD diode +5VS 1 R857 2 0_0402_5% 1 R856 2 @ 0_0402_5% DDC to HDMI CONN JHDMI1 HDMI_HPD +3VS +HDMI_5V_OUT 1 VGA_HDMI_SDATA 1 R880 <11> GMCH_DDC_DATA GMCH_DDC_DATA 1 R881 2 UMA@ 0_0402_5% UMA@ VGA_HDMI_SDATA_R 3 3 1 2 2 R87 6.8K_0402_5% HDMI_R_CKHDMI_R_CK+ HDMI_R_D0- HDMI_SCLK HDMI_R_D0+ HDMI_R_D1- BSH111 1N_SOT23-3 Q50 1 HDMI_R_D1+ HDMI_R_D2- HDMI_SDATA S D <14> VGA_HDMI_SDATA 2 0_0402_5% 2 VGA@ 0_0402_5% R879 1 1 2 2 GMCH_DDC_CLK VGA_HDMI_SCLK_R 2 VGA@ 0_0402_5% D <11> GMCH_DDC_CLK 1 R878 S VGA_HDMI_SCLK G <14> VGA_HDMI_SCLK R84 6.8K_0402_5% G 2 R579 4.7K_0402_5% UMA@ 2 R580 4.7K_0402_5% UMA@ D HDMI_SDATA HDMI_SCLK 1 1 +HDMI_5V_OUT HDMI_R_D2+ Place closed to JHDMI1 BSH111 1N_SOT23-3 Q49 +HDMI_5V_OUT D6 HDMI_HPD +5VS 2 F1 1 1 RB491D_SC59-3 2 A 3 2 R850 R851 1 VGA@ 2 0_0402_5% Y 4 R853 1 UMA@ 2 0_0402_5% U39 SN74AHCT1G125GW_SOT353-5 100K_0402_5% VGA_HPD <14> UMA_HPD <11> 1 @ @ HDMI_SCLK 2 0_0402_5% HDMI_SDATA 2 0_0402_5% W=40mils 2 1.1A_6VDC_FUSE C177 0.1U_0402_16V4Z 2 1 2.2K_0402_5% +3VS D 20 21 22 23 1 2 C914 0.1U_0402_16V4Z C 1 1 G C R845 2 5 1 0.1U_0402_16V4Z 2 P OE# C913 HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ SUYIN_100042MR019SX53ZL CONN@ VGA_HDMI_SCLK_R 1 R854 VGA_HDMI_SDATA_R 1 R855 +HDMI_5V_OUT 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HDMI_C_CLK- 1 R382 2 0_0402_5% HDMI_R_CK- L50 1 2 2 4 4 3 3 HDMI_R_CK+R866 1 UMA@ 2 750_0402_1% @ WCM-2012-900T_0805 HDMI_C_CLK+ 1 R383 2 0_0402_5% HDMI_R_CK+ HDMI_C_TX0- 1 R384 2 0_0402_5% HDMI_R_D0- 6 Q46A 2N7002DW-T/R7_SOT363-6 1 HDMI_R_CK- R867 1 UMA@ 2 750_0402_1% 2 1 +5VS L51 2 0.1U_0402_16V7K HDMI_C_CLK+ <14> HDMI_CLK-_VGA C713 VGA@1 2 0.1U_0402_16V7K HDMI_C_CLK- <14> HDMI_TX0+_VGA C714 VGA@1 2 0.1U_0402_16V7K HDMI_C_TX0+ <14> HDMI_TX0-_VGA C715 VGA@1 2 0.1U_0402_16V7K HDMI_C_TX0- <14> HDMI_TX1+_VGA C716 VGA@1 2 0.1U_0402_16V7K HDMI_C_TX1+ <14> HDMI_TX1-_VGA C717 VGA@1 2 0.1U_0402_16V7K HDMI_C_TX1- <14> HDMI_TX2+_VGA C718 VGA@1 2 0.1U_0402_16V7K HDMI_C_TX2+ <14> HDMI_TX2-_VGA C719 VGA@1 2 0.1U_0402_16V7K HDMI_C_TX2- 1 2 4 4 3 3 <10> HDMI_CLK+_UMA <10> HDMI_CLK-_UMA <10> HDMI_TX0+_UMA <10> HDMI_TX0-_UMA <10> HDMI_TX1+_UMA <10> HDMI_TX1-_UMA <10> HDMI_TX2+_UMA <10> HDMI_TX2-_UMA R858 R859 R860 R861 R862 R863 R864 R865 1 1 1 1 1 1 1 UMA@ UMA@ UMA@ UMA@ UMA@ UMA@ UMA@ UMA@ 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% Q46B 2N7002DW-T/R7_SOT363-6 4 HDMI_R_D0- R871 1 UMA@ 2 750_0402_1% +5VS @ WCM-2012-900T_0805 HDMI_C_TX0+ 1 R385 2 0_0402_5% HDMI_R_D0+ HDMI_R_D1+ R872 1 UMA@ 2 750_0402_1% 1 R386 2 0_0402_5% HDMI_R_D1- 1 2 2 4 4 3 3 B +5VS HDMI_R_D2+ R876 1 UMA@ 2 750_0402_1% HDMI_C_TX1+ 1 R387 2 0_0402_5% HDMI_R_D1+ HDMI_C_TX2- 1 R388 2 0_0402_5% HDMI_R_D2- HDMI_C_TX0+ 3 Q47B 2N7002DW-T/R7_SOT363-6 4 HDMI_R_D2- R877 1 UMA@ 2 750_0402_1% HDMI_C_CLK+ HDMI_C_CLK- Q47A 2N7002DW-T/R7_SOT363-6 1 HDMI_R_D1- R874 1 UMA@ 2 750_0402_1% L52 1 6 2 HDMI_C_TX1- @ WCM-2012-900T_0805 1 3 5 C712 VGA@1 2 5 B <14> HDMI_CLK+_VGA HDMI_R_D0+R869 1 UMA@ 2 750_0402_1% 1 +5VS 715-Ω for RS880M R866 R867 R869 R871 499_0402_1% VGA@ 499_0402_1% VGA@ 499_0402_1% VGA@ 499_0402_1% VGA@ L53 HDMI_C_TX0- 1 1 2 2 4 4 3 3 HDMI_C_TX1+ HDMI_C_TX1- @ WCM-2012-900T_0805 HDMI_C_TX2+ HDMI_C_TX2+ HDMI_C_TX2- 1 R390 2 0_0402_5% HDMI_R_D2+ R872 R874 R876 R877 499_0402_1% VGA@ 499_0402_1% VGA@ 499_0402_1% VGA@ 499_0402_1% VGA@ A A 2008/11/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title DVI/HDMI Connector Size Document Number Custom Rev 0.3 KBYF0 LA-5051P Date: Sheet Tuesday, February 03, 2009 1 17 of 46 A B C D E CRT Connector W=40mils +5VS +R_CRT_VCC D18 +CRT_VCC W=40mils F2 2 1 1 RB491D_SC59-3 2 1.1A_6VDC_FUSE 1 C430 0.1U_0402_16V4Z 2 1 1 2 150_0402_1% 1 C129 C108 2 1 2 C133 @ 1 2 C115 @ 1 2 C105 @ 1 2 C83 change to 47pf for ATI M66/M7x +CRT_VCC 2 R13 A 1 L8 2 FCM1608C-121T_0603 C98 1 10K_0402_5% CRT_VSYNC_2 DSUB_12 1 C90 R30 100K_0402_5% 1 @ 2 1 C125 C76 100P_0402_50V8J 100P_0402_50V8J 2 3 SN74AHCT1G125DCKR_SC70-5 1 P 5 2 0.1U_0402_16V4Z 2 2 A 2 +CRT_VCC 2 U4 4D_CRT_VSYNC Y G CRT_VSYNC OE# 1 DSUB_15 1 D_CRT_HSYNC 4 +CRT_VCC C66 16 17 SUYIN_070546FR015S233ZR CONN@ CRT_DET# <20> @ U3 Y 1 2 100P_0402_50V8J G CRT_HSYNC 2 2 CRT_HSYNC_2 FCM1608C-121T_0603 100P_0402_50V8J P 2 1 2 0.1U_0402_16V4Z OE# 1 5 C67 1 L11 G G 2 1 CRT_B_2 1 2 C145 CRT_G_2 2 0_0805_5% 100P_0402_50V8J 1 2 0_0805_5% 1 JCRT1 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 5P_0402_50V8C 2 C100 L15 1 5P_0402_50V8C 1 L20 CRT_B_1 2 FCM2012C-800_0805 CRT_R_2 5P_0402_50V8C C120 CRT_G_1 2 FCM2012C-800_0805 1 5P_0402_50V8C 2 2 150_0402_1% 1 5P_0402_50V8C C140 2 2 R54 5P_0402_50V8C 1 1 1 L13 150_0402_1% 1 2 0_0805_5% 1 6P_0402_50V8D L18 CRT_B R70 L24 6P_0402_50V8D CRT_G R74 CRT_R_1 2 FCM2012C-800_0805 1 L23 6P_0402_50V8D CRT_R 3 SN74AHCT1G125DCKR_SC70-5 <11> GMCH_CRT_B CRT_R R372 0_0402_5% UMA@1 2 CRT_G GMCH_CRT_B R373 0_0402_5% UMA@1 2 CRT_B +CRT_VCC +3VS R366 R36 4.7K_0402_5% VGA@ <14> VGA_CRT_G <14> VGA_CRT_B 2 G 2 CRT_VSYNC VGA_CRT_R R375 10_0402_5% 1 VGA@ 2 VGA_CRT_G R374 10_0402_5% 1 VGA@ 2 CRT_G VGA_CRT_B R376 10_0402_5% 1 VGA@ 2 CRT_B CRT_R 3 33_0402_5% DSUB_15 2 BSH111 1N_SOT23-3 Q52 1 R368 1 R35 1 2 VGA@ 0_0402_5% VGA_DDC_DATA <14> 1 2 VGA@ 0_0402_5% VGA_DDC_CLK <14> 2 G 1 S R369 1 D VGA@ DSUB_12 2 CRT_HSYNC R326 4.7K_0402_5% VGA@ 3 R27 S <14> VGA_CRT_R R379 0_0402_5% VGA@1 VGA_CRT_HSYNC 2 D <14> VGA_CRT_HSYNC R380 0_0402_5% VGA@1 2 2 6.8K_0402_5% VGA_CRT_VSYNC 3 +3VS R367 6.8K_0402_5% <14> VGA_CRT_VSYNC check with MXM board Place closed to chipset 1 GMCH_CRT_G 2 <11> GMCH_CRT_G CRT_HSYNC 1 3 CRT_VSYNC 2 <11> GMCH_CRT_R R378 GMCH_CRT_HSYNC 2 UMA@ 1 0_0402_5% R371 0_0402_5% GMCH_CRT_R UMA@1 2 1 <11,13> GMCH_CRT_HSYNC R381 0_0402_5% GMCH_CRT_VSYNC 2 UMA@ 1 1 <11,13> GMCH_CRT_VSYNC 33_0402_5% VGA@ BSH111 1N_SOT23-3 Q53 public board write w/o PH Place closed to chipset R17 R18 1 UMA@ 2 GMCH_CRT_DATA 0_0402_5% GMCH_CRT_DATA <11> 1 UMA@ 2 GMCH_CRT_CLK 0_0402_5% GMCH_CRT_CLK <11> 4 4 2008/11/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title CRT Connector Size B Date: Document Number Rev 0.3 KBYF0 LA-5051P Sheet Tuesday, February 03, 2009 E 18 of 46 A B 1 R154 C D E 2 A_RST# @ 8.2K_0402_5% U10A SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N C275 C278 C287 C279 C272 C274 C266 C267 Y A PCIE_PVDD P25 2 PCIE_PVSS +3VALW C298 5 B U13 Y A VGA_RST# 4 VGA_RST# <14> NC7SZ08P5X_NL_SC70-5 3 1 2 R185 @ 1 33_0402_5% External 14MHz CLK for SB710 NB_HT_CLKP NB_HT_CLKN P17 M18 CPU_HT_CLKP CPU_HT_CLKN M23 M22 SLT_GFX_CLKP SLT_GFX_CLKN <15> SB_14M_OSC 20M_0402_5% 2 SB_14M_OSC J19 J18 GPP_CLK0P GPP_CLK0N L20 L19 GPP_CLK1P GPP_CLK1N M19 M20 GPP_CLK2P GPP_CLK2N N22 P22 GPP_CLK3P GPP_CLK3N L18 25M_48M_66M_OSC J21 25M_X1 C192 SB_32KHI 2 25M_X2 LPCCLK0 LPCCLK1 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ0# LDRQ1#/GNT5#/GPIO68 BMREQ#/REQ5#/GPIO65 SERIRQ G22 E22 H24 H23 J25 J24 H25 H22 AB8 AD7 V15 <23> <23> <23> <23> 1 +1.8VS +3VS R394 4.7K_0402_5% H_PWRGD 3 1 H_PWRGD_L FDV301N_NL_SOT23-3 H_PWRGD_L <44> Q35 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PAD T12 @ PAD T13 @ PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 2 <23> <23> <23> <23> <23> <23> @ PAD T11 @ PAD T18 1 2 R180 0_0402_5% PM_CLKRUN# <30> 3 1 IN NC 2 SB_32KHI A3 X1 32.768KHZ_12.5P_MC-306 B3 <11> ALLOW_LDTSTOP <6> H_PROCHOT# <6> H_PWRGD <6,11> LDT_STOP# <6> LDT_RST# ALLOW_LDTSTOP H_PROCHOT# H_PWRGD LDT_STOP# LDT_RST# F23 F24 F22 G25 G24 ALLOW_LDTSTP PROCHOT# LDT_PG LDT_STP# LDT_RST# RTCCLK INTRUDER_ALERT# VBAT CLK_PCI_EC LPCCLK1 LPC_DRQ1# LPC_DRQ1# <30> SERIRQ SERIRQ <30> 0.1U_0402_16V4Z C289 1 STRAP PIN RTC_CLK <23> +RTCVCC 2008/11/03 2 1 R184 1 C293 2 2 510_0402_5% W=20mils 2 R178 1 1K_0402_5% J1 C297 1 @ 0_0603_5% for Clear CMOS 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C +RTCBATT 2 Compal Secret Data Security Classification B STRAP PIN D10 4 A CLK_PCI_EC <23,30> LPCCLK1 <23,30> EC & Debug +RTCVCC +RTCVCC_R 218S7EALA11FG_BGA528_SB700 Issued Date 2 22_0402_5% LPC_AD0 <30> LPC_AD1 <30> LPC_AD2 <30> LPC_AD3 <30> LPC_FRAME# <30> RTC_CLK @ 1 2 R127 1M_0402_5% C3 C2 B2 RTC Change Capacitors to correct RTC timeing X2 L PC SB_32KHO Close to SB CPU SB_32KHO 2 12P_0402_50V8J R120 1 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# D Title 3 0.1U_0402_16V4Z NC 2 OUT 3 1 4 RTC XTAL 1 2 R85 20M_0603_5% C212 J20 X2 PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 1 1 12P_0402_50V8J PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 1U_0402_6.3V4Z @ R83 1 NB_DISP_CLKP NB_DISP_CLKN M24 M25 P 0.1U_0402_16V4Z 2 A_RST# PCIE_RCLKP/NB_LNK_CLKP PCIE_RCLKN/NB_LNK_CLKN K23 K22 1 G 2 N25 N24 PCI INTERFACE <15> CLK_SBSRC_BCLK <15> CLK_SBSRC_BCLK# 1 33_0402_5% @ N1 AD3 AC4 AE2 AE3 PLT_RST# <11,13,26,28,30> NC7SZ08P5X_NL_SC70-5 CLK_SBSRC_BCLK CLK_SBSRC_BCLK# PCIRST# INTE#/GPIO33 INTF#/GPIO34 INTG#/GPIO35 INTH#/GPIO36 Close to SB PLT_RST# 4 P4 P3 P1 P2 T4 T3 U2 P7 V4 T1 V3 U1 V1 V2 T2 W1 T9 R6 R7 R5 U8 U5 Y7 W8 V9 Y8 AA8 Y4 Y3 Y2 AA2 AB4 AA1 AB3 AB2 AC1 AC2 AD1 W2 U7 AA7 Y1 AA6 W5 AA5 Y5 U6 W6 W4 V7 AC3 AD4 AB7 AE6 AB6 AD2 AE4 AD5 AC6 AE5 AD6 V5 CLOCK GENERATOR 2 R179 3 P24 1 C524 1U_0402_6.3V4Z PCIE_CALRP PCIE_CALRN PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5/GPIO41 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CBE0# CBE1# CBE2# CBE3# FRAME# DEVSEL# IRDY# TRDY# PAR STOP# PERR# SERR# REQ0# REQ1# REQ2# REQ3#/GPIO70 REQ4#/GPIO71 GNT0# GNT1# GNT2# GNT3#/GPIO72 GNT4#/GPIO73 CLKRUN# LOCK# 3 2 2 PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N 562_0402_1% T25 2.05K_0402_1% T24 +SB_PCIEVDD 1 U22 U21 U19 V19 R20 R21 R18 R17 U12 P B G 1 5 1 1 1 Part 1 of 5 PCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N D C523 10U_0805_10V4Z 2 2 SB700 A_RST# V23 V22 V24 V25 U25 U24 T23 T22 S A_RST# R149 R143 L59 1 2 MBC1608121YZF_0603 +3VALW 0.1U_0402_16V4Z 2 SB_RX0P_C SB_RX0N_C SB_RX1P_C SB_RX1N_C SB_RX2P_C SB_RX2N_C SB_RX3P_C SB_RX3N_C G +1.2V_HT 2 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 2 2 2 2 2 2 SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N +PCIE_VDDR C294 1 1 1 1 1 1 1 1 2 <10> <10> <10> <10> <10> <10> <10> <10> SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N 1 SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N 2 <10> <10> <10> <10> <10> <10> <10> <10> PCI CLKS 1 N2 PCI EXPRESS INTERFACE A_RST# 1 4 2 BAS40-04_SOT23-3 +CHGRTC Compal Electronics, Inc. SB700-PCIE/PCI/ACPI/LPC/RTC Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Sheet Tuesday, February 03, 2009 E 19 of 46 A SKU-ID B R509 C POP USB-12 Bluetooth POP SUS_STAT# SB700 has internal PD <30> EC_GA20 <30> EC_KBRST# <30> EC_SCI# <30> EC_SMI# SB_TEST2 2 @ 2.2K_0402_5% 2 @ 2.2K_0402_5% 2 @ 2.2K_0402_5% SB_TEST1 SB_TEST0 <26,28> SB_PCIE_WAKE# <6> H_THERMTRIP# <11> NB_PWRGD EC_RSMRST# <30> EC_RSMRST# 1 R124 2 EC_RSMRST# 2.2K_0402_5% R509 +3VS R510 +3VS 1 2 2.2K_0402_5% ICH_SMBCLK0 R410 1 2 2.2K_0402_5% ICH_SMBDATA0 AE18 AD18 AA19 SKU_ID W17 V17 W20 SB_SPKR W21 ICH_SMBCLK0 AA18 ICH_SMBDATA0 W18 ICH_SMBCLK1 K1 ICH_SMBDATA1 K2 AA20 Y18 C1 Y19 G5 2.2K_0402_5% 2 2.2K_0402_5% 1 UMA@ 2 <33> SB_SPKR <8,9,15,28> ICH_SMBCLK0 <8,9,15,28> ICH_SMBDATA0 <26> ICH_SMBCLK1 <26> ICH_SMBDATA1 2 R413 VGA@ 1 +3VALW R136 R135 1 2 2.2K_0402_5% ICH_SMBDATA1 1 2 10K_0402_5% SB_PCIE_WAKE# R536 1 @ 2 100K_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% EC_LID_OUT# <30> EC_LID_OUT# 1 1 1 1 <32> HDA_SYNC_MDC <33> HDA_SYNC_AUDIO <33> HDA_RST_AUDIO# <32> HDA_RST_MDC# STRAP PIN USB_OC#6 <29> USB_OC#6 EC_LID_OUT# R146 R152 R153 R147 HDA_BITCLK_AUDIO HDA_BITCLK_MDC HDA_SDOUT_MDC HDA_SDOUT_AUDIO <33> HDA_SDIN0 <32> HDA_SDIN1 2 2 2 2 USB_OC#2 USB_OC#1 <24,29> USB_OC#2 <29> USB_OC#1 HDA_BITCLK HDA_SDOUT HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 R144 R150 33_0402_5% 33_0402_5% R145 R151 33_0402_5% 33_0402_5% 1 1 1 1 2 2 HDA_SYNC 2 2 HDARST# E6 E7 USB_FSD12P USB_FSD12N F7 E8 USB_HSD11P USB_HSD11N H11 J10 USB_HSD10P USB_HSD10N E11 F11 USB_HSD9P USB_HSD9N A11 B11 USB_HSD8P USB_HSD8N C10 D10 USB_HSD7P USB_HSD7N G11 H12 USB_HSD6P USB_HSD6N USB_HSD5P USB_HSD5N SATA_IS0#/GPIO10 CLK_REQ3#/SATA_IS1#/GPIO6 SMARTVOLT1/SATA_IS2#/GPIO4 CLK_REQ0#/SATA_IS3#/GPIO0 CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40 SPKR/GPIO2 SCL0/GPOC0# SDA0/GPOC1# SCL1/GPOC2# SDA1/GPOC3# DDC1_SCL/GPIO9 DDC1_SDA/GPIO8 LLB#/GPIO66 SMARTVOLT2/SHUTDOWN#/GPIO5 DDR3_RST#/GEVENT7# B9 B8 A8 A9 E5 F8 E4 USB_OC6#/IR_TX1/GEVENT6# USB_OC5#/IR_TX0/GPM5# USB_OC4#/IR_RX0/GPM4# USB_OC3#/IR_RX1/GPM3# USB_OC2#/GPM2# USB_OC1#/GPM1# USB_OC0#/GPM0# M1 M2 J7 J8 L8 M3 L6 M4 L5 AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO42 AZ_SDIN1/GPIO43 AZ_SDIN2/GPIO44 AZ_SDIN3/GPIO46 AZ_SYNC AZ_RST# AZ_DOCK_RST#/GPM8# @ 1 R130 @ 2 2.2K_0402_5% H19 H20 H21 F25 IMC_GPIO0 IMC_GPIO1 SPI_CS2#/IMC_GPIO2 IDE_RST#/F_RST#/IMC_GPO3 D22 E24 E25 D23 IMC_GPIO4 IMC_GPIO5 IMC_GPIO6 IMC_GPIO7 2 R405 USB20_P12 USB20_N12 USB20_P12 <29> USB20_N12 <29> USB-6 HS-USB USB-5 MiniCard(TV) USB-4 Card Reader USB-3 USB Camera USB20_P8 USB20_N8 USB20_P8 <28> USB20_N8 <28> E12 E14 USB20_P6 USB20_N6 USB20_P6 <29> USB20_N6 <29> C12 D12 USB20_P5 USB20_N5 USB20_P5 <28> USB20_N5 <28> USB_HSD4P USB_HSD4N B12 A12 USB20_P4 USB20_N4 USB20_P4 <25> USB20_N4 <25> USB_HSD3P USB_HSD3N G12 G14 USB20_P3 USB20_N3 USB_HSD2P USB_HSD2N H14 H15 USB20_P2 USB20_N2 USB20_P3 USB20_N3 R50 R51 R52 R53 USB_HSD1P USB_HSD1N A13 B13 USB20_P1 USB20_N1 <16> <16> 1 @ 1 JV70@ 1 JV70@ 1 @ USB20_P1 <29> USB20_N1 <29> USB_HSD0P USB_HSD0N B14 A14 USB20_P0 USB20_N0 USB20_P0 <29> USB20_N0 <29> IMC_GPIO8 IMC_GPIO9 IMC_PWM0/IMC_GPIO10 SCL2/IMC_GPIO11 SDA2/IMC_GPIO12 SCL3_LV/IMC_GPIO13 SDA3_LV/IMC_GPIO14 IMC_PWM1/IMC_GPIO15 IMC_PWM2/IMC_GPO16 IMC_PWM3/IMC_GPO17 A18 B18 F21 D21 F19 E20 E21 E19 D19 E18 IMC_GPIO18 IMC_GPIO19 IMC_GPIO20 IMC_GPIO21 IMC_GPIO22 IMC_GPIO23 IMC_GPIO24 IMC_GPIO25 G20 G21 D25 D24 C25 C24 B25 C23 IMC_GPIO26 IMC_GPIO27 IMC_GPIO28 IMC_GPIO29 IMC_GPIO30 IMC_GPIO31 IMC_GPIO32 IMC_GPIO33 IMC_GPIO34 IMC_GPIO35 IMC_GPIO36 IMC_GPIO37 IMC_GPIO38 IMC_GPIO39 IMC_GPIO40 IMC_GPIO41 B24 B23 A23 C22 A22 B22 B21 A21 D20 C20 A20 B20 B19 A19 D18 C18 USB-2 USB (eSATA) for SJM70 Ext.USB/B for SJV70 CPU_SIC_SB CPU_SID_SB GPIO16 GPIO17 USB-1 Ext.USB/B USB-0 Ext.USB/B 2 2 2 2 USB20_P2_2 USB20_P2_1 USB20_N2_1 USB20_N2_2 USB20_P2_2 USB20_P2_1 USB20_N2_1 USB20_N2_2 <29> <24> <24> <29> CPU_SIC_SB <6> CPU_SID_SB <6> GPIO16 <23> GPIO17 <23> STRAP PIN STRAP PIN 3 2 R406 100K_0402_5% HDA_SDIN1 4 HDA_SDIN2 <18> CRT_DET# 2 Q36G 2N7002_SOT23 CRT_DET D S Compal Secret Data Security Classification 2008/11/03 Issued Date 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 2 High: CRT Plugged 1 HDA_SDIN0 1 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 3 1 R513 @ 1 R514 @ 1 R515 @ USB_RCOMP 1 11.8K_0402_1% CLK_48M_USB <15> 218S7EALA11FG_BGA528_SB700 +3VALW SB Power Domain :S5 INTEGRATED uC +3VS CLK_48M_USB USB-8 MiniCard(WLAN) RSMRST# PAD T14 <23> HDARST# 4 USB_FSD13P USB_FSD13N ICH_SMBCLK1 R134 <33> <32> <32> <33> 3 2 2.2K_0402_5% 1 D3 G8 INTEGRATED uC 1 R133 1 R132 1 R131 +3VALW USB_RCOMP USB MISC 10K_0402_5% 2 10K_0402_5% PM_SLP_S3# PM_SLP_S5# PBTN_OUT# SB_PWRGD SUS_STAT# 1 C8 USB 1.1 <30> <30> <30> <6,32> <11> NB_PW RGD Part 4 of 5 USBCLK/14M_25M_48M_OSC USB OC 1 R137 +3VS demo circuit LID use RI# 33_0402_5% @ 1 SB700 PCI_PME#/GEVENT4# RI#/EXTEVNT0# SLP_S2/GPM9# SLP_S3# SLP_S5# PWR_BTN# PWR_GOOD SUS_STAT# TEST2 TEST1 TEST0 GA20IN/GEVENT0# KBRST#/GEVENT1# LPC_PME#/GEVENT3# LPC_SMI#/EXTEVNT1# S3_STATE/GEVENT5# SYS_RESET#/GPM7# WAKE#/GEVENT8# BLINK/GPM6# SMBALERT#/THRMTRIP#/GEVENT2# NB_PWRGD USB 2.0 E1 E2 CRT_DET H7 PM_SLP_S3# F5 PM_SLP_S5# G1 PBTN_OUT# H2 SB_PWRGD H1 SUS_STAT# K3 SB_TEST2 H5 SB_TEST1 H4 SB_TEST0 H3 EC_GA20 Y15 EC_KBRST# W15 EC_SCI# K4 EC_SMI# K24 F1 J2 SB_PCIE_WAKE# H6 F2 H_THERMTRIP# J6 NB_PW RGD W14 GPIO EC_SWI# <30> EC_SWI# ACPI / WAKE UP EVENTS 1 @ 2 C232 22P_0402_50V8J @ 2 R109 1 2 U10D HD AUDIO DIS R417 E R510 UMA 1 D B C D Title Compal Electronics, Inc. SB700 USB/HD audio Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Sheet Tuesday, February 03, 2009 E 20 of 46 A B C D E Port Number Pri/SEC,Mas/Slave assignment SATA drive controlled by Port 0 Primary master SATA controler Port 1 Secondary master SATA controler Port 2 Primary slave SATA controler Port 3 Secondary slave SATA controler Port 4 Primary (Secondary) master PATA controler Port 5 Primary (Secondary) slave U10B 1 R411 1 L61 2 1 BLM18PG121SN1D_0603 SATA_TX4P SATA_TX4N AD15 AE15 SATA_RX4N SATA_RX4P AB16 AC16 SATA_TX5P SATA_TX5N C562 2.2U_0603_6.3V4Z Y12 SATA_X1 SATA_X2 AA12 SATA_X2 2 10K_0402_5% SATA_LED# W11 1 2 1 1 C560 C546 1U_0402_6.3V4Z 2 +3VS L34 C296 1U_0402_6.3V4Z +XTLVDD_SATA 2 0.1U_0402_16V4Z 2 1 BLM18PG121SN1D_0603 1 C545 1 2 SATA_CAL SATA_ACT#/GPIO67 AA11 PLLVDD_SATA W12 XTLVDD_SATA 2 R549 @ SPI_DI/GPIO12 SPI_DO/GPIO11 SPI_CLK/GPIO47 SPI_HOLD#/GPIO31 SPI_CS1#/GPIO32 G6 D2 D1 F4 F3 LAN_RST#/GPIO13 ROM_RST#/GPIO14 U15 J1 FANOUT0/GPIO3 FANOUT1/GPIO48 FANOUT2/GPIO49 M8 M5 M7 FANIN0/GPIO50 FANIN1/GPIO51 FANIN2/GPIO52 P5 P8 R8 TEMP_COMM TEMPIN0/GPIO61 TEMPIN1/GPIO62 TEMPIN2/GPIO63 TEMPIN3/TALERT#/GPIO64 C6 B6 A6 A5 B5 VIN0/GPIO53 VIN1/GPIO54 VIN2/GPIO55 VIN3/GPIO56 VIN4/GPIO57 VIN5/GPIO58 VIN6/GPIO59 VIN7/GPIO60 A4 B4 C4 D4 D5 D6 A7 B7 C667 1 1 @ 0.1U_0402_16V4Z 2 0_0603_5% +SB_SPI_VCC R546 1K_0402_5% @ SATA_RX5N SATA_RX5P V12 +3VALW 1 RB751V_SOD323 SB_SI_SPI_SO SB_SO_SPI_SI SB_SPICLK SB_HOLD# SB_SPICS# SB_SPICS# SB_HOLD# 1 @ R545 2 AE14 AD14 2 D30 2 SATA_RX3N SATA_RX3P @ +3VALW 2 AB14 AC14 SATA_CAL 1 1K_0402_1% SATA_X1 +PLLVDD_SATA 2 3 SATA_TX3P SATA_TX3N PATA controler R547 R548 2 @ @ 10K_0402_5% 10K_0402_5% U23 1 CE# 3 WP# 7 HOLD# 4 VSS If use, Un-pop R545 R260 1 R261 1 @ @ @ NB_THERMAL_DA SB_SPICLK SB_SO_SPI_SI SB_SI_SPI_SO NB_THERMAL_DC <11> 1 EC_THERM# 8 6 5 2 MX25L8005M2C-15G_SOP8 @ NB_THERMAL_DC pop after bring up @ NB_THERMAL_DC_R 1 2 NB_THERMAL_DA_R R110 @ 0_0402_5% 1 2 R111 0_0402_5% VDD SCK SI SO 2 0_0402_5% 2 +3VS C229 10P_0402_50V8J NB_THERMAL_DA <11> EC_THERM# <30> 2 0_0402_5% VGA_PRSNT_R 2 0_0402_5% VGA_PRSNT_L VGA_PRSNT_R <14> VGA_PRSNT_L <14> 2 D7 R104 1 ACIN 1 RB751V_SOD323 2 100K_0402_5% F6 AVSS G7 1 +SB_AVDD 1 1 2 C492 0.1U_0402_16V4Z 218S7EALA11FG_BGA528_SB700 ACIN <30,36,37,40> +3VS +3VALWS U44 AVDD VGA_PRSNT_R1 2 R295 10K_0402_5% VGA_PRSNT_L 1 2 R296 10K_0402_5% 5 SATA_X2 +3VS <31> SATA_LED# +1.2V_HT AD13 AE13 AD24 AD23 AE22 AC22 AD21 AE20 AB20 AD19 AE19 AC20 AD20 AE21 AB22 AD22 AE23 AC23 2 L55 2 1 BLM18PG121SN1D_0603 4 +3VALW C488 2.2U_0603_6.3V4Z NC7SZ08P5X_NL_SC70-5 @ 3 2 B 0.1U_0402_16V4Z 2 A 1 Y @ C670 P 2 R412 0.1U_0402_16V4Z 1 C283 SATA_RX2N SATA_RX2P IDE_D0/GPIO15 IDE_D1/GPIO16 IDE_D2/GPIO17 IDE_D3/GPIO18 IDE_D4/GPIO19 IDE_D5/GPIO20 IDE_D6/GPIO21 IDE_D7/GPIO22 IDE_D8/GPIO23 IDE_D9/GPIO24 IDE_D10/GPIO25 IDE_D11/GPIO26 IDE_D12/GPIO27 IDE_D13/GPIO28 IDE_D14/GPIO29 IDE_D15/GPIO30 G 10M_0402_5% 2 10P_0402_50V8J 2 AE12 AD12 AE16 AD16 Y3 2 25MHZ_20P SATA_TX2P SATA_TX2N 1 ACIN 3 R176 SATA_RX1N SATA_RX1P AB12 AC12 1 SATA_X1 1 C284 AD11 AE11 1 4.99_0402_1% SATA_STX_DRX_P2 2 SATA_STX_DRX_N2 2 4.99_0402_1% SATA_DTX_C_SRX_N2 <24> SATA_DTX_C_SRX_N2 SATA_DTX_C_SRX_P2 <24> SATA_DTX_C_SRX_P2 SATA_TX1P SATA_TX1N Part 2 of 5 ATA 66/100/133 R3421 1 R183 AE10 AD10 IDE_IORDY IDE_IRQ IDE_A0 IDE_A1 IDE_A2 IDE_DACK# IDE_DRQ IDE_IOR# IDE_IOW# IDE_CS1# IDE_CS3# AA24 AA25 Y22 AB23 Y23 AB24 AD25 AC25 AC24 Y25 Y24 1 10P_0402_50V8J 2 1 2 SATA_STX_R_DRX_P2 SATA_STX_R_DRX_N2 <24> SATA_STX_R_DRX_P2 <24> SATA_STX_R_DRX_N2 SATA_RX0N SATA_RX0P HW MONITOR ODD SATA_STX_DRX_P1 2 4.99_0402_1% SATA_STX_DRX_N1 2 4.99_0402_1% SATA_DTX_C_SRX_N1 <24> SATA_DTX_C_SRX_N1 SATA_DTX_C_SRX_P1 <24> SATA_DTX_C_SRX_P1 1 S- HDD SATA_STX_R_DRX_P1 1 SATA_STX_R_DRX_N1 R182 1 R181 <24> SATA_STX_R_DRX_P1 <24> SATA_STX_R_DRX_N1 SATA_TX0P SATA_TX0N AB10 AC10 SPI ROM SATA_DTX_C_SRX_N0 SATA_DTX_C_SRX_P0 <24> SATA_DTX_C_SRX_N0 <24> SATA_DTX_C_SRX_P0 SERIAL ATA <24> SATA_STX_DRX_P0 <24> SATA_STX_DRX_N0 HDD SB700 AD9 AE9 SATA PWR SATA_STX_DRX_P0 SATA_STX_DRX_N0 4 4 Compal Secret Data Security Classification 2008/11/03 Issued Date 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. SB700 SATA/IDE/SPI Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Sheet Tuesday, February 03, 2009 E 21 of 46 B C D FOR SB700 ALL issue A12 Will change to +1.2V_HT +SB_VDD @ 2 10U_0603_6.3V6M C529 C536 C556 C513 C542 C550 C538 C508 1 1 1 1 1 1 1 1 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 +3VS VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 Y20 AA21 AA22 AE25 VDD33_18_1 VDD33_18_2 VDD33_18_3 VDD33_18_4 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 L15 M12 M14 N13 P12 P14 R11 R15 T16 CKVDD_1.2V_1 CKVDD_1.2V_2 CKVDD_1.2V_3 CKVDD_1.2V_4 L21 L22 L24 L25 Part 3 of 5 CORE S0 C563 SB700 L9 M9 T15 U9 U16 U17 V8 W7 Y6 AA4 AB5 AB21 PCI/GPIO I/O 10U_0603_6.3V6M C544 C548 C551 +1.2V_HT 1 @ 2 0.1U_0402_16V4Z 1 @ 2 0.1U_0402_16V4Z 1 2 0.1U_0402_16V4Z @ L32 2 1 FBMA-L11-201209-221LMA30T_0805 +PCIE_VDDR CLKGEN I/O 10U_0603_6.3V6M IDE/FLSH I/O C558 2 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z C251 1 C250 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z +1.2V_SATA L60 2 1 FBMA-L11-201209-221LMA30T_0805 C565 1 1 1 1 10U_0603_6.3V6M 10U_0603_6.3V6M 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AA14 AB18 AA15 AA17 AC18 AD17 AE17 PCIE_VDDR_1 PCIE_VDDR_2 PCIE_VDDR_3 PCIE_VDDR_4 PCIE_VDDR_5 PCIE_VDDR_6 PCIE_VDDR_7 AVDD_SATA_1 AVDD_SATA_4 AVDD_SATA_2 AVDD_SATA_3 AVDD_SATA_5 AVDD_SATA_6 AVDD_SATA_7 3.3V_S5 I/O C525 1 C522 1 C527 1 P18 P19 P20 P21 R22 R24 R25 2 2 2 2 2 2 +1.2V_CKVDD C512 C504 C521 C526 C519 C511 1 1 1 1 1 1 S5_3.3V_1 S5_3.3V_2 S5_3.3V_3 S5_3.3V_4 S5_3.3V_5 S5_3.3V_6 S5_3.3V_7 A17 A24 B17 J4 J5 L1 L2 S5_1.2V_1 S5_1.2V_2 G2 G4 1 R138 2 FBMA-L11-201209-221LMA30T_0805 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AVDDTX_0 AVDDTX_1 AVDDTX_2 AVDDTX_3 AVDDTX_4 AVDDTX_5 AVDDRX_0 AVDDRX_1 AVDDRX_2 AVDDRX_3 AVDDRX_4 AVDDRX_5 PLL A16 B16 C16 D16 D17 E17 F15 F17 F18 G15 G17 G18 C252 10U_0603_6.3V6M C243 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 L28 C227 A10 B10 C242 V5_VREF AE7 +V5_VREF AVDDCK_3.3V J16 +AVDDCK_3.3V AVDDC C241 1 1 1 1 C503 C253 C506 C247 +1.2VALW L56 FBMA-L11-160808-221LMT 0603 +1.2_USB AVDDCK_1.2V 1 +1.2VALW 2 C231 2 C240 R578 2 USB I/O 2 2 2 2 2 2 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z 1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 10U_0603_6.3V6M 1 1 2 2 T10 U10 U11 U12 V11 V14 W9 Y9 Y11 Y14 Y17 AA9 AB9 AB11 AB13 AB15 AB17 AC8 AD8 AE8 AVSS_SATA_1 AVSS_SATA_2 AVSS_SATA_3 AVSS_SATA_4 AVSS_SATA_5 AVSS_SATA_6 AVSS_SATA_7 AVSS_SATA_8 AVSS_SATA_9 AVSS_SATA_10 AVSS_SATA_11 AVSS_SATA_12 AVSS_SATA_13 AVSS_SATA_14 AVSS_SATA_15 AVSS_SATA_16 AVSS_SATA_17 AVSS_SATA_18 AVSS_SATA_19 AVSS_SATA_20 A15 B15 C14 D8 D9 D11 D13 D14 D15 E15 F12 F14 G9 H9 H17 J9 J11 J12 J14 J15 K10 K12 K14 K15 AVSS_USB_1 AVSS_USB_2 AVSS_USB_3 AVSS_USB_4 AVSS_USB_5 AVSS_USB_6 AVSS_USB_7 AVSS_USB_8 AVSS_USB_9 AVSS_USB_10 AVSS_USB_11 AVSS_USB_12 AVSS_USB_13 AVSS_USB_14 AVSS_USB_15 AVSS_USB_16 AVSS_USB_17 AVSS_USB_18 AVSS_USB_19 AVSS_USB_20 AVSS_USB_21 AVSS_USB_22 AVSS_USB_23 AVSS_USB_24 +3VALW USB_PHY_1.2V_1 USB_PHY_1.2V_2 L29 2 1 FBMA-L11-201209-221LMA30T_0805 1 1 1 1 1 +1.2V_HT C505 C249 C502 C507 C248 +AVDD_USB C228 C236 C491 C497 C493 C489 C499 U10E SB700 L31 +S5_1.2V CORE S5 10U_0603_6.3V6M A-LINK I/O 10U_0603_6.3V6M C276 C547 C549 C552 C559 3 C401 POWER SATA I/O C254 C568 +3VALW 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +S5_3V +1.2V_HT C490 FBMA-L11-160808-221LMT 0603 10U_0603_6.3V6M @ 2 10U_0603_6.3V6M @ C557 +1.2V_HT FBMA-L11-201209-221LMA30T_0805 U10C 1 FBMA-L11-201209-221LMA30T_0805 2 +1.2VALW 1 R399 1 R391 +3VS C561 E FBMA-L11-160808-221LMT 0603 1U_0402_6.3V4Z 1U_0402_6.3V4Z 10U_0603_6.3V6M 1 K17 E9 +AVDDC 2 2 1 C291 1U_0603_10V4Z 1 L54 FBMA-L11-160808-221LMT 0603 1 D9 1 R172 +5VS 2 +3VS H18 J17 J22 K25 M16 M17 M21 P16 RB751V_SOD323 F9 +3VALW 2.2U_0603_6.3V4Z 2 1 C487 0.1U_0402_16V4Z 2 1 C496 PCIE_CK_VSS_1 PCIE_CK_VSS_2 PCIE_CK_VSS_3 PCIE_CK_VSS_4 PCIE_CK_VSS_5 PCIE_CK_VSS_6 PCIE_CK_VSS_7 PCIE_CK_VSS_8 AVSSC VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 PCIE_CK_VSS_9 PCIE_CK_VSS_10 PCIE_CK_VSS_11 PCIE_CK_VSS_12 PCIE_CK_VSS_13 PCIE_CK_VSS_14 PCIE_CK_VSS_15 PCIE_CK_VSS_16 PCIE_CK_VSS_17 PCIE_CK_VSS_18 PCIE_CK_VSS_19 PCIE_CK_VSS_20 PCIE_CK_VSS_21 Part 5 of 5 AVSSCK A2 A25 B1 D7 F20 G19 H8 K9 K11 K16 L4 L7 L10 L11 L12 L14 L16 M6 M10 M11 M13 M15 N4 N12 N14 P6 P9 P10 P11 P13 P15 R1 R2 R4 R9 R10 R12 R14 T11 T12 T14 U4 U14 V6 Y21 AB1 AB19 AB25 AE1 AE24 1 2 P23 R16 R19 T17 U18 U20 V18 V20 V21 W19 W22 W24 W25 L17 3 218S7EALA11FG_BGA528_SB700 L57 +1.2V_HT FBMA-L11-160808-221LMT 0603 2.2U_0603_6.3V4Z 2 0.1U_0402_16V4Z +AVDDCK_3.3V C495 C494 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1K_0402_5% 1K_0402_5% 2 +AVDDCK_1.2V 1 1 10U_0603_6.3V6M 1 1 C277 +AVDDCK_1.2V0.1U_0402_16V4Z 218S7EALA11FG_BGA528_SB700 2 2 GROUND A 2 1 C501 1 C510 L30 FBMA-L11-160808-221LMT 0603 2.2U_0603_6.3V4Z 2 1 C246 0.1U_0402_16V4Z 2 1 C500 +3VS 4 4 Compal Secret Data Security Classification 2008/11/03 Issued Date 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. SB700 power/GND Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Tuesday, February 03, 2009 Sheet E 22 of 46 B C REQUIRED STRAPS PULL HIGH BOOTFAIL TIMER ENABLED USE DEBUG STRAPS NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK PCI_CLK4 PCI_CLK5 RESERVED RESERVED LPC_CLK0 CLK_PCI_EC LPC_CLK1 ENABLE PCI MEM BOOT RTC_CLK AZ_RST_CD# INTERNAL RTC CLKGEN ENABLED GP17 EC ENABLED BOOTFAIL TIMER DISABLED IGNORE DEBUG STRAPS DISABLE PCI MEM BOOT DE FAULT DE FAULT DE FAULT H,H = Reserved L,H = LPC ROM (Default L,NC) L,L = FWH ROM R116 10K_0402_5% 2 1 R125 10K_0402_5% 2 1 R139 10K_0402_5% 2 1 +3VALW R121 10K_0402_5% 2 1 +3VALW R159 10K_0402_5% 2 1 +3VALW R161 10K_0402_5% 2 1 +3VALW R158 10K_0402_5% 2 1 +3VS DE FAULT @ @ @ @ @ @ @ @ +3VALW @ +3VALW R100 2.2K_0402_5% 2 1 @ R99 2.2K_0402_5% 2 1 R140 10K_0402_5% 2 1 R126 2.2K_0402_5% 2 1 @ R117 10K_0402_5% 2 1 R160 10K_0402_5% 2 1 @ R122 10K_0402_5% 2 1 R162 10K_0402_5% 2 1 2 R156 10K_0402_5% 2 1 2 +3VS EC DISABLED PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 CLK_PCI_EC LPCCLK1 RTC_CLK HDARST# GPIO17 GPIO16 R157 10K_0402_5% 2 1 <19> PCI_CLK2 <19> PCI_CLK3 <19> PCI_CLK4 <19> PCI_CLK5 <19,30> CLK_PCI_EC <19,30> LPCCLK1 <19> RTC_CLK <20> HDARST# <20> GPIO17 <20> GPIO16 +3VS DE FAULT 1 H,L = SPI ROM EXT. RTC (PD on X1, apply 32KHz to RTC_CLK) R155 10K_0402_5% 2 1 +3VS CLKGEN DISABLED GP16 Internal pull up DE FAULT 1 PULL LOW E R103 2.2K_0402_5% 2 1 PCI_CLK2 PCI_CLK3 CLK_PCI_PCM CLK_PCI_DBG D R102 2.2K_0402_5% 2 1 A @ DEBUG STRAPS PULL LOW PCI_AD23 USE DEFAULT PCIE STRAPS RESERVED DE FAULT DE FAULT DE FAULT DE FAULT DE FAULT USE SHORT RESET BYPASS PCI PLL BYPASS ACPI BCLK BYPASS IDE PLL USE EEPROM PCIE STRAPS 3 @ @ @ @ @ R164 2.2K_0402_5% 2 1 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 R166 2.2K_0402_5% 2 1 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD24 USE IDE PLL R167 2.2K_0402_5% 2 1 <19> <19> <19> <19> <19> <19> PCI_AD25 USE ACPI BCLK R169 2.2K_0402_5% 2 1 3 PCI_AD26 USE PCI PLL R165 2.2K_0402_5% 2 1 PCI_AD28 PULL HIGH PCI_AD27 USE LONG RESET R168 2.2K_0402_5% 2 1 SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23] @ 4 4 Compal Secret Data Security Classification 2008/11/03 Issued Date 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. SB700 STRAPS Size Document Number Custom KBYF0 Date: Rev 0.3 LA-5051P Sheet Tuesday, February 03, 2009 E 23 of 46 A B C D 0.1U_0402_16V4Z C482 10U_0805_10V4Z G H 1 1 1 C483 1 1 C421 C395 1 GND A+ AGND BB+ GND C396 C420 2 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 1000P_0402_50V7K 1 @ C424 1 @ C419 1 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_STX_DRX_P0 SATA_STX_DRX_N0 SATA_DTX_SRX_N0 SATA_DTX_SRX_P0 1 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_DTX_C_SRX_N0 SATA_DTX_C_SRX_P0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12 +3VS_HDD1 0.1U_0402_16V4Z 1 SATA_STX_RC_DRX_P0 C336 SATA_STX_RC_DRX_N0 C332 C345 C347 SATA_STX_DRX_P0 <21> SATA_STX_DRX_N0 <21> +1.5VS @ C423 2 2 2 1000P_0402_50V7K 1U_0603_10V4Z Pleace near HD CONN +5VS 1 1 1 C610 C611 C612 @ @ @ 1U_0402_6.3V4Z 0.1U_0402_16V4Z 2 2 2 0.1U_0402_16V4Z +1.5VS SATA_DTX_C_SRX_N0 <21> SATA_DTX_C_SRX_P0 <21> U2 +3VS_HDD1 Pleace near HD CONN (JSATA1) +3VS R348 0_0805_5% 2 1 +1.5VS JSATA1 1 2 3 4 5 6 7 1U_0402_6.3V4Z 1 F HDD +5VS 2 E 2 6 VDD1 VDD2 VDD3 VDD4 CE 9 15 19 SATA1_CE 1 @ @ C622 1 C620 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_PTX_RPI_DRX_P0 SATA_PTX_RPI_DRX_N0 3 4 AI+ AI- AO+ AO- 18 17 SATA_PTX_RPO_DRX_P0 SATA_PTX_RPO_DRX_N0 @ @ C618 1 C617 1 2 0.01U_0402_16V7K SATA_DTX_RPO_PRX_N0 2 0.01U_0402_16V7K SATA_DTX_RPO_PRX_P0 7 8 BO+ BO- BI+ BI- 14 13 SATA_DTX_RPI_PRX_N0 SATA_DTX_RPI_PRX_P0 GND1 GND2 GND3 GND4 5 16 12 21 R680 R679 R677 R676 Adjust HDD1 CHA I/O EQ Adjust HDD1 CHB I/O EQ 2 2 2 2 @ @ @ @ 1 1 1 1 470K_0402_5% 470K_0402_5% 470K_0402_5% 470K_0402_5% 1 20 10 11 A_EQ A_EM B_EQ B_EM PI2EQX3231BLZHE_TQFN20_3P5X4P5 @ SUYIN_127043FR022G226ZL_NR R404 1 R403 1 @ @ 2 0_0402_5% SATA_PTX_RPO_DRX_P0 R425 2 0_0402_5% SATA_PTX_RPO_DRX_N0 R402 1 R401 1 @ @ 2 0_0402_5% SATA_DTX_RPI_PRX_N0 2 0_0402_5% SATA_DTX_RPI_PRX_P0 @ 1 2 470_0402_5% Adjust HDD1 PCH TX Swing +1.5VS 2 Second-HDD R426 10K_0402_5% @ +5VS JSATA3 GND 1 A+ 2 A- 3 GND 4 B- 5 B+ 6 GND 7 C573 10U_0805_10V4Z 1U_0402_6.3V4Z 2 1 1 1 C576 2 1 C567 1 C574 1 C575 C486 2 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 1000P_0402_50V7K +3VS_HDD2 0.1U_0402_16V4Z 1 1 @ C570 @ C485 SATA_STX_RC_DRX_P1 C379 SATA_STX_RC_DRX_N1 C384 1 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_STX_R_DRX_P1 SATA_STX_R_DRX_N1 SATA_DTX_SRX_N1 SATA_DTX_SRX_P1 1 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_DTX_C_SRX_N1 SATA_DTX_C_SRX_P1 C378 C369 SATA1_CE SATA_STX_R_DRX_P1 <21> SATA_STX_R_DRX_N1 <21> 2 SATA_DTX_C_SRX_N1 <21> SATA_DTX_C_SRX_P1 <21> +3VS_HDD2 Pleace near HD CONN (JSATA3) +3VS R349 0_0805_5% 2 1 HDD1 Redriver Chip Enable 1 @ C569 2 2 2 1000P_0402_50V7K 1U_0603_10V4Z Pleace near HD CONN VCC3.3 VCC3.3 VCC3.3 GND GND GND VCC5 VCC5 VCC5 GND RESERVED GND VCC12 VCC12 VCC12 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 G1 G2 23 24 +5VS ODD JSATA2 OCTEK_SAT-22SB1G_RV CONN@ 15 14 3 GND GND GND A+ AGND BB+ GND 1 2 3 4 5 6 7 DP +5V +5V MD GND GND 8 9 10 11 12 13 SATA_STX_RC_DRX_P2 C302 SATA_STX_RC_DRX_N2 C301 1 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_STX_R_DRX_P2 SATA_STX_R_DRX_N2 SATA_DTX_SRX_N2 SATA_DTX_SRX_P2 1 1 2 0.01U_0402_16V7K 2 0.01U_0402_16V7K SATA_DTX_C_SRX_N2 SATA_DTX_C_SRX_P2 C300 C299 3 C333 0.1U_0402_16V4Z C806 150U_Y_6.3VM USB20_P2_1 R389 1 @ 2 USB20_N2_1 <20> USB20_N2_1 1 2 2 4 4 3 3 3 1 C807 1 2 1 2 1 2 C386 10U_0805_10V4Z JUSB4 2 USB20_N2_R USB20_P2_R 1 2 3 4 5 6 USB20_N2_R USB20_P2_R 0_0402_5% L37 VCC DD+ GND GND1 GND2 SUYIN_020173MR004S512ZL 4 D39 PJDLC05_SOT23~D WCM2012F2S-900T04_0805 USB20_P2_R USB20_N2_R <> R377 1 @ 2 1 4 2 0.1U_0402_16V4Z 2 1 C808 2 <29,36,43> SYSON# <20> USB20_P2_1 1 + 1 2 2 2 1000P_0402_50V7K C614 W=60mils 1 10U_0805_10V4Z 4.7U_0805_10V4Z 2 +USB_VCCA USB_OC#2 <20,29> 1 1U_0603_10V4Z 100K_0402_5% 1 2 R228 10K_0402_5% C580 TPS2061DRG4_SO8 C591 1 R242 8 7 6 5 OUT OUT OUT FLG 0.1U_0402_16V4Z C340 GND IN IN EN# Placea caps. near ODD CONN. 1 80mil U30 1 2 3 4 SATA_DTX_C_SRX_N2 <21> SATA_DTX_C_SRX_P2 <21> +5VS +3VALW +USB_VCCA SATA_STX_R_DRX_P2 <21> SATA_STX_R_DRX_N2 <21> +5VS CONN@ OCTEK_0709015-SD001_RV +5VALW 1 0.1U_0402_16V4Z 0_0402_5% Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/11/03 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D E F Title HDD & ODD Connector Size B Document Number Rev 0.3 KBYF0 LA-5051P Date: Tuesday, February 03, 2009 G Sheet 24 H of 46 5 4 3 2 +REG18_PLL 2 R362 1 +REG18 1 0_0402_5% U14 2 C592 1 R844 +3VS D @ 1 R843 +3VALW +XDPWR_SDPWR_MSPWR +XDPWR_SDPWR_MSPWR 2 0_0603_5% 2 0_0603_5% C593 1 0.1U_0402_16V4Z 1 C594 0.1U_0402_16V4Z 1 @ 4.7U_0603_6.3V6K2 2 RST# MODE_SEL XTLO XTLI 2 +3VS @ MODE_SEL 2 R363 1 1 R396 0_0402_5% CARD_AGND DM DP GPIO0 1 @ 1 2 C597 6P_0402_50V8D 6 46 AGND AGND R42 100K_0402_5% @ 1 0_0603_5% 2 C604 22P_0402_50V8J +3VS C SD_CMD JP56 XTLO 32 10 9 8 7 6 5 4 XD-D0 XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7 SDDAT3_XDWE# SDDAT4_XDWP#_MSD7 XDALE XDCD XD_RDY SDDAT2_XDRE# XDCE# XDCLE 34 33 35 40 39 38 37 36 XD-WE XD-WP XD-ALE XD-CD XD-R/B XD-RE XD-CE XD-CLE 11 31 7IN1 GND 7IN1 GND +CARDPWR 2 0_0603_5% 41 42 1 XD-VCC SDDAT5_XDD0_MSD6 SDCLK_XDD1_MSCLK SDDAT7_XDD2_MSD2 SDDAT1_XDD3_MSD1 XDD4_SDDAT1 XDD5_MSBS SDDAT0_XDD6_MSD0 SDDAT6_XDD7_MSD3 7 IN 1 CONN SD-VCC MS-VCC 21 28 SD_CLK SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-DAT4 SD-DAT5 SD-DAT6 SD-DAT7 SD-CMD SD-CD-SW 20 14 12 30 29 27 23 18 16 25 1 SD-WP-SW 2 MS-SCLK MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 MS-INS MS-BS C603 2 SDCLK_XDD1_MSCLK SDDAT0_XDD6_MSD0 XDD4_SDDAT1 SDDAT2_XDRE# SDDAT3_XDWE# SDDAT4_XDWP#_MSD7 SDDAT5_XDD0_MSD6 SDDAT6_XDD7_MSD3 SDDAT7_XDD2_MSD2 SD_CMD SDCD 1 1 C342 C484 0.1U_0402_16V4Z 2 2 10U_0805_10V4Z B 0.1U_0402_16V4Z SDWP SDCLK_XDD1_MSCLK SDDAT0_XDD6_MSD0 SDDAT1_XDD3_MSD1 SDDAT7_XDD2_MSD2 SDDAT6_XDD7_MSD3 MS_INS# XDD5_MSBS 26 17 15 19 24 22 13 7IN1 GND 7IN1 GND TAITW_R015-A10-LM_NR C599 0.1U_0402_16V4Z 1 2 2 R284 SDCLK_XDD1_MSCLK 1 0_0402_5% 1 +CARDPWR 3 1 A XTAL_CTR 2 R354 +CARDPWR EMI R400 EEDO EECS EESK SD_CMD 15 16 17 36 XDCLE XDCE# XDALE SDDAT2_XDRE# SDDAT3_XDWE# XD_RDY SDDAT4_XDWP#_MSD7 SDDAT5_XDD0_MSD6 SDCLK_XDD1_MSCLK_L SDDAT6_XDD7_MSD3 MS_INS# SDDAT7_XDD2_MSD2 SDDAT0_XDD6_MSD0 SDDAT1_XDD3_MSD1 XDD5_MSBS XDD4_SDDAT1 SDCD SDWP XDCD +CARDPWR @ 1 2 C600 6P_0402_50V8D 40~60 mil1 13 24 DGND DGND 1 C598 22P_0402_50V8J +XDPWR_SDPWR_MSPWR XTAL_CTR MS_D5 RREF D XTLI 2 2 2 43 42 41 40 39 38 37 35 34 31 29 28 27 26 25 23 21 20 19 18 2 1U_0402_6.3V4Z R392 0_0603_5% @ Y2 12MHZ_16PF_6X12000012 1 @ XD_CLE_SP19 XD_CE#_SP18 XD_ALE_SP17 SD_DAT2/XD_RE#_SP16 SD_DAT3/XD_WE#_SP15 XD_RDY_SP14 SD_DAT4/XD_WP#/MS_D7_SP13 SD_DAT5/XD_D0/MS_D6_SP12 SD_CLK/XD_D1/MS_CLK_SP11 SD_DAT6/XD_D7/MS_D3_SP10 MS_INS#_SP9 SD_DAT7/XD_D2/MS_D2_SP8 SD_DAT0/XD_D6/MS_D0_SP7 SD_DAT1/XD_D3/MS_D1_SP6 XD_D5_SP5 XD_D4/SD_DAT1_SP4 SD_CD#_SP3 SD_WP_SP2 XD_CD#_SP1 EEDI 1 C341 2 0_0402_5% R397 33_0402_5% @ 10 22 30 RTS5158E-GR_LQFP48_7X7 1 1 R398 VREG MS_D4 NC 2 2 R396 NC for RTS5158E R396 stuff for RTS5159 <15> CLK_SD_48M 2 4 5 14 1 2 6.19K_0402_1% 12 32 2 B 3V3_IN RST# MODE_SEL XTLO XTLI C595 1U_0402_6.3V4Z 2 @ C596 47P_0402_50V8J 8 44 45 47 48 RST# 2 0_0402_5% 1 R393 1 C AV_PLL NC NC CARD_3V3 D3V3 D3V3 Internal 200K Pull UP 1 Vender suggesttion USB20_N4 USB20_P4 <20> USB20_N4 <20> USB20_P4 <31> 5IN1_LED# R395 100K_0402_5% 1 3 7 9 11 33 A Compal Electronics, Inc. Compal Secret Data Security Classification 2008/11/03 Issued Date Deciphered Date 2009/11/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Card Reader JMB385 Size Document Number Custom Rev 0.3 KBYF0 LA-5051P Date: Tuesday, February 03, 2009 Sheet 1 25 of 46 A 1 R77 2 0_1206_5% +3V_LAN +3V_LAN R309 1 2 1_1206_1% R12 2 1_1206_1% 1 2 LAN_PME# 4.7K_0402_5% 1 R60 +3V_LAN C +3V_LAN C28 +1.2V_LAN 2 4 LAN_REGCTL12 1 60mil 1 0.1U_0402_16V4Z 2 2 4.7U_0805_10V4Z Q3 MMJT9435T1G_SOT223 +3V_LAN D +3V_LAN_R 1 C27 3 +3VALW B 1 1 1 C149 1 1 C417 1 C422 1 C68 C428 1 4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z C678 1 C412 1 1 C71 C132 1 1 C37 1 C448 C409 1 1 C438 C111 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 2 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z +1.2V_VDDCIO 1 C415 1 C39 +3V_LAN U5 R21 +3V_LAN R20 2 10K_0402_5% 1 2 1K_0402_5% 53 VMAIN_PRSNT 2 1K_0402_5% 54 VAUX_PRSNT 1 <30> ENERGY_DET <10> PCIE_ITX_C_PRX_P3 C142 1 <10> PCIE_PTX_C_IRX_P3 C143 1 <11,13,19,28,30> PLT_RST# 2 1 R56 R61 1 1 <20,28> SB_PCIE_WAKE# <30> EC_PME# 35 PCIE_RXD_P 25 PCIE_TXD_N 0_0402_5% LAN_RESET# 2 @ LAN_PME# 2 0_0402_5% 2 0_0402_5% 65 63 64 62 REGCTL12 REGCTL25/12_IO RDAC 14 18 37 XTALVDD VDDIO VDDIO VDDIO VDDIO VDDIO 23 6 15 19 56 61 VDDP VDDP/DC 17 68 VDDC VDDC VDDC VDDC VDDC VDDC 5 13 20 34 55 60 10 PERST 12 WAKE 58 SMB_CLK LAN_SMBDATA 57 SMB_DATA BIASVDD PCIE_PLLVDD PCIE_VDD/PLL PCIE_VDD 36 30 27 33 AVDD/DC AVDD/AVDDL AVDD/DC 38 45 52 39 44 46 51 69 XTALO R73 200_0402_1% 2 Y1 1 1 2 SPROM_WP 2 LAN_XTALO 25MHZ_20P C138 27P_0402_50V8J 4 GPIO_0(SERIAL_DO) 7 GPIO_1(SERIAL_DI) 8 GPIO_2 9 UART_MODE 1 C137 27P_0402_50V8J 2 LAN_XTALI 21 XTALI XTALO 22 XTALO 16 AVDDL AVDDL/T1_P REG_GND/S_IDDQ AVDDL/T2_P AVDDL PCIE_GND/VDD E- PAD 1 2 R67 0_0402_5% +LAN_PCIEVDD 24 LAN_LINK# 1 LAN_ACTIVITY# +3V_LAN LAN_LINK# <27> LAN_ACTIVITY# <27> +3V_LAN R29 2 4.7K_0402_5% 1 1 0_0402_5% +1.2V_VDDCIO A0 A1 A2 GND VCC WP SCL SDA +3V_LAN 1 SPROM_WP SPROM_CLK SPROM_DOUT 20mil L48 1 2 BLM18AG601SN1D_0603 +LAN_XTALVDD 8 7 6 5 +LAN_PCIEPLLVDD 1 1 C440 C445 +3V_LAN C444 20mil +LAN_PCIEVDD 1 1 C434 C441 +1.2V_LAN 0.1U_0402_16V4Z 2 +LAN_BIASVDD +LAN_PCIEPLLVDD 1 2 BLM18AG601SN1D_0603 1 +LAN_PCIEVDD L45 1 2 BLM18AG601SN1D_0603 +1.2V_LAN 3 2 4.7U_0805_10V4Z 20mil +LAN_AVDD 1 C427 0.1U_0402_16V4Z 2 +LAN_AVDDL +LAN_AVDDL LAN_MIDI1+ LAN_MIDI2+ +LAN_AVDDL +3V_LAN C437 C70 0.1U_0402_16V4Z 2 +LAN_AVDDL 1 C426 2 0.1U_0402_16V4Z C416 0.1U_0402_16V4Z 2 L39 1 2 +3V_LAN BLM18AG601SN1D_0603 1 20mil LAN_MIDI1+ <27> LAN_MIDI2+ <27> 5784 1 L38 1 2 BLM18AG601SN1D_0603 +1.2V_LAN 2 4.7U_0805_10V4Z 20mil +LAN_GPHYPLLVDD 1 1 C126 C122 L19 1 2 BLM18AG601SN1D_0603 +1.2V_LAN LAN_SMBDATA 0.1U_0402_16V4Z 2 +3V_LAN 2 4.7U_0805_10V4Z 4 1 Q4B @ 2N7002DW-T/R7_SOT363-6 1 2 R15 0_0402_5% @ +3V_LAN R16 4.7K_0402_5% 2 2 4 +1.2V_LAN L43 2 <20> ICH_SMBDATA1 4 L47 1 2 BLM18AG601SN1D_0603 0.1U_0402_16V4Z 2 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z +1.2V_VDDCIO 5 3 R312 R321 4.7K_0402_5%4.7K_0402_5% AT24C64AN-10SU-2.7_SO8 2 1.24K_0402_1% BCM5764MKML_QFN68 R14 4.7K_0402_5% 2 R311 4.7K_0402_5% 0.1U_0402_16V4Z 2 1 2 3 4 1 +3V_LAN +3V_LAN 1 U24 LAN_REGCTL12 LAN_RDAC1 R66 +3V_LAN +3V_LAN C410 2 R308 @ PCIE_TXD_P LAN_SMBCLK 3 1 PCIE_RXD_N 31 26 SCLK(EECLK) SI SO(EEDATA) CS 2 R24 0_0402_5% 2 R25 0_0402_5% SPROM_CLK SPROM_DIN SPROM_DOUT SPROM_CS GPHY_PLLVDD PCIE_PTX_IRX_N3 PCIE_PTX_IRX_P3 2 1 67 66 ENERGY_DET PCIE_ITX_C_PRX_P3 0.1U_0402_16V7K LINKLED SPD100LED SPD1000LED TRAFFICLED LOW PWR 1 LAN_XTALI 59 +LAN_GPHYPLLVDD 0.1U_0402_16V7K 2 PLT_RST# R47 ENERGY_DET PCIE_ITX_C_PRX_N3 32 <10> PCIE_ITX_C_PRX_N3 <10> PCIE_PTX_C_IRX_N3 3 SPROM_DIN 2 1 +3VS 4.7K_0402_5% LAN_MIDI2- <27> LAN_MIDI3- <27> LAN_MIDI3+ <27> 1 R37 2 R299 LAN_MIDI1- <27> 2 11 TRD0_N TRD0_P TRD1_N/AVDD PCIE_REFCLK_P TRD1_P/T1_N TRD2_N/AVDD CLKREQ TRD2_P/T2_N TRD3_N TRD3_P PCIE_REFCLK_N 1 29 2 28 CLK_PCIE_LAN 2 CLK_PCIE_LAN# LAN_MIDI0- <27> LAN_MIDI0+ <27> 1 <15> CLK_PCIE_LAN LAN_MIDI0LAN_MIDI0+ +LAN_AVDD LAN_MIDI1+LAN_AVDD LAN_MIDI2LAN_MIDI3LAN_MIDI3+ 1 <15> CLK_PCIE_LAN# 41 40 42 43 48 47 49 50 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z <20> ICH_SMBCLK1 6 1 LAN_SMBCLK A Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date Q4A @ 2N7002DW-T/R7_SOT363-6 1 2 @ R19 0_0402_5% 2008/11/03 Deciphered Date 2009/11/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B C Title BCM5764M_5787M Size Document Number Custom R ev 0.3 KBYF0 LA-5051P Date: Tuesday, February 03, 2009 D Sheet 26 of 46 5 4 3 2 1 T1 D <26> LAN_MIDI0+ <26> LAN_MIDI0- LAN_MIDI0+ LAN_MIDI0- <26> LAN_MIDI1+ <26> LAN_MIDI1- LAN_MIDI1+ LAN_MIDI1- <26> LAN_MIDI2+ <26> LAN_MIDI2- LAN_MIDI2+ LAN_MIDI2- <26> LAN_MIDI3+ <26> LAN_MIDI3- LAN_MIDI3+ LAN_MIDI3- 1 2 3 4 5 6 7 8 9 10 11 12 TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD4- D MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX4- 24 23 22 21 20 19 18 17 16 15 14 13 RJ45_MIDI0+ RJ45_MIDI0RJ45_MIDI1+ RJ45_MIDI1- 1 RJ45_MIDI2+ RJ45_MIDI2RJ45_MIDI3+ RJ45_MIDI3- 1 1 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z C403 1 1 1 R303 75_0402_1% C406 R304 75_0402_1% 0.1U_0402_16V4Z 2 40mil 2 1 2 C402 RJ45_GND 0.1U_0402_16V4Z 1 2 1 2 R302 75_0402_1% 2 C C400 2 R298 +3V_LAN R300 75_0402_1% 1 LAN_ACTIVITY# <26> LAN_ACTIVITY# 350uH_GSL5009LF-1 11 2 +3V_LAN Yellow LED+ 8 PR4- RJ45_MIDI3+ 7 PR4+ RJ45_MIDI1- 6 PR2- RJ45_MIDI2- 5 PR3- RJ45_MIDI2+ 4 PR3+ RJ45_MIDI1+ 3 PR2+ RJ45_MIDI0- 2 PR1- RJ45_MIDI0+ 1 PR1+ 10 1 1K_0402_5% 9 R307 Guide Pin SHLD2 14 SHLD1 13 C Green LEDGreen LED+ SUYIN_100073FR012G101ZL conn@ 2 2 Place close to TCT pin 1 1K_0402_5% RJ45_MIDI3- LAN_LINK# <26> LAN_LINK# R504 0_0603_5% @ 2 C397 220P_0402_50V7K JRJ45 12 Yellow LED- 1 C408 220P_0402_50V7K 2 LANGND 1 1 C26 2 40mil 1 1 C25 C24 1000P_1206_2KV7K R505 0_0603_5% 2 2 RJ45_GND 0.1U_0402_16V4Z 4.7U_0805_10V4Z B B LAN_ACTIVITY# 1 2 C398 68P_0402_50V8J @ LAN_LINK# 1 2 C405 68P_0402_50V8J @ For EMI A A Compal Electronics, Inc. Compal Secret Data Security Classification 2008/11/03 Issued Date Deciphered Date 2009/11/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title LAN Magnetic & RJ45/RJ11 Size B Date: Document Number Rev 0.3 KBYF0 LA-5051P Tuesday, February 03, 2009 Sheet 1 27 of 46 A B C D E For Wireless LAN +3VS 1 2 +1.5VS 1 C609 4.7U_0805_10V4Z 2 1 C613 0.1U_0402_16V4Z 2 +3VS 1 C390 4.7U_0805_10V4Z 2 1 C381 0.1U_0402_16V4Z 2 1 C382 0.1U_0402_16V4Z 2 C615 For TV-Tuner/HW MPEG 0.1U_0402_16V4Z 1 1 JMINI1 <15> CLK_PCIE_MINI1# <15> CLK_PCIE_MINI1 <10> PCIE_PTX_C_IRX_N2 <10> PCIE_PTX_C_IRX_P2 <10> PCIE_ITX_C_PRX_N2 <10> PCIE_ITX_C_PRX_P2 R282 1 @ 2 0_0402_5% WLAN_BT_DATA WLAN_BT_CLK MINI1_CLKREQ# CLK_PCIE_MINI1# CLK_PCIE_MINI1 PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P2 PCIE_ITX_C_PRX_N2 PCIE_ITX_C_PRX_P2 +3VS <30> E51TXD_P80DATA 0_0402_5% R469 1 2 <30> E51RXD_P80CLK E51TXD_P80DATA_R E51RXD_P80CLK 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 GND1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND2 54 2 FOX_AS0B226-S52N-7F~N CONN@ +3VS +3VS 1 2 WL_OFF# PLT_RST# R279 1 R278 1 2 0_0603_5% 2 0_0603_5% @ ICH_SMBCLK0 ICH_SMBDATA0 C387 @ 4.7U_0805_10V4Z 2 1 C380 @ 0.1U_0402_16V4Z 2 MINI1_LED# SB_PCIE_WAKE# <29> WLAN_BT_DATA <29> WLAN_BT_CLK <15> MINI2_CLKREQ# MINI1_LED# <30> (9~16mA) <15> CLK_PCIE_MINI2# <15> CLK_PCIE_MINI2 R550 100K_0402_5% R498 1 @ 2 0_0402_5% WLAN_BT_DATA WLAN_BT_CLK MINI2_CLKREQ# CLK_PCIE_MINI2# CLK_PCIE_MINI2 @ +3VALW <10> PCIE_PTX_C_IRX_N1 <10> PCIE_PTX_C_IRX_P1 PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_P1 PCIE_ITX_C_PRX_N1 PCIE_ITX_C_PRX_P1 +3VS E51TXD_P80DATA_R E51RXD_P80CLK 1 3 5 7 9 11 13 15 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 Normal 1000 750 +3V 330 250 250 (wake enable) +1.5VS 500 375 5 (Not wake enable) 53 54 55 56 +3VS 2 1 C385 0.1U_0402_16V4Z 2 C389 @ 0.1U_0402_16V4Z +3VS +1.5VS 2 PLT_RST# R344 1 R345 1 @ @ 2 0_0603_5% 2 0_0603_5% +3VS +3VALW ICH_SMBCLK0 ICH_SMBDATA0 USB20_N5 USB20_P5 USB20_N5 <20> USB20_P5 <20> +3VS G1 G2 G3 G3 Auxiliary Power (mA) Normal 1 JMINI2 USB20_N8 <20> USB20_P8 <20> Mini Card Power Rating Peak C383 @ 4.7U_0805_10V4Z ICH_SMBCLK0 <8,9,15,20> ICH_SMBDATA0 <8,9,15,20> USB20_N8 USB20_P8 H=5.2 mm Primary Power (mA) 1 WL_OFF# <30> PLT_RST# <11,13,19,26,30> +3VS +3VALW <10> PCIE_ITX_C_PRX_N1 <10> PCIE_ITX_C_PRX_P1 Power +1.5VS +1.5VS 2 53 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 1 SB_PCIE_WAKE# <20,26> SB_PCIE_WAKE# <29> WLAN_BT_DATA <29> WLAN_BT_CLK <15> MINI1_CLKREQ# FOX_AS0B226-S99N-7F CONN@ H=9.2 mm 3 3 4 4 2008/11/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title MINI CARD (WLAN & TV-Tuner) Size B Date: Document Number Rev 0.3 KBYF0 LA-5051P Sheet Tuesday, February 03, 2009 E 28 of 46 A B C D E Bluetooth Conn. +3VALW +3VS +BT_VCC 1 C320 JP10 C334 1 3 2 10K_0402_5% 2 1 1 R202 G BT_ON# 1U_0603_10V4Z 2 AO3413_SOT23-3 Q16 USB20_P12 USB20_N12 <20> USB20_P12 <20> USB20_N12 WLAN_BT_DATA WLAN_BT_CLK <28> WLAN_BT_DATA <28> WLAN_BT_CLK D <30> BT_ON# S 0.1U_0402_16V4Z W=40mils C330 9 1 10 1 1 C327 1 GND 2 3 4 5 6 7 8 GND ACES_87213-0800G CONN@ +BT_VCC 0.1U_0402_16V4Z 1 2 3 4 5 6 7 8 C335 R452 300_0603_5% 1 D 3 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z S Q42 2N7002_SOT23 2 G 2 2 +3VALW C555 1 +USB_VCCB 80mil GND IN IN EN# OUT OUT OUT FLG 2 PORT R421 100K_0402_5% 8 7 6 5 2 U29 1 2 3 4 1 +5VALW +5VALW R422 1 USB_OC#6 2 10K_0402_5% USB_OC#6 <20> JP54 TPS2061DRG4_SO8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 4.7U_0805_10V4Z 2 1 <24,36,43> SYSON# <24,36,43> SYSON# C566 0.1U_0402_16V4Z +3VALW 1 2 R516 100K_0402_5% 3 2 +USB_VCCB +USB_VCCB W=80mils 1 + 2 2 @ 2 HS USB PORT 470P_0402_50V7K USB20_P6 1 <20> USB20_N6 USB20_N6 4 USB20_N1 USB20_P1 USB_OC#1 <20> USB_OC#1 USB_OC#1 E&T_3703-E12N-03R 2 right 1 PORT FOR JV70 +5VALW 4 2 2 USB20_P6_1 3 3 USB20_N6_1 USB20_N6_1 USB20_P6_1 WCM2012F2S-900T04_0805 @ 2 1 2 3 4 VCC DD+ GND 5 6 GND1 GND2 JP55 +3VALW <24,36,43> SYSON# R520 100K_0402_5% @ SUYIN_020173MR004S512ZL 0_0402_5% USB_OC#2 <20> USB20_N2_2 <20> USB20_P2_2 <20,24> USB_OC#2 SYSON# USB20_N2_2 USB20_P2_2 USB_OC#2 1 2 3 4 5 6 7 8 2 D21 PJDLC05_SOT23~D C608 0.1U_0402_16V4Z @ 10 4 Right Up 2008/11/03 1 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A 9 2 3 USB20_N6_1 USB20_P6_1 1 GND 2 3 4 5 6 7 8 GND E-T_3703-E08N-03R 1 4 3 JUSB3 1 <> 1 R408 <20> USB20_N1 <20> USB20_P1 0_0402_5% L58 <20> USB20_P6 USB20_N0 USB20_P0 C607 0.1U_0402_16V4Z 1 1 150U_D2_6.3VM <20> USB20_N0 <20> USB20_P0 1 2 3 4 5 6 7 8 9 10 11 12 G1 G2 1 C498 2 R407 1 C539 SYSON# B C D Title NEW CARD & USB Connector Size B Date: Document Number Rev 0.3 KBYF0 LA-5051P Sheet Tuesday, February 03, 2009 E 29 of 46 4 3 1 For EC Tools +3VALW L35 C351 2 2 0.1U_0402_16V4Z 1 2+EC_VCCA 2 FBM-L11-160808-800LMT_0603 1 C356 C357 1000P_0402_50V7K C312 1000P_0402_50V7K 1 1 2 0.1U_0402_16V4Z EC_RCIRRX 2 R286 +3VALW R287 +3VS 1 R207 1 R208 EC_SMB_CK1 2 4.7K_0402_5% EC_SMB_DA1 2 4.7K_0402_5% 1 R217 1 R216 1 R561 1 R562 1 R473 EC_SMB_CK2 2 2.2K_0402_5% EC_SMB_DA2 2 2.2K_0402_5% ESB_CLK 2 4.7K_0402_5% ESB_DATA 2 4.7K_0402_5% 2 PM_CLKRUN# 8.2K_0402_5% 2 KSO1 47K_0402_5% 2 KSO2 47K_0402_5% 1 1 <6,14,38> <6,14,38> <6> <6> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 77 78 79 80 PM_SLP_S3# PM_SLP_S5# EC_SMI# EC_I2C_INT2_R ESB_CLK ESB_DATA TH_OVERT# ENERGY_DET FAN_SPEED1 BT_ON# E51TXD_P80DATA E51RXD_P80CLK ON/OFF PWR_SUSP_LED NUM_LED# 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 B +5VS LPC debug port 2 +3VS <14> TH_OVERT# <26> ENERGY_DET <35> FAN_SPEED1 1 C353 <29> BT_ON# 15P_0402_50V8J ENE@ <32> ON/OFF <31> PWR_SUSP_LED <31> NUM_LED# JP28 A E C_CRY1 E C_CRY2 CLK_14M_SIO LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_DRQ1# PLT_RST# R521 1 R523 1 SERIRQ CLK_14M_SIO <15> 67 83 84 85 86 87 88 EC_MUTE 97 98 99 109 3S/4S# 65W/90W# EC_VLDT_EN LID_SW# 119 120 126 128 EC_SI_SPI_SO EC_SO_SPI_SI EC_SPICLK EC_SPICS#/FSEL# 73 74 89 90 91 92 93 95 121 127 EC_RCIRRX EC_I2C_INT1_R FSTCHG BATT_GRN_LED# CAPS_LED# BATT_AMB_LED# PWR_LED SYSON VR_ON AC IN EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 100 101 102 103 104 105 106 107 108 EC_RSMRST# EC_LID_OUT# EC_ON EC_SWI# EC_PWROK BKOFF#_R WL_OFF# PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 110 112 114 115 116 117 118 VGATE ENBKL EAPD EC_THERM# SUSP# PBTN_OUT# EC_PME# 122 123 V18R 124 KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 PSCLK1/GPIO4A KSI4/GPIO34 PSDAT1/GPIO4B KSI5/GPIO35 PSCLK2/GPIO4C PS2 Interface KSI6/GPIO36 PSDAT2/GPIO4D KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 SDICS#/GPXOA00 KSO4/GPIO24 SDICLK/GPXOA01 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 KSO6/GPIO26 Matrix SDIDI/GPXID0 SPI Device Interface KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 SPIDI/RD# KSO10/GPIO2A SPIDO/WR# SPI Flash ROM SPICLK/GPIO58 KSO11/GPIO2B KSO12/GPIO2C SPICS# KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F CIR_RX/GPIO40 KSO16/GPIO48 CIR_RLC_TX/GPIO41 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 GPIO BATT_LOW_LED#/GPIO54 SCL1/GPIO44 SDA1/GPIO45 SUSP_LED#/GPIO55 SM Bus SCL2/GPIO46 SYSON/GPIO56 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A GPI XCLK1 XCLK0 11 24 35 94 113 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DAC_BRIG EN_DFAN1 IR EF CALIBRATE# GND GND GND GND GND @ <20> PM_SLP_S3# <20> PM_SLP_S5# <20> EC_SMI# 68 70 71 72 LPC_DRQ1# <19> 2 0_0402_5% 2 0_0402_5% KB926QFB1_LQFP128_14X14 20mil BATT_TEMP <38> MINI1_LED# 4 2 +3VALW Ra AD_BID0 Rb 1 C308 @ R203 100K_0402_5% AD_PID0 1 R209 18K_0402_5% 2 0.1U_0402_16V4Z Rb C317 100K_0402_5% 2 0.1U_0402_16V4Z B No EC change, so Keep the board ID = 0.3 E C_CRY1 E C_CRY2 2 2 C358 15P_0402_50V8J 1 1 C359 15P_0402_50V8J X1 32.768KHZ_12.5P_MC-306 C40 @ 100P_0402_50V8J EC_SPICLK 2 1 C41 @ 100P_0402_50V8J EC_SPICS#/FSEL# 2 1 C304 100P_0402_50V8J BATT_TEMP 2 1 C303 100P_0402_50V8J BATT_OVP 2 1 C355 100P_0402_50V8J AC IN 2 1 C46 100P_0402_50V8J ON/OFF 2 1 2 A Compal Electronics, Inc. Compal Secret Data 3 1 100K_0402_5% R187 VGATE <44> ENBKL <11,14> EAPD <33> EC_THERM# <21> SUSP# <32,36,43> PBTN_OUT# <20> EC_PME# <26> 2009/11/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ACES_85201-20051 @ 1 100K_0402_5% BT_ON# R189 100K_0402_5% C354 4.7U_0805_10V4Z Deciphered Date 65W/90W# 2 R246 +3VALW LPCCLK1 <19,23> 2008/11/03 BKOFF# <11,16> Analog Board ID definition, Please see page 3. ECAGND 2 1 FBM-L11-160808-800LMT_0603 Issued Date 2 0_0402_5% C Ra WL_OFF# <28> MEDIA_LED#_OUT <31> MINI1_LED# <28> 1 100K_0402_5% 2 10K_0402_5% R552 EC_SI_SPI_SO <31> EC_SO_SPI_SI <31> EC_SPICLK <31> EC_SPICS#/FSEL# <31> EC_RSMRST# <20> EC_LID_OUT# <20> EC_ON <32> EC_SWI# <20> EC_PWROK <32> 2 +3VALW EC_MUTE <34> MEDIA_LED#_IN <31> EC_ACIN <14> BT_LED# <31> TP_CLK <31> TP_DATA <31> FSTCHG <40> BATT_GRN_LED# <31> CAPS_LED# <31> BATT_AMB_LED# <31> PWR_LED <31> SYSON <36,42> VR_ON <44> ACIN <21,36,37,40> 2 4.7K_0402_5% R524 1 DAC_BRIG <16> EN_DFAN1 <35> IREF <40> CALIBRATE# <40> L36 Security Classification 5 R551 BKOFF#_R 1 R288 VGA_PWRGD <14> 3S/4S# <40> 65W/90W# <40> EC_VLDT_EN <32> LID_SW# <32> VGATE(A32) 1 R241 VR_ON BATT_OVP <40> ADP_I <40> BT_LED# TP_CLK TP_DATA 1 @ 3S/4S# 2 +3VALW 2 TP_CLK 4.7K_0402_5% 2 TP_DATA 4.7K_0402_5% 1 R221 1 R224 DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F DA Output 2 100K_0402_5% 1 2 2 <31> EC_I2C_INT2 <31> EC_I2C_INT1 +5VS R479 0_0402_5% 1 EC_I2C_INT2_R 1EC_I2C_INT1_R R480 0_0402_5% BATT_TEMP BATT_OVP ADP_I AD_BID0 VGA_PWRGD AD_PID0 R258 1 2 <31> ESB_EC_DA2 63 64 65 66 75 76 PLT_RST# 1 <31> ESB_EC_CK2 AD ACOFF BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 @ 2 0_0402_5% INVT_PWM <16> BEEP# <33> FAN_PWM <35> ACOFF <40> ECAGND 2 1 C305 0.01U_0402_16V7K 1 IN 1 EC_SMB_CK2 R474 0_0402_5% 2 CY@ 1 EC_SMB_DA2 R475 0_0402_5% ENE@ 2 1 ESB_CLK R477 0_0402_5% 2 ENE@ 1 ESB_DATA R478 0_0402_5% PWM Output INVT_PWM_R BEEP# NC CY@ 2 PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D 21 23 26 27 2 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 12 13 37 20 38 INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 2 EC_SCI# PM_CLKRUN# <20> EC_SCI# <19> PM_CLKRUN# GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC E51RXD_P80CLK <28> E51TXD_P80DATA <28> D 1 PLT_RST# <11,13,19,26,28> PLT_RST# 2 1 R188 47K_0402_5% 2 1 C306 0.1U_0402_16V4Z <31> ESB_EC_DA2 E51RXD_P80CLK E51TXD_P80DATA 2 CLK_PCI_EC <19,23> CLK_PCI_EC C KSO[0..17] <31> 1 2 3 4 ACES_85205-0400 @ AGND 1 @ 33_0402_5% 1 2 3 4 5 7 8 10 69 C331 @ 22P_0402_50V8J R219 2 2 1 <31> ESB_EC_CK2 KSO[0..17] 1 2 3 4 R614 EC_GA20 EC_KBRST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 <20> EC_GA20 <20> EC_KBRST# <19> SERIRQ <19> LPC_FRAME# <19> LPC_AD3 <19> LPC_AD2 <19> LPC_AD1 <19> LPC_AD0 RB751V_SOD323 +3VALW U16 VCC VCC VCC VCC VCC VCC 1 1 <32> RCIRRX KSI[0..7] <31> AVCC 2 Pin 74--ENE RST(R) or CY INT(R) Pin16--ENE RST(L) or CY INT(L) R198 10K_0402_5% D11 9 22 33 96 111 125 +3VALW D Place on RAM door JP11 KSI[0..7] 1 C337 2 2 0.1U_0402_16V4Z +3VALW 0.1U_0402_16V4Z 1 2 4 LID_SW# 2 10K_0402_5% 0.1U_0402_16V4Z 1 C315 1 C307 OUT 1 1 1 R211 EC_PME# 2 10K_0402_5% ECAGND @ 1 R204 NC +3VALW 2 3 5 2 Title EC ENE KB926 Size B Date: Document Number Rev 0.3 KBYF0 LA-5051P Tuesday, February 03, 2009 Sheet 1 30 of 46 U19 U18 EC_SPICS#/FSEL# 2 4.7K_0402_5% SPI_WP# 2 4.7K_0402_5% SPI_HOLD# 1 3 7 4 CE# WP# HOLD# VSS 8 6 R269 1 5 R268 1 2 R236 1 VDD SCK SI SO 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% INT_KBD Conn. EC_SPICLK <30> EC_SO_SPI_SI <30> EC_SI_SPI_SO <30> (Right) To Media/B Conn. @ C259 100P_0402_50V8J 1 1 2 2 @ C258 100P_0402_50V8J BTN_L TP_DATA TP_CLK D8 PSOT24C-LF-T7_SOT23-3 1 28 27 KSO0 G2 KSO1 G1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 JM70 CAP Sansor right JM70 +5VS +3VS JP2 6 5 4 3 2 1 @ ESB_EC_CK2300_0402_5%1 R563 2 ESB_EC_DA2300_0402_5%1 R582 2 @ <30> ESB_EC_CK2 <30> ESB_EC_DA2 <30> EC_I2C_INT1 6 5 4 3 2 1 8 7 CAP Sansor lift for JM70 1 2 3 4 ESB_EC_CK2300_0402_5%1 R587 ESB_EC_DA2300_0402_5%1 R588 <30> ESB_EC_CK2 <30> ESB_EC_DA2 <30> EC_I2C_INT2 8 7 6 5 @ C45 100P_0402_50V8J 100P_1206_8P4C_50V8 CP4 1 8 2 7 3 6 4 5 KSI6 KSI7 KSI5 KSI4 100P_1206_8P4C_50V8 Right SW4 JM70@ EVQPLHA15_4P 3 1 4 2 2 JV70 BTN_R @ C43 100P_0402_50V8J 3 SW5 JM70@ EVQPLHA15_4P 1 4 1 2 2 Left Right SW1 JV70@ EVQPLHA15_4P 3 1 BTN_R 3 2 SW2 JV70@ EVQPLHA15_4P 1 4 2 +5VS +3VS JP6 CP3 100P_1206_8P4C_50V8 CP2 1 8 2 7 3 6 4 5 Left 4 KSO4 KSO5 KSO6 KSO7 KSO0 KSO1 KSO2 KSO3 @ C42 100P_0402_50V8J BTN_L 1 BTN_L CP1 8 7 6 5 8 7 ACES_85201-0605 C906 CONN@ 33P_0402_50V8K @ C905 33P_0402_50V8K @ For EMI 1 2 3 4 BTN_R ACES_87151-1207G ACES_88747-2601 KSI3 KSI2 KSI1 KSI0 TP_DATA <30> TP_CLK <30> 5 6 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 G13 G14 0.1U_0402_16V4Z 5 6 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 Reserved for BIOS simulator. Footprint SO8 13 14 KSO[0..17] <30> 2 JP13 KSI[0..7] <30> KSO[0..17] JKB1 (Left) 1 @ C208 +SPI_VCC EC_SPICLK EC_SO_SPI_SI EC_SI_SPI_SO 8 6 5 2 VDD SCK SI SO MX25L1005AMC-12G_SOP8 @ MX25L8005M2C-15G_SOP8 KSI[0..7] CE# WP# HOLD# VSS 5 6 R233 1 R271 1 +3VALW 1 3 7 4 2 EC_SPICS#/FSEL# SPI_WP# SPI_HOLD# +SPI_VCC <30> EC_SPICS#/FSEL# +5VS To TP/B Conn. 2 0.1U_0402_16V4Z 3 C374 1 2 0_0603_5% 5 6 1 R273 +3VALW 1 6 5 4 3 2 1 2 2 6 5 4 3 2 1 8 7 8 7 TO POWER BTN/B for JV70 ACES_85201-0605 CONN@ C907 33P_0402_50V8K C908 2 JP45 1 2 33P_0402_50V8K CAP Sansor up for JV70 G1 G2 100P_1206_8P4C_50V8 1 2 ON/OFFBTN# <32> 1 3 4 C915 0.1U_0402_16V4Z 2 ACES_88266-02001 PWR_LED# PWR_SUSP_LED# 100P_0402_50V8J 1 2 100P_0402_50V8J 2 <30> PWR_LED R264 100K_0402_5% 100P_1206_8P4C_50V8 3 5 <30> PWR_SUSP_LED Q20A R247 100K_0402_5% 4 2 2N7002DW-T/R7_SOT363-6 C57 1 2 KSO17 C56 1 KSO16 2 100P_1206_8P4C_50V8 CP6 KSO12 1 8 KSO13 2 7 KSO14 3 6 KSO15 4 5 1 6 8 7 6 5 1 1 2 3 4 2N7002DW-T/R7_SOT363-6 CP5 KSO8 KSO9 KSO10 KSO11 Need Check Q20B To LED/B Conn. +3VS JP12 7 8 7 8 1 2 3 4 5 6 1 2 3 4 5 6 MEDIA_LED#_OUT MEDIA_LED#_OUT <30> BT_LED# <30> CAPS_LED# <30> NUM_LED# <30> ACES_85201-0605 CONN@ JM70 LED1 PWR_LED# +5VALW Color Need Confirm 1 R450 2 4 453_0402_1% R451 2 240_0402_5% 3 JM70 1 LED3 JM70@ JV70 +3VS PWR_SUSP_LED# 5 +5VALW 1.HDD 1.HDD 2.BT_LED 3.CAP LED 2.BT_LED 4.NUM_LED 4.NUM_LED 3.CAP LED PWR_LED# Color Need Confirm <30> MEDIA_LED#_IN MEDIA_LED#_IN 4 P 1 PWR_SUSP_LED# B U38 2 G 2 240_0402_5% 3 A 1 Y 3 R447 A 2 4 453_0402_1% B +5VALW 1 R446 A +5VALW HT-297UD/CB _BLUE/AMB_0603 B HT-297UD/CB _BLUE/AMB_0603 SATA_LED# SATA_LED# <21> 5IN1_LED# <25> NC7SZ08P5X_NL_SC70-5 HT-297UD/CB _BLUE/AMB_0603 R449 2 240_0402_5% 3 BATT_AMB_LED# B +5VALW 2 4 453_0402_1% A +5VALW 1 R448 1 BATT_GRN_LED# LED2 BATT_AMB_LED# <30> Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification BATT_GRN_LED# <30> 2008/11/03 Deciphered Date 2009/11/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title BIOS, I/O Port & K/B Connector Size Document Number Custom Rev 0.3 KBYF0 LA-5051P Date: Tuesday, February 03, 2009 Sheet 31 of 46 A B C D E Power Button ON/OFF switch HDA MDC Conn. +3VALW TOP Side R11 R301 +3VALW 1 2 @ 10K_0603_5% 1 2 @ 10K_0603_5% 2 1 R194 100K_0402_5% D12 2 ON/OFF <30> 1 51ON# 3 <20> HDA_SYNC_MDC <20> HDA_SDIN1 <20> HDA_RST_MDC# 51ON# <37> R281 1 2 HDA_SDIN1_MDC 33_0402_5% 1 3 5 7 9 11 2 4 6 8 10 12 GND1 RES0 IAC_SDATA_OUT RES1 GND2 3.3V IAC_SYNC GND3 IAC_SDATA_IN GND4 IAC_RESET# IAC_BITCLK 1 R283 HDA_BITCLK_MDC <20> R280 0_0402_5% GND GND GND GND GND GND C329 D13 1000P_0402_50V7K 1 HDA_SNC_MDC ,HDA_SDOUT_MDC DONT Cross Mode 1 C393 Connector for MDC Rev1.5 RLZ20A_LL34 2 22P_0402_50V8J 2 2 ACES_88018-124G CONN@ 13 14 15 16 17 18 2 1 5 6 4 EMI Notice 1 JM70@ SW3 SMT1-05-A_4P 1 2 JM70 3 1U_0603_10V4Z +3VALW DAN202UT106_SC70-3 ON/OFFBTN# 2 2 0_0402_5% 1 C394 1 ON/OFFBTN# <31> ON/OFFBTN# <20> HDA_SDOUT_MDC 1 Bottom Side 1 20mil JMDC1 EC_ON For EMI D Q15 2 G 3 2 <30> EC_ON R196 S 2N7002_SOT23 10K_0402_5% ON/OFFBTN# 2 JM70 1 2 CIR 1 2 3 +3VALW D22 PJDLC05_SOT23~D @ R501 100_0805_5% JM70@ 2 1 Power ON Circuit C645 +3VALW 1 14 OUT GND RCIRRX 4 2 1 2 RCIRRX <30> C644 1000P_0402_50V7K 2 JM70@ P 14 Vs GND TSOP36236TR_4P JM70@ U21B SN74LVC14APWLE_TSSOP14 I O 4 G 3 1 R254 1 2 @ 0_0402_5% SB_PWRGD <6,20> For South Bridge 7 C349 1U_0805_25V4Z S 2 O G I 7 2 G Q19 2N7002_SOT23 U21A SN74LVC14APWLE_TSSOP14 P 2 <36> SUSP 3 1 1 2 1 +3VALW 4.7U_0805_10V4Z JM70@ R249 180K_0402_5% D IR1 3 1 +3VS 1 R253 <30> EC_PWROK 2 0_0402_5% 3 3 +3VS +3VALW Lid Switch +3VALW +3VALW 1 (Hall Effect Switch) 8 1 For +VCCP/+1.05VS JV70 @ 2 U31 JM70 VLDT_EN <36,41,42> +3VALW 0_0402_5% OUTPUT EC_VLDT_EN1 1 2 1 <30> EC_VLDT_EN C352 D16 2 1 LID_R O 12 1 R250 2 0_0402_5% RB751V_SOD323 2 VGA@ C373 U28 VGA_ON <14> 3 1 1 I A3212ELHLT-T_SOT23W-3 JV70@ A3212ELHLT-T_SOT23W-3 JM70@ R285 47K_0402_5% 2 OUTPUT U21F SN74LVC14APWLE_TSSOP14 7 2 2 P 13 G 10 G O 7 1 14 U21E SN74LVC14APWLE_TSSOP14 P 14 +3VALW 2 0.1U_0402_16V4Z 1 4 C602 0.1U_0402_16V4Z GND +3VALW VDD 0_0402_5% I 3 GND R266 1 R257 VGA@ 330K_0402_5% SUSP# 11 2 14 O VDD R267 P I G 2 9 7 0.1U_0402_16V4Z 6 O 7 C377 RB751V_SOD323 I U21D SN74LVC14APWLE_TSSOP14 G 2 5 2 U21C SN74LVC14APWLE_TSSOP14 P 10K_0402_1% D14 SUSP# 1 <30,36,43> SUSP# 14 R272 2 LID_R 1 D31 2 LID_SW# <30> CH751H-40PT_SOD323-2 C601 10P_0402_50V8J 4 SUSP# 1 R252 2 @ 0_0402_5% 0.22U_0603_16V7K 1 VGA@ 2008/11/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Power OK, Reset and RTC Circuit, TP Size B Date: Document Number Rev 0.3 KBYF0 LA-5051P Sheet Tuesday, February 03, 2009 E 32 of 46 A B C D E F G H +VDDA 1 Codec Regulator R882 10K_0402_5% 2 @ +5VS 1 1 C916 C920 1 1U_0402_6.3V4Z 2 1 2 560_0402_5% C923 1 1U_0402_6.3V4Z 2 R887 1 2 560_0402_5% Q73 2 B E 1 1 MONO_IN +VDDA 2 GND 3 SHDN 40mil OUT 5 +VDDA BYP 4 C921 2 1 4.75v 1 C919 4.7U_0805_10V4Z 0.22U_0402_6.3V6K R886 2.4K_0402_1% 2SC2411K_SOT23 HD Audio Codec D67 L76 MBK1608121YZF_0603 1 2 +3VS_DVDD RB751V_SOD323 1 2 2 IN (output = 300 mA) 10mil 0.1U_0402_16V4Z R888 10K_0402_5% 1 G9191-475T1U_SOT23-5 1U_0402_6.3V4Z 1 2 C 3 <20> SB_SPKR C922 1 2 1 PCI Beep 4.7U_0805_10V4Z C917 C918 0.1U_0402_16V4Z L69 1 2 KC FBM-L11-201209-221LMAT_0805 R885 2 0_0805_5% U58 60mil L70 1 2 KC FBM-L11-201209-221LMAT_0805 R884 10K_0402_5% EC Beep <30> BEEP# +5VAMP 2 1U_0402_6.3V4Z 2 1 1 R883 1 C924 1 +3VS C926 C925 2 +AVDD_AC97 40mil L77 1 2 FBM-L11-160808-800LMT_0603 +VDDA 0.1U_0402_16V4Z 1 1 C928 1 2 2 0.1U_0402_16V4Z 10U_0805_10V4Z 10mil C929 1 C927 1 C930 C931 +MIC2_VREFO 2 R890 1 1K_0603_1% 2 R891 1 1K_0603_1% C934 C935 LOUT2_L 39 MIC2_R LOUT2_R 41 2 JM70@4.7U_0805_6.3V6K 2 JM70@4.7U_0805_6.3V6K 23 LINE1_L SPDIFO2 45 24 LINE1_R DMIC_CLK1/2 46 18 LINE1_VREFO NC 43 DMIC_CLK3/4 44 +MIC2_VREFO <34> MIC1_L <34> MIC1_R 2 2 MIC1_C_L 4.7U_0805_6.3V6K MIC1_C_R 4.7U_0805_6.3V6K MONO_IN 20 LINE2_VREFO 19 MIC2_VREFO 21 MIC1_L 22 MIC1_R 12 PCBEEP_IN 11 RESET# BITCLK 6 SDATA_IN 8 MONO_OUT 37 CBP 29 CPVEE 31 MIC1_VREFO 28 HPOUT_R 32 CBN 30 3 <20> HDA_RST_AUDIO# 10 <20> HDA_SYNC_AUDIO 5 <20> HDA_SDOUT_AUDIO <34> LINEIN_PLUG# <34> MIC_PLUG# <34> HP_PLUG# R602 1 2 10K_0402_1% 2 1 1 2 R894 R895 <30> EAPD <34> SPDIF DMIC_DATA 20K_0402_1% 5.11K_0402_1% 1 R896 1 R897 SENSE A SENSE B 2 0_0402_5% 2 0_0402_5% 2 3 13 34 47 48 4 7 SYNC SDATA_OUT GPIO0/DMIC_DATA1/2 GPIO1/DMIC_DATA3/4 SENSE A SENSE B EAPD SPDIFO1 DVSS1 DVSS2 VREF 27 JDREF 40 HPOUT_L 33 AVSS1 AVSS2 26 42 SENSE A 4 SENSE B A Impedance PORT-A (PIN 39, 41) C936 R892 1 0_0402_5% 2 1 10P_0402_50V8J 2 For EMI HDA_BITCLK_AUDIO <20> HDA_SDIN0_AUDIO1 R893 WOOFER_MONO 1 10mil 2 33_0402_5% +MIC1_VREFO_L 1 HP_L 10mil HP_L <34> 20K PORT-B (PIN 21, 22) 10K PORT-C (PIN 23, 24) 5.1K PORT-D (PIN 35, 36) 39.2K PORT-E (PIN 14, 15) 20K PORT-F (PIN 16, 17) 10K PORT-G (PIN 43, 44) 5.1K PORT-H (PIN 45, 46) C940 2.2U_0603_6.3V4Z 1 2 3 4 1 2 3 4 G1 G2 5 6 ACES_88266-04001 CONN@ D68 SM05T1G_SOT23-3 @ R898 20K_0402_1% 3 JP41 0_0603_5% DMIC_CLK DMIC_CLK_R DMIC_DATA R482 DMIC@ DMIC_DATA_R R481 DMIC@ 0_0603_5% 1 1 C941 C942 0.1U_0402_16V4Z 10U_0805_10V4Z 2 2 1 2 2 1 C675 220P_0402_50V8J @ C676 220P_0402_50V8J @ 1 R899 2 0_0805_5% 1 R900 2 0_0805_5% 1 R901 2 0_0805_5% 1 R902 2 0_0805_5% 1 R903 2 0_0805_5% 1 R904 2 0_0805_5% 4 GND Issued Date GNDA GND 2008/11/03 Compal Electronics, Inc. 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C D GNDA Compal Secret Data Security Classification B DMIC Conn. +3VS C939 C940 must close codec HP_R <34> CODEC_VREF Digital MIC for JM70 WOOFER_MONO <34> 2 2 C939 2.2U_0603_6.3V4Z HP_R HDA_SDIN0 <20> AGND DGND 1 DMIC_CLK Codec Signals 39.2K DMIC_CLK_R INT_MIC R470 AMIC@FBM-11-160808-700T_0603 DMIC_DATA_R 1 R471 AMIC@FBM-11-160808-700T_0603 C605 AMIC@ 220P_0402_50V7K 2 AMP_RIGHT <34> DEL SPDIF_HDMI ALC272-GR_LQFP48_7X7 Sense Pin AMP_LEFT <34> 2 MIC2_L 17 2 MIC1_L 1 C937 MIC1_R 1 C938 1 16 2 1 1 9 MIC2_C_L 4.7U_0805_6.3V6K MIC2_C_R 4.7U_0805_6.3V6K 1 1 AMP_RIGHT 2 C933 36 LINE2_R 3 C932 LOUT_R LINE2_L 15 1 <34> LINE_R 1K_0402_1% LINE_L JM70@ LINE_R JM70@ LOUT1_L AMP_LEFT 2 R472 2.2K_0402_5% AMIC@ 15mil For EMI 35 14 1 <34> LINE_L 2INT_MIC_R 1 Analog MIC for JV70 2 R889 INT_MIC DVDD AVDD1 U59 0.1U_0402_16V4Z 10U_0805_10V4Z 2 2 DVDD_IO 2 0.1U_0402_16V4Z 38 2 AVDD2 10U_0805_10V4Z 2 25 2 E F Title HD Audio Codec ALC268 Size B Document Number Rev 0.3 KBYF0 LA-5051P Date: Tuesday, February 03, 2009 G Sheet 33 H of 46 A B C D E Int. Speaker Conn. +5VAMP 20mil C944 0.1U_0402_16V4Z +5VAMP D70 +5VAMP D71 @ LIN+ <33> AMP_LEFT 2 1 2 1 2 AMP_C_LEFT 5 C948 R910 0_0402_5% 0.47U_0603_16V4Z LIN- 18 SPKR+ ROUT- 14 SPKR- LOUT+ 4 SPKL+ LOUT- 8 SPKL- 2N7002_SOT23 R909 100K_0402_5% R908 @ 100K_0402_5% LINE Out/Headphone Out 2007/12/07 S/PDIF Out JACK 20mil C759 2 2 D60 C760 10 SHUTDOWN HPOUT_R_1 1 2 56.2_0603_1% L62 HPOUT_L_1 1 2 56.2_0603_1% L63 1 R633 1 R634 2 HPOUT_R_2 2 FBM-11-160808-700T_0603 HPOUT_L_2 2 FBM-11-160808-700T_0603 SM05_SOT23 3 1 HP_L <33> HP_L 2 21 20 13 11 1 Check with EC HP_R <33> HP_R C950 0.47U_0603_16V4Z TPA6017A2PWP_TSSOP20 D65 SPDIF_PLUG# +5VSPDIF @ 2 PJDLC05_SOT23~D JHP1 1 1 2 2 2 BYPASS Keep 10 mil width 1 19 1 @ 1 2 3 C949 0.1U_0402_16V4Z 12 GND5 GND1 GND2 GND3 GND4 EC_MUTE S 2N7002_SOT23 330P_0402_50V7K 330P_0402_50V7K 1 1 <30> EC_MUTE D HP_PLUG# <33> +5VSPDIF ROUT+ NC 1 1 1 1 1 GAIN1 1 2 3 3 1 1 GAIN1 S 2 G Q38 3 2 9 1 2 C947 0.47U_0603_16V4Z GAIN0 2 G Q40 Q39 AO3413_SOT23-3 D 1 RIN- 2 2 1 2 1 2AMP_C_RIGHT 17 C946 R907 0_0402_5% 0.47U_0603_16V4Z GAIN0 1 <33> AMP_RIGHT 3 16 15 6 VDD PVDD1 PVDD2 RIN+ SPDIF_PLUG# 2 @ D 7 1 2 C945 0.47U_0603_16V4Z R906 100K_0402_5% S R905 100K_0402_5% G U60 5 6 G1 G2 ACES_88266-04001 CONN@ HP_PLUG# R626 100K_0402_5% R625 100K_0402_5% 2 2 +5VAMP 1 2 3 4 @ 2 JONS 1 2 3 4 2 2 SPK_L+ SPK_LSPK_R+ SPK_R2 2 0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5% 2 2 2 2 SM05_SOT23 3 10U_0805_10V4Z 1 1 1 1 1 1 1 1 R619 R618 R617 R616 SM05_SOT23 3 C943 JP3 SPKL+ SPKLSPKR+ SPKR- 1 JONS 3 3 4 4 5 5 8 8 9 9 10 10 DRIVE IC GND GND SPDIF <33> SPDIF 6 7 SINGA_2SJ-A373-H01 CONN@ 1 C762 JM70 2 100P_0402_50V8J LINE-IN JACK @ PJDLC05_SOT23~D D61 1 1 2 4.7K_0402_1% JM70@ Vo+ 5 IN+ Vo- 8 GND 7 JM70@ 2 0.068U_0603_16V7K 2 BYPASS EC_MUTE <30> 30mil 1 2 3 4 G1 G2 @ <33> MIC1_R <33> MIC1_L 4 D69 1 R911 1 R912 R645 2.2K_0402_5% MIC1_R_L 2 1K_0603_1% MIC1_L_L 2 1K_0603_1% R647 2.2K_0402_5% 1 B C 2 SM05_SOT23 3 1 @ MIC JACK D72 @ 1 2 PJDLC05_SOT23~D 1 L66 2 JMIC1 MIC_PLUG# 5 <33> MIC_PLUG# 4 2 FBM-11-160808-700T_0603 2 FBM-11-160808-700T_0603 1 L65 MIC2_R_1 3 6 2 1 MIC2_L_1 1 C771 220P_0402_50V7K 4 SINGA_2SJ-S351-015 2 Compal Electronics, Inc. 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A SINGA_2SJ-S351-015 JM70@ 3 Compal Secret Data 2008/11/03 Issued Date 3 6 2 1 D29 RB751V-40TE17_SOD323-2 RB751V-40TE17_SOD323-2 C770 220P_0402_50V7K Security Classification D66 +MIC1_VREFO_L D28 1 2 ACES_88266-02001 CONN@ C606 2.2U_0603_6.3V4Z JM70@ +MIC1_VREFO_L Left MIC2_R_1 MIC2_L_1 JP17 WOOFER+ W OOFER- APA3011XA-TRL_MSOP8 JM70@ 2 3 2 IN- WOOFER_IN+ 3 EC_MUTE 2 WOOFER_IN- 4 C651 1 1 C764 220P_0402_50V7K 2 JM70@ 1 JM70@ VDD SHUTDOWN# 1 2 C654 0.33U_0603_16V4Z JM70@ C763 220P_0402_50V7K JM70@ 2 +5VAMP 1 WOOFER_MONO 1 R467 100K_0402_5% 1 2 U43 6 R518 L44 1.8K_0402_5% 2 <33> WOOFER_MONO 1K_0402_1% R517 1 2 LINE_R_R 2 FBM-11-160808-700T_0603 LINE_L_R 2 FBM-11-160808-700T_0603 1 1 L64 1 1 +5VAMP 1 2 C656 JM70@ 0.01U_0603_50V7K 1 2 Fc(high)= 482Hz JM70@ 2 JM70@ 1 JM70@ LINE_L <33> LINE_L 2 R519 LINE_R <33> LINE_R Fc(low)= 2KHz SM05_SOT23 3 JM70 C652 0.1U_0603_25V7K 1 JM70@ 5 4 Gain = 5.1dB(BTL Mode) 1 10U_0805_10V4Z JM70@ 2 2 JLINE1 LINEIN_PLUG# <33> LINEIN_PLUG# 3 C671 1 3 +5VAMP 1 2 D Title Amplifier & Audio Jack Size B Date: Document Number Rev 0.3 KBYF0 LA-5051P Sheet Tuesday, February 03, 2009 E 34 of 46 @ H29 H_3P0 @ @ 1 @ H8 H_3P0 H9 H_3P0 @ 1 H7 H_3P0 1 @ 1 1 @ H6 H_3P0 @ H42 H_3P0 @ 1 @ H12 H_3P0 H5 H_3P0 1 H11 H_3P0 @ 1 @ H4 H_3P0 1 H3 H_3P0 1 1 1 @ 1 1 H2 H_3P0 H10 H_3P0 FAN1 Conn @ +5VS +5VS 10U_0805_10V4Z 2 1 C435 1 H40 H_3P2 1 C425 1000P_0402_50V7K 1 2 H41 H_3P2 @ H35 H_3P2 @ H38 H_3P2 @ @ H27 H_3P2 @ 1 H25 H_3P2 1 @ 1 1 @ H32 H_3P2 @ H39 H_3P2 @ 1 +3VS @ H26 H_3P2 1 0.047U_0402_16V7K @ H23 H_3P2 1 Change to SC1BAS16000 2 BAS16_SOT23-3 C429 10U_0805_10V4Z 1 2 1 D20 1 G990P11U_SOP8 H18 H_3P2 1 H17 H_3P2 1 D19 1SS355_SOD323-2 8 7 6 5 2 GND GND GND GND 1 C769 VEN VIN VO VSET @ R310 10K_0402_5% 40mil 2 <30> FAN_SPEED1 1 JP32 +VCC_FAN1 R346 1 2 0_0603_5% 1 2 3 ACES_85205-03001 CONN@ C411 1000P_0402_50V7K 2 @ R355 1 2 0_0603_5% R355 close to JP32 @ H43 H_10P0N @ 1 @ @ @ FD2 FD3 @ FIDUCIAL_C40M80 FD5 FD6 @ FIDUCIAL_C40M80 1 FIDUCIAL_C40M80 1 @ FD4 @ 1 1 H22 H_4P2 H28 H_4P1X4P6N FD1 FIDUCIAL_C40M80 @ FIDUCIAL_C40M80 @ FIDUCIAL_C40M80 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date @ 1 1 H31 H_4P1N 1 @ H21 H_4P2 1 H20 H_4P2 1 1 H19 H_4P2 1 <30> FAN_PWM 1 330_0402_5% 1 +VCC_FAN1 EN_DFAN1 1 R815 2 EN_FAN1_R 1 2 3 4 1 U26 2 <30> EN_DFAN1 H1 H_3P0 2008/11/03 Deciphered Date 2009/11/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title FAN & Screw Hole Size B Date: Document Number Rev 0.3 KBYF0 LA-5051P Tuesday, February 03, 2009 Sheet 35 of 46 A B C D E +5VALW TO +5VS +5VALW +5VALW 2 +5VS R177 100K_0402_5% U15 1 10U_0805_10V4Z 2 2 1U_0603_10V4Z 10U_0805_10V4Z 2 2 10U_0805_10V4Z R193 470_0603_5% SYSON# <24,29,43> SYSON# SYSON <30,42> SYSON 5VS_GATE SUSP 3 2 SUSP G Q13 2N7002_SOT23 1 R171 100K_0402_5% 2 D S 1 2 1 2 1 R212 200K_0402_5% S Q11 2N7002_SOT23 1 D +VSB D 2 G 1 1 C314 1 1 2 C318 AO4468_SO8 1 1 C310 1 2 3 4 S S S G 3 1 D D D D 1 C309 8 7 6 5 C328 R541 @ S 2 0.1U_0603_25V7K +5VALW 1 3 2 Q14G 2N7002_SOT23 1 D R276 100K_0402_5% <32> SUSP SUSP Q24 2N7002_SOT23 1 R275 10K_0402_5% +1.2VALW +3VS S +1.2V_HT 2 +3VALW D 2 G <30,32,43> SUSP# +3VALW TO +3VS 1 3 Q43 S 2N7002_SOT23 @ 1 2 G 3 ACIN <21,30,37,40> ACIN 2 1M_0402_5% 2 10U_0805_10V4Z 1 R10 470_0603_5% SI4856ADY_SO810U_0805_10V4Z 2 2 1U_0603_10V4Z AO4430 +5VALW D 2 SUSP G Q25 2N7002_SOT23 +VSB +1.8V to +1.8VS +1.8V C15 1.2V_GATE 2 1 R306 150K_0402_5% VLDT_EN# 2 Q27G 2N7002_SOT23 +1.8VS S 2 VLDT_EN# G Q26 2N7002_SOT23 R191 100K_0402_5% D S VLDT_EN# R543 1 2 C407 0.1U_0603_25V7K C285 1 1 R163 470_0603_5% 1 R186 10K_0402_5% D ACIN 2 G Q58 S 2N7002_SOT23 1 1 AO4430 1 C270 10U_0805_10V4Z 2 2 1U_0603_10V4Z SI4856ADY_SO8 10U_0805_10V4Z 2 2 10U_0805_10V4Z 1 2 C269 Q12 2N7002_SOT23 2 1 1M_0402_5% 1 2 3 4 S S S G S 3 C286 D D D D D 2 G <32,41,42> VLDT_EN U11 8 7 6 5 1 3 S 2 1 1 D 5VS_GATE 1 1 2 3 4 C16 S S S G 2 C14 D D D D 1 10U_0805_10V4Z 2 2 1U_0603_10V4Z 10U_0805_10V4Z 2 2 10U_0805_10V4Z R277 470_0603_5% 3 1 3 C388 2 AO4468_SO8 1 2 2 C391 1 1 8 7 6 5 1 C376 U1 1 2 3 4 S S S G 3 1 D D D D 1 1 C375 8 7 6 5 1 U22 2 D 3 SUSP 3 S 1 2 2 1 R424 510K_0402_5% 1 +VSB 1.8VS_GATE D 2 SUSP G Q37 2N7002_SOT23 3 C564 R542 2 G 2 0.1U_0603_25V7K 1 3 Q45 S 2N7002_SOT23 1 1M_0402_5% ACIN D 2 G +2.5VS +1.1VS +0.9V 2 2 2 1 1 1 D 1 D 1 D S 2VLDT_EN# G Q57 2N7002_SOT23 S 2 SYSON# G Q10 2N7002_SOT23 S 3 2 SUSP G Q44 2N7002_SOT23 3 S 3 2 SUSP G Q22 2N7002_SOT23 3 S 4 1 1 R173 470_0603_5% 1 R170 470_0603_5% 1 R544 470_0603_5% D D 3 4 R423 470_0603_5% 1 R270 470_0603_5% +1.8V 2 +1.5VS 2 3 Q51 S 2N7002_SOT23 2 SYSON# G Q9 2N7002_SOT23 2008/11/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title DC Interface Size B Date: Document Number Rev 0.3 KBYF0 LA-5051P Sheet Tuesday, February 03, 2009 E 36 of 46 A B C D 1 1 1 VIN @ PR2 10K_0402_5% PR3 84.5K_0402_1% 2 2 1 2 1 2 8 2 PR8 10K_0402_5% PC6 1000P_0402_50V7K RTCVREF 2 Vin Dectector Min. H-->L 16.976V L-->H 17.430V + PBJ1 P 1 RTC Battery 2 2 2 10K_0402_5% 2 PJP1 3 - 0 PU1A LM358DT_SO8 PD3 RLZ4.3B_LL34 PR5 22K_0402_5% 1 2 PC5 0.1U_0603_25V7K 2 1 PR7 1 3 + G 2 PR4 0_0402_5% 1 1 2 ACIN <21,30,36,40> PC4 100P_0402_50V8J PR197 10K_0402_1% 1 2 1 4 1 PC3 1000P_0402_50V7K 2 PC2 100P_0402_50V8J 2 PC1 1000P_0402_50V7K 2 2 1 1 1 2 1 SINGA_2DC-G756I200 G G VS VIN PR6 20K_0402_1% VIN 2 1 PL1 SMB3025500YA_2P 1 DC_IN_S1 PR1 1M_0402_1% 1 2 +RTCBATT 1 +RTCBATT Typ 17.525V 17.901V Max. 17.728V 18.384V @ MAXEL_ML1220T10 SP093MX0000 PJ2 VIN 2 +3VALWP 2 @ 2 PJ3 1 1 +3VALW 2 +1.8VP JUMP_43X118 2 1 1 +1.8V @ JUMP_43X118 (8.61A,400mils ,Via NO.= 20) (12.06A,480mils ,Via NO.=24) PD4 RLS4148_LL34-2 1 PJ4 PQ1 TP0610K-T1-E3_SOT23-3 PR9 68_1206_5% N1 3 VS 2 +VSBP PC8 0.1U_0603_25V7K 1 +VSB 2 1 GND 2 2 2 1 1 +1.1VS (1.9A,80mils ,Via NO.=4) PJ9 1 1 +1.2VALW +2.5VSP 2 2 1 1 +2.5VS @ JUMP_43X118 PC172 1 (1.0A,40mils ,Via NO.=2) 2 0.1U_0402_25V6 PJ11 1 1 +NB_CORE +1.5VSP 2 2 1 1 +1.5VS @ JUMP_43X118 (8.8A,360mils ,Via NO.=18) (1.0A,40mils ,Via NO.=2) 2 N2 2 PC10 1 4 2 PC9 10U_0805_10V4Z 2 +0.9V 1 IN 1 @ JUMP_43X118 @ JUMP_43X118 1U_0805_25V4Z Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/11/03 Deciphered Date 2009/11/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A +1.1VSP PJ10 2 +NB_COREP G920AT24U_SOT89-3 OUT 1 PJ7 1 (3.94A,160mils ,Via NO.=8) 1 2 4 2 @ JUMP_43X118 PU2 3 2 (2A,80mils ,Via NO.= 4) PJ8 2 +1.2VALWP 2 PR13 22K_0402_1% 3.3V 2 +0.9VP @ JUMP_43X79 (120mA,40mils ,Via NO.= 2) 2 2 1 1 1 2 PC7 0.22U_0603_25V7K 1 PR16 560_0603_5% 1 2 +5VALW PJ6 1 PR14 200_0603_5% PR15 560_0603_5% 1 2 1 (8.61A,400mils ,Via NO.= 20) RTCVREF +CHGRTC PJ5 1 JUMP_43X118 @ JUMP_43X39 PR12 100K_0402_1% <32> 51ON# 2 3 @ PR10 68_1206_5% 2 PR11 200_0603_5% 1 2 1 1 PD5 RLS4148_LL34-2 CHGRTCP 2 +5VALWP 1 2 2 BATT+ 3 B C Title DCIN & DETECTOR Size Document Number R ev 0.3 KBKC0_KBYF0 Date: Tuesday, February 03, 2009 D Sheet 37 of 46 A B C D PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 56 degree C VL VL VL 2 VMB SUYIN_200275MR007G161ZL 1 PR17 47K_0402_1% PR19 8.87K_0402_1% 1 2 8 PC13 0.01U_0402_25V7K 3 TM_REF1 - O 1 1 2 RLS4148_LL34-2 3 1 VL PR23 100K_0402_1% PR25 100K_0402_1% 2 2 PR26 1K_0402_1% 2 1 1 2 PC15 1000P_0402_50V7K 1 2 1 +3VALWP PR22 10.7K_0402_1% 2 1 PR24 6.49K_0402_1% 2 1 1 PC14 0.22U_0603_16V7K 2 2 PR21 100_0402_1% 1 PR20 100_0402_1% PD6 2 1 LM393DG_SO8 4 2 PQ2 DTC115EUA_SC70-3 PU3A + P 2 PC12 1000P_0402_50V7K 1 MAINPWON <6,39> 1 PR18 47K_0402_1% 1 2 2 PC11 0.1U_0603_25V7K 1 PH1 100K_0603_1%_TH11-4H104FT G 2 EC_SMCA EC_SMDA BATT+ 2 1 2 3 4 5 6 7 8 9 1 PL2 SMB3025500YA_2P 1 2 PJP2 1 1 2 2 BATT_TEMP <30> PH2 near main Battery CONN : BAT. thermal protection at 92 degree C Recovery at 56 degree C EC_SMB_CK1 <6,14,30> EC_SMB_DA1 <6,14,30> 2 VL @ PR27 100K_0402_1% 1 @ PR28 100K_0402_1% 1 2 PQ3 TP0610K-T1-E3_SOT23-3 @ PH2 100K_0603_1%_TH11-4H104FT 2 8 + 6 - O PR32 @ 12K_0402_1% @ PD7 2 7 1 3 RLS4148_LL34-2 LM393DG_SO8 2 2 @ 4 @ PC18 0.22U_0603_16V7K PU3B P 5 G 1 TM_REF1 1 1 1 2 2 2 @ @ PR30 12K_0402_1% 1 2 2 VL PC16 0.22U_0603_25V7K PR31 22K_0402_1% 1 2 2 1 PR29 100K_0402_1% 3 VL +VSBP 1 PC17 0.1U_0603_25V7K 3 B+ 1 VL 1 PR34 0_0402_5% 2 D 3 1 S PQ4 SSM3K7002F_SC59-3 2 G 2 1 <39,41> POK PC19 0.1U_0402_16V7K 1 PR33 100K_0402_1% @ 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/11/03 Deciphered Date 2009/11/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title BATTERY CONN / OTP Size Document Number R ev 0.3 KBKC0_KBYF0 Date: Tuesday, February 03, 2009 D Sheet 38 of 46 5 4 3 ISL6237_B+ 3 2 1 BST5A 2 PR39 2.2_0603_5% PC32 PC31 0.1U_0603_25V7K LX3 PHASE2 PHASE1 16 0.1U_0603_25V7K LX5 LGATE1 18 DL5 4 3 2 1 25 PQ8 AO4712_SO8 1 DL3 23 FB3 VL @ LGATE2 30 OUT2 32 REFIN2 PGND 22 OUT1 10 FB1 11 BYP 9 SKIP 29 2VREF_ISL6237 1 2 1 PC25 2200P_0402_50V7K 2 1 PR41 61.9K_0402_1% 2 DH5 17 1 + PC35 330U_6.3V_M 1 15 BOOT1 C 2 PR43 10K_0402_1% 1 2 UGATE1 PL3 10UH_MSCDRI-104A-100M-E_4.6A_20% 2 1 PR37 4.7_1206_5% 2 1 19 5 6 7 8 7 PC29 1U_0603_10V6K 1 2 PVCC 2 BOOT2 VCC UGATE2 24 LDO 3 6 VIN 26 D +5VALWP 1 1 4 DH3 PR38 1 BST3A 2.2_0603_5% 4.7U_0805_6.3V6K PC28 2 1 1U_0603_10V6K PC27 1 2 2 1 2 2 PQ7 AO4712_SO8 TP PC24 4.7U_1206_25V6K 2 1 5 6 7 8 8 7 6 5 1 2 3 8 7 6 5 PU4 33 PQ6 AO4466_SO8 4 PC34 680P_0603_50V7K 2 1 2 1 PR42 10K_0402_1% C PC26 0.1U_0603_25V7K 1 2 3 PR36 4.7_1206_5% 2 1 PC33 680P_0603_50V7K 2 1 2 1 + PR40 0_0402_5% 1 VL PQ5 AO4466_SO8 4 PL4 10UH_MSCDRI-104A-100M-E_4.6A_20% 1 2 +3VALWP PC23 4.7U_1206_25V6K 2 1 PR35 0_0805_5% 1 2 PC22 2200P_0402_50V7K 2 1 PC171 0.1U_0402_25V6 PC21 4.7U_1206_25V6K 2 1 2 1 D PC20 4.7U_1206_25V6K 2 1 PL15 FBMA-L11-322513-151LMA50T_1210 1 2 2 1 ISL6237_B+ B+ PC30 330U_6.3V_M 2 FB5 REF PC36 0.22U_0603_10V7K 8 LDOREFIN @ PR44 2 PR45 1 20 28 EN_LDO POK1 13 EN1 ILIM1 12 POK <38,41> PR48 ILM1 2 330K_0402_1% 1 B GND 21 TON ILIM2 31 ILIM2 2 1 330K_0402_1% ISL6237IRZ-T_QFN32_5X5 1 2 NC 5 EN2 PR53 0_0402_5% +5VALWP Ipeak=8.444A ; Imax=5.91A Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Vlimit=(5E-06 * 330K)/10=165mV Ilimit=165mV/18m ~ 165mV/15m =9.167A ~ 11A Iocp=Ilimit+Delta I/2 =9.7285A ~ 11.5615A Delta I=1.123A (Freq=400KHz) 2VREF_ISL6237 2 2 1 1 2 2VREF_ISL6237 1 2 1 3 2 PC38 0.047U_0402_16V7K @ PR55 47K_0402_5% 1 2 PR51 0_0402_5% @ PR50 0_0402_5% 1 2 PR52 806K_0603_1% 2 PR54 0_0402_5% 2 1 POK2 PC163 1U_0603_6.3V6M 2 1 27 VL <6,38> MAINPWON NC VL PR49 2 PD12 1SS355_SOD323-2 14 PC39 0.047U_0402_16V7K 2 1 1 B 4 PC37 0.22U_0603_25V7K PR46 100K_0402_1% 1 2 PR47 200K_0402_5% 1 2 PD8 RLZ5.1B_LL34 1 2 VS 0_0402_5% 1 0_0402_5% 2 @ PQ38 TP0610K-T1-E3_SOT23-3 5 4 A 1 A +3.3VALWP Ipeak=8.444A ; Imax=5.91A Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Vlimit=(5E-06 * 330K)/10=165mV Ilimit=165mV/18m ~ 165mV/15m =9.167A ~ 11A Iocp=Ilimit+Delta I/2 =9.721A ~ 11.554A Delta I=1.108A (Freq=300KHz) Compal Electronics, Inc. Compal Secret Data Security Classification 2008/11/03 Issued Date Deciphered Date 2009/11/03 +5V/+3V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 Title 2 Size Document Number Custom Rev 0.3 KBKC0_KBYF0 Date: Tuesday, February 03, 2009 Sheet 1 39 of 46 A B C B+ PQ10 AO4407A_SO8 LX_CHG PD10 2 6 ACSET REGN 1 OVPSET Fsw : 300KHz 8 OVPSET 9 AGND 21 CELLS 20 CELLS 2 2 1 2 2 2 1 3 1 2 PQ19 RHU002N06_SOT323-3 2 G 1 1 PR83 100K_0402_1% PR85 221K_0402_1% CHGEN# 1 2 D @ 2 VADJ D 3 PR82 1 2 0_0402_5% PQ17 SI2301BDS-T1-E3_SOT23-3 2 PR84 100K_0402_1% <30> Calibrate# 1 1 PR189 4.3K_0402_5% 3 1 1 PR66 100K_0402_1% PQ16 SSM3K7002F_SC59-3 @ 24751_VREF REGN 3 6 S PR80 887K_0402_1% 1 5 - D 2 G 24751_VREF 2 + 0 ACGOOD# @ PR188 0_0402_5% 1 2 1 7 3 ACIN <21,30,36,37> ADP_I <30> 2 1 PU1B @ PR75 100K_0402_1% PC64 @0.01U_0402_25V7K 1 2 PR74 100K_0402_1% VMB 2 1 PR81 105K_0402_1% 1 PR79 10K_0402_1% 1 2 2 PR76 10_0603_5% 1 2 24751_VREF IREF <30> 1 15 1 IADAPT 2 1 17.4K_0402_1% 1 VS PQ40 SSM3K7002F_SC59-3 1 3 2 2 1 SRSET PC67 0.01U_0402_25V7K S LM358DT_SO8 D 16 D 1 2 PQ39 SSM3K7002F_SC59-3 PC66 0.01U_0402_25V7K 3 S 3 1 D PR73 SRSET BATDRV PC65 100P_0402_50V8J D PC60 @0.1U_0603_25V7K CC=0.2~4.26A Iref=0.77448*Icharge Iref=0.155~3.3V ICHG setting PQ14_GATE 2 G PC59 0.1U_0603_25V7K PC63 0.1U_0603_25V7K G PQ37 SSM3K7002F_SC59-3 2 65W/90W# G 29 S <30> BATT_OVP TP ACGOOD 14 2 BATT-OVP=0.111*BATT+ 17 BQ24751ARHDR_QFN28_5X5 8 LI-4S :18V----BATT-OVP=1.998V SE_CHG- BAT 2 /BATDRV 2 G PR195 340K_0402_1% 2 1 0.1U_0402_16V7K SE_CHG+ VADJ 24751_VREF PR194 100K_0402_1% 2 1 PC168 ACOFF 1 2 19 18 2 PR196 200K_0402_1% 2 1 24751_VREF PR183 100K_0402_1% 12 13 1 PR72 100K_0402_1% ACSET VADJ ACGOOD# 3 SRP SRN 1 ACSET RTCVREF LI-3S :13.5V----BATT-OVP=1.5V VDAC PQ14 SI2301BDS-T1-E3_SOT23-3 2 PC62 0.1U_0603_25V7K Cells selector 11 2 1 2 3S/4S# <30> G PQ15 SSM3K7002F_SC59-3 VREF 2 ACOFF <30> 2 1 2 1 PR78 PR77 499K_0402_1% 340K_0402_1% PQ14_GATE PR63 64.9K_0402_1% 1 2 PC58 0.1U_0402_16V7K 1 2 2 3 PC61 1U_0603_10V6K PR71 100K_0402_1% 1 3 LEARN 3 1 2 1 2 24751_VREF 10 1 1 1 D <30> 22 2 24751_VREF @ PR70 0_0402_5% CELLS 4 PGND PR68 54.9K_0402_1% P 4 Cell G 3 Cell VREF 4 2 GND PR69 47K_0402_1% 24751_VREF 23 BATT+ S 2 24751_VREF S DL_CHG LODRV 2 1 2 2 CELLS 2 2 7 ACOP PC57 0.47U_0603_16V7K 1 Input UVP : 17.26V PQ13 AO4466_SO8 4 3 2 1 2 1 PR67 340K_0402_1% Input OVP : 22.3V PC55 1U_0603_10V6K 2 65W adapter Iadapter=(Vacset/Vvdac)*(0.1/PR48)=2.90A 1 24 1 Iadapter=(Vacset/Vvdac)*(0.1/PR48)=4.04A PR65 4.7_1206_5% 2 ACSET 2 1 PR64 54.9K_0402_1% 90W adapter 1 PC51 RLS4148_LL34-2 0.1U_0603_25V7K 1 REGN 2 Icharge=(Vsrset/Vvdac)*(0.1/PR36) 1 PR62 PL5 0.02_2512_1% 10UH_PCMB104T-100MS_6A_20% 1 2 1 4 1 25 3 2 1 PH 2 ACDRV ACDET PC53 10U_1206_25V6M 4 5 5 6 7 8 DH_CHG 1 26 2 HIDRV 4 1 ACN ACP 3 2 1 2 ACDRV RLZ24B_LL34 ACDET 2 3 PQ12 AO4407A_SO8 PQ11 AO4466_SO8 4 1 /BATDRV PC52 10U_1206_25V6M PR61 2.2_0603_5% 1 2 PR57 100K_0402_1% 2 BTST 1 27 PC45 2200P_0402_25V7K BTST PC49 @0.1U_0603_25V7K PC40 0.01U_0402_25V7K PC169 10U_1206_25V6M 2 1 PC48 0.1U_0603_25V7K 1 2 1 PVCC PC43 4.7U_1206_25V6K 2 28 1 CHGEN 1 PVCC PU5 1 A CN ACP 2 CHG_B+ 1 1 PC56 680P_0603_50V8J 1 @ PD13 1 2 JUMP_43X118 PC42 4.7U_1206_25V6K @ 5 6 7 8 3 2 4 2 PC47 0.1U_0603_25V7K 2 1 4 PC46 0.1U_0402_16V7K 1 2 2 2 2 1 PR60 340K_0402_1% PC50 2.2U_0805_25V6K PJ13 1 1 2 PC44 0.01U_0402_25V7K 2 1 1 2 PR182 3.3_1210_5% PR56 0.015_2512_1% 8 7 6 5 CHGEN# PR58 3.3_1210_5% 1 1 2 3 PR59 100K_0402_1% 1 2 3 4 1 8 7 6 5 PC174 0.1U_0402_25V6 2 1 5 6 7 8 PQ9 AO4407A_SO8 VIN D PC173 0.1U_0402_25V6 2 1 PQ18 SSM3K7002F_SC59-3 2 G <30> FSTCHG 4 S S PR80 PR85 4.0V L @ 0 4.1V L 887K 221K 4.2V H 887K 221K Charger ADJ Calibrate# CP setting A B Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/11/03 Deciphered Date 2009/11/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C Title CHARGER Size Document Number R ev 0.3 KBKC0_KBYF0 Date: Tuesday, February 03, 2009 D Sheet 40 of 46 A B C D 1 1 2 PR89 1 1 1 3 2.2_0603_1% D S 2 + PC164 220U_25V_M +5VALW ISL6228_B+ PC170 0.1U_0402_25V6 1 2 2.2_0603_1% PC70 0.1U_0603_25V7K 2 PR92 PC71 0.1U_0603_25V7K 2 PR93 1 2 8 1 2 2 3 4 5 PR95 18.2K_0402_1% 1 1 PC75 1000P_0402_50V7K FB2 27 VIN2 VIN1 2 VO1 FSET2 28 VCC2 PGOOD2 VCC1 FB1 FSET1 29 PR99 2 ISL6228_B+ GND_T PR98 90.9K_0402_1% 1 1 2 FB1_NB_COREP 1 PR94 22K_0402_1% 6 7 PR97 102K_0402_1% PGOOD1 2 2 PC74 1000P_0402_50V7K 2 PR96 3.3K_0402_5% 2 1 PC76 1000P_0402_25V8J 2 1 1 1 10_0603_1% 2 10_0603_1% 1 ISL6228_B+ 1 @ PC72 0.1U_0402_16V7K S 2 @ PQ20 SSM3K7002F_SC59-3 1 2 G 1 1 2 2 @ PC73 0.01U_0402_25V7K 1 D 2 1 <11> POWER_SEL @ PQ21 SSM3K7002F_SC59-3 2 G 3 @ PR91 0_0402_5% 1 2 2 2 @ PR90 0_0402_5% 1 PR88 2 +5VALW @ PR87 10K_0402_1% 1 2 @ PR86 12K_0402_1% PL14 HCB4532KF-800T90_1812 1 2 B+ 1 1.1V PC69 1U_0402_6.3V6K 2 LOW PC68 1U_0402_6.3V6K +5VALW 2 1.0V 1 FB1_NB_COREP HIGH 1 POWER_SEL PR100 66.5K_0402_1% PR101 PC77 3.3K_0402_5% 1000P_0402_25V8J 2 1 1 2 1 7.87K_0402_1% ISL6228_B+ PR102 OCSET1 VO2 1 26 11 EN1 PU6 OCSET2 25 EN2 24 ISL6228_B+ PHASE2 1 1 2 0.1U_0402_16V7K PC92 1U_0402_6.3V6K LG_NB_COREP 3 1.8UH_1164AY-1R8N=P3_9.5A_30% 1 PC87 330U_6.3V_M 2 2 2.2_0603_5% 1 BST_1.2V 1 +1.2VALWP PL8 + 2 PC88 680P_0603_50V8J 2 2 +5VALW 1 LG_1.2V 1.1VP Ipeak=8.9A ; Imax=6.23A DCR=6m ohm (max) Rocset=(Iocp*DCR)/10E-06=7.68K ohm Iocp=9.846A(1.3*DCR) Csen=L/(Rocset*DCR)=0.022uF <38,39> POK 2 1.2VP Ipeak=3.94A ; Imax=2.758A DCR=10m ohm (max) Rocset=(Iocp*DCR)/10E-06=6.65K ohm Iocp=5.542A(1.2*DCR) Csen=L/(Rocset*DCR)=0.027uF 1.2V_EN 1 2 PR114 0_0402_5% 1 1 2 PC90 0.1U_0402_10V7K PC91 1U_0402_6.3V6K PC89 1 2 2 PR107 8.06K_0402_1% 1 PR110 4.7_1206_5% 2 +5VALW 1 1 BOOT2 LX_1.2V PR112 NB_COREP_EN 1 UG_1.2V 22 21 PVCC2 20 19 PGND2 18 15 LGATE2 UGATE2 PGND1 BOOT1 17 1BST_NB_COREP14 PR108 2.2_0603_5% LGATE1 1 2 16 2 PC86 0.1U_0402_16V7K PVCC1 1 2 3 3 PR111 47K_0402_1% 2 1 23 2 UGATE1 PC84 4.7U_1206_25V6K 13 PC82 0.022U_0402_16V7K 2 UG_NB_COREP 1 2 3 4 4 S S S 1 G 2 PC85 680P_0603_50V8J PQ24 FDS6670AS_NL_SO8 D2 D2 G1 S1 PQ23 1 8 7 6 5 D D D D PR106 4.7_1206_5% G2 S2/D1 S2/D1 S2/D1 2 8 7 6 5 PC81 4.7U_1206_25V6K PHASE1 AO4932_SO8 1.2V_EN 1 12 2 + 2 8.06K_0402_1% LX_NB_COREP 1.2UH_1164AY-1R2N=P3_9.8A_30% 2 PR103 10 NB_COREP_EN 2 2 <32,36,42> VLDT_EN 1 ISL6228HRTZ-T_QFN28_4X4 1 PC83 330U_D2E_2.5VM PC79 4.7U_1206_25V6K 1 2 8 7 6 5 4 FB2_1.2V 71.5K_0402_1% 1 2 3 2 PL7 1 +NB_COREP PR104 7.87K_0402_1% 1 +1.1V PQ22 AO4466_SO8 PC78 4.7U_1206_25V6K 2 1 9 PC80 0.022U_0402_16V7K 1 2 2 Freq=366KHz Rfset=1/(1.5E-10 * Freq)=18.2K @ PC93 0.01U_0402_25V7K 4 4 Freq=303KHz Rfset=1/(1.5E-10 * Freq)=22K Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/11/03 Deciphered Date 2009/11/03 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title NB_COREP / 1.2VSB Size Document Number R ev 0.3 KBKC0_KBYF0 Date: Tuesday, February 03, 2009 D Sheet 41 of 46 5 4 3 2 1 PJ14 PR115 200K_0402_5% 1 2 11 V5DRV 10 9 DL_1.8V 2 TPS51117RGYR_QFN14_3.5x3.5 1 1 +1.8VP 1 + 2 S S S DRVL PQ27 FDS6670AS_NL_SO8 4 G 1 PGND 8 GND PGOOD PR190 4.7_1206_5% +5VALW PR119 17.4K_0402_1% 1 2 3 2 1 12 2 PC101 1U_0603_10V6K B+ D 1 15 14 LX_1.8V LL TRIP 0.1U_0603_25V7K 2 VFB DH_1.8V 5 6 7 8 5 13 D D D D V5FILT 7 +5VALW C @ PC99 47P_0402_50V8J 1 2 1 PC98 330U_6.3V_M 2 PC160 680P_0603_50V8J 3 2 1 VOUT 4 DRVH 2 1 3 VBST TON TP 1 2 6 PR118 0_0603_1% 1 2 1 @ JUMP_43X118 PL9 1.2UH_1164AY-1R2N=P3_9.8A_30% 1 2 PC96 BST_1.8V-1 1 2 PC97 @0.1U_0402_16V7K PR117 0_0603_1% 1 2 2 2 PR187 47K_0402_5% EN_PSV 1 PU7 1 <30,36> SYSON 2 4 BST_1.8V PR116 0_0402_5% 1 2 2 PC95 4.7U_1206_25V6K PQ26 AO4466_SO8 2 5 6 7 8 1 D PC94 4.7U_1206_25V6K 51117_B+ PC100 4.7U_0805_10V6K C 1 PR120 14K_0402_1% 1 2 2 PR121 10K_0402_1% VFB=0.75V Vo=VFB*(1+PR120/PR121)=1.8V Ton=19E-12*Ron*(((2/3)*Vo+100mV)/Vin)+50ns=3.1E-07 Freq=305KHz +1.2VALW 1 +5VALW B 1 2 2 1 1 2 FB 2 VIN 9 +1.1VSP @ PR123 1.3K_0402_1% 1 2 APL5912-KAC-TRL_SO8 @ @ PC104 0.01U_0402_25V7K 22U_0805_6.3V6M 3 PC105 2 1 4 VOUT 1 5 1 VCNTL VIN VOUT 2 EN @ PC103 4.7U_0805_6.3V6K 2 8 @ PR186 47K_0402_5% 2 @ PC106 1U_0603_10V6K GND 1 VLDT_EN 1 <32,36,41> VLDT_EN @ PR122 0_0402_5% 1 2 POK 6 @ PU8 7 PJ15 JUMP_43X79 @ 2 @ PC102 1U_0402_6.3V6K 1 B Cesr=15m ohm Ipeak=12.6A Imax=8.82A Delta I=((19-1.8)*(1.8/19))/(L*Freq)=5.332A Vtrip=Rtrip*10uA=0.24V Iocp-min=Vtrip/Rdsonmax*1.4+2.666=17.573A Iocp-max=Vtrip/Rdsontyp*1.2+2.666=26.908A Iocp=17.573~26.908A 2 @ PR124 3K_0402_1% A A 2008/11/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title 1.8VSP/+1.1VSP Size Document Number R ev 0.3 KBKC0_KBYF0 Date: Tuesday, February 03, 2009 Sheet 1 42 of 46 5 4 3 2 1 +3VS 2 PJ16 @ JUMP_43X79 D 1 2 VIN 9 +2.5VSP 1 PC109 0.01U_0402_25V7K 2 2 PR126 2.15K_0402_1% APL5915KAI-TRL_SO8 2 @ PR185 47K_0402_5% 1 1 EN 1 3 FB 1 VOUT PC108 4.7U_0805_6.3V6K 1 2 2 PC111 0.1U_0402_16V7K 4 GND 8 1 +3VS 5 PC110 22U_0805_6.3V6M PR125 10K_0402_1% 1 2 VIN VOUT 2 POK VCNTL PU9 7 6 2 D PC107 1U_0402_6.3V6K 2 1 1 1 +5VALW 2 PR127 1K_0402_1% C C 1 +1.8V 1 +1.8V PJ17 @ JUMP_43X79 6 NC 5 3 VREF NC 7 4 VOUT NC 8 TP 9 +3VALW 1 VCNTL GND 1 2 2 VIN 2 2 PC114 1U_0402_6.3V6K B 2 PQ28 SSM3K7002F_SC59-3 @ 1 1 2 1 S +0.9VP 2 2 1 2 PC118 @ 0.1U_0402_16V7K PR129 1K_0402_1% PC116 0.1U_0402_16V7K 1 PC117 0.01U_0402_25V7K 2 APL5915KAI-TRL_SO8 2 PR132 1.54K_0402_1% 2 G 2 9 1 VIN D 3 FB 2 @ PR131 0_0402_5% 1 2 +1.5VSP <24,29,36> SYSON# 1 3 1 4 VOUT 1 VOUT APL5331KAC-TRL_SO8 2 1 GND 1 EN PR128 1K_0402_1% PC115 4.7U_0805_6.3V6K 2 PC121 0.1U_0402_16V7K @ PR184 47K_0402_5% 1 8 1 <30,32,36> SUSP# 10K_0402_1% 1 2 5 PC119 22U_0805_6.3V6M POK VIN 2 7 PR130 1 6 PU11 VCNTL B PU10 1 2 PC113 4.7U_0805_6.3V6K 2 PC112 1U_0402_6.3V6K PJ18 @ JUMP_43X79 2 1 1 1 2 +5VALW PC120 10U_0805_6.3V6M 2 PR133 1.74K_0402_1% A A 2008/11/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/03 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title 0.9VP//1.5VSP/2.5VSP Size Document Number R ev 0.3 KBKC0_KBYF0 Date: Tuesday, February 03, 2009 Sheet 1 43 of 46 4 3 2 1 PR140 10_0402_5% 1 2 +CPU_CORE_NB 1 PC155 2200P_0402_50V7K 2 1 PC152 0.01U_0402_25V7K 2 1 1 11 COMP0 UGATE1 26 UGATE1 12 VW0 BOOT1 25 BOOT1 4 2 PC156 2200P_0402_50V7K 2 1 2 1 2 PHASE1 PL13 0.36UH_PCMC104T-R36MN1R17_30A_20% 1 4 3 2 1 1 4 2 2 PR172 1 10_0402_5% VW1 PR175 PC147 255_0402_1% 4700P_0402_25V7K FB_1 2 1 2 1 PC146 1000P_0402_50V7K 2 1 COMP1 2 PC148 180P_0402_50V8J PC142 680P_0603_50V7K PR177 2 1 PC150 2 1 PR178 6.81K_0402_1% 2 1 PR179 1K_0402_5% 2 1 54.9K_0402_1% 1200P_0402_50V7K PR180 1 2 1 PR181 6.81K_0402_1% 2 1 PC143 2 1 A 54.9K_0402_1% 1200P_0402_50V7K 2008/11/03 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/11/03 Deciphered Date 4 3 Title +CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 1 PR170 2 4.02K_0402_1% +CPU_CORE_1 Design Current: 12.6A Max current: 18A OCP_min:24A PC149 1000P_0402_50V7K PC151 2 1 +CPU_CORE_1 3 0.1U_0402_16V7K @ PH4 2 1 2 PR173 1 10_0402_5% @ 10K_0603_5%_TSM1A103J4302RE A PR176 1K_0402_5% 2 1 2 PR168 16.2K_0402_1% PR169 4.7_1206_5% PQ36 AO4456_SO8 1 PQ35 AO4456_SO8 4 1 2 PC141 0.22U_0603_10V7K 2 2 5 6 7 8 PR163 2.2_0603_5% BOOT1 1 2 1 RTN1 D IFF_1 1 B ISN1 1 PC153 0.01U_0402_25V7K 2 1 PC134 10U_1206_25V6M 2 1 3 2 1 5 49 PQ34 SI7686DP-T1-E3_SO8 UGATE1 +CPU_CORE_0 Design Current: 12.6A Max current: 18A OCP_min:24A ISP1 2 PC145 180P_0402_50V8J 0.1U_0402_16V7K @ PH3 1 2 PR159 1 10_0402_5% 10K_0603_5%_TSM1A103J4302RE @ CPU_B+ TP ISN1 24 ISN1 ISP1 23 ISP1 VW1 COMP1 22 21 FB1 20 VDIFF1 19 RTN1 VSEN1 18 17 LGATE0 LGATE1 COMP0 PC136 680P_0603_50V7K 2 VSEN1 VW0 PR174 PC144 255_0402_1% 4700P_0402_25V7K FB_0 2 1 2 1 PR155 1 2 4.02K_0402_1% PC137 2 1 ISN0 PHASE1 3 ISP0 28 27 PC138 1U_0603_16V6K PC140 10U_1206_25V6M 2 1 LGATE1 PC139 10U_1206_25V6M 2 1 29 LGATE0 3 2 1 LGATE1 4 3 2 1 30 1 31 PVCC PR154 4.7_1206_5% PQ33 AO4456_SO8 2 LGATE0 +5VS 2 C +CPU_CORE_0 PR151 16.2K_0402_1% PC157 2200P_0402_50V7K 2 1 32 PQ32 AO4456_SO8 4 PC154 0.01U_0402_25V7K 2 1 PGND0 1 PHASE0 1 2 33 PC135 0.22U_0603_10V7K 5 6 7 8 PHASE0 PL12 0.36UH_PCMC104T-R36MN1R17_30A_20% 1 4 2 5 6 7 8 UGATE0 PGND1 @ PR198 2 1 100K_0402_5% PC133 10U_1206_25V6M 2 1 5 1 37 UGATE_NB 39 38 PHASE_NB 40 42 43 44 46 45 47 41 PGND_NB LGATE_NB BOOT0 PHASE1 +CPU_CORE_1 D IFF_0 35 34 FB0 VDIFF0 PR171 0_0402_5% 2 1 <6> CPU_VDD1_FB_H BOOT0 UGATE0 PR150 2.2_0603_5% BOOT0 1 2 1 3 2 1 +1.8V 4 5 6 7 8 <6> CPU_VDD1_FB_L PQ31 SI7686DP-T1-E3_SO8 UGATE0 3 2 1 <6> CPU_VDD0_FB_L BOOT_NB 10 13 <6> CPU_VDD0_FB_H 36 BOOT_NB ISL6265IRZ-T_QFN48_6X6~D ISP0 ISN0 PR160 0_0402_5% VSEN0 2 1 PR161 +CPU_CORE_0 2 1 PR164 10_0402_5% 2 1 RTN0 0_0402_5% 2 PR165 1 0_0402_5% B PC130 220U_D2_4VM 2 PHASE0 1 2 PR167 10_0402_5% 9 OCSET_NB OCSET RTN_NB 8 FSET_NB RBIAS VSEN_NB ENABLE 7 FB_NB 6 COMP_NB SVC ISP0 2 1 34.8K_0402_1% PR158 2 1 82.5K_0402_1% 5 RTN0 PR157 SVD VSEN0 <30> VR_ON 4 16 1 0_0402_5% PWROK 15 2 PR156 3 PR166 10_0402_5% 1 2 <6> CPU_SVC PGOOD ISN0 1 0_0402_5% OFS/VFIXEN 2 14 2 PR152 1 VCC 48 VIN 2 <6> CPU_SVD CPU_VDDNB_FB_L <6> PR148 10_0402_5% PU12 PR153 0_0402_5% 1 2 1 2 PR192 0_0402_5% @ + PC131 680P_0603_50V7K CPU_B+ 1 PR145 0_0402_5% 2 1 2 <30> VGATE <19> H_PWRGD_L +VDDNB Design Current: 2.1A Max current: 3A OCP_min:5A 1 UGATE_NB PR149 @ 105K_0402_1% C PQ30 AO4712_SO8 LGATE_NB 2 2 1 1 2 PR147 105K_0402_1% D +CPU_CORE_NB PHASE_NB 2 PR146 @ 10K_0402_1% PR138 4.7_1206_5% 2 PC129 0.22U_0603_10V7K 4 + 2 PHASE_NB 2 PR144 @ 105K_0402_1% LGATE_NB PL11 3.3UH_SIQB74B-3R3PF_5.9A_20% 1 2 CPU_VDDNB_FB_H <6> PR142 11.3K_0402_1% 2 1 PC132 0.1U_0603_25V7K 1 PR143 0_0402_5% PR136 2.2_0603_5% BOOT_NB 1 2 1 PR141 0_0402_5% 2 1 2 PR139 2_0603_5% +3VS 1 +5VS PHASE_NB B+ 1 3 2 1 1 PQ29 AO4466_SO8 4 1 2 PR137 22K_0402_1% 2 1 2 PC128 0.1U_0603_25V7K CPU_B+ UGATE_NB PC127 1000P_0402_50V7K 2 1 1 +5VS D 1 PC123 1200P_0402_50V7K PL10 HCB4532KF-800T90_1812 1 2 2 PR135 2_0603_5% 1 2 5 6 7 8 2 3 2 1 1 PR134 44.2K_0402_1% 5 6 7 8 2 PC124 10U_1206_25V6M 2 1 CPU_B+ PC122 33P_0402_50V8K 2 1 PC125 220U_25V_M 5 2 Size Document Number Custom R ev 0.3 KBKC0_KBYF0 Date: Tuesday, February 03, 2009 Sheet 1 44 of 46 5 4 3 2 Version change list (P.I.R. List) Item D Reason for change Rev. PG# Modify List Page 1 of 1 for PWR Date Phase 1 EMI request. EMI request. 0.1 40 Change PR38,PR39,PR108,PR112,PR136,PR150,PR163 from 08, 12/24 SD013000080 to SD013220B80. to DVT 2 EMI request. EMI request. 0.1 40 Add PC170,PC171,PC172,PC173,PC174 SE00000G880 S CER CAP 0.1U 25V K X5R 0402 08, 12/24 to DVT EMI request. EMI request. 0.1 39 Add PL15 SM010016410 S SUPPRE_ KC FBMA-L11-322513151LMA50T 08, 12/24 to DVT 4 EMI request. EMI request. 0.1 41 Add PL14 SM010018210 S SUPPRE_ TAI-TECH HCB4532KF -800T90 1812 08, 12/24 to DVT 5 Link CIS error. Link CIS error. 0.1 40 08, 12/24 to DVT 6 cost down cost down 0.1 40 Change PC30 from SGA19331360 S POLY C 330U 6.3V M D3L ESR25M TPE H2.8 to SF000001G00 S_A-P_CAP 330U 6.3V M 6.3X5.7 LESR14M ME 08, 12/24 to DVT 7 cost down cost down 0.1 40 Change PC35 from SGA20151320 S POLY C 150U 6.3V M D2E TPE ESR18 H1.8 to SF000001G00 S_A-P_CAP 330U 6.3V M 6.3X5.7 LESR14M ME 08, 12/24 to DVT 8 cost down cost down 0.1 41, 42 Change PC87, PC98 from SGA19331D00 S POLY C 330U 2.5V M D2 TPE LESR15M H1.8 to SF000001G00 S_A-P_CAP 330U 08, 12/24 6.3V M 6.3X5.7 LESR14M ME to DVT 9 schematic update. schematic update. 0.1 44 layout space too small. layout space too small. 0.1 41 3 C Fixed Issue 1 10 Change PQ9, PQ10, PQ12 from SB944070000 S TR AO4407 1P SO8 W/D to SB00000DL00 S TR AO4407A 1P SO8 Delete PR198 SD028100380 S RES 1/16W 100K +-5% 0402 Change PQ23 from SB00000CG00 S TR AO4466 1N SO8 to SB00000BG00 S TR AO4932 2N SO8 D C 08, 12/24 to DVT 08, 12/24 to DVT Delete PQ25 SB00000AJ00 S TR AO4712 1N SO8 11 B 12 B 13 14 15 16 17 18 A A Compal Electronics, Inc. Compal Secret Data Security Classification 2008/11/03 Issued Date Deciphered Date 2009/11/03 PIR List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 Title 2 Size Document Number Custom Date: Rev 0.3 KBKC0_KBYF0 Tuesday, February 03, 2009 Sheet 1 45 of 46 5 4 3 2 1 NO DATE PAGE MODIFICATION LIST PURPOSE ----------------------------------------------------------------------------------------------------------------------------------------------- D C 12/17 p.12 L3,L4 change from bead to 0 Ohm 12/17 P.17 Add R858~R865 for VGA HDMI 12/17 P.18 R374,R375,R376 change from 0 ohm to 10 ohm 12/17 P.20 R50 ,R53 change from JV70@ to @ 12/17 P.20 R51 ,R52 change from JM70@ to JV70@ 12/17 P.24 JP18 change from ESATA to USB port 12/17 P.25 R396 change from 10K to 0 Ohm 12/17 P.31 C905~C907 change from 0.1u to 33P 12/17 P.31 U19 change from mount to @ ; U18 change from @ to mount 12/17 P.32 D22 change from mount to @ 12/18 P.24 SATA re-driver IC reserved 12/22 P.8 Add c124,c128,c151,c155,c55,c119,c113,c197 0.1uF EMI request 12/22 P.30 Add c40 c41 100P EMI request 12/22 P.30 Add c42,c43,c45 EMI request 12/22 P.37~p.45 upgrade PWR schematic 12/22 P.30 Add C65 22uF for CRT flicker 12/23 P.21 Delete R174,R175 01/16 P.16 Add r611,r612 connect to INVT_PWM 01/16 P.11 Add r347 connect to BKOFF# 01/16 P.30 add r288 BKOFF# D C Vari-Bright reserved Vari-Bright reserved 4.7k pull low B B A A Compal Secret Data Security Classification Issued Date 2008/11/03 Deciphered Date 2009/11/03 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Compal Electronics, Inc. HW PIR Size Document Number Rev 0.3 KBYF0 LA-5051P Date: Tuesday, February 03, 2009 Sheet 1 46 of 46 www.s-manuals.com
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.4 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Producer : Acrobat Distiller 6.0 (Windows) Modify Date : 2015:08:15 23:40:53+03:00 Create Date : 2009:02:09 15:38:03+08:00 Metadata Date : 2015:08:15 23:40:53+03:00 Document ID : uuid:17edd26d-1c8b-40c2-8bda-1e9f47767d75 Instance ID : uuid:f32678f9-107c-47e9-bee5-602803c9a712 Format : application/pdf Title : Compal LA-5051P - Schematics. www.s-manuals.com. Creator : Subject : Compal LA-5051P - Schematics. www.s-manuals.com. Page Count : 47 Keywords : Compal, LA-5051P, -, Schematics., www.s-manuals.com. Warning : [Minor] Ignored duplicate Info dictionaryEXIF Metadata provided by EXIF.tools