Compal LA 5154P Schematics. Www.s Manuals.com. R1.0 Schematics
User Manual: Motherboard Compal LA-5154P NAT02 - Schematics. Free.
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A B C D E 1 1 Compal Confidential 2 2 NAT02 M/B Schematics Document Intel Arrandale Processor with DDRIII + Ibex Peak-M 2009-11-26 3 3 REV:1.0 4 4 2009/09/21 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Cover Page Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet E 1 of 49 5 4 Block Diagram Compal confidential Model : NAT01 3 Clock Generator FFS FAN +3VS +5VS +3VS P.14 P.14 +1.1VS_VTT P.35 FDI x8 (UMA) P.35 HDMI CONN +5VS Intel Ibex Peak-M HDMI Level Shift P.36 P.36 100MHz To Card-reader subboard 8 IN 1 CONN +3VS +3VS +1.8VS IEEE1394 P.30 CardBus OZ888GS0 PCI Express BUS Express Card P.28 B RTL8111DL RJ45 +3VALW PCIE3 PCIE2 Mini Card 3 TV Tuner +3VS +1.5VS P.24 Mini Card 2 WLAN P.28 +3VS +1.5VS USB[x] PCIE1 Mini Card 1 WWAN P.27 +3VS +1.5VS USB[x] DC/DC Interface BATT IN P.33 P.27 PCI-Express x 8 (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S) C VCORE P.11,12 +0.75VS 6.4G/8.5G/10.6G Right Front Side. Right behind side. USBx14 3.3V 48MHz SATA x 6 100MHz (GEN1 1.5GT/S ,GEN2 3GT/S) HD Audio USB Port1 X1 To Single USB subboard P.30 Bluetooth P.30 3.3V 24MHz Touch Screen P.32 page 15,16,17 18,19, 20,21,22,23 Camera LPC BUS SPI ROM x1 32Mbitpage 15 +3VS 33MHz port 5 +5VALW +RTC_CELL +3VS P.31 P.30 port 0 E-ODD SB3526 P.30 Charge USB/E-SATA Ports X1 port 4 ENE KBC KB926QFD3 +3VALW C SPI port 1 S-HDD-2 S-HDD-1 +5VS +5VS +3VS +5VS page 32 P.29 P.29 P.29 B To Cap Sensor subboard Azalia Codec 92HD73C +3VS +VDDA SPI Int.KBD & P.32 BL P.25 Touch Pad AMP MAX9736A B+ AMP MAX4411x2 Flash ROM B+ Speaker P.26 AMP MAX9736A P.32 Subwoofer P.26 P.25 Dig. MIC 16Mx1sector HeadPhone & MIC Jack 1.5V/0.75V P.46 To Card-reader subboard P.30 +5V_ALW PCH +1.05VS USB Port X1 +5V_ALW P.31 USB[x] P.47 +1.5V 1.5V DDRIII 800/1066/1333 1GB/s x4 DPB D BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8 100MHz 2.7GT/s P.37 DDRIII-DIMM X2 100M/133M/166M(CFD) DMI x4 100MHz DPD DP CONN +5VS page 06 Dual Channel LVDS LVDS CONN 133MHz Memory BUS(DDRIII) page 5,6,7,8,9,10 +LCDVDD +3.3V_ALW CPU XDP 133/120/100/96/14.318MHZ to PCH 48MHZ to CardReader page 13 Processor rPGA988A VGA CRT CONN +5VS 1 IDT: 9LRS3199AKLFT SILEGO: SLG8SP587 Intel Arrandale (UMA) +CPU_CORE D 2 +3VS P.30 P.25 P.44 A A Power Sequence 1.1VS_VTT P.45 CHARGER 3V/5V P.41 P.42 GFX_Core/1.05V P.40 5 1.05V/1.8V P.48 Issued Date P.43 4 Compal Electronics, Inc. Compal Secret Data Security Classification DC IN 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Title Block Diagrams Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 2 of 49 A B C D SIGNAL STATE Voltage Rails 1 Full ON E SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF N/A N/A S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Power Plane Description S1 S3 VIN Adapter power supply (19V) N/A B+ AC or battery power rail for power circuit. N/A +CPU_CORE Core voltage for CPU ON OFF OFF +VGFX_CORE Core voltage for Graphic ON OFF OFF +0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF +1.05VS 1.05V switched power rail for PCH ON OFF OFF +1.1VS_VTT 1.1V switched power rail (1.05 for AUB CPU) ON OFF OFF +1.1VS 1.1V power rail for PCIE of GUP ON OFF OFF +1.5V 1.5V power rail for DDRIII ON ON OFF +1.5VS 1.5V switched power rail ON OFF OFF +1.8VS 1.8V switched power rail ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* +LAN_IO 3.3V power rail for LAN ON ON ON* +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF B+_BIAS B+ always on power rail ON ON ON* +RTCVCC RTC power ON ON ON 2 1 Board ID / SKU ID Table for AD channel Vcc Ra Board ID X00 X01 X02 MP X00 X01 X02 MP VGA M96 M96 M96 M96 Madison Madison Madison Madison 3.3V +/- 5% 100K +/- 1% Rb 0 8.2K +/- 1% 18K +/- 1% 33K +/- 1% 56K +/- 1% 100K +/- 1% 200K +/- 1% NC V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max 0.100 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V 2 Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. External PCI Devices Device IDSEL# REQ#/GNT# Interrupts USB Port Table EC SM Bus1 address 3 USB Port EC SM Bus2 address 0 Device Address Device Smart Battery 0001 011X b WWAN 2 WLAN 3 Express Card 4 Address 1 5 6 7 8 Ibex SM Bus address Device Address Clock Generator (9LRS3191AKLFT, SLG8SP585) 1101 0010b DDR DIMM0 1001 000Xb DDR DIMM1 1001 010Xb 9 10 11 BTO Option Table BTO Item Device USB&ESATA Reader/BD USB board WPAN WLAN WWAN NC NC Express Touch screen Bluetooth Camera BOM Structure 3 Free Fall Sensor CPU XDP 4 PCH XDP remove XDCP_ISL90727 0101 110Xb XDCP_ISL90728 0111 110Xb 4 2009/09/21 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Notes List Size B Date: Document Number Rev 1.0 NAT02 M/B LA-5154P Schematic Thursday, November 26, 2009 Sheet E 3 of 49 5 4 3 2 1 2500mA D SUSP# TPS51117RGYR (PU7) SUSP# ISL6268CAZ-T (PU8) D +1.8VS 15000mA +1.1VS_VTT 8881mA 65000mA ADAPTER VR_ON ISL62883HRZ-T (PU13) SI4800BDY (U25) +CPU_CORE 15000mA B+ GFXVR_PWRGD ISL62881HRZ-T (PU22) BATTERY 913mA RT9025 (PU12) +GFX_CORE 12800mA SYSON ISL6268CAZ-T (PU10) SUSP# TPS51117RGYR (PU6) SUSP# TPS51427 (PU5) +1.5VS +1.1VS ?mA SUSP# +1.5V RT9026 (PU10) +0.75VS 5700mA C CHARGER 0 Ohm +1.05VS +5VALW RUNON 8400mA +3VALW USB_EN# SI4800BDY (U22) EN_EOL# TPS2062ADR (U17) 2000mA SUSP SI3456BDY (Q3) 160mA +5VS FUSE +5V_CHGUSB SUSP FBM-11-160808-601-T (L29) 20mA +LAN_IO B 0 Ohm +3VS B EN_EOL# VDDEN RTL8111DL (U9) +CRT_VCC SI4800BDY (U21) 8677mA +EC_AVCC 0 Ohm 0 Ohm +LAN_VDD 0 Ohm C +1.05VS_CK505 +AVDD_AUDIO 0 Ohm +5VS_KBL 0 Ohm +3VS_CK505 +DVDD_AUDIO EN_EOL# SI2310BDS-T1-E3 (Q25) SI2310BDS (Q34) +LCDVDD +3VS_DELAY +3V_WLAN +3V_WLAN A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Power Rail Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 4 of 49 5 4 3 2 1 JCPU1E DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3 A24 C23 B22 A21 <17> <17> <17> <17> DMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2 DMI_PTX_HRX_P3 B24 D23 B23 A22 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] <17> <17> <17> <17> DMI_HTX_PRX_N0 DMI_HTX_PRX_N1 DMI_HTX_PRX_N2 DMI_HTX_PRX_N3 D24 G24 F23 H23 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] <17> <17> <17> <17> DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3 D25 F24 E23 G23 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] UMA E22 D21 D19 D18 G21 E19 F21 G18 H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7 D22 C21 D20 C18 G22 E20 F20 G19 FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] <17> H_FDI_FSYNC0 <17> H_FDI_FSYNC1 F17 E17 FDI_FSYNC[0] FDI_FSYNC[1] <17> H_FDI_INT C17 FDI_INT <17> H_FDI_LSYNC0 <17> H_FDI_LSYNC1 F18 D17 FDI_LSYNC[0] FDI_LSYNC[1] <17> <17> <17> <17> <17> <17> <17> <17> H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7 <17> <17> <17> <17> <17> <17> <17> <17> H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7 FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] Intel(R) FDI C H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7 DMI D DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] PCI EXPRESS -- GRAPHICS <17> <17> <17> <17> PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS B26 A26 B27 A25 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] PEG_IRCOMP R605 1 2 49.9_0402_1%~D EXP_RBIAS R613 1 2 750_0402_1%~D AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30 UMA Remove PCIE-16X <11> H_DIMMA_REF <12> H_DIMMB_REF RSVD32 RSVD33 AJ13 AJ12 @ @ PAD T97 PAD T98 RSVD34 RSVD35 AH25 AK26 @ @ PAD T99 PAD T100 RSVD36 RSVD_NCTF_37 AL26 AR2 @ PAD T101 RSVD38 RSVD39 RSVD_NCTF_40 RSVD_NCTF_41 RSVD_NCTF_42 RSVD_NCTF_43 R1035 3.01K_0402_1%~D1 @ 2 R1036 3.01K_0402_1%~D1 @ R1037 1 @ 3.01K_0402_1%~D 2 2 R1038 1 @ 3.01K_0402_1%~D 2 WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16 R212 0_0402_5%~D @ 1 2 @ 1 2 RSVD15 RSVD16 A20 B20 RSVD17 RSVD18 U9 T9 RSVD19 RSVD20 R213 0_0402_5%~D L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86 B19 A19 AC9 AB9 C1 A3 J29 J28 A34 A33 C35 B35 IC,AUB_CFD_rPGA,R0P9 CONN@ B RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 (SA_DIMM_VREF) RSVD10(SB_DIMM_VREF) RSVD11 RSVD12 RSVD13 RSVD14 RESERVED JCPU1A RSVD21 RSVD22 RSVD_NCTF_23 RSVD_NCTF_24 RSVD26 RSVD27 RSVD_NCTF_28 RSVD_NCTF_29 RSVD_NCTF_30 RSVD_NCTF_31 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58 RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65 RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75 RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85 VSS AJ26 AJ27 AP1 AT2 D @ PAD T102 AT3 AR1 AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32 E15 F15 A2 D15 C15 AJ15 AH15 R649 0_0402_5%~D @ 2 1 @ 2 1 R648 0_0402_5%~D C AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 B AP34 IC,AUB_CFD_rPGA,R0P9 CONN@ CFG0 - PCI-Express Configuration Select CFG4 - Display Port Presence *1:Single PEG 0:Bifurcation enabled *1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port CFG3 - PCI-Express Static Lane Reversal *:Default A A *1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ... Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PROCESSOR (1/6) DMI,FDI,PEG Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 5 of 49 4 3 2 1 +3VALW C1142 1 2 JCPU1B PECI R1042 1 0_0402_5%~D <20> H_THERMTRIP# H_THERMTRIP#_R 2 H_CPURST# AP26 RESET_OBS# 2 H_PM_SYNC_R AL15 PM_SYNC R263 1 0_0402_5%~D 2 H_CPUPWRGD_1 AN14 VCCPW RGOOD_1 2 H_CPUPWRGD_0 R1045 1 0_0402_5%~D <17> PM_DRAM_PWRGD 2 PM_DRAM_PWRGD_R PLT_RST# R289 1 1.5K_0402_1%~D 2 VCCPW RGOOD_0 AK13 SM_DRAMPW ROK AM15 VTTPW RGOOD AM26 TAPPW RGOOD PLT_RST#_R AL14 RSTIN# 2 E16 D16 CLK_CPU_DMI_R CLK_CPU_DMI#_R R606 1 R607 1 2 0_0402_5%~D 2 0_0402_5%~D DPLL_REF_SSCLK DPLL_REF_SSCLK# A18 A17 CLK_CPU_DP_R CLK_CPU_DP#_R RU83 1 RU84 1 2 0_0402_5%~D 2 0_0402_5%~D SM_DRAMRST# CLK_CPU_DMI <16> CLK_CPU_DMI# <16> F6 BSS138_SOT23~D 3 1 2 IN2 PM_EXT_TS#[0] PM_EXT_TS#[1] AN15 AP15 PM_EXTTS#0 PM_EXTTS#1_R PRDY# PREQ# AT28 AP27 XDP_PRDY# XDP_PREQ# TCK TMS TRST# AN28 AP28 AT27 XDP_TCLK XDP_TMS XDP_TRST# TDI TDO TDI_M TDO_M AT29 AR27 AR29 AP29 XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M DBR# AN25 XDP_DBR#_R R1060 1 XDP_DBRESET# 2 0_0402_5%~D BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23 XDP_OBS0_R XDP_OBS1_R XDP_OBS2_R XDP_OBS3_R XDP_OBS4_R XDP_OBS5_R XDP_OBS6_R XDP_OBS7_R R1044 1 R1046 1 R1047 1 R1048 1 R1049 1 R1050 1 R1051 1 R284 1 2 2 2 2 2 2 2 2 2 10K_0402_5%~D 2 10K_0402_5%~D 2 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D XDP_PREQ# XDP_PRDY# XDP_OBS0 XDP_OBS1 +1.1VS_VTT +1.5V 1 2 H_COMP0 H_COMP1 H_COMP2 H_COMP3 R1053 1 R1061 1 R1062 1 @ R650 R234 R659 R658 XDP_OBS2 XDP_OBS3 2 49.9_0402_1%~D 2 68_0402_5%~D 2 68_0402_5%~D 1 1 1 1 2 2 2 2 49.9_0402_1%~D 49.9_0402_1%~D 20_0402_1%~D 20_0402_1%~D XDP_OBS4 XDP_OBS5 1 PM_DRAM_PWRGD_R SM_RCOMP_0 R645 1 SM_RCOMP_1 R646 1 SM_RCOMP_2 R647 1 2 @ R1055 3K_0402_1%~D 2 100_0402_1%~D 2 24.9_0402_1%~D 2 130_0402_1%~D +3VS 1 3 S 2 G R480 4.7K_0402_5%~D 1 2 +3VS D <11,12,16> PCH_SMBDATA A PM_DRAM_PWRGD_R R1103 1 2 750_0402_1%~D D XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TCLK R657 R653 R656 R669 XDP_TRST# R651 1 2 51_0402_1%~D XDP_TDI_R XDP_TDO_M R661 1 R662 1 @ 2 0_0402_5%~D 2 0_0402_5%~D 1 1 1 1 @ @ @ @ 2 2 2 2 51_0402_1%~D 51_0402_1%~D 51_0402_1%~D 51_0402_1%~D PM_EXTTS#0_1 <11,12> XDP_TDI XDP_TDO R663 0_0402_5%~D XDP_DBRESET# <17> XDP_TDI_M XDP_TDO_R XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7 JP8 [Calpella] Platform – Design Guide Addendum / Update – Rev. 1.52 @ R1054 1.1K_0402_1%~D R290 4 2 1 1.5K_0402_1%~D +1.1VS_VTT C 1 @ R667 1 R668 2 2 0_0402_5%~D 0_0402_5%~D JTAG MAPPING Scan Chain (Default) STUFF -> R653, R657, R662 NO STUFF -> R655, R660 CPU Only STUFF -> R653, R655 NO STUFF -> R657, R660, R662 GMCH Only STUFF -> R660, R662 NO STUFF -> R653, R655, R657 2 WW51.4 CRB Board Rework/workaround- Rev 0.1 has changed the resistors in RSTIN# H_CATERR# H_PROCHOT# H_CPURST# O IC,AUB_CFD_rPGA,R0P9 CONN@ R1052 750_0402_1%~D B 0.1U_0402_10V6K~D U69 <11,12,20> +1.1VS_VTT 2 0_0402_5%~D R1040 1 R288 1 R1041 1 IN1 SM_DRAMRST# <11,12> Q36 SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 @ R1121 1 1 74AHC1G08GW_SOT353-5~D CLK_CPU_DP <16> CLK_CPU_DP# <16> DDR_RST_GATE AL1 AM1 AN1 SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] 10K_0402_5%~D <44> 1.5V_PWRGD P PEG_CLK PEG_CLK# 2 G 2 0_0402_5%~D CLK_CPU_XDP 2 0_0402_5%~D CLK_CPU_XDP# 1 <19,24,27,28,30,31> R316 1 0_0402_5%~D AN27 H_PWRGD_XDP_R <45> H_VTTPWRGD H_PWRGD_XDP THERMTRIP# R300 1 0_0402_5%~D R1043 1 0_0402_5%~D <20> H_CPUPWRGD AK15 PROCHOT# PWR MANAGEMENT <17> H_PM_SYNC AN26 R655 1 R654 1 D AT15 H_PROCHOT# <46> H_PROCHOT# C H_PECI_R CLK_CPU_ITP_R CLK_CPU_ITP#_R S 2 CATERR# AR30 AT30 G R1039 1 0_0402_5%~D H_PECI SKTOCC# AK14 THERMAL <20> AH24 H_CATERR# BCLK_ITP BCLK_ITP# R1136 1 CLK_CPU_BCLK <20> CLK_CPU_BCLK# <20> 3 PAD D COMP0 2 0_0402_5%~D 2 0_0402_5%~D 1 T5 AT26 SKTOCC#_R R609 1 R610 1 2 COMP1 CLK_CPU_BCLK_R CLK_CPU_BCLK#_R 2 COMP2 G16 A16 B16 BCLK BCLK# CLOCKS AT24 H_COMP1 MISC H_COMP2 H_COMP0 @ COMP3 DDR3 MISC AT23 JTAG & BPM H_COMP3 5 5 <17,31> PBTN_OUT# +1.1VS_VTT C315 1 0.1U_0402_16V4Z~D @ 2 XDP_OBS6 XDP_OBS7 R365 1K_0402_5%~D H_CPUPWRGD 1 1 R363 T103 PAD T104 PAD 2 2 @ @ H_PWRGOOD_R PBTN_OUT#_XDP 0_0402_5%~D H_PWRGD_XDP SMB_DATA_S3 SMB_CLK_S3 XDP_TCLK SMB_DATA_S3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 XDP Connector GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PW RGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 CONN@ GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 B R1063 1K_0402_5%~D 1 2 H_CPURST# H_RESET#_R 1 @ 2 R362 0_0402_5%~D PCI_PLTRST# <19> CLK_CPU_XDP CLK_CPU_XDP# H_RESET#_R XDP_DBRESET# XDP_TDO XDP_TRST# XDP_TDI XDP_TMS +1.1VS_VTT R1064 1K_0402_5%~D 2 R1065 51_0402_1%~D 1 2 1 +3VS Leakage Issue +1.1VS_VTT A SAMTE_BSH-030-01-L-D-A Q52 2N7002LT1G_SOT23-3 +3VS 1 3 S <11,12,16> PCH_SMBCLK D 2 G R1099 4.7K_0402_5%~D 1 2 +3VS SMB_CLK_S3 Q53 2N7002LT1G_SOT23-3 5 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Issued Date Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Title PROCESSOR (2/6) CLK,JTAG Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Sheet Thursday, November 26, 2009 1 6 of 49 4 B <11> DDR_A_BS0 <11> DDR_A_BS1 <11> DDR_A_BS2 <11> DDR_A_CAS# <11> DDR_A_RAS# <11> DDR_A_W E# A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AC3 AB2 U7 DDR_A_CAS# DDR_A_RAS# DDR_A_W E# AE1 AB3 AE9 SA_CK[0] SA_CK#[0] SA_CKE[0] SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_RAS# SA_WE# AA6 AA7 P7 Y6 Y5 P6 DDR_A_CLK1 <11> DDR_A_CLK1# <11> DDR_A_CKE1 <11> SA_CS#[0] SA_CS#[1] AE2 AE8 DDR_A_CS0# <11> DDR_A_CS1# <11> SA_ODT[0] SA_ODT[1] AD8 AF9 DDR_A_ODT0 <11> DDR_A_ODT1 <11> B9 D7 H7 M7 AG6 AM7 AN10 AN13 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDR_A_CLK0 <11> DDR_A_CLK0# <11> DDR_A_CKE0 <11> SA_CK[1] SA_CK#[1] SA_CKE[1] SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] DDR SYSTEM MEMORY A C DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 2 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] C9 F8 J9 N9 AH7 AK9 AP11 AT13 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] C8 F9 H9 M9 AH8 AK10 AN11 AR13 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 <12> DDR_B_BS0 <12> DDR_B_BS1 <12> DDR_B_BS2 <12> DDR_B_CAS# <12> DDR_B_RAS# <12> DDR_B_W E# 1 JCPU1D <12> DDR_B_D[0..63] <12> DDR_B_DM[0..7] <12> DDR_B_DQS#[0..7] <12> DDR_B_DQS[0..7] <12> DDR_B_MA[0..15] JCPU1C <11> DDR_A_D[0..63] <11> DDR_A_DM[0..7] <11> DDR_A_DQS#[0..7] <11> DDR_A_DQS[0..7] <11> DDR_A_MA[0..15] D 3 B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AB1 W5 R7 SB_BS[0] SB_BS[1] SB_BS[2] DDR_B_CAS# DDR_B_RAS# DDR_B_W E# AC5 Y7 AC6 SB_CAS# SB_RAS# SB_WE# DDR SYSTEM MEMORY - B 5 SB_CK[0] SB_CK#[0] SB_CKE[0] W8 W9 M3 DDR_B_CLK0 <12> DDR_B_CLK0# <12> DDR_B_CKE0 <12> SB_CK[1] SB_CK#[1] SB_CKE[1] V7 V6 M2 DDR_B_CLK1 <12> DDR_B_CLK1# <12> DDR_B_CKE1 <12> SB_CS#[0] SB_CS#[1] AB8 AD6 DDR_B_CS0# <12> DDR_B_CS1# <12> SB_ODT[0] SB_ODT[1] AC7 AD1 DDR_B_ODT0 <12> DDR_B_ODT1 <12> SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] D4 E1 H3 K1 AH1 AL2 AR4 AT8 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D5 F4 J4 L4 AH2 AL4 AR5 AR8 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C5 E3 H4 M5 AG2 AL5 AP5 AR7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 D C B IC,AUB_CFD_rPGA,R0P9 CONN@ IC,AUB_CFD_rPGA,R0P9 CONN@ A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Issued Date Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 A 3 2 Title PROCESSOR (3/6) DDRIII Size B Date: Document Number Rev 1.0 NAT02 M/B LA-5154P Schematic Thursday, November 26, 2009 Sheet 1 7 of 49 5 4 3 2 1 JCPU1F WW15 MOW +CPU_CORE Peak 21A A VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 POWER B +1.1VS_VTT 10U_0805_6.3V6M~D 10U_0805_6.3V6M~D 10U_0805_6.3V6M~D AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 +CPU_CORE 1 C174 2 1 C183 2 1 C192 2 1 C195 2 1 C203 2 1 C211 2 10U_0805_6.3V6M~D 10U_0805_6.3V6M~D 10U_0805_6.3V6M~D 1 10U_0805_6.3V6M~D C159 1 2 10U_0805_6.3V6M~D 10U_0805_6.3V6M~D 1 C191 2 1 C201 2 PSI# VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] PROC_DPRSLPVR VTT_SELECT C213 2 1 C233 2 10U_0805_6.3V6M~D 10U_0805_6.3V6M~D 1 C245 2 1 C190 2 10U_0805_6.3V6M~D 10U_0805_6.3V6M~D 1 C200 2 1 C212 2 10U_0805_6.3V6M~D D C232 2 10U_0805_6.3V6M~D (Place these capacitors between inductor and socket on Bottom) +1.1VS_VTT +CPU_CORE 1 330U_X_2VM_R6M~OK 1 1 C1009 + C1010 + 2 C1011 + @ 2 10U_0805_6.3V6M~D R1.0 modify 1 1 C185 10U_0805_6.3V6M~D 1 C194 1 C199 10U_0805_6.3V6M~D 1 C208 1 C214 1 C223 C239 2 2 2 2 2 2 2 2 330U_X_2VM_R6M~OK 330U_X_2VM_R6M~OK 10U_0805_6.3V6M~D 10U_0805_6.3V6M~D 10U_0805_6.3V6M~D 10U_0805_6.3V6M~D (Place these capacitors under CPU socket, top layer) CSC (Current Sense Configuration) 8/25 +1.1VS_VTT C222 1 C240 1 R1066 1 R1067 1 @ 2 1K_0402_1%~D 2 1K_0402_1%~D CPU_VID1 R1068 1 R1069 1 @ 2 1K_0402_1%~D 2 1K_0402_1%~D 2 2 22U_0805_6.3V6M~OK CPU_VID2 R1070 1 R1071 1 @ 2 1K_0402_1%~D 2 1K_0402_1%~D CPU_VID3 R343 1 @ R1072 1 2 1K_0402_1%~D 2 1K_0402_1%~D CPU_VID4 R1073 1 @ R1074 1 2 1K_0402_1%~D 2 1K_0402_1%~D CPU_VID5 R1075 1 R1076 1 @ 2 1K_0402_1%~D 2 1K_0402_1%~D CPU_VID6 C1034 H_PSI# AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 CPU_VID0 <46> CPU_VID1 <46> CPU_VID2 <46> CPU_VID3 <46> CPU_VID4 <46> CPU_VID5 <46> CPU_VID6 <46> H_DPRSLPVR <46> H_VTTVID1 R1077 1 @ R1078 1 2 1K_0402_1%~D 2 1K_0402_1%~D H_DPRSLPVR R347 1 R1079 1 @ 2 1K_0402_1%~D 2 1K_0402_1%~D H_PSI# 2 1K_0402_1%~D 2 1K_0402_1%~D R348 1 @ R1080 1 VCC_SENSE VSS_SENSE VTT_SENSE VSS_SENSE_VTT 1 @ C1557 AJ34 AJ35 B15 A15 C1035 2 22U_0805_6.3V6M~OK C1036 2 1 C1037 2 1 C1062 2 22U_0805_6.3V6M~OK 22U_0805_6.3V6M~OK 1 C1038 2 1 2 22U_0805_6.3V6M~OK (Place these capacitors on CPU cavity, Bottom Layer) +CPU_CORE 22U_0805_6.3V6M~OK C1039 1 C1040 2 1 22U_0805_6.3V6M~OK C1041 2 1 C1042 2 1 C1063 2 22U_0805_6.3V6M~OK 22U_0805_6.3V6M~OK 1 C1043 2 1 2 22U_0805_6.3V6M~OK (Place these capacitors on CPU cavity, Bottom Layer) B H_VTTVID1 <45> VTT Rail IMVP_IMON <46> 2 1000P_0402_50V7K~D R0.3 modify VCCSENSE_R R641 1 VSSSENSE_R R642 1 2 0_0402_5%~D 2 0_0402_5%~D VTT_SENSE <45> VSS_SENSE_VTT R608 1 1 R643 VCCSENSE VSSSENSE 2 100_0402_1%~D 1 R644 2 100_0402_1%~D +CPU_CORE VCCSENSE <46> VSSSENSE <46> +CPU_CORE 470U_D2_2VM_R4.5M~OK 1 C1044 + 4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF) 1 C251 2 + 1 C1012 2 1 + C533 2 + 1 C263 @ 2 1 + + C167 @ 2 2 470U_D2_2VM_R4.5M~OK470U_D2_2VM_R4.5M~OK470U_D2_2VM_R4.5M~OK470U_D2_2VM_R4.5M~OK470U_D2_2VM_R4.5M~OK TOP side (under inductor) 2 0_0402_5%~D +CPU-CORE Decoupling SPCAP,Polymer close to CPU side. MLCC 0805 X5R 2009/09/21 Issued Date ESR, mohm 4X470uF 4m ohm/4 16X22uF 3m ohm/12 16X10uF 3m ohm/16 Stuffing Option 2X470uF A Compal Electronics, Inc. 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 C,uF Compal Secret Data Security Classification 4 1 22U_0805_6.3V6M~OK Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V AN35 1 22U_0805_6.3V6M~OK <46> H_VTTVID1 = high, 1.05V ISENSE C +CPU_CORE 22U_0805_6.3V6M~OK AN33 G15 CPU_VID0 22U_0805_6.3V6M~OK AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15 H_VTTVID1 = low, 1.1V IC,AUB_CFD_rPGA,R0P9 CONN@ 5 10U_0805_6.3V6M~D 1 +1.1VS_VTT CPU VIDS C VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 SENSE LINES D CPU CORE SUPPLY AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 Continuous 18A 1.1V RAIL POWER 48A 2 Title PROCESSOR (4/6) PWR,Bypass Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 8 of 49 5 4 3 2 1 11/17 follow Intel suggest to change RU93 to 470 ohm UMA +VGFX_CORE UMA JCPU1G 2 J24 J23 H25 VTT1_45 VTT1_46 VTT1_47 GRAPHICS C 15A 3A +1.1VS_VTT 1 22U_0805_6.3V6M~OK 2 2 C179 C178 FDI 1 VAXG_SENSE VSSAXG_SENSE AR22 AT22 GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] AM22 AP22 AN22 AP23 AM23 AP24 AN24 VCC_AXG_SENSE <48> VSS_AXG_SENSE <48> D GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6 <48> <48> <48> <48> <48> <48> <48> +1.5V_CPU_DDR C1033 1 RU93 1 GFX_VR_EN GFX_DPRSLPVR GFX_IMON 22U_0805_6.3V6M~OK AR25 AT25 AM24 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 VTT0_59 VTT0_60 VTT0_61 VTT0_62 P10 N10 L10 K10 2 470_0402_5%~D GFXVR_EN <48> 1 2 GFXVR_DPRSLPVR <48> 0_0402_5%~D GFXVR_IMON <48> GFXVR_DPRSLPVR_R RU1 C1143 1 C1144 1 C1145 1 1 C193 1 C196 2 1 C202 2 1U_0402_6.3V4Z~D 1 C209 2 1 C216 2 1 C184 2 1 2 C224 1 2 + C250 2 1U_0402_6.3V4Z~D1U_0402_6.3V4Z~D 22U_0805_6.3V6M~OK +1.5V 2 0.1U_0402_16V7K~D 2 0.1U_0402_16V7K~D 2 0.1U_0402_16V7K~D 2 0.1U_0402_16V7K~D PJP12 @ JUMP_43X118 1 1 2 2 1U_0402_6.3V4Z~D1U_0402_6.3V4Z~D22U_0805_6.3V6M~OK 330U_D2_2V_Y~OK 2 1 - 1.5V RAILS 2 1 DDR3 330U_X_2VM_R6M~OK 2 1 VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 GRAPHICS VIDs 2 1 AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16 POWER + CU6 10U_0805_6.3V6M~D 2 CU52 CU1 10U_0805_6.3V6M~D D + CU5 22U_0805_6.3V6M~OK @ CU51 1 CU4 22U_0805_6.3V6M~OK 1 SENSE LINES 330U_X_2VM_R6M~OK PJP13 @ JUMP_43X118 1 1 2 2 PJP14 @ JUMP_43X118 1 1 2 2 C +1.1VS_VTT 1 +1.1VS_VTT 2 C160 10U_0805_6.3V6M~D 22U_0805_6.3V6M~OK 2 2 B C176 22U_0805_6.3V6M~OK VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68 J22 J20 J18 H21 H20 H19 VCCPLL1 VCCPLL2 VCCPLL3 L26 L27 M26 1 2 C158 22U_0805_6.3V6M~OK B 0.6A 1.8V 1 VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58 PEG & DMI 1 C177 K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25 1.1V +1.1VS_VTT 2.2U_0603_6.3V6K~D +1.8VS_VCCSFR C175 1 1U_0402_6.3V4Z~D 2 IC,AUB_CFD_rPGA,R0P9 CONN@ +1.8VS R228 0.022_0805_1%~OK 1 2 C182 1 C180 2 1 C168 2 1 1 2 2 22U_0805_6.3V6M~OK C165 1U_0402_6.3V4Z~D4.7U_0805_10V4Z~D A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Issued Date Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PROCESSOR (5/6) PWR Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 9 of 49 5 4 3 2 D C B VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 JCPU1I VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30 K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9 IC,AUB_CFD_rPGA,R0P9 CONN@ VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 D C VSS NCTF JCPU1H AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35 1 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 AT35 AT1 AR34 B34 B2 B1 A35 B IC,AUB_CFD_rPGA,R0P9 CONN@ A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Issued Date Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PROCESSOR (6/6) VSS Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 10 of 49 5 4 3 2 1 +1.5V M3 Circuit <7> DDR_A_DQS#[0..7] JDIMM1 <7> DDR_A_D[0..63] R178 1 <5> H_DIMMA_REF 1 <7> DDR_A_DM[0..7] R170 2 0_0402_5%~D DDR_A_DM0 VREF_POT0_R <7> DDR_A_MA[0..15] +V_DDR3_DIMMA_REF R227 1 @ 2 0_0402_5%~D DDR_A_D2 DDR_A_D3 PCH_SMBCLK 1 <6,12,16> PCH_SMBCLK PCH_SMBDATA <6,12,16> PCH_SMBDATA R169 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 DDR_A_D0 DDR_A_D1 <7> DDR_A_DQS[0..7] 1K_0402_1%~D 2 R179 1 +V_DDR3_DIMMA_REF +V_DDR3_DIMMA_REF VREF_DQA 2 0_0402_5%~D 1 1 0.1U_0402_16V4Z~D 2 2 C124 DDR_A_D8 DDR_A_D9 C112 D +V_DDR3_DIMMA_REF +V_DDR3_DIMMA_REF2 R1245 +V_DDR3_DIMMB_REF2 R1229 1 2 0_0402_5%~D @ 1 2 0_0402_5%~D @ +3V 1 @ C153 1 2 1U_0402_6.3V4Z~D GND RW 6 DDR_A_D24 DDR_A_D25 DDR_A_DM3 4 SDA ISL90727WIE627Z-TK_SC70-6 2 P 0 - @ R222 @R222 12.1K_0402_1%~D 1 1 DDR_A_D26 DDR_A_D27 @ R221 2.2_0402_5%~D 2 @ U46A LM358DT_SO8 VREF_POT0_R 1 @R220 @ R220 10_0402_5%~D 2 PCH_SMBCLK PCH_SMBDATA + G SCL 3 4 3 VREF_RW_POT0 5 1 2 DDR_A_D18 DDR_A_D19 2 VREF_OPAMP_POT0 @ C163 1U_0402_6.3V4Z~D DDR_A_CKE0 <7> DDR_A_CKE0 2 <7> DDR_A_BS2 C +5VALW 6 1 PP_S4GT_Q_0 @ R226 100K_0402_5%~D 2 <12> @ Q48A @Q48A 2N7002DW-7-F_SOT363-6~D PP_S4GT 2 PP_S4GT 1 PP_S4GT <7> DDR_A_CLK0 <7> DDR_A_CLK0# 1 3 @ Q48B 2N7002DW-7-F_SOT363-6~D @ R230 1M_0402_5%~D 4 <7> DDR_A_BS0 <7> DDR_A_WE# <7> DDR_A_CAS# 2 5 <17> PM_SLP_S4# <7> DDR_A_CS1# Layout Note: Place near JDIMM1 Layout Note: Place these 4 Caps near Command and Control signals of DIMMA M1 Circuit +1.5V B 10U_0805_6.3V6M~D 10U_0805_6.3V6M~D 10U_0805_6.3V6M~D 0.1U_0402_16V4Z~D 1 +1.5V 0.1U_0402_16V4Z~D +V_DDR3_DIMMA_REF2 R1247 2 C171 2 1 1 C187 2 C170 2 1 C205 2 1 1 2 C1013 2 1 C1045 2 1 1 C1046 2 C1064 2 + C197 330U_D2_2V_Y~OK 1K_0402_1%~D +V_DDR3_DIMMA_REF2 1 C204 1 2 1 C186 1 2 R1248 1K_0402_1%~D 10U_0805_6.3V6M~D 10U_0805_6.3V6M~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 2 10U_0805_6.3V6M~D Layout Note: Place near JDIMM1.203 & JDIMM1.204 R1057 1 +3VS DDR_RST_GATE <6,12,20> 2 G C1014 2.2U_0603_6.3V4Z~D 2 1 1 C280 2 C1016 1 2 C281 1 1 2 3 BSS138_SOT23~D C1017 10U_0805_6.3V6M~D H_DIMMA_REF <5> 1 2 2 C276 R1081 205 0.1U_0402_16V4Z~D 10K_0402_5%~D 2 Q37 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 @ R313 100K_0402_5%~D +1.5V DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D6 DDR_A_D7 R56 1K_0402_5%~D DDR_A_D12 DDR_A_D13 DDR_A_DM1 SM_DRAMRST# D SM_DRAMRST# <6,12> DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 G1 G2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDR_A_CKE1 DDR_A_CKE1 <7> DDR_A_MA15 DDR_A_MA14 C DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_CLK1 DDR_A_CLK1# DDR_A_CLK1 <7> DDR_A_CLK1# <7> DDR_A_BS1 DDR_A_RAS# DDR_A_BS1 <7> DDR_A_RAS# <7> DDR_A_CS0# DDR_A_ODT0 DDR_A_CS0# <7> DDR_A_ODT0 <7> DDR_A_ODT1 +V_DDR3_DIMMA_REF2 DDR_A_ODT1 <7> DDR_VREF_CA_DIMMA R1056 1 2 0_0402_5%~D DDR_A_D36 DDR_A_D37 DDR_A_DM4 1 DDR_A_D38 DDR_A_D39 C230 2.2U_0603_6.3V4Z~D DDR_A_D44 DDR_A_D45 1 2 C220 0.1U_0402_16V4Z~D 2 B DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 PM_EXTTS#0_1 SMBDATA SMBCLK PM_EXTTS#0_1 <6,12> SMBDATA <12,13,14,16> SMBCLK <12,13,14,16> +0.75VS 206 FOX_AS0A626-U4RN-7F CONN@ A DDR3 SO-DIMM A Standard Type Compal Secret Data Security Classification 2009/09/21 Issued Date 1U_0603_10V4Z~D1U_0603_10V4Z~D 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 DDR_A_D4 DDR_A_D5 1 C1015 2 1 S +V_DDR3_DIMMA_REF D 1U_0603_10V4Z~D1U_0603_10V4Z~D 1 73 75 77 DDR_A_BS2 79 81 DDR_A_MA12 83 DDR_A_MA9 85 87 DDR_A_MA8 89 DDR_A_MA5 91 93 DDR_A_MA3 95 DDR_A_MA1 97 99 DDR_A_CLK0 101 DDR_A_CLK0# 103 105 DDR_A_MA10 107 DDR_A_BS0 109 111 DDR_A_WE# 113 DDR_A_CAS# 115 117 DDR_A_MA13 119 DDR_A_CS1# 121 123 125 127 DDR_A_D32 129 DDR_A_D33 131 133 DDR_A_DQS#4 135 DDR_A_DQS4 137 139 DDR_A_D34 141 DDR_A_D35 143 145 DDR_A_D40 147 DDR_A_D41 149 151 DDR_A_DM5 153 155 DDR_A_D42 157 DDR_A_D43 159 161 DDR_A_D48 163 DDR_A_D49 165 167 DDR_A_DQS#6 169 DDR_A_DQS6 171 173 DDR_A_D50 175 DDR_A_D51 177 179 DDR_A_D56 181 DDR_A_D57 183 185 DDR_A_DM7 187 189 DDR_A_D58 191 DDR_A_D59 193 195 2 10K_0402_5%~D 197 199 201 203 2 +0.75VS A VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 1 RH 8 VDD 2 1 DDR_A_DQS#2 DDR_A_DQS2 @ R223 @R223 12.1K_0402_1%~D @U45 @ U45 1U_0402_6.3V4Z~D 2 DDR_A_D16 DDR_A_D17 2008/9/8 #400755 Calpella Clarksfield DDR3 SO-DIMM VREFDQ Platform Design Guide Change Details +5VALW 1 DDR_A_D10 DDR_A_D11 1 2 0_0402_5%~D @ +1.5V DDR_A_DQS#1 DDR_A_DQS1 +V_DDR3_DIMMB_REF R1246 M2 Circuit @ C164 2.2U_0805_16V4Z~D 1 2 1K_0402_1%~D VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 2 +1.5V 1 M1 Circuit +1.5V 4 3 2 Title Compal Electronics, Inc. DDRIII-SODIMM SLOT1 Size Document Number Custom NAT02 M/B LA-5154P Date: Rev 1.0 Schematic Sheet Thursday, November 26, 2009 1 11 of 49 5 4 3 2 1 +1.5V +1.5V M1 Circuit JDIMM2 M1 Circuit 2008/9/8 #400755 Calpella Clarksfield DDR3 SO-DIMM VREFDQ Platform Design Guide Change Details 1 +1.5V +V_DDR3_DIMMB_REF R166 VREF_DQB 2 0_0402_5%~D 1 DDR_B_D0 DDR_B_D1 M3 Circuit <5> H_DIMMB_REF R165 2 0_0402_5%~D 1 DDR_B_DM0 +V_DDR3_DIMMB_REF R1230 VREF_POT1_R 2 1K_0402_1%~D R186 1 @ DDR_B_D2 DDR_B_D3 2 0_0402_5%~D +V_DDR3_DIMMB_REF DDR_B_D8 DDR_B_D9 R1231 DDR_B_DQS#1 DDR_B_DQS1 1 D C110 1K_0402_1%~D 2 <7> DDR_B_DQS#[0..7] DDR_B_D10 DDR_B_D11 2 DDR_B_D16 DDR_B_D17 0.1U_0402_16V4Z~D <7> DDR_B_DM[0..7] 2 G DDR_B_DQS#2 DDR_B_DQS2 3 DDR_B_D18 DDR_B_D19 <7> DDR_B_MA[0..15] H_DIMMB_REF <5> 2 1 S Q44 1 <7> DDR_B_DQS[0..7] D +V_DDR3_DIMMB_REF C122 2.2U_0805_16V4Z~D 2 <7> DDR_B_D[0..63] DDR_RST_GATE <6,11,20> 1 PCH_SMBCLK <6,11,16> PCH_SMBCLK @ R321 100K_0402_5%~D DDR_B_D24 DDR_B_D25 PCH_SMBDATA <6,11,16> PCH_SMBDATA DDR_B_DM3 1 BSS138_SOT23~D DDR_B_D26 DDR_B_D27 M2 Circuit DDR_B_D4 DDR_B_D5 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D6 DDR_B_D7 DDR_B_D12 DDR_B_D13 D DDR_B_DM1 SM_DRAMRST# SM_DRAMRST# <6,11> DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21 DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 5 VREF_RW_POT1 5 + SDA 4 6 - ISL90728WIE627Z-TK_SC70-6 @ R197 12.1K_0402_1%~D 2.2_0402_5%~D 1 @ R194 10_0402_5%~D 2 PCH_SMBDATA VREF_POT1_R 2 1 RW SCL P GND 3 1 2 @ U46B LM358DT_SO8 @ R193 1 0 7 G 2 8 6 RH 2 PP_S4GT PP_S4GT 1 <11> <7> DDR_B_CLK0 <7> DDR_B_CLK0# 2 PP_S4GT_Q_1 D 3 VREF_OPAMP_POT1 @ C128 1U_0402_6.3V4Z~D S @ Q49 2N7002LT1G_SOT23-3 2 G <7> DDR_B_BS0 <7> DDR_B_WE# <7> DDR_B_CAS# <7> DDR_B_CS1# Layout Note: Place near JDIMM2 Layout Note: Place these 4 Caps near Command and Control signals of DIMMA B +1.5V 10U_0805_6.3V6M~D 10U_0805_6.3V6M~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 1 2 10U_0805_6.3V6M~D 1 C206 C188 2 1 C173 2 10U_0805_6.3V6M~D 1 C189 2 1 C207 2 10U_0805_6.3V6M~D 1 C1047 2 10U_0805_6.3V6M~D 1 2 C1048 1 C1049 2 0.1U_0402_16V4Z~D 1 C1050 2 1 2 + C198 330U_D2_2V_Y~OK 2 0.1U_0402_16V4Z~D Layout Note: Place near JDIMM2.203 & JDIMM2.204 R1059 1 +3VS +0.75VS 1 R1082 1U_0603_10V4Z~D C1020 A 2.2U_0603_6.3V4Z~D C1018 2 C282 2 C283 2 C1019 2 1U_0603_10V4Z~D 1 1 1 1 1 C298 2 1 2 1 2 C277 0.1U_0402_16V4Z~D CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 G2 206 G1 DDR_B_CKE1 <7> DDR_B_MA15 DDR_B_MA14 C DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_CLK1 DDR_B_CLK1# 2010/09/21 Deciphered Date 4 3 2 DDR_B_BS1 <7> DDR_B_RAS# <7> DDR_B_CS0# DDR_B_ODT0 DDR_B_CS0# <7> DDR_B_ODT0 <7> DDR_B_ODT1 +V_DDR3_DIMMB_REF2 DDR_B_ODT1 <7> DDR_VREF_CA_DIMMB R1058 1 2 0_0402_5%~D DDR_B_D36 DDR_B_D37 DDR_B_DM4 C231 DDR_B_D38 DDR_B_D39 1 1 2.2U_0603_6.3V4Z~D 2 2 C221 0.1U_0402_16V4Z~D B DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 M1 Circuit DDR_B_D46 DDR_B_D47 +1.5V DDR_B_D52 DDR_B_D53 +V_DDR3_DIMMB_REF2 R1249 DDR_B_DM6 1K_0402_1%~D DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 +V_DDR3_DIMMB_REF2 R1250 DDR_B_DQS#7 DDR_B_DQS7 1K_0402_1%~D DDR_B_D62 DDR_B_D63 PM_EXTTS#0_1 SMBDATA SMBCLK PM_EXTTS#0_1 <6,11> SMBDATA <11,13,14,16> SMBCLK <11,13,14,16> +0.75VS A DDR3 SO-DIMM B Standard Type Compal Secret Data 2009/09/21 Issued Date 1U_0603_10V4Z~D DDR_B_CLK1 <7> DDR_B_CLK1# <7> DDR_B_BS1 DDR_B_RAS# FOX_AS0A626-U8RN-7F CONN@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 DDR_B_CKE1 10U_0805_6.3V6M~D Security Classification 1U_0603_10V4Z~D 205 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 1 @ R196 12.1K_0402_1%~D VDD 73 75 77 DDR_B_BS2 79 81 DDR_B_MA12 83 DDR_B_MA9 85 87 DDR_B_MA8 89 DDR_B_MA5 91 93 DDR_B_MA3 95 DDR_B_MA1 97 99 DDR_B_CLK0 101 DDR_B_CLK0# 103 105 DDR_B_MA10 107 DDR_B_BS0 109 111 DDR_B_WE# 113 DDR_B_CAS# 115 117 DDR_B_MA13 119 DDR_B_CS1# 121 123 125 127 DDR_B_D32 129 DDR_B_D33 131 133 DDR_B_DQS#4 135 DDR_B_DQS4 137 139 DDR_B_D34 141 DDR_B_D35 143 145 DDR_B_D40 147 DDR_B_D41 149 151 DDR_B_DM5 153 155 DDR_B_D42 157 DDR_B_D43 159 161 DDR_B_D48 163 DDR_B_D49 165 167 DDR_B_DQS#6 169 DDR_B_DQS6 171 173 DDR_B_D50 175 DDR_B_D51 177 179 DDR_B_D56 181 DDR_B_D57 183 185 DDR_B_DM7 187 189 DDR_B_D58 191 DDR_B_D59 193 195 2 10K_0402_5%~D 197 199 2 201 10K_0402_5%~D 203 2 <7> DDR_B_BS2 4 1 2 PCH_SMBCLK 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 +5VALW 1 @ U8 C172 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 DDR_B_CKE0 <7> DDR_B_CKE0 1 @ C156 1U_0402_6.3V4Z~D VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 +1.5V +3V C 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Title Compal Electronics, Inc. DDRIII-SODIMM SLOT2 Size Document Number Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 12 of 49 A B C D E F G H +CLK_VDD +CLK_VDDSRC 0.1U_0402_16V4Z~D L79 2 1 FBMA-L11-201209-221LMA30T_0805 +1.05VS 1 2 1 C1052 C1051 10U_0805_10V4Z~D 1 1 10U_0805_10V4Z~D 2 1 C979 2 2 1 C1053 0.1U_0402_16V4Z~D 2 0.1U_0402_16V4Z~D L80 2 1 FBMA-L11-201209-221LMA30T_0805 +3VS 1 @ CU53 47P_0402_50V8J~D 2 C1061 C1065 10U_0805_10V4Z~D 0.1U_0402_16V4Z~D 1 1 2 1 C1054 2 1 C1055 2 1 C1056 2 10U_0805_10V4Z~D 0.1U_0402_16V4Z~D C1057 2 1 2 1 C1058 0.1U_0402_16V4Z~D 2 @ CU54 47P_0402_50V8J~D 1 0.1U_0402_16V4Z~D +CLK_VDDSRC +CLK_VDDSRC Clock Generator +CLK_VDD +CLK_VDD U49 Integrated 33ohm Resistor <16> CLK_BUF_DREF_96M <16> CLK_BUF_DREF_96M# CLK_BUF_DREF_96M CLK_BUF_DREF_96M# R1004 R1005 1 0_0402_5%~D 2 1 0_0402_5%~D 2 CLK_BUF_DREF_96M_R CLK_BUF_DREF_96M#_R 2 <16> CLK_BUF_PCIE_SATA <16> CLK_BUF_PCIE_SATA# <16> CLK_BUF_CPU_DMI <16> CLK_BUF_CPU_DMI# CLK_BUF_PCIE_SATA CLK_BUF_PCIE_SATA# R1006 R1008 CLK_BUF_PCIE_SATA_R 1 0_0402_5%~D 2 CLK_BUF_PCIE_SATA#_R 1 0_0402_5%~D 2 CLK_BUF_CPU_DMI CLK_BUF_CPU_DMI# R1010 R1011 1 0_0402_5%~D 2 1 0_0402_5%~D 2 CLK_BUF_CPU_DMI_R CLK_BUF_CPU_DMI#_R H_STP_CPU# Integrated 33ohm Resistor 1 2 3 4 5 6 7 8 VDD_USB_48 VSS_48M DOT_96 DOT_96# VDD_27 27MHZ 27MHZ_SS USB_48 9 10 11 12 13 14 15 16 VSS_27M SATA SATA# VSS_SRC SRC_1 SRC_1# VDD_SRC_IO CPU_STOP# 33 IDT: 9LRS3191AKLFT SILEGO: SLG8SP585 SCL SDA REF_0/CPU_SEL VDD_REF XTAL_IN XTAL_OUT VSS_REF CKPWRGD/PD# 32 31 30 29 28 27 26 25 VDD_CPU CPU_0 CPU_0# VSS_CPU CPU_1 CPU_1# VDD_CPU_IO VDD_SRC 24 23 22 21 20 19 18 17 SMBCLK SMBDATA REF_0/CPU_SEL R633 1 CLK_XTAL_IN CLK_XTAL_OUT 2 10P_0402_50V8J~D 1 C1109 R1.0 modify CK505_PW RGD SMBCLK <11,12,14,16> SMBDATA <11,12,14,16> CLK_BUF_ICH_14M <16> 2 33_0402_5%~D @ 2 CLK_BUF_CPU_BCLK_R CLK_BUF_CPU_BCLK#_R R1007 R1009 1 0_0402_5%~D 2 1 0_0402_5%~D 2 CLK_BUF_CPU_BCLK CLK_BUF_CPU_BCLK# CLK_BUF_CPU_BCLK <16> CLK_BUF_CPU_BCLK# <16> Integrated 33ohm Resistor TGND SLG8SP587VTR_QFN32_5X5 2 +CLK_VDD R631 10K_0402_5%~D 1 +CLK_VDD Silego Have Internal Pull-Up CK505_PW RGD R632 0_0402_5%~D @ 1 2 VGATE <17,31,46> 1 D R627 1 2 10K_0402_5%~D H_STP_CPU# 3 S 3 +CLK_VDDSRC 2 CLK_ENABLE# <46> G Q45 2N7002LT1G_SOT23-3 3 @ R1140 1 2 10K_0402_5%~D R634 1 2 10K_0402_5%~D REF_0/CPU_SEL C1059 2 R1141 @ 1M_0402_5%~D Y6 14.31818MHz_20P_FSX8L14.318181M20FDB~OK CLK_XTAL_OUT PIN 30 CPU_0 CPU_1 0 (Default) 133MHz 133MHz 1 100MHz 100MHz 2 2 IDT Have Internal Pull-Down 33P_0402_50V8J~D 1 1 1 CLK_XTAL_IN 2 1 C1060 33P_0402_50V8J~D 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D E F Title Clock Generator (CK505) Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 G Sheet 13 of H 49 FAN Control circuit Free Fall Sensor +FAN1_POWER +3VS C77 10U_1206_16V4Z~D 2 1 +5VS +3VS 1 C96 C91 1000P_0402_50V7K~D 2 1 2 10U_1206_16V4Z~D R1134 1 2 U7 1 2 3 4 EN_DFAN1 <31> EN_DFAN1 +3VS_ACL_IO +3VS VEN VIN VO VSET GND GND GND GND 8 7 6 5 0_0603_5%~D 1 1 2 C1067 10U_0805_10V4Z~D U50 DE351DLTR 1 JFAN1 +FAN1_POWER 2 2 1 2 3 1 2 G 3 G +3VS_ACL_IO +3VS 4 5 <19> ACCEL_INT# MOLEX_53261-0371~D CONN@ 1 1 6 VDD_IO VDD 8 9 INT 1 INT 2 12 13 14 <11,12,13,16> SMBDATA <11,12,13,16> SMBCLK +3VS 1 R1135 2 7 10K_0402_5%~D 2 4 5 10 GND GND GND GND +3VS SDO SDA / SDI / SDO SCL / SPC RSVD CS RSVD 3 11 DE351DLTR_LGA14_3X5 Must be placed in the center of the system. P/N : SA000039C00 (S IC DE351DLTR LGA 14P MOTION SENSOR) Power Button for debug only BTN TOP 2 3 1 4 2 SWO1 @ SMT1-05_4P PWR_ON-OFF_BTN# PWR_ON-OFF_BTN# <32> 3 4 SWO2 @ SMT1-05_4P 6 5 1 6 5 C98 0.1U_0402_16V4Z~D 2 RT9027BPS_SO8 40mil R141 10K_0402_5%~D <31> FAN_SPEED1 C1066 0.1U_0402_16V4Z~D Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title FAN & Screw Hole Size B Date: Document Number Rev 1.0 NAT02 M/B LA-5154P Schematic Thursday, November 26, 2009 Sheet 14 of 49 5 2 C398 18P_0402_50V8J~D 2 1 RC Delay 18~25mS close to RAM door PCH_RTCX1 @ 1 3 NC OSC 4 2 NC OSC 1 1 X2 C15 1U_0603_10V6K~D 1 2 R1100 U47A 10M_0402_5%~D 32.768KHZ_12.5PF_Q13MC14610002 C402 2 1 D REV1.0 B13 D13 RTCX1 RTCX2 PCH_RTCRST# C14 RTCRST# PCH_SRTCRST# D17 SRTCRST# PCH_RTCX2 FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 D33 B33 C32 A32 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 FWH4 / LFRAME# C34 LPC_FRAME# LDRQ0# LDRQ1# / GPIO23 A34 F34 SERIRQ AB9 1 @ 2 1M_0402_5%~D SM_INTRUDER# A16 INTRUDER# R51 1 2 330K_0402_5%~DPCH_INTVRMEN A14 INTVRMEN HDA_BITCLK_PCH A30 HDA_BCLK HDA_SYNC_PCH D29 HDA_SYNC INTVRMEN - Integrated SUS 1.1V VRM Enable High - Enable Internal VRs C13 1U_0603_10V6K~D 1 2 HDA for AUDIO R1083 R1084 <25> HDA_RST_AUDIO# R1085 <25> HDA_SDOUT_AUDIO R1086 1 1 1 HDA_BITCLK_PCH 2 33_0402_5%~D HDA_SYNC_PCH 2 33_0402_5%~D HDA_RST_PCH# 2 33_0402_5%~D HDA_SDOUT_PCH 2 33_0402_5%~D HDA_RST_PCH# <25> HDA_SDIN0 C30 HDA_RST# G30 HDA_SDIN0 F30 HDA_SDIN1 E32 HDA_SDIN2 F32 HDA_SDIN3 C HDA_BITCLK_AUDIO 2 10P_0402_50V8J~D 1 C1110 HDA_SDOUT_PCH @ R1024 R1232 <31,32> TOUCHKEY_TINT 1 1 @ 2 0_0402_5%~D 2 1K_0402_5%~D GPIO33 pull down only for ME disable +3VS B SPKR B29 HDA_SDO H32 HDA_DOCK_EN# / GPIO33 J30 HDA_DOCK_RST# / GPIO13 PCH_JTAG_TCK M3 JTAG_TCK PCH_JTAG_TMS K3 JTAG_TMS PCH_JTAG_TDI K1 JTAG_TDI PCH_JTAG_TDO J2 JTAG_TDO PCH_JTAG_RST# J4 TRST# PCH_SPI_CLK_1 R584 1 PCH_SPI_CLK_2 RU86 1 @ PCH_SPI_CS0# R571 1 2 0_0402_5%~D PCH_SPI_CLK BA2 2 0_0402_5%~D 2 15_0402_5%~DPCH_SPI_CS0#_R AV3 PCH_SPI_CS1# RU87 1 @ 2 15_0402_5%~DPCH_SPI_CS1#_R AY3 PCH_SPI_MOSI_1 PCH_SPI_MOSI_2 PCH_SPI_MISO_1 PCH_SPI_MISO_2 R575 RU88 R565 RU89 2 2 2 2 SATA1RXN SATA1RXP SATA1TXN SATA1TXP AH6 AH5 AH9 AH8 SATA2RXN SATA2RXP SATA2TXN SATA2TXP AF11 AF9 AF7 AF6 SATA3RXN SATA3RXP SATA3TXN SATA3TXP AH3 AH1 AF3 AF1 SATA4RXN SATA4RXP SATA4TXN SATA4TXP AD9 AD8 AD6 AD5 SATA5RXN SATA5RXP SATA5TXN SATA5TXP AD3 AD1 AB3 AB1 SERIRQ SATA_ITX_DRX_N0 SATA_ITX_DRX_P0 <31> 0.01U_0402_16V7K~D1 0.01U_0402_16V7K~D1 SATA_ITX_DRX_N1 C963 2 SATA_ITX_DRX_P1 C964 2 SATA_IRX_DTX_N0 <29> SATA_IRX_DTX_P0 <29> SATA_ITX_C_DRX_N0 <29>SATA SATA_ITX_C_DRX_P0 <29> 2 C961 2 C962 SATA_IRX_DTX_N1 <29> SATA_IRX_DTX_P1 <29> SATA SATA_ITX_C_DRX_N1 <29> SATA_ITX_C_DRX_P1 <29> 1 0.01U_0402_16V7K~D 1 0.01U_0402_16V7K~D for HDD1 for HDD2 From PCH EDS 5.16, SATA port2 & 3 are not available in all sku. SATA_ITX_DRX_N4 SATA_ITX_DRX_P4 SATA_ITX_DRX_N5 SATA_ITX_DRX_P5 0.01U_0402_16V7K~D1 0.01U_0402_16V7K~D1 0.01U_0402_16V7K~D1 0.01U_0402_16V7K~D1 C 2 C965 2 C966 SATA_IRX_DTX_N4 <29> SATA_IRX_DTX_P4 <29> SATA_ITX_C_DRX_N4 <29> SATA_ITX_C_DRX_P4 <29> 2 C967 2 C968 SATA_IRX_DTX_N5 <30> SATA_IRX_DTX_P5 <30> SATA_ITX_C_DRX_N5 <30>SATA SATA_ITX_C_DRX_P5 <30> SATA for ODD for eSATA +1.05VS SATAICOMPO AF16 SATAICOMPI AF15 SATA_COMP R139 1 2 37.4_0402_1%~OK SPI_CLK +3VS SPI_CS0# PCH_SATALED# R129 1 2 10K_0402_5%~D SATALED# T3 SATA0GP / GPIO21 Y9 R77 1 @ 2 10K_0402_5%~D SATA1GP / GPIO19 V1 R116 1 @ 2 10K_0402_5%~D SPI_CS1# +3VS B R1120 1K_0402_5%~D @ 1 2 PCH_SPKR 1 2 SERIRQ R115 10K_0402_5%~D 1 1 @ 1 1 @ 15_0402_5%~D PCH_SPI_MOSI AY1 15_0402_5%~D 33_0402_5%~D PCH_SPI_MISO AV1 33_0402_5%~D SPI_MOSI SPI_MISO IBEXPEAK-M_FCBGA1071~D @ @ +3V PAD T110 PAD T111 R111 +1.05VS 2 51_0402_1%~D 2 200_0402_5%~D 2 100_0402_1%~D @ PCH_JTAG_TDO R1131 1 R1104 1 R1105 1 2 51_0402_1%~D 2 200_0402_5%~D 2 100_0402_1%~D R1132 1 R1106 1 R1107 1 @ PCH_JTAG_TDI @ PCH_JTAG_RST# R1133 1 R1108 1 R1109 1 2 51_0402_1%~D 2 200_0402_5%~D 2 100_0402_1%~D R82 10K_0402_5%~D 10K_0402_5%~D 2 @ PCH_JTAG_TMS R1130 1 R1101 1 R1102 1 1 <25> HDA_SYNC_AUDIO 1 P1 AK7 AK6 AK11 AK9 D LPC_FRAME# <27,31> SERIRQ SATA0RXN SATA0RXP SATA0TXN SATA0TXP <27,31> <27,31> <27,31> <27,31> 2008 Intel MOW36/MOW50 2 <25> HDA_BITCLK_AUDIO PCH_SPKR <25> PCH_SPKR LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 1 2 ME1 1 SATA close to RAM door R64 RTC +RTCVCC IHDA RC Delay 18~25mS JTAG R36 20K_0402_1%~D SPI +RTCVCC PCH_SRTCRST# 2 LPC 18P_0402_50V8J~D 1 1 PCH_RTCRST# 1 2 R46 20K_0402_1%~D 2 CMOS1 3 2 +RTCVCC 4 +3VS U68 TDO: Reserved on ES1 Sample Mount R1104, R1105 on ES2 Sample PCH_SPI_CS1# RU91 PCH_SPI_MISO_2 SPI_W P2# 1 2 @ 3.3K_0402_5%~D +3VS MP mount R1130, R1131, R1132, R1133 and remove others 1 2 3 4 CS# SO WP# GND 8 7 6 5 VCC HOLD# SCLK SI SPI_HOLD2# 3.3K_0402_5%~D2 PCH_SPI_CLK_2 PCH_SPI_MOSI_2 @ MX25L1605AM2C-12G_SO8 1 RU90 @ +3VS SPI Flash (32Mbit/4Mbyte) +3VS U29 2 51_0402_1%~D 2 20K_0402_1%~D 2 10K_0402_5%~D PCH_SPI_CS0# 1 /CS VCC 8 PCH_SPI_MISO_1 2 DO /HOLD 7 SPI_HOLD1# 3 /WP CLK 6 PCH_SPI_CLK_1 4 GND DIO 5 PCH_SPI_MOSI_1 R1110 SPI_W P1# 1 2 3.3K_0402_5%~D +3VS A 3.3K_0402_5%~D2 1 R1122 +3VS Change to SA000021A0L A MX25L3205DM2I-12G_SO8~D 2009/09/21 Issued Date PCH_SPI_MOSI R173 1 @ 2 1K_0402_5%~D enable iTPM: SPI_MOSI High 5 PCH_JTAG_TCK R1111 1 2 4.7K_0402_5%~D CRB 1.0 Change to 4.7K 4 Compal Electronics, Inc. Compal Secret Data Security Classification +3VS Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Title PCH (1/9) SATA,HDA,SPI, LPC Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 15 of 49 5 4 3 2 1 U47B <27> CLK_PCIE_WAN# <27> CLK_PCIE_WAN <27> WWAN_CLKREQ# <27> CLK_PCIE_WLAN# <27> CLK_PCIE_WLAN MiniWLAN --> <27> WLAN_CLKREQ# T112PAD B Express card --> 10/100/1G LAN --> 2 0_0402_5%~D 1 PCH_GPIO73 R1123 1 R1124 1 2 0_0402_5%~D R_CLK_PCIE_WLAN# 2 0_0402_5%~D R_CLK_PCIE_WLAN R93 2 0_0402_5%~D 1 AK48 AK47 P9 PCH_GPIO18 R1012 1 R1013 1 2 0_0402_5%~D R_CLK_PCIE_WPAN# 2 0_0402_5%~D R_CLK_PCIE_WPAN R1014 1 2 0_0402_5%~D <30> CLK_PCIE_CB# <30> CLK_PCIE_CB R1015 1 R1016 1 2 0_0402_5%~D R_CLK_PCIE_CB# 2 0_0402_5%~D R_CLK_PCIE_CB <30> CB_CLKREQ# R1017 1 2 0_0402_5%~D <28> CLK_PCIE_EXPR# <28> CLK_PCIE_EXPR R558 1 R563 1 2 0_0402_5%~D R_CLK_PCIE_EXPR# 2 0_0402_5%~D R_CLK_PCIE_EXPR <28> EXP_CLKREQ# R1018 1 2 0_0402_5%~D <24> CLK_PCIE_GLAN# <24> CLK_PCIE_GLAN R1019 1 R1020 1 2 0_0402_5%~D R_CLK_PCIE_GLAN# 2 0_0402_5%~D R_CLK_PCIE_GLAN <24> GLAN_CLKREQ# R1021 1 2 0_0402_5%~D <28> WPAN_CLKREQ# T113PAD Card Reader --> 2 0_0402_5%~D R_CLK_PCIE_WAN# 2 0_0402_5%~D R_CLK_PCIE_WAN R76 AM43 AM45 U4 PCH_GPIO20 AM47 AM48 N4 @ AH42 AH41 PCH_GPIO25 PCH_GPIO26 A8 AM51 AM53 M9 PCH_GPIO44 AJ50 AJ52 H6 AK53 AK51 +3VS R1112 1 R1022 1 R84 2 10K_0402_5%~D +3VS WWAN_CLKREQ# 5 S 2 G D SMBDATA <11,12,13,14> PCH_SMBCLK PEG_CLKREQ#_R R43 1 3 2 10K_0402_5%~D 1 R635 4.7K_0402_5%~D 1 2 +3VS S H1 +3V 2 G PEG_A_CLKRQ# / GPIO47 R52 2.2K_0402_5%~D 2 1 SMBCLK SMBCLK <11,12,13,14> Q46 2N7002LT1G_SOT23-3 PCIECLKRQ1# / GPIO18 CLKOUT_PCIE2N CLKOUT_PCIE2P AD43 AD45 +3VS CLKOUT_DMI_N CLKOUT_DMI_P AN4 AN2 CLK_CPU_DMI# <6> CLK_CPU_DMI <6> CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P AT1 AT3 CLK_CPU_DP# <6> CLK_CPU_DP <6> PCIECLKRQ3# / GPIO25 CLKOUT_PCIE4N CLKOUT_PCIE4P AP3 AP1 CLK_BUF_CPU_BCLK# <13> CLK_BUF_CPU_BCLK <13> CLKIN_DOT_96N CLKIN_DOT_96P F18 E18 CLK_BUF_DREF_96M# <13> CLK_BUF_DREF_96M <13> AH13 AH12 CLK_BUF_PCIE_SATA# <13> CLK_BUF_PCIE_SATA <13> REFCLK14IN P41 CLK_BUF_ICH_14M CLKIN_PCILOOPBACK J42 CLK_PCI_FB <19> PCIECLKRQ4# / GPIO26 XTAL25_IN XTAL25_OUT AH51 AH53 XCLK_RCOMP AF38 R127 1 3 EC_SMB_CK2 EC_SMB_CK2 <27,28,31> +3VS R1149 2.2K_0402_5%~D 2 1 +3V PCH_SML1DAT 1 3 EC_SMB_DA2 EC_SMB_DA2 <27,28,31> Q58 2N7002LT1G_SOT23-3 Buffer Mode check is need or not <13> C1027 27P_0402_50V8J~D 1 2 XTAL25_IN XTAL25_OUT XCLK_RCOMP 1 Q57 2N7002LT1G_SOT23-3 CLKIN_BCLK_N CLKIN_BCLK_P CLKOUT_PCIE3N CLKOUT_PCIE3P C PCH_SML1CLK CLK_BUF_CPU_DMI# <13> CLK_BUF_CPU_DMI <13> CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P PCIECLKRQ2# / GPIO20 +3V AW 24 BA24 CLKIN_DMI_N CLKIN_DMI_P R1147 2.2K_0402_5%~D 2 1 2 90.9_0402_1%~D+1.05VS R548 1M_0402_5%~D R0.3 Modify XTAL25_IN should be pulled to GND using a 0Ω resistor. (Calpella_Schematic_Checklist_Rev1.6) B Y2 25MHZ_20P CLKOUT_PCIE5N CLKOUT_PCIE5P PCIECLKRQ5# / GPIO44 CLKOUT_PEG_B_N CLKOUT_PEG_B_P PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX0 / GPIO64 T45 CLKOUTFLEX1 / GPIO65 P43 CLKOUTFLEX2 / GPIO66 T42 CLKOUTFLEX3 / GPIO67 N50 1 2 C1028 27P_0402_50V8J~D Note: ADD 25MHz crystal for Display Clock Integration Q64 +3VS @ 1 2 R1204 10K_0402_5%~D 2 10K_0402_5%~D @ 1 R1207 EXP_CLKREQ# +3VS Q65 PCH_GPIO26 1 2N7002LT1G_SOT23-3 3 1 @ R1208 @ 1 2 R1205 10K_0402_5%~D 2 10K_0402_5%~D GLAN_CLKREQ# 3 Q66 PCH_GPIO44 1 2N7002LT1G_SOT23-3 A @ @ 1 2 R1209 10K_0402_5%~D 2 10K_0402_5%~D @ 1 R1210 2 +3VS 3 @ 4 Q67 PCH_GPIO25 1 2N7002LT1G_SOT23-3 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 2010/09/21 Deciphered Date Title PCH (2/9) PCIE, SMBUS, CLK D 2 10K_0402_5%~D 2 10K_0402_5%~D 1 1 T9 @ S R54 R95 CLKOUT_PCIE1N CLKOUT_PCIE1P @ CB_CLKREQ# PCH_GPIO44 PCH_GPIO56 SMBDATA Remove PCIECLKRQ0# / GPIO73 PCH_GPIO73 1 2N7002LT1G_SOT23-3 3 G 1 3 D PCH_GPIO74 CL_RST1# S 2 10K_0402_5%~D 2 10K_0402_5%~D 2 10K_0402_5%~D 1 +3VS G R78 1 R1087 1 R1023 1 T11 D PCH_GPIO60 PCH_GPIO25 PCH_GPIO26 T13 S 2 10K_0402_5%~D CL_CLK1 G 1 PCH_SMBDATA Q47 2N7002LT1G_SOT23-3 CL_DATA1 CLKOUT_PEG_A_N CLKOUT_PEG_A_P CLKOUT_PCIE0N CLKOUT_PCIE0P D 2 10K_0402_5%~D R81 S R1113 1 PCH_GPIO73 @ 1 2 R1203 10K_0402_5%~D 2 10K_0402_5%~D @ 1 R1206 G EC_LID_OUT# PCH_SML1DAT IBEXPEAK-M_FCBGA1071~D +3V A P13 2 10K_0402_5%~D 2 10K_0402_5%~D 2 PCH_GPIO20 PCH_GPIO18 PCH_GPIO56 PCH_SML1CLK G12 R638 4.7K_0402_5%~D 1 2 +3VS S PERN8 PERP8 PETN8 PETP8 @ <28> CLK_PCIE_WPAN# <28> CLK_PCIE_WPAN MiniWPAN --> R551 1 R550 1 BG34 BJ34 BG36 BJ36 E10 R53 2.2K_0402_5%~D 2 1 2 MiniWWAN --> PERN7 PERP7 PETN7 PETP7 SML1CLK / GPIO58 SML1DATA / GPIO75 +3V S C AT34 AU34 AU36 AV36 PCH_GPIO74 D C1025 2 C1026 2 PERN6 PERP6 PETN6 PETP6 M14 2 G 1 1 PCIE_IRX_GLANTX_N6 BA34 PCIE_IRX_GLANTX_P6 AW 34 PCIE_ITX_GLANRX_N6 BC34 0.1U_0402_16V7K~D PCIE_ITX_GLANRX_P6 BD34 0.1U_0402_16V7K~D SML1ALERT# / GPIO74 D +3VS D <24> PCIE_IRX_GLANTX_N6 <24> PCIE_IRX_GLANTX_P6 --> <24> PCIE_ITX_C_GLANRX_N6 <24> PCIE_ITX_C_GLANRX_P6 PERN5 PERP5 PETN5 PETP5 G8 2 G C973 2 C974 2 BF33 BH33 BG32 BJ32 C6 D <28> PCIE_IRX_EXPTX_N5 <28> PCIE_IRX_EXPTX_P5 <28> PCIE_ITX_C_EXPRX_N5 <28> PCIE_ITX_C_EXPRX_P5 J14 1 1 1 PCIE_IRX_EXPTX_N5 PCIE_IRX_EXPTX_P5 PCIE_ITX_EXPRX_N5 0.1U_0402_16V7K~D PCIE_ITX_EXPRX_P5 0.1U_0402_16V7K~D PERN4 PERP4 PETN4 PETP4 PCH_SMBDATA <6,11,12> PCH_GPIO60 2 10/100/1G LAN C971 2 C972 2 BA32 BB32 BD32 BE32 PCH_SMBCLK <6,11,12> C8 1 1 1 PCIE_IRX_CBTX_N4 PCIE_IRX_CBTX_P4 PCIE_ITX_CBRX_N4 0.1U_0402_16V7K~D PCIE_ITX_CBRX_P4 0.1U_0402_16V7K~D H14 SML0DATA 1. Connect Directly XDCP of DDR3 2. Level Shift1, Pull-Up to +3VS CLOCK GEN, DIMM1, DIMM2, FFS 3. Level Shift2, Pull-Up to +3VS CPU & PCH XDP EC_LID_OUT# <31> 2 Express card --> <30> PCIE_IRX_CBTX_N4 <30> PCIE_IRX_CBTX_P4 <30> PCIE_ITX_C_CBRX_N4 <30> PCIE_ITX_C_CBRX_P4 PERN3 PERP3 PETN3 PETP3 EC_LID_OUT# B9 SML0CLK 2 Card Reader --> C969 2 C970 2 SML0ALERT# / GPIO60 SMBus 1 1 PCIE_IRX_WPANTX_N3 AU30 PCIE_IRX_WPANTX_P3 AT30 PCIE_ITX_WPANRX_N3 AU32 0.1U_0402_16V7K~D PCIE_ITX_WPANRX_P3 AV32 0.1U_0402_16V7K~D Link MiniWPAN --> <28> PCIE_IRX_WPANTX_N3 <28> PCIE_IRX_WPANTX_P3 <28> PCIE_ITX_C_WPANRX_N3 <28> PCIE_ITX_C_WPANRX_P3 PERN2 PERP2 PETN2 PETP2 Controller 1 1 D SMBCLK SMBDATA PEG C1023 2 C1024 2 PCIE_IRX_WLANTX_N2 AW 30 PCIE_IRX_WLANTX_P2 BA30 PCIE_ITX_WLANRX_N2 BC30 0.1U_0402_16V7K~D PCIE_ITX_WLANRX_P2 BD30 0.1U_0402_16V7K~D SMBALERT# / GPIO11 PCI-E* <27> PCIE_IRX_WLANTX_N2 <27> PCIE_IRX_WLANTX_P2 --><27> PCIE_ITX_C_WLANRX_N2 <27> PCIE_ITX_C_WLANRX_P2 1 1 REV1.0 PERN1 PERP1 PETN1 PETP1 From CLK BUFFER MiniWLAN C1021 2 C1022 2 BG30 BJ30 BF29 BH29 Clock Flex <27> PCIE_IRX_WANTX_N1 <27> PCIE_IRX_WANTX_P1 <27> PCIE_ITX_C_WANRX_N1 <27> PCIE_ITX_C_WANRX_P1 MiniWWAN --> PCIE_IRX_WANTX_N1 PCIE_IRX_WANTX_P1 PCIE_ITX_WANRX_N1 0.1U_0402_16V7K~D PCIE_ITX_WANRX_P1 0.1U_0402_16V7K~D THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 16 of 49 5 4 3 2 1 +3V @ BE22 BF21 BD20 BE18 DMI0TXN DMI1TXN DMI2TXN DMI3TXN <5> DMI_PTX_HRX_P0 <5> DMI_PTX_HRX_P1 <5> DMI_PTX_HRX_P2 <5> DMI_PTX_HRX_P3 +1.05VS R590 49.9_0402_1%~D 1 2 BD22 BH21 BC20 BD18 DMI0TXP DMI1TXP DMI2TXP DMI3TXP PCH_GPIO72 2 8.2K_0402_5%~D PM_SLP_LAN# 2 10K_0402_5%~D SUS_PW R_ACK 2 10K_0402_5%~D EC_SW I# 2 10K_0402_5%~D ICH_PCIE_W AKE# 2 1K_0402_5%~D BH25 DMI_COMP R58 R70 2 2 @ <31> SUS_PW R_ACK MEPWROK A10 LAN_RST# D9 SUS_PW R_ACK C16 M1 DRAMPWROK RSMRST# <6,31> PBTN_OUT# 2 10K_0402_5%~D 2 D50 CH751H-40PT_SOD323-2~D PBTN_OUT# P5 PCH_ACIN P7 ACPRESENT / GPIO31 PCH_GPIO72 A6 BATLOW# / GPIO72 1 1 EC_SW I# PWRBTN# <5> <5> <5> <5> <5> <5> <5> <5> H_FDI_INT BF13 H_FDI_FSYNC0 FDI_FSYNC1 BH13 H_FDI_FSYNC1 <5> FDI_LSYNC0 BJ12 H_FDI_LSYNC0 <5> FDI_LSYNC1 BG14 H_FDI_LSYNC1 <5> J12 ICH_PCIE_W AKE# CLKRUN# / GPIO32 Y1 PM_CLKRUN# SUS_STAT# / GPIO61 P8 PCH_GPIO61 @ PAD T4 SUSCLK / GPIO62 F3 PCH_GPIO62 @ PAD T7 SLP_S5# / GPIO63 E4 SLP_S5# SLP_S4# H7 PM_SLP_S4# <11> SLP_S3# P12 SLP_S3# <31> SLP_M# K8 PM_SLP_M# @ PAD T2 TP23 N2 PM_SLP_DSW # @ PAD T8 ICH_PCIE_W AKE# 5 P G D 1 0_0402_5%~D <5> C <24,27,28,31> R30 PCH_RSMRST# @ 2 1 0_0402_5%~D Q50 MMBT3906_SOT23-3 1 3 EC_RSMRST# <31> R32 10K_0402_5%~D R27 1 2 4.7K_0402_5%~D +3V D3A 6 B 2 BAV99DW -7_SOT363 D3B PMSYNCH 4 SLP_LAN# / GPIO29 BJ10 F6 H_PM_SYNC 3 <6> BAV99DW -7_SOT363 R39 2.2K_0402_5%~D PM_SLP_LAN# 2 RI# PM_SLP_S5# <31> <5> 5 F14 4 1 SUS_PWR_DN_ACK / GPIO30 10/2 Intel suggestion change to 10K H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7 2 @ R1233 BJ14 SYS_PWROK PWROK <5> <5> <5> <5> <5> <5> <5> <5> FDI_INT DMI_IRCOMP K5 H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7 FDI_FSYNC0 M6 B17 3 H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7 1 0_0402_5%~D SYS_PW ROK_R 1 0_0402_5%~D PCH_RSMRST# <25,31,40,41> ACIN BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12 WAKE# <6> PM_DRAM_PW RGD R66 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 SYS_RESET# LAN_RST# +3V H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7 T6 SYS_PW ROK B DMI_ZCOMP BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12 XDP_DBRESET# <6> XDP_DBRESET# SYS_PW ROK VGATE BF25 FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 O 74AHC1G08GW _SOT353-5~D 1 C 1 R1088 1 @ R69 1 R1114 1 R72 1 R55 IN2 2 +3V 2 0.1U_0402_10V6K~D U62 E DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3 <5> <5> <5> <5> SLP_S5# C DMI0RXP DMI1RXP DMI2RXP DMI3RXP <5> <5> <5> <5> IN1 2 B DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3 BD24 BG22 BA20 BG20 XDP_DBRESET# 2 10K_0402_5%~D PM_CLKRUN# 2 8.2K_0402_5%~D 2 10K_0402_5%~D 1 C1125 2 1 DMI0RXN DMI1RXN DMI2RXN DMI3RXN FDI BC24 BJ22 AW20 BJ20 System Power Management 1 @ R110 1 @ R1125 1 R1211 REV1.0 DMI_HTX_PRX_N0 DMI_HTX_PRX_N1 DMI_HTX_PRX_N2 DMI_HTX_PRX_N3 <5> <5> <5> <5> +3VS DMI D PM_SLP_S4# UMA U47C 1 1 0_0402_5%~D 2 R1234 <27,31> EC_TX_P80_DATA IBEXPEAK-M_FCBGA1071~D R37 @ 2 1 0_0402_5%~D U2 P 4 B 2 ICH_PW ROK A 1 VGATE Y 3 SYS_PW ROK G 5 +3VS ICH_PW ROK VGATE <31> <13,31,46> TC7SH08FUF_SSOP5 A A SYS_PW ROK R31 ICH_PW ROK R41 LAN_RST# 1 2 10K_0402_5%~D 1 2 10K_0402_5%~D 1 R1115 2009/09/21 Issued Date Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. No used Integrated LAN, connecting LAN_RST# to GND 5 Compal Electronics, Inc. Compal Secret Data Security Classification 2 10K_0402_5%~D 4 3 2 Title PCH (3/9) DMI, FDI, PM Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 17 of 49 5 4 3 2 1 U47D 2 100K_0402_5%~D IGPU_BKLT_EN <35> VGA_PW M 1 <35> LVDS_DDC_CLK <35> LVDS_DDC_DATA RU3 +3VS RU4 1 2 2.2K_0402_5%~D LVDS_DDC_CLK RU7 1 2 2.2K_0402_5%~D LVDS_DDC_DATA RU8 1 2 10K_0402_5%~D LCTLA_CLK RU9 1 2 10K_0402_5%~D LCTLB_DATA RU10 1 2 2.2K_0402_5%~D CRT_DDC_CLK RU11 1 2 2.2K_0402_5%~D CRT_DDC_DATA RU94 1 2 2.2K_0402_5%~D SDVO_SDATA RU95 1 2 2.2K_0402_5%~D DP_DDC_DATA RU101 1 2 2.2K_0402_5%~D SDVO_SCLK RU102 1 2 2.2K_0402_5%~D DP_DDC_CLK RU12 RU13 RU14 1 L_DDC_CLK L_DDC_DATA LCTLA_CLK LCTLB_DATA AB46 V48 L_CTRL_CLK L_CTRL_DATA 2LVDS_IBG 2.37K_0402_1%~D AP39 AP41 LVD_IBG LVD_VBG 1 2LVD_VREF 0_0402_5%~D AT43 AT42 LVD_VREFH LVD_VREFL <35> LVDS_A0<35> LVDS_A1<35> LVDS_A2<35> LVDS_A0+ <35> LVDS_A1+ <35> LVDS_A2+ 1 1 <35> LVDS_BCLK<35> LVDS_BCLK+ <35> LVDS_B0<35> LVDS_B1<35> LVDS_B2<35> LVDS_B0+ <35> LVDS_B1+ <35> LVDS_B2+ VGA_CRT_B 150_0402_1%~D VGA_CRT_G 2 150_0402_1%~D VGA_CRT_R 2 150_0402_1%~D 2 L_BKLTCTL AB48 Y45 1 <35> LVDS_ACLK<35> LVDS_ACLK+ C Y48 LVDS_DDC_CLK LVDS_DDC_DATA change to 2.2k follow Intel checklist ver.1.6 RU6 L_BKLTEN L_VDD_EN <35> VGA_CRT_B <35> VGA_CRT_G <35> VGA_CRT_R <35> CRT_DDC_CLK <35> CRT_DDC_DATA LVDS_ACLKLVDS_ACLK+ AV53 AV51 LVDSA_CLK# LVDSA_CLK LVDS_A0LVDS_A1LVDS_A2- BB47 BA52 AY48 AV47 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LVDS_A0+ LVDS_A1+ LVDS_A2+ BB48 BA50 AY49 AV48 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDS_BCLKLVDS_BCLK+ AP48 AP47 LVDSB_CLK# LVDSB_CLK LVDS_B0LVDS_B1LVDS_B2- AY53 AT49 AU52 AT53 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDS_B0+ LVDS_B1+ LVDS_B2+ AY51 AT48 AU50 AT51 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 VGA_CRT_B VGA_CRT_G VGA_CRT_R AA52 AB53 AD53 CRT_BLUE CRT_GREEN CRT_RED CRT_DDC_CLK CRT_DDC_DATA <35> CRT_HSYNC <35> CRT_VSYNC CRT_DDC_CLK CRT_DDC_DATA Y53 Y51 CRT_HSYNC CRT_VSYNC DAC_IREF CRT_IRTN BJ46 BG46 SDVO_STALLN SDVO_STALLP BJ48 BG48 SDVO_INTN SDVO_INTP BF45 BH45 D T51 T53 SDVO_SCLK <36> SDVO_SDATA <36> RU5 DDPB_AUXN DDPB_AUXP DDPB_HPD BG44 BJ44 AU38 PCH_DPB_HPD DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38 PCH_DPB_N0 PCH_DPB_P0 PCH_DPB_N1 PCH_DPB_P1 PCH_DPB_N2 PCH_DPB_P2 PCH_DPB_N3 PCH_DPB_P3 DDPC_CTRLCLK DDPC_CTRLDATA Y49 AB49 DDPC_AUXN DDPC_AUXP DDPC_HPD BE44 BD44 AV40 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36 1 2 100K_0402_5%~D PCH_DPB_HPD CU7 CU8 CU9 CU10 CU11 CU12 CU13 CU14 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D <36> PCH_TMDS_D2# <36> PCH_TMDS_D2 <36> PCH_TMDS_D1# <36> PCH_TMDS_D1 <36> PCH_TMDS_D0# <36> PCH_TMDS_D0 <36> PCH_TMDS_CK# <36> PCH_TMDS_CK <36> HDMI D2 HDMI D1 HDMI D0 HDMI CLK C U50 U52 DP_DDC_CLK DP_DDC_DATA DDPD_AUXN DDPD_AUXP DDPD_HPD BC46 BD46 AT38 DP_AUX# DP_AUX DP_HPD DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36 DDPD_CTRLCLK DDPD_CTRLDATA V51 V53 CRT_IREF AD48 AB51 REV1.0 DP_DDC_CLK <37> DP_DDC_DATA <37> DP_AUX# <37> DP_AUX <37> DP_HPD <37> DISP_A0N_VGA DISP_A0P_VGA DISP_A1N_VGA DISP_A1P_VGA DISP_A2N_VGA DISP_A2P_VGA DISP_A3N_VGA DISP_A3P_VGA <37> <37> <37> <37> <37> <37> <37> <37> Display Port B IBEXPEAK-M_FCBGA1071~D1 B SDVO_TVCLKINN SDVO_TVCLKINP SDVO_CTRLCLK SDVO_CTRLDATA Digital Display Interface RU2 D T48 T47 LVDS 2 100K_0402_5%~D VGA_LVDDEN IGPU_BKLT_EN CRT RU85 1 <31> IGPU_BKLT_EN <35> VGA_LVDDEN 2 R126 1K_0402_0.5%~D A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Issued Date Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH (4/9) LVDS, CRT, DPI Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 18 of 49 5 4 3 2 1 U47E G38 H51 B37 A44 PIRQA# PIRQB# PIRQC# PIRQD# PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3# F51 A46 B45 M53 REQ0# REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 PCI_GNT0# PCI_GNT1# PCI_GNT3# F48 K45 F36 H53 GNT0# GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# B41 K53 A36 A48 8.2K_1206_8P4R_5%~D RP9 1 2 3 4 8 7 6 5 PCI_REQ0# PCI_PIRQB# PCI_PIRQF# PCI_REQ3# 8.2K_1206_8P4R_5%~D RP6 1 2 3 4 8 7 6 5 PCI_IRDY# PCI_PIRQD# PCI_REQ2# PCI_DEVSEL# 8.2K_1206_8P4R_5%~D RP8 1 2 3 4 C 8 7 6 5 PCI_FRAME# PCI_REQ1# PCI_TRDY# 8.2K_1206_8P4R_5%~D 1 R1239 ACCEL_INT# 2 8.2K_0402_5%~D <14> ACCEL_INT# Link to INT of G sensor K6 PCI_SERR# PCI_PERR# PCI_IRDY# B @ CLK_PCI_EC 1 C1111 CLK_PCI_FB 1 C1112 2 10P_0402_50V8J~D 2 10P_0402_50V8J~D R1031 R1116 R99 <27> CLK_DEBUG_PORT <31> CLK_PCI_EC <16> CLK_PCI_FB 1 1 1 PCIRST# SERR# PERR# PCI_DEVSEL# PCI_FRAME# A42 H44 F46 C46 IRDY# PAR DEVSEL# FRAME# PCI_PLOCK# D49 PLOCK# PCI_STOP# PCI_TRDY# D41 C48 STOP# TRDY# M7 PME# D5 PLTRST# @ <6> PCI_PLTRST# E44 E50 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 PCI_PLTRST# N52 P53 2 22_0402_5%~D R_CLK_DEBUG_PORTP46 R_CLK_PCI_EC 22_0402_5%~D 2 P51 R_CLK_PCI_FB 2 22_0402_5%~D P48 2008/1/6 2009MOW01 change to 22 ohm CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6 NV_ALE NV_CLE BD3 AY6 NV_ALE NV_CLE NV_RCOMP AU2 NV_RCOMP NV_RB# AV7 NV_W R#0_RE# NV_W R#1_RE# AY8 AY5 NV_W E#_CK0 NV_W E#_CK1 AV11 BF5 High = Enabled NV_ALE +3VS Low = Disabled 1 DMI Termination Voltage C976 0.1U_0402_16V4Z~D Set to Vss when LOW NV_CLE D 2 PCI_PLTRST# Set to Vcc when HIGH 2 B 1 A U44 Y PLT_RST# 4 MC74VHC1G08DFT2G SC70 5P PLT_RST# <6,24,27,28,30,31> 1 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_PLOCK# PCI_PERR# PCI_PIRQH# PCI_STOP# AV9 BG8 R1139 1U_0402_6.3V6K~D +VCCQ_NAND @ R1030 2 R167 1 R172 1 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24 USBP0USBP0+ USBP1USBP1+ USBP2USBP2+ USBP3USBP3+ USBP4USBP4+ USBP5USBP5+ USBRBIAS# B25 USB_BIAS USBRBIAS D25 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 N16 J16 F16 L16 E14 G16 F12 T15 @ @ R153 1 2 1K_0402_5%~D 2 1K_0402_5%~D 2 32.4_0402_1%~OK USBP0USBP0+ USBP1USBP1+ USBP2USBP2+ USBP3USBP3+ USBP4USBP4+ USBP5USBP5+ C <30> <30> <30> <30> <30> <30> <28> <28> <27> <27> <27> <27> USB Port EHCI 1 0 1 2 From PCH EDS 5.18, USB port6 & 7 are not available in all sku. USBP8USBP8+ USBP9USBP9+ USBP10USBP10+ USBP11USBP11+ USBP8USBP8+ USBP9USBP9+ USBP10USBP10+ USBP11USBP11+ 3 4 <28> <28> <32> <32> <30> <30> <30> <30> 5 6 7 EHCI 2 8 9 10 11 1 2 R63 22.6_0402_1%~D USB_OC0#_R USB_OC1#_R USB_OC2#_R USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7# R48 R67 R28 1 0_0402_5%~D 2 8 7 6 5 NV_DQS0 NV_DQS1 5 1 2 3 4 AY9 BD1 AP15 BD8 P C/BE0# C/BE1# C/BE2# C/BE3# RP4 D Danbury Technology Enabled NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 G J50 G42 H47 G34 8.2K_1206_8P4R_5%~D USB 8 7 6 5 NVRAM AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCI_PIRQA# PCI_PIRQG# PCI_PIRQC# PCI_SERR# PCI 1 2 3 4 REV1.0 H40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H36 RP5 3 +3VS 2 0_0402_5%~D 2 0_0402_5%~D 2 0_0402_5%~D 1 1 1 @ @ @ @ @ Device USB&ESATA Reader board USB board WPAN WLAN WWAN NC NC Express Touch screen Bluetooth Camera B ESATA_USB_OC# <30> USB_OC1# <30> USB_OC2# <30> PAD T114 PAD T115 PAD T116 PAD T117 PAD T118 RP10 USB_OC0#_R USB_OC1#_R USB_OC2#_R USB_OC3# IBEXPEAK-M_FCBGA1071~D OC[0..3] use for EHCI 1 OC[4..7] use for EHCI 2 1 2 3 4 8 7 6 5 +3V 10K_1206_8P4R_5%~D Boot BIOS Strap PCI_GNT#0 A * PCI_GNT#1 Boot BIOS Location 0 0 LPC 0 1 Reserved (NAND) 1 0 PCI 1 1 SPI PCI_GNT0# R75 1 @ 2 1K_0402_5%~D PCI_GNT1# R83 1 @ 2 1K_0402_5%~D PCI_GNT3# R1117 1 @ 2 1K_0402_5%~D RP7 8 7 6 5 +3V A Issued Date Low = A16 swap High = Default Compal Electronics, Inc. Compal Secret Data Security Classification Swap Override jumper 5 1 2 3 4 10K_1206_8P4R_5%~D A16 swap override Strap/Top-Block PCI_GNT#3 USB_OC4# USB_OC5# USB_OC6# USB_OC7# 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title PCH (5/9) PCI, USB, VRAM Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 19 of 49 5 4 3 +3VS T120PAD @ LAN_LOPW EN D37 TACH2 / GPIO6 LAN_CABDT J32 TACH3 / GPIO7 EC_SMI# F10 GPIO8 EC_SCI# K9 PCH_GPIO15 T7 GPIO15 PCH_GPIO16 AA2 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N AM3 CLK_CPU_BCLK# <6> GPIO17 F38 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_CPU_BCLK <6> +3V (Rev:1.0 GPIO24 Only) R59 R47 R86 EC_SCI# 2 10K_0402_5%~D EC_SMI# 2 10K_0402_5%~D 1 1 T121PAD @ 2 1K_0402_5%~DPCH_GPIO15 1 10/7 Not Use PCH_GPIO15 PU 1K to +3V T122PAD R117 1 PCH_GPIO28 2 10K_0402_5%~D R1118 1 R1119 1 PCH_GPIO45 2 10K_0402_5%~D PCH_GPIO46 2 10K_0402_5%~D C1559 1 2 0.047U_0402_16V4Z~D T123PAD R1.0 modify R106 1 R68 1 PCH_GPIO35 2 10K_0402_5%~D PCH_GPIO57 2 10K_0402_5%~D R134 1 @ PCH_GPIO27 2 10K_0402_5%~D <6,11,12> DDR_RST_GATE GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable Low: VCCVRM VR Disable <31> PCH_GPIO49 Y7 CLKOUT_PCIE6N CLKOUT_PCIE6P AH45 AH46 CLKOUT_PCIE7N CLKOUT_PCIE7P AF48 AF47 LAN_PHY_PWR_CTRL / GPIO12 A20GATE SCLOCK / GPIO22 H10 GPIO24 PCH_GPIO27 AB12 GPIO27 PCH_GPIO28 V13 GPIO28 PCH_GPIO34 M11 STP_PCI# / GPIO34 PCH_GPIO35 V6 PECI RCIN# GATEA20 U2 BE10 THRMTRIP# BD10 R101 1 2 10K_0402_5%~D KB_RST# R121 1 2 10K_0402_5%~D KB_RST# <31> H_CPUPW RGD THRMTRIP_PCH# 2 R175 <6> 1 56_0402_1%~D H_THERMTRIP# 2 R183 H_THERMTRIP# <6> 1 56_0402_1%~D +1.1VS_VTT SATACLKREQ# / GPIO35 PCH_GPIO36 AB7 SATA2GP / GPIO36 TP1 BA22 @ PCH_GPIO37 AB13 SATA3GP / GPIO37 TP2 AW22 VGA_PRSNT_R# V3 SLOAD / GPIO38 TP3 BB22 VGA_PRSNT_L# P3 SDATAOUT0 / GPIO39 TP4 AY45 PCH_GPIO45 H3 PCIECLKRQ6# / GPIO45 TP5 AY46 PCH_GPIO46 F1 PCIECLKRQ7# / GPIO46 TP6 AV43 PCH_GPIO48 AB6 SDATAOUT1 / GPIO48 TP7 AV45 PCH_GPIO49 AA4 SATA5GP / GPIO49 TP8 AF13 GPIO57 TP9 M18 TP10 N18 TP11 AJ24 TP12 AK41 TP13 AK42 TP14 M32 TP15 N32 TP16 M30 TP17 N30 TP18 H12 TP19 AA23 NC_1 AB45 NC_2 AB38 NC_3 AB42 NC_4 AB41 NC_5 T39 F8 A4 A49 A5 A50 A52 A53 B2 B4 B52 B53 BE1 BE53 BF1 BF53 BH1 BH2 BH52 BH53 BJ1 BJ2 BJ4 BJ49 BJ5 BJ50 BJ52 BJ53 D1 D2 D53 E1 E53 B GATEA20 H_PECI <6> KB_RST# T1 @ PCH_GPIO57 GATEA20 <31> BG10 PROCPWRGD D +3VS WW46 Platform/Design Updates 2008/11/17 54.9 1% ->56 5% C MAINPW ON <42,47> +1.1VS_VTT R184 @ 330_0402_5%~D 1 2 2 B 1 EC_SCI# TACH1 / GPIO1 BMBUSY# / GPIO0 C Q51 E 3 EC_SMI# <31> C38 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 RSVD <31> PCH_GPIO1 MISC <24> LAN_CABDT Y3 CPU <24> LAN_LOPW EN PCH_GPIO0 GPIO @ NCTF 2 2 2 2 2 2 2 2 2 2 2 2 2 2 T119PAD 10K_0402_5%~D PCH_GPIO0 10K_0402_5%~D PCH_GPIO1 10K_0402_5%~D PCH_GPIO16 10K_0402_5%~D GPIO17 10K_0402_5%~D PCH_GPIO22 10K_0402_5%~D VGA_PRSNT_R# 10K_0402_5%~D VGA_PRSNT_L# 10K_0402_5%~D PCH_GPIO36 10K_0402_5%~D PCH_GPIO37 10K_0402_5%~D PCH_GPIO48 10K_0402_5%~D PCH_GPIO49 10K_0402_5%~D LAN_LOPW EN 10K_0402_5%~D PCH_GPIO34 10K_0402_5%~D LAN_CABDT PCH_GPIO22 C 1 U47F R107 1 R62 1 R1126 1 R73 1 R87 1 R1127 1 R1128 1 R133 1 R128 1 R120 1 R1129 1 R61 1 R100 1 R1032 1 D 2 INIT3_3V# REV1.0 TP24 P6 C10 2SC2411K_SOT23 @ H_THERMTRIP# B (Do not pull high) TP24_SST @ PAD T6 IBEXPEAK-M_FCBGA1071~D A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Issued Date Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH (6/9) GPIO, CPU, MISC Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 20 of 49 5 4 3 2 1 +1.05VS +3VS C63 2 Near AB24 Top Side Near AB24 All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V rails AE50 VCCADAC[2] AE52 VSSA_DAC[1] AF53 VSSA_DAC[2] AF51 300mA LVDS BJ24 VCCIO[24] 42mA C114 Near AN20 1 C80 2 1U_0402_6.3V4Z~D 1 C85 2 Top Side 1U_0402_6.3V4Z~D 1 1 C90 C83 2 1U_0402_6.3V4Z~D 2 2 1U_0402_6.3V4Z~D Near AN35 +3VS Follow Intel suggestion 8/21 B C94 0.1U_0402_16V4Z~D 2 1 AN30 AN31 VCCIO[54] VCCIO[55] AN35 VCC3_3[1] HVCMOS VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] VCCIO[50] VCCIO[51] VCCIO[52] VCCIO[53] +VCCAPLL_FDI 1uH inductor, 405mA Change to 0 ohm for discrete C978 10U_0805_10V4Z~D 2 @ +1.05VS AT22 VCCVRM[1] BJ18 VCCFDIPLL AM23 VCCIO[1] AB34 VCC3_3[3] AB35 VCC3_3[4] AD35 +VCCA_LVDS VCCVRM[2] 3208mA 35mA 6mA 1 1 1 C64 0.1U_0402_16V4Z~D 47U_0805_4V6M~D 2 2 2 61mA AT16 VCCDMI[2] AU16 156mA VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9] D change to 2ohm change to 47U CRB 0.9 is 180 ohm @ 100MHz DG0.8 is 600 ohm FB (Page 290) UMA 2 0.022_0805_1%~OK +VCCTX_LVDS 1 CU15 1 LU1 CU16 1 2 1 0.1UH_MLF1608DR10KT_10%_1608 CU17 0.1uH inductor, 200mA 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D 22U_0805_6.3V6M~OK 2 2 2 +3VS 1 C Near AB34 R174 1 @ 2 0_0805_5%~D +1.05VS R182 1 @ 2 0_0805_5%~D +1.5VS R188 1 2 0.022_0805_1%~OK +1.8VS +1.1VS_VTT +VCC_DMI 1 R181 1 2 0.022_0805_1%~OK R189 1 @ 2 0.022_0805_1%~OK +1.05VS C95 1U_0402_6.3V4Z~D 2 AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15 2 2_0603_5%~D +1.8VS AT24 VCCDMI[1] RU15 1 Near AP43 0.1U_0402_16V4Z~D 2 35mA FDI +VCCVRM VCC3_3[2] L9 Near AE50 +VCCVRM +1.05VS L40 1 2 1UH_CBC2012T1R0M_20%~D 1 R125 0_0402_5%~D @ AP43 AP45 AT46 AT45 C58 DMI 10U_0805_10V4Z~D 1 AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27 NAND / SPI +1.05VS AH39 VCCAPLLEXP PCI E* C AH38 VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4] 1uH inductor, 405mA DG 0.8 is 1uH Have Internal VRM (DG0.8 Page 293) VCCALVDS VSSA_LVDS 59mA +1.05VS AK24 0.01U_0402_16V7K~D 1 C72 C69 +VCCADAC +3VS +1.05VS L81 1 @ +VCCAPLL_EXP 2 1UH_CBC2012T1R0M_20%~D 1 C1029 @ 10U_0805_10V4Z~D 2 Inductor (Page 291) VCCADAC[1] 69mA 1 VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4]1524mA VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] 2 C107 2 AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31 AJ30 AJ31 CRT 1U_0402_6.3V4Z~D 1 Intel suggest follow CRB 8/21 VCC CORE 10U_0805_10V4Z~D 1 D 60mA POWER U47G Near AT16 +VCCQ_NAND +1.8VS R138 1 C79 2 0.022_0805_1%~OK 1 B 0.1U_0402_16V4Z~D 2 85mA VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4] Near AK13 AM8 AM9 AP11 AP9 +3VS C97 REV1.0 IBEXPEAK-M_FCBGA1071~D 1 0.1U_0402_16V4Z~D 2 Near AM8 DG 0.8 is 1uH Inductor (Page 291) Have Internal VRM (DG0.8 Page 293) A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Issued Date Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH (7/9) PWR Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 21 of 49 4 3 AF41 VCCME[5] AF42 VCCME[6] V39 VCCME[7] All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V rails V41 VCCME[8] V42 VCCME[9] Y39 VCCME[10] Y41 VCCME[11] Y42 Near V9 C51 0.1U_0402_16V4Z~D +VCCRTCEXT 1 2 C AU24 +VCCVRM BB51 BB53 +VCCADPLLA +VCCADPLLB +1.05VS Near AH35 Near AJ35 1 C73 1U_0402_6.3V4Z~D 2 +1.05VS LU9 1 2 1 10UH_LB2012T100MR_20%~D CU64 2 1U_0402_6.3V4Z~D B Near AH23 1 C74 1 2 1U_0402_6.3V4Z~D C78 1U_0402_6.3V4Z~D 2 CU65 CU66 2 1U_0402_6.3V4Z~D 2 Follow Intel design +3V C46 0.1U_0402_16V4Z~D DCPRTC VCCVRM[3] 72mA VCCADPLLA[1] VCCADPLLA[2] 73mA BD51 BD53 VCCADPLLB[1] VCCADPLLB[2] AH23 AJ35 AH35 VCCIO[21] VCCIO[22] VCCIO[23] AF34 VCCIO[2] AH34 1 1U_0402_6.3V4Z~D 1 V9 VCCME[12] VCCIO[4] +VCCSST 1 2 V12 C50 Near V12 0.1U_0402_16V4Z~D DCPSST +VCCSUS Y22 1 2 C56 Near Y22 0.1U_0402_16V4Z~D DCPSUS 2 Near P18 VCCSUS3_3[30] U20 VCCSUS3_3[31] U22 VCCSUS3_3[32] V15 VCC3_3[5] V16 VCC3_3[6] AT18 C113 1 C89 4.7U_0805_10V4Z~D 2 1 C99 1 0.1U_0402_16V4Z~D 2 2 0.1U_0402_16V4Z~D Near AT18 A AU18 A12 Near A26 V5REF 357mA K49 VCC3_3[8] J38 VCC3_3[9] L38 + C1032 +VCC5REFSUS C28 1U_0402_6.3V6K~D 1 Near F24 +VCC5REF Change to 1U for power sequence issue on ICH9 VCC3_3[13] 0.1U_0402_16V4Z~D 2 VCC3_3[14] AD13 VCC3_3[7] > 1mA V_CPU_IO[1] V_CPU_IO[2] 2mA VCCRTC IBEXPEAK-M_FCBGA1071~D AD20 VCCIO[12] AF22 VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] AD19 AF20 AF19 AH20 VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] AB19 AB20 AB22 AD22 VCCME[13] VCCME[14] VCCME[15] VCCME[16] AA34 Y34 Y35 AA35 6mA VCCSUSHDA 2 1 Follow Intel Suggestion 8/21 C +5VS C36 1U_0402_6.3V6K~D 1 +3VS Near J38 Near AD13 +1.05VS 2 C67 0.1U_0402_16V4Z~D +VCCSATAPLL L84 1 @ 2 1 10UH_LB2012T100MR_20%~D 1 10uH inductor, 120mA C84 10U_0805_10V4Z~D 2 @ DG 0.8 is 10uH Inductor (Page 291) Have Internal VRM (DG0.8 Page 293) C75 1U_0402_6.3V4Z~D 2 @ B Near AK1 +VCCVRM +1.05VS 1 +5VALW C66 1U_0402_6.3V4Z~D 2 Near AB19 2 <33> SBPW R_EN# R1156 0_0402_5%~D 1 +1.05VS C1074 0.1U_0402_16V4Z~D PCH_VCCME13 PCH_VCCME14 PCH_VCCME15 PCH_VCCME16 R118 R92 R102 R109 1 1 1 1 2 2 2 2 L30 0_0603_5%~D 0_0603_5%~D 0_0603_5%~D 0_0603_5%~D 2 1 Q62 AO3413_SOT23-3 2 +5V +3V C37 1 A 2 1U_0402_6.3V4Z~D Near L30 +RTCVCC 1 C24 1 C25 1 2 0.1U_0402_16V4Z~D 2 0.1U_0402_16V4Z~D 4 Near A12 Compal Electronics, Inc. Compal Secret Data Security Classification C19 1U_0402_6.3V4Z~D2 5 R97 10_0402_5%~D 1 2 Near K49 C38 VCCIO[11] D49 CH751H-40PT_SOD323-2~D +3VS U35 VCCIO[10] R49 2 10_0402_5%~D 1 P36 AH19 1 +3VS N36 AT20 Near BD51 +5V VCC3_3[12] VCCVRM[4] 1 Follow Intel Suggestion 8/21 +1.05VS M36 AH22 +VCCADPLLB D48 CH751H-40PT_SOD323-2~D VCC3_3[11] VCCIO[9] 2009/09/21 Issued Date Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 D C109 1U_0402_6.3V4Z~D 2 2 220U_D2_4VM_R15~D +3V VCC3_3[10] AK3 AK1 2 220U_D2_4VM_R15~D Near U23 R569 0_0402_5%~D @ L83 1 2 10UH_LB2012T100MR_20%~D 2 >1mA 1 C104 1U_0402_6.3V4Z~D 2 10uH inductor, 120mA 1 +1.05VS VCCSUS3_3[29] Near V15 F24 VCCSATAPLL[1] VCCSATAPLL[2] P18 Y16 2 V5REF_SUS >1mA RTC 0.1U_0402_16V4Z~D +1.1VS_VTT VCCIO[56] V23 32mA U19 1 U23 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 2 2 1 +3VS C53 VCCSUS3_3[28] + C1030 VCCIO[3] AF32 1 163mA 1 C47 2 VCCME[4] 1 3 VCCME[3] AF43 USB VCCME[2] AD41 C1031 Near BB51 1 Near V39 1U_0402_6.3V4Z~D VCCME[1] AD39 +VCCADPLLA L82 1 2 10UH_LB2012T100MR_20%~D 10uH inductor, 120mA 1 2 Near AD38 1998mA AD38 1 C40 C49 22U_0805_6.3V6M~OK 2 2 1U_0402_6.3V4Z~D 2 DCPSUSBYP +3V Near V24 1 C70 2 22U_0805_6.3V6M~OK 1 V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26 +1.05VS C54 1U_0402_6.3V4Z~D 2 2 C60 2 1 VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27] +1.05VS 1 1 Follow Intel suggestion 22U_0805_6.3V6M~OK 1 Y20 HDA 2 0.1U_0402_16V4Z~D 2 Near Y20 +1.05VS C48 VCCLAN[2] 1 C57 Near AF23 1 VCCLAN[1] AF24 Clock and Miscellaneous +PCH_VCCD6W V24 V26 Y24 Y26 PCI/GPIO/LPC 1 C65 1U_0402_6.3V4Z~D 2 @ VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] 344mA AF23 1 R131 0_0402_5%~D D VCCACLK[2] SATA Near AP51 2 AP53 PCI/GPIO/LPC +1.05VS C86 1U_0402_6.3V4Z~D 2 @ VCCACLK[1] CPU C92 10U_0805_10V4Z~D 2 @ REV1.0 52mA AP51 G 10uH inductor, 120mA R124 1 @ 0_0603_5%~D POWER U47J L13 +1.1VS_VCCACLK 1 @ 2 10UH_LB2012T100MR_20%~D 1 1 1 D +1.05VS DG 0.8 is 10uH Inductor (Page 290) Have Internal VRM (DG0.8 Page 293) 2 S 5 2 Title PCH (8/9) PWR Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 22 of 49 5 4 U47I D C B A AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47 B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49 BB5 BC10 BC14 BC18 BC2 BC22 BC32 BC36 BC40 BC44 BC52 BH9 BD48 BD49 BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50 BE6 BE8 BF3 BF49 BF51 BG18 BG24 BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47 BH7 C12 C50 D51 E12 E16 E20 E24 E30 E34 E38 E42 E46 E48 E6 E8 F49 F5 G10 G14 G18 G2 G22 G32 G36 G40 G44 G52 AF39 H16 H20 H30 H34 H38 H42 3 2 1 U47H VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366] H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14 AB16 VSS[0] AA19 AA20 AA22 AM19 AA24 AA26 AA28 AA30 AA31 AA32 AB11 AB15 AB23 AB30 AB31 AB32 AB39 AB43 AB47 AB5 AB8 AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31 AD32 AD34 AU22 AD42 AD46 AD49 AD7 AE2 AE4 AF12 Y13 AH49 AU4 AF35 AP13 AN34 AF45 AF46 AF49 AF5 AF8 AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43 AH47 AH7 AJ19 AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32 AJ34 AT5 AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28 VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] REV1.0 VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47 D C B IBEXPEAK-M_FCBGA1071~D A REV1.0 Compal Electronics, Inc. Compal Secret Data Security Classification IBEXPEAK-M_FCBGA1071~D 2009/09/21 Issued Date Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH (9/9) VSS Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 23 of 49 A B D L10 FBMA-L11-322513-201LMA40T_1210 1 2 G 3 1 1 R1142 2 C958 2200P_0402_50V7K~D 2 1 2 1 2 4.7UH_1008HC-472EJFS-A_5%_1008 C304 2 <16> PCIE_IRX_GLANTX_N6 C305 2 <16> PCIE_ITX_C_GLANRX_P6 <16> PCIE_ITX_C_GLANRX_N6 2 1 20 PCIE_IRX_C_GLANTX_N6 21 PCIE_ITX_C_GLANRX_P6 15 PCIE_ITX_C_GLANRX_N6 16 <16> CLK_PCIE_GLAN <16> CLK_PCIE_GLAN# 17 18 <16> GLAN_CLKREQ# 25 <6,19,27,28,30,31> PLT_RST# 27 R239 1 2 2.49K_0402_1% HSIP LED0 HSIN R241 1 @ 2 0_0402_5%~D LAN_CKTAL1 LAN_CKTAL2 41 42 R242 1 2 15K_0402_5% RTL8111DL MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3 REFCLK_P REFCLK_N CLKREQB PERSTB RSET FB12 LANWAKEB ISOLATEB SROUT12 EVDD12 DVDD12 DVDD12 DVDD12 AVDD12 CKTAL1 CKTAL2 AVDD12 R1033 1 2 0_0402_5%~D 23 24 @ 7 14 31 47 22 LAN_CKTAL1 1 VDDSR VDDSR GND GND GND GND VDD33 VDD33 AVDD33 AVDD33 ENSR EGND LAN_CKTAL2 38 LAN_LED0 2 3 5 6 8 9 11 12 W=30mils 2 1 C310 1 C311 LAN_MDIP0 LAN_MDIN0 LAN_MDIP1 LAN_MDIN1 LAN_MDIP2 LAN_MDIN2 LAN_MDIP3 LAN_MDIN3 LAN_LED0 +LAN_DVDD12 W=60mils +LAN_DVDD12 19 30 36 13 10 39 W=40mils 1 2 1 2 29 37 2 1 2 1 2 1 1 2 C319 33P_0402_50V8J~D 2 R942 1 7 8 9 2 0.01U_0402_16V7K~D V_DAC LAN_MDIN0 LAN_MDIP0 10 11 12 MCT2 MX2+ MX2- 21 20 19 TCT3 TD3+ TD3- MCT3 MX3+ MX3- 18 17 16 TCT4 TD4+ TD4- MCT4 MX4+ MX4- 15 14 13 RJ45_TX2RJ45_TX2+ 75_1206_8P4R_5% 2 RJ45_RX1RJ45_RX1+ C323 1000P_1206_2KV7K 1 2 1 2 D4 LAN_LED2 1 RJ45_TX0RJ45_TX0+ PR4+ 6 PR2- RJ45_TX2- 5 PR3- RJ45_TX2+ 4 PR3+ RJ45_RX1+ 3 PR2+ RJ45_TX0- 2 RJ45_TX0+ 1 LINK_100_1000# 11 10 9 PR1GND PR1+ GND 14 15 Orange LEDYellow LED+ Green LED- 1 2 LAN_MDIN3 C873 1 2 6.8PF_0402_50V9~D LAN_MDIP3 C874 1 2 6.8PF_0402_50V9~D LAN_MDIN1 C875 1 2 6.8PF_0402_50V9~D LAN_MDIN2 C876 1 2 6.8PF_0402_50V9~D LAN_MDIP2 C877 1 2 6.8PF_0402_50V9~D LAN_MDIP1 C878 1 2 6.8PF_0402_50V9~D LAN_MDIN0 C879 1 2 6.8PF_0402_50V9~D LAN_MDIP0 C880 1 2 6.8PF_0402_50V9~D 3 D6 2 LED2_LED3 CH751H-40PT_SOD323-2~D LAN_LED1 1 2 LED1_LED3 CH751H-40PT_SOD323-2~D D5 LAN_LED3 1 7 RJ45_RX1- FOX_JM3611A-R4953B-7F CONN@ C291 0.1U_0402_10V6K~D 2 0.01U_0402_16V7K~D V_DAC LAN_MDIN1 LAN_MDIP1 TCT2 TD2+ TD2- 2 RJ45_TX3+ PR4- 12/11 reserve for EMI as Dell Tony request. C290 0.1U_0402_10V6K~D C324 1 4 5 6 RJ45_TX3RJ45_TX3+ 1 2 Yellow LED+ 8 2 C289 0.1U_0402_10V6K~D C322 1 2 0.01U_0402_16V7K~D V_DAC LAN_MDIN2 LAN_MDIP2 MCT1 MX1+ MX1- C288 0.1U_0402_10V6K~D C321 1 TCT1 TD1+ TD1- 1 4 3 2 1 Yellow LED- RJ45_TX3- R245 220_0402_5%~D LED2_LED3 1 LINK_10_1000# 2 +LAN_IO RP1 5 6 7 8 12 JRJ45 C309 0.1U_0402_10V6K~D TS1 24 23 22 +LAN_IO +LAN_IO These caps close to U9: Pin 1.29, 37, 40 1 2 3 13 R244 220_0402_5%~D LED1_LED3 1 2 1 +LAN_IO 0_0805_5%~D LINK OK R246 220_0402_5%~D LAN_ACTIVITY# 1 2 2 ( Should be place within 200 mils ) RTL8111DL-GR_LQFP48_7X7 2 2 0.01U_0402_16V7K~D V_DAC LAN_MDIN3 LAN_MDIP3 @ C303 0.01U_0402_16V7K~D +LAN_VDD 3 C320 1 1 R235 0_0603_5%~D These caps close to U9: Pin 44.45 +LAN_IO 1 1 2 These caps close to U9: Pin 10, 13, 30, 36, 39 2 25MHZ_20P_1BX25000CK1A C318 33P_0402_50V8J~D 2 2 1U_0603_10V6K~D 2 1U_0603_10V6K~D +LAN_DVDD12 48 1 40 43 1 +LAN_VDD 0_0603_5%~D 1 These caps close to U9: Pin 19 4 44 45 @ C302 0.1U_0402_10V6K~D W=30mils R884 C308 22U_1206_6.3V6M~D 1 2 GPO NC LAN_LED3 LAN_LED2 LAN_LED1 0.1U_0402_10V6K~D C292 26 28 +LAN_DVDD12 2 HSON 33 34 35 32 0.1U_0402_10V6K~D C293 ISOLATEB LED3/EEDO LED2/EEDI/AUX LED1/EESK EECS 0.1U_0402_10V6K~D C294 2 1K_0402_5%~D Y3 2 ( Should be place within 200 mils ) 0.1U_0402_10V6K~D C295 R240 1 <20> LAN_CABDT 2 C307 22U_1206_6.3V6M~D These components close to U9: Pin 48 0.1U_0402_10V6K~D C296 <20> LAN_LOPWEN HSOP 46 <17,27,28,31> ICH_PCIE_WAKE# +3VS 1 These caps close to U9: Pin 4 PCIE_IRX_C_GLANTX_P6 1 0.1U_0402_16V7K~D 1 +LAN_IO R947 3.6K_0402_5% 1 0.1U_0402_16V7K~D 1 C306 0.1U_0402_10V6K~D U9 <16> PCIE_IRX_GLANTX_P6 +LAN_VDD W=60mils L11 2 Q4 PMF3800SN_SC70-3 1 3 S 2 G EN_WOL# 1.5M_0402_5%~D <31> D @ C287 0.1U_0402_10V6K~D 2 EN_WOL 1 +LAN_IO 1 C285 22U_1206_6.3V6M~D 1 Q3 SI3456BDV-T1-E3_TSOP6~D R236 2 1 470K_0402_5% E W=60mils S 4 C286 22U_1206_6.3V6M~D 6 5 2 1 1 2 B+_BIAS D R0.3 Modify +3VALW W=60mils C284 1U_0603_10V6K~D C D7 LAN_LED3 1 2 BOTH_GST5009-LF 2 CH751H-40PT_SOD323-2~D CH751H-40PT_SOD323-2~D 4 LEDS1-0 00 01 10 4 11 LED0 Tx / Rx Tx / Rx Tx LINK10 / ACT LED1 LINK100 LINK10 /100 / 1000 LINK LINK100 / ACT LED2 LINK10 LINK10 / 100 Rx FULL LED3 LINK1000 LINK1000 FULL LINK1000 / ACT A B Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C D Title Gigabit LAN_RTL8111DL Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet E 24 of 49 A B C D E F G H +3VS C1086 2 2 IN1 4 O SUB_AMP_MUTE# <26> G IN2 2 @ 1 2 @ SENSE_A SENSE_B PC_BEEP EAPD# Int. 60k pull up. 5 14 15 31 MIC_CD_L MIC_CD_R PORTF_L PORTF_R 16 17 HP2_CD_L HP2_CD_R PORTG_L PORTG_R 43 44 PORTH_L PORTH_R 45 46 PCBEEP 47 EAPD/SPDIF IN/GPIO0 18 19 20 PORTI_L PORTI_C PORTI_R 48 40 1 5 1 HP_AMP_MUTE# 18 2 HP2_CD_R C354 2.2U_0805_10V7K~D HP2_CD_R1 HP2_CD_L HP2_CD_L1 C355 2.2U_0805_10V7K~D R1221 2K_0402_1%~D 1 2 1 2 R1222 2K_0402_1%~D C1120 1 HP1_AMP_L1_JK 2 HP1_AMP_R1_JK 10 19 SVDD PVDD HP2_CD_L2 13 C1121 270P_0402_50V7K~D 1 2 10 NC-4 INR NC-6 INL NC-8 NC-12 SGND PGND 17 5 2 C1N SVss C1P 3 PVss 2 1U_0603_10V4Z~D 1 7 C358 1 1 11 HP2_AMP_R 9 HP2_AMP_L BEEP# <15> PCH_SPKR 1 2 SB_SPKR_C 1 C946 0.1U_0402_16V4Z~D 2 PC_BEEP B C 21 JMIC1 1 2 6 3 1 2 MIC_CD_R1_JK L17 MIC_JD BLM18BD601SN1D_0603~D 1 3 MIC_CD_L1_JK 2 MIC_CD_R1_JK 2 1 2 7 8 9 10 SHLD1 SHLD2 NPTH1 NPTH2 4 1226 Modify D32 Center 4 6 HP2_AMP_L 1 8 HP2_AMP_R 1 NC-16 16 NC-20 20 R261 L19 68_0603_1%~D BLM18BD601SN1D_0603~D HP2_AMP_L1 1 HP2_AMP_L1_JK 2 2 2 5 3 FOX_JA6333L-B5S4-7F CONN@ HP2_AMP_R1_JK 2 L18 BLM18BD601SN1D_0603~D HP2_JD 1226 Modify 1 R0.3 Modify 2 D33 3 HP2_AMP_L1_JK 2 HP2_AMP_R1_JK SHLD1 SHLD2 NPTH1 NPTH2 4 5 Place close to Jack MAX4411ETP+T_TQFN20_4X4 JHP2 1 2 6 3 HP2_AMP_R1 1 R262 68_0603_1%~D 12 1 @ PACDN042Y3R_SOT23-3~D 1 2 7 8 9 10 FOX_JA6333L-B5S4-7F CONN@ 4 2 Issued Date Compal Electronics, Inc. Compal Secret Data 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D SGND 1 L16 BLM18BD601SN1D_0603~D 2 MIC_CD_L1_JK @ PACDN042Y3R_SOT23-3~D Security Classification R267 @ 10K_0402_5%~D R266 499K_0402_1%~D S PC_BEEP <26> 2 <31> R264 499K_0402_1%~D 1 2 2 2 FOX_JA6333L-B5S4-7F CONN@ R257 4.7K_0402_5%~D 1 MIC_CD_R1 2 1 C945 0.1U_0402_16V4Z~D 1 2 BEEP_C# PGND SVss 2 1 C357 1000P_0402_50V7K~D 1 19 PAD 15 R1.0 Modify Q43 PMF3800SN_SC70-3 2 G OUTL 270P_0402_50V7K~D 2 HP2_CD_R2 C360 1U_0603_10V4Z~D D 2 C351 1U_0603_10V4Z~D OUTR HP2_JD C865 1000P_0402_50V7K~D R544 39.2K_0402_1% R971 100K_0402_5%~D 2 1 7 8 9 10 SHLD1 SHLD2 NPTH1 NPTH2 4 5 Place close to Jack SHDNL# +AVDD_AUDIO R543 5.1K_0402_1%~D 1 2 1 C349 2.2U_0603_10V7K~D 1 2 MIC_CD_L1 1 SVDD SHDNR# PVDD 14 Q42B 2N7002DW-7-F_SOT363-6~D SENSE_A 1 HP1_JD C356 1000P_0402_50V7K~D 4 U12 AGND +3VS 1 1 2 3 1 2 6 C866 5 1 GND 2 R979 100K_0402_5%~D 2 3 3 R256 4.7K_0402_5%~D Rear or MIC MIC_CD_L JHP1 1 2 6 3 1 2 C345 1000P_0402_50V7K~D +MIC1_VREFO W=10 mil 1 C347 2 0_0805_5%~D 2 0_0805_5%~D 2 0_0805_5%~D 20 MAX4411ETP+T_TQFN20_4X4 HP1_AMP_R1_JK @ PACDN042Y3R_SOT23-3~D 2 1 3 <17,31,40,41> C350 2.2U_0603_10V7K~D 1 1000P_0402_50V7K~D R546 20K_0402_1%~D 1 P 3 +AVDD_AUDIO R545 5.1K_0402_1%~D 1 2 R547 39.2K_0402_1% R978 100K_0402_5%~D 2 R268 1 @ R269 1 @ R270 1 74AHC1G08GW_SOT353-5~D 16 1 R0.3 Modify D31 Reserved for TEST IN2 NC-20 12 1226 Modify 1 MIC_CD_R HP_AMP_MUTE# 4 S Q42A 2N7002DW-7-F_SOT363-6~D 1 O Q69 PMF3800SN_SC70-3 SENSE_B 2 2 L15 BLM18BD601SN1D_0603~D +3VS IN1 D 2 8 C353 100P_0402_50V8J~D 2 2 0.1U_0402_10V6K~D U60 G HP_JD# A HP1_AMP_R1 1 2 2 10K_0402_5%~D 1 6 NC-16 C352 100P_0402_50V8J~D 1 2 EA_EC_SPK_MUTE#1 HP1_JD 1 +MIC1_VREFO 1 2 1 +3VS HP1_AMP_R 27 33 VREFFILT CAP2 TC7SZ02FU_SSOP5 R1220 10K_0402_5%~D 4 C1N 4 NC-8 NC-12 C1P 21 R251 L14 68_0603_1%~D BLM18BD601SN1D_0603~D HP1_AMP_L1 1 HP1_AMP_L1_JK 2 2 2 G DVSS AVSS1 AVSS2 92HD73C1X5PRGXC1X8_QFP48_7X7 MIC_JD 1 2 7 26 42 HP_JD 4 Y INA +3VS HP1_AMP_L R252 68_0603_1%~D ACIN HP1_AMP_L 1U_0603_10V4Z~D Front 2 1 D53 CH751H-40PT_SOD323-2~D 1 2 R1163 0_0402_5%~D @ HP1_AMP_R 9 NC-6 INL Place close to Jack +3VS 2 G 3 NC-4 INR C339 +3VS C1119 HP_JD 2 1U_0603_10V4Z~D1 11 1 PAD 2 +MIC1_VREFO 10U_0603_6.3V6M~D P INB +3VS 3 2 R1213 2K_0402_1%~D SPK_CD_L <26> SPK_CD_R <26> R1214 1 SPDIF OUT0 SPDIF OUT1/GPIO3 OUTL 2 25 38 AVDD1 AVDD2 3 SENSE_A SENSE_B SENSE_C 12 35 36 OUTR SHDNL# U53 3 2 C1075 0.1U_0402_10V6K~D 2 13 34 32 15 HP1_CD_L2 13 C1108 270P_0402_50V7K~D 1 2 Int. Speaker and Sub woofer SPK_CD_L SPK_CD_R PORTE_L PORTE_R VREFOUT-E DMIC1/GPIO5 HP1_CD_R2 R1.0 Modify 23 24 29 SHDNR# C344 1000P_0402_50V7K~D 1 HP2_JD VOL_DN/DMIC_0/GPIO2 30 +3VS HP1_JD VOL_UP/DMIC_CLK/GPIO1 4 18 C1107 270P_0402_50V7K~D 1 2 C338 1 21 22 28 PORTD_L PORTD_R HP1_CD_L1 1 C337 2.2U_0805_10V7K~D HP1_CD_L HP1_CD_R 39 41 37 PORTC_L PORTC_R VREFOUT-C RESET# HP_AMP_MUTE# C343 1000P_0402_50V7K~D 74AHC1G08GW_SOT353-5~D 1 SYNC U10 14 HP1_CD_L 1U_0402_6.3V6K~D C348 3 P 5 0.1U_0402_10V6K~D U59 3 2 2 0_0402_5%~D 2 0_0402_5%~D 1 C342 100P_0402_50V8J~D 1 R1240 1 R1241 DMIC0 C341 100P_0402_50V8J~D EA_EC_SUB_MUTE# 1 HP_JD DVDD_IO G G <30> 2 132mA PORTB_L PORTB_R VREFOUT-B SDO 11 <15> HDA_RST_AUDIO# <30> DMIC_CLK C1118 1 2 SDI_CODEC 10 SPK_AMP_MUTE# <26> <15> HDA_SYNC_AUDIO 74AHC1G08GW_SOT353-5~D 8 2 1 C336 R1212 2.2U_0805_10V7K~D 2K_0402_1%~D HP1_CD_R HP1_CD_R1 1 2 PORTA_L PORTA_R VREFOUT-A BITCLK 5 <15> HDA_SDOUT_AUDIO IN2 +3VS 2 HDA_SDIN0_R 33_0402_5%~D 2 2 1 C325 1U_0603_10V4Z~D 1 17 4 O 1 R249 <15> HDA_SDIN0 P IN1 2 6 <15> HDA_BITCLK_AUDIO C1117 1 2 0.1U_0402_10V6K~D U58 5 HP_JD U11 74AHC1G08GW_SOT353-5~D +3VS EA_EC_SPK_MUTE# 1 4 EA_EC_SUB_MUTE# O IN2 2 10K_0402_5%~D R1219 75mA 2 1 2 PVss G 3 5 1 IN1 2 3 +3VS 0.1U_0402_16V4Z~D P 1 U57 2 2 1 +5VS R248 2 1 0_0603_5%~D C328 0.1U_0402_10V6K~D EAPD# EC_SUB_MUTE# <31> EC_SUB_MUTE# C1087 2 2 1 C335 1U_0402_6.3V6K~D 1 1 C334 10U_0603_6.3V6M~D 1 2 1 C327 0.1U_0402_10V6K~D 2 +3VS 1 C333 1U_0402_6.3V6K~D 1 74AHC1G08GW_SOT353-5~D C332 10U_0603_6.3V6M~D 2 10K_0402_5%~D +AVDD_AUDIO C331 1 R1218 0.1U_0402_10V6K~D C330 1U_0402_6.3V6K~D +3VS C326 0.1U_0402_10V6K~D <31> EC_SPK_HP_MUTE# +3VS +AVDD_AUDIO P 5 +DVDD_AUDIO 7 R247 0_0603_5%~D 2 1 5 +3VS +3VS 2 20K_0402_1%~D 0.1U_0402_16V4Z~D U56 EAPD# 1 IN1 EA_EC_SPK_MUTE# O 4 EC_SPK_HP_MUTE# 2 IN2 9 1 1 R1217 1 DVDD_CORE DVDD_CORE R0.3 Modify +3VS E F Title HD Audio_IDT92HD73C Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 G Sheet 25 H of 49 4 3 C902 22U_1210_25V6K~D 1 C903 22U_1210_25V6K~D R0.3 Modify <25> <25> SPK_CD_L 1 C911 SPK_CD_L PC_BEEP 1 C908 PC_BEEP SPK_CD_R 1 C915 <25> SPK_CD_R <25> PC_BEEP 1 C912 PC_BEEP C909 2200P_0402_25V7K~D 1 2SPK_CD_L3 R903 SPK_CD_L1 2 1U_0603_10V6K~D 1 2 16.5K_0402_1% PC_BEEP_1 2 0.1U_0402_10V6K~D 1 2 182K_0402_1% SPK_CD_R2 1 2 16.5K_0402_1% PC_BEEP_2 2 0.1U_0402_10V6K~D C914 1 2 OUTL+1 OUTL+2 R902 1 2 182K_0402_1% 5 FB_L SPK_CD_L4 6 IN_L R907 1 2 182K_0402_1% 19 SPK_CD_R4 18 1 2 182K_0402_1% 10 11 9 SPK_AMP_MUTE# SPK_AMP_MUTE_R# High-Pass Filiter,fc=500Hz, Av=1.45V/V +3VS For filterless modualation/spread-spectrum mode R910 1 2 0_0402_5%~D 20 Mono Select. Set MONO high for mono mode. 4 16 2 SDMK0340L-7-F_SOD323-2~D 21 1 C1553 2.2U_0603_10V6K~D 1 15 12 SPK_AMP_MUTE_R# 2 2 1 2 1 2 1 1U_0603_25V6-K~D R1567 1 2 330K_0402_5% C923 <25> SPK_AMP_MUTE# 1U_0603_25V6-K~D C926 1 1U_0603_25V6-K~D C925 R0.3 add C Internal Regulator Output. Internal 2V Bias. D59 C906 330P_0402_50V7K~D PGND2 PGND1 31 32 L68 BLM18PG181SN1_0603~D AMP_SPKL+ 1 2 1 2 NC1 NC2 NC3 R905 1 2SPK_CD_R2_FBL 11K_0402_1% 1 2 2 IN_R OUTR+1 OUTR+2 25 26 L69 BLM18PG181SN1_0603~D AMP_SPKR+ 1 2 1 SHDN# REGEN MUTE# 2 MODE OUTR-1 OUTR-2 MONO 23 24 VS REG COM BOOT L85 AMP_SPKL+_L AMP_SPK_JK_L+ 1 2 22UH_LQH55PN220MR0L_0.85A_20%~D C907 330P_0402_50V7K~D D 7 8 17 FB_R 0.022U_0402_25V7K~D 2 17.8K_0402_1% 1 R909 R906 C905 0.1U_0603_50V4Z~D 28 29 OUTL-1 OUTL-2 SPKER_CD_L2_FBL C910 1 2 C913 2200P_0402_25V7K~D 1 2 SPK_CD_R3 R908 SPK_CD_R1 2 1U_0603_10V6K~D 2 PVDD1 PVDD2 0.022U_0402_25V7K~D 2 17.8K_0402_1% 1 R904 R901 C904 0.1U_0603_50V4Z~D R900 1 2 11K_0402_1% SPK_CD_L2 D 2 1 3 AMP_SPKR- 1 Speaker amp impedance of JBL is 4 ohm. L86 AMP_SPKR+_R AMP_SPK_JK_R+ 1 2 22UH_LQH55PN220MR0L_0.85A_20%~D C917 330P_0402_50V7K~D AMP_SPK_JK_LAMP_SPK_JK_L+ AMP_SPK_JK_RAMP_SPK_JK_R+ L70 BLM18PG181SN1_0603~D AMP_SPK_JK_R2 1 C922 2 1 2 EP JSPK1 1 2 3 4 1 2 3 G5 5 4 G6 6 MOLEX_53261-0471 CONN@ @D21 @ D21 C921 330P_0402_50V7K~D @D20 @ D20 PESD24VS2UT_SOT23-3~D PESD24VS2UT_SOT23-3~D 0.1U_0805_50V7M~D C1N Speaker Connector 15 mils trace 2 1 1 3 C901 22U_1210_25V6K~D 2 1 1 2 1 L67 BLM18PG181SN1_0603~D AMP_SPKL- 1 AMP_SPK_JK_L2 1 2 27 30 1A/40mil 2 R0.3 Modify 2 U13 3 19V B+ 1 5 33 C C924 0.1U_0603_50V4Z~D 2 22 13 14 C1P AGND AGND MAX9736AETJ+T_TQFN32_7X7 U14 B+ 1A/40mil 27 30 2 R0.3 Modify 1 2 C1089 22U_1210_25V6K~D 1 2 C1090 22U_1210_25V6K~D 1 1 C1091 22U_1210_25V6K~D SUB_FB_L1 R1195 1 C1096 1 2 2 10K_0402_1%~D 1U_0603_10V6K~D SUB_FB_L3 0.047U_0402_16V7K~D 2 C1095 1 2 2 C1097 1 2 OUTL+1 OUTL+2 SUB_IN_L 5 FB_L 6 IN_L 1 SPK_CD_R <25> SPK_CD_R SPK_CD_L <25> SPK_CD_L 1 C1098 SUB_CD_R 2 0.47U_0603_10V7K~D 1 C1100 SUB_CD_L 2 0.47U_0603_10V7K~D R1199 9.09K_0402_1%~D 1 2 1 1 2 6.49K_0402_1%~D R1200 SUB_CD_R2 1 2 1 C1099 15.8K_0402_1% SUB_CD_R1 2 C1101 0.1U_0402_16V7K~D 2 R1201 9.09K_0402_1%~D 1 For filterless modualation/spread-spectrum mode 19 18 IN_R SUB_AMP_MUTE# SUB_AMP_MUTE_R# 10 11 9 SHDN# REGEN MUTE# 20 MODE 4 MONO 2 0_0402_5%~D Internal Regulator Output. Internal 2V Bias. SUB_AMP_MUTE_R# 2 2 1 C1558 2.2U_0603_10V6K~D 2 1 2 C1106 1U_0603_25V6-K~D SDMK0340L-7-F_SOD323-2~D R1568 1 2 330K_0402_5% 1 C1105 1U_0603_25V6-K~D <25> SUB_AMP_MUTE# 1 2 C1104 1U_0603_25V6-K~D A C1088 330P_0402_50V7K~D 31 32 L88 AMP_SW+ 1 2 BLM18PG181SN1_0603~D 7 8 17 1 15 12 MOLEX_53398-0271~D AMP_SW_JK+ 1 C1094 330P_0402_50V7K~D B 25 26 AMP_SW+ OUTR-1 OUTR-2 23 24 AMP_SW- VS REG COM 21 C1N 22 C1P BOOT 3 C1102 2 1 0.1U_0805_50V7M~D EP 33 C1103 0.1U_0603_50V4Z~D 2 13 14 A AGND AGND MAX9736AETJ+T_TQFN32_7X7 Issued Date Compal Electronics, Inc. Compal Secret Data 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 1 2 G1 G2 SUB WOOFER amp impedance of JBL is 4 ohm. OUTR+1 OUTR+2 Security Classification 5 JWFER1 1 2 3 4 FB_R SUB_IN_R 16 D60 AMP_SW_JK- 1 +3VS R12021 1 L87 1 2 BLM18PG181SN1_0603~D SUB_FB_L 2 0.01U_0402_16V7K~D High-Pass Filiter,fc=100 Hz, 500Hz, Av=1.45V/V R1.0 add AMP_SW- 2 NC1 NC2 NC3 R1198 1 2 PGND2 PGND1 SUB_FB_L4 R1196 1 2 100K_0402_1%~D 0.047U_0402_16V7K~D OUTL-1 OUTL-2 2 28 29 R1197 20K_0402_1%~D B PVDD1 PVDD2 C1093 0.1U_0603_50V4Z~D 2 R1194 1 2 11.5K_0402_1% SUB_FB_L2 SUB_FB_L C1092 0.1U_0603_50V4Z~D 1 3 2 Title Sub woofer / Speaker AMP Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 26 of 49 A B C +3VS D41 R02 Modify 2 1 2 C409 4.7U_0805_10V4Z~D 2 1 C408 .1U_0402_16V7K~D 2 1 C407 0.01U_0402_16V7K~D 2 1 @ C1114 47P_0402_50V8J~D 2 + C956 330U_D2E_6.3VM_R25~D 2 1 1 C405 4.7U_0805_10V4Z~D 2 1 C404 .1U_0402_16V7K~D 1 1 C403 0.01U_0402_16V7K~D 2 C1113 47P_0402_50V8J~D 1 @ +1.5VS W W AN_CLKREQ# <16> W W AN_CLKREQ# CLK_PCIE_W AN# CLK_PCIE_W AN <16> CLK_PCIE_W AN# <16> CLK_PCIE_W AN PCIE_IRX_W ANTX_N1 PCIE_IRX_W ANTX_P1 <16> PCIE_IRX_W ANTX_N1 <16> PCIE_IRX_W ANTX_P1 PCIE_ITX_C_W ANRX_N1 PCIE_ITX_C_W ANRX_P1 <16> PCIE_ITX_C_W ANRX_N1 <16> PCIE_ITX_C_W ANRX_P1 For EC debug pin R323 R287 R286 100K_0402_5%~D 1 2 1 1 2 0_0402_5%~D 2 0_0402_5%~D 6 2 5 3 4 1 +UIM_PW R 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 GND1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND2 54 JSIM1 Don't forget to remove R287 or disble debug port when doing SIM Pre-test and before RTS. +3VS JW W AN1 ICH_PCIE_W AKE# <17,24,28,31> ICH_PCIE_W AKE# 1 SRV05-4.TCT_SOT23-6~D +3VS <17,31> EC_TX_P80_DATA <31> EC_RX_P80_DATA E +1.5VS WWAN 2 D 5 6 7 8 9 10 UIM_VPP UIM_DATA C410 33P_0402_50V8J~D +UIM_PW R UIM_DATA UIM_CLK UIM_RST R285 1 2 3 4 UIM_RST UIM_CLK C411 33P_0402_50V8J~D Link ok C412 4.7U_0805_10V4Z~D 1 1 2 2 C413 .1U_0402_16V7K~D 2 0_0402_5%~D UIM_VPP 1 W W AN_RADIO_OFF# PLT_RST# R911 R912 GND VCC VPP RST I/O CLK NC NC GND GND MOLEX_475531001 CONN@ 2 0_0402_5%~D 2 0_0402_5%~D 1 1 Place as close as JSIM1 W W AN_RADIO_OFF# <31> PLT_RST# <6,19,24,28,30,31> EC_SMB_CK2 <16,28,31> EC_SMB_DA2 <16,28,31> USBP5_DUSBP5_D+ 2 USBP5_D+ L71 @ DLW 21SN121SQ2L_4P~D 2 2 1 1 USBP5_D- 3 3 TYCO_1775838-1~D CONN@ 4 4 1 R913 1 R914 USBP5+ <19> USBP5- <19> 2 0_0402_5%~D 2 0_0402_5%~D WLAN +3V_W LAN +1.5VS +3V_W LAN +3V_W LAN JW LAN1 <17,24,28,31> ICH_PCIE_W AKE# <28,30> COEX2_W LAN_ACTIVE 2 0_0402_5%~D 2 0_0402_5%~D 1 1 PCIE_IRX_W LANTX_N2 PCIE_IRX_W LANTX_P2 <16> PCIE_IRX_W LANTX_N2 <16> PCIE_IRX_W LANTX_P2 PCIE_ITX_C_W LANRX_N2 PCIE_ITX_C_W LANRX_P2 <16> PCIE_ITX_C_W LANRX_N2 <16> PCIE_ITX_C_W LANRX_P2 2 2 2 2 2 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D W LAN_RADIO_OFF# R922 R923 2 2 3 EC_SMB_CK2 <16,28,31> EC_SMB_DA2 <16,28,31> +1.5VS USBP4_D+ L72 @ DLW 21SN121SQ2L_4P~D 2 2 1 1 USBP4+ 1 <19> @ USBP4_D- 3 3 1 R924 1 R925 4 4 USBP4- <19> 2 2 0_0402_5%~D 2 0_0402_5%~D 1 2 1 2 4 COEX1_W LAN_ACTIVE 3 R997 10K_0402_5%~D BAT54C-7-F_SOT23~D Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Deciphered Date 2010/09/21 Title Mini Card_WLAN/WWAN 2 Issued Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A 2 1 1 BT_ACTIVE 2 <15,31> 1 2 1 <30> BT_ACTIVE LPC_AD[0..3] W LAN_RADIO_OFF# <31> PLT_RST# <6,19,24,28,30,31> 1 +3VS USBP4_DUSBP4_D+ D40 W PAN_ACTIVE <28> W PAN_ACTIVE 1 @ 2 0_0402_5%~D 2 0_0402_5%~D 1 1 TYCO_1775838-1~D CONN@ 4 LPC_FRAME# <15,31> LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 2 JP10 C418 0.01U_0402_16V7K~D GND2 1 1 1 1 1 C417 0.01U_0402_16V7K~D GND1 54 R919 R920 R915 R916 R917 C1116 47P_0402_50V8J~D 53 1 @ C416 4.7U_0805_10V4Z~D R918 R921 <6,19,24,28,30,31> PLT_RST# <19> CLK_DEBUG_PORT 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 C415 .1U_0402_16V7K~D CLK_PCIE_W LAN# CLK_PCIE_W LAN <16> CLK_PCIE_W LAN# <16> CLK_PCIE_W LAN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 C414 0.01U_0402_16V7K~D <16> W LAN_CLKREQ# 3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 C1115 47P_0402_50V8J~D ICH_PCIE_W AKE# R291 1 2 0_0402_5%~D COEX1_W LAN_ACTIVE W LAN_CLKREQ# B C D Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet E 27 of 49 5 4 3 2 +1.5VS PCIE_ITX_C_WPANRX_N3 PCIE_ITX_C_WPANRX_P3 <16> PCIE_ITX_C_WPANRX_N3 <16> PCIE_ITX_C_WPANRX_P3 53 C GND1 GND2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 2 2 2 2 1 2 C425 4.7U_0603_6.3V6M~D PCIE_IRX_WPANTX_N3 PCIE_IRX_WPANTX_P3 <16> PCIE_IRX_WPANTX_N3 <16> PCIE_IRX_WPANTX_P3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 1 C424 0.1U_0402_16V4Z~D CLK_PCIE_WPAN# CLK_PCIE_WPAN <16> CLK_PCIE_WPAN# <16> CLK_PCIE_WPAN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 1 C423 0.1U_0402_16V4Z~D 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 WPAN_ACTIVE_R 1 C422 0.047U_0402_16V4Z~D ICH_PCIE_WAKE# 1 2 0_0402_5%~D 1 2 0_0402_5%~D WPAN_CLKREQ# R292 R293 1 C421 0.047U_0402_16V4Z~D 2 JWPAN1 <17,24,27,31> ICH_PCIE_WAKE# <27,30> COEX2_WLAN_ACTIVE <27> WPAN_ACTIVE <16> WPAN_CLKREQ# 1 C420 0.047U_0402_16V4Z~D 1 +3VS +1.5VS +3VS +3VS C419 0.047U_0402_16V4Z~D WPAN Card D 1 D WPAN_RADIO_OFF# WPAN_RADIO_OFF# <31> 1 2 PLT_RST# <6,19,24,27,30,31> R1162 0_0402_5%~D R294 R298 2 0_0402_5%~D 2 0_0402_5%~D 1 1 EC_SMB_CK2 <16,27,31> EC_SMB_DA2 <16,27,31> USBP3_DUSBP3_D+ USBP3_DUSBP3_D+ L26 @ DLW21SN121SQ2L_4P~D 2 2 1 1 3 3 4 2 0_0402_5%~D 2 0_0402_5%~D 54 4 USBP3- <19> USBP3+ <19> 1 R295 1 R296 C TYCO_1775838-1~D Express Card Power Switch (1A) 1 +1.5VS B 2 2 12 AUX_IN 6 <31,33,43,44,45> SUSP# 1 10 9 18 SYSRST# 3.3Vout 3.3Vout 3 15 AUX_OUT 11 OCZ 19 SHDNZ PERSTZ STBYZ CPUSB# NC NC NC NC NC RCLKEN GND CPPE# 8 <17,24,27,31> ICH_PCIE_WAKE# +3VS_CARD_AUX PERST# +3VS_CARD 1 PERST# 2 4 5 13 14 16 <16> EXP_CLKREQ# 1 2 <16> CLK_PCIE_EXPR# <16> CLK_PCIE_EXPR <16> PCIE_IRX_EXPTX_N5 <16> PCIE_IRX_EXPTX_P5 <16> PCIE_ITX_C_EXPRX_N5 <16> PCIE_ITX_C_EXPRX_P5 EXP_CLKREQ# CPPE# CLK_PCIE_EXPR# CLK_PCIE_EXPR PCIE_IRX_EXPTX_N5 PCIE_IRX_EXPTX_P5 PCIE_ITX_C_EXPRX_N5 PCIE_ITX_C_EXPRX_P5 +1.5VS_CARD 7 (0.5A) 1 2 1 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 GND USBUSB+ CPUSB# REV REV SMBCLK SMBDATE +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PERn0 PERp0 GND PETn0 PETp0 GND 27 28 29 30 G1 G2 G3 G4 C428 4.7U_0805_10V4Z~D +1.5V_CARD Max. 650mA , Average 500mA +3V_CARD Max. 1300mA, Average 1000mA C427 0.1U_0402_16V4Z~D P2231NL E2_QFN20_4X4 A JEXP1 USBP8USBP8+ EXPR_CPUSB# USBP8USBP8+ EC_SMB_CK2 <16,27,31> EC_SMB_CK2 EC_SMB_DA2 <16,27,31> EC_SMB_DA2 +1.5VS_CARD +3VS_CARD_AUX 3.3Vin 3.3Vin 20 EXPR_CPUSB# <19> <19> U16 2 17 <31,33,44> SYSON CPPE# 2 Express Card C435 4.7U_0805_10V4Z~D PLT_RST# 2 C434 0.1U_0402_16V4Z~D <6,19,24,27,30,31> PLT_RST# 1 C431 0.1U_0402_16V4Z~D 2 C433 0.1U_0402_16V4Z~D 1 C432 0.1U_0402_16V4Z~D 1 1 C430 4.7U_0805_10V4Z~D +3VALW C429 0.1U_0402_16V4Z~D +3VS +3VS_CARD TAITW_PXPXAE-000LBS2ZZ4N0_NR CONN@ A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 B 3 2 Title Mini Card_WPAN / Express Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 28 of 49 A B C D E MOLEX_47662-2000_22P-T SATA HDD Place close U67 pin 2 & pin3 SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0 @ RU57 1 @ RU59 1 2 0_0402_5%~D SATA_ITX_R_DRX_P0 2 0_0402_5%~D SATA_ITX_R_DRX_N0 @ RU58 1 @ RU60 1 2 0_0402_5%~D ESATA_ITX_C_DRX_P0 2 0_0402_5%~D ESATA_ITX_C_DRX_N0 SATA_IRX_DTX_P0 SATA_IRX_DTX_N0 @ RU63 1 @ RU62 1 2 0_0402_5%~D SATA_IRX_R_DTX_P0 2 0_0402_5%~D SATA_IRX_R_DTX_N0 @ RU61 1 @ RU64 1 2 0_0402_5%~D ESATA_IRX_DTX_P0 2 0_0402_5%~D ESATA_IRX_DTX_N0 JSATA1 SP010812230 1 2 3 4 5 6 7 ESATA_ITX_C_DRX_P1 ESATA_ITX_C_DRX_N1 ESATA_IRX_DTX_N1C437 ESATA_IRX_DTX_P1C436 1 1 2 0.01U_0402_16V7K~DESATA_IRX_C_DTX_N1 2 0.01U_0402_16V7K~DESATA_IRX_C_DTX_P1 Place close U67 pin 21 & pin22 * 0 0dB 1 -3.5dB 1 2 1 2 1 2 U67 <15> SATA_IRX_DTX_N0 34 13 AI+ AI- 7 8 BO+ BOSEL0_A SEL0_B SEL1_A SEL1_B 32 15 SEL2_A SEL2_B RU73 RU75 1 1 2 0_0402_5%~D 2 0_0402_5%~D 31 16 SEL3_A SEL3_B RU77 RU79 1 1 2 5.1K_0402_1%~D 2 5.1K_0402_1%~D 30 29 @ RU80 1 2 470_0402_5%~D 19 2 0_0402_5%~D 2 0_0402_5%~D 11 12 +SATA_PWR 2 +SATA_PWR @ RU81 @ RU82 1 1 BIBI+ OUT+ OUTSD_A SD_B EN_A EN_B IREF ESATA_IRX_DTX_N0 ESATA_IRX_DTX_P0 ESATA_IRX_DTX_N0 CU48 ESATA_IRX_DTX_P0 CU49 17 18 @ RU72 1 @ RU74 1 2 0_0402_5%~D 2 0_0402_5%~D 36 35 @ RU76 1 @ RU78 1 2 0_0402_5%~D 2 0_0402_5%~D 2 2 1 0.01U_0402_25V7K~D ESATA_IRX_C_DTX_N0 1 0.01U_0402_25V7K~D ESATA_IRX_C_DTX_P0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 +5VS 37 PAD PI2EQX3201BZFEX_TQFN36_6X5 R0.3 change to SA00002YQ0L (S IC PI2EQX3201BLZFEX TQFN 36P) Place close U55 pin 2 & pin3 SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1 @ R1168 1 @R1168 @R1170 @ R1170 1 2 0_0402_5%~D SATA_ITX_R_DRX_P1 2 0_0402_5%~D SATA_ITX_R_DRX_N1 @ R1169 1 @ R1171 1 2 0_0402_5%~D ESATA_ITX_C_DRX_P1 2 0_0402_5%~D ESATA_ITX_C_DRX_N1 SATA_IRX_DTX_P1 SATA_IRX_DTX_N1 @ R1172 1 @R1172 @R1174 @ R1174 1 2 0_0402_5%~D SATA_IRX_R_DTX_P1 2 0_0402_5%~D SATA_IRX_R_DTX_N1 @ R1173 1 @ R1175 1 2 0_0402_5%~D ESATA_IRX_DTX_P1 2 0_0402_5%~D ESATA_IRX_DTX_N1 23 24 25 GND GND GND JSATA2 1 2 3 4 5 6 7 ESATA_ITX_C_DRX_P0 ESATA_ITX_C_DRX_N0 25 20 9 4 24 GND GND GND GND AGND CLKIN+ CLKIN- 21 22 2 1 GND RX+ RXGND TXTX+ GND +5VS 1 3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND Reserved GND 12V 12V GND1 12V GND2 2 Close to JSATA2. 1 2 1 2 1 2 C455 1000P_0402_50V7K~D 33 14 2 0_0402_5%~D 2 0_0402_5%~D ESATA_ITX_DRX_P0 ESATA_ITX_DRX_N0 2 C454 0.1U_0402_16V7K~D 2 0_0402_5%~D 2 0_0402_5%~D 1 1 27 26 2 1 MOLEX_47662-2000_NR CONN@ SATA HDD (On board) RU66 470_0402_5%~D CU47 4700P_0402_25V7K~D 2 1 ESATA_ITX_C_DRX_N0 2 1 C453 0.1U_0402_16V7K~D 1 1 RU69 RU71 2 +5VS 1 C452 10U_0805_10V4Z~D @ RU70 @ RU68 AO+ AO- 2 1 CU44 4700P_0402_25V7K~D 2 1 ESATA_ITX_C_DRX_P0 1 6 10 23 28 5 VDD VDD VDD VDD VDD AVDD 2 1 1 1 CU46 1 CU45 RU65 RU67 2 3 2 <15> SATA_ITX_C_DRX_P0 <15> SATA_ITX_C_DRX_N0 <15> SATA_IRX_DTX_P0 SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0 2 SATA_IRX_C_DTX_P0 0.01U_0402_16V7K~D 2 SATA_IRX_C_DTX_N0 0.01U_0402_16V7K~D 1 2 0_0402_5%~D 1 2 0_0402_5%~D 1 CU43 0.1U_0402_16V4Z~D 1.2x De-emphasis CU42 0.1U_0402_16V4Z~D 1x 1 SEL3_ [A:B] CU41 0.1U_0402_16V4Z~D 0 * Output De-emphasis Adjustment CU40 0.1U_0402_16V4Z~D Swing CU39 0.1U_0402_16V4Z~D SEL2_ [A:B] CU38 10U_1206_16V4Z~D Output Swing Control 1 C448 1000P_0402_50V7K~D @ V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12 C447 0.1U_0402_16V7K~D 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 +SATA_PWR 2 Close to JSATA1. C446 0.1U_0402_16V7K~D JP12 1 1 +5VS +SATA_PWR C445 10U_0805_10V4Z~D +1.8VS GND A+ AGND BB+ GND 2 23 24 TYCO_1770615-3~D 由由Kink pin尺尺尺由kink hole，將將將將將將將，也也也也也pin腳腳腳。 因因將 原HDD Conn.(REV.) –FOXCONN–SP01000LC0L layout 改改Tyco–SP01000E70L layout 即即即即即改pin腳腳腳腳腳腳 Place close U55 pin 21 & pin22 +SATA_PWR1 +1.8VS +SATA_PWR1 U55 <15> SATA_IRX_DTX_N1 7 8 34 13 AI+ AIBO+ BOSEL0_A SEL0_B 33 14 R1180 R1181 1 1 2 0_0402_5%~D 2 0_0402_5%~D 32 15 R1183 R1185 1 1 2 0_0402_5%~D 2 0_0402_5%~D 31 16 SEL3_A SEL3_B R1187 R1189 1 1 2 5.1K_0402_1%~D 2 5.1K_0402_1%~D 30 29 EN_A EN_B @ R1190 1 2 470_0402_5%~D 19 IREF SEL1_A SEL1_B R0.3 depop +SATA_PWR1 @ R1191 @ R1192 4 1 1 2 0_0402_5%~D 2 0_0402_5%~D 11 12 BIBI+ SEL2_A SEL2_B CLKIN+ CLKIN- OUT+ OUTSD_A SD_B GND GND GND GND AGND PAD SATA ODD CONN C1082 4700P_0402_25V7K~D 2 1 ESATA_ITX_C_DRX_P1 1 6 10 23 28 5 27 26 ESATA_ITX_DRX_P1 ESATA_ITX_DRX_N1 21 22 ESATA_IRX_DTX_N1 ESATA_IRX_DTX_P1 JODD1 R1193 470_0402_5%~D C1085 4700P_0402_25V7K~D 2 1 ESATA_ITX_C_DRX_N1 <15> SATA_ITX_C_DRX_P4 <15> SATA_ITX_C_DRX_N4 <15> SATA_IRX_DTX_N4 <15> SATA_IRX_DTX_P4 17 18 @ R1182 1 @ R1184 1 2 0_0402_5%~D 2 0_0402_5%~D 36 35 @ R1186 1 @ R1188 1 2 0_0402_5%~D 2 0_0402_5%~D C449 C450 2 2 1 2 3 4 5 6 7 SATA_ITX_C_DRX_P4 SATA_ITX_C_DRX_N4 1 0.01U_0402_25V7K~D SATA_IRX_C_DTX_N4 1 0.01U_0402_25V7K~D SATA_IRX_C_DTX_P4 +5VS 8 9 10 11 12 13 25 20 9 4 24 GND A+ AGND BB+ GND +5VS 1 DP V5 V5 MD GND GND G1 G2 G3 14 15 16 2 1 2 1 2 1 2 C441 1000P_0402_50V7K~D 2 0_0402_5%~D 2 0_0402_5%~D 3 C440 0.1U_0402_16V4Z~D 1 1 AO+ AO- 2 C439 1U_0603_10V4Z~D @ R1178 @ R1179 VDD VDD VDD VDD VDD AVDD 2 1 1 2 3 2 1 C438 10U_0805_10V4Z~D +SATA_PWR1 SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1 1 2 SATA_IRX_C_DTX_P1 C1083 0.01U_0402_16V7K~D 1 2 SATA_IRX_C_DTX_N1 C1084 0.01U_0402_16V7K~D R1176 1 2 0_0402_5%~D R1177 1 2 0_0402_5%~D 2 <15> SATA_ITX_C_DRX_P1 <15> SATA_ITX_C_DRX_N1 <15> SATA_IRX_DTX_P1 2 1 C1081 0.1U_0402_16V4Z~D 2 1 C1080 0.1U_0402_16V4Z~D 2 1 C1079 0.1U_0402_16V4Z~D 1 3 C1078 0.1U_0402_16V4Z~D 2 @ C1077 0.1U_0402_16V4Z~D 1 C1076 10U_1206_16V4Z~D JP11 MOLEX_47639-3000_13P CONN@ Close to ODD Conn 4 37 PI2EQX3201BZFEX_TQFN36_6X5 Equalizer Selection SEL0_ [A:B] SEL1_ [A:B] * Compliance Channel 0 0 no equalization 0 1 [0:2.5dB] @ 1.6 GHz 1 1 0 [2.5:4.5dB] @ 1.6 GHz 1 [4.5:6.5dB] @ 1.6 GHz A R0.3 change to SA00002YQ0L (S IC PI2EQX3201BLZFEX TQFN 36P) Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B C D Title ODD/SATA HDD Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet E 29 of 49 @ R1164 1 @R1164 @R1165 @ R1165 1 2 0_0402_5%~D SATA_ITX_R_DRX_P5 2 0_0402_5%~D SATA_ITX_R_DRX_N5 @ R949 1 @ R950 1 2 0_0402_5%~D ESATA_ITX_C_DRX_P 2 0_0402_5%~D ESATA_ITX_C_DRX_N SATA_IRX_DTX_P5 SATA_IRX_DTX_N5 @ R951 1 @R951 @R952 @ R952 1 2 0_0402_5%~D SATA_IRX_R_DTX_P5 2 0_0402_5%~D SATA_IRX_R_DTX_N5 @ R1166 1 @ R1167 1 2 0_0402_5%~D ESATA_IRX_DTX_P 2 0_0402_5%~D ESATA_IRX_DTX_N +ESATA_PWR +5V_CHGUSB +5VALW Place close U40 pin 21 & pin22 U17 JP13 1 1 2 3 4 2 +ESATA_PWR @ 2 2 2 2 0_0402_5%~D 2 0_0402_5%~D 33 14 @ R958 @ R959 1 1 2 0_0402_5%~D 2 0_0402_5%~D 32 15 R961 1 R963 1 2 0_0402_5%~D 2 0_0402_5%~D 31 16 +ESATA_PWR R965 R967 1 1 @ R968 1 +ESATA_PWR @R969 @ R969 @R970 @ R970 SEL1_A SEL1_B AO+ AO- 27 26 ESATA_ITX_DRX_P ESATA_ITX_DRX_N BIBI+ 21 22 ESATA_IRX_DTX_N ESATA_IRX_DTX_P SEL2_A SEL2_B 30 29 EN_A EN_B 19 IREF 2 0_0402_5%~D 2 0_0402_5%~D 11 12 R301 43.2K_0402_1%~D R302 <19> 75K_0402_1% USBP0+ 1 <19> USBP0- 2 USB_CHARGE_D+ 3 USB_CHARGE_D- OUT+ OUT- 17 18 @ R960 1 @R960 @R962 @ R962 1 2 0_0402_5%~D 2 0_0402_5%~D SD_A SD_B 36 35 @ R964 1 @R964 @R966 @ R966 1 2 0_0402_5%~D 2 0_0402_5%~D GND GND GND GND AGND 25 20 9 4 24 C466 0.1U_0402_16V4Z~D 1 2 U18 2 R953 390_0402_5% C944 4700P_0402_25V7K~D 2 1 ESATA_ITX_C_DRX_N 4 5 SEL3_A SEL3_B 2 10K_0402_1%~D 2 10K_0402_1%~D USB_DETECT 2 470_0402_5%~D 1 1 1 6 10 23 28 5 10 +3VALW 9 PWRSHARE_OE# D+ 8 USBP0_R_D+ D- 7 1D+ VCC 1D- S 2D+ 2DGND OE# USBP0_R_D- 6 R304 49.9K_0402_1%~D R305 49.9K_0402_1%~D PAD S OE# Function X H L H L L Disconnect D=1D D=2D TS3USB221RSER_QFN10_2x1P5~D S Logic"1" Work from BKT CLKIN+ CLKIN- PWRSHARE_OE# <31> R303 100K_0402_5%~D 2 1 1 2 ESATA_USB_OC# <19> TPS2062ADR_SO8~D 1 @ R956 @ R957 SEL0_A SEL0_B 1 C941 4700P_0402_25V7K~D 2 1 ESATA_ITX_C_DRX_P VDD VDD VDD VDD VDD AVDD 2 34 13 BO+ BO- 2 +5V_CHGUSB 1 7 8 AI+ AI- 2 1 2 3 2 <15> SATA_IRX_DTX_N5 SATA_ITX_C_DRX_P5 SATA_ITX_C_DRX_N5 1 2SATA_IRX_C_DTX_P5 C942 0.01U_0402_16V7K~D 1 2SATA_IRX_C_DTX_N5 C943 0.01U_0402_16V7K~D R954 1 2 0_0402_5%~D R955 1 2 0_0402_5%~D 2 1 ESATA_USB_OC# 8 7 6 5 OC1# OUT1 OUT2 OC2# 2 U40 <15> SATA_ITX_C_DRX_P5 <15> SATA_ITX_C_DRX_N5 <15> SATA_IRX_DTX_P5 2 1 1 -3.5dB 1 1 0dB 1 1 C940 0.1U_0402_16V4Z~D 0 1 C939 0.1U_0402_16V4Z~D * 1 C938 0.1U_0402_16V4Z~D 1.2x 1 C937 0.1U_0402_16V4Z~D 1x 1 De-emphasis C936 0.1U_0402_16V4Z~D 0 * SEL3_ [A:B] C463 10U_0805_10V4Z~D Swing C462 0.1U_0402_16V4Z~D SEL2_ [A:B] Output De-emphasis Adjustment C935 10U_0805_10V4Z~D <31> PWRSHARE_EN# Output Swing Control GND IN EN1# EN2# 1 +1.8VS SATA_ITX_C_DRX_P5 SATA_ITX_C_DRX_N5 2 Place close U40 pin 2 & pin3 +5V_CHGUSB 1 + 37 1 C460 150U_D2_6.3VM~D 2 C461 0.1U_0402_16V4Z~D ESATA 2 PI2EQX3201BZFEX_TQFN36_6X5 R0.3 depop JESA1 R0.3 change to SA00002YQ0L (S IC PI2EQX3201BLZFEX TQFN 36P) USBP0_R_D- Equalizer Selection SEL0_ [A:B] SEL1_ [A:B] 1 USB_DETECT * D @ Q63 PMF3800SN_SC70-3 2 G 3 USB_DETECT# 0 S 0 CH1 Compliance Channel 2 1 [0:2.5dB] @ 1.6 GHz 1 1 0 [2.5:4.5dB] @ 1.6 GHz 1 1 no equalization 0 4 D34 CH4 Vn Vp 4 5 4 [4.5:6.5dB] @ 1.6 GHz CH2 CH3 6 USBP0_R_D+ USBP0_DUSBP0_D+ 1 1 2 2 @L89 @ L89 WCM2012F2S-900T04_0805 R1571 1 2 0_0402_5%~D +5V_CHGUSB 2 0_0402_5%~D USBP0_D+ R1.0 modify @ CM1293-04SO_SOT23-6 R0.3 depop 3 USBP0_D- R1572 1 3 3 ESATA_ITX_C_DRX_P ESATA_ITX_C_DRX_N ESATA_IRX_DTX_N 2 C464 ESATA_IRX_DTX_P 2 C465 1 ESATA_IRX_C_DTX_N 4700P_0402_25V7K~D 1 ESATA_IRX_C_DTX_P 4700P_0402_25V7K~D 5 6 7 8 9 10 11 12 13 <32> USB_DETECT# Place close JESA1 1 2 3 4 VBUS DD+ GND USB GND A+ ESATA AGND GND BGND B+ GND GND GND 14 15 16 17 DET1 DET2 FOX_3Q3813C-RB1C3B-7F CONN@ Cardreader Connector @ L27 WCM2012F2S-900T04_0805 1 1 2 2 4 4 Bluetooth Camera Conn 3 3 JCAM1 <19> USBP11+ <19> USBP11+3VS <25> DMIC_CLK <25> USBP11+ USBP11- 1 0_0402_5%~D USBP_P11 1 0_0402_5%~D USBP_N11 1 BLM18BB221SN1D_2P~D DMIC_CLK R297 2 R299 2 L28 2 DMIC0 DMIC0 2 1 2 C459 100P_0402_50V8J~D 1 C458 100P_0402_50V8J~D Layout note: Pin5 thru individual via to GND layer 1 2 3 4 5 6 7 8 9 JBT1 <31> BT_DET# <27,28> COEX2_WLAN_ACTIVE <31> BT_OFF# <31> BT_RADIO_OFF# 1 2 3 4 5 6 7 BT_DET# 1 COEX2_WLAN_ACTIVE3 BT_OFF# 5 BT_RADIO_OFF# 7 9 11 13 15 2 4 6 8 10 12 14 GNDGND 2 BT_ACTIVE 4 6 USBP10+ 8 USBP1010 12 14 BT_ACTIVE <27> +3VS USBP10+ <19> USBP10- <19> 16 @ R995 10K_0402_5%~D BT_ACTIVE 1 2 <16> PCIE_ITX_C_CBRX_P4 <16> PCIE_ITX_C_CBRX_N4 <16> PCIE_IRX_CBTX_P4 <16> PCIE_IRX_CBTX_N4 @ USBP10- C457 1 <16> CLK_PCIE_CB <16> CLK_PCIE_CB# 2 47P_0402_50V8J~D @ USBP10+ D35 USBP_P11 1 CH1 CH4 4 DMIC_CLK <19> <19> HRS_DF12(3.0)-14DP-0.5V(86)~D GND GND MOLEX_48227-0701 CONN@ 1 3 5 7 9 11 13 C456 1 FOX_GS12301-1011A-9F~D 30 30 G4 34 29 29 G3 33 28 28 G2 32 27 31 USBP1+ 27 G1 26 26 USBP125 25 24 +5VALW 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 +3VS 16 16 15 15 14 14 13 13 12 12 PCIE_ITX_C_CBRX_P4 11 11 PCIE_ITX_C_CBRX_N4 10 10 9 9 PCIE_IRX_CBTX_P4 8 8 PCIE_IRX_CBTX_N4 7 7 6 6 CLK_PCIE_CB 5 5 CLK_PCIE_CB# 4 4 3 3 CB_CLKREQ# 2 2 PLT_RST# 1 1 to Single USB board <31> USB_EN# <19> USB_OC1# <16> CB_CLKREQ# <6,19,24,27,28,31> PLT_RST# 2 47P_0402_50V8J~D +5VALW <19> <19> JSUSB1 1 2 3 4 5 6 7 8 9 10 USBP2USBP2+ <31> USB_EN# <19> USB_OC2# <31> BATT_CHG_LED# <31> BATT_LOW_LED# 11 12 1 2 3 4 5 6 7 8 9 10 G1 G2 FCI_10089709-010010-LF CONN@ JCARD1 CONN@ 2 Vn 3 CH2 Vp 5 +3VS CH3 6 DMIC0 @ CM1293-04SO_SOT23-6 Place close JCAM1 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification USBP_N11 2009/09/21 Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title USB/BlueTooth/Camera/ESATA Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 30 of 49 +3VALW R0.3 modify 2 ECAGND R315 2 1 2.2K_0402_5%~DEC_SMB_CK1 R324 1 2 10K_0402_5%~D MSEN# R308 1 2 47K_0402_5% GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 <20> GATEA20 <20> KB_RST# <15> SERIRQ <15,27> LPC_FRAME# <15,27> LPC_AD3 <15,27> LPC_AD2 <15,27> LPC_AD1 <15,27> LPC_AD0 KSO2 <19> CLK_PCI_EC <6,19,24,27,28,30> PLT_RST# KSO1 For ENE strape pin <20> EC_SCI# <15,32> TOUCHKEY_TINT R0.3 Modify CLK_PCI_EC PLT_RST# EC_RST# EC_SCI# TOUCHKEY_TINT 1 2.2K_0402_5%~DEC_SMB_DA2 R318 2 1 2.2K_0402_5%~DEC_SMB_CK2 1 4.7K_0402_5%~DLCD_TST <32> 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 77 78 79 80 KSO[0..18] KSO[0..18] 1 4.7K_0402_5%~DBT_RADIO_OFF# R339 2 1 4.7K_0402_5%~D EC_FB_SCLK R342 2 1 4.7K_0402_5%~D EC_FB_SDATA +5VS R325 2 1 4.7K_0402_5%~D TP_DATA R326 2 1 4.7K_0402_5%~D TP_CLK R948 1 2 200K_0402_5% <47> <47> <16,27,28> <16,27,28> KSO5 EC Adam_Yang request <17,24,27,28> ICH_PCIE_WAKE# EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 SLP_S3# 6 PM_SLP_S5# 14 EC_SMI# 15 LID_SW# 16 EC_FB_SCLK 17 EC_FB_SDATA 18 PCIE_PME# 19 KB_BL_PWM# 25 FAN_SPEED1 28 WLAN_RADIO_OFF# 29 EC_TX_P80_DATA 30 EC_RX_P80_DATA 31 ON_OFF 32 PWR_BTN_LED# 34 EN_KBL# 36 <17> SLP_S3# <17> PM_SLP_S5# <20> EC_SMI# <32> LID_SW# <32> EC_FB_SCLK <32> EC_FB_SDATA 2 0_0402_5%~D R977 1 12 13 37 20 38 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSO18 +3VS R317 2 1 2 3 4 5 7 8 10 GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC <32> KB_BL_PWM# <14> FAN_SPEED1 <27> WLAN_RADIO_OFF# <17,27> EC_TX_P80_DATA <27> EC_RX_P80_DATA <32> ON_OFF <32> PWR_BTN_LED# <32> EN_KBL# XCLKI XCLKO PWM Output AD PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D 122 123 KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 PS2 Interface 2 SPI Flash ROM GPIO PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS# CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 2 R311 100K_0402_5%~D Ra 1 63 64 65 66 75 76 EC_PWM EC_PWM <35> BEEP# BEEP# <25> PWRSHARE_EN# PWRSHARE_EN# <30> ACOFF ACOFF <41> C522 1 2 0.01U_0402_16V7K~DECAGND C476 1 2 0.01U_0402_16V7K~DECAGND BATT_TEMP BATT_TEMP <47> BATT_OVP BATT_OVP <47> ADP_I ADP_I <41> AD_BID MSEN# MSEN# <35> SUS_PWR_ACK_R 1 2 SUS_PWR_ACK <17> R1569 0_0402_5%~D VCC * * 68 70 71 72 EC_SUB_MUTE# EN_DFAN1 IREF 83 84 85 86 87 88 LCD_TST USB_EN# GFXVR_PWRGD KSO5 TP_CLK TP_DATA 97 98 99 109 WPAN_RADIO_OFF# EN_WOL# BT_OFF# VGATE 119 120 126 128 FRD#SPI_SO FWR#SPI_SI SPI_CLK FSEL#SPICS# 73 74 89 90 91 92 93 95 121 127 EC_SPK_HP_MUTE# USB_DET#_DELAY FSTCHG BATT_CHG_LED# PWRSHARE_OE# BATT_LOW_LED# BKLT_KB_DET# SYSON VR_ON EC_ACIN 100 101 102 103 104 105 106 107 108 EC_RSMRST# EC_LID_OUT# EC_ON BT_RADIO_OFF# ICH_PWROK BKOFF# WWAN_RADIO_OFF# LCD_VCC_TEST_EN CP_SEL 110 112 114 115 116 117 118 PCH_GPIO49 EC_ENBKL BT_DET# SBPWR_EN SUSP# PBTN_OUT# PS_ID R1.0 modify * EC_SUB_MUTE# <25> EN_DFAN1 <14> IREF <41> CHGVADJ <41> 3.3V+/-5% Ra 4 G G 0.6V~1.6V 100K Board ID VGA Rb X00 UMA 0 +/- 5% 0V X01 UMA 8.2K+/- 5% 0.250V X02 UMA 18K +/- 5% 0.503V MP UMA 33K +/- 5% 0.819V LCD_TST <35> USB_EN# <30> GFXVR_PWRGD <48> KSO5 <32> TP_CLK <32> TP_DATA <32> Follow the suggestion of EC team to follow JAT10 setting. WPAN_RADIO_OFF# <28> EN_WOL# <24> BT_OFF# <30> VGATE <13,17,46> place close U19 R333 15_0402_5%~D 2 1 EC_SPK_HP_MUTE# <25> USB_DET#_DELAY <32> FSTCHG <41> BATT_CHG_LED# <30> PWRSHARE_OE# <30> BATT_LOW_LED# <30> BKLT_KB_DET# <32> SYSON <28,33,44> VR_ON <46> * * SPI_CLK_R 1 2 R557 0_0402_5%~D 1 2 EC_ENBKL 22P_0402_50V8J~D C1122 IGPU_BKLT_EN <18> * 10K_0402_5%~D 2 +3VALW R1215 1 EC_RSMRST# <17> EC_LID_OUT# <16> EC_ON <32> BT_RADIO_OFF# <30> ICH_PWROK <17> BKOFF# <35> WWAN_RADIO_OFF# <27> LCD_VCC_TEST_EN <35> CP_SEL <41> EC_ACIN 2 1 D54 CH751H-40PT_SOD323-2~D ACIN <17,25,40,41> Place under u20 GPI V18R 124 SPI_CS# SPI_SO +SPI_R * PCH_GPIO49 <20> BT_DET# <30> SBPWR_EN <33> SUSP# <28,33,43,44,45> PBTN_OUT# <6,17> PS_ID <40> * C480 1 2 1U_0603_10V4Z~D C482 2 1 0.1U_0402_16V4Z~D 1 3 5 7 1 3 5 7 2 4 6 8 2 4 6 8 +SPI_R SPI_CLK_R SPI_SI +3VALW E&T_2941-G08N-00E~D CONN@ SPI Flash (1Mbit/128Kbyte) SPI_CLK_R 2 R330 1 22_0402_5%~D 2 3 32.768KHZ_12.5PF_QTFM28-32768K1 22P_0402_50V8J~D 1 C483 ECAGND C481 33P_0402_50V8J~D C479 33P_0402_50V8J~D 2 1 2 Rb 20mils D3 Version : P/N : SA00001J580 R329 +3VALW 10K_0402_5%~D 2 1 Y5 1 AD_BID R312 C477 33K_0402_5%~D 0.1U_0402_16V4Z~D 2 JP1 PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 XCLK1 XCLK0 GND GND GND GND GND XCLKI 1 R328 2 @ 20M_0603_5% @ C478 15P_0402_50V8J~D PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F 21 23 26 27 SPI Device Interface SM Bus KB926QFD3_LQFP128 XCLKO 1 DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0 11 24 35 94 113 2 R327 10_0402_5%~D BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 DA Output 1 CLK_PCI_EC @ C474 0.1U_0402_16V4Z~D R1.0 modify INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 KSI[0..7] <32> KSI[0..7] R320 2 1 1 1 2.2K_0402_5%~DEC_SMB_DA1 @ R319 2 2 R0.3 modify BLM18BD601SN1D_0603~D AGND 1 10K_0402_5%~D R314 2 2 47K_0402_5% 2 EN_KBL# R926 2 R309 1 1 L30 1 10K_0402_5%~D USB_DET#_DELAY @ R1237 2 C473 1000P_0402_50V7K~D 1 +EC_AVCC 67 U19 +3VALW Board ID +3VALW 69 R0.3 Modify 1 0.1U_0402_16V4Z~D 2 VCC VCC VCC VCC VCC VCC C475 2 2 L29 BLM18BD601SN1D_0603~D 2 1 AVCC 2 470_0402_5%~D EC_RST# 2 +EC_AVCC 9 22 33 96 111 125 R307 1 KSI4 2 1 C472 1000P_0402_50V7K~D 2 47K_0402_5% 2 1 C471 1000P_0402_50V7K~D R322 1 2 1 C470 0.1U_0402_16V4Z~D 1 10K_0402_5%~D PCIE_PME# 1 C469 0.1U_0402_16V4Z~D R306 2 1 C468 0.1U_0402_16V4Z~D Add 47K pull high +3VALW C467 0.1U_0402_16V4Z~D 1 2 +SPI_R FSEL#SPICS# FRD#SPI_SO R331 15_0402_5%~D 2 1 SPI_CS# 1 2 SPI_SO R332 15_0402_5%~D 1 U20 1 2 3 4 CS# SO WP# GND VCC HOLD# SCLK SI 8 7 6 5 C484 0.1U_0402_16V4Z~D SPI_CLK_R SPI_SI 1 MX25L1005AMC-12G_SO8 2 FWR#SPI_SI R334 15_0402_5%~D R0.3 modify Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title EC_KB926/BIOS/Reed SW Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 31 of 49 A B C D E INT_KB_Conn.1 Power Button Circuit R335 JPBTN1 1 2 3 4 1 2 3 4 R0.3 Modify 1 R896 200_0402_5%~D 1 2 PWR_LED+ +5VALW PWR_BTN_LED# <31> PWR_BTN_LED# PWR_ON-OFF_BTN# D11 2 5 6 G5 G6 JAE_FL4S030HB3R3000 100K_0402_5%~D 2 To power board 1 +3VALW <31> KSO[0..18] <31> KSO[0..18] 1 <14> PWR_ON-OFF_BTN# KSI[0..7] <31> KSI[0..7] ON_OFF MOLEX_53261-0471 CONN@ 51ON# 3 51ON# KSI7 KSI6 KSI4 KSI2 KSI5 KSI1 KSI3 KSI0 KSO5 KSO4 KSO7 KSO6 KSO8 KSO3 KSO1 KSO2 KSO0 KSO12 KSO16 KSO15 KSO13 KSO14 KSO9 KSO11 KSO10 KSO17 KSO18 <40> BAT54C-7-F_SOT23~D 1 D30 EC_ON 1 PESD24VS2UT_SOT23-3~D 2 Q6 2 G R336 0_0402_5%~D 1 EC_ON PMF3800SN_SC70-3 <31> 2 3 3 PWR_ON-OFF_BTN# 1 D S R337 10K_0402_5%~D 2 Place close JPBTN1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND GND 32 31 KSI0 @ C485 100P_0402_50V8J~D KSO6 @ C486 100P_0402_50V8J~D KSI1 @ C487 100P_0402_50V8J~D KSO7 @ C488 100P_0402_50V8J~D KSI2 @ C489 100P_0402_50V8J~D KSO8 @ C490 100P_0402_50V8J~D KSI3 @ C491 100P_0402_50V8J~D KSO9 @ C492 100P_0402_50V8J~D KSI4 @ C493 100P_0402_50V8J~D KSO10 @ C494 100P_0402_50V8J~D KSI5 @ C495 100P_0402_50V8J~D KSO11 @ C496 100P_0402_50V8J~D KSI6 @ C497 100P_0402_50V8J~D KSO12 @ C498 100P_0402_50V8J~D KSI7 @ C499 100P_0402_50V8J~D KSO13 @ C500 100P_0402_50V8J~D KSO0 @ C501 100P_0402_50V8J~D KSO14 @ C502 100P_0402_50V8J~D KSO1 @ C503 100P_0402_50V8J~D KSO15 @ C504 100P_0402_50V8J~D KSO2 @ C505 100P_0402_50V8J~D KSO16 @ C506 100P_0402_50V8J~D KSO3 @ C507 100P_0402_50V8J~D KSO17 @ C508 100P_0402_50V8J~D KSO4 @ C509 100P_0402_50V8J~D KSO18 @ C510 100P_0402_50V8J~D KSO5 @ C511 100P_0402_50V8J~D 1 For EMI JKB1 CONN@ RTCVREF CLOSE TO U48 C1068 0.1U_0402_16V4Z~D Touch Screen Connector 51ON# <40> R0.3 Modify D36 1 2 NC A Y 4 Vn Vp 5 1 2 3 4 5 6 7 8 +3VS R1236 2 S R1145 100K_0402_5%~D 3 +3VS <19> <19> USBP9USBP9+ 2 0_0402_5%~D USBP9USBP9+ CH2 CH3 USBP9+ 6 2 R1238 1 1 D52 SDMK0340L-7-F USB_DET#_DELAY 2 <31> <31> <31> TP_CLK LID_SW# TP_DATA 1 2 3 4 5 6 TP_CLK LID_SW# TP_DATA +HALL_VCC 1 2 1 3 2 D BKLT_KB_DET# 1 BKLT_KB_DET# <31> D 3 1 Q39 MMBF170LT1G 1N SOT23-3 +5VS +3VS Cap Sensor S JCAP1 EN_KBL R931 2M_0402_5%~D FB_SDATA FB_SCLK R1003 @1 1 2 BLM18BD601SN1D_0603~D 1 2 BLM18BD601SN1D_0603~D TOUCHKEY_TINT 2 <31> EC_FB_SDATA <31> EC_FB_SCLK <15,31> TOUCHKEY_TINT L77 L78 3 Q40 PMF3800SN_SC70-3 6 5 4 3 2 0_0402_5%~D 2 1 1 +5VS_KBL C959 33P_0402_50V8J~D FB_SDATA 2 D56 PESD5V2S2UT_SOT23-3~D 1 C960 33P_0402_50V8J~D FB_SCLK 2 R0.3 Modify 1 JKBL1 BKLT_KB_DET 4 1 KB_BL_PWM D 1 2 3 4 1 2 3 GND 4 GND 5 6 3 S 20mil B 8 7 TYCO_2041084-6 CONN@ 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A 6 G2 5 G1 4 3 2 1 TYCO_2041084-4 CONN@ Q41 MMBF170LT1G 1N SOT23-3 2 G <31> KB_BL_PWM# 20mil 7 8 TYCO_2041084-6~D CONN@ 1 S 1 1 2 3 4 5 G1 6 G2 2 2 2 D 2 G R0.3 Modify C521 0.1U_0402_16V4Z~D 2 1 EN_KBL# 3 <31> D55 PESD5V2S2UT_SOT23-3~D 2 1 R927 10K_0402_5%~D S G 3 2 1 2 +HALL_VCC 0_0402_5%~D 2 LID_SW# 10K_0402_5%~D 1 +3VS 2 C514 100P_0402_50V8J~D C928 1U_0603_10V6K~D R928 300K_0402_5% 1 1 R933 1 R934 +3VALW C513 100P_0402_50V8J~D C512 0.1U_0402_16V4Z~D 3 3 1 B+_BIAS C927 0.1U_0402_16V4Z~D 2 JTP1 Touch PAD/B Conn. Power share Q38 +5VS_KBL SI3456BDV-T1-E3 1N TSOP6 W/D @ F1 0.75A_24V_1812L075-24DR~OK 6 5 4 2 1 2 20mil BKLT_KB_DET 1 1 2 2 G R929 20mil 0_0805_5%~D R930 100K_0402_5%~D 1 USB_DET#_DELAY <31> @ D58 SDMK0340L-7-F Keyboard back light +3VS JST_SM08B-SURS-TF(LF)(SN)~D CONN@ Place close JTCH1 R0.3 Modify +5VS +5VS 1 2 3 4 5 6 7 8 @ CM1293-04SO_SOT23-6 0_0402_5%~D 2 1 2 USBP9- 4 1 3 U51 TC7SZ14FU_SSOP5~D CH4 1 Q56 2N7002LT1G_SOT23-3 3 2.2U_0603_10V7K~D CH1 D 2 G G 1 1 5 1 10 2 2 JTCH1 G2 51ON# P 1 1 2 2 2 2 C1069 1 D51 SDMK0340L-7-F USB_DETECT# <30> USB_DETECT# R1144 220K_0402_5% R1143 10K_0402_1%~D 1 2 G1 RTCVREF 9 RTCVREF 2 RTCVREF C D Title PWROK/BTN/KB/Touch Pad Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet E 32 of 49 A B C 1 SYSON# D SBPWR_EN 2 G <31> SBPWR_EN 0.1U_0402_16V4Z~D 1 SBPWR_EN# <22> SBPWR_EN# 2 Q59 PMF3800SN_SC70-3 SYSON <28,31,44> SYSON S R1154 10K_0402_5%~D 1 D Q16 PMF3800SN_SC70-3 2 G S 3 1 1 1 C1072 4 1 2 2 C1071 2 1 2 R1235 R354 100K_0402_5%~D 1 Q60 S PMF3800SN_SC70-3 2 G C1073 R1151 3 SBPWR_EN# D 10U_0805_10V4Z~D 2 1 2 1 2 R1153 0_0402_5%~D C524 0.01U_0402_25V7K~D 3V_GATE 1 +5VALW 100K_0402_5%~D C1070 2 10U_0805_10V4Z~D 2 2 330K_0402_5% 169mA 1 2 3 2M_0402_5%~D 2 Q7 S PMF3800SN_SC70-3 2 G R340 2M_0402_5%~D 1 SUSP 3 1 1 D 2 1 1 R0.3 modify 2 1 R1152 3 4 1 2 1 AO4468 1N SO8 C517 10U_0805_10V4Z~D 3 2 1 C516 0.1U_0402_16V4Z~D 2 C515 10U_0805_10V4Z~D 330K_0402_5% U52 SI4800BDY-T1-E3_SO8 8 7 6 5 8.73A 8 7 6 5 +5VALW JP9 2 1 B+_BIAS U21 1 1 0.01U_0402_25V7K~D B+_BIAS 1 +3V @ +3VS 2 +3VALW R338 E +3VALW to +3V Transfer (PCH AUX Power) +3VALW to +3VS Transfer +3VALW D R355 10K_0402_5%~D +5VALW to +5VS Transfer +3VALW +5VALW +5VS +3VALW C525 0.01U_0402_25V7K~D C1147 2 1 2 100K_0402_5%~D 74AHC1G08GW_SOT353-5~D C1148 @ 2 R1252 1 0_0402_5%~D 1.5VS_DDR_PWRGD 1 2 SUSP# <28,31,43,44,45> SUSP# D 2 G 2 2 <44> 1 4 O SUSP SUSP Q13 S D Q21 PMF3800SN_SC70-3 2 G 3 P IN2 100K_0402_5%~D R396 2 1 S 2 G Q75 PMF3800SN_SC70-3 3 D 2 G IN1 1 5 2 SUSP 1 1 2 R360 0.01U_0402_25V7K~D Q68 S PMF3800SN_SC70-3 1 C1146 2 0.1U_0402_10V6K~D U64 PMF3800SN_SC70-3 3 @ R341 2 3 1 D 2 1 2 G 3 SUSP 2 R0.3 modify 0.01U_0402_25V7K~D 4 AO4468 1N SO8 2 1 1 100K_0402_5%~D 1 1 390K_0402_5% 1 2 2 R379 3 2 1 C520 10U_0805_10V4Z~D 330K_0402_5% 8 7 6 5 1 C519 0.1U_0402_16V4Z~D C518 10U_0805_10V4Z~D R1216 1 7.69A U22 +5VALW 1 B+_BIAS S R361 10K_0402_5%~D +1.5V to +1.5VS Transfer B+_BIAS +1.5VS +1.5V 470_0402_5%~D 470_0402_5%~D 470_0402_5%~D 470_0603_5% 2 C534 SUSP 1 1 D 2 G S Q19 PMF3800SN_SC70-3 3 1 470_0402_5%~D 2 R356 470_0402_5%~D D 3 SUSP S Q17 PMF3800SN_SC70-3 2 G S Q20 PMF3800SN_SC70-3 4 470P_0402_50V7K~D Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A R359 2 1 2 1 S Q74 PMF3800SN_SC70-3 D S Q54 PMF3800SN_SC70-3 +3VS 1 +5VS 2 G 3 1 2 1 SUSP D 2 G S Q12 PMF3800SN_SC70-3 R358 470_0603_5% D 2 G 3 2 SUSP SUSP 3 +0.75VS 1 1 2 2M_0402_5%~D 1 R1.0 modify 2 1 2 1 3 Q11 S PMF3800SN_SC70-3 R1158 1 D 2 G S Q61 PMF3800SN_SC70-3 220_0402_5%~D R364 R349 20K_0402_1%~D C536 D 2 G S S S G Si4634 1N SO8 4 SUSP D D D D SUSP 3 3 S Q15 PMF3800SN_SC70-3 +1.5V_CPU_DDR 10U_0805_10V4Z~D R346 470K_0402_5% D SBPWR_EN# 2 G +1.5V_CPU_DDR 1 2 3 4 1 1 D 2 G Q73 8 7 6 5 2 R1034 1 R352 2 R1155 3 SYSON# +1.5V 1 1 1 470P_0402_50V7K~D +1.5V to +1.5VS_DDR Transfer B+_BIAS +1.1VS_VTT R353 2 C532 +1.05VS 3 1 2 +3V 1 1 R1.0 modify +1.5V 2 R1157 2 1 4 2 1 Q10 S PMF3800SN_SC70-3 2 G 2M_0402_5%~D 1 3 SUSP D 1 2 1 2 Si4634 1N SO8 R345 20K_0402_1%~D C531 3 2 1 10U_0805_10V4Z~D 8 7 6 5 R344 470K_0402_5% 3 Discharge Circuit Q55 B C D Title DC/DC Interface Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet E 33 of 49 5 4 FD3 FIDUCAL FD4 FIDUCAL 1 ZZZ @ 1 @ 1 1 D FD2 FIDUCAL @ 2 D 1 FD1 FIDUCAL @ 3 PCB H_2P5 H6 @ HOLEA 1 H_2P2 H_3P1 H2 @ HOLEA C C H10 @ HOLEA H11 @ HOLEA H12 @ HOLEA H5 @ HOLEA H14 @ HOLEA 1 H9 @ HOLEA 1 H8 @ HOLEA 1 H7 @ HOLEA 1 1 H_1P6N H15 @ HOLEA H16 @ HOLEA 1 1 H23 @ HOLEA H35 @ HOLEA H36 @ HOLEA 1 1 1 1 1 H21 @ HOLEA 1 1 H24 @ HOLEA 1 1 H19 @ HOLEA 1 H18 @ HOLEA H3 @ HOLEA H4 @ HOLEA H20 @ HOLEA 1 H17 @ HOLEA 1 1 H_3P0 1 1 H25 @ HOLEA H26 @ HOLEA H27 @ HOLEA H28 @ HOLEA 1 1 1 1 H_3P2 B B H_4P0 H29 @ HOLEA 1 H_3P0X4P0 A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Issued Date Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Screws Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 34 of 49 4 3 1 CRT 2 D15 DAN217_SC59-3 D16 DAN217_SC59-3 1 D14 DAN217_SC59-3 1 +5VS +CRT_VCC W=40mils 1 5 D17 CRT_B P OE# G 3 P OE# U27 74AHCT1G125GW_SOT353-5 2 2 1 3 1 1 S 1 2 1 C550 4.7U_0805_10V4Z~D C551 0.1U_0402_16V4Z~D 6 5 2 1 <18> <18> 1 2 @ 1 C1128 C1127 0.1U_0603_50V4Z~D @ 1 C1129 PWR_SRC_ON 2 2 5P_0402_50V8C <18> <18> 2 5P_0402_50V8C <18> <18> <18> <18> 3 2 1 D S 2 G R1.0 Modify @ 1 C1130 Q71 SSM3K7002FU_SC70-3~D @ 1 C1131 <18> <18> 2 5P_0402_50V8C <18> <18> 2 5P_0402_50V8C R02: Reserve for EMI (Place close to JLVDS1) +3VS 1 <31> EC_PWM 2 @ R394 10K_0402_5%~D U54 2 VGA_PWM INA O 4 INB R382 74AHC1G32GW_SOT353-5~D 4.7K_0402_5%~D <31> BKOFF# BKOFF# 1 2 D19 2 @ R944 0_0402_5%~D 2 1 DISPOFF# @ R945 0_0402_5%~D 2 1 CH751H-40PT_SOD323-2~D 5 4 40 39 38 37 +3VS LCD_TST 36 EDID_CLK_LCD 2 1 0_0402_5%~D 35 2 1 0_0402_5%~D EDID_DATA_LCD 34 LVDS_A033 LVDS_A0LVDS_A0+ 32 LVDS_A0+ 31 LVDS_A130 LVDS_A1LVDS_A1+ 29 LVDS_A1+ 28 LVDS_A227 LVDS_A2LVDS_A2+ 26 LVDS_A2+ 25 LVDS_ACLK24 LVDS_ACLKLVDS_ACLK+ 23 LVDS_ACLK+ 22 LVDS_B021 LVDS_B0LVDS_B0+ 20 LVDS_B0+ 19 LVDS_B118 LVDS_B1LVDS_B1+ 17 LVDS_B1+ 16 LVDS_B215 LVDS_B2LVDS_B2+ 14 LVDS_B2+ 13 LVDS_BCLK12 LVDS_BCLKLVDS_BCLK+ 11 LVDS_BCLK+ 10 9 8 7 INVT_PWM 6 DISPOFF# 5 4 3 +INV_PWR_SRC 2 1 W=60mils INVT_PWM 1 3 1 A <18> G +3VS P 5 1 +3VS <18> <18> R1243 100K_0402_5%~D +LCDVDD R374 R375 <18> <18> 3 G 40mil <31> LCD_TST <18> LVDS_DDC_CLK <18> LVDS_DDC_DATA +INV_PWR_SRC D R0.3 Modify +INV_PWR_SRC 2 R380 10K_0402_5%~D 2 2 1 1 3 Q26 BSS138_SOT23~D D S 2 G 1 +LCDVDD 2 G LCD_VCC_TEST_EN 3 BAT54C-7-F_SOT23~D Q70 SI3457BDV-T1-E3_TSOP6~D 4 +LCDVDD 6.5 C549 0.1U_0402_16V4Z~D 1 <31> LCD_VCC_TEST_EN 2 C 1 3 S 1 1 AO3413_SOT23-3 Q25 R1242 100K_0402_5%~D 2 1 D 2 0_0805_5%~D 1 +LCDVDD C1126 1000P_0402_50V7K~D R378 56K_0402_5% 2 1 W=60mils 2 2 @ R381 1 40mil S <18> VGA_LVDDEN 3 2 3 Y B+ D37 VGA_LVDDEN 1 4 A 3 2 R0.3 Modify 2 G VSYNC_L 2 0_0603_5%~D R373 10K_0402_5%~D 1 2 +3VS R377 47K_0402_5% D R1161 D_CRT_VSYNC 1 R02: Add W=60mils Q24 SSM3K7002FU_SC70-3~D TYCO_1775763-2 CONN@ 2 HSYNC_L 2 0_0603_5%~D 1 U26 74AHCT1G125GW_SOT353-5 B+ B 16 17 R1160 D_CRT_HSYNC 4 Y 5 1 D D S CRT_VSYNC <18> CRT_VSYNC R376 470_0805_5% G G 5 1 2 2 1 2 A +CRT_VCC C546 0.1U_0402_16V4Z~D 1 2 Q23 PMF3800SN_SC70-3 +5V 1 D C548 15P_0402_50V8J~D S 2 2 G 1 1 1 2 2 2 2 2 1 1 1 1 1 2 1 CRT_HSYNC <18> CRT_HSYNC CRT_DDC_CLK_C +LCDVDD 2 C544 100P_0402_50V8J~D +CRT_VCC C545 0.1U_0402_16V4Z~D 1 2 CRT_DDC_DATA_C Q22 PMF3800SN_SC70-3 1 CRT_DDC_CLK_C 1 C547 15P_0402_50V8J~D 1 VSYNC_L C543 100P_0402_50V8J~D 3 C535 1U_0603_10V6K~D 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 MSEN# CRT_R_L HSYNC_L CRT_B_L C542 10P_0402_50V8J~D For EMI @ C541 10P_0402_50V8J~D 2 MSEN# CRT_DDC_DATA_C CRT_G_L C540 10P_0402_50V8J~D @ 1 C539 22P_0402_50V8J~D 2 @ C538 22P_0402_50V8J~D 2 1 R372 2K_0402_1%~D G G 3 <18> CRT_DDC_CLK BLM18BB470SN1D_2P~D 2 CRT_B_L +CRT_VCC +CRT_VCC R371 2K_0402_1%~D R370 2.2K_0402_5%~D R369 2.2K_0402_5%~D <18> CRT_DDC_DATA 1 C537 22P_0402_50V8J~D +3VS 1 L33 R368 150_0402_1%~D +3VS R367 150_0402_1%~D @ +3VS C R366 150_0402_1%~D @ CU58 10P_0402_50V8J~D CU57 10P_0402_50V8J~D CU56 10P_0402_50V8J~D @ BLM18BB470SN1D_2P~D 2 CRT_G_L 1 BLM18BB470SN1D_2P~D 2 1 2 1 LU8 <18> VGA_CRT_B L32 1 JCRT1 <31> 1 CRT_G BLM18BB470SN1D_2P~D 2 CRT_R_L 1 2 BLM18BB470SN1D_2P~D 2 2 <18> VGA_CRT_G 1 2 LU7 L31 CRT_R 1 BLM18BB470SN1D_2P~D 2 1 1 BAT1000-7-F_SOT23-3~D 2 2 LU6 <18> VGA_CRT_R 2 CU55 1 2 D 2 0.1U_0402_16V4Z~D 3 2 3 NC +3VS W=40mils 2 40 G9 49 39 G8 48 47 38 G7 37 G6 46 36 G5 45 35 G4 44 34 G3 43 33 G2 42 32 G1 41 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 JLVDS1 JAE_FI-G40SB-VF25-R2000 CONN@ reserve for RF request @ CU63 470P_0402_50V7K~D Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Title VGA / LVDS Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 35 of 49 B A 5 4 3 2 1 +3VS 1 +3VS CU22 1 CU23 1 CU18 1 CU24 1 2 2 2 2 2 1 OE# 2 2 QU1 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D RU92 0_1206_5% D 0.1U_0402_16V4Z~D S 3 1 CU26 0.1U_0402_16V4Z~D +3VS +3VS internal pull down 2 10K_0402_5%~D 2 4.7K_0402_5%~D OC_S0 OC_S1 3 4 FUNCTION1 FUNCTION2 RU29 1 2 3.4K_0402_1%~D OC_S2 6 ANALOG1(REXT) +3VS C VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V @ RU21 1 RU25 1 <18> SDVO_SDATA EC_DVI_DET 7 1 2.2K_0402_5%~D SDVO_SDATA 8 1 2.2K_0402_5%~D SDVO_SCLK 9 RU34 2 RU36 2 <18> SDVO_SCLK @ RU37 1 +3VS 2 4.7K_0402_5%~D Reserve RU37 4.7K pull high for ASM1442 2 OUT_D4+ OUT_D4- 16 17 OUT_D3+ OUT_D3- 19 20 OUT_D2+ OUT_D2- 22 23 OUT_D1+ OUT_D1- @1 CU60 HDMI_TX12 0.5P_0402_50V8 @1 CU61 HDMI_CLK2 0.5P_0402_50V8 @1 CU62 HDMI_TX02 0.5P_0402_50V8 1 5 12 18 24 27 31 36 37 43 OE# @ RU19 1 SCL_SINK 28 HDMI_SCLK RU20 2 1 2.2K_0402_5%~D SDA_SINK 29 HDMI_SDATA RU22 2 1 2.2K_0402_5%~D HPD_SINK 30 HDMI_HPD DDC_EN 32 FUNCTION3 FUNCTION4 34 35 EQ_S0 EQ_S1 GND GND GND GND GND GND GND GND GND GND D JHDMI1 HDMI_HPD +5VS_HDMI HDMI_R_CKHDMI_R_CK+ HDMI_R_D0- +5VS HDMI_R_D0+ HDMI_R_D1HDMI_R_D1+ HDMI_R_D2- 2 0_0402_5%~D @ RU28 RU30 @ RU32 RU33 1 1 1 1 2 2 2 2 +3VS HDMI_R_D2+ 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D 10K_0402_5%~D +3VS <18> PCH_DPB_HPD 2 10K_0402_5%~D C 48 47 IN_D4+ RU107 1 IN_D4- RU108 1 2 0_0402_5%~D 2 0_0402_5%~D PCH_TMDS_D2 <18> PCH_TMDS_D2# <18> IN_D3+ IN_D3- 45 44 IN_D3+ RU109 1 IN_D3- RU110 1 2 0_0402_5%~D 2 0_0402_5%~D PCH_TMDS_D1 <18> PCH_TMDS_D1# <18> IN_D2+ IN_D2- 42 41 IN_D2+ RU111 1 IN_D2- RU112 1 2 0_0402_5%~D 2 0_0402_5%~D PCH_TMDS_CK <18> PCH_TMDS_CK# <18> IN_D1+ IN_D1- 39 38 IN_D1+ RU113 1 IN_D1- RU114 1 2 0_0402_5%~D 2 0_0402_5%~D PCH_TMDS_D0 <18> PCH_TMDS_D0# <18> THERMAL_GND 49 IN_D4+ IN_D4- HDMI_CLK- @ RU24 1 1 1 MURATA DLW 21SN900HQ2L 4 4 LU2 HDMI_CLK+ HDMI_TX0- 2 2 3 3 HDMI_R_CK- @ RU31 1 2 0_0402_5%~D HDMI_R_CK+ @ RU35 1 2 0_0402_5%~D HDMI_R_D0- 1 MURATA DLW 21SN900HQ2L 4 Change U63 to SA00003GT00 1 2 2 3 3 B 2 10K_0402_5%~D 4 HDMI_TX0+ @ RU38 1 2 0_0402_5%~D HDMI_R_D0+ HDMI_TX1- @ RU40 1 2 0_0402_5%~D HDMI_R_D1- 0_0402_5%~D @ RU49 1 2 0_0402_5%~D ASM1442_QFN48_7X7 EC_DVI_DET 2 20 21 22 23 Unpop RU28,RU32 Pop RU30,RU33 LU3 @ RU47 1 RU48 1 HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield CK+ D0D0_shield D0+ D1D1_shield D1+ GND D2GND D2_shield GND D2+ GND FOX_QJ5119L-NVBT-7F CONN@ B +3VS 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HDMI_SDATA HDMI_SCLK 2 0_0402_5%~D RU27 1 SCL_SOURCE 13 14 HDMI_TX22 0.5P_0402_50V8 25 SDA_SOURCE ANALOG2 @1 CU59 OE* HPD_SOURCE OC_S3 10 HDMI_TX2+ @ 1 2 RU103 68_0402_5%~D HDMI_TX1+ @ 1 2 RU104 68_0402_5%~D HDMI_CLK+ @ 1 2 RU105 68_0402_5%~D HDMI_TX0+ @ 1 2 RU106 68_0402_5%~D CU50 1U_0402_6.3V6K~D 1 2 RU18 100K_0402_5%~D U63 2 11 15 21 26 33 40 46 Add RU25 4.7K pull down for ASM1442 Change RU29 to 3.4K for ASM1442 @ FU1 1.5A_6V_1206L150PR~D HDMI_HPD 2 G 2N7002LT1G_SOT23-3 D 2 1 1 CU21 2 1 1 CU20 2 1 +5VS RU17 10K_0402_5%~D 0.1U_0402_16V4Z~D 2 CU19 0.1U_0402_16V4Z~D 1 0.1U_0402_16V4Z~D 1 1 MURATA DLW 21SN900HQ2L 4 4 LU4 2 2 3 3 HDMI_TX1+ @ RU44 1 2 0_0402_5%~D HDMI_R_D1+ HDMI_TX2- @ RU45 1 2 0_0402_5%~D HDMI_R_D2- 1 1 MURATA DLW 21SN900HQ2L 4 4 LU5 HDMI_TX2+ @ RU46 1 2 2 3 3 2 0_0402_5%~D HDMI_R_D2+ A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Issued Date Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title HDMI Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 36 of 49 5 4 3 2 1 D D <18> DISP_A0N_VGA <18> DISP_A0P_VGA C561 2 C562 2 1 1 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D DISP_A0N DISP_A0P <18> DISP_A1N_VGA <18> DISP_A1P_VGA C563 2 C564 2 1 1 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D DISP_A1N DISP_A1P <18> DISP_A2N_VGA <18> DISP_A2P_VGA C566 2 C568 2 1 1 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D DISP_A2N DISP_A2P <18> DISP_A3N_VGA <18> DISP_A3P_VGA C569 2 C570 2 Place close JDP1 @ D38 DISP_A3N DISP_A3P 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 1 1 DISP_A0P 1 10 DISP_A0P DISP_A0N 2 9 DISP_A0N DISP_A1P 4 7 DISP_A1P DISP_A1N 5 6 DISP_A1N Co-lay +3VS_DP F2 +3VS DISP_A2P 1 10 DISP_A2P DISP_A2N 2 9 DISP_A2N DISP_A3P 4 7 DISP_A3P DISP_A3N 5 6 DISP_A3N DISP_HD @ RU115 110K_0402_1%~D DISP_A1N DISP_A2P 8 DISP_A2N DISP_A3P DP_DDC_DATA 4 Y U66 NC7SZ04P5X_NL_SC70-5~D 1 1 2 1 3 @ RU116 0_0402_5%~D 1 2 DP_HPD 2 2 1 @ QU5 BSS138_SOT23~D GND LANE1_N LANE2_P GND LANE2_N LANE3_P GND LANE3_N CONFIG1 CONFIG2 AUXCH_P GND AUXCH_N HPD RETURN DP_PWR B FOX_3V102P1-RB2BT-8F CONN@ DISP_HD 5 1 RU56 1 2 DP_CA_DET# NC RU55 2 1 DP_DDC_CLK 2.2K_0402_5%~D <18> S LANE1_P P +3VS 2 +3VS CU37 0.1U_0402_10V7K~D 2 1 SN74CBTD3306CPWR_TSSOP8~D 2 GND LANE0_N A 2 DP_CA_DET G 1A VCC 2A 1B 1OE# 2B 2OE# GND <18> @ QU6 BSS138_SOT23~D LANE0_P 3 <18> DP_DDC_CLK <18> DP_DDC_DATA 1 CU36 0.1U_0402_10V7K~D 1 2 8 3 6 4 3 +5VS 2 5 1 7 S 2 G 1 2 0.1U_0402_10V6K~D DISP_HD D 1 22U_0805_6.3V6M~D SN74CBTD3306CPWR_TSSOP8~D C572 DP_AUX_SW DP_AUX#_SW U65 DP_DDC_CLK DP_DDC_DATA DP_HPD 21 22 23 24 D 2 G 1M_0402_5%~D 8 3 6 4 C573 +3VS 1DP_AUX#_C CU35 0.1U_0402_10V7K~D RU97 100K_0402_5%~D 1 2 1A VCC 2A 1B 1OE# 2B 2OE# GND 5.1M_0402_5% 2 <18> DP_AUX# 2 5 1 7 R943 <18> DP_AUX @ RU99 10K_0402_5%~D @ RU98 100K_0402_5%~D CU34 0.1U_0402_10V7K~D 2 1 +5VS U70 +3VS R416 100K_0402_5%~D 2 DP_AUX#_SW DISP_HD 1 DPB_CA_DET= 1 TMDS Signaling DPB_CA_DET= 0 DP Signaling SW for MB side CU33 0.1U_0402_10V7K~D 2 1DP_AUX_C DISP_A3N DP_CA_DET DISP_CEC DP_AUX_SW Reserve near connector C JDP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DISP_A0N DISP_A1P +3VS RU96 1 2 RCLAMP0524P.TCT~D Follow Intel HPD design rev 1.6 B 2 1 DISP_A0P 3 2 2 QU4 BSS138_SOT23~D 1 2 1 D 1 3 S RU100 100K_0402_5%~D 1 0_1206_5%~D C953 0.1U_0402_16V4Z~D Vgs <=1.5 V G DP_HPD @ @ D39 C <18> 1 1.5A_6V_1206L150PR~D R409 2 RCLAMP0524P.TCT~D +5VS +3VS_DP 2 C952 10U_0805_10V4Z~D 8 1 GROUND 3 2.2K_0402_5%~D A A 1225 modify it. Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Display Port Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 37 of 49 5 4 3 2 V ersion Change L ist ( P. I. R . L ist ) Item Page# D Title D ate R equest O w ner 01 08 PROCESSOR (4/6) PWR,Bypass 2009/07/22 Compal 02 16 PCH (2/9) PCIE, SMBUS, CLK 2009/08/10 Compal 03 06 +1.5V and resert 2009/08/10 Compal 04 09 Separate +1.5V power 2009/08/10 Compal 05 11 VrefDQ 2009/08/10 Compal 06 12 VrefDQ 2009/08/10 Compal 1 Page 1 Issue D escription Solution D escription R ev. R343 un-pop,R1072 pop,R1074 pop,R1073 unpop,R1075 pop,R1076 un-pop Rev02 (X01) Pop C1027 with a 0 ohm resister Rev02 (X01) Reduce S3 state Power Add U63,Q36,R290,R310,R1103,R1136,C1142 Rev02 (X01) Reduce S3 state Power Add PJP12,PJP13,PJP14,C1033,C1143,C1144,C1145 Rev02 (X01) VrefDQ should be Maintained within SPEC during S3 Add Q37,R313 Rev02 (X01) VrefDQ should be Maintained within SPEC during S3 Add Q44,R321 Rev02 (X01) Design change for IMVP6.5 current gain XTAL25_IN should be pulled to GND using a 0Ω resistor. C C 07 20 DDR_RST_GATE 2009/08/10 Compal 08 33 VDDQ 2009/08/10 Compal 09 15 GPIO1D 2009/08/18 10 26 11 12 B D 13 Sub woofer / Speaker AMP 24,31 6 PROCESSOR (2/6) CLK,JTAG 11,12 DDR_RST_GATE from GPIO46 Add GPIO46 Rev02 (X01) Processor VDDQ should be turned off in S3 Add Q73,Q11,R346,R349,R1158,C534,C536 Rev02 (X01) Compal ADD EC GPIO1D to PCH GPIO33 Add GPIO33 Rev02 (X01) 2009/08/25 Compal Reserve Subwoofer delay circuit for mute Reserve D60, R1568, C1558 Rev02 (X01) 2009/08/25 Compal Follow crystal vendor's recommend 2009/08/25 Compal 2009/08/25 C318,C319,C479,C481 BOM change to SE071330J8L (S CER CAP 33P 50V +-5% NPO 0402) Rev02 (X01) Intel S3 solution disable POP R1054,R1055,R1121; Depop Q36,R290,R1103 Rev02 (X01) Compal Intel S3 solution disable Depop Q37,Q44,R56 Rev02 (X01) 14 33 DC/DC Interface 2009/08/25 Compal Intel S3 solution disable Depop Q73 Q73 BOM change to SB000001Y8L R358 BOM change to SD013470080 (S RES 1/10W 470 +-5% 0603) Rev02 (X01) 15 35 VGA / LVDS 2009/08/25 Compal to improve +LCDVDD voltage quality. Pop C550 Rev02 (X01) 16 31 EC_KB926/BIOS/Reed SW 2009/08/25 Compal Board ID change R312 BOM change to 8.2K Rev02 (X01) 17 31 EC_KB926/BIOS/Reed SW 2009/08/25 Compal Reserve a 0ohm resister on SUS_PWR_ACK from PCH to EC Reserve R1569 on SUS_PWR_ACK Rev02 (X01) 18 35 2009/09/01 Compal In common with MV Q71 BOM change to SB00000960L Rev02 (X01) 19 20 2009/09/21 Compal S3 POWER Reduction update from Intel Reserve C1559 on DDR_RST_GATE Rev03 (X02) 20 30 2009/09/21 Compal Reserve common choke on USB0 Reserve L89,R1571,R1572 Rev03 (X02) A B A 2009/09/21 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title HW PIR Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 38 of 49 5 4 3 2 V ersion Change L ist ( P. I. R . L ist ) Item Page# 01 30 02 Title D ate R equest O w ner 1 Page 1 Issue D escription Solution D escription R ev. Unpop R1164,R1165,R1166,R1167,R949,R950,R951,R952 pop JP13,C941,C944,C942,C943 Rev03 (X02) Q55,Q73 BOM change to SB00000DA0L Rev03 (X02) C1009,C1010 BOM change to SGA00002U1L Rev03 (X02) BOM change for C336,C337,C354,C355 Rev03 (X02) implement Subwoofer delay circuit for mute Pop D60,C1558 R1568 change to 330K Rev03 (X02) Compal Follow Intel HPD design remove RU98,RU99;add RU115; change QU4 to SB50138008L Rev03 (X02) 2009/09/21 Compal Follow Intel design Add LU9,CU64,CU65,CU66 Rev03 (X02) DDRIII SO-DIMM 2009/10/08 Compal Add M3 solution Pop R166,R178 Rev03 (X02) ESATA 2009/09/21 Compal 33 2009/09/21 Compal 03 8 2009/09/21 Compal 04 25 HD Audio_IDT92HD73C 2009/09/21 Compal 05 26 Sub woofer/Speaker AMP 2009/09/21 Compal 06 37 Display Port 2009/09/21 07 22 PCH (8/9) PWR Add ESATA re-driver D D 08 11,12 BOM reason 09 31 EC 2009/10/12 Compal For ENE issue Add R322 47K ohm pull high Rev03 (X02) 10 17 PCH 2009/10/15 Compal Bom reason Change U2 SA007080B90 to SA007080100 Rev03 (X02) 11 19 PCH 2009/10/16 Compal Design follow NAT01 Change R1139 SD02810038L to SE000000K8L Rev03 (X02) 12 31 EC 2009/10/22 Compal Change Board ID Change R312 SD02882018L to SD02818028L Rev03 (X02) 13 32 Touch Screen 2009/11/02 Compal Add for Touch Screen issue Add R1236 Rev03 (X02) 14 36 HDMI 2009/11/24 Compal For HDMI Deep color mode Unpop RU28,RU32 , Pop RU30,RU33 Rev10 (A00) 15 30 Camera 2009/11/02 Compal improve 888MHZ noise Add C458,C459 Rev10 (A00) 16 27 WLAN 2009/11/05 Compal for EC debug pin Add R323 100K pull down Rev10 (A00) 17 9 PWR 2009/11/05 Compal Intel suggest to reduce GFX voltage overshoot Change RU93 to 470ohm Rev10 (A00) 18 26 Sub woofer/Speaker Amp 2009/11/16 Compal Follow NAT01 design Change C922 & C1102 to 0.1uF Rev10 (A00) 19 31 EC 2009/11/19 Compal Change Board ID Change R312 SD02818028L to SD02833028L Rev10 (A00) 20 36 HDMI 2009/11/24 Compal Change HDMI level shift Change U63 to SA00003GT00 Rev10 (A00) 21 36 HDMI 2009/11/24 Compal For HDMI Deep color mode Add RU25 4.7K pull down for ASM1442 Rev10 (A00) 22 36 HDMI 2009/11/24 Compal For HDMI Deep color mode Reserve RU37 4.7K pull high for ASM1442 Rev10 (A00) 23 36 HDMI 2009/11/24 Compal For HDMI Level shift ASM1442 Change RU29 to 3.4K for ASM1442 Rev10 (A00) C C B B 24 25 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title HW PIR Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 39 of 49 4 3 2 1 +5VALW ADPIN 2 3 1 PS_ID <31> PQ2 FDV301N_NL_SOT23-3~D +5VALW 2 3 @ PD5 @PD5 SM24_SOT23 @ 1 PQ3 MMST3904-7-F_SOT323~D E PD6 DA204U_SOT323~D C PR19 10K_0402_1%~D 1 1 +5VALW 2 B D 2 2 G PR20 PR18 15K_0402_1%~D 100K_0402_1%~D 1 2 1 2 3 2 1 S 3 D 1 PR17 33_0402_5%~D 1 2 PR16 2.2K_0402_5%~D 1 2 DOCK_PSID PL2 BLM18BD102SN1D_0603~D 2 1 DOCK_PSID PSID PD4 DA204U_SOT323~D @ PR15 1 2 0_0402_5%~D PC7 1000P_0402_50V7K~D 2 1 PC6 100P_0402_50V8J~D 2 1 1000P_0402_50V7K~D 1 PC5 2 1 2 PC4 100P_0402_50V8J~D 1000P_0402_50V7K~D 1 PC3 2 1 PC2 100P_0402_50V8J~D 2 D VIN PL1 FBMA-L18-453215-900LMA90T_1812~D 1 2 7 7 6 6 5 5 4 4 3 3 2 2 1 1 MOLEX_87438-0743 @PJPDC1 @ PJPDC1 +3VALW 3 5 @ PR21 1 2 10K_0402_1%~D C C @ VIN 2 PC193 2200P_0402_50V7K~D PD2 2 P 4 - 1 MAX1615_IN Max. 18.234 17.597 1 typ. 17.841 17.210 MAX1615_#SHDN1 2 PR14 0_0402_5%~D MAX1615EUK+_SOT23-5~D 1 PC14 1U_0805_25V4Z~D A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 Min. 17.449 16.813 1 5 2 #SHDN 5/3+ 2 4 IN 2 Vin Detector OUT GND 4.7U_0805_6.3V6K~D 3 PC13 1 LM393DR_SO8 L-->H H-->L PU3 2 7 2 RTCVREF A @ PU17B O RTCVREF 3.3V 8 1 6 PR13 200_0805_5% + B G 5 <17,25,31,41> @ PR203 @PR203 10K_0402_5%~D @ PD1 RLZ4.3B_LL34 @ PR201 10K_0402_5%~D 1 ACIN 2 @ PC191 1000P_0402_50V7K~D @ PR192 1K_0402_5%~D 2 VinDe_Out @ PU17A LM393DR_SO8 2 @ 32.3 1 O - @ PR205 10K_0402_5%~D 1 1 PC192 2 1 8 + 1 2 1 PR206 19.6K_0402_1%~D 2 1 @ VinDe_Ref 2 @ 0.01U_0402_25V7K~D VIN P 2 1 2 @ PR193 22K_0402_1%~D VinDe_IN3 3 1 2 N41 PC12 0.1U_0603_25V7K~D 2 1 PC11 0.22U_0603_25V7K~D 2 51ON# @PR191 @PR191 82.5K_0402_1%~D PC194 .1U_0402_16V7K~D <32> 2 1 2 PR12 22K_0402_5%~D 1 2 VS 27.4 PR11 100K_0402_5%~D B VIN VS G 3 2 4 2 CHGRTCP PQ1 TP0610K-T1-E3_SOT23-3 1 PR208 68_1206_5%~D 1 @ PR202 1M_0402_1%~D 1 2 1 PR10 68_1206_5%~D RLS4148_LL34-2 2 1 1 1 RLS4148_LL34-2 2 2 BATT+ 1 1 PJP1 @ JUMP_43X118 1 1 2 2 PD3 @ PR204 56K_0402_5%~D 4 3 2 Title DCIN/Precharger Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 40 of 49 A B C PR90 4.7_1206_5%~D 2 1 D E PVCC_CHG B+ VIN 4 LODRV 23 PGND 22 LEARN 21 DL_CHG 3 2 1 2 7 ACOP PC34 0.47U_0603_16V7K~D +3VALW 2 9 PR35 54.9K_0402_1% AGND ACOFF 20 SRP 19 SRP SRN 18 SRN 1 2 PQ7 FDS6675BZ_SO8 4 3 2 1 G S S S D D D D 1 2 1000P_0402_50V7K~D PC18 2 1 1000P_0402_50V7K~D PC17 1 1 1 2 4.7U_0805_25V6K~D PC22 2 1 2 1 PC15 1 2 2 <31> PC37 0.1U_0603_25V7K~D PC38 0.1U_0603_25V7K~D 1 CELLS 3 PC36 .1U_0402_16V7K~D 1 2 PR88 0_0402_5%~D CELLS 1 2 VREF 2 1 2 OVPSET 2 8 4 PC32 10U_1206_25V6M~D 1 1 BATT+ 1 2 5 6 7 8 PQ8 FDS6690AS_NL_SO8 PC29 1U_0603_10V6K~D 2 PR33 100K_0402_1%~D PR29 0.02_2512_1% PL3 10U_919AS-100M-P3_4.5A_20% 1 2 2 RLS4148_LL34-2 PC28 0.1U_0603_25V7K~D 24 REGN 1 1 2 PC190 0.1U_0402_10V7K~D 2 1 @ 2 1 PR30 60.4K_0402_1% @ PC33 0.01U_0402_25V7K~D 2 1 SSM3K7002FU_SC70-3 1 1 3 PQ25 S 2 G ACSET 1 2 LX_CHG PD7 2 1 ACDRV ACDET 2 2 2 1 D 6 5 6 7 8 DH_CHG 5 6 7 8 PH 25 PC31 10U_1206_25V6M~D 26 2 HIDRV 1 /BATDRV ACN ACP 1 4 5 PR24 100K_0402_1%~D PC30 10U_1206_25V6M~D 2 3 4 3 2 1 ACN ACP ACDRV_CHG# 27 BTST 4.7U_0805_25V6K~D PC21 PC27 0.1U_0603_25V7K~D PQ6 FDS8884_SO8 PR25 2.2_0603_5%~D 1 2 4.7U_0805_25V6K~D PC23 CHG_B+ 1 PC188 1 0.1U_0603_25V7K~D 2 1 28 PVCC 1 CHGEN PR89 143K_0402_1%~D CP_SEL 2 2 JUMP_43X118 PC20 0.022U_0603_50V7~D 1 2 PU4 1 ACSET PR31 54.9K_0402_1% 1 2 @ 2 1 1000P_0603_50V7~D 2 1 CP setting OVPSET 3 REGN ACDET PR34 340K_0402_1%~D 4 2 PC26 0.1U_0603_25V7K~D PR37 1K_0603_5%~D 2 1 CP_SEL PJP17 1 PC24 .1U_0402_16V7K~D 1 2 2 @PC100 @ PC100 0.01U_0402_25V7K~D 8 7 6 5 CHGEN# 2 1 PR26 100K_0402_1%~D PC25 0.022U_0603_50V7~D 1 2 2 1 2 2 PR28 340K_0402_1%~D PC19 2.2U_0805_25V6K 1 D D D D SI4459ADY_SO8 PC16 0.01U_0603_50V7K~D <31> S S S G PC35 PR32 680P_0603_50V7K~D 4.7_1206_5%~D 2 1 2 1 1 2 3 4 PR22 0.015_2512_1% PC189 1 2 3 4 S S S G 2 1 1 PR23 3.3_1210_5%~D 1 2 D D D D FDS6675BZ_SO8 PR27 3.3_1210_5%~D 1 8 7 6 5 PQ5 2200P_0402_50V7K~D 2 1 PQ4 1 17 BAT VADJ 12 VADJ 13 /BATDRV 14 SRSET BATDRV RTCVREF PR38 2 1 51.1K_0402_1%~D SRSET 16 IREF <31> 2 ACIN 1 <31> ACGOOD# 1 ADP_I 2 2 PC43 100P_0402_50V8J~D 3.3A S 1 2 +COINCELL +RTCVCC 1 Z4012 3 2 PQ14 SSM3K7002FU_SC70-3 PR51 47K_0402_1%~D @ PJPRTC 1 1 2 2 3 G1 4 G2 CHGEN# MOLEX_53398-0271_2P <31> PR53 340K_0402_1%~D PD9 BAT54CW_SOT323~D 1 1 1 2 1 3 PQ13 SSM3K7002FU_SC70-3 D 3 1 1 3 2 S VREF S PQ16 SSM3K7002FU_SC70-3 2 G FSTCHG 1 PQ15 SSM3K7002FU_SC70-3 D 2 G COIN RTC Battery PR47 1K_0402_5%~D RTCVREF 2 1 3 S S 2 G 2 PC45 .1U_0402_16V7K~D D 2 1 0.1U_0805_25V7M~N 2 1 PR48 1 1 2 D GATE PR49 200K_0402_1%~D PR50 100K_0402_1%~D ACOFF 1 2 G 220K_0402_5% 2 PR54 220K_0402_5% PC44 1SS355TE-17_SOD323-2 1 2 PR52 1 PC47 0.1U_0603_25V7K~D 2 1 4 Current 3.3V 3 PQ11 SSM3K7002FU_SC70-3 VREF B+_BIAS VREF 32.8 2 2 100_0805_5%~D +5VALW PQ12 TP0610K-T1-E3_SOT23-3 1 3 470K_0402_5%~D 2 PD8 IREF <17,25,31,40> D 2 G +COINCELL PR46 1 PR42 47K_0402_1%~D VADJ PR45 499K_0402_1%~D B+ PR41 47K_0402_1%~D @ PC42 0.01U_0402_25V7K~D 1 PR40 100K_0402_1%~D 2 PR39 10_0603_5%~D 2 PR44 210K_0402_1%~D 1 2 1 VREF 3 CHGVADJ BQ24751ARHDR_QFN28_5X5 1 <31> 2 3 15 IADAPT PR43 @ 0_0402_5%~D 2 1 1 REGN ICHG setting ACGOOD 1 ACGOOD# PC41 0.1U_0603_25V7K~D 29 TP 2 1 1 2 ACSET Fsw : 300KHz VDAC 1 2 Input UVP : 16.98V 2 PR87 0_0402_5%~D 11 1 +3VALW PC40 0.1U_0603_25V7K~D Input OVP : 22.3V PR86 @ 0_0402_5%~D 2 1 Iadapter=(Vacset/Vvdac)*(0.1/PR22)=4.16A VREF 1 Icharge=(Vsrset/Vvdac)*(0.1/PR29)=3.3A PC39 1U_0603_10V6K~D 2 PR36 100K_0402_1%~D 1 2 GATE 2 90W adapter 3 10 PQ9 SI2301BDS-T1-E3_SOT23-3 4 PC46 1U_0603_10V4Z~D 2 2009/09/21 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Charger Size B Date: Document Number Rev 1.0 NAT02 M/B LA-5154P Schematic Thursday, November 26, 2009 Sheet E 41 of 49 5 4 3 2 1 TPS51427_B+ TPS51427_B+ B+ PR55 0_0805_5% 1 2 PL23 16 LGATE1 18 DL5 4 G 25 1 2 3 3 2 1 PHASE2 S S S LX3 DL3 23 FB3 LGATE2 30 OUT2 VL 32 REFIN2 2VREF_TPS51427 1 2 1 PGND 22 OUT1 10 FB1 11 BYP 9 SKIP 29 PC197 0.1U_0603_25V7K~D 2 1 PC53 2200P_0402_50V7K~D 2 1 PC52 4.7U_0805_25V6K~D 1 2 FB5 1 + 2 PC63 330U_D_6.3VM_R18M~D PHASE1 2.2_0603_5%~D PC61 0.1U_0603_25V7K~D LX5 PC80 0.1U_0402_10V7K~D 2 1 2 2 2.2_0603_5%~D PC57 0.1U_0603_25V7K~D S S S PR60 PR61 61.9K_0402_1%~D 1 2 BST5A 1 PR63 10K_0402_1%~D 1 2 17 2 1 2 1 PR58 PC62 4.7_1206_5%~D 680P_0603_50V7K~D BOOT1 PQ20 FDS6670AS_NL_SO8 BOOT2 PQ18 SI4686DY-T1-E3_SO8 3 2 1 DH5 24 5 6 7 8 15 BST3A D D D D 19 UGATE1 @ 1 4.7U_0805_6.3V6K~D PC56 2 1 7 3 VCC VIN PVCC UGATE2 1 2 4 1 G 2 LDO PC55 1 2 2 1 TP 26 +5VALWP PL5 2 1 2.2UH_MPLC1040L2R2_11A_20%~D PC59 1U_0603_10V6K~D 1 2 33 PR59 1 6 1 2 3 PQ19 FDS6670AS_NL_SO8 4 DH3 8 7 6 5 D D D D PC58 PR56 680P_0603_50V7K~D 4.7_1206_5%~D 2 1 2 1 2 2 PR57 0_0402_5%~D 2 C 1 + PR62 10K_0402_1%~D PC60 330U_D_6.3VM_R18M~D PC79 0.1U_0402_10V7K~D 2 1 1 PU5 1U_0603_10V6K~D 8 7 6 5 PC54 0.1U_0603_25V7K~D 4 PL4 1 2 2.2UH_MPLC1040L2R2_11A_20%~D +3VALWP 5 6 7 8 VL PQ17 SI4686DY-T1-E3_SO8 PC51 4.7U_0805_25V6K~D 1 2 D PC50 2200P_0402_50V7K~D 2 1 PC84 0.1U_0603_25V7K~D 2 1 FBMA-L18-453215-900LMA90T_1812 PC49 4.7U_0805_25V6K~D 1 2 D 2 PC48 4.7U_0805_25V6K~D 1 2 1 C REF PC64 0.22U_0603_10V7K~D 8 PJP5 @ JUMP_43X118 1 1 2 2 5 +5VALW 2 1 2 POK1 13 EN1 ILIM1 12 ILM1 ILIM2 31 ILIM2 21 2 0_0402_5%~D 1 VL 0_0402_5%~D 2 PR68 210K_0402_1%~D 2 1 ISL6237IRZ-T_QFN32_5X5 2 B 1 PR69 255K_0402_1%~D 5VALWP Thermai Design Current=6.88A OCP min=9A Fsw=400K @ 2VREF_TPS51427 2 1 5 2 PR71 0_0402_5%~D GND EN_LDO TON 28 NC POK2 PC66 1U_0603_10V6K~D 2 1 PC68 0.047U_0402_16V7K~N 2 1 1 @ PD17 1SS355TE-17_SOD323-2 PC67 0.047U_0603_16V7K~D 1 @ PR74 47K_0402_5%~D 1 2 2 3 PQ21 TP0610K-T1-E3_SOT23-3 @ PR75 0_0402_5%~D Rds(on) = 11.5m ohm(max) ; Rds(on) = 9m ohm(typical) PD11 1SS355TE-17_SOD323-2 A 3.3VALWP Thermal Design Current=8.5A OCP min=11A Fsw=300K PJP11 @ JUMP_43X118 1 1 2 2 PJP9 @ JUMP_43X118 1 1 2 2 1 14 2 1 806K_0603_1% @ PR70 0_0402_5%~D 2VREF_TPS51427 1 2 1 2 PR72 3 PAD-OPEN 2x2m~D PJP7 @ JUMP_43X118 1 1 2 2 +3VALW P 1 0_0402_5%~D 1 4 NC TPS51427_EN2 27 EN2 VL @ PJP24 VS +5VALW P <20,47> PR73 MAINPW ON 2 @ PQ10 DTC115EUA_SC70-3 2 A EN_LDO PC65 TPS51427_EN1 0.22U_0603_25V7K~D 1 @ 2 1 2 12 @ PR93 100K_0402_5%~D 1 2 2 20 PR66 100K_0402_1%~D 1 2 PR67 200K_0402_5%~D 1 2 1 @ VS PD10 RLZ5.1B_LL34 1 2 PR92 100K_0402_5%~D 3 PR91 100K_0402_5%~D 2 1 B+ @ PR64 2 PR65 1 @ PQ24 TP0610K-T1-E3_SOT23-3 B LDOREFIN +3VALW Rds(on) = 11.5m ohm(max) Rds(on) = 9m ohm(typical) 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Issued Date Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Title +3VALWP/+5VALWP Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 42 of 49 A B C D @ PJP20 VCCP_B++ 1 PC86 2200P_0402_50V7K~D 2 1 PC85 0.1U_0603_25V7K~D 2 1 1 2 PC70 10U_1206_25V6M~D 2 1 +1.05VSP Thermal Desig Current=5A OCP min=9A Fsw=300KHz PC69 10U_1206_25V6M~D 2 1 B+ PAD-OPEN 4x4m 1 5 6 7 8 PR76 267K_0402_1%~D 1 2 PR77 0_0402_5%~D 2 1 PR78 1 2.2_0603_5%~D PC71 0.1U_0603_25V7K~D 9 4 1 2 2 @ PC78 47P_0402_50V8J~D 2 1 S S S G PC77 4.7U_0805_10V6K~D + 2 PC75 680P_0603_50V7K~D 2 3 2 1 TPS51117RGYR_QFN14_3.5x3.5 1 PGND 8 7 GND 1 PC76 1U_0603_10V6K~D 2 DRVL 1 PC81 0.1U_0402_10V7K~D 2 1 PR82 0_0603_5%~D PC74 4.7U_0805_6.3V6K~D 2 1 TRIP_VCCPPR81 1 2 V5DRV_VCCP 10K_0402_1%~D PC73 220U_D2_4VM TP 3 2 1 10 PR83 4.7_1206_5%~D 2 1 PGOOD 11 +1.05VSP 1 6 TRIP V5DRV 2 VFB PQ23 FDS6670AS_NL_SO8 V5FILT 5 12 PL6 2.2UH_MPLC1040L2R2_11A_20%~D 1 2 5 6 7 8 4 FB_VCCP LL LX_VCCP D D D D V5FILT_VCCP UG_VCCP 1 VOUT 13 DRVH 2 3 14 15 1 TON +5VALW VBST 2 EN_PSV PU6 PR80 300_0603_5%~D 1 2 2 PQ22 SI4686DY-T1-E3_SO8 2 4 TON_VCCP +5VALW 2 2 @ PC72 .1U_0402_16V7K~D 2 PR79 30.1K_0402_1%~D BST_VCCP1 1 EN_VCCP 1 <28,31,33,44,45> SUSP# 1 PR84 8.66K_0402_1%~D @ PJP23 JUMP_43X118 2 ADJ 7 PGOOD 1 +1.8VSP EN 4 VDD GND PC87 1000P_0402_50V7K~D 1 2 2 +1.8VS GND 8 +5VALW 9 PR95 0_0402_5%~D 3 1 2 PR96 1K_0402_1%~D 2 1 1 PC88 10U_1206_25V6M~D PR97 806_0402_1%~D 2 1 SUSP# 1 @ PJP25 JUMP_43X118 1 2 2 @ PJP28 JUMP_43X118 1 2 2 6 2 <28,31,33,44,45> 2 1 RT9025 VOUT +1.05VS @ PC171 0.1U_0402_16V7K~D +1.8VSP VIN 2 3 PC126 10U_1206_25V6M~D 2 1 2 2 1 1 1 +3VALW PC172 10U_1206_25V6M~D +1.05VSP PU13 NC 1 1 3 @ PJP10 JUMP_43X118 1 1 2 2 5 2 PR85 21.5K_0402_1%~D PC170 1U_0402_6.3V6K~D +1.8VSP Thermal Desig Current=0.69A 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title +1.05VSP/+1.8VSP Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 D Sheet 43 of 49 A B C D PL24 6268_1.5VP_B+ 2 1.5VP Thermal Design Current=12.8A OCP min=16A Fsw=300KHz 1 PHASE_1.5VP UG_1.5VP PR220 10K_0402_1%~D PR221 1 2 2 2 2.2_0603_5%~D +5VALW 1 <6> 1.5V_PW RGD BOOT_1.5VP 1 PC215 0.1U_0603_25V7K~D VIN BOOT UG PHASE 5 15 16 1 PVCC PC216 1 2 14 4 2.2U_0603_6.3V6K~D 12 ISEN 11 PL15 1UH_FDUE1040D-1R0M-P3_21.3A_20% 1 2 5 +1.5VP 1 2 1 2 PC223 680P_0603_50V7K~D PR228 1 2 1 2 1 PC228 0.01U_0402_25V7K~D PR230 1.5K_0402_1%~D 2 1 + 2 1 1 2 2 2 PR229 45.3K_0402_1%~D + PC226 330U_Y_2.5VM 1 PC225 330U_Y_2.5VM 1 +1.5VP 33K_0402_1%~D PC227 2200P_0402_50V7K~D 1 2 68P_0402_50V8J~D PC224 PQ52 FDMS8670S_ POWER56-8~D 3 2 1 10 PU19 ISL6268CAZ-T_SSOP16 2 4 3 2 1 VO 4 PQ51 FDMS8670S_ POWER56-8~D FSET PR226 ISEN_1.5VP 1 2 3.01K_0402_1%~D 9 6 .1U_0402_16V7K~D FB COMP EN PC222 2 1 5 @ 7 PR225 0_0402_5%~D 1 2 <28,31,33> SYSON 5 2 PC218 2.2U_0603_6.3V6K~D PC221 0.1U_0402_10V7K~D 2 1 PGND LG_1.5VP PC220 10U_0805_6.3V6M~D 2 1 13 PC219 10U_0805_6.3V6M~D 2 1 LG VCC 1 4 PR227 4.7_1206_5%~D 6268_1.5VP 3 2 1 @ PC217 0.1U_0603_25V7K~D PQ50 FDMS8692_POW ER56-8-5~D PR224 4.7_0603_5%~D 1 2 6268_1.5VP 2 1 3 PGOOD GND 2 2 PR223 0_0603_5%~D 8 PR222 0_0603_5%~D 2 1 1 1 2 PC214 10U_1206_25V6M~D 1 6268_1.5VP 10U_1206_25V6M~D PC213 2 1 PC212 2200P_0402_50V7K~D 2 1 PC211 0.1U_0603_25V7K~D 2 1 FBMA-L18-453215-900LMA90T_1812 2 1 B+ 2 PR231 1K_0402_1%~D +1.5VP @ PJP22 JUMP_43X118 1 2 2 1 @ PJP35 JUMP_43X118 1 2 2 4 S5 9 S3 7 PR130 0_0402_5%~D 2 1 @ PR131 0_0402_5%~D 2 1 1 VTTSNS 8 6 2 5 GND VTTREF PC140 1U_0603_10V6K~D VTT +3VALW 1 3 10 2 VLDOIN GND PC143 0.1U_0402_16V7K~D +0.75VSP Thermal Design Current:0.7A Peak current:1A Vout=VDDQSNS/2=1.5V/2=0.75V 1 1 2 PC142 10U_0805_10V6K~D @ VDDQSNS VIN 2 2 1 PC141 10U_0805_10V6K~D 2 1 +0.75VSP 1 11 2 PGND 2 4 1 JUMP_43X118 PC138 2 1 1 PU10 RT9026_MSOP10 4.7U_0805_6.3V6K~D @ PJP18 +1.5VP PC139 2 1 3 4.7U_0805_6.3V6K~D 3 @ PC144 0.1U_0402_16V7K~D +1.5V 1.5VS_DDR_PW RGD SUSP# @ PJP21 +0.75VSP 2 1 Issued Date 4 <28,31,33,43,45> Compal Electronics, Inc. Compal Secret Data Security Classification +0.75VS PAD-OPEN 2x2m~D <33> 2009/09/21 Deciphered Date 2010/09/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title +1.5VSP/+0.75VSP Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 D Sheet 44 of 49 5 3 2 1 1.1VS_VTTP Thermal Design Current=18A OCP min=24A Fsw=300KHz 1 1 6268_1.1VS_VTTP PR234 0_0603_5%~D PR232 9.31K_0402_1%~D PHASE_1.1VS_VTTP 2 2 <6> H_VTTPWRGD D UG_1.1VS_VTTP 1 PC286 10U_1206_25V6M~D 1 2 PC232 10U_1206_25V6M~D 2 1 6268_1.1VS_VTTP_B+ PC231 10U_1206_25V6M~D 2 1 D PC230 2200P_0402_50V7K~D 2 1 PL22 FBMA-L18-453215-900LMA90T_1812 1 2 PC229 0.1U_0603_25V7K~D 2 1 B+ 4 PR233 1 PR327 2.7K_0402_1%~D 2 1 2 PC233 0.1U_0603_25V7K~D 1 2 2.2_0603_5%~D +5VALW BOOT_1.1VS_VTTP VIN BOOT UG PHASE PVCC 14 5 PQ53 FDMS8692_POWER56-8-5~D PR236 4.7_0603_5%~D 1 2 6268_1.1VS_VTTP PC234 1 2 4 2.2U_0603_6.3V6K~D PL16 1UH_FDUE1040D-1R0M-P3_21.3A_20% 1 2 PC239 0.1U_0402_10V7K~D 2 1 PC238 10U_0805_6.3V6M~D 2 1 1 PC237 10U_0805_6.3V6M~D 2 1 C PC241 680P_0603_50V7K~D 2 PR242 1.5K_0402_1%~D + 2 1 + 2 1 1 PC246 0.01U_0402_25V7K~D 1 PC244 330U_Y_2.5VM 4 +1.1VS_VTTP PC243 330U_Y_2.5VM PU20 ISL6268CAZ-T_SSOP16 PQ55 FDMS8670S_ POWER56-8~D 4 3 2 1 PR238 4.75K_0402_1%~D +1.1VS_VTTP PR305 10_0402_5%~D 5 5 ISEN_1.1VS_VTTP 1 2 PQ54 FDMS8670S_ POWER56-8~D 11 3 2 1 VO 10 12 1 2 9 PR241 45.3K_0402_1%~D 2 1 6 1 2 1 2 PC245 2200P_0402_50V7K~D PC242 68P_0402_50V8J~D 2 1 PR240 33K_0402_1%~D 2 FSET ISEN FB EN COMP 5 @ PC240 .1U_0402_16V7K~D 7 2 PR237 0_0402_5%~D 1 2 <28,31,33,43,44> SUSP# 1 C PGND 2 LG_1.1VS_VTTP 1 13 2 LG PR239 4.7_1206_5%~D VCC 1 4 PC236 2.2U_0603_6.3V6K~D 2 6268_1.1VS_VTTP 3 2 1 @ PC235 0.1U_0603_25V7K~D 1 2 1 3 PGOOD GND 2 15 16 1 2 8 PR235 0_0603_5%~D PR243 2K_0402_1%~D PR244 1 2 B 2 VTT_SENSE <8> 0_0402_5%~D B +3VS @ PR245 1 2 +1.1VS_VTT PR248 10K_0402_5%~D 2 2 1 1 3 1 2 D 3 PR250 10K_0402_5%~D 0.01U_0402_16V7K~D 1 2 PQ57 1 S PC247 0.068U_0402_16V7K~D PR249 1 <8> H_VTTVID1 D 2 PQ56 1 PJP33 @ JUMP_43X118 1 1 2 2 H_VTTVID1 <8> PR247 17.8K_0402_1%~D 1 Vo = 1.05V Vo = 1.1V 2 17.8K_0402_1%~D 1 H_VTTVID1 = "High" , H_VTTVID1 = "Low" , 2 PJP32 @ JUMP_43X118 1 2 1 2 PR246 10K_0402_5%~D 1 PJP31 @ JUMP_43X118 1 1 2 2 PC248 +1.1VS_VTTP S 2 10K_0402_5%~D 2 G SSM3K7002FU_SC70-3 PR251 100K_0402_5%~D 2 G SSM3K7002FU_SC70-3 A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title +1.1VS_VTTP Size Document Number Custom NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 45 of 49 Rev 1.0 8 7 6 5 4 3 2 1 +CPU_B+ 2 BOOT2_2 1 PC263 2 PR275 0_0402_5%~D 1 2 0_0402_5%~D 2 21 PC255 100U_25V_M~D 1 PR266 10K_0402_5%~D 2 2 1 PR263 3.65K_0603_1%~D 2 1 PC274 10U_1206_25V6K~D 2 1 2 1 PC273 10U_1206_25V6K~D PC272 2200P_0402_50V7K~D 2 1 PQ65 FDMS8692_POWER56-8-5~D PC271 0.1U_0603_25V7K~D 2 1 C 1 Layout Note: Place near Phase1 Choke G 2 2 1 PR297 1_0402_5%~D @ PR301 0_0402_5%~D 1 2 V2N VSUM- VSUM+ B ISEN1 VSUM- 2 1 @ PR304 100_0402_1%~D A 2009/09/21 Issued Date Deciphered Date 2010/09/21 Title +CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size C Date: 6 5 4 3 A Compal Electronics, Inc. Compal Secret Data Security Classification 7 +CPU_CORE V1N 1 1 3 2 PH5 10K_0603_1%_ERTJ1VG103FA~D 2 4 PR296 10K_0402_5%~D G 2 2 PR295 3.65K_0603_1%~D 2 1 2 LGATE1 PR294 4.7_1206_5%~D 3 1 PHASE1 D 2 4 PL19 0.36UH_ETQP4LR36ZFC_28A_20%~D 1 PR300 11K_0402_1%~D 2 1 1 2 1 @ PC284 1200P_0402_50V7K~D 4 PR291 PC275 2.2_0603_5%~D 0.22U_0603_10V7K~D 2 1 BOOT1_1 1 2 PR293 2.87K_0402_1%~D 2 1 PC278 0.022U_0603_25V7K~D 2 1 PC276 2700P_0402_50V7K~D 2 1 82.5_0402_1%~D PC277 0.33U_0603_10V7K~D PR299 0_0402_5%~D D PC285 .1U_0402_16V7K~D 10_0402_5%~D 2 PR298 1.15K_0402_1%~D 1 2 5 UGATE1 PC283 680P_0603_50V7K~D 2 1 VSSSENSE 3 2 1 PR288 12.1K_0402_1%~D S PC269 0.22U_0603_25V7K~D 1 2 1 2 2 PR303 1 PC282 330P_0402_50V7K~D VSSSENSE PC280 1 1 2 1 2 0_0402_5%~D 2 0.01U_0402_16V7K~D 1 PR290 2 2 0_0402_5%~D PC281 1000P_0402_50V7K~D 8 PC254 100U_25V_M~D PC253 100U_25V_M~D PC287 10U_1206_25V6K~D 2 1 PC252 10U_1206_25V6K~D 2 1 PC251 10U_1206_25V6K~D 2 1 5 PC250 2200P_0402_50V7K~D 2 1 PC249 0.1U_0603_25V7K~D 2 1 PR262 4.7_1206_5%~D 2 1 F +CPU_B+ 1 1_0402_5%~D 2 +5VS BOOT1 10_0402_5%~D PR302 1 <8> VSUM- IMVP_IMON PC270 0.033U_0603_16V7K~D PR287 1 PC268 1U_0603_10V6K~D 2 1 0_0402_5%~D PC279 330P_0402_50V7K~D B ISEN2 0_0402_5%~D 2 <8> 1 2 2 PR286 0_0402_5%~D 2 +CPU_B+ 1 1 1 PR283 2 0_0402_5%~D 2 2 PR289 1 <8> PR292 V1N VSUM+ +5VS VSUM+ 1 VCCSENSE PR264 1_0402_5%~D @ PR267 0_0402_5%~D 1 2 E 2 PR284 1 PR281 1 2 2 ISEN2 PR285 412K_0402_1%~D +CPU_CORE 2 ISL62883HRZ-T_QFN40_5X5~D 11 12 13 14 15 16 17 18 19 20 AGND PR277 1 PR282 3.4K_0402_1%~D 1 2 Layout Note: PH3 place near Phase1 L-MOS C 3 +CPU_CORE V2N 390P_0402_50V7K~D ISEN1 PC265 150P_0402_50V8J~D 41 30 29 28 27 26 25 24 23 22 21 BOOT2 UGATE2 PHASE2 VSSP2 LGATE2 VCCP PWM3 LGATE1 VSSP1 PHASE1 PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2 PC267 0.22U_0402_10V6K~D 1 2 1 1 2 PC261 1000P_0402_50V7K~D PR279 8.06K_0402_1%~D 2 1 @ PR278 249K_0402_1%~D 2 1 PR280 562_0402_1%~D 2 1 1 2 PC264 10P_0402_50V8J~D 2 1 PC260 22P_0402_50V8J~D 1 1 1 2 3 4 5 6 7 8 9 10 H_PROCHOT#_R PH4 470K_0402_5%_ERTJ0EV474J~D D 1 0_0402_5%~D 4.02K_0402_1%~D 2 2 1 1U_0603_10V6K~D PR274 56P_0402_50V8~D 2 PC266 0.22U_0402_10V6K~D PR276 1 2 PC258 1U_0603_10V6K~D 1 2 CLK_EN# DPRSLPVR VR_ON VID6 VID5 VID4 VID3 VID2 VID1 VID0 PU21 68_0402_5%~D 1 2 <6> H_PROCHOT# E 2 PR273 2 1 +1.1VS_VTT @ 2 H + 0_0402_5%~D 2 1 1 PC262 PR271 40 39 38 37 36 35 34 33 32 31 +1.1VS_VTT <8> H_PSI# PR272 1 2 147K_0402_1%~D @ PC259 1 G @ PR270 100K_0402_5%~D 1 2 ISEN1 VSEN RTN ISUMISUM+ VDD VIN IMON BOOT1 UGATE1 F 2 4 PC257 680P_0603_50V7K~D 2 1 G S 2 S LGATE2 D 3 D CLK_ENABLE# 1 VGATE 2 + B+ 1 G PR268 1.91K_0402_1%~D 2 <13,17,31> + 1 PL18 0.36UH_ETQP4LR36ZFC_28A_20%~D PHASE2 PR265 1.91K_0402_1%~D 1 2 PR269 0_0402_5%~D 1 2 1 Iccmax= TBD I_TDC=TDB OCP=68A, Intel spec=TDB UGATE2 <13> CLK_ENABLE# +3VS PQ64 FDMS8692_POWER56-8-5~D 2 PR261 499_0402_1%~D 1 4 3 2 1 BOOT2 PR260 0_0402_5%~D 1 PC256 0.22U_0603_10V7K~D 1 2 PQ63 FDMS8670S_ POWER56-8~D <8> H_DPRSLPVR PR259 2.2_0603_5%~D 2 1 3 VR_ON 4 2 1 <31> G 2 PQ60 FDMS8670S_ POWER56-8~D CPU_VID6 5 CPU_VID5 <8> 3 2 1 <8> 2 3 CPU_VID4 2 D <8> 2 S CPU_VID3 1 CPU_VID2 <8> PQ61 FDMS8692_POWER56-8-5~D <8> 2 PQ62 FDMS8670S_ POWER56-8~D CPU_VID1 5 CPU_VID0 <8> OCP calculation: Assume DCR=0.88mOhm G1=Rn/(Rn+Rsum/3), where Rn=PR224//(PR171+PH5); Rsum=PR143,PR215 DROOP=2*(DCR/2)*G1*Rdroop/Ri=1.896mOhm where Rdroop=PR161;Ri=PR212 Iocp=42.7u*Rdroop/DROOP=~68A. 2 3 2 1 <8> PR252 0_0402_5%~D 1 PR253 0_0402_5%~D 1 PR254 0_0402_5%~D 1 PR255 0_0402_5%~D 1 PR256 0_0402_5%~D 1 PR257 0_0402_5%~D 1 PR258 0_0402_5%~D 1 PQ59 FDMS8670S_ POWER56-8~D H PQ58 FDMS8692_POWER56-8-5~D PL17 FBMA-L18-453215-900LMA90T_1812~D 1 2 2 Document Number Rev 1.0 NAT02 M/B LA-5154P Schematic Thursday, November 26, 2009 Sheet 46 1 of 49 5 4 3 2 1 Battery Connect/OTP 2 3 PD15 DA204U_SOT323~D 2 3 PD14 DA204U_SOT323~D 1 1 2 BATT_SMC 2 2 PR176 1K_0402_5%~D 1 @ PC165 .1U_0402_16V7K~D CPU 2 1K_0402_5%~D 2 1 1 2 PC166 0.1U_0603_25V7K~D PR182 10.7K_0402_1%~D VL PR184 147K_0402_1%~D 1 2 +3VALWP C 2 PR177 1 1 1 VS BATT_TEMP <31> 1 VL 2 2 3 OTP_IN- 2 PR188 150K_0402_1%~D + PD16 P OTP_IN+ PH3 100K_0402_1%_NCP15WF104F03RC 0 - 1 OTP_OUT 1 2 MAINPWON <20,42> 1SS355TE-17_SOD323-2 PU12A LM358ADR_SO8 1 EC_SMB_CK1 <31> PR180 100_0402_5%~D PR190 150K_0402_1%~D 2 PC168 1000P_0402_50V7K~D 2 1 1 1 8 PR186 61.9K_0402_1%~D 1 2 OTP_IN G EC_SMB_DA1 <31> 4 2 PR179 100_0402_5%~D 1 1 PR185 205K_0402_1%~D 1 PR178 6.49K_0402_1%~D 2 9.BAT+ 8.BAT+ 7.ID 6.B/I 5.TS 4.SMD 3.SMC 2.GND 1.GND 2 BATT_TEMP 2 C 11 10 9 8 7 6 5 4 3 2 1 GND GND 9 8 7 6 5 4 3 2 1 PJPB1 SUYIN_200275MR009F50PZR~D SMART Battery: CPU VL 1 BATT_B/I PJPB1 battery connector @ Place clsoe to EC pin PR175 1K_0402_5%~D BATT_SMD 1 PC162 1000P_0402_50V7K~D 2 2 PC163 0.01U_0402_25V7K~D @ D PH3 under CPU botten side : CPU thermal protection at 90 +-3 degree C Recovery at 50 +-3 degree C PC164 100P_0402_50V8J~D 1 BATT+ 1 2 1 2 PC161 100P_0402_50V8J~D PL13 FBMA-L18-453215-900LMA90T_1812~D BATT++ 1 2 2 @ 1 BATT++ 1 @ BATT+ 3 PD13 DA204U_SOT323~D 2 D 3 PD12 DA204U_SOT323~D +3VALWP PC169 1U_0603_10V6K~D 1 BATT+ PR181 453K_0402_1%~D - 1 LM358ADR_SO8 5 BATT_IN 6 1 PR187 10K_0402_1%~D 2 1 + 0 PC167 0.01U_0402_25V7K~D 2 8 BATT_OUT 7 P 2 G 1 PR183 499K_0402_1%~D PU12B 4 <31> BATT_OVP B 2 VS B 2 PR189 86.6K_0402_1% LI-3S :13.5V----BATT_OVP=1.126V BATT_OVP=0.08338*BATT+ A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title BATTERY CONN Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 47 of 49 5 4 3 2 1 2 PR326 0_0603_5%~D 2 1 PR310 8.06K_0402_1%~D +VGFX_CORE 5 PQ46 FDMS8692_POWER56-8-5~D 1 1 +VGFX_COREP PL21 0.45UH_ETQP4LR45XFC_25A_20% 4 1 2 1 PC106 330U_Y_2VM 2 + 2 1 2 PR308 PH6 2.61K_0402_1%~D 10KB_0603_5%_ERTJ1VR103J 4 1 PC105 330U_Y_2VM 1 1 PR219 0_0402_5% 2 PR218 3.65K_0805_1%~D + 2 PC302 10U_0603_6.3V6M~D 1 2 2 1 3 PC288 0.1U_0402_10V7K~D 2 1 4 5 PQ44 PC179 0.22U_0402_10V5K~D 2 JUMP_43X118 @ 3 2 1 1 2 3 2 1 21 FDMS8670S_ POWER56-8~D 14 12 11 10 9 8 13 IMON VIN VDD ISUM+ BOOT VID1 1 C PR311 1 2 11K_0402_1%~D PC183 0.22U_0402_10V5K~D 1 2 2 4.87K_0402_1%~D PC200 100P_0402_50V8J~D PC182 15P_0402_50V8J~D 1 2 @ PQ45 FDMS8670S_ POWER56-8~D 2 1 2 1 PC180 PR216 680P_0603_50V7K~D 4.7_1206_5%~D 1 20 1 PJP37 3 2 1 1 2 1 PR314 10K_0402_1%~D PR309 2 CLK_EN# VID0 3 2 1 1 +VGFX_CORE 19 VID2 2 VCCP PR217 0_0603_5%~D 1 2 +5VALW 22 1 VID3 2 PC177 68P_0402_50V8J~D 23 2 1 VID4 1 24 1 VID5 2 PGOOD 4 17 18 DL_GFX 2 JUMP_43X118 2 16 LX_GFX 1 RBIAS 15 DH_GFX 2 3 47K_0402_1%~D2 VSSP LGATE VID6 1 VW 25 2 COMP 4 UGATE 26 PC178 1000P_0402_50V7K~D 5 4 BST_GFX PU22 ISL62881HRZ-T_QFN28_4X4 PHASE VR_ON PR307 825K_0402_1%~D FB DPRSLPVR PR306 9.76K_0402_1%~D VSEN 6 27 PR215 7 28 +VGFX_CORE C RTN 2 10_0402_5%~D ISUM AGND PR213 1 2 2.2_0603_5%~D PC174 330P_0402_50V7K~D 2 1 2 PC299 330P_0402_50V7K~D 29 <9> VCC_AXG_SENSE 1 VSS_AXG_SENSE <9> PC297 0.33U_0603_10V7K~D 1 2 PR212 1 1 2 PC298 1000P_0402_50V7K~D <9> VSS_AXG_SENSE @ PQ43 FDMS8692_POWER56-8-5~D ISUM- 2 +VGFX_COREP 5 ISUM+ D PJP36 5 PR211 10_0402_5%~D 1 2 PC296 0.033U_0603_16V7K~D 2 2 PC294 1U_0603_10V6K~D 2 1 PR210 24K_0402_1%~D 1 1 GFXVR_IMON <9> PC295 0.22U_0603_25V7K~D PR209 1_0603_5%~D 1 +5VALW 2 1 1 2 0.1U_0603_25V7K~D PC292 10U_1206_25V6M~D PC290 2 1 D 10U_1206_25V6M~D PC289 2 1 B+ 10U_1206_25V6M~D PC301 2 1 PC300 2200P_0402_50V7K~D 2 1 PL20 FBMA-L18-453215-900LMA90T_1812~D GFX_B+ 1 2 @ PC184 1 B 2 PR313 GFXVR_VID_0 <9> 0_0402_5%~D1 2 PR315 GFXVR_VID_1 <9> 0_0402_5%~D1 2 PR316 GFXVR_VID_2 <9> 2 0.1U_0402_10V7K~D 2 0_0402_5%~D1 0_0402_5%~D1 2 PR317 GFXVR_VID_3 <9> 0_0402_5%~D 1 2 PR318 GFXVR_VID_4 <9> 0_0402_5%~D 1 2 PR319 GFXVR_VID_5 <9> 0_0402_5%~D 1 2 PR320 GFXVR_VID_6 <9> 0_0402_5%~D 1 2 PR323 GFXVR_EN <9> 0_0402_5%~D 1 2 PR325 GFXVR_DPRSLPVR <9> PR321 1.87K_0402_1%~D PR324 82.5_0402_1%~D 1 2 1 2 1 <31> GFXVR_PW RGD B PC185 0.01U_0402_16V7K~D ISUM+ ISUM- +GFX_COREP TDC 15.4 A OCP Current 27A A A Compal Electronics, Inc. Compal Secret Data Security Classification 2009/09/21 Issued Date Deciphered Date 2010/09/21 +GFX_COREP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 Title 2 Size Document Number Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 48 of 49 5 4 3 2 V ersion Change L ist ( P. I. R . L ist ) Item Page# D Title +1.1VS_VTTP 1 Page 1 D ate R equest O w ner 08/31 Lin Will Slove EMI Add PL22 and Change PR233 form 0 ohm to 2.2 ohm. X01 Issue D escription Solution D escription R ev. 01 P51 02 P53 +CPU_Core 08/31 Lin Will Slove EMI Change PR259 and PR291 from 0 ohm to 2.2 ohm. X01 03 P55 +GFX_COREP 08/31 Lin Will Adjust load-line and Imon Change PR306 form 9.54K to 9.76K, PR210 from 22.3K to 24K and PC296 from 0.22uF to 0.033uF. X01 04 P55 +GFX_COREP 08/31 Lin Will Adjust output voltage ripple and thermal dispation Add PQ46 and change PC289, PC290, PC301 from 4.7uF to 10uF, and PC105, PC106 from 330uF 9mohm to 330uF 6mohm. X01 05 P43 +1.05VSP/+0.75VSP 10/14 Lin Will Slove the IC input power sequence. 06 P42 +3VALWP/+5VALWP 10/14 Lin Will Slove EMI. Change TPS51117 V5FILT and V5DRV from 5VS to 5VALW. D X02 Change PJP19 to PL23, and PR59, PR60 from 0 ohm to 2.2 ohm. X02 C C Change PJP29 to PL24. 07 P44 +1.5VSP/+0.75VSP 10/14 Lin Will Slove EMI. 08 P45 +1.1VS_VTTP 11/20 Lin Will Low down the power consumption. Charger +3VALWP/+5VALWP 11/20 Lin Will 1206 size shortage issue. +3VALWP/+5VALWP 11/20 Lin Will When adapter inserts and pulls out quickly two twice, it will make TPS51427 out of electricity. 09 10 P41/P42 P42 X02 Change PR232 from 43.2K to 9.31K, and add PR327 2.7K. X03 Change SE142475K8L(1206) to SE000006R8L(0805), and SE041224K8L(1206) to SE000005Z8L(0603). X03 Add PR91,PR92,PR93 100K, PQ24 TP0610K, PQ10 DTC115EUA, and PD17 1SS355TE-17. But all unpop. Change PU5 to ISL6237, and add PJP24. X03 B B A A 2009/09/21 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/09/21 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PWR PIR-1 Size Document Number Custom Rev 1.0 NAT02 M/B LA-5154P Schematic Date: Thursday, November 26, 2009 Sheet 1 49 of 49 www.s-manuals.com
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