Compal LA 6031P Schematics. Www.s Manuals.com. R1.0 Schematics
User Manual: Motherboard Compal LA-6031P NDU00, NDU10 - Schematics. Free.
Open the PDF directly: View PDF 
.
Page Count: 46
| Download | |
| Open PDF In Browser | View PDF |
A B C D E 1 1 NDU00/NDU10 Streamline-S 11.6” Streamline-M 13.3” 2 2 LA-6031P REV 1.0 Schematic Intel Arrandale SFF/IBEX PEAK 3 3 2010-04-12 Rev 1.0 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Cover Page Size B Date: Document Number Rev 1.0 NDU00_LA-6031P M/B Monday, April 12, 2010 Sheet E 1 of 45 A B C D E Compal Confidential Clock Generator Mobile Model Name :NDU00/NDU10 File Name : LA-6031P SLG8SP587VTR page 12 Arrandale CPU BGA 1288pins 1 1 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 Dual Channel page 5,6,7,8,9 1.5V DDRIII 800/1066 MT/s USB/B FDI X8 DMI X4 2.7GHz 2.5GHz BT conn USB port 0,1 USB port 5 page 30 page 25 3G Int. Camera USB port 12 USB port 11 page 26 USB page 12 5V 480MHz LVDS-A LCD Conn. page 11,10 BANK 0, 1, 2, 3 page 12 2 2 PCIeMini Card WiMax RGB CRT (Sub-board) page 13 USB USB port 13 page 26 5V 480MHz PCIe 1x DDP-C HDMI Level Shifter HDMI Conn. page 14 PCIe port 2 page 26 Intel Ibex Peak page 14 3G PCIe 1x PCIe port 4 page 26 RJ45+Transformer (Sub-board) page 27 5V 3GHz(300MB/s) 5V 3GHz(300MB/s) PCIe 1x page 27 FCBGA1071 1.5V 2.5GHz(250MB/s) page 24 USB port 3 eSATA 5V 480MHz PCIe port 5 page 24 USB USB port 3 page 24 3 PCIe 1x CardReader JMB389 page 28 SATA HDD0 SATA port 5 RTL8105E 10/100M PCIe port 1 SATA port 1 1.5V 2.5GHz(250MB/s) 3 Cardreader conn. PCIeMini Card WLAN 1.5V 2.5GHz(250MB/s) page 28 1.5V 2.5GHz(250MB/s) page 15~23 Power/B 3.3V 33 MHz LPC BUS SPI HD Audio 3.3V/1.5V 24MHz HDA Codec page 33 SPI ROM page 15 RTC CKT. Debug Port ALC259 ENE KB926 E0 page 32 page 29 page 31 page 15 4 Touch Pad DC/DC Interface CKT. page 33 page 34 Audio sub-board page 30 EC ROM page 25 page 32 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. page 37~43 B C SPK CONN page 30 4 Compal Electronics, Inc. Compal Secret Data Security Classification Power Circuit DC/DC A Int.KBD D Title Block Diagrams Size Document Number Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet E 2 of 45 5 NSWAA NTWAA Liverpool Intel Arrandale Sunderland Intel Arrandale 4 3 2 1 B+ Ipeak=5A, Imax=3.5A, Iocp min=8.1 DESIGN CURRENT 5A +5VALW DESIGN CURRENT 4A +5VS DESIGN CURRENT 5A +3VALW DESIGN CURRENT 330mA +3V_LAN DESIGN CURRENT 4A +3VS SUSP N-CHANNEL D D SI4800 TPS51125RGER Ipeak=5A, Imax=3.5A, Iocp min=7.9 WOL_EN# P-CHANNEL AO-3413 SUSP N-CHANNEL UMA_ENVDD SI4800 P-CHANNEL AO-3413 DESIGN CURRENT 1.5A +LCD_VDD BT_PWR# C C DESIGN CURRENT 180mA P-CHANNEL AO-3413 +BT_VCC +5VL +3VL VR_ON Ipeak=27A, Imax=18.9A, Iocp min=35 DESIGN CURRENT 48A +CPU_CORE Ipeak=12A, Imax=8.4A, Iocp min=15.6 DESIGN CURRENT 15A +GFX_CORE Ipeak=20A, Imax=14A, Iocp min=28.72 DESIGN CURRENT 18A +VTT/+1.05VS ADP3211AMNR2G GFXVR_EN ADP3211AMNR2G VTTP_EN B APW7138NITRL SYSON Ipeak=7.5A, Imax=5.25A, Iocp min=9.67 DESIGN CURRENT 7.5A B +1.5V RT8209BGQW SUSP DESIGN CURRENT 3A SI4856ADY +1.5VS_CPU_VDDQ SUSP DESIGN CURRENT 1.5A +0.75VS DESIGN CURRENT 1.2A +1.5VS DESIGN CURRENT 1.5A +1.8VS G2992F1U SUSP N-CHANNEL SI4800BDY SUSP# A MP2121DQ-LF-Z A Ipeak=1.7A, Imax=1.19A, Iocp min=3 Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Power Tree Size Document Number Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet 1 3 of 45 A B ( O MEANS ON Voltage Rails +RTCVCC X MEANS OFF ) +B +5VALW +5VL +3VALW D E BTO Option Table +1.5V +5VS Function Bluetooth HDMI 3G Mini Card explain Bluetooth HDMI 3G WIRELESS Mini Card Gensor +3VS +3VL power plane 1 C +1.5VS +GFX_CORE main WIMAX +CPU_CORE +VTT +0.75VS BTO BT@ IHDMI@ 3G@ WLAN@ WIMAX@ 2nd R5F211B4D31SP GSENSOR@ GSENSOR@ 1STGSENSOR@ 2NDGSENSOR@ 1ST@ +1.8VS 1 R5F211B4D34SP 2ND@ +1.5VS_CPU_VDDQ State SIGNAL STATE Full ON 2 S0 O O O O O S1 O O O O O O O O O X S3 S5 S4/AC 3 O O O X X S5 S4/ Battery only O O X X X S5 S4/AC & Battery don't exist O X X X X EC SM Bus1 address Power Device +3VL EC KB926 D3 +3VL Smart Battery Address 0001 011x b SLP_S3# SLP_S4# SLP_S5# HIGH HIGH HIGH S1(Power On Suspend) HIGH HIGH HIGH S3 (Suspend to RAM) LOW HIGH HIGH S4 (Suspend to Disk) LOW LOW HIGH S5 (Soft OFF) LOW LOW LOW G3 LOW LOW LOW 2 3 EC SM Bus2 address Power Device +3VS EC KB926 D3 Address +3VS Gensor +3VS PCH 0100 110x b PCH SM Bus address 4 Power Device +3VALW PCH Address +3VS Clock Generator 1101 001x b +3VS DDR DIMM0 1001 000x b +3VS DDR DIMM1 1001 010x b +3VS WLAN/Wimax/3G 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Notes List Size Document Number Custom Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet E 4 of 45 4 N19 H_PROCHOT#_D 2 68_0402_5% 1 R11 N67 N17 20 H_THERMTRIP# 2 0_0402_5% PLT_RST# @ PROCHOT# H_CPURST# 2 1K_0402_5% H_PMSYNCH 2 0_0402_5% 1 R21 1 R23 PMSYNCH N70 RESET_OBS# M17 PM_SYNC H_CPURST# 1 H_PWRGOOD1_R AM7 R26 2 0_0402_5% +1.5VS_CPU_VDDQ 20 H_PWRGOOD 2 17 DRAMPWROK H_PWRGOOD DRAMPWROK 2 0_0402_5% 1 H_PWRGOOD0_R R28 2 0_0402_5% 1 DRAMPWROK_R R31 VTTPWROK_CPU 1 39 VTTPWROK_CPU 12/22 follow NWQAA DRAMPWROK 2 19 BUF_PLT_RST# R33 3K_0402_1% @ TAPPWRGD 1 VCCPW RGOOD_0 SM_DRAMPW ROK H15 VTTPW RGOOD Y70 R32 VCCPW RGOOD_1 AM5 G3 1.5K_0402_1% Design guide 1.11update,PLTRST series resittor 1.5K, PL resistor 750 ohm PS@ R33 750_0402_1% Y67 DPLL_REF_SSCLK DPLL_REF_SSCLK# Y2 W4 SM_DRAMRST#_CPU CLK_PEG 16 CLK_PEG# 16 PS@ R8 100K_0402_5% SM_DRAMRST# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] PM_EXT_TS#[0] PM_EXT_TS#[1] BV33 SM_RCOMP_0 BP39 SM_RCOMP_1 BV40 SM_RCOMP_2 AV66 PM_EXTTS#0 AV64 PM_EXTTS#_R R10 1 R12 1 R14 1 2 100_0402_1% 2 24.9_0402_1% 2 130_0402_1% 2 R18 1 0_0402_5% DDR3 Compensation Signals Layout Note:Please these resistors near Processor TAPPW RGOOD RSTIN# U71 U69 TCK TMS TRST# T67 N65 P69 XDP_TCK XDP_TMS XDP_TRST# TDI TDO TDI_M TDO_M T69 T71 P71 T70 XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M DBR# W 71 BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] J69 J67 J62 K65 K62 J64 K69 M69 2 R25 1 1K_0402_5% +3VS EMI reverse, close to CPU XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7 XDP_PRDY# XDP_PREQ# XDP_TCK XDP_TMS XDP_DBRESET# INTEL_ARRANDALE_1288 2 C11 @ R1431 1 @ R1432 1 @ R1433 1 @ R1434 1 @ R1435 1 @ R1436 1 @ R1437 1 @ R1438 1 @ R1439 1 @ R1440 1 @ R1441 1 @ R1442 1 @ R1443 1 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 1 2 XDP_BPM#4_R XDP_BPM#5_R VTTPWROK_CPU 2 0_0402_5% @ R37 H_PWRGOOD 1 XDP_BPM#6_R XDP_BPM#7_R 1K_0402_5% H_PWRGOOD_R 2 17 PM_PBTN_OUT# 5 TAPPWRGD 1 @ R38 P G 3 A 2 TAPPWRGD_R 0_0402_5% PS@ R40 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% PAD PAD DRAMPWROK PS@ 1.5K_0402_1% XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R XDP_BPM#4_R XDP_BPM#5_R XDP_BPM#6_R XDP_BPM#7_R XDP_PRDY#_R XDP_PREQ#_R XDP_TCK_R XDP_TMS_R XDP_DBRESET#_R T2 T3 XDP_TCK_R SN74AHC1G08DCKR_SC70-5 GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PW RGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 SAMTE_BSH-030-01-L-D-A @ 2 0_0402_5% 1 R42 2010/04/12 2 0_0402_5% XDP_TDO 1 @ R27 2 0_0402_5% 1 R29 2 0_0402_5% 3 Scan Chain (Default) STUFF -> R20, R23, R27 NO STUFF -> R21, R26 CPU Only STUFF -> R20, R21 NO STUFF -> R23, R26, R27 GMCH Only STUFF -> R26, R27 NO STUFF -> R20, R21, R23 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 B +VTT CLK_CPU_XDP CLK_CPU_XDP# XDP_RST#_R XDP_DBRESET#_R XDP_TDO XDP_TRST# XDP_TDI XDP_TMS_R 1 R39 2 51_0402_5% 1 C12@ R41 0.1U_0402_10V6K 51_0402_5% 2 Compal Electronics, Inc. 2010/01/23 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 1 @ R22 @ Compal Secret Data Security Classification Issued Date 5 XDP_TDO_M JXDP1 XDP_BPM#2_R XDP_BPM#3_R 4 XDP_TDI XDP Connector 1 0.1U_0402_10V6K XDP_BPM#0_R XDP_BPM#1_R 12/22 follow NWQAA O 1 10K_0402_5% 2 0_0402_5% C XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7 +3VALW IN2 1 10K_0402_5% JTAG MAPPING R36 10K_0402_5% IN1 +VTT 1 R20 XDP_DBRESET# 17 +VTT 2 D XDP_TDI_R XDP_TDO_R XDP_PREQ#_R XDP_PRDY#_R 34,39 VTTPWROK 2 XDP_TDI_M B U2 2 Routed as a single daisy chain +VTT 1 RST_GATE 20 R24 0_0402_5% @ VTTPWROK R13 PM_EXTTS#_R R17 XDP_PRDY# XDP_PREQ# PRDY# PREQ# R34 750_0402_1% 1 R1477 2 R1484 1 0_0402_5% PS@ C878 0.1U_0402_10V6K 2 PS@ PM_EXTTS#0 PM_EXTTS# 10,11 1 SM_DRAMRST# 10,11 PS@ Q1 BSS138_NL_SOT23-3 1 BJ12 SM_DRAMRST#_CPU For S3 CPU power saving PMEG2010AEH_SOD123 1 2 D1 3 1 L21 J21 THERMTRIP# Power Management 1 PECI 1 R19 XDP_RST#_R 17 CATERR# JTAG & MBP 2 19,26,27,28,31,32 R15 68_0402_5% @ PROC_DETECT PEG_CLK PEG_CLK# 1 0_0402_5% 1 N61 K71 J70 CLK_CPU_XDP 1 2 1 R5 @ 2 0_0402_5% CLK_CPU_XDP# R6 @ 0_0402_5% 2 CATERR# BCLK_ITP BCLK_ITP# 2 R2 @ CLK_CPU_BCLK 20 CLK_CPU_BCLK# 20 CLK_CPU_XDP_R CLK_CPU_XDP#_R 1 T1 2 49.9_0402_1% AK7 AK8 2 TP_SKTOCC# M71 Clocks COMP0 BCLK BCLK# DDR3 Misc COMP1 AE66 PECI +VTT +VTT AD69 Thermal 20 COMP2 G 1 R9 COMP3 AC70 D PAD +VTT AD71 S H_COMP3 2 20_0402_1% H_COMP2 2 20_0402_1% H_COMP1 2 49.9_0402_1% H_COMP0 2 49.9_0402_1% 1 R1 1 R3 1 R4 1 R7 D R30 1.1K_0402_1% @ 1 For S3 CPU power saving Misc Layout rule 10mil width trace length < 0.5", spacing 20mil C 2 2 ： 3 U1B 2 5 2 Title CPU CLK/MISC/JTAG Size Document Number Custom Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet 1 5 of 45 A 5 4 3 2 1 04/20 INTEL #418125 update U1E D F7 J8 K8 J4 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] 17 17 17 17 DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 F9 J6 K9 J2 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] 17 17 17 17 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 H17 K15 J13 F10 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] 17 17 17 17 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 G17 M15 G13 J11 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 L2 N7 M4 P1 N10 R7 U7 W8 FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] 17 17 17 17 17 17 17 17 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 K1 N5 N2 R2 N9 R8 U6 W10 FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] 17 FDI_FSYNC0 17 FDI_FSYNC1 AC7 AC9 FDI_FSYNC[0] FDI_FSYNC[1] 17 FDI_INT AB5 17 FDI_LSYNC0 17 FDI_LSYNC1 AA1 AB2 Intel(R) FDI 17 17 17 17 17 17 17 17 FDI_INT FDI_LSYNC[0] FDI_LSYNC[1] B PCI EXPRESS -- GRAPHICS DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 DMI C 17 17 17 17 PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS B12 A13 D12 B11 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] G40 G38 H34 P34 G28 H25 H24 D29 B26 D26 B23 D22 A20 D19 A17 B14 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] F40 J38 G34 M34 J28 G25 K24 B28 A27 B25 A24 B21 B19 B18 B16 D15 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] N40 L38 M32 D40 A38 G32 B33 B35 L30 A31 B32 L28 N26 M24 G21 J20 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] L40 N38 N32 B39 B37 H32 A34 D36 J30 B30 D33 N28 M25 N24 F21 L20 PEG_COMP 1 R43 2 49.9_0402_1% PEG_RBIAS 1 R44 2 750_0402_1% PAD T142 PAD T141 PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD T140 T139 T138 T136 T135 T134 T133 T132 T130 T129 T128 T127 T126 PAD T121 CFG Straps for PROCESSOR CFG0 R93 1 2 @ 3.01K_0402_1% PCI-Express Configuration Select 1: Single PEG CFG0 0: Bifurcation enabled Not applicable for Clarksfield Processor CFG3 R79 1 2 @ 3.01K_0402_1% CFG3-PCI Express Static Lane Reversal 1: Normal Operation CFG3 0: Lane Numbers Reversed 15 -> 0, 14 ->1, ..... CFG4 R272 1 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 AL4 AM2 AK1 AK2 AK4 AJ2 AT2 AG7 AF4 AG2 AH1 AC2 AC4 AE2 AD1 AF8 AF6 AB7 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] AU1 RSVD_TP[0] T4 T2 RSVD15 RSVD16 U1 V2 RSVD17 RSVD18 AV71 AW70 RSVD19 RSVD20 AY69 BB69 RSVD21 RSVD22 D8 B7 RSVD23 RSVD24 A10 B9 RSVD26 RSVD27 C5 A6 RSVD_NCTF[7] RSVD_NCTF[8] E3 F1 RSVD_NCTF[6] RSVD_NCTF[5] 2 3.01K_0402_1% ES1 sample need negative voltage ES2 sample contact to GND CFG4-Display Port Presence 1: Disabled; No Physical Display Port attached to Embedded Display Port CFG4 0: Enabled; An external Display Port device is connected to the Embedded Display Port W66 W64 T116 PAD T117 PAD RSVD34 RSVD35 AC69 AC71 T118 PAD RSVD36 RSVD37 AA71 AA69 RSVD38 RSVD39 R66 R64 RSVD_NCTF[3] RSVD_NCTF[4] BT5 BR5 RSVD_NCTF[2] RSVD_NCTF[1] BV6 BV8 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD54 RSVD55 RSVD56 RSVD57 RSVD58 RESERVED U1A RSVD32 RSVD33 T119 PAD D AV69 AK71 AN69 AP66 AH66 AK66 AR71 AM66 AK69 AU71 AT70 AR69 AU69 AT67 RSVD_TP[2] RSVD_TP[1] AP2 AN7 RSVD62 RSVD63 AV4 AU2 RSVD64 RSVD65 BE69 BE71 DC_TEST_BV71 DC_TEST_BV69 DC_TEST_BV68 DC_TEST_BV5 DC_TEST_BV3 DC_TEST_BV1 DC_TEST_BT71 DC_TEST_BT69 DC_TEST_BT3 DC_TEST_BT1 DC_TEST_BR71 DC_TEST_BR1 DC_TEST_E71 DC_TEST_E1 DC_TEST_C71 DC_TEST_C69 DC_TEST_C3 DC_TEST_A71 DC_TEST_A69 DC_TEST_A68 DC_TEST_A5 BV71 BV69 BV68 BV5 BV3 BV1 BT71 BT69 BT3 BT1 BR71 BR1 E71 E1 C71 C69 C3 A71 A69 A68 A5 C T122 PAD B T124 PAD T125 PAD INTEL_ARRANDALE_1288 INTEL_ARRANDALE_1288 A A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title CPU DMI/FDI/PEG Size B Date: Document Number Rev 1.0 NDU00_LA-6031P M/B Monday, April 12, 2010 Sheet 1 6 of 45 5 4 3 2 U1C U1D 11 DDR_B_D[0..63] AT8 AT6 BB5 BB9 AV7 AV6 BE6 BE8 BF11 BE11 BK5 BH13 BF9 BF6 BK7 BN8 BN11 BN9 BG17 BK15 BK9 BG15 BH17 BK17 BN20 BN17 BK25 BH25 BJ20 BH21 BG24 BG25 BJ40 BM43 BF47 BF48 BN40 BH43 BN44 BN47 BN48 BN51 BH53 BJ55 BH48 BJ48 BM53 BN55 BF55 BN57 BN65 BJ61 BF57 BJ57 BK64 BK61 BJ63 BF64 BB64 BB66 BJ66 BF65 AY64 BC70 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 BT38 BH38 BF21 SA_BS[0] SA_BS[1] SA_BS[2] 10 DDR_A_CAS# 10 DDR_A_RAS# 10 DDR_A_W E# BK43 BL38 BF38 SA_CAS# SA_RAS# SA_WE# D C B BM34 BP35 BF20 DDRA_CLK0 10 DDRA_CLK0# 10 DDRA_CKE0 10 SA_CK[1] SA_CK#[1] SA_CKE[1] BK36 BH36 BK24 DDRA_CLK1 10 DDRA_CLK1# 10 DDRA_CKE1 10 SA_CS#[0] SA_CS#[1] BH40 BJ47 DDRA_SCS0# 10 DDRA_SCS1# 10 SA_ODT[0] SA_ODT[1] BF43 BL47 DDRA_ODT0 10 DDRA_ODT1 10 SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] BB10 BJ10 BM15 BN24 BG44 BG53 BN62 BH59 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 BV43 BV41 BV24 SB_BS[0] SB_BS[1] SB_BS[2] 11 DDR_B_CAS# 11 DDR_B_RAS# 11 DDR_B_W E# BU46 BT40 BT41 SB_CAS# SB_RAS# SB_WE# 10 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 AY5 DDR_A_DQS#0 BJ7 DDR_A_DQS#1 BN13 DDR_A_DQS#2 BL21 DDR_A_DQS#3 BH44 DDR_A_DQS#4 BK51 DDR_A_DQS#5 BP58 DDR_A_DQS#6 BE62 DDR_A_DQS#7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] AY7 BJ5 BL13 BN21 BK44 BH51 BM60 BE64 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] BT36 BP33 BV36 BG34 BG32 BN32 BK32 BJ30 BN30 BF28 BH34 BH30 BJ28 BF40 BN28 BN25 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 BA2 AW2 BD1 BE4 AY1 BC2 BF2 BH2 BG4 BG1 BR6 BR8 BJ4 BK2 BU9 BV10 BR10 BT12 BT15 BV15 BV12 BP12 BV17 BU16 BP15 BU19 BV22 BT22 BP19 BV19 BV20 BT20 BT48 BV48 BV50 BP49 BT47 BV52 BV54 BT54 BP53 BU53 BT59 BT57 BP56 BT55 BU60 BV59 BV61 BP60 BR66 BR64 BR62 BT61 BN68 BL69 BJ71 BF70 BG71 BC67 BK70 BK67 BD71 BD69 DDR_A_DM[0..7] DDR SYSTEM MEMORY A DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 SA_CK[0] SA_CK#[0] SA_CKE[0] DDR_A_DQS#[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..15] 10 10 10 11 11 11 SB_CK[0] SB_CK#[0] SB_CKE[0] BU33 BV34 BT26 DDRB_CLK0 11 DDRB_CLK0# 11 DDRB_CKE0 11 SB_CK[1] SB_CK#[1] SB_CKE[1] BV38 BU39 BT24 DDRB_CLK1 11 DDRB_CLK1# 11 DDRB_CKE1 11 SB_CS#[0] SB_CS#[1] BP46 BT43 DDRB_SCS0# 11 DDRB_SCS1# 11 SB_ODT[0] SB_ODT[1] BV45 BU49 DDRB_ODT0 11 DDRB_ODT1 11 SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] BB4 BL4 BT13 BP22 BV47 BV57 BU65 BF67 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 DDR_B_DM[0..7] D 11 C DDR SYSTEM MEMORY - B 10 DDR_A_D[0..63] 10 10 10 1 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] BE2 DDR_B_DQS#0 BM3 DDR_B_DQS#1 BU12 DDR_B_DQS#2 BT19 DDR_B_DQS#3 BT52 DDR_B_DQS#4 BV55 DDR_B_DQS#5 BU63 DDR_B_DQS#6 BG69 DDR_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] BD4 BN4 BV13 BT17 BT50 BU56 BV62 BJ69 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] BT34 BP30 BV29 BU30 BV31 BT33 BT31 BP26 BV27 BT27 BU42 BU26 BT29 BT45 BV26 BU23 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_DQS#[0..7] DDR_B_DQS[0..7] 11 11 B DDR_B_MA[0..15] 11 INTEL_ARRANDALE_1288 A A INTEL_ARRANDALE_1288 Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title CPU DDRIII Size B Date: Document Number Rev 1.0 NDU00_LA-6031P M/B Monday, April 12, 2010 Sheet 1 7 of 45 1 1 @ 1 2 1K_0402_5% 2 1K_0402_5% H_PSI# H_DPRSLPVR R1463 R1464 Add pull high_1130 2 1K_0402_5% 2 1K_0402_5% 1 1 @ Reserved pull low_1203 +VTT_DDR 1 2 1 2 1 2 +VTT 1 2 1 2 10U_0805_6.3V6M C61 2 10U_0805_6.3V6M C60 1 1 2 INTEL_ARRANDALE_1288 04/29 Change C55,C56,C57 from @47P_0402 to 1UF_0402 by HP. +CPU_CORE +CPU_CORE 0116 add 1U_0402_6.3V4Z 2 1 2 1 2 1 2 1 2 1U_0402_6.3V4Z C77 2 1 1U_0402_6.3V4Z C76 2 1 1U_0402_6.3V4Z C75 2 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 +VCAP0 H_VTTVID1 = High, 1.05V F68 PSI# CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 A61 D61 D62 A62 B63 D64 D66 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] AN1 VTT_SELECT[1] F66 PROC_DPRSLPVR A41 ISENSE F64 F63 VCC_SENSE VSS_SENSE 39 VTT_SENSE N13 VTT_SENSE 39 VSS_SENSE_VTT R12 VSS_SENSE_VTT 42 CPU_VID[0..6] H_VTTSELECT PAD T9 PAD T8 42 VCCSENSE VSSSENSE 42 VCCSENSE 42 VSSSENSE CPU CORE SUPPLY H_PSI# H_DPRSLPVR IMVP_IMON 0_0402_5% 1 2 1 2 R49 R50 VCCSENSE_R VSSSENSE_R VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_43 VTT0_44 VTT0_45 VTT0_46 VTT0_47 VTT0_48 VTT0_49 VTT0_50 VTT0_51 VTT0_52 VTT0_53 VTT0_54 VTT0_55 VTT0_56 VTT0_57 VTT0_58 VTT0_59 VTT0_60 VTT0_61 VTT0_62 VTT0_63 VTT0_64 VTT0_65 VTT0_66 VTT0_67 VTT0_68 VTT0_69 VTT0_70 VTT0_71 VTT0_72 VTT0_73 1.1V RAIL POWER POWER BD55 BD51 BD48 BB55 BB51 BB48 AY57 AY53 AY50 AW57 AW53 AW50 AU55 AU51 AU48 AR55 AR51 AR48 AN57 AN53 AN50 AL57 AL53 AL50 AK57 AK53 AK50 +VTT U1F H_VTTVID1 = Low, 1.1V VCAP0_1 VCAP0_2 VCAP0_3 VCAP0_4 VCAP0_5 VCAP0_6 VCAP0_7 VCAP0_8 VCAP0_9 VCAP0_10 VCAP0_11 VCAP0_12 VCAP0_13 VCAP0_14 VCAP0_15 VCAP0_16 VCAP0_17 VCAP0_18 VCAP0_19 VCAP0_20 VCAP0_21 VCAP0_22 VCAP0_23 VCAP0_24 VCAP0_25 VCAP0_26 VCAP0_27 0_0402_5% +VCAP1 VCAP1_1 VCAP1_2 VCAP1_3 VCAP1_4 VCAP1_5 VCAP1_6 VCAP1_7 VCAP1_8 VCAP1_9 VCAP1_10 VCAP1_11 VCAP1_12 VCAP1_13 VCAP1_14 VCAP1_15 VCAP1_16 VCAP1_17 VCAP1_18 VCAP1_19 VCAP1_20 VCAP1_21 VCAP1_22 VCAP1_23 VCAP1_24 VCAP1_25 VCAP1_26 VCAP1_27 BD44 BD41 BD37 BB44 BB41 BB37 AY46 AY42 AY39 AW46 AW42 AW39 AU44 AU41 AU37 AR44 AR41 AR37 AN46 AN42 AN39 AL46 AL42 AL39 AK46 AK42 AK39 +CPU_CORE Close to CPU VCCSENSE 1 R51 1 R52 VSSSENSE 2 100_0402_1% 2 100_0402_1% 10U_0805_6.3V6M +1.8VS 1 4.7U_0603_6.3V6K 1 C47 C48 2 W39 W37 U37 R39 R37 VCCPLL1 VCCPLL2 VCCPLL3 VCCPLL4 VCCPLL5 2 +1.5VS_CPU_VDDQ L2 2 0_0603_5% +VDDQ_CK 1 BB14 BB12 VDDQ_CK[1] VDDQ_CK[2] 1 C57 1U_0402_6.3V4Z AW14 AW12 AU60 AU59 AU12 AR60 AR59 AR12 AN60 AN59 AN35 AN33 AN17 AN15 AN14 AN12 AM10 AL60 AL59 AL17 AL15 AL14 AL12 AK35 AK33 AF39 AF37 AF35 AF33 AF32 AF30 AD39 BF60 BF59 BD60 BD59 BB60 BB59 AY60 AW60 AW35 AW33 AD37 AD35 AD33 AD32 AD30 W35 W33 W32 W30 W28 W26 W24 W23 U35 U33 U32 U30 U28 U26 U24 U23 R35 R33 R32 R30 R28 R26 R24 R23 AY10 VTT0_72 AN9 VTT0_73 A B C 2 INTEL_ARRANDALE_1288 VTT0_72 VTT0_73 R53 R54 2 0_0402_5% 2 0_0402_5% 1 1 +VTT INTEL_ARRANDALE_1288 1 1U_0402_6.3V4Z C74 1U_0402_6.3V4Z @ 2 1 1U_0402_6.3V4Z C73 2 1 1U_0402_6.3V4Z C72 C68 1U_0402_6.3V4Z C71 2 1 1U_0402_6.3V4Z C70 C67 C69 1 47P_0402_50V8J C66 AF57 AF55 AF53 AF51 AF50 AF48 AF46 AF44 AF42 AF41 AD55 AD51 AD48 AD44 AD41 AB55 AB51 AB48 AB44 AB41 AA55 AA51 AA48 AA44 AA41 W55 W51 W48 W44 W41 U55 U51 U48 U44 U41 R55 R51 R48 R44 R41 P60 N55 N51 N48 N44 N42 M60 M51 M44 L55 K60 K51 K44 J55 H60 H51 H44 G60 G55 G51 G44 F55 E60 E57 E53 E50 E46 E42 D59 D57 D55 D54 D52 D50 D48 D47 D45 D43 B60 B56 B53 B49 B46 B42 A57 A54 A50 A47 A43 POWER L1 0_0603_5% 10U_0805_6.3V6M C59 2 C65 10U_0805_6.3V6M 2 C64 10U_0805_6.3V6M 2 C63 10U_0805_6.3V6M C62 10U_0805_6.3V6M 2 1 2 +VTT AD15 AD14 AD12 AB12 AA12 W17 W15 W14 W12 R15 VTT1_12 VTT1_13 VTT1_14 VTT1_15 VTT1_16 VTT1_17 VTT1_18 VTT1_19 VTT1_20 VTT1_21 2 1 2 1 AW32 AW30 AW28 AW26 AW24 AW23 AW21 AW19 AW17 AW15 2 1 2 1 2 SENSE LINES GRAPHICS VIDs VTT0_DDR VTT0_DDR[1] VTT0_DDR[2] VTT0_DDR[3] VTT0_DDR[4] VTT0_DDR[5] VTT0_DDR[6] VTT0_DDR[7] VTT0_DDR[8] VTT0_DDR[9] @ 10U_0805_6.3V6M C58 +VTT 1 R1460 R1461 U1H SENSE LINES C 1 +VTT 2 1K_0402_5% 1 @ CPU VIDS 0112 change size 1 R1466 1.8V 2 + 2 1 C35 1U_0402_6.3V4Z 1 1 2 1 1U_0402_6.3V4Z C56 2 2 1 C34 1U_0402_6.3V4Z 1 1 C42 10U_0805_6.3V6M 2 VCAP2_1 VCAP2_2 VCAP2_3 VCAP2_4 VCAP2_5 VCAP2_6 VCAP2_7 VCAP2_8 VCAP2_9 VCAP2_10 VCAP2_11 VCAP2_12 VCAP2_13 VCAP2_14 VCAP2_15 VCAP2_16 VCAP2_17 VCAP2_18 VCAP2_19 +VTT GFXVR_IMON 43 +1.5VS_CPU_VDDQ 1U_0402_6.3V4Z C55 BU40 BU35 BU28 BN38 BM25 BL30 BJ38 BH32 BH28 BG43 BF16 BF15 BD35 BD33 BD32 BD30 BD28 BD26 BD24 BD23 BD21 BD19 BD17 BD15 BB35 BB33 BB32 BB30 BB28 BB26 BB24 BB23 BB21 BB19 BB17 BB15 1U_0402_6.3V4Z C54 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26 VDDQ27 VDDQ28 VDDQ29 VDDQ30 VDDQ31 VDDQ32 VDDQ33 VDDQ34 VDDQ35 VDDQ36 2 R47 39,43 C33 1U_0402_6.3V4Z 1 1U_0402_6.3V4Z C53 2 1U_0402_6.3V4Z C52 1 1U_0402_6.3V4Z C51 2 1U_0402_6.3V4Z C50 1U_0402_6.3V4Z C49 1 GFX_DPRSLPVR Reserved_1203 GFX_VID0 43 GFX_VID1 43 GFX_VID2 43 GFX_VID3 43 GFXVID4 43 GFX_VID5 43 GFX_VID6 43 4.7K_0402_5% @ 1 AH69 GFXVR_EN AL71 GFX_DPRSLPVR AL69 GFX_VR_EN GFX_DPRSLPVR GFX_IMON +VCAP2 AK62 AK60 AK59 AH60 AH59 AF60 AF59 AD60 AD59 AB60 AB59 AA60 AA59 W60 W59 U60 U59 R60 R59 AF71 AG67 AG70 AH71 AN71 AM67 AM70 GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] C41 10U_0805_6.3V6M 2 2 1K_0402_5% 1 VCC_AXG_SENSE 43 VSS_AXG_SENSE 43 C32 1U_0402_6.3V4Z 2 1 VTT1_1 VTT1_2 VTT1_3 VTT1_4 VTT1_5 VTT1_6 VTT1_7 VTT1_8 VTT1_9 VTT1_10 VTT1_11 PEG & DMI 2 1 C46 10U_0805_6.3V6M 1 C45 10U_0805_6.3V6M C44 10U_0805_6.3V6M 2 C43 10U_0805_6.3V6M 1 W21 W19 U21 U19 U17 U15 U14 U12 R21 R19 R17 AF12 AF10 VAXG_SENSE VSSAXG_SENSE C40 330U_B2_2.5VM_R15M +VTT VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 C31 1U_0402_6.3V4Z 0116 add B AN32 AN30 AN28 AN26 AN24 AN23 AN21 AN19 AL32 AL30 AL28 AL26 AL24 AL23 AL21 AL19 AK14 AK12 AJ10 AH14 AH12 AF28 AF26 AF24 AF23 AF21 AF19 AF17 AF15 AF14 AD28 AD26 AD24 AD23 AD21 AD19 AD17 GRAPHICS 2 C39 1U_0402_6.3V4Z 1 C30 1U_0402_6.3V4Z 2 2 C38 1U_0402_6.3V4Z 1 1 2 5 U1G C26 1U_0402_6.3V4Z 2 1 C29 1U_0402_6.3V4Z 2 2 C25 1U_0402_6.3V4Z 1 1 C37 1U_0402_6.3V4Z 2 C36 1U_0402_6.3V4Z 1 2 1 C28 1U_0402_6.3V4Z 2 1 2 C24 1U_0402_6.3V4Z 1 1 C27 1U_0402_6.3V4Z 2 C23 1U_0402_6.3V4Z 1 4 +CPU_CORE 1U_0402_6.3V4Z A R1465 2 GFXVR_EN 4.7K_0402_5% 1 R46 - 1.5V RAILS 2 Follow SCH check list 09/22 update DDR3 2 + 3 +VTT POWER 2 + 1 330U_2.5V_M_R17 2 1 330U_2.5V_M_R17 2 1 10U_0805_6.3V6M 2 10U_0805_6.3V6M 1U_0402_6.3V4Z 1 C22 C21 C20 C19 1 1 2 +GFX_CORE C18 C17 1 +VCAP0 1U_0402_6.3V4Z 2 1 1U_0402_6.3V4Z 1 C78 1U_0402_6.3V4Z D 2 +VCAP1 0112 add 7pcs Caps to follow Design guide 1U_0402_6.3V4Z 1 C79 2 1 C80 2 1U_0402_6.3V4Z 1 C81 2 1 C82 2 1U_0402_6.3V4Z 1 C83 2 1 C84 2 1 C85 2 1U_0402_6.3V4Z 1 C86 2 1 C87 2 1U_0402_6.3V4Z 1 C88 1 C89 2 2 C90 1U_0402_6.3V4Z 0112 add 7pcs Caps to follow Design guide 1U_0402_6.3V4Z 1 1U_0402_6.3V4Z 1 C91 2 2 1 C92 2 C93 2 1U_0402_6.3V4Z 1 1 C94 2 C95 2 1U_0402_6.3V4Z 1 1 C96 2 1U_0402_6.3V4Z 1 C97 2 1 C98 2 1U_0402_6.3V4Z 1 C99 2 1 C100 2 C101 2 D +VTT +CPU_CORE 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1U_0402_6.3V4Z C120 1 1U_0402_6.3V4Z C119 2 1U_0402_6.3V4Z C118 1 1U_0402_6.3V4Z C117 2 1U_0402_6.3V4Z C116 1 1U_0402_6.3V4Z C115 2 1U_0402_6.3V4Z C114 1 1U_0402_6.3V4Z C113 2 1U_0402_6.3V4Z C112 1 1U_0402_6.3V4Z C111 2 1U_0402_6.3V4Z C110 1 1U_0402_6.3V4Z C109 @ 1U_0402_6.3V4Z C108 2 1U_0402_6.3V4Z C107 1 1U_0402_6.3V4Z C106 @ C105 2 47P_0402_50V8J 1 C104 @ 47P_0402_50V8J C103 2 47P_0402_50V8J C102 1 47P_0402_50V8J @ 1U_0402_6.3V4Z 0116 add 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 Compal Secret Data Security Classification Issued Date 2 2010/04/12 Deciphered Date 2010/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 1U_0402_6.3V4Z 3 4 Title Compal Electronics, Inc. Auburndale(4/5)-PWR Size Document Number Custom NDU00_LA-6031P Date: Rev 1.0 M/B Monday, April 12, 2010 Sheet 5 8 of 45 3 4 0112 Add to follow design guide CPU CORE 1 1 1 2 1U_0402_6.3V4Z 1 1 C139 C140 2 1 C141 2 2 1U_0402_6.3V4Z 1 + 1U_0402_6.3V4Z 1 C149 2 C150 2 1 C151 C152 2 2 C153 2 1U_0402_6.3V4Z C168 2 1 2 1 2 1 2 1 2 C169 2 2 A 1- SV BGA 4x470uF bulk on C95,C96,C97,C98 2- LV BGA 3x330uF 9mR (SGA20331E10) bulk on C96,C97,C98 1 2 1 2 1 2 1 2 1 2 B C170 Under cavity 2 1U_0402_6.3V4Z For S3 CPU power saving +1.5V PS@ Q2 1 2 3 4 2 R55 470_0805_5% PS@ 1 C171 S S S G D D D D SI4856ADY_SO8 R57 820K_0402_5% PS@ Q3A 2 1 2 2 PS@ C172 Q3B PS@ 5 +VSB PS@ 6 1 1 3 1 R56 2 220K_0402_5% 1 2N7002DW-T/R7_SOT363-6 8 7 6 5 10U_0805_10V4K 2 PS@ 4 SUSP PS@ SUSP SUSP 34,41 2N7002DW-T/R7_SOT363-6 C FAN Control Circuit +5VS 1A 1 1SS355_SOD323-2 D2 @ 2 JFAN1 +FAN1 1 1 C13 10U_0805_10V4Z 2 U3 1 2 3 4 +FAN1 31 EN_DFAN1 10mil 1 2 EN VIN VOUT VSET 8 7 6 5 GND GND GND GND D3 @ C14 @ 1000P_0402_25V8J 1 1 2 3 1 2 3 4 5 GND GND ACES_88231-03041_3P @ BAS16_SOT23-3 APL5607KI-TRG_SO8 C15 10U_0805_10V4Z R45 2 10K_0402_5% 1 +3VS FAN_SPEED1 31 2 D C16 0.01U_0402_16V7K 1 @ Compal Secret Data Security Classification Issued Date 2010/04/12 Deciphered Date 2010/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 2 1 1 +1.5VS_CPU_VDDQ INTEL_ARRANDALE_1288 1 2 1 C164 22U_0805_6.3V6M 1U_0402_6.3V4Z 1 Under cavity C154 1 2 2 C163 22U_0805_6.3V6M 1U_0402_6.3V4Z C167 2 L C162 22U_0805_6.3V6M C166 2 + 2 C161 22U_0805_6.3V6M C165 2 1U_0402_6.3V4Z 1 2 1 2 1U_0402_6.3V4Z 1 2 1 05/06 update to change C95,C96,C97,C98 from SGA00002X00(330U_7mR) to SGA00004200(470U_4.5mR) C160 22U_0805_6.3V6M 1 + 2 1 C159 22U_0805_6.3V6M 1 2 1 1 1 1U_0402_6.3V4Z + 2 1 C158 22U_0805_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 1 C157 22U_0805_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 2 1 Inside cavity C144 2 2 1 2 1 C148 330U_D2_2VM_R9M 1U_0402_6.3V4Z 1 C143 2 2 1 1U_0402_6.3V4Z 1 C142 2 2 1 C147 330U_D2_2VM_R9M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 1 C138 22U_0805_6.3V6M 1 1U_0402_6.3V4Z C137 22U_0805_6.3V6M 2 C136 22U_0805_6.3V6M 1U_0402_6.3V4Z C126 2 C135 22U_0805_6.3V6M 2 C134 22U_0805_6.3V6M 2 1 C125 C133 22U_0805_6.3V6M 2 1 C124 C132 22U_0805_6.3V6M 2 1 C123 C131 22U_0805_6.3V6M C122 C130 22U_0805_6.3V6M C121 1U_0402_6.3V4Z C129 22U_0805_6.3V6M A40 A36 A33 A29 A26 A22 A19 A15 A12 A8 B62 B58 B55 B51 B48 B44 A59 A55 A52 A48 A45 AA17 AA15 AA14 AA4 W69 W62 W57 W53 W50 W46 W42 W6 W1 V70 U64 U62 U57 U53 U50 U46 U42 U39 U9 U4 T1 R70 R62 R57 R53 R50 R46 R42 R5 P4 N63 N57 N53 N50 N46 N30 N21 N15 M53 M42 M36 M1 L70 L57 L48 L47 L13 K64 K53 K43 K36 K34 K32 K25 K17 K11 K6 K4 J65 J57 J48 J47 J40 J9 H53 H43 H36 H1 G70 G57 G53 G48 G47 G43 G30 G24 G20 G15 F61 F48 F47 F28 C156 22U_0805_6.3V6M VSS VSS404 VSS405 VSS406 VSS407 VSS408 VSS409 VSS410 VSS411 VSS412 VSS413 VSS393 VSS394 VSS395 VSS396 VSS397 VSS398 VSS399 VSS400 VSS401 VSS402 VSS403 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS326 VSS327 VSS328 VSS329 VSS330 VSS331 VSS332 VSS333 VSS334 VSS335 VSS336 VSS337 VSS338 VSS339 VSS340 VSS341 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352 VSS353 VSS354 VSS355 VSS356 VSS357 VSS358 VSS359 VSS360 VSS361 VSS362 VSS363 VSS364 VSS365 VSS366 VSS367 VSS368 VSS369 VSS370 VSS371 VSS372 VSS373 +CPU_CORE 1U_0402_6.3V4Z C146 330U_D2_2VM_R9M INTEL_ARRANDALE_1288 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS374 VSS375 VSS376 VSS377 VSS378 VSS379 VSS380 VSS381 VSS382 VSS383 VSS384 VSS385 VSS386 VSS387 VSS388 VSS389 VSS390 VSS391 VSS392 VSS415 1U_0402_6.3V4Z C128 22U_0805_6.3V6M D AH53 AH51 AH50 AH48 AH46 AH44 AH42 AH41 AH39 AH37 AH35 AH33 AH32 AH30 AH28 AH26 AH24 AH23 AH21 AH19 AH17 AH15 AH4 AG64 AG9 AG6 AF69 AF62 AF1 AE70 AE64 AD62 AD57 AD53 AD50 AD46 AD42 AD4 AC67 AC64 AC10 AC5 AC1 AB70 AB62 AB57 AB53 AB50 AB46 AB42 AB39 AB37 AB35 AB33 AB32 AB30 AB28 AB26 AB24 AB23 AB21 AB19 AB17 AB15 AB14 AB9 AA66 AA64 AA62 AA57 AA53 AA50 AA46 AA42 AA39 AA37 AA35 AA33 AA32 AA30 AA28 AA26 AA24 AA23 AA21 AA19 F20 F4 E37 E33 E30 E16 E12 D41 D38 D34 D31 D27 D24 D20 D17 D13 D10 D6 B65 B40 1U_0402_6.3V4Z C155 22U_0805_6.3V6M C VSS U1J C145 330U_D2_2VM_R9M B VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 C127 22U_0805_6.3V6M A BU62 BU58 BU55 BU51 BU48 BU44 BU37 BU32 BU25 BU21 BU18 BU14 BU11 BU7 BP42 BN64 BN6 BM70 BM51 BM44 BM32 BM24 BM17 BL57 BL55 BL48 BL40 BL28 BL20 BK63 BK60 BK53 BK34 BK10 BJ64 BJ21 BJ9 BJ1 BH70 BH57 BH55 BH47 BH24 BH20 BH15 BG51 BG36 BF62 BF30 BF13 BF8 BE70 BE65 BE9 BE1 BD57 BD53 BD50 BD46 BD42 BD39 BD14 BB71 BB62 BB57 BB53 BB50 BB46 BB42 BB39 BB7 BB1 BA70 AY71 AY66 AY62 AY59 AY55 AY51 AY48 AR42 AR39 AR35 AR33 AR32 AR30 AR28 AR26 AR24 AR23 AR21 AR19 AR17 AR15 AR14 AR4 AR1 AP70 AP64 AN62 AN55 AY44 AY41 AY37 AY35 AY33 AY32 AY30 AY28 AY26 AY24 AY23 AY21 AY19 AY17 AY15 AY14 AY12 AY8 AY4 AW67 AW62 AW59 AW55 AW51 AW48 AW44 AW41 AW37 AV9 AV1 AU70 AU62 AU57 AU53 AU50 AU46 AU42 AU39 AU35 AU33 AU32 AU30 AU28 AU26 AU24 AU23 AU21 AU19 AU17 AU15 AU14 AU4 AT64 AT10 AR62 AR57 AR53 AR50 AR46 AN51 AN48 AN44 AN41 AN37 AN5 AN4 AM64 AM8 AL62 AL55 AL51 AL48 AL44 AL41 AL37 AL35 AL33 AL1 AK70 AK64 AK55 AK51 AK48 AK44 AK41 AK37 AK32 AK30 AK28 AK26 AK24 AK23 AK21 AK19 AK17 AK15 AJ70 AH62 AH57 AH55 BV66 BV64 BT68 BR69 BR68 BR3 BN71 BN1 BL71 BL1 R14 H71 F71 E69 E68 A66 A64 E5 C68 2 +VTT U1I VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 5 2 2 0.1U_0402_25V6 1 3 4 Title Compal Electronics, Inc. Auburndale(5/5)-GND/Bypass Size Document Number Custom NDU00_LA-6031P Date: Rev 1.0 M/B Monday, April 12, 2010 Sheet 5 9 of 45 4 3 +1.5V DDR3 SO-DIMM A Standard Type JDDRL1 DDR_A_D8 DDR_A_D9 D DDR_A_DQS#1 DDR_A_DQS1 close to JDDRL.1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 7 C 7 DDRA_CKE0 DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 7 7 DDRA_CLK0 DDRA_CLK0# DDR_A_MA10 7 DDR_A_BS0 7 7 DDR_A_W E# DDR_A_CAS# DDR_A_MA13 7 DDRA_SCS1# DDR_A_D32 DDR_A_D33 B DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 A DDR_A_D58 DDR_A_D59 1 C195 2 1 2 5 R65 10K_0402_5% 2 1 2.2U_0603_6.3V4Z C194 0.1U_0402_16V4Z R64 1 10K_0402_5% +3VS 2 +0.75VS CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 205 G1 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 G2 206 +1.5V 2 R58 7 DDR_A_DQS#[0..7] 1 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 M1 Circuit 7 DDR_A_DQS[0..7] DDR_A_DQS#0 DDR_A_DQS0 7 DDR_A_D[0..63] +1.5V R59 1K_0402_1% 7 DDR_A_DM[0..7] DDR_A_D6 DDR_A_D7 7 DDR_A_MA[0..15] R60 1K_0402_1% PS@ DDR_A_D12 DDR_A_D13 DDR_A_DM1 1 0_0402_5% +VREF_DQB +V_DDR3_DIMM_REF 2 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 2 R61 1 2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 1 0_0402_5% +VREF_DQA D R62 1K_0402_1% For S3 CPU power saving SM_DRAMRST# 5,11 2 DDR_A_DM0 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 1 1 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 2 2 DDR_A_D0 DDR_A_D1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 DDRA_CKE1 7 C DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDRA_CLK1 7 DDRA_CLK1# 7 DDR_A_BS1 7 DDR_A_RAS# 7 DDRA_SCS0# 7 DDRA_ODT0 7 +V_DDR3_DIMM_REF DDRA_ODT1 7 R63 1 0_0402_5% +DDR_VREF_CA_DIMMA DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 C175 2.2U_0603_6.3V4Z 1 C174 2.2U_0603_6.3V4Z C173 0.1U_0402_16V4Z +VREF_DQA 2 1 2 2 B Layout Note: Place near JDDRL 1 2 close to JDDRL.126 Reserve for cost down +1.5V DDR_A_DM6 DDR_A_D54 DDR_A_D55 1 + C192 330U_2.5V_M_R17 DDR_A_D60 DDR_A_D61 Layout Note: Place near JDDRL1.203 and 204 +1.5V @ C177 1 DDR_A_D52 DDR_A_D53 Layout Note: Place these 4 Caps near Command and Control signals of DIMMA +1.5V + +1.5V C176 0.1U_0402_16V4Z 5 +0.75VS 2 330U_B2_2.5VM_R15M C180 1 2 10U_0805_6.3V6M C178 1 2 0.1U_0402_16V4Z C182 1 2 10U_0805_6.3V6M C181 1 2 0.1U_0402_16V4Z C185 1 2 10U_0805_6.3V6M C184 1 2 0.1U_0402_16V4Z C188 1 2 10U_0805_6.3V6M C187 1 2 0.1U_0402_16V4Z C190 1 2 10U_0805_6.3V6M C193 1 2 10U_0805_6.3V6M C179 1 2 10U_0805_6.3V6M C183 2 1 1U_0402_6.3V4Z C186 2 1 1U_0402_6.3V4Z C189 2 1 1U_0402_6.3V4Z C191 2 1 1U_0402_6.3V4Z 2 DDR_A_DQS#7 DDR_A_DQS7 A DDR_A_D62 DDR_A_D63 +0.75VS PM_EXTTS# 5,11 PM_SMBDATA 11,12,16,26 PM_SMBCLK 11,12,16,26 Security Compal Electronics, Inc. Compal Secret Data Classification 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. @ FOX_AS0A626-U4SG-7H 4 3 2 Title DDRIII-SODIMM0 Size Document Number Custom Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet 1 10 of 45 B +1.5V C +1.5V 2 DDR_B_DM0 1 DDR_B_D2 DDR_B_D3 2 DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11 close to JDDRH.1 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25 DDR_B_DM3 DDR_B_D26 DDR_B_D27 7 2 7 DDRB_CKE0 DDR_B_BS2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 7 7 DDRB_CLK0 DDRB_CLK0# DDR_B_MA10 7 DDR_B_BS0 7 7 DDR_B_W E# DDR_B_CAS# DDR_B_MA13 7 DDRB_SCS1# DDR_B_D32 DDR_B_D33 3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35 DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 DDR_B_DM7 4 DDR_B_D58 DDR_B_D59 R67 1 10K_0402_5% +3VS 2.2U_0603_6.3V4Z 1 1 1 R68 2 10K_0402_5% 2 +0.75VS 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 205 C216 C217 2 2 0.1U_0402_16V4Z G1 @ A VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 G2 206 DDR_B_D4 DDR_B_D5 7 DDR_B_DQS#[0..7] DDR_B_DQS#0 DDR_B_DQS0 7 DDR_B_DQS[0..7] DDR_B_D6 DDR_B_D7 7 DDR_B_D[0..63] DDR_B_D12 DDR_B_D13 7 DDR_B_DM[0..7] 1 7 DDR_B_MA[0..15] DDR_B_DM1 SM_DRAMRST# 5,10 DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21 DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 DDRB_CKE1 7 2 DDR_B_MA15 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDRB_CLK1 7 DDRB_CLK1# 7 DDR_B_BS1 7 DDR_B_RAS# 7 DDRB_SCS0# 7 DDRB_ODT0 7 DDRB_ODT1 7 DDR_B_D36 DDR_B_D37 DDR_B_DM4 DDR_B_D38 DDR_B_D39 +V_DDR3_DIMM_REF R66 1 +DDR_VREF_CA_DIMMB 1 2 Layout Note: Place near JDDRH 2 0_0402_5% C199 0.1U_0402_16V4Z 1 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 C198 2.2U_0603_6.3V4Z 1 C197 0.1U_0402_16V4Z C196 2.2U_0603_6.3V4Z DDR_B_D0 DDR_B_D1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 E Standard Type DDR3 SO-DIMM B JDDRH1 +VREF_DQB D Layout Note: Place near JDDRH.203 and 204 3 +1.5V @ C200 1 close to JDDRH.126 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 +0.75VS 2 330U_B2_2.5VM_R15M 2 DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 Layout Note: Place these 4 Caps near Command and Control signals of DIMMB +1.5V 1 + A C203 1 2 10U_0805_6.3V6M C205 1 2 10U_0805_6.3V6M C208 1 2 10U_0805_6.3V6M C211 1 2 10U_0805_6.3V6M C213 1 2 10U_0805_6.3V6M C215 1 2 10U_0805_6.3V6M C201 1 2 0.1U_0402_16V4Z C204 1 2 0.1U_0402_16V4Z C207 1 2 0.1U_0402_16V4Z C210 1 2 0.1U_0402_16V4Z C202 1 2 10U_0805_6.3V6M C206 2 1 1U_0402_6.3V4Z C209 2 1 1U_0402_6.3V4Z C212 2 1 1U_0402_6.3V4Z C214 2 1 1U_0402_6.3V4Z DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 4 DDR_B_D62 DDR_B_D63 PM_EXTTS# 5,10 PM_SMBDATA 10,12,16,26 PM_SMBCLK 10,12,16,26 +0.75VS Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. FOX_AS0A626-U4RN-7F B C D Title DDRIII-SODIMM1 Size Document Number Custom Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet E 11 of 45 A B Clock Generator C D E F G +3VS_CK505 1 C221 2 2 2 10U_0805_10V4Z 0.1U_0402_16V4Z 2 C222 47P_0402_50V8J C223 C224 2 C225 C227 47P_0402_50V8J C226 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z FBMH1608HM601-T_0603 1 2 R73 0.1U_0402_16V4Z 1 1 1 C228 For SED C229 2 0.1U_0402_16V4Z R72 R70 R73 C230 no-mount C905 03/23 cap reserval. +3VS_CK505 Silego Have Internal Pull-Up +3VS_CK505 H_STP_CPU# +1.5VS_CK505 +1.05VS_CK505 16 16 1 R75 1 R77 CLK_DOT CLK_DOT# 2 0_0402_5% 2 0_0402_5% CLK_SATA CLK_SATA# 1 R81 1 R83 2 0_0402_5% 2 0_0402_5% CLK_SATA_R CLK_SATA#_R 16 PCH_CLK_DMI 16 PCH_CLK_DMI# 1 R85 1 R86 2 0_0402_5% 2 0_0402_5% PCH_CLK_DMI_R PCH_CLK_DMI#_R 16 16 2 1 2 3 4 5 6 7 8 VDD_USB_48 VSS_48M DOT_96 DOT_96# VDD_27 27MHZ 27MHZ_SS USB_48 SCL SDA REF_0/CPU_SEL VDD_REF XTAL_IN XTAL_OUT VSS_REF CKPWRGD/PD# 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 VSS_27M SATA SATA# VSS_SRC SRC_1 SRC_1# VDD_SRC_IO CPU_STOP# VDD_CPU CPU_0 CPU_0# VSS_CPU CPU_1 CPU_1# VDD_CPU_IO VDD_SRC 24 23 22 21 20 19 18 17 CLK_DOT_R CLK_DOT#_R H_STP_CPU# 33 10K_0402_5% 2 1 R74 SA00002XY00 U5 +3VS_CK505 CLK_ENABLE# 42 2 2 2 2 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z mount IDT 1 5 1 C904 +1.05VS_CK505 RTM 04/12 Q25B replace Q5B. Q25B 2N7002DW -T/R7_SOT363-6 IHDMI@ +1.5VS_CK505 1 CK_PW RGD 4 +1.5VS R69 10K_0402_5% +1.05VS_CK505 1 2 C220 For SED FBMH1608HM601-T_0603 10U_0805_10V4Z 0.1U_0402_16V4Z 1 2 R71 1 1 1 +1.05VS 1 1 C219 +3VS_CK505 3 C218 R72 @ 0_0603_5% 0.1U_0402_16V4Z 1 1 2 2 0.1U_0402_16V4Z 1 1 1 For SED FBMH1608HM601-T_0603 1 2 R70 1 For SED 2 For SED +3VS Clock gen H PM_SMBCLK 10,11,16,26 PM_SMBDATA 10,11,16,26 CLK_14M_PCH 16 CPU_SEL 1 2 33_0402_5% R76 CLK_XTAL_IN CLK_XTAL_OUT CLK_14M_PCH CK_PW RGD CLK_BCLK_R CLK_BCLK_R# R82 R84 1 1 10K_0402_5% 2 2 @C233 @C233 33P_0402_50V8K 2 0_0402_5% 2 0_0402_5% 1 CPU_SEL Y1 CLK_XTAL_IN 1 2 2 2 14.318MHZ_16PF_7A14300083 C231 C232 22P_0402_50V8J 22P_0402_50V8J 1 1 TGND 10K_0402_5% 2 +1.05VS 1 R80 2 Routing the trace at least 10mil RTM890N-631-GRT_QFN32_5X5 1 R78 IDT Have Internal Pull-Down CLK_BCLK 16 CLK_BCLK# 16 CLK_XTAL_OUT +1.5VS_CK505 @ CPU_SEL CPU_0/0# CPU_1/1# 0 (Default) 133MHz 133MHz 1 100MHz 100MHz For SED LCD/PANEL BD. Conn. 1.5A +LCDVDD_R 2 L3 1 0_0805_5% 1 +3VS C899 +LCD_INV 3 2 4 2 R94 100K_0402_5% C242 68P_0402_50V8J +LCD_VDD W=60mils Rated Current MAX:3000mA 1 1 2 2 1 0.1U_0402_16V4Z B+ 1 C243 0.1U_0402_25V6 18 LCD_TXCLK18 LCD_TXCLK+ 2 INVT_PW M_R 31 BKOFF# BKOFF# +3VS_LVDS_CAM @ 31 INVT_PW M 18 PCH_PW M 2 0_0402_5% 2 0_0402_5% L5 19 USB20_P11 1 19 USB20_N11 4 0_0402_5% 2 R89 @ +3VS INVT_PW M_R 1 R90 1 R91 1 2 2 USB20_P11_R 4 3 3 USB20_N11_R A D84 Issued Date 0_0402_5% 2 INT_MIC_CLK Deciphered Date 2 INT_MIC_DATA C D E 3 03/04 Pin24 +LCD_INV-->NC MGND4 MGND3 34 33 MGND2 MGND1 32 31 4 Compal Electronics, Inc. 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PACDN042Y3R_SOT23-3 Compal Secret Data 2010/04/12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 I-PEX_20143-030E-20F~D @ 3 1 0.1U_0402_16V4Z 1 2 C236 Security Classification W CM-2012-900T_0805 R97 1 W=20mils USB20_N11_R USB20_P11_R 29 INT_MIC_CLK 29 INT_MIC_DATA +3VS_LVDS_CAM 0_0603_5% 1 2 +LCD_INV R95 10K_0402_5% Reserve for EMI request 4 LCD_TXOUT1LCD_TXOUT1+ LCD_TXOUT2LCD_TXOUT2+ C244 680P_0402_50V7K Change to PCH control. C239 0.1U_0402_16V4Z 1 2 R96 1 18 18 18 18 1 Q4B 2N7002DW -T/R7_SOT363-6 C241 2 L4 2 1 FBMA-L11-201209-221LMA30T_0805 Q6 AO3413_SOT23 2 5 UMA_ENVDD 1 2 2 47K_0402_5% 1 C238 0.01U_0402_25V7K 1 3 1 1 R92 1 01/30 EMI request 0.1U_0402_16V7K 2 C237 G 2 +LCDVDD_R 680P_0402_50V7K 1 18 LCD_EDID_CLK 18 LCD_EDID_DATA C240 18 LCD_TXOUT018 LCD_TXOUT0+ 2 2 1 0.1U_0402_16V4Z W=60mils D 6 2 R88 100K_0402_5% Q4A 2N7002DW -T/R7_SOT363-6 18 2 C235 4.7U_0805_10V4Z +3VS S R87 150_0603_5% 1 C234 0.1U_0402_16V4Z 1 1 2 3 +3VS 2 +LCD_VDD JLVDS1 +LCD_VDD F Title Clock Generator (CK505)/ LVDS CONN Size Document Number Custom Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 G Sheet 12 of H 45 A B C D E CRT CONNECTOR 12/14 Fine tune pin define JP1 Pin1 Pin2 Pin8-->GND 12/21 pin 2,3 to RJ45_GND 12/22 Fine tune JP4 pin define 02/08 update connector footprint. JP1 12/21 transformer on board. RJ45_GND 1 1 18 18 18 18 27 27 RJ45_MIDI1+ RJ45_MIDI1- 27 27 RJ45_MIDI0+ RJ45_MIDI0- 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 UMA_CRT_CLK UMA_CRT_DATA UMA_CRT_VSYNC UMA_CRT_HSYNC 18 18 18 CRT_R CRT_G CRT_B +3VS +5VS C879 0.1U_0402_16V4Z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 GND1 20 GND2 1 01/28 EMI request. Change pin definition. 21 22 STARC_107K20-000000-G4 @ 12/17 EMI request. 2 2 3 3 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title CRT\TV\LVDS Size Document Number Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet E 13 of 45 5 4 3 2 1 +3VS ANALOG2 Function2 Function1 Swing Pre-Amp Slew-rate 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1 1 1 C246 C247 C248 C249 C250 C251 IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ Note C245 IHDMI@ 10U_0805_10V4Z Low Low Low 450 0 0 Low Low High 420 0 -3dB Shortest trace Low High Low 450 0 -3dB Shortest trace Low High High 460 0 -4dB Streamline PVT2 setting High Low Low 340 0 0 1 2 2 2 2 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 1 2 2 0.1U_0402_16V4Z C252 IHDMI@ 0.1U_0402_16V4Z D D Low High 400 2dB 0 Longest Trace High High Low 400 2dB 0 Longest Trace High High High 420 0 0 03/17 change to 3.9K, 04/12 EMI suggestion. 4 2 R116 10_0402_5% 4 2 2 3 @ 3 UMA_DVI_TXD1- 1 IHDMI@ L8 1 4 2 R119 10_0402_5% 1 4 2 2 3 @ 3 SDA_SOURCE 18 UMA_HDMI_CLK 9 SCL_SOURCE 1 IHDMI@ L9 1 1 4 2 R121 10_0402_5% 4 2 2 3 @ 3 HPD_SINK 30 DDC_EN 32 FUNCTION3 FUNCTION4 34 35 10 ANALOG2 13 14 OUT_D4+ OUT_D4- IN_D4+ IN_D4- 48 47 HDMI_TXC+ HDMI_TXC- IN_D3+ IN_D3- 45 44 HDMI_TX2+ HDMI_TX2HDMI_TX1+ HDMI_TX1HDMI_TX0+ HDMI_TX0- 19 20 OUT_D2+ OUT_D2- IN_D2+ IN_D2- 42 41 UMA_DVI_TXD0+ UMA_DVI_TXD0- 22 23 OUT_D1+ OUT_D1- IN_D1+ IN_D1- 39 38 1 5 12 18 24 27 31 36 37 43 GND GND GND GND GND GND GND GND GND GND THERMAL_PAD 49 OUT_D3+ OUT_D3- HDMI_R_D0HDMI_R_CK+ A HDMI_R_CKHDMI_SCLK HDMI_SDATA +HDMI_5V_OUT HDMI_HPD +3VS @ 2 2.2K_0402_5% IHDMI@ C253 1 C254 1 IHDMI@ C255 1 C256 1 IHDMI@ C257 1 C258 1 IHDMI@ C259 1 C260 1 C 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K IHDMI@ 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K IHDMI@ 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K IHDMI@ 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K IHDMI@ UMA_HDMI_TXC+ 18 UMA_HDMI_TXC- 18 UMA_HDMI_TX2+ 18 UMA_HDMI_TX2- 18 UMA_HDMI_TX1+ 18 UMA_HDMI_TX1- 18 UMA_HDMI_TX0+ 18 UMA_HDMI_TX0- 18 B ASM1442 QFN_48P_7X7 IHDMI@ +3VS Add circuit to control OE# pin for save power consumption R98 +3VS 2 1 PCH_HDMI_HPD 10K_0402_5% @ R124 10K_0402_5% IHDMI@ R99 100K_0402_5% @ 1 OE# 12/15 Vendor recommend +5VS F1 IHDMI@ PMEG2010AEH_SOD123 IHDMI@ 2 1 2 1 1.1A_6V_MINISMDC110F-2 D4 1 20 21 22 23 2 Q25A 2N7002DW -T/R7_SOT363-6 IHDMI@ 04/12 Q25B replace Q5B page 12. +HDMI_5V_OUT 2010/04/12 Issued Date 3 04/12 R1476 remove. HDMI_HPD 2 R123 100K_0402_5% @ Deciphered Date 2 C262 0.1U_0402_16V4Z 1 A Compal Electronics, Inc. 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 12/14 modify HPD circuit. C263 IHDMI@ 0.1U_0402_16V4Z Compal Secret Data Security Classification SUYIN_100042GR019M23BZR @ 5 0_0402_5% @ 0_0402_5% @ 0_0402_5% IHDMI@ 0_0402_5% @ 1 HDMI_R_D1HDMI_R_D0+ 1 1 2 2 1 HDMI_R_D2HDMI_R_D1+ 2 2 1 1 HDMI_R_D2- JHDMI1 D2+ D2_shield D2D1+ D1_shield D1D0+ D0_shield GND0 D0GND1 CK+ GND2 CK_shield GND3 CKCEC Reserved SCL SDA DDC/CEC_GND +5V HP_DET R107 R109 R111 R113 HDMI_HPD connect to U10.30 R1473 UMA_DVI_TXD1+ UMA_DVI_TXD1- HDMI_R_D1+ <01/27 update HDMI Connector > 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 @ 2 1 +3VS 12/14 R103 10K_0402_5% R105 2 1 4.7K_0402_5% +3VS IHDMI@ 1 HDMI Connector HDMI_R_D2+ HDMI_HPD 12/15 Vendor recommend 16 17 HDMI_R_D0+ W CM-2012-900T_0805 HDMI_R_D2+ 1 2 R122 IHDMI@ 10_0402_5% UMA_DVI_TXD2+ HDMI_SDATA UMA_DVI_TXD2+ UMA_DVI_TXD2- B UMA_DVI_TXD2- 29 HDMI_R_D1- W CM-2012-900T_0805 1 2 R120 IHDMI@ 10_0402_5% UMA_DVI_TXD1+ +3VS SDA_SINK +HDMI_5V_OUT 1 IHDMI@ 2 R101 2.2K_0402_5% 1 IHDMI@ 2 R102 2.2K_0402_5% HPD_SOURCE 8 12/15 Vendor recommend for deep color mode. W CM-2012-900T_0805 1 2 R118 IHDMI@ 10_0402_5% UMA_DVI_TXD0+ HDMI_R_D0- 28 ANALOG1(REXT) 18 UMA_HDMI_DATA R117 1 2 @ 0_0402_5% 2 1 R1472 4.7K_0402_5% UMA_DVI_TXC+ IHDMI@ UMA_DVI_TXC- SCL_SINK 2 1 IHDMI@ L7 1 1 FUNCTION1 FUCNTION2 2 @ 1 R100 10K_0402_5% HDMI_SCLK 1 UMA_DVI_TXD0- HDMI_R_CK+ 1 1 1 1 OE# 2 3 @ 3 R106 R108 R110 R112 25 6 2 W CM-2012-900T_0805 1 2 R115 10_0402_5% IHDMI@ UMA_DVI_TXC+ C 4 2 HDMI_R_CK- VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V 2 4 2 R104 10_0402_5% OE* 2 11 15 21 26 33 40 46 IHDMI@ IHDMI@ 0_0402_5% 2 3 0_0402_5% 2 4 2 @ 0_0402_5% 2 @ 0_0402_5% 2 R114 1 6 3.6K_0402_1% IHDMI@ common design 7 3.6K 18 PCH_HDMI_HPD +3VS 1 IHDMI@ L6 1 1 12/14 RV R100 +3VS High UMA_DVI_TXC- U6 2 Title HDMI Connector Size Document Number Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet 1 14 of 45 5 4 OSC 4 NC OSC 1 32.768KHZ_12.5PF_Q13MC14610002 2 2 1U_0402_6.3V4Z 2 C267 B13 D13 RTCX1 RTCX2 PCH_RTCRST# C14 RTCRST# PCH_SRTCRST# D17 SRTCRST# SM_INTRUDER# 2 1M_0402_5% PCH_INTVRMEN 2 330K_0402_5% A16 INTRUDER# 1 18P_0402_50V8J +RTCVCC Integrated SUS 1.05V VRM Enable 1 R129 1 R130 High - Enable Internal VRs PCH_INTVRMEN (must be always pulled high) HDA_SYNC This signal has a weak internal pull down. H=>On Die PLL is supplied by 1.5V Die PLL is supplied by 1.8V U8A PCH_RTCX1 PCH_RTCX2 D A14 INTVRMEN AZ_BITCLK A30 HDA_BCLK AZ_SYNC D29 HDA_SYNC PCH_SPKR 18,29 PCH_SPKR P1 AZ_RST# *L=>On HDA_SDO HDA_RST# HDA_SDIN0 F30 HDA_SDIN1 E32 HDA_SDIN2 F32 HDA_SDIN3 B29 HDA_SDO H32 HDA_DOCK_EN# / GPIO33 J30 HDA_DOCK_RST# / GPIO13 PCH_JTAG_TCK M3 JTAG_TCK PCH_JTAG_TMS K3 JTAG_TMS PCH_JTAG_TDI K1 JTAG_TDI PCH_JTAG_TDO J2 JTAG_TDO PCH_JTAG_RST# J4 TRST# Flash Descriptor Security Overide Low = Enabled High = Disabled HDA_DOCK_EN# AZ_SDOUT * 2 31 PW RME_CTRL# 29 AZ_SYNC_HD R132 1 2 33_0402_5% AZ_BITCLK R133 1 2 33_0402_5% AZ_SYNC 29 AZ_RST_HD# R134 1 2 33_0402_5% AZ_RST# 29 AZ_SDOUT_HD R135 1 2 33_0402_5% AZ_SDOUT R131 1K_0402_5% @ CR_CPPE# 1 29 AZ_BITCLK_HD 28 D33 B33 C32 A32 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 FWH4 / LFRAME# C34 LPC_FRAME# 26,31,32 LDRQ0# LDRQ1# / GPIO23 A34 F34 SERIRQ AB9 SPKR G30 This signal has a weak internal pull down. This signal can't PU LAD0 LAD1 LAD2 LAD3 FWH0 / FWH1 / FWH2 / FWH3 / C30 29 AZ_SDIN0_HD C 1 T143 PAD 1 R128 2 10K_0402_5% SERIRQ SATA0RXN SATA0RXP SATA0TXN SATA0TXP AK7 AK6 AK11 AK9 SATA1RXN SATA1RXP SATA1TXN SATA1TXP AH6 AH5 AH9 AH8 SATA2RXN SATA2RXP SATA2TXN SATA2TXP AF11 AF9 AF7 AF6 SATA3RXN SATA3RXP SATA3TXN SATA3TXP AH3 AH1 AF3 AF1 SATA4RXN SATA4RXP SATA4TXN SATA4TXP AD9 AD8 AD6 AD5 SATA5RXN SATA5RXP SATA5TXN SATA5TXP AD3 AD1 AB3 AB1 SATAICOMPO AF16 SATAICOMPI AF15 26,31,32 26,31,32 26,31,32 26,31,32 D +3VS SERIRQ 31,32 SATA_PRX_C_DTX_N1 24 SATA_PRX_C_DTX_P1 24 SATA_PTX_DRX_N1 24 SATA_PTX_DRX_P1 24 1ST HDD Desktop Only C SATA_PRX_C_DTX_N5 24 SATA_PRX_C_DTX_P5 24 SATA_PTX_DRX_N5 24 SATA_PTX_DRX_P5 24 eSATA +3VS SATAICOMP 1 R136 2 37.4_0402_1% +1.05VS Internal: Pull down 20k ITPM Enabled B SPI_MOSI 1 SPI_CLK PCH_SPI_CS0# AV3 SPI_CS0# AY3 SPI_CS1# 12/16 EMC request +3VS High = Enabled Low = Disabled (Default) 2 R140 +3VALW +3VALW @ 1PCH_SPI_MOSI 1K_0402_5% PCH_SPI_MISO AY1 SPI_MOSI AV1 SPI_MISO SATALED# T3 SATA_LED# SATA0GP / GPIO21 Y9 CR_W AKE# SATA1GP / GPIO19 V1 GPIO19 CR_W AKE# R138 2 1 10K_0402_5% GPIO19 R139 1 2 10K_0402_5% SATA_LED# 33 CR_W AKE# 28 D5 BAS40-04_SOT23-3 +RTCVCC U9 2 PCH_SPI_CS0# VCC 3 W 7 HOLD 1 S PCH_SPI_CLK 6 C PCH_SPI_MOSI 5 D PCH_JTAG_TCK 2 51_0402_5% 1 R150 8 VSS 4 for EMI request PCH_SPI_CLK 1 1 1 @ R148 10K_0402_5% 2 Q 2 PCH_SPI_MISO PCH Pin PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TCK PCH_JTAG_RST# RefDes R358 R535 R355 R354 R536 R537 R156 R643 R353 5 R149 @ 10_0402_5% 2/8 change back to original.(Lion Wang) del D86 and R1494. MX25L3205DM2I-12G SO8 @ C270 10P_0402_50V8J 06/01 change R125 from 4.7K to 51 ohm PCH JTAG Enable ES1 ES2 No Install 200ohm No Install 100ohm 200ohm 200ohm 100ohm 100ohm 200ohm 200ohm 100ohm 100ohm 51ohm 51ohm 20Kohm 20Kohm 10Kohm 10Kohm C269 0.1U_0402_16V4Z 2 2 2 1 @ R147 100_0402_5% 4MB C268 0.1U_0402_16V4Z +CHGRTC 1 1 PCH_JTAG_RST# 2 @ R146 100_0402_5% PCH_JTAG_TDI 2 PCH_JTAG_TDO +3VS @ R144 20K_0402_5% @ R143 200_0402_5% 1 1 1 @ R142 200_0402_5% 2 @ R145 100_0402_5% A 2 1 PCH_JTAG_TMS 2 1 2 @ R141 200_0402_5% B +RTCBATT IBEXPEAK-M QV20 A0_FCBGA1071 HM55@ +3VALW 2 10K_0402_5% 3 +3VALW BA2 R137 1 1 C388 33P_0402_50V8K PCH_SPI_CLK SPI AZ_BITCLK_HD 2 SATA_LED# 2 1 2PCH_SRTCRST# 1 R127 20K_0402_1% 1 C266 NC 2 LPC J1 3 SATA iME Setting. Y2 2 1U_0402_6.3V4Z RTC 2 1 C265 IHDA 1 R126 10M_0402_5% 2 1 1 2PCH_RTCRST# R125 20K_0402_1% 2 JTAG CMOS Setting, near DDR Door JCMOS1 +RTCVCC 3 C264 18P_0402_50V8J 2 1 1 2/1 Add R1494 D86 (EMI) A 2 PCH JTAG Disable (Default) ES1 ES2 No Install No Install No Install No Install No Install No Install No Install No Install 20Kohm No Install 10Kohm No Install 51ohm 51ohm No Install No Install No Install No Install Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title PCH-SPI/SATA/LPC/RTC/HDA Size B Date: Document Number Rev 1.0 NDU00_LA-6031P M/B Monday, April 12, 2010 Sheet 1 15 of 45 4 3 2 +3VALW 1 2 R151 2 R152 +3VS 1 2.2K_0402_5% 1 2.2K_0402_5% Q17B PCH_SMBDATA R153 R154 5 5 PM_SMBDATA 10,11,12,26 2N7002DW -T/R7_SOT363-6 Q17A PCH_SMBCLK 4 2 3 4.7K_0402_5% 4.7K_0402_5% 6 1 PM_SMBCLK 10,11,12,26 2N7002DW -T/R7_SOT363-6 U8B D D 10/19 Change pin assignment for common design PERN3 PERP3 PETN3 PETP3 For 8 pin SIM card For Card Reader 26 26 26 26 PCIE_PRX_W W ANTX_N4 PCIE_PRX_W W ANTX_P4 PCIE_PTX_C_W W ANRX_N4 PCIE_PTX_C_W W ANRX_P4 28 28 28 28 C897 2 C898 2 PCIE_PRX_C_CRTX_N5 PCIE_PRX_C_CRTX_P5 PCIE_PTX_C_CRRX_N5 PCIE_PTX_C_CRRX_P5 1 0.1U_0402_16V7K SIM8@ 1 0.1U_0402_16V7K SIM8@ C336 1 C868 1 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K BA32 BB32 PCIE_PTX_W W ANRX_N4BD32 PCIE_PTX_W W ANRX_P4BE32 PERN4 PERP4 PETN4 PETP4 BF33 BH33 BG32 BJ32 PERN5 PERP5 PETN5 PETP5 BA34 AW34 BC34 BD34 PERN6 PERP6 PETN6 PETP6 AT34 AU34 AU36 AV36 PERN7 PERP7 PETN7 PETP7 BG34 BJ34 BG36 BJ36 PERN8 PERP8 PETN8 PETP8 AK48 AK47 CLKOUT_PCIE0N CLKOUT_PCIE0P PCIE_PTX_CRRX_N5 PCIE_PTX_CRRX_P5 C NC 27 27 LAN CLK_LAN# CLK_LAN 27 CLKREQ_LAN# +3VS 1 10K_0402_5% 2 R168 CLKREQ_NEW # 1 10K_0402_5% 2 R169 CLKREQ_W LAN# 26 26 WLAN CLK_W LAN# CLK_W LAN 26 CLKREQ_W LAN# R170 0_0402_5% CLK_LAN#_R 1 2 CLK_LAN_R 1 2 R171 0_0402_5% CLKREQ_LAN# AM47 AM48 CLKOUT_PCIE2N CLKOUT_PCIE2P +3VALW 2 R173 CLKREQ_LAN# 1 10K_0402_5% 2 R174 CLKREQ_UW B# 1 10K_0402_5% 2 R175 CLKREQ_CR# 1 10K_0402_5% 2 R176 PCH_GPIO44 1 10K_0402_5% 2 R178 PCH_GPIO56 R1492 1 1 R1493 For 8 pin SIM card 26 26 CLK_W W AN# CLK_W W AN 26 CLKREQ_UW B# Card Reader 28 28 CLK_CR# CLK_CR PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P B 1 10K_0402_5% P9 R166 0_0402_5% CLK_W LAN#_R AM43 1 2 CLK_W LAN_R 1 2 AM45 R167 0_0402_5% CLKREQ_W LAN# U4 R1219 1 1 R1220 CLKREQ_CR# CLKREQ_NEW # N4 0_0402_5% 2 CLK_W W AN#_R 2 CLK_W W AN_R 0_0402_5% CLKREQ_UW B# AH42 AH41 0_0402_5% CLK_CR#_R 2 CLK_CR_R 2 0_0402_5% CLKREQ_CR# A8 AM51 AM53 M9 AJ50 AJ52 PCH_GPIO44 H6 AK53 AK51 PCH_GPIO56 P13 PCIECLKRQ1# / GPIO18 PCH_SMBDATA SML0CLK C6 PCH_SMLCLK0 SML0DATA G8 PCH_SMLDATA0 SML1ALERT# / GPIO74 PCH_GPIO74 SML1CLK / GPIO58 E10 PCH_SMLCLK1 SML1DATA / GPIO75 G12 PCH_SMLDATA1 CL_CLK1 T13 CL_DATA1 T11 CL_RST1# T9 PEG_A_CLKRQ# / GPIO47 H1 CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P AT1 AT3 CLKOUT_PCIE4N CLKOUT_PCIE4P PCIECLKRQ4# / GPIO26 @ CLKREQ_PEG# 1 R164 2 10K_0402_5% 1 R165 2 10K_0402_5% CLK_BCLK# 12 CLK_BCLK 12 CLKIN_DOT_96N CLKIN_DOT_96P F18 E18 CLK_DOT# 12 CLK_DOT 12 AH13 AH12 CLK_SATA# 12 CLK_SATA 12 P41 CLK_14M_PCH_R 1 2 R1445 33_0402_5% J42 XTAL25_IN XTAL25_OUT AH51 AH53 XCLK_RCOMP AF38 CLKOUTFLEX0 / GPIO64 T45 CLKOUTFLEX1 / GPIO65 P43 CLKOUTFLEX2 / GPIO66 T42 CLKOUTFLEX3 / GPIO67 N50 EC_SMB_CK2 31,32 +3VALW 4.7K_0402_5% 4.7K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2 2 2 2 2 1 1 1 1 1 R159 R160 R161 R162 R163 C FROM CLK GEN FOR: 133/100/96/14.318 MHZ B R172 2 PCH_X1 XCLK_RCOMP 1 2 R177 90.9_0402_1% 2 1 PCH_X2 1 25MHZ_20PF_7A25000012 1 27P_0402_50V8J 2 2 C275 PCH_X1 PCH_X2 1M_0402_5% 1 Y3 CLK_14M_PCH 12 CLK_PCILOOP 19 C276 27P_0402_50V8J +1.05VS C277 @ 0_0402_5% Note: Stuff 0 ohm if 25MHz crystal un-stuff for EMI request 12/18 EMC Remove R179 and C278 12/18 EMC request change value CLK_14M_PCH 1 R180 2 10_0402_5% 2 2010/04/12 Issued Date Deciphered Date Compal Electronics, Inc. 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 A 1 10P_0402_50V8J Compal Secret Data Security Classification 4 1 +3VALW C279 5 EC_SMB_DA2 31,32 CLK_PEG# 5 CLK_PEG 5 IBEXPEAK-M QV20 A0_FCBGA1071 HM55@ A 4 2N7002DW -T/R7_SOT363-6 PCH_SMLCLK0 PCH_SMLDATA0 PCH_GPIO60 PCH_GPIO74 EC_LID_OUT# AP3 AP1 CLKIN_PCILOOPBACK 6 4.7K_0402_5% 4.7K_0402_5% 2N7002DW -T/R7_SOT363-6 CLKIN_BCLK_N CLKIN_BCLK_P REFCLK14IN R157 R158 3 PCH_SMLCLK1 PCH_CLK_DMI# 12 PCH_CLK_DMI 12 CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P Q19B PCH_SMLDATA1 AW24 BA24 CLKIN_DMI_N CLKIN_DMI_P +3VS 1 2.2K_0402_5% 1 2.2K_0402_5% AD43 AD45 AN4 AN2 CLKOUT_PCIE5N CLKOUT_PCIE5P 2 R155 2 R156 +3VALW M14 CLKOUT_DMI_N CLKOUT_DMI_P PCIECLKRQ3# / GPIO25 PEG_B_CLKRQ# / GPIO56 C8 EC_LID_OUT# 31 Q19A CLKOUT_PCIE3N CLKOUT_PCIE3P CLKOUT_PEG_B_N CLKOUT_PEG_B_P PCH_SMBCLK PCH_GPIO60 CLKOUT_PEG_A_N CLKOUT_PEG_A_P PCIECLKRQ2# / GPIO20 PCIECLKRQ5# / GPIO44 H14 J14 SML0ALERT# / GPIO60 SMBus 01/27 Reserve for 8 pin SIM card. EC_LID_OUT# 5 AU30 AT30 AU32 AV32 SMBDATA B9 2 PERN2 PERP2 PETN2 PETP2 SMBCLK Link 1 0.1U_0402_16V7K W LAN@ 1 0.1U_0402_16V7K W LAN@ AW30 BA30 PCIE_PTX_W LANRX_N2 BC30 PCIE_PTX_W LANRX_P2 BD30 SMBALERT# / GPIO11 Controller C271 2 C272 2 PERN1 PERP1 PETN1 PETP1 PEG PCIE_PRX_W LANTX_N2 PCIE_PRX_W LANTX_P2 PCIE_PTX_C_W LANRX_N2 PCIE_PTX_C_W LANRX_P2 1 0.1U_0402_16V7K 1 0.1U_0402_16V7K PCI-E* C273 2 C274 2 From CLK BUFFER 26 26 26 26 For WLAN PCIE_PRX_C_LANTX_N1 PCIE_PRX_C_LANTX_P1 PCIE_PTX_C_LANRX_N1 PCIE_PTX_C_LANRX_P1 Clock Flex 27 27 27 27 For LAN BG30 BJ30 PCIE_PTX_LANRX_N1 BF29 PCIE_PTX_LANRX_P1 BH29 2 Title CLK/PCIE/SMBUS Size B Date: Document Number Rev 1.0 NDU00_LA-6031P M/B Monday, April 12, 2010 Sheet 1 16 of 45 5 4 3 2 1 D D PCH_SUSPW RDN 2 10K_0402_5% PCH_LOW _BAT# 2 10K_0402_5% IBEX_RI# 2 10K_0402_5% BC24 BJ22 AW20 BJ20 DMI0RXN DMI1RXN DMI2RXN DMI3RXN 6 6 6 6 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 BD24 BG22 BA20 BG20 DMI0RXP DMI1RXP DMI2RXP DMI3RXP 6 6 6 6 DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 BE22 BF21 BD20 BE18 DMI0TXN DMI1TXN DMI2TXN DMI3TXN 6 6 6 6 DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3 BD22 BH21 BC20 BD18 DMI0TXP DMI1TXP DMI2TXP DMI3TXP 1 R184 +1.05VS PM_PW ROK 1 10K_0402_5% PW ROK 1 10K_0402_5% LAN_RST# 1 10K_0402_5% 2 R185 2 R186 2 R187 C BH25 BF25 Close to PCH @ 2 0_0402_5% DMI_ZCOMP XDP_DBRESET# 5 XDP_DBRESET# 5 31,42 T6 VGATE M6 PW ROK B17 SYS_RESET# 4 O PWROK IN2 SN74AHC1G08DCKR_SC70-5 3 2 1 R191 2 0_0402_5% LAN_RST# K5 A10 D9 5 DRAMPW ROK PCH_RSMRST# C16 MEPWROK LAN_RST# DRAMPWROK RSMRST# B 31 31 PCH_SUSPW RDN @ 1 2 R192 0_0402_5% 5 PM_PBTN_OUT# PCH_SUSPW RDN 1 R193 31,33,35 2 330K_0402_5% D6 1 2 ACIN M1 SUS_PWR_DN_ACK / GPIO30 P5 PWRBTN# PCH_ACIN P7 ACPRESENT / GPIO31 PCH_LOW _BAT# A6 BATLOW# / GPIO72 PBTN_OUT# +3VALW 6 6 6 6 6 6 6 6 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 6 6 6 6 6 6 6 6 FDI_INT BJ14 FDI_INT FDI_FSYNC0 BF13 FDI_FSYNC0 FDI_FSYNC1 BH13 FDI_FSYNC1 6 FDI_LSYNC0 BJ12 FDI_LSYNC0 6 FDI_LSYNC1 BG14 FDI_LSYNC1 6 WAKE# 6 6 EC_SW I# J12 CLKRUN# / GPIO32 Y1 SUS_STAT# / GPIO61 P8 SYS_PWROK P VGATE FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 C 1 R188 +3VS 0.1U_0402_16V4Z 1 2 C280 U12 1 IN1 PM_PW ROK FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12 DMI_IRCOMP G 31 DMI_COMP 2 49.9_0402_1% System Power Management 1 R181 1 R182 1 R183 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 FDI +3VALW 6 6 6 6 DMI U8C PM_CLKRUN# 2 R189 2 R190 2 1 10K_0402_5% +3VALW 1 +3VS 8.2K_0402_5% SUS_STAT# R1505 1 0_0402_5% EC_SW I# EC_SW I# 27 PADT4 PADT4 SUS_CLK SUSCLK / GPIO62 F3 SLP_S5# / GPIO63 E4 PM_SLP_S5# 31 SLP_S4# H7 PM_SLP_S4# 31 SLP_S3# P12 PM_SLP_S3# 31 SLP_M# K8 TP23 N2 SUS_CLK 31 03/10 for EC Y4 crystal. 03/22 damping for EMI. B PMSYNCH BJ10 PMSYNCH 5 CH751H-40PT_SOD323-2 IBEX_RI# F14 RI# SLP_LAN# / GPIO29 F6 IBEXPEAK-M QV20 A0_FCBGA1071 HM55@ +3VALW 2 1K_0402_5% @1 2 R195 Q18 1 E MMBT3906_SOT23-3 RSMRST# circuit 4 2 2 1 R197 4.7K_0402_5% D7A BAV99DW -7_SOT363 2 D37 1 PCH_RSMRST# CH751H-40PT_SOD323-2 D86 @ 1 2 POK 36,38 CH751H-40PT_SOD323-2 D7B BAV99DW -7_SOT363 6 A 1 2 B +3VALW PW ROK PCH_RSMRST# 2 1 R196 10K_0402_5% C 3 5 0_0402_5% 31 EC_RSMRST# A 03/24 add +3VALW Power OK. 1 2 R198 2.2K_0402_5% Compal Electronics, Inc. Compal Secret Data Security Classification 3 1 R194 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH-DMI/FDI/PWM Size B Date: Document Number Rev 1.0 NDU00_LA-6031P M/B Monday, April 12, 2010 Sheet 1 17 of 45 5 4 3 2 1 U8D 2 R203 2 R204 LCD_EDID_DATA 1 4.7K_0402_5% 1 R202 C 2 R208 UMA_CRT_CLK 1 2.2K_0402_5% 2 R209 UMA_CRT_DATA 1 2.2K_0402_5% 1 R210 1 R211 1 R212 2 150_0402_1% 2 150_0402_1% 2 150_0402_1% LVDSA_CLK# LVDSA_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 12 LCD_TXOUT0+ 12 LCD_TXOUT1+ 12 LCD_TXOUT2+ BB48 BA50 AY49 AV48 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 AP48 AP47 LVDSB_CLK# LVDSB_CLK AY53 AT49 AU52 AT53 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 AY51 AT48 AU50 AT51 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 AA52 AB53 AD53 CRT_BLUE CRT_GREEN CRT_RED V51 V53 CRT_DDC_CLK CRT_DDC_DATA 13 UMA_CRT_HSYNC 13 UMA_CRT_VSYNC Y53 Y51 CRT_HSYNC CRT_VSYNC 1CRT_IREF 1K_0402_1% AD48 AB51 PCH Strap Pin DAC_IREF CRT_IRTN DDPB_AUXN DDPB_AUXP DDPB_HPD BG44 BJ44 AU38 DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38 D R205 2 IHDMI@ 100K_0402_5% 1 +3VS R206 2.2K_0402_5% IHDMI@ R207 2.2K_0402_5% IHDMI@ DDPC_CTRLCLK DDPC_CTRLDATA Y49 AB49 UMA_HDMI_CLK 14 UMA_HDMI_DATA 14 DDPC_AUXN DDPC_AUXP DDPC_HPD BE44 BD44 AV40 PCH_HDMI_HPD 14 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36 UMA_HDMI_TX2UMA_HDMI_TX2+ UMA_HDMI_TX1UMA_HDMI_TX1+ UMA_HDMI_TX0UMA_HDMI_TX0+ UMA_HDMI_TXCUMA_HDMI_TXC+ 14 14 14 14 14 14 14 14 DDPD_CTRLCLK DDPD_CTRLDATA 13 UMA_CRT_CLK 13 UMA_CRT_DATA 2 R214 T51 T53 03/22 common design. LVD_VREFH LVD_VREFL BB47 BA52 AY48 AV47 UMA_CRT_G BF45 BH45 SDVO_CTRLCLK SDVO_CTRLDATA 12 LCD_TXOUT012 LCD_TXOUT112 LCD_TXOUT2- UMA_CRT_B UMA_CRT_R LVD_IBG LVD_VBG AV53 AV51 UMA_CRT_B UMA_CRT_G UMA_CRT_R SDVO_INTN SDVO_INTP L_CTRL_CLK L_CTRL_DATA 12 LCD_TXCLK12 LCD_TXCLK+ +3VS BJ48 BG48 1 D SDVO_STALLN SDVO_STALLP L_DDC_CLK L_DDC_DATA 1 +3VS LCD_EDID_CLK 1 4.7K_0402_5% LCTL_CLK 2 AB46 2 10K_0402_5% LCTL_DATA V48 10K_0402_5% LVDS_IBG 2 AP39 2.37K_0402_1% AP41 T6 PAD AT43 AT42 1 1 R200 R201 BJ46 BG46 2 +3VS L_BKLTCTL AB48 Y45 12 LCD_EDID_CLK 12 LCD_EDID_DATA SDVO_TVCLKINN SDVO_TVCLKINP 2 PCH_PW M L_BKLTEN L_VDD_EN Digital Display Interface 12 T48 T47 Y48 LVDS 31 UMA_ENBKL 12 UMA_ENVDD UMA_ENBKL 2 100K_0402_5% HDMI C Danbury Technology Enabled NV_ALE U50 U52 DDPD_AUXN DDPD_AUXP DDPD_HPD BC46 BD46 AT38 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36 CRT 1 R199 R213 2 IHDMI@ 100K_0402_5% 1 Check list: 8.2k PU 03/22 common design. 2 R218 @ 1 1K_0402_5% NV_ALE NV_ALE 19 2 R219 @ NV_CLE 1 1K_0402_5% NV_CLE 19 Internal: Pull down 20k During Reset: Low Initial: Low IBEXPEAK-M QV20 A0_FCBGA1071 HM55@ Internal: Pull down 20k During Reset: HZ Initial: Low Check list: 10k PU @ PCH_SPKR 1 2 R215 1K_0402_5% 1K_0402_5% 2 @ 1 R216 PCI_GNT#0 1K_0402_5% 2 @ 1 R217 PCI_GNT#1 2 R220 @ 1 1K_0402_5% Low= Disable High= Enable NV_CLE Low= Set to Vss (Default) High= Set to Vcc B PCH_SPKR 15,29 Internal: Pull up 20k During Reset: High Initial: High Check list: 4.7k PD DMI Termination Voltage NO REBOOT Strap PCH_SPKR Internal: Pull down 20k During Reset: Low Initial: Low +1.8VS_PCH_NAND +3VS B High = Enabled Low = Disabled (Default) PCI_GNT#0 19 PCI_GNT#1 19 Internal: Pull up 20k During Reset: High Initial: High PCI_GNT#3 PCI_GNT#3 19 Internal: Pull up 20k During Reset: High Initial: High Boot BIOS Strap PCI_GNT#1 PCI_GNT#0 0 0 1 1 0 1 0 1 modify..... Boot BIOS Loaction LPC (Default) Reserved (NAND) PCI SPI UMA_CRT_B L41 1 2 NBQ100505T-800Y-N_2P UMA_CRT_G L42 1 2 NBQ100505T-800Y-N_2P UMA_CRT_R L43 1 2 NBQ100505T-800Y-N_2P 13 13 CRT_R 13 1 2 A16 Swap Override Strap PCI_GNT#3 CRT_B CRT_G C900 2.2P_0402_50V8C 1 2 1 C901 2.2P_0402_50V8C 2 C902 2.2P_0402_50V8C Low= A16 swap override Enable High= A16 swap override Disable 2/2 Add L41 L42 L43 C900 C901 C902 for EMI request A A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH-CRT/LVDS/HDMI Size Document Number Custom Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet 1 18 of 45 4 3 1 2 3 4 PCI_STOP# PCI_PIRQE# PCI_PIRQC# PCI_PIRQG# 8 7 6 5 8.2K_0804_8P4R_5% GNT2#: Not pull low, internal pull up 20K 18 18 PCI_GNT#0 PCI_GNT#1 18 PCI_GNT#3 +3VS RP4 1 2 3 4 B 8 7 6 5 PCI_REQ#3 PCI_PIRQF# PCI_PIRQB# PCI_REQ#0 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# G38 H51 B37 A44 PIRQA# PIRQB# PIRQC# PIRQD# PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3 F51 A46 B45 M53 REQ0# REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 F48 K45 F36 H53 GNT0# GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# B41 K53 A36 A48 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 PCI_SERR# PCI_PERR# E44 E50 SERR# PERR# PCI_IRDY# PCI_DEVSEL# PCI_FRAME# A42 H44 F46 C46 IRDY# PAR DEVSEL# FRAME# PCI_PLOCK# D49 PLOCK# PCI_STOP# PCI_TRDY# D41 C48 STOP# TRDY# M7 PME# D5 PLTRST# K6 T37 PAD 8.2K_0804_8P4R_5% +3VS RP5 1 2 3 4 8 7 6 5 PCI_DEVSEL# PCI_PERR# PCI_SERR# PCI_PLOCK# 8.2K_0804_8P4R_5% 5,26,27,28,31,32 32 CLK_PCI_DDR 31 CLK_PCI_EC 16 CLK_PCILOOP PLT_RST# R226 22_0402_5% R227 22_0402_5% R228 22_0402_5% 2 2 2 1 1 1 CLK_SIO CLK_EC CLK_PCH N52 P53 P46 P51 P48 2 0_0402_5% PCIRST# AU2 NV_RB# AV7 NV_WR#0_RE# NV_WR#1_RE# AY8 AY5 NV_WE#_CK0 NV_WE#_CK1 CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 @ 1 2 R222 32.4_0402_1% U13 H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24 USBRBIAS# B25 USBRBIAS D25 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 N16 J16 F16 L16 E14 G16 F12 T15 @ 1 IN1 4 5 BUF_PLT_RST# O USB20_N0 USB20_P0 USB20_N1 USB20_P1 30 30 30 30 USB-RIGHT1 PLT_RST# 2 IN2 AV11 BF5 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P C 5 NV_RCOMP P C/BE0# C/BE1# C/BE2# C/BE3# RP3 1 R221 NV_ALE 18 NV_CLE 18 +3VS J50 G42 H47 G34 8.2K_0804_8P4R_5% BD3 AY6 G PCI_PIRQH# PCI_TRDY# PCI_FRAME# PCI_PIRQA# 8 7 6 5 NV_ALE NV_CLE SN74AHC1G08DCKR_SC70-5 3 RP2 1 2 3 4 C AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6 R223 100K_0402_5% @ USB-RIGHT2 USB20_N3 24 USB20_P3 24 eSATA-USB USB20_N5 25 USB20_P5 25 BT +3VALW 2 8.2K_0804_8P4R_5% NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 D R1421 330K_0402_5% 1 PCI_REQ#1 PCI_REQ#2 PCI_PIRQD# PCI_IRDY# 8 7 6 5 NV_DQS0 NV_DQS1 AV9 BG8 1 RP1 1 2 3 4 AY9 BD1 AP15 BD8 1 2 +3VS 2 NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 USB D NVRAM U8E H40 AD0 N34 AD1 C44 AD2 A38 AD3 C36 AD4 J34 AD5 A40 AD6 D45 AD7 E36 AD8 H48 AD9 E40 AD10 C40 AD11 M48 AD12 M45 AD13 F53 AD14 M40 AD15 M43 AD16 J36 AD17 K48 AD18 F40 AD19 C42 AD20 K46 AD21 M51 AD22 J52 AD23 K51 AD24 L34 AD25 F42 AD26 J40 AD27 G46 AD28 F44 AD29 M47 AD30 H36 AD31 PCI 5 D83 USB_OC#1_D 2 USB20_N10 USB20_P10 USB20_N11 USB20_P11 USB20_N12 USB20_P12 USB20_N13 USB20_P13 USBBIAS 2 R224 1 22.6_0402_1% USB_OC#0 USB_OC#1_D USB_OC#2 USB_OC#3 USB_OC#4 26 26 12 12 26 26 26 26 8 pins SIM card B Int. Camera 3G +3VALW WiMax(WLAN) USB_OC#2 2 10K_0402_5% USB_OC#3 2 10K_0402_5% EXP_CPPE# 2 10K_0402_5% Within 500 mils USB_OC#0 30,31 1 R1501 1 R1502 1 R1430 RP6 USB_OC#0 SLP_CHG_M3_PCH SLP_CHG_M4_PCH USB_OC#4 SLP_CHG_M3_PCH 24 SLP_CHG_M4_PCH 24 4 3 2 1 5 6 7 8 10K_0804_8P4R_5% 12/21 reserved 0120 reserved for both. IBEXPEAK-M QV20 A0_FCBGA1071 HM55@ USB_OC#1 24,31 CH751H-40PT_SOD323-2 03/23 common design. EXP_CPPE# 1 A A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH USB/PCI/NAND Size B Date: Document Number Rev 1.0 NDU00_LA-6031P M/B Monday, April 12, 2010 Sheet 1 19 of 45 5 4 3 2 1 U8F High = Enabled (Default) Low = Disabled MISC PCH_GPIO12 K9 LAN_PHY_PWR_CTRL / GPIO12 A20GATE PCH_GPIO15 T7 GPIO15 EC_SCI# J32 TACH3 / GPIO7 EC_SMI# EC_SMI# F10 GPIO8 PCH_GPIO16 1019 change net name to follow common design 3G_OFF# 3G_OFF# BT_DET# 2 R232 @ BT_DET# PCH_GPIO27 1 1K_0402_5% PCH_GPIO28 25,26 BT_PW R# 25 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N AM3 F38 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 Y7 B 5 31 RST_GATE THM_ALT# SCLOCK / GPIO22 H10 GPIO24 AB12 GPIO27 V13 GPIO28 M11 STP_PCI# / GPIO34 PECI RCIN# BE10 THRMTRIP# BD10 TP1 BA22 SATA3GP / GPIO37 TP2 AW22 PCH_GPIO38 V3 SLOAD / GPIO38 TP3 BB22 PCH_GPIO39 P3 SDATAOUT0 / GPIO39 TP4 AY45 PCH_GPIO45 H3 PCIECLKRQ6# / GPIO45 TP5 AY46 RST_GATE F1 PCIECLKRQ7# / GPIO46 TP6 AV43 ISDBT_DET AB6 SDATAOUT1 / GPIO48 TP7 AV45 THM_ALT# AA4 SATA5GP / GPIO49 TP8 AF13 GPIO57 TP9 M18 TP10 N18 TP11 AJ24 TP12 AK41 TP13 AK42 TP14 M32 TP15 N32 TP16 M30 TP17 N30 TP18 H12 TP19 AA23 NC_1 AB45 NC_2 AB38 NC_3 AB42 NC_4 AB41 NC_5 T39 +3VALW EC_SMI# 1 2 R248 10K_0402_5% 1 2 PCH_GPIO57 R249 10K_0402_5% 1 2 PCH_GPIO15 R250 1K_0402_5% 1 2 PCH_GPIO28 R251 10K_0402_5% 1 2 PCH_GPIO45 R252 10K_0402_5% 1 2 RST_GATE R253 10K_0402_5% 1 2 PCH_GPIO12 10K_0402_5% R254 SATA2GP / GPIO36 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 INIT3_3V# TP24 1 2 PCH_GPIO36 10K_0402_5% R1495 1 2 PCH_GPIO37 10K_0402_5% R1496 IBEXPEAK-M QV20 A0_FCBGA1071 HM55@ 1 10K_0402_5% D +3VS GATEA20 31 CLK_CPU_BCLK# 5 CLK_CPU_BCLK 5 1 R231 2 0_0402_5% PECI 5 KB_RST# 31 H_PW RGOOD 5 THRMTRIP_PCH# 1 R233 2 56_0402_1% SATACLKREQ# / GPIO35 AB13 A4 A49 A5 A50 A52 A53 B2 B4 B52 B53 BE1 BE53 BF1 BF53 BH1 BH2 BH52 BH53 BJ1 BJ2 BJ4 BJ49 BJ5 BJ50 BJ52 BJ53 D1 D2 D53 E1 E53 GATEA20 KB_RST# PROCPWRGD 2 R229 R230 10K_0402_5% T1 PCH_GPIO37 F8 KB_RST# PCH_PECI AB7 PCH_GPIO57 +3VS BG10 PCH_GPIO36 C 1 2 PCH_GPIO0 10K_0402_5% R235 1 2 PCH_GPIO1 10K_0402_5% R236 1 2 PCH_GPIO6 8.2K_0402_5% R237 EC_SCI# 1 2 10K_0402_5% R238 1 2 PCH_GPIO16 10K_0402_5% R239 1 2 3G_OFF# 10K_0402_5% R240 BT_DET# 1 2 10K_0402_5% R241 1 @ 2 PCH_GPIO36 10K_0402_5% R242 1 @ 2 PCH_GPIO37 10K_0402_5% R243 1 2 PCH_GPIO38 10K_0402_5% R244 1 2 PCH_GPIO39 10K_0402_5% R245 1 2 ISDBT_DET 10K_0402_5% R246 1 2 THM_ALT# 10K_0402_5% R247 U2 AA2 V6 BT_RST# +3VS AF48 AF47 CLKOUT_PCIE7N CLKOUT_PCIE7P EC_SCI# 26 AH45 AH46 1 TACH2 / GPIO6 CLKOUT_PCIE6N CLKOUT_PCIE6P 2 D37 CPU PCH_GPIO27 PCH_GPIO6 31 25 On-Die PLL VR TACH1 / GPIO1 BMBUSY# / GPIO0 31 GPIO15 a Strong pull up may be needed for GPIO Functionality Internal: Pull down 20k During Reset: Low Initial: Low C38 RSVD Internal: Pull up 20k During Reset: High Initial: High PCH_GPIO1 GPIO Not pull down Y3 NCTF GPIO8 D PCH_GPIO0 H_THERMTRIP# 5 1 R234 2 +VTT 56_0402_1% C P6 C10 B Not pull low internal pull up Internal: Pull up 20k During Reset: High Initial: High 02/08 reserved for porject ID. A A @ 1 2 BT_RST# 10K_0402_5% R255 @ EC_SMI# 1 2 R256 1K_0402_5% Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH CPU/GPIO Size B Date: Document Number Rev 1.0 NDU00_LA-6031P M/B Monday, April 12, 2010 Sheet 1 20 of 45 4 3 +1.05VS 2 +1.05VS 1 C282 1U_0402_6.3V4Z 2 +VTT PJ18 2 2 1 1 @ JUMP_43X118 2 C296 B +PCH_VRM 2 R263 AN35 VCC3_3[1] +PCH_FDI_VRM AT22 VCCVRM[1] BJ18 VCCFDIPLL +1.05VS AM23 VCCIO[1] LVDS 40mA AF53 VSSA_DAC[2] AF51 AH38 AH39 VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4] AP43 AP45 AT46 AT45 HVCMOS VCC3_3[2] AB34 VCC3_3[3] AB35 VCC3_3[4] AD35 2 2 1 1 C284 0.1U_0402_16V4Z 2 +3VS L10 2 1 MURATA_BLM18AG601SN1D_0603 C285 10U_0805_10V4Z +1.8VS C286 0.01U_0402_25V4Z C287 0.01U_0402_25V4Z 2 0.1U_0402_16V4Z C288 1 close to AB34 C +PCH_VRM 196mA 3062mA 61mA 37mA VCCVRM[2] AT24 VCCDMI[1] AT16 VCCDMI[2] AU16 +PCH_DMI_VRM VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9] 1 R257 +PCH_VRM 2 0_0402_5% +1.5VS +1.05VS +PCH_VCCDMI 1 2 156mA 375mA D close to AE50 +3VS +3VS 375mA DMI VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] VCCIO[50] VCCIO[51] VCCIO[52] VCCIO[53] VCCIO[54] VCCIO[55] 1 0.1U_0402_16V4Z 1 0_0402_5% VCCAPLLEXP AN30 AN31 +3VS VSSA_DAC[1] 1 +3VS_VCCADAC 1 VCCALVDS PCI E* 2 10U_0805_10V4Z 2 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z AE52 VSSA_LVDS NAND / SPI BJ24 AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27 VCCIO[24] FDI AK24 1 C289 1 C290 1 C291 1 C292 1 C293 VCCADAC[2] > 1mA 59mA +1.05VS AE50 1432mA +1.05VS C VCCADAC[1] 69mA CRT D 1 VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] 1U_0402_6.3V4Z C283 C281 10U_0805_10V4Z 2 POWER U8G AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31 AJ30 AJ31 VCC CORE 5 AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15 1 R259 @ 2 1 R258 0_0402_5% 2 0_0603_5% C294 1U_0402_6.3V4Z 2 R260 +1.8VS 1 0_0402_5% close to AT16 +1.8VS_PCH_NAND +1.8VS 1 R261 2 C295 0.1U_0402_16V4Z 1 close to Ak13 1 R262 2 0_0603_5% +3VS @ 2 0_0603_5% B +3VS 85mA VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4] AM8 AM9 AP11 AP9 2 C297 close to AM8 IBEXPEAK-M QV20 A0_FCBGA1071 HM55@ 0.1U_0402_16V4Z 1 A A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title PCH POWER-1 Size B Date: Document Number Rev 1.0 NDU00_LA-6031P M/B Monday, April 12, 2010 Sheet 1 21 of 45 3 POWER 2 2 1 C306 22U_0805_6.3V6M +1.05VS 2 2 R266 0_0603_5% @ 2 +1.05VS_PCHDPLL_A 2 L12 1 2 10UH_LB2012T100MR_20% C311 1U_0402_6.3V4Z 1 2 2 C315 1U_0402_6.3V4Z AF43 VCCME[4] AF41 VCCME[5] +1.05VS 1 C316 1U_0402_6.3V4Z 163mA 1849mA AF42 VCCME[6] V39 VCCME[7] V41 VCCME[8] V42 VCCME[9] Y39 VCCME[10] Y41 VCCME[11] Y42 VCCME[12] V9 DCPRTC 196mA VCCVRM[3] 68mA BB51 BB53 VCCADPLLA[1] VCCADPLLA[2] 69mA +1.05VS_PCHDPLL_B BD51 BD53 VCCADPLLB[1] VCCADPLLB[2] 1U_0402_6.3V4Z 1 1 AH23 AJ35 AH35 VCCIO[21] VCCIO[22] VCCIO[23] AF34 VCCIO[2] 1 C314 + 220U_6.3V_R17 VCCME[3] AU24 +PCH_VRM 1 2 C307 1U_0402_6.3V4Z +VCCRTCEXT 2 0.1U_0402_16V4Z 1 C310 + 220U_6.3V_R17 AD41 1 L11 1 2 10UH_LB2012T100MR_20% VCCME[2] 1 1 C309 C VCCME[1] AD39 C317 2 C318 2 2 1U_0402_6.3V4Z AH34 VCCIO[3] AF32 VCCIO[4] 1 C320 +VCCSST 2 0.1U_0402_16V4Z V12 DCPSST 1 C321 2 +V1.1A_INT_VCCSUS Y22 0.1U_0402_16V4Z DCPSUS VCCSUS3_3[28] U23 VCCIO[56] V23 +1.05VS V5REF_SUS F24 +PCH_VCC5REFSUS > 1mA > 1mA 375mA V5REF K49 VCC3_3[8] J38 VCC3_3[9] L38 VCC3_3[10] M36 VCC3_3[11] N36 VCC3_3[12] P36 VCC3_3[13] U35 VCC3_3[14] AD13 3062mA 31mA VCCSATAPLL[1] VCCSATAPLL[2] C303 0.1U_0402_16V4Z 2 2 1 1 C304 0.1U_0402_16V4Z +3VALW +5VALW D8 R264 100_0402_1% +3VS 2 C308 1 0.1U_0402_16V4Z D9 CH751H-40PT_SOD323-2 +PCH_VCC5REF R265 C 100_0402_1% +PCH_VCC5REF 1 +3VS 2 +5VS 1 C305 22U_0805_6.3V6M AD38 D +3VALW 2 2 2 Near V39 1 DCPSUSBYP 1 C302 1U_0402_6.3V4Z 320mA 1U_0402_6.3V4Z 2 2 2 VCCLAN[2] Y20 V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26 C298 1 If two VccME rails can be combined, only total 2 x 22 µF and 2 x 1 µF caps are necessary 1 C301 22U_0805_6.3V6M AF24 VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27] 1 1 1 C300 22U_0805_6.3V6M VCCLAN[1] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] 3062mA 2 +1.05VS AF23 52mA 1 +1.05VS V24 V26 Y24 Y26 2 Near AD38 VCCACLK[2] USB 1 +TP_PCH_VCCDSW 0.1U_0402_16V4Z 2 C299 VCCACLK[1] AP53 PCI/GPIO/LPC VccLAN may be grounded if Intel LAN is disabled AP51 1 U8J D 2 CH751H-40PT_SOD323-2 4 Clock and Miscellaneous 5 C312 1U_0402_6.3V4Z C313 0.1U_0402_16V4Z 1 +3VS 2 C319 1 0.1U_0402_16V4Z AK3 AK1 +1.05VS 2 0.1U_0402_16V4Z VCCSUS3_3[29] U19 VCCSUS3_3[30] U20 VCCSUS3_3[31] U22 VCCSUS3_3[32] +3VS 1 C324 2 0.1U_0402_16V4Z +1.05VS 1 C325 1 C326 1 C327 2 4.7U_0603_6.3V6K 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 C328 2 0.1U_0402_16V4Z 375mA V15 VCC3_3[5] V16 VCC3_3[6] Y16 VCC3_3[7] VCCIO[9] 196mA VCCVRM[4] AT20 VCCIO[10] AH19 VCCIO[11] AD20 VCCIO[12] AF22 VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] AD19 AF20 AF19 AH20 VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] AB19 AB20 AB22 AD22 SATA 1 C322 163mA P18 PCI/GPIO/LPC +3VALW 3062mA > 1mA AT18 V_CPU_IO[1] AU18 V_CPU_IO[2] CPU B AH22 1849mA VCCRTC 1 C329 2 1U_0402_6.3V4Z 1 C331 2 0.1U_0402_16V4Z 2mA HDA A12 A RTC +RTCVCC 6mA IBEXPEAK-M QV20 A0_FCBGA1071 HM55@ VCCME[13] VCCME[14] VCCME[15] VCCME[16] VCCSUSHDA B +PCH_VRM +1.05VS 1 C323 1U_0402_6.3V4Z 2 +1.05VS AA34 +PCH_VCCME1 Y34 +PCH_VCCME2 Y35 +PCH_VCCME3 AA35 +PCH_VCCME4 R267 R268 R269 R270 L30 1 2 LP@ C330 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 1 1 1 1 2 2 2 2 2 1 R1467 0_0402_5% 2 R1468 180_0402_1% 2 R1469 150_0402_1% 1 LP@ 1 1U_0402_6.3V4Z 2010/04/12 Issued Date Deciphered Date 3 A 12/14 Reserve 1.5VA for low power. Compal Electronics, Inc. 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 VCCSUSHDA can be either 1.5V or 3.3V Compal Secret Data Security Classification 5 +3VALW 2 Title PCH POWER-2 Size Document Number Custom Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet 1 22 of 45 5 4 3 2 1 U8I AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47 B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49 BB5 BC10 BC14 BC18 BC2 BC22 BC32 BC36 BC40 BC44 BC52 BH9 BD48 BD49 BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50 BE6 BE8 BF3 BF49 BF51 BG18 BG24 BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47 BH7 C12 C50 D51 E12 E16 E20 E24 E30 E34 E38 E42 E46 E48 E6 E8 F49 F5 G10 G14 G18 G2 G22 G32 G36 G40 G44 G52 AF39 H16 H20 H30 H34 H38 H42 D C B A VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366] H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14 U8H AB16 VSS[0] AA19 AA20 AA22 AM19 AA24 AA26 AA28 AA30 AA31 AA32 AB11 AB15 AB23 AB30 AB31 AB32 AB39 AB43 AB47 AB5 AB8 AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31 AD32 AD34 AU22 AD42 AD46 AD49 AD7 AE2 AE4 AF12 Y13 AH49 AU4 AF35 AP13 AN34 AF45 AF46 AF49 AF5 AF8 AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43 AH47 AH7 AJ19 AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32 AJ34 AT5 AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28 VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] D C B IBEXPEAK-M QV20 A0_FCBGA1071 HM55@ A Compal Electronics, Inc. Compal Secret Data Security Classification IBEXPEAK-M QV20 A0_FCBGA1071 HM55@ 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47 4 3 2 Title PCH-GND Size Document Number Custom Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet 1 23 of 45 5 4 3 2 1 SATA HDD Conn. +5VS 1.2A 1 Place closely JHDD SATA CONN. 1 C332 10U_0805_10V4Z 2 1 C333 0.1U_0402_16V4Z 2 1 C334 0.1U_0402_16V4Z 2 C335 0.1U_0402_16V4Z 2 D D 1/28 Add JHDD2 JHDD2 Layout symbol reverse JHDD1, recerse the pin define JHDD2 JHDD1 13 14 GND GND 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 +5VS GND GND 10 9 8 7 6 5 4 3 2 1 0120 change to GND. SATA_PTX_C_DRX_P1 SATA_PTX_C_DRX_N1 C340 1 C341 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PTX_DRX_P1 15 SATA_PTX_DRX_N1 15 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 C342 1 C343 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PRX_C_DTX_N1 15 SATA_PRX_C_DTX_P1 15 12 11 10 9 8 7 6 5 4 3 2 1 +5VS SATA_PTX_C_DRX_P1 SATA_PTX_C_DRX_N1 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 CONN@ ACES_87036-1001-CP ACES_85201-1205N @ 2/2 Update JHDD1 10pin-->12pin Add wire connector for H/W SATA verify C C eSATA/USB Combo +5V_ALW SLP_CHG_M3 SLP_CHG_M4 HIGH LOW Mode 3 31 USB_CHG_EN# 1 2 3 4 +3VALW Mode 4 LOW SLP_CHG B HIGH FUNCTION LOW D=1D HIGH U45 19 USB20_P3 19 USB20_N3 D=2D USB_OC#1 19,31 RT9715BGS_SO8 C390 1 1D+ VCC USB20_N3_S 2 1D- S 9 USB20_P3 3 2D+ D+ 8 USB20_P3_R USB20_N3 4 2D- D- 7 USB20_N3_R 5 GND OE# 6 USB_CHG_EN# 1 +USB_VCCB 8 7 6 5 GND VOUT VIN VOUT VIN VOUT EN FLG 1 0.1U_0402_16V4Z USB20_P3_S 10 W=60mils 1.4A U14 2 2 C344 19 SLP_CHG_M4_PCH 31 SLP_CHG_M4_EC @ R285 0_0402_5% 2 1 R949 75K_0402_1% Use PCH USB20_P3_R 2 2 1 1 USB20_P3_RL USB20_N3_R 3 3 4 4 USB20_N3_RL USB20_P3_S USB20_N3_S +USB_VCCB 2 1 3 IO2 2 5 9 12 1A 2A 3A 4A 14 VCC 1B 2B 3B 4B GND 2 IO1 USB20_P3_RL B 2 @R286 @ R286 JSATA1 USB20_N3_RL USB20_P3_RL 1 0_0402_5% 1 15 SATA_PTX_DRX_P5 15 SATA_PTX_DRX_N5 C347 1 C348 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PTX_C_DRX_P5 SATA_PTX_C_DRX_N5 15 SATA_PRX_C_DTX_N5 15 SATA_PRX_C_DTX_P5 C349 1 C350 1 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K SATA_PRX_DTX_N5 SATA_PRX_DTX_P5 2 R950 51K_0402_1% eSATA/USB Conn 1/26 update JSATA1 footprint USB20_P3_S_O 3 USB20_N3_S_O 6 8 R225 1 2 11 100_0402_5% 1 2 3 4 VBUS DD+ GND USB 5 6 7 8 9 10 11 GND A+ ESATA AGND BB+ GND 12 13 14 15 GND GND GND GND A TAIW I_EU114-117CRL-TW _11P-T @ 7 Compal Electronics, Inc. Compal Secret Data Security Classification SN74CBT3125PW RG4_TSSOP14 C391 0.1U_0402_16V4Z 5 2 CM1293A-02SR_SOT143-4 2 2 1 R951 51K_0402_1% 1OE# 2OE# 3OE# 4OE# 2 1 4 10 13 SLP_CHG_M4 1 USB20_N3_RL 0120 reserve both EC and PCH. U46 A PWR GND W CM2012F2SF-900T04_0805 R952 43K_0402_1% USB20_P3_S_O USB20_N3_S_O SLP_CHG_M3 2 C346 @ 4 +USB_VCCB SLP_CHG_M4 1 + 0.1U_0402_16V4Z +5VALW L16 SLP_CHG_M3 1 2 1 31 SLP_CHG_M3_EC 1000P_0402_50V7K 1 C345 1 19 SLP_CHG_M3_PCH W=60mils 220U_6.3V_M_R17 D10 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 +USB_VCCB SLP_CHG# 31 TS3USB221RSER_QFN10_2x1P5~D R1487 2 R1488 @ 2 R1489 2 R1490 2 @ C351 4.7U_0805_10V4Z @ 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Title SATA-HDD/ODD/USB Size Document Number Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet 1 24 of 45 5 4 3 2 1 BlueTooth Interface +3VS 2 +3VS 3 1 2 1 1 2 R274 47K_0402_5% 1 BT@ C354 0.01U_0402_25V7K BT@ 2 20,26 BT_PW R# D G 1 2 D C353 0.1U_0402_16V7K BT@ S R273 100K_0402_5% BT@ D Q7 BT@ AO3413_SOT23 (MAX=200mA) +BT_VCC +BT_VCC 1 C356 4.7U_0805_10V4Z BT@ 2 C357 0.1U_0402_16V4Z BT@ JBT2 20 BT_RST# 1 BT@ 2 R276 0_0402_5% Bluetooth Connector 19 19 USB20_P5 USB20_N5 20 BT_DET# BT_RESET# BT@ 2 1 R275 0_0402_5% 1 2 3 4 5 6 1 2 3 4 5 G1 6 G2 7 8 ACES_88231-06001 CONN@ C355 0.1U_0402_16V4Z BT@ C C please close to JKB1 KSO2 1 C358 1 C359 KSO0 1 C360 KSO4 1 C361 KSO3 1 C362 KSO5 1 C363 KSO14 1 C364 KSO6 1 C365 KSO7 1 C366 KSO13 1 C367 KSO8 1 C368 KSO9 1 C369 KSO10 1 C370 KSO11 1 C371 KSO12 1 C372 KSO15 1 C373 KSI7 1 C374 KSI2 1 C375 KSI3 1 C376 KSI4 1 C377 KSI0 1 C378 KSI5 1 C379 KSI6 1 C380 KSI1 1 C381 CAPS_LED# 1 C382 NUM_LED# 1 C383 CURS_LED# 1 C384 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J KSO1 KEYBOARD CONN. for 13.3” KEYBOARD CONN. for 11.6” JKB2 JKB1 JKB34 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 B 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 JKB29 KSO2 KSO1 KSO0 KSO4 KSO3 KSO5 KSO14 KSO6 KSO7 KSO13 KSO8 KSO9 KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1 JKB4 CAPS_LED# CURS_LED# NUM_LED# ACES_88170-3400 @ JKB34 JKB29 KSO2 KSO1 KSO0 KSO4 KSO3 KSO5 KSO14 KSO6 KSO7 KSO13 KSO8 KSO9 KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1 JKB4 CAPS_LED# CURS_LED# NUM_LED# ACES_88170-3400 KSI[0..7] @ KSO[0..15] A 1 2 R279 300_0402_5% +3VS 1 2 R280 300_0402_5% +3VS 2 1 R281 300_0402_5% KSI[0..7] +3VS CAPS_LED# 31 CURS_LED# 31 NUM_LED# 31 31 KSO[0..15] 31 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 A Compal Electronics, Inc. Compal Secret Data Security Classification B 2 Title USB/BT/FP/Int. Cam Size Document Number Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet 1 25 of 45 PLT_RST# 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 54 12/14 Reserve debug. 16 PCIE_PRX_W LANTX_N2 16 PCIE_PRX_W LANTX_P2 16 PCIE_PTX_C_W LANRX_N2 16 PCIE_PTX_C_W LANRX_P2 +3V_W LAN 1 2 1R282 0_0402_5% 2 R283 0_0402_5% E51_TXD E51_RXD Debug card using 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 G3 G4 CM8 W LAN@ 2 2 0.01U_0402_25V4Z CM9 W LAN@ C387 47P_0402_50V8J 16 PCIE_PTX_C_W W ANRX_N4 W LAN@ 16 PCIE_PTX_C_W W ANRX_P4 +3VS LPC_FRAME# 15,31,32 LPC_AD3 15,31,32 LPC_AD2 15,31,32 LPC_AD1 15,31,32 LPC_AD0 15,31,32 12/14 Reserve debug. W L_OFF# PLT_RST# W L_OFF# 31 PLT_RST# 5,19,27,28,31,32 1 CM10 0.1U_0402_16V4Z 2 3G@ LED_W IMAX# 33 1 1 PM_SMBCLK PM_SMBDATA USB20_N12 19 USB20_P12 19 LED_W IMAX# +UIM_PW R RM1 4.7K_0402_5% @ JGSIM1 1 2 3 UIM_RESET UIM_CLK DM1 RLZ20A_LL34 3G@ +3VS RN3 03/19 add PLT_RST# for 3G card. +UIM_PW R +UIM_PW R USB20_N13 19 USB20_P13 19 1 2 R1429 100K_0402_5% W IMAX@ GND GND 3G_OFF# 20 PLT_RST# P-TW O_A54402-A0G16-N @ PM_SMBCLK 10,11,12,16 PM_SMBDATA 10,11,12,16 LED_W IMAX# 53 54 2 1 2 4.7U_0805_10V4Z C385 47P_0402_50V8J 3G@ 1 CM12 10P_0402_50V8J 3G@ 2 7 1 CM13 10P_0402_50V8J 2 3G@ 2 PLT_RST# 100K_0402_5% DM2 DAN217_SC59 @ VCC RST CLK NC GND VPP I/O 4 5 6 NC 8 UIM_VPP UIM_DATA 1 MOLEX_47273-0001~D @ DM3 DAN217_SC59 @ DM4 DAN217_SC59 @ CM11 22P_0402_50V8J 2 @ +UIM_PW R BELLW _80052-1021 @ JGSIM2 WLAN&BT Combo module circuits +UIM_PW R 1 VCC GND 5 BT on module UIM_RESET 2 RST VPP 6 UIM_VPP UIM_CLK 3 CLK I/O 7 UIM_DATA 4 RFU RFU 8 9 NC BT on module Enable Disable BT_CRTL HI LO BT_PWR# LO HI NC USB20_N10 19 10 HB_4210826-SINR02 @ USB20_P10 19 **If +3V_WLAN is +3VS, please remove D21. 01/26 Co-lay with JGSIM1. D85 1 BT_CTRL 2 CH751H-40PT_SOD323-2 20,25 BT_PW R# 2 G Q27 1 29,31,34,37,40 SUSP# D 3 31 31 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 G1 G2 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 55 56 CM7 W LAN@ 2 2 4.7U_0805_10V4Z 1 CLK_W LAN# CLK_W LAN 2 4 6 8 10 12 14 16 2 2 16 16 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 CM1 0.01U_0402_25V4Z 3G@ 1 BT_CTRL 16 CLKREQ_W LAN# 1 3 5 7 9 11 13 15 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 +UIM_PW R For SED 90 MIL 0.1U_0402_16V4Z 1 1 1 CM2 CM3 3G@ 3G@ 2 +1.5VS JW LAN1 1 3 5 7 9 11 13 15 1 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 UIM_DATA UIM_CLK UIM_RESET UIM_VPP 1 JUMP_43X79 16 PCIE_PRX_W W ANTX_N4 16 PCIE_PRX_W W ANTX_P4 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 2 4 6 8 10 12 14 16 1 +3V_W LAN 01/27 Reserve for 8 pin SIM card. +3VS 2 4 6 8 10 12 14 16 3 1 For SED 0.1U_0402_16V4Z 1 1 1 @ 2 1 CLK_W W AN# CLK_W W AN 2 +3VS 2 4.7U_0805_10V4Z +1.5VS PJ16 2 2 16 16 1 3 5 7 9 11 13 15 2 2 0.01U_0402_25V4Z C386 47P_0402_50V8J W LAN@ 1 3 5 7 9 11 13 15 3 +3V_W LAN 2 1 1 JUMP_43X79 @ 16 CLKREQ_UW B# 1 CM6 W LAN@ 1 2 CM5 W LAN@ 2 2 CM4 W LAN@ For SED 0.1U_0402_16V4Z 1 1 PJ15 J3G1 2 +3V_W LAN +3VALW +3VS PCIe Mini Card-3G 3 PCIe Mini Card-WLAN/WiMax S 2N7002_SOT23-3 W LAN@ 01/20 For combine WLAN card. Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title PCIe-WLAN/HDDVD/NAND/NEW Size Document Number Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet 26 of 45 5 4 3 2 1 12/14 Fine tune pin define UL1 Pin37 Pin40 -->Dummy UL1 16 PCIE_PRX_C_LANTX_P1 CL1 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1 22 HSOP 16 PCIE_PRX_C_LANTX_N1 CL2 1 2 0.1U_0402_16V7K 23 HSON 17 18 HSIP HSIN PCIE_PRX_LANTX_N1 16 PCIE_PTX_C_LANRX_P1 16 PCIE_PTX_C_LANRX_N1 D RL19 16 CLKREQ_LAN# 5,19,26,28,31,32 0_0402_5% 16 PLT_RST# 16 16 CLK_LAN CLK_LAN# LAN_X1 +3V_LAN CLKREQB 25 PERSTB 19 20 REFCLK_P REFCLK_N 43 LAN_X2 44 2 EC_SW I# 10K_0402_5% 1 17 EC_SW I# LAN_W AKE# 28 ISOLATEB 26 @ @ +3V_LAN 1 RL20 1 RL21 1 RL22 2 1K_0402_5% 2 1K_0402_5% 2 1K_0402_5% ENSW REG 12/18 vendor request CKXTAL2 +3VS ISOLATEB 14 15 38 NC/SMBCLK NC/SMBDATA GPO/SMBALERT 33 1 2 2.49K_0402_1% 2 RL6 1K_0402_1% 30 32 MDIP0 MDIN0 MDIP1 MDIN1 NC/MDIP2 NC/MDIN2 NC/MDIP3 NC/MDIN3 1 2 4 5 7 8 10 11 LL1 RL2 2 RL1 2 +LAN_REGOUT 1 2 4.7UH_1008HC-472EJFS-A_5%_1008 1 10K_0402_5% 1 10K_0402_5% LAN_MDI0+ LAN_MDI0LAN_MDI1+ LAN_MDI1- 1 2 2 1 D CL9 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 13 29 41 +LAN_VDD10 DVDD33 DVDD33 27 39 +3V_LAN +LAN_VDD10 AVDD33 AVDD33 AVDD33 AVDD33 VDDREG VDDREG 46 RSET GND PGND AVDD10 AVDD10 AVDD10 AVDD10 REGOUT 21 3 6 9 45 36 1 LL2 CL18 1U_0402_6.3V4Z +3V_LAN +3V_AVDDXTAL 1 2 CL10 2 CL4 2 CL5 2 CL6 2 CL7 1 1 1 1 +LAN_EVDD10 2 0_0603_5% 12 42 47 48 +3V_LAN Close to Pin 27,39,12,47,48 Layout Note: LL1 must be within 200mil to Pin36 CL13 CL8,CL9 must be within 4.7U_0805_6.3V6M 200mil to LL1 +LAN_REGOUT: Width =60mil DVDD10 DVDD10 DVDD10 EVDD10 24 49 1 2 2 CL17 0.1U_0402_16V4Z 1 Close to Pin 3,6,9,13,29,41,45 +LAN_VDD10 Close to Pin 21 0.1U_0402_16V4Z +LAN_EVDD10 0.1U_0402_16V4Z +LAN_VDD10 0.1U_0402_16V4Z +3V_LAN +LAN_VDDREG 2 0_0603_5% +LAN_REGOUT 1 LL3 CL28 4.7U_0603_6.3V6K RTL8105E-VB-GR_QFN48_6X6 8111E@ Need to re-link database ISOLATEB +LAN_VDD10 Can change to 2.2uH&4.7uF 0.1U_0402_16V4Z ENSWREG C 1 RL5 EECS/SCL EEDI/SDA Main: SHI0000AA00 2nd : SHI0000AB00 LANWAKEB 34 35 +LAN_VDDREG 31 37 40 CKXTAL1 @ RL3 LED3/EEDO LED1/EESK LED0 0.1U_0402_16V4Z 1 2 2 CL29 0.1U_0402_16V4Z 1 1 1 1 1 2 CL19 2 CL20 2 CL21 2 CL22 C RL7 15K_0402_5% +3V_LAN +3V_AVDDXTAL RL8 0_0402_5% +3V_LAN YL1 LAN_X1 1LAN_X2 2 RL9 @ 0_0402_5% RL4 0_0402_5% +LAN_VDD10 25MHZ_20PF_7A25000012 1 CL26 27P_0402_50V8J 2 CL11@ 1 CL27 27P_0402_50V8J 2 1 0.1U_0402_16V4Z ENSW REG Reserved For 1.05V Crystal 2 RL23 0_0402_5% @ B B +3VALW TO +3V_LAN +3VALW 2 +3VALW Vgs=-4.5V,Id=3A,Rds<97mohm 1 1 1 2 2 47K_0402_5% 1 CL14 AO3413_SOT23 0.01U_0402_25V7K 2 1 1 RL16 2 G W OL_EN# 3 QL1 D 31 UL2 2 1 CL12 0.1U_0402_16V7K S RL24 100K_0402_5% LAN_MDI1+ LAN_MDI1- PJ17 JUMP_43X39 @ 2 CL30 1 0.01U_0402_16V7K +3V_LAN LAN_MDI0+ LAN_MDI0- 2 1 CL15 4.7U_0805_10V4Z @ A TD+ TDCT NC NC CT RD+ RD- TX+ TXCT NC NC CT RX+ RX- 16 15 14 13 12 11 10 9 RJ45_MIDI1+ RJ45_MIDI1- RJ45_MIDI1+ 13 RJ45_MIDI1- 13 CL31 1 1 CL32 RJ45_MIDI0+ RJ45_MIDI0- RJ45_MIDI0+ 13 RJ45_MIDI0- 13 2 75_0402_1% 2 75_0402_1% RJ45_GND RL26 RJ45_GND 12/21 place transformer on board. 1U_0402_6.3V4Z 2 A Compal Secret Data Security Classification Issued Date 2010/04/12 2010/02/02 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 RL25 2 1000P_0402_50V7K 1 2 1 1000P_0402_50V7K NS681680 1 CL8 2 1 2 3 4 5 6 7 8 4 3 2 Title Compal Electronics, Inc. RTL8105E/RTL8111E Size Document Number Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet 1 27 of 45 A B C D +1.8VS_OUT place close to pin 5 (CC3-CC2-CC1) 1 2 CC4 close to pin 10 D3E mode (Intel only) Intel can use PCIe root port RC4 10K_0402_5% PCH GPIO13 +3VS UC1 16 16 CLK_CR# CLK_CR CLK_CR# CLK_CR PCIE_PTX_C_CRRX_N5 PCIE_PTX_C_CRRX_P5 16 PCIE_PTX_C_CRRX_N5 16 PCIE_PTX_C_CRRX_P5 16 PCIE_PRX_C_CRTX_N5 16 PCIE_PRX_C_CRTX_P5 CC8 CC9 1 1 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 PCIE_PRX_CRTX_N5 PCIE_PRX_CRTX_P5 2 RC2 12K_0402_1% JMB389@ RC2 9.1K_0402_1% JMB385@ 1 APREXT 12mil +SEL43 3 4 APCLKN APCLKP 9 8 APRXN APRXP 11 12 APTXN APTXP 7 APVDD APV18 NC/TAV33 5 10 36 DV33 DV33 DV33 DV18 DV18 19 20 44 18 37 MDIO0 MDIO1 MDIO2 MDIO3 MDIO6/4 MDIO5 G/MDIO6 SA00003Z400 MDIO7 MDIO8 XRSTN MDIO9 XTEST MDIO10 MDIO11 MDIO12 CPPE_N MDIO13 CR1_CD2N MDIO14 48 47 46 45 41 42 24 40 29 28 27 26 25 23 22 NC/SPI_SCK NC/SPI_CSN NC/SPI_SO NC/SPI_SI 30 33 34 35 APGND NC/GND NC/GND NC/GND 6 31 32 38 APREXT 43 39 SDDV/MDIO4 TXIN/NC JMB389 PLT_RST# 2 RC3 0_0402_5% JMB385@ 2 1 2 CPPE# XD_CD# 13 14 MS_CD# SD_CD# 15 16 CR1_CD1N CR1_CD0N 17 CR1_PCTLN 40 mils +3VS +VCC_OUT SD_CD# 33 CR_LED# CR_LED# 21 PU HDA SUS +TVA33 place near JMB389@ 1 RC19 0_0402_5% CC5 1 2 1 CC6 40mil 1 CC7 pin 19,20 and 44 +TVA33 15 CR_CPPE# RC5 1 0_0402_5% CPPE# 2 2 15 CR_W AKE# RC14 1 0_0402_5% SD_CD# 2 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 +1.8VS_OUT JMB389@ CC12 0.1U_0402_16V4Z PCH GPIO21 XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 SEL41 SDCLK_MSCLK_XDCE# SEL24 XD_CLE XD_SD_MMC_D4 XD_SD_MMC_D5 XD_SD_MMC_D6 XD_SD_MMC_D7 XD_RE# XD_RB# XD_ALE CC12 close to pin 36 2 CC11 1 1 2 10U_0805_10V4Z Power On Strapping setting CC11 close to pin18 For intenal LDO's usage Description Pin name CC10 0.22U_0402_6.3V4K High CC10 close to pin37 MDIO7 MDIO14 CR1_LEDN XD_CD# JMB389-QGAZ0C_QFN48_7X7 JMB389@ low ★ on-board add-in card ★ CR_LED high active CR_LED low active SEL33 +3VS XD_CLE MS_CD# 1 20mil MDIO7 UC1 JMB385-QGAZ0C QFN 48P JMB385@ GND JMB385@ 1 2 RC27 4.7K_0402_5% 1 JMB385@2 RC29 4.7K_0402_5% 1 2 RC32 4.7K_0402_5% JMB385@ 49 5,19,26,27,31,32 JMB389@ 100_0402_5% 1 2 RC3 1 CC13 0.1U_0402_16V4Z JMB389@ +3VALW 1 2 1 CC4 2 2 1 CC3 0.1U_0402_16V4Z JMB389C / JMB385C 1 CC2 1000P_0402_50V7K 2 0.22U_0402_6.3V4K 1 CC1 10U_0805_10V4Z 20mil XD_ALE 1 RC28 2 1K_0402_5% 1 2 1K_0402_5% MDIO14 RC26 SA00003G010 1 RC25 @ 2 2 200K_0402_5% place 6 GND vias on T-pad +VCC_OUT XDW P#_SDW P# XD_RB# SDCMD_MSBS_XDW E# SD_CD# 1 2 RC7 10K_0402_5% 2 1 RC9 1K_0402_5% 1 2 RC30 10K_0402_5% JMB385@ SDCLK_MSCLK_XDCE# 2 1 RC11 JMB389@ 22_0402_5% 2 1 RC12 JMB389@ 22_0402_5% 2 1 RC13 JMB389@ 22_0402_5% RC11 FBMA-10-100505-121T_0402 JMB385@ RC12 FBMA-10-100505-121T_0402 JMB385@ RC13 FBMA-10-100505-121T_0402 JMB385@ SD_CLK MS_CLK XD_CE# JMB385@ RC15 1 2 MS_CLK JMB385@ RC16 1 2 100P_0402_50V8J 100_0402_5% XD_CE# JMB385@RC24 JMB385@RC24 1 @ 2 RC18 0_0402_5% 1 2 JMB385@ SEL24 RC1 1 CC24 JMB385@ 1 2 2 100P_0402_50V8J +VCC_OUT 0_0402_5% 2 JMB385@ CC17 1 2 1 13 22 43 SD_VCC MS_VCC XD_VCC SD_CLK SDCMD_MSBS_XDW E# SD_CD# XDW P#_SDW P# XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 XD_SD_MMC_D4 XD_SD_MMC_D5 XD_SD_MMC_D6 XD_SD_MMC_D7 10 19 1 2 4 3 25 23 21 17 8 5 SD_CLK SD_CMD SD_CD SD_WP SD/MMC_DAT0 SD/MMC_DAT1 SD/MMC_DAT2 SD/MMC_DAT3 MMC_DATA4 MMC_DATA5 MMC_DATA6 MMC_DATA7 XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 MS_CLK MS_CD# SDCMD_MSBS_XDW E# 12 11 14 18 20 16 9 MS_DATA0 MS_DATA1 MS_DATA2 MS_DATA3 MS_SCLK MS_INS MS_BS CC18 2 3/18 22U change to 10U RC21 0_0402_5% 1 2 JMB389@ JREAD1 40 mils 0.1U_0402_16V4Z CC21 SEL33 3 Reserved for EMI,close to JREAD 10U_0805_10V6K 2 1 0.1U_0402_16V4Z @ CC20 0.1U_0402_16V4Z 3 CC23 JMB385@ 1 2 100P_0402_50V8J 100_0402_5% 1 CC22 JMB385@ 1 2 100_0402_5% Reserved for EMI,close to UC1.42 XD_CD# SD_CLK 4 XD_D0 XD_D1 XD_D2 XD_D3 XD_D4 XD_D5 XD_D6 XD_D7 35 36 37 38 39 40 41 42 XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 XD_SD_MMC_D4 XD_SD_MMC_D5 XD_SD_MMC_D6 XD_SD_MMC_D7 XD_CD XD_R/B XD_RE XD_CE XD_CLE XD_ALE XD_WE XD_WP 26 27 28 29 30 31 32 33 XD_CD# XD_RB# XD_RE# XD_CE# XD_CLE XD_ALE SDCMD_MSBS_XDW E# XDW P#_SDW P# SD_GND SD_GND MS_GND MS_GND XD_GND XD_GND GND GND 7 15 6 24 34 44 45 46 SEL41 XDW P#_SDW P# RC22 0_0402_5% 1 2 JMB385@ RC23 0_0402_5% SDCMD_MSBS_XDW E# 1 2 JMB389@ +SEL43 RC20 0_0402_5% 1 2 JMB385@ JMB389@ CC16 2.2U_0603_6.3V6K 1 2 CC16 close to pin43 For internal LDO in SD3.0 4 TAITW_R013-P12-HM_44P_NR-T CONN@ 01/26 Update new card reader symbol to EVT Compal Secret Data Security Classification Issued Date 2010/04/12 Deciphered Date 2010/10/08 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title Compal Electronics, Inc. Card Reader-JMB389C/385C Size Document Number Custom Date: Rev 1.0 NBQAA LA6071P M/B Monday, April 12, 2010 Sheet D 28 of 45 A B C +PVDD1 RA2 2 1 0_0603_1% 0.1U_0402_16V4Z 1 1 CA57 2 @ 1 0.1U_0402_16V4Z @ MIC1_L 30 MIC1_L RA24 1 RA25 +MIC1_VREFO_L 1 2 1K_0402_5% 2 2.2K_0402_5% place close to JP2_1103 MIC1_R_L @ CA65 0.1U_0402_16V4Z 1 2 4.7U_0805_10V4Z MIC1_R_L 2 CA21 1 MIC1_R_R 1 2 4.7U_0805_10V4Z 23 24 14 15 21 22 16 17 CA22 2 12 INT_MIC_DATA 2 INT_MIC_CLK_R 3 +3VS 1 @ CA62 10P_0402_50V8J 2 1 1 4 31 EC_MUTE# RA27 @ 4.7K_0402_5% 1 2 38 LINE2_L LINE2_R SPK_OUT_R+ SPK_OUT_R- AZ_RST_HD# MONO_IN 2 100P_0402_50V8J 1 CA12 CA63 @ 0.1U_0402_16V4Z 11 15 AZ_RST_HD# 12 SENSE_A 13 03/19 change to AGND. 18 2 1 2 CA15 2.2U_0603_6.3V4Z 36 35 31 +MIC1_VREFO_L CA47 1 2 0.1U_0603_50V7K CA48 1 2 0.1U_0603_50V7K 43 42 49 7 0.1U_0402_16V4Z +5VS 1 1 CA59 @ @ CA58 2 2 10U_0805_10V4Z RA3 10U_0805_10V4Z 0.1U_0402_16V4Z 2 1 +5VS 0_0603_1% CA3 1 1 CA4 CA5 1 SPKL+ SPKL- 30 30 45 44 SPKR+ SPKR- 30 30 SYNC 10 HP_L HP_R Headphone out 20K PORT-B (PIN 21, 22) Ext. MIC 10K PORT-C (PIN 23, 24) 39.2K PORT-E (PIN 14, 15) 20K PORT-F (PIN 16, 17) 10K PORT-H (PIN 20) place close to chip 30 MIC_SENSE 30 NBA_PLUG 30 30 2 RA10 1 20K_0402_1% RA21 39.2K_0402_1% 2 0.1U_0603_50V7K SENSE_A 12/16 More R on small board, Del RA4 RA5 MIC2_L MIC2_R GPIO0/DMIC_DATA BCLK AZ_SYNC_HD 6 15 AZ_BITCLK_HD 15 2 GPIO1/DMIC_CLK PD# SDATA_IN 8 EAPD 47 SPDIFO 48 MONO_OUT 20 RESET# PCBEEP SENSE A MIC2_VREFO SENSE B MIC1_VREFO_R LDO_CAP CBP 5 CBN VREF MIC1_VREFO_L PVSS2 PVSS1 DVSS2 DVSS1 JDREF CPVEE AVSS1 AVSS2 AZ_SDOUT_HD 15 AZ_SDIN0_HD_R 2 RA6 1 33_0402_5% AZ_SDIN0_HD 15 Beep sound EC Beep 29 27 AC_VREF 19 AC_JDREF2 RA9 34 31 +MIC1_VREFO_R CA23 10U_0805_10V4Z 1 2 30 28 1 CA14 EC_BEEP# PCI Beep 1 20K_0402_1% 2 2.2U_0603_6.3V4Z 26 37 1 1 CA17 2 2 0.1U_0402_16V4Z 15,18 PCH_SPKR @ CA16 10U_0805_10V4Z RA7 1 2 47K_0402_5% 3 1 RA18 MONO_IN 0.1U_0402_16V4Z 1 place close to chip DGND CA13 1 2 RA8 1 2 47K_0402_5% RA12 10K_0402_5% AGND 2 2 0.1U_0603_50V7K CA50 1 1 (PIN 48) ALC259-VB5-GR_QFN48_7X7 CA49 1 Function PORT-I (PIN 32, 33) place close to chip 40 41 32 33 SENSE B 1 CA6 Codec Signals 39.2K 5.1K 2 10U_0805_10V4Z 2 2 2 2 10U_0805_10V4Z 0.1U_0402_16V4Z HP_OUT_L HP_OUT_R SDATA_OUT 2 @ RA26 10_0402_5% 25 SPK_OUT_L+ SPK_OUT_L- MIC1_L MIC1_R UA1 AVDD2 46 39 LINE1_L LINE1_R for EMI request AZ_BITCLK_HD PVDD2 9 1 1K_0402_5% @ 1 2 MIC1_R_R PVDD1 RA23 MIC1_R 0.1U_0402_16V4Z 2 DVDD Ext. Mic 30 MIC1_R CA64 1 DVDD_IO +MIC1_VREFO_R 2.2K_0402_5% 2 0.1U_0402_16V4Z 2 +AVDD 1 CA7 10U_0805_10V4Z 2 2 AVDD1 1 RA22 1 Impedance SENSE A RA11 2 1 0_0603_1% 1 @ CA60 +PVDD2 1 CA61 1 CA8 Sense Pin 2 10U_0805_10V4Z place close to chip +3VS_DVDD 10U_0805_10V4Z 2 2 place close to chip 2 1 CA1 +5VS CA43 2 10U_0805_10V4Z E 1 1 CA2 2 2 JA1 JUMP_43X39 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 CA44 CA56 1 RA1 2 1 0_0603_1% +3VS D 2 CA18 0.1U_0402_16V4Z 3 2 0_0603_5% EC_MUTE# 1 03/19 change to AGND. RA28 1 12 INT_MIC_CLK RA45 4.7K_0402_5% INT_MIC_CLK_R 2 33_0402_5% CA66 33P_0402_50V8K 1 2 2 12/16 for EMI request 03/19 common design. EC control EC_MUTE# behavior :tri-state / low-state (4.75V(4.56~4.94V)) 300mA +5VALW W=40Mil @ UA2 2 0.1U_0402_16V4Z 1 2 RA30 26,31,34,37,40 SUSP# 1 2 0_0402_5% 3 IN OUT 5 BYP 4 CA68 1 GND SHDN @ G9191-475T1U_SOT23-5 1 1 @ CA70 0.1U_0402_16V4Z MV：Reserved 4.75V LDO 2 @CA69 @ CA69 1 2 2.2U_0805_16V4Z @ CA67 4 0.1U_0402_16V4Z 2 4 / Compal Secret Data Security Classification 2010/04/12 Issued Date 2009/04/14 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 12/22 reserve for power saving A 01/20 change to +AVDD. +AVDD B C D Title Compal Electronics, Inc. HD Audio ALC272 Codec Size Document Number Custom Date: Rev 1.0 NDU00_LA-6031P M/B Monday, April 12, 2010 Sheet E 29 of 45 A B C USB+Audio FFC conn Pin=20pin, pitch=0.5 D E Speaker Connector 01/30 New JP2 Layout symbol reverse old conn, reserse the pin define 1 1 placement near Audio Codec +USB_VCCA JP2 19 19 19 19 USB20_P1 USB20_N1 USB20_P1 USB20_N1 USB20_P0 USB20_N0 USB20_P0 USB20_N0 29 29 NBA_PLUG MIC_SENSE 29 29 29 29 HP_R HP_L MIC1_R MIC1_L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 MIC1_R MIC1_L 01/30 Pin definition EMI request. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND GND DA4 3 1 RA13 29 SPKL+ SPKL+ 02/04 change back to 20 pins. SPKL- 29 SPKR+ SPKL- SPKR+ 31 USB_EN# USB_EN# +5VALW For EMI request GND IN IN EN# OUT OUT OUT OC# 8 7 6 5 TPS2061IDGNR_MSOP8 R1491 1 1 2 3 4 2 100K_0402_5% 1 2 3 4 5 6 GND GND +USB_VCCA U47 2 C869 1 1000P_0402_50V7K USB_OC#0 19,31 1 CA20 RA14 @ 10U_0805_10V4Z 2 2 1 0_0603_1% RA15 2 1 0_0603_1% 2 1 MIC1_L MIC1_R HP_L HP_R 29 SPKR- SPKR- JSPK1 SPK_R1 SPK_R2 SPK_L1 SPK_L2 SPK_L2 1 2 3 4 5 6 SPK_R1 CA26 RA16 @ 10U_0805_10V4Z 2 2 1 0_0603_1% 1 2 3 4 GND1 GND2 ACES_88231-04001 DA5 3 2 1 1 2 3 4 5 6 7 8 CA24 1U_0402_6.3V4Z @ 1 CA25 @ 10U_0805_10V4Z 2 ACES_87151-2005N @ W=60mils 1.4A +5VALW PACDN042Y3R_SOT23-3 1 29 2 SPK_L1 1 CA19 @ 10U_0805_10V4Z 2 JP3 2 2 1 0_0603_1% 1 1 CA27 1U_0402_6.3V4Z @ 2 PACDN042Y3R_SOT23-3 2 SPK_R2 12/16 Fine tune SPK_L1,SPK_L2,SPK_R1 and SPK_R2 for SPK CONN@ JST_SM06B-XSRK-ETB(HF) C870 4.7U_0805_10V4Z 2 @ 12/19 Reserved JP6 for audio test 01/26 common design pull high 3 3 4 4 / Compal Secret Data Security Classification 2010/04/12 Issued Date 2009/04/14 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. AMP/Audio Jack/HP/SPEAKER/VR Size Document Number Custom Date: Rev 1.0 NDU00_LA-6031P M/B Monday, April 12, 2010 Sheet E 30 of 45 5 4 3 +3VL_EC 0.1U_0402_16V4Z 1 1 1 C398 C399 2 0_0805_5% 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 1 2 C400 C401 2 2 0.1U_0402_16V4Z C397 C403 1000P_0402_50V7K 1 1 1000P_0402_50V7K U15 1 CLK_PCI_EC D R298 @ 10_0402_5% 2 1 2 CLK_PCI_EC 12 13 ECRST# 37 20 38 19 CLK_PCI_EC 5,19,26,27,28,32 PLT_RST# 1 0.1U_0402_16V4Z 2 C448 1 KB_RST# 0.1U_0402_16V4Z 2 C449 1 PLT_RST# 0.1U_0402_16V4Z 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 77 78 79 80 SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 C 1013 EMC request 25 KSI[0..7] KSI[0..7] 25 KSO[0..17] KSO[0..17] RP7 1 2 3 4 +3VL +3VS 8 7 6 5 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 36 36 16,32 16,32 2.2K_0804_8P4R_5% 17 PM_SLP_S3# 17 PM_SLP_S5# 20 EC_SMI# 20 THM_ALT# +3VL 1 R301 1 R303 B KSO1 2 47K_0402_5% 2 47K_0402_5% KSO2 17 PCH_SUSPW RDN 12 INVT_PW M 9 FAN_SPEED1 32 HDPLOCK 26 E51_TXD 26 E51_RXD 33 ON/OFFBTN# 33 PW R_SUSP_LED# 25 NUM_LED# to avoid EC entry ENE test mode VTTP_EN 100K_0402_5% 1 2 E51_TXD 17 +3VALW 122 123 VTTP_EN 39 EN_DFAN1 9 IREF 37 CHGVADJ 37 97 98 99 109 VGATE W OL_EN# PW RME_CTRL# LID_SW # SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS# 119 120 126 128 R_SPI_CLK 0_0402_5% R271 CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 73 74 89 90 91 92 93 95 121 127 EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 CIR_IN 1 EC_MUTE# 29 USB_EN# 30 USB_CHG_EN# 24 HDPINT 32 TP_CLK 33 TP_DATA 33 2 R1444 FSTCHG BATT_FULL_LED# CAPS_LED# PW R_ON_LED# SYSON VR_ON ACIN_D C903 0.1U_0402_16V4Z 32.768KHZ_12.5PF_Q13MC14610002 1 5 1 P OE# 2 A +5VS TP_CLK 1 4.7K_0402_5% TP_DATA 1 4.7K_0402_5% +3V_ALW VGATE 17,42 W OL_EN# 27 PW RME_CTRL# 15 LID_SW # 33 2 LID_SW # 2 47K_0402_5% EC_SI_SPI_SO 32 EC_SO_SPI_SI 32 R271 1 SPI_CS# 1 10K_0402_5% 2 R300 2 R302 SPI_CLK 2 1 C352 32 32 SYSON 1 R305 2 4.7K_0402_5% +5VL SLP_CHG_M4_EC 24 FSTCHG 37 BATT_FULL_LED# 33 CAPS_LED# 25 BATT_LOW _LED# 33 PW R_ON_LED# 33 SYSON 40 VR_ON 42 +3VL 1 2 R306 330K_0402_5% EC_RSMRST# 100 EC_RSMRST# 17 EC_LID_OUT# D12 101 EC_LID_OUT# 16 EC_ON ACIN_D 102 2 1 EC_ON 33 103 SLP_CHG_M3_EC 24 PM_PW ROK CH751H-40PT_SOD323-2 104 R1503 1 2 0_0402_5% PM_PW ROK 17 R1504 22_0402_5% BKOFF# 105 2 1 BKOFF# 12 W L_OFF# 106 W L_OFF# 26 CURS_LED# 107 CURS_LED# 25 03/23 add current resistance. EC_SLE 108 17,33,35 B +3VL GPI PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 110 112 114 115 116 117 118 V18R 124 SLP_CHG# PM_SLP_S4# 17 UMA_ENBKL 18 USB_OC#1 19,24 SLP_CHG# 24 SUSP# 26,29,34,37,40 PBTN_OUT# 17 USB_OC#0 19,30 SLP_CHG# SUSP# +EC_V18R +3VALW R1474 C408 4.7U_0805_10V4Z 1 @ 2 R1428 1 10K_0402_5% R423 2 1 10K_0402_5% EC_SEL EC Version High KB926D3 Low KB926E0 2 100K_0402_5% EC_SLE KB926QFE0_LQFP128_14X14 R1475 1 2 100K_0402_5% 2 0.1U_0402_16V4Z SPI_CLK 1 L40 2 1 0_0603_5% 2 C450 10P_0402_50V8J A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date @ ACIN 12/16 EMI request U60 @ SN74AHCT1G125GW _SOT353-5 EC_RSMRST# Y 4 03/10 for Y4 remove. R1499 1 C 01/27 toshiba request 1 R304 Deciphered Date 2010/01/23 Title ENE-KB926 RevD2 3 @ 0_0603_5% 2 G R1498 10K_0402_5% 2 100P_0402_50V8J 2 100P_0402_50V8J HDPACT 32 SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0 XCLK1 XCLK0 L39 +3VL_EC 1 @ 2 2 5 PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A +EC_AVCC 15P_0402_50V8J OSC NC 4 OSC NC Y4 EC_MUTE# USB_EN# USB_CHG_EN# HDPINT TP_CLK TP_DATA HDPACT BATT_TEMPA 1 C405 ACIN_D 1 C406 37 37 12/17 EC recommend R1497 2 0_0402_5% @1 SUS_CLK +3VALW C410 3 2 15P_0402_50V8J 2 83 84 85 86 87 88 SPI Flash ROM GPIO ON/OFFBTN# 1 1 1 C409 PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F ADP_I ADP_V SPI Device Interface SM Bus R1500 @ 1 2 100K_0402_5% @ 10M_0402_5% A 68 70 71 72 37 BATT_TEMPA 36 ADP_I ADP_V Add pull high_1130 2CRY2 1 6 14 EC_SMI# 15 THM_ALT# 16 17 18 PCH_SUSPW RDN 19 INVT_PW M 25 FAN_SPEED1 28 HDPLOCK 29 E51_TXD 30 E51_RXD 31 ON/OFFBTN# 32 PW R_SUSP_LED# 34 NUM_LED# 36 CRY1 CRY2 R1459 10K_0402_5% @ C410 20P 50V J NPO 0402 R311 CRY1 PM_SLP_S3# ACOFF DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F +3VL_EC 1 R310 100K_0402_5% 1 2 2 R309 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 ACOFF VTTP_EN EN_DFAN1 IREF CHGVADJ BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 PS2 Interface EC_BEEP# 29 BATT_TEMPA DA Output KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 PCH_OFF 34 EC_BEEP# 63 64 65 66 75 76 AD Input PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D 21 23 26 27 AGND 2 C407 20 EC_SCI# 33 W L_BT_LED# ECRST# PWM Output 69 R299 47K_0402_5% 2 1 INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 ECAGND +3VL GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC GND GND GND GND GND C404 @ 22P_0402_50V8J 1 2 3 4 5 7 8 10 20 GATEA20 20 KB_RST# 15,32 SERIRQ 15,26,32 LPC_FRAME# 15,26,32 LPC_AD3 15,26,32 LPC_AD2 15,26,32 LPC_AD1 15,26,32 LPC_AD0 11 24 35 94 113 D Use E0 AVCC VCC VCC VCC VCC VCC VCC for EMI request 1 2 0.1U_0402_16V4Z 1 2 C402 67 +3VL_EC R511 1 9 22 33 96 111 125 +3VL 2 +EC_AVCC 2 0_0402_5% 4 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Size Document Number Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet 1 31 of 45 A B C D E 1 1 SPI Flash (256KB) LPC Debug Port Socket: SP07000F500 & SP07000H900 Please place the PAD under DDR DIMM. +3VL H1 +3VS 20mils 1 C411 6 5 7 4 PLT_RST# 5,19,26,27,28,31 15,26,31 LPC_AD3 8 3 LPC_AD2 15,26,31 15,26,31 LPC_AD1 9 2 LPC_AD0 15,26,31 10 1 CLK_PCI_DDR 19 U16 8 0.1U_0402_16V4Z 2 3 7 31 SPI_CS# 1 31 6 SPI_CLK 5 31 EC_SO_SPI_SI VCC VSS 4 15,31 SERIRQ W HOLD 1 2 R312 0_0402_5% S C D Q 2 EC_SI_SPI_SO 31 15,26,31 LPC_FRAME# MX25L2005CMI-12G SO8 @ DEBUG_PAD 2 SPI_CLK 1 R314 2 10_0402_5% 1 C415 2 reserve for EMI 12/25 EMI request reserve. R313,C414 2 10P_0402_50V8J reserve for EMI, close to U22 G-Sensor RG2 @ 2 +3VS 1 +3VS_HDP 0_0603_5% CG12 1U_0402_6.3V4Z GSENSOR@ 2 UG3 1 1 3 2 3 VIN +3VS_HDP CH751H-40PT_SOD323-2 2 2 GSENSOR@ CG13 1U_0402_6.3V4Z 5 VOUT 1 GSENSOR@ GND SHDN# BP UG6 4 G9191-330T1U_SOT23-5 UG1 2 12 SELF_TEST +3VS_HDP 4 6 8 9 Vdd1 Vdd2 Voutx Vouty Voutz ST PD FS NC1 NC2 NC3 NC4 NC5 Rev GND1 GND2 VOUTXCG1 VOUTYCG2 VOUTZCG3 3 5 7 1 1 1 SELF_TEST 2 P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# 12 1 4.7K_0402_5% 3 RG4 2 GSENSOR@ 1GXOUT 4.7K_0402_5% 4 2 1ST@ 0.033U_0402_16V7K 2 1ST@ 0.033U_0402_16V7K 2 1ST@ 0.033U_0402_16V7K 5 RG5 2 GSENSOR@ 10 11 14 15 16 1GXIN 4.7K_0402_5% CG9 0.1U_0402_16V4Z UG4 2ND@ 2 1 VOUTX 2 CG10 0.1U_0402_16V4Z XOUT 2ND@ 2 1 VOUTY 3 CG11 0.1U_0402_16V4ZYOUT 2ND@ 2 1 VOUTZ 4 ZOUT 9 7 10 13 1 13 31 HDPINT RG6 2 GSENSOR@ 4.7K_0402_5% HDPINT RG7 2 GSENSOR@ 1K_0402_5% 1 8 1 9 CG7 0.1U_0402_16V4Z GSENSOR@ 2 HDPACT 3 31 RESET# P1_4/TXD0 XOUT/P4_7 RG9 47K_0402_5% GSENSOR@ 13 P1_3/KI3#/AN11/TZOUT 14 P1_2/KI2#/AN10/CMP0_2 15 HDPLOCK 31 VSS/AVSS XIN/P4_6 P4_2/VREF VCC/AVCC P1_1/KI1#/AN9/CMP0_1 MODE P1_0/KI0#/AN8/CMP0_0 P4_5/INT0#/RXD1 10 P1_7/CNTR00/INT10# 1 CG8 GSENSOR@ 0.1U_0402_16V4Z R5F211B4D34SP_LSSOP20 2 1STGSENSOR@ P3_3/TCIN/INT3#/SSI00/CMP1_0 P3_4/SCS#/SDA/CMP1_1 VOUTZ RG10 47K_0402_5% 2 1 GSENSOR@ 16 +3VS_HDP 17 VOUTX 18 VOUTY 1 2 CG6 0.1U_0402_16V4Z GSENSOR@ 19 20 EC_SMB_DA2 16,31 4 2ND@ 0G-DET SLEEP# G-SELECT ST VDD 6 NC NC NC NC NC 1 8 11 12 14 VSS 5 Compal Secret Data Security Classification 2010/04/12 Issued Date 2009/04/14 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MMA7360LR2_LGA14 A 6 7 +3VS_HDP SELF_TEST 11 RG3 2 GSENSOR@ 1 +3VS_HDP P1_6/CLK0/SSI01 1ST@ TSH35TR_LGA16 4 P3_5/SSCK/SCL/CMP1_2 GSENSOR@ 0.22U_0402_10V4Z +3VS_HDP +3VS_HDP 1 16,31 EC_SMB_CK2 CG14 2 1 2 GSENSOR@ DG1 1 1 +5VS B C D Title Compal Electronics, Inc. SPI/LPC/PS2/MDC/FM/CIR Size Document Number Custom Date: Rev 1.0 NDU00_LA-6031P M/B Monday, April 12, 2010 Sheet E 32 of 45 5 4 3 2 Power Button & Lid switch +3VALW JPB1 0.1U_0402_16V4Z @ C428 PCB R323 10K_0402_5% P-TW O_161011-04021 @ 2 ZZZ1 2N7002DW -T/R7_SOT363-6 5 EC_ON 2 31 PCB LA-6031P REV01 D 1 1 D Q20B 1 2 3 4 GND GND 4 1 2 3 4 5 6 ON/OFFBTN# 31 ON/OFFBTN# ISPD 35 3 51_ON# 1 01/27 change connector. Screw Hole Touch/B Connector H15 +5VS 31 31 31 TP_CLK TP_DATA R1485 LID_SW # 2 1 22_0402_5% TP_CLK TP_DATA LID_SW # H17 7 8 G1 G2 03/11 change connector. R1447 +3VS R1448 +5VS R1449 DC_IN PW R_ON_LED# SUSPEND_LED BATT_FULL_LED# BATT_LOW _LED# HDD_LED W IMAX_LED W L_BT_LED# MEDIA_LED 31 PW R_ON_LED# 31 PW R_SUSP_LED# 31 BATT_FULL_LED# 31 BATT_LOW _LED# 31 W L_BT_LED# H_2P6X2P1N @ H4 R1451 and R1543 change to 220 ohm. R1450 R1451 R1452 R1453 R1454 R1455 R1456 R1457 R1458 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 120_0402_5% 220_0402_5% 120_0402_5% 220_0402_5% 120_0402_5% 120_0402_5% 120_0402_5% 120_0402_5% 120_0402_5% 13 14 H_2P3 @ 1 H_2P3 @ 1 H_2P3 @ 1 1 1 1 H_2P3 @ H_2P3 @ H_2P1N @ @ 1 2 3 4 5 6 7 8 9 10 11 12 C H5 H_4P0 @ H6 H_4P0 @ H7 H_4P0 @ H_4P0 @ PCB Fedical Mark PAD FD1 @ FD2 @ 1 1102 change follow 3V or 5V. JLED1 1 2 3 4 5 6 7 8 9 10 11 12 H_2P3 @ H2 FD3 @ 1 +5V_ALW H14 CPU LED/B Connector 1 +3V_ALW 1 2 0_0402_5% @ 1 2 0_0402_5% 1 2 @ 0_0402_5% 1 2 0_0402_5% H13 01/26 change connector. 1030 reserve power R1446 H12 P-TW O_161021-06021_6P-T 12/24 Victor request 01/26 change to +5V_ALW H11 H_2P3X3P0 1 TP_DATA CM1293A-02SR SOT143-4 C H10 FD4 @ 1 1 1 2 H_2P3 @ 1 IO1 IO2 GND @ 1 VIN 3 1 2 3 4 5 6 1 4 H9 1 JTP1 1 2 3 4 5 6 1 TP_CLK 1 +3V_ALW D15 +5VS H8 01/27 toshiba request GND1 GND2 ACES_88231-12001 17,31,35 2 ACIN B B R326 @ DC_IN 2 0_0402_5% 2 3 +3VS 1 Q20A 2N7002DW -T/R7_SOT363-6 1 RC10 4.7K_0402_5% 4 Q23B 2N7002DW -T/R7_SOT363-6 +5VS 2 (Active Low,16mA) +5VALW 2 C871 0.1U_0402_16V7K Close to H10 1 MEDIA_LED 6 CR_LED# 28 5 1 1 2 C872 0.1U_0402_16V7K Close to H12 1 C873 0.1U_0402_16V7K Close to H13 ES2 del Q23 and add R236. 2 SATA_LED# 15 0120 for LED flash issue. 2 R324 1 10K_0402_5% 6 5 +5VS @ 2 LED_W IMAX# 26 A W IMAX_LED 3 HDD_LED 3 @ 6 5 +5VS @ 2 R325 1 10K_0402_5% 4 @ 1 Q22A 2N7002DW -T/R7_SOT363-6 4 Q22B 2N7002DW -T/R7_SOT363-6 1 Q21A 2N7002DW -T/R7_SOT363-6 @ R336 Q21B 2N7002DW -T/R7_SOT363-6 @ 1 2 R338 0_0402_5% 1 2 0_0402_5% A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Comm. SW/ Sub Conn./LEDS Size Document Number Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet 1 33 of 45 A B C +3VALW TO +3VS +3VALW D E +5VALW TO +5VS +1.5V to +1.5VS +5VALW Vgs=-0V,Id=9A,Rds=18.5mohm +3VS +5VS +1.5V 4.7U_0805_10V4Z +1.5VS 4.7U_0805_10V4Z +5V_ALW to +5VALW Transfer +5V_ALW C439 2 2 2 R335 820K_0402_5% +3V_ALW 1 2 1 2 1 @ 1 2 1 @ 2 1 1 PCH_OFF_R 5 C889 Q26B 2N7002DW -7-F_SOT363-6 2 @ 1 2 @ 3 @ 1 @ R1479 (5A,200mils ,Via NO.= 10) 3 1 C888 10U_0805_10V4Z C892 10U_0805_10V4Z 2 @ C887 0.1U_0402_16V4Z 1 @2 R1481 47K_0402_5% 4 1 200K_0402_5% R1478 1 SI7326DN-T1-E3_PAK1212-8 U49 1 2 5 3 2 C896 0.1U_0402_16V4Z @ 1 @ 0.01U_0402_25V7K 2 1PCH_OFF_R 2 10K_0402_5% @ Q26A 1 2 C884 0.1U_0402_16V7K 2 PCH_OFF 2 2 @ 1 C890 2 (OCP min=7.9A) @ For S3 CPU power saving +3VALW Reserve for EMI test 2 1 2 C883 0.1U_0402_16V7K 1 R1486 31 2 C882 0.1U_0402_16V7K 1 2 C881 0.1U_0402_16V7K C880 0.1U_0402_16V7K 2 @ +1.5VS 2 1 C886 10U_0805_10V4Z 4 @ 6 2 @ 2N7002DW-7-F_SOT363-6 12/21 EMI request +3VALW +VSB 1 10U_0805_10V4Z @ SUSP 5 2 2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6 @ JUMP_43X118 C885 0.1U_0402_16V4Z 1 2 @ 1 Q15B 0.01U_0402_25V7K 1 200K_0402_5% 2 SI7326DN-T1-E3_PAK1212-8 U48 1 2 5 3 R1480 47K_0402_5% C891 Q15A J3 @ JUMP_43X118 2 1 +3VALW J2 +VSB 1 R332 2 +VSB 220K_0402_5% 4 1 FDS6676AS 6 1 R329 +3V_ALW to +3VALW Transfer +5VALW 2 2 470_0805_5% 2 1 Q13B 1 1U_0402_6.3V4Z SI4800BDY_SO8 Q13A SUSP 5 2 2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6 C434 1 R334 200K_0402_5% @ 1 2 3 4 S S S G 2 2 C438 2 C433 D D D D 4 2 1 8 7 6 5 1 0.1U_0402_25V6 C437 +VSB Q14 470_0805_5% 1U_0402_6.3V4Z 1 R331 2 47K_0402_5% 6 1 R328 C440 Q11B 2 3 1 2 SI4800BDY_SO8 Q11A SUSP 2 5 2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6 1 2 3 4 4.7U_0805_10V4Z 2 S S S G 4 R333 330K_0402_5% +VSB D D D D Vgs=10V,Id=14.5A,Rds=6mohm 1 C432 1 6 1 C436 1 2 1 2 0.022U_0402_25V7K 4.7U_0805_10V4Z C435 1 R330 2 47K_0402_5% 8 7 6 5 1 1U_0402_6.3V4Z SI4800BDY_SO8 1 R327 1 2 2 C431 0.01U_0402_25V7K 2 4.7U_0805_10V4Z 1 2 3 4 2 S S S G Q12 3 1 1 D D D D C430 4 8 7 6 5 C429 1 4.7U_0805_10V4Z 470_0805_5% Q10 1 3 PS@ R337 100K_0402_5% 3 EMI_1224 +5VS +5VALW +VSB +3VL +5VS Q16B 2N7002DW -T/R7_SOT363-6 3 +3V_LAN 0.75VR_EN# 41 1 EMI_1102 PS@ @ C874 0.1U_0402_16V7K 4 2 C875 0.1U_0402_16V7K 2 C876 0.1U_0402_16V7K 1 2 +5VS C877 0.1U_0402_16V7K 1 3 +5VS @ 9,41 SUSP SUSP Q24A 2N7002DW -T/R7_SOT363-6 Q24B 2N7002DW -T/R7_SOT363-6 5 2 4 2 26,29,31,37,40 SUSP# SUSP 2 1 R341 100K_0402_5% PS@ another at page42 R342 10K_0402_5% 1 4 1 1 +5VS SUSP 2 R340 470_0805_5% PS@ R340 47_0805_5% 4 +5VS Q16A 2N7002DW -T/R7_SOT363-6 +5VALW For S3 CPU power saving +0.75VS 1 1 6 2 5 6 1 @ 0.75VR_EN 2 100K_0402_5% 1 1 2 1 R339 2 1 @ 2 2 1 1 2 C895 C447 0.1U_0402_16V7K 5,39 VTTPW ROK 0.1U_0402_16V7K 1 2 C894 C446 0.1U_0402_16V7K 0.1U_0402_16V7K 2 0.1U_0402_16V7K C445 0.1U_0402_16V7K C893 PS@ Close H8,H9,H11 and H14 each. EMI_1102 Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title DC-DC INTERFACE Size Document Number Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet E 34 of 45 A B C D VS VIN 1 N1 PR3 5.6K_0402_5% 2 - O 2 PC6 .1U_0402_16V7K PACIN 1 LM393DG_SO8 PACIN 37 1 + 2 17,31,33 PD1 GLZ4.3B_LL34-2 PR7 10K_0402_1% 2 1 PR8 10K_0402_1% +CHGRTC Vin Detector 3.3V 2 VIN 2 2 2 2 PC5 0.068U_0402_10V6K PR6 20K_0402_1% 3 1 ACIN PU1A 1 1 1 8 PR5 22K_0402_1% 1 2 2 PC4 100P_0402_50V8J PR4 10K_0402_1% 1 2 P 1 PR2 84.5K_0402_1% 2 1 2 @ PC17 680P_0402_50V7K 1 2 PC2 100P_0402_50V8J PC3 1000P_0402_50V7K 2 @ SINGA_2DW -0005-B03 1 4 2 - 1 - 3 2 2 @ PC21 680P_0402_50V7K + 1 1 PC1 1000P_0402_50V7K + 1 G DC_IN_S2 2 7A_24VDC_429007.W RML 1 1 1 DC_IN_S1 PJP1 4 PF1 DC301001M80 PR1 1M_0402_1% 1 2 VIN PL1 SMB3025500YA_2P 1 2 High 18.384 17.901 17.430 Low 17.728 17.257 16.976 1 1 PD3 RLS4148_LL34-2 CHGRTCP 2 PR11 200_0603_5% 1 2 PR10 68_1206_5% N1 3 1 1 VS 1 1 PD4 2 VIN N3 1 2 PR15 22K_0402_1% 1 RTC Battery 1 PR19 100K_0402_1% 1 2 +RTCBATT VL PR20 2.2M_0402_5% 2 1 2 +VTTP PJ3 1 2 1 1 1 D (100mA,40mils ,Via NO.= 2) +VTT (20A,800mils ,Via NO.= 40) +1.5VP 1 1 +VSB @ JUMP_43X39 2 1 1 +1.5V 1 2 1 1 +0.75VS 2 1 1 PACIN +3VL @ JUMP_43X39 2 (100mA,40mils ,Via NO.= 2) @ JUMP_43X118 (7.5A,300mils ,Via NO.=15) +GFX_COREP 1 2 Precharge detector 15.97V/14.84V FOR ADAPTOR (OCP min=9.67A) PJ7 PR27 47K_0402_1% PQ2 2 2 1 SSM3K7002FU_SC70-3 G PJ19 2 +3VLP PJ6 (120mA,40mils ,Via NO.= 1) 2 2 3 +5VL @ JUMP_43X39 (OCP min=28.72A) PJ5 2 1 PC12 1000P_0402_50V7K S +5V_ALW (OCP min=8.1A) +0.75VSP 1 PR24 499K_0402_1% PR26 191K_0402_1% 1 1 @ JUMP_43X118 2 2 PR25 @ 66.5K_0402_1% @ JUMP_43X118 (5A,200mils ,Via NO.= 10) 2 2 VL +CHGRTC PJ10 2 2 +5VALW P PQ3 DTC115EUA_SC70-3 3 2 1 PJ4 (OCP min=7.9A) 2 2 @ JUMP_43X118 (5A,200mils ,Via NO.= 10) PC13 1000P_0402_50V7K PJ14 PC11 1000P_0402_50V7K 1 PR23 10K_0402_0.1% 1 1 @ JUMP_43X118 1 2 3 2 PJ2 2 +3V_ALW 6 2 PJ1 5 - 2 LM393DG_SO8 3 + O 1 3 ACON 2 7 1 SP093MX0000 1 1 37 PU1B 2 EN0 2 38 8 PD5 RB715F_SOT323-3 @ MAXEL_ML1220T10 PC10 1U_0805_25V4Z 1 PR18 499K_0402_1% 2 PR22 560_0603_5% 1 2 P 1 N2 PR21 560_0603_5% 1 2 G 2 PC9 10U_0805_10V4Z 2 1 4 IN GND + PBJ1 2 1 OUT 1 3 G920AT24U_SOT89-3 2 PU2 3.3V 2 2 2 - PR17 200_0603_5% +VSBP B+ PR16 1K_1206_5% 1 +CHGRTC +5VALW P 2 PR14 1K_1206_5% 1 51_ON# +3VALW P 1 RLS4148_LL34-2 2 2 33 PC8 0.1U_0603_25V7K 2 PC7 0.22U_0603_25V7K 2 PR13 100K_0402_1% 2 2 PR12 1K_1206_5% 1 2 PR9 PQ1 68_1206_5% TP0610K-T1-E3_SOT23-3 2 2 BATT+ 1 1 PD2 RLS4148_LL34-2 +GFX_CORE 1 1 @ JUMP_43X118 @ JUMP_43X79 4 4 (1.3A,52mils ,Via NO.= 3) PJ13 2 2 1 1 @ JUMP_43X118 (12A,480mils ,Via NO.=24) PJ8 2 +1.8VSP 2 1 1 @ JUMP_43X79 +1.8VS (OCP min=15.6A) Issued Date (1.7A,68mils ,Via NO.= 4) 2010/04/12 Deciphered Date 2010/10/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. (OCP min=3A) A Compal Electronics, Inc. Compal Secret Data Security Classification B C Title DCIN / DETECTOR Size Document Number Rev 1.0 LA-6031P Date: Sheet Monday, April 12, 2010 D 35 of 45 A B C D PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 56 degree C 1 10A_125V_451010MRL PF2 1 2 1 2 PR30 47K_0402_1% PH2 near main battery CONN: BAT.thermal protection at 78 degree C Recovery at 42 degree C BATT+ @ PC18 0.1U_0402_25V6K 1 +3VLP PC16 1000P_0402_50V7K 2 2 PR29 1K_0402_1% 1 1 2 BATT_P3 BATT_P4 BATT_P5 EC_SMDA EC_SMCA 1 BATT_S1 1 2 3 4 5 6 7 8 9 PC15 0.01U_0402_25V7K 1 PR33 1K_0402_1% VL 2 PR34 22K_0402_1% PR31 34.8K_0402_1% 2 PR36 6.49K_0402_1% 2 1 2 +3VLP PR35 10.2K_0402_1% 1 3 2 BATT_P3 BATT_P4 BATT_P5 EC_SMDA EC_SMCA PC14 0.1U_0603_25V7K 1 PR40 100_0402_1% 8 GND RHYST1 7 3 OT1 TMSNS2 6 4 OT2 RHYST2 5 2 PH1 100K_0402_1%_NCP15W F104F03RC 1 BATT_TEMPA 31 PR32 15.4K_0402_1%~N G718TM1U_SOT23-8 1 1 VCC TMSNS1 2 2 2 2 @ SUYIN_200045MR009G171ZR PR39 100_0402_1% 1 1 PR38 1K_0402_1% 1 PU3 2 EC_SMB_DA1 31 2 2 GND GND GND GND BATT_S1 1 2 3 4 5 6 7 8 9 1 10 11 12 13 1 2 3 4 5 6 7 8 9 1 PD7 2 PJSOT24C_SOT23-3 3 PJP3 1 PD8 PJSOT24C_SOT23-3 1 For 13.3" 2 @ SUYIN_200045MR009G171ZR 2 GND GND GND GND 1 2 3 4 5 6 7 8 9 PL2 SMB3025500YA_2P 1 2 2 PJP2 10 11 12 13 1 VMB For 11.6" 1 EC_SMB_CK1 31 VS_ON PH2 100K_0402_1%_NCP15W F104F03RC 2 38 PQ5 TP0610K-T1-E3_SOT23-3 3 B+ +VSBP 1 2 PR46 22K_0402_1% 1 2 1 2 2 1 2 @ PC20 0.1U_0603_25V7K VL PC19 0.22U_0603_25V7K 3 2 1 PR44 100K_0402_1% 3 @ PR48 0_0402_5% 2 1 1 D 3 POK S PQ6 SSM3K7002FU_SC70-3 2 G 2 1 17,38 @ PC22 .1U_0402_16V7K 1 PR47 100K_0402_1% 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Deciphered Date 2010/10/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title BATTERY CONN / OTP Size Document Number Rev 1.0 LA-6031P Date: Monday, April 12, 2010 Sheet D 36 of 45 A B C D B+ PQ7 23 3 EN CSON 22 4 CELLS CSOP 21 5 ICOMP CSIN 20 VCOMP CSIP 19 ICM PHASE 18 LX_CHG 8 VREF UGATE 17 DH_CHG 9 CHLIM BOOT 16 10 ACLIM VDDP 15 11 VADJ LGATE 14 GND PGND 13 10U_1206_25V6M PC88 4 4.7U_0805_25V6-K 2 1 PC25 2 4.7U_0805_25V6-K 2 1 PC24 10U_1206_25V6M 1 4.7U_0805_25V6-K 2 1 2 12 VIN 1 PD13 2 1 2 DL_CHG 26251VDD 2 PACIN G PQ16 SSM3K7002FU_SC70-3 PR75 4.7_0603_5% PC44 4.7U_0805_6.3V6K 1 BATT+ 4 2 3PC41 10U_1206_25V6M 2 1 PR69 4.7_1206_5% PR67 0.02_1206_1% CHG PC40 10U_1206_25V6M 2 1 4 2 1 PL3 10U_LF919AS-100M-P3_4.5A_20% 1 2 1 PD14 RB751V-40TE17_SOD323-2 1 2 5 6 7 8 PC39 0.1U_0603_25V7K BST_CHGA 2 1 6251VDDP S 2 2 2 PQ17 AO4466_SO8 AO4466_SO8 1 2 D PC32 0.1U_0603_25V7K 4 PR65 2.2_0603_1% PR71 0_0603_5% BST_CHG 1 1 3 CSON 1 2 PR61 20_0603_5% 1 2 PC31 0.047U_0603_16V7K CSOP 1 2 PR62 20_0603_5% 2 1 PR63 PC36 20_0603_5% 0.1U_0603_25V7K 1 2 5 6 7 8 PR74 20K_0402_1% PR58 200K_0402_1% 1 2 1SS355_SOD323-2 3 2 1 2 6251aclim ACOFF 2 PC42 680P_0603_50V8J 3 PR72 26.7K_0402_1% 6251VREF 1 2 1 1SS355_SOD323-2 1 DCIN ACSET ACPRN PQ19 PR73 100K_0402_1% 2 1 1 3 VDD 2 3 2 1 ACOFF 6251VREF VIN PD11 PQ15 DTC115EUA_SC70-3 2 ACOFF PC30 0.1U_0603_25V7K 2 1 1 IREF DCIN 24 6 2 PR70 31 174K_0402_1% 2 1 1 31 PU5 1 PR66 47K_0402_1% 2 7 2 @ PC37 100P_0402_50V8J 1 2 PC38 .1U_0402_16V7K ADP_I 2 31 1 1 PC43 0.01U_0402_25V7K 2 1 PQ20 DTC115EUA_SC70-3 1 6.81K_0402_1% 2 SUSP# 26,29,31,34,40 2 0.01U_0402_25V7K 2 1 1 3 ACON PR64 PR56 10K_0402_1% RB715F_SOT323-3 S PR68 22K_0402_5% 1 2 1 PACIN PC35 1 2 6800P_0402_25V7K 2 PR53 47K_0402_1% 1 2 FSTCHG 2 1 1 PQ18 SSM3K7002FU_SC70-3 PC28 2.2U_0603_6.3V6K 2 1 1 2 PC34 1 D 2 G 6251_EN 1 PD10 3 @ PC33 680P_0402_50V7K 1 2 2 35 PR60 100K_0402_1% 2 CSON 35 PR55 100K_0402_1% 2 1 2 1 2 PC29 .1U_0402_16V7K PR59 150K_0402_1% PQ12 DTC115EUA_SC70-3 6251VDD PR57 10K_0402_1% 2 1 FSTCHG DCIN 1 PR54 100K_0402_1% 1 S PACIN CSIN 2 2 1 2 31 PQ14 SSM3K7002FU_SC70-3 1 1 4 1 P3 1 1 PQ13 DTC115EUA_SC70-3 D 2 G 2 PC23 @ JUMP_43X118 PC46 2 3 PD12 1SS355_SOD323-2 1 2 3 1 2 3 4 2 PQ10 TP0610K-T1-E3_SOT23-3 PR51 10_0603_5% 3 1 1 2 2 PR52 47K_0402_1% PC26 5600P_0402_25V7K PC27 0.1U_0603_25V7K 2 1 CSIP PR50 200K_0402_1% 2 1 PQ11 DTA144EUA_SC70-3 8 7 6 5 PJ9 8 7 6 5 1 3 1 AO4407A_SO8 10U_1206_25V6M 2 1 PQ9 1 2 3 1 2 3 4 8 7 6 5 CHG_B+ PC47 PQ8 AO4435_SO8 VIN B+ PR49 0.033_1206_1% 3 P3 1 P2 AO4435_SO8 1 2 3 ISL6251AHAZ-T_QSOP24 1 31 CHGVADJ PR76 15.4K_0402_1% 1 2 PR77 31.6K_0402_1% 3 VIN 1 2 3 PR78 309K_0402_1% CP= 92%*Iada; CP=2.178A 2 Iada=0~2.368(45W) ADP_V 31 PR72=26.7k PR80 47K_0402_1% PR49=0.033 PC45 .1U_0402_16V7K 2 2 Vaclim=1.08V(65W) 1 1 CP mode PR79 10K_0402_1% 1 2 CC=0.25A~3A CHGVADJ=(Vcell-4)*9.445 IREF=1.096*Icharge Vcell IREF=0.254V~3.048V 4V VCHLIM need over 95mV 4.2V 1.882V 4.35V 3.2935V 4 CHGVADJ 0V 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Deciphered Date 2010/10/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title CHARGER Size Document Number Rev 1.0 LA-6031P Date: Monday, April 12, 2010 Sheet D 37 of 45 5 4 3 2 1 2 1 PC48 1U_0603_10V6K 2VREF_51125 D D D S 3 S 19 LG_5V +5VALWP 1 + 2 PC68 .1U_0402_16V7K PC63 150U_V_6.3VM_R18 1 1 2 PC62 680P_0603_50V8J 3 2 1 PQ24 AON7702L_DFN8-5 PR84 4.7_1206_5% 2 1 2 PC66 .1U_0402_16V7K VL 2 3 2 1 5 VCLK 18 EN0 4 1 13 C PL6 4.7UH_PCMC063T-4R7MN_5.5A_20% 1 2 TPS51125RGER_QFN24_4X4 2 2VREF_51125 4 17,36 1 DRVL1 POK 2 DRVL2 PR96 @ 0_0402_5% 5 1 2 12 1 PC52 10U_1206_25V6M 1 2 LX_5V B++ PQ37 SSM3K7002FU_SC70-3 2 G PC51 2200P_0402_50V7K ENTRIP1 UG_5V 20 2 PC61 0.1U_0603_25V7K 2 G 1 1 D PQ36 SSM3K7002FU_SC70-3 1 2 3 21 LL1 ESR = 18m Ohm 3 B ENTRIP1 VFB1 DRVH1 LL2 2 2 VREF DRVH2 11 VREG5 10 1 ENTRIP2 4 PR93 PC55 2.2_0603_1% .1U_0402_16V7K BST_5V 1 2 1 2 PC60 4.7U_0805_10V6K ENTRIP1 Total Capacitor = 150 uF VFB2 22 PR94 499K_0402_1% 1 2 PR95 100K_0402_5% F = 305kHz TONSEL 23 VBST1 EN0 1 Imax = 3.5A B+ 1 2 3 2 35 PC57 1U_0402_6.3V6K 4 5 PGOOD VBST2 1 1 2 3 AON7702L_DFN8-5 PC58 680P_0603_50V8J 2 1 + 5 PR83 4.7_1206_5% 2 1 PC56 150U_V_6.3VM_R18 1 2 PC67 @.1U_0402_16V7K Ipeak = 5A 1 LG_3V PQ23 PQ22 AON7408L_DFN8-5 VREG3 VIN 9 PR91 121K_0402_1% 2 24 17 8 B++ VO1 16 VO2 GND 7 SKIPSEL PR92 2 1 2 BST_3V 2.2_0603_1% PC54 UG_3V .1U_0402_16V7K LX_3V 1 PL5 4.7UH_PCMC063T-4R7MN_5.5A_20% 1 2 ENTRIP2 P PAD 4 C +3VALWP 6 PU6 25 1 15 2 AON7408L_DFN8-5 PR90 121K_0402_1% 1 2 PC53 4.7U_0805_10V6K 2 1 PQ21 PC65 .1U_0402_16V7K 1 5 1 2 PC50 10U_1206_25V6M 1 2 1 2 PC64 @ 1U_0603_25V6K PR89 19.6K_0402_1% 1 2 +3VLP 2 PC49 2200P_0402_50V7K 1 B+ PR88 20K_0402_1% 1 2 ENTRIP2 HCB4532KF-800T90_1812 PR87 30K_0402_1% 1 2 14 B++ PL4 PR86 13K_0402_1% 1 2 @ Ipeak = 5A B Imax = 3.5A F = 245kHz Total Capacitor = 150 uF VS_ON PQ38 DTC115EUA_SC70-3 2 2 1 PR85 42.2K_0402_1% 3 2 PR82 100K_0402_1% 1 1 2 VS @ PC59 0.01U_0402_16V7K 36 ESR = 18m Ohm 1 PR81 100K_0402_1% 1 2 VL A A Compal Electronics, Inc. Compal Secret Data Security Classification 2010/04/12 Issued Date Deciphered Date 2010/10/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title +5VALWP/+3VALWP Size Document Number Rev 1.0 LA-6032P Date: Monday, April 12, 2010 Sheet 1 38 of 45 A C D PL7 HCB2012KF-121T50_0805 1+VTTP_B+ VTTPW ROK +5VS 1 5,34 PR102 3.4K_0402_1% 4 VCC BST_+VTTP PR106 4.7_0603_5% 1 2 +VTTP_VCC 5 DH_+VTTP 1 2 BOOT UG 15 PR105 0_0402_5% PQ26 TPCA8030-H_SOP-ADV8-5 4 PVCC 14 LG 13 PGND 12 1 2 PC73 2.2U_0603_6.3V6K DL_+VTTP 3 3 2 1 +VTTP +VTTP 1 1 + PR107 4.7_1206_5% 2 2 1 2 4 +1.05V PC77 680P_0603_50V8J VO 2 PR108 4.99K_0402_1% 10 9 FB @ SE_+VTTP 1 2 1 @ PC78 0.01U_0402_16V7K @ PC79 33P_0402_50V8J 2 1 @ 7 6 2 1 PR109 0_0402_5% PR110 33.2K_0402_1% 2 1 2 1 PC80 2200P_0603_50V7K 1 2 1 PC76 .1U_0402_16V7K 31 VTTP_EN 11 PQ27 ISEN FSET EN FB_+VTTP 5 PR111 57.6K_0402_1% 2 1 NC 2 TPCA8028-H_SOP-ADVANCE8-5 5 2 APW 7138NITRL_SSOP16 1SS355_SOD323-2 @ PD15 8,43 GFXVR_EN PL8 1.0UH_PCMC104T-1R0MN_20A_20% 1 2 1 PC74 2.2U_0603_6.3V6K 2 2 PC75 330U_D2E_2.5VM_R9M VIN +5V_ALW 1 PC72 0.1U_0603_25V7K 3 2 1 3 +VTTP_VCC PGOOD GND PU7 DH_+VTTP PR104 4.53K_0402_1% 16 2 PHASE 2.43K_0402_1% PR125 1 LX_+VTTP 2 1 1 2 PR103 2.2_0603_1% 1 2 2 VTTPW ROK_CPU 5 2 2 1 PC69 4.7U_0805_25V6-K 2 1 PC70 4.7U_0805_25V6-K 2 1 2 1 8 B+ PC71 4.7U_0805_25V6-K 1 B Ipeak = 20A @ 2 PR112 3.32K_0402_1% 1 1 1 2 PR114 4.42K_0402_1% 1 1 Imax = 14A 2+VTTP PR113 0_0402_5% 2 PR115 10_0402_5% 2 PR116 10_0402_5% 3 F = 231kHz VTT_SENSE 8 Total Capacitor = 990 uF VSS_SENSE_VTT 8 ESR = 3m Ohm 4 4 Compal Secret Data Security Classification Issued Date 2010/04/12 Deciphered Date 2010/01/23 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title Compal Electronics, Inc. +VTTP Size Document Number Rev 1.0 NDU00_LA-6031P M/B Date: Sheet Monday, April 12, 2010 D 39 of 45 5 4 3 2 1 PL9 HCB2012KF-121T50_0805 PQ28 AO4466_SO8 3 2 1 VDDP 10 PR122 18K_0402_1% LGATE 9 DL_1.5V 1 11 LX_1.5V 1 PR120 4.7_1206_5% 12 CS +5V_ALW 2 PQ29 AO4712_SO8 1 + 2 NC 2 4 RT8209BGQW _W QFN14_3P5X3P5 2 7 PHASE +1.5VP PC89 4.7U_0805_10V6K PC85 220U_6.3V_M PGOOD 13 1 FB 6 0.1U_0603_25V7K UGATE 2 5 DH_1.5V 2 5 6 7 8 VDD PL10 1.8UH_SIL104R-1R8PF_9.5A_30% 1 2 PC84 1 BOOT VOUT 4 14 15 1 3 2 C TON 2 PR119 2.2_0603_1% 1 1 PC86 4.7U_0603_6.3V6K 2 8 PR121 100_0603_1% 1 2 +5V_ALW EN/DEM PU8 GND 2 @PC83 @ PC83 .1U_0402_16V7K B+ D Ipeak = 7.5A PC87 680P_0603_50V8J BST_1.5V 1 PGND SYSON 1 4 3 2 1 PR118 0_0402_5% 1 2 1 31 PR117 255K_0402_1% 1 2 2 PC82 4.7U_0805_25V6-K 2 5 6 7 8 1 D PC81 4.7U_0805_25V6-K 2 1 1.5V_B+ C Imax = 5.25A F = 313kHz PR123 10K_0402_1% 1 2 PR124 10K_0402_1% 2 1 Total Capacitor = 550 uF ESR = 6.6m Ohm PR192 0_0402_5% 1 2 SUSP# 26,29,31,34,37 2 6 TP 11 MP2121DQ-LF-Z_QFN10_3X3 @ PR196 4.7_1206_5% 2 PC138 22U_0805_6.3V6M POK 1 7 F =1.5MHz +1.8VSP 2 BS IN 1 5 8 Total Capacitor =44 uF 1 IN SW PL15 2.2UH_SILM320A-2R2_1.6A_30% 1 2 PC137 22U_0805_6.3V6M 2 PR195 0_0402_5% 4 GND 9 2 1 2 1 SW Imax = 5.25A 10 2 1 GND 3 EN/SYNC 1 2 FB 2 PD17 B340A_SMA2 1 2 1 PC136 10U_0805_10V4Z 2 @ JUMP_43X39 PC135 10U_0805_10V4Z 1 2 2 PC134 0.1U_0402_25V6 2 1 +5V_ALW Ipeak =1.7A PU9 PC133 0.1U_0402_16V7K 1 PJ12 @PC132 @ PC132 0.1U_0402_16V7K 1 +1.8VSP PR193 316K_0402_1% 1 PR194 402K_0402_1% 2 1 1 B 2 B ESR = 2.5m Ohm PC139 680P_0603_50V7K A A Compal Secret Data Security Classification Issued Date 2010/04/12 Deciphered Date 2010/10/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. +1.5VP/+1.8VSP Size Document Number Custom Date: Monday, April 12, 2010 Rev 1.0 NDU00_LA-6031P M/B Sheet 1 40 of 45 A B C D 1 1 +1.5V PJ11 @ JUMP_43X79 1 VCNTL 6 GND NC 5 3 VREF NC 7 4 VOUT NC 8 TP 9 +5V_ALW 1 1 VIN 2 2 2 PR128 1K_0402_1% 1 2 9,34 SUSP @ PR129 0_0402_5% 1 2 PU10 4.7U_0805_6.3V6K PC96 1 2 2 1 PC95 1U_0603_10V6K 1 +0.75VSP 2 1 2 1 PC98 0.1U_0402_10V7K S PR131 1K_0402_1% 2 1 3 2 PC97 .1U_0402_16V7K D 2 G 1 34 0.75VR_EN# PR130 0_0402_5% 1 2 PQ30 SSM3K7002FU_SC70-3 G2992F1U_SO8 PC99 10U_0805_6.3V6M 2 2 3 3 4 4 Compal Secret Data Security Classification Issued Date 2010/04/12 Deciphered Date 2010/10/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title Compal Electronics, Inc. 0.75VSP Size Document Number Rev 1.0 NDU00_LA-6031P M/B Date: Sheet Monday, April 12, 2010 D 41 of 45 A B C D E F G H +VTTP 8 1 B+ 4 33 @ PC140 47U_25V_M PC103 47U_25V_M 1 2 + 2 2 +CPU_CORE 1 PL12 0.36UH_PCMC104T-R36MN1R105_30A_20% 1 2 1 2 PR148 4.7_1206_5% 1 17 PQ31 TPCA8030-H_SOP-ADV8-5 5 1 + 2 PC111 680P_0603_50V7K Ipeak =27A Imax = 18.9A F =350kHz PH3 220K_0402_5%_ERTJ0EV224J~D 1 2 Total Capacitor =1320 uF ESR = 2.25m Ohm Place RTH1 close to inductor on the same layer 1 1 1 PC113 560P_0402_50V7K PC112 1000P_0402_50V7K PR159 165K_0402_1% 2 2 2 2 2 PC108 2.2U_0603_10V6K 3 2 1 CSCOMP CSFB CPU_DRVL 18 16 15 CSREF RT LLINE 13 12 +5VS 1 CPU_RAMP 20 19 4 1 2 CPU_RAMP-1 1 3 PR160 95.3K_0603_1% 1 2 PC114 1000P_0402_50V7K 2 Connect to input caps 1 8 8 VCCSENSE VSSSENSE +CPU_B+ AGND CPU_SW PR157 71.5K_0402_1% 2 1 PR156 422K_0402_1% IREF 9 PR153 147K_0402_1% 1 2 CPU_RPM CPU_CSCOMP 1 PR152 80.6K_0402_1% CPU_IREF 1 2 2 2 1 1 3 AGND CPU_DRVH 21 CPU_CSCOMP PR155 0_0402_5% PR161 1K_0402_1% 2 1 CPU_CSFB PR158 0_0402_5% CPU_CSCOMP Avoid high dV/dt RAMP ILIM PR150 20K_0402_1% 14 2 PR151 5.76K_0402_1% DRVL PGND 2 PC110 470P_0402_50V8J PU11 GPU CPU_ILIM 8 PR149 1K_0402_1% PVCC COMP 11 1 7 FB CPU_RT 2 2CPU_COMP-1 1 5 CPU_COMP 6 RPM 1 PC109 47P_0402_50V8J 10 CPU_FB 2 1 1 PC107 220P_0402_50V7K ADP3211AMNR2G_QFN32_5X5 22 PR147 PC105 2.2_0603_1% 0.22U_0603_25V7K 2CPU_BOOST-1 1 2 2 SW FBRTN 23 CPU_BOOST 1 PQ32 TPCA8028-H_SOP-ADVANCE8-5 CLKEN# 4 24 3 2 1 DRVH 3 2 12 CLK_ENABLE# 2 2 1 BST IMON PR154 261K_0402_1% 1 2 PC106 1000P_0402_50V7K 2 PWRGD 2 5 26 25 VID6 VID5 27 VID4 VID3 28 29 VID2 VID1 1 VCC 1 PR146 10K_0402_1% PC104 1U_0805_25V6K 2 CPU_VCC 1 2 VID6 VID5 VID4 VID3 VID2 VID1 30 31 32 EN VID0 +3VS 2 PR143 10_0603_1% 1 VID0 CPU_EN 1 PR145 7.32K_0402_1% 2 PC102 0.068U_0402_16V7K PL11 FBMA-L11-201209-121LMA50T_0805 PC101 10U_1206_25V6M PR135 1 IMVP_IMON 1 PR144 0_0402_5% 1 2 +CPU_B+ 2 8 @ PR134 309K_0402_1% +5VS 1 2 +VTTP PC100 10U_1206_25V6M VGATE 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 17,31 2 PR132 10K_0402_1% PR133 0_0402_5% 2 1CPU_PWRGD Anburndale ULV(6-0):0010100 8 1K_0402_1% 1 2 PR215 2 1 CPU_VID6 8 1K_0402_1% 1 PR142 @ PR208 CPU_VID6 2 1 +3VS PR141 1K_0402_1% 1 PR140 PR214 CPU_VID5 2 1 1K_0402_1% 1 1 1K_0402_1% 1 @ PR207 CPU_VID5 2 CPU_VID2 31 CPU_VID3 8 CPU_VID4 8 CPU_VID5 8 CPU_VID6 8 @ PR213 CPU_VID4 2 PR139 1K_0402_1% 1 1 1K_0402_1% 1 PR206 CPU_VID4 2 CPU_VID1 PR212 CPU_VID3 2 PR138 1K_0402_1% 1 PR137 1K_0402_1% 1 @ PR205 CPU_VID3 2 1 @ PR210 CPU_VID2 2 1 1K_0402_1% 1 VR_ON 1K_0402_1% 1 PR204 CPU_VID2 2 CPU_VID0 1K_0402_1% 1 PR209 CPU_VID1 2 1 PR211 2 PR136 CPU_VID0 1K_0402_1% 1 1 1K_0402_1% 1 @ PR203 CPU_VID1 2 1 1 @ PR202 CPU_VID0 2 PC115 1000P_0402_50V7K Shortest the net trace 4 4 2010/04/12 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2010/10/02 Title +CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size B C D E F Rev 1.0 NDU00_LA-6031P M/B Date: A Document Number G Monday, April 12, 2010 Sheet 42 H of 45 A B C D E F G H 8 8 8 GFX_VID2 8,39 GFX_VID3 8 GFXVID4 8 GFX_VID5 8 GFX_VID6 8 GFXVR_EN GFX_VID1 1 GFX_VID0 1 PR162 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% +5VS B+ 3 2 1 33 2 1 2 1 +GFX_COREP 1 PC126 330U_D2E_2.5VM_R9M 4 +1.1V PR178 4.7_1206_5% + 12 2 17 PC117 10U_1206_25V6M 1 2 PC130 1000P_0402_50V7K PQ34 1 PQ33 TPCA8030-H_SOP-ADV8-5 5 2 PC123 2.2U_0603_10V6K 2 PC127 680P_0603_50V7K PH4 220K_0402_5%_ERTJ0EV224J~D 2 Ipeak =12A Place RTH1 close to inductor on the same layer Imax = 8.4A F =365kHz 1 1 1 PC129 560P_0402_50V7K PC128 1000P_0402_50V7K Total Capacitor =44 uF PR189 165K_0402_1% 2 GFX_RAMP-1 ESR = 4.37m Ohm 1 3 1 PR190 34.8K_0603_1% 1 Connect to input caps 2 PL14 0.36UH_PCMC104T-R36MN1R105_30A_20% 1 2 TPCA8028-H_SOP-ADVANCE8-5 GFX_DRVL 18 1 2 2 3 2 1 +5VS 5 26 1 CSCOMP CSFB 20 19 4 16 15 LLINE CSREF 14 13 GFX_SW PR188 71.5K_0402_1% 2 1 PR187 422K_0402_1% RT 12 GFX_RAMP GFX_DRVH 21 PR176 PC120 2.2_0603_1% 0.22U_0603_25V7K 2GFX_BOOST-1 1 2 2 2 8 8 VCC_AXG_SENSE VSS_AXG_SENSE +GFX_B+ AGND 22 1 11 IREF PR183 165K_0402_1% 1 2 GFX_RPM PR182 80.6K_0402_1% GFX_IREF 1 2 GFX_RT 1 GFX_CSCOMP 1 2 1 1 3 AGND 23 GFX_BOOST 1 GFX_CSCOMP PR186 0_0402_5% PR191 1K_0402_1% 2 1 GFX_CSFB 2 RAMP ILIM 2 8 GFX_CSCOMP PR185 0_0402_5% DRVL PGND PR180 20K_0402_1% PR181 6.65K_0402_1% Avoid high dV/dt PU12 GPU 2 PC125 470P_0402_50V8J PVCC COMP 7 2 GFX_ILIM PR179 1K_0402_1% FB RPM 1 GFX_VCC 9 2 2GFX_COMP-1 1 5 GFX_COMP 6 10 1 PC124 47P_0402_50V8J ADP3211AMNR2G_QFN32_5X5 24 PC116 10U_1206_25V6M 1 GFX_VCC VID6 VID5 27 VID4 28 VID3 VID2 29 SW FBRTN PR184 274K_0402_1% 1 2 GFX_FB 2 2 1 2 PR171 PR169 PR170 1 1 25 PR168 1 PR167 1 1 PR166 VID1 30 DRVH CLKEN# 4 PC118 1U_0805_25V6K 2 1 31 32 EN BST IMON 3 PC122 220P_0402_50V7K 1 PWRGD 1 2 PC121 1000P_0402_50V7K PL13 FBMA-L11-201209-121LMA50T_0805 PR172 10_0603_1% VCC 1 2 2 +GFX_B+ GFX_EN 1 1 2 1 PR175 7.87K_0402_1% 2 PC119 0.056U_0402_16V7K 2 2 GFXVR_IMON 1 8 PR173 @ 309K_0402_1% PR174 0_0402_5% 1 1 PR164 2 +VTTP VID0 GFXVR_PWRGD PR165 @ 10K_0402_1% PR163 @ 0_0402_5% 2 1GFX_PWRGD 2 1 +3VS PC131 1000P_0402_50V7K Shortest the net trace 4 4 2010/04/12 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2010/10/02 Title +GFX THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size B C D E F Rev 1.0 NDU00_LA-6031P M/B Date: A Document Number G Monday, April 12, 2010 Sheet 43 H of 45 NO DATE PAGE MODIFICATION LIST PURPOSE -----------------------------------------------------------------------------------------------------------------------------2009/11/9(EVT) P38 +5VALWP/+3VALWP PC54,PC55,PC65,PC66 change SE076104KM8 to SE076104K80 2009/11/9(EVT) P39 +VTTP 2009/11/9(EVT) P41 +0.75VSP Change PQ30 2009/11/9(EVT) P42 CPU_CORE Change PU11 change to ADP3211 Design change 2009/11/9(EVT) P42 CPU_CORE Change PH3 &PH4 change to A51 material 2009/11/9(EVT) P37 CHARGE Change PR49 change to 33m Design change 2009/11/9(EVT) P38 +5VALWP/+3VALWP PR90 & PR91 change to 121K Design change 2009/12/1(DVT) P39 +CPU-CORE Resever PD15 change to A51 material Design change to SB000009610 Design change Add PR202~PR215 pull-up & pull-down Design change 2009/12/17(DVT) P36 Battery Change PR31,PR32,PR34,PR35 Design change 2009/12/17(DVT) P37 CHARGE Change PC23,PC24,PC25,PC81,PC82 1206 to 0805 Design change 2009/12/22(DVT) P42 CPU_CORE Change PR147 0 ohm change to 2.2 ohm EMI commond 2009/12/22(DVT) P43 GFX Change PR176 0 ohm change to 2.2 ohm EMI commond 2009/12/22(DVT) P39 +VTTP ADD material PR125 & PR104 & PR102 and add net VTTPWORK_CPU Design change 2010/01/25(PVT) P36 Battery Add PD7,PD8 EMI require 2010/01/27(PVT) P37 CHARGE Add 10u x3 PC46,PC47,PC88 EMC require 2010/02/04(PVT) P41 +0.75VSP Resever PR129 Add PR130 and PC97 Design change 2009/02/04(PVT) P38 +5VALWP/+3VALWP Change PQ38 Design change 2010/02/04(PVT) P42 CPU_CORE Change PR160 to 95.3K and PR145 to 7.32K Design change P36 Battery 2010/02/08(PVT-2) Change PR21&PR22 and +CHGRTC Design change Compal Secret Data Security Classification Issued Date 2010/04/12 Deciphered Date 2010/10/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Compal Electronics, Inc. Power PIR Size Document Number Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 Sheet 44 of 45 5 Item Fixed Issue (Reason for change) 4 PAGE Modify List 3 Date 2 1 Intel S3 power saving 05 Install Q1, R1484, C878, R8, R40 and Remove R2, R42 12/25 DVT 2 HDMI Detection function 14 modify HDMI_HPD circuit (Remove U7) 12/25 DVT 3 Sleep charge control method change SLP_CHG_M3_R & SLP_CHG_M4_R change from PCH to Pin103 & 74 of EC 12/25 DVT 4 Implement Low power HDA 22 Reserve R1468 & R1469 for 1.5VALW (Low Power HDA) 12/25 DVT 5 Debug usage 26 Reserve LPC bus at WLAN solt 12/14 DVT 6 LAN circuit change for Vendore request 27 RL21 contact to GND 12/18 DVT 7 Avoid power leakage & reduce double pull up 27 Remove RL3 12/25 DVT 8 Transformer change 27 Move Transformer from Sub-board to M/B 12/21 DVT 9 Prevent Card Reader IC damagewhen insert dummy card 28 Add F2 12/24 DVT 10 Audio PD# issue (Could not work) 29 Add RA29 pull up 12/19 DVT 11 Avoid Audio noise 29 reserve and unistall CA70, CA68, CA69, UA2, RA30, CA67 12/22 DVT 12 Enhance Right side USB ability 30 modify JP2 pin assignment and reserve JP3 pad for test 12/19 DVT 13 Sleep charge control method change 31 add pin 21 of EC for control ALW power MOS 12/21 DVT 14 Sleep charge control method change 34 add twoV_ALW power transfer circuits (3V_ALW to 3VALW & 5V_ALW to 5VALW) 12/21 DVT 15 system idle hang up issue 8 CPU_PSI# Pull down 1k ohm & H_DPRSLPVR pull up 1k ohm to Vtt 12/19 DVT 16 Sleep charge control method change 24 change U14 power from 5VALW to 5V_ALW 12/21 DVT 18 EC_SWI# pull up twice. R190 27 RL3 reserved. 01/20 PVT 19 Audio LDO reserved for AVDD. 29 UA2 pin 5 for +AVDD 01/20 PVT 20 For S3 power saving. 05 Reserve R2 and change R1484 to 0 ohm. 01/20 PVT 21 For 3G LED flash when resume from S3. 33 Reserve Q21 and Q22 circuit. Add R338 and R336. 01/20 PVT 22 Don't need discharge circuit. 34 Modify Q26 and Q27 circuit. 01/20 PVT 23 Reserve for PCH and EC both. 19,24,31 Add R1487,R1488,R1489 and R1490. 01/20 PVT 24 Change JHDD1 pin 4 to GND. 24 01/20 PVT 25 Add BT power control circuit. 26 Add D85 and Q27. 01/20 PVT 26 change cardreader connector. 28 ME request 01/26 PVT 27 change LED always power 33 3G LED flash issue. 01/26 PVT 28 change TP connector. 33 ME request 01/26 PVT 29 JGSIM2 connector. 26 01/26 PVT 30 add R1491 in USB_EN# 30 01/26 PVT 31 Lid switch change to +3V_ALW 32 add USB port 9 and PCIe port 4 for 8 pin SIM card. 16,19,26 33 add R1494 and D84 near D5. and add L,C near U8 15,18 EMI request 02/03 PVT 34 change MIC1_R and MIC1_L pull high. 29 MIC issue. 02/03 PVT 35 JLVDS1 pin24 change to NC. 12 Common design. 03/04 PVT2 36 CRT trace modify. 18 wrong trace. 03/04 PVT2 37 D5 layout close to PCH (U8) layout change. 03/04 PVT2 38 Change O2 to JMicron card reader. 03/22 PVT2 19 & 31 1 Phase D D 17 C C B B 31,33 Toshiba request. 28 01/26 PVT 01/27 PVT 39 USB OC# change. 19 Common design. 03/22 PVT2 40 Add R1505. 17 EMI request 03/22 PVT2 A A Issued Date 2010/04/12 Deciphered Date 2006/07/26 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Compal Electronics, Inc. Compal Secret Data Security Classification Title PIR Size Document Number Rev 1.0 NDU00_LA-6031P M/B Date: Monday, April 12, 2010 1 Sheet 45 of 45 www.s-manuals.com
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.4 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Create Date : 2010:04:12 15:42:22Z Creator Tool : PScript5.dll Version 5.2.2 Modify Date : 2014:06:24 21:10:06+03:00 Metadata Date : 2014:06:24 21:10:06+03:00 Format : application/pdf Creator : Title : Compal LA-6031P - Schematics. www.s-manuals.com. Subject : Compal LA-6031P - Schematics. www.s-manuals.com. Producer : GPL Ghostscript 8.15 Document ID : uuid:09c9be2f-73d9-4888-ace4-1522b5518e7b Instance ID : uuid:af4a0cea-bc15-4236-bcc9-85b6c1d6d49b Page Count : 46 Keywords : Compal, LA-6031P, -, Schematics., www.s-manuals.com. Warning : [Minor] Ignored duplicate Info dictionaryEXIF Metadata provided by EXIF.tools