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User Manual: Motherboard Compal LA-8481P Q3ZMC UMA - Schematics. Free.
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A B C D E Compal Confidential Model Name : Q3ZMC File Name : LA-8481P 1 1 Compal Confidential 2 2 Q3ZMC UMA M/B Schematics Document Intel Ivy/Sandy Bridge SFF BGA 1023p Processor /Panther Point 989p PCH / DDR3L Memory Down *8 2012-04-11 3 3 REV:1.0(MP SMT) 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 2013/4/6 Deciphered Date Title Cover Page THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A B C D Thursday, April 12, 2012 Sheet E 1 of 51 Rev 1.0 A B C D E PCB ZZZ1 LA-8481P DAZ0NS00100 DDR3L-ON BOARD 1 Intel Ivy Bridge ULV eDP Conn. Fan Control page 34 page 22 Two Channel 1.35V DDR3L 1333Mhz Processor BGA1023 120MHz eDP 1 Memory BUS(DDR3L) page 11,12 page 4~10 FDI x8 Thunderbolt DMI x4 HDMI Conn. 100MHz 100MHz page 23 2.7GT/s 1GB/s x4 page 24~27 Intel Panther Point-M 2 TMDS DP PCH 100MHz PCI-Express x 8 (PCIE2.0 5GT/s) port 5~8 port 2 Thunderbolt WLAN page 24~27 Camera Bluetooth mSATA (Reserve) USB port 9 USB port 10 USB port 8 USB port 12 page 31 page 31 USBx14 3.3V 48MHz HD Audio 3.3V 24MHz page 22 page 28 page 28 2 SPI D/B HDA Codec ALC271X-VB6/ALC281X page 13~21 page 32 LPC SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) Card reader page 28 Debug Port USB3.0 port 1,2 USB2.0 port 0,1 989pin BGA 100MHz port 1 USB 3.0 conn x2 page 22 TPM port 0 SPI ROM x2 page 30 Int. Speaker x 2 page 13 Int. DMIC x 1 page 32 mSATA Phone Jack x 1 page 32 page 32 LPC BUS page 29 3 3 33MHz ENE KB930/KB9012 page 33 RTC CKT. LS-8481P Audio/B page 13 page 32 Touch Pad Int.KBD page 33 Power On/Off CKT. page 33 DC/DC Interface CKT. page 33 LS-8482P Card Reader/B page 22 LS-8483P LED/B page 35 page 32 EC ROM x1 @ for page KB930 33 4 4 Power Circuit DC/DC LS-8484P Battery/B page 36~45 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 2013/4/6 Deciphered Date Title Block Diagrams THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A B C D Thursday, April 12, 2012 Sheet E 2 of 51 Rev 1.0 A B C D E Voltage Rails Power Plane 1 S1 S3 S5 VIN Adapter power supply (19V) Description N/A N/A N/A BATT+ Battery power supply (12.6V) N/A N/A N/A B+ AC or battery power rail for power circuit. N/A N/A N/A +VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* +CPU_CORE Core voltage for CPU ON OFF OFF +VGFX_CORE Core voltage for UMA graphic ON OFF OFF +1.05VS_VTT +1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU ON OFF OFF +1.05VS_PCH +1.05VS_VTT to +1.05VS_PCH power for PCH ON OFF OFF +1.35V +1.35VP to +1.35V power rail for DDR3L ON ON OFF +1.35VS +1.35V to +1.35VS switched power rail ON OFF OFF +0.675VS +0.675VSP to +0.675VS switched power rail for DDR3L terminator ON OFF OFF +1.5VS +1.5VSP to +1.5VS power rail for PCH ON OFF OFF +1.8VS +3VALW to 1.8VS switched power rail for PCH ON OFF OFF +3VALW +3VALWP to +3VALW always on power rail ON ON ON* +3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Resistor) ON ON ON* +3VS +3VALW to +3VS power rail ON OFF OFF +5VALW +5VALWP to +5VALW always on power rail ON ON ON* +5VS +5VALW to +5VS switched power rail ON OFF OFF +RTCVCC RTC power ON ON ON +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Full ON Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. EC SM Bus1 address Device Address Smart Battery 0001 011X b EC SM Bus2 address Device Address PCH SM Bus address Device Address ChannelA A0 1010 000X ChannelB A4 1010 010X SLP_S1# SLP_S3# SLP_S4# SLP_S5# 1 Board ID / SKU ID Table for AD channel Vcc Ra/Rc/Re Board ID 2 SIGNAL STATE 0 1 2 3 4 5 6 7 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BOARD ID Table Board ID 0 1 2 3 4 5 6 7 2 BTO Option Table PCB Revision 0.1,0.2 0.3 DVT:unknown MCU+MKS Motor,With TB IC 0.4 PVT1:PADAUK MCU+MKS Motor,Without TB IC 0.4 PVT2:PADAUK MCU+MKS Motor,With TB IC 1.0 3 BTO Item Unpop Connector UMA CPU PCH DDR3 DDR3L On Board DRAM 128bit RAM eDP LVDS BOM Structure @ CONN@ UMA@ IVB@ HM77@ DDR3@ DDR3L@ X76@ 128@ eDP@ LVDS@ 3 USB Port Table BOM Config 4319HNBOL01:UMA@/DDR3L@/eDP@/USB3.0@/9012@/TB@/IVB@/HM77@/DS3@/TXM@/TPM@/128@/ 4319HNBOL02:UMA@/DDR3L@/eDP@/USB3.0@/9012@/TB@/IVB@/HM77@/DS3@/TXM@/TPM@ USB 2.0 USB 1.1 Port UHCI0 UHCI1 EHCI1 UHCI2 UHCI3 UHCI4 EHCI2 UHCI5 4 UHCI6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 USB port (Rear side 3.0) USB port (Rear side 3.0) Debug Port Camera mSATA(Reserve) BlueTooth USB2.0 Conn USB3.0 Conn Thunderbolt USB2.0@ USB3.0@ TB@ KB930 KB9012 930@ 9012@ Normal S3 Deep S3 S3@ DS3@ TPM+TCM TPM TCM TXM@ TPM@ TCM@ 2012/4/6 4 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 2 External USB Port 2013/4/6 Deciphered Date Title Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A B C D Thursday, April 12, 2012 Sheet E 3 of 51 Rev 1.0 A B C D E +1.05VS_VTT 1 PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms R532 24.9_0402_1% <15> <15> <15> <15> DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 N3 P7 P3 P11 <15> <15> <15> <15> DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 <15> <15> <15> <15> DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 <15> <15> <15> <15> <15> <15> <15> <15> FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 <15> <15> <15> <15> <15> <15> <15> <15> FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 U7 W11 W1 AA6 W6 V4 Y2 AC9 U6 W10 W3 AA7 W7 T4 AA3 AC8 AA11 AC12 U11 1 <15> FDI_INT 2 R118 24.9_0402_1% Add eDP circuit W=4mil,S=15mil,L=500mil EDP_HPD# AF3 AD2 AG11 AG4 AF4 <22> EDP_AUXN <22> EDP_AUXP AC3 AC4 AE11 AE7 1 <22> EDP_TXN0 <22> EDP_TXN1 AC1 AA4 AE10 AE6 <22> EDP_TXP0 <22> EDP_TXP1 2 R809 1K_0402_5% EDP_COMP EDP_HPD# DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC eDP_COMPIO eDP_ICOMPO eDP_HPD# eDP_AUX# eDP_AUX eDP +1.05VS_VTT AA10 AG8 <15> FDI_LSYNC0 <15> FDI_LSYNC1 W=12mil,S=15mil,L=500mil <22> EDP_HPD# K3 M7 P4 T3 <15> FDI_FSYNC0 <15> FDI_FSYNC1 3 eDP@ K1 M8 N4 R2 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] PCI EXPRESS -- GRAPHICS M2 P6 P1 P10 Intel(R) FDI +1.05VS_VTT eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms should not be left floating ,even if disable eDP function... DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI 2 <15> <15> <15> <15> PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] G3 G1 G4 H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7 PEG_ICOMPO signals should be routed with - max length = 500 milstypical impedance = 14.5 mohms 2 UCPU1A 1 PEG_COMP 1 G3,W=4mil,S=15mil,L=500mil G1,W=12mil,S=15mil,L=500mil G4,W=4mil,S=15mil,L=500mil UMA only=>PEG NC K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6 2 G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4 F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4 3 IVY-BRIDGE_BGA1023 IVB@ ULV type P/N: 1.SA00005B000:S IC AV8063801057400 QBP7 K0 1.7G BGA 2.SA00005AZ30:S IC AV8063801057401 QBTP K0 1.5G BGA 4 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 Issued Date Deciphered Date 2013/4/6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title PROCESSOR(1/7) DMI,FDI,PEG Size Document Number Custom Q3ZMC M/B LA-8481P Schematic Date: Sheet Thursday, April 12, 2012 E 4 of 51 Rev 1.0 A B C D E 1 1 UCPU1B 2 H_CPUPWRGD 1 10K_0402_5% H_CPUPWRGD Processor Pullups follow CRB1.0 R220 2 +1.05VS_VTT @ PAD <18,32> H_PECI 1 62_0402_5% H_PROCHOT# <32> H_PROCHOT# R216 56_0402_5% 1 2 H_CATERR# C49 H_PECI A48 H_PROCHOT#_R D45 <18> H_THRMTRIP# Follow DG 1.2 & CRB1.0 Buffered reset to CPU +3VS 5 P 2 BUFO_CPU_RST# R227 43_0402_1% 1 2 SN74LVC1G07DCKR_SC70-5 BE45 D44 2 Use open drain MOS: +1.35VS PH pop 200ohm series resister pop 130ohm Y 4 1 R97 PM_SYS_PWRGD_BUF 1 MC74VHC1G09DFT2G_SC70-5 2 130_0402_5% R116 2 @ 1 1K_0402_5% CLK_CPU_DPLL R117 2 @ 1 1K_0402_5% SM_DRAMRST# BF44 BE43 BG43 SM_RCOMP0 R149 SM_RCOMP1 R486 SM_RCOMP2 R484 SM_DRAMRST# <6> 2 2 2 1 140_0402_1% 1 25.5_0402_1% 1 200_0402_1% DDR3 Compensation Signals Trace:10mil ,Spacing:13mil, Max.Length:500mil PM_SYNC UNCOREPWRGOOD SM_DRAMPWROK RESET# TDI TDO N53 N55 L56 L55 J58 XDP_TCK XDP_TMS XDP_TRST# @ PAD @ PAD @ PAD T2 T3 T4 M60 L59 XDP_TDI XDP_TDO @ PAD @ PAD T5 T6 K58 XDP_DBRESET# 3 +3VS DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] XDP_DBRESET# R569 2 XDP_DBRESET# <15> G58 E55 E59 G55 G59 H60 J59 J61 1 1 1K_0402_5% CRB1.0 PH 1K +3VS Check list 1.0 PH 5K +3VS Check list 1.2 PH 10K +3VS Debug port DG1.1-1.2 50~5K ohm 2 C102 100P_0201_25V8J For EMI PM_DRAM_PWRGD R829 39_0402_5% @ 1 D 3 S SUSP 2 G 4 PM_DRAM_PWRGD_R 1 2 3 A <35,40> SUSP C787 100P_0201_25V8J Q74 SSM3K7002FU_SC70-3 @ Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2 2012/4/6 2013/4/6 Deciphered Date Title PROCESSOR(2/7) PM,XDP,CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A CLK_CPU_DPLL# 2 5 P B G 1 <15> PM_DRAM_PWRGD CLK_CPU_DPLL <14> CLK_CPU_DPLL# <14> R88 200_0402_5% U5 2 <15> SYS_PWROK +1.05VS_VTT IVY-BRIDGE_BGA1023 IVB@ 1 1 CLK_CPU_DPLL CLK_CPU_DPLL# AT30 THERMTRIP# SM_DRAMPWROK:DRAM power ok BUF_CPU_RST# +3VALW 2 4 除除CPU_CORE以以以以OK PM_DRAM_PWRGD_R +1.35VS C101 0.1U_0402_16V4Z UNCOREPWRGOOD: BUF_CPU_RST# @ R225 0_0402_5% 都ok後後CPU做reset Follow DG 1.2 & CRB1.0 @ R80 0_0402_5% 2 H_CPUPWRGD_R B46 1 <18> H_CPUPWRGD 1 G 3 RESET#: C48 <15> H_PM_SYNC R226 75_0402_5% 4 Y A SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] TCK TMS TRST# U15 NC 2 <17,22,24,30,32> PLT_RST# PROCHOT# SM_DRAMRST# +1.05VS_VTT 2 1 PECI PRDY# PREQ# C396 0.1U_0201_10V6K AG3 AG1 CLK_CPU_DMI <14> CLK_CPU_DMI# <14> Checklist1.0 P.64 Processor Graphis Disable Guide DIS only SKU or UMA eDP disable DPLL_REF_SSCLK PD 1K_5% to GND DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT Use open drain MOS: +1.05VS_VTT PH pop 75ohm series resister pop 43ohm 1 1 DPLL_REF_CLK DPLL_REF_CLK# J3 H2 CATERR# PWR MANAGEMENT 3 C45 PROC_DETECT# JTAG & BPM 1 0.1U_0402_10V7K 2 T1 PROC_SELECT# CLOCKS 偵偵CPU有有有有 XBOX 三三三三 C57 THERMAL 2 @ C784 F49 <17> H_SNB_IVB# Follow DG 1.2 & CRB1.0 R223 2 BCLK BCLK# DDR3 MISC 外外外 MISC 非 都 後後 做 PROC_SELECT# Future platforms,PH VCPLL and connect to PCH DF_TVS PCH->CPU UNCOREPWRGOOD: CORE OK SM_DRAMPWROK:DRAM power ok RESET#: ok CPU reset B C D Thursday, April 12, 2012 Sheet E 5 of 51 Rev 1.0 A B C D UCPU1C UCPU1D BD37 BF36 BA28 <11> DDR_A_BS0 <11> DDR_A_BS1 <11> DDR_A_BS2 1 DDR_A_CLK0 <11> DDR_A_CLK0# <11> DDR_A_CKE0 <11> AT40 AU40 BB26 DDR_A_CLK1 DDR_A_CLK1# R263 75_0402_1% SA_CS#[0] SA_CS#[1] SA_ODT[0] SA_ODT[1] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] SA_CAS# SA_RAS# SA_WE# BB40 BC41 DDR_A_CS0# <11> AY40 BA41 DDR_A_ODT0 <11> AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_DQS#[0..7] <11> AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS[0..7] <11> BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_MA[0..15] <11> BG39 BD42 AT22 <12> DDR_B_BS0 <12> DDR_B_BS1 <12> DDR_B_BS2 AV43 BF40 BD45 <12> DDR_B_CAS# <12> DDR_B_RAS# <12> DDR_B_WE# IVY-BRIDGE_BGA1023 IVB@ DIMM_DRAMRST#_R 2 1 4 <11,12,14> DRAMRST_CNTRL_PCH 2 0_0402_5% R413 1 DS3@ 2 0_0402_5% 2 <32> DRAMRST_CNTRL_EC R418 1 1 2 @ R416 0_0402_5% 1 C78 .047U_0402_16V7K DDR_B_CLK0 <12> DDR_B_CLK0# <12> DDR_B_CKE0 <12> 1 SB_CK[1] SB_CK#[1] SB_CKE[1] BA36 BB36 BF27 DDR_B_CLK1 DDR_B_CLK1# SB_CS#[0] SB_CS#[1] SB_ODT[0] SB_ODT[1] SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] SB_BS[0] SB_BS[1] SB_BS[2] SB_CAS# SB_RAS# SB_WE# BE41 BE47 DDR_B_CS0# <12> AT43 BG47 DDR_B_ODT0 <12> AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_DQS#[0..7] <12> AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS[0..7] <12> BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 2 DDR_B_MA[0..15] <12> 3 Address 0~13:For 128*16 Address 0~14:For 256*16 Address 0~15:For 512*16 1 R63 1K_0402_5% 2 DIMM_DRAMRST# DIMM_DRAMRST# <11,12> S0 DRAMRST_CNTRL_PCH hgih ,MOS ON SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH Dimm not reset S3 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# Low,DDR3 DRAMRST# HIGH Dimm not reset S4,S5 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# Low,DDR3 DRAMRST# Low Dimm reset SM_DRAMRST# 1 C785 100P_0201_25V8J 2 1 2 1 C786 100P_0402_50V8J 2 C788 100P_0402_50V8J 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 2013/4/6 Deciphered Date Title B PROCESSOR(3/7) DDRIII THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A R264 75_0402_1% R66 1K_0402_5% Q6 BSS138-G_SOT23-3 G R79 4.99K_0402_1% BA34 AY34 AR22 +1.35V 2 1 2 SM_DRAMRST# D 3 S <5> SM_DRAMRST# SB_CK[0] SB_CK#[0] SB_CKE[0] 1 R78 0_0402_5% 1 2 @ 通通DIMM做reset SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] IVY-BRIDGE_BGA1023 IVB@ Follow CRB1.0 CPU AL4 AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9 BD13 BF12 BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59 AM60 AL59 AF61 AH60 1 AU36 AV36 AY26 2 SA_CK[1] SA_CK#[1] SA_CKE[1] SA_BS[0] SA_BS[1] SA_BS[2] BE39 BD39 AT41 <11> DDR_A_CAS# <11> DDR_A_RAS# <11> DDR_A_WE# SA_CK[0] SA_CK#[0] SA_CKE[0] DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 2 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] DDR SYSTEM MEMORY A 2 3 <12> DDR_B_D[0..63] AG6 AJ6 AP11 AL6 AJ10 AJ8 AL8 AL7 AR11 AP6 AU6 AV9 AR6 AP8 AT13 AU13 BC7 BB7 BA13 BB11 BA7 BA9 BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR SYSTEM MEMORY B <11> DDR_A_D[0..63] 1 E C D Thursday, April 12, 2012 Sheet E 6 of 51 Rev 1.0 A B C D E Default "1",EDS R1.0 P.88 CFG Straps for Processor UCPU1E CFG4 CFG5 CFG6 CFG7 2 1 1 R810 @ 49.9_0402_1% VCC_VAL_SENSE 2 VSS_VAL_SENSE 1 R812 @ 49.9_0402_1% +VGFX_CORE VCC_VAL_SENSE VSS_VAL_SENSE H43 K43 VAXG_VAL_SENSE VSSAXG_VAL_SENSE H45 K45 PAD @ F48 VCC_VAL_SENSE VSS_VAL_SENSE VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_DIE_SENSE BCLK_ITP BCLK_ITP# RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 N59 N58 1: Normal Operation; Lane # definition matches socket pin map definition CFG2 * N42 L42 L45 L47 0:Lane Reversed 1 CFG2 M13 M14 U14 W14 P13 R234 1K_0402_1% AT49 K24 eDP enable AH2 AG13 AM14 AM15 CFG4 * 1:Disable 0:Enable N50 2 T56 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] 1 CFG2 +CPU_CORE B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53 2 CFG0 PAD @ RESERVED T72 PEG Static Lane Reversal - CFG2 is for the 16x IVY-BRIDGE_BGA1023 IVB@ CFG4 1 A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1 DC_TEST_C4_D3 eDP@ R204 1K_0402_1% DC_TEST_A59_C59 2 2 DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58 DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1 DC_TEST_A61_C61 PCIE Port Bifurcation Straps DC_TEST_BE59_BE61 DC_TEST_BG59_BG61 CFG[6:5] (Default) 1x16 PCI Express *11: 10: 2x8 PCI Express 01: Reserved DC_TEST_BE3_BG3 00: 1x8,2x4 PCI Express DC_TEST_BE1_BG1 These pins are for solder joint reliability and non-critical to function. For BGA only. CFG6 CFG5 1 2 1 R813 @ 49.9_0402_1% RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 1 VSSAXG_VAL_SENSE 2 BA19 AV19 AT21 BB21 BB19 AY21 BA22 AY22 AU19 AU21 BD21 BD22 BD25 BD26 BG22 BE22 BG26 BE26 BF23 BE24 R230 1K_0402_1% @ @ 2 1 VAXG_VAL_SENSE RSVD6 RSVD7 2 H48 K48 R811 @ 49.9_0402_1% R228 1K_0402_1% 3 3 PEG DEFER TRAINING CFG7 CRB1.0 P.12 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training 1 CFG7 R224 1K_0402_1% 2 @ 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 2013/4/6 Deciphered Date Title PROCESSOR(4/7) RSVD,CFG THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A B C D Thursday, April 12, 2012 Sheet E 7 of 51 Rev 1.0 A B C UCPU1F ULV SC/DC 33A D POWER E 8.5A +1.05VS_VTT VCCIO[1] VCCIO[3] VCCIO[4] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] VCCIO[9] VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] 1 330uF 1+1 10uF (0603) *5 1uF (0201) *16 +1.05VS_VTT AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15 330uF 1 10uF (0603) *5 1uF (0201) *10 +3VALW 2 VCCIO_SEL For 2012 CPU support R521 10K_0402_5% +1.05VS_VTT A19 * 1 : +1.05VS_VTT W16 W17 0: +1.0VS_VTT VCCIO_SEL 1 VCCIO50 VCCIO51 2 1 VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] R520 10K_0402_5% @ 2 VCCIO_SEL BC22 VCCIO_SEL_R R582 1 2 0_0402_5% @ +1.05VS_VTT +1.05VS_VTT VCCPQE[1] VCCPQE[2] AM25 AN22 C951 1U_0201_4V6M Check List R1.5 VIDALERT#:75ohm ±5% pull-up to VCCIO close to IMVP7 VIDSCLK: 55ohm ±5% pull-up to VCCIO close to IMVP7 VIDSOUT: 130ohm ±5% pull-up to VCCIO close to CPU 130ohm ±5% pull-up to VCCIO close to IMVP7 R574 130_0402_5% 3 VIDALERT# VIDSCLK VIDSOUT A44 B43 C44 R576 1 R577 1 R578 1 H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT VR_SVID_ALRT# <43> VR_SVID_CLK <43> VR_SVID_DAT <43> +CPU_CORE VCC_SENSE VSS_SENSE F43 VCCSENSE_R G43 VSSSENSE_R R579 1 R581 1 2 0_0402_5% 2 0_0402_5% @ @ R588 100_0402_1% 2 Place the PU,PD resistors close to CPU VCCSENSE <43> VSSSENSE <43> 1 R107 AN16 AN17 2 10_0402_5% VCCIO_SENSE VSSIO_SENSE VCCIO_SENSE 1 VCCIO_SENSE VSS_SENSE_VCCIO 1 +1.05VS_VTT R589 100_0402_1% <41> Check List R1.5 VCCSENSE:100ohm ±1% pull-up to VCC near processor. VSSSENSE:100ohm ±1% pull-down to GND near processor. 2 SENSE LINES 2 43_0402_1% 2 0_0402_5% 2 0_0402_5% @ @ 1 SVID 2 2 3 INTEL Recommend VCCIO PD 0.9 1 2 AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48 1 1 VCC[1] VCC[2] VCC[3] VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16] VCC[17] VCC[18] VCC[19] VCC[20] VCC[21] VCC[22] VCC[23] VCC[24] VCC[25] VCC[26] VCC[27] VCC[28] VCC[29] VCC[30] VCC[31] VCC[32] VCC[33] VCC[34] VCC[35] VCC[36] VCC[37] VCC[38] VCC[39] VCC[40] VCC[41] VCC[42] VCC[43] VCC[44] VCC[45] VCC[46] VCC[47] VCC[48] VCC[49] VCC[50] VCC[51] VCC[52] VCC[53] VCC[54] VCC[55] VCC[56] VCC[57] VCC[58] VCC[59] VCC[60] VCC[61] VCC[62] VCC[63] VCC[64] VCC[66] VCC[67] VCC[68] VCC[69] VCC[70] VCC[71] VCC[72] VCC[73] VCC[74] VCC[75] VCC[76] QUIET RAILS A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38 CORE SUPPLY INTEL Recommend VCC 3*330uF,12*22uF(0805),16*2.2uF(0402) PD0.9 PEG IO AND DDR IO +CPU_CORE R105 10_0402_5% 2 IVY-BRIDGE_BGA1023 IVB@ 4 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 4 Should change to connect from power cirucit & layout differential with VCCIO_SENSE. 2012/4/6 2013/4/6 Deciphered Date Title PROCESSOR(5/7) PWR,BYPASS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A B C D Thursday, April 12, 2012 Sheet E 8 of 51 Rev 1.0 B ULV SC/DC GT1: 18A GT2: 33A 1 2 2 1 VREF 2 1 1 2 2 1 2 1 2 1 2 1 2 2 1 C970 1 1 2 C987 2 C993 2 2 2 2 2 2 2 2 1 C992 1 C1009 1 C994 1 C1006 1 C1008 1 C1007 1 C1010 1 C986 1 C1002 2 1 2 C989 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 - 1.5V RAILS DDR3 GRAPHICS C990 VCCSA[1] VCCSA[2] VCCSA[3] VCCSA[4] VCCSA[5] VCCSA[6] VCCSA[7] VCCSA[8] VCCSA[9] VCCSA[10] VCCSA[11] VCCSA[12] VCCSA[13] VCCSA[14] VCCSA[15] VCCSA[16] 1 2 QUIET RAILS SENSE LINES AM28 AN26 C985 1U_0201_4V6M VDDQ_SENSE VSS_SENSE_VDDQ BC43 BA43 VCCSA_VID For 2012 future CPU VCCSA voltage select VCCSA_SENSE VCCSA_VID[0] VCCSA_VID[1] VCCSA U10 VCCSA_SENSE CPU EDS1.3 P.93 VCCSA_VID0 Must PD D48 D49 H_VCCSA_VID0 H_VCCSA_VID1 H_VCCSA_VID0 H_VCCSA_VID1 1 L17 L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21 W20 VCCDQ[1] VCCDQ[2] 3 SENSE LINES 6A VCCPLL[1] VCCPLL[2] VCCPLL[3] 1.8V RAIL BB3 BC1 BC4 VCCSA VID lines 1 2 1 2 1 10U_0603_6.3V6M 2 + C599 330U_B2_2VM_R15M SGA00004400 2 0.1U_0201_10V6K 1 +1.35VS 1 10U_0603_6.3V6M 2 1U_0201_4V6M 10U_0603_6.3V6M 1 C991 0.1U_0201_10V6K 10U_0603_6.3V6M 2 C988 10U_0603_6.3V6M 1 C984 1U_0201_4V6M 2 C983 0.1U_0201_10V6K 1 C982 10U_0603_6.3V6M C997 C981 1U_0201_4V6M 1U_0201_4V6M C996 C980 0.1U_0201_10V6K 1U_0201_4V6M C995 C979 10U_0603_6.3V6M 1U_0201_4V6M INTEL Recommend VCCSA 1*330uF,5*10uF(0603) ,5*1uF(0402) PD0.9 C978 Place BOT OUT Conn <42> VID0 VID1 Vout SNB IVB ULV 0 0 0.9V V V V 0 1 0.8V V V 1 0 0.725V X V V 1 1 0.675V X V V <42> <42> R129 0_0402_5% @ 0.85V V 2 IVY-BRIDGE_BGA1023 IVB@ 4 C977 1U_0201_4V6M 1U_0201_4V6M 2 Short for +1.35VS to +1.35V_CPU_VDDQ 0.1U_0201_10V6K C1179 INTEL Recommend VDDQ 1*330uF,8*10uF(0603) ,10*1uF(0402) PD0.9 AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33 1U_0201_4V6M C1180 1 @ R68 1K_0402_1% 0.1U_0201_10V6K C1181 R540 1K_0402_5% 2 5A VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8] VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26] 1 1U_0201_4V6M C999 1U_0201_4V6M C607 330U_B2_2VM_R15M SGA00004400 C998 C647 0.1U_0201_10V6K <11> <12> 0.1U_0201_10V6K +VCCSA SA_DIMM_VREFDQ SB_DIMM_VREFDQ 1U_0201_4V6M 2 C584 1U_0201_4V6M C583 1U_0201_4V6M 2 +VCCSA 2 VAXG_SENSE VSSAXG_SENSE 1.2A +1.8VS_VCCPLL 3 C606 220U_B2_2.5VM_R15M SGA00004I00 SA_DIMM_VREFDQ SB_DIMM_VREFDQ SA_DIMM_VREFDQ SB_DIMM_VREFDQ @ R69 1K_0402_1% 2 100_0402_5% 1 +V_SM_VREF BE7 BG7 0.1U_0201_10V6K 1 1 AY43 1U_0201_4V6M F45 G45 R396 1 R534 1K_0402_5% +1.35VS <43> VCC_AXG_SENSE <43> VSS_AXG_SENSE 1 SM_VREF 2 100_0402_5% +1.8VS + VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22] VAXG[23] VAXG[24] VAXG[25] VAXG[26] VAXG[27] VAXG[28] VAXG[29] VAXG[30] VAXG[31] VAXG[32] VAXG[33] VAXG[34] VAXG[35] VAXG[36] VAXG[37] VAXG[38] VAXG[39] VAXG[40] VAXG[41] VAXG[42] VAXG[43] VAXG[44] VAXG[45] VAXG[46] VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54] VAXG[55] VAXG[56] 0.1U_0201_10V6K +VGFX_CORE R381 1 R477 0_0805_5% 1 2 +V_SM_VREF should have 20 mil trace width 0.1U_0201_10V6K Check List R1.5 VCCAXG_SENSE:100ohm ±5% pull-up to VCC near processor. VSSAXG_SENSE:100ohm ±5% pull-down to GND near processor. 2 POWER +1.35VS 1U_0201_4V6M 2 INTEL Recommend VCCPLL 1*330uF,2*1uF(0402) PD 0.9 E 1U_0201_4V6M AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46 N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61 1 + UCPU1G D SA_DIMM_VREFDQ SB_DIMM_VREFDQ For Future CPU M3 support, Sandey bridge not support M3, Check list1.0 & CRB say can NC +VGFX_CORE SA RAIL INTEL Recommend VAXG 2*330uF,5*22uF(0805),6*10uF(0603),6*1uF(0402) PD 0.9 C 1 A 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 2013/4/6 Deciphered Date Title PROCESSOR(6/7) PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A B C D Thursday, April 12, 2012 Sheet E 9 of 51 Rev 1.0 A B C D E UCPU1H UCPU1I A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53 A9 AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56 AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46 AC6 AD17 AD20 AD4 AD61 AE13 AE8 AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59 AG10 AG14 AG18 AG47 AG52 AG61 AG7 AH4 AH58 AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48 AJ7 AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61 AM13 AM20 AM22 AM26 AM30 AM34 2 3 VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] 1 AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13 BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53 BG9 C29 C35 C40 D10 D14 D18 D22 D26 D29 D35 D4 D40 D43 D46 D50 D54 D58 D6 E25 E29 E3 E35 E40 F13 F15 F19 F29 F35 F40 F55 G51 G6 G61 H10 H14 H17 H21 H4 H53 H58 J1 J49 J55 K11 K21 K51 K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61 M11 M15 VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS NCTF 1 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48 A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61 2 @ @ @ @ @ @ @ @ @ @ @ @ @ @ PAD T58 PAD T59 PAD T60 PAD T61 PAD T62 PAD T63 PAD T64 PAD T65 PAD T66 PAD T67 PAD T68 PAD T69 PAD T70 PAD T71 3 CR CheckList Rev1.5 IVY-BRIDGE_BGA1023 IVB@ IVY-BRIDGE_BGA1023 IVB@ 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 2013/4/6 Deciphered Date Title PROCESSOR(7/7) VSS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A B C D Thursday, April 12, 2012 Sheet E 10 of 51 Rev 1.0 A B C D E Channel A DDR_A_MA[0..15] <6> DDR_A_MA[0..15] DDR_A_DQS#[0..7] <6> DDR_A_DQS#[0..7] DDR_A_DQS[0..7] <6> DDR_A_DQS[0..7] DDR_A_D[0..63] E7 D3 <12,6> DIMM_DRAMRST# DDR_A_DQS#1 DDR_A_DQS#0 G3 B7 DIMM_DRAMRST# T2 1 R992 2 240_0402_1% L8 J1 L1 J9 L9 1 R996 2 240_0402_1% CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B2 D9 G7 K2 K8 N1 N9 R1 R9 A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0 J7 K7 K9 DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE# K1 L2 J3 K3 L3 DDR_A_DQS2 DDR_A_DQS3 F3 C7 E7 D3 DDR_A_DQS#2 DDR_A_DQS#3 G3 B7 DIMM_DRAMRST# T2 1 R993 2 240_0402_1% B1 B9 D1 D8 E2 E8 F9 G1 G9 L8 J1 L1 J9 L9 1 R997 2 240_0402_1% 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ +0.675VS BA0 BA1 BA2 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 1 2 B2 D9 G7 K2 K8 N1 N9 R1 R9 A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 M2 N8 M3 DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0 J7 K7 K9 DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE# K1 L2 J3 K3 L3 DDR_A_DQS4 DDR_A_DQS5 F3 C7 E7 D3 DDR_A_DQS#4 DDR_A_DQS#5 G3 B7 DIMM_DRAMRST# T2 1 R994 2 240_0402_1% B1 B9 D1 D8 E2 E8 F9 G1 G9 L8 J1 L1 J9 L9 1 R998 2 240_0402_1% 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ C1519 10U_0603_6.3V6M 2 1 +1.35V A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 RESET ZQ/ZQ0 2 G R1104 1K_0402_1% 2 2 <12,14,6> DRAMRST_CNTRL_PCH Layout Note: Place near each memory part 1 R1108 1K_0402_1% 2 1 2 1 1 + 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 C1464 330U_D2_2V_Y C1474 10U_0603_6.3V6M C1472 10U_0603_6.3V6M near U58 C1473 10U_0603_6.3V6M C1465 10U_0603_6.3V6M near U57 C1475 10U_0603_6.3V6M C1463 10U_0603_6.3V6M C1479 10U_0603_6.3V6M C1469 10U_0603_6.3V6M near U56 @ 2 R1107 1K_0402_1% 2.2U_0603_6.3V6K C1482 0.1U_0402_16V4Z C1483 +1.35V 4 1 +VREFCA_A 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 C1468 1U_0402_6.3V6K C1478 1U_0402_6.3V6K C1471 1U_0402_6.3V6K C1470 0.1U_0201_10V6K C1467 0.1U_0201_10V6K C1477 1U_0402_6.3V6K C1476 1U_0402_6.3V6K C1466 0.1U_0201_10V6K 1 +1.35V 1 DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0 J7 K7 K9 DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE# K1 L2 J3 K3 L3 G3 B7 T2 DIMM_DRAMRST# L8 J1 L1 J9 L9 1 R999 2 240_0402_1% DDR3 CLK Termination 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_RAS# 36_0201_1% DDR_A_CAS# 36_0201_1% DDR_A_ODT0 36_0201_1% DDR_A_CKE0 36_0201_1% DDR_A_WE# 36_0201_1% DDR_A_MA10 36_0201_1% DDR_A_CS0# 36_0201_1% DDR_A_BS2 36_0201_1% DDR_A_BS0 36_0201_1% DDR_A_MA12 36_0201_1% DDR_A_MA0 36_0201_1% DDR_A_BS1 36_0201_1% DDR_A_MA3 36_0201_1% DDR_A_MA1 36_0201_1% DDR_A_MA2 36_0201_1% DDR_A_MA4 36_0201_1% DDR_A_MA5 36_0201_1% DDR_A_MA11 36_0201_1% DDR_A_MA9 36_0201_1% DDR_A_MA14 36_0201_1% DDR_A_MA13 36_0201_1% DDR_A_MA6 36_0201_1% DDR_A_MA7 36_0201_1% DDR_A_MA8 36_0201_1% DDR_A_MA15 36_0201_1% near U59 2 0.1U_0402_16V4Z DDR_A_RAS# <6> 1 2 DDR_A_CAS# <6> R1102 30.1_0402_1% DDR_A_ODT0 <6> DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 DDR_A_D52 DDR_A_D54 DDR_A_D48 DDR_A_D50 DDR_A_D53 DDR_A_D55 DDR_A_D49 DDR_A_D51 D7 C3 C8 C2 A7 A2 B8 A3 DDR_A_D63 DDR_A_D61 DDR_A_D58 DDR_A_D60 DDR_A_D59 DDR_A_D56 DDR_A_D62 DDR_A_D57 1 +1.35V BA0 BA1 BA2 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE A1 A8 C1 C9 D2 E9 F1 H2 H9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU 2 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ DDR_A_CKE0 <6> 3 Delete U70 SPD EEROM circuit SA00004KS00 S IC EE 2K AT24C02C-XHM-T TSSOP 8P R1103 30.1_0402_1% END topology DDR_A_WE# <6> <6> DDR_A_CLK0 DDR_A_CS0# <6> C1457 1.8P_0201_50V8C DDR_A_BS2 <6> External DDR Thermal Sensor <6> DDR_A_CLK0# DDR_A_BS0 <6> +3VS C97 0.1U_0402_16V4Z 1 2 1.CAD Note: Cterm= 1.6pF should be kept near feeding point of first SDRAM DDR_A_BS1 <6> 2.CAD Note: Rtt= 30.1ohms, Ctt= 0.1uF should be kept within 600mils from last SDRAM U4 1 2 3 4 VDD D+ SCLK SDATA D- ALERT# THERM# GND 8 EC_SMB_CK2 <14,24,32> 7 6 EC_SMB_DA2 <14,24,32> 1 R546 2 +3VS 10K_0402_5% 5 W83L771AWG-2 TSSOP8P SA00003PU00 4 SA00003PU00 S IC W83L771AWG-2 TSSOP 8P SENSOR Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 Deciphered Date 2013/4/6 Title DDRIII DIMMA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A F3 C7 1 R995 2 240_0402_1% 2 1 R284 1 R290 1 R291 1 R294 1 R295 1 R296 1 R297 1 R298 1 R301 1 R303 1 R304 1 R306 1 R309 1 R311 1 R312 1 R313 1 R315 1 R317 1 R318 1 R319 1 R323 1 R325 1 R332 1 R333 1 R342 1 1 2 1 @ M2 N8 M3 DDR_A_DQS#6 DDR_A_DQS#7 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 VREFCA VREFDQ 2 1 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 1 Q78 1 D S 3 BSS138_NL_SOT23-3 +1.35V +VREFDQ_A C1480 2.2U_0603_6.3V6K 2 <9> SA_DIMM_VREFDQ R1106 1K_0402_1% C1481 0.1U_0402_16V4Z C1511 1U_0201_4V6M C1512 0.1U_0201_10V6K C1513 0.1U_0201_10V6K C1514 1U_0201_4V6M C1459 0.1U_0201_10V6K C1460 1U_0201_4V6M C1461 0.1U_0201_10V6K C1462 1U_0201_4V6M @ R1105 0_0402_5% 1 2 2 E7 D3 C1458 +0.675VS M3 support 1 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ +0.675VS +1.35V +VREFDQ_A DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_DQS6 DDR_A_DQS7 DDR3 CTL/ADD Termination 3 2 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU 1 A1 A8 C1 C9 D2 E9 F1 H2 H9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DML DMU NC/ODT1 NC/CS1 NC/CE1 NCZQ1 DDR_A_D42 DDR_A_D45 DDR_A_D47 DDR_A_D44 DDR_A_D46 DDR_A_D40 DDR_A_D43 DDR_A_D41 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 DQSL DQSU D7 C3 C8 C2 A7 A2 B8 A3 M8 H1 +1.35V BA0 BA1 BA2 ODT/ODT0 CS/CS0 RAS CAS WE DDR_A_D32 DDR_A_D34 DDR_A_D33 DDR_A_D35 DDR_A_D37 DDR_A_D39 DDR_A_D36 DDR_A_D38 1 M2 N8 M3 +VREFDQ_A N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 E3 F7 F2 F8 H3 H8 G2 H7 2 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 2 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 1 F3 C7 VDD VDD VDD VDD VDD VDD VDD VDD VDD DDR_A_D25 DDR_A_D29 DDR_A_D27 DDR_A_D28 DDR_A_D31 DDR_A_D30 DDR_A_D26 DDR_A_D24 1 U59 +VREFCA_A VREFCA VREFDQ 2 DDR_A_DQS1 DDR_A_DQS0 2 BA0 BA1 BA2 @ D7 C3 C8 C2 A7 A2 B8 A3 M8 H1 1 1 2 K1 L2 J3 K3 L3 2 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DDR_A_D16 DDR_A_D19 DDR_A_D20 DDR_A_D18 DDR_A_D22 DDR_A_D23 DDR_A_D17 DDR_A_D21 C1263 2.2U_0603_6.3V6K DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE# 1 +1.35V A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 E3 F7 F2 F8 H3 H8 G2 H7 C1262 0.1U_0402_16V4Z J7 K7 K9 +VREFDQ_A N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 C1261 2.2U_0603_6.3V6K DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0 DDR_A_D3 DDR_A_D1 DDR_A_D2 DDR_A_D4 DDR_A_D7 DDR_A_D0 DDR_A_D6 DDR_A_D5 2 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 U58 +VREFCA_A VREFCA VREFDQ C1260 0.1U_0402_16V4Z M2 N8 M3 D7 C3 C8 C2 A7 A2 B8 A3 1 C1254 0.1U_0402_16V4Z DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 M8 H1 C1259 2.2U_0603_6.3V6K @ C1258 2.2U_0603_6.3V6K 2 C1253 0.1U_0402_16V4Z 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DDR_A_D8 DDR_A_D10 DDR_A_D13 DDR_A_D11 DDR_A_D12 DDR_A_D15 DDR_A_D9 DDR_A_D14 0.1U_0402_16V4Z C1257 +VREFDQ_A N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 E3 F7 F2 F8 H3 H8 G2 H7 0.1U_0402_16V4Z C1256 2 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 0.1U_0402_16V4Z C1255 0.1U_0402_16V4Z C1252 1 U57 +VREFCA_A VREFCA VREFDQ 1 M8 H1 2 U56 +VREFCA_A 1 2 <6> DDR_A_D[0..63] B C D Thursday, April 12, 2012 E Sheet 11 of 51 Rev 1.0 2 F3 C7 DDR_B_DQS1 DDR_B_DQS0 E7 D3 <11,6> DIMM_DRAMRST# DDR_B_DQS#1 DDR_B_DQS#0 G3 B7 DIMM_DRAMRST# T2 1 R1005 2 240_0402_1% 128@ L8 J1 L1 J9 L9 1 R1009 2 240_0402_1% 128@ 1 128@ B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE A1 A8 C1 C9 D2 E9 F1 H2 H9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 M2 N8 M3 DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0 J7 K7 K9 DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE# K1 L2 J3 K3 L3 F3 C7 E7 D3 DDR_B_DQS#2 DDR_B_DQS#3 G3 B7 DIMM_DRAMRST# T2 1 R1006 2 240_0402_1% 128@ B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_DQS2 DDR_B_DQS3 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU 2 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 1 R1010 2 240_0402_1% 128@ L8 J1 L1 J9 L9 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 DDR_B_D16 DDR_B_D23 DDR_B_D17 DDR_B_D22 DDR_B_D21 DDR_B_D18 DDR_B_D20 DDR_B_D19 D7 C3 C8 C2 A7 A2 B8 A3 DDR_B_D30 DDR_B_D25 DDR_B_D27 DDR_B_D28 DDR_B_D26 DDR_B_D29 DDR_B_D31 DDR_B_D24 M8 H1 CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE 1 DQSL DQSU DML DMU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 M2 N8 M3 DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0 J7 K7 K9 DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE# K1 L2 J3 K3 L3 F3 C7 E7 D3 DDR_B_DQS#4 DDR_B_DQS#5 G3 B7 DIMM_DRAMRST# T2 1 R1007 2 240_0402_1% 128@ B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_DQS4 DDR_B_DQS5 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU 2 A1 A8 C1 C9 D2 E9 F1 H2 H9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 2 128@ B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD 128@ +VREFDQ_B +1.35V BA0 BA1 BA2 1 1 R1011 2 240_0402_1% 128@ 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ L8 J1 L1 J9 L9 U63 +VREFCA_B VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 DDR_B_D37 DDR_B_D39 DDR_B_D36 DDR_B_D38 DDR_B_D32 DDR_B_D34 DDR_B_D33 DDR_B_D35 D7 C3 C8 C2 A7 A2 B8 A3 DDR_B_D42 DDR_B_D41 DDR_B_D47 DDR_B_D44 DDR_B_D46 DDR_B_D45 DDR_B_D43 DDR_B_D40 M8 H1 CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE 1 128@ DQSL DQSU DML DMU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 M2 N8 M3 DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0 J7 K7 K9 DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE# K1 L2 J3 K3 L3 F3 C7 E7 D3 DDR_B_DQS#7 DDR_B_DQS#6 G3 B7 DIMM_DRAMRST# T2 1 R1008 2 240_0402_1% 128@ B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_DQS7 DDR_B_DQS6 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU 2 A1 A8 C1 C9 D2 E9 F1 H2 H9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 2 128@ B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD 128@ +VREFDQ_B +1.35V BA0 BA1 BA2 1 1 K1 L2 J3 K3 L3 @ 1 DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE# +VREFDQ_B +1.35V BA0 BA1 BA2 2 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 C1301 0.1U_0402_16V4Z J7 K7 K9 DDR_B_D1 DDR_B_D2 DDR_B_D7 DDR_B_D5 DDR_B_D6 DDR_B_D4 DDR_B_D3 DDR_B_D0 128@ U62 +VREFCA_B VREFCA VREFDQ C1302 2.2U_0603_6.3V6K DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0 D7 C3 C8 C2 A7 A2 B8 A3 M8 H1 1 C1291 2.2U_0603_6.3V6K M2 N8 M3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 DDR_B_D12 DDR_B_D10 DDR_B_D13 DDR_B_D11 DDR_B_D8 DDR_B_D15 DDR_B_D9 DDR_B_D14 C1300 0.1U_0402_16V4Z DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 E3 F7 F2 F8 H3 H8 G2 H7 C1293 2.2U_0603_6.3V6K N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 C1299 0.1U_0402_16V4Z C1298 0.1U_0402_16V4Z C1292 2.2U_0603_6.3V6K 1 @ DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 U61 +VREFCA_B VREFCA VREFDQ E 0.1U_0402_16V4Z C1297 +VREFDQ_B 2 <6> <6> 0.1U_0402_16V4Z C1296 2 2 DDR_B_D[0..63] DDR_B_MA[0..15] 0.1U_0402_16V4Z C1295 0.1U_0402_16V4Z C1294 128@ 1 <6> 2 M8 H1 1 128@ <6> DDR_B_DQS[0..7] U60 +VREFCA_B 1 DDR_B_DQS#[0..7] D 1 Channel B C 2 B 2 A 1 R1012 2 240_0402_1% 128@ L8 J1 L1 J9 L9 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 DDR_B_D61 DDR_B_D58 DDR_B_D60 DDR_B_D62 DDR_B_D56 DDR_B_D59 DDR_B_D57 DDR_B_D63 D7 C3 C8 C2 A7 A2 B8 A3 DDR_B_D55 DDR_B_D52 DDR_B_D51 DDR_B_D49 DDR_B_D54 DDR_B_D48 DDR_B_D50 DDR_B_D53 1 +1.35V BA0 BA1 BA2 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD VDD VDD VDD VDD VDD VDD VDD VDD CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE A1 A8 C1 C9 D2 E9 F1 H2 H9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU DML DMU A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1 2 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 96-BALL SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96 X76@ +1.35V 1 +0.675VS @ R1122 0_0402_5% 1 2 +0.675VS near U60 near U61 near U62 2 near U63 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_B_RAS# 36_0201_1% DDR_B_CAS# 36_0201_1% DDR_B_ODT0 36_0201_1% DDR_B_CKE0 36_0201_1% DDR_B_WE# 36_0201_1% DDR_B_MA10 36_0201_1% DDR_B_CS0# 36_0201_1% DDR_B_BS2 36_0201_1% DDR_B_BS0 36_0201_1% DDR_B_MA12 36_0201_1% DDR_B_MA0 36_0201_1% DDR_B_BS1 36_0201_1% DDR_B_MA3 36_0201_1% DDR_B_MA1 36_0201_1% DDR_B_MA2 36_0201_1% DDR_B_MA4 36_0201_1% DDR_B_MA5 36_0201_1% DDR_B_MA11 36_0201_1% DDR_B_MA9 36_0201_1% DDR_B_MA14 36_0201_1% DDR_B_MA13 36_0201_1% DDR_B_MA6 36_0201_1% DDR_B_MA7 36_0201_1% DDR_B_MA8 36_0201_1% DDR_B_MA15 36_0201_1% DDR_B_RAS# <6> DDR_B_CAS# <6> DDR_B_ODT0 <6> DDR_B_CKE0 DDR_B_WE# DDR_B_CS0# <6> <6> <6> DDR_B_BS0 <6> DDR_B_BS1 <6> B C DDR3 CLK Termination C1506 128@ 1 2 0.1U_0402_16V4Z 128@ R1117 30.1_0402_1% 128@ R1118 30.1_0402_1% END topology <6> DDR_B_CLK0 128@ C1505 1.8P_0201_50V8C <6> DDR_B_CLK0# 1.CAD Note: Cterm= 1.6pF should be kept near feeding point of first SDRAM 4 2.CAD Note: Rtt= 30.1ohms, Ctt= 0.1uF should be kept within 600mils from last SDRAM Compal Electronics, Inc. Compal Secret Data 2012/4/6 Deciphered Date 2013/4/6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A 3 <6> DDR_B_BS2 Security Classification Issued Date Delete U71 SPD EEROM circuit SA00004KS00 S IC EE 2K AT24C02C-XHM-T TSSOP 8P 1 1 1 2 4 2 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 128@ C1484 330U_D2_2V_Y 128@ C1495 10U_0603_6.3V6M 128@ C1493 10U_0603_6.3V6M 128@ C1494 10U_0603_6.3V6M 128@ C1486 10U_0603_6.3V6M 128@ C1496 10U_0603_6.3V6M 128@ C1485 10U_0603_6.3V6M 128@ C1500 10U_0603_6.3V6M C1490 10U_0603_6.3V6M 128@ + 128@ 2.2U_0603_6.3V6K C1507 128@ R1119 1K_0402_1% +1.35V +VREFCA_B 0.1U_0402_16V4Z C1508 1 2 1 2 1 2 1 2 1 2 1 1 2 2 2 1 1 2 128@ C1489 0.1U_0201_10V6K 128@ C1499 1U_0402_6.3V6K 128@ C1492 1U_0402_6.3V6K 128@ C1491 1U_0402_6.3V6K 128@ C1488 0.1U_0201_10V6K 128@ C1498 0.1U_0201_10V6K 128@ C1497 0.1U_0201_10V6K C1487 0.1U_0201_10V6K 128@ 128@ R1120 1K_0402_1% 2 2 +1.35V 2 2 2 2 memory part +1.35V 1 128@ R380 1 128@ R308 1 128@ R339 1 128@ R349 1 128@ R343 1 128@ R348 1 128@ R354 1 128@ R370 1 128@ R340 1 128@ R352 1 128@ R407 1 128@ R351 1 128@ R392 1 128@ R398 1 128@ R377 1 128@ R356 1 128@ R355 1 128@ R359 1 128@ R367 1 128@ R408 1 128@ R335 1 128@ R350 1 128@ R336 1 128@ R344 1 128@ R390 1 2 G 128@ R1121 1K_0402_1% 128@ 128@ 2 1 BSS138_NL_SOT23-3 2 1 Q79 @ 1 2 3 1 1 2 1 2 1 2 1 2 1 2 1 1 2 2 D S 2 DDR3 CTL/ADD Termination +VREFDQ_B <11,14,6> DRAMRST_CNTRL_PCH Layout Note: Place near each 128@ R1123 1K_0402_1% C1510 0.1U_0402_16V4Z 128@ <9> SB_DIMM_VREFDQ C1509 2.2U_0603_6.3V6K 128@ C1515 0.1U_0201_10V6K 128@ C1516 0.1U_0201_10V6K 128@ C1517 1U_0201_4V6M 128@ C1518 0.1U_0201_10V6K 128@ C1501 1U_0201_4V6M 128@ C1502 0.1U_0201_10V6K 128@ C1503 1U_0201_4V6M C1504 1U_0201_4V6M 3 1 M3 support D Title DDRIII DIMMB Size Document Number Custom Date: Q3ZMC M/B LA-8481P Schematic Thursday, April 12, 2012 E Sheet 12 of 51 Rev 1.0 A B C PCH_RTCX1 1 R638 1 R568 0_0603_5% @ 1 1 PCH_RTCRST# 32.768KHZ_12.5PF_9H03200019 SJ100004Z00 1 1 C756 C757 18P_0402_50V8J 18P_0402_50V8J PCH_SRTCRST# 1 1 C502 1U_0402_6.3V6K +RTCBATT PCH_RTCX2 X1 2 1 2 R338 20K_0402_5% 1 2 R337 20K_0402_5% E 2 D5 BAS40-04_SOT23-3 +RTCVCC 2 1 2 2 1 2 2 2 +RTCVCC C516 1U_0402_6.3V6K 2 10M_0402_5% 3 1 D +CHGRTC C197 20MIL 0.1U_0402_16V4Z RTC Battery:Chargeable +RTCVCC R353 1 2 1M_0402_5% SM_INTRUDER# R347 1 2 330K_0402_5% PCH_INTVRMEN INTVRMEN * ：Integrated VRM enable ：Integrated VRM disable H L (INTVRMEN should always be pull high.) U37A C20 HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature PCH_RTCRST# D20 LOW= Disable (Default internal PD) 2 @ R322 1K_0402_5% 2 1 PCH_SRTCRST# G22 SM_INTRUDER# K22 2 R320 <32> HDA_SDO @ HDA_SDOUT_PCH PCH_INTVRMEN C17 1 0_0402_5% HDA_SDO HDA_BITCLK_PCH N34 HDA_SYNC_PCH L34 * ME debug mode,this signal has a weak internal PD Low = Disabled (Default) High = Enabled [Flash Descriptor Security Overide] <33> PCH_SPKR PCH_SPKR T10 HDA_RST_PCH# K34 FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 RTCRST# FWH4 / LFRAME# SRTCRST# INTRUDER# LDRQ0# LDRQ1# / GPIO23 INTVRMEN SERIRQ HDA_BCLK HDA_SYNC SPKR HDA_RST# +VCCSUS3_3 E34 G34 C34 On Die PLL VR Select is supplied by 1.5V when smapled high * HDA_SDOUT_PCH 2 G S <33> HDA_SYNC_AUDIO 1 R676 2 33_0402_5% HDA_SYNC_PCH_R 1 <33> HDA_RST_AUDIO# 1 R673 2 33_0402_5% HDA_RST_PCH# N32 D 1 R677 2 HDA_BITCLK_PCH 33_0402_5% R672 51_0402_5% 2 1 @ 1 R671 100_0402_1% 2 @ @ PCH_JTAG_TDI R669 100_0402_1% R699 1 R700 1 +3VS J3 PCH_JTAG_TMS H7 0_0402_5% R468 1M_0402_5% HDA_SDIN2 HDA_SDIN3 PCH_JTAG_TDI K5 PCH_JTAG_TDO H1 2 3.3K_0402_5% 2 3.3K_0402_5% 1 2 3.3K_0402_5% 2 PCH_SPI_CS1# R733 2 PCH_SPI_MOSI_0 R737 2 PCH_SPI_MOSI_1 R734 1 2 PCH_SPI_MISO_0 R736 2 PCH_SPI_MISO_1 R738 1 PCH_SPI_CLK PCH_SPI_CS0# SPI_WP0# SPI_HOLD0# 1 3 7 4 PCH_SPI_CS1# PCH_SPI_MISO_1 SPI_WP1# PCH_SPI_CS1#_R Y14 T1 0_0402_5% HDA_DOCK_RST# / GPIO13 SATA5RXN SATA5RXP SATA5TXN SATA5TXP JTAG_TCK JTAG_TMS JTAG_TDI SATAICOMPO SATAICOMPI JTAG_TDO SPI_CLK SATA3RBIAS LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 <30,32> <30,32> <30,32> <30,32> CRB:10K ohm Check List 1.0:8.2K ohm D36 LPC_FRAME# LPC_FRAME# <30,32> E36 K36 PCH_GPIO23 PCH_GPIO23 <18> V5 SERIRQ SERIRQ <30,32> SERIRQ R403 2 1 10K_0402_5% PCH_SATALED# R662 2 1 10K_0402_5% +3VS 2 AM3 AM1 AP7 AP5 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 <29> <29> <29> <29> AM10 AM8 AP11 AP10 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 <29> <29> <29> <29> AD7 AD5 AH5 AH4 +3VS AB8 AB10 AF3 AF1 R687 10K_0402_5% Y7 Y5 AD3 AD1 PCH_GPIO21 Y3 Y1 AB3 AB1 +1.05VS_PCH SATA_COMP R389 37.4_0402_1% 1 2 R388 49.9_0402_1% 1 2 +1.05VS_PCH SATA3_COMP Y11 Y10 AB12 AB13 Switchable Graph R688 @ 10K_0402_5% GPIO21 0 1 Switchable * Non SG V4 33_0402_5% 1 PCH_SPI_MOSI U3 33_0402_5% 3 +3VS 1 RBIAS_SATA3 R650 2 750_0402_1% R674 4.7K_0402_5% SPI_CS1# SATALED# SPI_MOSI SATA0GP / GPIO21 SPI_MISO SATA1GP / GPIO19 P3 PCH_SATALED# V14 PCH_GPIO21 P1 PCH_GPIO19 PCH_GPIO19 No use PH 10K +3VS Debug Port DG 1.2 PH 4.7K +3VS GPIO19 has internal Pull up PCH_SPI_MISO 33_0402_5% COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ 1 33_0402_5% VCC SCLK SI SO 8 6 5 2 2MB=16Mb VCC HOLD# SCLK SI B Boot BIOS Strap Boot BIOS +3VS 4MB=32Mb CS# SO WP# GND AH1 SPI_CS0# 1 CS# WP# HOLD# GND 1 2 3 4 T3 33_0402_5% 8 7 6 5 MX25L1606EM2I-12G_SO8 SA00003FO10 A HDA_DOCK_EN# / GPIO33 SATA4RXN SATA4RXP SATA4TXN SATA4TXP LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 33_0402_5% 1 U42 R703 1 HDA_SDO SATA3COMPI PCH_SPI_CLK_0 PCH_SPI_MOSI_0 PCH_SPI_MISO_0 MX25L3206EM2I-12G_SO8 SA00003K800 +3VS SATA3RXN SATA3RXP SATA3TXN SATA3TXP SATA3RCOMPO 2 PCH_SPI_CLK_0 R739 2 PCH_SPI_CLK_1 R704 U40 4 PCH_JTAG_TCK PCH_SPI_CS0# 2 R670 100_0402_1% @ R658 200_0402_5% 1 PCH_JTAG_TMS 1 PCH_JTAG_TDO @ R659 200_0402_5% 2 2 @ +3VALW_PCH 1 R660 200_0402_5% 1 2 @ +3VALW_PCH 2 2 1 R665 2 HDA_SDOUT_PCH 33_0402_5% 2 1 +3VALW_PCH 1 R302 <33> HDA_SDOUT_AUDIO A36 C36 Q20 BSS138W-7-F_SOT323-3 1 HDA_SYNC_PCH 3 3 SATA2RXN SATA2RXP SATA2TXN SATA2TXP HDA_SDIN1 +5VS 1.8V when sampled low Needs to be pulled High for Huron River platfrom <33> HDA_BITCLK_AUDIO A34 Prevent back drive issue. HDA_SDIN0 SATA HDA_SDIN0 <33> HDA_SDIN0 HDA_SYNC_PCH IHDA 1 1K_0402_5% JTAG 2 SATA1RXN SATA1RXP SATA1TXN SATA1TXP SPI R328 This signal has a weak internal pull-down SATA0RXN SATA0RXP SATA0TXN SATA0TXP C38 A38 B37 C37 1 +VCCSUS3_3 RTCX2 2 * RTCX1 1 PCH_RTCX2 2 PCH_SPKR 2 2 1K_0402_5% 1 R405 1 LPC A20 SATA 6G PCH_RTCX1 @ RTC +3VS Reserve for EMI @ PCH_SPI_CLK 1 R977 2 22_0402_5% +3VS SPI_HOLD1# R701 2 PCH_SPI_CLK_1 PCH_SPI_MOSI_1 @ C1216 1 2 * GPIO51 0 0 1 1 GPIO19 0 1 0 1 4 22P_0402_50V8J Issued Date +3VS Compal Electronics, Inc. Compal Secret Data Security Classification 1 3.3K_0402_5% LPC Reserved SPI 2012/4/6 2013/4/6 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C D Title PCH (1/8) SATA,HDA,SPI, LPC, XDP Size Document Number Custom Q3ZMC M/B LA-8481P Schematic Date: Thursday, April 12, 2012 Sheet E 13 of 51 Rev 1.0 A B C D E +VCCSUS3_3 U37B Y40 Y39 No use PH 10K +3VALW 2 Y37 Y36 LAN_CLKREQ# <22> CLK_PCIE_CARD# <22> CLK_PCIE_CARD Card Reader <22> CARD_CLKREQ# A8 Y43 Y45 CARD_CLKREQ# L12 V45 V46 No use PH 10K +3VALW 3 MINI2_CLKREQ# L14 AB42 AB40 No use PH 10K +3VALW PEG_CLKREQ# E6 V40 V42 No use PH 10K +3VALW <24> CLK_TB_REFCLK# <24> CLK_TB_REFCLK <24> TB_CLKREQ# PCH_GPIO45 CLK_TB_REFCLK# CLK_TB_REFCLK V38 V37 TB_CLKREQ# K12 AK14:CLKOUT_ITPXDP_N AK13:CLKOUT_ITPXDP_P No use PH 10K +3VALW 4 2 1 10K_0402_5% MINI1_CLKREQ# R686 2 1 10K_0402_5% TB_SMB_DA_GPIO6 AK14 AK13 2 10K_0402_5% PCH_SML1CLK R375 1 2 2.2K_0402_5% PCH_SML1DATA R369 1 2 2.2K_0402_5% PCH_GPIO47 R683 1 2 10K_0402_5% No use PH 10K +3VALW S3 reduse 1 No use PH 10K +3VALW PH 2.2K +3VALW CL_CLK1 +3VS M7 3 PCH_SMBDATA CL_DATA1 CL_RST1# T11 P10 PEG_A_CLKRQ# / GPIO47 CLKOUT_PCIE0N CLKOUT_PCIE0P CLKOUT_PEG_A_N CLKOUT_PEG_A_P M10 PCH_GPIO47 AB37 AB38 AV22 AU22 CLK_CPU_DMI# CLK_CPU_DMI 1 10K_0402_5% PCH_GPIO73 R399 2 1 10K_0402_5% LAN_CLKREQ# R684 2 1 10K_0402_5% CARD_CLKREQ# R410 2 1 10K_0402_5% MINI2_CLKREQ# R400 2 1 10K_0402_5% PEG_CLKREQ# R414 2 1 10K_0402_5% PCH_GPIO45 R425 2 1 10K_0402_5% TB_CLKREQ# A 1 D_CK_SCLK Q27B DMN66D0LDW-7_SOT363-6 D_CK_SCLK <33> Pull up at EC side. For DDR,EC 3 AM12 AM13 CLK_CPU_DPLL# CLK_CPU_DPLL 4 EC_SMB_DA2 2 EC_SMB_DA2 <11,24,32> Q22A DMN66D0LDW-7_SOT363-6 CLK_CPU_DMI# <5> CLK_CPU_DMI <5> PCIECLKRQ1# / GPIO18 CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P CLKOUT_PCIE2N CLKOUT_PCIE2P CLKIN_DMI_N CLKIN_DMI_P PCIECLKRQ2# / GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P CLKIN_GND1_N CLKIN_DMI2_N CLKIN_GND1_P CLKIN_DMI2_P PCIECLKRQ3# / GPIO25 CLKIN_DOT_96N CLKIN_DOT_96P CLKOUT_PCIE4N CLKOUT_PCIE4P CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P PCIECLKRQ4# / GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P REFCLK14IN PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLKOUT_PEG_B_N CLKOUT_PEG_B_P XTAL25_IN XTAL25_OUT BF18 BE18 CLK_CPU_DPLL# <5> CLK_CPU_DPLL <5> CLK_BUF_CPU_DMI# CLK_BUF_CPU_DMI 2 10K_0402_5% 2 10K_0402_5% BJ30 BG30 CLKIN_GND1# CLKIN_GND1 R330 1 R331 1 2 10K_0402_5% 2 10K_0402_5% G24 E24 CLK_BUF_DREF_96M# CLK_BUF_DREF_96M R346 1 R345 1 2 10K_0402_5% 2 10K_0402_5% AK7 AK5 CLK_BUF_PCIE_SATA# R387 1 CLK_BUF_PCIE_SATA R393 1 2 10K_0402_5% 2 10K_0402_5% K45 CLK_BUF_ICH_14M R292 1 2 10K_0402_5% H45 CLK_PCI_LPBACK V47 V49 XTAL25_IN XTAL25_OUT Y47 XCLK_RCOMP 2 R293 @ 1 EC_SMB_CK2 Q22B DMN66D0LDW-7_SOT363-6 EC_SMB_CK2 <11,24,32> Pull down 10K ohm for using internal Clock 1 1 33_0402_5% C421 2 22P_0402_50V8J CLK_PCI_LPBACK <17> 3 @ Reserve for EMI please close to PCH R289 90.9_0402_1% 1 2 PEG_B_CLKRQ# / GPIO56 XCLK_RCOMP 6 PCH_SML1CLK 120MHz for eDP. R357 1 R358 1 +1.05VS_PCH CLKOUT_PCIE6N CLKOUT_PCIE6P +3VS PCIECLKRQ6# / GPIO45 CLKOUT_PCIE7N CLKOUT_PCIE7P PCIECLKRQ7# / GPIO46 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67 K43 CLK_FLEX0 @ F47 CLK_FLEX1 @ H47 CLK_FLEX2 @ K49 DGPU_PRSNT# T52 PAD T53 PAD T21 PAD R610 10K_0402_5% UMA@ DGPU_PRSNT# XTAL25_IN R628 10K_0402_5% @ 1 R611 XTAL25_OUT 3 Check List R1.0 p.37 Clock Req# pull high power source DIS,Optimus UMA Issued Date 2012/4/6 3 1 C744 8.2P_0402_50V8D 0 1 1 GND 4 1 GND Y1 1 2 2 2 C745 4 8.2P_0402_50V8D Compal Electronics, Inc. Compal Secret Data Security Classification 2 1M_0402_5% 25MHZ_10PF_7V25000014 GPIO67 +VCCSUS3_3 2 D_CK_SDATA <33> +3VS No use PH 10K +3VALW PCH_SML1DATA CLKOUT_DMI_N CLKOUT_DMI_P +3VS 4 D_CK_SDATA Q27A DMN66D0LDW-7_SOT363-6 R415 4.7K_0402_5% 1 2 +3VS 6 DGPU_PRSNT# R652 For TP R427 4.7K_0402_5% 1 2 PCH_SMBCLK COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ +3VS R424 T13 1 S No use PH 10K +3VALW V10 R647 D TB_SMB_DA_GPIO6 No use PH 10K +3VS 1K_0402_5% PCH_GPIO74 G <24> TB_SMB_DA_GPIO6 M1 AA48 AA47 PERN8 PERP8 PETN8 PETP8 CLKOUT_PCIE1N CLKOUT_PCIE1P 2 S MINI1_CLKREQ# No use PH 10K +3VS PERN7 PERP7 PETN7 PETP7 PCIECLKRQ0# / GPIO73 1 D AB49 AB47 <28> CLK_PCIE_MINI1# <28> CLK_PCIE_MINI1 <28> MINI1_CLKREQ# J2 R648 G Mini Card 1 (On Board WLAN) PCH_GPIO73 PCH_SML1DATA 2.2K_0402_5% DRAMRST_CNTRL_PCH 2 BE38 BC38 AW 38 AY38 M16 2.2K_0402_5% 2 2 2 0.1U_0201_10V6K 2 0.1U_0201_10V6K PCIE_PRX_DTX_N8 PCIE_PRX_DTX_P8 PCIE_PTX_DRX_N8 PCIE_PTX_DRX_P8 S3 reduse PCH_SML1CLK 2 1 5 BG40 BJ40 AY40 BB40 DRAMRST_CNTRL_PCH <11,12,6> G12 PCH_GPIO74 1 R664 S 2 0.1U_0201_10V6K 2 0.1U_0201_10V6K PCIE_PRX_DTX_N7 PCIE_PRX_DTX_P7 PCIE_PTX_DRX_N7 PCIE_PTX_DRX_P7 PERN6 PERP6 PETN6 PETP6 C8 E14 R668 PCH_SMBDATA D 1 1 BJ38 BG38 AU36 AV36 SML1DATA / GPIO75 PH 2.2K +3VALW DRAMRST_CNTRL_PCH C13 PCH_SMBCLK SMB_ALERT# <33> G C688 C687 1 1 2 0.1U_0201_10V6K 2 0.1U_0201_10V6K PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6 SML1CLK / GPIO58 10K_0402_5% S <24> PCIE_PRX_DTX_N8 <24> PCIE_PRX_DTX_P8 <24> PCIE_PTX_C_DRX_N8 <24> PCIE_PTX_C_DRX_P8 C686 C685 1 1 2 0.1U_0201_10V6K 2 0.1U_0201_10V6K SML1ALERT# / PCHHOT# / GPIO74 A12 2 D <24> PCIE_PRX_DTX_N7 <24> PCIE_PRX_DTX_P7 <24> PCIE_PTX_C_DRX_N7 <24> PCIE_PTX_C_DRX_P7 C684 C683 1 1 PERN5 PERP5 PETN5 PETP5 SML0DATA PCH_SMBDATA 1 G <24> PCIE_PRX_DTX_N6 <24> PCIE_PRX_DTX_P6 <24> PCIE_PTX_C_DRX_N6 <24> PCIE_PTX_C_DRX_P6 Thunderbolt C681 C682 BG37 BH37 AY36 BB36 SML0CLK C9 R383 2 <24> PCIE_PRX_DTX_N5 <24> PCIE_PRX_DTX_P5 <24> PCIE_PTX_C_DRX_N5 <24> PCIE_PTX_C_DRX_P5 PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5 PERN4 PERP4 PETN4 PETP4 SML0ALERT# / GPIO60 PCH_SMBCLK SMB_ALERT# 5 BF36 BE36 AY34 BB34 PERN3 PERP3 PETN3 PETP3 H14 No use PH 10K +3VALW 1 1 SMBDATA SMB_ALERT# 2 BG36 BJ36 AV34 AU34 PERN2 PERP2 PETN2 PETP2 E12 1 BE34 BF34 BB32 AY32 SMBCLK Link 2 0.1U_0201_10V6K 2 0.1U_0201_10V6K PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2 SMBALERT# / GPIO11 SMBUS 1 1 2 0.1U_0201_10V6K 2 0.1U_0201_10V6K PERN1 PERP1 PETN1 PETP1 Controller C573 C572 1 1 BG34 BJ34 AV32 AU32 FLEX CLOCKS <28> PCIE_PRX_DTX_N2 <28> PCIE_PRX_DTX_P2 <28> PCIE_PTX_C_DRX_N2 <28> PCIE_PTX_C_DRX_P2 Mini Card 1 On Board WLAN C617 C678 PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1 CLOCKS Card Reader PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 PCI-E* <22> <22> <22> <22> 2013/4/6 Deciphered Date Title PCH (2/8) PCIE, SMBUS, CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: B C D Thursday, April 12, 2012 Sheet E 14 of 51 Rev 1.0 A B C D E U37C PCH_GPIO30 1 10K_0402_5% PCH_GPIO72 R649 2 1 10K_0402_5% RI# R373 2 1 200_0402_5% PM_DRAM_PWRGD 1 10K_0402_5% PCH_ACIN +3VALW_PCH 1 R341 R634 2 @ 2 1 10K_0402_5% BC24 BE20 BG18 BG20 <4> <4> <4> <4> DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 BE24 BC20 BJ18 BJ20 <4> <4> <4> <4> DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 AW24 AW20 BB18 AV18 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 AY24 AY20 AY18 AU18 <4> <4> <4> <4> PCH_RSMRST# DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI0RXN DMI1RXN DMI2RXN DMI3RXN FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 FDI_INT +1.05VS_PCH BJ24 1 R625 1 R632 2 DMI_IRCOMP 49.9_0402_1% 2 DMI2RBIAS 750_0402_1% BG25 BH21 DMI_ZCOMP FDI_FSYNC0 DMI_IRCOMP FDI_FSYNC1 DMI2RBIAS FDI_LSYNC0 FDI_LSYNC1 4mil width and place within 500mil of the PCH not support Deep S4,S5 mux with SUS_PWR_DN_ACK <32> SUSACK# 2 @ R372 1 <5> XDP_DBRESET# 2 @ R661 SUSACK#_R 0_0402_5% 1 PCH_PWROK R382 2 2 PCH_PWROK_R 0_0402_5% @ K3 XDP_DBRESET#_R 0_0402_5% SYS_PWROK not support AMT APWROK can mux with PWROK (check list1.0 P.40) C12 P12 L22 L10 PM_DRAM_PWRGD B13 <5> PM_DRAM_PWRGD <32> PCH_RSMRST# 1 <32> SUSWARN# 2 @ R412 <32> ACPRESENT R456 2 PCH_ACIN 0_0402_5% C21 PCH_GPIO30 0_0402_5% K16 PBTN_OUT# <32> PBTN_OUT# 1 PCH_RSMRST# 1 @ <32,35,38,39> ACIN D19 2 PCH_ACIN RB751V-40_SOD323-2 E20 H20 No use PH 10K +3VALW PCH_GPIO72 E10 Ring Indicator CRB1.0 PH 10K +3VALW RI# A10 System Power Management DSWVRMEN 1 SUSACK# SYS_RESET# SYS_PWROK PWROK APWROK DRAMPWROK RSMRST# BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 <4> <4> <4> <4> <4> <4> <4> <4> BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 <4> <4> <4> <4> <4> <4> <4> <4> AW16 FDI_INT AV12 FDI_FSYNC0 BC10 FDI_FSYNC1 AV14 FDI_LSYNC0 BB10 A18 WAKE# CLKRUN# / GPIO32 SUS_STAT# / GPIO61 +RTCVCC FDI_INT <4> FDI_FSYNC0 <4> FDI_FSYNC1 <4> DSWODVREN FDI_LSYNC0 <4> FDI_LSYNC1 * FDI_LSYNC1 <4> DSWODVREN E22 R426 1 @ B9 R421 PCH_PCIE_WAKE# N3 CLKRUN# G8 SUS_STAT# N14 SUSCLK_R 1 2 PCH_RSMRST# 0_0402_5% 2 DPWROK 0_0402_5% DPWROK <32> SLP_S5# / GPIO63 SLP_S4# SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# PWRBTN# SLP_A# ACPRESENT / GPIO31 SLP_SUS# BATLOW# / GPIO72 PMSYNCH RI# SLP_LAN# / GPIO29 D10 PM_SLP_S5# H4 PM_SLP_S4# F4 PM_SLP_S3# G10 SLP_A# G16 SLP_SUS# AP14 H_PM_SYNC K14 PCH_GPIO29 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ 2 R360 2 1 330K_0402_5% 1 330K_0402_5% @ ： ： DSWODVREN - On Die DSW VR Enable H Enable internal DSW +1.05VS not support Deep S4,S5 DPWROK mux with RSMRST# check list1.0 P.42 PCH_PCIE_WAKE# <24,28> CLKRUN# <30> No T15 @ CRB=>1k ohm Follow Check List R1.5 use PH 10K +3VS 2 0_0402_5% 1 PCH_GPIO29 1 +VCCSUS3_3 2 10K_0402_5% R395 @ PM_SLP_S4# <32> +3VS CLKRUN# PM_SLP_S3# <32> Can be left NC when IAMT is not support on the platfrom SLP_SUS# <32> not support Deep S4,S5 can NC PCH EDS1.2 P.74 PAD 2 2 10K_0402_5% SUSCLK <32> PM_SLP_S5# <32> T51 @ PCH_PCIE_WAKE# R656 PAD @ R973 SUSCLK / GPIO62 R361 L Disable Must always PH at +RTCVCC 1 S3@ DPWROK 1 R653 1 2 8.2K_0402_5% DPWROK 1 1 10K_0402_5% 2 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 R463 100K_0402_5% 2 2 R402 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 FDI R378 <4> <4> <4> <4> DMI +VCCSUS3_3 H_PM_SYNC <5> No use PH 10K +3VALW 是是是是NC 3 3 5 Y 3 SYS_PWROK MC74VHC1G08DFT2G_SC70-5 SYS_PWROK <5> 2 R681 10K_0402_5% 2 R680 10K_0402_5% 4 SYS_PWROK 1 1 <43> VGATE ALL power OK P <32> PCH_PWROK +3VS U39 2 B 1 A G tell PCH all power ok but cpu core C603 1 1 .047U_0402_16V7K @ 2 2 C789 100P_0402_50V8J 4 4 VGATE VGATE 1 2 1 C790 100P_0402_50V8J 2 C791 100P_0201_25V8J Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 2013/4/6 Deciphered Date Title PCH (3/8) DMI,FDI,PM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A B C D Thursday, April 12, 2012 Sheet E 15 of 51 Rev 1.0 A B C D E UMA Panel Backlight ON/OFF ENBKL R612 2 @ 1 0_0402_5% IGPU_BKLT_EN U37D P45 <22> DPST_PWM 1 J47 M45 T40 K47 Delete LVDS function T45 P39 AF37 AF36 AE48 AE47 AK39 AK40 AN48 AM47 AK47 AJ48 AN47 AM49 AK49 AJ47 AF40 AF39 2 LVDS disable: DATA/Clock/Control can NC VCC_TX_LVDS,VCCA_LVDS connected to GND AH45 AH47 AF49 AF45 AH43 AH49 AF47 AF43 N48 P49 T49 CRT disable: DATA/Clock/Control can NC DAC_IREF still need PD VCCADAC connected to +3VS T39 M40 M47 M49 CRT_IREF L_BKLTCTL AM42 AM40 SDVO_STALLN SDVO_STALLP L_DDC_CLK L_DDC_DATA AP39 AP40 SDVO_INTN SDVO_INTP L_CTRL_CLK L_CTRL_DATA LVD_IBG LVD_VBG SDVO_CTRLCLK SDVO_CTRLDATA LVD_VREFH LVD_VREFL LVDSA_CLK# LVDSA_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 DDPB_AUXN DDPB_AUXP DDPB_HPD CRT_BLUE CRT_GREEN CRT_RED DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P DDPC_CTRLCLK DDPC_CTRLDATA DAC_IREF CRT_IRTN SDVO_SCLK SDVO_SDATA AT49 AT47 AT40 PCH_DPB_HPD AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49 PCH_DPB_N0 PCH_DPB_P0 PCH_DPB_N1 PCH_DPB_P1 PCH_DPB_N2 PCH_DPB_P2 PCH_DPB_N3 PCH_DPB_P3 SDVO_SCLK <23> SDVO_SDATA <23> PCH_DPB_HPD <23> PCH_DPB_N0 PCH_DPB_P0 PCH_DPB_N1 PCH_DPB_P1 PCH_DPB_N2 PCH_DPB_P2 PCH_DPB_N3 PCH_DPB_P3 <23> <23> <23> <23> <23> <23> <23> <23> HDMI D2 HDMI D1 HDMI D0 HDMI CLK AP47 AP49 AT38 DDPC_AUXN DDPC_AUXP DDPC_HPD 2 AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P DDPD_AUXN DDPD_AUXP DDPD_HPD DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P CRT_HSYNC CRT_VSYNC P38 M39 P46 P42 DDPD_CTRLCLK DDPD_CTRLDATA CRT_DDC_CLK CRT_DDC_DATA 1 SDVO_CTRLDATA strap pull high at level shift page M43 M36 PCH_DPD_CLK PCH_DPD_DAT AT45 AT43 BH41 PCH_DPD_AUXN PCH_DPD_AUXP DPD_HPD BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 PCH_DPD_N0 PCH_DPD_P0 PCH_DPD_N1 PCH_DPD_P1 PCH_DPD_N2 PCH_DPD_P2 PCH_DPD_N3 PCH_DPD_P3 PCH_DPD_CLK <25> PCH_DPD_DAT <25> PCH_DPD_AUXN <24> PCH_DPD_AUXP <24> DPD_HPD <24> PCH_DPD_N0 PCH_DPD_P0 PCH_DPD_N1 PCH_DPD_P1 PCH_DPD_N2 PCH_DPD_P2 PCH_DPD_N3 PCH_DPD_P3 <24> <24> <24> <24> <24> <24> <24> <24> Thunderbolt 3 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ R307 1K_0402_5% 2 For CRT diable =>Change 1K 0.5% to 5% AP43 AP45 SDVO_TVCLKINN SDVO_TVCLKINP 1 3 T43 T42 L_BKLTEN L_VDD_EN Digital Display Interface IGPU_BKLT_EN <22> PCH_ENVDD LVDS PD 100K at EC side CRT <32> ENBKL +3VS R252 1 2 2.2K_0402_5% R254 1 2 2.2K_0402_5% PCH_DPD_DAT PCH_DPD_CLK 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 Deciphered Date 2013/4/6 Title PCH (4/9) LVDS,CRT,DP,HDMI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A B C D Thursday, April 12, 2012 Sheet E 16 of 51 Rev 1.0 A B C E U37E 1 R433 R434 R435 R439 1 1 1 1 2 2 2 2 8.2K_0402_5% PCH_GPIO55 8.2K_0402_5% PCH_GPIO53 8.2K_0402_5% PCH_GPIO52 8.2K_0402_5% PCH_GPIO5 R442 R443 R444 R445 1 1 1 1 2 2 2 2 8.2K_0402_5% PCH_GPIO51 8.2K_0402_5% PCH_GPIO2 8.2K_0402_5% ODD_DA# 8.2K_0402_5% PCH_GPIO4 NV_DQS0 NV_DQS1 +3VS R267 1 B21 M20 AY16 BG46 2 10K_0402_5% DGPU_PWR_EN +3VS NV_RB# PCH_USB3_RX1_N PCH_USB3_RX2_N PCH_USB3_RX1_P PCH_USB3_RX2_P <31> PCH_USB3_RX1_P <31> PCH_USB3_RX2_P USB3.0 PCH_USB3_TX1_N PCH_USB3_TX2_N <31> PCH_USB3_TX1_N <31> PCH_USB3_TX2_N 2 Boot BIOS Strap Internal PH NV_RCOMP 2 8.2K_0402_5% DGPU_HOLD_RST# <31> PCH_USB3_RX1_N <31> PCH_USB3_RX2_N GNT1#/ GPIO51 NV_ALE NV_CLE PCH_USB3_TX1_P PCH_USB3_TX2_P <31> PCH_USB3_TX1_P <31> PCH_USB3_TX2_P GPIO19 GPIO51 Boot BIOS Bit10 Destination Bit11 0 1 BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40 BE28:USB3Rn1 BC30:USB3Rn2 BE32:USB3Rn3 BJ32:USB3Rn4 BC28:USB3Rp1 BE30:USB3Rp2 BF32:USB3Rp3 BG32:USB3Rp4 AV26:USB3Tn1 BB26:USB3Tn2 AU28:USB3Tn3 AY30:USB3Tn4 AU26:USB3Tp1 AY26:USB3Tp2 AV28:USB3Tp3 AW30:USB3Tp4 NV_RE#_WRB0 NV_RE#_WRB1 NV_WE#_CK0 NV_WE#_CK1 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P Reserved 1 0 PCI 1 1 SPI 0 0 LPC PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# K40 K38 H38 G38 Used as GPIO only. External pull-up of 8.2 kOhms to 10 kOhms to +V3.3S required. DGPU_HOLD_RST# PCH_GPIO52 DGPU_PWR_EN C46 C44 E40 無無 PCH_GPIO51 PCH_GPIO53 PCH_GPIO55 D47 E42 F46 PCH_GPIO2 ODD_DA# PCH_GPIO4 PCH_GPIO5 G42 G40 C42 D44 Used as GPIO only. PH(Internal PH), * PCI Interrupt Requests 如如GPIO PH +3VS PAD K10 T13 @ 3 <22,24,30,32,5> PLT_RST# CLK_PCI_LPBACK CLK_PCI_LPC CLK_PCI_TXM <14> CLK_PCI_LPBACK <32> CLK_PCI_LPC <30> CLK_PCI_TXM R604 R316 R327 2 1 1 PLT_RST# 1 22_0402_5% 2 22_0402_5% 2 22_0402_5% T7 @ T8 @ PAD PAD CLK_PCI0 CLK_PCI1 CLK_PCI2 CLK_PCI3 CLK_PCI4 C6 H49 H43 J48 K42 H40 PIRQA# PIRQB# PIRQC# PIRQD# REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 USB R310 1 TP21 TP22 TP23 TP24 NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 USBRBIAS# USBRBIAS AT10 BC8 DMI,FDI Termination Voltage AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 AV5 AY1 Set to Vcc when HIGH DF_TVS 1 Set to Vss when LOW DG1.2 CRB1.0 PH 2.2K series 1K For 2012 support +1.8VS 1 8.2K_0402_5% PCI_PIRQC# 8.2K_0402_5% PCI_PIRQB# 8.2K_0402_5% PCI_PIRQA# 8.2K_0402_5% PCI_PIRQD# AY7 AV7 AU3 BG4 R651 2.2K_0402_5% 2 R654 DF_TVS 1 1K_0402_5% 2 2 2 2 2 NVRAM 1 1 1 1 NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 PCI R423 R428 R431 R432 BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45 RSVD +3VS Only GPIO function D H_SNB_IVB# <5> AV10 CLOSE TO THE BRANCHING POINT AT8 AY5 BA2 AT12 BF3 C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32 USB20_N0 USB20_P0 USB20_N1 USB20_P1 C33 USBRBIAS USB20_N0 USB20_P0 USB20_N1 USB20_P1 <31> <31> <31> <31> USB3 ( side) USB3 ( side) 2 USB3 ( side) USB3 ( side) EHCI 1 Some PCH config not support USB port 6 & 7. USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N8 <28> USB20_P8 <28> USB20_N9 <31> USB20_P9 <31> USB20_N10 <22> USB20_P10 <22> WLAN USB(Bluetooth) Debug Port CMOS Camera (LVDS) EHCI 2 Mini Card (mSATA) 1 R620 2 22.6_0402_1% Within 500 mils B33 +VCCSUS3_3 PME# PLTRST# CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 3 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 A14 K20 B17 C16 L16 A16 D14 C14 USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7# USB_OC0# USB_OC0# <31> USB_OC2# USB_OC7# USB_OC5# 2 R384 2 R401 2 R374 2 R379 1 10K_0402_5% 1 10K_0402_5% 1 10K_0402_5% 1 10K_0402_5% 2 R448 2 R447 2 R386 2 R446 1 10K_0402_5% 1 10K_0402_5% 1 10K_0402_5% 1 10K_0402_5% +VCCSUS3_3 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ USB_OC1# USB_OC4# R371 0_0402_5% 2 1 @ USB_OC3# USB_OC6# IRST_RST# R461 1 2 0_0402_5% 4 PLT_RST_BUF# <28> 1 Y R376 100K_0402_5% MC74VHC1G08DFT2G_SC70-5 2 <32> IRST_RST# @ G 1 R462 U26 2 B 2 IRST_RST_R# 1 A 0_0402_5% 3 PLT_RST# P 5 +3VS 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 2013/4/6 Deciphered Date Title PCH (5/9) PCI, USB, NVRAM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A B C D Thursday, April 12, 2012 Sheet E 17 of 51 Rev 1.0 A B C D E HDA_SYNC PH(PLL =+1.5VS) 1 @ R618 10K_0402_5% 2 10K_0402_5% No use PH 10K +3VS DGPU_HPD_INT# H36 EC_SCI# E38 EC_SMI# C10 No use PH +3VALW <24> TB_FORCE_PWR EC LID SW OUT No use PH +3VALW No use PH +3VS <32> EC_LID_OUT# <29> MSATA_DET# TB_FORCE_PWR C4 EC_LID_OUT# G2 MSATA_DET# 2 1 2 10K_0402_5% 1 2 10K_0402_5% U2 D40 ODD_DETECT# WWAN_OFF# SATA2GP/GPIO36,SATA3GP/GPIO37 1.Used as for Mechanical Presence detect Use a weak external pull-up (150K-200k Ohms) to Vcc3_3 or use 10K external pull-up that is enabled only after PLTRST# de-assertion. 2.Used as GP Input (Pin HW default) Ensure GPI is not driven high during strap sampling window No use PH 10K +3VS PCH_GPIO22 T5 CRB1.0 PH 10K +3VALW PCH_GPIO24 E8 No use PD 10K to GND PCH_GPIO27 E16 No use PH 10K +3VALW PCH_GPIO28 P8 No use PH 10K +3VS PCH_GPIO34 K1 RAID0_DET K4 No use can NC(+3VS power plane) <29> RAID0_DET V8 Can't PH ODD_DETECT# Can't PH WWAN_OFF# M5 No use PH 10K +3VS Optimus(L)/ non optimus(H) OPTIMUS_EN# N2 No use PH 10K +3VS PCH_GPIO39 M3 No use PH 10K +3VS PCH_GPIO48 V13 SATA5GP&TEMP_ALERT# CRB PH 10K +3VS <24> TB_SMB_CK_GPIO7 No use PH +3VALW TB_SMB_CK_GPIO7 V3 PCH_GPIO57 D6 BMBUSY# / GPIO0 TACH4 / GPIO68 TACH1 / GPIO1 TACH5 / GPIO69 TACH2 / GPIO6 TACH6 / GPIO70 TACH3 / GPIO7 TACH7 / GPIO71 A44 UMA@ +3VS 1 R406 @ 2 10K_0402_5% R429 1 R430 1 TB_PLUG_EVENT 2 10K_0402_5% OPTIMUS_EN# A45 A46 @ 2 10K_0402_5% R614 1 2 10K_0402_5% PCH_GPIO1 A5 R326 1 2 10K_0402_5% DGPU_HPD_INT# A6 R663 1 2 10K_0402_5% MSATA_DET# GPIO38 R305 1 2 10K_0402_5% DGPU_PWROK OPTIMUS_EN# 3 * Muxless nonMuxless B3 B47 BD1 0 1 BD49 BE1 R675 1 2 10K_0402_5% PCH_GPIO34 R679 1 2 10K_0402_5% PCH_GPIO48 R404 1 2 10K_0402_5% TB_SMB_CK_GPIO7 Define Q5LJ1(DDR3) or Q3ZMC(DDR3L) +VCCSUS3_3 R458 BE49 BF1 1 2 10K_0402_5% PCH_GPIO24 BF49 DDR3@ R457 1 2 10K_0402_5% DDR3L@ PCH_GPIO70 A40 PCH_GPIO71 1 2 1 1 +3VS R419 10K_0402_5% GPIO15 A20GATE SATA4GP / GPIO16 TACH0 / GPIO17 SCLOCK / GPIO22 GPIO24 / MEM_LED PECI RCIN# PROCPWRGD THRMTRIP# INIT3_3V# P4 GATEA20 <32> AU16 PCH_PECI_R P5 EC_KBRST# 1 2 @ 0_0402_5% R248 AY11 AY10 PCH_THRMTRIP#_R 1 R385 STP_PCI# / GPIO34 NC_2 GPIO35 NC_3 SATA2GP / GPIO36 NC_4 SATA3GP / GPIO37 NC_5 CTRL+ALT+DEL 2 H_THRMTRIP# 390_0402_5% non CPU power ok H_THRMTRIP# <5> 130c shut sown T14 INIT3_3V NC_1 PECI CPU-EC EC_KBRST# <32> H_CPUPWRGD <5> GPIO27 GPIO28 H_PECI <32,5> Check list1.0 P.59 +3VS This signal has weak internal PU, can't pull low,leave NC AH8 ODD_EN# R324 1 2 10K_0402_5% EC_KBRST# R420 1 2 10K_0402_5% AH10 TS_VSS1~4 PD to GND AK10 P37 SLOAD / GPIO38 SDATAOUT0 / GPIO39 SDATAOUT1 / GPIO48 VSS_NCTF_15 SATA5GP / GPIO49 VSS_NCTF_16 GPIO57 VSS_NCTF_17 VSS_NCTF_1 VSS_NCTF_19 VSS_NCTF_2 VSS_NCTF_20 VSS_NCTF_3 VSS_NCTF_21 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_6 VSS_NCTF_24 VSS_NCTF_7 VSS_NCTF_25 VSS_NCTF_8 VSS_NCTF_26 VSS_NCTF_9 VSS_NCTF_27 VSS_NCTF_10 VSS_NCTF_28 VSS_NCTF_11 VSS_NCTF_29 VSS_NCTF_12 VSS_NCTF_30 VSS_NCTF_13 VSS_NCTF_31 VSS_NCTF_14 VSS_NCTF_32 BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 3 BJ6 C2 GPIO39 GPIO23 GPIO22 0 0 0 0 0 0 1 1 0 1 0 1 Elpida DDP 1GB*8 (Ch A,B) Elpida DDP 1GB*4 (Ch A) Elpida Mono 512MB*8(Ch A,B) Hynix Mono 512MB*8(Ch A,B) C48 D1 D49 E1 E49 +3VS F1 R274 1 X76@ 2 10K_0402_5% R275 1 X76@ 2 10K_0402_5% R278 1 X76@ 2 10K_0402_5% R279 1 X76@ 2 10K_0402_5% R281 1 X76@ 2 10K_0402_5% R282 1 X76@ 2 10K_0402_5% PCH_GPIO22 F49 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ PCH_GPIO24 R657 1 2 10K_0402_5% TB_FORCE_PWR R391 1 2 1K_0402_5% EC_LID_OUT# 1 2 10K_0402_5% R397 @ * DDR3L(Q3ZMC) DDR3 PCH_GPIO23 PCH_GPIO23 <13> Remove NCTF test point 2011/9/23 0 1 PCH_GPIO57 GPIO24 Unmultiplexed NOTE: GPIO24 configuration register bits are not cleared by CF9h reset event. CRB1.0 PH10K to +3VALW GPIO36/GPIO37 is Strap functionality that requires internal pull down to be sampled at rising PWROK. When uses as SATA2GP/SATA3GP for mechanical presence detect -use a external pull up 150K-200K ohm to Vcc3_3 When used as GP input -ensure GPI is not driven high during strap sampling window When Unused as GPIO or SATA*GP -use 8.2K-10K pull-down check list page 47 Issued Date 2012/4/6 B PCH_GPIO39 4 Compal Electronics, Inc. Compal Secret Data Security Classification 2013/4/6 Deciphered Date Title PCH (6/9) GPIO, CPU, MISC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A 2 AK11 GPIO24 +VCCSUS3_3 4 PCH_GPIO69 C41 LAN_PHY_PWR_CTRL / GPIO12 NCTF A4 +3VS ODD_EN# B41 GPIO8 VSS_NCTF_18 3.Unused as GPIO or SATA*GP Use 8.2K-10K pull-down to ground. C40 1 A42 PCH_GPIO27 HR Check List R364 1 1 PCH_GPIO1 DGPU_PWROK 1 T7 No use PH 10K +3VS <32> EC_SMI# Deep S4,S5 wake event signal RTC alarm,Power BTN,GPIO27 PCH_GPIO27 (Have internal Pull-High) Deep S4,S5 wake event signal No use PD to GND,HR Check list1.0 P.70 TB_PLUG_EVENT CPU/MISC 2 1 R417 1K_0402_5% <24> TB_PLUG_EVENT <32> EC_SCI# R363 R621 10K_0402_5% U37F No use PH 10K +3VS GPIO 2 PCH_GPIO28 Debug Port DG 1.2 PH 4.7K +3VALW_PCH R362 PCH_GPIO70 R619 10K_0402_5% GPIO69 GPIO70 0 0 0 1 1 0 1 1 1 R422 4.7K_0402_5% @ PCH_GPIO69 1 1 @R617 @ R617 10K_0402_5% 2 PCH_GPIO71 不不不 For eDP only, eDP or LVDS +VCCSUS3_3 @R616 @ R616 10K_0402_5% 2 H On-Die PLL voltage regulator enable L On-Die PLL Voltage Regulator disable Project ID * x x x x +3VS 2 * +3VS 2 ：： This signal has a weak internal pull up @ R615 10K_0402_5% 2 On-Die PLL Voltage Regulator +3VS GPIO71 1 0 2 LVDS/eDP LVDS eDP GPIO28 C D Thursday, April 12, 2012 Sheet E 18 of 51 Rev 1.0 A B C D E Thermal Senser share with VCCADAC power rail so can't remove this power ：On-Die PLL voltage regulator enable AN16 H AN17 VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA AN21 AN26 AN27 +1.05VS_PCH AP21 2 AP23 2 2 1 2 C492 1U_0201_4V6M 2 1 C474 1U_0201_4V6M 1 @ C486 1U_0201_4V6M 1 C496 1U_0201_4V6M 2 C543 10U_0603_6.3V6M 1 AP24 AP26 AT24 AN33 Place Near AN16,AN21,AN33 AN34 +3VS BH29 1 Place Near BH29 2 AP16 @ PAD T14 +1.05VS_VCCAPLL_FDI BG6 VCCTX_LVDS[2] 40mA VCCTX_LVDS[3] 1 C420 C418 10U_0603_6.3V6M 2 VCCTX_LVDS[4] AK36 1 R272 1 LVDS@ 2 0_0402_5% +VCCA_LVDS AK37 R270 0_0402_5% eDP@ AM37 AM38 +1.8VS Place Near AM37 AP36 AP37 R280 0_0402_5% eDP@ +3VS VCCAPLLEXP VCCIO[15] VCCIO[16] PPT:3711mA CPT:3709mA VCC3_3[6] V33 228mA 1 VCC3_3[7] R271 1 LVDS@ 2 0_0402_5% +VCCTX_LVDS VCCIO[28] V34 2 Place Near V33 I/O Buffer Voltage C449 0.1U_0201_10V6K VCCIO[17] PPT:167mA CPT:175mA VCCIO[18] VCCIO[19] PPT:47mA CPT:42mA VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] PCH Power Rail Table VCCVRM[3] AT16 +VCCAFDI_VRM VCCDMI[1] AT20 Trace 20mil AB36 1 VCCVRM[2] VCCFDIPLL VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] C480 1U_0201_4V6M place near AT20 DMI buffer logic Core Well I/O Buffer place near AB36 AG16 +1.8VS VccDFTERM should PH +1.8VS or +3VS AG17 1 AJ16 2 VCCPNAND[4] C477 1U_0201_4V6M 2 2 2mA VCC3_3[3] 1 +1.05VS_PCH VCCIO[25] VCCIO[26] Internal PLL and VRM(+1.5VS) +1.05VS_PCH VCCIO[1] C749 0.1U_0201_10V6K +VCCAFDI_VRM VCCTX_LVDS[1] DMI On-Die PLL Voltage Regulator BJ22 VCCALVDS VSSALVDS NAND / SPI +VCCAPLLEXP T33 @ 1 C419 0.01U_0402_16V7K .1U_0402_16V7K 2 2 1 1mA VCCIO PAD 1 U47 +3VS +1.05VS_PCH AN19 VSSADAC L23 MBK1608221YZF_2P 2 1 Place Near U48 +VCCADAC 2 Place Near AA23 VCCADAC U48 1 2 VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17] +3VS PPT:63mA CPT:1mA 2 1 2 2 1 C505 0.1U_0201_10V6K 2 1 C517 1U_0201_4V6M 1 C519 1U_0201_4V6M 1 C754 10U_0603_6.3V6M PAD-OPEN 4x4m JUMP_43X79 AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31 CRT +1.05VS_PCH LVDS 1 PPT:1700mA CPT:1300mA HVCMOS 2 POWER U37G J3 @ VCC CORE +1.05VS_VCCPP AJ17 Voltage Rail Voltage S0 Iccmax Current(A) V_PROC_IO 1.05 0.001 Processor I/F V5REF 5 0.001 PCH Core Well Reference Voltage V5REF_Sus 5 0.001 Suspend Well Reference Voltag Vcc3_3 3.3 0.266 I/O Buffer Voltage VccADAC 3.3 0.001 Display DAC Analog Power. This power is supplied by the core well. 2 VccADPLLA 1.05 0.08 Display PLL A power C523 0.1U_0201_10V6K VccADPLLB 1.05 0.08 Display PLL B power place near AG16 VccCore 1.05 1.3 Internal Logic Voltage VCCPNAND change to VccDFTERM VccDMI 1.05 0.042 DMI Buffer Voltage VccIO 1.05 2.925 Core Well I/O buffers VccASW 1.05 1.01 1.05 V Supply for Intel R Management Engine and Integrated LAN VccSPI 3.3 0.02 3.3 V Supply for SPI Controller Logic VccDSW 3.3 0.003 3.3v supply for Deep S4/S5 well H VccpNAND 1.8 0.19 1.8V power supply for DF_TVS VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA VccRTC 3.3 6 uA Battery Voltage VccSus3_3 3.3 0.266 Suspend Well I/O Buffer Voltage +3VS AP17 1 AU20 C491 1U_0201_4V6M 3 2 On-Die PLL Voltage Regulator Near AU20 Trace 20mil VCCIO[27] VCCDMI[2] FDI +1.05VS_PCH 10mA VCCSPI V1 For SPI control logi 1 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ 2 C770 1U_0402_6.3V6K 3 ：On-Die PLL voltage regulator enable +VCCAFDI_VRM +1.5VS R394 1 @ 2 0_0402_5% +VCCAFDI_VRM VCCVRM==>1.5V FOR MOBILE VCCVRM==>1.8V FOR DESKTOP VCCVRM = 160mA detal waiting for newest spec 配HDA_SYNC PH(PLL =+1.5VS) 4 3.3 / 1.5 0.01 VccVRM 1.8 / 1.5 0.16 High Definition Audio Controller Suspend Voltage 1.8 V Internal PLL and VRMs (1.8 V for Desktop) VccCLKDMI 1.05 0.02 DMI Clock Buffer Voltage VccSSC 1.05 0.095 Spread Modulators Power Supply VccDIFFCLKN 1.05 0.055 Differential Clock Buffers Power Supply VccALVDS 3.3 0.001 VccTX_LVDS 1.8 0.06 Analog power supply for LVDS (Mobile Only) Analog power supply for LVDS (Mobile Only) 2012/4/6 4 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date VccSusHDA 2013/4/6 Deciphered Date Title PCH (7/9) PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A B C D Thursday, April 12, 2012 Sheet E 19 of 51 Rev 1.0 A B C D E For Deep SX turn off +V5REF_SUS,+VCCSUS3_3 ：On-Die PLL voltage regulator enable BH23 +VCCAPLL_CPY_PCH T32 @ H AL29 +1.05VS_PCH PAD suppied by internal 1.05V VR must NC T9 AL24 +VCCSUS1 @ AA24 C552 22U_0805_6.3V6M 1 C547 22U_0805_6.3V6M 2 2 AA26 AA27 AA29 AA31 AC26 @ 2 C513 1U_0201_4V6M 1 C478 1U_0201_4V6M 2 1 C518 1U_0201_4V6M 1 2 AC27 AC29 AC31 AD29 AD31 Near AA19 W21 W23 Near BD47 W24 W26 W29 W31 +1.05VS_VCCA_B_DPL 2 3 C752 22U_0805_6.3V6M 1 1 2 C429 1U_0201_4V6M L49 10UH_LB2012T100MR_20% W33 Near N16 Near BF47 2 C521 N16 +VCCRTCEXT Y49 +1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL +1.05VS_PCH 2 1 C467 1U_0201_4V6M Place near AF17 PAD 1 +VCCSST 0.1U_0201_10V6K V16 +1.05VM_VCCSUS T17 V19 T10 @ +1.05VS_PCH BJ8 2 1 2 1 2 VCCASW[9] VCCASW[10] VCCASW[11] VCCASW[12] VCCASW[13] VCCASW[14] VCCASW[15] V5REF_SUS 1 V23 Near T23 2 V24 1 C490 0.1U_0201_10V6K 2 Near A22 1 2 C495 0.1U_0201_10V6K 1 C494 0.1U_0201_10V6K 1 VCCSUS3_3[1] 1mA V5REF VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCC3_3[1] VCC3_3[8] VCCASW[16] VCC3_3[4] 1 2 2 1 2 2 C497 0.1U_0201_10V6K Near P24 2 +VCCSUS3_3 P24 +V5REF_SUS +1.05VS_PCH T26 R334 100_0402_5% RB751V-40_SOD323-2 Near M26 M26 +PCH_V5REF_SUS AN23 +VCCA_USBSUS 1 AN24 P34 T11 PAD 2 +3VS +5VS 0.1U_0402_16V4Z @ suppied by internal 1.05V VR Must NC +VCCSUS3_3 D14 +PCH_V5REF_RUN +VCCSUS3_3 1 P20 C470 1U_0603_10V6K C501 0.1U_0201_10V6K 2 2 Near P34 Near N20 P22 2 1 N20 N22 R321 100_0402_5% RB751V-40_SOD323-2 +3VS AA16 1 W16 T34 C771 0.1U_0201_10V6K 2 Place near AJ2 VCCASW[17] 1 1 C522 0.1U_0201_10V6K 2 Place near AA16,W16 C471 0.1U_0201_10V6K 2 Place near T34 VCCASW[18] VCCASW[19] VCC3_3[2] VCCASW[20] DCPRTC VCCVRM[4] VCCIO[13] VCCADPLLB VCCIO[6] VCCAPLLSATA VCCVRM[1] VCCIO[7] VCCIO[8] VCCIO[9] VCCIO[11] 55mA VCCIO[2] VCCIO[3] VCCIO[10] 95mA VCCIO[4] AJ2 +1.05VS_PCH AF13 1 AH13 2 AH14 GPIO28 AF14 AK1 +VCCSATAPLL 3 On-Die PLL Voltage Regulator ：On-Die PLL voltage regulator enable PAD AC16 VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA +VCCAFDI_VRM +1.05VS_PCH AC17 Near AC16 AD17 1 C482 1U_0201_4V6M +1.05VS_PCH 2 DCPSUS[1] DCPSUS[2] 1mA @ T48 H AF11 DCPSST V_PROC_IO Near AH13,AH14,AF13 C533 1U_0201_4V6M VCCASW[22] VCCASW[23] VCCASW[21] T21 V21 T19 +VCCSUS3_3 A22 2 Place near BJ8 T24 C484 DCPSUS[4] 2 T23 +RTCVCC C493 1U_0402_6.3V6K C541 0.1U_0201_10V6K 1 C537 0.1U_0201_10V6K 4 2 C526 Near V16 C544 4.7U_0603_6.3V6K isolation between SSC (AG33) and DIFFCLKN(AF33,AF34,AG34) 18mil width(DIFFCLKN) 10mil (SSC) VCCASW[8] BF47 1 C476 1U_0201_4V6M suppied by internal 1.05V VR Must NC VCCASW[7] CPT:75mA VCCIO[8,9,11] change to VccDIFFCLKN VCCIO[10] change to VccSSC Place near AG33 VCCASW[6] VCCADPLLA PPT:80mA AF17 AF33 AF34 AG34 2 VCCASW[5] BD47 AG33 2 Place near AF33, AF34,AG34 VCCASW[4] VCCIO[12] +VCCAFDI_VRM +1.05VS_PCH 1mA VCCASW[3] VCCRTC 10mA VCCSUSHDA P32 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ Need +3VALW and 0.1U close PCH 1 C473 0.1U_0201_10V6K 4 2 Near P32 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 2012/4/6 2013/4/6 Deciphered Date Title PCH (8/9) PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A B 1 +VCCSUS3_3 D16 VCCIO[34] VCCIO[5] 1 0.1U_0201_10V6K +1.05VS_PCH 1 C524 1U_0201_4V6M VCCASW[2] 903mA SATA 2 2 C426 1U_0201_4V6M 1 C751 22U_0805_6.3V6M 2 VCCSUS3_3[10] MISC +1.05VS_VCCA_A_DPL VCCASW[1] HDA 2 1 VCCSUS3_3[9] PCI/GPIO/LPC AA21 1 1 DCPSUS[3] Clock and Miscellaneous AA19 L54 10UH_LB2012T100MR_20% 1 2 VCCIO[14] VCCSUS3_3[6] +1.05VS_PCH +1.05VS_PCH Deep S3 VCCSUS3_3[7] PPT:126mA CPT:119mA VCCSUS3_3[8] VCCAPLLDMI2 2 1 C820 0.01U_0402_16V7K 2 1 T29 VCC3_3[5] CPU VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA VCCIO[33] Near N26 2 1 1 PAD On-Die PLL Voltage Regulator VCCIO[32] T27 C819 0.01U_0402_16V7K DS3@ 2 GPIO28 DCPSUSBYP <35> PCH_PWR_EN# C468 1U_0201_4V6M 2 2 T38 P28 2 PCH_PWR_EN# 1 R757 1K_0402_5% 1 +3VS_VCC_CLKF33 VCCIO[31] 1 Q64 AP2301GN-HF_SOT23-3 1 V12 3 1 2 +PCH_VCCDSW VCCIO[30] 1mA 1 R756 2 2.2K_0402_5% 2 T12 @ VCCDSW3_3 1 P26 DS3@ 1 T16 USB PAD suppied by internal 1.05V VR must NC VCCIO[29] Q68 AP2301GN-HF_SOT23-3 R752 20K_0402_5% Near T38 VCCACLK 2 Near T16 1 +1.05VS_PCH N26 C816 .1U_0402_16V7K 2 AD49 R755 20K_0402_5% 2 1 C520 0.1U_0201_10V6K 3 POWER U37J 1 Not support Deep S4,S5 connect to +3VALW +V5REF_SUS +5VALW 2 +VCCACLK 0_0402_5% C817 .1U_0402_16V7K +3VS_VCC_CLKF33 1 C440 1U_0402_6.3V6K 1 C465 10U_0603_6.3V6M +3VALW_PCH 10mil +VCCSUS3_3 +3VALW @ R273 1 RTC L26 10UH_LB2012T100MR_20% 1 2 20mil +1.05VS_PCH +1.05V analog internal clock PLL Can NC +3VS C D Thursday, April 12, 2012 Sheet E 20 of 51 Rev 1.0 A B C D E U37I 1 U37H H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3 2 3 VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3 VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28 1 2 3 4 4 COUGARPOINT_FCBGA989~D SA00005AGI0 S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO! HM77@ Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 2013/4/6 Deciphered Date Title PCH (9/9) VSS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A B C D Thursday, April 12, 2012 Sheet E 21 of 51 Rev 1.0 5 4 3 2 1 Panel POWER CIRCUIT +LCDVDD SM010014520 3000ma 220ohm@100mhz DCR 0.04 +3VS +3VALW 2 1 W=60mils R6 10K_0402_5% 1 2 R5 300_0603_5% W=40mils +INVPWR_B+ L1 FBMA-L11-201209-221LMA30T_0805 2 1 2 D D AP2301GN-HF_SOT23-3 2 4 S G S 1 1 2 2 C11 680P_0402_50V7K 2 Q1B DMN66D0LDW-7_SOT363-6 C562 4.7U_0603_6.3V6K 1 1 W=60mils 1 6 C2 .047U_0402_16V7K C7 68P_0402_50V8J Q28 +LCDVDD 1 D 2 <16> PCH_ENVDD D 3 3 1 R2 1K_0402_5% 2 1 5 G Q1A DMN66D0LDW-7_SOT363-6 B+ C479 4.7U_0603_6.3V6K 1 1 2 2 C10 0.1U_0402_16V4Z R4 eDP panel + Card Reader Conn. 2 100K_0402_5% +INVPWR_B+ W=40mils JLVDS1 20mils C 40mils C5 1 DPST_PWM R86 2 1 100P_0201_25V8J PCIE_PTX_C_DRX_P1 PCIE_PTX_C_DRX_N1 <14> PCIE_PTX_C_DRX_P1 <14> PCIE_PTX_C_DRX_N1 PCIE_DTX_C_PRX_P1 PCIE_DTX_C_PRX_N1 <14> PCIE_PRX_DTX_P1 <14> PCIE_PRX_DTX_N1 C8 1 BKOFF# 2 100P_0201_25V8J @ 6 R18 1 2 10K_0402_5% I/O2 3 USB20_P10 CLK_PCIE_CARD CLK_PCIE_CARD# <14> CLK_PCIE_CARD <14> CLK_PCIE_CARD# USB20_P10 USB20_N10 <17> USB20_P10 <17> USB20_N10 +3VS USB20_N10 B D15 I/O4 5 4 VDD GND I/O3 I/O1 2 +3VS PLT_RST# CARD_CLKREQ# <17,24,30,32,5> PLT_RST# <14> CARD_CLKREQ# 2 10K_0402_5% +3VALW ON/OFFBTN# LID_SW# <33> ON/OFFBTN# <32> LID_SW# <16> DPST_PWM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 +3VS BKOFF# DPST_PWM EDP_HPD <32> BKOFF# 1 60mils AZC099-04S.R7G_SOT23-6 <4> EDP_TXP1 <4> EDP_TXN1 <4> EDP_TXP0 <4> EDP_TXN0 <4> EDP_AUXP <4> EDP_AUXN 0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K 0.1U_0201_10V6K 1 1 1 1 1 1 2eDP@ 2eDP@ 2eDP@ 2eDP@ 2eDP@ 2eDP@ +LCDVDD C912 C913 C910 C911 C914 C915 EDP_TXP1_C EDP_TXN1_C EDP_TXP0_C EDP_TXN0_C EDP_AUXP_C EDP_AUXN_C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 C B G1 G2 G3 G4 G5 41 42 43 44 45 ACES_50398-04071-001 CONN@ <4> EDP_HPD# To LED/B Conn. 1 D 2 G EDP_HPD ACES_88058-060N 1 eDP@ Q29 SSM3K7002FU_SC70-3 8 7 3 S eDP@ R480 100K_0402_5% 20mils 2 <32> BATT_BLUE_LED# <32> BATT_AMB_LED# <32> PWR_LED# <32> PWR_SUSP_LED# 6 5 4 3 2 1 +3VALW BATT_BLUE_LED# BATT_AMB_LED# PWR_LED# PWR_SUSP_LED# A GND GND 6 5 4 3 2 1 A JLED1 CONN@ Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 Deciphered Date 2013/4/6 Title LVDS Connector THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: 5 4 3 2 Thursday, April 12, 2012 Sheet 1 22 of 51 Rev 1.0 5 4 3 2 1 W=40mils +HDMI_5V_OUT F1 +5VS 1 2 1 1.1A_6VDC_FUSE 2 D C C345 0.1U_0402_16V4Z D <16> PCH_DPB_N0 <16> PCH_DPB_P0 C280 C281 2 2 1 .1U_0402_16V7K 1 .1U_0402_16V7K HDMI_TX2HDMI_TX2+ <16> PCH_DPB_N1 <16> PCH_DPB_P1 C283 C282 2 2 1 .1U_0402_16V7K 1 .1U_0402_16V7K HDMI_TX1HDMI_TX1+ <16> PCH_DPB_N2 <16> PCH_DPB_P2 C287 C286 2 2 1 .1U_0402_16V7K 1 .1U_0402_16V7K HDMI_TX0HDMI_TX0+ <16> PCH_DPB_N3 <16> PCH_DPB_P3 C285 C284 2 2 1 .1U_0402_16V7K 1 .1U_0402_16V7K HDMI_CLKHDMI_CLK+ +HDMI_5V_OUT C +3VS +3VS 1 2 2.2K_0402_5% SDVO_SCLK R253 1 2 2.2K_0402_5% SDVO_SDATA 2 R250 2 2 680_0402_5% 2 680_0402_5% HDMI_TX1HDMI_TX1+ R583 1 R587 1 2 680_0402_5% 2 680_0402_5% HDMI_TX0HDMI_TX0+ R564 1 R570 1 2 680_0402_5% 2 680_0402_5% HDMI_CLK- R573 1 HDMI_CLK+ R590 1 2 680_0402_5% 2 680_0402_5% HDMI_GND 1 6 6 G Q16A DMN66D0LDW-7_SOT363-6 HDMI_SDATA D SDVO_SDATA S <16> SDVO_SDATA HDMI_SCLK D S 3 1 2 R255 2.2K_0402_5% G 5 1 4 SDVO_SCLK R592 1 R594 1 2 +3VS Q16B DMN66D0LDW-7_SOT363-6 G <16> SDVO_SCLK HDMI_TX2HDMI_TX2+ D Pull high at connector side 1 2 R257 2.2K_0402_5% @ R785 0_0402_5% S 1 Q14B DMN66D0LDW-7_SOT363-6 Place closed to JHDMI1 B B HDMI connector +3VS JHDMI1 HDMI_HPD +HDMI_5V_OUT 1 HDMI_SDATA HDMI_SCLK R198 1M_0402_5% 5 HDMI_CLKG 2 Q14A DMN66D0LDW-7_SOT363-6 3 HDMI_HPD HDMI_CLK+ HDMI_TX0- D 4 1 1 S <16> PCH_DPB_HPD R219 100K_0402_5% HDMI_TX0+ HDMI_TX1- C324 100P_0201_25V8J HDMI_TX1+ HDMI_TX2- 2 2 HDMI_TX2+ 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield CK+ D0D0_shield D0+ D1D1_shield D1+ GND D2GND D2_shield GND D2+ GND 20 21 22 23 CONCR_099AMAC19CBACNF CONN@ A Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date A 2012/4/6 Deciphered Date 2013/4/6 Title HDMI Connector THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev Q3ZMC M/B LA-8481P Schematic 1.0 Date: 5 4 3 2 Thursday, April 12, 2012 Sheet 1 23 of 51 +3VS_LC CRYSTAL_P +3VS_LC +3VS_POC <16> PCH_DPD_P0 <16> PCH_DPD_N0 <16> PCH_DPD_AUXP <16> PCH_DPD_AUXN AA6 AB3 V1 R2 PCH_DPD_P3 PCH_DPD_N3 C1332 TB@2 C1333 TB@2 1 0.1U_0201_10V6K 1 0.1U_0201_10V6K PCH_DPD_P3_C PCH_DPD_N3_C E14 D13 PCH_DPD_P2 PCH_DPD_N2 C1334 TB@2 C1335 TB@2 1 0.1U_0201_10V6K 1 0.1U_0201_10V6K PCH_DPD_P2_C PCH_DPD_N2_C E16 D15 PCH_DPD_P1 PCH_DPD_N1 C1336 TB@2 C1337 TB@2 1 0.1U_0201_10V6K 1 0.1U_0201_10V6K PCH_DPD_P1_C PCH_DPD_N1_C E18 D17 PCH_DPD_P0 PCH_DPD_N0 C1339 TB@2 C1341 TB@2 1 0.1U_0201_10V6K 1 0.1U_0201_10V6K PCH_DPD_P0_C PCH_DPD_N0_C E20 D19 PCH_DPD_AUXP PCH_DPD_AUXN C1342 TB@2 C1343 TB@2 1 0.1U_0201_10V6K 1 0.1U_0201_10V6K PCH_DPD_AUXP_C PCH_DPD_AUXN_C A6 B5 DPD_HPD U6 <16> DPD_HPD TO PCH TB@ R1049 100K_0402_5% E6 D5 E8 D7 E10 D9 E12 D11 A4 B3 T75PAD <14> PCIE_PRX_DTX_P5 <14> PCIE_PRX_DTX_N5 <14> PCIE_PRX_DTX_P6 <14> PCIE_PRX_DTX_N6 <14> PCIE_PRX_DTX_P7 <14> PCIE_PRX_DTX_N7 <14> PCIE_PRX_DTX_P8 <14> PCIE_PRX_DTX_N8 @ DPSNK1_HPD T5 PCIE_PRX_DTX_P5 PCIE_PRX_DTX_N5 C1345 TB@2 C1346 TB@2 1 0.1U_0201_10V6K 1 0.1U_0201_10V6K PCIE_PRX_C_DTX_P5 PCIE_PRX_C_DTX_N5 AD5 AD7 PCIE_PRX_DTX_P6 PCIE_PRX_DTX_N6 C1347 TB@2 C1348 TB@2 1 0.1U_0201_10V6K 1 0.1U_0201_10V6K PCIE_PRX_C_DTX_P6 PCIE_PRX_C_DTX_N6 AD9 AD11 PCIE_PRX_DTX_P7 PCIE_PRX_DTX_N7 C1349 TB@2 C1350 TB@2 1 0.1U_0201_10V6K 1 0.1U_0201_10V6K PCIE_PRX_C_DTX_P7 PCIE_PRX_C_DTX_N7 AD13 AD15 PCIE_PRX_DTX_P8 PCIE_PRX_DTX_N8 C1351 TB@2 C1352 TB@2 1 0.1U_0201_10V6K 1 0.1U_0201_10V6K PCIE_PRX_C_DTX_P8 PCIE_PRX_C_DTX_N8 AD17 AD19 <17,22,30,32,5> PLT_RST# R1046 R1047 2 2.2K_0402_5% 2 2.2K_0402_5% 1 R1052 TB@ 2 PERST# 0_0402_5% R6 TMU_CLK_OUT TMU_CLK_IN MISC GPIO_0__PA_HV_EN__BYP0 GPIO_1__PB_HV_EN__BYP0 TEST_EN GPIO_2__GO2SX TEST_PWR_GOOD GPIO_3 GPIO_4_WAKE_OD_N RSENSE GPIO_5_CIO_PLUG_EVENT RBIAS GPIO_6_OD__CIO_SDA_OD GPIO_7_OD__CIO_SCL_OD XTAL_25_IN GPIO__8_EN_CIO_PWR_N_OD XTAL_25_OUT GPIO_9__OK2GO2SX_N_OD GPIO_10__PA_CIO_SEL__BYP1 TCK GPIO_11__PB_CIO_SEL__BYP1 TMS GPIO_12__PA_DP_PWRDN__BYP2 TDI GPIO_13__PB_DP_PWRDN__BYP2 TDO GPIO_14 GPIO_15 THERMDA PWR_ON_POC_RSTN NC EN_LC_PWR DPSNK0_3_P DPSNK0_3_N DPSRC_3_P DPSRC_3_N DPSNK0_2_P DPSNK0_2_N DPSRC_2_P DPSRC_2_N DPSNK0_1_P DPSNK0_1_N DPSRC_1_P DPSRC_1_N DPSNK0_0_P DPSNK0_0_N DPSNK0_AUX_P DPSNK0_AUX_N DPSNK0_HPD DPSNK1_3_P DPSNK1_3_N DPSNK1_2_P DPSNK1_2_N DPSNK1_1_P DPSNK1_1_N DPSNK1_0_P DPSNK1_0_N DPSNK1_AUX_P DPSNK1_AUX_N DPSRC_0_P DPSRC_0_N DPSRC_AUX_P DPSRC_AUX_N DPSRC_HPD_OD @ @ @ @ PAD T76 PAD T77 PAD T78 PAD T79 R1033 2 TB@ 1 10K_0402_5% 2 TB@ 1 10K_0402_5% +3VS_POC AA4 Y3 TMU_CLK_IN G2 M1 Y1 W2 J4 AA2 AB1 AC2 P3 M5 M3 L2 H3 L4 T3 V5 J2 K5 PA_HV_EN TB_GPIO1 TB_GO2SX TB_FORCE_PWR_R TB_WAKE# CIO_PLUG_EVENT TB_SMB_DA TB_SMB_CK EN_CIO_PWR# TB_OK2GO2SX# PA_CIO_SEL TB_GPIO11 PA_DP_PWRDN TB_GPIO13 TB_GPIO14 TB_GPIO15 TB_PWRON_POC_RST# EN_LC_PWR PA_HV_EN <45> TB_GO2SX <32> R1097 2 TB@ 1 0_0402_5% R1039 2 TB@ 1 0_0402_5% TB_FORCE_PWR <18> PCH_PCIE_WAKE# <15,28> EN_CIO_PWR# <27> TB_OK2GO2SX# <32> PA_CIO_SEL <25> EN_CIO_PWR# TB_OK2GO2SX# PA_DP_PWRDN TB_GPIO13 R1034 R1029 R1035 R1028 2 2 2 2 PA_HV_EN TB_GPIO1 R1040 R1027 2 TB@ 2 TB@ 1 1K_0402_5% 1 10K_0402_5% TB_FORCE_PWR_R R1041 2 TB@ 1 10K_0402_5% TB_GPIO11 TB_GPIO14 TB_GPIO15 EN_LC_PWR PA_DP_PWRDN <25> TB_PWRON_POC_RST# <32> EN_LC_PWR <42> R1042 R1043 R1044 R1045 2 2 2 1 TB@ TB@ TB@ TB@ TB@ TB@ TB@ TB@ 1 1 1 1 1 1 1 2 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 100K_0402_5% EC control~~ trig after SUSP# asserted for 30ms A14 B15 A12 B13 TB_SMB_CK R1129 2 TB@ 1 0_0402_5% TB_SMB_DA R1128 2 TB@ 1 0_0402_5% TB_SMB_CK_GPIO7 <18> TB_SMB_DA_GPIO6 <14> A10 B11 A8 B9 TB_SMB_CK R1131 2 @ 1 0_0402_5% TB_SMB_DA R1130 2 @ 1 0_0402_5% EC_SMB_CK2 <11,14,32> EC_SMB_DA2 <11,14,32> C2 D3 V3 +3VS_POC TB@ R1050 10K_0402_5% TB@ R1051 10K_0402_5% EN_CIO_PWR# 5 +3VS_POC TB@ C1344 2 1 0.1U_0402_16V4Z U67 2 B CIO_PLUG_EVENT 1 A TB@ Q89A DMN66D0LDW-7_SOT363-6 TB@ 4 Y TB_PLUG_EVENT TB_PLUG_EVENT <18> MC74VHC1G08DFT2G_SC70-5 DPSNK1_HPD PETP_0 PETN_0 PETP_1 PETN_1 PETP_2 PETN_2 PERP_0 PERN_0 PERP_1 PERN_1 PCIe PETP_3 PETN_3 PERST_N PERP_2 PERN_2 PERP_3 PERN_3 REFCLK_100_IN_P REFCLK_100_IN_N AB9 AA10 PCIE_PTX_C_DRX_P5 PCIE_PTX_C_DRX_N5 AA12 AB13 PCIE_PTX_C_DRX_P6 PCIE_PTX_C_DRX_N6 AB15 AA16 PCIE_PTX_C_DRX_P7 PCIE_PTX_C_DRX_N7 AA18 AB19 PCIE_PTX_C_DRX_P8 PCIE_PTX_C_DRX_N8 AB21 AD21 CLK_TB_REFCLK CLK_TB_REFCLK# PCIE_PTX_C_DRX_P5 <14> PCIE_PTX_C_DRX_N5 <14> +3VS_LC PCIE_PTX_C_DRX_P6 <14> PCIE_PTX_C_DRX_N6 <14> PCIE_PTX_C_DRX_P7 <14> PCIE_PTX_C_DRX_N7 <14> PCIE_PTX_C_DRX_P8 <14> PCIE_PTX_C_DRX_N8 <14> TB_CLKREQ#_R TB@ 1 6 TB_CLKREQ# TB_CLKREQ# <14> D CR_JTCK CR_JTMS CR_JTDI CR_TDO R1019 R1020 R1021 R1022 EE_DI EE_DO EE_CS_N EE_CLK PCIE_RST_0_N PCIE_RST_1_N PCIE_RST_2_N PCIE_RST_3_N TB_CLKREQ#_R 5 2 2 2 2 AA24 AB23 MONOBS_P MONOBS_N N6 T1 Y5 U2 W6 P CRYSTAL_P CRYSTAL_N U20 W20 Y7 U4 <16> PCH_DPD_P1 <16> PCH_DPD_N1 2 2.2K_0402_5% 2 2.2K_0402_5% 1 TB@ 1 TB@ G R4 P5 AD3 W4 PCIe_RST_0_N PCIe_RST_1_N PCIe_RST_2_N PCIe_RST_3_N PCIE_CLKREQ_OD_N 3 2 1K_0402_1% +3VS_LC <16> PCH_DPD_P2 <16> PCH_DPD_N2 1 @ 1 @ TB_CLKREQ#_R R1031 TMU_CLK_IN MONDC0 MONDC1 2 EE_DI EE_DO EE_CS_N 1 EE_CLK_R 0_0402_5% R1032 1 TB@ <16> PCH_DPD_P3 <16> PCH_DPD_N3 R1036 R1037 G AD23 AC24 N4 AB5 TB@ TB@ TB@ TB@ TB_SMB_DA TB_SMB_CK +3VS_LC 1 R1038 1 1 1 1 TB_SMB_DA TB_SMB_CK U66A 2 2 TB@ EE_CLK 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% R1048 1 10K_0402_5% 3 2 1 2 1 10K_0402_5% intra pair skew: 5 mil. inter pair skew: 10 mil W18 W16 ATMEL: AT25512(64KB):SA000055T00 AT25256B(32KB):SA00005G500 CAT:CAT25256VI-GT3(32KB):SA00005DB00 @ 2 TB@ 4 1 TB@ C1340 2 2 1 AT25512N-SH-T_SO8 SA00005G500 GND 4 Y2 TB@ SOURCE PORT 0 2 GND RECEIVE 1 Display Port TB@ C1338 SINK PORT 0 TB@ SINK PORT 1 TB@ TB@ EE_CS_N EE_DO R1026 3.3K_0402_5% 2 1 R1025 3.3K_0402_5% 2 1 R1024 3.3K_0402_5% 2 1 R1023 3.3K_0402_5% 2 1 1 2 3 4 2 1 C1330 CS# SO WP# GND 2 1 1 INTEL Recommend 32K EEPROM 1 0.01U_0402_16V7K @ VCC HOLD# SCK SI 3 TRANSMIT 2 @ R1018 0_0402_5% 8 7 6 5 25MHZ_10PF_7V25000014 3 R1066 G EE_CLK EE_DI TB_GO2SX S TB@ 2 1M_0402_5% 6.8P_0402_50V8C 2 TB@ U65 TB@ 1 R1101 D 1 6.8P_0402_50V8C C1331 0.1U_0402_16V4Z CRYSTAL_N TB@ S +3VS_LC Q89B DMN66D0LDW-7_SOT363-6 CLK_TB_REFCLK <14> CLK_TB_REFCLK# <14> R1053 2 1 @ 0_0402_5% CACTUS-RIDGE_FCBGA288 TB@ SA00005QT20 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 Deciphered Date 2013/4/6 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Intel Thunderbolt(1/4) Q3ZMC M/B LA-8481P Schematic Date: Thursday, April 12, 2012 Sheet 24 of 51 Rev 1.0 PCH_DPD_CLK PCH_DPD_CLK +3VS_POC <16> 5 2 S 6 1 G D S 4 1 Q82B DMN66D0LDW-7_SOT363-6 D S 2 5 2 5 G D S D TB@ 6 TB@ R1124 1K_0402_5% 4 2 Q92B TB@ NTGD4161PT1G_TSOP6~D 1 3 3 1 G Q92A NTGD4161PT1G_TSOP6~D 1 G Q91B TB@ NTGD4161PT1G_TSOP6~D D TB@ Q32 SSM3K7002FU_SC70-3 2 G PA_CFG1_LSEO0 3 S A16 B17 PA_AUX_P_C PA_AUX_N_C C1361 TB@1 TB@ C1354 TB@1 TB@ 2 0.22U_0402_10V6K 2 0.22U_0402_10V6K PA_AUX_P PA_AUX_N F3 F1 PA_DPSRC_HPD H1 @ 2 1 TB@ 2 DPA_AUX_N R1059 100K_0402_5% 5 G 1 TB@ 2 PA_LSTX_LSEO1_R R1061 10K_0402_5% TB@ R1116 10K_0402_5% TB@ Q86A DMN66D0LDW-7_SOT363-6 6 4 S G S 2 PA_LSRX_LSOE1_U 1M_0402_5% 2 TB@ DPA_AUX_P 100K_0402_5% 2 TB@ DPA_AUX_HPD 10K_0402_5% 2 TB_CIO_TX_P0 TB@ 470K_0402_5% 2 TB@ TB_CIO_TX_N0 470K_0402_5% 2 TB@ TB_CIO_TX_P1 470K_0402_5% 2 TB@ TB_CIO_TX_N1 470K_0402_5% 1 TB@ C1355 TB@1 TB@ C1362 TB@1 TB@ 2 0.22U_0402_10V6K 2 0.22U_0402_10V6K TB_CIO_TX_P0_C TB_CIO_TX_N0_C G24 E24 TB_CIO_RX_P0_C TB_CIO_RX_N0_C C1363 TB@1 TB@ C1356 TB@1 TB@ 2 0.22U_0402_10V6K 2 0.22U_0402_10V6K TB_CIO_RX_P0 TB_CIO_RX_N0 G22 E22 K1 G4 TB_CIO_TX_P1 TB_CIO_TX_N1 C1357 TB@1 TB@ C1364 TB@1 TB@ 2 0.22U_0402_10V6K 2 0.22U_0402_10V6K TB_CIO_TX_P1_C TB_CIO_TX_N1_C L24 J24 TB_CIO_RX_P1_C TB_CIO_RX_N1_C C1365 TB@1 TB@ C1366 TB@1 TB@ 2 0.22U_0402_10V6K 2 0.22U_0402_10V6K TB_CIO_RX_P1 TB_CIO_RX_N1 L22 J22 TB@ Q86B DMN66D0LDW-7_SOT363-6 U3 1 TB@ 2 1 R1075 100K_0402_5% TB@ +3VS_POC OE# C1374 IN CFG2 LSrx Mode N2 J6 PA_LSTX_LSEO1 PA_LSRX_LSOE1 TB@ 2 1 0.1U_0201_10V6K PA_DPSRC_1_P PA_DPSRC_1_N PA_AUX_P PA_AUX_N PB_DPSRC_1_P PB_DPSRC_1_N PB_AUX_P PB_AUX_N PA_DPSRC_HPD PB_DPSRC_HPD PA_CIO0_TX_P__DPSRC_0_P PA_CIO0_TX_N__DPSRC_0_N PB_CIO2_TX_P__DPSRC_0_P PB_CIO2_TX_N__DPSRC_0_N PA_CIO0_RX_P PA_CIO0_RX_N PA_CONFIG1__CIO_0_LSEO PA_CONFIG2__CIO_0_LSOE PB_CIO2_RX_P PB_CIO2_RX_N PB_CONFIG1__CIO_2_LSEO PB_CONFIG2__CIO_2_LSOE PA_CIO1_TX_P__DPSRC_2_P PA_CIO1_TX_N__DPSRC_2_N PB_CIO3_TX_P__DPSRC_2_P PB_CIO3_TX_N__DPSRC_2_N PA_CIO1_RX_P PA_CIO1_RX_N PA_LSTX__CIO_1_LSEO PA_LSRX__CIO_1_LSOE PB_CIO3_RX_P PB_CIO3_RX_N PB_LSTX__CIO_3_LSEO PB_LSRX__CIO_3_LSOE A22 B23 A20 B21 D1 E2 K3 R24 N24 R22 N22 P1 H5 W24 U24 W22 U22 L6 G6 CACTUS-RIDGE_FCBGA288 TB@ SA00005QT20 Comments All Thunderbolt TX traces have pi filter when embedded capacitors before and after inductor should be 0.45pF 1 0 0 X DP 1 1 X X HDMI 0 0 1 0 TBT TBT cable but no TBT link 0 0 1 1 TBT TBT mode 0 X 0 X None Cable is disconnected @ PAD T80 TB@ TB@ TB@ TB@ Route Thunderbolt traces as 85 Ohm control impedance. Match inside pair 2 mil.Match between lanes NA Thunderbolt lenght must be between 0.8 inch to 2 inch 4 OUT 3 CFG1 2 0_0402_5% 2 0_0402_5% 5 VCC 2 R1058 1 TB@ R1060 1 TB@ PA_LSTX_LSEO1_R PA_LSRX_LSOE1_R HPD PA_LSRX_LSOE1_U PA_CFG1_LSEO0 PA_CFG2_LSOE0 D MDP_HPD 2 TB_CIO_TX_P0 TB_CIO_TX_N0 PA_DPSRC_HPD 3 2 2 +3VS_POC 1 +3VS_POC TB@ PB_DPSRC_3_P PB_DPSRC_3_N R1065 10K_0402_5% 1 2 PA_DPSRC_1P PA_DPSRC_1N R1064 10K_0402_5% 1 2 2 0.22U_0402_10V6K 2 0.22U_0402_10V6K R1063 10K_0402_5% 1 2 C1359 TB@1 TB@ C1360 TB@1 TB@ R1062 10K_0402_5% 1 2 PA_DPSRC_1P_C PA_DPSRC_1N_C PA_DPSRC_3_P PA_DPSRC_3_N PORT2 A18 B19 PORT3 PA_DPSRC_3P PA_DPSRC_3N DPSRC Port A TB@ 2 0.22U_0402_10V6K 2 0.22U_0402_10V6K DPSRC Port B TB@ C1353 TB@1 TB@ C1358 TB@1 TB@ PORT0 1 @ PA_DPSRC_3P_C PA_DPSRC_3N_C PORT1 PI3VEDP212ZLEX_TQFN32_6X3~D TB@ U66B R1057 49.9_0402_1% 1 2 21 28 33 TB@ R1115 10K_0402_5% 1 R1067 1 R1068 1 R1069 1 R1070 1 R1071 1 R1072 1 R1073 2 TB@ 3 Q82A DMN66D0LDW-7_SOT363-6 15 14 13 R1056 49.9_0402_1% 1 2 GND GND GPAD TB@ Q91A NTGD4161PT1G_TSOP6~D R1055 1K_0402_5% 1 2 AUX+B AUX-B HPD_B 5 4 PA_AUX_P_C <16> TB@ 1 TB@ C1372 0.1U_0201_10V6K C1373 0.1U_0201_10V6K 2 SEL HPD_SEL AUX_SEL D0+B D0-B PA_LSTX_LSEO1_R PA_LSRX_LSOE1_U PCH_DPD_DAT DMN66D0LDW-7_SOT363-6 6 R1054 1K_0402_5% 1 2 C1370 0.1U_0201_10V6K C1369 0.1U_0201_10V6K C1368 0.1U_0201_10V6K C1367 0.1U_0201_10V6K C1371 0.1U_0201_10V6K 1 10 11 32 25 24 23 22 DMN66D0LDW-7_SOT363-6 D 2 PA_DP_PWRDN AUX+ AUXHPD D0+B D0-B D1+B D1-B PCH_DPD_DAT D TB@ 1 6 7 8 PA_CIO_SEL <24> PA_CIO_SEL +3VS_POC DPA_AUX_P DPA_AUX_N DPA_AUX_HPD D0+ D0D1+ D1- 1 Q81B G <24> PA_DP_PWRDN 1 2 4 5 TB@ 6 S 2 TB@ PA_SRC_3P PA_SRC_3N PA_LSTX_SRC_1P PA_LSRX_SRC_1N PA_AUX_P_C PA_AUX_N_C TB@ 3 Q81A S 2 TB@ 1 19 18 17 4 PA_AUX_N_C D 2 TB@ 1 PA_DPSRC_3P_C PA_DPSRC_3N_C PA_DPSRC_1P_C PA_DPSRC_1N_C G 2 TB@ 1 AUX+A AUX-A HPD_A 31 30 27 26 S 1 D0+A D0-A D1+A D1-A D +3VS_POC VDD VDD VDD VDD VDD VDD G 3 9 12 16 20 29 PA_CFG1_LSEO0 S H D L Port B is active U68 G Port A is active PA_CFG1_LSEO0 +3VS_POC CIO SEL/HPD_SEL /AUX_SEL Function GND PA_LSRX_LSOE1_R D42 TB_CIO_RX_P0_C 1 1 74AHC1G125GW_SOT353-5 10 9 TB_CIO_RX_P0_C PA_LSTX_SRC_1P D43 1 1 10 9 PA_LSTX_SRC_1P TB_CIO_TX_P1 D44 1 1 10 9 TB_CIO_TX_P1 9 8 TB_CIO_RX_N0_C PA_LSRX_SRC_1N 2 2 9 8 PA_LSRX_SRC_1N TB_CIO_TX_N1 2 2 9 8 TB_CIO_TX_N1 @ @ @ PA_CIO_SEL TB@ D47 BAR90-02LRH_TSLP-2-7-2 2 1 AUX_CHP 2 1 AUX_CHN 1 S 2 G <32> TB_LED 4 4 7 7 AUX_CHP TB_CIO_TX_N0 5 5 6 6 TB_CIO_TX_N0 PA_SRC_3N 5 5 6 6 PA_SRC_3N AUX_CHN 5 5 6 6 AUX_CHN 1 TB@ 1 2 C1387 330P_0402_50V7K TB@ C1386 330P_0402_50V7K R1091 1M_0402_5% 1 2 R1090 1M_0402_5% 1 2 TB@ EN HV_EN OUT 0 0 0V 0 1 0V 1 0 3.3V 1 1 12V ISET_V3P3 ISET_S3 ISET_S0 RSVD RSVD 18 15 16 +VCC3V3_PA @ T73 PAD TB@ 1 2 TB@ 1 2 1 @ 1 2 TB@ TB@ 40mil 2 TB@ TPS22980RGPR_VQFN20_4X4 HPD LANE0_P CONFIG1 LANE0_N CONFIG2 GND GND LANE1_P LANE3_P LANE1_N LANE3_N GND GND LANE2_P AUX_CHP LANE2_N AUX_CHN RETURN DP_PWR 21 22 23 24 TB@ R1088 0_0402_5% 1 GND GND V3P3OUT L66 OUT OUT +VCC_DP TB@ L65 1 2 FBMA-L11-201209-221LMA30T_0805 2 EN HV_EN S0 12 14 2 0_0402_5% 2 R1079 100K_0402_5% 1 2 C1003 0.1U_0402_16V4Z 6 7 +VCC_DP_L BLM31PG500SN1L 1206 Current limited: Ilim = 40Kohm/Rset 8 9 10 2 TB@ R1086 2 1 0_0402_5% 2 36.5K_0402_1% 2 35.7K_0402_1% 2 35.7K_0402_1% 1 40mil C1005 0.1U_0402_16V4Z R1112 1 TB@ R1110 1 TB@ R1111 1 TB@ 5 11 17 TB@ 2 C1004 0.1U_0402_16V4Z +3VS_POC R1084 1 TB@ 2 10K_0402_5% HV_EN 2 0_0402_5% Q85 BC846B_SOT23-3 TB@ PA_CFG1_LSEO0, PA_CFG2_LSOE0 should be used by GPU as the DP CONFIG1/CONFIG2 inputs, if required TB@ VHV VHV 1 2 2 +3VS_POC R1074 1 TB@ 3 2 2 U2 2 TB@ 1 TB@ C1417 0.01U_0402_16V7K TB@ 2 PA_CFG1_LSEO0_A PA_CFG2_LSOE0 Q88B DMN66D0LDW-7_SOT363-6 1 HV_EN 2 1 TPad TB@ R1113 10K_0402_5% 2 TB@ TB@ R712 10K_0402_5% + 1 21 TB@ 1 1 2 3 4 13 1 40mil +HV_12V C1378 0.01U_0402_50V7K MDP_HPD 60mil +3VS_POC 19 20 D0-B V3P3 V3P3 2 G 1 +HV_12V R1114 2.05K_0402_1% 1 2 1 TB@ R1087 1K_0402_5% 1 2 R1085 1K_0402_5% 1 2 2 Q84 TB@ BC846B_SOT23-3 1 2 3 C1376 0.01U_0402_50V7K 1 2 1 TB@ 2 mDP_HPD_R 2 R1078 1 TB@ 3 0_0402_5% TB_CIO_TX_P0 4 TB_CIO_RX_P0_C 5 TB_CIO_TX_N0 6 TB_CIO_RX_N0_C C1377 0_0402_5% 2 1 2 0.01U_0402_50V7K 7 R1089 1 TB@ 2 8 R1080 1 TB@ TB@ 9 0_0402_5% PA_LSTX_SRC_1P 10 PA_SRC_3P 11 PA_LSRX_SRC_1N 12 PA_SRC_3N 2 0_0402_5% 13 R1081 1 TB@ 2 0_0402_5% 14 R1082 1 TB@ 15 TB_CIO_TX_P1 16 AUX_CHP 17 TB_CIO_TX_N1 18 AUX_CHN 40mil 19 RETURN 20 +VCC_DP D S TB@ R711 10K_0402_5% TB@ 8 L05ESDL5V0NA-4 SLP2510P8 1 LEGO@ Q31 SSM3K7002FU_SC70-3 TB@ C1380 30P_0402_50V8J R1126 10K_0402_5% TB@ TB@ 5 Q88A DMN66D0LDW-7_SOT363-6 8 L05ESDL5V0NA-4 SLP2510P8 JTB1 GND GND GND GND GND 2 3 3 R1083 1 TB@ C1001 0.1U_0402_16V4Z 2 3 3 LEGO@ R1125 10K_0402_5% C1000 150U_B2_6.3VM_R35M 1 TB_CIO_RX_P0_C TB_CIO_RX_N0_C 2 AUX_CHP 1 2 1 +3VS_POC 1 PA_SRC_3P 8 +3VS_POC 6 7 7 3 3 3 TB@ C1379 30P_0402_50V8J G D S 1 4 4 +3VS_POC Pull High +3VS at PCH side <32> TB_EJECT_BTN 3 PA_SRC_3P 1 1 DPA_AUX_N DPA_AUX_P G D S 4 TB_CIO_TX_P0 L05ESDL5V0NA-4 SLP2510P8 TB@ L64 650NH +-5% LQW18CNR65J00D 2 TB@ L63 650NH +-5% LQW18CNR65J00D PA_CFG1_LSEO0 7 7 LEGO@ Q30 SSM3K7002FU_SC70-3 TB@ BAR90-02LRH_TSLP-2-7-2 D46 R1127 10K_0402_5% TB@ 4 4 2 TB@ TB_CIO_TX_P0 D0+B D 3 TB@ TB_CIO_RX_P1_C TB_CIO_RX_N1_C R1077 1.5K_0402_5% 2 1 R1076 1.5K_0402_5% 2 1 TB_CIO_RX_N0_C 2 2 JAE_SP11-11986-T01 TB@ C1381 0.01U_0402_50V7K VCC_DP@3V , max current 500mA VCC_DP@12V, max current 0.8A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 Deciphered Date 2013/4/6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Intel Thunderbolt(2/4) Size Document Number Custom Rev 1.0 Q3ZMC M/B LA-8481P Schematic Date: Thursday, April 12, 2012 Sheet 25 of 51 +1.05VS_LC +1.05VS_CIO C1443 0.1U_0201_10V6K TB@ 2 1 2 TB@ 2 CACTUS-RIDGE_FCBGA288 TB@ SA00005QT20 2 2 TB@ 1 2 TB@ 1 2 C1413 0.01U_0201_10V7K 2 1 C1412 0.01U_0201_10V7K TB@ C1409 0.1U_0201_10V6K C1408 0.1U_0201_10V6K C1407 0.1U_0201_10V6K C1406 0.1U_0201_10V6K 1 TB@ 1 2 +3VS_LC M7 P7 T7 L18 N18 R18 H11 H13 H15 H17 H7 K7 TB@ 1 2 TB@ 1 TB@ 2 1 2 TB@ 1 2 TB@ 2 1 +3VS_POC TB@ 1 2 TB@ C1433 1000P_0201_16V7K 1 VCC3P3 VCC3P3 VCC3P3 VCC3P3_CIO VCC3P3_CIO VCC3P3_CIO VCC3P3_DP VCC3P3_DP VCC3P3_DP VCC3P3_DP VCC3P3_DPAUX VCC3P3_POC 1 C1428 0.01U_0201_10V7K 2 VCC C1398 1000P_0201_16V7K TB@ 1 TB@ C1427 0.1U_0201_10V6K 1 TB@ 1 W10 V11 U10 T11 R14 R10 P15 P11 N14 N10 M15 M11 L14 L10 K15 K11 C1425 .1U_0402_16V7K 2 C1416 0.01U_0201_10V7K 1 2 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 C1424 .1U_0402_16V7K TB@ 1 TB@ VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_ON VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_DPAUX VCC1P0_DPAUX C1445 0.1U_0201_10V6K C1434 0.1U_0201_10V6K TB@ 2 C1435 0.1U_0201_10V6K C1415 0.01U_0201_10V7K TB@ C1444 0.1U_0201_10V6K C1397 1000P_0201_16V7K U66C J8 J10 J12 J14 J16 K17 T15 U14 V7 W8 G10 G12 G14 G16 G18 H19 K19 M19 P19 T19 V15 V19 W12 W14 G8 H9 1 2 U66D A2 A24 B1 B7 C4 C6 C8 C10 C12 C14 C16 C18 C20 C22 C24 D21 D23 E4 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 G20 H21 H23 J18 J20 K21 K23 L20 M21 M23 N20 P21 P23 R20 T21 T23 U18 V13 V17 V21 V23 Y9 VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE GND K9 K13 L8 L12 L16 M9 M13 M17 N8 N12 N16 P9 P13 P17 R8 R12 R16 T9 T13 T17 U8 U12 U16 V9 AD1 Y11 Y13 Y15 Y17 Y19 Y21 Y23 AA8 AA14 AA20 AA22 AB7 AB11 AB17 AC4 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 CACTUS-RIDGE_FCBGA288 TB@ SA00005QT20 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 Deciphered Date 2013/4/6 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Intel Thunderbolt(3/4) Q3ZMC M/B LA-8481P Schematic Date: Thursday, April 12, 2012 Sheet 26 of 51 Rev 1.0 1 2 +3VS_LC 2 2 TB@ C1447 1U_0402_6.3V6K +3VS 1 2 1 JUMP_43X79 +3VS_POC 3VS_LC_GATE 1 2 TB@ R1094 220_0402_5% 2 1 1 JUMP_43X79 VCC3V3POC, IC CONN max current 500mA , VCC3V3POC, DP CONN max current 500mA , VCC3V3POC to VCC3V3 max current 350mA , 1.05VS_CIO_CHG 2 TB@ R1093 220_0402_5% 1.05LC_CHG TB@ 1 R1096 TB@ R1092 220_0402_5% 3VS_LC_CHG EN_3VLC_PWR# +1.05VS_CIO J4 2 TB@ R1095 100K_0402_5% +1.05VS_LC J2 1 1 +3VS_POC +3VALW 2 TB@ C1446 1U_0402_6.3V6K +3VS_LC 1 2 +5VALW 60mil 1 3 40mil 2 TB@ Q70 AP2301GN-HF_SOT23-3 +3VS_POC Discharge circuit +3VALW to +3VS_POC VCC3V3_LC max current 350mA 1 40mil 2 +3VS_POC to +3VS_LC 6 S EN_CIO_PWR# TB@ Q72 SSM3K7002FU_SC70-3 2 1 1 S D G S 1 D TB@ Q75B DMN66D0LDW-7_SOT363-6 +1.05VS_LC to +1.05VS_CIO VCC1V05_LC, max current 750mA 80mil VCC1V05_CIO, max current 1.5A 80mil +1.05VS_LC 4 2 2 2 2 2 10U_0603_6.3V6M 1 10U_0603_6.3V6M TB@ C1452 +VSB C1453 +1.05VS_CIO TB@ U74 SI7716ADN-T1-GE3_POWERPAK8-5 1 2 5 3 TB@ 1 TB@ 1 Rds=2.6mΩ(Typ) 3.2mΩ(Max) C1454 0.1U_0402_16V4Z _VCC1V05_LC,max current 750mA _VCC1V05_CIO,max current 1.5A _VCC3V3POC,max current 5mA _VCC3V3_LC,max current 350mA _VCC_DP@3V,max current 500mA _VCC_DP@12V,max current 0.8A in the case of 12V min power should be 10W EN_3VLC_PWR# 2 TB@ Q71B G DMN66D0LDW-7_SOT363-6 3 6 G 2 EN_3VLC_PWR# 2 D 4 1 TB@ C1448 .1U_0603_25V7K G 5 S <42> 1.05VS_LC_PG D 3 100K_0402_5% TB@ Q71A DMN66D0LDW-7_SOT363-6 TB@ R1099 100K_0402_5% 1 1 TB@ R1100 10K_0402_5% 5 D G EN_CIO_PWR# <24> EN_CIO_PWR# S 4 TB@ Q75A DMN66D0LDW-7_SOT363-6 @ R1109 1M_0402_5% 2 3 1 1.05CIO_GATE 1 TB@ C1456 .1U_0603_25V7K 2 V TB_PWRON_POC_RST# TB_PWRON_POC_RST# T2 A4 S2 Q70, +3VS_LC PU11, +1.05VS_LC U74, +1.05VS_CIO H1 PA_HV_EN PA_DP_PWRDN PA_CIO_SEL 1=TB 0=DP PU16, PQ47 VV +1.05VS_LC EN_CIO_PWR# CACTUS RIDGE V U68 S4 V U66 A3 V A2 T1? 1.05VS_LC_PG EN_LC_PWR V +3VS_POC V A1 +3VS_POC S1 +12VS_TB TB_GO2SX PCH TB_PLUG_EVENT S3 EC TB_OK2GO2SX# V +3VS_LC V V PCH_PCIE_WAKE# Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 Deciphered Date 2013/4/6 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Intel Thunderbolt(4/4) Q3ZMC M/B LA-8481P Schematic Date: Thursday, April 12, 2012 Sheet 27 of 51 Rev 1.0 5 4 3 2 1 For Wireless LAN 60mil +3VS +3VS_W LAN Mini Card Power Rating +3VS_W LAN U1 +3VS_W LAN J10 1 2 1 JUMP_43X79 @ D C403 4.7U_0805_10V4Z 2 1 C735 0.1U_0201_10V6K 2 1 +3VS_W LAN C387 0.1U_0201_10V6K 2 3 1 40mil(1A) G9 G10 <17> USB20_P8 <17> USB20_N8 Q47 AP2301GN-HF_SOT23-3 <17> PLT_RST_BUF# <15,24> PCH_PCIE_W AKE# <32> EC_PME# R702 1 R490 1 @ 2 0_0402_5% 2 0_0402_5% 2 <32> W L_OFF# 3VSW LAN_GATE 1K_0402_5% 1 D S 2 G Q61 SSM3K7002FU_SC70-3 BT_CTRL R491 1 BT_LED R492 1 <32> BT_LED BT Enable Disable BT_ON# L H BT_CTRL H L 2 0_0402_5% 2 0_0402_5% +3VS_W LAN R962 1 BT @ D1 PCH_PCIE_W AKE#_R E1 G6 G7 E12 G8 BT_CTRL_R BT_LED_R F4 1 3 S 2 G <32> BT_ON# Clock PERN0 PERP0 PETN0 PETP0 PCIE signal USB_D+ USB_D- USB signal PERST_L WAKE_L WIFI_DISABLE WIFI_LED BT_DISABLE BT_LED Control GND NC 2 10K_0402_5% PCH_PCIE_W AKE#_R G1 G3 G5 G12 H1 H2 H11 H12 L1 L2 L3 L10 L11 L12 F10 F9 F8 GND[1] GND[2] GND[3] GND[4] GND[5] GND[6] GND[7] GND[8] GND[9] GND[10] GND[11] GND[12] GND[13] GND[14] GND[15] GND[16] GND[17] GND[18] GND[19] GND[20] GND[21] GND[22] GND[23] GND[24] GND[25] GND[26] GND[27] GND[28] GND[29] GND[30] GND[31] GND[32] GND[33] GND[34] GND[35] GND[36] GND[37] GND[38] GND[39] GND[40] GND[41] GND[42] GND[43] GND[44] GND[45] GND[46] GND[47] GND[48] GND[49] GND[50] GND[51] GND[52] GND[53] GND[54] GND[55] GND[56] GND[57] GND[58] GND[59] GND[60] GND[61] GND[62] GND[63] A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B11 B12 C1 C4 C5 C6 C7 C8 C9 C10 C12 D3 D4 D5 D6 D7 D8 D9 D10 D12 E3 E4 E5 E6 E7 E8 E9 E10 F3 F5 F6 F7 D C T77H281.01_81P BT_CTRL D Power C539 0.1U_0201_10V6K 2 1 R185 1K_0402_5% 1 2 C500 .1U_0402_16V7K 2 2 C 2 3VSW LAN_GATE_R 1 100K_0402_5% R472 1 <32> AOAC_ON 1 R451 3 +3VALW REFCLKREFCLK+ CLKREQ_L L6 L7 L8 L9 <14> PCIE_PRX_DTX_N2 <14> PCIE_PRX_DTX_P2 <14> PCIE_PTX_C_DRX_P2 <14> PCIE_PTX_C_DRX_N2 +3VS_W LAN 3V3 3.3VAUX L4 L5 F1 <14> CLK_PCIE_MINI1# <14> CLK_PCIE_MINI1 <14> MINI1_CLKREQ# +3VALW F12 G4 Q62 SSM3K7002FU_SC70-3 B B A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 Deciphered Date 2013/4/6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title On Board WLAN Size Document Number Custom Q3ZMC M/B LA-8481P Schematic Date: Thursday, April 12, 2012 Sheet 1 28 of 51 Rev 1.0 A B C D E For mSATA Function 40mil +3VS +3VS_FULL H +1.5VS Port0 L @ 2 2 1 JUMP_43X39 2 1 C455 4.7U_0603_6.3V6K 1 2 C475 0.1U_0201_10V6K 1 C466 0.1U_0201_10V6K 2 1@ C442 0.1U_0402_16V4Z 1 2 2 C441 0.1U_0402_16V4Z +1.5VS +3VS_FULL 1 JMINI1 <13> SATA_PTX_DRX_N1 <13> SATA_PTX_DRX_P1 <13> SATA_PRX_DTX_P1 <13> SATA_PRX_DTX_N1 C625 1 C627 1 2 0.01U_0201_10V7K SATA_PTX_C_DRX_N1 2 0.01U_0201_10V7K SATA_PTX_C_DRX_P1 C628 1 C626 1 2 0.01U_0201_10V7K SATA_PRX_C_DTX_P1 2 0.01U_0201_10V7K SATA_PRX_C_DTX_N1 From DG=>Change to 0.01u <13> SATA_PRX_DTX_P0 <13> SATA_PRX_DTX_N0 <13> SATA_PTX_DRX_N0 <13> SATA_PTX_DRX_P0 C621 1 C622 1 2 0.01U_0201_10V7K SATA_PRX_C_DTX_P0 2 0.01U_0201_10V7K SATA_PRX_C_DTX_N0 C623 1 C624 1 2 0.01U_0201_10V7K SATA_PTX_C_DRX_N0 2 0.01U_0201_10V7K SATA_PTX_C_DRX_P0 +3VS_FULL 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 4 6 8 10 12 14 16 RAID0_DET <18> R329 100K_0402_5% 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 2 G1 G2 G3 G4 2 4 6 8 10 12 14 16 R300 R288 1K_0402_5% 53 54 55 56 1 2 0_0402_5% E51TXD_P80DATA_R 2 0_0402_5% E51RXD_P80CLK_R 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 1 3 5 7 9 11 13 15 1 R299 1 R287 1 <32> E51TXD_P80DATA <32> E51RXD_P80CLK 2 1 3 5 7 9 11 13 15 1 1 Port0,1 2 J8 1 +3VS_FULL RAID0_DET 20mil BELLW _80060-1021 2 2 100K_0402_5% MSATA_DET# MSATA_DET# <18> 3 3 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 Deciphered Date 2013/4/6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title mSATA HDD Connector Size Document Number Custom Q3ZMC M/B LA-8481P Schematic Date: Thursday, April 12, 2012 Sheet E 29 of 51 Rev 1.0 5 4 3 2 1 MOTOR/RTC 40mils 40mils +3VALW +3V_MCU JMR1 10mils VR_LEFT <32> VR_RIGHT <32> R21 10K_0402_5% 20mil R789 470K_0402_5% 2 +RTCBATT_R D S Q87 SI3456DDV-T1-GE3_TSOP6 MOTOR_GATE 6 CONN@ 4 3 MOTOR_PWR_ON# E-T_4260K-Q08N-13L 6 5 2 1 G VR_LEFT VR_RIGHT D +VSB 2 +3VALW MOTOR_PPS_L <32> MOTOR_PPS_R <32> 3 40mil 1 +MT_VCC +3V_MCU MOTOR_PPS_L MOTOR_PPS_R 1 1 2 3 4 5 6 7 8 9 10 1 2 Q93A DMN66D0LDW-7_SOT363-6 1 <32,45> MOTOR_PWR_ON 5 4 1 2 3 4 5 6 7 8 GND GND D Q93B DMN66D0LDW-7_SOT363-6 C811 0.1U_0603_25V7K 2 C C TPM 2 10mil +3V_TXM 2 +3VALW JUMP_43X39 J15 @ 2 1 2 +3VALW_TPM J16 @ 1 1 1 2 JUMP_43X39 TXM@ C1 10U_0603_6.3V6M 2 B 1 TXM@ C3 0.1U_0201_10V6K near pin24 2 1 2 2 JUMP_43X39 TPM@ C6 10U_0603_6.3V6M TXM@ C4 0.1U_0201_10V6K 1 +3VS 1 10mil J17 @ 1 1 2 +3VALW 1 2 near pin19 TPM@ C9 0.1U_0201_10V6K B near pin5 U7 TPM@ R963 1 @ BADD_BA0 CLKRUN# 1 2 6 9 15 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 26 23 20 17 CLK_PCI_TXM LPC_FRAME# PLT_RST# SERIRQ 28 21 22 16 27 7 2 10K_0402_5% <15> CLKRUN# <13,32> <13,32> <13,32> <13,32> LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 <17> CLK_PCI_TXM <13,32> LPC_FRAME# <17,22,24,32,5> PLT_RST# <13,32> SERIRQ GPIO0/XOR_OUT GPIO1 GPIO2/GPX GPIO3/BADD GPIO4/CLKRUN# VSB VDD1 VDD2 TEST LAD0 LAD1 LAD2 LAD3 LPCPD# LCLK LFRAME# LRESET# SERIRQ PP NC NC NC NC NC NC VSS1 VSS2 VSS3 5 19 24 +3VALW_TPM_R R966 1 TPM@ 2 0_0402_5% +3V_TXM 8 +3VALW_TPM TPM -Address: Pin9 BADD 1: 7Eh-7Fh (Default) 0: EEh-EFh 3 10 11 12 13 14 4 18 25 NPCT42XAA0WX_TSSOP28 SA00005PH00 A CLK_PCI_TXM @ 1 R716 2 33_0402_5% @C724 @ C724 1 2 A 22P_0402_50V8J Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 2013/4/6 Deciphered Date Title TPM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: 5 4 3 2 Thursday, April 12, 2012 Sheet 1 30 of 51 Rev 1.0 R9 USB3.0@ 2 1 PCH_USB3_TX1_P_C C424 0.1U_0201_10V6K USB3.0@ 2 1 PCH_USB3_TX1_N_C C422 0.1U_0201_10V6K <17> PCH_USB3_TX1_P <17> PCH_USB3_TX1_N 1 @ 3 3 2 1 3 4 1 U3TXDP1 U3TXDP1 D35 1 1 U3TXDN1 4 @ 10 9 U3TXDP1 2 2 9 8 U3TXDN1 U3RXDP1 4 4 7 7 U3RXDP1 U3RXDN1 5 5 6 6 U3RXDN1 U3TXDN1 L3 R10 1 @ OCE2012120YZF_4P 2 0_0402_5% R11 1 @ 2 0_0402_5% 1 +5VALW For ESD request 2 0_0402_5% USB3.0@ 2 2 +USB3_VCCA C432 0.01U_0402_16V7K 1 2 U17 1 2 3 4 <32> USB_EN# GND VIN VIN EN 3 3 D 8 <17> USB20_N0 1 3 4 R710 1 R713 1 <17> USB20_N9 1 @ R715 1 R714 @ 4 U3RXDN1 3 2 USB20_P0P9 0_0402_5% 2 USB20_N0N9 0_0402_5% @ R314 0_0402_5% 2 1 USB_OC0# <17> AP2301MPG-13_MSOP8 1 C417 @ 0.1U_0402_16V4Z 2 D 3 4 2 For USB2.0 ESD request U2DP0 0_0402_5% 1 W=80mils L05ESDL5V0NA-4 SLP2510P8 D24 2 @ R691 USB3.0@ USB20_N0N9 2 2 USB20_P0P9 <17> USB20_P9 U3RXDP1 OCE2012120YZF_4P 1 @ 2 0_0402_5% 2 USB20_P0P9 0_0402_5% 2 USB20_N0N9 0_0402_5% 1 5 +USB3_VCCA 1 U2DN0 4 U2DP0 6 4 I/O4 I/O2 VDD GND I/O3 I/O1 1 3 2 +3VALW 1 U2DN0 AZC099-04S.R7G_SOT23-6 L52 W CM2012F2S-900T04_0805 1 2 @ R689 0_0402_5% 2 <17> USB20_P0 1 1 3 L4 R12 2 C393 470P_0402_50V7K PCH_USB3_RX1_N <17> PCH_USB3_RX1_N 2 8 7 6 5 VOUT VOUT VOUT FLG +USB3_VCCA USB3.0@ PCH_USB3_RX1_P <17> PCH_USB3_RX1_P EPAD 4 9 5 SGA00001E00 S POLY C 150U 6.3V M B2LESR45M PSL H1.9 USB3.0 Conn. JUSB1 1 2 3 4 5 6 7 8 9 10 U2DN0 U2DP0 U3RXDN1 R744 U3RXDP1 100K_0402_5% U3TXDN1 U3TXDP1 <32> USB_HPD# VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+ DET GND GND GND GND 11 12 13 14 TAIW I_USB005-107CRL-TW Resister overlap with L52 CONN@ C R20 2 D36 3 L6 R15 2 1 3 1 @ 4 1 4 +USB3_VCCA For ESD request U3TXDP2 W=80mils @ U3TXDP2 1 1 10 9 U3TXDP2 U3TXDN2 2 2 9 8 U3TXDN2 U3RXDP2 4 4 7 7 U3RXDP2 U3RXDN2 5 5 6 6 U3RXDN2 U3TXDN2 OCE2012120YZF_4P 2 0_0402_5% 3 3 1 @ +3VALW 8 2 0_0402_5% <17> PCH_USB3_RX2_P <17> PCH_USB3_RX2_N PCH_USB3_RX2_P 2 PCH_USB3_RX2_N 3 L5 R17 B 2 1 3 4 1 U3RXDP2 4 U3RXDN2 1 USB3.0@ L05ESDL5V0NA-4 SLP2510P8 OCE2012120YZF_4P 1 @ 2 0_0402_5% USB_HPD# 2 R16 1 + 2 2 C394 <17> PCH_USB3_TX2_N 2 0_0402_5% 1 C391 470P_0402_50V7K <17> PCH_USB3_TX2_P 1 @ USB3.0@ 150U_B2_6.3VM_R35M USB3.0@ 2 1 PCH_USB3_TX2_P_C C428 .1U_0402_16V7K USB3.0@ 2 1 PCH_USB3_TX2_N_C C427 .1U_0402_16V7K SGA00001E00 S POLY C 150U 6.3V M B2LESR45M PSL H1.9 USB3.0 Conn. JUSB2 1 2 3 4 5 6 7 8 9 10 U2DN1 U2DP1 U3RXDN2 R745 U3RXDP2 100K_0402_5% U3TXDN2 U3TXDP2 For USB2.0 ESD request <17> USB20_N1 <17> USB20_P1 1 @ R743 USB3.0@ 2 2 3 3 2 1 4 U2DP1 1 U2DN1 4 U2DP1 +USB3_VCCA L53 W CM2012F2S-900T04_0805 1 2 @ R693 0_0402_5% 6 5 4 VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+ DET GND GND GND GND 11 12 13 14 B TAIW I_USB005-107CRL-TW CONN@ D33 0_0402_5% C I/O4 I/O2 VDD GND I/O3 I/O1 3 2 1 U2DN1 AZC099-04S.R7G_SOT23-6 A A Compal Secret Data Security Classification Issued Date 2012/4/6 Deciphered Date 2013/4/6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title USB3.0 Size Document Number Custom Q3ZMC M/B LA-8481P Schematic Date: Thursday, April 12, 2012 Sheet 1 31 of 51 Rev 1.0 A B C D E +3VALW U53 0.1U_0201_10V6K R939 1 R941 1 2 2.2K_0402_5% EC_SMB_DA1 R942 1 2 2.2K_0402_5% EC_SMB_CK1 R943 @ 1 @ 2 1K_0402_5% 2 10K_0402_5% GATEA20 EC_KBRST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 <18> GATEA20 <18> EC_KBRST# <13,30> SERIRQ <13,30> LPC_FRAME# <13,30> LPC_AD3 <13,30> LPC_AD2 <13,30> LPC_AD1 <13,30> LPC_AD0 EC_SMI# CLK_PCI_LPC PLT_RST# EC_RST# EC_SCI# AOAC_ON <17> CLK_PCI_LPC <17,22,24,30,5> PLT_RST# EC_PME# <18> EC_SCI# <28> AOAC_ON +3VS R944 1 2 2.2K_0402_5% EC_SMB_CK2 R945 1 2 2.2K_0402_5% EC_SMB_DA2 R946 1 2 10K_0402_5% EC_SCI# R949 1 2 100K_0402_5% PLT_RST# 1 C1209 2 <33> KSI[0..7] 2 0.01U_0402_16V7K <33> KSO[0..15] ESD request @ R951 2 R952 2 <31> USB_EN# @ 1 0_0402_5% 1 0_0402_5% KSI[0..7] KSO[0..15] <15> ACPRESENT 1 2 3 4 5 7 8 10 12 13 37 20 38 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 USB_EN#_R ACPRESENT 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 77 78 79 80 GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC & MISC LPC_AD0 2 10K_0402_5% <22> PWR_SUSP_LED# <33> MOTOR_LED# Board ID +3VALW IRST_RST# Analog Board ID definition, Please see page 3. 2 <25> TB_LED <15> SUSCLK R957 100K_0402_5% 1 R959 R961 2 AD_BID0 XCLKI/GPIO5D XCLKO/GPIO5E 9012@ R960 56K_0402_5% 1 1 C1213 0.1U_0201_10V6K C1215 2 1 Rb 122 123 PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO0C GPIO0D EC_INVT_PWM/GPIO11 FAN_SPEED1/GPIO14 EC_PME#/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A 1 100K_0402_5% 2 1 Ra TB_LED 2 EC_XCLK0 @ 0_0402_5% 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D IREF/GPIO3E CHGVADJ/GPIO3F EC_MUTE#/GPIO4A USB_EN#/GPIO4B CAP_INT#/GPIO4C EAPD/GPIO4D TP_CLK/GPIO4E TP_DATA/GPIO4F PS2 Interface CPU1.5V_S3_GATE/GPXIOA00 WOL_EN/GPXIOA01 HDA_SDO/GPXIOA02 VCIN0_PH/GPXIOD00 C1204 0.1U_0201_10V6K C451 1000P_0201_16V7K R928 2 @ 1 10K_0402_5% BKOFF# R934 1 @ 2 10K_0402_5% TP_CLK R929 1 2 4.7K_0402_5% TP_DATA R931 1 2 4.7K_0402_5% R935 2 930@ 1 200K_0402_5% R1017 2 9012@ 1 200K_0402_5% +3VS 1 2 2 C450 1000P_0201_16V7K 21 23 26 27 MOTOR_PWR_ON BEEP# FAN_PWM ACOFF C1206 2 BATT_TEMP 63 64 65 66 75 76 SPI Flash ROM GPIO Bus SPIDI/GPIO5B SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A ENBKL/GPIO40 PECI_KB930/GPIO41 FSTCHG/GPIO50 BATT_CHG_LED#/GPIO52 CAPS_LED#/GPIO53 PWR_LED#/GPIO54 BATT_LOW_LED#/GPIO55 SYSON/GPIO56 VR_ON/GPIO57 PM_SLP_S4#/GPIO59 EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04 PROCHOT_IN/GPXIOA05 H_PROCHOT#_EC/GPXIOA06 VCOUT0_PH/GPXIOA07 GPO BKOFF#/GPXIOA08 PBTN_OUT#/GPXIOA09 PCH_APWROK/GPXIOA10 SA_PGOOD/GPXIOA11 GPIO AC_IN/GPXIOD01 EC_ON/GPXIOD02 ON/OFF/GPXIOD03 GPI LID_SW#/GPXIOD04 SUSP#/GPXIOD05 GPXIOD06 PECI_KB9012/GPXIOD07 V18R 1 100P_0402_50V8J ECAGND ECAGND <37> BATT_TEMP <37> TB_EJECT_BTN <25> ADP_I <37,38> ADP_I AD_BID0 VR_RIGHT TB_OK2GO2SX# 2 VR_RIGHT <30> TB_OK2GO2SX# <24> 68 70 71 72 SUSACK# TB_GO2SX WL_OFF# TB_PWRON_POC_RST# 83 84 85 86 87 88 EC_MUTE# SLP_SUS# MOTOR_PPS_L EAPD TP_CLK TP_DATA 97 98 99 109 USB_HPD# DRAMRST_CNTRL_EC HDA_SDO VCIN0_PH_R 119 120 126 128 73 74 89 90 91 92 93 95 121 127 BT_LED EC_SPOK MOTOR_VID0 MOTOR_VID1 2 R950 ENBKL VR_LEFT FSTCHG BATT_BLUE_LED# MOTOR_PPS_R PWR_LED# BATT_AMB_LED# SYSON VR_ON PM_SLP_S4# 100 101 102 103 104 105 106 107 108 PCH_RSMRST# EC_LID_OUT# VCIN1_PROCHOT_R H_PROCHOT#_EC GPXIOA07 BKOFF# PBTN_OUT# SUSWARN# SA_PGOOD 110 112 114 115 116 117 118 EC_ACIN EC_ON ON/OFF LID_SW# SUSP# BT_ON# KB9012_PECI 124 +V18R EC_MUTE# <33> SLP_SUS# <15> MOTOR_PPS_L <30> EAPD <33> TP_CLK <33> TP_DATA <33> 2 C1207 1 100P_0402_50V8J 2 VR_HOT# <43> VR_HOT# R940 0_0402_5% 1 @ H_PROCHOT# <5> D S 2 G H_PROCHOT#_EC USB_HPD# <31> DRAMRST_CNTRL_EC <6> HDA_SDO <13> Q60 SSM3K7002FU_SC70-3 2 Latest design guide suggest change to 74LVC1G06. BT_LED <28> EC_SPOK <37> MOTOR_VID0 <45> MOTOR_VID1 <45> KB930&9012 Co-Layout Item Pin 111 is a power source for HW operation of KB9012. So, power plan will be different between KB930 and KB9012. 1 100K_0402_5% ENBKL <16> VR_LEFT <30> FSTCHG <38> BATT_BLUE_LED# <22> MOTOR_PPS_R <30> PWR_LED# <22> BATT_AMB_LED# <22> SYSON <35,40> VR_ON <43> PM_SLP_S4# <15> +EC_VCC 1 930@ 2 R930 0_0402_5% 1 9012@ 2 R932 0_0402_5% +3VALW +3VLP Pin74(KB930),Pin118(KB9012) are with different PECI pin location, so HW must co-layout for it. Please make sure which EC pin will be connected to PECI circuit. PCH_RSMRST# <15> EC_LID_OUT# <18> 1 KB9012_PECI R958 2 9012@ H_PECI <18,5> 43_0402_1% Pin104 co-layout circuit is for power fail function of KB930 and KB9012. At KB930, PCH_PWROK will be connected to pin 104. At KB9012,PCH_PWROK will be connected to pin 32, and VCOUT0_PH will be connected to pin 104. BKOFF# <22> PBTN_OUT# <15> SUSWARN# <15> SA_PGOOD <42> 1 9012_PCH_PWROK 2 @ R956 0_0402_5% 2 1 GPXIOA07 R955 930@ 0_0402_5% 2 1 R954 9012@ 0_0402_5% EC_ON <39> ON/OFF <33> LID_SW# <22> SUSP# <35,38,40,41> BT_ON# <28> 1 @ 2 1 @ 2 R947 VCIN1_PROCHOT_R C1214 4.7U_0603_6.3V6K L57 1 ECAGND 2 FBMA-L11-160808-800LMT_0603 MAINPWON <39> 0_0402_5% +3VALW_EC KSO1 R936 2 930@ 1 47K_0402_5% KSO2 R937 2 930@ 1 47K_0402_5% 3 PCH_PWROK <15> 0_0402_5% R953 20mil 2 +3VLP ACIN <15,35,38,39> SUSACK# <15> TB_GO2SX <24> WL_OFF# <28> TB_PWRON_POC_RST# <24> VCIN0_PH_R 1 +3VALW 1 RB751V-40_SOD323-2 D37 2 KB9012QF-A3_LQFP128_14X14 1 MOTOR_PWR_ON <30,45> BEEP# <33> FAN_PWM <34> ACOFF <36> SPI Device Interface GND/GND GND/GND GND/GND GND/GND GND0 R965 1 3 PM_SLP_S3# PM_SLP_S5# EC_SMI# PCH_PWR_EN MOTOR_BTN DPWROK IRST_RST# BI_DET FAN_SPEED1 EC_PME# E51TXD_P80DATA E51RXD_P80CLK 9012_PCH_PWROK PWR_SUSP_LED# MOTOR_LED# <15> PM_SLP_S3# <15> PM_SLP_S5# <18> EC_SMI# <35> PCH_PWR_EN <33> MOTOR_BTN <15> DPWROK <17> IRST_RST# <33> BI_DET <34> FAN_SPEED1 <28> EC_PME# <29> E51TXD_P80DATA <29> E51RXD_P80CLK 2 EC_ACIN DA Output EC_SMB_CK1/GPIO44 EC_SMB_DA1/GPIO45 SM EC_SMB_CK2/GPIO46 EC_SMB_DA2/GPIO47 GPIO0F BEEP#/GPIO10 GPIO12 ACOFF/GPIO13 BATT_TEMP/GPIO38 GPIO39 ADP_I/GPIO3A GPIO3B GPIO42 IMON/GPIO43 AD Input 11 24 35 94 113 +3VALW_EC EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 EC_MUTE# FAN_PWM 1 +3VS PWM Output CLK_PCI_EC PCIRST#/GPIO05 EC_RST# EC_SCII#/GPIO0E GPIO1D KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 +EC_VCC <37> ECAGND +EC_VCC SYSON# <35> <37,38> <37,38> <11,14,24> <11,14,24> 1 100K_0402_5% 1 1 +3VALW_EC 2 1 1 1 FAN_SPEED1 R948 3 C1208 2 1 2 C1203 1000P_0201_16V7K +3VALW_EC 2 2 C1202 1000P_0201_16V7K 2 2 EC_RST# 2 1 C1201 0.1U_0201_10V6K 1 JUMP_43X39 1 47K_0402_5% 2 1 C1200 0.1U_0201_10V6K 1 R938 2 2 1 C1199 0.1U_0201_10V6K J11 @ C1198 0.1U_0201_10V6K +3VLP +3VALW_EC 1 LID_SW# 67 2 2 EC_VDD/AVCC 1 JUMP_43X39 AGND/AGND 1 L56 FBMA-L11-160808-800LMT_0603 1 2 +EC_VCCA @ 69 J9 9 22 33 96 111 125 +3VALW @ R933 33_0402_5% 2 1 CLK_PCI_LPC EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD0 EC_VDD/VCC @ C1205 22P_0402_50V8J 2 1 VCIN0_PH <37> VCIN1_PROCHOT <37> 20P_0402_50V8 Follow KB930 checking List +3VALW_EC TB_EJECT_BTN R976 1 2 2.2K_0402_5% 4 4 2 VR_LEFT 2 VR_RIGHT R454 100K_0402_1% R455 100K_0402_1% 2012/4/6 2013/4/6 Deciphered Date Title EC ENE-KB930/KB9012 1 1 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: A B C D Thursday, April 12, 2012 Sheet E 32 of 51 Rev 1.0 KSI[0..7] <32> KSO[0..15] <32> +3VALW +3VS D 1 R971 10K_0402_5% 10 9 8 7 6 5 4 3 2 1 SMB_ALERT#_R Q9 SMB_ALERT#_R ON/OFFBTN# <22> ON/OFFBTN# SSM3K7002FU_SC70-3 R967 1 A 1 2 2 TP_DATA <32> TP_CLK <32> C216 100P_0402_50V8J +3VALW_EC 1 R974 0_0402_5% D_CK_SCLK TP_DATA ACES_85208-24071 CONN@ 1 D_CK_SDATA TP_CLK R908 100K_0402_5% C252 1 @ 2 100P_0201_25V8J KSO6 C251 1 @ 2 100P_0201_25V8J KSO13 C258 1 @ 2 100P_0201_25V8J KSO5 C250 1 @ 2 100P_0201_25V8J KSO12 C271 1 @ 2 100P_0201_25V8J KSO4 C249 1 @ 2 100P_0201_25V8J KSI0 C263 1 @ 2 100P_0201_25V8J KSO3 C248 1 @ 2 100P_0201_25V8J KSO11 C256 1 @ 2 100P_0201_25V8J KSI4 C267 1 @ 2 100P_0201_25V8J KSO10 C255 1 @ 2 100P_0201_25V8J KSO2 C247 1 @ 2 100P_0201_25V8J KSI1 C272 1 @ 2 100P_0201_25V8J KSO1 C246 1 @ 2 100P_0201_25V8J KSI2 C265 1 @ 2 100P_0201_25V8J KSO0 C245 1 @ 2 100P_0201_25V8J KSO9 C254 1 @ 2 100P_0201_25V8J KSI5 C268 1 @ 2 100P_0201_25V8J KSI3 C266 1 @ 2 100P_0201_25V8J KSI6 C269 1 @ 2 100P_0201_25V8J KSO8 C253 1 @ 2 100P_0201_25V8J KSI7 C270 1 @ 2 100P_0201_25V8J @ 2 0_0402_5% 3 2 3 B +3VS Audio/B 20pin 1 KSO7 100P_0201_25V8J R975 1 2 JAUDIO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 G1 G2 G3 G4 C R968 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 HDA_BITCLK_AUDIO <13> 10K_0402_5% 2 100P_0201_25V8J C259 1 @ 2 MOTOR_BTN <32> BAV70W_SOT323-3 HDA_RST_AUDIO# <13> HDA_SYNC_AUDIO <13> HDA_SDOUT_AUDIO <13> HDA_SDIN0 <13> BEEP EAPD <32> EC_MUTE# <32> BI_GATE# MOTOR_BTN_SW# MOTOR_LED# <32> +3VALW 10mil 20mil +3VS 60mil +5VS C1224 1 <32> BEEP# 2 1 R970 1U_0402_6.3V6K C1227 1 <13> PCH_SPKR 2 2 BEEP 560_0402_5% 1 R972 1U_0402_6.3V6K 2 560_0402_5% 1 C260 1 @ 2 KSO14 1 3 @ D4 @D4 AZ5125-02S.R7G_SOT23-3 C196 0.1U_0201_10V6K 1 KSO15 MOTOR_BTN_SW# D41 RB751V-40_SOD323-2 2 B EMI request @ R909 100K_0402_5% D22 1 BOT side @ D6 AZ5125-02S.R7G_SOT23-3 2 +3VS +3VLP 2 C217 100P_0402_50V8J 1 1 +3VS E-T_6701K-Q08N-00R 25 26 ON/OFF <32> D_CK_SCLK <14> D_CK_SDATA <14> 2 GND1 GND2 9012@ R907 100K_0402_5% 2 0_0402_5% @ 2 G G 8 7 6 5 4 3 2 1 3 1 1 <14> SMB_ALERT# CONN@ JTP1 +3VLP 930@ R144 100K_0402_5% 2 KSO[0..15] KSI0 KSI1 KSI2 KSO0 KSO1 KSO2 KSI3 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSI4 KSO9 KSI5 KSI6 KSO10 KSO11 KSI7 KSO12 KSO13 KSO14 KSO15 8 2 A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 7 ON/OFF BTN Motor BTN +3VS 2 G JKB1 6 2 TP Conn. KSI[0..7] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 5 1 KB Conn. 4 2 3 1 2 S 1 C Battery Reset 10mil ACES_50406-02071-001 +RTCVCC 1 CONN@ R850 1 2 510K_0402_5% R969 1 D 3 2 BI_GATE# BI_DET <32> BI <37> 1K_0402_5% S 2 G Q8 SSM3K7002FU_SC70-3 Need Check Gate Threshold Voltage Battery BI Low voltage is 0.8V D D Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 2013/4/6 Deciphered Date Title BIOS, I/O Port & K/B Connector THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Thursday, April 12, 2012 Date: 1 2 3 4 5 6 7 Sheet 33 8 of 51 Rev 1.0 FAN Conn 20mil FIDUCIAL_C40M80 1 +3VS H1 H_5P2 @ FIDUCIAL_C40M80 FD4 @ FIDUCIAL_C40M80 @ FIDUCIAL_C40M80 H2 H_5P2 H3 H_5P2 H4 H_5P2 H5 H_5P2 @ @ 1 @ 1 @ 1 6 5 1 G2 G1 1 4 3 2 1 @ ACES_88266-04001 CONN@ Thermal module @ 定定定 H10 H_2P5x3P0 @ H8 H_4P0 @ @ @ H11 H_4P0N @ Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date H9 H_4P0 1 H7 H_4P0 1 H6 H_4P0 1 2 4 3 2 1 1 @ <32> FAN_PWM C579 1000P_0402_50V7K FAN_SPEED1 FAN_PWM 1 2 JFAN1 1 FD3 Stand-Off R489 10K_0402_5% <32> FAN_SPEED1 @ 1 1 C587 1000P_0402_50V7K 1 2 FD2 1 FD1 1 C585 10U_0805_25V6K 1 2 1 +5VS 2012/4/6 Deciphered Date 2013/4/6 Title Step Motor,FAN,Screw Hole THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: Thursday, April 12, 2012 Sheet 34 of 51 Rev 1.0 A B +5VALW to +5VS +3VALW to +3VALW_PCH(PCH AUX Power) +5VS U22 SI7716ADN-T1-GE3_POWERPAK8-5 1 2 5 3 2 +3VALW E 2 2 <40,5> SUSP SUSP 3 5 <32,38,40,41> SUSP# Q19B DMN66D0LDW-7_SOT363-6 1 1 S C499 .1U_0603_25V7K R251 10K_0402_5% 2 D G DMN66D0LDW-7_SOT363-6 Q59A 4 2 S Q19A DMN66D0LDW-7_SOT363-6 1 4 D G 1 SUSP 3 6 1 R246 100K_0402_5% 1 2 2 1 4 1 0_0402_5% G 5VS_GATE 5 SUSP @ S 10mil 2 1 R437 20K_0402_5% R629 2 R440 470_0603_5% D 2 +5VALW +3VALW_PCH C701 4.7U_0603_6.3V6K 1 C469 1U_0603_10V6K 1 1 20mil C498 4.7U_0603_10V6K 1 C464 4.7U_0603_10V6K 2 20mil D +5VALW Rds=13.5mΩ(Typ) 16.5mΩ(Max) +VSB C +3VALW to +3VS 1 2 2 6 4 +5VALW R441 100K_0402_5% D 1 2 2 R436 470_0603_5% 3VS_GATE G +VSB 10mil 1 C458 1U_0402_6.3V6K R368 47K_0402_5% 2 1 1 C461 4.7U_0603_6.3V6K C375 10U_0603_6.3V6M 2 +3VS U21 SI7716ADN-T1-GE3_POWERPAK8-5 1 2 5 3 2 2 +3VALW Rds=13.5mΩ(Typ) 16.5mΩ(Max) 2 SUSP 3 C463 .1U_0603_25V7K 2 D G 5 SUSP Q25B DMN66D0LDW-7_SOT363-6 1 1 1 S 20mil SYSON# <32> SYSON# 6 4 S 2 G SYSON 1.35VS_GATE 2 SUSP D 2 C380 .1U_0603_25V7K 2 1 +5VALW Q15B DMN66D0LDW-7_SOT363-6 1 1 2 1 3 1 R449 100K_0402_5% S @ Q21 SSM3K7002FU_SC70-3 <20> PCH_PWR_EN# 1 <32> PCH_PWR_EN 1 G S 4 2 3 1 S D ACIN 2 G <15,32,38,39> ACIN @ R277 1M_0402_5% Q15A DMN66D0LDW-7_SOT363-6 R268 510K_0402_5% 5 SUSP @ D 3 2 1 R269 200K_0402_5% 3 D +VSB 20mil R245 470_0603_5% 6 10mil 2 2 2 1 4 1 2 1 1 C338 1U_0402_6.3V6K 2 C339 4.7U_0603_6.3V6K 1 +1.35VS U12 SI7716ADN-T1-GE3_POWERPAK8-5 1 2 5 3 2 G +1.35V C376 0.1U_0402_16V4Z 2 C377 0.1U_0402_16V4Z C460 10U_0603_6.3V6M 3 1 R438 100K_0402_5% +1.35V to +1.35VS Rds=2.6mΩ(Typ) 3.2mΩ(Max) Q59B DMN66D0LDW-7_SOT363-6 1 1 S <32,40> SYSON D Q25A DMN66D0LDW-7_SOT363-6 S 2 G Q26 SSM3K7002FU_SC70-3 2 R450 100K_0402_5% S D S 2 1 1 Q23 2 SUSP G SSM3K7002FU_SC70-3 4 R508 470_0603_5% D Q5 2 SUSP G SSM3K7002FU_SC70-3 S 3 D 1 1 Q24 @ 2 SYSON# G SSM3K7002FU_SC70-3 +1.8VS R29 470_0603_5% 3 3 S 1 2 D R366 22_0603_5% 3 1 1 @ R365 470_0603_5% +1.05VS_VTT 2 1 +0.675VS 2 +1.35V 4 Q34 2 SUSP G SSM3K7002FU_SC70-3 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 2013/4/6 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DC Interface Q3ZMC M/B LA-8481P Schematic Date: A B C D Thursday, April 12, 2012 Sheet E 35 of 51 Rev 1.0 A B C D VIN PR2 1K_1206_5% 1 2 VIN PC4 1000P_0402_50V7K PQ1 TP0610K-T1-E3_SOT23-3 PD1 LL4148_LL34-2 2 1 3 B+ 1 1 2 1 2 2 PR4 1K_1206_5% 1 2 PR6 100K_0402_5% PR3 1K_1206_5% 1 2 1 PC3 100P_0402_50V8J 1 1 1 PC2 100P_0402_50V8J 1 PR1 1K_1206_5% 1 2 2 2 ACES_88266-04001 PC1 1000P_0402_50V7K 2 1 1 2 3 4 GND GND DC_IN_S1 2 PJP1 1 2 3 4 5 6 Pre_CHG PL1 SMB3025500YA_2P 1 2 PR5 100K_0402_5% 1 PR7 100K_0402_5% 1 2 PQ3 PDTC115EU_SOT323-32 2 3 3 2 PQ2 PDTC115EU_SOT323-3 1 2 0_0402_5% PD2 PR22 BAS40CW _SOT323-3 <32> ACOFF 2 1 2 1 3 +5VALWP PJ1 +3VALWP 1 1 PJ2 2 2 +3VALW 1 +5VALWP JUMP_43X79 PJ8 1 2 1 2 JUMP_43X39 3 BATT+ +VSBP 1 1 2 2 +5VALW JUMP_43X39 PJ4 PJ3 @ PD4 LL4148_LL34-2 2 1 1 JUMP_43X79 PJ10 1 2 1 2 2 2 +VSB 1 +1.35VP 1 2 2 +1.35V JUMP_43X79 PJ5 1 2 1 2 JUMP_43X39 VS 3 JUMP_43X79 PJ7 PJ6 +1.8VSP 1 1 2 2 1 +1.8VS +1.05VS_VCCPP JUMP_43X39 1 2 2 +1.05VS_VTT JUMP_43X79 PJ9 +0.675VSP 1 1 2 2 +0.675VS JUMP_43X39 PJ12 1 +HV_12VP PJ11 +3VLP PR57 560_0603_5% 1 2 4 +RTCBATT_R PR102 560_0603_5% 1 2 +RTCBATT +CHGRTC PR12 0_0402_5% 1 +VCCSAP 1 1 2 1 2 PJ15 +1.05VS_LCP 2 1 1 2 2 4 +1.05VS_LC JUMP_43X39 Issued Date Compal Electronics, Inc. Compal Secret Data 2012/4/6 Deciphered Date 2013/4/6 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: B +HV_12V +VCCSA JUMP_43X118 Security Classification A 2 2 JUMP_43X39 C DCIN/PRECHARGE Rev 1.0 Chief River VC Thursday, April 12, 2012 D Sheet 36 of 51 A B C D CONN@ ACES_88231-08001 1 EC_SMDA EC_SMCA TH BI+ 2 1 PR17 100_0402_1% EC_SMB_DA1 <32,38> EC_SMB_CK1 <32,38> 1 1 <40,41> BATT+ 2 PL2 SMB3025500YA_2P 1 2 BATT_S1 PC9 0.01U_0402_25V7K 2 PC8 1000P_0402_50V7K 2 1 PR15 100_0402_1% <40,41> VMB 1 1 2 3 4 5 6 7 8 9 10 2 1 1 2 3 4 5 6 7 8 GND1 GND2 PJP2 PR19 1K_0402_5% G718 PR20 6.49K_0402_1% 2 1 ENE9012 +3VALW 3.92K ADP_I <32,38> 2.21K 1 65W 65W @ PR33 1.65K_0402_1% PR21 1K_0402_1% 8.87K 6.98K 1 90W 2 BI <33> VCIN1 1.2V 0.925V 90W @ PR33 6.98K_0402_1% 2 BATT_TEMP <32> 1.456V 1.148V 2 2 VCIN1_PROCHOT <32> For 65W adapter==>action 70W , Recovery 54W 1 For 90W adapter==>action 97W , Recovery 75W PR38 10K_0402_1% 2 For 40W thunder bolt adapter==>action 50W , Recovery 38W VCIN1=0.9V recover = 0.683V PQ6 TP0610K-T1-E3_SOT23-3 PH1 under CPU botten side : CPU thermal protection at 92 degree C for reference +EC_VCC <32> 1 1 3 PR29 12.4K_0402_1% 2 2 PC14 .1U_0402_16V7K D S 2 G PQ7 SSM3K7002FU_SC70-3 1 VCIN0_PH <32> 2 2 @ PC15 1U_0402_6.3V6K 1 @ PR34 1K_0402_5% 1 2 1 <39> SPOK 3 2 @ PR28 100K_0402_1% 1 2 1 +VSBP PC13 0.1U_0603_25V7K 2 @ 1 2 VL 2 PR27 22K_0402_1% 2 1 1 1 PR26 100K_0402_1% <32> EC_SPOK 3 PC12 0.22U_0603_25V7K 3 B+ PC17 .1U_0402_16V7K PH1 1 EC side 2 100K_0201_1%_TSMAB104F4251RZ ECAGND ECAGND <32> 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 Deciphered Date 2013/4/6 Title BATTERY CONN / OTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C 4 Rev 1.0 Chief River VC Thursday, April 12, 2012 D Sheet 37 of 51 A B C D 1 D 3 for reverse input protection S 2 G 1 2 1 PR39 1M_0402_5% 1 PQ8 SI1304BDL-T1-E3_SC70-3 2 PR40 3M_0402_5% 1 VIN P1 PQ9 SIS412DN-T1-GE3_POW ERPAK8-5 P2 PQ10 SIS412DN-T1-GE3_POW ERPAK8-5 B+ PR41 0.02_1206_1% CHG_B+ PQ11 SIS412DN-T1-GE3_POW ERPAK8-5 PJ21 Pre_CHG 2 CSON1 PR55 6.8_0603_5% BQ24725_BATDRV 1 L-->H H-->L 2 3 1 2 1 1 2 1 PQ15 SSM3K7002FU_SC70-3 PC44 100P_0402_50V8J S Close EC B 1 PR43 0_0402_5% 2 1 PC36 0.01U_0402_50V7K 2 PC39 2200P_0402_50V7K PC35 10U_0805_25V6K 2 1 1 PC34 10U_0805_25V6K 2 1 2 CSON1 1 PC38 0.1U_0402_25V6 CSOP1 1 2 PC37 0.1U_0402_25V6 1 PR53 4.7_1206_5% 2 EC_SMB_DA1 <32,37> Min. 3.906A Typ Max. 4.006A 4.108A 4 ADP_I <32,37> @ PC45 0.1U_0402_16V7K Compal Secret Data 2012/4/6 Deciphered Date 2013/4/6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A Max. 18.275V 17.898V ILIM and external DPM Security Classification Issued Date Typ 18.063V 17.687V EC_SMB_CK1 <32,37> PR65 66.5K_0603_0.1% PR66 0_0402_5% 1 2 Min. 17.852V 17.476V 2 3 2 G PC43 0.1U_0402_16V7K D 4 <32,35,40,41> SUSP# 2 2 1 Vin Dectector PR63 154K_0603_0.1% 1 2 1 <32> FSTCHG PR64 100K_0402_1% 1 2 3 2 PR58 316K_0402_1% ACDET PQ14 PDTC115EU_SOT323-3 @ 1 PC42 0.01U_0402_25V7K 2 1 1 PR62 2M_0402_1% 2 PR60 280K_0603_0.1% 1 2 3 +3VALW PR61 100K_0402_1% VIN 2 --> 1 PR59 2M_0402_1% battery 4.35/cell *4 =17.4, battery voltage back to back --> Vin 2 1 PD9 RB751V-40_SOD323-2 2 SRN 1 11 @ PC40 680P_0402_50V7K 12 PR54 10_0603_5% 2 CSOP1 ILIM SCL SRP 1 1 ACDET BATDRV 9 <15,32,35,39> ACIN ACOK 13 2 2 3 2 1 5 14 10 PR56 100K_0402_1% 3 5 SDA ACOK SRN 8 2 SRP ACDRV IOUT 1 CMSRC 7 4 PL4 PR52 4.7UH_FDSD0630-H-4R7M-P3_5.5A_20% 0.01_1206_1% 1 2 CHG 1 4 BQ24725_LX PQ13 SIS412DN-T1-GE3_POWERPAK8-5 GND 4 DL_CHG 3 2 1 ACP 15 1 REGN BTST LODRV ACDET BQ24725_ACDRV 2 BATT+ PC33 1 2 16 17 18 HIDRV 19 20 VCC ACN 6 +3VLP 3 1 PQ12 SIS412DN-T1-GE3_POW ERPAK8-5 PD7 RB751V-40_SOD323-2 BQ24725RGRR_VQFN20_3P5X3P5 BQ24725_CMSRC 2 5 1 PR48 2.2_0603_5% 1 PR50 0_0402_5% 2DH_CHG-1 4 DH_CHG 1 2 PC41 0.1U_0603_25V7K 2 PAD PHASE 1 @ PR44 4.12K_0603_1% 1U_0603_25V6K PU4 PC27 0.01U_0402_50V7K 2 BQ24725_BATDRV 1 2 DH_CHG BQ24725_LX BQ24725_BST 2 PR47 10_1206_1% 1 1U_0603_25V6K 21 4 PC23 0.1U_0402_25V6 2 1 2 2 3 PC29 0.047U_0402_25V7K 1 2 2 PC31 1 2 1 2 3 5 PD6 BAS40CW_SOT323-3 1 1 PC28 0.1U_0402_25V6 2 BQ24725_ACP 1 2 BQ24725_ACN PC30 0.1U_0603_25V7K 2 PC24 2200P_0402_50V7K 2 2 VIN PC26 0.1U_0402_25V6 1 2 PR46 4.12K_0603_1% 1 PR45 4.12K_0603_1% 2 1 2 1 1 1 JUMP_43X79 PC22 10U_0805_25V6K 2 1 3 2 4 2 1 1 PC21 10U_0805_25V6K 5 4 1 PC16 0.1U_0402_25V6 2 @ 2 1 4 PC25 2200P_0402_50V7K 2 1 1 2 3 PR42 0_0402_5% 1 2 3 5 C Title Compal Electronics, Inc. PWR DCIN / Pre-charge Size Document Number Custom Rev 1.0 Q3ZMC M/B LA-8481P Schematic Date: Sheet Thursday, April 12, 2012 D 38 of 51 5 4 3 2 1 Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO PC46 1U_0603_10V6K 2VREF_8205 1 D 2 D PR67 13.7K_0402_1% 1 2 PR69 20K_0402_1% 2 1 RT8205_B+ G S 1 1 PC67 1U_0603_10V6K 5 PC57 0.1U_0603_25V7K 2 1 PC53 2200P_0402_50V7K 2 1 PC56 4.7U_0805_25V6-K 2 1 PC55 4.7U_0805_25V6-K 2 1 1 19 LG_5V 3 2 1 LX_5V SIS412DN-T1-GE3_POW ERPAK8-5 PC65 4.7U_0805_10V6K 1 2 Typ: 175mA 1 2 3 2 1 @ +5VALWP 1 + PC63 680P_0402_50V7K SECFB 4 PR76 4.7_1206_5% PL7 4.7UH_FDSD0630-H-4R7M-P3_5.5A_20% 1 2 5 2 3 ENTRIP1 S PQ21 PDTC115EU_SOT323-3 2 2 930@ PR83 316K_0402_1% 1 2 2 G 2 PC62 150U_B2_6.3VM_R35M @ Typ 13.5m ohm max 16.5m ohm RT8205 TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP) (2)SMPS2=375KHZ(+3VALWP) B TPS51125A TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP) (2)SMPS2=305KHZ(+3VALWP) 3.3VALWP Delta I = 2.709A (Freq=305KHz) Iocp = 8.7746A ~ 10.42 5VALWP Delta I = 3.199A (Freq=245KHz) Iocp = 9.0195A ~ 10.673A +3.3VALWP Ipeak=7A ; Imax=4.9A Delta I=2.2036A=>1/2Delta I=1.1017A (F=375K Hz) Rds(on)=16.5m ohm(max) ; Rds(on)=13.5m ohm(typical) Ilimit_min=(147K*10uA)/(10*16.5m*1.2)=7.42A Ilimit_max=(147K*10uA)/(10*13.5m*1.2)=9.07A Iocp=Ilimit+1/2Delta I=8.52A~10.174A +5VALWP Ipeak=7A ; Imax=4.9A Delta I=2.6129A=>1/2Delta I=1.3064A (F=300K Hz) Rds(on)=16.5m ohm(max) ; Rds(on)=13.5m ohm(typical) Ilimit_min=(147K*10uA)/(10*16.5m*1.2)=7.42A Ilimit_max=(147K*10uA)/(10*13.5m*1.2)=9.074A Iocp=Ilimit+1/2Delta I=8.7264A ~ 10.38A A D 2 3 D 930@ PR81 1M_0402_1% 1 2 930@ PQ22 PDTC115EU_SOT323-3 5 G 930@ PQ23A DMN66D0LDW -7_SOT363-6 930@ PQ23B DMN66D0LDW -7_SOT363-6 4 VS VS 6 930@ PR84 1M_0402_1% 1 2 1 VL 1 ACIN VIN UG_5V 20 PR79 100K_0402_1% 2 1 3 2 1 930@ PR85 10K_0402_1% 2 1 930@ PR82 402K_0402_1% 930@ PD11 LL4148_LL34-2 2 1 21 9012@ PR100 2.2K_0402_1% 1 2 PR80 0_0402_5% 1 2 <32> MAINPWON PR74 PC59 2.2_0603_5% 0.1U_0603_25V7K 2 1 2 BST_5V 1 3 <32> EC_ON PQ20B DMN66D0LDW -7_SOT363-6 4 1 VL 2VREF_8205 D 5 G S ENTRIP1 FB1 1 2 PC64 1U_0603_10V6K 2 1 PR78 150K_0402_1% 2 1 RT8205_B+ 1 2 22 VL 2 PC66 0.1U_0603_25V7K 3 6 D 23 SI7716ADN-T1-GE3_POW ERPAK8-5 ENTRIP2 C SPOK <37> PQ19 B PQ20A DMN66D0LDW -7_SOT363-6 PQ17 4 24 18 14 13 PR77 499K_0402_1% 1 2 Typ 13.5m ohm max 16.5m ohm ENTRIP1 REF LGATE1 VREG5 LGATE2 VIN PHASE1 EN B+ 1 2 3 @ TONSEL UGATE1 PHASE2 4 PD10 RLZ5.1B_LL34 1 2 4 ENTRIP2 5 6 UGATE2 17 12 LG_3V VFB=2.0V PQ18 SI7716ADN-T1-GE3_POW ERPAK8-5 PC61 680P_0402_50V7K 2 1 + 2 A RT8205_B+ PR72 147K_0402_1% 2 VREG3 RT8205LZQW (2)_W QFN24_4X4 PGOOD BOOT2 BOOT1 @ 1 PC60 150U_B2_6.3VM_R35M 5 PR75 4.7_1206_5% 2 1 PL6 3.3UH_FDSD0630-H-3R3M-P3_6.6A_20% 2 1 1 VOUT1 16 8 PR73 1 2 1 BST_3V 9 2.2_0603_5% UG_3V 10 PC58 0.1U_0603_25V7K 11 LX_3V SIS412DN-T1-GE3_POW ERPAK8-5 2 VOUT2 GND 1 2 3 7 +3VALWP P PAD FB2 25 15 4 ENTRIP2 C PU5 1 PC54 4.7U_0805_10V6K PQ16 PR71 147K_0402_1% 2 1 2 5 PC49 0.1U_0603_25V7K 2 1 +3VLP SKIPSEL 2 PC52 2200P_0402_50V7K 2 1 2 PC51 4.7U_0805_25V6-K 2 1 1 JUMP_43X79 PC50 4.7U_0805_25V6-K 2 1 1 PR70 20K_0402_1% 1 2 Typ: 175mA PJ17 B+ PR68 30K_0402_1% 2 1 Compal Secret Data Security Classification 2012/4/6 Issued Date S 2013/4/6 Deciphered Date Title Compal Electronics, Inc. 3VALW/5VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Thursday, April 12, 2012 Date: Rev 1.0 Chief River VC 5 4 3 2 Sheet 1 39 of 51 A B C D Ipeak = 9.8A, Imax = 6.86A Delta I = 2.88A, F= 290KHz, Rton= 887K ohm Rtrip = 19.6K ohm OCP= 13.45~16.56A 1 2 1 1 PJ24 JUMP_43X39 1 PQ24 SIS412DN-T1-GE3_POW ERPAK8-5 2 4 3 4 +VTT_REFP 1 1 +1.35VP 5 RT8207MZQW _W QFN20_3X3 VTTREF 1 2 PGND CS VDDP 4 LG_1.5V 14 13 + 1 15 PR88 19.6K_0402_1% 2 1 PC74 330U_B2_2.5VM_R15M 2 @ PC75 680P_0402_50V7K 2 LX_1.5V 16 LGATE VTTSNS GND 2 @ PR87 4.7_1206_5% PHASE UG_1.5V 17 UGATE BOOT BST_1.5V 19 VTTGND PL9 1.5UH_MMD-06CZ-1R5M-V1_9A_20% PR86 PC71 2.2_0603_5% 0.1U_0603_25V7K 1 2 BST_1.5V-1 1 2 3 2 1 2 PAD VLDOIN 1 VTT 1 PC73 10U_0805_25V6K 2 1 PC72 10U_0805_25V6K 2 PU6 21 20 靠靠Output Cap PAD +0.675VSP 18 3 2 1 2 2 JUMP_43X39 2 B+ 2 2 PJ13 1 1 1 1 JUMP_43X79 PC68 10U_0805_25V6K +1.35VP 5 +1.35VS PJ18 1 1.5V_B+ PQ25 SI7716ADN-T1-GE3_POW ERPAK8-5 Rds=13.5mΩ(Typ) 16.5mΩ(Max) 12 1 PR89 5.1_0603_5% +5VALW need change OCP setting 2 1 2 1 PR90 10K_0402_5% PC77 1U_0603_10V6K 2 1 PGOOD 10 TON S5 8 S5_1.5V 2 PC78 1U_0603_10V6K @ PGOOD_1.5V PR94 4.64K_0402_1% 2 1 1 PR95 5.76K_0402_1% PQ26 SSM3K7002FU_SC70-3 FB=0.75V To GND = 1.5V To VDD = 1.35V FB=0.6V Note:Iload(max)=3.5A S5 S0 Hi Hi On On S3 Lo Hi On On Lo Lo S4/S5 1.35VP VTT_REFP 0.675VSP On Off (Hi-Z) Off Off Off (Discharge) (Discharge) (Discharge) SY8033BDBC_DFN10_3X3 @ 1 2 SY8033B enable pin without internal pull down, and RT8061or other 2nd source has 500K pull down resistor!So please review your application if R1>249K will cause enable pin logic high level is not enough Note: S3 - sleep ; S5 - power off Issued Date 4 Compal Secret Data Security Classification 2012/4/6 Deciphered Date 2013/4/6 Title 1.5VP/0.75VSP/1.8VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A PC82 22U_0805_6.3VAM PR99 10K_0402_1% 2 1 1 1 FB_1.8V +1.8VSP PC81 68P_0402_50V8J 2 1 1 PR97 20K_0402_1% 2 1 2 PR96 4.7_0805_5% 6 NC FB EN 11 1 2 4 S3 3 3 PL10 1UH_PH041H-1R0MS_3.8A_20% 1 2 SVIN PC84 0.1U_0402_16V7K 1 2 STATE LX TP PR257 100K_0402_1% 1 2 +1.8VSP_ON PR98 1M_0402_5% LX PVIN LX_1.8V PC87 47P_0402_50V8J 5 SUSP# PVIN NC PC80 22U_0805_6.3VAM 8 2 2 9 1 JUMP_43X39 7 2 10 1 1 2 PC85 680P_0402_50V7K PJ14 1 2 +3VALW 4 PU7 PG 3 2 S 2 G 11 +3VALW 2 1 D 3 <35,5> SUSP VDD PR93 887K_0402_1% 2 1 1.5V_B+ 2 @ PC79 0.1U_0402_16V7K 2 PC325 .1U_0402_16V7K 1 <32,35> SYSON 9 7 S3_1.5V PR92 0_0402_5% 1 2 1 <32,35,38,41> SUSP# PR91 680K_0402_1% 1 2 S3 VDDQ FB PC76 0.033U_0402_16V7K 5 6 1 2 +1.35VP 2 2 B C Rev 1.0 Chief River VC Thursday, April 12, 2012 D Sheet 40 of 51 5 4 3 2 1 +3VS 2 PQ29 V5IN TST DRVL TP PR114 470K_0402_1% SW_+1.05VS_VTTP 1 2 PL14 1UH_VMPI0703AR-1R0M-Z01_11A_20% 1 2 7 6 +5VALW LG_+1.05VS_VTTP 11 +1.05VS_VCCPP + @ PR115 4.7_1206_5% 3 2 1 1 2 2 TPS51212DSCR_SON10_3X3 1 PQ30 MDU1511RH_POWERDFN56-8-5 4 PC101 1U_0603_10V6K C @ PC104 680P_0402_50V7K 2 Rds=2.6mΩ(Typ) 3.2mΩ(Max) 1 VFB UG_+1.05VS_VTTP 8 2 SW BST_+1.05VS_VTTP 9 MDV1525URH_PDFN33-8-5 D 1 EN 10 B+ 5 DRVH 1 5 VBST TRIP PC99 0.1U_0603_25V7K 1 2 2 RF_+1.05VS_VTTP PGOOD 2 3 2 1 PR111 2.2_0603_5% 1 2 1 FB_+1.05VS_VTTP 4 2 PC100 0.1U_0402_16V7K 1 TRIP_+1.05VS_VTTP2 2 5 1 4 EN_+1.05VS_VTTP 3 1 SUSP# PR112 52.3K_0402_1% 2 1 PR113 330K_0402_1% 1 2 1 JUMP_43X79 @ PR274 0_0402_5% PU9 1 +1.05VS_VTTP_B+ PC97 10U_0805_25V6K <42> VCCPPWRGOOD D PJ19 Cesr= 15m ohm Ipeak= 15.24A Imax= 10.668A Delta I= 3.306A ==>1/2 Delta I= 1.653A Vtrip=Rtrip*10uA= 0.523V Iocp= 18.74A~22.66A 2 PR101 0_0402_5% 2 1 PC96 2200P_0402_50V7K 2 1 PR261 10K_0402_1% PC95 0.1U_0402_25V6 2 1 1 VFB= 0.704V Vo=VFB*(1+PR116/PR119)= 1.05V Freq= 266~314KHz , 290KHz(typ) PC103 .1U_0402_16V7K 等 IVB ES2 PC102 330U_B2_2.5VM_R15M 2 改改 1.05V 之之改之 0.1U_0402_16V7K C PR116 4.87K_0402_1% 2 1 VFB=0.7V 1 PC105 1000P_0402_50V7K 2 1 等 PR119 10K_0402_1% 2 IVB ES2 PR117 1.2K_0402_1% 2 1 改改 1.05V PR118 100_0402_1% 1 2 之之之之 VCCIO_SENSE <8> +1.8VS 2 2 +5VALW 1 B 1 PC86 1U_0402_6.3V6K PJ20 JUMP_43X39 @ 1 3 1 PR105 1.54K_0402_1% PC90 0.01U_0402_25V7K 1 9 PU8 APL5915KAI-TRL_SO8 +1.5VS 1 2 PC88 22U_0805_6.3V6M 2 VIN PC91 4.7U_0805_6.3V6K 2 GND FB 4 2 PC89 0.1U_0402_16V7K 1 1 EN 5 2 VOUT 8 2 PR103 47K_0402_5% VIN VOUT 1 PR106 100K_0402_5% 1 2 1 <32,35,38,40> SUSP# POK 2 7 VCNTL 6 2 1 B 2 PR104 1.74K_0402_1% A A Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2012/4/6 2013/4/6 Deciphered Date Title +1.05VS_VTTP/+1.0VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Rev 1.0 Chief River VC Thursday, April 12, 2012 Sheet 1 41 of 51 5 4 3 2 1 VID [0] 0 0 1 1 +VCC_SAP TDC 4.2A Peak Current 6A OCP current 7.2A VID[1] 0 1 0 1 VCCSA Vout 0.9V 0.8V 0.725V 0.675V output voltage adjustable network D D PU10 SY8037DCC_DFN12_3X3 8 LX SVIN LX FB PG VOUT EN VID1 VID0 PL15 0.47UH +-20% PCMC042T-R47MN 6A 1 2 +VCCSA_PHASE 2 3 SA_PGOOD <32> PR120 100K_0402_5% 2 +VCCSA_PWRGD 1 4 5 1 +VCCSA_EN +3VS 2 PR124 0_0402_5% 6 1 VCCPPWRGOOD <41> @ PC109 680P_0402_50V7K 2 +VCCSA_VID0 13 +VCCSA_VID1 +VCCSAP @ PR126 @PR126 4.7_0805_5% 2 7 PVIN 1 PC115 2200P_0402_50V7K 2 1 9 LX PC114 22U_0805_6.3V6M 1 2 2 10 PC106 68P_0402_50V8J 2 1 PVIN PC113 22U_0805_6.3V6M 1 2 1 11 PC112 .1U_0402_16V7K 2 1 JUMP_43X79 12 1 +VCCSA_PWR_SRC 2 2 1 2 PC120 22U_0805_6.3V6M 1 2 1 PC119 0.1U_0603_25V7K 1 2 1 PC118 2200P_0402_50V7K +3VALW GND PJ23 @ PC107 .1U_0402_16V7K H_VCCSA_VID0 <9> PR122 1K_0402_5% 2 1 The 1k PD on the VCCSA VIDs are empty. These should be stuffed to ensure that VCCSA VID is 00 prior to VCCIO stability. PR121 1K_0402_5% 2 1 C C PR128 100_0402_5% 2 1 H_VCCSA_VID1 <9> PR130 0_0402_5% 2 1 VCCSA_SENSE <9> PC92 22U_0805_6.3VAM 2 PR109 7.5K_0402_1% PR110 4.7_0805_5% B @ PC111 680P_0402_50V7K 1 FB_1.05TPP 1 1 PU11 SY8032ABC_SOT23-6 PR108 10K_0402_1% 2 2 2 PR107 1M_0402_1% 2 +1.05TPP_ON 2 EN_LC_PWR PC117 0.1U_0402_16V7K <24> EN_LC_PWR FB=0.6V 1 B PR258 0_0402_5% 1 2 +1.05VS_LCP 1 1 EN PL8 1UH_PH041H-1R0MS_3.8A_20% 1 2 2 GND FB LX_1.05TPP 1 PG 3 PC93 22U_0805_6.3VAM 6 LX 1 5 JUMP_43X39 <27> 1.05VS_LC_PG IN 2 4 PC108 22U_0805_6.3VAM 2 2 PC94 68P_0402_50V8J 2 1 1 1 1 2 PJ16 +3VALW PR123 100K_0402_5% 1 2 2 1 +3VALW A A Compal Secret Data Security Classification Issued Date 2012/4/6 Deciphered Date 2013/4/6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: 5 4 3 2 Compal Electronics, Inc. VCC_SAP/+1.5VSDGPUP/+1.05VS_DGPU Document Number Rev 1.0 Chief River VC Thursday, April 12, 2012 Sheet 1 42 of 51 3 @ PC125 1000P_0402_50V7K PC127 0.01UF_0402_25V7K 2 1 PR204 1_0402_5% 2 PR203 3.65K_0603_1% 1 PR200 4.7_1206_5% VSUMG- 3 2 1 1 PR162 1_0603_5% PQ40 MDU1511RH_POWERDFN56-8-5 2 PR174 2 1.91K_0402_1% 1 +3VS UGATE1 PR192 0_0603_5% 1 2 5 PC176 10U_0805_25V6K 2 1 CPU_B+ PQ37 MDV1525URH_PDFN33-8-5 VGATE <15> UGATE1-1 4 2 PC157 33U_D_25VM_R60M BOOT1 ISL95836HRTZ-T_TQFN40_5X5~D PC179 10U_0805_25V6K 2 1 UGATE1 C For ULV 17W 1+1 CPU_CORE LL= -2.9mΩ, GFX_CORE LL= -3.9mΩ, PC178 10U_0805_25V6K 2 1 1 2 PC154 1U_0603_10V6K 2 1 LGATE1 PHASE1 Rds(on)typ : 2.4m ohm max: 3.3m ohm PC177 10U_0805_25V6K 2 1 PR159 0_0603_5% PC155 1U_0603_10V6K 30 29 28 27 26 25 24 23 22 21 2 BOOT2 UGATE2 PHASE2 LGATE2 VCCP VDD PWM3 LGATE1 PHASE1 UGATE1 +5VS PR196 0_0402_5% 1 2 VSUMG+ 1 2 + 2 DCR: 1.19mΩ±5% +CPU_CORE @ 4 10K_0402_1%_ERTJ0EG103FA 1 VSUM+ 2 PR198 3.65K_0603_1% B @ 3 2 1 VSUM- Close Phase 1 choke PC175 2 1 PC188 680P_0402_50V7K 2 1 2 1 PR195 4.7_1206_5% 5 1 PR180 12 PC187 0.22U_0603_16V7K LGATE1 PH6 2 PC174 150P_0402_50V8J 2 1 2 1 PR190 137K_0402_1% 2 1 B+ PL16 FBMA-L11-322513-151LMA50T_1210 1 PL21 0.24UH_FDUE0630J-H-R24M-P3_22A_20% 1 Structure> 2 PHASE1 PR194 2.2_0603_5% 1 1 BOOT1 2 .1U_0402_16V7K PR189 1.91K_0402_1% 2 1 2.61K_0402_1% 1 11K_0402_1% 2 PR184 2 1 1 PR183 499_0402_1% 1 PC170 68P_0402_50V8J 2 1 PC166 0.1U_0603_25V7K 1 2 PC167 470P_0402_50V7K 2 1 2 PR177 42.2K_0402_1% 2 1 2 PR176 2K_0402_1% 2 1 PR187 523_0402_1% B 1 @ PC169 1000P_0402_50V7K VSUM+ PC162 470P_0402_50V7K 2 +VGFX_CORE 1 BOOT1G ISUMNG RTNG FBG COMPG PGOODG PWM2G LGATE1G PHASE1G UGATE1G BOOT1G 4 PR206 2.2_0603_5% 40 39 38 37 36 35 34 33 32 31 TP PC189 0.22U_0603_16V7K PC190 680P_0402_50V7K 2 1 2 UGATE1G 3 2 1 @ PC126 0.1U_0402_16V7K 41 PC184 10U_0805_25V6K 2 1 3 2 1 5 2 PHASE1G ISEN3/FB2 ISEN2 ISEN1 ISUMP ISUMN RTN FB COMP PGOOD BOOT1 1 2 1 1 2 +1.05VS_VTT PH5 470K_0402_5%_ TSM0B474J4702RE 2 1 2 1 2 PR168 0_0402_5% 1 2 PR169 130_0402_1% 1 2 PR170 75_0402_5% 1 2 PR171 54.9_0402_1% 1 2 @ ISUMPG ISEN1G ISEN2G NTCG SCLK ALERT# SDA VR_HOT# VR_ON NTC 11 12 13 14 15 16 17 18 19 20 1 1 2 470K_0402_5%_ TSM0B474J4702RE 2 PR160 0_0402_5% 1 2 0_0402_5% PR164 0_0402_5% 1 2 PR165 0_0402_5% 1 PR161 @ PC156 47P_0402_50V8J 1 2 3 4 5 6 7 8 9 10 ISEN2G NTCG SCLK ALERT# SDA PR172 27.4K_0402_1% 2 <8> VR_SVID_CLK <8> VR_SVID_ALRT# <8> VR_SVID_DAT <32> VR_HOT# <32> VR_ON PR155 0_0402_5% 1 2 PR173 3.83K_0402_1% +5VS PH4 PL23 0.24UH_FDUE0630J-H-R24M-P3_22A_20% 1 Structure> 2 PHASE1G LGATE1G LGATE1G C PR158 3.83K_0402_1% 1 2 DCR: 1.19mΩ±5% +5VS PR152 27.4K_0402_1% 2 1 @ D 4 UGATE1G BOOT1G PU13 PC183 10U_0805_25V6K 2 1 5 PQ38 MDV1525URH_PDFN33-8-5 PR147 2 1 1.91K_0402_1% +3VS 2 1 PR143 36.5K_0402_1% @ PC141 1000P_0402_50V7K 2 1 PC140 0.1U_0603_25V7K 1 2 PR142 11K_0402_1% 1 2 PR141 2.61K_0402_1% 1 2 1 .1U_0402_16V7K PC137 2 1 D VSUMG+ CPU_B+ 2 1 PR137 2.61K_0402_1% PC182 10U_0805_25V6K 2 1 PC135 150P_0402_50V8J 1 2 1 PR136 137K_0402_1% 2 1 1 2 PR135 523_0402_1% 2 1 PC134 470P_0402_50V7K 2 1 2 1 PR134 499_0402_1% PC181 10U_0805_25V6K 2 1 PC133 68P_0402_50V8J 2 1 PH3 10K_0402_1%_ERTJ0EG103FA VSUMG- 1 2 2 <9> VCC_AXG_SENSE <9> VSS_AXG_SENSE local sense revese HW 2 1 4 1 5 PQ39 MDU1511RH_POWERDFN56-8-5 2 VSUM- 1 PR201 1_0402_5% Rds(on)typ : 2.4m ohm max: 3.3m ohm @ PC180 330P_0402_50V7K 2 1 <8> VCCSENSE <8> VSSSENSE 2 1 PC186 0.01UF_0402_25V7K local sense revese HW A A Compal Secret Data Security Classification Issued Date 2012/4/6 2013/4/6 Deciphered Date Title Compal Electronics, Inc. CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Rev 1.0 Chief River VC Thursday, April 12, 2012 Sheet 1 43 of 51 4 3 2 1 2 1 2 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 2 1 2 2 1 2 1 2 1 2 PC254 47U_0805_6.3V6M PC253 47U_0805_6.3V6M 2 PC252 47U_0805_6.3V6M 2 1 For TOP side C PC267 22U_0805_6.3V6M 1 2 PC251 22U_0805_6.3V6M ‧ Can connect to GND if motherboard only 2 1 PC266 22U_0805_6.3V6M 2 Vaxg PC265 22U_0805_6.3V6M 1 1 PC250 22U_0805_6.3V6M 2 1 1 2 PC246 10U_0603_6.3V6M 1 2 PC245 10U_0603_6.3V6M 1 2 PC244 10U_0603_6.3V6M 1 2 PC243 10U_0603_6.3V6M 1 2 1 2 PC242 10U_0603_6.3V6M 1 2 PC294 1U_0201_4V6M PC293 1U_0201_4V6M 2 1 PC292 1U_0201_4V6M 2 1 PC264 1U_0201_4V6M 2 1 PC258 1U_0201_4V6M 2 1 PC235 1U_0201_4V6M 2 1 PC234 1U_0201_4V6M 2 1 PC233 1U_0201_4V6M 2 1 PC232 1U_0201_4V6M 2 1 PC231 1U_0201_4V6M 2 1 2 2 1 PC247 10U_0603_6.3V6M PC320 2.2U_0402_6.3V6M PC318 2.2U_0402_6.3V6M PC316 1U_0201_4V6M PC240 1U_0201_4V6M PC239 2.2U_0402_6.3V6M PC238 1U_0201_4V6M PC237 2.2U_0402_6.3V6M PC256 330U_D2_2V_Y PC319 1U_0201_4V6M PC317 1U_0201_4V6M PC275 1U_0201_4V6M PC229 1U_0201_4V6M PC228 1U_0201_4V6M PC227 1U_0201_4V6M PC226 1U_0201_4V6M 2 2 PC249 22U_0805_6.3V6M 2 C PC261 47U_0805_6.3V6M + PC260 47U_0805_6.3V6M 1 PC259 47U_0805_6.3V6M 1 + D For BOT side +CPU_CORE 1 PC255 330U_B_2.5VM_R9M PC236 1U_0201_4V6M D 1 +CPU_CORE PC225 1U_0201_4V6M 1 +VGFX_CORE PC230 1U_0201_4V6M 2 1 PWR Rule CPU LL=2.9m ohm dedign 330uF/9m *4, 22uF *12, 2.2uF*16 GFX LL=3.9m ohm design 330uF/9m *2, 22uF*6, 10uF*6 , 1uF*11 1.05V 330uF*2 10uF*10, 1u*26 2 5 supports external graphics and if GFX VR is not stuffed in a common motherboard design, ‧ VAXG can be left floating in a common +CPU_CORE PC356 1U_0201_4V6M 1 + PC271 330U_D2_2V_Y 2 1 1 + @PC272 330U_D2_2V_Y + 2 2 PC273 need link SGA00006J00. PC273 560U 2V M D2 PC357 1U_0201_4V6M B 1 + 2 PC291 330U_B2_2.5VM_R15M PC280 22U_0805_6.3V6M PC354 1U_0201_4V6M 2 1 PC355 1U_0201_4V6M 2 1 1 2 PC281 22U_0805_6.3V6M PC327 1U_0201_4V6M 2 1 PC284 1U_0201_4V6M 2 1 1 2 PC282 22U_0805_6.3V6M PC328 1U_0201_4V6M 2 1 PC285 1U_0201_4V6M 2 1 1 2 PC283 22U_0805_6.3V6M 2 1 PC286 1U_0201_4V6M 2 1 PC329 1U_0201_4V6M 2 1 +1.05VS_VTT PC279 22U_0805_6.3V6M PC330 1U_0201_4V6M 2 1 2 1 PC287 1U_0201_4V6M 2 1 PC331 1U_0201_4V6M 2 1 PC288 1U_0201_4V6M 2 1 PC332 1U_0201_4V6M 2 1 PC289 1U_0201_4V6M 2 1 PC333 1U_0201_4V6M 2 1 PC321 1U_0201_4V6M 2 1 PC334 1U_0201_4V6M 2 1 PC322 1U_0201_4V6M 2 1 PC351 1U_0201_4V6M 2 1 PC323 1U_0201_4V6M 2 1 PC353 1U_0201_4V6M 2 1 PC352 1U_0201_4V6M 2 1 PC324 1U_0201_4V6M 2 1 2 1 B PC326 1U_0201_4V6M 2 1 2 1 motherboard design (Gfx VR keeps VAXG from floating) if the VR is stuffed A A INTEL Recommend 3*330uF(1 in other page),12*22uF, 5 no stuff from PDDG 1.0 Compal Secret Data Security Classification 2012/4/6 Issued Date Deciphered Date 2013/4/6 Title Compal Electronics, Inc. CPU_CORE_CAP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Rev 1.0 Chief River VC Thursday, April 12, 2012 Sheet 1 44 of 51 4 3 PQ47 AON7403L_DFN8-5 1 +5VALW 1 2 1 2 3 2 PL27 4.7UH_MMD-04BZ-4R7M-S1L_2.4A_20% PD15 1 2 LX_12VSP 2 5 +HV_12VP 2 PC360 1U_0402_6.3V6K PR289 86.6K_0402_1% 1 1 2 1 SX34 SMA 2 PC359 0.01U_0402_16V7K 2 1 4 1 1 2 PR288 100K_0402_5% D PC358 0.01U_0402_16V7K 2 JUMP_43X39 1 1 PR291 10K_0402_1% D 2 G 1 7 PR294 0_0402_5% 1 +5VALW 2 2 FREQ_12VSP9 3 FREQ SS EN 2 FB_12VSP 10 SS_12VSP FB =1.24V 1COMP_12VSP COMP GND GND PR295 10K_0402_1% C 1 5 PC363 0.1U_0402_10V7K PC365 0.01U_0402_16V7K RT9297GQW_WDFN10_3X3 2 1 2 1 PR293 100K_0402_5% 11 C 4 1 PAD 2 PR292 10K_0402_5% FB 2 EN_12VSP Vin 1 LX PU16 2 6 S LX 3 PQ48 SSM3K7002FU_SC70-3 8 1 D 2 PR290 10K_0402_5% <24> PA_HV_EN 1 PC362 10U_0805_25V6K 2 1 PJ22 2 PC361 10U_0805_25V6K 2 1 5 PC364 4700P_0402_25V7K L/RDC=C*R 2.2uL/40mohm=0.00022uF*250Kohm Rdc=40ohm(max) 3V3/2V JACKET 1 2 1 Motor_VCC4 4.7U_0603_10V6K Motor_EN 5 SW VCC IN EN FREQ 9 Motor_IN 8 Motor_FREQ 7 Motor_FB 2 PR300 1 PC372 10U_0805_25V6K PR301 8.45K_0402_1% FB=0.815V 1Motor_FB +3VALW +MT_VCC 0 0 2 1 0 3.3 0 1 reserve 1 1 5 2 1 MOTOR_VID1 <32> G 1 PC375 0.1U_0402_25V6 4 S 2 2 1 PR308 100K_0402_5% 1 2 5 S VID1 PR306 10K_0402_5% D PQ49B DMN66D0LDW-7_SOT363-6 1 1 2 MOTOR_VID0 <32> 1 6 PR307 100K_0402_5% 1 2 2 G VID0 +3VALW 3 2 2 PR304 5.76K_0402_1% 10K_0402_5% D A 1 432K_0402_1% PC373 1000P_0402_25V8J B 2 1 Motor_FB PR303 7.68K_0402_1% PQ49A DMN66D0LDW-7_SOT363-6 B+ 2 100K_0402_5% PR302 FB PC369 22U_0805_6.3V6M 2 2 1 1 PR299 6 PG @ PC374 0.1U_0201_10V6K 1 >1.6V ENABLE 10K_0402_5% 2 PJ26 JUMP_43X39 1 2 1 2 1 2 PC371 BST Motor_SW 2 <30,32> MOTOR_PWR_ON 1 Motor_FB 10 1 B Motor_BST 3 PR297 12K_0402_1% PC368 0.01U_0402_25V7K 2 1 2 PR298 10_0402_5% 1 PU17 MP2334DD-LF-Z_QFN12_2X3 11 GND 12 1 GND GND 2 13 SW SW 5V_BST# +MT_VCC PR296 PC367 300K_0402_1% 470P_0402_50V7K 1 2 1 Motor_Compensate2 1 2 PC366 1U_0402_16V6K 2 1 PL28 2.2UH_1231AS-H-2R2M-P3_1.9A_20% 1 2 2 @ PR309 10K_0402_5% PC376 0.1U_0402_25V6 2 Compal Secret Data Security Classification 2012/4/6 Issued Date 2013/4/6 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 A @ PR310 @PR310 10K_0402_5% 4 3 2 Compal Electronics, Inc. 12V & MOTOR Power Document Number Rev 1.0 Thursday, April 12, 2012 Sheet 1 45 of 51 5 4 VR_ON 3 (PU1000) ISL6266ACRZ-T 2 +CPU_CORE 1 +1.5VS_DMC D D TQFN48 VGA_ON Page 55 (PU998) APW7138NITRL SSOP16 ADAPTER SYSON VS_ON BATTERY (SUSP#) VCCPWRGOOD SUSP (U13) SI4800BDY-T1-GE3 VGA_ON# +1.5VS Page 44 (PU5) RT8209BGQW +1.5V SUSP (PU6) RT8209BGQW WQFN14 (PU8) APL5331KAC-TRL SO8 Page 51 +1.05V_VCCP Page 53 PJP25 U38 (PU3) RT8205EGQW (U40) AO4430L SO8 Page 54 WQFN14 B+ +VGA_CORE +1.5VSDGPU Page 44 +0.75VS Page 53 +1.05VS_PCH L76 +CLK_1.05VS +1.05VSDGPU +VCCSA C C WQFN24 CHARGER Page 49 (PU3) RT8205EGQW WQFN24 Page 49 +5VALW SUSP SYSON# (U49) SI4800BDY SO8 (U46) TPS2062ADR +3VALW SUSP PCH_PWR_EN# (PU6) SY8033BDBC DFN10 Page 44 Page 51 SUSP (U14) SI4800BDY SO8 R599 (RE1) Page 44 SUSP (U68) SI4800BDY (UB1) RT9701-PB SO8 SOT23-5 Page 44 Page 45 B B +5VS +USB_VCCB +1.8VS +3VALW_PCH +3V_LAN (U39) BCM57780 +CRT_VCC +3VALW_EC +3V ENVDD ENVDD (Q51) AO3413L SO23-3 +HDMI_5V_OUT +3VS +3VS_CK505 Page 37 VGA_ON (Q30) AO3413L SO23-3 (Q34) AO3413L Page 30 SO23-3 Page 24 +DVDD_AUDIO +1.2V_LAN +BT_VCC +LCDVDD +3VSDGPU +5VS_HDD1 +3V_WLAN +5VS_ODD +3V_DMC A A +5VAMP +VDDA Compal Secret Data Security Classification Issued Date 2012/4/6 2013/4/6 Deciphered Date Title Compal Electronics, Inc. Power Rail THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Q3ZMC M/B LA-8481P Schematic Date: 5 4 3 2 Thursday, April 12, 2012 Sheet 1 46 of 51 Rev 1.0 5 4 3 2 1 D D 2 A3 PU6 +3VALW 2 V B4 V 4 EC PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# PM_SLP_A# PM_SLP_SUS# C B6 H_CPUPWRGD PLT_RST# V 14 15 CPU C 6 V ON/OFF V A4 V PBTN_OUT# EC_ON PCH 5 PM_DRAM_PWRGD V V B7 SYSON 7 SYSON# V A5 V PCH_RSMRST# V V 51ON# SYS_PWROK 13 PQ4 B3 +3VALW_PCH +5VALW_PCH 3 2 +1.35V PU6 V B+ B7 V B2 A5 U22 +5VS 8 SUSP#,SUSP B V B1 B5 U21 +3VS V BATT U14,+3VALW_PCH QH4,+5VALW_PCH U12 +1.35VS V B+ V V A2 PU4 VV VIN V V BATT MODE A1 V AC MODE V PCH_PWR_EN# PU6 +0.675V PU9 +1.05VS_VCCP 9 V VR_ON VGATE B V V VCCPPWRGOOD 11 PU10 +VCCSA PU13 +CPU_CORE A A Compal Secret Data Security Classification Issued Date 2012/4/6 2013/4/6 Deciphered Date Title Compal Electronics, Inc. Power sequence THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 Q3ZMC M/B LA-8481P Schematic Date: 5 4 3 2 Thursday, April 12, 2012 Sheet 1 47 of 51 5 4 3 2 Version change list (P.I.R. List) Item D 1 Fixed Issue Add ADP_ID circuit Page 1 of 2 for PWR Reason for change Acer will add pull down resistor in adapter to detect ADP_ID. Rev. PG# 0.1 36 2 Add Jack_TEMP and PH1 circuit Acer request add a thermistor on jack of DC in cable to protect jack. 0.1 37 3 Adjust 1.35V ocp setting and add boost resistor Adjust 1.35V ocp setting Add boost resistor 0.1 40 Add 1.05V boost resistor and adjust output voltage Change choke to 1uH for efficiency of heavy load 0.1 Adjust GFX frequence to 400kHz for reduce ripple Adjust CPU output cap for transient 4 5 6 Add 1.05V boost resistor and adjust output voltage Change choke to 1uH Adjust GFX frequence Adjust CPU output cap 1 Modify List Date Add Add Add Add PU1 SA003310280 (S IC LMV331IDCKRG4 SC70 5P COMPARATORS) PQ27 SB000009Q80(S TR 2N7002KW 1N SOT323-3) PR13 PR16 SD034100280(S RES 1/16W 10K +-1% 0402) PR14 SD034100380(S RES 1/16W 100K +-1% 0402) Add Add Add Add Del PU3 SA00003K300 (S IC G718TM1U SOT23 8P OTP) PR30 SD000009R00(S RES 1/16W 46.4K +-1% 0402) PR35 SD034953180(S RES 1/16W 9.53K +-1% 0402) PR37 SD034232280(S RES 1/16W 23.2K +-1% 0402) PR127 SD028000080(S RES 1/16W 0 +-5% 0402) Phase 2011/12/05 EVT2 D 2011/12/05 EVT2 Change PR88 to SD000003580(S RES 1/16W 19.6K +-1% 0402) Change PR86 to SD013220B80(S RES 1/10W 2.2 +-5% 0603) 2011/12/05 EVT2 41 Change PR111 to SD013220B80(S RES 1/10W 2.2 +-5% 0603) Change PR116 to SD034487100(S RES 1/16W 4.87K +-1% 0402 (LF)) Change PL14 to SH00000KS00(S COIL 1UH +-20% VMPI0703AR-1R0M-Z01 11A) 2011/12/05 EVT2 0.1 43 Change PR143 to SD034365280(S RES 1/16W 36.5K +-1% 0402) 2011/12/05 EVT2 0.1 44 Change PC273 to SGA00006J00(S POLY C 560U 2V M D2 LESR4.5M SX H1.9) unpop PC272 SGA20331E10(S POLY C 330U 2V Y D2 LESR9M EEFSX H1.9) 2011/12/05 EVT2 C C 7 8 Adjust 0.675V enable timing Adjust 0.675V enable timing 0.1 40 Adjust 1.05VS_LCP sequence Change 1.05VS_LCP from APL5930 to SY8032 for thoundbolt sequence. 0.2 42 9 Change PC325 to SE076104K80(S CER CAP .1U 16V K X7R 0402) Change PU11 to SA000055100(S IC SY8032ABC SOT23 6P PWM) Change PR107 to SD034100480(S RES 1/16W 1M +-1% 0402) Add PL8 to SH00000MN00(S COIL 1UH +-20% PH041H-1R0MS 3.8A) Add PR110 to SD002470B80(S RES 1/8W 4.7 +-5% 0805) Change PC111 to SE074681K80(S CER CAP 680P 50V K X7R 0402) Change PC92 to SE000008L80(S CER CAP 22U 6.3V M X6S 0805 H1.25) Add PR123 to SD028100380(S RES 1/16W 100K +-5% 0402) Change PR108 to SD034100280(S RES 1/16W 10K +-1% 0402) Change PR109 to SD034750180(S RES 1/16W 7.5K +-1% 0402) Change PC94 to SE071680J80(S CER CAP 68P 50V J NPO 0402) 2011/12/05 EVT2 2012/01/05 DVT 2012/01/05 DVT DVT 10 add boost resistor add Charger boost resistor 0.2 38 11 add boost resistor add 3V5V boost resistor 0.2 39 Change PR73 and PR74 to SD013220B80(S RES 1/10W 2.2 +-5% 0603) 2012/01/05 2012/01/05 DVT 2012/01/05 DVT Change PR48 to SD013220B80(S RES 1/10W 2.2 +-5% 0603) B B 12 add boost resistor add CPU and GFX boost resistor 0.2 43 Change PR194 and PR206 to SD013220B80(S RES 1/10W 2.2 +-5% 0603) 13 Change main source Change main source for reduce component kind 0.2 39 Change PL7 to SH00000MB00(S COIL 4.7UH +-20% FDSD0630-H-4R7M=P3 5.5A (7*7*3)) Adjust Jack_TEMP resistor Adjust Jack_TEMP resistor, because PCCP change thermistor to 0603 size(TSM1A104F4361RZ) 0.2 37 change PR30 to SD034442280(S RES 1/16W 44.2K +-1% 0402) change PR37 to SD034215280(S RES 1/16W 21.5K +-1% 0402) 2012/01/05 DVT Add ADP_ID circuit Add ADP_ID circuit(65W) 0.2 36 Add PR23 to SD028000080(S RES 1/16W 0 +-5% 0402) change PR16 to SD034270280(S RES 1/16W 27K +-1% 0402) Add PC142 to SE074102K80(S CER CAP 1000P 50V K X7R 0402) 2012/01/05 DVT 2012/01/31 DVT 14 15 16 Change main source Change main source for 不不不不不 with HW change PQ7,PQ26,PQ15,PQ27,PQ48 from SB000009Q80 to SB000009610(S TR SSM3K7002FU 1N SC70-3) 0.2 A A 17 2012/4/6 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2013/4/6 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PIR (PWR) Rev 1.0 Q3ZMC M/B LA-8481P Schematic Date: 5 4 3 2 Thursday, April 12, 2012 Sheet 1 48 of 51 5 4 3 2 Version change list (P.I.R. List) Item D 18 Fixed Issue Del ADP_ID circuit Page 2 of 2 for PWR Reason for change Acer will change adapter type to so del ADP_ID circuit. 音音音 from PoGo, Rev. PG# 0.3 36 19 20 Del jack_temp circuit 1 音音音 from PoGo, Acer will change adapter type to so del jack_temp protect circuit. 0.3 37 21 SPOK change to EC_SPOK For reduce power consumption of DS3, so close +VSB power in DS3, DS4, DS5. 0.3 37 22 change VCCSA IC version SY8037C IC version change to SY8037D for accord with intel VCCSA spec. 0.3 42 23 Add snubber Add snubber of GFX by hw request. 0.3 43 Modify List Del Del Del Del Del Del Del Date PU1 SA003310280 (S IC LMV331IDCKRG4 SC70 5P COMPARATORS) PQ27 SB000009Q80(S TR 2N7002KW 1N SOT323-3) PR13 SD034100280(S RES 1/16W 10K +-1% 0402) PR14 SD034100380(S RES 1/16W 100K +-1% 0402) PR23 to SD028000080(S RES 1/16W 0 +-5% 0402) PR16 to SD034270280(S RES 1/16W 27K +-1% 0402) PC142 to SE074102K80(S CER CAP 1000P 50V K X7R 0402) Phase 2012/03/13 PVT D Del PU3 SA00003K300 (S IC G718TM1U SOT23 8P OTP) Del PR30 to SD034442280(S RES 1/16W 44.2K +-1% 0402) Del PR35 SD034953180(S RES 1/16W 9.53K +-1% 0402) Del PR37 to SD034215280(S RES 1/16W 21.5K +-1% 0402) Add PC17 SE076104K80(S CER CAP .1U 16V K X7R 0402) Change PR29 to SD00000AJ80(S RES 1/16W 12.4K +-1% 0402) Del PR28 SD034100380(S RES 1/16W 100K +-1% 0402) Del PR34 SD028100180(S RES 1/16W 1K +-5% 0402) Del PC15 SE000000K80(S CER CAP 1U 6.3V K X5R 0402) 2012/03/13 PVT 2012/03/13 PVT 2012/03/13 PVT 2012/03/13 PVT Change PU10 to SA00005O000(S IC SY8037DDCC DFN 12P PWM) Add PR200 SD001470B80(S RES 1/4W 4.7 +-5% 1206) Add PC190 SE074681K80(S CER CAP 680P 50V K X7R 0402) C C 24 Add MOTOR POWER HW change motor power solution to PWM. 0.3 45 0.3 37 25 26 27 28 Adjust HW throttling point Because thunder bolt adapter is 40W, OCP 130% adjust HW throttling to 125% 50W recover point 38W Add Add Add Add Add Add Add Add Add Add Add Add Add Add Add Add Add Add Add PU17 SA00005NY00(S IC MP2334DD-LF-Z QFN 12P PWM) PL28 SH00000N000(S COIL 2.2UH +-20% 1231AS-H-2R2M=P3 1.9A) PC366 SE00000OU00(S CER CAP 1U 16V K X5R 0402) PC367 SE074471K80(S CER CAP 470P 50V K X7R 0402) PC368 SE075103K80(S CER CAP .01U 25V K X7R 0402) PC369, PC371 SE00000MA00(S CER CAP 4.7U 10V K X5R 0603) PC372 SE00000QK00(S CER CAP 10U 25V K X5R 0805 H1.25) PC373 SE068102J80(S CER CAP 1000P 25V J NPO 0402) PC375, PC376 SE00000G880(S CER CAP 0.1U 25V K X5R 0402) PR296 SD034300380(S RES 1/16W 300K +-1% 0402) PR297 SD034120280(S RES 1/16W 12K +-1% 0402) PR298 SD028100A00(S RES 1/16W 10 +-5% 0402) PR300 SD034432380(S RES 1/16W 432K +-1% 0402) PR301 SD000000680(S RES 1/16W 8.45K +-1% 0402) PR302, PR307, PR308 SD028100380(S RES 1/16W 100K +-5% 0402) PR303 SD000002300(S RES 1/16W 7.68K +-1% 0402) PR304 SD034576180(S RES 1/16W 5.76K +-1% 0402) PR299, PR305, PR306 SD028100280(S RES 1/16W 10K +-5% 0402) PQ49 SB00000DH00(S TR DMN66D0LDW-7 2N SOT363-6) Change PR33 to SD034165180(S RES 1/16W 1.65K +-1% 0402) 2012/03/13 PVT 2012/03/13 PVT B B 29 30 31 32 33 A A 34 2012/4/6 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification Deciphered Date 2013/4/6 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PIR (PWR) Rev 1.0 Q3ZMC M/B LA-8481P Schematic Date: 5 4 3 2 Thursday, April 12, 2012 Sheet 1 49 of 51 5 4 3 2 Version Change List ( P. I. R. List ) Item Page# D Title Date Request Owner 0919(In Layout) 1.Update R,C 0201,0402,0603,0805,1206 PCB footprint to small size 2.Swap DDR Data BUS 0921 1.TB chip:U66 footprint add "-NH" for Non HDI 2.1.8p_0402:C402,C404 change to 75ohm_0402:R263,R264 0922 1.Change C1457,C1505 form 1.8P 0402 to 0201:SE00000HB80 2.Del DDR CHA,B no use CLK1,CLK1# circuit 3.Change C606,C607 from D2 330uF to B2 330uF 2.5V ESR 15mohm:SGA00004400 4.Swap total KB connector:JKB1 pin define 0923 1.Add DS3 function:SUSWARN#,SUSACK#,EC_DRAMRST_GATE 2.Add Motor function:Motor_IN1,Motor_IN2,Motor_IN3,Motor_IN4, Door_Det_L,Button: KSI0 & KSO10 3.Remove PCH NCTF test point 4.HDMI Fuse:F1 change to P5WS5 use footprint:F_1812 5.Remove HDMI common mode choke:L36,L38,L39,L40 6.Change 0.1uF_0402_16V7K to 0.1uF_0201_10V6K:SE00000SV00 =>C521,C520,C526,C449,C523,C537,C541,C494,C495,C490,C497,C771,C522,C471,C473 7.Change 0.01uF_0402_16V7K to 0.01uF_0201_10V7K:SE172103K80 =>C425,C462 8.Change C751,C752 to B2 220uF 2.5V ESR 15mohm:SGA00004500 0924 1.Make MB to Audio/B connector pin define 2.Change RP 8.2K:R256,R262,R276,R386 to 8.2K_0402 3.Change RP 10K:R386 to 10K_0402 4.Update TB schematic p.24,25,27 5.Change Q64,Q68 from AO3419L:SB000006R10 to AP2301GN-HF:SB000007H10 6.Integration of all 2N7002 SOT23 parts to SSM3K7002F_SC59-3:SB000009080 =>Q74,Q20,Q1,Q2,Q32,Q16,Q17,Q14,Q37,Q7,Q21,Q23,Q24,Q5,Q34,Q29,Q60,Q66,Q67,Q72 Not yet=>Q6,Q78,Q79 B Page 1 Issue Description 0920 1.Change U74,U21,U22 mos to 3*3 thermal pad package:SB00000GW00 C 1 0925 1.Delete LVDS function,Combine eDP,Card Reader function to JLVDS1 Remove:R259,R260,R285,R286,R156,R157,TXCLK+-,TX0+1,TX1+-,TX2+-,DDC CLK,DATA Remove:C462,C425,C412,L20,only place PU:R271,R272,PD:R270,R280 2.Change all SSM3K7002F_SC59-3:SB000009080 to SSM37K002FU_SC70-3:SB000009610 =>Q74,Q20,Q1,Q2,Q32,Q16,Q17,Q14,Q37,Q7,Q21,Q23,Q24,Q5,Q34,Q29,Q60,Q66,Q67,Q72 Not yet=>Q6,Q78,Q79 3.Change 10U_0805_6.3V6M:SE093106M80 to 10U_0603_6.3V6M:SE000005T80 =>C754,C543,C418,C465 4.Remove 0_0603_5%:R416,R421,R426,R327 0926 1.Change HDMI level shift Q16,Q17 to DMN66D0LDW-7_SOT363-6:SB00000DH00 2.Modify TB schematic 0402 cap to 0201 0927 1.Remove J7 2.Change C599 330U D2 2V ESR 9mohm to 330U B2 2.5V ESR 15mohm:SGA00004400 3.Change EC +3VALW_EC 0.1U_0402_16V4Z to 0.1U_0201_10V6K:SE00000SV00 =>C1198,C1199,C1200,C1201,C1204 1000P_0402_50V7K to 1000P_0201_16V7K:SE000007U80 =>C1202,C1203 4.Remove R329 5.Change C751,C752 to 22U_0805_6.3V6M:SE000000I10 6.Remove J4(one of +1.05VS_VTT to +1.05VS_PCH jumper) 0928 1.Change 2.Remove 3.Change 4.Change 5.Remove Solution Description RTC cap from 1U 0603 to 1U 0402:C502,C516 FAN some parts:R753,C788,D51,D52 USB connector foot print to TAIWI_USB005-107CRL-TW_10P-T C196,C387,C735,C102 to 0.1uF_0201_10V6K:SE00000SV00 L2 0929 1.Remove C510,C511 2.Remove Camera Choke:L7,R13,R14 3.Q1,Q2 change to DMN66D0LDW-7_SOT363-6:SB00000DH00 4.R273,R394 change from 0_0603 to 0_0402 5.Remove Step Motor SW1 6.Change LED/B connector from 8 pin to 4 pin 7.Change Jumper from 43*118 to 43*79 =>J2,J8,J10,J11 Rev. 1013 1.Add Step Motor circuit 2.On Board iSSD:i100 change to mSATA SSD 3.WLAN change to on board:MD225 4.Change Card Reader PCIE from Port4 to Port1 CLK from Port5 to Port4 5.Change mSATA SATA port from Port1 to Port0 6.Add USB port 12 for mSATA 7.Remove D11,D12 and C357,C358 (HDMI RF request) 8.C396,C324 change to 0201 9.Remove C472 for +5VALW source cap D 1014 1.Remove DPST_PWM buffer:U13,R783,R85 2.Change +3VS_FULL cap:C475,C466 from 0.1uF_0402 to 0201 3.Change SATA cap:C621,C622,C623,C624 from 0.01uF_0402 to 0201 0930 1.Remove +VCCSA cap:C1182,C1183 2.Remove +USB3_VCCA cap:C390 3.Change C427,C428 to 0.1U_0201_10V6K 4.Add ESD diode:D6 for TP SMBUS 5.Change L65 to 220ohm 3A 0805 6.Swap DDR ChB Data,DQS# 6,7 7.Change U12 mos to 3*3 thermal pad package:SB00000GW00 8.Remove X2,C1361,C1362 9.C378+C375 change to 10uF*1 10.C460+C459 change to 10uF*1 11.Remove C986,C987,C989,C990 =>Add 1uF 0201*10 1017 1.Add power source of +VCCAFDI_VRM at P.20 2.Update DS3,AOAC control signal connected to EC 1018~1021 C 1024 1.Remove R130 2.Define DRAM ID 3.Update TB schematic 4.Swap USB2.0 ESD pin 5.Add on/off BTN for debug 1003 1.Change EC side GPIO:PWR_LED to PWR_LED#,Remove Q32,R512 2.For separate coaxial and wire,update eDP MB connector pin define 3.Remove JLED1 connector 4.Change C427:0.1U_0402_16V4Z to 0.1U_0201_10V6K:SE00000VS00 1005 1.Swap DDR ChB Data,DQS# 6,7 2.Change PCH PCIE 0.1U_0402_16V7K to 0.1U_0201_10V6K:SE00000SV00 =>C572,C573,C617,C618,C681,C682,C683,C684,C685,C686,C687,C688 2.Change eDP cap from 0.1U_0402_16V7K to 0.1U_0201_10V6K:SE00000SV00 =>C910,C911,C912,C913,C914,C915 3.Add R80:0ohm of H_CPU_PWRGD for ESD request 4.Remove On Board WLAN:MD225 5.Add Motor parts(Not Ready) 6.Add iSSD i100 parts(Not Ready) 1027 1.Swap JTP1 pin for new module 2.Gerber schematic 1028 For Load 1.Update 2.Update 3.Update BOM Block Diagram CPU,PCH part number BOM config 整整整 1101 1.For 2.Combine PWR schematic 3.A test SMT schematic B 1006 1.Change R754,R751 0ohm from 0603 to 0402 2.Change C484 0.1U from 0603 to 0402 3.For DS3,Change power source from +3VALW_PCH to +VCCSUS3_3 4.Change R629 from 0_0805 to 0_0402 5.Change SATA cap from 0.1U_0402_16V7K to 0.01U_0201_10V7K =>C621~C628 1010 1.Add BATT_RST#,VR_LEFT,VR_RIGHT pin 2.Add iSSD i100 128GB*2 schematic 3.Add USB_HPD# pin 1011 1.Add Battery Reset function 2.Swap USB2.0,3.0 choke for connector side 順順 A A Compal Secret Data Security Classification Issued Date 2012/4/6 2013/4/6 Deciphered Date Title Compal Electronics, Inc. EE P.I.R THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 Q3ZMC M/B LA-8481P Schematic Date: 5 4 3 2 Thursday, April 12, 2012 Sheet 1 50 of 51 5 4 3 2 Version Change List ( P. I. R. List ) Item Page# D C B Title Date Request Owner 0108(DVT) 1.For DS3,change P.18 PCH power source from +3VALW_PCH to +VCCSUS3_3 (R422,R657,R391,R397,R458) 2.Change TB_CLKREQ#_R power source from +3VS_POC to +3VS_LC (Q67,R1031) 3.Change Q67 direction 4.Change TB_SMB_DA,TB_SMB_CLK from PH +3VS_LC(R1036,R1037) to PL(R1046,R1047) 5.Change Q71 +3VS_LC enable pin from EN_LC_PWR to 1.05VS_LC_PG 6.Change R1110 from 348K_0402_1% to 35.7K_0402_1% 7.Change TB_GO2SX from PL to PH +3VS_POC(R1066) 8.Add TCM (U8) package into board file 9.For EC_PME#,R490 change to pop 10.For Motor BTN,R974 change to pop 11.Add MSATA RAID0 function (C625,C627,C626,C628) 12.Add PCH:GPIO35 to RAID0_DET,external pull down(R329) 13.Change TP from 6 pin to 8 pin,Add level shift Q9 14.Combine Q66,Q67 to Q89 dual package 15.For DS3,Add EC.82 ACPRESENT to PCH_ACIN(pop R456,unpop D19) 16.For eDP only,PCH_GPIO71 change from PL to NC(unpop R618) 17.For Motor VR,change from PH to PL 100K(R454,R455) 0113 1.Remove mSATA USB port12 2.For ESD request,Reserve 0.1uf for FAN_SPEED1,FAN_PWM (C451,C450) 0117 (Final Schematic for Gerber) 1.Add Q30,Q31 for "LED" TB cable 2.Add MD222 BT_LED test point:T74 3.Add test point T75,T76,T77,T78,T79,T80 for TB boundary scan 0120 1.Unpop Power BTN(SW1) 2.For change BID from 0 to 1,pop R957:8.2K 3.For DS3,S3,Change R418 BOM config from S3@ to normal 0131 1.For ,Change C394,C1000 from SGA00001E00 to SGA00002N80 2.For ,Change C599,C607 main source:SGA00004700,2nd source:SGA00004400 3.For ,Change C1484,C1464 main source from SGA20331E10 to SGA19331D10 4.For Vendor Report, Change Y1,Y2 from SJ10000DJ00:25MHZ 20PF +-30PPM 7V25000016 to SJ10000E800:25MHZ 10PF +-20PPM 7V25000014 Change C744,C745 form 27pf to 10pf Change C1338,C1340 from 20pf to 6.8pf 5.For cost,C496,C478 change to unpop 6.For cost,Change C505 from 1uF 0201 to 0.1uF 0201 7.For cost,Change C993,C992,C1009,C994,C1006,C1008,C1007,C1010,C986,C1002 from 1uF 0201 to 0.1uF 0201 8.For ESD request,pop 1000pf for FAN_SPEED1,FAN_PWM (C451,C450) and Unpop C579 1000p of FAN_SPEED1 9.For IOAC power control by EC,pop Q47 缺 缺缺 統 統統 統缺 A Page 2 Issue Description 1201(EVT2 Gerber) 1.Modify EVT1 SMT memo into Schematic 2.Add 1U_0201_4V_6M *4(C1511,C1512,C1513,C1514) for ChA 3.Add 1U_0201_4V_6M *4(C1515,C1516,C1517,C1518) for ChB 4.Delete ChA,ChB SPD ROM(U70,U72) circuit 5.JLVDS.15 change from VR_LEFT to GND 6.TB,pull high PCH_DPD_CLK,PCH_DPD_DAT to +3VS(R252,R254) 7.TB,add Buffer:U3 EN pin pull down resistor:R1075 8.TB,Change R1067 pull down form PA_LSRX_LSOE1_R to PA_LSRX_LSOE1_U 9.WLAN,Modify PCIE TX,RX,change P/N of RX signal 10.WL_OFF# connected to EC_Pin71 BT_ON# connected to EC_Pin117 11.mSATA,+3VS_FULL:Change C455 to 4.7U_0603_6.3V_6K,+1.5VS:Delete C433 12.Update Motor circuit,P.30 13.Add TPM/TCM co-layout circuit,P.30 14.USB PWR SW IC enable pin co-lay SYSON# and USB_EN#_R(EC_Pin81) 15.EC,P.32 (1)power source co-lay +3VALW/+3VLP (2)DC mode S4/S5 turn on +3VALW,+5VALW for Motor, MOTOR_BTN(EC_Pin17) (3)PPS_L connected to MOTOR_PPS_L(EC_Pin85) (4)PPS_R connected to MOTOR_PPS_R(EC_Pin91) (5)Turn on/off Motor +5VALW connected to MOTOR_PWR_ON(EC_Pin21) (6)Audio/B add Motor LED connected to MOTOR_LED#(EC_Pin36) (7)BI_DET changed to EC_Pin25 (8)Adapter ID pin connected to ADP_ID(EC_Pin64) 16.Update JAUDIO connector type and pin define,P.33 17.Add Motor BTN circuit,P.33 1207 1.PCH_ACIN pull high R341 Change from 200K to 10K 1 Solution Description 0303 (PVT) Modify DVT SMT memo for BOM 1.C744,C745 change from 10P 25V J NPO 0402:SE00000F180 to 10P 50V J NPO 0402:SE071100J80 2.For INTEL TB review,pop R1036,R1037,R1048,unpop R1046,R1047,R1066 3.TB,C1424,C1425 change from SE000000K80:1U_0402_6.3V6K to SE076104K80:.1U_0402_16V7K 4.For USB enable pin change from SYSON#:R952 to USB_EN#:R951 Modify PVT layout 0.Remove on/off# BTN SW1 footprint 1.Change BT port from Port13 to Port8 2.Remove TCM parts:U8,R964,R965,C12,C1225 3.Remove EC 930 SPI ROM:U38,R694,R690,R698,R705,R692,C722,R695,C727 4.Remove SUS_PWR_DN_ACK for S3:EC U53.19,R409,R411 5.Update JLVDS1 pin define for +3VALW short issue 6.Add JLED1 connector 7.Remove JMT1,JMT2,JRTC1 and Change to JMR1 8pin conn. 8.Add EC U53.19:IRST_RST# (R461) to U26.1 for IOAC+IRST issue 9.Change 0ohm to 0ohm_short:R80,R314,R320,R372,R382,R394,R412,R421, R577,R578,R579,R581,R582,R612,R629,R661,R785,R940,R947,R953,R956, R959,R967,R973,R974 10.For WLAN issue,Change PCH_PCIE_WAKE#_R(EC_PME#) pull high from +3VALW to +3VS_WLAN.Add R962,Remove R943 11.Change Motor Power source from PMOS to NMOS Remove:R452,R453,Q69,C818,R754,J14 Add:U23,Q90,R459,C472,C503,C504,C481,R460 12.Remove net :ADP_ID 13.For TB ref. design,Add dual PMOS Q91,Q92,NMOS Q32,R1124 0306 14.Add DPWROK PL:R463 for INTEL suggestion 15.Remove JP1 EC debug port 16.Remove MDP_HPD ESD:D45 17.Add H11:H_4P0N for eDP connector 18.Add EC_SPOK(U53.120) to control +VSBP 19.add BT_LED U53.119 control pin,R492 20.add TB_FORCE_PWR:R1097 to PCH_GPIO12 21.Add WLAN discharge circuit:Q62B,R473=>Remove 22.For ACER TB request,add PH R1125 to +3VS_POC 0308 23.Remove ME RST# 0ohm:R561 24.Add C785,C786,C787,C788,C789 for ESD request 25.Add Q69 group(Q69,Q62B,R452,R453,R754,C818,R474,C540) for +3V_MCU 26.Change +3VS_FULL:J8 from 43*79 to 43*39 0309 27.Change Q62 dual 2N7002 to normal 2N7002 28.Add IRST_RST# PH:R965 to +3VALW_EC 29.Motor +3V_MCU design: Delete PMOS:Q69 group(Q69,Q62B,R452,R453,R754,C818,R474,C540) Add NMOS:Q87 group(Q87,Q93,R21,R789,C811) 漏漏 Rev. 0402 Modify for 1.0 layout 1.Add soft start R756,C819 of Q68:+VCCSUS3_3 and R757,C820 of Q64:+V5REF_SUS 2.Add TB GPIO7(R1129) to PCH GPIO49,GPIO6(R1128) to PCH GPIO20 3.Add TB wake# colay:R1098 to U53.64(EC GPIO49),PH R976 to +3VALW_EC 4.Add TB +3VS_POC jumper colay +3VS(J4) and +3VALW(J2) 5.Delete colay J13(+3VALW to +VCCSUS3_3),R751(+5VALW to +V5REF_SUS) 6.Add C1519:10U_0603 for +0.675VS 7.Change C1468,C1471,C1476,C1477,C1478,C1491,C1492,C1499 from 0.1U_0201_10V6K to 1U_0402_6.3V6K 8.Add R277,R1109 for MOS Vgs(th) reserve. 9.Change Motor BTN SW:R974 from 0ohm_short to normal 0ohm 10.Add C790,C791 of VGATE for ESD team 11.Reduce Jumper size from 43*118 to 43*79:PJ17,PJ7,J3 Change Jumper sixe from 43*118(PJ1) to 43*79(PJ1)+43*39(PJ8) Change Jumper sixe from 43*118(PJ2) to 43*79(PJ2)+43*39(PJ10) D 0411 Modify for PreMP SMT update PVT SMT memo 1.Add C787:100P_0201_25V8J for PM_DRAM_PWRGD 2.Add C785:100P_0201_25V8J and C786:100P_0402_50V8J for DIMM_DRAMRST# 3.Add C788:100P_0402_50V8J for SM_DRAMRST# 4.Add C789:100P_0402_50V8J for SYS_PWROK 5.For TB GPIO6,GPIO7,change PH to PL,unpop R1036,R1037,pop R1046,R1047 6.Delete Q65 for TB GPIO6,GPIO7 7.Add TB_FORCE_PWR_R to PCH,pop R1097,unpop PH:R657 at PCH side 8.For TB_PLUG_EVENT,unpop PCH side PH:R406 update for PreMP 1.Add C790:100P_0402_50V8J,C791:100P_0201_25V8J for VGATE 2.Change Board ID to "4" for 1.0=>R960:56K 3.Change PCH from SA00005AG00:HM77 QPRG to MP version SA00005AGI0:HM77 SLJ8C 4.TB chip change to MP version:NA 5.Change LA8481P from DA6:DAA00003N00 to DAZ:DAZ0NS00100 6.Change Y1:25MHz cap:C744,C745 from 10P to 8.2P_0402_50V8D 7.For VR,change R454,R455 from 100K_5% to 100K_1% 8.Add C1261,C1291 2.2U_0603_6.3V6K for DDR Memory test issue 9.Change C1504,C1501,C1517,C1503,C1511,C1460,C1462,C1514 from 0.1uF 0201 to 1uF 0201 10.Change TB R1083,R1078,R1089,R1080,R1081,R1082,R1088,R1086 from 12.1ohm to 0ohm,R1086 change to @ C 0412 Modify for 1A layout 11.For Motor_BTN,add PH:R909 to +3VLP 12.Remove EC_TB_WAKE#:R1098 13.For LEGO,Change control pin from PCH to EC (1)LED:PCH_GPIO34 change to EC_GPIO122(TB_LED) (2)Eject:PCH_GPIO48 change to EC_GPIO64,pop R976(TB_EJECT_BTN) (3)pop Q30,Q31,R1125,unpop R1056,R1057 B 0312 Modify for PVT SMT 1.For EC_SMI#,R939 change to @ 2.For PCH_ACIN,R341 change to @ 3.For ACER only,TPM change from SA00005EG00 to SA00005PH00 4.Change SPOK control function from PWR to EC_SPOK 5.Change HDMI cap form SE076103K80:0.01u to SE076104K80:0.1u:C280~C287 6.Change Board ID form 1 to 2,R960 chnage to 18K_0402_5% 7.For Vgs(th) issue,change Q20 from 2N7002 to BSS138(SB000002X00) 8.For Q5LJ1 RTC issue, change X1 from SJ10000DM00:S CRYSTAL 32.768KHZ 12.5PF 9H03200019 to SJ100004Z00:S CRYSTAL 32.768K 12.5PF 1TJF125DP1A000D 9.Remove KB cap 100P_0201*24pcs C245,C246,C247,C248,C249,C250,C251,C252,C253,C254,C255,C256,C258,C259, C260,C263,C265,C266,C267,C268,C269,C270,C271,C272 10.For ME PE review,remove C442 11.For cost,Change DDR C1464 to @ 12.For cost,Change DDR C1258,C1259,C1261,C1291,C1292,C1293 to @ 13.For cost,Change DDR cap from 1uF_0201 to 0.1uF_0201 C1462,C1461,C1460,C1459,C1514,C1513,C1512,C1511, C1466,C1476,C1477,C1467,C1470,C1471,C1478,C1468 C1504,C1503,C1502,C1501, C1518,C1517,C1516,C1515, C1487,C1497,C1498,C1488,C1491,C1492,C1499,C1489 14.For cost,Change TB C1406,C1407,C1443,C1444 from 1uF_0201 to 0.1uF_0201 0314 15.For HF parts,change Q6 from SB501380020 to SB501380050 16.For HF parts,change Q87 from SB534560020 to SB534560030 0315 17.Combine Power latest schematic Compal Secret Data Security Classification Issued Date A 2012/4/6 2013/4/6 Deciphered Date Title Compal Electronics, Inc. EE P.I.R THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev 1.0 Q3ZMC M/B LA-8481P Schematic Date: 5 4 3 2 Thursday, April 12, 2012 Sheet 1 51 of 51 www.s-manuals.com
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.4 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Create Date : 2012:04:13 10:38:19Z Creator Tool : PScript5.dll Version 5.2.2 Modify Date : 2014:10:13 22:03:28+03:00 Metadata Date : 2014:10:13 22:03:28+03:00 Format : application/pdf Creator : Title : Compal LA-8481P - Schematics. www.s-manuals.com. Subject : Compal LA-8481P - Schematics. www.s-manuals.com. Producer : GPL Ghostscript 8.15 Document ID : uuid:12f5b453-cb82-4658-8f3d-d235247b13c7 Instance ID : uuid:e4a41b4b-c5bf-449e-a358-e0845e9ce9b0 Page Count : 52 Keywords : Compal, LA-8481P, -, Schematics., www.s-manuals.com. Warning : [Minor] Ignored duplicate Info dictionaryEXIF Metadata provided by EXIF.tools