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Compal Confidential
1

Model Name : Q1VZC
File Name :LA-8943P
BOM P/N:43

ZZZ1

ZZZ2

ZZZ3

ZZZ4

ZZZ5
1

LA-8943P
DA2@

PCB
DAZ@

LS-8941P
DA2@

LS-8942P
DA2@

LS-8943P
DA2@

Compal Confidential
2

2

CHROME M/B Schematics Document
Intel Sandy Bridge ULV Processor + Panther Point PCH

2012-08-10

3

3

REV:1.0

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

2013/03/21

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Cover Page
Rev
0.1

CHROME M/B LA-8943P Schematic

Date:

A

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Friday, August 10, 2012

Sheet
E

1

of

45

A

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E

Compal Confidential
Model Name : Q1VZC
File Name :LA-8943P
Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2

1

Intel
Sandy Bridge ULV

BANK 0, 1, 2, 3

Dual Channel

1

page 11,12

1.5V DDRIII 1066/1333

Processor
BGA1023
17W

eDP(UMA)

page 4~10

FDI x8
CRT Conn
page 24

HDMI Conn.

LVDS/eDP Conn.

page 23

CLK=100MHz

page 22

2

DMI x4
CLK=100MHz

USB 2.0
conn x1(Option for USB3.0)
page 34

2.5GB/s x4

2.7GT/s

TMDS(UMA)
RGB(UMA)

Intel
HD Audio
3.3V 24MHz

Port 10

2

Port 8

Broadcom
57785page

MINI Card
WLAN

25

page 36

Port 3
PCI-Express x 8
(PCIE2.0 5GT/s) 100MHz

PCH

page 22

Port 2,3

LAN(GbE)/CardReader

Panther Point-M

CMOS
Camera

page 30

Port 1

USBx14
3.3V 48MHz

LVDS(UMA)

USB 2.0
conn x2

Port 2

SPI
SATA x 6 (GEN2 3.0GT/S ,GEN3 6GT/S)

HDA Codec

100MHz

ALC271X-VB6
page 31

989pin BGA

SM Bus

page 13~21
3

Int. Speaker
page 31

SPI ROM x1
page 13

Touch Pad

LPC BUS

page 30

CLK=33MHz

ENE
KB932page

RTC CKT.

GEN3

Port 0

SATA HDD
Conn.

3

page 24

LS-8941P
LED/B
page 30

29

page 13

LS-8942P
IO/B
page 28

Power On/Off CKT.
SPI ROM x1

page 36

Int.KBD

page 29

4

page 30

TPM
LS-8943P

page 30

HDD/B

DC/DC Interface CKT.

page 24

4

page 33

A

2012/03/21

Issued Date

page 34~43

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Power Circuit DC/DC

Deciphered Date

2013/03/21

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C

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Title

Block Diagrams

Size
Document Number
Custom

CHROME M/B LA-8943P Schematic

Date:

Sheet

Friday, August 10, 2012
E

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SIGNAL

STATE

Voltage Rails
Power Plane

1

Full ON
Description

S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

BATT+

Battery power supply (12.6V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

+VGFX_CORE

Core voltage for UMA graphic

ON

OFF

OFF

HIGH

HIGH

HIGH

ON

ON

ON

ON

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

1

Board ID / SKU ID Table for AD channel

ON

OFF

OFF

ON

OFF

OFF

+1.5V

+1.5VP to +1.5V power rail for DDRIII

ON

ON

OFF

Vcc
Ra/Rc/Re

+1.5VS

+1.5V to +1.5VS switched power rail

ON

OFF

OFF

Board ID

+1.8VS

(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU

ON

OFF

OFF
ON

0
1
2
3
4
5
6
7

ON

ON

ON

ON

OFF

+3VS

+3VALW to +3VS power rail

ON

OFF

OFF
ON

+5VALW

+5VALWP to +5VALW power rail

ON

ON

+5VREF_SUS

+5VALW to +5VREF_SUS power rail for PCH (Short resister)

ON

ON

OFF

+5VS

+5VALW to +5VS switched power rail

ON

OFF

OFF

+VSB

+VSBP to +VSB always on power rail for sequence control

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

Clock

HIGH

+0.75VP to +0.75VS switched power rail for DDR terminator

+3VALW always on power rail

+VS

LOW

+1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU

+3VALW to +VCCSUS3_3 power rail for PCH (Short Jump)

+V

HIGH

+0.75VS

+3VALW

+VALW

S1(Power On Suspend)

+1.05VS_VTT

+VCCSUS3_3

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

E

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

BOARD ID Table

2

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address
Device

Address

Smart Battery

0001 011X b

PCH SM Bus address
Device
ChannelA
ChannelB

A0
B0

1010 000X
1010 010X

2

BTO Option Table

PCB Revision
0.1

BTO Item
BOM Structure
Celeron 867
C867@
Celeron 877
C877@
Unpop
@
EDP@
eDP Panel
LVDS Panel
LVDS@
Connector
CONN@
USB3 Only
USB3@
Deep S3
DS3@
Normal S3
S3@
Intel i5/i7 CPU only I57@
Celeron/Pentium/i3
CP3@
CPU only

USB Port Table
USB 2.0 USB 1.1 Port

Address
DIMM0
DIMM0

Board ID
0
1
2
3
4
5
6
7

JDIMM1(STD)
JDIMM2(REV)

UHCI0

3

UHCI1
EHCI1
UHCI2
UHCI3
UHCI4
EHCI2

UHCI5
UHCI6

0
1
2
3
4
5
6
7
8
9
10
11
12
13

3 External
USB Port
USB 2.0(Options for USB3.0)
USB port(Left 2.0)
USB Port(Left 2.0)

3

USB 3.0 Port
1
2
XHCI
3
4

Mini Card(WLAN)
Camera

USB Port(Right 3.0)

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

2013/03/21

Deciphered Date

Title

Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Wednesday, August 15, 2012

Sheet
E

3

of

45

Rev
0.1

A

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E

1

+1.05VS_VTT

R1
24.9_0402_1%
UCPU1A
1

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

<15>
<15>
<15>
<15>

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

<15>
<15>
<15>
<15>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

U6
W10
W3
AA7
W7
T4
AA3
AC8

<15>
<15>

FDI_FSYNC0
FDI_FSYNC1

<15>

FDI_INT

1

U7
W11
W1
AA6
W6
V4
Y2
AC9

FDI_LSYNC0
FDI_LSYNC1

2

EDP_HPD#

U11
AA10
AG8

EDP_AUXN
EDP_AUXP

<22>
<22>

EDP_TXN0
EDP_TXN1

<22>
<22>

EDP_TXP0
EDP_TXP1

AG4
AF4
AC3
AC4
AE11
AE7

1

<22>
<22>

AF3
AD2
AG11

2

AC1
AA4
AE10
AE6

EDP_HPD#

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC

eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
eDP_AUX#
eDP_AUX
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

eDP

EDP_HPD#

AA11
AC12

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

W=12mil L=500mil S=15mil
EDP_COMP

<22>

K3
M7
P4
T3

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

3

R3
1K_0402_5%
EDP@

K1
M8
N4
R2

<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>

<15>
R2
<15>
24.9_0402_1%

+1.05VS_VTT

N3
P7
P3
P11

PCI EXPRESS -- GRAPHICS

<15>
<15>
<15>
<15>

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

Intel(R) FDI

+1.05VS_VTT

eDP_COMPIO and ICOMPO signals
should be shorted near balls and
routed with typical impedance
<25 mohms
can't be left floating
,even if disable eDP function...

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

DMI

2

<15>
<15>
<15>
<15>

M2
P6
P1
P10

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

G3
G1
G4
H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7
K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

2

W=12mil L=500mil S=15mil

PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms

PEG_COMP

1

C867@

Celeron 867

HR

1.3G

SA00005BH40(S IC AV8062701148901 SR0FK J1 1.3G ABO!)

C877@

Celeron 877

HR

1.4G

SA00005QI10(S IC AV8062701148001 QB35 J1 1.4G ABO!)

UCPU1

UCPU1

AV8062701148001
C877@

AV8062700852800
C847@

SA00005QI10

SA00005VK20
2

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4
F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

3

IVY-BRIDGE_BGA1023
C867@

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

Issued Date

Deciphered Date

2013/03/21

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size
Document Number
Custom

CHROME M/B LA-8943P Schematic

Date:

Friday, August 10, 2012

Sheet
E

4

of

45

Rev
0.1

A

B

C

D

E

0921 LVDS@->@

+1.05VS_VTT

CLK_CPU_DPLL#

R4

2 LVDS@ 1 1K_0402_5%

CLK_CPU_DPLL

R5

2 LVDS@ 1 1K_0402_5%

Checklist1.5 P.67 Graphis Disable Guide
eDP disable:
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PU 1K_5% to +1.05VS_VTT

1

1

UCPU1B

偵偵CPU有有有有

Follow DG 1.5& Tacoma_Fall2 1.0
XBOX

reserve
2

C65

1 0.1U_0402_16V4Z

三三三三

T1

PAD @

H_CATERR#

C49

H_PECI

A48

1 10K_0402_5%

+1.05VS_VTT
<29,35>

R7

2

<18,29>

H_PECI

1 62_0402_5%

R8
56_0402_5%
1
2

H_PROCHOT#

H_PROCHOT#

H_PROCHOT#_R

2

<18>

Buffered reset to CPU

+3VS

2

5
P

3

A

PROCHOT#

<15>

C48

H_PM_SYNC

BUFO_CPU_RST#

R15
43_0402_1%
1
2

<18>

1

H_CPUPW RGD

BUF_CPU_RST#

R13

2 H_CPUPW RGD_R
0_0402_5%

非CORE外外外OK

B46

PM_SYNC

UNCOREPWRGOOD

UNCOREPWRGOOD:

PM_DRAM_PW RGD_R

BE45

SM_DRAMPWROK

SN74LVC1G07DCKR_SC70-5

SM_DRAMPWROK:DRAM power ok

都ok後後CPU做reset

BUF_CPU_RST#

RESET#:

Follow DG 1.5 & Tacoma_Fall2 1.0
+3VALW

3

1

R16
200_0402_5%

<15>

1

SYS_PW ROK

2

PM_DRAM_PW RGD

B
A

3

<15>

G VCC

U2

Y

SM_DRAMRST#

4

PM_SYS_PW RGD_BUF

1
R18

CLK_CPU_DPLL <14>
CLK_CPU_DPLL# <14>

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

AT30

SM_DRAMRST#

BF44
BE43
BG43

SM_RCOMP0 R9
SM_RCOMP1 R10
SM_RCOMP2 R11

SM_DRAMRST#

2
2
2

<6>

1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%

DDR3 Compensation Signals

2

RESET#

TDI
TDO

DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

N53
N55
L56
L55
J58

XDP_TCK
@
XDP_TMS
@
XDP_TRST# @

PAD T2
PAD T3
PAD T4

M60
L59

XDP_TDI
XDP_TDO

PAD T5
PAD T6

K58

XDP_DBRESET#

@
@

XDP_DBRESET#

<15,28>

G58
E55
E59
G55
G59
H60
J59
J61
3

C476

1

H_CPUPW RGD_R

+3VS
IVY-BRIDGE_BGA1023
C867@

XDP_DBRESET# R17

12/22 Add(ESD request)

2

1 1K_0402_5%

Tacoma_Fall2 1.0 PU 1K +3VS
Check list 1.5 PU 1K +3VS
Debug port DG1.1-1.3 50~5K ohm

2

5

2

@
2

180P_0402_50V8J

1

C67
0.1U_0402_16V4Z

Use open drain logic gate:
+1.5V_CPU_VDDQ PU pop 200ohm
+1.5V_CPU_VDDQ
series resister pop 130ohm

D44

CLK_CPU_DPLL
CLK_CPU_DPLL#

THERMTRIP#

R12
75_0402_5%

G

2

PLT_RST#

Y

4

PECI

TCK
TMS
TRST#

C66
0.1U_0402_16V4Z

AG3
AG1

SM_RCOMP2
W=15mil L=500mil S=13mil

+1.05VS_VTT

U1

NC

D45

H_THRMTRIP#

CLK_CPU_DMI <14>
CLK_CPU_DMI# <14>

SM_RCOMP0,SM_RCOMP1
W=20mil L=500mil S=13mil

PRDY#
PREQ#

2
R14
0_0402_5%
1
2 1
@

C45

DPLL_REF_CLK
DPLL_REF_CLK#

J3
H2

CATERR#

PWR MANAGEMENT

1

PLT_RST#

PROC_DETECT#

Use open drain logic gate:
+1.05VS_VTT PU pop 75ohm
series resister pop 43ohm

1

Follow DG 1.5 & Tacoma_Fall2 1.0

<17>

PROC_SELECT#

H_CPUPW RGD

follow Checklist 1.5
2

C57

THERMAL

@

R6

F49

H_SNB_IVB#

CLOCKS

<17>

BCLK
BCLK#

DDR3
MISC

外外外

JTAG & BPM

非
都 後後 做

MISC

PROC_SELECT#
PH VCPLL and connect to PCH DF_TVS

PCH->CPU
UNCOREPWRGOOD: CORE
OK
SM_DRAMPWROK:DRAM power ok
CPU reset
RESET#: ok

2
PM_DRAM_PW RGD_R
130_0402_5%

MC74VHC1G09DFT2G_SC70-5

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

Issued Date

Deciphered Date

2013/03/21

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

PROCESSOR(3/7) DDRIII

Size
Document Number
Custom

CHROME M/B LA-8943P Schematic

Date:

Sheet

Friday, August 10, 2012
E

5

of

45

Rev
0.1

A

B

C

D

UCPU1C

UCPU1D
<12>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

1

2

3

<11>
<11>
<11>

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

<11>
<11>
<11>

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

BD37
BF36
BA28

BE39
BD39
AT41

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

AU36
AV36
AY26

DDR_B_D[0..63]
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

SA_CLK_DDR0 <11>
SA_CLK_DDR#0 <11>
DDRA_CKE0_DIMMA <11>

AT40
AU40
BB26

SA_CLK_DDR1 <11>
SA_CLK_DDR#1 <11>
DDRA_CKE1_DIMMA <11>

BB40
BC41

DDRA_CS0_DIMMA#
DDRA_CS1_DIMMA#

AY40
BA41

SA_ODT0
SA_ODT1

<11>
<11>

<11>
<11>

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS#[0..7]

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS[0..7]

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_MA[0..15]

<11>

<11>

<11>

<12>
<12>
<12>

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

<12>
<12>
<12>

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

BG39
BD42
AT22

AV43
BF40
BD45

IVY-BRIDGE_BGA1023
C867@

SB_CLK_DDR0 <12>
SB_CLK_DDR#0 <12>
DDRB_CKE0_DIMMB <12>
1

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

BA36
BB36
BF27

SB_CLK_DDR1 <12>
SB_CLK_DDR#1 <12>
DDRB_CKE1_DIMMB <12>

BE41
BE47

DDRB_CS0_DIMMB#
DDRB_CS1_DIMMB#

AT43
BG47

SB_ODT0
SB_ODT1

<12>
<12>

<12>
<12>

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS#[0..7]

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS[0..7]

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

<12>

2

DDR_B_MA[0..15]

<12>

<12>

3

IVY-BRIDGE_BGA1023
C867@

1

1
DIMM_DRAMRST#_R
Q1
BSS138_NL_SOT23-3

2
R24
0_0402_5%
1
2
DS3@

EC_RST_GATE

2

1

R23
0_0402_5%
1
2
DS3@

RST_GATE

G

4

<29>

BA34
AY34
AR22

2
3

SM_DRAMRST#
R22
4.99K_0402_1%

<14>

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

R20
1K_0402_5%

D

SM_DRAMRST#

S

<5>

R19
0_0402_5%
1
2
@

通通DIMM做reset

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

+1.5V

Follow CRB1.0

CPU

AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60

DDR SYSTEM MEMORY B

DDR_A_D[0..63]

DDR SYSTEM MEMORY A

<11>

E

RST_GATE_R
RST_GATE_R

1

2

C68
0.047U_0402_16V7K

<11,12>

1
R21

2
1K_0402_5%

DIMM_DRAMRST#

<11,12>

S0
DRAMRST_CNTRL_PCH hgih ,MOS ON
SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH
Dimm not reset
S3
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# HIGH
Dimm not reset
S4,5
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# low
Dimm reset

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

2013/03/21

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

Rev
0.1

CHROME M/B LA-8943P Schematic

Date:

A

PROCESSOR(3/7) DDRIII

C

D

Friday, August 10, 2012

Sheet
E

6

of

45

A

B

C

D

E

CFG Straps for Processor
CFG2

PAD @
PAD @

VCC_VAL_SENSE
VSS_VAL_SENSE

H43
K43

T39
T40

PAD @
PAD @

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE

H45
K45

T8

PAD @

F48
H48
K48

2

BA19
AV19
AT21
BB21
BB19
AY21
BA22
AY22
AU19
AU21
BD21
BD22
BD25
BD26
BG22
BE22
BG26
BE26
BF23
BE24

VCC_VAL_SENSE
VSS_VAL_SENSE
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_DIE_SENSE

RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38

2

R25
1K_0402_1%
@

N42
L42
L45
L47

1

PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane # definition matches
socket pin map definition

CFG2

M13
M14
U14
W14
P13

*

0:Lane Reversed

CFG4

AT49
K24

關關

EDP@

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

AH2
AG13
AM14
AM15
N50

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

R28
1K_0402_1%

eDP enable

*

CFG4
A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

啟啟

UMA,Optimus eDP
DISO eDP

1

RSVD39
RSVD40

RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

N59
N58

2

T37
T38

BCLK_ITP
BCLK_ITP#

DC_TEST_C4_D3

DC_TEST_A59_C59

1:Disable
0:Enable

2

CFG6
CFG5

These pins are for solder joint
reliability and non-critical to
function. For BGA only.

1

CFG4
CFG5
CFG6
CFG7

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

R31
1K_0402_1%
@

DC_TEST_A61_C61

R32
1K_0402_1%
@

2

CFG2
1

B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53

1

CFG0

2

PAD @

RESERVED

T7

1

UCPU1E

DC_TEST_BE59_BE61
DC_TEST_BG59_BG61

DC_TEST_BE3_BG3

PCIE Port Bifurcation Straps

DC_TEST_BE1_BG1

11: (Default) 1x16 PCI Express
CFG[6:5]

IVY-BRIDGE_BGA1023
C867@

2x8 PCI Express
*10:
01: Reserved
00: 1x8,2x4 PCI Express

3

3

1

CFG7
R33
1K_0402_1%

2

@

Tacoma_Fall2 1.0 P.12

PEG DEFER TRAINING
CFG7

1: (Default) PEG Train immediately following
xxRESETB de assertion
0: PEG Wait for BIOS for training

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

Issued Date

Deciphered Date

2013/03/21

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

PROCESSOR(4/7) RSVD,CFG

Size
Document Number
Custom

Rev
0.1

CHROME M/B LA-8943P Schematic

Date:

Sheet

Friday, August 10, 2012
E

7

of

45

B

C

UCPU1F

ULV type
DC 33A

D

POWER

8.5A
+1.05VS_VTT

INTEL Recommend VCCIO
2*330UF,10*10uF(0603) and 26*1uF(0402)
PD0.8
CAP at P.51

AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

For PEG

2

+3VS

R34
10K_0402_5%
@

W16
W17

VCCIO_SEL

1

VCCIO_SEL after Ivy bridge ES2 Voltage support

R35
10K_0402_5%
@

BC22
2

VCCIO_SEL

BC22

*

1/NC : (Default) +1.05VS_VTT
0: +1.0VS_VTT

VCCIO_SEL

+1.05VS_VTT

A44
B43
C44

3

Place the PU
resistors close to CPU

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

R38
R39
R40

1
1
1

2 43_0402_1%
2 0_0402_5%
2 0_0402_5%

SVID_ALERT#
<41>
SVID_CLK <41>
SVID_DATA <41>

R44

AN16
AN17

1

1
1

2
2

0_0402_5%
0_0402_5%

2 10_0402_5% +1.05VS_VTT
VCCIO_SENSE

VSSIO_SENSE

VCCSENSE
VSSSENSE

R46
10_0402_5%

Should change to connect form
power cirucit & layout differential
with VCCIO_SENSE.

2

IVY-BRIDGE_BGA1023
C867@

<41>
<41>

R45
100_0402_1%

<40>

1

VCCIO_SENSE
VSS_SENSE_VCCIO

R42
R43

2

F43 VCCSENSE_R
G43 VSSSENSE_R

R41
100_0402_1%

1

VCC_SENSE
VSS_SENSE

1

+CPU_CORE

2

SENSE LINES

R37
75_0402_5%

2

R36
130_0402_5%

1
2
C69
1U_0402_6.3V6K

VIDALERT#
VIDSCLK
VIDSOUT

+1.05VS_VTT

1

AM25
AN22

1

+1.05VS_VTT

VCCPQE[1]
VCCPQE[2]

Place the PU
resistors close to VR

4

1

1

PEG IO AND DDR IO

For DDR

+1.05VS_VTT

VCCIO50
VCCIO51

SVID

3

VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]

QUIET
RAILS

2

CORE SUPPLY

INTEL Recommend VCC
4*470UF,12*22uF(0805) and 35*2.2uF(0402)
PD0.8
CAP at P.51

1

VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]
VCC[26]
VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]
VCC[33]
VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]
VCC[42]
VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[66]
VCC[67]
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]

AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48

2

VCCIO[1]
VCCIO[3]
VCCIO[4]
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]

+CPU_CORE

A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38

E

2

A

4

Check list 1.5

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

2013/03/21

Deciphered Date

Title

PROCESSOR(5/7) PWR,BYPASS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

8

of

45

A

B

C

D

E

+V_SM_VREF should
have 20 mil trace width

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

1

VREF

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

R50
1K_0402_1%
@

C80

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

2

2

2

2

2

2

2

2

2

1

C79

1

C78

1

C77

1

C76

1

C75

1

C74

1

C73

1

C72

1

C71

1U_0402_6.3V6K

1

2

1

+1.5VS
J1

1
1U_0402_6.3V6K

2

JUMP_43X118
@

1
+ C81
330U_D2_2V_Y

2

C89

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

2

2

2

2

2

2

2

1

C88

1

C87

1

C86

1

C85

1

C84

1

C83

1

C82

10U_0603_6.3V6M

1

Place BOT OUT BGA

2

- 1.5V RAILS

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
Check list1.5 P18 M1 default M3 no stuff

+1.5V_CPU_VDDQ

Place TOP IN BGA
1U_0402_6.3V6K

DDR3

R48
1K_0402_5%

INTEL Recommend VDDQ
1*330uF,8*10uF(0603) ,10*1uF(0402)
PD0.8

10U_0603_6.3V6M

GRAPHICS

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

1

2

5A
VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]
VDDQ[9]
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]

C70
0.1U_0402_16V4Z

<11>
<12>

1
2

R49
1K_0402_1%
@

2

1

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

1U_0402_6.3V6K

1

+V_SM_VREF

BE7
BG7

10U_0603_6.3V6M

+VGFX_CORE

AY43

1U_0402_6.3V6K

CR CheckList Rev1.5

SM_VREF

1U_0402_6.3V6K

2

VAXG[1]
VAXG[2]
VAXG[3]
VAXG[4]
VAXG[5]
VAXG[6]
VAXG[7]
VAXG[8]
VAXG[9]
VAXG[10]
VAXG[11]
VAXG[12]
VAXG[13]
VAXG[14]
VAXG[15]
VAXG[16]
VAXG[17]
VAXG[18]
VAXG[19]
VAXG[20]
VAXG[21]
VAXG[22]
VAXG[23]
VAXG[24]
VAXG[25]
VAXG[26]
VAXG[27]
VAXG[28]
VAXG[29]
VAXG[30]
VAXG[31]
VAXG[32]
VAXG[33]
VAXG[34]
VAXG[35]
VAXG[36]
VAXG[37]
VAXG[38]
VAXG[39]
VAXG[40]
VAXG[41]
VAXG[42]
VAXG[43]
VAXG[44]
VAXG[45]
VAXG[46]
VAXG[47]
VAXG[48]
VAXG[49]
VAXG[50]
VAXG[51]
VAXG[52]
VAXG[53]
VAXG[54]
VAXG[55]
VAXG[56]

1U_0402_6.3V6K

AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46
N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61

R47
1K_0402_5%

2

DC 16A

INTEL Recommend VAXG
2*470uF,6*22uF(0805) and 6*10uF(0603)
11*1U(0402)
PD0.8

1

POWER

2

UCPU1G
+VGFX_CORE

1

+1.5V_CPU_VDDQ

SGA20331E10 S POLY C 330U
2V Y D2 LESR9M EEFSX H1.9

2

R51
+1.5V_CPU_VDDQ

100_0402_5%

2

+VCCSA

2

Place TOP IN BGA
+VCCSA

1
2

1
2

1
2

2

1

C99
1U_0402_6.3V6K

1

C98
1U_0402_6.3V6K

2

C97
1U_0402_6.3V6K

2

C96
1U_0402_6.3V6K

SGA20331E10 S POLY C 330U
2V Y D2 LESR9M EEFSX H1.9

+ C94
330U_D2_2V_Y

C95
1U_0402_6.3V6K

1

6A

L17
L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21
W20

VCCSA[1]
VCCSA[2]
VCCSA[3]
VCCSA[4]
VCCSA[5]
VCCSA[6]
VCCSA[7]
VCCSA[8]
VCCSA[9]
VCCSA[10]
VCCSA[11]
VCCSA[12]
VCCSA[13]
VCCSA[14]
VCCSA[15]
VCCSA[16]

AM28
AN26

2

1

VCCDQ[1]
VCCDQ[2]

C90
1U_0402_6.3V6K

3

BC43
BA43

VDDQ_SENSE
VSS_SENSE_VDDQ

VCCSA

U10

VCCSA_SENSE

VCCSA_SENSE

CPU EDS1.3 P.93
VCCSA_VID0 Must PD
D48
D49

VCCSA_VID[0]
VCCSA_VID[1]

H_VCCSA_VID0
H_VCCSA_VID1

H_VCCSA_VID0
H_VCCSA_VID1

1

+ C91
@
220U_B2_2.5VM_R35

2

1

C93
1U_0402_6.3V6K

C92
1U_0402_6.3V6K

SGA00001700 S POLY C 220U
220U 2.5V M B2 ESR35 TPE H1.9

1

VCCPLL[1]
VCCPLL[2]
VCCPLL[3]

SENSE LINES

BB3
BC1
BC4

1

VCCSA VID
lines

Place BOT OUT Conn

SA RAIL

2

+1.8VS

1.2A

1.8V RAIL

R52
100_0402_5%

3

VAXG_SENSE
VSSAXG_SENSE

SENSE
LINES

F45
G45

VCC_GFXSENSE
VSS_GFXSENSE

1

<41>
<41>

QUIET RAILS

2

INTEL Recommend VCCPLL
1*330uF,2*1uF(0402)
PD0.8

<39>

<39>
<39>

R53
0_0402_5%

VID0 VID1 Vout

HR

CR

0

0

0.9V

V

V

0

1

0.85V

V

V

1

0

0.775V

X

V

1

1

0.75V

X

V

@

2

2

2

2

1

10U_0603_6.3V6M

1

C104

1

C103

1

C102

10U_0603_6.3V6M

1

C101

10U_0603_6.3V6M

2

C100

10U_0603_6.3V6M

INTEL Recommend VCCSA
1*330uF,5*10uF(0603) ,5*1uF(0402)
PD0.8

10U_0603_6.3V6M

4

2

IVY-BRIDGE_BGA1023
C867@

Place BOT OUT BGA

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

2013/03/21

Deciphered Date

Title

PROCESSOR(6/7) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

9

of

45

A

B

C

D

E

UCPU1H
UCPU1I

2

3

4

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]

VSS

VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53
BG9
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35
D4
D40
D43
D46
D50
D54
D58
D6
E25
E29
E3
E35
E40
F13
F15
F19
F29
F35
F40
F55
G51
G6
G61
H10
H14
H17
H21
H4
H53
H58
J1
J49
J55
K11
K21
K51
K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61
M11
M15

VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]

VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]

VSS

NCTF

1

A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53
A9
AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56
AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46
AC6
AD17
AD20
AD4
AD61
AE13
AE8
AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61
AG7
AH4
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AJ7
AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
AM34

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59
G48

1

2

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

3

IVY-BRIDGE_BGA1023
C867@

4

Issued Date
IVY-BRIDGE_BGA1023
C867@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

Deciphered Date

2013/03/21

Title

PROCESSOR(7/7) VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

10

of

45

A

B

C

D

E

+1.5V
+V_DDR_REFA

+1.5V

2

G

2

1

<12,6>

RST_GATE_R

DDR_A_DQS#[0..7]

2

DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11

<6>

DDR_A_DQS[0..7]
DDR_A_D[0..63]

1

DDR_A_D16
DDR_A_D17

<6>
<6>

DDR_A_MA[0..15]

DDR_A_DQS#2
DDR_A_DQS2

<6>

DDR_A_D18
DDR_A_D19

All VREF traces should
have 10 mil trace width

Layout Note:
Place near JDIMM1

+1.5V

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

2

1

2

C110
1U_0402_6.3V6K

2

1

C109
1U_0402_6.3V6K

1

C108
1U_0402_6.3V6K

2

C107
1U_0402_6.3V6K

1

<6>

<6>

DDR_A_BS2

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

2

+1.5V

2

1

2

DDR_A_MA3
DDR_A_MA1

C114
10U_0603_6.3V6M

2

1

C113
10U_0603_6.3V6M

1

C112
10U_0603_6.3V6M

2

C111
10U_0603_6.3V6M

1

DDR_A_MA8
DDR_A_MA5

<6>
<6>

<6>

+1.5V

@
2

SA_CLK_DDR0
SA_CLK_DDR#0

<6>

DDR_A_BS0

<6>
<6>

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDRA_CS1_DIMMA#

DDRA_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

1
+

2

C118
330U_D2_2V_Y

DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35

SGA20331E10
330U 2V H1.9
9mohm POLY

DDR_A_D40
DDR_A_D41

3

DDR_A_D42
DDR_A_D43

+0.75VS

DDR_A_D48
DDR_A_D49

2

1

2

C124
1U_0402_6.3V6K

2

1

C123
1U_0402_6.3V6K

1

C122
1U_0402_6.3V6K

2

C121
1U_0402_6.3V6K

1

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

Layout Note:
Place near JDIMM1.203,204
+3VS

2

205

G1

R60

TYCO_2-2013022-1
CONN@

10K_0402_5%

SP07000JN10

G2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
1

DIMM_DRAMRST#

DIMM_DRAMRST#

<12,6>

DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21

DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31

DDRA_CKE1_DIMMA

DDRA_CKE1_DIMMA

<6>

DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7

2

DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
SA_CLK_DDR1
SA_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDRA_CS0_DIMMA#
SA_ODT0
SA_ODT1

SA_CLK_DDR1
SA_CLK_DDR#1

<6>
<6>

+1.5V

DDR_A_BS1
<6>
DDR_A_RAS#
<6>
DDRA_CS0_DIMMA#
SA_ODT0 <6>
SA_ODT1

<6>

R57
1K_0402_1%

<6>

+VREF_CA
DDR_A_D36
DDR_A_D37

1
DDR_A_D38
DDR_A_D39

2

DDR_A_D44
DDR_A_D45

1

2

R58
1K_0402_1%

DDR_A_DQS#5
DDR_A_DQS5

3

DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
D_CK_SDATA
D_CK_SCLK

D_CK_SDATA <12,14>
D_CK_SCLK <12,14>

+0.75VS

206

Channel A

1

1

2

R59
10K_0402_5%

4

1

C126
2.2U_0603_6.3V6K

2

C125
0.1U_0402_16V4Z

1

2

+0.75VS

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

DDR_A_DQS#0
DDR_A_DQS0

C120
0.1U_0402_16V4Z

2

1

C117
10U_0603_6.3V6M

1

C116
10U_0603_6.3V6M

2

C115
10U_0603_6.3V6M

1

SA_CLK_DDR0
SA_CLK_DDR#0

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_A_D4
DDR_A_D5

C119
2.2U_0603_6.3V6K

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDRA_CKE0_DIMMA

DDRA_CKE0_DIMMA

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

1

2
2

R56
1K_0402_1%

C106
0.1U_0402_16V4Z

D

S

1
Q2

C105
2.2U_0603_6.3V6K

1
3
@
BSS138_NL_SOT23-3

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2

SA_DIMM_VREFDQ

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1

<9>

1

M3 support(unpop)

DDR_A_D0
DDR_A_D1

2

1

JDIMM1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

+V_DDR_REFA
R54
1K_0402_1%

R55
0_0402_5%
1
2
@

+1.5V



4

1/3 Modify

DIMM_1 Standard H:4.0mm
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

2013/03/21

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDRIII DIMMA

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

11

of

45

Rev
0.1

A

B

C

D

E

+1.5V
+V_DDR_REFB

+1.5V

2

G

<11,6>

RST_GATE_R

DDR_B_DQS#[0..7]

DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11

<6>

DDR_B_DQS[0..7]
DDR_B_D[0..63]

2

DDR_B_D2
DDR_B_D3

DDR_B_D16
DDR_B_D17

<6>
<6>

DDR_B_MA[0..15]

DDR_B_DQS#2
DDR_B_DQS2

<6>

DDR_B_D18
DDR_B_D19

All VREF traces should
have 10 mil trace width

Layout Note:
Place near JDIMM2

+1.5V

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

2

1

2

C143
1U_0402_6.3V6K

2

1

C145
1U_0402_6.3V6K

1

C128
1U_0402_6.3V6K

2

C141
1U_0402_6.3V6K

1

<6>

DDRB_CKE0_DIMMB

DDRB_CKE0_DIMMB
<6>

DDR_B_BS2

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

2

DDR_B_MA8
DDR_B_MA5

+1.5V

DDR_B_MA3
DDR_B_MA1

2

1

2

C137
10U_0603_6.3V6M

2

1

C133
10U_0603_6.3V6M

1

C131
10U_0603_6.3V6M

2

C147
10U_0603_6.3V6M

1

<6>
<6>

<6>

SB_CLK_DDR0
SB_CLK_DDR#0

SB_CLK_DDR0
SB_CLK_DDR#0

DDR_B_MA10
DDR_B_BS0

<6>

DDR_B_BS0

<6>
<6>

DDR_B_WE#
DDR_B_CAS#

DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDRB_CS1_DIMMB#

DDRB_CS1_DIMMB#

+1.5V

@
2

+

DDR_B_DQS#4
DDR_B_DQS4

C139
330U_D2_2V_Y
@

2

DDR_B_D34
DDR_B_D35

SGA20331E10
330U 2V H1.9
9mohm POLY

DDR_B_D40
DDR_B_D41

3

DDR_B_D42
DDR_B_D43
+0.75VS

2

1

2

DDR_B_DQS#6
DDR_B_DQS6

C132
1U_0402_6.3V6K

2

1

C146
1U_0402_6.3V6K

1

C140
1U_0402_6.3V6K

2

C138
1U_0402_6.3V6K

1

DDR_B_D48
DDR_B_D49

DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

Layout Note:
Place near JDIMM2.203,204

+3VS

1

R61

2 10K_0402_5%

2

1

2

R64
10K_0402_5%

1

C134
2.2U_0603_6.3V6K

0.1U_0402_16V4Z
C135

4

1

2

+0.75VS

205
207

GND1
BOSS1

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
BOSS2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DIMM_DRAMRST#

1

DIMM_DRAMRST#

<11,6>

DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21

DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31

DDRB_CKE1_DIMMB

DDRB_CKE1_DIMMB

<6>

DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7

2

DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
SB_CLK_DDR1
SB_CLK_DDR#1
DDR_B_BS1
DDR_B_RAS#
DDRB_CS0_DIMMB#
SB_ODT0
SB_ODT1

SB_CLK_DDR1
SB_CLK_DDR#1

<6>
<6>

+1.5V

DDR_B_BS1
<6>
DDR_B_RAS#
<6>
DDRB_CS0_DIMMB#
SB_ODT0 <6>
SB_ODT1

<6>

R65
1K_0402_1%

<6>

+VREF_CB
DDR_B_D36
DDR_B_D37

1
DDR_B_D38
DDR_B_D39

2

DDR_B_D44
DDR_B_D45

1

2

C129
0.1U_0402_16V4Z

2

1

C130
10U_0603_6.3V6M

1

C142
10U_0603_6.3V6M

2

C149
10U_0603_6.3V6M

1

1

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

DDR_B_DQS#0
DDR_B_DQS0

C136
2.2U_0603_6.3V6K

DDR_B_D32
DDR_B_D33

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDR_B_D4
DDR_B_D5

1

2

1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

2

2
2

R63
1K_0402_1%

C148
0.1U_0402_16V4Z

D

S

1

1
Q3

C127
2.2U_0603_6.3V6K

1
3
@
BSS138_NL_SOT23-3

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

1

SB_DIMM_VREFDQ

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

R66
1K_0402_1%

2

1
<9>

DDR_B_D0
DDR_B_D1

1

R62
0_0402_5%
1
2
@

M3 support(unpop)

+1.5V
JDIMM2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

+V_DDR_REFB
R67
1K_0402_1%

DDR_B_DQS#5
DDR_B_DQS5

3

DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
D_CK_SDATA
D_CK_SCLK

D_CK_SDATA <11,14>
D_CK_SCLK <11,14>

+0.75VS

206
208

TYCO_2-2013287-1
CONN@

SP07000KW00

Channel B

4


12/21 Modify

DIMM_2 Reverse H:4.0mm

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

2013/03/21

Deciphered Date

Title

DDRIII DIMMB

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

12

of

45

Rev
0.1

A

B

C

D

E

RTCRST close RAM door J1
1

+RTCBATT
1
C163
1U_0603_10V6K

@
2

2
R75
20K_0402_5%
1
2
R76
20K_0402_5%

20mil
2

1

PCH_RTCRST#

1

1

PCH_SRTCRST#
1

R77
0_0603_5%

1

@

1

D1
BAS40-04_SOT23-3
+RTCVCC
3

20mil

+CHGRTC

1
U16
+RTCVCC

U16

R78

1

2 1M_0402_5%

SM_INTRUDER#

R79

1

2 330K_0402_5%

PCH_INTVRMEN

2

3/7 Add

：Integrated VRM enable
：Integrated VRM disable

BD82HM70
HM70@

H

(INTVRMEN should always be pull high.)

FWH4 / LFRAME#
SRTCRST#
INTRUDER#

LDRQ0#
LDRQ1# / GPIO23

INTVRMEN

SERIRQ

HDA_SYNC_PCH
PCH_SPKR

N34
L34

PCH_SPKR

T10

HDA_RST_PCH#

K34

HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#

G34
C34

*

+5VS

2

HDA_RST_PCH#

1
1

HDA_SYNC_PCH_R

2 HDA_SDOUT_PCH

2

PCH_JTAG_TCK

J3

PCH_JTAG_TMS

H7

0_0402_5%

@
R93
1M_0402_5%

2

HDA_RST_AUDIO#
HDA_SDOUT_AUDIO

N32
R91
51_0402_5%
2
1

R90
2

A36
C36

D

<31>
<31>

HDA_SYNC_AUDIO

3
2 HDA_BITCLK_PCH

HDA_SDOUT_PCH
Q4
BSS138_NL_SOT23-3
1HDA_SYNC_PCH

S

<31>

G

3

HDA_BITCLK_AUDIO

2

1.8V when sampled low
Needs to be pulled High for Huron River platfrom

<31>

A34

Prevent back drive issue.

PAD

T9

@

PAD

T10 @

PCH_JTAG_TDI

K5

PAD

T11 @

PCH_JTAG_TDO

H1

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

1
0_0402_5%

<28>

PCH_SPI_MOSI_1_R

1
0_0402_5%

PCH_SPI_MISO_1_R

1
0_0402_5%

<28>

PCH_SPI_CS0#_1_R

1
0_0402_5%

<28>

PCH_SPI_CLK_1_R

1
0_0402_5%

<28>

3,18,28,29,30>

1
1K_0402_5%

SPI_WP1#_R

R559
R558
R557
R556
R555

R554

2 SPI_HOLD1#
DEG@
2 PCH_SPI_MOSI_1
DEG@
2 PCH_SPI_MISO_1
DEG@

2
10M_0402_5%

PCH_SPI_CLK_1

2

R98

1 33_0402_5%

T3

PCH_SPI_CLK

2

R100

1 33_0402_5%

PCH_SPI_CS0#

Y14

PCH_SPI_CS1#_2

2

R101

1 33_0402_5%

PCH_SPI_CS1#

T1

2
2

R103

1 33_0402_5%
1 33_0402_5%

PCH_SPI_MOSI

R104
2
PCH_SPI_MISO_1
R105
2
PCH_SPI_MISO_2
R106

V4
U3

1

18P_0402_50V8J

1

1
33_0402_5%
PCH_SPI_CS0#_1
SPI_WP1#
SPI_HOLD1#

MIM@ 2 3.3K_0402_5%
2 3.3K_0402_5%

1
3
7
4

CS#
WP#
HOLD#
GND

HDA_SDO
HDA_DOCK_EN# / GPIO33

2

A

+3VS

1

SERIRQ

<29,30>

JTAG_TMS
JTAG_TDI

SATAICOMPO
SATAICOMPI

R86
10K_0402_5% @

R234
1K_0402_5%
@

HDD1

2

12/1 Del

HM70 not support
SATA for port1/port3

3

Y11

L=500mil S=15mil

Y10

SATA_COMP

1

AB12

L=500mil S=15mil

AB13

SATA3_COMP

AH1

RBIAS_SATA3

+1.05VS_VTT

1

2
49.9_0402_1%

1

2
750_0402_1%

R97

SATA3RBIAS

+1.05VS_VTT
2
37.4_0402_1%

R94

JTAG_TDO

SPI_CLK

SATA_PRX_DTX_N0 <24>
SATA_PRX_DTX_P0 <24>
SATA_PTX_DRX_N0 <24>
SATA_PTX_DRX_P0 <24>

PCH_GPIO21

Y3
Y1
AB3
AB1

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

JTAG_TCK

R85
10K_0402_5%

R230
10K_0402_5%

Y7
Y5
AD3
AD1

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

HDA_DOCK_RST# / GPIO13

R99

+3VS

R102
4.7K_0402_5%

SPI_CS0#
SPI_CS1#

SATALED#

SPI_MOSI
SPI_MISO

P3

PCH_SATALED#

V14

PCH_GPIO21

P1

PCH_GPIO19

PCH_GPIO19

SATA0GP / GPIO21
SATA1GP / GPIO19

HM77@ COUGARPOINT_FCBGA989
MIM@ R560 0_0402_5%
+BIOS_SPI
+3VS
1
2
RB751V-40_SOD323-2
1
2
4M@
8
D23 CRM@
VCC 6
PCH_SPI_CLK_1
SCLK 5
PCH_SPI_MOSI_1
SI 2
PCH_SPI_MISO_1
SO

MX25L3206EM2I-12G_SO8
SA000041P00

12/7 Change symbol of U18 from SA00000XT00 to SA000041O00
U18
R111

C168
18P_0402_50V8J

+3VS
+3VS

<29,30>

No use PU 10K +3VS

Debug Port DG 1.2 PU 4.7K +3VS

GPIO19 has internal Pull up

PCH_SPI_MISO
33_0402_5%

U17
R109 1
R108 1

SERIRQ

LPC_FRAME#

AB8
AB10
AF3
AF1

SATA3COMPI

PCH_SPI_CS0#_1

PCH_SPI_MOSI_2
PCH_SPI_MOSI_1

+BIOS_SPI

PCH_GPIO23

V5

Boot BIOS Strap
Reserve for EMI
PCH_SPI_CLK
33_0402_5%

1

PCH_SPI_CLK_1
33_0402_5%

1

PCH_SPI_CLK_2
33_0402_5%

1

@

2
R110

C166
10P_0402_50V8J
1
2
@

@

2
R466

22P_0402_50V8J
1
2 C465
@

@

2
R467

22P_0402_50V8J
1
2 C466
@

2

C167
2

1 33_0402_5%

SPI ROM FOR ME (4MB)
Footprint 200mil

32.768KHZ_12.5PF_1TJF125DP1A000D

1

R96

PCH_RTCX2

Y1
1

2

2 SPI_WP1#
CRM@

PCH_RTCX1
1
R107

4

PCH_SPI_CLK_2

2 PCH_SPI_CS0#_1
DEG@
2 PCH_SPI_CLK_1
DEG@

E36
K36

AD7
AD5
AH5
AH4

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SPI

SPI_HOLD1#_R

LPC_FRAME#

<29,30>
<29,30>
<29,30>
<29,30>

AM10
AM8
AP11
AP10

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA3RCOMPO

<28>

D36

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

AM3
AM1
AP7
AP5

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA

E34

HDA_SDIN0

HDA_SDIN0

IHDA

<31>

HDA_SYNC_PCH

1.5V when sampled high

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

1

RTCRST#

C38
A38
B37
C37

PCH_GPIO23
HDA_BITCLK_PCH

2

<31>

On Die PLL VR Select is supplied by

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

2

C17

This signal has a weak internal pull-down

R88
33_0402_5%
1
R89
33_0402_5%
1
R92
33_0402_5%
1
R95
33_0402_5%
1

1 10K_0402_5%

2

K22

PCH_INTVRMEN

RTCX2

JTAG

1 1K_0402_5%

2

1

G22

SM_INTRUDER#

RTCX1

+VCCSUS3_3
2

R81

1

C467
22P_0402_50V8J
@

ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]

R87

PCH_SATALED#

1

HDA_SDOUT_PCH

2 R83
1 MIM@
0_0402_5%
2 R149
1 CRM@
4.7K_0402_5%

SPI_WP1#_R

1 10K_0402_5%

1

*

D20

1
HDA_SDO

2

2

<13,18,28,29,30>

PCH_RTCRST#

HDA_BITCLK_AUDIO

HDA_SDO
<29>

R80

2

R84
1K_0402_5%
2
1
@

C20

PCH_SRTCRST#

11/30 Add (EMI request)
+VCCSUS3_3

PCH_RTCX2

SATA 6G

*

LOW= Disable (Default internal PD)

A20

LPC

PCH_SPKR

HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature

2

SERIRQ

U16A
PCH_RTCX1

RTC

2 1K_0402_5%

@

+3VS

SA00005WU20

+3VS
1

20mil

SA00005MQ20

L

R82

C165
0.1U_0402_16V4Z

BD82NM70
NM70@

INTVRMEN

*

5/23 Add

2

2

2

C164
1U_0603_10V6K

2

+RTCVCC

R74
0_0603_5%

PCH_SPI_CS1#_2
PCH_SPI_MISO_2
2 3.3K_0402_5% SPI_WP2#

SPI ROM FOR ME (1MB)
Footprint 200mil

1
2
3
4

CS#
SO
WP#
GND

+3VS
+3VS

1M@
VCC
HOLD#
SCLK
SI

8
7
6
5

SPI_HOLD2#
PCH_SPI_CLK_2
PCH_SPI_MOSI_2

MX25L8006EM2I-12G_SO8
SA000041O00
B

R112
1
2
3.3K_0402_5%

3/26 Add

11/30 Add
MX25L6406EM2I-12G_SO8
8M@

*

LPC
Reserved
SPI

2012/03/21

GPIO51
0
0
1
1

GPIO19
0
1
0
1

4

SA00004G600

Compal Electronics, Inc.
2013/03/21

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

Boot BIOS

Compal Secret Data

Security Classification
Issued Date

U17

D

Title

PCH (1/9) SATA,HDA,SPI, LPC, XDP

Size Document Number
Custom

CHROME M/B LA-8943P Schematic

Date:

Friday, August 10, 2012

Sheet
E

13

of

45

Rev
0.1

A

B

C

D

E

+VCCSUS3_3

U16B

BF36
BE36
AY34
BB34
+3VS
R121

2

1 10K_0402_5%

MINI1_CLKREQ#

R123

2

1 10K_0402_5%

PCH_GPIO20

BG37
BH37
AY36
BB36

+VCCSUS3_3
R124

2

R126

2

@

1 10K_0402_5%

PCH_GPIO73

1 10K_0402_5%

LAN_CLKREQ#

R127

2

1 10K_0402_5%

PCH_GPIO26

R128

2

1 10K_0402_5%

PCH_GPIO44

R129

2

1 10K_0402_5%

HM70 not support
PCIE port 5-8

2

1 10K_0402_5%

PCH_GPIO46

R142

2

1 10K_0402_5%

PCH_GPIO56

BG40
BJ40
AY40
BB40
BE38
BC38
AW 38
AY38

PCH_GPIO45

R130

BJ38
BG38
AU36
AV36

Y40
Y39
2

No use PU 10K +3VALW
<27>
<27>

WLAN
No use PU 10K +3VS

PCH_GPIO73

AB49
AB47

CLK_PCIE_MINI1#
CLK_PCIE_MINI1

<27>

MINI1_CLKREQ#

J2

MINI1_CLKREQ#

M1
AA48
AA47

PCH_GPIO20

No use PU 10K +3VS
<25>
<25>

PCIE LAN
No use PU 10K +3VALW

Y37
Y36

CLK_PCIE_LAN#
CLK_PCIE_LAN

<25>

LAN_CLKREQ#

V10

LAN_CLKREQ#

A8
Y43
Y45

No use PU 10K +3VALW

PCH_GPIO26

No use PU 10K +3VALW

PCH_GPIO44

L12
V45
V46

3

L14
AB42
AB40

PCH_GPIO56

E6
V40
V42

No use PU 10K +3VALW

PCH_GPIO45

T13
V38
V37

No use PU 10K +3VALW

PCH_GPIO46

K12
AK14
AK13

PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5

SML0ALERT# / GPIO60
SML0CLK
SML0DATA

SML1ALERT# / PCHHOT# / GPIO74
SML1CLK / GPIO58
SML1DATA / GPIO75

PERN6
PERP6
PETN6
PETP6
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8

CL_CLK1
CL_DATA1
CL_RST1#

A12

PCH_SMBDATA

<29>

DDR,WLAN,SMBUS
<27,30>

PCH_SMBDATA

RST_GATE

RST_GATE

C8

PU 2.2K +3VALW

<27,30>

<6>

S3 reduse

No use PU 10K +3VALW

2

10K_0402_5%

PCH_SMBCLK

R114

1

2

2.2K_0402_5%

PCH_SMBDATA

R115

1

2

2.2K_0402_5%

RST_GATE

R116

1

2

1K_0402_5%

PCH_GPIO74

R117

1

2

10K_0402_5%

PCH_SML1CLK

R118

1

2

2.2K_0402_5%

PCH_SML1DATA

R119

1

2

2.2K_0402_5%

PCH_GPIO47

R120

1

2

10K_0402_5%

1

G12

C13

PCH_GPIO74

E14

PCH_SML1CLK

EC-PCH SMBUS

M16

PCH_SML1DATA

PU 2.2K +3VALW

S3 reduse

No use PU 10K +3VALW

+3VS

For DDR , TP
R122
4.7K_0402_5%
1
2

M7
PCH_SMBDATA 6

T11

1

Q5A
DMN66D0LDW-7_SOT363-6

P10

+3VS

D_CK_SDATA

D_CK_SDATA

<11,12>

D_CK_SCLK

<11,12>

R125
4.7K_0402_5%
1
2
+3VS

3

4

D_CK_SCLK

Q5B
DMN66D0LDW-7_SOT363-6

PEG_A_CLKRQ# / GPIO47

CLKOUT_PCIE1N
CLKOUT_PCIE1P

C9

SMB_ALERT#
PCH_SMBCLK

1

PCH_SMBCLK

CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0# / GPIO73

PCH_SMBCLK

R113

5

BG36
BJ36
AV34
AU34

SMBDATA

H14

SMB_ALERT#

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

M10

PCH_GPIO47

+3VS

No use PU 10K +3VALW

Pull up at EC side.

AB37
AB38
PCH_SML1DATA 6

CLKOUT_DMI_N
CLKOUT_DMI_P

PCIECLKRQ1# / GPIO18
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P

PCIECLKRQ2# / GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P

CLKIN_DMI2_N
CLKIN_DMI2_P

PCIECLKRQ3# / GPIO25
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

PCIECLKRQ4# / GPIO26
CLKOUT_PCIE5N
CLKOUT_PCIE5P

REFCLK14IN

PCIECLKRQ5# / GPIO44

CLKIN_PCILOOPBACK

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

XTAL25_IN
XTAL25_OUT

AV22
AU22

CLK_CPU_DMI#
CLK_CPU_DMI

AM12
AM13

CLK_CPU_DPLL#
CLK_CPU_DPLL

BF18
BE18

CLK_CPU_DMI# <5>
CLK_CPU_DMI <5>
CLK_CPU_DPLL# <5>
CLK_CPU_DPLL <5>

120MHz for eDP.

CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI

2 10K_0402_5%
2 10K_0402_5%

BJ30
BG30

CLKIN_GND1#
CLKIN_GND1

R133 1
R134 1

2 10K_0402_5%
2 10K_0402_5%

G24
E24

CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M

R135 1
R136 1

2 10K_0402_5%
2 10K_0402_5%

AK7
AK5

CLK_BUF_PCIE_SATA# R137 1
CLK_BUF_PCIE_SATA
R138 1

2 10K_0402_5%
2 10K_0402_5%

K45

CLK_BUF_ICH_14M

R139 1

2 10K_0402_5%

H45

CLK_PCI_LPBACK

V47
V49

XTAL25_IN
XTAL25_OUT

2
1
R140 @
33_0402_5%

Y47

3

PCH_SML1CLK

1
C175 @

CLK_PCI_LPBACK

2
22P_0402_50V8J

PCIECLKRQ7# / GPIO46
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P

4

CLKOUTFLEX3 / GPIO67

EC_SMB_CK2

EC_SMB_CK2

<29>

3

R141
90.9_0402_1%
1
2

XCLK_RCOMP

+1.05VS_VTT

XTAL25_IN

1

2
1M_0402_5%

R144

CLKOUTFLEX2 / GPIO66

<29>

<17>

XTAL25_OUT

CLKOUTFLEX1 / GPIO65

EC_SMB_DA2

Pull down 10K ohm
for using internal Clock

PCIECLKRQ6# / GPIO45
CLKOUTFLEX0 / GPIO64

2

Q6B
DMN66D0LDW-7_SOT363-6

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

EC_SMB_DA2

Reserve for EMI please close to PCH

W=12mil S=15mil
XCLK_RCOMP

Q6A
DMN66D0LDW-7_SOT363-6

R131 1
R132 1

PEG_B_CLKRQ# / GPIO56

1

5

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

PERN2
PERP2
PETN2
PETP2

SMB_ALERT#

2

BE34
BF34
BB32
AY32

E12

2

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

Link

1
1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

SMBUS

C169
C174

1
1

Controller

PCIE LAN

<25> PCIE_PRX_DTX_N3
<25> PCIE_PRX_DTX_P3
<25> PCIE_PTX_C_DRX_N3
<25> PCIE_PTX_C_DRX_P3

C170
C171

SMBCLK

FLEX CLOCKS

<27> PCIE_PRX_DTX_N2
<27> PCIE_PRX_DTX_P2
<27> PCIE_PTX_C_DRX_N2
<27> PCIE_PTX_C_DRX_P2

SMBALERT# / GPIO11

CLOCKS

1

WLAN

No use PU 10K +3VALW
PERN1
PERP1
PETN1
PETP1

PCI-E*

BG34
BJ34
AV32
AU32

K43

CLK_FLEX0

@

F47

CLK_FLEX1

@

H47

CLK_FLEX2

@

K49

CLK_FLEX3

@

T12

PAD

T13

PAD

T14

PAD

T33

PAD

25MHZ_10PF_7V25000014

3
1
C176
12P_0402_50V8J

3

1
GND
4

GND
Y2

1
1

2

2

2

C177
12P_0402_50V8J

COUGARPOINT_FCBGA989
HM77@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

2013/03/21

Deciphered Date

Title

PCH (2/9) PCIE, SMBUS, CLK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

14

of

45

Rev
0.1

A

B

C

D

E

U16C

1 10K_0402_5%

PCH_ACIN

+VCCSUS3_3
1

R153

2

1 10K_0402_5%

SUSWARN#_R

R154

2

1 10K_0402_5%

PCH_GPIO72

R155

2

1 10K_0402_5%

RI#

R157

2

1 200_0402_5%

PM_DRAM_PWRGD

2

1 10K_0402_5%

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

<4>
<4>
<4>
<4>

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

<4>
<4>
<4>
<4>

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

BC24
BE20
BG18
BG20

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BE24
BC20
BJ18
BJ20

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

AW24
AW20
BB18
AV18

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

AY24
AY20
AY18
AU18

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

+1.05VS_VTT

BJ24

L=500mil S=15mil

PCH_RSMRST#

1
R160
1
R161

2
DMI_IRCOMP
49.9_0402_1%
2
DMI2RBIAS
750_0402_1%

DMI_ZCOMP

BG25
BH21

FDI_FSYNC0

DMI_IRCOMP

FDI_FSYNC1

DMI2RBIAS

FDI_LSYNC0
FDI_LSYNC1

4mil width and place
within 500mil of the PCH

<28,5>

SUSACK#

XDP_DBRESET#

2
SUSACK#_R
0_0402_5%

1

2 XDP_DBRESET#_R
0_0402_5%

R164

2

not support AMT APWROK can mux
with PWROK (check list1.5 P.47)

PCH_PWROK

DSWVRMEN

2 0_0402_5%

1 DS3@

1
R166

C12

SUSACK#

K3

SYS_PWROK

P12

2 PCH_PWROK_R
0_0402_5%

L22

SYS_RESET#
SYS_PWROK
PWROK

L10

<5>

PM_DRAM_PWRGD

<29>
<29>

1/11 Add "ACPRESENT" signal. (follow Q5LJ1)

PCH_RSMRST#
R179 1 S3@
1 DS3@
R196

SUS_PWR_DN_ACK
<29> SUSWARN#
<29>

<29>

1
2
0_0402_5%

ACPRESENT

B13

PCH_RSMRST#

C21

2 0_0402_5%
2
0_0402_5%

PBTN_OUT#

R177

PM_DRAM_PWRGD

SUSWARN#_R

APWROK
DRAMPWROK
RSMRST#

K16

PBTN_OUT#

E20

PCH_ACIN

H20

DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

AW16

FDI_INT

AV12

FDI_FSYNC0

BC10

FDI_FSYNC1

AV14

FDI_LSYNC0

BB10

FDI_LSYNC1

A18
E22

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>

FDI_INT

<29,33,36,37>

1

ACIN

2

RB751V-40_SOD323-2
PCH_GPIO72

No use PU 10K +3VALW
3

SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#

SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3#
PWRBTN#

Ring Indicator CRB1.0 PU 10K +3VALW

E10
A10

RI#

DSWODVREN

*

R150

2

R152

2

1 330K_0402_5%
1 330K_0402_5%

@

：
：

DSWODVREN - On Die DSW VR Enable
H Enable internal DSW +1.05VS
1

L Disable
Must always PU at +RTCVCC
+VCCSUS3_3
PCH_PCIE_WAKE# R156

1

PCH_GPIO29

R158

1

CLKRUN#

R162

1

2 10K_0402_5%

<4>

FDI_FSYNC0

<4>

FDI_FSYNC1

<4>

FDI_LSYNC0

<4>

FDI_LSYNC1

<4>

2 10K_0402_5%

@

+3VS
2 8.2K_0402_5%

DSWODVREN
R483 1
1
R482

0_0402_5%
S3@ 2 PCH_RSMRST#
2
DS3@ 0_0402_5%

B9

PCH_PCIE_WAKE#

N3

CLKRUN#

G8

SUS_STAT#

N14

SUSCLK

D10

PM_SLP_S5#

H4

PM_SLP_S4#

F4

PM_SLP_S3#

G10

SLP_A#

G16

SLP_SUS#

PCH_DPWROK

<29>

not support Deep S4,S5 DPWROK mux with
RSMRST#
check list1.5 P.50

PCH_PCIE_WAKE#
CLKRUN#

<25,27>

PCH_DPWROK

2

No use PU 10K +3VS

<30>

R165
100K_0402_5%
@

T15 @ PAD

SLP_A#

SUSCLK

T34 @ PAD
T35 @ PAD
T36 @ PAD

<29>

PM_SLP_S5#

<29>

PM_SLP_S4#

<29>

PM_SLP_S3#

<29>

T16 @ PAD

D2 @
PCH_ACIN

+RTCVCC

2

<29>

SUSACK#
R163

System Power Management

R178 1 S3@

SUS_PWR_DN_ACK

not support Deep S4,S5
can be left unconnected.
Check list1.5 P.81

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT

Follow Tacoma 1.0
R159

<4>
<4>
<4>
<4>

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

1

2

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

FDI

R151

<4>
<4>
<4>
<4>

DMI

+3VALW_PCH

ACPRESENT / GPIO31

SLP_SUS#

BATLOW# / GPIO72

PMSYNCH

RI#

SLP_LAN# / GPIO29

AP14

H_PM_SYNC

K14

PCH_GPIO29

SLP_SUS#
H_PM_SYNC

<29>

Can be left NC
when IAMT is not
support on the
platfrom
not support
Deep S4,S5 can NC
PCH EDS1.5 P.75

<5>
3

No use PU 10K +3VALW

COUGARPOINT_FCBGA989
HM77@

+3VS

Y
A

SYS_PWROK

3

MC74VHC1G08DFT2G_SC70-5

SYS_PWROK

R168
10K_0402_5%

2

R167
10K_0402_5%

4

<5>

1

1

C178

1

@
0.047U_0402_16V7K
2

2

VGATE

1

<41>

P

U19
2
B

PCH_PWROK

G

<29>

ALL power OK

5

tell PCH all power ok
but cpu core

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

Deciphered Date

2013/03/21

Title

PCH (3/9) DMI,FDI,PM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

15

of

45

A

B

C

1 0_0402_5%

IGPU_BKLT_EN

PD 100K
at EC side
1

<22>

PCH_ENVDD

<22>

DPST_PWM

<22>
<22>

+3VS

1 LVDS@ 2 2.2K_0402_5%

CTRL_CLK

R172

1 LVDS@ 2 2.2K_0402_5%

CTRL_DATA

PCH_LCD_CLK
PCH_LCD_DATA

R171

DIS only can NC

2.37K_0402_1%
2
1

2
R173
0_0402_5%

1 LVDS@ 2 2.2K_0402_5%

PCH_LCD_CLK

R175

1 LVDS@ 2 2.2K_0402_5%

PCH_LCD_DATA

Check list1.5 P.60 disable Graphics
ALL Can NC
but DAC_IREF still need PD
LVDS disable:
DATA/Clock/Control an NC
VCC_TX_LVDS,VCCA_LVDS PD to GND
2

CTRL_CLK
CTRL_DATA

W=10mil S=30mil

UMA LVDS DDC
R174

T40
K47

L=500mil S=30mil

Change to eDP only
R170

P45

<22>
<22>

PCH_TXCLKPCH_TXCLK+

<22>
<22>
<22>

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

<22>
<22>
<22>

PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+

LVDS_IBG

AF37
AF36

LVD_VREF

AE48
AE47

1
PCH_TXCLKPCH_TXCLK+

AK39
AK40

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

AN48
AM47
AK47
AJ48

PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+

AN47
AM49
AK49
AJ47
AF40
AF39

UM77 not support
LVDS/CRT

AH45
AH47
AF49
AF45

+3VS

R484
R485

1
1

2 2.2K_0402_5%
2 2.2K_0402_5%

PCH_CRT_CLK
PCH_CRT_DATA

R486
R487
R488

1
1
1

2 150_0402_1%
2 150_0402_1%
2 150_0402_1%

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

T45
P39

AH43
AH49
AF47
AF43

<24>
<24>
<24>
<24>
<24>
<24>
<24>

3

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

PCH_CRT_CLK
PCH_CRT_DATA

PCH_CRT_HSYNC
PCH_CRT_VSYNC

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

N48
P49
T49

PCH_CRT_CLK
PCH_CRT_DATA

T39
M40

PCH_CRT_HSYNC
PCH_CRT_VSYNC

M47
M49
T43
T42

SDVO_TVCLKINN
SDVO_TVCLKINP

L_BKLTCTL

SDVO_STALLN
SDVO_STALLP

L_DDC_CLK
L_DDC_DATA

SDVO_INTN
SDVO_INTP

LVD_IBG
LVD_VBG

SDVO_CTRLCLK
SDVO_CTRLDATA

LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA

DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN

COUGARPOINT_FCBGA989
R531
FCM1005KF-301T01 0402

AM42
AM40
AP39
AP40

SDVO_CTRLDATA strap pull high
at level shift page

P38
M39

SDVO_SCLK
SDVO_SDATA

AT49
AT47
AT40

PCH_DPB_HPD

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

1

SDVO_SCLK <23>
SDVO_SDATA <23>

PCH_DPB_HPD

<23>

PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

<23>
<23>
<23>
<23>
<23>
<23>
<23>
<23>

HDMI D2
HDMI D1
HDMI D0
HDMI CLK

P46
P42
AP47
AP49
AT38

2

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

3

HM77@

2

2

R176
1K_0402_0.5%

AP43
AP45

L_CTRL_CLK
L_CTRL_DATA

1

1

CRT_IREF
CRT_IRTN

L_BKLTEN
L_VDD_EN

Digital Display Interface

2

LVDS

R169

J47
M45

IGPU_BKLT_EN

CRT

ENBKL

ENBKL

E

U16D

UMA Panel Backlight ON/OFF
<29>

D

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

Deciphered Date

2013/03/21

Title

PCH (4/9) LVDS,CRT,DP,HDMI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

16

of

45

Rev
0.1

A

B

C

E

U16E

PCI_PIRQC#
PCI_PIRQB#
PCI_PIRQA#
PCI_PIRQD#

R469
R470
R471
R472

1

2
2
2
2

1
1
1
1

R473
R474
R475
R476

PCH_GPIO55
PCH_GPIO53
PCH_GPIO52
PCH_GPIO5

8.2K_0402_5% 2
8.2K_0402_5% 2

1
1

R477
R478

PCH_GPIO51
PCH_GPIO2

8.2K_0402_5% 2

1

R480

PCH_GPIO4

8.2K_0402_5% 2
10K_0402_5% 2

1
1

R523
R180

PCH_GPIO3
PCH_GPIO54

B21
M20
AY16
BG46

+3VS

@

2
8.2K_0402_5%

PCH_GPIO50

<28>

PCH_USB3_RX2_N

<28>

PCH_USB3_RX2_P

PCH_USB3_RX2_N

PCH_USB3_RX2_P

USB3.0
<28>

2

PCH_USB3_TX2_N

PCH_USB3_TX2_N

Boot BIOS Strap
GPIO19 GPIO51 Boot BIOS
Bit10 Destination

<28>

PCH_USB3_TX2_P

PCH_USB3_TX2_P

Bit11

GNT1#/
GPIO51

0

Internal
PH

1

NV_ALE
NV_CLE
NV_RCOMP
NV_RB#

2
8.2K_0402_5%

1
R182

TP21
TP22
TP23
TP24

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

NV_RE#_WRB0
NV_RE#_WRB1
NV_WE#_CK0
NV_WE#_CK1

Reserved

1

0

PCI

1

1

SPI

0

0

LPC

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

K40
K38
H38
G38

CR Check list 1.5 only use for GPIO
No use PU +3VS

PCH_GPIO50
PCH_GPIO52
PCH_GPIO54

C46
C44
E40

無無

PCH_GPIO51
PCH_GPIO53
PCH_GPIO55

D47
E42
F46

PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5

G42
G40
C42
D44

*
PCI Interrupt Requests

如如

CR Check list 1.5 only use for GPIO
PH(Internal PH),
GPIO PU +3VS
<30>

PCH_GPIO2

PAD

3

<5>
<14>
<29>
<30>

CLK_PCI_LPBACK
CLK_PCI_LPC
CLK_PCI_TPM

CLK_PCI_LPBACK
CLK_PCI_LPC
CLK_PCI_TPM

R191
R192
R193

K10

T17 @
PLT_RST#

PLT_RST#
1
1
1

2 22_0402_5% CLK_PCI0
2 22_0402_5% CLK_PCI1
2 22_0402_5% CLK_PCI2
CLK_PCI3
T18 @
CLK_PCI4
T19 @

PAD
PAD

C6
H49
H43
J48
K42
H40

PIRQA#
PIRQB#
PIRQC#
PIRQD#

AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AY1

1

DF_TVS

*Note:457511 Rev 1.3-p.20

DMI,FDI Termination Voltage

AV10
AT8

DF_TVS

AY5
BA2
AT12
BF3

Set to Vcc when HIGH

HR CPU NC

Set to Vss when LOW

HR&CR co-lay CPU PU

CR Check list P.89 PU 2.2K series 1K
+1.8VS

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

USB

1
R181

NV_DQS0
NV_DQS1

PCI

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

1

1
1
1
1

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3

USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3

<28>
<28>
<28>
<28>
<28>
<28>

USB2 (Left side2)

USBRBIAS

EHCI 1

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

R184

C33

USB20_N8
USB20_P8

USB20_N8
USB20_P8

USB20_N10
USB20_P10

USB20_N10
USB20_P10

<27>
<27>

Mini Card (WLAN)

<22>
<22>

<5>

+VCCSUS3_3

CMOS Camera (LVDS)

EHCI 2

USB_OC0#
USB_OC7#
USB_OC5#

USBRBIAS

1
R189

2
22.6_0402_1%

USB_OC1#
USB_OC4#

L=500mil S=15mil

USB_OC3#
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

H_SNB_IVB#

HM70 not support USB2.0 for port 4-7 &12 &13

B33
A14
K20
B17
C16
L16
A16
D14
C14

1
1K_0402_5%

CLOSE TO THE BRANCHING POINT

PME#
PLTRST#

2

DF_TVS

USB2 (Left side1)

USB_OC6#
USBRBIAS#

2

R183
2.2K_0402_5%

USB3 (Left side)
2

2
2
2
2

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

NVRAM

12/6 Add R469~R480

RSVD

+3VS

Only GPIO
function

D

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

USB_OC0#
USB_OC1#

<28>
<28>

USB_OC2#

2
R185
2
R186
2
R187
2
R188
2
R197
2
R208
2
R215
2
R217

1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%

3

11/30 Add (EMI request)
COUGARPOINT_FCBGA989
HM77@

C469
@

2

1

CLK_PCI_LPC

22P_0402_50V8J
C474
@

2

1

CLK_PCI_LPBACK

22P_0402_50V8J
C482
@

2

1

CLK_PCI_TPM

22P_0402_50V8J
R194
0_0402_5%
2
1
@
+3VS

4

4

PLT_RST_BUF#

<25,27,29,30>

1

Y

Issued Date

2

MC74VHC1G08DFT2G_SC70-5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

R195
100K_0402_5%

3

G

U20
2
B
1
A

PLT_RST#

P

5

4

2012/03/21

2013/03/21

Deciphered Date

Title

PCH (5/9) PCI, USB, NVRAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

17

of

45

Rev
0.1

A

B

C

D

E

HDA_SYNC PH(PLL =+1.5VS)
+3VS

2
R201
10K_0402_5%
EDP@

1
2

1

LVDS
eDP

SPI_WP1#_RPCH

R203
10K_0402_5%
MIM@

R204
10K_0402_5%
MIM@

1

Fan Tachometer Inputs
TACH1~7 only on server
can insted to GPIO

R202
4.7K_0402_5%

REC_MODE

1

1

PCH_GPIO71

GPIO71
1
0

1

LVDS/eDP

R200
100K_0402_5%
CRM@

2
2

11/21 EDP@->POP

+VCCSUS3_3
1

R199
10K_0402_5%
CRM@

R198
10K_0402_5%
LVDS@

H On-Die PLL voltage regulator enable
L On-Die PLL Voltage Regulator disable

2

：：

This signal has a weak internal pull up

2

U16F

No use PU 10K +3VS

PCH_GPIO1

A42

PCH_GPIO6

H36

EC_SCI#

E38

EC_SMI#

C10

1

No use PU 10K +3VS
No use PU 10K +3VS
No use PU 10K +3VALW

1

R209

@

2 10K_0402_5%

No use PU +3VALW

2

<29>

EC_SMI#

<30>

No use PU +3VALW

<29>

PCH_GPIO27

1 200K_0402_5% PCH_GPIO36

EC_LID_OUT#

No use PU +3VS

<28,29>

CRM@
1
2
0_0402_5% R239

DEV_MODE

1

@

2 1K_0402_5%

EC_SMI#

EC_LID_OUT#

G2

PCH_GPIO16

U2

PCH_GPIO17

D40

RAM flag

PCH_GPIO22

T5

No use PU +3VALW

DDR3/DDR3L

PCH_GPIO24

E8

No use PD 10K to GND

PCH_GPIO27

E16

No use PU 10K +3VALW

PCH_GPIO28

P8

No use PU 10K +3VS

PCH_GPIO34

K1

PCH_GPIO35

K4

BT ON/OFF
PAD

T20 @

Can't PU
PAD

Can't PU
SATA2GP/GPIO36 & SATA3GP/GPIO37
Sampled at Rising edge of PWROK.
Weak internal pull-down.
(weak internal pull-down is disabled
after PLTRST# de-asserts)
NOTE: This signal should NOT be
pulled high when strap is sampled

C4

PCH_GPIO12

No use PU 10K +3VS

No use can NC

+3VALW_PCH
R214

PCH_GPIO12

No use PU +3VS

+3VS

R211

EC_SCI#

No use PU 10K +3VS

T21 @

PCH_GPIO36

V8

PCH_GPIO37

M5

PCH_GPIO38

N2

PCH_GPIO39

M3

No use PU 10K +3VS

PCH_GPIO48

V13

SATA5GP&TEMP_ALERT# CRB PU 10K +3VS

PCH_GPIO49

V3

No use PU +3VALW

PCH_GPIO57

D6

No use PU 10K +3VS

RAM flag

TACH5 / GPIO69

TACH2 / GPIO6

TACH6 / GPIO70

TACH3 / GPIO7

TACH7 / GPIO71

A44

9/15 Layout
request remove
Test point
They will route
by itself

+3VS

A45

R216

1

2 10K_0402_5%

PCH_GPIO0

R218

1

2 10K_0402_5%

PCH_GPIO1

R219

1

2 10K_0402_5%

PCH_GPIO6

R220

1

2 10K_0402_5%

PCH_GPIO16

B3

R221

1

2 10K_0402_5%

PCH_GPIO17

B47

R522

1

2 10K_0402_5%

PCH_GPIO38

BD1

3

A46
A5
A6

BD49

12/13 Add
R222

1

2 10K_0402_5%

PCH_GPIO34

BE1

R223

1

2 10K_0402_5%

PCH_GPIO48

BE49

R225

1

2 10K_0402_5%

PCH_GPIO49

BF1
+VCCSUS3_3

BF49

+VCCSUS3_3

PCH_GPIO68

B41

REC_MODE

C41

SPI_WP1#_RPCH

A40

PCH_GPIO71

PCH_GPIO68

2
D32

<27>

1
CRM@
RB751V-40_SOD323-2

SPI_WP1#_R

2

+3VS

LAN_PHY_PWR_CTRL / GPIO12
GPIO15

A20GATE

SATA4GP / GPIO16
TACH0 / GPIO17
SCLOCK / GPIO22

1

10K_0402_5%

GPIO24 / MEM_LED

PECI
RCIN#
PROCPWRGD
THRMTRIP#
INIT3_3V#

P4

GATEA20

AU16

PCH_PECI_R

P5

EC_KBRST#

1
2
@
0_0402_5% R207

AY10

NC_1
STP_PCI# / GPIO34
NC_2
GPIO35
NC_3
SATA2GP / GPIO36
NC_4
SATA3GP / GPIO37
NC_5

PECI CPU-EC
CTRL+ALT+DEL

<29>

H_CPUPWRGD
PCH_THRMTRIP#_R 1
R210

non CPU power ok

<5>

2
H_THRMTRIP#
390_0402_5%

H_THRMTRIP#

T14

INIT3_3V

Checklist1.5 P.69
+3VS

This signal has weak internal
PU, can't pull low,leave NC

AH8
AK11
AH10

TS_VSS1~4
PD to GND

AK10

2 10K_0402_5%

PCH_GPIO12

1

2 1K_0402_5%

EC_LID_OUT#

R232

1

2 10K_0402_5%

PCH_GPIO57

1

@

R212

1

2 10K_0402_5%

PCH_GPIO68

R213

1

2 10K_0402_5%

P37

SDATAOUT0 / GPIO39
SDATAOUT1 / GPIO48

VSS_NCTF_15

SATA5GP / GPIO49

VSS_NCTF_16

GPIO57

VSS_NCTF_17

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3

VSS_NCTF_21

VSS_NCTF_4
VSS_NCTF_5

VSS_NCTF_22
VSS_NCTF_23

VSS_NCTF_6

VSS_NCTF_24

VSS_NCTF_7

VSS_NCTF_25

VSS_NCTF_8

VSS_NCTF_26

VSS_NCTF_9

VSS_NCTF_27

VSS_NCTF_10

VSS_NCTF_28

VSS_NCTF_11

VSS_NCTF_29

VSS_NCTF_12

VSS_NCTF_30

VSS_NCTF_13

VSS_NCTF_31

VSS_NCTF_14

VSS_NCTF_32

BG2
BG48
BH3
BH47
BJ4

9/15 Layout
request remove
Test point
They will route
by itself

BJ44
BJ45
BJ46
BJ5
3

BJ6
C2
C48
D1
D49
E1
E49
F1
F49
+3VS

PCH_GPIO24

+3VS

R229
10K_0402_5%

2 10K_0402_5%

R231
10K_0402_5%

PCH_GPIO39

GPIO36/GPIO37 is Strap functionality
that requires internal pull down to be sampled at rising PWROK.
When uses as SATA2GP/SATA3GP for mechanical presence detect
-use a external pull up 150K-200K ohm to Vcc3_3
When used as GP input
-ensure GPI is not driven high during strap sampling window
When Unused as GPIO or SATA*GP
-use 8.2K-10K pull-down
check list page 47

R235
10K_0402_5%
@

Issued Date

2012/03/21

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification

PCH_GPIO22

2

GPIO24 Unmultiplexed
NOTE: GPIO24 configuration
register bits are not cleared by
CF9h reset event.
CRB1.0 PU 10K to +3VALW

R233
10K_0402_5%
@
2

4

2

SLOAD / GPIO38

1

R226

EC_KBRST#

2

1

R228

2 10K_0402_5%

130c shut down

<5>

1

R227

1

<29>

<29,5>

EC_KBRST#

AY11

GPIO27
GPIO28

H_PECI

COUGARPOINT_FCBGA989
HM77@
R224

<13,28,29,30>

R206

GPIO8

VSS_NCTF_18
A4

C40

2

Deep S4,S5 wake event signal
RTC alarm,Power BTN,GPIO27
PCH_GPIO27 (Have internal Pull-High)
Deep S4,S5 wake event signal

<29>

TACH4 / GPIO68

TACH1 / GPIO1

1

Debug Port DG 1.2 PU 4.7K +3VALW_PCH

BMBUSY# / GPIO0

1

T7

CPU/MISC

PCH_GPIO0

GPIO

R205
1K_0402_5%

No use PU 10K +3VS

NCTF

2

PCH_GPIO28

@

2

+3VS

2

1

On-Die PLL Voltage Regulator

*

+3VS
1

GPIO28

2013/03/21

Deciphered Date

Title

PCH (6/9) GPIO, CPU, MISC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

18

of

45

A

B

C

D

E

Thermal Senser share with VCCADAC power rail
so can't remove this power

POWER

1/10 Add

VSSADAC

1

C183

1

0.01U_0402_16V7K 0.1U_0402_16V7K
2
2

VCCALVDS

1mA

VSSALVDS

VCCTX_LVDS[1]
VCCTX_LVDS[2]

60mA VCCTX_LVDS[3]
VCCTX_LVDS[4]

AK37

R237
0_0402_5%
EDP@

AM37
AM38

AN17
AN21
AN26
AN27

+1.05VS_VTT

AP21

2

AP23

2

AP26
AT24
AN33

Place Near AN16,AN21,AN33

AN34

+3VS
BH29
1

Place Near
BH29

C196
0.1U_0402_16V7K

AP16
@
T23

+1.05VS_VCCAPLL_FDI

BG6

1

AP37

VCC3_3[6]

1

LVDS@
C186

3

2

1

2

0921 LVDS@->POP
1

LVDS@
C187
0.01U_0402_16V7K

2

+VCCTX_LVDS

LVDS@
C188
22U_0805_6.3V6M

Near
AU20

2

C484
22U_0805_6.3V6M
@

L2
0.1UH_MLF1608DR10KT_10%_1608
2
1
LVDS@

R238
0_0402_5%
EDP@

0.01U_0402_16V7K

V34

0.1uH inductor, 200mA
1121 EDP@->POP

I/O Buffer Voltage

C189
0.1U_0402_16V7K

2

VCCIO[17]

VCCVRM[3]

AT16

VCCIO[21]

VCCIO[23]
VCCIO[24]

Internal PLL and VRM(+1.5VS)

+1.05VS_VTT

VCCIO[20]

VCCIO[22]

PCH Power Rail Table

+1.5VS

VCCIO[18]
VCCIO[19]

VCCDMI[1]

47mA

VCCIO[1]

AT20
1
AB36

DMI buffer logic

C195
1U_0402_6.3V6K

2

place
near AT20

Core Well I/O Buffer

190mA

VCCIO[25]
VCCIO[26]

VCCPNAND[1]

VCC3_3[3]

VCCVRM[2]
VCCFDIPLL

VCCPNAND[2]
VCCPNAND[3]

AG16
+1.8VS

1

2
VCCPNAND[4]

VccDFTERM should PH +1.8VS or +3VS

AG17
AJ16
AJ17

VCCIO[27]
VCCDMI[2]

10mA

COUGARPOINT_FCBGA989
HM77@

VCCSPI

Voltage Rail

Voltage

S0 Iccmax
Current(A)

V_PROC_IO

1.05

0.002

Processor I/F

V5REF

5

0.001

PCH Core Well Reference Voltage

V5REF_Sus

5

0.001

Suspend Well Reference Voltag

Vcc3_3

3.3

0.178

I/O Buffer Voltage

VccADAC

3.3

0.063

Display DAC Analog Power. This power is
supplied by the core well.

VccADPLLA

1.05

0.075

Display PLL A power

C197
0.1U_0402_16V7K

VccADPLLB

1.05

0.075

Display PLL B power

place
near AG16

VccCore

1.05

1.73

Internal Logic Voltage

V1

For SPI control logi
1

2

+1.8VS

Place Near V33

+3VS

AU20
C198
1U_0402_6.3V6K

2

1

V33
1

VCC3_3[7]

1

1121 LVDS@ ->@

+3VS

+1.05VS_VTT
AP17

On-Die PLL Voltage Regulator

3799mA

+1.5VS

2

PAD

VCCIO[16]

FDI

2

1

C194
1U_0402_6.3V6K

2

1

C193
1U_0402_6.3V6K

2

1

C192
1U_0402_6.3V6K

1

C191
1U_0402_6.3V6K

2

C190
10U_0603_6.3V6M

1

AP24

HVCMOS

H On-Die PLL voltage regulator
enable
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

VCCIO[15]

1

+3VS

1121 EDP@->POP

Place Near AM37

AP36

178mA

VCCAPLLEXP

DMI

：

AN16

NAND / SPI

On-Die PLL Voltage Regulator

2

C483
0.01U_0402_16V7K
@

1 LVDS@ 2
R236
0_0805_5%

VCCIO[28]

VCCIO

+VCCAPLLEXP BJ22

T22 @

C185
10U_0603_6.3V6M

AK36 +VCCA_LVDS

2
PAD

1

C184

U47

1121 LVDS@ ->@

+1.05VS_VTT
AN19

VCCADAC

+3VS

L1
MBK1608221YZF_2P
2
1

Place Near U48

+VCCADAC

1

Place Near AA23

63mA

U48

2

2

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

LVDS

2

1

C182
1U_0402_6.3V6K

2

1

C181
1U_0402_6.3V6K

1

C180
1U_0402_6.3V6K

2

1

C179
10U_0603_6.3V6M

1

VCC CORE

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

+1.05VS_VTT

CRT

1730mA

1

U16G

2

+1.05VS_VTT

C199
1U_0402_6.3V6K

2

VccDMI

1.05

0.047

DMI Buffer Voltage

VccIO

1.05

3.799

Core Well I/O buffers

VccASW

1.05

0.803

1.05 V Supply for Intel R Management
Engine and Integrated LAN

VccSPI

3.3

0.01

3.3 V Supply for SPI Controller Logic

VccDSW

3.3

0.003

3.3v supply for Deep S4/S5 well

VccpNAND

1.8

0.19

1.8V power supply for DF_TVS

VccRTC

3.3

6 uA

Battery Voltage

VccSus3_3

3.3

0.065

Suspend Well I/O Buffer Voltage

3

Trace 20mil

：

H On-Die PLL voltage regulator
enable
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

4

3.3 / 1.5

0.01

VccVRM

1.8 / 1.5

0.16

High Definition Audio Controller Suspend
Voltage
1.8 V Internal PLL and VRMs (1.8 V for
Desktop)

VccCLKDMI

1.05

0.02

DMI Clock Buffer Voltage

VccSSC

1.05

0.095

Spread Modulators Power Supply

VccDIFFCLKN

1.05

0.055

Differential Clock Buffers Power Supply

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.06

Analog power supply for LVDS (Mobile
Only)
Analog power supply for LVDS (Mobile
Only)

2012/03/21

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

VccSusHDA

2013/03/21

Deciphered Date

Title

PCH (7/9) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

19

of

45

D

：

AL29

+1.05VS_VTT

+3VALW_PCH
1
R242

BH23

+VCCAPLL_CPY_PCH

T27 @

2
0_0402_5%

+VCCDSW3_3

PAD

+VCCSUS1 AL24

T25 @

AA24

C216
330U_D2_2V_Y
@

2

AA27
AA29
AA31

2

Near BF47

1

2

2

C213
1U_0402_6.3V6K

1

1

C212
1U_0402_6.3V6K

L5
10UH_LB2012T100MR_20%

2

AA26

AC26
1

C211
1U_0402_6.3V6K

+
2

Near BD47

+1.05VS_VCCA_B_DPL
C217
1U_0402_6.3V6K

1

2

2

C209
22U_0805_6.3V6M

+1.05VS_VCCA_A_DPL
C210
1U_0402_6.3V6K

1

1

C208
22U_0805_6.3V6M

1

2

VCCSUS3_3[7]

65mA

VCCAPLLDMI2
VCCIO[14]
DCPSUS[3]

VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]

AC27
AC29
AC31
AD29
AD31

Near AA19

W21
W23
W24
W26

SGA20331E10
330U 2V H1.9
9mohm POLY

W29
W31
W33

Near M6

VCCASW[1]
VCCASW[2]

803mA

VCCIO[34]

1mA

VCCASW[3]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]

V5REF_SUS
DCPSUS[4]
VCCSUS3_3[1]

1mA

VCCASW[15]

V5REF

VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCC3_3[1]
VCC3_3[8]

VCCASW[16]

VCC3_3[4]

1
0.1U_0402_16V7K

N16

+VCCRTCEXT

Y49

VCCASW[19]

VCC3_3[2]

VCCASW[20]
DCPRTC
VCCVRM[4]

VCCIO[13]

3

BF47

+1.05VS_VCCA_B_DPL

AF17
AF33
AF34
AG34

+1.05VS_VTT

Place
near AG33

suppied by internal
1.05V VR Must NC

VCCIO[3]
AG33

Place
near AF33,
AF34,AG34

2
C226

Near V16
PAD

1
+VCCSST
0.1U_0402_16V7K

V16

+1.05VM_VCCSUS T17
V19

T30 @

2

2

2

1

2

C233
0.1U_0402_16V7K

1

C232
0.1U_0402_16V7K

2

1

2

1
2

2

R568
1K_0402_5%

<25,33>
+VCCSUS3_3

PCH_PWR_EN#

For Deep S3 turn off +V5REF_SUS,+VCCSUS3_3

T23
T24

1

V23

Near T23

2

V24

1

C206
0.1U_0402_16V7K

C203
0.1U_0402_16V7K

2

Near T24

+VCCSUS3_3

P24

+5VREF_SUS

+1.05VS_VTT
D3
RB751V-40_SOD323-2

T26

R243
100_0402_5%

Near M26
M26

+PCH_V5REF_SUS

AN23 +VCCA_USBSUS
AN24

@

1
2
C207
0.1U_0402_16V7K

T28
PAD

suppied by internal
1.05V VR Must NC

+VCCSUS3_3

+3VS

+5VS

D4

P34

+PCH_V5REF_RUN
+VCCSUS3_3

R244
100_0402_5%

1

N22
P20

C214
1U_0603_10V6K
C215
1U_0402_6.3V6K

2

2

Near P34

Near N20

P22

2

1

N20

+3VS

AA16
1

W16
T34

C218
0.1U_0402_16V7K

2 Place near
AJ2

1

1

C219
0.1U_0402_16V7K

2 Place near
AA16,W16

C220
0.1U_0402_16V7K

2 Place

near

T34

VCCIO[4]

95mA

AF13
1
AH13

VCCASW[22]
VCCASW[23]
VCCASW[21]

Near AH13,AH14,AF13
C222
1U_0402_6.3V6K

GPIO28

AF14
AK1

+VCCSATAPLL

@ T29

PAD

AC16

：

H On-Die PLL voltage regulator
enable
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

+1.05VS_VTT

AC17
AD17

3

On-Die PLL Voltage Regulator
+1.5VS

AF11

+1.05VS_VTT

DCPSUS[1]
DCPSUS[2]

2mA

2

AH14

DCPSST

V_PROC_IO

+1.05VS_VTT

AJ2

Near AC16
1

C227
1U_0402_6.3V6K

2

T21
V21
T19

VCCRTC

COUGARPOINT_FCBGA989
HM77@

10mAVCCSUSHDA

P32

Need +3VALW and 0.1U close PCH
1

C234
0.1U_0402_16V4Z

4

2

Near P32

Near A22
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

2013/03/21

Deciphered Date

Title

PCH (8/9) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

CHROME M/B LA-8943P Schematic

Date:

A

B

1

+VCCSUS3_3
A22

1

1

2

Near N26

T29

+RTCVCC

C231
1U_0402_6.3V6K

Place
near BJ8

1

C230
0.1U_0402_16V7K

1

C229
0.1U_0402_16V7K

2

C228
4.7U_0603_6.3V6K

1

4

VCCIO[10]

+1.05VS_VTT
BJ8

isolation between SSC (AG33)
and DIFFCLKN(AF33,AF34,AG34)
18mil width(DIFFCLKN)
10mil (SSC)

VCCIO[2]

+1.05VS_VTT

1 C225
1U_0402_6.3V6K
2

55mA

MISC

2

VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[11]

HDA

Place
near AF17

VCCIO[6]
VCCAPLLSATA
VCCVRM[1]

CPU

2

1 C224
1U_0402_6.3V6K

VCCADPLLB

75mA
75mA

RTC

1 C223
1U_0402_6.3V6K

VCCADPLLA

SATA

BD47

+1.05VS_VCCA_A_DPL
+1.05VS_VTT

PCH_PWR_EN#

C500

VCCASW[18]

VCCIO[12]

+1.5VS

T27

VCCASW[17]

VCCIO[5]

2
C221

C204
1U_0402_6.3V6K

0.1U_0402_16V7K
1
2

RB751V-40_SOD323-2

PCI/GPIO/LPC

AA21

+1.05VS_VTT

2

VCCIO[33]

Clock and Miscellaneous

AA19

1

VCCIO[32]

2

2

R552
1K_0402_5%

VCC3_3[5]

VCCSUS3_3[6]

+1.05VS_VTT

L4
10UH_LB2012T100MR_20%
1
2

DCPSUSBYP

3mA

P28

1

1

PAD

On-Die PLL Voltage Regulator
H On-Die PLL voltage regulator
enable
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

T38

+3VS_VCC_CLKF33

VCCIO[31]

C499

2

suppied by internal
1.05V VR must NC

GPIO28

V12

+PCH_VCCDSW

T26 @

VCCIO[30]
VCCDSW3_3

1

P26

1
0_0603_5%

1
DS3@

2

PAD

T16

Near T16

0.1U_0402_16V7K
1
2

3
Q8
AP2301GN-HF_SOT23-3

1

2

N26

1
DS3@

2

Near T38

VCCIO[29]

S3@
2
R240

1

1

Not support Deep S4,S5
connect to +3VALW

+1.05VS_VTT

VCCACLK

USB

2

POWER

U16J
AD49

C202
0.1U_0402_16V7K

+5VREF_SUS

+5VALW

20mil

2

R241
20K_0402_5%

2

+VCCDSW3_3
1

2

C205
0.1U_0402_16V7K

1

C201
1U_0402_6.3V6K

1
C200
10U_0603_6.3V6M

2

+3VS_VCC_CLKF33

1

R288
20K_0402_5%

3
Q68
AP2301GN-HF_SOT23-3

+VCCACLK

T24 @

1

PAD

+VCCSUS3_3

JUMP_43X39
J13 @
1

C279
0.1U_0402_16V7K

L3
10UH_LB2012T100MR_20%
1
2

+3VALW

VCCDMI = 47mA detal waiting for newest spec

+1.05V analog
internal clock PLL
Can NC

2

+3VS

E

1

VCC3_3 = 178mA detal waiting for newest spec

2

C

1

B

2

A

C

D

Friday, August 10, 2012

Sheet
E

20

of

45

A

B

C

D

E

U16I

1

U16H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

2

3

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

COUGARPOINT_FCBGA989
HM77@

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

1

2

3

4

4

COUGARPOINT_FCBGA989
HM77@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

2013/03/21

Deciphered Date

Title

PCH (9/9) VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

21

of

45

A

B

C

LCD POWER CIRCUIT
+LCDVDD
1

1

6 2

R246
10K_0402_5%

C236
680P_0402_50V7K

1

2

3

2
1K_0402_5%
2
1
R247

3
4

1

+CAM_VCC

W=60mils
1

1

2

2

<16>
<16>

C240
0.1U_0402_16V4Z

R248
100K_0402_5%
2

R525
INVTPWM

1

2
10K_0402_5%

1
R249

2

<16>

@

+3VS

U22 @
2
1
100K_0402_5% OE#

DPST_PWM

2
3

VCC

12/13 Add

<16>
<16>

PCH_TXOUT1+
PCH_TXOUT1-

<16>
<16>

PCH_TXOUT0+
PCH_TXOUT0-

PCH_LCD_DATA
PCH_LCD_CLK
<29>

IN

1

C471

BKOFF#

+LCDVDD

R489 1

EDP_HPD

R454 1 LVDS@ 2 0_0402_5%
R455 1 LVDS@ 2 0_0402_5%

PCH_TXCLK+_R
PCH_TXCLK-_R

R456 1 LVDS@ 2 0_0402_5%
R457 1 LVDS@ 2 0_0402_5%

PCH_TXOUT2+_R
PCH_TXOUT2-_R

R458 1 LVDS@ 2 0_0402_5%
R459 1 LVDS@ 2 0_0402_5%

PCH_TXOUT1+_R
PCH_TXOUT1-_R

R460 1 LVDS@ 2 0_0402_5%
R461 1 LVDS@ 2 0_0402_5%

PCH_TXOUT0+_R
PCH_TXOUT0-_R

R462 1 LVDS@ 2 0_0402_5%
R463 1 LVDS@ 2 0_0402_5%

PCH_LCD_DATA_R
PCH_LCD_CLK_R
BKOFF#
INVTPWM

2 220P_0402_50V7K

+3VS
+LCDVDD

2 10K_0402_5%

INVTPWM
+LED_VOUT

GND

74AHC1G125GW_SOT353-5
1
R250

PCH_TXOUT2+
PCH_TXOUT2-

5

4

PCH_TXCLK+
PCH_TXCLK-

<16>
<16>

<16>
<16>

+3VS
OUT

USB20_P10_R
USB20_N10_R

Camera

+LCDVDD

DMN66D0LDW-7_SOT363-6
C239
Q9B
4.7U_0603_6.3V6K

5

JLVDS1

D

2

PCH_ENVDD

1

LCD/LED PANEL Conn.

Q10
AO3419L_SOT23-3

G

C238
0.047U_0402_16V7K

220ohm@100mhz
DCR 0.04

2

S

2
1

1

2

1

<16>

C235
4.7U_0603_6.3V6K

2

DMN66D0LDW-7_SOT363-6
Q9A

+LED_VOUT
B+
L6
FBMA-L11-201209-221LMA30T_0805
2
1
L7
FBMA-L11-201209-221LMA30T_0805
2
1
@
1
1
C237
SM010014520 3000ma
68P_0402_50V8J

W=60mils

1

R245
300_0603_5%

E

W=60mils

+3VS
+3VALW

D

C247

2
0_0402_5%

0.1U_0402_16V4Z

1

2

1

2

1

C248
10U_0603_6.3V6M

2

W=60mils

C249
0.1U_0402_16V4Z

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

SP010011S00

EDP_AUXN
EDP_AUXP

1

<4>
<4>

D

EDP_HPD

<4>
<4>

EDP_TXP0
EDP_TXN0

<4>
<4>

EDP_TXP1
EDP_TXN1

1

2
G
S

3

Q11
SSM3K7002FU_SC70-3
EDP@

2

3

GND1
GND2
GND3
GND4
GND5
GND6

11/29 Modify.

eDP

EDP_HPD#

2

31
32
33
34
35
36

STARC_107K30-000001-G2_30P
CONN@

Place closed to JLVDS1

W=60mils

<4>

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

R251
100K_0402_5%
EDP@

EDP@ C241 1
EDP@ C242 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCH_LCD_DATA_R
PCH_LCD_CLK_R

EDP@ C243 1
EDP@ C244 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCH_TXOUT1+_R
PCH_TXOUT1-_R

EDP@ C245 1
EDP@ C246 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCH_TXOUT2+_R
PCH_TXOUT2-_R
3

D5

Camera

3

USB20_P10_R

2

USB20_N10_R

1

11/29 Modify D5(ESD request)

L30ESDL5V0C3-2

R252 1
L8
<17>

USB20_P10

<17>

USB20_N10

2
3

2 0_0402_5%
@

2

1

3

4

1

USB20_P10_R

4

USB20_N10_R

WCM2012F2SF-670T04_0805
R253 1

+3VS

4

2
0_0603_5%

+CAM_VCC

2012/03/21

Deciphered Date

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

1
R453

2 0_0402_5%

2013/03/21

Title

LVDS&eDP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

22

of

45

Rev
0.1

A

B

C

D

R255
0_0603_5%
1
2
@

2

4
L9
WCM-2012-900T_0805
1

F1

1

1

+HDMI_5V

2

3
D6
RB491D-YS_SOT23-3

1

R254 1

HDMI_CLK+

W=40mils
+HDMI_5V_OUT

+5VS

E

SM070001310 400ma 90ohm@100mhz DCR 0.3

1.1A_6V_SMD1812P110TF

2

PCH_DPB_N0
PCH_DPB_P0

C251
C252

2
2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

HDMI_TX2HDMI_TX2+

<16>
<16>

PCH_DPB_N1
PCH_DPB_P1

C253
C254

2
2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

HDMI_TX1HDMI_TX1+

<16>
<16>

PCH_DPB_N2
PCH_DPB_P2

C255
C256

2
2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

HDMI_TX0HDMI_TX0+

PCH_DPB_N3
PCH_DPB_P3

C257
C258

2
2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

HDMI_CLKHDMI_CLK+

<16>
<16>

3

3

1

HDMI_R_CK+

0_0402_5%

2

2
2

0_0402_5%

HDMI_R_CK-

2

0_0402_5%

HDMI_R_D0+

@
C250
0.1U_0402_16V4Z

R257 1

HDMI_TX0+

4
L10
WCM-2012-900T_0805
1
<16>
<16>

2

4

R256 1

HDMI_CLK-

1

@

@

4

3

3

1

2

2

R258 1

HDMI_TX0-

2

1

0_0402_5%

HDMI_R_D0-

0_0402_5%

HDMI_R_D1+

@
R259 1

HDMI_TX1+

4
L11
WCM-2012-900T_0805
1
HDMI_TX1-

R260

@

2

4

3

3

1

2

2

1

2

0_0402_5%

HDMI_R_D1-

2

0_0402_5%

HDMI_R_D2+

@
HDMI_TX2+

4

+3VS

L12
WCM-2012-900T_0805
1

2

1

1

@

4

3

3

1
2

2

2

2

R263 1

HDMI_TX2-

0_0402_5%

HDMI_R_D2-

@

2

2

R262
1M_0402_5%

1

PCH_DPB_HPD

6

HDMI_HPD

1

2

C259
220P_0402_50V7K

HDMI_TX2HDMI_TX2+

R264 1
R265 1

2 680_0402_5% HDMI_GND
2 680_0402_5%

HDMI_TX1HDMI_TX1+

R266 1
R267 1

2 680_0402_5%
2 680_0402_5%

HDMI_TX0HDMI_TX0+

R268 1
R270 1

2 680_0402_5%
2 680_0402_5%

HDMI_CLK- R271 1
HDMI_CLK+ R272 1

2 680_0402_5%
2 680_0402_5%
3

2

Q12A
DMN66D0LDW-7_SOT363-6
R269
100K_0402_5%

1

<16>

R261

+3VS

3/1 Add (ESD request)
+HDMI_5V_OUT

2

C492

+3VS
SDVO_SCLK

2 2.2K_0402_5%

SDVO_SDATA

1

2

2

<28>
C493
@
0.1U_0402_16V4Z

HDMI_HPD

+3VS

1
R293

2

0_0402_5%

HDMI connector

HDMI_SDATA
HDMI_SCLK
R276
2.2K_0402_5%

HDMI_R_CK-

<16>

SDVO_SDATA

SDVO_SDATA

4

1

1

2
1

SDVO_SCLK

SDVO_SCLK

5

<16>

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+HDMI_5V_OUT

R275
2.2K_0402_5%

6

HDMI_R_CK+
HDMI_R_D0-

RF request
HDMI_SCLK

HDMI_R_D0+
HDMI_R_D1-

1

Q13A
DMN66D0LDW-7_SOT363-6
3

HDMI_SDATA

@

1

Q13B
DMN66D0LDW-7_SOT363-6
@

Place closed to JHDMI1

2

2

3

JHDMI1

2

2 2.2K_0402_5%

R274 1

0.1U_0402_16V4Z

1

1

R273 1

D7
RB751V-40_SOD323-2

2

3

DMN66D0LDW-7_SOT363-6
Q12B

5
4

+3VS

C260
47P_0402_50V8J

HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+

C261
47P_0402_50V8J

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21
22
23

HONGL_13-13201904CP_19P
CONN@

DC232001000

4

4

11/29 Modify.

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

Deciphered Date

2013/03/21

Title

HDMI Conn

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

23

of

45

Rev
0.1

A

B

C

D

E

2

3

2

3

W=40mils
+5VS

+R_CRT_VCC
D11
2

@
D10
L30ESDL5V0C3-2

1

CH491DPT_SOT23-3

1

C262
0.1U_0402_16V4Z

1

1

@
D9
L30ESDL5V0C3-2

+CRT_VCC
F2
1.1A_6V_SMD1812P110TFW=40mils
1
2

CRT Connector

2

1

CRB1.0 use 47ohm@100Mhz Bead

PCH_CRT_B

0_0603_5%
0_0603_5%1

2 L15

CRT_G_1

PCH_CRT_B

0_0603_5%
0_0603_5%1

2 L17

CRT_B_1

2

2

2

2

JCRT1
PAD

CRT_G_2

1

2

1

2

1

2
1
2 L19
0_0603_5%

+CRT_VCC

2

A

4

Y

DC060004W00
D-SUB

DSUB_12

1

C274
10P_0402_50V8J
@

CRT_VSYNC_2
1

1

C275
10P_0402_50V8J
2@

2

16
17

G
G

CONTECK_80435-5K1-152
CONN@

100P_0402_50V8J

CRT_HSYNC_2

1
2 L20
0_0603_5%

CRT_HSYNC_1

JCRT1.5
@ T32
PAD

C272

C276 2
68P_0402_50V8J

74AHCT1G125GW_SOT353-5

2

DSUB_15
1

G

CRT_HSYNC

P

1
PCH_CRT_HSYNC R281 2
33_0402_5%

PCH_CRT_HSYNC

1 10K_0402_5%

U23

3

<16>

1

R280 2
5

2 0.1U_0402_16V4Z

OE#

C273 1
2

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

JCRT1.11
@ T31

CRT_B_2
C271
2.2P_0402_50V8C

2

CRT_R_2

C270
2.2P_0402_50V8C

2

1

C269
2.2P_0402_50V8C

2

1

C268
2.2P_0402_50V8C

2

1

C267
2.2P_0402_50V8C

@

2

1

C266
2.2P_0402_50V8C

@

2

1

C265
10P_0402_50V8J

1

C264
10P_0402_50V8J

R279
150_0402_1% @

C263
10P_0402_50V8J

R277
R278
150_0402_1% 150_0402_1%

1

L14
FBMA-L10-160808-600LMT 0603
1
2
L16
FBMA-L10-160808-600LMT 0603
1
2
L18
FBMA-L10-160808-600LMT 0603
1
2

CRT_R_1

PCH_CRT_G

1

<16>

PCH_CRT_G

2 L13

0_0603_5%
0_0603_5%1

1

<16>

PCH_CRT_R

PCH_CRT_R

1

<16>

1

12/30 Modify.

2

C277
68P_0402_50V8J

+CRT_VCC

+3VS

CRT_VSYNC_1

1

4

R283
2.2K_0402_5%

1

2

74AHCT1G125GW_SOT353-5

<16>

PCH_CRT_DATA

1

PCH_CRT_DATA
5

HDD Board Conn

<16>

PCH_CRT_CLK

PCH_CRT_CLK

4

R284
2.2K_0402_5%
2

Y

G

A

1

2

CRT_VSYNC

+CRT_VCC
U24

2

1
PCH_CRT_VSYNC R282 2
33_0402_5%

PCH_CRT_VSYNC

3

<16>

P

5

2 0.1U_0402_16V4Z

OE#

C278 1

6

DSUB_12

Q15A
DMN66D0LDW-7_SOT363-6
3

DSUB_15

Q15B
DMN66D0LDW-7_SOT363-6
JHDD1
3

<13>
<13>

C281 1
C282 1

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

<13>
<13>
+5VS

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
+5VS_HDD

+3VS

@ J2
1

1

2

2

JUMP_43X79

1
2
3
4
5
6
7
8
9
10
11
12

3

1
2
3
4
5
6
7
8
9
10
11
12

GND
GND

13
14

ACES_85201-1205N
CONN@

SP01000E400

+5VS_HDD

100mils

2

1

2

1

2

C488
1000P_0402_50V7K

1

2

C487
0.1U_0402_16V4Z

1

C486
1U_0603_10V6K

C485
10U_0805_10V4Z

3/29 Add (EMI request)

+3VS

1

2

C502
@
0.1U_0402_16V4Z

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

2013/03/21

Deciphered Date

Title

CRT&HDD Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

24

of

45

Rev
0.1

A

B

C

D

E

+3VALW

LAN_PWR_EN#

2
R548 1
@
0_0402_5%
2
R549 1
1K_0402_5%

BIASVDDH
VDDC
VDDC

XTALVDDH
AVDDH
AVDDH

2
+3V_LAN
7
56
62

2

1

C301
0.1U_0402_16V4Z

2

1

VDDO
VDDO
VDDO

2

TRD2_N
TRD2_P

1

+LAN_AVDDL

39
45
51

+LAN_GPHYPLLVDDL

36

+LAN_PCIEPLLVDD

32

2

29

AVDDL
AVDDL
AVDDL

TRD1_N
TRD1_P
TRD0_N
TRD0_P

GPHY_PLLVDDL

+LAN_BIASVDDH

17

+LAN_XTALVDDH

48
42

+LAN_AVDDH

+3V_LAN

49
50

LAN_MIDI3LAN_MIDI3+

47
46

LAN_MIDI2LAN_MIDI2+

43
44

LAN_MIDI1LAN_MIDI1+

41
40

LAN_MIDI0LAN_MIDI0+

60mil

LAN_MIDI3LAN_MIDI3+

<26>
<26>

LAN_MIDI2LAN_MIDI2+

<26>
<26>

LAN_MIDI1LAN_MIDI1+

<26>
<26>

LAN_MIDI0LAN_MIDI0+

<26>
<26>

1

2

C302

20mil
C304

C498
0.1U_0402_16V4Z

SCLK_SPD1000LED#
SPD100LED#_SERIALDO

2

65

LAN_LINK#

.1U_0402_16V7K
.1U_0402_16V7K

2

<27,29>

EC_PME#
+3V_LAN

<15,27>

C303 1

2 0.1U_0402_16V4Z

PLT_RST_BUF#

PCIE_PRX_C_DTX_P3
PCIE_PRX_C_DTX_N3

2 4.7K_0402_5%
@

28
27
33
34

PCIE_TXD_P
PCIE_TXD_N
PCIE_RXD_P
PCIE_RXD_N

TRAFFICLED#_SERIALDI
GPIO1_LR_OUT
GPIO_0

2 0_0402_5%

R290 1

R292 1

PLT_RST_BUF#
CLK_PCIE_LAN
CLK_PCIE_LAN#

2 C305
2 C308

R289 1

R291 1

PCH_PCIE_WAKE#

<17,27,29,30>
<14>
<14>

1
1

66

2 0_0402_5%

3

LAN_PME#

2 0_0402_5%

11
31
30

SI_EEDATA
CS#_EECLK

<26>
<26>
<26>
<26>

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3

R295
R296
R298
R299

1
1
1
1

2
2
2
2

56_0402_5%
56_0402_5%
56_0402_5%
56_0402_5%

CR_DATA0_R
CR_DATA1_R
CR_DATA2_R
CR_DATA3_R

25
24
23
22
52
53
54
55

PREST#
PCIE_REFCLK_P
PCIE_REFCLK_N
SR_DISABLE/XD_DETECT#
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7

MS_INS#/XD_CE#
GPIO2_MEDIA_SENSE/XD_RE#
CR_WP#/XD_WP#
CR_LED_CR_BUS_PWR/XD_ALE
CR_CLK/XD_RY_BY#

+3VS
R310 1

2 1K_0402_5%

R311 1

2 4.7K_0402_5%

58

1

1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z
L23
1
2
BLM18AG601SN1D_2P

+LAN_AVDDH

67
+VDDO_CR_R

R286 2

1 0_0402_5%

R287 1

2 0_0603_5%

LAN_ACTIVITY#

<26>

+3V_LAN

L22

0.1U_0402_16V4Z

1

C307

2

1

2

0.1U_0402_16V4Z

+VDDO_CR

5
64
63

2

SPROM_DOUT
SPROM_CLK

WAKE#

SD_DETECT/XD_WE#
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3

L21
1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z

2

20mil

2

8

1

<26>

C306
<14> PCIE_PRX_DTX_P3
<14> PCIE_PRX_DTX_N3
<14> PCIE_PTX_C_DRX_P3
<14> PCIE_PTX_C_DRX_N3

2

2

+LAN_BIASVDDH

PCIE_PLLVDDL

1

1

20mil
+LAN_XTALVDDH

PCIE_PLLVDDL
SO_LINKLED#

1

37

C298
0.1U_0402_16V4Z

35
61

TRD3_N
TRD3_P

C289
0.1U_0402_16V4Z

1

C299
4.7U_0603_6.3V6K

D
G

S

1

2

R569
1
2
@
10K_0402_5%
PCH_PWR_EN#

2

+1.2V_LAN

1

+3V_LAN

3
AO3419L_SOT23-3
Q37

<29>

2

1

R285
2 0_0805_5%
@

1

<20,33>

1

VDDO_CR

C297
4.7U_0603_6.3V6K

2

C478
0.1U_0402_16V4Z

2

20
R02 Modify

C477
0.1U_0402_16V4Z

2

U25

1/3 Add(Broadcom request)

1

4.7U_0603_6.3V6K
C296

1

C300
0.1U_0402_16V4Z

2

1

C295
0.1U_0402_16V4Z

2

1

C294
0.1U_0402_16V4Z

2

1

C292
0.1U_0402_16V4Z

2

1

C293
0.1U_0402_16V4Z

+VDDO_CR
1

C288
0.1U_0402_16V4Z

1

C291
0.1U_0402_16V4Z

C290
4.7U_0603_6.3V6K

+1.2V_LAN

CR_CMD_XD_CLE

1

CR_DETECT

CR_DETECT

<26,28>

68
59
9
57

CR_WP#_R

R303

2

1 0_0402_5%

CR_WP#

60

CR_PWR_EN_R

R306

2

1 0_0402_5%

CR_PWR_EN

21

CR_CLK_R

R307

1

26

CR_CMD_R

R308

 2 33_0402_5%

1

2 33_0402_5%

CR_WP#

<26>

CR_PWR_EN

For EMI request

<26>

CR_CLK

CR_CLK

CR_CMD

CR_CMD

C309

<26>

 1

<26>

2

10P_0402_50V8J

VMAIN_PRSNT

+3V_LAN

1

2

R312

6
10

4.7K_0402_5%

LAN_XTALI
LAN_XTALO_R
1
1
C316
15P_0402_50V8J

GND
2

GND

<14>

4
2

2 LAN_RDAC
1.24K_0402_1%

12

LAN_CLKREQ#
R550

1

2

15mil38

1
R315

3LAN_XTALO

C317
15P_0402_50V8J

+3V_LAN

1

16

40mil

L24
2
+1.2V_LAN_OUT 1
4.7UH_PG031B-4R7MS_1.1A_20%

13
C310
0.1U_0402_16V4Z

XTALO
XTALI

40mil
+1.2V_LAN
1

1

2

2

EMI Request...2010/07/27

C311
10U_0603_6.3V6M

SM010005500 500ma 600ohm@100mhz DCR 0.38

R02 Modify
GND PLANE

3

SR_VFB

RDAC
CLK_REQ#

BCM57785XA0KMLG_QFN68_8X8
2

SR_VDDP
SR_VDD

15
14

69

25MHZ_10PF_7V25000014

1

LOW_PWR

R314
200_0402_1%
2

Y3
1

19
18

LAN_XTALO_R
LAN_XTALI

TEST2
SR_LX

4

3

TEST1

20mil

40mil
1 0.1U_0402_16V4Z
C312

1

2

2

L25
1
2
BLM18AG601SN1D_2P

+LAN_PCIEPLLVDD

+3V_LAN
4.7U_0603_6.3V6K
C313

C314
0.1U_0402_16V4Z

1

1

2

2

3

+1.2V_LAN

C315
4.7U_0603_6.3V6K

PLACE NEXT P14

10K_0402_5%

20mil

L26
1
2
BLM18AG601SN1D_2P

+LAN_GPHYPLLVDDL
C318
0.1U_0402_16V4Z

1

1

2

2

1

1

2

2

+1.2V_LAN

C319
4.7U_0603_6.3V6K

+3V_LAN

0

1

C320 1

1

@

1
2
R317
4.7K_0402_5%

1

@

1

AT24C02

SPROM_DOUT
(EEDATA)
2
R316
4.7K_0402_5%

On chip

SPROM_CLK
(EECLK)

2
R319
4.7K_0402_5%

20mil

L27
1
2
BLM18AG601SN1D_2P

+LAN_AVDDL
C321
U26 @
8
7
6
5

VCC
WP
SCL
SDA

A0
A1
A2
GND

1
2
3
4

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

AT24C04BN-SH-T_SO8
SA00004QG00
4

@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

Deciphered Date

2013/03/21

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

LAN Boardcom 57785
Size
Document Number
Custom

CHROME M/B LA-8943P Schematic

Date:
A

B

+1.2V_LAN

C322

1

1

4

R318
4.7K_0402_5%

2

SPROM_CLK
SPROM_DOUT

2 0.1U_0402_16V4Z

C

D

Friday, August 10, 2012

Sheet
E

25

of

45

Rev
0.1

B

C

D

BOTHHAND: S X'FORM_ GST5009-D LF LAN, SP050006B00
TIMAG:S X'FORM_ IH-160 LAN , SP050006F00

E

LAN Connector

C474,C475 and D14
ME interefer,do not pop!!

TL1

RJ45_MIDI0RJ45_MIDI0+

2

LAN_ACTIVITY#
LAN_LINK#

D12
L30ESDL5V0C3-2
@
C324 68P_0402_50V8J
@
2
1
<25>

RJ45_GND

Place close to TCT pin

1
1K_0402_5%

2

C496
0.1U_0402_16V4Z

5

RJ45_MIDI2+

4

RJ45_MIDI1+

3

RJ45_MIDI0-

2

RJ45_MIDI0+

1

PR4+
PR2PR3PR3+
PR2+
PR1SHLD2
PR1+

14
13

LED-(G)

11

40mil

LED+(G)
SANTA_130452-A
CONN@

2

DC234005S00
12/21 Modify

C331 1

RJ45_GND

EMI Request

@
1 0.1U_0402_16V4Z
C506

1

2

2 10P_0402_50V8J

40mil

2

LANGND
1

1

@
0.1U_0402_16V4Z
C505

1

2
1

2
1

RJ45_MIDI2-

PR4-

1

J3
JUMP_43X39
@

2

4/16 ESD reuqest

LANGND

6

1

2

@

2

C495
@

7

RJ45_MIDI1-

12

R04 modify for EMI

JP4

RJ45_MIDI3+

LED+(Y)

SHLD1

2

2

@
JP3

LSE-200NX3216TRLF_1206-2
1
2

2

1

@
JP2

LSE-200NX3216TRLF_1206-2

C494
0.1U_0402_16V4Z

1

1

0.1U_0402_16V4Z

@
JP1

LSE-200NX3216TRLF_1206-2

LSE-200NX3216TRLF_1206-2

+3VS

1

2

MCT3
MCT2
MCT1
MCT0

3/1 Add (ESD request)

8

LAN_LINK#

LAN_LINK#
2
R320

+3V_LAN

11/30 Modify(EMI Request)

2

2

RJ45_MIDI3-

RJ45_GND
R03 Modify

3

1

MCT0

LED-(Y)

9

2

350UH_IH-160
SP050006F00

1
1K_0402_5% 1
C329
220P_0402_50V7K

15
14
13

2
R325

+3V_LAN

RJ45_MIDI1+
RJ45_MIDI1-

JRJ1
10

LAN_ACTIVITY#

LAN_ACTIVITY#

1

2

MCT4
MX4+
MX4-

MCT1

<25>

1
2
L28
100UH_SSC0301101MCF_0.18A_20%

2

1

TCT4
TD4+
TD4-

18
17
16

RJ45_MIDI2RJ45_MIDI2+

@ C332
100P_0402_50V8J

2

1

MCT3
MX3+
MX3-

MCT2

C323
220P_0402_50V7K

1

TCT3
TD3+
TD3-

21
20
19

68P_0402_50V8J
2
1
@
C330

RJ45_MIDI3+
RJ45_MIDI3-

3

10
11
12

LAN_MIDI0LAN_MIDI0+

MCT2
MX2+
MX2-

MCT3

2

LAN_MIDI0LAN_MIDI0+

7
8
9

TCT2
TD2+
TD2-

24
23
22

1

<25>
<25>

LAN_MIDI1+
LAN_MIDI1-

MCT1
MX1+
MX1-

2
R323
75_0603_1%
2
1
R324
75_0603_1%

LAN_MIDI1+
LAN_MIDI1-

4
5
6

TCT1
TD1+
TD1-

2
1
R321
75_0603_1%
2
1
R322
75_0603_1%
1

<25>
<25>

LAN_MIDI2LAN_MIDI2+

C328
0.1U_0402_16V4Z

LAN_MIDI2LAN_MIDI2+

1
2
3

C327
0.1U_0402_16V4Z

<25>
<25>

LAN_MIDI3+
LAN_MIDI3-

C326
0.1U_0402_16V4Z

LAN_MIDI3+
LAN_MIDI3-

C325
0.1U_0402_16V4Z

1

<25>
<25>

D13
L30ESDL5V0C3-2

A

R04 modify

Card Reader Connector
JREAD1

10
11
12
13

WP SW
CD SW
GND SW
GND SW

GND
GND

14
15

SP07000TF00
12/23 Modify(2in1 CARD READER)
(
2.85mm)

板板

40mil

<25>

CR_PWR_EN

2
G
Q16
2N7002K_SOT23-3

2/25 Change symbol of Q16 from SB000009080 to
SB00000EN00

D

S

1

GND
VIN
VIN
EN

VOUT
VOUT
VOUT
FLG

8
7
6
5

AP2301MPG-13_MSOP8

2

1

2

1

2

1

2

CR_CLK_CONN

4

R04 modify
+5VS

1

1

2

@

2

+5VALW
1
C335
0.1U_0402_16V4Z

@

+5VS

C334
0.1U_0402_16V4Z

3/1 Add (EMI request)

C333
0.1U_0402_16V4Z

4

R547
33_0402_5%
2
1
 @

+SDPWR_MMCPWR

U27
1
2
3
4

R327
300_0603_5%

T-SOL_156-1000302601_11P
CONN@

C489
2 CR_CLK_C
 1
@
10P_0402_50V8J

3

2
@
R326
0_0805_5%

C338
0.1U_0402_16V4Z

CR_WP#
2
1
R591
0_0402_5%

DAT0
DAT1
DAT2
CD/DAT3

1

C337
0.1U_0402_16V4Z

CR_WP#
CR_DETECT

8
9
1
2

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3

+3VALW

C336
4.7U_0603_6.3V6K

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3

CR_CLK_CONN

EPAD

<25>
<25,28>

1 0_0402_5%

9

<25>
<25>
<25>
<25>

2

C339
0.1U_0402_16V4Z

R570

CR_CLK

1

<25>

2

+SDPWR_MMCPWR

+VDDO_CR

CMD
VSS
VDD
CLK
VSS

1

3

3
4
5
6
7

CR_CMD

CR_CMD

3

<25>

2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

2013/03/21

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

Card Reader

CHROME M/B LA-8943P Schematic

C

D

Friday, August 10, 2012

Sheet
E

26

of

45

Rev
0.1

B

C

60mil

+3VS_WLAN

+3VS_WLAN

+1.5VS

WLAN&BT Combo module circuits

@ J4
+3VS_WLAN

1

2

2

1

JUMP_43X79
+3VALW

2
PCH_PCIE_WAKE#_R
4.7K_0402_5%
AC@ 2
DISASSOCIATE#
4.7K_0402_5%

2

@ J5

1

1

4.7U_0603_6.3V6K

2
0.1U_0402_16V4Z

2

2

C342

1

2

2

R350

WLAN_PME#

<25,29>

1 MIM@

2

1

@

2

1

@

2

R330

EC_PME#

0_0402_5%
D31

<14>
<14>
<14>

<14>
<14>
<14>
<14>

2

MINI1_CLKREQ#

1
RB751V-40_SOD323-2

CLK_PCIE_MINI1#
CLK_PCIE_MINI1

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2

PCIE_PTX_C_DRX_N2
PCIE_PTX_C_DRX_P2

+3VS_WLAN

2

R340 1
R341 1

E51TXD_P80DATA
E51RXD_P80CLK

2 0_0402_5% E51TXD_P80DATA_R
2 0_0402_5% E51RXD_P80CLK_R

GND1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

H

L

BT_ON#

L

H

<29>

WL_OFF#
PLT_RST_BUF#

MINI1_SMBCLK R337 1
MINI1_SMBDATA R338 1
USB20_N8
USB20_P8

2 0_0402_5%
2 0_0402_5%

@
@

D

S

2
G

BT_ON#

WL_OFF# <29>
PLT_RST_BUF# <17,25,29,30>

Q38
2N7002K_SOT23-3
BT@

PCH_SMBCLK <14,30>
PCH_SMBDATA <14,30>

<17>
<17>
2

DISASSOCIATE#

DISASSOCIATE#

<29>

+3VALW

+3VS_WLAN
Q17
AO3419L_SOT23-3

54

3
AC@

1

40mil(1A)

+3VALW

AC@

1
R334

2 3VSWLAN_GATE_R
1
100K_0402_5%
R335

AC@

2

3VSWLAN_GATE
1K_0402_5%

R336
470_0603_5%
@

1

11/29 Modify

D

S

2
G

2

1

C347
0.1U_0402_16V7K 3VSWLAN_R
AC@

Q18
2N7002K_SOT23-3
AC@

1

WLAN_ON

1

<29>

R339
1K_0402_5%
1
2
AC@
C348
0.1U_0402_16V7K
AC@

D

2

2
E51RXD_P80CLK_R
4.7K_0402_5%

3

+3VS_WLAN

@

1

BT_CTRL

SP07000QC00

2

2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

PLAST_SSM010-52-B-K
CONN@

BT_CTRL

1
R349

BT_CTRL

G

R541
1K_0402_5%
BT@

R342
100K_0402_5%

BT on
module
Disable

JMINI1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53

1

1

<29>
<29>

BT on
module
Enable

2

+1.5VS +3VS_WLAN

0_0402_5%

R332

C346
0.1U_0402_16V4Z

PCH_PCIE_WAKE#_R
0_0402_5%
0_0402_5%

R331

PCH_PCIE_WAKE#

2

1

S

<29>

<15,25>

1 CRM@ 2

WLAN_PME#_EC

4.7U_0603_6.3V6K

C345
0.1U_0402_16V4Z

2

<29>

1

C344

Mini Card Power Rating

JUMP_43X79

1

1

C343
0.1U_0402_16V4Z

2

1
R333
1
R545

1

C341

1

1

3

+3VS

E

1

MINI CARD(Wireless LAN)

D

D

A

2
G

Q19
2N7002K_SOT23-3

3

S

3VSWLAN_GATE

@

3

3

+3VALW_EC

4
1Y1

1Z
1Y0
1S

9
KSI2_SWITCHED

2Y1
2Z
2Y0
PAD
GND

<30>

11
6

4

2S

2
KSO14

BTN_B

<29,30>
CRM@

4
ON/OFF

EC_RST#

BTN_A EC_ENTERING_RW

5

EC_IN_RW

<29,30>
KSI2

F3_BTN

8

ON/OFF

+3VALW_EC

2

8

R589 1

2
CRM@

6
7

PCH_GPIO68_R

EC_RST#

0_0402_5%

EC_ENTERING_RW

<28,29>

<29>

R577 1 CRM@ 2 0_0402_5%

PCH_GPIO68

<18>

SLG4N059VTR_TDFN8_2X2

SA00005HG00

10
7

1

1

PW R_BTN#

GND

3

3

PAD

KSO14_SWITCHED

2

F3_BTN

5

<30>

ON/OFF

9

VCC

U41

VDD

U40

2

1

C503
0.1U_0603_25V7K
CRM@

C504
0.1U_0603_25V7K
CRM@

1

<28,29,30>

4

CRM@
NX3L4684TK_MO-229-10_3X3

5/17 update SA00005HN00

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

2013/03/21

Deciphered Date

Title

MINI CARD (WLAN)/Holeless RST

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

27

of

45

Rev
0.1

A

B

C

Debug Board

D

3/29 Add (EMI request)
1

<17>
<17>

JDB1
<13> PCH_SPI_CS0#_1_R
<13> PCH_SPI_MISO_1_R
<13> SPI_HOLD1#_R
<29> EC_SPICLK
<29> EC_SO_SPI_SI_R1

1

<25,26>

<23>

R592 1

CR_DETECT

<29>

+EC_SPI

2
DEG@ 0_0402_5%

EC UART_TXD

1

HDMI_HPD

R593

2
DEG@ 0_0402_5%

<18,29> DEV_MODE
<15,5> XDP_DBRESET#
<27,29,30> KSI2
<29,30> KSO4

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

G1

G2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

+BIOS_SPI

1
R590

2

USB20_N3

2

3

USB20_P3

1

3

4

PCH_SPI_CLK_1_R
<13>
PCH_SPI_MOSI_1_R
<13>

+3VALW _EC

REC_MODE_L
EC UART_RXD

@

1

1

USB20_N3_2

4

USB20_P3_2
JIO1

<30>

<29>
<29>

<17>

USB20_P2

<17>

USB20_N2

2
3

R572
0_0402_5%
2
@
L33

2

1

3

4

1

<13,18,29,30>

@

<17>

52

USB_OC1#
+5VALW

1

USB20_P2_2

4

USB20_N2_2

<29>

USB_ON#

<31>
<31>
<31>
<31>
<31>

HP_RIGHT
HP_LEFT
COM_MIC
HP_PLUG#
INT_MIC_R

+5VS

2

R573
0_0402_5%

LID_SW #_R <30>
KSI0 <29,30>
KSO3 <29,30>
KSO9 <29,30>

USB20_P3_2
USB20_N3_2
USB20_P2_2
USB20_N2_2

USB2.0
USB2.0

W CM-2012-900T_4P
SPI_W P1#_R

22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

2

R574
0_0402_5%

1
ON/OFFBTN#

IO Board

SM070000K00

W CM-2012-900T_4P

EC_SPICS#/FSEL#_R
<29>
EC_SI_SPI_SO_R1
<29>
EC_RST# <27,29>

2
DEG@ 0_0402_5%

R571
0_0402_5%
2
@
L32

E

SM070000K00

3/1 Add (ESD request)

HP_RIGHT
HP_LEFT
COM_MIC
HP_PLUG#
INT_MIC_R

G2
G1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

1

CONN@
ACES_85201-2005N

+3VALW

SP010011U00

E&T_1001K-F50C-05R
CONN@
2

0.1U_0402_16V4Z

3/29 Add (ESD request) +5VALW

USB3.0

1
@

2

+5VALW
C351
0.01U_0402_16V7K
1
2

C501
0.1U_0402_16V4Z

USB_ON#

2

1

C497

2

+USB3_VCCA

W=60mils

U28

1
2
3
4

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

8
7
6
5

R344
0_0402_5%

1

2

USB_OC0#

<17>

G547I2P81U_MSOP8

For ESD request

U3RXDP2
U3TXDN2

109

U3RXDN2

2 2

98

U3RXDP2

4 4

77

U3TXDN2

5 5

U3TXDP2

1

66

@

2

+USB3_VCCA

C352

W=100mils

0.1U_0402_16V4Z

1

2

+
<17>

U3TXDP2

USB20_N1

1

USB20_N1

@

R348
L31
3
3

3 3

2

U2DN1_L
0_0402_5%

4

C353
150U 6.3V_M

1
2

4

8

2

@
L05ESDL5V0NA-4 SLP2510P8
<17>

SM070000S80 WCM2012F2SF-670T04 67ohm
<17>

PCH_USB3_TX2_P

<17>

PCH_USB3_TX2_N

USB3@
2
1
PCH_USB3_TX2_P_C
C349
0.1U_0402_16V7K
USB3@
2
1
PCH_USB3_TX2_N_C
C350
0.1U_0402_16V7K

R343 1

@

L29

3
2

3
2

USB3@
4
4

U3TXDP2

1

U3TXDN2

@

2 0_0402_5%

R346 1

@

2 0_0402_5%

<17>

PCH_USB3_RX2_P

<17>

PCH_USB3_RX2_N

L30

PCH_USB3_RX2_N

2

4

2

1

U3RXDN2
U3RXDP2

VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+

GND
GND
GND
GND

10
11
12
13

DC23300AI00

D16

USB3@

3

U2DP1_L

JUSB1

1
2
3
4
5
6
7
8
9

For USB2.0 ESD request

2
3

U2DN1_L
U2DP1_L

LOTES_AUSB0015-P001A
CONN@

R345 1

PCH_USB3_RX2_P

USB3.0 Conn.

U3TXDN2
U3TXDP2

1

4

3

1

W CM-2012-900T_0805
1
2
@
R351
0_0402_5%

USB20_P1

W CM2012F2SF-670T04_0805

SM070000S80 WCM2012F2SF-670T04 67ohm

1

SM070001310 WCM2012F2SF-900T04 90ohm

2 0_0402_5%

1

USB20_P1

2

C354
470P_0402_50V7K

3

U3RXDN2

D15
1 1

4

U3RXDP2

1

U3RXDN2

U2DP1_L

3

I/O1

I/O4

REF1 REF2
I/O2

I/O3

6
5
4

+USB3_VCCA
4

U2DN1_L

AZC099-04S_SOT23
W CM2012F2SF-670T04_0805
R347 1

@

2 0_0402_5%

Compal Secret Data

Security Classification
2012/03/21

Issued Date

Deciphered Date

2013/03/21

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

IO Board & USB3.0
Size
Document Number
Custom

Rev
0.1

CHROME M/B LA-8943P Schematic

Date:

Friday, August 10, 2012

Sheet
E

28

of

45

B

C

1

<27,28>

EC_RST#

EC_RST#

<18> GATEA20
<18> EC_KBRST#
<13,30> SERIRQ
<13,30> LPC_FRAME#
<13,30> LPC_AD3
<13,30> LPC_AD2
<13,30> LPC_AD1
<13,30> LPC_AD0

+3VALW_EC
R372

1

2 2.2K_0402_5%

EC_SMB_DA1

R368

1

2 2.2K_0402_5%

EC_SMB_CK1

<17>
<17,25,27,30>

+3VALW

CLK_PCI_LPC
PLT_RST_BUF#

<18>
<27>

1

R369

EC_SCI#
WLAN_ON

GATEA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

1
2
3
4
5
7
8
10

CLK_PCI_LPC
PLT_RST_BUF#
EC_RST#
EC_SCI#
WLAN_ON

12
13
37
20
38

PU at LAN side
@
2

R373

1

2 2.2K_0402_5%

EC_SMB_CK2

R375

1

2 2.2K_0402_5%

EC_SMB_DA2

R376

1

2 10K_0402_5%

EC_SCI#

C475

1

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
SUSWARN#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

EC_KBRST#

180P_0402_50V8J

12/22 Add(ESD request)

1

C368

2 0.01U_0402_16V7K

PLT_RST_BUF#
<27,28,30>

@

ESD request

X1
32.768KHZ_12.5PF_9H03200019
1 EC_XCLK0
EC_XCLK1 2
@
1
@

2

C370
15P_0402_50V8J

C371
15P_0402_50V8J

<27,28,30>

KSI[0..7]

KSI[0..7]

KSO[0..15]

KSO[0..15]

U30

4/11 Modify

1

2

KB932QF-A0_LQFP128
932@

@

SA000055I00
<35,36>
<35,36>
<14>
<14>

DEG@
<28>

EC UART_TXD

<28>

EC UART_RXD

R563 1
R564 1

2 E51TXD_P80DATA
0_0402_5%
DEG@ 2 E51RXD_P80CLK
0_0402_5%

1/11 Add "ACPRESENT" signal. (follow Q5LJ1)
<35>

EC_SPOK

EC_SPOK

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

<15> PM_SLP_S3#
<15> PM_SLP_S5#
<18> EC_SMI#
<15> SUSWARN#
<15> SUS_PWR_DN_ACK
<15> ACPRESENT

EC_DPWROK
EC_SPOK_R
FAN_SPEED1
EC_PME#
E51TXD_P80DATA
E51RXD_P80CLK
9012_PCH_PWROK
PWR_SUSP_LED#
WL_OFF#

R542 1 CRM@ 2 0_0402_5%

3

<32>
<25,27>
<27>
<27>

FAN_SPEED1
EC_PME#
E51TXD_P80DATA
E51RXD_P80CLK

<30>
<27>

PWR_SUSP_LED#
WL_OFF#

AD Input

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

1

5/22 Add

2
20P_0402_50V8

EVT@

R392
0_0402_5%

EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PW M/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PW ROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

PS2 Interface

C373

9012@

R392

SPI Flash ROM

2

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

GPIO
Bus

GPIO

ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PW R_LED#/GPIO54
BATT_LOW _LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APW ROK/GPXIOA10
SA_PGOOD/GPXIOA11

GPI

2
BT_ON#

BT_ON#

C367 2
BATT_TEMP
WLAN_PME#_EC
ADP_I
AD_BID0
AD_PID0
ENBKL

68
70
71
72

SUSACK#
EN_DFAN1
WLAN_PME#
LAN_PWR_EN#

83
84
85
86
87
88

EC_MUTE#
USB_ON#
SLP_SUS#
EAPD
TP_CLK
TP_DATA

97
98
99
109

EC_ENTERING_RW
EC_RST_GATE
HDA_SDO
VCIN0_PH_R

119
120
126
128

EC_SI_SPI_SO
EC_SO_SPI_SI
EC_SPICLK_R
EC_SPICS#/FSEL#

1

2

4.7K_0402_5%

R364

1

2

4.7K_0402_5%

EC_MUTE#

R366

1

@

2 10K_0402_5%

R578

1

@

2 10K_0402_5%

EC_ENTERING_RW

<27>

<27>

WLAN_PME#_EC

ENBKL

BATT_TEMP <35>
<27>
ADP_I <35,36>

<41>

VR_HOT

1
@

DMN66D0LDW-7_SOT363-6

Latest design guide suggest change to
74LVC1G06.

SUSACK# <15>
EN_DFAN1 <32>
WLAN_PME# <27>
LAN_PWR_EN# <25>

2 9012@ 1
R374
200K_0402_5%

1
R146
1
R147
1 R148
1 R143

EC_ACIN

EC_SPICLK

1

<28>

R378

AGND/AGND

1

2 0_0402_5%
R585

1 932@

930_PECI

1
R544

1K_0402_5%
932@

C376
0.1U_0402_16V4Z
@

2 100K_0402_5%

A

4

+EC_SPI

2 932@

0_0402_5%

Issued Date

B

PCH_PWROK

0_0402_5%

2 9012@ 1
R384

+3VALW_EC

R385
10K_0402_5%
SUSP# <33,36,38,39,40>
@
SPI_WP1#_R <13,18,28,30>

MAINPWON

0_0402_5%

KSO1

R399 2 932@

1 47K_0402_5%

KSO2

R398 2 932@

1 47K_0402_5%

VCIN0_PH_R

R387 1 9012@ 2 0_0402_5%

VCIN1_PROCHOT_R

R391 1 9012@ 2 0_0402_5%

VCIN0_PH

<35>

VCIN1_PROCHOT

2

1

<28>

ADP_I

ON/OFF

2
C385
100P_0402_50V8J


1

2
C409
100P_0402_50V8J


1

C410
100P_0402_50V8J
@

EC_SMB_DA1

EC_SMB_CK1

+EC_VCC

2

2

1

C421
100P_0402_50V8J
1 

C423
100P_0402_50V8J
1 

2

C375
0.1U_0402_16V4Z
@

Compal Electronics, Inc.
2013/03/21

Title

EC ENE-KB9012/KB932

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHROME M/B LA-8943P Schematic

C

<35>

Near EC pin for power noise.

KB932 use 256KB ROM
KB9012 Embedded 128KB ROM

Deciphered Date

D

3

R386
10K_0402_5%
@

Compal Secret Data
2012/03/21

<15>
<35,37>

Pin104 This co-layouted circuit is for power fail function of
KB932 and KB9012.At KB932, PCH_PWROK will be connected to pin 104.
At KB9012,PCH_PWROK will be connected to pin 32,
and VCOUT0_PH will be connected to pin 104.

Date:

A

1

R383

11/15 Power modify

2
1
+EC_SPI
D20
932@
1
2 0.1U_0402_16V4Z
RB751V-40_SOD323-2
U31
C378
1
8
VCC 7
2 /CS
SPI_HOLD#
R396 1 932@ 2 4.7K_0402_5%
+EC_SPI
3 DO_IO1 /HOLD 6
EC_SPICLK
CLK 5
4 /W P
1
2
EC_SO_SPI_SI_R
EC_SO_SPI_SI_R1
GND
DIO_IO0
R600
0_0402_5% DEG@
W25X20BVSNIG_SO8
SA00003GM10
932@

<15>

<18,5>

2 9012@ 1
9012_PCH_PWROK
R382
0_0402_5%

SA_PGOOD
+3VALW_EC

Security Classification

MC74VHC1G08DFT2G_SC70-5

2
DS3@

PCH_DPWROK

H_PECI

43_0402_1%

Pin74(KB932),Pin118(KB9012) are with different PECI pin location,
so HW must co-layout for it.
Please make sure which EC pin will be connected to PECI circuit.

+3VALW_EC

KB932&9012 Co-Layout Item
Y

43_0402_1%

C372
4.7U_0603_6.3V6K

2

20mil

R584 2

2

1 9012@ 2
R381

+V18R

KB9012QF-A3_LQFP128_14X14

1

+3VLP

0_0402_5%

R380
9012_PECI

1

L35
1
ECAGND 2
FBMA-L11-160808-800LMT_0603

2

+3VALW

0_0402_5%

2
MIM@

GPXIOA07

@

<15,33,36,37>

Pin 111 is a power source for HW operation of KB9012.
So, power plan will be different between KB930 and KB9012.

PCH_RSMRST# <15>
EC_LID_OUT# <18>

EC_ON <30,37>
ON/OFF <27,30>
LID_SW# <30>

2
CRM@

1

+EC_VCC

PCH_RSMRST#
EC_LID_OUT#
VCIN1_PROCHOT_R
H_PROCHOT#_EC
GPXIOA07
BKOFF#
PBTN_OUT#
PCH_PWR_EN
SA_PGOOD

BKOFF# <22>
PBTN_OUT# <15>
PCH_PWR_EN <33>
SA_PGOOD <39>

ACIN

RB751V-40_SOD323-2
2
1 100P_0402_50V8J

C369

KB932&9012 Co-Layout Item

2 932@ 49.9_0402_1% EC_SI_SPI_SO_R
2 932@ 49.9_0402_1% EC_SO_SPI_SI_R
2 932@ 49.9_0402_1%
EC_SPICLK
2 49.9_0402_1% EC_SPICS#/FSEL#_R
932@

100
101
102
103
104
105
106
107
108

EC_ACIN
EC_ON
ON/OFF
LID_SW#
SUSP#
SPI_WP1#_R_1
9012_PECI

+3VALW

2 932@ 1
R377
200K_0402_5%
D19
2
1

EC_ENTERING_RW
<27>
EC_RST_GATE <6>
HDA_SDO <13>

P

B

<35,5>

5

H_PROCHOT#_EC

H_PROCHOT#_EC

EC_MUTE# <31>
USB_ON# <28>
SLP_SUS# <15>
EAPD <31>
TP_CLK <30>
TP_DATA <30>

EC_SPICS#/FSEL#_R
EC_SPICS#/FSEL#_R
1
2
EC_SI_SPI_SO_R
EC_SI_SPI_SO_R1
R588 DEG@ 0_0402_5%
2 4.7K_0402_5% SPI_WP#
R397 1
@
+EC_SPI

G

U32
2

H_PROCHOT#

Q20B

<16>

REC_MODE_L_R 1
R562 2 0_0402_5%
REC_MODE_L <28>
930_PECI
CRM@
FSTCHG
FSTCHG <36>
BATT_AMB_LED#
BATT_AMB_LED#
<30>
1
2
DEV_MODE_R
DEV_MODE <18,28>
PWR_LED#
R565 @
0_0402_5%
PWR_LED# <30>
BATT_BLUE_LED#
BATT_BLUE_LED# <30>
SYSON
R524
SYSON <33,38>
VR_ON
ENBKL 1
VR_ON
<41>
PM_SLP_S4#
PM_SLP_S4# <15>

124

V18R

5

2

1

R371
0_0402_5%
2
1

1 100P_0402_50V8J ECAGND

73
74
89
90
91
92
93
95
121
127

110
112
114
115
116
117
118

AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW #/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07

SPI_WP1#_R

1

3

SPOK
EC_DPWROK

C377
0.1U_0402_16V4Z
@

R363

TP_DATA

R379

1

SD028180280
1

+3VALW

R395
100K_0402_5%
@

2

2
2

+3VALW

5/22 Add

18K_0402_5%
PVT@

<35,37>

1

1

Analog Board ID definition,
Please see page 3.

AD_PID0

DISASSOCIATE#
BEEP# <31>

63
64
65
66
75
76

<28>

Project ID

R394
0_0402_5%
CP3@

Rb

DISASSOCIATE#
BEEP#

8.2K_0402_5%
DVT@

<28>

Ra

TP_CLK

932@

+3VALW

R393
100K_0402_5%
I57@

<30>

SPI Device Interface

GND/GND
GND/GND
GND/GND
GND/GND
GND0

XCLKI/GPIO5D
XCLKO/GPIO5E

SD028820180

4

BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43

CPU1.5V_S3_GATE/GPXIOA00
W OL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00

C374
0.1U_0402_16V4Z

2

2

Rb

1

SMB_ALERT#_R

+3VLP

1

AD_BID0

122
123

EC_XCLK1
2
EC_XCLK0
0_0402_5%
1
100K_0402_5%

1
R388
2
R390

SUSCLK

21
23
26
27

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

69

R392

1

Ra

<15>

Analog Board ID definition,
Please see page 3.

1

Q20A
DMN66D0LDW-7_SOT363-6

<35>

+3VALW
+3VLP
+3VS

+3VS

DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

11
24
35
94
113

2

Board ID

ECAGND

6

SMB_ALERT#

<35>

+3VALW

R389
100K_0402_5%

<14>

PWM Output

2 100K_0402_5% EC_PME#

@

+3VS

2

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

2

2 100K_0402_5%
2 100K_0402_5%

3

1

1
1

4

U30

1

R360
R579

@

1

2

ECAGND

2

LID_SW#

1

0.1U_0402_16V4Z

2

+3VS

C365
0.1U_0402_16V4Z

2

1

2
0_0603_5%

+EC_VCC

E

1/10 Add

2

C366 2

1
R362

EC_RST#

2

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

+3VALW_EC

1 47K_0402_5%

+3VALW_EC
1

EC_VDD/AVCC

2

@
R365 2

1

C364
1000P_0402_50V7K

+3VLP

1

C363
1000P_0402_50V7K

1

C362
0.1U_0402_16V4Z

2
0_0603_5%

C361
0.1U_0402_16V4Z

1
R359

1
CLK_PCI_LPC
33_0402_5%

@

C360
0.1U_0402_16V4Z

2
R361

C359
0.1U_0402_16V4Z

C358
22P_0402_50V8J
2
1
@

D

+EC_VCCA
L34
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA
2
1

67

+3VALW

9
22
33
96
111
125

A

Friday, August 10, 2012

Sheet
E

29

of

45

Rev
0.1

4

A

B

KSO14

+3VS

KSO15

C382 1

2

100P_0402_50V8J

KSO13

C383 1

2

100P_0402_50V8J

KSO12

C384 1

2

100P_0402_50V8J

KSI0

C386 1

2

100P_0402_50V8J

KSO11

C387 1

2

100P_0402_50V8J

ACES_85208-24071
CONN@

KSO10

C388 1

2

100P_0402_50V8J

SP01000RY00

KSI1

C390 1

2

100P_0402_50V8J

KSO7

C391 1

2

100P_0402_50V8J

KSO9

C392 1

2

100P_0402_50V8J

KSO6

C393 1

2

100P_0402_50V8J

KSI3

C394 1

2

100P_0402_50V8J

KSO5

C395 1

2

100P_0402_50V8J

KSO8

C396 1

2

100P_0402_50V8J

KSO4

C397 1

2

100P_0402_50V8J

KSO0

C400 1

2

100P_0402_50V8J

KSO3

C401 1

2

100P_0402_50V8J

KSI5

C398 1

2

100P_0402_50V8J

KSI4

C399 1

2

100P_0402_50V8J

KSI6

C402 1

2

100P_0402_50V8J

KSO2

C403 1

2

100P_0402_50V8J

CLK_PCI_TPM_R_2

TP Conn.

2

<18>

PCH_GPIO2

2

PCH_GPIO12

2
1
D26
CRM@
RB751V-40_SOD323-2

TP_CLK
TP_DATA

MIM@ 1
0_0402_5%

1 R599
2 0_0402_5%
CRM@
2 0_0402_5%
R594 1
@
<29> SMB_ALERT#_R
R595 1 CRM@ 2 0_0402_5%
<14,27> PCH_SMBCLK
R596 1 CRM@ 2 0_0402_5%
<14,27> PCH_SMBDATA
<29>
<29>

TP_DATA
TP_CLK

CRM@
R543
10K_0402_5%

1
2
3
4
5
6
7
8
9
10

1
2

2

2

Lid
Switch(Hall
Effect Switch)

+3VALW

+3VLP

R581
0_0402_5%

R582
0_0402_5%
@

51_0402_5%
R567

D@

2

1
1

VDD
3

C473
10P_0402_50V8J

D

S

Q7
2N7002K_SOT23-3
932@

2
G

3

AH180W G-7_SC59-3

2

LED1
HT-191NB5-A168_BLUE

LED Board
+3VALW
PW R_LED#

PW R_LED#

JLED1

<29,30>

10mil

<29,30>
<29>
<29>
<29>

PW R_LED#
PW R_SUSP_LED#
BATT_BLUE_LED#
BATT_AMB_LED#

1
2
3
4
5
6

PWR_LED#
PWR_SUSP_LED#
BATT_BLUE_LED#
BATT_AMB_LED#

For power button ESD request
D30
ON/OFFBTN#

7
8

ACES_51524-0060N-001
CONN@
4

2

SP010014M10

1

12/22 Modify.

1
2
3
4
5 G1
6 G2

@

01/12 Change to ACES_51524-0060N-001 .

3
L30ESD24VC3-2_SOT23-3

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

Issued Date

Deciphered Date

2013/03/21

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

C472
0.1U_0402_16V4Z

OUTPUT

1

LID_SW #_R

LID_SW #_R

1

2

3

2

RB751V-40_SOD323-2

Q22
S

LID_SW #

LID_SW #

<28>

1

R490
932@
10K_0402_5%

<29>

51_0402_5%
R528
@

2

U39

GND

<34>

D29

1

2

EC_ON

1

1
<27,29,30>

2

1
2
G
SSM3K7002F_SC59-3

R526
47K_0402_5%

1

51ON#

2

G1
G2

ACES_87151-0807G
CONN@
C406
0.1U_0402_16V4Z

2

ON/OFF

51ON#

LID_SW #_R

4

CONN@
3
4

1
2

ACES_87212-02G0

0_0402_5%
CRM@

(BLUE)

BAV70W _SOT323-3

EC_ON

1

2

ON/OFF

3

<29,37>

JP5

R553

+3VALW

+3VALW +3VS

100K_0402_5%
R409
9012@

ON/OFFBTN# 1

SW 4
EVQPLMA15_4P

C407
100P_0402_50V8J

1
2
3
4
5
6
7
8
GND
GND

1

D22

1

3

2

R580
0_0402_5%
@

Power LED

2

1

4

2
1

2

1

Q14
AO3419L_SOT23-3
@

D

JTP1

1

100K_0402_5%
R408
932@

3

3

G
G

2

1

<13,18

S

G

1K_0402_1%

AZ5125-02S.R7G_SOT23-3

1

ON/OFFBTN#

6
5

<28>

+3VLP

1

SPI_W P1#_R

0_0402_5%
2

2

R587
10K_0402_5%
@

ON/OFF

2

<27,29,30>

CRM@
1 R583
2

1

+3V_TP

C408
100P_0402_50V8J
@

+3VALW

<17>

+EC_SPI

R586
10K_0402_5%
@

+3V_TP

2 CRM@ 1
R598
0_0402_5%

100P_0402_50V8J

C404

ON/OFF BTN

+3VS

Kill SW

R597

+3VS
+VCCSUS3_3

1

C405 1

KSO1

CLK_PCI_TPM

1

LPC_PD#

D21

100P_0402_50V8J

CLK_PCI_TPM
0_0402_5%

<13,29>

R566

<17>

KSI7

2

SERIRQ

2

@ R546
33_0402_5%
2
1

100P_0402_50V8J

12/30 Modify.

KSI2_SW ITCHED 1

2
BTB@

LPC_FRAME# <13,29>
LPC_AD1 <13,29>
LPC_AD0 <13,29>

1

2

@ C481
22P_0402_50V8J
2
1

2

C389 1

R145

1

R540
BTB@
10K_0402_5%

3

GND1
GND2

<13,29>
<13,29>

1

100P_0402_50V8J

1

FOX_NQT510166-LOAO-7F

2

KSO14_SW ITCHED

LPC_AD3
LPC_AD2

<27>

C381 1

25
26

2

LPC_AD3
LPC_AD2
CLK_PCI_TPM_R_2
LPC_FRAME#
LPC_AD1
LPC_AD0
LPC_PD#
SERIRQ

1

KSO14_SW ITCHED

<27,29>

2
4
6
8
10
12
14
16

2
4
6
8
10
12
14
16

2

MIM@

+3VALW
+3VS

CONN@

1
3
5
7
9
11
13
15

2

0_0402_5%

<27,28,29>

1
3
5
7
9
11
13
15

2

2

KSI2

CLKRUN#
PLT_RST_BUF#

CLKRUN#
PLT_RST_BUF#

3

0_0402_5%

JTPM2
<15>
<17,25,27,29>

<27>

2 1

MIM@
R576

1

KSO14_SW ITCHED

2

<27,28,29>

1

1

KSI2_SW ITCHED

<27,28,29>

KSO[0..15]

KSI2_SW ITCHED
R575

E

TPM
KSI[0..7]

KSO[0..15]

2

1

KB KSI[0..7]
Conn.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

D

2

JKB1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

KSI0
KSI1
KSI2_SW ITCHED
KSO0
KSO1
KSO2
KSI3
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSI4
KSO9
KSI5
KSI6
KSO10
KSO11
KSI7
KSO12
KSO13
KSO14_SW ITCHED
KSO15

C

B

C

D

Title

TP/IO Port/ KB CONN/TPM
Size
Document Number
Custom

CHROME M/B LA-8943P Schematic

Date:

Sheet

Friday, August 10, 2012
E

30

of

45

Rev
0.1

A

R411 1
R412 1

40mil

2 0_0603_5%
2 0_0603_5%

4.75V

JUMP_43X39
@

SPK_R+
SPK_R-

3

2

SPKR+
SPKR-

2

1

1

E

Int. Speaker Conn.

40mil

2

D24
AZ5125-02S.R7G_SOT23-3

2
2

BEEP#

1

1

BEEP#_R

<13>

2

PCH_SPKR

1
C413
100P_0402_50V8J

R415
4.7K_0402_5%

2

SPKL+
SPKL-

R416 1
R417 1

2 0_0603_5%
2 0_0603_5%

1
2
3
4

G1
G2

5
6

1

ACES_88266-04001
CONN@

40mil

SPK_L+
SPK_L-

3

R414
47K_0402_5%

1

1
2
3
4

SPK_L+
SPK_LSPK_R+
SPK_R-

C412 need to close U34.12
2

(output = 300 mA)

JSPK1

MONO_IN
1U_0402_6.3V6K

C412
R413
47K_0402_5%

1

2

1

<29>

1

C411
0.1U_0402_16V4Z

1

D

+VDDA

J6

60mil

C

1/4 Modify SPK Pin define

2

+5VS

B

D25
AZ5125-02S.R7G_SOT23-3

SM010014520 3000ma 220ohm@100mhz DCR 0.04

+PVDD_HDA

1

40mil

HD Audio Codec

2

Place near Pin46

20mil

1

1
C422

2

Combo MIC
<28>

2

COM_MIC

COM_MIC

1 COM_MIC_R
1K_0402_5%

R420

MIC2_C_L
4.7U_0603_6.3V6K
2
MIC2_C_R
4.7U_0603_6.3V6K

C425 1

16
17

1

23
24

C463
1000P_0402_50V7K

21

2

External MIC

22
35

1

Combo MIC
2

36
29

10mil
30

Internal MIC
External MIC

68mA 600mA

10mil31

+INTMIC_VREFO

10mil

2

35mA

SPK_OUT_L+

40

SPKL+

MIC2_R

SPK_OUT_L-

LINE1_L

SPK_OUT_R+

41

SPKL-

45

LINE1_R

SPKR+

44

SPK_OUT_RMIC1_L
HPOUT_L

SPKR-

32

MIC1_R
HPOUT_R

HP_LEFT

33

CBN

HP_RIGHT

CBP

SDATA_OUT

MIC2_VREFO

SYNC
RESET#

MIC1_VREFO_R
BCLK

8

HP_PLUG#

28

R428 2

LDD_CAP
GPIO1/DMIC_CLK
JDREF
PD#

Place near
codec
2
2

R429
R430

HP_PLUG#
MIC2JD

1
1

C432

1

2 2.2U_0603_6.3V6K

39.2K_0402_1%
20K_0402_1%
<29>

CPVEE

SENSE_A
SENSE_B

1

EAPD

R431

34

10mil13
18
47

2
0_0402_5%

48
7
49
J7
JUMP_43X39

1

@ 1

2

J8
JUMP_43X39

2

1

@ 1

J9
JUMP_43X39

1

4

@ 1

GND

2

2

2

<28>

2

HDA_SDIN0

33_0402_5%

5

HDA_SDOUT_AUDIO

10
11

HDA_SYNC_AUDIO
HDA_RST_AUDIO#

6

<13>

<13>
<13>

HDA_BITCLK_AUDIO

CPVEE

PCBEEP

SENSE A
SENSE B
EAPD

MONO_OUT
AVSS2
VREF

2

R421

<13>

12

AVSS1
PVSS2
PVSS1

GND

EC_MUTE#

+MIC2_VREFO
3

reseve for EMI

2 C430

+3VS

22P_0402_50V8J

MIC2JD

HDA_RST_AUDIO#

<29>

C429
@
0.1U_0402_16V7K

MONO_IN

R425
22K_0402_5%

D

R424
4.7K_0402_5%
@

For EMI

4

2
0_0402_5%

<13>

3

Q23
BSS138_NL_SOT23-3 S

1

2
G

1

MIC2JD_R

C428
10U_0603_6.3V6M

2

1

R423
2.2K_0402_5%
COM_MIC

R426
22K_0402_5%

2

2

20
37
27

CODEC_VREF

10mil

SPDIFO
DVSS

2
1
@
0_0402_5%

1 281@

EAPD

HDA_RST_AUDIO#

26
43
42

C433 1

2 0.1U_0402_16V4Z

C434 1

2 2.2U_0603_6.3V6K

C435 1
@

2 10U_0603_6.3V6M

Place next pin27

ALC271X-VB6-CG_QFN48_6X6

DGND

2

J10
JUMP_43X39

2

1

2

1

2
@ 1
J11
JUMP_43X39

1

2

1 R422

@

GPIO0/DMIC_DATA

1 20K_0402_1% JDREF 19

<28>

<28>

HP_RIGHT

MIC1_VREFO_L

Place near pin28

<28>

C464
220P_0402_50V7K

HP_LEFT

HDA_SDIN0_AUDIO

1

10U_0603_6.3V6M

INT_MIC_R

1

MIC2_L

R427
C431 1

INT_MIC_R

9

1
DVDD

DVDD_IO

46

39

38

25

LINE2_R

SDATA_IN

C427
2.2U_0603_6.3V6K

+MIC2_VREFO

3

LINE2_L

PVDD2

2

15

PVDD1

C426 1

14

AVDD2

C462 1

AVDD1

1
INT_MIC
1K_0402_5%

2

Place near Pin1, 9
U34

1U_0603_10V6K
2
LINE2_C_L
1U_0603_10V6K
2
LINE2_C_R

C461 1

2
R464

15mil

0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

INT_MIC_R

2

2

Place near Pin25, 38

Internal MIC

C420

0.1U_0402_16V4Z
C424

2

C418

1

1

C419
10U_0805_10V4Z

C417

R465
10K_0402_5%

+3VS

1

2

2

20mil

0.1U_0402_16V4Z

1

1

2
L38 1
BLM18AG121SN1D_2P

+VDDA

1

L37 1
2
BLM18AG121SN1D_2P

10U_0603_6.3V6M

+3VS_DVDD

+AVDD_HDA

1

Place near Pin39
SM010030010 200ma 120ohm@100mhz DCR 0.2

+INTMIC_VREFO

SM010030010 200ma 120ohm@100mhz DCR 0.2

2

2

1

3

2

C416

1

1

C415

1

1

C414
10U_0805_10V4Z

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

2

L36 2
1
FBMA-L11-201209-221LMA30T_0805

+VDDA

2

4

2
@ 1
J12
JUMP_43X39
@ 1

GNDA

GND

2

2

GNDA
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

2013/03/21

Deciphered Date

Title

HD Audio Codec ALC271X

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

31

of

45

Rev
0.1

FAN1 Conn
+5VS

H3
H_2P5

H4
H_2P5

H5
H_2P5

H6
H_2P5

1

1

1

1

D27
1SS355_SOD323-2

@

1

1

H2
H_2P5

@

@

@

@

@

H7
H_2P5

H8
H_2P5

H9
H_2P5

H10
H_2P5

H11
H_2P5

@

@

@

@

H12
H_3P8

H13
H_3P8

H14
H_3P8

H15
H_3P8

4
5

2

C439
1000P_0402_50V7K

1

1

1

1
2
3

1

1
2

JFAN1
1
2
3

+VCC_FAN1
FAN_SPEED1

FAN_SPEED1
1

@

C438
1000P_0402_50V7K
1
2

R433
10K_0402_5%

@

@

@

@

CPU support plate

GND
GND
ACES_85204-0300N
CONN@

H16
H_3P6

H17
H18
H19
H_3P0N H_3P2X3P7N H_3P2X3P5N

12/1 Add

1

1

@

@

@

FD1

8
7
6
5

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FD3

FD4

2
R432

1
2
3
4

+VCC_FAN1
1
300_0402_5%
1

2

EN
VIN
VOUT
VSET

GND
GND
GND
GND

APL5607KI-TRG_SO8
C470
0.1U_0402_16V4Z

@

1

@

FIDUCIAL_C40M80

@

@

FIDUCIAL_C40M80

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

FD2

1

1

C436
2 10U_0805_10V4Z

U33

EN_DFAN1

@

+5VS
1

<29>

1

2/3 Modify.

1

SP02000JR00

1

<29>

1

+3VS

1

C437
10U_0805_10V4Z
1
2

1

@
1

1

D28
BAS16_SOT23-3
2

1

2

40mil

2012/03/21

Deciphered Date

2013/03/21

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FAN & Screw Hole
Rev
0.1

CHROME M/B LA-8943P Schematic

Date:

Friday, August 10, 2012

Sheet

32

of

45

A

B

C

+5VALW TO +5VS

+3VALW to +3VALW_PCH(PCH AUX Power)

+5VS
U35
AO4478L_SO8

C447
0.1U_0603_25V7K

1

R435
100K_0402_5%

<38,39,40>

SUSP

SUSP

1

1

2

<29,36,38,39,40>

SUSP#

1

SUSP

Q24A
DMN66D0LDW-7_SOT363-6

D

2
G

Q35
2N7002K_SOT23-3

R439
10K_0402_5%

S

2

3
Q24B

1

3

1

+5VS_R

2
1

2

2

R630

0_0603_5%

5VS_GATE

2

4

5

SUSP

DMN66D0LDW-7_SOT363-6

2

+3VALW_PCH

2

R434
470_0603_5%

6

4

10mil

1

R436
20K_0402_1%

1 C443

1

2

+VSB

2

+3VALW

C445
4.7U_0603_6.3V6K

2

1

1U_0603_10V6K

1

+5VALW

20mil

1
2
3

C442
4.7U_0603_10V6K

20mil

C441
4.7U_0603_10V6K

2

1

C440
4.7U_0603_10V6K

1

8
7
6
5

E

1

+5VALW

D

+5VALW

2

+3VALW TO +3VS
+3VALW

R440
100K_0402_5%
@

+3VS

10mil

1
3

2

C453
0.1U_0603_25V7K

2

4

R444
100K_0402_5%

1

+1.5VS

10mil

1
3

R448
510K_0402_5%

2
D

S

2
G

1
1

3

2

2

1

2

2
S

1

R452
470_0603_5%

+1.5V_R

1

1

+1.8VS_R

D

2
SUSP
G
Q32
2N7002K_SOT23-3

@

D

2 SUSP
G
Q33
2N7002K_SOT23-3

@S

3

3

S

+1.5V

1

1
1

1
3

SUSP

R451
470_0603_5%

+1.05VS_VTT_R

D

2
SUSP
G
Q31
2N7002K_SOT23-3

2

+1.8VS

R450
470_0603_5%

+0.75VS_R

S

Q28
2N7002K_SOT23-3

2

2

1
2

R449
22_0603_5%

4

C460
0.1U_0603_25V7K

+1.05VS_VTT

D

S

Q30
2N7002K_SOT23-3
@

+0.75VS

1

4

ACIN

3

ACIN

D

2
G

3

1

@

<15,29,36,37>

PCH_PWR_EN

R446
100K_0402_5%

+1.5VS_R

Q29A
DMN66D0LDW-7_SOT363-6

1.5VS_GATE

5

Q29B
DMN66D0LDW-7_SOT363-6

2

<29>

R445
470_0603_5%

1

1

1

PCH_PWR_EN#

PCH_PWR_EN#

6

4

1

R447
200K_0402_5%

SUSP

2

3

2

1
2
3

C458
1U_0402_6.3V6K

+VSB

<20,25>

8
7
6
5

C457
4.7U_0603_6.3V6K

20mil
3

2

C456
0.1U_0402_16V4Z

2

C455
0.1U_0402_16V4Z

1

C454
4.7U_0603_6.3V6K

C459
4.7U_0603_6.3V6K

1

1
1

Q27A
DMN66D0LDW-7_SOT363-6

U38
AO4478L_SO8

1

2

+5VALW

+1.5V

1

Q36
2N7002K_SOT23-3
@

SUSP

+1.5V to +1.5VS

2

S

2
G

2

Q27B
DMN66D0LDW-7_SOT363-6

2

D

3

SYSON

SYSON

R443
100K_0402_5%

2
1

<29,38>

+3VS_R

3VS_GATE

5

SUSP

2

SYSON#
R441
470_0603_5%

1

2

+VSB

1

2

4

1

R442
47K_0402_5%

20mil

2

6 1

1
2
3

C452
1U_0402_6.3V6K

1

8
7
6
5

C451
4.7U_0603_6.3V6K

2

2

C450
4.7U_0603_6.3V6K

1

C449
4.7U_0603_6.3V6K

2

1

U37
AO4478L_SO8

2
SYSON#
G
Q34
2N7002K_SOT23-3

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/03/21

2013/03/21

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DC Interface

CHROME M/B LA-8943P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

33

of

45

Rev
0.1

5

4

2

1

PL1
1

1

+3VALW

1

JUMP_43X118

PC2
1000P_0402_50V7K

1

2

2

+0.75VS

JUMP_43X79
2

PC6
1000P_0402_50V7K

PJ2
1

@

1

2

2

@
PJ3
2

+5VALWP

@

1

1

1

+5VALW

2

+VCCSAP

JUMP_43X118
@ PC8
1000P_0402_50V7K

@

2

1

1

+VCCSA
D

JUMP_43X118

2

PC7 @
1000P_0402_50V7K

PJ4

2

1

PC5
100P_0402_50V8J

@ PC1
1000P_0402_50V7K

2

PC4
100P_0402_50V8J

2

2

1

1

1
2

1
2

PC3
1000P_0402_50V7K

+0.75VSP

PJ1 @
2

+3VALWP

2

D

470P_0402_50V7K PC14

1
2

ACES 88266-04001
CONN@

VIN

HCB2012KF-121T50_0805
1
2

DCJK_IN
330P_0402_50V7K PC10

GND 4
GND 3
2
1

4
3
2
1

1

PJP1
6
5

3

PJ6
2

@ PC9
1000P_0402_50V7K

1

1

+1.8VS

JUMP_43X118

2

PJ13
@ JUMP_43X39
1
2
1
2

2

@

@
PQ16
TP0610K-T1-E3_SOT23-3

2
@PC11
@
PC11
1000P_0402_50V7K

<30> 51ON#

+

2

1

PR1
560_0603_5%
1
2

PR2
560_0603_5%
1
2

1

JUMP_43X118

@ PC12
1000P_0402_50V7K

2

@ PC301
0.1U_0603_25V7K

2

@

+VSBP

+VSB

2

PJ11
2

2

1

C

1

@

JUMP_43X118
PJ12
2
1
2
1

@PC13
@
PC13
1000P_0402_50V7K

DVT remove

1

+1.05VSP

@

+1.05VS_VTT

JUMP_43X118

2

-

PBJ1 @

@ PC302
0.22U_0603_25V7K
2

2

@
PR11
22K_0402_1%
1
2

1

1
2

@
PR10
100K_0402_1%
C

+1.5V
1

2

VS

1

1

1

3

PJ10
@ JUMP_43X39
1
2
1
2

+1.5VP
PJ9

N1

1

BATT+

932@ PD4
LL4148_LL34-2
2
1

1

+1.8VSP

+RTCBATT

ML1220T13RE

+CHGRTC

PR3
0_0402_5%
1
2

+3VLP

B

B

A

A

Compal Secret Data

Security Classification
Issued Date

2012/03/21

2013/03/21

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR DCIN / Pre-charge

Size Document Number
Custom

Rev
0.1

CHROME M/B LA-8942P Schematic

Date:

Friday, August 10, 2012

Sheet
1

34

of

46

5

4

3

2

1

footprint :SUYIN_200275MR008G15QZR_8P-T
PN:DC040007N10 SOCKET BATT C200275MR008G15QZR 8P W/FORK
@
PJP2
10
9
8
7
6
5
4
3
2
1

D

Adaptor protection

Adaptor Throttling point ADP_I
40W
42.88W
1.126V

EC_SMDA
EC_SMCA
TH
BI+

Recovery point ADP_I
33.2W
0.874V

PR58
100_0402_1%

2

GND
GND
8
7
6
5
4
3
2
1

2

D

EC_SMB_DA1

<29,36>

EC_SMB_CK1

<29,36>

+3VLP

+EC_VCCA

1

2

2
3

MAINPWON
2

+3VLP

4

+3VS

BATT_TEMP <29>

GND RHYST1
~OT1TMSNS2
~OT2 RHYST2

1

1

2

2

2

VCIN1_PROCHOT <29>

932@ PR68
1.91K_0402_1%
PR79
10K_0402_1%
2

1
1

1
PC69
0.1U_0603_25V7K

1

SD034100280 10K OHM

9012@ PR81
0_0402_5%
1
2

2

3

+VSBP

2

2

1

PC68
0.22U_0603_25V7K

2

1
PR70
100K_0402_1%
2

D

VL

1

PR105
0_0402_5%
9012@

G

PR71
22K_0402_1%
1
2

3

S

B+

C

5

G
S

BSS84LT1G_SOT23-3

2

2

932@ PQ32
2N7002KW_SOT323-3

VCIN0_PH <29>

6

932@ PR80
0_0402_5%
1
2

D

EC_SPOK

932@ PR66
2
1
9.76K_0402_1%

PH1
100K_0402_1%_NCP15WF104F03RC

PR110 @
100K_0402_1%

1

PR67 932@
100K_0402_1%

<29>

7

G718TM1U_SOT23-8

<29,5> H_PROCHOT#

PQ19

8

2

C

VCC TMSNS1

2

1
PR65
1K_0402_1%

2

PU3 932@

PR64
@
100K_0402_1%

9012@ PR63
5.62K +-1% 0402
PR63 932@
590_0402_1%

1

+3VLP

ADP_I <29,36>

9012@
PR78
12.4K_0402_1%
1

PC65
0.1U_0603_25V7K

+3VALW

PR111 @
6.49K_0402_1%
2
1

932@ PR61
21.5K_0402_1%

1

PC67
0.01U_0402_25V7K

VL

1

PR62 932@
6.49K_0402_1%
2
1

1

PR60
1K_0402_5%

1

JUMP_43X118
PC66
1000P_0402_50V7K

2

1

1

2

1
2

2

2

<40,41>
BATT+

PJ5 @
2

1

1

1

<40,41>
VMB

SUYIN_200275GR008G16MZR

1

PR59
100_0402_1%

<29> H_PROCHOT#_EC

<29>

ECAGND

PH1 under CPU bottom side :
CPU thermal protection at 92 degree C
Recovery at 56 degree C

2

+3VALW

PR72
100K_0402_1%

@ PC70
0.1U_0603_25V7K

2

2

1

PQ20
2N7002KW 1N SOT323-3

@ PR74
10K_0402_1%

@PR75
@
PR75
10K_0402_1%

@ PU4
1
VCC TMSNS1
2
GND RHYST1
3
OT1 TMSNS2

1

@ PR76
100K_0402_1%

<29,37> MAINPWON

4

OT2 RHYST2

1

2

VL
8

PH2_R

7

2

1

@ PR77
47K_0402_1%

6
5

1

S

2
G

1

1

D

2

2

1

SPOK

PC71
1U_0402_6.3V6K

<29,37>

PR73
1K_0402_5%
1
2

3

B

1

B

G718TM1U_SOT23-8

2

@ PH2
100K_0402_1%_NCP15WF104F03RC

For 65W adapter==>action 70W , Recovery 54W
For 90W adapter==>action 97W , Recovery 75W
A

A

Compal Secret Data

Security Classification
Issued Date

2012/03/21

2013/03/21

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR-BATTERY CONN/OTP

Size Document Number
Custom

CHROME M/B LA-8942P Schematic

Date:

Friday, August 10, 2012

Sheet
1

35

of

46

Rev
0.1

B

C

D

1M_0402_5%

PC117
0.1U_0402_25V6

1

1

PC115
0.1U_0402_25V6
2
1

2

2

PC114
0.1U_0402_25V6

1

PC113
0.1U_0402_25V6
2
1

2

2

9012@ PR14
0.02_1206_1%

1

2N7002KW 1N SOT323-3

PR13

1
1

S

B+

2

PR12

1

PQ4
2
G

D

3

for reverse input protection

PC121
0.1U_0402_25V6

A

3M_0402_5%

1

change PR14 from 0.02 to 0.025
for ADP_I setting
B+

11

BQ24725_BATDRV

2

2

1

10

1

PR16
0_0402_5%

2

2

PC25
0.01U_0402_50V7K

1

4

2

1

PC37
0.01U_0402_50V7K

PC36
2200P_0402_50V7K

PC34
10U_0805_25V6K
2
1

PC33
10U_0805_25V6K
2
1

1
2

CSON1

PC38
0.1U_0402_25V6

1

1
2

CSOP1

1

PR26
4.7_1206_5%

2

2
1
2

PC148
100P_0402_50V8J

1
2

1

PC41
0.01U_0402_25V7K

2

1

ADP_I

BATT+

<29,35>

<29,35>

4

<29,35>

@ PC44
0.1U_0402_25V6

2

1

3

PQ11
2N7002KW 1N SOT323-3

3

1

PR33
100K_0402_1%

PR39
0_0402_5%
1
2

D

Compal Secret Data

Security Classification

S

2

PC147
100P_0402_50V8J

EC_SMB_CK1

@

EC_SMB_DA1
PC43

Issued Date

A

2

316K_0402_1%

@

100P_0402_50V8J

9,33,38,39,40> SUSP#

3

PR31

1

PC149
100P_0402_50V8J

PR37
66.5K_0402_1%

2

1
2

1

ACDET

2

2
G

ILIM

SCL
9

2

1
2

PR35
154K_0402_1%

2

280K_0402_1%

1

1

<29> FSTCHG

SDA

PR32

1

1 2
4

ACDET=
2.4 ~3.15 V
Vin=20.55~18.6V

PC42
1000P_0402_50V7K

PR34
2M_0402_1%

VIN

PQ10
PDTC115EU_SOT323-3

PR38
100K_0402_1%

+3VALW
BQ24725_ILIMT

PR36
2M_0402_1%

1
1

2

1.Change PR33 to 280K 0.1%
2.Chagee PR35 and PR36 to 0.1%.
3.Change PC30 to 1000P.
4.Add PR52,PR70,PR72,PQ17,PQ21.
5.Add GPIO pin,need check HW/EC.
6.Chanrge PR31 to 1K.

8

2

1K_0402_1%
ACDET

6

PR30

1

<15,29,33,37> ACIN

BATDRV
IOUT

ACOK

7

5

ACDET

2

10K_0402_1%

3

PC48
470P_0402_50V7K

SRN

3

330P_0402_50V7K
2
1

SRP

ACDRV

2

PC63
1

CMSRC

SRP1

2

PR27
10_0603_5%
2 CSOP1
PR28
6.8_0603_5%
12 SRN 1
2 CSON1

13

PR29

1

+3VLP

1

5

14

GND

3
2
1

ACP

4

DL_CHG

1

15

LODRV

PC39
680P_0402_50V7K

3
2
1

2
16
REGN

17
BTST

18
HIDRV

19

20
VCC

ACN

PL3
PR25
10UH_FDSD0630-H-100M-P3_3.8A_20%
0.01_1206_1%
1
2 CHG
1
4
BQ24725_LX

2

4

2

BATT+

PC31
1
2

PQ9
SIS412DN-T1-GE3_POWERPAK8-5

BQ24725_ACDRV

2

5

1

PQ8
SIS412DN-T1-GE3_POW ERPAK8-5

4

1

3

BATT_GATE

PD6
RB751V-40_SOD323-2

BQ24725ARGRR _VQFN20_3P5X3P5
BQ24725_CMSRC

470P_0402_50V7K PC17

2

1

PC22
330P_0402_50V7K
2
1

1

PC19
10U_0805_25V6K

2

1

PC18
10U_0805_25V6K

PR21
2.2_0603_5%

1
BQ24725_BST 2

DH_CHG

PR20
10_1206_1%
BQ24725_LX

PR23
1_0603_5%
1
2

DH_CHG

2
PC40
0.1U_0402_25V6

2

PAD

2

2

PHASE

1

BQ24725_BATDRV 1

PC35
0.1U_0402_25V6

1

0.1U_0402_25V6
2
1

1
BQ24725_VCC2

BQ24725_ACP

1

21
PC32
@ 2.2U_0805_25V6K

SIS412DN-T1-GE3_POW ERPAK8-5

@

PR17
4.12K_0603_1%

1U_0603_25V6K
PU1

1

2

@ PR24
3.3_1206_5%

PQ7

PC27

1U_0603_25V6K

1
2
3

5

0.047U_0402_25V7K

1

PC30
1
2
BQ24725_ACN

1 2

2

@ PR22
3.3_1206_5%

PC29
0.1U_0402_25V6

1

PR19
4.12K_0603_1%

2

1

PR18
4.12K_0603_1%

2

1

2

PC26
0.1U_0402_25V6

2

2

2

BAS40CW H_SOT323-3

1

PC28

BTB_GATE

VIN

1

PD5

PC23
2200P_0402_50V7K

2

2

4

VIN

2

PC20
470P_0402_50V7K

1

3

2

2

330P_0402_50V7K

5

PC16
1

1
2
3

CHG_B+

PL2
1UH_NRS4018T1R0NDGJ_3.2A_30%

932@ PR14
0.025_1206_1%
1
4

3

2

1
4

2

1

PC24
2200P_0402_50V7K

@

1

1
2
3

5

2

P2
PQ6
SIS412DN-T1-GE3_POW ERPAK8-5

PC15
0.1U_0402_25V6

P1
PQ5
SIS412DN-T1-GE3_POW ERPAK8-5

PR15
0_0402_5%

VIN

2012/03/21

Deciphered Date

2013/03/21

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C

Title

Compal Electronics, Inc.
PWR DCIN / Pre-charge

Size Document Number
Custom

CHROME M/B LA-8942P Schematic

Date:

Sheet

Friday, August 10, 2012
D

36

of

46

Rev
0.1

5

4

3

2

+3VLP

1

PC52

1

2
1U_0603_10V6K
@ PC99
100P_0402_50V8J
1
2

PR40
13.7K_0402_1%
1
2

PR41
30.9K_0402_1%
1
2

VFB=2V

VFB=2V

118K_0402_1%

VCLK

DRVL1

17

5

PC54
0.1U_0603_25V7K
2
1

3
2
1
1

UG_5V

2

PR69 2.2K_0402_5%
9012@
2
1

2

確確PR51

1

PR51 0_0402_5%
2

+5VALWP

1

1
3
2
1

Rds=13.5mΩ(min)
= 16.5mΩ(max)

PC62
1U_0603_10V6K

1

2

EN_5V

2

PQ15
SI7716ADN-T1-GE3_POW ERPAK8-5

VL
PC61
1U_0603_25V6K
2
1

1

RT8243_B+

2

+

4

+5VALWP

PR50 0_0402_5%
1
2
EN_3V

<29,35> MAINPWON

PC53
2200P_0402_50V7K
2
1

1
16

PR52

Rds=13.5mΩ(min)
= 16.5mΩ(max)

<29,30> EC_ON

PL6
4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20%

LG_3V

2.2_0603_1%
B

PC56
0.1U_0603_25V7K
1
2

LG_5V

1
2
3

ESR=17m ohm 2

PC51
4.7U_0805_25V6-K
2
1

LX_5V
PR47
2.2_0603_5%
1
2
BST_5V

2

VO1

VREG5

18

15

4

DRVH1

14

11

PQ14
SI7716ADN-T1-GE3_POW ERPAK8-5

VIN

DRVH2

DRVL2

5

10

SIS412DN-T1-GE3_POW ERPAK8-5

19

+
PC58
680P_0402_50V7K
2
1

PC57
220U_6.3V_M

VBST2
VBST1

UG_3V

C

4

ESR=17m ohm 2

PC59 220U_6.3V_M

1

PC55
0.1U_0603_25V7K

9

12

2
PR48
4.7_1206_5%
2
1

1

SW1

PR46
2 1
2BST_3V
2.2_0603_5%

1

EN_5V

TPS51225CRUKR_QFN20_3X3

SW2

13

1
2
3
PL5
4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20%

+3VALWP

8

LX_3V

20

PQ13

@ PR49
4.7_1206_5%

PGOOD

21

@ PC60
680P_0402_50V7K

EN1
7

PC50
4.7U_0805_25V6-K
2
1

2
PR45

1

3

4

2
VFB1

PAD

4

<29,35> SPOK

RT8243_B+

5

C

EN2

VREG3

6

EN_3V

VFB2

PU2

SIS412DN-T1-GE3_POW ERPAK8-5

CS2

PQ12

PR43
20K_0402_1%
1
2

CS1

2
5

5

CS2

PC49
2200P_0402_50V7K
2
1

PC47
10U_0805_25V6K
2
1

PC46
0.1U_0603_25V7K
2
1

B+

1

RT8243_B+
PL4
HCB2012KF-121T50_0805
1
2

D

FB_5V

1
PR44
95.3K_0402_1%

FB_3V

PR42
20K_0402_1%
1
2

CS1

D

@ PC85
100P_0402_50V8J
1
2

B

(1)SMPS1=300KHZ (+5VALWP)
(2)SMPS2=355KHZ (+3VALWP)

EN_5V3V

EN
Rising=1.6~0.3V

1

PR54 0_0402_5%
932@ PD11
LL4148_LL34-2
2
1

1

932@
PR53 0_0402_5%
2

2

VIN

932@ PR82
887K_0402_1%
1
2

D

5
G
932@ PQ22
S 932@ PQ35A
PDTC115EUA_SC70-3 DMN66D0LDW -7_SOT363-6
4

1

2

S

932@ PQ35B
DMN66D0LDW -7_SOT363-6

1

PC64
4.7U_0603_6.3V6M

D

2
G

VS

2

6

1

A

932@ PR108
412K_0402_1%
1
2

2
1
932@ PR56
100K_0402_1%

932@ PR109
1M_0402_1%
1
2

VL

VS

3 2
1
932@ PR107
10K_0402_1%

1

ACIN

@ PR55
0_0402_5%

+3.3VALWP
Ipeak=5.6A ; 1.2Ipeak=6.72A; Imax=3.92A
f=375KHz, L=4.7UH
Rdson=13~16m ohm
1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=1.48/2=0.74A
Vlimit=10*10^-6*150Kohm/10=0.15V
Ilimit=0.15/(16m*1.2)~0.15/(13m)=7.82A~11.53A
Iocp=7.7A (8.536A>8.4A -> ok)

+5VALWP
Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A
f=300KHz, L=4.7UH,Rentrip=154k ohm
Rdson=15~18m ohm
1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.63/2=0.815A
Vlimit=10*10^-6*154Kohm/10=0.15V
Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A
Iocp=14.2A

Compal Secret Data

Security Classification
2012/03/21

Deciphered Date

2013/03/21

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Compal Electronics, Inc.
3VALWP/5VALWP

3

Issued Date

A

Size
Document Number
Custom

CHROME M/B LA-8942P Schematic

Date:

Friday, August 10, 2012

Sheet
1

37

of

46

Rev
0.1

A

B

C

D

PJ18
1

1.5V_B+

1
2

5

+1.5VP

1

2

JUMP_43X79

PC72
10U_0805_25V6K

1

B+

2

1

@

PQ30
SIS412DN-T1-GE3_POW ERPAK8-5

1

4

PC76
0.1U_0603_25V7K
1
2
BST_1.5V-1

PL16
1

1
1

D

3

S

S3

S5

S0

Hi

Hi

On

On

S3

Lo

Hi

On

On

Lo

Lo

S4/S5

1.5VP

VTT_REFP

1

220U 2V Y D2 ESR15M
PC232

2
3
2
1

1
2

PGOOD

need change OCP setting

PC78
1U_0603_10V6K

@

PGOOD_1.5V

PR95
10.5K_0402_1%
2
1

3

PR169
10K_0402_1%

2
G

FB=0.75V
To GND = 1.5V
To VDD = 1.35V

2N7002KW _SOT323-3

STATE

+5VALW

2

PQ31

2
1
PR174
5.1_0603_5%

VDD_1.5V

+3VALW

PC100
100P_0402_50V8J
1
2

3

<33,39,40> SUSP

2

Rds=13.5mΩ(Typ)
16.5mΩ(Max)

2
1
PR97
10K_0402_5%
PC77
1U_0603_10V6K
2
1

8
S5_1.5V

S3
7
S3_1.5V
FB_1.5V

2

@ PC96
0.1U_0402_16V7K

2

PC325
0.1U_0402_16V7K

1

<29,33> SYSON

11

2

PC75
680P_0402_50V7K

PQ29
SI7716ADN-T1-GE3_POW ERPAK8-5

12

VDD

+

1.5V_TON
PR172
887K_0402_1%
2
1 1.5V_B+

PR171
0_0402_5%
1
2
1

<29,33,36,39,40> SUSP#

PR173
680K_0402_1%
1
2

TON

VDDQ

PR170
21.5K_0402_1%
2
1
1.5V_CS

13

CS
VDDP

FB

PC98
0.033U_0402_16V7K

VTTREF

6

1
2

5

+1.5VP

RT8207MZQW _W QFN20_3X3

10

+VTT_REFP

GND

14

PGND

S5

4

VTTSNS

1

2
4

LG_1.5V

1

15

LGATE

9

3

+1.5VP

PR175
4.7_1206_5%

2

2

2

1.5UH +-20% PCMC063T- 9A

5

LX_1.5V
16

PR96
0_0603_5%
1
2

PHASE

UG_1.5V
17
UGATE

19

VTTGND

BST_1.5V

2
LDO_IN

PAD

BOOT

1

VLDOIN

PU8
21

20

靠靠Output Cap PAD
VTT

1

PC73
10U_0805_25V6K

2

2

1

PC97
10U_0805_25V6K

+0.75VSP

18

2

3
2
1

1

PJ15
JUMP_43X79

 VFB=0.75V
V=0.75*(1+10K/10.5K)=1.52V
Fsw=286K to 200KHz

0.75VSP
On
Off
(Hi-Z)

Cout ESR=17m ohm Rdson(max)=16.5 mohm
Ipeak=12 A, Imax=8.4A, Iocp=14.4A

Off
Off
Off
(Discharge) (Discharge) (Discharge)

Rdson(typ)=13.5 mohm.

Delta I=((Vin-Vo)*(Vo/Vin))/(L*Fsw)=2.195A
=>1/2Delta I=1.099A
Iocpmax=((21.5K*11uA)/0.0135)+0.5 delta I= A
Iocpmin=((21.5K*9uA)/(0.0165))+0.5 delta I=15.6A

4

Note: S3 - sleep ; S5 - power off

Compal Secret Data

Security Classification
Issued Date

4

2012/03/21

Deciphered Date

2013/03/21

Title

Compal Electronics, Inc.
PWR-+1.5VP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHROME M/B LA-8942P Schematic

Date:

A

B

C

Friday, August 10, 2012

Sheet
D

38

of

46

Rev
0.1

4

3

2

1

3

5

+1.8VSP
1

4

DMN66D0LDW-7_SOT363-6
PQ34B
@

PC80
68P_0402_50V8J
2
1

5

<33,38,40> SUSP
D

2

PR84
20K_0402_1%
PU6

3

EN

FB

GND

PG

LX

6

FB_1.8V
FB=0.6Volt

5
4

IN

PR87
10K_0402_1%

SY8032ABC_SOT23-6

PL9
1UH +-20% VMPI0703AR-1R0M-Z01 11A
2
1LX_1.8V

PJ16
1

8032_IN

1

2

2

+3VALW

@
2

PC79
22U_0805_6.3V6M

1

4.7_0603_5%
PR83
2
1

JUMP_43X79

680P_0402_50V7K
PC84
2
1

22U_0805_6.3V6M
PC82
2
1

+1.8VSP

22U_0805_6.3V6M
PC81
2
1

2
1

PC83
0.1U_0402_10V7K

2

PR86
1M_0402_5%

2

1

1

EN_1.8V

2

2

PR85 200K_0402_5%

1

1

<29,33,36,38,40> SUSP#

D

1.8VSP
Ipeak=1.24A
Vout=0.6*(1+(20K/10K))=1.8V

C

C

PG

VOUT
VID1

EN
VID0

1

3

SA_PGOOD

PR89
100K_0402_5%
1
2

4
5

1

+VCCSA_EN

2

PR90
0_0402_5%

6

<29>

+3VS

2

1

B

100P_0402_50V8J

2

1

PC146

1

PR88
4.7_0603_5%

VCCPPWRGOOD

<40>

PC145
100P_0402_50V8J
@

@ PC94
680P_0402_50V7K

2

13

@
FB_VCCSA

+VCCSAP

@

PC93
2200P_0402_50V7K
2
1

LX

FB

2

7

SVIN

2

PC92
22U_0805_6.3V6M
1
2

8

LX

PL10
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2

+VCCSA_PHASE

PC91
22U_0805_6.3V6M
1
2

10
PC88
68P_0402_50V8J
2
1 FB_VCCSA_IC9

PVIN

1

PC90
.1U_0402_16V7K
2
1

2

11

LX

2

1

PVIN

1

JUMP_43X79

12

+VCCSA_PWR_SRC

GND

2

PC89
22U_0805_6.3V6M
1
2

2

PC87
0.1U_0402_25V6
1
2

1

PC86
2200P_0402_50V7K

1

SY8037DDCC DFN 12P

PU7

PJ17

+3VALW

@ PC95
.1U_0402_16V7K

H_VCCSA_VID0
PR91
1K_0402_5%
2
1

<9>

B

The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.

PR92
1K_0402_5%
2
1

H_VCCSA_VID1

PR93
100_0402_1%
2
1

<9>

PR94
0_0402_5%
2
1

+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A

A

VID [0]
0
0
1
1

VCCSA_SENSE

<9>

VID[1]
0
1
0
1

VCCSA Vout(ULV only)
0.9V
0.85V
0.775V
0.75V

A

output voltage adjustable network

Compal Secret Data

Security Classification
Issued Date

2012/03/21

Deciphered Date

2013/03/21

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PWR +VCCSAP
Size
C
Date:

5

4

3

2

Compal Electronics, Inc.
Document Number

Rev
0.1

CHROME M/B LA-8942P Schematic
Friday, August 10, 2012

Sheet
1

39

of

46

5

4

3

2

1

D

D

PL11
HCB2012KF-121T50_0805

2

2

4

3
2
1

1

TP

LG_1.05V

11

TPS51212DSCR_SON10_3X3

PQ24
AO4456_SO8
PC111
4.7U_0805_10V6K

2
2

SUSP

1

<33,38,39>

Rds=4.5mΩ(min)- 5.6mΩ(Max)

1

1

2

1

PC104
0.1U_0402_25V6
2
1

1

+

2

B

PR176

2

1

1

2

VCCIO_SENSE

<8>

100_0402_1%

2

1000P_0402_50V7K 1.2K_0402_1%
PC122
PR186


2

PR106
10K_0402_1%

A

1

DMN66D0LDW -7_SOT363-6
PQ34A
@

1
2
4.99K_0402_1%
PR188

 VFB=0.75V
V=0.704*(1+4.02K/10K)=1.052V
Fsw=290KHz

PC103
2200P_0402_50V7K
2
1

1

PC102
4.7U_0805_25V6-K

PC112
680P_0603_50V7K

2

6

FB_1.05V

2

PR104
470K_0402_1%

B

PR102
4.7_1206_5%

4
6

2

1

5
6
7
8
+5VALW

C

330U_D2_2V_Y_R9
PC257

DRVL

LX_1.05V

7

2

TST

8

2200P_0402_50V7K

V5IN

PC105
0.1U_0402_25V6

+1.05VSP

PC110

SW

VFB

UG_1.05V

PC109
0.1U_0402_25V6
2
1

5

VFB=0.7V

EN

9

PC124
0.1U_0402_25V6

PC107
0.1U_0402_16V7K

DRVH

1

4

VBST

TRIP

B+

1

PL12
1UH +-20% VMPI0703AR-11A
1
2

2

3

PGOOD

BST_1.05V

1

2

2

10

2

1.05V_EN

2

@ PR103
30K_0402_5%

84.5K_0402_1%
2
1

1

SUSP#

1

33,36,38,39>

PR100

PR101
330K_0402_1%
1
2

PR99
PC106
2.2_0603_5%
0.1U_0603_25V7K
1
2 BST_1.05V-1 1
2

PU9

1

VCCPPW RGOOD

1

<39>

3
2
1

1

PR98
10K_0402_1%

2

1

+1.05VSP

PQ23
SIS412DN-T1-GE3_POWERPAK8-5

5

C

PC101
4.7U_0805_25V6-K

1.05V_B+

Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.
Ipeak=15.6A, Imax=10.92A, Iocp=18.72A

A

Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=2.06A
Iocpmax=((15K*11uA)/0.0045)+1.665A=23.54A
Iocpmin=((15K*9uA)/(0.0056*1.3))+1.665A=19A
Iocp=A

Compal Secret Data

Security Classification
2012/03/21

Issued Date

Deciphered Date

2013/03/21

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR +1.05VS_VCCPP/+0.75VSP

Size
Document Number
Custom

CHROME M/B LA-8942P Schematic

Date:

Friday, August 10, 2012

Sheet
1

40

of

46

Rev
0.1

C

D

E

+GFX_B+

@ PC125
1000P_0402_50V7K

2 2

1

2

0.1U_0402_25V6

1
2

1
2

PC131
10U_0805_25V6K

PC130
10U_0805_25V6K

5
4

UGA_GFX

1
+
PC132

MDV1525URH
PL15
0.22UH 20% FDUE0640J-H-R22M=P3 25A
2
1

2

2

1
1 2

PR138
1_0402_5%

PC135
680P_0402_50V7K

1

1

PC194
470P_0402_50V7K

PHASEA_GFX

PR130
3.65K_0402_1%

VSUMG-

UGA_GFX

2

2
1
BOOTA_GFX

PR154
4.7_0603_5%

VSUMG+

5
4

LGA_GFX

LGA_GFX

1

1
PR159
0_0603_5%

2

2

@PR185
@
PR185
2

19

LG1_CPU

1.91K_0402_1%
1

18

PHASE1_CPU

17

UG1_CPU

PC261
1U_0603_10V6K
2
1

20

PR179
2
UG1_CPU

0_0603_5%
1
UG1_CPU-1

4

PC21
470P_0402_50V7K

2

PC45
1

330P_0402_50V7K
2
1

PC116
33U_25V_M

2
1

1

2

2

PR137
1_0402_5%
1

1

PC123
PR128
680P_0402_50V7K 4.7_0603_5%

1
2
1
2

PQ33
MDU1511RH_POWERDFN56-8-5

2.61K_0402_1%

1
PR180
1 2

1
11K_0402_1%
2
PR184

2

VSUM-

10K_0402_1%_ERTJ0EG103FA
2

1

PC259
0.1U_0603_25V7K

1
2

PC169
0.068U_0402_16V7K

PR187
324_0402_1%

2

PR129
3.65K_0402_1%

VSUM+

Close Phase 1 choke

VSUM-

+CPU_CORE
Load line= -2.9 mohm
0.22uH DCR= 1.1~1.3 m ohm

.1U_0402_16V7K

local sense revese HW

3

PH3

PC266
2
1

PC264
150P_0402_50V8J
2
1
2
1
PR190
137K_0402_1%

1

PC143
PR146
2200P_0402_50V7K 649 +-1% 0402
2
1
2
1

PC170
68P_0402_50V8J
2
1

LG1_CPU

PR189
1.91K_0402_1%
2
1

VSUM+

4

3
2
1

4

PL14
0.22UH_PCMB104T-R22MS_35A_20%
2
1

5

5 3
2
1

PC171
0.1U_0603_25V7K
1 2
1

@ PQ26
@PQ26

1
PR183
499_0402_1%

2

B+

+CPU_CORE

PR177
42.2K_0402_1%
2
1

PC260
470P_0402_50V7K
2
1
2

+

MDU1516URH_POWERDFN56-8-5

PHASE1_CPU
PR181
2.2_0603_5%
BOOT_CPU 2

MDU1511RH_POWERDFN56-8-5

2

1

PH5
470KB_0402_5%_ERTJ0EV474J

1

HCB2012KF-121T50_0805
2
1

PQ25

+3VS

LG1_CPU

PR203
2K_0402_1%
2
1

PC119
10U_0805_25V6K

<15>

PC120
0.1U_0402_25V6

1.91K_0402_1%
1

2

1
2
VGATE
PR202
2

5

@PR197
@
PR197
0_0402_5%

3

PC162
470P_0402_50V7K
2
1

PL18

+CPU_B+
BOOT_CPU

2

+5VS

2

21

PC118
10U_0805_25V6K

BOOT1

PC258
1U_0603_10V6K
1
2

25
UGATEG

27

28

29

30

31

26
BOOTG

PGOODG

COMPG

FBG

RTNG

32
9

UGATE1

22

3
2
1

1
2

PHASE1

ISEN2

23

PR162
1_0603_5%

PR204
3.83K_0402_1%

2

@PC126
@
PC126
0.1U_0402_16V7K

PR201
61.9K_0402_1%

1

1
2

+1.05VS_VTT

NTC

+5VS

@

1

1

@

2
PR156
130_0402_1%
1
2
PR200
75_0402_5%
1
2
PR160
54.9_0402_1%

2
PR168
0_0402_5%

@

8

PR196
0_0402_5%

1

1

@ PC263
47P_0402_50V8J

2

LGATE1

24

GT2
Iccmax=29A
Max Istep=13A
PS1 current=20A
TDP=18.3A

+GFX_CORE
Load line = -3.9m ohm
0.22uH DCR= 0.97+-5% m ohm

16

7
1

VR_HOT#

PGOOD

VR_HOT

PWM2

COMP

<29>

VDD

SDA

15

5

FB

SVID_DATA

ISL95833HRTZ-T_TQFN32_4X4

14

SVID_DATA

ALERT#

13

<8>

SVID_ALERT# 4

VCCP

RTN

SVID_ALERT#

LGATEG

SCLK

12

<8>

VR_ON

ISUMN

3

PHASEG

11

2

ISUMNG

PAD

2
0_0402_5%

NTCG

ISUMP

SVID_CLK

ISUMPG

1

SVID_CLK

<8>

2

@

1
PR165

VR_ON

1 PH4
NTCG
470KB_0402_5%_ERTJ0EV474J

6

PC163
100P_0402_50V8J
2
1 SVID_CLK

@

PC161
100P_0402_50V8J
2
1 SVID_ALERT#

PC144
100P_0402_50V8J
2
1
SVID_DATA

<29>

2

ISEN1

PR158
3.83K_0402_1%
1
2

10

2

33

+5VS
PU13
PR152
61.9K_0402_1%
2
1

+VGFX_CORE

SH00000O200

PQ28
MDU1511RH_POWERDFN56-8-5

1

0.1U_0603_25V7K
PC183
2
1 2
1
BOOTA_GFX
PR182 2.2_0603_5%

PR205
2K_0402_1%

PR147

2

PQ27
2
1
PR140
2.55K_0402_1%
PHASEA_GFX

2
1
1.91K_0402_1%

VSUMG+

+3VS

PC134
470P_0402_50V7K
2
1
2
1
PR134
499_0402_1%

2
1
PR143
33.2K_0402_1%

PC141
0.022U_0402_25V7K
2
1

PC140
0.1U_0603_25V7K
1
2

PC136
150P_0402_50V8J
2
1
2
1
PR136
137K_0402_1%

3
2
1

PC133
68P_0402_50V8J
2
1
PR135
430_0402_1%
2
1

2

PR142
11K_0402_1%
1
2

PR141
2.61K_0402_1%
1
2 1

2

B+
1

3
2
1

1

PC127
0.01UF_0402_25V7K

PL17

HCB2012KF-121T50_0805
2
1

2

PR139
649 +-1% 0402
1
2

PC142
<9> VSS_GFXSENSE
2200P_0402_50V7K

PH6
10K_0402_1%_ERTJ0EG103FA
VSUMG-

.1U_0402_16V7K
PC137
2
1

VCC_GFXSENSE

1

<9>

local sense revese HW

1

PC160
33U_25V_M

B

1

A

ICCMAX=33A
I tdc=15.8~ 20 (Tdc-up)A
PS1=20A
Max Istep=28A

@PC265
@
PC265
330P_0402_50V7K
2
1
<8>
<8>

VCCSENSE
VSSSENSE

2

1

PC262
0.01UF_0402_25V7K

4

4

local sense revese HW

Compal Secret Data

Security Classification
Issued Date

2012/03/21

Deciphered Date

2013/03/21

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CPU/GFX_CORE

CHROME M/B LA-8942P Schematic

Date:

A

B

C

D

Friday, August 10, 2012

Sheet
E

41

of

46

Rev
0.1

1U_0402_6.3V6K
PC244

330U_D2_2V_Y

PC210
10U_0603_6.3V6M
2
1
PC211
10U_0603_6.3V6M
2
1
PC212
10U_0603_6.3V6M
2
1
PC213
10U_0603_6.3V6M
2
1
PC214
10U_0603_6.3V6M
2
1
PC215
10U_0603_6.3V6M
2
1
PC216
10U_0603_6.3V6M
2
1
PC217
10U_0603_6.3V6M
2
1
PC218
10U_0603_6.3V6M
2
1
PC224
10U_0603_6.3V6M
2
1

1U_0402_6.3V6K
PC223
1U_0402_6.3V6K
PC222
1U_0402_6.3V6K
PC221
1U_0402_6.3V6K
PC220
1U_0402_6.3V6K
PC219

PC203

2
2

1
1

1U_0402_6.3V6K
PC209
1U_0402_6.3V6K
PC208
1U_0402_6.3V6K
PC207
1U_0402_6.3V6K
PC206
1U_0402_6.3V6K
PC205

330U_D2_2V_Y
PC182
330U_D2_2V_Y
PC181
330U_D2_2V_Y
PC180
330U_D2_2V_Y
PC179

PC185
330U_D2_2V_Y
PC184
330U_D2_2V_Y

PC178
10U_0603_6.3V6M
2
1
PC177
10U_0603_6.3V6M
2
1
PC176
10U_0603_6.3V6M
2
1
PC175
10U_0603_6.3V6M
2
1
PC174
10U_0603_6.3V6M
2
1
PC173
10U_0603_6.3V6M
2
1

PC172
22U_0805_6.3V6M

PC168
22U_0805_6.3V6M

PC167
22U_0805_6.3V6M

PC166
22U_0805_6.3V6M

PC165
22U_0805_6.3V6M

1U_0402_6.3V6K
PC227
1U_0402_6.3V6K
PC225
1U_0402_6.3V6K
PC226
1U_0402_6.3V6K
PC228
1U_0402_6.3V6K
PC229
1U_0402_6.3V6K
PC235
1U_0402_6.3V6K
PC230
1U_0402_6.3V6K
PC231
1U_0402_6.3V6K
PC236
1U_0402_6.3V6K
PC237
1U_0402_6.3V6K
PC238
1U_0402_6.3V6K
PC240

PWR - PROCESSOR DECOUPLING

1U_0402_6.3V6K
PC242
1U_0402_6.3V6K
PC241
1U_0402_6.3V6K
PC243
1U_0402_6.3V6K
PC245
1U_0402_6.3V6K
PC247
1U_0402_6.3V6K
PC246
1U_0402_6.3V6K
PC248
1U_0402_6.3V6K
PC250
1U_0402_6.3V6K
PC249
1U_0402_6.3V6K
PC251
1U_0402_6.3V6K
PC252
1U_0402_6.3V6K
PC253

CHROME M/B LA-8942P Schematic

46
of
42
Sheet

Rev
0.1
Document Number
Size

Friday, August 10, 2012
Date:

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.
Compal Secret Data

1
2

2
2
2
2
2

2013/03/21
Deciphered Date
2012/03/21
Issued Date

1U_0402_6.3V6K
PC204

PC108
470P_0402_50V7K

PC202
2.2U_0402_6.3V6M

PC201
2.2U_0402_6.3V6M

PC200
2.2U_0402_6.3V6M

PC199
2.2U_0402_6.3V6M

PC198
2.2U_0402_6.3V6M

PC197
2.2U_0402_6.3V6M

PC196
2.2U_0402_6.3V6M

1U_0402_6.3V6K
PC239

2

PC159
22U_0805_6.3V6M

PC158
22U_0805_6.3V6M
PC233
22U_0805_6.3V6M

PC234
22U_0805_6.3V6M

PC74
330P_0402_50V7K

PC193
2.2U_0402_6.3V6M

PC192
2.2U_0402_6.3V6M

PC191
2.2U_0402_6.3V6M

PC190
2.2U_0402_6.3V6M

PC189
2.2U_0402_6.3V6M

PC188
2.2U_0402_6.3V6M

PC187
2.2U_0402_6.3V6M

PC195
2.2U_0402_6.3V6M

+

3
4

PC157
22U_0805_6.3V6M

PC156
22U_0805_6.3V6M

PC155
22U_0805_6.3V6M

PC154
22U_0805_6.3V6M

PC153
22U_0805_6.3V6M

PC152
22U_0805_6.3V6M

PC151
22U_0805_6.3V6M

PC186
2.2U_0402_6.3V6M

1U_0402_6.3V6K
PC254

1

Mid-Frequency Decoupling
10x10µF
+1.05VS_VTT

1
1

1
1
1
1

1
1
1

2
2
2
2
2
2

2
2

A

Low-Frequency
Decoupling 1x330 µF 9m
A

Security Classification
2
2
2
2
2
2
2
2
2
2
2
2
2

5

1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2

1
1
1
1

1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

2
2
2

High-Frequency Decoupling
27x1µF
+1.05VS_VTT

B
B

1

High-Frequency Decoupling
16x2.2µF
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

1
1
1

PC150
22U_0805_6.3V6M

+CPU_CORE

1
1

Low-Frequency
Decoupling 2x330 µF 9m
+
+

Low-Frequency
Decoupling 3x330 µF 9m

High-Frequency Decoupling
11x1µF
+

1
1

+

1

2
2
2
2

PC164
22U_0805_6.3V6M

Mid-Frequency Decoupling
12x22µF

1
1
2
2
2
2

1
1
1
1
1

C

1
@

+
+

2
2
2
2
2
2
2
2

1
1
C

1
1
1
1

D

2
2
2
2
2
2
D

Mid-Frequency Decoupling
6x10µF 0603
1
1
1
1
1
1
1
1

1
1
1
1
1
1

+VGFX_CORE
+VGFX_CORE

Mid-Frequency Decoupling
6x22µF
+CPU_CORE

1
2
3
4
5

CR PDDG Rev 0.95

5

4

3

2

Version change list (P.I.R. List)
Item

D

Fixed Issue

Page 1 of 1
for PWR
Reason for change

Rev.

PG#

1

Modify DCIN/Pre-change power circuit

0.1

34

2

Modify Battery CONN/OTP power circuit

0.1

35

3

Modify CHARGER

0.1

36

4

Modify 3VALWP/5VALWP power circuit

0.1

37

5

Modify 1.5VP/0.75VSP power circuit

0.1

6

Modify 1.05VS power circuit

0.1

Modify List

Date

Add PC301 330P_0402_50V7K,
PC302 470P_0402_50V7K for EMI solution

Phase

2012/4/5

EVT

2012/4/5

EVT

2012/4/5

EVT

Add Snubber PR48 4.7_1206_5%,
PC58 680P_0402_50V7K for EMI solution

2012/4/5

EVT

38

Add Snubber PR175 4.7_1206_5%,
PC75 680P_0402_50V7K for EMI solution

2012/4/5

EVT

40

Delete PR105 5.1K_0402_1%; PR178 0_0402_5%,
Add PR188 4.99K_0402_1%; PR186 1.2K_0402_1%,
PC122 1000P_0402_50V7K; PC124 0.1U_0402_25V6
for improve load response

2012/4/5

EVT

C

B

1

Add PR80 0ohm to GND for BOM control
(9012 AGND)
Add PC16,PC63 330P_0402_50V7K,
PC20, PC48 470P_0402_50V7K,
PC113, PC114, PC115, PC117, PC121 0.1U_0402_25V6
PR26 4.7_1206_5%, PC39 680P_0402_50V7K
for EMI solution

D

C

7

Modify CPU/GFX_CORE power circuit

0.1

41

Add PC45 330P_0402_50V7K,
PC21 470P_0402_50V7K for EMI solution
Add PC169 0.047I_0402_25V7K,
change PR187 from 523 to 348_0402_1%
change PR135 from 412 to 430_0402_1%

2012/4/5

EVT

8

Modify CPU/GFX_CORE power circuit

0.1

41

change PL14 from 0.22U_PCMB104T-R22MS_35A_20%
to 0.22UH MMD-10RCZ-R22M-28A (from H=3 to H=4)
change PR201, PR152 from 27.4K to 61.9K_0402_1%,
2012/4/5
change PH4,PH5 470K_0402_5%(from Thinking to Panasonic)
thermal issue

EVT

9

Modify PROCESSOR DECOUPLING power circuit

0.1

42

Add PC74 330P_0402_50V7K,
PC108 470P_0402_50V7K for EMI solution

2012/4/5

EVT

10

Modify DCIN/Pre-change power circuit

0.1

34

Sawp PC10 and PC301;
Sawp PC14 and PC302

2012/4/5

EVT

2012/4/18

EVT

2012/4/26

EVT

2012/4/26

EVT

2012/4/26

EVT

B

11

Modify Battery CONN/OTP power circuit

0.1

35

Add PR105 0ohm to GND for BOM control
(9012 H_PROCHOT#_EC)
change PR61 from 21K to 21.5K and
PR66 from 9.53K to 9.76K for
92 throttling and 56C recovery

12

Modify Battery CONN/OTP power circuit

0.1

35

Delete PR78 and add PR61, PR63 for EC932,
change PR66 from 9.53kohm to 9.76k ohm,
OTP setting 92C thermal protection, 56C recovery

13

Modify 3VALWP/5VALWP power circuit

0.1

37

14

Modify CPU/GFX_CORE power circuit

0.1

41

Change PR56 from 402K to 100K
for 3V/5V enable setting,
Add PR53 for 3V/5V enable setting.
change PR187 from 348 to 324 for OCP 40A fine tune,
change PC169 from 0.047U to 0.068U (RC match)

A

A

15

Modify CHARGER

0.1

36

change PC22 from 0.1U_0402_25V6 to 330P_0402_50V7K

2012/03/21

Deciphered Date

EVT

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

2012/5/2

2013/03/21

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PIR1 (PWR)

CHROME M/B LA-8942P Schematic

Date:

5

4

3

2

Friday, August 10, 2012

Sheet
1

43

of

46

Rev
0.1

5

4

3

2

Version change list (P.I.R. List)
Item
D

Fixed Issue

1

Page 1 of 1
for PWR
Reason for change

PG#

Modify List

Date

Phase

0.2

35

change PR63 from 2.26K to 590 ohm,
PR68 from 9.1 to 1.91K
From 46.2W~38W to 42.8W~33.2W

2012/5/7

EVT

1

Modify Prochot# setting from
G718(EVT MEMO introction)

2

Modify Battery CONN/OTP power circuit
Modify 3VALWP/5VALWP power circuit

0.2

35
37

Sawp PR81 and PR82 location
leverage Mimic winsows

2012/5/17

DVT

Modify Battery CONN/OTP power circuit

0.2

35

Add PR111 between
3VLP and battery connect TH for EC932

2012/5/23

DVT

Remove PQ16 PC302 PR10 PR11

0.2

3

KB9012 to

Rev.

34

Remove 51ON#

RC, BATT+ to VS switch
2012/5/23

4
MAINPWON double pull high.

0.2

35

D

Remove PR64
2012/5/23

5
C

C

6

Modify 3v5v EN pin voltage (from 4.9V
to 4.524V) for EN pin rating.

7

Modify 3v5v EN pin voltage
EN pin rating.

for

0.2

35

0.3

35

Change PR108 from 316K to 412K.

Change PR82 from 1000K to 887K.

2012/5/23

2012/7/9

PVT

8
9
B

B

10
11

12

13

14
A

A

15
2012/03/21

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2013/03/21

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PIR1 (PWR)

CHROME M/B LA-8942P Schematic

Date:

5

4

3

2

Friday, August 10, 2012

Sheet
1

44

of

46

Rev
0.1

5

4

3

(PU13)
RT8167BGQW

VR_ON

WQFN40

ADAPTER
D

SYSON

SON10

+1.5VS

+1.5V_CPU_VDDQ

+1.05VS_VTT

Page 40
PJ4

+VCCSAP

DFN12

CHARGER

PJ11 & PJ12

+1.05VSP

(PU7)
SY8037DCC

VCCPPWRGOOD

J1

Page 33

+0.75VS

Page 38

D

(U38)
AO4478L_SO8

SUSP

+1.5V

(PU9)
TPS51212DSCR

SUSP#

BATTERY

+VGFX_CORE

Page 41

WQFN20

1

+CPU_CORE

(PU8)
RT8207MZQW

SUSP#

B+

2

+VCCSA

Page 39

(PU2)
RT8243BZQW

EC_ON
MAINPWON

WQFN20

Page 37

C

C

+LED_VOUT
+5VALW
SUSP

SYSON#

(U35)
AO4478L
SOP8

PCH_PWR_EN#

(U28)
G547I2P81U
Page 33

+5VS

R630

+3VALW
PCH_PWR_EN#

(Q8)
AP2301GN-HF

MSOP8

SOT23-3

+USB3_VCCA

Page 20

+5VREF_SUS

PCH_PWR_EN#

(Q68)
AP2301GN-HF
SOT23-3

+3VALW_PCH

R285

Q37

SUSP

R359

Page 20

SOP8

+VCCSUS3_3

+3V_LAN

WLAN_ON

(U37)
AO4478L

+3VALW_EC

+3VS_WLAN
Page 33

MSOP8

+3VS

Page 26

+SDPWR_MMCPWR
PCH_ENVDD

(U25)
BCM57785

+CRT_VCC

CR_PWR_EN

(U27)
AP2301MPG

B

+DVDD_AUDIO

(Q10)
AO3419L
SO23-3

+HDMI_5V_OUT
J4

+1.2V_LAN

+3VS_WLAN

B

Page 22

+LCDVDD

+5VS_HDD
R453

+VDDA

(U34)
ALC271X-VB6

+CAM_VCC

TPM
(U33)
APL5607KI-TRG
TP

A

A

Compal Secret Data

Security Classification
Issued Date

2012/03/21

2013/03/21

Deciphered Date

Title

Compal Electronics, Inc.
Power Rail

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CHROME M/B LA-8942P Schematic

Date:

5

4

3

2

Friday, August 10, 2012

Sheet
1

45

of

46

Rev
0.1

5

4

3

2

1

D

D

2

B7

EC_ON

B6

U19

PM_DRAM_PWRGD

PBTN_OUT#

14
15

U2

CPU

H_CPUPWRGD
PLT_RST#

UCPU1
C

6

PU8
+1.5VP
U35
+5VS

8

11
VGATE

V

SUSP#,SUSP

V

SYSON#

U37
+3VS

V

7

U38
+1.5VS

V

SYSON

V

V

V

A4

13

PCH
U16

PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_A#
PM_SLP_SUS#

C

ON/OFF

PCH_RSMRST#

5

SYS_PWROK

V

4

U30

V V

51ON#

9012_PCH_PWROK

EC
A5

10

PU6
+1.8VS

V

V

PQ17
B3

V

+5VALW
B4

V

B+

V

B2

PCH_PWROK

2

V V

B1

B7

V V

+3VALW

2

V V

PU2

A5

V

B+

BATT

+VCCDSW3_3
+5VREF_SUS

3

B5

V

PU1

A3

VV

A2

V

V V

VIN

V

BATT
MODE

Q68,+VCCDSW3_3
Q8,+5VREF_SUS

A1

V

AC
MODE

V

PCH_PWR_EN#

PU8
+0.75VSP

B

B

V

PU9
+1.05VSP

VCCPPWRGOOD

PU7
+VCCSAP

9

V

V

SUSP#,SUSP

PU10
+CPU_CORE
+VGFX_CORE

VR_ON
A

Compal Secret Data

Security Classification
Issued Date

A

2012/03/21

2013/03/21

Deciphered Date

Title

Compal Electronics, Inc.
Power sequence

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

CHROME M/B LA-8942P Schematic

Date:

5

4

3

2

Friday, August 10, 2012

Sheet
1

46

of

46

www.s-manuals.com
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