Compal LA A061P Schematics. Www.s Manuals.com. R1.0 Schematics

User Manual: Motherboard Compal LA-A061P ZEA00 - Schematics. Free.

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A

B

C

D

E

1

1

Compal Confidential
C560 LA-A061P Schematics Document

2

2

INTEL Haswell CPU with DDRIII + PCH Lynx-Point
AIO M/B
September 24, 2013
3

3

REV:1.0

4

4

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Cover Page
Rev
0.3

ZEA00 LA-A061P M/B

Date:

A

B

C

D

Tuesday, September 24, 2013

Sheet
E

1

of

59

A

LVDS Conn.

B

LVDS

LVDS Converter
RTD2136R

C

D

Intel CPU
Haswell
Desktop

DP
PCI-Expressx8
HDMI

E

Memory BUS(DDRIII) 204pin DDR3/L-SO-DIMM X2
Dual Channel

1.5V DDR3 1333/1600 MHz

LGA1150

1

FDI

1

DMI

DIS Only
SATA port 0

DDR3 VRAMx4pcs
1GB/2GB

VGA Chip
N14M-GE2-B-AIO
GeForce 705M,29x29mm

SATA port 1

SATA ODD Conn.
USB3.0 conn.

USB 3.0 X2
USB 2.0 X2

PCIE or SATA
(By BOM Control)
USB2.0

2

Intel PCH
LynxPoint
H81

HDMI OUT conn.
PCIE

LAN_RTL8111G
10/100/1G

RJ45 conn.

3.5" SATA HDD Conn.

PCIE
USB2.0

PCIE

USB Charger_TPS2546

USB3.0 conn.

PCIE Mini Card conn.
TV Card or m-SATA SSD

2

BCAS Card conn.

PCIe Mini Card conn.
WLAN
Card Reader conn.
6 in 1

Card reader IC_RTS5229
(SD/SDHC/SDXC/MMC/MS/MS-Pro)

USB2.0
conn.

USB2.0
conn.

USB 2.0
USB 2.0 X 4
USB 2.0

VGA Conn.
(Reserve)

IR(Reserve)

VGA

Camera+MIC

HD Audio

LPC BUS

EC
ENE KB9012

Touch conn.

FCBGA-708
23mm x 22mm

3

D-Mic/A-Mic

Audio Codec
ALC272-VA4

MIC Jack
HPOUT

USB2.0
conn.

LINEOUT

3

USB2.0
conn.

SPK AMP
ALC109

SPI

SPI ROM
(8MBx1)

4

3W SPK *2
Conn

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/01

Issued Date

4

HP Jack

Deciphered Date

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Block Diagram
Rev
0.3

ZEA00 LA-A061P M/B

Date:

A

B

C

D

Tuesday, September 24, 2013

Sheet
E

2

of

59

5

4

PU13

3

2

1

+VGA_CORE

ISL62881C

+CPU_B+

Bead

+CPU_CORE

PU9,10,11,12
NCP5911MNTBG

+GFX_CORE

+CPU_CORE
+GFX_CORE

1.5V

D

PU4
APL5610CI
PU5

Intel Sandy Bridge

+1.8VS

+1.05VS_VCCIOP

+VCCSA

JUMP

CPU

D

+VCCSA
+1.05VS_VCCIO

+1.05VS_VCCIO

JUMP

TPS51212DSCR

+VCCSAP

JUMP

+1.05VS_VPCH

+5VALWP
JDCIN1

RT8243_B+

Beat

B+

PU2

+3VALWP

RT8243BZQW

+5VALW

JUMP

+5VALW

Q61

+5VS

AP4800BGM
+3VALW

JUMP

PU3

+1.8VSP

APL5930KAI
+3VALW

JUMP

JUMP

+1.8VS
PU6

+1.5VP

RT8207MZQW

C

+1.5V

JUMP

C

+1.5V

Q60
+0.75VSP

AP4800BGM

+12VS

U69

FAN1

AO4304L

+3VS

+1.5VS_VGA

PU7

JUMP

TPS54331DR

+1.5V

+12VSP

+1.5V
+0.75VS

+0.75VS

JUMP

DDR3 SODIMM X 2

+3VS

MOS
+1.5VS

+1.8VS
+12VS

B+

+12VS

+3VALW_PCH

+3VALW_PCH

LCD

Intel Shark bay

+1.05VS_VPCH

+3VS

Converter

PCH

H81

+3VS

RTC

+RTCVCC

+5VS

Battery

+5VS

AMP X 2
B

VRAM X 8

+3VALW

+1.5VS_VGA

MOS

+5VALW

MOS
+1.05VS_VGA

U11

APL3510BKI

Conn

MOS

APL5930KAI

MOS

Scaler

Mini Card

Conn

WLAN

+12VS

+5VS

+5VS

+5VS

EC

Mini Card

SATA HDD

LVDS CONN

A

RTD2136R

+LCDVDD

+5VALW

+3VALW

+3VS

+1.05V

+3V_LAN

+3V

+3VALW

+3VS

+12VS

1.5VS

1.5VS

+3VS

+3VALW

+5VALW

Power/B

MOS

+3VS

+3VS

+3VALW

+3VALW_MINI

ALC272

Issued Date

2013/04/01

Deciphered Date

2014/04/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

CAM

A

+Digital Mic

Title

Power Tree
Size

Document Number

Rev
0.3

ZEA00 LA-A061P M/B
Date:

5

+3VS

Compal Electronics, Inc.

Compal Secret Data

Security Classification

+3VS

Audio codec

SATA ODD

KB9012

(TV)

RTS5229

VGA

+3VS_VGA

+5VALW

+3VS

+3V_SCA

Media card
controller

N14M-GE2

+VGA_CORE

+3VS

RT9701

U3

MOS

U34

+5VS

USB3.0 X 2

U33

+USB_VCCB

U46

+USB_VCCA

+USB_VCCA

B

+1.05VS_VGA

+5VALW

ALC109

Tuesday, September 24, 2013
1

Sheet

3

of

59

A

SIGNAL

STATE

1

B

*1

SLP_S3# SLP_S4# SLP_S5#

+VALW

C

+1.5V +0.75VS

+RTCVCC

S0(Full ON)

HIGH

HIGH

HIGH

ON

ON

ON

ON

ON

S1(Power On Suspend)

HIGH

HIGH

HIGH

ON

ON

ON

ON

ON

S3(Suspend to RAM)

LOW

HIGH

HIGH

ON

OFF

ON

OFF

ON

S4(Suspend to Disk)

LOW

LOW

HIGH

ON

OFF

OFF

OFF

ON

LOW

S5(Soft OFF)

LOW

LOW

ON

USB Port Table

*2

+VS

OFF

OFF

OFF

D

BOM Structure Table

USB 2.0 USB 1.1 Port

EHCI1
RMH1

ON

UHCI2

Note:

UHCI3

*1:+VALW power reail include +3VALW,+5VALW,B+,+VSB,+3VALW_PCH
*2:+VS power reail include +3VS,+5VS,+12VS,+1.05VS_VPCH,+1.5VS_VGA,+VGA_CORE,+CPU_CORE

UHCI4
UHCI5

RMH2

Device

0
1
2
3
4
5
6
7
8
9
10
11
12
13

UHCI0

UHCI6

Co-lay w/USB30 PORT0
Co-lay w/USB30 PORT1(Debug)
Rear IO USB20 Conn
Rear IO USB20 Conn
WLAN
Touch
Disabled on H81
Disabled on H81
Rear IO USB20 Conn
Rear IO USB20 Conn(Debug)
TV
Camera
Disabled on H81
Disabled on H81

SATA Port Table
Port
2

6G

3G

PCIE Port Table

Device
0
1
2
3
4
5

Port Device
1
2
3
4
5
6
7
8

HDD
m-SATA
Disabled on H81
Disabled on H81
ODD
NC

BOARD ID Table
PCH SM Bus Address

3

HEX

EC SM Bus1 Address

Power

Device

+3VS

DDR(JDDRL2)

Address
1010 000X b

+3VS

DDR(JDDRH1)

1010 010X b

Power

Device

HEX

Address

ALC106

48H

0100_100xb

Device

HEX

SKU ID(Project) Table

Address

VGA Ext. thermal sensor
VGA Int. thermal sensor
(default)

LAN
Card Reader
WLAN
TV
NC
NC
Disabled on H81
Disabled on H81

BTO Item
BOM Structure
CONN@
ME components
UMA Only
UMA@
DISCRETE Only
DIS@
EMI Pop components
EMI@
ESD Pop components
ESD@
EMI Unpop components @EMI@
ESD Unpop components @ESD@
HDMI OUT
HDMIO@
TV
TV@
SSD
SSD@
CRT
CRT@(EVTonly)
Unpop
@
VRAM select
X76@
EVT@
EVT for Reserve
components
PCB
PCB@
GPIO68_H@
GPIO68_L@
GPIO69_H@
SKU IO Select
GPIO69_L@
GPIO70_H@
GPIO70_L@
Touch
TOUCH@
Non Charger
NCHG@
Charger
CHG@

0

0

0

0

0

1

0

1

0

0

1

1

0

1

0x9b

1

2

PCB
Revision
0.1
0.2
0.3

Board
ID
0
3
4
5

Project Project Project
_ID2
_ID1
_ID0
(GPIO68) (GPIO69) (GPIO70)

PCH SML1 Bus Address
Power

E

0

1

0

1

1

1

0

1

1

1

3

SKU
UMA
4519QH38L04
UMA_W/HDMI
4519QH38L05
DIS-MIC1G
4519QH38L06

TV@
DIS@

DIS-SAM1G_W/HDMI

DIS@
TV@
DIS@

4519QH38L07
DIS-MIC2G_W/HDMI

4519QH38L08
DIS-MIC2G_W/HDMI

4519QH38L09

DIS@
TV@

EMI@ ESD@ GPIO68_L@ GPIO69_L@
NLDO@ 8111G@
CHG@
HDMIO@ EMI@ ESD@ GPIO68_L@ GPIO69_L@
NLDO@ 8111G@
NCHG@ TOUCH@
EMI@ ESD@ GPIO68_L@ GPIO69_H@
NLDO@ 8111G@ TOUCH@
HDMIO@ EMI@ ESD@ GPIO68_L@ GPIO69_H@
NLDO@ 8111G@
NCHG@
EMI@ ESD@ GPIO68_H@ GPIO69_L@
NLDO@ 8111G@
TOUCH@
NCHG@
HDMIO@ EMI@ ESD@ GPIO68_H@ GPIO69_L@
NLDO@ 8111G@
TOUCH@
NCHG@

GPIO70_L@ PCB@
GPIO70_H@ PCB@
GPIO70_L@ PCB@
GPIO70_H@ PCB@
GPIO70_L@ PCB@
GPIO70_L@ PCB@

4

4

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Notes List
Rev
0.3

ZEA00 LA-A061P M/B

Date:

A

B

C

D

Tuesday, September 24, 2013

Sheet
E

4

of

59

5

1

4

1
@ESD@ C2112
1
@ESD@ C2
1
@ESD@ C3
1
@ESD@ C4

PAD

PAD

H_PROCHOT#
H_THERMTRIP#

R11 follow CDB R42PR add
0ohm serial resistor

10K_0402_5%
0.1U_0402_16V4Z

1

2 R16
1

2

[17]

H_PW RGOOD

T2

H_PECI
1
1
@ R11
@ R12

H_PM_SYNC
1
H_PW RGOOD
@ R14

[14] H_PM_SYNC
[17] H_PW RGOOD

R12 follow CDB R34PR add
0ohm serial resistor

2
0_0402_5%

CPU_PLTRST#

100 MHz

[13]
[13]
[13]
[13]
[13]
[13]

TP_SKTOCC#

T1

D38

SKTOCC#

MISC
DDR3

R9
51_0402_5%
1
2
[17,43]

[43]
[17]

R1
P1
R2

R4
R3
R6
SM_RCOMP01
SM_RCOMP11
SM_RCOMP21

AK22

SM_DRAMRST#_R 1

JCPU1B

+1.05VS_VCCIO

PECI 10mil spacing and
Max Length < 15"

H_CATERR#
H_PECI
2 H_PROCHOT#_R
2 H_THERMTRIP#_R
0_0402_5%
0_0402_5%

P36
AB35
H_PW RGOOD_R
PM_DRAM_PW RGD_R AK21
M39
CPU_PLTRST#

CLK_DPNS_DN
CLK_DPNS_DP
CLK_DP_DN
CLK_DP_DP
CLK_CPU_DMI#
CLK_CPU_DMI

CLK_DPNS_DN
CLK_DPNS_DP
CLK_DP_DN
CLK_DP_DP
CLK_CPU_DMI#
CLK_CPU_DMI

M36
N37
K38
F37

W6
W5
U5
U6
V4
V5

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST#

CATERR#
THERMAL
PECI
PROCHOT#
THERMTRIP#

PM_SYNC
PWRGOOD
SM_DRAMPWROK
RESET#

R8

0_0402_5%

v1.0 update

PWR
JTAG

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

CLK
DPLL_REF_CLKN
DPLL_REF_CLKP
SSC_DPLL_REF_CLKN
SSC_DPLL_REF_CLKP
BCLKN
BCLKP

L39
L37
D39
E39
E37
F38
F39
G40

XDP_PRDY#
XDP_PREQ#
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
XDP_DBRESET#_R

G39
J39
G38
H37
H38
J38
K39
K37

XDP_OBS0
XDP_OBS1
BPM2#
BPM3#
BPM4#
BPM5#
BPM6#
BPM7#

1
@ R18

HDMI OUT
(To Conn.)

2 H_THERMTRIP#
1K_0402_1%

For BDW new CPU
1

2
0.1U_0402_16V4Z

@ESD@ C44

@ESD@ C2143
1

2

F17
E17
G18
F18
H19
G19
G20
F20

PCH_HDMIOUT_TX2PCH_HDMIOUT_TX2+
PCH_HDMIOUT_TX1PCH_HDMIOUT_TX1+
PCH_HDMIOUT_TX0PCH_HDMIOUT_TX0+
PCH_HDMIOUT_CLKPCH_HDMIOUT_CLK+

T13
T14
T15
T16
T17
T19
T21
T23

0.1U_0402_16V4Z
H_PW RGOOD_R

v0.2 update

PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD

E19
D19
D20
C20
E21
D21
D22
C22

+1.05VS_VCCIO

T9

SM_DRAMRST#
1

DDIC_TXCN0
DDIC_TXCP0
DDIC_TXCN1
DDIC_TXCP1
DDIC_TXCN2
DDIC_TXCP2
DDIC_TXCN3
DDIC_TXCP3

DP_RCOMP

eDP

FDI0_TX0N0
FDI0_TX0P0
FDI0_TX0N1
FDI0_TX0P1
EDP_DISP_UTIL

DDID_TXDN0
DDID_TXDP0
DDID_TXDN1
DDID_TXDP1
DDID_TXDN2
DDID_TXDP2
DDID_TXDN3
DDID_TXDP3

DDI

[10,11]

2

8
7
6
5

D

@ C5 0.1U_0402_16V4Z

PAD

51_8P4R_5%

T159 PAD
T10
T11
T3
T4
T5
T6
T7
T8

PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD

R17

DDIB_TXBN0
DDIB_TXBP0
DDIB_TXBN1
DDIB_TXBP1
DDIB_TXBN2
DDIB_TXBP2
DDIB_TXBN3
DDIB_TXBP3

1
2
3
4

XDP_TDO
XDP_TCK
XDP_TRST#

1

XDP_DBRESET#_R
@ESD@ C2142

2

0.1U_0402_16V4Z

ESD request Close to JCPU1 G40

+VCCIOA

JCPU1I
[30]
[30]
[30]
[30]
[30]
[30]
[30]
[30]

T156 PAD
T157 PAD
T158 PAD

RP19
@

PRDY#
PREQ#
TCK
TMS
TRST#
TDI
TDO
DBR#

XDP_TMS
XDP_TDI
XDP_PREQ#

2

FOX_3H993827-4M41-01H_HASW ELL

+1.05VS_VPCH

v0.2 update
ESD request Close to JCPU1

100_0402_1%
75_0402_1%
100_0402_1%
2
2
2

C6

Place C6 close to CPU pin J40 as
close as possible. No stub

C

1

Trace width=12mil, spacing 20mil, max L=500mil

ESD request Close to CPU as possible
D

2

PU/PD for JTAG signals

2
CPU_PLTRST#
0.1U_0402_16V4Z
2
XDP_DBRESET#_R
0.1U_0402_16V4Z
2
H_PECI
5P_0402_50V
2
H_PROCHOT#_R
0.1U_0402_16V4Z
2
H_PM_SYNC
0.1U_0402_16V4Z

@ESD@ C124

3

R4

24.9_0402_1%
1
DP_RCOMP 2

B14
A14
C13
B13

FDI_CTX_PRX_N0
FDI_CTX_PRX_P0
FDI_CTX_PRX_N1
FDI_CTX_PRX_P1

FDI_CTX_PRX_N0
FDI_CTX_PRX_P0
FDI_CTX_PRX_N1
FDI_CTX_PRX_P1

E16 EDP_DISP_UTIL

C15
B15
B16
A16
C17
B17
B18
A18

DP_RCOMP trace width=20mil
spacing 25mil length<200mil

EDP_DISP_UTIL

CPU_EDP_TXN0
CPU_EDP_TXP0
CPU_EDP_TXN1
CPU_EDP_TXP1
CPU_EDP_TXN2
CPU_EDP_TXP2
CPU_EDP_TXN3
CPU_EDP_TXP3

C7
C8
C9
C10

1
1
1
1
T18
T20
T22
T24

2
2
2
2

[14]
[14]
[14]
[14]
[29]

FDI For VGA

C

eDP brightness

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

CPU_EDP_TXN0_C
CPU_EDP_TXP0_C
CPU_EDP_TXN1_C
CPU_EDP_TXP1_C

PAD
PAD
PAD
PAD

[29]
[29]
[29]
[29]

eDP
(To LVDS Converter)

FOX_3H993827-4M41-01H_HASW ELL

B

B

1

+1.5V

v0.2 update

2

R19
1.8K_0402_5%
A

1

DRAMPW ROK
1

A

2PM_DRAM_PW RGD_R
@ R20
0_0402_5%

R21
3.3K_0402_5%
2

[14]

1

2

C11
1000P_0402_50V7K
@

PDG P132
HSW A0+LPT A0 change R21 to 4.7K, R19 to 3.3K

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2014/04/01

Title

Haswell_JTAG/XDP/DDI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

Rev
0.3

ZEA00 LA-A061P M/B

3

2

Tuesday, September 24, 2013

Sheet
1

5

of

59

5

4

3

2

1

PCIE_GTX_C_CRX_N[0..15]
PCIE_GTX_C_CRX_P[0..15]
PCIE_CTX_C_GRX_N[0..15]
PCIE_CTX_C_GRX_P[0..15]
+VCCIOA

D

PCIE_GTX_C_CRX_P[0..15]

[21]
[21]

PCIE_CTX_C_GRX_N[0..15]

[21]

PCIE_CTX_C_GRX_P[0..15]

[21]
D

1

PEG_RCOMP trace width=12mil
spacing 15mil length<400mil

PCIE_GTX_C_CRX_N[0..15]

R22
24.9_0402_1%

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

[14]
[14]
[14]
[14]

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

[14]
[14]
[14]
[14]

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

[14]
[14]

FDI_CSYNC
FDI_INT

B

T3
V1
V2
W3

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

U3
U1
W2
Y3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

AA5
AB4
AC4
AC2

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

AA4
AB3
AC5
AC1

FDI_CSYNC
FDI_INT

D16
D18

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

FDI_CSYNC
DISP_INT

PEG

[14]
[14]
[14]
[14]

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

FDI

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

DMI

C

[14]
[14]
[14]
[14]

PEG_RCOMP
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

P3
F15
E14
F13
E12
F11
G10
F9
G8
D4
E5
F6
G5
H6
J5
K6
L5
E15
D14
E13
D12
E11
F10
E9
F8
D3
E4
F5
G4
H5
J4
K5
L4
B12
C11
D10
C9
D8
C7
B6
C5
E2
F3
G2
H3
J2
K3
M3
L2
A12
B11
C10
B9
C8
B7
A6
B5
E1
F2
G1
H2
J1
K2
M2
L1

PEG_RCOMP
PCIE_GTX_C_CRX_N15
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_N7
PCIE_GTX_C_CRX_N6
PCIE_GTX_C_CRX_N5
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_N3
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_P15
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_P0
PCIE_CTX_GRX_N15
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P0

2

JCPU1A

Reserve for x16 GPU

Reserve for x16 GPU
C

C2080 1
C2081 1
C2082 1
C2083 1
C2084 1
C2085 1
C2086 1
C2087 1
C12 1
C13 1
C14 1
C15 1
C16 1
C17 1
C18 1
C19 1
C2088 1
C2089 1
C2090 1
C2091 1
C2092 1
C2093 1
C2094 1
C2095 1
C20 1
C21 1
C22 1
C23 1
C24 1
C25 1
C26 1
C27 1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

@
@
@
@
@
@
@
@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
@
@
@
@
@
@
@
@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K

PCIE_CTX_C_GRX_N15
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P0

Reserve for x16 GPU

Reserve for x16 GPU
B

FOX_3H993827-4M41-01H_HASWELL

Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/01

Deciphered Date

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Haswell_DMI/PEG/FDI
Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Sheet

Tuesday, September 24, 2013
1

6

of

59

5

4

3

[11]

1

DDR_B_D[0..63]

DDR_A_D[0..63]
JCPU1C

AW33
AV33
AU31
AV31
AT33
AU33
AT31
AW31

B

SA_ECC_CB0
SA_ECC_CB1
SA_ECC_CB2
SA_ECC_CB3
SA_ECC_CB4
SA_ECC_CB5
SA_ECC_CB6
SA_ECC_CB7

SA_CK0
SA_CKN0
SA_CK1
SA_CKN1
SA_CK2
SA_CKN2
SA_CK3
SA_CKN3
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS0#
SA_CS1#
SA_CS2#
SA_CS3#
SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3
SA_BS0
SA_BS1
SA_BS2
SA_RAS#
SA_WE#
SA_CAS#
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSN8
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SA_DQSP8
SM_VREF
SA_DIMM_VREFDQ

JCPU1D
AY15
AY16
AW15
AV15
AV14
AW14
AW13
AY13

DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#

AV22
AT23
AU22
AU23

DDRA_CKE0
DDRA_CKE1

AU14
AV9
AU10
AW8
AW10
AY8
AW9
AU8
AV12
AY11
AT21

DDRA_SCS0#
DDRA_SCS1#

AU12
AU11
AU9
AU13
AV16
AU16
AW17
AU17
AW18
AV17
AT18
AU18
AT19
AW11
AV19
AU19
AY10
AT20
AU21

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDRA_CLK0 [10]
DDRA_CLK0# [10]
DDRA_CLK1 [10]
DDRA_CLK1# [10]

DDRA_CKE0
DDRA_CKE1

[10]
[10]

DDRA_SCS0#
DDRA_SCS1#

DDRA_ODT0
DDRA_ODT1

[10]
[10]

DDRA_ODT0
DDRA_ODT1

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_RAS#
DDR_A_W E#
DDR_A_CAS#

[10]
[10]
[10]
[10]
[10]

DDR_A_RAS# [10]
DDR_A_W E# [10]
DDR_A_CAS# [10]
DDR_A_MA[0..15]
[10]

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

AE38 DDR_A_DQS#0
AJ38 DDR_A_DQS#1
AN38 DDR_A_DQS#2
AU36 DDR_A_DQS#3
AW5 DDR_A_DQS#4
AP2 DDR_A_DQS#5
AK2 DDR_A_DQS#6
AF2 DDR_A_DQS#7
AU32

DDR_A_DQS#[0..7]

AE39
AJ39
AN39
AV36
AV5
AP3
AK3
AF3
AV32

DDR_A_DQS[0..7]

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

[10]

[10]

+VREF_CAA

+V_SM_VREF should
have 20 mil trace width

AB38

+V_SM_VREF

AB39 +VREF_DQA_R 1

1

2
2

R23

2_0402_1%

C30

SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS0#
SB_CS1#
SB_CS2#
SB_CS3#
SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3
SB_BS0
SB_BS1
SB_BS2

SB_RAS#
SB_WE#
SB_CAS#
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSN8

SB_ECC_CB0
SB_ECC_CB1
SB_ECC_CB2
SB_ECC_CB3
SB_ECC_CB4
SB_ECC_CB5
SB_ECC_CB6
SB_ECC_CB7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS8
SB_DIMM_VREFDQ

AM20
AM21
AP22
AP21
AN20
AN21
AP19
AP20

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

AW29
AY29
AU28
AU29

DDRB_CKE0
DDRB_CKE1

AP17
AN15
AN17
AL15
AM17
AL16
AM16
AK15
AK17
AL18
AW28

DDRB_SCS0#
DDRB_SCS1#

AM18
AK16
AP16

DDR_B_RAS#
DDR_B_W E#
DDR_B_CAS#

AL19
AK23
AM22
AM23
AP23
AL23
AY24
AV25
AU26
AW25
AP18
AY25
AV26
AR15
AV27
AY28

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

[11]
[11]

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

[11]
[11]
[11]

DDR_B_RAS#
DDR_B_W E#
DDR_B_CAS#

[11]
[11]
[11]

DDR_B_MA[0..15]

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

[11]

C

AF35
AL33
AP33
AN28
AN12
AP8
AL8
AG7
AN25

DDR_B_DQS[0..7]

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

[11]

[11]

B

AB40 +VREF_DQB_R 1

1
1
2

2_0402_1%

DDRB_ODT0
DDRB_ODT1

[11]
[11]

DDR_B_DQS#[0..7]

@

R28

[11]
[11]

DDRB_SCS0#
DDRB_SCS1#

DDRB_ODT0
DDRB_ODT1

+VREF_CAB

2

R26

D

DDRB_CKE0
DDRB_CKE1

AF34 DDR_B_DQS#0
AK33 DDR_B_DQS#1
AN33 DDR_B_DQS#2
AN29 DDR_B_DQS#3
AN13 DDR_B_DQS#4
AR8 DDR_B_DQS#5
AM8 DDR_B_DQS#6
AG6 DDR_B_DQS#7
AN26

FOX_3H993827-4M41-01H_HASW ELL
1

DDRB_CLK0 [11]
DDRB_CLK0# [11]
DDRB_CLK1 [11]
DDRB_CLK1# [11]

2

R25

2

+VREF_DQB

2_0402_1%

C32
0.022U_0402_25V7K
24.9_0402_1%

2

1

SB_CK0
SB_CKN0
SB_CK1
SB_CKN1
SB_CK2
SB_CKN2
SB_CK3
SB_CKN3

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R27

1

2

AM26
AM25
AP25
AP26
AL26
AL25
AR26
AR25

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

C33

2
2

0.022U_0402_25V7K
24.9_0402_1%

@

2_0402_1%

@
C28

0.022U_0402_25V7K
24.9_0402_1%

1 R24
C29

+VREF_DQA
0.1U_0402_16V4Z

1

C31

FOX_3H993827-4M41-01H_HASW ELL

2

1

AE34
AE35
AG35
AH35
AD34
AD35
AG34
AH34
AL34
AL35
AK31
AL31
AK34
AK35
AK32
AL32
AN34
AP34
AN31
AP31
AN35
AP35
AN32
AP32
AM29
AM28
AR29
AR28
AL29
AL28
AP29
AP28
AR12
AP12
AL13
AL12
AR13
AP13
AM13
AM12
AR9
AP9
AR6
AP6
AR10
AP10
AR7
AP7
AM9
AL9
AL6
AL7
AM10
AL10
AM6
AM7
AH6
AH7
AE6
AE7
AJ6
AJ7
AF6
AF7

1

C

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

1

D

AD38
AD39
AF38
AF39
AD37
AD40
AF37
AF40
AH40
AH39
AK38
AK39
AH37
AH38
AK37
AK40
AM40
AM39
AP38
AP39
AM37
AM38
AP37
AP40
AV37
AW37
AU35
AV35
AT37
AU37
AT35
AW35
AY6
AU6
AV4
AU4
AW6
AV6
AW4
AY4
AR1
AR4
AN3
AN4
AR2
AR3
AN2
AN1
AL1
AL4
AJ3
AJ4
AL2
AL3
AJ2
AJ1
AG1
AG4
AE3
AE4
AG2
AG3
AE2
AE1

2

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

R29
2

[10]

2

A

A

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Haswell_DDR3
Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

7

of

59

5

4

3

2

1

+CPU_CORE

+1.5V Decoupling:
1X 390U , 9X 22U,5*10U

JCPU1E

B

+1.5V

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1
1

C34

C35

2

1

1

C36

2

22U_0805_6.3V6M

C37

2

1

1

C38

2

22U_0805_6.3V6M

1

C39

2

C40

2

22U_0805_6.3V6M

1

C41

2

1

1

C42

2

22U_0805_6.3V6M

1

+ C45
390U 2.5V M ESR10

2

2

2

v0.2 update

22U_0805_6.3V6M

C2071

1

2

10U_0603_6.3V6M

C2072

1

C2073

2

1

C2074

2

10U_0603_6.3V6M

1

C2075

D

2
10U_0603_6.3V6M

Pull high resistor close to CPU
SVID signal 50 ohm impedance
spacing >12mil length 3-6"
+1.05VS_VCCIO
+VCCIO_OUT

+1.05VS_VCCIO

+VCCIO_OUT

1

1

1
R32
110_0402_5%

R33
75_0402_5%

@

2

+1.05VS_VPCH

1

R30
0_0603_5%

2

@ R31
0_0603_5%

+VCCIOA
VCCIO_OUT
VCOMP_OUT

L40
P4

+1.05VS_VCCIOA(PEG,FDI RCOMP pull high PWR)
+1.05VS_VPCH

@ R34
1
VR_SVID_CLK_R
1
VR_SVID_DAT_R
H_CPU_SVIDALRT# 1
@ R35
R36

0_0402_5%
2
2
2
0_0402_5%
43_0402_1%

F40
E40

VR_SVID_CLK [50]
VR_SVID_DAT [50]
VR_SVID_ALRT# [50]
2
100_0402_1%

1
R37

VSS_SENSE
VCC_SENSE

R38
150_0402_1%

[50]
[50]

C

2

VSS_SENSE
VCC_SENSE

C38
C37
B37

1

VIDSCLK
VIDSOUT
VIDALERT#

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

N40 CPU_PW RDB

2

T135 PAD
+CPU_CORE

A24
A25
A26
A27
A28
A29
A30
B25
B27
B29
B31
B33
B35
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
D25
P8
M8
M33
M29
M27
M25
M23
M21
M19
M17
M15
M13
L34
L33

1
R39
100_0402_1%

CPU_PW RDB

+CPU_CORE

1

PWR_DEBUG

R37,R39 close to CPU

@
R40
10K_0402_5%

2

C

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

2

D

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

AJ12
AJ13
AJ15
AJ17
AJ20
AJ21
AJ24
AJ25
AJ28
AJ29
AJ9
AT17
AT22
AU15
AU20
AU24
AV10
AV11
AV13
AV18
AV23
AV8
AW16
AY12
AY14
AY9

2

D27
D29
D31
D33
D35
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
F23
F25
F27
F29
F31
F33
F35
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
H23
H25
H27
H29
H31
H33
H35
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
K19
K21
K23
K25
K27
K29
K31
K33
K35
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
L31
L32

B

FOX_3H993827-4M41-01H_HASW ELL

A

A

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Haswell_POWER
Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

8

of

59

4

FOX_3H993827-4M41-01H_HASW ELL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CFG Straps for Processor

JCPU1H
AR18
AR19
AR20
AR21
AR22
AR23
AR24
AR27
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR39
AR40
AR5
AT1
AT10
AT11
AT12
AT13
AT14
AT15
AT16
AT2
AT24
AT25
AT26
AT27
AT28
AT29
AT3
AT30
AT32
AT34
AT36
AT38
AT39
AT4
AT5
AT6
AT7
AT8
AT9
AU2
AU25
AU3
AU30
AU34
AU38
AU5
AU7
AV21
AV28
AV3
AV30
AV34
AV38
AV7
AW26
AW3
AW30
AW32
AW34
AW36
AW7
AY17
AY23
AY26
AY27
AY30
AY5
AY7
B10
B23
B24
B26

FOX_3H993827-4M41-01H_HASW ELL

N34
N39
N4
N6
N7
N8
P2
P34
P35
P38
P39
P40
P5
P7
R3
R35
R37
R38
R39
R40
R5
R6
R7
R8
T1
T2
T33
T36
T37
T38
T39
T4
T5
T6
T7
U2
U33
U34
U35
U36
U37
U4
U7
V3
V33
V34
V40
V6
V7
V8
W1
W33
W35
W37
W4
W7
Y33
Y4
Y5
Y6
A15
A17
A23
A5
A7
AA3
AA33
AA35
AA38
AA6
AA7
AA8
AB34

AU40
AV39
AW38
AY3
B38
B39
C40
D40

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A11
A13
H17
H18
H20
H21
H22
H24
H26
H28
H30
H32
H34
H36
H39
H4
H7
H8
H9
J11
J14
J18
J19
J20
J3
J36
J37
J6
J7
K1
K10
K14
K15
K16
K17
K18
K20
K22
K24
K26
K28
K30
K32
K34
K36
K4
K40
K7
L11
L13
L14
L3
L35
L36
L38
L6
L7
L8
L9
M1
M12
M14
M16
M18
M20
M22
M24
M26
M28
M30
M32
M34
M35
M37
M4
M40
M5
M6
M7
M9
N1
N2
N3
N33

(CFG[19:0] internal pull high to VCCIO)

JCPU1J
T25
T26
T27
T28
T29
T30
T32
T33
T34
T35
T36
T37
T38
T39
T40
T41
T42
T43
T44
T45
T46

PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD

CPU_A4
CPU_AV1
CPU_AW 2
CPU_B3

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG_RCOMP

T136PAD
T137PAD
T138PAD
T140PAD
T139PAD
T141PAD
T142PAD
T143PAD
T144PAD
T145PAD
T146PAD
T147PAD
T148PAD
T149PAD
T150PAD
T151PAD
T152PAD
T153PAD
T154PAD
T155PAD

R36
P37
N38
N36
K8
K13
K12
K11
J8
J16
J13
J12
J10
H16
D1
C39
C2
A4
AV1
AW2
B3

AA37
Y38
AA36
W38
V39
U39
U40
V38
T40
Y35
AA34
V37
Y34
U38
W34
V35
Y37
Y36
W36
V36
H40

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG_RCOMP

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
FC_AB8
FC_K9
FC_Y7
TESTLO_N5
TESTLO_P6

AB33
AB36
Y8
W8
U8
T8
T35
T34
R34
R33
P33
N35
M38
M11
M10
L12
L10
J9
J40
J17
J15
H15
H14
H12
AY18
AW27
AW24
AW23
AC8
AK20
AL20
AT40
AU1
AU27
AU39
AV2
AV20
AV24
AV29
AW12

CFG2
CFG3
CFG5
CFG6

2
2
2
2

1K_0402_1%
1K_0402_1%
1K_0402_1%
1K_0402_1%

CPU_T8
PAD T31
+1.05VS_VPCH

1
@

CPU_N35

R45 0_0603_5%

@
1

2

+VCCST
+PCH_VPROC
@ R46
0_0603_5%
1
2

C47
4.7U_0603_10V6K

0828

1

1

2

2

+VCCST
C

2 0_0402_5%
1

TESTLO_N5
TESTLO_P6

FOX_3H993827-4M41-01H_HASW ELL

D

2

@ R47
AB8 +VCCIO2PCH
1
K9
+VCCST
Y7
VCCST_PW RGD
N5
P6

1
1
1
1

R41
@ R42
R43
@ R44

2

PM_PW ROK

[14,43]

1

B28
B30
B32
B34
B36
B4
B8
C12
C14
C16
C18
C19
C21
C23
C3
C36
C4
C6
D11
D13
D15
D17
D2
D23
D24
D26
D28
D30
D32
D34
D36
D37
D5
D6
D7
D9
E10
E18
E20
E22
E23
E3
E36
E38
E6
E7
E8
F1
F12
F14
F16
F19
F21
F22
F24
F26
F28
F30
F32
F34
F36
F4
F7
G11
G12
G13
G14
G15
G16
G17
G21
G3
G36
G37
G6
G7
G9
H1
H10
H11
H13

C48
0.1U_0402_16V4Z

B

JCPU1G
AB37
AB5
AB6
AB7
AC3
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AC40
AC6
AC7
AD1
AD2
AD3
AD33
AD36
AD4
AD5
AD6
AD7
AD8
AE33
AE36
AE37
AE40
AE5
AE8
AF1
AF33
AF36
AF4
AF5
AF8
AG33
AG36
AG37
AG38
AG39
AG40
AG5
AG8
AH1
AH2
AH3
AH33
AH36
AH4
AH5
AH8
AJ11
AJ14
AJ16
AJ18
AJ19
AJ22
AJ23
AJ26
AJ27
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AJ37
AJ40
AJ5
AJ8
AK1
AK10
AK11
AK12
AK13
AK14
AK18

C46
0.1U_0402_16V4Z

C

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

1

R49
R48
2.67K_0402_1%

6.04K_0402_1%

2

D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2

R50
49.9_0402_1%
2
1
R51
49.9_0402_1%
2
1

JCPU1F
AK19
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK36
AK4
AK5
AK6
AK7
AK8
AK9
AL11
AL14
AL17
AL21
AL22
AL24
AL27
AL30
AL36
AL37
AL38
AL39
AL40
AL5
AM1
AM11
AM14
AM15
AM19
AM2
AM24
AM27
AM3
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AM4
AM5
AN10
AN11
AN14
AN16
AN18
AN19
AN22
AN23
AN24
AN27
AN30
AN36
AN37
AN40
AN5
AN6
AN7
AN8
AN9
AP1
AP11
AP14
AP15
AP24
AP27
AP30
AP36
AP4
AP5
AR11
AR14
AR16
AR17

3

R52
49.9_0402_1%
2
1

5

0828

B

FOX_3H993827-4M41-01H_HASW ELL

A

A

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2014/04/01

Title

Haswell_GND/CFG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

9

of

59

5

[7]

2

1

DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
DDR_A_D[0..63]

CHA SO-DIMM 0(A0)

DDR_A_MA[0..15]
+VREF_DQA

R626
1K_0402_1%
1
2

+1.5V

+1.5V
JDIMM1

2

DDR_A_D0
DDR_A_D1

1

2

DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9

Close to JDIMM1

DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

[7]
[7]

C

DDRA_CKE0

DDRA_CKE0

DDR_A_BS2

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDRA_CLK0
DDRA_CLK0#

[7] DDRA_CLK0
[7] DDRA_CLK0#
DDR_A_BS0

DDR_A_MA10
DDR_A_BS0

[7] DDR_A_WE#
[7] DDR_A_CAS#

DDR_A_WE#
DDR_A_CAS#

[7]

[7]

DDR_A_MA13
DDRA_SCS1#

DDRA_SCS1#

DDR_A_D32
DDR_A_D33

DDR_A_D40
DDR_A_D41

B

DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57

+0.75VS

1

1

R630
@

2

0_0402_5%
2

2

C2049
0.1U_0402_16V4Z

@

C2048
2.2U_0603_6.3V6K

SPD setting (SA0, SA1)
PU/PD by Channel A/B
->Channel A 00
->Channel B 01

1

205

G1

G2

DDR_A_DQS#0
DDR_A_DQS0

D

DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
SM_DRAMRST#

SM_DRAMRST#

[11,5]

DDR_A_D14
DDR_A_D15

Layout Note:
Place near JDIMM1

DDR_A_D20
DDR_A_D21

+1.5V
DDR_A_D22
DDR_A_D23

C2032 1

DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3

DDRA_CKE1

2 10U_0805_6.3V6M

C2034 1

2 10U_0805_6.3V6M

C2035 1

2 10U_0805_6.3V6M

C2036 1

2 0.1U_0402_16V4Z

C2037 1

2 0.1U_0402_16V4Z

C2038 1

2 0.1U_0402_16V4Z

C2039 1

2 0.1U_0402_16V4Z

C2040 1

2 0.1U_0402_16V4Z

C2041 1

2 0.1U_0402_16V4Z

C2042 1

2 0.1U_0402_16V4Z

C2043 1

2 0.1U_0402_16V4Z

+1.5V

DDR_A_D30
DDR_A_D31

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

2 390U 2.5V M ESR10

C2033 1

DDRA_CKE1

[7]

DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4

C

DDR_A_MA2
DDR_A_MA0
DDRA_CLK1
DDRA_CLK1#
DDR_A_BS1
DDR_A_RAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1

DDRA_CLK1
DDRA_CLK1#

Layout Note: Place these Caps near
+1.5V of JDIMM1

[7]
[7]
+1.5V

DDR_A_BS1
[7]
DDR_A_RAS#
[7]
DDRA_SCS0#
DDRA_ODT0

[7]
[7]

DDRA_ODT1

[7]

R628
1K_0402_1%
+VREF_CAA

+VREF_CAA
DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45

1

2

R629
1K_0402_1%
1

2

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47

B

close to JDIMM1.126

DDR_A_D52
DDR_A_D53

+0.75VS

DDR_A_D54
DDR_A_D55

Layout Note:
Place near JDIMM1 Pin203 and 204

DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7

PM_SMBDATA
PM_SMBCLK

1

1

2

2

C2046

DDR_A_D62
DDR_A_D63

PM_SMBDATA [11,13,40,5]
PM_SMBCLK [11,13,40,5]

C2047
0.1U_0402_16V4Z

+3VS

DDR_A_D4
DDR_A_D5

4.7U_0603_6.3V6K

DDR_A_D58
DDR_A_D59

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

C2045
0.1U_0402_16V4Z

DDR_A_D34
DDR_A_D35

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

C2044
2.2U_0603_6.3V6K

DDR_A_DQS#4
DDR_A_DQS4

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

+

2

D

1

C2031
2.2U_0603_6.3V6K

C2030
0.1U_0402_16V4Z

R627
1K_0402_1%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

1

1

+VREF_DQA

2

[7]

1

[7]

+1.5V

3

2

[7]

4

+0.75VS

206

FOX_AS0A626-U2SN-7F
CONN@

Standard H:5.2mm
A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/01

Deciphered Date

2014/04/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

DDRIII-SODIMMA
Size
C
Date:

5

4

3

2

Document Number

Rev
0.3

ZEA00 LA-A061P M/B
Tuesday, September 24, 2013
1

Sheet

10

of

59

A

B

DDR_B_D[0..63]

+VREF_DQB

R631
1K_0402_1%
2

+1.5V

CHB SO-DIMM
+1.5V

1

JDIMM2
DDR_B_D0
DDR_B_D1

2

2

C2051
0.1U_0402_16V4Z

C2050
2.2U_0603_6.3V6K

1

1

2

DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11

Close to JDIMM2

DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

2

[7]
[7]

DDRB_CKE0

DDRB_CKE0

DDR_B_BS2

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDRB_CLK0
DDRB_CLK0#

[7] DDRB_CLK0
[7] DDRB_CLK0#
[7]

DDR_B_BS0

[7] DDR_B_WE#
[7] DDR_B_CAS#
[7]

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDRB_SCS1#

DDRB_SCS1#

DDR_B_D32
DDR_B_D33

3

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57

4

+3VS

@ C2068
2.2U_0603_6.3V6K

1

2

1
2
R635
+0.75VS
1 10K_0402_5%
C2069
0.1U_0402_16V4Z
2

205

G1

G2

1

DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
SM_DRAMRST#

SM_DRAMRST#

[10,5]

DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21

Layout Note:
Place near JDIMM2
+1.5V

DDR_B_D22
DDR_B_D23

@
C2052 1

DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31

2 390U 2.5V M ESR10

C2053 1

2 10U_0805_6.3V6M

C2054 1

2 10U_0805_6.3V6M

C2055 1

2 10U_0805_6.3V6M

C2056 1

2 0.1U_0402_16V4Z

C2057 1

2 0.1U_0402_16V4Z

C2058 1

2 0.1U_0402_16V4Z

C2059 1

2 0.1U_0402_16V4Z

C2060 1

2 0.1U_0402_16V4Z

C2061 1

2 0.1U_0402_16V4Z

C2062 1

2 0.1U_0402_16V4Z

C2063 1

2 0.1U_0402_16V4Z

+1.5V
2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDRB_CKE1

DDRB_CKE1

[7]

DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDRB_CLK1
DDRB_CLK1#
DDR_B_BS1
DDR_B_RAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1

DDRB_CLK1 [7]
DDRB_CLK1# [7]
DDR_B_BS1 [7]
DDR_B_RAS# [7]
DDRB_SCS0# [7]
DDRB_ODT0 [7]
DDRB_ODT1

+VREF_CAB

DDR_B_D44
DDR_B_D45

+VREF_CAB

R633
1K_0402_1%

[7]

DDR_B_D36
DDR_B_D37

DDR_B_D38
DDR_B_D39

Layout Note: Place these Caps near
+1.5V of JDIMM2

+1.5V

1

2

3

R634
1K_0402_1%
1

2

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47

Close to JDIMM2

DDR_B_D52
DDR_B_D53

+0.75VS

DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PM_SMBDATA
PM_SMBCLK
+0.75VS

1

1

2

2

C2066

PM_SMBDATA [10,13,40,5]
PM_SMBCLK [10,13,40,5]

C2067
0.1U_0402_16V4Z

DDR_B_D58
DDR_B_D59

DDR_B_D4
DDR_B_D5

4.7U_0603_6.3V6K

SPD setting (SA0, SA1)
PU/PD by Channel A/B
->Channel A 00
->Channel B 01

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

C2065
0.1U_0402_16V4Z

DDR_B_D34
DDR_B_D35

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

C2064
2.2U_0603_6.3V6K

DDR_B_DQS#4
DDR_B_DQS4

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

+

+1.5V

1

DDR_B_MA[0..15]

2

[7]

R632
1K_0402_1%

E

DDR_B_DQS[0..7]

[7]

1

D

1

[7]

1

C

DDR_B_DQS#[0..7]

2

[7]

Layout Note:
Place near JDIMM2 Pin203 and 204

4

206

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

SUYIN_600023HB204G208ZL
CONN@

2013/04/01

2014/04/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Standard H:9.2mm

Date:

A

DDRIII-SODIMM B
Rev
0.3

ZEA00 LA-A061P M/B

B

C

D

Tuesday, September 24, 2013

Sheet
E

11

of

59

4

3

PCH_RTCRST#

2
Y1

RC Delay 18~25mS
R70 1
20K_0402_5%

@
2PCH_SRTCRST#

JME1
1
2

C103 1
1U_0402_6.3V6K

C102
6P_0402_50V8J
2
32.768KHZ_7PF_Q13FC135000040
2

iME Setting.

D

1

2

PCH_RTCX1

AN40

PCH_RTCX2

AN39

PCH_SRTCRST#

AR39

SM_INTRUDER#

AR41

PCH_INTVRMEN

AV36

PCH_RTCRST#

AR38

AZ_BITCLK

AV23

v0.3 update

RC Delay 18~25mS
Integrated SUS 1.05V VRM Enable
High - Enable Internal VRs
PCH_INTVRMEN (must be always pulled high)

AZ_SYNC
[37]

PCH_SPKR

PCH_SPKR

+RTCVCC

AZ_RST#
1

2
390K_0402_5%

PCH_INTVRMEN

[37]

AZ_SDIN0_HD

AZ_SDIN0_HD

R32
AU24
AT26
AV22

+RTCVCC

AT22
1

R77

2
1M_0402_5%

AW23

SM_INTRUDER#

GPIO33-->GPIO only in DT(GPO)
+3VALW _PCH

GPIO13-->GPIO only in DT
1

2
10K_0402_5%

R80
C

T131PAD

AZ_SDOUT

AU22

PCH_GPIO33

AV26

PCH_GPIO13

AN22

INTRUDER#

SATA_RXN1
SATA_RXP1

INTVRMEN

SATA_TXN1
SATA_TXP1

RTCRST#
SATA_RXN2
SATA_RXP2
HDA_BCLK
SATA_TXN2
SATA_TXP2

HDA_SYNC
SPKR
HDA_RST#
HDA_SDI0
HDA_SDI1
HDA_SDI2
HDA_SDI3

SATA_RXN3
SATA_RXP3
SATA_TXN3
SATA_TXP3
SATA_RXN4/PERN1
SATA_RXP4/PERP1
SATA_TXN4/PETN1
SATA_TXP4/PETP1

HDA_SDO
SATA_RXN5/PERN2
SATA_RXP5/PERP2

DOCKEN#/GPIO33
HDA_DOCK_RST#/GPIO13

SATA_TXN5/PETN2
SATA_TXP5/PETP2
SATA_RCOMP

High = Enabled (No Reboot)
Low = Disabled (Default)

SATALED#

Has weak internal pull-down

* +3VS

Y40

PCH_JTAG_TMS

W40

2
1K_0402_5%

PCH_SPKR

PCH_JTAG_TDI

W39

PCH_JTAG_TDO

Y38

HDA_SYNC

This signal has a weak internal pull down
*H=>On Die PLL is supplied by 1.5V (mobile)
L=>On Die PLL is supplied by 1.8V (DT)
Strap: This signal has a weak internal pull-down.
Do not pull high.

T56 PAD

PCH_TP25

AM34

T58 PAD

PCH_TP22

AH24

T59 PAD

PCH_TP20

W37

JTAG_TCK

SATA0GP/GPIO21

JTAG_TMS

SATA1GP/GPIO19

JTAG_TDI
JTAG_TDO
TP25

JTAG

PCH_JTAG_TCK

@
R82

SRTCRST#

SATA_TXN0
SATA_TXP0

PCH_GPIO13

PCH_SPKR
1

RTCX2

AZALIA

R74

AV24

SATA_RXN0
SATA_RXP0

RTCX1

RTC

C101 1
1U_0402_6.3V6K

1

2

R69
10M_0402_5%
2
1

R71 1
20K_0402_5%

+RTCVCC

C104
6P_0402_50V8J
1
2

1

LPT_PCH_DT_EDS

U1A
@
JCOMS1
1
2

CMOS Setting, near DDR Door

2

SATA

5

SATA_IREF
TP9
TP8

B28
A28

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

F31
H31

SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

D30
C30

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

B34
C34

SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

[35]
[35]

SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

[35]
[35]

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

[40]
[40]

SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

[40]
[40]

HDD
D

m-SATA

A31
B31

+3VS

RP1
SATA_LED#
GPIO21
GPIO19

B35
D35

1
2
3
4

SATA Port 2~3 Is Disable For H81

B32
C32
G33
F33

8
7
6
5
10K_8P4R_5%
@

[15]

A26
B26

SATA_PRX_DTX_N4
SATA_PRX_DTX_P4

L28
K28

SATA_PTX_DRX_N4
SATA_PTX_DRX_P4

PCH_GPIO51 R75

PCH_GPIO51

SATA_PRX_DTX_N4
SATA_PRX_DTX_P4

[35]
[35]

SATA_PTX_DRX_N4
SATA_PTX_DRX_P4

[35]
[35]

1

2 10K_0402_5%

BOOT Device
Strap (SPI)

ODD

C27
B27

SATA_RCOMP 50ohm
length<600mil

G28
F28
D33

R81
7.5K_0402_1%
2
SATA_RCOMP 1

J39

SATA_LED#

M37

GPIO21

J40

GPIO19

A33

SATA_IREF

K34

PCH_TP9

PAD

K33

PCH_TP8

PAD T57

Place R81 within 500 mils of
the PCH. Avoid routing next to
clock pins.

+1.5VS
SATA_LED#

[42]

@ESD@ C2141
1
SATA_LED#

+1.5VS

C

0.1U_0402_16V4Z
2

T55

v0.2 update for ESD

TP22
TP20

DH82LPDS_FCBGA708

1

AZ_SYNC_R

2 AZ_SYNC
0_0402_5%

@

R87
2

1 R86

B

B

1M_0402_5%

HDA_SDO

ME debug mode,
this signal has a weak internal pull down
= Disable (default)
*Low
High = Enable (flash descriptor security overide)
[43]

PW RME_CTRL#

2
PW RME_CTRL# 1
AZ_SDOUT
@
R91
0_0402_5%
2
Remove R129 @ 5/5 for ME
@ 1K_0402_5% update reserve.

1
R92

RP20
1
2
3
4

[37] AZ_SDOUT_HD
[37] AZ_BITCLK_HD
[37] AZ_RST_HD#
[37] AZ_SYNC_HD

8
7
6
5

AZ_SDOUT
AZ_BITCLK
AZ_RST#
AZ_SYNC_R

33_8P4R_5%

@
1
R96

A

@ESD@

2
PCH_JTAG_TCK
51_0402_1%

1
C2113

A

2
AZ_RST#
0.1U_0402_16V4Z

@ESD@

1
C2136

2
AZ_RST_HD#
0.1U_0402_16V4Z

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

ESD request Close to PCH

Deciphered Date

2014/04/01

Title

PCH_HDA/JTAG/SATA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

v0.2 update

Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

12

of

59

5

4

3

2

1

LPT_PCH_DT_EDS

U1C

+3VALW _PCH

Close PCH
RP3

[40]
[40]

TV Card
[40]

TV_CLKREQ#

TV_CLKREQ#

P37

PCIECLKRQ2#/GPIO20/SMI#
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3

AA39

PCIECLKRQ3#/GPIO25

Y4
Y2

+3VS
CLKREQ4
R120 1
R121 1

2 10K_0402_5%
2 10K_0402_5%

CLKREQ_W LAN#
TV_CLKREQ#

R123 1

2 10K_0402_5%

CLKREQ5

AA36

PCIECLKRQ4#/GPIO26

CLKREQ6

W32

1
1
1
1

2
2
2
2

CLKREQ4
CLKREQ5
CLKREQ6
CLKREQ7

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

v0.2 update

AA40

[41,43]

1
R128 EMI@

CLK_PCI_EC

2
CLK_PCI_EC_R
22_0402_5%

CLKIN_SATA#
CLKIN_SATA
REFCLK14IN
CLKIN_33MHZLOOPBACK
XTAL25_IN
XTAL25_OUT

PCIECLKRQ7#/GPIO46

CLKOUTFLEX0/GPIO64

CLKOUT_ITPXDP#
CLKOUT_ITPXDP

CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66

CLKOUT_33MHZ0
CLKOUTFLEX3/GPIO67

AV7
22_0402_5%
2
CLK_PCILOOP_R

CLKIN_DOT96#
CLKIN_DOT96

CLKOUT_PCIE_N7
CLKOUT_PCIE_P7

AV5

R127 EMI@
1
CLK_PCILOOP

CLKIN_GND#
CLKIN_GND

PCIECLKRQ6#/GPIO45

U6
U7

C

CLKIN_DMI#
CLKIN_DMI

R2
T2

CLK_CPU_DMI#
CLK_CPU_DMI

T3
T5

CLK_DP_DN
CLK_DP_DP

W2
U2

CLK_DPNS_DN
CLK_DPNS_DP

G22
F22

PCH_CLK_DMI#
PCH_CLK_DMI

G16
F16

CLKIN_GND0#
CLKIN_GND0

AP11
AM11

CLK_DOT#
CLK_DOT

H35
H36

CLK_SATA#
CLK_SATA

CLK_CPU_DMI# [5]
CLK_CPU_DMI [5]

PCH_CLK_DMI#
PCH_CLK_DMI
CLKIN_GND0#
CLKIN_GND0

1
2
3
4

CLK_DP_DN
CLK_DP_DP

[5]
[5]

CLK_DPNS_DN
CLK_DPNS_DP

AR7

CLK_14M_PCH

AM22

CLK_PCILOOP

N7
N6

PCH_X1
PCH_X2

CLKOUT_33MHZ2

AN9

ICLK_IREF

CLKOUT_33MHZ3

AU5

TP19
TP18

CLKOUT_33MHZ4

DIFFCLK_BIASREF

CLK_SATA#
CLK_SATA

R115 1
R117 1

2 10K_0402_5%
2 10K_0402_5%

CLK_14M_PCH

R119 1

2 10K_0402_5%

For EMI
1
R122

CLK_PCILOOP

R124 2
AV9

PCH_X1

AU8

1

C106
N10

10P_0402_50V8J

+1.5VS

U11
U10

PCH_TP19
PCH_TP18

R11

XCLK_RBIAS

T66
T68
1

PAD
PAD

1
Y2

2

7.5K_0402_1%

LPT_PCH_DT_EDS

LPC_AD2

B

[41,43]

8
7
6
5

PCH_SMLDATA1
PCH_SMLCLK1
+3VS

AP26

LPC_AD2

AJ24

LPC_AD3

LPC_AD3

AN26

LPC_FRAME# AP24

LPC_FRAME#

AK22
AK26
[41,43]

SERIRQ

SERIRQ

G39

SMBus

LAD1

SMBCLK

LAD2

SMBDATA

LAD3

SML0ALERT#/GPIO60
SML0CLK

LFRAME#
SML0DATA
LDRQ0#
SML1ALERT#/PCHHOT#/GPIO74
LDRQ1#/GPIO23
SML1CLK/GPIO58
SERIRQ

PCH_GPIO11

AG36

PCH_SMBCLK

AG32

PCH_SMBDATA

AG35

PCH_GPIO60

2
6

PCH_SMBDATA

3

PCH_SMBCLK
AE32

PCH_SMLCLK0

AE35

PCH_SMLDATA0

AJ39

PCH_GPIO74

AK36

PCH_SMLCLK1

AK33

PCH_SMLDATA1

R130
R131

4.7K_0402_5%
4.7K_0402_5%

1

PM_SMBDATA

[10,11,40,5]

PM_SMBCLK

[10,11,40,5]

Q2A
2N7002KDW H_SOT363-6
4

2N7002KDW H_SOT363-6
Q2B

B

+3VS

1

PCH_SMLDATA1

6

EC_SMB_DA2

[21,43,46]

2N7002KDW H_SOT363-6
Q3A
5

SML1DATA/GPIO75

AG31

5

LPC_AD1

SMBALERT#/GPIO11
LAD0

10P_0402_50V8J

2

LPC_AD1

[41,43]

AN24

LPC

[41,43]

[41,43]

LPC_AD0

LPC_AD0

C107

RP5
1
2
3
4

2.2K_0804_8P4R_5%

[41,43]

2

+1.5VS
+3VALW _PCH

SERIRQ

C

PCH_X2

25MHZ_10PF_X3G025000DA1H-X

2

+3VS
2
R132

1 1M_0402_5%

AT9

R129

1
10K_0402_5%

@EMI@
1
2
C105
22P_0402_50V8J

2
10_0402_5%

AV8

DH82LPDS_FCBGA708

U1D

D

10K_8P4R_5%
[5]
[5]

CLKOUT_33MHZ1

AU2

10K_8P4R_5%
RP2
8
7
6
5

@EMI@

CLKOUT_PCIE_N6
CLKOUT_PCIE_P6

R6
R7
CLKREQ7

CLKOUT_DPNS#
CLKOUT_DPNS

PCIECLKRQ5#/GPIO44

AA7
AA6

@ R659
@ R660
@ R661
@ R662

mibile only

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

CLKREQ_LAN#

+3VS

mibile only

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4

W35
W7
W6

+3VALW _PCH

CLKOUT_DP#
CLKOUT_DP

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

W11
W10

CLK_TV#
CLK_TV

CLK_TV#
CLK_TV

PCIECLKRQ1#/GPIO18

AC11
AC10

VGA

1

CLKREQ_W LAN#

CLKREQ_W LAN#

P39

CLKOUT_DMI#
CLKOUT_DMI

CLK_PCIE_VGA# [21]
CLK_PCIE_VGA [21]

AE6
AE7

3

[40]

CLK_W LAN#
CLK_W LAN

CLK_W LAN#
CLK_W LAN

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLOCK SIGNAL

WLAN

AC6
AC7

CLKREQ_LAN#

CLKREQ_LAN#

[40]
[40]

CLK_LAN#
CLK_LAN

CLKOUT_PEG_B#
CLKOUT_PEG_B

CLK_PCIE_VGA#
CLK_PCIE_VGA

IN

[39]
D

CLK_LAN#
CLK_LAN

PCIECLKRQ0#/GPIO73

AA3
AA2

NC OUT

[39]
[39]

LAN

W34

CLKOUT_PEG_A#
CLKOUT_PEG_A

NC

CLKREQ_CR#

CLKREQ_CR#

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

8
7
6
5

4

[36]

AE10
AE11

CLK_CR#
CLK_CR

CLK_CR#
CLK_CR

1
2
3
4

2

[36]
[36]

Card Reader

PCH_GPIO11
PCH_GPIO74
CLK_DOT#
CLK_DOT

[43]
[43]

PCH_SPICLK
PCH_SPICS#

PCH_SPICLK

U39

PCH_SPICS#

R38

1

2

R35
R40

PCH_SPI_IO3

R134
1K_0402_5%

[43]

PCH_SPISI

[43]

PCH_SPISO

PCH_SPISI

P40

PCH_SPISO

R36

PCH_SPI_IO2

U40

PCH_SPI_IO3

U37

C-Link

SPI_CS0#

CL_DATA
CL_RST#

SPI_CS2#
SPI_MOSI
SPI_MISO

TP1
TP2

Thermal

TP4

SPI_IO2
TP3
SPI_IO3
TD_IREF

+3VALW _PCH

Reserve R658 for C38

1
2
3
4

CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)

8
7
6
5

2

C108
0.1U_0402_16V4Z

RP7
PCH_SPI_IO3_R 1
PCH_SPI_CLK_L 2
3
PCH_SPI_SI_L
4

8PCH_SPI_IO3
7PCH_SPICLK
6PCH_SPISI
5PCH_SPI_IO2

W 25Q64FVSSIQ_SO8

Socket P/N: SP07000H900
5

PCH_SPI_CLK_L

for EMI
R139
10_0402_5%
@

2

+3VALW _BIOS
U2

PAD

T70

PAD

U34

CLINK_RST#

T71

PAD

A2

PCH_TP1

T73

PAD

A3

PCH_TP2

T74

PAD

B2

PCH_TP4

T75

PAD

B1

PCH_TP3

T76

PAD

C3

2
TD_IREF 1
8.2K_0402_1%
R135

PCH_SMLCLK1

4

3

EC_SMB_CK2

[21,43,46]

2N7002KDW H_SOT363-6
Q3B

Control Link only for support Intel IAMT.
+3VALW _PCH

RP6
1
2
3
4

PCH_SMLCLK0
PCH_SMLDATA0
PCH_GPIO60

8
7
6
5

15_8P4R_5%
EMI@

1

2

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

C109
10P_0402_50V8J
@

Deciphered Date

2014/04/01

Title

PCH_CLK\LPC\SPI\SMBUS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.3

ZEA00 LA-A061P M/B

Date:

4

A

DH82LPDS_FCBGA708

1

@ R658
0_0402_5%

Now is IC Footprint
@ R137
0_0402_5%
2PCH_SPI_CS#_R
PCH_SPICS# 1
1
2 PCH_SPI_SO_L
PCH_SPISO
PCH_SPI_IO2_R
R138
15_0402_5%
EMI@

T69

CLINK_DATA

2.2K_0804_8P4R_5%
1

2

SPI ROM (8MByte )_SA000039A30

CLINK_CLK

U35

1

Please close to PCH

A

U36

SPI_CS1#

SPI

+3VALW _PCH
R133
1K_0402_5%
1
2 PCH_SPI_IO2

CL_CLK
SPI_CLK

3

2

Tuesday, September 24, 2013

Sheet
1

13

of

59

5

4

3

2

1

D

D

LPT_PCH_DT_EDS

U1B

+3VALW _PCH

RP8
1
2
3
4

8
7
6
5

SUSW ARN#_R
EC_SW I#_R
PCH_GPIO72

10K_8P4R_5%

2
R141
2
R142

C

1
PCH_RSMRST#
10K_0402_5%
1
PM_PW ROK
10K_0402_5%

[6]
[6]

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1

L24
G24

[6]
[6]

DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

F26
K26

[6]
[6]

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1

K24
H24

[6]
[6]

DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

G26
L26

[6]
[6]

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1

C20
D21

[6]
[6]

DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

[6]
[6]

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1

[6]
[6]

DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

B22
A24

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1

B20
B21

DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

C22
B24
A19

+1.5VS
+3VS

L22
K22

2
@ R145

1
PM_PW ROK
10K_0402_5%

+1.5VS

PM_PW ROK

IN1
IN2

OUT

1

10K_0402_5%
2
XDP_DBRESET#

4

SYS_PW ROK

1

2

R15
+3VS

PM_PW ROK

1
@ R148

R147
10K_0402_5% Platform not supporting Intel ME M3 state

3

[43,9]

1

VGATE

GND

[43,5,50]

1
DMI_RCOMP
7.5K_0402_1%
SUSACK#

U3
MC74VHC1G08DFT2G_SC70-5

VCC

5

+3VS

2
R146

2

APWROK can be connected to PWROK.
[5]
[43]

PCH_RSMRST#

[43]

SUSW ARN#

[43,5]
SUSACK#

2
R154

1
SUSW ARN#_R
0_0402_5%

@

DRAMPW ROK

PBTN_OUT#
+3VALW _PCH

1
@ R149
1
@ R151
1
@ R153
2
R155

B

@ESD@
@ESD@
@ESD@
@ESD@
@ESD@
@ESD@

1
C2114
1
C2115
1
C2116
1
C2117
1
C2118
1
C2119
1
C2120

AJ37
N36
W31
AT40
AA32

DRAMPW ROK

AE38

2
PCH_RSMRST#_RAM40
0_0402_5%
2
AG41
SUSW ARN#_R
0_0402_5%
2
AK41
PBTN_OUT#_R
0_0402_5%
1
AM36
PCH_GPIO31
10K_0402_5%
AJ40
PCH_GPIO72
AE36

Stuff R154 if EC does not want to
involve in the handshake mechanism
for the DeepSX state entry and exit

@ESD@

2
PW ROK_R
0_0402_5%

B19

AC35
PCH_GPIO29

AL39

DMI_RXN0
DMI_RXN1
FDI_RXN0
DMI_RXN2
DMI_RXN3

FDI_RXN1

DMI_RXP0
DMI_RXP1

FDI_RXP0
FDI_RXP1

DMI_RXP2
DMI_RXP3

TP16

DMI_TXN0
DMI_TXN1

TP5

DMI

DMI_TXN2
DMI_TXN3

FDI

TP15
TP10

DMI_TXP0
DMI_TXP1

FDI_CSYNC
FDI_INT

DMI_TXP2
DMI_TXP3

FDI_IREF

DMI_IREF

TP17

TP12

TP13

TP7

FDI_RCOMP

N1

FDI_CTX_PRX_N0

FDI_CTX_PRX_N0

P2

FDI_CTX_PRX_N1

FDI_CTX_PRX_N1

[5]

N2

FDI_CTX_PRX_P0

FDI_CTX_PRX_P0

[5]

P3

FDI_CTX_PRX_P1

FDI_CTX_PRX_P1

[5]

R4
PCH_DPW ROK
K5
P5

SYS_PWROK
PWROK

DSWVRMEN

System Power
Management

APWROK

DPWROK
WAKE#

SUS_STAT#/GPIO61

DRAMPWROK

SUSCLK/GPIO62

RSMRST#

SLP_S5#/GPIO63

SUSWARN#/SUSPWRNACK/GPIO30

SLP_S4#

PWRBTN#

SLP_S3#

ACPRESENT/GPIO31

SLP_A#

GPIO72

SLP_SUS#

RI#

PMSYNCH

TP21

SLP_LAN#

L2

FDI_CSYNC

L3

FDI_INT

N11

2
0_0402_5%

PCH_RSMRST#

[6]

[6]
+RTCVCC

+1.5VS

C

R12
DSW VREN

R143

1

2 390K_0402_5%

N12
K2

FDI_RCOMP

1

AM41

DSW VREN

2

+1.5VS

7.5K_0402_1%

AV38

PCH_DPW ROK

AK34

PCIE_W AKE#

PCIE_W AKE#

AD37

SUS_STAT#

T89

PAD

W36

RTC_CLK

T134

PAD

AA35

PM_SLP_S5#

AT35

PM_SLP_S4#

AK40

PM_SLP_S3#

AN37

PM_SLP_A#

T90

AK38

PM_SLP_SUS#

T91

F40

H_PM_SYNC
1

AU36

SLP_WLAN#/GPIO29

2

2
XDP_DBRESET#
0.1U_0402_16V4Z
2
SYS_PW ROK
0.1U_0402_16V4Z
2
DRAMPW ROK
0.1U_0402_16V4Z
2
PW ROK_R
0.1U_0402_16V4Z
2
PCH_RSMRST#_R
0.1U_0402_16V4Z
2
PCH_DPW ROK
0.1U_0402_16V4Z
2
PM_PW ROK
0.1U_0402_16V4Z

@

L5

DMI_RCOMP

SYS_RESET#

1
R140

Stuff R140 if do not support DeepSX state

R144

SUSACK#

[5]

*

：
：

DSWVREN - Internal Deep Sleep 1.05V regulator
H Enable
L Disable

[39,40]

+3VALW _PCH
PM_SLP_S5#

[43]

PM_SLP_S4#

[43]

PM_SLP_S3#

[43]

PCIE_W AKE#
PCH_GPIO29

R150 1
R152 1

2 1K_0402_5%
2 10K_0402_5%

PCH_GPIO29 default GPI
PU to +3VALW base on module design.

PAD
PAD
H_PM_SYNC

B

[5]

@ C2158
0.1U_0402_16V7K
1
2

PCIE_W AKE#

C43
0.1U_0402_16V4Z
@ESD@

V1.0 update

DH82LPDS_FCBGA708

Platform not supporting Intel ME M3 state
PM_SLP_A# can be left NC

ESD request Close to PCH

A

A

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCH_DMI/FDI/PM
Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

14

of

59

5

+3VS

4

PCI PU resistor

2
@ R157
2
@ R158

RP9
1
2
3
4
R159
R160
R161

1
1
1

8
7
6
5

PCI_PIRQD#
PCI_PIRQB#
PCH_GPIO5
PCI_PIRQC#

8.2K_8P4R_5%
2 8.2K_0402_5%
2 8.2K_0402_5%
2 8.2K_0402_5%
8
7
6
5

1
10K_0402_5%
1
10K_0402_5%

2

1

PCH_GPIO53
PCH_GPIO55

Internal pull high
Strap defalut high
GPIO53 DMI AC mode if Low
GPIO55 A16 SWAP OVERRIDE if Low

PCH_GPIO50
PCH_GPIO52
PCH_GPIO54

RP10
1
2
3
4

D

3

PCH_GPIO4
PCI_PIRQA#
PCH_GPIO3
PCH_GPIO2

D

+3VS
8.2K_8P4R_5%

AH3

PCH_CRT_VSYNC

AH2

1

2

CRT_IREF

AF5

649_0402_1%

AG4

[29]

PCH_EDP_PWM

PCH_EDP_PWM

AP2

[29]

PCH_EDP_BLEN
T133

PAD

1
@R167
@
R167
1
@R170
@
R170

DGPU_PWR_EN
[12]

PCH_GPIO51

PCH_EDP_BLEN

AT2

PCH_EDP_VDDEN

AP1

PCI_PIRQA#

AU29

PCI_PIRQB#

AU27

PCI_PIRQC#

AW28

PCI_PIRQD#

AV27

2
0_0402_5%
2
0_0402_5%

PCH_GPIO50

AH26

PCH_GPIO52

AJ26

PCH_GPIO54
PCH_GPIO51

AU31

PCH_GPIO53

AV31

PCH_GPIO55
B

AW33

R30

DDPC_CTRLDATA

VGA_DDC_DATA
VGA_HSYNC

DDPD_CTRLCLK
DDPD_CTRLDATA

DAC_IREF
VGA_IRTN
EDP_BKLTCTL
EDP_BKLTEN
EDP_VDDEN

AN3

PCH_HDMI_CLK

AM2

PCH_HDMI_DATA

AN4

PCH_DPD_CLK

AN2

PCH_DPD_DAT

AK6

DDPB_AUXN

AG7

DDPC_AUXN

PCH_HDMIOUT_DATA
PAD

T92

PAD

T93

[30]

1

HDMI OUT
(To Conn.)

Seperate U10, U57 location
@ R164
0_0402_5%
2

[30]

1

+3VS

eDP
(LVDS Converter)

1

DDPB_AUXN
DDPC_AUXN
DDPD_AUXN
DDPB_AUXP
DDPC_AUXP
DDPD_AUXP
DDPB_HPD

PIRQA#
DDPC_HPD
PIRQB#
DDPD_HPD

PAD
PAD

AG11

PCH_DDPD_AUXN

AK8

DDPB_AUXP

AG6

DDPC_AUXP

AG10

PCH_DDPD_AUXP C113

AJ2

PCH_HDMIOUT_HPD

AH5

DPD_HPD

AJ4

DDPD_HPD

PCH_PLT_RST# 1

T97

C112 1

2 0.1U_0402_16V4Z

PAD

T98

PAD

T99

PCH_DDPD_AUXN_C

[29]

LVDS Converter

PCH_DDPD_AUXP_C

[29]

LVDS Converter

2

IN1
IN2

PIRQD#
PIRQE#/GPIO2
GPIO50

PCI

PIRQF#/GPIO3
PIRQG#/GPIO4

GPIO54
PIRQH#/GPIO5
GPIO51
PME#
GPIO53
PLTRST#
GPIO55

OUT

4

PLT_RST#

PLT_RST#

[21,41,43]

For GPU/TPM/EC

1

2 0.1U_0402_16V4Z

R166
100K_0402_5%

PCH_HDMIOUT_HPD
PAD

[30]

HDMI OUT

T100
R677
1
1
@ R678

LVDS Converter

0_0402_5%
2
2
0_0402_5%

AR30 PCH_GPIO2
1

AV29 PCH_GPIO3
AV28 PCH_GPIO4

+3VALW_PCH
+3VS

v0.3 update
for wake from WLAN(BCM43142)

@ C2029
0.1U_0402_16V4Z

For Card reader/
LAN/WLAN/TV

2

AT27 PCH_GPIO5
AA31 PCI_PME#

PAD T101
PADT101
1

AA37 PCH_PLT_RST#

PCH_DDPD_AUXN_C R172 1

@

2 100K_0402_5%
+3VS

PCH_DDPD_AUXP_C R173 1

@

2 100K_0402_5%

1
C2121
0.1U_0402_16V4Z
2
@ESD@

2

IN1
IN2

CRB Reserve PU/PL

U5
MC74VHC1G08DFT2G_SC70-5
OUT

4

PLT_A_RST# [36,39,40]
B

1
R171
100K_0402_5%
2

DH82LPDS_FCBGA708

C

U4
MC74VHC1G08DFT2G_SC70-5

T96

PIRQC#

GPIO52

C111
0.1U_0402_16V4Z

2

VGA_VSYNC

LVDS

[23,43]

2

2
PCH_CRT_HSYNC

DDPC_CTRLCLK

VGA_DDC_CLK

PCH_HDMIOUT_CLK

1

AL3

VGA_RED

PCH_HDMIOUT_DATA

2

PCH_CRT_DATA

CRT_IREF Close to PCH <500mils

DGPU_HOLD_RST#

[29]

R606
100K_0402_5%

1

AL2

DDPB_CTRLDATA

PCH_HDMIOUT_CLK

AJ5

5

AC2

PCH_CRT_CLK

VGA_GREEN

AM1

VCC

PCH_CRT_R

DDPB_CTRLCLK

GND

PCH_CRT_VSYNC

R165

[21,43]

PCH_DDPD_HPD

2
0_0402_5%

3

[41]

AE2

5

PCH_CRT_HSYNC

PCH_CRT_G

Data Need longer than CLK 1 inch

LPT_PCH_DT_EDS

VGA_BLUE

VCC

PCH_CRT_DATA

[41]

v0.2 update

1

1
R605 @

GND

[41]

Disable use 1K on mobile

To Converter

Q57
BSS138LT1G_SOT23-3

3

2.2K_0804_8P4R_5%

3

PCH_CRT_CLK

AC3

DISPLAY

PCH_CRT_R

[41]

DDPD_HPD

D

[41]

8
7
6
5

S

PCH_CRT_G

U1E

PCH_CRT_B

CRT

C

Close to PCH <250mils

PCH_CRT_B

[41]

1
2
3
4

PCH_DPD_CLK
PCH_DPD_DAT
PCH_HDMIOUT_CLK
PCH_HDMIOUT_DATA

NOTE:PCH adds support for panel power sequencing required for
embedded DisplayPort support. L_VDDEN, L_BKLTEN and L_BKLTCTL pins are
added on the PCH for panel power sequencing. It is important to note that a 6
layer board design may be required to access these pins on the PCH package
in a fully featured platform design.

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

150_0804_8P4R_1%
CRT@
[41]

+5VS

RP17

2
PCH_CRT_CLK
2.2K_0402_5%
2
PCH_CRT_DATA
2.2K_0402_5%

G

1 CRT@
R162
1 CRT@
R163
RP11
1
8
2
7
3
6
4
5

2

C2135
ESD@
0.1U_0402_16V4Z
v0.2 update

A

A

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2014/04/01

Title

PCH_CRT/DDC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

15

of

59

4

C117/C118 --> Close to U36
C115/C116 --> Close to U25
C119/C120 --> Close to JMINI2

D

[36]
[36]

Card Reader

LAN

[36]
[36]

PCIE_PTX_C_CRRX_N1
PCIE_PTX_C_CRRX_P1

[39]
[39]

PCIE_PRX_LANTX_N2
PCIE_PRX_LANTX_P2

TV Card

PCIE_PTX_C_LANRX_N2
PCIE_PTX_C_LANRX_P2

[40]
[40]

PCIE_PRX_W LANTX_N3
PCIE_PRX_W LANTX_P3

[40]
[40]

PCIE_PTX_C_W LANRX_N3
PCIE_PTX_C_W LANRX_P3

[40]
[40]

PCIE_PRX_TVTX_N4
PCIE_PRX_TVTX_P4

[40]
[40]

PCIE_PTX_TVRX_N4
PCIE_PTX_TVRX_P4

C115
C116

2
2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

C117
C118

2
2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

C119
C120

2
2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

PCIE_PRX_CRTX_N1
PCIE_PRX_CRTX_P1

L14
K14

PCIE_PTX_CRRX_N1
PCIE_PTX_CRRX_P1

B12
B11

PCIE_PRX_LANTX_N2
PCIE_PRX_LANTX_P2

F14
G14

PCIE_PTX_LANRX_N2
PCIE_PTX_LANRX_P2

D11
C11

PCIE_PRX_W LANTX_N3
PCIE_PRX_W LANTX_P3

F11
H11

PCIE_PTX_W LANRX_N3
PCIE_PTX_W LANRX_P3

B9
A9

PCIE_PRX_TVTX_N4
PCIE_PRX_TVTX_P4

J11
L11

PCIE_PTX_TVRX_N4
PCIE_PTX_TVRX_P4

B8
C8

T102
T103

PAD
PAD

T104
T105

PAD
PAD

T106
T107

PAD
PAD

T108
T109

PAD
PAD

G9
F9
B7
A7
F7
H7
E1
D2
K6
K8
G3
G5

PCIE Port 7~8 Is Disable For H81

J2
J3
H2
H1
B13

+1.5VS
T112
T113
B

1

+1.5VS

1

R175

2

PAD
PAD
PCIE_RCOMP

L16
K16
C13

D

LPT_PCH_DT_EDS

U1I
PERN1/USB3RN3
PERP1/USB3RP3

USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB2N8
USB2P8
USB2N9
USB2P9
USB2N10
USB2P10
USB2N11
USB2P11
USB2N12
USB2P12
USB2N13
USB2P13

PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4

PCIe

0.1U close to JMINI1
C

2

CAM & Touch Can't in same USB2.0 Controller for C38

Close to device side

PCIE_PRX_CRTX_N1
PCIE_PRX_CRTX_P1

[39]
[39]

WLAN

3

PERN5
PERP5
PETN5
PETP5

USB

5

USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6

PERN6
PERP6
PETN6
PETP6
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8

USBRBIAS#
USBRBIAS

PCIE_IREF

TP24
TP23

TP11

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14

TP6
PCIE_RCOMP

7.5K_0402_1%

AV10
AU10
AV11
AW11
AN14
AP14
AJ16
AK16
AU15
AV15
AU12
AT12
AV14
AW14
AU17
AT17
AW16
AV16
AN16
AP16
AJ18
AK18
AP18
AN18
AW18
AV18
AP20
AN20

USB20_N0
USB20_P0
USB20_DEBN1
USB20_DEBP1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5

F20
G20
B18
C18
G18
H18
B15
B16
K20
L20
D15
C15
L18
K18
B14
A14

U3RXDN_A
U3RXDP_A
U3TXDN_A
U3TXDP_A
U3RXDN_B
U3RXDP_B
U3TXDN_B
U3TXDP_B

AV20
AU20

USBBIAS

AK14
AJ14
AE40
AF37
AD39
AD40
AF39
AC41
AF40
AG40

USB20_N0 [33]
USB20_P0 [33]
USB20_DEBN1 [33]
USB20_DEBP1 [33]
USB20_N2 [34]
USB20_P2 [34]
USB20_N3 [34]
USB20_P3 [34]
USB20_N4 [40]
WLAN
USB20_P4 [40]
USB20_N5 [41]
Touch
USB20_P5 [41]

USB 3.0 side IO
Rear IO USB 2.0 Port 1 & 2

USB2.0 Port 6,7,12,13 Is Disable For H81
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11

USB20_N8 [34]
USB20_P8 [34]
USB20_DEBN9 [34]
USB20_DEBP9 [34]
USB20_N10 [40]
USB20_P10 [40]
USB20_N11 [41]
USB20_P11 [41]

Rear IO USB 2.0 Port 3 & 4
TV
Int. Camera

USB2.0 Port 6,7,12,13 Is Disable For H81
C

U3RXDN_A
U3RXDP_A
U3TXDN_A
U3TXDP_A
U3RXDN_B
U3RXDP_B
U3TXDN_B
U3TXDP_B

[33]
[33]
[33]
[33]
[33]
[33]
[33]
[33]

Side IO USB 3.0 Port 2 (Charger)

Side IO USB 3.0 Port 1 (Debug)

USB3.0 Port 5~6 Is Disable For H81
1
R174
PAD
PAD

2
22.6_0402_1%

USB_BIAS trace <500mils

T110
T111

USB30_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

USB30_OC#0 [33]
USB_OC#1 [34]

Side IO USB 3.0 Port 1 & 2
Rear IO USB 2.0 Port 1 & 2

USB_OC#5

Rear IO USB 2.0 Port 3 & 4

[34]

+3VALW _PCH

B

RP12
DH82LPDS_FCBGA708

USB_OC#1
USB_OC#6
USB_OC#4
USB_OC#7

1
2
3
4

USB_OC#5
USB_OC#2
USB_OC#3
USB30_OC#0

1
2
3
4

8
7
6
5
10K_8P4R_5%
RP13
8
7
6
5
10K_8P4R_5%

A

A

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCH_PCI-E/USB
Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

16

of

59

5

4

3

2

GPIO8 no longer a strap,
GPIO8 is determined /override by soft strap.

8
7
6
5

@ESD@ C2122
1

1

PCH_GPIO0
EC_SMI#

C

1
10K_0402_5%

PCH_GPIO27

T115

PAD

In Deep Sleep Power Well. Unmuxed.
Defaults to GPI.
Not used Weak pull-up 10kΩ to VccDSW3_3
-->Check list1.5 P402.
PD to GND for Huron River!!
GPIO28
On-Die PLL Voltage Regulator
H: Enable
L: Disable

1

+3VALW _PCH

2

R201
1K_0402_5%

G38

EC_SMI#

AC40

PCH_GPIO15

AC32

PCH_GPIO16

M39

AL40

GPO

+3VALW _PCH
2
R199

LPT_PCH_DT_EDS

PCH_GPIO22

L38

PCH_GPIO24

AE34

PCH_GPIO27

AU34

PCH_GPIO28

V41

PCH_GPIO32

N32

PCH_GPIO34

N34

PCH_GPIO35

M40

GPO

PCH_GPIO36

H40

GPO

PCH_GPIO37

N41

PCH_GPIO38

H41

PCH_GPIO39

R31

PCH_GPIO48

L40

PCH_GPIO49

N40

PCH_GPIO57

AC36

BMBUSY#/GPIO0

TP14

GPIO8

PECI

LAN_PHY_PWR_CTRL/GPIO12
GPIO15
SATA4GP/GPIO16
SCLOCK/GPIO22
GPIO24
GPIO27
GPIO28

RCIN#
PROCPWRGD
THRMTRIP#
PLTRST_PROC#
VSS

2
10K_0402_5%
2
1K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

PCH_GPIO36
PCH_GPIO37
PCH_GPIO36
PCH_GPIO37

1

1

GPIO70_H@
R182
10K_0402_5%

R183
10K_0402_5%

GPIO69_L@
R187
10K_0402_5%

2

2

PCH_GPIO70

PCH_GPIO71

1

GPIO68_L@
R188
10K_0402_5%

PCH_GPIO69

GPIO70_L@
R189
10K_0402_5%

@
R190
10K_0402_5%

GPIO32
PWM0
GPIO34
PWM1
GPIO35/NMI#
PWM2
SATA2GP/GPIO36
PWM3
SATA3GP/GPIO37
TACH0/GPIO17
SLOAD/GPIO38
TACH1/GPIO1
SDATAOUT0/GPIO39

FAN

SDATAOUT1/GPIO48

TACH2/GPIO6
TACH3/GPIO7

SATA5GP/GPIO49
TACH4/GPIO68
GPIO57

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K36
D40

H_PW RGOOD

C40

H_THERMTRIP#

G40

TACH7/GPIO71

Server/Workstation only.

H_PECI
KB_RST#

[5]

H_THERMTRIP# [5]
DGPU_THERMTRIP#

2
0_0402_5%

CPU_PLTRST#

1

2
10K_0402_5%
2
10K_0402_5%

[43]

H_PW RGOOD

V28

1
R194
1
R196

KB_RST#

[43,5]

[21]

[5]

C2124
0.1U_0402_16V4Z
@ESD@

1
H_PW RGOOD
@ESD@ C2125

2
0.1U_0402_16V4Z

H_THERMTRIP# 1
@EMI@ C125

2
0.1U_0402_16V4Z

C

AL31

V0.3 update for sequence EA

AM31
AP31
AV30
AP28

PCH_GPIO17

AT31

PCH_GPIO1

AM28

PCH_GPIO6

AV34

EC_SCI#

AT30

PCH_GPIO68

AV35

PCH_GPIO69

AK28

PCH_GPIO70

AT34

PCH_GPIO71

AJ31

PCH_SST

1
@ R200

2
0_0402_5%

EC_SCI#

DGPU_PW ROK

[23,52,53]

[43]

PCHSTRAP 4&9

Config
PADT116
PADT116

Set by GPIO16/49

11

USB X6,PCIEX8,SATAX4

01

USB X4,PCIEX8,SATAX6

00

B

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTF

Clock validation strap
ICG is EN when LOW
*GPIO36 with internal pull-down

SST

[43]
GATEA20

5P_0402_50V
2
2
0_0402_5%

1
@ R197

F41

+3VS

0.1U_0402_16V4Z
2
GATEA20

@ESD@ C2123
1
1
PCH_PECI_R
@ R195
KB_RST#

2

TACH6/GPIO70
AT1
AT41
AU1
AV1
AV2
AV40
AV41
AW2
AW40
B40
B41
C41
D1
D41
AC31

N30

GPIO

PCH_GPIO28

1
@ R202
1
@ R203
1
@ R204
1
@ R206

PCH_GPIO68

GATEA20

TACH5/GPIO69

+3VS

GPIO69_H@
R180
10K_0402_5%

D

PCH_GPIO32

U1F

[43]

GPIO68_H@
R181
10K_0402_5%

+3VS

PCH_GPIO35
PCH_GPIO22
PCH_GPIO34

The current default is clock enable

B

PCH_GPIO48

10K_8P4R_5%

This signal has a weak internal pull-up but
requires an external pull down.

*

PCH_GPIO39

RP15
1
2
3
4

EC_SMI#
@
R193
1K_0402_5%

PCH_GPIO38

+3VS

2

@
R192
10K_0402_5%

PCH_GPIO24

CPU/Misc

1

+3VALW _PCH

2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

+3VS

2

1
R663
1
R184
1
R185
1
R186
1
@ R191

+3VS

1

10K_8P4R_5%

Integrated Clock Chip Enable (Removed)
H: Disable
L: Enable

2

PCH_GPIO1
PCH_GPIO6
EC_SCI#
PCH_GPIO17

2

GPIO8

8
7
6
5

SKU ID TABLE

1

1
2
3
4

2
PCH_GPIO57
10K_0402_5%

GPIO68 GPIO69 GPIO69
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

2

1
R179

SKU ID
SKU1
SKU2
SKU3
SKU4
SKU5
SKU6
SKU7
SKU8

120821

1

2
PCH_GPIO0
10K_0402_5%

2

1
R177

PCH_GPIO15

1

1
1K_0402_5%

RP14

*

1

2

2
R176

D

2

+3VS

1

+3VALW _PCH

AF3
AV21
V38
V40
W12
W20
W22
W28
W3

+3VS
1
R205
1
R207

2
PCH_GPIO16
10K_0402_5%
2
PCH_GPIO49
10K_0402_5%

DH82LPDS_FCBGA708

TLS
Hi:with confidentiality
Low:with no confidentiality
*GPIO37 with internal pull-down

A

A

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCH_CPU/GPIO
Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

17

of

59

5

4

3

2

1

+PCH_VCCDSW3_3

1

1

2

AH18
AH20
AH22
AJ20

+1.05VS_VPCH

U8
+3VS

AF26

AM7
AM9

2

C

AV3
AV4

@ CH17
1U_0402_6.3V6K

1

Integrated VRMs enabled. DCPSUS1, DCPSUS2 and
DCPSUS3 can be left floating.

AW3
AW4
AW9
U12
V14
W14

+PCH_VCCCLK

AB2
AA16
W16

Close to AW21
+3VALW_PCH

AC12

VCCIO
VCCVRM

Azalia

VCC

AW26

VCCSUSHDA

VCCCLK3_3
VCCCLK3_3

VCCCLK3_3
VCCCLK3_3
VCCCLK3_3
VCCCLK3_3
VCCCLK3_3
VCCCLK3_3

V_PROC_IO

SPI

VCCSPI

AW35

CH14
1
2
1

0.1U_0402_16V4Z
C39

+3VALW_PCH

+PCH_VPROC

R41

1

2
0_0402_5%

@

RH10
W26

VCCASW

2

2

1

2

2

2

2

1

2

Close to B6

Close to AG1
Close to AW26

Close to AP35

Close to AP33

C

T14

VCCVRM

+PCH_VPROC

B4

VCCVRM

+1.05VS_VPCH
C1

VCCVRM

+PCH_VPROC
C2

1

Close to T14

2

Close C39

1

2

1

2

CH22
1U_0402_6.3V6K

+1.5VS
1

CH21
0.1U_0402_16V4Z

VCCVRM

VCCCLK
VCCCLK

CH20
0.1U_0402_16V4Z

DH82LPDS_FCBGA708

+1.05VS_VPCH

AD25

VCCASW
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCCLK

+PCH_DCPRTC

1

VCCCLK3_3
VCCCLK3_3
VCCCLK3_3

1

AP33

VCCRTC

Internal DCPRTC
VRM

CPU

+RTCVCC

AP35

VCCSUS3_3

RTC

VCCCLK3_3
VCCCLK3_3

1

1

1
@ R210

2
0_0805_5%

+PCH_VCCCLK

1
@ R211

2
0_0805_5%

Place near pin U12

2

Place near pin W14

Place near pin AB2

1

2

CH28
1U_0402_6.3V6K

+3VS

2

1

CH27
1U_0402_6.3V6K

AA16, W16

2

1

CH26
1U_0402_6.3V6K

2

1

CH25
1U_0402_6.3V6K

1

CH24
1U_0402_6.3V6K

2

@ CH23
10U_0603_6.3V6M

1

B

2

+3VALW_PCH

2

+1.05VS_VPCH

1

+1.05VS_VPCH

DCPSUS2

CH19
0.1U_0402_16V4Z

T16
V16

2
0.1U_0402_16V4Z

CH18
1U_0402_6.3V6K

2
+PCH_USB_DCPSUS2
0_0402_5%

1

AG1
B6
AW21

VCC3_3
VCC3_3
VCC3_3

ICC

1
@ RH3

AG12
AK11

D

CH16
1U_0402_6.3V6K

AR4
AT5
+1.05VS_VPCH

+PCH_VCCSST
CH5

CH15
0.1U_0402_16V4Z

AP5
AP7

+PCH_VCCCLK3_3

AH28

Close to AW39

+3VS

DCPSST
GPIO/LPCInternal
VRM

VCCIO
VCCIO
VCCIO
VCCIO

+PCH_VCCDSW3_3

CH13
1U_0402_6.3V6K

2

close to M14

+PCH_VCC

VCC3_3

2

AW38
AW39
AV39

CH9
0.1U_0402_16V4Z

1

AB1

+PCH_VCC

VCCUSBPLL

1

2

+3VALW_PCH

CH12
0.1U_0402_16V4Z

2

A40
CH11
10U_0603_6.3V6M

close to AF26

1

CH10
1U_0402_6.3V6K

close to AP22

AJ22

+PCH_USB_DCPSUS2

+1.05V_+1.5V_RUN

VCCDSW3_3
VCCDSW3_3
VCCDSW3_3

VSS

1

0_0402_5%

CH8
1U_0402_6.3V6K

2

AF20
AF22
AF23
M14

+1.05VS_VPCH

AK20
P20

VCCSUS3_3
VCCSUS3_3

2

@ RH1

CH7
0.1U_0402_16V4Z

1

CH6
1U_0402_6.3V6K

2

AP22

CH3
1U_0402_6.3V6K

+3VALW_PCH

VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3

USB

1

CH2
1U_0402_6.3V6K

CH1
0.1U_0402_16V4Z

D

LPT_PCH_DT_EDS

U1H

CH4
0.1U_0402_16V4Z

Close to AK20
+3VALW_PCH

Place near pin V16

B

+PCH_VCCCLK3_3
1
@ R212

2
0_0805_5%

R213
1K_0402_5%

+RTCVCC

2

Place near pin AR4

Place near pin AT5

1

2

CH32
1U_0402_6.3V6K

+1.05VS_VPCH

2

1

CH31
1U_0402_6.3V6K

Place near pin AV4

1

CH30
1U_0402_6.3V6K

2

CH29
1U_0402_6.3V6K

1

D1
2+RTCBATT_R

+RTCVCC

3
@ C127
0.1U_0402_16V4Z

Place near pin AP5

1

1

2

2

1

2

1

+RTCBATT

+3VSB

BAV70W_SOT323-3
C128
1U_0402_6.3V6K

Close to AP33

+PCH_VCC

1

2

1

2

CH34
1U_0402_6.3V6K

10uH

+PCH_VCC
CH33
10U_0603_6.3V6M

LH1
1
2
10UH_LQM21FN100M70L _20%

A

A

Place near pin AB1

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/01

Deciphered Date

2014/04/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PCH_POWER-1
Size
C
Date:

5

4

3

2

Document Number

Rev
0.3

ZEA00 LA-A061P M/B
Tuesday, September 24, 2013
1

Sheet

18

of

59

5

4

3

2

1

If CRT disable Pin AF2 & Pin AE1 can connect to GND
1

2
RH11

0_0402_5%

D

CRT@
1

+VCCADAC

1

2

C129

VCCIO
VCCIO
VCC3_3
VCC3_3

HVCMOS

DCPSUS1

Internal
DCPSUSBYPVRM
DCPSUSBYP
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW

VCCSUS3_3
VCCSUS3_3

USB3

DCPSUS3
VCCIO
VCCVRM
VCCVRM
VCCVRM

PCIe/DMI

VCCVRM
VCCIO
VCCVRM

SATA

VCCIO

VCCMPHY

+3VS
2

P16
+3VALW_PCH
U30
W30
AE30

P19
P17
A38
K1
A4

Close to AN33 2
+PCH_USB_DCPSUS3
+1.05VS_VPCH

P22

+1.05VS_VPCH

1

P23
P25
P26
P28
T19
T20
AF19

+1.05VS_VPCH

+1.05V_+1.5V_RUN
2

1
0_0603_5%

@

RH8

1

2

1

2

2

1

2

+1.05V_+1.5V_RUN

1

2

1

2

VCC

1.05V

1.29 A

VCCIO

1.05V

3.629 A

VCCADAC1_5

1.5V

0.070 A

VCCADAC3_3

3.3V

0.0133 A

VCCCLK

1.05V

0.306 A

VCCCLK3_3

3.3V

0.055 A

VCCVRM

1.5V

0.179 A

VCC3_3

3.3V

0.133 A

VCCASW

1.05V

0.67 A

VCCSUSHDA

3.3V

0.01 A

VCCSPI

3.3V

0.022 A

VCCSUS3_3

3.3V

0.261 A

VCCDSW3_3

3.3V

0.015 A

V_PROC_IO

1.05V

0.004 A

C

+1.05VS_VPCH
@
+PCH_USB_DCPSUS1
0_0402_5%
1

2

Close to P17,P26,P28,AF19

@ CH57
1U_0402_6.3V6K

+PCH_VCCDSW_R

2

S0 Iccmax Current (A)

Close to W30

CH56
10U_0603_6.3V6M

2

1

CH55
10U_0603_6.3V6M

2

1

CH54
1U_0402_6.3V6K

+1.5VS

1

CH53
1U_0402_6.3V6K

+PCH_VCCDSW
5.11_0402_1%

2

+1.05V_+1.5V_RUN

A39

1

Voltage

Close to P14, P16

B39

CH52
1U_0402_6.3V6K

B

2

1

+1.05V_+1.5V_RUN

2

1

1

+PCH_USB_DCPSUS1

AM33
AN33

DH82LPDS_FCBGA708

RH7

1

P14

CH51
1U_0402_6.3V6K

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

0_0402_5%

B37

CH50
10U_0603_6.3V6M

Close to PIN AD17,AD19

VCCVRM

+1.05VS_VPCH

CH49
10U_0603_6.3V6M

2

0_0402_5%
2
+3VS
2

RH5

FDI

+1.05V_+1.5V_RUN

@ CH48
10U_0603_6.3V6M

1

CRT@ RH4
1
1

AE1 +3VS_AE1

As Intel recommend to unpop

CH44
0.1U_0402_16V4Z

2

CH47
1U_0402_6.3V6K

1

22U_0805_6.3V6M

2

CH46
10U_0603_6.3V6M

1

AU41
AU40
AA23
AA25
AA26
AB22
AB23
AB25
AB26
AD17
AD19
AD20
AD22
AD23
AF25

V26

Voltage Rail

@

CH45
0.1U_0402_16V4Z

+PCH_VCCDSW

VSS
VCCADACBG3_3

Core

+1.05VS_VPCH

CRT DAC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

+1.5VS

CH43
1U_0402_6.3V6K

2

AA19
AA20
AB16
AB17
AB19
AB20
AD16
V17
V19
V20
V22
V23
V25
W17
W19
W23
W25

CH39
1U_0402_6.3V6K

2

1

CH38
1U_0402_6.3V6K

C

1

CH37
1U_0402_6.3V6K

2

CH41
10U_0603_6.3V6M

1

AF2

2

2
BLM18PG181SN1D_0603

@CH42
@
CH42
10U_0603_6.3V6M

VCCADAC1_5

2

1

CH36
10U_0603_6.3V6M

+1.05VS_VPCH

1

CRT@ CH40
0.1U_0402_16V4Z

2
LPT_PCH_DT_EDS

U1G

CRT@ CH35
0.01U_0402_16V7K

1

D

PCH Power Rail Table

LH2

2

1
RH6

Integrated VRMs enabled. DCPSUS1, DCPSUS2 and
DCPSUS3 can be left floating.

B

+1.05VS_VPCH
+PCH_USB_DCPSUS3

2

1

2

@ CH60
1U_0402_6.3V6K

1

@ CH59
10U_0603_6.3V6M

2

@

CH58
1U_0402_6.3V6K

1

1
RH9

2
0_0603_5%

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/01

2014/04/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCH_POWER-2
Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

19

of

59

5

4

U1J
A12
A16
A21
A35
B3
B25
B30
B33
B38
C6
C25
C37
D4
D6
D7
D8
D9
D12
D13
D14
D16
D18
D19
D20
D22
D24
D25
D26
D27
D28
D31
D32
D34
D37
E3
E4
E5
E7
E12
E31
E35
E38
F18
F24
F35
F37
F38

D

C

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

3

2

1

LPT_PCH_DT_EDS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G2
H4
H6
H8
H9
H14
H16
H20
H22
H26
H28
H33
H34
H38
J5
J31
J37
K4
K9
K31
L37
L41
M16
M18
M20
M22
M24
M26
M28
N4
N8
N31
N35
N38
R1
R8
R10
R34
T17
T22
T23
T25
T26
T28
U1
U4
U31

U1K
U32
W5
W8
Y1
Y41
AA5
AA8
AA10
AA11
AA12
AA14
AA17
AA22
AA28
AA30
AA34
AB4
AB14
AB28
AC5
AC8
AC30
AC34
AC38
AD14
AD26
AD28
AE4
AE8
AE12
AE31
AE41
AF14
AF16
AF17
AF28
AG2
AG8
AG30
AG34
AG38
AH14
AH16
AJ1
AJ28
AK9

DH82LPDS_FCBGA708

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

LPT_PCH_DT_EDS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AK24
AK37
AL5
AL11
AL37
AM4
AM6
AM8
AM14
AM16
AM18
AM20
AM24
AM26
AM35
AM38
AN28
AP4
AP9
AR11
AR35
AR37
AT7
AT8
AT10
AT11
AT14
AT15
AT16
AT18
AT20
AT21
AT23
AT24
AT28
AT29
AT33
AT36
AT38
AU3
AU39
AV12
AV17
AV33
AW7
AW30

D

C

DH82LPDS_FCBGA708

B

B

A

A

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCH_GND
Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

20

of

59

5

4

C

Reserve for x16 GPU

@
R228
0_0402_5%
2

@
R229
10K_0402_5%

+3VS_VGA
B

1
R230

2
200_0402_1%

4

Y
A

@

AJ12
AP29

PLT_RST_VGA#
PEX_TERMP

T117
T118

2

R234
2.49K_0402_1%
DIS@

v0.2 update

3
4

1

GPU_PWM_VID
VGA_GPIO12
NVVDD_PSI

GPU_PWM_VID
NVVDD_PSI

0327
T130

VGA_GPIO16

[52]

0327 Update

[52]

Update

0327 Update
+3VS_VGA
DIS@
EVENT#_R
VGA_EDID_CLK
VGA_EDID_DATA

DACA_RED
DACA_GREEN
DACA_BLUE
DACA_HSYNC
DACA_VSYNC
DACA_VDD
DACA_VREF
DACA_RSET

I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA

VGA_CRT_CLK

AM9
AN9

I2CB_SCL
I2CB_SDA

AG10
AP9
AP8

2

+DACA_VDD

1 DIS@
R224
10K_0402_5%

OVERT#
VGA_GPIO12

C

0327 Update

R4
R5

VGA_CRT_CLK
VGA_CRT_DATA

R7
R6

I2CB_SCL
I2CB_SDA

R2
R3

VGA_EDID_CLK
VGA_EDID_DATA

T4
T3

VGA_SMB_CK2
VGA_SMB_DA2

60mA
PLLVDD
SP_PLLVDD

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

VGA_CRT_DATA

2
DIS@ 10K_0402_5%
2
DIS@ 2.2K_0402_5%
2
DIS@ 2.2K_0402_5%
2
DIS@ 2.2K_0402_5%
2
DIS@ 2.2K_0402_5%
2
DIS@ 2.2K_0402_5%
2
DIS@ 2.2K_0402_5%
2
DIS@ 10K_0402_5%
2
10K_0402_5%

+1.05VS_VGA

30 ohms @100MHz (ESR=0.05)

PEX_WAKE_N
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N

AK9
AL10
AL9

1
R217
1
R218
1
R219
1
R220
1
R221
1
R222
1
R223
1
R225
1
R226

PEX_RST_N
PEX_TERMP

VID_PLLVDD
XTAL_IN
XTAL_OUT
XTAL_OUTBUFF
XTAL_SSIN

AD8
AE8
AD7

R227 1
@
2
0_0402_5%

45mA
45mA

+SP_PLLVDD

H3
H2

XTALIN
XTAL_OUT

J4
H1

XTALOUT
XTALSSIN

1

2

DIS@

1

2

Near GPU
B

DIS@

Under GPU

DIS@ R232
10K_0402_5%

N14M-GE2-B-AIO-A2

DIS@ L1
1
2
SBY100505T-300Y-N_0402

+PLLVDD

R233
10K_0402_5%
DIS@

1

v0.2 update

D

2

OVERT#
EVENT#_R

2

R231
100K_0402_5%

DIS@
Q4A
DMN66D0LDW-7 2N_SOT363-6

0327 Update

[17]

Q4B
DMN66D0LDW-7 2N_SOT363-6
DIS@

5

T119
T120

2

3

U7
MC74VHC1G08DFT2G SC70 5P

DGPU_THERMTRIP#

0.1U_0402_10V6K

0327 Update

T129

GPU_VID1
GPU_VID2

2 10K_0402_5%
1

6

VGA_GPIO3

1

B

AJ26
AK26

Differential signal

1

1

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#

AJ11

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

GPU_VID4
GPU_VID3

1

2

DGPU_HOLD_RST#

P

PLT_RST#

CLK_REQ_GPU#

AL13
AK13
AK12

[13] CLK_PCIE_VGA
[13] CLK_PCIE_VGA#

5
[15,43]

PCIE_GTX_CRX_P0
PCIE_GTX_CRX_N0
PCIE_GTX_CRX_P1
PCIE_GTX_CRX_N1
PCIE_GTX_CRX_P2
PCIE_GTX_CRX_N2
PCIE_GTX_CRX_P3
PCIE_GTX_CRX_N3
PCIE_GTX_CRX_P4
PCIE_GTX_CRX_N4
PCIE_GTX_CRX_P5
PCIE_GTX_CRX_N5
PCIE_GTX_CRX_P6
PCIE_GTX_CRX_N6
PCIE_GTX_CRX_P7
PCIE_GTX_CRX_N7
PCIE_GTX_CRX_P8
PCIE_GTX_CRX_N8
PCIE_GTX_CRX_P9
PCIE_GTX_CRX_N9
PCIE_GTX_CRX_P10
PCIE_GTX_CRX_N10
PCIE_GTX_CRX_P11
PCIE_GTX_CRX_N11
PCIE_GTX_CRX_P12
PCIE_GTX_CRX_N12
PCIE_GTX_CRX_P13
PCIE_GTX_CRX_N13
PCIE_GTX_CRX_P14
PCIE_GTX_CRX_N14
PCIE_GTX_CRX_P15
PCIE_GTX_CRX_N15

G

[15,41,43]

0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K

AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25

+3VS_VGA

2

1

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

P6
M3
L6
P5
P7
L7
M7
N8
M1
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1

DIS@
R214
1
@
C130
2

C164

PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_N3
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_N5
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_N6
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_N7
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_P15
PCIE_GTX_C_CRX_N15

C131 1
C132 1
C133 1
C134 1
C135 1
C136 1
C137 1
C138 1
C139 1
C140 1
C141 1
C142 1
C143 1
C144 1
C145 1
C146 1
C2096 1
C2097 1
C2098 1
C2099 1
C2100 1
C2101 1
C2102 1
C2103 1
C2104 1
C2105 1
C2106 1
C2107 1
C2108 1
C2109 1
C2110 1
C2111 1

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

+3VS_VGA
Part 1 of 7

C163

Reserve for x16 GPU

DIS@

22U_0805_6.3V6M

D

AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27

0.1U_0402_10V6K

PCIE_GTX_C_CRX_N[0..15]

PCIE_GTX_C_CRX_N[0..15]

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N15

1

PCIE_GTX_C_CRX_P[0..15]

PLT_RST#

1

2

[6]

U6A
PCIE_GTX_C_CRX_P[0..15]

GPIO

[6]

2

PCIE_CTX_C_GRX_N[0..15]

DACs

PCIE_CTX_C_GRX_N[0..15]

I2C

[6]

3

PCIE_CTX_C_GRX_P[0..15]

CLK

PCIE_CTX_C_GRX_P[0..15]

PCI EXPRESS

[6]

Under GPU(below 150mils)
Put C169 close to U65.AE8
+3VS_VGA

EC_SMB_CK2

[13,43,46]

1

2N7002DW-T/R7_SOT363-6

@
R238
10K_0402_5%

XTALIN

1

OSC

NC

XTAL_OUT

VGA_SMB_DA2

2

DIS@
Q5A
1

6

EC_SMB_DA2

[13,43,46]

DIS@ C171
10P_0402_50V8J

1
4

C169

C167

C166

C165

C168

2
DIS@

2
DIS@
A

1

2

v0.3 update

Reserve pull-up and down.
Don’t have to install
component for default, NV
reply on 5/4. when system
no support CLKREQ

Compal Secret Data

Security Classification
Issued Date

2013/04/01

2014/04/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

2
DIS@

1

@
R239
10K_0402_5%

2N7002DW-T/R7_SOT363-6

2
DIS@

1

2

27MHZ 10PF +-20PPM X3G027000DA1H

2

2
DIS@

1

0.1U_0402_10V6K

3

+SP_PLLVDD

1

0.1U_0402_10V6K

OSC

2

CLK_REQ_GPU#

DIS@ C170
10P_0402_50V8J

1

1

0.1U_0402_10V6K

DIS@
Q5B
3

DIS@ Y3
4
NC

2

1

1
A

180ohms (ESR=0.2) Bead

+3VS_VGA

4

VGA_SMB_CK2

150mA

1
2
DIS@ L2
BLM18PG330SN1D_0603

4.7U_0402_6.3V6M

DIS@
R237
2.2K_0402_5%

5

2

2

DIS@
R236
2.2K_0402_5%

1
2
DIS@ R235 10M_0402_5%

22U_0805_6.3V6M

+1.05VS_VGA

+3VS_VGA

3

2

Compal Electronics, Inc.
N14M-GE2-PCIE/DAC/GPIO
Document Number

Rev
0.3

ZEA00 LA-A061P M/B
Tuesday, September 24, 2013

Sheet
1

21

of

59

5

4

3

U6D

2

1

DIS@
Part 4 of 7

IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5
AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1

IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N
IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N

B

AK3
AK2
AB3
AB4
AF3
AF2

VGA_VSS_SENSE

VGA_VCC_SENSE

[52]

VGA_VSS_SENSE

[52]

trace width: 16mils
differential voltage sensing.
differential signal routing.

DIS@

2
1
R624
100_0402_1%

TEST
TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

AK11
AM10
AM11
AP12
AP11
AN11

TESTMODE

1
R241
DIS@

T122
T123
T124
T125

2
10K_0402_5%

10K_0402_5%
R240
DIS@

C

SERIAL
ROM_CS_N
ROM_SCLK
ROM_SI
ROM_SO

H6
H4
H5
H7

ROM_CS
ROM_SCLK
ROM_SI
ROM_SO

L2

R242 DIS@
2

GENERAL
BUFRST_N
CEC
MULTI_STRAP_REF0_GND

AG3
AG2

L5

VGA_VCC_SENSE

1

IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N

GND_SENSE

L4

2

C

IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

LVDS/TMDS

AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5

D

+VGA_CORE

R623
100_0402_1%
DIS@

VDD_SENSE
AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4

P8
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
T8
V32

2

AJ9
AH9
AP6
AP5
AM7
AL7
AN8
AM8
AK8
AL8

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1

D

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N

NC

AM6
AN6
AP3
AN3
AN5
AM5
AL6
AK6
AJ6
AH6

IFPC_AUX_I2CW _SCL
IFPC_AUX_I2CW _SDA_N
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N

THERMDP
THERMDN

L3
J1

ROM_SCLK [28]
ROM_SI [28]
ROM_SO [28]

10K_0402_5%
1

1
2
R243 DIS@
10K_0402_5%
1
2
R244 @
40.2K_0402_1%

J2
J7
J6
J5
J3

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

+3VS_VGA

Un-pop R244-0415 Update
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

[28]
[28]
[28]
[28]
[28]

B

K3
K4

IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N

Reserve 1MB SPI ROM FOR VBIOS ROM
+3VS_VGA

20mils
1

N14M-GE2-B-AIO-A2

1

EVT@
C172
0.1U_0402_16V4Z
2
1

ROM_CS
ROM_SO

33_0402_5%
2
ROM_CS_R
2
ROM_SO_R
0_0402_5%

U8

1
2
3
4

CS#
DO
W P#
GND

2

EVT@
R246
10K_0402_5%

2

EVT@
R245
10K_0402_5%
EVT@
R247
1
1
R248
EVT@

EVT@

VCC
HOLD#
CLK
DIO

8
7
6
5

MX25L1005AMC-12G SOP

A

Compal Secret Data

Security Classification
2013/04/01

Issued Date

Deciphered Date

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

ROM_HOLD#
EVT@ R249
ROM_SCLK_R 1
1
ROM_SI_R
EVT@ R250

33_0402_5%
2
ROM_SCLK
2
ROM_SI
33_0402_5%

A

Compal Electronics, Inc.
N14M-GE2-LVDS/HDMI/DP/THM
Document Number

ZEA00 LA-A061P M/B
Sheet

Tuesday, September 24, 2013
1

22

of

59

Rev
0.3

3

AG26

C187

C186

10U_0805_10V6K
2
1

C211
@

2

Place near balls

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

C213
@

1U_0603_10V6K

1
C215
@
2

1
C216
@
2
C

C214
@

Place near balls

+IFPEF_PLLVDD

@

+3VS_VGA
@
L5
MMZ1608D301BT_0603
1
2

220mA
1

2

C225
@

R02

+1.05VS_VGA
@
L6
MBK1608221YZF_2P
1
2

+IFPE_IOVDD1 @ R266 2 10K_0402_5%

72mA
4.7U_0603_6.3V6K

+IFPE_IOVDD
N14M-GE2-B-AIO-A2

4/3 Update:
Un-stuff R253, R256, R259 and R265.

B

2

1

2

C221
@

1

2

1

2

C222
@

1
C226
@
2

1
C227
@
2

C223
@

Place near balls

AC7
AC8

IFPE_IOVDD
IFPF_IOVDD

1

DIS@

FB_CAL_TERM_GND
AB8 +IFPEF_PLLVDD1 @ R264 2 10K_0402_5%
AD6
1 @ R265 2 1K_0402_1%

2

0.1U_0402_10V6K

2

C212
@

1

0.1U_0402_10V6K

AG6 +IFPD_IOVDD 1 @ R262 2 10K_0402_5%

1

2

2

DIS@

1

1

0.1U_0402_10V6K

AG7 +IFPD_PLLVDD 1 @ R260 2 10K_0402_5%
AN2
1 @ R259 2 1K_0402_1%

1U_0402_6.3V6K

4.7U_0603_6.3V6K

0_0603_5%
@

2

4.7U_0603_6.3V6K

C220

C219
4.7U_0603_6.3V6K

2

1

+VDD33

IFPEF_PLVDD
IFPEF_RSET

C206

C205

4.7U_0805_25V6-K

C204

1U_0603_10V6K

0.1U_0402_10V6K

C210

C209

4.7U_0603_6.3V6K

2
DIS@

1

Reserve for NV DG

AF6 +IFPC_IOVDD 1 @ R257 2 10K_0402_5%

IFPD_IOVDD

C207

C185

10U_0805_10V6K
2
1

C184

10U_0805_10V6K
2
1

C183

10U_0805_10V6K
2
1

C182

C191

C190

4.7U_0603_6.3V6K

C181

4.7U_0603_6.3V6K

C180

1U_0402_6.3V6K

1U_0402_6.3V6K

C179
C189

22U_0805_6.3V6M

2

DIS@

1

1

1

1U_0402_6.3V6K

FB_CAL_PU_GND

DIS@

+1.5V to +1.5VS_VGA

1

FB_CAL_PD_VDDQ
IFPD_PLLVDD
IFPD_RSET

+3VS_VGA
@
L4
MMZ1608D301BT_0603
1
2

4.7U_0603_6.3V6K

H25

R251

2

AF7 +IFPC_PLLVDD 1 @ R255 2 10K_0402_5%
AF8
2 @ R256 1 1K_0402_1%

IFPC_IOVDD

Place near to L156

Supply from Power-0411 update.

1

2

C231
@

+5VALW

1

2

C232
@

1

2

1
C234
@
2

1
C235
@
2

C233
@

1

2

C236
@

1

1

2

1

2

C237
@

Place under GPU
DIS@
R268
100K_0402_5%

+1.05VS_VGA
@
L7
MBK1608221YZF_2P
1
2

72mA

+IFPC_IOVDD

4.7U_0603_6.3V6K

2
51.1_0402_1%

Place near GPU

+VDD33

AG8 +IFPAB_IOVDD 1 @ R254 2 10K_0402_5%
AG9

IFPC_PLLVDD
IFPC_RSET

2
DIS@

110mA

+IFPC_PLLVDD

FB_VDDQ_SENSE
FB_GND_SENSE

2

1

DIS@

2
DIS@

+3VS_VGA

Place near balls

AH8 +IFPAB_PLLVDD1 @ R252 2 10K_0402_5%
1 @ R253 2 1K_0402_1%
AJ8

IFPA_IOVDD
IFPB_IOVDD

1

+PEX_PLLVDD

J8
K8
L8
M8

VDD33_0
VDD33_1
VDD33_2
VDD33_3

2
DIS@

DIS@

+1.05VS_VGA

BLM18PG121SN1D_0603

Place near balls
1

C217

PEX_PLLVDD

2
DIS@

1

2

DIS@

1

0.1U_0402_10V6K

1
R263

C178

AG12

PEX_SVDD_3V3

1

2

1

1U_0402_6.3V6K

51.1Ohm

DIS@

1

0.1U_0402_10V6K

FB_CAL_xTERM_GND

DIS@

H27

2

DIS@
L3
2

150mA

+PEX_PLLVDD

4.7U_0603_6.3V6K

42.2Ohm

2
42.2_0402_1%

210mA

+PEX_PLLHVDD

D

DIS@

4.7U_0603_6.3V6K

FB_CAL_x_PU_GND

1
R261

DIS@

J27

1

Under GPU(below 150mils)

AH12

PEX_PLL_HVDD

DIS@

4.7U_0603_6.3V6K

40.2Ohm

2
40.2_0402_1%

DIS@

120ohms @100MHz
(ESR=0.18)

0.1U_0402_10V6K

FB_CAL_x_PD_VDDQ

F2
1
R258

DIS@

DIS@

+1.05VS_VGA

0.1U_0402_10V6K

+1.5VS_VGA

DDR3

CALIBRATION PIN

DIS@

2

2

DIS@

C228
0.1U_0402_10V6K

Follow PUN-05893

DIS@

2

1

1

+3VS_VGA

IFPAB_PLLVDD
IFPAB_RSET

F1

2

1

2

1U_0402_6.3V6K

C

1

1

DIS@

Under GPU(below 150mils)

4.7U_0603_6.3V6K

rise 1.5v system source voltage to 1.55-1.57V

2

DIS@

C218
0.1U_0402_10V6K

DIS@

1

C208

2

2

DIS@

0.1U_0402_10V6K

DIS@

C203

C202

C201

DIS@

2

1

2

DIS@

1

0.1U_0402_10V6K

DIS@

2

1

2

DIS@

1

DIS@
C224
0.1U_0402_10V6K

2

1

0.1U_0402_10V6K

DIS@

C200

C199

2

1

0.1U_0402_10V6K

DIS@

0.1uF X7R 0402 * 8
0.1U_0402_10V6K

2

1

0.1U_0402_10V6K

DIS@

C198

C197

C196

DIS@

2

1

0.1U_0402_10V6K

DIS@

2

1

0.1U_0402_10V6K

2

1

0.1U_0402_10V6K

DIS@

C195

C194

C193

DIS@

2

1

0.1U_0402_10V6K

DIS@

2

1

1U_0603_10V6K

2

1

1U_0603_10V6K

C192

1

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

Under GPU(below 150mils)
1uF X7R 0402 * 2

AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13

1

22U_0805_6.3V6M

4.7uF X7R 0402 * 2

+1.05VS_VGA

AG19
AG21
AG22
AG24
AH21
AH25

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5

1U_0402_6.3V6K

1
1
DIS@ DIS@

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43

22U_0805_6.3V6M

1
DIS@

2

C177

2

AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
V27
W27
W30
W33
Y27

1

Near GPU

2000mA

Part 5 of 7

1U_0402_6.3V6K

1
DIS@

2

C176
10U_0603_6.3V6M

C173

2

C175
10U_0603_6.3V6M

2

@

C174
10U_0603_6.3V6M

+1.5VS_VGA

10U_0603_6.3V6M

22U_0805_6.3V6M

D

1

DIS@

3.5A

C188

U6E

Near GPU

22U_0805_6.3V6M

+1.5VS_VGA

2

1U_0402_6.3V6K

4

POWER

5

1
C239
@
2

1
C240
@
2

B

C238
@

Place under GPU

2

Un-pop update-0415

+3VS to +3VS_VGA

1

1

D

G

1

S

2

1 2

2
1

2

DIS@
DIS@ Q12
S
2N7002_SOT23

R275
470_0603_5%
DIS@

D

2
C250

2
G

DIS@

1

2

3

S
0.1U_0603_25V7K

Compal Secret Data

Security Classification
Issued Date

2
G

2013/04/01

2014/04/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

S

Date:

5

1

4

3

2

0.1U_0402_10V6K

DGPU_PWROK#

2
G
S
DIS@
R281
100K_0402_5%

2

3

1
1

1

100K_0402_5%
DIS@
Q11
v0.3 update
2N7002_SOT23

2

2
G

DIS@
C251

@

0_0402_5%
DIS@
Q13
2N7002KW_SOT323-3

1

D

3
DIS@
R276

2
DGPU_PWR_EN

D

3

[15,43]

1

v0.3 update

R278
2

DIS@
C245
10U_0603_6.3V6M

C249

2

1

1

D

2

R283
0_0402_5%
2

3

@
DGPU_PWROK#

2

1U_0603_10V6K

v0.3 update
DIS@
Q14
2N7002KW_SOT323-3

JUMP_43X79

DGPU_PWR_EN#
R277 DIS@
22_0603_5%

1

10U_0805_10V6K

v0.3 update

DIS@
C248

1

DIS@
C247

2

4

2

2

DIS@
AO4354_SOIC-8
R279
20K_0402_1% DIS@
R282
DIS@
2K_0402_1%
1
2

1
2
3

2

2

DIS@ Q9
AO3413L_SOT23-3
DIS@
R274
100K_0402_5%

1

8
7
6
5

@

1

+5VALW

1

2

1
C246
10U_0805_10V6K

1

1

+3VS_VGA

J2

1

JUMP_43X118
DIS@
Q10

+5VALW

A

@

2

+3VS

0.1U_0402_10V6K

2

S

DIS@
Q8
2N7002_SOT23

R273
100K_0402_5%
@

+1.05VS_VGA
J3

D

2
G

1

+1.05VS_VPCH

1

@ R272
0_0402_5%
2

1

1

DGPU_PWROK

3

DGPU_PWROK#

[17,52,53]

R280 DIS@
1DGPU_PWR_EN#

A

10K_0402_5%

Compal Electronics, Inc.
N14M-GE2-POWER
Document Number

Rev
0.3

ZEA00 LA-A061P M/B
Tuesday, September 24, 2013

Sheet
1

23

of

59

5

4

3

2

1

U6F

C

B

A

GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_OPT
GND_OPT

D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W 13
W 15
W 17
W 18
W 20
W 22
W 28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W 32

Part 7 of 7

AA12
AA14
AA16
AA19
AA21
AA23
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23
M12
M14
M16
M19
M21
M23
N13
N15
N17
N18
N20
N22
P12
P14
P16
P19
P21
P23
R13
R15
R17
R18
R20
R22
T12
T14
T16
T19
T21
T23
U13
U15
U17
U18
U20
U22
V13
V15

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55

XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16

XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30
XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38

V17
V18
V20
V22
W 12
W 14
W 16
W 19
W 21
W 23
Y13
Y15
Y17
Y18
Y20
Y22

D

U1
U2
U3
U4
U5
U6
U7
U8
V1
V2
V3
V4
V5
V6
V7
V8

C

W2
W3
W4
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8

B

0403 Update

A

Issued Date

Compal Secret Data
2013/04/01

Deciphered Date

2014/04/01

Title

Date:

4

XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8

XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71

N14M-GE2-B-AIO-A2
DIS@

Security Classification

N14M-GE2-B-AIO-A2
DIS@

+VGA_CORE

U6G

+VGA_CORE

POWER

D

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99

GND

Part 6 of 7

A2
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
A33
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AA13
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AA15
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7

3

2

Compal Electronics, Inc.
N14M-GE2-VGA CORE, GND
Document Number

Rev
0.3

ZEA00 LA-A061P M/B
Tuesday, September 24, 2013

Sheet
1

24

of

59

5

[26,27]

FBA_D[0..63]

4

3

FBA_MA[14..0]

FBA_D[0..63]

FBA_BA[2..0]

2

1

[26,27]
[26,27]

U6C
U6B

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBA_WE#

FBA_CAS#
FBA_CS0#_H

[26,27]

0403 Update

FBA_CAS# [26,27]
FBA_CS0#_H
[27]

FBA_ODT_H
FBA_CKE_H
FBA_MA13
FBA_MA8
FBA_MA6
FBA_MA11
FBA_MA5
FBA_MA3
FBA_BA2
FBA_BA1
FBA_MA12
FBA_MA10
FBA_RAS#

FBA_ODT_H
FBA_CKE_H

FBA_RAS#

R32
AC32

R28
AC28

[26,27]

[27]
[27]

[26,27]

+1.5VS_VGA

R285
R287

1
1

@
@

2 60.4_0402_1%
2 60.4_0402_1%

can be unstuff by default
R30
R31
AB31
AC31

FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#

FBA_CLK0 [26]
FBA_CLK0# [26]
FBA_CLK1 [27]
FBA_CLK1# [27]

K31
L30
H34
J34
AG30
AG31
AJ34
AK34

FB_CLAMP

FB_DLL_AVDD

E1

+FB_PLLAVDD

Place close to BGA

J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33

200mA

E11
E3
A3
C9
F23
F27
C30
A24

1
2 +FB_PLLAVDD
DIS@ L8
BLM18PG330SN1D_0603

v0.3 update

FB_CLAMP

R02
R288 DIS@
2

D10
D5
C3
B9
E23
E28
B30
A23

10K_0402_5%
1
+FB_PLLAVDD

K27

C252
1

0.1U_0402_10V6K
2

Place close to ball

FB_VREF

U27

H26

DIS@

1

2

DIS@

Place close to ball

1

2

DIS@

D9
E4
B2
A9
D22
D28
A30
B23

+FB_PLLAVDD

1

2

[26,27] FBA_DQM[7..0]
[26,27] FBA_DQS[7..0]
[26,27] FBA_DQS#[7..0]

FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7

FBB_CMD_RFU0
FBB_CMD_RFU1

D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17

D

Mode D - Mirror Mode Mapping
DATA Bus
Address

FBB_CLK0
FBB_CLK0_N
FBB_CLK1
FBB_CLK1_N

FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N

FBB_WCKB01
FBB_WCKB01_N
FBB_WCKB23
FBB_WCKB23_N
FBB_WCKB45
FBB_WCKB45_N
FBB_WCKB67
FBB_WCKB67_N

FBB_PLL_AVDD

G14
G20

R284 1
R286 1

@
@

2 60.4_0402_1%
2 60.4_0402_1%

can be unstuff by default
D12
E12
E20
F20

F8
E8
A5
A6
D24
D25
B27
C27

D6
D7
C6
B6
F26
E26
A26
A27

C

FBx_CMD3

CKE_L

FBx_CMD4

A14

A14

FBx_CMD5

RST

RST

FBx_CMD6

A9

A9

FBx_CMD7

A7

A7

FBx_CMD8

A2

A2

FBx_CMD9

A0

A0

FBx_CMD10

A4

A4

FBx_CMD11

A1

A1

FBx_CMD12

BA0

BA0

FBx_CMD13

WE#

WE#

FBx_CMD14

A15

A15

FBx_CMD15

CAS#

CAS#

FBx_CMD16

CS0#_H

FBx_CMD17
FBx_CMD18

ODT_H

FBx_CMD19

H17

+FB_PLLAVDD

1

2
DIS@

Place close to ball

DIS@

B

CKE_H

FBx_CMD20

A13

A13

FBx_CMD21

A8

A8

FBx_CMD22

A6

A6

FBx_CMD23

A11

A11

FBx_CMD24

A5

A5

FBx_CMD25

A3

A3

FBx_CMD26

BA2

BA2

FBx_CMD27

BA1

BA1

FBx_CMD28

A12

A12

FBx_CMD29

A10

A10

FBx_CMD30

RAS#

RAS#

Must connect to power when partition B unused!

A

30ohms (ESR=0.01) Bead
P/N;SM010007W00

Compal Secret Data

Security Classification
Issued Date

2013/04/01

2014/04/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

ODT_L

FBx_CMD2

FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7

N14M-GE2-B-AIO-A2
DIS@

CS0#_L

FBx_CMD1

C12
C20
+1.5VS_VGA

FBB_DEBUG0
FBB_DEBUG1

32..63

0..31

FBx_CMD0

Place close to BGA

N14M-GE2-B-AIO-A2
DIS@

A

FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31

C253

FBA_RST#

[26]
[26]

+1.05VS_VGA

FBA_WCKB01
FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N

FBA_PLL_AVDD

M30
FBA_DQS#0
H30
FBA_DQS#1
E34
FBA_DQS#2
M34
FBA_DQS#3
FBA_DQS#4 AF30
FBA_DQS#5 AK31
FBA_DQS#6 AM34
FBA_DQS#7 AF32

FBA_ODT_L
FBA_CKE_L

FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63

0.1U_0402_10V6K

FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N

FBA_ODT_L
FBA_CKE_L
FBA_MA14
FBA_RST#
FBA_MA9
FBA_MA7
FBA_MA2
FBA_MA0
FBA_MA4
FBA_MA1
FBA_BA0
FBA_WE#

[26]

C256

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N

FBA_CS0#_L

C255

M31
G31
E33
M33
AE31
AK30
AN33
AF33

FBA_DEBUG0
FBA_DEBUG1

FBA_CS0#_L

22U_0805_6.3V6M

FBA_DQS0
FBA_DQS1
FBA_DQS2
FBA_DQS3
FBA_DQS4
FBA_DQS5
FBA_DQS6
FBA_DQS7

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_CMD_RFU0
FBA_CMD_RFU1

U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31

C254

P30
F31
F34
M32
AD31
AL29
AM32
AF34

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

1U_0402_6.3V6K

B

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

0.1U_0402_10V6K

C

L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33

MEMORY INTERFACE
A

D

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

MEMORY INTERFACE B

Part 3 of 7

G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26

Part 2 of 7

4

3

2

Compal Electronics, Inc.
N14M-GE2-MEM Interface
Document Number

Rev
0.3

ZEA00 LA-A061P M/B
Tuesday, September 24, 2013

Sheet
1

25

of

59

5

4

3

2

1

Memory Partition A - Lower 32 bits
FBA_D[0..63]
+1.5VS_VGA

FBA_MA[14..0]

1

FBA_BA[2..0]

DIS@ R289

U70
+FBA_VREF_CA0
+FBA_VREF_DQ0

1.1K_0402_1%
2

0.01U_0402_25V7K

1

+FBA_VREF_CA0

DIS@ R290

2

1.1K_0402_1%

1

+FBA_VREF_CA0

FBA_MA0
FBA_MA1
FBA_MA2
FBA_MA3
FBA_MA4
FBA_MA5
FBA_MA6
FBA_MA7
FBA_MA8
FBA_MA9
FBA_MA10
FBA_MA11
FBA_MA12
FBA_MA13
FBA_MA14

C257

D

2

DIS@

1

+1.5VS_VGA

DIS@ R640

0403 Update

M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

[25,27]

U71

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

FBA_D4
FBA_D1
FBA_D6
FBA_D2
FBA_D7
FBA_D0
FBA_D5
FBA_D3

D7
C3
C8
C2
A7
A2
B8
A3

FBA_D31
FBA_D25
FBA_D28
FBA_D24
FBA_D29
FBA_D26
FBA_D30
FBA_D27

M8
H1

+FBA_VREF_CA0
+FBA_VREF_DQ0

Group3 (BOT)

+1.5VS_VGA

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

FBA_MA0
FBA_MA1
FBA_MA2
FBA_MA3
FBA_MA4
FBA_MA5
FBA_MA6
FBA_MA7
FBA_MA8
FBA_MA9
FBA_MA10
FBA_MA11
FBA_MA12
FBA_MA13
FBA_MA14

Group0 (IN3)

VREFCA
VREFDQ

0403 Update

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

FBA_D19
FBA_D20
FBA_D17
FBA_D22
FBA_D16
FBA_D23
FBA_D18
FBA_D21

D7
C3
C8
C2
A7
A2
B8
A3

FBA_D10
FBA_D15
FBA_D8
FBA_D13
FBA_D9
FBA_D12
FBA_D11
FBA_D14

Group1 (TOP)

T2
L8

1

B

DIS@
R295
243_0402_1%

J1
L1
J9
L9

ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

FBA_DQS#2 G3
FBA_DQS#1 B7

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

2

FBA_CKE_L

2
DIS@

1

2

C271

C270

C269

2
DIS@

1

@

1U_0402_6.3V6K

2
DIS@

1

1

2
DIS@

2
DIS@

2
DIS@

2013/04/01

1

2

@

1

2

@

1

2

@

1

2
DIS@

1

2

@

1

2

@

Deciphered Date

2014/04/01

Title

Date:

4

3

RST

RST

FBx_CMD6

A9

A9

FBx_CMD7

A7

A7

FBx_CMD8

A2

A2

C

FBx_CMD9

A0

A0

FBx_CMD10

A4

A4

FBx_CMD11

A1

A1

FBx_CMD12

BA0

BA0

FBx_CMD13

WE#

WE#

FBx_CMD14

A15

A15

FBx_CMD15

CAS#

CAS#
CS0#_H
ODT_H

FBx_CMD19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

A14

FBx_CMD5

FBx_CMD18

B1
B9
D1
D8
E2
E8
F9
G1
G9

1

A14

FBx_CMD17

Compal Secret Data

Security Classification
Issued Date

1

CKE_L

FBx_CMD4

FBx_CMD16

1

DIS@ R292
10K_0402_5%

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DIS@
R293
10K_0402_5%

U71 SIDE
0.1U_0402_10V6K

2
DIS@

1

C268
1U_0402_6.3V6K

2
DIS@

1

C267
1U_0402_6.3V6K

2
DIS@

1

C266
1U_0402_6.3V6K

2
DIS@

1

C265
1U_0402_6.3V6K

@

1

C264
0.1U_0402_10V6K

2

0.1U_0402_10V6K

2
DIS@

1

C263

C262

C261

2
DIS@

1

1U_0402_6.3V6K

2
DIS@

1

1U_0402_6.3V6K

C260

1

0.1U_0402_10V6K

+1.5VS_VGA

1U_0402_6.3V6K

2
DIS@

1U_0402_6.3V6K

C259

C258

2
DIS@

1

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

FBA_ODT_L

96-BALL
SDRAM DDR3
K4W2G1646E-BC1A _FBGA96
X76@

U70 SIDE
0.1U_0402_10V6K

0.1U_0402_10V6K

A

1

ZQ/ZQ0

J1
L1
J9
L9

96-BALL
SDRAM DDR3
K4W2G1646E-BC1A _FBGA96
X76@
+1.5VS_VGA

RESET

L8
DIS@
R296
243_0402_1%

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

T2

FBA_RST#

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

1

DIS@
R294
10K_0402_5%

RESET

DML
DMU

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODT_L

FBx_CMD3

2

1

CKE_H

FBx_CMD20

A13

A13

FBx_CMD21

A8

A8

FBx_CMD22

A6

A6

FBx_CMD23

A11

A11

FBx_CMD24

A5

A5

FBx_CMD25

A3

A3

FBx_CMD26

BA2

BA2

FBx_CMD27

BA1

BA1

FBx_CMD28

A12

A12

FBx_CMD29

A10

A10

FBx_CMD30

RAS#

RAS#

B

C281

FBA_RST#

FBA_RST#

DQSL
DQSU

E7
D3

FBA_DQM2
FBA_DQM1

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

C280
1U_0402_6.3V6K

[25,27]

DQSL
DQSU

F3
C7

FBA_DQS2
FBA_DQS1

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

ODT/ODT0
CS/CS0
RAS
CAS
WE

C279
1U_0402_6.3V6K

FBA_DQS#0 G3
FBA_DQS#3 B7

DML
DMU

K1
L2
J3
K3
L3

1

E7
D3

DQSL
DQSU

FBA_ODT_L
FBA_CS0#_L
FBA_RAS#
FBA_CAS#
FBA_WE#

C278
1U_0402_6.3V6K

FBA_DQM0
FBA_DQM3

FBA_CLK0#

F3
C7

A1
A8
C1
C9
D2
E9
F1
H2
H9

32..63

CS0#_L

FBx_CMD0

C277
1U_0402_6.3V6K

1

FBA_DQS0
FBA_DQS3

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

[25,27]

0..31

FBx_CMD2

C276
0.1U_0402_10V6K

DIS@
R291
160_0402_1%

ODT/ODT0
CS/CS0
RAS
CAS
WE

FBA_DQS#[7..0]

FBx_CMD1

0.1U_0402_10V6K

K1
L2
J3
K3
L3

CK
CK
CKE/CKE0

C275

FBA_ODT_L
FBA_CS0#_L
FBA_RAS#
FBA_CAS#
FBA_WE#

J7
FBA_CLK0
FBA_CLK0# K7
FBA_CKE_L K9

[25,27]

DATA Bus
Address

B2
D9
G7
K2
K8
N1
N9
R1
R9

C274

FBA_CLK0

FBA_ODT_L
FBA_CS0#_L
FBA_RAS#
FBA_CAS#
FBA_WE#

CK
CK
CKE/CKE0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

1U_0402_6.3V6K

J7
K7
K9

BA0
BA1
BA2

C273

[25]
[25]
[25,27]
[25,27]
[25,27]

0403 Update

2

FBA_CLK0
FBA_CLK0#
FBA_CKE_L

M2
N8
M3

1U_0402_6.3V6K

DIS@

FBA_CLK0
FBA_CLK0#
FBA_CKE_L

FBA_BA0
FBA_BA1
FBA_BA2

C272

[25]
[25]
[25]

2

B2
D9
G7
K2
K8
N1
N9
R1
R9

1U_0402_6.3V6K

2

C

1

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

1

1.1K_0402_1%

C2076

0.01U_0402_25V7K

DIS@ R641

+FBA_VREF_DQ0

BA0
BA1
BA2

[25,27]

FBA_DQS[7..0]

CMD mapping mod Mode D

+1.5VS_VGA

2

2
1

+FBA_VREF_DQ0

M2
N8
M3

FBA_DQM[7..0]

D

Group2 (IN1)

1.1K_0402_1%
FBA_BA0
FBA_BA1
FBA_BA2

[25,27]

[25,27]

2
DIS@

A

Compal Electronics, Inc.
N14M-GE2-VRAM A Lower
Document Number

ZEA00 LA-A061P M/B
Tuesday, September 24, 2013

Sheet
1

26

of

59

Rev
0.3

5

4

3

2

1

Memory Partition A - Upper 32 bits
FBA_D[0..63]

1

+1.5VS_VGA

U72

FBA_MA[14..0]

U73

DIS@ R297
+FBA_VREF_CA1
+FBA_VREF_DQ1

2

1.1K_0402_1%
+FBA_VREF_CA1

DIS@ R298

2

1.1K_0402_1%

+FBA_VREF_CA1

C282

0.01U_0402_25V7K

1

D

1

2

DIS@

1

+1.5VS_VGA

FBA_MA0
FBA_MA1
FBA_MA2
FBA_MA3
FBA_MA4
FBA_MA5
FBA_MA6
FBA_MA7
FBA_MA8
FBA_MA9
FBA_MA10
FBA_MA11
FBA_MA12
FBA_MA13
FBA_MA14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

FBA_BA0
FBA_BA1
FBA_BA2

M2
N8
M3

0403 Update

DIS@ R642

2

1.1K_0402_1%

DIS@ R643

2

1.1K_0402_1%

C2077

0.01U_0402_25V7K

1

+FBA_VREF_DQ1
1

+FBA_VREF_DQ1

[25]
[25]
[25]

2

FBA_CLK1
FBA_CLK1#
FBA_CKE_H

FBA_CLK1
FBA_CLK1#
FBA_CKE_H

M8
H1

J7
K7
K9

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

FBA_D36
FBA_D33
FBA_D38
FBA_D34
FBA_D37
FBA_D32
FBA_D39
FBA_D35

D7
C3
C8
C2
A7
A2
B8
A3

FBA_D45
FBA_D42
FBA_D46
FBA_D41
FBA_D47
FBA_D43
FBA_D44
FBA_D40

+FBA_VREF_CA1
+FBA_VREF_DQ1

Group4 (IN1)

Group5 (TOP)

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

FBA_MA0
FBA_MA1
FBA_MA2
FBA_MA3
FBA_MA4
FBA_MA5
FBA_MA6
FBA_MA7
FBA_MA8
FBA_MA9
FBA_MA10
FBA_MA11
FBA_MA12
FBA_MA13
FBA_MA14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

FBA_BA0
FBA_BA1
FBA_BA2

M2
N8
M3

0403 Update

+1.5VS_VGA
B2
D9
G7
K2
K8
N1
N9
R1
R9

M8
H1

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

FBA_D63
FBA_D59
FBA_D61
FBA_D56
FBA_D60
FBA_D58
FBA_D62
FBA_D57

D7
C3
C8
C2
A7
A2
B8
A3

FBA_D52
FBA_D51
FBA_D54
FBA_D50
FBA_D53
FBA_D48
FBA_D55
FBA_D49

Group7 (IN3)

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

FBA_CLK1#
FBA_DQS#4 G3
FBA_DQS#5 B7

DQSL
DQSU

FBA_CKE_H
[25,26]

FBA_ODT_H

FBA_RST#

FBA_RST#

T2

1
DIS@ R302
243_0402_1%

J1
L1
J9
L9

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

FBA_DQM7
FBA_DQM6

E7
D3

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

2
DIS@

2

@

1

2

C300

C299

1

1U_0402_6.3V6K

2
DIS@

C298

C297

C296
@

1

1U_0402_6.3V6K

2

1

1U_0402_6.3V6K

2
DIS@

1

1U_0402_6.3V6K

C295

C294

2
DIS@

1

@

1

2

@

2

[25,26]

0..31

32..63

CS0#_L
ODT_L

FBx_CMD3

CKE_L

FBx_CMD4

A14

A14

FBx_CMD5

RST

RST

FBx_CMD6

A9

A9

FBx_CMD7

A7

A7

FBx_CMD8

A2

A2

FBx_CMD9

A0

A0

FBx_CMD10

A4

A4

FBx_CMD11

A1

A1

FBx_CMD12

BA0

BA0

FBx_CMD13

WE#

WE#

FBx_CMD14

A15

A15

FBx_CMD15

CAS#

C

CAS#
CS0#_H

FBx_CMD17
FBx_CMD18

ODT_H

FBx_CMD19

B1
B9
D1
D8
E2
E8
F9
G1
G9

1

FBA_DQS#[7..0]

FBx_CMD16

U73 SIDE
0.1U_0402_10V6K

2
DIS@

1

0.1U_0402_10V6K

2
DIS@

1

C293
1U_0402_6.3V6K

2
DIS@

1

C292
1U_0402_6.3V6K

2
DIS@

1

C291
1U_0402_6.3V6K

2
DIS@

1

C290
1U_0402_6.3V6K

2
DIS@

1

C289
0.1U_0402_10V6K

C288

C287

2
DIS@

1

0.1U_0402_10V6K

2
DIS@

1

1U_0402_6.3V6K

C286

1

1U_0402_6.3V6K

2
DIS@

1U_0402_6.3V6K

1

ZQ/ZQ0

A1
A8
C1
C9
D2
E9
F1
H2
H9

96-BALL
SDRAM DDR3
K4W2G1646E-BC1A _FBGA96
X76@
+1.5VS_VGA

C285

C284

2
DIS@

1U_0402_6.3V6K

2
DIS@

1

RESET

J1
L1
J9
L9

DIS@ R303
243_0402_1%

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

L8

U72 SIDE
0.1U_0402_10V6K

C283

0.1U_0402_10V6K

1

DML
DMU

T2

FBA_RST#

96-BALL
SDRAM DDR3
K4W2G1646E-BC1A _FBGA96
X76@
+1.5VS_VGA

DQSL
DQSU

FBA_DQS#7 G3
FBA_DQS#6 B7

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

1

DIS@
R301
10K_0402_5%

2

2

DIS@
R300
10K_0402_5%

1

L8

F3
C7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

@

1

2
DIS@

1

2
DIS@

1

2

@

1

2

C306

DML
DMU

FBA_DQS7
FBA_DQS6

ODT/ODT0
CS/CS0
RAS
CAS
WE

Address

FBx_CMD2

C305
1U_0402_6.3V6K

E7
D3

K1
L2
J3
K3
L3

[25,26]

FBx_CMD1

C304
1U_0402_6.3V6K

FBA_DQM4
FBA_DQM5

DQSL
DQSU

FBA_ODT_H
FBA_CS0#_H
FBA_RAS#
FBA_CAS#
FBA_WE#

[25,26]

FBA_DQS[7..0]

D

FBx_CMD0

C303
1U_0402_6.3V6K

F3
C7

A1
A8
C1
C9
D2
E9
F1
H2
H9

FBA_DQM[7..0]

DATA Bus
Group6 (BOT)

B2
D9
G7
K2
K8
N1
N9
R1
R9

C302
1U_0402_6.3V6K

FBA_DQS4
FBA_DQS5

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

C301
0.1U_0402_10V6K

1

DIS@
R299
160_0402_1%

ODT/ODT0
CS/CS0
RAS
CAS
WE

0.1U_0402_10V6K

2

FBA_CLK1

K1
L2
J3
K3
L3

1

0403 Update

FBA_ODT_H
FBA_CS0#_H
FBA_RAS#
FBA_CAS#
FBA_WE#

FBA_ODT_H
FBA_CS0#_H
FBA_RAS#
FBA_CAS#
FBA_WE#

2

[25]
[25]
[25,26]
[25,26]
[25,26]

[25,26]

CMD mapping mod Mode D

+1.5VS_VGA

BA0
BA1
BA2

J7
FBA_CLK1
FBA_CLK1# K7
FBA_CKE_H K9

E3
F7
F2
F8
H3
H8
G2
H7

[25,26]

FBA_BA[2..0]

DIS@

C

B

E3
F7
F2
F8
H3
H8
G2
H7

[25,26]

CKE_H

FBx_CMD20

A13

A13

FBx_CMD21

A8

A8

FBx_CMD22

A6

A6

FBx_CMD23

A11

A11

FBx_CMD24

A5

A5

FBx_CMD25

A3

A3

FBx_CMD26

BA2

BA2

FBx_CMD27

BA1

BA1

FBx_CMD28

A12

A12

FBx_CMD29

A10

A10

FBx_CMD30

RAS#

RAS#

B

@

A

A

Compal Secret Data

Security Classification
Issued Date

2013/04/01

Deciphered Date

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
N14M-GE2-VRAM A Upper
Document Number

ZEA00 LA-A061P M/B
Tuesday, September 24, 2013

Sheet
1

27

of

59

Rev
0.3

5

4

3

2

1

+3VS_VGA

2

2

R323 @
10K_0402_1%

1

R322
10K_0402_1%
X76@

1

1

R321
10K_0402_1%
X76@

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

2

2
R327
10K_0402_1%
X76@

R328 DIS@
10K_0402_1%

1

R326
10K_0402_1%
X76@

1

R325
10K_0402_1%
X76@

1

1

X76 for VRAM Config

R324
10K_0402_1%
X76@

2

D

1

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

2

[22]
[22]
[22]
[22]
[22]

2

D

R320
10K_0402_1%
X76@

1

1

R319
10K_0402_1%
X76@

2

2

2

[PUN-06026-001]

[VRAM Config-RVL-06366-001]
GPU

Frenq.

Memory Size

+3VS_VGA

N14M-GE2

900 MHz

1

N14M-GE2

R334 DIS@
10K_0402_1%

900 MHz

256M* 16* 4
2GB

strap2

strap1

0

1

1

strap0
0

R327
PD 10K

R321
PU 10K

R320
PU 10K

R324
PD 10K

0

1

0

1

R327
PD 10K

R321
PU 10K

R325
PD 10K

R319
PU 10K

0

0

0

1

Micron (0x1)
MT41J128M16JT-107G:K
SA00005SM30

R327
PD 10K

R326
PD 10K

R325
PD 10K

R319
PU 10K

1

1

0

1

Micron (0xD)
MT41K256M16HA-107G:E
SA000065D20

R322
PU 10K

R321
PU 10K

R325
PD 10K

R319
PU 10K

1

0

1

1

Samsung (0xB)
K4W4G1646B-HC11
SA000068R10

R322
PU 10K

R326
PD 10K

R320
PU 10K

R319
PU 10K

0

1

0

0

Hynix (0x4)
H5TC4G63AFR-11C
SA00006E800

R327
PD 10K

R321
PU 10K

R325
PD 10K

R324
PD 10K

1

R333 DIS@
10K_0402_1%

1

1

R332 DIS@
10K_0402_1%

R331 @
4.99K_0402_1%

strap3

Samsung (0x5)
K4W2G1646E-BC11
SA00005SH00

2

1

R330 @
10K_0402_1%

2

2

[22] ROM_SI
[22] ROM_SO
[22] ROM_SCLK

ROM_SI
ROM_SO
ROM_SCLK

1

R329 @
10K_0402_1%

128M* 16* 4
1GB

2

2

2

C

Memory Config
Hynix (0x6)
H5TQ2G63BFR-11C
SA00003YO10

C

B

B

A

A

Compal Secret Data

Security Classification
Issued Date

2013/04/01

Deciphered Date

2014/04/01

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

N14M-GE2_MISC
ZEA00 LA-A061P M/B

Tuesday, September 24, 2013

Sheet
1

28

of

59

Rev
0.3

5

4

3

2

1

Power Consumption:
+3VS

Pin 22 (PVCC) < 50 mA
Pin 18 (SWR_VDD) < 200mA (layout trace > 40 mil)

+3VS_RTD

1

2

Pin5 (DPV33) < 20mA

@ R337
0_0805_5%

D

1

2

D

Pin 17 (SWR_LX) < 600mA (layout trace > 60 mil)

C358
1U_0402_6.3V6K

Pin 15 (SWR_VCCK) < 100mA (layout trace > 60 mil)
Pin 43 (VCCK) < 50mA
Pin 11 (DPV12) < 100mA
SE070104Z80

v0.2 update

S CER CAP .1U 16V Z Y5V 0402
S CER CAP .1U 16V Z Y5V 0402

Vendor suggest to reserve for FW/EDID debug
+3VS_DVCCTL
+3VS_DVCCTL

v0.2 update

@ C363

EVT@
U19

+3VS_AVCCTL
EESCL
EESDA

2

2

eDP portD

[5]
[5]

CPU_EDP_TXP1_C
CPU_EDP_TXN1_C

PCH_DDPD_HPD

PCH_DDPD_HPD

+1.2VS_SW R

C370

2

9
10
4
3

[5]

EDP_DISP_UTIL

PCH

[15]

PCH_EDP_PW M

1
R344

2
LVDS_HPD_R
1K_0402_5%

@ R345 1

1

@ R347 1

2 0_0402_5%
1

2

MODE_CFG1
MODE_CFG0

To EC

EC_SMB_CK1
EC_SMB_DA1

@ R351
1
1
@ R352

TXE0+
TXE0-

AUX-CH_P
AUX-CH_N

TXE1+
TXE1TXE2+
TXE2-

DP_HPD

TXE3+
TXE321
2
12

12K_0402_1%

EC_SMB_CK1
EC_SMB_DA1

LANE1P
LANE1N

TXEC+
TXEC-

2 0_0402_5%

R349

[32,43]
[32,43]

LANE0P
LANE0N

0_0402_5%
2
EC_SMB_CK1_R
2
EC_SMB_DA1_R
0_0402_5%

48
47
13
14

PWMIN
TESTMODE
DP_REXT

MODE_CFG1
MODE_CFG0
CIICSCL1
CIICSDA1

MIICSCL1
MIICSDA1

OTHERS

2

1 C372

CPU

0.1U_0402_16V4Z

2

1

C371
10U_0603_6.3V6M

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

C369
1

CPU_EDP_TXP1_C
CPU_EDP_TXN1_C

PCH_DDPD_AUXP_C
PCH_DDPD_AUXN_C

PCH_DDPD_AUXP_C
PCH_DDPD_AUXN_C
[15]

B

CPU_EDP_TXP0_C
CPU_EDP_TXN0_C

7
8

TXO3+
TXO3-

DP_V12

DP

[15]
[15]

[5]
[5]

CPU_EDP_TXP0_C
CPU_EDP_TXN0_C

VCCK

TXO3+
TXO3-

TXO3+ [32]
TXO3- [32]

25
26

TXEC+
TXEC-

TXEC+ [32]
TXEC- [32]

31
32

TXE0+
TXE0-

TXE0+ [32]
TXE0- [32]

29
30

TXE1+
TXE1-

TXE1+ [32]
TXE1- [32]

27
28

TXE2+
TXE2-

TXE2+ [32]
TXE2- [32]

23
24

TXE3+
TXE3-

TXE3+ [32]
TXE3- [32]

1

33
34

1
TXO2+ [32]
TXO2- [32]

@ R341
4.7K_0402_5%

R343
4.7K_0402_5%
MODE_CFG0

MODE_CFG1

LVDS

@ R346
4.7K_0402_5%

R342
4.7K_0402_5%

+3VS_DVCCTL

+3VS_DVCCTL

R637
4.7K_0402_5%

R636
4.7K_0402_5%
EESCL

EESDA

1

2

TXO2+
TXO2-

TXO2+
TXO2-

1

0.1U_0402_16V4Z

11

SWR_VCCK

TXO1+ [32]
TXO1- [32]

37
38

+3VS_DVCCTL

PANEL_VCC
PWMOUT
BL_EN

DP_GND
GND
PAD

46
45

EESCL
EESDA

20
19
44

S_ENVDD
S_BKOFF#

@ R638
4.7K_0402_5%
S_ENVDD

[32,43]
S_INVT_PW M

S_BKOFF#

B

2

43

TXO1+
TXO1-

+3VS_DVCCTL

1

1 C368

0.1U_0402_16V4Z

10U_0603_6.3V6M

2

1 C367

SWR_LX

TXO1+
TXO1-

1

15

39
40

EVT Debug Only, un-pop for DVT

2

17

TXO0+ [32]
TXO0- [32]

1

+SW _LX

TXO0+
TXO0-

TXO0+
TXO0-

2

2 0_0603_5%

DP_V33

TXOC+ [32]
TXOC- [32]

41
42

@ R639
4.7K_0402_5%

2

1

SWR_VDD

PWR

@ R340

5

TXOC+
TXOC-

2

+1.2VS_SW R

35
36

1

18

TAI_HCB2012KF-221T30
L10
1
2

TXOC+
TXOC-

PVCC

C

2

22

1
2
3
4

Addr:A8 (1010 100x)

RTD2136R

TAI_HCB2012KF-221T30
L9
1
2

A0
A1
A2
GND

CAT24C02W I-GT3_SO8

U20

+3VS_RTD

VCC
WP
SCL
SDA

2

+3VS_DVCCTL

+3VS_AVCCTL

1 C366

8
7
6
5

2

1

LVDS

C365
22U_0805_6.3V6M

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

2

1 C364

1

0.1U_0402_16V4Z

C

10U_0603_6.3V6M

2

1 C362

GND

1 C361

[32]

[32,43]

6

Pin 47

16
49

0

RTD2136R-CG_QFN48_6x6

0

X

1

ROM

1
EP Mode

Pin 48
EEPROM

1

+3VS_RTD

@ R353
1K_0402_5%

A

2

A

PreMP

PCH_DDPD_HPD

Compal Secret Data

Security Classification
2013/04/01

Issued Date

Deciphered Date

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
LVDS Converter RTD2136S
Document Number

Rev
0.3

ZEA00 LA-A061P M/B
Tuesday, September 24, 2013

Sheet
1

29

of

59

A

B

C

D

E

F

G

H

1

1

HDMIOUT_TX2+_C
HDMIOUT_TX2-_C

[31]
[31]

HDMIOUT_TX1+_C
HDMIOUT_TX1-_C

[31]
[31]

HDMIOUT_CLK+_C
HDMIOUT_CLK-_C
HDMIOUT_TX0+_C
HDMIOUT_TX0-_C

[31]
[31]
[31]
[31]

UMA & DIS for Optimus

PCH_HDMIOUT_TX1+
PCH_HDMIOUT_TX1-

[5]
[5]

PCH_HDMIOUT_CLK+
PCH_HDMIOUT_CLK-

[5]
[5]

PCH_HDMIOUT_TX0+
PCH_HDMIOUT_TX0-

HDMIO@
HDMIO@

C373
C374

1
1

2 0.1U_0402_10V6K HDMIOUT_TX2+_C
2 0.1U_0402_10V6K HDMIOUT_TX2-_C

R607 1 HDMIO@2 470_0402_5%
R608 1 HDMIO@2 470_0402_5%

PCH_HDMIOUT_TX1+
PCH_HDMIOUT_TX1-

HDMIO@
HDMIO@

C375
C376

1
1

2 0.1U_0402_10V6K HDMIOUT_TX1+_C
2 0.1U_0402_10V6K HDMIOUT_TX1-_C

R609 1 HDMIO@2 470_0402_5%
R610 1 HDMIO@2 470_0402_5%

PCH_HDMIOUT_CLK+
PCH_HDMIOUT_CLK-

HDMIO@
HDMIO@

C377
C378

1
1

2 0.1U_0402_10V6K HDMIOUT_CLK+_C
2 0.1U_0402_10V6K HDMIOUT_CLK-_C

R611 1 HDMIO@2 470_0402_5%
R612 1 HDMIO@2 470_0402_5%

PCH_HDMIOUT_TX0+
PCH_HDMIOUT_TX0-

HDMIO@
HDMIO@

C379
C380

1
1

2 0.1U_0402_10V6K HDMIOUT_TX0+_C
2 0.1U_0402_10V6K HDMIOUT_TX0-_C

R613 1 HDMIO@2 470_0402_5%
R614 1 HDMIO@2 470_0402_5%

2

Close to HDMI Connector
+3VS

1

[5]
[5]

PCH_HDMIOUT_TX2+
PCH_HDMIOUT_TX2-

D

3

PCH_HDMIOUT_TX2+
PCH_HDMIOUT_TX2-

HDMI_Term_CON

[5]
[5]

S

2
G

2

HDMIO@
Q58
2N7002K_SOT23-3

Close to HDMI Connector,<1000mils Length

+3VS

2.2k 3VS Pull-High on PCH side

2.2k 5V Pull-High on Connector side
3

2

3

PCH_HDMIOUT_DATA

PCH_HDMIOUT_DATA

1

PCH_HDMIOUT_CLK

Q56B
DMN66D0LDW -7_SOT363-6
HDMIO@
3
HDMIOUT_SCLK

5

[15]

[15]

PCH_HDMIOUT_CLK

Q56A
DMN66D0LDW -7_SOT363-6
HDMIO@
6
HDMIOUT_SDATA

4

HDMIOUT_SDATA

HDMIOUT_SCLK

[31]

[31]

Close to connector

+3VS
1
E

PCH_HDMIOUT_HPD

[31]

R616
200K_0402_5%
HDMIO@

4

2

INTEL HDMI HPD PD 20K

2

R168
20K_0402_5%

4

HDMIOUT_HPD

1

2
B

1

[15]

R615
10K_0402_5%
1
2
HDMIO@

C

3

Q59
MMBT3904_NL_SOT23-3
HDMIO@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/01

2014/04/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDMI-OUT Level Shift
Rev
0.3

ZEA00 LA-A061P M/B

Tuesday, September 24, 2013

Date:

A

B

C

D

E

F

G

Sheet

30
H

of

59

5

4

3

2

1

HDMI-OUT Connector
[30]
[30]

4

HDMIOUT_CLK+_C

1

HDMIOUT_CLK-_C

4

L38 HDMIO@
3

3

HDMIOUT_R_CK+

2

HDMIOUT_R_CK-

1
2
MURATA DLW 21SN900HQ2L

+HDMI_EDID_5V

HDMIOUT_R_D2HDMIOUT_R_D1+

HDMIOUT_TX0-_C

1

2

4

3

2

HDMIOUT_R_D0+

3

HDMIOUT_R_D0-

R532
2.2K_0402_1%
HDMIO@
2

[30]

1
4

[30]
[30]

MURATA DLW 21SN900HQ2L

EMI Reauest

2

R531
2.2K_0402_1%
HDMIO@

L39 HDMIO@
HDMIOUT_TX0+_C

HDMIOUT_R_D1HDMIOUT_R_D0+

1

1

D

[30]

JHDMI1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

HDMIOUT_R_D2+

EMI Reauest

HDMIOUT_R_D0HDMIOUT_R_CK+
HDMIOUT_R_CK-

HDMIOUT_SCLK
HDMIOUT_SDATA

HDMIOUT_SCLK
HDMIOUT_SDATA

[30]

+HDMI_EDID_5V
HDMIOUT_HPD

HDMIOUT_HPD

D2+
D2_shield
D2D1+
D1_shield
D1D0+
D0_shield
D0GND4
CK+
GND3
CK_shield GND2
CKGND1
CEC
Reserved
SCL
SDA
DDC/CEC_GND
+5V
HP_DET

D

23
22
21
20

SUYIN_100042GR019M12RZR
CONN@
L40 HDMIO@
[30]

HDMIOUT_TX1+_C

[30]

HDMIOUT_TX1-_C

1
4

1

2

4

3

2

HDMIOUT_R_D1+

3

HDMIOUT_R_D1-

MURATA DLW 21SN900HQ2L

EMI Reauest
D20
HDMIOUT_R_D1+ 1 1

C

L41 HDMIO@
[30]

HDMIOUT_TX2+_C

[30]

HDMIOUT_TX2-_C

4
1

4

3

1

2

3
2

C

HDMIO@
10 9 HDMIOUT_R_D1+

HDMIOUT_R_D1- 2 2

9 8

HDMIOUT_R_D1-

HDMIOUT_R_CK- 4 4

7 7

HDMIOUT_R_CK-

HDMIOUT_R_CK+ 5 5

6 6 HDMIOUT_R_CK+

HDMIOUT_R_D2+
3 3

HDMIOUT_R_D2-

8

MURATA DLW 21SN900HQ2L

EMI Reauest
IP4292CZ10-TBR XSON10

ESD Reauest

D21
HDMIOUT_R_D0+ 1 1

HDMIO@
10 9

HDMIOUT_R_D0+

HDMIOUT_R_D0- 2 2

9 8

HDMIOUT_R_D0-

HDMIOUT_R_D2- 4 4

7 7

HDMIOUT_R_D2-

HDMIOUT_R_D2+ 5 5

6 6

HDMIOUT_R_D2+

3 3
U34

B

+HDMI_EDID_5V

HDMIO@

8
B

+5VS

IP4292CZ10-TBR XSON10
OUT
1

1
C532
0.1U_0402_16V7K
HDMIO@

ESD Reauest
1

IN
GND

2

3

2

2

C534
0.1U_0402_16V7K
HDMIO@

AP2330W -7_SC59-3
HDMIOUT_SCLK
HDMIOUT_SDATA

200mA

2

3

3

2

HDMIOUT_HPD

HDMIO@
D22
PESD5V0U2BT_SOT23-3

HDMIO@
D23
PESD5V0U2BT_SOT23-3

(Cj=3.5pF)

(Cj=3.5pF)
1

ESD Reauest
1

ESD Reauest

A

A

Compal Secret Data

Security Classification
2013/04/01

Issued Date

Deciphered Date

2014/04/01

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDMI-OUT
Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

31

of

59

5

[29]
[29]

TXE0+
TXE0-

[29]
[29]

TXE1+
TXE1-

[29]
[29]

TXE2+
TXE2-

[29]
[29]

TXE3+
TXE3-

[29]
[29]

TXOC+
TXOC-

TXEC+
TXEC-

TXO0+
TXO0-

[29]
[29]

TXO1+
TXO1-

[29]
[29]

TXO2+
TXO2-

[29]
[29]

TXO3+
TXO3-

1

LVDS Conn.

TXE0+
TXE0TXE1+
TXE1-

D

[29]
[29]

2

Converter

JLVDS1

TXE2+
TXE2-

TXOCTXOC+

TXE3+
TXE3-

TXO1TXO1+
TXO3TXO3+
TXE0TXE0+
TXE2TXE2+

TXOC+
TXOCTXO0+
TXO0-

@ R361 1
+LCDVDD

TXO1+
TXO1-

2 0_0402_5%

100mil

@ C386
680P_0402_50V7K

G31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

G32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

INVPWR_B+:
Current Rating: Max=375mA

TXO0TXO0+
TXO2TXO2+

B+

@EMI@
C384
680P_0402_50V7K

TXE1TXE1+
TXE3TXE3+

+LCDVDD

1
2
TAI_HCB2012KF-221T30_0805 1

100mil

v0.3 update

@EMI@
C385
680P_0402_50V7K

JCON1
2

LCD_PWM
LCD_BKOFF#
[29,43]
[29,43]

EC_SMB_CK1
EC_SMB_DA1

2

1

TXO3+
TXO3-

D

INVPWR_B+

EMI@
L11

100mil

TXECTXEC+

100mil

ACES_87216-3016
CONN@

1

TXO2+
TXO2-

31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

1

TXEC+
TXEC-

3

2

[29]
[29]

4

@C387
@
C387
680P_0402_50V7K

2

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
11
12

GND
GND

13
14

ACES_50228-0127N-001
CONN@

C

C

+LCDVDD Rising Time: 300us~10ms
Current Rating: Max=1500mA

Active High
U21

B

C390
1U_0603_10V6K

1
2
@R362
@
R362
0_0402_5%

5
4

VOUT

1

100mil
+LCDVDD

VIN
GND

2

SS

1

EN

C388
4.7U_0603_10V6K

3

1

1

2

2

@ C389
@C389
0.1U_0402_16V4Z
B

APL3512ABI-TRG_SOT23-5
@ C391
2 0.01U_0402_16V7K

2

1

100mil

Converter

[29,43]

EC
[29,43]

S_ENVDD

[43]

1
@R363
@
R363

2
0_0402_5%

BKOFF#

1
R364

2
0_0402_5%

0_0402_5%
2
LCDVDD_EN

EC_ENVDD

1
@R367
@
R367

2
R368
100K_0402_5%

0_0402_5%

v0.3 update

2

[43]

2

EC

LCD_BKOFF#
R366
100K_0402_5%

v0.3 update

1

Converter

R365
1

S_BKOFF#

1

+5VALW

Converter
EC

[29]

S_INVT_PWM

1
@ R369

2
0_0402_5%

INVT_PWM

1
@ R370

2
0_0402_5%

[43]

LCD_PWM

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/01

Deciphered Date

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

LVDS
Document Number

Rev
0.3

ZEA00 LA-A061P M/B
Tuesday, September 24, 2013

Sheet
1

32

of

59

5

4

3

2

1

+USB3_VCCA

1

0_0402_5%
2
EMI@

L12
1
2
3
4

SYSON#

SYSON#

GND
IN
IN
EN#

[16]

8
7
6
5

OUT
OUT
OUT
OC#

[16]
USB30_OC#0

USB20_DEBN1

USB20_DEBN1

1

USB20_DEBP1

USB20_DEBP1

4

[16]

APL3510BXI-TRG MSOP8
D

@ R373

1

2

4

3

2

USB20_DEBN1_L

3

USB20_DEBP1_L

@ R376
470_0603_5%

MURATA DLW 21HN900SQ2L
0_0402_5%
1
2

v0.3 update

+USB3_VCCA

L13
[16]

U3RXDN_A

U3RXDN_A

4

[16]

U3RXDP_A

U3RXDP_A

1

EMI@
3

1

2

3

5
6
7
8
9

U3RXDN_A_L
U3RXDP_A_L

2

C2016
1

0.1U_0402_16V7K
2
U3TXDP_A_C

1

3

1

2

10
11

1
+

v0.3 update

LOTES_ABA-USB-124-P01
CONN@

EMI@

4

GND2
GND3

3

U3TXDN_A_L

2

U3TXDP_A_L

2

ESD@
D3
USB20_DEBP1_L

2

USB20_DEBN1_L

3

1

W CM2012F2S-900T04_0805

1

2

0.1U_0402_16V7K

L14

D

+USB3_VCCA

USB20_DEBN1_L
USB20_DEBP1_L

C397

4

GND4
GND5

1
2
3
4

47U_0805_6.3V6M

U3TXDP_A

0.1U_0402_16V7K
2
U3TXDN_A_C

@
Q15

C2070

[16]

C2015
1

VBUS
DD+
GND

100U_6.3V_M

For EMI request

SSRXSSRX+
GND1
SSTXSSTX+

C394

12
13

U3TXDN_A

S 2N7002K_SOT23-3

JUSB2

4

W CM2012F2S-900T04_0805

[16]

D

2
G

SYSON#

1

[34,43,44]

U22

2

@ C393
0.1U_0402_16V7K
2
1

1

2.5A

@ R371

2

+USB3_VCCA

1

W=80mils

+5VSB

3

W=80mils

PESD5V0U2BT_SOT23-3

Non Changer
C

C

W=80mils

W=80mils

+5VALW

+USB3_VCCB

2.5A

@ C401
0.1U_0402_16V7K
2
1

U24
1
2
3
4

SYSON#

NCHG@

GND
IN
IN
EN#

8
7
6
5

OUT
OUT
OUT
OC#

USB30_OC#0

APL3510BXI-TRG MSOP8

Charger

2

4

3

CHG@
C395
0.1U_0402_16V4Z
1
2

W=80mils

[43]
[43]

1

USB20_N0
USB20_P0
2 0_0402_5%

4
5
6
7
8

IN

OUT

FAULT# STATUS#
DM_OUT
DP_OUT

DM_IN
DP_IN

ILIM_SEL ILIM_LO
EN
ILIM_HI
GND
GPAD

9
11
10

U3RXDN_B

U3RXDN_B 1

[16]

U3RXDP_B

U3RXDP_B

4

USB20_N0_CHR
USB20_P0_CHR

15
16

1
1
R380
R381

14
17

[16]

1

2

4

3

2

5
6
7
8
9

U3RXDN_B_L
U3RXDP_B_L

3

W CM2012F2S-900T04_0805
12
13
2
2
80.6K_0402_1%
30K_0402_1%

CHG@
CHG@

[16]

U3TXDN_B

[16]

U3TXDP_B

C2017
1

0.1U_0402_16V7K
L17
2 U3TXDN_B_C 1
1

C2018
1

0.1U_0402_16V7K
2 U3TXDP_B_C

TPS2546RTER_QFN16_3X3

4

4

SSRXSSRX+
GND1
SSTXSSTX+

VBUS
DD+
GND

GND4
GND5

GND2
GND3

1
2
3
4
10
11

+USB3_VCCB

EMI@
2
3

2

U3TXDN_B_L

3

U3TXDP_B_L

LOTES_ABA-USB-124-P01
CONN@
1
+

W CM2012F2S-900T04_0805

CTL3
GPXIOA11(pin108)
1
1
1

ILIM_SEL
GPIO21(pin40)
1
0
1

For ESD request
D5

D6

U3RXDN_A_L

1

10

U3RXDN_A_L

U3RXDN_B_L

1

10

U3RXDN_B_L

U3RXDP_A_L

2

9

U3RXDP_A_L

U3RXDP_B_L

2

9

U3RXDP_B_L

U3TXDN_A_L

4

7

U3TXDN_A_L

U3TXDN_B_L

4

7

U3TXDN_B_L

U3TXDP_A_L

5

6

U3TXDP_A_L

U3TXDP_B_L

5

6

U3TXDP_B_L

100U_6.3V_M

CTL2
GPIO22(pin41)
1
1
0

@ Q16
2N7002K_SOT23-3
B

2

CTL1
GPXIOA07(pin104)
1
1
0

S

USB20_N0_CHR_L
USB20_P0_CHR_L

v0.3 update
Charger CT
EC GPIO
S0(CDP)
S3(SDP)
S4/S5(DCP)

D

2
G

SYSON#
JUSB1

1

2

0.1U_0402_16V7K

CTL1
CTL2
CTL3

12

v0.3 update

W=80mils

+USB3_VCCB

EMI@

C400

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

2
3

CHG@

Charge USB Port

47U_0805_6.3V6M

@ R382 1
@ R383 1
@ R384 1

@ R389
470_0603_5%

C399

USB_CHRMODE1
USB_CHRMODE2
USB_CHRMODE3

USB20_P0_CHR_L

C398

[43]
[43]
[43]

USB_ILIM_SEL
USB_CHR_EN

@ R379 1

U23
13

USB30_OC#0
USB20_N0
USB20_P0

3

For EMI request

+USB3_VCCB

L16

[16]
[16]

USB20_N0_CHR_L

MURATA DLW 21HN900SQ2L
@ R619
0_0402_5%
1
2

+5VSB

B

2

1

4

USB20_P0_CHR

+USB3_VCCB

EMI@

1

2

1

USB20_N0_CHR

0_0402_5%
2

1

1
L15

3

@ R618

2
USB20_N0_CHR
0_0402_5%
2
USB20_P0_CHR
0_0402_5%

1

1
R675
1
R676

2

v0.3 update
USB20_N0
NCHG@
USB20_P0
NCHG@

ESD@
D4
USB20_P0_CHR_L 2

3

3

1
USB20_N0_CHR_L 3

A

8

A

8
PESD5V0U2BT_SOT23-3

IP4292CZ10-TBR
Part Number = SC300002F00
ESD@

Security Classification
Issued Date

IP4292CZ10-TBR
Part Number = SC300002F00
ESD@

Compal Electronics, Inc.

Compal Secret Data
Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB 3.0 CONN
Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Sheet
1

33

of

59

5

4

3

2

1

USB20
+USB_VCCA
JUSB5
1
L37
[16]

USB20_N2

[16]

USB20_P2

USB20_N2

3

USB20_P2

2

VCC

EMI@

3

4

2

1

4

USB20_N2_R

2

USB20_P2_R

3

DD+

1
4

MURATA DLW 21HN900SQ2L

+USB_VCCA

5

GND1

6

GND GND2

TYCO_2041230-1
CONN@

D

+USB_VCCA

1

1
L36
[16]
[16]

USB20_N3

USB20_N3

USB20_P3

USB20_P3

3
2

4

2

1

4

USB20_N3_R

2

USB20_P3_R

3

C520
220U_6.3V_M

VCC

EMI@

3

D

1

+
JUSB6

1
C521

2

2

2

C522
0.1U_0402_16V7K

DD+

1
4

5

GND1

0.1U_0402_16V7K

v1.0 update

6

GND GND2

MURATA DLW 21HN900SQ2L

TYCO_2041230-1
CONN@

+USB_VCCB
JUSB4
1
L35
[16]

USB20_N8

[16]

USB20_P8

USB20_N8

3

USB20_P8

2

VCC

EMI@

3

4

2

1

4

USB20_N8_R

2

USB20_P8_R

3

DD+

1
4

MURATA DLW 21HN900SQ2L

+USB_VCCB

5

GND1

6

GND GND2

TYCO_2041230-1
CONN@

+USB_VCCB

1

JUSB3
1
L34
[16]
[16]

USB20_DEBN9
USB20_DEBP9

USB20_DEBN9
USB20_DEBP9

3
2

2

4
1

4

USB20_DEBN9_R

2

USB20_DEBP9_R

3

C514
220U_6.3V_M

VCC

EMI@

3

1

+

C

1
C515

2

2

2

C

C516
0.1U_0402_16V7K

DD+

1
4

5

GND1

GND GND2

MURATA DLW 21HN900SQ2L

0.1U_0402_16V7K

v1.0 update

6

TYCO_2041230-1
CONN@

For USB2.0 ESD diode
ESD@
D16

W=100mils

2.5A

+5VALW

USB20_N2_R

W=100mils

ESD@
D18

2

USB20_N8_R

2

USB20_P8_R

3

USB20_DEBN9_R

2

USB20_DEBP9_R

3

1

+USB_VCCA

USB20_P2_R

3

USB20_N3_R

2

USB20_P3_R

3

1

U31
8
7
6
5

PESD5V0U2BT_SOT23-3
ESD@
D17
USB_OC#1

APL3510BXI-TRG MSOP8
C519
0.1U_0402_16V7K

[16]

1

1

W=100mils
+USB_VCCB
+USB_VCCA

USB_OC#5
1

USB_OC#5

[16]

+USB_VCCB

1

8
7
6
5

C524
4.7U_0603_10V6K

@ R508
470_0603_5%

2

1

2

OUT
OUT
OUT
OC#

APL3510BXI-TRG MSOP8
C525
0.1U_0402_16V7K

Near Connector JUSB

@ R509
470_0603_5%

2

SYSON#

GND
IN
IN
EN#

B

PESD5V0U2BT_SOT23-3

Near Connector JUSB1

U32
1
2
3
4

1

PESD5V0U2BT_SOT23-3

2

2.5A

+5VALW

USB_OC#1

C518
4.7U_0603_10V6K

1

W=100mils

1

PESD5V0U2BT_SOT23-3
ESD@
D19

D

2
G

@ Q22
2N7002K_SOT23-3
3

SYSON#

2

1

2

OUT
OUT
OUT
OC#

SYSON#

1

SYSON#

SYSON#

B

GND
IN
IN
EN#

D

3

[33,43,44]

1
2
3
4

S

2
G

S

@ Q23
2N7002K_SOT23-3

A

A

Compal Secret Data

Security Classification
2013/04/01

Issued Date

Deciphered Date

2014/04/01

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB20
Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

34

of

59

5

4

3

2

1

D29

SATA ODD Conn

SATA HDD Conn.

+12VS

+5VS

100mil
JODP1
+12VS

100mil

100mil
C405
10U_0603_6.3V6M

ACES_88290-044G
CONN@

1

1

2

2

C403
10U_0603_6.3V6M

1

1

2

2

1 1

10 9

SATA_PTX_C_DRX_P0

SATA_PTX_C_DRX_N0

2 2

9 8

SATA_PTX_C_DRX_N0

SATA_PRX_C_DTX_N0

4 4

7 7

SATA_PRX_C_DTX_N0

SATA_PRX_C_DTX_P0

5 5

6 6

SATA_PRX_C_DTX_P0

3 3
C404
0.1U_0402_25V6

8

C406
0.1U_0402_25V6

1
2
3
4
GND
GND

Place close to JODP1.

ESD Reauest

Place close to JHDP1

+5VS

1
2
3
4
5
6

v0.3 update

IP4292CZ10-TBR XSON10

JHDP1

D

+12VS

100mil
1

ACES_88290-044G
CONN@

C407
10U_0805_25V6K

2

1

C408
0.1U_0402_25V6

1

D

+5VS

SATA_PTX_C_DRX_P0

2

1
2
3
4
GND
GND

+5VS

1
2
3
4
5
6

ESD@

2

@ C409
1U_0603_25V6K

Place close to JHDP1
JODD1
[12]
[12]

SATA_PTX_DRX_P4
SATA_PTX_DRX_N4

[12]
[12]

SATA_PRX_DTX_N4
SATA_PRX_DTX_P4

1
C410 1
C411
C413 1
C415 1

2
2 0.01U_0402_25V7K
0.01U_0402_25V7K
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

1
2
3
4
5
6
7
8
9

SATA_PTX_C_DRX_P4
SATA_PTX_C_DRX_N4
SATA_PRX_C_DTX_N4
SATA_PRX_C_DTX_P4

Place CAP close to JODD <100mil

GND
A+
AGND
BB+
GND
G1
G2

JHDD1

TYCO_4-1775058-5
CONN@

[12]
[12]

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

[12]
[12]

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

1
C412 1
C414
C416 1
C417 1

2
2 0.01U_0402_25V7K
0.01U_0402_25V7K
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

1
2
3
4
5
6
7
8
9

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0

Place CAP close to JHDD <100mil

GND
A+
AGND
BB+
GND
G1
G2
TYCO_4-1775058-7
CONN@

C

C

FAN Control Circuit
+3VS

+12VS

EMI@ C418
1
C419
1

60mil

1

1

v0.3 update

D7
BAV70W _SOT323-3

R397

2
2

1
2
3
4

FAN_CPU_SPEED_R
FAN_CPU_PW M_R

100_0402_5%

1
2
3
4

5
6

5
6

ACES_85205-0400N
CONN@

1

2

v1.0 update

1000P_0402_50V7K
2

JFAN1

2

1K_0402_5%
1
1

FAN_SPEED
FAN_PW M

3

R396
[43]
[43]

2

R395
10K_0402_5%

470P_0805_100V
2

C420
1000P_0402_50V7K

B

B

A

A

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SATA-HDD/ODD/USB
Document Number

Rev
0.3

ZEA00 LA-A061P M/B
Tuesday, September 24, 2013

Sheet
1

35

of

59

5

4

+1.2VS_CR_DV

+1.2VS_CR_AV

20mil
C421

1

2

C423
C422
0.1U_0402_16V4Z

1

40mil

1

2

4.7U_0603_6.3V6K

D

1

2

+3VS

20mil

1

2

3

2

C425
C424
0.1U_0402_16V4Z

4.7U_0603_6.3V6K

1

1

2

2

C426
0.1U_0402_16V4Z

10U_0603_6.3V6M

D

Place close to Pin9

+3VS
C427
20mil
1U_0402_6.3V6K
2
1 +DV33_18

40mil

+1.2VS_CR_AV
+1.2VS_CR_DV

40mil

+3VS_CR

W=12mil, L<200mil
[16] PCIE_PTX_C_CRRX_P1
[16] PCIE_PTX_C_CRRX_N1
[16] PCIE_PRX_CRTX_P1
[16] PCIE_PRX_CRTX_N1

C429 1
C430 1

1
R400

[15,39,40]

1

PLT_A_RST#

PCIE_PTX_C_CRRX_P1
PCIE_PTX_C_CRRX_N1
2 0.1U_0402_16V7K PCIE_PRX_C_CRTX_P1
2 0.1U_0402_16V7K PCIE_PRX_C_CRTX_N1

23

PLT_RST#_CR

1

2

@EMI@
C432
0.1U_0402_16V4Z

[13]

24

CLKREQ_CR#

CLKREQ_CR#
+3VS

1
2
@ R408
10K_0402_5%

1
2
5
6
3
4

2

@ R406
0_0402_5%

10

2 RREF 8
6.2K_0402_1%

[13] CLK_CR
[13] CLK_CR#

C

U25

9
15
7
11

+3VS

1
R409

2 GPIO_CR
10K_0402_5%

19

Length of per trace 2inch no more 2 via
mismatch trace length <100mil
50ohm +-15% impedance.

3V3_IN
SP3
AV12
DV12_S
Card_3V3
GND

25

1
@ R399
1
SD_D0_MS_D1
@ R401
1
SD_CLK_MS_D0
@ R402
1
SD_CMD_MS_D2
@ R403
1
SD_D3_MS_D3
@ R404
1
SD_D2_MS_CLK
EMI@ R405
SD_D1

RREF
HSIP
HSIN
HSOP
HSON

SP1
SP2
SP3
SP4
SP5
SP6

12
13
14
16
17
18

SD_D1
SD_D0_MS_D1
SD_CLK_MS_D0
SD_CMD_MS_D2
SD_D3_MS_D3
SD_D2_MS_CLK

REFCLKP
REFCLKN
PERST#

SD_W P

CLK_REQ#

SD_CD#

GPIO

MS_INS#

2 SD_D1_R
0_0402_5%
2 SD_D0_MS_D1_R
0_0402_5%
2 SD_CLK_MS_D0_R 1
0_0402_5%
2 SD_CMD_MS_D2_R
0_0402_5%
2 SD_D3_MS_D3_R
0_0402_5%
2 SD_D2_MS_CLK_R 1
33_0402_5%

EMI@
C428
5P_0402_50V

2
EMI@
C431
5P_0402_50V

2
C

v0.3 update

20

SD_WP_MS_BS

21

SD_CD#

22

MS_CD#

RTS5229-GR_QFN24_4X4

Place close to JCR1 pin 12,21
+3VS_CR

40mil

C433
10U_0603_6.3V6M
+3VS_CR

1

1

2

2

C434
0.1U_0402_16V4Z

40mil
B

B

JCR1
SD_D2_MS_CLK_R
SD_D3_MS_D3_R
SD_D2_MS_CLK_R
SD_CMD_MS_D2_R
SD_D3_MS_D3_R
MS_CD#

2

+3VS_CR

SD_CMD_MS_D2_R

@ R412
47_0603_5%

1

SD_CLK_MS_D0_R
SD_D0_MS_D1_R
SD_CLK_MS_D0_R
SD_WP_MS_BS

1

2N7002K_SOT23-3
SD_CD#

D

3

@ Q17

S

2
G

SD_D0_MS_D1_R
SD_D1_R
SD_CD#
SD_WP_MS_BS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

SD-DAT2
MS-VSS
SD-DAT3/MMC-RSV
MS-VCC
MS-SCLK
SD-CMD/MMC-CMD
MS-DAT3
MS-INS
SD-VSS/MMC-VSSI
MS-DAT2
SD-VDD/MMC-VDD
MS-DAT0
MS-DAT1
SD-CLK/MMC-CLK
MS-BS
MS-VSS
SD-VSS/MMC-VSS2
SD-DAT0/MMC-DAT
SD-DAT1
SD-CD
SD-GND
GND1
SD-W P
GND2

23
24

T-SOL_143-2300302603
CONN@

Reserve card power discharge circuit
A

A

Compal Secret Data

Security Classification
2013/04/01

Issued Date

Deciphered Date

2014/04/01

Title

Compal Electronics, Inc.
RTS5229 Media Card Controller

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
0.3

ZEA00 LA-A061P M/B

Tuesday, September 24, 2013

Sheet
1

36

of

59

4

v1.0 update
+5V_VDDA_HD

OUT

CODEC_PW REN
+5VS

1 LDO@ 2
R421 10K_0402_5%

2

SHDN

BP

4

1

LDO_BP

APL5320-475BI-TRG_SOT23-5

HP_DET#

C441
0.1U_0402_16V4Z

2

2

C442
10U_0603_6.3V6M

Close to Pin1

17
23
24
18

For ESD and EMI

20

1

MIC1_L

1

@EMI@
R427
4.7K_0402_5%

4.7U_0603_10V6K
4.7U_0603_10V6K

1

MIC1_R

MONO_IN

2MIC1_L_C 21
2MIC1_R_C 22
12

LOUT_R

MIC2_L

LOUT2_L

MIC2_R

LOUT2_R

LINE1_L

SPDIFO2

LINE1_R

DMIC_CLK1/2

LINE1_VREFO
LINE2_VREFO

NC
DMIC_CLK3/4

MIC2_VREFO
BITCLK

11

AZ_RST_HD#
[12]
C455
@EMI@ 0.01U_0402_25V7K
[41]
[43]

MIC_DET#
HP_DET#_CODEC

[12]
INT_DMIC_DATA
CODEC_MUTE#2
R433 1
R434

AZ_SYNC_HD
AZ_SDOUT_HD

10
5

2
0_0402_5%
2 CODEC_MUTE_R 3
1
13
SENSE_A
2 20K_0402_1% SENSE_B
34
5.1K_0402_1%
47
[43] EAPD_CODEC
@ R432
1

48

35

AMP_FRONT_LEFT

36

MIC1_R

SDATA_IN

PCBEEP_IN

MONO_OUT
CBP

RESET#
CPVEE
SYNC
MIC1_VREFO
SDATA_OUT
HPOUT_R
GPIO0/DMIC_DATA1/2
GPIO1/DMIC_DATA3/4
CBN
SENSE A
SENSE B
VREF
EAPD

JDREF

SPDIFO1

HPOUT_L

DVSS1
DVSS2

41

43

SENSE B

1

@EMI@
@EMI@
R424
C451
10_0402_5% 10P_0402_50V8J
1
2
1
2

44

INT_DMIC_CLK
@EMI@
C450
27P_0402_50V8J

2

[41]

1
C

D9
2

2

6

AZ_BITCLK_HD

AVSS1
AVSS2

8

HDA_SDIN0_AUDIO

37
29

1
R425
4.7K_0402_5%

[12]

31

1
2
33_0402_5%
R428

AZ_SDIN0_HD

10 mil

1
C454

2
2.2U_0603_10V6K

28
32
30
27
40
33

MIC1_R

R429
1K_0402_5%
1
2

MIC1_R_R1

MIC1_L

1

MIC1_L_R1

[12]

CBP

2

R430
1K_0402_5%

L19 EMI@
1
2
FBM-11-160808-601-T_0603
1
2
L20 EMI@
FBM-11-160808-601-T_0603

HP_RIGHT
1
C458

CBN

10 mil

MIC_DET#

4

MIC1_R_R

3
6
2
1

MIC1_L_R

EMI@
C456
330P_0402_50V7K

1

1

2

EMI@
2 C457
330P_0402_50V7K

7
8
SINGATRON 2SJ-B351-S39

2
2.2U_0603_10V6K

+VREF

1

272JDREF
HP_LEFT

26
42

R435
20K_0402_1%

C460

1

1

2

2

2

C461

ESD@
C459
0.1U_0402_16V7K

Close to Pin27
B

MIC1_R_R

HP_RIGHT

MIC_DET#

PL

MIC1_L_R

HP_LEFT

1
R440
1
R441

2
HP_RIGHT_R
75_0603_1%
2
HP_LEFT_R
75_0603_1%

EMI@
1
L21 EMI@
1
L22

LOUT1 (PIN 35,36)

39.2K

LINE2 (PIN 14, 15)

20K

MIC2 (PIN 16, 17)

[37,43]

HP_DET#

2
FBM-11-160808-601-T_0603
2
FBM-11-160808-601-T_0603

ESD@ D10
PESD5V0U2BT_SOT23-3

ESD@ D11
PESD5V0U2BT_SOT23-3

3
6
2
1

PL

1

1

2

2

8

EMI@
C463
330P_0402_50V7K

SINGATRON 2SJ-B351-S39
1
ESD@
C464
0.1U_0402_16V7K

A

Compal Secret Data
2013/04/01

2014/04/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4

CONN@

ESD@ D12
PESD5V0U2BT_SOT23-3

Issued Date

HP-OUT (PIN 32,33)

PR

2

Security Classification

10K

4

7
EMI@
C462
330P_0402_50V7K

MIC1 (PIN 21, 22)

5.1K

JHP1
5
HP_DET#

2

3

PR

2

LOUT2 (PIN 39, 41)

HP_DET#

3

Codec Signals

LINE1 (PIN 23, 24)

5

CONN@

HP OUT

10K

5.1K

JMIC1
5

1

20K

EXT MIC IN

Need
600 Ohm
500 mA

Need
600 Ohm
500 mA

2

Impedance

R426
4.7K_0402_5%

+MIC1_VREFO

1

A

D8

MURATA_BLM15BB221SN1D_0402
INT_DMIC_CLK_R

AGND

39.2K
SENSE A

+MIC1_VREFO

EMI@ L45

45
46

v0.3 update

3

Sense Pin

Internal Speaker

EMI@

1

DGND

C443
0.1U_0402_16V4Z

[38]

0.1U_0402_16V4Z

2
0_0603_5%
2
0_0603_5%
2
0_0603_5%
2
0_0603_5%

2

39

DGND To AGND Bypass
1
@ R436
1
@ R437
1
@ R438
1
@ R439

[38]

AMP_FRONT_RIGHT

ALC272-VA4-CG_LQFP48_7X7

B

1

Close to Pin9

C448
10U_0603_6.3V6M

10U_0603_6.3V6M

4
7

2

2

Close to U7

2

MIC1_L

2

R431 @EMI@
100K_0402_5%

19

LOUT1_L

LINE2_R

1

1

16

LINE2_L

1

1

15

C447
0.1U_0402_16V4Z

1

14

C452
C453

0.1U_0402_16V4Z

R422
4.7K_0402_5%

2

AVDD1

0.1U_0402_16V4Z

+3VS

C436
1
2 MONO_IN

MONO_IN_1

1

2

2
100P_0402_50V8J U27

9

2

1

2

2

1
C449
@EMI@

DVDD

2
10U_0805_10V6K

1
C446

DVDD_IO

C445

1 R419

47K_0402_5%

Change to AGND for
high frequency noise issue

38

C444

1

25

1

1

PCH_SPKR

D

1

LDO@ C440
0.22U_0402_6.3V6K

0.1U_0402_16V4Z

2

C2019
47U_0805_6.3V6M

[12]

[37,43]

PCI Beep
[12]

@ R420
0_0402_5%
2 HP_DET#_CODEC
HP_DET# 1

+HD_AVDD

L18
1
2
FCM1608KF-800T07_0603

47K_0402_5%

2

+5V_VDDA_HD

C

C439
4.7U_0603_10V6K

+3VS_VDD

AVDD2

[43]

5

GND

3

@ R418
0_0603_5%

1

IN

2
D

LDO@

U26
1

2

1

C438
0.1U_0402_16V4Z

1 R413

EC_BEEP#

@ R417
10K_0402_5%

2

2

Beep sound

EC Beep
[43]

+3VS

2

0_0603_5%
2

1

+3VS

Output:4.75v
Max I:350mA

2

R416
1

2

1

@
1
C437
4.7U_0603_10V6K

+5V_VDDA_HD

Codec Regulator

+5VS

3

1

5

3

2

HDA-ALC272/HP/MIC
Document Number

Rev
0.3

ZEA00 LA-A061P M/B
Tuesday, September 24, 2013

Sheet
1

37

of

59

A

B

+5VS

v0.3 update
4.7U_0805_25V6K
C465
1
2

4

R448
12K_0402_1%
1
2
C469
1
2

1 @ R447 2

C470 22U_0805_6.3V6M
1
2

R449
2.4K_0402_1%
+PVDD

47P_0402_50V8J

120 mil
C471

1

10U_0805_10V6K
0.1U_0402_16V4Z
1
1
1
C473 C474

C472

10U_0805_10V6K
2

2

Close to Pin12

2
2
0.1U_0402_16V4Z

U29
4
5

Close to Pin4,5
1

[37]

AMP_FRONT_LEFT

@ R452
0_0402_5%
1
2

R451
5.6K_0402_1%
1
2

R453
1.1K_0402_1%
1
2

1
C475

AMP_PD#
1
C476

1

AMP_FRONT_RIGHT

R457
1.1K_0402_1%
1
2

2 AMP_L_C
1U_0402_6.3V6K

2

2

R459
5.6K_0402_1%

v0.2 update

OUT-RN
AVDD
OUT-RP
OUT-LN

14

INPUT-L
OUT-LP

9

1
8

OUTPR

2

OUTNL

3

1

2

20K_0402_5%
R464
20K_0402_5%

+PVDD

OUTPL

HOLD/SDA/G2
INPUT-R

16

AMP_G2

15

AMP_G1

10

Mode1 Mode2

MODE1

@ R455
0_0402_5%

@ R460
0_0402_5%

MODE1
MODE2

AGND

BYPASS

EPAD

11
@ R463
0_0402_5%
1
2

R462
+PVDD

Mode selet: Fix Gain

@ R454
0_0402_5%

VOL/SCL/G1

MODE2

OUTNR

6

SDb

13

MODE1

7

17

MODE2

Pin15

Pin16

G1

G2

I2C

SCL

SDA

0

PWM

PWM

Hold

1

DC

DC

Hold

0

0

0

1

1
1

Option
Fixed Gain

2

@ R461
0_0402_5%

1

[37]

R458
10K_0402_5%

@ R456
0_0402_5%
1
2

1

2

1

AMP_PD#

PVDDL
PVDDR

2
12
R617
0_0402_5%

2 AMP_R_C
1U_0402_6.3V6K

2

[43]

@

1

+3VS

2

1
2
HCB2012KF-221T30_2P
2
L24 1
@
HCB2012KF-221T30_2P

1

1

1
2
3
@

120 mil L23

2

C466
1U_0402_6.3V6K

APL5610CI-TRG_SOT23-6

0_0402_5%
+5VS

3

POK FB

+5VS

1

2

DRVGND

1

FDS8884_SO8

8
7
6
5

4

5
R445
10K_0402_5%
1
2

1

VCC EN

2

2

2

C468

4.7U_0805_10V6K

1

1

4.7U_0805_10V6K

C467

Q18

R444
10K_0402_5%
1
2

U28
6

+12VS
1

E

2

2 0.1U_0402_16V4Z

1

2 0.1U_0402_16V4Z

1

2

1

C2155

1

C2154

@ESD@

D

2

@ESD@

C

Vo=0.8(1+R606/R607)
Output:4.8V
Max I:7.5A

ALC109-CGT_EPAD-SOP16

C477
2 2.2U_0805_25V6K

Gain Select
+PVDD

AMP_G2

Gain

0

11dB

0

1

14dB

1

0

19dB

1

1

25dB

1

1

AMP_G1

C478
470P_0603_50V8J
EMI@

OUTPL

C481
1000P_0603_50V7K
2 EMI@

3

2
1

@ R669
0_0402_5%

@ R670
0_0402_5%

v1.0 update

CONN@

C485
1000P_0603_50V7K
2 EMI@

2

3
1

D14
PESD5V0U2BT_SOT23-3
ESD@

R468
22_1206_5%
EMI@
2

2

R467
22_1206_5%
EMI@

C484
470P_0603_50V8J
EMI@

D13
PESD5V0U2BT_SOT23-3
ESD@

1

C483
1000P_0603_50V7K
2 EMI@

3A/120ohm/100MHz

3

2

2

1

C482
470P_0603_50V8J
EMI@

L28 EMI@
MURATA BLM18PG121SN1D 0603
1
2
SPKL1

OUTNL
1

SPKR+

3A/120ohm/100MHz

1 2

L27 EMI@
MURATA BLM18PG121SN1D 0603
1
2
1

OUTPR

1 2

AMP_G2

(Default)

R466
22_1206_5%
EMI@

2

R465
22_1206_5%
EMI@

C480
470P_0603_50V8J
EMI@

SPKL+
SPKLSPKR+
SPKR-

AMP_G1

@ R668
0_0402_5%

2

SPKR-

C479
1000P_0603_50V7K
2 EMI@

1 2

1 2

1

OUTNR

L26 EMI@
MURATA BLM18PG121SN1D 0603
1
2
SPKL+
3A/120ohm/100MHz
1

1

L25 EMI@
MURATA BLM18PG121SN1D 0603
1
2
3A/120ohm/100MHz
1

ACES_87212-04G0
JSPK1
1
2 1
3 2
4 3
5 4
6 GND
GND

2

3

1

2

@ R667
0_0402_5%

0

4

4

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2014/04/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AMP
Rev
0.3

ZEA00 LA-A061P M/B

Date:

A

B

C

D

Tuesday, September 24, 2013

Sheet
E

38

of

59

5

4

3

WOL circuit
v0.2 update

@ J5
1

1

2

C556

1

2

G

+5VALW

1

1

@ Q27
SSM3K7002FU_SC70-3

@ C559 1

2 10U_0805_10V6K

C560

1

2 0.1U_0402_16V4Z

@ C2128 1

2 10U_0805_10V6K
C561

1

2 1U_0402_6.3V6K

C554
0.1U_0402_16V4Z

1

1

2

2

C555
4.7U_0603_10V6K
D


C555 is X5R
C554, C555 close to U26
Pin22

C553, C557, C558, C560, close to Pin 3,8,22,30
C561(1uF) close to Pin22

@

2
10K_0402_5%

CLK_LAN
CLK_LAN#

15
16

CLKREQ_LAN#

12

LAN_W AKE#_R

21

ISOLATE#

20
19

PLT_A_RST#
1

40 mils
1
R580

2

ESD@
C2134
0.1U_0402_16V4Z

23
+LAN_VDDREG
2
31
2.49K_0402_1%

+LAN_VDDREG

v0.2 update

29
28

LAN_X2
LAN_X1

HSIP
HSIN
REFCLK_P
REFCLK_N

22

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3

1
2
4
5
6
7
9
10

LAN_MIDI0+
LAN_MIDI0LAN_MIDI1+
LAN_MIDI1LAN_MIDI2+
LAN_MIDI2LAN_MIDI3+
LAN_MIDI3-

25
26
27

LAN_LED_ORG#
LAN_LED_YEL#
LAN_LED_GRN#

LANWAKEB
ISOLATEB

LED2
LED1/GPIO
LED0

PERSTB
VDDREG
RSET

CKXTAL2
CKXTAL1

REGOUT

GND

24

60 mils

33

1

2

1
D

S

LAN_MIDI0+

1

LAN_MIDI0-

2

LAN_MIDI1+

3

LAN_MIDI1-

4

@ R582
0_0402_5%

2

6
EMI@
C565
0.01U_0402_16V7K

2

C568 8111GS@
0.1U_0402_16V4Z

8111GS
(SWR Mode)

Yellow

LAN_LED_YEL#

R583
510_0402_5%
1
2

LAN_MIDI2+

7

LAN_MIDI2-

8

LAN_MIDI3+

9

LAN_MIDI3-

10

L4

TD1+ R1
TD1- R2
TD2+ R3
TD2- R4
CT R5
CT R6
TD3+ R7
TD3- R8
TD4+ R9
TD4- R10

20mils
LAN_LED_YEL#_R

B

11

L1

+3V_LAN
+
12

ESD@ D24
Part Number = SC300001J00
1
10
LAN_MIDI110 9
2 1
LAN_MIDI0+
9 8
3 2
LAN_MIDI1+
3
8
4
7
LAN_MIDI04
7
5
6
5
6

2

2
G
3

LAN_W AKE#_R

UDE_RV1-26295NU1
CONN@

GND

2
0_0402_5%

GND
GND

L2

15
16

LAN_GND

DC234008N10

11

@ R585


C567 is X5R

8111G
(LDO Mode)

1

L44
8111GS@
2.2UH +-5% NLC252018T-2R2J-N
1
2
1
8111GS@ C567
4.7U_0603_10V6K

C

+
14

5

@ R584
10K_0402_5%

1
1

LAN_LED_ORG#_R

+LAN_VDD10

60 mils

8111G@
C566
0.1U_0402_16V4Z

L3

20mils

vendor recommend

8111G@
R581
0_0603_5%
1
2

13

+

Green / Orage

+LAN_REGOUT

B

@ Q28
2N7002K_SOT23-3

LAN_LED_ORG#

R576
249_0402_1%
1
2

JRJ1

20mils
LAN_LED_GRN#_R

CLKREQB

RTL8111G-CG_QFN32_4X4

+3V_LAN

R575
249_0402_1%
1
2

1

1
R577

13
14

HSOP
HSON

LAN_LED_GRN#

2

CLK_LAN
CLK_LAN#

2
1K_0402_5%

PCIE_W AKE#

2 0.1U_0402_16V4Z

1

PCIE_PTX_C_LANRX_P2
PCIE_PTX_C_LANRX_N2

[15,36,40] PLT_A_RST#

[14,40]

1

2
0_0603_5%

+LAN_VDD10

DVDD10

PCIE_PRX_C_LANTX_P2 17
PCIE_PRX_C_LANTX_N2 18

CLKREQ_LAN#

R579
15K_0402_5%

C558

1

2 0.1U_0402_16V4Z

2

1
R578

1 .1U_0402_16V7K
1 .1U_0402_16V7K

+3V_LAN

11
32

+LAN_VDD10

U36

PCIE_PTX_C_LANRX_P2
PCIE_PTX_C_LANRX_N2

+3VS

2 0.1U_0402_16V4Z

@ C562
0.1U_0402_16V4Z

AVDD33
AVDD33

C563 2
C564 2

PCIE_PRX_LANTX_P2
PCIE_PRX_LANTX_N2

[13]

2 0.1U_0402_16V4Z

1

2

3
8
30

S

AVDD10
AVDD10
AVDD10

3

2
1

D

2
G

[13]
[13]
+3VS

1

C557

@ R572

@ R574
200K_0402_5%
1
2

Close to Pin 17,18

[16]
[16]

1

C553
2 0.1U_0402_16V4Z

C552, C556, C559, C2128 close to Pin 11,32

+3V_LAN rising time (10%~90%) need > 0.5ms and <100ms.

[16]
[16]

1

+LAN_VDDREG

v1.0 update

@ R573
100K_0402_5%

W OL_EN#

+3V_LAN

C552

60mil

D

S

D

3
@ Q26
AO3413_SOT23-3

40 mils

+LAN_VDD10

+3V_LAN
+3V_LAN

60mil

60 mils

40 mils

JUMP_43X79
2

+3VALW _PCH

C

1

Power ( Decoupling Cap. )

Short J5 for WOL support (Enable/Disable by BIOS setup)

[43]

2

LAN_LED_YEL#
TCLAMP3304N.TCT_SLP2626P10-10
LAN_LED_ORG#

0_0805_5%
1

2

@

LAN_MIDI2+
@ESD@ D26
PESD5V0U2BT_SOT23-3

LAN_MIDI2-

LAN_GND
1

GND

Crystal

R586
2
3

ESD@ D25
Part Number = SC300001J00
1
10
LAN_MIDI310 9
2 1
9 8
3 2
LAN_MIDI3+
8 7
4 3
7 6
5 4
5
6
11

LAN_X1
A

A

Y4
1
4

OSC
NC

NC
OSC

2

TCLAMP3304N.TCT_SLP2626P10-10

3

LAN_X2

1 25MHZ_10PF_X3G025000DA1H-X 1
C569
10P_0402_50V8J

2

2

Compal Secret Data

Security Classification
C570
10P_0402_50V8J

2013/04/01

Issued Date

2014/04/01

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LAN RTL8111G
Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

39

of

59

5

4

MINI(TV)/m-SATA
SSD
Mini Card Slot 1---TV tuner

3

Current: +3VS : 2750mA, 1.5V: 500mA

v1.0 update

[14,39]

@ R470
0_0402_5%
1
2 PCIE_W AKE#_R

PCIE_W AKE#
+3VS

[13]

TV_CLKREQ#

TV_CLKREQ#

D

[13]
[13]

CLK_TV#
CLK_TV
B_DETECT_R

[12]
[12]
[12]
[12]

SSD@ C2020 1
SSD@ C2021 1
TV@ R620 1
TV@ R621 1
SSD@ C2023 1
SSD@ C2022 1
TV@ C121 1
TV@ C122 1

SATA_PRX_DTX_P1
SATA_PRX_DTX_N1
[16] PCIE_PRX_TVTX_N4
[16] PCIE_PRX_TVTX_P4
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
[16] PCIE_PTX_TVRX_N4
[16] PCIE_PTX_TVRX_P4

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
2 0_0402_5%
2 0_0402_5%
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_PRX_R_TVTX_N4
PCIE_PRX_R_TVTX_P4
PCIE_PTX_C_TVRX_N4
PCIE_PTX_C_TVRX_P4
+3VS

@ R478
@ R477
@ R479

0_0402_5%
0_0402_5%
0_0402_5%
1
1
1

+3VS
+12VS

2
2
2

+3VS_TV_R
+12VS_TV1
+12VS_TV2

@ R665
1
1

0_0402_5%
2
+12VS_TV1
2
+12VS_TV2

@ R666

0_0402_5%

@ C494
0.1U_0402_16V4Z

1

1

2

2 @ C495
0.1U_0402_16V4Z

1

+3VS

JMINI1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND1 GND2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

1

2
4.7U_0805_10V4Z

+3VS

+1.5VS

120mil

1

TV@
C488

H=4mm
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53

E51_TXD
E51_RXD

2

TV@
C489

TV@
C490
0.1U_0402_16V4Z

2

TV@
C491

40mil

1

TV@
C492

2
4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VS

+VCC_SIM
B_DAT
B_CLK
B_RST
@ R471 1

+VCC_SIM
D

2 0_0402_5%

+5VS

+3VS

TV@
1

PLT_A_RST#

PLT_A_RST#

@ R474
@ R476
1
PM_SMBCLK_TV
PM_SMBDATA_TV 1

0_0402_5%
0_0402_5%
2
2

USB20_N10
USB20_P10

+VCC_SIM

[15,36,39]

F1
2

Smart Card Conn.(B-CAS)

+VCC_SIM
1

2A_63V_0437002.W R_1206

C493
330P_0402_50V7K
2 TV@

v0.3 update
PM_SMBCLK [10,11,13,5]
PM_SMBDATA [10,11,13,5]

[16]
[16]

JBCAS1
1
2
3
4
5
6
7
8
9
10
GND
GND

54

LOTES_AAA-PCI-049-P06-A
CONN@

1
2
3
4
5
6
7
8
9
10
11
12

DET1
B_DETECT_R
B_DAT
B_CLK
B_RST
+VCC_SIM

+VCC_SIM
1

ACES_85201-1005N
CONN@

2

TV@
C496
0.1U_0402_16V4Z

C

C

WLAN & Bluetooth

+3VALW _MINI

Combo Card

+1.5VS
R480
@ 0_0603_5%
1
2

40mil

+1.5VS_MINI

20mil

1

Mini Card Slot 2--- WLAN Current: 3.3 : 750mA,

1

1

80mil
+3VALW _MINI

G

2

2
1

R484 @
200K_0402_5%
1
2

[16]
[16]

1

1

W L_PW RON

D

2

C503 @
0.1U_0402_16V4Z

[16]
[16]

Q21 @
3

[43]

2
G

@

CLK_W LAN#
CLK_W LAN

PCIE_PRX_W LANTX_N3
PCIE_PRX_W LANTX_P3
PCIE_PTX_C_W LANRX_N3
PCIE_PTX_C_W LANRX_P3

S 2N7002K_SOT23-3
+3VALW _MINI

[43]
[43]

Add power on/off for support
wake on WLAN in S3 & S4 & S5

E51TXD_P80DATA
E51RXD_P80CLK

E51_TXD
E51_RXD

1

2

@ R507

0_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53

Debug card using
[43]

BT_ON

1

2

1

+

C499

2

@ C502
68U_B2_6.3VM_R70M

@ C500
0.1U_0402_16V4Z

2

JMINI2

2 0_0402_5%

CLKREQ_W LAN#
[13]
[13]

@ R483
100K_0402_5%
B

R482 1

BT_ON
[13]

H=4mm

@ R481
0_0402_5%
1
2

PCIE_W AKE#

AO3413_SOT23-3

+5VALW

2

1

0.1U_0402_16V4Z

D

S

+3VALW _PCH

3

2

C498

C2157
0.1U_0402_16V7K
1
2

JUMP_43X79
2
2

@ Q20

80mil

1

0.1U_0402_16V7K

v1.0 update

Short J4
@ J4
1
1

C497
4.7U_0603_6.3V6K

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND1 GND2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+3VALW _MINI
+1.5VS_MINI
@ R622
1

@ R510
1

0_0402_5%
2

W L_OFF#_EC

PLT_A_RST#
@ R485
@ R486
1
PM_SMBCLK_W L
1
PM_SMBDATA_W L

W LAN_LED#
BT_LED#

[43]

B

0_0402_5%
0_0402_5%
2
PM_SMBCLK
2
PM_SMBDATA
USB20_N4
USB20_P4

[16]
[16]

W LAN_LED# [42]
BT_LED# [42]

54
W LAN_LED#

LOTES_AAA-PCI-049-P06-A
CONN@

2

10K_0402_5%
2
+3VALW _MINI

BT_LED#

R489
1K_0402_5%

R487
1

10K_0402_5%
2

1
R488

2
10K_0402_5%

+3VALW _MINI

PLT_A_RST#

@ESD@
2 0.1U_0402_16V4Z
C2153 1

v0.3 update

A

Compal Secret Data

Security Classification
2013/04/01

Issued Date

2014/04/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

A

2

PCIe-WLAN/TV_B-CAS
Document Number

Rev
0.3

ZEA00 LA-A061P M/B
Tuesday, September 24, 2013

Sheet
1

40

of

59

5

4

3

TPM(Reserve)

2

1

Screw Hole
H5

H6

H7
H_4P2
@

PCH heat
sink

H26
H_4P2
@

H_4P2
@
1

H_4P2
@

1

H_4P2
@
1

1

1

+3VS

H4
H_4P2
@

1

H2
H_4P6X4P2
@

1

H1

H11

H12

H23

H14

JP1

[15,21,43]

@ R674

0_0402_5%

HOMET_PH02Z22BJZ202
CONN@

H25
1
2

HOMET_PH02Z22BJZ202
CONN@

2

TPM@
2 C2132
10U_0603_6.3V6M

H20

ZZZ1
H_3P3
@

FD1
@

FD2
@

FD3
@

FD4

H27

H28
H_1P5N
@

@

H21
H_1P5N
@

ZZZ2

PCB@

DAZ@

H22
H_7P0N
@

H_7P0N
@
1

1

1
2

1

H_3P5
@

1

1

D

JP2

1

1

H_12P0
@
1

H_12P0
@

H_4P4
@

1
2

H_6P4
@
1

1

1

1

1

1

1

H19

H10
H_4P4
@

H_3P3
@

+3VSB

TPM@
C2131
0.1U_0402_16V4Z

ST33ZP24AR28PVSP_TSSOP28

1
@ C2133
0.1U_0402_16V4Z

H13
5
8
12
13
14

NC
VNC
NC
NC
NC

LRESET#

H24

H_6P4
@

1

16

H9
H_4P4
@

H_6P4
@

1
2

4
11
18

GND
GND
GND

NC
LCLK
NC
NC

H8

6
9

NC
VNC

H_6P4
@

1

2

LPCPD#
SERIRQ
LAD0
LAD1
LFRAME#
LAD2
LAD3

H_2P9
@

1

25
21
19
15

+3VS

1
2
3
7

NC
NC
NC
PP

H_2P9
@

1

1

PLT_RST#

2
33_0402_5%

VPS
VPS

H_2P9
@

1

1
TPM@ R673

CLK_PCI_EC

28
27
26
23
22
20
17

SERIRQ
LPC_AD0
LPC_AD1
LPC_FRAME#
LPC_AD2
LPC_AD3

SERIRQ
LPC_AD0
LPC_AD1
LPC_FRAME#
LPC_AD2
LPC_AD3

TPM@

U75
24
10

1

2

H_2P9
@

H18

1

[13,43]

2

TPM@
C2130
10U_0603_6.3V6M

H17

1

[13,43]
[13,43]
[13,43]
[13,43]
[13,43]
[13,43]

1

1

D

1

H16

1

TPM@
C2129
0.1U_0402_16V4Z

H15

Co-lay Nuvton_NPCT421LA0WX

1

20 mils

PCB LA-A061P

PCB LA-A061P

CRT Conn(Reserve 15pin)

2

CRT@
[15]

PCH_CRT_R

[15]

PCH_CRT_G

[15]

PCH_CRT_B

F2
1

30 mils

2

2A_63V_0437002.W R_1206

1

1

L31

1

CRT@
C505
2.2P_0402_50V8C

2

8
7
6
5

30 mils

2 NBQ100505T-800Y_0402

CRT_R_L

2 NBQ100505T-800Y_0402

CRT_G_L

2 NBQ100505T-800Y_0402

CRT_B_L

CRT@

CRT@
RP16
150_0804_8P4R_1%

+CAM_PWR

1

C

1
2
3
4

500mA
+3VS

1

L30

CRT@

C

WebCam+Digital Mic

L29

1

CRT@
C506

1

CRT@
C507
2.2P_0402_50V8C

2
2
2.2P_0402_50V8C

CRT@
C508
2.2P_0402_50V8C

1

1

CRT@
C509

1

CRT@
C510
2.2P_0402_50V8C
2
2
2.2P_0402_50V8C

2

C504

v0.3 update
2

L32
[16]
[16]

4

USB20_P11

1

USB20_N11

10U_0603_6.3V6M

Need PU/PL on PCH/FCH side
(2.2K*2pcs for DDC & 150_8P4R*1pcs for RGB)

EMI@

4

JCAM1
3

1

JCRT1

2

3
2

30 mils

+CAM_PWR

USB20_P11_R
USB20_N11_R
+CAM_PW R

MURAT_DLW 21SN900HQ2L_0805

B

3

2

[37] INT_DMIC_DATA
[37] INT_DMIC_CLK

1
2
3
4
5
6
7
8

1 GND
2
3
4
5
6
7
8 GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14

CRT_R_L
CRT_G_L
CRT_B_L
HSYNC
VSYNC
CRT_DDC_CLK
CRT_DDC_DAT

9

10
+HDMI_EDID_5V

ACES_87213-0800G
CONN@

1
2
3
4
5
6
7 G2
8 G1
9
10
11
12
13
14

16
15

B

ACES_87212-14G0
CONN@
D15
PESD5V0U2BT_SOT23-3
ESD@

Touch

30 mils

+5VS_TOUCH

JTCH1
1
2
3
4
5
GND
GND

BYP

VCC_VIDEO

VIDEO1

VCC_DDC

VIDEO2

8

+HDMI_EDID_5V

CRT@
1
2
C512
0.22U_0402_16V7K

3

CRT_R_L

+5VS

TOUCH@
1
2
F3
2A_63V_0437002.W R_1206

L33

TOUCH@
1
2
3
4
5
6
7

4
USB20_N5_R
USB20_P5_R
1

PCH_CRT_DATA

10

[15]

PCH_CRT_CLK

11

v0.3 update
[15]

C513 0.1U_0402_16V4Z
1
2

[15]

TOUCH@

4

3

1

2

7

[15]

4

CRT_G_L

5

CRT_B_L

PCH_CRT_VSYNC
PCH_CRT_HSYNC

13
15

DDC_IN1

VIDEO3

DDC_IN2

DDC_OUT1

SYNC_IN1
SYNC_IN2

DDC_OUT2
SYNC_OUT1

USB20_N5
USB20_P5

2

[16]
[16]

GND

SYNC_OUT2

R494
4.7K_0402_5%
CRT@

9

CRT_DDC_DAT

12

CRT_DDC_CLK
R496 CRT@
1
VSYNC_R

14

3
6

R493
4.7K_0402_5%
CRT@
1

+3VS

500mA

A

2

CRT@

VCC_SYNC

2

+5VS

1

2

U30
+HDMI_EDID_5V

1

1

@ C511
0.1U_0402_16V4Z
1
2

R497

16

HSYNC_R

2 22_0402_5%

VSYNC

1 CRT@ 2 22_0402_5%

HSYNC

A

TPD7S019-15DBQR_SSOP16

MURAT_DLW 21SN900HQ2L_0805

EMI Reauest

ACES_87212-05G0
CONN@
2

USB20_P5_R

3

Compal Secret Data

Security Classification

@EMI@
D28
USB20_N5_R

2013/04/01

Issued Date
1

2014/04/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PESD5VOU2BT_SOT23-3

Date:

5

4

3

2

PWR/Cap./TP/LED/LP/LS/Screw
Document Number

Rev
0.3

ZEA00 LA-A061P M/B
Tuesday, September 24, 2013

Sheet
1

41

of

59

A

B

C

JPW R1

v0.3 update
+3VSB

1

PW R_ON_LED

S

[43]

2
G

EC_SW _AD1

Q66
SSM3K7002FU_SC70-3

1
2
3
4
5
6
7
8
9
10

G11
G12

Pin1~7:
LED Board

11
12

Pin6~10:
Switch Board&
Power Button Board
1

ACES_87212-10G0
CONN@

2

@ R567
8.2K_0402_5%

1
[43]

3

PW R_ON_LED#

1
2
3
4
5
6
7
8
9
10

CIR_IN
BT_LED#
SATA_LED#
W LAN_LED#
1
2
+5VS_SB
F4
2A_63V_0437002.W R_1206
1
2
+3VSB_SB
F5
2A_63V_0437002.W R_1206
ON/OFFBTN#
EC_SW _AD1

[43] CIR_IN
[40] BT_LED#
[12] SATA_LED#
[40] W LAN_LED#
+5VS

1

E

8Pin sub-board Conncetor

Power/B & SW/B Connector

D

D

v1.0 update

D2
2

@ SW 1
1

3

ON/OFFBTN#

1

ON/OFF_R#

3
2

2

ON/OFF#

1
@ R360
0_0402_5%

4

C382
100P_0402_50V8J

BAV70W _SOT323-3
6
5

[43]

1

SMT1-05-A_4P

2

C38 common SPEC request

TOP side For debug
(Unpop after MP)

1
PSU@
R657
10K_0402_5%

+5VS_SB
+3VSB_SB

EMI@ C2144
EMI@ C2145

1
1

2 0.1U_0402_16V4Z
2 470P_0402_50V7K

CIR_IN
BT_LED#
SATA_LED#

EMI@ C2146
EMI@ C2147
EMI@ C2148

1
1
1

2 330P_0402_50V7K
2 330P_0402_50V7K
2 330P_0402_50V7K

W LAN_LED#
PW R_ON_LED#
ON/OFFBTN#
EC_SW _AD1

EMI@
EMI@
EMI@
EMI@

1
1
1
1

2
2
2
2

C2149
C2150
C2151
C2152

1
EC_ON

EC_ON

D

S

2
G

[46]

PSU@
Q64
SSM3K7002FU_SC70-3

2

2

[43]

2

3

PS_ON#

470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K

v1.0 update

3

3

4

4

Compal Secret Data

Security Classification
2013/04/01

Issued Date

Deciphered Date

2014/04/01

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Sub-board Connector
Rev
0.3

ZEA00 LA-A061P M/B

Tuesday, September 24, 2013

Sheet
E

42

of

59

B

[17]
[17]
[13,41]
[13,41]
[13,41]
[13,41]
[13,41]
[13,41]

+3VALW _EC
1

2
47K_0402_5%
1
2
R545
47K_0402_5%

KSO1

R543
1

C546
0.1U_0402_16V4Z
EMI@

@ESD@ C2137
1
@ESD@ C2138
1
@ESD@ C2139
1
@ESD@ C2140
1

2

For EMC

Place closely pin 13

KSO2

0.1U_0402_16V4Z
2
CIR_IN
0.1U_0402_16V4Z
2 PW R_ON_LED
0.1U_0402_16V4Z
2 EC_SW _AD1
0.1U_0402_16V4Z
2 ON/OFF#

[13,41]
1
2 [15,21,41]
R544
[17]
47K_0402_5%
1
2
C547
0.1U_0402_16V4Z

+3VALW _EC

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

1
2
3
4
5
7
8
10

CLK_PCI_EC
PLT_RST#

CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#

12
13
37
20
38

EC_SCI#

AMP_PD#

+3VS
R549
R550
+3VALW _EC
2

R551
R553

1
1

2 2.2K_0402_5%
2 2.2K_0402_5%

EC_SMB_CK1
EC_SMB_DA1

v0.2 update
1
1

2 2.2K_0402_5%
2 2.2K_0402_5%

EC_SMB_CK2
EC_SMB_DA2

1
1

2 4.7K_0402_5%
2 4.7K_0402_5%

H_PROCHOT#_EC
PIDRST

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
DGPU_HOLD_EC#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

AMP_PD#
EC_CRISIS
KSI4
KSI5
KSI6
KSI7
EC_CRISIS_KSO0
KSO1
KSO2
KSO3

v0.2 update
[44,47]

+3VALW _EC
R554
R664

T128PAD @

PCH_EDP_BLEN
[32] EC_ENVDD
[44,47] 35V_PG
[37] CODEC_PW REN

EC_CRISIS
PIDRST

EC DEBUG port

PCH_EDP_BLEN
EC_ENVDD
35V_PG
CODEC_PW REN

Reserve R2009 for EC debug.
R556
2

[29,32]
[29,32]
[13,21,46]
[13,21,46]

E51_TXD

100K_0603_5%

[15,21]

PSU_PG#
[14]
[32]
[35]
1
@ R559

3

[29,32]

[15,23]

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

[14] PM_SLP_S3#
[14] PM_SLP_S5#
[17] 1 EC_SMI# 2
@ R557
0_0402_5%

DGPU_HOLD_RST#

S_ENVDD

SUSW ARN#
INVT_PW M
FAN_SPEED
2

@ R560

CRY1
R561 100K_0402_5%
1
2

JECDB1
1
2
3
4
5
6

1
2
3
4
5
6
GND
GND

PSU_PG#
SUSW ARN#
INVT_PW M
FAN_SPEED
S_ENVDD_R
E51_TXD
E51_RXD
PM_PW ROK
MUTE_CODEC
DGPU_PW R_EC

0_0402_5%

EC DEBUG CONNECTOR
KSO3
KSI6
KSI7
KSI4
KSI5

0_0402_5%

[40] E51_TXD
[40] E51_RXD
[14,9] PM_PW ROK
[37] CODEC_MUTE#
1
2

DGPU_PW R_EN

1
1

122
123

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

AD Input

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00

SPI Flash ROM

EC_BEEP#
FAN_PW M

63
64
65
66
75
76

EC_BEEP#
FAN_PW M

PSU_DET_AD
EC_SW _AD1

[37]
[35]

PSU_DET_AD [46]
EC_SW _AD1 [42]

AD_BID

68
70
71
72
83
84
85
86
87
88

HP_DET#

HP_DET#

EAPD_CODEC
EC_3V5V_EN
@ R552
1
VGATE_R
W L_PW RON
PW RME_CTRL#

97
98
99
109

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

GPIO
Bus

GPIO

ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07

GPI

V18R

[37]
EC_3V5V_EN

2 4.7K_0402_5%

R547 1

2 10K_0402_5%

VR_ON

R548 1

2 10K_0402_5%

1

VR_ON
[47]

2

@EMI@ C548

0.1U_0402_16V4Z

ESD request Close to EC
VGATE [14,5,50]
W L_PW RON [40]
PW RME_CTRL# [12]

ECAGND 1

R563 2
0_0402_5%
@

H_PROCHOT#_EC

119
120
126
128

PCH_SPISO_EC
PCH_SPISI_EC
PCH_SPICLK_EC
PCH_SPICS#_EC

73
74
89
90
91
92
93
95
121
127

CIR_IN
USB_ILIM_SEL
W OL_EN#
S_BKOFF#_R
BT_ON
PW R_ON_LED
SYSON#
SYSON
VR_ON
PM_SLP_S4#

100
101
102
103
104
105
106
107
108

PCH_RSMRST#
USB_CHRMODE2
VCIN1_PH
USB_CHR_EN
USB_CHRMODE1
BKOFF#
PBTN_OUT#
PCH_PW R_EN
USB_CHRMODE3

@ R644
@ R645
@ R646
@ R647

1
1
1
1

2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

PCH_SPISO [13]
PCH_SPISI [13]
PCH_SPICLK [13]
PCH_SPICS# [13]

110
112
114
115
116
117
118

CIR_IN [42]
USB_ILIM_SEL [33]
W OL_EN# [39]

2

@ R555

S_BKOFF#

[29,32]

0_0402_5%

v0.2 update

PCH_RSMRST# [14]
USB_CHRMODE2 [33]
USB_CHR_EN [33]
USB_CHRMODE1 [33]
BKOFF# [32]
PBTN_OUT# [14,5]
PCH_PW R_EN
USB_CHRMODE3 [33]

EC_ON
ON/OFF#

EC_ON
ON/OFF#

SUSP#
W L_OFF#_EC
EC_PECI_9012

124

1

BT_ON [40]
PW R_ON_LED [42]
SYSON# [33,34,44]
SYSON [48]
VR_ON [50]
PM_SLP_S4# [14]

NOTE:
Strap Pin-->Pull high
P109=VCIN0_PH
P102=VCIN1_PH
P103=VCOUT1
P104=VCOUT0_PH

[44]

[42]

[42]

SUSP# [44,45,48,49]
W L_OFF#_EC [40]
H_PECI [17,5]

1
2
C549
4.7U_0603_6.3V6K

+EC_V18R

1
H_PECI
@ESD@ C2126
PCH_RSMRST# 1
@ESD@ C2127

L43
FCM1608KF-800T07_0603
2

H_PROCHOT#

2
5P_0402_50V
2
5P_0402_50V

ESD request Close to EC

Q25

C551
47P_0402_50V8J

VCIN1_PH

4.7K_0402_5% 1

2 R564

W OL_EN#

100K_0402_5% 1

2 R565

ON/OFF#

4.7K_0402_5% 1

2 R566

CIR_IN

10K_0402_5%

1

2 R671

Compal Electronics, Inc.

Compal Secret Data
2013/04/01

Issued Date

[5]

1

S 2N7002K_SOT23-3 2

2
G

2014/04/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EC_CRISIS_KSO0

EC KB930/KB conn
Rev
0.3

ZEA00 LA-A061P M/B

@

Date:

B

C

3

+3VALW _EC

D

Security Classification

JCOMS2

2

V0.3 update for sequence EA

KB9012QF-A4_LQFP128_14X14

1

VR_HOT#
From power CPU_CORE

PIDRST

AC in-->One touch -->Power button--> Clear CMOS
Always short-->AC in-->Power button--> Crisis

A

R546 1

SUSP#

[37]

EAPD_CODEC

0_0402_5%
2 VGATE

SYSON

v0.2 update

XCLKI/GPIO5D
XCLKO/GPIO5E

1

1

SPI Device Interface

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

@

2

1
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

PS2 Interface

3

JPIDRST
1
2

1

BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43

21
23
26
27

ECAGND

[50]

EC_CRISIS

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

R542
56K_0402_5%

Rb

PWM Output

E-T_6905-E06N-00R
CONN@
Pitch 1.0mm Hight 1.9mm

4

2

ECAGND

Modify from VBA00

Reset converter
board panel ID

R540
100K_0402_5%

Ra
AD_BID

1
2
C550
20P_0402_50V8
7
8

C539
0.1U_0402_16V4Z

2

67

2

11
24
35
94
113

1

+3VALW _EC

2

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

v0.2 update for ESD
[38]

2

U35

EME(Internal PU) to aviod test mode

PLT_RST#

2

E

+EC_AVCC

1

EC_VDD/AVCC

2

2

1

AGND/AGND

1

2

1

9
22
33
96
111
125

2

EMI@

ESD request close to KB9012 pin1

2

1

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

C545
6.8P_0402_50V8C
EMI@

2
GATEA20
0.1U_0402_16V4Z

2

1

GND/GND
GND/GND
GND/GND
GND/GND
GND0

1

1
C544

1

C543
0.1U_0402_16V4Z

1

10U_0603_6.3V6M

R541
10_0402_5%
EMI@

1

C542
0.1U_0402_16V4Z

CLK_PCI_EC

D

L42
FCM1608KF-800T07_0603
1
2
+EC_AVCC

2

0_0603_5%
C536

C541
0.1U_0402_16V4Z

KSI7

C540
0.1U_0402_16V4Z

2 R539

C538
1000P_0402_50V7K

+3VSB
4.7K_0402_5% 1

C537
1000P_0402_50V7K

Place closely pin 12

C

+3VALW _EC

@R538
@R538
1

69

A

+3VALW _EC

D

Tuesday, September 24, 2013

Sheet
E

43

of

59

4

B

C

+3VALW TO +3VS
+5VALW TO +5VS

+3VALW TO +3VALW_PCH

+3VS_LS

J6

1
2
@ C579
0.022U_0402_25V7K

6
7

+5VALW
1

VOUT1
VOUT1

ON1

CT1

VBIAS

GND

ON2

CT2

VIN2
VIN2

VOUT2
VOUT2
GPAD

@ C584
1U_0603_10V6K

C575
1

12

1000P_0402_50V7K
2

2

1

W=160mils

2

3

W=160mils

1

1U_0603_10V6K

11
10

VL

+5VS_LS
2
1000P_0402_50V7K

1
C578

J7

9
8

1

2
JUMP_43X118

C582
0.1U_0402_16V7K

15

@ C576
4.7U_0603_10V6K

+5VS

@

TPS22966DPUR_SON14_2X3

1

1

2

2

@ C583
4.7U_0603_10V6K

1
D

2
G

PCH_PW R_EN

1

2

2

1

@ C577
0.1U_0402_16V4Z

R672
2

100K_0402_5%

1

Q63
3

[43]

1

v0.3 update

R591
100K_0402_5%

1

2

2

AO3415L_SOT23-3

@ C580

@ C572
4.7U_0603_10V6K

+3VALW _PCH

Q65

1

2

VIN1
VIN1

C574
0.1U_0402_16V7K

1

5

5VS_ON

JUMP_43X118
14
13

D

3
4

R589
0_0402_5%
1
2
@

SUSP#

2

3VS_ON

1

G

1

@ C573
0.01U_0402_25V7K
1
2

+3VSB

2

S

1

R587
0_0402_5%
1
2
@

U38

+3VS

@

1
1
2

E

Vgs=10V,Id=9A,Rds=18.5mohm

+3VALW
@ C571
1U_0603_10V6K

D

2

A

S

SSM3K7002FU_SC70-3

C589
0.1U_0402_16V4Z

2

+1.5V to +1.5VS
+1.5VS

8
7
6
5

9.6A

1
2
3

1

C586
4.7U_0603_10V6K

2

2

C585
1U_0402_6.3V6K

v0.3 update
R592
470_0805_5%

2
C587
4.7U_0603_10V6K

2

6

2

1
4

1

@ESD@
2 0.1U_0402_16V4Z
C2156 1

+3VALW _PCH

1

Q29
AO4354_SO8

2

+1.5V

+12VS
+5VALW
2

SUSP
2

1

Q30A
2N7002KDW H_SOT363-6
1

R595
1K_0402_5%

SUSP

1

1
330K_0402_5%

R597

C588
0.022U_0402_25V7K

Q31B

2

[43,45,48,49]

SUSP# 5

SUSP#

4

2

Q30B
2N7002KDW H_SOT363-6

4

5

SUSP

3

3

1.5VS_GATE

1

2

R596
100K_0402_5%

2N7002KDW H_SOT363-6

+1.5V

+12VS_PSU

D

D

+12VS

Q35
SSM3K7002BF 1N SC59-3
2 SYSON#
SYSON#
G

PSU@
8
D 7
D 6
D 5
D

S
S
S
G

2

U74
1
2
3
4

2
Q34
SSM3K7002BF 1N SC59-3
2
SUSP
G

1

2

R602
470_0805_5%

1
C2078
1U_0603_25V6
PSU@

AO4435_SO8

[33,34,43]

2

R650
470_0603_5%
PSU@

3

3

S

3

S

3

S

3

S

Q33
SSM3K7002BF 1N SC59-3
2
SUSP
G

D

1

Q32
SSM3K7002BF 1N SC59-3
2
SUSP
G

1

1

D

R601
470_0805_5%

2

R600
22_0805_5%

2

R599
470_0805_5%

3

+12V1 TO +12VS (Reserve for PSU)

1

1

+1.05VS_VCCIO

1

+0.75VS

1

+1.05VS_VPCH
1

Discharge circuit
3

2

R651

1

2

R652

6

20K_0402_5%
PSU@

Q60A
DMN66D0LDW -7_SOT363-6
PSU@

2

1
R604
330K_0402_5%

2

SUSP

Q60B
DMN66D0LDW -7_SOT363-6
PSU@

1

SUSP#

R603
100_0805_5%

1
C2079
0.1U_0603_25V7K
2 PSU@

1
B+

1
5

20K_0402_5%
PSU@

4

+12VS_PSU
+12VS

1

D

3

4

2

4

S

Q36
SSM3K7002BF 1N SC59-3

1

[43,47]

D

3

2
G
Q37
SSM3K7002BF 1N SC59-3
2
35V_PG
G

S

2014/04/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Add +12VALW discharge circuit for
prevent DC plug in leakage 5/5.
A

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Date:

B

C

D

DC-DC INTERFACE
ZEA00 LA-A061P M/B

Document Number

Tuesday, September 24, 2013

Sheet
E

44

Rev
0.3
of

59

5

4

3

2

1

D

D

ADA@

ADA@
1
4

BOOT

VCC

VIN

GND

SW

EN

BG

5
7

EN_12V

6

FB

12V_FB

9

ADA@
2

PR3
60.4K_0402_1%
ADA@

2

1

8

12V_LX
PC5
10U_0805_25V6K

2

PC4
10U_0805_25V6K

1

PC3
0.1U_0603_25V7K
2
1

2

+12V_B+

ADA@
PC2
1U_0603_25V6K
1
2

1

ADA@

1

12V_VCC

SUSP#

[43,44,48,49]

1

2

PR4
14K_0402_1%

3
2
1

Vo=0.8(1+Rt/Rb)=12V

ADA@

1
2

1
2

PC9
22U_1206_16V6-M

1

+12VSP
PC8
22U_1206_16V6-M

2

1

EMI@ PR102
4.7_1206_5%
2
1

ADA@

C

ADA@

PC7
22U_1206_16V6-M

4

EMI@ PC155
680P_0603_50V7K
2
1

5
6
7
8

ADA@
PL1
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
1
2

2

C

2

PR5
1K_0402_1%

ADA@
Power dissapation: 0.577W

PQ1
FDS6690AS_NL_SO8
ADA@

0_0402_5%
2

ADA@
1

12V_LG

PR2
1

@

PC10
330P_0402_50V7K

ADA@
1

JUMP_43X118

3

1

@ PJ1
2
2

B+

PU1
RT8298A_SO8
2

GND

ADA@

PC6
470P_0402_50V7K

ADA@
ADA@
PC1
PR1
0.1U_0603_25V7K
0_0603_5%
2
1 BOOT_12V_11
2

VFB=0.8V
@ PJ2
2
2

+12VSP

1

1

+12VS

JUMP_43X118

Power dissapation: 0.06W

@

PSU@

PJ12
2

ATX12V1_1

2

1

1

+12VS_PSU

JUMP_43X118
B

B

A

A

Compal Secret Data

Security Classification
2012/04/27

Issued Date

2013/04/27

Deciphered Date

Title

Compal Electronics, Inc.
PWR- 12VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

VBA11 LA-A111 M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

45

of

56

A

B

C

D

PJ3

EMI reserve

1
1

2
NC

PGOOD

FB

EN

3
4
5

PR106
60.4K_0402_1%
PSU@
FB_3VSB

1
2

10U_0805_25V6K
PC163

1
2

1

22U_0805_25V6M
PC162
2
1

B+

1

1

ADA@

PJ11
2

B+

1

1

2
1
1

1

2

EN_3VSB

GND
S IC RT9818A-44GU3

2

PR109
20K_0402_1%
PSU@
2

2

PC154
0.1U_0402_25V6K
2
1

PSU@

+3VSBP

PC148
1U_0402_6.3V6K
PSU@

PR108
13.3K_0402_1%
PSU@

PSU@

PSU@

2

PJP102

2

1
3

VDD RESET#

PC150
680P_0603_50V7K
@EMI@

1

PU101 PSU@
1

1

PSU@

1

LX

LX_3VSB

2

LX

SVIN

2

2

6

PVIN

PSU@
PL103
1UH_FDSD0630-H-1R0M-P3_11A_20%
1
2

1

PC152
22U_0805_6.3VAM

7

NC

1

8
PSU@

TP
PVIN

1

9

PC144
22U_0805_6.3VAM

2

2

11
10

PR107
10K_0402_1%

PR119
1K_0402_1%

CCM_060003HA002G202ZL
CONN@

JUMP_43X118

PC146
68P_0402_50V8J
2
1

PSU@
1

22U_0805_6.3VAM
PC151
2
1

2

@EMI@ PC145
2200P_0402_50V7K
2
1

1

1

2

@

PSU@

PSU@

JUMP_43X79

@EMI@ PC149
0.1U_0402_25V6K
2
1

2

@EMI@

PU102

@RF@
PC147
68P_0402_50V8J
2
1

PJ101

2

2

RT8061AZQW_WDFN10_3X3

2

1

JUMP_43X79

1

2

+5VALW

-

JUMP_43X118

2

ADA@

EMI@

PSU@

PJ10
2

PR105
4.7_0603_5%
@EMI@

PJ104

+

@

P2-1

[43]

EMI@

2

1

@EMI@

22U_0805_25V6M
PC161

2

@EMI@

2

+

1

1 @EMI@
0.01_2512_1%

1

+RTCBATT

VIN-

2

3

22U_1206_25VA
PC160

4

2

PC165
220U_25V_M

1
2

@

1

22U_1206_25VA
PC159

VIN+

4

1
2

PR6
8
7
6
5

ADA@ PC14
.1U_0603_25V7K

1
2
3

ADA@ PC13
.1U_0603_25V7K
2
1
PR7
200K_0402_1%
ADA@

1
2

EMI@ PC12
1000P_0402_50V7K

1
2

100P_0402_50V8J
PC17

1

JBATT1

B+

+12V2

@

PSU@

EMI@
PC16
100P_0402_50V8J

1

PR8
150K_0402_1%
ADA@

PSU_DET_AD

@
2

+5VSB

EMI@

2

1
2

2

@EMI@
22U_1206_25VA
PC164

1

@EMI@
22U_1206_25VA
PC158

2

22U_0805_25V6M
PC157

1

EMI@

EMI@ PL3
HCB2012KF-121T50_0805
1
2

1

ATX12V1_1

PC153
PR118
.1U_0402_16V7K 750_0402_1%
ADA@
2
1
2
1

ADA@

+3VSB

22U_0805_25V6M
PC156

1
2

LOTES_AJAK0031-P002A

EMI@ EMI@
1000P_0402_50V7K
PC11
2
1

1

ADA@
AO4407AL_SO8
PQ2

EMI@ PL2
HCB2012KF-121T50_0805
1
2

ATX12V1
PJP101
7
GND 6
GND 5
GROUND 4
POWER 3
DETECT 2
POWER 1
GROUND

2

@ JUMP_43X118

PC15
0.1U_0603_25V7K
ADA@

2

ATX12V1_1

4
2

ATX12V1
@
1

+3VSBP

PJ102
1

4

3

2

1

3
1

+5VSB

LOTES_APOW0009-P001C

+3VSB

2

2

JUMP_43X79
@

ADA@

PJ103
1

+3VSB

1

2

2

+3VALW

JUMP_43X79

2

@
PL5
1
2
BLM15BD121SN1D_2P

VIN-

1

2

+3VS

PS_ON#_1 1

2

PS_ON#

[43]
3

2

PC19

@
PU2
1
2
3
4

VIN+
VINGND
VS

A1
A0
SDA
SCL

8
7
6
5

VIN_A1
VIN_A0
EC_SMB_DA2
EC_SMB_CK2

@ PR104
10K_0402_1%

1

1

PC18
@

0.1U_0402_16V7K
@

3

PSU@
PR101
0_0402_5%

@
PL4
1
2
BLM15BD121SN1D_2P

0.1U_0402_16V7K

PR9
0_0402_5%
1
VIN+ 2

EC_SMB_DA1
EC_SMB_CK1

[13,21,43]
[13,21,43]

HPA00900AIDCNR_SOT23-8

2

2

+3VS

VIN_A1

PR11
0_0402_5%
1

1
2

PR10
0_0402_5%
@

2

PR12
0_0402_5%

PR13
0_0402_5%
1

4

1

VIN_A0

4

@

Current sense solution 2
Ventura for CPU side
slave address : 1000001
please placemnet near R-sense

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/01

Deciphered Date

2012/11/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PSU IN
Size
C
Date:

A

B

C

Document Number

Rev
0.1

Tuesday, September 24, 2013
D

Sheet

46

of

56

C

D

5

LG_3V

17
16

PQ5

CSP_3V
4

+3VALWP

3
2
1

RT8127GQW_WQFN28_4X4
CSN_3V

DCR=40m Ohm

@EMI@ PC31
0.1U_0402_25V6K
2
1
@RF@
PC32
68P_0402_50V8J
2
1

@EMI@ PC30
2200P_0402_50V7K
2
1

PC29
10U_0805_25V6K
2
1

PC28
10U_0805_25V6K
2
1

SIS412DN-T1-GE3_POWERPAK8-5

@

ESR=17m Ohm

PL9
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
1
2

+3VALWP

Power dissapation:1.0542W
PR23
16K_0402_1%

PC37
330U_6.3V_M

18

3
2
1

LX_3V

@EMI@ PC42
@EMI@ PR26
680P_0603_50V7K
4.7_1206_5%
2
1
2
1

19

2

5

21 UG_3V PR22
1 PR112 2 UG_3V_1
4
PC35
2.2_0603_1%
0.1U_0603_50V7K 0_0805_5%
20
1
2 BST_3V_1
1
2
BST_3V

35V_PG [43,44]

COMP_5V

PQ4

PC33
1U_0603_25V6K
2
1

PR28
2.61K_0402_1%
1
2

1

22

CSN1

FB1

COMP1

2
1
PR20
26.1K_0402_1%

23
+3VLP

24
12VLDOEN

12VLDO
15

14

PGOOD

EN1/SS1

13

12

11

8

EN2/SS2

CSP1

RT8127_12V

PR29
1.8K_0402_1%
2
1

PR16
0_0402_5%

2

2

26

25
SKIP_35V
SKIP

27
VCC

LDOEN

29

CSN2

PC38
1
2

1
+
2

2

0.047U_0402_25V7K

OCP Seting : 6.15A

SI7716ADN-T1-GE3_POWERPAK8-5

Power dissapation: 0.1623W
FB_3V
PR32
200_0402_1%
2
1

PC45
1
2
220P_0402_50V7K
PR34
27K_0402_1% PC49
2
1 1
2

2

220P_0402_50V7K
PR35
PC48
27K_0402_1%
1
2 2
1

PR36
6.04K_0402_1%
2
1

28

GND

PGND1

FB_5V
PC47
1
2

LDOBYP

LGATE1/RT

CSP2

Power dissapation: 0.2773W

PC44
PR31
2200P_0402_50V7K 200_0402_1%
1
2
2
1

PHASE1

PGND2

COMP2

7

VF=0.8V

LGATE2

FB2

5

CSN_5V

BOOT1

RT8127_12V

PC43
0.1U_0402_25V6K
1
2

OCP Seting : 7.9A

6

PHASE2

2
1
30K_0402_1%
PR30

Cap. ESR=17m

CSP_5V

VIN
UGATE1

1

Power dissapation: 0.1269W

PC25
4.7U_0603_6.3V6K
2
1

BOOT2

PC41
0.1U_0402_25V6K
1
2

0.047U_0402_25V7K

4

1
2
3

PC39
1
2

SI7716ADN-T1-GE3_POWERPAK8-5

1

PR27
4.53K_0402_1%
1
2

5
PQ6

12VLDOEN_35V
LDOEN_35V

UGATE2

9

5
1
2
3

SIS412DN-T1-GE3_POWERPAK8-5
PR100
4 UG_5V_11
2
1
UG_5V
0_0805_5% PC34
PR21
1
2 BST_5V_1
1
2 BST_5V 2
2.2_0603_1%
LX_5V 3
0.1U_0603_50V7K
LG_5V 4

@EMI@
PC40 @EMI@ PR25
680P_0603_50V7K
4.7_1206_5%
2
1
2
1

2

2

PR24
16K_0402_1%

PC36
330U_6.3V_M

2

@

DCR=17m Ohm

Power dissapation: 0.8047W
+

PU3
PQ3

PL8
2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%
1
2

+5VALWP ESR=17m Ohm

1

PC27
10U_0805_25V6K
2
1

PC26
10U_0805_25V6K
2
1

@EMI@ PC23
0.1U_0402_25V6K
2
1

Rds(ON) :Max=16.5m-ohm
Min=13.5m-ohm

@EMI@ PC24
2200P_0402_50V7K
2
1

Power dissapation: 0.2553W

EMI@ PL7
HCB1608KF-121T30_0603
2
1

@

10

EMI@ PL6
HCB1608KF-121T30_0603
2
1
@RF@ PC22
68P_0402_50V8J
2
1

B+

PR17
10K_0402_1%
2
1

1

LDOBYP_35V

RT8127_12V

2
1
PR19
10K_0402_1%

2

VL
PC21
4.7U_0603_6.3V6K
PR15
1
0_0402_5%
1

VL
1

E

VL

PR14
0_0402_5%
1
2

+5VALWP

PR18
10K_0402_1%
2
1

B

0.1U_0402_25V6K
PC20
1
2

A

COMP_3V

PC46
2200P_0402_50V7K
1
2

PR33
6.2K_0402_1%
2
1

PR38
1.15K_0402_1%
1

3

EC_3V5V_EN

PR39
0_0402_5%
1
2

1000P_0402_50V7K

Cap. ESR=17m
Rds(ON) :Max=16.5m-ohm
Min=13.5m-ohm

PR37
1.96K_0402_1%

3V5V_EN

3

1
2

EC pin must set to Open Drain
(EC GPIO spec is 5V/4mA)
Initial EC pin: Low
3V/5V on : EC pin Open
3V/5V off : EC pin Low

PC50
0.1U_0402_25V6K

1

[43]

PR103
0_0402_5%
PSU@

2

2

1

1000P_0402_50V7K

@

PJ4
+3VALWP

2

2

1

1

+3VALW

@ JUMP_43X118
PJ5

+V_5VP
Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A
Fsw=300K,
Iocp>=8.66A
Rds H/S --> typ:24 mohm ; max: 30 mohm
L/S --> typ: 13.5 mohm ; max: 16.5 mohm

+5VALWP

2

2

1

1

+5VALW

@ JUMP_43X118

TON (1)SMPS1=300KHZ (+5VALWP)
(2)SMPS2=300KHZ (+3VALWP)

4

4

+V_3.3VP
Ipeak=4.437A ; 1.2Ipeak=5.325A; Imax=3.106A
Fsw=300K
Iocp>=5.33A
Rds H/S --> typ:24 mohm ; max: 30 mohm
L/S --> typ: 13.5 mohm ; max: 16.5 mohm

Compal Secret Data

Security Classification
2012/09/01

Issued Date

2013/12/31

Deciphered Date

Title

Compal Electronics, Inc.
PWR- 3VALWP/5VALWP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
0.1

VCA00 LA-9792P M/B
Sheet

Tuesday, September 24, 2013
E

47

of

56

4

3

2

1

0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
OCP Current 0.9A

Power dissapation: 0.1096W
1.5V_B+

PR40
0_0603_5%
1
2

BST_1.5V-1
PC56
0.1U_0603_25V7K
1
2

1
2

1

PC59
10U_0805_6.3V6M

2
3
4

VTTREF_1.5V

+1.5VP

5

1

VDDQ

2

20
VTT

19
VLDOIN

18

1
VDD

Pin 5 is FB

PC62
0.033U_0402_16V7K

6

7

2

+5VSB

8

SI7716ADN-T1-GE3_POWERPAK8-5

BOOT

VTTREF

1
PC63
1U_0603_10V6K

17

VDDP

GND

2

C

PC64 @EMI@
680P_0603_50V7K

Power dissapation: 0.2484W

TON_1.5V

DCR=17m
Cap. ESR=17m
Rds(ON) :Max=16.5m-ohm
Min=13.5m-ohm

11

VDD_1.5V

+5VSB

RT8207MZQW_WQFN20_3X3

2

C

1

SNUB_+1.5VP 2

4

1
2
3

PC61
330U_6.3V_M

PR42 @EMI@
4.7_1206_5%

CS

21

@

1

FB

PR43
5.1_0603_5%
1
2

2

1

PQ8

12

PAD

VTTSNS

S3

5

PC60
1U_0603_10V6K
1
2

PU4

VTTGND

PGND

S5

13

1

2

14

PR41
10.2K_0402_1%
1
2 CS_1.5V

1
2
3

PL11
SIS412DN-T1-GE3_POWERPAK8-5
2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%
2
1

LGATE

TON

Power dissapation: 1.372W

15

PHASE

OCP SET: 7.1A

UGATE

LG_1.5V

PC57
10U_0805_6.3V6M

SW_1.5V

2
0_0805_5%

D

+0.75VSP

PQ7

4 UG_1.5V_1
1

+

+1.5VP

UG_1.5V

PR113

+1.5VP

Pin 19 is LDOVIN
BST_1.5V

16

5

2

1

PC55
10U_0805_25V6K

1
2

@ PC54
10U_0805_25V6K

1
2

@EMI@ PC53
2200P_0402_50V7K

1
2

0.1U_0402_25V6K
@EMI@ PC52

2

1

D

@RF@ PC51
68P_0402_50V8J

HCB1608KF-121T30_0603

PGOOD

2

9

EMI@ PL10
1

10

+1.5VIN

PC58
10U_0805_6.3V6M

5

[43]

SYSON

1.5V_B+

PR45
0_0402_5%
1
2

PR44
887K_0402_1%
1
2

PJ6

+1.5VP

EN_1.5V

2

2

1

1

+1.5V

@ JUMP_43X118
PJ7
1
@

1

2

2

+0.75VS

JUMP_43X79

2

1

[43,44,45,49] SUSP#

PR46
0_0402_5%
2
1

+0.75VSP

EN_0.75VSP

@ PC65
0.1U_0402_10V6K

2

1

Fsw=285K
Ipeak=11A, Imax=7.7A, Iocp=1.2*Ipeak=13.2A
Fsw= 285K Hz
Iocp(set) =13.44A~20.49A
Rds H/S --> typ:24 mohm ; max: 30 mohm
L/S --> typ: 13.5 mohm ; max: 16.5 mohm

@PC66
@
PC66
0.1U_0402_10V6K

B

B

B+

+5VSB

Level
L
L
H

+0.75VSP
off
off
on

VTTREF_1.5V
off
on
on

Note: S3 - sleep ; S5 - power off
PR308
100K_0402_1%

5
6
7
8

2

Mode
S5
S3
S0

1

PSU@

4

3
2
1

AO4407AL_SO8
PQ303
PSU@

@

+1.5VIN
1

ADA@

PJ13
B+

2

2

1

1

+1.5VIN

JUMP_43X118

PD301 PSU@
SX34_SMA2
A

2

A

+5VSB
Compal Secret Data

Security Classification
2012/09/01

Issued Date

2013/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
1.5VP
Document Number

Rev
0.1

Tuesday, September 24, 2013

Sheet
1

48

of

56

5

4

3

2

Power dissapation: 0.1053W

1

EMI@ PL12
1

+1.05V_12V

2

B+

PQ9

VFB

V5IN

TST

DRVL
TP

PR52

DH_1.05V

8

6

PL13
2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%
1
2

LX_1.05V
0_0402_5%
1 PR50
2

7

11

Power dissapation: 0.606W

DH_1.05V_1

DL_1.05V

+5VALW

PC72
1U_0402_6.3V6K

+1.05V

@EMI@
PR51
4.7_1206_5%

PQ10

PC74
330U_6.3V_M

SW

BST_1.05V

1

EN

10
9

2

DRVH

1

5

TRIP

VBST

TPS51212DSCR_SON10_3X3

4

1

1

TST_1.05V

PGOOD

SI7716ADN-T1-GE3_POWERPAK8-5

2

3
4

2

@ PC73
.1U_0402_16V7K

2

5

EN_1.05V

PR48
1
2 TRIP_1.05V
82.5K_0402_1%

PC71
0.22U_0603_25V7K
2
BST_1.05V-1 1

1

PR49
0_0402_5%
1
2

2

1
SUSP#

PR47
2.2_0603_5%
1
2
PR114
1
2
0_0805_5%

3
2
1

PU5

[43,44,45,48]

D

4

FB=0.7v

OCP SET: 7.2A

@EMI@ PC70
2200P_0402_50V7K
2
1

SIS412DN-T1-GE3_POWERPAK8-5

@EMI@ PC69
0.1U_0402_25V6K
2
1

5

D

@RF@ PC68
68P_0402_50V8J
2
1

PC67
10U_0805_25V6K
2
1

HCB1608KF-121T30_0603

2

470K_0402_5%

@EMI@
PC75

+

2

1000P_0603_50V7K

C

FB_1.05V

3
2
1

C

1

Power dissapation: 0.2643W
PR53

2

5.1K_0402_1%
2
1

Vtrip range ==> 0.2V ~ 3V

PR54
10.2K_0402_1%

1

 VFB=0.7V
V=0.7*(1+5.1K/10.1958K)=1.05V
Fsw=290KHz

+1.05V

@ PJ8
2
2

1

1

+1.05VS_VPCH

JUMP_43X118

Rds(ON) :Max=16.5m-ohm
Typ=13.5m-ohm
B

B

Ipeak=6.526A, Imax=4.568A, 1.2*Ipeak=7.831A
Iocp(set)=7.851A~11.555A

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/01

2013/12/31

Deciphered Date

Title

+1.05VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev
0.1
Sheet

Tuesday, September 24, 2013
1

49

of

56

2

3

4

Place close to
phase 1 inductir

+CPU_Vin
PC76
470P_0402_50V8J

PC77
10P_0402_50V8J

2

2

PR55
1

1

PR56
1K_0402_1%

49.9_0402_1%
1
FB

2
4.99k_0402_1%

1

PC78
PR61 1.74K_0402_1%
2
1

2

4700P_0402_25V7K

VR_HOT#
VR_SVID_DAT
VR_SVID_ALRT#
VR_SVID_CLK
VGATE
TSENSE

1

1

2

2

1

2

CSSUM

CSP3

[50,51]

CSP2

[50,51]

CSP1

[50,51]

CSN1

[50,51]

CSN2

[50,51]

CSN3

[50,51]

CSN1

[50,51]

CSP1

[50,51]

CSN2

[50,51]

CSP2

[50,51]

169K_0603_1%

PR70

B

169K_0603_1%
1

CSREF
CSN4A
CSN2A
CSP2A

2
PR73 1
10_0402_1%
PC85
1000P_0402_50V8J
65W@
2
PR75 1
10_0402_1%

CSN3
CSP3A
PU6
NCP81102MNTXG_QFN32_4x4

2
PR98 1
10_0402_1%

DRVON

[51]

PWM3
PWM1

CSN1
2

65W@
PR80
59K_0402_1%

PR81
68K_0402_1%

0.047U_0402_16V7K
PC89

1

2

2

69.8k_0402_1%
PR79

1

1

[51]

1

CSP1A

PR80

2
PR84
6.98K_0402_1%

C

35W@
65W@
1

CSN2A

2

37.4K_0402_1%
PR78
0_0402_5%

2

65W@
0.047U_0402_16V7K
PC88

1

PUT COLSE TO
VCORE HOT SPOT
PR66 @ 66.5K=108C

CSN1
CSP1A

24.9K_0402_1%

2

C

2

PWM2
[51]

100K_0402_1%_NCP15WF104F03RC

2
1

PH2

1
2

PR77
66.5K_0402_1%

1
VGATE

169K_0603_1%
1

65W@
PR68

1

2

[51]
PR76
10K_0402_1%

1

Switching Frequency
PR110 @ 24.9K=320KHZ

TSENSE

VGATE

24
23
22
21
20
19
18
17

PR99
2

PR110

+3VS

[14,43,5]

2.2U_0603_6.3V6K

9
10
11
12
13
14
15
16

VR_SVID_DAT
VR_SVID_ALRT#
VR_SVID_CLK

VR_SVID_DAT
VR_SVID_ALRT#
VR_SVID_CLK

PC86

2

2

1

PC84
0.1U_0402_25V6K

2
1

1
2
75_0402_1%
PR72

PR71
130_0402_1%
2
1
[8]
[8]
[8]

PR74
54.9_0402_1%

CSCOMP
CSSUM
CSREF
CSN4
CSP4
CSN2
CSP2
CSN3

2

2

ENABLE
VCC
VR_HOT
SDIO
ALERT
SCLK
VR_RDY
TSENSE

PC87
0.1U_0402_25V6K

1
2_0402_1%

@

1
2
3
4
5
6
7
8

PR69

+5VS

CSCOMP

32
31
30
29
28
27
26
25

33
EPAD

B

+1.05VS_VCCIO

390P_0402_50V7K
PR65
2

9.31K_0402_1%
35W@

VSP
VSN
DIFFOUT
FB
COMP
VRMP
IOUT
ILIM

VR_ON

1

1

VCC_SENSE_1
PR66
0_0402_5%
1
2

VR_HOT#

VR_HOT#

65W@

2
14.7K_0402_1%

ILIM

[43]

1

Iout_A

PC79

PR67

VCC_SENSE

PR65

2

PR63

[8]

PC80
1000P_0402_50V8J

2

26.7K_0402_1%
PC81

PWM4 / ROSC
PWM2 / VBOOT
PWM3 / IMAX
PWM1 / ADDR
DRON
CSP1
CSN1
CSP3

[43]

75_0402_1%

1

2

PR64
0_0402_5%
1
2

PR62
1

VSS_SENSE_1

2

1

1

+1.05VS_VCCIO

1

2

VSS_SENSE

2
0.01U_0402_50V7K

PC82
1200P_0402_50V7K

[8]

1

PR59 75K_0402_1%
2
1

+CPU_Vin1

PR60
0_0402_5%
1
2

A

COMP

DIFFOUT

1

2

PR58
2

PR57 1K_0402_1%

PC83
390P_0402_50V7K
1
2

2

1

1

220K_0402_5%_ERTJ0EV224J
2
PH1

1

A

5

165K_0402_1%

1

ASM for 3Phase opration

65W@
1

CSP2A

2
PR83
6.98K_0402_1%

ASM for 2Phase opration

+5VS

+5VS
CSN3

[50,51]

CSP3

[50,51]

CSN4A

2

0.047U_0402_16V7K
PC137

1

1

PR111
2K_0402_1%
35W@

1

2

2

CSN3
PR82
2K_0402_1%

CSN2A

CSP3A

1

2
PR93
6.98K_0402_1%

D

D

Title

NCP81102
Size
Date:
1

2

3

4

Document Number
VCA00 LA-9792P M/B

Rev
0.1

Tuesday, September 24, 2013
5

Sheet

50

of

56

1

[50]

[50,51]
DRVON
PWM3

1

PR94

+5VS
2
1
0_0402_5%
3

4
PWM

EN

VCC
SW

DRVL
GND

5

6

LG3
PQ17

PC143
2.2U_0603_6.3V6K
4

2

PQ19

4
2
3

3

+CPU_CORE

CSN3
[50]

CSP3
[50]

1

4

1

2

1

Size

Date:

@

PC124
22U_0805_6.3V6M

1

1

1
PC118
22U_0805_6.3V6M

2

+

2

2

PC117
22U_0805_6.3V6M

2

PC130
22U_0805_6.3V6M

1

1

PC109
560U_2.5V_M

1

2

PC123
22U_0805_6.3V6M

2

PC116
22U_0805_6.3V6M

10U_0805_25V6K

PC105
2
1

10U_0805_25V6K

1

2

1

1
PC115
22U_0805_6.3V6M

2

2

+

1

2

PC122
22U_0805_6.3V6M

1

PC108
560U_2.5V_M

2

1
PC121
22U_0805_6.3V6M

2

2

PC114
22U_0805_6.3V6M

PC103
2
1
10U_0805_25V6K
PC104
2
1

1

PC129
22U_0805_6.3V6M

1

+

PC128
22U_0805_6.3V6M

2

PC120
22U_0805_6.3V6M

1

2

PC127
22U_0805_6.3V6M

2

+CPU_Vin

2

2

[50]
PC113
22U_0805_6.3V6M

CSP2

PC107
560U_2.5V_M

@

PC136
22U_0805_6.3V6M

4

2

+

1

1

[50]

1

2

PL18
0.36UH_FDU1040J-H-R36M=P3_33A_20%

CSN2

PC106
560U_2.5V_M

PC126
22U_0805_6.3V6M

1

3

PC119
22U_0805_6.3V6M

+

1

SW3

1

2

7
2
0_0805_5%
4

2

1
2
3

5

1

1

1

1
EMI@ PC99
1000P_0402_50V7K

2

EMI@ PC98
100P_0402_50V8J

2

EMI@ PC97
100P_0402_50V8J

2

EMI@ PC96
1000P_0402_50V7K

2

2
1
1
2
@EMI@ PR88
@EMI@ PC95
4.7_1206_5%
1000P_0603_50V7K

SIRA06DP-T1-GE_POWERPAKSO-8-5

[50]

PC135
22U_0805_6.3V6M

PR95

65W@
LOTES_APOW0008-P001C

1

HG3 1

CSP1

[50]

2

8

CSN1

PC134
22U_0805_6.3V6M

4

1

1
+

2

Tuesday, September 24, 2013
5

2

+
PC101
100U_25V_M

5

2

PC90
1

PC92
1
10U_0805_25V6K

2

10U_0805_25V6K

10U_0805_25V6K
PC91
2
1

4

PC100
100U_25V_M

HG1_1

SIR472DP-T1-GE3_POWERPAK8-5

3
2
1

+CPU_CORE

PC133
22U_0805_6.3V6M

PQ18

65W@
PL17
0.36UH_FDU1040J-H-R36M=P3_33A_20%

PJP103
1
1 2
2 3
3 4
4

1

BST3_1

1

65W@
PC111
2.2U_0603_6.3V6K
4

3

2

4

2

PC125
22U_0805_6.3V6M

LG2
PQ16
65W@

10U_0805_25V6K

PQ15
65W@

65W@
4

2

PU9
NCP81151MNTBG_DFN8_2X2
9
FLAG
SW2

2
1
1
2
@EMI@ PR92
@EMI@ PC112
4.7_1206_5%
1000P_0603_50V7K

65W@

PC140
2
1

5
4

SIRA06DP-T1-GE_POWERPAKSO-8-5

65W@
PR89
2.2_0603_1%

10U_0805_25V6K

6
2
0_0805_5%

4
+12V2

1

1

PC138
0.22U_0603_25V7K
65W@

PL15
0.36UH_FDU1040J-H-R36M=P3_33A_20%

2

DRVH
2

PR97
2.2_0603_1%
1
2
65W@
PR90

3

PC132
22U_0805_6.3V6M

2
BST
DRVL
7
PQ14
65W@
SIR472DP-T1-GE3_POWERPAK8-5

4
SIRA06DP-T1-GE_POWERPAKSO-8-5

PC94

1

1
SW
BST2_1
5

2.2U_0603_6.3V6K

PQ13

2

C

VCC
GND
HG2 1

5

2

PC131
22U_0805_6.3V6M

BST3
EN

PQ12

5

PC102
65W@
0.22U_0603_25V7K
PU8
NCP81151MNTBG_DFN8_2X2
9
FLAG
1
8
BST
DRVH

LG1

10U_0805_25V6K
PC139
2
1

4
PWM

5

PC142
2
1

3
2

6

2
0_0805_5%

1
2
3

2

GND

PR86

2
1
1
2
@EMI@ PR96
@EMI@ PC141
4.7_1206_5%
1000P_0603_50V7K

+5VS
1

DRVL

SW1

SIRA06DP-T1-GE_POWERPAKSO-8-5

PR91
2
1
0_0402_5%
VCC

4

SIR472DP-T1-GE3_POWERPAK8-5

BST2

EN

3
2
1

4

HG1 1

SIRA06DP-T1-GE_POWERPAKSO-8-5

1
2
3

2

PQ11

5

PWM2
3

BST1_1

1
2
3

B

DRVON
PR87
2
1
0_0402_5%
7

HG2_1

+5VS

5

[50]
DRVON
SW

5

A

PWM

3
2
1

1
2
3

[50,51]
2

1

PU7
NCP81151MNTBG_DFN8_2X2
9
FLAG
1
8
BST
DRVH

HG3_1

2

1

PC93
0.22U_0603_25V7K

1

2

[50,51]
PWM1

2

5

2

1

[50]

BST1 1

1

2

EN resistor:
NCP81151@ 0 R
NCP5911@ 4K

SIRA06DP-T1-GE_POWERPAKSO-8-5

1
2
3

2

1

PR85
2.2_0603_1%

+CPU_Vin
5

HCB2012KF-121T50_0805
EMI@ PL14
1
2

HCB2012KF-121T50_0805
EMI@ PL16
1
2
+CPU_Vin
A

1@

+CPU_Vin
+CPU_CORE

1

+CPU_CORE
2

PC110
560U_2.5V_M

+CPU_CORE
B

C

D
D

Title
Document Number
VCA00 LA-9792P M/B

Power Stage

Sheet
51
of
56
Rev
0.1

5

4

3

2

1

EMI@DIS@
PL403
HCB1608KF-121T30_0603
2
1
EMI@DIS@
PL401
HCB1608KF-121T30_0603
2
1

+GPU_CORE_VIN

1

GPU_UGATE1

DIS@
PR427
10K_0402_1%

2
0_0805_5%

4

GPU_UGATE1_1

3
2
1

2

D

DIS@
DIS@
PR405
PC407
2.2_0603_5%
0.22U_0603_25V7K
1
2 GPU_BOOT1_1
2
1

BOOT1

1

21

5

1
2
SNUB_GPU1

2

DIS@
PC417
560U_2.5V_M

@EMI@
PC411
680P_0603_50V7K

1

GPU_UGATE2

2
GPU_UGATE2_1

4

1

3
2
1

2
0_0805_5%

SIR472DP-T1-GE3_POWERPAK8-5

5

@
PQ404
PR117

@

+VGA_CORE
@
PL404
0.36UH_FDU1040J-H-R36M=P3_33A_20%

N14P-GE2
Ipeak=
Imax=
Iocp=

4

4

2

3
B

2

1

1
@EMI@
PR423
4.7_1206_5%

1

5

5
4

@
PQ406

@EMI@
PC418
680P_0603_50V7K

2

GPU_LGATE2

@
PQ405

1
2
3

GPU_BOOT2

@
@
PR426
PC423
2.2_0603_5%
0.22U_0603_25V7K
1
2 GPU_BOOT2_1 2
1

SIRA06DP-T1-GE_POWERPAKSO-8-5

GPU_LX2

[17,23]

SIRA06DP-T1-GE_POWERPAKSO-8-5

+5VALW

PC421
10U_0805_25V6K
2
1

GPU_EN

1
DIS@
+
PC410
560U_2.5V_M

+GPU_CORE_VIN

@

DGPU_PWROK

2

+3VS

+
2

19

RT8813AGQW_WQFN24_4X4

DIS@ PR424
2.2_0402_1%
2
1

DIS@
PR425
10K_0402_1%
1
2

1

0_0402_5%
2 PR415 1

GPU_PVCC

1
2
3

B

DIS@
PC409
560U_2.5V_M

+5VALW

PR421
4.7K_0402_1%
DIS@

1

PH701 close to MOSFET
Trigger point 110 degree

+

20

+3VS

DIS@ PC420
0.1U_0402_25V6K

VGA_VCC_SENSE

DIS@ PH401
100K_0402_1%_NCP15WF104F03RC
1
2
DIS@
PR420
3.92K_0402_1%
2
1
2
1

[22]

DIS@

2

2

1

GPU_VREF

+VGA_CORE

1

@ PC422
10U_0805_25V6K
2
1

BOOT2
18

16
GPU_PGOOD

PHASE2

22

DIS@
PC414
4.7U_0603_10V6K

DIS@ PC425
1U_0402_16V6K

PR419
0_0402_5%

3

24
23

2

UGATE1

EN

15
GPU_DSBL/ISEN1

UGATE2

LAGTE2
PGOOD

@
PR418
82K_0402_1%
1
2

PVCC

17

SS

4

2

1

GPU_PSI

3

2

GPU_VID

4

GND/PWM3

RGND

GND

@
PC419
100P_0402_50V8J
1
2 GPU_FB2

TON

25

PR417
0_0402_5%
1
2
DIS@

@

LGATE1

VSNS

1

C

PHASE1

VREF

VCC/ISNE1

10

11
GPU_FB
@ PC416 10P_0402_50V8J
@PC416
1
2
GPU_COMP12

DIS@
PR413
10K_0402_1%
1
2

2

1

9

GPU_TON
GPU_FBRTN

@
PC415
@
PR416
47P_0402_50V8J
51_0402_1%
1
2 GPU_FB1
1
2

REFIN

14

2

PC401
1000P_0402_50V7K

2

8

GPU_VREF

DIS@ PR422
499K_0402_1%
2
1

13

+GPU_CORE_VIN

0_0402_5%
PR401

7

TSNS/ISEN3

GPU_REFIN

GPU_TSNS/ISEN3

1

For RT8813

PSI

GPU_REFADJ
PU401

6

@
PR414
57.6K_0402_1%
2
1
C

5

VGA_VSS_SENSE

GPU_TALERT/ISEN2

[22]

VID

DIS@ PC412
1800P_0402_50V7K
1
2
DIS@ PC413
0.01U_0402_50V7K
1
2

D

@EMI@
PR407
4.7_1206_5%

1

1
2
3

OCP setting in 47A
GPU_BOOT1

4

1
2
3

1
2

DIS@
PR410
3K_0402_1%

REFADJ

DIS@
PR412
24K_0402_1%
2
1

TALERT/ISEN2

DIS@
PR411
3K_0402_1%
1
2

4

1

2

DIS@
PR409
39K_0402_1%
1
2

@ PC408
0.1U_0402_25V6K

GPU_LGATE1

DIS@
PR408
30K_0402_1%
2
GPU_VREF 1

DIS@
PQ403

SIRA06DP-T1-GE_POWERPAKSO-8-5

+3VS_VGA

5

DIS@
PQ402

SIRA06DP-T1-GE_POWERPAKSO-8-5

DIS@ PR406
4.7K_0402_1%
1
2

@

DIS@
PL402
0.36UH_FDU1040J-H-R36M=P3_33A_20%
GPU_LX1

Design for
N14M-GE2

+12V2

PC406
10U_0805_25V6K
2
1

PR115

DIS@ PC405
10U_0805_25V6K
2
1

[21]

@EMI@ PC404
2200P_0402_50V7K
2
1

NVVDD_PSI

@RF@ PC402
68P_0402_50V8J
2
1

SIR472DP-T1-GE3_POWERPAK8-5

DIS@
PQ401
DIS@

0_0402_5%
1 PR404 2

2

0_0402_5%
1 PR403 2

GPU_PWM_VID

1

[21]

+GPU_CORE_VIN

5

1

PSI pull up on HW site
DIS@
PR402
10K_0402_1%

@EMI@ PC403
0.1U_0402_25V6K
2
1

+3VS

Follow GB4-128 demand

1

2

DIS@
PC441
22U_0805_6.3V6M

1
2

PC440
DIS@
47U_0805_6.3V6M

DIS@
PC438
4.7U_0603_6.3V6K

DIS@
PC437
4.7U_0603_6.3V6K
2
1

PlaceNear GPU
DIS@
PC436
4.7U_0603_6.3V6K
2
1

DIS@
PC435
4.7U_0603_6.3V6K
2
1

DIS@
PC434
4.7U_0603_6.3V6K
2
1

DIS@
PC433
4.7U_0603_6.3V6K
2
1

DIS@
PC432
4.7U_0603_6.3V6K
2
1

DIS@
PC431
4.7U_0603_6.3V6K
2
1

DIS@
PC430
4.7U_0603_6.3V6K
2
1

1
2

DIS@
PC429
4.7U_0603_6.3V6K
2
1

+VGA_CORE

Place Under GPU

+VGA_CORE

DIS@
PC451
4.7U_0805_6.3V6K

DIS@
PC450
4.7U_0805_6.3V6K
2
1

DIS@
PC449
4.7U_0805_6.3V6K
2
1

DIS@
PC448
4.7U_0805_6.3V6K
2
1

1
2

DIS@
PC447
4.7U_0805_6.3V6K
2
1

DIS@
PC446
0.1U_0402_10V7K

DIS@
PC445
0.1U_0402_10V7K
2
1

DIS@
PC444
0.1U_0402_10V7K
2
1

2

1

A

DIS@
PC443
0.1U_0402_10V7K
2
1

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/11/14

Issued Date

Deciphered Date

2013/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

PWR_VGA_CORE/VGA_PCIE
Document Number

Rev
0.1

Tripoli
Tuesday, September 24, 2013
1

Sheet

52

of

56

A

B

C

D

EMI@DIS@
PL20
HCB1608KF-121T30_0603
1
2

Power dissapation: 0.0978W

DIS@

RF

DRVL
TP

7
6
11

DIS@
PQ22

1

4

1

TPS51212DSCR_SON10_3X3

LG_V1.5V
PC206
1U_0402_6.3V6K
DIS@

DIS@ PL21
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
1
2

PR143
470K_0402_1%
DIS@

3
2
1

SI7716ADN-T1-GE3_POW ERPAK8-5

2

2

PR144

1
+
2

+VRAM_1.5VSP

DIS@ PC207
330U_2.5V_M

V5IN

Power dissapation: 1.0786W

1

VFB

8

1

SIS412DN-T1-GE3_POW ERPAK8-5

2

5

SW

DIS@
UG_V1.5V 1 PR116 2 UG_V1.5V_1
0_0805_5%
SW _V1.5V
0_0402_5%
1 PR140 2
+5VALW

PR142
4.7_1206_5%
@EMI@

4

EN

9

2

1

FB_V1.5V
@
PC205
.1U_0402_16V7K

DRVH

2

2

@
PR141
10K_0402_1%

3

TRIP

10

PC208
1000P_0603_50V7K
@EMI@

EN_V1.5V

2

TRIP_V1.5V

VBST

1

DGPU_PW ROK

1
2
78.7K_0402_1%

1

[15,23,43]

PR139
0_0402_5%
1
2

PGOOD

4

2.2_0603_5%
0.22U_0603_25V7K

PU10 DIS@
1

PR138

2

DIS@

PC204
1
2

3
2
1

OCP SET:6.3A

PR137 2

5

DIS@
1

BST_V1.5V

+12V2

@EMI@ PC203
2200P_0402_50V7K

1
2

0.1U_0402_25V6K
@EMI@ PC202
2
1

1
2

DIS@
PQ21

@RF@ PC201
68P_0402_50V8J

5

1

@ PC200
10U_0805_25V6K
2
1

DIS@ PC199
10U_0805_25V6K
2
1

+VRAM_12V

2

PR145

10K_0402_1%
1
2

1

DIS@

2
11.5K_0402_1%

Power dissapation: 0.1985W

DIS@

+VRAM_1.5VSP

Cap. ESR=17m
Rds(ON) :Max=15m-ohm
Typ=12m-ohm
Vtrip range ==> 0.2V ~ 3V
 VFB=0.7V
V=0.7*(1+11.5K/10K)=1.505V
Fsw=290KHz

@ PJ9
2
2

1

1

+1.5VS_VGA

JUMP_43X118

3

3

Ipeak=4.7A, Imax=3.29A, Iocp=1.2*Ipeak=5.64A
Iocp(set)=5.718A~8.304A

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/09/01

Deciphered Date

2013/12/31

Title

PWR-VRAM_1.5VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.1

VCA00 LA-9792P M/B

Date:

A

B

C

Tuesday, September 24, 2013
D

Sheet

53

of

56

5

4

3

3.3V
5.13A

+V_3.3VP

RT8127

5V
6.55A

+V_5VP
D

TPS51212

1.05V
6A

+1.05V

RT8207M

2

1

PCH, GPU, Codec, Card reader,
LAN, WLAN, LVDS, TV Tuner, WebCam
Codec, Toch Screen, Panel,
HDD, ODD, USB Port, stereo
D

PCH, GPU

+1.5VP

1.5V
5.9A

CPU, PCH, DDR, TV Tuner

+0.75VSP

0.75V
0.75A

DDR

Adaptor(19V)
120W/90W
C

RT8298

12V
2.58A

+12V

+CPU_CORE

NCP81102

TPS51212

+VRAM_1.5VSP

C

HDD, Fan

1.8V
75A peak for 65W CPU, 48A peak for 35W CPU

1.5V
5.23A

B

B

RT8813

+VGA_CORE

1.0V
38.69A

A

A

2011/09/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/09/12

Deciphered Date

Title

Power Rail

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.4

QLA13/15 LA-8501P M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

55

of

59

5

4

3

2

1

Clock and Reset Diagram
Channel A
DDR3-SO-DIMM
Channel B
DDR3-SO-DIMM

D

H_PWRGOOD

100MHz

CLK_DP_DP

DDRB_CLK[0..1]
SM_DRAMRST#

CLK_PCIE_VGA

CLK_PCIE_LAN

100MHz

PLT_A_RST#

A

PWRGOOD

Nvidia
N14M-GE2

DDRA_CLK[0..1]
SM_DRAMRST#

C

RESET#

27MHz

CPU_PLTRST#

C

100MHz

CLK_CPU_DMI

Intel CPU
Haswell
LGA1150
37.5mm x 37.5mm

LAN

100MHz

PLT_A_RST#

Realtek

Audio Codec
ALC-272-VA4

AZ_BITCLK_HD
24MHz

AZ_RST_HD#

B

CLK_PCI_EC

KBC
PCI_RST#

33.3MHz

PLT_RST#

WLAN/BT

100MHz

PLT_A_RST#

KB_RST#

On Mini Card

B

CLK_TV
100MHz

TV Tuner

PLT_A_RST#

On Mini Card

A

PLT_RST#

G20IN

RT5229

CLK_WLAN

A_RST#

GATEA20

ENE KB9012-A3

8111G

Card Reader

100MHz

PCH
LynxPoint
H81
FCBGA-708
23mm x 22mm

25MHz

Realtek

PLT_A_RST#

CLK_CR

eDP to LVDS
RTD2136R

D

KBRST#

PCH_RSMRST#
PM_PWROK
VGATE

25MHz

RSMRST#
PWR_GOOD
RTC

32.768KHz

A

A

2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2014/04/01

Deciphered Date

Title

Clock/Reset Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.3

VIA15 LA-A071P M/B

Date:

5

4

3

2

Sheet

Tuesday, September 24, 2013
1

56

of

59

5

4

3

2

1

PLT_RST#

PWR BTN

Power Button
D

PLT_RST#

ON/OFF

NVIDIA
MXM

VRAM

PLT_RST_VGA#

PEX_RST_N

D

ECRST#

RC
delay

H
DRAMPWROK
1.5VS

VGATE

AP4800
MOS

PIN 107

B

PIN 106

E
SUSP#

+0.75VSP(+0.75VS)
RT8207MZQW
+1.5VP(+1.5V)

PIN 116
PIN 2

D

PWM

+3V_SCA_R

PIN 100

SYSON

SCALER_ON

AP2301
MOS

PIN 95

PROCPWRGD
PWROK
APWROK

PBTN_OUT#

RC
delay
PCH_PLT_RST#

GPIO7

EC_SMI#

GPIO8

GATEA20

A20GATE

C

PM_SLP_S5#
PM_SLP_S4#

PIN 110

PM_SLP_S3#

PIN 6

AZ_RST_HD#
ALC892 Codec

PWM

PLTRST#

RCIN#

EC_SCI#

PIN 14

RT8243BZQW

B

PLTRST_PROC#

RSMRST#

KB_RST#

Slot 2 Mini Card
WLAN
PLT_A_RST#

PWRBTN#

PCH_RSMRST#

B

A
+5VALW

PM_PWROK

RTL8111F-CGT
PCIE Gold Finger

DRAMPWROK

PIN 109

DC-IN

+3VALW

PIN 15
PIN 1

B+

A

PIN 20

SYS_PWROK

RTS5229 Card reader

SRTCRST#

PIN 37

RC
delay

SM_DRAMRST#

PWM

C

PCH_SRTCRST#

TPS51212DSCR

PCH_RTCRST#

+1.05VCCIOP

PLT_RST#

RTCRST#

LDO

UNCOREPWRGOOD

SCALER_ON

RT8299

CACTUS-RIDGE
Thunder bolt

PM_SYNC

+12VSP

CPU_PLTRST#

RESET#

H_PM_SYNC

C

EC
KB9012QF-A3

DGPU_HOLD_RST#
(PCH GPIO50)

Intel
Haswell
(desktop)

PMSYNC

MOS

PIN 89

PROCPWRGD

WOL_EN

AQ3413

DDR3 SO-DIMM

SSM3K7002FU
+3.3V_LAN

SM_DRAMPWROK

PWM

PM_DRAM_PWRGD_R

PIN121
PIN 97

H_PWRGOOD

VGATE

SM_DRAMRST#

NCP6131S52MNR2G

VGA_PWROK
(PCH GPIO17)

PIN 13

VR_ON
+CPU_CORE

PIN 114

FBA_RST#

G

PLT_RST#

PCH
H87

(desktop)

GPIO52

SLP_S5#
SLP_S4#

GPIO54

SLP_S3#
HDA_SDO

GPIO50

DGPU_PWR_EN

F

2013/04/01

Issued Date

Deciphered Date

A

DGPU_HOLD_RST#

Compal Electronics, Inc.

Compal Secret Data

Security Classification

MXM

2014/04/01

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Reset Diagram
Rev
0.3

VCA00 LA-9791P M/B

Date:

5

4

3

2

Sheet

Tuesday, September 24, 2013
1

57

of

59

5

4

3

2

1

NO
DATE
PAGE
MODIFICATION LIST
PURPOSE
-----------------------------------------------------------------------------------------------------------------------------------------1.
20130604
P47
Add PC154 and Change the pu101 to SA00005A600
For Pericom issue
2.
20130729
P45
Add PR105 ,PC155 Snaber
For EMI Request
3.
20130729
P45
Add PR1
For EMI Request
3.
20130729
P45
Add PR39
For S5 power loss issue

D

D

C

C

B

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/09/12

2012/09/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PWR_PIR
Size
Document Number
Custom

4

3

2

Rev
0.5

B555 VAA15 LA-A072P MB

Date:
5

Sheet

Tuesday, September 24, 2013
1

57

of

61

5

4

3

2

1

COMPAL CONFIDENTIAL
D

MODEL NAME:
PCB NAME:
REVISION:
DATE:

ZEA00 Power Sequence Block Diagram (Discrete)
LA-A061P
0.1
Adaptor
2013/04/01

Reserve For PSU

+5VSB
PS_ON#

+5VSB

E

PSU

PSU_PG

11PM_PWROK

+3VSB

PU102

PSU_PG
PSU_PG#

2 F
PU3

ATX12V1_1

EC

35V_PG

+12V2

PBTN_OUT#
PM_SLP_S3#

7

PM_SLP_S5#

6

PCH

13 DRAMPWROK

U1

14

PJ11

B+

+5VALW

D

+3VALW

CPU
JCPU1

16 +CPU_CORE

PJ10

C

H_PWRGOOD

19 CPU_PLTRST#

U35

+5VALWP
+3VALWP

ATX12V1_1

C

5

B+

12

18 SYS_PWROK

4 PCH_RSMRST#
B EC_ON#

PJP101
PSU Conn

B

PS_ON#

D

C

PU8

PU7

PJP901

PU9

15

+12V2

+3VSB

1

PU6

10

A

+5VSB/B+ PU4

SYSON

+1.5VP(+1.5V)/
+0.75VP(+0.75VS)
For DDR

+CPU_CORE

VGATE

VR_ON

ON/OFF#

ON/OFFBTN#

VR_SVID_DAT
VR_SVID_ALRT#
VR_SVID_CLK

17

8
SUSP# 9

DGPU_PWROK

Q29
+1.5VS

20
PCH_PWR_EN

B

+1.5V

3

B

+3VALW

U38
+5VS

+12V2

+3VSB

PU10

GPU_PWM_VID

+12V2

+5VALW

+3VALW_PCH

+VRAM_1.5VSP
(+1.5VS_VGA)

21

U37
U38
+3VS

PU401
+VGA_CORE

ATX12V1_1 U74
(+12VS_PSU)
+12VS

A

A

Reserve For PSU
2013/04/01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2014/04/01

Deciphered Date

Title

Power Sequence Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
0.3

ZEA00 LA-A061P M/B

Date:

5

4

3

2

Tuesday, September 24, 2013

Sheet
1

58

of

59

5

4

3

2

1

HW PIR (Product Improve Record)
ZEA00 LA-A061P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 --> 0.2
GERBER-OUT DATE: 2013/06/20

D

NO
DATE
PAGE
MODIFICATION LIST
PURPOSE
---------------------------------------------------------------------------------------------------------------------------------------1. Change C45 from SF000002V00 to SF000003X00
2. Change +LCDVDD enable control from EC to LVDS convertor,un-pop R367 and R365 change short pad.
3. Change LCD_BKOFF# control from EC to LVDS convertor,un-pop R364 and R363 change 0 ohm.
4. Remove un-used components(U18,R335,R336,C357,C359,C360,R338,R339) for eDP to LVDS convertor.
5. Pop R428 for AZ_SDIN0_HD.
6. U2 footprint change from socket to IC.
7. Add RH11
8. Change Y2 from SJ10000CU00 to SJ10000DE00,change C106 & C107 from 27pF to 4.7pF
9. Change R423 location to L45
10. Change D7 from SC2N202U010 to SC600000B00 for
11. Change Q29 from SB548000210 to SB00000ZN00.
12. Change D8&D9 from SCS00002G00 to SCS00000Z00
13. X1 code change:1.Change Q2,Q3,Q4,Q5,Q30,Q31 from SB01000JE00 to SB00000EO00. 2.Change Q9 from SB934130020 to SB934130000.
3.Change Q10 from SB00000FC00 to SB00000F400. 4.Change L1 from SM01000JE00 to SB01000JN00.
14. Change R551 & R553 pull-high from +3VS to +3VALW_PCH for leakage.
15. Add R677 & R678 & R679 for PTC request, Change R473,R490,R679,R677,R678 from 0ohm to PTC(SP040005X00).
16. Change Q10 from SB00000FC00 to SB00000L800 for
17. Remove R469 0ohm for TV.
18. Add C2134 ,C2135,C2136,C2137,C2138,C2139,C2140,C2141,C2143 for ESD.
19. Remove JXDP1,OC1,OC2,RC3,RC4,R125,R126.
20. Pop U7&R231, un-pop R228 for PLT_RST_VGA#.
21. Swap SATA_PRX_DTX_N1 & SATA_PRX_DTX_P1 for m-SATA pin define.
22. Un-pop LAN power components Q26,Q27,R573,R574,C562.
23.0 ohm change to short pad: R347,R585,R507,R674,R644,R645,R646,R647
24.Change R453&R457 from 0ohm to 1.1K, R451&R459 from 300ohm to 5.6Kohm.
25.Pop R438,R439 for ESD request.

D

替替替

替替替

C

C

同

B

需需需

PVT change list:
1. Change Q10 from SB00000FC00(EOL soon) to SB00000ZN00( Q29),SB00000FC00 as 2nd source.Schematic,
2. Change U23 pin12_+USB3_VCCA to +USB3_VCCB, pop U22, un-pop U24 for USB charger
3. R365 change from short pad to 0ohm.
4. U5 pin5 change from +3VSto +3VALW_PCH for BCM43142 wake from WLAN issue.
5. Change R473,R490,R677,R678,R679 from SP040005X00_0603 size to F1,F2,F4,F5,F3 SP040003S00_1206 size.
6. Change L11 from SM010014520 to SM01000EJ00 for ACL request
7. Change L8 from SM010007W00 to SM010019400 for ACL request
8. Change D7 from SC2N202U010 to SC600000B00(same as D1/D2), SC2N202U010 as 2nd source..
9. Change RP19 from SD309510A80(T88 P/N) to SD309510A10.
11. Change R276 from 10k to 100k for +3VS_VGA rise time.
12. Change R672 from 10k to 100k for +3VALW_PCH rise time.
14. Change R438 & R439 from 0_0603 to short pad.
15. Un-pop C125 & C548 for sequence EA.
16. Change C394, C398,C520 & C514 from 220uF(LELON_SF000001F00) to 100uF (Panasonic_SF000005100) to meet Inrush EA & ACL request.
17. Change C170 & C171 from 12pF to 10pF for EA.
20. Change C106 & C107 from 4.7pF to 10pF for 25MHz crystal.
21. Add R677 & reserve R678 on U5 AND gate for PLT_A_RST#
13. Change JUSB1 & JUSB2 from DC23300AE00 to DC233008R00(VBA11)
24. Change R591 pull-high from +5VSB to VL for power S5 Erp request.
22. Change D20 & D21 from SC300001Y00 to SC300002F00 for ESD request
23. Change D22 & D23 from SCA00001100 to SCA00000T00 for ESD ACL request
10. Add C2144~C2152 for EMI request.
18. Change R402 from short pad to 22ohm for EMI, R399,R401,R403 & R404 change from short pad to 0 ohm for EMI request.
19. Reserve C2153,C2154,C2155,C2156, add D29 for ESD.
20. Change R282 from 100k to 2k, R277 from 470 to 22 ohm for GPU power sequence.
21. Change Y1 from SJ100001K00 to SJ10000FA00 ,C102 & C107 to 6pF.

B

pre-MP change list:
1. Change R399,R401,R402,R403,R404 from 0ohm to short pad.
2. Add C2157 and reserve C2158.
3. Change R8,R470,R669,R670,R416 from 0ohm to short pad.
4. Un-pop JECDB1 & SW1.
5. For R3 P/N, change PCH P/N from SA00006RF00 to SA00006RF20, PCB P/N from DA60011S000 to DA60011S010 and GPU P/N from SA00006ZF00 to SA00006ZF10.
6. Change C520 & C514 from 100uF to 220uF.
7. Pop C2149~C2152 for ESD request.
8. Change C559 & C2128 from 0603 to 0805.
9. Change C2145 from 0.1uF to 470pF, change C2149~C2152 from 330pF to 470pF for EMI.
10. Add C418 for EMI.

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/01

Issued Date

Deciphered Date

2014/04/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

HW-PIR
Size

Document Number

Rev
0.3

VCA00 LA-9791P M/B
Date:

Tuesday, September 24, 2013

Sheet
1

59

of

59

www.s-manuals.com



---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.6
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39
Create Date                     : 2013:09:24 12:09:03
Modify Date                     : 2015:10:28 22:02:33+02:00
Creator Tool                    : PScript5.dll Version 5.2.2
Metadata Date                   : 2015:10:28 22:02:33+02:00
Producer                        : GPL Ghostscript 8.15
Format                          : application/pdf
Title                           : Compal LA-A061P - Schematics. www.s-manuals.com.
Creator                         : 
Subject                         : Compal LA-A061P - Schematics. www.s-manuals.com.
PXC Viewer Info                 : PDF-XChange Viewer;2.5.201.0;Jan 23 2012;21:08:47;D:20131112072001+01'00'
Document ID                     : uuid:9479e00b-63e2-43a9-bda0-d379ca0b3bf4
Instance ID                     : uuid:c13fab9c-0ae1-471b-b60e-5a690db7271b
Has XFA                         : No
Page Count                      : 60
Keywords                        : Compal, LA-A061P, -, Schematics., www.s-manuals.com.
Warning                         : [Minor] Ignored duplicate Info dictionary

EXIF Metadata provided by EXIF.tools