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User Manual: Motherboard Compal LA-A972P Goliad MLK 12 UMA ENTRY - Schematics. Free.
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A
B
C
D
E
COMPAL CONFIDENTIAL
1
MODEL NAME : Goliad MLK 12 UMA ENTRY
LA-A972P
PCB NO :
BOM P/N : 4319RK31LXX
1
GPIO MAP: 3.3b
Goliad MLK 12" UMA ENTRY
2
2
Broadwell U Processor
2013-12-23
REV : 0.2 (X01)
@ : Nopop Component
EMC@ : EMI, ESD and RF Component
@EMC@ : EMI, ESD and RF Nopop Component
CXDP@ : XDP Component
CONN@ : Connector Component
VPRO@ : Vpro Component
NVPRO@ : Non-Vpro Component
3
Layout Dell logo
4
3
COPYRIGHT 2013
ALL RIGHT RESERVED
REV: X01
PWB: FGFC2
DATE: 1352-01
4
MB PCB
Part Number
Description
DA8000ZB000
PCB 14A LA-A972P REV0 MB W/O DOCKING 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Title
Cover Sheet
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
E
Rev
0.1
1
of
48
A
B
C
D
E
Reverse Type
Goliad MLK 12 UMA Entry Block Diagram
DDR3L-DIMM X2
BANK 0, 1, 2, 3
Memory BUS (DDR3L)
Trough eDP Cable
PAGE 18 19
1333/1600MHz
LCD Touch
USB2.0[4]
1
eDP CONN
Camera
PAGE 23
USB POWER SHARE
DDI2
mDP CONN
PAGE 33
PAGE 24
BROADWELL ULT
Parade
PS8339
WIGIG_DP
PAGE 23
TPS2544
USB2.0[0]
INTEL
1
PAGE 23
USB2.0[5]
Dual Lane eDP1.3
USB3.0[1]
USB3.0/2.0+PS
USB2.0[3]
USB3.0[4]
USB3.0/2.0
PAGE 31
USB
PAGE 31
DDI1
PAGE 25
USB2.0[1]
USB3.0/2.0
USB3.0[2]
PAGE 32
2
HDMI CONN
PAGE 24
PAGE 6~17
Card reader
SD4.0
O2 Micro OZ777FJ2LN
PAGE 29
PAGE 29
HD Audio I/F
INT.Speaker
PAGE 21
PCIE1
SATA1
HDA Codec
ALC3234
SPI
PCI Express BUS
Universal Jack
PAGE 21
PAGE 21
W25Q64CVSSIQ
LPC
PCIE3
PCIE5_L0 PCIE4
Trough eDP Cable
Dig. MIC
64M 4K sector
W25Q32BVSSIQ
32M 4K sector
3
2
HDMI
Intel Clarkville
I218LM
SMSC SIO
ECE1099
WLAN/BT/
WIGIG
PAGE 28
PAGE 30
WIGIG_DP
PAGE 28
SIM+HALL/B
USH CONN
PAGE 35
3
PAGE 27
PAGE 27
CPU XDP Port
PAGE 9
KB/TP CONN
BC BUS
SMSC KBC
MEC5085
Automatic Power
Switch (APS)PAGE 9
PAGE 37
PAGE 36
RJ45
LID switch
Full Mini Card
mSATAPAGE 20
Discrete TPM
AT97SC3205
USB2.0[2]
Transformer
PAGE 7
FAN CONN
PAGE 36
PAGE 28
DC/DC Interface
PAGE 38
4
Smart Card
RFID
Power On/Off
SW & LED PAGE 39
USH
BCM5882
TDA8034HN
DELL CONFIDENTIAL/PROPRIETARY
Fingerprint
CONN
FP_USB
Compal Electronics, Inc.
USB2.0[6]
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
PAGE 27 USH board
A
B
C
D
Title
Block diagram
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
E
Rev
0.1
2
of
48
4
5
4
3
2
1
POWER STATES
SLP
S3#
Signal
State
D
C
SLP
S4#
SLP
S5#
SLP
A#
ALWAYS
PLANE
M
PLANE
SUS
PLANE
RUN
PLANE
PCIE
CLOCKS
S0 (Full ON) / M0
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
ON
S3 (Suspend to RAM) / M3
LOW
HIGH
HIGH
HIGH
ON
ON
ON
OFF
OFF
S4 (Suspend to DISK) / M3
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
OFF
S5 (SOFT OFF) / M3
LOW
LOW
LOW
HIGH
ON
ON
OFF
OFF
OFF
S3 (Suspend to RAM) / M-OFF
LOW
HIGH
HIGH
LOW
ON
OFF
ON
OFF
OFF
S4 (Suspend to DISK) / M-OFF
LOW
LOW
HIGH
LOW
ON
OFF
OFF
OFF
OFF
S5 (SOFT OFF) / M-OFF
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
OFF
USB3.0
power
plane
+5V_ALW
+3.3V_SUS
+5V_RUN
+3.3V_M
+1.35V_MEM
+3.3V_RUN
+1.05V_M
+3.3V_ALW_PCH
+0.675V_DDR_VTT
+3.3V_RTC_LDO
+1.05V_RUN
DESTINATION
JUSB1-->Rear left
USB3.0 2
JUSB3-->Right
PCIE 1
USB3.0 3
MMI (CARD READER)
PCIE 2
USB3.0 4
JUSB2-->Rear Right
PCIE 3
D
LOM
PCIE 4
WLAN - JNGFF1
PCIE 5
WiGig - JNGFF1
PCIE 6
PM TABLE
+3.3V_ALW
SATA
USB3.0 1
+3.3V_M
+1.05V_M
(M-OFF)
SATA 3
NA
SATA 2
NA
SATA 1
JMINI3
SATA 0
NA
C
+VCC_CORE
DESTINATION
USB PORT#
State
B
S0
ON
ON
ON
ON
ON
S3
ON
ON
OFF
ON
OFF
S5 S4/AC
ON
OFF
OFF
ON
OFF
S5 S4/AC doesn't exist
OFF
OFF
OFF
OFF
OFF
BDW
ULT
USH
0
JUSB1
1
JUSB3
2
WLAN + BT
3
JUSB2
4
Touch Screen
5
CAMERA
6
USH
7
WWAN
0
BIO
1
NA
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Port assignment
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
3
of
40
5
4
3
2
RUN_ON
1
MPHYP_PWR_EN
TPS22966
(UZ2)
SI3456
(QZ6)
D
D
EN_INVPWR
ADAPTER
FDC654P
(QV1)
+BL_PWR_SRC
+1.05V_RUN
A_ON
BATTERY
SY8208
(PU300)
+1.05V_MODPHY
+1.05V_M
+PWR_SRC
ALWON
TPS51285
(PU100)
+5V_ALW
C
C
CHARGER
TPS22966
(UZ3)
APL3512
(UV24)
TPS22965
(UZ11)
RUN_ON
RUN_ON
3.3V_HDD_EN
EN_LCDPWR
PCH_ALW_ON
SIO_SLP_LAN#
A_ON
TPS22966
(UZ2)
TPS22966
(UZ9)
USB_PWR_EN1#
TPS2544
(UI3)
USB_PWR_EN2#
G547I2P81U
(UI1)
G547I2P81U
(UI2)
+0.675V_DDR_VTT
+3.3V_SUS
+3.3V_M
+3.3V_LAN
+3.3V_WLAN
+LCDVDD
+3.3V_RUN
+5V_RUN
+5V_USB_CHG_PWR
+USB_SIDE_PWR
+USB_RIGHT_PWR
3.3V_CAM_EN#
+1.35V_MEM
0.675V_DDR_VTT_ON
+VCC_CORE
TPS22966
(UZ8)
USB_PWR_SHR_EN#
B
SUS_ON
B
RT8207
(PU200)
H_VR_EN
ISL95813
(PU501)
AUX_EN_WOWL
SUS_ON
+3.3V_ALW
+3.3V_ALW_PCH
+3.3V_HDD
LP2301ALT1G
(QZ1)
A
+3.3V_CAM
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Power rails
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
4
of
40
5
4
3
2
2.2K
SMBUS Address [0x9a]
+3.3V_ALW_PCH
2.2K
AP2
MEM_SMBCLK
AH1
MEM_SMBDATA
1
2.2K
2.2K
+3.3V_RUN
4 202
200
2N7002
DIMMA
2N7002
1K
BDW
D
202
+3.3V_ALW_PCH
1K
AN1
AH3
AU3
AK1
SML1_SMBCLK
3A
SML0DATA
31
LOM
53
SML1_SMBDATA
A5
28
D
DIMMB
200
SML0CLK
2.2K
XDP
51
2.2K
+3.3V_ALW_PCH
B6
2.2K
3A
2.2K
B4
DOCK_SMB_CLK
A3
DOCK_SMB_DAT
1A
1A
+3.3V_ALW
2.2K
C
C
2.2K
1B
B5
LCD_SMBCLK
A4
LCD_SMDATA
+3.3V_ALW
1B
2.2K
KBC
2.2K
1C
A56
PBAT_SMBCLK
1C
B59
PBAT_SMBDAT
+3.3V_ALW
7
100 ohm
6
100 ohm
BATTERY
CONN
2.2K
2.2K
A50
1E
MEC 5085
B53
1E
+3.3V_SUS
M9
USH_SMBCLK
L9
USH_SMBDAT
USH
B
B
2.2K
2.2K
2B
A49
CARD_SMBCLK
2B
B52
CARD_SMBDAT
B50
CHARGER_SMBCLK
+3.3V_ALW
10K
10K
1G
A47
1G
+3.3V_ALW
9
8
CHARGER_SMBDAT
Charger
2.2K
2.2K
2D
B7
A
2D
A7
+3.3V_ALW
BAY_SMBDAT
A
BAY_SMBCLK
2.2K
2.2K
2A
2A
5
B48
B49
GPU_SMBDAT
DELL CONFIDENTIAL/PROPRIETARY
+3.3V_ALW
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
GPU_SMBCLK
4
3
2
Title
SMbus Block diagram
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
5
of
40
5
4
3
UMA SATA port
Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the entire region of the SPI flash to be updated using FPT.
D
+3.3V_ALW_PCH
ME_FWP_EC 2
@ RC301
1 ME_FWP
0_0402_5%
PT, ST pop RC2 & SW1; MP pop RC301.
1
2
1
ME_FWP
RC1
330K_0402_5%
2
1
2
3
4
5
ME_FWP_EC
SATA1
E-Dock
mSATA G12 UMA
NA
mSATA G12 Entry
E-Dock
mSATA G14 DSC
NA
SW1
<36>
SATA0
E-Dock
RC2
1K_0402_5%
+RTC_CELL
2
A
B
C
G1
G2
NA
HDD
PCB
1
SATA2/PCIE6 L1 SATA3/PCIE6 L0
G14 UMA
M2 3042
2nd PCIe Lane for PCIe Cache
G14U_En
NA
D
SATA2/PCIE6_L1 contact to WWAN
M2 3030 WIGIG SATA3/PCIE6 L0 contact to WLAN
M2 3042
2nd PCIe Lane for PCIe Cache
NA
contact to WWAN
NA
M2 3042
SATA-Cache(no HCA)
mSATA G14D_En
HDD
M2 3042
(HCA & SATA-Cache)
NA
M2 3042
(HCA & SATA-Cache)
contact to WWAN
M2 3030 WIGIG contact to WLAN
NA
SS3-CMFTQR9_3P
ME_FWP PCH has internal 20K PD.
FLASH DESCRIPTOR SECURITY OVERRIDE
PCH_INTVRMEN
LOW = ENABLE (DEFAULT)
-->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
CC1
1
INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
High - Enable Internal VRs
Low - Enable External VRs
2
1
PCH_RTCX1_R
2
0_0402_5%
@ RC4
PCH_RTCX1
YC1
32.768KHZ_12.5PF_9H03220008
2
2
1
1
12P_0402_50V8J
RC7
10M_0402_5%
C
C
UC1E
BDW_ULT_DDR3L
CC2
1
1
2
RC9
PCH_RTCX2
12P_0402_50V8J
INTRUDER#
PCH_INTVRMEN
SRTCRST#
PCH_RTCRST#
1M_0402_5%
2
2 20K_0402_5%
20K_0402_5%
1
RC10 1
RC8
+RTC_CELL
2
<9>
1
1
CC3
1
@
CMOS1
1
CC4
2
1U_0402_6.3V6K
2
B
TPM setting
<21>
PCH_AZ_CODEC_SDIN0
ME_FWP 1
RC11
Clear ME RTC Registers
Shunt
Clear CMOS
Open
Keep ME RTC Registers
Open
Keep CMOS
<9> PCH_JTAG_TRST#
<9> PCH_JTAG_TCK
<9> PCH_JTAG_TDI
<9> PCH_JTAG_TDO
<9> PCH_JTAG_TMS
+1.05V_M
RPC21
8
7
6
5
@ RC300
PCH_JTAG_TDI
PCH_JTAG_TMS
PCH_JTAG_TDO
+1.05V_M
1
2
1
@
2
RC21
1
2
PCH_AZ_SDOUT
1K_0402_5%
AW8
AV11
AU8
AY10
AU12
AU11
AW10
AV10
AY8
PCH_JTAG_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_JTAGX
AU62
AE62
AD61
AE61
AD62
AL11
AC4
AE63
AV2
HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_RST/I2S_MCLK
AUDIO
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
HDA_DOCK_EN/I2S1_TXD
HDA_DOCK_RST/I2S1_SFRM
I2S1_SCLK
SATA
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
PCH_TRST
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
RSVD
RSVD
JTAGX
RSVD
JTAG
SATA_IREF
RSVD
RSVD
SATA_RCOMP
SATALED
J5
H5
B15
A15
for DOCK
J8
H8
A17
B17
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
SATA HDD
for PCIe Cache (WWAN)
F5
E5
C17
D17
V1
U1
V6
AC1
A12
L11
K10
C12
U3
for SATA-CACHE (WWAN)
MPCIE_RST#
HDD_DET# <20>
SATA2_PCIE6_L1
<12>
mCARD_PCIE#_SATA_R
B
<36,7>
+PCH_ASATA3PLL
SATA_COMP
SATA_ACT#
SATA_ACT#
+3.3V_RUN
<39>
RPC18
5
6
7
8
MPCIE_RST#
HDD_DET#
<29,7>
<10>
@ CC100
1U_0402_6.3V6K
MMICLK_REQ#
DGPU_PWROK
4
3
2
1
10K_8P4R_5%
BDW-ULT-DDR3L_BGA1168
5 OF 19
PCH_JTAG_TCK
51_0402_5%
<20>
<20>
<20>
<20>
J6
H6
B14
C15
2
PCH_JTAG_JTAGX
1K_0402_1%
1
2
PCH_AZ_BITCLK
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
PM_TEST_RST
<9>
10K_0402_5%
51_0804_8P4R_5%
@ RC18
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
CMOS setting
Shunt
1
2
3
4
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
RTC
2
SHORT PADS~D
2
1U_0402_6.3V6K
CMOS_CLR1
RTCX1
RTCX2
INTRUDER
INTVRMEN
SRTCRST
RTCRST
PCH_RTCRST#
CMOS place near DIMM
ME_CLR1
AW5
AY5
AU6
AV7
AV6
AU7
SATA Impedance Compensation
+PCH_ASATA3PLL
1
SATA_COMP
3.01K_0402_1%
HDA for Codec
A
<21>
<21>
PCH_AZ_CODEC_SDOUT
1
2
1
2
RC19
PCH_AZ_CODEC_SYNC
RC20
1
PCH_AZ_CODEC_RST#
RC22
1 EMC@
PCH_AZ_CODEC_BITCLK
RC23
PCH_AZ_SDOUT
33_0402_5%
PCH_AZ_SYNC
33_0402_5%
2
PCH_AZ_RST#
33_0402_5%
2
PCH_AZ_BITCLK
33_0402_5%
A
CC5
@EMC@
27P_0402_50V8J
1
<21>
2
<21>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Reserve for EMI
5
2
RC17
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
4
3
2
Title
CPU (1/12)
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
6
of
48
5
4
3
2
1
+3.3V_RUN
+3.3V_ALW_PCH
BDW_ULT_DDR3L
<27>
AA3
Y7
Y4
AC2
AA2
AA4
Y6
AF1
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_CS2#
PCH_SPI_DO
PCH_SPI_DIN
PCH_SPI_DO2
PCH_SPI_DO3
PCH_SPI_CLK
D
<27> PCH_SPI_CS2#
<27> PCH_SPI_DO
<27> PCH_SPI_DIN
LPC
SMBUS
SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
SPI
AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3
SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SML0CLK
SML0DATA
SML1ALERT/PCHHOT/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74
C-LINK
<11>
PCH_GPIO73 <12>
SML1_SMBCLK <36>
SML1_SMBDATA <36>
SML1_SMBCLK
SML1_SMBDATA
PCH_CL_CLK1
PCH_CL_DATA1
PCH_CL_RST1#
RPC14
6
MEM_SMBCLK
SML0_SMBCLK
SML0_SMBDATA
AF2
AD2
AF4
CL_CLK
CL_DATA
CL_RST
PCH_SMB_ALERT#
MEM_SMBCLK
MEM_SMBDATA
2
LAD0
LAD1
LAD2
LAD3
LFRAME
1
DDR_XDP_WAN_SMBCLK
4
DDR_XDP_WAN_SMBDAT
<18,19,9>
SML0_SMBCLK
499_0402_1%
SML0_SMBDATA
499_0402_1%
QC1B
DMN66D0LDW-7_SOT363-6
SML0_SMBCLK
2
1
2
1
@ RC30
SML0_SMBDATA
LAN_SMBCLK
0_0402_5%
<28>
LAN_SMBDATA
0_0402_5%
BDW-ULT-DDR3L_BGA1168
7 OF 19
1
64Mb Flash ROM
1
SPI_PCH_CS0#
2
@RC35
@
RC35
0_0402_5%
RPC11
2
1
2
1
2
1
2
1
1
@EMC@
@EMC@
CC10
RC62
33P_0402_50V8J
33_0402_5%
@EMC@
@EMC@
CC9
RC61
33P_0402_50V8J
33_0402_5%
C
SPI_PCH_DIN 1
SPI_PCH_DO 2
SPI_PCH_CLK 3
SPI_PCH_DO3 4
RC29
1
RC31
2 SPI_PCH_DO2
1K_0402_5%
2 SPI_PCH_DO3
1K_0402_5%
8
7
6
5
1
2
1
RC33
D
RC34
+3.3V_RUN
1
RN3
1
RN4
CC6
2
0.1U_0402_25V6
UC2
SOFTWARE TAA
+3.3V_SPI
2
DDR_XDP_WAN_SMBDAT 2
2.2K_0402_5%
DDR_XDP_WAN_SMBCLK 2
2.2K_0402_5%
<28>
+3.3V_SPI
SPI_CLK64
8
7
6
5
2.2K_0804_8P4R_5%
MEM_SMBDATA 3
PCH_CL_CLK1 <30>
PCH_CL_DATA1 <30>
PCH_CL_RST1# <30>
@ RC32
SPI_CLK32
1
2
3
4
SML1_SMBDATA
SML1_SMBCLK
MEM_SMBCLK
MEM_SMBDATA
<18,19,9>
QC1A
DMN66D0LDW-7_SOT363-6
5
UC1G
AU14
AW12
AY12
AW11
AV12
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
<20,36> LPC_LAD0
<20,36> LPC_LAD1
<20,36> LPC_LAD2
<20,36> LPC_LAD3
<20,36> LPC_LFRAME#
1
2
3
4
SPI_PCH_CS0#_R
SPI_DIN64
SPI_PCH_DO2_64
SPI_DIN64
SPI_DO64
SPI_CLK64
SPI_PCH_DO3_64
/CS
DO(IO1)
/WP(IO2)
GND
8
7
6
5
VCC
/HOLD(IO3)
CLK
DI(IO0)
SPI_PCH_DO3_64
SPI_CLK64
SPI_DO64
W25Q64FVSSIQ_SO8
+3.3V_SPI
33_0804_8P4R_5%
SPI_PCH_DO2 1
RC38
2 SPI_PCH_DO2_64
33_0402_5%
1
32Mb Flash ROM
CC7 VPRO@
2
0.1U_0402_25V6
UC3 VPRO@
SPI_PCH_CS1#
RC50 1
2 0_0402_5%
VPRO@
SPI_PCH_DO3 1
SPI_PCH_CLK 2
SPI_PCH_DO 3
SPI_PCH_DIN 4
RPC12 VPRO@
8 SPI_PCH_DO3_32
7 SPI_CLK32
6 SPI_DO32
5 SPI_DIN32
1
2
3
4
SPI_PCH_CS1#_R
SPI_DIN32
SPI_PCH_DO2_32
/CS
DO/IO1
/WP/IO2
GND
VCC
/HOLD/IO3
CLK
DI/IO0
8
7
6
5
SPI_PCH_DO3_32
SPI_CLK32
SPI_DO32
W25Q32FVSSIQ_SO8
C
33_0804_8P4R_5%
CC8
2
2 SPI_PCH_DO2_32
33_0402_5%
1
MMI --->
<29> CLK_PCIE_MMI#
<29> CLK_PCIE_MMI
<29,6> MMICLK_REQ#
+3.3V_RUN
+3.3V_RUN
10/100/1G LAN --->
RPC6
4
3
2
1
5
6
7
8
LANCLK_REQ#
CONTACTLESS_DET#
<10,27>
mCARD_PCIE#_SATA_R
PCH_GPIO16 <12>
10K_8P4R_5%
WLAN (NGFF1)--->
RC66 1
B41
A41
PCH_GPIO19 Y5
2 10K_0402_5%
<28> CLK_PCIE_LAN#
<28> CLK_PCIE_LAN
<28> LANCLK_REQ#
<30> CLK_PCIE_WLAN#
<30> CLK_PCIE_WLAN
<12,30> WLANCLK_REQ#
LANCLK_REQ#
C41
B42
AD1
WLANCLK_REQ#
B38
C37
N1
WIGIGCLK_REQ#
A39
B39
U5
<36,6>
WGIG (NGFF1)--->
<30> CLK_PCIE_WIGIG#
<30> CLK_PCIE_WIGIG
<12,30> WIGIGCLK_REQ#
HCA/PCIe cache (NGFF2)--->
B
C43
C42
U2
MMICLK_REQ#
+3.3V_RUN
RC68
1
B37
A37
2 10K_0402_5% PCH_GPIO23
T2
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18
XTAL24_IN
XTAL24_OUT
RSVD
RSVD
DIFFCLK_BIASREF
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20
SIGNALS
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
PCIE1
G12 UMA SD card
PCIE2 PCIE3 PCIE4
NA
LOM
WLAN
PCIE5
WIGIG
PCIE6
M2 3042
(HCA & SATA-Cache)
G12 Entry SD card
NA
LOM
WLAN
WIGIG
NA
G14 DSC SD card
NA
LOM
WLAN
GPU
WIGIG
G14 UMA SD card
NA
LOM
WLAN
WIGIG
M2 3042
(HCA & SATA-Cache)
G14D_En SD card
NA
LOM
WLAN
GPU
WIGIG
PCI_CLK_LPC_0 EMC@
RC74 1
2 22_0402_5%
PCI_CLK_LPC_1 EMC@
RC67 1
2 22_0402_5%
1
CLK_BIASREF
C35
C34
AK8
AL8
MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4
AN15
AP15
PCI_CLK_LPC_0
PCI_CLK_LPC_1
15P_0402_50V8J
+PCH_VCCACLKPLL
NA
LOM
WLAN
WIGIG
1
CLK_BIASREF
3.01K_0402_1%
2
1
1
1
1
2
2
2
2
MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4
B35
A35
from CPU
CLK_PCI_MEC
<36>
PCH_SPI_CS1#
RC240
RC241
RC242
RC243
RC69
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
CLK_PCI_LPDEBUG
<20,36>
PCH_SPI_DIN
PCH_SPI_CLK
2
CLK_PCI_MEC
12P_0402_50V8J
1
@EMC@
CC12
PCH_SPI_CS0#
2
1
@EMC@
CC13
PCH_SPI_DO3
PCH_SPI_DO2
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
2
RC231
1
0_0402_5%
+3.3V_SPI
+3.3V_M
Reserve for EMI
support SPI TPM support LPC TPM
to SPI ROM
2
RC224
2
RC225
2
RC226
2
RC227
2
RC228
2
RC229
2
RC230
JSPI1
1
2 1
3 2
SPI_PCH_DO
4 3
5 4
SPI_PCH_DIN
6 5
7 6
SPI_PCH_CLK
8 7
SPI_PCH_CS0# 9 8
10 9
SPI_PCH_DO2 11 10
12 11
SPI_PCH_DO3 13 12
14 13
15 14
16 15
17 16
18 17
19 18
20 19
20
SPI_PCH_CS1#
Please place RC224~RC331 with JSPI1 at the same MB side.
G14U_En SD card
CC11
2
1
2 XTAL24_OUT_R
0_0402_5%
@ RC65
K21
M21
C26
B
PCH_SPI_DO
CLK_PCI_LPDEBUG
12P_0402_50V8J
XTAL24_IN
XTAL24_OUT
YC2
24MHZ_12PF_X3G024000DC1H
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
BDW-ULT-DDR3L_BGA1168
6 OF 19
PCB
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLOCK
A25
B25
15P_0402_50V8J
3
4
BDW_ULT_DDR3L
UC1F
RC63
1M_0402_5%
2
VPRO@
PCIECLK for UMA
1
1
2
SPI_PCH_DO2 1
RC55
4
LPC_0
LPC_1
SIO
DOCK
MEC
DEBUG
LPC_0
CLKBUFF
6
SIO
8
MEC
10
TPM
LPC_1
DOCK
DEBUG
12
14
16
18
20
G1
G2
G3
G4
NA
A
2
21
22
23
24
A
E-T_6700K-Y20N-00L
CONN@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (2/12)
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
7
of
48
5
4
D
UC1C
<18>
DDR_A_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
C
B
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
3
BDW_ULT_DDR3L
<19>
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
DDR CHANNEL A
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
AU37
AV37
AW36
AY36
M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#1
M_CLK_DDR1
AU43
AW43
AY42
AY43
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
AP33
AR32
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
2
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
<18>
<18>
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
<18>
<18>
AP32
AY34
AW34
AU34
DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#
AU35
AV35
AY41
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
AP49
AR51
AP51
DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#
<18>
<18>
<18>
DDR_A_BS0 <18>
DDR_A_BS1 <18>
DDR_A_BS2 <18>
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
UC1D
DDR_B_D[0..63]
M_CLK_DDR#0 <18>
M_CLK_DDR0 <18>
M_CLK_DDR#1 <18>
M_CLK_DDR1 <18>
<18>
<18>
<18>
+SM_VREF_CA
+SM_VREF_DQ0
+SM_VREF_DQ1
BDW-ULT-DDR3L_BGA1168
3 OF 19
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
1
D
BDW_ULT_DDR3L
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
DDR CHANNEL B
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3
AY49
AU50
AW49
AV50
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
AM32
AK32
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_CLK_DDR#2 <19>
M_CLK_DDR2 <19>
M_CLK_DDR#3 <19>
M_CLK_DDR3 <19>
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
<19>
<19>
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
<19>
<19>
AL32
AM35
AK35
AM33
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
AL35
AM36
AU49
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
<19>
<19>
<19>
DDR_B_BS0 <19>
DDR_B_BS1 <19>
DDR_B_BS2 <19>
DDR_B_MA[0..15]
<19>
C
DDR_B_DQS#[0..7]
<19>
DDR_B_DQS[0..7]
<19>
B
BDW-ULT-DDR3L_BGA1168
4 OF 19
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (3/12)
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
8
of
48
5
4
3
1
@ RC77
2
1
2 0_0402_5%
+3.3V_RUN
5
O
PCH_PLTRST#_EC
<20,27,30,36>
<36>
PM_APWROK
@ RC304
100K_0402_5%
2 PM_APWROK_L
0_0402_5%
2
B
1
1.05V_M_PWRGD
PM_APWROK_R
UC6
TC7SH08FU_SSOP5~D
2
0_0402_5%
@ RC27
1
<43>
+PCH_VCCDSW3_3
+RTC_CELL
4
O
A
3
PM_APWROK 1
@ RC26
1
2
2
A
UC5
TC7SH08FU_SSOP5~D
SIO_SLP_A#
P
O
@ UC4
74AHC1G09GW_TSSOP5
P
A
4 PCH_PLTRST#_EC
G
2
B
1
1 ME_RESET#
8.2K_0402_5%
SYS_RESET#
2
1
@ RC82
2
@ RC80
4
G
1
RC81
3
RC79
B
1
D
RC78
330K_0402_5%
ME_SUS_PWR_ACK
10K_0402_5%
2 SUSACK#
10K_0402_5%
2 SUS_STAT#/LPCPD#
10K_0402_5%
PCH_PLTRST#
3
2
P
1
G
1
XDP_DBRESET#
5
+3.3V_ALW2
5
+3.3V_RUN
+3.3V_ALW_PCH
D
DSWODVREN
RPC1
4
3
2
1
5
6
7
8
10K_8P4R_5%
1
2
@ RC92
Fix Intel 7260 can not detect issue.
It will cause “floating” situation before 3V_RUN coming of AND gate
PCH_PCIE_WAKE#
AC_PRESENT
<36,9>
PCH_BATLOW#
PM_LANPHY_ENABLE
10K_0402_5%
<9>
PM_LANPHY_ENABLE
<27>
<29>
<28>
<12,28>
@ RC87 1
@ RC88 1
@ RC89 1
PLTRST_USH#
PLTRST_MMI#
PLTRST_LAN#
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
DSWODVREN - ON DIE DSW VR ENABLE
PCH_PLTRST#
HIGH = ENABLED (DEFAULT)
LOW = DISABLED
1
2
RC91
PCH_RSMRST#_Q
47K_0402_5%
UC1H
BDW_ULT_DDR3L
SYSTEM POWER MANAGEMENT
<36>
+3.3V_RUN
<36>
<15,36>
PM_APWROK_R
PCH_PLTRST#
<37> PCH_RSMRST#_Q
<36> ME_SUS_PWR_ACK
<36> SIO_PWRBTN#
<36,9> AC_PRESENT
<9> PCH_BATLOW#
<35>
SIO_SLP_WLAN#
PCH_RSMRST#_Q
ME_SUS_PWR_ACK
SIO_PWRBTN#
AC_PRESENT
PCH_BATLOW#
SIO_SLP_S0#
SIO_SLP_WLAN#
AW6
AV4
AL7
AJ8
AN4
AF3
AM5
+3.3V_RUN
C
2
SUSACK
SYS_RESET
SYS_PWROK
PCH_PWROK
APWROK
PLTRST
DSWVRMEN
DPWROK
WAKE
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
PWRBTN
ACPRESENT/GPIO31
BATLOW/GPIO72
SLP_S0
SLP_WLAN/GPIO29
UC7 CXDP@
14
2
1
2 TDI_XDP_R
0_0402_5%
5
4
RUNPWROK
<6>
PCH_JTAG_TMS
PCH_JTAG_TMS
12
TRST#_XDP
RUNPWROK
9
10
RUNPWROK
<36>
1A
1B
3
CPU_XDP_TDO
6
CPU_XDP_TDI
13
RUNPWROK
1OE
2A
2B
3A
8
3B
CPU_XDP_TMS
Place near JXDP1
<13>
<13>
CFG0
CFG1
<13>
<13>
CFG2
CFG3
4A
11
4B
4OE
RC5 need to close to JCPU1
<15>
15
H_VCCST_PWRGD
CFG2
CFG3
XDP_OBS0_R
XDP_OBS1_R
CPU_XDP_TRST#
7
GND
CFG0
CFG1
<13>
<13>
CFG4
CFG5
CFG4
CFG5
CFG6
<13> CFG6
2 1K_0402_5%
RC102 1
CFG7
<13> CFG7
CXDP@
2 1K_0402_5%
H_CPUPWRGD @ RC103 1
H_VCCST_PWRGD_XDP
SIO_PWRBTN#
74CBTLV3126BQ_DHVQFN14_2P5X3
PCH_JTAG_TRST#
2
0_0402_5%
1
CPU_XDP_TRST#
RC109 CXDP@
<15>
<6>
PCH_JTAG_JTAGX
2
0_0402_5%
1
CPU_XDP_TCLK
RC112 CXDP@
CPU_PWR_DEBUG#
<18,19,7> DDR_XDP_WAN_SMBDAT
<18,19,7> DDR_XDP_WAN_SMBCLK
<6> PCH_JTAG_TCK
SYS_PWROK
CPU_XDP_TCLK
H_CATERR#
49.9_0402_1%
2
H_PROCHOT#
62_0402_5%
1
1
2
@EMC@
CC83
100P_0402_50V8J
RC123
10K_0402_5%
2
PECI_EC
1
RC121
2
H_PROCHOT#_R
56_0402_5%
H_CPUPWRGD
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
<18>
DDR3_DRAMRST#_CPU
<18> DDR_PG_CTRL
A
D61
K61
N62
K63
C61
AU60
AV60
AU61
AV15
AV61
PROC_DETECT
CATERR
PECI
PROCHOT
PROCPWRGD
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1
C
CFG8
CFG9
CFG10
CFG11
CFG10
CFG11
<13>
<13>
CFG19
CFG18
CFG19
CFG18
<13>
<13>
CFG12
CFG13
CFG12
CFG13
<13>
<13>
CFG14
CFG15
CFG14
CFG15
<13>
<13>
TDO_XDP
TRST#_XDP
PCH_JTAG_TDI
PCH_JTAG_TMS
1
CFG3_R
RC113
CXDP@
<13>
<13>
<13>
<13>
2
RC106
CXDP@
1
PCH_PLTRST#_EC
1K_0402_5%
2
CFG3
1K_0402_5%
+1.05V_RUN
1
B
@
RC117
Place near JXDP1.48
XDP_DBRESET#
1
2
CC21 CXDP@
0.1U_0402_25V6
<36>
H_CATERR#
PECI_EC
@ CC22
0.1U_0402_25V6
BDW_ULT_DDR3L
UC1B
EMI request add
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC123
CFG17
CFG16
CFG8
CFG9
XDP_RST#_R
XDP_DBRESET#
CONN@
SYS_PWROK
H_PROCHOT#
CFG17
CFG16
2
TDO_XDP
51_0402_5%
CXDP@
RC120
1K_0402_5%
1
CPU_XDP_TCLK
RC119 @
H_PROCHOT#
<36,45,46>
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
+3.3V_ALW_PCH
1
TDI_XDP_R
RC118 @
@EMC@
CC20
22P_0402_50V8J
H_CPUPWRGD
SIO_SLP_S0#
1
TDO_XDP
RC115 @
PCH_JTAG_TCK 2
0_0402_5%
1
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17
SAMTE_BSH-030-01-L-D-A
2
0_0402_5%
2
PCH_JTAG_TDO
0_0402_5%
2
SYS_RESET#
2
RC116
1
GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
2
1
B
<6>
2
1
PCH_RTCRST#
PCH_RTCRST#
POWER_SW#_MB
JXDP1
3OE
reference Shark Bay ULT Validation Customer Debug Port
Implementation Requirement Rev 1.0
@ RC114
<6>
<36,39>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND
GND
+1.05V_RUN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
CPU_XDP_PREQ#
CPU_XDP_PRDY#
2OE
GND PAD
+1.05V_VCCST
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
+PCH_VCCDSW3_3
<30>
+1.05V_RUN
VCC
2
PCH_JTAG_TDI 1
RC99
CXDP@
PCH_JTAG_TDI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SIO_SLP_S3#
+PCH_VCCDSW3_3
CONN@
ACES_50506-01841-P01
1
2 TDO_XDP
0_0402_5%
RUNPWROK
<6>
AJ6
AT4
AL5
AP4
AJ7
JAPS1
+3.3V_ALW_PCH
PCH_DPWROK <36>
PCH_PCIE_WAKE# <35,36>
20130726 same as Goliad
@ CC19
0.1U_0402_25V6
1
RC98
CXDP@
CLKRUN#
CLKRUN# <10,36>
SUS_STAT#/LPCPD#
1
2
SUSCLK_R
SUSCLK
SIO_SLP_S5# @ RC136
0_0402_5%
SIO_SLP_S5# <36>
T8
PAD~D @
T9
PAD~D @
SIO_SLP_S4#
SIO_SLP_S4# <36>
SIO_SLP_S3#
SIO_SLP_S3# <36>
SIO_SLP_A#
SIO_SLP_A# <36>
SIO_SLP_SUS#
SIO_SLP_SUS# <36>
SIO_SLP_LAN#
SIO_SLP_LAN# <36,38>
+1.05V_RUN
@ CC18
0.1U_0402_25V6
PCH_JTAG_TDO
DSWODVREN
PCH_DPWROK
PCH_PCIE_WAKE#
V5
AG4
AE6
AP5
BDW-ULT-DDR3L_BGA1168
8 OF 19
CC17 CXDP@
1
0.1U_0402_25V6
<6>
SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN
AW7
AV5
AJ5
1
@ RC95
AK2
AC3
AG2
AY7
AB5
AG7
SUSACK#
SYS_RESET#
SYS_PWROK
SUSACK#
SYS_PWROK
RESET_OUT#
ME_RESET#
8.2K_0402_5%
1
2
2
1
MISC
PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO
JTAG
THERMAL
J62
K62
E60
E61
E59
F63
F62
CPU_XDP_PRDY#
CPU_XDP_PREQ#
CPU_XDP_TCLK
CPU_XDP_TMS
CPU_XDP_TRST#
CPU_XDP_TDI
CPU_XDP_TDO
J60
H60
H61
H62
K59
H63
K60
J61
XDP_OBS0_R
XDP_OBS1_R
XDP_OBS2_R
XDP_OBS3_R
XDP_OBS4_R
XDP_OBS5_R
XDP_OBS6_R
XDP_OBS7_R
Place near JXDP1.47
+3.3V_RUN
2
XDP_DBRESET#
1K_0402_5%
+1.05V_RUN
DDR3L
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
T10
T11
T12
T13
T14
T15
2
1
@
RC124
2
1
@
RC125
2
1
@
RC126
2
1
CPU_XDP_TCLK 2
51_0402_5%
CPU_XDP_TRST# 2
51_0402_5%
1
CPU_XDP_TMS
51_0402_5%
CPU_XDP_TDI
51_0402_5%
CPU_XDP_PREQ#
51_0402_5%
CPU_XDP_TDO
51_0402_5%
PWR
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
1 RC122
@
@
@
@
@
@
BDW-ULT-DDR3L_BGA1168
2 OF 19
1
RC127
RC128
@
RC129
A
DDR3 COMPENSATION SIGNALS
200_0402_1%
121_0402_1%
100_0402_1%
2
1 RC130
SM_RCOMP0
2
1 RC131
SM_RCOMP1
2
1 RC132
SM_RCOMP2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
CPU (4/12)
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
9
of
48
5
4
3
2
1
D
D
UC1A
C54
C55
B58
C58
B55
A55
A57
B57
<25> DDI1_LANE_N0
<25> DDI1_LANE_P0
<25> DDI1_LANE_N1
<25> DDI1_LANE_P1
<25> DDI1_LANE_N2
<25> DDI1_LANE_P2
<25> DDI1_LANE_N3
<25> DDI1_LANE_P3
C51
C50
C53
B54
C49
B50
A53
B53
<24> DDI2_LANE_N0
<24> DDI2_LANE_P0
<24> DDI2_LANE_N1
<24> DDI2_LANE_P1
<24> DDI2_LANE_N2
<24> DDI2_LANE_P2
<24> DDI2_LANE_N3
<24> DDI2_LANE_P3
BDW_ULT_DDR3L
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
DDI
EDP
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL
C45
B46
A47
B47
EDP_CPU_LANE_N0
EDP_CPU_LANE_P0
EDP_CPU_LANE_N1
EDP_CPU_LANE_P1
EDP_CPU_LANE_N0
EDP_CPU_LANE_P0
EDP_CPU_LANE_N1
EDP_CPU_LANE_P1
COMPENSATION PU FOR eDP
<23>
<23>
<23>
<23>
+VCCIOA_OUT
C47
C46
A49
B49
2
EDP_COMP
24.9_0402_1%
A45
B45
EDP_CPU_AUX#
EDP_CPU_AUX
D20
A43
EDP_COMP
1
RC133
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
EDP_CPU_AUX# <23>
EDP_CPU_AUX <23>
C
C
BDW-ULT-DDR3L_BGA1168
1 OF 19
+3.3V_RUN
RPC15
5
6
7
8
4
3
2
1
SIO_RCIN#
<12,36>
CLKRUN# <36,9>
USH_DET# <12,27>
IRQ_SERIRQ
<12,36>
BDW_ULT_DDR3L
UC1I
+3.3V_RUN
RPC2
10K_8P4R_5%
<23> EDP_BIA_PWM
<23> PANEL_BKLEN
<23,36> ENVDD_PCH
1
2
2
1
@ RC139
@ RC140
ENVDD_PCH
100K_0402_5%
PCH_GPIO53
1K_0402_5%
<27,7> CONTACTLESS_DET#
<6> DGPU_PWROK
<12> HDD_FALL_INT
<12> PCH_GPIO80
@ T16
PAD~D
<12>
EDP_BIA_PWM
PANEL_BKLEN
ENVDD_PCH
DGPU_PWROK
HDD_FALL_INT
TOUCHPAD_INTR#
<12> PCH_GPIO52
PCH_GPIO53
B
B8
A9
C6
U6
P4
N4
N2
AD4
U7
L1
L3
R5
L4
EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
eDP SIDEBAND
PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME
B9
C9
D9
D11
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
C5
B6
B5
A6
CPU_DPB_AUX#
CPU_DPC_AUX#
CPU_DPB_AUX
CPU_DPC_AUX
C8
A8
D6
DPB_HPD
DPC_HPD
EDP_CPU_HPD
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
<25>
<25>
<24>
<24>
1
2
3
4
CPU_DPB_CTRLDAT
CPU_DPB_CTRLCLK
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
8
7
6
5
2.2K_0804_8P4R_5%
RPC20
DISPLAY
PCIE
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
CPU_DPB_AUX# <25>
CPU_DPC_AUX#
<24>
CPU_DPB_AUX <25>
CPU_DPC_AUX
<24>
1
2
3
4
CPU_DPB_AUX#
CPU_DPB_AUX
CPU_DPC_AUX
CPU_DPC_AUX#
8
7
6
5
100K_0804_8P4R_5%
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
DDPB_HPD
DDPC_HPD
EDP_HPD
DPB_HPD <25>
DPC_HPD <24>
EDP_CPU_HPD
<23>
EDP_CPU_HPD
100K_0402_5% 2
1 RC141
DPB_HPD
100K_0402_5% 2
1 RC142
B
BDW-ULT-DDR3L_BGA1168
9 OF 19
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (5/12)
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
10
of
48
5
4
3
2
1
PCIE for UMA
UC1K
D
WIGIG --->
<30>
<30>
PCIE_PRX_WIGIGTX_N5
PCIE_PRX_WIGIGTX_P5
<30>
<30>
PCIE_PTX_WIGIGRX_N5
PCIE_PTX_WIGIGRX_P5
PCIE_PRX_WIGIGTX_N5
PCIE_PRX_WIGIGTX_P5
F10
E10
PCIE_PTX_WIGIGRX_N5
PCIE_PTX_WIGIGRX_P5
C23
C22
F8
E8
B23
A23
H10
G10
B21
C21
E6
F6
B22
A21
10/100/1G LAN --->
C
WLAN (Mini Card 2)--->
MMI -->
<28>
<28>
PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
<28>
<28>
PCIE_PTX_GLANRX_N3
PCIE_PTX_GLANRX_P3
<30>
<30>
<30>
<30>
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
PCIE_PTX_WLANRX_N4
PCIE_PTX_WLANRX_P4
<29>
<29>
PCIE_PRX_MMITX_N1
PCIE_PRX_MMITX_P1
<29>
<29>
PCIE_PTX_MMIRX_N1
PCIE_PTX_MMIRX_P1
PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
G11
F11
PCIE_PTX_GLANRX_N3
PCIE_PTX_GLANRX_P3
C29
B30
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
F13
G13
PCIE_PTX_WLANRX_N4
PCIE_PTX_WLANRX_P4
B29
A29
PCIE_PRX_MMITX_N1
PCIE_PRX_MMITX_P1
G17
F17
PCIE_PTX_MMIRX_N1
PCIE_PTX_MMIRX_P1
B31
A31
<31> USB3TN4
<31> USB3TP4
+PCH_AUSB3PLL
RC149
1
C30
C31
F15
G15
<31> USB3RN4
<31> USB3RP4
2 3.01K_0402_1% PCH_PCIE_RCOMP
E15
E13
A27
B27
D
BDW_ULT_DDR3L
PERN5_L0
PERP5_L0
USB2N0
USB2P0
PETN5_L0
PETP5_L0
USB2N1
USB2P1
PERN5_L1
PERP5_L1
USB2N2
USB2P2
PETN5_L1
PETP5_L1
USB2N3
USB2P3
PERN5_L2
PERP5_L2
USB2N4
USB2P4
PETN5_L2
PETP5_L2
USB2N5
USB2P5
PERN5_L3
PERP5_L3
USB2N6
USB2P6
PETN5_L3
PETP5_L3
USB2N7
USB2P7
PERN3
PERP3
PETN3
PETP3
USB3RN1
USB3RP1
PCIE
USB
PERN4
PERP4
USB3TN1
USB3TP1
USB3RN2
USB3RP2
PETN4
PETP4
USB3TN2
USB3TP2
AN8
AM8
USBP0USBP0+
AR7
AT7
USBP1USBP1+
AR8
AP8
USBP2USBP2+
AR10
AT10
USBP3USBP3+
AM15
AL15
USBP4USBP4+
AM13
AN13
USBP5USBP5+
AP11
AN11
USBP6USBP6+
PCB
USB2 7
USBP0- <31>
USBP0+ <31>
-----> Ext Port 1 Charge
USBP1- <32>
USBP1+ <32>
-----> Ext Port 3
USBP2- <30>
USBP2+ <30>
-----> WLAN/BT
USBP3- <31>
USBP3+ <31>
-----> Ext Port 2
USBP4- <23>
USBP4+ <23>
-----> Touch
G14 DSC WWAN
USBP5- <23>
USBP5+ <23>
-----> Camera
G14 UMA WWAN
USBP6- <27>
USBP6+ <27>
-----> USH
AR13
AP13
G12 UMA WWAN
G12 Entry
NA
G14D_En
NA
G14U_En
NA
-----> WWAN
G20
H20
C33
B34
E18
F18
B33
A33
USB3RN1
USB3RP1
<31>
<31>
USB3TN1
USB3TP1
<31>
<31>
USB3RN2
USB3RP2
<32>
<32>
USB3TN2
USB3TP2
<32>
<32>
-----> Ext USB3 Port 1 Charge
C
-----> Ext USB3 Port 3
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
USBRBIAS
USBRBIAS
RSVD
RSVD
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
RSVD
RSVD
PCIE_RCOMP
PCIE_IREF
AJ10
AJ11
AN10
AM10
AL3
AT1
AH2
AV3
USBRBIAS
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
----->
<31>
<12,32> ----->
<12,31> ----->
<12>
USB Port0 (JUSB1)
USB Port1 (JUSB3)
USB Port3 (JUSB2)
+3.3V_ALW_PCH
RPC19
<12>
<7>
PCH_GPIO44
4
3
2
1
USB_OC0#
PCH_SMB_ALERT#
<12,37> KB_DET#
5
6
7
8
10K_8P4R_5%
BDW-ULT-DDR3L_BGA1168
11 OF 19
B
B
USBRBIAS
PCIE5
G12 UMA SD card
NA
LOM
WLAN
WIGIG
PCIE6
1
PCIE2 PCIE3 PCIE4
M2 3042
(HCA & SATA-Cache)
G12 Entry SD card
NA
LOM
WLAN
WIGIG
NA
G14 DSC SD card
NA
LOM
WLAN
GPU
WIGIG
G14 UMA SD card
NA
LOM
WLAN
WIGIG
M2 3042
(HCA & SATA-Cache)
G14D_En SD card
NA
LOM
WLAN
GPU
WIGIG
G14U_En SD card
NA
LOM
WLAN
WIGIG
NA
2
PCIE1
RC152
22.6_0402_1%
PCB
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15
mils.
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (6/12)
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
11
of
48
5
4
3
2
1
+PCH_VCCDSW3_3
2
1 LAN_WAKE#
10K_0402_5%
RC153
+1.05V_VCCST
2
H_THERMTRIP#
1K_0402_5%
1
RC25
+3.3V_RUN
D
D
2
1
2
1
+3.3V_RUN
MPHYP_PWR_EN
100K_0402_5%
SIO_EXT_SCI#
100K_0402_5%
RC155
RC156
RPC17
5
6
7
8
PCH_GPIO76
<30,7>
<10>
BDW_ULT_DDR3L
UC1J
WLANCLK_REQ#
PCH_GPIO80
4
3
2
1
10K_8P4R_5%
+3.3V_RUN
1
<12,36> SIO_EXT_WAKE#
<28,9> PM_LANPHY_ENABLE
2
TPM_PIRQ#
10K_0402_5%
RC247
<27>
<7> PCH_GPIO16
TPM_PIRQ#
<28,36>
4
3
2
1
5
6
7
8
SLATE_MODE
USB_OC2# <11,31>
PCH_GPIO46 <12>
PCH_GPIO73
<11> PCH_GPIO44
MEDIACARD_IRQ#
@ T22 PAD~D
<23> TOUCH_PANEL_INTR#
<38> MPHYP_PWR_EN
<11,37> KB_DET#
@ T21
PAD~D
<23> 3.3V_CAM_EN#
<36> SIO_EXT_SMI#
<12> PCH_GPIO46
RPC10
TPM_PIRQ#
NFC_IRQ
<29>
+3.3V_ALW_PCH
HOST_ALERT1_R_N
LAN_WAKE#
LAN_WAKE#
PCH_NFC_RST for Goliad
C
<7>
10K_8P4R_5%
@ T27
PAD~D
MEDIACARD_RST#
PCH_GPIO57
SLATE_MODE
PCH_GPIO59
PCH_GPIO44
DIMM_DET
PCH_GPIO49
TOUCH_PANEL_INTR#
MPHYP_PWR_EN
KB_DET#
PCH_GPIO14
3.3V_CAM_EN#
SIO_EXT_SMI#
PCH_GPIO9
PCH_GPIO10
RPC5
4
3
2
1
5
6
7
8
P1
AU2
AM7
AD6
Y1
T3
AD5
AN5
AD7
AN3
PCH_GPIO76
SIO_EXT_WAKE#
SIO_EXT_SMI#
PCH_GPIO9
MEDIACARD_RST#
MEDIACARD_IRQ#
<20> HDD_DEVSLP
<36> SIO_EXT_SCI#
<21> SPKR
SIO_EXT_SCI#
SPKR
AG6
AP1
AL4
AT5
AK4
AB6
U4
Y3
P3
Y2
AT3
AH4
AM4
AG5
AG3
AM3
AM2
P2
C4
L2
N5
V2
BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46
CPU/
MISC
RPC7
5
6
7
8
PCH_GPIO57
D60
V4
T4
AW15
AF20
AB21
H_THERMTRIP#_R
SIO_RCIN#
IRQ_SERIRQ
PCH_OPI_COMP
@ 0_0402_5% 2
1 RC161
H_THERMTRIP#
CPPE#
100K_0402_5%
FFS_INT2
100K_0402_5%
PCH_GPIO67
10K_0402_5%
PCH_GPIO68
10K_0402_5%
<36>
SIO_RCIN#
<10,36>
IRQ_SERIRQ
<10,36>
GPIO
SERIAL IO
GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2
GC6_EVENT#_Q
GPU_GC6_FB_EN
PCH_GPIO85
BBS_BIT
PCH_GPIO87
3.3V_TP_EN
1
2
1
2
1
2
1
RC160
RC158
RC163
RC164
CPPE#
CPUSB#
CAM_MIC_CBL_DET# 5
6
PCH_GPIO69
7
GC6_EVENT#_Q
8
PCH_GPIO87
@ T109 PAD~D
4
3
2
1
10K_8P4R_5%
RPC3
3.3V_TS_EN <23>
3.3V_HDD_EN
<20>
<10>
PCH_GPIO52
TOUCH_PANEL_INTR# 5
6
7
3.3V_TP_EN
8
GPU_GC6_FB_EN
4
3
2
1
C
10K_8P4R_5%
FFS_INT2
LCD_CBL_DET#
I2C0_SDA
I2C0_SCL
I2C1_SDA_VMM
I2C1_SCL_VMM
USH_DET#
CAM_MIC_CBL_DET#
PCH_GPIO66
PCH_GPIO67
PCH_GPIO68
PCH_GPIO69
LCD_CBL_DET#
RPC4
<23>
USH_DET# <10,27>
CAM_MIC_CBL_DET#
LCD_CBL_DET#
CPUSB#
3.3V_TS_EN
PCH_GPIO85
5
6
7
8
I2C1_SDA_VMM
I2C1_SCL_VMM
I2C0_SCL
I2C0_SDA
1
2
3
4
4
3
2
1
10K_8P4R_5%
<23>
RPC8
8
7
6
5
2.2K_0804_8P4R_5%
BDW-ULT-DDR3L_BGA1168
10 OF 19
USB_OC3# <11>
SIO_EXT_WAKE# <12,36>
USB_OC1# <11,32>
2
RPC16
10K_8P4R_5%
4
3
2
1
THRMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD
RPC9
5
6
7
8
<10> HDD_FALL_INT
<30,7> WIGIGCLK_REQ#
<10> TOUCHPAD_INTR#
<6> SATA2_PCIE6_L1
10K_8P4R_5%
4
3
2
1
10K_8P4R_5%
1
2
DIMM Detect
HIGH
LOW
ENABLE
DISABLE
HOST_ALERT1_R_N
TLS CONFIDENTIALITY
1 DIMM
2 DIMM
HIGH
LOW(DEFAULT)
ENABLE
DISABLE
1
PCH_OPI_COMP
49.9_0402_1%
@ RC180
1K_0402_5%
RC303
10K_0402_5%
TOP-BLOCK SWAP OVERRIDE
HIGH
LOW(DEFAULT)
+3.3V_RUN
1
2
+3.3V_ALW_PCH
DIMM_DET
RC179
1K_0402_5%
PCH_GPIO66
2
1
RC175
@ RC171
1
1
2
B
2
2
3.3V_CAM_EN#
100K_0402_5%
NFC_IRQ
100K_0402_5%
MPHYP_PWR_EN
10K_0402_5%
RC174
+3.3V_RUN
1
1
+3.3V_RUN
2
2
PCH_GPIO59
100K_0402_5%
@ RC302
10K_0402_5%
1
@ RC176
1K_0402_5%
2
RC245
1
B
2
RC178
SPKR
No Reboot on TCO Timer expiration
HIGH
ENABLE
LOW(DEFAULT) DISABLE
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (7/12)
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
12
of
48
5
4
3
2
1
D
D
CFG STRAPS for CPU
UC1S
BDW_ULT_DDR3L
CFG8
CFG9
CFG10
AA62
U63
AA61
U62
V63
CFG_RCOMP
A5
E1
D1
J20
H18
B12
TDI_IREF
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RESERVED
RSVD
RSVD
RSVD
PROC_OPI_RCOMP
CFG16
CFG18
CFG17
CFG19
RSVD
RSVD
CFG_RCOMP
VSS
VSS
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
TD_IREF
AV63
AU63
PAD~D T28 @
PAD~D T29 @
C63
C62
B43
PAD~D T30 @
PAD~D T31 @
A51
B51
PAD~D T33 @
PAD~D T34 @
L60
PAD~D T35 @
2
CFG16
CFG18
CFG17
CFG19
CFG4
EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE
CFG0
N60
W23
Y22
AY15 PROC_OPI_RCOMP
C
CFG1
AV62
D58
P22
N21
P20
R20
PCH/PCH LESS MODE SELECTION
BDW-ULT-DDR3L_BGA1168
19 OF 19
CFG1
2
RC185
1
RC186
1:(Default) Normal Operation; No stall
0:Lane Reversed
1
<9>
<9>
<9>
<9>
AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
CFG0
CFG1
@ RC184
1K_0402_1%
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
2
C
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
@ RC183
1K_0402_1%
1
CFG0
1:(Default) Normal Operation
0:Lane Reversed
1
CFG_RCOMP
49.9_0402_1%
2 TDI_IREF
8.2K_0402_1%
PROC_OPI_RCOMP
49.9_0402_1%
1
2
RC187
B
B
CFG9
CFG8
CFG4
2
1
1
2
2
2
ALLOW THE USE OF NOA ON LOCKED UNITS
1: Enable(Default): Noa will be disable in
locked units and enable in un-locked
CFG8
units
0: Enable Noa will be available pegardless of
the locking of the unit
RC191
1K_0402_5%
NO SVID PROTOCOL CAPABLE VR CONNECTED
1: VRS support SVID protocol are present
0:No VR support SVID is present
CFG9
The chip will not generate(OR Respond to)
SVID activity
@ RC190
1K_0402_1%
SAFE MODE BOOT
1: POWER FEATURES ACTIVATED DURING
RESET
CFG10
0: POWER FEATURES (ESPECIALLY CLOCK
GATINE ARE NOT ACTIVATED
@ RC189
1K_0402_1%
@ RC188
1K_0402_1%
1
1
CFG10
Display Port Presence Strap
CFG4
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (8/12)
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
13
of
48
5
4
3
2
1
D
D
2
1
1
@ RC192
0_0402_5%
BDW_ULT_DDR3L
UC1Q
AY2
DC_TEST_AY2_AW2
AY3
DC_TEST_AY3_AW3
AY60
DC_TEST_AY60
DC_TEST_AY61_AW61 AY61
DC_TEST_AY62_AW62 AY62
B2
TP_DC_TEST_B2
B3
DC_TEST_A3_B3
B61
DC_TEST_A61_B61
B62
B63
DC_TEST_B62_B63
C1
C2
DC_TEST_C1_C2
DAISY_CHAIN_NCTF_AY2
DAISY_CHAIN_NCTF_AY3
DAISY_CHAIN_NCTF_AY60
DAISY_CHAIN_NCTF_AY61
DAISY_CHAIN_NCTF_AY62
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_B62
DAISY_CHAIN_NCTF_B63
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
BDW-ULT-DDR3L_BGA1168
17 OF 19
C
DC_TEST_A3_B3
DC_TEST_A4
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63
DC_TEST_A60
DC_TEST_A61_B61
DC_TEST_A62
DC_TEST_AV1
DC_TEST_AW1
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
DC_TEST_AW63
2
2
0_0402_5%
2
0_0402_5%
1
@ RC193
1
@ RC194
4
C
3
2
0_0402_5%
A3
A4
1
@ RC195
Package Daisy Chain:
1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4
2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60
3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63
4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1
UC1R
AT2
AU44
AV44
D15
B
F22
H22
J21
BDW_ULT_DDR3L
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
N23
R23
T23
U10
B
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
AL1
AM11
AP7
AU10
AU15
AW14
AY14
BDW-ULT-DDR3L_BGA1168
18 OF 19
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (9/12)
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
14
of
48
5
4
3
2
1
ESD Request
2
22U_0603_6.3V6M
0_0603_5%
+1.35V_MEM
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
2
CC34
10U_0603_6.3V6M
1
2
2
+VCC_CORE
CC24
100P_0402_50V8J
UC1L
L59
J58
+1.35V_MEM
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
H_VR_READY
RC201
3
VCC
A
Y
5
1
@ CC35
4
2
2
0.1U_0402_25V6
1
2
RESET_OUT#
NC
RC202
1K_0402_5%
+3.3V_ALW
UC8
1
+VCC_CORE
H_VCCST_PWRGD
GND
74AUP1G07GW_TSSOP5
VCCSENSE
+VCCIO_OUT
+VCCIOA_OUT
+1.05V_VCCST
<45>
2
RC204
75_0402_1%
1
SVID ALERT
1
<9>
<45>
<45>
VIDSCLK
H_VCCST_PWRGD
H_VR_EN
H_VR_READY
<9>
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
H_VCCST_PWRGD
H_VR_EN
H_VR_READY
CPU_PWR_DEBUG#
H_CPU_SVIDALRT#
RC207
@ T74
@ T75
@ T76
@ T77
PAD~D
PAD~D
PAD~D
PAD~D
CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils
2
1
+1.05V_VCCST
RC208
110_0402_1%
SVID DATA
CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 1500mils
2
43_0402_5%
VIDALERT_N
VIDSOUT
VIDSOUT
+VCC_CORE
E63
AB23
A59
E20
AD23
AA23
AE59
L62
N63
L63
B59
F60
C59
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
+1.05V_VCCST
AC22
AE22
AE23
+VCC_CORE
AB57
AD57
AG57
C24
C28
C32
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
HSW ULT POWER
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
C
B
+1.05V_VCCST
@ PJP23
PAD-OPEN1x1m
1
2
A
CC37
1U_0402_6.3V6K
VCCSENSE
CAD Note: RC209 SHOULD BE PLACED CLOSE TO CPU
1
2
@
1
CC36
22U_0603_6.3V6M
VCCSENSE
F59
N58
AC58
BDW_ULT_DDR3L
RSVD
RSVD
BDW-ULT-DDR3L_BGA1168
12 OF 19
+1.05V_RUN
2
2
RC209
100_0402_1%
1
VCC_SENSE
<45>
@ CC33
10U_0603_6.3V6M
@EMC@
@ RC199
10K_0402_5%
1
1
C
<45>
CC32
10U_0603_6.3V6M
2
22U_0603_6.3V6M
+1.05V_VCCST
B
CC31
10U_0603_6.3V6M
@ RC198
10K_0402_5%
2
H_VR_EN
1.5K_0402_5%
<45>
D
H_VCCST_PWRGD
+1.05V_VCCST
<36,9>
@ CC30
10U_0603_6.3V6M
+3.3V_RUN
1
@EMC@ CC85
CC29
10U_0603_6.3V6M
+1.05V_RUN
CPU_PWR_DEBUG#
CC28
2.2U_0402_6.3V6M
2
22U_0603_6.3V6M
CC27
2.2U_0402_6.3V6M
1
@EMC@ CC84
@ CC26
2.2U_0402_6.3V6M
2
22U_0603_6.3V6M
@ CC25
2.2U_0402_6.3V6M
RC197
150_0402_5%
D
VDDQ DECOUPLING
+VCC_CORE
1
@EMC@ CC79
2
+1.05V_RUN
RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES
2
@ RC196
+1.35V_MEM
1
@EMC@ CC23
1
+1.05V_RUN
+VCC_CORE
1
2
+VCCIO_OUT
2
2
+1.05V_RUN
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (10/12)
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
15
of
48
5
4
3
+1.05V_M
PAD-OPEN1x1m
@
PJP51
+1.05V_MODPHY_PCH
1
2
1
2
1
2
+
2
1
+
2
@EMC@ CC42
330U_D3_2.5VY_R6M
1
@EMC@ CC41
330U_D3_2.5VY_R6M
+
@ CC39
330U_D3_2.5VY_R6M
CC40
1U_0402_6.3V6K
CC44
1U_0402_6.3V6K
CC40 place near K9;
CC44 place near L10
CC43 place near M9
VCCHSIO
S0 Iccmax = 1.838A
@ CC43
1U_0402_6.3V6K
D
1
2
1
1
2
+1.05V_MODPHY
2
+1.05V_RUN
D
+RTC_CELL
DCPSUS4
AB8
+1.05V_RUN
USB2
1
2
1
2
2
1
1
2
2
B
2
1
2
1
CC82
1U_0402_6.3V6K
@ CC80
1U_0402_6.3V6K
CC82 place near A20
VCCACLKPLL
S0 Iccmax = 31mA
CC81
100U_1206_6.3V6M
LC5
1
2
2.2UH_LQM2MPN2R2NG0L_30%
1
+1.05V_RUN
2 0_0402_5%
CC80 place near AH10
VCCDSW3_3
S0 Iccmax = 114mA
CC73 place near AH11
VCCSUS3_3
S0 Iccmax = 63mA
+PCH_VCCACLKPLL
0_0402_5%
+3.3V_ALW
@ RC2171
1
RC213 @
Reminder below power rail need isolation for layout refer
attach file for more detail that from Intel review feedback.
+PCH_VCCDSW3_3
2
1
@ RC216
2
0_0402_5%
CC78
1U_0402_6.3V6K
+3.3V_ALW_PCH
1
RC212 @
LC4
1
2
2.2UH_LQM2MPN2R2NG0L_30%
CC78 place near J18
VCCCLK
S0 Iccmax = 200mA
CC77
100U_1206_6.3V6M
B
+3.3V_ALW_PCH
2
0_0402_5%
+3.3V_ALW
CC72 place near AG16
+PCH_VCC1P05
2
@ CC97 0.47U_0402_10V6K
CC97 place near AH10
intel DG Rev 1.2 , page 500
47.3 Boot Strap Capacitor
+PCH_RTC_VCCSUS3_3
CC73
1U_0402_6.3V6K
RSVD
VCC1_05
VCC1_05
AC20
AG16
AG17
2
1
CC69 place near U8
C
1
SUS OSCILLATOR
2
1
2013/06/10 refer 6L_WP chnage to float,6/14 change back
U8
T9
LPT LP POWER
BDW-ULT-DDR3L_BGA1168
13 OF 19
+1.05V_RUN
2
@
1
VCCSDIO
VCCSDIO
2
SERIAL IO
1
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
1
+3.3V_ALW_PCH
+PCH_VCCDSW
1
2
2
+1.5V_RUN
2
1
2
1
1
2
1
1
2
1
1
2
2
2
1
2
CC70 close to Pin J17
CC71 close to Pin R21
J18
K19
A20
J17
R21
T21
K18
M20
V21
AE20
AE21
CC65 place near AG19
+3.3V_RUN
CC72
1U_0402_6.3V6K
+PCH_VCCDSW3_3
2
CC65
1U_0402_6.3V6K
VCCTS1_5
VCC3_3
VCC3_3
1
1
5.11_0402_1%
CC66
0.1U_0402_10V7K
THERMAL SENSOR
J15
K14
K16
CC61 CC62 place near AE9
CC69
1U_0402_6.3V6K
1
GPIO/LPC
2
+PCH_VCCDSW
RC211
+PCH_VCCDSW_R
CORE
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3
+PCH_VCCDSW
CC60
10U_0603_6.3V6M
DCPSUS2
+1.05V_M
CC59
1U_0402_6.3V6K
VRM
+1.05V_RUN
CC59 and CC60 place near
J11; CC58 place near AE8
CC58
1U_0402_6.3V6K
+PCH_VCC1P05
+PCH_VCCACLKPLL
CC71
1U_0402_6.3V6K
2
+1.05V_M
+3.3V_RUN
+1.05V_RUN
CC70
1U_0402_6.3V6K
CC68
1U_0402_6.3V6K
CC67
100U_1206_6.3V6M
CC68 place near AA21
VCCAPLL
S0 Iccmax = 57mA
HDA
VCCHDA
J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
CC61
1U_0402_6.3V6K
LC3
1
2
2.2UH_LQM2MPN2R2NG0L_30%
+PCH_VCCDSW3_3
AC9
AA9
AH10
V8
W9
CC64 place near V8
2013/06/10 refer 6L_WP chnage to +3.3V_M, 6/14 change back
CC64
22U_0603_6.3V6M
+V1.05S_APLLOPI
+3.3V_RUN
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
@ CC62
22U_0603_6.3V6M
CC63 place near AC9
C
+1.05V_RUN
AH13
+3.3V_ALW_PCH
CC63
22U_0603_6.3V6M
CC57
0.1U_0402_10V7K
CC56
22U_0603_6.3V6M
CC55
22U_0603_6.3V6M
CC56 place near B11
VCCSATA3PLL
S0 Iccmax = 42mA
AH14
CC57 place near AH14
AG14
AG13
USB3
DCPSUS3
1
J13
1
+3.3V_ALW_PCH
2
+PCH_ASATA3PLL
LC2
1
2
2.2UH_LQM2MPN2R2NG0L_30%
CC54 place near Y8
2
VCCASW
VCCASW
+1.05V_MODPHY
+3.3V_M
Y8
2
VCCSPI
OPI
1
SPI
RSVD
VCCAPLL
VCCAPLL
AH11
+PCH_RTC_VCCSUS3_3
AG10
AE7 +DCPRRTC 1
2
CC52
0.1U_0402_10V7K
1
VCCSUS3_3
VCCRTC
DCPRTC
2
Y20
AA21
W21
RTC
@ CC54
0.1U_0402_10V7K
+V1.05S_APLLOPI
HSIO
2
1
2
1
1
2
2
+PCH_AUSB3PLL
+PCH_ASATA3PLL
VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL
CC50
1U_0402_6.3V6K
@ CC53
1U_0402_6.3V6K
CC47
22U_0603_6.3V6M
CC51
22U_0603_6.3V6M
CC47 place near B18
VCCUSB3PLL
S0 Iccmax = 41mA
BDW_ULT_DDR3L
UC1M
K9
L10
M9
N8
P9
B18
B11
+1.05V_MODPHY_PCH
+1.05V_RUN
CC48
0.1U_0402_10V7K
+PCH_AUSB3PLL
LC1
1
2
2.2UH_LQM2MPN2R2NG0L_30%
CC49
0.1U_0402_10V7K
+1.05V_MODPHY
1
CC48,CC49, CC50 place near AG10
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (11/12)
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
16
of
48
5
4
3
2
1
D
D
UC1N
A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
C
B
UC1O
BDW_ULT_DDR3L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
BDW_ULT_DDR3L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
UC1P
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13
BDW_ULT_DDR3L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
VSS
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
C
V58
AH46
V23
E62
AH16
VSSSENSE
<45>
BDW-ULT-DDR3L_BGA1168
16 OF 19
B
VSSSENSE
RC218
BDW-ULT-DDR3L_BGA1168
15 OF 19
1
2
100_0402_1%
CAD Note: RC218 SHOULD BE PLACED CLOSE TO CPU
BDW-ULT-DDR3L_BGA1168
14 OF 19
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
CPU (12/12)
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
17
of
48
3
DDR_A_MA3
DDR_A_MA1
M_CLK_DDR0
M_CLK_DDR#0
<8>
DDR_A_BS0
<8> DDR_A_WE#
<8> DDR_A_CAS#
Layout Note:
Place near
JDIMM1.203,204
<8>
DDR_CS1_DIMMA#
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
1
2
1
2
1
2
1
2
1
2
DDR_A_D17
DDR_A_D16
DDR_A_D36
DDR_A_D33
DDR_A_D34
DDR_A_D38
DDR_A_D62
DDR_A_D58
DDR_A_D60
DDR_A_D61
2
@ RD16
0_0402_5% +3.3V_RUN
0_0402_5%
2
@ CD31
2.2U_0402_6.3V6M
1
+0.675V_DDR_VTT
CD32
0.1U_0402_25V6
A
1
2
1
2
1
@ RD15
205
207
GND1
BOSS1
GND2
BOSS2
1
2
1
+DIMM1_VREF_DQ
<8>
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
2
2_0402_1%
DDR_CS0_DIMMA#
M_ODT1
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D7
<8>
<8>
DDR_A_BS1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA#
M_ODT0
<8>
+SM_VREF_CA_DIMM
+5V_ALW
DDR_A_D18
DDR_A_D19
DDR3L SODIMM ODT GENERATION
DDR_A_D22
DDR_A_D23
DDR_A_D37
DDR_A_D32
1
3
1
RD10
1
RD11
1
RD12
1
RD13
0.675V_DDR_VTT_ON
DDR_A_D35
DDR_A_D39
DDR_A_D63
DDR_A_D59
B
QD1
L2N7002WT1G_SC-70-3
+1.35V_MEM
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#7
DDR_A_DQS7
2
M_ODT0
66.5_0402_1%
2
M_ODT1
66.5_0402_1%
2
66.5_0402_1%
2
66.5_0402_1%
M_ODT2
<19>
M_ODT3
<19>
+1.35V_MEM
DDR_A_D56
DDR_A_D57
UD1
1
<9>
+0.675V_DDR_VTT
C
+SM_VREF_DQ0
1
RD5
@ RD14
2M_0402_5%
DDR_A_DQS#4
DDR_A_DQS4
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
RD9
220K_0402_5%
DDR_A_D21
DDR_A_D20
CD29
10U_0603_6.3V6M
CD28
10U_0603_6.3V6M
CD27
0.1U_0402_25V6
CD26
0.1U_0402_25V6
2
DDR_A_D2
DDR_A_D6
CD25
0.1U_0402_25V6
CD24
0.1U_0402_25V6
1
+0.675V_DDR_VTT
DDR_CKE1_DIMMA
CD23
2.2U_0402_6.3V6M
DDR_A_DQS#0
DDR_A_DQS0
+1.35V_MEM
DDR_A_D54
DDR_A_D55
CD22
0.1U_0402_25V6
DDR_A_D0
DDR_A_D1
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
CAD NOTE
PLACE THE CAP NEAR TO DIMM RESET PIN
DDR_A_DQS#6
DDR_A_DQS6
RD7
24.9_0402_1%
<8>
<8>
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
DDR_A_D52
DDR_A_D53
1
DDR_A_MA8
DDR_A_MA5
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
<9>
DDR_A_D42
DDR_A_D46
2
DDR_A_MA12
DDR_A_MA9
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR3_DRAMRST#_CPU
1
DDR_A_BS2
2
0_0402_5%
2
DDR_CKE0_DIMMA
1
@ RD3
2
DDR_A_BS2
DDR3_DRAMRST#
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
<8>
<19>
CD21
0.022U_0402_16V7K
2
DDR_CKE0_DIMMA
DDR_A_D45
DDR_A_D40
RD6
1.8K_0402_1%
+
CD20
330U_D3_2.5VY_R6M
CD19
10U_0603_6.3V6M
CD18
10U_0603_6.3V6M
CD17
10U_0603_6.3V6M
CD15
10U_0603_6.3V6M
@ CD16
10U_0603_6.3V6M
CD14
10U_0603_6.3V6M
CD12
10U_0603_6.3V6M
@ CD13
10U_0603_6.3V6M
1
<8>
DDR_A_D27
DDR_A_D26
2
+1.35V_MEM
C
DDR3_DRAMRST#
RD4
1.8K_0402_1%
DDR_A_D49
DDR_A_D48
DDR_A_D25
DDR_A_D24
S
DDR_A_D51
DDR_A_D50
+1.35V_MEM
DDR_A_D15
DDR_A_D11
D
DDR_A_D43
DDR_A_D47
D
DDR_A_DQS#1
DDR_A_DQS1
2
G
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D9
DDR_A_D12
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
CD11
1U_0402_6.3V6K
CD10
1U_0402_6.3V6K
CD4
1U_0402_6.3V6K
CD9
1U_0402_6.3V6K
CD8
1U_0402_6.3V6K
CD3
1U_0402_6.3V6K
CD2
1U_0402_6.3V6K
CD7
1U_0402_6.3V6K
1
DDR_A_D44
DDR_A_D41
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
@ CD6
0.1U_0402_25V6
DDR_A_D30
DDR_A_D31
+1.35V_MEM
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
2
DDR_A_DQS#3
DDR_A_DQS3
+1.35V_MEM
CONN@
2
DDR_A_D29
DDR_A_D28
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
1
1
1
2
DDR_A_D14
DDR_A_D10
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
1
RD2
470_0402_5%
Layout Note:
Place near JDIMM1
CD1
0.1U_0402_25V6
CD5
2.2U_0402_6.3V6M
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
DDR_A_D13
DDR_A_D8
1
JDIMM1
D
B
H=4mm
Reverse Type
+1.35V_MEM
2
+DIMM1_VREF_DQ
DDR_A_MA[0..15]
1
DDR_A_DQS[0..7]
<8>
2
DDR_A_D[0..63]
<8>
2
1
DDR_A_DQS#[0..7]
<8>
2
<8>
4
2
5
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
DDR_PG_CTRL
<19,7,9>
<19,7,9>
2
3
NC
VCC
A
Y
5
4
1
@ CD30
2
0.1U_0402_25V6
0.675V_DDR_VTT_ON
0.675V_DDR_VTT_ON
<42>
GND
74AUP1G07GW_TSSOP5
206
208
A
LCN_DAN06-K4406-0103
20130730 SP07000LT00
CIS Link OK
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
DDR3L
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
18
of
48
4
3
DDR_B_MA10
DDR_B_BS0
DDR_B_BS0
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_CS3_DIMMB#
B
DDR_B_D3
DDR_B_D7
DDR_B_D21
DDR_B_D20
+0.675V_DDR_VTT
DDR_B_D22
DDR_B_D23
1
2
1
2
1
2
1
2
1
2
2
CD62
10U_0603_6.3V6M
CD61
10U_0603_6.3V6M
CD60
0.1U_0402_25V6
CD59
0.1U_0402_25V6
CD58
0.1U_0402_25V6
CD57
0.1U_0402_25V6
1
DDR_B_D36
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D35
DDR_B_D39
DDR_B_D52
DDR_B_D49
DDR_B_D48
DDR_B_D53
+3.3V_RUN
+3.3V_RUN
1
2
2
CD64
0.1U_0402_25V6
@ CD63
2.2U_0402_6.3V6M
A
+0.675V_DDR_VTT
@ RD28
0_0402_5%
2
0_0402_5%
1
1
1
2
@ RD27
205
207
GND1
BOSS1
GND2
BOSS2
1
2
1
2
1
2
1
2
C
+1.35V_MEM
+DIMM2_VREF_DQ
DDR_B_MA6
DDR_B_MA4
+SM_VREF_DQ1
1
DDR_B_MA2
DDR_B_MA0
2
RD23
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
<8>
<8>
DDR_B_BS1 <8>
DDR_B_RAS# <8>
1
M_CLK_DDR3
M_CLK_DDR#3
2_0402_1%
DDR_CS2_DIMMB#
M_ODT2
DDR_CS2_DIMMB#
M_ODT2 <18>
M_ODT3
<18>
<8>
+SM_VREF_CA_DIMM
DDR_B_D5
DDR_B_D0
DDR_B_D2
DDR_B_D6
CD56
2.2U_0402_6.3V6M
DDR_B_DQS#0
DDR_B_DQS0
<8>
DDR_B_MA11
DDR_B_MA7
CD55
0.1U_0402_25V6
DDR_B_D4
DDR_B_D1
Layout Note:
Place near
JDIMM2.203,204
DDR_CKE3_DIMMB
DDR_B_MA15
DDR_B_MA14
RD25
24.9_0402_1%
DDR_B_WE#
DDR_B_CAS#
<8> DDR_B_WE#
<8> DDR_B_CAS#
<8>
DDR_CKE3_DIMMB
2
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#2
<8>
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
1
<8>
<8>
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
DDR_B_MA3
DDR_B_MA1
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
RD24
1.8K_0402_1%
2
DDR_B_MA8
DDR_B_MA5
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR_B_D63
DDR_B_D62
CD54
0.022U_0402_16V7K
+
CD53
330U_D3_2.5VY_R6M
CD52
10U_0603_6.3V6M
CD51
10U_0603_6.3V6M
CD50
10U_0603_6.3V6M
CD49
10U_0603_6.3V6M
CD48
10U_0603_6.3V6M
@ CD47
10U_0603_6.3V6M
CD45
10U_0603_6.3V6M
@ CD46
10U_0603_6.3V6M
2
DDR_B_MA12
DDR_B_MA9
CAD NOTE
PLACE THE CAP NEAR TO DIMM RESET PIN
2_0402_1%
DDR_B_DQS#7
DDR_B_DQS7
1
DDR_B_BS2
DDR_B_BS2
2
RD22
1.8K_0402_1%
<8>
DDR_B_D47
DDR_B_D43
DDR_B_D61
DDR_B_D60
+SM_VREF_CA
1
RD19
2
DDR_CKE2_DIMMB
DDR_CKE2_DIMMB
+1.35V_MEM
+SM_VREF_CA_DIMM
1
<8>
C
DDR_B_D45
DDR_B_D44
<18>
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
CD44
1U_0402_6.3V6K
CD43
1U_0402_6.3V6K
CD42
1U_0402_6.3V6K
CD41
1U_0402_6.3V6K
CD40
1U_0402_6.3V6K
CD39
1U_0402_6.3V6K
CD38
1U_0402_6.3V6K
CD37
1U_0402_6.3V6K
DDR_B_D59
DDR_B_D58
DDR3_DRAMRST#
DDR_B_D30
DDR_B_D31
RD21
24.9_0402_1%
DDR_B_D56
DDR_B_D57
DDR3_DRAMRST#
1
DDR_B_D46
DDR_B_D42
DDR_B_D25
DDR_B_D24
RD20
1.8K_0402_1%
DDR_B_DQS#5
DDR_B_DQS5
+1.35V_MEM
+1.35V_MEM
CD36
0.022U_0402_16V7K
DDR_B_D40
DDR_B_D41
D
DDR_B_D13
DDR_B_D15
2
DDR_B_D26
DDR_B_D27
DDR_B_DQS#1
DDR_B_DQS1
@ CD35
0.1U_0402_25V6
Layout Note:
Place near JDIMM2
DDR_B_D12
DDR_B_D9
1
DDR_B_DQS#3
DDR_B_DQS3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
RD18
1.8K_0402_1%
DDR_B_D28
DDR_B_D29
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
2
DDR_B_D10
DDR_B_D11
CONN@
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
1
1
2
1
2
DDR_B_D8
DDR_B_D14
CD34
0.1U_0402_25V6
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
DDR_B_MA[0..15]
CD33
2.2U_0402_6.3V6M
DDR_B_DQS[0..7]
<8>
+1.35V_MEM
JDIMM2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DDR_B_D[0..63]
<8>
D
+1.35V_MEM
DDR_B_DQS#[0..7]
<8>
1
H=4mm
Reverse Type
+DIMM2_VREF_DQ
<8>
2
2
5
DDR_B_D16
DDR_B_D17
B
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D19
DDR_B_D18
DDR_B_D37
DDR_B_D32
DDR_B_D34
DDR_B_D38
DDR_B_D51
DDR_B_D55
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D50
+0.675V_DDR_VTT
DDR_XDP_WAN_SMBDAT <18,7,9>
DDR_XDP_WAN_SMBCLK <18,7,9>
206
208
A
LCN_DAN06-K4406-0103
20130730 SP07000LT00 CIS Link OK
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
DDR3L
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
19
of
48
5
4
3
2
1
D
D
+3.3V_HDD source
+3.3V_RUN
UZ11
C
1
<12>
3
3.3V_HDD_EN
@ RN6
10K_0402_5%
1
+3.3V_RUN
@ PJP4
VIN
VOUT
VIN
VOUT
7
+3.3V_HDD_UZ11
2
6
2
2
CZ65
470P_0402_50V7K
1
@
VBIAS
CT
GND
GND
5
9
1
1
RN7
10K_0402_5%
+3.3V_HDD
CZ64
0.1U_0402_10V7K
4
2
PAD-OPEN1x3m
3.3V_HDD_EN
+5V_ALW
1
8
2
2
C
ON
TPS22967DSGR_SON8_2X2
+3.3V_HDD
Mini mSATA H=4
1
2 HDD_DEVSLP
10K_0402_5%
@ RN1
+3.3V_HDD
+3.3V_HDD
JMINI3
B
PCH_PLTRST#_EC
<27,30,36,9> PCH_PLTRST#_EC
<36,7> CLK_PCI_LPDEBUG
<6>
<6>
<6>
<6>
SATA_PRX_DTX_P1
SATA_PRX_DTX_N1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
CN3
CN4
CN5
CN6
2
2
1
1 .01U_0402_16V7K
.01U_0402_16V7K
SATA_PRX_DTX_P1_C
SATA_PRX_DTX_N1_C
2
2
1 .01U_0402_16V7K
1 .01U_0402_16V7K
SATA_PTX_DRX_N1_C
SATA_PTX_DRX_P1_C
+3.3V_HDD
1
2
CN2
0.1U_0402_25V6
2
CN1
0.1U_0402_25V6
1
@
<6>
HDD_DET#
HDD_DET#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
CONN@
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
LPC_LFRAME#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
HDD_DEVSLP
B
LPC_LFRAME# <36,7>
LPC_LAD3 <36,7>
LPC_LAD2 <36,7>
LPC_LAD1 <36,7>
LPC_LAD0 <36,7>
HDD_DEVSLP
<12>
54
LCN_DAN08-52406-0500
A
A
Place near JMINI3
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
HDD CONN
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
20
of
56
1
1
SLEEVE
2.2K_0402_5%
RA6
16
RING2
SLEEVE
29
17
18
19
1
10U_0603_6.3V6M
2
0_0402_5%
AUD_NB_MUTE#
20
+MIC2_VREF_OUT
1
2
1
1
2
2
2
47
27
39
7
@
1
RA40
INT_SPK_L+
INT_SPK_LINT_SPK_R+
INT_SPK_R-
2
3
48
1
DMIC_CLK_L
EMC@ RA14
1
1
2
2
2
1
1
1
1
2
42
43
45
44
2
AUD_OUT_L
AUD_OUT_R RA7
RA8
2
1
32
33
SPK-OUT-L+
SPK-OUT-LSPK-OUT-R+
SPK-OUT-R-
1
1
2
AUD_HP_OUT_L
2 24.9_0402_1% AUD_HP_OUT_R
24.9_0402_1%
AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
B
MONO-OUT
+MIC2_VREF_OUT
GPIO0/DMIC-DATA
GPIO1/DMIC-CLK
SPDIF-OUT/GPIO2
MIC2-VREFO
MIC2-L(PORT-F-L)/RING
MIC2-R(PORT-F-R)/SLEEVE
MIC_CAP
37
35
CBP
CBN
2
1
1U_0603_10V6K
CA35 2
PDB
28
12
34
VREF
PCBEEP
CPVEE
LDO1-CAP
LDO2-CAP
LDO3-CAP
DMIC0 <23>
DMIC_CLK <23>
DMIC_CLK
33_0402_5%
Place CA29 close to Codec
CA29
NC
2
place close to pin12
1 2.2U_0603_6.3V6K
2
CA27
2
CA28
AUD_PC_BEEP
2
1
CA49
1U_0603_10V6K
1
0.1U_0402_25V6
1
0.1U_0402_25V6
1
RA12
1
RA13
2
1K_0402_5%
2
1K_0402_5%
SPKR
<12>
BEEP
<36>
DMIC_CLK
CA30
22P_0402_50V8J
2
2
CA25
1
RA41
CA53
10U_0603_6.3V6M
CA52
10U_0603_6.3V6M
2
2
10K_0402_5%
RA44 100K_0402_5%
1
1
RA18
@
CA51
10U_0603_6.3V6M
@EMC@ CA33
10P_0402_50V8J
+3.3V_RUN_AUDIO
1
AUD_NB_MUTE#
1
<35>
1
+3.3V_RUN_AUDIO
CA31
1U_0603_10V6K
2
@EMC@ RA17
33_0402_5%
SLEEVE & RING2 trace width require least
40mil and its length as short as possible.
HPOUT-L(PORT-I-L)
HPOUT-R(PORT-I-R)
LINE1-R(PORT-C-R)
LINE1-L(PORT-C-L)
LINE1-VREFO-R
LINE1-VREFO-L
LINE2-R(PORT-E-R)
LINE2-L(PORT-E-L)
CA26
1U_0603_10V4Z
Close to UA1 pin6
RESETB
@
1
RING2
2.2K_0402_5%
2
21
22
30
31
23
24
JD1
SDATA-IN
@EMC@
2
RA5
11
13
14
15
2
+5V_RUN_PVDD
1
MIC1_R
MIC1_L
+MIC1_VREFO_R
+MIC1_VREFO_L
HP/LINE1 JD(JD1)
MIC2/LINE2 JD(JD2)
SPDIFO/FRONT JD(JD3)/GPIO3
SYNC
+VDDA_PVDD
2
PCH_AZ_CODEC_RST#
PCH_AZ_CODEC_RST#
SDATA-OUT
36
41
46
1
8
PCH_AZ_SDIN0_R
CPVDD
PVDD1
PVDD2
BCLK
place close to pin46
2
4
0_0402_5% DVSS
49
GND
ALC3234-CG_MQFN48_6X6
25
38
AVSS1
AVSS2
2
RA9
2
1
2
2
33_0402_5%
1
1
1
1
2
2
1
PCH_AZ_CODEC_SDIN0
<6>
5
10
Place RA9 close to UA1
2
3
2
1
3
2
1
1
1
1
1
2
2
2
2
2
<6>
PCH_AZ_CODEC_SDOUT
PCH_AZ_CODEC_SYNC
+MIC2_VREF_OUT
PCH_AZ_CODEC_BITCLK
DVDD-IO
place close to pin41
CA48
10U_0603_6.3V6M
PCH_AZ_CODEC_SDOUT
<6>
6
@ RA39
0_0805_5%
<6>
PCH_AZ_CODEC_BITCLK
1
CA47
0.1U_0402_25V6
PCH_AZ_CODEC_BITCLK
+1.5V_RUN_AUDIO
place close to pin36
CA46
10U_0603_6.3V6M
<6>
26
40
AVDD1
AVDD2
+5V_RUN_AUDIO
@ RA4
0_0603_5%
9
DVDD
ACES_50279-0040N-001
20130730 CIS Link OK
Close to UA1
B
2
UA1
1
+3.3V_RUN_AUDIO
CA45
0.1U_0402_25V6
GND
GND
1
CA18
4.7U_0603_6.3V6K
@EMC@ DA7
L03ESDL5V0CC3-2_SOT23-3
@EMC@ CA24
1000P_0402_50V7K
@EMC@ CA19
1000P_0402_50V7K
@EMC@ CA23
1000P_0402_50V7K
@EMC@ CA22
1000P_0402_50V7K
@EMC@ DA6
L03ESDL5V0CC3-2_SOT23-3
5
6
place close to pin40
CA17
0.1U_0402_25V6
1
2
3
4
2
BLM15PX600SN1D_2P
CA16
4.7U_0603_6.3V6K
1
2
3
4
CA11
0.1U_0402_25V6
INT_SPKR_L+
INT_SPKR_LINT_SPKR_R+
INT_SPKR_R-
CA50
0.1U_0402_25V6
JSPK1
2 BLM15PX330SN1D_2P
2 BLM15PX330SN1D_2P
2 BLM15PX330SN1D_2P
2 BLM15PX330SN1D_2P
CA10
4.7U_0603_6.3V6K
EMC@ LA6 1
EMC@ LA7 1
EMC@ LA8 1
EMC@ LA9 1
CA9
10U_0603_6.3V6M
CA10,CA11 close to pin1
CONN@
40 mils trace keep 20 mil spacing
INT_SPK_L+
INT_SPK_LINT_SPK_R+
INT_SPK_R-
CA8
0.1U_0402_25V6
+3.3V_RUN_AUDIO
Internal Speakers Header
LA5
@ RA3
0_0603_5%
1
+VDDA_AVDD1
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.)
+1.5V_RUN
1
+5V_RUN_AUDIO
place close to pin26
2
2
place close to pin3
Verb table configures as 1 JD mode with
internal 47K pull high to save external rBOM.
Place closely to Pin 13.
JD1
+MIC1_VREFO_R
@ PJP9
1
+5V_RUN
2
2
1
1
2
@EMC@
RA35
0_0402_5%
1
2
@EMC@
RA36
0_0402_5%
1
2
MIC1_L
CA43
1
MIC1_R
CA44
1
2
1
+3.3V_RUN
1
2
HP-Out-Right
Nokia-MIC
HP-Out-Left
iPhone-MIC
4.7U_0603_6.3V6K
+3.3V_RUN_AUDIO
Global Headset
1
PAD-OPEN1x2m
Combo Jack
JHP1
2
RING2
AUD_HP_OUT_L
EMC@ LA10 1
EMC@ LA2 1
A
7
3
2 BLM15PX330SN1D_2P RING2_R
2
AUD_HP_OUT_L1
BLM15BD601SN1D_2P
1
Normal
Open
5
SLEEVE
BLM15BD601SN1D_2P
2
AUD_HP_OUT_R1
2 BLM15PX330SN1D_2P
1
2
2
3
1
2
2
3
3
1
2
1
2
@EMC@
CA13 680P_0402_50V7K
QA2A
DMN66D0LDW-7_SOT363-6
1
6
SINGA_2SJ3080-003111F
CONN@
1
RA2
100K_0402_5%
@EMC@
CA12 680P_0402_50V7K
EMC@
DA3
L03ESDL5V0CC3-2_SOT23-3
EMI De-pop
EMC@
DA2
L03ESDL5V0CC3-2_SOT23-3
Realtek feedback
Prevent the Noise from Combo Jack
while system entry into S3 / S4 /S5
2
EMC@
DA1
L03ESDL5V0CC3-2_SOT23-3
AUD_NB_MUTE#
2
1
@EMC@ CA4
680P_0402_50V7K
2
2
1
@EMC@ CA3
220P_0402_50V7K
2
1
@EMC@ CA2
220P_0402_50V7K
1
5
2
4
1
EMC@ LA3 1
EMC@ LA11 1
@EMC@ CA1
680P_0402_50V7K
2
AUD_HP_OUT_R
SLEEVE
A
6
AUD_HP_NB_SENSE
RA21
100K_0402_5%
1
+RTC_CELL
QA2B
DMN66D0LDW-7_SOT363-6
4
3
+3.3V_RUN_AUDIO
AUD_HP_OUT_R
RA1
10K_0402_5%
2
2
PAD-OPEN1x1m
@ PJP6
@EMC@
RA37
0_0402_5%
Digital Mic (Goliad MLK no single Mic)
+5V_RUN_AUDIO
@ PJP10
AUD_HP_OUT_L
4.7U_0603_6.3V6K
2
2
PAD-OPEN1X2m
1
place at AGND and DGND plane
Add for solve
pop noise and
detect issue
2 1
2 1
<35>
1
1
2
3
AUD_HP_NB_SENSE
RA24
4.7K_0402_5%
2
G
@
CA41
0.1U_0402_25V6
QA1
L2N7002WT1G_SC-70-3
D
S
DA5
RB751S40T1G_SOD523-2
RA25
4.7K_0402_5%
DA4
RB751S40T1G_SOD523-2
+MIC1_VREFO_L
CIS Link OK
Place CA12 & CA13
close to Audio Jack
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
Title
Codec _ALC3235
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
Rev
0.1
21
of
48
2
1
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
Title
DP 1.2 MST HUB
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
Rev
0.1
22
of
48
5
4
3
2
1
+3.3V_TSP
DLW21HN900HQ2L_4P
4
3
4
3
ACES_50398-04041-001
1
<12>
EMC@ LV1 1
DISP_ON
LCD_TST
1
D
LED CONN
JLED1
ESD depop location
<10>
+LCDVDD
EDP_CPU_AUX#_C
EDP_CPU_AUX_C
EDP_CPU_LANE_P0_C
EDP_CPU_LANE_N0_C
EDP_CPU_LANE_P1_C
EDP_CPU_LANE_N1_C
CV1 2
CV2 2
CV3 2
CV4 2
CV5 2
CV6 2
LCD_CBL_DET#
1
1
1
1
1
1
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
20130822
EDP_CPU_AUX# <10>
EDP_CPU_AUX <10>
EDP_CPU_LANE_P0
<10>
EDP_CPU_LANE_N0
<10>
EDP_CPU_LANE_P1
<10>
EDP_CPU_LANE_N1
<10>
<12>
1
S
D
1
2
2
2
BAT54CW_SOT323-3
RV2
4.7K_0402_5%
RV1
4.7K_0402_5%
1
<36>
PANEL_BKEN_EC
D
S
2
G
3.3V_TS_EN
<10>
1
DISP_ON
BIA_PWM_EC
PANEL_BKLEN
1
BIA_PWM_EC
<12>
3
<10>
3
2
EDP_BIA_PWM
3
<35>
QV7
L2N7002WT1G_SC-70-3
EDP_BIA_PWM
1
Close to JEDP1.1
DV2
3
+3.3V_RUN
QV8
LP2301ALT1G_SOT23-3
2
G
1
@
1
@
2
2
2
1
1
@
2
@
Close to JEDP1.40
+3.3V_TSP
RV6
10K_0402_5%
CA7
0.1U_0402_25V6
Close to JEDP1.33
C
+3.3V_RUN
+3.3V_RUN
CZ2
0.1U_0402_16V4Z
Close to JEDP1.11,12
+3.3V_TSP
CZ1
0.1U_0402_25V6
@
+3.3V_CAM
CV8
0.1U_0402_25V6
1
+LCDVDD
CV7
0.1U_0603_50V7K
2
8
7
ACES_50277-0060N-001
<36>
DV1
1
CONN@
GND2
6 GND1
5 6
4 5
3 4
2 3
1 2
1
+5V_ALW
<39> BATT_WHITE_LED#
<39> BATT_YELLOW_LED#
<39> PANEL_HDD_LED#
<39> BREATH_WHITE_LED#
For Touchscreen
+BL_PWR_SRC
2
<11>
@EMC@
C
BIA_PWM
<11>
USBP4+
DV4
2
BIA_PWM
BLM15BB221SN1D_2P~D
EDP_CPU_HPD
USBP4-
AZC199-02SPR7G_SOT23-3
CONN@
Close to JEDP1.24~27
2
3
2
2
<21>
1
1
1
+BL_PWR_SRC
2
<12>
2
CAM_MIC_CBL_DET#
pin 15: LOOP_BACK
2
<21>
DMIC_CLK
+3.3V_RUN
+3.3V_CAM
USBP5_DUSBP5_D+
1
LV27EMC@
3
DMIC0
@EMC@ CA6
100P_0402_50V8J
G1
G2
G3
G4
G5
JEDP1
USBP4_DUSBP4_D+
TOUCH_PANEL_INTR#
@EMC@ CA5
100P_0402_50V8J
D
41
42
43
44
45
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
BAT54CW_SOT323-3
B
B
Backlight POWER
WebCAM
+BL_PWR_SRC
+LCDVDD
+3.3V_ALW
@ CV9
2
1
2
3
ENVDD_PCH
BAT54CW_SOT323-3
1
QV2
L2N7002WT1G_SC-70-3
RV5
change back to CCD_OFF at Goliad project
USBP5+
<11>
USBP5-
1
1
2
4
3
2
USBP5_D+
3
USBP5_D-
A
4
1
4
EN
AP2821KTR-G1_SOT23-5
2nd source SA00003AR00
3
S
1
D
2
47K_0402_5%
3
2
G
LZ1 EMC@
<11>
EN_LCDPWR
2
1
2
3
1
D
S
2
<10,36>
GND
VIN
1
PWR_SRC_ON
1
VIN
2
2
LCD_VCC_TEST_EN
RV3
100K_0402_5%
2
G
<36>
5
CV10
0.01U_0402_16V7K
AO6405_TSOP6
CV12
0.1U_0603_50V7K
3.3V_CAM_EN#
VOUT
10U_0603_6.3V6M
DV3
G
RV4
100K_0402_5%
CV11
1000P_0402_50V7K
3
1
S
4
QZ1
LP2301ALT1G_SOT23-3
1
UV24
1
D
6
5
2
1
@
QV1
+3.3V_RUN
2
+PWR_SRC
+3.3V_CAM
<12>
LCDVDD POWER
<36>
A
EN_INVPWR
DLW21HN900HQ2L_4P
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
eDP CONN & Touch screen
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
23
of
48
5
4
3
2
1
+5V_RUN
+VHDMI_VCC
4
3
GND
2
TMDS_CON_CLK
3
TMDS_CON_CLK#
1
1
2
2
4
2
1
2
1
CV27
10U_0603_6.3V6M
HDMI_LANE_N3
@ CV30
0.1U_0402_10V7K
HDMI_LANE_P3
<25>
+VHDMI_VCC
UV10
AP2330W-7_SC59-3
LV3 EMC@
<25>
D
1
2
2.2K_0402_5%
RV9
IN
1
RV7
@
<25>
OUT
HDMI_DAT_AUX#
2
2.2K_0402_5%
3
HDMI_DAT_AUX#
1
1
HDMI_CLK_AUX
2
D
HDMI_CLK_AUX
CV24
0.1U_0402_16V4Z
<25>
HDMI connector
DLW21HN900HQ2L_4P
LV6 EMC@
<25>
HDMI_LANE_P2
<25>
HDMI_LANE_N2
1
1
2
4
3
2
TMDS_CON_P2
3
TMDS_CON_N2
JHDMI1 CONN@
<25>
4
HDMI_DAT_AUX#
HDMI_CLK_AUX
DLW21HN900HQ2L_4P
LV10
<25>
HDMI_LANE_P1
<25>
HDMI_LANE_N1
1
4
2
EMC@
1
2
4
3
2
TMDS_CON_P1
3
TMDS_CON_N1
10K_0402_5%
1
@ RV8
HDMI_CEC
TMDS_CON_CLK#
TMDS_CON_CLK
TMDS_CON_N0
DLW21HN900HQ2L_4P
C
LV12
<25>
1
HDMI_LANE_P0
TMDS_CON_P0
TMDS_CON_N1
EMC@
1
2
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDMI_HPD
+3.3V_RUN
2
TMDS_CON_P0
3
TMDS_CON_N0
TMDS_CON_P1
TMDS_CON_N2
TMDS_CON_P2
<25>
4
HDMI_LANE_N0
4
3
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
C
LCN_AUF05-1922S10-0019
DLW21HN900HQ2L_4P
20130730 DC232002PB0 CIS Link OK
+3.3V_RUN
CV511
0.1U_0402_25V6
UV502
CPU_DPC_AUX
SW_mDP_AUX_C
0.1U_0402_10V7K
CV513
2
1
SW_mDP_AUX#_C
0.1U_0402_10V7K
mDP_AUX#_C
CPU_DPC_AUX#
BE0
A0
3
VCC
BE3
B0
4
5
A3
BE1
A1
6
7
B3
BE2
B1
A2
GND
B2
14
13
12
<10>
DDI2_LANE_P1
<10>
DDI2_LANE_N1
2
CV504
2
CV505
2
CV506
AP2337SA-7_SOT23-3
<10>
<10>
DDI2_LANE_P0
<10>
DDI2_LANE_N0
CV507
2
CV508
1 mDP_LANE_P0_C
0.1U_0402_10V7K
1 mDP_LANE_N0_C
0.1U_0402_10V7K
mDP_AUX#_C
mDP_LANE_N2_C
mDP_AUX_C
mDP_LANE_P2_C
11
10
9
CPU_DPC_CTRLDAT
<10>
mDP_LANE_N3_C
mDP_LANE_N1_C
mDP_LANE_P3_C
mDP_LANE_P1_C
8
+5V_RUN
+3.3V_RUN
+3.3V_RUN
1
1
RV502
1
0
HDMI
2
1
D
5
mDP
3
DPC_HPD
1
mDP_HPD
RV505
2
100K_0402_5%
2
100K_0402_5%
2
5.1M_0402_5%
1
1M_0402_5%
2
100K_0402_5%
mDP_AUX#_C
mDP_AUX_C
DPB_MB_P14
mDP_LANE_N0_C
mDP_CA_DET
mDP_LANE_P0_C
mDP_HPD
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DPB_MB_P14
DP_PWR
GND
AUX_CH_N
LANE2_N
AUX_CH_P
LANE2_P
GND
GND
LANE3_N
LANE1_N
LANE3_P
LANE1_P
GND
GND
CONFIG2
LANE0_N
CONFIG1
LANE0_P
HOT-PLUG
GND
CONN@
24
23
22
21
GND4
GND3
GND2
GND1
ACON_MAR2E-20K1800
mDP_CA_DET
A
mDP_HPD
QV501
L2N7002WT1G_SC-70-3
20130730 DC060008GB0
CIS Link OK
DELL CONFIDENTIAL/PROPRIETARY
QV502
L2N7002WT1G_SC-70-3
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
function
1
<10>
S
mDP_CA_DET
S
2
G
mDP_CA_DET
2
RV504
mDP_CA_DET#
D
RV503
G
2
RV507
100K_0402_5%
1
RV501
A
1
mDP connector
1 mDP_LANE_P1_C
0.1U_0402_10V7K
1 mDP_LANE_N1_C
0.1U_0402_10V7K
JmDP1
CPU_DPC_CTRLCLK
2
B
OUT
DDI2_LANE_N2
1
2
1 mDP_LANE_P2_C
0.1U_0402_10V7K
1 mDP_LANE_N2_C
0.1U_0402_10V7K
GND
<10>
2
CV503
1 mDP_LANE_P3_C
0.1U_0402_10V7K
1 mDP_LANE_N3_C
0.1U_0402_10V7K
PI3C3125LEX_TSSOP14~D
1
<10>
mDP_AUX_C
1
2
3
<10>
CV512
2
1
DDI2_LANE_P2
2
CV502
3
2
<10>
2
CV501
2
1
DDI2_LANE_N3
UV501
IN
@
+3.3V_RUN
DDI2_LANE_P3
<10>
2
CV509
.01U_0402_16V7K
CV510
0.1U_0402_16V4Z
AUX/DDC SW for DDI2 to Mini DP
B
<10>
+VDISPLAY_VCC
1
4
3
2
Title
HDMI CONN
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
24
of
48
5
4
3
2
1
2 WIGIG_AUX#
100K_0402_5%
1
2 PS8339B_IN_CA_DET
100K_0402_5%
1
2 WIGIG_AUX
100K_0402_5%
1
2 PS8339B_OUT_CA_DET
1M_0402_5%
@ RV68
G12 UMA PS8339+PS8338
RV554
G12 Entry
PS8339
RV67
PS8339
+3.3V_RUN
@ RV60
4.7K_0402_5%
2
1
@ RV58
4.7K_0402_5%
2
1
RV57
4.7K_0402_5%
2
1
@ RV56
4.7K_0402_5%
2
1
RV55
4.7K_0402_5%
2
1
@ RV54
4.7K_0402_5%
2
1
@ RV551
4.7K_0402_5%
2
1
@ RV51
4.7K_0402_5%
2
1
PS8339
<10>
<10>
DDI1_LANE_P0
DDI1_LANE_N0
<10>
<10>
DDI1_LANE_P1
DDI1_LANE_N1
<10>
<10>
DDI1_LANE_P2
DDI1_LANE_N2
<10> DDI1_LANE_P3
<10> DDI1_LANE_N3
G14D_En PS8339+PS8338
G14U_En
1
2
2
PS8339B_DP_CFG0
PS8339B_MODE_SW
G14 DSC PS8339+PS8338
G14 UMA
2
CV69
0.1U_0402_25V6
1
RV555
CV66
0.1U_0402_25V6
D
DP SWITCH
1
CV62
0.01U_0402_16V7K
PCB
2
CV61
0.01U_0402_16V7K
1
+3.3V_RUN
1
+3.3V_RUN
<10>
<10>
<10>
<10>
CPU_DPB_AUX
CPU_DPB_AUX#
UV7
14
28
41
56
44
45
38
CV71 1
CV72 1
2 0.1U_0402_25V6
2 0.1U_0402_25V6
DDI1_LANE_P0_C
DDI1_LANE_N0_C
3
4
CV73 1
CV74 1
2 0.1U_0402_25V6
2 0.1U_0402_25V6
DDI1_LANE_P1_C
DDI1_LANE_N1_C
6
7
CV75 1
CV76 1
2 0.1U_0402_25V6
2 0.1U_0402_25V6
DDI1_LANE_P2_C
DDI1_LANE_N2_C
9
10
CV77 1
CV78 1
2 0.1U_0402_25V6
2 0.1U_0402_25V6
DDI1_LANE_P3_C
DDI1_LANE_N3_C
12
13
CV79 1
CV80 1
2 0.1U_0402_25V6
2 0.1U_0402_25V6
CPU_DPB_AUX_C
CPU_DPB_AUX#_C
52
51
CPU_DPB_CTRLCLK 50
CPU_DPB_CTRLDAT 49
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
PS8339B_IN_CA_DET
PS8339B_TMDS_DDCBUF
<10>
DPB_HPD
11
5
VDD33
VDD33
VDD33
VDD33
1
PS8339B_TMDS_DDCBUF 2
2
PS8339B_INPUT_EQ
PS8339B_DP_CFG0
2
RV66
4.7K_0402_5%
2
1
RV65
4.7K_0402_5%
2
1
@
RV63
4.7K_0402_5%
2
1
@ RV64
4.7K_0402_5%
2
1
RV62
4.7K_0402_5%
2
1
@
@ RV61
4.7K_0402_5%
2
1
PS8339B_MODE_SW
@ RV550
4.7K_0402_5%
2
1
@ RV52
4.7K_0402_5%
2
1
8
27
4.99K_0402_1%
RV50
PS8339B_DP_CFG1
1
1
PS8339B_TMDS_RT
DP_D2p
DP_D2n
IN_D0p
IN_D0n
DP_D3p
DP_D3n
IN_D1p
IN_D1n
DP_AUXp_SCL
DP_AUXn_SDA
DP_HPD
IN_D2p
IN_D2n
DP_CA_DET
IN_D3p
IN_D3n
DP_CFG1
IN_AUXp
IN_AUXn
TMDS_CH0p
TMDS_CH0n
IN_DDC_SCL
IN_DDC_SDA
TMDS_CH1p
TMDS_CH1n
IN_CA_DET
TMDS_CH2p
TMDS_CH2n
IN_HPD
TMDS_CLKp
TMDS_CLKn
2.2U_0402_6.3V6M
CV60
PS8339B_TMDS_PRE
C
DP_D1p
DP_D1n
DP_CFG0/SCL_CTL
SW/SDA_CTL
I2C_CTL_EN
PS8339B_INPUT_EQ
PS8339B_MODE
DP_D0p
DP_D0n
46
PS8339B_MODE
53
CEXT
TMDS_SCL
TMDS_SDA
TMDS_DDCBUF
TMDS_HPD
PEQ
REXT
PD
MODE
TMDS_RT
TMDS_PRE
GND
GND
GND
Thermal/GND
40
39
37
36
34
33
31
30
55
54
32
WIGIG_LANE_P0
WIGIG_LANE_N0
<30>
<30>
WIGIG_LANE_P1
WIGIG_LANE_N1
<30>
<30>
WIGIG_LANE_P2
WIGIG_LANE_N2
<30>
<30>
WIGIG_LANE_P3
WIGIG_LANE_N3
<30>
<30>
WIGIG_AUX <30>
WIGIG_AUX# <30>
WIGIG_HPD
<30>
42
PS8339B_OUT_CA_DET
29
PS8339B_DP_CFG1
19
18
HDMI_LANE_P0
HDMI_LANE_N0
<24>
<24>
22
21
HDMI_LANE_P1
HDMI_LANE_N1
<24>
<24>
25
24
HDMI_LANE_P2
HDMI_LANE_N2
<24>
<24>
16
15
HDMI_LANE_P3
HDMI_LANE_N3
<24>
<24>
48
47
HDMI_CLK_AUX
HDMI_DAT_AUX#
<24>
<24>
17
23
20
D
HDMI_HPD
<24>
C
PS8339B_TMDS_RT
PS8339B_TMDS_PRE
26
35
43
57
PS8339BQFN56GTR2-A0_QFN56_7X7
MODE = L: Control Switching Mode, HDMI ID disable
= H: Automatic Switching Mode, HDMI ID disable
= M: Automatic Switching Mode, HDMI ID enable
TMDS_PRE = L: no pre-emphasis
= H: 1.5dB pre-emphasis
= M: 3.0dB pre-emphasis
B
TMDS_RT = L: Standard open drain driver
= H: Open drain driver with termination resistors
B
TMDS_DDCBUF = L: DDC pass through
= H: DDC active buffer
= M: DDC pass through with 40 kohm pull up resistor
PEQ = L: default, LEQ, compensate channel loss up to 12dB @ HBR2
= H: HEQ, compensate channel loss up to 15dB @ HBR2
= M: LLEQ, compensate channel loss up to 5dB @ HBR2
DP_CFG1 = L: default, auto test disable & input offset cancellation enable
= H: auto test enable & input offset cancellation enable
= M: auto test disable & input offset cancellation disable
DP_CFG0 = L: default, automatic EQ enable & AUX interception enable
= H: automatic EQ disable & AUX interception enable
= M: automatic EQ disable & AUX interception disable, no pre-emphasis, 800mVpp swing
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
DP SW
Size
Document Number
Rev
0.1
LA-A972P
Date:
Monday, March 17, 2014
Sheet
1
25
of
48
5
4
3
2
1
D
D
C
C
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
DP to VGA & VGA Conn
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
26
of
47
5
4
3
2
1
D
D
+3.3V_M
+3.3V_M_TPM
+3.3V_M_TPM
@ PJP11
1
2
1
+3.3V_SUS
9
8
+3.3V_RUN
+5V_RUN
<9> PLTRST_USH#
<35> USH_PWR_STATE#
<10,7> CONTACTLESS_DET#
@
@
1
+3.3V_SUS
2
1
2
1
1
AT97SC3205_TSSOP28~D
@
5
13
14
15
27
28
+3.3V_RUN
1
NBO_1
NBO_2
NBO_3
NBO_4
NBO_5
NBO_6
GND
GND
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
USBP6USBP6+
<36> USH_SMBCLK
<36> USH_SMBDAT
<35> BCM5882_ALERT#
+5V_RUN
C
JUSH1 CONN@
<11>
<11>
2
USH_PWR_STATE#
1M_0402_5%
RZ10
2
TESTBI
TESTI
1
2
17
6
7
1
MISO
MOSI
SPI_CLK
SPI_CS#
SPI_RST#
PIRQ#
GPIO_1
GPIO_2
GPIO_3
GPIO-Express-00
PP/GPIO
2
TPM_PIRQ#
26
23
21
22
16
20
RZ9
CZ12
0.1U_0402_25V6
2
SPI_DINTPM
SPI_DOTPM
SPI_CLKTPM
PCH_SPI_CS2#_R
12
CZ11
0.1U_0402_25V6
1
1
V_BAT
USH CONN
2
USH_SMBCLK
2.2K_0402_5%
2
USH_SMBDAT
2.2K_0402_5%
RZ8
VCC
VCC
VCC
VCC
@EMC@
CZ9
0.1U_0402_25V6
1
PCH_PLTRST#_EC
<12>
1
3
10
19
24
CZ10
0.1U_0402_25V6
@EMC@
RZ35
33_0402_5%
2
2 33_0402_5%
2 33_0402_5%
2 33_0402_5%
2 0_0402_5%
+3.3V_SUS
UZ1
25
18
11
4
SPI_CLKTPM
B
2
2
2
<20,30,36,9>
CZ7
2200P_0402_50V7K
RZ30 1
RZ29 1
RZ26 1
@ RZ17 1
<7> PCH_SPI_DIN
<7> PCH_SPI_DO
<7> PCH_SPI_CLK
<7> PCH_SPI_CS2#
CZ6
2200P_0402_50V7K
CZ5
4700P_0402_25V7K
@ CZ4
0.1U_0402_25V6
1
PAD-OPEN1x1m
C
<10,12>
USH_DET#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND
GND
21
22
CONCR_205200FW010
Close to JUSH1
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
USH & TPM
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
27
of
48
3
1
CL6
<12,36>
41
42
28
31
LAN_WAKE#
2
3
LAN_DISABLE#_R
SMBus Device Address 0xC8
MDI_PLUS3
MDI_MINUS3
SMB_CLK
SMB_DATA
LANWAKE_N
LAN_DISABLE_N
TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
32
34
33
35
XTALO
XTALI
9
10
LED0
LED1
LED2
1
1
1
2
1
2
2
GND
25MHZ_18PF_7V25000034
12
XTAL_OUT
XTAL_IN
VDD0P9_43
VDD0P9_11
VDD0P9_40
VDD0P9_22
VDD0P9_16
VDD0P9_8
EMC@
EMC@
6
VCT_LAN_R1
1
@ RL3
+RSVD_VCC3P3_1 RL6
CTRL0P9
VSS_EPAD
WGI218LM-QQ89-B0_QFN48_6X6~D
1
2
0_0402_5%
1 4.7K_0402_5%
2 5.6_0402_5%
2
LAN_TX1+L
RL23 1
2 5.6_0402_5%
LAN_TX2+L
LAN_TX2-L
LAN_TX1-L
RL24 1
2 5.6_0402_5%
LAN_TX3+L
LAN_TX3-L
LAN_TX2+L
RL25 1
2 5.6_0402_5%
LAN_TX2-L
RL26 1
2 5.6_0402_5%
LAN_TX3+L
RL27 1
2 5.6_0402_5%
LAN_TX3-L
RL28 1
2 5.6_0402_5%
+3.3V_LAN
4
2
+3.3V_LAN_OUT
1
@ RL8
15
19
29
+0.9V_LAN
47
46
37
0_0603_5%
+3.3V_LAN
LAN_TX0+L_R
1
2 5.6_0402_5%
RL22 1
5
CL30 EMC@
3.3P_0402_50V8J
LAN_TX0-L_R
LAN_TX1+L_R
CL31 EMC@
3.3P_0402_50V8J
LAN_TX1-L_R
LAN_TX2+L_R
CL32 EMC@
3.3P_0402_50V8J
D
LAN_TX2-L_R
LAN_TX3+L_R
CL33 EMC@
3.3P_0402_50V8J
LAN_TX3-L_R
Pin 6 is SVR_EN in Clarkville
43
11
40
22
16
8
+0.9V_LAN
LL1
TEST_EN
RBIAS
2
RL21 1
LAN_TX0-L
LAN_TX1+L
LAN_TX1-L
1
LAN_TX3+
LAN_TX3-
EMC@
EMC@
LAN_TX0+L
LAN_TX0+L
LAN_TX0-L
7
Idc_min=500mA
DCR=100mohm
2
REGCTL_PNP10 1
4.7UH_BRC2012T4R7MD_20%
49
Place CL3, CL4 and LL1 close to UL1
CL4
10U_0603_6.3V6M
2
30
RL13
3.01K_0402_1%
GND
RES_BIAS
RL12
1K_0402_5%
1
1
IN
CL14
27P_0402_50V8J
CL13
27P_0402_50V8J
Note:
+1.0V_LAN will work at 0.95V to 1.15V
4
OUT
2
YL1
3
LAN_TEST_EN
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TCK
JTAG
PAD~D
PAD~D
VDD3P3_15
VDD3P3_19
VDD3P3_29
VDD0P9_47
VDD0P9_46
VDD0P9_37
2
26
27
25
RL11
1M_0402_5%
2
1
1
1
1
2
2
2
2
2
0_0402_5%
VDD3P3_IN
VDD3P3_4
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
23
24
EMC@
EMC@
CL3
0.1U_0402_10V7K
CL8
0.1U_0402_10V7K
CL11
0.1U_0402_10V7K
CL10
0.1U_0402_10V7K
CL12
22U_0603_6.3V6M
2
CL9
0.1U_0402_10V7K
1
1
XTALO_R
@ RL10
RSVD_VCC3P3_1
LAN_DISABLE#_R
@ T88
@ T89
+0.9V_LAN
SVR_EN_N
LAN_TX2+
LAN_TX2-
2
2
12NH_0603CS-120EJTS_5%
12NH_0603CS-120EJTS_5%
2
2
12NH_0603CS-120EJTS_5%
12NH_0603CS-120EJTS_5%
2
2
12NH_0603CS-120EJTS_5%
12NH_0603CS-120EJTS_5%
2
2
12NH_0603CS-120EJTS_5%
12NH_0603CS-120EJTS_5%
1
1
LL23
LL24
1
1
LL25
LL26
1
1
LL27
LL28
CL7
1U_0603_10V6K
@ RL9
10K_0402_5%
<35>
PERp
PERn
MDI_PLUS2
MDI_MINUS2
20
21
1
EMC@ LL21
1
EMC@ LL22
2
1
CL5
PETp
PETn
MDI_PLUS1
MDI_MINUS1
LAN_TX1+
LAN_TX1-
2
2
0_0402_5%
PCIE_PTX_GLANRX_P3
PCIE_PTX_GLANRX_N3
PE_CLKP
PE_CLKN
LAN_TX0+
LAN_TX0-
17
18
1
1
@ RL7
<11>
<11>
<7> LAN_SMBCLK
<7> LAN_SMBDATA
2
1
PM_LANPHY_ENABLE
1
<12,9>
@ RL5
10K_0402_5%
D
2
CL2
38
39
13
14
1
PCIE_PRX_GLANTX_N3
1 PCIE_PRX_GLANTX_P3_C
0.1U_0402_10V7K
1 PCIE_PRX_GLANTX_N3_C
0.1U_0402_10V7K
2 PCIE_PTX_GLANRX_P3_C
0.1U_0402_10V7K
2 PCIE_PTX_GLANRX_N3_C
0.1U_0402_10V7K
MDI_PLUS0
MDI_MINUS0
2
<11>
2
CL1
CLK_REQ_N
PE_RST_N
1
<7> CLK_PCIE_LAN
<7> CLK_PCIE_LAN#
PCIE_PRX_GLANTX_P3
44
45
1
<11>
+3.3V_LAN
48
36
LANCLK_REQ#
PLTRST_LAN#
MDI
2
@ RL4
<7>
<9>
PCIE
TP_LAN_JTAG_TMS
10K_0402_5%
TP_LAN_JTAG_TCK
10K_0402_5%
1
LANCLK_REQ#
4.7K_0402_5%
SMBUS
2
LED
2
1
@ RL2
1
1
UL1
1
@ RL1
2
+3.3V_LAN
2
Layout Notice : Place bead as
close UL4 as possible
2
4
2
5
C
C
1
+3.3V_SUS
PJP25
PAD-OPEN1x1m
@
+3.3V_ALW
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
1
CZ43
2
470P_0402_50V7K
1
CZ42
2
470P_0402_50V7K
PJP27
10
9
8
1
+3.3V_WLAN_UZ8
AUX_EN_WOWL
100K_0402_5%
2
2
0.1U_0402_10V7K
15
TPS22966DPUR_SON14_2X3
1
RZ38
2
11
2
10/15 change to
SP050006Y00 (S X'FORM_ NS692417 LAN)
+3.3V_WLAN
PAD-OPEN1x3m
@
@
CZ53
0.1U_0402_10V7K
GPAD
+3.3V_SUS_UZ8 1
@ CZ41
12
1
VBIAS
+3.3V_LAN
14
13
CL19
0.1U_0402_10V7K
6
7
CT1
CL18
470P_0402_50V7K
5
AUX_EN_WOWL
AUX_EN_WOWL
VOUT1
VOUT1
ON1
1
+5V_ALW
<30,35>
VIN1
VIN1
2
4
2
3
SUS_ON
1
1
2
<36,42>
2
UZ8
RJ45 LOM circuit
+3.3V_LAN:20mils
TL1
JLOM1
LAN_TX3-L_R
1
1:1
TD1+
TX1+
1
LAN_ACTLED_YEL#
RL14
2
10
LAN_ACTLED_YEL_R#
150_0402_5%
9
LAN_TX3+L_R 2
TD1TX1-
23 NB_LAN_TX3+
+3.3V_LAN
B
3
4
<35>
TC7SH08FU_SSOP5
LAN_TX1-L_R
LAN_TX1+L_R 6
LAN_TX2-L_R
QL1A
DMN66D0LDW-7_SOT363-6
6
LOM_ACTLED_YEL# 1
4
5
TDCT1
TXCT1
TDCT2
TD2+
TXCT2
TX2+
1:1
22
7
TD2-
TX2-
1:1
TD3+
TX3+
NB_LAN_TX3-
8
NB_LAN_TX3+
7
NB_LAN_TX1-
6
NB_LAN_TX2-
5
NB_LAN_TX2+
4
NB_LAN_TX1+
3
NB_LAN_TX0-
2
NB_LAN_TX0+
1
Z2805
21
Z2807
20 NB_LAN_TX1-
1
1
WLAN_LAN_DISBL#
2
Y
A
2
P
B
G
2
3
1
LOM_SPD10LED_GRN#
CL17
0.47U_0603_10V7K
LOM_SPD100LED_ORG#
0.1U_0402_10V7K
UL2
CL16
0.47U_0603_10V7K
5
@ CL15
1
2
19 NB_LAN_TX1+
1
LED_10_GRN#
RL19
LED_100_ORG# 1
RL20
18 NB_LAN_TX2-
2
11
LED_10_GRN_R#
150_0402_5%
2
LED_100_ORG_R#
150_0402_5%
13
12
LAN_ACTLED_YEL#
LAN_TX2+L_R 8
Yellow LEDYellow LED+
PR4PR4+
PR3PR3+
PR2+
PR1GND
PR1+
GND
Green-Orange LED+
SANTA_130456-341
LAN_TX0+L_R 12
TD4-
TX4-
20130726 same as Goliad
Z2806
15
Z2808
14 NB_LAN_TX0-
13 NB_LAN_TX0+
1 75_0402_1%
TXCT4
TX4+
1:1
16
1 75_0402_1%
TDCT4
TD4+
TXCT3
1 75_0402_1%
TDCT3
1 75_0402_1%
1
10
LAN_TX0-L_R 11
14
Orange LED-
17 NB_LAN_TX2+
1
2
2
5
SYS_LED_MASK#
CL21
0.47U_0603_10V7K
LED_100_ORG#
CL20
0.47U_0603_10V7K
QL1B
DMN66D0LDW-7_SOT363-6
4
3
LOM_SPD100LED_ORG#
9
<35,39>
15
Green LED-
2
SYS_LED_MASK#
B
PR2-
rev1
TD3TX3-
SYS_LED_MASK#
CONN@
24 NB_LAN_TX3-
NS692417
1
CL22
2
EMC@
150P_1808_2.5KV8J
RL18 2
+GND_CHASSIS
use 40mil trace if necessary
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
QL2B
DMN66D0LDW-7_SOT363-6
4
3
5
RL17 2
GND
CHASSIS
SYS_LED_MASK#
RL16 2
RL15 2
A
LED_10_GRN#
2
QL2A
DMN66D0LDW-7_SOT363-6
6
LOM_SPD10LED_GRN#1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
A
4
3
2
Title
LAN
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
28
of
48
A
B
+3.3V_MMI
C
D
E
CR3 close to U27.9
CR1 CR2 close to U27.35
1
2
1
2
1
2
2
1
2
CR2
0.1U_0402_25V6
CR3
0.1U_0402_25V6
CR6
0.1U_0402_25V6
CR4
0.1U_0402_25V6
1
CR1
4.7U_0603_6.3V6K
CR4 close to U27.42
CR6 close to U27.23
1
+3.3V_MMI
1
+3.3V_MMI
UR1
PCIE_PTX_MMIRX_P1
PCIE_PTX_MMIRX_N1
PCIE_PRX_MMITX_P1
PCIE_PRX_MMITX_N1
RR2
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
2
PE_REXT
191_0402_1%
PCIE_PTX_MMIRX_P1_C
PCIE_PTX_MMIRX_N1_C
4
CR24 1
CR25 1
CR26 1
CR27 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PCIE_PRX_MMITX_P1_C
PCIE_PRX_MMITX_N1_C
7
8
2
<7>
<7>
RR6
100K_0402_5%
1
+3.3V_MMI
<12>
<6,7>
14
16
MEDIACARD_IRQ#
17
MMICLK_REQ#
IO_LDOSEL
@ RR8
100K_0402_5%
1
15
PLTRST_MMI#
MEDIACARD_PWREN
IO_LDOSEL
2
2
3
CLK_PCIE_MMI#
CLK_PCIE_MMI
<9>
6
5
18
22
+3.3V_RUN_CARD
24
+1.8V_RUN_CARD
1
1
1
2
+1.8V_RUN_CARD
2
SD_SKT_18VOUT
2
SD_SKT_33VOUT
MAIN_LDO_VIN
1
2
AUX _33VIN
MAIN_LDO_12VOUT
CR31 near UR1.22
CORE_12VCCD
SD_WPI
SD_CD#
UHSII_12VCCAIN/NC
UHSII_12VCCAIN/NC
UHSII_12VCCAIN/NC
SD_CLK
SD_CMD
PE_12VCCAIN
MMC_D7
MMC_D6
MMC_D5
MMC_D4
SD_D3
SD_D2
SD_D1
SD_D0
PE_REXT
PE_RXP
PE_RXM
PE_TXP
PE_TXM
SD_RCLK_M/NC
SD_RCLK_P/NC
SD_D1P/NC
SD_D1M/NC
SD_D0M/NC
SD_D0P/NC
PE_REFCLKM
PE_REFCLKP
PE_RST#_GATE#
MAIN_LDO_EN
SD_REXT/NC
20
21
SDWP
SD/MMCCD#
43
45
SD/MMCCLK_R
SD/MMCCMD
RR1
1 EMC@ 2 10_0402_5%
39
40
44
46
47
48
37
38
SD/MMCDAT3@EMC@ RR31
SD/MMCDAT2@EMC@ RR41
SD/MMCDAT1
SD/MMCDAT0
29
30
32
33
34
35
SD_UHS2_D1P
SD_UHS2_D1N
SD_UHS2_D0N
SD_UHS2_D0P
26
SD/MMCCLK
1
1
SD_SKT_33VIN
1
SD_REXT
RR5
2 0_0402_5%
2 0_0402_5%
2
2
2
1
1
2
1
1
36
31
28
1
<11>
<11>
+3.3V_RUN_CARD
2
SD/MMCDAT3_R
SD/MMCDAT2_R
EMI solution for SD card
CR34 near UR1.24
@EMC@ CR23
5P_0402_50V8C
CR22
0.1U_0402_25V6
CR21
0.1U_0402_25V6
CR18
4.7U_0603_6.3V6K
CR19
0.1U_0402_25V6
2
41
+SD_IO_LDO
SD_33VCCD
1
2
1
1
2
2
1
2
2
1
10
+AUX_LDO
25
CR34
4.7U_0603_6.3V6K
11
12
CR31
1U_0402_6.3V6K
13
<11>
<11>
AUX_LDO_CAP
UHSII_33VCCAIN/NC
CR17
1U_0402_6.3V6K
23
If support RTD3 cold the AUX and MAIN power rail should be
use different power rail; for RTD3 hot please keep this circuit
+1.2V_LDO
2
OZ777FJ2LN
PE_33VCCAIN
SD_IO_LDO_CAP
42
CR15
0.1U_0402_25V6
1
9
27
CR14
4.7U_0603_6.3V6K
CR13
0.1U_0402_25V6
CR10
0.1U_0402_25V6
CR9
4.7U_0603_6.3V6K
CR8
0.1U_0402_25V6
CR7
4.7U_0603_6.3V6K
+1.2V_LDO
2
EMI depop location
2
4.7K_0402_1%
DEV_WAKE#
CLKREQ#
LED#
IO0_LDOSEL
GND
19
49
OZ777FJ2LN_QFN48_6X6
please routing daisy chain
1. from UR1.38 (SD_D0) -> UR1.30 (SD_RCLK_P) -> LR3.4
2. From UR1.37 (SD_D1) -> UR1.29 (SD_RCLK_N) -> LR3.1
R231,R297,R306,R315,R333,R337 for EMI solution
+3.3V_MMI
3
3
+3.3V_RUN
@
1
+3.3V_MMI
PJP26
2
PAD-OPEN1x1m
1
RR15
2 MEDIACARD_PWREN
10K_0402_5%
CONN@
JSD1
2
1
2
RR11
1M_0402_5%
CR35
0.1U_0402_25V6
1
+3.3V_RUN_CARD
+1.8V_RUN_CARD
SD/MMCCMD
SD/MMCCLK
4
14
2
5
SD/MMCCD#
SDWP
18
19
SD/MMCDAT0
SD/MMCDAT1
SD/MMCDAT2_R
SD/MMCDAT3_R
SD_UHS2_D0P
SD_UHS2_D0N
SD_UHS2_D1P
SD_UHS2_D1N
7
8
9
1
11
12
16
15
3
6
10
13
17
VDD/VDD1
VDD2
CMD
CLK
CARD DETECT
WRITE PROTEC
DAT0/RCLK+
DAT1/RCLKDAT2
CD/DAT3
D0+
DOD1+
D1VSS1
VSS2
VSS3
VSS4
VSS5
20
21
22
23
24
25
26
GND1
GND2
GND3
GND4
GND5
GND6
GND7
ALPS_SCDADA0101_NR
4
4
20130726 SP070011L00 CIS Link OK
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Title
Card Reader
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
E
Rev
0.1
29
of
48
5
4
3
2
1
NGFF slot A Key A
NGFF for UMA
+3.3V_WLAN
JNGFF1
WIGIG_HPD
CZ21 1
CZ22 1
<11>
<11>
CLK_PCIE_WLAN
CLK_PCIE_WLAN#
WLANCLK_REQ#
PCIE_WAKE#
PCIE_WAKE#
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PCIE_PTX_WIGIGRX_P5_C
PCIE_PTX_WIGIGRX_N5_C
PCIE_PRX_WIGIGTX_P5
PCIE_PRX_WIGIGTX_N5
<7>
<7>
CLK_PCIE_WIGIG
CLK_PCIE_WIGIG#
69
AUX_EN_WOWL
<36>
EC_32KHZ_MEC5085
1
2
4
SUSCLK
WIGIG_32KHZ_R
1
@ RZ56
2
0_0402_5%
1
RZ57
2
0_0402_5%
WIGIG_32KHZ
C
TC7SH08FU_SSOP5
+3.3V_WLAN
1
2
2
CZ19
4.7U_0603_6.3V6K
WLAN_WIGIG60GHZ_DIS#_R
CZ66
47P_0402_50V8J
2
CZ18
0.1U_0402_25V6
1
<12,7>
68
CZ17
0.1U_0402_25V6
BT_RADIO_DIS#
WIGIGCLK_REQ#
PCIE_WAKE#
DZ1
RB751S40T1G_SOD523-2
<35>
<20,27,36,9>
PCH_PLTRST#_EC
CZ16
0.047U_0402_16V4Z
1
<25>
<25>
WIGIG_32KHZ
PCH_PLTRST#_EC
PCH_PLTRST#_EC
BT_RADIO_DIS#_R
WLAN_WIGIG60GHZ_DIS#_R
CZ20
0.047U_0402_16V4Z
WLAN_WIGIG60GHZ_DIS#
GND
WIGIG_LANE_N0
WIGIG_LANE_P0
PCH_CL_RST1# <7>
PCH_CL_DATA1 <7>
PCH_CL_CLK1 <7>
@ CZ15
0.1U_0402_25V6
<35>
<9>
UZ12
Y
A
3
C
B
GND
<25>
<25>
BELLW_80148-3521
G
<28,35>
P
5
+3.3V_ALW
D
WIGIG_LANE_N1
WIGIG_LANE_P1
1
PCIE_PTX_WIGIGRX_P5
PCIE_PTX_WIGIGRX_N5
PCIE_PTX_WLANRX_P4_C
PCIE_PTX_WLANRX_N4_C
2
2
WIGIG_AUX# <25>
WIGIG_AUX <25>
1
<7>
<7>
<12,7>
<35>
<11>
<11>
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PCIE_PRX_WLANTX_P4
PCIE_PRX_WLANTX_N4
1
1 CV150
CV149
1
1 CV152
CV153
1
1 CV156
CV157
2
2
@
2
<11>
<11>
2
2
2
CZ13 1
CZ14 1
BT_LED#
WIGIG_AUX#_C
WIGIG_AUX_C 0.1U_0402_25V6
0.1U_0402_25V6
WIGIG_LANE_N1_C
WIGIG_LANE_P1_C
0.1U_0402_25V6
0.1U_0402_25V6
WIGIG_LANE_N0_C
WIGIG_LANE_P0_C
0.1U_0402_25V6
0.1U_0402_25V6
2
PCIE_PTX_WLANRX_P4
PCIE_PTX_WLANRX_N4
WIGIG_LANE_N2_C
WIGIG_LANE_P2_C
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
1
<25>
<11>
<11>
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
WIGIG_LANE_N3_C
WIGIG_LANE_P3_C
2
WIGIG_LANE_N2
WIGIG_LANE_P2
2
2 0.1U_0402_25V6
0.1U_0402_25V6
2
2 0.1U_0402_25V6
0.1U_0402_25V6
WLAN_LED#
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
1
<25>
<25>
1
CV145 1
CV146
1
CV147 1
CV148
2
4
6
1
WIGIG_LANE_N3
WIGIG_LANE_P3
2
4
6
2
<25>
<25>
CONN@
1
3
5
7
1
D
1
3
5
7
USBP2+
USBP2-
2
<11>
<11>
BT_RADIO_DIS#_R
DZ2
RB751S40T1G_SOD523-2
STATE # CONFIG_0
0
B
CONFIG_1
CONFIG_2
CONFIG_3
Module Type
GND
GND
GND
SSD-SATA
GND
1
GND
HIGH
GND
GND
Power Rating TBD
PWR
Rail
SSD-PCIE
8
HIGH
GND
GND
GND
WWAN
14
HIGH
GND
HIGH
HIGH
HCA-PCIE
15
HIGH
HIGH
HIGH
HIGH
NA
Primary Power
Voltage
Tolerance
Peak
Aux Power
Normal
Normal
+3.3V
LED control circuit
B
3.3V_ALW for LID power
+3.3V_WLAN
1
5
2
1
12
11
10
9
8
7
6
5
4
3
2
1
RZ15
100K_0402_5%
4
BT_LED#
2
12
11
10
9
8
7
6
5
4
3
2
1
+3.3V_ALW
LID_CL#
<36,39>
RZ14
100K_0402_5%
GND2
GND1
2
JSH1
14
13
WLAN_LED#
1
3
WIRELESS_LED#
<35,39>
QZ2B
DMN66D0LDW-7_SOT363-6
6
QZ2A
DMN66D0LDW-7_SOT363-6
CONCR_205120FW010
CONN@
+3.3V_ALW
1
2
C263
0.1U_0402_16V4Z
A
A
@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
NGFF Card
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
30
of
40
5
4
3
2
1
+5V_USB_CHG_PWR
USB3RN1_D-
DI1
1 1
10 9
USB3RN1_D-
USB3RP1_D+
2 2
9 8
USB3RP1_D+
USB3TN1_D-
4 4
7 7
USB3TN1_D-
USB3TP1_D+
5 5
6 6
USB3TP1_D+
EMC@
LI1 EMC@
USBP0_DUSBP0_D+
2
3 3
8
D
USB3RN1_DUSB3RP1_D+
<11>
USB3TN1
2
1
USB3TP1_C
0.1U_0402_10V7K
1
2
1
USB3TN1_C
0.1U_0402_10V7K
4
CI5
CI4
1
2
4
3
2
USB3TP1_D+
3
USB3TN1_D-
DLW21HN900HQ2L_4P
+5V_ALW
PS_USBP0_D+
DLW21HN900HQ2L_4P
4
3
4
3
USBP0_D+
PS_USBP0_D-
1
USBP0_D-
1
LI3 EMC@
2
2
CONN@
VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+
10
11
12
13
GND
GND
GND
GND
SANTA_373070-2
D
20130730 DC23300C0B0 CIS Link OK
1
USB3TP1
1
2
3
4
5
6
7
8
9
1
L05ESDL5V0NA-4_SLP2510P8-10-9
LI2 EMC@
<11>
USB3TN1_DUSB3TP1_D+
DI2 EMC@
AZC199-02SPR7G_SOT23-3
2
DLW21HN900HQ2L_4P
3
USB3RN1_D-
2
3
3
3
USB3RP1_D+
1
4
2
2
2
CI3
0.1U_0402_25V6
4
USB3RN1
JUSB1
1
CI1
100U_1206_6.3V6M
<11>
1
USB3RP1
1
<11>
+5V_USB_CHG_PWR
UI3
1
+5V_ALW
2
CI19
0.1U_0402_25V6
1
<11>
<11>
2
3
USBP0USBP0+
<11>
13
USB_OC0#
4
ILIM_SEL
<35>
5
USB_PWR_SHR_VBUS_EN
IN
OUT
DM_OUT
DP_OUT
FAULT#
6
7
8
USB_PWR_SHR_EN#
10
11
PCB
PS_USBP0_D+
PS_USBP0_D-
EN
ILIM_LO
ILIM_HI
CTL1
CTL2
CTL3
NC
GND
GNDP
+5V_ALW
USB2 0
USB2 3
G12 UMA USB3102 NX3DV221
ILIM_SEL
CI19 near UI3.1
<35,36>
DP_IN
DM_IN
12
15
16
RI14
2
1
22.1K_0402_1%
G12 Entry
9
14
17
NA
NA
G14 DSC USB3102 NX3DV221
TPS2544RTER_WQFN16_3X3
C
RI13
2
C
G14 UMA USB3102 NX3DV221
1
ILIM_SEL
10K_0402_5%
G14D_En
NA
NA
G14U_En
NA
NA
+USB_RIGHT_PWR
LI9 EMC@
B
USB3RN4_D-
JUSB2
4
3
USB3RP4_D+
DLW21HN900HQ2L_4P
USB3RN4_D-
1 1
10 9
USB3RN4_D-
USB3RP4_D+
2 2
9 8
USB3RP4_D+
USB3TN4_D-
4 4
7 7
USB3TN4_D-
USB3TP4_D+
5 5
6 6
USB3TP4_D+
1
2
3
4
5
6
7
8
9
USBP3_DUSBP3_D+
CI10
0.1U_0402_25V6
USB3RP4
3
CI8
100U_1206_6.3V6M
<11>
4
EMC@
USB3RN4_DUSB3RP4_D+
2
3 3
USB3TN4_DUSB3TP4_D+
3
DI6
VBUS
DD+
GND
SSRXSSRX+
GND
SSTXSSTX+
CONN@
GND
GND
GND
GND
10
11
12
13
SANTA_373070-2
3
2
2
2
1
1
2
1
USB3RN4
1
<11>
2
B
LI8 EMC@
<11>
USB3TP4
2
1
CI28
2
CI27
1
USB3TN4_C
0.1U_0402_10V7K
USB3TP4_C
0.1U_0402_10V7K
1
4
1
4
2
3
2
3
USB3TN4_D-
DI3
8
1
USB3TN4
USB3TP4_D+
1
<11>
L05ESDL5V0NA-4_SLP2510P8-10-9
EMC@
AZC199-02SPR7G_SOT23-3
20130730 DC23300C0B0 CIS Link OK
DLW21HN900HQ2L_4P
+USB_RIGHT_PWR
+5V_ALW
2
4
3
2
USBP3_D+
3
USBP3_D-
2
1
1
4
2
USBP3-
1
CI12
0.1U_0402_25V6
<11>
USBP3+
@ CI11
10U_0603_6.3V6M
LI4 EMC@
<11>
1
UI2
<35>
1
2
3
4
USB_PWR_EN2#
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
USB_OC2#
<11,12>
SY6288D10CAC_MSOP8
DLW21HN900HQ2L_4P
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
USB3.0
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.1
LA-A972P
Sheet
1
31
of
48
4
3
2
LI6 EMC@
1
2
4
3
2
USB3RP2_D+
3
USB3RN2_D-
DI4
1 1
USB3RP2_D+
JUSB3
EMC@
USB3RN2_D-
2 2
9 8
USB3RP2_D+
USB3TN2_D-
4 4
7 7
USB3TN2_D-
USB3TP2_D+
5 5
6 6
USB3TP2_D+
<11>
USB3TP2
<11>
USB3TN2
1
USB3TP2_C
0.1U_0402_10V7K
1
2
1
USB3TN2_C
0.1U_0402_10V7K
4
CI13
1
2
4
3
2
USB3TP2_D+
3
USB3TN2_D-
2
LI5 EMC@
2
3 3
CI16
8
1
2
3
4
5
6
7
8
9
USBP1_R_DUSBP1_R_D+
1
USB3RN2_DUSB3RP2_D+
CI17
10 9
0.1U_0402_25V6K~D
CI14
100U_1206_6.3V6M
DLW21HN900HQ2L_4P
D
+USB_SIDE_PWR
USB3RN2_D-
2
USB3TN2_DUSB3TP2_D+
2
USB3RN2
3
4
2
<11>
1
USB3RP2
1
3
<11>
1
5
DI5 EMC@
AZC199-02SPR7G_SOT23-3
D
GND
GND
GND
GND
10
11
12
13
TAITW_PUBAUE-09FLBS1FF4H0
1
DLW21HN900HQ2L_4P
CONN@
VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+
1
L05ESDL5V0NA-4_SLP2510P8-10-9
+USB_SIDE_PWR
+5V_ALW
1
2
2
CI7
0.1U_0402_25V6
@ CI6
10U_0603_6.3V6M
1
UI1
<35>
USB_PWR_EN1#
1
2
3
4
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
USB_OC1#
<11,12>
SY6288D10CAC_MSOP8
C
C
<11>
USBP1+
<11>
USBP1-
4
1
DLW21HN900HQ2L_4P
3
4
3
1
LI7 EMC@
2
2
USBP1_R_D+
USBP1_R_D-
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
USB SW
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
32
of
48
5
4
3
2
1
D
D
C
C
NFC on USH/B
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
NFC
Size
Date:
Document Number
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
33
of
48
5
4
3
2
1
D
D
C
C
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
E-Dock
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.1
LA-A972P
Sheet
1
34
of
48
5
4
3
2
1
+3.3V_ALW
RPE9
8
7
6
5
1 USB_PWR_SHR_VBUS_EN
2
USB_PWR_EN2#
3
USB_PWR_EN1#
4
USB_PWR_SHR_EN#
<31,36>
100K_0804_8P4R_5%
+3.3V_ALW
VCC
UE3
<36> BC_DAT_ECE1099
<36> BC_CLK_ECE1099
<9>
SIO_SLP_WLAN#
@ T97 PAD~D
<28> LAN_DISABLE#_R
<21> AUD_HP_NB_SENSE
<21> AUD_NB_MUTE#
<23> PANEL_BKEN_EC
<28,30> AUX_EN_WOWL
@ T98 PAD~D
BC_DAT_ECE1099
BC_CLK_ECE1099
EXPRESS_DET#
USB_DB_DET#
32
33
39
40
1
2
3
4
5
6
7
1
2
1
RE21
2
GPIO10/KSI0
GPIO11/KSI1
GPIO12/KSI2
GPIO13/KSI3
GPIO14/KSI4
GPIO15/KSI5
GPIO16/KSI6
GPIO17/KSI7
GPIO20/KSO00
SMB_ADDR
10K_0402_5%
SYS_LED_MASK#
10K_0402_5%
<36>
BC_INT#_ECE1099
BC_INT#_ECE1099
34
SMB_ADDR
35
37
2
10K_0402_5%
1
38
RE24
PCIE_WAKE#_R
10K_0402_5%
BC_INT#/SMB_INT#
SMB_ADDR
2
1
RE35
PCIE_WAKE#
PCIE_WAKE#_R 2
@ RE275
BC_DAT/SMB_DATA
BC_CLK/SMB_CLK
C
RE87
1
1
PAD-OPEN1x1m
2
2
2
CE3
0.1U_0402_25V6
PROCHOT_GATE
100K_0402_5%
D
PJP14
CE2
0.1U_0402_25V6
2
CE1
10U_0603_6.3V6M
1
@ RE83
+3.3V_ALW
+3.3V_ALW_UE3
@
1
2
1
RE11
1
RE8
<30>
28
WLAN_WIGIG60GHZ_DIS#
100K_0402_5%
2
BT_RADIO_DIS#
100K_0402_5%
8
2
VCC
1
D
GPIO21/KSO01
GPIO22/KSO02
GPIO23/KSO03
GPIO24/KSO04
GPIO25/KSO05
GPIO26/KSO06
GPIO27/KSO07
GPIO30/KSO08
GPIO31/KSO09
GPIO32/KSO10
GPIO33/KSO11
GPIO34/KSO12
GPIO35/KSO13
GPIO36/KSO14
GPIO37/KSO15
GPIO00/KSO16
GPIO01/KSO17
GPIO02/KSO18
GPIO03/KSO19
GPIO04/KSO20
GPIO05/KSO21
GPIO06/KSO22
GPIO07
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
29
30
31
36
SMART_DET#
SYS_LED_MASK#
WLAN_WIGIG60GHZ_DIS#
PCIE_WAKE#_R
VGA_ID
1
0_0402_5%
2
@ RE274
PCH_PCIE_WAKE#
<36,9>
Stuff RE275 and no stuff RE274 keep E5 design
Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
PAD~D T32@
USH_PWR_STATE#
BT_RADIO_DIS#
1
0_0402_5%
<27>
BT_RADIO_DIS# <30>
WLAN_LAN_DISBL# <28>
SYS_LED_MASK# <28,39>
LED_SATA_DIAG_OUT# <39>
WIRELESS_LED# <30,39>
WLAN_WIGIG60GHZ_DIS#
<30>
C
MASK_SATA_LED#
USB_PWR_SHR_VBUS_EN
PROCHOT_GATE
MASK_SATA_LED#
BCM5882_ALERT#
USB_PWR_EN1#
USB_PWR_EN2#
TOUCH_SCREEN_PD#
<39>
USB_PWR_SHR_VBUS_EN
<31>
<27>
USB_PWR_EN1# <32>
USB_PWR_EN2# <31>
PAD~D T96 @
RESERVED
TEST_PIN
Thermal Slug(VSS)
41
ECE1099-FZG_QFN40_6X6~D
+3.3V_ALW
1
VGA_ID
100K_0402_5%
1
VGA_ID
@ 100K_0402_5%
2
RE84
2
RE85
VGA_ID0
B
Discrete
0
UMA
1
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
ECE5048
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.1
LA-A972P
Sheet
1
35
of
47
5
4
+3.3V_ALW
3
2
1
+RTC_CELL
+3.3V_ALW
2
1
2
2
CPU
DP2/DN2
DIMM
4
3
2
1
FAN1_PWM
FAN1_TACH
+5V_RUN
CONN@
DN2a/DP2a
WiGig
DP3/DN3
VGA
DP4/DN4
V.R
2
20130730 same as Goliad
@
1
1
2
2
1
C
E
2
2
B
QE3
MMBT3904WT1G_SC70-3~D
REM_DIODE1_N
THERMATRIP2#
+1.05V_RUN
1
3
1
RE70
DP2/DN2 for SODIMM on QE5, place QE5 close
to SODIMM and CE37 close to QE5
E
1
2
1
1
2
E
2
B
QE5
MMBT3904WT1G_SC70-3~D
REM_DIODE2_N
1
THSEL_STRAP
RE78
1
1
VSET_5085
2
2
B
E QE6
MMBT3904WT1G_SC70-3~D
2
2
C
1
1
2
H_THERMTRIP#
C
3
3
1
2
QE7
<12>
REM_DIODE4_P
2
1
2
MMBT3904WT1G_SC70-3~D
DP4/DN4 for Skin on QE6, place QE6 close to Vcore VR choke.
FWP#
1
BOARD_ID
2
X00
X01
X02
A00
C
2
B
DN2a/DP2a for WiGig on QE7, place QE7 close
to WiGig/WLAN and CE46 close to QE7
RE77
1.58K_0402_1%
4700p
4700p
4700p
4700p
2
2.2K_0402_5%
3
3
4
1
2
6
1
+3.3V_ALW
REM_DIODE1_P
5
B
reserve for DC fan
Place under CPU
Place CE35 close to the QE3 as possible
RUNPWROK
1
DP1/DN1
6
5
1
4
3
2
1
JFAN1
2
1
2
GND2
GND1
CE38
0.1U_0402_25V6
REV
1
1
1
1
2
2
2
8
7
6
5
ACES_50277-0040N-001
QE4
MMBT3904WT1G_SC70-3
1
2
3
4
2
RE88
<45,46,9>
2
B66
2
1
2
1
2
2
1
2
1
2
H_PROCHOT#
I_BATT <46>
I_SYS <46>
CE36
0.1U_0402_25V6
1
1
47K_0402_5%
RE69
8.2K_0402_5%
2
PCH_RSMRST#
8
7
6
5
10K_8P4R_5%
<46>
1
1
2
1
1
1
2
1
2
3
4
@ CE42
0.1U_0402_25V6
2
+3.3V_ALW
THERMATRIP3#
CHARGER_SMBDAT
CHARGER_SMBCLK
2 2200P_0402_50V7K
I_ADP
@ CE37
100P_0402_50V8J
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_PLTRST#_EC
1
100K_0402_5%
RPE6
CE24, CE26, CE27 Place near UE2
THERMATRIP2#
THERMATRIP3#
THSEL_STRAP
H_PROCHOT#
1
2
RE64
4.7K_0402_5%
@CE39
100P_0402_50V8J
240K
130K
33K
1K
CE40
@ RE82
10K_0402_5%
G1
G2
<9>
VSET_5085
@ CE46
100P_0402_50V8J
*
+3.3V_RUN
1
2
3
4
5
6
7
8
9
10
PECI_EC
2 2200P_0402_50V7K
@ CE35
100P_0402_50V8J
RE79
+3.3V_ALW
RE81
10K_0402_5%
Pin8 5075_TXD for EC Debug
pin9 5048_TXD for SBIOS
debug
CE40
4700P_0402_25V7K
11
12
1
2
3
4
5
6
7
8
9
10
CE27 1
+RTC_CELL
+1.05V_RUN
2
43_0402_5%
2 2200P_0402_50V7K
5085 Channel Location
QE2B
DMN66D0LDW-7_SOT363-6
+3.3V_ALW
RE79
130K_0402_5%
CONN@
JLPDE1
QE2A
DMN66D0LDW-7_SOT363-6
RE73
10K_0402_5%
MSCLK
MSDATA
HOST_DEBUG_TX
ACES_50521-01041-P01
2
RE62
DOCK_PWR_SW#
CE26 1
8
7
6
5
100K_0804_8P4R_5%
REM_DIODE2_P
@ RE75
100K_0402_5%
RE72
10K_0402_5%
RPE7
10K_8P4R_5%
RE71
49.9_0402_1%
A
REM_DIODE4_N
REM_DIODE4_P
1
2
3
4
BC_DAT_ECE1117
POA_WAKE#
VCI_IN2#
Close to UE2 at least 250mils
1
RE60
CE24 1
RE67
10K_0402_5%
RE68
100K_0402_5%
CE29
22P_0402_50V8J
2
RUN_ON
+3.3V_ALW
11
12
GND1
GND2
C
RPE5
+3.3V_ALW2
Thermal diode mapping
+3.3V_ALW
EMI depop location
<36,38>
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
+3.3V_ALW
2
1K_0402_5%
RE57
+3.3V_RUN
@EMC@ CE34
4.7P_0402_50V8C
MEC_XTAL2
+3.3V_ALW
1
2
3
4
5
6
7
8
9
10
+PECI_VREF
PECI_EC_R
ACAV_IN
<46>
ALWON <41>
Setting for Thermal Design
RUN_ON#
1
2
3
4
5
6
7
8
9
10
CHARGER_SMBDAT
<46>
CHARGER_SMBCLK
<46>
SIO_SLP_SUS# <9>
PBAT_PRES# <40,46>
USH_SMBDAT
<27>
USH_SMBCLK
<27>
@ CE41
0.1U_0402_25V6
2
YE1
32.768KHZ_12.5PF_Q13FC135000040
2.2K_0804_8P4R_5%
1
ACAV_IN
ALWON
POWER_SW_IN#
DOCK_PWR_SW#
VCI_IN2#
POA_WAKE#
8
7
6
5
DE1
RB751S40T1G_SOD523-2
@EMC@ RE66
10_0402_5%
1
CE28
22P_0402_50V8J
@ RE65
100_0402_1%
JTAG1 CONN@
@SHORT PADS~D
CE30
1U_0402_6.3V6K
MEC_XTAL1
+3.3V_RUN
1
2
3
4
CE32
10U_0603_6.3V6M
RE63
100K_0402_5%
32 KHz Clock
+3.3V_ALW
RPE3
A_ON <38>
SIO_EXT_WAKE# <12>
SYS_PWROK <9>
ENVDD_PCH
<10,23>
USH_SMBDAT
USH_SMBCLK
REM_DIODE1_N
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE2_P
<37,41>
CLK_PCI_MEC
Place close pin A29
JDEG1
B13
A13
B14
A14
A15
B16
A16
B17
B15
A17
A12
B34
A2
B29
A46
B61
A57
ALW_PWRGD_3V_5V
0_0402_5%
EXPRESS_SMBDATA
EXPRESS_SMBCLK
GPU_SMBDAT
GPU_SMBCLK
A59
B51
A48
2
for no-dock : B2 use Free
AC_PRESENT <9>
SIO_PWRBTN# <9>
ESR <2ohms
JTAG_RST#
1
ALW_PWRGD_3V_5V_EC
@ RE283
<30>
<9>
MEC5085-LZY_DQFN132_11X11
CE31
4.7U_0603_6.3V6K
+3.3V_ALW
CONN@
1
XTAL1
XTAL2
15mil
B
DN1_DP1A/THERM
DP1_DN1A/VREF_T
DN2_DP2A
DP2_DN2A
DN3_DP3A
DP3_DN3A
DN4_DP4A
DP4_DN4A
VIN
VSET
VCP
THERMTRIP2#
GPIO002/THERMTRIP3#
GPIO024/THSEL_STRAP
PROCHOT_IN#/PROCHOT_IO#
V_ISYS0
V_ISYS1
<36,38>
1
A61
A62
VREF_PECI
PECI_DAT
AGND
MEC_XTAL2 2
@ RE61
MEC_XTAL1
1
MEC_XTAL2_R
0_0402_5%
GPIO011/nSMI
GPIO061/LPCPD#
SER_IRQ
LRESET#
PCI_CLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
GPIO100/NEC_SCI
RUN_ON
0_0402_5%
PM_APWROK <9>
RESET_OUT# <15,9>
PCH_PCIE_WAKE#
<35,9>
GPU_SMBDAT
GPU_SMBCLK
CHARGER_SMBDAT
CHARGER_SMBCLK
B62
A64
A60
B67
A63
B63
B68
0_0402_5%
1
A6
A27
A28
B30
A29
B31
A30
B32
A31
B33
A32
A33
EXPRESS_SMBDATA
EXPRESS_SMBCLK
A_ON
2
2
SIO_EXT_SMI#
SIO_RCIN#
IRQ_SERIRQ
PCH_PLTRST#_EC
CLK_PCI_MEC
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
BGP0
VCI_OVRD_IN
VCI_OUT
VCI_IN0#
VCI_IN1#
VCI_IN2#
VCI_IN3#
AC_PRESENT
SIO_PWRBTN#
A3
B4
A4
B5
B7
A7
B48
B49
A47
B50
B52
A49
B53
A50
2
1
@ RE279
<37>
SIO_SLP_A# <9>
EC_32KHZ_MEC5085
ME_SUS_PWR_ACK
RUN_ON_EC
PM_APWROK
RESET_OUT#
PCH_PCIE_WAKE#
1
@ RE280
RUN_ON_EC
BREATH_LED# <39>
BAT1_LED# <39>
BAT2_LED# <39>
BAT1_LED#
BAT2_LED#
ALW_PWRGD_3V_5V_EC
A54
B58
SIO_SLP_S3#
1
<12> SIO_EXT_SMI#
<10,12> SIO_RCIN#
<10,12> IRQ_SERIRQ
<20,27,30,9> PCH_PLTRST#_EC
<7> CLK_PCI_MEC
<20,7> LPC_LFRAME#
<20,7> LPC_LAD0
<20,7> LPC_LAD1
<20,7> LPC_LAD2
<20,7> LPC_LAD3
<10,9> CLKRUN#
<12> SIO_EXT_SCI#
SYSPWR_PRES
PCH_RSMRST#
<6,7>
2
<9> SIO_SLP_S5#
<21> BEEP
<37> BC_CLK_ECE1117
<37> BC_DAT_ECE1117
<37> BC_INT#_ECE1117
GPIO123/BCM_A_CLK
GPIO122/BCM_A_DAT
GPIO121/BCM_A_INT#
GPIO032/BCM_E_CLK
GPIO031/GPTP-OUT2/BCM_E_DAT
GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7
GPIO047/LSBCM_D_CLK
GPIO046/LSBCM_D_DAT/GANG_STROBE
GPIO045/LSBCM_D_INT#
PCH_ALW_ON
SIO_SLP_S3#
PCH_DPWROK
MSDATA
MSCLK
PCH_RSMRST#
FWP#
1
A43
B45
A42
B20
A18
B19
A20
B21
A19
<12,28>
ME_FWP_EC <6>
RUNPWROK <9>
EN_INVPWR
<23>
SIO_SLP_S4# <9>
SIO_SLP_LAN#
<38,9>
USB_PWR_SHR_EN#
<31,35>
PCH_ALW_ON <38>
SIO_SLP_S3# <9>
PCH_DPWROK <9>
2
ACAV_IN_NB
0_0402_5%
<30,39>
1
2
2
1
2
BC_CLK_ECE1099
BC_DAT_ECE1099
BC_INT#_ECE1099
ACAV_IN_NB
SIO_SLP_S5#
BEEP
BC_CLK_ECE1117
BC_DAT_ECE1117
BC_INT#_ECE1117
LAN_WAKE#
mCARD_PCIE#_SATA_R
1
1
ACAV_IN
@ RE278
<35> BC_CLK_ECE1099
<35> BC_DAT_ECE1099
<35> BC_INT#_ECE1099
2 0_0402_5%
1
for no-dock : A43 use BC_CLK_ECE1099
for no-dock : B45 use BC_DAT_ECE1099
for no-dock : A42 use BC_INT#_ECE1099
C
<40> PS_ID
<9> SUSACK#
BIA_PWM_EC
<23>
LID_CL#
<46>
@ RE91 1
2
trace width 20 mils
trace width 20 mils
SUS_ON_EC
0_0402_5%
B57
B1
A55
A1
B28
B2
A8
B9
A9
B39
A44
AC_DIS
BOARD_ID
mCARD_PCIE#_SATA
LAN_WAKE#
HOST_DEBUG_TX
ME_FWP_EC
RUNPWROK
EN_INVPWR
3
2
@ RE281
GPIO003/I2C1A_DATA
GPIO004/I2C1A_CLK
GPIO005/I2C1B_DATA/BCM_B_DAT
GPIO006/I2C1B_CLK/BCM_B_CLK
GPIO012/I2C1H_DATA/I2C2D_DATA
GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3
GPIO130/I2C2A_DATA/BCM_C_DAT
GPIO131/I2C2A_CLK/BCM_C_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO141/I2C1F_DATA/I2C2B_DATA
GPIO142/I2C1F_CLK/I2C2B_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK
H_VSS
1
SUS_ON
SUS_ON
GPIO151/GPTP-IN4/GANG_DATA2
GPIO152/GPTP-OUT4
GPIO050/FAN_TACH1/GTACH0/GANG_START
GPIO051/FAN_TACH2/GANG _MODE
GPIO052/FAN_TACH3/GTACH1/GANG_ERROR
GPIO053/PWM0
GPIO054/PWM1/GPWM1
GPIO055/PWM2
GPIO056/PWM3/GPWM0
VSS_RO
<28,42>
100K_0804_8P4R_5%
1
10_0402_5%
CE25
0.1U_0402_25V6
BIA_PWM_EC
FAN1_PWM
B22
A21
B23
B24
A23
B25
A24
A10
B10
B8
B27
B44
B46
B26
A25
B36
B37
B38
A34
A35
A36
A40
B43
A45
B65
RE58
100K_0402_5%
FAN1_TACH
LID_CL_SIO#
SUS_ON_EC
PS_ID
VR_CAP
for no-dock : A21 use LID_CL_SIO#
B18
RUN_ON
SUS_ON
A_ON
PCH_ALW_ON
GPIO156/LED1/GANG_DATA1
GPIO157/LED0
GPIO153/LED2/GANG_DATA4
GPIO027/GPTP-OUT1
GPIO026/GPTP-IN1
GPIO001/ECSPI_CS1/32KHZ_OUT
GPIO015/GPTP-OUT7
GPIO016/GPTP-IN8
GPIO017/GPTP-OUT8
GPIO107/NRESET_OUT
GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY
GPIO145/I2C1K_DATA/JTAG_TDI
GPIO146/I2C1K_CLK/JTAG_TDO
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
JTAG_RST#
VSS_ADC
1
2
3
4
GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0
GPIO110/PS2_CLK2/GPTP-IN6
GPIO111/PS2_DAT2/GPTP-OUT6
GPIO112/PS2_CLK1A
GPIO113/PS2_DAT1A
GPIO114/PS2_CLK0A
GPIO115/PS2_DAT0A
GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5
GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6
B54
SIO_SLP_S4#
0_0402_5%
RPE10
8
7
6
5
VTR
VTR
VTR
VTR
VTR
VTR
VSS
2
A51
B55
B56
A53
B47
VTR_ADC
+VR_CAP B12
1
@ RE282
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
LCD_VCC_TEST_EN
LCD_VCC_TEST_EN
2
RE26
LID_CL_SIO#
<39,9>
C
1
RE20
H_VTR
B60
MSDATA
10K_0402_5%
2
LCD_TST
100K_0402_5%
PBAT_SMBDAT
PBAT_SMBCLK
A5
B6
A37
B40
A38
B41
A39
B42
B59
A56
SML1_SMBDATA
SML1_SMBCLK
CLK_TP_SIO
DAT_TP_SIO
LCD_TST
2
RE86
GPIO021/RC_ID1
GPIO020/RC_ID2
GPIO014/GPTP-IN7/RC_ID3
GPIO025/UART_CLK
GPIO120/UART_TX/V2P_COUT_HI1
GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1
VCC_PWRGD
GPIO060/KBRST/BCM_B_INT#
GPIO101/ECGP_SCLK
GPIO103/ECGP_MISO
GPIO105/ECGP_MOSI
GPIO102/BCM_C_INT#
GPIO104/SLP_S0#
GPIO106
GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP
GPIO117/MSCLK/V2P_COUT_HI
GPIO127/A20M
nFWP
B11
B3
A11
A26
B35
A41
A52
<40> PBAT_SMBDAT
<40> PBAT_SMBCLK
1
VBAT
C1
1
2
1
2
1
1
1
1
1
2
2
2
2
1
2
2
1
2
for no-dock : A38 use LCD_TST
for no-dock : B41 use Free
for no-dock : A39 use SLP_ME_CSW_DEV#
<23>
for no-dock : B42 use Free
POWER_SW#_MB
CE8
0.047U_0402_16V4Z
A58
SML1_SMBDATA
SML1_SMBCLK
<37> CLK_TP_SIO
<37> DAT_TP_SIO
<23> LCD_TST
CE12
1U_0402_6.3V6K
A22
<7>
<7>
10K_0402_5%
D
CE19
0.1U_0402_25V6
RE56
2
UE2
B64
2
PAD-OPEN1x1m
CE23
0.1U_0402_25V6
2
RE55
2
@ PJP15
1
EN_INVPWR
100K_0402_5%
RESET_OUT#
10K_0402_5%
CE18
0.1U_0402_25V6
1
FAN1_PWM
10K_0402_5%
FAN1_TACH
10K_0402_5%
CE22
0.1U_0402_25V6
2
CE17
0.1U_0402_25V6
2
1
1
+3.3V_ALW_UE2
@CE16
0.1U_0402_25V6
2
1
RE51
CE21
10U_0603_6.3V6M
1
+3.3V_ALW
@ CE10
1
2
1U_0402_6.3V6K
1
RE33
POWER_SW_IN#
CE15
1U_0402_6.3V6K
+3.3V_RUN
2
CE20
0.1U_0402_25V6
D
1
CE14
1U_0402_6.3V6K
CE13
0.1U_0402_25V6
+3.3V_ALW_UE2
RE48
1
1
2
+3.3V_ALW_UE2
E
BC_DAT_ECE1099
100K_0402_5%
PBAT_SMBDAT
2.2K_0402_5%
PBAT_SMBCLK
2.2K_0402_5%
B
2
RE25
100K_0402_5%
2
1
RE43
+RTC_CELL
RE31
100K_0402_5%
2
1
RE37
+RTC_CELL_VBAT
CE11
0.1U_0402_25V6
1
RE36
0_0402_5%
EP
1
@ RE32
2
1K_0402_5%
A
Channel 1
Thermal Monitoring Interface Strap Option
HIGH
Thermistor Readings
LOW
Diode Readings
REM_DIODE4_N
Rest=1.58K , Tp=96 degree
BOARD_ID rise time is measured from 5%~68%.
CLK_PCI_LPDEBUG
DELL CONFIDENTIAL/PROPRIETARY
<20,7>
HB_A531015-SCHR21
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
MEC5085
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.1
LA-A972P
1
Sheet
36
of
48
5
4
3
2
1
D
D
Touch Pad
+3.3V_RUN
Keyboard
+3.3V_TP
+3.3V_TP
@ PJP16
2
CONCR_205160FW010
2
2
DAT_TP_SIO
CLK_TP_SIO
17
18
C
GND1
GND2
JKBTP1
1
1
2
+3.3V_TP
2
BC_CLK_ECE1117
+3.3V_TP +3.3V_ALW +5V_RUN
1
<36>
@EMC@ CZ31
10P_0402_50V8J
@EMC@ CZ30
10P_0402_50V8J
1
CLK_TP_SIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
1
2
2
DAT_TP_SIO
1
CLK_TP_SIO
+5V_RUN
+3.3V_ALW
<36> BC_INT#_ECE1117
<36> BC_DAT_ECE1117
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
@ CZ29
0.1U_0402_25V6
<36>
KB_DET#
@ CZ28
0.1U_0402_25V6
DAT_TP_SIO
<11,12>
@ CZ27
0.1U_0402_25V6
<36>
RZ19
4.7K_0402_5%
PAD-OPEN1x1m
RZ18
4.7K_0402_5%
1
1
Place close to JKBTP1
C
CONN@
20130730 same as Goliad
EMI depop location
RSMRST circuit
@eDP Cable
Part Number
2
VCC
RESET#
3
@eDP TS Cable
Part Number
0.1U_0402_25V6
Part Number
Description
NBX0001KE00
FFC 26P G P0.5 PAD=0.3 47MM MB-USH
DC02C007Q00
@KBTP FFC
Description
H-CONN SET 14A MB-EDP-LED-CAMERA-TS
Part Number
Description
NBX0001KD00
FFC 16P G P0.5 PAD=0.3 82MM MB-KBTP
5
<36>
1
PCH_RSMRST#
2
RSMRST#
B
A
@NFC Board FFC
O
GND
3
2
@ CZ34
1
2
P
1
@USH Board FFC
Description
H-CONN SET 14A MB-EDP-LED-CAMERA
+3.3V_ALW
G
1
@ CZ35
0.01U_0402_16V7K
1
+5V_ALW_U41
2
2
@ UZ5
@ RZ22
10K_0402_5%
B
DC02C007P00
+3.3V_ALW
@ RZ21
33_0402_5%
1
+5V_ALW
4
PCH_RSMRST#_Q
B
<9>
Part Number
Description
NBX0001KC00
UZ6
TC7SH08FU_SSOP5~D
RT9818A-44GU3_SC70-3
FFC 15P F P0.5 PAD=0.3 40.5MM MB-NFC
@FP FFC
Part Number
<36,41>
ALW_PWRGD_3V_5V
1
@ RZ51
Description
NBX0001KB00
2
0_0402_5%
@DC-IN Cable
Part Number
DC30100MF00
@SIM+Hall/B FFC
Description
CONN SET 0VN DCJACK-MB 2DW1003-038110F
@RTC BATT
Part Number
DC30100MF00
FFC 8P F P0.5 PAD=0.3 22.5MM MB-FP
Part Number
NBX0001CR00
Description
FFC 12P G P0.5 PAD=0.3 73.3MM MB-SIM+HALL/B
@ Speak
Description
CONN SET 0VN DCJACK-MB 2DW1003-038110F
Part Number
Description
PK230003Q0L SPK PACK ZJX 2.0W 4 OHM FG
@ FAN
Part Number
Description
DC28A000800 FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Keyboard
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
37
of
48
4
2
2
<36>
3
4
+5V_ALW
5
A_ON
6
7
2
VIN1
VIN1
VOUT1
VOUT1
ON1
CT1
VBIAS
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
GPAD
+1.05V_MODPHY
14
13
12
11
10
+1.05V_RUN_UZ7
0.01_1206_1%
D
1
2
VPRO@ CZ23
470P_0402_50V7K @ PJP13
1
+3.3V_M_UZ2
15
NVPRO@
1
RZ41
2
RUN_ON
2
0.1U_0402_10V7K
9
8
TPS22966DPUR_SON14_2X3
2
1
@ CZ24
1
2
VPRO@ CZ49
470P_0402_50V7K
@ PJP36
2
0_0402_5%
2
+3.3V_M
PAD-OPEN1x2m
@CZ50
0.1U_0402_10V7K
For No-Vpro HW configs
+3.3V_RUN
+3.3V_M
1
1
A_ON
PAD-OPEN1x1m
2
VPRO@ RZ42
if support MODPHY off keep DSC solution
MODPHY timing spec 0.7V/us and <65us
EN_+V1.05SP
NVPRO@
<43>
2
RZ54
0_0603_5%
0_0402_5%
+3.3V_ALW_PCH/+3.3V_LAN source
C
+3.3V_ALW_PCH
1
C
RUN_ON
RUN_ON
+3.3V_ALW
1
+1.05V_RUN
2
UZ2 VPRO@
1
2
+1.05V_M
<36>
+1.05V_RUN
1
RZ52
1
1
G
3
1
2
3
4
1
2
6
1
1
+1.05V_M
PJP18 @
NVPRO@
PAD-OPEN1x3m
CZ25
220P_0402_50V7K
MPHYP_PWR_EN
QZ10A
DMN66D0LDW-7_SOT363-6
<12>
2
1.05V_MODPHY_EN
5
For No-Vpro HW configs
4
QZ10B
DMN66D0LDW-7_SOT363-6
MPHYP_PWR_EN#
+1.05V_M
Max Rating: 2495 mA
+1.05V_RUN
+1.05V_RUN/+3.3V_M source
CZ38
10U_0603_6.3V6M
RZ16
100K_0402_5%
D
RZ5
100K_0402_5%
+3.3V_ALW2
1
+1.05V_MODPHY
QZ6
SI3456DDV-T1-GE3_TSOP6
6
5
2
1
2
1
+1.05V_M
+5V_ALW
D
+1.05V_MODPHY
3
S
5
PJP19
PAD-OPEN1x1m
@
UZ3
1
2
<36>
3
PCH_ALW_ON
4
+5V_ALW
<36,9>
5
SIO_SLP_LAN#
6
7
VIN1
VIN1
VOUT1
VOUT1
ON1
CT1
VBIAS
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
GPAD
2
+3.3V_ALW
14
13
+3.3V_ALW_PCH_UZ3 1
@CZ36
@
CZ36
2
0.1U_0402_10V7K
12
1
CZ37
2
470P_0402_50V7K
11
10
9
8
1
CZ62
1
+3.3V_LAN_UZ3
@CZ63
@
CZ63
2
470P_0402_50V7K
2
0.1U_0402_10V7K
15
PJP20
2
TPS22966DPUR_SON14_2X3
1
+3.3V_LAN
PAD-OPEN1x1m
@
+5V_RUN
+3.3V_RUN/+5V_RUN source
B
1
B
PJP21
PAD-OPEN1x3m
@
UZ9
3
4
5
RUN_ON
+3.3V_ALW
6
7
VIN1
VIN1
VOUT1
VOUT1
ON1
CT1
VBIAS
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
1
+5V_RUN_UZ9
@ CZ44
12
1
CZ45
2
2
470P_0402_50V7K
1
CZ46
2
1000P_0402_50V7K
@ PJP22
1
2
+3.3V_RUN
0.1U_0402_10V7K
11
10
9
8
+3.3V_RUN_UZ9
15
TPS22966DPUR_SON14_2X3
CZ47
0.1U_0402_10V7K
GPAD
14
13
1
1
2
2
+5V_ALW
PAD-OPEN1x3m
2
@
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Power control
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
38
of
48
5
4
3
HDD LED solution for White LED
2
1
Battery LED
2
QZ3B
DMN66D0LDW-7_SOT363-6
<6>
4
SATA_ACT#
PANEL_HDD_LED#
1
+5V_ALW
<23>
QZ5B
DMN66D0LDW-7_SOT363-6
QZ3A
DMN66D0LDW-7_SOT363-6
DZ3
3
PANEL_HDD_LED#
3
RZ24
10K_0402_5%
1
+3.3V_ALW
2
1
6
<36>
2
4
BAT2_LED#
5
2
5
QZ4
MASK_SATA_LED#
1
<35>
DZ4
<35>
1
LED_SATA_DIAG_OUT#
3
1
BAT2_LED#_Q
RZ25
RB751S40T1G_SOD523-2
D
+5V_ALW
LED7
2
BATT_WHITE#
1
BATT_YELLOW#
3
390_0402_5%
2
W
MASK_BASE_LEDS#
4
D
Y
DDTA114EUA-7-F_SOT323-3
LTW-295DSKS-5A_YEL-WHITE
2
1
RZ27
SYS_LED_MASK#
RB751S40T1G_SOD523-2
2
680_0402_5%
1
RZ43
+5V_ALW
2
1K_0402_5%
BATT_WHITE_LED#
<23>
QZ5A
DMN66D0LDW-7_SOT363-6
BAT1_LED#
1
6
BAT1_LED#_Q 1
RZ28
2
330_0402_5%
BATT_YELLOW_LED#
<23>
QZ14A
DMN66D0LDW-7_SOT363-6
1
6 SATA_LED# 2
QZ14B
DMN66D0LDW-7_SOT363-6
4
2
3
<36>
MASK_BASE_LEDS#
3
2
1
RZ44
1
5
QZ12
LED6
1
RZ36
MASK_BASE_LEDS#
2
390_0402_5%
DDTA114EUA-7-F_SOT323-3
2
SATA_LED 2
270_0402_5%
1
LTW-193ZDS5_WHITE
WLAN LED solution for White LED
Breath LED
+5V_ALW
3
+5V_ALW
<36>
QZ7A
DMN66D0LDW-7_SOT363-6
1
6
QZ7B
DMN66D0LDW-7_SOT363-6
4
3 BREATH_LED#_Q
LED3
LTW-193ZDS5_WHITE
1
2BREATH_WHITE_LED
BREATH_WHITE_LED_SNIFF
1
RZ32
C
2
270_0402_5%
Place LED3 close to SW3
2
2
WIRELESS_LED#
BREATH_LED#
5
2
<30,35>
RZ31
100K_0402_5%
1
+3.3V_ALW
C
1
QZ9
MASK_BASE_LEDS#
MASK_BASE_LEDS#
DDTA114EUA-7-F_SOT323-3
1
LED5
1
RZ33
2 WLAN_LED
390_0402_5%
2
RZ34
2
BREATH_WHITE_LED#
680_0402_5%
BREATH_WHITE_LED#
<23>
1
LTW-193ZDS5_WHITE
+3.3V_ALW
2
LID_CL#
A
0.1U_0402_25V6
O
3
<30,36>
B
P
1
SYS_LED_MASK#
G
5
@ CZ48
1
2
<28,35>
4MASK_BASE_LEDS#
UZ10
TC7SH08FU_SSOP5~D
B
B
POWER & INSTANT ON SWITCH
<36,9>
2
POWER_SW#_MB
SW2
1
4
3
SKRBAAE010_4P
LED Circuit Control Table
SYS_LED_MASK#
Fiducial Mark
@ FD1
1
FIDUCIAL MARK~D
@ FD2
1
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened)
@ H1 @ H2 @ H3 @ H4 @ H5 @ H6
H_2P3 H_2P5 H_2P5 H_2P8 H_2P8 H_2P8
LID_CL#
0
1
1
X
0
1
@ H13 @ H14 @ H15 @ H16
H_3P4 H_3P4 H_3P4 H_3P4
@ H19
H_2P1
@ H20
@ H21
H_3P0N H_3P0N
A
A
@ H17
H_2P8
@ ST1
CLIP_C5P1
1
1
1
1
1
1
1
@ H18
H_2P8
1
1
1
1
@ H7 @ H8 @ H9 @ H10 @ H11 @ H12
H_2P5 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8
1
FIDUCIAL MARK~D
1
@ FD3
1
1
1
FIDUCIAL MARK~D
@ ST2 @ ST3
H_3P3 H_3P3
@ FD4
1
1
1
1
1
1
1
1
1
1
DELL CONFIDENTIAL/PROPRIETARY
FIDUCIAL MARK~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
PAD, LED
Size
Document Number
Date:
Monday, March 17, 2014
LA-A972P
Sheet
1
Rev
0.1
39
of
48
5
4
3
2
1
+COINCELL
1
COIN RTC Battery
PR1
1K_0402_5%
+Z4012 2
+3.3V_RTC_LDO
2
3
3
4
D
TYCO_2-1775293-2~D
+RTC_CELL
1
PD3
@ JRTC1
1
2 1 G
2 G
+COINCELL
D
BAS40CW_SOT323-3
1
PC1
1U_0603_10V4Z
1
PD2 EMC@
TVNST52302AB0_SOT523-3
EMC@PL1
PC3
2200P_0402_50V7K~D
2
1
PBATT+_C
C
+3.3V_ALW
FBMJ4516HS720NT_2P~D
1
2
3
2
3
2
PD1 EMC@
TVNST52302AB0_SOT523-3
Primary Battery Connector
EMC@PL2
FBMJ4516HS720NT_2P~D
1
2
1
1
2
+PBATT
2
PR2
LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2
1
1 2
2 3
PBAT_SMBCLK_C
3 4
PBAT_SMBDAT_C
4 5
PBAT_PRES#_C
5 6
6 7
7 8
8 9
9 10
GND 11
GND
PRP2
8
7
6
5
1
2
3
4
PBAT_SMBCLK
PBAT_SMBDAT
100K_0402_5%
<37>
<37>
PBAT_PRES#
<36,48>
100_0804_8P4R_5%
C
@ PBATT1
GND
PR7
1
0_0402_5%
S
1
2.2K_0402_5%
1
PS_ID
<36>
+5V_ALW
C
PQ3
MMST3904-7-F_SOT323-3
B
PR11
10K_0402_1%
E
3
2
1
2
B
PQ2
FDV301N-G_SOT23-3
1
2
G
2
100K_0402_1%
PD5
AZC199-02SPR7G_SOT23-3
EMC@
B
1
2
3
PR10
PR8
PR9
33_0402_5%
1
2
3
D
1
2
2
PL3 EMC@
BLM15AG102SN1D_2P
2
1
NB_PSID
2
+3.3V_ALW
@
PR12
1
15K_0402_1%
DC_IN+ Source
+DC_IN
+DCIN_JACK
1
PR16
-DCIN_JACK
2
5
4
3
2
1
4.7K_0805_5%
5
4
3
2
1
A
@
A
PC22 EMC@
10U_0805_25V6K
2
1
ACES_50299-0050N-001
7
GND 6
GND
PC9 EMC@
1000P_0603_50V7K
2
1
EMC@ PL4
FBMJ4516HS720NT_2P
1
2
PJP1
@ PJPDC1
1
2
DELL CONFIDENTIAL/PROPRIETARY
PAD-OPEN 1x3m
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+DCIN
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.1
LA-A902P
Sheet
1
40
of
47
A
B
C
D
E
PC105
2200P_0402_50V7K
+3.3V_RTC_LDO
EMC12UnonD@
+3.3V_ALW2
1
1
PR100
6.49K_0402_1%
1
2
PR101
15K_0402_1%
1
2
1
2
2
10
UG_3V
PC109
PR110
0.1U_0603_25V7K
2.2_0603_5%
1
2 BST_3V_C
1
2
2
3
1
CS1
VFB1
19
PR114
200_0402_1%
1
2
BST_3V
9
16
UG_5V
SW2
8
VBST2
17
BST_5V
18
SW1
1
2
3
PQ100
SIS412DN-T1-GE3_POWERPAK8-5
2
4
PR109
PC110
2.2_0603_5%
0.1U_0603_25V7K
1
2 BST_5V_C
1
2
PQ101
DRVL1
SIS412DN-T1-GE3_POWERPAK8-5
PL102
3.3UH +-20% 6.3A 7X7X3 MOLDING
1
2
+5V_ALWP
1SNUB_3V
2
4
+3V5V_PWR_SRC
PQ103
4.7_1206_5%
3
2
1
1
SI7716ADN-T1-GE3_POWERPAK8-5
2
SI7716ADN-T1-GE3_POWERPAK8-5
PC118
4.7U_0603_10V6K
2
1
PC117
0.1U_0603_25V7K
2
1
PQ102
1
2
3
@EMC@ PC111
680P_0603_50V7K
PR112 @EMC@
LG_5V
4
PC115
150U_D_6.3VM_R15M
LG_3V
@EMC@ PR111
4.7_1206_5%
+
2
2
SNUB_5V
1
EN
1
5
15
VIN
EN1
20
13
11
SW1
5
12
DRVL2
SW2
VREG5
3
2
1
VBST1
2
PC113
150U_D_6.3VM_R15M
14
1
4
21
TPS51285BRUKR_QFN20_3X3
DRVH2
DRVH1
PGOOD
VCLK
PL101
2.2UH +-20% 7.8A 7X7X3 MOLDING
1
2
+3.3V_ALWP
PAD
VO1
7
PGOOD_3V_5V
PC102
10U_0805_25V6K
2
1
EN2
VREG3
4
5
CS2
VFB2
6
EN
2
100K_0402_1%
PR107
PR108
0_0402_5%
1
2
5
PC101
10U_0805_25V6K
2
1
2
@EMC@ PC105
2200P_0402_50V7K
2
1
+PWR_SRC
PU100
1
2
+3V5V_PWR_SRC
2
PR105
PAD-OPEN 1x3m
16.9K_0402_1%
PR106
+3.3V_ALW 20K_0402_1%
5
+3V5V_PWR_SRC
PR104
10K_0402_1%
1
2
PC100
4.7U_0603_10V6K
2
1
ALW_PWRGD_3V_5V
PJP100
1
PR103
0_0402_5%
1
<36>
@EMC@PL100
1UH +-20% 6.6A 5X5X3 MOLDING
1
2
1
PR102
10K_0402_1%
1
2
1
+
2
PC114 @EMC@
680P_0603_50V7K
+5V_ALW2
3
3
EN
3.3 VALWP
TDC: 4.5 A
Peak Current: 6.4 A
OCP Current: 7.68 A
Cap ESR(@20 ): 18 mohm
Choke DCR(@20 ): 15.5 mohm
<36>
ALWON
PR113
0_0402_5%
1
2
5 VALWP
TDC: 3.5 A
Peak Current: 5.0 A
OCP Current: 6.0 A
Cap ESR(@20 ): 18 mohm
Choke DCR(@20 ): 25 mohm
PJP101
+5V_ALWP
℃℃
1
2
+5V_ALW
PAD-OPEN 1x3m
℃℃
PJP102
+3.3V_ALWP
2
+3.3V_ALW
PAD-OPEN 1x3m
PC119
1U_0603_10V6K
2
1
TYP
MAX
H/S Rds(on) :24.0 mohm , 30.0 mohm
L/S Rds(on) :13.5 mohm , 16.5 mohm
1
TYP
MAX
H/S Rds(on) :24.0 mohm , 30.0 mohm
L/S Rds(on) :13.5 mohm , 16.5 mohm
4
4
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
+5V_ALW/3.3V_ALW
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.1
LA-A902P
Sheet
41
of
47
E
DELL CONFIDE
5
4
3
2
1
PC203
0.675 Volt
TDC 0.7 A
Peak Current 1.0 A
OCP Current 2.6 A
2200P_0402_50V7K
EMC12UnonD@
PJP200
D
PAD-OPEN1x1m
+0.675V_P
14
1
19
18
20
VTT
2
+V_DDR_REF
PR204
0_0603_5%
4
VTTREF
+V_DDR_REF
C
+1.35V_MEN_P
5
VDDQ
PC212
0.033U_0402_16V7K
FB sense trace
when FB pull down to GND
FB
VDD
3
2
6
PC211
1U_0603_10V6K
1
2
3
VLDOIN
VDDP
S3
5.1_0603_5%
SI7716ADN-T1-GE3_POWERPAK8-5
2
GND
RT8207MZQW_WQFN20_3X3
7
11
VDD_1.35V
@EMC@
PC208
1
VTTSNS
S5
2
CS
1
+5V_ALW
PQ201
PR202
21
PAD
VTTGND
PGND
TON
5
1
12
1
PU200
CS_1.35V
PC209
1U_0603_10V6K
4
LGATE
8
1
2
3
PR201
19.6K_0402_1%
1
2
UGATE
15
BOOT
16
DL_1.35V
17
SW_1.35V
PC205
22U_0805_6.3V6M
DH_1.35V
13
PR203 @EMC@
4.7_1206_5%
1
2
2
SNUB_1.35V
+
PC207
220U_D2_2VY_R17M
1
+1.35V_MEN_P
2
2.2_0603_5%
SIS412DN-T1-GE3_POWERPAK8-5
C
1
+VLDOIN_1.35V
4
PQ200
PL200
1UH +-20% 11A 7X7X3 MOLDING
1
2
BOOT_1.35V
PHASE
+1.35V_MEN_P
PR200 2
PGOOD
1
2
5
1
2
@EMC@ PC203
2200P_0402_50V7K
PC201
10U_0805_25V6K
2
1
PC200
10U_0805_25V6K
2
1
@
PJP201
1
9
1.35V_B+
10
2
PAD-OPEN 1x2m~D
0.22U_0603_16V7K
1
BOOT_1.35V_C
+PWR_SRC
PC204
D
PR205
8.06K_0402_1%
1
2
2
680P_0603_50V7K
1.35V_FB
+5V_ALW
PC213
100P_0402_50V8J
1
2
1.35V_B+
PR206
2
S5_1.35V
1
SUS_ON
1
768K_0402_1%
1
<36,38>
PR207
0_0402_5%
1
2
1.35 _MEN
TDC: 6.6 A
Peak Current: 9.5 A
OCP Current: 11.4 A
Cap ESR(@20 ): 17 mohm
Choke DCR(@20 ): 7.4 mohm
2
2
@ PC215
.1U_0402_16V7K
℃℃
TYP
H/S Rds(on) : 24.0 mohm ,
L/S Rds(on) : 13.5 mohm ,
B
1
0.675V_DDR_VTT_ON
@ PC214
.1U_0402_16V7K
2
<18>
B
10K_0402_1%
PR209
PR210
0_0402_5%
1
2
+1.35V_MEN_P
FB sense trace
MAX
30.0 mohm
16.5 mohm
PJP203
1
1
2
2
JUMP_1x3m
+1.35V_MEN_P
PJP204
1
1
2
2
+1.35V_MEM
JUMP_1x3m
PJP202
1
+0.675V_P
+0.675V_DDR_VTT
2
PAD-OPEN1x1m
Mode
S5
S3
S0
A
S3
L
L
H
S5
L
H
H
+1.35V_MEN
off
on
on
+V_DDR_REF
off
on
on
+0.675V_P
off
off(Hi-Z)
on
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+1.35V_MEN/+0.675V_DDR_VTT
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.1
LA-A902P
Sheet
1
42
of
47
5
4
3
2
1
PC300
+1.05V_MEN
TDC: 5.7 A
Peak Current: 8.1 A
OCP Current: 9.7 A fix by IC
Choke DCR(@20 ): 14.0 mohm
2200P_0402_50V7K
EMC12UnonD@
℃
D
D
1
EN_+V1.05SP <9,36>
1M_0402_1%
PR303
2
PJP300
+1.05V_MP
1
+1.05V_M
2
PAD-OPEN 1x2m~D
PJP302
PU300
1
2
100K_0402_1%
2
1
@ PC308
22U_0805_6.3VAM
1
2
PC307
22U_0805_6.3VAM
1
PR310
10K_0402_1%
B
2
2
@
PR308
0_0402_5%
B
2
1
ILMT_1.05V
PC306
47U_0805_6.3V6M
5
SY8208DQNC_QFN10_3X3
+3.3V_ALW
2
FB_+V1.05SP
7
1
LDO
4
2
PG
FB
PC305
47U_0805_6.3V6M
BYP
+1.05V_MP
PC304
330P_0402_50V7K
ILMT
C
PL301
0.68UH +-20% 7.9A 5X5X3 MOLDING
1
2
SW_+V1.05SP
10
1
LX
PC302
PR312
0.1U_0603_25V7K
0_0603_5%
6BST_+V1.05SP
1
2
1
2
BST_+V1.05SP_C
PR307
PR309
7.5K_0402_1%
1K_0402_5%
2
1
2
1
10U_0805_25V6K
PC303
2
1
GND
1
1
2
9
3
ILMT_1.05V
PR313
0_0402_5%
1
21.05V_MP_PWROK 2
1
+3.3V_ALW
EN
BS
PR315
@ PR306
0_0402_5%
IN
1
1.05V_M_PWRGD
<15>
8
2
+3.3V_ALW
+V1.05SP_B+
PC310
4.7U_0603_6.3V6K
2
PAD-OPEN 1x2m~D
2200P_0402_50V7K
@EMC@ PC300
2
1
1
C
PC309
4.7U_0603_6.3V6K
2
1
+PWR_SRC
@EMC@ PR305
@EMC@ PC301
4.7_1206_5%
680P_0603_50V7K
1
2SNB_1.05V1
2
DELL CONFIDENTIAL/PROPRIETARY
A
A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+1.05V_M
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.1
LA-A902P
Sheet
1
43
of
47
5
4
3
2
1
+1.5V_RUN
TDC: 0.47 A
Peak Current: 0.67 A
D
D
+3.3V_RUN
1
+5V_ALW
PJP400
2
PC400
1U_0402_6.3V6K
2
1
PAD-OPEN1x1m
+1.5V_VIN
2
PU400
1
+1.5V_RUN
PAD-OPEN1x1m
1
PR402
8.66K_0402_1%
2
PC403
0.01U_0402_25V7K
1
9
PC404
22U_0805_6.3V6M
APL5930KAI-TRG_SO8
2
1
.1U_0402_16V7K
2
PJP401
1
1.5VSP
2
PC402 @EMC@
@ PR401
47K_0402_5%
FB
VIN
C
PC401
4.7U_0805_6.3V6K
3
2
1
1
EN
GND
8
1
2
100K_0402_5%
4
2
VOUT
PR400
1
VOUT
5
2
POK
VIN
1
6
7
+3.3V_RUN
VCNTL
C
2
PR403
10K_0402_1%
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+1.5VSP
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.1
LA-A902P
Sheet
1
44
of
47
5
4
3
2
1
2 PR504 1
36.5K_0402_1%
1
PR503
2
681K_0402_1%
1
PR502
75_0402_1%
2
VBAT
SLEWA
THERM
IMON
OCP-I
B-RAMP
F-IMAX
O-USR
8
7
6
5
4
3
2
1
@ PR513
1
2
75_0402_1%
1
1_0603_5%
PWM1
PC503
1000P_0402_50V7K
1
2
2
1
PC520 @EMC@
2200P_0402_50V7K
PC519
100U_D_20VM_R55M
9
PC504
8 PGND2
2
7 PWM
CORE_BOOT_C 1
CORE_BOOT
BOOT
VSW
0.1U_0402_25V6
PGND1
1
2 CORE_BOOT_R
6
5 BOOT_R VDD
PR517
VIN
SKIP#
2.2_0603_5%
TI recommend 1nF
C
+VCC_CORE
4
3
2
1SKIP#1
1
CSD97374CQ4M_SON8_3P5X4P5
2SKIP#
PR520
0_0402_5%
1
2
1U_0603_10V7K
PC509
+5V_RUN
3
2
PR512
2.15K_0402_1%
1
2
VIDSCLK
<15>
VIDALERT_N
VCCSENSE
from processor
VIDSOUT
VSSSENSE
2
VFB
PR532
0_0402_5%
1
2
GFB
CPU 15W
TDC 10 A
Peak Current 32 A
OCP Current 38.4 A
DC Load line -2.0 mV/A
Choke DCR: 0.66m +-7% ohm
Icc_Dyn_VID1 27 A
PH500 B value: 4250k 1%
PH501 B value: 3370k 1%
1
B
CSN1
1
+VCC_PWR_SRC
<17>
PR531
0_0402_5%
1
2
2
PC511
0.1U_0402_25V6
PR515
3.01K_0402_1%
2
1
PR514
20K_0402_1%
2
1
1
2
1
PR529
110_0402_1%
2
1
2
PR528
75_0402_1%
1
<15>
PR527
54.9_0402_1%
2
<15>
<15>
@
PC513
0.068U_0402_16V7K
+1.05V_VCCST
B
2
1
PC502
0.068U_0402_16V7K
H_PROCHOT#
1
<9,36,46>
PH501
10K +-1% 0402 B25/50 3370K
CSP1
2
2
PL500
0.15UH_ETQP4LR15AFM_29A_20%
4
1
CORE_SW
4.7_1206_5%
+3.3V_RUN
CORE_SW_CSP
2
@EMC@ PC508 @EMC@ PR522
2
1 CORE_SNUB
2
1
PR519
VIDALERT_N
2
PR526
10_0603_1%
1
1
2
PC512
1500P_0402_50V7K
+5V_ALW
PC514
1
PR534
0_0402_5%
47P_0402_50V8J
VIDSCLK
1
0.33U_0603_10V7K
PC507
1
VREF
2
@ PC518
10U_0805_25V6K
2
1
+3.3V_RUN
2
2
PC510
1U_0603_10V7K
PR535
4.75K_0402_1%
<15>
VR_HOT#
2
1
H_VR_READY
PU501
1
TPS51624RSM QFN 32P VCORE IC
2
2
2
2
4.22K_0402_1%
10K_0402_5%
1
@ PR516
1.91K_0402_1%
1
PR521
1
<15>
PR539
0_0402_5%
1
PWM1
DROP
COMP
VREF
V5A
GND
VR_HOT#
VCLK
ALERT#
GND
25
26
27
28
29
30
31
32
33
@ PC506
1
2
100P_0402_50V8J
+
2
680P_0603_50V7K
VR_ON
SKIP#
PWM1
PWM2
N/C
PGOOD
VDD
VDIO
C
EMC12UnonD@
SKIP#
VIDSOUT
CSP1
CSN1
CSN2
CSP2
PU3
N/C
GFB
VFB
VFB
GFB
17
18
19
20
21
22
23
24
1
16
15
14
13
12
11
10
9
PU500
CSN1
+3.3V_RUN
+3.3V_RUN
H_VR_EN
@ PC517
10U_0805_25V6K
2
1
PR536
1
2
0_0402_5%
10K_0402_5%
1 PR523
@EMC@ PL501
1
2
FBMA-L11-453215800LMA90T_2P
2
CSP1
EMC12UnonD@
+VCC_PWR_SRC
PC516
10U_0805_25V6K
2
1
PR511
2
PAD-OPEN 4x4m
PC505
1U_0603_10V6K
1
680P_0603_50V7K 2200P_0402_50V7K
PJP500
1
PC515
10U_0805_25V6K
2
1
1
PR509
20K_0402_1%
2
1
PR508
+PWR_SRC
2
+VCC_PWR_SRC
PC520
O-USR
2
2
PR507
1
F-IMAX
100K_0402_1%
B-RAMP
150K_0402_1%
39K_0402_5%~N
PR510
EMC12UnonD@
PC508
D
OCP-I
2 PR506 1
1
SLEWA
4.7_1206_5%
@
39K_0402_1%
D
PC501
.1U_0402_16V7K
2
1
PR505
10K_0402_5%
2
1
2
PR501
1
PC500
1
IMON
2
2
75_0402_1%
@ PR500
2
1
PH500
1
100K 1% 0402 B25/50 4250K
316K_0402_1%
VREF
4700P_0603_50V7K
PR522
2
@ PR518
2M_0402_1%
1
1
A
2 OCP-I
@ PR524
2M_0402_1%
A
2
@ PR525
27K_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+VCC_CORE
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.1
LA-A902P
Sheet
1
45
of
47
A
B
C
1
PC713
PR726
EMC12UnonD@
EMC12UnonD@
2
1
IDCHG
LODRV
GND
BAT
2
GNDA_CHG
PJP701
1
1
17
1
D1
G1
2
PR723
10_0603_1%
S2
3
S2
PC721 @EMC@
1000P_0603_50V7K
+PBATT
+VCHGR
PR721
0.01_1206_1%
1
4
1
3
2
PR726
4.7_1206_5%
@EMC@
GNDA_CHG
PC726
0.1U_0402_25V6
1
2
PC727
0.1U_0402_25V6
1
2
PC728
0.1U_0402_25V6
1
2
GNDA_CHG
GNDA_CHG
Maximum charging current is 7.2A
PAD-OPEN1x1m
GNDA_CHG
2
@ PR729
154K_0402_1%
2
PR722
4.02K_0402_1%
1
2
18
2
1
2
CHG_SNUB
PWPD
19
S2
SRN
/BATDRV
D2/S1
G2
/BATPRES
BQ24777RUYR WQFN 28P CHARGER
PBAT_PRES#
7
20
2.2UH +-20% 12A 10X10X4 MOLDING
1
29
0_0402_5%
2
BQ24770_REGN
2
H_PROCHOT#
PR725
1K_0402_1%
<36,40>
PL701
2
10K_0402_1%
CMPOUT
CELL
1
PQ704
AON6970_DFN5X6D-8-7
16
PR728
1
+PWR_SRC
+PWR_SRC
21
4
NC
5
CMPIN
PC724
10U_0805_25V6K
2
1
/PROCHOT
SRP
15
2
22
6
14
@
PMON
PR799
13
@
PC708
22U_0805_25V6M
2
1
CHG_LGATE
@ PC707
22U_0805_25V6M
2
1
CHG_SW
23
PC705
10U_0805_25V6K
2
1
CHG_UGATE
27
PC704
10U_0805_25V6K
2
1
26
PC717
22U_0805_25V6M
2
1
PHASE
IADP
PC716
22U_0805_25V6M
2
1
HIDRV
ACOK
PC715
22U_0805_25V6M
2
1
SCL
PC706
22U_0805_25V6M
2
1
1
ACN
2
4
SDA
Near PL701
@ PC725
10U_0805_25V6K
2
1
10
BTST
PR712
2.2_0603_5%
25
1
2 CHG_BTS_C
CHG_BTS
PC723
10U_0805_25V6K
2
1
0_0402_5%
2
ACDET
24
1
PR717
1
1U_0603_10V6K
REGN
PC722 @EMC@
0.1U_0603_25V7K
2
1
9
CMSRC
@
8
PC710
1
2
PC714
22U_0805_25V6M
2
1
7
GNDA_CHG
BQ24770_REGN
@EMC@ PC713
2200P_0402_50V7K
2
1
5
VCC
ACP
2
2
PR710
294K_0402_1%
1
2
2
2
0_0402_5%
CHARGER_SMBCLK
@ PT2 PAD~D
GNDA_CHG
2
PC729
1U_0603_25V6K
1
2
<9,36,45,46>
12
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
1
PC703
0.1U_0402_25V6
2
1
I_SYS
11
1
PR714
PR788
20K_0402_1%
1
2
I_BATT
1 BQ24770_REGN
<36>
<36>
28
6
PC719
100P_0402_50V8J
1
2
2
GNDA_CHG
I_ADP
PU700
+DCIN
1
0.1U_0402_25V6
PC718
100P_0402_50V8J
1
2
PR709
1M_0402_1%
2
1
6
1
2
1
<36>
PC709
1U_0805_25V6K
2
1
3
@ PT1 PAD~D
CHARGER_SMBDAT
PC702
0.1U_0402_25V6
1
2
GNDA_CHG
PR730
4.02K_0402_1%
GNDA_CHG
PR716
1
PR718
1
PR720
1
2
PC701
1U_0603_25V6K
1
2
PC712
0.047U_0603_25V7K~D
2
1
1
PC711
<36>
PR715
154K_0402_1%
D
PR711
49.9K_0402_1%
2
1
<36>
ACAV_IN
1
S
BQ24770_REGN
3
2
PR705
0_0402_5%
ACDRV
4
1
2
PR708
SDMK0340L-7-F_SOD323-2~D
10_1206_5%
<36>
G
PR713
100K_0402_1%
100_0402_1%
1
1
1
2
SDMK0340L-7-F_SOD323-2~D
PD705
PQ711
DMN65D8LW-7_SOT323-3
AC Det
Max:16.82V
Typ :16.54V
Min :16.26V
CSSN_1
CSSP_1
PR731
4.02K_0402_1%
2
1
2
1
2
3
DCX124EK-7-F_SC74R-6
PR704
0_0402_5%
+PBATT
AC_DIS
5
@
PR703
PD704
+DC_IN
DCX124EK-7-F_SC74R-6
@ PQ708A
CHARGER_SMBCLK
CHARGER_SMBDAT
pull up 10K in HW side (R827 R828)
PC721
2
PAD-OPEN 1x2m~D
4
2
1
+DC_IN
<36,46>
CHAGER_SRC
PJP700
1
3
1
PR737
4.7_0402_1%
1
@ PQ708B
2
2
+PWR_SRC_AC
4
2200P_0402_50V7K4.7_1206_5% 1000P_0603_50V7K
PC730
0.1U_0402_25V6
2
2
1
PR701
0.01_1206_1%
+SDC_IN
EMC12UnonD@
PC731
0.022U_0603_50V7K
1
4
+DC_IN
D
EMC@ PL700
1UH_PCMB042T-1R0MS_4.5A_20%
2
1
SIS496EDNT-T1-GE3 1N POWERPAK1212-8
PQ710
PQ709
SI7716ADN-T1-GE3_POWERPAK8-5
1+DC_IN_SS
1
2
2
5
3
3
5
GNDA_CHG
BATDRV#
3
3
PD703
PDS5100H-13_POWERDI5-3
3
1
2
PQ701
SI4835DDY-T1-E3_SO8
1
2
3
8
7
6
5
+PBATT
4
+VCHGR
BATDRV#
4
4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
Charger
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.1
LA-A902P
D
Sheet
46
of
47
5
4
3
D
2
1
PC900
22U_0805_6.3V6M
1
2
2
1
PC901
22U_0805_6.3V6M
1
PC913
22U_0805_6.3V6M
+
2
C
1
PC914
22U_0805_6.3V6M
2
2
1
PC903
22U_0805_6.3V6M
1
PC915
2.2U_0805_10V6K
2
2
PC904
22U_0805_6.3V6M
D
962
1
PC916
2.2U_0805_10V6K
2
PC105
PC917 @
22U_0805_6.3V6M
2200P_0402_50V7K
PC966
220U 2.5V Y D2 ESR9M H1.9 SX
1
2
2
1
PC902
22U_0805_6.3V6M
1
Based on _RF Cheng. Hill
鄭鄭鄭(11257) for PT 20131107
+VCC_CORE
1
2
EMC14UnonD@
@ PC106
0.1U_0402_25V6
PC203
2200P_0402_50V7K
EMC14UnonD@
@ PC206
0.1U_0402_25V6
C
PC300
2200P_0402_50V7K
EMC14UnonD@
@ PC311
0.1U_0402_25V6
PR522
4.7_1206_5%
EMC14UnonD@
680P_0603_50V7K
PC520
@ PC521
2200P_0402_50V7K
B
PC508
EMC14UnonD@
EMC14UnonD@
0.1U_0402_25V6
PC713
2200P_0402_50V7K
EMC14UnonD@
B
@ PC732
0.1U_0402_25V6
PR726
PC721
680P_0603_50V7K
4.7_1206_5%
EMC14UnonD@
EMC14UnonD@
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
PROCESSOR DECOUPLING
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.1
LA-A902P
Sheet
1
47
of
47
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
Title
Request
Date Owner
Issue Description
Solution Description
Rev.
D
D
1
47
VCC_CORE
10/8
Compal
2
42
1.35V_MEN
10/8
RICHTEK
3
46
Charger
10/8
Compal
4
6
7
8
9
B
X01
To prevent IC damage
Add PR204
X01
Change PR715, PR729 to 154k
X01
Fine tune divider voltage
Change
Change
Change
Change
Change
PR307 to 7.5k
PR310, PR102, PR104, PR403 to 10k
PR100 to 6.49k
PR101 to 15k
PR402 to 8.66k
X01
+1.05V_M
+1.5V_RUN
+3V/+5V
10/22
VCC_CORE
10/31
Compal
Fine tune IMON
Add PR518, PR524, PR525
ALL
10/31
Compal
RF request
Pop PR522,PC508, PR726, PC721, PC713, PL501, PC520
X01
46
Charger
12/05
Compal
Has the same behavior with dock circuit
Add PQ711
X01
46
Charger
12/05
Compal
To add 2nd source
Remove PQ702 Add PQ709, PQ710
X01
46
Charger
12/05
Compal
To reduce leakage current
Remove PD701 Add PD704, PD705
X01
41,43,44
C
5
To prevent acoustic noise issue
Remove PC923, PC924, PC925, PC926, PC927, PC928, PC929, PC930, PC931,
PC940, PC941, PC943, PC946, PC947, PC948
Add PC966
45
ALL
Compal
To improve the ability of anti-noise
C
X01
10
46
Charger
3/03
Compal
To set OVP level
Remove PR729
11
46
Charger
3/03
Compal
To set IC function
Remove PC720
12
40
DCIN
3/03
Compal
For ME change request
Change PBATT1
X02
13
40
DCIN
3/03
Compal
For EMC change request
Add PD5 PC20 PC21 PC22 Remove PC11
X02
B
X02
Add PR788, PR799
X02
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
PWR P.I.R (1/1)
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.1
LA-A902P
Sheet
1
48
of
48
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
Title
Date
Request
Owner
Issue Description
Solution Description
Rev.
D
D
1
6
HW
2013/10/8
COMPAL
Follow intel reference circuit.
Add CC100, RC300 on CPU pin AC4, net name is PM_TEST_RST
0.2(X01)
2
27
HW
2013/10/8
COMPAL
Dell drop POA function.
Change JUSH1 from 26 pin to 20 pin, pin define follow E5
0.2(X01)
3
36
HW
2013/10/8
COMPAL
Dell drop POA function.
remove POA_WAKE# off page symbol
remove POA_ON/OFF#,make UE2.B62 to be NC pin
0.2(X01)
4
22
HW
2013/10/9
COMPAL
0.2(X01)
C
C
5
B
24
HW
2013/10/9
COMPAL
correct HDMI schematic error.
swap HDMI LANE0 & LANE2 BUS
0.2(X01)
0.2(X01)
6
23
HW
2013/10/9
COMPAL
Follow EMC suggestion
Change LI1,LI2,LI3,LI4,LI5,LI6,LI7,LI8,LI9,LV3,LV6,LV10,LV12,LV27
From SM070003K00 (S COM FI_ CHILISIN CMMI21T-900Y-N)
To
SM070003Y00 (S COM FI_ MURATA DLW21HN900HQ2L)
7
9
HW
2013/10/9
COMPAL
reserved for S3 within 2s , system shutdown
issue debug.
add RC26, reserved RC27.
0.2(X01)
8
36
HW
2013/10/9
COMPAL
board ID change.
RE79 change to 130K
0.2(X01)
9
24
HW
2013/10/9
COMPAL
SATA ciruit issue
Swap mSATA P & N
0.2(X01)
10
36
HW
2013/10/14
COMPAL
follow intel latest design guide.
pop RE56 and change from 8.2K to 10K , it's
resistor
11
7
HW
2013/10/16
COMPAL
RF requirement.
add CC14, CC15 and move CC12, CC13 to behind the
0.2(X01)
RESET_OUT# pull down
resistor
0.2(X01)
(RC72)
B
0.2(X01)
12
20,23,31,32
HW
2013/10/17
COMPAL
follow ESD recommend list.
change all ESD diode CPN
change DI2, DI3, DI5, DV4 from SCA00001100(S ZEN ROW PJDLC05C 3P C/A
SOT23) to SC600001600(S DIO ROW AZC199-02S.R7G C/C SOT23 ESD)
change DI1,DI6,DI4 from SC300002800(S DIO(BR) TVWDF1004AD0 DFN ESD)
to SC300002C00(S DIO(BR) L05ESDL5V0NA-4 SLP2510P8 ESD)
change DA1,DA2,DA3,DA6,DA7 from SCA00001L00(S ZEN ROW L30ESDL5V0C3-2
C/A SOT23 ESD) to SCA00002900(S ZEN ROW L03ESDL5V0CC3-2 C/A SOT-23
ESD)
13
38
HW
2013/10/17
COMPAL
power doesn't split VPRO & NPRO BOM.
add RZ41, RZ42, reserve it for VPRO & NVPRO option.
0.2(X01)
14
39
HW
2013/10/17
COMPAL
SSI design will cause LED behavior error.
QL1 Pin2,5 & QL2 Pin2 change from MASK_BASE_LEDS# to SYS_LED_MASK#
0.2(X01)
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
EE P.I.R (1/3)
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.3
LA-A972P
Sheet
1
60
of
70
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
Title
Date
Request
Owner
Issue Description
Solution Description
Rev.
15
20
HW
2013/10/17
COMPAL
To solve Line-on HDD dirty shut down issue.
UZ8 Pin2 change from +3.3V_ALW to 3.3V_RUN
0.2(X01)
16
28, 36, 38
HW
2013/10/17
COMPAL
follow Dell requirement.
Add back SUS_ON, change control pin from SUS_ON to SIO_SLP_S4#
1. UZ8.3 from SIO_SLP_S4# to SUS_ON
2. UE2.B23 → SUS_ON_EC , RPE10.2 → SUS_ON
3. add RE282, RE281, RE280, RE279
4. UE2.B9 → RUN_ON_EC
0.2(X01)
17
12
HW
2013/10/24
COMPAL
18
6
HW
2013/10/24
COMPAL
debug usage.
add RC301
0.2(X01)
add RC304, 100K pull down, on PCH_PLTRST#_EC
0.2(X01)
1
2
3
4
0.2(X01)
0.2(X01)
19
9
HW
2013/10/28
COMPAL
reserve it to prevent PCH_PLTRST# floating
when power on
20
6, 7, 22,
28
HW
2013/10/23
COMPAL
follow xtal vender suggest
it's designed for E5 Goliad, E6 GMLK doesn't
remove RZ1
need.
C
D
CC1 &CC2 change from 18PF to 3PF
CC8 & CC11 change from 18PF to 15PF
CL13 & CL14 change from 33PF to 27PF
RV81 change from 0 ohm to 2.2K & CV113 change to 18PF
C
21
23
HW
2013/10/29
COMPAL
0.2(X01)
22
30
HW
2013/10/29
COMPAL
23
12
HW
2013/10/29
COMPAL
To solve backdrive issue.
Change TPM_PIRQ# pull up ( RC247) to +3.3V_RUN from +3.3V_ALW_PCH
0.2(X01)
24
30
HW
2013/10/30
COMPAL
Dell doesn't support MODPHY.
add PJP36, depop QZ6, QZ10, RZ16, RZ5, CZ25, CZ38
0.2(X01)
25
7
HW
2013/11/2
COMPAL
SMBUS Pull High
Add RN3&RN4 pull high to +3.3V_RUN for DDR_XDP_WAN_SMBDAT/SMBCLK
0.2(X01)
26
21
HW
2013/11/2
COMPAL
EMC request.
Add RA42, RA43.
0.2(X01)
add CA12, CA13
change DA1, DA2, DA3, DA4 from GNDA to GND
0.2(X01)
move TPM_PIRQ# from PCH_GPIO14 to PCH_GPIO17, add T21 on PCH_GPIO14
0.2(X01)
0.2(X01)
B
B
27
21
HW
2013/11/05
COMPAL
follow vender suggestion. It's for 15KV
ESD fail issue.
28
12
HW
2013/11/05
COMPAL
GPIO 14 is sus power well, it has risk to
cause back drive.
39
21
HW
2013/12/17
COMPAL
0.3(X01)
40
22
HW
2013/12/17
COMPAL
0.3(X01)
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
EE P.I.R (2/3)
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.3
LA-A972P
Sheet
1
61
of
70
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
Title
Date
Request
Owner
Issue Description
Solution Description
Rev.
D
D
29
22
HW
2013/12/17
COMPAL
30
22
HW
2013/12/17
COMPAL
31
22
2013/12/17
COMPAL
32
7
2013/12/27
COMPAL
HW
HW
0.3(X01)
1.POP RE88,UZ6,RE51
2. remove QZ12,RZ48,RZ49,RZ50
Base on Pre-PT RSMRST EA result
0.3(X01)
0.3(X01)
Intel recommend
Change RC33, RC34 from 1k to 499 ohm
0.3(X01)
C
C
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
EE P.I.R (3/3)
Size
Document Number
Date:
Monday, March 17, 2014
Rev
0.3
LA-A971P
Sheet
1
62
of
70
www.s-manuals.com
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