Compal NM A281P Schematics. Www.s Manuals.com. R0.4 Schematics
User Manual: Motherboard Compal NM-A281P ACLU5/ACLU6 - Schematics. Free.
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A B C D E 1 1 LCFC Confidential G Project M/B Schematics Document 2 2 AMD FT3B Beema SOC with DDRIIIL AMD JET-LE 2014-2-12 REV:0.4 3 3 4 4 Title LC Future Center Secret Data Security Classification Issued Date 2013/08/15 Deciphered Date 2013/08/15 Cover Page THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 A B C D Sheet E 1 of 60 A B C D E LCFC confidential File Name : ACLU5&6 AMD Jet LE/ Topaz XT S3 Package: 23mmX23mm PCI-Express 4x Gen2 Page 18~24 PEG 0~3 VRAM 256/128*16 DDR3L*4 2GB/1GB 1 Memory BUS (DDR3L) Single Channel DDR3L-SO-DIMM X2 Page 14,15 1.35V DDR3L 1600 MT/s 1 UP TO 8G x 2 Page 25~26 HDMI HDMI Conn. USB Left Page 34 USB 3.0 1x AMD FT3b APU VGA CRT Conn. USB 2.0 2x USB 2.0 Port8 USB 3.0 Port0 JUSB2 USB 2.0 Port3 Page 36 JUSB1 Page 41 eDP x2 Lane eDP Conn Beema 15W /2.4G USB2.0 1x Int. Camera USB 2.0 1x Touch Screen Page 33 USB2.0 Port5 USB2.0 Port4 (Integrated FCH) 2 2 Int. MIC Conn. Page 33 USB2.0 1x USB Right USB2.0 Port0 JUSB3 (Debug Port) SATA HDD Page 42 SATA Gen3 SATA Port0 SATA ODD Page 42 USB2.0 1x BGA-769 24.5mm*24.5mm SATA Gen1 USB 2.0 1x RTL8111GUL (1G) RTL8106EUL (10M/100M) Page 38 3 Page 37 SD/MMC Conn. USB Board SATA Port1 LAN Realtek RJ45 Conn. Cardreader Realtek RTS5170 USB2.0 Port2 PCIe 1x PCIe 1x NGFF Card WLAN&BT PCIe Port1 USB2.0 Port6 Page 40 PCIe Port2 SPI BUS HD Audio Page 4~9 Codec SPI ROM 0 8MB Page 07 Sub-board ( for 14") 3 POWER BOARD NS-A272 USB Board NS-A271 SPK Conn. Conexant CX20752 Page 43 Page 43 Sub-board ( for 15") EC ITE IT8586E-LQFP Page 44 HP&Mic Combo Conn. USB Board Touch Pad Page 45 4 Int.KBD Page 45 Thermal Sensor NCT7718W POWER BOARD NS-A273 USB Board NS-A275 ODD Board NS-A274 4 Page 39 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 2013/08/15 Deciphered Date Block Diagram THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 A B C D E Sheet 2 of 60 A B Voltage Rails ( O --> Means ON C E , X --> Means OFF ) Board ID need to be update! +5VS +1.8VS +1.5VS B+ +5VALW VL +3VALW +3VL +1.8VALW 1 SIGNAL STATE +3VS power plane D +1.35V +0.95VS (+VSYSMEN) +0.675VS +APU_CORE +APU_CORE_NB SLP_S3# SLP_S5# +VALW +V +VS Clock BOARD Config. GPIOxx HIGH HIGH ON ON ON ON S1 (Power On Suspend) HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW ON OFF OFF OFF S5 (Soft OFF) LOW LOW ON OFF OFF OFF GPIOxx GPIOxx 0 S0 (Full ON) 0 Function 0 1 +VGA_CORE State +0.95VALW +3VGS +1.8VGS +1.35VGS USB Port Table +0.95VGS USB 2.0 USB 3.0 2 S0 O O O S3 O O O S5 S4/AC O S5 S4/ Battery only S5 S4/AC & Battery don't exist O X X O EC_SMB_CK1 EC_SMB_DA1 3 EC_SMB_CK2 EC_SMB_DA2 APU_SCLK0 APU_SDATA0 X O X X X X X X X xHCI 0 1 BOM Structure Table 3 External USB Port RIGHT USB (2.0) N/A Card Reader LEFT USB (2.0) Touch Screen Camera Blue Tooth N/A LEFT USB (3.0) N/A BOM Structure @ ME@ 14@ 15@ UMA@ PX@ 8106EUL@ 8111GUL@ GIGA@ TS@ ZODD@ AOAC@ HDT@ Kabini@ SDV@ PCIE PORT LIST GPU IT8586E X BATT V IT8586E IT8586E SODIMM Port WLAN Thermal Sensor X X X X X V V V X +3VALW +3VALW IT8586E V +3VS +3VS_VGA X IT8586E +3VS APU X +3VS 0 1 2 3 4 5 6 7 8 9 EHCI SMBUS Control Table SOURCE Port X X APU X APU_SIC APU_SID V APU_SIC APU_SID APU Charger 0 1 2 3 0 1 2 3 GPP V X GFX 4 Device Address Battery 0X16 Thermal Sensor 1001_100xb Charger 0001 0010 b GPU 0x41(default) APU Thermal Diode TBU For 15" part UMA SKU ID part Discrete GPU SKU ID part 8106EUL LAN part 2 8111GUL LAN Part Giga LAN Part Touch Screen part Zero Power ODD part AOAC support part HDT Debug part Kabini APU part SDV PWR part 3 GPU X EC SM Bus2 address Address For 14" part Device VRAM Device Connector N/A WLAN LAN N/A +3VS EC SM Bus1 address BTO Item Not stuff X76 SAMSUNG 2G S2G@ M2G@ H2G@ S1G@ M1G@ H1G@ X76 MICRON 2G X76 HYNIX 2G X76 SAMSUNG 1G X76 MICRON 1G X76 HYNIX 2G APU SM Bus address Device Address DDR DIMMA 1001 000Xb DDR DIMMB 1001 010Xb WLAN RSVD 4 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 2013/08/15 Deciphered Date Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 A B C D E Sheet 3 of 60 5 4 3 2 1 Beema (MEM & PCIE I/F) D D UC1A OK<14,15> MEMORY DDRA_MA[15..0] DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11 DDRA_MA12 DDRA_MA13 DDRA_MA14 DDRA_MA15 AG38 W35 W38 W34 U38 U37 U34 R35 R38 N38 AG34 R34 N37 AN34 L38 L35 DDRA_BS0# DDRA_BS1# DDRA_BS2# AJ38 AG35 N34 M_ADD0 M_DATA0 M_ADD1 M_DATA1 M_ADD2 M_DATA2 M_ADD3 M_DATA3 M_ADD4 M_DATA4 M_ADD5 M_DATA5 M_ADD6 M_DATA6 M_ADD7 M_DATA7 DDRA_BS0# DDRA_BS1# DDRA_BS2# DDRA_DM[7..0] M_ADD9 M_DATA8 M_ADD10 M_DATA9 M_ADD11 M_DATA10 M_ADD12 M_DATA11 M_ADD13 M_DATA12 M_ADD14 M_DATA13 M_ADD15 @ 1 TC10 B32 B38 G40 N41 AG40 AN41 AY40 AY34 Y40 M_DATA14 C OK <14,15> DDRA_DQS[0..7] OK<14,15> DDRA_DQS#[0..7] DDRA_DQS[0..7] DDRA_DQS#[0..7] TC15 TC16 M_DATA16 M_BANK2 M_DATA17 M_DM0 M_DATA19 M_DM1 M_DATA20 M_DM2 M_DATA21 M_DM3 M_DATA22 M_DM4 OK OK SODIMM1 <14> <14> <14> <14> <15> <15> <15> <15> DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# DDRA_CLK2 DDRA_CLK2# DDRA_CLK3 DDRA_CLK3# DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# DDRA_CLK2 DDRA_CLK2# DDRA_CLK3 DDRA_CLK3# AC35 AC34 AA34 AA32 AE38 AE37 AA37 AA38 M_DATA23 M_DM6 M_DATA24 M_DM7 M_DATA25 M_DM8 M_DATA26 M_DQS_H0 M_DATA28 M_DQS_L0 M_DATA29 M_DQS_H1 M_DATA30 M_DQS_L1 G38 MEM_MA_RST# MEM_MA_EVENT#AE34 MEM_MA_RST# MEM_MA_EVENT# M_DATA31 M_DQS_L2 M_DATA32 M_DQS_H3 M_DATA33 M_DQS_L3 M_DATA34 M_DQS_H4 M_DATA35 M_DQS_L4 M_DATA36 M_DQS_H5 M_DATA37 M_DQS_L5 M_DATA38 M_DQS_H6 SODIMM0 OK SODIMM1 <14> <14> <15> <15> DDRA_CKE0 DDRA_CKE1 DDRA_CKE2 DDRA_CKE3 L34 J38 J37 J34 DDRA_ODT0 DDRA_ODT1 DDRA_ODT2 DDRA_ODT3 AN38 AU38 AN37 AR37 DDRA_CS0# DDRA_CS1# DDRA_CS2# DDRA_CS3# AJ34 AR38 AL38 AN35 DDRA_RAS# DDRA_CAS# DDRA_WE# AJ37 AL34 AL35 +MEM_VREF T_APU_M_VREFDQ AD40 AC38 DDRA_CKE0 DDRA_CKE1 DDRA_CKE2 DDRA_CKE3 M_DATA39 M_DQS_H7 M_DATA40 M_DQS_L7 M_DATA41 M_DQS_H8 M_DATA42 M_DQS_L8 M_DATA43 M_CLK_H0 M_DATA45 M_CLK_L0 M_DATA46 M_CLK_H1 M_DATA47 OK SODIMM0 OK SODIMM1 OK SODIMM0 <14> <14> <15> <15> DDRA_ODT0 DDRA_ODT1 DDRA_ODT2 DDRA_ODT3 <14> <14> <15> <15> DDRA_CS0# DDRA_CS1# DDRA_CS2# DDRA_CS3# OK OK<14,15> OK<14,15> OK<14,15> DDRA_RAS# DDRA_CAS# DDRA_WE# SODIMM1 M_CLK_H2 M_DATA48 M_CLK_L2 M_DATA49 M_CLK_H3 M_DATA50 M_CLK_L3 M_DATA51 M_RESET_L M_DATA53 M_EVENT_L M_DATA54 M41 N40 T41 U40 L40 M40 R40 T40 DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31 AF40 AF41 AK40 AK41 AE40 AE41 AJ40 AJ41 DDRA_DQ36 DDRA_DQ37 DDRA_DQ34 DDRA_DQ35 DDRA_DQ32 DDRA_DQ33 DDRA_DQ38 DDRA_DQ39 OK WLAN <40> <40> PCIE_PRX_DTX_P4 PCIE_PRX_DTX_N4 LAN <37> <37> PCIE_PRX_DTX_P3 PCIE_PRX_DTX_N3 OK P_GPP_RXP0 P_GPP_TXP0 P_GPP_RXN0 P_GPP_TXN0 PCIE_PRX_DTX_P4 PCIE_PRX_DTX_N4 R5 R4 P_GPP_RXP1 P_GPP_TXP1 P_GPP_RXN1 P_GPP_TXN1 PCIE_PRX_DTX_P3 PCIE_PRX_DTX_N3 N5 N4 P_GPP_RXP2 P_GPP_TXP2 P_GPP_RXN2 P_GPP_TXN2 N10 N8 P_GPP_RXP3 P_GPP_TXP3 P_GPP_RXN3 P_GPP_TXN3 +0.95VS_GFX_APU 1 RC7 2 1.69K_0402_1% P_TX_ZVDD W8 L2 L1 ACLU1 PCIE_PTX_DRX_P4 PCIE_PTX_DRX_N4 .1U_0402_10V6-K 1 .1U_0402_10V6-K 1 2 CC21 2 CC22 PCIE_PTX_C_DRX_P4 PCIE_PTX_C_DRX_N4 J2 J1 PCIE_PTX_DRX_P3 PCIE_PTX_DRX_N3 .1U_0402_10V6-K 1 .1U_0402_10V6-K 1 2 CC19 2 CC20 PCIE_PTX_C_DRX_P3 PCIE_PTX_C_DRX_N3 H2 H1 P_RX_ZVDD_095 W7 P_TX_ZVDD_095 Net name changed to same as K2 K1 +0.95VS_GFX_APU 2 P_RX_ZVDD 1K_0402_1% PCIE_PTX_C_DRX_P4 PCIE_PTX_C_DRX_N4 <40> <40> PCIE_PTX_C_DRX_P3 PCIE_PTX_C_DRX_N3 <37> <37> WLAN OK LAN OK OK swap DQ32/33 and DQ36/37 @ 09/06 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 L5 L4 1 RC8 C P_GFX_RXP0 P_GFX_TXP0 P_GFX_RXN0 P_GFX_TXN0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 J5 J4 P_GFX_RXP1 P_GFX_TXP1 P_GFX_RXN1 P_GFX_TXN1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 G5 G4 P_GFX_RXP2 P_GFX_TXP2 P_GFX_RXN2 P_GFX_TXN2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 D7 E7 P_GFX_RXP3 P_GFX_TXP3 G2 G1 PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0 .1U_0402_10V6-K 1 .1U_0402_10V6-K 1 2 CC11 PX@ 2 CC12 PX@ PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 F2 F1 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1 .1U_0402_10V6-K 1 .1U_0402_10V6-K 1 2 CC13 PX@ 2 CC14 PX@ PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 E2 E1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2 .1U_0402_10V6-K 1 .1U_0402_10V6-K 1 2 CC15 PX@ 2 CC16 PX@ AM41 DDRA_DQ40 AN40 DDRA_DQ41 AT41 DDRA_DQ42 AU40 DDRA_DQ43 AL40 DDRA_DQ44 AM40 DDRA_DQ45 AR40 DDRA_DQ46 AT40 DDRA_DQ47 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 D2 D1 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3 .1U_0402_10V6-K 1 .1U_0402_10V6-K 1 2 CC17 PX@ 2 CC18 PX@ PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3 GPU OK<19> OK<19> P_GFX_RXN3 P_GFX_TXN3 PCIE_CTX_C_GRX_P[0..3] OK <19> PCIE_CTX_C_GRX_N[0..3] OK <19> ROUTE PCIE-LINK DIFF PAIR @ 85 OHM +/- 10% PCIE_CRX_GTX_P[0..3] FT3 REV 0.53 PCIE_CRX_GTX_N[0..3] @ Beema FT3-REV-0P53_BGA769 AV41 DDRA_DQ48 AW40 DDRA_DQ49 BA38 DDRA_DQ55 AY37 DDRA_DQ51 AU41 DDRA_DQ52 AV40 DDRA_DQ53 AY39 DDRA_DQ54 AY38 DDRA_DQ50 swap DQ55 and DQ50 @ 09/06 M0_CKE0 M0_CKE1 M_DATA56 M1_CKE0 M_DATA57 M1_CKE1 M_DATA58 M0_ODT0 M_DATA60 M0_ODT1 M_DATA61 M1_ODT0 M_DATA62 M1_ODT1 M_DATA63 M0_CS_L0 M_CHECK0 M0_CS_L1 M_CHECK1 M1_CS_L0 M_CHECK2 M1_CS_L1 M_CHECK3 BA36 AY35 BA32 AY31 BA37 AY36 BA33 AY32 M_CHECK7 V41 W40 AB40 AC40 U41 V40 AA41 AB41 M_ZVDDIO_MEM_S AD41 M_CHECK4 @ 1 OK R10 R8 M_CLK_L1 M_DATA59 B UC1B M_DQS_L6 M_DATA55 OK DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 M_DQS_H2 M_DATA52 <14,15> <14,15> F40 F41 K40 K41 E40 E41 J40 J41 M_DM5 M_DATA44 SODIMM0 DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 PCIE M_BANK1 M_DATA27 B33 DDRA_DQS0 A33 DDRA_DQS#0 B40 DDRA_DQS1 A40 DDRA_DQS#1 H41 DDRA_DQS2 H40 DDRA_DQS#2 P41 DDRA_DQS3 P40 DDRA_DQS#3 DDRA_DQS4 AH41 DDRA_DQS#4 AH40 AP41 DDRA_DQS5 DDRA_DQS#5 AP40 BA40 DDRA_DQS6 DDRA_DQS#6 AY41 AY33 DDRA_DQS7 DDRA_DQS#7 BA34 @ 1T_DDRA_DQS8 AA40 @ 1T_DDRA_DQS#8 Y41 B37 A38 D40 D41 B36 A37 B41 C40 <14,15>OK DDRA_DQ[63..0] M_BANK0 M_DATA18 DDRA_DM0 DDRA_DM1 DDRA_DM2 DDRA_DM3 DDRA_DM4 DDRA_DM5 DDRA_DM6 DDRA_DM7 T_DDRA_DM8 DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 M_ADD8 M_DATA15 OK<14,15> OK<14,15> OK<14,15> OK<14,15> B30 A32 B35 A36 B29 A30 A34 B34 M_RAS_L M_CHECK5 M_CAS_L M_CHECK6 M_WE_L DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63 B ECC +VSYSMEM_APU OK M_VREF M_VREFDQ TC35 2 RC1 1 39.2_0402_1% FT3 REV 0.53 @ Beema FT3-REV-0P53_BGA769 R103 connection to VDDIO_SUS should be directly to the plane without a long trace OK 1 +VSYSMEM_APU MEM Reference Voltage RC4 1K_0402_1% 2 EVENT# pull high +MEM_VREF @ 2 1 2 1 2 CC2 1000P_0402_50V7K 2 1 CC1 .1U_0402_10V6-K RC5 1K_0402_1% CC115 .47U_0402_6.3V6K 1 +VSYSMEM_APU RC6 1 OK 2 1K_0402_5% UC1 UC1 UC1 UC1 BEEMA AM6400ITJ44JB 2.4G ZM181103J4470 1.8G ZM151103J4470 1.5G ZM1332M2J2370 1.35G SA000065O10 SA000067O00 SA000067P00 MEM_MA_EVENT# Layout: Place within 1000 SA000067Q00 mils of the APU socket. A ZZZ A PCB NM-A281 DA60000U810 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Beema (MEM & PCIE I/F) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 4 of 60 5 4 3 2 1 Beema (DISPLAY/CLK/MISC) S0 @ APU_SIC RC2281 TB RS APU_SID RC2291 TB RS 2 0_0402_5% @ 2 0_0402_5% EC_SMB_CK2 <20,39,44> EC_SMB_DA2 <20,39,44> +3VS APU_CRT_HSYNC RC67 1 RC66 1 @ 2 1K_0402_5% 2 1K_0402_5% NOTE: APU_CRT_HSYNC PU FOR AMD INTERNAL,PD FOR CUSTOMER D D +3VS UC1C DISPLAY/SVI2/JTAG/TEST OK OK HDMI <34> <34> APU_HDMI_TX2+ APU_HDMI_TX2- <34> <34> APU_HDMI_TX1+ APU_HDMI_TX1- <34> <34> APU_HDMI_TX0+ APU_HDMI_TX0- <34> <34> APU_HDMI_CLK+ APU_HDMI_CLK- <33> <33> eDP <33> <33> Net name changed to same as A9 B9 TDP1_TXP0 DP_150_ZVSS TDP1_TXN0 DP_2K_ZVSS APU_HDMI_TX1+ APU_HDMI_TX1- A10 B10 TDP1_TXP1 DP_DIGON B16 DP_150_ZVSS A21 DP_2K_ZVSS B17 O PCH_ENBKL A17 O PCH_ENVDD DP_VARY_BL A18 O PCH_EDP_PWM TDP1_TXN1 APU_HDMI_TX0+ APU_HDMI_TX0- A11 B11 TDP1_TXP2 APU_HDMI_CLK+ APU_HDMI_CLK- A12 B12 TDP1_TXP3 CPU_EDP_TX0+ CPU_EDP_TX0- A4 B4 LTDP0_TXP0 LTDP0_AUXP LTDP0_TXN0 LTDP0_AUXN CPU_EDP_TX1+ CPU_EDP_TX1- A5 B5 LTDP0_TXP1 LTDP0_HPD TDP1_TXN2 TDP1_AUXP TDP1_TXN3 TDP1_HPD OK OK <44> APU_PWROK H_PROCHOT# TB RS B14 A6 B6 LTDP0_TXP2 LTDP0_TXN2 DAC_GREEN A14 T_TDP0_TXP3 T_TDP0_TXN3 A7 B7 LTDP0_TXP3 DAC_BLUE B15 TC17 TC18 @ 1 @ 1 T_DISP_CLKP T_DISP_CLKN K15 H15 APU_SVT APU_SVC APU_SVD APU_SVT APU_SVC APU_SVD I G31 O D27 I/O E29 B22 B21 APU_SIC APU_SID 3.3V Level DISP_CLKIN_H DAC_VSYNC SVT SVD A16 DAC_ZVSS SIC H27 H29 D25 A27 B27 A26 B26 B28 I A28 I B24 I A24 I AV35 AU35 E33 1 APU_TEST4_THERMDA 1 APU_TEST5_THERMDC 1 APU_TEST6 NC APU_TEST14_BP0 RC55 1 APU_TEST15_BP1 RC56 1 APU_TEST16_BP2 RC57 1 APU_TEST17_BP3 RC58 1 APU_TEST18_PLLTEST1 RC44 1 APU_TEST19_PLLTEST0 RC45 1 APU_TEST25_H_BYPASSCLK RC59 1 APU_TEST25_L_BYPASSCLK RC1491 1 @ APU_TEST28_H_PLLCHARZ 1 @ APU_TEST28_L_PLLCHARZ 1 @ APU_TEST31_MEM_TEST A29 H21 H25 APU_TEST34_L_TSTCLKIN_L APU_TEST36 APU_TEST37 1 @ TC28 AJ10 AJ8 R32 N32 AP29 APU_TEST42_USB_ATEST0 APU_TEST43_USB_ATEST1 APU_TEST39 APU_TEST40 APU_TEST41_TMON_CAL 1 1 1 1 1 TC25 TC26 TC29 TC30 TC27 TEST4 SID TEST5 TEST6 LDT_RST_L TEST15 APU_PWROK APU_PWROK_R I B19 OD A19 APU_PWROK TEST16 TEST17 LDT_PWROK TEST18 PROCHOT_L TEST25_H TEST19 ALERT_L TEST25_L TDI TEST28_L TDO TEST31 OK <59> @ 1 TC31 APU_VDD_SEN_L @ 1 @ 1 TC60 TC61 VDDIO_MEM & VDD_0.95 D23 G23 VDDIO_SUS_SENSE E25 E23 VDD_095_FB_H VDD_095_FB_L AV33 AU33 RC31 1 RC32 1 OK <36> APU_CRT_G OK <36> APU_CRT_B OK <36> 1 CPU_EDP_HPD <36> <36> APU_CRT_DDC_CLK APU_CRT_DDC_DATA 4.7K_0402_5% 4.7K_0402_5% 2.2K_0402_5% 4.7K_0402_5% 4.7K_0402_5% RC13 RC14 2 2 1 1 1K_0402_5% 1K_0402_5% 2 2 300_0402_5% 300_0402_5% RC163 1 APU_RST# APU_PWROK 2 100K_0402_5% STUDY C <36> <36> OK 2 499_0402_1% @ @ @ @ @ @ @ TC19 TC20 Thermal Sensor? TC21 2 1K_0402_5% 2 1K_0402_5% 2 1K_0402_5% 2 1K_0402_5% 2 1K_0402_5% 2 1K_0402_5% +1.8VS_APU 2 510_0402_1% 2 510_0402_1% TC22 TC23 TC24 OK +1.8VS_APU A29 For STAMP APU_TEMPIN0 TCK TMS RSVD TRST_L TEST36 DBRDY TEST37 DBREQ_L TEST42 APU_VDDNB_SEN_H APU_VDD_SEN_H RC18 2 2 2 1 1 +1.8VS_APU OK <33> APU_CRT_HSYNC APU_CRT_VSYNC DAC_ZVSS 1.8V 1.8V OK <59> OK <59> 2 150_0402_1% ALERT# APU_PROCHOT#_R 1 1 1 2 2 OK <34> APU_CRT_R G19 I/OAPU_CRT_HSYNC E19 O DAC_SDA TEST14 D29 D31 D35 D33 G27 B25 A25 2 150_0402_1% SVC APU_RST_L APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ# 2 150_0402_1% RC22 1 APU_CRT_DDC_CLK APU_CRT_DDC_DATA I B20 OD A20 OK RC21 1 OK OK RC160 RC161 @ RC162 RC53 RC54 The processor asserts PROCHOT_L when the hardware thermal control (HTC) is active. External hardware can assert PROCHOT_L to reduce APU power consumption by forcing HTC activation. <33>OK OK <33> CPU_EDP_HPD D19 D21 DAC_SCL APU_RST# APU_RST#_R CC4 150P_0402_50V8-J @ APU_HDMI_HPD DISP_CLKIN_L 1.8V APU_PROCHOT#_R A22 OD B18 ALERT# <34>OK OK <34> APU_HDMI_DDC_CLK APU_HDMI_DDC_DATA CPU_EDP_AUX CPU_EDP_AUX# RC23 1 LTDP0_TXN3 DAC_HSYNC 1 2 CPU_EDP_HPD DAC_RED TEST28_H 2 H17 IPD T_TDP0_TXP2 T_TDP0_TXN2 A19 For STAMP APU_TEMPIN2 1 CC3 150P_0402_50V8-J @ CPU_EDP_AUX CPU_EDP_AUX# @ 1 @ 1 A20 For STAMP APU_TEMPIN1 RC29 1 Kabini@ 2 0_0402_5% @ 2 0_0402_5% RC147 1 D15 E15 @ 1 @ 1 RC28 1 Kabini@ 2 0_0402_5% Output to APU Vcore VR SVID EN Pin APU_HDMI_HPD TC52 TC53 OK OK OK <59> APU_HDMI_DDC_CLK APU_HDMI_DDC_DATA H19 IPD TC62 TC63 OK <59> OK <59> OK <59> Avoid plane splits and signal plane changes, route on single routing layer. D17 E17 APU_HDMI_DDC_CLK APU_HDMI_DDC_DATA APU_HDMI_HPD APU_CRT_DDC_CLK APU_CRT_DDC_DATA +3VS <33>OK <33>OK OK <33> PCH_ENBKL PCH_ENVDD PCH_EDP_PWM SDA. LTDP0_TXN1 2 Lane is OK to support FHD Panel SVID I/F: Do not terminate. OK OK 2 150_0402_1% 2 2K_0402_1% In I2C mode AUXP pins change to SCL, and AUXN pins change to DisplayPort Auxiliary Channel pins are dual-mode pins. TDP1_AUXN CPU_EDP_TX1+ CPU_EDP_TX1- C RC10 1 RC11 1 DP_BLON CPU_EDP_TX0+ CPU_EDP_TX0- ACLU1 APU_HDMI_TX2+ APU_HDMI_TX2- OK OK OK OK OK VDDCR_NB_SENSE TEST43 VDDCR_CPU_SENSE TEST39 VDDIO_MEM_S_SENSE TEST40 VSS_SENSE TEST41 DP_STEREOSYNC E21 VDD_095_FB_H VDD_095_FB_L @ @ @ @ @ O APU_TEST35_STEREOSYNC To drive active shutter glasses for stereoscopic 3D viewing on 120-Hz panels RC60 RC61 RC62 RC63 1 1 1 1 @ @ @ @ 2 2 2 2 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% OK +1.8VS_APU RC65 1 RC64 1 @ @ 2 1K_0402_5% 2 1K_0402_5% return path is optional, so remove. FT3 REV 0.53 @ B Beema FT3-REV-0P53_BGA769 B OK +1.8VS_APU +1.8VS_APU +1.8VS_APU +1.8VS_APU HDT+ Header +1.8VS_APU JHDT1 @ 3 2 APU_RST# 1 2A 2Y GND VCC 1 1 HDT@ RC38 1K_0402_5% 3 5 2 1 4 2 UC2 HDT@ APU_PWROK RC33 300_0402_5% HDT@ 2 RC27 300_0402_5% HDT@ 7 APU_PWROK_BUF 9 APU_TRST# 5 6 1A 1Y SN74LVC2G07YZPR_WCSP6 Change to 1 2 3 4 APU_RST#_BUF SN74LVC2G07DCK SOT 8 7 6 5 11 13 15 APU_PWROK RC2031 APU_RST# RC1931 10K_0804_8P4R_5% RCP1 HDT@ 2 0_0402_5% APU_PWROK_BUF 2 0_0402_5% APU_RST#_BUF @ @ 17 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2 APU_TCK 4 APU_TMS 6 APU_TDI 8 APU_TDO 10 APU_PWROK_BUF 12 APU_RST#_BUF 14 APU_DBRDY 16 APU_DBREQ# 18 APU_TEST19_PLLTEST0 20 APU_TEST18_PLLTEST1 1K_0804_8P4R_5% CC29 SAMTE_ASP-136446-07-B 5 4 Zx05 1 2 A .1U_0402_10V6-K A 1 1 CC5 .1U_0402_10V6-K HDT@ 2 RCP4 HDT@ 8 1 7 2 6 3 5 4 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Beema (DISPLAY/CLK/MISC) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 Symbol 3 2 1 Sheet 5 of 60 4 3 +3VS 1 1 2 RC170 2.2K_0402_5% RC171 2.2K_0402_5% DIMM1, DIMM2, Mini CARD 2 Default is H 2 1 RC210 10K_0402_5% @ SMB_CLK_S3 RC187 10K_0402_5% 14@ 1 1 CC6 150P_0402_50V8-J SMB_CLK_S3 <14,15,40> 2 RC189 10K_0402_5% PX@ RC188 10K_0402_5% RC209 10K_0402_5% @ D SMB_DATA_S3 1 LPC_RST#_R 1 2 RC190 10K_0402_5% @ 2 2 33_0402_5% 2 RC74 1 APU_LPC_RST# D RC185 10K_0402_5% UMA@ 1 1 <44> BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 2 GPIO49 GPIO51 GPIO71 GPIO70 1 CC121 150P_0402_50V8-J 2 2 1 RC186 10K_0402_5% 15@ 1 RC78 100K_0402_5% @ 2 ID1 HI is UMA , LO is DIS PCIE_RST#_R 2 2 33_0402_5% 2 RC75 1 PLT_RST# 1 SMB_CLK_S3 OK +3VS ID0 HI is 15' , LO is 14' PLT_RST# & APU_LPC_RST OK <19,37,40> 2 Broad ID OK 1 5 Beema (GEVENT/GPIO/SD/AZ) SMB_DATA_S3 <14,15,40> GPIO49/51/71 require external PH or PL, so used for Board ID GPIO70 is reserved and has interanl PH RSMRST# OK +3VS 2 1 10K_0402_5% <44> 10ms T RC86 EC_RSMRST# DC2 2 RSMRST#_R Need update symobol 2 2 1 10K_0402_5% <9> SYS_RESET# <44> <44> PM_SLP_S3# PM_SLP_S5# EC_SYS_PWRGD IPU S5 PM_SLP_S3# PM_SLP_S5# RC87 1 RC88 1 TB @ RS 2 0_0402_5% 1.8V Strap Pin PH TB RS TB @ RS 2 0_0402_5% 2 0_0402_5% @ I AY5 I BA8 IAM19 I PU AY7 PCIE_WAKE#_RA I PUAW11 PWRBTN#_R SYS_PWRGD_R O AY3 O BA5 PM_SLP_S3#_R PM_SLP_S5#_R TB RS S4/S5 is Low SD_PWR_CNTL SD_PWR_CTRL BA23 SD_CLK/GPIO73 AY22 I PU SD_CLK_R LPC_RST_L PCIE_RST_L RSMRST_L SD_CMD/GPIO74 SD_CD/GPIO75 PWR_BTN_L SD_WP/GPIO76 PWR_GOOD SYS_RESET_L/GEVENT19_L WAKE_L/GEVENT8_L SLP_S3_L SLP_S5_L 1 AU13 AY10 AY6 APU_TEST0 APU_TEST1 APU_TEST2 1 @ TC36 1 @ TC37 AY23 I PUSD_CMD_R AY20 I PU SD_CD# BA20 I PU SD_WP SD_DATA0/GPIO77 BA22 I SD_DATA1/GPIO78 AY21 I SD_DATA2/GPIO79 AY24 I SD_DATA3/GPIO80 BA24 I SD_LED/GPIO45 TC51 @ 1 TC64 @ 1 TC65 @ 1 RC85 10K_0402_5% DC4 1 2 RB751V-40_SOD323-2 <44> <44> <44> SYS_PWRGD_R 1 Need update symobol 2 AY25 O 1 @ TC38 1 @ TC39 1 @ TC40 PUSD_DATA0_R PUSD_DATA1_R PUSD_DATA2_R PUSD_DATA3_R 1 @ TC41 1 @ TC42 1 @ TC43 1 @ TC44 CC9 1U_0402_6.3V6K @ OK <42> OK 2 1 RC192 @ 0_0402_5% PCIE_WAKE#_RA APU_GEVENT22# 2 1 @ 0_0402_5% RC184 2 DC3 1 1 2 3 4 TEST1/TMS SCL0/GPIO43 TEST2 SDA0/GPIO47 1 @ TC45 SD_LED AU25 AV25 EC_WAKE# I I I I KBRST# GATEA20 EC_SCI# PU PU PU PU AR23 AR31 AN5 AL7 KBRST_L SCL1/GPIO227 GA20IN/GEVENT0_L SDA1/GPIO228 ODD_EN <40> <37> WLAN_CLKREQ# LAN_CLKREQ# <20> GPU_CLKREQ# <44> <43> HDA_SDIN0 IPU S5 I I I I I CLK_REQ#0 WLAN_CLKREQ# LAN_CLKREQ# CLK_REQ#3 GPU_CLKREQ# <41> OC1# for USB2.0x1 <45> OC1# for USB3.0x2 SDM10U45LP-7_DFN1006-2-2 @ I PU IPU S5 AC_PRESENT_R ODD_DETECT# GPI TC48 @ 1 IR_TX1 TC49 @ 1 IR_RX1 =>GPO ODD_EN ODD_DETECT# LPC_PME_L/GEVENT3_L LPC_SMI_L/GEVENT23_L GPIO49 USB_OC1# USB_OC2# RC1021 2 0_0402_5% @ GPIO51 AP15 AV13 BA9 BA10 AV15 PU AU29 PU AW29 PU AR27 PU AV27 PU AY29 USB_OC0# USB_OC1# USB_OC2# USB_OC3# AY8 AW1 AV1 AY1 HDA_BITCLK HDA_SDOUT HDA_SDIN0_R HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SYNC HDA_RST# AN2 AN1 AK2 AK1 AM1 AL2 AM2 AL1 +3VS 32K_X1 AJ2 32K_X2 AJ1 AY11 BA11 OK OK SMB_CLK_S3 SMB_DATA_S3 AC_PRES/IR_RX0/GEVENT16_L DEVSLP[0]/GPIO55 IR_TX0/GEVENT21_L GPIO57 IR_TX1/GEVENT6_L GPIO58 IR_RX1/GEVENT20_L DEVSLP[1]/GPIO59 IR_LED_L/LLB_L/GPIO184 GPIO64 SPKR/GPIO66 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60 GPIO68 CLK_REQ1_L/GPIO61 GPIO69 CLK_REQ2_L/GPIO62 GPIO70 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63 GPIO71 CLK_REQG_L/GPIO65/OSCIN GPIO174 AP27 AY28 BA28 AV23 AP21 BA26 AV19 AY27 BA27 AU21 AY26 AV21 AM21 BA3 AV17 GEVENT4_L BA4 GEVENT7_L AR15 GEVENT10_L AP17 GEVENT11_L AP11 GEVENT17_L AN8 BLINK/GEVENT18_L AU17 GEVENT22_L BA6 USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L GEVENT2_L USB_OC1_L/TDI/GEVENT13_L USB_OC2_L/TCK/GEVENT14_L USB_OC3_L/TDO/GEVENT15_L AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO167 APU_SCLK1 APU_SDATA1 RC164 RC165 I S0 GPI I S0 GPI IPU S0 =>GPO RC194 IPU S0 =>GPO IPU S0 =>GPO IPU S0 GPI IPU S0 =>GPO IPU S0 IPU S0 IPU S0 I S0 I S5 =>GPO =>GPO GPI GPI 1 1 BOARD_ID0 OK CMOS_ON# BOARD_ID1 OK 2 1 0_0402_5% @ PCH_BT_OFF# PCH_WLAN_OFF# 1 APU_GPIO59 PXS_RST#_R @ TC57 @TC57 GENINT1_L/GPIO32 AZ_SDIN3/GPIO170 GENINT2_L/GPIO33 BA29 AP23 OK OK 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2 2 2 2 2 2 PCIE_WAKE#_RA PBTN_OUT# PM_SLP_S3# PM_SLP_S5# AC_PRESENT_R ODD_EN ODD_DETECT# APU_SCLK1 APU_SDATA1 ODD_DA# APU_GEVENT22# USB_OC0# USB_OC1# USB_OC2# USB_OC3# 100K_0402_5% 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2 2 2 2 2 2 2 2 2 1 1 2 2 2 2 APU_TEST2 APU_TEST1 APU_TEST0 GPU_CLKREQ# 15K_0402_5% 2 15K_0402_5% 2 15K_0402_5% 2 10K_0402_5% 2 @ @ @ @ @ 1 1 1 1 1 1 RC168 RC169 RC172 RC173 RC174 RC230 CMOS_ON# <33> SATA0_DEVSLP PCH_BT_OFF# PCH_WLAN_OFF# OK OK <42> OK <40> OK <40> OK <43> @ @ 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 RC91 RC83 RC89 RC90 RC208 RC214 RC218 RC109 RC110 RC219 RC216 RC94 RC95 RC96 RC97 @ @ @ @ @ C 1 RC16 1 RC3 1 RC2 1 RC204 RSMRST#R PD is support Mirror core GEVENT2# APU_GEVENT4# APU_GEVENT7# @ TC54 @ TC55 ODD_DA# S5 APU_GEVENT22# APU_GPIO321 @ TC56 IPU S0 GPI VR_VGA_PWRGD OK PCH_BEEP Strap Pin PL AZ_SDIN1/GPIO168 AZ_SDIN2/GPIO169 S0 PWR Domain S5 PWR Domain 2 10K_0402_5% 2 10K_0402_5% PXS_PWREN_R VGA_PWROK_R BOARD_ID3 BOARD_ID2 APU_GPIO174 APU_GEVENT10#1 APU_GEVENT11#1 IPU S5 IPU Strap Pin PH IPU S5 GPI LAN_CLKREQ# WLAN_CLKREQ# CLK_REQ#0 CLK_REQ#3 GPU_CLKREQ# VGA_PWROK_R +3VALW_APU TEST0 GPIO50 <42> EC_WAKE# RC79 1 PBTN_OUT# PBTN_OUT# ACPI/SD/AZ/GPIO/RTC/MISC RC93 2 2 1 100K_0402_5% +1.8VALW_APU @ RC84 <44> <44> Panjit: BSS138 NXP: BSH111 Other one: FDV301N OR AO3414 +3VALW_EC +3VALW C 1.8V RSMRST#_R CC122 1U_0402_6.3V6K @ OK OK Provided test points or other means to allow access for debug purposes. UC1D O AY4 O AY9 LPC_RST#_R PCIE_RST#_R 1 RB751V-40_SOD323-2 SB00000PF0J SB50111001J (CRB PWR Dealy: 47K/1uF) RC81 10K_0402_5% 1 RCP2 8 7 6 5 CMOS_ON# PCH_BT_OFF# PCH_WLAN_OFF# 10K_0804_8P4R_5% 1 @ RC82 OK OK OK +1.8VALW_APU 2 2 1 100K_0402_5% +3VALW_EC +3VALW RSMRST#_R SYS_PWRGD_R HDA_BITCLK HDA_SDIN0_R HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 OK <9> 100K_0402_5% 100K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2 2 1 1 1 1 1 1 1 2 2 2 2 2 @ @ @ @ @ @ RC206 RC207 RC103 RC104 RC105 RC106 RC107 Integrated PU is not supported when the pin is configured for USB over current function ODD_DA# BLINK OK <42> <9> OK OK VR_VGA_PWRGD OK <19,58> AZ_SYNC AZ_RST_L FANIN0/GPIO56 AV31 AU31 RTCCLK AV11 FANOUT0/GPIO52 APU_GPIO521 @ TC58 APU_GPIO561 @ TC59 X32K_X1 These 3 GPIO pin use same one as Kabini CRB. RC221 1 PX@ 2 10K_0402_5% PXS_PWREN_R RC222 1 PX@ 2 10K_0402_5% PXS_RST#_R RC223 1 @ 2 10K_0402_5% YC1 VR_VGA_PWRGD 1 2 32.768KHZ_12.5PF_200458-PG14 X32K_X2 @ IPU S5 Strap Pin PH SUSCLK <40,9>OK FT3 REV 0.53 Beema FT3-REV-0P53_BGA769 VGA VR side has PH to +3VS B B RC108 1 1 20M_0402_5% RC224 1 @ 2 100K_0402_5% PXS_PWREN_R RC225 1 @ 2 100K_0402_5% PXS_RST#_R RC205 1 UMA@ 2 2K_0402_5% 2 2 CC118 20P_0402_50V8 @ @ @ CC119 20P_0402_50V8 2 RC226 2 RC227 2 RC211 1 2 RCP3 8 7 6 5 APU_GPIO174 APU_GEVENT4# APU_GEVENT7# 1 @ 1 PX@ 1 PX@ 1 PX@ RC92 RC12 RC9 RC15 AC_PRESENT PXS_PWREN PXS_RST# VGA_PWROK 2 2 2 2 0_0402_5% 1K_0402_5% 0_0402_5% 0_0402_5% AC_PRESENT_R PXS_PWREN_R PXS_RST#_R VGA_PWROK_R Output to GPU Vcore VR SVID EN Pin +3VALW_APU 10K_0402_5% 1 10K_0402_5% 1 10K_0402_5% 1 2 VIL Max is 0.7V VR_VGA_PWRGD OK <44> OK <23,58> OK <19> OK <19,44,58> APU_GEVENT4# APU_GEVENT7# APU_GPIO174 1 CC141 .1U_0402_10V6-K @ 1 2 3 4 10K_0804_8P4R_5% A A RCP6 <43> <43> <43> <43> 1 2 3 4 HDA_RST_AUDIO# HDA_SYNC_AUDIO HDA_BITCLK_AUDIO HDA_SDOUT_AUDIO 8 7 6 5 HDA_RST# HDA_SYNC HDA_BITCLK HDA_SDOUT 33_0804_8P4R_5% T PN change Idea pad PN:SD300003700 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Beema (GEVENT/GPIO/SD/AZ) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 6 of 60 5 4 3 2 1 Beema (SATA/USB/LPC/SPI/CLK) D D Net name changed to same as ACLU1 UC1E CLK/SATA/USB/SPI/LPC OK HDD <42> <42> SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 <42> <42> SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 <42> <42> OK SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 BA14 AY14 SATA_TX0P SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 BA16 AY16 SATA_RX0N SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 AY19 BA19 SATA_TX1P SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 AY17 BA17 SATA_RX1N AR19 AP19 SATA_ZVSS W4 USBCLK/14M_25M_48M_OSC SATA_RX0P USB_ZVSS AG4 USB_RCOMP USB_HSD0P AL4 AL5 USB20_P0 USB20_N0 USB_HSD0N SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_TX1N USB_HSD1P USB_HSD1N ODD <42> <42> SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 +0.95VS_APU SATA_RX1P USB_HSD2P USB_HSD2N RC114 RC115 OK 1 1 2 1K_0402_1% 2 1K_0402_1% SATA_CALRN SATA_CALRP SATA_ZVDD_095 USB_HSD3P USB_HSD3N +3VS OK 1 RC113 @ 2 10K_0402_5% APU_GPIO67 O BA30 SATA_ACT_L/GPIO67 USB_HSD4P USB_HSD4N AY12 USB_HSD5P USB_HSD5N SATA_X2 USB_HSD6P USB_HSD6N <19> CLK_PCIE_GPU CLK_PCIE_GPU# <40> <40> CLK_PCIE_WLAN CLK_PCIE_WLAN# <37> CLK_PCIE_LAN CLK_PCIE_LAN# <19> OK OK C OK <37> CLK_PCIE_GPU CLK_PCIE_GPU# RC116 RC117 1 1 @ @ 2 0_0402_5% CLK_PCIE_GPU_R 2 0_0402_5% CLK_PCIE_GPU#_R CLK_PCIE_WLAN CLK_PCIE_WLAN# RC118 RC119 1 1 @ @ 2 0_0402_5% CLK_PCIE_WLAN_R 2 0_0402_5% CLK_PCIE_WLAN#_R CLK_PCIE_LAN CLK_PCIE_LAN# RC120 RC121 1 1 @ @ 2 0_0402_5% CLK_PCIE_LAN_R 2 0_0402_5% CLK_PCIE_LAN#_R TC32 U4 U5 GFX_CLKP USB_HSD7P GFX_CLKN USB_HSD7N AC8 AC10 GPP_CLK0P USB_HSD8P GPP_CLK0N USB_HSD8N AE4 AE5 GPP_CLK1P USB_HSD9P GPP_CLK1N USB_HSD9N AC4 AC5 GPP_CLK2P AA5 AA4 GPP_CLK3P USB_SS_0TXP GPP_CLK3N USB_SS_0TXN X14M_25M_48M_OSC USB_SS_0RXP X14M_25M_48M_OSC O AP13 @ 1 48M_X1 N2 USB_SS_ZVSS CLK_PCI_EC LPC_CLK1 RC122 RC123 OK<44> OK<44> OK<44> OK<44> OK <44,9> OK <44> 1 1 2 33_0402_5% 2 0_0402_5% Strap Pin PL AY2 Strap Pin PH AW2 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# SERIRQ TC33 TC46 USB20_P5 USB20_N5 AD1 AD2 USB20_P6 USB20_N6 USB20_P0 USB20_N0 OK <45> OK <45> RIGHT USB (2.0) USB20_P3 USB20_N3 OK <45> OK <45> Card Reader P2 USB20_P2 USB20_N2 OK <41> OK <41> LEFT USB (2.0) P3 USB20_P4 USB20_N4 OK <33> OK <33> Touch Screen USB20_P5 USB20_N5 OK <33> OK <33> Camera USB20_P6 USB20_N6 OK <40> OK <40> Blue Tooth USB20_P1 USB20_N1 <41> OK <41> LEFT USB (3.0) X48M_X2 USB_SS_1RXP P2&P3 exchanged as layout request @ 09/12 AC1 AC2 AB1 AB2 USB20_P1 USB20_N1 AA1 AA2 Net name changed to same as AE10 USBSS_CALRN USBSS_CALRP USB30_RX_P1 USB30_RX_N1 R1 R2 1 1 RC130 RC131 2 1K_0402_1% 2 1K_0402_1% USB30_TX_P1 USB30_TX_N1 <41> <41> USB30_RX_P1 USB30_RX_N1 P8 ACLU1 +0.95VALW_USB3 C OK OK LEFT USB (3.0)OK <41> <41> Net name changed to same as ACLU1 W1 W2 LPCCLK0 AU7 AW9 AR4 AR11 SPI_DI/GPIO164 AR7 10 AU11 SPI_HOLD_L/GEVENT9_L SPI_WP_L/GPIO161 AU9 LPCCLK1 SPI_CLK/GPIO162 SPI_CS1_L/GPIO165 TC47 AE1 AE2 X48M_X1 @ AT2 AT1 AR2 AR1 Strap Pin PH AP2 AP1 @ 1 AV29 AP25 @ 1 AV2 @ 1 USB20_P4 USB20_N4 USB30_TX_P1 USB30_TX_N1 USB_SS_1TXN LPCCLK0 LPCCLK1 AF1 AF2 V2 USB_SS_0RXN V1 USB_SS_1RXN OK <44,9> OK <9> USB20_P2 USB20_N2 T2 T1 USB_SS_1TXP N1 USB20_P3 USB20_N3 AG1 AG2 OK 2 11.8K_0402_1% AMD Debug port! AG7 AG8 AE8 USB_SS_ZVDD_095_USB3_DUAL GPP_CLK2N OK 48M_X2 AJ4 AJ5 RC138 1 SATA_X1 If the integrated clock generator is used, these pins are left unconnected. BA12 1 @ TC34 CLK_USB48M SATA_TX0N LAD0 SPI_CS2_L/GPIO166 10 SPI_DO/GPIO163 LAD1 LAD2 LAD3 LFRAME_L SPI_CLK_R SPI_CS0#_R RC135 RC134 1 1 @ @ 2 0_0402_5% 2 0_0402_5% SPI_CLK SPI_CS0# SPI_SI_R SPI_SO_R SPI_HOLD#_R SPI_WP#_R RC136 RC137 RC178 RC179 1 1 1 1 @ @ @ @ 2 2 2 2 SPI_SI SPI_SO SPI_HOLD# SPI_WP# 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% SPI_CLK SPI_CS0# <44> <44> SPI_SI SPI_SO <44> <44> OK LDRQ0_L SERIRQ/GPIO48 LPC_CLKRUN_L LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L FT3 REV 0.53 @ Beema FT3-REV-0P53_BGA769 OK +3VALW_APU +3VS +3V_SPI APU SPI is ALW PWR B RC175 1 RC125 1 @ 2 0_0402_5% @ 2 0_0402_5% B +3V_SPI TB RS 8M ROM +3V_SPI 1 1 1 RC127 RC128 RC129 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% SPI_WP# SPI_HOLD# SPI_CS0# Change to PR??? 48MHz/10pF Crystal @ SPI_CLK RC126 1 @ 2 10_0402_5% CC127 1 2 10P_0402_50V8J For EMI OK 48M_X1 48M_X2 OK +3V_SPI 8MB SPI ROM SA000039A2J 64M W25Q64FVSSIG 1 RC191 1 2 A 1 2 OSC1 NC1 1 SA00005Z100 64M GD25B64BSIGR 2 1M_0402_5% UC5 YC2 NC2 OSC2 SPI_CS0# 1 SPI_SO 2 SPI_WP# 3 4 3 48MHZ_10PF_7V48000017 CC123 12P_0402_50V8-J 1 2 4 CC124 12P_0402_50V8-J CS# DO CC10 .1U_0402_10V6-K 2 VCC HOLD# WP# CLK GND DI 8 7 SPI_HOLD# 6 SPI_CLK 5 SPI_SI A W25Q64FVSSIG_SO8 Issued Date Change to 15pF as vendor suggest Title LC Future Center Secret Data Security Classification SJ10000IO00 TXC: 7V48000017 (48MHz) 2013/08/15 Deciphered Date 2013/08/15 Beema (SATA/USB/LPC/SPI/CLK) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Date: 5 4 3 2 Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 1 Sheet 7 of 60 5 4 3 2 1 Beema (POWER & DECOUPLING) +1.35V APU GND +VSYSMEM J10 2 @ 2 1 1 JUMP_43X118 Need Short +3VS +3VS_APU RC30 1 2 0_0603_5% TB RS CC69 CC71 1 1 +VSYSMEM_APU +VSYSMEM 2 180P_0402_50V8-J +APU_CORE UC1F POWER 1 2 J35 L32 L37 N35 R31 R37 U32 U35 W31 W32 W37 AA31 AA35 AC32 AC37 AE31 AE35 AG32 AG37 AJ35 AL32 AL37 AR35 PAD-OPEN 4x4m Need Short +3VALW_APU @J13 @ J13 1 2 PAD-OPEN 4x4m CC101 +1.8VALW 1 Need Short 2 1U_0402_6.3V6K +1.8VALW_APU @ 2 0_0603_5% 1 VDDIO_MEM_S_1 VDDCR_CPU_1 L21 VDDIO_MEM_S_2 VDDCR_CPU_2 L23 VDDIO_MEM_S_3 VDDCR_CPU_3 L25 VDDIO_MEM_S_4 VDDCR_CPU_4 L27 VDDIO_MEM_S_5 VDDCR_CPU_5 L29 CC117 1 CC126 VDDCR_CPU_8 N27 VDDIO_MEM_S_8 VDDIO_MEM_S_10 VDDCR_CPU_10 R23 VDDIO_MEM_S_11 VDDCR_CPU_11 R27 VDDIO_MEM_S_12 VDDCR_CPU_12 U21 CC97 CC98 CC99 C VDDIO_MEM_S_13 VDDCR_CPU_13 U23 VDDIO_MEM_S_14 VDDCR_CPU_14 U27 VDDIO_MEM_S_15 VDDCR_CPU_15 W21 CC100 VDDIO_MEM_S_16 VDDIO_MEM_S_17 VDDIO_MEM_S_18 VDDIO_MEM_S_19 VDDIO_MEM_S_20 VDDIO_MEM_S_21 VDDIO_MEM_S_22 VDDIO_MEM_S_23 2 180P_0402_50V8-J 1 2 4.7U_0603_6.3V6K 1 2 1U_0402_6.3V6K 2 1U_0402_6.3V6K CC68 1 2 1U_0402_6.3V6K CC74 1 2 1U_0402_6.3V6K CC75 1 2 1U_0402_6.3V6K 1 1 2 1U_0402_6.3V6K 1 2 1U_0402_6.3V6K 1 2 1U_0402_6.3V6K 1 2 1U_0402_6.3V6K 1 2 1U_0402_6.3V6K 1 2 180P_0402_50V8-J AL10 AL11 +1.8VALW_APU +0.95VALW 0.5A +0.95VALW_USB3 @ 1 13/17A 1 2 0_0603_5% TB RS +0.95VS_APU 2 0_0603_5% @ CC103 1 2 10U_0603_6.3V6M CC106 1 2 10U_0603_6.3V6M CC105 1 2 1U_0402_6.3V6K CC107 1 2 1U_0402_6.3V6K CC108 1 CC104 1 0.2A AL13 AM13 +0.95VALW_USB3 1A AR5 AU4 AV7 AW5 +0.95VALW_APU 0.5A 2 1U_0402_6.3V6K AE11 AE13 AJ11 AJ13 2 180P_0402_50V8-J 4.5uA 2 2 0_0402_5% @ CC109 1 2 1U_0402_6.3V6K CC111 1 2 1U_0402_6.3V6K CC112 1 2 1U_0402_6.3V6K CC113 1 2 1U_0402_6.3V6K VDD_33_ALW_1 VDD_33_1 VDD_33_ALW_2 VDD_33_2 VDD_095_1 VDD_095_USB3_DUAL_2 VDD_095_2 VDD_095_USB3_DUAL_3 VDD_095_3 VDD_095_USB3_DUAL_4 VDD_095_4 VDD_095_ALW_1 VDD_095_ALW_2 VDD_095_ALW_3 VDD_095_ALW_4 1 2 180P_0402_50V8-J C91,C89,C90 PLACE ON TOP LAYER 1 CC91 2 1U_0402_6.3V6K 1 CC92 2 1U_0402_6.3V6K +0.95VS_APU 1.5A CC79 +3VS_APU AM15 AM17 0.2A +0.95VS_APU 1 2 1U_0402_6.3V6K CC84 1 2 1U_0402_6.3V6K CC85 1 2 1U_0402_6.3V6K CC86 1 2 1U_0402_6.3V6K CC87 1 2 1U_0402_6.3V6K CC78 1 2 10U_0603_6.3V6M CC83 1 2 10U_0603_6.3V6M 2 0_0402_5% CC88 1 2 1U_0402_6.3V6K CC80 1 2 180P_0402_50V8-J +0.95VS @ J9 1 3A 2 GND VSS_1 VSS_63 VSS_2 VSS_64 VSS_3 VSS_65 VSS_4 VSS_66 VSS_5 VSS_67 VSS_6 VSS_68 VSS_7 VSS_69 VSS_8 VSS_70 VSS_9 VSS_71 VSS_10 VSS_72 VSS_11 VSS_73 VSS_12 VSS_74 VSS_13 VSS_75 VSS_14 VSS_76 VSS_15 VSS_77 VSS_16 VSS_78 VSS_17 VSS_79 VSS_18 VSS_80 VSS_19 VSS_81 VSS_20 VSS_82 VSS_21 VSS_83 VSS_22 VSS_84 VSS_23 VSS_85 VSS_24 VSS_86 VSS_25 VSS_87 VSS_26 VSS_88 VSS_27 VSS_89 VSS_28 VSS_90 VSS_29 VSS_91 VSS_30 VSS_92 VSS_31 VSS_93 VSS_32 VSS_94 VSS_33 VSS_95 VSS_34 VSS_96 VSS_35 VSS_97 VSS_36 VSS_98 VSS_37 VSS_99 VSS_38 VSS_100 VSS_39 VSS_101 VSS_40 VSS_102 VSS_41 VSS_103 VSS_42 VSS_104 VSS_43 VSS_105 VSS_44 VSS_106 VSS_45 VSS_107 VSS_46 VSS_108 VSS_47 VSS_109 VSS_48 VSS_110 VSS_49 VSS_111 VSS_50 VSS_112 VSS_51 VSS_113 VSS_52 VSS_114 VSS_53 VSS_115 VSS_54 VSS_116 VSS_55 VSS_117 VSS_56 VSS_118 VSS_57 VSS_119 VSS_58 VSS_120 VSS_59 VSS_121 VSS_60 VSS_122 VSS_61 VSS_123 VSS_62 VSS_124 J3 J7 J8 J39 K11 K13 K17 K19 K21 K23 K25 K27 K29 K31 L3 L7 L8 L10 L11 L15 L19 L31 L39 L41 M1 M2 N3 N7 N15 N19 N25 N29 N31 N39 P1 P2 R3 R7 R15 R19 R25 R29 R39 R41 U1 U2 U3 U7 U8 U11 U15 U19 U25 U29 U31 U39 W3 W5 W11 W15 W19 W25 W29 W39 W41 Y1 Y2 AA3 AA7 AA8 AA11 AA15 AA19 AA25 AA29 AA39 AC3 AC7 AC11 AC15 AC19 AC25 AC29 AC31 AC39 AC41 AE3 AE7 AE25 AE29 AE32 AE39 AG3 AG5 AG10 AG11 AG13 AG15 AG19 AG25 AG29 AG31 AG39 AG41 AH1 AH2 AJ3 AJ7 AJ15 AJ17 AJ19 AJ23 AJ25 AJ29 AJ31 AJ32 AJ39 AL3 AL8 AL15 AL17 AL19 AL25 AL29 VSS_125 VSS_187 VSS_126 VSS_188 VSS_127 VSS_189 VSS_128 VSS_190 VSS_129 VSS_191 VSS_130 VSS_192 VSS_131 VSS_193 VSS_132 VSS_194 VSS_133 VSS_195 VSS_134 VSS_196 VSS_135 VSS_197 VSS_136 VSS_198 VSS_137 VSS_199 VSS_138 VSS_200 VSS_139 VSS_201 VSS_140 VSS_202 VSS_141 VSS_203 VSS_142 VSS_204 VSS_143 VSS_205 VSS_144 VSS_206 VSS_145 VSS_207 VSS_146 VSS_208 VSS_147 VSS_209 VSS_148 VSS_210 VSS_149 VSS_211 VSS_150 VSS_212 VSS_151 VSS_213 VSS_152 VSS_214 VSS_153 VSS_215 VSS_154 VSS_216 VSS_155 VSS_217 VSS_156 VSS_218 VSS_157 VSS_219 VSS_158 VSS_220 VSS_159 VSS_221 VSS_160 VSS_222 VSS_161 VSS_223 VSS_162 VSS_224 VSS_163 VSS_225 VSS_164 VSS_226 VSS_165 VSS_227 VSS_166 VSS_228 VSS_167 VSS_229 VSS_168 VSS_230 VSS_169 VSS_231 VSS_170 VSS_232 VSS_171 VSS_233 VSS_172 VSS_234 VSS_173 VSS_235 VSS_174 VSS_236 VSS_175 VSS_237 VSS_176 VSS_238 VSS_177 VSS_239 VSS_178 VSS_240 VSS_179 VSS_241 VSS_180 VSS_242 VSS_181 VSSBG_DAC VSS_182 VSS_243 VSS_183 VSS_244 AL39 AL41 AM11 AM27 AM31 AN3 AN7 AN39 AP31 AR3 AR13 AR17 AR21 AR25 AR29 AR39 AR41 AU1 AU2 AU3 AU15 AU19 AU23 AU27 AU39 AV9 AW3 AW7 AW13 AW15 AW17 AW19 AW21 AW23 AW25 AW27 AW31 AW33 AW35 AW37 AW39 AW41 AY13 AY15 AY18 AY30 BA2 BA7 BA13 BA15 BA18 BA21 BA25 BA31 BA35 BA39 A15 AL31 AM29 D C VSS_184 VSS_185 VSS_186 FT3 REV 0.53 @ PAD-OPEN 4x4m FT3 REV 0.53 @ FT3-REV-0P53_BGA769 Beema FT3-REV-0P53_BGA769 Beema Need Short +0.95VS_GFX_APU +0.95VS_APU 0.6A 1 RC145 @ TB RS FT3 REV 0.53 Beema UC4 GND 2 10K_0402_5% CC82 1 2 1U_0402_6.3V6K CC81 1 2 10U_0603_6.3V6M FT3-REV-0P53_BGA769 CC110 0.22U_0402_10V6K RC1461 2 1U_0402_6.3V6K A8 A13 A23 A31 A35 A39 B8 B13 B23 B31 B39 C1 C2 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 C39 C41 D9 D11 D13 E3 E4 E9 E11 E13 E27 E31 E35 E38 E39 G3 G7 G11 G13 G15 G17 G21 G25 G29 G35 G37 G39 G41 H11 H13 H23 H31 VDD_095_GFX_3 AA10 VDDBT_RTC_G @ 2 0_0402_5% 2 4.7U_0603_6.3V6K 1 CC90 VDD_095_GFX_2 W10 AN4 TB @ RS 1 CC89 A2 A3 B3 C3 AG23 AG27 AJ21 AJ27 VDD_095_5 AL21 VDD_095_6 AL23 VDD_095_7 AL27 VDD_095_8 AM23 VDD_095_9 AM25 VDD_095_USB3_DUAL_1 +1.5VS 1 CC125 VDD_095_GFX_1 U10 1 +0.95VALW_APU TB RS VDD_18_2 VDD_18_4 +RTCBATT_APU B VDD_18_ALW_2 VDD_18_3 @ +0.95VALW VDD_18_1 2 180P_0402_50V8-J Wake-on-Ring supported: Connect to +1.5V S5 rail Wake-on-Ring not supported: Connect to +1.5V S0 rail +1.8VS_APU VDD_18_ALW_1 2 1U_0402_6.3V6K +APU_CORE_NB VDDIO_AZ_ALW_2 +3VALW_APU @ RC1421 B1 B2 VDDIO_AZ_ALW_1 2 1U_0402_6.3V6K +VDDIO_AZ_APU VDDCR_NB_4 N13 VDDCR_NB_5 N17 VDDCR_NB_6 R11 VDDCR_NB_7 R13 VDDCR_NB_8 R17 VDDCR_NB_9 U13 VDDCR_NB_10 U17 VDDCR_NB_11 W13 VDDCR_NB_12 W17 VDDCR_NB_13 AA13 VDDCR_NB_14 AA17 VDDCR_NB_15 AC13 VDDCR_NB_16 AC17 VDDCR_NB_17 AE15 VDDCR_NB_18 AE17 VDDCR_NB_19 AE19 VDDCR_NB_20 AG17 VDDCR_NB_21 AG21 +VDDIO_AZ_APU 1 2 1U_0402_6.3V6K 1 CC70 VDDCR_NB_1 L13 0.1A RC144 1 CC73 CC77 VDDCR_CPU_16 W23 VDDCR_CPU_17 W27 VDDCR_CPU_18 AA21 VDDCR_CPU_19 AA23 VDDCR_CPU_20 AA27 VDDCR_CPU_21 AC21 VDDCR_CPU_22 AC23 VDDCR_CPU_23 AC27 VDDCR_CPU_24 AE21 VDDCR_CPU_25 AE23 VDDCR_CPU_26 AE27 @ 1 CC67 CC76 VDDCR_NB_3 N11 CC96 RC143 2 10U_0603_6.3V6M VDDCR_CPU_9 R21 VDDIO_MEM_S_9 VDDCR_NB_2 L17 CC95 S0 DOMAIN 1 RC139 CC94 S5 DOMAIN CC66 VDDCR_CPU_7 N23 VDDIO_MEM_S_7 TB RS CC93 180P_0402_50V8-J A23 For STAMP APU_TEMPRETURN 20/25A VDDCR_CPU_6 N21 VDDIO_MEM_S_6 @ RC1401 2 2 1U_0402_6.3V6K 1 2 0_0603_5% 2 0_0603_5% TB RS 2.9A CC102 UC1H GND TB @ RS RC1321 RC1331 2 1U_0402_6.3V6K 1 UC1G +1.8VS @ 2 1U_0402_6.3V6K @J8 @ J8 CC72 D +1.8VS_APU All RLC follow CRB, need dobulc check with DG. 200mA @ 3 2 B +VCCRTC Vout Vin 1 RC148 1 2 10K_0402_5% 1 1 AP2138N-1.5TRG1_SOT23-3 2 JCOMS1 @ SHORT PADS 2 SA000063Q00 BCD: AP2138N-1.5TRG1 SA000063O00 ANPEC: APL510215AITRG CC114 1U_0402_6.3V6K A 1 CC26 2 1 2 CC27 1 2 CC28 1 2 @ CC139 1 2 CC130 1 2 CC131 1 2 CC132 1 2 CC133 1U_0402_6.3V6K 2 CC25 1U_0402_6.3V6K 1 1U_0402_6.3V6K 2 CC24 1U_0402_6.3V6K 1 22U_0805_6.3V6M 2 CC23 180P_0402_50V8-J 2 1 180P_0402_50V8-J 2 +VSYSMEM_APU CC64 1 180P_0402_50V8-J 2 CC63 1 10U_0603_6.3V6M 2 CC62 1 10U_0603_6.3V6M 2 CC61 1 10U_0603_6.3V6M 2 CC60 1 1U_0402_6.3V6K 2 CC59 1 1U_0402_6.3V6K 2 CC58 1 1U_0402_6.3V6K 2 CC57 1 1U_0402_6.3V6K 2 CC65 1 1U_0402_6.3V6K CC56 1 1U_0402_6.3V6K 2 CC120 1U_0402_6.3V6K 1 1U_0402_6.3V6K 2 CC55 1U_0402_6.3V6K 1 180P_0402_50V8-J 2 CC54 10U_0603_6.3V6M 1 10U_0603_6.3V6M CC53 10U_0603_6.3V6M 10U_0603_6.3V6M +APU_CORE_NB 1 2 A +VSYSMEM +APU_CORE 2 CC45 1 2 CC46 1 2 CC47 1 2 CC48 1 2 CC49 1 2 CC50 CC51 1 2 1 2 CC52 1U_0402_6.3V6K 1 1U_0402_6.3V6K 2 CC44 1U_0402_6.3V6K 1 1U_0402_6.3V6K 2 CC43 1U_0402_6.3V6K 1 1U_0402_6.3V6K 2 CC42 1U_0402_6.3V6K 1 1U_0402_6.3V6K 2 CC41 1U_0402_6.3V6K 1 1U_0402_6.3V6K 2 CC40 1U_0402_6.3V6K 1 180P_0402_50V8-J 2 CC39 10U_0603_6.3V6M 1 10U_0603_6.3V6M 10U_0603_6.3V6M CC38 1 1 2 2 CC145 22U_0805_6.3V6M @ 1 2 CC146 22U_0805_6.3V6M @ Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Beema (POWER & DECOUPLING) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 8 of 60 5 4 3 2 1 Beema (STRAPS & OTHERS) RC176 10K_0402_5% D RC181 10K_0402_5% @ 2 RC154 10K_0402_5% @ 1 +3VALW_APU 1 +3VALW_APU 2 RC153 10K_0402_5% @ 2 RC152 10K_0402_5% @ 1 +3VALW_APU 1 1 RC151 10K_0402_5% +3VALW_APU 2 RC150 10K_0402_5% +3VALW_APU 2 S0 PWR, PH +3VS??? Or need isloate~~ 2 EC 2 D +3VALW_APU 1 1 +3VALW_APU RC154,RC176,RC181 change to @ due to internal PH LPC_FRAME# GEVENT2# <6> SYS_RESET# I BLINK RC155 2K_0402_5% @ I SPI ROM Internal CLK Gen Default Default LPC ROM Exteranl CLK Gen PULL HIGH C PULL LOW Boot Fail Timer Enabled 1.8V SPI Boot Fail Timer Disabled 3.3V SPI Default Default Normal Power Up Coin Battery &Reset Timing LDT_RST#/ LDT_PWRGD output to APU Default Default Default Reserved Direct DC Reserved RC156 2K_0402_5% @ RC157 2K_0402_5% RC158 2K_0402_5% RC159 2K_0402_5% @ 1 RTCCLK RC177 2K_0402_5% @ RC180 2K_0402_5% @ 2 I 1 SYS_RESET_L II 1 GEVENT2_L 2 II 2 LPCCLK0 II 1 LPCCLK1 2 II 1 LFRAME_L BLINK 2 Type SUSCLK 2 <6> 1 Signal CLK_PCI_EC <6> <40,6> STRAP PINS LPC_CLK1 2 <7> <44,7> 1 <44,7> C Type I straps become valid immediately after capture with the rising edge of RSMRST_L. Type II straps become valid after PWR_GOOD is asserted All Strap pins must be configured with either external pull-up or pull-down resistors. B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Beema (STRAPS & OTHERS) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 9 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Blank THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Date: 5 4 3 2 Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 1 Sheet 10 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Blank THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Date: 5 4 3 2 Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 1 Sheet 11 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Blank THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Date: 5 4 3 2 Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 1 Sheet 12 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Blank THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Date: 5 4 3 2 Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 1 Sheet 13 of 60 4 3 2 DDRA_DQ[0..63] DDR3 SO-DIMM A DDRA_DQS[0..7] DDRA_DQS#[0..7] DDRA_DQ24 DDRA_DQ25 DDRA_DM3 C +VSYSMEM DDRA_DQ26 DDRA_DQ27 B DDRA_DQ32 DDRA_DQ33 DDRA_DQS#4 DDRA_DQS4 DDRA_DQ34 DDRA_DQ35 DDRA_DQ40 DDRA_DQ41 DDRA_DM5 DDRA_DQ42 DDRA_DQ43 DDRA_DM7 DDRA_DQ58 DDRA_DQ59 A +3VS CD28 2.2U_0402_6.3V6M 1 1 2 2 CD29 .1U_0402_10V6-K 205 207 GND1 BOSS1 GND2 BOSS2 206 208 1 CD17 @ 1 2 1 2 CD18 1 2 CD19 @ 1 2 CD20 1 2 CD22 @ 1 2 CD21 1 2 CD23 @ 1 2 CD58 1 2 CD59 1 2 CD60 1 @ 2 CD61 1 2 DDRA_MA2 DDRA_MA0 DDRA_CLK1 DDRA_CLK1# DDRA_CLK1 DDRA_CLK1# <4> <4> DDRA_BS1# DDRA_RAS# <15,4> <15,4> DDRA_CS0# DDRA_ODT0 <4> <4> DDRA_ODT1 +VREF_CA <4> DDRA_BS1# DDRA_RAS# DDRA_CS0# DDRA_ODT0 DDRA_ODT1 +VSYSMEM EMI CD62 1 2 CD63 1 2 CD66 1 2 CD67 @ 1 2 @ 1 2 @ 1 2 @ 1 2 RF 1 2 CD11 33P_0402_50V8J @ B DDRA_DQ36 DDRA_DQ37 DDRA_DM4 DDRA_DQ38 DDRA_DQ39 DDRA_DQ44 DDRA_DQ45 Layout Note: Place near DIMM +0.675VS DDRA_DQS#5 DDRA_DQS5 DDRA_DQ46 DDRA_DQ47 DDRA_DQ52 DDRA_DQ53 CD24 DDRA_DM6 1 2 DDRA_DQ54 DDRA_DQ55 CD25 @ 1 2 CD26 1 2 CD27 @ 1 2 DDRA_DQ60 DDRA_DQ61 DDRA_DQS#7 DDRA_DQS7 DDRA_DQ62 DDRA_DQ63 A MEM_MA_EVENT# SMB_DATA_S3 SMB_CLK_S3 MEM_MA_EVENT# <15,4> SMB_DATA_S3 <15,40,6> SMB_CLK_S3 <15,40,6> +0.675VS 1 0.65A@0.75V CD70 33P_0402_50V8J @ For RF 4 1 2 DDRA_MA6 DDRA_MA4 2 LCN_DAN06-K4406-0103 ME@ 5 CD16 DDRA_MA11 DDRA_MA7 4.7U_0603_6.3V6K DDRA_DQ56 DDRA_DQ57 <4> 1U_0402_6.3V6K DDRA_DQ50 DDRA_DQ51 DDRA_CKE1 DDRA_MA15 DDRA_MA14 Layout Note: Place near DIMM1 1U_0402_6.3V6K DDRA_DQS#6 DDRA_DQS6 +VSYSMEM DDRA_CKE1 C 3A@1.5V +VSYSMEM 1U_0402_6.3V6K DDRA_DQ48 DDRA_DQ49 DDRA_DQ30 DDRA_DQ31 .1U_0402_10V6-K DDRA_MA13 DDRA_CS1# DDRA_DQS#3 DDRA_DQS3 .1U_0402_10V6-K DDRA_CS1# DDRA_DQ28 DDRA_DQ29 .1U_0402_10V6-K <4> 2 .1U_0402_10V6-K DDRA_WE# DDRA_CAS# 2 1 CD7 0.047U_0402_16V7K DDRA_WE# DDRA_CAS# 2 1 .1U_0402_10V6-K <15,4> <15,4> 2 DDRA_DQ22 DDRA_DQ23 RD25 1K_0402_1% CD6 0.047U_0402_16V7K DDRA_MA10 DDRA_BS0# DDRA_DM2 1 CD5 0.047U_0402_16V7K DDRA_BS0# 1 10U_0805_10V6K <15,4> <4> <4> RD11 1K_0402_1% DDRA_DQ20 DDRA_DQ21 10U_0805_10V6K DDRA_CLK0 DDRA_CLK0# DDRA_CLK0 DDRA_CLK0# 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 DDRA_DQ14 DDRA_DQ15 +VREF_CA 15mil .1U_0402_10V6-K DDRA_MA3 DDRA_MA1 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS5# DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS7# DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 15mil .1U_0402_10V6-K DDRA_MA8 DDRA_MA5 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 TEST VSS27 DQ32 DQ33 VSS29 DQS4# DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS6# DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 <15,4> .1U_0402_10V6-K DDRA_MA12 DDRA_MA9 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 MEM_MA_RST# RD12 1K_0402_1% +VREF_DQ .1U_0402_10V6-K DDRA_BS2# RD10 1K_0402_1% DDRA_DM1 MEM_MA_RST# .1U_0402_10V6-K DDRA_CKE0 DDRA_BS2# +VSYSMEM .1U_0402_10V6-K DDRA_CKE0 DDRA_DQ12 DDRA_DQ13 .1U_0402_10V6-K <4> <15,4> +VSYSMEM DDRA_DQ6 DDRA_DQ7 CD119 1000P_0402_50V7K DDRA_DQ18 DDRA_DQ19 D DDRA_DQS#0 DDRA_DQS0 CD118 .1U_0402_10V6-K DDRA_DQS#2 DDRA_DQS2 <15,4> 2 DDRA_DQ16 DDRA_DQ17 DDRA_DM[0..7] 22U_0603_6.3V6-M DDRA_DQ10 DDRA_DQ11 DDRA_DM[0..7] DDRA_DQ4 DDRA_DQ5 CD117 1000P_0402_50V7K DDRA_DQS#1 DDRA_DQS1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 CD116 .1U_0402_10V6-K DDRA_DQ8 DDRA_DQ9 VSS1 DQ4 DQ5 VSS3 DQS0# DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS3# DQS3 VSS24 DQ30 DQ31 VSS26 <15,4> <15,4> 1 DDRA_DQ2 DDRA_DQ3 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS1# DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS2# DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 2 DDRA_DM0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 1 DDRA_DQ0 DDRA_DQ1 <15,4> DDRA_MA[0..15] JDDR1 2 D <15,4> DDRA_DQS[0..7] DDRA_DQS#[0..7] DDRA_MA[0..15] +VREF_DQ 1 DDRA_DQ[0..63] 22U_0805_6.3V6M 5 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 2013/08/15 Deciphered Date DDRIII SO-DIMM A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 3 2 1 Sheet 14 of 60 5 4 3 2 DDR3 SO-DIMM B DDRA_DQ[0..63] DDRA_DQS[0..7] DDRA_DQS#[0..7] +VREF_DQ DDRA_DQ0 DDRA_DQ1 D DDRA_DM0 DDRA_DQ2 DDRA_DQ3 DDRA_DQ8 DDRA_DQ9 DDRA_DQS#1 DDRA_DQS1 DDRA_DQ10 DDRA_DQ11 DDRA_DQ16 DDRA_DQ17 DDRA_DQ26 DDRA_DQ27 C +VSYSMEM <4> DDRA_CKE2 DDRA_CKE2 <14,4> DDRA_BS2# DDRA_BS2# DDRA_MA12 DDRA_MA9 DDRA_MA8 DDRA_MA5 DDRA_DQS#4 DDRA_DQS4 DDRA_DQ34 DDRA_DQ35 DDRA_DQ40 DDRA_DQ41 DDRA_DM5 DDRA_DQ56 DDRA_DQ57 DDRA_DM7 DDRA_DQ58 DDRA_DQ59 A RD22 1 +3VS 1 CD54 2.2U_0402_6.3V6M 1 2 2 2 10K_0402_5% 205 CD48 .1U_0402_10V6-K G1 G2 206 LCN_DAN06-K4406-0102 ME@ DDRA_DQ22 DDRA_DQ23 CD44 DDRA_DQ28 DDRA_DQ29 2 DDRA_DQS#3 DDRA_DQS3 1 2 CD45 1 2 CD36 1 2 C +VSYSMEM DDRA_CKE3 DDRA_CKE3 <4> DDRA_MA15 DDRA_MA14 3A@1.35V +VSYSMEM DDRA_MA11 DDRA_MA7 EMI DDRA_MA6 DDRA_MA4 DDRA_MA2 DDRA_MA0 CD43 DDRA_CLK3 DDRA_CLK3# DDRA_CLK3 DDRA_CLK3# <4> <4> DDRA_BS1# DDRA_RAS# <14,4> <14,4> DDRA_CS2# DDRA_ODT2 <4> <4> DDRA_ODT3 +VREF_CA <4> DDRA_BS1# DDRA_RAS# DDRA_CS2# DDRA_ODT2 DDRA_ODT3 1 2 CD42 1 2 CD64 1 2 CD65 1 2 CD68 1 2 CD69 1 2 CD30@ 1 + 2 CD72 1 2 CD73 1 2 @ 1 2 B DDRA_DQ36 DDRA_DQ37 DDRA_DM4 DDRA_DQ38 DDRA_DQ39 Layout Note: Place near DIMM +0.675VS DDRA_DQ44 DDRA_DQ45 DDRA_DQS#5 DDRA_DQS5 DDRA_DQ46 DDRA_DQ47 CD32 DDRA_DQ52 DDRA_DQ53 1 2 CD31 @ 1 2 CD33 1 2 CD34 @ 1 2 DDRA_DM6 DDRA_DQ54 DDRA_DQ55 DDRA_DQ60 DDRA_DQ61 DDRA_DQS#7 DDRA_DQS7 DDRA_DQ62 DDRA_DQ63 A MEM_MA_EVENT# SMB_DATA_S3 SMB_CLK_S3 MEM_MA_EVENT# <14,4> SMB_DATA_S3 <14,40,6> SMB_CLK_S3 <14,40,6> +0.675VS 0.65A@0.75V 1 2 4 CD35 DDRA_DQ30 DDRA_DQ31 CD71 33P_0402_50V8J @ For RF 5 1 4.7U_0603_6.3V6K DDRA_DQ50 DDRA_DQ51 DDRA_DM2 1U_0402_6.3V6K DDRA_DQS#6 DDRA_DQS6 +VREF_CA 1U_0402_6.3V6K DDRA_DQ48 DDRA_DQ49 15mil +VREF_DQ 1U_0402_6.3V6K DDRA_DQ42 DDRA_DQ43 +VREF_CA 15mil CD10 0.047U_0402_16V7K DDRA_DQ32 DDRA_DQ33 +VREF_DQ DDRA_DQ20 DDRA_DQ21 10U_0805_10V6K B <14,4> 10U_0805_10V6K <4> MEM_MA_RST# DDRA_DQ14 DDRA_DQ15 330U_D2_2VM_R9M DDRA_CS3# DDRA_MA13 DDRA_CS3# DDRA_DM1 MEM_MA_RST# .1U_0402_10V6-K DDRA_WE# DDRA_CAS# DDRA_DQ12 DDRA_DQ13 .1U_0402_10V6-K DDRA_WE# DDRA_CAS# DDRA_DQ6 DDRA_DQ7 .1U_0402_10V6-K DDRA_BS0# <14,4> <14,4> 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 <14,4> D .1U_0402_10V6-K <14,4> DDRA_MA10 DDRA_BS0# <4> <4> CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 DDRA_DM[0..7] .1U_0402_10V6-K DDRA_CLK2 DDRA_CLK2# DDRA_CLK2 DDRA_CLK2# CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 <14,4> DDRA_DQS#0 DDRA_DQS0 .1U_0402_10V6-K DDRA_MA3 DDRA_MA1 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDRA_DM[0..7] DDRA_DQ4 DDRA_DQ5 <14,4> DDRA_MA[0..15] 1000P_0402_50V7K DDRA_DM3 <14,4> .1U_0402_10V6-K DDRA_DQ24 DDRA_DQ25 <14,4> DDRA_DQS[0..7] 1000P_0402_50V7K DDRA_DQ18 DDRA_DQ19 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 .1U_0402_10V6-K DDRA_DQS#2 DDRA_DQS2 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDRA_DQ[0..63] DDRA_DQS#[0..7] DDRA_MA[0..15] JDDR2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 1 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 2013/08/15 Deciphered Date DDRIII SO-DIMM B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 3 2 1 Sheet 15 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 2013/08/15 Deciphered Date Blank THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 16 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 2013/08/15 Deciphered Date Blank THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 17 of 60 5 4 3 2 1 VGA Note list need to be update! D D Power-Up/Down Sequence Without BACO option : "Mars" has the following requirements with regards to power-supply sequencing to avoid damaging the ASIC: PE_GPIO0 : Low ‐> Reset dGPU ; High ‐>Normal operation PE_GPIO1 : Low ‐> dGPU Power OFF ; High ‐> dGPU Power ON dGPU Power Pins ‧All the ASIC supplies must reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. The maximum slew rate on all rails is 50 mV/米s. The external pull ups on the DDC/AUX signals (if applicable) should ramp up before or after both VDDC and VDD_CT have ramped up. VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC should reach 90% before VDD_CT starts to ramp up (or vice versa). For power down, reversing the ramp-up sequence is recommended. C Voltage Max current VDD_CT, DP_VDDR, SPLL_PVDD, MPLL_PVDD, PCIE_PVDD, TSVDD, VDDR4, AVDD, VDD1DI 1.8V 1243mA DP_VDDC, SPLL_VDDC, PCIE_VDDC, BIF_VDDC 0.95V 4560mA VDDR3 3.3V 25mA VDDR1 1.5V 1.5A VDDC 0.8~1.125V TBD VDDCI 0.8~1.1V 8.8A C 0 ~ 20ms VDDR3(+3VGS) PX5.5 0ms min. VDDC(+VGA_CORE) FCH PE_GPIO0 (PXS_RST#) dGPU VDDCI(+VGA_CORE) +0.95VGS BIF_VDDC PE_GPIO1 (PXS_PWREN) PCIE_VDDC(+0.95VGS) +3VS VDDR1(+1.5VGS) MOS 100ms min. +5VALW VDD_CT(+1.8VGS) Regulator 1 2 +3VGS Short PX_MODE and PX_PWREN +0.95VGS +1.5VS B MOS 3 Regulator 4 PERSTb(GPU_RST#) default 1ms +3VS 6 100us min. B +1.8VGS LDO REFCLK(CLK_PCIE_VGA) +1.5VGS B+ +VGA_CORE Straps Reset Name Pin Assignment Straps Valid PE_GPIO0 GPIO191 Global ASIC Reset PE_GPIO1 GPIO192 A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 Deciphered Date 2013/08/05 VGA Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 18 of 60 5 OK<4> PCIE_CTX_C_GRX_P[3..0] OK<4> PCIE_CTX_C_GRX_N[3..0] 4 3 PCIE_CTX_C_GRX_P[3..0] 2 PCIE_CRX_GTX_P[3..0] UV1A PCIE_CTX_C_GRX_N[3..0] D PCIE_CRX_GTX_N[3..0] PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 AF30 AE31 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 AE29 AD28 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 AD30 AC31 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3 AC29 AB28 AB30 AA31 AA29 Y28 Y30 W31 W29 V28 V30 U31 C U29 T28 R29 P28 P30 N31 N29 M28 M30 L31 L29 K30 B OK<7> OK<7> CLK_PCIE_GPU CLK_PCIE_GPU# AK30 AK32 CLK_PCIE_GPU CLK_PCIE_GPU# PCIE_TX0P PCIE_TX0N PCIE_RX1P PCIE_RX1N PCIE_TX1P PCIE_TX1N PCIE_RX2P PCIE_RX2N PCIE_TX2P PCIE_TX2N PCIE_RX3P PCIE_RX3N PCIE_TX3P PCIE_TX3N PCIE_RX4P PCIE_RX4N PCIE_TX4P PCIE_TX4N PCIE_RX5P PCIE_RX5N PCIE_TX5P PCIE_TX5N PCIE_RX6P PCIE_RX6N PCIE_TX6P PCIE_TX6N PCIE_RX7P PCIE_RX7N PCIE_TX7P PCIE_TX7N NC#V30 NC#U31 NC#W24 NC#W23 NC#U29 NC#T28 NC#T30 NC#R31 NC#R29 NC#P28 NC#V27 NC#U26 PCI EXPRESS INTERFACE T30 R31 PCIE_RX0P PCIE_RX0N NC#U24 NC#U23 NC#T26 NC#T27 NC#P30 NC#N31 NC#T24 NC#T23 NC#N29 NC#M28 NC#P27 NC#P26 NC#M30 NC#L31 NC#P24 NC#P23 NC#L29 NC#K30 NC#M27 NC#N26 1 PCIE_CRX_GTX_P[3..0] <4>OK PCIE_CRX_GTX_N[3..0] <4>OK AH30 AG31 PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0 .1U_0402_10V6-K 1 .1U_0402_10V6-K 1 2 PX@ 2 PX@ CV1 CV2 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 AG29 AF28 PCIE_CRX_C_GTX_P1 PCIE_CRX_C_GTX_N1 .1U_0402_10V6-K 1 .1U_0402_10V6-K 1 2 PX@ 2 PX@ CV3 CV4 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 AF27 AF26 PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2 .1U_0402_10V6-K 1 .1U_0402_10V6-K 1 2 PX@ 2 PX@ CV5 CV6 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 AD27 AD26 PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3 .1U_0402_10V6-K 1 .1U_0402_10V6-K 1 2 PX@ 2 PX@ CV7 CV8 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 D AC25 AB25 Y23 Y24 AB27 AB26 VRAM 1G Y27 Y26 ZZZ M2G@ ZZZ S2G@ ZZZ H2G@ W24 W23 C MICRON 2G V27 U26 SAMSUNG 2G X7603112002 U24 U23 HYNIX 2G X7603112001 X7603112003 VRAM 2G T26 T27 ZZZ M1G@ ZZZ S1G@ ZZZ H1G@ T24 T23 MICRON 1G P27 P26 SAMSUNG 1G X7603112005 HYNIX 1G X7603112004 X7603112006 P24 P23 M27 N26 B CLOCK PCIE_REFCLKP PCIE_REFCLKN +0.95VGS CALIBRATION PCIE_CALR_TX 1K_0402_1% 1 PX@ OK<20> N10 AL27 GPU_RST# 1 GPU_RST# 2 RV4 1 RV7 @ PCIE_CALR_RX RV3 1 PX@ 2 1.69K_0402_1% AA22 RV5 1 PX@ 2 1K_0402_1% PERSTB JET-S3-LE_FCBGA631 PX@ 2 RV6 100K_0402_5% PX@ TEST_PG Y22 2 0_0402_5% OK DV3 GPU_RST# 2 VR_VGA_PWRGD 3 5 OK <58,6> OK <37,40,6> PLT_RST# 1 2 IN1 IN2 GND PXS_RST# 3 OK<6> VR_VGA_PWRGD UV2 VCC A PX@ 1 +3VGS OUT 4 VGA_PWROK VGA_PWROK BAT54AWT1G_SOT323-3 A GPU_RST# Title LC Future Center Secret Data Security Classification MC74VHC1G08DFT2G_SC70-5 PX@ Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_PCIE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D A3 DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Date: 5 OK <44,58,6> 4 3 2 Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 Sheet 1 19 of 60 5 4 3 2 1 RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE CONFIGURATION STRAPS UV1B +1.8VGS 1 2 NC#AK5 NC#AM3 NC#AK6 NC#AM5 DPB NC#AJ7 NC#AH6 NC#AK8 NC#AL7 RVP2 PX@ CV31 PX@ OK 1 2 3 4 GPU_SVD GPU_SVC GPU_VID3 GPU_VID4 8 7 6 5 GPU_SVD_R GPU_SVC_R GPU_VID3_R GPU_VID4_R W6 V6 AC6 AC5 33_0804_8P4R_5% T PN change Idea pad PN SD300003700 AA5 AA6 +3VGS NC#W6 NC#V6 NC#V4 NC#U5 NC#AC6 NC#AC5 NC#AA5 NC#AA6 NC#W3 NC#V2 DPC NC#Y4 NC#W5 10K_0402_5% 1 2 RV8 @ TV11 @ 1 PAD 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 1 1 1 1 2 RV9 2 RV12 2 RV13 2 RV14 @ @ @ @ U1 W1 U3 Y6 AA1 GPU_GPIO5 VGA_VDDCI_SEN TV12 @ 1 PAD GPU_GPIO0 GPU_GPIO8 GPU_GPIO9 GPU_GPIO10 PLL_ANALOG_IN NC#U1 NC#W1 NC#U3 NC#Y6 NC#AA1 NC#AA3 NC#Y2 NC#J8 ROM_CONFIG[0] ROM_CONFIG[1] ROM_CONFIG[2] X AH3 AH1 100 = 256MB PS_0[4] N/A AK3 AK1 Reserved for internal use only. Must be 1 at reset. AUD_PORT_CONN_ PINSTRAP[0] The LSB (least significant bit) of the strap option that indicates the number of audio-capable display outputs. X PS_1[1] STRAP_BIF_GEN3_EN_A 1 = PCIe GEN3 is supported. 0 = PCIe GEN3 is not supported. X PS_1[2] STRAP_BIF_CLK_PM_EN 0 = The CLKREQB power management capability is disabled 1 = The CLKREQB power management capability is enabled 0 Reserved for internal use only. Must be 0 at reset. 0 PS_1[4] STRAP_TX_CFG_DRV_ FULL_SWING 0 = The transmitter half-swing is enabled 1 = The transmitter full-swing is enabled 1 PS_1[5] STRAP_TX_DEEMPH_EN 0 = Tx deemphasis disabled. 1 = Tx deemphasis enabled. AK6 AM5 AJ7 AH6 N/A PS_1[3] AK8 AL7 V4 U5 W3 V2 VGA_VSSI_SEN 1 PS_2[1] N/A Reserved. PS_2[2] N/A Reserved. PS_2[3] STRAP_BIOS_ROM_EN Y4 W5 PS_2[4] AA3 Y2 STRAP_BIF_VGA_DIS PS_2[5] N/A J8 PS_3[1] PS_3[2] PS_3[3] <44> VGA_AC_BATT OK <58> GPU_VR_HOT# OK <58> C RV104 1 GPU_SVD GPU_SVD 2 0_0402_5% GPU_GPIO8 GPU_GPIO9 GPU_GPIO10 @ 1 1 @ @ 10K_0402_5% 0_0402_5% 1 1 PX@ 2 RV68 2 RV105 @ 0_0402_5% 1 PX@ 2 RV124 0_0402_5% 2 RV103 2 RV67 10K_0402_5% OK <58> GPU_SVC GPU_SVC OK<6> VGA_SMB_DATA VGA_SMB_CLK GPU_GPIO5 GPU_VID5 RB751V-40_SOD323-2 2 DV1 1 GPU_CLKREQ# GPU_VID3 GPU_GPIO16 GPIO_19_CTF GPU_VID4 GPU_GPIO21 GPU_GPIO22 GPU_VID2 GPU_VID1 GPU_CLKREQ#_R 10K_0402_5% 10K_0402_5% 10K_0402_5% 1 1 1 @ @ @ 2 RV72 2 RV75 2 RV78 JTAG_TRSTB JTAG_TDI JTAG_TMS 10K_0402_5% 1 @ 2 RV40 JTAG_TCK L6 L5 L3 L1 K4 K7 AF24 JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS 1JTAG_TDO TESTEN +3VGS PAD TV7 @ RV64 1 PX@ 2 1K_0402_5% AB13 W8 W9 W7 AD10 AJ9 AL9 PAD 1 TV6 @ AC14 AB16 PX_EN 4.7K_0402_5% 1 PX@ 2 1 AC16 NC_RSET NC_AVDD NC_AVSSQ NC_VDD1DI NC_VSS1DI FutureASIC/SEYMOUR/PARK CEC_1 NC_SVI2#AK12 NC_SVI2#AL11 NC_SVI2#AJ11 NC_GENLK_CLK NC_GENLK_VSYNC NC_SWAPLOCKA NC_SWAPLOCKB NC_GENERICA NC_GENERICB NC_GENERICC NC_GENERICD NC_GENERICE_HPD4 NC#AJ9 DBG_CNTL0 PS_0 PS_1 PS_2 NC_HPD1 PX_EN PS_3 1 1 2 CV32 NC_DDC1CLK NC_DDC1DATA NC_AUX1P NC_AUX1N RV46 1M_0402_5% PX@ NC_DDC2CLK NC_DDC2DATA 1 1 PX@ 2 RV45 PX@ 2 RV50 XTALIN XTALOUT AM28 AK28 XO_IN XO_IN2 AC22 AB22 XTALIN XTALOUT NC_AUX2P NC_AUX2N XO_IN XO_IN2 NC#AD20 NC#AC20 XTALOUT NC#AE16 NC#AD16 10P_0402_50V8J SEYMOUR/FutureASIC PAD PAD 1 1 TV13@ TV14@ +1.8VGS AH26 AJ27 AD22 AG24 AE22 PS_0 AE23 AD23 GPU_DPLUS GPU_DMINUS T4 T2 GPIO_28_FDO +TSVDD R5 AD17 AC17 DPLUS DMINUS RV74 10K_0402_5% @ PS_1 1 RV77 2K_0402_1% PX@ AM12 1 CEC_1 @ TV5 PAD AK12 AL11 AJ11 2 CV15 .01U_0402_16V7-K @ 1 GENLK_CLK GENLK_VSYNC 1 TV1 TV2 PAD @ PAD @ PS_2 AG13 AH12 PS_0 AD19 PS_1 AE17 PS_2 AE20 PS_3 2 NC_DDCVGACLK NC_DDCVGADATA THERMAL CV18 .01U_0402_16V7-K @ R_pu(Ω) R_pd(Ω) PS_1[5:1] 1 1 0 0 0 RV74=NC RV77=4.75K CV16=NC PS_2[5:1] 1 1 0 0 0 RV60=NC RV69=4.75K CV16=NC PS_3[5:1] 1 1 X X X RV60=X76 RV69=X76 AE6 AE5 R_pu (次) AD2 AD4 000 2000 001 4530 2000 010 6980 4990 011 Bits [5:4] 4530 4990 100 680 00 3240 5620 101 82 01 3400 10000 110 10 10 4750 NC 111 NC 11 Capacitor Value (nF) Note: 0402 1% resistors are required. 1.1 JET-S3-LE_FCBGA631 PX@ 0 1 1.0 1 0 0.9 1 1 0.8 * Connect GPIO_28 to 10K pull down to enable MLPS. GPU_SVD GPU_SVC 1 +3VGS A 4 D QV4B S VGA_SMB_DATA EC_SMB_CK2 <39,44,5> EC_SMB_DA2 <39,44,5> 5 2 2 6 PX@ 2N7002KDWH_SOT363-6 G 2 QV4A 1 VGA_SMB_CLK QV14 MMBT3904_SOT23-3 @ D @ 2 E RV44 47K_0402_5% PX@ S 1 .01U_0402_16V7-K CV216 RV134 100K_0402_5% @ 1 1 +3VGS RV43 47K_0402_5% PX@ 2 C Internal VGA Thermal Sensor 3 1 2 1 2 2 C QV13 MMBT3904WH_SOT323-3 PX@ E 2 B 3 2 RV133 1 @ 47K_0402_5% 1 1 PX@ 2 RV132 47K_0402_5% 2 B 1 G GPIO_19_CTF 1 PX@ 2 2.2K_0402_5% RV131 1K_0402_5% PX@ @ SDM10U45LP-7_DFN1006-2-2 A 1 1 DV2 2 2 1 2 1 1 C 1 RV130 20K_0402_5% @ .1U_0402_10V6-K GPU_RST# GPU_RST# RV129 20K_0402_5% FOR ONE TIME CTF USE 47K @ FOR RESETABLE CTF USE 2K CV215 <19> 1 1 2 3 E 2 RV128 PX@ RV207 10K_0402_5% @ B QV12 MMBT3906_SOT23-3 @ RV206 10K_0402_5% PX@ RV242 0_0402_5% PX@ RV127 20K_0402_5% @ RV204 10K_0402_5% PX@ <44> 2 WRST# RV205 10K_0402_5% @ OK ACLU5 has no THRMTRIP#, so to EC WRST#? +3VGS +VDDIO_GPU 1 PX@ 2 0_0402_5% RV234 2 0 1 1 SVD 0 1 2 Output Voltage (V) SVC B 2 (1.8V@20mA TSVDD) RV42 10K_0402_5% PX@ GPIO28_FDO TSVDD TSVSS Bits [3:1] 4750 8450 AD13 AD11 AC1 AC3 CV16=X76 NC AC11 AC13 AE16 AD16 CV15=NC R_pd (次) 2 2 PX@ LV3 1 BLM15AG121SH1D_2P C(nF) 1 1 0 0 1 RV71=8.45k RV77=2K 1 2 +1.8VGS 1U_0402_6.3V6K PX@ CV21 2 RV41 1 @ 10K_0402_5% CV19 .01U_0402_16V7-K X76@ 2 BOM Bit 5 4 3 2 1 +1.8VGS +3VS 1 RV70 2K_0402_1% X76@ PS_0[5:1] AD20 AC20 3 PX@ 2N7002KDWH_SOT363-6 RV135 1 PX@ 2 0_0402_5% Issued Date 5 Title LC Future Center Secret Data Security Classification No GPIO Reserve for NV GPU 2013/08/08 Deciphered Date 2013/08/05 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 4 C RV63 8.45K_0402_1% X76@ PS_3 1 MLPS AE19 CV16 .01U_0402_16V7-K @ 2 +1.8VGS RV69 4.75K_0402_1% PX@ AC19 1 RV80 4.75K_0402_1% PX@ +1.8VGS AL13 AJ13 X +1.8VGS RV71 8.45K_0402_1% PX@ NC_DBG_VREFG 2 27MHZ_10PF_7V27000050 OSC1 GND1 OSC2 GND2 4 3 TS_A DDC/AUX 10K_0402_5% 10K_0402_5% AH24 AG25 RV60 10K_0402_5% @ JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO TESTEN NC#AF24 PLL/CLOCK B 1 NC_HSYNC NC_VSYNC AUD_PORT_CONN_ PINSTRAP[2] AL25 AJ25 2RV54 @ 10P_0402_50V8J PX@ 2 DAC1 XTALIN CV25 YV1 PX@ NC_G NC_AVSSN#AJ25 NC_B NC_AVSSN#AG25 X 1 OK GPIO_0 NC_GPIO_1 NC_GPIO_2 SMBDATA SMBCLK GPIO_5_AC_BATT GPIO_6 NC_GPIO_7 GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK NC_GPIO_11 NC_GPIO_12 NC_GPIO_13 NC_GPIO_14 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT NC_GPIO_18 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21 GPIO_22_ROMCSB GPIO_29 GPIO_30 CLKREQB NA Determines the maximum number of digital display audio endpoints that will be presented to the OS and user.(Combine with PS_0[5]) 111 = No usable endpoints. 110 = One usable endpoint. 111= No usable endpoints. 101 = Two usable endpoints. 100 = Three usable endpoints. 011 = Four usable endpoints. 010 = Five usable endpoints. 001 = Six usable endpoints. 000 = All endpoints are usable. AUD_PORT_CONN_ PINSTRAP[1] PS_3[5] 0 Board configuration related strapping, such as for memory ID 100 = Hynix 1G 000 = Hynix 2G 111 = Micron 1G 010 = Micron 2G 110 = Samsung 1G 001 = Samsung 2G BOARD_CONFIG[0] BOARD_CONFIG[1] BOARD_CONFIG[2] PS_3[4] AM26 AK26 X 1 U6 U10 T10 U8 U7 T9 T8 T7 P10 P4 P2 N6 N5 N3 Y9 N1 M4 R6 W10 M2 P8 P7 N8 AK10 AM10 N7 GPU_GPIO0 Reserve SCL SDA NC_R NC_AVSSN#AK26 GENERAL PURPOSE I/O NA 0= Disable 0 = VGA controller capacity enabled. 1 = The device will not be recognized as the system＊s VGA controller. Reserved 2 R1 R3 GPU_GPIO22 GPU_VID1 GPU_GPIO21 GPU_VID5 GPU_VID2 NA 0 = Disable the external BIOS ROM device. 1 = Enable the external BIOS ROM device. 1 RV81 RV97 RV98 RV99 RV106 D X 1= Enable 1 2 2 2 2 2 @ @ @ @ @ 0= Not support TV10 PAD @ 2 1 1 1 1 1 1 PS_0[5] AK5 AM3 I2C 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% RECOMMENDED SETTINGS Description Define the ROM type when STRAP_BIOS_ROM_EN = 1, Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0. 1 1 +3VGS DVO Strap Name PS_0[1] PS_0[2] PS_0[3] 2 GPU_SVC_R NC#AK3 NC#AK1 MLPS Bit 1 6 4 NC#AH3 NC#AH1 AG3 AG5 2 2 10U_0603_6.3V6M .1U_0402_10V6-K CV236 PX@ GPU_SVD_R DPA AF2 AF4 1 2 2 GND 7 RV241 PX@ 2 1 10K_0402_5% D Reserve 2B DIR 8 74AVCH2T45GD_XSON8_3X2 PX@ 1 1 2A 5 RV238 10K_0402_5% @ 1B NC#AG3 NC#AG5 2 3 GPU_VID4_R VCC(B) 1A DBG_DATA16 DBG_DATA15 DBG_DATA14 DBG_DATA13 DBG_DATA12 DBG_DATA11 DBG_DATA10 DBG_DATA9 DBG_DATA8 DBG_DATA7 DBG_DATA6 DBG_DATA5 DBG_DATA4 DBG_DATA3 DBG_DATA2 DBG_DATA1 DBG_DATA0 1 VCC(A) 2 NC#AF2 NC#AF4 N9 L9 AE9 Y11 AE8 AD9 AC10 AD7 AC8 AC7 AB9 AB8 AB7 AB4 AB2 Y8 Y7 .1U_0402_10V6-K 2 1 GPU_VID3_R RV237 10K_0402_5% PX@ CV223 PX@ 1 2 .1U_0402_10V6-K UV11 1 1 RV236 10K_0402_5% PX@ 2 CV222 PX@ 1 2 2 2 +3VGS RV235 10K_0402_5% @ ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET 2 +3VGS 3 2 ATI_JET-LE_Main_MSIC Size Document Number Custom Date: Rev 0.4 NM-A281 Thursday, February 20, 2014 1 Sheet 20 of 60 5 4 3 2 1 UV1F D D NC_VARY_BL NC_DIGON NC_UPHYAB_TMDPA_TX0N NC_UPHYAB_TMDPA_TX0P NC_UPHYAB_TMDPA_TX1N NC_UPHYAB_TMDPA_TX1P NC_UPHYAB_TMDPA_TX2N NC_UPHYAB_TMDPA_TX2P NC_UPHYAB_TMDPA_TX3N NC_UPHYAB_TMDPA_TX3P NC_TXOUT_L3P NC_TXOUT_L3N AB11 AB12 AL15 AK14 AH16 AJ15 AL17 AK16 AH18 AJ17 AL19 AK18 C C TMDP NC_UPHYAB_TMDPB_TX0N NC_UPHYAB_TMDPB_TX0P NC_UPHYAB_TMDPB_TX1N NC_UPHYAB_TMDPB_TX1P NC_UPHYAB_TMDPB_TX2N NC_UPHYAB_TMDPB_TX2P NC_UPHYAB_TMDPB_TX3N NC_UPHYAB_TMDPB_TX3P NC_TXOUT_U3P NC_TXOUT_U3N AH20 AJ19 AL21 AK20 AH22 AJ21 AL23 AK22 AK24 AJ23 JET-S3-LE_FCBGA631 PX@ B B A A Title LC Future Center Secret Data Security Classification Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_TMDP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 Sheet 1 21 of 60 5 4 +1.8VGS 2 1 +0.95VGS 1 2 1U_0402_6.3V6K CV40 PX@ D +DP_VDDR 10U_0603_6.3V6M CV39 PX@ 0_0603_5% UV1G UV1E DP POWER 1 AG15 AG16 AF16 AG17 AG18 AG19 AF14 2 NC/DP POWER NC_DP_VDDR#AG15 NC_DP_VDDR#AG16 NC_DP_VDDR#AF16 NC_DP_VDDR#AG17 NC_DP_VDDR#AG18 NC_DP_VDDR#AG19 DP_VDDR#AF14 NC#AE11 NC#AF11 NC#AE13 NC#AF13 NC#AG8 NC#AG10 NC_DP_VDDC#AG20 NC_DP_VDDC#AG21 NC_DP_VDDC#AF22 NC_DP_VDDC#AG22 DP_VDDC#AD14 NC#AF6 NC#AF7 NC#AF8 NC#AF9 AE11 AF11 AE13 AF13 AG8 AG10 AA27 AB24 AB32 AC24 AC26 AC27 AD25 AD32 AE27 AF32 AG27 AH32 K28 K32 L27 M32 N25 N27 P25 P32 R27 T25 T32 U25 U27 V32 W25 W26 W27 Y25 Y32 (0.95V@560mA DP_VDDC) @ 2 +DP_VDDC 1 2 .1U_0402_16V7K PX@ CV37 0_0603_5% 1U_0402_6.3V6K PX@ CV38 RV47 1 2 (1.8V@425mA DP_VDDR) @ RV48 1 3 1 2 C 2 @ RV49 1 150_0402_1% AG20 AG21 AF22 AG22 AD14 AG14 AH14 AM14 AM16 AM18 AF23 AG23 AM20 AM22 AM24 AF19 AF20 AE14 AF17 NC_DP_VSSR_1 NC_DP_VSSR_2 NC_DP_VSSR_3 NC_DP_VSSR_4 NC_DP_VSSR_5 NC_DP_VSSR_6 NC_DP_VSSR_7 NC_DP_VSSR_8 NC_DP_VSSR_9 NC_DP_VSSR_10 NC_DP_VSSR_11 NC_DP_VSSR_12 DP_VSSR_13 NC#AE1 NC#AE3 NC#AG1 NC#AG6 NC#AH5 NC#AF10 NC#AG9 NC#AH8 NC#AM6 NC#AM8 NC#AG7 NC#AG11 NC_UPHYAB_DP_CALR NC#AE10 AF6 AF7 AF8 AF9 AE1 AE3 AG1 AG6 AH5 AF10 AG9 AH8 AM6 AM8 AG7 AG11 AE10 M6 N13 N16 N18 N21 P6 P9 R12 R15 R17 R20 T13 T16 T18 T21 T6 U15 U17 U20 U9 V13 V16 V18 Y10 Y15 Y17 Y20 R11 T11 AA11 M12 N11 V11 JET-S3-LE_FCBGA631 PX@ B GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98 GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 VSS_MECH_1 VSS_MECH_2 VSS_MECH_3 A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6 D C B A32 AM1 AM32 JET-S3-LE_FCBGA631 PX@ A A Title LC Future Center Secret Data Security Classification Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_DP Power THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 Sheet 1 22 of 60 5 4 3 2 1 +1.35VGS UV1D 2 1 2 1 2 10U_0603_6.3V6M PX@ CV71 2 1 2 1 1 RF 2 2 CV502 33P_0402_50V8J @ 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 PLL 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2.2U_0402_6.3V6M PX@ CV151 1 2.2U_0402_6.3V6M PX@ CV137 2 2.2U_0402_6.3V6M PX@ CV133 1 2.2U_0402_6.3V6M PX@ CV159 2 2.2U_0402_6.3V6M PX@ CV152 1 2.2U_0402_6.3V6M PX@ CV84 +VGA_CORE AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 AA12 M11 N12 U11 VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDDC_23 VDDC_24 VDDC_25 10U_0603_6.3V6M PX@ CV135 2 1 1 10U_0603_6.3V6M PX@ CV134 2 1 2 10U_0603_6.3V6M PX@ CV160 NC_VDDR4_1 NC_VDDR4_2 NC_VDDR4_3 1 10U_0603_6.3V6M PX@ CV156 2 1 1U_0402_6.3V6K PX@ CV27 For EMC V12 Y12 U12 +MPLL_PVDD 10U_0603_6.3V6M PX@ CV34 1 2 VDDR3_1 VDDR3_2 VDDR3_3 VDDR3_4 (1.8V@130mA MPLL_PVDD) 10U_0603_6.3V6M PX@ CV26 PX@ 1 2 GBK160808T-221Y-N I/O AA17 AA18 AB17 AB18 1 POWER @ CV24 .1U_0402_16V7K LV4 C +VDDR3 1U_0402_6.3V6K PX@ CV149 +1.8VGS CORE 2 10U_0603_6.3V6M PX@ CV153 2 0_0402_5% @ VDD_CT_1 VDD_CT_2 VDD_CT_3 VDD_CT_4 1 2.2U_0402_6.3V6M PX@ CV150 1 LV8 L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22 10U_0603_6.3V6M PX@ CV139 (3.3V@25mA VDDR3) (0.95V@2500mA PCIE_VDDC) 2.2U_0402_6.3V6M PX@ CV148 +3VGS D +0.95VGS PCIE_VDDC_1 PCIE_VDDC_2 PCIE_VDDC_3 PCIE_VDDC_4 PCIE_VDDC_5 PCIE_VDDC_6 PCIE_VDDC_7 PCIE_VDDC_8 PCIE_VDDC_9 PCIE_VDDC_10 PCIE_VDDC_11 PCIE_VDDC_12 LEVEL TRANSLATION AA20 AA21 AB20 AB21 2 2.2U_0402_6.3V6M PX@ CV146 2 1 1U_0402_6.3V6K PX@ CV69 1U_0402_6.3V6K PX@ CV144 1 2 2.2U_0402_6.3V6M PX@ CV143 2 0_0402_5% @ 1 1U_0402_6.3V6K PX@ CV68 1 LV7 AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26 NC#AB23 NC#AC23 NC#AD24 NC#AE24 NC#AE25 NC#AE26 NC#AF25 NC#AG26 2.2U_0402_6.3V6M PX@ CV141 +VDD_CT (1.8V@13mA VDD_CT) VDDR1_1 VDDR1_2 VDDR1_3 VDDR1_4 VDDR1_5 VDDR1_6 VDDR1_7 VDDR1_8 VDDR1_9 VDDR1_10 VDDR1_11 VDDR1_12 VDDR1_13 VDDR1_14 VDDR1_15 VDDR1_16 VDDR1_17 (1.8V@100mA PCIE_PVDD) AM30 PCIE_PVDD 2.2U_0402_6.3V6M PX@ CV77 H13 H16 H19 J10 J23 J24 J9 K10 K23 K24 K9 L11 L12 L13 L20 L21 L22 D +1.8VGS +1.8VGS MEM I/O 2 1U_0402_6.3V6K PX@ CV46 1 10U_0603_6.3V6M PX@ CV47 2 1U_0402_6.3V6K PX@ CV67 1 1U_0402_6.3V6K PX@ CV66 2 2.2U_0402_6.3V6M PX@ CV76 1 1U_0402_6.3V6K PX@ CV65 2 2.2U_0402_6.3V6M PX@ CV75 1 1U_0402_6.3V6K PX@ CV64 2 2.2U_0402_6.3V6M PX@ CV74 1 2.2U_0402_6.3V6M PX@ CV73 2 .1U_0402_16V7K PX@ CV56 1 .01U_0402_16V7-K PX@ CV217 2 2.2U_0402_6.3V6M PX@ CV55 1 2.2U_0402_6.3V6M PX@ CV54 2 2.2U_0402_6.3V6M PX@ CV53 1 2.2U_0402_6.3V6M PX@ CV52 2 2.2U_0402_6.3V6M PX@ CV51 1 CV501 33P_0402_50V8J @ PCIE 10U_0603_6.3V6M PX@ CV48 For DDR3/GDDR5, 1500mA@1.5V RF 1 2 1 1 2 2 RF CV503 33P_0402_50V8J @ C +0.95VGS (0.95V@1400mA BIF_VDDC) +1.8VGS 1 MPLL_PVDD +VGA_CORE 1 For EMC @ 2 1 2 H8 SPLL_VDDC J7 SPLL_PVSS 1 1 2 1 2 1 2 1 2 1 2 1 2 10U_0603_6.3V6M PX@ CV220 +SPLL_VDDC 10U_0603_6.3V6M PX@ CV138 PX@ 1 2 BLM15AG121SH1D_2P 1U_0402_6.3V6K PX@ CV136 LV6 M13 M15 M16 M17 M18 M20 M21 N20 VDDCI_1 VDDCI_2 VDDCI_3 VDDCI_4 VDDCI_5 VDDCI_6 VDDCI_7 VDDCI_8 SPLL_PVDD 1U_0402_6.3V6K PX@ CV132 H7 (0.95V@100mA SPLL_VDDC) 1U_0402_6.3V6K PX@ CV158 +SPLL_PVDD +0.95VGS 2 .1U_0402_16V7K PX@ CV219 1 2 (GDDR3/DDR3 8.8A@1.12V VDDCI) .1U_0402_16V7K PX@ CV218 2 CV33 .1U_0402_16V7K @ 2 1 L8 ISOLATED CORE I/O .1U_0402_16V7K @ CV36 For EMC +MPLL_PVDD 1U_0402_6.3V6K PX@ CV35 1 +SPLL_PVDD 1U_0402_6.3V6K PX@ CV30 PX@ 1 2 BLM15AG121SH1D_2P 10U_0603_6.3V6M PX@ CV29 CV28 .1U_0402_16V7K LV5 R21 U21 BIF_VDDC_1 BIF_VDDC_2 (1.8V@75mA SPLL_PVDD) CV41 1U_0402_6.3V6K PX@ 1 1 RF 2 2 CV504 33P_0402_50V8J @ JET-S3-LE_FCBGA631 PX@ 2 B B PXS_PWREN# 1 PX@ 2 RV53 20K_0402_5% S 1 A 2 G D QV8 PX@ 2 3 1 2 1 CV212 1 2 RV91 470_0603_5% @ 1 2 2 CV211 D QV10 2 PX@ PXS_PWREN# G 1 PX@ 2 RV92 100K_0402_5% 2N7002KW_SOT323-3 @ 1 .1U_0402_16V7K @ @2 CV210 10U_0603_6.3V6M @ + 10U_0603_6.3V6M PX@ 330U_D2_2V_Y 1 S 2N7002KW_SOT323-3 @ CV145 .1U_0402_16V7K PX@ PXS_PWREN# S 2N7002KW_SOT323-3 2 G D RV118 120K_0402_5% PX@ QV11 PX@ S 2N7002KW_SOT323-3 1 2 CV213 .1U_0402_16V7K PX@ A 2 RV1000 100K_0402_5% PX@ 3 PXS_PWREN PXS_PWREN +VSB <46> CV214 1 2 3 5 QV9 PXS_PWREN# 1 1 1 OK <58,6> 2 QV7 G 2 JUMP_43X118 AON6414AL_DFN8-5 CV209 1 3 D 2 1 PX@ 2 RV52 20K_0402_5% 2 1 +1.35VGS 2 @ 1 2 1 2 2 G +5VALW 2 CV208 1 RV51 470_0603_5% @ 10U_0603_6.3V6M PX@ 1 PX@ CV142 1 10U_0603_6.3V6M PX@ D S QV6 3 LP2301ALT1G_SOT23-3 CV140 1 3 2 JV2 1 1 JUMP_43X39 Need OPEN +1.35V 2 @ 2 1 1 JV1 +1.35V TO +1.35VGS +3VGS 4 Need OPEN 1U_0402_10V6K PX@ +3VS 10U_0603_6.3V6M PX@ +3.3VS TO +3VGS Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 2013/08/05 Deciphered Date ATI_JET-LE_Power THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 23 of 60 5 4 3 2 1 UV1C FBA_D[63..0] FBA_MA[15..0] <25,26> FBA_MA[15..0] FBA_BA[2..0] FBA_BA[2..0] GDDR5/DDR3 FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 <25,26> <25,26> D +1.35VGS 1 C 2 RV61 40.2_0402_1% PX@ 1 +VDD_MEM15_REFDA 1 RV65 100_0402_1% PX@ 2 2 CV154 1U_0402_6.3V6K PX@ 1 +1.35VGS RV62 40.2_0402_1% PX@ +VDD_MEM15_REFSA +VDD_MEM15_REFDA +VDD_MEM15_REFSA 1 2 B 1 RV66 100_0402_1% PX@ 2 2 CV157 1U_0402_6.3V6K PX@ 2 PX@ RV55 1 120_0402_1% PAD @ TV8 PAD @ TV9 1 1 K27 J29 H30 H32 G29 F28 F32 F30 C30 F27 A28 C28 E27 G26 D26 F25 A25 C25 E25 D24 E23 F23 D22 F21 E21 D20 F19 A19 D18 F17 A17 C17 E17 D16 F15 A15 D14 F13 A13 C13 E11 A11 C11 F11 A9 C9 F9 D8 E7 A7 C7 F7 A5 E5 C3 E1 G7 G6 G1 G3 J6 J1 J3 J5 K26 J26 J25 K25 DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31 GDDR5/DDR3 MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA0_8/MAA_13 MAA0_9/MAA_15 MEMORY INTERFACE FBA_D[63..0] MAA1_0/MAA_8 MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12 MAA1_5/MAA_BA2 MAA1_6/MAA_BA0 MAA1_7/MAA_BA1 MAA1_8/MAA_14 MAA1_9/RSVD WCKA0_0/DQMA0_0 WCKA0B_0/DQMA0_1 WCKA0_1/DQMA0_2 WCKA0B_1/DQMA0_3 WCKA1_0/DQMA1_0 WCKA1B_0/DQMA1_1 WCKA1_1/DQMA1_2 WCKA1B_1/DQMA1_3 EDCA0_0/QSA0_0 EDCA0_1/QSA0_1 EDCA0_2/QSA0_2 EDCA0_3/QSA0_3 EDCA1_0/QSA1_0 EDCA1_1/QSA1_1 EDCA1_2/QSA1_2 EDCA1_3/QSA1_3 DDBIA0_0/QSA0_0B DDBIA0_1/QSA0_1B DDBIA0_2/QSA0_2B DDBIA0_3/QSA0_3B DDBIA1_0/QSA1_0B DDBIA1_1/QSA1_1B DDBIA1_2/QSA1_2B DDBIA1_3/QSA1_3B ADBIA0/ODTA0 ADBIA1/ODTA1 CLKA0 CLKA0B CLKA1 CLKA1B RASA0B RASA1B CASA0B CASA1B CSA0B_0 CSA0B_1 MVREFDA MVREFSA CSA1B_0 CSA1B_1 NC#J25 MEM_CALRP0 CKEA0 CKEA1 DRAMRST L10 CLKTESTA CLKTESTB K8 L7 WEA0B WEA1B DRAM_RST K17 J20 H23 G23 G24 H24 J19 K19 G20 L17 FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA13 FBA_MA15 J14 K14 J11 J13 H11 G11 J16 L15 G14 L16 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_BA2 FBA_BA0 FBA_BA1 FBA_MA14 E32 E30 A21 C21 E13 D12 E3 F4 FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 H28 C27 A23 E19 E15 D10 D6 G5 FBA_DQS0 FBA_DQS1 FBA_DQS2 FBA_DQS3 FBA_DQS4 FBA_DQS5 FBA_DQS6 FBA_DQS7 H27 A27 C23 C19 C15 E9 C5 H4 FBA_DQS#0 FBA_DQS#1 FBA_DQS#2 FBA_DQS#3 FBA_DQS#4 FBA_DQS#5 FBA_DQS#6 FBA_DQS#7 L18 K16 FBA_ODTA0 FBA_ODTA1 H26 H25 FBA_CLKA0 FBA_CLKA0# G9 H9 FBA_CLKA1 FBA_CLKA1# G22 G17 FBA_RASA0# FBA_RASA1# G19 G16 FBA_CASA0# FBA_CASA1# H22 J22 FBA_CSA0# G13 K13 FBA_CSA1# K20 J17 FBA_CKEA0 FBA_CKEA1 G25 H10 FBA_WEA0# FBA_WEA1# D FBA_DQM[7..0] <25,26> FBA_DQS[7..0] <25,26> C FBA_DQS#[7..0] FBA_ODTA0 FBA_ODTA1 <25> <26> FBA_CLKA0 FBA_CLKA0# <25> <25> FBA_CLKA1 FBA_CLKA1# <26> <26> FBA_RASA0# FBA_RASA1# <25> <26> FBA_CASA0# FBA_CASA1# <25> <26> <25,26> B FBA_CSA0# <25> FBA_CSA1# <26> FBA_CKEA0 FBA_CKEA1 <25> <26> FBA_WEA0# FBA_WEA1# <25> <26> CLKTESTA CLKTESTB JET-S3-LE_FCBGA631 PX@ 1 DRAMRST RV58 4.99K_0402_1% PX@ 2 A 2 RV56 1 PX@ 10_0402_5% 2 PX@ RV57 1 51.1_0402_1% 1 2 FBA_RST# CV147 120P_0402_50V8-J PX@ A <25,26> Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 2013/08/05 Deciphered Date ATI_JET-LE_MEM IF THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 24 of 60 5 4 3 2 1 FBA_MA[15..0] FBA_BA[2..0] Memory Partition A - Lower 32 bits <24,26> FBA_DQS[3..0] <24> FBA_DQM[3..0] <24> FBA_DQS#[3..0] FBA_D[31..0] ACLU5 swap the VRAM Data @ 08/26 VRAM 8 pcs change to 4 pcs @ 09/26 <24,26> <24> <24> UV6 UV5 D FBA_DQS0 FBA_DQS3 F3 C7 D7 C3 C8 C2 A7 A2 B8 A3 FBA_D9 FBA_D10 FBA_D13 FBA_D12 FBA_D8 FBA_D14 FBA_D15 FBA_D11 +1.35VGS Group2 (IN1) DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 +1.35VGS 1 K1 L2 J3 K3 L3 FBA_D19 FBA_D16 FBA_D23 FBA_D21 FBA_D22 FBA_D18 FBA_D20 FBA_D17 RV18 4.99K_0402_1% PX@ RV20 4.99K_0402_1% PX@ CV100 Group1 (TOP) RV19 4.99K_0402_1% PX@ 1 2 2 FBA_ODTA0 FBA_CSA0# FBA_RASA0# FBA_CASA0# FBA_WEA0# Group3 (BOT) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 E3 F7 F2 F8 H3 H8 G2 H7 +FBA_VREFC0_U CV101 1 J7 K7 K9 FBA_D31 FBA_D27 FBA_D30 FBA_D25 FBA_D28 FBA_D24 FBA_D29 FBA_D26 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 RV21 4.99K_0402_1% PX@ 1 2 FBA_CLKA0 FBA_CLKA0# FBA_CKEA0 D7 C3 C8 C2 A7 A2 B8 A3 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 Group0 (IN3) VREFCA VREFDQ 1 M2 N8 M3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 FBA_D1 FBA_D6 FBA_D2 FBA_D7 FBA_D0 FBA_D5 FBA_D3 FBA_D4 2 FBA_BA0 FBA_BA1 FBA_BA2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 E3 F7 F2 F8 H3 H8 G2 H7 @ N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 2 +FBA_VREFC0_L .1U_0402_10V6-K FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 VREFCA VREFDQ @ M8 H1 .1U_0402_10V6-K +FBA_VREFC0_U 1 M8 H1 +FBA_VREFC0_L 2 D +1.35VGS +1.35VGS FBA_DQS#0 FBA_DQS#3 G3 B7 DML DMU RESET 2 ZQ J1 L1 J9 L9 M7 RV16 243_0402_1% PX@ 2 RV15 10K_0402_5% @ 1 1 L8 FBA_MA15 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQSL DQSU T2 FBA_RST# FBA_RST# DQSL DQSU NC1 NC2 NC3 NC4 NC5 K1 L2 J3 K3 L3 FBA_DQS2 FBA_DQS1 F3 C7 FBA_DQM2 FBA_DQM1 E7 D3 FBA_DQS#2 FBA_DQS#1 G3 B7 FBA_RST# T2 RV17 243_0402_1% PX@ FBA_MA15 CV78 CV89 RESET ZQ NC1 NC2 NC3 NC4 NC5 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 FBA_CLKA0 RV26 40.2_0402_1% PX@ B1 B9 D1 D8 E2 E8 F9 G1 G9 CV104 PX@ 1 2 .01U_0402_16V7-K RV27 40.2_0402_1% PX@ B 1 PX@ 2 2 1U_0402_10V6-K 1 PX@ 2 CV94 1U_0402_10V6-K 1 PX@ 2 CV93 1U_0402_10V6-K 1 PX@ 2 CV92 1U_0402_10V6-K 1 PX@ PX@ 2 CV91 1U_0402_10V6-K 1 CV90 10U_0603_6.3V6-M 2 1U_0402_10V6-K 1 PX@ 2 DQSL DQSU A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 UV6 SIDE +1.35VGS CV83 1U_0402_10V6-K 1 PX@ 2 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 C FBA_CLKA0# CV82 1U_0402_10V6-K 1 PX@ 2 CV81 1U_0402_10V6-K 1 PX@ 2 CV80 1U_0402_10V6-K 1 PX@ PX@ 2 10U_0603_6.3V6-M 1 CV79 DML DMU A1 A8 C1 C9 D2 E9 F1 H2 H9 96-BALL SDRAM DDR3 K4W4G1646B-HC11_FBGA96 UV5 SIDE +1.35VGS VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 DQSL DQSU J1 L1 J9 L9 M7 96-BALL SDRAM DDR3 K4W4G1646B-HC11_FBGA96 B ODT CS RAS CAS WE L8 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 FBA_ODTA0 FBA_CSA0# FBA_RASA0# FBA_CASA0# FBA_WEA0# CK CK CKE B2 D9 G7 K2 K8 N1 N9 R1 R9 1 E7 D3 A1 A8 C1 C9 D2 E9 F1 H2 H9 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 J7 K7 K9 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 2 FBA_DQM0 FBA_DQM3 ODT CS RAS CAS WE FBA_CLKA0 FBA_CLKA0# FBA_CKEA0 BA0 BA1 BA2 1 FBA_ODTA0 FBA_CSA0# FBA_RASA0# FBA_CASA0# FBA_WEA0# M2 N8 M3 2 <24> <24> <24> <24> <24> CK CK CKE FBA_BA0 FBA_BA1 FBA_BA2 1 <24,26> FBA_CLKA0 FBA_CLKA0# FBA_CKEA0 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 2 C <24> <24> <24> BA0 BA1 BA2 +1.35VGS UV5 SIDE CV155 2 1 2 1 2 1 2 CV99 1 2 .1U_0402_10V6-K 1 CV98 PX@ .1U_0402_10V6-K 2 CV97 PX@ .1U_0402_10V6-K 1 PX@ 2 CV96 PX@ .1U_0402_10V6-K 1 CV95 PX@ .1U_0402_10V6-K 2 .1U_0402_10V6-K 1 CV88 PX@ .1U_0402_10V6-K 2 UV6 SIDE +1.35VGS CV87 PX@ .1U_0402_10V6-K 1 CV86 PX@ .1U_0402_10V6-K PX@ 2 PX@ .1U_0402_10V6-K 1 CV85 A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 2013/08/05 Deciphered Date ATI_JET-LE_VRAM_A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 25 of 60 5 4 3 2 1 FBA_MA[15..0] FBA_BA[2..0] Memory Partition A - Upper 32 bits FBA_DQS[7..4] <24> FBA_DQM[7..4] <24> FBA_DQS#[7..4] FBA_D[63..32] DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 FBA_D55 FBA_D51 FBA_D54 FBA_D48 FBA_D52 FBA_D50 FBA_D53 FBA_D49 M2 N8 M3 C FBA_CLKA1 J7 FBA_CLKA1# K7 FBA_CKEA1 K9 <24> <24> <24> FBA_CLKA1 FBA_CLKA1# FBA_CKEA1 <24> <24> <24> <24> <24> FBA_ODTA1 FBA_CSA1# FBA_RASA1# FBA_CASA1# FBA_WEA1# <24,25> FBA_RST# FBA_ODTA1 FBA_CSA1# FBA_RASA1# FBA_CASA1# FBA_WEA1# K1 L2 J3 K3 L3 FBA_DQS4 FBA_DQS5 F3 C7 FBA_DQM4 FBA_DQM5 E7 D3 FBA_DQS#4 FBA_DQS#5 G3 B7 FBA_RST# T2 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 CK CK CKE ODT CS RAS CAS WE VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 DQSL DQSU DML DMU VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQSL DQSU RESET ZQ RV30 Group6 (BOT) RV31 4.99K_0402_1% PX@ +1.35VGS B2 D9 G7 K2 K8 N1 N9 R1 R9 FBA_BA0 FBA_BA1 FBA_BA2 M2 N8 M3 FBA_CLKA1 FBA_CLKA1# FBA_CKEA1 J7 K7 K9 A1 A8 C1 C9 D2 E9 F1 H2 H9 FBA_ODTA1 FBA_CSA1# FBA_RASA1# FBA_CASA1# FBA_WEA1# K1 L2 J3 K3 L3 FBA_DQS7 FBA_DQS6 F3 C7 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 FBA_DQM7 FBA_DQM6 E7 D3 FBA_DQS#7 FBA_DQS#6 G3 B7 FBA_RST# T2 L8 BA0 BA1 BA2 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 CK CK CKE ODT CS RAS CAS WE VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 DQSL DQSU DML DMU VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 DQSL DQSU RESET ZQ RV32 4.99K_0402_1% PX@ CV127 1 2 B2 D9 G7 K2 K8 N1 N9 R1 R9 +FBA_VREFC1_U CV128 RV33 4.99K_0402_1% PX@ 1 2 +FBA_VREFC1_L A1 A8 C1 C9 D2 E9 F1 H2 H9 C A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 FBA_CLKA1 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 1 B1 B9 D1 D8 E2 E8 F9 G1 G9 J1 L1 J9 L9 M7 RV29 243_0402_1% PX@ FBA_MA15 96-BALL SDRAM DDR3 K4W4G1646B-HC11_FBGA96 NC1 NC2 NC3 NC4 NC5 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 B1 B9 D1 D8 E2 E8 F9 G1 G9 RV38 40.2_0402_1% PX@ 2 NC1 NC2 NC3 NC4 NC5 1 FBA_MA15 J1 L1 J9 L9 M7 CV131 PX@ 1 2 .01U_0402_16V7-K RV39 40.2_0402_1% PX@ 96-BALL SDRAM DDR3 K4W4G1646B-HC11_FBGA96 2 2 RV28 243_0402_1% PX@ 2 1 1 L8 BA0 BA1 BA2 +1.35VGS 4.99K_0402_1% PX@ +1.35VGS FBA_BA0 FBA_BA1 FBA_BA2 D +1.35VGS Group7 (IN3) 1 FBA_D56 FBA_D59 FBA_D57 FBA_D61 FBA_D60 FBA_D62 FBA_D63 FBA_D58 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 E3 F7 F2 F8 H3 H8 G2 H7 1 Group5 (TOP) DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 2 FBA_D40 FBA_D45 FBA_D43 FBA_D44 FBA_D42 FBA_D46 FBA_D41 FBA_D47 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 Group4 (IN1) VREFCA VREFDQ 1 D7 C3 C8 C2 A7 A2 B8 A3 M8 H1 +FBA_VREFC1_L 2 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 FBA_D38 FBA_D35 FBA_D37 FBA_D32 FBA_D36 FBA_D34 FBA_D39 FBA_D33 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 E3 F7 F2 F8 H3 H8 G2 H7 PX@ N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 .1U_0402_10V6-K FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14 VREFCA VREFDQ @ M8 H1 .1U_0402_10V6-K +FBA_VREFC1_U <24> <24> UV8 2 UV7 D <24,25> <24,25> B B FBA_CLKA1# UV7 SIDE +1.35VGS CV105 1 PX@ 2 CV121 2 1U_0402_10V6-K 1 PX@ 2 CV120 1U_0402_10V6-K PX@ 1 PX@ 2 CV126 2 .1U_0402_10V6-K 1 PX@ 2 CV125 .1U_0402_10V6-K 1 PX@ 2 CV124 .1U_0402_10V6-K 1 PX@ 2 CV123 .1U_0402_10V6-K 1 PX@ 2 1 1U_0402_10V6-K PX@ 2 1U_0402_10V6-K 1 CV119 UV8 SIDE CV122 .1U_0402_10V6-K 1 PX@ 2 CV115 .1U_0402_10V6-K 1 PX@ 2 2 CV118 +1.35VGS CV114 .1U_0402_10V6-K 1 PX@ PX@ 2 CV113 .1U_0402_10V6-K 1 .1U_0402_10V6-K PX@ 2 .1U_0402_10V6-K 1 CV112 1 PX@ CV111 2 CV117 1U_0402_10V6-K UV7 SIDE +1.35VGS 1 PX@ 2 CV116 10U_0603_6.3V6-M 1 PX@ 2 CV110 1U_0402_10V6-K 1 PX@ 2 UV8 SIDE +1.35VGS CV109 1U_0402_10V6-K 1 PX@ 2 CV108 1U_0402_10V6-K 1 PX@ PX@ 2 CV107 1U_0402_10V6-K 1 1U_0402_10V6-K PX@ 2 10U_0603_6.3V6-M 1 CV106 A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 2013/08/05 Deciphered Date ATI_JET-LE_VRAM_B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 26 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 2013/08/05 Deciphered Date Blank THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 27 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 2013/08/05 Deciphered Date Blank THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 28 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 2013/08/05 Deciphered Date Blank THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 29 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 2013/08/05 Deciphered Date Blank THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 30 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 2013/08/05 Deciphered Date Blank THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 31 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 2013/08/05 Deciphered Date Blank THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 32 of 60 5 4 3 B+ to +LEDVDD POWER LCD POWER CIRCUIT OK need rework to +3VS 2A 80 mil +LCDVDD_CON +LEDVDD 0_0805_5% 2 1 @ 1 IN2 OUT GND C1 1U_0402_6.3V6K 4 2 IN1 EN 1 +LCDVDD_CON 2 4.7U_0603_6.3V6-K 3 1 C2 PCH_ENVDD 2 G5243AT11U_SOT23-5 SA00005XJ00 CMOS Camera 2A 80 mil 4.7U_0805_25V6-K R17 U7 5 1 OK B+ +3VS 2 OK Need Short +3VS C14 1 J1 1 +3VS_CMOS LP2301ALT1G_SOT23-3 @ D S W=40 mils Q7 3 PCH_ENVDD 1 R3 1 @ 1 1 2 G PCH_ENVDD 2 2 JUMP_43X39 2 D <5> +3VS_CMOS_R @ 1 R35 100K_0402_5% 2 0_0603_5% W=40mils D C3 .1U_0402_10V6-K 2 2 <6> 2 R5 1 @ 100K_0402_5% CMOS_ON# 1 2 C10 .1U_0402_10V6-K @ JEDP1 OK +LEDVDD CPU_EDP_TX0+ CPU_EDP_TX0- C19 C16 1 1 2 .1U_0402_10V6-K 2 .1U_0402_10V6-K EDP_TX0+ EDP_TX0- CPU_EDP_TX1+ CPU_EDP_TX1- C17 C18 1 1 2 .1U_0402_10V6-K 2 .1U_0402_10V6-K EDP_TX1+ EDP_TX1- CPU_EDP_AUX C20 CPU_EDP_AUX# C21 1 1 2 .1U_0402_10V6-K 2 .1U_0402_10V6-K EDP_AUX EDP_AUX# 2 +3VS PCH_ENBKL R10 4.7K_0402_5% @ 1 2 @ 0_0402_5% R11 1 C 1 R14 1 2 0_0402_5% DISPOFF# 2 0_0402_5% ENBKL +3VS ENBKL <44> CPU_EDP_AUX CPU_EDP_AUX# OK R8 100K_0402_1% R9 100K_0402_1% @ @ +3VS <5> 1 2 @ 0_0402_5% R21 C22 680P_0402_50V7K @ 1 2 R13 100K_0402_1% R15 100K_0402_1% @ @ 1 2 2 +3VS CPU_EDP_HPD +LCDVDD_CON W=60mils OK<43> OK <43> 2 +3VS DMIC_DATA DMIC_CLK OK<7> OK<7> R182 1 @ R183 1 @ +3VS_CMOS USB20_P5 USB20_N5 2 0_0402_5% 2 0_0402_5% USB20_P5_R 2 0_0402_5% USB20_N5_R 2 1 PCH_EDP_PWM 1 C24 0.047U_0402_16V7K OK INVT_PWM @ INVT_PWM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C G1 G2 G3 G4 G5 31 32 33 34 35 ACES_50406-03071-001 ME@ W=40mils 1 1 OK<5> R19 ACLU5 ACLU1 has two PCH PWM Pin OK 1 EDP_AUX EDP_AUX# R18 1K_0402_5% @ DISPOFF# OK 2 1 R16 100K_0402_5% CPU_EDP_TX1+ CPU_EDP_TX1- OK<5> OK<5> @ @ CPU_EDP_TX0+ CPU_EDP_TX0- OK <5> OK <5> 2 PCH_ENBKL R12 1 BKOFF# 2 <44> OK<5> 1 OK OK <5> OK <5> 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 R20 100K_0402_5% 2 EMI request B B Touch Screen <44> OK R22 EC_TS_ON# .1U_0402_10V6-K 2 TS@ C23 1 1 TS@ 2 100K_0402_5% +3VS_TS_R +3VS_TS LP2301ALT1G_SOT23-3 D S 3 1 JTS1 TS@ 2 G C25 .1U_0402_10V6-K @ EMI request +3VS_TS_R 1 TS@ 2 0_0402_5% 1 2 0_0402_5% R28 2 TS@ 1 10K_0402_5% TS_RS R23 R24 1 TS@ 1 TS@ 2 0_0402_5% 2 0_0402_5% +3VS_TS 1 R26 @ @ USB20_N4_CONN USB20_P4_CONN USB20_P4_CONN +3VS_TS 2 0_0402_5% 1 2 3 4 5 6 USB20_N4_CONN +3VALW R27 1 2 3 4 5 6 GND1 GND2 7 8 ACES_87213-00601-P01 ME@ Touch Screen 3 C13 @ R25 USB20_N4 USB20_P4 1 @ 2 +3VS 2 <7> <7> @ 1 2 1 470P_0402_50V7K @ 1 470P_0402_50V7K 2 100P_0402_50V8J 1 INVT_PWM C12 DISPOFF# C11 DMIC_CLK 1 2 Q11 D2 For EMI USB20_N4 USB20_P5 1 USB20_N5 4 1 2 2 USB20_P5_R 3 USB20_N5_R 1 1 2 2 USB20_N4_CONN USB20_P4 4 4 3 3 USB20_P4_CONN 4 3 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 A For EMI CMM21T-900M-N_4P CMM21T-900M-N_4P D1 AZC199-02S.R7G_SOT23-3 @ AZ5215-01F_DFN1006P2E2 1 OK @ @ 2 For EMI L12 L13 2 A 2013/08/05 Deciphered Date eDP/ CMOS/Touch screen THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 33 of 60 5 4 HDMI_CLK-_C OK HDMI_CLK+_C 4 OK HDMI_TX0-_C 1 OK HDMI_TX0+_C 4 OK HDMI_TX1-_C 1 1 2 1 @ L2 OK 3 1 2 2 1 HDMI_CLK-_CON 2 3.3P_0402_50V8-C C26 @ D 3 1 HDMI_CLK+_CON 4 3 C27 HDMI2012F2SF-900T04_4P 2 3.3P_0402_50V8-C +3VS D @ L3 1 2 2 1 HDMI_TX0-_CON C28 2 3.3P_0402_50V8-C @ 3 3 2 3.3P_0402_50V8-C 5 HDMI_TX0+_CON 1 C29 HDMI2012F2SF-900T04_4P 4 HDMI_DET D3 1 1 10 9 HDMI_DET HDMIDAT_R 2 2 9 8 HDMIDAT_R HDMICLK_R 4 4 7 7 HDMICLK_R +5VS_HDMI 5 5 6 6 +5VS_HDMI G @ L4 1 2 2 1 HDMI_TX1-_CON Q1B 2 3.3P_0402_50V8-C C30 4 3 3 OK<5> 2 3.3P_0402_50V8-C APU_HDMI_DDC_CLK APU_HDMI_DDC_CLK 2N7002KDWH_SOT363-6 G 1 HDMI_TX1+_CON C31 HDMI2012F2SF-900T04_4P 4 2 4 HDMI_TX1+_C HDMICLK_R D OK 3 S @ Q1A OK HDMI_TX2+_C 4 1 2 4 3 2 HDMI_TX2-_CON 3 HDMI_TX2+_CON 1 2 3.3P_0402_50V8-C C32 OK<5> @ 1 C33 APU_HDMI_DDC_DATA 1 APU_HDMI_DDC_DATA 6 8 HDMIDAT_R D 1 S HDMI_TX2-_C 3 3 @ L5 OK 2 3.3P_0402_50V8-C 2N7002KDWH_SOT363-6 AZ1045-04F_DFN2510P10E-10-9 @ HDMI2012F2SF-900T04_4P For EMC For EMC 2 499_0402_1% 1 2 499_0402_1% OK HDMI_TX0-_C R31 1 2 499_0402_1% OK HDMI_TX0+_C R32 1 2 499_0402_1% OK HDMI_TX1-_C R33 1 2 499_0402_1% OK HDMI_TX1+_C R34 1 2 499_0402_1% OK HDMI_TX2-_C R37 1 2 499_0402_1% OK HDMI_TX2+_C C +5VS +5VS +5VS_HDMI_F 1 2 499_0402_1% RTMDS 499 ohm 3 1 2 0_0805_5% @ 1 R39 2K_0402_5% R40 2K_0402_5% C34 .1U_0402_10V6-K 2 S 1 2 APU_HDMI_HPD R205 100K_0402_5% R203 100K_0402_5% JHDMI1 HDMI_DET 2 100K_0402_5% B 2 @ E 2 2 150K_0402_5% R202 1 B MMBT3904WH_SOT323-3 2 1 Q13 OK <5> 2N7002KW_SOT323-3 G 3 D 2 R42 R36 2 1 C Q43 +3VS BAT54S-7-F_SOT23-3 1 0.5A_8V_KMC3S050RY 1 1 @ Follow Zx05 1 Provide DC bias R38 F1 1 3 RB491D_SOT23-3 D4 +3VS +5VS_HDMI D5 2 1 1 R30 2 R29 HDMI_CLK+_C 2 HDMI_CLK-_C OK 3 OK 1 C HDMIDAT_R HDMICLK_R OK<5> APU_HDMI_CLK- APU_HDMI_CLK- C35 2 1 .1U_0402_10V6-K HDMI_CLK-_C R43 2 @ 1 0_0402_5% HDMI_CLK-_CON OK<5> OK<5> APU_HDMI_CLK+ APU_HDMI_TX0- APU_HDMI_CLK+ APU_HDMI_TX0- C36 C37 2 2 1 .1U_0402_10V6-K 1 .1U_0402_10V6-K HDMI_CLK+_C R44 2 HDMI_TX0-_C R45 2 @ @ 1 0_0402_5% 1 0_0402_5% HDMI_CLK+_CON HDMI_TX0-_CON OK<5> OK<5> APU_HDMI_TX0+ APU_HDMI_TX1- APU_HDMI_TX0+ APU_HDMI_TX1- C38 C39 2 2 1 .1U_0402_10V6-K 1 .1U_0402_10V6-K HDMI_TX0+_C R46 2 HDMI_TX1-_C R47 2 @ @ 1 0_0402_5% 1 0_0402_5% HDMI_TX0+_CON HDMI_TX1-_CON APU_HDMI_TX1+ APU_HDMI_TX2- APU_HDMI_TX1+ APU_HDMI_TX2- C40 C41 2 2 1 .1U_0402_10V6-K 1 .1U_0402_10V6-K HDMI_TX1+_C R48 2 HDMI_TX2-_C R49 2 @ @ 1 0_0402_5% 1 0_0402_5% HDMI_TX1+_CON HDMI_TX2-_CON APU_HDMI_TX2+ APU_HDMI_TX2+ C42 2 1 .1U_0402_10V6-K HDMI_TX2+_C R50 2 @ 1 0_0402_5% HDMI_TX2+_CON OK<5> OK<5> OK<5> 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND1 CK_shield GND2 CK+ D0GND3 D0_shield GND4 D0+ D1D1_shield D1+ D2D2_shield D2+ 20 21 B 22 23 FOX_QJ111A1-RC0AH1-8H ME@ Close to JHDMI1 A HDMI_CLK+_CON D6 1 1 10 9 HDMI_CLK+_CON HDMI_TX1-_CON D7 1 1 10 9 HDMI_TX1-_CON HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON 3 3 A 3 3 8 8 AZ1045-04F_DFN2510P10E-10-9 @ For EMC AZ1045-04F_DFN2510P10E-10-9 @ Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 2013/08/15 Deciphered Date HDMI_CONN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 34 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 2013/08/15 Deciphered Date Blank THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 35 of 60 5 4 3 2 1 +CRT_VCC_CON +5VS_HDMI +5VS @ RVG39 1 CRT Connector 2 0_0603_5% D16 @ @ 1 2 +CRT_VCC_CON 0.5A_8V_KMC3S050RY W=40mils 1 2 1 F2 1 3 RB491D_SOT23-3 C164 .1U_0402_10V6-K D26 AZ5425-01F_DFN1006P2E2 1 2 D 2 2 D JCRT1 APU_CRT_B 2 <5> 2 OK R199 150_0402_1% R200 150_0402_1% 1 R201 150_0402_1% 1 1 1 2 L18 1 2 FCM1608CF-121T03_2P L19 1 2 FCM1608CF-121T03_2P 1 1 1 2 2 2 T5 1 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 CRT_DET# CRT_R_CON CRT_DDC_DAT_CON CRT_G_CON HSYNC_CON CRT_B_CON 1 2 1 2 10P_0402_50V8J C148 APU_CRT_G 10P_0402_50V8J C149 <5> 1 2 FCM1608CF-121T03_2P 10P_0402_50V8J C150 OK L17 10P_0402_50V8J C158 APU_CRT_R 10P_0402_50V8J C157 <5> 10P_0402_50V8J C156 OK 2 @ PAD VSYNC_CON CRT_DDC_CLK_CON 1 CLOSE TO CONN 2 +5VS @ C166 .1U_0402_10V6-K G G 16 17 @ SUYIN_070546HR015M25KZR C139 ME@ 100P_0402_50V8J 2 @ C 0_0402_5% OE# U4 74AHCT1G125GW_SOT353-5 2 APU_CRT_HSYNC A OE# P 5 1 2 L20 4 CRT_HSYNC_1 Y CRT_HSYNC_R 1 2 HSYNC_CON PBY100505T-800Y-N 3 1 R215 1 2 0_0402_5% @ 2 CRB use 27 ohm SR +5VS 10P_0402_50V8J C135 G OK<5> For EMC R204 1 1 C @ CRT_R_CON D18 1 1 10 9 CRT_R_CON CRT_G_CON 2 2 9 8 CRT_G_CON CRT_B_CON 4 4 7 7 CRT_B_CON CRT_DET# 5 5 6 6 CRT_DET# @ L20/L21 Change to 0 ohm??? 3 3 1 OE# C167 .1U_0402_10V6-K 1 L21 4 CRT_VSYNC_1 Y 1 CRT_VSYNC_R G A OE# 5 P 2 APU_CRT_VSYNC 2 VSYNC_CON PBY100505T-800Y-N 1 3 B R216 1 2 2 0_0402_5% @ +3VS @ B 1 1 2K_0402_5% HSYNC_CON D19 1 1 10 9 HSYNC_CON VSYNC_CON 2 2 9 8 VSYNC_CON CRT_DDC_CLK_CON 4 4 7 7CRT_DDC_CLK_CON CRT_DDC_DAT_CON 5 5 6 6CRT_DDC_DAT_CON 3 3 2 R198 2 6 S 1 8 CRT_DDC_DAT_CON_R CRT_DDC_DAT_CON G 5 D APU_CRT_DDC_DATA 2K_0402_5% G 2 +5VS R197 OK<5> AZ1045-04F_DFN2510P10E-10-9 @ 10P_0402_50V8J C136 OK<5> 8 U5 74AHCT1G125GW_SOT353-5 2 AZ1045-04F_DFN2510P10E-10-9 @ Q38A 2N7002KDWH_SOT363-6 AMD require 33 ohm SR For EMC S OK<5> 4 3 2N7002KDWH_SOT363-6 Q38B CRT_DDC_CLK_CON_R CRT_DDC_CLK_CON D APU_CRT_DDC_CLK @ C138 68P_0402_50V8J A 1 1 2 2 C137 @ 100P_0402_50V8J A RP2 CRT_DDC_DAT_CON_R CRT_DDC_CLK_CON_R CRT_VSYNC_1 CRT_HSYNC_1 1 2 3 4 8 7 6 5 CRT_DDC_DAT_CON CRT_DDC_CLK_CON CRT_VSYNC_R CRT_HSYNC_R 33_0804_8P4R_5% T PN change Idea pad PN SD300003700 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 2013/08/15 Deciphered Date CRT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 36 of 60 5 4 3 2 1 +3VALW TO +3VALW_LAN +3VALW Need short JL1 1 1 2 +3VALW_LAN rising time (10%~90%): 0.5msˉspecˉ100ms +3VALW_LAN +3VALW_LAN +LAN_VDDREG @ width : 40 mils 2 @ RL1 1 2 0_0603_5% Close to Pin11 CL5 1 2 Close to Pin32 CL6 1 2 1 CL7 2 Close to Pin11 1 .1U_0402_10V6-K 2 .1U_0402_10V6-K 1 4.7U_0603_6.3V6K CL4 4.7U_0603_6.3V6K JUMP_43X79 CL1 4.7U_0603_6.3V6K 2 1 D CL2 .1U_0402_10V6-K 2 Close to Pin32 +3VALW_LAN OK <44> UL1 2 G QL1 1 3 1 D LAN_CLKREQ#_R 1 2 RL4 10K_0402_5% @ RL5 10K_0402_5% @ ACLU1 reserved BDW GPIO27, ACLU5 removed 2 0_0402_5% RL6 1 @ LAN_WAKE# +3VS 2 +3VALW_LAN @ LAN_CLKREQ# S D OK <6> 2N7002KW_SOT323-3 PCIE_WAKE#_R C RL8 1 2 2.49K_0402_1% OK +3VS 1 TL3 @ 1 TL5 @ 1 TL4 @ 1 OK RL9 1K_0402_1% 2 OK OK <19,40,6> PLT_RST# OK<4> PCIE_PRX_DTX_N3 OK<4> PCIE_PRX_DTX_P3 ISOLATE# CL10 1 CL11 1 2 .1U_0402_10V6-K 2 .1U_0402_10V6-K 33 32 31 30 29 28 27 26 25 24 +LAN_REGOUT 23 +LAN_VDDREG 22 +LAN_VDD10 21 PCIE_WAKE#_R 20 ISOLATE# 19 PLT_RST# PCIE_PRX_C_DTX_N3 18 PCIE_PRX_C_DTX_P3 17 +3VALW_LAN RSET +LAN_VDD10 LAN_XTALO LAN_XTALI 0_0402_5% 2 GND AVDD33_2 RSET AVDD10 CKXTAL2 CKXTAL1 LED0 LED1/GPIO LED2 REGOUT VDDREG DVDD10 LANWAKEB ISOLATEB PERSTB HSON HSOP REFCLK_N REFCLK_P HSIN HSIP CLKREQB AVDD33_1 MDIN3 MDIP3 AVDD10_2 MDIN2 MDIP2 MDIN1 MDIP1 AVDD10_1 MDIN0 MDIP0 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OK CLK_PCIE_LAN# <7> CLK_PCIE_LAN <7>OK OK PCIE_PTX_C_DRX_N3 <4> OK PCIE_PTX_C_DRX_P3 <4> CLK_PCIE_LAN# CLK_PCIE_LAN PCIE_PTX_C_DRX_N3 PCIE_PTX_C_DRX_P3 LAN_CLKREQ#_R +3VALW_LAN LAN_MDI3LAN_MDI3+ +LAN_VDD10 LAN_MDI2LAN_MDI2+ LAN_MDI1LAN_MDI1+ +LAN_VDD10 LAN_MDI0LAN_MDI0+ OK OK LAN_MDI3LAN_MDI3+ OK <38> OK <38> LAN_MDI2LAN_MDI2+ LAN_MDI1LAN_MDI1+ OK <38> OK <38> OK <38> OK <38> LAN_MDI0LAN_MDI0+ OK <38> OK <38> 1 RL18 @ C 1 CL10 close to Pin18 CL11 close to Pin17 RL11 15K_0402_5% 2 UL1 8106@ RTL8111GUL-CG_QFN32_4X4 8111@ RTL8106EUL-CG B B SA000060Q00 For RTL8111GUL/ RTL8106EUL (SWR mode) +LAN_VDD10 +LAN_REGOUT 2 LL1 1 2.2UH_NLC252018T-2R2J-N_5% 1 CL15 4.7U_0603_6.3V6K 2 1 2 1 CL16 .1U_0402_10V6-K 2 1 CL17 .1U_0402_10V6-K 2 1 CL18 .1U_0402_10V6-K 2 1 CL19 .1U_0402_10V6-K 2 1 CL20 .1U_0402_10V6-K Close to Pin3, 8, 22, 30 LAN ROM LAN_XTALI YL1 1 2 GND2 GND1 OSC2 Close to Pin22(Reserved) A 4 3 1 25MHZ_10PF_7V25000014 2 CL22 .1U_0402_10V6-K @ LAN_XTALO OSC1 1 CL12 12P_0402_50V8-J 2 Layout Note: LL1 must be within 200mil to Pin36, CL15,CL16 must be within 200mil to LL1 +LAN_REGOUT: Width =60mil OK A 2 1 CL21 1U_0402_6.3V6K @ 2 Issued Date Title LC Future Center Secret Data Security Classification CL13 12P_0402_50V8-J 2013/08/08 2013/08/05 Deciphered Date LAN_RTL8111GUL/RTL8106EUL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 37 of 60 5 4 3 2 1 DL1/DL2 1'S PN:SC300003M00 6 LAN_MDI2+ 7 NC5 NC2 VDD GND NC3 NC4 I/O3 I/O1 3 LAN_MDI3- swap @ 9/13 11 8 1 C +3VALW_LAN 4 5 6 LAN_MDI1+ 7 I/O2 NC5 NC2 VDD GND NC3 NC4 I/O3 I/O1 22 3 <37> LAN_MDI1+ <37> LAN_MDI1- LAN_MDI1+ 20 LAN_MDI1- 19 18 <37> <37> LAN_MDI2+ LAN_MDI2- LAN_MDI2+ 17 LAN_MDI2- 16 15 DL2 I/O4 NC1 LAN_MDI0- LAN_MDI3+ Place Close to TL1 9 2 LAN_MDI0- 21 AZ3033-04F_DFN2525P10E10 LAN_MDI1- <37> 10 LAN_MDI0- 1 10 2 11 <37> LAN_MDI3+ <37> LAN_MDI3- LAN_MDI3+ 14 LAN_MDI3- 13 CL24 0.1U_0402_25V6 MX1+ TD1+ MX1- TD1- MCT2 TCT2 MX2+ TD2+ MX2- TD2- MCT3 TCT3 MX3+ TD3+ MX3- TD3- MCT4 TCT4 MX4+ TD4+ MX4- TD4- 1 MCT 2 LAN_MDO0+ D 3 LAN_MDO0- 4 MCT 5 LAN_MDO1+ 6 LAN_MDO1- 7 MCT 8 LAN_MDO2+ 9 LAN_MDO2- 10 MCT 11 LAN_MDO3+ 12 LAN_MDO3- RL17 75_0603_5% 1 I/O2 TCT1 1 4 5 I/O4 NC1 23 DL3 BS4200N-C-LV_SMB-F2 2 +3VALW_LAN 9 2 LAN_MDI0+ 2 LAN_MDI2- LAN_MDI0+ 1 DL1 <37> 8111@ MCT1 2 TL1 24 D CL32 10P_0603_50V8-J @ 1 1 2 2 CL25 1000P_1206_2KV7-K C BOTH_GST5009 LF swap @ 9/13 8 1 LAN_MDI0+ TL1 8106@ CHASSIS1_GND AZ3033-04F_DFN2525P10E10 Place Close to TL2 TST1284C LF LAN SP050008L00 JRJ1 ME@ GND_4 GND_3 B OK LAN_MDO0+ 1 LAN_MDO0- 2 LAN_MDO1+ 3 LAN_MDO2+ 4 LAN_MDO2- 5 LAN_MDO1- 6 LAN_MDO3+ 7 LAN_MDO3- 8 GND_2 PR1+ GND_1 12 11 10 9 B PR1PR2+ CHASSIS1_GND PR3+ PR3PR2PR4+ PR4SANTA_130460-3 A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 Deciphered Date LAN_Transformer 2013/08/05 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Date: 5 4 3 2 Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 Sheet 1 38 of 60 5 4 3 2 1 D D SMSC thermal sensor placed near DIMM +3VS 2 REMOTE-_R U1 1 1 C47 .1U_0402_10V6-K 2 +3VS R51 REMOTE+_R 2 REMOTE-_R 3 2 1 @ 10K_0402_5% 4 SCL D+ SDA D- ALERT# T_CRIT# 8 EC_SMB_CK2 7 EC_SMB_DA2 EC_SMB_CK2 <20,44,5> OK EC_SMB_DA2 <20,44,5> OK C R175 1 PX@ R176 1 UMA@ 2 0_0402_5% REMOTE+_R REMOTE2- R177 1 UMA@ 2 0_0402_5% REMOTE-_R REMOTE1- R178 1 PX@ E 1 Q15 MMBT3904WH_SOT323-3 PX@ 6 5 GND Near CPU core REMOTE2+ C46 100P_0402_50V8J @ Address 1001_101xb REMOTE2+ C 2 B 2 REMOTE1- VDD NCT7718W_MSOP8 REMOTE1+ 1 1 C45 100P_0402_50V8J @ 3 C44 2200P_0402_50V7K Near GPU&VRAM REMOTE1+ OK 1 REMOTE+_R 1 2 B 2 E 3 Close to U1 REMOTE2- C Q16 MMBT3904WH_SOT323-3 UMA@ 2 0_0402_5% C 2 0_0402_5% REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: Trace width/space:10/10 mil Trace length:<8" FAN Conn B B +5VS @ R52 1 1 C49 10U_0805_10V6K 2 JFAN1 2 0_0603_5% C50 .1U_0402_10V6-K @ 1 2 3 4 5 6 +5VS_FAN OK<44> 1 OK <44> EC_FAN_SPEED EC_FAN_PWM 2 1 2 3 4 GND1 GND2 ACES_85205-04001 ME@ A A Title LC Future Center Secret Data Security Classification Issued Date 2013/08/08 Deciphered Date 2013/08/05 Thermal sensor/FAN CONN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 Sheet 1 39 of 60 A B C D Mini-Express Card(WLAN/WiMAX) E +3VS_WLAN JWLAN1 1 3 5 7 GND1 USB_D+ USB_DGND2 9 NC 11 NC 13 NC 15 NC 17 MLDIR_SENSE 19 DP_ML3N 21 DP_ML3P 23 25 GND3 27 DP_ML2N 29 DP_ML2P 31 GND4 33 DP_HPD 35 GND5 37 PETP0 39 PETN0 41 GND6 43 PERP0 45 PERN0 47 GND7 49 REFCLKP0 51 REFCLKN0 53 GND8 55 CLKREQ0# 57 PEWAKE0# 59 GND9 61 PETP1 63 PETN1 65 GND10 67 PERP1 69 PERN1 71 GND11 73 REFCLKP1 75 REFCLKN1 GND12 USB20_P6 USB20_N6 1 OK <4> OK<4> PCIE_PTX_C_DRX_P4 PCIE_PTX_C_DRX_N4 OK<4> OK<4> PCIE_PRX_DTX_P4 PCIE_PRX_DTX_N4 OK<7> OK<7> CLK_PCIE_WLAN CLK_PCIE_WLAN# OK OK <44> WLAN_CLKREQ_Q# WLAN_WAKE# +3VALW R125 1 +3VS_WLAN R126 1 @ 2 10K_0402_5% 2 10K_0402_5% 76 3.3VAUX1 3.3VAUX2 LED#1 NC NC NC NC LED#2 GND16 DP_AUXN DP_AUXP GND13 DP_ML1N DP_ML1P GND14 DP_ML0N DP_ML0P GND15 RESERVED1 RESERVED2 RESERVED3 COEX3 COEX2 COEX1 SUSCLK PERST0# RESERVED/W_DISABLE#2 W_DISABLE#1 I2C_DATA I2C_CLK I2C_ALERT# RESERVED4 PERST1# CLKREQ1# PEWAKE1# 3.3VAUX4 3.3VAUX5 PEG1 PEG2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 1 @ T2 1 @ T3 1 EC_TX_RSVD EC_RX_RSVD R62 R63 1 1 @ @ R185 1 2 100_0402_1% 2 100_0402_1% 2 100_0402_1% EC_RX If EC have error single , can remove it. SUSCLK_R R55 PLT_RST# BT_OFF# R53 WLAN_OFF# R56 SMB_DATA_S3_R R58 SMB_CLK_S3_R R59 1 @ T4 EC_TX_R R184 1 @ 2 0_0402_5% 1 1 1 1 @ @ @ 2 2 2 2 1 OK <44> OK SUSCLK <6,9> PLT_RST# <19,37,6> OK PCH_BT_OFF# <6> OK PCH_WLAN_OFF# <6>OK OK SMB_DATA_S3 <14,15,6> SMB_CLK_S3 <14,15,6>OK 1K_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 2 100_0402_1% EC_TX OK <44> +3VS_WLAN EC_TX_R 1 OK<7> OK<7> R186 100K_0402_5% 77 2 JAE_SM3ZS067U410BAR1000 ME@ 2 2 WLAN_CLKREQ# OK +3VS to +3VS_WLAN (AOAC) OK Need short +3VS +3VS J2 +3VS_WLAN 1 2 2 G +3VS C83 @ 1 D 1 2 LP2301ALT1G_SOT23-3 S 1 +3VALW 3 Q17 1 AOAC@ WLAN_CLKREQ_Q# D AOAC@ 3 WLAN_CLKREQ# S <6> +3VS_WLAN @ 2 JUMP_43X79 R60 10K_0402_5% AOAC@ Q18 1 1 2 G 2N7002KW_SOT323-3 2 R61 1 @ 2 0_0402_5% <44> AOAC_ON# R54 1 AOAC@ 2 100K_0402_5% If support AOAC, NC R61; if not support AOAC, stuff R61. C53 .1U_0402_10V6-K AOAC@ 1 2 C54 .1U_0402_10V6-K AOAC@ RF Solution .1U_0402_10V6-K 2 C59 @ 1 .1U_0402_10V6-K 2 C60 @ 1 2 .1U_0402_10V6-K C170@ 1 .1U_0402_10V6-K 2 C172@ 1 2 .1U_0402_10V6-K 3 3 4 4 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. A B C NGFF WLAN 2013/08/05 Deciphered Date D Size Document Number Custom Date: Rev 0.4 NM-A281 Thursday, February 20, 2014 E Sheet 40 of 60 A B C D E 1 1 2 2.2U_0603_10V6-K 1 2 C58 <44,45> 3 USB_ON# USB_ON# +USB_VCCA U2 +5VALW OK 4 GND VOUT3 VIN1 VOUT2 VIN2 VOUT1 EN/EN FLAG 1 C55 + +USB_VCCA LEFT SIDE USB3.0 PORT X2 2 C56 1 @ 220U_6.3V_M 2 1U_0603_25V6M C57 1 @ 2 470P_0402_50V7K 8 7 1 6 JUSB1 5 USB_OC1# AP2820CMMTR-G1_MSOP8 Low Active 2A 1 2 USB_OC1# <6> OK OK C61 1000P_0402_50V7K @ <7> <7> USB20_N2 USB20_P2 USB20_N2 USB20_P2 R65 R64 1 1 @ @ 2 0_0402_5% 2 0_0402_5% 1 2 3 4 USB20_N2_R USB20_P2_R VBUS DD+ GND ME@ 5 6 7 8 GND1 GND2 GND3 GND4 C-K_20267-5K11-02 USB20_P2_R +USB_VCCA @ 1 1 D11 2 2 2 AZ5425-01F_DFN1006P2E2 1 1 D10 2 2 @ AZ5425-01F_DFN1006P2E2 1 D9 2 2 2 1 USB20_N2_R AZ5425-01F_DFN1006P2E2 OK @ USB20_P1_R 7 4 4 USB30_TX_R_N1 USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1 3 3 8 AZ1045-04F_DFN2510P10E-10-9 3 USB30_RX_P1 2 USB30_RX_N1 3 OK OK 4 @ D14 @ 3 DLW21SN900HQ2L_4P 1 USB30_RX_R_P1 2 1 3 L9 D13 1 USB30_TX_R_N1 7 CMM21T-900M-N_4P USB20_N1_R 2 OK USB20_P2_R 2 USB30_RX_R_P1 1 3 2 2 3 9 AZ5425-01F_DFN1006P2E2 4 USB30_RX_R_P1 8 1 4 2 OK @ 1 1USB30_RX_R_N1 1 USB20_P2 1 D12 USB30_RX_R_N1 9 10 USB20_N2_R 2 OK 2 2 1 AZ5425-01F_DFN1006P2E2 L8 USB20_N2 For EMC 4 USB30_RX_R_N1 +USB_VCCA swap @ 9/13 DLW21SN900HQ2L_4P 1 USB30_TX_R_P1 USB30_TX_C_P1 2 2 1 USB30_TX_C_N1 3 3 L10 4 4 1 USB20_N1 4 2 4 3 C63 1 @ 2 470P_0402_50V7K JUSB2 <7> USB30_TX_P1 <7> <7> USB30_TX_N1 USB20_P1 <7> <7> USB20_N1 USB30_RX_P1 <7> USB30_RX_N1 OK 1 2 1U_0603_25V6M USB30_TX_R_N1 swap @ 9/13 L11 USB20_P1 OK C62 1 @ 2 USB20_P1_R OK 3 USB20_N1_R OK CMM21T-900M-N_4P USB30_TX_P1 C64 1 2 .1U_0402_10V6-K USB30_TX_C_P1 R68 1 @ 2 0_0402_5% USB30_TX_R_P1 USB30_TX_N1 C65 USB20_P1 1 2 .1U_0402_10V6-K USB30_TX_C_N1 R69 R70 1 1 @ @ 2 0_0402_5% 2 0_0402_5% USB30_TX_R_N1 USB20_P1_R USB20_N1 USB30_RX_P1 R71 R72 1 1 @ @ 2 0_0402_5% 2 0_0402_5% USB20_N1_R USB30_RX_R_P1 USB30_RX_N1 R73 1 @ 2 0_0402_5% USB30_RX_R_N1 9 1 8 3 7 2 6 4 5 ME@ StdA_SSTX+ VBUS StdA_SSTXD+ GND_DRAIN DStdA_SSRX+ GND_5 StdA_SSRX- GND_1 GND_2 GND_3 GND_4 10 11 12 13 SUYIN_020053GR009M2736L 4 4 For EMC Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 Deciphered Date 2013/08/05 USB2.0/USB3.0 PORT (LEFT) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 A B C D Sheet E 41 of 60 A B C D E F G H SATA HDD Conn. JHDD1 OK<7> OK<7> SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 OK<7> OK<7> 1 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 C66 C67 1 1 2 .01U_0402_16V7-K 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C68 C69 1 1 2 .01U_0402_16V7-K 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N0 SATA_PRX_C_DTX_P0 <6> 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SATA0_DEVSLP SATA0_DEVSLP Need short J3 OK 1 2 3 4 5 6 7 1 +5VS +5VS_HDD @ 1 2 2 JUMP_43X79 +5VS_HDD 1 2 1 C74 1000P_0402_50V7K @ 2 1 C75 .1U_0402_10V6-K @ 2 C76 1U_0603_25V6M @ 1 1 C77 10U_0805_10V6K 2 2 FOR 14" ME@ SATA ODD Conn. GND_1 A+ AGND_2 BB+ GND_3 1 JODD1 OK <7> OK <7> V33_1 V33_2 V33_3 GND_4 GND_5 GND_6 V5_1 V5_2 V5_3 GND_7 DAS/DSS GND_8 V12_1 V12_2 V12_3 OK <7> OK <7> SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 14@ C70 14@ C71 1 1 2 .01U_0402_16V7-K 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_14 SATA_PTX_C_DRX_N1_14 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 14@ C72 14@ C73 1 1 2 .01U_0402_16V7-K 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_14 SATA_PRX_C_DTX_P1_14 OK 1 2 3 4 5 6 7 8 9 10 11 12 13 ODD_DETECT#_R OK GND_1 RX+ RXGND_2 TXTX+ GND_3 +5V_ODD ODD_DA#_R DP +5V_1 +5V_2 MD GND_4 GND_5 GND1 GND2 14 15 SUYIN_127382FB013S255ZL ME@ C78 10U_0805_10V6K @ SUYIN_127043HR022M32QZR_22P-T FOR 15" 2 2 For EMC SATA ODD FFC Conn +5VS to +5V_ODD OK OK OK Need short J4 1 OK OK @ 1 2 2 JODD2 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 15@ C79 15@ C80 1 1 2 .01U_0402_16V7-K 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_15 SATA_PTX_C_DRX_N1_15 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 15@ C81 15@ C82 1 1 2 .01U_0402_16V7-K 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_15 SATA_PRX_C_DTX_P1_15 1 2 3 4 5 6 7 8 9 10 JUMP_43X79 OK<6> +5V_ODD LP2301ALT1G_SOT23-3 D 1 3 1 +3VS G R77 10K_0402_5% Q22 G @ 3 @ S 2N7002KW_SOT323-3 OK <6> 2N7002KW_SOT323-3 1 ODD_DA# APU S0 GPIO 1 C165 AMD Zero PWR ODD 2 R80 1 2 2 3 D 2 ODD_EN# D 1 @ GEVENT is S5 Reserve for APU GEVENT S5 Q21 S 2N7002KW_SOT323-3 GND_1 GND_2 ACES_51524-01001-003 ME@ +3VS 2 G R81 100K_0402_5% 11 12 1 @ D 2 ODD_EN APU S5 GPIO 3 <6> Device Attention/Device Present require GEVENT, but all R79 470_0603_5% @ C87 .01U_0402_16V7-K 1 Q20 1 @ 2 +5V_ODD ODD_DA#_R ODD_DA#_R S 1 2 1 2 ODD_EN# 100K_0402_5% C85 2 R78 3 1 C86 2 1 2 2 G R76 10K_0402_5% @ .1U_0402_10V6-K @ R75 10K_0402_5% @ 10U_0805_10V6K 1 1 1 Q19 ODD_DETECT#_R 2 S 3 1 @ 2 0_0402_5% R74 ODD_DETECT# APU S5 GEVENT APU PH to +3VALW_APU Need check if ODD side only PD to GND. R161 Otherwise require isloate circuit 0_0402_5% @ 2 +5VS .1U_0402_10V6-K +5VALW 1 2 3 4 5 6 7 8 9 10 @ 2 0_0402_5% 4 4 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 2013/08/05 Deciphered Date HDD/ODD CONN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 A B C D E F G Sheet 42 H of 60 3 +3VS 2 +1.5VS 1 +5VA +3VS @ RA2 2 0_0603_5% +3.3VD OK 1 RA8 +3VS 2 0_0402_5% @ +3VALW +5VS 2 0_0402_5% DVDD_IO ACLU5 use +1.5VS @ RA7 1 D 2 0_0603_5% +5VA 2 0_0603_5% +5VD CA1 @ RA10 1 .1U_0402_10V6-K @ RA11 1 OK +3VL 2 RA3 1 @ 2 0_0603_5% RA5 1 @ 2 0_0603_5% RA25 1 AVDD_HP 2 1 OK AVDD_HP 2 1 2 0_0603_5% D Close to Pin28 Close to Pin24 1 Close to Pin3 Close to Pin7 OK DA1 RA17 PLUG_IN RA36 1 2 39.2K_0402_1% 2 33_0402_5% 1 RA18 1 2 RA19 @ 0_0402_5% JSENSE OK 36 40 1 DMIC_CLK_R DMIC_DATA_R .1U_0402_10V6-K 11 1 2 CA13 13 16 +5VD 1 2 20K_0402_1% CA14 1 2 1U_0402_6.3V6K 19 20 CA17 1 2 2.2U_0402_6.3V6M 21 41 MICBIASC MICBIASB PORTB_R_LINE PORTB_L_LINE CLASS-D_REF PORTD_A_MIC PORTD_B_MIC LPWR_5.0 RPWR_5.0 HGNDA HGNDB FLY_P FLY_N AVDD_HP AVEE PORTA_R PORTA_L GND 35 34 MICBIASB OK 33 32 LINE_B_R LINE_B_L 30 31 PORTD_A_MIC PORTD_B_MIC DA2 OK OK RA37 3K_0402_1% OK OK 25 26 RING2_CONN RING3_CONN 24 AVDD_HP OK 23 22 HPOUT_R HPOUT_L RA20 1 RA21 1 RA41@ 0_0402_5% RA39 100_0402_5% RA40 Close 100_0402_5% RA38 3K_0402_1% CA35 10U_0603_6.3V6M 1 2 2 1 1 2 2.2U_0402_6.3V6M CA6 CA5 .1U_0402_10V6-K @RA42 @ RA42 0_0402_5% 1 1U_0402_6.3V6K CA10 OK OK CA9 .1U_0402_10V6-K SPK_R+ SPK_R- LINE_B_L 17 15 1 OK OK LINE_B_R OK 1 SPK_L+ SPK_L- OK MICBIASB LEFT+ LEFTRIGHT+ RIGHT- MUSIC_REQ/GPIO0/PORTC_L_MIC DMIC_CLK/MUSIC_REQ/GPIO0 DMIC_DAT/GPIO1 12 14 +3.3VD 2 C to Pin29 2 OK <45> DMIC_CLK DMIC_DATA JSENSE GPIO1/PORTC_R_MIC AVDD_3.3 VREF_1.65V +5VA 2 1 OK <33> OK <33> PC_BEEP SPKR_MUTE# CX20751-11Z 27 29 28 1 38 37 RA15 5.11K_0402_1% SDATA_IN SDATA_OUT AVDD_3.3 VREF_1.65V AVDD_5V 2 10 39 JSENSE 2 C 6 4 SDATA_IN SYNC 1 OK OK 2 PC_BEEP SPKR_MUTE# BIT_CLK 2 2 HDA_SDIN0 HDA_SDOUT_AUDIO 8 1 3 HDA_SYNC_AUDIO OK<6> 5 HDA_SYNC_AUDIO RA16 1 33_0402_5% HDA_SDOUT_AUDIO 1 BAT54AWT1G_SOT323-3 +3.3VD OK<6> HDA_BITCLK_AUDIO OK 2 1 HDA_BITCLK_AUDIO OK<6> FILT_1.8V VDD_IO VDDO_3.3 DVDD_3.3 FILT_1.8V DVDD_IO 1 OK<6> RESET# 3 7 2 18 Close to Pin27 1 1 2 2 CA36 10U_0603_6.3V6M 2 HDA_RST_AUDIO# 9 HDA_RST_AUDIO# 2 2 2 UA1 OK<6> 1 1U_0402_6.3V6K CA8 RA14 10K_0402_5% BAT54CW_SOT323-3 CA16 close to Pin18 CA17 close to Pin2 1 CA7 .1U_0402_10V6-K PCH_BEEP 2 1 3 2 PC_BEEP1 1 1 OK .1U_0402_10V6-K 1 2 CA2 PC_BEEP CA4 4.7U_0603_10V6-K 2 BEEP# .1U_0402_10V6-K CA3 <44> <6> 1 .1U_0402_10V6-K CA12 4 .1U_0402_10V6-K CA11 5 2 75_0402_1% 2 75_0402_1% OK <45> OK <45> HP_OUTR HP_OUTL +5VD RA22 1 PORTD_A_MIC PORTD_B_MIC 2 1 +3.3VD B Close to Pin11,13,16 2 RA24 1 @ 0_0402_5% 1 2 2 CA19 .1U_0402_10V6-K 1 CA18 .1U_0402_10V6-K 2 CA16 4.7U_0603_10V6-K CA15 4.7U_0603_10V6-K CX20752-21Z_QFN40_5X5 1 HDA_RST_AUDIO# EC_MUTE# RB751V-40_SOD323-2 2 DA4 1 @ 2 0_0402_5% RA4 1 @ 2 0_0402_5% RA6 1 @ 2 0_0402_5% RA9 1 @ 2 0_0402_5% RA12 1 @ 2 0_0402_5% RA13 1 @ 2 0_0402_5% 2 100_0402_5% 2 100_0402_5% CA20 1 CA21 1 2 2.2U_0402_6.3V6M 2 2.2U_0402_6.3V6M OK <45> OK <45> RING3_CONN RING2_CONN RA23 B GNDA Use 250mils wide trace bridging AGND and DGND at codec 2 OK 1 GND RA28 47K_0402_5% RB751V-40_SOD323-2 2 @ DA3 1 RA1 1 1 OK SPKR_MUTE# JSPK1 @ 2 2 @1 1 1 2 3 4 SPK_R+_CONN SPK_R-_CONN SPK_L+_CONN SPK_L-_CONN 1 2 3 4 5 6 470P_0402_50V7K 2 1 CA34 @1 2BLM18PG221SN1D_2P 2BLM18PG221SN1D_2P 2BLM18PG221SN1D_2P 2BLM18PG221SN1D_2P 470P_0402_50V7K 2 1 CA33 @1 2 1 1 1 1 470P_0402_50V7K 2 1 CA32 @1 2 LA1 LA2 LA3 LA4 470P_0402_50V7K 2 1 CA31 2 220P_0402_50V7K CA30 CA26 2 SPK_R+ SPK_RSPK_L+ SPK_L- GND1 GND2 ACES_88231-04001 ME@ 2 @ CA25 1 33P_0402_50V8J CA24 2 @ @ 2 1 33P_0402_50V8J CA23 1 22P_0402_50V8-J CA22 @ 2 22P_0402_50V8-J 22P_0402_50V8-J A 1 2 1 220P_0402_50V7K CA29 HDA_SDOUT_AUDIO 2 HDA_BITCLK_AUDIO RA27 1 @ 27_0402_5% HDA_SDIN0 1 220P_0402_50V7K CA28 HDA_SYNC_AUDIO 2 RA35 1 @ 0_0402_5% DMIC_CLK_R 220P_0402_50V7K CA27 PLUG_IN C15 HDA_RST_AUDIO# 100P_0402_50V8J EC_MUTE# 220P_0402_50V7K <44> C43 OK A For EMI Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 2013/08/05 Deciphered Date Codec_CX20752 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 43 of 60 4 3 2 +3VALW_R 2 0_0402_5% @ <7,9> OK <7> OK <7> OK <7> OK <7> 2 RB751V-40_SOD323-2 1 <7,9> 2 100K_0402_5% CLK_PCI_EC WRST# OK <40> OK <40> 1 EC_RX EC_TX APU_LPC_RST# EC_RX EC_TX APU_LPC_RST# <6> EC_SCI# <6> GATEA20 CE12 1U_0402_6.3V6K<6> 2 KSI[0..7] <45> KSO[0..17] KSO[0..17] C OK OK<45> <52,53> <52,53> <55> Charger, BATT <20,39,5> APU,GPU,Thermal Sensor +3VL<20,39,5> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK1 EC_SMB_DA1 VDDQ_PGOOD EC_SMB_CK2 EC_SMB_DA2 EC_SMB_CK2 EC_SMB_DA2 Change RE27 to 0ohm jump OK <37> OK <41,45> <52,54,56> <6> OK <6> OK <6> 2 0_0402_5% LAN_WAKE# VSTBY0 GPE4 33 35 93 USB_ON# USB_ON# ALW_PWRGD EC_RSMRST# 112 125 PWM LPC 2 128 EC_WAKE# AC_PRESENT DAC2/TACH0B/GPJ2 DAC3/TACH1B/GPJ3 DAC4/DCD0#/GPJ4 DAC5/RIG0#/GPJ5 CE10 2 2 CE11 RE50 10K_0402_5% @ @ max Phase SDV V V V V V D EXTERNAL SERIAL FLASH GPH3/ID3 GPH4/ID4 GPH5/ID5 GPH6/ID6 NC1 NC2 NC3 NC4 SPI Flash ROM AC_IN# LID_SW# UART EGAD/GPE1 EGCS#/GPE2 EGCLK/GPE3 Bus GPIO GPJ1 SSCE0#/GPG2 SSCE1#/GPG0 DSR0#/GPG6 DTR1#/SBUSY/GPG1/ID7 CRX0/GPC0 CTX0/TMA0/GPB2 RI1#/GPD0 RI2#/GPD1 TACH2/GPJ0 TACH1A/TMA1/GPD7 TACH0A/GPD6 L80HLAT/BAO/GPE0 L80LLAT/GPE7 GPIO 24 25 28 29 30 31 32 34 120 124 66 67 68 69 70 71 72 73 78 79 80 81 85 86 87 88 89 90 PWR_LED# <45> OK OK BATT_CHG_LED# <45> OK BATT_LOW_LED# <45> VGA_AC_BATT <20> VGA_AC_BATT EC_FAN_PWM BATT_LEN# SUSP# SUSP# NTC_V ADC1 BATT_TEMP Board_ID RE53 2 @ <51> BATT_TEMP VR_IMVP_IMON OK <52> OK <46,55,56,58> NTC_V 10_0402_5% RE52 0_0402_5% @ <39>OK EC_FAN_PWM BEEP# <43> 2 VCC PS2CLK0/TMB0/CEC/GPF0 PS2DAT0/TMB1/GPF1 GPF2 PS2 GPF3 PS2CLK2/GPF4 PS2DAT2/GPF5 WAKE UP CK32KE/GPJ7 CK32K/GPJ6 ADC0/GPI0 ADC1/GPI1 ADC2/GPI2 ADC3/GPI3 ADC4/GPI4 ADC5/DCD1#/GPI5 ADC6/DSR1#/GPI6 ADC7/CTS1#/GPI7 ADC DAC GINT/CTS0#/GPD5 RTS1#/GPE5 CLKRUN#/GPH0/ID0 2 V V V V V VAD_BID 0 V 0.289 0.538 0.875 0.155 0.664 AVCC PWM0/GPA0 PWM1/GPA1 PWM2/GPA2 PWM3/GPA3 PWM4/GPA4 PWM5/GPA5 PWM6/SSCK/GPA6 PWM7/RIG1#/GPA7 TMRI0/GPC4 TMRI1/GPC6 @ RE27 1 CE9 2 V V V V V typ +5VS +3VS IT8586E/AX LQFP-128L PWRSW# SM XLP_OUT SMCLK1/GPC1 SMDAT1/GPC2 SMCLK2/PECI/GPF6 SMDAT2/PECIRQT#/GPF7 CRX1/SIN1/SMCLK3/GPH1/ID1 CTX1/SOUT1/GPH2/SMDAT3/ID2 CE8 2 1 V AD_BID 0 V 0.250 0.503 0.819 0.148 0.638 minimum trace width 12 mil 74 26 50 92 114 121 127 11 KSI0/STB# KSI1/AFD# KSI2/INIT# KSI3/SLIN# KSI4 KSI5 KSI6 KSI7 KSO0/PD0 Int. K/B KSO1/PD1 KSO2/PD2 Matrix KSO3/PD3 KSO4/PD4 KSO5/PD5 KSO6/PD6 KSO7/PD7 KSO8/ACK# KSO9/BUSY KSO10/PE KSO11/ERR# KSO12/SLCT KSO13 KSO14 KSO15 KSO16/SMOSI/GPC3 KSO17/SMISO/GPC5 110 111 115 116 117 118 94 95 ON/OFF ON/OFF KBRST#/GPB6 SERIRQ/GPM6 LFRAME#/GPM5 LAD3/GPM3 LAD2/GPM2 LAD1/GPM1 LAD0/GPM0 LPCCLK/GPM4 WRST# ECSMI#/GPD4 PWUREQ#/BBO/SMCLK2ALT/GPC7 LPCPD#/GPE6 LPCRST#/GPD2 ECSCI#/GPD3 GA20/GPB5 58 59 60 61 62 63 64 65 36 37 38 39 40 41 42 43 44 45 46 51 52 53 54 55 56 57 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI[0..7] <45> 4 5 6 7 8 9 10 13 14 15 16 17 22 23 126 LPC_FRAME# CE7 2 1 min 2 KBRST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 CLK_PCI_EC CE6 2 1 VAD_BID 0 V 8.2K +/- 5% 0.216 18K +/- 5% 0.436 33K +/- 5% 0.712 4.7K +/- 5% 0.141 24K +/- 5% 0.612 RE51 @ 0_0402_5% 1 <6> <7> RE8 3 VBAT WRST# +3VALW_R DE1 @1 UE1 PWR PH VSTBY1 VSTBY2 VSTBY3 VSTBY4 VSTBY5 VSTBY(PLL) <20> S5 VCORE Change RE6 to 0ohm jump APU 12 2 0_0402_5% 1 1 @ RE6 1 1 .1U_0402_10V6-K +3VALW_EC +3VS RE4 1 +VCCRTC EC_AGND 1 RE34 0K +/- 5% 0 1 2 3 4 5 Board_ID D LPC_FRAME# All capacitors close to EC +3VALW_R .1U_0402_10V6-K CE5 1000P_0402_50V7K EC_AGND 2 100K +/- 1% Board ID RE33 10K_0402_5% @ VCOREVCC 3.3V +/- 5% Vcc RE33 1 1 CE4 .1U_0402_10V6-K 2 HCB1608KF-181T20 2 .1U_0402_10V6-K 2 CE3 1 HCB1608KF-181T20 1 LE2 1 @ .1U_0402_10V6-K 2 +3VALW_R .1U_0402_10V6-K 1 +3VL 0_0603_5% +3VALW .1U_0402_10V6-K LE1 Close EC 2 .1U_0402_10V6-K +3VALW_R 2 0_0603_5% RE3 1 2 RE1 1 +3VALW_EC 1 BORAD ID Config @ TP_CLK RE12 2 1 4.7K_0402_5% TP_DATA RE13 2 1 4.7K_0402_5% 1 5 <52,53> EC_APU_ALWEN <56> ADP_I <53> VR_IMVP_IMON <59> ADAPTER_ID <51> +3VALW_R RE18 1 SUSP# @ 2 100K_0402_5% VR_APU_PWRGD <59> MAINPWON <51,54> H_PROCHOT#_EC ENBKL <33> REP2 PBTN_OUT# RE54 2 TP_CLK TP_DATA @ 10_0402_5% 96 97 98 99 EC_SPI_CS0# EC_SPI_SI EC_SPI_SO EC_SPI_CLK 108 109 LID_SW# 1 2 3 4 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 <56> OK OK 8 7 6 5 +3VALW_R C +3VS 2.2K_0804_8P4R_5% CAPS_LED# <45> EC_VR_ON <59> ACOFF <53> EC_SYS_PWRGD <6> PCH_PWROK can be removed 101 102 103 105 <6> APUALW_PWRGD TP_CLK <45> TP_DATA <45> REP4 1 2 3 4 EC_FAN_SPEED USB_ON# LAN_WAKE# 8 7 6 5 +3VS +5VALW +3VALW_R 10K_0804_8P4R_5% ACIN# LID_SW# 82 83 84 77 100 106 104 107 119 123 18 21 76 48 47 19 20 <53> OK OK <45> EC_ON <54> ADAPTER_ID_ON# PM_SLP_S5# PM_SLP_S5# EC_MUTE# PCH_PWR_EN +3VS <51> <6> <43> OK <46,52> 2 RE25 SYSON <55>OK OK BKOFF# <33> AOAC_ON# <40>OK PM_SLP_S3# <6> SYSON BKOFF# @ 1 VGA_PWROK 0_0402_5% RE11 1 @ 2 10K_0402_5% LPC_FRAME# RE7 1 @ 2 10K_0402_5% ENBKL RE9 1 @ 2 100K_0402_5% ACLU5 ON/OFF RE35 1 @ 2 10K_0402_5% BKOFF# RE36 1 @ 2 10K_0402_5% LID_SW# RE38 1 <19,58,6> +3VL OK NOVO# <45> OK EC_TS_ON# <33> OK EC_FAN_SPEED <39> WLAN_WAKE# <40> OK NUM_LED# <45> EC_FAN_SPEED WLAN_WAKE# EC_FAN_PWM Clock 2 10K_0402_5% SUSP# RE19 1 2 100K_0402_5% SYSON RE21 1 2 100K_0402_5% BKOFF# RE40 1 2 10K_0402_5% ADC1 RE14 1 2 100K_0402_5% 75 VSS2 VSS3 VSS4 VSS5 VSS6 27 49 91 113 122 1 IT8586E-AX_LQFP128_14X14 AVSS B VSS1 B EC_AGND ACIN 1 +3VL @ EC_SPI_CS0# RE45 2 RE42 @ 10K_0402_5% 1 0_0402_5% SPI_CS0# 1 0_0402_5% SPI_SI 1 0_0402_5% SPI_SO 1 0_0402_5% SPI_CLK SPI_CS0# <7> @ RE47 2 2 EC_SPI_SI ACIN# SPI_SI <7> SPI_SO <7> @ EC_SPI_SO RE48 2 EC_SPI_CLK RE49 2 Mirror Core EMI/ESD Req @ +3VL SPI_CLK <7> APU_LPC_RST# CLK_PCI_EC RE2 EC_ON RE55 2 1 @ SYSON 2 10_0402_5% +3VS 1 100K_0402_5% A 1 For factory EC flash H_PROCHOT# OK CE2 10P_0402_50V8J @ +3VL RE43 2 EC_SMB_CK1 EC_SMB_DA1 1 100K_0402_5% RE44 2 @ 1 10K_0402_5% RE46 2 @ 1 10K_0402_5% 1 1 1 1 1 @ IT1 @ IT2 @ IT3 @ IT4 @ IT5 PAD 1 PAD 1 PAD 1 @ IT6 @ IT7 @ IT8 PAD PAD PAD PAD PAD <59> VR_HOT# RE34 1 @ QE1 H_PROCHOT#_EC 5 H_PROCHOT# D 1 S 2 2 2N7002KW_SOT323-3 3 KSI7 KSI6 WRST# 2 CE1 @ 220P_0402_50V7K @ 2 CE13 .1U_0402_10V6-K BATT_TEMP @ CE16 1 2 100P_0402_50V8J ACIN# @ CE17 1 2 100P_0402_50V8J @ CE18 1 2 1U_0402_6.3V6K ON/OFF A 1 CE19 @ .1U_0402_10V6-K 2 2 0_0402_5% G when mirror, GPG2 pull high when no mirror, GPG2 pull low 2 1 Change RE34 to 0ohm jump 1 +3VALW_R EC_MUTE# 1 CE14 47P_0402_50V8J @ <5> Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 Deciphered Date 2013/08/05 EC ITE8586LQFP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 4 3 2 1 Sheet 44 of 60 5 4 3 2 1 ON/OFF switch 1 KSO[0..17] <44> JKB2 2 1 NOVO_BTN# ON/OFF 1 R85 2 0_0402_5% <44> OK CAPS_LED# PWR_CAPS_LED KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1 CAPS_LED# 3 D BAT54CW_SOT323-3 2 @ SW5 R111 100K_0402_5% @ SMT1-05_4P @ R119 1 ON/OFFBTN# J5 1 R114 100K_0402_5% 1 4 1 3 2 6 5 +3VL 2 +3VALW 1 14" 2 0_0402_5% ON/OFF ON/OFF <44> OK 2 @ SHORT PADS 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND1 GND2 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 OK <44> 2 R84 300_0402_5% 27 28 2 R90 300_0402_5% AZ5215-01F_DFN1006P2E2 2 D23 1 KSO[0..17] @ OK KSI[0..7] D15 NOVO# NOVO# +3VS 1 14" 1 2 1 OK 15" 1 <44> 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 NUM_LED# PWR_NUM_LED CAPS_LED# PWR_CAPS_LED KSO17 KSO16 KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1 NUM_LED# TP_PWR TP_CLK TP_DATA JTP1 TP_CLK TP_DATA TP_CLK TP_DATA C116 C115 2 @1 2 OK OK OK TP_P5 TP_P6 100P_0402_50V8J @1 100P_0402_50V8J OK 2 C114 .1U_0402_10V6-K <44> <44> 1 1 2 3 4 5 6 1 2 3 4 5 6 GND1 GND2 D21 7 8 2 ACES_50503-0060N-001 ME@ @ +3VL 1 AZ5215-01F_DFN1006P2E2 1 2 3 GND1 GND2 7 8 ACES_50503-0060N-001 ME@ 2 2 1 1 2 1 2 2 1 1 2 D17 2.2U_0603_10V6-K 1 2 C119 1 2 3 4 5 6 <41,44> OK USB_ON# USB_ON# 4 GND VOUT3 VIN1 VOUT2 KSI0_15 KB_7 KSO0_14 KSO2_15 KB_8 KSI2_14 KSO4_15 KB_9 KSI3_14 KSO7_15 KB_10 KSO5_14 KSO8_15 KB_11 KSO1_14 KSO6_15 KB_12 KSI0_14 KSO3_15 D KB_13 KSO2_14 KSO12_15 KB_14 KSO4_14 KSO13_15 KB_15 KSO7_14 KSO14_15 KB_16 KSO8_14 KSO11_14 KB_17 KSO6_14 KSO10_15 KB_18 KSO3_14 KSO15_15 KB_19 KSO12_14 KSO16_15 KB_20 KSO13_14 KSO17_15 KB_21 KSO14_14 KB_LED_PWR_15 KB_22 KSO11_14 CAPS_LED#_15 KB_23 KSO10_14 VDD_15 KB_24 KSO15_14 NUM_LED#_15 C VIN2 VOUT1 EN/EN 8 +USB_VCCB 7 +3VS 6 5 FLAG AP2820CMMTR-G1_MSOP8 Low Active 2A @ LID_SW# USB_OC2# 1 2 USB_OC2# C120 1000P_0402_50V7K @ OK <6> <7> OK USB20_P0 <7> OK USB20_N0 USB20_P0 R66 USB20_N0 R67 OK USB20_P3 OK USB20_N3 USB20_P3 R86 USB20_N3 R87 <7> <7> <44> OK<43> OK<43> OK @ OK <43> OK <43> OK TP_P6 HP_OUTR HP_OUTL RING2_CONN RING3_CONN <43> PLUG_IN 18 17 16 20_0402_5% USB20_P0_R 15 20_0402_5% USB20_N0_R 14 13 1 20_0402_5% USB20_P3_R 12 @ 1 20_0402_5% USB20_N3_R 11 @ 10 9 8 7 HP_OUTR 6 HP_OUTL 5 4 RING2_CONN 3 2 RING3_CONN 1 PLUG_IN 1 1 @ @ ACES_50505-0184N-P01 20 18 G2 19 17 G1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 @ JUSB3 USB20_N0 1 USB20_P0 4 USB20_P3 1 USB20_N3 4 1 2 4 3 2 USB20_N0_R 3 USB20_P0_R B DT5 1 1 L14 CMM21T-900M-N_4P L15 2 GND2 GND1 EVQPLHA15_4P D24 2 2 GND2 GND1 EVQPLHA15_4P 1 5 A1 A B B1 6 3 4 2 1 A A1 B1 B 2 5 1 1 2 2 5 A1 GND2 GND1 B1 6 4 2 1 1 15@ @ KSO1_15 KB_6 KSI5_14 +USB_VCCB U3 1 JPWRB1 1 2 3 4 5 6 NOVO_BTN# ON/OFFBTN# LID_SW# For EMC 2 3 14@ 6 TP-R 4 TP-L 6 3 5 TP-R SW4 DT3 TP_RIGHT Button OK DT4 2 TP-L 6 2 5 SW3 EVQPLHA15_4P A 1 GND A 4 B GND TP_P6 AZ5215-01F_DFN1006P2E2 4 15@ @ TP_RIGHT Button OK 5 DAT A1 3 GND2 GND1 DAT AZ5215-01F_DFN1006P2E2 B B1 3 14@ EVQPLHA15_4P CLK 6 VDD 2 4 1 CLK B VDD 2 3 1 SW2 DT2 AZ5215-01F_DFN1006P2E2 SW1 For 15" AZ5215-01F_DFN1006P2E2 1 D20 2 TP_P5 1 OK TP_LEFT Button OK AZ5215-01F_DFN1006P2E2 TP_P5 +5VALW AZ5215-01F_DFN1006P2E2 AZ5215-01F_DFN1006P2E2 TP_LEFT Button KSO5_15 KB_5 KSI4_14 1 1 OK For 14" 31 32 Right Side USB2.0 Port X 1 (USB/B) @ 2 AZC199-02S.R7G_SOT23-3 For EMC OK KSI3_15 USB I/O Connector DT1 1 OK 2 R141 1 0_0402_5% KSI2_15 KB_3 KSI6_14 PWR/B Connector 3 2 R160 1 @ 0_0402_5% 2 +5VS 30 GND1 29 GND2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ACES_50504-3041-001 ME@ TP/B Connector +3VS KB_2 KSI7_14 KB_4 KSO9_14 ACES_88514-02601-071 ME@ C 15" KSO0_15 KB_1 KSI1_14 AZ5215-01F_DFN1006P2E2 JKB1 2 R83 100K_0402_5% @ 1 OK <44> KSI[0..7] 2 2 R82 100K_0402_5% D22 K/B Connector +3VALW 2 +3VL @ 1 2 4 3 2 USB20_P3_R 3 USB20_N3_R CMM21T-900M-N_4P For 14" For 15" LED OK <44> PWR_LED# PWR_LED# LED1 1 2 14@ R142 1 2 1.5K_0402_5% +5VALW R143 1 2 470_0402_5% +3VALW LTW-C193TS5 LED4 1 2 15@ LTW-C193TS5 OK <44> BATT_LOW_LED# BATT_LOW_LED# LED2 1 2 14@ LTST-C193KFKT-LC A A LED5 1 2 15@ LTST-C193KFKT-LC OK <44> BATT_CHG_LED# BATT_CHG_LED# LED3 1 2 14@ R144 1 2 1.5K_0402_5% +5VALW LTW-C193TS5 1 Issued Date 2 15@ 2013/08/08 Deciphered Date 2013/08/05 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. LTW-C193TS5 5 Title LC Future Center Secret Data Security Classification LED6 4 3 2 KBD/PWR/IO/LED/TP Conn. Size Document Number Custom Date: 1 Rev 0.4 NM-A281 Friday, February 21, 2014 Sheet 45 of 60 A B C D 2 OK R2 1 SUSP# 2 0_0402_5% @ C180 1U_0402_6.3V6-K 1 1 2 2 6 7 C179 1U_0402_6.3V6-K 2 GND ON2 VIN2_1 VIN2_2 CT2 VOUT2_2 VOUT2_1 C173 1 2 2200P_0402_25V7-K 2 C176 1 2 1000P_0402_50V7K 9 8 2 C142 1U_0603_25V6M J12 @ 1 2 Q6A OK<44,55,56,58> +/- 1.5% 2N7002KDWH_SOT363-6 S C146 10U_0805_25V6K @ R213 @ 470_0603_5% AON6414AL VDS=30V VGS=20V, ID=50A, Rds=8mohm @ VGS=10V VGS(th)=2.5V Max +/-5% 3.6A AON6414AL_DFN8-5 2 +3VALW 1 2 J7 1 1 C145 10U_0603_6.3V6M 2 C147 1U_0603_25V6M +3VALW_APU @ 1 2 2 JUMP_43X79 R188 @ 470_0603_5% LP2301ALT1G_SOT23-3 Id=3.2A @ 3 2N7002KW_SOT323-3 1 Q40 @ 2 SUSP G S 2 Q37 R187 C144 820K_0402_5% 0.01U_0402_25V7K 1 D +VSB D 2 G PCH_PWR_EN#_R 2N7002KW_SOT323-3 3 S 2N7002KW_SOT323-3 2 1 1 3 2 10.95VS_GATE 2 @ R189 1 0_0402_5% 470K_0402_5% 3 S D 2 G SUSP R190 2 1 Q46 @ 2 G 5VS_GATE 2 Q45 R193 2 0.95VS_GATE_R 1 @ 0_0402_5% Q29 2 2 +VSB 1 D R212 C143 820K_0402_5% 0.01U_0402_25V7K 3 2 2 1 1 1 1.8VS_GATE 2 @ R214 1 0_0402_5% 470K_0402_5% 1 R194 2 @ 2 R206 1 0_0402_5% (No symbol) G R211 1 2 @ 0_0402_5% Need change to AON6414AL D 1.8VS_GATE_R 5VS_GATE S @ 2 R210 1 0_0402_5% 2 SUSP S 2N7002KDWH_SOT363-6 Need Short 9m OHM is requried 1 2 3 5 1 5 G C174 @ 0.1U_0402_10V7-K +0.95VALW to +0.95VS +0.95VS 1 Q6B D 1 2 Q41 D 2 G SUSP# 2 JUMP_43X118 Need Short +0.95VALW 1 C175 @ 0.1U_0402_10V7-K +5VS 1 +5VS_LS 15 R159 47_0603_5% SUSP 1 2 10 1 C140 10U_0603_6.3V6M 2 11 TPS22966DPUR_WSON14_2X3 1 1 1 JUMP_43X118 12 36m OHM is requried 1 2 3 4 C141 10U_0805_25V6K @ AON6414AL_DFN8-5 5 1 VBIAS GPAD C177 @ 1U_0402_6.3V6-K AON6414AL VDS=30V VGS=20V, ID=50A, Rds=8mohm @ VGS=10V VGS(th)=2.5V Max +/- 5% 1.5A +1.8VS CT1 1 +1.8VALW to +1.8VS Q39 5 5VSON 2 +1.8VALW 4 +5VALW +5VALW VOUT1_2 VOUT1_1 ON1 2 C178 @ 1U_0402_6.3V6-K 5VSON VIN1_1 VIN1_2 3 1 3 3VSON +0.675VS R157 100K_0402_5% 4 1 2 6 3VSON R156 100K_0402_5% @ +3VS @ 1 2 0_0402_5% @ 1 +3VS_LS 4 R4 1 J11 14 13 2 U13 1 2 2 Need Short VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm +3VALW +5VALW 1 +5VS, C159 ‐‐> 1.5ms +3VS, C160 ‐‐> 2.5ms 1 +VCCRTC OK 1 Load Switch +5VALW To +5VS +3VALW To +3VS +/- 2% E For DisCharge 1 S 2N7002KW_SOT323-3 2 C131 .1U_0402_10V6-K @ +5VALW PCH_PWR_EN#_R R158 1 2 R195 1 PX@ 100K_0402_5% 2 1 R196 120K_0402_5% PX@ 2 OK 2N7002KW_SOT323-3 PX@ 2 C159 .1U_0402_16V7K PX@ PCH_PWR_EN D 2 PCH_PWR_EN G 7m OHM is requried ??? 3 C160 2 PX@ Q30 <44,52> 1 1 C162 1U_0603_25V6M 2 PX@ 2 R208 1 PX@ 100K_0402_5% 1 PXS_PWREN# G S 1 R155 100K_0402_5% @ PCH_PWR_EN# S 2N7002KW_SOT323-3 R162 100K_0402_5% 2 2 C163 2 PX@ 10U_0603_6.3V6M 1 AON6414AL VDS=30V VGS=20V, ID=50A, Rds=8mohm @ VGS=10V VGS(th)=2.5V Max +VSB Q35 3 OK C154 .1U_0402_16V7K PX@ 2 1 D C161 10U_0805_25V6K PX@ 1 AON4304 VDS=30V VGS=20V, ID=18A, Rds=6mohm @ VGS=10V VGS(th)=2.4V Max R163 100K_0402_5% @ 3 +VSB 1 C152 1U_0603_25V6M 2 PX@ 5 +/- 3% 2A 2 100K_0402_5% D Q36 2 PXS_PWREN# R207 G 120K_0402_5% PX@ S 2N7002KW_SOT323-3 PX@ 3 C151 2 PX@ 1 AON6414AL VDS=30V VGS=20V, ID=50A, Rds=8mohm @ VGS=10V VGS(th)=2.5V Max 1 +0.95VGS 1 2 3 10U_0603_6.3V6M C155 2 PX@ 1 Q44 PX@ AON6414AL_DFN8-5 1 1 +0.95VALW 36m OHM is requried 2 2 3 +/- 1.5% +/- 3% 0.5A 4 5 1 +1.8VGS 1 2 3 10U_0603_6.3V6M Q42 PX@ AON6414AL_DFN8-5 4 C153 10U_0805_25V6K PX@ +1.8VALW 10U_0603_6.3V6M +/- 2% @ 1 Reserve for GPU/APU share +0.95V 2 1 +0.95VALW to +0.95VGS 2 Reserve for GPU/APU share +1.8V +1.8VALW to +1.8VGS 1 +3VALW_R Need check all the EN pin and PWR Sequence. OK PXS_PWREN# G 1 D Q5 2 S 2N7002KW_SOT323-3 4 D PXS_PWREN# 2 G G @ 1 2 1 2 2 Q4 R166 470_0603_5% @ @ S 2N7002KW_SOT323-3 @ 3 PXS_PWREN# D 3 PXS_PWREN# 3 <23> R165 470_0603_5% @ 1 2 R171 470_0603_5% @ 4 Q31 +VGA_CORE 1 +0.95VGS 1 +1.8VGS S 2N7002KW_SOT323-3 Issued Date Title LC Future Center Secret Data Security Classification GPU Power Discharger 2013/08/15 Deciphered Date 2013/08/15 DC V TO VS INTERFACE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 A B C D E Sheet 46 of 60 5 4 3 Power Sequence Block need to be update! 2 2 1 SPOK V PU5 D D VGA_PWRGD A1 3 V 2 A5 B7 PBTN_OUT# PM_SLP_S3# PM_SLP_S5# V V V 51_ON# 5 EC B4 11 FCH_PWRGD PLT_RST# V APU_PWRGD 14 APU_RST# CPU C PU7 +VSYSMEM 8a +3VGS QV2 V 7 V SYSON 12 V KBRST# V V 13 PXS_PWREN ON/OFF PQ1 15 B6 V V A4 FCH 6 EC_ON C VGA_PWRGD V V VS EC_RSMRST# V 4 PU401 B1 V B3 B7 +3VALW V PU401 2 V B+ B2 A5 V BATT +1.1VVALW B5 V PU301 BATT MODE A3 VV A2 V VIN V V AC MODE 9 V VR_ON V V V U15 +1.1VS PU8 +1.2VS VDDCI PU11 +VGA_CORE PU13 B VGA V +0.95VGS PU12 8b V +1.8VGS PU6 V V V V PU7 +0.75VS V V V V PU10 +1.5VS V +1.5VGS U14 U13 +3VS VGATE B U12 +5VS V 10 8 V SUSP#,SUSP VGA_PWRGD PU14 +CPU_CORE A A V PU14 +APU_CORE_NB Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 2013/08/15 Deciphered Date Power sequence Block THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 47 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 Deciphered Date Virtual symbol 2013/08/05 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Date: 5 4 3 2 Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 Sheet 1 48 of 60 5 4 pad_sht7p0x6p65b10p66x9p9d2p8 Pad_ct8p0b9p0d2p8 1 Pad_ct8p0b9p0d2p8 H7 HOLEA H8 HOLEA H9 HOLEA H10 HOLEA 1 1 H11 HOLEA H12 HOLEA PAD_SHAPET8P8X8P0B9P0D2P8 PAD_SHAPET8P0X8P75B9P0D2P8 PAD_CT8P0B5P0D4P0 PAD_CT8P0B5P0D4P0 PAD_CT8P0B5P0D4P0 PAD_CT8P0B5P0D4P0 1 H6 HOLEA 1 H5 HOLEA 1 1 1 1 H2 HOLEA H4 HOLEA 1 H3 HOLEA D pad_c2p3d2p3n 1 H1 HOLEA pad_o2p3x2p8d2p3x2p8n 1 pad_o2p3x2p8d2p3x2p8n 1 1 pad_c2p3d2p3n 2 NH5 HOLEA 1 D NH4 HOLEA 1 NH3 HOLEA 1 NH1 HOLEA 3 pad_ct6p0d4p3 Pad_ct6p0b8p0d4p6 PAD_SHAPET5P0X6P0B7P0D2P3 H23 HOLEA H24 HOLEA H21 HOLEA 1 H22 HOLEA 1 H20 HOLEA 1 H17 HOLEA 1 H16 HOLEA 1 1 H15 HOLEA 1 H14 HOLEA 1 H13 HOLEA 1 C 1 C CHASSIS1_GND pad_ct6p0shapeb8p0x6p75d2p3 pad_cb8p0d7p0 PAD_CT6P0shapeb10p04x10p0d2p8 pad_ct6p0b7p0d2p3 pad_shapet6p8x8p0cb8p0d2p5 PAD_CT5P5B6P0D3P3 PAD_CT5P5B6P0D3P3 PAD_CT5P5B6P0D3P3 PAD_CT5P5B6P0D3P3 FD6 GP9 PAD_RT2P21X2P99 @ +3VS 1 2 GP12 PAD_RT2P45X2P5 @ B 1 1 GP8 PAD_RT2P65X2P2 @ 1 GP7 PAD_RT2P65X2P2 @ 1 1 1 1 GP11 PAD_RT2P45X2P5 @ FFC CONN GROUND PAD 1 1 2 C168 .1U_0402_10V6-K @ GP6 PAD_RT2P65X2P2 @ 1 1 1 GP5 PAD_RT2P65X2P2 @ 1 1 GP4 PAD_RT2P65X2P2 @ 1 1 For EMC GP10 PAD_RT2P21X2P99 @ 1 +VGA_CORE GP3 PAD_RT2P65X2P2 @ 1 1 PAD_SHAPET5P0X6P0-U GP2 PAD_RT2P65X2P2 @ 1 1 1 1 1 1 1 PAD_SHAPET5P0X6P0-D GP1 PAD_RT2P65X2P2 @ 1 FD5 1 FD4 1 FD3 B 1 FD2 H18 HOLEA 1 FD1 H19 HOLEA 1 PCB Fedical Mark PAD 1 PAD_CT5P5B8P0D2P5 C169 .1U_0402_10V6-K @ A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/08 Deciphered Date Hole 2013/08/05 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Date: 5 4 3 2 Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 Sheet 1 49 of 60 5 4 3 EN Silergy SY8208CQNC Converter FOR SYSTEM EN Silergy SY8206BQNC Converter FOR SYSTEM B+ D Adaptor EC_ON EC_ON 2 1 +5VLP/ 100mA D +5VALW/5A PGOOD ALW_PWRGD +3VLP/ 100mA Silergy SY8868ABC Converter +3VALW/4A PGOOD ALW_PWRGD +1.8VALW/2.3A FOR APU VDDIO EC_APU_ALWEN C TI BQ24737RGRR Battery Charger Switch Mode SYSON S5 SUSP# S3 C +0.675VS/1.3A FOR DDR Intersil ISL62771HRTZ Switch Mode FOR APU/NB Core EC_VR_ON EN PGOOD PGOOD_NB Silergy SYX198DQNC Converter Battery Li-ion 4S1P/41WH EC_APU_ALWEN ANPEC APL5930KAI-TRG LDO +1.5VSP/150mA FOR APU VDDIO SUSP# EN PGOOD APU Core/20A/25A APU Core NB/13A/17A VR_APU_PWRGD +0.95VS/7.68A FOR APU VDD EN PGOOD +1.35V/11A PGOOD SMBus B Richtek RT8231AGQW Switch Mode EN PGOOD Interisl ISL62771HRTZ Switch Mode B APUALW_PWRGD +VGA_CORE/20A VIDs PXS_PWREN EN FOR GPU VDDC PGOOD VR_VGA_PWRGD A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 Power Diagram THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Date: 5 4 3 2 Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 1 Sheet 50 of 60 4 3 2 RTC_VCC 1 1 JRTC1 PC429 1000P_0402_50V7K 2 @ PL102 HCB2012KF-121T50_0805 1 2 PC428 470P_0402_50V7K 2 ACES_50299-00501-003 ME@ 1 <44> PC427 470P_0402_50V7K ADAPTER_ID 1 ADAPTER_ID PL101 HCB2012KF-121T50_0805 1 2 APDIN1 2 PF1 7A_24VDC_429007.WRML 1 2 APDIN 2 1 2 3 4 5 PC426 1000P_0402_50V7K D 1 2 3 4 5 +3VL +VCCRTC 2 VIN JDCIN1 1 PD1 RB751V-40_SOD323-2 + D 1 5 PR417 2 1 1 2 2 BAT_D 1 PD2 1K_0603_5% @ FDK_ML1220-TT28 @ RB751V-40_SOD323-2 1 2 PR4448 0_0402_5% RTC Battery @ +3VALW C PH1 under CPU botten side : CPU thermal protection at 92+-3 degree C Recovery at 56 +-3 degree C VIN 1 C 2 1 PR419 750_0603_1% PR420 1M_0402_5% 1 PR423 40.2K_0402_1% 2 2 3 1 PD6 AZ5425-01F_DFN1006P2E2 PU403 <44> 1 @ <44,54> MAINPWON PR426 0_0402_5% 2 1 2 OTP_N_003 3 4 VCC TMSNS1 GND RHYST1 OT1 TMSNS2 OT2 RHYST2 8 7 OTP_N_002 6 2 1 PR425 499K_0402_1% 1 ADAPTER_ID_ON# PQ28B 2N7002KDWH_SOT363-6 B PH1 100K_0402_1%_NCP15WF104F03RC @ 5 2 5 G S 2 1 2 PR422 13.7K_0402_1% @ D PR424 1M_0402_5% 2 PC432 0.1U_0402_25V6 2 1 1 ADAPTER_ID B PR29 47K_0402_1% @ @ 4 1 PQ28A 2N7002KDWH_SOT363-6 +3VL 1 1 S +3VALW PC430 0.1U_0402_25V6-K 2 ADAPTER_ID_ON#_G G 1 2 PR421 @ 0_0402_5% 1 2 6 2 2 +5VLP D G718TM1U_SOT23-8 @ <44> NTC_V A A Title LC Future Center Secret Data Security Classification Issued Date 2013/08/15 2013/08/15 Deciphered Date DCIN / RTC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 Sheet 1 51 of 60 4 3 EC_SMB_CK1 EC_SMB_DA1 PL404 HCB2012KF-121T50_0805 1 2 <44,53> <44,53> 1 PC434 0.01U_0402_25V7K D SUYIN_200082GR007G232ZR ME@ +3VALW PD7 @ AZC199-02S.R7G_SOT23-3 For 15 For 14 BATT_TEMP_IN 1 2 BATT_TEMP PD8 @ AZ5215-01F_DFN1006P2E2 <44,53> 1 SUYIN_200082GR007G232ZR ME@ PC433 1000P_0402_50V7K 2 PR429 100K_0402_1% 1 2 EC_SMCA EC_SMDA BATT_TEMP_IN 2 2 100_0402_1% 2 100_0402_1% 2 1 1 1 2 3 4 5 6 7 8 9 2 PR427 PR428 1 EC_SMCA EC_SMDA 1 2 3 4 5 6 7 GND1 GND2 BATT+ 1 D 1 2 3 4 5 6 7 8 9 JBATT2 PL403 HCB2012KF-121T50_0805 1 2 2 1 2 3 4 5 6 7 GND1 GND2 VMB2 VMB PF2 8A_24V_F1206HI8000V024T 1 2 JBATT1 1 3 VMB2 2 1 5 PR430 10K_0402_5% C C PR1 10M_0402_5% 1 2 DC_UVP_2 PU404A AS393MTR-G1_SO8 2 PR440 PJ409 JUMP_43X39 2 1 2 +VSB S B +3VL +3VALW PR4449 100K_0402_1% <44> D PR443 10K_0402_1% 1 2 BATT_LEN# 6 2 S 2N7002KW_SOT323-3 1 <53> 5 G PQ3B 2N7002KDWH_SOT363-6 100K_0402_1% +VSBP 2 3 1 1 PC439 1U_0402_6.3V6K @ 3 PR441 1 2 1K_0402_1% PCH_PWR_EN BATT_OUT 8 4 1 G 2 <44,46> D 2 O1 -_1 PR442 100K_0402_1% 1 2 PQ4 VSBP_1 2 1 ALW_PWRGD 1 <44,54,56> 1 PR439 @ 0_0402_5% 1 2 B PR438 49.9K_0402_1% 2 @ TP0610K-T1-E3_SOT23-3 0.1U_0402_25V6 PC438 22K_0402_1% +_1 1 2 P 3 PQ2 G 2 PR436 10K_0402_1% 1 2 1 PR434 280K_0402_1% PC437 0.1U_0603_25V7-M +3VALW 4 1 1 2 VSBP_3 PC435 0.01U_0402_25V7K 2 +VSBP 2 0.22U_0603_25V7K 2 PC436 2 1 PR435 100K_0402_1% 2 1 PR437 1 VSBP_2 1 1 VMB2 3 B+ +3VALW 100K_0402_1% PR433 +5VALW PR432 100K_0402_1% 1 2 PR431 @ 0_0603_5% 1 2 D 2 G S 1 PQ3A 2N7002KDWH_SOT363-6 A A Title LC Future Center Secret Data Security Classification Issued Date 2013/08/15 2013/08/15 Deciphered Date BATTERY CONN/OTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 Sheet 1 52 of 60 5 4 3 2 1 B+ Charge Option() bit[8]=1 P3 1 Reserve for EMC request DISCHG_G PR56 47K_0402_1% 1 2 1 DISCHG_G-1 1 P2-1 1 1 2 1 737_VCC PC33 0.1U_0402_25V6-K 737_SCL 9 PR67 0_0402_5% 2 @ @ EC_SMB_DA1 PR69 0_0402_5% 1 2 1 5 6 7 8 PQ11 GND ACP ACDET AO4466L_SO8 BTST ACOK REGN 17 PR66 2.2_0603_5% 1 2 BST_CHG PC36 0.047U_0603_25V7-K 2 1 4 16 PU4 SCL HIDRV 18 DH_CHG 19 LX_CHG 15 DL_CHG PL3 4.7UH_PCMB063T-4R7MS_5.5A_20% 1 2 CHG BQ24737RGRR_VQFN20_3P5X3P5 737_SDA 8 SDA PHASE 1 2 1 BATT+ PC40 1500P_0402_50V7K 2 3 2 1 1 2 SRP SRN 5 6 7 8 4 SRP_1 13 3 PR71 2.2_0805_5% AO4466L_SO8 2 2 2 PR76 6.8_0603_5% PR75 316K_0402_1% PC42 0.1U_0402_25V6-K 1 1 PC41 0.1U_0402_25V6-K 2 737_SRP B 1 +3VL 4 2 PR77 10_0603_5% 737_ILIM PR78 90.9K_0402_1% B PQ12 21 1 PR74 40.2K_0402_1% 2 SRN_1 12 CMPIN 4 ILIM BM# 11 1 PAD PR70 0.01_1206_1% 1 1 737_ILIM LODRV 2 4 PR72 0_0402_5% 1 2 BM# PQ27B 2N7002KDWH_SOT363-6 S @ 10 2 D 5 G BATT_OUT BATT_TEMP IOUT 1 3 PC37 100P_0402_50V8J <44,52> 7 ADP_I ADP_I PACIN PQ26A 2N7002KDWH_SOT363-6 3 2 1 5 CMPOUT 6 ACPRN ACN VCC 737_ACDET 1 <44> 2 G S C EC_SMB_CK1 PQ29A 2N7002KDWH_SOT363-6 D 2 1 14 3 2 1 PR64 390K_0603_1% PR65 59K_0402_1% 1 2 PC35 0.1U_0402_25V6-K 1 2 PACIN_P PR62 1M_0402_5% PC34 1U_0603_25V6M 2 PD5 RB751V-40_SOD323-2 2 1 20 PQ29B 2N7002KDWH_SOT363-6 2 PD4 1SS355_SOD323-2 PC39 10U_0805_25V6K 2 1 1 D 4 <44,52> 1 PACIN_N 1 S <44,52> 5 S VIN S D D PC38 10U_0805_25V6K 2 1 6 PR68 10K_0402_5% 1 2 ACOFF-1 2 G ACOFF BQ24737_VDD 1 5 G PACIN_G <44> 1 PC31 1U_0603_25V6M 2 1 PR58 200K_0402_1% G 2 3 PR63 47K_0402_1% 1 2 PACIN C <52> PQ30A 2N7002KDWH_SOT363-6 P2-2 4 G S 2 PQ30B 2N7002KDWH_SOT363-6 S BATT_OUT PC32 0.1U_0402_25V6-K 2 2 PD3 1SS355_SOD323-2 4 D PR60 68K_0402_1% 2 PQ26B 2N7002KDWH_SOT363-6 PR61 10_1206_5% 2 1 6 2 5 G PC30 0.1U_0402_25V6-K 1 2 6 P2 3 D PC29 0.1U_0402_25V6-K 1 1 PR59 20K_0402_1% 1 3 P2_G1 PQ10 LTC015EUBFS8TL_UMT3F-3 PR57 10K_0402_1% 3 2 VIN 2 PC24 0.1U_0402_25V6-K D 2 2 8 7 6 5 1 PC44 10U_0805_25V6K @ 4 PC45 10U_0805_25V6K @ 2ACOFF-1 737_ACN PC28 2200P_0402_50V7K 737_ACP PQ8 AO4407AL_SO8 1 2 3 PC27 4.7U_0805_25V6-K 1 2 3 PC26 4.7U_0805_25V6-K 1 2 1 1P2_G2 2 PL905 HCB2012KF-121T50_0805 1 2 PC23 10U_0805_25V6K @ PR55 200K_0402_1% 1 2 4 PC25 4.7U_0805_25V6-K 1 2 2 3 2 1 2 1 PQ9 LTA044EUBFS8TL_UMT3F-3 PR54 200K_0402_5% PC21 10U_0805_25V6K @ 1 PC22 2200P_0402_50V7K 1 2 1 4 4 D PR53 0.01_1206_1% 2 2 PC20 0.1U_0402_25V6-K 1 2 1 2 1 1 PJ2 @ JUMP_43X118 8 7 6 5 2 1 2 3 2 PQ7 SI4483_SO8 1 2 3 1 P2 PQ6 AO4407AL_SO8 8 7 6 5 2 VIN 737_SRN 2 1 +3VALW PR4447 10K_0402_5% PC43 0.1U_0402_25V6-K 2 1 ACIN# <44> BQ24737_VDD 1 1 2 G PQ906 2N7002KW_SOT323-3 2 3 1 2 D 10K_0402_1% PR83 10K_0402_1% PR84 47K_0402_1% 1 PR4446 S 6 1 2 PACIN D 2 2 G PQ27A 2N7002KDWH_SOT363-6 S 1 ACPRN PR88 12K_0402_1% A A Modified for B+ voltage step ACPRN PR334 0_0402_5% 1 2 @ ACIN# Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 CHARGER THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Date: 5 4 3 2 Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 1 Sheet 53 of 60 5 4 B+ 3 2 1 +3VALW @ PJ401 PC409 4.7U_0603_6.3V6K 2 2 1 2 PC410 680P_0402_50V7K @ 1 PC411 0.01U_0402_25V7K 1 +3VALW_P 2 5 SY8206BQNC_QFN10_3X3 2 PR404 4.7_0603_5% PJ402 1 1 2 2 JUMP_43X79 PC441 2200P_0402_25V7-K +3VLP @ 1 +3VALW_P D @ PC440 0.1U_0402_25V6 LDO +3VLX +3VALW PL401 2.2UH_PCMB063T-2R2MS_8A_20% 1 2 PC407 22U_0805_6.3V6M 2 1 OUT FB 10 4 PR444 PC403 2.2_0603_5% 0.1U_0603_25V7-M 1 2 1 2 PC406 22U_0805_6.3V6M 2 1 EN1 +3VBS PC405 22U_0805_6.3V6M 2 1 3 LX 6 1 2 PC408 @ 0.1U_0402_25V6 RB751V-40_SOD323-2 @ GND 1 PR405 1M_0402_5% 2 1 MAINPWON BS 2 1 1 PD15 +3VALW_FB PG IN PC404 22U_0805_6.3V6M 2 1 9 +3VALW_EN EN2 +3V_PWRGD 2 8 2 1 1 1 PR411 1M_0402_5% @ PR403 2.2K_0402_5% 1 2 EC_ON TDC :4A OCP :8A PU401 7 2 D 1 1 2 PC402 0.1U_0402_25V6 2 2 JUMP_43X79 PC421 10U_0805_25V6K 2 1 1 2 PC401 10U_0805_25V6K 1 +3VLP +3VL PJ403 @ JUMP_43X39 1 2 1 2 2 PR407 1K_0402_1% C C B+ @ +5VALW PJ405 PC413 10U_0805_25V6K +5VALW_P B 1 2 PC425 6800P_0402_25V7-K 1 PC424 680P_0402_50V7K @ PC443 2200P_0402_25V7-K SY8208CQNC_QFN10_3X3 PC442 0.1U_0402_25V6 2 1 1 7 PC420 22U_0805_6.3V6M 2 1 +5VLP @ PR406 4.7_0603_5% PJ406 +5VALW_P PC419 22U_0805_6.3V6M 2 1 LDO 4 +5VALW PL402 3.3UH_PCMB063T-3R3MS_6.5A_20% 1 2 PC418 22U_0805_6.3V6M 2 1 FB +5VLX PC417 22U_0805_6.3V6M 2 1 OUT 10 PR4445 PC415 2.2_0603_5% 0.1U_0603_25V7-M 1 2 1 2 2 LX EN +5VBS 2 RB751V-40_SOD323-2 @ VCC 6 2 3 BS 1 1 2 +5VFB PG GND +5V_PWRGD 1 MAINPWON 1 1 2 MAINPWON 1U_0603_25V6M +5VALW_EN PR413 1M_0402_5% 2 PD16 <44,51> PC422 0.1U_0402_25V6 @ 5 IN 2 2 PR412 2.2K_0402_5% 1 2 1 EC_ON 1 EC_ON 8 9 PC416 1 2+5VVCC <44> TDC :5A OCP :11A PU402 +5V_VIN PC423 4.7U_0603_6.3V6K 1 2 1 2 2 PC412 10U_0805_25V6K 2 2 1 1 PC414 0.1U_0402_25V6 1 JUMP_43X79 2 @ 2 1 1 JUMP_43X118 B 2 PR416 1K_0402_1% 2 +3VALW +3V_PWRGD 1 PR408 100K_0402_5% PR409 0_0402_5% 1 2 ALW_PWRGD <44,52,56> @ +5V_PWRGD PR410 0_0402_5% 1 2 @ A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 2013/08/15 Deciphered Date PWR_3VALW/5VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 54 of 60 A B C D TDC :11A OCP :14A 2 18 2 PC508 0.1U_0402_10V6-K 21 1 1 PAD VTTGND PC507 10U_0603_6.3V6M 2 +0.675VSP 20 BOOT +0.675VSP VTT +1.35VP 19 1 2 13 11 CS PR507 2.2_0603_5% 1 2 1 1 0.22U_0603_25V7K 17 VTTREF 15 DL_1.35V LGATE PGOOD 10 S3 7 S5 S3_1.35V B+_1.35V 8 FB_1.35V S5_1.35V 2 PR995 10K_0402_1% 9 6 1 2 3 1 @ 1 PC512 680P_0402_50V7K PR504 887K_0402_1% 1 2 TON_1.35V FB 1 VDDQ TON VDD 5 2 @ +0.675VSP 3 4 12 VTTREF_0.675V VTTREF_0.675V PR510 5.1_0603_5% 2 1 +5VALW 1 5 2 PQ502 AON6414AL_DFN GND RT8231AGQW PHASE 4 PR994 7.68K_0402_1% 2 PC511 0.033U_0402_16V7K 1 2 PR503 100K_0402_1% 1 2 2 16 LX_1.35V PR508 @ 4.7_0603_5% 1 2 VTTSNS PU501 1 2 2 PC516 470P_0402_50V7K + PC509 330U_2.5V_M PC515 0.1U_0402_25V6 2 1 PC514 2200P_0402_25V7-K 2 1 1 UGATE 1 2 3 DH_1.35V PL501 0.68UH_PCMB063T-R68MS_16A_+-20% 1 2 +1.35VP 2 PC506 1 2 4 +0.675VSP TDC :1.3A PR506 237K_0402_1% VLDOIN PQ501 AON6414AL_DFN PGND +1.35V 14 5 +3VALW PR511 @ 100K_0402_1% 2 1 PR512 100K_0402_1% 1 2 VID 1 2 PC513 10U_0805_25V6-K 1 2 1 PC505 10U_0805_25V6-K 2 1 2 1 @ JUMP_43X79 PC504 2200P_0402_25V7-K 1 B+_1.35V PC503 0.1U_0402_25V6 2 1 1 PJ501 2 PC501 10U_0603_6.3V6M +1.35VP B+ PC510 1U_0402_10VA-K 2 +3VALW VDDQ_PGOOD <44> PJ502 2 2 1 1 @ JUMP_43X118 <44,46,56,58> PR501 0_0402_5% 1 2 SUSP# PJ504 2 +1.35VP @ 2 1 1 +1.35V @ JUMP_43X118 3 1 3 2 S3_1.35V PJ503 1 SYSON 2 1 1 +0.675VS @ JUMP_43X39 PC502 0.1U_0402_10V6-K PR505 0_0402_5% 2 S5_1.35V 2 <44> 2 +0.675VSP 2 1 PR513 @ 0_0402_5% 1 @ PC517 0.1U_0402_10V6-K 4 4 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 1.35VS/+0.675VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 A B C D Sheet 55 of 60 A B C D 2 +3VALW PR601 10K_0402_5% OUT PR602 4.7_0603_5% @ 10 GND FB 7 PC606 680P_0402_50V7K @ 1 2 SS 3 1 PC607 .1U_0402_10V6-K @ PJ602 2 2 1 1 +1.8VALW JUMP_43X79 PC629 0.1U_0402_25V6 EN 8 1 PR605 1M_0402_5% PR604 0_0402_5% 2 2 1 EC_APU_ALWEN 4 EN_1.8VSP 6 2 ALW_PWRGD LX3 +1.8VSP PC604 22U_0805_6.3V6M 2 1 PR623 0_0402_5% 1 2 @ 1_8VS_LX 5 PC628 22U_0805_6.3V6M 2 1 1 2 1 LX2 2 LX1 PC631 22U_0805_6.3V6M 2 1 VIN 1 PU601 1 TDC :2.3A OCP :3.8A PL601 1UH_PH041H-1R0MS_3.8A_20% 1 2 1 2 2 1 JUMP_43X79 @ +1.8VALW 9 1_8VS_PVIN PG 1 PC602 22U_0805_6.3V6M 1 PC601 22U_0805_6.3V6M 2 1 2 PC630 0.1U_0402_10V6-K 2 1 2 1 1_8VS_PG PJ601 +3VALW 1 SY8868QMC_QFN10_2X2 PC663 .1U_0402_10V6-K 2 @ PR625 200K_0402_1% 1 2 1 1_8VS_FB PR655 100K_0402_1% 1 2 2 PC603 22P_0402_50V8-J +5VALW 1 +1.5VS TDC :150mA EC_APU_ALWEN ALW_PWRGD EC_APU_ALWEN PR622 0_0402_5% 1 2 @ PR612 0_0402_5% 1 2 +1.5VS 2 FB PR608 21.5K_0402_1% 5332_FB PC610 10U_0603_6.3V6M PR610 24K_0402_1% 2 +3VS 0.95VS_EN 1 <44> ALW_PWRGD 1 1 PC611 0.1U_0402_10V6-K <44,52,54> 1 2 @ 2 1 PR611 100K_0402_5% @ PR609 0_0402_5% 1 2EN_1_5VSP SUSP# EN POK 2 PC609 4.7U_0603_6.3V6K 2 JUMP_43X39 2 <44,46,55,58> 8 7 +1.5VSP 3 4 VOUT1 VOUT2 1 2 JUMP_43X79 VCNTL VIN TP 1 6 5 9 5332_VIN PJ603 @ 2 @ 1 1 1 1 2 1 PJ606 2 +3VALW 2 PU602 APL5930KAI-TRG_SO8 GND PC608 1U_0402_6.3V6K 2 2 @ 2 3 PC612 .1U_0402_10V6-K @ 3 +0.95VALW PU603 SYX198DQNC B+ TDC :7.68A OCP :12A PJ604 PC624 4.7U_0603_6.3V6K PR618 20K_0402_1% PC623 2200P_0402_25V7-K PC622 0.1U_0402_25V6 2 1 1 PC627 330P_0402_50V8J PC626 680P_0402_50V7K @ PC621 22U_0805_6.3V6M 2 1 PC625 4.7U_0603_6.3V6K 2 +3VALW 0.95VS_LDO 2 2 +0.95VALWP PR617 1K_0402_1% APUALW_PWRGD +0.95VALW PJ605 2 2 1 1 JUMP_43X118 1 2 <44> 5 PC620 22U_0805_6.3V6M 2 1 LDO PC618 22U_0805_6.3V6M 2 1 PG +0.95VALWP PR615 4.7_0603_5% @ 1 2 PR616 1M_0402_5% @ 0.95VS_LX 7 PC617 22U_0805_6.3V6M 2 1 BYP 20.95VS_ILNT PR614 @ 100K_0402_5% 10 4 1 LX FB ILMT 2 GND PL602 0.68UH_PCMB063T-R68MS_16A_+-20% 1 2 1 3 PR624 PC613 0_0603_5% 0.1U_0603_25V7-M 2 1 2 0.95VS_BS1 2 9 1 6 2 BS 1 EN 1 2 PC615 10U_0805_25V6K PC614 10U_0805_25V6K 2 1 IN 2 1 8 1 +3VALW 2 2 JUMP_43X79 @ 1 B+_0.95VS 2 1 1 1 1 2 PC616 0.1U_0402_25V6 2 PR620 10K_0402_5% @ 1 1 0.95VS_FB +3VALW 2 PR621 34K_0402_1% 4 4 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 +1.35VS_VGA/+1.5VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 A B C D Sheet 56 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 57 of 60 5 4 3 2 1 +VGA_B+ PX@ PL804 HCB2012KF-121T50_0805 1 2 PC816 0.1U_0402_25V6 PR837 @ 32.4K_0402_1% 1 2 @ PX@ PC1185 22U_0805_6.3V6M 1 2 PC1184 22U_0805_6.3V6M 1 2 2 2 @ +VGA_CORE 1 PR842 PX@ PC825 30K_0402_1% 150P_0402_50V8-JPX@ 1 2VGA_FB_1 1 2 1 1 2 1 2 PX@ B PX@ PC1255 330P_0402_50V8J PX@ PC815 330U_D2_2V_Y 2 1 2 PX@ VSUM- 1 PX@ PR844 PX@ PC827 PX@ 2K_0402_1% 680P_0402_50V7K 2 1VGA_FB_3 1 2 PR293 10_0402_1% 2 1 PX@ 2 PC1182 22U_0805_6.3V6M PC824 0.22U_0402_10V6K @ PR841 PX@ 619_0402_1% 1 2 PC822 PX@ 100P_0402_50V8J 1 2 PR831 PX@ 3.65K_0402_1% PC1183 22U_0805_6.3V6M 2 PC806 330U_D2_2V_Y 2 ISEN2 PC826 0.033U_0402_16V7K 1 2 1 2 PC828 0.033U_0402_16V7K VSUM+ PX@ PR840 10K_0402_5% 1 1 @ PC821 PX@ PR836 PX@ 100P_0402_50V8J 499_0402_1% 1 2 VGA_FB_2 1 2 PC823 PX@ 330P_0402_50V8J 2 1 1 2 1 2 1 2 PH802 10K_0402_NTC PX@ 2 PR843 11K_0402_1% PX@ 2 2 PR838 2.61K_0402_1% PX@ 1 1 PR835 PX@ 1.02K_0402_1% 1 2 VSUM- 1 2 PR830 PX@ 10K_0402_1% 1 2 PC817 680P_0402_50V7K @ ISEN1 PC819 0.22U_0402_10V6K PX@ PC812 10U_0805_25V6K 2 1 + PR828 10_0402_1% 1 4 1 PR827 4.7_0603_5% @ 2 VGA_LGATE2 PC810 10U_0805_25V6K 2 1 1 2 PC814 PX@ 0.22U_0603_25V7K 2 PX@ 2BOOT2_R 1 1 1 PX@ 5 PR826 VGA_BOOT2 PX@ PL802 0.36UH_PCMB063T-R36MS_20A_20% 1 2 PX@ VGA_PHASE2 ISEN2 PC818 0.22U_0402_10V6K PX@ PC805 330U_D2_2V_Y 1 PX@ 3 2 1 <19,6> B 1 PX@ VSUM+ VR_VGA_PWRGD 2.2_0603_5% VSUM- PC803 10U_0805_25V6K 2 1 5 4 VGA_UGATE2 +3VGS PR829 @ 10K_0402_5% 1 PR834 2 10K_0402_5% @ PX@ C PC813 PX@ 0.1U_0402_25V6-K PC820 PX@ 0.1U_0402_25V6 1 2 PR810 PX@ 10_0402_1% + 2 +VGA_B+ PQ804 AON6554_DFN PX@ 2 PC802 10U_0805_25V6K 2 1 PC801 0.1U_0402_25V6 2 1 3 2 1 PR824 100K_0402_1% PX@ 1 2 1 PC809 1U_0603_25V6M PX@ PQ803 AON6414AL_DFN PX@ TP 2 VGA_COMP VGA_FB VGA_ISUMN PC808 1U_0603_25V6M PX@ VGA_NTC +5VS +5VS 3 2 1 2 PR825 10.7K_0402_1% PX@ PR823 130K_0402_1% PX@ 2 2 PH801 470K_0402_3%_NCP15WM474E03RC PX@ PR804 PX@ 3.65K_0402_1% @ 1 1 VGA_NTC_1 1 2 VGA_BOOT1 PR806 10K_0402_1% PX@ VSUM+ 1 21 2 VGA_UGATE1 PC807 680P_0402_50V7K @ 1 22 + ISEN1 VGA_PHASE1 +VGA_CORE 1 2 23 1 VGA_LGATE1 PR814 0_0402_5% 2 TDC :20A OCP :35A PX@ PR809 4.7_0603_5% @ 2 24 1 PR816 1 2 1_0603_5% PX@ 1 2 VGA_NTC PQ802 AON6554_DFN PX@ VGA_VDD +3VGS PR821 PX@ 27.4K_0402_1% 1 2 2 5 VGA_VDDP 25 +VGA_CORE PL801 0.36UH_PCMB063T-R36MS_20A_20% 1 2 PX@ 3 2 1 VGA_LGATE2 26 D 1 27 2 VGA_PHASE2 1 VGA_UGATE2 41 COMP PGOOD 20 19 18 PR822 1.91K_0402_1% PX@ FB BOOT1 VGA_BOOT2 28 PX@ PC811 0.1U_0402_25V6 2 1 UGATE1 IMON PQ801 AON6414AL_DFN PX@ 5 PWROK 30 29 2 1 2 32 PR802 PX@ 10K_0402_5% BOOT_NB 33 PHASE_NB UGATE_NB 31 PR801 PX@ 10K_0402_5% 2 1 35 34 LGATE_NB COMP_NB PGOOD_NB PR848 10K_0402_5% 2 1 38 37 36 39 PHASE1 RTN @ ENABLE 1 PC831 .1U_0402_10V6-K PX@ LGATE1 NTC 1 PR820 0_0402_5% @ ISL62771HRTZ_TQFN40_5X5 VSEN 10 SUSP# VDD SVT ISUMN 9 VDDIO 17 2 VGA_PWROK 1 8 VDDP 16 VGA_ENABLE PR819 0_0402_5% 1 2 LGATE2 SVD ISUMP 7 VR_HOT_L 15 6 +VDDIO_GPU +3VGS <19,44,6> 2 <44,46,55,56> 5 PR803 PX@ 2.2_0603_5% 1 2 BOOT1_R 1 PC804 PX@ 0.22U_0603_25V7K 4 VGA_LGATE1 BOOT2 PX@ VGA_PHASE1 VGA_BOOT1 PHASE2 11 PXS_PWREN 4 VGA_VRHOT_L PR849 0_0402_5% PX@ 2 1 SVC 2 <23,6> PR818 20K_0402_1% PX@ 2 1 20_0402_5% @ GPU_SVD 1 C <20> PR812 10K_0402_1% PX@ 4 VGA_UGATE1 UGATE2 14 1 PR811 GPU_VR_HOT# IMON_NB ISEN1 GPU_SVC NTC_NB ISEN2 3 2 <20> 2 13 <20> 1 12 PX@ 100K_0402_1% 1 2 PR807 PX@ 100K_0402_1% 1 2 VSEN_NB PR805 ISUMN_NB PU801 ISUMP_NB 40 @ FB_NB PR847 0_0402_5% 2 1 @ B+ PX@ PL805 HCB2012KF-121T50_0805 1 2 D PX@ PR294 10_0402_1% 2 1 PX@ PC830 1000P_0402_50V7K PX@ A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 +VGA_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 58 of 60 PC906 + 2 1 + 2 +APU_CORE_NB D 1 3 +APU_CORE_NB 2 1 2 2 + 2 PR914 10_0402_1% 1 + 2 @ PC1013 22U_0805_6.3V6M 1 VSUMN_NB + PC916 680P_0402_50V7K @ 1 PC1012 22U_0805_6.3V6M 2 1 VSUMP_NB 1 PC1011 22U_0805_6.3V6M 2 1 1 3 2 1 LGATE_NB PR915 422_0402_1% 1 2VSUMN_NB_11 4 2 PC1017 330U_D2_2V_Y 2 1 5 PC913 0.22U_0603_25V7K 4 LGATE_NB 1 PR911 3.65K_0402_1% PR910 4.7_0603_5% @ 2 COMP_NB PQ902 AON6554_DFN 2 PGOOD_NB 1 VSUMN_NB FB_NB PC915 0.1U_0402_25V6 @ PR909 2.2_0603_5% 1 2 BOOT_NB_R1 2 PR912 11K_0402_1% VSEN_NB 1 PC914 0.01U_0402_25V7K 2 1 2 PH901 10K_0402_NTC 1 2 1 2NB_NTCS 2 PR908 2.61K_0402_1% BOOT_NB TDC :13A OCP :22A PL904 0.36UH 20% PCMB063T-R36MS 20A PHASE_NB VSUMP_NB B+ PL807 HCB2012KF-121T50_0805 1 2 68U_25V_M 1 68U_25V_M PC910 1 2 1 4 UGATE_NB 0.01U_0402_25V7K PC905 2 PC908 47P_0402_50V8J 2 1 PQ901 AON6414AL_DFN 1 PL806 HCB2012KF-121T50_0805 1 2 2200P_0402_50V7K PC909 1 2FB_NB_1 1 2 PR907 PC907 499_0402_1% @ PC911 100P_0402_50V8J 330P_0402_50V8J 1 2 PR904 @ 32.4K_0402_1% 1 PR903 82K_0402_1% 1 PR902 1.58K_0402_1% 2 10U_0805_25V6K PC904 1 PR906 0_0402_5% CPU_B+ PC902 150P_0402_50V8-J 2FB_NB_2 1 2 1 1 2 2 +APU_CORE_NB D 2 2 APU_VDDNB_SEN_H 1 3 2 1 <5> 1 PR901 2K_0402_1% 10U_0805_25V6K PC903 1FB_NB_3 2 2 5 2 PC901 680P_0402_50V7K PR905 100_0402_1% 1 2 3 PC1016 330U_D2_2V_Y 4 PC1015 330U_D2_2V_Y 5 PHASE_NB UGATE_NB 1 3 2 1 2 VSUM+_APU 1 PR936 3.65K_0402_1% PC935 680P_0402_50V7K 1 2 VSUM-_APU @ 1 3 2 1 ISEN1_APU 2 PC931 47P_0402_50V8J 1 1 + 2 1 + 2 PC1026 22U_0805_6.3V6M PC1025 22U_0805_6.3V6M 2 1 PC1020 22U_0805_6.3V6M 2 1 PC1019 22U_0805_6.3V6M 2 1 PC1021 22U_0805_6.3V6M 2 1 B 2 PR944 @ 32.4K_0402_1% 1 2APU_FB_1 1 2 PR949 PC934 267K_0402_1% 150P_0402_50V8-J PC1027 22U_0805_6.3V6M PC1024 22U_0805_6.3V6M 2 1 PC1023 22U_0805_6.3V6M 2 1 PC1022 22U_0805_6.3V6M 2 1 62771_SVC_A PC1010 22U_0805_6.3V6M 2 1 <5> PR269 @ 1K_0402_1% PC1009 22U_0805_6.3V6M 2 1 APU_VDD_SEN_L 2 2 @ 62771_SVD_A 62771_SVT_A 1 1 1 A PR272 @ 220_0402_5% 2 PR271 220_0402_5% @ PR273 220_0402_5% @ 2 2 <5> 1 PR955 2 10_0402_1% APU_VDD_SEN_H 2 1 PC939 0.1U_0402_25V6 A 1 PR953 2 0_0402_5% PC940 PR954 330P_0402_50V8J 0_0402_5% @ 2 1 PR268 PC1008 22U_0805_6.3V6M 2 1 PR267 @ 1K_0402_1% PC1007 22U_0805_6.3V6M 2 1 PC936 680P_0402_50V7K +APU_CORE 1 PR951 2K_0402_1% PR952 10_0402_1% 2 1 +1.35V 2 2 1APU_FB_3 1 1 2 2 1 2 PR948 2.37K_0402_1% @ 1 1 2 APU_FB_2 1 2 PC930 PR942 100P_0402_50V8J 499_0402_1% 2 PR947 @ 10K_0402_5% 1 1 2 @ PC932 0.22U_0402_10V6K 1 PC937 0.047U_0402_25V7K 2 1 1 1APU_R_B 1 1K_0402_1% VSUM+_APU PR950 11K_0402_1% PC938 0.1U_0402_25V6 2 1 1 2 PC933 330P_0402_50V8J 2 1 PR943 499_0402_1% 1 2 PR945 2.61K_0402_1% PH904 10K_0402_NTC + 2 PC929 0.1U_0402_25V6 1 2 2 VSUM-_APU 2 1.1V 1.0V 0.9V 0.8V(Default) 1 0 1 0 1 1 PR939 10_0402_1% PR941 10K_0402_5% Boot Voltage 2APU_NTCS 2 0 0 1 1 +APU_CORE PC1003 22U_0805_6.3V6M 4 LGATE1_APU PQ905 AON6554_DFN 3 PC1002 22U_0805_6.3V6M 2 1 4 4 2 PC1001 22U_0805_6.3V6M 2 1 2 2 PC927 0.22U_0603_25V7K 1 PR935 4.7_0603_5% @ 2 PC1006 330U_D2_2V_Y 2 1 PR934 2.2_0603_5% 1 2BOOT1_R_A 1 BOOT1_APU PQ904 AON6554_DFN SVD PC1018 22U_0805_6.3V6M 2 1 2 2 0.01U_0402_25V7K PC925 1 PHASE1_APU PC1005 330U_D2_2V_Y <44> 1 VR_APU_PWRGD PC1004 330U_D2_2V_Y PR957 0_0402_5% 2 @ 5 1 LGATE1_APU SVC TDC :20A OCP :30A PL903 0.36UH_PCMC104T-R36MN1R105_30A_20% 3 2 1 PR956 0_0402_5% 2 @ 2 1 1 1 PGOOD_APU ISEN2_APU PRE-PWROK METAL VID CODES +APU_CORE 4 UGATE1_APU PR931 1.91K_0402_1% PGOOD_NB B PC1014 22U_0805_6.3V6M 2 1 1 2 PQ903 AON6414AL_DFN 2 2 5 41 20 18 62771_FB_APU 19 17 +3VS 5 PR933 10.7K_0402_1% 62771_RTN_APU 2 PH903 470K_0402_3%_NCP15WM474E03RC 16 2 62771_VSEN_APU 62771NTC_APU 1 CPU_B+ 2200P_0402_50V7K PC922 BOOT1_APU 1 UGATE1_APU 2 PR927 1_0603_5% 2 22 21 1 10U_0805_25V6K PC924 PHASE1_APU 1 LGATE1_APU 23 C +5VS TP PGOOD COMP FB RTN VSEN ISUMN BOOT1 APU_VDD 24 +5VALW 10U_0805_25V6K PC923 UGATE1 IMON 25 1 PR923 @ 0_0402_5% 2 PWROK 2 1 PHASE1 PR920 0_0402_5% 2 @ APU_VDDP PC921 1U_0603_25V6M LGATE1 ENABLE 1 28 27 26 2 32 VDD ISL62771HRTZ_TQFN40_5X5 SVT 29 1 VDDIO 30 PC920 1U_0603_25V6M BOOT_NB 31 33 PHASE_NB UGATE_NB 34 LGATE_NB PGOOD_NB 35 36 VDDP 11 1 APU_NTC_1 1 COMP_NB 39 38 37 FB_NB SVD 2 PR991 27.4K_0402_1% 1 2 PR940 0_0402_5% VSEN_NB 40 LGATE2 PC926 0.1U_0402_25V6 +5VS ISUMP_NB VR_HOT_L 15 1 PHASE2 62771_ISUMN_APU APU_PWROK UGATE2 SVC ISUMP <5> 62771A_IMON BOOT2 IMON_NB ISEN1 APU_SVT EC_VR_ON NTC_NB 14 <5> PR961 0_0402_5% 2 1 VR_IMVP_IMON APU_SVD +1.8VS <44> <44> 2 IMON_NB PR919 0_0402_5% 1 2 62771_SVC_A 3 PR921 0_0402_5% @ 1 262771_VRHOT_A 4 PR922 0_0402_5% @ 1 262771_SVD_A 5 PR926 0_0402_5% @ 1 262771_VDDIO_A 6 PR928 0_0402_5% @ 1 2 62771_SVT_A 7 PR929 0_0402_5% @ 1 2 62771_EN_A 8 PR930 0_0402_5% @ 1 262771_PWROK_A 9 @ 2 1 62771A_IMON 10 PR932 133K_0402_1% VR_HOT# <5> 1 62771NTC_NB APU_SVC ISUMN_NB PH902 470K_0402_3%_NCP15WM474E03RC 2 ISEN2 1 2 1000P_0402_50V7K PC919 PR924 133K_0402_1% 2 1 <44> PR916 @ 10K_0402_5% PU901 <5> C BOOT_NB PC917 @ 0.22U_0402_10V6K NTC 1 1 13 PR918 10.7K_0402_1% 1 2 62771NTC_NB_R 2NB_R_B 2 12 PC918 0.1U_0402_25V6 PR917 27.4K_0402_1% 1 2 1 2 1 Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 PWR_CPU Core THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thursday, February 20, 2014 Date: Rev 0.4 NM-A281 5 4 3 2 1 Sheet 59 of 60 5 4 3 2 1 D D C C B B A A Issued Date Title LC Future Center Secret Data Security Classification 2013/08/15 Deciphered Date 2013/08/15 PROCESSOR DECOUPLING THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Date: 5 4 3 2 Document Number Rev 0.4 NM-A281 Thursday, February 20, 2014 Sheet 1 60 of 60 www.s-manuals.com
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