ARM® Cortex® M4 32b MCU+FPU, 225DMIPS, Up To 512kB Flash/128+4KB RAM, USB OTG HS/FS, 17 TIMs, 3 ADCs, 20 Comm. Interfaces Cortex Manual
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- Table 1. Device summary
- 1 Introduction
- 2 Description
- 3 Functional overview
- 3.1 ARM® Cortex®-M4 with FPU and embedded Flash and SRAM
- 3.2 Adaptive real-time memory accelerator (ART Accelerator™)
- 3.3 Memory protection unit
- 3.4 Embedded Flash memory
- 3.5 CRC (cyclic redundancy check) calculation unit
- 3.6 Embedded SRAM
- 3.7 Multi-AHB bus matrix
- 3.8 DMA controller (DMA)
- 3.9 Flexible memory controller (FMC)
- 3.10 Quad SPI memory interface (QUADSPI)
- 3.11 Nested vectored interrupt controller (NVIC)
- 3.12 External interrupt/event controller (EXTI)
- 3.13 Clocks and startup
- 3.14 Boot modes
- 3.15 Power supply schemes
- 3.16 Power supply supervisor
- 3.17 Voltage regulator
- 3.18 Real-time clock (RTC), backup SRAM and backup registers
- 3.19 Low-power modes
- 3.20 VBAT operation
- 3.21 Timers and watchdogs
- 3.22 Inter-integrated circuit interface (I2C)
- 3.23 Universal synchronous/asynchronous receiver transmitters (USART)
- 3.24 Serial peripheral interface (SPI)
- 3.25 HDMI (high-definition multimedia interface) consumer electronics control (CEC)
- 3.26 Inter-integrated sound (I2S)
- 3.27 SPDIF-RX Receiver Interface (SPDIFRX)
- 3.28 Serial Audio interface (SAI)
- 3.29 Audio PLL (PLLI2S)
- 3.30 Serial Audio Interface PLL(PLLSAI)
- 3.31 Secure digital input/output interface (SDIO)
- 3.32 Controller area network (bxCAN)
- 3.33 Universal serial bus on-the-go full-speed (OTG_FS)
- 3.34 Universal serial bus on-the-go high-speed (OTG_HS)
- 3.35 Digital camera interface (DCMI)
- 3.36 General-purpose input/outputs (GPIOs)
- 3.37 Analog-to-digital converters (ADCs)
- 3.38 Temperature sensor
- 3.39 Digital-to-analog converter (DAC)
- 3.40 Serial wire JTAG debug port (SWJ-DP)
- 3.41 Embedded Trace Macrocell™
- 4 Pinout and pin description
- 5 Memory mapping
- 6 Electrical characteristics
- 6.1 Parameter conditions
- 6.2 Absolute maximum ratings
- 6.3 Operating conditions
- 6.3.1 General operating conditions
- 6.3.2 VCAP_1/VCAP_2 external capacitor
- 6.3.3 Operating conditions at power-up / power-down (regulator ON)
- 6.3.4 Operating conditions at power-up / power-down (regulator OFF)
- 6.3.5 Reset and power control block characteristics
- 6.3.6 Over-drive switching characteristics
- 6.3.7 Supply current characteristics
- Table 23. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch) or RAM
- Table 24. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled with prefetch) or RAM
- Table 25. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled)
- Table 26. Typical and maximum current consumption in Sleep mode
- Table 27. Typical and maximum current consumptions in Stop mode
- Table 28. Typical and maximum current consumptions in Standby mode
- Table 29. Typical and maximum current consumptions in VBAT mode
- Table 30. Typical current consumption in Run mode, code with data processing running from Flash memory or RAM, regulator ON (ART accelerator enabled except prefetch), VDD=1.7 V
- Table 31. Typical current consumption in Run mode, code with data processing running from Flash memory, regulator OFF (ART accelerator enabled except prefetch)
- Table 32. Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V
- Table 33. Typical current consumption in Sleep mode, regulator OFF
- Table 34. Switching output I/O current consumption
- Table 35. Peripheral current consumption
- 6.3.8 Wakeup time from low-power modes
- 6.3.9 External clock source characteristics
- 6.3.10 Internal clock source characteristics
- 6.3.11 PLL characteristics
- 6.3.12 PLL spread spectrum clock generation (SSCG) characteristics
- 6.3.13 Memory characteristics
- 6.3.14 EMC characteristics
- 6.3.15 Absolute maximum ratings (electrical sensitivity)
- 6.3.16 I/O current injection characteristics
- 6.3.17 I/O port characteristics
- 6.3.18 NRST pin characteristics
- 6.3.19 TIM timer characteristics
- 6.3.20 Communications interfaces
- Table 61. I2C characteristics
- Table 62. FMPI2C characteristics
- Table 63. SPI dynamic characteristics
- Table 64. QSPI dynamic characteristics in SDR Mode
- Table 65. QSPI dynamic characteristics in DDR Mode
- Table 66. I2S dynamic characteristics
- Table 67. SAI characteristics
- Table 68. USB OTG full speed startup time
- Table 69. USB OTG full speed DC electrical characteristics
- Table 70. USB OTG full speed electrical characteristics
- Table 71. USB HS DC electrical characteristics
- Table 72. USB HS clock timing parameters
- Table 73. Dynamic characteristics: USB ULPI
- 6.3.21 12-bit ADC characteristics
- Table 74. ADC characteristics
- Table 75. ADC static accuracy at fADC = 18 MHz
- Table 76. ADC static accuracy at fADC = 30 MHz
- Table 77. ADC static accuracy at fADC = 36 MHz
- Table 78. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions
- Table 79. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions
- 6.3.22 Temperature sensor characteristics
- 6.3.23 VBAT monitoring characteristics
- 6.3.24 Reference voltage
- 6.3.25 DAC electrical characteristics
- 6.3.26 FMC characteristics
- Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings
- Table 87. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings
- Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
- Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings
- Table 90. Asynchronous multiplexed PSRAM/NOR read timings
- Table 91. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
- Table 92. Asynchronous multiplexed PSRAM/NOR write timings
- Table 93. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
- Table 94. Synchronous multiplexed NOR/PSRAM read timings
- Table 95. Synchronous multiplexed PSRAM write timings
- Table 96. Synchronous non-multiplexed NOR/PSRAM read timings
- Table 97. Synchronous non-multiplexed PSRAM write timings
- Table 98. Switching characteristics for NAND Flash read cycles
- Table 99. Switching characteristics for NAND Flash write cycles
- Table 100. SDRAM read timings
- Table 101. LPSDR SDRAM read timings
- Table 102. SDRAM write timings
- Table 103. LPSDR SDRAM write timings
- 6.3.27 Camera interface (DCMI) timing specifications
- 6.3.28 SD/SDIO MMC card host interface (SDIO) characteristics
- 6.3.29 RTC characteristics
- 7 Package information
- 8 Part numbering
- Appendix A Application block diagrams
- Revision history