ARM® Cortex® M4 32b MCU+FPU, 225DMIPS, Up To 512kB Flash/128+4KB RAM, USB OTG HS/FS, 17 TIMs, 3 ADCs, 20 Comm. Interfaces Cortex Manual
User Manual:
Open the PDF directly: View PDF 
.
Page Count: 202
| Download | |
| Open PDF In Browser | View PDF |
STM32F446xC/E
ARM® Cortex®-M4 32b MCU+FPU, 225DMIPS, up to 512kB Flash/128+4KB RAM,
USB OTG HS/FS, 17 TIMs, 3 ADCs, 20 comm. interfaces
Datasheet - production data
Features
&"'!
• Core: ARM® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Fl ash memory, frequency up to 180 MHz,
MPU, 225 DMIPS/1.25 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
• Memories
– 512 kB of Flash memory
– 128 KB of SRAM
– Flexible external memory controller with up
to 16-bit data bus:
SRAM,PSRAM,SDRAM/LPSDR SDRAM,
Flash NOR/NAND memories
– Dual mode Quad SPI interface
• LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
• Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC, 20×32 bit backup
registers + optional 4 KB backup SRAM
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels
and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
• Up to 17 timers: 2x watchdog, 1x SysTick timer
and up to twelve 16-bit and two 32-bit timers up
to 180 MHz, each with up to 4 IC/OC/PWM or
pulse counter
• Debug mode
– SWD & JTAG interfaces
– Cortex®-M4 Trace Macrocell™
September 2016
This is information on a product in full production.
LQFP64 (10 × 10mm)
LQFP100 (14 × 14mm) UFBGA144 (7 x 7 mm)
LQFP144 (20 x 20 mm) UFBGA144 (10 x 10 mm)
WLCSP 81
• Up to 114 I/O ports with interrupt capability
– Up to 111 fast I/Os up to 90 MHz
– Up to 112 5 V-tolerant I/Os
• Up to 20 communication interfaces
– SPDIF-Rx
– Up to 4 × I2C interfaces (SMBus/PMBus)
– Up to 4 USARTs/2 UARTs (11.25 Mbit/s,
ISO7816 interface, LIN, IrDA, modem
control)
– Up to 4 SPIs (45 Mbits/s), 3 with muxed I2S
for audio class accuracy via internal audio
PLL or external clock
– 2 x SAI (serial audio interface)
– 2 × CAN (2.0B Active)
– SDIO interface
– Consumer electronics control (CEC) I/F
• Advanced connectivity
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
– Dedicated USB power rail enabling on-chip
PHYs operation throughout the entire MCU
power supply range
• 8- to 14-bit parallel camera interface up to
54 Mbytes/s
• CRC calculation unit
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID
Table 1. Device summary
Reference
STM32F446xC/E
DocID027107 Rev 6
Part number
STM32F446MC, STM32F446ME,
STM32F446RC, STM32F446RE,
STM32F446VC, STM32F446VE,
STM32F446ZC, STM32F446ZE.
1/202
www.st.com
Contents
STM32F446xC/E
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
ARM® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . 17
3.2
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 17
3.3
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 18
3.6
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10
Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 21
3.12
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.13
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17
2/202
Compatibility with STM32F4 family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.16.1
Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.16.2
Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.1
Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.2
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.17.3
Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 27
3.18
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 28
3.19
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.20
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.21
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DocID027107 Rev 6
STM32F446xC/E
Contents
3.21.1
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.21.2
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.21.3
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.21.4
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.21.5
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.21.6
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.22
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.23
Universal synchronous/asynchronous receiver transmitters (USART) . . 34
3.24
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.25
HDMI (high-definition multimedia interface) consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.26
Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.27
SPDIF-RX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . 35
3.28
Serial Audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.29
Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.30
Serial Audio Interface PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.31
Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 36
3.32
Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.33
Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 37
3.34
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 37
3.35
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.36
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.37
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.38
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.39
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.40
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.41
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4
Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DocID027107 Rev 6
3/202
5
Contents
4/202
STM32F446xC/E
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.2
VCAP_1/VCAP_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.3
Operating conditions at power-up / power-down (regulator ON) . . . . . . 79
6.3.4
Operating conditions at power-up / power-down (regulator OFF) . . . . . 79
6.3.5
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 80
6.3.6
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.7
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.8
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.9
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.3.10
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.11
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.12
PLL spread spectrum clock generation (SSCG) characteristics . . . . . 110
6.3.13
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.14
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.3.15
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 116
6.3.16
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.17
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.3.18
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.19
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.20
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.21
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.22
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.3.23
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.24
Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.25
DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.26
FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.27
Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 172
6.3.28
SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 173
6.3.29
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
DocID027107 Rev 6
STM32F446xC/E
7
8
Contents
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
7.1
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
7.2
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
7.3
LQFP144 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
7.4
UFBGA144 7 x 7 mm package information . . . . . . . . . . . . . . . . . . . . . . 186
7.5
UFBGA144 10 x 10 mm package information . . . . . . . . . . . . . . . . . . . . 189
7.6
WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.7
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
A.1
USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 197
A.2
USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 199
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
DocID027107 Rev 6
5/202
5
List of figures
STM32F446xC/E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
6/202
Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Compatible board for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
STM32F446xC/E block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STM32F446xC/E and Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 23
Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 24
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Startup in regulator OFF: slow VDD slope
power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . . 27
Startup in regulator OFF mode: fast VDD slope
power-down reset risen before VCAP_1/VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . 27
STM32F446xC/xE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
STM32F446xC/xE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
STM32F446xC LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
STM32F446xC/xE WLCSP81 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
STM32F446xC/xE UFBGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Typical VBAT current consumption
(RTC ON/backup RAM OFF and LSE in low power mode) . . . . . . . . . . . . . . . . . . . . . . . . 91
Typical VBAT current consumption
(RTC ON/backup RAM OFF and LSE in high drive mode). . . . . . . . . . . . . . . . . . . . . . . . . 92
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
LACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
FMPI2C timing diagram and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 138
ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
DocID027107 Rev 6
STM32F446xC/E
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
List of figures
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 146
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 147
12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 153
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 155
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 156
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 158
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 164
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 168
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 168
SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
LQFP64-10x10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 176
LQFP64 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 179
LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 182
LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
UFBGA144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
UFBGA144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
UQFP144 7 x 7 mm marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . 188
UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
UQFP144 10 x 10 mm marking example (package top view). . . . . . . . . . . . . . . . . . . . . . 191
WLCSP81 - 81-pin, 3.693 x 3.815 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
WLCSP81- 81-pin, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
WLCSP81 10 x 10 mm marking example (package top view) . . . . . . . . . . . . . . . . . . . . . 194
USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . 197
USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 197
USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 198
USB controller configured as peripheral, host, or dual-mode
and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
DocID027107 Rev 6
7/202
7
List of tables
STM32F446xC/E
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
8/202
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F446xC/E features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 25
Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 27
Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
STM32F446xx pin and ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
STM32F446xC/E register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 78
VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Operating conditions at power-up/power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . . 79
Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 79
reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM . . . . . . . 83
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled with prefetch) or RAM . . . . . . . . . 84
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 86
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 89
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 90
Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 91
Typical current consumption in Run mode, code with data processing
running from Flash memory or RAM, regulator ON
(ART accelerator enabled except prefetch), VDD=1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Typical current consumption in Run mode, code with data processing running
from Flash memory, regulator OFF (ART accelerator enabled except prefetch). . . . . . . . 94
Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V . . . . . . . . . . . . . . 95
Typical current consumption in Sleep mode, regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . 96
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
DocID027107 Rev 6
STM32F446xC/E
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
List of tables
Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
FMPI2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
QSPI dynamic characteristics in SDR Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
QSPI dynamic characteristics in DDR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 143
ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 143
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Asynchronous non-multiplexed SRAM/PSRAM/NOR read NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 155
Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 157
DocID027107 Rev 6
9/202
10
List of tables
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
10/202
STM32F446xC/E
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 159
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 164
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 169
SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V. . . . . . . . . . . . . . . 175
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . 176
LQPF100, 14 x 14 mm 100-pin low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 183
UFBGA144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) . . . . . . . . . . . . . . . . 187
UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 190
WLCSP81- 81-pin, 3.693 x 3.815 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
WLCSP81 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 193
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
DocID027107 Rev 6
STM32F446xC/E
1
Introduction
Introduction
This document provides the description of the STM32F446xC/E products.
The STM32F446xC/E document should be read in conjunction with the STM32F4xx
reference manual.
For information on the Cortex®-M4 core, please refer to the Cortex®-M4 programming
manual (PM0214), available from the www.st.com.
DocID027107 Rev 6
11/202
40
Description
2
STM32F446xC/E
Description
The STM32F446xC/E devices are based on the high-performance ARM® Cortex®-M4 32-bit
RISC core operating at a frequency of up to 180 MHz. The Cortex-M4 core features a
Floating point unit (FPU) single precision which supports all ARM® single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
The STM32F446xC/E devices incorporate high-speed embedded memories (Flash memory
up to 512 Kbyte, up to 128 Kbyte of SRAM), up to 4 Kbytes of backup SRAM, and an
extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB
buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers.
They also feature standard and advanced communication interfaces.
•
Up to four I2Cs;
•
Four SPIs, three I2Ss full simplex. To achieve audio class accuracy, the I2S peripherals
can be clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization;
•
Four USARTs plus two UARTs;
•
An USB OTG full-speed and an USB OTG high-speed with full-speed capability (with
the ULPI), both with dedicated power rails allowing to use them throughout the entire
power range;
•
Two CANs;
•
Two SAIs serial audio interfaces. To achieve audio class accuracy, the SAIs can be
clocked via a dedicated internal audio PLL;
•
An SDIO/MMC interface;
•
Camera interface;
•
HDMI-CEC;
•
SPDIF Receiver (SPDIFRx);
•
QuadSPI.
Advanced peripherals include an SDIO, a flexible memory control (FMC) interface, a
camera interface for CMOS sensors. Refer to Table 2: STM32F446xC/E features and
peripheral counts for the list of peripherals available on each part number.
The STM32F446xC/E devices operates in the –40 to +105 °C temperature range from a 1.7
to 3.6 V power supply.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor
(refer to Section 3.16.2: Internal reset OFF). A comprehensive set of power-saving mode
allows the design of low-power applications.
The STM32F446xC/E devices offer devices in 6 packages ranging from 64 pins to 144 pins.
The set of included peripherals changes with the device chosen.
12/202
DocID027107 Rev 6
STM32F446xC/E
Description
These features make the STM32F446xC/E microcontrollers suitable for a wide range of
applications:
•
Motor drive and application control
•
Medical equipment
•
Industrial applications: PLC, inverters, circuit breakers
•
Printers, and scanners
•
Alarm systems, video intercom, and HVAC
•
Home audio appliances
Table 2. STM32F446xC/E features and peripheral counts
Peripherals
Flash memory in Kbytes
SRAM in
Kbytes
STM32F44
6MC
STM32F44
6ME
STM32F44
6RC
STM32F44
6RE
STM32F44
6VC
STM32F44
6VE
STM32F44
6ZC
STM32F44
6ZE
256
512
256
512
256
512
256
512
System
128 (112+16)
Backup
4
FMC memory controller
Timers
Yes(1)
No
Generalpurpose
10
Advancedcontrol
2
Basic
2
SPI / I2S
4/3 (simplex)(2)
I2C
4/1 FMP +
USART/UART
4/2
USB OTG FS
Yes (6-Endpoints)
USB OTG HS
Yes (8-Endpoints)
Communication
CAN
interfaces
2
SAI
2
SDIO
Yes
SPDIF-Rx
1
HDMI-CEC
1
(3)
1
Quad SPI
Camera interface
GPIOs
12-bit ADC
Number of channels
Yes
63
50
114
16
24
3
14
16
12-bit DAC
Number of channels
Yes
2
Maximum CPU frequency
180 MHz
1.8 to 3.6 V(4)
Operating voltage
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Operating temperatures
Packages
81
Junction temperature: –40 to + 125 °C
WLCSP81
LQFP64
DocID027107 Rev 6
LQFP100
LQFP144
UFBGA144
13/202
40
Description
STM32F446xC/E
1.
For the LQFP100 package, only FMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the
NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used
since Port G is not available in this package.
2.
The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3.
For the LQFP64 package, the Quad SPI is available with limited features.
4.
VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external
power supply supervisor (refer to Section 3.16.2: Internal reset OFF).
2.1
Compatibility with STM32F4 family
The STM32F446xC/xV is software and feature compatible with the STM32F4 family.
The STM32F446xC/xV can be used as drop-in replacement of the other STM32F4 products
but some slight changes have to be done on the PCB board.
Figure 1. Compatible board design for LQFP100 package
670)[[
3%QRWDYDLODEOHDQ\PRUH
5HSODFHGE\9 &$3
3(
3(
3(
3(
3(
3(
3%
9&$3
966
9''
3'
3'
3'
3'
3%
3%
3%
3%
3(
3(
3(
3(
3(
3(
3%
3%
9&$3
9''
670)670)OLQH
670)670)OLQH
670)670)OLQH
670) 670) OLQH
3'
3'
3'
3'
3%
3%
3%
3%
966 9''
966 9''
069
14/202
DocID027107 Rev 6
STM32F446xC/E
Description
Figure 2. Compatible board for LQFP64 package
670)[[
3%
9&$3
9''
3%
3%
9''
9&$3
3$
3$
3$
3$
3$
3$
3&
3&
3&
3&
3%
3%
3%
3%
9''
966
3%QRWDYDLODEOHDQ\PRUH
5HSODFHGE\9&$3
9''
966
3$
3$
3$
3$
3$
3$
3&
3&
3&
3&
3%
3%
3%
3%
9''
966
3%
3%
9&$3
966
9''
3&
3&
3&
3$
3$
3&
3&
3&
3$
3$
670)670)OLQH
9LQFUHDVHGWRI
&$3
(65RUEHORZ
966 9''
966 9''
069
Figure 3 shows the STM32F446xx block diagram.
DocID027107 Rev 6
15/202
40
Description
STM32F446xC/E
Figure 3. STM32F446xC/E block diagram
'0$
),)2
,'9%86
6WUHDPV
*3'0$
),)2
&/.&6D&6E'> @
)/$6+N%
65$0.%
65$0.%
$+%
0+]
6WUHDPV
325
$+%0+]
),)2
86%
27*)6
6833/<
683(59,6,21
3253'5
%25
5HVHW
,QW
#9''$
*3,23257'
86$570%SV
3(
*3,23257(
86$570%SV
3)
*3,23257)
86$570%SV
3*
*3,23257*
86$570%SV
5(6(7
&/2&.
0$1$*7
&75/
3+
*3,23257+
86$570%SV
/6
86$570%SV
7,0(53:0
&+DV$)
E
E
:LQ:$7&+'2*
VPFDUG
86$57
86$570%SV
LU'$
026,0,62
6&.166DV$)
63,,6
86$570%SV
026,0,62
6&.166DV$)
86$570%SV
63,
6'6&.)6
0&/.DV$)
86$570%SV
6$,
),)2
VPFDUG
86$570%SV
86$57
LU'$
6$,
86$570%SV
6'6&.)6
0&/.DV$)
9''5()B$'&
$,1FRPPRQ
WRWKH$'&V
$,1FRPPRQ
WRWKH$'&
$,1WR$'&
7,0(5
7,0(5
E
E
$'&
$'&
$'&
&+ D V$)
7,0(5 E
&+DV$)
E
&+DV$)
86$57
86$57
VPFDUG
LU'$
'$&
'$&DV$)
5;7;6&.
&76576DV$)
5;7;6&.
&76576DV$)
8$57
5;7;DV$)
8$57
5;7;DV$)
63',)
63',)B5;> @DV$)
+'0,&(&
+'0,B&(&D V$)
63,,6
026,0,626&.
166:60&.DV$)
63,,6
026,0,626&.
166:60&.DV$)
6&/6'$60%$/DV$)
,&60%86
,&60%86
'$&
&+DV$)
VPFDUG
LU'$
)03,&
6&/6'$60%$/DV$)
6&/6'$60%$/DV$)
6&/6'$60%$/DV$)
,7)
E[&$1
E[&$1
16/202
&+(75DV$)
7,0(5 E
,&60%86
#9''$
,)
$/$50B287
67$03
67$03
&+(75DV$)
#9''$
86$570%SV
7(036(1625
WR9
26&B,1
26&B287
&+(75DV$)
E
),)2
5;7;6&.
&76576DV$)
26&,1
26&287
7,0(5 E
7,0(5 E
7,0(5
86$570%SV
9 '' WR9
966
9&$3
7,0(5 E
7,0(5
7,0(5
86$570%SV
&+DV$)
5;7;6&.
&76576DV$)
.%%.35$0
E
7,0(5
86$570%SV
&+DV$)
$:8
%.35(*
7,0(5 E
$ 3% 0+]
3:03:0
(75%.,1DV$)
;7$/N+]
57&
$+%$3% $+%$3%
E
7,0(53:0
86$570%SV
9''$ 966$
9%$7
#9%$7
$3% 0+]
3:03:0
(75%.,1DV$)
6',200&
9''86% 729
''
,'9%86
:'*.
*3'0$
$3% 0+]
'
&0'&.DV$)
*3'0$
(;7,7:.83
86$570%SV
#9''
6WDQGE\LQWHUIDFH
&5&
),)2
$)
92/75(*
9729
;7$/26&
0+]
/6
*3,23257&
86$570%SV
3'
#9''$
32:(501*7
3//3//3//
*3,23257%
86$570%SV
3&
5&+6
5&/6
3:5&7/
3%
*3,23257$
86$570%SV
)&/.
+ &/.
$3%3 &/.
$3%3 &/.
$+%3&/.
$+ %3&/.
3$
+6<1&96<1&
3,;&.'
15(6(7
39'
'LJ)LOWHU
*3'0$
&$0(5$
,7)
3+<
86%
27*+6
4XDG63,
'$&DV$)
DocID027107 Rev 6
),)2
9''86% 729
''
8/3, &/.'
',56731;7
3+<
6%86
&/.1(> @$> @'> @
12(11:(11%/> @
6'&/.(> @6'1(> @
15$61&$61$'9
1:$,7,171
),)2
,%86
'%86
(;70(0&7/)0&
65$0365$0125)/$6+
1$1')/$6+6'5$0
),)2
$50
&257(;0
0+]
$+%B(0,
038 )38
19,&
)/$6+
,)
75$&(&.
75$&('
-7$* 6:
(70
$+%%860$75,;60
-7567-7',
-7&.6:&/.
-7'26:'-7'2
7;5;
7;5;
069
STM32F446xC/E
Functional overview
3
Functional overview
3.1
ARM® Cortex®-M4 with FPU and embedded Flash and SRAM
The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The ARM® Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional
code-efficiency, delivering the high-performance expected from an ARM core in the memory
size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F446xC/E family is compatible with all ARM tools and software.
Figure 3 shows the general block diagram of the STM32F446xC/E family.
Note:
Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core.
3.2
Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard ARM® Cortex®-M4 with FPU processors. It balances the inherent performance
advantage of the ARM® Cortex®-M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 225 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 180 MHz.
3.3
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
DocID027107 Rev 6
17/202
40
Functional overview
3.4
STM32F446xC/E
Embedded Flash memory
The devices embed a Flash memory of 512KB available for storing programs and data.
3.5
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
3.6
Embedded SRAM
All devices embed:
•
Up to 128Kbytes of system SRAM.
RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.
•
4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
3.7
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, USB HS) and
the slaves Flash memory, RAM, QuadSPI, FMC, AHB and APB peripherals and ensures a
seamless and efficient operation even when several high-speed peripherals work
simultaneously.
18/202
DocID027107 Rev 6
STM32F446xC/E
Functional overview
Figure 4. STM32F446xC/E and Multi-AHB matrix
6
6
6
6
86%B+6B0
86%27*
+6
'0$B3
*3
'0$
'0$B0(0
'0$B0(0
'0$B3,
6EXV
6
*3
'0$
6
,&2'(
'&2'(
$&&(/
6
'EXV
,EXV
$50
&RUWH[0
)ODVK
PHPRU\
65$0
.E\WH
65$0
.E\WH
$+%
SHULSKHUDOV
$3%
$+%
SHULSKHUDOV
$3%
)0&H[WHUQDO
0HP&WO4XDG63,
%XVPDWUL[6
-36
3.8
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
DocID027107 Rev 6
19/202
40
Functional overview
STM32F446xC/E
The DMA can be used with the main peripherals:
3.9
•
SPI and I2S
•
I2C
•
USART
•
General-purpose, basic and advanced-control timers TIMx
•
DAC
•
SDIO
•
Camera interface (DCMI)
•
ADC
•
SAI1/SAI2
•
SPDIF Receiver (SPDIFRx)
•
QuadSPI
Flexible memory controller (FMC)
All devices embed an FMC. It has seven Chip Select outputs supporting the following
modes: SDRAM/LPSDR SDRAM, SRAM, PSRAM, NOR Flash and NAND Flash. With the
possibility to remap FMC bank 1 (NOR/PSRAM 1 and 2) and FMC SDRAM bank 1/2 in the
Cortex-M4 code area.
Functionality overview:
•
8-,16-bit data bus width
•
Read FIFO for SDRAM controller
•
Write FIFO
•
Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is 90 MHz.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.10
Quad SPI memory interface (QUADSPI)
All devices embed a Quad SPI memory interface, which is a specialized communication
interface targeting Single, Dual or Quad SPI flash memories. It can work in direct mode
through registers, external flash status register polling mode and memory mapped mode.
Up to 256 Mbytes external flash are memory mapped, supporting 8, 16 and 32-bit access.
Code execution is supported. The opcode and the frame format are fully programmable.
Communication can be either in Single Data Rate or Dual Data Rate.
20/202
DocID027107 Rev 6
STM32F446xC/E
3.11
Functional overview
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 91 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4 with FPU core.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support tail chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.12
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 114 GPIOs can be connected
to the 16 external interrupt lines.
3.13
Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16
MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The application
can then select as system clock either the RC oscillator or an external 4-26 MHz clock
source. This clock can be monitored for failure. If a failure is detected, the system
automatically switches back to the internal RC oscillator and a software interrupt is
generated (if enabled). This clock source is input to a PLL thus allowing to increase the
frequency up to 180 MHz. Similarly, full interrupt management of the PLL clock entry is
available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 180 MHz while the maximum frequency of the high-speed APB domains is
90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.
The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio
class performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
DocID027107 Rev 6
21/202
40
Functional overview
3.14
STM32F446xC/E
Boot modes
At startup, boot pins are used to select one out of three boot options:
•
Boot from user Flash
•
Boot from system memory
•
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial (UART, I2C, CAN, SPI and USB) communication interface. Refer to
application note AN2606 for details.
3.15
Note:
Power supply schemes
•
VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
•
VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply
supervisor (refer to Section 3.16.2: Internal reset OFF). Refer to Table 3: Voltage regulator
configuration mode versus device operating mode to identify the packages supporting this
option.
•
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
•
VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6V) for USB transceivers.
For example, when device is powered at 1.8V, an independent power supply 3.3V can
be connected to VDDUSB. When the VDDUSB is connected to a separated power supply,
it is independent from VDD or VDDA but it must be the last supply to be provided and the
first to disappear. The following conditions VDDUSB must be respected:
–
During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
–
During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower
than VDD
–
VDDUSB rising and falling time rate specifications must be respected.
–
In operating mode phase, VDDUSB could be lower or higher than VDD:
– If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.The VDDUSB
supply both USB transceiver (USB OTG_HS and USB OTG_FS).
– If only one USB transceiver is used in the application, the GPIOs associated to
the other USB transceiver are still supplied by VDDUSB.
– If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered
by VDDUSB are operating between VDD_MIN and VDD_MAX.
22/202
DocID027107 Rev 6
STM32F446xC/E
Functional overview
Figure 5. VDDUSB connected to an external independent power supply
9''86%B0$;
86% IXQFWLRQDODUHD
9''86%
9''86%B0,1
86%QRQ
IXQFWLRQDO
DUHD
9'' 9''$
86%QRQ
IXQFWLRQDO
DUHD
2SHUDWLQJPRGH
3RZHUGRZQ
9''B0,1
3RZHURQ
WLPH
06 9
3.16
Power supply supervisor
3.16.1
Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other package, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.16.2
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and should maintain the device in
reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to
VSS, to allows device to operate down to 1.7v. Refer to Figure 6: Power supply supervisor
interconnection with internal reset OFF.
DocID027107 Rev 6
23/202
40
Functional overview
STM32F446xC/E
Figure 6. Power supply supervisor interconnection with internal reset OFF
s
^dDϯϮ&ϰϰϲdž
ƉƉůŝĐĂƚŝŽŶƌĞƐĞƚ
ƐŝŐŶĂů;ŽƉƚŝŽŶĂůͿ
sd
WZͺKE
s^^
WZŶŽƚĂĐƚŝǀĞ͗ϭ͘ϳǀфsфϯ͘ϲǀ
D^ϯϯϴϰϰsϭ
The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V.
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
•
The brownout reset (BOR) circuitry must be disabled
•
The embedded programmable voltage detector (PVD) is disabled
•
VBAT functionality is no more available and VBAT pin should be connected to VDD.
All packages, except for the LQFP100/LQFP64, allow to disable the internal reset through
the PDR_ON signal.
3.17
Voltage regulator
The regulator has four operating modes:
•
•
3.17.1
Regulator ON
–
Main regulator mode (MR)
–
Low power regulator (LPR)
–
Power-down
Regulator OFF
Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
24/202
DocID027107 Rev 6
STM32F446xC/E
Functional overview
There are three power modes configured by software when the regulator is ON:
•
MR mode used in Run/sleep modes or in Stop modes
–
In Run/Sleep mode
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). Different voltages scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
The over-drive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
–
In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).
•
LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
•
–
LPR operates in normal mode (default mode when LPR is ON)
–
LPR operates in under-drive mode (reduced leakage mode).
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin.
All packages have the regulator ON feature.
Table 3. Voltage regulator configuration mode versus device operating mode(1)
Voltage regulator
configuration
Run mode
Sleep mode
Stop mode
Standby mode
Normal mode
MR
MR
MR or LPR
-
Over-drive
mode(2)
MR
MR
-
-
Under-drive mode
-
-
MR or LPR
-
Power-down
mode
-
-
-
Yes
1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.
3.17.2
Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
DocID027107 Rev 6
25/202
40
Functional overview
STM32F446xC/E
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. The two 2.2 µF ceramic capacitors should
be replaced by two 100 nF decoupling capacitors.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
•
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
•
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
•
The over-drive and under-drive modes are not available.
Figure 7. Regulator OFF
9
([WHUQDO9&$3BSRZHU
$SSOLFDWLRQUHVHW
VXSSO\VXSHUYLVRU
([WUHVHWFRQWUROOHUDFWLYH VLJQDO RSWLRQDO
ZKHQ9&$3B 0LQ9
9''
3$
9''
1567
%<3$66B5(*
9
9&$3B
9&$3B
DL 9
The following conditions must be respected:
Note:
26/202
•
VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
•
If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 8).
•
Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 9).
•
If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
The minimum value of V12 depends on the maximum frequency targeted in the application.
DocID027107 Rev 6
STM32F446xC/E
Functional overview
Figure 8. Startup in regulator OFF: slow VDD slope
power-down reset risen after VCAP_1/VCAP_2 stabilization
9''
3'5 9RU9
9
0LQ9
9&$3B9&$3B
WLPH
1567
WLPH
DL I
1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 9. Startup in regulator OFF mode: fast VDD slope
power-down reset risen before VCAP_1/VCAP_2 stabilization
9''
3'5 9RU9
9&$3B9&$3B
9
0LQ9
1567
WLPH
3$DVVHUWHGH[WHUQDOO\
WLPH
DL H
1. This figure is valid whatever the internal reset mode (ON or OFF).
3.17.3
Regulator ON/OFF and internal reset ON/OFF availability
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
Package
LQFP64
LQFP100
Regulator ON
Regulator OFF
Yes
No
DocID027107 Rev 6
Internal reset ON Internal reset OFF
Yes
No
27/202
40
Functional overview
STM32F446xC/E
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
Package
Regulator ON
Regulator OFF
Yes
No
LQFP144
UFBGA144
WLCSP81
3.18
Yes
BYPASS_REG
set to Vss
Yes
BYPASS_REG
set to VDD
Internal reset ON Internal reset OFF
Yes
PDR_ON
set to VDD
Yes
PDR_ON
set to VSS
Real-time clock (RTC), backup SRAM and backup registers
The backup domain includes:
•
The real-time clock (RTC)
•
4 Kbytes of backup SRAM
•
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC provides a programmable alarm and programmable
periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is
also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data
which need to be retained in VBAT and standby mode. This memory area is disabled by
default to minimize power consumption (see Section 3.19: Low-power modes). It can be
enabled by software.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 3.19: Low-power
modes).
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the VDD supply when present or from the VBAT pin.
28/202
DocID027107 Rev 6
STM32F446xC/E
3.19
Functional overview
Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator
modes in stop mode):
–
Normal mode (default mode when MR or LPR is enabled)
–
Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup).
Table 5. Voltage regulator modes in stop mode
•
Voltage regulator
configuration
Main regulator (MR)
Low-power regulator (LPR)
Normal mode
MR ON
LPR ON
Under-drive mode
MR in under-drive mode
LPR in under-drive mode
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event
occurs.
The standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.
3.20
VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
DocID027107 Rev 6
29/202
40
Functional overview
Note:
STM32F446xC/E
When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is not connected to VDD (Internal Reset OFF), the VBAT functionality is
no more available and VBAT pin should be connected to VDD.
30/202
DocID027107 Rev 6
STM32F446xC/E
3.21
Functional overview
Timers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
Table 6. Timer feature comparison
Timer
type
Advancedcontrol
General
purpose
Basic
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)(1)
TIM1,
TIM8
16-bit
Up,
Down,
Up/down
Any integer
between 1
and 65536
Yes
4
Yes
90
180
TIM2,
TIM5
32-bit
Up,
Down,
Up/down
Any integer
between 1
and 65536
Yes
4
No
45
90/180
TIM3,
TIM4
16-bit
Up,
Down,
Up/down
Any integer
between 1
and 65536
Yes
4
No
45
90/180
TIM9
16-bit
Up
Any integer
between 1
and 65536
No
2
No
90
180
TIM10,
TIM11
16-bit
Up
Any integer
between 1
and 65536
No
1
No
90
180
TIM12
16-bit
Up
Any integer
between 1
and 65536
No
2
No
45
90/180
TIM13,
TIM14
16-bit
Up
Any integer
between 1
and 65536
No
1
No
45
90/180
TIM6,
TIM7
16-bit
Up
Any integer
between 1
and 65536
Yes
0
No
45
90/180
1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR
register.
DocID027107 Rev 6
31/202
40
Functional overview
3.21.1
STM32F446xC/E
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
Input capture
•
Output compare
•
PWM generation (edge- or center-aligned modes)
•
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.21.2
General-purpose timers (TIMx)
There are ten synchronized general-purpose timers embedded in the STM32F446xC/E
devices (see Table 6 for differences).
•
TIM2, TIM3, TIM4, TIM5
The STM32F446xC/E include 4 full-featured general-purpose timers: TIM2, TIM5,
TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives
up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•
TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
3.21.3
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
32/202
DocID027107 Rev 6
STM32F446xC/E
3.21.4
Functional overview
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.21.5
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.21.6
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
3.22
•
A 24-bit downcounter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0
•
Programmable clock source.
Inter-integrated circuit interface (I2C)
Four I²C bus interfaces can operate in multimaster and slave modes. Three I²C can support
the standard (up to 100 KHz) and fast (up to 400 KHz) modes.
One I²C can support the standard (up to 100 KHz), fast (up to 400 KHz) and fast mode plus
(up to 1MHz) modes.
They (all I²C) support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as
slave).
A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 7).
Table 7. Comparison of I2C analog and digital filters
Pulse width of
suppressed spikes
Analog filter
≥ 50 ns
DocID027107 Rev 6
Digital filter
Programmable length from 1 to 15
I2C peripheral clocks
33/202
40
Functional overview
3.23
STM32F446xC/E
Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, and UART5).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate
at up to 5.62 bit/s.
USART1, USART2, USART3 and USART6 also provide hardware management of the CTS
and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.
Table 8. USART feature comparison(1)
USART
name
SPI
Standard
Modem
LIN maste
features (RTS/CTS)
r
irD
A
Smartcard
(ISO 7816)
Max. baud
rate in Mbit/s
(oversamplin
g by 16)
Max. baud
rate in Mbit/s
(oversamplin
g by 8)
APB
mapping
USART1
X
X
X
X
X
X
5.62
11.25
APB2
(max.
90 MHz)
USART2
X
X
X
X
X
X
2.81
5.62
APB1
(max.
45 MHz)
USART3
X
X
X
X
X
X
2.81
5.62
APB1
(max.
45 MHz)
UART4
X
X
X
-
X
-
2.81
5.62
APB1
(max.
45 MHz)
UART5
X
X
X
-
X
-
2.81
5.62
APB1
(max.
45 MHz)
USART6
X
X
X
X
X
X
5.62
11.25
APB2
(max.
90 MHz)
1. X = feature supported.
3.24
Serial peripheral interface (SPI)
The devices feature up to four SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, and SPI4 can communicate at up to 45 Mbits/s, SPI2 and
SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
34/202
DocID027107 Rev 6
STM32F446xC/E
Functional overview
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.
3.25
HDMI (high-definition multimedia interface) consumer
electronics control (CEC)
The devices embeds a HDMI-CEC controller that provides hardware support of consumer
electronics control (CEC) (Appendix supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead.
3.26
Inter-integrated sound (I2S)
Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in master or slave mode, in simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
3.27
SPDIF-RX Receiver Interface (SPDIFRX)
The SPDIF-RX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main features of the SPDIF-RX are the following:
•
Up to 4 inputs available
•
Automatic symbol rate detection
•
Maximum symbol rate: 12.288 MHz
•
Stereo stream from 32 to 192 kHz supported
•
Supports Audio IEC-60958 and IEC-61937, consumer applications
•
Parity bit management
•
Communication using DMA for audio samples
•
Communication using DMA for control and user channel information
•
Interrupt capabilities
The SPDIF-RX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream.
The user can select the wanted SPDIF input, and when a valid signal will be available, the
SPDIF-RX will re-sample the incoming signal, decode the Manchester stream, recognize
frames, sub-frames and blocks elements. It delivers to the CPU decoded data, and
associated status flags.
DocID027107 Rev 6
35/202
40
Functional overview
STM32F446xC/E
The SPDIF-RX also offers a signal named spdifrx_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
3.28
Serial Audio interface (SAI)
The devices feature two serial audio interfaces (SAI1 and SAI2). Each serial audio
interfaces based on two independent audio sub blocks which can operate as transmitter or
receiver with their FIFO. Many audio protocols are supported by each block: I2S standards,
LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output, supporting audio sampling
frequencies from 8 kHz up to 192 kHz. Both sub blocks can be configured in master or in
slave mode. The SAIs use a PLL to achieve audio class accuracy.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub blocks can be configured in synchronous mode when full-duplex mode is
required.
SAI1 and SA2 can be served by the DMA controller.
3.29
Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows
to achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
I2S/SAI flow with an external PLL (or Codec output).
3.30
Serial Audio Interface PLL(PLLSAI)
An additional PLL dedicated to audio and USB is used for SAI1 and SAI2 peripheral in case
the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.
The PLLSAI is also used to generate the 48MHz clock for USB FS and SDIO in case the
system PLL is programmed with factors not multiple of 48MHz.
3.31
Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
36/202
DocID027107 Rev 6
STM32F446xC/E
Functional overview
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
3.32
Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.
3.33
Universal serial bus on-the-go full-speed (OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The USB has dedicated power
rails allowing its use throughout the entire power range. The major features are:
3.34
•
Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
•
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•
6 bidirectional endpoints
•
12 host channels with periodic OUT support
•
HNP/SNP/IP inside (no need for any external resistor)
•
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.
The USB OTG HS supports both full-speed and high-speed operations. It integrates the
transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI)
for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an
external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The USB has dedicated power
rails allowing its use throughout the entire power range.
DocID027107 Rev 6
37/202
40
Functional overview
STM32F446xC/E
The major features are:
3.35
•
Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing
•
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•
8 bidirectional endpoints
•
16 host channels with periodic OUT support
•
Internal FS OTG PHY support
•
External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
•
Internal USB DMA
•
HNP/SNP/IP inside (no need for any external resistor)
•
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can sustain a data transfer rate up to 94.5 Mbyte/s (in 14-bit mode) at 54 MHz.
Its features:
3.36
•
Programmable polarity for the input pixel clock and synchronization signals
•
Parallel data communication can be 8-, 10-, 12- or 14-bit
•
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
Supports continuous mode or snapshot (a single frame) mode
•
Capability to automatically crop the image black & white.
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 90 MHz.
3.37
Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
38/202
DocID027107 Rev 6
STM32F446xC/E
Functional overview
Additional logic functions embedded in the ADC interface allow:
•
Simultaneous sample and hold
•
Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
3.38
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the
sensor output voltage into a digital value. When the temperature sensor and VBAT
conversion are enabled at the same time, only VBAT conversion is performed.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
3.39
Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•
two DAC converters: one for each output channel
•
8-bit or 10-bit monotonic output
•
left or right data alignment in 12-bit mode
•
synchronized update capability
•
noise-wave generation
•
triangular-wave generation
•
dual DAC channel independent or simultaneous conversions
•
DMA capability for each channel
•
external triggers for conversion
•
input voltage reference VREF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
3.40
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
DocID027107 Rev 6
39/202
40
Functional overview
STM32F446xC/E
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.41
Embedded Trace Macrocell™
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F446xx through a small number of ETM pins to an external hardware trace port
analyser (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
40/202
DocID027107 Rev 6
STM32F446xC/E
Pinout and pin description
9%$7
3&
3&26&B,1
3&26&B287
3+26&B,1
3+26&B287
1567
3&
3&
3&
3&
966$95()
9''$95()
3$
3$
3$
3%
3%
%227
3%
3%
3%
3%
3%
3'
3&
3&
3&
3$
3$
966
9''
Figure 10. STM32F446xC/xE LQFP64 pinout
/4)3
9''
966
3$
3$
3$
3$
3$
3$
3&
3&
3&
3&
3%
3%
3%
3%
3$
966
9''
3$
3$
3$
3$
3&
3&
3%
3%
3%
3%
9&$3B
966
9''
4
Pinout and pin description
06 9
1. The above figure shows the package top view.
DocID027107 Rev 6
41/202
66
Pinout and pin description
STM32F446xC/E
6$$
633
0%
0%
0"
0"
"//4
0"
0"
0"
0"
0"
0$
0$
0$
0$
0$
0$
0$
0$
0#
0#
0#
0!
0!
Figure 11. STM32F446xC/xE LQFP100 pinout
,1&0
6$$
633
6#!0?
0!
0!
0!
0!
0!
0!
0#
0#
0#
0#
0$
0$
0$
0$
0$
0$
0$
0$
0"
0"
0"
0"
0!
633
6$$
0!
0!
0!
0!
0#
0#
0"
0"
0"
0%
0%
0%
0%
0%
0%
0%
0%
0%
0"
6#!0?
633
6$$
0%
0%
0%
0%
0%
6"!4
0#
0# /3#?).
0# /3#?/54
633
6$$
0( /3#?).
0( /3#?/54
.234
0#
0#
0#
0#
6$$
633!62%&
62%&
6$$!
0!
0!
0!
-36
1. The above figure shows the package top view.
42/202
DocID027107 Rev 6
STM32F446xC/E
Pinout and pin description
/4)3
9 ''
9 66
9 &$3B
3$
3$
3$
3$
3$
3$
3&
3&
3&
3&
9 ''86%
9 66
3*
3*
3*
3*
3*
3*
3*
3'
3'
9 ''
9 66
3'
3'
3'
3'
3'
3'
3%
3%
3%
3%
9 &$3B
9 ''
9 5()
9 ''$
3$
3$
3$
3$
9 66
9 ''
3$
3$
3$
3$
3&
3&
3%
3%
3%
3)
3)
9 66
9 ''
3)
3)
3)
3*
3*
3(
3(
3(
9 66
9 ''
3(
3(
3(
3(
3(
3(
3%
3%
3(
3(
3(
3(
3(
9%$7
3&
3&
3&
3)
3)
3)
3)
3)
3)
9 66
9 ''
3)
3)
3)
3)
3)
3+
3+
15 67
3&
3&
3&
3&
9 ''
9 66$
9 ''
3'5B21
3(
3(
3%
3%
%22 7
3%
3%
3%
3%
3%
3*
9 ''
9 66
3*
3*
3*
3*
3*
3*
3'
3'
9 ''
9 66
3'
3'
3'
3'
3'
3'
3&
3&
3&
3$
3$
Figure 12. STM32F446xC LQFP144 pinout
DL F
1. The above figure shows the package top view.
DocID027107 Rev 6
43/202
66
Pinout and pin description
STM32F446xC/E
Figure 13. STM32F446xC/xE WLCSP81 ballout
$
9''
3&
3'
3'
3%
3%
%227
9''
3(
%
966
3$
3'
3'
3%
3%
966
3'5B
21
9%$7
&
3$
9&$3B
3$
3'
3%
3%
3%
3&
3&
'
3&
3$
3&
3&
3'
3(
3(
15(6(7
3&
(
9''
86%
3$
3$
3$
3$
3$
3$
3&
3+
)
3&
3&
3&
3$
3%
3$
966$
3&
3+
*
3'
3'
3%
3%
3(
3$
3$
966
3&
+
3'
3%
966
3%
3(
3%
3$
9''$
9''
-
3%
9''
9&$3B
3(
3(
3%
3&
%<3$66B
5(*
3$
06Y9
1. The above figure shows the package top view.
44/202
DocID027107 Rev 6
STM32F446xC/E
Pinout and pin description
Figure 14. STM32F446xC/xE UFBGA144 ballout
$
3&
3(
3(
3(
3(
3%
3%
3'
3'
3$
3$
3$
%
3&
3(
3(
3(
3%
3%
3*
3*
3'
3&
3&
3$,
&
3&
9%$7
3)
3)
3%
3%
3*
3*
3'
3&
9''
86%
3$
'
3+
966
9''
3)
%227
3%
3*
3*
3'
3'
3$
3$
(
3+
3)
3)
3)
3'5B
21
966
966
3*
3'
3'
3&
3$
)
1567
3)
3)
9''
9''
9''
9''
9''
9''
9''
3&
3&
*
3)
3)
3)
966
9''
9''
9''
966
9&$3B
966
3*
3&
+
3&
3&
3&
3&
%<3$66
B5(*
966
9&$3B
3(
3'
3*
3*
3*
-
966$
3$
3$
3&
3%
3*
3(
3(
3'
3*
3*
3*
.
95()
3$
3$
3&
3)
3*
3(
3(
3'
3'
3'
3'
/
95()
3$
3$
3%
3)
3)
3(
3(
3'
3'
3%
3%
0
9''$
3$
3$
3%
3)
3)
3(
3(
3%
3%
3%
3%
06Y 9
1. The above picture shows the package top view.
DocID027107 Rev 6
45/202
66
Pinout and pin description
STM32F446xC/E
Table 9. Legend/abbreviations used in the pinout table
Name
Abbreviation
Pin name
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
FTf
5V tolerant IO, I2C FM+ option
TTa
3.3 V tolerant I/O directly connected to ADC
B
Dedicated BOOT0 pin
RST
Bidirectional reset pin with weak pull-up resistor
Pin type
I/O structure
Notes
Definition
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
Table 10. STM32F446xx pin and ball descriptions
D7
A3
1
PE2
I/O FT
-
-
2
D6
A2
2
PE3
I/O FT
-
TRACED0, SAI1_SD_B,
FMC_A19, EVENTOUT
-
-
3
A9
B2
3
PE4
I/O FT
-
TRACED1, SPI4_NSS,
SAI1_FS_A, FMC_A20,
DCMI_D4, EVENTOUT
-
-
TRACED2, TIM9_CH1,
SPI4_MISO, SAI1_SCK_A,
FMC_A21, DCMI_D6,
EVENTOUT
-
-
46/202
4
-
B3
LQFP144
1
WLCSP 81
-
TRACECLK, SPI4_SCK,
SAI1_MCLK_A,
QUADSPI_BK1_IO2,
FMC_A23, EVENTOUT
LQFP100
Alternate functions
LQFP64
Notes
I/O structure
Pin type
UFBGA144
Pin Number
4
Pin name (function
after reset)
PE5
I/O FT
DocID027107 Rev 6
Additional
functions
-
STM32F446xC/E
Pinout and pin description
Table 10. STM32F446xx pin and ball descriptions (continued)
I/O FT
Notes
I/O structure
Pin name (function
after reset)
Pin type
LQFP144
UFBGA144
WLCSP 81
LQFP100
LQFP64
Pin Number
Alternate functions
Additional
functions
-
TRACED3, TIM9_CH2,
SPI4_MOSI, SAI1_SD_A,
FMC_A22, DCMI_D7,
EVENTOUT
-
-
-
-
-
5
-
B4
5
PE6
1
6
B9
C2
6
VBAT
2
7
C8
A1
7
PC13
I/O FT
-
EVENTOUT
TAMP_1/WKUP1
3
8
C9
B1
8
PC14OSC32_IN(PC14)
I/O FT
-
EVENTOUT
OSC32_IN
4
9
D9
C1
9
PC15OSC32_OUT(PC15)
I/O FT
-
EVENTOUT
OSC32_OUT
-
-
-
C3
10
PF0
I/O FT
-
I2C2_SDA, FMC_A0,
EVENTOUT
-
-
-
-
C4
11
PF1
I/O FT
-
I2C2_SCL, FMC_A1,
EVENTOUT
-
-
-
-
D4
12
PF2
I/O FT
-
I2C2_SMBA, FMC_A2,
EVENTOUT
-
-
-
-
E2
13
PF3
I/O FT
-
FMC_A3, EVENTOUT
ADC3_IN9
-
-
-
E3
14
PF4
I/O FT
-
FMC_A4, EVENTOUT
ADC3_IN14
-
-
-
E4
15
PF5
I/O FT
-
FMC_A5, EVENTOUT
ADC3_IN15
-
10
-
D2
16
VSS
S
-
-
-
-
-
11
-
D3
17
VDD
S
-
-
-
-
-
-
-
F3
18
PF6
-
TIM10_CH1, SAI1_SD_B,
QUADSPI_BK1_IO3,
EVENTOUT
ADC3_IN4
ADC3_IN5
S
-
I/O FT
-
-
-
F2
19
PF7
I/O FT
-
TIM11_CH1,
SAI1_MCLK_B,
QUADSPI_BK1_IO2,
EVENTOUT
-
-
-
G3
20
PF8
I/O FT
-
SAI1_SCK_B, TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
ADC3_IN6
-
-
-
G2
21
PF9
I/O FT
-
SAI1_FS_B, TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
ADC3_IN7
-
-
-
G1
22
PF10
I/O FT
-
DCMI_D11, EVENTOUT
ADC3_IN8
5
12
E9
D1
23
PH0-OSC_IN(PH0)
I/O FT
-
EVENTOUT
OSC_IN
DocID027107 Rev 6
47/202
66
Pinout and pin description
STM32F446xC/E
Table 10. STM32F446xx pin and ball descriptions (continued)
UFBGA144
LQFP144
F9
E1
24
PH1OSC_OUT(PH1)
7
14
D8
F1
25
NRST
8
15
G9
H1
26
Notes
WLCSP 81
13
Alternate functions
I/O FT
-
EVENTOUT
OSC_OUT
RS
T
-
-
-
-
SAI1_MCLK_B,
OTG_HS_ULPI_STP,
FMC_SDNWE,
EVENTOUT
ADC123_IN10
ADC123_IN11
I/O
PC0
I/O structure
LQFP100
6
Pin name (function
after reset)
Pin type
LQFP64
Pin Number
I/O FT
Additional
functions
9
16
-
H2
27
PC1
I/O FT
-
SPI3_MOSI/I2S3_SD,
SAI1_SD_A,
SPI2_MOSI/I2S2_SD,
EVENTOUT
10
17
E8
H3
28
PC2
I/O FT
-
SPI2_MISO,
OTG_HS_ULPI_DIR,
FMC_SDNE0, EVENTOUT
ADC123_IN12
-
SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
FMC_SDCKE0,
EVENTOUT
ADC123_IN13
11
18
F8
H4
29
PC3
-
19
H9
-
30
VDD
S
-
-
-
-
-
-
G8
-
-
VSS
S
-
-
-
-
12
20
F7
J1
31
VSSA
S
-
-
-
-
-
-
-
K1
-
VREF-
S
-
-
-
-
-
21
-
L1
32
VREF+
S
-
-
-
-
13
22
H8
M1
33
VDDA
S
-
-
-
-
-
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS,
UART4_TX, EVENTOUT
ADC123_IN0,
WKUP0/TAMP_2
ADC123_IN1
ADC123_IN2
14
23
J9
J2
34
I/O FT
PA0-WKUP(PA0)
I/O FT
15
24
G7
K2
35
PA1
I/O FT
-
TIM2_CH2, TIM5_CH2,
USART2_RTS,
UART4_RX,
QUADSPI_BK1_IO3,
SAI2_MCLK_B,
EVENTOUT
16
25
E7
L2
36
PA2
I/O FT
-
TIM2_CH3, TIM5_CH3,
TIM9_CH1, USART2_TX,
SAI2_SCK_B, EVENTOUT
48/202
DocID027107 Rev 6
STM32F446xC/E
Pinout and pin description
Table 10. STM32F446xx pin and ball descriptions (continued)
Alternate functions
Additional
functions
-
TIM2_CH4, TIM5_CH4,
TIM9_CH2, SAI1_FS_A,
USART2_RX,
OTG_HS_ULPI_D0,
EVENTOUT
ADC123_IN3
17
26
E6
M2
37
PA3
18
27
-
G4
38
VSS
S
-
-
-
-
-
-
J8
H5
-
BYPASS_REG
I
FT
-
-
-
19
28
-
F4
39
VDD
S
-
-
-
-
-
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
OTG_HS_SOF,
DCMI_HSYNC,
EVENTOUT
ADC12_IN4,
DAC_OUT1
-
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
OTG_HS_ULPI_CK,
EVENTOUT
ADC12_IN5,
DAC_OUT2
-
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
I2S2_MCK, TIM13_CH1,
DCMI_PIXCLK,
EVENTOUT
ADC12_IN6
ADC12_IN7
20
21
22
29
30
31
H7
F6
G6
J3
K3
L3
40
41
42
PA4
PA5
PA6
I/O FT
Notes
I/O structure
Pin name (function
after reset)
Pin type
LQFP144
UFBGA144
WLCSP 81
LQFP100
LQFP64
Pin Number
I/O TC
I/O TC
I/O FT
23
32
E5
M3
43
PA7
I/O FT
-
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SD,
TIM14_CH1,
FMC_SDNWE,
EVENTOUT
24
33
J7
J4
44
PC4
I/O FT
-
I2S1_MCK, SPDIFRX_IN2,
FMC_SDNE0, EVENTOUT
ADC12_IN14
-
USART3_RX,
SPDIFRX_IN3,
FMC_SDCKE0,
EVENTOUT
ADC12_IN15
25
34
-
K4
45
PC5
I/O FT
DocID027107 Rev 6
49/202
66
Pinout and pin description
STM32F446xC/E
Table 10. STM32F446xx pin and ball descriptions (continued)
27
35
36
H6
L4
M4
46
47
PB0
PB1
I/O structure
Pin type
LQFP144
UFBGA144
WLCSP 81
F5
Pin name (function
after reset)
I/O FT
I/O FT
Notes
26
LQFP100
LQFP64
Pin Number
Alternate functions
Additional
functions
-
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
SPI3_MOSI/I2S3_SD,
UART4_CTS,
OTG_HS_ULPI_D1,
SDIO_D1, EVENTOUT
ADC12_IN8
-
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
OTG_HS_ULPI_D2,
SDIO_D2, EVENTOUT
ADC12_IN9
-
28
37
J6
J5
48
PB2-BOOT1
(PB2)
I/O FT
-
TIM2_CH4, SAI1_SD_A,
SPI3_MOSI/I2S3_SD,
QUADSPI_CLK,
OTG_HS_ULPI_D4,
SDIO_CK, EVENTOUT
-
-
-
M5
49
PF11
I/O FT
-
SAI2_SD_B,
FMC_SDNRAS,
DCMI_D12, EVENTOUT
-
-
-
-
L5
50
PF12
I/O FT
-
FMC_A6, EVENTOUT
-
-
-
-
-
51
VSS
S
-
-
-
-
-
-
-
G5
52
VDD
S
-
-
-
-
-
-
-
K5
53
PF13
I/O FT
-
FMPI2C1_SMBA,
FMC_A7, EVENTOUT
-
-
-
-
M6
54
PF14
I/O FTf
-
FMPI2C1_SCL, FMC_A8,
EVENTOUT
-
-
-
-
L6
55
PF15
I/O FTf
-
FMPI2C1_SDA, FMC_A9,
EVENTOUT
-
-
-
-
K6
56
PG0
I/O FT
-
FMC_A10, EVENTOUT
-
-
-
-
J6
57
PG1
I/O FT
-
FMC_A11, EVENTOUT
-
-
38
J5
M7
58
PE7
I/O FT
-
TIM1_ETR, UART5_RX,
QUADSPI_BK2_IO0,
FMC_D4, EVENTOUT
-
-
39
H5
L7
59
PE8
I/O FT
-
TIM1_CH1N, UART5_TX,
QUADSPI_BK2_IO1,
FMC_D5, EVENTOUT
-
-
40
G5
K7
60
PE9
I/O FT
-
TIM1_CH1,
QUADSPI_BK2_IO2,
FMC_D6, EVENTOUT
-
50/202
DocID027107 Rev 6
STM32F446xC/E
Pinout and pin description
Table 10. STM32F446xx pin and ball descriptions (continued)
LQFP64
LQFP100
WLCSP 81
UFBGA144
LQFP144
Pin name (function
after reset)
Pin type
I/O structure
Notes
Pin Number
Alternate functions
-
-
-
H6
61
VSS
S
-
-
-
-
-
-
-
G6
62
VDD
S
-
-
-
-
-
41
J4
J7
63
PE10
I/O FT
-
TIM1_CH2N,
QUADSPI_BK2_IO3,
FMC_D7, EVENTOUT
-
-
42
-
H8
64
PE11
I/O FT
-
TIM1_CH2, SPI4_NSS,
SAI2_SD_B, FMC_D8,
EVENTOUT
-
-
43
-
J8
65
PE12
I/O FT
-
TIM1_CH3N, SPI4_SCK,
SAI2_SCK_B, FMC_D9,
EVENTOUT
-
-
44
-
K8
66
PE13
I/O FT
-
TIM1_CH3, SPI4_MISO,
SAI2_FS_B, FMC_D10,
EVENTOUT
-
-
45
-
L8
67
PE14
I/O FT
-
TIM1_CH4, SPI4_MOSI,
SAI2_MCLK_B, FMC_D11,
EVENTOUT
-
-
46
-
M8
68
PE15
I/O FT
-
TIM1_BKIN, FMC_D12,
EVENTOUT
-
-
Additional
functions
29
47
H4
M9
69
PB10
I/O FT
-
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
SAI1_SCK_A,
USART3_TX,
OTG_HS_ULPI_D3,
EVENTOUT
-
-
-
M10
70
PB11
I/O FT
-
TIM2_CH4, I2C2_SDA,
USART3_RX, SAI2_SD_A,
EVENTOUT
-
30
48
J3
H7
71
VCAP_1
S
-
-
-
-
31
49
H3
-
-
VSS
S
-
-
-
-
32
50
J2
G7
72
VDD
S
-
-
-
-
-
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
SAI1_SCK_B,
USART3_CK, CAN2_RX,
OTG_HS_ULPI_D5,
OTG_HS_ID, EVENTOUT
-
33
51
G4
M11
73
PB12
I/O FT
DocID027107 Rev 6
51/202
66
Pinout and pin description
STM32F446xC/E
Table 10. STM32F446xx pin and ball descriptions (continued)
35
52
53
J1
M12
L11
74
75
PB13
PB14(1)
I/O structure
Pin type
LQFP144
UFBGA144
WLCSP 81
H2
Pin name (function
after reset)
I/O FT
I/O FT
Notes
34
LQFP100
LQFP64
Pin Number
Alternate functions
Additional
functions
-
TIM1_CH1N,
SPI2_SCK/I2S2_CK,
USART3_CTS, CAN2_TX,
OTG_HS_ULPI_D6,
EVENTOUT
OTG_HS_VBUS
-
TIM1_CH2N, TIM8_CH2N,
SPI2_MISO,
USART3_RTS,
TIM12_CH1,
OTG_HS_DM, EVENTOUT
-
-
36
54
G3
L12
76
PB15(1)
I/O FT
-
RTC_REFIN, TIM1_CH3N,
TIM8_CH3N,
SPI2_MOSI/I2S2_SD,
TIM12_CH2, OTG_HS_DP,
EVENTOUT
-
55
-
L9
77
PD8
I/O FT
-
USART3_TX,
SPDIFRX_IN1, FMC_D13,
EVENTOUT
-
-
56
-
K9
78
PD9
I/O FT
-
USART3_RX, FMC_D14,
EVENTOUT
-
-
57
-
J9
79
PD10
I/O FT
-
USART3_CK, FMC_D15,
EVENTOUT
-
-
FMPI2C1_SMBA,
USART3_CTS,
QUADSPI_BK1_IO0,
SAI2_SD_A, FMC_A16,
EVENTOUT
-
-
TIM4_CH1,
FMPI2C1_SCL,
USART3_RTS,
QUADSPI_BK1_IO1,
SAI2_FS_A, FMC_A17,
EVENTOUT
-
-
TIM4_CH2,
FMPI2C1_SDA,
QUADSPI_BK1_IO3,
SAI2_SCK_A, FMC_A18,
EVENTOUT
-
-
-
58
59
H1
G2
H9
L10
80
81
PD11
PD12
I/O FT
I/O FTf
-
60
G1
K10
82
PD13
-
-
-
G8
83
VSS
S
-
-
-
-
-
-
-
F8
84
VDD
S
-
-
-
-
52/202
I/O FTf
DocID027107 Rev 6
STM32F446xC/E
Pinout and pin description
Table 10. STM32F446xx pin and ball descriptions (continued)
-
K11
85
PD14
I/O FTf
-
-
62
-
K12
86
PD15
I/O FTf
-
TIM4_CH4,
FMPI2C1_SDA, FMC_D1,
EVENTOUT
-
-
-
-
J12
87
PG2
I/O FT
-
FMC_A12, EVENTOUT
-
-
-
-
J11
88
PG3
I/O FT
-
FMC_A13, EVENTOUT
-
-
-
-
J10
89
PG4
I/O FT
-
FMC_A14/FMC_BA0,
EVENTOUT
-
-
-
-
H12
90
PG5
I/O FT
-
FMC_A15/FMC_BA1,
EVENTOUT
-
-
-
-
H11
91
PG6
I/O FT
-
QUADSPI_BK1_NCS,
DCMI_D12, EVENTOUT
-
-
-
-
H10
92
PG7
I/O FT
-
USART6_CK, FMC_INT,
DCMI_D13, EVENTOUT
-
-
-
-
G11
93
PG8
I/O FT
-
SPDIFRX_IN2,
USART6_RTS,
FMC_SDCLK, EVENTOUT
-
-
-
-
-
94
VSS
S
-
-
-
-
-
-
-
F10
-
VDD
S
-
-
-
-
-
-
E1
C11
95
VDDUSB
S
-
-
-
-
-
TIM3_CH1, TIM8_CH1,
FMPI2C1_SCL,
I2S2_MCK, USART6_TX,
SDIO_D6, DCMI_D0,
EVENTOUT
-
-
TIM3_CH2, TIM8_CH2,
FMPI2C1_SDA,
SPI2_SCK/I2S2_CK,
I2S3_MCK, SPDIFRX_IN1,
USART6_RX, SDIO_D7,
DCMI_D1, EVENTOUT
-
-
TRACED0, TIM3_CH3,
TIM8_CH3, UART5_RTS,
USART6_CK, SDIO_D0,
DCMI_D2, EVENTOUT
-
37
38
39
63
64
65
F1
F2
F3
G12
F12
F11
LQFP144
61
WLCSP 81
-
TIM4_CH3,
FMPI2C1_SCL,
SAI2_SCK_A, FMC_D0,
EVENTOUT
LQFP100
Alternate functions
LQFP64
Notes
I/O structure
Pin type
UFBGA144
Pin Number
96
97
98
Pin name (function
after reset)
PC6
PC7
PC8
I/O FTf
I/O FTf
I/O FT
DocID027107 Rev 6
Additional
functions
-
53/202
66
Pinout and pin description
STM32F446xC/E
Table 10. STM32F446xx pin and ball descriptions (continued)
41
66
67
E2
E11
E12
99
100
PC9
PA8
I/O structure
Pin type
LQFP144
UFBGA144
WLCSP 81
D1
Pin name (function
after reset)
I/O FT
I/O FT
Notes
40
LQFP100
LQFP64
Pin Number
Alternate functions
Additional
functions
-
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, UART5_CTS,
QUADSPI_BK1_IO0,
SDIO_D1, DCMI_D3,
EVENTOUT
-
-
MCO1, TIM1_CH1,
I2C3_SCL, USART1_CK,
OTG_FS_SOF,
EVENTOUT
-
OTG_FS_VBUS
42
68
F4
D12
101
PA9
I/O FT
-
TIM1_CH2, I2C3_SMBA,
SPI2_SCK/I2S2_CK,
SAI1_SD_B, USART1_TX,
DCMI_D0, EVENTOUT
43
69
E3
D11
102
PA10
I/O FT
-
TIM1_CH3, USART1_RX,
OTG_FS_ID, DCMI_D1,
EVENTOUT
-
44
70
C1
C12
103
PA11(1)
I/O FT
-
TIM1_CH4, USART1_CTS,
CAN1_RX, OTG_FS_DM,
EVENTOUT
-
45
71
E4
B12
104
PA12(1)
I/O FT
-
TIM1_ETR, USART1_RTS,
SAI2_FS_B, CAN1_TX,
OTG_FS_DP, EVENTOUT
-
46
72
D2
A12
105 PA13(JTMS-SWDIO) I/O FT
-
JTMS-SWDIO,
EVENTOUT
-
-
73
C2
G9
106
47
74
B1
G10 107
48
75
A1
F9
108
49
76
C3
A11
109 PA14(JTCK-SWCLK) I/O FT
50
77
54/202
B2
A10
110
VCAP_2
S
-
-
-
-
VSS
S
-
-
-
-
VDD
S
-
-
-
-
-
JTCK-SWCLK,
EVENTOUT
-
-
JTDI,
TIM2_CH1/TIM2_ETR,
HDMI_CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
UART4_RTS, EVENTOUT
-
PA15(JTDI)
I/O FT
DocID027107 Rev 6
STM32F446xC/E
Pinout and pin description
Table 10. STM32F446xx pin and ball descriptions (continued)
52
53
78
79
80
D4
A2
B11
B10
C10
111
112
113
PC10
PC11
PC12
I/O structure
Pin type
LQFP144
UFBGA144
WLCSP 81
D3
Pin name (function
after reset)
I/O FT
I/O FT
I/O FT
Notes
51
LQFP100
LQFP64
Pin Number
Alternate functions
Additional
functions
-
SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
QUADSPI_BK1_IO1,
SDIO_D2, DCMI_D8,
EVENTOUT
-
-
SPI3_MISO, USART3_RX,
UART4_RX,
QUADSPI_BK2_NCS,
SDIO_D3, DCMI_D4,
EVENTOUT
-
-
I2C2_SDA,
SPI3_MOSI/I2S3_SD,
USART3_CK, UART5_TX,
SDIO_CK, DCMI_D9,
EVENTOUT
-
-
-
81
B3
E10
114
PD0
I/O FT
-
SPI4_MISO,
SPI3_MOSI/I2S3_SD,
CAN1_RX, FMC_D2,
EVENTOUT
-
82
C4
D10
115
PD1
I/O FT
-
SPI2_NSS/I2S2_WS,
CAN1_TX, FMC_D3,
EVENTOUT
-
54
83
D5
E9
116
PD2
I/O FT
-
TIM3_ETR, UART5_RX,
SDIO_CMD, DCMI_D11,
EVENTOUT
-
-
-
84
-
D9
117
PD3
I/O FT
-
TRACED1,
SPI2_SCK/I2S2_CK,
USART2_CTS,
QUADSPI_CLK,
FMC_CLK, DCMI_D5,
EVENTOUT
-
85
A3
C9
118
PD4
I/O FT
-
USART2_RTS, FMC_NOE,
EVENTOUT
-
-
86
-
B9
119
PD5
I/O FT
-
USART2_TX, FMC_NWE,
EVENTOUT
-
-
-
-
E7
120
VSS
S
-
-
-
-
-
-
-
F7
121
VDD
S
-
-
-
-
DocID027107 Rev 6
55/202
66
Pinout and pin description
STM32F446xC/E
Table 10. STM32F446xx pin and ball descriptions (continued)
B4
A8
122
PD6
I/O FT
-
-
88
A4
A9
123
PD7
I/O FT
-
USART2_CK,
SPDIFRX_IN0, FMC_NE1,
EVENTOUT
-
-
LQFP144
87
WLCSP 81
-
SPI3_MOSI/I2S3_SD,
SAI1_SD_A, USART2_RX,
FMC_NWAIT, DCMI_D10,
EVENTOUT
LQFP100
Alternate functions
LQFP64
Notes
I/O structure
Pin type
UFBGA144
Pin Number
Pin name (function
after reset)
Additional
functions
-
-
-
-
E8
124
PG9
I/O FT
-
SPDIFRX_IN3,
USART6_RX,
QUADSPI_BK2_IO2,
SAI2_FS_B,
FMC_NE2/FMC_NCE3,
DCMI_VSYNC,
EVENTOUT
-
-
-
D8
125
PG10
I/O FT
-
SAI2_SD_B, FMC_NE3,
DCMI_D2, EVENTOUT
-
-
-
-
C8
126
PG11
I/O FT
-
SPI4_SCK, SPDIFRX_IN0,
DCMI_D3, EVENTOUT
-
-
-
-
-
B8
127
PG12
I/O FT
-
SPI4_MISO,
SPDIFRX_IN1,
USART6_RTS, FMC_NE4,
EVENTOUT
-
-
-
D7
128
PG13
I/O FT
-
TRACED2, SPI4_MOSI,
USART6_CTS, FMC_A24,
EVENTOUT
-
-
TRACED3, SPI4_NSS,
USART6_TX,
QUADSPI_BK2_IO3,
FMC_A25, EVENTOUT
-
-
-
-
C7
129
PG14
-
-
-
-
130
VSS
S
-
-
-
-
-
-
-
F6
131
VDD
S
-
-
-
-
-
-
-
B7
132
PG15
-
USART6_CTS,
FMC_SDNCAS,
DCMI_D13, EVENTOUT
-
-
JTDO/TRACESWO,
TIM2_CH2, I2C2_SDA,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
EVENTOUT
-
55
89
56/202
A5
A7
133
I/O FT
I/O FT
PB3(JTDO/TRACES
WO)
I/O FT
DocID027107 Rev 6
STM32F446xC/E
Pinout and pin description
Table 10. STM32F446xx pin and ball descriptions (continued)
57
58
90
91
92
A6
C5
A6
B6
C6
134
135
136
PB4(NJTRST)
PB5
PB6
59
93
B6
D6
137
PB7
60
94
A7
D5
138
BOOT0
61
62
95
96
C6
C7
C5
B5
139
140
PB8
PB9
I/O structure
Pin type
LQFP144
UFBGA144
WLCSP 81
B5
Pin name (function
after reset)
I/O FT
I/O FT
I/O FT
I/O FT
I
B
I/O FT
I/O FT
Notes
56
LQFP100
LQFP64
Pin Number
Alternate functions
Additional
functions
-
NJTRST, TIM3_CH1,
I2C3_SDA, SPI1_MISO,
SPI3_MISO,
SPI2_NSS/I2S2_WS,
EVENTOUT
-
-
TIM3_CH2, I2C1_SMBA,
SPI1_MOSI/I2S1_SD,
SPI3_MOSI/I2S3_SD,
CAN2_RX,
OTG_HS_ULPI_D7,
FMC_SDCKE1,
DCMI_D10, EVENTOUT
-
-
TIM4_CH1, HDMI_CEC,
I2C1_SCL, USART1_TX,
CAN2_TX,
QUADSPI_BK1_NCS,
FMC_SDNE1, DCMI_D5,
EVENTOUT
-
-
TIM4_CH2, I2C1_SDA,
USART1_RX,
SPDIFRX_IN0, FMC_NL,
DCMI_VSYNC,
EVENTOUT
-
-
-
VPP
-
TIM2_CH1/TIM2_ETR,
TIM4_CH3, TIM10_CH1,
I2C1_SCL, CAN1_RX,
SDIO_D4, DCMI_D6,
EVENTOUT
-
-
TIM2_CH2, TIM4_CH4,
TIM11_CH1, I2C1_SDA,
SPI2_NSS/I2S2_WS,
SAI1_FS_B, CAN1_TX,
SDIO_D5, DCMI_D7,
EVENTOUT
-
-
-
-
97
-
A5
141
PE0
I/O FT
-
TIM4_ETR,
SAI2_MCLK_A,
FMC_NBL0, DCMI_D2,
EVENTOUT
-
98
-
A4
142
PE1
I/O FT
-
FMC_NBL1, DCMI_D3,
EVENTOUT
DocID027107 Rev 6
57/202
66
Pinout and pin description
STM32F446xC/E
Table 10. STM32F446xx pin and ball descriptions (continued)
LQFP64
LQFP100
WLCSP 81
UFBGA144
LQFP144
Pin name (function
after reset)
Pin type
I/O structure
Notes
Pin Number
Alternate functions
63
99
B7
E6
-
VSS
S
-
-
-
-
-
-
B8
E5
143
PDR_ON
S
-
-
-
-
64
100
A8
F5
144
VDD
S
-
-
-
-
1. PA11, PA12, PB14 and PB15 I/Os are supplied by VDDUSB
58/202
DocID027107 Rev 6
Additional
functions
AF0
AF1
AF2
AF3
AF4
AF5
I2C1/2/3
/4/CEC
SPI1/2/3/
4
Port
AF6
AF7
AF8
AF9
SPI2/3/
SAI/
CAN1/2
USART1/
SPI2/3/4/
USART6/ TIM12/13/
2/3/UART
SAI1
UART4/5/
14/
5/SPDIFR
SPDIFRX QUADSPI
X
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/
QUADSPI/
OTG2_HS/
OTG1_FS
OTG1_FS
FMC/
SDIO/
OTG2_FS
DCMI
-
SYS
DocID027107 Rev 6
TIM1/2
TIM3/4/5
PA0
-
TIM2_CH1/
TIM2_ETR
TIM5_CH1
TIM8_ETR
-
-
-
USART2_
CTS
UART4_
TX
-
-
-
-
-
-
EVENT
OUT
PA1
-
TIM2_CH2
TIM5_CH2
-
-
-
-
USART2_
RTS
UART4_
RX
QUADSPI_
BK1_IO3
SAI2_
MCLK_B
-
-
-
-
EVENT
OUT
PA2
-
TIM2_CH3
TIM5_CH3
TIM9_CH1
-
-
-
USART2_
TX
SAI2_
SCK_B
-
-
-
-
-
-
EVENT
OUT
PA3
-
TIM2_CH4
TIM5_CH4
TIM9_CH2
-
-
SAI1_
FS_A
USART2_
RX
-
-
OTG_HS_
ULPI_D0
-
-
-
-
EVENT
OUT
PA4
-
-
-
-
-
SPI1_NSS/I
2S1_WS
SPI3_NSS
/
I2S3_WS
USART2_
CK
-
-
-
-
OTG_HS_
SOF
DCMI_
HSYNC
-
EVENT
OUT
PA5
-
TIM2_CH1/
TIM2_ETR
-
TIM8_
CH1N
-
SPI1_SCK/I
2S1_CK
-
-
-
-
OTG_HS_
ULPI_CK
-
-
-
-
EVENT
OUT
PA6
-
TIM1_
BKIN
TIM3_CH1
TIM8_
BKIN
-
SPI1_MISO
I2S2_
MCK
-
-
TIM13_CH1
-
-
-
DCMI_
PIXCLK
-
EVENT
OUT
PA7
-
TIM1_
CH1N
TIM3_CH2
TIM8_
CH1N
-
SPI1_MOSI
/
I2S1_SD
-
-
-
TIM14_CH1
-
-
FMC_
SDNWE
-
-
EVENT
OUT
PA8
MCO1
TIM1_CH1
-
-
I2C3_
SCL
-
-
USART1_
CK
-
-
OTG_FS_
SOF
-
-
-
-
EVENT
OUT
PA9
-
TIM1_CH2
-
-
I2C3_
SMBA
SPI2_SCK
/I2S2_CK
SAI1_
SD_B
USART1_
TX
-
-
-
-
-
DCMI_D0
-
EVENT
OUT
PA10
-
TIM1_CH3
-
-
-
-
-
USART1_
RX
-
-
OTG_FS_
ID
-
-
DCMI_D1
-
EVENT
OUT
PA11
-
TIM1_CH4
-
-
-
-
-
USART1_
CTS
-
CAN1_RX
OTG_FS_
DM
-
-
-
-
EVENT
OUT
PA12
-
TIM1_ETR
-
-
-
-
-
USART1_
RTS
SAI2_
FS_B
CAN1_TX
OTG_FS_
DP
-
-
-
-
EVENT
OUT
PA13
JTMSSWDIO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PA14
JTCKSWCLK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PA15
JTDI
TIM2_CH1/
TIM2_ETR
-
-
HDMI_
CEC
SPI1_NSS/
I2S1_WS
SPI3_
NSS/
I2S3_WS
-
UART4_RT
S
-
-
-
-
-
-
EVENT
OUT
Port A
Pinout and pin description
59/202
SYS
TIM8/9/
10/11/
CEC
STM32F446xC/E
Table 11. Alternate function
AF0
AF1
AF2
AF3
AF4
AF5
I2C1/2/3
/4/CEC
SPI1/2/3/
4
Port
DocID027107 Rev 6
Port B
AF6
AF7
AF8
AF9
SPI2/3/
SAI/
CAN1/2
USART1/
SPI2/3/4/
USART6/ TIM12/13/
2/3/UART
SAI1
UART4/5/
14/
5/SPDIFR
SPDIFRX QUADSPI
X
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/
QUADSPI/
OTG2_HS/
OTG1_FS
OTG1_FS
FMC/
SDIO/
OTG2_FS
DCMI
-
SYS
TIM1/2
TIM3/4/5
PB0
-
TIM1_CH2N
TIM3_CH3
TIM8_
CH2N
-
-
-
SPI3_MOS
I/
I2S3_SD
UART4_
CTS
-
OTG_HS_
ULPI_D1
-
SDIO_D1
-
-
EVENT
OUT
PB1
-
TIM1_CH3N
TIM3_CH4
TIM8_
CH3N
-
-
-
-
-
-
OTG_HS_
ULPI_D2
-
SDIO_D2
-
-
EVENT
OUT
PB2
-
TIM2_CH4
-
-
-
-
SAI1_
SD_A
SPI3_MOS
I/
I2S3_SD
-
QUADSPI_
CLK
OTG_HS_
ULPI_D4
-
SDIO_CK
-
-
EVENT
OUT
PB3
JTDO/
TRACES
WO
TIM2_CH2
-
-
I2C2_
SDA
SPI1_SCK
/I2S1_CK
SPI3_SCK
/
I2S3_CK
-
-
-
-
-
-
-
-
EVENT
OUT
PB4
NJTRST
-
TIM3_CH1
-
I2C3_
SDA
SPI1_MISO
SPI3_
MISO
SPI2_NSS/
I2S2_WS
-
-
-
-
-
-
-
EVENT
OUT
PB5
-
-
TIM3_CH2
-
I2C1_
SMBA
SPI1_MOSI
/I2S1_SD
SPI3_
MOSI/
I2S3_SD
-
-
CAN2_RX
OTG_HS_
ULPI_D7
-
FMC_
SDCKE1
DCMI_
D10
-
EVENT
OUT
PB6
-
-
TIM4_CH1
HDMI_
CEC
I2C1_
SCL
-
-
USART1_
TX
-
CAN2_TX
QUADSPI_
BK1_NCS
-
FMC_
SDNE1
DCMI_D5
-
EVENT
OUT
PB7
-
-
TIM4_CH2
-
I2C1_
SDA
-
-
USART1_
RX
SPDIF_
RX0
-
-
-
FMC_NL
DCMI_
VSYNC
-
EVENT
OUT
PB8
-
TIM2_CH1/
TIM2_ETR
TIM4_CH3
TIM10_
CH1
I2C1_
SCL
-
-
-
-
CAN1_RX
-
-
SDIO_D4
DCMI_D6
-
EVENT
OUT
PB9
-
TIM2_
CH2
TIM4_CH4
TIM11_
CH1
I2C1_
SDA
SPI2_NSS/
I2S2_WS
SAI1_
FS_B
-
-
CAN1_TX
-
-
SDIO_D5
DCMI_D7
-
EVENT
OUT
PB10
-
TIM2_CH3
-
-
I2C2_
SCL
SPI2_SCK/
I2S2_CK
SAI1_
SCK_A
USART3_
TX
-
-
OTG_HS_
ULPI_D3
-
-
-
-
EVENT
OUT
PB11
-
TIM2_CH4
-
-
I2C2_
SDA
-
-
USART3_
RX
SAI2_
SD_A
-
-
-
-
-
-
EVENT
OUT
PB12
-
TIM1_BKIN
-
-
I2C2_
SMBA
SPI2_NSS/
I2S2_WS
SAI1_
SCK_B
USART3_
CK
-
CAN2_RX
OTG_HS_
ULPI_D5
-
OTG_
HS_ID
-
-
EVENT
OUT
PB13
-
TIM1_CH1N
-
-
-
SPI2_SCK/
I2S2_CK
-
USART3_
CTS
-
CAN2_TX
OTG_HS_
ULPI_D6
-
-
-
-
EVENT
OUT
PB14
-
TIM1_CH2N
-
TIM8_
CH2N
-
SPI2_MISO
-
USART3_
RTS
-
TIM12_CH1
-
-
OTG_
HS_DM
-
-
EVENT
OUT
PB15
RTC_
REFIN
TIM1_CH3N
-
TIM8_
CH3N
-
SPI2_MOSI
/I2S2_SD
-
-
-
TIM12_CH2
-
-
OTG_
HS_DP
-
-
EVENT
OUT
STM32F446xC/E
SYS
TIM8/9/
10/11/
CEC
Pinout and pin description
60/202
Table 11. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
I2C1/2/3
/4/CEC
SPI1/2/3/
4
Port
AF6
AF7
AF8
AF9
SPI2/3/
SAI/
CAN1/2
USART1/
SPI2/3/4/
USART6/ TIM12/13/
2/3/UART
SAI1
UART4/5/
14/
5/SPDIFR
SPDIFRX QUADSPI
X
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/
QUADSPI/
OTG2_HS/
OTG1_FS
OTG1_FS
FMC/
SDIO/
OTG2_FS
DCMI
-
SYS
DocID027107 Rev 6
TIM1/2
TIM3/4/5
PC0
-
-
-
-
-
-
SAI1_
MCLK_B
-
-
-
OTG_HS_
ULPI_STP
-
FMC_
SDNWE
-
-
EVENT
OUT
PC1
-
-
-
-
-
SPI3_MOSI
/I2S3_SD
SAI1_
SD_A
SPI2_MOS
I
/I2S2_SD
-
-
-
-
-
-
-
EVENT
OUT
PC2
-
-
-
-
-
SPI2_MISO
-
-
-
-
OTG_HS_
ULPI_DIR
-
FMC_
SDNE0
-
-
EVENT
OUT
PC3
-
-
-
-
-
SPI2_MOSI
/
I2S2_SD
-
-
-
-
OTG_HS_
ULPI_NXT
-
FMC_
SDCKE0
-
-
EVENT
OUT
PC4
-
-
-
-
-
I2S1_MCK
-
-
SPDIF_
RX2
-
-
-
FMC_
SDNE0
-
-
EVENT
OUT
PC5
-
-
-
-
-
-
-
USART3_
RX
SPDIF_
RX3
-
-
-
FMC_
SDCKE0
-
-
EVENT
OUT
PC6
-
-
TIM3_CH1
TIM8_CH1
FMPI2C1
_SCL
I2S2_MCK
-
-
USART6_T
X
-
-
-
SDIO_D6
DCMI_D0
-
EVENT
OUT
PC7
-
-
TIM3_CH2
TIM8_CH2
FMPI2C1
_SDA
SPI2_SCK/
I2S2_CK
I2S3_MCK
SPDIF_
RX1
USART6_R
X
-
-
-
SDIO_D7
DCMI_D1
-
EVENT
OUT
PC8
TRACE
D0
-
TIM3_CH3
TIM8_CH3
-
-
-
UART5_
RTS
USART6_C
K
-
-
-
SDIO_D0
DCMI_D2
-
EVENT
OUT
PC9
MCO2
-
TIM3_CH4
TIM8_CH4
I2C3_
SDA
I2S_CKIN
-
UART5_
CTS
-
QUADSPI_
BK1_IO0
-
-
SDIO_D1
DCMI_D3
-
EVENT
OUT
PC10
-
-
-
-
-
-
SPI3_SCK
/
I2S3_CK
USART3_
TX
UART4_TX
QUADSPI_
BK1_IO1
-
-
SDIO_D2
DCMI_D8
-
EVENT
OUT
PC11
-
-
-
-
-
-
SPI3_
MISO
USART3_
RX
UART4_RX
QUADSPI_
BK2_NCS
-
-
SDIO_D3
DCMI_D4
-
EVENT
OUT
PC12
-
-
-
-
I2C2_
SDA
-
SPI3_
MOSI/
I2S3_SD
USART3_
CK
UART5_TX
-
-
-
SDIO_CK
DCMI_D9
-
EVENT
OUT
PC13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
Port C
Pinout and pin description
61/202
SYS
TIM8/9/
10/11/
CEC
STM32F446xC/E
Table 11. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
I2C1/2/3
/4/CEC
SPI1/2/3/
4
Port
DocID027107 Rev 6
Port D
AF6
AF7
AF8
AF9
SPI2/3/
SAI/
CAN1/2
USART1/
SPI2/3/4/
USART6/ TIM12/13/
2/3/UART
SAI1
UART4/5/
14/
5/SPDIFR
SPDIFRX QUADSPI
X
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/
QUADSPI/
OTG2_HS/
OTG1_FS
OTG1_FS
FMC/
SDIO/
OTG2_FS
DCMI
-
SYS
TIM1/2
TIM3/4/5
PD0
-
-
-
-
-
SPI4_MISO
SPI3_
MOSI/
I2S3_SD
-
-
CAN1_RX
-
-
FMC_D2
-
-
EVENT
OUT
PD1
-
-
-
-
-
-
-
SPI2_NSS/
I2S2_WS
-
CAN1_TX
-
-
FMC_D3
-
-
EVENT
OUT
PD2
-
-
TIM3_ETR
-
-
-
-
-
UART5_RX
-
-
-
SDIO_CMD
DCMI_
D11
-
EVENT
OUT
PD3
TRACE
D1
-
-
-
-
SPI2_SCK/
I2S2_CK
-
USART2_
CTS
-
QUADSPI_
CLK
-
-
FMC_CLK
DCMI_
D5
-
EVENT
OUT
PD4
-
-
-
-
-
-
-
USART2_
RTS
-
-
-
-
FMC_NOE
-
-
EVENT
OUT
PD5
-
-
-
-
-
-
-
USART2_
TX
-
-
-
-
FMC_NWE
-
-
EVENT
OUT
PD6
-
-
-
-
-
SPI3_
MOSI/
I2S3_SD
SAI1_
SD_A
USART2_
RX
-
-
-
-
FMC_
NWAIT
DCMI_
D10
-
EVENT
OUT
PD7
-
-
-
-
-
-
-
USART2_
CK
SPDIF_
RX0
-
-
-
FMC_NE1
-
-
EVENT
OUT
PD8
-
-
-
-
-
-
-
USART3_
TX
SPDIF_
RX1
-
-
-
FMC_D13
-
-
EVENT
OUT
PD9
-
-
-
-
-
-
-
USART3_
RX
-
-
-
-
FMC_D14
-
-
EVENT
OUT
PD10
-
-
-
-
-
-
-
USART3_
CK
-
-
-
-
FMC_D15
-
-
EVENT
OUT
PD11
-
-
-
-
FMPI2C1
_SMBA
-
-
USART3_
CTS
-
QUADSPI_
BK1_IO0
SAI2_SD_A
-
FMC_A16
-
-
EVENT
OUT
PD12
-
-
TIM4_CH1
-
FMPI2C1
_SCL
-
-
USART3_
RTS
-
QUADSPI_
BK1_IO1
SAI2_FS_A
-
FMC_A17
-
-
EVENT
OUT
PD13
-
-
TIM4_CH2
-
FMPI2C1
_SDA
-
-
-
-
QUADSPI_
BK1_IO3
SAI2_SCK_A
-
FMC_A18
-
-
EVENT
OUT
PD14
-
-
TIM4_CH3
-
FMPI2C1
_SCL
-
-
-
SAI2_
SCK_A
-
-
-
FMC_D0
-
-
EVENT
OUT
PD15
-
-
TIM4_CH4
-
FMPI2C1
_SDA
-
-
-
-
-
-
-
FMC_D1
-
-
EVENT
OUT
STM32F446xC/E
SYS
TIM8/9/
10/11/
CEC
Pinout and pin description
62/202
Table 11. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
I2C1/2/3
/4/CEC
SPI1/2/3/
4
Port
AF6
AF7
AF8
AF9
SPI2/3/
SAI/
CAN1/2
USART1/
SPI2/3/4/
USART6/ TIM12/13/
2/3/UART
SAI1
UART4/5/
14/
5/SPDIFR
SPDIFRX QUADSPI
X
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/
QUADSPI/
OTG2_HS/
OTG1_FS
OTG1_FS
FMC/
SDIO/
OTG2_FS
DCMI
-
SYS
DocID027107 Rev 6
TIM1/2
TIM3/4/5
PE0
-
-
TIM4_ETR
-
-
-
-
-
-
-
SAI2_
MCLK_A
-
FMC_
NBL0
DCMI_D2
-
EVENT
OUT
PE1
-
-
-
-
-
-
-
-
-
-
-
-
FMC_
NBL1
DCMI_D3
-
EVENT
OUT
PE2
TRACE
CLK
-
-
-
-
SPI4_SCK
SAI1_
MCLK_A
-
-
QUADSPI_
BK1_IO2
-
-
FMC_A23
-
-
EVENT
OUT
PE3
TRACE
D0
-
-
-
-
-
SAI1_
SD_B
-
-
-
-
-
FMC_A19
-
-
EVENT
OUT
PE4
TRACE
D1
-
-
-
-
SPI4_NSS
SAI1_
FS_A
-
-
-
-
-
FMC_A20
DCMI_D4
-
EVENT
OUT
PE5
TRACE
D2
-
-
TIM9_CH1
-
SPI4_MISO
SAI1_
SCK_A
-
-
-
-
-
FMC_A21
DCMI_D6
-
EVENT
OUT
PE6
TRACE
D3
-
-
TIM9_CH2
-
SPI4_MOSI
SAI1_
SD_A
-
-
-
-
-
FMC_A22
DCMI_D7
-
EVENT
OUT
PE7
-
TIM1_ETR
-
-
-
-
-
-
UART5_RX
-
QUADSPI_
BK2_IO0
-
FMC_D4
-
-
EVENT
OUT
PE8
-
TIM1_CH1N
-
-
-
-
-
-
UART5_TX
-
QUADSPI_
BK2_IO1
-
FMC_D5
-
-
EVENT
OUT
PE9
-
TIM1_CH1
-
-
-
-
-
-
-
-
QUADSPI_
BK2_IO2
-
FMC_D6
-
-
EVENT
OUT
PE10
-
TIM1_CH2N
-
-
-
-
-
-
-
-
QUADSPI_
BK2_IO3
-
FMC_D7
-
-
EVENT
OUT
PE11
-
TIM1_CH2
-
-
-
SPI4_NSS
-
-
-
-
-
FMC_D8
-
-
EVENT
OUT
PE12
-
TIM1_CH3N
-
-
-
SPI4_SCK
-
-
-
-
SAI2_
SCK_B
-
FMC_D9
-
-
EVENT
OUT
PE13
-
TIM1_CH3
-
-
-
SPI4_MISO
-
-
-
-
SAI2_
FS_B
-
FMC_D10
-
-
EVENT
OUT
PE14
-
TIM1_CH4
-
-
-
SPI4_MOSI
-
-
-
-
SAI2_
MCLK_B
-
FMC_D11
-
-
EVENT
OUT
PE15
-
TIM1_BKIN
-
-
-
-
-
-
-
-
-
-
FMC_D12
-
-
EVENT
OUT
Port E
SAI2_
SD_B
63/202
Pinout and pin description
SYS
TIM8/9/
10/11/
CEC
STM32F446xC/E
Table 11. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
I2C1/2/3
/4/CEC
SPI1/2/3/
4
Port
AF6
AF7
AF8
AF9
SPI2/3/
SAI/
CAN1/2
USART1/
SPI2/3/4/
USART6/ TIM12/13/
2/3/UART
SAI1
UART4/5/
14/
5/SPDIFR
SPDIFRX QUADSPI
X
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/
QUADSPI/
OTG2_HS/
OTG1_FS
OTG1_FS
FMC/
SDIO/
OTG2_FS
DCMI
-
SYS
DocID027107 Rev 6
SYS
TIM1/2
TIM3/4/5
TIM8/9/
10/11/
CEC
PF0
-
-
-
-
I2C2_
SDA
-
-
-
-
-
-
-
FMC_A0
-
-
EVENT
OUT
PF1
-
-
-
-
I2C2_
SCL
-
-
-
-
-
-
-
FMC_A1
-
-
EVENT
OUT
PF2
-
-
-
-
I2C2_
SMBA
-
-
-
-
-
-
-
FMC_A2
-
-
EVENT
OUT
PF3
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A3
-
-
EVENT
OUT
PF4
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A4
-
-
EVENT
OUT
PF5
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A5
-
-
EVENT
OUT
PF6
-
-
-
TIM10_
CH1
-
-
SAI1_
SD_B
-
-
QUADSPI_
BK1_IO3
-
-
-
-
-
EVENT
OUT
PF7
-
-
-
TIM11_
CH1
-
-
SAI1_
MCLK_B
-
-
QUADSPI_
BK1_IO2
-
-
-
-
-
EVENT
OUT
PF8
-
-
-
-
-
-
SAI1_
SCK_B
-
-
TIM13_CH1
QUADSPI_
BK1_IO0
-
-
-
-
EVENT
OUT
PF9
-
-
-
-
-
-
SAI1_
FS_B
-
-
TIM14_CH1
QUADSPI_
BK1_IO1
-
-
-
-
EVENT
OUT
PF10
-
-
-
-
-
-
-
-
-
-
-
-
-
DCMI_
D11
-
EVENT
OUT
PF11
-
-
-
-
-
-
-
-
-
-
SAI2_SD_B
-
FMC_
SDNRAS
DCMI_
D12
-
EVENT
OUT
PF12
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A6
-
-
EVENT
OUT
PF13
-
-
-
-
FMPI2C1
_SMBA
-
-
-
-
-
-
-
FMC_A7
-
-
EVENT
OUT
PF14
-
-
-
-
FMPI2C1
_SCL
-
-
-
-
-
-
-
FMC_A8
-
-
EVENT
OUT
PF15
-
-
-
-
FMPI2C1
_SDA
-
-
-
-
-
-
-
FMC_A9
-
-
EVENT
OUT
Pinout and pin description
64/202
Table 11. Alternate function (continued)
Port F
STM32F446xC/E
AF0
AF1
AF2
AF3
AF4
AF5
I2C1/2/3
/4/CEC
SPI1/2/3/
4
Port
DocID027107 Rev 6
Port G
AF6
AF7
AF8
AF9
SPI2/3/
SAI/
CAN1/2
USART1/
SPI2/3/4/
USART6/ TIM12/13/
2/3/UART
SAI1
UART4/5/
14/
5/SPDIFR
SPDIFRX QUADSPI
X
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/
QUADSPI/
OTG2_HS/
OTG1_FS
OTG1_FS
FMC/
SDIO/
OTG2_FS
DCMI
-
SYS
TIM1/2
TIM3/4/5
PG0
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A10
-
-
EVENT
OUT
PG1
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A11
-
-
EVENT
OUT
PG2
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A12
-
-
EVENT
OUT
PG3
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A13
-
-
EVENT
OUT
PG4
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A14/
FMC_BA0
-
-
EVENT
OUT
PG5
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A15/
FMC_BA1
-
-
EVENT
OUT
PG6
-
-
-
-
-
-
-
-
-
-
QUADSPI_
BK1_NCS
-
-
DCMI_
D12
-
EVENT
OUT
PG7
-
-
-
-
-
-
-
-
USART6_C
K
-
-
-
FMC_INT
DCMI_
D13
-
EVENT
OUT
PG8
-
-
-
-
-
-
-
SPDIFRX_
IN2
USART6_R
TS
-
-
-
FMC_
SDCLK
-
-
EVENT
OUT
PG9
-
-
-
-
-
-
-
SPDIFRX_
IN3
USART6_R
X
QUADSPI_
BK2_IO2
SAI2_FS_B
-
FMC_NE2/
FMC_NCE3
DCMI_
VSYNC(1)
-
EVENT
OUT
PG10
-
-
-
-
-
-
-
-
-
-
SAI2_SD_B
-
FMC_NE3
DCMI_D2
-
EVENT
OUT
PG11
-
-
-
-
-
-
SPI4_
SCK
SPDIFRX_
IN0
-
-
-
-
-
DCMI_D3
-
EVENT
OUT
PG12
-
-
-
-
-
-
SPI4_
MISO
SPDIFRX_
IN1
USART6_R
TS
-
-
-
FMC_NE4
-
-
EVENT
OUT
PG13
TRACE
D2
-
-
-
-
-
SPI4_
MOSI
-
USART6_C
TS
-
-
-
FMC_A24
-
-
EVENT
OUT
PG14
TRACE
D3
-
-
-
-
-
SPI4_
NSS
-
USART6_T
X
QUADSPI_
BK2_IO3
-
-
FMC_A25
-
-
EVENT
OUT
PG15
-
-
-
-
-
-
-
-
USART6_C
TS
-
-
-
FMC_
SDNCAS
DCMI_
D13
-
EVENT
OUT
65/202
Pinout and pin description
SYS
TIM8/9/
10/11/
CEC
STM32F446xC/E
Table 11. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
I2C1/2/3
/4/CEC
SPI1/2/3/
4
Port
AF6
AF7
AF8
AF9
SPI2/3/
SAI/
CAN1/2
USART1/
SPI2/3/4/
USART6/ TIM12/13/
2/3/UART
SAI1
UART4/5/
14/
5/SPDIFR
SPDIFRX QUADSPI
X
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/
QUADSPI/
OTG2_HS/
OTG1_FS
OTG1_FS
FMC/
SDIO/
OTG2_FS
DCMI
-
SYS
SYS
TIM1/2
TIM3/4/5
TIM8/9/
10/11/
CEC
PH0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
Port H
1.
Pinout and pin description
66/202
Table 11. Alternate function (continued)
The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3.
DocID027107 Rev 6
STM32F446xC/E
STM32F446xC/E
5
Memory mapping
Memory mapping
The memory map is shown in Figure 15
Figure 15. Memory map
[))))))))
5HVHUYHG
[([))))))))
&RUWH[0LQWHUQDO
SHULSKHUDOV
[([()))))
$+%
[[')))))))
5HVHUYHG
[&[)))))))
[%))
$+%
0E\WH
%ORFN
&RUWH[0
,QWHUQDO
SHULSKHUDOV
5HVHUYHG
[
[[)))))))
[))))
[(
[')))))))
0E\WH
%ORFN
)0&
['
[&)))))))
$+%
0E\WH
%ORFN
)0&4XDG63,
[$
[ )))))))
[
[)))))))
0E\WH
%ORFN
)0&EDQN
DQG4XDG63,
[
5HVHUYHG
[&[))))
[%))
0E\WH
%ORFN
)0&EDQN
[
[)))))))
$3%
0E\WH
%ORFN
3HULSKHUDOV
[
[)))))))
0E\WH
%ORFN
65$0
[
[)))))))
0E\WH
%ORFN
65$0
[
5HVHUYHG
[[)))))))
5HVHUYHG
[[))))
65$0 .%DOLDVHG
%\ELWEDQGLQJ
65$0 .%DOLDVHG
%\ELWEDQGLQJ
[&[))))
5HVHUYHG
[)))&[)))))))
2SWLRQ%\WHV
[)))&[)))&)
5HVHUYHG
6\VWHPPHPRU\
5HVHUYHG
2SWLRQE\WHV
[)))$[))))))
[)))[)))$)
[))(&[))())))
[))(&[))(&)
[
[[))))
[)))
[[%)))
5HVHUYHG
[[))(%)))
5HVHUYHG
[[))))
5HVHUYHG
[[)))))))
)ODVKPHPRU\
[[)))))
5HVHUYHG
$OLDVHGWR)ODVKV\VWHP
PHPRU\RU65$0GHSHQGLQJ
RQWKH%227SLQV
5HVHUYHG
$3%
[[))))))
[
[[)))))
DocID027107 Rev 6
069
67/202
71
Memory mapping
STM32F446xC/E
Table 12. STM32F446xC/E register boundary addresses(1)
Bus
Boundary address
-
0xE00F FFFF - 0xFFFF FFFF
Reserved
Cortex-M4
0xE000 0000 - 0xE00F FFFF
Cortex-M4 internal peripherals
0xD000 0000 - 0xDFFF FFFF
FMC bank 6
0xC000 0000 - 0xCFFF FFFF
FMC bank 5
AHB3
0xA000 2000 - 0x0xBFFF FFFF
Reserved
0xA000 1000 - 0x0xA000 1FFF
QuadSPI control register
0xA000 0000 - 0xA000 0FFF
FMC control register
0x9000 0000 - 0x9FFF FFFF
QuadSPI
0x8000 0000 - 0x8FFF FFFF
FMC bank 3
0x7000 0000 - 0x0x7FFF FFFF
-
AHB2
68/202
Peripheral
Reserved
0x6000 0000 - 0x6FFF FFFF
FMC bank 1
0x5006 0C00- 0x5FFF FFFF
Reserved
0x5006 0800- 0x500F 07FF
Reserved
0x5005 0400 - 0x5006 07FF
Reserved
0x5005 0000 - 0x5005 03FF
DCMI
0x5004 0000- 0x5004 FFFF
Reserved
0x5000 0000 - 0X5003 FFFF
USB OTG FS
DocID027107 Rev 6
STM32F446xC/E
Memory mapping
Table 12. STM32F446xC/E register boundary addresses(1) (continued)
Bus
Boundary address
Peripheral
-
0x4008 0000- 0x4FFF FFFF
Reserved
0x4004 0000 - 0x4007 FFFF
USB OTG HS
0x4002 BC00- 0x4003 FFFF
0x4002 B000 - 0x4002 BBFF
0x4002 9400 - 0x4002 AFFF
0x4002 9000 - 0x4002 93FF
0x4002 8C00 - 0x4002 8FFF
Reserved
0x4002 8800 - 0x4002 8BFF
0x4002 8400 - 0x4002 87FF
0x4002 8000 - 0x4002 83FF
0x4002 6800 - 0x4002 7FFF
AHB1
0x4002 6400 - 0x4002 67FF
DMA2
0x4002 6000 - 0x4002 63FF
DMA1
0X4002 5000 - 0X4002 5FFF
Reserved
0x4002 4000 - 0x4002 4FFF
BKPSRAM
0x4002 3C00 - 0x4002 3FFF
Flash interface register
0x4002 3800 - 0x4002 3BFF
RCC
0X4002 3400 - 0X4002 37FF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2C00 - 0x4002 2FFF
0x4002 2800 - 0x4002 2BFF
0x4002 2400 - 0x4002 27FF
Reserved
0x4002 2000 - 0x4002 23FF
0x4002 1C00 - 0x4002 1FFF
GPIOH
0x4002 1800 - 0x4002 1BFF
GPIOG
0x4002 1400 - 0x4002 17FF
GPIOF
0x4002 1000 - 0x4002 13FF
GPIOE
0X4002 0C00 - 0x4002 0FFF
GPIOD
0x4002 0800 - 0x4002 0BFF
GPIOC
0x4002 0400 - 0x4002 07FF
GPIOB
0x4002 0000 - 0x4002 03FF
GPIOA
DocID027107 Rev 6
69/202
71
Memory mapping
STM32F446xC/E
Table 12. STM32F446xC/E register boundary addresses(1) (continued)
Bus
Boundary address
-
0x4001 6C00- 0x4001 FFFF
0x4001 6800 - 0x4001 6BFF
Peripheral
Reserved
0x4001 5C00 - 0x4001 5FFF
SAI2
0x4001 6000 - 0x4001 67FF
Reserved
0x4001 5800 - 0x4001 5BFF
SAI1
0x4001 5400 - 0x4001 57FF
0x4001 5000 - 0x4001 53FF
Reserved
0x4001 4C00 - 0x4001 4FFF
APB2
70/202
0x4001 4800 - 0x4001 4BFF
TIM11
0x4001 4400 - 0x4001 47FF
TIM10
0x4001 4000 - 0x4001 43FF
TIM9
0x4001 3C00 - 0x4001 3FFF
EXTI
0x4001 3800 - 0x4001 3BFF
SYSCFG
0x4001 3400 - 0x4001 37FF
SPI4
0x4001 3000 - 0x4001 33FF
SPI1
0x4001 2C00 - 0x4001 2FFF
SDIO
0x4001 2400 - 0x4001 2BFF
Reserved
0x4001 2000 - 0x4001 23FF
ADC1 - ADC2 - ADC3
0x4001 1800 - 0x4001 1FFF
Reserved
0x4001 1400 - 0x4001 17FF
USART6
0x4001 1000 - 0x4001 13FF
USART1
0x4001 0800 - 0x4001 0FFF
Reserved
0x4001 0400 - 0x4001 07FF
TIM8
0x4001 0000 - 0x4001 03FF
TIM1
DocID027107 Rev 6
STM32F446xC/E
Memory mapping
Table 12. STM32F446xC/E register boundary addresses(1) (continued)
Bus
Boundary address
-
0x4000 8000- 0x4000 FFFF
0x4000 7C00 - 0x4000 7FFF
Peripheral
Reserved
0x4000 7800 - 0x4000 7BFF
APB1
0x4000 7400 - 0x4000 77FF
DAC
0x4000 7000 - 0x4000 73FF
PWR
0x4000 6C00 - 0x4000 6FFF
HDMI-CEC
0x4000 6800 - 0x4000 6BFF
CAN2
0x4000 6400 - 0x4000 67FF
CAN1
0x4000 6000 - 0x4000 63FF
FMPI2C1
0x4000 5C00 - 0x4000 5FFF
I2C3
0x4000 5800 - 0x4000 5BFF
I2C2
0x4000 5400 - 0x4000 57FF
I2C1
0x4000 5000 - 0x4000 53FF
UART5
0x4000 4C00 - 0x4000 4FFF
UART4
0x4000 4800 - 0x4000 4BFF
USART3
0x4000 4400 - 0x4000 47FF
USART2
0x4000 4000 - 0x4000 43FF
SPDIFRX
0x4000 3C00 - 0x4000 3FFF
SPI3 / I2S3
0x4000 3800 - 0x4000 3BFF
SPI2 / I2S2
0x4000 3400 - 0x4000 37FF
Reserved
0x4000 3000 - 0x4000 33FF
IWDG
0x4000 2C00 - 0x4000 2FFF
WWDG
0x4000 2800 - 0x4000 2BFF
RTC & BKP Registers
0x4000 2400 - 0x4000 27FF
Reserved
0x4000 2000 - 0x4000 23FF
TIM14
0x4000 1C00 - 0x4000 1FFF
TIM13
0x4000 1800 - 0x4000 1BFF
TIM12
0x4000 1400 - 0x4000 17FF
TIM7
0x4000 1000 - 0x4000 13FF
TIM6
0x4000 0C00 - 0x4000 0FFF
TIM5
0x4000 0800 - 0x4000 0BFF
TIM4
0x4000 0400 - 0x4000 07FF
TIM3
0x4000 0000 - 0x4000 03FF
TIM2
1. The grey color is used for reserved boundary addresses.
DocID027107 Rev 6
71/202
71
Electrical characteristics
STM32F446xC/E
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 16.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 17.
Figure 16. Pin loading conditions
Figure 17. Pin input voltage
-#5 PIN
-#5 PIN
# P&
6).
-36
72/202
DocID027107 Rev 6
-36
STM32F446xC/E
6.1.6
Electrical characteristics
Power supply scheme
Figure 18. Power supply scheme
9%$7
9%$7
WR9
*3,2V
,1
î)
9''
îQ)
î)
9''86%
9&$3B
9&$3B
966
,2
/RJLF
.HUQHOORJLF
&38GLJLWDO
5$0
9ROWDJH
UHJXODWRU
%<3$66B5(*
5HVHW
FRQWUROOHU
3'5B21
9''
)ODVKPHPRU\
27*
)6
3+<
9''86%
Q)
)
9''$
95()
Q)
)
/HYHOVKLIWHU
287
9''
%DFNXSFLUFXLWU\
26&.57&
:DNHXSORJLF
%DFNXSUHJLVWHUV
EDFNXS5$0
3RZHU
VZLWFK
Q)
)
95()
$'&
95()
$QDORJ
5&V
3//
966$
06Y9
1. VDDA and VSSA must be connected to VDDand VSS, respectively.
2. VDDUSB is a dedicated independent USB power supply for the on-chip full-speed OTG PHY module and
associated DP/DM GPIOs. Its value is independent from the VDD and VDDA values, but must be the last
supply to be provided and the first to disappear. If VDD is different from VDDUSB and only one on-chip OTG
PHY is used, the second OTG PHY GPIOs (DP/DM) are still supplied at VDDUSB (3.3V).
3. VDDUSB is available only on WLCSP81, UFBGA144 and LQFP144 packages. For packages where VDDUSB
pin is not available, it is internally connected to VDD.
4. VCAP_2 pad is not available on LQFP64.
Caution:
Each power supply pair (VDD/VSS, VDDA/VSSA...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
DocID027107 Rev 6
73/202
175
Electrical characteristics
6.1.7
STM32F446xC/E
Current consumption measurement
Figure 19. Current consumption measurement scheme
,''B9%$7
9%$7
,''
9''
9''$
9''86%
06Y9
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 13: Voltage characteristics,
Table 14: Current characteristics, and Table 15: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 13. Voltage characteristics
Symbol
VDD–VSS
VIN
Ratings
Min
Max
–0.3
4.0
Input voltage on FT & FTf pins(2)
VSS–0.3
VDD+4.0
Input voltage on TTa pins
VSS–0.3
4.0
Input voltage on any other pin
VSS–0.3
4.0
VSS
9.0
Variations between different VDD power pins
-
50
Variations between all the different ground pins
-
50
External main supply voltage (including VDDA, VDD,
VDDUSB and VBAT)(1)
Input voltage on BOOT0 pin
|ΔVDDx|
|VSSX −VSS|
VESD(HBM)
Electrostatic discharge voltage (human body model)
Unit
V
mV
see Section 6.3.15:
Absolute maximum
ratings (electrical
sensitivity)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Table 14 for the values of the maximum allowed
injected current.
74/202
DocID027107 Rev 6
-
STM32F446xC/E
Electrical characteristics
Table 14. Current characteristics
Symbol
Ratings
Max.
ΣIVDD
Total current into sum of all VDD power lines (source)(1)
Σ IVSS
(1)
Σ IVDDUSB
25
Maximum current into each VDD power pin (source)(1)
IVSS
(1)
ΣIIO
ΣIINJ(PIN)
100
- 100
Output current sunk by any I/O and control pin
25
Output current sourced by any I/Os and control pin
- 25
Total output current sunk by sum of all I/Os and control pins (2)
120
Total output current sunk by sum of all USB I/Os
25
Total output current sourced by sum of all I/Os and control
IINJ(PIN)
- 240
Total current into VDDUSB power line (source)
IVDD
IIO
240
Total current out of sum of all VSS ground lines (sink)
Maximum current out of each VSS ground pin (sink)
Unit
pins(2)
Injected current on FT, FTf, RST and B pins
mA
-120
–5/+0(3)
Injected current on TTa pins
±5(4)
Total injected current (sum of all I/O and control pins)(5)
±25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified
maximum value.
4. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –
5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 55.
Table 55. I/O current injection susceptibility(1)
Functional susceptibility
Symbol
IINJ
Description
Negative
injection
Positive
injection
Injected current on BOOT0 pin
–0
NA
Injected current on NRST pin
–0
NA
Injected current on PE2, PE3,PE4, PE5, PE6, PC13, PC14,
PF10, PH0, PH1, NRST, PC0, PC1, PC2, PC3, PG15, PB3,
PB4, PB5, PB6, PB7, PB8, PB9, PE0, PE1
–0
NA
Injected current on any other FT and FTf pins
-5
NA
Injected current on any other pins
–5
+5
Unit
mA
1. NA = not applicable.
Note:
It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
DocID027107 Rev 6
117/202
175
Electrical characteristics
6.3.17
STM32F446xC/E
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 56: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 16. All I/Os are
CMOS and TTL compliant.
Table 56. I/O static characteristics
Symbol
VIL
Parameter
-
BOOT0 I/O input low level
voltage
1.75 V ≤ VDD ≤
3.6 V,
– 40 °C≤ TA ≤
105 °C
-
-
1.7 V ≤ VDD ≤ 3.6 V,
0 °C ≤ TA ≤105 °C
-
BOOT0 I/O input high level
voltage
BOOT0 I/O input hysteresis
I/O input leakage current (3)
I/O FT input leakage current
(4)
Max
Unit
(1)
-
VHYS
118/202
Typ
1.7 V≤VDD≤3.6 V
FT, FTf, TTa and NRST I/O
input hysteresis
Ilkg
Min
FT, FTf, TTa and NRST I/O
input low level voltage
FT, FTf, TTa and NRST I/O
input high level voltage(4)
VIH
Conditions
1.7 V≤VDD≤3.6 V
1.75 V≤VDD ≤3.6 V,
– 40 °C≤TA ≤105 °C
0.35VDD–0.04
0.3VDD(2)
V
0.1VDD+0.1(1)
0.45VDD+0.3(1)
0.7VDD(2)
-
V
0.17VDD+0.7(1)
-
-
1.7 V≤VDD≤3.6 V
-
10%VDD
-
1.75 V≤VDD ≤3.6 V,
–40 °C≤TA ≤105 °C
-
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
-
VSS ≤VIN ≤VDD
-
-
±1
VIN = 5 V
-
-
3
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
DocID027107 Rev 6
-
V
100m
-
µA
STM32F446xC/E
Electrical characteristics
Table 56. I/O static characteristics (continued)
Symbol
Parameter
RPU
All pins
except for
PA10/PB12
Weak pull-up (OTG_FS_ID,
equivalent
OTG_HS_ID)
resistor(5)
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
RPD
CIO(7)
Weak pulldown
equivalent
resistor(6)
All pins
except for
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
Conditions
Typ
Max
30
40
50
7
10
14
Unit
VIN = VSS
kΩ
30
40
50
7
10
14
-
5
-
VIN = VDD
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
I/O pin capacitance
Min
-
pF
1. Guaranteed by design.
2. Tested in production.
3. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 55: I/O
current injection susceptibility
4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 55: I/O current injection
susceptibility
5. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the
series resistance is minimum (~10% order).
6. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
7.
Hysteresis voltage between Schmitt trigger switching levels. Guaranteed based on test during characterization.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 31.
DocID027107 Rev 6
119/202
175
Electrical characteristics
STM32F446xC/E
Figure 31. FT I/O input characteristics
9,/9,+ 9
'
9'
L
P
,+
Q
9
QW
H
P
LUH 77/UHTXLUHPHQW
U
9,+PLQ 9
26
0
&
'
9'
Q
R
WL
XF
LQ
RG
+P
,
SU
9
LQ
QV
WLR
HG
VW
XOD
P
L
7H
V
LJQ
HV
$UHDQRW
Q'
R
G
VH
GHWHUPLQHG
''
D
%
9
D[
,/P
QV9
ODWLR
X
LP
V
VLJQ
Q'H
HGR
77/UHTXLUHPHQW9,/PD[
%DV
9
7HVWHGLQSURGXFWLRQ&026UHTXLUHPHQW9,/PD[ 9''
X
HT
9'' 9
069
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can
sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed
should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 14).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 14).
Output voltage levels
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 16. All I/Os are CMOS and TTL compliant.
120/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
Table 57. Output voltage characteristics
Symbol
Parameter
VOL(1)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
VOL (1)
Output low level voltage for an I/O pin
VOH (3)
Output high level voltage for an I/O pin
VOL(1)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
VOL(1)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
VOL(1)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
Conditions
Min
Max
CMOS port(2)
IIO = +8 mA
2.7 V ≤VDD ≤3.6 V
-
0.4
VDD–0.4
-
-
0.4
2.4
-
-
1.3(4)
VDD–1.3(4)
-
-
0.4(4)
VDD–0.4(4)
-
-
0.4(5)
VDD–0.4(5)
-
TTL port(2)
IIO =+ 8mA
2.7 V ≤VDD ≤3.6 V
IIO = +20 mA
2.7 V ≤VDD ≤3.6 V
IIO = +6 mA
1.8 V ≤VDD ≤3.6 V
IIO = +4 mA
1.7 V ≤VDD ≤3.6V
Unit
V
V
V
V
V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 14.
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 14 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Based on characterization data.
5. Guaranteed by design.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 32 and
Table 58, respectively.
Unless otherwise specified, the parameters given in Table 58 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 16.
Table 58. I/O AC characteristics(1)(2)
OSPEEDR
y[1:0] bit
value(1)
Symbol
fmax(IO)out
Parameter
Maximum frequency(3)
00
tf(IO)out/
tr(IO)out
Output high to low level fall
time and output low to high
level rise time
Conditions
Min
Typ
Max
CL = 50 pF, VDD ≥ 2.7 V
-
-
4
CL = 50 pF, VDD ≥ 1.7 V
-
-
2
CL = 10 pF, VDD ≥ 2.7 V
-
-
8
CL = 10 pF, VDD ≥ 1.8 V
-
-
4
CL = 10 pF, VDD ≥ 1.7 V
-
-
3
CL = 50 pF, VDD = 1.7 V
to 3.6 V
-
-
100
DocID027107 Rev 6
Unit
MHz
ns
121/202
175
Electrical characteristics
STM32F446xC/E
Table 58. I/O AC characteristics(1)(2) (continued)
OSPEEDR
y[1:0] bit
value(1)
Symbol
fmax(IO)out
Parameter
Maximum frequency(3)
01
tf(IO)out/
tr(IO)out
fmax(IO)out
Output high to low level fall
time and output low to high
level rise time
Maximum frequency(3)
10
tf(IO)out/
tr(IO)out
fmax(IO)out
Output high to low level fall
time and output low to high
level rise time
Maximum frequency(3)
11
tf(IO)out/
tr(IO)out
-
122/202
tEXTIpw
Output high to low level fall
time and output low to high
level rise time
Conditions
Min
Typ
Max
CL = 50 pF, VDD≥ 2.7 V
-
-
25
CL = 50 pF, VDD≥ 1.8 V
-
-
12.5
CL = 50 pF, VDD≥ 1.7 V
-
-
10
CL = 10 pF, VDD ≥ 2.7 V
-
-
50
CL = 10 pF, VDD≥ 1.8 V
-
-
20
CL = 10 pF, VDD≥ 1.7 V
-
-
12.5
CL = 50 pF, VDD ≥ 2.7 V
-
-
10
CL = 10 pF, VDD ≥ 2.7 V
-
-
6
CL = 50 pF, VDD ≥ 1.7 V
-
-
20
CL = 10 pF, VDD ≥ 1.7 V
-
-
10
CL = 40 pF, VDD ≥ 2.7 V
-
-
50(4)
CL = 10 pF, VDD ≥ 2.7 V
-
-
100(4)
CL = 40 pF, VDD ≥ 1.7 V
-
-
25
CL = 10 pF, VDD ≥ 1.8 V
-
-
50
CL = 10 pF, VDD ≥ 1.7 V
-
-
42.5
CL = 40 pF, VDD ≥2.7 V
-
-
6
CL = 10 pF, VDD ≥ 2.7 V
-
-
4
CL = 40 pF, VDD ≥ 1.7 V
-
-
10
CL = 10 pF, VDD ≥ 1.7 V
-
-
6
CL = 30 pF, VDD ≥ 2.7 V
-
-
100(4)
CL = 30 pF, VDD ≥ 1.8 V
-
-
50
CL = 30 pF, VDD ≥ 1.7 V
-
-
42.5
CL = 10 pF, VDD≥ 2.7 V
-
-
180(4)
CL = 10 pF, VDD ≥ 1.8 V
-
-
100
CL = 10 pF, VDD ≥ 1.7 V
-
-
72.5
CL = 30 pF, VDD ≥ 2.7 V
-
-
4
CL = 30 pF, VDD ≥1.8 V
-
-
6
CL = 30 pF, VDD ≥1.7 V
-
-
7
CL = 10 pF, VDD ≥ 2.7 V
-
-
2.5
CL = 10 pF, VDD ≥1.8 V
-
-
3.5
CL = 10 pF, VDD ≥1.7 V
-
-
4
10
-
-
Pulse width of external
signals detected by the EXTI
controller
DocID027107 Rev 6
-
Unit
MHz
ns
MHz
ns
MHz
ns
ns
STM32F446xC/E
Electrical characteristics
1. Guaranteed by design.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of
the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 32.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.
Figure 32. I/O AC characteristics definition
(;7(51$/
287387
21&/
WU ,2 RXW
WI ,2 RXW
7
0D[LPXPIUHTXHQF\LVDFKLHYHGLI WUWI 7DQGLIWKHGXW\F\FOHLV
ZKHQORDGHGE\&/VSHFLILHGLQWKHWDEOH³,2$&FKDUDFWHULVWLFV´
6.3.18
DLG
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 56: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 16.
Table 59. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RPU
Weak pull-up equivalent resistor(1)
VIN = VSS
30
40
50
kΩ
-
-
-
100
ns
VDD > 2.7 V
300
-
-
ns
Internal Reset source
20
-
-
µs
VF(NRST)(2)
NRST Input filtered pulse
VNF(NRST)(2) NRST Input not filtered pulse
TNRST_OUT
Generated reset pulse duration
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
2. Guaranteed by design.
DocID027107 Rev 6
123/202
175
Electrical characteristics
STM32F446xC/E
Figure 33. Recommended NRST pin protection
9''
([WHUQDO
UHVHWFLUFXLW
538
1567
,QWHUQDO5HVHW
)LOWHU
)
670)
DLF
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 59. Otherwise the reset is not taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
6.3.19
TIM timer characteristics
The parameters given in Table 60 are guaranteed by design.
Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 60. TIMx characteristics(1)(2)
Symbol
Conditions(3)
Min
Max
Unit
AHB/APBx prescaler=1 or
2 or 4, fTIMxCLK = 180 MHz
1
-
tTIMxCLK
AHB/APBx prescaler>4,
fTIMxCLK = 90 MHz
1
-
tTIMxCLK
0
fTIMxCLK/2
MHz
-
16/32
bit
-
65536 × 65536
tTIMxCLK
Parameter
tres(TIM)
Timer resolution time
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK = 180 MHz
Timer resolution
ResTIM
tMAX_COUNT
Maximum possible count with
32-bit counter
-
1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR
register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK = 4x PCLKx.
6.3.20
Communications interfaces
I2C interface characteristics
The I2C interface meets the requirements of the standard I2C communication protocol with
the following restrictions: the I/O pins SDA and SCL too are mapped as not “true”
open-drain. When configured as open-drain, the PMOS connected between the I/O pin and
VDD is disabled, but is still present.
124/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
The I2C characteristics are described in Table 61. Refer also to Section 6.3.17: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 61. I2C characteristics
Symbol
Parameter
Standard mode
I2C(1)(2)
Fast mode I2C(1)(2)
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
tsu(SDA)
SDA setup time
250
-
100
-
-
3450(3)
-
900(4)
-
3.45
-
0.9
th(SDA)
SDA data hold time
tv(SDA, ACK) Data, ACK valid time
µs
ns
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1000
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
300
-
300
th(STA)
Start condition hold time
4.0
-
0.6
-
tsu(STA)
Repeated Start condition
setup time
4.7
-
0.6
-
tsu(STO)
Stop condition setup time
4.0
-
0.6
-
µs
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
-
1.3
-
µs
tSP
Pulse width of the spikes
that are suppressed by the
analog filter for standard and
fast mode
-
-
0.05
0.09(5)
µs
Cb
Capacitive load for each bus
line
-
400
-
400
pF
µs
1. Guaranteed based on test during characterization.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode
clock.
3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
5. The minimum width of the spikes filtered by the analog filter is above tSP(max).
DocID027107 Rev 6
125/202
175
Electrical characteristics
STM32F446xC/E
Figure 34. I2C bus AC waveforms and measurement circuit
s ''B,&
s ''B,&
53
53
670)[[
56
6'$
,ð&EXV
56
6&/
67$575(3($7('
67$57
67$57
WVX 67$
6'$
WI 6'$
WU 6'$
WK 67$
WVX 6'$
WZ 6&/+
WZ 672 67$
6723
WK 6'$
6&/
WZ 6&//
WU 6&/
WI 6&/
WVX 672
DL F
1. RS = series protection resistor.
2. RP = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.
126/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
FMPI2C characteristics
The FMPI2C characteristics are described in Table 62.
Refer also to Section 6.3.17: I/O port characteristics for more details on the input/output
alternate function characteristics (SDA and SCL).
Table 62. FMPI2C characteristics(1)
Standard mode
-
fFMPI2CC
Fast mode
Fast+ mode
Parameter
Unit
Min
Max
Min
Max
Min
Max
2
-
8
-
17
16(2)
-
FMPI2CCLK frequency
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
0.5
-
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
0.26
-
tsu(SDA)
SDA setup time
0.25
-
0.10
-
0.05
-
tH(SDA)
SDA data hold time
0
-
0
-
0
-
-
3.45
-
0.9
-
0.45
tv(SDA,ACK) Data, ACK valid time
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
0.100
-
0.30
-
0.12
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
0.30
-
0.30
-
0.12
th(STA)
Start condition hold time
4
-
0.6
-
0.26
-
tsu(STA)
Repeated Start condition
setup time
4.7
-
0.6
-
0.26
-
tsu(STO)
Stop condition setup time
4
-
0.6
-
0.26
-
4.7
-
1.3
-
0.5
-
tSP
Pulse width of the spikes that
are suppressed by the
analog filter for standard and
fast mode
-
-
0.05
0.09
0.05
0.09
Cb
Capacitive load for each bus
Line
-
400
-
400
-
550(3)
tw(STO:STA) Stop to Start condition time
(bus free)
us
pF
1. Guaranteed based on test during characterization.
2. When tr(SDA,SCL)<=110ns.
3. Can be limited. Maximum supported value can be retrieved by referring to the following formulas:
tr(SDA/SCL) = 0.8473 x Rp x Cload
Rp(min) = (VDD -VOL(max)) / IOL(max)
DocID027107 Rev 6
127/202
175
Electrical characteristics
STM32F446xC/E
Figure 35. FMPI2C timing diagram and measurement circuit
s ''B,&
s ''B,&
53
53
670)[[
56
6'$
,ð&EXV
56
6&/
67$575(3($7('
67$57
67$57
WVX 67$
6'$
WI 6'$
WU 6'$
WK 67$
WVX 6'$
WZ 6&/+
WZ 672 67$
6723
WK 6'$
6&/
WZ 6&//
WU 6&/
WI 6&/
WVX 672
DL F
128/202
DocID027107 Rev 6
STM32F446xC/E
Electrical characteristics
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 63 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 16, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C=30pF
•
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 63. SPI dynamic characteristics(1)
Symbol
fSCK
1/tc(SCK)
Parameter
SPI clock frequency
Conditions
Min
Typ
Master full duplex/receiver mode,
2.7 V≤VDD≤3.6 V
SPI1/4
45
Master transmitter
1.71V @
2OW N
#OL
#OL
#OLI
#OLN
TH3$#,+,?!DD#
TH3$#,+,?3.$%
TD3$#,+,?3.$%
&-#?3$.%;=
TD3$#,+,?.2!3
TH3$#,+,?.2!3
&-#?3$.2!3
TH3$#,+,?.#!3
TD3$#,+,?.#!3
&-#?3$.#!3
&-#?3$.7%
TSU3$#,+(?$ATA
&-#?$;=
TH3$#,+(?$ATA
$ATA
$ATA
$ATAI
$ATAN
-36
DocID027107 Rev 6
169/202
175
Electrical characteristics
STM32F446xC/E
Table 100. SDRAM read timings(1)(2)
Symbol
Parameter
Min
Max
tw(SDCLK)
FMC_SDCLK period
2THCLK-0.5
2THCLK+0.5
tsu(SDCLKH _Data)
Data input setup time
1
-
th(SDCLKH_Data)
Data input hold time
4
-
td(SDCLKL_Add)
Address valid time
-
3
td(SDCLKL_ SDNE)
Chip select valid time
-
1.5
th(SDCLKL_SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS)
SDNRAS valid time
-
1.5
th(SDCLKL_SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
0.5
th(SDCLKL_SDNCAS)
SDNCAS hold time
0
-
Unit
ns
1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK.
2. Guaranteed based on test during characterization.
Table 101. LPSDR SDRAM read timings(1)(2)
Symbol
Parameter
Min
Max
tw(SDCLK)
FMC_SDCLK period
2THCLK - 0.5
2THCLK + 0.5
tsu(SDCLKH _Data)
Data input setup time
1
-
th(SDCLKH_Data)
Data input hold time
5
-
td(SDCLKL_Add)
Address valid time
-
3
td(SDCLKL_ SDNE)
Chip select valid time
-
3
th(SDCLKL_SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS) SDNRAS valid time
-
2
th(SDCLKL_SDNRAS) SDNRAS hold time
0
-
td(SDCLKL_SDNCAS) SDNCAS valid time
-
2
th(SDCLKL_SDNCAS) SDNCAS hold time
0
-
1. CL = 10 pF.
2. Guaranteed based on test during characterization.
170/202
DocID027107 Rev 6
Unit
ns
STM32F446xC/E
Electrical characteristics
Figure 63. SDRAM write access waveforms
&-#?3$#,+
TD3$#,+,?!DD#
TH3$#,+,?!DD2
TD3$#,+,?!DD2
2OW N
&-#?!> @
#OL
#OL
#OLI
#OLN
TH3$#,+,?!DD#
TH3$#,+,?3.$%
TD3$#,+,?3.$%
&-#?3$.%;=
TH3$#,+,?.2!3
TD3$#,+,?.2!3
&-#?3$.2!3
TD3$#,+,?.#!3
TH3$#,+,?.#!3
TD3$#,+,?.7%
TH3$#,+,?.7%
&-#?3$.#!3
&-#?3$.7%
TD3$#,+,?$ATA
$ATA
&-#?$;=
$ATA
$ATAI
$ATAN
TH3$#,+,?$ATA
TD3$#,+,?.",
&-#?.",;=
-36
Table 102. SDRAM write timings(1)(2)
Symbol
Parameter
Min
Max
Unit
MHz
F(SDCLK)
Frequency of operation
-
90
tw(SDCLK)
FMC_SDCLK period
2THCLK - 0.5
2THCLK + 0.5
td(SDCLKL _Data)
Data output valid time
-
2
th(SDCLKL _Data)
Data output hold time
0.5
-
td(SDCLK _Add)
Address valid time
-
3
td(SDCLKL _SDNWE)) SDNWE valid time
-
1.5
th(SDCLKL_SDNWE))
SDNWE hold time
0
-
td(SDCLKL_SDNE))
Chip select valid time
-
1.5
th(SDCLKL_SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS) SDNRAS valie time
-
1
th(SDCLKL_SDNRAS) SDNRAS hold time
0
-
td(SDCLKL_SDNCAS) SDNCAS valid time
-
1
th(SDCLKL_SDNCAS) SDNCAS hold time
0
-
ns
1. CL = 10 pF on data and address line. CL=15 pF on FMC_SDCLK.
2. Guaranteed based on test during characterization.
DocID027107 Rev 6
171/202
175
Electrical characteristics
STM32F446xC/E
Table 103. LPSDR SDRAM write timings(1)(2)
Symbol
Parameter
Min
Max
Unit
MHz
F(SDCLK)
Frequency of operation
-
84
tw(SDCLK)
FMC_SDCLK period
2THCLK - 0.5
2THCLK + 0.5
td(SDCLKL _Data)
Data output valid time
-
5
th(SDCLKL _Data)
Data output hold time
0.5
-
td(SDCLK _Add)
Address valid time
-
3
td(SDCLKL _SDNWE)) SDNWE valid time
-
3
th(SDCLKL_SDNWE))
SDNWE hold time
0
-
td(SDCLKL_SDNE))
Chip select valid time
-
2.5
th(SDCLKL_ SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS) SDNRAS valid time
-
2
th(SDCLKL_SDNRAS) SDNRAS hold time
0
-
td(SDCLKL_SDNCAS) SDNCAS valid time
-
2
td(SDCLKL_SDNCAS) SDNCAS hold time
0
-
ns
1. CL = 10 pF.
2. Guaranteed based on test during characterization.
6.3.27
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 104 for DCMI are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 16, with the following configuration:
•
DCMI_PIXCLK polarity: falling
•
DCMI_VSYNC and DCMI_HSYNC polarity: high
•
Data formats: 14 bits
Table 104. DCMI characteristics
Symbol
-
Parameter
Frequency ratio DCMI_PIXCLK/fHCLK
DCMI_PIXCLK Pixel clock input
DPixel
172/202
Pixel clock input duty cycle
Min
Max
-
0.4
-
-
54
MHz
30
70
%
tsu(DATA)
Data input setup time
1
-
th(DATA)
Data input hold time
3.5
-
tsu(HSYNC)
tsu(VSYNC)
DCMI_HSYNC/DCMI_VSYNC input setup time
2
-
th(HSYNC)
th(VSYNC)
DCMI_HSYNC/DCMI_VSYNC input hold time
0
-
DocID027107 Rev 6
Unit
ns
STM32F446xC/E
Electrical characteristics
Figure 64. DCMI timing diagram
'&0,B3,;&/.
'&0,B3,;&/.
WK +6<1&
WVX +6<1&
'&0,B+6<1&
WK +6<1&
WVX 96<1&
'&0,B96<1&
WVX '$7$
WK '$7$
'$7$> @
069
6.3.28
SD/SDIO MMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Table 105 for the SDIO are derived
from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply
voltage conditions summarized in Table 16, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Figure 65. SDIO high-speed mode
TF
TR
T#
T7#+(
T7#+,
#+
T/6
T/(
$ #-$
OUTPUT
T)35
T)(
$ #-$
INPUT
AI
DocID027107 Rev 6
173/202
175
Electrical characteristics
STM32F446xC/E
Figure 66. SD default mode
#+
T/6$
T/($
$ #-$
OUTPUT
AI
Table 105. Dynamic characteristics: SD / MMC characteristics(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer mode
-
0
-
50
MHz
-
SDIO_CK/fPCLK2 frequency ratio
-
-
-
8/3
-
tW(CKL)
Clock low time
fpp =50MHz
9.5
10.5
-
tW(CKH)
Clock high time
fpp =50MHz
8.5
9.5
-
ns
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU
Input setup time HS
fpp =50MHz
1
-
-
tIH
Input hold time HS
fpp =50MHz
4.5
-
-
ns
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV
Output valid time HS
fpp =50MHz
-
12.5
13
tOH
Output hold time HS
fpp =50MHz
11
-
-
ns
CMD, D inputs (referenced to CK) in SD default mode
tISUD
Input setup time SD
fpp =25MHz
2.5
-
-
tIHD
Input hold time SD
fpp =25MHz
5.5
-
-
ns
CMD, D outputs (referenced to CK) in SD default mode
tOVD
Output valid default time SD
fpp =24MHz
-
3.5
4
tOHD
Output hold default time SD
fpp =24MHz
2
-
-
1. Guaranteed based on test during characterization.
2. VDD = 2.7 to 3.6 V.
174/202
DocID027107 Rev 6
ns
STM32F446xC/E
Electrical characteristics
Table 106. Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer mode
-
0
-
50
MHz
SDIO_CK/fPCLK2 frequency ratio
-
-
-
8/3
-
tW(CKL)
Clock low time
fpp =50MHz
9.5
10.5
-
tW(CKH)
Clock high time
fpp =50MHz
8.5
9.5
-
ns
CMD, D inputs (referenced to CK) in eMMC mode
tISU
Input setup time HS
fpp =50MHz
0.5
-
-
tIH
Input hold time HS
fpp =50MHz
7.5
-
-
ns
CMD, D outputs (referenced to CK) in eMMC mode
tOV
Output valid time HS
fpp =50MHz
-
13.5
14.5
tOH
Output hold time HS
fpp =50MHz
12
-
-
ns
1. Guaranteed based on test during characterization.
2. VDD = 2.7 to 3.6 V.
6.3.29
RTC characteristics
Table 107. RTC characteristics
Symbol
Parameter
-
fPCLK1/RTCCLK frequency ratio
Conditions
Any read/write operation
from/to an RTC register
DocID027107 Rev 6
Min
Max
4
-
175/202
175
Package information
7
STM32F446xC/E
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1
LQFP64 package information
Figure 67. LQFP64-10x10 mm 64 pin low-profile quad flat package outline
PP
*$8*(3/$1(
F
$
$
$
6($7,1*3/$1(
&
$
FFF &
'
'
'
.
/
/
(
(
(
E
3,1
,'(17,),&$7,21
H
:B0(B9
1. Drawing is not to scale
Table 108. LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
176/202
DocID027107 Rev 6
STM32F446xC/E
Package information
Table 108. LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
D
11.800
12.000
12.200
0.4646
0.4724
0.4803
D1
9.800
10.000
10.200
0.3858
0.3937
0.4016
D3
-
7.500
-
-
0.2953
-
E
11.800
12.000
12.200
0.4646
0.4724
0.4803
E1
9.800
10.000
10.200
0.3858
0.3937
0.4016
E3
-
7.500
-
-
0.2953
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
K
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 68. LQFP64 Recommended footprint
AIC
1. Drawing is not to scale.
2. Dimensions are in millimeters.
DocID027107 Rev 6
177/202
199
Package information
STM32F446xC/E
Device marking for LQFP64
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 69. LQFP64 marking example (package top view)
5HYLVLRQFRGH
3URGXFWLGHQWLILFDWLRQ
$
670)
5(7
< ::
3LQLGHQWLILHU
'DWHFRGH
06Y 9
1. Parts marked as “ES”, "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
178/202
DocID027107 Rev 6
STM32F446xC/E
7.2
Package information
LQFP100 package information
Figure 70. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline
MM
C
!
!
!
3%!4).' 0,!.%
#
'!5'% 0,!.%
$
,
$
!
+
CCC #
,
$
0).
)$%.4)&)#!4)/.
%
%
%
B
E
,?-%?6
1. Drawing is not to scale.
Table 109. LQPF100, 14 x 14 mm 100-pin low-profile quad flat
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
-
12.000
-
-
0.4724
-
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
DocID027107 Rev 6
179/202
199
Package information
STM32F446xC/E
Table 109. LQPF100, 14 x 14 mm 100-pin low-profile quad flat
package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
-
12.000
-
-
0.4724
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 71. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint
AIC
1. Dimensions are expressed in millimeters.
180/202
DocID027107 Rev 6
STM32F446xC/E
Package information
Device marking for LQFP100 package
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 72. LQFP100 marking example (package top view)
3URGXFWLGHQWLILFDWLRQ
670)
5HYLVLRQFRGH
9&7
$
'DWHFRGH
< ::
3LQLGHQWLILHU
06Y9
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID027107 Rev 6
181/202
199
Package information
7.3
STM32F446xC/E
LQFP144 package information.
Figure 73. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline
PP
*$8*(3/$1(
C
!
F
$
!
$
!
$
3%!4).'
0,!.%
#
FFF &
MM
CCC #
'
$
'
$
'
$
/
+
,
/
,
.
!
$
'!5'% 0,!.%
(
(
%
(
%
%
E
B
0).
)$%.4)&)#!4)/.
E
3,1
!?-%?6
,'(17,),&$7,21
H
$B0(B9
1. Drawing is not to scale.
182/202
DocID027107 Rev 6
STM32F446xC/E
Package information
Table 110. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
21.800
22.000
22.200
0.8583
0.8661
0.874
D1
19.800
20.000
20.200
0.7795
0.7874
0.7953
D3
-
17.500
-
-
0.689
-
E
21.800
22.000
22.200
0.8583
0.8661
0.8740
E1
19.800
20.000
20.200
0.7795
0.7874
0.7953
E3
-
17.500
-
-
0.6890
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID027107 Rev 6
183/202
199
Package information
STM32F446xC/E
Figure 74. LQFP144 recommended footprint
DL H
1. Dimensions are expressed in millimeters.
184/202
DocID027107 Rev 6
STM32F446xC/E
Package information
Device marking for LQFP144 package
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 75. LQFP144 marking example (package top view)
2SWLRQDOJDWHPDUN
5HYLVLRQFRGH
3URGXFWLGHQWLILFDWLRQ
$
670)=(7
'DWHFRGH
< ::
3LQLGHQWLILHU
06Y9
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID027107 Rev 6
185/202
199
Package information
7.4
STM32F446xC/E
UFBGA144 7 x 7 mm package information
Figure 76. UFBGA144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline
= 6HDWLQJSODQH
GGG =
$ $ $
$ $
(
H
$EDOO
$EDOO
LGHQWLILHU LQGH[DUHD
)
;
(
$
)
'
'
H
<
0
%277209,(:
E EDOOV
HHH 0 = < ;
III 0 =
7239,(:
$$6B0(B9
1. Drawing is not in scale.
Table 111. UFBGA144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data
inches(1)
millimeters
Symbol
186/202
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.460
0.530
0.600
0.0181
0.0209
0.0236
A1
0.050
0.080
0.110
0.0020
0.0031
0.0043
A2
0.400
0.450
0.500
0.0157
0.0177
0.0197
A3
-
0.130
-
-
0.0051
-
A4
0.270
0.320
0.370
0.0106
0.0126
0.0146
b
0.230
0.280
0.320
0.0091
0.0110
0.0126
D
6.950
7.000
7.050
0.2736
0.2756
0.2776
D1
5.450
5.500
5.550
0.2146
0.2165
0.2185
E
6.950
7.000
7.050
0.2736
0.2756
0.2776
E1
5.450
5.500
5.550
0.2146
0.2165
0.2185
e
-
0.500
-
-
0.0197
-
F
0.700
0.750
0.800
0.0276
0.0295
0.0315
DocID027107 Rev 6
STM32F446xC/E
Package information
Table 111. UFBGA144 - 144-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data (continued)
inches(1)
millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
ddd
-
-
0.100
-
-
0.0039
eee
-
-
0.150
-
-
0.0059
fff
-
-
0.050
-
-
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 77. UFBGA144 - 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package recommended footprint
'SDG
'VP
Ϭ^ͺ&Wͺsϭ
Table 112. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA)
Dimension
Recommended values
Pitch
0.50 mm
Dpad
0.280 mm
Dsm
0.370 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening
0.280 mm
Stencil thickness
Between 0.100 mm and 0.125 mm
Pad trace width
0.120 mm
DocID027107 Rev 6
187/202
199
Package information
STM32F446xC/E
Device marking for UFBGA144 7 x 7 mm package
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 78. UQFP144 7 x 7 mm marking example (package top view)
3URGXFW
LGHQWLILFDWLRQ
670)
=(+
'DWHFRGH
< ::
%DOO$
LQGHQWLILHU
$
$GGLWLRQDO
LQIRUPDWLRQ
06Y 9
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
188/202
DocID027107 Rev 6
STM32F446xC/E
7.5
Package information
UFBGA144 10 x 10 mm package information
Figure 79. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package outline
& 6HDWLQJSODQH
GGG =
$ $ $
$ $
(
H
$EDOO
$EDOO
LGHQWLILHU LQGH[DUHD
)
$
(
$
)
'
'
H
%
0
%277209,(:
E EDOOV
HHH 0 & $ %
III 0 &
7239,(:
$
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
Tagged PDF : Yes
Language : en
Page Layout : SinglePage
Page Mode : UseNone
Page Count : 202
Creator : C2 v2.1.0.1 build 007 - c2_rendition_config : Techlit_Active
Producer : Acrobat Distiller 9.0.0 (Windows)
Title : ARM® Cortex®-M4 32b MCU+FPU, 225DMIPS, up to 512kB Flash/128+4KB RAM, USB OTG HS/FS, 17 TIMs, 3 ADCs, 20 comm. interfaces
Keywords : Technical Literature, 027107, Product Development, Specification, Datasheet, STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, STM32F446ZE
Modify Date : 2016:09:02 13:29:21+02:00
Subject : -
Author : STMICROELECTRONICS
Create Date : 2016:09:02 13:23:22Z
EXIF Metadata provided by EXIF.tools