Efr32xg13 Reference Manual
User Manual:
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- Table of Contents
- 1. About This Document
- 2. System Overview
- 2.1 Introduction
- 2.2 Block Diagrams
- 2.3 MCU Features overview
- 2.4 Oscillators and Clocks
- 2.5 RF Frequency Synthesizer
- 2.6 Modulation Modes
- 2.7 Transmit Mode
- 2.8 Receive Mode
- 2.9 Data Buffering
- 2.10 Unbuffered Data Transfer
- 2.11 Frame Format Support
- 2.12 Hardware CRC Support
- 2.13 Convolutional Encoding / Decoding
- 2.14 Binary Block Encoding / Decoding
- 2.15 Data Encryption and Authentication
- 2.16 Timers
- 2.17 RF Test Modes
- 3. System Processor
- 4. Memory and Bus System
- 4.1 Introduction
- 4.2 Functional Description
- 4.3 Access to Low Energy Peripherals (Asynchronous Registers)
- 4.4 Flash
- 4.5 SRAM
- 4.6 DI Page Entry Map
- 4.7 DI Page Entry Description
- 4.7.1 CAL - CRC of DI-page and calibration temperature
- 4.7.2 EXTINFO - External Component description
- 4.7.3 EUI48L - EUI48 OUI and Unique identifier
- 4.7.4 EUI48H - OUI
- 4.7.5 CUSTOMINFO - Custom information
- 4.7.6 MEMINFO - Flash page size and misc. chip information
- 4.7.7 UNIQUEL - Low 32 bits of device unique number
- 4.7.8 UNIQUEH - High 32 bits of device unique number
- 4.7.9 MSIZE - Flash and SRAM Memory size in kB
- 4.7.10 PART - Part description
- 4.7.11 DEVINFOREV - Device information page revision
- 4.7.12 EMUTEMP - EMU Temperature Calibration Information
- 4.7.13 ADC0CAL0 - ADC0 calibration register 0
- 4.7.14 ADC0CAL1 - ADC0 calibration register 1
- 4.7.15 ADC0CAL2 - ADC0 calibration register 2
- 4.7.16 ADC0CAL3 - ADC0 calibration register 3
- 4.7.17 HFRCOCAL0 - HFRCO Calibration Register (4 MHz)
- 4.7.18 HFRCOCAL3 - HFRCO Calibration Register (7 MHz)
- 4.7.19 HFRCOCAL6 - HFRCO Calibration Register (13 MHz)
- 4.7.20 HFRCOCAL7 - HFRCO Calibration Register (16 MHz)
- 4.7.21 HFRCOCAL8 - HFRCO Calibration Register (19 MHz)
- 4.7.22 HFRCOCAL10 - HFRCO Calibration Register (26 MHz)
- 4.7.23 HFRCOCAL11 - HFRCO Calibration Register (32 MHz)
- 4.7.24 HFRCOCAL12 - HFRCO Calibration Register (38 MHz)
- 4.7.25 AUXHFRCOCAL0 - AUXHFRCO Calibration Register (4 MHz)
- 4.7.26 AUXHFRCOCAL3 - AUXHFRCO Calibration Register (7 MHz)
- 4.7.27 AUXHFRCOCAL6 - AUXHFRCO Calibration Register (13 MHz)
- 4.7.28 AUXHFRCOCAL7 - AUXHFRCO Calibration Register (16 MHz)
- 4.7.29 AUXHFRCOCAL8 - AUXHFRCO Calibration Register (19 MHz)
- 4.7.30 AUXHFRCOCAL10 - AUXHFRCO Calibration Register (26 MHz)
- 4.7.31 AUXHFRCOCAL11 - AUXHFRCO Calibration Register (32 MHz)
- 4.7.32 AUXHFRCOCAL12 - AUXHFRCO Calibration Register (38 MHz)
- 4.7.33 VMONCAL0 - VMON Calibration Register 0
- 4.7.34 VMONCAL1 - VMON Calibration Register 1
- 4.7.35 VMONCAL2 - VMON Calibration Register 2
- 4.7.36 IDAC0CAL0 - IDAC0 Calibration Register 0
- 4.7.37 IDAC0CAL1 - IDAC0 Calibration Register 1
- 4.7.38 DCDCLNVCTRL0 - DCDC Low-noise VREF Trim Register 0
- 4.7.39 DCDCLPVCTRL0 - DCDC Low-power VREF Trim Register 0
- 4.7.40 DCDCLPVCTRL1 - DCDC Low-power VREF Trim Register 1
- 4.7.41 DCDCLPVCTRL2 - DCDC Low-power VREF Trim Register 2
- 4.7.42 DCDCLPVCTRL3 - DCDC Low-power VREF Trim Register 3
- 4.7.43 DCDCLPCMPHYSSEL0 - DCDC LPCMPHYSSEL Trim Register 0
- 4.7.44 DCDCLPCMPHYSSEL1 - DCDC LPCMPHYSSEL Trim Register 1
- 4.7.45 VDAC0MAINCAL - VDAC0 Cals for Main Path
- 4.7.46 VDAC0ALTCAL - VDAC0 Cals for Alternate Path
- 4.7.47 VDAC0CH1CAL - VDAC0 CH1 Error Cal
- 4.7.48 OPA0CAL0 - OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1
- 4.7.49 OPA0CAL1 - OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1
- 4.7.50 OPA0CAL2 - OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1
- 4.7.51 OPA0CAL3 - OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1
- 4.7.52 OPA1CAL0 - OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1
- 4.7.53 OPA1CAL1 - OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1
- 4.7.54 OPA1CAL2 - OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1
- 4.7.55 OPA1CAL3 - OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1
- 4.7.56 OPA2CAL0 - OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=1
- 4.7.57 OPA2CAL1 - OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=1
- 4.7.58 OPA2CAL2 - OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=1
- 4.7.59 OPA2CAL3 - OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=1
- 4.7.60 CSENGAINCAL - Cap Sense Gain Adjustment
- 4.7.61 OPA0CAL4 - OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0
- 4.7.62 OPA0CAL5 - OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0
- 4.7.63 OPA0CAL6 - OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0
- 4.7.64 OPA0CAL7 - OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0
- 4.7.65 OPA1CAL4 - OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0
- 4.7.66 OPA1CAL5 - OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0
- 4.7.67 OPA1CAL6 - OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0
- 4.7.68 OPA1CAL7 - OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0
- 4.7.69 OPA2CAL4 - OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=0
- 4.7.70 OPA2CAL5 - OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=0
- 4.7.71 OPA2CAL6 - OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=0
- 4.7.72 OPA2CAL7 - OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0
- 5. Serial Flash
- 5.1 Introduction
- 5.2 Features
- 5.3 Functional Description
- 5.3.1 Memory Organization
- 5.3.2 Serial Interface
- 5.3.3 Instruction Set
- 5.3.4 Registers
- 5.3.5 Reading Memory
- 5.3.6 Programming and Erasing Memory
- 5.3.6.1 Program/Erase Suspend and Resume
- 5.3.6.2 Write Enable (WREN, 0x06)
- 5.3.6.3 Write Disable (WRDI, 0x04)
- 5.3.6.4 Page Program (PP, 0x02)
- 5.3.6.5 Sector Erase (SER, 0xD7 / 0x20)
- 5.3.6.6 Block Erase 32k (BER32, 0x52)
- 5.3.6.7 Block Erase 64k (BER64, 0xD8)
- 5.3.6.8 Chip Erase (CER, 0xC7 / 0x60)
- 5.3.6.9 Program/Erase Suspend (PERSUS, 0x75 / 0xB0)
- 5.3.6.10 Program/Erase Resume (PERRSM, 0x7A / 0x30)
- 5.3.7 Write Protection
- 5.3.8 Security Information Row and Unique ID
- 5.3.9 Power Down
- 5.3.10 Software Reset
- 6. Radio Transceiver
- 7. DBG - Debug Interface
- 7.1 Introduction
- 7.2 Features
- 7.3 Functional Description
- 7.4 Register Map
- 7.5 Register Description
- 7.5.1 AAP_CMD - Command Register
- 7.5.2 AAP_CMDKEY - Command Key Register
- 7.5.3 AAP_STATUS - Status Register
- 7.5.4 AAP_CTRL - Control Register
- 7.5.5 AAP_CRCCMD - CRC Command Register
- 7.5.6 AAP_CRCSTATUS - CRC Status Register
- 7.5.7 AAP_CRCADDR - CRC Address Register
- 7.5.8 AAP_CRCRESULT - CRC Result Register
- 7.5.9 AAP_IDR - AAP Identification Register
- 8. MSC - Memory System Controller
- 8.1 Introduction
- 8.2 Features
- 8.3 Functional Description
- 8.3.1 User Data (UD) Page Description
- 8.3.2 Lock Bits (LB) Page Description
- 8.3.3 Device Information (DI) Page
- 8.3.4 Bootloader
- 8.3.5 Device Revision
- 8.3.6 Post-reset Behavior
- 8.3.7 Flash Startup
- 8.3.8 Wait-states
- 8.3.9 Suppressed Conditional Branch Target Prefetch (SCBTP)
- 8.3.10 Cortex-M4 If-Then Block Folding
- 8.3.11 Instruction Cache
- 8.3.12 Low Voltage Flash Read
- 8.3.13 Erase and Write Operations
- 8.4 Register Map
- 8.5 Register Description
- 8.5.1 MSC_CTRL - Memory System Control Register
- 8.5.2 MSC_READCTRL - Read Control Register
- 8.5.3 MSC_WRITECTRL - Write Control Register
- 8.5.4 MSC_WRITECMD - Write Command Register
- 8.5.5 MSC_ADDRB - Page Erase/Write Address Buffer
- 8.5.6 MSC_WDATA - Write Data Register
- 8.5.7 MSC_STATUS - Status Register
- 8.5.8 MSC_IF - Interrupt Flag Register
- 8.5.9 MSC_IFS - Interrupt Flag Set Register
- 8.5.10 MSC_IFC - Interrupt Flag Clear Register
- 8.5.11 MSC_IEN - Interrupt Enable Register
- 8.5.12 MSC_LOCK - Configuration Lock Register
- 8.5.13 MSC_CACHECMD - Flash Cache Command Register
- 8.5.14 MSC_CACHEHITS - Cache Hits Performance Counter
- 8.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter
- 8.5.16 MSC_MASSLOCK - Mass Erase Lock Register
- 8.5.17 MSC_STARTUP - Startup Control
- 8.5.18 MSC_CMD - Command Register
- 8.5.19 MSC_BOOTLOADERCTRL - Bootloader read and write enable, write once register
- 8.5.20 MSC_AAPUNLOCKCMD - Software Unlock AAP Command Register
- 8.5.21 MSC_CACHECONFIG0 - Cache Configuration Register 0
- 9. LDMA - Linked DMA Controller
- 9.1 Introduction
- 9.2 Block Diagram
- 9.3 Functional Description
- 9.4 Examples
- 9.5 Register Map
- 9.6 Register Description
- 9.6.1 LDMA_CTRL - DMA Control Register
- 9.6.2 LDMA_STATUS - DMA Status Register
- 9.6.3 LDMA_SYNC - DMA Synchronization Trigger Register (Single-Cycle RMW)
- 9.6.4 LDMA_CHEN - DMA Channel Enable Register (Single-Cycle RMW)
- 9.6.5 LDMA_CHBUSY - DMA Channel Busy Register
- 9.6.6 LDMA_CHDONE - DMA Channel Linking Done Register (Single-Cycle RMW)
- 9.6.7 LDMA_DBGHALT - DMA Channel Debug Halt Register
- 9.6.8 LDMA_SWREQ - DMA Channel Software Transfer Request Register
- 9.6.9 LDMA_REQDIS - DMA Channel Request Disable Register
- 9.6.10 LDMA_REQPEND - DMA Channel Requests Pending Register
- 9.6.11 LDMA_LINKLOAD - DMA Channel Link Load Register
- 9.6.12 LDMA_REQCLEAR - DMA Channel Request Clear Register
- 9.6.13 LDMA_IF - Interrupt Flag Register
- 9.6.14 LDMA_IFS - Interrupt Flag Set Register
- 9.6.15 LDMA_IFC - Interrupt Flag Clear Register
- 9.6.16 LDMA_IEN - Interrupt Enable register
- 9.6.17 LDMA_CHx_REQSEL - Channel Peripheral Request Select Register
- 9.6.18 LDMA_CHx_CFG - Channel Configuration Register
- 9.6.19 LDMA_CHx_LOOP - Channel Loop Counter Register
- 9.6.20 LDMA_CHx_CTRL - Channel Descriptor Control Word Register
- 9.6.21 LDMA_CHx_SRC - Channel Descriptor Source Data Address Register
- 9.6.22 LDMA_CHx_DST - Channel Descriptor Destination Data Address Register
- 9.6.23 LDMA_CHx_LINK - Channel Descriptor Link Structure Address Register
- 10. RMU - Reset Management Unit
- 11. EMU - Energy Management Unit
- 11.1 Introduction
- 11.2 Features
- 11.3 Functional Description
- 11.3.1 Energy Modes
- 11.3.2 Entering Low Energy Modes
- 11.3.3 Exiting a Low Energy Mode
- 11.3.4 Power Configurations
- 11.3.5 DC-to-DC Interface
- 11.3.6 Analog Peripheral Power Selection
- 11.3.7 Digital LDO Power Selection
- 11.3.8 IOVDD Connection
- 11.3.9 Voltage Scaling
- 11.3.10 EM23 Peripheral Retention Disable
- 11.3.11 Brown Out Detector (BOD)
- 11.3.12 Voltage Monitor (VMON)
- 11.3.13 Powering off SRAM blocks
- 11.3.14 Temperature Sensor
- 11.3.15 Registers latched in EM4
- 11.3.16 Register Resets
- 11.4 Register Map
- 11.5 Register Description
- 11.5.1 EMU_CTRL - Control Register
- 11.5.2 EMU_STATUS - Status Register
- 11.5.3 EMU_LOCK - Configuration Lock Register
- 11.5.4 EMU_RAM0CTRL - Memory Control Register
- 11.5.5 EMU_CMD - Command Register
- 11.5.6 EMU_EM4CTRL - EM4 Control Register
- 11.5.7 EMU_TEMPLIMITS - Temperature limits for interrupt generation
- 11.5.8 EMU_TEMP - Value of last temperature measurement
- 11.5.9 EMU_IF - Interrupt Flag Register
- 11.5.10 EMU_IFS - Interrupt Flag Set Register
- 11.5.11 EMU_IFC - Interrupt Flag Clear Register
- 11.5.12 EMU_IEN - Interrupt Enable Register
- 11.5.13 EMU_PWRLOCK - Regulator and Supply Lock Register
- 11.5.14 EMU_PWRCTRL - Power Control Register.
- 11.5.15 EMU_DCDCCTRL - DCDC Control
- 11.5.16 EMU_DCDCMISCCTRL - DCDC Miscellaneous Control Register
- 11.5.17 EMU_DCDCZDETCTRL - DCDC Power Train NFET Zero Current Detector Control Register
- 11.5.18 EMU_DCDCCLIMCTRL - DCDC Power Train PFET Current Limiter Control Register
- 11.5.19 EMU_DCDCLNCOMPCTRL - DCDC Low Noise Compensator Control Register
- 11.5.20 EMU_DCDCLNVCTRL - DCDC Low Noise Voltage Register
- 11.5.21 EMU_DCDCLPVCTRL - DCDC Low Power Voltage Register
- 11.5.22 EMU_DCDCLPCTRL - DCDC Low Power Control Register
- 11.5.23 EMU_DCDCLNFREQCTRL - DCDC Low Noise Controller Frequency Control
- 11.5.24 EMU_DCDCSYNC - DCDC Read Status Register
- 11.5.25 EMU_VMONAVDDCTRL - VMON AVDD Channel Control
- 11.5.26 EMU_VMONALTAVDDCTRL - Alternate VMON AVDD Channel Control
- 11.5.27 EMU_VMONDVDDCTRL - VMON DVDD Channel Control
- 11.5.28 EMU_VMONIO0CTRL - VMON IOVDD0 Channel Control
- 11.5.29 EMU_RAM1CTRL - Memory Control Register
- 11.5.30 EMU_RAM2CTRL - Memory Control Register
- 11.5.31 EMU_DCDCLPEM01CFG - Configuration bits for low power mode to be applied during EM01, this field is only relevant if LP mode is used in EM01.
- 11.5.32 EMU_EM23PERNORETAINCMD - Clears corresponding bits in EM23PERNORETAINSTATUS unlocking access to peripheral
- 11.5.33 EMU_EM23PERNORETAINSTATUS - Status indicating if peripherals were powered down in EM23, subsequently locking access to it.
- 11.5.34 EMU_EM23PERNORETAINCTRL - When set corresponding peripherals may get powered down in EM23
- 12. CMU - Clock Management Unit
- 12.1 Introduction
- 12.2 Features
- 12.3 Functional Description
- 12.3.1 System Clocks
- 12.3.1.1 HFCLK - High Frequency Clock
- 12.3.1.2 HFCORECLK - High Frequency Core Clock
- 12.3.1.3 HFBUSCLK - High Frequency Bus Clock
- 12.3.1.4 HFPERCLK - High Frequency Peripheral Clock
- 12.3.1.5 HFRADIOCLK - High Frequency Radio Clock
- 12.3.1.6 ADCnCLK - ADC Core Clock
- 12.3.1.7 LFACLK - Low Frequency A Clock
- 12.3.1.8 LFBCLK - Low Frequency B Clock
- 12.3.1.9 LFECLK - Low Frequency E Clock
- 12.3.1.10 PCNTnCLK - Pulse Counter n Clock
- 12.3.1.11 WDOGnCLK - Watchdog Timer Clock
- 12.3.1.12 CRYOCLK - Cryotimer Clock
- 12.3.1.13 RFSENSECLK - RFSENSE Clock
- 12.3.1.14 AUXCLK - Auxiliary Clock
- 12.3.1.15 Debug Trace Clock
- 12.3.2 Oscillators
- 12.3.3 Configuration For Operating Frequencies
- 12.3.4 Energy Modes
- 12.3.5 Clock Output on a Pin
- 12.3.6 Clock Input from a Pin
- 12.3.7 Clock Output on PRS
- 12.3.8 Error Handling
- 12.3.9 Interrupts
- 12.3.10 Wake-up
- 12.3.11 Protection
- 12.3.12 Digital Phase-Locked Loop
- 12.3.13 Precision Low Frequency Oscillator
- 12.3.1 System Clocks
- 12.4 Register Map
- 12.5 Register Description
- 12.5.1 CMU_CTRL - CMU Control Register
- 12.5.2 CMU_HFRCOCTRL - HFRCO Control Register
- 12.5.3 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register
- 12.5.4 CMU_LFRCOCTRL - LFRCO Control Register
- 12.5.5 CMU_HFXOCTRL - HFXO Control Register
- 12.5.6 CMU_HFXOSTARTUPCTRL - HFXO Startup Control
- 12.5.7 CMU_HFXOSTEADYSTATECTRL - HFXO Steady State control
- 12.5.8 CMU_HFXOTIMEOUTCTRL - HFXO Timeout Control
- 12.5.9 CMU_LFXOCTRL - LFXO Control Register
- 12.5.10 CMU_DPLLCTRL - DPLL Control Register
- 12.5.11 CMU_DPLLCTRL1 - DPLL Control Register
- 12.5.12 CMU_CALCTRL - Calibration Control Register
- 12.5.13 CMU_CALCNT - Calibration Counter Register
- 12.5.14 CMU_OSCENCMD - Oscillator Enable/Disable Command Register
- 12.5.15 CMU_CMD - Command Register
- 12.5.16 CMU_DBGCLKSEL - Debug Trace Clock Select
- 12.5.17 CMU_HFCLKSEL - High Frequency Clock Select Command Register
- 12.5.18 CMU_LFACLKSEL - Low Frequency A Clock Select Register
- 12.5.19 CMU_LFBCLKSEL - Low Frequency B Clock Select Register
- 12.5.20 CMU_LFECLKSEL - Low Frequency E Clock Select Register
- 12.5.21 CMU_STATUS - Status Register
- 12.5.22 CMU_HFCLKSTATUS - HFCLK Status Register
- 12.5.23 CMU_HFXOTRIMSTATUS - HFXO Trim Status
- 12.5.24 CMU_IF - Interrupt Flag Register
- 12.5.25 CMU_IFS - Interrupt Flag Set Register
- 12.5.26 CMU_IFC - Interrupt Flag Clear Register
- 12.5.27 CMU_IEN - Interrupt Enable Register
- 12.5.28 CMU_HFBUSCLKEN0 - High Frequency Bus Clock Enable Register 0
- 12.5.29 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0
- 12.5.30 CMU_HFRADIOALTCLKEN0 - High Frequency Alternate Radio Peripheral Clock Enable Register 0
- 12.5.31 CMU_LFACLKEN0 - Low Frequency A Clock Enable Register 0 (Async Reg)
- 12.5.32 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg)
- 12.5.33 CMU_LFECLKEN0 - Low Frequency E Clock Enable Register 0 (Async Reg)
- 12.5.34 CMU_HFPRESC - High Frequency Clock Prescaler Register
- 12.5.35 CMU_HFCOREPRESC - High Frequency Core Clock Prescaler Register
- 12.5.36 CMU_HFPERPRESC - High Frequency Peripheral Clock Prescaler Register
- 12.5.37 CMU_HFRADIOPRESC - High Frequency Radio Peripheral Clock Prescaler Register
- 12.5.38 CMU_HFEXPPRESC - High Frequency Export Clock Prescaler Register
- 12.5.39 CMU_LFAPRESC0 - Low Frequency A Prescaler Register 0 (Async Reg)
- 12.5.40 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg)
- 12.5.41 CMU_LFEPRESC0 - Low Frequency E Prescaler Register 0 (Async Reg). When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect
- 12.5.42 CMU_HFRADIOALTPRESC - High Frequency Alternate Radio Peripheral Clock Prescaler Register
- 12.5.43 CMU_SYNCBUSY - Synchronization Busy Register
- 12.5.44 CMU_FREEZE - Freeze Register
- 12.5.45 CMU_PCNTCTRL - PCNT Control Register
- 12.5.46 CMU_ADCCTRL - ADC Control Register
- 12.5.47 CMU_ROUTEPEN - I/O Routing Pin Enable Register
- 12.5.48 CMU_ROUTELOC0 - I/O Routing Location Register
- 12.5.49 CMU_ROUTELOC1 - I/O Routing Location Register
- 12.5.50 CMU_LOCK - Configuration Lock Register
- 12.5.51 CMU_HFRCOSS - HFRCO Spread Spectrum Register
- 13. SMU - Security Management Unit
- 13.1 Introduction
- 13.2 Features
- 13.3 Functional Description
- 13.4 Register Map
- 13.5 Register Description
- 13.5.1 SMU_IF - Interrupt Flag Register
- 13.5.2 SMU_IFS - Interrupt Flag Set Register
- 13.5.3 SMU_IFC - Interrupt Flag Clear Register
- 13.5.4 SMU_IEN - Interrupt Enable Register
- 13.5.5 SMU_PPUCTRL - PPU Control Register
- 13.5.6 SMU_PPUPATD0 - PPU Privilege Access Type Descriptor 0
- 13.5.7 SMU_PPUPATD1 - PPU Privilege Access Type Descriptor 1
- 13.5.8 SMU_PPUFS - PPU Fault Status
- 14. RTCC - Real Time Counter and Calendar
- 14.1 Introduction
- 14.2 Features
- 14.3 Functional Description
- 14.4 Register Map
- 14.5 Register Description
- 14.5.1 RTCC_CTRL - Control Register (Async Reg)
- 14.5.2 RTCC_PRECNT - Pre-Counter Value Register (Async Reg)
- 14.5.3 RTCC_CNT - Counter Value Register (Async Reg)
- 14.5.4 RTCC_COMBCNT - Combined Pre-Counter and Counter Value Register
- 14.5.5 RTCC_TIME - Time of day register (Async Reg)
- 14.5.6 RTCC_DATE - Date register (Async Reg)
- 14.5.7 RTCC_IF - RTCC Interrupt Flags
- 14.5.8 RTCC_IFS - Interrupt Flag Set Register
- 14.5.9 RTCC_IFC - Interrupt Flag Clear Register
- 14.5.10 RTCC_IEN - Interrupt Enable Register
- 14.5.11 RTCC_STATUS - Status register
- 14.5.12 RTCC_CMD - Command Register
- 14.5.13 RTCC_SYNCBUSY - Synchronization Busy Register
- 14.5.14 RTCC_POWERDOWN - Retention RAM power-down register (Async Reg)
- 14.5.15 RTCC_LOCK - Configuration Lock Register (Async Reg)
- 14.5.16 RTCC_EM4WUEN - Wake Up Enable
- 14.5.17 RTCC_CCx_CTRL - CC Channel Control Register (Async Reg)
- 14.5.18 RTCC_CCx_CCV - Capture/Compare Value Register (Async Reg)
- 14.5.19 RTCC_CCx_TIME - Capture/Compare Time Register (Async Reg)
- 14.5.20 RTCC_CCx_DATE - Capture/Compare Date Register (Async Reg)
- 14.5.21 RTCC_RETx_REG - Retention register
- 15. WDOG - Watchdog Timer
- 15.1 Introduction
- 15.2 Features
- 15.3 Functional Description
- 15.4 Register Map
- 15.5 Register Description
- 15.5.1 WDOG_CTRL - Control Register (Async Reg)
- 15.5.2 WDOG_CMD - Command Register (Async Reg)
- 15.5.3 WDOG_SYNCBUSY - Synchronization Busy Register
- 15.5.4 WDOGn_PCHx_PRSCTRL - PRS Control Register (Async Reg)
- 15.5.5 WDOG_IF - Watchdog Interrupt Flags
- 15.5.6 WDOG_IFS - Interrupt Flag Set Register
- 15.5.7 WDOG_IFC - Interrupt Flag Clear Register
- 15.5.8 WDOG_IEN - Interrupt Enable Register
- 16. PRS - Peripheral Reflex System
- 16.1 Introduction
- 16.2 Features
- 16.3 Functional Description
- 16.4 Register Map
- 16.5 Register Description
- 16.5.1 PRS_SWPULSE - Software Pulse Register
- 16.5.2 PRS_SWLEVEL - Software Level Register
- 16.5.3 PRS_ROUTEPEN - I/O Routing Pin Enable Register
- 16.5.4 PRS_ROUTELOC0 - I/O Routing Location Register
- 16.5.5 PRS_ROUTELOC1 - I/O Routing Location Register
- 16.5.6 PRS_ROUTELOC2 - I/O Routing Location Register
- 16.5.7 PRS_CTRL - Control Register
- 16.5.8 PRS_DMAREQ0 - DMA Request 0 Register
- 16.5.9 PRS_DMAREQ1 - DMA Request 1 Register
- 16.5.10 PRS_PEEK - PRS Channel Values
- 16.5.11 PRS_CHx_CTRL - Channel Control Register
- 17. PCNT - Pulse Counter
- 17.1 Introduction
- 17.2 Features
- 17.3 Functional Description
- 17.4 Register Map
- 17.5 Register Description
- 17.5.1 PCNTn_CTRL - Control Register (Async Reg)
- 17.5.2 PCNTn_CMD - Command Register (Async Reg)
- 17.5.3 PCNTn_STATUS - Status Register
- 17.5.4 PCNTn_CNT - Counter Value Register
- 17.5.5 PCNTn_TOP - Top Value Register
- 17.5.6 PCNTn_TOPB - Top Value Buffer Register (Async Reg)
- 17.5.7 PCNTn_IF - Interrupt Flag Register
- 17.5.8 PCNTn_IFS - Interrupt Flag Set Register
- 17.5.9 PCNTn_IFC - Interrupt Flag Clear Register
- 17.5.10 PCNTn_IEN - Interrupt Enable Register
- 17.5.11 PCNTn_ROUTELOC0 - I/O Routing Location Register
- 17.5.12 PCNTn_FREEZE - Freeze Register
- 17.5.13 PCNTn_SYNCBUSY - Synchronization Busy Register
- 17.5.14 PCNTn_AUXCNT - Auxiliary Counter Value Register
- 17.5.15 PCNTn_INPUT - PCNT Input Register
- 17.5.16 PCNTn_OVSCFG - Oversampling Config Register (Async Reg)
- 18. I2C - Inter-Integrated Circuit Interface
- 18.1 Introduction
- 18.2 Features
- 18.3 Functional Description
- 18.3.1 I2C-Bus Overview
- 18.3.2 Enable and Reset
- 18.3.3 Safely Disabling and Changing Slave Configuration
- 18.3.4 Clock Generation
- 18.3.5 Arbitration
- 18.3.6 Buffers
- 18.3.7 Master Operation
- 18.3.8 Bus States
- 18.3.9 Slave Operation
- 18.3.10 Transfer Automation
- 18.3.11 Using 10-bit Addresses
- 18.3.12 Error Handling
- 18.3.13 DMA Support
- 18.3.14 Interrupts
- 18.3.15 Wake-up
- 18.4 Register Map
- 18.5 Register Description
- 18.5.1 I2Cn_CTRL - Control Register
- 18.5.2 I2Cn_CMD - Command Register
- 18.5.3 I2Cn_STATE - State Register
- 18.5.4 I2Cn_STATUS - Status Register
- 18.5.5 I2Cn_CLKDIV - Clock Division Register
- 18.5.6 I2Cn_SADDR - Slave Address Register
- 18.5.7 I2Cn_SADDRMASK - Slave Address Mask Register
- 18.5.8 I2Cn_RXDATA - Receive Buffer Data Register (Actionable Reads)
- 18.5.9 I2Cn_RXDOUBLE - Receive Buffer Double Data Register (Actionable Reads)
- 18.5.10 I2Cn_RXDATAP - Receive Buffer Data Peek Register
- 18.5.11 I2Cn_RXDOUBLEP - Receive Buffer Double Data Peek Register
- 18.5.12 I2Cn_TXDATA - Transmit Buffer Data Register
- 18.5.13 I2Cn_TXDOUBLE - Transmit Buffer Double Data Register
- 18.5.14 I2Cn_IF - Interrupt Flag Register
- 18.5.15 I2Cn_IFS - Interrupt Flag Set Register
- 18.5.16 I2Cn_IFC - Interrupt Flag Clear Register
- 18.5.17 I2Cn_IEN - Interrupt Enable Register
- 18.5.18 I2Cn_ROUTEPEN - I/O Routing Pin Enable Register
- 18.5.19 I2Cn_ROUTELOC0 - I/O Routing Location Register
- 19. USART - Universal Synchronous Asynchronous Receiver/Transmitter
- 19.1 Introduction
- 19.2 Features
- 19.3 Functional Description
- 19.3.1 Modes of Operation
- 19.3.2 Asynchronous Operation
- 19.3.2.1 Frame Format
- 19.3.2.2 Parity bit Calculation and Handling
- 19.3.2.3 Clock Generation
- 19.3.2.4 Auto Baud Detection
- 19.3.2.5 Data Transmission
- 19.3.2.6 Transmit Buffer Operation
- 19.3.2.7 Frame Transmission Control
- 19.3.2.8 Data Reception
- 19.3.2.9 Receive Buffer Operation
- 19.3.2.10 Blocking Incoming Data
- 19.3.2.11 Clock Recovery and Filtering
- 19.3.2.12 Parity Error
- 19.3.2.13 Framing Error and Break Detection
- 19.3.2.14 Local Loopback
- 19.3.2.15 Asynchronous Half Duplex Communication
- 19.3.2.16 Single Data-link
- 19.3.2.17 Single Data-link with External Driver
- 19.3.2.18 Two Data-links
- 19.3.2.19 Large Frames
- 19.3.2.20 Multi-Processor Mode
- 19.3.2.21 Collision Detection
- 19.3.2.22 SmartCard Mode
- 19.3.3 Synchronous Operation
- 19.3.4 Hardware Flow Control
- 19.3.5 Debug Halt
- 19.3.6 PRS-triggered Transmissions
- 19.3.7 PRS RX Input
- 19.3.8 PRS CLK Input
- 19.3.9 DMA Support
- 19.3.10 Timer
- 19.3.11 Interrupts
- 19.3.12 IrDA Modulator/ Demodulator
- 19.4 Register Map
- 19.5 Register Description
- 19.5.1 USARTn_CTRL - Control Register
- 19.5.2 USARTn_FRAME - USART Frame Format Register
- 19.5.3 USARTn_TRIGCTRL - USART Trigger Control register
- 19.5.4 USARTn_CMD - Command Register
- 19.5.5 USARTn_STATUS - USART Status Register
- 19.5.6 USARTn_CLKDIV - Clock Control Register
- 19.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register (Actionable Reads)
- 19.5.8 USARTn_RXDATA - RX Buffer Data Register (Actionable Reads)
- 19.5.9 USARTn_RXDOUBLEX - RX Buffer Double Data Extended Register (Actionable Reads)
- 19.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register (Actionable Reads)
- 19.5.11 USARTn_RXDATAXP - RX Buffer Data Extended Peek Register
- 19.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register
- 19.5.13 USARTn_TXDATAX - TX Buffer Data Extended Register
- 19.5.14 USARTn_TXDATA - TX Buffer Data Register
- 19.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register
- 19.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register
- 19.5.17 USARTn_IF - Interrupt Flag Register
- 19.5.18 USARTn_IFS - Interrupt Flag Set Register
- 19.5.19 USARTn_IFC - Interrupt Flag Clear Register
- 19.5.20 USARTn_IEN - Interrupt Enable Register
- 19.5.21 USARTn_IRCTRL - IrDA Control Register
- 19.5.22 USARTn_INPUT - USART Input Register
- 19.5.23 USARTn_I2SCTRL - I2S Control Register
- 19.5.24 USARTn_TIMING - Timing Register
- 19.5.25 USARTn_CTRLX - Control Register Extended
- 19.5.26 USARTn_TIMECMP0 - Used to generate interrupts and various delays
- 19.5.27 USARTn_TIMECMP1 - Used to generate interrupts and various delays
- 19.5.28 USARTn_TIMECMP2 - Used to generate interrupts and various delays
- 19.5.29 USARTn_ROUTEPEN - I/O Routing Pin Enable Register
- 19.5.30 USARTn_ROUTELOC0 - I/O Routing Location Register
- 19.5.31 USARTn_ROUTELOC1 - I/O Routing Location Register
- 20. LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
- 20.1 Introduction
- 20.2 Features
- 20.3 Functional Description
- 20.4 Register Map
- 20.5 Register Description
- 20.5.1 LEUARTn_CTRL - Control Register (Async Reg)
- 20.5.2 LEUARTn_CMD - Command Register (Async Reg)
- 20.5.3 LEUARTn_STATUS - Status Register
- 20.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg)
- 20.5.5 LEUARTn_STARTFRAME - Start Frame Register (Async Reg)
- 20.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg)
- 20.5.7 LEUARTn_RXDATAX - Receive Buffer Data Extended Register (Actionable Reads)
- 20.5.8 LEUARTn_RXDATA - Receive Buffer Data Register (Actionable Reads)
- 20.5.9 LEUARTn_RXDATAXP - Receive Buffer Data Extended Peek Register
- 20.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg)
- 20.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg)
- 20.5.12 LEUARTn_IF - Interrupt Flag Register
- 20.5.13 LEUARTn_IFS - Interrupt Flag Set Register
- 20.5.14 LEUARTn_IFC - Interrupt Flag Clear Register
- 20.5.15 LEUARTn_IEN - Interrupt Enable Register
- 20.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg)
- 20.5.17 LEUARTn_FREEZE - Freeze Register
- 20.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register
- 20.5.19 LEUARTn_ROUTEPEN - I/O Routing Pin Enable Register
- 20.5.20 LEUARTn_ROUTELOC0 - I/O Routing Location Register
- 20.5.21 LEUARTn_INPUT - LEUART Input Register
- 21. TIMER/WTIMER - Timer/Counter
- 21.1 Introduction
- 21.2 Features
- 21.3 Functional Description
- 21.3.1 Counter Modes
- 21.3.1.1 Events
- 21.3.1.2 Operation
- 21.3.1.3 Clock Source
- 21.3.1.4 Peripheral Clock (HFPERCLK)
- 21.3.1.5 Compare/ Capture Channel 1 Input
- 21.3.1.6 Underflow/Overflow from Neighboring Timer
- 21.3.1.7 One-Shot Mode
- 21.3.1.8 Top Value Buffer
- 21.3.1.9 Quadrature Decoder
- 21.3.1.10 X2 Decoding Mode
- 21.3.1.11 X4 Decoding Mode
- 21.3.1.12 TIMER/WTIMER Rotational Position
- 21.3.2 Compare/Capture Channels
- 21.3.2.1 Input Pin Logic
- 21.3.2.2 Compare/Capture Registers
- 21.3.2.3 Input Capture
- 21.3.2.4 Period/Pulse-Width Capture
- 21.3.2.5 Compare
- 21.3.2.6 Compare Mode Registers
- 21.3.2.7 Frequency Generation (FRG)
- 21.3.2.8 Pulse-Width Modulation (PWM)
- 21.3.2.9 Up-count (Single-slope) PWM
- 21.3.2.10 2x Count Mode (Up-count)
- 21.3.2.11 Up/Down-count (Dual-slope) PWM
- 21.3.2.12 2x Count Mode (Up/Down-count)
- 21.3.2.13 Timer Configuration Lock
- 21.3.3 Dead-Time Insertion Unit
- 21.3.4 Debug Mode
- 21.3.5 Interrupts, DMA and PRS Output
- 21.3.6 GPIO Input/Output
- 21.3.1 Counter Modes
- 21.4 Register Map
- 21.5 Register Description
- 21.5.1 TIMERn_CTRL - Control Register
- 21.5.2 TIMERn_CMD - Command Register
- 21.5.3 TIMERn_STATUS - Status Register
- 21.5.4 TIMERn_IF - Interrupt Flag Register
- 21.5.5 TIMERn_IFS - Interrupt Flag Set Register
- 21.5.6 TIMERn_IFC - Interrupt Flag Clear Register
- 21.5.7 TIMERn_IEN - Interrupt Enable Register
- 21.5.8 TIMERn_TOP - Counter Top Value Register
- 21.5.9 TIMERn_TOPB - Counter Top Value Buffer Register
- 21.5.10 TIMERn_CNT - Counter Value Register
- 21.5.11 TIMERn_LOCK - TIMER Configuration Lock Register
- 21.5.12 TIMERn_ROUTEPEN - I/O Routing Pin Enable Register
- 21.5.13 TIMERn_ROUTELOC0 - I/O Routing Location Register
- 21.5.14 TIMERn_ROUTELOC2 - I/O Routing Location Register
- 21.5.15 TIMERn_CCx_CTRL - CC Channel Control Register
- 21.5.16 TIMERn_CCx_CCV - CC Channel Value Register (Actionable Reads)
- 21.5.17 TIMERn_CCx_CCVP - CC Channel Value Peek Register
- 21.5.18 TIMERn_CCx_CCVB - CC Channel Buffer Register
- 21.5.19 TIMERn_DTCTRL - DTI Control Register
- 21.5.20 TIMERn_DTTIME - DTI Time Control Register
- 21.5.21 TIMERn_DTFC - DTI Fault Configuration Register
- 21.5.22 TIMERn_DTOGEN - DTI Output Generation Enable Register
- 21.5.23 TIMERn_DTFAULT - DTI Fault Register
- 21.5.24 TIMERn_DTFAULTC - DTI Fault Clear Register
- 21.5.25 TIMERn_DTLOCK - DTI Configuration Lock Register
- 22. LETIMER - Low Energy Timer
- 22.1 Introduction
- 22.2 Features
- 22.3 Functional Description
- 22.4 Register Map
- 22.5 Register Description
- 22.5.1 LETIMERn_CTRL - Control Register (Async Reg)
- 22.5.2 LETIMERn_CMD - Command Register
- 22.5.3 LETIMERn_STATUS - Status Register
- 22.5.4 LETIMERn_CNT - Counter Value Register
- 22.5.5 LETIMERn_COMP0 - Compare Value Register 0 (Async Reg)
- 22.5.6 LETIMERn_COMP1 - Compare Value Register 1 (Async Reg)
- 22.5.7 LETIMERn_REP0 - Repeat Counter Register 0 (Async Reg)
- 22.5.8 LETIMERn_REP1 - Repeat Counter Register 1 (Async Reg)
- 22.5.9 LETIMERn_IF - Interrupt Flag Register
- 22.5.10 LETIMERn_IFS - Interrupt Flag Set Register
- 22.5.11 LETIMERn_IFC - Interrupt Flag Clear Register
- 22.5.12 LETIMERn_IEN - Interrupt Enable Register
- 22.5.13 LETIMERn_SYNCBUSY - Synchronization Busy Register
- 22.5.14 LETIMERn_ROUTEPEN - I/O Routing Pin Enable Register
- 22.5.15 LETIMERn_ROUTELOC0 - I/O Routing Location Register
- 22.5.16 LETIMERn_PRSSEL - PRS Input Select Register
- 23. CRYOTIMER - Ultra Low Energy Timer/Counter
- 23.1 Introduction
- 23.2 Features
- 23.3 Functional Description
- 23.4 Register Map
- 23.5 Register Description
- 23.5.1 CRYOTIMER_CTRL - Control Register
- 23.5.2 CRYOTIMER_PERIODSEL - Interrupt Duration
- 23.5.3 CRYOTIMER_CNT - Counter Value
- 23.5.4 CRYOTIMER_EM4WUEN - Wake Up Enable
- 23.5.5 CRYOTIMER_IF - Interrupt Flag Register
- 23.5.6 CRYOTIMER_IFS - Interrupt Flag Set Register
- 23.5.7 CRYOTIMER_IFC - Interrupt Flag Clear Register
- 23.5.8 CRYOTIMER_IEN - Interrupt Enable Register
- 24. VDAC - Digital to Analog Converter
- 24.1 Introduction
- 24.2 Features
- 24.3 Functional Description
- 24.3.1 Enabling and Disabling a Channel
- 24.3.2 Conversions
- 24.3.3 Reference Selection
- 24.3.4 Warmup Time and Initial Conversion
- 24.3.5 Analog Output
- 24.3.6 Output Mode
- 24.3.7 Async Mode
- 24.3.8 Refresh Timer
- 24.3.9 Clock Prescaling
- 24.3.10 High Speed
- 24.3.11 Sine Generation Mode
- 24.3.12 Interrupt Flags
- 24.3.13 PRS Outputs
- 24.3.14 DMA Request
- 24.3.15 LESENSE Trigger Mode
- 24.3.16 Opamps
- 24.3.17 Calibration
- 24.3.18 Warmup Mode
- 24.4 Register Map
- 24.5 Register Description
- 24.5.1 VDACn_CTRL - Control Register
- 24.5.2 VDACn_STATUS - Status Register
- 24.5.3 VDACn_CH0CTRL - Channel 0 Control Register
- 24.5.4 VDACn_CH1CTRL - Channel 1 Control Register
- 24.5.5 VDACn_CMD - Command Register
- 24.5.6 VDACn_IF - Interrupt Flag Register
- 24.5.7 VDACn_IFS - Interrupt Flag Set Register
- 24.5.8 VDACn_IFC - Interrupt Flag Clear Register
- 24.5.9 VDACn_IEN - Interrupt Enable Register
- 24.5.10 VDACn_CH0DATA - Channel 0 Data Register
- 24.5.11 VDACn_CH1DATA - Channel 1 Data Register
- 24.5.12 VDACn_COMBDATA - Combined Data Register
- 24.5.13 VDACn_CAL - Calibration Register
- 24.5.14 VDACn_OPAx_APORTREQ - Operational Amplifier APORT Request Status Register
- 24.5.15 VDACn_OPAx_APORTCONFLICT - Operational Amplifier APORT Conflict Status Register
- 24.5.16 VDACn_OPAx_CTRL - Operational Amplifier Control Register
- 24.5.17 VDACn_OPAx_TIMER - Operational Amplifier Timer Control Register
- 24.5.18 VDACn_OPAx_MUX - Operational Amplifier Mux Configuration Register
- 24.5.19 VDACn_OPAx_OUT - Operational Amplifier Output Configuration Register
- 24.5.20 VDACn_OPAx_CAL - Operational Amplifier Calibration Register
- 25. OPAMP - Operational Amplifier
- 25.1 Introduction
- 25.2 Features
- 25.3 Functional Description
- 25.3.1 Opamp Configuration
- 25.3.1.1 Enable Sources
- 25.3.1.2 Warmup Time
- 25.3.1.3 Settle Time
- 25.3.1.4 Startup Delay
- 25.3.1.5 Input Configuration
- 25.3.1.6 Output Configuration
- 25.3.1.7 Gain Programming
- 25.3.1.8 Offset Calibration
- 25.3.1.9 Disabling of Rail-to-Rail Operation
- 25.3.1.10 Unity Gain Bandwidth Scaling
- 25.3.1.11 Opamp Output Scaling
- 25.3.2 Interrupts and PRS Output
- 25.3.3 APORT Request and Conflict Status
- 25.3.4 Opamp Modes
- 25.3.4.1 General Opamp Mode
- 25.3.4.2 Voltage Follower Unity Gain
- 25.3.4.3 Inverting input PGA
- 25.3.4.4 Non-inverting PGA
- 25.3.4.5 Cascaded Inverting PGA
- 25.3.4.6 Cascaded Non-inverting PGA
- 25.3.4.7 Two Opamp Differential Amplifier
- 25.3.4.8 Three Opamp Differential Amplifier
- 25.3.4.9 Instrumentation Amplifier
- 25.3.4.10 Common Reference
- 25.3.4.11 Dual Buffer ADC Driver
- 25.3.5 Opamp VDAC Combination
- 25.3.1 Opamp Configuration
- 25.4 Register Map
- 25.5 Register Description
- 26. ACMP - Analog Comparator
- 26.1 Introduction
- 26.2 Features
- 26.3 Functional Description
- 26.4 Register Map
- 26.5 Register Description
- 26.5.1 ACMPn_CTRL - Control Register
- 26.5.2 ACMPn_INPUTSEL - Input Selection Register
- 26.5.3 ACMPn_STATUS - Status Register
- 26.5.4 ACMPn_IF - Interrupt Flag Register
- 26.5.5 ACMPn_IFS - Interrupt Flag Set Register
- 26.5.6 ACMPn_IFC - Interrupt Flag Clear Register
- 26.5.7 ACMPn_IEN - Interrupt Enable Register
- 26.5.8 ACMPn_APORTREQ - APORT Request Status Register
- 26.5.9 ACMPn_APORTCONFLICT - APORT Conflict Status Register
- 26.5.10 ACMPn_HYSTERESIS0 - Hysteresis 0 Register
- 26.5.11 ACMPn_HYSTERESIS1 - Hysteresis 1 Register
- 26.5.12 ACMPn_ROUTEPEN - I/O Routing Pine Enable Register
- 26.5.13 ACMPn_ROUTELOC0 - I/O Routing Location Register
- 26.5.14 ACMPn_EXTIFCTRL - External override interface control
- 27. ADC - Analog to Digital Converter
- 27.1 Introduction
- 27.2 Features
- 27.3 Functional Description
- 27.3.1 Clock Selection
- 27.3.2 Conversions
- 27.3.3 ADC Modes
- 27.3.4 Warm-up Time
- 27.3.5 Input Selection
- 27.3.6 Reference Selection and Input Range Definition
- 27.3.7 Programming of Bias Current
- 27.3.8 Feature Set
- 27.3.9 Interrupts, PRS Output
- 27.3.10 DMA Request
- 27.3.11 Calibration
- 27.3.12 EM2 Deep Sleep or EM3 Stop Operation
- 27.3.13 ASYNC ADC_CLK Usage Restrictions and Benefits
- 27.3.14 Window Compare Function
- 27.3.15 ADC Programming Model
- 27.4 Register Map
- 27.5 Register Description
- 27.5.1 ADCn_CTRL - Control Register
- 27.5.2 ADCn_CMD - Command Register
- 27.5.3 ADCn_STATUS - Status Register
- 27.5.4 ADCn_SINGLECTRL - Single Channel Control Register
- 27.5.5 ADCn_SINGLECTRLX - Single Channel Control Register continued
- 27.5.6 ADCn_SCANCTRL - Scan Control Register
- 27.5.7 ADCn_SCANCTRLX - Scan Control Register continued
- 27.5.8 ADCn_SCANMASK - Scan Sequence Input Mask Register
- 27.5.9 ADCn_SCANINPUTSEL - Input Selection register for Scan mode
- 27.5.10 ADCn_SCANNEGSEL - Negative Input select register for Scan
- 27.5.11 ADCn_CMPTHR - Compare Threshold Register
- 27.5.12 ADCn_BIASPROG - Bias Programming Register for various analog blocks used in ADC operation.
- 27.5.13 ADCn_CAL - Calibration Register
- 27.5.14 ADCn_IF - Interrupt Flag Register
- 27.5.15 ADCn_IFS - Interrupt Flag Set Register
- 27.5.16 ADCn_IFC - Interrupt Flag Clear Register
- 27.5.17 ADCn_IEN - Interrupt Enable Register
- 27.5.18 ADCn_SINGLEDATA - Single Conversion Result Data (Actionable Reads)
- 27.5.19 ADCn_SCANDATA - Scan Conversion Result Data (Actionable Reads)
- 27.5.20 ADCn_SINGLEDATAP - Single Conversion Result Data Peek Register
- 27.5.21 ADCn_SCANDATAP - Scan Sequence Result Data Peek Register
- 27.5.22 ADCn_SCANDATAX - Scan Sequence Result Data + Data Source Register (Actionable Reads)
- 27.5.23 ADCn_SCANDATAXP - Scan Sequence Result Data + Data Source Peek Register
- 27.5.24 ADCn_APORTREQ - APORT Request Status Register
- 27.5.25 ADCn_APORTCONFLICT - APORT Conflict Status Register
- 27.5.26 ADCn_SINGLEFIFOCOUNT - Single FIFO Count Register
- 27.5.27 ADCn_SCANFIFOCOUNT - Scan FIFO Count Register
- 27.5.28 ADCn_SINGLEFIFOCLEAR - Single FIFO Clear Register
- 27.5.29 ADCn_SCANFIFOCLEAR - Scan FIFO Clear Register
- 27.5.30 ADCn_APORTMASTERDIS - APORT Bus Master Disable Register
- 28. IDAC - Current Digital to Analog Converter
- 28.1 Introduction
- 28.2 Features
- 28.3 Functional Description
- 28.4 Register Map
- 28.5 Register Description
- 28.5.1 IDAC_CTRL - Control Register
- 28.5.2 IDAC_CURPROG - Current Programming Register
- 28.5.3 IDAC_DUTYCONFIG - Duty Cycle Configuration Register
- 28.5.4 IDAC_STATUS - Status Register
- 28.5.5 IDAC_IF - Interrupt Flag Register
- 28.5.6 IDAC_IFS - Interrupt Flag Set Register
- 28.5.7 IDAC_IFC - Interrupt Flag Clear Register
- 28.5.8 IDAC_IEN - Interrupt Enable Register
- 28.5.9 IDAC_APORTREQ - APORT Request Status Register
- 28.5.10 IDAC_APORTCONFLICT - APORT Request Status Register
- 29. LESENSE - Low Energy Sensor Interface
- 29.1 Introduction
- 29.2 Features
- 29.3 Functional description
- 29.3.1 Channel Configuration
- 29.3.2 Scan Sequence
- 29.3.3 Sensor Timing
- 29.3.4 Sensor Interaction
- 29.3.5 Sensor Sampling
- 29.3.6 Sensor Evaluation
- 29.3.7 Decoder
- 29.3.8 Measurement Results
- 29.3.9 VDAC Interface
- 29.3.10 ACMP Interface
- 29.3.11 ACMP and VDAC Duty Cycling
- 29.3.12 ADC Interface
- 29.3.13 DMA Requests
- 29.3.14 PRS Output
- 29.3.15 RAM
- 29.3.16 Application Examples
- 29.4 Register Map
- 29.5 Register Description
- 29.5.1 LESENSE_CTRL - Control Register (Async Reg)
- 29.5.2 LESENSE_TIMCTRL - Timing Control Register (Async Reg)
- 29.5.3 LESENSE_PERCTRL - Peripheral Control Register (Async Reg)
- 29.5.4 LESENSE_DECCTRL - Decoder control Register (Async Reg)
- 29.5.5 LESENSE_BIASCTRL - Bias Control Register (Async Reg)
- 29.5.6 LESENSE_EVALCTRL - LESENSE evaluation control (Async Reg)
- 29.5.7 LESENSE_PRSCTRL - PRS control register (Async Reg)
- 29.5.8 LESENSE_CMD - Command Register
- 29.5.9 LESENSE_CHEN - Channel enable Register (Async Reg)
- 29.5.10 LESENSE_SCANRES - Scan result register (Async Reg)
- 29.5.11 LESENSE_STATUS - Status Register (Async Reg)
- 29.5.12 LESENSE_PTR - Result buffer pointers (Async Reg)
- 29.5.13 LESENSE_BUFDATA - Result buffer data register (Async Reg) (Actionable Reads)
- 29.5.14 LESENSE_CURCH - Current channel index (Async Reg)
- 29.5.15 LESENSE_DECSTATE - Current decoder state (Async Reg)
- 29.5.16 LESENSE_SENSORSTATE - Decoder input register (Async Reg)
- 29.5.17 LESENSE_IDLECONF - GPIO Idle phase configuration (Async Reg)
- 29.5.18 LESENSE_ALTEXCONF - Alternative excite pin configuration (Async Reg)
- 29.5.19 LESENSE_IF - Interrupt Flag Register
- 29.5.20 LESENSE_IFS - Interrupt Flag Set Register
- 29.5.21 LESENSE_IFC - Interrupt Flag Clear Register
- 29.5.22 LESENSE_IEN - Interrupt Enable Register
- 29.5.23 LESENSE_SYNCBUSY - Synchronization Busy Register
- 29.5.24 LESENSE_ROUTEPEN - I/O Routing Register (Async Reg)
- 29.5.25 LESENSE_STx_TCONFA - State transition configuration A (Async Reg)
- 29.5.26 LESENSE_STx_TCONFB - State transition configuration B (Async Reg)
- 29.5.27 LESENSE_BUFx_DATA - Scan results (Async Reg)
- 29.5.28 LESENSE_CHx_TIMING - Scan configuration (Async Reg)
- 29.5.29 LESENSE_CHx_INTERACT - Scan configuration (Async Reg)
- 29.5.30 LESENSE_CHx_EVAL - Scan configuration (Async Reg)
- 30. GPCRC - General Purpose Cyclic Redundancy Check
- 30.1 Introduction
- 30.2 Features
- 30.3 Functional Description
- 30.4 Register Map
- 30.5 Register Description
- 30.5.1 GPCRC_CTRL - Control Register
- 30.5.2 GPCRC_CMD - Command Register
- 30.5.3 GPCRC_INIT - CRC Init Value
- 30.5.4 GPCRC_POLY - CRC Polynomial Value
- 30.5.5 GPCRC_INPUTDATA - Input 32-bit Data Register
- 30.5.6 GPCRC_INPUTDATAHWORD - Input 16-bit Data Register
- 30.5.7 GPCRC_INPUTDATABYTE - Input 8-bit Data Register
- 30.5.8 GPCRC_DATA - CRC Data Register
- 30.5.9 GPCRC_DATAREV - CRC Data Reverse Register
- 30.5.10 GPCRC_DATABYTEREV - CRC Data Byte Reverse Register
- 31. TRNG - True Random Number Generator
- 31.1 Introduction
- 31.2 Features
- 31.3 Functional Description
- 31.4 Register Map
- 31.5 Register Description
- 31.5.1 TRNGn_CONTROL - Main Control Register
- 31.5.2 TRNGn_FIFOLEVEL - FIFO Level Register (Actionable Reads)
- 31.5.3 TRNGn_FIFODEPTH - FIFO Depth Register
- 31.5.4 TRNGn_KEY0 - Key Register 0
- 31.5.5 TRNGn_KEY1 - Key Register 1
- 31.5.6 TRNGn_KEY2 - Key Register 2
- 31.5.7 TRNGn_KEY3 - Key Register 3
- 31.5.8 TRNGn_TESTDATA - Test Data Register
- 31.5.9 TRNGn_STATUS - Status Register
- 31.5.10 TRNGn_INITWAITVAL - Initial Wait Counter
- 31.5.11 TRNGn_FIFO - FIFO Data (Actionable Reads)
- 32. CRYPTO - Crypto Accelerator
- 32.1 Introduction
- 32.2 Features
- 32.3 Usage and Programming Interface
- 32.4 Functional Description
- 32.5 Register Map
- 32.6 Register Description
- 32.6.1 CRYPTO_CTRL - Control Register
- 32.6.2 CRYPTO_WAC - Wide Arithmetic Configuration
- 32.6.3 CRYPTO_CMD - Command Register
- 32.6.4 CRYPTO_STATUS - Status Register
- 32.6.5 CRYPTO_DSTATUS - Data Status Register
- 32.6.6 CRYPTO_CSTATUS - Control Status Register
- 32.6.7 CRYPTO_KEY - KEY Register Access (No Bit Access) (Actionable Reads)
- 32.6.8 CRYPTO_KEYBUF - KEY Buffer Register Access (No Bit Access) (Actionable Reads)
- 32.6.9 CRYPTO_SEQCTRL - Sequence Control
- 32.6.10 CRYPTO_SEQCTRLB - Sequence Control B
- 32.6.11 CRYPTO_IF - AES Interrupt Flags
- 32.6.12 CRYPTO_IFS - Interrupt Flag Set Register
- 32.6.13 CRYPTO_IFC - Interrupt Flag Clear Register
- 32.6.14 CRYPTO_IEN - Interrupt Enable Register
- 32.6.15 CRYPTO_SEQ0 - Sequence register 0
- 32.6.16 CRYPTO_SEQ1 - Sequence Register 1
- 32.6.17 CRYPTO_SEQ2 - Sequence Register 2
- 32.6.18 CRYPTO_SEQ3 - Sequence Register 3
- 32.6.19 CRYPTO_SEQ4 - Sequence Register 4
- 32.6.20 CRYPTO_DATA0 - DATA0 Register Access (No Bit Access) (Actionable Reads)
- 32.6.21 CRYPTO_DATA1 - DATA1 Register Access (No Bit Access) (Actionable Reads)
- 32.6.22 CRYPTO_DATA2 - DATA2 Register Access (No Bit Access) (Actionable Reads)
- 32.6.23 CRYPTO_DATA3 - DATA3 Register Access (No Bit Access) (Actionable Reads)
- 32.6.24 CRYPTO_DATA0XOR - DATA0XOR Register Access (No Bit Access) (Actionable Reads)
- 32.6.25 CRYPTO_DATA0BYTE - DATA0 Register Byte Access (No Bit Access) (Actionable Reads)
- 32.6.26 CRYPTO_DATA1BYTE - DATA1 Register Byte Access (No Bit Access) (Actionable Reads)
- 32.6.27 CRYPTO_DATA0XORBYTE - DATA0 Register Byte XOR Access (No Bit Access) (Actionable Reads)
- 32.6.28 CRYPTO_DATA0BYTE12 - DATA0 Register Byte 12 Access (No Bit Access)
- 32.6.29 CRYPTO_DATA0BYTE13 - DATA0 Register Byte 13 Access (No Bit Access)
- 32.6.30 CRYPTO_DATA0BYTE14 - DATA0 Register Byte 14 Access (No Bit Access)
- 32.6.31 CRYPTO_DATA0BYTE15 - DATA0 Register Byte 15 Access (No Bit Access)
- 32.6.32 CRYPTO_DDATA0 - DDATA0 Register Access (No Bit Access) (Actionable Reads)
- 32.6.33 CRYPTO_DDATA1 - DDATA1 Register Access (No Bit Access) (Actionable Reads)
- 32.6.34 CRYPTO_DDATA2 - DDATA2 Register Access (No Bit Access) (Actionable Reads)
- 32.6.35 CRYPTO_DDATA3 - DDATA3 Register Access (No Bit Access) (Actionable Reads)
- 32.6.36 CRYPTO_DDATA4 - DDATA4 Register Access (No Bit Access) (Actionable Reads)
- 32.6.37 CRYPTO_DDATA0BIG - DDATA0 Register Big Endian Access (No Bit Access) (Actionable Reads)
- 32.6.38 CRYPTO_DDATA0BYTE - DDATA0 Register Byte Access (No Bit Access) (Actionable Reads)
- 32.6.39 CRYPTO_DDATA1BYTE - DDATA1 Register Byte Access (No Bit Access) (Actionable Reads)
- 32.6.40 CRYPTO_DDATA0BYTE32 - DDATA0 Register Byte 32 access. (No Bit Access)
- 32.6.41 CRYPTO_QDATA0 - QDATA0 Register Access (No Bit Access) (Actionable Reads)
- 32.6.42 CRYPTO_QDATA1 - QDATA1 Register Access (No Bit Access) (Actionable Reads)
- 32.6.43 CRYPTO_QDATA1BIG - QDATA1 Register Big Endian Access (No Bit Access) (Actionable Reads)
- 32.6.44 CRYPTO_QDATA0BYTE - QDATA0 Register Byte Access (No Bit Access) (Actionable Reads)
- 32.6.45 CRYPTO_QDATA1BYTE - QDATA1 Register Byte Access (No Bit Access) (Actionable Reads)
- 33. GPIO - General Purpose Input/Output
- 33.1 Introduction
- 33.2 Features
- 33.3 Functional Description
- 33.4 Register Map
- 33.5 Register Description
- 33.5.1 GPIO_Px_CTRL - Port Control Register
- 33.5.2 GPIO_Px_MODEL - Port Pin Mode Low Register
- 33.5.3 GPIO_Px_MODEH - Port Pin Mode High Register
- 33.5.4 GPIO_Px_DOUT - Port Data Out Register
- 33.5.5 GPIO_Px_DOUTTGL - Port Data Out Toggle Register
- 33.5.6 GPIO_Px_DIN - Port Data In Register
- 33.5.7 GPIO_Px_PINLOCKN - Port Unlocked Pins Register
- 33.5.8 GPIO_Px_OVTDIS - Over Voltage Disable for all modes
- 33.5.9 GPIO_EXTIPSELL - External Interrupt Port Select Low Register
- 33.5.10 GPIO_EXTIPSELH - External Interrupt Port Select High Register
- 33.5.11 GPIO_EXTIPINSELL - External Interrupt Pin Select Low Register
- 33.5.12 GPIO_EXTIPINSELH - External Interrupt Pin Select High Register
- 33.5.13 GPIO_EXTIRISE - External Interrupt Rising Edge Trigger Register
- 33.5.14 GPIO_EXTIFALL - External Interrupt Falling Edge Trigger Register
- 33.5.15 GPIO_EXTILEVEL - External Interrupt Level Register
- 33.5.16 GPIO_IF - Interrupt Flag Register
- 33.5.17 GPIO_IFS - Interrupt Flag Set Register
- 33.5.18 GPIO_IFC - Interrupt Flag Clear Register
- 33.5.19 GPIO_IEN - Interrupt Enable Register
- 33.5.20 GPIO_EM4WUEN - EM4 wake up Enable Register
- 33.5.21 GPIO_ROUTEPEN - I/O Routing Pin Enable Register
- 33.5.22 GPIO_ROUTELOC0 - I/O Routing Location Register
- 33.5.23 GPIO_ROUTELOC1 - I/O Routing Location Register 1
- 33.5.24 GPIO_INSENSE - Input Sense Register
- 33.5.25 GPIO_LOCK - Configuration Lock Register
- 34. APORT - Analog Port
- 35. CSEN - Capacitive Sense Module
- 35.1 Introduction
- 35.2 Features
- 35.3 Timing
- 35.4 Conversion Types
- 35.5 Input Configuration
- 35.6 Converison Modes
- 35.7 Output Data
- 35.8 Low Frequency Noise Filter (Chopping)
- 35.9 Wake on Threshold and Exponential Moving Average
- 35.10 Analog Adjustments
- 35.11 DMA Interface
- 35.12 Register Map
- 35.13 Register Description
- 35.13.1 CSEN_CTRL - Control
- 35.13.2 CSEN_TIMCTRL - Timing Control
- 35.13.3 CSEN_CMD - Command
- 35.13.4 CSEN_STATUS - Status
- 35.13.5 CSEN_PRSSEL - PRS Select
- 35.13.6 CSEN_DATA - Output Data
- 35.13.7 CSEN_SCANMASK0 - Scan Channel Mask 0
- 35.13.8 CSEN_SCANINPUTSEL0 - Scan Input Selection 0
- 35.13.9 CSEN_SCANMASK1 - Scan Channel Mask 1
- 35.13.10 CSEN_SCANINPUTSEL1 - Scan Input Selection 1
- 35.13.11 CSEN_APORTREQ - APORT Request Status
- 35.13.12 CSEN_APORTCONFLICT - APORT Request Conflict
- 35.13.13 CSEN_CMPTHR - Comparator Threshold
- 35.13.14 CSEN_EMA - Exponential Moving Average
- 35.13.15 CSEN_EMACTRL - Exponential Moving Average Control
- 35.13.16 CSEN_SINGLECTRL - Single Conversion Control
- 35.13.17 CSEN_DMBASELINE - Delta Modulation Baseline
- 35.13.18 CSEN_DMCFG - Delta Modulation Configuration
- 35.13.19 CSEN_ANACTRL - Analog Control
- 35.13.20 CSEN_IF - Interrupt Flag
- 35.13.21 CSEN_IFS - Interrupt Flag Set
- 35.13.22 CSEN_IFC - Interrupt Flag Clear
- 35.13.23 CSEN_IEN - Interrupt Enable
- 36. Revision History
- Appendix 1. Abbreviations