Efr32xg13 Reference Manual

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EFR32xG13 Wireless Gecko
Reference Manual
The Wireless Gecko portfolio of SoCs (EFR32) include Mighty
Gecko (EFR32MG13), Blue Gecko (EFR32BG13), and Flex
Gecko (EFR32FG13) families. With support for Zigbee®, Thread,
Bluetooth Low Energy (BLE) and proprietary protocols, the Wireless Gecko portfolio is ideal for enabling energy-friendly wireless
networking for IoT devices.
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup
times, a scalable high-power amplifier, an integrated balun and no-compromise MCU
features.

KEY FEATURES

• 32-bit ARM® Cortex-M4 core with 40 MHz
maximum operating frequency
• Scalable Memory and Radio configuration
options available in several footprint
compatible QFN packages
• 12-channel Peripheral Reflex System
enabling autonomous interaction of MCU
peripherals
• Autonomous Hardware Crypto Accelerator
and True Random Number Generator
• Integrated balun for 2.4 GHz and
integrated PA with up to 19 dBm transmit
power for 2.4 GHz and 20 dBm transmit
power for Sub-GHz radios
• Integrated DC-DC with RF noise mitigation
• Integrated PLFRCO eliminates external 32
kHz crystal for BLE applications

Core / Memory

ARM CortexTM M4 processor
with DSP extensions, FPU and MPU

ETM

Debug Interface

Clock Management

Flash Program
Memory

LDMA
Controller

RAM Memory

H-F Crystal
Oscillator

H-F
RC Oscillator

Auxiliary H-F RC
Oscillator

L-F
RC Oscillator

L-F Crystal
Oscillator

Precision L-F
RC Oscillator

Energy Management
Voltage
Regulator

Voltage Monitor

DC-DC
Converter

Power-On Reset

CRYPTO
CRC

Brown-Out
Detector

Ultra L-F RC
Oscillator

Other

True Random
Number Generator
SMU

32-bit bus
Peripheral Reflex System

Radio Transceiver
Sub GHz

RFSENSE

BALUN

I
LNA
RF Frontend
Q

BUFC

I/O Ports

Timers and Triggers

External
Interrupts

Timer/Counter

General
Purpose I/O

Low Energy
Timer

Protocol Timer

IFADC
Low Energy
UARTTM

2.4 GHz

PGA

USART

To Sub GHz
receive I/Q
mixers and PA

AGC

Frequency
Synthesizer

MOD

To 2.4 GHz receive
I/Q mixers and PA

RAC

FRC

I
LNA
RF Frontend

Serial
Interfaces

DEMOD

CRC

RFSENSE

I2C

Low Energy
Sensor Interface

Pin Reset

Pulse Counter

Watchdog Timer

Pin Wakeup

Real Time
Counter and
Calendar

Cryotimer

To Sub GHz
and 2.4 GHz PA

Analog I/F
ADC
Analog
Comparator
IDAC
Capacitive
Touch
VDAC
Op-Amp

Lowest power mode with peripheral operational:
EM0—Active

EM1—Sleep

EM2—Deep Sleep

EM3—Stop

silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

EM4—Hibernate

EM4—Shutoff

Preliminary Rev. 0.5

Table of Contents
1. About This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Introduction.

. 1

1.2 Conventions

. 2

1.3 Related Documentation

. 3

2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Introduction.

. 5

2.2 Block Diagrams .

. 6

2.3 MCU Features overview .

. 7

2.4 Oscillators and Clocks .

. 9

2.5 RF Frequency Synthesizer

. 9

2.6 Modulation Modes .

. 9

2.7 Transmit Mode

.10

2.8 Receive Mode .

.10

2.9 Data Buffering .

.10

2.10 Unbuffered Data Transfer

.10

2.11 Frame Format Support

.11

2.12 Hardware CRC Support .

.11

2.13 Convolutional Encoding / Decoding .

.11

2.14 Binary Block Encoding / Decoding

.11

2.15 Data Encryption and Authentication .

.12

2.16 Timers .

.13

2.17 RF Test Modes .

.13

3. System Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Introduction.

.14

3.2 Features.

.15

3.3 Functional Description . . . . .
3.3.1 Interrupt Operation . . . . .
3.3.1.1 Avoiding Extraneous Interrupts .
3.3.1.2 IFC Read-clear Operation . .
3.3.2 Interrupt Request Lines (IRQ) . .

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4. Memory and Bus System . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Introduction.

.20

4.2 Functional Description . . . . . .
4.2.1 Peripheral non-word access behavior
4.2.2 Bit-banding . . . . . . . . .
4.2.3 Peripheral Bit Set and Clear . . .
4.2.4 Peripherals . . . . . . . . .

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silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Preliminary Rev. 0.5

4.2.5 Bus Matrix . . . . . . . .
4.2.5.1 Arbitration . . . . . . . .
4.2.5.2 Peripheral access Performance
4.2.5.3 Bus Faults . . . . . . . .

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4.3 Access to Low Energy Peripherals (Asynchronous Registers) .
4.3.1 Writing. . . . . . . . . . . . . . . . . . .
4.3.1.1 Delayed Synchronization . . . . . . . . . . . .
4.3.1.2 Immediate Synchronization . . . . . . . . . . .
4.3.2 Reading . . . . . . . . . . . . . . . . . .
4.3.3 FREEZE Register . . . . . . . . . . . . . . .

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4.4 Flash .

.31

4.5 SRAM

.32

4.6 DI Page Entry Map .

.33

4.7 DI Page Entry Description . . . . . . . . . . . . . . .
4.7.1 CAL - CRC of DI-page and calibration temperature . . . . .
4.7.2 EXTINFO - External Component description . . . . . . .
4.7.3 EUI48L - EUI48 OUI and Unique identifier . . . . . . . .
4.7.4 EUI48H - OUI . . . . . . . . . . . . . . . . . .
4.7.5 CUSTOMINFO - Custom information . . . . . . . . . .
4.7.6 MEMINFO - Flash page size and misc. chip information
. . .
4.7.7 UNIQUEL - Low 32 bits of device unique number . . . . . .
4.7.8 UNIQUEH - High 32 bits of device unique number . . . . .
4.7.9 MSIZE - Flash and SRAM Memory size in kB . . . . . . .
4.7.10 PART - Part description . . . . . . . . . . . . . .
4.7.11 DEVINFOREV - Device information page revision . . . . .
4.7.12 EMUTEMP - EMU Temperature Calibration Information . . .
4.7.13 ADC0CAL0 - ADC0 calibration register 0 . . . . . . . .
4.7.14 ADC0CAL1 - ADC0 calibration register 1 . . . . . . . .
4.7.15 ADC0CAL2 - ADC0 calibration register 2 . . . . . . . .
4.7.16 ADC0CAL3 - ADC0 calibration register 3 . . . . . . . .
4.7.17 HFRCOCAL0 - HFRCO Calibration Register (4 MHz) . . . .
4.7.18 HFRCOCAL3 - HFRCO Calibration Register (7 MHz) . . . .
4.7.19 HFRCOCAL6 - HFRCO Calibration Register (13 MHz)
. . .
4.7.20 HFRCOCAL7 - HFRCO Calibration Register (16 MHz)
. . .
4.7.21 HFRCOCAL8 - HFRCO Calibration Register (19 MHz)
. . .
4.7.22 HFRCOCAL10 - HFRCO Calibration Register (26 MHz) . . .
4.7.23 HFRCOCAL11 - HFRCO Calibration Register (32 MHz) . . .
4.7.24 HFRCOCAL12 - HFRCO Calibration Register (38 MHz) . . .
4.7.25 AUXHFRCOCAL0 - AUXHFRCO Calibration Register (4 MHz) .
4.7.26 AUXHFRCOCAL3 - AUXHFRCO Calibration Register (7 MHz) .
4.7.27 AUXHFRCOCAL6 - AUXHFRCO Calibration Register (13 MHz)
4.7.28 AUXHFRCOCAL7 - AUXHFRCO Calibration Register (16 MHz)
4.7.29 AUXHFRCOCAL8 - AUXHFRCO Calibration Register (19 MHz)
4.7.30 AUXHFRCOCAL10 - AUXHFRCO Calibration Register (26 MHz)
4.7.31 AUXHFRCOCAL11 - AUXHFRCO Calibration Register (32 MHz)
4.7.32 AUXHFRCOCAL12 - AUXHFRCO Calibration Register (38 MHz)
4.7.33 VMONCAL0 - VMON Calibration Register 0 . . . . . . .

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silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Preliminary Rev. 0.5

4.7.34
4.7.35
4.7.36
4.7.37
4.7.38
4.7.39
4.7.40
4.7.41
4.7.42
4.7.43
4.7.44
4.7.45
4.7.46
4.7.47
4.7.48
4.7.49
4.7.50
4.7.51
4.7.52
4.7.53
4.7.54
4.7.55
4.7.56
4.7.57
4.7.58
4.7.59
4.7.60
4.7.61
4.7.62
4.7.63
4.7.64
4.7.65
4.7.66
4.7.67
4.7.68
4.7.69
4.7.70
4.7.71
4.7.72

VMONCAL1 - VMON Calibration Register 1 . . . . . . . . . . .
VMONCAL2 - VMON Calibration Register 2 . . . . . . . . . . .
IDAC0CAL0 - IDAC0 Calibration Register 0 . . . . . . . . . . .
IDAC0CAL1 - IDAC0 Calibration Register 1 . . . . . . . . . . .
DCDCLNVCTRL0 - DCDC Low-noise VREF Trim Register 0 . . . . .
DCDCLPVCTRL0 - DCDC Low-power VREF Trim Register 0 . . . . .
DCDCLPVCTRL1 - DCDC Low-power VREF Trim Register 1 . . . . .
DCDCLPVCTRL2 - DCDC Low-power VREF Trim Register 2 . . . . .
DCDCLPVCTRL3 - DCDC Low-power VREF Trim Register 3 . . . . .
DCDCLPCMPHYSSEL0 - DCDC LPCMPHYSSEL Trim Register 0 . . .
DCDCLPCMPHYSSEL1 - DCDC LPCMPHYSSEL Trim Register 1 . . .
VDAC0MAINCAL - VDAC0 Cals for Main Path . . . . . . . . . .
VDAC0ALTCAL - VDAC0 Cals for Alternate Path . . . . . . . . .
VDAC0CH1CAL - VDAC0 CH1 Error Cal . . . . . . . . . . . .
OPA0CAL0 - OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1
OPA0CAL1 - OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1
OPA0CAL2 - OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1
OPA0CAL3 - OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1
OPA1CAL0 - OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1
OPA1CAL1 - OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1
OPA1CAL2 - OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1
OPA1CAL3 - OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1
OPA2CAL0 - OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=1
OPA2CAL1 - OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=1
OPA2CAL2 - OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=1
OPA2CAL3 - OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=1
CSENGAINCAL - Cap Sense Gain Adjustment . . . . . . . . . .
OPA0CAL4 - OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0
OPA0CAL5 - OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0
OPA0CAL6 - OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0
OPA0CAL7 - OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0
OPA1CAL4 - OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0
OPA1CAL5 - OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0
OPA1CAL6 - OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0
OPA1CAL7 - OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0
OPA2CAL4 - OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=0
OPA2CAL5 - OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=0
OPA2CAL6 - OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=0
OPA2CAL7 - OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0

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5. Serial Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.1 Introduction.

. 100

5.2 Features.

. 100

5.3 Functional Description . .
5.3.1 Memory Organization. .
5.3.2 Serial Interface . . . .
5.3.2.1 USART1 Configuration
5.3.2.2 Timing . . . . . .

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silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

101
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104

Preliminary Rev. 0.5

5.3.2.3 Hold Operation . . . . . . . . . . . .
5.3.2.4 Power Up and Power Down . . . . . . . .
5.3.3 Instruction Set . . . . . . . . . . . . .
5.3.4 Registers . . . . . . . . . . . . . . .
5.3.4.1 Read Status Register (RDSR, 0x05) . . . . .
5.3.4.2 Write Status Register (WRSR, 0x01) . . . . .
5.3.4.3 Read Function Register (RDFR, 0x48) . . . .
5.3.4.4 Write Function Register (WRFR, 0x42) . . . .
5.3.5 Reading Memory . . . . . . . . . . . .
5.3.5.1 Read Data (RD, 0x03) . . . . . . . . . .
5.3.5.2 Fast Read Data (FR, 0x0B) . . . . . . . .
5.3.6 Programming and Erasing Memory . . . . . .
5.3.6.1 Program/Erase Suspend and Resume . . . .
5.3.6.2 Write Enable (WREN, 0x06) . . . . . . . .
5.3.6.3 Write Disable (WRDI, 0x04) . . . . . . . .
5.3.6.4 Page Program (PP, 0x02). . . . . . . . .
5.3.6.5 Sector Erase (SER, 0xD7 / 0x20) . . . . . .
5.3.6.6 Block Erase 32k (BER32, 0x52) . . . . . .
5.3.6.7 Block Erase 64k (BER64, 0xD8) . . . . . .
5.3.6.8 Chip Erase (CER, 0xC7 / 0x60). . . . . . .
5.3.6.9 Program/Erase Suspend (PERSUS, 0x75 / 0xB0)
5.3.6.10 Program/Erase Resume (PERRSM, 0x7A / 0x30)
5.3.7 Write Protection . . . . . . . . . . . .
5.3.7.1 Sector Unlock (SECUNLOCK, 0x26) . . . . .
5.3.7.2 Sector Lock (SECLOCK, 0x24) . . . . . . .
5.3.8 Security Information Row and Unique ID . . . .
5.3.8.1 Information Row Program (IRP, 0x62) . . . .
5.3.8.2 Information Row Read (IRRD, 0x68) . . . . .
5.3.8.3 Read Unique ID Number (RDUID, 0x4B) . . .
5.3.9 Power Down. . . . . . . . . . . . . .
5.3.9.1 Deep Power Down (DP, 0xB9) . . . . . . .
5.3.9.2 Release Deep Power Down (RDPD, 0xAB). . .
5.3.10 Software Reset . . . . . . . . . . . .
5.3.10.1 Reset Enable (RSTEN, 0x66) . . . . . . .
5.3.10.2 Reset (RST, 0x99). . . . . . . . . . .

6. Radio Transceiver
6.1 Introduction.

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7. DBG - Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.1 Introduction.

. 125

7.2 Features.

. 125

7.3 Functional Description . . . . . . .
7.3.1 Debug Pins . . . . . . . . . .
7.3.2 Embedded Trace Macrocell v3.5 (ETM)
7.3.3 Debug and EM2 Deep Sleep/EM3 Stop
7.3.4 Authentication Access Point . . . .
7.3.4.1 Command Key . . . . . . . .
7.3.4.2 Device Erase . . . . . . . . .
7.3.4.3 System Reset . . . . . . . .
7.3.4.4 System Bus Stall . . . . . . .

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silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

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Preliminary Rev. 0.5

7.3.4.5 User Flash Page CRC . . . . . .
7.3.5 Debug Lock . . . . . . . . . .
7.3.6 AAP Lock. . . . . . . . . . .
7.3.7 Debugger reads of actionable registers.
7.3.8 Debug Recovery . . . . . . . .

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7.4 Register Map .

. 128

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7.5 Register Description . . . . . . . . .
7.5.1 AAP_CMD - Command Register . . .
7.5.2 AAP_CMDKEY - Command Key Register
7.5.3 AAP_STATUS - Status Register . . . .
7.5.4 AAP_CTRL - Control Register . . . .
7.5.5 AAP_CRCCMD - CRC Command Register
7.5.6 AAP_CRCSTATUS - CRC Status Register
7.5.7 AAP_CRCADDR - CRC Address Register
7.5.8 AAP_CRCRESULT - CRC Result Register
7.5.9 AAP_IDR - AAP Identification Register .

8. MSC - Memory System Controller

127
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128
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129
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132
133

. . . . . . . . . . . . . . . . . . . . . . 134

8.1 Introduction.

. 134

8.2 Features.

. 135

8.3 Functional Description . . . . . . . . . . . . .
8.3.1 User Data (UD) Page Description . . . . . . . .
8.3.2 Lock Bits (LB) Page Description . . . . . . . . .
8.3.3 Device Information (DI) Page . . . . . . . . . .
8.3.4 Bootloader . . . . . . . . . . . . . . . .
8.3.5 Device Revision . . . . . . . . . . . . . .
8.3.6 Post-reset Behavior . . . . . . . . . . . . .
8.3.7 Flash Startup . . . . . . . . . . . . . . .
8.3.8 Wait-states . . . . . . . . . . . . . . . .
8.3.8.1 One Wait-state Access . . . . . . . . . . .
8.3.8.2 Zero Wait-state Access . . . . . . . . . . .
8.3.8.3 Operation Above . . . . . . . . . . . . .
8.3.9 Suppressed Conditional Branch Target Prefetch (SCBTP)
8.3.10 Cortex-M4 If-Then Block Folding . . . . . . . .
8.3.11 Instruction Cache. . . . . . . . . . . . . .
8.3.12 Low Voltage Flash Read . . . . . . . . . . .
8.3.13 Erase and Write Operations . . . . . . . . . .
8.3.13.1 Mass erase . . . . . . . . . . . . . . .

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8.4 Register Map .

8.5 Register Description . . . . . . . . . . .
8.5.1 MSC_CTRL - Memory System Control Register
8.5.2 MSC_READCTRL - Read Control Register . .
8.5.3 MSC_WRITECTRL - Write Control Register . .
8.5.4 MSC_WRITECMD - Write Command Register .
8.5.5 MSC_ADDRB - Page Erase/Write Address Buffer
8.5.6 MSC_WDATA - Write Data Register . . . .
8.5.7 MSC_STATUS - Status Register . . . . .

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silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

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149

Preliminary Rev. 0.5

8.5.8 MSC_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . .
8.5.9 MSC_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . .
8.5.10 MSC_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . .
8.5.11 MSC_IEN - Interrupt Enable Register . . . . . . . . . . . . . . .
8.5.12 MSC_LOCK - Configuration Lock Register . . . . . . . . . . . . . .
8.5.13 MSC_CACHECMD - Flash Cache Command Register
. . . . . . . . .
8.5.14 MSC_CACHEHITS - Cache Hits Performance Counter . . . . . . . . .
8.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter . . . . . . .
8.5.16 MSC_MASSLOCK - Mass Erase Lock Register . . . . . . . . . . . .
8.5.17 MSC_STARTUP - Startup Control
. . . . . . . . . . . . . . . .
8.5.18 MSC_CMD - Command Register . . . . . . . . . . . . . . . . .
8.5.19 MSC_BOOTLOADERCTRL - Bootloader read and write enable, write once register
8.5.20 MSC_AAPUNLOCKCMD - Software Unlock AAP Command Register . . . .
8.5.21 MSC_CACHECONFIG0 - Cache Configuration Register 0 . . . . . . . .

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9. LDMA - Linked DMA Controller. . . . . . . . . . . . . . . . . . . . . . . . 162
9.1 Introduction.
9.1.1 Features .

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. 162
. 163

9.2 Block Diagram.

. 164

9.3 Functional Description . . . . . . . . . . . . . .
9.3.1 Channel Descriptor . . . . . . . . . . . . . .
9.3.1.1 DMA Transfer Size . . . . . . . . . . . . . .
9.3.1.2 Source/Destination Increments . . . . . . . . . .
9.3.1.3 Block Size . . . . . . . . . . . . . . . . .
9.3.1.4 Transfer Count . . . . . . . . . . . . . . .
9.3.1.5 Descriptor List . . . . . . . . . . . . . . .
9.3.1.6 Addresses . . . . . . . . . . . . . . . . .
9.3.1.7 Addressing Modes . . . . . . . . . . . . . .
9.3.1.8 Byte Swap . . . . . . . . . . . . . . . . .
9.3.1.9 DMA Size and Source/Destination Increment Programming
9.3.2 Channel Configuration . . . . . . . . . . . . .
9.3.2.1 Address Increment/Decrement . . . . . . . . . .
9.3.2.2 Loop Counter . . . . . . . . . . . . . . . .
9.3.3 Channel Select Configuration . . . . . . . . . . .
9.3.4 Starting a transfer . . . . . . . . . . . . . . .
9.3.4.1 Peripheral Transfer Requests . . . . . . . . . .
9.3.5 Managing Transfer Errors . . . . . . . . . . . .
9.3.6 Arbitration . . . . . . . . . . . . . . . . .
9.3.6.1 Arbitration Priority . . . . . . . . . . . . . .
9.3.6.2 DMA Transfer Arbitration . . . . . . . . . . . .
9.3.7 Channel descriptor data structure . . . . . . . . .
9.3.7.1 XFER descriptor structure . . . . . . . . . . .
9.3.7.2 SYNC descriptor structure . . . . . . . . . . .
9.3.7.3 WRI descriptor structure . . . . . . . . . . . .
9.3.8 Interaction with the EMU . . . . . . . . . . . .
9.3.9 Interrupts . . . . . . . . . . . . . . . . . .
9.3.10 Debugging . . . . . . . . . . . . . . . . .

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9.4 Examples . . . . . . . . . .
9.4.1 Single Direct Register DMA Transfer

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. 177
. 177

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silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

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177

Preliminary Rev. 0.5

9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8

Descriptor Linked List . . . . .
Single Descriptor Looped Transfer .
Descriptor List with Looping . . .
Simple Inter-Channel Synchronization
2D Copy . . . . . . . . . .
Ping-Pong . . . . . . . . .
Scatter-Gather . . . . . . . .

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. 188

9.6 Register Description . . . . . . . . . . . . . . . . . . . . .
9.6.1 LDMA_CTRL - DMA Control Register . . . . . . . . . . . . . .
9.6.2 LDMA_STATUS - DMA Status Register . . . . . . . . . . . . .
9.6.3 LDMA_SYNC - DMA Synchronization Trigger Register (Single-Cycle RMW) .
9.6.4 LDMA_CHEN - DMA Channel Enable Register (Single-Cycle RMW) . . .
9.6.5 LDMA_CHBUSY - DMA Channel Busy Register . . . . . . . . . .
9.6.6 LDMA_CHDONE - DMA Channel Linking Done Register (Single-Cycle RMW)
9.6.7 LDMA_DBGHALT - DMA Channel Debug Halt Register . . . . . . . .
9.6.8 LDMA_SWREQ - DMA Channel Software Transfer Request Register . . .
9.6.9 LDMA_REQDIS - DMA Channel Request Disable Register . . . . . .
9.6.10 LDMA_REQPEND - DMA Channel Requests Pending Register
. . . .
9.6.11 LDMA_LINKLOAD - DMA Channel Link Load Register . . . . . . . .
9.6.12 LDMA_REQCLEAR - DMA Channel Request Clear Register . . . . .
9.6.13 LDMA_IF - Interrupt Flag Register . . . . . . . . . . . . . .
9.6.14 LDMA_IFS - Interrupt Flag Set Register
. . . . . . . . . . . .
9.6.15 LDMA_IFC - Interrupt Flag Clear Register . . . . . . . . . . . .
9.6.16 LDMA_IEN - Interrupt Enable register . . . . . . . . . . . . .
9.6.17 LDMA_CHx_REQSEL - Channel Peripheral Request Select Register
. .
9.6.18 LDMA_CHx_CFG - Channel Configuration Register . . . . . . . .
9.6.19 LDMA_CHx_LOOP - Channel Loop Counter Register . . . . . . . .
9.6.20 LDMA_CHx_CTRL - Channel Descriptor Control Word Register . . . .
9.6.21 LDMA_CHx_SRC - Channel Descriptor Source Data Address Register . .
9.6.22 LDMA_CHx_DST - Channel Descriptor Destination Data Address Register .
9.6.23 LDMA_CHx_LINK - Channel Descriptor Link Structure Address Register .

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9.5 Register Map .

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181
182
184
186
187
189
189
190
191
191
192
192
193
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194
194
195
195
196
196
197
197
198
202
203
204
207
207
208

10. RMU - Reset Management Unit . . . . . . . . . . . . . . . . . . . . . . . 209
10.1 Introduction .

. 209

10.2 Features .

. 209

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10.3 Functional Description . .
10.3.1 Reset levels . . . . .
10.3.2 RMU_RSTCAUSE Register
10.3.3 Power-On Reset (POR) .
10.3.4 Brown-Out Detector (BOD)
10.3.5 RESETn pin Reset . . .
10.3.6 Watchdog Reset . . . .
10.3.7 Lockup Reset . . . . .
10.3.8 System Reset Request. .
10.3.9 Reset state . . . . . .
10.3.10 Register reset signals . .
silabs.com | Smart. Connected. Energy-friendly.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

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214
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214
214
214

Preliminary Rev. 0.5

10.3.10.1 Registers with alternate reset

. 215

10.4 Register Map.

. 216

10.5 Register Description . . . . . . . . .
10.5.1 RMU_CTRL - Control Register . . . . .
10.5.2 RMU_RSTCAUSE - Reset Cause Register
10.5.3 RMU_CMD - Command Register . . . .
10.5.4 RMU_RST - Reset Control Register . . .
10.5.5 RMU_LOCK - Configuration Lock Register .

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217
217
219
220
220
221

11. EMU - Energy Management Unit . . . . . . . . . . . . . . . . . . . . . . . 222
11.1 Introduction .

. 222

11.2 Features .

. 223

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11.3 Functional Description. . . . . . . .
11.3.1 Energy Modes. . . . . . . . . .
11.3.1.1 EM0 Active . . . . . . . . . .
11.3.1.2 EM1 Sleep . . . . . . . . . .
11.3.1.3 EM2 Deep Sleep . . . . . . . .
11.3.1.4 EM3 Stop . . . . . . . . . .
11.3.1.5 EM4 Hibernate . . . . . . . .
11.3.1.6 EM4 Shutoff . . . . . . . . .
11.3.2 Entering Low Energy Modes . . . . .
11.3.2.1 Entry into EM1 Sleep . . . . . .
11.3.2.2 Entry into EM2 Deep Sleep or EM3 Stop
11.3.2.3 Entry into EM4 Hibernate or EM4 Shutoff
11.3.3 Exiting a Low Energy Mode . . . . .
11.3.4 Power Configurations . . . . . . .
11.3.4.1 Power Configuration 0: Unconfigured .
11.3.4.2 Power Configuration 1: No DC-DC . .
11.3.4.3 Power Configuration 2: DC-DC . . .
11.3.5 DC-to-DC Interface . . . . . . . .
11.3.5.1 Bypass Mode . . . . . . . . .
11.3.5.2 Low Power (LP) Mode . . . . . .
11.3.5.3 Low Noise (LN) Mode . . . . . .
11.3.5.4 DC-to-DC Programming Guidelines . .
11.3.6 Analog Peripheral Power Selection. . .
11.3.7 Digital LDO Power Selection . . . . .
11.3.8 IOVDD Connection . . . . . . . .
11.3.9 Voltage Scaling . . . . . . . . .
11.3.9.1 EM01 Voltage Scaling . . . . . .
11.3.9.2 EM23 Voltage Scaling . . . . . .
11.3.9.3 EM4H Voltage Scaling . . . . . .
11.3.9.4 Voltage Scaling Recommended Use .
11.3.10 EM23 Peripheral Retention Disable . .
11.3.11 Brown Out Detector (BOD) . . . . .
11.3.11.1 AVDD BOD. . . . . . . . . .
11.3.11.2 DVDD and DECOUPLE BOD . . .
11.3.12 Voltage Monitor (VMON) . . . . . .
11.3.13 Powering off SRAM blocks . . . . .
11.3.14 Temperature Sensor . . . . . . .
silabs.com | Smart. Connected. Energy-friendly.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

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242
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243

Preliminary Rev. 0.5

11.3.15 Registers latched in EM4.
11.3.16 Register Resets . . . .

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. 244
. 244

11.4 Register Map .

. 245

11.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 247
11.5.1 EMU_CTRL - Control Register . . . . . . . . . . . . . . . . . . . . . . 247
11.5.2 EMU_STATUS - Status Register . . . . . . . . . . . . . . . . . . . . . 249
11.5.3 EMU_LOCK - Configuration Lock Register . . . . . . . . . . . . . . . . . . 251
11.5.4 EMU_RAM0CTRL - Memory Control Register
. . . . . . . . . . . . . . . . 252
11.5.5 EMU_CMD - Command Register . . . . . . . . . . . . . . . . . . . . . 253
11.5.6 EMU_EM4CTRL - EM4 Control Register . . . . . . . . . . . . . . . . . . 254
11.5.7 EMU_TEMPLIMITS - Temperature limits for interrupt generation . . . . . . . . . . 255
11.5.8 EMU_TEMP - Value of last temperature measurement . . . . . . . . . . . . . . 255
11.5.9 EMU_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . . . . 256
11.5.10 EMU_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . . . . 258
11.5.11 EMU_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . . . . 260
11.5.12 EMU_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . . . . 262
11.5.13 EMU_PWRLOCK - Regulator and Supply Lock Register . . . . . . . . . . . . . 264
11.5.14 EMU_PWRCTRL - Power Control Register. . . . . . . . . . . . . . . . . . 265
11.5.15 EMU_DCDCCTRL - DCDC Control . . . . . . . . . . . . . . . . . . . . 266
11.5.16 EMU_DCDCMISCCTRL - DCDC Miscellaneous Control Register
. . . . . . . . . 267
11.5.17 EMU_DCDCZDETCTRL - DCDC Power Train NFET Zero Current Detector Control Register 269
11.5.18 EMU_DCDCCLIMCTRL - DCDC Power Train PFET Current Limiter Control Register . . . 270
11.5.19 EMU_DCDCLNCOMPCTRL - DCDC Low Noise Compensator Control Register
. . . . 271
11.5.20 EMU_DCDCLNVCTRL - DCDC Low Noise Voltage Register . . . . . . . . . . . 272
11.5.21 EMU_DCDCLPVCTRL - DCDC Low Power Voltage Register . . . . . . . . . . . 273
11.5.22 EMU_DCDCLPCTRL - DCDC Low Power Control Register . . . . . . . . . . . . 274
11.5.23 EMU_DCDCLNFREQCTRL - DCDC Low Noise Controller Frequency Control . . . . . 275
11.5.24 EMU_DCDCSYNC - DCDC Read Status Register . . . . . . . . . . . . . . . 275
11.5.25 EMU_VMONAVDDCTRL - VMON AVDD Channel Control . . . . . . . . . . . . 276
11.5.26 EMU_VMONALTAVDDCTRL - Alternate VMON AVDD Channel Control . . . . . . . 277
11.5.27 EMU_VMONDVDDCTRL - VMON DVDD Channel Control . . . . . . . . . . . . 278
11.5.28 EMU_VMONIO0CTRL - VMON IOVDD0 Channel Control . . . . . . . . . . . . 279
11.5.29 EMU_RAM1CTRL - Memory Control Register . . . . . . . . . . . . . . . . 280
11.5.30 EMU_RAM2CTRL - Memory Control Register . . . . . . . . . . . . . . . . 281
11.5.31 EMU_DCDCLPEM01CFG - Configuration bits for low power mode to be applied during EM01,
this field is only relevant if LP mode is used in EM01. . . . . . . . . . . . . . . . 282
11.5.32 EMU_EM23PERNORETAINCMD - Clears corresponding bits in EM23PERNORETAINSTATUS
unlocking access to peripheral . . . . . . . . . . . . . . . . . . . . . . . 283
11.5.33 EMU_EM23PERNORETAINSTATUS - Status indicating if peripherals were powered down in
EM23, subsequently locking access to it. . . . . . . . . . . . . . . . . . . . . 285
11.5.34 EMU_EM23PERNORETAINCTRL - When set corresponding peripherals may get powered down
in EM23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

12. CMU - Clock Management Unit . . . . . . . . . . . . . . . . . . . . . . . 289
12.1 Introduction .

. 289

12.2 Features .

. 290

12.3 Functional Description
12.3.1 System Clocks . .

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. 291
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silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Preliminary Rev. 0.5

12.3.1.1 HFCLK - High Frequency Clock . . . . . .
12.3.1.2 HFCORECLK - High Frequency Core Clock . .
12.3.1.3 HFBUSCLK - High Frequency Bus Clock . . .
12.3.1.4 HFPERCLK - High Frequency Peripheral Clock .
12.3.1.5 HFRADIOCLK - High Frequency Radio Clock .
12.3.1.6 ADCnCLK - ADC Core Clock . . . . . . .
12.3.1.7 LFACLK - Low Frequency A Clock . . . . .
12.3.1.8 LFBCLK - Low Frequency B Clock . . . . .
12.3.1.9 LFECLK - Low Frequency E Clock . . . . .
12.3.1.10 PCNTnCLK - Pulse Counter n Clock . . . .
12.3.1.11 WDOGnCLK - Watchdog Timer Clock. . . .
12.3.1.12 CRYOCLK - Cryotimer Clock . . . . . .
12.3.1.13 RFSENSECLK - RFSENSE Clock . . . . .
12.3.1.14 AUXCLK - Auxiliary Clock. . . . . . . .
12.3.1.15 Debug Trace Clock . . . . . . . . .
12.3.2 Oscillators . . . . . . . . . . . . . .
12.3.2.1 Enabling and Disabling . . . . . . . . .
12.3.2.2 Oscillator Start-up Time and Time-out . . . .
12.3.2.3 Switching Clock Source . . . . . . . . .
12.3.2.4 HFXO Configuration . . . . . . . . . .
12.3.2.5 LFXO Configuration . . . . . . . . . .
12.3.2.6 HFRCO and AUXHFRCO Configuration . . .
12.3.2.7 LFRCO Configuration . . . . . . . . .
12.3.2.8 RC Oscillator Calibration . . . . . . . .
12.3.2.9 Automatic HFXO Start . . . . . . . . .
12.3.3 Configuration For Operating Frequencies . . .
12.3.4 Energy Modes. . . . . . . . . . . . .
12.3.5 Clock Output on a Pin . . . . . . . . . .
12.3.6 Clock Input from a Pin . . . . . . . . . .
12.3.7 Clock Output on PRS . . . . . . . . . .
12.3.8 Error Handling. . . . . . . . . . . . .
12.3.9 Interrupts . . . . . . . . . . . . . .
12.3.10 Wake-up . . . . . . . . . . . . . .
12.3.11 Protection . . . . . . . . . . . . . .
12.3.12 Digital Phase-Locked Loop . . . . . . . .
12.3.12.1 Enabling and Disabling . . . . . . . .
12.3.12.2 Lock Modes . . . . . . . . . . . .
12.3.12.3 Configurations . . . . . . . . . . .
12.3.12.4 Lock Detection . . . . . . . . . . .
12.3.12.5 Spectrum Spreading . . . . . . . . .
12.3.13 Precision Low Frequency Oscillator . . . . .

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12.4 Register Map.

. 318

12.5 Register Description . . . . . . . . . . . . . . . .
12.5.1 CMU_CTRL - CMU Control Register . . . . . . . . . .
12.5.2 CMU_HFRCOCTRL - HFRCO Control Register . . . . . .
12.5.3 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register . . .
12.5.4 CMU_LFRCOCTRL - LFRCO Control Register . . . . . .
12.5.5 CMU_HFXOCTRL - HFXO Control Register . . . . . . .
12.5.6 CMU_HFXOSTARTUPCTRL - HFXO Startup Control . . . .
12.5.7 CMU_HFXOSTEADYSTATECTRL - HFXO Steady State control

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silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

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315
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316
316
316
316
317
317
317
320
320
322
324
325
327
329
330

Preliminary Rev. 0.5

12.5.8 CMU_HFXOTIMEOUTCTRL - HFXO Timeout Control . . . . . . . . . . . . . . 331
12.5.9 CMU_LFXOCTRL - LFXO Control Register . . . . . . . . . . . . . . . . . 334
12.5.10 CMU_DPLLCTRL - DPLL Control Register . . . . . . . . . . . . . . . . . 336
12.5.11 CMU_DPLLCTRL1 - DPLL Control Register . . . . . . . . . . . . . . . . . 337
12.5.12 CMU_CALCTRL - Calibration Control Register . . . . . . . . . . . . . . . . 338
12.5.13 CMU_CALCNT - Calibration Counter Register . . . . . . . . . . . . . . . . 340
12.5.14 CMU_OSCENCMD - Oscillator Enable/Disable Command Register . . . . . . . . . 341
12.5.15 CMU_CMD - Command Register . . . . . . . . . . . . . . . . . . . . 342
12.5.16 CMU_DBGCLKSEL - Debug Trace Clock Select . . . . . . . . . . . . . . . 343
12.5.17 CMU_HFCLKSEL - High Frequency Clock Select Command Register . . . . . . . . 343
12.5.18 CMU_LFACLKSEL - Low Frequency A Clock Select Register . . . . . . . . . . . 344
12.5.19 CMU_LFBCLKSEL - Low Frequency B Clock Select Register . . . . . . . . . . . 345
12.5.20 CMU_LFECLKSEL - Low Frequency E Clock Select Register . . . . . . . . . . . 346
12.5.21 CMU_STATUS - Status Register . . . . . . . . . . . . . . . . . . . . . 347
12.5.22 CMU_HFCLKSTATUS - HFCLK Status Register . . . . . . . . . . . . . . . 349
12.5.23 CMU_HFXOTRIMSTATUS - HFXO Trim Status
. . . . . . . . . . . . . . . 350
12.5.24 CMU_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . . . 351
12.5.25 CMU_IFS - Interrupt Flag Set Register
. . . . . . . . . . . . . . . . . . 354
12.5.26 CMU_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . . . . 356
12.5.27 CMU_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . . . . 359
12.5.28 CMU_HFBUSCLKEN0 - High Frequency Bus Clock Enable Register 0 . . . . . . . . 361
12.5.29 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0 . . . . . 362
12.5.30 CMU_HFRADIOALTCLKEN0 - High Frequency Alternate Radio Peripheral Clock Enable Register
0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
12.5.31 CMU_LFACLKEN0 - Low Frequency A Clock Enable Register 0 (Async Reg) . . . . . 363
12.5.32 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg) . . . . . 364
12.5.33 CMU_LFECLKEN0 - Low Frequency E Clock Enable Register 0 (Async Reg) . . . . . 364
12.5.34 CMU_HFPRESC - High Frequency Clock Prescaler Register . . . . . . . . . . . 365
12.5.35 CMU_HFCOREPRESC - High Frequency Core Clock Prescaler Register . . . . . . . 366
12.5.36 CMU_HFPERPRESC - High Frequency Peripheral Clock Prescaler Register
. . . . . 366
12.5.37 CMU_HFRADIOPRESC - High Frequency Radio Peripheral Clock Prescaler Register . . 367
12.5.38 CMU_HFEXPPRESC - High Frequency Export Clock Prescaler Register . . . . . . . 367
12.5.39 CMU_LFAPRESC0 - Low Frequency A Prescaler Register 0 (Async Reg) . . . . . . . 368
12.5.40 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg)
. . . . . . 369
12.5.41 CMU_LFEPRESC0 - Low Frequency E Prescaler Register 0 (Async Reg). When waking up from
EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect
. . . . . . . . 370
12.5.42 CMU_HFRADIOALTPRESC - High Frequency Alternate Radio Peripheral Clock Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
12.5.43 CMU_SYNCBUSY - Synchronization Busy Register . . . . . . . . . . . . . . 371
12.5.44 CMU_FREEZE - Freeze Register . . . . . . . . . . . . . . . . . . . . 374
12.5.45 CMU_PCNTCTRL - PCNT Control Register . . . . . . . . . . . . . . . . . 375
12.5.46 CMU_ADCCTRL - ADC Control Register . . . . . . . . . . . . . . . . . . 376
12.5.47 CMU_ROUTEPEN - I/O Routing Pin Enable Register . . . . . . . . . . . . . 377
12.5.48 CMU_ROUTELOC0 - I/O Routing Location Register . . . . . . . . . . . . . . 378
12.5.49 CMU_ROUTELOC1 - I/O Routing Location Register . . . . . . . . . . . . . . 379
12.5.50 CMU_LOCK - Configuration Lock Register . . . . . . . . . . . . . . . . . 380
12.5.51 CMU_HFRCOSS - HFRCO Spread Spectrum Register . . . . . . . . . . . . . 381

13. SMU - Security Management Unit . . . . . . . . . . . . . . . . . . . . . . 382
silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Preliminary Rev. 0.5

13.1 Introduction .

. 382

13.2 Features .

. 382

13.3 Functional Description . . . .
13.3.1 PPU - Peripheral Protection Unit
13.3.2 Programming Model. . . . .
13.3.2.1 Interrupt Control/Status . . .
13.3.2.2 PPU Control. . . . . . .

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13.4 Register Map.

. 385

13.5 Register Description . . . . . . . . . . . . . . .
13.5.1 SMU_IF - Interrupt Flag Register . . . . . . . . . .
13.5.2 SMU_IFS - Interrupt Flag Set Register . . . . . . . .
13.5.3 SMU_IFC - Interrupt Flag Clear Register . . . . . . .
13.5.4 SMU_IEN - Interrupt Enable Register . . . . . . . .
13.5.5 SMU_PPUCTRL - PPU Control Register . . . . . . .
13.5.6 SMU_PPUPATD0 - PPU Privilege Access Type Descriptor 0
13.5.7 SMU_PPUPATD1 - PPU Privilege Access Type Descriptor 1
13.5.8 SMU_PPUFS - PPU Fault Status . . . . . . . . . .

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14. RTCC - Real Time Counter and Calendar

383
383
384
385
385
386
386
386
387
387
388
389
391
393

. . . . . . . . . . . . . . . . . . . 395

14.1 Introduction .

. 395

14.2 Features .

. 396

14.3 Functional Description . . . .
14.3.1 Counter . . . . . . . . .
14.3.1.1 Normal Mode . . . . . .
14.3.1.2 Calendar Mode. . . . . .
14.3.1.3 RTCC Initialization . . . .
14.3.2 Capture/Compare Channels . .
14.3.3 Interrupts and PRS Output . .
14.3.3.1 Main Counter Tick PRS Output
14.3.4 Energy Mode Availability . . .
14.3.5 Register Lock . . . . . . .
14.3.6 Oscillator Failure Detection . .
14.3.7 Retention Registers . . . . .
14.3.8 Debug Session . . . . . .

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14.4 Register Map.

. 405

14.5 Register Description . . . . . . . . . . . . . . . . . . .
14.5.1 RTCC_CTRL - Control Register (Async Reg) . . . . . . . . . .
14.5.2 RTCC_PRECNT - Pre-Counter Value Register (Async Reg) . . . . .
14.5.3 RTCC_CNT - Counter Value Register (Async Reg) . . . . . . . .
14.5.4 RTCC_COMBCNT - Combined Pre-Counter and Counter Value Register
14.5.5 RTCC_TIME - Time of day register (Async Reg) . . . . . . . . .
14.5.6 RTCC_DATE - Date register (Async Reg) . . . . . . . . . . .
14.5.7 RTCC_IF - RTCC Interrupt Flags . . . . . . . . . . . . . .
14.5.8 RTCC_IFS - Interrupt Flag Set Register . . . . . . . . . . . .
14.5.9 RTCC_IFC - Interrupt Flag Clear Register . . . . . . . . . . .
14.5.10 RTCC_IEN - Interrupt Enable Register
. . . . . . . . . . .
14.5.11 RTCC_STATUS - Status register
. . . . . . . . . . . . .

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silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

396
397
398
399
400
401
404
404
404
404
404
404
405
406
406
408
408
409
410
411
412
413
414
415
416

Preliminary Rev. 0.5

14.5.12
14.5.13
14.5.14
14.5.15
14.5.16
14.5.17
14.5.18
14.5.19
14.5.20
14.5.21

RTCC_CMD - Command Register . . . . . . . . . . . . . .
RTCC_SYNCBUSY - Synchronization Busy Register . . . . . . . .
RTCC_POWERDOWN - Retention RAM power-down register (Async Reg)
RTCC_LOCK - Configuration Lock Register (Async Reg) . . . . . .
RTCC_EM4WUEN - Wake Up Enable . . . . . . . . . . . . .
RTCC_CCx_CTRL - CC Channel Control Register (Async Reg) . . . .
RTCC_CCx_CCV - Capture/Compare Value Register (Async Reg) . . .
RTCC_CCx_TIME - Capture/Compare Time Register (Async Reg) . . .
RTCC_CCx_DATE - Capture/Compare Date Register (Async Reg) . . .
RTCC_RETx_REG - Retention register . . . . . . . . . . . .

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416
416
417
417
418
419
421
422
423
423

15. WDOG - Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . 424
15.1 Introduction .

. 424

15.2 Features .

. 424

15.3 Functional Description . . .
15.3.1 Clock Source . . . . . .
15.3.2 Debug Functionality . . . .
15.3.3 Energy Mode Handling . . .
15.3.4 Register access . . . . .
15.3.5 Warning Interrupt. . . . .
15.3.6 Window Interrupt . . . . .
15.3.7 PRS as Watchdog Clear . .
15.3.8 PRS Rising Edge Monitoring .

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15.4 Register Map.

. 428

15.5 Register Description . . . . . . . . . . . . . . . .
15.5.1 WDOG_CTRL - Control Register (Async Reg) . . . . . .
15.5.2 WDOG_CMD - Command Register (Async Reg) . . . . . .
15.5.3 WDOG_SYNCBUSY - Synchronization Busy Register . . . .
15.5.4 WDOGn_PCHx_PRSCTRL - PRS Control Register (Async Reg)
15.5.5 WDOG_IF - Watchdog Interrupt Flags . . . . . . . . .
15.5.6 WDOG_IFS - Interrupt Flag Set Register . . . . . . . .
15.5.7 WDOG_IFC - Interrupt Flag Clear Register . . . . . . .
15.5.8 WDOG_IEN - Interrupt Enable Register . . . . . . . . .

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424
425
425
425
425
425
426
427
427
429
429
432
433
434
435
436
437
438

16. PRS - Peripheral Reflex System . . . . . . . . . . . . . . . . . . . . . . . 439
16.1 Introduction .

. 439

16.2 Features .

. 439

16.3 Functional Description . . . . . .
16.3.1 Channel Functions . . . . . . .
16.3.1.1 Operational Mode . . . . . . .
16.3.1.2 Edge Detection and Clock Domains .
16.3.1.3 Configurable PRS Logic . . . . .
16.3.2 Producers . . . . . . . . . .
16.3.3 Consumers. . . . . . . . . .
16.3.4 Event on PRS . . . . . . . . .
16.3.5 DMA Request on PRS . . . . . .
16.3.6 Example . . . . . . . . . .

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silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

440
440
440
441
441
441
442
443
443
444

Preliminary Rev. 0.5

16.4 Register Map.

. 444

16.5 Register Description . . . . . . . . . . . .
16.5.1 PRS_SWPULSE - Software Pulse Register . . .
16.5.2 PRS_SWLEVEL - Software Level Register
. . .
16.5.3 PRS_ROUTEPEN - I/O Routing Pin Enable Register
16.5.4 PRS_ROUTELOC0 - I/O Routing Location Register
16.5.5 PRS_ROUTELOC1 - I/O Routing Location Register
16.5.6 PRS_ROUTELOC2 - I/O Routing Location Register
16.5.7 PRS_CTRL - Control Register . . . . . . . .
16.5.8 PRS_DMAREQ0 - DMA Request 0 Register . . .
16.5.9 PRS_DMAREQ1 - DMA Request 1 Register . . .
16.5.10 PRS_PEEK - PRS Channel Values . . . . . .
16.5.11 PRS_CHx_CTRL - Channel Control Register . .

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17. PCNT - Pulse Counter

445
445
446
447
448
451
453
455
456
457
458
459

. . . . . . . . . . . . . . . . . . . . . . . . . . 466

17.1 Introduction .

. 466

17.2 Features .

. 466

17.3 Functional Description . . . . . . . . .
17.3.1 Pulse Counter Modes . . . . . . . . .
17.3.1.1 Single Input Oversampling Mode . . . . .
17.3.1.2 Externally Clocked Single Input Counter Mode
17.3.1.3 Quadrature decoder modes . . . . . .
17.3.1.4 Externally Clocked Quadrature Decoder Mode
17.3.1.5 Oversampling Quadrature Decoder Mode . .
17.3.2 Hysteresis . . . . . . . . . . . . .
17.3.3 Auxiliary counter . . . . . . . . . . .
17.3.4 Triggered compare and clear. . . . . . .
17.3.5 Register Access . . . . . . . . . . .
17.3.6 Clock Sources. . . . . . . . . . . .
17.3.7 Input Filter . . . . . . . . . . . . .
17.3.8 Edge Polarity . . . . . . . . . . . .
17.3.9 PRS and PCNTn_S0IN,PCNTn_S1IN Inputs .
17.3.10 Interrupts . . . . . . . . . . . . .
17.3.10.1 Underflow and Overflow Interrupts . . . .
17.3.10.2 Direction Change Interrupt . . . . . .
17.3.11 Cascading Pulse Counters . . . . . . .

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17.4 Register Map.

. 481

17.5 Register Description . . . . . . . . . . . . .
17.5.1 PCNTn_CTRL - Control Register (Async Reg) . . .
17.5.2 PCNTn_CMD - Command Register (Async Reg)
. .
17.5.3 PCNTn_STATUS - Status Register . . . . . . .
17.5.4 PCNTn_CNT - Counter Value Register . . . . . .
17.5.5 PCNTn_TOP - Top Value Register . . . . . . .
17.5.6 PCNTn_TOPB - Top Value Buffer Register (Async Reg)
17.5.7 PCNTn_IF - Interrupt Flag Register . . . . . . .
17.5.8 PCNTn_IFS - Interrupt Flag Set Register . . . . .
17.5.9 PCNTn_IFC - Interrupt Flag Clear Register . . . .
17.5.10 PCNTn_IEN - Interrupt Enable Register . . . . .

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silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

467
467
467
467
468
469
471
474
475
476
477
477
477
478
478
478
478
479
480
482
482
486
486
487
487
488
488
489
490
491

Preliminary Rev. 0.5

17.5.11
17.5.12
17.5.13
17.5.14
17.5.15
17.5.16

PCNTn_ROUTELOC0 - I/O Routing Location Register . . .
PCNTn_FREEZE - Freeze Register . . . . . . . . .
PCNTn_SYNCBUSY - Synchronization Busy Register . . .
PCNTn_AUXCNT - Auxiliary Counter Value Register . . . .
PCNTn_INPUT - PCNT Input Register
. . . . . . . .
PCNTn_OVSCFG - Oversampling Config Register (Async Reg)

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492
494
495
495
496
497

18. I2C - Inter-Integrated Circuit Interface . . . . . . . . . . . . . . . . . . . . . 498
18.1 Introduction .

. 498

18.2 Features .

. 498

18.3 Functional Description . . . . . . . . . . .
18.3.1 I2C-Bus Overview . . . . . . . . . . . .
18.3.1.1 START and STOP Conditions . . . . . . . .
18.3.1.2 Bus Transfer . . . . . . . . . . . . .
18.3.1.3 Addresses . . . . . . . . . . . . . .
18.3.1.4 10-bit Addressing . . . . . . . . . . . .
18.3.1.5 Arbitration, Clock Synchronization, Clock Stretching
18.3.2 Enable and Reset . . . . . . . . . . . .
18.3.3 Safely Disabling and Changing Slave Configuration .
18.3.4 Clock Generation. . . . . . . . . . . . .
18.3.5 Arbitration . . . . . . . . . . . . . . .
18.3.6 Buffers . . . . . . . . . . . . . . . .
18.3.6.1 Transmit Buffer and Shift Register . . . . . .
18.3.6.2 Receive Buffer and Shift Register . . . . . .
18.3.7 Master Operation. . . . . . . . . . . . .
18.3.7.1 Master State Machine . . . . . . . . . .
18.3.7.2 Interactions . . . . . . . . . . . . . .
18.3.7.3 Automatic ACK Interaction . . . . . . . . .
18.3.7.4 Reset State . . . . . . . . . . . . . .
18.3.7.5 Master Transmitter . . . . . . . . . . .
18.3.7.6 Master Receiver . . . . . . . . . . . .
18.3.8 Bus States . . . . . . . . . . . . . . .
18.3.9 Slave Operation . . . . . . . . . . . . .
18.3.9.1 Slave State Machine . . . . . . . . . . .
18.3.9.2 Address Recognition . . . . . . . . . . .
18.3.9.3 Slave Transmitter . . . . . . . . . . . .
18.3.9.4 Slave Receiver . . . . . . . . . . . . .
18.3.10 Transfer Automation . . . . . . . . . . .
18.3.10.1 DMA . . . . . . . . . . . . . . . .
18.3.10.2 Automatic ACK . . . . . . . . . . . .
18.3.10.3 Automatic STOP . . . . . . . . . . . .
18.3.11 Using 10-bit Addresses . . . . . . . . . .
18.3.12 Error Handling . . . . . . . . . . . . .
18.3.12.1 ABORT Command . . . . . . . . . . .
18.3.12.2 Bus Reset . . . . . . . . . . . . . .
18.3.12.3 I2C-Bus Errors . . . . . . . . . . . .
18.3.12.4 Bus Lockup . . . . . . . . . . . . .
18.3.12.5 Bus Idle Timeout . . . . . . . . . . . .
18.3.12.6 Clock Low Timeout . . . . . . . . . . .
18.3.12.7 Clock Low Error . . . . . . . . . . . .
18.3.13 DMA Support . . . . . . . . . . . . .

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silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

499
500
501
502
503
503
504
504
504
505
505
505
506
507
508
509
510
511
511
512
514
516
516
517
517
518
520
520
521
521
521
521
521
521
521
522
522
522
522
523
523

Preliminary Rev. 0.5

18.3.14 Interrupts .
18.3.15 Wake-up .

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. 523
. 523

18.4 Register Map.

. 524

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18.5 Register Description . . . . . . . . . . . . . . . . . . . .
18.5.1 I2Cn_CTRL - Control Register . . . . . . . . . . . . . . . .
18.5.2 I2Cn_CMD - Command Register . . . . . . . . . . . . . . .
18.5.3 I2Cn_STATE - State Register . . . . . . . . . . . . . . . .
18.5.4 I2Cn_STATUS - Status Register . . . . . . . . . . . . . . .
18.5.5 I2Cn_CLKDIV - Clock Division Register . . . . . . . . . . . . .
18.5.6 I2Cn_SADDR - Slave Address Register
. . . . . . . . . . . .
18.5.7 I2Cn_SADDRMASK - Slave Address Mask Register . . . . . . . .
18.5.8 I2Cn_RXDATA - Receive Buffer Data Register (Actionable Reads) . . .
18.5.9 I2Cn_RXDOUBLE - Receive Buffer Double Data Register (Actionable Reads)
18.5.10 I2Cn_RXDATAP - Receive Buffer Data Peek Register . . . . . . .
18.5.11 I2Cn_RXDOUBLEP - Receive Buffer Double Data Peek Register
. . .
18.5.12 I2Cn_TXDATA - Transmit Buffer Data Register . . . . . . . . . .
18.5.13 I2Cn_TXDOUBLE - Transmit Buffer Double Data Register . . . . . .
18.5.14 I2Cn_IF - Interrupt Flag Register
. . . . . . . . . . . . . .
18.5.15 I2Cn_IFS - Interrupt Flag Set Register . . . . . . . . . . . . .
18.5.16 I2Cn_IFC - Interrupt Flag Clear Register . . . . . . . . . . . .
18.5.17 I2Cn_IEN - Interrupt Enable Register . . . . . . . . . . . . .
18.5.18 I2Cn_ROUTEPEN - I/O Routing Pin Enable Register . . . . . . . .
18.5.19 I2Cn_ROUTELOC0 - I/O Routing Location Register . . . . . . . .

525
525
528
529
530
531
531
532
532
533
533
534
534
535
536
538
540
542
543
544

19. USART - Universal Synchronous Asynchronous Receiver/Transmitter . . . . . . . . 547
19.1 Introduction .

. 547

19.2 Features .

. 548

19.3 Functional Description . . . . . . . . .
19.3.1 Modes of Operation . . . . . . . . . .
19.3.2 Asynchronous Operation . . . . . . . .
19.3.2.1 Frame Format . . . . . . . . . . .
19.3.2.2 Parity bit Calculation and Handling . . . .
19.3.2.3 Clock Generation . . . . . . . . . .
19.3.2.4 Auto Baud Detection . . . . . . . . .
19.3.2.5 Data Transmission . . . . . . . . .
19.3.2.6 Transmit Buffer Operation . . . . . . .
19.3.2.7 Frame Transmission Control . . . . . .
19.3.2.8 Data Reception. . . . . . . . . . .
19.3.2.9 Receive Buffer Operation . . . . . . .
19.3.2.10 Blocking Incoming Data . . . . . . .
19.3.2.11 Clock Recovery and Filtering. . . . . .
19.3.2.12 Parity Error. . . . . . . . . . . .
19.3.2.13 Framing Error and Break Detection . . .
19.3.2.14 Local Loopback . . . . . . . . . .
19.3.2.15 Asynchronous Half Duplex Communication .
19.3.2.16 Single Data-link . . . . . . . . . .
19.3.2.17 Single Data-link with External Driver . . .
19.3.2.18 Two Data-links . . . . . . . . . .
19.3.2.19 Large Frames . . . . . . . . . . .

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silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

549
550
550
551
552
553
554
554
555
556
556
557
558
559
560
560
561
561
561
562
562
563

Preliminary Rev. 0.5

19.3.2.20 Multi-Processor Mode . . . . . . .
19.3.2.21 Collision Detection . . . . . . . .
19.3.2.22 SmartCard Mode. . . . . . . . .
19.3.3 Synchronous Operation . . . . . . .
19.3.3.1 Frame Format . . . . . . . . . .
19.3.3.2 Clock Generation . . . . . . . . .
19.3.3.3 Master Mode . . . . . . . . . .
19.3.3.4 Operation of USn_CS Pin . . . . . .
19.3.3.5 AUTOTX . . . . . . . . . . . .
19.3.3.6 Slave Mode . . . . . . . . . . .
19.3.3.7 Synchronous Half Duplex Communication
19.3.3.8 I2S . . . . . . . . . . . . . .
19.3.3.9 Word Format . . . . . . . . . .
19.3.3.10 Major Modes . . . . . . . . . .
19.3.3.11 Using I2S Mode . . . . . . . . .
19.3.4 Hardware Flow Control. . . . . . . .
19.3.5 Debug Halt . . . . . . . . . . . .
19.3.6 PRS-triggered Transmissions . . . . .
19.3.7 PRS RX Input . . . . . . . . . .
19.3.8 PRS CLK Input . . . . . . . . . .
19.3.9 DMA Support . . . . . . . . . . .
19.3.10 Timer . . . . . . . . . . . . .
19.3.10.1 Response Timeout . . . . . . . .
19.3.10.2 RX Timeout . . . . . . . . . .
19.3.10.3 Break Detect . . . . . . . . . .
19.3.10.4 TX Start Delay . . . . . . . . .
19.3.10.5 Inter-Character Space . . . . . . .
19.3.10.6 TX Chip Select End Delay . . . . .
19.3.10.7 Response Delay . . . . . . . . .
19.3.10.8 Combined TX and RX Example . . . .
19.3.10.9 Combined TX delay and RX break detect
19.3.10.10 Other Stop Conditions . . . . . .
19.3.11 Interrupts . . . . . . . . . . . .
19.3.12 IrDA Modulator/ Demodulator . . . . .

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19.4 Register Map.

. 583

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19.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . .
19.5.1 USARTn_CTRL - Control Register . . . . . . . . . . . . . . . . . .
19.5.2 USARTn_FRAME - USART Frame Format Register . . . . . . . . . . . .
19.5.3 USARTn_TRIGCTRL - USART Trigger Control register . . . . . . . . . . .
19.5.4 USARTn_CMD - Command Register
. . . . . . . . . . . . . . . . .
19.5.5 USARTn_STATUS - USART Status Register . . . . . . . . . . . . . . .
19.5.6 USARTn_CLKDIV - Clock Control Register . . . . . . . . . . . . . . .
19.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register (Actionable Reads) . . . .
19.5.8 USARTn_RXDATA - RX Buffer Data Register (Actionable Reads) . . . . . . . .
19.5.9 USARTn_RXDOUBLEX - RX Buffer Double Data Extended Register (Actionable Reads)
19.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register (Actionable Reads) . . . .
19.5.11 USARTn_RXDATAXP - RX Buffer Data Extended Peek Register . . . . . . . .
19.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register . . . .
19.5.13 USARTn_TXDATAX - TX Buffer Data Extended Register . . . . . . . . . .
19.5.14 USARTn_TXDATA - TX Buffer Data Register . . . . . . . . . . . . . .
silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

565
565
566
567
567
568
569
569
570
570
570
570
571
572
574
574
574
574
574
575
575
576
578
579
579
580
580
580
580
581
581
581
581
582
584
584
589
591
593
594
595
596
596
597
598
598
599
600
601

Preliminary Rev. 0.5

19.5.15
19.5.16
19.5.17
19.5.18
19.5.19
19.5.20
19.5.21
19.5.22
19.5.23
19.5.24
19.5.25
19.5.26
19.5.27
19.5.28
19.5.29
19.5.30
19.5.31

USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register .
USARTn_TXDOUBLE - TX Buffer Double Data Register . . . . .
USARTn_IF - Interrupt Flag Register . . . . . . . . . . . .
USARTn_IFS - Interrupt Flag Set Register . . . . . . . . . .
USARTn_IFC - Interrupt Flag Clear Register . . . . . . . . .
USARTn_IEN - Interrupt Enable Register . . . . . . . . . . .
USARTn_IRCTRL - IrDA Control Register . . . . . . . . . .
USARTn_INPUT - USART Input Register
. . . . . . . . . .
USARTn_I2SCTRL - I2S Control Register . . . . . . . . . .
USARTn_TIMING - Timing Register . . . . . . . . . . . .
USARTn_CTRLX - Control Register Extended . . . . . . . . .
USARTn_TIMECMP0 - Used to generate interrupts and various delays
USARTn_TIMECMP1 - Used to generate interrupts and various delays
USARTn_TIMECMP2 - Used to generate interrupts and various delays
USARTn_ROUTEPEN - I/O Routing Pin Enable Register . . . . .
USARTn_ROUTELOC0 - I/O Routing Location Register . . . . . .
USARTn_ROUTELOC1 - I/O Routing Location Register . . . . . .

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602
603
604
606
608
610
612
614
616
618
620
621
623
625
627
629
634

20. LEUART - Low Energy Universal Asynchronous Receiver/Transmitter . . . . . . . . 637
20.1 Introduction .

. 637

20.2 Features .

. 638

20.3 Functional Description . . . . . .
20.3.1 Frame Format . . . . . . . . .
20.3.1.1 Parity Bit Calculation and Handling .
20.3.2 Clock Source . . . . . . . . .
20.3.3 Clock Generation. . . . . . . .
20.3.4 Data Transmission . . . . . . .
20.3.4.1 Transmit Buffer Operation . . . .
20.3.4.2 Frame Transmission Control . . .
20.3.5 Data Reception . . . . . . . .
20.3.5.1 Receive Buffer Operation . . . .
20.3.5.2 Blocking Incoming Data . . . . .
20.3.5.3 Data Sampling . . . . . . . .
20.3.5.4 Parity Error . . . . . . . . .
20.3.5.5 Framing Error and Break Detection .
20.3.5.6 Programmable Start Frame . . .
20.3.5.7 Programmable Signal Frame . . .
20.3.5.8 Multi-Processor Mode . . . . .
20.3.6 Loopback . . . . . . . . . .
20.3.7 Half Duplex Communication . . . .
20.3.7.1 Single Data-link . . . . . . .
20.3.7.2 Single Data-link with External Driver
20.3.7.3 Two Data-links . . . . . . . .
20.3.8 Transmission Delay . . . . . . .
20.3.9 PRS RX Input . . . . . . . .
20.3.10 DMA Support . . . . . . . .
20.3.11 Pulse Generator/ Pulse Extender . .
20.3.11.1 Interrupts . . . . . . . . .
20.3.12 Register access. . . . . . . .

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.
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silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

639
640
640
640
641
641
642
642
643
643
644
644
644
645
645
645
646
646
646
647
647
647
647
648
648
649
649
649

Preliminary Rev. 0.5

20.4 Register Map.

20.5 Register Description . . . . . . . . . . . . . . . . . . . . . .
20.5.1 LEUARTn_CTRL - Control Register (Async Reg) . . . . . . . . . . .
20.5.2 LEUARTn_CMD - Command Register (Async Reg) . . . . . . . . . . .
20.5.3 LEUARTn_STATUS - Status Register . . . . . . . . . . . . . . .
20.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg) . . . . . . . .
20.5.5 LEUARTn_STARTFRAME - Start Frame Register (Async Reg) . . . . . . .
20.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg) . . . . . . .
20.5.7 LEUARTn_RXDATAX - Receive Buffer Data Extended Register (Actionable Reads)
20.5.8 LEUARTn_RXDATA - Receive Buffer Data Register (Actionable Reads) . . . .
20.5.9 LEUARTn_RXDATAXP - Receive Buffer Data Extended Peek Register . . . .
20.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg) .
20.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg)
. . . . .
20.5.12 LEUARTn_IF - Interrupt Flag Register . . . . . . . . . . . . . . .
20.5.13 LEUARTn_IFS - Interrupt Flag Set Register . . . . . . . . . . . . .
20.5.14 LEUARTn_IFC - Interrupt Flag Clear Register . . . . . . . . . . . .
20.5.15 LEUARTn_IEN - Interrupt Enable Register . . . . . . . . . . . . .
20.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg) . . . . . .
20.5.17 LEUARTn_FREEZE - Freeze Register
. . . . . . . . . . . . . .
20.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register . . . . . . . .
20.5.19 LEUARTn_ROUTEPEN - I/O Routing Pin Enable Register . . . . . . . .
20.5.20 LEUARTn_ROUTELOC0 - I/O Routing Location Register . . . . . . . .
20.5.21 LEUARTn_INPUT - LEUART Input Register . . . . . . . . . . . . .

. 650

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.

651
651
654
655
656
656
657
657
658
658
659
660
661
662
663
664
665
666
667
668
669
672

21. TIMER/WTIMER - Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . 673
21.1 Introduction .

. 673

21.2 Features .

. 674

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21.3 Functional Description . . . . . . . .
21.3.1 Counter Modes . . . . . . . . . .
21.3.1.1 Events . . . . . . . . . . . .
21.3.1.2 Operation . . . . . . . . . . .
21.3.1.3 Clock Source . . . . . . . . . .
21.3.1.4 Peripheral Clock (HFPERCLK) . . . .
21.3.1.5 Compare/ Capture Channel 1 Input . . .
21.3.1.6 Underflow/Overflow from Neighboring Timer
21.3.1.7 One-Shot Mode . . . . . . . . .
21.3.1.8 Top Value Buffer . . . . . . . . .
21.3.1.9 Quadrature Decoder . . . . . . . .
21.3.1.10 X2 Decoding Mode . . . . . . . .
21.3.1.11 X4 Decoding Mode . . . . . . . .
21.3.1.12 TIMER/WTIMER Rotational Position . .
21.3.2 Compare/Capture Channels . . . . . .
21.3.2.1 Input Pin Logic . . . . . . . . . .
21.3.2.2 Compare/Capture Registers . . . . .
21.3.2.3 Input Capture . . . . . . . . . .
21.3.2.4 Period/Pulse-Width Capture . . . . .
21.3.2.5 Compare . . . . . . . . . . . .
21.3.2.6 Compare Mode Registers . . . . . .
21.3.2.7 Frequency Generation (FRG) . . . . .
21.3.2.8 Pulse-Width Modulation (PWM) . . . .
silabs.com | Smart. Connected. Energy-friendly.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

675
675
676
676
677
677
677
677
677
678
679
680
680
681
681
681
681
682
683
684
685
686
686

Preliminary Rev. 0.5

21.3.2.9 Up-count (Single-slope) PWM . . .
21.3.2.10 2x Count Mode (Up-count) . . .
21.3.2.11 Up/Down-count (Dual-slope) PWM .
21.3.2.12 2x Count Mode (Up/Down-count) .
21.3.2.13 Timer Configuration Lock . . . .
21.3.3 Dead-Time Insertion Unit . . . . .
21.3.3.1 Output Polarity . . . . . . . .
21.3.3.2 PRS Channel as a Source . . . .
21.3.3.3 Fault Handling . . . . . . . .
21.3.3.4 Action on Fault . . . . . . . .
21.3.3.5 Exiting Fault State. . . . . . .
21.3.3.6 DTI Configuration Lock . . . . .
21.3.4 Debug Mode . . . . . . . . .
21.3.5 Interrupts, DMA and PRS Output . .
21.3.6 GPIO Input/Output . . . . . . .

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21.4 Register Map.

. 698

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21.5 Register Description . . . . . . . . . . . . . . . . . .
21.5.1 TIMERn_CTRL - Control Register
. . . . . . . . . . . .
21.5.2 TIMERn_CMD - Command Register . . . . . . . . . . . .
21.5.3 TIMERn_STATUS - Status Register . . . . . . . . . . . .
21.5.4 TIMERn_IF - Interrupt Flag Register . . . . . . . . . . . .
21.5.5 TIMERn_IFS - Interrupt Flag Set Register . . . . . . . . . .
21.5.6 TIMERn_IFC - Interrupt Flag Clear Register . . . . . . . . .
21.5.7 TIMERn_IEN - Interrupt Enable Register . . . . . . . . . .
21.5.8 TIMERn_TOP - Counter Top Value Register . . . . . . . . .
21.5.9 TIMERn_TOPB - Counter Top Value Buffer Register . . . . . .
21.5.10 TIMERn_CNT - Counter Value Register . . . . . . . . . .
21.5.11 TIMERn_LOCK - TIMER Configuration Lock Register . . . . .
21.5.12 TIMERn_ROUTEPEN - I/O Routing Pin Enable Register . . . .
21.5.13 TIMERn_ROUTELOC0 - I/O Routing Location Register . . . . .
21.5.14 TIMERn_ROUTELOC2 - I/O Routing Location Register . . . . .
21.5.15 TIMERn_CCx_CTRL - CC Channel Control Register . . . . . .
21.5.16 TIMERn_CCx_CCV - CC Channel Value Register (Actionable Reads)
21.5.17 TIMERn_CCx_CCVP - CC Channel Value Peek Register . . . .
21.5.18 TIMERn_CCx_CCVB - CC Channel Buffer Register . . . . . .
21.5.19 TIMERn_DTCTRL - DTI Control Register . . . . . . . . . .
21.5.20 TIMERn_DTTIME - DTI Time Control Register . . . . . . . .
21.5.21 TIMERn_DTFC - DTI Fault Configuration Register
. . . . . .
21.5.22 TIMERn_DTOGEN - DTI Output Generation Enable Register . . .
21.5.23 TIMERn_DTFAULT - DTI Fault Register . . . . . . . . . .
21.5.24 TIMERn_DTFAULTC - DTI Fault Clear Register . . . . . . .
21.5.25 TIMERn_DTLOCK - DTI Configuration Lock Register
. . . . .

687
689
690
691
691
692
695
695
696
696
696
696
696
697
697
699
699
702
703
706
707
708
710
711
711
712
712
713
714
719
723
726
726
727
728
730
732
734
735
736
737

22. LETIMER - Low Energy Timer . . . . . . . . . . . . . . . . . . . . . . . . 738
22.1 Introduction .

. 738

22.2 Features .

. 738

22.3 Functional Description
22.3.1 Timer. . . . . .

.
.

. 739
. 739

silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Preliminary Rev. 0.5

22.3.2 Compare Registers . . . . .
22.3.3 Top Value . . . . . . . .
22.3.3.1 Buffered Top Value . . . .
22.3.3.2 Repeat Modes . . . . . .
22.3.3.3 Free-Running Mode . . . .
22.3.3.4 One-shot Mode. . . . . .
22.3.3.5 Buffered Mode . . . . . .
22.3.3.6 Double Mode . . . . . .
22.3.3.7 Clock Source . . . . . .
22.3.3.8 PRS Input Triggers . . . .
22.3.3.9 Debug. . . . . . . . .
22.3.4 Underflow Output Action . . .
22.3.5 PRS Output . . . . . . .
22.3.6 Examples . . . . . . . .
22.3.6.1 Triggered Output Generation .
22.3.6.2 Continuous Output Generation
22.3.6.3 PWM Output . . . . . .
22.3.6.4 Interrupts . . . . . . . .
22.3.7 Register access . . . . . .

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22.4 Register Map.

. 752

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22.5 Register Description . . . . . . . . . . . . . . .
22.5.1 LETIMERn_CTRL - Control Register (Async Reg) . . . .
22.5.2 LETIMERn_CMD - Command Register . . . . . . . .
22.5.3 LETIMERn_STATUS - Status Register . . . . . . . .
22.5.4 LETIMERn_CNT - Counter Value Register . . . . . . .
22.5.5 LETIMERn_COMP0 - Compare Value Register 0 (Async Reg)
22.5.6 LETIMERn_COMP1 - Compare Value Register 1 (Async Reg)
22.5.7 LETIMERn_REP0 - Repeat Counter Register 0 (Async Reg)
22.5.8 LETIMERn_REP1 - Repeat Counter Register 1 (Async Reg)
22.5.9 LETIMERn_IF - Interrupt Flag Register . . . . . . . .
22.5.10 LETIMERn_IFS - Interrupt Flag Set Register . . . . .
22.5.11 LETIMERn_IFC - Interrupt Flag Clear Register . . . . .
22.5.12 LETIMERn_IEN - Interrupt Enable Register . . . . . .
22.5.13 LETIMERn_SYNCBUSY - Synchronization Busy Register .
22.5.14 LETIMERn_ROUTEPEN - I/O Routing Pin Enable Register
22.5.15 LETIMERn_ROUTELOC0 - I/O Routing Location Register .
22.5.16 LETIMERn_PRSSEL - PRS Input Select Register . . . .

739
740
740
740
741
742
743
744
744
745
745
746
748
748
749
750
751
751
752
753
753
755
755
756
756
757
757
758
758
759
760
761
761
762
763
766

23. CRYOTIMER - Ultra Low Energy Timer/Counter . . . . . . . . . . . . . . . . . 769
23.1 Introduction .

. 769

23.2 Features .

. 769

23.3 Functional Description .
23.3.1 Block Diagram . . .
23.3.2 Operation . . . . .
23.3.3 Debug Mode . . . .
23.3.4 Energy Mode availability

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.

23.4 Register Map.

769
770
771
771
772

. 772

23.5 Register Description .

. 773

silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Preliminary Rev. 0.5

23.5.1
23.5.2
23.5.3
23.5.4
23.5.5
23.5.6
23.5.7
23.5.8

CRYOTIMER_CTRL - Control Register . . . .
CRYOTIMER_PERIODSEL - Interrupt Duration .
CRYOTIMER_CNT - Counter Value . . . . .
CRYOTIMER_EM4WUEN - Wake Up Enable . .
CRYOTIMER_IF - Interrupt Flag Register . . .
CRYOTIMER_IFS - Interrupt Flag Set Register .
CRYOTIMER_IFC - Interrupt Flag Clear Register
CRYOTIMER_IEN - Interrupt Enable Register .

24. VDAC - Digital to Analog Converter

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773
774
775
775
776
776
777
777

. . . . . . . . . . . . . . . . . . . . . 778

24.1 Introduction .

. 778

24.2 Features .

. 779

24.3 Functional Description . . . . .
24.3.1 Enabling and Disabling a Channel .
24.3.2 Conversions . . . . . . . .
24.3.2.1 Continuous Mode . . . . . .
24.3.2.2 Sample/Off Mode . . . . . .
24.3.2.3 Conversion Trigger . . . . .
24.3.2.4 PRS Triggers . . . . . . .
24.3.3 Reference Selection. . . . . .
24.3.4 Warmup Time and Initial Conversion
24.3.5 Analog Output. . . . . . . .
24.3.6 Output Mode . . . . . . . .
24.3.6.1 Single Ended Output . . . . .
24.3.6.2 Differential Output . . . . . .
24.3.7 Async Mode . . . . . . . .
24.3.8 Refresh Timer . . . . . . . .
24.3.9 Clock Prescaling . . . . . . .
24.3.10 High Speed . . . . . . . .
24.3.11 Sine Generation Mode . . . .
24.3.12 Interrupt Flags . . . . . . .
24.3.12.1 Conversion Done . . . . .
24.3.12.2 Buffer Level . . . . . . .
24.3.12.3 Overflow/Underflow . . . . .
24.3.12.4 EM2/3 Sleep Error . . . . .
24.3.13 PRS Outputs. . . . . . . .
24.3.14 DMA Request . . . . . . .
24.3.15 LESENSE Trigger Mode . . . .
24.3.16 Opamps . . . . . . . . .
24.3.17 Calibration . . . . . . . .
24.3.17.1 Channel 1 Calibration . . . .
24.3.17.2 Manual Calibration . . . . .
24.3.18 Warmup Mode . . . . . . .

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24.4 Register Map.

. 786

24.5 Register Description . . . . . . . . . . .
24.5.1 VDACn_CTRL - Control Register . . . . . .
24.5.2 VDACn_STATUS - Status Register . . . . .
24.5.3 VDACn_CH0CTRL - Channel 0 Control Register

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silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

779
780
780
780
780
780
780
781
781
781
781
782
782
782
782
782
783
783
784
784
784
784
784
784
784
784
785
785
785
785
785
787
787
790
792

Preliminary Rev. 0.5

24.5.4 VDACn_CH1CTRL - Channel 1 Control Register . . . . . . . . . . . . . .
24.5.5 VDACn_CMD - Command Register . . . . . . . . . . . . . . . . . . .
24.5.6 VDACn_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . .
24.5.7 VDACn_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . .
24.5.8 VDACn_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . .
24.5.9 VDACn_IEN - Interrupt Enable Register
. . . . . . . . . . . . . . . . .
24.5.10 VDACn_CH0DATA - Channel 0 Data Register . . . . . . . . . . . . . . .
24.5.11 VDACn_CH1DATA - Channel 1 Data Register . . . . . . . . . . . . . . .
24.5.12 VDACn_COMBDATA - Combined Data Register . . . . . . . . . . . . . .
24.5.13 VDACn_CAL - Calibration Register . . . . . . . . . . . . . . . . . . .
24.5.14 VDACn_OPAx_APORTREQ - Operational Amplifier APORT Request Status Register .
24.5.15 VDACn_OPAx_APORTCONFLICT - Operational Amplifier APORT Conflict Status Register
24.5.16 VDACn_OPAx_CTRL - Operational Amplifier Control Register . . . . . . . . .
24.5.17 VDACn_OPAx_TIMER - Operational Amplifier Timer Control Register . . . . . . .
24.5.18 VDACn_OPAx_MUX - Operational Amplifier Mux Configuration Register . . . . . .
24.5.19 VDACn_OPAx_OUT - Operational Amplifier Output Configuration Register . . . . .
24.5.20 VDACn_OPAx_CAL - Operational Amplifier Calibration Register . . . . . . . . .

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794
796
797
799
801
803
804
805
805
806
807
808
809
812
813
816
818

25. OPAMP - Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . 820
25.1 Introduction .

. 820

25.2 Features .

. 820

25.3 Functional Description . . . . .
25.3.1 Opamp Configuration . . . . .
25.3.1.1 Enable Sources . . . . . .
25.3.1.2 Warmup Time . . . . . . .
25.3.1.3 Settle Time . . . . . . . .
25.3.1.4 Startup Delay . . . . . . .
25.3.1.5 Input Configuration . . . . .
25.3.1.6 Output Configuration . . . . .
25.3.1.7 Gain Programming . . . . .
25.3.1.8 Offset Calibration . . . . . .
25.3.1.9 Disabling of Rail-to-Rail Operation
25.3.1.10 Unity Gain Bandwidth Scaling .
25.3.1.11 Opamp Output Scaling . . . .
25.3.2 Interrupts and PRS Output . . .
25.3.3 APORT Request and Conflict Status
25.3.4 Opamp Modes . . . . . . .
25.3.4.1 General Opamp Mode . . . .
25.3.4.2 Voltage Follower Unity Gain . .
25.3.4.3 Inverting input PGA . . . . .
25.3.4.4 Non-inverting PGA . . . . .
25.3.4.5 Cascaded Inverting PGA . . .
25.3.4.6 Cascaded Non-inverting PGA . .
25.3.4.7 Two Opamp Differential Amplifier.
25.3.4.8 Three Opamp Differential Amplifier
25.3.4.9 Instrumentation Amplifier . . .
25.3.4.10 Common Reference . . . .
25.3.4.11 Dual Buffer ADC Driver . . .
25.3.5 Opamp VDAC Combination . . .

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.
.
.
.
.

25.4 Register Map.

. 832

silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

821
822
822
822
823
823
823
823
824
824
825
825
825
825
825
825
825
826
826
827
827
828
829
830
831
831
831
832

Preliminary Rev. 0.5

25.5 Register Description .

. 832

26. ACMP - Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . 833
26.1 Introduction .

. 833

26.2 Features .

. 834

26.3 Functional Description . .
26.3.1 Warm-up Time . . . .
26.3.2 Response Time . . . .
26.3.3 Hysteresis . . . . . .
26.3.4 Input Selection . . . .
26.3.5 Capacitive Sense Mode .
26.3.6 Interrupts and PRS Output
26.3.7 Output to GPIO . . . .
26.3.8 APORT Conflicts . . .
26.3.9 Supply Voltage Monitoring
26.3.10 External override interface

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.
.
.
.
.
.
.
.
.
.

26.4 Register Map.

. 842

.
.
.
.
.
.
.
.
.
.
.
.
.
.
.

26.5 Register Description . . . . . . . . . . . . . . .
26.5.1 ACMPn_CTRL - Control Register . . . . . . . . . .
26.5.2 ACMPn_INPUTSEL - Input Selection Register . . . . .
26.5.3 ACMPn_STATUS - Status Register . . . . . . . . .
26.5.4 ACMPn_IF - Interrupt Flag Register . . . . . . . . .
26.5.5 ACMPn_IFS - Interrupt Flag Set Register . . . . . . .
26.5.6 ACMPn_IFC - Interrupt Flag Clear Register . . . . . .
26.5.7 ACMPn_IEN - Interrupt Enable Register . . . . . . .
26.5.8 ACMPn_APORTREQ - APORT Request Status Register . .
26.5.9 ACMPn_APORTCONFLICT - APORT Conflict Status Register
26.5.10 ACMPn_HYSTERESIS0 - Hysteresis 0 Register . . . .
26.5.11 ACMPn_HYSTERESIS1 - Hysteresis 1 Register . . . .
26.5.12 ACMPn_ROUTEPEN - I/O Routing Pine Enable Register .
26.5.13 ACMPn_ROUTELOC0 - I/O Routing Location Register . .
26.5.14 ACMPn_EXTIFCTRL - External override interface control .

835
836
836
837
838
839
841
841
841
841
842
843
843
846
851
852
852
853
854
855
856
858
859
860
861
863

27. ADC - Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . 865
27.1 Introduction .

. 865

27.2 Features .

. 866

27.3 Functional Description . . . . . . . . . .
27.3.1 Clock Selection . . . . . . . . . . . .
27.3.2 Conversions . . . . . . . . . . . . .
27.3.3 ADC Modes . . . . . . . . . . . . .
27.3.3.1 Single Channel Mode . . . . . . . . .
27.3.3.2 Scan Mode . . . . . . . . . . . . .
27.3.4 Warm-up Time . . . . . . . . . . . .
27.3.5 Input Selection . . . . . . . . . . . .
27.3.5.1 Configuring ADC Inputs in Single Channel Mode
27.3.5.2 Configuring ADC Inputs in Scan Mode . . . .
27.3.5.3 APORT Conflicts . . . . . . . . . . .

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.
.
.
.
.
.
.
.
.
.

silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

867
868
868
869
869
869
870
872
873
874
876

Preliminary Rev. 0.5

27.3.6 Reference Selection and Input Range Definition . .
27.3.6.1 Basic Full-Scale Voltage Configuration . . . . .
27.3.6.2 Advanced Full-Scale Voltage Configuration . . .
27.3.7 Programming of Bias Current . . . . . . . .
27.3.8 Feature Set . . . . . . . . . . . . . .
27.3.8.1 Conversion Tailgating . . . . . . . . . .
27.3.8.2 Repetitive Mode . . . . . . . . . . . .
27.3.8.3 Conversion Trigger . . . . . . . . . . .
27.3.8.4 Output Results . . . . . . . . . . . . .
27.3.8.5 Resolution . . . . . . . . . . . . . .
27.3.8.6 Oversampling . . . . . . . . . . . . .
27.3.8.7 Adjustment . . . . . . . . . . . . . .
27.3.8.8 Channel Connection . . . . . . . . . . .
27.3.8.9 Temperature Measurement. . . . . . . . .
27.3.8.10 ADC as a Random Number Generator . . . .
27.3.9 Interrupts, PRS Output . . . . . . . . . . .
27.3.10 DMA Request . . . . . . . . . . . . .
27.3.11 Calibration . . . . . . . . . . . . . .
27.3.11.1 Offset Calibration. . . . . . . . . . . .
27.3.11.2 Gain Calibration . . . . . . . . . . . .
27.3.12 EM2 Deep Sleep or EM3 Stop Operation . . . .
27.3.13 ASYNC ADC_CLK Usage Restrictions and Benefits
27.3.14 Window Compare Function . . . . . . . . .
27.3.15 ADC Programming Model . . . . . . . . .

.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.

27.4 Register Map.

. 891

27.5 Register Description . . . . . . . . . . . . . . . . . . . . . . .
27.5.1 ADCn_CTRL - Control Register . . . . . . . . . . . . . . . . . .
27.5.2 ADCn_CMD - Command Register . . . . . . . . . . . . . . . . .
27.5.3 ADCn_STATUS - Status Register . . . . . . . . . . . . . . . . . .
27.5.4 ADCn_SINGLECTRL - Single Channel Control Register . . . . . . . . . .
27.5.5 ADCn_SINGLECTRLX - Single Channel Control Register continued . . . . . .
27.5.6 ADCn_SCANCTRL - Scan Control Register . . . . . . . . . . . . . .
27.5.7 ADCn_SCANCTRLX - Scan Control Register continued . . . . . . . . . .
27.5.8 ADCn_SCANMASK - Scan Sequence Input Mask Register . . . . . . . . .
27.5.9 ADCn_SCANINPUTSEL - Input Selection register for Scan mode . . . . . . .
27.5.10 ADCn_SCANNEGSEL - Negative Input select register for Scan . . . . . . .
27.5.11 ADCn_CMPTHR - Compare Threshold Register . . . . . . . . . . . .
27.5.12 ADCn_BIASPROG - Bias Programming Register for various analog blocks used in
tion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.5.13 ADCn_CAL - Calibration Register . . . . . . . . . . . . . . . . .
27.5.14 ADCn_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . .
27.5.15 ADCn_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . .
27.5.16 ADCn_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . .
27.5.17 ADCn_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . .
27.5.18 ADCn_SINGLEDATA - Single Conversion Result Data (Actionable Reads) . . .
27.5.19 ADCn_SCANDATA - Scan Conversion Result Data (Actionable Reads) . . . .
27.5.20 ADCn_SINGLEDATAP - Single Conversion Result Data Peek Register
. . . .
27.5.21 ADCn_SCANDATAP - Scan Sequence Result Data Peek Register . . . . . .

silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

. .
. .
. .
. .
. .
. .
. .
. .
. .
. .
. .
. .
ADC
. .
. .
. .
. .
. .
. .
. .
. .
. .
. .

876
877
878
880
880
880
881
882
884
884
885
885
886
886
886
887
887
887
887
888
888
889
889
890

. 892
. 892
. 895
. 896
. 898
. 903
. 906
. 909
. 912
. 914
. 917
. 919
opera. 920
. 921
. 923
. 925
. 927
. 929
. 930
. 930
. 931
. 931

Preliminary Rev. 0.5

27.5.22
. .
27.5.23
27.5.24
27.5.25
27.5.26
27.5.27
27.5.28
27.5.29
27.5.30

ADCn_SCANDATAX - Scan Sequence Result Data + Data Source Register (Actionable Reads)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
ADCn_SCANDATAXP - Scan Sequence Result Data + Data Source Peek Register . . . 932
ADCn_APORTREQ - APORT Request Status Register . . . . . . . . . . . . . 933
ADCn_APORTCONFLICT - APORT Conflict Status Register . . . . . . . . . . . 934
ADCn_SINGLEFIFOCOUNT - Single FIFO Count Register . . . . . . . . . . . . 935
ADCn_SCANFIFOCOUNT - Scan FIFO Count Register . . . . . . . . . . . . . 935
ADCn_SINGLEFIFOCLEAR - Single FIFO Clear Register . . . . . . . . . . . . 936
ADCn_SCANFIFOCLEAR - Scan FIFO Clear Register . . . . . . . . . . . . . 936
ADCn_APORTMASTERDIS - APORT Bus Master Disable Register . . . . . . . . . 937

28. IDAC - Current Digital to Analog Converter. . . . . . . . . . . . . . . . . . . 940
28.1 Introduction .

. 940

28.2 Features .

. 940

28.3 Functional Description . . . .
28.3.1 Current Programming . . . .
28.3.2 IDAC Enable and Warm-up . .
28.3.3 Output Control . . . . . .
28.3.4 APORT Configuration . . . .
28.3.5 Interrupts . . . . . . . .
28.3.6 Minimizing Output Transition . .
28.3.7 Duty Cycle Configuration . . .
28.3.8 Calibration . . . . . . . .
28.3.9 PRS Triggered Charge Injection

.
.
.
.
.
.
.
.
.
.

28.4 Register Map.

. 943

28.5 Register Description . . . . . . . . . . . . . . .
28.5.1 IDAC_CTRL - Control Register
. . . . . . . . . .
28.5.2 IDAC_CURPROG - Current Programming Register . . . .
28.5.3 IDAC_DUTYCONFIG - Duty Cycle Configuration Register .
28.5.4 IDAC_STATUS - Status Register . . . . . . . . . .
28.5.5 IDAC_IF - Interrupt Flag Register . . . . . . . . . .
28.5.6 IDAC_IFS - Interrupt Flag Set Register . . . . . . . .
28.5.7 IDAC_IFC - Interrupt Flag Clear Register . . . . . . .
28.5.8 IDAC_IEN - Interrupt Enable Register . . . . . . . .
28.5.9 IDAC_APORTREQ - APORT Request Status Register
. .
28.5.10 IDAC_APORTCONFLICT - APORT Request Status Register

.
.
.
.
.
.
.
.
.
.
.

941
941
941
942
942
942
942
942
942
943
944
944
946
947
947
948
948
949
949
950
950

29. LESENSE - Low Energy Sensor Interface . . . . . . . . . . . . . . . . . . . 951
29.1 Introduction .

. 952

29.2 Features .

. 952

.
.
.
.
.
.
.

29.3 Functional description .
29.3.1 Channel Configuration
29.3.2 Scan Sequence . .
29.3.3 Sensor Timing. . .
29.3.4 Sensor Interaction .
29.3.5 Sensor Sampling . .
29.3.6 Sensor Evaluation .

silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

953
954
955
956
958
959
960

Preliminary Rev. 0.5

29.3.6.1 Threshold comparison . . .
29.3.6.2 Sliding window . . . . . .
29.3.6.3 Step detection . . . . . .
29.3.7 Decoder. . . . . . . . .
29.3.8 Measurement Results . . . .
29.3.9 VDAC Interface . . . . . .
29.3.10 ACMP Interface . . . . . .
29.3.11 ACMP and VDAC Duty Cycling
29.3.12 ADC Interface . . . . . .
29.3.13 DMA Requests . . . . . .
29.3.14 PRS Output . . . . . . .
29.3.15 RAM . . . . . . . . .
29.3.16 Application Examples . . . .
29.3.16.1 Capacitive Sense . . . .
29.3.16.2 LC sensor . . . . . . .
29.3.16.3 LESENSE Decoder 1 . . .
29.3.16.4 LESENSE Decoder 2 . . .

.
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.
.
.
.
.
.
.
.
.
.
.

29.4 Register Map.

. 973

29.5 Register Description . . . . . . . . . . . . . . . . . . . . . . .
29.5.1 LESENSE_CTRL - Control Register (Async Reg) . . . . . . . . . . . .
29.5.2 LESENSE_TIMCTRL - Timing Control Register (Async Reg) . . . . . . . .
29.5.3 LESENSE_PERCTRL - Peripheral Control Register (Async Reg) . . . . . . .
29.5.4 LESENSE_DECCTRL - Decoder control Register (Async Reg) . . . . . . . .
29.5.5 LESENSE_BIASCTRL - Bias Control Register (Async Reg) . . . . . . . . .
29.5.6 LESENSE_EVALCTRL - LESENSE evaluation control (Async Reg) . . . . . .
29.5.7 LESENSE_PRSCTRL - PRS control register (Async Reg) . . . . . . . . .
29.5.8 LESENSE_CMD - Command Register . . . . . . . . . . . . . . . .
29.5.9 LESENSE_CHEN - Channel enable Register (Async Reg) . . . . . . . . .
29.5.10 LESENSE_SCANRES - Scan result register (Async Reg) . . . . . . . . .
29.5.11 LESENSE_STATUS - Status Register (Async Reg) . . . . . . . . . . .
29.5.12 LESENSE_PTR - Result buffer pointers (Async Reg) . . . . . . . . . . .
29.5.13 LESENSE_BUFDATA - Result buffer data register (Async Reg) (Actionable Reads)
29.5.14 LESENSE_CURCH - Current channel index (Async Reg) . . . . . . . . .
29.5.15 LESENSE_DECSTATE - Current decoder state (Async Reg) . . . . . . . .
29.5.16 LESENSE_SENSORSTATE - Decoder input register (Async Reg) . . . . . .
29.5.17 LESENSE_IDLECONF - GPIO Idle phase configuration (Async Reg) . . . . .
29.5.18 LESENSE_ALTEXCONF - Alternative excite pin configuration (Async Reg) . . .
29.5.19 LESENSE_IF - Interrupt Flag Register . . . . . . . . . . . . . . . .
29.5.20 LESENSE_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . .
29.5.21 LESENSE_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . .
29.5.22 LESENSE_IEN - Interrupt Enable Register . . . . . . . . . . . . . .
29.5.23 LESENSE_SYNCBUSY - Synchronization Busy Register . . . . . . . . .
29.5.24 LESENSE_ROUTEPEN - I/O Routing Register (Async Reg) . . . . . . . .
29.5.25 LESENSE_STx_TCONFA - State transition configuration A (Async Reg) . . . .
29.5.26 LESENSE_STx_TCONFB - State transition configuration B (Async Reg) . . . .
29.5.27 LESENSE_BUFx_DATA - Scan results (Async Reg) . . . . . . . . . . .
29.5.28 LESENSE_CHx_TIMING - Scan configuration (Async Reg) . . . . . . . .
29.5.29 LESENSE_CHx_INTERACT - Scan configuration (Async Reg) . . . . . . .

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.
.
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.
.
.
.
.
.

. 975
. 975
. 978
. 980
. 983
. 986
. 986
. 987
. 988
. 988
. 989
. 990
. 991
. 991
. 992
. 992
. 993
. 994
. 998
. 1001
. 1003
. 1005
. 1007
. 1008
. 1009
. 1011
. 1013
. 1014
. 1015
. 1016

silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

960
961
961
962
965
966
966
966
967
967
967
967
967
968
969
971
972

Preliminary Rev. 0.5

29.5.30 LESENSE_CHx_EVAL - Scan configuration (Async Reg)

30. GPCRC - General Purpose Cyclic Redundancy Check

. 1018

. . . . . . . . . . . . . .1020

30.1 Introduction .

. 1020

30.2 Features .

. 1020

30.3 Functional Description . . . . . . . .
30.3.1 Polynomial Specification . . . . . . .
30.3.2 Input and Output Specification . . . . .
30.3.3 Initialization . . . . . . . . . . .
30.3.4 DMA Usage . . . . . . . . . . .
30.3.5 Byte-Level Bit Reversal and Byte Reordering

.
.
.
.
.
.

. 1021
. 1022
. 1022
. 1022
. 1022
. 1023

30.4 Register Map.

. 1025

.
.
.
.
.
.
.
.
.
.
.

. 1026
. 1026
. 1027
. 1027
. 1028
. 1028
. 1029
. 1029
. 1030
. 1030
. 1031

30.5 Register Description . . . . . . . . . . . . . . .
30.5.1 GPCRC_CTRL - Control Register . . . . . . . . . .
30.5.2 GPCRC_CMD - Command Register . . . . . . . . .
30.5.3 GPCRC_INIT - CRC Init Value . . . . . . . . . . .
30.5.4 GPCRC_POLY - CRC Polynomial Value . . . . . . .
30.5.5 GPCRC_INPUTDATA - Input 32-bit Data Register . . . .
30.5.6 GPCRC_INPUTDATAHWORD - Input 16-bit Data Register .
30.5.7 GPCRC_INPUTDATABYTE - Input 8-bit Data Register . .
30.5.8 GPCRC_DATA - CRC Data Register . . . . . . . . .
30.5.9 GPCRC_DATAREV - CRC Data Reverse Register . . . .
30.5.10 GPCRC_DATABYTEREV - CRC Data Byte Reverse Register

31. TRNG - True Random Number Generator

. . . . . . . . . . . . . . . . . . .1032

31.1 Introduction .

. 1032

31.2 Features .

. 1032

31.3 Functional Description . . . . . .
31.3.1 Built-In Tests . . . . . . . . .
31.3.2 FIFO Interface. . . . . . . . .
31.3.3 Data Format - Byte Ordering . . . .
31.3.4 TRNG Usage . . . . . . . . .
31.3.4.1 Checking the Conditioning Function .
31.3.4.2 Checking the Entropy Source . . .
31.3.4.3 Programming a Random Key . . .
31.3.4.4 Reading Samples . . . . . . .

.
.
.
.
.
.
.
.
.

. 1033
. 1033
. 1033
. 1034
. 1034
. 1035
. 1036
. 1036
. 1036

31.4 Register Map.

. 1036

31.5 Register Description . . . . . . . . . . . . . . . .
31.5.1 TRNGn_CONTROL - Main Control Register . . . . . . .
31.5.2 TRNGn_FIFOLEVEL - FIFO Level Register (Actionable Reads)
31.5.3 TRNGn_FIFODEPTH - FIFO Depth Register . . . . . . .
31.5.4 TRNGn_KEY0 - Key Register 0 . . . . . . . . . . .
31.5.5 TRNGn_KEY1 - Key Register 1 . . . . . . . . . . .
31.5.6 TRNGn_KEY2 - Key Register 2 . . . . . . . . . . .
31.5.7 TRNGn_KEY3 - Key Register 3 . . . . . . . . . . .
31.5.8 TRNGn_TESTDATA - Test Data Register . . . . . . . .
31.5.9 TRNGn_STATUS - Status Register . . . . . . . . . .

.
.
.
.
.
.
.
.
.
.

. 1037
. 1037
. 1039
. 1039
. 1040
. 1040
. 1041
. 1041
. 1042
. 1043

silabs.com | Smart. Connected. Energy-friendly.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Preliminary Rev. 0.5

31.5.10 TRNGn_INITWAITVAL - Initial Wait Counter . .
31.5.11 TRNGn_FIFO - FIFO Data (Actionable Reads) .

.
.

. 1044
. 1044

32. CRYPTO - Crypto Accelerator. . . . . . . . . . . . . . . . . . . . . . . .1045
32.1 Introduction .

. 1045

32.2 Features .

. 1046

32.3 Usage and Programming Interface

. 1046

32.4 Functional Description . . . . . . . .
32.4.1 Data and Key Registers . . . . . . .
32.4.1.1 DATA0 Zero . . . . . . . . . . .
32.4.1.2 DDATA0 and DDATA1 Quick Observation .
32.4.1.3 Result Width . . . . . . . . . .
32.4.2 Instructions and Execution . . . . . .
32.4.2.1 Sequences . . . . . . . . . . .
32.4.2.2 Available Instructions. . . . . . . .
32.4.2.3 MULx Details . . . . . . . . . .
32.4.2.4 DATA1INC and DATA1INCCLR Instructions
32.4.2.5 BBSWAP128 Instruction . . . . . .
32.4.2.6 Carry . . . . . . . . . . . . .
32.4.3 Repeated Sequence . . . . . . . .
32.4.4 AES . . . . . . . . . . . . . .
32.4.5 SHA . . . . . . . . . . . . . .
32.4.6 ECC . . . . . . . . . . . . . .
32.4.7 GCM and GMAC . . . . . . . . . .
32.4.8 DMA . . . . . . . . . . . . . .
32.4.8.1 DMA Initial Bytes Skip . . . . . . .
32.4.8.2 DMA Unaligned Read/Write . . . . .
32.4.9 BUFC Data Transfer . . . . . . . .
32.4.10 Debugging . . . . . . . . . . .
32.4.11 Example: Cipher Block Chaining (CBC) . .
32.4.11.1 CBC Encryption . . . . . . . . .
32.4.11.2 CBC Decryption . . . . . . . . .

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.

. 1047
. 1048
. 1049
. 1050
. 1050
. 1050
. 1051
. 1052
. 1054
. 1054
. 1054
. 1055
. 1055
. 1056
. 1058
. 1058
. 1059
. 1059
. 1060
. 1060
. 1061
. 1062
. 1062
. 1063
. 1064

32.5 Register Map.

. 1065

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.

. 1067
. 1067
. 1070
. 1072
. 1077
. 1078
. 1079
. 1080
. 1081
. 1082
. 1083
. 1084
. 1085
. 1086
. 1087

32.6 Register Description . . . . . . . . . . . . . . . . . . . . . . .
32.6.1 CRYPTO_CTRL - Control Register . . . . . . . . . . . . . . . . .
32.6.2 CRYPTO_WAC - Wide Arithmetic Configuration . . . . . . . . . . . . .
32.6.3 CRYPTO_CMD - Command Register . . . . . . . . . . . . . . . .
32.6.4 CRYPTO_STATUS - Status Register . . . . . . . . . . . . . . . . .
32.6.5 CRYPTO_DSTATUS - Data Status Register . . . . . . . . . . . . . .
32.6.6 CRYPTO_CSTATUS - Control Status Register . . . . . . . . . . . . .
32.6.7 CRYPTO_KEY - KEY Register Access (No Bit Access) (Actionable Reads) . . .
32.6.8 CRYPTO_KEYBUF - KEY Buffer Register Access (No Bit Access) (Actionable Reads)
32.6.9 CRYPTO_SEQCTRL - Sequence Control . . . . . . . . . . . . . . .
32.6.10 CRYPTO_SEQCTRLB - Sequence Control B . . . . . . . . . . . . .
32.6.11 CRYPTO_IF - AES Interrupt Flags . . . . . . . . . . . . . . . . .
32.6.12 CRYPTO_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . .
32.6.13 CRYPTO_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . .
32.6.14 CRYPTO_IEN - Interrupt Enable Register . . . . . . . . . . . . . .
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32.6.15 CRYPTO_SEQ0 - Sequence register 0 . . . . . . . . . . . . . . . . . . 1087
32.6.16 CRYPTO_SEQ1 - Sequence Register 1 . . . . . . . . . . . . . . . . . . 1088
32.6.17 CRYPTO_SEQ2 - Sequence Register 2 . . . . . . . . . . . . . . . . . . 1088
32.6.18 CRYPTO_SEQ3 - Sequence Register 3 . . . . . . . . . . . . . . . . . . 1089
32.6.19 CRYPTO_SEQ4 - Sequence Register 4 . . . . . . . . . . . . . . . . . . 1089
32.6.20 CRYPTO_DATA0 - DATA0 Register Access (No Bit Access) (Actionable Reads) . . . . 1090
32.6.21 CRYPTO_DATA1 - DATA1 Register Access (No Bit Access) (Actionable Reads) . . . . 1090
32.6.22 CRYPTO_DATA2 - DATA2 Register Access (No Bit Access) (Actionable Reads) . . . . 1091
32.6.23 CRYPTO_DATA3 - DATA3 Register Access (No Bit Access) (Actionable Reads) . . . . 1091
32.6.24 CRYPTO_DATA0XOR - DATA0XOR Register Access (No Bit Access) (Actionable Reads) 1092
32.6.25 CRYPTO_DATA0BYTE - DATA0 Register Byte Access (No Bit Access) (Actionable Reads) 1092
32.6.26 CRYPTO_DATA1BYTE - DATA1 Register Byte Access (No Bit Access) (Actionable Reads) 1093
32.6.27 CRYPTO_DATA0XORBYTE - DATA0 Register Byte XOR Access (No Bit Access) (Actionable
Reads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093
32.6.28 CRYPTO_DATA0BYTE12 - DATA0 Register Byte 12 Access (No Bit Access) . . . . . 1094
32.6.29 CRYPTO_DATA0BYTE13 - DATA0 Register Byte 13 Access (No Bit Access) . . . . . 1094
32.6.30 CRYPTO_DATA0BYTE14 - DATA0 Register Byte 14 Access (No Bit Access) . . . . . 1095
32.6.31 CRYPTO_DATA0BYTE15 - DATA0 Register Byte 15 Access (No Bit Access) . . . . . 1095
32.6.32 CRYPTO_DDATA0 - DDATA0 Register Access (No Bit Access) (Actionable Reads) . . . 1096
32.6.33 CRYPTO_DDATA1 - DDATA1 Register Access (No Bit Access) (Actionable Reads) . . . 1096
32.6.34 CRYPTO_DDATA2 - DDATA2 Register Access (No Bit Access) (Actionable Reads) . . . 1097
32.6.35 CRYPTO_DDATA3 - DDATA3 Register Access (No Bit Access) (Actionable Reads) . . . 1097
32.6.36 CRYPTO_DDATA4 - DDATA4 Register Access (No Bit Access) (Actionable Reads) . . . 1098
32.6.37
CRYPTO_DDATA0BIG - DDATA0 Register Big Endian Access (No Bit Access) (Actionable
Reads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098
32.6.38 CRYPTO_DDATA0BYTE - DDATA0 Register Byte Access (No Bit Access) (Actionable Reads)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
32.6.39 CRYPTO_DDATA1BYTE - DDATA1 Register Byte Access (No Bit Access) (Actionable Reads)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
32.6.40 CRYPTO_DDATA0BYTE32 - DDATA0 Register Byte 32 access. (No Bit Access) . . . . 1100
32.6.41 CRYPTO_QDATA0 - QDATA0 Register Access (No Bit Access) (Actionable Reads) . . . 1100
32.6.42 CRYPTO_QDATA1 - QDATA1 Register Access (No Bit Access) (Actionable Reads) . . . 1101
32.6.43
CRYPTO_QDATA1BIG - QDATA1 Register Big Endian Access (No Bit Access) (Actionable
Reads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101
32.6.44 CRYPTO_QDATA0BYTE - QDATA0 Register Byte Access (No Bit Access) (Actionable Reads)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1102
32.6.45 CRYPTO_QDATA1BYTE - QDATA1 Register Byte Access (No Bit Access) (Actionable Reads)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1102

33. GPIO - General Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . 1103
33.1 Introduction .

. 1103

33.2 Features .

. 1104

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. 1105
. 1106
. 1108
. 1108
. 1108
. 1108
. 1108

33.3 Functional Description .
33.3.1 Pin Configuration. . .
33.3.1.1 Over Voltage Tolerance
33.3.1.2 Alternate Port Control
33.3.1.3 Drive Strength . . .
33.3.1.4 Slewrate . . . . .
33.3.1.5 Input Disable . . .
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33.3.1.6 Configuration Lock . .
33.3.2 EM4 Wake-up . . . . .
33.3.3 EM4 Retention . . . .
33.3.4 Alternate Functions . . .
33.3.4.1 Analog Connections . .
33.3.4.2 Debug Connections . .
33.3.5 Interrupt Generation. . .
33.3.5.1 Edge Interrupt Generation
33.3.5.2 Level Interrupt Generation
33.3.6 Output to PRS. . . . .
33.3.7 Synchronization . . . .

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. 1109
. 1109
. 1110
. 1110
. 1110
. 1110
. 1111
. 1111
. 1112
. 1112
. 1112

33.4 Register Map.

. 1113

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. 1115
. 1115
. 1117
. 1122
. 1127
. 1127
. 1128
. 1128
. 1129
. 1130
. 1133
. 1136
. 1139
. 1141
. 1142
. 1143
. 1144
. 1144
. 1145
. 1145
. 1146
. 1147
. 1148
. 1149
. 1150
. 1151

33.5 Register Description . . . . . . . . . . . . . . . . .
33.5.1 GPIO_Px_CTRL - Port Control Register . . . . . . . . .
33.5.2 GPIO_Px_MODEL - Port Pin Mode Low Register . . . . . .
33.5.3 GPIO_Px_MODEH - Port Pin Mode High Register . . . . . .
33.5.4 GPIO_Px_DOUT - Port Data Out Register . . . . . . . . .
33.5.5 GPIO_Px_DOUTTGL - Port Data Out Toggle Register . . . . .
33.5.6 GPIO_Px_DIN - Port Data In Register . . . . . . . . . .
33.5.7 GPIO_Px_PINLOCKN - Port Unlocked Pins Register . . . . .
33.5.8 GPIO_Px_OVTDIS - Over Voltage Disable for all modes . . . .
33.5.9 GPIO_EXTIPSELL - External Interrupt Port Select Low Register .
33.5.10 GPIO_EXTIPSELH - External Interrupt Port Select High Register
33.5.11 GPIO_EXTIPINSELL - External Interrupt Pin Select Low Register
33.5.12 GPIO_EXTIPINSELH - External Interrupt Pin Select High Register
33.5.13 GPIO_EXTIRISE - External Interrupt Rising Edge Trigger Register
33.5.14 GPIO_EXTIFALL - External Interrupt Falling Edge Trigger Register
33.5.15 GPIO_EXTILEVEL - External Interrupt Level Register . . . .
33.5.16 GPIO_IF - Interrupt Flag Register . . . . . . . . . . .
33.5.17 GPIO_IFS - Interrupt Flag Set Register . . . . . . . . .
33.5.18 GPIO_IFC - Interrupt Flag Clear Register . . . . . . . . .
33.5.19 GPIO_IEN - Interrupt Enable Register . . . . . . . . . .
33.5.20 GPIO_EM4WUEN - EM4 wake up Enable Register . . . . .
33.5.21 GPIO_ROUTEPEN - I/O Routing Pin Enable Register . . . .
33.5.22 GPIO_ROUTELOC0 - I/O Routing Location Register . . . . .
33.5.23 GPIO_ROUTELOC1 - I/O Routing Location Register 1 . . . .
33.5.24 GPIO_INSENSE - Input Sense Register . . . . . . . . .
33.5.25 GPIO_LOCK - Configuration Lock Register . . . . . . . .

34. APORT - Analog Port . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152
34.1 Introduction .

. 1152

34.2 Features .

. 1152

34.3 Functional Description .
34.3.1 APORT ABUS Naming .
34.3.2 Managing ABUSes . .

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. 1153
. 1154
. 1157

35. CSEN - Capacitive Sense Module . . . . . . . . . . . . . . . . . . . . . . 1159
35.1 Introduction .

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. 1159

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35.2 Features .

. 1160

35.3 Timing . . . . . . .
35.3.1 Clocks . . . . . .
35.3.2 Conversion Triggers. .
35.3.3 Shutdown and Warmup

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. 1160
. 1160
. 1160
. 1161

35.4 Conversion Types . . . . . . .
35.4.1 SAR Conversion Type . . . . .
35.4.2 Delta Modulation Conversion Type .

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. 1161
. 1161
. 1162

35.5 Input Configuration .

. 1164

35.6 Converison Modes . . . . .
35.6.1 Single Channel Conversions .
35.6.2 Scan Conversions . . . .
35.6.3 Bonded Channel Conversions

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. 1164
. 1165
. 1166
. 1167

35.7 Output Data .

. 1168

35.8 Low Frequency Noise Filter (Chopping) .

. 1169

35.9 Wake on Threshold and Exponential Moving Average .

. 1170

35.10 Analog Adjustments . . . .
35.10.1 Current Reference and Gain
35.10.2 Current Drive . . . . .
35.10.3 Reset (Discharge) Timing .

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. 1171
. 1171
. 1171
. 1171

35.11 DMA Interface .

. 1172

35.12 Register Map .

. 1173

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. 1174
. 1174
. 1178
. 1179
. 1179
. 1180
. 1181
. 1181
. 1182
. 1184
. 1185
. 1187
. 1188
. 1189
. 1189
. 1190
. 1191
. 1192
. 1193
. 1194
. 1195
. 1196
. 1197

35.13 Register Description . . . . . . . . . . . . . .
35.13.1 CSEN_CTRL - Control . . . . . . . . . . . .
35.13.2 CSEN_TIMCTRL - Timing Control . . . . . . . .
35.13.3 CSEN_CMD - Command . . . . . . . . . . .
35.13.4 CSEN_STATUS - Status . . . . . . . . . . .
35.13.5 CSEN_PRSSEL - PRS Select . . . . . . . . .
35.13.6 CSEN_DATA - Output Data . . . . . . . . . .
35.13.7 CSEN_SCANMASK0 - Scan Channel Mask 0 . . . .
35.13.8 CSEN_SCANINPUTSEL0 - Scan Input Selection 0 . .
35.13.9 CSEN_SCANMASK1 - Scan Channel Mask 1 . . . .
35.13.10 CSEN_SCANINPUTSEL1 - Scan Input Selection 1 . .
35.13.11 CSEN_APORTREQ - APORT Request Status
. . .
35.13.12 CSEN_APORTCONFLICT - APORT Request Conflict .
35.13.13 CSEN_CMPTHR - Comparator Threshold . . . . .
35.13.14 CSEN_EMA - Exponential Moving Average . . . .
35.13.15 CSEN_EMACTRL - Exponential Moving Average Control
35.13.16 CSEN_SINGLECTRL - Single Conversion Control . .
35.13.17 CSEN_DMBASELINE - Delta Modulation Baseline . .
35.13.18 CSEN_DMCFG - Delta Modulation Configuration . .
35.13.19 CSEN_ANACTRL - Analog Control . . . . . . .
35.13.20 CSEN_IF - Interrupt Flag . . . . . . . . . . .
35.13.21 CSEN_IFS - Interrupt Flag Set . . . . . . . . .
35.13.22 CSEN_IFC - Interrupt Flag Clear . . . . . . . .
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35.13.23 CSEN_IEN - Interrupt Enable

. 1198

36. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
36.1 Revision 0.5 .

. 1199

36.2 Revision 0.1 .

. 1199

Appendix 1. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .1200

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Reference Manual

About This Document

1. About This Document

1.1 Introduction
This document contains reference material for the EFR32xG13 Wireless Gecko devices. All modules and peripherals in the
EFR32xG13 Wireless Gecko devices are described in general terms. Not all modules are present in all devices and the feature set for
each device might vary. Such differences, including pinout, are covered in the device data sheets.

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1.2 Conventions
Register Names
Register names are given with a module name prefix followed by the short register name:
TIMERn_CTRL - Control Register
The "n" denotes the module number for modules which can exist in more than one instance.
Some registers are grouped which leads to a group name following the module prefix:
GPIO_Px_DOUT - Port Data Out Register
The "x" denotes the different ports.
Bit Fields
Registers contain one or more bit fields which can be 1 to 32 bits wide. Bit fields wider than 1 bit are given with start (x) and stop (y) bit
[y:x].
Bit fields containing more than one bit are unsigned integers unless otherwise is specified.
Unspecified bit field settings must not be used, as this may lead to unpredictable behaviour.
Address
The address for each register can be found by adding the base address of the module found in the Memory Map (see Figure 4.2 System Address Space with Core and Code Space Listing on page 21), and the offset address for the register (found in module Register
Map).
Access Type
The register access types used in the register descriptions are explained in Table 1.1 Register Access Types on page 2.
Table 1.1. Register Access Types
Access Type

Description

Read only. Writes are ignored

Readable and writable

RW1

Readable and writable. Only writes to 1 have effect

(R)W1

Sometimes readable. Only writes to 1 have effect. Currently only
used for IFC registers (see 3.3.1.2 IFC Read-clear Operation)

Read value undefined. Only writes to 1 have effect

Write only. Read value undefined.

RWH

Readable, writable, and updated by hardware

RW(nB), RWH(nB), etc.

"(nB)" suffix indicates that register explicitly does not support peripheral bit set or clear (see 4.2.3 Peripheral Bit Set and Clear)

RW(a), R(a), etc.

"(a)" suffix indicates that register has actionable reads (see
7.3.7 Debugger reads of actionable registers)

Number format
0x prefix is used for hexadecimal numbers
0b prefix is used for binary numbers
Numbers without prefix are in decimal representation.
Reserved
Registers and bit fields marked with reserved are reserved for future use. These should be written to 0 unless otherwise stated in the
Register Description. Reserved bits might be read as 1 in future devices.
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Reset Value
The reset value denotes the value after reset.
Registers denoted with X have unknown value out of reset and need to be initialized before use. Note that read-modify-write operations
on these registers before they are initialized results in undefined register values.
Pin Connections
Pin connections are given with a module prefix followed by a short pin name:
CMU_CLKOUT1 (Clock management unit, clock output pin number 1)
The location for the pin names given in the module documentation can be found in the device-specific datasheet.
1.3 Related Documentation
Further documentation on the EFR32xG13 Wireless Gecko devices and the ARM Cortex-M4 can be found at the Silicon Labs and ARM
web pages:
www.silabs.com
www.arm.com

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System Overview

2. System Overview
Quick Facts
What?
0 1 2 3

The EFR32 Wireless Gecko is a highly integrated,
configurable and low power wireless System-onChip (SoC) with a robust set of MCU and radio peripherals.
Why?
The radio enables support for zigbee, Thread, Bluetooth Low Energy (BLE) and proprietary protocols in
2.4 GHz and sub-GHz frequency bands while the
MCU system allows customized protocols and applications to run efficiently.
How?
Dynamic or fixed packet lengths, optional address
recognition, and flexible CRC and crypto schemes
makes the EFR32xG13 Wireless Gecko ideal for
many low power wireless IoT applications. High performance analog and digital peripherals allows complete applications to run on the EFR32xG13 Wireless Gecko SoC.

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System Overview
2.1 Introduction
The high level features of EFR32xG13 Wireless Gecko include:
• High performance radio transceiver
• Dual-band operation
• Low power consumption in transmit, receive, and standby modes
• Excellent receiver performance, including sensitivity, selectivity and blocking
• Excellent transmitter performance, including programmable output power, low phase noise and PA ramping
• Ultra Low Energy RF Detection for wake-up from any Energy Mode, through RFSENSE
• Configurable protocol support, including standards and customer developed protocols
• Preamble and frame synchronization insertion in transmit and recovery in receive
• Flexible CRC support, including configurable polynomial and multiple CRCs for single data frames
• Basic address filtering performed in hardware
• High performance, low power MCU system
• High Performance 32-bit ARM Cortex-M4 CPU
• Flexible and efficient energy management
• Complete set of digital peripherals
• Peripheral Reflex System (PRS)
• Precision analog interfaces
• Low external component count
• Fully integrated 2.4 GHz BALUN
• Integrated tunable crystal loading capacitors
A further introduction to the MCU and radio system is included in the following sections.
Note:
Detailed performance numbers, current consumption, pinout etc. is available in the device datasheet.

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2.2 Block Diagrams
The block diagram for the EFR32xG13 Wireless Gecko System-On-Chip series is shown in (Figure 2.1 EFR32xG13 Wireless Gecko
System-On-Chip Block Diagram on page 6).

Core / Memory

ARM CortexTM M4 processor
with DSP extensions, FPU and MPU

ETM

Debug Interface

Clock Management

Flash Program
Memory

LDMA
Controller

RAM Memory

H-F Crystal
Oscillator

H-F
RC Oscillator

Auxiliary H-F RC
Oscillator

L-F
RC Oscillator

L-F Crystal
Oscillator

Precision L-F
RC Oscillator

Energy Management
Voltage
Regulator

Voltage Monitor

DC-DC
Converter

Power-On Reset

Other
CRYPTO
CRC
True Random
Number Generator

Brown-Out
Detector

Ultra L-F RC
Oscillator

SMU

32-bit bus
Peripheral Reflex System

Radio Transceiver
Sub GHz

RFSENSE

BALUN

I
LNA
RF Frontend
Q

FRC

Low Energy
UARTTM

To Sub GHz
receive I/Q
mixers and PA

AGC

Frequency
Synthesizer

MOD

To 2.4 GHz receive
I/Q mixers and PA

I/O Ports

Timers and Triggers

External
Interrupts

Timer/Counter

General
Purpose I/O

Low Energy
Timer

Analog I/F

Protocol Timer

IFADC

2.4 GHz

PGA

USART

RAC

DEMOD
BUFC

I
LNA
RF Frontend

Serial
Interfaces

CRC

RFSENSE

I2C

Low Energy
Sensor Interface

Pin Reset

Pulse Counter

Watchdog Timer

Pin Wakeup

Real Time
Counter and
Calendar

Cryotimer

To Sub GHz
and 2.4 GHz PA

ADC
Analog
Comparator
IDAC
Capacitive
Touch
VDAC
Op-Amp

Lowest power mode with peripheral operational:
EM0—Active

EM1—Sleep

EM2—Deep Sleep

EM3—Stop

EM4—Hibernate

EM4—Shutoff

Figure 2.1. EFR32xG13 Wireless Gecko System-On-Chip Block Diagram

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System Overview
2.3 MCU Features overview
• ARM Cortex-M4 CPU platform
• High Performance 32-bit processor @ up to 40 MHz
• Memory Protection Unit
• Wake-up Interrupt Controller
• Flexible Energy Management System
• 5 Energy Modes from EM0 to EM4 provide flexibility between higher performance and low power
• Power routing configurations including DCDC control
• Voltage Monitoring and Brown Out Detection
• State Retention
• Up to 512 KB Flash
• Up to 64 KB RAM
• Up to 31 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 8 Channel DMA Controller
• Alternate/primary descriptors with scatter-gather/ping-pong operation
• 12 Channel Peripheral Reflex System
• Autonomous inter-peripheral signaling enables smart operation in low energy modes
• CRYPTO Advanced Encryption Standard Accelerator
• AES encryption / decryption, with 128 or 256 bit keys
• Multiple AES modes of operation, including Counter (CTR), Galois/Counter Mode (GCM), Cipher Block Chaining (CBC), Cipher
Feedback (CFB) and Output Feedback (OFB).
• Accelerated SHA-1 and SHA-2 (SHA-224 / SHA-256)
• Accelerated Elliptic Curve Cryptography (ECC), with binary or prime fields
• Flexible 256-bit ALU and sequencer
• True Random Number Generator (TRNG)
• General Purpose Cyclic Redundancy Check
• Programmable 16-bit polynomial, fixed 32-bit polynomial
• The General Purpose Cyclic Redundancy Check (GPCRC) module comes in addition to the radio CRC
• Communication interfaces
• 3 Universal Synchronous/Asynchronous Receiver/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• Triple buffered full/half-duplex operation
• Hardware flow control
• 4-16 data bits
• 1 Low Energy UART
• Autonomous operation with DMA in Deep Sleep Mode
• 2 I2C Interface with SMBus support
• Address recognition in Stop Mode
• Timers/Counters
• 2 16-bit Timer/Counter
• 3 or 4 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 1 32-bit Timer/Counter
• 3 or 4 Compare/Capture/PWM channels
• Dead-Time Insertion on WTIMER0
• 16-bit Low Energy Timer
• 32-bit Ultra Low Energy Timer/Counter (CRYOTIMER) for periodic wake-up from any Energy Mode
• 32-bit Real-Time Counter and Calendar
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•

•
•

• 16+16+32 bit Protocol Timer
• 16-bit Pulse Counter
• Asynchronous pulse counting/quadrature decoding
• 2 Watchdog Timers with dedicated RC oscillator
Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• All APORT input channels available
• On-chip temperature sensor
• Single ended or differential operation
• Conversion tailgating for predictable latency
• 12-bit 500 ksps Digital to Analog Converter
• 2 single ended channels/1 differential channel
• Up to 3 Operational Amplifiers
• Supports rail-to-rail inputs and outputs
• Programmable gain
• Current Digital to Analog Converter
• Source or sink a configurable constant current
• 2 Analog Comparator
• Programmable speed/current
• Capacitive Sense Module
• Supports multi-channel scan and multi-channel gang conversions
• Low power, fast response times
• Analog Port
Low-energy sensor interface
• Autonomous sensor monitoring in deep sleep mode
• Wide range of supported sensors, including LC sensors and capacitive touch switches
Ultra efficient Power-on Reset and Brown-Out Detector
Debug Interface
• 4-pin Joint Test Action Group (JTAG) interface
• 2-pin serial-wire debug (SWD) interface
• Embedded Trace Macrocell (ETM)

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2.4 Oscillators and Clocks
EFR32xG13 Wireless Gecko has six different oscillators integrated, as shown in Table 2.1 EFR32xG13 Wireless Gecko Oscillators on
page 9.
Table 2.1. EFR32xG13 Wireless Gecko Oscillators
Oscillator

Frequency

Optional?

External
components

Description

HFXO

38 MHz - 40 MHz

Crystal

High accuracy, low jitter high frequency crystal oscillator. Tunable crystal loading capacitors are fully integrated. The HFXO
is required for all types of RF communication to be active.

HFRCO

1 MHz - 38 MHz

Medium accuracy RC oscillator, typically used for timing during startup of the HFXO and as a clock source as long as no
RF communication is active.

AUXHFRCO

1 MHz - 38 MHz

Medium accuracy RC oscillator, typically used as alternative
clock source for Analog to Digital Converter or Debug Trace.

PLFRCO

32.768 kHz

Self-Calibrating RC oscillator, typically used for RTCC and
BLE sleep timing.

LFRCO

32768 Hz

Medium accuracy frequency reference typically used for medium accuracy RTCC timing.

LFXO

32768 Hz

Yes

Crystal

High accuracy frequency reference typically used for high accuracy RTCC timing. Tunable crystal loading capacitors are
fully integrated.

ULFRCO

1000 Hz

Ultra low frequency oscillator typically used for the watchdog
timer.

The RC oscillators can be calibrated against either of the crystal oscillators in order to compensate for temperature and voltage supply
variations. Hardware support is included to measure the frequency of various oscillators against each other. The PLFRCO oscillator
automatically recalibrates itself against an available HFXO clock for highest precision.
Oscillator and clock management is available through the Clock Management Unit (CMU), see section 12. CMU - Clock Management
Unit for details.
2.5 RF Frequency Synthesizer
The Fractional-N RF Frequency Synthesizer (SYNTH) provides a low phase noise LO signal to be used in both receive and transmit
modes.
The capabilities of the SYNTH include:
•
•
•
•

High performance, low phase noise
Fast frequency settling
Fast and fully automated calibration
Sub 100 Hz frequency resolution across the supported frequency bands

2.6 Modulation Modes
EFR32xG13 Wireless Gecko supports a wide range of modulation modes in transmit and receive:
•
•
•
•
•
•
•

2-FSK, 2-GFSK, 4-FSK, 4-GFSK, MSK, GMSK, O-QPSK with half-sine shaping, ASK / OOK, DBPSK TX
NRZ or Manchester support
UART mode over air for legacy protocols
Data rates ranging from 600 bps up to 2 Mbps
Configurable frequency deviation
Configurable Direct Sequence Spread Spectrum (DSSS), with spread sequences up to 32 chips encoding up to 4 information bits
Configurable 4-FSK symbol encoding

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System Overview
2.7 Transmit Mode
In transmit mode EFR32xG13 Wireless Gecko performs the following functionality:
•
•
•
•
•
•

Automatic PA power ramping during the start and end of a frame transmit
Programmable output power
Optional preamble and synchronization word insertion
Accurate transmit frame timing to support time synchronized radio protocols
Optional Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) hardware support
Integrated transmit test modes, as described in 2.17 RF Test Modes

2.8 Receive Mode
In receive mode EFR32xG13 Wireless Gecko performs the following functionality:
• A single-ended (2.4 GHz) or differential (Sub-GHz) LNA amplifies the input RF signal. The amplified signal is then mixed to a low-IF
signal through the quadrature down-coversion mixer. Further signal filtering is performed before conversion to a digital signal
through the I/Q ADC.
• Digitally configurable receiver bandwidth from 100 Hz to 2.5 MHz
• Timing recovery on received data, including simultaneous support for two different frame synchronization words
• Automatic frequency offset compensation, to compensate for carrier frequency offset between the transmitter and receiver
• Support for a wide range of modulation formats as described in section 2.6 Modulation Modes
2.9 Data Buffering
EFR32xG13 Wireless Gecko supports buffered transmit and receive modes through its buffer controller (BUFC), with four individually
configurable buffers. The BUFC uses the system RAM as storage, and each buffer can be individually configured with parameters such
as:
•
•
•
•

Buffer size
Buffer interrupt thresholds
Buffer RAM location
Overflow and underflow detection

In receive mode, data following frame synchronization is moved directly from the demodulator to the buffer storage.
In transmit mode, data following the inserted preamble and synchronization word is moved directly from the buffer storage to the modulator.
2.10 Unbuffered Data Transfer
For most system designs it is recommended to use the data buffering within EFR32xG13 Wireless Gecko to provide a convenient user
interface.
In cases where data buffering within EFR32xG13 Wireless Gecko is not desired, it is possible to set up direct unbuffered data transfers
using a single-pin or two-pin interface on EFR32xG13 Wireless Gecko. A bit clock output is provided on the Serial Clock (SC) output
pin, and a serial bitstream is provided to EFR32xG13 Wireless Gecko in a transmit mode and from EFR32xG13 Wireless Gecko in a
receive mode.
In unbuffered data transfer modes the hardware support provided by EFR32xG13 Wireless Gecko to perform preamble and frame synchronization insertion in transmit mode and detection in receive mode can still optionally be used.

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System Overview
2.11 Frame Format Support
EFR32xG13 Wireless Gecko has an extensive support for frame handling in transmit and receive modes, which allows effective handling of even advanced protocols. The support includes:
• Preamble and frame synchronization inserted into transmitted frames
• Full frame synchronization of received frames
• Simple address matching of received frames in hardware, further configurable address and frame filtering supported through sequencer
• Support for variable length frames
• Automated CRC calculation and verification
• Configurable bit ordering, with the most or least significant bit transmitted and received first
The frame format support is controlled by the Frame Controller (FRC).
2.12 Hardware CRC Support
EFR32xG13 Wireless Gecko supports a configurable CRC generation in transmit and verification in receive mode:
•
•
•
•
•
•

8, 16, 24 or 32 bit CRC value
Configurable polynomial and initialization value
Optional inversion of CRC value over air
Configurable CRC byte ordering
Support for multiple CRC values calculated and verified per transmitted or received frame
The CRC module is typically controlled by the Frame Controller (FRC) for in-line operations in transmit and receive modes. Alternatively, the CRC module may be accessed directly from software to calculate and verify CRC data.

2.13 Convolutional Encoding / Decoding
EFR32xG13 Wireless Gecko includes hardware support for convolutional encoding and decoding, for forward error correction (FEC).
This feature is performed by the Frame Controller (FRC) module:
•
•
•
•

Constraint length configurable up to 7, for the highest robustness
Configurable puncturing, to achieve rates between 1/2 rate and full rate
Configurable soft decision or hard decision decoding
Convolutional coding may be used together with the symbol interleaver to improve robustness against burst errors

2.14 Binary Block Encoding / Decoding
EFR32xG13 Wireless Gecko includes hardware support for binary block encoding and decoding, both performed real-time in the the
transmit and receive path. This is performed in the Frame Controller (FRC) module:
The block coding works on blocks of up to 16 bits of data and adds parity bits to be capable of single or multiple bit corrections by the
receiver.
• One or more parity bits can be added and verified
• Bit error correction
• Lookup-codes can be used to implement virtually any block coding scheme

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System Overview
2.15 Data Encryption and Authentication
EFR32xG13 Wireless Gecko has hardware support for AES encryption, decryption and authentication modes. These security operations can be performed on data in RAM or any data buffer, without further CPU intervention. The key size is 128 bits.
AES modes of operations directly supported by the EFR32xG13 Wireless Gecko hardware are listed in Table 2.2 AES modes of operation with hardware support on page 12. In addition to these modes, other modes can also be implemented by using combinations of
modes. For example, the CCM mode can be implemented using the CTR and CBC-MAC modes in combination.
Table 2.2. AES modes of operation with hardware support
AES Mode

Encryption / Decryption

Authentication

Comment

ECB

Yes

Electronic Code Book

CTR

Yes

Counter mode

CCM

Yes

Counter with CBC-MAC

CCM*

Yes

CCM with encryption-only and
integrity-only capabilities

GCM

Yes

Galois Counter Mode

CBC

Yes

Cipher Block Chaining

CBC-MAC

Yes

Cipher Block Chaining, Message Authentication Code

CMAC

Yes

Cipher-based MAC

CFB

Yes

Cipher Feedback

OFB

Yes

Output Feedback

The CRYPTO module can operate directly on data buffers provided by the BUFC module. It is also possible to provide data directly
from the embedded Cortex-M4 or via DMA.
A True Random Number Generator (TRNG) module is also included for additional security. The TRNG is a non-deterministic random
number generator based on a full hardware solution, and is suitable for cryptographic key generation.

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System Overview
2.16 Timers
EFR32xG13 Wireless Gecko includes multiple timers, as can be seen from Table 2.3 EFR32xG13 Wireless Gecko Timers Overview on
page 13.
Table 2.3. EFR32xG13 Wireless Gecko Timers Overview
Timer

Number of instances

Typical clock source

Overview

RTCC

1 (2)

Low frequency (LFXO or
LFRCO)

32 bit Real Time Counter and
Calendar, typically used to enable wakeup on compare match.
A second RTC module is used
by the radio software drivers for
accurately timing inactive periods in the radio communication
protocol.

PROTIMER

High frequency (HFXO or
HFRCO)

16+16+32 bit Protocol Timer,
typically used to accurately control detailed RF protocol timing
in transmit and receive modes.

TIMER

High frequency (HFXO or
HFRCO)

16 bit general purpose timer.

WTIMER

High frequency (HFXO or
HFRCO)

32 bit general purpose timer.

Systick timer

High frequency (HFXO or
HFRCO)

32 bit systick timer integrated in
the Cortex-M4. Typically used
as an Operating System timer.

WDOG

Low frequency (LFXO, LFRCO
or ULFRCO)

Watch dog timer. Once enabled,
this module must be periodically
accessed. If not, this is considered an error and the
EFR32xG13 Wireless Gecko is
reset in order to recover the
system.

LETIMER

Low frequency (LFXO, LFRCO
or ULFRCO)

Low energy general purpose
timer.

Advanced interconnect features allows synchronization between timers. This includes:
• Start / stop any high frequency timer synchronized with the RTCC
• Trigger RSM state transitions based on compare timer compare match, for instance to provide clock cycle accuracy on frame transmit timing
2.17 RF Test Modes
EFR32xG13 Wireless Gecko supports a wide range of RF test modes typically used for characterization and regulation compliance
testing, including:
•
•
•
•
•

Unmodulated carrier transmit
Modulated carrier transmit, with internal configurable pseudo random data generator
Continuous data reception for Bit Error Rate (BER) measurements
Storing of raw receiver data to RAM
Transmit of raw frequency data from RAM

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System Processor

3. System Processor
Quick Facts
What?
0 1 2 3

The industry leading Cortex-M4 processor from
ARM is the CPU in the EFR32xG13 Wireless Gecko
devices.
Why?
The ARM Cortex-M4 is designed for exceptionally
short response time, high code density, and high 32bit throughput while maintaining a strict cost and
power consumption budget.

CM4 Core
32-bit ALU
Hardware divider

Single cycle
32-bit multiplier

Control Logic

DSP extensions

Floating-Point Unit

Thumb & Thumb-2
Decode

Instruction Interface

Data Interface

NVIC Interface

Memory Protection Unit

How?
Combined with the ultra low energy peripherals
available in EFR32xG13 Wireless Gecko devices,
the Cortex-M4 processor's Harvard architecture, 3
stage pipeline, single cycle instructions, Thumb-2 instruction set support, and fast interrupt handling
make it perfect for 8-bit, 16-bit, and 32-bit applications.

3.1 Introduction
The ARM Cortex-M4 32-bit RISC processor provides outstanding computational performance and exceptional system response to interrupts while meeting low cost requirements and low power consumption.
The ARM Cortex-M4 implemented is revision r0p1.

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System Processor
3.2 Features
• Harvard architecture
• Separate data and program memory buses (No memory bottleneck as in a single bus system)
• 3-stage pipeline
• Thumb-2 instruction set
• Enhanced levels of performance, energy efficiency, and code density
• Single cycle multiply and hardware divide instructions
• 32-bit multiplication in a single cycle
• Signed and unsigned divide operations between 2 and 12 cycles
• Atomic bit manipulation with bit banding
• Direct access to single bits of data
• Two 1MB bit banding regions for memory and peripherals mapping to 32MB alias regions
• Atomic operation, cannot be interrupted by other bus activities
• 1.25 DMIPS/MHz
• Memory Protection Unit
• Up to 8 protected memory regions
• 24 bits System Tick Timer for Real Time OS
• Excellent 32-bit migration choice for 8/16 bit architecture based designs
• Simplified stack-based programmer's model is compatible with traditional ARM architecture and retains the programming simplicity of legacy 8-bit and 16-bit architectures
• Alligned or unaligned data storage and access
• Contiguous storage of data requiring different byte lengths
• Data access in a single core access cycle
• Integrated power modes
• Sleep Now mode for immediate transfer to low power state
• Sleep on Exit mode for entry into low power state after the servicing of an interrupt
• Ability to extend power savings to other system components
• Optimized for low latency, nested interrupts
3.3 Functional Description
For a full functional description of the ARM Cortex-M4 implementation in the EFR32xG13 Wireless Gecko family, the reader is referred
to the ARM Cortex-M4 documentation.

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System Processor
3.3.1 Interrupt Operation

Module

Cortex-M NVIC
IFS[n]

IFC[n]

IEN[n]
SETENA[n]/CLRENA[n]
Active interrupt

Interrupt
condition

set

clear

IF[n]

IRQ
set

clear

Interrupt
request

SETPEND[n]/CLRPEND[n]
Software generated interrupt

Figure 3.1. Interrupt Operation
The interrupt request (IRQ) lines are connected to the Cortex-M4. Each of these lines (shown in Table 3.1 Interrupt Request Lines (IRQ)
on page 17) is connected to one or more interrupt flags in one or more modules. The interrupt flags are set by hardware on an interrupt condition. It is also possible to set/clear the interrupt flags through the IFS/IFC registers. Each interrupt flag is then qualified with its
own interrupt enable bit (IEN register), before being OR'ed with the other interrupt flags to generate the IRQ. A high IRQ line will set the
corresponding pending bit (can also be set/cleared with the SETPEND/CLRPEND bits in ISPR0/ICPR0) in the Cortex-M4 NVIC. The
pending bit is then qualified with an enable bit (set/cleared with SETENA/CLRENA bits in ISER0/ICER0) before generating an interrupt
request to the core. Figure 3.1 Interrupt Operation on page 16 illustrates the interrupt system. For more information on how the interrupts are handled inside the Cortex-M4, the reader is referred to the ARM Cortex-M4 Technical Reference Manual.
3.3.1.1 Avoiding Extraneous Interrupts
There can be latencies in the system such that clearing an interrupt flag could take longer than leaving an Interrupt Service Routine
(ISR). This can lead to the ISR being re-entered as the interrupt flag has yet to clear immediately after leaving the ISR. To avoid this,
when clearing an interrupt flag at the end of an ISR, the user should execute ARM's Data Synchronization Barrier (DSB) instruction.
Another approach is to clear the interrupt flag immediately after identifying the interrupt source and then service the interrupt as shown
in the pseudo-code below. The ISR typically is sufficiently long to more than cover the few cycles it may take to clear the interrupt status, and also allows the status to be checked for further interrupts before exiting the ISR.

irqXServiceRoutine() {
do {
clearIrqXStatus();
serviceIrqX();
} while(irqXStatusIsActive());
}

3.3.1.2 IFC Read-clear Operation
In addition to the normal interrupt setting and clearing operations via the IFS/IFC registers, there is an additional atomic Read-clear
operation that can be enabled by setting IFCREADCLEAR=1 in the MSC_CTRL register. When enabled, reads of peripheral IFC registers will return the interrupt vector (mirroring the IF register), while at the same time clearing whichever interrupt flags are set. This operation is functionally equivalent to reading the IF register and then writing the result immediately back to the IFC register.

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System Processor
3.3.2 Interrupt Request Lines (IRQ)
Table 3.1. Interrupt Request Lines (IRQ)
IRQ #

Source(s)

EMU

WDOG0

WDOG1

LDMA

GPIO_EVEN

TIMER0

USART0_RX

USART0_TX

ACMP0
ACMP1

ADC0

IDAC0

I2C0

GPIO_ODD

TIMER1

USART1_RX

USART1_TX

LEUART0

PCNT0

CMU

MSC

CRYPTO0

LETIMER0

RTCC

CRYOTIMER

FPUEH

SMU

WTIMER0

USART2_RX

USART2_TX

I2C1

VDAC0

CSEN

LESENSE

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System Processor
IRQ #

Source(s)

CRYPTO1

TRNG0

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Memory and Bus System

4. Memory and Bus System
Quick Facts
What?
0 1 2 3

A low latency memory system including low energy
Flash and RAM with data retention which makes the
energy modes attractive.
Why?

Flash
ARM Cortex-M

How?

RAM
Radio
DMA Controller
Peripherals

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RAM retention reduces the need for storing data in
Flash and enables frequent use of the ultra low energy modes EM2 Deep Sleep and EM3 Stop.

Low energy and non-volatile Flash memory stores
program and application data in all energy modes
and can easily be reprogrammed in system. Low
leakage RAM with data retention in EM0 Active to
EM3 Stop removes the data restore time penalty,
and the DMA ensures fast autonomous transfers
with predictable response time.

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Memory and Bus System
4.1 Introduction
The EFR32xG13 Wireless Gecko contains an AMBA AHB Bus system to allow bus masters to access the memory mapped address
space. A multilayer AHB bus matrix connects the 5 master bus interfaces to the AHB slaves (Figure 4.1 EFR32xG13 Wireless Gecko
Bus System on page 20). The bus matrix allows several AHB slaves to be accessed simultaneously. An AMBA APB interface is used
for the peripherals, which are accessed through an AHB-to-APB bridge connected to the AHB bus matrix. The 5 AHB bus masters are:
• Cortex-M4 ICode: Used for instruction fetches from Code memory (valid address range: 0x00000000 - 0x1FFFFFFF)
• Cortex-M4 DCode: Used for debug and data access to Code memory (valid address range: 0x00000000 - 0x1FFFFFFF)
• Cortex-M4 System: Used for data and debug access to system space. It can access entire memory space except Code memory
(valid address range: 0x20000000 - 0xFFFFFFFF)
• DMA: Can access the entire memory space except the internal core memory region and the DMEM code region
• Sequencer Code: Used for instruction fetches and data accesses. Instruction fetches still come from data memory. (valid address
range: 0x00000000 - 0x0FFFFFFF, 0x20000000 - 0x3FFFFFFF)
• Sequencer System: Can access entire memory space except internal core memory region and RAM code space (valid address
range: 0x00000000 - 0x0FFFFFFF, 0x20000000 - 0xDFFFFFFF)
• BUFC: Can access general purpose SRAM (valid address range: 0x20000000 - 0x20FFFFFF)
• FRC: Can access general purpose SRAM (valid address range: 0x20000000 - 0x20FFFFFF)

Cortex-M

ICode
DCode

Sequencer

AHB Multilayer
Bus Matrix

Flash

System

RAM0

Code

RAMn

System

BUFC

SEQ_RAM
CRYPTO

FRC
AHB/APB
Bridge

DMA

Peripheral 0

Peripheral n

Figure 4.1. EFR32xG13 Wireless Gecko Bus System

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Memory and Bus System
4.2 Functional Description
The memory segments are mapped together with the internal segments of the Cortex-M4 into the system memory map shown by Figure 4.2 System Address Space with Core and Code Space Listing on page 21.

Figure 4.2. System Address Space with Core and Code Space Listing
Additionally, the peripheral address map is detailed by Figure 4.3 System Address Space with Peripheral Listing on page 22.

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Memory and Bus System

Figure 4.3. System Address Space with Peripheral Listing
The embedded SRAM is located at address 0x20000000 in the memory map of the EFR32xG13 Wireless Gecko. When running code
located in SRAM starting at this address, the Cortex-M4 uses the System bus interface to fetch instructions. This results in reduced
performance as the Cortex-M4 accesses stack, other data in SRAM and peripherals using the System bus interface. To be able to run
code from SRAM efficiently, the SRAM is also mapped in the code space at address 0x10000000.
When running code from this space, the Cortex-M4 fetches instructions through the I/D-Code bus interface, leaving the System bus
interface for data access.
The SRAM mapped into the code space can however only be accessed by the CPU and not any other bus masters, e.g. DMA. See
4.5 SRAM for more detailed info on the system SRAM.
The Sequencer RAM is used by the Sequencer for both instructions and data. This RAM is also available for general use by most AHB
masters.

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Memory and Bus System
4.2.1 Peripheral non-word access behavior
When writing to peripheral registers, all accesses are treated as 32-bit accesses. This means that writes to a register need to be large
enough to cover all bits of register, otherwise, any uncovered bits may become corrupted from the partial-word transfer. Thus, the safest
practice is to always do 32-bit writes to peripheral registers.
When reading, there is generally no issue with partial word accesses, however, note that any read action (e.g. FIFO popping) will be
triggered regardless of whether the actual FIFO bit-field was included in the transfer size.
Note: The implementation of bit-banding in the core is such that bit-band accesses forward the transfer size info into the actual bus
transfer size, so the same restrictions apply to bit-band accesses as apply to normal read/write accesses.

4.2.2 Bit-banding
The SRAM bit-band alias and peripheral bit-band alias regions are located at 0x22000000 and 0x42000000 respectively. Read and
write operations to these regions are converted into masked single-bit reads and atomic single-bit writes to the embedded SRAM and
peripherals of the EFR32xG13 Wireless Gecko.
Note: Bit-banding is only available through the CPU. No other AHB masters (e.g. DMA) can perform Bit-banding operations.
Using a standard approach to modify a single register or SRAM bit in the aliased regions, would require software to read the value of
the byte, half-word or word containing the bit, modify the bit, and then write the byte, half-word or word back to the register or SRAM
address. Using bit-banding, this can be done in a single operation, consuming only two bus cycles. As read-writeback, bit-masking and
bit-shift operations are not necessary in software, code size is reduced and execution speed improved.
The bit-band regions allow each bit in the SRAM and Peripheral areas of the memory map to be addressed. To set or clear a bit in the
embedded SRAM, write a 1 or a 0 to the following address:

bit_address = 0x22000000 + (address – 0x20000000) ∙ 32 + bit ∙ 4
where address is the address of the 32-bit word containing the bit to modify, and bit is the index of the bit in the 32-bit word.
To modify a bit in the Peripheral area, use the following address:

bit_address = 0x42000000 + (address – 0x40000000) ∙ 32 + bit ∙ 4

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Memory and Bus System
4.2.3 Peripheral Bit Set and Clear
The EFR32xG13 Wireless Gecko supports bit set and bit clear access to all peripherals except those listed in Table 4.1 Peripherals that
Do Not Support Bit Set and Bit Clear on page 24. The bit set and bit clear functionality (also called Bit Access) enables modification of
bit fields (single bit or multiple bit wide) without the need to perform a read-modify-write (though it is functionally equivalent). Also, the
operation is contained within a single bus access (for HF peripherals), unlike the Bit-banding operation described in section 4.2.2 Bitbanding which consumes two bus accesses per operation. All AHB masters can utilize this feature.
The bit clear aliasing region starts at 0x44000000 and the bit set aliasing region starts at 0x46000000. Thus, to apply a bit set or clear
operation, write the bit set or clear mask to the following addresses:

bit_clear_address = address + 0x04000000
bit_set_address = address + 0x06000000
For bit set operations, bit locations that are 1 in the bit mask will be set in the destination register:

register = (register OR mask)
For bit clear operations, bit locations that are 1 in the bit mask will be cleared in the destination register:

register = (register AND (NOT mask))
Note: It is possible to combine bit clear and bit set operations in order to arbitrarily modify multi-bit register fields, without affecting other
fields in the same register. In this case, care should be taken to ensure that the field does not have intermediate values that can lead to
erroneous behavior. For example, if bit clear and bit set operations are used to change an analog tuning register field from 25 to 26, the
field would initially take on a value of zero. If the analog module is active at the time, this could lead to undesired behavior.
The peripherals listed in Table 4.1 Peripherals that Do Not Support Bit Set and Bit Clear on page 24 do not support Bit Access for any
registers. All other peripherals do support Bit Access, however, there may be cases of certain registers that do not support it. Such
registers have a note regarding this lack of support.
Table 4.1. Peripherals that Do Not Support Bit Set and Bit Clear
Module
EMU
RMU
CRYOTIMER
TRNG0

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Memory and Bus System
4.2.4 Peripherals
The peripherals are mapped into the peripheral memory segment, each with a fixed size address range according to Table 4.2 Peripherals on page 25, Table 4.3 Low Energy Peripherals on page 25 , and Table 4.4 Core Peripherals on page 26.
Table 4.2. Peripherals
Address Range

Module Name

0x400E6000 - 0x400E6400

PRS

0x40022000 - 0x40022400

SMU

0x4001F000 - 0x4001F400

CSEN

0x4001E000 - 0x4001E400

CRYOTIMER

0x4001D000 - 0x4001D400

TRNG0

0x4001C000 - 0x4001C400

GPCRC

0x4001A000 - 0x4001A400

WTIMER0

0x40018400 - 0x40018800

TIMER1

0x40018000 - 0x40018400

TIMER0

0x40010800 - 0x40010C00

USART2

0x40010400 - 0x40010800

USART1

0x40010000 - 0x40010400

USART0

0x4000C400 - 0x4000C800

I2C1

0x4000C000 - 0x4000C400

I2C0

0x4000A000 - 0x4000B000

GPIO

0x40008000 - 0x40008400

VDAC0

0x40006000 - 0x40006400

IDAC0

0x40002000 - 0x40002400

ADC0

0x40000400 - 0x40000800

ACMP1

0x40000000 - 0x40000400

ACMP0
Table 4.3. Low Energy Peripherals
Address Range

Module Name

0x40055000 - 0x40055400

LESENSE

0x40052400 - 0x40052800

WDOG1

0x40052000 - 0x40052400

WDOG0

0x4004E000 - 0x4004E400

PCNT0

0x4004A000 - 0x4004A400

LEUART0

0x40046000 - 0x40046400

LETIMER0

0x40042000 - 0x40042400

RTCC

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Memory and Bus System
Table 4.4. Core Peripherals
Address Range

Module Name

0xE0041000 - 0xE0081000

ETM

0xE0000000 - 0xE0040000

CM4

0x400F0400 - 0x400F0800

CRYPTO1

0x400F0000 - 0x400F0400

CRYPTO0

0x400E2000 - 0x400E3000

LDMA

0x400E1000 - 0x400E1400

FPUEH

0x400E0000 - 0x400E0800

MSC

4.2.5 Bus Matrix
The Bus Matrix connects the memory segments to the bus masters as detailed in 4.1 Introduction.
4.2.5.1 Arbitration
The Bus Matrix uses a round-robin arbitration algorithm which enables high throughput and low latency, while starvation of simultaneous accesses to the same bus slave are eliminated. Round-robin does not assign a fixed priority to each bus master. The arbiter does
not insert any bus wait-states during peak interaction. However, one wait state is inserted for master accesses occurring after a prolonged inactive time. This wait state allows for increased power efficiency during master idle time.
4.2.5.2 Peripheral access Performance
The Bus Matrix is a multi-layer energy optimized AMBA AHB compliant bus with an internal bandwidth of 5x a single AHB interface.
The Cortex-M4, DMA Controller, and peripherals (not peripherals in the low frequency clock domain) run on clocks which can be prescaled separately. Clocks and prescaling are described in more detail in 12. CMU - Clock Management Unit . This section describes the
expected bus wait states for a peripheral based on its frequency relative to the HFCLK frequency. For this discussion, PERCLK refers
to a selected peripheral's clock frequency, which is some integer division of the HFCLK frequency.
Another factor that effects the cycle latency of peripheral accesses is the Peripheral Access Wait Mode (WAITMODE in MSC_CTRL)
configuration, which is present in some parts in the EFR32 series. For instance, when set to WS0, a higher throughput (in terms of
HFCLK cycles) is possible than with a higher wait state setting. However, this family of parts does not have configurable wait states.
Instead, refer to the access performance information for WS0 for this device family.

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Memory and Bus System
4.2.5.2.1 WS0 mode
In general, when accessing a peripheral, the latency in number of HFCLK cycles, not including master arbitration, is given by:

Nbus cycles = Nslave cycles ∙ fHFCLK/fPERCLK, best-case write accesses
Nbus cycles = Nslave cycles ∙ fHFCLK/fPERCLK + 1, best-case read accesses
Nbus cycles = (Nslave cycles + 1) ∙ fHFCLK/fPERCLK - 1, worst-case write accesses
Nbus cycles = (Nslave cycles + 1) ∙ fHFCLK/fPERCLK, worst-case read accesses
where Nslave cycles is the throughput of the slave's bus interface in number of PERCLK cycles per transfer, including any wait cycles
introduced by the slave.
Figure 4.4. Bus Access Latency (General Case)
Note that a latency of 1 cycle corresponds to 0 wait states.
Additionally, for back-to-back accesses to the same peripheral, the throughput in number of cycles per transfer is given by:

Nbus cycles = Nslave cycles ∙ fHFCLK/fPERCLK, write accesses
Nbus cycles = (Nslave cycles + 1) ∙ fHFCLK/fPERCLK, read accesses
Figure 4.5. Bus Access Throughput (Back-to-Back Transfers)
Lastly, in the highest performing case, where PERCLK equals HFCLK and the slave does not introduce any additional wait states, the
access latency in number of cycles is given by:

Nbus cycles = 1, write accesses
Nbus cycles = 2, read accesses
Figure 4.6. Bus Access Latency (Max Performance)

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Memory and Bus System
4.2.5.2.2 WS1 mode
In general, when accessing a peripheral, the latency in number of HFCLK cycles, not including master arbitration, is given by:

Nbus cycles = Nslave cycles ∙ fHFCLK/fPERCLK + 2, best-case write accesses
Nbus cycles = Nslave cycles ∙ fHFCLK/fPERCLK + 1, best-case read accesses
Nbus cycles = (Nslave cycles + 1) ∙ fHFCLK/fPERCLK + 1, worst-case write accesses
Nbus cycles = (Nslave cycles + 1) ∙ fHFCLK/fPERCLK, worst-case read accesses
where Nslave cycles is the throughput of the slave's bus interface in number of PERCLK cycles per transfer, including any wait cycles
introduced by the slave.
Figure 4.7. Bus Access Latency (General Case)
Note that a latency of 1 cycle corresponds to 0 wait states.
Additionally, for back-to-back accesses to the same peripheral, the throughput in number of cycles per transfer is given by:

Nbus cycles = max{fHFCLK/fPERCLK, 2} + Nslave cycles ∙ fHFCLK/fPERCLK, write accesses
Nbus cycles = (Nslave cycles + 1) ∙ fHFCLK/fPERCLK, read accesses
Figure 4.8. Bus Access Throughput (Back-to-Back Transfers)
Lastly, in the highest performing case, where PERCLK equals HFCLK and the slave does not introduce any additional wait states, the
access latency in number of cycles is given by:

Nbus cycles = 3, write accesses
Nbus cycles = 2, read accesses
Figure 4.9. Bus Access Latency (Max Performance)

4.2.5.2.3 Core Access Latency
Note that the cycle counts in the equations above is in terms of the HFCLK. When the core is prescaled from the bus clock, the core will
see a reduced number of latency cycles given by:

Ncore cycles = ceiling( Nbus cycles ∙ fHFCORECLK/fHFCLK )
where master arbitration is not included.
Figure 4.10. Core Access Latency

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Memory and Bus System
4.2.5.3 Bus Faults
System accesses from the core can receive a bus fault in the following condition(s):
• The core attempts to access an address that is not assigned to any peripheral or other system device. These faults can be enabled
or disabled by setting the ADDRFAULTEN bit appropriately in MSC_CTRL.
• The core attempts to access a peripheral or system device that has its clock disabled. These faults can be enabled or disabled by
setting the CLKDISFAULTEN bit appropriately in MSC_CTRL.
• The bus times out during an access. For example, this could happen while trying to synchronize volatile read data during an LE
peripheral access. See 12.3.1.1 HFCLK - High Frequency Clock. These faults can be enabled or disabled by setting the TIMEOUTFAULTEN bit appropriately in MSC_CTRL.
In addition to any condition-specific bus fault control bits, the bus fault interrupt itself can be enabled or disabled in the same way as all
other internal core interrupts.
4.3 Access to Low Energy Peripherals (Asynchronous Registers)
The Low Energy Peripherals are capable of running when the high frequency oscillator and core system is powered off, i.e. in energy
mode EM2 Deep Sleep and in some cases also EM3 Stop. This enables the peripherals to perform tasks while the system energy consumption is minimal.
The Low Energy Peripherals are listed in Table 4.3 Low Energy Peripherals on page 25.
All Low Energy Peripherals are memory mapped, with automatic data synchronization. Because the Low Energy Peripherals are running on clocks asynchronous to the high frequency system clock, there are some constraints on how register accesses are performed,
as described in the following sections.
4.3.1 Writing
Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into the Low Energy clock domain to
maintain data consistency and predictable operation. There are two different synchronization mechanisms on the EFR32, immediate
synchronization, and delayed synchronization. Immediate synchronization is available for the RTCC, LESENSE and LETIMER, and results in an immediate update of the target registers. Delayed synchronization is used for the remaining Low Energy Peripherals, and for
these peripherals, a write operation requires 3 positive edges of the clock on the Low Energy Peripheral being accessed. Registers
requiring synchronization are marked "Async Reg" in their description header.
Note: On the Gecko series of devices, all LE peripherals are subject to delayed synchronization.

High Frequency Clock Domain

Low Frequency Clock

Synchronizer 0

Synchronizer 1
.
.
.
Synchronizer n

High Frequency Clock
Write request 0
Write request 1

Write request n

Freeze

Low Frequency Clock Domain

Synchronization Done
Write request [0:n]
Set 0

Syncbusy Register 0

Clear 0

Set 1

Syncbusy Register 1
.
.
.
Syncbusy Register n

Clear 1

Set n

Clear n

Figure 4.11. Write operation to Low Energy Peripherals

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Memory and Bus System
4.3.1.1 Delayed Synchronization
After writing data to a register which value is to be synchronized into the Low Energy Peripheral using delayed synchronization, a corresponding busy flag in the _SYNCBUSY register (e.g. LETIMER_SYNCBUSY) is set. This flag is set as long as synchronization is in progress and is cleared upon completion.
Note: Subsequent writes to the same register before the corresponding busy flag is cleared is not supported. Write before the busy flag
is cleared may result in undefined behavior. In general the SYNCBUSY register only needs to be observed if there is a risk of multiple
write access to a register (which must be prevented). It is not required to wait until the relevant flag in the SYNCBUSY register is
cleared after writing a register. E.g., EM2 Deep Sleep can be entered directly after writing a register.
See Figure 4.12 Write operation to Low Energy Peripherals on page 30 for an overview of the writing mechanism operation.

High Frequency Clock Domain

Write request 1

Write request n

Low Frequency Clock Domain
Low Frequency Clock

Low Frequency Clock

Synchronizer 0

Synchronizer 1
.
.
.
Synchronizer n

High Frequency Clock
Write request 0

Freeze

Synchronization Done
Write request [0:n]
Set 0

Syncbusy Register 0

Clear 0

Set 1

Syncbusy Register 1
.
.
.
Syncbusy Register n

Clear 1

Set n

Clear n

Figure 4.12. Write operation to Low Energy Peripherals

4.3.1.2 Immediate Synchronization
In contrast to the peripherals with delayed synchronization, peripherals with immediate synchronization do not experience a delay from
a value is written to it takes effect in the peripheral. They are updated immediately on the peripheral write access. If such a write is done
close to an edge on the clock of the peripheral, the write is delayed to after the clock edge. This will introduce wait-states on the peripheral access.
Peripherals with immediate synchronization each have a SYNCBUSY register. Commands written to a peripheral with immediate synchronization are not executed before the first peripheral clock after the write. In this period, the SYNCBUSY flag for the command register is set, indicating that the command has not yet been performed. Secondly, to maintain compatibility with the Gecko series, the rest
of the SYNCBUSY registers are also present, but these are always 0, indicating that register writes are always safe.
Note: If compatibility with the Gecko series is a requirement for a given application, the rules that apply to delayed synchronization with
respect to SYNCBUSY should also be followed for the peripherals that support immediate synchronization.

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Memory and Bus System
4.3.2 Reading
When reading from a Low Energy Peripheral, the data read is synchronized regardless if it originates in the Low Energy clock domain
or High Frequency clock domain. See Figure 4.13 Read operation from Low Energy Peripherals on page 31 for an overview of the
reading operation.
Note: Writing a register and then immediately reading the new value of the register may give the impression that the write operation is
complete. This may not be the case. Please refer to the SYNCBUSY register for correct status of the write operation to the Low Energy
Peripheral.

High Frequency Clock Domain
Freeze

Low Frequency Clock Domain
Low Frequency Clock

Low Frequency Clock

Synchronizer 0

Synchronizer 1
.
.
.
Synchronizer n

High Frequency Clock

HW Status Register 0
Read
Synchronizer

HW Status Register 1
.
.
.
HW Status Register m

Low Energy
Peripheral
Main
Function

Read Data

Figure 4.13. Read operation from Low Energy Peripherals

4.3.3 FREEZE Register
In all Low Energy Peripheral with delayed synchronization there is a _FREEZE register (e.g. RTCC_FREEZE). The
register contains a bit named REGFREEZE. If precise control of the synchronization process is required, this bit may be utilized. When
REGFREEZE is set, the synchronization process is halted allowing the software to write multiple Low Energy registers before starting
the synchronization process, thus providing precise control of the module update process. The synchronization process is started by
clearing the REGFREEZE bit.
Note: The FREEZE register is also present on peripherals with immediate synchronization, but there it has no effect

4.4 Flash
The Flash retains data in any state and typically stores the application code, special user data and security information. The Flash
memory is typically programmed through the debug interface, but can also be erased and written to from software.
• Up to 512 KB of memory
• Page size of 2 KB (minimum erase unit)
• Minimum 10K erase cycles endurance
• Greater than 10 years data retention at 85°C
• Lock-bits for memory protection
• Data retention in any state

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Memory and Bus System
4.5 SRAM
The primary task of the SRAM memory is to store application data. Additionally, it is possible to execute instructions from SRAM, and
the DMA may be set up to transfer data between the SRAM, Flash and peripherals.
• Up to 64 KB of memory
• Bit-band access support
• Set of RAM blocks may be powered down when not in use
• Data retention of the entire memory in EM0 Active to EM3 Stop
Note: The individual RAM sections may be smaller on some parts, however, the RAM AHB slaves maintain a contiguous address map.
For example, if RAM0 is half-size on a part, then RAM1 is relocated to begin immediately after RAM0's last address. Using the provided
software header files and linker scripts allows handling of this remapping in an autonomous manner.

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Memory and Bus System
4.6 DI Page Entry Map
The DI page contains production calibration data as well as device identification information. See the peripheral chapters for how each
calibration value is to be used with the associated peripheral.
The offset address is relative to the start address of the DI page.(see 8.3 Functional Description)
Offset

Name

Type

Description

0x000

CAL

CRC of DI-page and calibration temperature

0x020

EXTINFO

External Component description

0x028

EUI48L

EUI48 OUI and Unique identifier

0x02C

EUI48H

OUI

0x030

CUSTOMINFO

Custom information

0x034

MEMINFO

Flash page size and misc. chip information

0x040

UNIQUEL

Low 32 bits of device unique number

0x044

UNIQUEH

High 32 bits of device unique number

0x048

MSIZE

Flash and SRAM Memory size in kB

0x04C

PART

Part description

0x050

DEVINFOREV

Device information page revision

0x054

EMUTEMP

EMU Temperature Calibration Information

0x060

ADC0CAL0

ADC0 calibration register 0

0x064

ADC0CAL1

ADC0 calibration register 1

0x068

ADC0CAL2

ADC0 calibration register 2

0x06C

ADC0CAL3

ADC0 calibration register 3

0x080

HFRCOCAL0

HFRCO Calibration Register (4 MHz)

0x08C

HFRCOCAL3

HFRCO Calibration Register (7 MHz)

0x098

HFRCOCAL6

HFRCO Calibration Register (13 MHz)

0x09C

HFRCOCAL7

HFRCO Calibration Register (16 MHz)

0x0A0

HFRCOCAL8

HFRCO Calibration Register (19 MHz)

0x0A8

HFRCOCAL10

HFRCO Calibration Register (26 MHz)

0x0AC

HFRCOCAL11

HFRCO Calibration Register (32 MHz)

0x0B0

HFRCOCAL12

HFRCO Calibration Register (38 MHz)

0x0E0

AUXHFRCOCAL0

AUXHFRCO Calibration Register (4 MHz)

0x0EC

AUXHFRCOCAL3

AUXHFRCO Calibration Register (7 MHz)

0x0F8

AUXHFRCOCAL6

AUXHFRCO Calibration Register (13 MHz)

0x0FC

AUXHFRCOCAL7

AUXHFRCO Calibration Register (16 MHz)

0x100

AUXHFRCOCAL8

AUXHFRCO Calibration Register (19 MHz)

0x108

AUXHFRCOCAL10

AUXHFRCO Calibration Register (26 MHz)

0x10C

AUXHFRCOCAL11

AUXHFRCO Calibration Register (32 MHz)

0x110

AUXHFRCOCAL12

AUXHFRCO Calibration Register (38 MHz)

0x140

VMONCAL0

VMON Calibration Register 0

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Memory and Bus System
Offset

Name

Type

Description

0x144

VMONCAL1

VMON Calibration Register 1

0x148

VMONCAL2

VMON Calibration Register 2

0x158

IDAC0CAL0

IDAC0 Calibration Register 0

0x15C

IDAC0CAL1

IDAC0 Calibration Register 1

0x168

DCDCLNVCTRL0

DCDC Low-noise VREF Trim Register 0

0x16C

DCDCLPVCTRL0

DCDC Low-power VREF Trim Register 0

0x170

DCDCLPVCTRL1

DCDC Low-power VREF Trim Register 1

0x174

DCDCLPVCTRL2

DCDC Low-power VREF Trim Register 2

0x178

DCDCLPVCTRL3

DCDC Low-power VREF Trim Register 3

0x17C

DCDCLPCMPHYSSEL0 RO

DCDC LPCMPHYSSEL Trim Register 0

0x180

DCDCLPCMPHYSSEL1 RO

DCDC LPCMPHYSSEL Trim Register 1

0x184

VDAC0MAINCAL

VDAC0 Cals for Main Path

0x188

VDAC0ALTCAL

VDAC0 Cals for Alternate Path

0x18C

VDAC0CH1CAL

VDAC0 CH1 Error Cal

0x190

OPA0CAL0

OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1

0x194

OPA0CAL1

OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1

0x198

OPA0CAL2

OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1

0x19C

OPA0CAL3

OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1

0x1A0

OPA1CAL0

OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1

0x1A4

OPA1CAL1

OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1

0x1A8

OPA1CAL2

OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1

0x1AC

OPA1CAL3

OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1

0x1B0

OPA2CAL0

OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=1

0x1B4

OPA2CAL1

OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=1

0x1B8

OPA2CAL2

OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=1

0x1BC

OPA2CAL3

OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=1

0x1C0

CSENGAINCAL

Cap Sense Gain Adjustment

0x1D0

OPA0CAL4

OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0

0x1D4

OPA0CAL5

OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0

0x1D8

OPA0CAL6

OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0

0x1DC

OPA0CAL7

OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0

0x1E0

OPA1CAL4

OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0

0x1E4

OPA1CAL5

OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0

0x1E8

OPA1CAL6

OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0

0x1EC

OPA1CAL7

OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0

0x1F0

OPA2CAL4

OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=0

0x1F4

OPA2CAL5

OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=0

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Memory and Bus System
Offset

Name

Type

Description

0x1F8

OPA2CAL6

OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=0

0x1FC

OPA2CAL7

OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0

4.7 DI Page Entry Description
4.7.1 CAL - CRC of DI-page and calibration temperature

Name

Bit

Name

Access

31:24

Reserved

Reserved for future use

23:16

TEMP

Calibration temperature as an usigned int in DegC
(25 = 25DegC)

15:0

CRC

CRC of DI-page (CRC-16-CCITT)

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CRC

Access

TEMP RO

0x000

Bit Position
31

Offset

Description

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Memory and Bus System
4.7.2 EXTINFO - External Component description

Bit

Name

Access

31:24

Reserved

Reserved for future use

23:16

REV

MCM Revision

Value

Mode

Description

REV1

Revision 1

255

NONE

No external component present

CONNECTION

Connection protocal to external interface

Value

Mode

Description

SPI

SPI control interface

255

NONE

None

TYPE

15:8

7:0

TYPE

REV

Name

CONNECTION RO

Access

0x020

Bit Position
31

Offset

Description

External Component
Value

Mode

Description

IS25LQ040B

IS25LQ040B-JWLE1 512kB Serial Flash

AT25S041

AT25S041-DWFHT 512kB Serial Flash

255

NONE

None

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Memory and Bus System
4.7.3 EUI48L - EUI48 OUI and Unique identifier

OUI48L

Access

Name

UNIQUEID RO

0x028

Bit Position
31

Offset

Bit

Name

Access

Description

31:24

OUI48L

Lower Octet of EUI48 Organizationally Unique Identifier

23:0

UNIQUEID

Unique identifier

4.7.4 EUI48H - OUI

OUI48H RO

0x02C

Bit Position
31

Offset

Access
Name

Bit

Name

Access

Description

31:16

Reserved

Reserved for future use

15:0

OUI48H

Upper two Octets of EUI48 Organizationally Unique
Identifier

4.7.5 CUSTOMINFO - Custom information

PARTNO RO

0x030

Bit Position
31

Offset

Access

Name

Bit

Name

Access

Description

31:16

PARTNO

Custom part identifier as unsigned integer (e.g. 903)
65535 for standard product

15:0

Reserved

Reserved for future use

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Memory and Bus System
4.7.6 MEMINFO - Flash page size and misc. chip information

Bit

Name

Access

Description

31:24

FLASH_PAGE_SIZE

Flash page size in bytes coded as 2 ^ ((MEM_INFO_PAGE_SIZE + 10) & 0xFF). Ie. the value 0xFF
= 512 bytes.

23:16

PINCOUNT

Device pin count as unsigned integer (eg. 48)

15:8

PKGTYPE

Package Identifier as character

Value

Mode

Description

WLCSP

WLCSP package

BGA

BGA package

QFN

QFN package

QFP

QFP package

TEMPGRADE

Temperature Grade of product as unsigned integer enumeration

Value

Mode

Description

N40TO85

-40 to 85degC

N40TO125

-40 to 125degC

N40TO105

-40 to 105degC

N0TO70

0 to 70degC

7:0

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TEMPGRADE

PKGTYPE

Name

PINCOUNT

Access

FLASH_PAGE_SIZE RO

0x034

Bit Position
31

Offset

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Memory and Bus System
4.7.7 UNIQUEL - Low 32 bits of device unique number

UNIQUEL RO

0x040

Bit Position
31

Offset

Access

Name

Bit

Name

Access

Description

31:0

UNIQUEL

Low 32 bits of device unique number

4.7.8 UNIQUEH - High 32 bits of device unique number

UNIQUEH RO

0x044

Bit Position
31

Offset

Access

Name

Bit

Name

Access

Description

31:0

UNIQUEH

High 32 bits of device unique number

4.7.9 MSIZE - Flash and SRAM Memory size in kB

Name

FLASH RO

SRAM

Access

0x048

Bit Position
31

Offset

Bit

Name

Access

Description

31:16

SRAM

Ram size, kbyte count as unsigned integer (eg. 16)

15:0

FLASH

Flash size, kbyte count as unsigned integer (eg. 128)

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Memory and Bus System
4.7.10 PART - Part description

Bit

Name

Access

Description

31:24

PROD_REV

Production revision as unsigned integer

23:16

DEVICE_FAMILY

Device Family

Value

Mode

Description

EFR32MG1P

EFR32 Mighty Gecko Family Series 1 Device Config
1

EFR32MG1B

EFR32 Mighty Gecko Family Series 1 Device Config
1

EFR32MG1V

EFR32 Mighty Gecko Family Series 1 Device Config
1

EFR32BG1P

EFR32 Blue Gecko Family Series 1 Device Config 1

EFR32BG1B

EFR32 Blue Gecko Family Series 1 Device Config 1

EFR32BG1V

EFR32 Blue Gecko Family Series 1 Device Config 1

EFR32FG1P

EFR32 Flex Gecko Family Series 1 Device Config 1

EFR32FG1B

EFR32 Flex Gecko Family Series 1 Device Config 1

EFR32FG1V

EFR32 Flex Gecko Family Series 1 Device Config 1

EFR32MG12P EFR32 Mighty Gecko Family Series 1 Device Config
2

EFR32MG12B EFR32 Mighty Gecko Family Series 1 Device Config
2

EFR32MG12V EFR32 Mighty Gecko Family Series 1 Device Config
2

EFR32BG12P EFR32 Blue Gecko Family Series 1 Device Config 2

EFR32BG12B EFR32 Blue Gecko Family Series 1 Device Config 2

EFR32BG12V EFR32 Blue Gecko Family Series 1 Device Config 2

EFR32FG12P EFR32 Flex Gecko Family Series 1 Device Config 2

EFR32FG12B EFR32 Flex Gecko Family Series 1 Device Config 2

EFR32FG12V EFR32 Flex Gecko Family Series 1 Device Config 2

EFR32MG13P EFR32 Mighty Gecko Family Series 1 Device Config
3

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DEVICE_NUMBER RO

Name

DEVICE_FAMILY

PROD_REV

Access

0x04C

Bit Position
31

Offset

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Memory and Bus System
Bit

Name

Access

EFR32MG13B EFR32 Mighty Gecko Family Series 1 Device Config
3

EFR32MG13V EFR32 Mighty Gecko Family Series 1 Device Config
3

EFR32BG13P EFR32 Blue Gecko Family Series 1 Device Config 3

EFR32BG13B EFR32 Blue Gecko Family Series 1 Device Config 3

EFR32BG13V EFR32 Blue Gecko Family Series 1 Device Config 3

EFR32FG13P EFR32 Flex Gecko Family Series 1 Device Config 3

EFR32FG13B EFR32 Flex Gecko Family Series 1 Device Config 3

EFR32FG13V EFR32 Flex Gecko Family Series 1 Device Config 3

EFR32MG14P EFR32 Mighty Gecko Family Series 1 Device Config
4

EFR32MG14B EFR32 Mighty Gecko Family Series 1 Device Config
4

EFR32MG14V EFR32 Mighty Gecko Family Series 1 Device Config
4

EFR32BG14P EFR32 Blue Gecko Family Series 1 Device Config 4

EFR32BG14B EFR32 Blue Gecko Family Series 1 Device Config 4

EFR32BG14V EFR32 Blue Gecko Family Series 1 Device Config 4

EFR32FG14P EFR32 Flex Gecko Family Series 1 Device Config 4

EFR32FG14B EFR32 Flex Gecko Family Series 1 Device Config 4

EFR32FG14V EFR32 Flex Gecko Family Series 1 Device Config 4

EFM32G

EFM32 Gecko Device Family

EFM32GG

EFM32 Giant Gecko Device Family

EFM32 Tiny Gecko Device Family

EFM32TG

EFM32 Tiny Gecko Device Family

EFM32LG

EFM32 Leopard Gecko Device Family

EFM32WG

EFM32 Wonder Gecko Device Family

EFM32 Zero Gecko Device Family

EFM32ZG

EFM32 Zero Gecko Device Family

EFM32 Happy Gecko Device Family

EFM32HG

EFM32 Happy Gecko Device Family

EFM32PG1B

EFM32 Pearl Gecko Family Series 1 Device Config
1

EFM32JG1B

EFM32 Jade Gecko Family Series 1 Device Config
1

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Description

Preliminary Rev. 0.5 | 41

Reference Manual

Memory and Bus System
Bit

15:0

Name

Access

Description

EFM32PG12B EFM32 Pearl Gecko Family Series 1 Device Config
2

EFM32JG12B EFM32 Jade Gecko Family Series 1 Device Config
2

EFM32PG13B EFM32 Pearl Gecko Family Series 1 Device Config
3

EFM32JG13B EFM32 Jade Gecko Family Series 1 Device Config
3

100

EFM32GG11B EFM32 Giant Gecko Family Series 1 Device Config
1

103

EFM32TG11B EFM32 Tiny Gecko Family Series 1 Device Config 1

120

EZR32LG

EZR32 Leopard Gecko Device Family

121

EZR32WG

EZR32 Wonder Gecko Device Family

122

EZR32HG

EZR32 Happy Gecko Device Family

DEVICE_NUMBER

Part number as unsigned integer (e.g. 233 for
EFR32BG1P233F256GM48-B0)

4.7.11 DEVINFOREV - Device information page revision

DEVINFOREV RO

0x050

Bit Position
31

Offset

Access

Name

Bit

Name

Access

31:8

Reserved

Reserved for future use

7:0

DEVINFOREV

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Description

DEVINFO layout revision as unsigned integer (initially 1)

Preliminary Rev. 0.5 | 42

Reference Manual

Memory and Bus System
4.7.12 EMUTEMP - EMU Temperature Calibration Information

4
4

EMUTEMPROOM RO

5
5

0x054

Bit Position
31

Offset

Access

Name

Bit

Name

Access

Description

31:8

Reserved

Reserved for future use

7:0

EMUTEMPROOM

EMU_TEMP temperature reading at room

4.7.13 ADC0CAL0 - ADC0 calibration register 0

Bit

Name

Access

Reserved

Reserved for future use

30:24

GAIN2V5

Gain for 2.5V reference

23:20

NEGSEOFFSET2V5

Negative single ended offset for 2.5V reference

19:16

OFFSET2V5

Offset for 2.5V reference

Reserved

Reserved for future use

14:8

GAIN1V25

Gain for 1.25V reference

7:4

NEGSEOFFSET1V25

Negative single ended offset for 1.25V reference

3:0

OFFSET1V25

Offset for 1.25V reference

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RO
OFFSET1V25

NEGSEOFFSET1V25 RO

RO 11
GAIN1V25

RO
OFFSET2V5

GAIN2V5

Name

NEGSEOFFSET2V5

Access

RO 27

0x060

Bit Position
31

Offset

Description

Preliminary Rev. 0.5 | 43

Reference Manual

Memory and Bus System
4.7.14 ADC0CAL1 - ADC0 calibration register 1

Bit

Name

Access

Reserved

Reserved for future use

30:24

GAIN5VDIFF

Gain for for 5V differential reference

23:20

NEGSEOFFSET5VDIFF

Negative single ended offset with for 5V differential
reference

19:16

OFFSET5VDIFF

Offset for 5V differential reference

Reserved

Reserved for future use

14:8

GAINVDD

Gain for VDD reference

7:4

NEGSEOFFSETVDD

Negative single ended offset for VDD reference

3:0

OFFSETVDD

Offset for VDD reference

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RO
OFFSETVDD

RO
NEGSEOFFSETVDD

RO 11
GAINVDD

RO
OFFSET5VDIFF

GAIN5VDIFF

Name

NEGSEOFFSET5VDIFF RO

Access

RO 27

0x064

Bit Position
31

Offset

Description

Preliminary Rev. 0.5 | 44

Reference Manual

Memory and Bus System
4.7.15 ADC0CAL2 - ADC0 calibration register 2

OFFSET2XVDD

Name

2
2

Access

3
3

NEGSEOFFSET2XVDD RO

0x068

Bit Position
31

Offset

Bit

Name

Access

Description

Reserved

Reserved for future use

30:24

Reserved

Reserved for future use

23:20

Reserved

Reserved for future use

19:16

Reserved

Reserved for future use

15:8

Reserved

Reserved for future use

7:4

NEGSEOFFSET2XVDD

Negative single ended offset for 2XVDD reference

3:0

OFFSET2XVDD

Offset for 2XVDD reference

4.7.16 ADC0CAL3 - ADC0 calibration register 3

TEMPREAD1V25 RO

0x06C

Bit Position
31

Offset

Access

Name

Bit

Name

Access

31:16

Reserved

Reserved for future use

15:4

TEMPREAD1V25

3:0

Reserved

Reserved for future use

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Description

Temperature reading at 1V25 reference

Preliminary Rev. 0.5 | 45

Reference Manual

Memory and Bus System
4.7.17 HFRCOCAL0 - HFRCO Calibration Register (4 MHz)

Bit

Name

Access

Description

31:28

VREFTC

HFRCO Temperature Coefficient Trim on Comparator
Reference

FINETUNINGEN

HFRCO enable reference for fine tuning

26:25

CLKDIV

HFRCO Clock Output Divide

LDOHP

HFRCO LDO High Power Mode

23:21

CMPBIAS

HFRCO Comparator Bias Current

20:16

FREQRANGE

HFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
RO

TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x080

Bit Position
31

Offset

HFRCO Fine Tuning Value

HFRCO Tuning Value

Preliminary Rev. 0.5 | 46

Reference Manual

Memory and Bus System
4.7.18 HFRCOCAL3 - HFRCO Calibration Register (7 MHz)

Bit

Name

Access

Description

31:28

VREFTC

HFRCO Temperature Coefficient Trim on Comparator
Reference

FINETUNINGEN

HFRCO enable reference for fine tuning

26:25

CLKDIV

HFRCO Clock Output Divide

LDOHP

HFRCO LDO High Power Mode

23:21

CMPBIAS

HFRCO Comparator Bias Current

20:16

FREQRANGE

HFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
RO

TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x08C

Bit Position
31

Offset

HFRCO Fine Tuning Value

HFRCO Tuning Value

Preliminary Rev. 0.5 | 47

Reference Manual

Memory and Bus System
4.7.19 HFRCOCAL6 - HFRCO Calibration Register (13 MHz)

Bit

Name

Access

Description

31:28

VREFTC

HFRCO Temperature Coefficient Trim on Comparator
Reference

FINETUNINGEN

HFRCO enable reference for fine tuning

26:25

CLKDIV

HFRCO Clock Output Divide

LDOHP

HFRCO LDO High Power Mode

23:21

CMPBIAS

HFRCO Comparator Bias Current

20:16

FREQRANGE

HFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
RO

TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x098

Bit Position
31

Offset

HFRCO Fine Tuning Value

HFRCO Tuning Value

Preliminary Rev. 0.5 | 48

Reference Manual

Memory and Bus System
4.7.20 HFRCOCAL7 - HFRCO Calibration Register (16 MHz)

Bit

Name

Access

Description

31:28

VREFTC

HFRCO Temperature Coefficient Trim on Comparator
Reference

FINETUNINGEN

HFRCO enable reference for fine tuning

26:25

CLKDIV

HFRCO Clock Output Divide

LDOHP

HFRCO LDO High Power Mode

23:21

CMPBIAS

HFRCO Comparator Bias Current

20:16

FREQRANGE

HFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
RO

TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x09C

Bit Position
31

Offset

HFRCO Fine Tuning Value

HFRCO Tuning Value

Preliminary Rev. 0.5 | 49

Reference Manual

Memory and Bus System
4.7.21 HFRCOCAL8 - HFRCO Calibration Register (19 MHz)

Bit

Name

Access

Description

31:28

VREFTC

HFRCO Temperature Coefficient Trim on Comparator
Reference

FINETUNINGEN

HFRCO enable reference for fine tuning

26:25

CLKDIV

HFRCO Clock Output Divide

LDOHP

HFRCO LDO High Power Mode

23:21

CMPBIAS

HFRCO Comparator Bias Current

20:16

FREQRANGE

HFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
RO

TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x0A0

Bit Position
31

Offset

HFRCO Fine Tuning Value

HFRCO Tuning Value

Preliminary Rev. 0.5 | 50

Reference Manual

Memory and Bus System
4.7.22 HFRCOCAL10 - HFRCO Calibration Register (26 MHz)

Bit

Name

Access

Description

31:28

VREFTC

HFRCO Temperature Coefficient Trim on Comparator
Reference

FINETUNINGEN

HFRCO enable reference for fine tuning

26:25

CLKDIV

HFRCO Clock Output Divide

LDOHP

HFRCO LDO High Power Mode

23:21

CMPBIAS

HFRCO Comparator Bias Current

20:16

FREQRANGE

HFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
RO

TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x0A8

Bit Position
31

Offset

HFRCO Fine Tuning Value

HFRCO Tuning Value

Preliminary Rev. 0.5 | 51

Reference Manual

Memory and Bus System
4.7.23 HFRCOCAL11 - HFRCO Calibration Register (32 MHz)

Bit

Name

Access

Description

31:28

VREFTC

HFRCO Temperature Coefficient Trim on Comparator
Reference

FINETUNINGEN

HFRCO enable reference for fine tuning

26:25

CLKDIV

HFRCO Clock Output Divide

LDOHP

HFRCO LDO High Power Mode

23:21

CMPBIAS

HFRCO Comparator Bias Current

20:16

FREQRANGE

HFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
RO

TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x0AC

Bit Position
31

Offset

HFRCO Fine Tuning Value

HFRCO Tuning Value

Preliminary Rev. 0.5 | 52

Reference Manual

Memory and Bus System
4.7.24 HFRCOCAL12 - HFRCO Calibration Register (38 MHz)

Bit

Name

Access

Description

31:28

VREFTC

HFRCO Temperature Coefficient Trim on Comparator
Reference

FINETUNINGEN

HFRCO enable reference for fine tuning

26:25

CLKDIV

HFRCO Clock Output Divide

LDOHP

HFRCO LDO High Power Mode

23:21

CMPBIAS

HFRCO Comparator Bias Current

20:16

FREQRANGE

HFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
RO

TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x0B0

Bit Position
31

Offset

HFRCO Fine Tuning Value

HFRCO Tuning Value

Preliminary Rev. 0.5 | 53

Reference Manual

Memory and Bus System
4.7.25 AUXHFRCOCAL0 - AUXHFRCO Calibration Register (4 MHz)

Bit

Name

Access

Description

31:28

VREFTC

AUXHFRCO Temperature Coefficient Trim on Comparator Reference

FINETUNINGEN

AUXHFRCO enable reference for fine tuning

26:25

CLKDIV

AUXHFRCO Clock Output Divide

LDOHP

AUXHFRCO LDO High Power Mode

23:21

CMPBIAS

AUXHFRCO Comparator Bias Current

20:16

FREQRANGE

AUXHFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x0E0

Bit Position
31

Offset

AUXHFRCO Fine Tuning Value

AUXHFRCO Tuning Value

Preliminary Rev. 0.5 | 54

Reference Manual

Memory and Bus System
4.7.26 AUXHFRCOCAL3 - AUXHFRCO Calibration Register (7 MHz)

Bit

Name

Access

Description

31:28

VREFTC

AUXHFRCO Temperature Coefficient Trim on Comparator Reference

FINETUNINGEN

AUXHFRCO enable reference for fine tuning

26:25

CLKDIV

AUXHFRCO Clock Output Divide

LDOHP

AUXHFRCO LDO High Power Mode

23:21

CMPBIAS

AUXHFRCO Comparator Bias Current

20:16

FREQRANGE

AUXHFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x0EC

Bit Position
31

Offset

AUXHFRCO Fine Tuning Value

AUXHFRCO Tuning Value

Preliminary Rev. 0.5 | 55

Reference Manual

Memory and Bus System
4.7.27 AUXHFRCOCAL6 - AUXHFRCO Calibration Register (13 MHz)

Bit

Name

Access

Description

31:28

VREFTC

AUXHFRCO Temperature Coefficient Trim on Comparator Reference

FINETUNINGEN

AUXHFRCO enable reference for fine tuning

26:25

CLKDIV

AUXHFRCO Clock Output Divide

LDOHP

AUXHFRCO LDO High Power Mode

23:21

CMPBIAS

AUXHFRCO Comparator Bias Current

20:16

FREQRANGE

AUXHFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x0F8

Bit Position
31

Offset

AUXHFRCO Fine Tuning Value

AUXHFRCO Tuning Value

Preliminary Rev. 0.5 | 56

Reference Manual

Memory and Bus System
4.7.28 AUXHFRCOCAL7 - AUXHFRCO Calibration Register (16 MHz)

Bit

Name

Access

Description

31:28

VREFTC

AUXHFRCO Temperature Coefficient Trim on Comparator Reference

FINETUNINGEN

AUXHFRCO enable reference for fine tuning

26:25

CLKDIV

AUXHFRCO Clock Output Divide

LDOHP

AUXHFRCO LDO High Power Mode

23:21

CMPBIAS

AUXHFRCO Comparator Bias Current

20:16

FREQRANGE

AUXHFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x0FC

Bit Position
31

Offset

AUXHFRCO Fine Tuning Value

AUXHFRCO Tuning Value

Preliminary Rev. 0.5 | 57

Reference Manual

Memory and Bus System
4.7.29 AUXHFRCOCAL8 - AUXHFRCO Calibration Register (19 MHz)

Bit

Name

Access

Description

31:28

VREFTC

AUXHFRCO Temperature Coefficient Trim on Comparator Reference

FINETUNINGEN

AUXHFRCO enable reference for fine tuning

26:25

CLKDIV

AUXHFRCO Clock Output Divide

LDOHP

AUXHFRCO LDO High Power Mode

23:21

CMPBIAS

AUXHFRCO Comparator Bias Current

20:16

FREQRANGE

AUXHFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x100

Bit Position
31

Offset

AUXHFRCO Fine Tuning Value

AUXHFRCO Tuning Value

Preliminary Rev. 0.5 | 58

Reference Manual

Memory and Bus System
4.7.30 AUXHFRCOCAL10 - AUXHFRCO Calibration Register (26 MHz)

Bit

Name

Access

Description

31:28

VREFTC

AUXHFRCO Temperature Coefficient Trim on Comparator Reference

FINETUNINGEN

AUXHFRCO enable reference for fine tuning

26:25

CLKDIV

AUXHFRCO Clock Output Divide

LDOHP

AUXHFRCO LDO High Power Mode

23:21

CMPBIAS

AUXHFRCO Comparator Bias Current

20:16

FREQRANGE

AUXHFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x108

Bit Position
31

Offset

AUXHFRCO Fine Tuning Value

AUXHFRCO Tuning Value

Preliminary Rev. 0.5 | 59

Reference Manual

Memory and Bus System
4.7.31 AUXHFRCOCAL11 - AUXHFRCO Calibration Register (32 MHz)

Bit

Name

Access

Description

31:28

VREFTC

AUXHFRCO Temperature Coefficient Trim on Comparator Reference

FINETUNINGEN

AUXHFRCO enable reference for fine tuning

26:25

CLKDIV

AUXHFRCO Clock Output Divide

LDOHP

AUXHFRCO LDO High Power Mode

23:21

CMPBIAS

AUXHFRCO Comparator Bias Current

20:16

FREQRANGE

AUXHFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x10C

Bit Position
31

Offset

AUXHFRCO Fine Tuning Value

AUXHFRCO Tuning Value

Preliminary Rev. 0.5 | 60

Reference Manual

Memory and Bus System
4.7.32 AUXHFRCOCAL12 - AUXHFRCO Calibration Register (38 MHz)

Bit

Name

Access

Description

31:28

VREFTC

AUXHFRCO Temperature Coefficient Trim on Comparator Reference

FINETUNINGEN

AUXHFRCO enable reference for fine tuning

26:25

CLKDIV

AUXHFRCO Clock Output Divide

LDOHP

AUXHFRCO LDO High Power Mode

23:21

CMPBIAS

AUXHFRCO Comparator Bias Current

20:16

FREQRANGE

AUXHFRCO Frequency Range

15:14

Reserved

Reserved for future use

13:8

FINETUNING

Reserved

Reserved for future use

6:0

TUNING

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3
TUNING

FINETUNING

RO 18
FREQRANGE

RO 22
CMPBIAS

RO 24
LDOHP

RO
CLKDIV

FINETUNINGEN RO 27

Name

Access

VREFTC

0x110

Bit Position
31

Offset

AUXHFRCO Fine Tuning Value

AUXHFRCO Tuning Value

Preliminary Rev. 0.5 | 61

Reference Manual

Memory and Bus System
4.7.33 VMONCAL0 - VMON Calibration Register 0

Name

Access

Description