Course: ECE 124 Digital Circuits And Systems Manual
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Page Count: 96
- 2 Introduction and ECE-124 Labs Outline
- 3 Lab 1 – Design Entry Using Altera Quartus-II
- 4 Lab 2 – VHDL - Combinational Circuits PART 1 – Simple ALU Design
- 4.1 Prelab
- 4.2 Lab2 Outline
- 4.3 Lab2 Activities
- 4.3.1 Recall from Lab1:
- 4.3.2 Recalling Some Constructs of a VHDL Design
- 4.3.3 Design Re-use of VHDL – Structural Coding Style
- 4.3.4 Project Setup for Lab2
- 4.3.5 NEW VHDL Component - What is a Seven Segment Decoder?
- 4.3.6 Lab2-Part A – Hunting for “BUGS”
- 4.3.7 NEW VHDL Component - What is a Multiplexer or MUX function?
- 4.3.8 Lab2-Part B – Using the Seven Segment Displays
- 4.3.9 Lab2-Part C- Project Brief for Lab2 Demo
- 4.4 POST- Lab2 Activities
- 4.5 LAB2 SUBMISSION FORM
- 5 LAB3: VHDL for Combinational Circuits PART 2 – Energy Monitor
- 5.1 Prelab
- 5.2 Lab3 Outline
- 5.3 Lab3 Activities
- 5.4 POST - Lab3 Activities
- 5.5 LAB3 SUBMISSION FORM
- 6 LAB4: VHDL for Sequential Circuits – Flip-flops & State-Machines
- 6.1 Prelab
- 6.2 Lab4 Outline
- 6.3 Lab4 Activities
- 6.3.1 Recall from Lab3:
- 6.3.2 Brief Discussion on Sequential Processing
- 6.3.3 New VHDL Component – What is a Flip-Flop?
- 6.3.4 What are VHDL Processes?
- 6.3.5 Initial Project Setup for Lab4
- 6.3.6 Lab4 Part A – Creating Some Simple Flip-Flop Register Designs
- 6.3.7 New VHDL Component – What is a State Machine?
- 6.3.8 Lab4 Part B - Project Brief for Lab4 Demo
- 6.4 POST – Lab4 Activities
- 6.5 LAB4 SUBMISSION FORM