Zd1 F Quanta Re Schematics
User Manual: Quanta ZD1 - Schematics. Free.
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5 4 X'TAL 14.318MHZ 3 2 1 P33 CLOCK GENERATOR P2 FSB TVOUT CRT Thermal Sensor X4 DMI interface HDD (SATA) P24 SATA0 SATA1 SB PATA P24 Bluetooth P21 P25 CCD USB7 MXM-NB8P-GS USB6 ( nVidia ) VRAM 256M Mini Card / VRAM 512M WLAN / 3G(TV) P17 USB5 C P22 PCI-Express PCIE-2 Int MIC P27 P21 B P23 PCIE-4 MIC Jack PCIE-6 P27 Connector X'TAL 25M BROADCOM 1394 +Cardreader Controller 10/100/1G LAN 5787M P20 B R5C832/833 P28 Transformer P20 EC (WPC8769LDG) RJ45 P31 P21 IEEE 1394 Port Media Card Reader P28 Fan Header P21,P30 P28 SPI ROM w P27 Line in w .R P27 PCIE-5 X'TAL24.576MHZ P12,P13,P14,P15 X'TAL 32.768K w Audio Amplifier P29 PCIE-1 PCI Bus LPC Azalia Audio Controller ALC268&888 P26 Robson New Card X'TAL 32.768KHZ USB Port x 4 USB0~3 DVI LVDS VGA/TV out ah as USB4 ICH8M USB 2.0 Azalia P35,36 P16 P5,P6,P7,P8,P9,P10,P11 C +1.8V / +1.05V P37 DDRII SO-DIMM 0 SO-DIMM 1 ia La pt op .c Dual Channel DDR2 533/667 MHz D P32 DISCHARGE PCI-Express 16X Lan P18 ODD (PATA) P33 667/800 Mhz NB Crestline PM965 VGA LVDS WXGA WSXGA+ WUXGA BATTERYCHARGER (ISL6251) 5V/3.3V (ISL6236) P3 P19 TFT LCD Panel P37 CPU Merom 479 uFCPGA P3,P4 om SELGO: SLG8SP512K05 D +1.2V/+1.25V/1.5V/2.5V VCORE(ISL6262A) ZD1(CHAPALA) SYSTEM BLOCK DIAGRAM VR P31 P26 BOM MARK A Speaker Phone Jack P27 P27 MDC 1.5 P26 EV@ EXT VGA 要打 Touch Pad CIR P30 A IV@ INT VGA 要打 268@ AUDIO 268 要打 P21 888@ AUDIO 888要打 PROJECT : ZD1 K/B COON. Quanta Computer Inc. P30 Size Document Number Rev E Block Diagram Date: 5 4 3 2 Wednesday, April 25, 2007 Sheet 1 1 of 38 5 4 3 2 1 Clock Generator Change list: B-test 1.Change U31 P/N to ALPRS365K13 (ICS) +3V +3V +3V +3V_VDD_A R205 BKP1608HS181-T C347 C349 C340 C352 C362 C342 C345 C339 4.7U/10V .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 10U/6.3V R435 *10K_4 R443 *10K_4 PCI_CLK_SIO D PCLK_ICH R439 10K_4 +1.25V_VDD U31 <14> SATACLKREQ# <28> PCLK_PCM <22,30> PCLK_DEBUG <31> PCLK_591 PCI_CLK_SIO <13> PCLK_ICH C <14> CLKUSB_48 C: For EMI solution MCH_BSEL1 0_4 R206 0_4 R431 2 9 16 39 55 VDD_A_REF 61 VDD_A_48 VDD_PCI VDD_48 VDD_PLL3 VDD_SRC VDD_CPU VDD_REF *30P/50V_4 XTAL_OUT CPU_0 XTAL_IN CPU_0# PCI_0/CLKREQ_A# CPU_1_MCH PCI_1/CLKREQ_B# CPU_1_MCH# PCI_2 SRC_8/CPU_ITP PCI_3 SRC_8#/CPU_ITP# ^PCI_4/LCDCLK_SEL PCIF_5/ITP_EN NC R447 33_4 FSA 10 57 USB_48MHz/FS_A FS_B/TEST_MODE R423 33_4 FSC 62 REF/FS_C/TEST_SEL 3 IV@0X2 DREFCLK_R DREFCLK#_R 1XTAL length < 500mils <3> CPU_BSEL0 +1.05V RP45 3 1 4 IV@0X2 2 SRC_2 SRC_2# SRC_3/CLKREQ_C# SRC_3#/CLKREQ_D# SRC_4 SRC_4# SRC_6 SRC_6# SRC_7/CLKREQ_F# SRC_7#/CLKREQ_E# SRC_9 SRC_9# SRC_10 SRC_10# SRC_11/CLKREQ_H# SRC_11#/CLKREQ_G# 21 22 24 25 27 28 41 40 44 43 30 31 34 35 33 32 CLK_PCIE_SATA_R CLK_PCIE_SATA#_R CLK_PCIE_LAN_R CLK_PCIE_LAN#_R CLK_PCIE_MINI1_R CLK_PCIE_MINI1#_R CLK_PCIE_ICH_R CLK_PCIE_ICH#_R PECLK_VGA_R PECLK_VGA#_R CLK_PCIE_NEW_C_R CLK_PCIE_NEW_C#_R CLK_PCIE_3GPLL_R CLK_PCIE_3GPLL#_R CLK_PCIE_TV_R CLK_PCIE_TV#_R RP47 3 1 RP49 3 1 RP51 3 1 RP50 1 3 RP48 1 3 RP53 3 1 RP52 3 1 RP36 3 1 4 2 4 2 4 2 2 4 2 4 4 2 4 2 4 2 SRC_0/DOT_96 SRC_0#/DOT_96# SCL SDA CG_XOUT <3> CPU_BSEL2 +1.05V CLK_DREFSSCLK <7> CLK_DREFSSCLK# <7> 0X2 CLK_PCIE_SATA <12> CLK_PCIE_SATA# <12> CLK_PCIE_LAN <20> CLK_PCIE_LAN# <20> CLK_PCIE_MINI1 <22> CLK_PCIE_MINI1# <22> CLK_PCIE_ICH <13> CLK_PCIE_ICH# <13> CLK_MXM <17> CLK_MXM# <17> CLK_PCIE_NEW_C <23> CLK_PCIE_NEW_C# <23> CLK_PCIE_3GPLL <7> CLK_PCIE_3GPLL# <7> CLK_PCIE_TV <22> CLK_PCIE_TV# <22> 0X2 0X2 0X2 EV@0X2 0X2 0X2 0X2 PCLK_DEBUG 2.2K_4 CLKUSB_48 MCH_BSEL2 R424 10K_4 FSC C Clock Gen I2C +3V Q27 RHU002N06 3 <14,16,22,23> PDAT_SMB R455 R456 0_4 MCH_BSEL0 R428 R429 10K_4 10K_4 1 CGDAT_SMB 1 CGCLK_SMB +3V B 3 <14,16,22,23> PCLK_SMB MCH_BSEL0 <7> BSEL Frequency Select Table *56_4 FSC FSB FSA Frequency 0 0 0 266Mhz 0 0 1 133Mhz 0 1 1 166Mhz 0 1 0 200Mhz 1 1 0 400Mhz w *1K_4 R451 0_4 MCH_BSEL1 MCH_BSEL1 <7> R449 *0_4 R454 *1K_4 R425 0_4 1 1 1 Reserved R427 *0_4 1 0 1 100Mhz R426 *1K_4 1 0 0 333Mhz MCH_BSEL2 MCH_BSEL2 <7> A PROJECT : ZD1 Quanta Computer Inc. Size 4 3 2 Document Number Rev E CLOCK GENERATOR CK505 W/REGULATOR Date: 5 10K_4 Q28 RHU002N06 Main: ICS9LPRS365BGLFT:ALPRS365K13 SLG8SP512T: AL8SP512K05 A +1.05V R433 MCH_BSEL0 R446 +3V CLK_CPU_BCLK <3> CLK_CPU_BCLK# <3> CLK_MCH_BCLK <5> CLK_MCH_BCLK# <5> PCIE_CLK_RBS <29> PCIE_CLK_RBS# <29> ICS9LPRS365BGLFT R450 <3> CPU_BSEL1 2 0X2 4 2 0X2 4 2 0X2 4 CLK_DREFSSCLK_R CLK_DREFSSCLK#_R w .R CPU Clock select 33P/50V_4 RP42 1 3 RP44 1 3 RP46 1 3 48 w C565 B Y4 14.318MHz CLK_CPU_BCLK_R CLK_CPU_BCLK#_R CLK_MCH_BCLK_R CLK_MCH_BCLK#_R PCIE_CLK_RBS_R PCIE_CLK_RBS#_R 17 18 64 63 VSS_PCI VSS_48 VSS_I/O VSS_PLL3 VSS_SRC_1 VSS_SRC_2 VSS_SRC_3 VSS_CPU VSS_REF PM_STPCPU# <14> PM_STPPCI# <14> CK_PWRGD <14> LCDCLK/27M LCDCLK#/27M_SS 13 14 8 11 15 19 23 29 42 52 58 CG_XIN 33P/50V_4 54 53 51 50 47 46 R430 R432 R434 R436 R440 R444 CGCLK_SMB CGDAT_SMB C563 37 38 56 59 60 1 3 4 5 6 7 RP43 4 2 <7> CLK_DREFCLK <7> CLK_DREFCLK# CPU_STOP# PCI_STOP# CKPWRGD/PD# +1.25V_VDD ah as <14> 14M_ICH 12 20 26 36 45 49 CG_XOUT CG_XIN 475_4 SATACLKREQ#_R 33_4 PCI_CLK_7412_R 33_4 PCLK_MINI_R 33_4 PCLK_591_R 33_4 PCI_CLK_SIO_R 33_4 PCLK_ICH_R 14M_ICH C645 VDD_I/O VDD_PLL3_I/O VDD_SRC_I/O_1 VDD_SRC_I/O_2 VDD_SRC_I/O_3 VDD_CPU_I/O ia La pt op .c 4.7U/10V .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 10U/6.3V 2 +3V_VDD_A C355 C350 C375 C372 C353 C360 C359 C358 2 R220 BKP1608HS181-T R207 10K_4 om +1.25V D Sheet Monday, May 07, 2007 1 2 of 38 5 4 A6 A5 C4 A20M# FERR# IGNNE# D5 C6 B4 A3 STPCLK# LINT0 LINT1 SMI# M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] H_DEFER# <5> H_DRDY# <5> H_DBSY# <5> H_LOCK# <5> C1 F3 F4 G3 G2 H_CPURST# <5> H_RS#0 <5> H_RS#1 <5> H_RS#2 <5> H_TRDY# <5> HIT# HITM# G6 E4 H_HIT# <5> H_HITM# <5> XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET# D21 H_PROCHOT_R# A24 H_THERMDA B25 H_THERMDC PROCHOT# THERMDA THERMDC C7 THERMTRIP# H CLK PM_THRMTRIP# A22 A21 BCLK[0] BCLK[1] 0_4 R355 56.2/F_4 R82 *2.2K_4 Layout note: Z=55 ohm H_GTLREF<0.5" A R365 <5> H_DSTBN#1 1K/F_4 <5> H_DSTBP#1 <5> H_DINV#1 R101 R369 R364 2K/F T10 T74 T7 T73 <2> CPU_BSEL0 <2> CPU_BSEL1 <2> CPU_BSEL2 B22 B23 C21 BSEL[0] BSEL[1] BSEL[2] 200 *0_4 +3V R363 *10K_4 U24 H_THERMDA 8 SCLK VCC 1 7 SDA DXP 2 C518 6 ALERT# DXN 3 2200P/50V_4 4 OVERT# GND 5 H_THERMDC MAX6657 ADDRESS: 98H CPUFAN#_ON Layout Note:Routing 10:10 mils and away from noise source with ground gard <30> CPUFAN#_ON ah as C PU/PD (ITP700) +1.05V AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 COMP[0] COMP[1] COMP[2] COMP[3] R26 U26 AA1 Y1 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 MISC Q3 R55 D4 FDV301N *10K_4 *BAS316 C39 R56 56.2/F_4 1 XDP_TMS R44 39/F_4 XDP_TDI R42 150/F_4 XDP_BPM#5 R47 *54.9/F_4 XDP_TDO R45 54.9/F_4 R54 27/F_4 *1U B Q4 MMBT3904 3 SYS_SHDN# <33> PM_THRMTRIP# <7,12> XDP_TCK Layout Note: Thermal trip should connect to ICH8 & GMCH without T-ing (ZS1 default NC) XDP_TRST# R46 680/F_4 Layout note: L<0.5" COMP0/2 Z=27.4ohm COMP1/3 Z=54.9 H_DSTBN#3 <5> H_DSTBP#3 <5> H_DINV#3 <5> COMP0 COMP1 COMP2 COMP3 2 +1.05V PM_THRMTRIP# H_DSTBN#2 <5> H_DSTBP#2 <5> H_DINV#2 <5> H_D#[63:48] <5> H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 +1.05V <7,14,34> DELAY_VR_PWRGOOD 1 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 2 Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 R367 R366 R48 R43 27.4/F 54.9/F_4 27.4/F 54.9/F_4 H_DPSLP# <12> H_DPWR# <5> Layout Note:Connect from SB and daisy chain to CPU CORE VR.Not use T connect.(SB/VR/CPU/NB) A ICH_DPRSTP# <7,12,34> PROJECT : ZD1 H_PWRGD <12> H_CPUSLP# <5> PSI# <34> Size Quanta Computer Inc. Document Number Date: Monday, May 07, 2007 Merom Ball-out Rev 1a 5 D LM86VCC C517 R362 <14,17> THERM_ALERT# w .R D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# DATA GRP 2 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 R357 10K_4 H_D#[47:32] <5> D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# H_GTLREF AD26 *1K_4 CPU_TEST1 C23 *1K_4 CPU_TEST2 D25 CPU_TEST3 C24 CPU_TEST4 AF26 CPU_TEST5 AF1 CPU_TEST6 A26 R361 10K_4 1 H_PROCHOT# <34> CLK_CPU_BCLK <2> CLK_CPU_BCLK# <2> U22B E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 DATA GRP 1 +1.05V H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 R360 .1U/10V_4 w H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[31:16] 3 SYS_RST# <14> +1.05V Q26 RHU002N06 Default PU 56ohm if no use. Serial R NC, If connect to power side PU 68ohm. Serial R 2.2K w <5> <5> <5> <5> 1 Thermal Trip DATA GRP 3 B <31,32> MBDATA T8 T2 T3 T6 T4 T5 R358 3 2 H4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 Q25 RHU002N06 +3V LOCK# THERMAL DATA GRP 0 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 <31,32> MBCLK 56.2/F_4 +1.05V H_INIT# <12> RESET# RS[0]# RS[1]# RS[2]# TRDY# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# +3V +3V H_BREQ#0 <5> R79 Merom Ball-out Rev 1a <5> H_D#[15:0] CPU Thermal monitor 2 H5 F21 E1 D20 H_IERR# B3 IERR# INIT# ICH H_STPCLK_R# H_ADS# <5> H_BNR# <5> H_BPRI# <5> F1 BR0# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# H1 E2 G5 om <12> H_A20M# <12> H_FERR# <12> H_IGNNE# 0_4 1 3 <5> H_ADSTB1# <12> H_INTR <12> H_NMI <12> H_SMI# DEFER# DRDY# DBSY# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 R350 <12> H_STPCLK# ADS# BNR# BPRI# ADDR GROUP 1 C K3 H2 K2 J3 L1 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 2 ia La pt op .c <5> H_A#[35:17] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# CONTROL <5> H_ADSTB0# <5> H_REQ#[4:0] J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 XDP/ITP SIGNALS D H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 ADDR GROUP 0 CPU(HOST) 3 U22A RESERVED <5> H_A#[16:3] Rev E CPU(1 of 2)/FAN/Thermal 4 3 2 Sheet 1 3 of 38 5 4 3 2 1 CPU(Power) VCC_CORE U22D U22C C49 C55 C59 C69 C84 C94 C102 C56 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 C60 C42 C47 C53 C58 C63 C80 C90 C99 C51 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 C93 C97 C91 C44 C83 C70 DESIGN GUIDE CHANGE FROM 22UF *20 TO 10UF *32 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 C C86 C77 C61 C48 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 + C40 C57 C52 + C41 330U/2.5V_7 330U_7 + C100 330U/2.5V_7 Option1:330U*6(ESR=1.5m ohm aggregate , ESL=0.8nH/6) and 22U*20(ESR=3mohm typ/20 , ESL=0.6nH/20) Option2:330U*6(ESR=1.5m ohm aggregate , ESL=1.8nH/6) and 22U*32(ESR=3mohm typ/32 , ESL=0.6nH/32) B A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCA[01] VCCA[02] B26 C26 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] AD6 AF5 AE5 AF4 AE3 AF3 AE2 Ivcc Max 52A Ivccp Max 6A(VCCP supply before Vcc stable) Max 2A(VCCP supply after Vcc stable) Ivcca Max 130mA om C46 +1.05V C76 C45 C75 .1U/16V .1U/16V .1U/16V .1U/16V .1U/16V C81 ia La pt op .c C43 .1U/16V C89 C82 +1.05V 0C Delete R75,R63 0104 + C54 ohm 330U/2.5V_7ESR=12m +1.5V .01U near to B26 ball +VCCA_PROC ah as D A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 R368 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 <34> <34> <34> <34> <34> <34> <34> VCC_CORE C520 0 C130 .01U/16V_4 10U/10V_8 R62 100/F VCCSENSE AF7 VCCSENSE <34> VSSSENSE AE7 VSSSENSE <34> Merom Ball-out Rev 1a w .R . R58 100/F Routing 27.4ohm with 50mils spacing PU/PD near to CPU 1" VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] D C B Merom Ball-out Rev 1a w w . A A PROJECT : ZD1 Size Quanta Computer Inc. Document Number Date: Monday, May 07, 2007 Rev E CPU(2 of 2) 5 4 3 2 Sheet 1 4 of 38 5 4 3 2 1 NB(HOST) D D R376 .1U/10V_4 C H_RCOMP 24.9_4 10:20 mils(Width:Spacing) ah as R370 w .R B R111 H_SCOMP +1.05V 54.9_4 R110 H_SCOMP# 54.9_4 H_SWING H_RCOMP B3 C2 H_SWING H_RCOMP H_SCOMP H_SCOMP# W1 W2 H_SCOMP H_SCOMP# B6 E5 H_CPURST# H_CPUSLP# w <3> H_CPURST# <3> H_CPUSLP# H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 R383 B9 A9 H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 K5 L2 AD13 AE13 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 M7 K3 AD2 AH11 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 L7 K2 AC2 AJ10 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 M14 E13 A11 H13 B12 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#_0 H_RS#_1 H_RS#_2 E12 D7 D8 H_RS#0 H_RS#1 H_RS#2 C H_A#[35:32] are not supported in Calero Interposer Crestline support 36 bit address H_ADS# <3> H_ADSTB0# <3> H_ADSTB1# <3> H_BNR# <3> H_BPRI# <3> H_BREQ#0 <3> H_DEFER# <3> H_DBSY# <3> CLK_MCH_BCLK <2> CLK_MCH_BCLK# <2> H_DPWR# <3> H_DRDY# <3> H_HIT# <3> H_HITM# <3> H_LOCK# <3> H_TRDY# <3> H_DINV#[3:0] <3> B H_DSTBN#[3:0] <3> H_DSTBP#[3:0] <3> H_REQ#[4:0] <3> H_RS#[2:0] <3> H_AVREF H_DVREF CRESTLINE_1p0 w +1.05V H_AVREF H_DVREF HOST 0.1U close to B3 C530 100_4 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 ia La pt op .c H_SWING R378 E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13 om H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 +1.05V 221_4 H_A#[35:3] <3> U30A <3> H_D#[63:0] 1K_4 A H_AVREF A R384 0_4 H_DVREF 0.1U close to B9 R382 C153 2K_4 .1U/10V_4 PROJECT : ZD1 Size Quanta Computer Inc. Document Number Rev E GMCH HOST(1/7) Date: 5 4 3 2 Sheet Monday, May 07, 2007 1 5 of 38 4 3 Vcc1_5 for Calero Vcc1_25/Vcc1_05 for Crestline D U30C <18> INT_LVDS_EDIDCLK <18> INT_LVDS_EDIDDATA <18> INT_LVDS_DIGON For Calero : 1.5K For Cresstline:2.4K IV&EV Dis/Enable setting T45 INT_TXLCLKOUTINT_TXLCLKOUT+ INT_TXUCLKOUTINT_TXUCLKOUT+ LVDS_IBG L41 LVDS_VBGL43 N41 N40 D46 C45 D44 E42 LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK <18> INT_TXLOUT0<18> INT_TXLOUT1<18> INT_TXLOUT2- G51 E51 F49 LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 <18> INT_TXLOUT0+ <18> INT_TXLOUT1+ <18> INT_TXLOUT2+ G50 E50 F48 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 <18> INT_TXUOUT0<18> INT_TXUOUT1<18> INT_TXUOUT2- G44 B47 B45 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 <18> INT_TXUOUT0+ <18> INT_TXUOUT1+ <18> INT_TXUOUT2+ E44 A47 A45 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 INT_TV_COMP INT_TV_Y/G INT_TV_C/R +3V R151 R200 E27 G27 K27 TVA_DAC TVB_DAC TVC_DAC F27 J27 L27 TVA_RTN TVB_RTN TVC_RTN TV_DCONSEL_0 M35 TV_DCONSEL_1 P33 *2.2K_4 *2.2K_4 TV_DCONSEL_0 TV_DCONSEL_1 If no use can be NC INT_CRT_BLU <19> INT_CRT_BLU INT_CRT_GRN <19> INT_CRT_GRN INT_CRT_RED <19> INT_CRT_DDCCLK <19> INT_CRT_DDCDAT <19> INT_HSYNC R169 R405 <19> INT_VSYNC K33 G35 IV@39_4 HSYNC1 F33 CRTIREF C32 IV@39_4 VSYNC1 E33 CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC w .R IV&EV Dis/Enable setting HSYNC/VSYNC serial R place close to NB N43 EXP_A_COMPX M43 PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41 PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 R201 +1.05_PEG 24.9/F_4 PEG_RXN[15:0] <17> SDVO/PCIE/LVDS not implement 16 lanes NC For IV@ Connect to 150ohm CRT R/G/B TV A/B/C Connect to 39ohm HSYNC/VSYNC R167 R166 EV@0_4 EV@0_4 R147 IV@150/F_4 INT_TV_COMP R145 IV@150/F_4 INT_TV_Y/G R144 IV@150/F_4 INT_TV_C/R R157 IV@150/F_4 INT_CRT_BLU R148 IV@150/F_4 INT_CRT_GRN R155 IV@150/F_4 INT_CRT_RED D HSYNC1 VSYNC1 PEG_RXP[15:0] <17> PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 N45 C_PEG_TXN0 U39 C_PEG_TXN1 U47 C_PEG_TXN2 N51 C_PEG_TXN3 R50 C_PEG_TXN4 T42 C_PEG_TXN5 Y43 C_PEG_TXN6 W46 C_PEG_TXN7 W38 C_PEG_TXN8 AD39 C_PEG_TXN9 AC46 C_PEG_TXN10 AC49 C_PEG_TXN11 AC42 C_PEG_TXN12 AH39 C_PEG_TXN13 AE49 C_PEG_TXN14 AH44 C_PEG_TXN15 C305 C300 C309 C307 C308 C301 C316 C331 C320 C311 C326 C313 C322 C318 C315 C329 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 M45 C_PEG_TXP0 T38 C_PEG_TXP1 T46 C_PEG_TXP2 N50 C_PEG_TXP3 R51 C_PEG_TXP4 U43 C_PEG_TXP5 W42 C_PEG_TXP6 Y47 C_PEG_TXP7 Y39 C_PEG_TXP8 AC38 C_PEG_TXP9 AD47 C_PEG_TXP10 AC50 C_PEG_TXP11 AD43 C_PEG_TXP12 AG39 C_PEG_TXP13 AE50 C_PEG_TXP14 AH43 C_PEG_TXP15 C303 C299 C306 C304 C310 C302 C317 C325 C321 C312 C327 C324 C323 C319 C314 C328 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 EV@.1U/10V_4 PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15 C PEG_TXN[15:0] <17> PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 PEG_TXP[15:0] <17> PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15 B IV&EV Dis/Enable setting CRESTLINE_1p0 TV_DCONSEL_0 R513 TV_DCONSEL_1 R514 w w 0 R397 For Calero : 255 For Cresstline:1.3K/F For external VGA:0 ohm Flexible and safe CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# VGA <19> INT_CRT_RED B H32 G32 K29 J29 F29 E29 TV <19> INT_TV_COMP <19> INT_TV_Y/G <19> INT_TV_C/R PEG_COMPI PEG_COMPO ah as C IV@2.4K_4 LVDS <18> <18> <18> <18> R182 L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN 1 For EV@ Connect to GND CRT R/G/B TV A/B/C HSYNC/VSYNC ia La pt op .c J40 H39 E39 E40 C37 D35 K40 10K_4 10K_4 GRAPHICS R406 R413 +3V PCI-EXPRESS <18> L_BKLT_CTRL <23> INT_LVDS_BLON 2 om 5 EV@0_4 EV@0_4 A A INTEL FAE reuqest PD. PROJECT : ZD1 Quanta Computer Inc. Size Document Number Date: Monday, May 07, 2007 Rev E GMCH GRAPHICS(2/7) 5 4 3 2 Sheet 1 6 of 38 5 4 3 2 Strapping table U30B CFG[11:10] CFG[13:12] PCI Express Graphics Lane Reversal Reserved XOR/ ALLZ/ Clock Un gating CFG[15:14] CFG16 Reserved FSB Dynamic ODT SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4 BE29 AY32 BD39 BG37 M_CKE0 M_CKE1 M_CKE2 M_CKE3 <16> <16> <16> <16> SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 BG20 BK16 BG16 BE13 M_CS#0 M_CS#1 M_CS#2 M_CS#3 <16> <16> <16> <16> SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 BH18 BJ15 BJ14 BE16 M_ODT0 M_ODT1 M_ODT2 M_ODT3 <16> <16> <16> <16> SM_RCOMP SM_RCOMP# BL15 BK14 M_RCOMP M_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL BK31 BL31 SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF_0 SM_VREF_1 AR49 AW4 +SM_VREF_MCH DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# B42 C42 H48 H47 CLK_DREFCLK CLK_DREFCLK# CLK_DREFSSCLK CLK_DREFSSCLK# PEG_CLK PEG_CLK# K44 K45 CLK_PCIE_3GPLL CLK_PCIE_3GPLL# INTEL CRB ADD 0.1UF C165 00 = Clock gating disable 01 = ALL-Z Mode Enable 10 = XOR Mode Enable 11 = Normal Cperation (Default) 0 = Dynamic ODT disable 1 = Dynamic ODT Enable (Default) CFG[18:17] CFG19 Reserved DMI Lane Reversal CFG20 SDVO/PCIe concurrent SDVO_CTRLDATA SDVO Present 0 = Normal operation 1 = Reverse Lanes (Default) 0 = Only SDVO or PCIE x1 is operation (Default) 1 = SDVO and PCIE x1 are operating simultaneously via the PEG port 0 = No SDVO Card present (Default) 1 = SDVO Card Present INTEL CRB CRESSTLINE SHOULD USE 20OHM C +1.8VSUS M_RCOMP# R Value select For Calero : 80.6ohm For Cresstline:20ohm But check list use 80.6ohm R387 80.6ohm 20/F_4 R388 20/F_4 M_RCOMP <2> MCH_BSEL0 <2> MCH_BSEL1 <2> MCH_BSEL2 T34 T24 T29 ah as +3V T37 T28 R170 10K_4 CLK_MCH_OE# R395 10K_4 PM_EXTTS#0 R149 10K_4 PM_EXTTS#1 T25 T27 T32 T40 B w .R +3V R138 *4.02K/F_4 MCH_CFG_9 R127 *4.02K/F_4 MCH_CFG_12 R139 *4.02K/F_4 MCH_CFG_13 R137 *4.02K/F_4 MCH_CFG_19 R171 *4.02K/F_4 MCH_CFG_16 R129 *4.02K/F_4 MCH_CFG_20 R174 *4.02K/F_4 R140 R130 R407 0_4 0_4 0_4 0_4 A G41 L39 L36 J36 AW49 RST_IN#_MCH 100_4 AV20 *0_4 PM_THRMTRIP#_GMCH N20 0_4 PM_DPRSLPVR_GMCH G36 BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2 R416 w +1.8VSUS R154 1K/F_4 R417 BK1608LL121 *1K/F_4 SM_RCOMP_VOH R165 C241 C232 3.01K/F_4 .01U/16V_4 2.2U/6.3V +SM_VREF_MCH R418 C295 *1K/F_4 .1U/10V_4.1U/10V_4 P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC +SMDDR_VREF +1.8VSUS RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 PM_BMBUSY#_R ICH_DPRSTP#_R PM_EXTTS#0_R PM_EXTTS#1_R w MCH_CFG_5 R184 R177 R401 R150 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34 PM <14> PM_BMBUSY# <3,12,34> ICH_DPRSTP# <16> PM_EXTTS#0 <16> PM_EXTTS#1 <3,14,34> DELAY_VR_PWRGOOD <13> PLTRST#_NB <3,12> PM_THRMTRIP# <14,34> PM_DPRSLPVR RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 CFG MCH_CFG_3 MCH_CFG_4 MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_8 MCH_CFG_9 MCH_CFG_10 MCH_CFG_11 MCH_CFG_12 MCH_CFG_13 MCH_CFG_14 MCH_CFG_15 MCH_CFG_16 MCH_CFG_17 MCH_CFG_18 MCH_CFG_19 MCH_CFG_20 T30 T75 H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 om CFG9 0 = Reserved 1 = Mobile CPU (Default) 0 = Normal mode 1 = Low Power mode 0 = Reserved Lanes 1 = Normal operation (Default) MUXING Low Power PCI Express M_CLK#0 M_CLK#1 M_CLK#2 M_CLK#3 0 = DMI X2 1 = DMI X4 (Default) DDR CFG8 AW30 BA23 AW25 AW23 CLK Reserved CPU Strap SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4 Configuration 010 = FSB 800MHz 011 = FSB 667MHz DMI CFG6 CFG7 M_CLK0 M_CLK1 M_CLK2 M_CLK3 GRAPHICS VID Reserved DMI X2 Select AV29 BB23 BA25 AV23 AN47 AJ38 AN42 AN46 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 AM47 AJ39 AN41 AN45 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 AJ46 DMI_RXN0 AJ41 DMI_RXN1 AM40 DMI_RXN2 AM44 DMI_RXN3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 AJ47 DMI_RXP0 AJ42 DMI_RXP1 AM39 DMI_RXP2 AM43 DMI_RXP3 D CLK_DREFCLK <2> CLK_DREFCLK# <2> CLK_DREFSSCLK <2> CLK_DREFSSCLK# <2> C CLK_PCIE_3GPLL <2> CLK_PCIE_3GPLL# <2> DMI_TXP[3:0] <13> DMI_RXN[3:0] <13> DMI_RXP[3:0] <13> MCH_GFX_VID_0 MCH_GFX_VID_1 MCH_GFX_VID_2 MCH_GFX_VID_3 R183 *0_4 T41 T42 T43 T44 SUSB# <14,31> +1.25V CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# TEST_1 TEST_2 AM49 AK50 AT43 AN49 AM50 +1.25V_CL_VREF H35 K36 G39 CLK_MCH_OE# G40 A37 GMCH_TEST1 R32 GMCH_TEST2 R422 CL_CLK0 <14> CL_DATA0 <14> MPWROK <14,31> CL_RST#0 <14> MCH_ICH_SYNC# R178 R168 1K/F_4 C559 R420 .1U/10V_4 392/F <14> 0_4 20K_4 CRESTLINE_1p0 A +1.25V SM_RCOMP_VOL C143 4 <16> <16> <16> <16> B E35 A39 C38 B39 E36 R163 C250 C233 1K/F_4 .01U/16V_4 2.2U/6.3V CLK_DREFCLK CLK_DREFCLK# CLK_DREFSSCLK CLK_DREFSSCLK# R409 R529 R531 R411 R532 R533 *4.7K_4 EV@0_4 EV@0_4 *4.7K_4 EV@0_4 EV@0_4 PROJECT : ZD1 0C Delete R410 and R408 0110 Quanta Computer Inc. Size Document Number Date: Monday, May 07, 2007 INTEL FAE suggest PD for external graphics 5 <16> <16> <16> <16> DMI_TXN[3:0] <13> DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VR_EN ME CFG[4:3] CFG5 SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4 MISC Strap Description FSB Frequency Select RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD Pin Name CFG[2:0] P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 .1U/10V_4 D20 ia La pt op .c All strap are sampled with respect to the leading edge of the GMCH power ok signal CFG[17:3] have internal pull-up CFG[18:19] have internal pull-down Any CFG signal strapping option not list below should be left NC pin D 1 3 Rev E GMCH (STRAPPING/OTHER 3/7) 2 Sheet 1 7 of 38 5 4 3 2 1 NB(Memory controller) D CRESTLINE_1p0 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 BJ29 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 SA_RAS# SA_RCVEN# BE18 AY20 SA_WE# BA19 M_A_DM[7:0] <16> M_A_DQS[7:0] <16> M_A_DQS#[7:0] <16> M_A_A[13:0] <16> M_A_A14 <16> M_A_RAS# <16> T35 M_A_WE# <16> w TP_SA_RCVEN# U30E AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 B BL17 AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6 ah as SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 MEMORY M_A_BS0 <16> M_A_BS1 <16> M_A_BS2 <16> M_A_CAS# <16> SYSTEM BB19 BK19 BF29 w .R MEMORY A SA_BS_0 SA_BS_1 SA_BS_2 w B SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SYSTEM C <16> M_B_DQ[63:0] U30D AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11 DDR M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 DDR <16> M_A_DQ[63:0] ia La pt op .c om D SB_BS_0 SB_BS_1 SB_BS_2 AY17 BG18 BG36 M_B_BS0 <16> M_B_BS1 <16> M_B_BS2 <16> M_B_CAS# <16> SB_CAS# BE17 SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_RAS# SB_RCVEN# BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 BE24 AV16 AY18 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 SB_WE# BC17 TP_SB_RCVEN# M_B_DM[7:0] <16> C M_B_DQS[7:0] <16> M_B_DQS#[7:0] <16> M_B_A[13:0] <16> B M_B_A14 <16> M_B_RAS# <16> T26 M_B_WE# <16> CRESTLINE_1p0 A A PROJECT : ZD1 Quanta Computer Inc. Size Document Number Date: Monday, May 07, 2007 Rev E GMCH DDR(4/7) 5 4 3 2 Sheet 1 8 of 38 5 4 3 2 1 NB(Power-1) +1.05V +1.05V_AXG U30G +1.05V_AXG A IV@0_8 R118 IV@0_8 w VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7 AW45 BC39 BE39 BD17 BD4 AW8 AT6 .1U/10V_4 +1.05V_AXG +1.05V_AXG + C521 + C522 IV@330U_7 IV@330U_7 VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50 D C191 C174 C172 C201 C185 IV@.47U IV@1U IV@10U_8 IV@.1U_4 IV@.1U_4 +1.05V_AXG R152 EV@0_4 VSS NCTF +1.05V_AXG R100 .22U/6.3V_4 C239 C235 C262 C203 C220 C263 10U/10V_8 .22U/6.3V_4 .22U/6.3V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28 C POWER VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6 A3 B2 C1 BL1 BL51 A51 +1.05V +1.05V w .R VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 w B VCC GFX R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14 +1.05V .22U/6.3V_4 C214 VSS SCB C 10U/10V_8 C243 VCC AXM 330U/2V_7 10U/10V_8 10U/10V_8 C252 VCC NCTF C249 C238 ah as .1U/10V_4 C247 VCC SM LF + C552 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 VCC SM C254 AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30 VCC GFX NCTF POWER +1.8VSUS U30F AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37 VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19 VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7 AT33 AT31 AK29 AK24 AK23 AJ26 AJ23 VCC AXM NCTF VCC_13 T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31 om R30 0C Delete R156 0104 +1.05V VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83 ia La pt op .c VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC CORE D AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32 B CRESTLINE_1p0 VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7 C156 C154 C151 C171 C264 C257 C291 .1U/10V_4 .1U/10V_4 .22U/6.3V_4 .22U/6.3V_4 .47U/10V 1U/16V 1U/16V A PROJECT : ZD1 CRESTLINE_1p0 Quanta Computer Inc. Size Document Number Date: Wednesday, April 25, 2007 Rev E GMCH Power-1(5/7) 5 4 3 2 Sheet 1 9 of 38 5 4 3 NB(Power-2) 1 CRT/TV Disable/Enable guideline R172 +3V L50 +1.25V 2 INT VGA disable VCCSYNC connect to GND 10UH_8 + C558 470U/2V_7 +3V L47 R162 Ball Enable Disable IV@.1U_4 EV@0_4 VCCA_CRT 3.3V GND VCCA_C_TVO VCCD_CRT 1.5V GND VCCD_TVO IV@BKP1608HS181-T C547 D Ball C246 C557 .1U/10V_4 LVDS Disable/Enable guideline External VGA with EV@part, Internal VGA with IV@ part IV@0 *IV@22U_8 C237 C245 R404 IV@.1U_4 IV@22N_4 EV@0_4 Enable External VGA with EV@part,Internal VGA with IV@ part If SDVO Disable LVDS Disable If SDVO enable LVDS Disable If SDVO enable LVDS enable Disable Signal 3.3V GND VCCD_LVDS GND 1.8V 1.8V 1.5V 1.5V VCCA_LVDS GND GND 1.8V VCCTX_LVDS GND GND 1.8V VCCDQ_CRT 1.5V GND VCCABG_DAC 3.3V GND VCCA_A_TVO 3.3V GND VSSABG_DAC GND GND VCCA_B_TVO 3.3V GND VCC_SYNC GND 3.3V EXTERNAL INTERNAL D R179 IV@0 R186 BKP1608HS181-T EV@0_4 C136 C R106 0.5/F R415 +3V .1U/10V_4 AL2 +1.25VM_VCCA_MPLL AM2 +1.8VSUS_VCC_LVDS A41 C270 B41 IV@1000P_4 K50 K49 C297 .1U/10V_4 R390 +1.25V +1.25VM_VCCA_HPLL +3V_VCCA_PEG_BG 0_8 V1.25M_MPLL_RC 22U/6.3V_8 C132 0 C535 +1.25V_VCCD_PEG_PLL +1.25VM_VCCA_SM C539 C173 C538 4.7U/10V 22U/6.3V_8 1U/16V AW18 AV19 AU19 AU18 AU17 C163 + 100U/10V_7 *22U_8 CRB RECOMMEND 180OHM@100MHz Rdc= 0.09OHM (max) R185 AT22 AT21 AT19 AT18 AT17 AR17 AR16 0 L21 IV@BKP1608HS181-T C265 C253 C258 *1U *1U 22U/6.3V_8 .1U/10V_4 C225 +1.25VM_VCCA_SM_CK +3V C227 R135 IV@.1U_4 IV@22N_4 EV@0_4 +3V_TV_DAC B C229 C228 R136 IV@.1U_4 IV@22N_4 EV@0_4 R173 EV@0_4 R164 IV@0 +1.5V_VCCD_CRT +1.5V_VCCD_TVDAC +1.5V_VCCD_QDAC C540 R105 +1.25V IV@22U_8 R146 IV@22N_4 EV@0_4 INT VGA disable VCCD_TVDAC still +1.5V IV&EV Dis/Enable setting +1.5V R402 +1.25V VCCA_PEG_BG VSSA_PEG_BG VCCA_PEG_PLL VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 POWER VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2 VCCA_SM_CK_1 VCCA_SM_CK_2 C25 B25 C27 B27 B28 A28 VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2 M32 L29 VCCD_CRT VCCD_TVDAC N28 VCCD_QDAC AN2 VCCD_HPLL C142 +1.25V_VCCD_PEG_PLL U48 VCCD_PEG_PLL J41 H42 VCCD_LVDS_1 VCCD_LVDS_2 C298 .1U/10V_4 L23 VSSA_LVDS +1.25VM_MCH_VCCD_HPLL BKP1608HS181-T w C215 IV@.1U_4 VCCA_LVDS R203 CRESTLINE_1p0 +1.05V U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1 C134 VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6 AT23 AU28 AU24 AT29 AT25 AT30 VCC_AXD_NCTF AR29 VCC_AXF_1 VCC_AXF_2 VCC_AXF_3 VCC_DMI B23 B21 A21 2.2U/10V_8 +1.25VM_AXD C137 C202 1U/16V *22U_8 AJ50 +1.25V_VCC_DMI VCC_TX_LVDS A43 VCC_HV_1 VCC_HV_2 C40 B40 330U/2V_7 0 +1.25V R124 C196 C182 1U/16V 10U/10V_8 0 +1.25V C R421 0 +1.25V C560 .1U/10V_4 L46 C192 BK24 +1.8VSUS_VCC_SM_CK BK23 BJ24 BJ23 + C523 2.2U/10V_8 .47U/10V R134 C221 +1.25V_VCC_AXF VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4 1UH_8 C542 .1U/10V_4 22U/6.3V_8 R391 +1.8VSUS +V1.8_SMCK_RC 1/F C541 22U/6.3V_8 IV&EV Dis/Enable setting +1.8VSUS_VCC_TX_LVDS L48 IV@1UH_8 +1.8VSUS VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5 AD51 W50 W51 V49 V50 VCC_RXR_DMI_1 VCC_RXR_DMI_2 AH50 AH51 VTTLF1 VTTLF2 VTTLF3 C144 om VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 +3V_VCC_HV R412 C554 + C553 EV@0_4 IV@1000P_4 IV@220U_7 +1.05_PEG B L22 A7 F2 AH1 C330 C138 C524 C532 + C332 2.2U/10V_8 220U/2.5V_7 .47U/6.3V_4 .47U/6.3V_4 .47U/6.3V_4 91nH +1.05V VCC_RXR_DMI and VCC_PEG connect to+1.05V + C334 1/F_8 220U/2.5V_7 +V1.25S_PEGPLL_FB w C226 IV@10U_8 VCCA_MPLL 0 .1U/10V_4 C543 BC29 BB29 w .R C198 VCCA_HPLL ah as +1.25V U51 VTT VCCA_DPLLB HV .1U/10V_4 +1.8VSUS H49 VTTLF 22U/6.3V_8 VCCA_DPLLA +1.25V_VCCA_DPLLB AXD C145 VSSA_DAC_BG B49 AXF L15 C135 B32 +1.25V_VCCA_DPLLA SM CK BKP1608HS181-T VCCA_DAC_BG PEG IV&EV Dis/Enable setting +3V_VCCA_DAC_BG A30 DMI EV@0_4 PLL R403 IV@22N_4 A LVDS C546 IV@.1U_4 VCCA_CRT_DAC_1 VCCA_CRT_DAC_2 A PEG .1U/10V_4 VCCSYNC A33 B33 A SM C544 C296 L14 +1.25V +3V_VCCA_CRT_DAC ia La pt op .c 470U/2V_7 IV@0 A CK + C338 R396 TV +3V_TV_DAC D TV/CRT 10UH_8 LVDS L24 +1.25V J32 CRT U30H +3V_VCCSYNC C341 2.2U/10V_8 0 C218 C217 D41 .1U/10V_4 22N/16V_4 A +1.05V R414 +1.8VSUS R153 Change to 100 ohm Resistor IV@100 C219 IV@.1U_4 C200 IV@22N_4 R133 1 +1.05V_SD PDZ5.6B +1.8V_VCCD_LVDS C279 C555 R187 IV@1U *IV@10U_8 EV@0_4 A +3V_VCC_HV R515 10 R181 +3V 0 PROJECT : ZD1 C189 Use site for filter cap with Gfx enabled CS 4 C269 +1.25V AND +1.25M shall be +1.5V for Calero Interposer EV@0_4 IV@1U 5 IV@0 2 3 .1U/10V_4 Quanta Computer Inc. Size Document Number Date: Wednesday, April 25, 2007 Rev E GMCH Power-2(6/7) 2 Sheet 1 10 of 38 5 4 3 2 1 NB(Power-3) U30I A D U30J VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50 om C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39 ia La pt op .c AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41 ah as B VSS VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 w .R C VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 w A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16 w D 0C Delete R142,R197,R198,R143 0104 C VSS B CRESTLINE_1p0 A CRESTLINE_1p0 PROJECT : ZD1 Quanta Computer Inc. Size Document Number Date: Wednesday, April 25, 2007 Rev E GMCH Power-3(7/7) 5 4 3 2 Sheet 1 11 of 38 5 4 3 2 1 RTC +VCCRTC RTC_RST# RTC_N02 1 R331 2 3 1K R326 C461 Y3 1.2K +5VPCU R320 47K R314 R280 10M 32.768KHZ Q20 MMBT3904 RTC_N03 10P/50V_4 *RTC_RST C448 U34A 18P/50V_4 CLK_32KX1 CLK_32KX2 AG25 AF24 RTCX1 RTCX2 RTC_RST# AF23 RTCRST# 150K +VCCRTC CN39 R304 1M_4 ICH_INTRUDER# ICH_INTVRMEN LAN100_SLP 1 2 3 4 RTC CONN C SB Strap T69 INTVRMEN ICH_GPIO13 Low = Internal VR disable High = Internal VR enable(Default) ACZ_BCLK ACZ_SYNC ACZ_RST# Low = Internal VR disable High = Internal VR enable(Default) +VCCRTC T83 T61 +VCCRTC <14> ACZ_SDOUT T65 T71 R252 332K/F ICH_INTVRMEN R264 *0_4 <30> SATA_LED# LAN100_SLP R263 *0_4 <24> <24> <24> <24> SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0 <24> <24> <24> <24> SATA_RXN1 SATA_RXP1 SATA_TXN1 SATA_TXP1 HDA ACZ_SYNC A ACZ_BCLK ACZ_RST# 33_4 R307 33_4 R487 33_4 R502 33_4 R489 33 R503 33 R309 R289 33_4 33_4 GPIO33# GPIO34# B24 GLAN_CLK D22 LAN_RSTSYNC C21 B21 C22 LAN_RXD0 LAN_RXD1 LAN_RXD2 D21 E20 C20 LAN_TXD0 LAN_TXD1 LAN_TXD2 AH21 GLAN_COMPI GLAN_COMPO AJ16 AJ15 HDA_BIT_CLK HDA_SYNC AE14 HDA_RST# AJ17 AH17 AH15 AD13 HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 AE13 HDA_SDOUT AE10 AG14 SATA_LED# HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 AF10 SATALED# SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA_TXN0_C SATA_TXP0_C *3900P/25V_4 *3900P/25V_4 SATA_TXN1_C SATA_TXP1_C AG3 AG4 AJ4 AJ3 SATA1RXN SATA1RXP SATA1TXN SATA1TXP AF2 AF1 AE4 AE3 SATA2RXN SATA2RXP SATA2TXN SATA2TXP <2> CLK_PCIE_SATA# <2> CLK_PCIE_SATA AB7 AC6 SATA_CLKN SATA_CLKP R277 AG1 AG2 C627 C626 24.9/F_4 SATA_BIAS L<500mils ACZ_SDOUT_AUDIO <26> ACZ_SDOUT_MDC <26> ACZ_SYNC_AUDIO ACZ_SYNC_MDC <26> <26> LAD0 LAD1 LAD2 LAD3 <22,30,31> <22,30,31> +1.05V <22,30,31> <22,30,31> FWH4/LFRAME# C4 LDRQ0# LDRQ1#/GPIO23 G9 E6 LDRQ0# ICH_GPIO23 AF13 AG26 GATEA20 DPRSTP# DPSLP# AF26 AE26 H_DPRSTP#_R H_DPSLP#_R R261 R255 0_4 0_4 H_PWRGD_R R480 0_4 A20GATE A20M# GLAN_DOCK#/GPIO13 D25 C25 3900P/25V_4 3900P/25V_4 C628 C629 E5 F5 G8 F6 FERR# AD24 CPUPWRGD/GPIO49 AG29 IGNNE# AF27 INIT# INTR RCIN# AE24 AC20 AH14 NMI SMI# AD23 AG28 SATARBIAS# SATARBIAS STPCLK# AA24 AE27 H_THERMTRIP_R TP8 AA23 ICH_TP8 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 DA0 DA1 DA2 AA4 AA1 AB3 PDA0 PDA1 PDA2 Y6 Y5 DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ W4 W3 Y2 Y3 Y1 W5 T53 T50 R254 R260 *56.2/F_4 GATEA20 <31> H_A20M# <3> R475 *56.2/F_4 56.2/F_4 ICH_DPRSTP# <3,7,34> H_DPSLP# <3> H_FERR# <3> C H_PWRGD <3> H_IGNNE# <3> H_INIT# <3> H_INTR <3> RCIN# <31> RCIN# THRMTRIP# DCS1# DCS3# +1.05V LFRAME# <22,30,31> +1.05V H_NMI <3> H_SMI# <3> H_STPCLK# <3> R268 56.2/F_4 R258 T59 PDD[15:0] <24> 24/F R267 *0_4 PM_THRMTRIP# <3,7> Placement close SB L<2" B PDA[2:0] <24> PDCS1# <24> PDCS3# <24> PDIOR# <24> PDIOW# <24> PDDACK# <24> IRQ14 <24> PIORDY <24> PDDREQ <24> ICH8M REV 1.0 w R291 ACZ_SDOUT INTVRMEN LAN100_SLP w ACZ_SDOUT ACZ_SDIN2 ACZ_SDIN3 INTRUDER# AF25 AD21 AF6 AF5 AH5 AH6 w .R R259 332K/F B <26> ACZ_SDIN0 <26> ACZ_SDIN1 AD22 ah as LAN100_SLP FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 om 1K_4 JP5 RTC LPC 1U/10V LAN / GLAN CPU 1U/10V IHDA C506 2 R319 20K_4 IDE R348 C499 SATA 1 RB500V ia La pt op .c R_3VRTC 2 D28 D 1 1 RB500V 2 2 D27 +3VPCU 1 D +3V 0810 UR FAE: RCIN# DOESN'T NEED PU BIT_CLK_AUDIO <26> BIT_CLK_MDC <26> RCIN# R498 *10K_4 GATEA20 R290 8.2K_4 A PROJECT : ZD1 ACZ_RST#_AUDIO <26,27> ACZ_RST#_MDC <26> Quanta Computer Inc. Size Document Number Rev E ICH8M HOST(1/4) Date: 5 4 3 2 Sheet Monday, May 07, 2007 1 12 of 38 5 4 3 2 SB-PCI U34D PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 WLAN <22> <22> <22> <22> PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4 ROBSON <29> <29> <29> <29> PCIE_RXN5 PCIE_RXP5 PCIE_TXN5 PCIE_TXP5 <20> <20> <20> <20> GLAN_RXN GLAN_RXP GLAN_TXN GLAN_TXP GLAN .1U/10V_4 .1U/10V_4 C611 C612 .1U/10V_4 .1U/10V_4 PCIE_TXN1_C PCIE_TXP1_C PERN1 PERP1 PETN1 PETP1 PCIE_TXN2_C PCIE_TXP2_C M27 M26 L29 L28 PERN2 PERP2 PETN2 PETP2 K27 K26 J29 J28 PERN3 PERP3 PETN3 PETP3 C385 C389 .1U/10V_4 .1U/10V_4 PCIE_TXN4_C PCIE_TXP4_C H27 H26 G29 G28 PERN4 PERP4 PETN4 PETP4 C379 C374 .1U/10V_4 .1U/10V_4 PCIE_TXN5_C PCIE_TXP5_C F27 F26 E29 E28 PERN5 PERP5 PETN5 PETP5 C371 C365 .1U/10V_4 .1U/10V_4 GLAN_TXN_SB GLAN_TXP_SB D27 D26 C29 C28 PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP C23 B23 E22 SPI_CLK SPI_CS0# SPI_CS1# D23 F21 SPI_MOSI SPI_MISO USBOC#0 USBOC#1 USBOC#2 USBOC#3 USBOC#4 USBOC#5 USBOC#6 NC_EN# USBOC#8 USBOC#9 C <23> NC_EN# AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18 OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9# <28> AD[0..31] DMI0RXN DMI0RXP DMI0TXN DMI0TXP V27 V26 U29 U28 DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 <7> <7> <7> <7> DMI1RXN DMI1RXP DMI1TXN DMI1TXP Y27 Y26 W29 W28 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 <7> <7> <7> <7> DMI2RXN DMI2RXP DMI2TXN DMI2TXP AB26 AB25 AA29 AA28 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 <7> <7> <7> <7> DMI3RXN DMI3RXP DMI3TXN DMI3TXP AD27 AD26 AC29 AC28 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 <7> <7> <7> <7> DMI_CLKN DMI_CLKP T26 T25 CLK_PCIE_ICH# <2> CLK_PCIE_ICH <2> DMI_ZCOMP DMI_IRCOMP Y23 Y24 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2 USBRBIAS# USBRBIAS F2 F3 USB USBP9USBP9+ USBP0USBP0+ USBP1USBP1+ USBP2USBP2+ USBP3USBP3+ USBP4USBP4+ USBP5USBP5+ USBP6USBP6+ USBP7USBP7+ USBP8USBP8+ T57 T58 Low = A16 swap override enabled High = Default R217 24.9/F_4 *1K_4 USB USB USB NEW CARD C457 PLT_RST-R# 5 .1U/10V_4 U15 2 4 3 PIRQA# PIRQB# PIRQC# PIRQD# REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3# REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 A4 D7 E18 C18 B19 F18 A11 C10 C/BE0# C/BE1# C/BE2# C/BE3# C17 E15 F16 E17 IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# C8 D9 G6 D16 A7 B7 F10 C16 C9 A17 IRDY# PLTRST# PCICLK PME# AG24 B10 G7 PLT_RST-R# R481 PCLK_ICH F8 G11 F12 B3 INTE# INTF# INTG# INTH# Interrupt I/F PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5 REQ0# <28> GNT0# <28> T48 T51 T47 D CBE0# CBE1# CBE2# CBE3# <28> <28> <28> <28> IRDY# <28> PAR <28> PCIRST# <22,28> DEVSEL# <28> PERR# <28> DEVSEL# PERR# LOCK# SERR# STOP# TRDY# FRAME# SERR# <28> STOP# <28> TRDY# <28> FRAME# <28> 0 R211 PLTRST#_NB <7> PCLK_ICH <2> PCI_PME# <28> *0_4 CRT_SENSE# <19,31> C 3G CARD R226 22.6/F +3V +3V RP33 6 7 8 9 10 RP35 5 4 3 2 1 DEVSEL# INTF# INTG# SERR# INTC# INTB# +3V 6 7 8 9 10 8.2KX8 5 4 3 2 1 STOP# REQ1# FRAME# REQ2# 8.2KX8 +3V_S5 +3V RP38 USBOC#1 USBOC#5 NC_EN# USBOC#0 +3V_S5 6 7 8 9 10 B RP34 5 4 3 2 1 TRDY# LOCK# IRDY# PERR# USBOC#4 USBOC#6 USBOC#3 USBOC#2 +3V 6 7 8 9 10 8.2KX8 5 4 3 2 1 INTE# INTD# REQ3# INTA# 8.2KX8 PLTRST# <14,17,20,22..24,29..31> 1 TC7SH08FU A F9 B5 C5 A10 PCI ICH8M REV 1.0 w .R +3V w +3V_S5 w +3V_S5 8.2K_4 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CCD +3V 8.2K_4 U34B D20 E19 D19 A20 D17 A21 A19 C19 A18 B16 A12 E16 A14 G16 A15 B6 C11 A9 D11 B12 C12 D10 C7 F13 E11 E13 E12 D8 A6 E8 D6 A3 MINI PCIE INTH# USBOC#9 R491 INTA# INTB# INTC# INTD# <28> INTA# <28> INTB# BLUETOOTH REQ0# USBOC#8 R248 DMI_IRCOMP_R<500mils USB ah as A16 SWAP Override strap GNT3# <25> <25> <22> <22> <25> <25> <25> <25> <21> <21> <23> <23> <22> <22> <18> <18> <22> <22> USB_RBIAS_PN 1.USB_RBIAS_PN<500mils 2.Avoid routing next to clock/high speed signals B R474 DMI_IRCOMP_R ICH8M REV 1.0 PCI_GNT#3 +1.5V AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 ia La pt op .c TV CARD <22> <22> <22> <22> C405 C397 P27 P26 N29 N28 PCI-Express Direct Media Interface PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1 SPI D NEW CARD <23> <23> <23> <23> om SB-PCIE/USB/DMI 1 R295 A 100K PROJECT : ZD1 Quanta Computer Inc. Size Document Number Rev E ICH8M PCIE\PCI\USB(2/4) Date: 5 4 3 2 Sheet Monday, May 07, 2007 1 13 of 38 R306 R490 <2> PM_STPPCI# <2> PM_STPCPU# +3V 0_4 0_4 <28,31> CLKRUN# <20,22,31> PCIE_WAKE# <28,30,31> SERIRQ <3,17> THERM_ALERT# U36 1 2 3 <34> VR_PWRGD_CK410# 5 SUS_STAT#/LPCPD# SYS_RESET# AG12 BMBUSY#/GPIO0 SMB_ALERT# AG22 SMBALERT#/GPIO11 PM_STPPCI_ICH# PM_STPCPU_ICH# AE20 AG18 STP_PCI#/GPIO15 STP_CPU#/GPIO25 CLKRUN# AH11 CLKRUN#/GPIO32 PCIE_WAKE# SERIRQ THERM_ALERT# AE17 AF12 AC13 WAKE# SERIRQ THRM# 4 VR_PWRGD_CLKEN AJ20 VRMPWRGD AJ22 TP7 AJ8 AJ9 AH9 AE16 AC19 AG8 AH12 AE11 AG10 AH25 AD16 AG13 AF9 AJ11 AD10 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 GPIO12 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 TP7 T79 NC7SZ04 <31> KBSMI# <22,23,31> LID591# BAS316 D43 BAS316 <31> SCI# D42 T80 T62 KBSMI#_ICH LID591#_ICH ICH_GPIO7 SCI# ICH_GPIO12 BOARD_ID0 BOARD_ID1 BOARD_ID3 ICH_GPIO22 ICH_GPIO27 ICH_GPIO28 SATACLKREQ# ICH_GPIO38 ICH_GPIO39 ICH_GPIO48 T70 T85 T63 +3V <2> SATACLKREQ# R500 T66 *10K_4 C R497 <7> MCH_ICH_SYNC# internal PD 0_4 T68 <26> PCSPK PCSPK SATA GPIO SMB F4 AD15 <7> PM_BMBUSY# R317 *10K_4 .1U/10V_4 C475 AF17 LPC_PD# SYS_RST# RI# AD9 SPKR MCH_ICH_SYNC#_R AJ13 MCH_SYNC# ICH_TP3 AJ21 TP3 ICH8M REV 1.0 CLK14 CLK48 AJ12 AJ10 AF11 AG11 GPIO21 BOARD_ID2 GPIO36 GPIO37 AG9 G5 14M_ICH CLKUSB_48 T81 T67 T72 14M_ICH <2> CLKUSB_48 <2> SUSCLK D3 SLP_S3# SLP_S4# SLP_S5# AG23 AF21 AD18 SLP_S3# SLP_S4# SLP_S5# S4_STATE#/GPIO26 AH27 ICH_GPIO26 PWROK AE23 ICH_PWROK DPRSLPVR/GPIO16 AJ14 PM_DPRSLPVR_R BATLOW# AE21 PM_BATLOW#_R R303 R288 100/F_4 100/F_4 SUSB# <7,31> SUSC# <31> T64 Since your CPU VRM has no DPRSTP# pin, connect PM_DPRSLPVR to IMVP6 is correct T77 PWRBTN# C2 DNBSWON# LAN_RST# AH20 PM_LAN_ENABLE_R RSMRST# AG27 PM_RSMRST#_R R501 100/F_4 DNBSWON# <31> R494 0_4 PLTRST# <13,17,20,22..24,29..31> E1 CK_PWRGD <2> CLPWROK E3 MPWROK <7,31> AJ25 CL_CLK0 CL_CLK1 F23 AE18 CL_CLK0 <7> CL_CLK1 <22> CL_DATA0 CL_DATA1 F22 AF19 CL_DATA0 <7> CL_DATA1 <22> CL_VREF0 CL_VREF1 D24 AH23 CL_RST# AJ23 MEM_LED/GPIO24 ME_EC_ALERT/GPIO10 EC_ME_ALERT/GPIO14 WOL_EN/GPIO9 AJ27 AJ24 AF22 AG19 R286 453/F_4 RSVD 1 0 1 1 Normal opration(Default) 10K_4 R269 10K_4 R225 R294 SMB_DATA_ME 10_4 *33_4 PCLK_SMB R496 2.2K_4 PDAT_SMB R262 2.2K_4 SMB_ALERT# R287 10K_4 PCIE_WAKE# R265 1K_4 Enter XOR Chain 1 0 R250 C380 C462 10P/50V_4 *10P_4 PM_BATLOW#_R R249 Set PCIE port config bit 1 B Controller Link 1 VREF for IAMT support only R256 10K_4 ICH_GPIO10 R519 10K_4 R321 *1K ACZ_SDOUT <12> ICH_TP3 PCSPK R257 KBSMI#_ICH R522 10K_4 LID591#_ICH R534 10K_4 <31> PWROK_EC R479 5 2 100K_4 3 A PWROK_EC 5 C620 DELAY_VR_PWRGOOD 1 <3,7,34> DELAY_VR_PWRGOOD w +3V *10K_4 INTEL FAE (08/17) "Add RSMRST# isolation (important!!! See ww22 Santa Rosa MoW)" +3VSUS R51 ICH_GPIO39 R485 10K_4 Q6 MMBT3906 INTEL CRB SHOW IT PM_RSMRST#_R PM_LAN_ENABLE_R R493 *0_4 3 4.7K_4 1 RSMRST# <31> TO ICH8 B FROM uR(EC) R61 10K_4 DISABLE LAN: STUFF +3V ICH_GPIO14 R520 10K_4 ICH_GPIO9 R278 100K_4 VR_PWRGD_CLKEN R492 100K_4 ICH_PWROK R266 10K_4 SATACLKREQ# w R495 *1K_4 Low = Default High = No Reboot +3V 8.2K_4 SYS_RST# w .R +3V C 2 0 0 *10K_4 SMB_CLK_ME .1U/10V_4 R310 10K_4 THERM_ALERT# R251 8.2K_4 SERIRQ R292 10K_4 CLKRUN# R484 8.2K_4 SCI# R488 10K_4 D6 BAV99 3 1 Description 10K_4 R305 C382 R213 453/F_4 .1U/10V_4 T78 T82 T84 2 HDA_SDOUT R272 CL_RST#1 ah as ICH_RSV0 RI# R210 3.24K/F C458 CL_RST#0 <7> ICH_GPIO24 ICH_GPIO10 ICH_GPIO14 ICH_GPIO9 HDA_SPKR 14M_ICH +3V CL_VREF0_SB CL_VREF1_SB No Reboot strap CLKUSB_48 +3V_S5 R299 3.24K/F +3V_S5 XOR Chain Entrance Strap If no use internal LAN MAC connect LAN_RST# to PLTRST# Use internal LAN MAC connect LAN_RST# to RSMRST# should go high no sooner than 10 ms after both VccLAN3_3 and VccLAN1_5 have reached their nominal voltages. PM_DPRSLPVR <7,34> CK_PWRGD SLP_M# D 2 D RI# SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37 D5 BAV99 3 R64 2.2K_4 1 <3> SYS_RST# R504 *10K_4 SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1 1 ia La pt op .c T49 2 Clocks +3V AJ26 AD19 AG21 AC17 AE19 Power MGT PCLK_SMB PDAT_SMB CL_RST#1 SMB_CLK_ME SMB_DATA_ME <2,16,22,23> PCLK_SMB <2,16,22,23> PDAT_SMB <22> CL_RST#1 SYS GPIO SB-GPIO CRB STP_PCI# PU is no stuff. CRB STP_CPU# always keeps high to ensure ME alive in M1 state. (CLK_MCH_BCLK/# must keep alive to make ME work) I think there will be update for this design, I suggest you to keep PU and 0Ω isolation resistors for this signal. 3 U34C om 4 MISC GPIO Controller Link 5 .1U/16V_4 U14 4 ICH_PWROK TC7SH08FU 4 +3V Board ID ID3 ID2 0 0 ID1 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 3 +3V +3V +3V ID0 R308 *10K_4 BOARD_ID3 R293 10K_4 R506 *10K_4 BOARD_ID2 R483 10K_4 R486 A R505 *10K_4 *10K_4 BOARD_ID1 R499 BOARD_ID0 PROJECT : ZD1 R482 10K_4 Quanta Computer Inc. 10K_4 Size Document Number Date: Monday, May 07, 2007 Rev E ICH8M GPIO(3/4) 2 Sheet 1 14 of 38 5 4 +3V .1U/10V_4 .1U/10V_4 +5VREF_SUS_SB +1.5V_B L25 FBMJ2125HS420-T_8 +1.5V Intel use 0.5UH inductor + C395 C414 C413 C388 220U/2.5V_710U/10V_8 10U/10V_8 2.2U/6.3V +1.5V C455 C456 10U/6.3V 1U/16V C C433 1U/16V B C377 AJ6 VCCSATAPLL AE7 AF7 AG7 AH7 AJ7 VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05] AC1 AC2 AC3 AC4 AC5 VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08] VCC1_5_A[09] VCC1_5_A[10] AC10 AC9 VCC1_5_A[11] VCC1_5_A[12] AA5 AA6 VCC1_5_A[13] VCC1_5_A[14] G12 G17 H7 VCC1_5_A[15] VCC1_5_A[16] VCC1_5_A[17] AC7 AD7 R231 0 W23 VCC1_5_A[25] F19 G20 VCCLAN3_3[1] VCCLAN3_3[2] +1.5V_VCCGLANPLL A24 VCCGLANPLL 1_8 +1.5V_GLANP L52 +1.5V_GLAN A26 A27 B26 B27 B28 VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] VCCGLAN1_5[5] B25 VCCGLAN3_3 1UH_12 A C573 C576 10U/6.3V 2.2U/6.3V GLAN POWER .1U/10V_4 +1.5V VCC1_5_A[20] VCC1_5_A[21] VCC1_5_A[22] VCC1_5_A[23] VCC1_5_A[24] VCCLAN1_05[1] VCCLAN1_05[2] +3V_VCCLAN C386 R445 F1 L6 L7 M6 M7 F17 G18 w +3V +1.5V VCCUSBPLL U34E VCCDMIPLL_ICH 1UH_12 C615 L54 +1.5V_ICH +1.25V +1.25V_DMI R471 1_8 C616 .01U/16V_4 10U/6.3V R478 +1.05V 0_8 C619 R29 AE28 AE29 V_CPU_IO[1] V_CPU_IO[2] AC23 AC24 VCC3_3[01] AF29 VCC3_3[02] AD2 VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06] AC8 AD8 AE8 AF8 VCC3_3[07] VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] AA3 U7 V7 W1 W6 W7 Y7 VCC3_3[14] VCC3_3[15] VCC3_3[16] VCC3_3[17] VCC3_3[18] VCC3_3[19] VCC3_3[20] VCC3_3[21] VCC3_3[22] VCC3_3[23] VCC3_3[24] A8 B15 B18 B4 B9 C15 D13 D5 E10 E7 F11 R243 0 10U/10V_8 C369 C367 +VCCSUSHDA VCCSUS1_05[1] VCCSUS1_05[2] J6 AF20 TP_VCCSUS1_05_ICH_1 TP_VCCSUS1_05_ICH_2 AC16 TP_VCCSUS1_5_ICH_1 AC18 AC21 AC22 AG20 AH28 VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] P6 P7 C1 N7 P1 P2 P3 P4 P5 R1 R3 R5 R6 .1U/10V_4 4.7U/10V C436 C437 .1U/10V_4 .1U/10V_4 C378 .1U/10V_4 .1U/10V_4 .1U/10V_4 AD11 VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04] VCCSUS3_3[05] VCCSUS3_3[06] .1U/10V_4 .1U/10V_4 VCCSUSHDA J7 C423 C420 +3V_1.5V_HDA_IO_ICH C3 C431 +3V AC12 VCCSUS3_3[01] C430 +1.05V_V_CPU_IO VCCHDA VCCSUS1_5[2] VCC1_5_A[18] VCC1_5_A[19] D1 w .1U/10V_4 .1U/10V_4 .1U/10V_4 +1.5V VCC_DMI[1] VCC_DMI[2] VCCSUS1_5[1] USB CORE C403 C396 C398 VCCDMIPLL w .R .1U/10V_4 VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] ATX 1U/16V V5REF_SUS AA25 AA26 AA27 AB27 AB28 AB29 D28 D29 E25 E26 E27 F24 F25 G24 H23 H24 J23 J24 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25 W25 Y25 ARX C426 G4 VCCA3GP +1.5V_APLL L29 10UH_8 +1.05V om C419 V5REF[1] V5REF[2] A13 B13 C13 C14 D14 E14 F14 G14 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 ia La pt op .c C391 A16 T7 VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26] VCC1_05[27] VCC1_05[28] ah as +5VREF_SB VCCRTC CORE 100 AD25 VCCP_CORE D R244 1 U34F IDE PDZ5.6B +5V +1.05V C434 VCCPSUS 10 1 R227 1 PDZ5.6B +5V_S5 C424 1U/6.3V_4.1U/10V_4.1U/10V_4 PCI C427 D19 VCCPUSB D18 2 +VCCRTC 2 2 +3V_S5 3 R245 *0 +1.5V_S5 C422 R517 0 +3V_S5 .1U/16V Can be connect to +3V_S5 or +1.5V_S5 R516 0 +3V R247 *0 +1.5V C429 Can be connect to or +1.5V .1U/10V_4 +3V +3V_S5 TP_VCCSUS1_5_ICH_2 C368 C366 .1U/10V_4 .022U/16V_4 +V3.3A_USB_ICH R241 0_8 C411 4.7U/10V TP_VCCSUS1_05_ICH_1 TP_VCCSUS1_05_ICH_2 VCCCL1_05 G22 TP_VCCCL1_05_ICH VCCCL1_5 A22 VCCCL1_5_INT_ICH VCCCL3_3[1] VCCCL3_3[2] F20 G21 +V3.3M_ICH C392 C454 TP_VCCSUS1_5_ICH_1 TP_VCCSUS1_5_ICH_2 TP_VCCCL1_05_ICH C574 C575 1U/16V *.1U_4 .1U/16V .1U/16V T60 T54 T52 A23 A5 AA2 AA7 A25 AB1 AB24 AC11 AC14 AC25 AC26 AC27 AD17 AD20 AD28 AD29 AD3 AD4 AD6 AE1 AE12 AE2 AE22 AD1 AE25 AE5 AE6 AE9 AF14 AF16 AF18 AF3 AF4 AG5 AG6 AH10 AH13 AH16 AH19 AH2 AF28 AH22 AH24 AH26 AH3 AH4 AH8 AJ5 B11 B14 B17 B2 B20 B22 B8 C24 C26 C27 C6 D12 D15 D18 D2 D4 E21 E24 E4 E9 F15 E23 F28 F29 F7 G1 E2 G10 G13 G19 G23 G25 G26 G27 H25 H28 H29 H3 H6 J1 J25 J26 J27 J4 J5 K23 K28 K29 K3 K6 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] K7 L1 L13 L15 L26 L27 L4 L5 M12 M13 M14 M15 M16 M17 M23 M28 M29 M3 N1 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 N4 N5 N6 P12 P13 P14 P15 P16 P17 P23 P28 P29 R11 R12 R13 R14 R15 R16 R17 R18 R28 R4 T12 T13 T14 T15 T16 T17 T2 U12 U13 U14 U15 U16 U17 U23 U26 U27 U3 U5 V13 V15 V28 V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5 AB6 AD5 U4 W24 VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12] A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29 D C B ICH8M REV 1.0 A ICH8M REV 1.0 +1.5V R452 0 PROJECT : ZD1 C577 R228 4.7U/10V +3V R209 0 0 +3V Quanta Computer Inc. +3V_GLAN Size Document Number Date: Wednesday, April 25, 2007 Rev E ICH8M Power(4/4) 5 4 3 2 Sheet 1 15 of 38 +SMDDR_VREF +SMDDR_VTERM 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 M_A_DQS#1 M_A_DQS1 M_A_DQ11 M_A_DQ14 M_A_DQ16 M_A_DQ21 M_A_DQS#2 M_A_DQS2 M_A_DQ19 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DM3 M_A_DQ31 M_A_DQ30 M_CKE0 C M_A_BS2 M_A_A12 M_A_A9 M_A_A8 M_A_A5 M_A_A3 M_A_A1 M_A_A10 M_A_BS0 M_A_WE# M_A_CAS# M_CS#1 M_ODT1 M_A_DQ37 M_A_DQ33 M_A_DQS#4 M_A_DQS4 M_A_DQ34 M_A_DQ35 M_A_DQ40 M_A_DQ41 M_A_DM5 M_A_DQ53 M_A_DQ48 M_A_DQS#6 M_A_DQS6 M_A_DQ50 M_A_DQ51 M_A_DQ56 M_A_DQ61 M_A_DM7 M_A_DQ62 M_A_DQ59 PDAT_SMB PCLK_SMB +3V VSS20 DQ20 DQ21 VSS6 NC3 DM2 VSS21 DQ22 DQ23 VSS24 DQ28 DQ29 VSS25 DQS#3 DQS3 VSS10 DQ30 DQ31 VSS8 CKE1 VDD8 A15 A14 VDD11 A11 A7 A6 VDD4 A4 A2 A0 VDD12 BA1 RAS# S0# VDD1 ODT0 A13 VDD6 NC2 VSS12 DQ36 DQ37 VSS28 DM4 VSS42 DQ38 DQ39 VSS55 DQ44 DQ45 VSS43 DQS#5 DQS5 VSS56 DQ46 DQ47 VSS44 DQ52 DQ53 VSS57 CK1 CK1# VSS45 DM6 VSS32 DQ54 DQ55 VSS35 DQ60 DQ61 VSS7 DQS#7 DQS7 VSS36 DQ62 DQ63 VSS13 SA0 SA1 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DDR2_SODIMM_H5.2_RVS A SO-DIMM0 M_A_DQ26 M_A_DQ27 M_CKE1 M_A_A14 R180 M_A_DQ6 M_A_DQ7 M_A_DQ12 M_A_DQ13 M_A_DM1 M_CLK0 M_CLK#0 M_A_DQ10 M_A_DQ15 M_A_DQ20 M_A_DQ17 PM_EXTTS#0 M_A_DM2 M_A_DQ18 M_A_DQ22 M_A_DQ28 M_A_DQ29 M_A_DQS#3 M_A_DQS3 +1.8VSUS M_B_DQ0 M_B_DQ1 M_B_DQS#0 M_B_DQS0 M_B_DQ3 M_B_DQ2 M_B_DQ8 M_B_DQ9 M_B_DQS#1 M_B_DQS1 M_B_DQ10 M_B_DQ11 M_B_DQS#2 M_B_DQS2 M_B_DQ19 M_B_DQ23 M_B_DQ25 M_B_DQ24 M_B_DM3 M_B_DQ26 M_B_DQ27 M_A_A14 M_B_BS2 M_A_A11 M_A_A7 M_A_A6 M_B_A12 M_B_A9 M_B_A8 +SMDDR_VTERM .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 C169 C190 C175 C234 C222 C275 C231 C274 C277 C176 C276 C178 C278 C177 M_A_A4 M_A_A2 M_A_A0 M_A_BS1 M_A_RAS# M_CS#0 M_ODT0 M_A_A13 M_A_DQ36 M_A_DQ32 +SMDDR_VREF M_A_DM4 M_A_DQ38 M_A_DQ39 M_A_DQ44 M_A_DQ45 C337 1U/10V_4 M_CLK1 M_CLK#1 M_A_DM6 C123 M_A_DQ60 M_A_DQ57 C127 M_A_DQS#7 M_A_DQS7 A_SA0 A_SA1 SMbus address A0 R99 R94 M_B_A10 M_B_BS0 M_B_WE# M_B_CAS# M_CS#3 M_ODT3 M_B_DQ32 M_B_DQ36 M_B_DQS#4 M_B_DQS4 M_B_DQ39 M_B_DQ38 M_B_DQ44 M_B_DQ45 M_B_DM5 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 +3V M_A_DQ54 M_A_DQ55 M_B_A5 M_B_A3 M_B_A1 330U/2.5V_7 C244 C260 C194 C184 C266 C212 C242 C224 C248 M_A_DQ52 M_A_DQ49 A_SA0 A_SA1 .1U/16V_4 C545 M_A_DQ46 M_A_DQ42 M_A_DQ58 M_A_DQ63 C333 +1.8VSUS M_A_DQS#5 M_A_DQS5 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 M_B_DQ17 M_B_DQ20 M_CKE2 56_4 +1.8VSUS .1U/16V_4 1U/10V_4 M_B_DQ47 M_B_DQ43 M_B_DQ48 M_B_DQ49 M_B_DQS#6 M_B_DQS6 M_B_DQ50 M_B_DQ51 M_B_DQ56 M_B_DQ57 M_B_DM7 M_B_DQ58 M_B_DQ59 10K_4 10K_4 +SMDDR_VTERM 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 56X2_4 2 4 CN24 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 VREF VSS47 DQ0 DQ1 VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50 VSS46 DQ4 DQ5 VSS15 DM0 VSS5 DQ6 DQ7 VSS16 DQ12 DQ13 VSS17 DM1 VSS53 CK0 CK0# VSS41 DQ14 DQ15 VSS54 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD) VSS20 DQ20 DQ21 VSS6 NC3 DM2 VSS21 DQ22 DQ23 VSS24 DQ28 DQ29 VSS25 DQS#3 DQS3 VSS10 DQ30 DQ31 VSS8 CKE1 VDD8 A15 A14 VDD11 A11 A7 A6 VDD4 A4 A2 A0 VDD12 BA1 RAS# S0# VDD1 ODT0 A13 VDD6 NC2 VSS12 DQ36 DQ37 VSS28 DM4 VSS42 DQ38 DQ39 VSS55 DQ44 DQ45 VSS43 DQS#5 DQS5 VSS56 DQ46 DQ47 VSS44 DQ52 DQ53 VSS57 CK1 CK1# VSS45 DM6 VSS32 DQ54 DQ55 VSS35 DQ60 DQ61 VSS7 DQS#7 DQS7 VSS36 DQ62 DQ63 VSS13 SA0 SA1 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 M_B_DQ31 M_B_DQ30 RP20 1 3 RP19 M_B_A3 1 M_B_A5 3 RP23 M_B_A4 1 M_B_A6 3 RP26 M_B_A7 1 M_B_A11 3 RP29 M_B_A9 1 M_B_A12 3 RP18 M_B_BS1 1 M_B_A2 3 RP7 M_ODT2 1 M_B_A13 3 RP16 M_B_BS0 1 M_B_WE# 3 RP32 M_CKE2 1 M_B_BS2 3 RP12 M_B_CAS# 1 M_B_A10 3 RP15 M_CS#2 1 M_B_RAS# 3 RP30 M_CKE3 1 M_B_A8 3 RP8 M_CS#3 1 M_ODT3 3 M_CKE3 M_B_A14R175 M_B_DQ4 M_B_DQ5 M_B_DM0 M_B_DQ6 M_B_DQ7 M_B_DQ12 M_B_DQ13 M_B_DM1 M_CLK2 M_CLK#2 M_B_DQ15 M_B_DQ14 M_B_DQ16 M_B_DQ21 PM_EXTTS#1 M_B_DM2 M_B_DQ18 M_B_DQ22 M_B_A0 M_B_A1 PDAT_SMB PCLK_SMB +3V M_B_DQ29 M_B_DQ28 M_B_DQS#3 M_B_DQS3 56_4 M_B_A14 M_B_A11 M_B_A7 M_B_A6 M_B_A4 M_B_A2 M_B_A0 +1.8VSUS R204 R202 *1K_4 *1K_4 D M_ODT2 M_B_A13 M_B_DQ37 M_B_DQ33 <7> PM_EXTTS#1 PM_EXTTS#1 <7> PM_EXTTS#0 PM_EXTTS#0 PCLK_SMB M_CS#[3:0] <7> M_CS#[3:0] M_ODT[3:0] <7> M_ODT[3:0] M_CKE[3:0] <7> M_CKE[3:0] M_CLK#[3:0] <7> M_CLK#[3:0] M_CLK[3:0] <7> M_CLK[3:0] M_A_CAS# <8> M_A_CAS# M_A_RAS# <8> M_A_RAS# M_A_WE# <8> M_A_WE# M_B_DM4 +SMDDR_VREF M_B_DQ34 M_B_DQ35 C335 M_B_DQ41 M_B_DQ40 .1U/16V_4 C336 +1.8VSUS M_B_DQS#5 M_B_DQS5 C519 M_B_DQ46 M_B_DQ42 C259 C216 C197 C267 C223 C204 C211 C195 C268 M_B_DQ52 M_B_DQ53 M_CLK3 M_CLK#3 M_B_DM6 M_A_BS[2:0] <8> M_A_BS[2:0] M_A_DM[7:0] <8> M_A_DM[7:0] M_A_DQS#[7:0] <8> M_A_DQS#[7:0] 1U/10V_4 330U/2.5V_7 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 M_A_DQS[7:0] <8> M_A_DQS[7:0] M_A_A[14:0] <8> M_A_A[14:0] B M_A_DQ[63:0] <8> M_A_DQ[63:0] M_B_CAS# <8> M_B_CAS# M_B_RAS# <8> M_B_RAS# M_B_WE# <8> M_B_WE# M_B_BS[2:0] <8> M_B_BS[2:0] M_B_DQ54 M_B_DQ55 +3V M_B_DQ60 M_B_DQ61 C125 C122 M_B_DQS#7 M_B_DQS7 .1U/16V_4 M_B_DM[7:0] <8> M_B_DM[7:0] M_B_DQS#[7:0] <8> M_B_DQS#[7:0] M_B_DQS[7:0] <8> M_B_DQS[7:0] 1U/10V_4 M_B_A[14:0] <8> M_B_A[14:0] M_B_DQ[63:0] <8> M_B_DQ[63:0] M_B_DQ62 M_B_DQ63 C PDAT_SMB <2,14,22,23> PCLK_SMB +SMDDR_VTERM .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 C283 C183 C199 C251 C187 C240 C230 C271 C272 C170 C255 C236 C261 C273 M_B_BS1 M_B_RAS# M_CS#2 B_SA0 B_SA1 +SMDDR_VREF <2,14,22,23> PDAT_SMB + M_A_DQ47 M_A_DQ43 VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD) M_A_DM0 + B 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 M_A_A10 M_A_BS0 w .R M_A_DQ8 M_A_DQ9 RP17 1 3 RP22 M_A_A2 1 M_A_A4 3 RP21 M_A_A5 1 M_A_A3 3 RP25 M_A_A6 1 M_A_A7 3 RP24 M_A_A8 1 M_A_A1 3 RP27 M_A_A11 1 M_A_A9 3 RP6 M_ODT0 1 M_A_A13 3 RP14 M_A_RAS# 1 M_A_BS1 3 RP31 M_A_A12 1 M_A_BS2 3 RP13 M_A_WE# 1 M_A_CAS# 3 RP10 M_CS#0 1 M_A_A0 3 RP28 M_CKE0 1 M_CKE1 3 RP9 M_CS#1 1 M_ODT1 3 M_A_DQ4 M_A_DQ5 w D M_A_DQ2 M_A_DQ3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 w M_A_DQS#0 M_A_DQS0 VSS46 DQ4 DQ5 VSS15 DM0 VSS5 DQ6 DQ7 VSS16 DQ12 DQ13 VSS17 DM1 VSS53 CK0 CK0# VSS41 DQ14 DQ15 VSS54 PC4800 DDR2 SDRAM SO-DIMM (200P) M_A_DQ0 M_A_DQ1 VREF VSS47 DQ0 DQ1 VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50 1 om +1.8VSUS CN25 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 PC4800 DDR2 SDRAM SO-DIMM (200P) +1.8VSUS 3 ah as +SMDDR_VREF 4 ia La pt op .c 5 +3V B_SA1 B_SA0 R96 R95 10K_4 10K_4 DDR2_SODIMM_H9.2_RVS Close to DIMM0 SO-DIMM1 SMbus address A2 Close to DIMM1 A PROJECT : ZD1 Quanta Computer Inc. Size Document Number Rev E DDRII SO-DIMM Date: 5 4 3 2 Monday, May 07, 2007 Sheet 1 16 of 38 4 3 2 1 0C Change power name from +1.8V to +1.8V_MXM 0108 C <18> EV_LVDS_UTX#0 <18> EV_LVDS_UTX#1 <18> EV_LVDS_UTX#2 <18> EV_LVDS_UTX0 <18> EV_LVDS_UTX1 <18> EV_LVDS_UTX2 PEG_RXP[15:0] <6> <18> EV_LVDS_LTX#0 <18> EV_LVDS_LTX#1 <18> EV_LVDS_LTX#2 <18> EV_LVDS_LTX0 <18> EV_LVDS_LTX1 <18> EV_LVDS_LTX2 <18> EV_LVDS_VDDEN <23> EV_LVDS_BLON <18> EV_LVDS_BL_BRGHT <18> EV_LVDS_DDCCLK <18> EV_LVDS_DDCDAT PEG_TXN[15:0] PEX_TX0# PEX_TX1# PEX_TX2# PEX_TX3# PEX_TX4# PEX_TX5# PEX_TX6# PEX_TX7# PEX_TX8# PEX_TX9# PEX_TX10# PEX_TX11# PEX_TX12# PEX_TX13# PEX_TX14# PEX_TX15# 118 112 106 100 94 88 82 76 70 64 58 52 46 40 34 28 PEG_TXN[15:0] <6> PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 <19> EV_CRT_HSYNC <19> EV_CRT_VSYNC <19> EV_CRT_R <19> EV_CRT_G <19> EV_CRT_B <19> EV_CRT_DDCCLK <19> EV_CRT_DDCDAT <19> EV_TV_Y/G <19> EV_TV_C/R PEG_TXP[15:0] 120 114 108 102 96 90 84 78 72 66 60 54 48 42 36 30 PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15 PEG_TXP[15:0] <6> 122 26 <19> EV_TV_COMP 172 166 160 154 LVDS_UTX0# LVDS_UTX1# LVDS_UTX2# LVDS_UTX3# EV_LVDS_UTX0 EV_LVDS_UTX1 EV_LVDS_UTX2 174 168 162 156 LVDS_UTX0 LVDS_UTX1 LVDS_UTX2 LVDS_UTX3 EV_LVDS_LCLK# EV_LVDS_LCLK 178 180 LVDS_LCLK# LVDS_LCLK EV_LVDS_LTX#0 EV_LVDS_LTX#1 EV_LVDS_LTX#2 202 196 190 184 LVDS_LTX0# LVDS_LTX1# LVDS_LTX2# LVDS_LTX3# EV_LVDS_LTX0 EV_LVDS_LTX1 EV_LVDS_LTX2 204 198 192 186 LVDS_LTX0 LVDS_LTX1 LVDS_LTX2 LVDS_LTX3 EV_LVDS_VDDEN EV_LVDS_BLON EV_LVDS_BL_BRGHT 212 216 214 LVDS_PPEN LVDS_BLEN LVDS_BL_BRGHT EV_LVDS_DDCCLK EV_LVDS_DDCDAT 210 208 DDCC_CLK DDCC_DAT EV_CRT_HSYNC EV_CRT_VSYNC 139 141 VGA_HSYNC VGA_VSYNC EV_CRT_R EV_CRT_G EV_CRT_B 136 140 144 VGA_RED VGA_GREEN VGA_BLUE EV_CRT_DDCCLK EV_CRT_DDCDAT 143 145 DDCA_CLK DDCA_DAT EV_TV_Y/G 128 TV_Y/HDTV_Y/TV_CVBS EV_TV_C/R 124 TV_C/HDTV_Pr EV_TV_COMP 132 TV_CVBS/HDTV_Pb MXMDATA MXMCLK EVPRSNT1# R188 Q7 EV@RHU002N06 1 EV@10U/10V_8 EV@.1U/16V_4*EV@.1u_4 HDMITX0N HDMITX1N HDMITX2N DVI_A_TX0 DVI_A_TX1 DVI_A_TX2 227 221 215 HDMITX0P HDMITX1P HDMITX2P DVI_A_HPD 205 HDMI_HP_A DDCB_CLK DDCB_DAT 220 218 MXM_HDMI_DDCCLK_R MXM_HDMI_DDCDATA_R IGP/DVI_B_CLK# IGP/DVI_B_CLK 177 179 IGP/DVI_B_TX0# IGP/DVI_B_TX1# IGP_/DVI_B_TX2# 201 195 189 IGP/DVI_B_TX0 IGP/DVI_B_TX1 IGP_DVI_B_TX2 203 197 191 DVI_B_HPD/GND 181 IGP IGP IGP IGP IGP IGP IGP IGP IGP IGP IGP 147 149 151 159 161 163 165 167 169 171 173 RSVD RSVD RSVD RSVD RSVD RSVD 185 183 155 153 131 129 HDMITX0P <23> HDMITX1P <23> HDMITX2P <23> HDMI_HP_A <23> C +3V EV@0_4 Q8 EV@RHU002N06 133 135 RUNPWROK SMB_DAT SMB_CLK AC/BATT# 16 MXM_PWROK 157 MXM_ACIN R528 D44 EV@MXM CONNECTOR_2 EV@0_4 VIN PWROK_MXM <31> ACIN *EV@BAS316 Q52 EV@DTA114YUA 3 3 MXM_CLK <31> C289 C287 C288 EV@4.7U/25V_8 EV@4.7U/25V_8 EV@4.7U/25V_8 1 B R530 *10K_4 C290 C64 +3V 1 R541 *EV@10K_4 C50 Q53 EV@2N7002E EV@.1U/25V_4 EV@.1U/25V_4 EV@.1U/25V_4 2 ACIN <22,31,32> Modify Rev:D 3 MXM_DATA <31> A C294 *EV@.1u_4 C562 *EV@.1u_4 +3V C561 *EV@.1u_4 C280 MXMCLK R81 EV@4.7K_4 MXMDATA R86 EV@4.7K_4 +1.8V_MXM +2.5V C286 C548 +5V C550 C549 PROJECT : ZD1 C551 + C647 EV@1U/10V_4 EV@.1U/16V_4 330U/2.5V_7 EV@10U/10V_8 EV@.1U/16V_4 EV@1U/10V_4 EV@.1U/16V_4 Quanta Computer Inc. Size Document Number Date: Monday, May 07, 2007 4 Rev E MXM change from 10k to 4.7k , NV suggestion. on 10/20 5 HDMITX0N <23> HDMITX1N <23> HDMITX2N <23> +3V <26> MXM_SPDIF_OUT C256 225 219 213 HDMICLK- <23> HDMICLK+ <23> 0C Change power name from +1.8V to +1.8V_MXM 0108 +3V C282 DVI_A_TX0# DVI_A_TX1# DVI_A_TX2# +3V MXMDATA C284 HDMICLKHDMICLK+ THERM# EV@MXM CONNECTOR_2 A 207 209 0C Connect to EC 0104 EV@0_4 THERM# 137 R196 <3,14> THERM_ALERT# MXMCLK PRSNT1# PRSNT2# EV_LVDS_UTX#0 EV_LVDS_UTX#1 EV_LVDS_UTX#2 DVI_A_CLK# DVI_A_CLK 10K PEX_TX0 PEX_TX1 PEX_TX2 PEX_TX3 PEX_TX4 PEX_TX5 PEX_TX6 PEX_TX7 PEX_TX8 PEX_TX9 PEX_TX10 PEX_TX11 PEX_TX12 PEX_TX13 PEX_TX14 PEX_TX15 <18> EV_LVDS_LCLK# <18> EV_LVDS_LCLK PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 LVDS_UCLK# LVDS_UCLK 47K GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 117 111 105 99 93 87 81 75 69 63 57 51 45 39 33 27 148 150 TV MXM_SPDIF_OUT <18> EV_LVDS_UCLK# <18> EV_LVDS_UCLK PEG_RXP[15:0] PEX_RX0 PEX_RX1 PEX_RX2 PEX_RX3 PEX_RX4 PEX_RX5 PEX_RX6 PEX_RX7 PEX_RX8 PEX_RX9 PEX_RX10 PEX_RX11 PEX_RX12 PEX_RX13 PEX_RX14 PEX_RX15 CN27B EV_LVDS_UCLK# EV_LVDS_UCLK CRT B 17 19 20 21 22 23 24 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 126 130 134 138 142 146 152 158 164 170 175 176 182 187 188 193 194 199 200 206 211 217 223 224 229 1V8RUN 1V8RUN 1V8RUN 1V8RUN 1V8RUN 1V8RUN 1V8RUN PEG_RXN[15:0] <6> PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 LVDS 2 4 6 8 10 12 14 0_4 3 2V5RUN +1.8V_MXM 3.5Amp R410 2 222 0_4 ia La pt op .c +2.5V 0.5Amp R297 ah as 3V3RUN 3V3RUN 3V3RUN 115 109 103 97 91 85 79 73 67 61 55 49 43 37 31 25 MXM_HDMI_DDCCLK <23> CLK_MXM# <2> CLK_MXM <2> PEG_RXN[15:0] 5VRUN PEX_RX0# PEX_RX1# PEX_RX2# PEX_RX3# PEX_RX4# PEX_RX5# PEX_RX6# PEX_RX7# PEX_RX8# PEX_RX9# PEX_RX10# PEX_RX11# PEX_RX12# PEX_RX13# PEX_RX14# PEX_RX15# 3MXM_HDMI_DDCCLK 1 1 CLK_MXM# CLK_MXM 0F Modify 0425 *EV@RHU002N06 D PLTRST# <13,14,20,22..24,29..31> 2 226 228 230 +3V *4.7K_4 Q55 om 121 123 +3V 1.5Amp R75 MXM_HDMI_DDCCLK_R MXM_HDMI_DDCDATA <23> DVI-A PEX_REFCLK# PEX_REFCLK 3MXM_HDMI_DDCDATA 1 DVI PLTRST# *EV@RHU002N06 DVI-B 127 MXM_HDMI_DDCDATA_R w .R 18 +3V *4.7K_4 Q54 2 +5V 0.5Amp PEX_RST# PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC PWR_SRC w 4Amp CLK_REQ# 125 w D 1 3 5 7 9 11 13 15 R63 0C Change footprint 0103 CN27A VIN +3V 2 +3V 2 5 3 2 Sheet 1 17 of 38 5 4 3 2 1 LVDS +5V RN6 2 4 1 IV@0X2 3 INT_TXLCLKOUT- <6> INT_TXLCLKOUT+ <6> TXLOUT0TXLOUT0+ RN15 4 2 3 IV@0X2 1 INT_TXLOUT0- <6> INT_TXLOUT0+ <6> TXLOUT1TXLOUT1+ RN17 2 4 1 IV@0X2 3 INT_TXLOUT1- <6> INT_TXLOUT1+ <6> TXLOUT2TXLOUT2+ RN12 4 2 3 IV@0X2 1 INT_TXLOUT2- <6> INT_TXLOUT2+ <6> 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 <23> DISPON VIN R9 0_8 INVCC0 TXUOUT2+ TXUOUT2- 2 EV@0X2 4 EV_LVDS_LCLK# <17> EV_LVDS_LCLK <17> RN14 3 1 4 EV@0X2 2 EV_LVDS_LTX#0 <17> EV_LVDS_LTX0 <17> RN16 1 3 2 EV@0X2 4 EV_LVDS_LTX#1 <17> EV_LVDS_LTX1 <17> RN11 3 1 4 EV@0X2 2 EV_LVDS_LTX#2 <17> EV_LVDS_LTX2 <17> C 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 LVDS_VADJ USBP7-_R USBP7+_R TXLOUT2+ TXLOUT2- 2 4 1 IV@0X2 3 INT_TXUCLKOUT- <6> INT_TXUCLKOUT+ <6> RN4 4 2 3 IV@0X2 1 INT_TXUOUT0- <6> INT_TXUOUT0+ <6> TXUOUT1TXUOUT1+ RN8 2 4 1 IV@0X2 3 INT_TXUOUT1- <6> INT_TXUOUT1+ <6> TXUOUT2TXUOUT2+ RN10 4 2 3 IV@0X2 1 INT_TXUOUT2- <6> INT_TXUOUT2+ <6> TXUCLKOUT+ TXUCLKOUT- RN1 1 3 2 EV@0X2 4 EV_LVDS_UCLK# <17> EV_LVDS_UCLK <17> RN3 3 1 4 EV@0X2 2 EV_LVDS_UTX#0 <17> EV_LVDS_UTX0 <17> RN7 1 3 2 EV@0X2 4 EV_LVDS_UTX#1 <17> EV_LVDS_UTX1 <17> RN9 3 1 4 EV@0X2 2 EV_LVDS_UTX#2 <17> EV_LVDS_UTX2 <17> +3V w R399 2.2K_4 TXUOUT0+ TXUOUT0- LCD_EDIDDATA LCD_EDIDCLK +5V <6> INT_LVDS_EDIDCLK R400 R398 EV@0_4 C C4 *10U + <6> INT_LVDS_DIGON <17> EV_LVDS_VDDEN 2.2K_4 1000P/X7R/50V_4 <17> EV_LVDS_DDCDAT <6> INT_LVDS_EDIDDATA R14 IV@0_4 R13 EV@0_4 R394 EV@0_4 R392 IV@0_4 DISP_ON 6 IN OUT 1 4 IN GND 2 3 ON/OFF GND 5 LCDVCC_1 R10 C23 0_8 C17 .1U/10V_4 LCDVCC C14 2.2U/10V_8 C13 C16 .1U/10V_4 .01U/16V_4 2.2U/10V_8 AAT4280 LCD_EDIDCLK IV@0_4 C22 U1 .1U/10V_4 R12 Crestline suggest 100K G73 suggest 10K(ZS1 Default)100K_4 (Need to confirm with Max) R393 C21 1000P/50V_4 B C3 +3V A +3V +3V w <17> EV_LVDS_DDCCLK VIN 0X2 ACES_88242-40XX_LVDS w .R B RP1 ah as RN2 4 2 D TXLOUT1+ TXLOUT1- C12 TXUOUT0TXUOUT0+ EC_L_BKLT_CTRL <31> EV_LVDS_BL_BRGHT <17> L_BKLT_CTRL <6> CCD_POWER <21> USBP7- <13> USBP7+ <13> TXLCLKOUT+ TXLCLKOUT- 1000P/50V_4 TXUCLKOUTTXUCLKOUT+ 0_4 *EV@0_4 *IV@0_4 3 1 TXUOUT1+ TXUOUT1- ia La pt op .c 1 3 R5 R7 R6 CN1 LCDVCC TXLOUT0+ TXLOUT0RN5 +3V om D TXLCLKOUTTXLCLKOUT+ A LCD_EDIDDATA PROJECT : ZD1 Quanta Computer Inc. Size Document Number Rev E LVDS Date: 5 4 3 2 Sheet Monday, May 07, 2007 1 18 of 38 1 2 3 4 8 <6> INT_CRT_GRN <6> INT_CRT_BLU <6> INT_HSYNC <6> INT_VSYNC <6> INT_CRT_DDCCLK <6> INT_CRT_DDCDAT SYS_VGA_BLU R28 EV@0_4 HSYNC SYS_VGA_RED L3 BLM18BA220SN1 CRT_R1 R25 EV@0_4 VSYNC SYS_VGA_GRN L2 BLM18BA220SN1 CRT_G1 R20 EV@0_4 CRTDCLK SYS_VGA_BLU L1 BLM18BA220SN1 R17 EV@0_4 CRTDDAT IV@0_4 R31 IV@0_4 R34 IV@0_4 R27 IV@0_4 R24 IV@0_4 R19 IV@0_4 R18 IV@0_4 +5V 1 CRT_BYP .22U/25V C28 7 8 2 +3V SYS_VGA_RED C29 .1U/10V_4SYS_VGA_GRN SYS_VGA_BLU 3 4 5 6 VCC_SYNC SYNC_OUT2 SYNC_OUT1 VCC_DDC BYP SYNC_IN2 VCC_VIDEO SYNC_IN1 VIDEO_1 VIDEO_2 VIDEO_3 GND <6> INT_TV_C/R CN13 150/F_4 150/F_4 150/F_4 C20 C15 CRT_B1 C11 10P/50V_410P/50V_4 10P/50V_4 6 1 7 2 8 3 9 4 10 5 C19 C25 10P/50V_410P/50V_4 10P/50V_4 11 CRT_11 12 DDCDAT_1 13 CRTHSYNC 14 CRTVSYNC 15 DDCCLK_1 R380 EV@0_4 R373 EV@0_4 R377 EV@0_4 R379 IV@0_4 R371 IV@0_4 R374 IV@0_4 16 14 CRT_VSYNC1 CRT_HSYNC1 VSYNC HSYNC DDC_IN1 DDC_IN2 10 11 CRTDCLK CRTDDAT DDC_OUT1 DDC_OUT2 9 12 DDCCLK_1 DDCDAT_1 L4 L5 BLM18BA220SN1 BLM18BA220SN1 D2 CRTVSYNC CRTHSYNC CRTVDD3 R23 R22 SYS_TV_Y/G 2.7K_4 2.7K_4 SYS_TV_C/R R26 2.7K_4 +3V L40 R21 2.7K_4 BLM18PG181SN1D TV-CHROMA CN22 4 4 3 3 9 9 8 8 2 2 1 1 C10 .1U/10V_4 C9 *10P_4 CRTVSYNC C18 *10P_4 CRTHSYNC C8 10P/50V_4 DDCCLK_1 C24 10P/50V_4 DDCDAT_1 TV-LUMA R372 150/F_4 C525 6P/50V_4 C526 L42 CRTVDD3 B BLM18PG181SN1D C531 6P/50V_4 6P/50V_4 TV_OUT L41 TV-COMP SYS_TV_Y/G 6P/50V_4 +3V D38 3 TV-CHROMA 6P/50V_4 150/F_4 SYS_TV_COMP R375 C527 150/F_4 6P/50V_4 D TV-LUMA 2 DA204U 2 DA204U 2 DA204U R381 +3V D36 3 TV-COMP C533 BLM18PG181SN1D C528 1 D37 3 CRT_SENSE# <13,31> C SYS_TV_COMP 1 D MTW355 1 FOR ESD +3V A SYS_TV_C/R w D2C: NEW ADD T1 D3 *MTW355 w <6> INT_TV_COMP C26 6 <6> INT_TV_Y/G R8 w .R <17> EV_TV_COMP R11 ah as TV Out (SVHS) MiniDIN 7-pin <17> EV_TV_C/R R15 15 13 IP4772 <17> EV_TV_Y/G CRTVDD3 CRT U2 CRTVDD3 C30 .1U/10V_4 B SSM14 17 R29 D1 +5V 5 <6> INT_CRT_RED SYS_VGA_GRN EV@0_4 5 <17> EV_CRT_DDCDAT EV@0_4 R35 om <17> EV_CRT_DDCCLK R32 7 <17> EV_CRT_VSYNC SYS_VGA_RED 7 <17> EV_CRT_HSYNC EV@0_4 6 <17> EV_CRT_B R30 ia La pt op .c <17> EV_CRT_G C 7 CRT CONNECTOR AND ESD <17> EV_CRT_R A 6 16 CRT Select 5 PROJECT : ZD1 Quanta Computer Inc. Size Document Number Date: Monday, May 07, 2007 Rev E CRT/TVOUT 1 2 3 4 5 6 7 Sheet 19 8 of 38 5 LAN 4 3 2 1 +3V_S5 2 Q11 DTC144EUA R107 4.7K_4 +3V_S5 PCIE_WAKE_R# 1 VAUX_25 +3V_S5 D 2.2U/10V_8 .1U/16V_4 C68 GPHY_PLLVDD C74 2.2U/10V_8 .1U/16V_4 C87 PCIE_PLLVDD C98 2.2U/10V_8 .1U/16V_4 BLM11A601S VAUX_12 L11 BLM11A601S L12 BLM11A601S C PCIE_SDS_VDD C92 C96 2.2U/10V_8 <13> <13> <13> <13> C103 C105 GLAN_RXP GLAN_RXN GLAN_TXP GLAN_TXN R91 <13,14,17,22..24,29..31> PLTRST# <2> CLK_PCIE_LAN <2> CLK_PCIE_LAN# 0_4 R71 R70 R598 R90 R77 R73 +3V_S5 +3V LAN_LOWPWR <31> LAN_LOWPWR .1U/16V_4 .1U/16V_4 +3V_S5 .1U/16V_4 1K_4 1K_4 0_4 *4.7K_4 47K 47K AUX_PRES VMA_PRES LAN_SMBC LAN_SMBD 35 GPHY_PLLVDD 30 68-Pin QFN 27 33 PCIE_VDD PCIE_VDD 24 PCIE_GND 54 53 3 VAUXPRSNT VMAINPRSNT LOW_PWR 58 57 SMB_CLK SMB_DATA 22 21 XTALO XTALI RDAC 37 RDAC 1 AVDD 38 C107 .1U/16V_4 AVDD 45 AVDD_F14 AVDD 52 TRD3TRD3+ 49 50 TRD2TRD2+ 48 47 TRD1TRD1+ 42 43 TRD0TRD0+ 41 40 LINKLED# SPD100LED# SPD1000LED# TRAFFICLED# PCIE_TXDP PCIE_TXDN PCIE_RXDP PCIE_RXDN WAKE# PERST# REFCLK+ REFCLK- R66 1.21K GPIO2 8 UART_MODE GPIO1_SERIALDI GPIO0_SERIALDO 9 7 4 SCLK SI SO CS# 65 63 64 62 NC/(ENERGY_DET) 59 REGCTL25 18 REGCTL12 11 T14 CLK_LAN_X2 2 1 67 66 L13 L9 NC(CLK_REQ#) REG_GND 14 C88 .1U/16V_4 C118 C109 C95 C117 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 .1U/16V_4 TX3P TX3N C111 C101 C113 .1U/16V_4 .1U/16V_4 .1U/16V_4 2.2U/10V_8 X-TX3P X-TX3N MCT3 MX3+ MX3- 10 11 12 TCT4 TD4+ TD4- MCT4 MX4+ MX4- 15 14 13 X-TX1P <21> X-TX1N <21> X-TX2P <21> X-TX2N <21> X-TX3P <21> X-TX3N <21> R40 75/F_4 R39 75/F_4 R38 75/F_4 R37 75/F_4 TX3N TX3P TX2N TX2P C36 1500P/2KV_1808 TX1N TX1P C TX0N TX0P LINKLED# 100# 1000# LAN_ACTLED# +3V_S5 LAN_ACTLED# <21> T12 R88 4.7K_4 T13 R92 *4.7K_4 R97 4.7K_4 C114 .1U/16V_4 BCM_WP T11 U5 8 7 6 5 BCM_SCL SI BCM_SDA VCC WP SCL SDA A0 A1 NC GND 1 2 3 4 CS# R599 0_4 LAN REGCTL25 AT24C64 LAN_ENERGYDET LAN_ENERGYDET <31> Broadcom recommended cost down solution +3V_S5 C119 Q9 MMJT9435 C133 .1U/16V_4 D8 LINKLED# 1 D9 100# 1 D7 1000# 1 2.2U/10V_8 LAN REGCTL12 VAUX_25 16 3 C139 Q10 MMJT9435 C141 .1U/16V_4 LAN_LINKLED# LAN_LINKLED# <21> B VAUX_25 2 4 69 1 BAS316 2 BAS316 2 BAS316 2 LAN_REG1_2V C124 VAUX_12 C131 .1U/16V_4 C140 .1U/16V_4 +3V_S5 C121 47U/6.3V_12 C66 C67 .01U/16V_4 .01U/16V_4 10U/6.3V_8 Close Transformer LAN_REG1_2V C106 X-TX2P X-TX2N TCT3 TD3+ TD3- 18 17 16 2.2U/10V_8 +3V_S5 .1U/16V_4 X-TX1P X-TX1N 7 8 9 X-TX0P <21> X-TX0N <21> C65 A C116 21 20 19 C71 .1U/16V_4 GND C104 .1U/16V_4 TX2P TX2N BLM11A601S MCT2 MX2+ MX2- w C85 .1U/16V_4 TCT2 TD2+ TD2- X-TX0P X-TX0N w VAUX_12 TX1P TX1N 4 5 6 MCT1 MX1+ MX1- 10U/10V_8 U4 TCT1 TD1+ TD1- 24 23 22 NS892402P w .R 27P/50V_4 C115 BLM11A601S 1 Y1 25MHZ C108 XTALVDD BCM5787M 10mm X 10mm 2 B 23 PCIE_PLLVDD CLK_LAN_X2 CLK_LAN_X1 27P/50V_4 XTALVDD VDDP VDDP VDDIO VDDIO VDDIO VDDIO VDDIO AVDDL AVDDL AVDDL AVDDL GLAN_TXP_5787 26 GLAN_TXN_5787 25 31 32 PCIE_WAKE_R# 12 -LAN_RST 10 29 28 CLK_LAN_X1 C110 39 44 46 51 C73 .1U/16V_4 TX0P TX0N 1 2 3 ia La pt op .c C72 36 3 L8 AVDDL C78 BIASVDD ah as BLM11A601S VDDC VDDC VDDC VDDC VDDC VDDC BLM11A601S 17 68 6 15 19 56 61 L10 5 13 20 34 55 60 U21 VAUX_25 L7 BIASVDD VAUX_12 D VDDP+AVDD) C112 .1U/16V_4 om C120 .1U/16V_4 2 4 3 <14,22,31> PCIE_WAKE# BCM_SCL R85 *4.7K_4 SI R84 *4.7K_4 CS# R83 4.7K_4 R112 1.5_12 R109 *1_12 +3V_S5 A VAUX_25 PROJECT : ZD1 A1A: (9/1 BCM recommend) in order to pull up C321/C51 and Q17 pin 3 to 3V_LAN rail. Quanta Computer Inc. Size Document Number Date: Monday, May 07, 2007 Rev E BCM5787 LAN/TRANSFORMER 5 4 3 2 Sheet 1 20 of 38 1 2 3 4 5 6 7 CAMERA MODULE CONNECTOR RJ45-11 C27 1000P/X7R/50V_4 C31 1000P/X7R/50V_4 A CN14 X-TX3N 3 RX2- X-TX3P 4 RX2+ X-TX1N 5 RX1- X-TX2N 6 TX2- X-TX2P 7 TX2+ <20> X-TX3N <20> X-TX3P <20> X-TX1N <20> X-TX2N <20> X-TX2P <20> X-TX1P <20> X-TX0N <20> X-TX0P +3V_S5 R36 16 GND18 18 8 RX1+ X-TX0N 9 TX1- X-TX0P 10 TX1+ 11 LED2_P_A2 LAN_LINKLED# <20> LAN_LINKLED# B GND16 X-TX1P +3V_LED2 220_4 +3V +3V GND15 15 GND17 17 C34 470PF/3KV_1808 12 LED2_GRNN_A3 13 TIP RINGL 14 RING C32 R1 4.7K_4 1000P/50V_4 2 CCD_POWERON <31> Q2 DTC144EU 1 2 C35 470PF/3KV_1808 1000P/X7R/50V_4 2nd FAN +3VPCU w .R R587 *10K_4 2 Q19 AO3413 1 +3VSUS 3 BT_POWER_R L31 BK2125HS330_8 C464 C467 BT_POWER 2.2U/10V_8 1000P/X7R/50V_4 C BT_POWERON# <31> +5V +5V Q34 *RHU002N06 B BLUETOOTH MODULE CONNECTOR 1000P/X7R/50V_4 C R586 *10K_4 2.2U/10V_8 C2 CN3 ah as C33 C1 Q1 AO3413 FI-S2P-HF(JAE) FOXCONN_JM34F23-P2053 +3VPCU 3 TIPL RINGL TIPL CIR 1 + LED1_YELN_Y 3 LED1_YELP_Y 2 1 1 om +3V_LED1 LAN_ACTLED# 2 220_4 2 R33 <20> LAN_ACTLED# CCD_POWER <18> ia La pt op .c +3V_S5 CCD_POWER + A R543 3 1 CIRRX2 <31> R219 BT_POWER Q33 *AO3413 *10K_4 2 <13> USBP4+ <13> USBP4<22> BT_LED 2 +5VPCU D R197 U37 47 C646 4.7U/10V_8 1 2 3 4 5 C635 1 0C Modify circuits 0104 CIRR_X2 2ND_FAN_ON Q31 *2N7002E RP39 1 3 2 0X2 4 USBP4+_R USBP4-_R BT_LED CN31 3 TV_FAN w <31> TV_FAN w 3 0_4 CN12 1 CIRR_X2 8 1 2 3 1 2 3 4 5 6 7 Aces 88266-0500 *0.1U/X7R/50V C490 C480 C495 *22P_4 *22P_4 .01U/16V_4 *FAN_CON D EVER_IRM-V038_TRI-P Modify Rev:D PROJECT : ZD1 Quanta Computer Inc. Size Document Number Date: Monday, May 07, 2007 Rev E BT/CCD/RJ45-11/CIR/2nd FAN 1 2 3 4 5 6 7 Sheet 21 8 of 38 1 2 3 4 5 6 7 8 +3VPCU D48 MINI-Card R67 +3V +3V_MC 0 L6 FBJ3216HS800_12 +1.5V <13> PCIE_RXP4 <13> PCIE_RXN4 <2> CLK_PCIE_MINI1 <2> CLK_PCIE_MINI1# R49 *4.7K_4 *DTC144EU 16 14 12 10 8 6 4 2 NBSWON# WL_LED# USBP6+_R USBP6-_R RP4 RF_EN_RR LFRAME#_R LAD3_R LAD2_R LAD1_R LAD0_R R65 R60 R57 R53 R52 R50 Alltop_MINI CARD +3G_VDD 16 14 12 10 8 6 4 2 USBP8+_D USBP8-_D 4 0X2 2 R253 R477 UIM_VPP UIM_RST UIM_CLK UIM_DATA UIM_PWR Modify Rev:E +1.5V 2 +3V +3VPCU D51 1 MX2_WWW# 1 MY0 3 2 DA204U +3V CN5 <30,31> MX4_WL# R536 <30,31> MX2_WWW# <30,31> MX1_EMAIL# <30,31> MX5_BT# <21> BT_LED <30,31> MX3_3G# 0 0C Change footprint 0103 3G MINI_LED <31> TV_KEY MY0 CN8 1 2 3 4 5 6 7 8 Aces 88501-120N +3VPCU +3VPCU Aces 88501-0801 CN30 C651 1000P/50V_4 .1U/10V_4 C Q35 AO3413 2 S-Video-C S-Video-Y USBON# USBP1USBP1+ <25,31> USBON# <13> USBP1<13> USBP1+ 2 USBP1-_R 4 USBP1+_R 0X2_4 1 3 RP40 +5V_S5 1000P/X7R/50V_4 Q32 2N7002 2 <17,31,32> ACIN +3VSUS +3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CVBS 1 2 3 4 5 6 7 8 9 10 11 12 WL_LED Modify Rev:D R508 R507 Audio Left 150/F_4 150/F_4 Audio Right <30> CAPSLED <30> NUMLED <30> IDE_LED <31> NBSWON# UIM_VPP UIM_RST UIM_CLK UIM_DATA UIM_PWR <14,23,31> LID591# <30,31> PWRLED# <30,31> SUSLED# PWRLED# SUSLED# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Aces_88501-1601 Modify Rev:D +3V R270 CLK_PCIE_TV CLK_PCIE_TV# PCIE_RXP2 PCIE_RXN2 PCIE_TXP2 PCIE_TXN2 150/F_4 150/F_4 150/F_4 CLK_PCIE_TV <2> CLK_PCIE_TV# <2> PCIE_RXP2 <13> PCIE_RXN2 <13> PCIE_TXP2 <13> PCIE_TXN2 <13> 1 3G MINI_LED 3 PROJECT : ZD1 0_4 Quanta Computer Inc. Size 3G MINI_LED# Document Number Rev E MINI PCI-E card/3G/TV/Media Key Close near Mini-card connector Date: 3 0C Change footprint 0103 CN4 AC_IN Aces_87212-1600L R512 R511 C421 C438 C442 .1U/10V_4.1U/10V_4 10P/50V_4 B 2 DA204U R545 10K_4 R509 150/F_4 3 Q18 DTA114YUA +3G_VDD 2 +3VPCU D47 +5V_S5 Close near CN30 EMI SOLUTION C637 R510 1 2 DA204U R539 0_4 C507 3 DA204U WL_LED C428 .1U/10V_4 .1U/10V_4 C432 C383 4.7U/10V_8 4.7U/10V_8 MX3_3G# 0_4 MMB_A_KEY R525 0_4 R526 0_4 MMB_MX0_E_KEY# MMB_MY0 R527 0_4 LZA10-2ACB104MT TBCLK_R LZA10-2ACB104MT TBDATA_R L19 L18 +5V_S5 CVBS S-Video-Y S-Video-C FBJ3216HS800_12 1 3 3G_ON <31> D L27 3 R132 10K_4 <31> A_KEY <30,31> MX0_E_KEY# <30,31> MY0 <31> TB2CLK <31> TB2DATA USBP8+ <13> USBP8- <13> PDAT_SMB PCLK_SMB 0_4 0_4 PLTRST# C213 2.2U/10V_8 RP37 3 1 PDAT_SMB_3G PCLK_SMB_3G +5V_TV-CARD + C193 MX4_WL# R352 1 R131 10K_4 0_4 3G MINI_LED# R274 w FBJ3216HS800_12 +3VPCU D50 1 3 UIM_VPP UIM_RST UIM_CLK UIM_DATA UIM_PWR +1.5V GND +3.3V 3G_LED# +5V L59 +3V 47K GND REFCLK+ REFCLKGND CLKREQ# Reserved Reserved WAKE# 53 +5V_TV-CARD 15 13 11 9 7 5 3 1 +3VPCU D46 Q24 DTA114YUA LFRAME# <12,30,31> LAD3 <12,30,31> LAD2 <12,30,31> LAD1 <12,30,31> LAD0 <12,30,31> ah as CLK_PCIE_TV CLK_PCIE_TV# 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 w .R S-Video-Y S-Video-C +3.3V GND +1.5V LED_WPAN# LED_WLAN# LED_WWAN# GND USB_D+ USB_DGND SMB_DATA SMB_CLK +1.5V GND +3.3Vaux PERST# W_DISABLE# GND w PCIE_RXP2 PCIE_RXN2 C Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved GND PETp0 PETn0 GND GND PERp0 PERn0 GND UIM_C4 UIM_C8 GND PCIE_TXP2 PCIE_TXN2 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 GND Audio Right Audio Left 54 CVBS 2 DA204U 2.2U/10V_8 .1U/10V_4 +3V_MMB MINIPCI EXP_Aces 3 DA204U Media Key +3G_VDD CN34 MX5_BT# 2 WL_LED# 3G/TV MINI CARD +1.5V +3G_VDD 1 3 C513 PLTRST# <13,14,17,20,23,24,29..31> RF_EN <31> 0_4 0_4 0_4 0_4 0_4 0_4 B 0C delete net FAN_OT# 0103 51 + C514 USBP6+ <13> USBP6- <13> PDAT_SMB <2,14,16,23> PCLK_SMB <2,14,16,23> PCIE_WAKE#_MINI-Card 1 4 0X2 2 3 1 A D49 1 10K 3 <14,20,31> PCIE_WAKE# Reserved Reserved Reserved Reserved Reserved +1.5V GND +3.3V +3VPCU D45 +1.5V 1 2 Q5 GND REFCLK+ REFCLKGND CLKREQ# Reserved Reserved WAKE# +3V_MINI-CARD 2 +3VSUS 15 13 11 9 7 5 3 1 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 1 <13> PCIE_TXP4 <13> PCIE_TXN4 +3.3V GND +1.5V LED_WPAN# LED_WLAN# LED_WWAN# GND USB_D+ USB_DGND SMB_DATA SMB_CLK +1.5V GND +3.3Vaux PERST# Reserved GND 3 0_4 KEDRON_GND_37 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved GND PETp0 PETn0 GND GND PERp0 PERn0 GND Reserved Reserved om R68 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 47K CL_RST#0_CN *0_4 *0_4 CL_DATA1_CN CL_CLK1_CN *0_4 KEDRON_GND_43 0_4 +3V_MINI-CARD 10K R80 R76 R74 R69 2 DA204U +3VPCU CN19 <14> CL_RST#1 <14> CL_DATA1 <14> CL_CLK1 3 .1U/10V_4 10U/10V_8 *0 2 A *0_4 *0_4 R59 MX1_EMAIL# For ESD close to conn. side C79 ia La pt op .c R78 R72 <13,28> PCIRST# <2,30> PCLK_DEBUG +3VSUS 1 +3V_MINI-CARD + C62 4 5 6 7 Monday, May 07, 2007 Sheet 22 8 of 38 D 4 PERST# +NEW_3VAUX +NEW_1.5V NEW_SMDATA NEW_SMCLK R441 R442 <13> USBP5+ <13> USBP5- PERP3 PERN3 CLK_PCIE_NEW_C CLK_PCIE_NEW_C# NC_EN# +NEW_3V PERST# +NEW_3VAUX +NEW_1.5V NEW_SMDATA NEW_SMCLK USBP5+_R USBP5-_R U33 QFN-TPS2231RGP 27 28 *Aces_NEW CARD PERP3 PERN3 CLK_PCIE_NEW_C CLK_PCIE_NEW_C# NC_EN# +NEW_3V C PERST# +NEW_3VAUX +NEW_1.5V NEW_SMDATA NEW_SMCLK USBP5+_R USBP5-_R +NEW_3V 1.3A AUXIN AUXOUT 15 +NEW_3VAUX 275mA 1.5VIN 1.5VIN 1.5VOUT 1.5VOUT 11 13 +NEW_1.5V 650mA 6 20 *SYSRST# *SHDN# 1 10 9 NC_EN# 0C Connect to NC_EN# 0103 18 16 7 21 *STBY# *CPPE# *CPUSB# *RCLKEN NC GND GNDPAD PERST# OC# 8 19 3.3VIN 3.3VIN +3V_S5 17 +1.5V 12 14 PLTRST#_NEW *Taitwun_NEW CARD <13,14,17,20,22,24,29..31> D TI PERST# : AL002231001 RICOH : AL005538001 GMT : AL000577008 29 30 GND1 GND29 PETp0 GND30 PETn0 GND2 GND27 PERp0 GND28 PERn0 GND3 REFCLK+ REFCLKCPPE# CLKREQ# +3.3V1 +3.3V2 PERST# +3.3VAUX WAKE# +1.5V1 +1.5V2 SMB_DATA SMB_CLK RESERVED1 RESERVED2 CPUSB# USB_D+ USB_DGND4 PLTRST#_NEW 1 Q37 2N7002 3 PLTRST# ia La pt op .c 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 3 5 2 4 +3V CN43 PCIE_TXP1 PCIE_TXN1 REV:B MODIFY 3.3VOUT 3.3VOUT +3V REV:B MODIFY 27 28 +3V_S5 +3V +NEW_3V +1.5V 4 2 +NEW_3V D NEW CARD'S POWER SWITCH 29 30 GND1 GND29 PETp0 GND30 PETn0 GND2 GND27 PERp0 GND28 PERn0 GND3 REFCLK+ REFCLKCPPE# CLKREQ# +3.3V1 +3.3V2 PERST# +3.3VAUX WAKE# +1.5V1 +1.5V2 SMB_DATA SMB_CLK RESERVED1 RESERVED2 CPUSB# USB_D+ USB_DGND4 +NEW_3VAUX C599 .1U/10V_4 +NEW_3V C582 C598 C597 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 RP41 Q30 C351 2.2U/10V_8 FOX_EXPCARD C357 C348 <2,14,16,22> PDAT_SMB 3 .1U/10V_4 .1U/10V_4 2.2U/10V_8 +NEW_3V Q29 2N7002E .1U/10V_4 <2,14,16,22> PCLK_SMB 3 NEW_SMCLK 1 +5V +5V +3V D35 B BAS316 DISPON <18> DISPON D11 BAS316 w .R R194 100K_4 LID591# <14,22,31> R354 R353 2K_4 2K_4 L39 IV@0_4 R189 EV@0_4 <17> HDMITX2N <17> HDMITX1P 2 HDMITX1N HDMITX0P HDMITX0N HDMICLK+ <17> HDMITX0N <17> HDMICLK+ HDMICLK- <17> HDMICLKHDMI_DDCCLK HDMI_DDCCLK HDMI_DDCDATA 220R_100MHZ C515 *.1U_4 R359 <17> HDMI_HP_A EV@10K_4 EV_LVDS_BLON <17> L38 <17> MXM_HDMI_DDCDATA HDMI_DDCDATA HDMI monitor default have PU to 5V.So ZY3 PD for level change.And serial R for current limited Crestline suggest 100K G73 suggest 10K(ZS1 Default) (Need confirm with Max) R602 1K_4 HP_DET 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R356 EV@10K_4 SHELL1 D2+ D2 Shield D2D1+ D1 Shield D1D0+ D0 Shield D0GND CK+ CK Shield GND CKCE Remote NC DDC CLK DDC DATA GND +5V HP DET SHELL2 20 B 23 22 21 HDMI CON +5V 220R_100MHZ C516 HDMITX0P HDMITX0N *.1U_4 3 100K_4 HDMITX2N HDMITX1P <17> HDMITX1N <17> HDMITX0P INT_LVDS_BLON <6> w *1K_4 R191 C632 C631 C633 .1U/16V_4 .1U/16V_4 .1U/16V_4 HDMI_HP_A U26 1 2 3 4 5 1 2 VCC 4 5 *RClamp0514M_AG 10 10 9 9 GND 8 7 7 6 6 HDMITX0P HDMITX0N HDMI_HP_A A EC_FPBACK# <31> Q12 1 A R190 w R192 BAS316 HDMITX2P <17> HDMITX2P NV suggestion near HDMI connector <17> MXM_HDMI_DDCCLK D10 0C Change footprint 0103 CN21 D34 BAS316 C NEW_SMDATA 1 C344 ah as HDMI C354 10KX2_4 2N7002E .1U/10V_4 +NEW_1.5V C579 LID SWITCH C581 3 1 <2> CLK_PCIE_NEW_C <2> CLK_PCIE_NEW_C# <13> NC_EN# 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PCIE_TXP1 PCIE_TXN1 27 28 2 C381 C376 GND5 GND1 PETp0 GND27 PETn0 GND28 GND2 PERp0 PERn0 GND3 REFCLK+ REFCLKCPPE# CLKREQ# +3.3V1 +3.3V2 PERST# +3.3VAUX WAKE# +1.5V1 +1.5V2 SMB_DATA SMB_CLK RESERVED1 RESERVED2 CPUSB# USB_D+ USB_DGND4 GND6 1 2 <13> PCIE_TXP1 <13> PCIE_TXN1 <13> PCIE_RXP1 <13> PCIE_RXN1 29 26 25 24 23 PERP3 22 PERN3 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 0_4 USBP5+_R 3 0_4 USBP5-_R 2 1 30 2 CN44 2 New card 3 CN9 om 5 HDMITX2P HDMITX2N DTC144EU HDMITX1P HDMITX1N U27 1 2 3 4 5 1 2 VCC 4 5 *RClamp0514M_AG 10 10 9 9 GND 8 7 7 6 6 HDMITX2P HDMITX2N HDMICLK+ HDMICLK- HDMITX1P HDMITX1N HDMI_DDCCLK HDMI_DDCDATA U25 1 2 3 4 5 1 2 VCC 4 5 *RClamp0514M_AG 10 10 9 9 GND 8 7 7 6 6 PROJECT : ZD1 HDMICLK+ HDMICLKHDMI_DDCCLK HDMI_DDCDATA Quanta Computer Inc. Size Document Number Date: Monday, May 07, 2007 Rev E NEW CARD/HDMI/LID 5 4 3 2 Sheet 1 23 of 38 1 2 3 4 SATA HDD2 SATA HDD1 Main 23 GND23 23 GND1 RXP RXN GND2 TXN TXP GND3 1 2 3 4 5 6 7 GND1 RXP RXN GND2 TXN TXP GND3 1 2 3 4 5 6 7 3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND RSVD GND 12V 12V 12V 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND RSVD GND 12V 12V 12V 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 GND24 24 GND24 24 SATA_TXP1 <12> SATA_TXN1 <12> SATA_RXN1_C SATA_RXP1_C +3.3VSATA1 R229 C361 C370 *0_8 *.01U/25V_4 *.01U/25V_4 SATA_RXN1 <12> SATA_RXP1 <12> +3.3VSATA1 +3V +3.3VSATA1 +3.3VSATA1 C400 *10U/10V_8 C401 *10U/10V_8 C390 *.1U/10V_4 HDDA5V R246 +5V HDDA5V *0_8 C425 *10U/10V_8 C415 *.1U/16V_4 C417 *.1U/16V_4 C416 *.01U/16V_4 C418 *.01U/16V_4 SATA_RXN0_C SATA_RXP0_C +3.3VSATA2 HDDB5V R464 C583 C585 0_8 .01U/25V_4 .01U/25V_4 SATA_RXN0 <12> SATA_RXP0 <12> +3.3VSATA2 +3V +3.3VSATA2 R476 +5V +3.3VSATA2 C601 10U/10V_8 C595 10U/10V_8 C592 .1U/10V_4 HDDB5V 0_8 + + C439 *150U/6.3V_7343 *C16654-122A4-L_Serial_ATA A SATA_TXP0 <12> SATA_TXN0 <12> ia La pt op .c C621 150U/6.3V_7343 C614 10U/10V_8 C617 .1U/16V_4 C618 .1U/16V_4 C606 .01U/16V_4 C607 .01U/16V_4 C16654-122A4-L_Serial_ATA B CN28 SUYIN-ODDREV-800194MR050S110ZL +5V IDERST# PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 10K_4 C PDIOW# PIORDY IRQ14 PDA1 PDA0 PDCS1# IDELED# <12> PDCS1# <30> IDELED# +5V_ODD C292 .1U/10V_4 R176 470_4 +3V C R199 10K_4 PDDREQ <12> PDIOR# <12> PDDACK# +5V <13,14,17,20,22,23,29..31> PLTRST# PLTRST# 1 Q13 IDERST# 3 DTC144EU PDDACK# <12> PDIAG# R195 PDA2 PDCS3# *10K_4 +5V PDCS3# <12> +5V_ODD L49 C281 C285 .1U/10V_4 .1U/10V_4 0_8 +5V PDD[15..0] C556 <12> PDA[2..0] <12> 150U/6.3V_7343 w w 1000P/X7R/50V_4 RCSEL PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 PDDREQ PDIOR# + C293 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 w .R <12> PDIOW# <12> PIORDY <12> IRQ14 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 52 R193 51 52 IDELED# ah as ODD (PATA) B 2 A CN32 GND23 om CN33 D D PROJECT : ZD1 Quanta Computer Inc. Size Document Number Date: Monday, May 07, 2007 Rev E SATA-HDD & PATA-ODD 1 2 3 Sheet 4 24 of 38 5 4 3 USB 2 1 USBPWR1 C536 C537 100U/6.3_3528 1000P/X7R/50V_4 +5V_S5 CN23 U28 <22,31> USBON# IN1 IN2 4 1 9 EN# GND GND-C OUT3 OUT2 OUT1 8 7 6 OC# 5 USBPWR1 RP11 3 1 <13> USBP0<13> USBP0+ USBP0-_R USBP0+_R 4 0X2_4 2 1 2 3 4 1 2 3 4 5 6 7 8 5 6 7 8 D Alltop_USB R389 *6.34K/F U29 CM1293-04SO TPS2061DGNR 1 CH1 2 VN 3 CH2 CH4 6 VP 5 CH3 4 +5V_S5 om D 2 3 USBPWR2 C508 CH2 VP 5 CH3 4 RP3 <13> USBP2+ <13> USBP2- C HOLES CPU NUT 8 1 9 +5V_S5 C534 .1U/10V_4 HOLE25 *H-TC256BC315D118P2-8 2 5 3 6 4 7 C509 .1U/10V_4 C HOLE5 *H-TC256BC315D118P2-8 2 5 3 6 4 7 B HOLE10 H-C236D142P2-8 2 5 3 6 4 7 HOLE27 *H-TC256BC315D118P2-8 2 5 3 6 4 7 8 1 9 8 1 9 HOLE19 *H-TC256BC217D118P2-8 2 5 3 6 4 7 HOLE22 *H-TC256BC315D118P2-8 2 5 3 6 4 7 HOLE26 *H-TC256BC315D118P2-8 2 5 3 6 4 7 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 PAD11 EMIPAD EMIPAD *EMIPAD EMIPAD *EMIPAD EMIPAD *EMIPAD *EMIPAD EMIPAD EMIPAD EMIPAD 1 1 1 1 1 1 1 1 1 HOLE28 *H-TC256BC315D118P2-8 2 5 3 6 4 7 HOLE29 *H-TC236BC217D118P2-8 2 5 3 6 4 7 8 1 9 PAD1 1 Modify Rev:E 1 w HOLE12 H-TC98BC197D59P2 2 5 3 6 4 7 8 1 9 HOLE8 H-TC98BC197D59P2 2 5 3 6 4 7 8 1 9 8 1 9 8 1 9 HOLE23 H-TC98BC197D59P2 2 5 3 6 4 7 +5V_S5 HOLE1 HOLE2 *H-TC354BC256D118P2-8 *H-TC256BC315D118P2-8 2 5 2 5 3 6 3 6 4 7 4 7 w MINI CARD NUT HOLE24 H-TC98BC197D59P2 2 5 3 6 4 7 HOLE11 HOLE20 *H-TC256BC315D118P2-8 *H-TC256BC315D118P2-8 2 5 2 5 3 6 3 6 4 7 4 7 ah as HOLE18 H-C236D142P2-8 2 5 3 6 4 7 5 6 7 8 10 12 Suyin_dual_usb 2 0X2_4 USBP2+_R USBP2-_R 4 1 3 8 1 9 HOLE17 H-C236D142P2-8 2 5 3 6 4 7 1 2 3 4 9 11 w .R HOLE14 H-C236D142P2-8 2 5 3 6 4 7 8 1 9 8 1 9 HOLE13 H-C236D142P2-8 2 5 3 6 4 7 8 1 9 HOLE9 H-C236D142P2-8 2 5 3 6 4 7 EMI PAD PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 EMIPAD EMIPAD EMIPAD EMIPAD EMIPAD EMIPAD *EMIPAD *EMIPAD *EMIPAD EMIPAD EMIPAD 1 1 1 1 1 1 1 1 1 Footprint error: PAD15 , PAD4 ,PAD16: emipad97x87 1 HOLE4 H-TC197BC98D59P2-8 2 5 3 6 4 7 PROJECT : ZD1 Quanta Computer Inc. 8 1 9 HOLE3 H-TC197BC98D59P2-8 2 5 3 6 4 7 A 1 MDC NUT 8 1 9 A HOLE21 *H-C236D142P2 2 5 3 6 4 7 8 1 9 8 1 9 HOLE15 H-C236D142P2 2 5 3 6 4 7 MXM NUT 8 1 9 B HOLE6 H-C236D142P2 2 5 3 6 4 7 8 1 9 HOLE16 H-C236D142P2 2 5 3 6 4 7 8 1 9 HOLE7 H-C236D142P2 2 5 3 6 4 7 0X2_4 +5V_S5 8 1 9 VN 3 6 8 1 9 G548A2P8U 2 RP2 CH4 8 1 9 *6.34K/F CH1 8 1 9 R41 1 C37 1000P/X7R/50V_4 8 1 9 OC# 5 U20 CM1293-04SO USBPWR2 8 1 9 EN# GND GND-C 8 7 6 8 1 9 4 1 9 OUT3 OUT2 OUT1 8 1 9 IN1 IN2 CN18 ia La pt op .c U3 2 3 8 1 9 +5V_S5 100U/6.3_3528 100U/6.3_3528 USBP3-_R USBP3+_R 4 2 8 1 9 3 1 <13> USBP3<13> USBP3+ C38 Size Document Number Rev E USB/HOLE Date: 5 4 3 2 Sheet Monday, May 07, 2007 1 25 of 38 5 4 3 2 CODEC(ALC268) 1 R313 LINE OUT Amplifier 10K C463 +5V_ADO C441 .1U/10V_4 Gain = -(Rf/Ri) TI321611U480_1206 C443 10U/10V_8 C479 .1U/10V_4 C648 C487 .1U/10V_4 C650 C649 C501 C469 .1U/10V_4 4.7U/10V_8 1000P/50V_4 1000P/50V_4 U18 C652 10P/50V_4 FRONT-L 10P/50V_4 C465 10U/10V_8 R312 10K 4 +3V_AVDD ADOGND MIC1-VREFO-R MIC2-VREFO 0 +1.5V R275 *0 <27> SECNTL MIC1-VREFO-L MIC1-VREFO-L <27> +AZA_VDD FRONT-L 1 D24 1 D23 <27> MUTE# MIC2-VREFO <27> FRONT-R C502 4.7U/10V_8 C449 C450 4.7U/10V .1U/10V_4 25 26 AVSS1 AVDD1 28 27 VREF MIC1-VREFO-L 30 31 32 29 LINE1-VREFO MIC2-VREFO GPIO1 33 NC MIC1-VREFO-R 35 20 C489 42 AVSS2 CD-GND 19 C483 .1U/10V_4 43 NC CD-L 18 C481 .1U/10V_4 MIC2_INT_R MIC2_INT_L Acer ALC268&888 NC 15 C444 10U/10V_8 C452 .1U/10V_4 PCBEEP PCBEEP 888@0_4 ACZ_SDIN268 BIT_CLK268 R281 C451 U16 5 VOUT VIN *G961-18ADJTEU(SOT89-5) 1 2 A 3 5 22_4 INR C466 1U/16V R346 20K/F R347 10K/F 7 R302 *36K_4 ADOGND R524 888@0_4 4 <27> D ADOGND + - C478 47P/50V_4 R325 10K HPR HPR <27> C460 MIC2_INTR1 <27> 4.7U/6.3V +NVDD +3V_AVDD +NVDD U35 1 C630 4.7U/6.3V C C+ 6 /SHDN 5 GND 4 VOUT 2 VIN 3 C- ADOGND 1412MUTE# G5930 ADOGND Change C19 to 4.7u MIC2_INTL1 <27> MIC1_JD <27> LINEIN_JD 5.1K/F BEEP_1 OUTR HPL G1412 ADOGND 1U/16V 9 11 12 14 2 13 17 VR <27> VR1 LINE_JD <27> R273 10K_4 PCSPK DIGVOL_UP <31> DIGVOL_UP DIGVOL_DN <31> DIGVOL_DN 2 3 A B <12> ACZ_SDIN0 <12> 5 <12> ACZ_SDOUT_MDC <12> ACZ_SYNC_MDC <12> ACZ_SDIN1 <12> ACZ_RST#_MDC +3V_S5 0 CN2 ACZ_SDOUT_MDC ACZ_SYNC_MDC R3 22_4 MDC_SDIN1 BIT_CLK_AUDIO <12> 1 3 5 7 9 11 15 GND AC_SDO GND AC_SYNC AC_SDI AC_RST# GND RSV RSV 3.3V GND GND AC_BCLK GND 2 4 6 8 10 12 16 R4 *0 C5 .1U/10V_4 BIT_CLK_MDC <12> MDC 22P/50V_4 ACZ_SDOUT_AUDIO 5 +3V_S5 R16 MDC <12,27> 4 B 0C Change power from +3V to +3v_S5 to slove wake on ring issue 0111 ACZ_SYNC_AUDIO 1 4 PCSPK <14> R279 1K_4 ACZ_RST#_AUDIO C VR_XRE094_NOBLE R2 *22_4 C7 *10P-50V_4 <12> EAPD R301 *12K_4 Vo=1.2*(R371+R372)/R371= 4.8V 1U/16V SHDNR# SHDNL# 8 ADOGND C6 *10P-50V_4 MXM_SPDIF_OUT A MXM_SPDIF_OUT <17> The pin2 of ALC888 define MXM_SPDIF_OUT PROJECT : ZD1 w VEN w 4 ADJ *0 GND R271 22_4 R282 w .R +5V_ADO C453 1 16 MIC1-L <27> C474 R349 SVSS NVDD 0C Change size to 0603 0111 .1U/10V_4 C440 100P-50V R537 Tied at one point only under the codec or near the codec +5V SENSEA 12 11 9 14 13 MIC1-L 10K 5 NC1 NC2 NC3 NC4 SGND PGND TPAD C468 C447 4.7U/6.3V .1U/10V_4 MIC1-R <27> ah as B MUTE_888 SPDIF_OUT_888 +3V 10 888@1U/16V SURR-L 888@1U/16V SURR-R NC Sense A +AZA_VDD C639 C640 8 SPDIFO 7 48 6 EAPD DVDD1 DMIC-CLK 47 RESET# 16 SYNC MIC2-L DVDD2 NC 46 SDATA-IN MIC2-R 45 DVSS2 NC 17 BIT-CLK 44 SDATA-OUT EAPD_268 268@0_4 ADOGND 34 21 CD-R R311 0 Sense B MIC1-L HP-OUT-R 0C Modify circuits for subwoofer 0111 R335 FRONT-L JDREF 41 R324 6 10 +3V_AVDD ADOGND LINE1-L <27> 40 1 <27> MONO_OUT_L <27> MONO_OUT_R MIC1-R LINE1-R <27> SURR-R MXM_SPDIF_OUT MONO_OUT_L MONO_OUT_R LINE1-L 20K/F SPDIF_OUT <27> SPDIF_OUT LINE1-R 23 MIC1-R DVSS1 268@0_4 24 LINE1-L HP-OUT-L 5 R538 LINE1-R 10U/10V_8 2 BLM11A601S C435 *4.7U/10V_8 22 4 EAPD AVDD2 L28 1 +3V 39 ADOGND <27> EAPD MONO-OUT 38 DMIC-3/4/GPIO3 R329 ADOGND <27> SURR-R 37 3 C C477 1412MUTE# ia La pt op .c SURR-L <27> SURR-L FRONT-R 268@0_4 MONO_OUT_268 +5V_ADO DMIC-1/2/GPIO0 R523 2 MONO_OUT_L 36 ADOGND +NVDD 2 MTW355 2 *MTW355 +5V_ADO FRONT-R U19 100K_4 SVDD PVDD om +3V R276 R296 +3V_AVDD MIC1-VREFO-R <27> 3 15 HPL OUTL - INL + D 7 L30 47P/50V_4 6 +5V Quanta Computer Inc. Size Document Number Rev E REALTEK ALC268&888/MDC/VR Date: 3 2 Sheet Monday, May 07, 2007 1 26 of 38 5 4 Speaker Amplifier 3 2 1 SYSTEM LINE OUT/SPDIF +5V_ADO +3V_AVDD C471 1U/16V +3V_SPD C446 .1U/10V_4 R316 <26> SPDIF_OUT ADOGND SECNTL SPDIFO 0_4 LINEOUT_JD: HP not insert->H HP insert->L SECNTL <26> C473 .1U/10V_4 Gain = -(Rf/Ri) C476 2.2U/10V_8 SURR-R-1 R300 10K R330 C484 R315 C470 INSPKR+ 10K 330P/25V_4 10K 330P/25V_4 ADOGND R328 100K_4 4.7U/6.3V C445 4.7U/6.3V C482 1441 MUTE 3 1441 MUTE SURR-R-2 1 LIN1 18 RIN1 2 17 16 3 R327 0_4 5 R298 0_4 11 14 6 8 23 4 15 RBYPASS LBYPASS SE/BTL G1441 Q22 IN1/IN2 13 ROUT+ ROUTLOUT+ LOUT- 19 12 24 7 <26> <26> ADOGND HPL HPR HPL HPR 75/F_4 75/F_4 L35 L34 INSPKR+ INSPKRINSPKL+ INSPKL- R340 *1K_4 ia La pt op .c 1 ADOGND +3V_AVDD EC MUTE <31> AMP_MUTE# 1 D22 2 MTW355 <26> EAPD 1 D20 2 MTW355 1 D21 2 *MTW355 <12,26> ACZ_RST#_AUDIO R283 10K_4 MUTE# R551 R550 R547 R549 R548 R546 R540 R408 R337 R284 C472 C459 CN35 0C Change to 0 Ω0122 INSPKR-N INSPKR+N INSPKL-N INSPKL+N 1 25 36 4 C623 C624 C625 C622 47P/50V_4 47P/50V_4 47P/50V_4 47P/50V_4 22K_4 LINEOUT_JD ADOGND SYSTEM LINE IN/SUBWOOFER ah as ADOGND <26> LINE1-R LINE1-L_1 L37 BK1608LL121 C504 10U/10V_8 LINE1-R_1 L36 BK1608LL121 Q43 Q42 LINEOUT_JD 1 Q21 ME2347 3 LINEINL_SYS LINEINR_SYS <26> LINEIN_JD +3V 2 ADOGND C505 470P/50V_4 470P/50V_4 1 2 6 3 4 <26> MIC1-L <26> MIC1-VREFO-R 7 LINEOUT_JD <26> 2N7002 C <26> MIC1-R R345 2.2K_4 C493 2.2U/6.3V MIC1_L1 L33 BK1608LL121 MIC1_L R339 2.2K_4 MIC1_R1 L32 BK1608LL121 MIC1_R C497 2.2U/6.3V CN41 D2C: NEW ADD 1 2 6 3 4 <26> MIC1_JD 7 8 5 2SJ-T351-S11 C498 C496 470P/50V_4 470P/50V_4 8 FOR ESD LINEIN_JD ADOGND For ESD close to audio out connecter D2C: NEW ADD FOR ESD INT MIC array 1 1 MIC1_JD R333 3 4.7K_4 1 D29 2 MTW355 MIC2-VREFO 3 <26> 6 7 SUBWOOFER w MIC2_INTR1 Singatron DFTJ06FR741 2SJ-T351-S11 Foxconn DFTJ06FRA39 JA6233L-P3T4-7F Alltop DFTJ06FR899 C12107-D06A9-L ADOGND CN11 6 MIC2_INTR1 1 2 3 4 MIC2_INTL1 R285 R332 4.7K_4 85204-0200L_INT_MIC A <26> C486 *22P-50V_4 w 1 2 3 4 5 DA204U MIC2_INTR1 ADOGND Singatron DFTJ06FR732 2SJ-T351-S15 Foxconn DFTJ06FRA21 JA6233L-U3T4-7F Alltop DFTJ06FR902 C12107-906A9-L ADOGND 2 2 For ESD close to audio out connecter +5V_ADO D32 +5V_ADO DA204U 1441 MUTE B Normal OPEN Jack 2SJ-T351-S15 D31 <26> MONO_OUT_L <26> MONO_OUT_R +3V_SPD 5 w .R C500 ADOGND CN16 3 Foxconn DFTJ10FR470 2FB5441-BKMC-7F Singatron DFTJ10FR437 2SJ1371-0010A1 LINE_JD Normal OPEN Jack +5V 1 2N7002 2 <26> MIC1-VREFO-L CN42 10U/10V_8 +5V_ADO D33 MIC BLUE C503 FOR ESD 2 R594 85204-04001_SPEAKER-CON <26> LINE1-L R595 10K_4 +5V 2SJ1371-0010A1_SPDIF Normal OPEN Jack 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D LED Drive IC ADOGND DA204U LINE_JD SPEAKER L55 L56 L57 L58 7 8 6 SPDIFO +5V MUTE# <26> C INSPKRINSPKR+ INSPKLINSPKL+ C492 470P/50V_4 9 1 ADOGND C491 470P/50V_4 D2C: NEW ADD ADOGND 2 R343 *1K_4 5 4 10 3 2 1 HPL_SYS HPR_SYS BK1608LL121 BK1608LL121 ADOGND 2N7002 B R342 R341 CN40 LINEOUT_JD 20 3 MUTE# LIN2 RIN2 SHDN B1A: Add R588 & R591 VOL 3 INSPKL+ +5V_ADO U17 SURR-L-2 om 10K CT NC SECNTL R336 VDD3 SURR-L-1 LVDD RVDD 2.2U/10V_8 THRMPAD GND/HS GND/HS GND/HS GND/HS <26> SURR-R C494 25 22 21 10 9 <26> SURR-L D Pin5 connect to Pin3 on Jack BLACK ADOGND 2 C485 10U/10V_8 ADOGND 1 D30 MIC2-VREFO 2 MTW355 0 ADOGND A ADOGND MIC2_INTL1 MIC2_INTL1 <26> C488 *22P-50V_4 PROJECT : ZD1 ADOGND Quanta Computer Inc. Size Document Number Rev E AMP /AUDIO JACK CONN Date: 5 4 3 2 Monday, May 07, 2007 Sheet 1 27 of 38 5 4 +3V R5C832 : AJ5C8320H26 R5C833 : AJ5C8330H05 +3V C364 C580 4.7U/10V .01U/16V_4 .01U/16V_4 VCC_ROUT_832 D C571 C572 .01U/16V_4 .01U/16V_4 C593 .47U/6.3V_4 C586 .47U/6.3V_4 10 20 27 32 41 128 VCC_PCI1 VCC_PCI2 VCC_PCI3 VCC_PCI4 VCC_PCI5 VCC_PCI6 61 VCC_RIN 16 34 64 114 120 VCC_3V VCC_MD AD25 AD25 INTA#,B# R208 150/F_4 PCM_IDSEL PowerOnReset for VccCore C When GRESET# is controlled by system, the pull-up resistor(R762) and capacitor(C492) do not need to apply. <13> PAR <13> CBE3# <13> CBE2# <13> CBE1# <13> CBE0# +3V PCLK_PCM R473 100K_4 GRST#_832 <13> REQ0# <13> GNT0# <13> FRAME# <13> IRDY# <13> TRDY# <13> DEVSEL# <13> STOP# <13> PERR# <13> SERR# R457 *22_4 C613 .22u/10V_4 C578 *22p_4 <13,22> PCIRST# Ground guard <2> PCLK_PCM <13> PCI_PME# <14,31> CLKRUN# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 PAR C/BE3# C/BE2# C/BE1# C/BE0# IDSEL PCI / OTHER REQ2# GNT2# 125 126 127 1 2 3 5 6 9 11 12 14 15 17 18 19 36 37 38 39 40 42 43 44 46 47 48 49 50 51 52 53 33 7 21 35 45 8 REQ0# GNT0# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# 124 123 23 24 25 26 29 30 31 REQ# GNT# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# GRST#_832 PCIRST# 71 119 GBRST# PCIRST# PCLK_PCM 121 PCICLK PCI_PME# 70 CLKRUN# 117 1394_XIN FW^22P/50V_4 Y5 FW^24.576MHz 2 C605 1 B 94 1394_XOUT 95 FIL0_PWR 96 R463 10K_4 10K_4 XDEN 55 R458 UDIO5 57 R460 R462 UDIO3 UDIO4 65 59 SCL_CARD SDA_CARD UDIO2 56 UDIO1 60 UDIO0/SRIRQ# 72 VCC A INTA# 115 INTA# INTB# 116 INTB# 66 GRST# R467 R465 FW^56.2/F_4 FW^56.2/F_4 XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1 XD_D2/MS_D2/SD_D2 XD_D3/MS_D3/SD_D3 XD_RE#/CLK XD_WE#/MS_BS/SD_CMD SD_CDZ XD_R/B#/SD_WP# SERIRQ <14,30,31> INTA# <13> INTB# <13> L53 C594 C589 C373 C587 4.7U/10V .1u/16V_4 .01U/16V_4 1000P/X7R/50V_4 113 104 105 108 109 TPBIAS0 TPB0N TPB0P TPA0N TPA0P MDIO17 MDIO16 MDIO15 MDIO14 MDIO13 MDIO12 MDIO11 MDIO10 87 92 89 91 90 93 81 82 XD_D7 XD_D6 XD_D5 XD_D4 XD_D3/MS_D3/SD_D3 XD_D2/MS_D2/SD_D2 XD_D1/MS_D1/SD_D1 XD_D0/MS_D0/SD_D0 MDIO05 MDIO08 MDIO19 MDIO18 MDIO02 MDIO03 75 88 83 85 78 77 XD_WPO# XD_WE#/MS_BS/SD_CMD XD_ALE XD_CLE XD_CE# XD_R/B#/SD_WP# MDIO00 80 SD_CDZ MDIO01 79 MS_CDZ MDIO09 MDIO04 MDIO06 MDIO07 84 76 74 73 L1394_TPA0+ L1394_TPA0- 2 D40 2 D39 MS_SD_CLK R470 MC_PWR_CTRL_0 TP_XD_LED# COMMON MODE CHOKE NEAR CONN. CN26 C590 5 1 3 4 2 6 SUYIN_1394 FW^270P/25V_4 R472 10K_4 1 BAS316 1 BAS316 56.2/F XD_CDZ XD_RE#/CLK T76 38M030006-00 IEEE 1394 CONN 6POLE R/A 787956-1 DIP AMP 23 25 29 10 11 24 12 36 35 (4)SD-VCC (7)SD-DAT0 (8)SD-DAT1 (9)SD-DAT2 (1)SD-DAT3 (5)SD-CLK (2)SD-CMD SD-CD SD-WP Q16 SDA_CARD SCL_CARD XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1 XD_D2/MS_D2/SD_D2 XD_D3/MS_D3/SD_D3 XD_RE#/CLK MS_CDZ XD_WE#/MS_BS/SD_CMD 14 19 20 18 16 15 17 21 (9)MS-VCC (4)MS-DATA0 (3)MS-DATA1 (5)MS-DATA2 (7)MS-DATA3 (8)MS-SCLK (6)MS-INS (2)MS-BS 13 22 (3)SD/(1)MS/(1)XD-GND (6)SD/(10)MS/(9)XD-GND *10K_4 *10K_4 10K_4 2N7002 1 3 Q17 MC_PWR_CTRL_0# 2 33 (18)XD-VCC C +3V R242 (19)XD-CD (2)XD-R/B (3)XD-RE (4)XD-CE (5)XD-CLE (6)XD-ALE (7)XD-WE (8)XD-WP 34 1 2 3 4 5 6 7 XD_CDZ XD_R/B#/SD_WP# XD_RE#/CLK XD_CE# XD_CLE XD_ALE XD_WE#/MS_BS/SD_CMD XD_WPO# (10)XD-D0 (11)XD-D1 (12)XD-D2 (13)XD-D3 (14)XD-D4 (15)XD-D5 (16)XD-D6 (17)XD-D7 8 9 26 27 28 30 31 32 XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1 XD_D2/MS_D2/SD_D2 XD_D3/MS_D3/SD_D3 XD_D4 XD_D5 XD_D6 XD_D7 SDIO-GND SDIO-GND1 37 38 ME2347 30mil VCC_XD MC_PWR_CTRL_0 R240 C412 100K_4 4.7u/6.3V VCC_XD C410 .01U/16V_4 C409 C407 .01U/16V_4 .01U/16V_4 CARD_READER_TTN_R013-B10-XX-C B VCC_XD VCC_XD VCC_XD CN36 XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1 XD_D2/MS_D2/SD_D2 XD_D3/MS_D3/SD_D3 XD_RE#/CLK XD_WE#/MS_BS/SD_CMD SD_CDZ XD_R/B#/SD_WP# 23 25 29 10 11 24 12 36 35 (4)SD-VCC (7)SD-DAT0 (8)SD-DAT1 (9)SD-DAT2 (1)SD-DAT3 (5)SD-CLK (2)SD-CMD SD-CD SD-WP XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1 XD_D2/MS_D2/SD_D2 XD_D3/MS_D3/SD_D3 XD_RE#/CLK MS_CDZ XD_WE#/MS_BS/SD_CMD 14 19 20 18 16 15 17 21 (9)MS-VCC (4)MS-DATA0 (3)MS-DATA1 (5)MS-DATA2 (7)MS-DATA3 (8)MS-SCLK (6)MS-INS (2)MS-BS 13 22 (3)SD / (1)MS / (9)XD-GND (6)SD / (10)MS / (19)XD-GND VCC_XD CN38 (18)XD-VCC 33 (19)XD-CD (2)XD-R/B (3)XD-RE (4)XD-CE (5)XD-CLE (6)XD-ALE (7)XD-WE (8)XD-WP 34 1 2 3 4 5 6 7 XD_CDZ XD_R/B#/SD_WP# XD_RE#/CLK XD_CE# XD_CLE XD_ALE XD_WE#/MS_BS/SD_CMD XD_WPO# (10)XD-D0 (11)XD-D1 (12)XD-D2 (13)XD-D3 (14)XD-D4 (15)XD-D5 (16)XD-D6 (17)XD-D7 8 9 26 27 28 30 31 32 XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1 XD_D2/MS_D2/SD_D2 XD_D3/MS_D3/SD_D3 XD_D4 XD_D5 XD_D6 XD_D7 GND1 GND2 37 38 XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1 XD_D2/MS_D2/SD_D2 XD_D3/MS_D3/SD_D3 XD_RE#/CLK XD_WE#/MS_BS/SD_CMD SD_CDZ XD_R/B#/SD_WP# XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1 XD_D2/MS_D2/SD_D2 XD_D3/MS_D3/SD_D3 XD_RE#/CLK MS_CDZ XD_WE#/MS_BS/SD_CMD 21 31 34 9 11 25 15 39 41 SD-VCC SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-CLK SD-CMD SD-C/D SD-WP 19 29 40 SD-VSS1 SD-VSS2 SD-GND 12 22 24 20 16 14 18 26 10 28 42 43 MS-VCC MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 MS-SCLK MS-INS MS-BS MS-VSS1 MS-VSS2 GND GND XD-VCC 38 XD-CD XD-R/B XD-RE XD-CE XD-CLE XD-ALE XD-WE XD-WP 2 3 4 5 6 7 8 13 XD_CDZ XD_R/B#/SD_WP# XD_RE#/CLK XD_CE# XD_CLE XD_ALE XD_WE#/MS_BS/SD_CMD XD_WPO# XD-D0 XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7 23 27 30 32 33 35 36 37 XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1 XD_D2/MS_D2/SD_D2 XD_D3/MS_D3/SD_D3 XD_D4 XD_D5 XD_D6 XD_D7 XG-GND1 XD-GND2 1 17 *PROCONN-MXP038-A0-4010 * NOT Use EEPROM : R759 : installed R760,U43,C505 : NOT installed * Use EEPROM : R760,U43,C505 : installed R759 : NOT installed +3V R230 7 8 Memory Card Power Supply *CARD_READER_PLASTREN-CM47-X-38P-L R234 D L1394_TPB0L1394_TPB0+ VCC_XD +3V R5C832T_V00 A U12 5 6 SDA SCL 7 WP 4 GND A0 A1 A2 1 2 3 VCC 8 *FW^24LC08 PCLK(33MHz) 4 2 FW^0_4P2R L1394_TPB0L1394_TPA0L1394_TPA0+ L1394_TPB0+ VCC_XD TPBIAS0 TPBN0 TPBP0 TPAN0 TPAP0 HWSPND# 3 1 RN13 * NOT Use EEPROM : PU * Use EEPROM : PD 98 106 110 112 > 100 ns PRST# 100K_4 *100K_4 AVCC_PHY1 AVCC_PHY2 AVCC_PHY3 AVCC_PHY4 w RSV FW^0_4P2R 4 2 5 IN 1 CARD READER SERIRQ w >60 ns FW^.01U/16V_4 CN37 R5C832T_V00 GUARD GND C588 FW^.33U/10V 3 1 FW^5.1K/F_4 BK1608HS220_6_1A FIL0 VREF When HWSPND# is controlled by system, the pull-up resistor(R755) dose not need to apply. R469 10K_4 58 XO 100 TPB0P C584 RN18 TPB0N R468 MSEN TEST XI REXT FW^56.2/F_4 TPA0P TPA0N +3V CLKRUN# FW^.01U/16V_4 > 1 ms AGND1 AGND2 AGND3 AGND4 AGND5 99 102 103 107 111 R461 FW^56.2/F_4 1394_COM 832_SUS# PME# 101 97 4 13 22 28 54 62 63 68 118 122 R459 +3V IEEE1394/SD VREF_PWR GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 +3V FW^10K/F_4 C596 86 w .R REXT AS CLOSE AS POSSIBLE TO R5C833 69 FW^.01U/16V_4 R466 4.7U/10V HWSPND# FW^22P/50V_4 C602 C591 .01U/16V_4 1394_AVCC U32A C604 C399 VCC_ROUT1 VCC_ROUT2 VCC_ROUT3 VCC_ROUT4 VCC_ROUT5 <13> AD[31..0] AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 PAR CBE3# CBE2# CBE1# CBE0# PCM_IDSEL TPBIAS0 67 1 C564 3 C566 .01U/16V_4 2 .1u/16V_4 1394 +3V om C603 .01U/16V_4 1 ia La pt op .c C610 4.7U/10V 2 U32B ah as C570 3 +3V PROJECT : ZD1 C408 Quanta Computer Inc. *.1u/16V_4 Size Document Number Date: Monday, May 07, 2007 Rev E R5C832/833(5IN1/1394) 5 4 3 2 Sheet 1 28 of 38 5 4 3 2 1 ROBSON DIAMOND-LAKE ASIC +3V RBS_AVDDL RBS_AVDDT +1.2V RBS_AVDD U8 VDDO1 VDDO2 VDDO3 VDDO4 VDDO5 GND_PAD NF_WE[0]# NF_WE[1]# 33_4 WE#[0]_R 54 55 RE#[0]_RBS R158 33_4 RE#[0]_R 39 40 NF_RE[0]# NF_RE[1]# R159 33_4 CE#[0]_R 42 43 49 50 NF_CE[0]# NF_CE[1]# NF_CE[2]# NF_CE[3]# CLE_RBS R161 ALE_RBS R128 WP#_RBS READY_BUSY_RBS 33_4 33_4 CLE_RBS_R ALE_RBS_R NF_CLE NF_ALE NF_WP# NF_RB BUSY 2 R141 330_4 DISK_BUSY_R 51 53 56 37 33 T16 T15 T18 T17 T19 TP_RBS_RSVD2 TP_RBS_RSVD3 TP_RBS_RSVD4 TP_RBS_RSVD5 TP_RBS_RSVD6 9 10 11 12 14 RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] 19 ISET 30 29 CLKP CLKN 26 25 RXP RXN R117 C 1.4K/F_4 3 8 13 41 45 47 VDDR1 VDDR2 DIS_REG12 46 48 44 NF_IO[0] NF_IO[1] NF_IO[2] NF_IO[3] NF_IO[4] NF_IO[5] NF_IO[6] NF_IO[7] NF_IO[8] NF_IO[9] NF_IO[10] NF_IO[11] NF_IO[12] NF_IO[13] NF_IO[14] NF_IO[15] DIS_REG12 R160 PLACE CLOSE TO NAND FALSH 1K_4 NF_IO_00 NF_IO_01 NF_IO_02 NF_IO_03 NF_IO_04 NF_IO_05 NF_IO_06 NF_IO_07 NF_IO_08 NF_IO_09 NF_IO_10 NF_IO_11 NF_IO_12 NF_IO_13 NF_IO_14 NF_IO_15 57 59 62 64 66 68 4 6 58 60 63 65 67 1 5 7 NAND I/F ISET_RBS RE#[0]_RBS ALE_RBS CLE_RBS WE#[0]_RBS WP#_RBS 31 32 TP_RBS_RSVD7 TP_RBS_RSVD8 T36 T33 RSVD[09] RSVD[10] RSVD[11] RSVD[12] 28 21 20 34 TP_RBS_RSVD9 TP_RBS_RSVD10 TP_RBS_RSVD11 TP_RBS_RSVD12 T31 T22 T23 T38 RSVD[00] RSVD[01] 16 17 TP_RBS_RSVD0 TP_RBS_RSVD1 T20 T21 TXP TXN 23 22 +3V CLOCK <13> PCIE_TXP5 <13> PCIE_TXN5 T39 <13,14,17,20,22..24,30,31> PLTRST# CLRREQ#_RBS R600 0_4 R601 <31> RBS_RST# 35 36 *0_4 TXP_RBS_R TXN_RBS_R C162 C160 C159 PCIE_RXP5 <13> PCIE_RXN5 <13> CLKREQ# PERST# C210 C150 C207 +3V RBS_AVDD L16 BK1608HS800-T +1.5V C148 C147 C152 .1U/10V_4 .01U/16V_4 .1U/10V_41U/6.3V_4 C155 C161 .1U/10V_4 C166 C205 C149 PRE/VSS I/O[0] I/O[1] I/O[2] I/O[3] I/O[4] I/O[5] I/O[6] I/O[7] 38 29 30 31 32 41 42 43 44 1 2 3 4 5 11 14 15 23 24 25 27 28 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 DNU1 DNU2 DNU3 26 33 34 35 39 40 45 46 47 48 20 21 22 VCC1 VCC2 VSS1 VSS2 13 36 12 37 C208 NF_IO_00_R NF_IO_01_R NF_IO_02_R NF_IO_03_R NF_IO_04_R NF_IO_05_R NF_IO_06_R NF_IO_07_R R113 R114 R115 R116 R119 R121 R122 R125 33_4 NF_IO_00 33_4 NF_IO_01 33_4 NF_IO_02 33_4 NF_IO_03 33_4 NF_IO_04 33_4 NF_IO_05 33_4 NF_IO_06 33_4 NF_IO_07 C FLASH(48P)512MB TSOP48-ZS1 +3V C128 C129 C126 7 6 9 10 8 17 16 18 19 R/B1# NC24 CE1# NC25 RE# ALE CLE WE# WP# PRE/VSS I/O[0] I/O[1] I/O[2] I/O[3] I/O[4] I/O[5] I/O[6] I/O[7] 38 29 30 31 32 41 42 43 44 1 2 3 4 5 11 14 15 23 24 25 27 28 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 DNU1 DNU2 DNU3 26 33 34 35 39 40 45 46 47 48 20 21 22 12 37 VCC1 VCC2 VSS1 VSS2 13 36 NF_IO_08_R NF_IO_09_R NF_IO_10_R NF_IO_11_R NF_IO_12_R NF_IO_13_R NF_IO_14_R NF_IO_15_R R87 R89 R93 R98 R102 R103 R104 R108 33_4 NF_IO_08 33_4 NF_IO_09 33_4 NF_IO_10 33_4 NF_IO_11 33_4 NF_IO_12 33_4 NF_IO_13 33_4 NF_IO_14 33_4 NF_IO_15 B FLASH(48P)512MB TSOP48-ZS1 .01U/16V_4 .1U/10V_41U/6.3V_4 C206 .1U/10V_4 .1U/10V_4.01U/16V_4 .01U/16V_4 1U/6.3V_4 RBS_AVDDT L17 BK1608HS800-T C146 C209 .1U/10V_41U/6.3V_4 w C188 .1U/10V_4.01U/16V_4 .1U/10V_41U/6.3V_4 w C164 w .R +1.5V R123 *10K_4 ah as STUFF: INDICATES A 2KB VIRTUAL PAGE. => 256MB DESTUFF: INDIACTESS A 4KB VIRTUAL PAGE => 512MB & 1024MB +1.2V R/B1# NC24 CE1# NC25 RE# ALE CLE WE# WP# U6 RE#[0]_RBS ALE_RBS CLE_RBS WE#[0]_RBS WP#_RBS NF_IO_00 +3V C157 CE#[0]_RBS B 7 6 9 10 8 17 16 18 19 .01U/16V_4 .1U/10V_41U/6.3V_4 .1U/10V_4 .1U/10V_4 PCIE I/F Diamond_Lake QFN68-8X8-4-69P-ZS1 PLACE AS CLOSE AS POSSIBLE TO DIAMOND-LAKE ASIC. C158 D U7 CE#[0]_RBS RSVD[07] RSVD[08] INTEL NAND FLASH R120 1K_4 READY_BUSY_RBS RESERVED <2> PCIE_CLK_RBS <2> PCIE_CLK_RBS# PLACEMENT NOTE: PLACE TERMINATION RESISTERS AT 10% TO 25% DISTANCE FROM NAND FLASH. +3V +1.5V POWER R126 LED1 *LED_G_LTST-C190KGKT VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 om 2 15 38 52 61 69 WE#[0]_RBS CE#[0]_RBS 1 AVDD AVDDT AVDDL ia La pt op .c D 18 24 27 C167 C168 .01U/16V_4 .1U/10V_41U/6.3V_4 +1.5V LAYOUT NOTE: ANY VIA ADDED BENEATH THE NAND FLASH NEEDS TO HAVE A SOLDERMASK ON IT. RBS_AVDDL L20 BK1608HS800-T C186 C179 .1U/10V_4 .01U/16V_4 .1U/10V_41U/6.3V_4 C180 C181 A A PROJECT : ZD1 Quanta Computer Inc. Size Document Number Date: Monday, May 07, 2007 Rev E ROBSON 5 4 3 2 Sheet 1 29 of 38 5 4 INT K/B MY15 MY14 MY13 MY12 MY11 MY10 MY9 MY8 MY7 MY6 MY5 MY4 MY3 MX7 MX6 MY2 MX5_BT# MX4_WL# MX3_3G# MX2_WWW# MY1 MY0 MX1_EMAIL# MX0_E_KEY# MY16 MY17 MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MY16 MY17 MX7 MX6 MX5_BT# MX4_WL# MX3_3G# MX2_WWW# MX1_EMAIL# MX0_E_KEY# 1 +3V CPU FAN CN6 <31> MY15 <31> MY14 <31> MY13 <31> MY12 <31> MY11 <31> MY10 <31> MY9 <31> MY8 <31> MY7 <31> MY6 <31> MY5 <31> MY4 <31> MY3 <31> MX7 <31> MX6 <31> MY2 <22,31> MX5_BT# <22,31> MX4_WL# <22,31> MX3_3G# <22,31> MX2_WWW# <31> MY1 <22,31> MY0 <22,31> MX1_EMAIL# <22,31> MX0_E_KEY# <31> MY16 <31> MY17 2 +5V R351 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 C638 10K_4 0C Add 0103 2.2U/10V_8 +3VSUS <31> FANSIG +5V RP5 MX3_3G# MX2_WWW# MX1_EMAIL# MX0_E_KEY# 10 9 8 7 6 1 2 3 4 5 U23 MX4_WL# MX5_BT# MX6 MX7 2 <3> CPUFAN#_ON CPUFAN#_ON VO GND /FON GND GND VSET GND 1 CPUFAN# <31> CPUFAN# VIN 4 CN20 TH_FAN_POWER 3 5 6 7 8 C512 C511 C510 2.2U/10V_8 .01U/16V_4 *.01U_4 1 2 3 G995 10KX8 D FAN_CON FANPWR = 1.6*VSET om D 3 ia La pt op .c Aces 88502-2641 DEBUG PORT LED Reserved for LPC debug card EC Debug Port +3V +3V +3V +3VPCU +3V <31> EC_SOUT_CR_DEBUG <31> EC_SWD_DEBUG C R323 R322 10K_4 R334 330_4 <24> IDELED# <12> SATA_LED# D26 BAS316 D25 BAS316 2 1 2 3 4 CN10 *ACES_88231-0400 IDE_LED IDE_LED <22> 3 10K_4 R318 10K_4 1 EC_SOUT_CR_DEBUG 2 EC_SWD_DEBUG 3 4 Q23 1 2N7002E LAD0 LAD1 LAD2 LAD3 <12,22,31> LAD0 <12,22,31> LAD1 <12,22,31> LAD2 <12,22,31> LAD3 <2,22> PCLK_DEBUG <12,22,31> LFRAME# <13,14,17,20,22..24,29,31> PLTRST# <14,28,31> SERIRQ T87 T88 T89 T90 T91 T92 T93 T94 LFRAME# PLTRST# SERIRQ C Reserve to debug T/P +5V +3VPCU R344 B LED2 330_4 1 4 SUSLED# <22,31> 2 3 PWRLED# <22,31> R338 w .R LED_DUAL_LIGHT LED3 330_4 1 4 2 3 L45 BLM21P300S +TPVDD ah as +5V R386 10K_4 CN7 B 1 2 3 4 5 6 TPDATA_R TPCLK_R ACES_88058-0601 w w EMI solution +5V C642 Q14 DTA114YUA +1.5V C641 1000P/50V_4 1000P/50V_4 +3V C643 C644 1000P/50V_4 1000P/50V_4 +3V 3 NUMLED 1 NUMLED <22> 3 CAPSLED A CAPSLED <22> 330_4 2 10K 330_4 2 10K 47K 1 R221 47K R235 <31> NUMLED# .1U/16V_4 LZA10-2ACB104MT LZA10-2ACB104MT BATLED0# <31> +3V A C529 L44 L43 <31> TBDATA <31> TBCLK BATLED1# <31> LED_DUAL_LIGHT Q15 DTA114YUA R385 10K_4 PROJECT : ZD1 NUMLED# <31> CAPSLED# CAPSLED# Quanta Computer Inc. Size Document Number Date: Monday, May 07, 2007 Rev E FAN,LED,KB,DEBUG PORT,TP 5 4 3 2 Sheet 1 30 of 38 4 3 +3VPCU +3VPCU 1/13 Vendor mail: Dedicate cap for AVCC L51 +3V 2 C406 C402 1/13 Comfirm by vendor mail: VBAT for keep PLL power let power up can quick. no VBAT will switch to VCCpower. If PLL no power will cause boot time delay. C600 C384 .1U/10V_4 If .1U/10V_410U/10V_8 C387 122 <14> D15 SCI# BAS316 SCI#_uR 6 <22> A_KEY 124 C394 *10P_4 <13,14,17,20,22..24,29,30> PLTRST# PLTRST# GA20 LDRQ/GPIO24/HGPIO01 LPCPD/GPIO10/HGPIO00 7 LREST PWUREQ <14,28,30> SERIRQ 125 SERIRQ 08/10 FAE: SMI DOESN'T NEED DIODE <14> KBSMI# 9 SMI C MX0_E_KEY# MX1_EMAIL# MX2_WWW# MX3_3G# MX4_WL# MX5_BT# MX6 B MY16 MY17 53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33 KBSOUT0/JENK KBSOUT1/TCK KBSOUT2/TMS KBSOUT3/TDI KB KBSOUT4 KBSOUT5/TDO KBSOUT6/RDY KBSOUT7 KBSOUT8 KBSOUT9 KBSOUT10 KBSOUT11 KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62 KBSOUT15/GPIO61/XOR_OUT KBSOUT16/GPIO60 KBSOUT17/GPIO57/HGPIO03 MBCLK MBDATA MXM_CLK MXM_DATA 70 69 67 68 SCL1 SDA1 SCL2 SDA2 72 71 10 11 12 13 PSCLK1 PSDAT1 PSCLK2/GPIO26 PSDAT2/GPIO27 PSCLK3/GPIO25 PSDAT3/GPIO12 77 32KX1/32KCLKIN <30> TBCLK <30> TBDATA <22> TB2CLK <22> TB2DATA 8768_32KX1 R212 8768_32KX2 R216 33K/F C356 5.6P/50V_4 3 4 C363 32.768KHZ A SPI IR SMB 4 VDD A_PWM0 A_PWM1/GPIO21 B_PWM0/GPIO13 SPI_DI/GPIO77 SPI_DO/GPO76/SHBM SPI_SCK/GPIO75 32KX2 WPC8769LDG +3V TEMP_ABAT 64 95 93 94 119 109 120 65 66 15 16 17 20 21 22 23 24 25 26 27 28 91 110 112 PS/2 DA3_GPI97 4.7K_4 I/O ADDRESS SETTING I/O Address CC-SET <32> CPUFAN# <30> TV_KEY <22> T86 R542 ACIN <17,22,32> NBSWON# <22> LID591# <14,22,23> SUSB# <7,14> EC_FPBACK# <23> SUSLED# <22,30> PWRLED# <22,30> BATLED0# <30> BATLED1# <30> VRON <34> MAINON <35..37> PWROK_MXM <17> AMP_MUTE# <27> TV_FAN <21> SUSON <36,37> LAN_ENERGYDET <20> *0 0C Add net 0104 TV_FAN 0C Add net 0104 LAN_ENERGYDET 0C Add net 0110 0C Add net 0110 D/C# <32> S5_ON <33,37> LAN_LOWPWR <20> LAN_LOWPWR DNBSWON#_uR HWPG BAS316 D17 SWD/GPIO66 81 SWD_DEBUG CLKOUT/GPIO55 30 uR_TP_CLKOUT VCC_POR 85 VCC_POR# R224 104 VREF_uR R236 CORE DEFINED 2Eh 2Fh 11 164Eh 164Fh BADDR0 CCD_POWERON BADDR1 SOUT_CR_DEBUG R237 *10K_4 SHBM RF_EN 10K_4 R222 C MBCLK MBDATA 22 R597 22 6 5 Modify Rev:D 7 +3VPCU A0 A1 A2 1 2 3 VCC GND 8 4 SCL SDA WP C343 .1U/10V_4 24LC08 SPI FLASH +3VPCU SPI_SDI_uR R233 10K_4 12/4 Add 22 ohm for EMI SPI_SCK_uR_R 0_4 2 SPI_SDO_uR_R 5 SPI_SCK_uR_R 6 SPI_CS0#_uR 1 VDD 8 HOLD 7 WP 3 VSS 4 SO SI SCK CE C393 .1U/10V_4 W25X80VSSIG B 1/13 Comfirm by vendor mail : If the Southbridge enables 'Long Wait Abort' by default, the flash device should be 50MHz (or faster) EC_SOUT_CR_DEBUG <30> SPI_SDO_uR_R +3VPCU U11 CIRRX2 <21> 0_4 R596 R218 U9 RSMRST# <14> SUSC# <14> PWROK_EC <14> 0_4 R238 10K_4 PCIE_WAKE# <14,20,22> RBS_RST# <29> FANSIG <30> 0 R215 R239 1/13 Comfirm by vendor mail : Disabled ('1') if using FWH device on LPC. Enabled ('0') if using SPI flash for both system BIOS and EC firmware CRT_SENSE# <13,19> RF_EN <22> CELL-SET <32> R453 01 10 CCD_POWERON ACITVE LO => HI RF_EN SPI_SDI_uR SPI_SDO_uR SPI_CS0#_uR SPI_SCK_uR XOR TREE TEST MODE ACER ID EC_L_BKLT_CTRL <18> USBON# <22,25> 3G_ON <22> SOUT_CR_DEBUG Data 00 DNBSWON# <14> BT_POWERON# <21> CCD_POWERON <21> T55 08/10 FAE: ADD TP FOR DEBUG R419 *0 PWROK_EC_uR Index SHBM=0: Enable shared memory with host BIOS PWROK_MXM 86 87 90 92 VREF R223 DIGVOL_UP <26> DIGVOL_DN <26> RSMRST#_uR F_SDI F_SDO F_CS0 F_SCK CRT_SENSE# BADDR1-0 32 118 62 84 83 82 4.7K_4 4.7K_4 4.7K_4 4.7K_4 MTEMP <32> DIGVOL_UP DIGVOL_DN 31 117 63 R448 R438 R544 R535 D 11/23 Reduce switch On/Off noise T56 75 73 74 113 14 114 111 IRRX1/GPIO72 IRRX2_IRSL0/GPIO70 IRTX/GPIO71 SIN_CR/CIRRX/GPIO87 GPIO34/CIRRX2 CIRTX/GPIO16/HGPIO04 SOUT_CR/GPO83/BADDR1 FIU 08/10 FAE: ADD ONE GAD PAD UNDER X'TAL, AND KEEP CLEANCE. 5.6P/50V_4 1/13 Comfirm by vendor mail : Connect to AGND 8769AGND TIMER w Y2 79 w 2 1 0810 FAE: CHECK X'TAL'S FOOTPRINT CEECK RESULT: OK 20M TA1/GPIO56 TA2/GPIO20 TB1/GPIO14/HGPIO4 .1U/10V_4 ah as <3,32> MBCLK <3,32> MBDATA <17> MXM_CLK <17> MXM_DATA KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7 GND1 GND2 GND3 GND4 GND5 GND6 <22,30> MY0 <30> MY1 <30> MY2 <30> MY3 <30> MY4 <30> MY5 <30> MY6 <30> MY7 <30> MY8 <30> MY9 <30> MY10 <30> MY11 <30> MY12 <30> MY13 <30> MY14 <30> MY15 <30> MY16 <30> MY17 54 55 56 57 58 59 60 61 w .R MX0_E_KEY# MX1_EMAIL# MX2_WWW# MX3_3G# MX4_WL# MX5_BT# <30> MX6 <30> MX7 GPIO01 GPIO03 GPIO06/HGPIO06 GPIO07/HGPIP07 GPIO23 GPIO30 GPIO31 GPIO32 GPIO33 GPIO36 GPIO40 GPIO42/TCK GPIO GPIO43/TMS GPIO44/TDI GPIO45 GPIO46/TRST GPO47/JEN0 GPIO50/TDO GPIO51 GPIO52/RDY GPIO53 GPIO81 GPO82/HGPIO00/TRIS GPO84/HGPIO01/BADDR0 5 18 45 78 89 116 <22,30> <22,30> <22,30> <22,30> <22,30> <22,30> 101 105 106 107 LPC ECSCI 123 <30> NUMLED# D/A KBRST 29 <30> CAPSLED# DA0/GPI94 DA1/GPI95 DA2/GPI96 DA3/GPI97 CLKRUN/GPIO11/HGPIO02 VCORF 121 <12> RCIN# 97 98 99 100 108 96 .1U/10V_4 C636 BUTTON ON KEYBOARD MATRIX EC_SWD_DEBUG <30> T46 4.7K_4 +3VPCU 0_4 +A3VPCU 44 <12> GATEA20 A/D AD0/GPI90 AD1/GPI91 AD2/GPI92 AD3/GPI93 AD4/GPIO05 AD5/GPIO04 C634 DIGVOL_DN +3VPCU MBCLK MBDATA MXM_CLK MXM_DATA +3V ia La pt op .c 8 <14,28> CLKRUN# R232 *22_4 LFRAME LAD0 LAD1 LAD2 LAD3 LCLK DIGVOL_UP 0~AVCC power for DA pin power reference VCORF_uR PCLK_591 PCLK_591 3 126 127 128 1 2 AGND <12,22,30> LFRAME# <12,22,30> LAD0 <12,22,30> LAD1 <12,22,30> LAD2 <12,22,30> LAD3 <2> PCLK_591 08/10 FAE: 0.1UF 80 U10 VBAT C567 C404 .1U/10V_4 .1U/10V_4 103 C609 .1U/10V_4 102 C608 .1U/10V_4 VCC1 VCC2 VCC3 VCC4 VCC5 C568 .1U/10V_4 AVCC C569 2.2U/10V_8 D 19 46 76 88 115 .1U/10V_410U/10V_8 8769AGND SM BUS PU 1/13 Comfirm by vendor mail: VDD must power up after VCC/AVCC +A3VPCU BLM18AG601SN1 1 om 5 08/14 FAE: Please connect VREF(uRider pin104) to +A3VPCU instead of +3VPCU. C346 L26 HZ0603B601R-00 1U/16V GPIO PIN PU R214 10K_4 TV_KEY R518 +3VPCU INTERNAL KEYBOARD STRIP SET A +3VPCU 4.7K_4 MY0 R437 10K_4 8769AGND <37> HWPG_CPUIO <33> HWPG_3/5VPCU <35> HWPG_1.05V <36> HWPG_1.8V 5 D12 BAS316 D14 BAS316 D16 BAS316 D13 BAS316 HWPG 08/10 FAE: L83 CAN CHANGE FROM BEAD TO SHORT. BUT, PLEASE PUT AGND & 32K CAP & AVCC CAP AT ONE POINT. R521 PROJECT : ZD1 Quanta Computer Inc. 0_4 ZS1 STILL USE BEAD FOR SAFE. MPWROK <7,14> 4 Size Document Number Date: Monday, May 07, 2007 Rev E PC8769L & FLASH 3 2 Sheet 1 31 of 38 4 3 0.02_3720 PR82 VA 1 2 LITTLE-7A-1206 HI0805R800R-00_8 PQ31 SUD45P03-15 2 PDS1040S-13 3 PC11 0.1U/X7R/25V_8 PR9 220K/F PR8 220K/F 2 PR10 15 VDD 1 20 BOOT ISL6251_VDD PQ35 2N7002E PR111 100K/F 1 PQ34 2N7002E ISL6251_PHASE LGATE 14 ISL6251_LGATE PGND 13 GND 12 VADJ 11 ACLIM 10 9 VCOMP ICOMP PC101 100P/NPO/50V_6 C PQ29 FDS6900AS G1 D1 1 D1 2 6 G2 3 5 S2 4 4 VA3 PL11 SIL104R-100PF PR81 0.03_3720 6251LR 1 BAT-V 2 PC154 2200P/50V_6 PC89 .01U/50V_6 VREF PR100 19.6K/F PR91 *514K/F VADJ PC94 PC91 10U/X6S/25V_1206 10U/X6S/25V_1206 CSOP CSON Float = 4.2V / CELL B ACLIM PR102 33K/F PU1 ISL6251A PR85 *514K/F CC-SET <31> LIM = (1/R2)*(((0.05/VREF=2.39)VACLM)+0.050) PC96 100P/NPO/50V_6 CURRNT LIMIT POINT =(90w/19v)*0.85= 4.026A 4.026A=(1/0.02)((0.05/2.365)Vaclm+0.05) Vaclm=((33//152)/(33//152+19.6//152))*Vref PR16 ICMNT PR92 10K/F R2=adapter current sense resistnece *100_4 PC102 .01U/50V_6 A PC13 *3300P/X7R-50V_6 PROJECT : ZD1 CELL-SET = Hi ----> Cells = VDD ---->4S CELL-SET = Low ----> Cells = GND ---->3S 5 1 0.1U/X7R/25V_8 7 S1/D2 8 PL12 HI0805R800R-00_8 VREF PC95 6.8N/X7R/50V_6 6251CELLS_2 2 w A 2 18 VIN 10U/X6S/25V_1206 1 w PR105 100K/F 6 CELLS PR110 10K/F <31> CELL-SET PHASE 3 PC3 .01U/50V_6 3 *100K/F 1 PR158 PR14 10K/F w .R 2 PD1 ZD3.6V 6251CELLS_1 MTEMP 1 1 MBDATA <3,31> PD2 ZD3.6V 6251EN PR15 10K/F 6251VCOMP2 +3VPCU 6251VCOMP1 2 100K/F EN PR86 10K/F 4 PL9 HI0805R800R-00_8 17 ACSET 6251ICOMP 5 LITTLE-7A-1206 PC83 6251ACSET 2 3 MBCLK <3,31> MBDATA 2 PQ1 2N7002E PC92 4.7U/X5R/10V_8 2 PC93 .1U/X7R/50V_8 6251B_1 UGATE VRFE PR87 130K/F 8 HI0805R800R-00_8 PL8 BAT-V PR83 2.7 6251B_2 16 ISL6251_UGATE DCIN ICM 24 ah as 1 2 PR157 47P/NPO/50V_6 0.1U/X7R/50V_6 PR2 100_4 2 PF2 1 2 10mil D/C# <31> PD10 RB500V VDDP CSOP 7 DCIN CN15 PR1 100_4 0 PC90 PC6 1 ISL6251_VDDP 47n/X7R/25V_6 22 CSON MTEMP <31> PC12 2.2U/X5R/10V_8 1 2 CHLIM 2 20 PC8 1 PR167 PC86 47P/NPO/50V_6 PR7 PR90 4.7 PC9 23 0.1U/X7R/50V_6 ACPRN 100P/NPO/50V_6 MBAT+ MTEMP 4 PR6 10K 2P PR5 20 CSIN 20/F 21 CSON SUYIN_BATTERY 4 ia La pt op .c PR4 CSOP CSIP 19 C PC1 PC97 0.1U/X7R/25V_8 2200P/50V_6 PC153 PC7 0.1U/X7R/50V_6 CSIN_1 PC2 5 3 CSIP 10K/F PR166 2 8 9 2 PQ2 IMD2AT108 ISL6251_VDD B 6 CSIN ZD12V 1 2 3 4 5 6 7 1 1 10K/F PR13 6.8K/F PR11 33K D PD4 ACIN_1 PC151 2200P/50V_6 3 PC82 PC87 .1U/X7R/50V_8 .1U/X7R/50V_8 <17,22,31> ACIN 3 PD3 RB500V D PR12 PQ32 SUD45P03-15 VIN 4 1P 2200P/50V_6 2 PC85 .1U/X7R/50V_8 1 om PC152 POWER_JACK PC84 .1U/X7R/50V_8 PL13 3 1 1 1 2P 1 2 3 4 PD9 1P HI0805R800R-00_8 PL10 PF1 PJ1 2 1 5 3 2 Quanta Computer Inc. Size Custom Document Number Date: Monday, May 07, 2007 Rev C ISL6251 CHARGER Sheet 1 32 of 38 5 4 MAIND 3 2 1 MAIND <36,37> SUSD SUSD <37> PL20 1 <3> SYS_SHDN# HI0805R800R-00_8 PL5 2 ISL6236_3V PR146 0_4 PL18 VIN VIN D HI0805R800R-00_8 D HI0805R800R-00_8 VL 1 2 3 1 PD7 VL 1 2 3 4 2 8 5 7 2 3V_LX C DDPWRGD_R 3V5V_EN PR152 1/F 2 PC76 + 330U/6.3V_6X5.7 0.1U/X7R/50V_6 PR149 *0 3V_DL 0 DDPWRGD_R PR150 0 HWPG_3/5VPCU <31> 3 PR160 1M 2 1 3 2 1 1 +5V_S5 1 2 5 6 2 4 MAIND 0.1U/X7R/50V_6 PQ17 FDC653N_NL 3 S5D +3VSUS 0.1U/X7R/50V_6 PC59 0.1U/X7R/50V_6 PQ18 FDC653N_NL 3 +3V PC77 0.1U/X7R/50V_6 FDS8884 0.1U/X7R/50V_6 PQ16 FDC653N_NL 3 PC64 1 2 5 6 1 2 5 6 PQ26 FDC653N_NL 3 PC63 0.1U/X7R/50V_6 +5V PQ41 PQ44 2N7002E A PC70 4 MAIND 4 SUSD +3VPCU 1 2 5 6 w 5 6 7 8 0.1U/X7R/50V_6 +3VPCU PC62 +3VPCU 4 S5D PR76 39K/F_4 +5VPCU w 3 3 <31,37> PR69 200K/F_4 PC68 0.1U/X7R/50V_6 PC146 PR153 1M 2 4 22_8 1 B Iocp=6.25-(2.18/2)=5.16A Vth=5.16A*28mOhm=145mV R(Ilim)=(145mV*10)/5uA ~294K 1 +15V_ALWP 15V PR159 1M PD8 BAT54-7-F CHN217 PR68 15V OCP:6.25A L(ripple current) =(19-3.3)*3.3/(2.5u*0.5M*19) ~2.18A 2 1 3 1 +5VPCU +3V_S5 PC60 0.1U/X7R/50V_6 A PC61 0.1U/X7R/50V_6 PC142 0.1U/X7R/50V_6 PROJECT : ZD1 modify 0103 2007 5 PC65 PR147 0 PC141 0.1U/X7R/50V_6 2 w .R Iocp==OCP-(Delta IL/2)=10-(6/2)=7A Vth=7A*15mOhm=105mV R(Ilim)=(105mV*10)/5uA ~210K 2 PR70 290K/F_4 2 1 PC66 1U/16V_6 ah as PC67 0.1U/X7R/50V_6 B PDTC143TT 32 31 30 29 28 27 26 25 PC58 0.1U/X7R/50V_6 CHN217 PD6 Delta IL(ripple current)=(Vin-Vout)*Vout/(L*f*Vin) =(19-5)*5/(1.5u*0.4M*19) ~6A S5_ON +3VPCU PL6 2.5uH_7.5A 1 OCP:10A PQ43 PR78 OCP : 6.25A 3V_DH 1 1 3 VIN REFIN2 ILIM2 OUT2 SKIP# PGOOD2 EN2 DH2 LX2 2 PC137 0.1U/X7R/50V_6 2 PU7 ISL6236 3V_DH PR141 *0_4 6 1 1 LDOREFIN LDO VIN RTC ONLDO VCC TON REF 8 7 6 5 4 3 2 1 PR75 1/F 2 Add on 9/27 PQ27 FDS6690AS 1 2 1 PC75 0.1U/X7R/50V_6 PR144 0_4 PR143 *0_4 BST1 DL1 VDD SECFB GND PGND DL2 BST2 5V_DL 1 PC79 0.1U/X7R/50V_6 PC143 10U/X6S/25V_1206 PAD PAD PAD 4 + BYP OUT1 FB1 ILIM1 PGOOD1 EN1 DH1 LX1 PAD PAD 35 34 33 1 2 3 1 PR151 8 7 6 5 2 PC78 PR148 *0_4 9 10 11 12 2 210K/F_4 DDPWRGD_R 13 3V5V_EN 14 15 16 37 36 PQ23 FDS6900AS 1 17 18 19 20 21 22 23 24 +5VPCU 5V_LX 330U/6.3V_6X5.7 ia La pt op .c 1 2 8 7 6 5 150K/F_4 PC144 10U/X6S/25V_1206 PC80 PC145 2200P/X7R/50V_6 10U/X6S/25V_1206 G1 5V_DH FDS8884 C 2 S1/D2 4 +5VPCU PL7 1.5uH_10A PC140 0.1U/X7R/50V_6 PC81 0.1U/X7R/50V_6 D1 PR138 OCP: 10A PC139 .01U/25V_6 3V_DL PR139 0_4 PC135 1U/16V_6 G2 PC136 0.1U/X7R/50V_6 3V5V_EN PQ25 PR140 0_4 D1 PC72 PC74 2200P/X7R/50V_6 10U/X6S/25V_1206 PC138 4.7U/X5R/10V_8 S2 PC73 0.1U/X7R/50V_6 PR145 39K/F_4 2 1 PR142 390K_4 om 2 VL 4 3 2 Quanta Computer Inc. Size Custom Document Number Date: Monday, May 07, 2007 Rev B ISL6251 CHARGER Sheet 1 33 of 38 5 4 3 2 1 PL2 HI0805R800R-00_8 VIN_6262 PL1 HI0805R800R-00_8 PC155 2200P/50V_6 PR99 *0 DELAY_VR_PWRGOOD H_VID1 H_VID0 6262_LG1 4 *2200P/100V_6 VR_TT# 6 NTC 38 VID1 UGATE2 H_VID2 39 VID2 BOOT2 H_VID3 40 VID3 41 VID4 H_VID5 H_VID6 <7,14> PM_DPRSLPVR <3,7,12> ICH_DPRSTP# <14> VR_PWRGD_CK410# VID6 44 VR_ON PR18 499/F_4 DPRSLPVR 45 DPRSLPVR PR104 0_4 46 DPRSTP# PR103 0_4 47 CLK_EN# 23 PC109 1 2 13 19 2 1 2 3 2 + PC120 PC160 + PC119 330U/2V_7 330U/2V_7 *2200P/100V_6 1 PR124 PR125 0 0 B 1 ED8-B -0623-33nf to 68nf PR28 PR27 2.7K/F_4 11K/F_4 68N/X7R/25V_6 2 PC20 470P/X7R-50V_4 10 COMP VO w 6.81K/F_4 14 w 15 PC110 .01U/16V_4 PR129 3.65K/F PR128 10K/F PR127 1/F PR126 *0 VSUM PR84 Panasonic ERT-J1VR103J 18 10K _6 NTC ISEN1 PR123 1K/F_4 PR119 3.48K/F_4 2 1 1 1 2 2 DFB PC107 1 2 17 VW RTN ED8-B -0623-390p to330p VSEN 9 PC113 .01U/16V_4 *2.2 4 PQ36 AOL1412 VSUM 0.22U/X7R/10V_6 1000P/X7R/50V_6 0.36uH 2 1000P/X7R/50V_4 PR112 13.3K/F_4 1 FB PC18 1 PR113 VSUM 2 w .R FB2 1 220P/X7R/50V_4 OCSET 8 DROOP PC15 PL15 1 PR164 PC22 11 2 PC159 *2200P/50V_6 ISEN2 25 PC108 0.1U/X7R/50V_6 4 6262_LG2 VDIFF 1000P/X7R/50V_6 97.6K/F_4 PC118 10U/X6S/25V_1206 PC112 10U/X6S/25V_1206 PC105 1K/F_4 A 29 ISEN2 NC 12 2 PGND2 PC158 2200P/50V_6 6262_PH2 PC115 0.22U/X5R/25V_6 PR118 PR25 LGATE2 30 1K/F_4 PR115 255/F_4 1 43 VR_ON CLKEN# PHASE2 28 VID5 0_4 PR117 6262_UG2 27 PR116 2.2 26 1 2 PC106 0.22U/X5R/25V_8 PR17 <4> H_VID6 <31> VRON B 42 AOL1414 2 4.7U/X6S/25V_8 1 <4> H_VID5 1 PQ37 1 H_VID4 <4> H_VID4 *2.2 2 H_VID1 31 2 <4> H_VID3 PVCC VID0 C PR163 PC116 +5V_S5 0.22U/X5R/25V_6 PC104 2 <4> H_VID2 ISEN1 SOFT 37 <4> H_VID0 <4> H_VID1 24 2 H_VID0 33 ISEN1 ah as 7 1 PC17 0.022U/X7R/50V_6 2 2 PGND1 2 PR24 4.02K/F_4 PC16 1 .01U/16V_4 0 VIN_6262 1 RBIAS 5 *0 PR89 0 ISEN2 2 4 32 1 147K/F LGATE1 2 PR101 1/F PR29 PR88 2 PGD_IN 34 1 PSI# 3 PHASE1 1 2 PGD_IN 10K/F PR30 5 PSI#_1 *0_4 PR31 5 0_4 PR23 PR109 470K_4 NTC DPRSLPVR 35 PR107 2.2 36 1 2 1 2 3 PR106 VR_ON ED8-B -0623-add PR20 *0 BOOT1 3.65K/F 1 PSI# *10K/F_4 PSI#_1 UGATE1 PC103 0.22U/X5R/25V_8 <3> H_PROCHOT# Panasonic ERT-J0EV474J GND_T 16 PR108 GND 49 Throttling temp. 105 degree C +3VSUS C 21 1 Close to Phase 1 Inductor 4 3 PC157 PR32 + PC99 VSUM 2 ISL6262A 0.36uH 2 ia La pt op .c 3V3 PGOOD 1 48 20 22 PU8 VIN PC21 1U/X7R/25V_8 VCC 2 0_8 1 PR114 VCC_CORE *330U/2V_7 PQ33 AOL1412 2 PC100 0.1U/X7R/50V_6 D Yonah: VCC_CORE/ 36A om PC114 0.1U/X7R/50V_6 PR121 10/F PR162 *2.2 1.91K/F_4 1 PSI# PSI# 2 <3> 2 PR21 2 +5V_S5 PL14 1 6262_PH1 PR19 10_4 5 PR120 10/F for ISL6262A PC14 0.1U/X7R/50V_6 1 2 1 2 4 +3V VIN_6262 1 2 3 PWR_MON 4.99K/F PGD_IN 1 1 PR22 Merom: VCC_CORE/ 44A PC88 PC10 PC4 10U/X6S/25V_1206 PC5 470U/25V_10*10.2 0.1U/X7R/50V_6 PC156 10U/X6S/25V_1206 *2200P/50V_6 1 2 3 6262_UG1 4 H_VID2 3 H_VID3 PR161 *2.2 1 H_VID4 PQ30 AOL1414 2 H_VID5 <3,7,14> 2 + D H_VID6 1 VIN 1 PR98 *0 2 PR97 *0 2 PR96 *0 1 PR95 *0 1 PR94 *0 5 PR93 *0 1 +1.05V PC19 0.22U/X5R/25V_6 Close to Phase 1 Inductor ED8-B -0623-3.9k to 3.48k PC117 180P/NPO/50V_4 ISL6262_VO 2 1 PC111 .01U/16V_4 A Parallel PR26 0_4 PR122 0_4 VCCSENSE <4> VSSSENSE <4> PROJECT : ZD1 Size Custom Date: 5 4 3 2 Quanta Computer Inc. Document Number Rev C CPU CORE(ISL6262) Monday, May 07, 2007 Sheet 1 34 of 38 1 2 3 4 5 A ia La pt op .c om A VIN-1.5V PL4 VIN +5V_S5 PC56 2 5 6 7 8 PR53 *.1U_6 12 VOUT LX 11 FBK 4 PGOOD 6 VDDP 9 DL 8 VSSA PGND 7 5 NC TPAD 17 14 NC 13.3K/F PR56 + 11K/F 4 GND GND +1.05V 1R5UH-3.8mR DL-1.5V ah as 0.1U/50V_6 C 10 PL3 PR55 PC44 10U/Y5U/10V_8 PR54 10K/F VOUT=(1+R2/R3)*0.5 C Rdson=15m ohm w w w .R Rdson*Iocp=PR55*10u PC47 560U/2.5V_6X5.7 FDS6690AS PC52 33P/NPO/50V_6 1.5V_FB PQ46 3 2 1 3 ILIM 16A DH-1.5V 21 1 VCCA 18 1000P/X7R/50V_6 PC53 2 0.1U/X7R/50V_6 PC54 2 PC48 1 <31> HWPG_1.05V 2 B FDS8884 1 13 DH PQ45 2 BST VIN GND PR136 *10K 4 4.7U/Y5V/10V_8 3 2 1 EN/PSV 16 PC57 5 6 7 8 15 1 PC49 PC51 .1U/X7R/50V_8 20 47K +3V GND PR57 PU6 SC411MLTRT 19 <31,36,37> MAINON SW1010C 1 B PD5 1 PC50 PR58 1M PC55 .1U/X7R/50V_8 10U/X6S/25V_1206 10U/X6S/25V_1206 2 10 HI0805R800R-00_8 D D PROJECT : ZD1 Quanta Computer Inc. Size Document Number Rev C VTT +1.05V Date: 1 2 3 4 Monday, May 07, 2007 Sheet 5 35 of 38 5 4 3 2 1 D om D +1.8VSUS 5 6 7 8 PR33 PR135 +SMDDR_VREF 0 5VIN PC129 0.033U/50V_6 PR38 5VIN 18 5 GND DRVL 3 VTTGND PGND 16 S3_1.8V PR134 0 PR133 0 MODE S3 11 7 VTTREF S5 12 S5_1.8V 14 5VIN 8 COMP 9 VDDSNS 10 *0 V5IN PGOOD 13 CS 15 VDDQSET 21 22 23 24 25 26 27 DIS_MODE PR35 14K/F PR37 R1 +1.8VSUS PR130 4 MAX Current 10A PC123 + PC23 10U/X5R/10V_8 560U/2.5V_6X5.7 C *2.2/F SUSON <31,37> +3VPCU PQ4 FDS6690AS +3VPCU PC121 *2200P/50V_6 PQ3 *FDS6690AS (10u*PR35)/Rdson+Delta_I/2=Iocp HWPG_1.8V <31> PC128 4.7U/X5R/6.3V_6 ah as R2 PL16 4 5VIN 2 0 PC24 PC124 10U/X6S/25V_1206 10U/X6S/25V_1206 1R5UH-3.8mR MAINON <31,35,37> 100K/F PC32 0 +1.8VSUS PR41 PR132 *1000P/50V_6 +5VPCU 0.1U/X7R/50V_6 17 6 *0 FOR DDR II PR40 PC29 5 6 7 8 20 LL 3 2 1 VBST VTTSNS 5 6 7 8 VTT 4 PC25 *2200P/50V_6 FDS8884 19 3 2 1 DIS_MODE 2 PQ39 3 2 1 10U/X6S/25V_1206 DRVH 1 PC130 VLDOIN GND GND GND GND GND GND GND +SMDDR_VTERM 1 ia La pt op .c 4 PU9 TPS51116 C 2200P/X7R/50V_6 *2.2/F 10U/X6S/25V_1206 10U/X6S/25V_1206 VIN HI0805R800R-00_8 PC126 PC127 PC131 PL17 PR156 110k PR165 76.8k +1.8VSUS B 1 2 5 6 B *0.47U/10V_6 PQ38 FDC653N_NL 3 4 +1.8V +1.8V_MXM PL19 PC161 HI0805R800R-10_6 PC125 0.1U/X7R/50V_6 0.01u/16v_6 MAX Current 3.5A PC162 0.01u/16v_6 PC161 ,PL19 & PC162 near CN27 w w if tune Vout PR38 un-mount, PR156 PR165 mount 0 PC122 1 PR131 w .R R1=(100*Vout-R2)K 2 <33,37> MAIND A A PROJECT : ZD1 Quanta Computer Inc. Size Document Number Date: Monday, May 07, 2007 Rev B DDR 1.8V(TPS51116) 5 4 3 2 Sheet 1 36 of 38 3 2 1 PR34 MAINON 1 2 3 5 VO2 6 +2.5V 3 VIN1 GND1 8 0.5A 4 VIN2 GND2 9 PU2 AT818 0.1U/X7R/50V_6 10U/X5R/6.3V_6 9338DRV 4 D *560U/2.5V_6X5.7 100K_4 5 EN 1 VCC PC41 PR50 20K/F PC133 + Vout1 = (1+Rg/Rh)*0.5 PU5 G9338 ADJ PR51 10K/F PC132 PC134 560U/2.5V_6X5.7 10U/X5R/6.3V_6 MAINON +1.8VSUS C SOT23-5-2_8-95 PU10 *AT5206G-1.5V PC149 *470P/X7R-50V_4 PR154 *0_4 2 1 2 4 BP 1 GND SH <31,33> S5_ON +SMDDR_VREF +1.8VSUS ah as PR155 *0_4 VIN +3VSUS PR74 22 PR73 22 2 PQ19 2N7002E 1 PQ24 2N7002E +1.8V_MXM +1.05V PR60 PR65 1M NC 5 PR46 19.6K/F +2.5V C 34K/F +5V PU3 *G966 4 VPP PGOOD 1 2 VEN 6 3 8 9 VIN GND GND VO +1.2V 1A NC 5 B PR36 *17.4K/F PC30 *10U/Y5U/10V_8 0.8V SUSD <33> PC34 *10U/X5R/6.3V_6 PR42 *34K/F PC69 *2200p_4 +3V PR66 22 Vout =0.8(1+R1/R2) =1.2V +5V PR62 22 +SMDDR_VTERM PR63 22 +1.5V PR64 22 +1.25V PR137 22 15V PR67 22 PR72 1M 3 3 3 3 3 3 A MAIND <33,36> 3 3 MAIND 3 PC40 10U/Y5U/10V_8 Vout =0.8(1+R1/R2) =1.25V *0.1U/Y5V/16V_4 RUN_ON_G 3 +1.25V 2A Add by power on 10/19 PR59 22 22 VIN GND GND PR47 PC33 w 1 PQ20 2N7002E w VIN A 2 PQ22 2N7002E 3 8 9 VO 0.8V *10K/F +1.8VSUS 1 PR79 1M 6 PC39 *0.1U/Y5V/16V_4 PR39 MAINON 3 w .R 2 1 PQ28 DTC144EU 1 <31,36> SUSON 2 1 VEN 0.1U/X7R/50V_6 PR71 1M 3 3 3 2 PR80 22 SUSD 3 SUS_ON_G VPP PGOOD 2 PC31 15V B PR77 1M 10K/F PC147 *1U/X7R-25V_8 PC150 *10U/X6S-25V_1206 2 2 1 3 PR45 4 200mA 5 VOUT 1 VIN PC38 10U/X5R/6.3V_6 +1.5V_S5 2 PC148 *1U/X7R-25V_8 PU4 G966 PC36 0.1U/X7R/50V_6 1 Vout=0.8*[1+(R1/R2)] +5V 0.1U/X7R/50V_6 Rh 0.1U/X7R/50V/_6 +3VPCU PR44 634K/F_4 R2 7 ADJ 0.01U/X7R/50V_6 om 6 Rg 9338EN 4 +5VPCU DRV ia La pt op .c 0_4 PGD GND PR49 3 D PC37 22U/Y5U/6.3V_8 PC35 0.1U/X7R/50V_6 1 PC46 REV:3A MODIFY MAINON PR43 294K/F_4 +1.5V <4,10,13,15,22,23,26,29,30> 2 PR48 <31> HWPG_CPUIO PC28 0.1U/X7R/50V_6 3A 2 +1.5V 0 +3V PC26 PC27 10U/Y5U/10V_8 1U/16V_6 R1 VTT-ADJ 0.8V PR52 ADJ PC45 8 7 6 5 PC42 VO1 EN 7 PC43 + +3VSUS 0/F_6 FDS8884 GND0 2 ADJ PQ5 +1.8VSUS 1 ADJ 4 7 5 2 2 PQ40 2N7002E PQ15 2N7002E PQ21 2N7002E PC71 *2200p_4 1 2 PQ12 2N7002E 1 1 2 PQ11 2N7002E 1 2 PQ10 2N7002E 1 2 PQ14 2N7002E 1 2 PQ8 2N7002E 1 2 PQ13 2N7002E 1 PQ9 DTC144EU 2 PR61 1M 1 2 1 <31,35,36> MAINON PROJECT : ZD1 Quanta Computer Inc. Size Document Number Date: Monday, May 07, 2007 Rev C Discharge (1.5V/2.5V) 5 4 3 2 Sheet 1 37 of 38 5 Model 4 3 1 ZY3 MODEL CHANGE LIST REV FROM 1A X 1A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A Page22 : TV card change support to +1.5V. 1A 2A Page18 : Install R5, depop R7,: Follow customer request use EC to control backlight ON/OFF function. 1A 2A Page14 : GPIO10: Reserve PU, 10K +> It is GPO and OD; GPIO14: Reserve PD, 10K => It is GPI as AC present and active high; Page6 : TV_DCONSEL[0:1], UMA =>NC, External VGA tie to GND. 1A 2A Page10 : Depop R153 & pop L23 for system can not boot Page14 : U36 package didn't math footprint, change P/N. Page26 : Remove R275, install R276; remove R4, install R16; Change R245, R247 power source from +1.5V_S5/+1.5V to +3V_S5/+3V , Follow customer request modem change support to +3VSUS. Page22 : MMB(CN8) PIN define error. 2A Page31 : 2nd FAN change design Page23 : New card power SW (location: U33) change same as ZO1 Page31 : add 2 capacity 0.1uF(C634,C636) in DIGVOL_UP / DIGVOL_DN pins Page28 : MMC card can not be detected , U32(ES2) sample will fix this issue. Page14 : The CLPWROK pin of ICH8 connect with HWPG signal Page22 : change CN7 pin definition for T/P no function. Page24 : change CN8 pin definition MMB no function. ia La pt op .c Page26 : Co-layout ALC268 and 888S Page28 : SD card can not be detected , U32(ES2) sample will fix this issue. Page14 : The signal of KBSMI#_ICH add diode , and it PU to +3V_S5 The signal of LID591#_ICH add diode , and it PU to +3V_S5 for ICH8 electric leakage issue. Page26 : Change subwoofer from 4pin to 5pin connector. 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 1A 2A 2A 2B 2A 2B 2A 2B 2A 2B 2A 2B Page17 : Adding (Q52 & R541 & Q53) extra circuitry to prevent power leakage from system into MXM 2A 2B Page21 : Change power of CIR from +3VPCU and +5VPCU. 2A 2B 2A 2B 2B 3A 2B 3A 2B 3A 2B 3A 2B 3A Page07 : DPLL_REF_CLK, DPLL_REF_CLK#, DPLL_REF_SSCLK and DPLL_REF_SSCLK#. To GND Page36 : Add PI filter to reduce the power ripple of +1.8V. Page16 : Modify SMbus address A2 , The signal of B_SA1 need to PU and B_SA0 need to PD Page26 : add 2 capacity 1uF(C639,C640) for subwoofer ah as Page30 : add capacity 2.2uF(C638) Page31 : AEC pin24 is multi function pin, when EC power up, pin17 will change to JTAG/TCK function not GPIO. So,need to change from pin24 (GPIO47) to pin27 (GPIO52). Page22: Power/B connector add two LED control signal and change to 16 pin from 14-pin for meet ACER LED spec . Page22: Q35 change to AO3413 form DTA114 for increase LED driving power. Page23: BL_ON pull up resistor from 10kohm to 100Khom(R194 ).+3V pull up will cause power on leakage on BL_ON signal due to our VGA have 10kohm pull low. B Page19 : Connect CRT of CN13.16 & 17 to GND for ESD Page22 & 25: 2B 3A 2B 3A C B w .R Page17 : Add capacity 330uF(C647) & Remove R541 2D 2A 1A 2A Page19 : Floating CN13.16 & CN13.17 ,CN14.15 & CN14.16 for ESD test 2C 2A 1A 1A Page31 : Follow customer request 2nd FAN is controlled by EC 2B 1A 1A Page 2 : Add C645 for EMI solution C D om D To X FIRST RELEASED: E200610-3793 (PCB: DA0ZD1MB6A0) 1A ZD1 MB 2 Combine USB/B (CN17) and TV/B(CN30) connector, Connector change to 16 pin. and +5_S5 from 1pin to 2pin. Page25 : Connect HOLE 28 & 29 to GND for ESD Page32~37 : Update power circuit Page37 : Remove 1.2V circuit Page26 : Add 1000pF and 10pF total 4 PCS Location: C648 , C649, C650, C652 (between +5V_ADOand AGND). Page22 : CN8.8 remove +5V & R540 & connect to +3V (K) Page27 : Modify and ADD. AGND bridge (R337,R284,C459 and C472 = 0 Ohm). Page22 : Add D45~D51 for ESD Page28 : Change CN36.37 & 38 ,CN37.37 & 38 ,CN38.42 & 43 from ADOGND and GND. w 3A w Page34 : Remove PR161, PR163, PC156, PC159 Page32 : PD9 Change footprint Page25 : Add EMI Spring Page27 : Add GND & AGND bridge (R546,R540,R408) Page22 : Modify pin define (TV/B(CN30) connector) F A Page23 & 17 : HDMI circuits modify: R297, R410 & R602) . Add level-shifter for MXM_HDMI_DDCCLK and MXM_HDMI_DDCDATA.( Location: Q54 ,Q55 , R75, R63, A PROJECT : ZD1 Quanta Computer Inc. DOC NO. Size Document Number Rev 1A Change list Date: Monday, May 07, 2007 Sheet 5 38 of PROJECT MODEL : ZD1 PART NUMBER: 38 4 APPROVED BY: DRAWING BY: 3 2007/ 2/15 DATE: REVISON: 2 3A 1
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