Wistron LA480 Schematics. Www.s Manuals.com. Rsd Schematics
User Manual: Motherboard Wistron LA480 - Schematics. Free.
Open the PDF directly: View PDF 
.
Page Count: 104
| Download | |
| Open PDF In Browser | View PDF |
5 4 3 2 1 UMA & Optimus Schematics Document D D IVY Bridge(rPGA989) C B Intel PCH(Panther Point) C DY :NotInstalled UMA:UMA platform installed OPS:Optimus HR:Huron River CR:Chief River V: V-Series installed BWistron Corporation A 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Cover Page Size A4 Date: Document Number Rev SD LA480 Friday, January 06, 2012 Sheet 1 of 103 A 5 4 ##OnMainBoard 3 2 Block Diagram (UMA/Optimus co-lay) VRAM 2GB/1GB/512MB4 D DDR3 800MHz Intel CPU NVIDIA N13P-GL (V) N13M-GE1 (B) DDRIII 1066/1333/1600 Channel A DDRIII 1066/1333/1600 Channel B 4,5,6,7,8,9,10 DMI x 4 LVDS USB2.0 x 3 63 PCIE x 1 RTL8111F PCH Panther Point PCIE x 1/USB2.0 x 1 SATA x 1/USB2.0 x 1 ETHERNET (10/100/1000Mb) 49 74 RJ45 CONN 59 31 USB 3.0 x 2 Combo Jack C OUTPUTS VCC_GFXCORE VGA 92 TPS51728 INPUTS OUTPUTS DCBATOUT VGA_CORE TI CHARGER 40 BQ24737 Mini-Card INPUTS OUTPUTS +DC_IN_S5 +PBATT USB x 2 USB 2.0 x 2 44 TPS51640 INPUTS 65 DCBATOUT SYSTEM DC/DC 47 RT8068A OUTPUTS 3D3V_S5 USB x 2 1D8V_S0 B LDO 46 RT8207 17,18,19,20,21,22,23,24,25 SATA x 2 INPUTS 26 HDD Azalia CODEC REALTEK ALC269Q-VC2 5V_S5 56 Flash ROM 8MB 60 OUTPUTS 0D75V_S0 PCB LAYER ODD LPC Bus Analog DMIC 0D75V_S0 1D5V_S3 DDR_VREF_S3 INPUTS SPI (B only) OUTPUTS DCBATOUT 56 Internal DMIC 46 RT8207M 26 ACPI 1.1 USB 2.0 x 1 AZALIA (V only) 3D3V_AUX_S5 5V_S5 3D3V_S5 INPUTS 66 PCIE ports (8) Finger Print 64 CardReader ALCOR AU6435B52 OUTPUTS SYSTEM DC/DC LPC I/F SD/MMC+/MS/ B MS Pro/xD D 41 TPS51225 High Definition Audio SATA ports (6) Finger Print BD 1D05V_VTT INPUTS Mini-Card WLAN USB 3.0/2.0 ports (14) CAMERA DCBATOUT DCBATOUT GLAN REALTEK Intel RGB CRT Bluetooth OUTPUTS SYSTEM DC/DC 71.08111.N03, IC PCIE CTRL RTL8111F-CGT QFN 48P HDMI 50 45 INPUTS SYSTEM DC/DC FDI x 4 x 2 (UMA only) 51 CRT VCC_CORE TPS51219 LA580 91.4TE01.001 11273 SC DDRIII Slot 1 1066/1333/1600 15 83.84,85,86,87 49 DCBATOUT DDRIII Slot 0 1066/1333/1600 14 DDRIII: 1066/1333/1600 MHz LCD OUTPUTS DCBATOUT (Discrete only) HDMI INPUTS SYSTEM DC/DC IVY Bridge PCIe x 16 42~43 TPS51640 LA480 Project Code 91.4TD01.001 PCB P/N 11264 Revision SC 88,89,90,91 C 1 CPU DC/DC L1:Top L2:GND L3:Signal L4:Signal LPC debug port L5:VCC L6:Signal L7:GND L8:Signal 71 29 KBC NUVOTON NPCE885G A SMBus 27 A 2CH SPEAKER Wistron Corporation 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih, Taipei Hsien 221, Taiwan, R.O.C G-Sensor (V only) 79 Touch PAD 69 Int. KB 69 Thermal EMC2103-2-AP 2528 Fan Title Block Diagram 28 Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 2 of 103 5 PCH Strapping Name SPKR D 4 3 Processor Strapping Chief River Schematic Checklist Rev0.72 Schematics Notes Reboot option at power-up Default Mode: Internal weak Pull-down. No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ - 10-kΩ weak pull-up resistor. INIT3_3V# Weak internal pull-up. Leave as "No Connect". GNT3#/GPIO55 GNT2#/GPIO53 GNT1#/GPIO51 GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail. Configuration (Default value for each bit is 1 unless specified otherwise) CFG[2] PCI-Express Static Lane Reversal 1: 0: Disable Danbury:Left floating, no pull-down required. C HAD_DOCK_EN# /GPIO[33] CFG[7] Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. GPIO8 0 11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training D 11 1 DMI termination voltage. Weak internal pull-up. Do not pull low. Low (0) - Flash Descriptor Security will be overridden. Also, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features. High (1) - Security measure defined in the Flash Descriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for strapping functions. HDA_SDO GPIO15 1 15 -> 0, 14 -> 1, ... PCI-Express Port Bifurcation Straps Disable Danbury: Leave floating (internal pull-down) NC_CLE Normal Operation. Lane Numbers Reversed Default Value Disabled - No Physical Display Port attached to 1: Embedded DisplayPort. Enabled - An external Display Port device is 0: connectd to the EMBEDDED display Port CFG[4] CFG[6:5] NV_ALE Chief River Schematic Checklist Rev0.72 Strap Description Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor] 1 Pin Name SPI_MOSI Enable Danbury: 2 Low(0) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality. High(1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality. Note : This is an un-muxed signal. This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#. CRB has a 1-kohm pull-up on this signal to +3.3VA rail. GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is enabled. Voltage Rails POWER PLANE VOLTAGE 5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 1D0V_S0 VCCSA 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0 5V 3.3V 1.8V 1.5V 1.05V 1.0V 0.9 - 0.675V 0.75V 0.35V to 1.5V 0.4 to 1.25V 1.8V 3.3V 1V DESCRIPTION 5V_USBX_S3 1D5V_S3 DDR_VREF_S3 5V 1.5V 0.75V BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5 6V-14.1V 6V-14.1V 5V 5V 3.3V 3.3V 1D05V_LAN 1.05V 3D3V_M 1D05V_M 3.3V 1.05V S0/M0, SX/M3, WOL_EN 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states 3D3V_AUX_S5 3.3V G3, Sx Powered by Li Coin Cell in G3 and 3D3V_S5 in Sx ACTIVE IN C S0 CPU Core Rail Graphics Core Rail S3 All S states AC Brick Mode only ON whenever iAMT is active S0/M0, SX/M3 B B Default = Do not connect (floating) High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails. GPIO27 PCIe Routing LANE1 A X USB Table port9 Pair is debug port Device USB3.0 ext port 1 USB3.0 ext port 2 I 2 C / SMBus Addresses 2 USB3.0 ext port 3 Device 3 USB3.0 ext port 4 Mini Card2(WWAN) LANE3 Card Reader 4 BLUETOOTH (USB1.1) LANE4 Mini Card1(WLAN) 5 Fingerprint (USB1.1) 6 X LANE5 X 7 X LANE6 Intel GBE LAN / LAN 8 Mini Card2 (WWAN) 9 USB ext. port 4 / E-SATA /USB CHARGER X 10 CARD READER LANE8 Express Card 11 Mini Card1 (WLAN) 12 CCD 13 New Card 5 4 SATA SMBus ADDRESSES 1 LANE2 SATA Table Pair 0 LANE7 ON for iAMTLegacy WOL Chief River CRV Ref Des Address Hex Bus EC SMBus 1 Battery CHARGER BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA EC SMBus 2 PCH eDP SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA PCH SMBus SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot G-Sensor MINI PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK Device 0 HDD1 1 mSATA 2 N/A 3 N/A 4 ODD 5 ESATA A Wistron Corporation 3 2 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Table of Content Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 3 of 103 5 4 SSID = CPU 3 01.00IVY.000 IVY BRIDGE ORCAD SYMBOL. Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap. 1D05V_VTT 19 DMI_RXP[3:0] 19 FDI_TXN[7:0] C DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 B28 B26 A24 B23 DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 G21 E22 F21 D21 DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 G22 D22 F20 C21 DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3 FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 A21 H19 E19 F18 B21 C20 D18 E17 FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 A22 G19 E20 G18 B20 C19 D19 F17 FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3 19 FDI_FSYNC0 19 FDI_FSYNC1 J18 J17 FDI0_FSYNC FDI1_FSYNC 19 FDI_INT H20 FDI_INT 19 FDI_LSYNC0 19 FDI_LSYNC1 J19 H17 FDI0_LSYNC FDI1_LSYNC A18 A17 B16 EDP_COMPIO EDP_ICOMPO EDP_HPD C15 D15 EDP_AUX EDP_AUX# C17 F16 C16 G15 EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3 C18 E16 D16 F15 EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3 Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap. 19 FDI_TXP[7:0] Note: Lane reversal does not apply to FDI sideband signals. B27 B25 A25 B24 R402 1 2 24D9R2F-L-GP DP_COMP R403 1 2 10KR2J-3-GP eDP_HPD DY B eDP 1D05V_VTT PCI EXPRESS* - GRAPHICS 19 DMI_RXN[3:0] DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI 19 DMI_TXP[3:0] SANDY Intel(R) FDI 19 DMI_TXN[3:0] 1 Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils. 1 OF 9 CPU1A D 2 R401 1 24D9R2F-L-GP NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO J22 J21 H22 PEG_IRCOMP_R PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15 K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0 PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0 PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15 M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0 C401 C402 C403 C404 C405 C406 C407 C408 C409 C410 C411 C412 C413 C414 C415 C416 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0 PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15 M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25 PEG_C_TXP15 PEG_C_TXP14 PEG_C_TXP13 PEG_C_TXP12 PEG_C_TXP11 PEG_C_TXP10 PEG_C_TXP9 PEG_C_TXP8 PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0 C417 C418 C419 C420 C421 C422 C423 C424 C425 C426 C427 C428 C429 C430 C431 C432 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0 2 PEG_RXN[0..15] D 83 PEG_RXP[0..15] 83 C PEG Static Lane Reversal PEG_TXN[0..15] 83 PEG_TXP[0..15] 83 B SANDY NOTE: Select a Fast FET similar to 2N7002E whose rise/ fall time is less than 6 ns. If HPD on eDP interface is disabled, connect it to CPU VCCIO via a 10-kΩ pull-Up resistor on the motherboard. A Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils. SKT-BGA989C470395-1H180 62.10055.421 2nd = 62.10040.771 NOTE. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort. A Wistron Corporation 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (PCIE/DMI/FDI) Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 4 of 103 5 4 SSID = CPU 3 SANDY SNB_IVB# AN34 SKTOCC# 1D05V_VTT TP501 SKTOCC#_R 1 C502 SC47P50V2JN-3GP TP502 1 H_CATERR# AL33 CATERR# AN33 PECI A28 A27 DPLL_REF_SSCLK DPLL_REF_SSCLK# A16 A15 CLK_EXP_P CLK_EXP_N 20 20 CLK_DP_P_R CLK_DP_N_R CLK_DP_N_R 1 CLK_DP_P_R 2 SM_DRAMRST# 37 H_PECI 1 R513 27,42 H_PROCHOT# 2 H_PROCHOT#_R 56R2J-4-GP AL32 PROCHOT# AN32 THERMTRIP# Connect EC to PROCHOT# through inverting OD buffer. 22,36 H_THERMTRIP# SM_DRAMRST# DDR3 MISC 22,27 THERMAL Intel recommends 43pf 1 H_PROCHOT# 2 BCLK BCLK# 2 D 1 R501 62R2J-GP 1 Disabling Guidelines: If motherboard only supports external graphics: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistorpower (~15 mW) may be wasted. Need Add Test Point CLOCKS C26 MISC C26: PROC_SELECT# 22 H_SNB_IVB# 2 2 OF 9 CPU1B V8 BUF_CPU_RST# 2 R509 750R2F-GP 1 1 R510 1K5R2F-2-GP AR33 UNCOREPWRGOOD SM_DRAMPWROK RESET# 1 PLT_RST# AP33 PM_SYNC C501 SC220P50V2KX-3GP JTAG & BPM AM34 2 H_CPUPW RGD_R 0R0402-PAD 2 10KR2J-3-GP PWR MANAGEMENT 1 R504 1 R503 37 VDDPW RGOOD 18,27,31,36,65,66,71,80,82,83,97 AK1 A5 A4 SM_RCOMP_0 R506 1 SM_RCOMP_1 R507 1 SM_RCOMP_2 R508 1 D 0511-CHECK 1 4K99R2F-L-GP 2 140R2F-GP 2 25D5R2F-GP 2 200R2F-L-GP In order to minimize resistance, use thick traces to route all COMP signals, use 10-mils wide trace for routing less than 500 mils, or 20-mils wide trace for routing between 500 mils and 1000 mils. Keep 20-mils spacing to any other signals in order to minimize crosstalk. 1D05V_VTT 19 H_PM_SYNC C 2 R502 Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils. If PROCHOT# is not used, then it must be terminated with a 68ohm ±5% pull-up resistor to VTT. 22,97 H_CPUPW RGD SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST# R8 1D05V_VTT RN502 SRN1KJ-7-GP 4 3 PRDY# PREQ# AP29 AP27 XDP_PRDY# XDP_PREQ# 1 1 TP511 TP512 TCK TMS TRST# AR26 AR27 AP30 XDP_TCLK XDP_TMS XDP_TRST# 1 TP513 TDI TDO AR28 AP26 XDP_TDI XDP_TDO 1 DBR# AL35 XDP_DBRESET# BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7 AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 XDP_TDO R523 1 2 51R2J-2-GP RN501 XDP_TMS XDP_TDI XDP_TCLK XDP_TRST# TP516 1 2 3 4 8 7 6 5 C SRN51J-1-GP 2 2 DY 0511-CHECK SANDY 62.10055.421 2nd = 62.10040.771 SKT-BGA989C470395-1H180 3D3V_S0 B A DEL DEL DEL DEL DEL ASM ASM U501 R519 C503 R517 R515 R510 R509 19 XDP_DBRESET# XDP_DBRESET# 1 R516 2 1KR2J-1-GP B A Wistron Corporation 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (THERMAL/CLOCK/PM ) Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 5 of 103 5 4 3 2 1 SSID = CPU 3 OF 9 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 D C B 14 14 14 14 14 14 M_A_BS0 M_A_BS1 M_A_BS2 C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 AE10 AF10 V6 SA_BS0 SA_BS1 SA_BS2 AE8 AD9 AF9 M_A_CAS# M_A_RAS# M_A_W E# SA_CAS# SA_RAS# SA_WE# DDR SYSTEM MEMORY A SANDY 14 M_A_DQ[63:0] 4 OF 9 CPU1D SANDY SA_CLK0 SA_CLK#0 SA_CKE0 AB6 AA6 V9 SA_CLK1 SA_CLK#1 SA_CKE1 AA5 AB5 V10 SA_CLK2 SA_CLK#2 SA_CKE2 AB4 AA4 W9 SA_CLK3 SA_CLK#3 SA_CKE3 AB3 AA3 W10 SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3 AK3 AL3 AG1 AH1 M_A_DIM0_CS#0 14 M_A_DIM0_CS#1 14 SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3 AH3 AG3 AG2 AH2 M_A_DIM0_ODT0 14 M_A_DIM0_ODT1 14 M_A_DIM0_CLK_DDR0 14 M_A_DIM0_CLK_DDR#0 14 M_A_DIM0_CKE0 14 15 M_B_DQ[63:0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_A_DIM0_CLK_DDR1 14 M_A_DIM0_CLK_DDR#1 14 M_A_DIM0_CKE1 14 SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7 C4 G6 J3 M6 AL6 AM8 AR12 AM15 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 D4 F6 K3 N6 AL5 AM9 AR11 AM14 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15 AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 M_A_DQS#[7:0] 14 M_A_DQS[7:0] 14 M_A_A[15:0] 14 15 15 15 15 15 15 M_B_BS0 M_B_BS1 M_B_BS2 M_B_CAS# M_B_RAS# M_B_W E# C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 AA9 AA7 R6 AA10 AB8 AB9 SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 DDR SYSTEM MEMORY B CPU1C SB_CAS# SB_RAS# SB_WE# SANDY 62.10055.421 2nd = 62.10040.771 62.10055.421 2nd = 62.10040.771 AE2 AD2 R9 SB_CLK1 SB_CLK#1 SB_CKE1 AE1 AD1 R10 SB_CLK2 SB_CLK#2 SB_CKE2 AB2 AA2 T9 SB_CLK3 SB_CLK#3 SB_CKE3 AA1 AB1 T10 SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3 AD3 AE3 AD6 AE6 M_B_DIM0_CS#0 15 M_B_DIM0_CS#1 15 SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3 AE4 AD4 AD5 AE5 M_B_DIM0_ODT0 15 M_B_DIM0_ODT1 15 M_B_DIM0_CLK_DDR0 15 M_B_DIM0_CLK_DDR#0 15 M_B_DIM0_CKE0 15 D M_B_DIM0_CLK_DDR1 15 M_B_DIM0_CLK_DDR#1 15 M_B_DIM0_CKE1 15 SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7 D7 F3 K6 N3 AN5 AP9 AK12 AP15 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 C7 G3 J6 M3 AN6 AP8 AK11 AP14 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 C M_B_DQS#[7:0] 15 M_B_DQS[7:0] 15 B SB_BS0 SB_BS1 SB_BS2 SANDY SB_CLK0 SB_CLK#0 SB_CKE0 M_B_A[15:0] 15 A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 5 4 3 2 Size A3 Document Number Date: Friday, January 06, 2012 CPU (DDR) Rev SD LA480 Sheet 1 6 of 103 5 4 3 2 SSID = CPU 1 1 1 TP703 1 2 1: Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 1 CFG4 TP704 Display Port Presence Strap R703 1KR2J-1-GP 2 DY CFG4 1 CFG16 AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 AJ31 AH31 AJ33 AH33 RSVD#AJ31 RSVD#AH31 RSVD#AJ33 RSVD#AH33 AJ26 RSVD#AJ26 1: Disabled; No Physical Display Port attached to Embedded Display Port 0: Enabled; An external Display Port device is connected to the Embedded Display Port B4 D1 12 DDR_W R_VREF01 12 DDR_W R_VREF02 C TP705 1 H_VCCP_SEL RSVD#B4 RSVD#D1 F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 RSVD#F25 RSVD#F24 RSVD#F23 RSVD#D24 RSVD#G25 RSVD#G24 RSVD#E23 RSVD#D23 RSVD#C30 RSVD#A31 RSVD#B30 RSVD#B29 RSVD#D30 RSVD#B31 RSVD#A30 RSVD#C29 J20 B18 A19 RSVD#J20 RSVD#B18 RSVD#A19 J15 RSVD#J15 SANDY RESERVED CFG2 OPS D TP717 TP702 PEG Static Lane Reversal - CFG2 is for the 16x R702 1KR2J-1-GP 5 OF 9 CPU1E CFG2 1 RSVD#L7 RSVD#AG7 RSVD#AE7 RSVD#AK2 RSVD#W8 L7 AG7 AE7 AK2 W8 RSVD#AT26 RSVD#AM33 RSVD#AJ27 AT26 AM33 AJ27 RSVD#T8 RSVD#J16 RSVD#H16 RSVD#G16 T8 J16 H16 G16 RSVD#AR35 RSVD#AT34 RSVD#AT33 RSVD#AP35 RSVD#AR34 AR35 AT34 AT33 AP35 AR34 RSVD#B34 RSVD#A33 RSVD#A34 RSVD#B35 RSVD#C35 D B34 A33 A34 B35 C35 C RSVD#AJ32 RSVD#AK32 AJ32 AK32 RSVD#AH27 AH27 TP713 1 TP720 RSVD#AN35 RSVD#AM35 AN35 AM35 CLK_XDP_ITP_P CLK_XDP_ITP_N 1 1 TP718 TP719 RSVD#AT2 RSVD#AT1 RSVD#AR1 AT2 AT1 AR1 B B SANDY SKT-BGA989C470395-1H180 62.10055.421 2nd = 62.10040.771 CFG5 1 R704 1KR2J-1-GP 2 DY DY 2 PCIE Port Bifurcation Straps R701 1KR2J-1-GP 1 CFG6 CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled 1 CFG7 DY PEG DEFER TRAINING R705 1KR2J-1-GP CFG7 2 A A Wistron Corporation 1: PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 5 4 3 2 Size A3 Document Number Date: Friday, January 06, 2012 CPU (RESERVED) LA480 Sheet 1 7 of Rev SD 103 5 4 3 CPU1F VCC CORE:53A 0511-CHECK CAP. POWER 2 6 OF 9 VCCIO:8.5A 0511-CHECK CAP. VCC_CORE 1 SANDY 0511-CHECK 1D05V_VTT 1 2 1 1 C845 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 R807 SVID C VIDALERT# VIDSCLK VIDSOUT AJ29 AJ30 AJ28 H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT 1 R803 2 75R2F-2-GP 2 43R2J-GP 1D05V_VTT VR_SVID_ALERT# 42 H_CPU_SVIDCLK 42 H_CPU_SVIDDAT 42 B 1 R804 0511-CHECK 2 130R2F-1-GP 1D05V_VTT 1 check Place neer PCU pin. 1D05V_VTT 1 VCCIO_SENSE VSSIO_SENSE 1 R801 100R2F-L1-GP-U R809 10R2F-L-GP 2 AJ35 AJ34 42 42 2 VCCSENSE VSSSENSE 1 VCC_SENSE VSS_SENSE VCCIO_SENSE VSSIO_SENSE B10 A10 2 R808 10R2F-L-GP VCC_CORE R802 100R2F-L1-GP-U VCCIO_SENSE 45 VSSIO_SENSE 45 2 1 2 1 2 1 2 1 2 1 2 1 2 DY For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7 For CRB VIDALERT# need to pull high 75 ohm close to CPU SENSE LINES CORE SUPPLY 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 C844 SC10U6D3V5KX-1GP 1 D 1D05V_VTT C843 SC10U6D3V5KX-1GP 2 2 1 2 C841 SC10U6D3V5KX-1GP C842 C840 DY SC10U6D3V5KX-1GP C830 SC10U6D3V5KX-1GP 1 C839 SC10U6D3V5KX-1GP C829 SC10U6D3V5KX-1GP 2 C838 SC10U6D3V5KX-1GP C814 SC10U6D3V5KX-1GP 1 C810 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP C813 SC10U6D3V5KX-1GP 2 C809 SC10U6D3V5KX-1GP J23 C808 Reserve C846 & C847 C812 SC10U6D3V5KX-1GP VCCIO C807 SC10U6D3V5KX-1GP E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 C806 SC10U6D3V5KX-1GP A VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO C805 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP B VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 SC10U6D3V5KX-1GP C828 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC SC10U6D3V5KX-1GP C831 C827 SC10U6D3V5KX-1GP C832 DY C826 SC10U6D3V5KX-1GP C833 C825 SC10U6D3V5KX-1GP C834 C824 SC10U6D3V5KX-1GP DY C820 SC10U6D3V5KX-1GP C823 C811 SC10U6D3V5KX-1GP C819 SC10U6D3V5KX-1GP C835 DY SC10U6D3V5KX-1GP C822 C804 SC10U6D3V5KX-1GP C818 SC10U6D3V5KX-1GP C836 C803 SC10U6D3V5KX-1GP C837 C821 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP C C817 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP C816 DY SC10U6D3V5KX-1GP C815 C802 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP 1 C801 D AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 PEG AND DDR VCC_CORE A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Custom SANDY 62.10055.421 2nd = 62.10040.771 5 4 Date: 3 2 CPU (VCC_CORE) Rev SD LA480 Sheet Friday, January 06, 2012 1 8 of 103 5 4 3 2 1 VCC_GFXCORE 2 2 1 2 1 2 1 C914 C 1 C917 2 1 C915 2 1 C913 VCCSA VCCA:6A 2 C912 2 1 2 1 C911 1 C910 DY 2 C909 2 VREF DDR3 -1.5V RAILS VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA M27 M26 L26 J26 J25 J24 H26 H25 VCCSA_SENSE H23 VCCSA_SENSE 48 FC_C22 VCCSA_VID1 C22 C24 VCCSA_SELECT0 48 VCCSA_SELECT1 48 +V0.85S - VCCSA - System Agent rail voltage can be [0.9, 0.725, 0.8, 0.675] V for IVB [0.9, 0.8] V for SNB B 4 3 SA RAIL 1.8V RAIL 1 SANDY RN901 SRN1KJ-7-GP 62.10055.421 2nd = 62.10040.771 1 2 2 1 2 1 2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ SC10U6D3V5KX-1GP 1 1D5V_S0 VDDQ:5A AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 SC10U6D3V5KX-1GP 2 Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width. SC10U6D3V5KX-1GP VCCPLL VCCPLL VCCPLL +V_SM_VREF_CNT 37 SC10U6D3V5KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP B6 A6 A2 C924 AL1 SM_VREF SC10U6D3V5KX-1GP C922 +V_SM_VREF_CNT should have 10 mil trace width SC10U6D3V5KX-1GP C923 D R907 100R2F-L1-GP-U Refer to the latest Huron River Mainstream PDG (Doc# 436735) for more details on S3 power reduction implementation. SC10U6D3V5KX-1GP VCCPLL:1.2A VCC_AXG_SENSE VSS_AXG_SENSE VCC_AXG_SENSE 42 VSS_AXG_SENSE 42 SC10U6D3V5KX-1GP C926 AK35 AK34 VAXG_SENSE VSSAXG_SENSE C916 B 1D8V_S0 R906 100R2F-L1-GP-U 7 OF 9 SC10U6D3V5KX-1GP C SANDY MISC 1 2 DY VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG GRAPHICS 1 2 RC902 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 DY SC33P50V2JN-3GP SC10U6D3V5KX-1GP 1 C921 AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 RC901 SC33P50V2JN-3GP C920 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP 2 C906 SC10U6D3V5KX-1GP C919 C905 SC10U6D3V5KX-1GP C918 C904 SC10U6D3V5KX-1GP C908 C903 SC10U6D3V5KX-1GP C907 SC10U6D3V5KX-1GP 2 C902 SC10U6D3V5KX-1GP 1 C901 2 PROCESSOR VAXG: 24A D SENSE LINES 0511-CHECK 1 POWER CPU1G VCC_GFXCORE 1 0511-CHECK CAP A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU (VCC_GFXCORE) 5 4 3 2 Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 9 of 103 5 4 3 2 1 SSID = CPU 8 OF 9 CPU1H AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 D C B VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SANDY VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 9 OF 9 CPU1I AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SANDY VSS SANDY SANDY 62.10055.421 2nd = 62.10040.771 62.10055.421 2nd = 62.10040.771 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 D C B A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 5 4 3 2 CPU (VSS) Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 10 of 103 5 4 3 2 1 D C D BLANK C B B Wistron Corporation A 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A4 Document Number LA480 Date: Friday, January 06, 2012 Rev SD Sheet 11 of 103 A 5 4 3 2 1 VREF circuit -M1 (Voltage Driver Network) & M3 (Driven by Processor) Implementation CAD Note: All VREF traces should have 20:20 mil trace geometry. Note that while 20 mil trace width is optimal, short violations is acceptable if required due to tight routing constraints. SA_DIMM_VREFDQ 1 R1226 DY SB_DIMM_VREFDQ 2 0R2J-2-GP Driven by process (PIN#B4) 1 R1208 2 0R2J-2-GP D U1201 U1202 S 1 DDR_W R_VREF01_B4 D DY S 7 DDR_W R_VREF02 1 7 DDR_W R_VREF01 D R1227 1KR2F-3-GP G DY DDR_W R_VREF01_D1 G 2N7002K-2-GP 2 2N7002K-2-GP 2 R1228 1KR2F-3-GP DY Driven by process (PIN#D1) 84.2N702.J31 2ND = 84.2N702.031 84.2N702.J31 2ND = 84.2N702.031 20,37 DRAMRST_CNTRL_PCH 20,37 DRAMRST_CNTRL_PCH DDR_W R_VREF01_B4 2 DDR_VREF_S3 1 DDR_VREF_S3 SODDIM0 R1204 0R0402-PAD C 1 2 R1222 0R0402-PAD 1 M_VREF_CA_DIMM0 1 C1201 SCD1U10V2KX-4GP 2 R1209 0R2J-2-GP 2 1 M_VREF_DQ_DIMM0 1 2 CLOSE PIN1 C 1 2 R1203 0R0402-PAD R1232 0R0402-PAD +V_SM_VREF 37 C1203 SCD1U10V2KX-4GP 2 1 DY R1218 0R0402-PAD 1+V_VREF_PATH3 2 +V_VREF_PATH1 CLOSE PIN 1 DY R1219 0R2J-2-GP DDR_W R_VREF01_D1 2 1 D R1221 0R0402-PAD 2 1 B DDR_VREF_S3 2 R1217 0R0402-PAD B DDR_VREF_S3 R1225 0R2J-2-GP 2 DY 1 2 R1207 0R0402-PAD 1 DY2 R1216 0R2J-2-GP M_VREF_DQ_DIMM1 M_VREF_CA_DIMM1 1 2 1 1 SODDIM1 C1202 SCD1U10V2KX-4GP 2 2 R1210 0R0402-PAD C1204 SCD1U10V2KX-4GP CLOSE PIN CLOSE PIN +V_VREF_PATH2 <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 5 4 3 2 Size A3 Document Number Date: Friday, January 06, 2012 M3 Rev SD LA480 Sheet 1 12 of 103 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title <Title> Size A4 Document Number LA480 Date: Friday, January 06, 2012 Rev SD Sheet 13 of 103 A 5 4 126 1 15,37 DDR3_DRAMRST# 30 0D75V_S0 203 204 200 202 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2 2 PCH_SMBDATA 15,20,65,66 PCH_SMBCLK 15,20,65,66 198 3D3V_S0 TS#_DIMM0_1 15 199 C1401 SCD1U10V2KX-5GP C1402 SC2D2U10V3KX-1GP TS#_DIMM0_1 1D5V_S3 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 1 R1403 10KR2J-3-GP 2 SODIMM A DECOUPLING 1D5V_S3 C 0511-CHECK 1 1 DY C1410 DY 2 DY C1409 2 1 C1408 2 1 C1407 2 1 C1406 2 1 2 1 2 C1416 DY C1417 1 C1415 C1405 2 C1414 Layout Note: Place these Caps near SO-DIMMB. 1 DY C1404 2 C1403 1 TC1401 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206 Thermal EVENT 3D3V_S0 DY 2 77 122 125 1 197 201 SA0_DIM0 SA1_DIM0 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 1 1 2 If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32 2 1 1 2 1 2 1 2 1 2 2 116 120 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD D SC10U6D3V5KX-1GP 6 M_A_DIM0_ODT0 6 M_A_DIM0_ODT1 M_VREF_CA_DIMM0 M_VREF_DQ_DIMM0 11 28 46 63 136 153 170 187 SC10U6D3V5KX-1GP 12 29 47 64 137 154 171 188 NC#77 NC#122 NC#125/TEST Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30 SC10U10V5ZY-1GP M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 SA0 SA1 M_A_DIM0_CLK_DDR1 6 M_A_DIM0_CLK_DDR#1 6 R1402 10KR2J-3-GP SCD1U10V2KX-5GP B VDDSPD 102 104 SCD1U10V2KX-5GP 6 6 EVENT# 6 6 M_A_DIM0_CLK_DDR0 6 M_A_DIM0_CLK_DDR#0 6 SCD1U10V2KX-5GP M_A_DQS[7:0] 10 27 45 62 135 152 169 186 SDA SCL M_A_DIM0_CKE0 M_A_DIM0_CKE1 101 103 SCD1U10V2KX-5GP SC10U6D3V5KX-1GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP M_A_DQS#[7:0] M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 73 74 R1401 10KR2J-3-GP SC10U6D3V5KX-1GP C1418 DY CK1 CK1# BA0 BA1 6 6 SC10U6D3V5KX-1GP C1422 DY CK0 CK0# M_A_DIM0_CS#0 M_A_DIM0_CS#1 SC10U10V5ZY-1GP C1421 CKE0 CKE1 114 121 6 6 6 SC10U6D3V5KX-1GP C1420 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 CS0# CS1# SA1_DIM0 M_A_RAS# M_A_WE# M_A_CAS# SC10U6D3V5KX-1GP Place these caps close to VTT1 and VTT2. DY 1 SA0_DIM0 110 113 115 ST330U2VDM-4-GP C1419 2 NP1 NP2 2 C M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 NP1 NP2 RAS# WE# CAS# 1 109 108 6 M_A_BS0 6 M_A_BS1 M_A_DQ[63:0] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 2 6 M_A_BS2 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79 1 6 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 2 D 6 1 M_A_A[15:0] 2 SSID = MEMORY 0D75V_S0 3 DIMM1 B DDR3-204P-96-GP-U1 62.10017.V61 2ND = *62.10017.X51 3RD = *62.10017.V61 (H=8mm) A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DDR3-SODIMM1 5 4 3 2 Size A2 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 14 of 103 5 4 SSID = MEMORY 203 204 PCH_SMBDATA 14,20,65,66 PCH_SMBCLK 14,20,65,66 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2 1 C1502 SC2D2U10V3KX-1GP SA1_DIM1 SA0_DIM1 0511-CHECK 1 1D5V_S3 R1502 10KR2J-3-GP 2 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34 C SO-DIMMB is placed farther from the Processor than SO-DIMMA 1D5V_S3 SODIMM B DECOUPLING C1510 1 C1509 DY 2 1 1 C1508 DY 2 1 C1507 2 1 2 1 2 C1513 C1506 C1514 1 C1512 C1505 2 C1511 C1504 DY 1 C1503 DY 1 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206 2 DY 2 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# 77 122 125 1 C1501 SCD1U10V2KX-5GP 2 SA0_DIM1 SA1_DIM1 2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS R1501 10KR2J-3-GP 199 197 201 1 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 3D3V_S0 3D3V_S0 TS#_DIMM0_1 14 2 198 2 1 2 1 2 1 2 1 0D75V_S0 200 202 SC10U6D3V5KX-1GP 30 14,37 DDR3_DRAMRST# NC#1 NC#2 NC#/TEST D SC10U6D3V5KX-1GP 126 1 M_VREF_CA_DIMM1 M_VREF_DQ_DIMM1 SA0 SA1 M_B_DIM0_CLK_DDR1 6 M_B_DIM0_CLK_DDR#1 6 11 28 46 63 136 153 170 187 SC10U10V5ZY-1GP 116 120 6 M_B_DIM0_ODT0 6 M_B_DIM0_ODT1 VDDSPD 102 104 SCD1U10V2KX-5GP 12 29 47 64 137 154 171 188 EVENT# M_B_DIM0_CLK_DDR0 6 M_B_DIM0_CLK_DDR#0 6 SCD1U10V2KX-5GP 6 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 SDA SCL 6 6 101 103 SCD1U10V2KX-5GP M_B_DQS[7:0] 6 10 27 45 62 135 152 169 186 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 M_B_DIM0_CKE0 M_B_DIM0_CKE1 SCD1U10V2KX-5GP M_B_DQS#[7:0] B M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 CK1 CK1# BA0 BA1 6 6 73 74 SC10U6D3V5KX-1GP C1521 SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP 2 1 6 6 6 SC10U6D3V5KX-1GP C1520 DY CK0 CK0# M_B_DIM0_CS#0 M_B_DIM0_CS#1 SC10U6D3V5KX-1GP C1519 CKE0 CKE1 M_B_RAS# M_B_WE# M_B_CAS# 114 121 SC10U10V5ZY-1GP Place these caps close to VTT1 and VTT2. 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 CS0# CS1# 110 113 115 SC10U10V5ZY-1GP C1518 DY 2 NP1 NP2 1 C M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 NP1 NP2 RAS# WE# CAS# 2 109 108 6 M_B_BS0 6 M_B_BS1 M_B_DQ[63:0] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 1 6 M_B_BS2 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79 2 6 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 1 D 6 2 M_B_A[15:0] 0D75V_S0 3 DIMM2 B DDR3-204P-144-GP-U1 (H=4mm) 62.10024.G21 2nd = *62.10017.X41 3rd = *62.10017.V51 62.10017.X41 3RD:62.10017.V51 A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DDR3-SODIMM2 5 4 3 2 Size A2 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 15 of 103 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DDR3-SODIMM2 Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 16 of 1 103 A A B C D E 3D3V_S0 RN1701 L_CTRL_DATA L_CTRL_CLK J47 M45 L_BKLTEN L_VDD_EN 49 L_BKLT_CTRL P45 L_BKLTCTL 49 LVDS_DDC_CLK_R 49 LVDS_DDC_DATA_R L_CTRL_CLK L_CTRL_DATA T40 K47 L_DDC_CLK L_DDC_DATA T45 P39 L_CTRL_CLK L_CTRL_DATA LVDS_IBG AF37 AF36 LVD_IBG LVD_VBG LVDS_VREFH LVDS_VREFL AE48 AE47 LVD_VREFH LVD_VREFL 49 LVDSA_CLK# 49 LVDSA_CLK AK39 AK40 LVDSA_CLK# LVDSA_CLK 49 LVDSA_DATA0# 49 LVDSA_DATA1# 49 LVDSA_DATA2# AN48 AM47 AK47 AJ48 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 AN47 AM49 AK49 AJ47 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 AF40 AF39 LVDSB_CLK# LVDSB_CLK RN1705 SRN150F-1-GP AH45 AH47 AF49 AF45 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 Close to PCH AH43 AH49 AF47 AF43 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 1 L_BKLT_EN LVDS_VDD_EN 3 4 SRN100KJ-6-GP RN1704 R1701 2K37R2F-GP Close to PCH 2 1 3 4 2 SRN0J-6-GP Close to PCH and keep 20mil away from other signal. 49 LVDSA_DATA0 49 LVDSA_DATA1 49 LVDSA_DATA2 0511-CHECK CRT_RED CRT_BLUE CRT_GREEN 5 6 7 8 50 CRT_HSYNC 50 CRT_VSYNC DAC_IREF_R 1 1 2 1 2 DY R1702 1KR2D-1-GP N48 P49 T49 CRT_BLUE CRT_GREEN CRT_RED T39 M40 CRT_DDC_CLK CRT_DDC_DATA M47 M49 CRT_HSYNC CRT_VSYNC T43 T42 DAC_IREF CRT_IRTN AP43 AP45 SDVO_STALLN SDVO_STALLP AM42 AM40 SDVO_INTN SDVO_INTP AP39 AP40 3D3V_S0 RN1706 SRN2K2J-1-GP DDI Port B Detect:(SDVO_CTRL_ DATA) 1: Port B detected 0: Port B not detected P38 M39 DDPB_AUXN DDPB_AUXP DDPB_HPD AT49 AT47 AT40 DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49 DDPC_CTRLCLK DDPC_CTRLDATA 4 PCH_HDMI_CLK 51 PCH_HDMI_DATA 51 HDMI_PCH_DET 51 HDMI_DATA2_R# 51 HDMI_DATA2_R 51 HDMI_DATA1_R# 51 HDMI_DATA1_R 51 HDMI_DATA0_R# 51 HDMI_DATA0_R 51 HDMI_CLK_R# 51 HDMI_CLK_R 51 HDMI 0511-CHECK P46 P42 3 DDPC_AUXN DDPC_AUXP DDPC_HPD AP47 AP49 AT38 DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 PORT PORT-B DDPD_CTRLCLK DDPD_CTRLDATA CRT 4 3 2 1 2 DY 50 CRT_DDC_CLK 50 CRT_DDC_DATA SCD1U50V3KX-GP 2 EC1702 SCD1U50V3KX-GP DY SCD1U50V3KX-GP 1 EC1701 CRT_BLUE CRT_GREEN CRT_RED EC1703 50 CRT_BLUE 50 CRT_GREEN 50 CRT_RED SDVO_TVCLKINN SDVO_TVCLKINP SDVO_CTRLCLK SDVO_CTRLDATA Digital Display Interface RN1702 3 49 L_BKLT_EN 49 LVDS_VDD_EN 2 1 L_DDC_DATA(K47): This signal is on the LVDS interface. This signal needs to be left NC if eDP is used for the local flat panel display 4 2 1 4 OF 10 PCH1D SRN2K2J-1-GP 3 4 4 3 LVDS 1 2 M43 M36 DDPD_AUXN DDPD_AUXP DDPD_HPD AT45 AT43 BH41 DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 DDI PCH Pin Names HDMI/DVI Mapping DDPB_[0]P DDPB_[0]N DDPB_[1]P DDPB_[1]N DDPB_[2]P DDPB_[2]N DDPB_[3]P DDPB_[3]N DDPB_AUXP DDPB_AUXN DDPB_HPD SDVO_CTRLCLK SDVO_CTRLDATA TMDSB_DATA2 TMDSB_DATA2# TMDSB_DATA1 TMDSB_DATA1# TMDSB_DATA0 TMDSB_DATA0# TMDSB_CLK TMDSB_CLK# NA NA HDMIB_HPD HDMIB_CTRLCLK HDMIB_CTRLDATA 2 2 PANTHER-GP-NF Notes: 1K 0.5% 0402 The recommended value for this external resistor is 1.0 k ±0.5%. The CRT DAC outputs may be measured when the display is completely white. If CRT DAC signal voltage value is between 665 mV to 770 mV, then the video level is within VESA specification and the reference resistor value is optimal for the motherboard design. <Core Design> 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title A B C D PCH : LVDS/CRT/DDI Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet E 17 of 103 A B C 4 RN1801 INT_PIRQH# INT_PIRQB# INT_PIRQF# INT_PIRQA# 3D3V_S0 1 2 3 4 5 10 9 8 7 6 3D3V_S0 INT_PIRQD# LCD_DET# INT_PIRQC# INT_PIRQG# SRN8K2J-2-GP-U 2 1 PCI_GNT3# R1801 DY 4K7R2J-2-GP A16 swap override Strap/Top-Block Swap Override jumper PCI_GNT#3 Low = A16 swap override/Top-Block Swap Override enabled High = Default For PPT USB3.0 feature BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30 62 USB3_RX1_N DGPU_HOLD_RST# 1 R1819 2 10KR2J-3-GP 62 USB3_RX3_N 62 USB3_RX1_P 3 62 USB3_RX3_P 62 USB3_TX1_N 62 USB3_TX3_N 3D3V_S0 62 USB3_TX1_P 2 62 USB3_TX3_P 3D3V_S0 R1814 10KR2F-2-GP B21 M20 AY16 BG46 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 USB3RN1 USB3RN2 USB3RN3 USB3RN4 USB3RP1 USB3RP2 USB3RP3 USB3RP4 USB3TN1 USB3TN2 USB3TN3 USB3TN4 USB3TP1 USB3TP2 USB3TP3 USB3TP4 RSVD28 RSVD29 R1815 10KR2F-2-GP 83 DGPU_HOLD_RST# TP1805 1 1 93 DGPU_PWR_EN# DGPU_HOLD_RST# DGPU_SELECT# DGPU_PWR_EN# BBS_BIT1 DGPU_PWM_SELECT# PCI_GNT3# 49 LCD_DET# 27,56 SATA_ODD_DA# 3D3V_S0 2 INT_PIRQC# INT_PIRQD# 1 R1813 0R2J-2-GP R1817 8K2R2J-3-GP INT_PIRQF# INT_PIRQG# INT_PIRQH# 2 TP1813 1 DY PCI_PME# C46 C44 E40 D47 E42 F46 G42 G40 C42 D44 K10 C6 PIRQA# PIRQB# PIRQC# PIRQD# REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54 GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55 PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5 65,71 CLK_PCI_LPC 20 CLK_PCI_FB 27 CLK_PCI_KBC DGPU_PWM_SELECT# 2 R1804 R1805 R1806 1 1 1 2 22R2J-2-GP 2 22R2J-2-GP 2 22R2J-2-GP CLK_PCI_LPC_R H49 CLK_PCI_FB_R H43 CLK_PCI_KBC_R J48 K42 H40 AT10 BC8 AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 AV5 AV10 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P USBRBIAS# USBRBIAS PLTRST# CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 1 DY 1 DY 2 R1802 1KR2J-1-GP 2 R1803 1KR2J-1-GP BBS_BIT1 BBS_BIT0 OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14 21 BOOT BIOS Strap GNT1#/GPIO51 NV_ALE NV_RCOMP SATA1GP/GPIO19 0 0 BOOT BIOS Location LPC 0 1 Reserved 1 0 Reserved 1 1 SPI(Default) TP1814 TP1812 1 1 AT8 Mini Card2 (WWAN) AY5 BA2 AT12 BF3 C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32 USB_PN0 USB_PP0 Gx8 USB Table C33 USB_RBIAS TP1819 TP1820 1 1 USB_PN1 USB_PP1 USB_PN2 USB_PP2 USB_PN3 USB_PP3 USB_PN4 USB_PP4 USB_PN5 USB_PP5 Pair 62 62 82 82 62 62 63 63 82 82 USB_PN8 66 USB_PP8 66 USB_PN9 82 USB_PP9 82 USB_PN10 64 USB_PP10 64 USB_PN11 65 USB_PP11 65 USB_PN12 49 USB_PP12 49 0 USB3.0 ext port 1 USB2.0 ext port 4 USB3.0 ext port 2 BLUETOOTH CARD READER USB2.0 ext port 3 Fingerprint Mini Card1 (WLAN) CAMERA 1 2 R1811 22D6R2F-L1-GP Device 3 X 1 USB3.0, ext port1 2 USB2.0, ext port4 3 USB3.0, ext port2 4 Bluetooth 5 CARD READER 6 X 7 X 8 3G 9 USB2.0, ext. port 3 10 Finger Print 11 Mini Card1 (WLAN) 12 CAMERA 13 X USB 2.0 Overcurrent Pin Default Usage B33 PME# 1 PCI_PLTRST# K40 K38 H38 G38 USB 1 2 DY PCI 2 1 R1818 INT_PIRQA# 8K2R2J-3-GP INT_PIRQB# 4 AY7 AV7 AU3 BG4 Utilize Port 9 for USB debug DY DGPU_PWR_EN# E 5 OF 10 PCH1E SSID = PCH D A14 K20 B17 C16 L16 A16 D14 C14 USB_OC#0_1 USB_OC#2_3 USB_OC#4_5 USB_OC#6_7 USB_OC#8_9 USB_OC#10_11 USB_OC#12_13 PCH_GPIO14 USB_OC#0_1 USB_OC#2_3 USB_OC#4_5 62 61 62 USB_OC#8_9 82 Pin Default Port Mapping OC0# OC1# OC2# OC3# Port Port Port Port 0, 2, 4, 6, Port Port Port Port 1 3 5 7 Pin Default Port Mapping OC4# OC5# OC6# OC7# Port 8, Port 9 Port 10, Port 11 Port 12, Port 13 Not Used 2 PANTHER-GP-NF OC[3:0]# for Device 29 (Ports 0-7) OC[7:4]# for Device 26 (Ports 8-13) Reserve Buffer or not? PLT_RST# 2 USB_OC#2_3 PCH_GPIO14 USB_OC#6_7 USB_OC#0_1 PCI_PLTRST# 3D3V_S5 1 2 3 4 5 10 9 8 7 6 USB_OC#12_13 USB_OC#8_9 USB_OC#10_11 USB_OC#4_5 3D3V_S5 SRN8K2J-2-GP-U 1 R1816 100KR2J-1-GP 1 5,27,31,36,65,66,71,80,82,83,97 RN1802 1 R1807 0R2J-2-GP C1801 SC220P50V2KX-3GP DY 2 2 DY 1 1 <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title A B C D PCH : PCI/USB/NVRAM/RSVD Size A2 Document Number Date: Friday, January 06, 2012 Sheet E Rev SD LA480 18 of 103 A B C D E SSID = PCH For platforms not supporting Deep S4/S5 1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board) 2.DPWROK and RSMRST# will rise at the same time (connected on board) 3.SLP_SUS# and SUSACK# are left as ‘no connect’ 4.SUSWARN# used as SUSPWRDNACK/GPIO30 4 3 OF 10 PCH1C DMI_RXN[3:0] 4 DMI_RXP[3:0] 4 1 R1926 DY 1 R1904 2 SYS_PWROK 10KR2J-3-GP 2 PWROK 100KR2J-1-GP DMI_TXN[3:0] 4 DMI_TXP[3:0] DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 BC24 BE20 BG18 BG20 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 BE24 BC20 BJ18 BJ20 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 AW24 AW20 BB18 AV18 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 AY24 AY20 AY18 AU18 DMI0RXN DMI1RXN DMI2RXN DMI3RXN FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 FDI 4 DMI Signal Routing Guideline: DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils. FDI_INT 1D05V_VTT R1905 1 DY 3D3V_S0 Platforms supporting Deep S4/S5, but not wishing 10KR2J-3-GP to participate in the handshake during wake and Deep S4/S5 entry may tie SUSACK# to SUSWARN#. 2 BJ24 SYS_RESET# R1901 2 49D9R2F-GP 1 2 R1902 750R2F-GP 1 DMI_COMP_R BG25 RBIAS_CPY BH21 DMI_ZCOMP FDI_FSYNC0 DMI_IRCOMP FDI_FSYNC1 DMI2RBIAS FDI_LSYNC0 FDI_LSYNC1 3 SUS_ACK#: For non-DWS platforms, this signal can be left unconnected. Due to the internal pull-up on this signal it will be pulled high in order for the boot sequence to proceed. R1916 5 XDP_DBRESET# SYS_PWROK: the system is ready to start the exit from reset (de-asserts PLT_RST# to the processor) 1 R1915 1 DY 2 1 R1914 2 0R0402-PAD 1 2 0R2J-2-GP R1930 1 2 0R2J-2-GP R1931 SYS_RESET# K3 P12 Active Sleep Well (ASW) Power OK 45 MPWROK 0R0402-PAD 1 DY R1923 27 S0_PWR_GOOD S0_PWR_GOOD after PM_SLP_S3# delay 200 ms C12 0R2J-2-GP 36 SYS_PWROK PWROK: it indicates to PCH that its CORE well power is stable. SUSACK# 2 DSWVRMEN 2 0R2J-2-GP PWROK MEPWROK L22 L10 SUSACK# SYS_RESET# SYS_PWROK PWROK APWROK Non-SBA B13 37 PM_DRAM_PWRGD SBA 27,97 PM_PWRBTN# PM_RSMRST# C21 SUS_PWR_ACK K16 PM_PWRBTN# E20 H20 27 AC_PRESENT BATLOW# E10 PM_RI# A10 DRAMPWROK RSMRST# System Power Management SUS_PWR_ACK 4 DPWROK WAKE# CLKRUN#/GPIO32 SUS_STAT#/GPIO61 SUSCLK/GPIO62 SLP_S5#/GPIO63 SLP_S4# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PWRBTN# SLP_A# ACPRESENT/GPIO31 SLP_SUS# BATLOW#/GPIO72 PMSYNCH RI# SLP_LAN#/GPIO29 BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9 FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 FDI_TXN[7:0] 4 FDI_TXP[7:0] 4 DSWODVREN - On Die DSW VR Enable FDI_INT AV12 FDI_FSYNC0 4 BC10 FDI_FSYNC1 4 AV14 FDI_LSYNC0 4 BB10 FDI_LSYNC1 4 DSWODVREN E22 PCH_DPWROK DSWODVREN 1 R1992 1 DY R1911 10KR2J-3-GP PCIE_WAKE# N14 SUS_CLK D10 PM_SLP_S5# PCH_SUSCLK_KBC PM_SLP_S3# 27,36,37,47 G10 PM_SLP_A# 27,45 H_PM_SYNC PM_SLP_LAN# 1 R1919 1 3 2 8K2R2J-3-GP This signal is used to control power planes to the IntelR ME sub-system. This signal will be asserted in M-off state. If M3 is not supported then SLP_A# will have the same timings as SLP_S3#. TP1904 AP14 K14 2 330KR2J-L1-GP 27 PM_SLP_S4# 27,46,97 1 DY TP1902 F4 PM_SLP_SUS# 1 27 H4 G16 R1918 2 330KR2J-L1-GP TP1901 1 R1913 2 0R0402-PAD 1 1 31,65,66 PM_CLKRUN# 1 R1917 3D3V_S0 PM_CLKRUN# 2 PM_RSMRST# 0R0402-PAD 2 RTC_AUX_S5 N3 PM_SUS_STAT# Disabled 4 B9 G8 Enabled (DEFAULT) LOW RTC_AUX_S5 AW16 A18 HIGH For platforms supporting DEEP S4/S5 state, a low on this signal indicates that PCH is in Deep Sleep state and that EC/platform logic does not need to keep the Suspend Rails ON. If high means EC must keep SUS rails ON. If DEEP S4/S5 is not supported, then this pin can be left unconnected. 5 TP1905 2 2 3D3V_S5 PANTHER-GP-NF RN1901 8 7 6 5 SUSPWRDNACK : No longer requires a 10-K pull-up to VccSUS (3.3 V). BATLOW# PM_RI# SUS_PWR_ACK PCIE_WAKE# 1 2 3 4 SRN10KJ-6-GP 2 R1922 2 1 10KR2J-3-GP AC_PRESENT 1 10KR2J-3-GP PM_PWRBTN# PCH_WAKE# CRB : 1K CHKLIST: 10K 3D3V_AUX_S5 2 R1909 R1908 2 10KR2J-3-GP 1 2 R1925 1 100KR2J-1-GP R1924 10KR2J-3-GP 1 DY Q1901 3V_5V_POK_# 4 3 5 2 6 1 PM_RSMRST# PM_RSMRST# 1 R1921 1KR2J-1-GP 2 RSMRST#_KBC 27 3V_5V_POK 41 2N7002KDW-GP 84.2N702.A3F 2nd = 84.DM601.03F 1 1 <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title A B C D PCH : DMI/FDI/PM Size A2 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet E 19 of 103 A B C D 3D3V_S5 SSID = PCH 3D3V_S5 0511-CHECK 1 4 E R2004 10KR2J-3-GP BG40 BJ40 AY40 BB40 3 BE38 BC38 AW38 AY38 Y40 Y39 PCIE_CLK_RQ0# WLAN CLK 65 CLK_PCIE_WLAN# 65 CLK_PCIE_WLAN RN2012 1 2 J2 SRN0J-6-GP CLK_PCH_SRC1_N 4 CLK_PCH_SRC1_P 3 AB49 AB47 PCIE_CLK_WLAN_REQ# 65 PCIE_CLK_WLAN_REQ# M1 AA48 AA47 PCIE_CLK_CR_REQ# 31 CLK_PCIE_LAN# 31 CLK_PCIE_LAN LAN CLK RN2016 1 2 SRN0J-6-GP CLK_PCH_SRC3_N 4 CLK_PCH_SRC3_P 3 PCIE_CLK_LAN_REQ# 31 PCIE_CLK_LAN_REQ# V10 PCIE_CLK_LAN_REQ# A8 SML1CLK/GPIO58 SML1DATA/GPIO75 PERN8 PERP8 PETN8 PETP8 CL_CLK1 CL_DATA1 CL_RST1# 1 SML0_DATA 3D3V_S0 RN2007 C13 PCH_GPIO74 E14 SML1_CLK M16 SML1_DATA L14 SML1_CLK 27 Q2001 SMB_DATA SML1_DATA 27 M7 CL_CLK 1 TP2001 T11 CL_DATA 1 TP2002 P10 CL_RST# 1 TP2003 PCIE_CLK_RQ6# T13 V38 V37 1 M10 PEG_CLKREQ#_R R2003 2 0R0402-PAD AB37 AB38 CLKOUT_PEG_A_N CLKOUT_PEG_A_P CLK_PCIE_NEW_REQ# K12 TP2010 TP2011 3D3V_S0 PCIE_CLK_XDP_N PCIE_CLK_XDP_P 1 1 AK14 AK13 PEG_CLKREQ# CLKOUT_PCIE2N CLKOUT_PCIE2P CLKIN_DMI_N CLKIN_DMI_P PCIECLKRQ2#/GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P CLKIN_GND1_N CLKIN_GND1_P CLK_EXP_N CLK_EXP_P AM12 AM13 CLK_DP_N CLK_DP_P 4 3 PCIE_CLK_CR_REQ# PCIE_CLK_WLAN_REQ# BF18 BE18 CLK_BUF_EXP_N CLK_BUF_EXP_P BJ30 BG30 CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P G24 E24 CLK_BUF_DOT96_N CLK_BUF_DOT96_P AK7 AK5 CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P 2 1 SRN10KJ-5-GP 1 3 R2006 1M1R2J-GP 2 3 C2008 SC15P50V2JN-2-GP C2007 SC15P50V2JN-2-GP 2 1 XTAL-25MHZ-155-GP 5 5 3D3V_S0 3D3V_S0 3 4 CLKOUT_PCIE4N CLKOUT_PCIE4P CLKIN_SATA_N CLKIN_SATA_P PCIECLKRQ4#/GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P REFCLK14IN PCIECLKRQ5#/GPIO44 R2012 10KR2J-3-GP R2013 10KR2J-3-GP Non-SBA UMA CLKIN_PCILOOPBACK CLKOUT_PEG_B_N CLKOUT_PEG_B_P UMA_DISCRETE# UMA: 1 1 DIS :0 1 SG(PX) : 0 0 Optimus(Muxless) : 1 0 SBA_Support# DGPU_PRSNT# CLKIN_DOT_96N CLKIN_DOT_96P K45 CLK_BUF_REF14 H45 CLK_PCI_FB V47 V49 XTAL25_IN XTAL25_OUT PL 10K FOR Integrated CLOCK GEN mode. RN2020 SRN10KJ-5-GP CLK_BUF_DOT96_N 1 4 CLK_BUF_DOT96_P 2 3 CLK_PCI_FB XTAL25_IN XTAL25_OUT 18 +VCCDIFFCLKN PEG_B_CLKRQ#/GPIO56 Y47 XCLK_RCOMP CLKOUT_PCIE6N CLKOUT_PCIE6P XCLK_RCOMP 1 2 R2007 90D9R2F-1-GP RN2021 CLK_BUF_CKSSCD_N 1 CLK_BUF_CKSSCD_P 2 SRN10KJ-5-GP 4 3 RN2019 CLK_BUF_EXP_N 1 CLK_BUF_EXP_P 2 SRN10KJ-5-GP 4 3 R2010 10KR2J-3-GP R2011 10KR2J-3-GP SBA OPS CLK_BUF_REF14 1 R2008 10KR2J-3-GP 22 3D3V_S5 RN2001 1 2 3 4 1 2 3 4 2 8 7 6 5 CLK_PCIE_NEW_REQ# PCIE_CLK_LAN_REQ# PCIE_CLK_RQ5# PCIE_CLK_RQ4# 2 SRN10KJ-6-GP RN2002 8 EC_SWI# 7 PCIE_CLK_RQ0# 6 5 PEG_B_CLKRQ# SRN10KJ-6-GP PCIECLKRQ6#/GPIO45 CLKOUTFLEX0/GPIO64 CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67 K43 JTAG_TCK F47 CLK_PCH_48M_L H47 CLK_27M_VGA_R K49 DGPU_PRSNT# 1 TP2004 DY 1 R2016 1 PANTHER-GP-NF 2 22R2J-2-GP CLK_PCH_48M 82 TP2005 EC2003 DY – Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3 – Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2 if more than 2 PCI clocks + PCI loopback are routed. PCIECLKRQ1# and PCIECLKRQ2# Support S0 power only 14,15,65,66 82.30020.D41 2nd = 82.30020.G71 3rd = 82.30020.G61 TP2006 TP2007 1 1 RN2018 1 2 4 XTAL25_OUT SRN10KJ-5-GP PCIECLKRQ3#/GPIO25 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P PCH_SMBCLK 2 83 CLK_PCIE_VGA# 83 CLK_PCIE_VGA 83 AV22 AU22 CLKOUT_DMI_N CLKOUT_DMI_P CLKOUT_DP_N CLKOUT_DP_P PCIECLKRQ7#/GPIO46 PCH_SMBDATA 14,15,65,66 1 serial 0ohm RN? PCIECLKRQ1#/GPIO18 CLKOUT_PCIE7N CLKOUT_PCIE7P 3 1 E6 V40 V42 2 4 2 PEG_B_CLKRQ# 1 5 2N7002KDW-GP SCD1U16V2KX-3GP DY 6 84.2N702.A3F 2nd = 84.DM601.03F SMB_CLK 0511-CHECK FLEX CLOCKS AB42 AB40 3 4 SRN2K2J-1-GP X2001 PEG_A_CLKRQ#/GPIO47 CLKOUT_PCIE1N CLKOUT_PCIE1P SML0_CLK 2 R2009 1KR2J-1-GP XTAL25_IN CLKOUT_PCIE0N CLKOUT_PCIE0P PCIECLKRQ0#/GPIO73 4 RN2006 3 SRN10KJ-5-GP 1 12,37 1 EC2002 2 SCD1U16V2KX-3GP 1 DY 2 SCD1U16V2KX-3GP EC2001 L12 V45 V46 PCIE_CLK_WLAN_REQ# PCIE_CLK_RQ5# 2 SML1ALERT#/PCHHOT#/GPIO74 PERN7 PERP7 PETN7 PETP7 C8 G12 DRAMRST_CNTRL_PCH RN2008 Y37 Y36 Y43 Y45 PCIE_CLK_RQ4# PERN6 PERP6 PETN6 PETP6 DRAMRST_CNTRL_PCH 2 1 LAN PERN5 PERP5 PETN5 PETP5 A12 2 BJ38 BG38 AU36 AV36 DRAMRST_CNTRL_PCH 1 BG37 BH37 AY36 BB36 3 RN2005 4 SRN2K2J-1-GP 1 2 1 PCIE_TXN4_C PCIE_TXP4_C SML0CLK SML0DATA 2 1 PCIE_CLK_RQ6# PCH_GPIO74 2 2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP Card Reader SML1_CLK SML1_DATA 4 SMB_DATA 80 WLAN SML0ALERT#/GPIO60 1 RN2004 2 SRN2K2J-1-GP 1 1 1 DY 4 3 2 C2005 C2006 PERN4 PERP4 PETN4 PETP4 SMB_DATA SML0_DATA SML0_CLK 1 PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4 C9 R2005 10KR2J-3-GP SMB_CLK 80 2 31 31 31 31 BF36 BE36 AY34 BB34 PERN3 PERP3 PETN3 PETP3 SMBDATA SMB_CLK 1 RN2003 2 SRN2K2J-1-GP 2 BG36 BJ36 AV34 AU34 PERN2 PERP2 PETN2 PETP2 EC_SWI# H14 2 BE34 BF34 BB32 AY32 E12 4 3 1 PCIE_TXN2_C PCIE_TXP2_C SMBUS 2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP SMBCLK Link 1 1 WWAN Controller C2016 C2015 PEG_CLKREQ#_R SMBALERT#/GPIO11 PCI-E* PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 PERN1 PERP1 PETN1 PETP1 CLOCKS 65 65 65 65 BG34 BJ34 AV32 AU32 2 2 OF 10 PCH1B If PCIE port 1 is disabled, it will cause all PCIE port disabled SMB_CLK SMB_DATA 1 1 <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title A B C D PCH : PCIE/SMBUS/CLK Size A2 Document Number Date: Friday, January 06, 2012 Sheet E Rev SD LA480 20 of 103 A B SSID = PCH 1 2 E INTVRMEN- Integrated SUS 1.05V VRM Enable High - Enable internal VRs Low - Enable external VRs 4 3 RTC_X2 2 10MR2J-L-GP 1 1 D RTC_AUX_S5 SRN20KJ-GP-U RTC_X1 RN2104 C2103 SC1U6D3V2KX-GP 2 R2101 C X2101 0511-CHECK 1 1 33R2J-2-GP2 DY 1 R2122 HDA_SYNC 1 R2123 HDA_SDOUT 2 29 HDA_SPKR HDA_RST# 29 33R2J-2-GP2 33R2J-2-GP2 29 HDA_CODEC_RST# 29 HDA_CODEC_BITCLK 1 R2126 1 R2129 1 R2102 HDA_SDOUT 2 DY 1KR2J-1-GP HDA_SDOUT N34 L34 K34 E34 HDA_SDIN0 G34 HDA_RST# HDA_BITCLK KBC_RTCRST# 27 Notes: ME_UNLOCK (HDA_SDO) connect to EC. Make sure EC drive this pin "low" all the time. Flash Descriptor Security Overide +3VS_+1.5VS_HDA_IO C17 T10 83.00016.K11 2nd = 83.00016.M11 3rd = 83.00016.N11 DY 3 33R2J-2-GP2 29 HDA_CODEC_SDOUT HDA_SYNC D2130 BAS16-6-GP 1 29 HDA_CODEC_SYNC R2130 0R2J-2-GP 1 2 HDA_BITCLK 0511-CHECK ADD BLOCK FET IN CODEC PAGE. K22 27 ME_UNLOCK Low = Default High = Enable R2107 C34 A34 HDA_SDOUT 2 1KR2J-1-GP 1 TP2105 1 PCH_GPIO33 A36 C36 N32 NO REBOOT STRAP 3D3V_S0 3 No Reboot Strap 1 R2106 HDA_SPKR 2 DY 1KR2J-1-GP Low = Default HDA_SPKR High = No Reboot PCH_JTAG_TCK_BUF J3 TP2102 1 PCH_JTAG_TMS H7 TP2103 1 PCH_JTAG_TDI K5 TP2104 1 PCH_JTAG_TDO H1 RTCRST# D36 LPC_FRAME#_L FWH4/LFRAME# SRTCRST# INTRUDER# INTVRMEN SPKR SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP HDA_RST# HDA_SDIN0 HDA_SDIN2 HDA_SDIN3 HDA_SDO HDA_DOCK_EN#/GPIO33 JTAG_TDO SATAICOMPO 60 SPI_CS1#_R 27,60 SPI_SI_R +3VS_+1.5VS_HDA_IO R2103 1 Y14 SBA 1 R2110 PCH_SPI_SI 33R2J-2-GP V4 2 T1 U3 27,60 SPI_SO_R 2 1KR2J-1-GP T3 SPI_CLK 68 INT_SERIRQ APS_LED 27 SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0 66 66 66 66 m-SATA AM10 AM8 AP11 AP10 SATA_RXN1 SATA_RXP1 SATA_TXN1 SATA_TXP1 56 56 56 56 HDD1 mSATA, CRV USE PORT2 SATA_RXN4 SATA_RXP4 SATA_TXN4 SATA_TXP4 56 56 56 56 ODD E-SATA 1D05V_VTT SATA_COMP R2112 1 2 37D4R2F-GP SATA3RBIAS 3 1D05V_VTT AB12 AB13 SATA3_COMP R2113 1 2 49D9R2F-GP AH1 RBIAS_SATA3 R2114 1 2 750R2F-GP SPI_CS0# OD SPI_CS1# SPI 27,60 SPI_CS0#_R PCH_SPI_CLK 33R2J-2-GP 2 PCH_SPI_CS0# 0R2J-2-GP 2 PCH_SPI_CS1# 0R2J-2-GP 2 4 DY AM3 AM1 AP7 AP5 Y10 SATAICOMPI SATA3COMPI 1 R2108 1 R2109 1 R2117 APS_LED Y11 SATA3RCOMPO 27,60 SPI_CLK_R R2128 10KR2J-3-GP 27,65,71 Y3 Y1 AB3 AB1 SATA5RXN SATA5RXP SATA5TXN SATA5TXP JTAG_TDI LPC_FRAME# Y7 Y5 AD3 AD1 SATA4RXN SATA4RXP SATA4TXN SATA4TXP HDA_DOCK_RST#/GPIO13 JTAG_TMS 2 22R2F-1-GP AB8 AB10 AF3 AF1 SATA3RXN SATA3RXP SATA3TXN SATA3TXP JTAG_TCK 1 3D3V_S0 27,65,71 AD7 AD5 AH5 AH4 SATA2RXN SATA2RXP SATA2TXN SATA2TXP HDA_SDIN1 R2121 V5 SERIRQ HDA_SYNC 2 2 2 2 E36 K36 LDRQ0# LDRQ1#/GPIO23 HDA_BCLK 1 1 1 1 2 RTCX2 LPC_AD[0..3] 22R2F-1-GP LPC_AD0 22R2F-1-GP LPC_AD1 22R2F-1-GP LPC_AD2 22R2F-1-GP LPC_AD3 R2111 R2118 R2119 R2120 1 G22 LPC D20 SRTC_RST# LPC_AD0_TPM LPC_AD1_TPM LPC_AD2_TPM LPC_AD3_TPM C38 A38 B37 C37 FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 SATA 6G 1 2ND = 84.2N702.031 2 DY 0R2J-2-GP RTC_RST# SM_INTRUDER# 1M1R2J-GP PCH_INTVRMEN 2 330KR2F-L-GP 2 R2104 1 R2105 RTC_AUX_S5 2 84.2N702.J31 1 R2131 C20 RTC C2104 2N7002K-2-GP SC1U6D3V2KX-GP G2101 GAP-OPEN RTC_X2 RTCX1 IHDA D S A20 SATA G RTCRST_ON RTC_X1 JTAG 2 2 27 2 82.30001.C21 Q2102 1 XTAL-32D768KHZ-15-GP 1 1 C2102 SC15P50V2JN-2-GP SC15P50V2JN-2-GP 4 Check with SW 1 OF 10 PCH1A 2 C2101 SPI_MOSI SPI_MISO SATA_LED# P3 SATALED# P1 SATA1GP/GPIO19 SATA_LED# 68 BBS_BIT0 18 SATA_DET#0 V14 SATA0GP/GPIO21 HDA_SYNC PANTHER-GP-NF This signal has a weak internal pull down. On Die PLL VR is supplied by 1.5V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R2310 CHECK CHECK 4.7K PD PCH_JTAG_TCK_BUF 1 R2134 2 51R2J-2-GP PLL ODVR VOLTAGE HDA_SYNC Low = 1.8V (Default) High = 1.5V CHECK 3D3V_S0 RN2103 SATA_LED# SATA_DET#0 This signal has a weak internal pull-down. On Die PLL VR is supplied by 1.5 V from VccVRM when sampled high, 1.8 V from VccVRM when sampled low. PCH_SPI_CLK HDA_CODEC_BITCLK HDA_CODEC_SDOUT SPI_CS0#_R EC2102 C2102 EC2103 C2103 EC2101 C2101 22 1 2 3 4 S_GPIO 8 7 6 5 SRN10KJ-6-GP 2E 1 DY SC4D7P50V2CN-1GP 1 1 DY SC4D7P50V2CN-1GP DY SC4D7P50V2CN-1GP 1 2 SCD1U16V2KX-3GP HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete. EC2104 DY 2E 2 2E 2 INT_SERIRQ 1 R2125 2 8K2R2J-3-GP 10K? 84.2N702.J31 2ND = 84.2N702.031 Q2101 HDA_CODEC_SYNC_L S 1 HDA_CODEC_SYNC 2 1 R2124 33R2J-2-GP HDA_SYNC D 2 R2127 1MR2F-GP G 2N7002K-2-GP Vth? 5V_S0 1 1 <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title A B C D PCH : HDA/JTAG/SATA Size A2 Document Number Date: Friday, January 06, 2012 Sheet E Rev SD LA480 21 of 103 A B R2202 HR:200K (64.20035.6DL) CRV:10K (63.10334.1DL) 1 H36 1 R2215 DY U2 PCH_GPIO27 PLL_ODVR_EN 3D3V_S0 3D3V_S5 2 2 10KR2J-3-GP 1 10KR2J-3-GP 1 2 2 Gsensor_ID 2 10KR2J-3-GP 8 7 6 5 PSW_CLR# MFG_MODE PCH_GPIO27 P8 PSW_CLR# K1 FP_DET# K4 DMI_OVRVLTG V8 FDI_OVRVLTG M5 MFG_MODE N2 GFX_CRB_DET M3 PCH_GPIO48 R2226 10KR2J-3-GP DY 1 3 R2221 10KR2J-3-GP 2 E16 G2201 GAP-OPEN 1 R2220 FP_DET# 1 DY R2224 PCH_TEMP_ALERT# 1 R2222 RN2201 EC_SMI# 1 EC_SCI# 2 DGPU_HPD_INTR# 3 PCH_GPIO22 4 E8 K D2201 CH751H-40-1-GP PCH_GPIO48 T5 SRN10KJ-6-GP R2225 1 2 10KR2J-3-GP 1 2 R2228 10KR2J-3-GP V13 PCH_TEMP_ALERT# V3 USB3_PWR_ON D6 1 PCH_NCTF_1 TP2212 1 PCH_NCTF_7 A4 A44 1 R2229 2 10KR2J-3-GP 3D3V_S5 FP_DET# A45 1 A46 RN2204 4 3 SRN10KJ-5-GP 1 2 A5 R2223 10KR2J-3-GP A6 2 RTC_DET# USB3_PWR_ON PCH_GPIO15 PLL_ODVR_EN 1 R2201 2 1 R2234 2 B3 1KR2J-1-GP B47 BD1 DY 10KR2J-3-GP BD49 TP2207 1 PCH_NCTF_2 BE1 TP2208 1 PCH_NCTF_3 BE49 TP2209 1 PCH_NCTF_4 2 1KR2J-1-GP H_SNB_IVB# 5 A40 VRAM_SIZE2 DMI & FDI Termination Voltage Set to Vss when LOW Set to Vcc when HIGH NV_CLE GPIO15 A20GATE PECI SATA4GP/GPIO16 TACH0/GPIO17 SCLOCK/GPIO22 GPIO24 GPIO27 GPIO28 PROCPWRGD THRMTRIP# INIT3_3V# DF_TVS TS_VSS1 STP_PCI#/GPIO34 TS_VSS2 GPIO35 TS_VSS3 SATA2GP/GPIO36 TS_VSS4 P4 H_A20GATE AU16 NC_1 1 R2203 H_RCIN# AY11 27 2 DY 0R2J-2-GP PCH_THERMTRIP_R T14 INIT3_3V# AY1 NV_CLE 1 H_PECI 5,27 27 H_CPUPWRGD AY10 1 R2204 390R2J-1-GP TP2201 AK11 AH10 AK10 TS_VSS 1 R2219 0R0402-PAD 2 2 H_THERMTRIP# 5,36 TS Signal Disable Guideline: TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4 should not float on the motherboard. They should be tied to GND directly. P37 3 SDATAOUT0/GPIO39 3D3V_S0 SDATAOUT1/GPIO48 VSS_NCTF_15#BG2 SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16#BG48 GPIO57 VSS_NCTF_17#BH3 VSS_NCTF_1#A4 VSS_NCTF_2#A44 VSS_NCTF_3#A45 VSS_NCTF_19#BJ4 VSS_NCTF_20#BJ44 VSS_NCTF_21#BJ45 VSS_NCTF_4#A46 VSS_NCTF_22#BJ46 VSS_NCTF_5#A5 VSS_NCTF_23#BJ5 VSS_NCTF_6#A6 VSS_NCTF_24#BJ6 VSS_NCTF_7#B3 VSS_NCTF_8#B47 VSS_NCTF_9#BD1 VSS_NCTF_10#BD49 VSS_NCTF_11#BE1 VSS_NCTF_12#BE49 PROCPWRGD (PCH) --> UNCOREPOWRGOOD (CPU) Indicates that VccSA, VDDQ, VccA (1.8V) and VccIO power supplies are stable. This signal will be asserted only after PWROK assertion. 5,97 AH8 SATA3GP/GPIO37 SLOAD/GPIO38 H_PECI_R P5 BG2 VSS_NCTF_25#C2 FDI TERMINATION VOLTAGE OVERRIDE BG48 R2207 DY 10KR2J-3-GP BH3 BH47 BJ4 FDI_OVRVLTG VSS_NCTF_26#C48 VSS_NCTF_27#D1 VSS_NCTF_28#D49 VSS_NCTF_29#E1 VSS_NCTF_30#E49 VSS_NCTF_13#BF1 VSS_NCTF_31#F1 VSS_NCTF_14#BF49 VSS_NCTF_32#F49 GPIO37 (FDI_OVRVLTG) LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT) R2208 10KR2J-3-GP BJ44 BJ45 PCH_NCTF_9 1 TP2214 BJ46 PCH_NCTF_10 1 TP2215 BJ5 PCH_NCTF_5 TP2210 1 BJ6 3D3V_S0 C2 DMI TERMINATION VOLTAGE OVERRIDE C48 R2209 DY 10KR2J-3-GP D1 D49 PCH_NCTF_8 1 TP2213 E1 PCH_NCTF_6 1 TP2211 DMI_OVRVLTG GPIO36 (DMI_OVRVLTG) LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT) R2210 10KR2J-3-GP E49 F1 2 BF1 INTERNAL GFX 1 R1809 LAN_PHY_PWR_CTRL/GPIO12 VSS_NCTF_18#BH47 TP2206 NV_CLE 20 GPIO8 RCIN# D40 Gsensor_ID A TACH7/GPIO71 SBA_Support# C41 VRAM_SIZE1 1 10K 10K G2 TACH3/GPIO7 SATA_ODD_PWRGT 56 B41 1 DY PCH_GPIO15 2PCH_GPIO16 0R2J-2-GP PCH_GPIO22 DY R2221 C4 DGPU_PWROK_C 2 0R2J-2-GP KIXNOK R2226 C10 TACH6/GPIO70 2 92,93 DGPU_PWROK E38 ICC_EN# RTC_DET# SATA_ODD_PRSNT# 1 R2216 EC_SCI# TACH5/GPIO69 TACH2/GPIO6 1 60 56 SATA_ODD_PRSNT# ST EC_SCI# TACH4/GPIO68 TACH1/GPIO1 2 27 SRN10KJ-5-GP GPIO27 has a weak[20K] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down. BMBUSY#/GPIO0 2 A42 DGPU_HPD_INTR# 2 H_A20GATE H_RCIN# 4 R1808 2K2R2J-2-GP C40 1 R2218 T7 CPU/MISC S_GPIO GPIO0 2 100R2J-2-GP EC_SMI# GPIO 21 G-Sensor 6 OF 10 PCH1F 1 RN2203 3 4 E 1D8V_S0 3D3V_S0 2 1 D Note: For PCH debug with XDP, need to NO STUFF R2218 SATA_ODD_PRSNT# 2 10KR2J-3-GP 1 R2202 NCTF 4 NCTF TEST PIN: A4,A44,A45,A46,A5,A6,B3,B47, BD1,BD49,BE1,BE49,BF1,BF49, BG2,BG48,BH3,BH47,BJ4,BJ44, BJ45,BJ46,BJ5,BJ6,C2,C48,D1, D49,E1,E49,F1,F49 3D3V_S0 C BF49 F49 PANTHER-GP-NF EXTERNAL GFX 2 2 R2205 DY 10K 3D3V_S0 2 1 1 DY 3D3V_S0 R2230 10KR2J-3-GP R2232 10KR2J-3-GP DY DY 2 100K 1 R2206 R2205 DY 10KR2J-3-GP Integrated Clock Chip Enable DY ICC_EN# VRAM_SIZE1 VRAM_SIZE2 1 R2211 1KR2J-1-GP HIGH (R2211 DY)- DISABLED [DEFAULT] 2 ICC_EN# LOW (R2211)- ENABLED PLL ON DIE VR ENABLE GFX_CRB_DET NOTE:This signal has a weak internal pull-up 20K ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT DISABLED -- LOW (R2212 STUFFED) 1 2 Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable. 2 R2206 100KR2J-1-GP PLL_ODVR_EN 1 DY R2212 1KR2J-1-GP R2211 BOM CTRL HR:1K CRV:DY GPIO8 has a weak[20K] internal pull up. Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable. 2 1 1 <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title PCH : GPIO/NTCF/MISC A B C D Size A2 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet E 22 of 103 5 4 3 2 1 SSID = PCH 3D3V_DAC_S0 6A VCCIO21 AP24 VCCIO22 VCCIO24 VCCVRM3 AT16 VCCDMI1 AT20 VCCCLKDMI R2306 AN34 VCCIO26 VCCDFTERM1 AG16 BH29 VCC3_3_3 VCCDFTERM2 AG17 VCCDFTERM3 AJ16 VCCDFTERM4 AJ17 1 VCCFDIPLL BG6 AP17 1D05V_VTT +1.05VS_VCC_DMI 0.042A (Totally current of VCCDMI) AU20 VCCAFDIPLL VCCIO27 VCCDMI2 PANTHER-GP-NF 1 1 2 3 1 2 1D05V_VTT R2307 DY 1 2 0R0402-PAD C2321 SC1U6D3V2KX-GP C2325 (1uFx1) (10uFx1) 1D8V_S0 1 0.19A IN GND EN DY OUT 5 NC#4 4 DY C2324 AME8818BEEV330Z-GP 74.08818.B3F B Reserve 0ohm for power measurement? C2322 SCD1U10V2KX-5GP (0.1uFx1) 74.09091.J3F GMT OBS REASON:G9091 series is going to EOL and no room for further cost reduction. Pls help to use AME AME8818 , TI TLV702 and GMT G9090 for replacement. 3D3V_S5 VCCSPI V1 0.02A VCCSPI_3D3V 2 TP2302 VCCVRM2 FDI AP16 +VCCAFDI_VRM 3D3V_DAC_S0 (1uF x1) 2 2 0.159A(Totally current of VCCVRM) C2310 SCD1U10V2KX-5GP 3.3V CRT LDO 5V_S0 U2302 1 B 1D05V_VTT 2 0R0402-PAD 1 C2320 SC1U6D3V2KX-GP 1 VCCIO25 DFT / SPI 1 (0.1uF x1) 1D5V_S0 R2308 1 2 0R0402-PAD 0.02A 2 3D3V_S0 AN33 1 1 2 +VCCAFDI_VRM +1.05VS_VCC_DMI AB36 C Reserve 0ohm for power measurement? C2319 SCD1U10V2KX-5GP +1.05VS_VCC_DMI_CCI 0.266A (Totally VCC3_3 current) 2 2 2 1 1 1 V34 1 VCC3_3_7 1 2 HVCMOS 1 1 2 3D3V_S0 C2329 (0.1uFx1) 0.266A 0.042A DMI VCCIO23 AT24 V33 0.16A VCCIO AP26 C2330 SC1U6D3V2KX-GP VCCIO20 AP23 VCC3_3_6 C2317 SCD01U50V2KX-1GP 1 AP21 C2316 SCD01U50V2KX-1GP 1D8V_S0 1 2 R2305 0R0603-PAD 2 VCCIO19 AP37 +1.8VS_VCCTX_LVDS 2 VCCIO18 AN27 VCCTX_LVDS4 (0.01uF x2) (22uF x1) 0.06A 1 AN26 AP36 2 VCCIO17 AM38 VCCTX_LVDS3 SC1U10V2KX-1GP AN21 AM37 VCCTX_LVDS2 3D3V_S0 1 2 R2304 0R0603-PAD 2 VCCIO16 VCCTX_LVDS1 2 AN17 2 CRT +3VS_VCCA_LVDS LVDS 2 VCC CORE 1 1 2 1 1 2 1 2 1 2 SC1U6D3V2KX-GP 1 VCCIO15 C2309 SCD1U10V2KX-5GP SCD1U10V2KX-5GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP 2 C2308 AK37 D 3D3V_S0 SC1U6D3V2KX-GP C2307 VSSALVDS 2 0R2J-2-GP SC1U6D3V2KX-GP C2306 AK36 C2333 1 R2302 C2326 SC10U6D3V3MX-GP C2328 VCCAPLLEXP AN16 (10uF x1) 2.925A(Total current of VCCIO) C C2327 BJ22 VCCALVDS C2315 SC10U6D3V3MX-GP VCCAPLLEXP 1 C2314 SC1U6D3V2KX-GP TP2301 1D05V_VTT VCCIO28 VSSADAC U47 0.001A 1D05V_VTT AN19 VCCADAC SCD1U10V2KX-5GP VCCCORE1 VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE5 VCCCORE6 VCCCORE7 VCCCORE8 VCCCORE9 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE13 VCCCORE14 VCCCORE15 VCCCORE16 VCCCORE17 L2301 1 2 BLM18PG181SN1D-GP 1 0.001A U48 +VCCA_DAC_1_2 C2313 SCD01U50V2KX-1GP 2 C2303 SCD1U10V2KX-5GP 1 C2304 SC1U6D3V2KX-GP 2 C2302 SC1U6D3V2KX-GP 2 C2312 SC1U6D3V2KX-GP SC1U6D3V2KX-GP 1 C2311 AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31 2 0R2J-2-GP 2 7 OF 10 +VCCA_DAC_3V POWER 1.3A(Total current of VCCCORE) 1 PCH1G 1D05V_VTT 2 D DY 1 R2301 R2309 1 2 0R0402-PAD 74.09198.G7F OBS C2323 SC1U6D3V2KX-GP (1uFx1) VCCVRM(Internal PLL and VRMs): A.1.5V for Mobile B.1.8 V for Desktop Refer to NPCE795 shared SPI flash architecture A <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title PCH : POWER1 5 4 3 2 Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 23 of 103 C VCCACLK 1 +VCCPDSW T16 VCCDSW3_3 DCPSUSBYP V12 DCPSUSBYP TP2404 1 +VCCAPLL_CPY_PCH BH23 AL29 TP2402 +VCCSUS1 AL24 1 C2410 SC1U6D3V2KX-GP 2 1 VCCSUS3_3_9 V23 VCCSUS3_3_10 V24 VCCSUS3_3_6 P24 VCCIO34 T26 V5REF_SUS M26 +5VA_PCH_VCC5REFSUS DCPSUS4 AN23 +VCCA_USBSUS VCCSUS3_3_1 AN24 C2424 SCD1U10V2KX-5GP 3D3V_S5 VCCASW5 AA29 VCCASW6 AA31 VCCASW7 AC26 VCCASW8 AC27 VCCASW9 AC31 VCCASW11 AD29 VCCASW12 AD31 VCCASW13 W21 VCCASW14 W23 VCCASW15 W24 VCCASW16 W26 VCCASW17 W29 VCCASW18 W31 VCCASW19 W33 VCCASW20 V5REF P34 VCCSUS3_3_2 N20 VCCSUS3_3_3 N22 VCCSUS3_3_4 P20 VCCSUS3_3_5 P22 3D3V_S5 0.001A +5VS_PCH_VCC5REF VCC3_3_1 AA16 VCC3_3_8 W16 VCC3_3_4 T34 VCC3_3_2 AJ2 1 (1uFx1) C2430 SCD1U10V2KX-5GP VCCIO5 AF13 VCCIO12 AH13 VCCIO13 AH14 VCCVRM4 VCCIO6 AF14 C2429 SCD1U10V2KX-5GP (0.1uFx1) 1D05V_VTT 1 +VCCDIFFCLK AF17 AF33 AF34 AG34 VCCIO7 VCCDIFFCLKN1 VCCDIFFCLKN2 VCCDIFFCLKN3 1 (1uFx1) 0.055A 1 1 2 R2406 0R0603-PAD C2414 SC1U6D3V2KX-GP +V1.05S_SSCVCC 2 (1uFx1) 2 0.095A AG33 VCCSSC V16 DCPSST T17 V19 DCPSUS1 DCPSUS2 2 1 +VCCSST C2415 SCD1U10V2KX-5GP (0.1uFx1) (1uFx1) TP2406 1 DCPSUS R2413 0.001A 1 1 V_PROC_IO_R C2418 SCD1U10V2KX-5GP BJ8 V_PROC_IO C2419 SCD1U10V2KX-5GP A22 VCCRTC A B 1 1 2 C2421 SCD1U10V2KX-5GP VCCIO2 AC16 VCCIO3 AC17 VCCIO4 AD17 1 VCCASW22 T21 VCCASW23 V21 VCCASW21 T19 VCCSUSHDA P32 TP2407 +VCCAFDI_VRM 1D05V_VTT (1uFx1) C2435 SCD1U10V2KX-5GP +3VS_+1.5VS_HDA_IO 3D3V_S5 1 2 R2409 0R0603-PAD (0.1uFx1) 0.01A <Core Design> 1 C2433 SCD1U10V2KX-5GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title C2422 SCD1U10V2KX-5GP PCH : POWER2 2 1 2 C2416 SC1U6D3V2KX-GP AF11 2 PANTHER-GP-NF 6uA (0.1uFx2) (1uFx1) +V1.05S_VCCAPLL_SATA3 VCCVRM1 +3VS_+1.5VS_HDA_IO HDA 2 RTC_AUX_S5 SC1U6D3V2KX-GP 1 C2417 2 2 1 0R0402-PAD (0.1uFx2) (4.7uFx1_0603) 2 AK1 1D05V_M 1D05V_VTT 1 C2413 SC1U6D3V2KX-GP 2 1 +V1.05S_SSCVCC 2 R2405 2 1 0R0402-PAD VCCAPLLSATA 1 (1uFx1) 1D05V_VTT CPU C2412 SC1U6D3V2KX-GP (1uFx1) 2 +VCCDIFFCLKN VCCADPLLB C2432 SC1U6D3V2KX-GP 1 1D05V_VTT +VCCDIFFCLK BF47 RTC R2404 2 1 0R0402-PAD VCCADPLLA +1.05VS_VCCA_B_DPL MISC 1D05V_VTT SATA (0.1uFx1) BD47 (0.1uFx2) C2431 SCD1U10V2KX-5GP 3D3V_S0 DCPRTC +1.05VS_VCCA_A_DPL 3 2 2 Y49 +VCCAFDI_VRM (1uFx1) 3D3V_S0 2 C2411 SCD1U10V2KX-5GP N16 C2427 SC1U10V2KX-1GP 2 2 +VCCRTCEXT 0.16A (Totally current of VCCVRM R2407 1 10R2J-2-GP 3D3V_S5 C2428 SC1U6D3V2KX-GP 5V_S0 D2402 CH751H-40PT-GP 83.R0304.A8F 2nd = 83.R2004.B8F 1 (1uFx1) (220uFx1) VCCASW10 3D3V_S0 1 2 AA27 0.001A TP2403 1 VCCASW4 (0.1uFx1) 2 VCCASW3 AA26 C2426 SCD1U10V2KX-5GP 2 C2425 SCD1U10V2KX-5GP 1D05V_VTT 1 AA24 R2408 1 10R2J-2-GP (0.1uFx1) 2 0.08A +1.05VS_VCCA_B_DPL 2 T24 4 2 1 2 1 2 C2409 SC1U6D3V2KX-GP (1uFx1) (220uFx1) C2444 SC10U6D3V3MX-GP VCCSUS3_3_8 5V_S5 D2401 CH751H-40PT-GP 83.R0304.A8F 2nd = 83.R2004.B8F (0.1uFx1) 1 0.08A +1.05VS_VCCA_A_DPL DY T23 2 VCCASW2 PCI/GPIO/LPC L2402 68.10050.10Y 2nd = 68.1001E.10N DCPSUS3 VCCASW1 AC29 L2403 1 2 IND-10UH-218-GP VCCSUS3_3_7 3D3V_S5 3D3V_S5 0.097A (Totally current of VCCSUS3_3) Clock and Miscellaneous 2 2 2 1 1 1 1 2 1D05V_VTT DY T29 VCCIO14 AA21 C2408 SC1U6D3V2KX-GP 1 C2407 SC1U6D3V2KX-GP 2 C2406 SC1U6D3V2KX-GP 1 C2437 SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC10U6D3V3MX-GP 2 C2436 3 C2443 SC10U6D3V3MX-GP T27 VCCIO33 VCCAPLLDMI2 AA19 1.01A (Total current of VCCASW) 68.10050.10Y 2nd = 68.1001E.10N P28 VCCIO32 (1uFx1) C2423 SCD1U10V2KX-5GP 1 1 1D05V_M 1 2 IND-10UH-218-GP VCCIO31 VCC3_3_5 USB (10uFx1) 1D05V_VTT C2403 P26 1 C2402 SC1U10V2KX-1GP T38 2 C2401 SC10U6D3V5KX-1GP +V3.3S_VCC_CLKF33 1 1 +V3.3S_VCC_CLKF33 2 68.10050.10Y 2nd = 68.1001E.10N VCCIO30 1 (10uFx1) (1uFx1) 1 2 IND-10UH-218-GP VCCIO29 N26 2 1 2 R2403 0R0603-PAD TP2405 L2401 4 1D05V_VTT 10 OF 10 2 POWER 1 AD49 2 0.002A (0.1uFx1) 3D3V_S0 VCCACLK 1 3D3V_S5 1 1 PCH1J TP2401 E 1 SSID = PCH D 2 B 2 A C D Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet E 24 of 103 A B C D SSID = PCH PCH1I 4 8 OF 10 PCH1H H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3 3 2 AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28 PANTHER-GP-NF 1 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 9 OF 10 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS328 VSS329 VSS330 VSS331 VSS333 VSS334 VSS335 VSS337 VSS338 VSS340 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352 H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28 B C 4 3 2 <Core Design> 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title PANTHER-GP-NF A E D PCH : VSS Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet E 25 of 103 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Reserved Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 26 of 1 103 A 5 4 3 2 3D3V_AUX_KBC 1 3D3V_AUX_S5 1 2 R2725 0R0805-PAD SSID = KBC 3D3V_AUX_KBC 3D3V_S0_KBC 1 2 1 CAP_LED 65 AOAC_EN 38 AD_OFF 82 USB_CHG_EN 36,97 S5_ENABLE 82 ADP_LED 39 BAT_IN# 49,70 LID_CLOSE# 19 RSMRST#_KBC 19,46,97 PM_SLP_S4# -MSATA_DET 3G_EN TP2703 65 PCIE_WLAN_WAKE# 65 WIFI_RF_EN 63,65 BLUETOOTH_EN 19 S0_PWR_GOOD 21,60 SPI_CS1#_R 21,60 SPI_CS0#_R 21,60 SPI_CLK_R 21,60 SPI_SO_R 21,60 SPI_SI_R 21 KBC_RTCRST# SBA 33R2J-2-GP 2 33R2J-2-GP 33R2J-2-GP 0R2J-2-GP 33R2J-2-GP 2 2 2 2 1 Non-SBA 1 1 1 1 1 79 6 109 14 15 80 17 20 21 26 123 82 83 84 NC_KBC_GPIO51 R2744 R2736 R2719 R2737 R2722 EC_SPI_CS#_C EC_SPI_CLK_C EC_SPI_DI_C EC_SPI_DO_C 90 92 86 87 91 75 1 1 1 2 2 2 GPIO2 GPIO24 GPIO30/F_WP# GPIO34/CIRRXL GPIO36 GPIO41/F_WP# GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO51/N2TCK GPIO67N2TMS GPIO75 GPIO76 GPIO77 GPIO52/PSDAT3/RDY# GPIO50/PSCLK3/TDO GPIO27/PSDAT2 GPIO26/PSCLK2 GPIO35/PSDAT1 GPIO37/PSCLK1 7 2 3 1 128 127 126 125 8 9 29 124 121 122 1 2 LPC_AD[0..3] 1 2 R2735 R2730 1 R2740 1 R2741 1 R2742 1 0R0402-PAD 1 2 33R2J-2-GP 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 1 2 R2729 ECSCI#_KBC SATA_ODD_DA#_R LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 33R2J-2-GP R2738 27 25 11 10 71 72 GPIO17/SCL1/N2TCK GPIO22/SDA1/N2TMS GPIO73/SCL2 GPIO74/SDA2 GPIO23/SCL3 GPIO31/SDA3 GPIO47/SCL4 GPIO53/SDA4 21,65,71 32 118 62 65 22 81 66 16 68 DC_BATFULL 29 KBC_BEEP 68 PWRLED 40 STOP_CHG# 38 AD_DETECT 68 NUM_LED 68 KBC_NOVO_BTN# 68 CHARGE_LED INT_SERIRQ 21 PM_CLKRUN# 19 PANEL_BLEN 49 ME_UNLOCK E51_RxD E51_TxD 23 113 111 19 PCH_SUSCLK_KBC 29 AMP_MUTE# 77 30 SATA_ODD_DA# 18,56 H_A20GATE 22 H_RCIN# 22 0R2J-2-GP 31 63 64 56 HDD_DET# 82 USB_AO_SEL0 19,36,37,47 PM_SLP_S3# PLT_RST# 5,18,31,36,65,66,71,80,82,83,97 CLK_PCI_KBC 18 LPC_FRAME# 21,65,71 21 65 65 BLON_OUT 49 PM_SLP_A# 19,45 GSENSE_ON# 79 CHG_USB_OC# 82 TPDATA 69 TPCLK 69 41 <------ TP F_CS0# F_SCK F_SDI_F_SDIO1 F_SDI_F_SDIO0 GPIO81/F_WP# 70 69 67 68 119 120 24 28 KCOL[0..15] 2 PLT_RST#_EC LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R 2 114 GPIO94/DA0 GPIO95/DA1 GPIO96/DA2 GPIO97/DA3 DY 2 OF 2 U2701B ECRST# 5,22 H_PECI 1D05V_VTT R2721 R2720 1 1 2 43R2J-GP 2 0R2J-2-GP ECRST# 85 PECI EC_VTT 13 12 BAT_SCL 39,40 BAT_SDA 39,40 SML1_CLK 20 SML1_DATA 20 LAN_PWR_ON 31 <------ BATTERY / CHARGER <------PCH / eDP GPIO56/TA1 GPIO14/TB1 GPIO1/TB2 GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PW M GPIO32/D_PW M GPIO45/E_PWM GPIO66/G_PW M GPIO33/H_PWM GPIO40/F_PWM GPIO46/CIRRXM/TRIST# GPIO87/CIRRXM/SIN_CR GP/I/O83/SOUT_CR/TRIST# KBSOUT0/GPOB0/JENK# KBSOUT1/GPIOB1/TCK KBSOUT2/GPIOB2/TMS KBSOUT3/GPIOB3/TDI KBSOUT4/GPOB4/JEN0# KBSOUT5/GPIOB5/TDO KBSOUT6/GPIOB6/RDY# KBSOUT7/GPIOB7 KBSOUT8/GPIOC0 KBSOUT9/GPOC1/SDP_VIS# KBSOUT10_P80_CLK/GPIOC2 KBSOUT11_P80_DAT/GPIOC3 KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62 KBSOUT15/GPIO61/XOR_OUT GPIO60/KBSOUT16 GPIO57/KBSOUT17 GPIO0/EXTCLK GPIO55/CLKOUT/IOX_DIN_DIO KBSIN0/GPIOA0/N2TCK KBSIN1/GPIOA1/N2TMS KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7 VCC_POR# PECI VTT 53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33 KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17 54 55 56 57 58 59 60 61 KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7 1 1 69 TP2707 TP2708 KROW[0..7] 3D3V_AUX_KBC 69 1 1 68 R2776 100KR2J-1-GP TP2704 101 105 106 107 LRESET#/GPIOF7 LCLK/GPIOF5 LFRAME#/GPIOF6 LAD3/GPIOF4 LAD2/GPIOF3 LAD1/GPIOF2 LAD0/GPIOF1 SERIRQ/GPIOF0 GPIO11/CLKRUN# GPIO65/SMI# ECSCI#/GPIO54 GPIO10/LPCPD# GPIO85/GA20 KBRST#/GPIO86 GPIO90/AD0 GPIO91/AD1 GPIO92/AD2 GPIO93/AD3 GPIO5/AD4 GPIO4/AD5 GPIO3/AD6 GPIO7/AD7 R2717 10KR2J-3-GP DY PM_SLP_A# C2716 NPCE885GA0DX-GP SCD1U16V2KX-3GP 3D3V_AUX_KBC R2720 and C2716 Need very close to EC RTCRST_ON 21 PROCHOT_EC CHG_ON# 40 2 3D3V_AUX_S5 CAMERA_EN -MSATA_DET VREF AC_IN# 1 VGA_CURRENT CPU_CURRENT GSENSE_X GSENSE_Y 49 66 1 2 0R0402-PAD R2706 100KR2J-1-GP HDD_DET# DY C2711 SC220P50V2KX-3GP 1 R2714 10KR2J-3-GP 40 2 42 42 79 79 97 98 99 100 108 96 95 94 PCB_VER_AD ADT_TYPE MODEL_ID_AD RTC_AUX_S5 0R0402-PAD 1 OF 2 1 DY 2 R2712 AC_IN_KBC R2775 100KR2J-1-GP 2 1 3D3V_AUX_S5 3D3V_AUX_KBC 0R0402-PAD 2 D Code change to Low Active on 8/19 RC2701 SC33P50V2JN-3GP 1 104 AD_IA C2714 SCD1U10V2KX-5GP DY 2 R2709 0R0805-PAD VBKUP 102 4 VDD AVCC VCC1 VCC2 VCC3 VCC4 VCC5 2 1 2 40 2 1 C2713 2 DY SCD1U10V2KX-5GP R2701 100KR2F-L1-GP DY 1 R2739 ADT_TYPE ADT_TYPE 1 38 C2703 SC2D2U10V3KX-1GP R2743 U2701A 19 46 76 88 115 1 C2710 2 1 1 1 1 1 2 2 2 2 1 C2709 SCD1U10V2KX-5GP 2 C2708 SC1U6D3V2KX-GP 1 C2707 SCD1U10V2KX-5GP 2 C2706 SCD1U10V2KX-5GP 2 C2702 SCD1U10V2KX-5GP SCD1U10V2KX-5GP 1 C2705 DY SCD1U10V2KX-5GP R2707 10KR2F-2-GP C2704 SCD1U10V2KX-5GP 65W: 1.7V 90W: 3.3V C2701 SC2D2U10V3KX-1GP DY SC33P50V2JN-3GP 1 RC2702 3D3V_AUX_KBC 2 D 3D3V_S0 VBAT 2 R2702 0R0603-PAD VSBY 1 PSL_OUT_GPIO71# PSL_IN2_GPI6# PSL_IN1_GPI70# 74 93 73 NC_EC_ENABLE 1 KBC_PWRBTN_EC# AC_IN_KBC 44 KBC_VCORF TP2705 KBC_NOVO_BTN# EC_SPI_DI_C 117 112 110 19,97 PM_PWRBTN# 19 AC_PRESENT USB_PWR_EN_R GPIO20/TA2/IOX_DIN_DIO GP/I/O84/IOX_SCLK/XORTR# GPO82/IOX_LDSH/TEST# VCORF 2 2 AGND C2712 SC1U10V2KX-1GP 103 GND1 GND2 GND3 GND4 GND5 GND6 18 45 78 89 116 5 NPCE885GA0DX-GP C R2773 100KR2J-1-GP 1 61,62,82 1 C 2 EC_AGND R2711 1 0R0402-PAD Reset IC: Prevent EC_GPIO47 High Active BIOS data loss solution 3D3V_AUX_S5 2 H_PROCHOT# 5,42 28,36,86 PURE_HW_SHUTDOWN# 2 2N7002K-2-GP 84.2N702.031 2ND = 84.2N702.J31 2 1 ECRST#_B R2723 10KR2J-3-GP DY B Q2701 MMBT3906-4-GP R2705 10KR2J-3-GP 3D3V_AUX_S5 U2702 DY 2 1 E H_PROCHOT#_EC R2733 0R0402-PAD S 2 D 1 G R2732 100KR2J-1-GP C 1 1 2 R2770 1KR2J-1-GP C2715 SC1U6D3V2KX-GP Q2702 PROCHOT_EC AD_OFF 1 ECRST# 1 PURE_HW_SHUTDOWN# 2 84.03906.F11 2nd = 84.C3906.A11 GND VCC 3 RESET# G690L293T73UF-GP 74.00690.I7B 1 R2716 2 DY 0R2J-2-GP D2704 22 EC_SCI# B 1 3D3V_AUX_S5 B ECSCI#_KBC 1 3 2 R2704 10KR2J-3-GP WHY 2 2 1 KBC_PWRBTN# 1 68 KBC_PWRBTN_EC# R2703 470R2J-2-GP C2717 SC220P50V2KX-3GP DY 2 R2774 100KR2J-1-GP 2 G2701 GAP-OPEN 1 1 83.00016.K11 2ND = 83.00016.F11 2 BAS16-6-GP EC GPIO standard PH/PL 3D3V_AUX_KBC RN2701 BAT_SCL BAT_SDA 3D3V_AUX_KBC 3 4 1 SML1_CLK R2727 47KR2F-GP RN48 5 2 6 1 RN2703 BAT_IN# LID_CLOSE# BOM CTRL 3D3V_S0 4 3 1 2 SRN100KJ-6-GP MODEL_ID_AD 1 R2728 100KR2F-L1-GP SMBC_THERM 28,86 SMBD_THERM 28,86 RN2705 S5_ENABLE ECRST# 4 3 1 2 3D3V_AUX_KBC SRN10KJ-5-GP 2N7002KDW-GP 3D3V_S0 PCIE_WLAN_WAKE# 10KR2J-3-GP 84.2N702.A3F 2nd = 84.DM601.03F 2 R2724 64K9R2F-1-GP 1 R2715 BOM CTRL 2 DY PCB_VER_AD 1 3D3V_S0 Pull Down Pull High UMA 100.0K 33.0K 2.481V OPTIMUS 100.0K 47.0K 2.245V R2726 100KR2F-L1-GP Voltage E51_RxD A Pull-Low Resistor Pull-High Resistor Voltage (3D3V_AUX_S5) SA 100.0K 10.0K 3.0V SB 100.0K 20.0K 2.75V SC 100.0K 33.0K 2.48V -1 100.0K 47.0K 2.24V Reserved 100.0K 64.9K 2.0V Reserved 100.0K 76.8K 1.87V Reserved 100.0K 100.0K 1.65V 2 MODEL_ID_AD (Pin100) PCB Version A/D (Pin98) 1 2 1 SRN10KJ-5-GP 3 2 SML1_DATA 3 4 2 SMBC_THERM SMBD_THERM Q2703 4 2 1 SRN4K7J-8-GP 1 DY2 R2708 10KR2J-3-GP BLUETOOTH_EN 2 DY 1 R2710 10KR2J-3-GP A 71.00885.A0G IC EMB CTRL NPCE885PA0DX LQFP 128P <Core Design> Wistron Corporation 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title <Title> Size A1 Document Number LA480 Date: Friday, January 06, 2012 Rev SD Sheet 27 of 103 5 4 SSID = Thermal 3 2 Thermal sensor 1 20110718_Carrey: For Vendor suggestion, add 390pF Cap. as closed to pin B/C and E of Q2803 T8 2200p close to smsc2103 chip Close to SO-DIMM on top side. H_THERMDA 1 1 C 2 CPU TEMP: H_THERMDA and H_THERMDC routing 10mil trace width and spacing. Locate Capacity near Thermal diode. 1 E REMOTE2- 2 C2804 SC390P50V2KX-GP DY C2805 SC2200P50V2KX-2GP 2 1 D H_THERMDC CPU backside or inside the socket 2200p close to smsc2103 chip C C2802 SC2200P50V2KX-2GP MMBT3904W T1G-GP Q2802 MMBT3904W T1G-GP B C2808 SC390P50V2KX-GP B Q2803 C2803 SC390P50V2KX-GP 2 B E 1 D 2 C E 3 1 2 SA 0905 change to 390p Q2804 MMBT3904W T1G-GP 4 WIRE PWM Fan Control circuit REMOTE2+ 5V_S0 1 3D3V_S0 THERM_SCI# FAN_PW M SHDN --> 2N3904 ON External diode 2 1 16 15 THERM_SYS_SHDN# THERM_SCI# 7 6 9 8 27,86 SMBC_THERM 27,86 SMBD_THERM 1 1 3 4 3D3V_S0 DY SRN10KJ-5-GP 3 H_THERMDA H_THERMDC REMOTE2+ REMOTE2- VDD DP1 DN1 DP2/DN3 ND2/DP3 SYS_SHDN# ALERT# GPIO1 GPIO2 4 5 TACH PWM 10 11 TRIP_SET SHDN_SEL 14 13 2103_4 2103_5 20100707_EMI TP2802 TP2803 1 1 D2801 FAN_TACH_1 TRIP_SET R2806 1 SHDN_SEL 2 649R2F-GP T8 = 98 TRIP_SET: 649 ohm => 87 dgree C SMCLK SMDATA GND GND 2 EC2802 2 2 2103_VDD 2 SCD1U10V2KX-4GP 2 RN2801 2 1 U2801 1 C2806 4 3 2 1 2 C FAN_PW M_C 1 EC2801 DY 5 SC1KP50V2KX-1GP R2805 68R2-GP 1 R2804 0R0402-PAD SC1KP50V2KX-1GP 1 2 DY 5V_S0_FAN FAN_TACH 1 SHDN_SEL 2 R2812 10KR2J-3-GP FAN1 6 1 R2801 6K8R2J-GP R2802 0R0805-PAD AFTP2807 2 3D3V_S0 2 2 1 C 10KR2J-3-GP 3D3V_S0 20110718_Carrey: For Vendor suggestion, add 10k pull high to 3D3V_S0 R2803 SC4D7U6D3V3KX-GP 1 C2801 1 between CPU, VGA and DIMM on bottom side ACES-CON4-GP-U1 20.F0714.004 CHECK PIN DEFINE FAN_TACH FAN_PW M CH551H-30PT-GP AFTP2801 AFTP2805 AFTP2806 83.R5003.C8F 1st = 83.R5003.J8F 2ND = 83.R5003.I8F 1 1 1 FAN_PW M_C FAN_TACH 5V_S0_FAN 12 17 B B EMC2103-2-AP-GP 3D3V_S0 3D3V_S0 2 3 3D3V_AUX_S5 1 pin6, ALERT# OD pin7, SYS_SHDN# OD S 2 1 Q2801 THERM_SYS_SHDN# R2809 10KR2J-3-GP 1 R2808 100KR2J-1-GP DY 2 D2802 BAT54PT-GP 83.00054.T81 2ND = 83.BAT54.D81 3rd = 83.BAT54.S81 <Core Design> A D 1 27,36,86 PURE_HW _SHUTDOW N# G IMVP_PW RGD_T 1 2 R2811 0R0402-PAD C2807 SCD1U10V2KX-5GP 2N7002K-2-GP 1 R2810 10KR2J-3-GP 2 DY 2 DY A Wistron Corporation IMVP_PW RGD 36,42 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 84.2N702.031 2ND = 84.2N702.J31 Title THERMAL SENSOR SMSC EMC2103 5 4 3 2 Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 28 of 103 5 4 3 2 1 AUD_5V 5V_S0 5V_S0 1A R2902 2 DY 1 R2904 1 Close to Codec <<Attention>> Surges of PVDD >7V duration 0.1ms when class D amplifier is working may damage the amplifier, 10uF tantalum capacitors are required at PVDD1 and PVDD2 to suppress the surge. 1 2 0R5J-5-GP 2 0R0805-PAD C2905 SC10U6D3V3MX-GP 2 1 1 SC10U6D3V3MX-GP SCD1U10V2KX-5GP 2 C2904 SCD1U10V2KX-5GP SC10U6D3V3MX-GP D AUD_PVDD C2927 2 C2903 1 C2902 2 2 0R0805-PAD 1 1 R2903 AU_GND Tied at one point only under the ALC269 or near the ALC269 AU_GND D Close to Codec AUD_PORTA_R AUD_PORTA_L 1 R2905 1 R2906 2 75R2J-1-GP 2 75R2J-1-GP AUD_MIC1_VREFO_L AUD_HPOUT_R 82 AUD_HPOUT_L 82 EXT MIC AUD_MIC2_VREFO AUD_CPVEE 2 1 C2906 SC2D2U10V3KX-1GP 58 1 2 AU_GND AUD_LDO_CAP C2907 SC10U6D3V3MX-GP AUD_MIC1_VREFO_L 1 58 AUD_DMIC_CLK 3D3V_S0 27 1 0R0402-PAD 1 AUD_MIC1_COMBO_R 1KR2J-1-GP AUD_MIC1_COMBO_R R2924 1 2 2 C2901 SC4D7U6D3V3KX-GP AU_GND 82 2 1 2 R2925 22KR2J-GP Capacitor Working Voltage ALC269 having AVDD=5V ±5%, so the capacitors must have a 10V working voltage. A working voltage of 16V is recommended to provide margin for variations in the application C2928 SC10U6D3V3MX-GP 2 1 1 26 25 27 VREF AVSS1 AVDD1 AU_GND 23 22 AUD_PORTB_R C2914 1 2 SC4D7U6D3V3KX-GP 21 AUD_PORTB_L C2915 1 2 SC4D7U6D3V3KX-GP AUD_MIC1_COMBO EXT MIC 20 C AUD_JDREF 19 1 R2909 20KR2F-L-GP 18 17 AUD_PORTF_R C2916 16 AUD_PORTF_L C2917 2 AU_GND 2 SC4D7U6D3V3KX-GP 1 AUD_MIC2 B Series-MIC 2 SC4D7U6D3V3KX-GP 1 58 ANALOG MIC B Series-MIC 15 14 AUD_SENSE_A 13 1 2 R2912 39K2R2F-L-GP HPOUT_JD 82 PCBEEP RESET# DIGITAL 12 AUD_PC_BEEP 2 C2918 SCD1U10V2KX-5GP KBC_BEEP_R 2 1 1 11 R2915 4K7R2J-2-GP 2 C2921 SC100P50V2JN-3GP 1 R2914 10KR2J-3-GP HDA_SPKR 21 1 R2916 10KR2J-3-GP KBC_BEEP 27 2 2 10 SYNC ANALOG 1 29 30 31 28 LDO-CAP MIC2-VREFO MIC1-VREFO-R 32 AUD_SDATA_OUT 2 R2918 C2913 SCD1U10V2KX-5GP AU_GND AUD_DMIC_CLK_R 0R0402-PAD HDA_CODEC_RST# HDA_CODEC_SYNC AUD_SDATAIN 2 R2917 1 22R2J-2-GP HDA_SDIN0 HDA_CODEC_BITCLK_R 2 R2919 1 0R0402-PAD HDA_CODEC_BITCLK AMP_MUTE# 21 HDA_CODEC_SDOUT 1 2 R2901 2K2R2J-2-GP 24 HDA_CODEC_RST# 58 AUD_DMIC_DATA B DVDD-IO DVDD1 GND LINE2-L SENSE_A 9 SPDIFO 1 1 MIC1-VREFO-L EAPD/COMBO_JACK C2920 2 2 33 LINE2-R SCD1U10V2KX-5GP SC1U6D3V2KX-GP 1 C2919 CPVEE PVDD2 AUD_DVDD 2 0R0805-PAD HP-OUT-L MIC2-L 3D3V_S0 1 R2913 34 SPK-R+ AUD_DVDD 48 MIC2-R SDATA-IN 47 49 SENSE_B ALC269Q-VC-GR-GP SPK-R- 8 AUD_COMBOJACK PVSS2 DVSS2 46 JDREF BIT-CLK AUD_PVDD PVSS1 7 45 MONO-OUT 6 44 58 AUD_SPK_R+ SPK-L- SDATA-OUT 43 58 AUD_SPK_R- MIC1-L PD# 42 MIC1-R GPIO1/DMIC-CLK 41 LINE1-L SPK-L+ 5 58 AUD_SPK_L- 2 AU_GND LINE1-R PVDD1 4 40 3 C 39 2 1 22KR2J-GP close to pin27 AVDD2 GPIO0/DMIC-DATA AUD_PVDD 58 AUD_SPK_L+ R2923 AUD_COMBOJACK AU_GND AVSS2 2 38 1 R2922 AUD_MIC1_COMBO C2910 SCD1U10V2KX-5GP 2 1 2 AUD_CBN AU_GND 37 C2909 SC1U6D3V2KX-GP AUD_5V HP-OUT-R CBP U2901 35 36 AU_GND CBN 1 Close to Codec 2 C2912 SCD1U10V2KX-5GP 2 C2911 SC4D7U6D3V3KX-GP 1 AUD_5V AUD_CBP 2 1 close to pin27 C2908 SC2D2U10V3KX-1GP 1 AU_GND 21 21 B 21 21 1 HDA_CODEC_BITCLK_R C2926 SC6D8P50V2DN-GPDY 2 1 1 HDA_CODEC_RST# C2925 SC6D8P50V2DN-GPDY 2 2 AUD_SDATA_OUT C2924 SC22P50V2JN-4GP DY 2 1 AUD_DMIC_DATA C2923 SC33P50V2JN-3GP DY 2 DY C2922 SC33P50V2JN-3GP DY 2 R2920 4K7R2J-2-GP 1 AUD_DMIC_CLK 1 AMP_MUTE# 2 R2921 10KR2J-3-GP For EMI issue. 20100705_AUD A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title AUDIO CODEC 5 4 3 2 Size A2 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 29 of 103 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A4 Document Number Reserved Date: Friday, January 06, 2012 5 4 3 Rev SD LA480 2 Sheet 30 of 1 103 A 5 4 3 2 1 main pwr if have no ASF 3D3V_S0 1 25MHz XTAL LAN_XTAL0 R3136 1KR2J-1-GP 1 3 2 LAN_XTAL1 C3103 C3148 RTL_ISOLATE# 1 15pF VB480 12pF 78.15034.1FL 2 X3101 4 R3119 15KR2F-GP 12pF VB580 12pF 78.12034.1FL 2 XTAL-25MHZ-155-GP 82.30020.D41 D D 2 1M1R2J-GP C3103 SC12P50V2JN-3GP BOM CTRL 1D05V_LAN_S5 1 1D05V_LAN_S5 3D3V_LAN_S5 3D3V_LAN_S5 C3148 SC12P50V2JN-3GP High:Link up Low:Link down LAN_XTAL0 LAN_XTAL1 1 R3130 3D3V_LAN_S5 2 2 1 2nd = 82.30020.G71 3rd = 82.30020.G61 LAN_RSET 2 2K49R2F-GP 1 R3123 LAN_ACT_LED# GPO SPEED_100# 59 48 47 46 45 44 43 42 41 40 39 38 37 71.08111.N03, IC PCIE CTRL RTL8111F-CGT QFN 48P 59 59 MDI0+ MDI0- 59 59 MDI1+ MDI1- 59 59 MDI2+ MDI2- 59 59 MDI3+ MDI3- 1 2 3 4 5 6 7 8 9 10 11 12 1D05V_LAN_S5 1D05V_LAN_S5 1D05V_LAN_S5 MDIP0 MDIN0 AVDD10 MDIP1 MDIN1 AVDD10 MDIP2 MDIN2 AVDD10 MDIP3 MDIN3 AVDD33 C 2 1KR2J-1-GP LAN_EECS R3122 1 2 10KR2J-3-GP LAN_EEDI R3126 1 2 10KR2J-3-GP SMB_LAN_DATA R3128 1 2 10KR2J-3-GP 3D3V_LAN_VDDSREG R3125 For Enable Switch Regulator. R3124 For Disable Switch Regulator. 36 35 34 33 32 31 30 29 28 27 26 25 REGOUT VDDREG VDDREG ENSWREG EEDI/SDA LED3/EEDO EECS/SCL DVDD10 LANWAKE# DVDD33 ISOLATE# PERST# DVDD10 SMBCLK SMBDATA CLKREQ# HSIP HSIN REFCLK_P REFCLK_N EVDD10 HSOP HSON GND 3D3V_LAN_S5 GND 1D05V_LAN_REGOUT 3D3V_LAN_S5 LAN_ENSWREG LAN_EEDI LAN_EEDO 1 LAN_EECS RTL_ISOLATE# 1 49 1 The SM DATA with 10K ohm pull GND. AVDD33 AVDD33 RSET AVDD10 CKXTAL2 CKXTAL1 AVDD33 DVDD10 LED0 DVDD3 GPO/SMBALERT LED1/EESK U3101 8111F can use GPIO to inform system to do LAN PHY power down. R3120 TP3102 1D05V_LAN_S5 PCIE_WAKE# 19,65,66 3D3V_LAN_S5 PLT_RST# DY 1 R3125 2 0R0402-PAD R3124 0R2J-2-GP 2 71.08111.J03, IC PCI-E RTL8111E-VL-CGT QFN 48P GPO 59 5,18,27,36,65,66,71,80,82,83,97 Make sure PCIE_Wake# & PCIE_CLK_LAN_RQ1#connected to 10K resistor pull high close to PCH side C 13 14 15 16 17 18 19 20 21 22 23 24 RTL8111F-CGT-GP 1D05V_LAN_S5 SMB_LAN_DATA 1 LAN_CLKREQ# R3121 1D05V_LAN_EVDD10 3D3V_LAN_S5 DY C3145 1 SCD1U10V2KX-4GP 2 PCIE_RXP4_C 20 PCIE_RXN4 C3147 1 SCD1U10V2KX-4GP 2 PCIE_RXN4_C 1 R3135 C3152 D 1 2 1 LAN_PWR_ON_T Q3103 AO3419L-GP 84.03419.031 2nd = 84.00048.031 3rd = 84.03334.031 C3150 D 2 1 R3133 100KR2J-1-GP SC1U10V2KX-1GP SCD1U10V2KX-4GP 2 S SCD1U10V2KX-4GP C3151 2 0R5J-5-GP G PCIE_RXP4 1 3D3V_S5 20 2 2 0R0402-PAD 20 PCIE_CLK_LAN_REQ# 20 PCIE_TXP4 20 PCIE_TXN4 20 CLK_PCIE_LAN 20 CLK_PCIE_LAN# Q3104 2N7002K-2-GP 84.2N702.J31 2ND = 84.2N702.031 1D05V_LAN_S5 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 S G Layout Note: C3128&C3149 Close to U3101 pin21 C3137 1 2 1 C3136 2 1 2 1 2 1 2 1 2 B 27 LAN_PWR_ON SC4D7U6D3V3KX-GP 1 2 R3134 0R0603-PAD SCD1U10V2KX-4GP 1 C3144 SCD1U10V2KX-4GP 2 C3149 3D3V_LAN_VDDSREG C3143 SCD1U10V2KX-4GP SCD1U10V2KX-4GP 1 1D05V_LAN_EVDD10 C3128 SCD1U10V2KX-4GP C3142 1 2 R3131 0R0603-PAD SC1U10V2KX-1GP SCD1U10V2KX-4GP C3141 SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP 2 C3139 SCD1U10V2KX-4GP C3140 C3138 Layout Note: Close to U3101 pin C3130 ~ C3134,C3138,C3139 For VDD10 pins - 3, 6, 9, 13, 29, 41, 45. 3D3V_LAN_S5 C3135 C3134 SCD1U10V2KX-4GP 1 C3133 SCD1U10V2KX-4GP 2 C3132 SCD1U10V2KX-4GP L3102 adopt spec. C3104 change to 4.7uF X5R type capacitor C3131 SCD1U10V2KX-4GP 1 C3130 SCD1U10V2KX-4GP 2 C3129 SCD1U10V2KX-4GP SC4D7U6D3V3KX-GP 1 2 L3102 C3146 IND-4D7UH-192-GP 2 1D05V_LAN_REGOUT B Layout Note: C3135, C3140~C3144 Close to U3101 pin For VDD33 pins - 12, 27, 39, 42, 47, 48. A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei<Core HsienDesign> 221, Taiwan, R.O.C. Title LAN RTL8111F 5 4 3 2 Size A2 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 31 of 103 5 4 3 2 1 D D C C B B A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 5 4 3 2 R5U220 (CARD READER) Size A1 Document Number Date: Friday, January 06, 2012 Rev SD LA480 1 Sheet 32 of 103 A B C D E 4 4 BLANK 3 3 2 2 <Core Design> Wistron Corporation 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Reserved Size A4 Date: A B C Document Number LA480 Friday, January 06, 2012 D Rev SD Sheet 33 of E 103 1 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Reserved Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 34 of 1 103 A 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title USB 3.0 Controller Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 35 of 1 103 A 5 4 3 2 1 10KR2J-3-GP Q3603 19,27,37,47 PM_SLP_S3# Z_12V_D4 2 2 Q3605 G D S PM_SLP_S3 4 3 5 2 6 1 PM_SLP_S3# 2N7002K-2-GP 2N7002KDW-GP 84.2N702.J31 2nd = 84.2N702.031 84.2N702.A3F 2nd = 84.DM601.03F 3D3V_S5 1 2 3 4 D 8 D 7 D 6 D 5 AO4468-GP 1D5V_S0 1D5V_S3 1 2 3 4 C3611 SCD01U50V2KX-1GP U3602 S S S G 84.04468.037 2nd = 84.08882.037 1 83.00016.K11 2ND = 83.00016.M11 3rd = 83.00016.N11 D 3D3V_S0 83.9R103.D3F RUN_ENABLE_ALL_G 1 R3612 D 8 D 7 D 6 D 5 AO4468-GP 0R0402-PAD D3602 MMPZ5239BPT-GP U3606 S S S G D 8 D 7 D 6 D 5 AO4468-GP 84.04468.037 2nd = 84.08882.037 2 R3617 100KR2J-1-GP 3D3V_AUX_S5 2 D3603 BAS16-6-GP U3601 S S S G 84.04468.037 2nd = 84.08882.037 2 R3626 A 1 3 PM_SLP_S3# 2 1 1 G 330KR2J-L1-GP 1 R3618 2 Z_12V_G3 2 R3621 330KR2J-L1-GP 1 SCD22U25V3KX-GP R3620 10KR2J-3-GP C3612 C3606 K 1 NDS0610-NL-GP DY SCD01U50V2KX-1GP 1 SCD1U50V3KX-GP DY D 1 S 10KR2J-3-GP 2 Z_12V 2 R3619 19 1 2 3 4 2 C3607 Q3604 SYS_PWROK 1KR2F-3-GP 19,27,37,47 RUN_ENABLE 2ND = 84.00610.C31 84.S0610.B31 1 2 2 1 28,42 IMVP_PWRGD DCBATOUT R3614 CRB : 1K R3614 D 5V_S5 5V_S0 Run Power Power Sequence 1 1D5V_S0 MAX Current 3000 mA Design Current 2100 mA Total= 11.39A C C DY 1 1D05V_VTT 2 H_THERMTRIP# R3622 56R2J-4-GP 5,22 E 3D3V_S5 1 Q3601 MMBT2222A-3-GP R3608 2 84.2N702.J31 2ND = 84.2N702.031 19,27,37,47 3 1 1 2 PURE_HW_SHUTDOWN# PM_SLP_S3# 27,28,86 2ND = 83.00016.M11 3rd = 83.00016.N11 R3602 200KR2F-L-GP DY D3601 BAS16-6-GP 83.00016.K11 1 3V_5V_EN 37,97 Q3606 2N7002K-2-GP 2 41 PS_S3CNTRL 100KR2J-1-GP G 2 2 1 R3632 2K2R2J-2-GP S B D 2 C R3616 4K7R2J-2-GP C3602 SCD1U10V2KX-5GP 1 PLT_RST# 1 5,18,27,31,65,66,71,80,82,83,97 R3603 2 S5_ENABLE 2KR2F-3-GP TP3601 27,97 1 B B A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Power Plane Enable 5 4 3 2 Size A1 Document Number Date: Friday, January 06, 2012 Rev SD LA480 1 Sheet 36 of 103 3 Close to DIMM S3 Power Reduction Circuit SM_DRAMPWROK DEL R3714 R3705 ->100K DY C3701 0D75V_S0 R3703 22R2J-2-GP R3704 220R2J-L2-GP DY Q3701 2 2N7002K-2-GP 84.2N702.J31 2ND = 84.2N702.031 Q3702 DY 2N7002K-2-GP 2N7002K-2-GP S G 84.2N702.J31 2ND = 84.2N702.031 PS_S3CNTRL 36,97 PS_S3CNTRL SM_DRAMPWROK must have a maximum of 15ns rise or fall time over VDDQ * 0.55± 200mV and the edge must be monotonic Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK 3D3V_S5 S 84.2N702.J31 2ND = 84.2N702.031 PM_SLP_S3# 19,27,36,47 G FROM M1/M3 C3701 SCD1U10V2KX-4GP Q3702_D R3705 100KR2J-1-GP G 2 +V_SM_VREF D D 1 1 +V_SM_VREF_CNT 9 D D S 12 DY Q3701_D Q3708 D 1D5V_S0 2 DY20R2J-2-GP 1 R3707 1 1 Close to CPU S3 Power Reduction Circuit Processor VREF_DQ Implementation 2 2 4 1 5 Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK add 0.1uF 1D5V_S3 1 1 1D5V_S0 5 3 GND OUT Y 4 5 D S S3 Power Reduction Circuit SM_DRAMRST# 1 R3711 0R0402-PAD S D 1 SM_DRAMRST# G 2 DY 2 0R2J-2-GP DY R3720 0R2J-2-GP R3701 4K99R2F-L-GP DY 2N7002K-2-GP DY SM_DRAMRST#_D 1 2 R3712 1KR2F-3-GP C3702 SC100P50V2JN-3GP DDR3_DRAMRST# 14,15 84.2N702.J31 2ND = 84.2N702.031 DRAMRST_CNTRL_PCH 1 G 36,97 PS_S3CNTRL DY VDDPWRGOOD_D Q3707 R3722 39R2J-L-GP 2SM_DRAMRST#_R 2 OD AND gate required 73.01G09.AAH 2nd = 73.01G09.0AB 3rd = 73.01G09.BAH DY Q3703 VDDPW RGOOD 5 1 74VHC1G09DFT2G-GP VDDPW RGOOD_R 1 2 R3719 130R2F-1-GP 2 DY 2 C3704 SCD1U10V2KX-5GP 1 R3709 2 VCC IN A 1 IN B 2 2 1 2 U3701 2 PM_DRAM_PW RGD_R 0R0402-PAD 0D75V_EN 1 2 C R3706 1KR2F-3-GP R3708 200R2F-L-GP 1 1 R3715 19 PM_DRAM_PW RGD 1 R3713 200R2F-L-GP C 2 2N7002K-2-GP 12,20 C3703 SCD047U16V2KX-1-GP 84.2N702.J31 2ND = 84.2N702.031 B B 5 S3 Power Reduction Q3704 G 36,97 PS_S3CNTRL D 0D75V_EN S 2N7002K-2-GP 84.2N702.J31 2ND = 84.2N702.031 1 1.05VTT_PW RGD 45,48 2 R3710 0R0402-PAD 19,27,36,47 PM_SLP_S3# 1 R3716 2 DY 22R2J-2-GP 0D75V_EN 46 <Core Design> 1 A A Wistron Corporation 2 DY C3705 SCD1U10V2KX-5GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 5 4 3 2 Size A3 Document Number Date: Friday, January 06, 2012 ADAPTER Rev SD LA480 Sheet 1 37 of 103 5 4 3 2 1 Adaptor in to generate DCBATOUT D D ADT_TYPE_R1 1 1 2 PR3806 0R0402-PAD ADT_TYPE 27 3 2 R3801 274R2F-GP C ADT_TYPE_R PD3802 1 2 C 3D3V_AUX_KBC BAV99-8-GP DCIN14 AD_JK AD+_2 A AD_DETECT 27 1 B E D D D D 8 7 6 5 C AO4407AL-GP 84.04407.G37 Id= -10A Qg= -22nC Rdson=14~22mohm PR3804 27 AD_OFF B R1 C E R2 PDTC124EU-1-GP B PDTA124EU-1-GP 84.00124.K1K 2ND = 84.00024.01K PR3802 100KR2J-1-GP PR3805 DY 100KR2J-1-GP 2 2 PQ3801 1 1 DY 34K8R2F-1-GP 2 1 2 DY AD_OFF#_1 2 PQ3802 PC3803 SCD1U50V3KX-GP 1 2 3 4 PU3801 S S S G PR3801 PC3802 1 83.P6SBM.DAG 2ND = 83.P6SMB.JAG 3TH = 83.P6SMB.CAG DY 2 PC3801 SCD1U50V3KX-GP 1 1 PR3803 DY 200KR2F-L-GP DY 2 1 PC3806 SCD1U50V3KX-GP 2 SC1KP50V2KX-1GP 2 1 PC3807 SCD1U50V3KX-GP SC1U50V5ZY-1-GP 2 C3802 200KR2F-L-GP SC100P50V2JN-3GP C3801 PD3801 P6SBMJ27APT-GP R2 1 MLX-CONN10-4-GP K 2 1 1 2 AD_JK_F FUSE-7A24V-5-GP 21.D0241.205 AD+ F3801 1 7 8 9 10 2 6 2 3 4 5 R1 1 B 84.00124.H1K 2ND = 84.00124.X1K AFTP3805 AFTP3804 AFTP3801 AFTP3802 AFTP3803 AFTP3806 1 1 1 1 1 1 AD_JK_F ADT_TYPE_R GND DCIN14 for 14" VB480 & VB485 DCIN15 for 15" VB580 & VB585 <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 5 4 3 2 DCIN_JACK Size A3 Document Number Date: Friday, January 06, 2012 Rev LA480 SD Sheet 1 38 of 103 5 4 3 2 1 D D BATTERY CONNECTOR 1 PC3902 SC2200P50V2KX-2GP 2 2 PC3901 SCD1U50V3KX-GP 1 BT+ Swap for V480 BAT1 RN3901 8 7 6 5 D3902 1 BAV99-8-GP 2 DY 3 DY 3 BAT_IN#_1 ME change P/N at SIT Old 20.81529.007 Nwq 20.81720.007 1 1 BAT_SCL BATA_SDA_1 BATA_SCL_1 BT+ C 20.81720.007 BAT_SDA B 1 1 1 1 1 1 BAT_IN# AFTP3902 AFTP3903 AFTP3904 AFTP3905 AFTP3906 AFTP3907 2 2 AFTP3909 AFTP3910 Varistor BAT_VCC BAT_VCC I2C_CLK I2C_DAT TEMP GND GND GND GND ALP-CON7-33-GP D3903 1 2 DY 3 2 2 K 1 2 1 DY A AFTP3908 DY BATA_SCL_1 BATA_SDA_1 BAT_IN#_1 PC3903 1 SC10P50V2JN-4GP DY 1 MLVS0402M04-GP 83.5R603.D3F 2ND = 83.5R603.Q3F 1 MLVS0402M04-GP PC3905 SC470P50V2KX-3GP PD3901 MMPZ5232BPT-GP-U 1 PC3904 1 PL3903 1 2 3 4 5 6 7 8 9 SC10P50V2JN-4GP PL3902 MLVS0402M04-GP SRN33J-7-GP PL3901 2 1 2 3 4 27,40 BAT_SCL 27,40 BAT_SDA 27 BAT_IN# C BT+ BAV99-8-GP B D3901 1 2 BAV99-8-GP 3D3V_AUX_KBC DY on LAB stage <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 5 4 3 2 BATT_CONN Size Document Number Date: Friday, January 06, 2012 Rev LA480 SD Sheet 1 39 of 103 5 4 AD+_TO_SYS 8 7 6 5 AD+ 17 BQ24737_BTST 1 1 4 3 2 1 PC4017 SCD1U50V3KX-GP Charger Current=1.4~3.6A 16 PWR_CHG_IOUT BQ24737RGRR-GP 1 1 2 1 2 7 1 2 PR4024 7D5R2F-GP 4 3 2 1 1 BQ24737_SRN BM# 1 11 BQ24737_SRP SC10U25V5KX-GP SRN BQ24737_REGN_R 13 12 PC4020 PC4021 PC4019 SC10U25V5KX-GP SRP ILIM PU4005 SC10U25V5KX-GP 10 PC4025 SC470P50V2KX-3GP SIS412DN-T1-GE3-GP S S S G BQ24737_ILIM PR4020 100KR2J-1-GP PR4025 10R2F-L-GP 1 2 1 BQ24737_LODRV SDA D D D D 8 BT+ PR4017 D01R3721F-GP-U 1 2 2 15 PL4001 BT+_R 1 2 IND-5D6UH-48-GP-U1 2 LODRV BQ24737_PHASE 5 6 7 8 SCL BQ24737_HIDRV 19 1 9 18 2 PHASE 2 CMPIN 1 CMPOUT 2 4 BQ24737_CMPIN BAT_SCL 2 2 PU4004 SIS412DN-T1-GE3-GP 2 1 2 5 6 7 8 PC4009 SC1U10V2KX-1GP 2 1 2 2 2 1 PG4004 GAP-CLOSE-PWR-3-GP S BTST HIDRV PR4016 3D3MR2J-GP 27,39 BAT_SDA 3D3V_AUX_S5 CHG_AGND A PD4003 CH520S-30PT-GP PG4003 GAP-CLOSE-PWR-3-GP 27,39 ACDET REGN 3 CHG_AGND C 1 2 1 2 2 1 2 2 PR4008 100KR2F-L1-GP VCC BQ24737_CMPOUT PR4014 120KR2F-L-GP CHG_AGND CHG_AGND 6 BOM CTRL R2 BQ24737_CMPOUT BQ24737_ACDET K SCD1U50V3KX-GP PC4022 PQ4005 2N7002A-7-GP G 1 1 1 1 PC4007 SCD01U50V2KX-1GP 20 PR4011 100KR2J-1-GP 2 0R2J-2-GP 1 2 1 D PR4007 12K4R2F-GP R1 PR4019 1 1 PU4003 PC4006 SCD1U25V2KX-GP S S S G PWR_CHG_IOUT STOP_CHG# 2 2 CHG_AGND 1st = 83.R2003.P8F 2nd = 83.1R003.N8F 3rd = 83.R2003.B8M DCBATOUT 68.00143.041 BQ24737_REGN CHG_AGND 2 1 2 CHG_AGND BQ24737_REGN L4001 1 2 BLM18PG330SN1D-GP L4002 1 2 BLM18PG330SN1D-GP DCBATOUT_L PC4004 SCD1U50V3KX-GP D D D D 27 BQ24737_VCC PC4001 SC1U25V5KX-1GP 2 PR4015 20R5F-1GP PR4006 316KR3F-2-GP PR4010 49K9R2F-L-GP 1 1 2 1 2N7002KDW-GP 84.2N702.A3F 2nd = 84.DM601.03F STOP_CHG# connects to KBC D PC4005 SC10U25V5KX-GP PC4002 SCD1U50V3KX-GP 1 6 1 PR4009 10KR2F-2-GP Id= -10A Qg= -22nC Rdson=14~22mohm 68.00143.041 2 5 1 100K 3D3V_AUX_S5 8 7 6 5 PC4024 SC10U25V5KX-GP 118k D D D D 1 PC4003 PWR_CHG_ACN 2 2 1 AC_IN 4 AD_JK 120w PR4005 470KR2J-2-GP ACN 100K PQ4001 3 PWR_CHG_ACP 60.4k 64.60425.6DL PR4003 49K9R2F-L-GP PG4002 GAP-CLOSE-PWR-3-GP 2 90w PU4002 S S S G AO4407AL-GP PG4001 GAP-CLOSE-PWR-3-GP ACP 100K AD+ 1 41.2k AD+_G_2 2 100K 80w 1 2 3 4 84.04407.G37 84.04407.G37 Id= -10A Qg= -22nC Rdson=14~22mohm 1 65w BT+ 1 PR4004 2 D01R3721F-GP-U 2 R2 DCBATOUT PR4002 100KR2J-1-GP AD+_G_1 R1 12.4K 64.12425.6DL DC_IN_D AD+ total power 1 2 2 PR4001 10KR2F-2-GP 1 2 3 4 2 AO4407AL-GP 1 A8( ANNIE/ASTRO) PR4007,PR4008 PU4001 S S S G D D D D 1 SSID = Charger D 3 C GND ACOK# IOUT 1 2 PR4013 0R0402-PAD 1 PR4034 DY BAT_SDA 2 3K3R2J-3-GP 27 CHG_AGND 3D3V_AUX_S5 CHG_AGND 2 PC4016 SCD1U50V3KX-GP BQ24737_CSON_1 1 CHG_ON# 1 BAT_SCL 2 3K3R2J-3-GP G S DY BQ24737_CSOP_1 2 1 PC4011 SC220P50V2KX-3GP 2 2 D 1 2 PR4018 0R0402-PAD PC4023 SCD1U25V2KX-GP 1 PR4033 27 1 PR4032 100KR2J-1-GP PQ4007 2N7002A-7-GP CHG_AGND 3D3V_AUX_S5 AD_IA 1 21 1 PR4026 33KR2F-GP 2 DY 5 14 2 DY BQ24737_REGN 3D3V_AUX_S5 GND PR4022 10KR2F-2-GP CHG_AGND PR4029 100KR2J-1-GP 1 2 3D3V_AUX_S5 PR4030 100KR2J-1-GP 27 AC_IN# AC_IN# B 2 B D AC_IN 84.2N702.E31 2ND = 84.2N702.D31 AC_IN# PQ4008 G S 2N7002A-7-GP A A <Core Design> Wistron Corporation 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title <Title> 5 4 3 2 Size A2 Document Number LA480 Date: Friday, January 06, 2012 Rev SD 1 Sheet 40 of 103 5 4 3 2 1 SSID = PWR.Plane.Regulator_5v3p3v D DCBATOUT DCBATOUT DCBATOUT_PWR_3D3V PWR_5V_EN1 D DCBATOUT_PWR_5V 2 1 PR4121 0R0402-PAD PG4102 1 2 PG4133 1 2 GAP-CLOSE-PWR PG4103 1 2 GAP-CLOSE-PWR PG4131 1 2 GAP-CLOSE-PWR PG4104 1 2 PWR_3D3V_EN2 2 1 PR4127 0R0402-PAD GAP-CLOSE-PWR PG4130 1 2 3V_5V_EN 36 GAP-CLOSE-PWR GAP-CLOSE-PWR PG4132 1 2 GAP-CLOSE-PWR PG4128 1 2 GAP-CLOSE-PWR PG4129 1 2 DCBATOUT GAP-CLOSE-PWR DCBATOUT_PWR_3D3V DCBATOUT_PWR_5V GAP-CLOSE-PWR 2 1 1 2 2 1 1 2 GAP-CLOSE-PWR PG4115 1 2 PC4129 SC2200P50V2KX-2GP 1 2 PC4123 SC560P50V-GP 5V_PWR_2 PR4114 0R2J-2-GP PR4115 15KR2F-GP PWR_5V_FB1_R 2 1 2 DY 1 1 13 3 2 PC4127 SC1U10V2KX-1GP 21 GAP-CLOSE-PWR PG4114 1 2 DY B 1 PC4125 SC18P50V2JN-1-GP PR4120 10KR2F-2-GP PC4126 SC1U10V2KX-1GP 3D3V_PWR_2 3D3V_AUX_S5 Close to VFB Pin (pin2) 2 1 PR4116 0R0603-PAD 2 2 PR4119 100KR2J-1-GP 1 1 DY 2 1 1 2 DY 2 1 3D3V_S5 VREG5 VREG3 2 GAP-CLOSE-PWR-3-GP GND PWR_5V3D3V_VREG3 PWR_3D3V_FB2_R PC4124 DYSC18P50V2JN-1-GP 19 S 2 1 2 PG4101 1 2 1 2 PGOOD 3D3V_PWR_2 PR4117 10KR2F-2-GP PR4102 121KR2F-L-GP 19 G PC4120 1 PWR_5V_CS1 PT4101 PG4117 1 1 Id=16A, Qg=7.3nC, Rdson=13.5~16.5 mohm 1 2 VCLK 7 1 1 PWR_5V_EN1 PR4111 DY 2D2R5F-2-GP 2 CS1 20 PU4102 SIS412DN-T1-GE3-GP 2 CS2 PWR_5V_FB1 2 5 EN1 PWR_5V_VO1 2 2 PWR_3D3V_CS2 EN2 14 GAP-CLOSE-PWR PG4122 1 2 68.3R310.20A 1PWR_5V_SNUB 6 VFB1 PR4101 121KR2F-L-GP 1 2 5 6 7 8 5 6 7 8 PWR_3D3V_EN2 VFB2 TPS51225CRUKR-GP 3V_5V_POK DCBATOUT PR4122 10KR2F-2-GP DY 5 2 DCBATOUT_UVP_1 6 DY PD4105 Vz=5.1V ECRST# DCBATOUT_UVP_2 DY27MMPZ5231BPT-GP 1 3 1 4 1 1 2 DY 2 1 PU4106 PR4125 40K2R2F-GP 2 1 3D3V_PWR_2 D C GAP-CLOSE-PWR PG4121 1 2 PL4101 1 2 IND-3D3UH-57GP 4 3 2 1 4 G PR4113 DCBATOUT PWR_5V_DRVL1 4 3 2 1 1 12 VIN 1 2 3 4 S DY0R2J-2-GP Close to VFB Pin (pin5) PWR_5V_LL1 S S S G PWR_3D3V_FB2 PC4128 SC2200P50V2KX-2GP B 18 8 7 6 5 VO1 DY Id=12A, Qg=3.8nC, SC330P50V3KX-GP Rdson=24~30 mohm PR4112 6K65R2F-GP 2 2 1 2 8 7 6 5 D D D D S S S G 1 2 3 4 1 2 1PWR_3D3V_SNUB DRVL1 D D D D 1 1 2 2 1 2 1 DRVL2 16 15 GAP-CLOSE-PWR PG4120 1 2 SE330U6D3VM-15-GP 2 SW1 PWR_5V_DRVH1 PG4119 1 2 Cyntec. 3.3uH 6.5*6.9*3 DCR=28~30mohm 5V_PWR Idc=6A, Isat=13.5A SCD1U10V2KX-4GP 1 DRVH1 SW2 PWR_5V_VBST1 S 5V_S5 5V_PWR Design Current=5.25A OCP>7.8A GAP-CLOSE-PWR-3-GP 2 DRVH2 17 G S S S G 2 VBST1 PC4116 SCD1U50V3KX-GP VBST2 SC10U25V5KX-GP 8 11 SCD1U50V3KX-GP PC4118 1 2PWR_5V_VBST1_1 1 2 1D5R2F-GP PR4109 D SC10U25V5KX-GP PWR_3D3V_DRVL2 PC4121 GAP-CLOSE-PWR PU4101 SIS412DN-T1-GE3-GP D D D D SIS412DN-T1-GE3-GP GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR PG4113 1 2 2 D PR4110 DY 2D2R5F-2-GP PU4105 PG4116 SE220U6D3VM-30-GP SCD1U10V2KX-4GP GAP-CLOSE-PWR PG4112 1 2 PT4102 G PR4108 PC4117 1PWR_3D3V_VBST2_1 1 2 PWR_3D3V_VBST29 SCD1U50V3KX-GP 1D5R2F-GP PWR_3D3V_DRVH210 PWR_3D3V_LL2 68.2R210.20B PC4119 PU4103 PC4115 S S S G S PL4102 1 2 IND-2D2UH-46-GP-U GAP-CLOSE-PWR PG4111 1 2 PU4104 SIS412DN-T1-GE3-GP PC4114 Id=12A, Qg=3.8nC, Rdson=24~30 mohm D D D D GAP-CLOSE-PWR PG4109 1 2 DY SCD01U50V2KX-1GP 3D3V_PWR GAP-CLOSE-PWR PG4110 1 2 D Cyntec. 2.2uH 7.3*6.6*3 DCR=18~20mohm Idc=8A, Isat=14A 3D3V_PWR PG4108 1 2 Id=12A, Qg=3.8nC, Rdson=24~30 mohm SC10U25V5KX-GP 3D3V_S5 SC10U25V5KX-GP C SCD1U50V3KX-GP SC10U25V5KX-GP Design Current=5.25A OCP>7.8A PC4111 1 PC4112 PC4113 PC4109 PC4110 PR4129 750KR2F-GP 2N7002DW-7F-GP DY PR4126 1KR2F-3-GP 2 DY A 2 A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title TPS51123_5V_3D3V Size Document Number Date: Friday, January 06, 2012 Rev SD 5 4 3 2 Sheet 1 41 of 103 5 4 1 2 2 Close to PWR IC PC4202 Open 3 DY SCD22U10V2KX-1GP D 1D05V_VTT 1 PR4202 2 130R2F-1-GP H_CPU_SVIDDAT 1 PR4203 2 H_CPU_SVIDCLK PW R_CPU_CORE_CCSP2 43 PW R_CPU_CORE_CCSN2 43 PW R_CPU_CORE_CCSN1 43 PW R_CPU_CORE_CCSP1 43 CPU_CURRENT PC4201 1 D 27 2 SCD22U10V2KX-1GP PR4204 1 2 1 2 121KR2F-L-GP PR4201 75KR2F-GP 54D9R2F-L1-GP 1 VCORE_AGND VCORE_AGND PC4204 1 VCCSENSE 8 VSSSENSE DY 2 SCD1U10V2KX-4GP PR4206 1 2 NTC-100K-1-GP PWR_CPU_CORE_CIMON PWR_CPU_CORE_COCP-I PWR_CPU_CORE_CTHERM 8 PWR_CPU_CORE_CCOMP SC33P50V2JN-3GP PR4205 1 2 10K7R2F-GP 3D3V_S5 PW R_CPU_CORE_VREF PC4203 1 2 1 PR4207 2PW R_CPU_CORE_VREF 15K8R2F-GP 5V_S5 C 0R0402-PAD 2 PR4232 2 PR4213 2 PR4233 2 PR4231 1 1 0R0402-PAD 1 0R0402-PAD 1 0R0402-PAD 0R0402-PAD PW R_CPU_CORE_VCLK PW R_CPU_CORE_ALERT# PW R_CPU_CORE_VDIO PW R_CPU_CORE_VR_HOT# PW R_CPU_CORE_SLEW A PW R_GFX_PW RGD PW R_CPU_CORE_GF-IMAX 1 PU4201 TPS51640ARSLR-GP 49 48 47 46 45 44 43 42 41 40 39 38 37 2 GND V5 CDH1 CBST1 CSW1 CDL1 V5DRV PGND CDL2 CSW2 CBST2 CDH2 VBAT PW R_CPU_CORE_CDH1 43 PW R_CPU_CORE_CBST1 43 5V_S5 PW R_CPU_CORE_CSW 1 43 PW R_CPU_CORE_CDL1 43 N221068268 1 PR4216 PW R_CPU_CORE_CDL2 43 PW R_CPU_CORE_CSW 2 43 PW R_CPU_CORE_CBST2 43 PW R_CPU_CORE_CDH2 43 2 10KR2F-2-GP 1 PW R_CPU_CORE_VRON 1 CF_IMAX VREF V3R3 VR_ON CPGOOD VCLK ALERT# VDIO VR_HOT# SLEWA GPGOOD GF_IMAX SC2D2U10V3KX-1GP PC4207 2 2 PR4234 13 14 15 16 17 18 19 20 21 22 23 24 1 3D3V_S5 48 D85V_PW RGD 28,36 IMVP_PW RGD 8 H_CPU_SVIDCLK 8 VR_SVID_ALERT# 8 H_CPU_SVIDDAT 5,27 H_PROCHOT# PW R_CPU_CORE_CF-IMAX PW R_CPU_CORE_VREF 2 CGFB CVFB CCOMP CCSN3 CCSP3 CCSP2 CCSN2 CCSN1 CCSP1 CIMON COCP_I CTHERM SCD33U6D3V2KX-1-GP PC4206 1 SC4D7U10V3KX-GP 2 PR4211 10KR2J-3-GP PR4210 10R2F-L-GP VCORE_AGND 2 1 2 PC4205 SC1U6D3V2KX-GP 1 VCORE_AGND PR4209 1 2 90K9R2F-GP GGFB GVFB GCOMP GCSN GCSP GIMON GOCP_I GTHERM GSKIP# GPWM CSKIP# CPWM3 3D3V_S0 PR4208 1 2 24KR2F-GP 12 11 10 9 8 7 6 5 4 3 2 1 C PC4208 9 VSS_AXG_SENSE B 9 VCC_AXG_SENSE 1 PR4218 1 1 PW R_CPU_CORE_VREF PR4221 169KR2F-1-GP 2 2 PR4220 200KR2F-L-GP PW R_CPU_CORE_SLEW A 1 1 PW R_CPU_CORE_GF-IMAX 1 PC4209 VCORE_AGND 2 SC33P50V2JN-3GP B 1 2 PW R_CPU_CORE_VREF PR4217100KR2F-L1-GP PW R_CPU_CORE_CSKIP# 1 2 VCORE_AGND PR4219 56KR2F-GP 2 5K76R2F-2-GP DY PW R_GFX_GPW M 44 1 PR4222 PW R_CPU_CORE_VREF 2 DY 100KR2F-L1-GP 1 PR4223 DY 2 20KR2F-L-GP VCORE_AGND PR4225 150KR2F-L-GP PW R_GFX_GSKIP# 44 2 PW R_CPU_CORE_VREF 15K8R2F-GP 1 PR4226 2 2 PR4224 30KR2F-GP 25 26 PWR_CPU_CORE_GCOMP 27 28 29 PWR_CPU_CORE_GIMON 30 PWR_CPU_CORE_GOCP-I 31 PWR_CPU_CORE_GTHERM 32 33 34 35 36 DCBATOUT_VCC_CORE 1 PR4227 1 PC4211 VCORE_AGND 2 NTC-100K-1-GP DY 2 SCD1U10V2KX-4GP 44 PW R_GFX_CORE_GSCN PR4228 44 PW R_GFX_CORE_GSCP 1 2 1 2 PR4229 75KR2F-GP VCORE_AGND 309KR2F-GP 1 2 PR4230 0R0402-PAD A PC4210 1 <Core Design> 2 SCD22U10V2KX-1GP Wistron Corporation VCORE_AGND 1 2 PR4239 0R0402-PAD 5 4 3 A 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. VGA_CURRENT 27 Title 2 TPS51640_CPU_CORE(1/3) Size Document Number Date: Friday, January 06, 2012 Rev <Doc> SD Sheet 1 42 of 103 5 4 3 2 1 DCBATOUT_VCC_CORE 1 42 PW R_CPU_CORE_CSW 1 9 PW R_CPU_CORE_CBST1_1 2 GAP-CLOSE-PW R 1 2 1 2 ST330U2VDM-4-GP 1 2 ST330U2VDM-4-GP ST330U2VDM-4-GP 1 PT4305 PT4306 SE100U25VM-10GP C 1st = 69.60011.071 2 SCD027U25V2KX-GP 42 PW R_CPU_CORE_CSW 2 9 PW R_CPU_CORE_CCSN1 42 PW R_CPU_CORE_CCSP1 42 1 2 1 DY 2 1 2 1 2 2 1 SC10U25V5KX-GP PC4305 42 PW R_CPU_CORE_CDH2 SC10U25V5KX-GP PC4307 1 DCBATOUT_VCC_CORE PU4304 B PR4235 1 2 NTC-100K-1-GP PT4303 BOM control PC4306 84.03606.037 FDMS3606S-GP-U 1 PC4216 SC10U25V5KX-GP PU4304 2 2 PR4237 1 2nd source SC10U25V5KX-GP PC4310 84.03606.037 FDMS3606S-GP-U 1 PR4238 28KR2F-GP PU4303 PT4302 121KR2F-L-GP 84.03606.037 84.03606.037 FDMS3606S-GP-U 2 PG4301 GAP-CLOSE-PW R-3-GP 1 7 6 5 FDMS3600-02-RJK0215-COLAY-GP PU4302 GAP-CLOSE-PW R PG4309 1 2 PR4236 18KR2F-GP 1 84.03606.037 FDMS3606S-GP-U 1 2 L-D36UH-1-GP 2 2 3 4 10 2 8 42 PW R_CPU_CORE_CDL1 PU4301 2 1 2 1 1 9 Main source GAP-CLOSE-PW R PG4308 1 2 PU4302 1 C GAP-CLOSE-PW R PG4307 1 2 PL4301 DY 2 D GAP-CLOSE-PW R PG4306 1 2 VCC_CORE FDMS3600-02-RJK0215-COLAY-GP SCD1U50V3KX-GP GAP-CLOSE-PW R PG4305 1 2 Design current: 42.4A 1 1 2 PR4301 0R3J-0-U-GP 42 PW R_CPU_CORE_CBST1 DCBATOUT_VCC_CORE PG4304 1 2 7 6 5 8 PC4301 1 2 2 42 PW R_CPU_CORE_CDH1 2 3 4 10 DY SC10U25V5KX-GP PC4304 PU4301 SC10U25V5KX-GP PC4303 D SC10U25V5KX-GP PC4302 SC10U25V5KX-GP PC4312 1 DCBATOUT PC4315 SCD1U50V3KX-GP PC4316 SCD1U50V3KX-GP 2 3 4 10 B 7 6 5 8 PW R_CPU_CORE_CBST2_1 VCC_CORE FDMS3600-02-RJK0215-COLAY-GP PL4302 84.03606.037 2 2 L-D36UH-1-GP PU4303 1 PT4304 1 PT4301 ST330U2VDM-4-GP 2 ST330U2VDM-4-GP 8 42 PW R_CPU_CORE_CDL2 2 7 6 5 PG4302 GAP-CLOSE-PW R-3-GP PR4308 18KR2F-GP 9 2 2 3 4 10 1 2 SCD1U50V3KX-GP 1 1 PC4308 1 1 42 PW R_CPU_CORE_CBST2 1 2 PR4302 0R3J-0-U-GP PR4309 FDMS3600-02-RJK0215-COLAY-GP 1 2 DY 121KR2F-L-GP PR4310 1 28KR2F-GP 2 1 2 NTC-100K-1-GP PR4303 1st = 69.60011.071 A 1 PC4314 2 SCD027U25V2KX-GP <Core Design> PW R_CPU_CORE_CCSN2 A Wistron Corporation 42 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. PW R_CPU_CORE_CCSP2 5 4 3 2 42 Title TPS51640_CPU_CORE(2/3) Size Document Number Date: Friday, January 06, 2012 Rev <Doc> SD Sheet 1 43 of 103 5 4 3 Main source D DCBATOUT DCBATOUT_VCC_GFXCORE PU4402 84.07608.037 FDMS7608S-GP PU4403 84.07608.037 FDMS7608S-GP 2 1 2nd source D PG4401 1 2 GAP-CLOSE-PW R PG4402 1 2 BOM control 1 PC4410 SCD1U50V3KX-GP 2 1 2 2 2 1 2 2 3 4 10 1 SC10U25V5KX-GP PC4404 PW R_GFX_CORE_DRVH SC10U25V5KX-GP PC4403 PU4402 SC10U25V5KX-GP PC4402 GAP-CLOSE-PW R SC10U25V5KX-GP PC4409 GAP-CLOSE-PW R PG4404 1 2 1 DCBATOUT_VCC_GFXCORE 1 GAP-CLOSE-PW R PG4403 1 2 Design current: 22A 9 C 7 6 5 8 PW R_GFX_CORE_SW C VCC_GFXCORE PL4401 FDMS3600-02-RJK0215-COLAY-GP 84.07608.037 PU4403 PR4405 1 28KR2F-GP 2 1 1 FDMS3600-02-RJK0215-COLAY-GP 84.07608.037 PT4403 2 8 PT4402 ST330U2VDM-4-GP 7 6 5 PG4303 PT4401 GAP-CLOSE-PW R-3-GP PR4407 1 2 121KR2F-L-GP 1 PW R_GFX_CORE_DRVL 2 9 2 PR4410 18KR2F-GP ST330U2VDM-4-GP 2 3 4 10 1 2 L-D36UH-1-GP 2 SC1U25V3KX-1-GP 1 ST330U2VDM-4-GP 2 2 2PW R_GFX_CBST1_1 1 0R3J-0-U-GP PC4401 1 1 PR4401 1 PW R_GFX_CORE_BST 1 2 NTC-100K-1-GP PR4409 1st = 69.60011.071 1 PC4408 B 2 SCD022U25V2KX-GP PW R_GFX_CORE_GSCN 42 B PW R_GFX_CORE_GSCP 42 PU4401 42 PW R_GFX_GSKIP# 42 PW R_GFX_GPW M 1 2 3 4 BST SKIP# PWM GND GND DRVH SW VDD DRVL 9 8 7 6 5 5V_S5 PW R_GFX_CORE_DRVH PW R_GFX_CORE_SW PW R_GFX_CORE_DRVL 1 PW R_GFX_CORE_BST 2 TPS51601DRBR-GP PC4407 SC2D2U10V3KX-1GP <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 5 4 3 2 TPS51640_CPU_CORE(3/3) Size Document Number Date: Friday, January 06, 2012 Rev <Doc> SD Sheet 1 44 of 103 5 4 3 2 1 TPS51219 for 1D05V DCBATOUT 1 2 DY PWR_DCBATOUT_VCCP 1V 1 1 2 2 4 3 2 1 GAP-CLOSE-PWR-3-GP PG4527 1 2 5 6 7 8 2 4 3 2 1 2 PC4518 SC2D2U6D3V2MX-GP PR4520 64K9R2F-1-GP G S 84.00460.037 Id=40A, Qg=16.8~25.5nC, Rdson=4.9~6.1 mohm 1 PT4502 PU4503 1 PWR_VCCP_V5FILT 0.68uH 7.3*6.6*3 DCR=5~5.5mohm Idc=15.5A, Isat=25A D 2 1 PR4514 3D3R2F-GP GAP-CLOSE-PWR-3-GP PG4528 1 2 PT4501 GAP-CLOSE-PWR-3-GP PG4529 1 2 GAP-CLOSE-PWR-3-GP PG4530 1 2 77.C3371.051 330uF, 2.5V, ESR=9mΩ, Iripple=3.726A GAP-CLOSE-PWR-3-GP PG4531 1 2 C GAP-CLOSE-PWR-3-GP PG4532 1 2 2 1 2 1 2 L GAP-CLOSE-PWR-3-GP PG4526 1 2 1D05V_PWR 2 1 1 2 COMP TRIP GND PGND 5 1PWR_VCCP_TRIP 6 7 8 1 2 10KR2F-2-GP 1.05V 5V_S5 SIR460DP-T1-GE3-GP H GAP-CLOSE-PWR-3-GP PG4525 1 2 Design Current = 11.69A OCP> 17.9A COIL-D68UH-5-GP D D D D Vout REFIN SC1KP50V2KX-1GP PR4515 0R0402-PAD GAP-CLOSE-PWR-3-GP PG4524 1 2 PL4501 S S S G SC2200P50V2KX-2GP PC4519 DY C GAP-CLOSE-PWR-3-GP PG4523 1 2 GAP-CLOSE-PWR 1 TPS51219RTER-GP PC4512 SCD01U50V2KX-1GP 1 2PWR_VCCP_COMP GAP-CLOSE-PWR PG4518 1 2 S PWR_VCCP_SW PWR_VCCP_DRVH PWR_VCCP_DRVL D GAP-CLOSE-PWR-3-GP PG4522 1 2 SE330U2D5VDM-1GP PC4510 PR4521 DY SW DH DL V5 12 11 10 9 GAP-CLOSE-PWR-3-GP PG4521 1 2 SE330U2D5VDM-1GP 1 2 VREF REFIN GSNS VSNS 5 6 7 8 PWR_VCCP_MODE 2 2 2 PU4501 1 H_SNB_IVB#_PWRCTRL 2 3 4 PR4513 DY 0R2J-2-GP 17 16 15 14 13 PR4511 100KR2F-L1-GP G GND PGOOD MODE EN BST 1 1 1 PR4518 DY 8K25R2F-1-GP S S S G PC4515 SCD1U10V2KX-4GP PWR_VCCP_VBST 1 PR4508 PC4520 SCD1U50V3KX-GP 3D3V_S5 EC_SC_1003 PU4502 PC4513 2 PWR_VCCP_LL_1 1 2 2D2R3J-2-GP SCD1U50V3KX-GP PC4517 SC10U25V5KX-GP PWR_VCCP_VREF SIR172DP-T1-GE3-GP 2 0R0402-PAD D D D D 1 PR4502 37,48 1.05VTT_PWRGD PC4516 D Id=20A, Qg=9.8~15nC, Rdson=10.3~12.4 mohm SC10U25V5KX-GP 2 10KR2J-3-GP 1 84.00172.037 1 PR4509 1D05V_VTT PG4520 1 2 GAP-CLOSE-PWR PG4517 1 2 2 PR4505 1 2 1KR2F-3-GP 3D3V_S0 1D05V_PWR PG4519 2 GAP-CLOSE-PWR PG4516 1 2 1 PC4514 SC1U6D3V2KX-GP D PWR_DCBATOUT_VCCP PWR_VCCP_EN 2 2 1 PR4510 0R0402-PAD 46,47 RUNPWROK GAP-CLOSE-PWR-3-GP PG4533 1 2 PWR_VCCP_VSNS 1 TPS51219_GSNS_M PR4519 1 PR4522 2 2 0R0402-PAD 0R0402-PAD VCCIO_SENSE VSSIO_SENSE 8 8 GAP-CLOSE-PWR-3-GP PG4534 1 2 Parallel GAP-CLOSE-PWR-3-GP Differential Sense feedback Resistor need close to controller 3D3V_S5 PG4540 2 PU4504 1D05V_PWR_M MPWROK PG4543 2 1 11 PR4525 RT8068AZQWID-GP-U SBA SBA SBA 1D05V_FB_GAP R1 PR4526 15KR2F-GP SBA PC4526 PC4525 SBA PWR_1D05V_FB 1 PC4524 SC22P50V2GN-GP GAP-CLOSE-PWR PG4544 1 2 PR4527 20KR2F-L-GP R2 2 SBA 1 2 SBA 7 6 1 IND-2D2UH-161-GP-U 1 PC4527 2 0R5J-5-GP Non-SBA GAP-CLOSE-PWR SBA 2 PGOOD 2 R4501 3 1 2 DY 1 1D05V_VTT 1D05V_M PL4502 PWR_1D05V_PHASE 2 FB 2 1 1 LX#3 NC#7 EN 1 2 1 19 2 0R0402-PAD 4 SVIN GND 2 2 3D3V_S5 LX#2 SC10U6D3V3MX-GP DY LX#1 PVIN SC10U6D3V3MX-GP 1 PR4523 PC4523 SC1U6D3V2KX-GP PWR_1D05V_EN 5 PVIN SC100P50V2JN-L-GP PM_SLP_A# SBA 8 100KR2F-L1-GP 19,27 SC10U6D3V3MX-GP B SC10U6D3V3MX-GP SBA 9 PC4522 2 1 2 SBA PC4521 PWR_1D05V_SVIN 1 1 2 GAP-CLOSE-PWR-3-GP PG4547 1 PR4524 2D2R2J-GP 10 1 GAP-CLOSE-PWR PWR_1D05V_PVDD 2 1 GAP-CLOSE-PWR PG4541 1 2 B Vo=0.6*(1+(R1/R2)) A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title TPS51211_1D05V Size Document Number Date: Friday, January 06, 2012 Rev SD 5 4 3 2 Sheet 1 45 of 103 A B C D E SSID = PWR.Plane.Regulator_1p5v0p75v DCBATOUT DCBATOUT_1D5V PG4601 1 2 GAP-CLOSE-PWR-3-GP 1D5V_PWR PG4602 1 2 GAP-CLOSE-PWR-3-GP PG4606 1 2 GAP-CLOSE-PWR-3-GP PR4601 4 PWR_1D5V_VCC5 PG4603 1 2 GAP-CLOSE-PWR-3-GP 5V_S5 2 PC4602 SC1U10V2KX-1GP VDD 4 3 2 1 12 PL4601 PWR_1D5V_VDDQ PWR_1D5V_FB PC4616 SC18P50V2JN-1-GP G DY PC4615 SC330P50V2KX-3GP 2 1 2 1 PC4613 SCD1U50V3KX-GP 1 DY 2 1 2 PT4602 EC4601 SCD1U50V3KX-GP PWR_1D5V_SW_1 PC4621 PG4615 1 2 GAP-CLOSE-PWR-3-GP PG4616 1 2 GAP-CLOSE-PWR-3-GP PG4617 1 2 GAP-CLOSE-PWR-3-GP PG4618 1 2 GAP-CLOSE-PWR-3-GP S 2 2 DY VTTREF PG4619 1 2 GAP-CLOSE-PWR-3-GP RT8207MZQW-GP-U 1 4 4 3 2 1 PR4608 30K9R2F-GP R1 R2 PG4620 1 2 GAP-CLOSE-PWR-3-GP 2 2 PR4609 30KR2F-GP 2 PR4610 0R0402-PAD DDR_VREF_S3 PC4619 SCD033U16V2KX-GP 19,27,97 PM_SLP_S4# Vout=0.75*(1+R1/R2) 1 2 PR4611 0R0402-PAD PWR_1D5V_EN 1 1 DY PC4622 SCD1U10V2KX-5GP 2 2 1PWR_1D5V_VTTREF GND 3 21 GND VTTSNS 5 6 1 FB PU4603 PC4620 1 1 2 1 2 1 2 1 2 VTT Id=40A, Qg=16.8~25.5nC, Rdson=4.9~6.1 mohm COIL-1UH-34-GP-U PR4607 2D2R5F-2-GP 2 14 VTTGND DY 1 PGND D 3 PG4614 1 2 GAP-CLOSE-PWR-3-GP 2 2 PWR_1D5V_LGATE SIR460DP-T1-GE3-GP 0D75V_S0 PG4613 1 2 GAP-CLOSE-PWR-3-GP 1D5V_PWR SCD1U10V2KX-4GP 15 VLDOIN S S S G PC4617 PG4612 1 2 GAP-CLOSE-PWR-3-GP Design Current = 11.69A OCP>19.92A SC4D7U6D3V3KX-GP LGATE 1 D D D D DY SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP 2 PC4618 PG4611 1 2 GAP-CLOSE-PWR-3-GP Cyntec. 1.0uH 7.3*6.6*3 DCR=9~10mohm Idc=11A, Isat=22A PG4626 GAP-CLOSE-PWR-3-GP PHASE PWR_1D5V_PHASE VDDQ 2 PC4623 PG4610 1 2 GAP-CLOSE-PWR-3-GP 2 S3 16 +0D75V_DDR_P 20 PG4608 1 2 GAP-CLOSE-PWR-3-GP S5 84.00460.037 1 2 PWR_1D5V_UGATE 4 PG4609 1 2 GAP-CLOSE-PWR-3-GP SE330U2D5VDM-1GP PC4610 SC10U6D3V3MX-GP S 1 19 1D5V_PWR 17 G 1 0D75V_EN TON PC4608 2PWR_1D5V_VBST_1 1 2 2D2R3J-2-GP SCD1U50V3KX-GP 2 7 UGATE PGOOD 1 PR4605 1 8 PWR_1D5V_VBST 2 9 PWR_1D5V_EN VDDP 13 PWR_1D5V_TON 18 5 6 7 8 620KR3J-GP PU4601 BOOT 1 3 37 CS 2 10 45,47 RUNPWROK PR4606 1 2 11 1 DY DCBATOUT_1D5V S S S G PR4604 10KR2F-2-GP PU4602 Id=20A, Qg=9.8~15nC, Rdson=10.3~12.4 mohm PC4612 SC10U25V5KX-GP 84.00172.037 PC4607 SC1U10V2KX-1GP SIR172DP-T1-GE3-GP 2 D D D D D PWR_1D5V_CS 5V_S5 1 1 2 PR4603 0R0603-PAD PC4611 SC10U25V5KX-GP PWR_1D5V_PVCC5 3D3V_S0 PG4604 1 2 GAP-CLOSE-PWR-3-GP DCBATOUT_1D5V 1 1 2 PC4601 1 5 6 7 8 2 PR4602 9K76R2F-1-GP SC1KP50V2KX-1GP 1 1 2 5D1R2F-GP 1D5V_S3 PG4605 1 2 GAP-CLOSE-PWR-3-GP +0D75V_DDR_P PG4624 1 2 GAP-CLOSE-PWR-3-GP PG4625 1 2 GAP-CLOSE-PWR-3-GP <Core Design> 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title A B C D RT8207M_1D5V_0D75V Size Document Number Date: Friday, January 06, 2012 Rev <Doc> SD Sheet E 46 of 103 5 4 3 2 1 SSID = PWR.Plane.Regulator_1p8v D D 3D3V_S5 RT8068A for 1D8V_S0 PG4712 2 GAP-CLOSE-PW R PG4701 1 2 Design Current=1.1A PU4701 1D8V_PW R 3 7 FB 6 1 GND 11 RT8068AZQW ID-GP-U PR4704 20KR2F-L-GP 2 R1 2 PW R_1D8V_FB 1 1 PC4704 SC22P50V2GN-GP PR4706 10KR2F-2-GP R2 2 2 DY PC4706 PC4708 GAP-CLOSE-PW R PG4705 1 2 GAP-CLOSE-PW R PG4711 1 2 GAP-CLOSE-PW R PC4705 45,46 RUNPW ROK 2 0R0402-PAD 2 19,27,36,37 PM_SLP_S3# C GAP-CLOSE-PW R PG4704 1 2 1D8V_FB_GAP PR4705 100KR2J-1-GP PG4713 2 SC100P50V2JN-3GP 1 PR4702 1 2 LX#3 NC#7 2 IND-2D2UH-46-GP-U 1 1 2 2 1 LX#2 1 PGOOD PL4702 PW R_1D8V_PHASE 2 EN 4 3D3V_S0 1 1 2 1 2 1 SVIN 5 1D8V_S0 1 SC10U6D3V3MX-GP 8 PC4703 SC1U6D3V2KX-GP PW R_1D8V_EN LX#1 SC10U6D3V3MX-GP 2 PC4709 PVIN SCD1U50V3KX-GP DY SC10U6D3V3MX-GP SC10U6D3V3MX-GP PC4707 PC4702 9 2 2 GAP-CLOSE-PW R PVIN GAP-CLOSE-PWR-3-GP PG4714 1 PR4703 2D2R2J-GP 10 PW R_1D8V_SVIN 1 PW R_1D8V_PVDD GAP-CLOSE-PW R PG4703 1 2 1 1 C Vo=0.6*(1+(R1/R2)) B B A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title PWM_1D8V_RT8015B Size Document Number Date: Friday, January 06, 2012 Rev SD 5 4 3 2 Sheet 1 47 of 103 5 4 3 2 1 TPS51461 for VCCSA 3D3V_S0 5V_S5 D 1 D PC4814 2 2 PR4806 1R2F-GP 1 2 PC4816 GAP-CLOSE-PW R PG4809 1 2 GAP-CLOSE-PW R SC2D2U10V3KX-1GP GAP-CLOSE-PW R PG4808 1 2 1 2 PR4808 0R0402-PAD D85V_PW RGD 42 1 PR4812 PW R_VCCSA_VID1 PWR_VCCSA_PGOOD PG4807 1 2 2 PW R_VCCSA_VIN SC1U10V2KX-1GP 5V_S5 2DY 1KR2F-3-GP 1 2 1 2 PR4804 PW R_VCCSA_VID0 PW R_VCCSA_EN PWR_VCCSA_V5DRV VCCSA_SELECT1 9 0R0402-PAD PR4805 VCCSA_SELECT0 9 0R0402-PAD 1 1 1 1 PR4809 4K7R2J-2-GP 2 PR4801 0R0402-PAD 20101130 X02: Follow the standard schematics. 1.05VTT_PW RGD 37,45 2 DY 1 2 1 2 1 2 1 2 1 2 1 1PWR_VCCSA_SNUB 2 DY VID1 VCCSA L 0.9V H 0.8V H L 0.725V H H 0.675V GAP-CLOSE-PW R PG4806 1 2 B GAP-CLOSE-PW R PC4817 SC3300P50V2KX-1GP 1 2 2 1 L L GAP-CLOSE-PW R PG4803 1 2 GAP-CLOSE-PW R PG4805 1 2 PC4818 DY SC560P50V-GP PWR_VCCSA_COMP_1 VID0 PG4801 2 GAP-CLOSE-PW R PG4804 1 2 2 2 1 GAP-CLOSE-PW R PG4802 1 2 2 1 SCD1U50V3KX-GP 1 VCCSA PC4812 PC4806 SCD01U50V2KX-1GP SC22U6D3V5MX-2GP VCCSA_SENSE 9 PC4801 PR4810 0R0402-PAD SC22U6D3V5MX-2GP 2 PC4811 1 SC22U6D3V5MX-2GP PWR_VCCSA_COMP PWR_VCCSA_VREF PW R_VCCSA_SLEW DY PC4810 68.R3510.101 SC22U6D3V5MX-2GP PR4803 DY 2D2R5F-2-GP 1 PR4811 2 0D85V_S0 100R2F-L1-GP-U 20101130 X02: Follow the standard schematics. 0D85V_S0 PL4801 1 2 IND-D35UH-GP PW R_VCCSA_SW PW R_VCCSA_VOUT C TDK. 0.35uH 5*5*3 DCR=3.9mohm Idc=11A, Isat=14.9A 2 74.51461.043 PR4802 4K99R2F-L-GP B 1 SC22U6D3V5MX-2GP GND VREF COMP SLEW VOUT MODE PW R_VCCSA_BST1 PR4807 2 PW R_VCCSA_BST_R 0R2J-2-GP 12 11 10 9 8 7 PC4807 BST SW#11 SW#10 SW#9 SW#8 SW#7 PC4809 PGND PGND PGND VIN VIN VIN GND 1 2 3 4 5 6 1 PC4813 SC4D7U25V5KX-GP SC4D7U25V5KX-GP 2 1 PC4815 2 PC4803 SCD1U50V3KX-GP 2 1 PW R_VCCSA_VIN 19 20 21 22 23 24 25 Design Current = 4.2A OCP> 8.4A PC4805 SCD1U50V3KX-GP 1 PW R_VCCSA_VIN 20101130 X02: Follow the standard schematics. 2 C V5DRV V5FILT PGOOD VID1 VID0 EN 18 17 16 15 14 13 PU4801 PC4804 TPS51461RGER-GP SC1U6D3V2KX-GP PC4802 SCD22U10V2KX-1GP <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 5 4 3 2 VCCSA_TPS51461 Size Document Number Date: Friday, January 06, 2012 Rev <Doc> SD Sheet 1 48 of 103 LVDS connector SSID = VIDEO LCD / Inverter Connector DCBATOUT_LCD 3D3V_S0 LVDS_DDC_DATA_R LVDS_DDC_CLK_R 2 2 C4906 1 C4902 1 2 1 3 4 RN4902 SRN2K2J-1-GP SCD1U50V3KX-GP SC1U25V3KX-1-GP 1 2 1.2A C4916 SCD01U50V2KX-L-GP LVDS1 41 1 CAMERA POWER L_BKLT_CTRL R4928 18 3D3V_S0_CAMERA 18 18 U4902 1 2 3 OUT GND OC# IN EN/EN# 3D3V_S0_CAMERA_IN 5 4 1 R4922 CAMERA_EN 1 C4912 SC4D7U6D3V3KX-GP SY6288CAAC-GP USB_PN12 USB_PP12 1 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 33R2J-2-GP 1 R4926 1 1 R4925 R4924 Pin11 is CAMERA GND BLON_OUT_C LCD_BRIGHTNESS LCD_PRESENCE# USB_CAMERA# USB_CAMERA 2 0R0805-PAD Pin15 is CAMERA shielding GND LID_CLOSE# 27 27,70 LID_CLOSE# C4911 SC4D7U6D3V3KX-GP 3D3V_AUX_S5 2 74.06288.07F 2 1 Layout 40 mil LCD_DET# 3D3V_S0_CAMERA 3D3V_S0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin20 is Hall Sensor GND 17 LVDSA_CLK 17 LVDSA_CLK# 17 LVDSA_DATA2 17 LVDSA_DATA2# Active Active Active Active 17 LVDSA_DATA1 17 LVDSA_DATA1# DCBATOUT_LCD LCDVDD DCBATOUT C4922 SC1U6D3V2KX-GP 2 FUSE-D5A32V-14-GP LCDVDD_R 2 FUSE-3A32V-12-GP 42 C4921 SCD1U10V2KX-5GP JAE-CON40-4-GP 20.K0568.040 1 1 F4901 POLYSW-1D1A24V-GP-U 2nd = 69.50007.A41 Main:69.50007.A41 Second:69.50007.A31 5 1 3D3V_AUX_S5 1 1KR2J-1-GP 2 BLON_OUT_C R4911 1 4 3 LCDVDD_DISCHARGE 5 2 LVDS_VDD_EN 6 1 2N7002KDW-GP 84.2N702.A3F 2nd = 84.DM601.03F For EMI request Close to LVDS connector BLON_OUT 2 LVDS_VDD_EN# 27 C4910 SC100P50V2JN-3GP Q4901 R4929 100KR2J-1-GP 2 R4903 R4930 100R2J-2-GP 1 DY 2 1 2 LCDVDD 100KR2J-1-GP SCD1U16V2KX-3GP 74.05285.07F OBS check 2nd source=74.05285.07F LCDVDD Discharge C4909 1 LVDS_VDD_EN SY6288CAAC-GP 2 C4907 4 2 IN EN/EN# 1 OUT GND OC# SC4D7U6D3V3KX-GP 1 3D3V_DDC_S0 2 LID_CLOSE# U4901 1 2 3 SC4D7U6D3V3KX-GP 2 2 2 Layout 40 mil C4908 1 F4903 1 F4902 1 C4904 SC1KP50V2KX-1GP 3D3V_S0 SCD1U50V3KX-GP 1 C4905 LCDVDD 17 LVDSA_DATA0 17 LVDSA_DATA0# 17 LVDS_DDC_DATA_R 17 LVDS_DDC_CLK_R 3D3V_S0 LCD POWER 1 High High High High 2 SY6288CAAC AP2171WG-7 OBS OBS 1 74.06288.07F 74.02171.07F 74.07534.A7F 74.05240.A7F 2 SILERGY DIODES UPI GMT AFTP4901 Panel BL brightness/Power En/BL En LCD_BRIGHTNESS DY 17 L_BKLT_EN 17 L_BKLT_CTRL 17 LVDS_VDD_EN 1 R4905 2 L_BKLT_CTRL LVDS_VDD_EN 0R0402-PAD 1 1 EC4902 2 1 2 2 DY SC5D6P50V2CN-1GP DY SC5D6P50V2CN-1GP 1 EC4905 SC33P50V2JN-3GP EC4904 PANEL_BLEN 27 C4901 SC100P50V2JN-3GP 2 LVDSA_CLK# LVDSA_CLK <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title LCD Connector Size A2 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 49 of 103 5 4 3 2 1 CRT connector CRT1 1 CRT_R CRT_G CRT_B 2 VCC_CRT 12 15 1 2 3 CRT_VSYNC_CON CRT_HSYNC_CON GND GND GND GND GND GND GND CRT_RED CRT_GREEN CRT_BLUE 14 13 D NC#4 NC#11 DDCDATA_ID1 DDCCLK_ID3 VSYNC HSYNC 4 11 CRT DDCDATA & DDCCLK level shift Pull High 5V Design on CRT Board 5 6 7 8 10 16 17 AFTP5009 1 5V_CRT_S0 5V_S0 3D3V_S0 3D3V_S0_DDC 1 R5003 500mA 2 10KR2J-3-GP D-SUB-15-136-GP 1 CRT_DDCDATA_CON CRT_DDCCLK_CON C5013 SCD01U50V2KX-1GP F5001 FUSE-1D1A6V-4GP-U 20.20961.015 2 3D3V_S0 D D5001 CH551H-30PT-GP 69.50007.691 2nd = 69.50007.771 2 9 1 5V_CRT_S0 83.R5003.C8F 2ND = 83.5R003.08F 3rd = 83.R5003.G8F RN5002 SRN2K2J-1-GP RN5003 SRN10KJ-5-GP 3D3V_S0_DDC 3 4 Q5001 17 CRT_DDC_DATA 4 3 5 2 6 1 CRT_DDCDATA_CON 2 1 5V_CRT_S0 CRT_DDCDATA_CON CRT_DDCCLK_CON CRT_R CRT_G CRT_B CRT_VSYNC_CON CRT_HSYNC_CON 1 1 1 1 1 1 1 1 3 4 2 1 5V_CRT_DDC AFTP5001 AFTP5002 AFTP5003 AFTP5004 AFTP5005 AFTP5006 AFTP5007 AFTP5008 2N7002KDW-GP 17 CRT_DDC_CLK 84.DM601.03F 2nd = 84.2N702.A3F CRT_DDCCLK_CON CRT Hsync & Vsync level shift 1 5V_S0 C5007 SCD1U10V2KX-5GP C 2 C U5001 1 7 4 G1# G2# A1 A2 GND Y1 Y2 VCC 2 5 CRT_VSYNC CRT_HSYNC CRT_VSYNC1_2 CRT_HSYNC1_2 6 3 R5001 R5002 17 17 2 10R2J-2-GP 2 10R2J-2-GP 1 1 5V_CRT_S0 CRT_VSYNC_CON CRT_HSYNC_CON 5V_CRT_S0 8 D5002 TC7WT125FU-GP 73.7W125.007 2nd = 73.2G125.A0B CRT RGB D5006 2 DY 3 CRT_HSYNC_CON 2 DY 3 CRT_RED 1 1 CH221GP-GP-U CH221GP-GP-U 17 L5001 1 2 FCM1608CF-220T05-GP CRT_RED D5003 CRT_R D5007 2 2 68.00245.011 2nd = 68.00230.021 DY 3 CRT_VSYNC_CON DY 3 CRT_GREEN 1 1 17 L5002 1 2 FCM1608CF-220T05-GP CRT_GREEN CH221GP-GP-U CRT_G CH221GP-GP-U D5004 68.00245.011 2nd = 68.00230.021 D5008 2 DY 3 CRT_DDCDATA_CON 2 DY 3 CRT_BLUE 1 CH221GP-GP-U CH221GP-GP-U D5005 B 2 DY 3 CRT_DDCCLK_CON 1 CH221GP-GP-U 1 DY 2 1 1 2 DY SC100P50V2JN-3GP DY CRT_DDCDATA_CON CRT_HSYNC_CON CRT_VSYNC_CON CRT_DDCCLK_CON C5011 C5010 SC18P50V2JN-1-GP 2 C5009 SC18P50V2JN-1-GP DY SC100P50V2JN-3GP 1 C5008 2 1 1 1 CRT_B C5006 2 2 1 1 2 2 1 2 1 2 3 4 C5005 SC10P50V2JN-4GP 68.00245.011 2nd = 68.00230.021 C5004 SC10P50V2JN-4GP DY L5003 1 2 FCM1608CF-220T05-GP SC10P50V2JN-4GP SRN150F-1-GP DY C5003 SC8P250V2CC-GP DY SC8P250V2CC-GP RN5001 SC8P250V2CC-GP B C5002 1 C5001 2 CRT_BLUE 8 7 6 5 17 A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CRT Connector 5 4 3 2 Size A2 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 50 of 103 5 4 3 2 1 SSID = VIDEO HDMI Passive Level Shifter Close to HDMI Connector HDMI CONNECTOR HDMI1 17 HDMI_CLK_R# 17 HDMI_CLK_R C5103 C5104 1 1 2 2 SCD1U10V2KX-5GP SCD1U10V2KX-5GP HDMI_CLK_R_C1# HDMI_CLK_R_C1 C5105 C5106 1 1 2 2 SCD1U10V2KX-5GP SCD1U10V2KX-5GP HDMI_DATA0_R_C1# HDMI_DATA0_R_C1 C5110 C5107 1 1 2 2 SCD1U10V2KX-5GP SCD1U10V2KX-5GP HDMI_DATA1_R_C1# HDMI_DATA1_R_C1 C5108 C5109 1 1 2 2 SCD1U10V2KX-5GP SCD1U10V2KX-5GP HDMI_DATA2_R_C1# HDMI_DATA2_R_C1 20 D CHASSIS HDMI_DATA2_R_C 1 17 HDMI_DATA0_R# 17 HDMI_DATA0_R 17 HDMI_DATA1_R# 17 HDMI_DATA1_R 17 HDMI_DATA2_R# 17 HDMI_DATA2_R 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 5 6 7 8 8 7 6 5 Close to HDMI Connector 4 3 2 1 RN5102 SRN680-U-GP 1 2 3 4 RN5101 SRN680-U-GP HDMI_PLL_GND 21 HDMI_DATA1_R_C# HDMI_DATA0_R_C HDMI_DATA0_R_C# HDMI_CLK_R_C HDMI_CLK_R_C# HDMI_PIN13 83.R5003.C8F 3rd = 83.R5003.G8F 2ND = 83.5R003.08F DDC_CLK_HDMI DDC_DATA_HDMI CH551H-30PT-GP F5101 5V_HDMI HPD_HDMI_CON 2 C5102 AFTP5121 1 SKT-HDMI21-1-GP-U D 2 22.10296.571 Q5103 2N7002K-2-GP SCD1U10V2KX-5GP CHASSIS HDMI_DATA2_R_C# HDMI_DATA1_R_C 1 D 5V_HDMI_S0 1 2 1 FUSE-1D1A6V-4GP-U 5V_S0 D5101 69.50007.691 2nd = 69.50007.771 DY 1 R5113 2 0R2J-2-GP S 1 G 84.2N702.J31 2ND = 84.2N702.J31 3D3V_S0 R5104 100KR2J-1-GP C C 2 DY ESD Request EMI's request HDMI_CLK_R_C1# HDMI_PIN13 R5114 0R2J-2-GP 1 2 HDMI_CLK_R_C# HDMI_DATA1_R_C1# R5118 0R2J-2-GP 1 2 HPD_HDMI_CON HDMI_DATA1_R_C# DDC_DATA_HDMI HDMI_DATA0_R_C1# R5116 0R2J-2-GP 1 2 HDMI_DATA0_R_C# HDMI_DATA1_R_C1 HDMI_DATA1_R_C HDMI_DATA2_R_C1# R5120 0R2J-2-GP 1 2 HDMI_DATA2_R_C# DY DY 1 1 1 D5107 D5108 2 D5106 2 2 PESD5V0U1BL-GP-U1 HDMI_CLK_R_C R5119 0R2J-2-GP 1 2 D5105 2 DY PESD5V0U1BL-GP-U1 B HDMI_CLK_R_C1 R5115 0R2J-2-GP 1 2 HDMI_DATA2_R_C# 180R2F-1-GP HDMI_DATA1_R_C# 180R2F-1-GP HDMI_DATA0_R_C# 180R2F-1-GP 2 HDMI_CLK_R_C# 180R2F-1-GP 2 DY PESD5V0U1BL-GP-U1 HDMI_CLK_R_C 1 R5107 1 R5108 1 R5109 1 R5110 PESD5V0U1BL-GP-U1 HDMI_DATA0_R_C 2 HDMI_DATA1_R_C 2 HDMI_DATA2_R_C 1 DDC_CLK_HDMI B HDMI DDC Passive Level Shifter D5102 BAW56-5-GP HDMI_DATA0_R_C1 R5117 0R2J-2-GP 1 2 HDMI_DATA0_R_C HDMI_DATA2_R_C1 R5121 0R2J-2-GP 1 2 83.00056.Q11 2nd = 83.00056.K11 HDMI_DATA2_R_C 1 3 5V_S0 2 5V_HDMI_S0_2 5V_HDMI_S0_1 1 3D3V_S0 R5101 1MR2F-GP RN5103 SRN2K2J-1-GP HPD_HDMI_CON A 1 S 17 HDMI_PCH_DET 2N7002K-2-GP Q5104 R5106 100KR2J-1-GP 17 PCH_HDMI_DATA 2 84.2N702.J31 2ND = 84.2N702.031 DG: 20K PD 1 2 2 3D3V_S0 D A 4 3 DG: 2.2K PU Q5102 G 1 6 2 5 3 4 2N7002KDW-GP 17 PCH_HDMI_CLK DDC_DATA_HDMI <Core Design> Wistron Corporation DDC_CLK_HDMI 84.2N702.A3F 2nd = 84.DM601.03F 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title HDMI Level Shifter/Connector 5 4 3 2 Size A2 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 51 of 103 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title eDP Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 52 of 1 103 A 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title S-VIDEO Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 53 of 1 103 A 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Reserved Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 54 of 1 103 A 5 4 3 2 1 SSID = User.Interface ITP Connector D D H_CPURST# use pull-up Resistor close ITP connector 500 mil ( max ), others place near CPU side. C C CPU ITP Connector TCK(PIN 5) TCK(PIN AC5) FBO(PIN 11) B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ITP Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 55 of 1 103 A 5 4 3 2 1 SATA HDD Connector HDD1 D 21 21 SCD01U50V2KX-1GP SCD01U50V2KX-1GP SATA_TXP1 SATA_TXN1 SCD01U50V2KX-1GP SCD01U50V2KX-1GP 21 SATA_RXN1 21 SATA_RXP1 1 C5614 1 C5613 SATA_TXP1_C SATA_TXN1_C 1 1 2 C5616 2 C5615 SATA_RXN1_C SATA_RXP1_C 3D3V_S0_HDD 2 27 HDD_DET# 5V_S0_HDD 2 C5606 SCD1U10V2KX-5GP SC10U10V5KX-2GP 1 C5605 2 1 R5606 0R0805-PAD 1 5V_S0 2 2 DY SCD1U10V2KX-5GP SC10U6D3V5KX-1GP DY D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 C5601 1 C5604 2 1 R5603 0R0805-PAD 1 3D3V_S0 2 2 24 NP2 22 21 20 19 18 17 16 FFS_INT2 TP5607 1 FFS_INT2 1 NP1 23 SKT-SATA22P-27-GP-U1 62.10065.471 C C ODD Connector 21 21 SATA_TXN4 SATA_TXP4 SCD01U50V2KX-1GP SCD01U50V2KX-1GP 2 2 1 C5611 1 C5612 SATA_TXN4_C SATA_TXP4_C 21 21 SATA_RXN4 SATA_RXP4 SCD01U50V2KX-1GP SCD01U50V2KX-1GP 2 2 1 C5607 1 C5608 SATA_RXN4_C SATA_RXP4_C DY 1 SATA_ODD_DA# 18,27 R5602 0R2J-2-GP R5604 10KR2J-3-GP DY 2 Mars: Exchange ODD and ESATA differential pair each other. SATA_ODD_DA#_C 2 SATA_ODD_PRSNT# 22 1 SATA_RX- and SATA_RX+ Trace Length match within 20 mil SATA Zero Power ODD SATA_RXN4_C SATA_RXP4_C +5V +5V S3 S2 AA+ NP1 NP2 BB+ P4 P1 GND GND GND GND GND GND GND S1 S4 S7 P5 P6 14 15 SATA_ODD_DA#_C SATA_ODD_PRSNT# 5V_S0 When the drive is powered on, the FET to the MD/DA pin drive is OFF. When the drive is powered off, the FET to the MD/DA pin is ON C5609 1 R5607 0R0805-PAD 2 4 3 2 1 ODD_PW R_5V_IN EN2# EN1# IN GND OC2# OUT2 OUT1 OC1# GND 5 6 7 8 9 ODD_PW R_5V 100 mil C5610 SC10U6D3V5KX-1GP NP1 NP2 5V_S0 SKT-SATA7P-6P-59-GP-U 1 22.10300.B91 B ODD_PW R_5V U5601 TPS2064DGNR-GP-U 22 SATA_ODD_PW RGT SC10U6D3V5KX-1GP S5 S6 MD DP 1 SATA_TXN4_C SATA_TXP4_C P2 P3 Current limit Active High typ =>2A TI TPS2069DGNR MSOP 8P UPI UP7534PRA8-15 MSOP 8P GMT G547F1P81U MSOP 8P (OBS) UPI UP7534ARA8-15 MSOP8P 2 B 74.02069.079 74.07534.D79 74.00547.C79 74.07534.A79 1 ODD1 2 ODD_PW R_5V 2 R5605 100KR2J-1-GP DY TI DIODES UPI 74.02069.079 TPS2069DGNR AP2171WG-7 74.07534.A7F OBS High Active High Active High Active A <Core Design> 4 5 6 2 2 10KR2J-3-GP 10KR2J-3-GP 2 1 1 1 SATA_ODD_PW RGT SATA_ODD_DA# R5608 R5609 3 ODD_PWRGT# 3D3V_S0 A SATA_ODD_DA#_C Q5601 2N7002KDW -GP Wistron Corporation 84.2N702.A3F 2nd = 84.DM601.03F 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. SUPPORT ZERO SATA ODD Title HDD/ODD SATA_ODD_PW RGT SATA_ODD_DA# Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 56 of 103 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title E-SATA+USB Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 57 of 1 103 A 5 4 3 2 Int. Digital MIC for V series 1 3D3V_S0 MIC1 6 AUD_DMIC_CLK_L AUD_DMIC_DATA_L V Series-MIC 1 C5806 DY DY MLVG0402220NV09BP-GP MLVG0402220NV09BP-GP 2 C5805 CHECK PIN DEFINE AFTP5809 AFTP5810 1 1 AUD_DMIC_CLK_L AUD_DMIC_DATA_L AFTP5805 AFTP5806 1 1 3D3V_S0 GND 5 ACES-CON4-17-GP-U1 2 C5804 1 1 V Series-MIC 2 D 1 V Series-MIC AUD_DMIC_CLK_L AUD_DMIC_DATA_L 2 2 SC1KP50V2KX-1GP L5801 SBY100505T-601Y-N-GP 1 1 L5802 SBY100505T-601Y-N-GP 29 AUD_DMIC_CLK 29 AUD_DMIC_DATA 4 3 2 20.F1621.004 D ME change P/N at SIT Old 20.F1639.004 New 20.F1621.004 INTERNAL STEREO SPEAKERS Int. Mono Analog MIC for B series 29 AUD_SPK_L+ 2 SPK1 B Series-MIC DY C AU_GND AU_GND 2 4 AFTP5807 2 AUD_DMIC_DATA_L 0R2J-2-GP 1 R5812 DY B Series-MIC 1 ACES-CON2-17-GP 20.F1621.002 Only needed if speaker connector is physically far from audio codec. When in doubt, it's always a good idea to have population option. 2 D5801 AU_GND SPK2 3 1 Place these EMI components close to speaker connector. C AFTP5808 2 4 1 29 AUD_SPK_R+ ACES-CON2-17-GP 20.F1621.002 29 AUD_SPK_R- EC5804 SC47P50V2JN-3GP 2 EC5803 SC47P50V2JN-3GP AFTP5801 AFTP5802 AFTP5803 AFTP5804 1 1 1 1 AUD_SPK_L+ AUD_SPK_LAUD_SPK_R+ AUD_SPK_R- 1 2 0R2J-2-GP MLVG0402220NV05BP-GP-U 1 1 R5813 2 C5807 SC100P50V2JN-3GP 3 1 CHECK PIN DEFINE, RIGHT? LEFT? 2 1KR2J-1-GP B Series-MIC EC5802 SC47P50V2JN-3GP 2 AUD_MIC2 AUD_DMIC_CLK_L 2 1 29 1 R5808 1 EC5801 SC47P50V2JN-3GP B Series-MIC 2 29 AUD_SPK_L- 2K2R2J-2-GP 1 1 R5811 1 29 AUD_MIC2_VREFO Table 58.1 - Bi-direction ESD multi-source Supplier Description ROHM RSB5.6SMT2R N/A 83.RSB56.BAF ON SEMI ESD5B5.0ST1G N/A 83.ESD5B.0AF NXP PESD5V0S1BB N/A 83.0005V.0AF Lenovo P/N Wistron P/N B B A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Audio Jack 5 4 3 2 Size A2 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 58 of 103 5 4 FOR CO-LAY 3 2 1 TVS 83.00005.BAE DIODE ARR SRV05-4.TCT SOT-23-6 GIGA Lan Transformer XF5901 D 31 C5903 SCD01U50V2KX-1GP 23 RJ45_7 24 MCT2 22 RJ45_8 31 MDI3- 3 31 MDI2+ 5 2 1 XRF_TDC C5901 value modify to 0.01uF ~ 0.4uF capacitor 1CT:1CT 1 2 MDI3+ 1CT:1CT 20 RJ45_4 4 21 MCT1 19 RJ45_5 17 RJ45_3 31 MDI2- 6 31 MDI1+ 8 D5901 RJ45_6 18 MCT4 16 RJ45_6 14 RJ45_1 10 15 MCT3 12 13 RJ45_2 9 MDI1- 31 Swap for V480 DY 1CT:1CT 7 31 D 83.09904.AAE DIODE ESD AZC099-04S SOT23-6L 11 MDI0+ 1CT:1CT MDI0- 3 5 2 RJ45_2 RJ45_1 1 RJ45_3 31 4 SRV05-4-2-GP 6 XFORM-24P-19-GP C 68.IH601.301 2ND = 68.89240.30D D5902 RJ45_4 1st 68.IH601.301(Taimag) 68.HH035.301(Taimag) 2nd 68.2413S.30A(Lankom) 68.H6441.301(Lankom) C DY for for 4 SRV05-4-2-GP 3 5 2 RJ45_7 1000 10/100 for 1000 for 10/100 RJ45_8 1 RJ45_5 6 MCT2 MCT1 MCT4 MCT3 8 7 6 5 LAN Connector RN5902 SRN75J-1-GP 1 2 3 4 3D3V_LAN_S5 RJ45 1 11 12 14 2 1 13 RJ45-8P-91-GP 2 EC5901 SCD1U50V3KX-GP 1 RJ45_1 SPEED_100#_1 GREEN 2 330R2J-3-GP C5904 SC1KP2KV6KX-GP CHASSIS CHASSIS 1 R5904 B 15 YELLOW 31 SPEED_100# LAN_ACT_LED#_1 2 330R2J-3-GP RJ45_8 RJ45_7 RJ45_6 RJ45_5 RJ45_4 RJ45_3 RJ45_2 MCT_R 31 LAN_ACT_LED# 1 R5903 16 10 9 8 7 6 5 4 3 2 CHASSIS CHASSIS B 22.10277.U11 close to RJ45 <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title RJ45 / Transformer 5 4 3 2 Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 59 of 103 5 4 3 2 1 SSID = Flash.ROM SPI FLASH ROM (8M byte) for PCH D D 3D3V_SPI 3D3V_SPI 2 1 3D3V_SPI 3D3V_SPI 1 1 2 3 4 DY SCD1U10V2KX-5GP SC10U6D3V5KX-1GP R6004 4K7R2J-2-GP C6002 2 1 C6001 RN6001 SRN4K7J-8-GP 2 3D3V_S5 1 2 R6010 0R0402-PAD the same page 23 VCCSPI power U6001 EC6002 SC4D7P50V2CN-1GP DY 9 8 7 6 5 SPI_HOLD_0# SPI_CLK_R_1 SPI_SI_R_1 2 LILY-BIOS-COLAY-GP-U EC6003 SC4D7P50V2CN-1GP C 1 R6006 1 R6007 2 233R2J-2-GP 33R2J-2-GP SPI_CLK_R 21,27 SPI_SI_R 21,27 1 GND VCC HOLD# C DQ0 DY DY 2 S# DQ1 W#/VPP VSS 1 1 2 3 4 SPI_SO SPI_W P# 2 1 1 R6001 33R2J-2-GP 2 21,27 SPI_CS0#_R 21,27 SPI_SO_R EC6001 SC4D7P50V2CN-1GP C 3D3V_SPI 4MB 1 Marcronix MX25L3206EM2I-12G 72.25320.C01 72.25Q32.A01 Winbond W25Q032BVSSIG SO8 R6005 4K7R2J-2-GP SBA DY 9 8 7 6 5 LILY-BIOS-COLAY-GP-U EC6005 SC4D7P50V2CN-1GP SBA N25Q032A13ESE40 72.25032.H01 Marcronix MX25L6406EM2I-12G 72.25640.D01 72.25Q64.B01 Winbond W25Q064CVSSIG SBA SPI_HOLD_0# SPI_CLK_R_2 SPI_SI_R_2 1 R6008 1 R6009 DY DY 2 233R2J-2-GP 33R2J-2-GP SO8 SPI_CLK_R 21,27 SPI_SI_R 21,27 Numonyx SBA 1 GND VCC HOLD# C DQ0 2 EC6004 SC4D7P50V2CN-1GP S# DQ1 W#/VPP VSS 1 SBA 1 2 3 4 SPI_SO1 SPI_W P# 2 1 1 R6003 33R2J-2-GP 2 21 SPI_CS1#_R 21,27 SPI_SO_R 2 2 Numonyx 8MB 3D3V_SPI U6002 N25Q064A13ESE40 72.25Q64.D01 16MB EC6006 SC4D7P50V2CN-1GP Marcronix MX25L12836EZNI-10G 72.25128.X01 B B MX25L12835EZNI-10G 72.25128.Y01 WSON Winbond W25Q128BVEIG 72.25128.I01 Numonyx N25Q128A13EF840 72.25128.B03 SSID = RBATT R6012 0R2J-2-GP 1 DY 2 RTC_AUX_S5 3D3V_AUX_S5 +RTC_VCC Q6002 Q6001 RTC_PW R G 2 RTC_PW R 1 R6002 2 1KR2J-1-GP 83.R0304.B81 2nd = 83.00040.E81 +RTC_VCC R6011 10MR2J-L-GP 3 1 2 4 Width=20mils RTC_DET# 20 S 2N7002K-2-GP 1 2 A 1 CH715FPT-GP 1 C6003 SC1U6D3V2KX-GP D 2 RTC14 3 <Core Design> ACES-CON2-11-GP A 20.F0772.002 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. AFTP6002 AFTP6001 5 4 1 1 Title +RTC_VCC GND Flash/RTC 3 2 Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 60 of 103 5 4 3 2 1 USB Board CONN. D D Support 2A 5V_S5 5V_USB4_S3 U6102 at least 80 mil 1 27,62,82 USB_PW R_EN_R SCD1U10V2KX-5GP DY 4 IN EN/EN# 1 2 3 OUT GND OC# at least 80 mil USB_OC#2_3 18 SY6288CAAC-GP 2 C6103 5 74.06288.07F Place U6102 close to USBCN1 C C B B <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title USB Connector 5 4 3 2 Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 61 of 103 5 4 3 USB3.0 Port1 2 USB3.0 Port2 5V_S5 USB3.0 Port4 USB3.0 Port3 2A 1 U6201 USB_PWR_EN_R 2 SCD1U10V2KX-5GP 1 C6205 27,61,82 D 1 2 3 4 GND IN EN1# EN2# GND OC1# OUT1 OUT2 OC2# 9 8 7 6 5 USB_OC#0_1 at least 80 mil 18 5V_USB1_S3 5V_USB2_S3 USB_OC#4_5 18 TPS2064DGNR-GP-U D 5V_USB1_S3 5V_USB2_S3 2 3 2 10 11 12 13 DD+ STDA_SSTXSTDA_SSTX+ 5 6 USB3_RX1_N_R USB3_RX1_P_R 8 9 USB3_TX1_N_R USB3_TX1_P_R 10 11 12 13 GND GND_DRAIN USB2 1 USB_PN3_R USB_PP3_R 2 3 TC6202 4 7 SKT-USB13-77-GP SE220U6D3VM-30-GP SE220U6D3VM-30-GP TC6201 STDA_SSRXSTDA_SSRX+ 2 1 USB_PN1_R USB_PP1_R VBUS 1 USB1 1 10 11 12 13 STDA_SSRXSTDA_SSRX+ DD+ STDA_SSTXSTDA_SSTX+ 10 11 12 13 5 6 USB3_RX3_N_R USB3_RX3_P_R 8 9 USB3_TX3_N_R USB3_TX3_P_R D6204 USB3_RX1_N_R USB3_RX1_P_R USB3_TX1_N_R USB3_TX1_P_R 4 7 GND GND_DRAIN 1 2 G1 3 4 L1#1L1#8 L2#2L2#7 GNDGND L3#3L3#6 L4#4L4#5 8 7 G2 6 5 USB3_RX1_N_R USB3_RX1_P_R USB3_TX1_N_R USB3_TX1_P_R RCLAMP0524P-GP SKT-USB13-77-GP TC6202 place near the USB2 connector 22.10339.K61 VBUS 22.10339.K61 1st = 83.3V3U4.0A0 TC6201 place near the USB1 connector R6201 18 USB3_TX1_P 1 C6206 2 USB3_TX1_P_C SCD1U16V2KX-3GP 1 R6207 2 0R0402-PAD USB3_TX1_P_R 1 C6209 18 USB3_TX3_P 2 USB3_TX3_P_C SCD1U16V2KX-3GP 1 2 0R0402-PAD D6201 USB3_TX3_P_R USB3_RX3_N_R USB3_RX3_P_R USB3_TX3_N_R USB3_TX3_P_R 1 2 G1 3 4 L1#1L1#8 L2#2L2#7 GNDGND L3#3L3#6 L4#4L4#5 8 7 G2 6 5 USB3_RX3_N_R USB3_RX3_P_R USB3_TX3_N_R USB3_TX3_P_R RCLAMP0524P-GP 1st = 83.3V3U4.0A0 C C R6202 18 USB3_TX1_N 1 C6208 2 USB3_TX1_N_C SCD1U16V2KX-3GP 1 USB3_RX1_P 1 USB3_RX1_N 1 R6208 2 0R0402-PAD USB3_TX1_N_R 1 C6210 18 USB3_TX3_N 2 USB3_TX3_N_C SCD1U16V2KX-3GP 1 R6203 18 USB3_RX1_P 1 18 USB3_RX3_P USB3_RX3_P_R 2 0R0402-PAD R6209 2 0R0402-PAD USB3_RX1_N_R 1 18 USB3_RX3_N 2 0R0402-PAD 5V_USB1_S3 B 1 USB3_RX3_N_R 5V_USB2_S3 B 4 1 4 D6202 PRTR5V0U2X-GP D6203 PRTR5V0U2X-GP DY USB_PP1_R USB3_TX3_N_R R6210 USB3_RX1_P_R 2 0R0402-PAD R6204 18 USB3_RX1_N 2 0R0402-PAD 2 3 DY USB_PN1_R USB_PP3_R 2 3 USB_PN3_R R6205 18 1 USB_PN1 2 0R0402-PAD USB_PN1_R R6211 18 USB_PN3 1 18 USB_PP3 1 2 0R0402-PAD USB_PN3_R R6206 18 1 USB_PP1 2 0R0402-PAD USB_PP1_R R6212 2 0R0402-PAD USB_PP3_R A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title USB 3.0 Port*2 5 4 3 2 Size A2 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 62 of 103 5 4 3 2 1 SSID = User.Interface D D Bluetooth conn. 3D3V_BT_S0 3D3V_S0 U6301 DY 2 IN 5 EN/EN# 4 3D3V_BT_IN 1 2 R6301 0R0805-PAD BLUETOOTH_EN 27,65 SY6288CAAC-GP 2 EC6302 SCD1U16V2KX-3GP OUT GND OC# 1 1 1 2 3 74.06288.07F DY C SILERGY DIODES UPI GMT BT Module pin definition is same as LA470 BT1 AFTP6302 AFTP6303 AFTP6304 7 B 1 2 3 4 5 6 3D3V_BT_S0 BT_LED AFTP6305 AFTP6306 DY C 74.06288.07F 74.02171.07F 74.07534.A7F 74.05240.A7F 1 1 1 1 1 C6302 SC4D7U6D3V3KX-GP SY6288CAAC AP2171WG-7 OBS OBS High High High High Active Active Active Active 3D3V_BT_S0 USB_PP4 USB_PN4 BT_LED GND B USB_PN4 18 USB_PP4 18 8 ACES-CON6-42-GP 20.F1705.006 DY <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Bluetooth Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 63 of 1 103 A 5 4 3 2 1 Finger Printer Connector D D 3D3V_S0 3V_FP_S0 1 2 C6401 SCD1U10V2KX-4GP FPCN1 7 2 1 R6403 0R0805-PAD C C 1 18 18 USB_PP10 USB_PN10 1 R6401 1 R6402 Biometric_USBPP Biometric_USBPN 1 AFTP6401 2 2 0R0402-PAD 0R0402-PAD 2 3 4 5 6 8 ACES-CON6-13-GP 20.K0320.006 AFTP6402 AFTP6403 AFTP6404 3V_FP_S0 Biometric_USBPN Biometric_USBPP 1 1 1 B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Finger Printer Connector Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 64 of 1 103 A 5 4 3 2 1 SSID = Wireless Mini Card Connector(802.11a/b/g/n) D D 1D5V_S0 3D3V_S0 Place near MINI Card CONN 1 1 R6512 0R5J-5-GP 0R0805-PAD R6516 +3V_MINI_W LAN 20 CLK_PCIE_W LAN# 20 CLK_PCIE_W LAN 27 27 1 R6501 1 R6502 E51_RXD E51_TXD C 2 2 0R0402-PAD 0R0402-PAD 20 20 PCIE_RXN2 PCIE_RXP2 20 20 PCIE_TXN2 PCIE_TXP2 +3V_MINI_W LAN E51_RXD_R E51_TXD_R +3V_MINI_W LAN 5V_S5 DY 1 R6503 +5V_MINI_DEBUG 2 0R3J-0-U-GP 1 R6519 2 0R2J-2-GP 3 5 7 9 11 13 15 4 6 8 10 12 14 16 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 NP2 WIFI_RF_EN 27 1 +1D5V_MINI_W LAN PLT_RST# 5,18,27,31,36,66,71,80,82,83,97 +3V_MINI_W LAN PLT_RST#_W LAN 1 R6510 C6504 SCD1U16V2KX-3GP 2 2 LPC_AD0_C LPC_AD1_C LPC_AD2_C LPC_AD3_C LPC_FRAME#_C C6503 SC10U6D3V5KX-1GP 2 0R0402-PAD C6505 SC10U6D3V5KX-1GP C6506 SCD1U16V2KX-3GP 1 0R2J-2-GP C6502 SCD1U16V2KX-3GP C6507 SCD1U16V2KX-3GP C 2 R6513 1 +3V_MINI_W LAN 1 BT_ENABLE 2 NP1 2 PCH_SMBCLK 14,15,20,66 PCH_SMBDATA 14,15,20,66 USB_PN11 18 USB_PP11 18 5V_S5 WLAN_LED# CLK_PCI_LPC_C 1 TP6501 1 27,63 BLUETOOTH_EN 20 PCIE_CLK_W LAN_REQ# PCIE_W AKE#_1 C6501 SCD1U16V2KX-3GP 2 DY 1 2 2 0R2J-2-GP 0R2J-2-GP 1 1 1 2 R6520 R6511 2 W LAN1 53 27 PCIE_W LAN_W AKE# 19,31,66 PCIE_W AKE# 1 2 AOAC-DY 1 2 +1D5V_MINI_W LAN 2 R6521 10KR2J-3-GP 2 3D3V_S5 +3V_MINI_W LAN 1 +1D5V_MINI_W LAN 54 BLUETOOTH_EN TYCO-CONN52A-2-GP 20.F1743.052 B Reserve for AOAC B 8 7 6 LPC_AD1_C G6502 1 LPC_AD2_C G6503 1 LPC_AD3_C G6504 1 LPC_FRAME#_C G6505 1 2 GAP-OPEN 2 GAP-OPEN 2 GAP-OPEN 2 GAP-OPEN 2 GAP-OPEN LPC_AD0 21,27,71 LPC_AD1 21,27,71 LPC_AD2 21,27,71 LPC_AD3 21,27,71 LPC_FRAME# 21,27,71 AOAC G6506~G6511 placememt close close WLAN1 in bottom side 1 2 R6515 4 C6508 G6501 1 U6501 TPCF8105-GP AOAC 3 AOAC 5 +3V_MINI_W LAN 100KR2J-1-GP 2 1 SCD1U10V2KX-5GP 2 1 3D3V_S5 LPC_AD0_C R6518 10KR2J-3-GP AOAC B AOAC_EN R2 PDTC115EE-1-GP C E AOAC AOAC_EN_1 DY R6517 10KR2J-3-GP <Core Design> CLK_PCI_LPC_C G6511 1 2 27 R1 2 Q6502 A 1 1 AOAC_EN_2 2 GAP-OPEN CLK_PCI_LPC A 18,71 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 84.00115.C1K 2nd = 84.09115.011 3rd = 84.00015.01H Title MINICARD(WLAN)/ITP CONN 5 4 3 2 Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 65 of 103 5 4 3 2 1 SSID = Wireless mSATA for V Series Only D D Mini Card Connector(Full Card) Place near MINI Card CONN +3V_MINI_W W AN +1D5V_MINI_W W AN 19,31,65 PCIE_W AKE# DY 2 0R2J-2-GP C6608 1 1 2 1 1 R6604 +3V_MINI_W W AN 21 21 SATA_RXP0 SATA_RXN0 C6611 1 C6612 1 2SCD01U50V2KX-1GP 2SCD01U50V2KX-1GP SATA_RXP0_C SATA_RXN0_C 21 21 SATA_TXN0 SATA_TXP0 C6614 1 C6620 1 2SCD01U50V2KX-1GP 2SCD01U50V2KX-1GP SATA_TXN0_C SATA_TXP0_C +3V_MINI_W W AN C6610 2 1 2 2 +1D5V_MINI_W W AN SC33P50V2JN-3GP SCD047U16V2KX-1-GP B 0R0805-PAD R6606 WLAN2 +1D5V_MINI_W W AN C6609 1 1 0R0805-PAD R6607 SCD1U16V2KX-3GP 2 C6607 SC33P50V2JN-3GP SCD047U16V2KX-1-GP 1 C6606 3D3V_S0 53 2 +1D5V_MINI_W W AN +3V_MINI_W W AN 2 1 2 1 2 1 1 2 DY Place near Pin 24 C 1D5V_S0 C6604 SC33P50V2JN-3GP 2 C6603 SC33P50V2JN-3GP 1 C6602 SCD047U16V2KX-1-GP SCD047U16V2KX-1-GP 2 C6601 SC4D7U6D3V3KX-GP 2 C6619 SC4D7U6D3V3KX-GP 1 C6618 27 -MSATA_DET +3V_MINI_W W AN 1 2 R6608 0R0402-PAD 1 NP1 2 3 5 7 9 11 13 15 4 6 8 10 12 14 16 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 NP2 +3V_MINI_W W AN C PLT_RST#_W AN 1 +3V_MINI_W W AN PCH_SMBCLK PCH_SMBDATA R6603 R6601 1 PLT_RST# 5,18,27,31,36,65,71,80,82,83,97 PCH_SMBCLK 14,15,20,65 PCH_SMBDATA 14,15,20,65 USB_P8USB_P8+ 3G_LED# 2 R6605 0R0402-PAD 1 1 DY DY 2 0R3J-0-U-GP 2 0R3J-0-U-GP USB_PN8 18 USB_PP8 18 TP6602 54 B TYCO-CONN52A-2-GP 20.F1743.052 <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title WWAN Connector 5 4 3 2 Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 66 of 103 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Reserved Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 67 of 1 103 A 5 4 3 2 1 SSID = User.Interface R6824 1 DY 2 0R2J-2-GP LEDCN1 10 Q6810 R2 SATA_LED#_Q E C PDTA143ET-GP EC6808 2 84.00143.M11 2nd = 84.02143.011 8 7 6 5 4 3 2 3D3V_S0 NUM_LED_Q CAP_LED_Q SATA_LED#_Q APS_LED#_Q 1 B SATA_LED# R1 D 21 R6813 R6812 R6810 R6818 NUM_LED_R 2 2 470R2J-2-GP CAP_LED_R 2 470R2J-2-GP SATA_LED#_R 2 100R2J-2-GP APS_LED#_R 470R2J-2-GP 1 1 1 1 D V Series-APS 6 1 2N7002KDW -GP 1 V Series-APS 9 DY ACES-CON8-15-GP 2 1 C6813 2 1 2 2 CAP_LED 27 EC6809 SCD1U16V2KX-3GP 2 SC1KP50V2KX-1GP 5 SC1KP50V2KX-1GP NUM_LED NUM_LED_Q SC1KP50V2KX-1GP SC1KP50V2KX-1GP 27 3 2 EC6806 EC6811 EC6807 Q6802 4 1 1 1 SC1KP50V2KX-1GP 20.K0315.008 1 AFTP6808 CAP_LED_Q 1 3D3V_S0 1 1 1 1 NUM_LED_R CAP_LED_R SATA_LED#_R APS_LED#_R AFTP6801 AFTP6803 AFTP6804 AFTP6805 AFTP6806 Q6801 C 21 APS_LED 1 APS_LED#_Q 3 R1 C 2 R2 LTC043ZUB-FS8-GP 84.00043.011 CHARGER LED Q6804 27 DC_BATFULL LED2 4 3 5 2 6 1 DC_BATFULL#_Q GREEN DC_BATFULL#_Q CHARGE_LED 27 2 3 CHARGE_LED#_R 1 R6802 2 3D3V_S5 100R2J-2-GP Yellow CHARGE_LED#_Q 1 2N7002KDW -GP CHARGE_LED#_Q LED-GY-8-GP-U 83.00326.070 B 1 B 1 G6801 AFTP6814 GAP-OPEN 1 BTNCN1 2 AFTP6813 7 1 8 EC6805 1 3D3V_S5 KBC_PW RBTN#_R 2 KBC_NOVO_BTN#_R 3 PW RLED 4 5 6 3D3V_S5 PW RLED KBC_NOVO_BTN#_R KBC_PW RBTN#_R ACES-CON6-22-GP-U 20.K0487.006 <Core Design> 2 2 2 2100R2J-2-GP 100R2J-2-GP SC1KP50V2KX-1GP SC1KP50V2KX-1GP SC1KP50V2KX-1GP SC1KP50V2KX-1GP A 2 EC6801 EC6802 EC6804 1 1 1 1 1 R6809 R6807 2 27 KBC_PW RBTN# 27 KBC_NOVO_BTN# 27 PW RLED 1 1 1 1 AFTP6809 AFTP6810 AFTP6811 AFTP6812 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title LED Bard/Power Button 5 4 3 2 Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 68 of 103 A B C SSID = KBC D E Normal Pad for B Series 5V ClickPad for V Series 3.3V SSID = Touch.Pad Internal KeyBoard Connector RN6903 TP_SW_R TP_SW_L 5V_S0 27 RN6904 RN6901 4 3 4 7 TP_PIN6 TP_PIN5 TP_PIN4 TP_PIN1 TP_PIN2 TP_PIN3 AFTP6902 AFTP6903 1 1 TP_SW_L TP_SW_R 1 2 3 4 5 6 ACES-CON6-13-GP RN6906 2C C6903 6903 DY 26 TP_PIN2 TP_PIN3 TP_PIN4 TP_PIN5 TP_PIN6 20.K0320.006 3D3V_S0 C6904 6904 2C 1 1 8 TP_DATA TP_CLK AFTP6939 B Series-TP TP_PIN1 DY 4 3 TP_CLK 1 2 C6902 SRN0J-6-GP V Series-TP V Series-TP TP_PIN1 TP_PIN2 PCH_SMBCLK 14,15,20,66 1 1 1 1 1 1 SRN0J-6-GP C6901 B Series-TP 1 AFTP6901 AFTP6930 AFTP6929 AFTP6931 AFTP6932 5V_S0 TP_CLK TP_DATA 4 3 SRN33J-5-GP-U SB 1015 Swap data and clk TP_PIN2 TP_PIN1 1 2 2 1 2 4 3 R6901 0R2J-2-GP DY 2 TPCLK TPDATA TPCLK TPDATA 1 KCOL10 KCOL11 KCOL14 KCOL13 KCOL12 KCOL3 KCOL6 KCOL8 KCOL7 KCOL4 KCOL2 KROW0 KCOL1 KCOL5 KROW3 KROW2 KCOL0 KROW5 KROW4 KCOL9 KROW6 KROW7 KROW1 RN6902 27 27 SCD1U10V2KX-4GP 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AFTP6942 TPAD1 RN6905 SC100P50V2JN-3GP KCOL15 1 TP_PIN6 TP_PIN3 1 2 B Series-TP TP_CLK SC100P50V2JN-3GP 1 4 3 SRN0J-6-GP SCD1U10V2KX-4GP 25 TP_DATA SRN10KJ-5-GP AFTP6904 AFTP6905 AFTP6906 AFTP6907 AFTP6908 AFTP6909 AFTP6910 AFTP6911 AFTP6912 AFTP6913 AFTP6914 AFTP6915 AFTP6916 AFTP6917 AFTP6918 AFTP6919 AFTP6920 AFTP6921 AFTP6922 AFTP6923 AFTP6924 AFTP6925 AFTP6926 AFTP6927 AFTP6928 1 KB14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TP_PIN5 TP_PIN4 1 2 SRN100J-3-GP B Series-TP 2 KCOL[0..15] KCOL15 KCOL10 KCOL11 KCOL14 KCOL13 KCOL12 KCOL3 KCOL6 KCOL8 KCOL7 KCOL4 KCOL2 KROW0 KCOL1 KCOL5 KROW3 KROW2 KCOL0 KROW5 KROW4 KCOL9 KROW6 KROW7 KROW1 GND 4 4 3 27 1 2 KROW[0..7] PCH_SMBDATA 14,15,20,66 RN6907 TP_DATA 4 3 1 2 TP_PIN3 TP_PIN4 SRN0J-6-GP V Series-TP ACES-CON24-7-GP 20.K0320.024 2nd = 20.K0391.024 3 1 TPSW1 SW-TACT4-14-GP 62.40009.D71 2 5 5 3 TP_SW_L 1 TP_SW_R B Series-TP 3 4 6 4 6 3 62.40009.D71 2 B Series-TP KB14 for 14" VB480 & VB485 KB15 for 15" VB580 & VB585 TPSW2 SW-TACT4-14-GP 1 1 AFTP6940 AFTP6941 2 2 1 1 <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title TOUCH PAD CONNECTOR A B C D Size A2 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet E 69 of 103 5 4 3 2 1 D D C C B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Hall Sensor Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 70 of 1 103 A 5 4 3 2 1 D D 3D3V_S0 DB1 21,27,65 LPC_AD0 21,27,65 LPC_AD1 21,27,65 LPC_AD2 21,27,65 LPC_AD3 21,27,65 LPC_FRAME# 5,18,27,31,36,65,66,80,82,83,97 PLT_RST# 18,65 CLK_PCI_LPC C 1 2 3 4 5 6 7 8 9 10 11 12 C MLX-CON10-7-GP 20.D0183.110 DY B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Dubug connector Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 71 of 1 103 A 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Reserved Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 72 of 1 103 A 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Reserved Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 73 of 1 103 A 5 4 3 2 1 D D C C B B A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CARD Reader CONN 5 4 3 2 Size A2 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 74 of 103 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title New Card Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 75 of 1 103 A 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Reserved Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 76 of 1 103 A 5 4 3 2 1 D D C C B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Reserved Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 77 of 1 103 A 5 4 3 2 1 D D BLANK C C B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Reserved Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 78 of 1 103 A 5 4 3 2 1 3D3V_S5 VCC3_ACC 2 1 1 E B R1 SCD1U10V2KX-4GP R2 84.00114.H1K 2nd = 84.09114.A11 3rd = 84.00014.01H C7902 SC10U6D3V5KX-1GP Q7901 PDTA114EE-3-GP-U D C7901 2 2 10R2J-2-GP 1 R7901 C VCC3M_Q34 G-Sensor V Series Only D ANALOG_AGND 1 27 GSENSE_ON# R7902 100KR2J-1-GP 4 NC#4 ANALOG_AGND 15 NC#9 VOUTX 12 NC#11 11 NC#13 13 NC#16 16 C7904 SCD1U10V2KX-4GP GSENSE_X_R ROHM-KIONIX 2 56KR2J-L1-GP C7907 SCD1U10V2KX-4GP C7905 SCD1U10V2KX-4GP 2nd = 74.KXTC8.0BZ 74.KXTC8.0BZ 1 R7907 2 56KR2J-L1-GP C7908 SCD1U10V2KX-4GP 2 LIS34ALTR-GP KXTC8-2850-GP 1 R7906 GSENSE_Y 27 GSENSE_X 27 ANALOG_AGND 1 9 10 1 NC#1 VOUTY GSENSE_Y_R 2 1 C 8 1 GND GND GND 2 5 6 7 VOUTZ TP7901 2 ST GND 1 1 1 R7904 0R0402-PAD 2 R7903 100KR2J-1-GP 2 3 1 2 GSENSE_TST 1 GSENSE_Z RES TP7902 C VDD U7901 14 2 DY ANALOG_AGND B B <Core Design> Wistron Corporation Layout Comment : A (1) Place C483, C484, Q46, R528, R530, C479, C476, R509, R508 close to U55. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title G-Sensor (2) Avoid routing under DCDC switching area. Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 79 of 1 103 A 5 4 3 2 1 D D RFID 3D3V_S5 1 3D3V_S0 3D3V_S5 R8001 4K7R2J-2-GP 2 U8001 Q8001 B C R1 PROT_EEPROM NC#1 NC#2 PROT# GND VCC WP SCL SDA 8 7 6 5 C SMB_CLK 20 SMB_DATA 20 1 E 1 2 3 4 PDTC115TE-GP BUL08-1FVJ-WGE2-GP 84.00115.E1K 2nd = 84.09115.A11 3rd = 84.00015.B1H 72.BUL08.A0Q 2nd = 72.24S08.A0Q 3rd = 72.26C08.00R PLT_RST# 2 C C8001 SCD01U50V2KX-1GP 5,18,27,31,36,65,66,71,82,83,97 Table 80.1- Transistor multi-source Supplier Description Lenovo P/N NXP PDTC115TE N/A Wistron P/N 84.00115.E1K B B ROHM LTC015TEB N/A 84.00015.B1H Panasonic DRC9115T0L N/A 84.09115.A11 Table 80.2- EEPROM multi-source Supplier Description Lenovo P/N Wistron P/N <Core Design> A ROHM BUL08-1FVJ-WGE2 N/A 72.BUL08.A0Q NXP PCA24S08ADP N/A 72.24S08.A0Q SANYO LE26CAP08TT-TLM-H N/A 72.26C08.00R Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title RF ID Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 80 of 1 103 A 5 4 3 2 1 D D BLANK C C B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Reserved Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 81 of 1 103 A 5 4 3 2 1 5V_USB4_S3 USB_PN2_R EC8202 SCD1U16V2KX-3GP USBCN1 11 1 3 USB_PN2 2 18 2 1 R8201 and R8203 Dual layout with TR8201 D TR8202 FILTER-130-GP 3D3V_AUX_S5 1st = 68.11900.20A 18 ADP_LED USB_PN2_R USB_PP2_R AFTP8206 4 1 27 1 2 3 4 5 6 7 8 9 10 12 D USB_PP2_R USB_PP2 ACES-CON10-19-GP 20.K0420.010 RN8202 18 USB_OC#8_9 27,61,62 USB_PW R_EN_R 1 2 USB_PW R_OC# USB_PW R_EN 4 3 SRN0J-6-GP B Series-USB PWR C AFTP8201 AFTP8202 AFTP8203 AFTP8204 AFTP8205 1 1 1 1 1 5V_USB4_S3 3D3V_AUX_S5 ADP_LED USB_PN2_R USB_PP2_R AFTP8210 AFTP8213 AFTP8223 AFTP8212 AFTP8209 1 1 1 1 1 HPOUT_JD USB_PW R_OC# USB_PW R_EN USB_AO_SEL0 AUD_MIC1_COMBO_R AFTP8207 AFTP8208 1 1 AUD_HPOUT_R AUD_HPOUT_L AFTP8211 1 AU_GND AFTP8214 AFTP8215 AFTP8216 AFTP8217 AFTP8218 AFTP8219 AFTP8220 AFTP8221 AFTP8224 1 1 1 1 1 1 1 1 1 USB_PP5_R USB_PN5_R USB_PP9_R USB_PN9_R CLK_PCH_48M PLT_RST# 3D3V_S0_CARD 5V_S5 AFTP8222 AFTP8225 1 1 GND C RN8201 1 2 27 CHG_USB_OC# 27 USB_CHG_EN USB_PW R_OC# USB_PW R_EN 4 3 SRN0J-6-GP V Series-USB PWR USB_PN9_R 3 USB_PN9 2 CDRCN1 TR8201 FILTER-130-GP 32 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 18 4 1 1st = 68.11900.20A USB_PP9_R USB_PP9 B 18 USB_PN5 0R0402-PAD 1 2 R8206 USB_PN5_R AUD_HPOUT_R 29 AUD_HPOUT_L 29 AUD_MIC1_COMBO_R HPOUT_JD 29 29 USB_PW R_OC# USB_AO_SEL0 27 AU_GND USB_PP5_R USB_PN5_R Cardreader USB_PP9_R USB_PN9_R B USB Port3 USB_PW R_EN 3D3V_S0 CLK_PCH_48M 20 PLT_RST# 5,18,27,31,36,65,66,71,80,83,97 3D3V_S0_CARD 1 R8202 0R0805-PAD 2 3D3V_S0_CARD CLK_PCH_48M 1 18 DY EC8203 1 USB_PP5 2 R8207 SC22P50V2JN-4GP 1 EC8201 20.K0510.030 2 ACES-CON30-9-GP-U SCD1U16V2KX-3GP 18 0R0402-PAD 1 2 5V_S5 31 USB_PP5_R <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title IO Board Connector 5 4 3 2 Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 82 of 103 5 4 3 2 1 PCI Express PEX_IOVVD/Q Combined (DG-05587-001_v03_p.72_Table 10) Capacitor Type 1.0uF 4.7uF 10uF 22uF SPEC. (DG-05587-001_v03_p.70) PEX_CLK_REQ_N is an open-drain bi-directional signal; by default it should have a 10 kΩ pull-up to 3.3V. This signal is an active low signal. D 4 PEG_TXP[0..15] PEG_RXP[0..15] 4 4 PEG_TXN[0..15] PEG_RXN[0..15] 4 X6S X5R 3D3V_VGA_S0 Footprint Population Location Under GPU Near GPU Midway Between GPU and Power Supply Midway Between GPU and Power Supply 4 2 4 4 0402 0603 0805 0805 X6S X6S X5R X5R (+/-22%、-55~105℃) (+/-15%、-55~85℃) 1D05V_VGA_S0 D 1.05V ±30mV 3300mA total PEG_RXP6 PEG_RXN6 SCD22U10V2KX-1GP SCD22U10V2KX-1GP OPS 1 OPS 1 2 C8314 2 C8313 PEG_RXP7 PEG_RXN7 SCD22U10V2KX-1GP SCD22U10V2KX-1GP OPS 1 OPS 1 2 C8316 2 C8315 PEG_RXP8 PEG_RXN8 PEG_RXP9 PEG_RXN9 SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP OPS 1 OPS 1 OPS 1 OPS 1 2 C8318 2 C8317 2 C8320 2 C8319 PEG_TXP2 PEG_TXN2 AP14 AP15 PEG_C_RXP3 PEG_C_RXN3 AL16 AK16 PEG_TXP3 PEG_TXN3 AN15 AM15 PEG_C_RXP4 PEG_C_RXN4 AK17 AJ17 PEG_TXP4 PEG_TXN4 AN17 AM17 PEG_C_RXP5 PEG_C_RXN5 AH17 AG17 PEG_TXP5 PEG_TXN5 AP17 AP18 PEG_C_RXP6 PEG_C_RXN6 AK18 AJ18 PEG_TXP6 PEG_TXN6 AN18 AM18 PEG_C_RXP7 PEG_C_RXN7 AL19 AK19 PEG_TXP7 PEG_TXN7 AN20 AM20 PEG_C_RXP8 PEG_C_RXN8 AK20 AJ20 PEG_TXP8 PEG_TXN8 AP20 AP21 PEG_C_RXP9 PEG_C_RXN9 AH20 AG20 PEG_TXP9 PEG_TXN9 PEG_RXP10 PEG_RXN10 B SCD22U10V2KX-1GP SCD22U10V2KX-1GP OPS 1 OPS 1 2 C8322 2 C8321 PEG_TXP10 PEG_TXN10 PEG_RXP11 PEG_RXN11 SCD22U10V2KX-1GP SCD22U10V2KX-1GP OPS OPS 1 1 2 C8324 2 C8323 SCD22U10V2KX-1GP SCD22U10V2KX-1GP OPS 1 OPS 1 2 C8326 2 C8325 SCD22U10V2KX-1GP SCD22U10V2KX-1GP OPS 1 OPS 1 2 C8328 2 C8327 PEG_C_RXP14 AK24 PEG_C_RXN14 AJ24 PEG_TXP14 PEG_TXN14 PEG_RXP15 PEG_RXN15 SCD22U10V2KX-1GP SCD22U10V2KX-1GP OPS 1 OPS 1 2 C8332 2 C8331 AP26 AP27 PEG_C_RXP15 AL25 PEG_C_RXN15 AK25 PEG_TXP15 PEG_TXN15 AN27 AM27 Near GPU Capacitor Type PEX_RX3 PEX_RX3# PEX_RX4 PEX_RX4# X5R Footprint X5R X5R 0.1uF 4.7uF PEX_TX4 PEX_TX4# PEX_PLL_HVDD PEX_SVDD_3V3 Midway Between GPU and Power Supply Population 0402 0603 1 2 Near GPU Near GPU AG12 PEX_RX7 PEX_RX7# OPS C8347 C8348 PEX_RX8 PEX_RX8# GND_SENSE 1 R8310 PLT_RST# DY 2 VGA_RST# 0R2J-2-GP C8349 4.7uF(X5R) K0603 ×2 3D3V_S0 U8301 1 18 DGPU_HOLD_RST# PLT_RST# DY 2 3 VGA_CORE 1 R8304 VDD_SENSE 5,18,27,31,36,65,66,71,80,82,97 OPS Near GPU PEX_TX8 PEX_TX8# dGPU reset (DG-05587-001_v03_p.71_Table 9) PEX_TX7 PEX_TX7# B VCC A Y 5 VGA_RST# 4 GND R8319 10KR2J-3-GP 74LVC1G08GW-1-GP 73.01G08.L04 OPS OPS 1st = 73.01G08.DHG 2nd = 73.7SZ08.DAH 3rd = 73.01G08.FHG 2 0R2J-2-GP L4 L5 PEX_TX9 PEX_TX9# NVVDD_SENSE 92 NVGND_SENSE 92 R8305 0R2J-2-GP PEX_RX9 PEX_RX9# DY PEX_TX10 PEX_TX10# NC_3V3AUX PEX_RX10 PEX_RX10# PCI Express PEX_PLLVDD (DG-05587-001_v03_p.72_Table 11) Capacitor Type P8 SPEC. (DG-05587-001_v03_p.70) PEX_TSTCLK_OUT should be terminated with a 200Ω resistor. PEX_TX11 PEX_TX11# PEX_RX11 PEX_RX11# PEX_TSTCLK_OUT PEX_TSTCLK_OUT# AJ26 AK26 PEX_TSTCLK_OUT R8306 2 PEX_TSTCLK_OUT# 100nF 1.0uF 4.7uF OPS X6S X5R 1 200R2F-L-GP PEX_RX12 PEX_RX12# 100nF(X7R) K0402 ×1 PEX_PLLVDD AG26 3D3V_VGA_S0 TESTMODE AK11 TESTMODE 1 R8307 PEX_TERMP AP29 PEX_TERMP 1 R8309 OPS 2 10KR2J-3-GP 1 R8308 DY PEX_RX14 PEX_RX14# PEX_TX15 PEX_TX15# Footprint X6S X5R X5R 0402 0603 0805 2 10KR2J-3-GP OPS C8350 Population 1 1 1 B Location Under GPU Near GPU Near GPU (+/-22%、-55~105℃) (+/-15%、-55~85℃) 1D05V_VGA_S0 OPS-BOM CTRL 1.0nF(X5R) 4.7nF(X5R) K0402 ×1 K0603 ×1 1.05V ±30mV 150mA total VCC1R05VIDEO_PEX_PLLVDD PEX_RX13 PEX_RX13# PEX_RX15 PEX_RX15# C Location 3.3V ±10% 210mA total AH12 0.1uF(X5R) K0402 ×1 PEX_RX6 PEX_RX6# PEX_TX14 PEX_TX14# C8346 (+/-15%、-55~85℃) OPS PEX_TX6 PEX_TX6# PEX_TX13 PEX_TX13# OPS C8345 3D3V_VGA_S0 PEX_TX5 PEX_TX5# PEX_TX12 PEX_TX12# SC22U6D3V5MX-2GP 2 1 1 2 C8343 SC10U6D3V3MX-GP PCI Express PEX_SVDD/PLL_HVDD Connected to NV3V3 (DG-05587-001_v03_p.72_Table 12) PEX_TX3 PEX_TX3# PEX_RX5 PEX_RX5# SC4D7U6D3V3KX-GP 2 1 Under GPU OPS OPS OPS C8351 SC4D7U6D3V3KX-GP 2 C8330 2 C8329 PEX_RX2 PEX_RX2# C8342 SC1U6D3V2KX-GP OPS 1 OPS 1 AN26 AM26 PEX_TX2 PEX_TX2# OPS C8341 SCD1U10V2KX-5GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP AN24 AM24 PEG_C_RXP13 AH23 PEG_C_RXN13 AG23 PEG_TXP13 PEG_TXN13 PEG_RXP14 PEG_RXN14 AP23 AP24 PEG_C_RXP12 AK23 PEG_C_RXN12 AJ23 PEG_TXP12 PEG_TXN12 PEG_RXP13 PEG_RXN13 AN23 AM23 PEG_C_RXP11 AL22 PEG_C_RXN11 AK22 PEG_TXP11 PEG_TXN11 PEG_RXP12 PEG_RXN12 AN21 AM21 PEG_C_RXP10 AK21 PEG_C_RXN10 AJ21 PEX_RX1 PEX_RX1# OPS C8340 SC22U6D3V5MX-2GP 2 1 AK15 AJ15 AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28 SC22U6D3V5MX-2GP 2 1 PEG_C_RXP2 PEG_C_RXN2 OPS PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14 1 AN14 AM14 PEX_TX1 PEX_TX1# 22uF(X5R) M0805 ×4 2 PEG_TXP1 PEG_TXN1 PEX_RX0 PEX_RX0# SC4D7U6D3V3KX-GP 2 1 AH14 AG14 10uF(X5R) M0805 ×4 2 2 C8312 2 C8311 PEG_C_RXP1 PEG_C_RXN1 PEX_TX0 PEX_TX0# 4.7uF(X5R) K0603 ×2 1 OPS 1 OPS 1 2 C8310 2 C8309 AN12 AM12 1uF(X5R) K0402 ×4 R8311 2 1 0R3J-0-U-GP (DG-05587-001_v03_p.71_Table 9) 1 SCD22U10V2KX-1GP SCD22U10V2KX-1GP OPS OPS 1 1 2 C8308 2 C8307 PEG_TXP0 PEG_TXN0 PEX_REFCLK PEX_REFCLK# C8339 OPS C8352 Stuff 0 ohm(63.00000.00L) for N13P-GS/N13M-GS, Stuff bead(68.00082.001) for N13P-GL/N13M-GE 2 PEG_RXP5 PEG_RXN5 SCD22U10V2KX-1GP SCD22U10V2KX-1GP OPS 1 OPS 1 2 C8306 2 C8305 AK14 AJ14 1 0.22uF(X5R) K0402 PEG_RXP4 PEG_RXN4 SCD22U10V2KX-1GP SCD22U10V2KX-1GP OPS 1 OPS 1 2 C8304 2 C8303 PEG_C_RXP0 PEG_C_RXN0 2 SPEC. (DG-05587-001_v03_p.70) For PCI ECPRESS connection, please use 0.22uF,20%,0402,X5R or better AC couplimg capacitors. SCD22U10V2KX-1GP SCD22U10V2KX-1GP OPS 1 OPS 1 2 C8301 2 C8302 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 PEX_IOVDD_6 C8336 SC10U6D3V3MX-GP 1 PEG_RXP3 PEG_RXN3 SCD22U10V2KX-1GP SCD22U10V2KX-1GP OPS 1 OPS 1 PEX_CLKREQ# OPS OPS 2 PEG_RXP2 PEG_RXN2 SCD22U10V2KX-1GP SCD22U10V2KX-1GP PEX_RST# SC4D7U6D3V3KX-GP 2 1 PEG_RXP0 PEG_RXN0 PEG_RXP1 PEG_RXN1 C AL13 AK13 20 CLK_PCIE_VGA 20 CLK_PCIE_VGA# 2N7002K-2-GP 84.2N702.J31 2ND = 84.2N702.031 AK12 C8335 1 VGA_PEG_CLKREQ# S AG19 AG21 AG22 AG24 AH21 AH25 OPS C8334 2 VGA_RST# AJ12 D PEX_WAKE# SC1U6D3V2KX-GP 2 1 AJ11 OPS C8333 SC1U6D3V2KX-GP 2 1 G 20 PEG_CLKREQ# OPS 1 OF 17 1/17 PCI_EXPRESS SC4D7U6D3V3KX-GP 2 1 VGA1A SC1U6D3V2KX-GP 2 1 DY R8303 SC1U6D3V2KX-GP 2 1 Q8301 R8302 SCD1U10V2KX-4GP 2 1 2 OPS 2 10KR2J-3-GP 1 OPS 3D3V_VGA_S0 10KR2J-3-GP 1 (DG-05587-001_v03_p.71_Table 9) OPS 2 2K49R2F-GP Under GPU Near GPU N13P-GS-A1-GP OPS-BOM CTRL A SPEC. (DG-05587-001_v03_p.214) By default, pull-down the TESTMODE pin to GND with a 10kΩ resistor. For XOR tree testing, TESTMODE should be pulled up to 3v3 with a 10 kΩ resistor. A SPEC. (DG-05587-001_v03_p.70) PEX_TERMP is used for internal calibration; pull-down this signal with 2.49 kΩ,1% resistor. <Core Design> Wistron Corporation 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title N13P_GPU (1/5): PEG Size A2 Date: 5 4 3 2 Document Number Rev SD LA48 Friday, January 06, 2012 1 Sheet 83 of 103 A B C E 10 OF 17 VGA1J 5/17 IFPAB LVDS Interface D ALL PINS NC FOR GF117 TP8401 1 IFPAB_RSET AJ8 4 IFPA_TXC# IFPA_TXC IFPA_TXD0# IFPA_TXD0 1 IFPAB_PLLVDD AH8 AN6 AM6 IFPAB_PLLVDD IFPA_TXD1# IFPA_TXD1 R8401 10KR2J-3-GP AN3 AP3 TP8403 AM5 AN5 1 IFPC_RSET AF8 AF7 IFPC_RSET IFPC_PLLVDD R8405 10KR2J-3-GP OPS AH6 AJ6 DVI/HDMI DP I2CW_SDA I2CW_SCL IFPC_AUX_I2CW_SDA# IFPC_AUX_I2CW_SCL TXC TXC IFPC_L3# IFPC_L3 TXD0 TXD0 IFPC_L2# IFPC_L2 TXD1 TXD1 IFPC_L1# IFPC_L1 TXD2 TXD2 IFPC_L0# IFPC_L0 AG2 AG3 AG4 AG5 2 IFPA_TXD3# IFPA_TXD3 IFPC_PLLVDD AK6 AL6 1 2 SPEC. (DG-05587-001_v03_p.160) Pull down IFPxy IOVDD with 10kΩ resistor. Pull down IFPxy PLLVDD with 10kΩ resistor. The other IO pins can be NC, this includes unused data lines. 4 ALL PINS NC FOR GF117 OPS IFPA_TXD2# IFPA_TXD2 11 OF 17 VGA1K 6/17 IFPC IFPAB_RSET IFPB_TXC# IFPB_TXC AG8 IFPAB_IOVDD IFPA_IOVDD IFPB_TXD4# IFPB_TXD4 IFPB_IOVDD 1 AG9 IFPB_TXD5# IFPB_TXD5 AP5 AP6 AL7 AM7 IFPC_IOVDD 1 R8402 10KR2J-3-GP IFPC AH9 AJ9 2 IFPB_TXD6# IFPB_TXD6 IFPB_TXD7# IFPB_TXD7 GPIO14 IFPAB 3 AM8 AN8 AL8 AK8 AF6 IFPC_IOVDD R8406 10KR2J-3-GP N13P-GS-A1-GP OPS OPS-BOM CTRL GPIO15 AJ2 AJ3 AJ1 AK1 P2 2 OPS AH4 AH3 N4 3 N13P-GS-A1-GP OPS-BOM CTRL 13 OF 17 VGA1M 8/17 IFPEF 12 OF 17 VGA1L 7/17 IFPD HDMI Interface ALL PINS NC FOR GF117 ALL PINS NC FOR GF117 DVI-DL DVI-SL/HDMI DP TP8404 1 AB8 IFPF_REST AD6 IFPE_AUX_I2CY_SDA# IFPE_AUX_I2CY_SCL IFPD_RSET 1 AB4 AB3 IFPD_PLLVDD IFPEF_PLLVDD IFPEF_RSET TXC TXC TXC TXC IFPE_L3# IFPE_L3 AC5 AC4 TXD0 TXD0 2 TXD0 TXD0 IFPE_L2# IFPE_L2 OPS IFPE TXD1 TXD1 TXD2 TXD2 2 TXD2 TXD2 HPD_E IFPE_L1# IFPE_L1 IFPE_L0# IFPE_L0 GPIO18 IFPD_RSET IFPD_PLLVDD OPS IFPD AC1 AD1 AD3 AD2 IFPD_IOVDD R1 1 HPD_E TXD1 TXD1 AG7 R8407 10KR2J-3-GP AC3 AC2 2 R8403 10KR2J-3-GP AN2 DVI/HDMI DP I2CX_SDA I2CX_SCL IFPD_AUX_I2CX_SDA# IFPD_AUX_I2CX_SCL AK2 AK3 1 IFPEF_PLLVDD I2CY_SDA I2CY_SCL 1 TP8402 I2CY_SDA I2CY_SCL AG6 IFPD_IOVDD TXC TXC IFPD_L3# IFPD_L3 TXD0 TXD0 IFPD_L2# IFPD_L2 TXD1 TXD1 IFPD_L1# IFPD_L1 TXD2 TXD2 IFPD_L0# IFPD_L0 GPIO17 AK5 AK4 AL4 AL3 AM4 AM3 2 AM2 AM1 M6 N13P-GS-A1-GP OPS-BOM CTRL 2 R8408 10KR2J-3-GP IFPEF_IOVDD AC7 IFPE_IOVDD I2CZ_SDA I2CZ_SCL IFPF_AUX_I2CZ_SDA# IFPF_AUX_I2CZ_SCL OPS AF2 AF3 IFPF_IOVDD 1 AC8 2 R8404 10KR2J-3-GP OPS IFPF TXC TXC IFPF_L3# IFPF_L3 TXD3 TXD3 TXD0 TXD0 IFPF_L2# IFPF_L2 TXD4 TXD4 TXD1 TXD1 IFPF_L1# IFPF_L1 TXD5 TXD5 TXD2 TXD2 IFPF_L0# IFPF_L0 HPD_F GPIO19 AF1 AG1 AD5 AD4 AF5 AF4 AE4 AE3 P3 N13P-GS-A1-GP OPS-BOM CTRL 1 1 <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title A B C D N13P_GPU (2/5): DIGITALOUT Size A2 Document Number Date: Friday, January 06, 2012 Rev LA48 SD Sheet E 84 of 103 FB_VREF H26 R32 AC32 FBA_DEBUG0 FBA_DEBUG1 FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1# FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7 FBA_WCK1 FBA_WCK1# FBA_WCK23 FBA_WCK23# FBA_WCK45 FBA_WCK45# FBA_WCK67 FBA_WCK67# FB_VREF FBA_WCKB1 FBA_WCKB1# FBA_WCKB23 FBA_WCKB23# FBA_WCKB45 FBA_WCKB45# FBA_WCKB67 FBA_WCKB67# FBA_PLL_AVDD R28 R8518 1 AC28 1 R8519 DY DY R30 R31 AB31 AC31 J30 J31 J32 J33 AH31 AJ31 AJ32 AJ33 66mA U27 FB_PLLVDD X7R X5R 0402 0805 E11 E3 A3 C9 F23 F27 C30 A24 FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7 90 90 90 90 91 91 91 91 FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7 D10 D5 C3 B9 E23 E28 B30 A23 90 90 90 90 91 91 91 91 FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7 D9 E4 B2 A9 D22 D28 A30 B23 FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7 Population Location 1 per pin 1 Under GPU Near GPU OPS C8517 OPS C8518 FBB_ODT1 FBB_CKE1 FBB_A13 FBB_A8 FBB_A6 FBB_A11 FBB_A5 FBB_A3 FBB_BA2 FBB_BA1 FBB_A12 FBB_A10 FBB_RAS# 91 91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 FBB_DEBUG0 FBB_DEBUG1 FBB_WCK1 FBB_WCK1# FBB_WCK23 FBB_WCK23# FBB_WCK45 FBB_WCK45# FBB_WCK67 FBB_WCK67# FBB_WCKB1 FBB_WCKB1# FBB_WCKB23 FBB_WCKB23# FBB_WCKB45 FBB_WCKB45# FBB_WCKB67 FBB_WCKB67# THE FBB_WCKBxx PINS ARE USED ONLY ON GK107 THEY ARE NC FOR GF108 AND FOR GF117 R8523 0R3J-0-U-GP 1 2 FBB_PLL_AVDD G14 R8520 1 G20 1 R8521 DY DY 2 60D4R2F-GP 2 10KR2J-3-GP FBB_CLK0 FBB_CLK0# FBB_CLK1 FBB_CLK1# 90 90 91 91 OPS SCD1U10V2KX-5GP 2 1 SCD1U10V2KX-5GP 2 1 SCD1U10V2KX-5GP 2 1 SCD1U10V2KX-5GP 2 1 SCD1U10V2KX-5GP 2 1 SCD1U10V2KX-5GP 2 1 SCD1U10V2KX-5GP 2 1 SCD1U10V2KX-5GP 2 1 OPS C8508 C8514 OPS C8511 OPS OPS C8515 C8512 1uF(X7R) K0603 ×4 OPS C8516 C 10uF(X5R) M0805 ×2 F1 F2 1D5V_VGA_S0 FB_CAL_PU_GND J27 FB_CAL_PD_VDDQ 1 R8501 2 40D2R2F-GP H27 FB_CAL_PU_GND H25 FB_CAL_TERM_GND OPS N13P-GS-A1-GP OPS-BOM CTRL F8 E8 A5 A6 D24 D25 B27 C27 OPS R8502 OPS R8503 Default GPU Drive Calibration for DDR3 (DG-05587-001_v03_p.82_Table 17) D6 D7 C6 B6 F26 E26 A26 A27 Memory/PKG FBVDDQ DDR3 1.5V FBCAL_PU_GND FBCAL_PU_VDDQ 42.2Ω FBCAL_TERM_GND 40.2Ω 51.1Ω B *Use only 1% resistors for driver calibration. (DG-05587-001_v03_p.88_Table 25) 66mA FB_PLLVDD H17 OPS-BOM CTRL Stuff 0 ohm(63.00000.00L) for N13P-GS/N13M-GS, Stuff bead(68.00084.H41) for N13P-GL/N13M-GE FBCLK Termination placed at each VRAM FBA_CLK1 Under GPU FBA_CLK0 R8504 160R2F-GP Near GPU R8505 160R2F-GP FBB_CLK0 OPS FBA_CLK0# R8506 160R2F-GP OPS R8507 160R2F-GP FBB_CLK1# OPS FBB_CLK0# (DG-05587-001_v03_p.84_Table 20) R8514 OPS R8515 OPS R8516 10KR2J-3-GP 2 1 R8513 OPS 10KR2J-3-GP 2 1 R8512 OPS 10KR2J-3-GP 2 1 R8511 OPS 10KR2J-3-GP 2 1 R8510 OPS 10KR2J-3-GP 2 1 R8509 OPS 10KR2J-3-GP 2 1 R8508 OPS 10KR2J-3-GP 2 1 OPS 10KR2J-3-GP 2 1 FBB_CKE0 FBB_CKE1 FBB_RST FBB_ODT0 FBB_ODT1 10KR2J-3-GP 2 1 FBA_CKE0 FBA_CKE1 FBA_RST FBA_ODT0 FBA_ODT1 (+/-15%、-55~125℃) (+/-15%、-55~85℃) (DG-05587-001_v03_p.83_Table 19) FBB_CLK1 OPS 10KR2J-3-GP 2 1 A X7R X5R C8507 C8519 Memory ODTx, CKEx and RST Termination 1 OPS C8506 N13P-GS-A1-GP Bead Type 0603 C8510 OPS 4.7uF(X5R) K0603 ×2 FB_CAL_TERM_GND D12 E12 E20 F20 OPS Near GPU FB_CAL_PD_VDDQ FBA_CLK1# 30Ω @100MHz (ESR=0.01Ω) C8513 OPS FB_VDDQ_SENSE C12 C20 C8509 OPS 1 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 90,91 91 C8505 2 FBB_RST FBB_A9 FBB_A7 FBB_A2 FBB_A0 FBB_A4 FBB_A1 FBB_BA0 FBB_WE# FBB_A15 FBB_CAS# FBB_CS1# FB_GND_SENSE FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7 OPS-BOM CTRL 100nF(X7R) K0402 ×3 90 90 OPS C8504 Under GPU OPS 1D5V_VGA_S0 FBB_CLK0 FBB_CLK0# FBB_CLK1 FBB_CLK1# 1D05V_VGA_S0 1.05V ±30mV 167mA total FBB_CMD_RFU0 FBB_CMD_RFU1 FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7 (DG-05587-001_v03_p.88_Table 25) FBx_PLL_AVDD, FB_DLL_AVDD and PLLVDD combined (DG-05587-001_v03_p.88_Table 26) Footprint 88 88 89 89 K31 L30 H34 J34 AG30 AG31 AJ34 AK34 OPS-BOM CTRL 100nF 22uF 260D4R2F-GP 2 10KR2J-3-GP FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1# N13P-GS-A1-GP Capacitor Type 90 90 90 90 91 91 91 91 90 FBB_ODT0 FBB_CKE0 OPS C8503 SC4D7U6D3V3KX-GP 2 1 89 89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 FBB_CS0# OPS 1 FBA_ODT1 FBA_CKE1 FBA_A13 FBA_A8 FBA_A6 FBA_A11 FBA_A5 FBA_A3 FBA_BA2 FBA_BA1 FBA_A12 FBA_A10 FBA_RAS# ODT CKE A13 A8 A6 A11 A5 A3 BA2 BA1 A12 A10 RAS# A13 A8 A6 A11 A5 A3 BA2 BA1 A12 A10 RAS# FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31 C8502 2 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 88,89 89 FB CMD mapping Mode D-N13x D13 E14 F14 A12 B12 C14 B14 G15 F15 E15 D15 A14 D14 A15 B15 C17 D18 E18 F18 A20 B20 C18 B18 G18 G17 F17 D16 A18 D17 A17 B17 E17 OPS C8501 SC4D7U6D3V3KX-GP 2 1 FBA_RST FBA_A9 FBA_A7 FBA_A2 FBA_A0 FBA_A4 FBA_A1 FBA_BA0 FBA_WE# FBA_A15 FBA_CAS# FBA_CS1# SCD1U10V2KX-5GP 2 1 1 88 88 1D5V_VGA_S0 THE FBA_WCKBxx PINS ARE USED ONLY ON GK107 THEY ARE NC FOR GF108 AND FOR GF117 TP8507 88 FBA_ODT0 FBA_CKE0 A14 RST A9 A7 A2 A0 A4 A1 BA0 WE# A15 CAS# CS0# OPS FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 FBVDDQ_38 FBVDDQ_39 FBVDDQ_40 FBVDDQ_41 FBVDDQ_42 FBVDDQ_43 FBVDDQ_44 D 1 FBA_CMD_RFU0 FBA_CMD_RFU1 FBA_CS0# ODT CKE A14 RST A9 A7 A2 A0 A4 A1 BA0 WE# A15 CAS# AA27 AA30 AB27 AB33 AC27 AD27 AE27 AF27 AG27 B13 B16 B19 E13 E16 E19 H10 H11 H12 H13 H14 H15 H16 H18 H19 H20 H21 H22 H23 H24 H8 H9 L27 M27 N27 P27 R27 T27 T30 T33 V27 W27 W30 W33 Y27 4 OF 17 SC1U6D3V3KX-2GP 2 1 FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31 U30 T31 U29 R34 R33 U32 U33 U28 V28 V29 V30 U34 U31 V34 V33 Y32 AA31 AA29 AA28 AC34 AC33 AA32 AA33 Y28 Y29 W31 Y30 AA34 Y31 Y34 Y33 V31 CS0# VGA1D 14/17 FBVDDQ SC4D7U6D3V3KX-GP 2 1 FB CMD mapping Mode D-N13x FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 B FBx_CMD0 FBx_CMD1 FBx_CMD2 FBx_CMD3 FBx_CMD4 FBx_CMD5 FBx_CMD6 FBx_CMD7 FBx_CMD8 FBx_CMD9 FBx_CMD10 FBx_CMD11 FBx_CMD12 FBx_CMD13 FBx_CMD14 FBx_CMD15 FBx_CMD16 FBx_CMD17 FBx_CMD18 FBx_CMD19 FBx_CMD20 FBx_CMD21 FBx_CMD22 FBx_CMD23 FBx_CMD24 FBx_CMD25 FBx_CMD26 FBx_CMD27 FBx_CMD28 FBx_CMD29 FBx_CMD30 FBx_CMD31 1D5V_VGA_S0 0.1uF(X7R) K0402 ×8 SC1U6D3V3KX-2GP 2 1 N13x DDR3 Data Bits Data Bits mode D [31:0] [63:32] (+/-15%、-55~125℃) (+/-22%、-55~105℃) (+/-15%、-55~85℃) 2 M30 H30 E34 M34 AF30 AK31 AM34 AF32 Mode D Command Mapping (DG-05587-001_v03_p.78_Table 16) X7R X6S X5R Under GPU Under GPU Under GPU Near GPU 8 2 2 4 1 FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7 35mA (DG-05587-001_v03_p.88_Table 25) Population Location 8 2 2 4 2 88 88 88 88 89 89 89 89 FB_PLLVDD K27 42D2R2F-GP 2 1 M31 G31 E33 M33 AE31 AK30 AN33 AF33 FB_DLL_AVDD FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63 Footprint 0402 0603 0603 0805 X7R X7R X6S X5R 0.1uF 1uF 4.7uF 10uF 51D1R2F-GP 2 1 FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 DY G9 E9 G8 F9 F11 G11 F12 G12 G6 F5 E6 F6 F4 G4 E2 F3 C2 D4 D3 C1 B3 C4 B5 C5 A11 C11 D11 B11 D8 A8 C8 B8 F24 G23 E24 G24 D21 E21 G21 F21 G27 D27 G26 E27 E29 F29 E30 D30 A32 C31 C32 B32 D29 A29 C29 B29 B21 C23 A21 C21 B24 C24 B26 C26 1 88 88 88 88 89 89 89 89 FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63 2 P30 F31 F34 M32 AD31 AL29 AM32 AF34 FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 Capacitor Type 90,91 FBB_D[63..0] 2 10KR2F-2-GP SCD1U10V2KX-5GP 2 1 88 88 88 88 89 89 89 89 FB_CLAMP PS_FB_CLAMP 1 R8522 1 GPU FBVDDQ Decoupling (DG-05587-001_v03_p.86_Table 22) SC10U6D3V3MX-GP C FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 E1 SCD1U10V2KX-5GP 2 1 D L28 M29 L29 M28 N31 P29 R29 P28 J28 H29 J29 H28 G29 E31 E32 F30 C34 D32 B33 C33 F33 F32 H33 H32 P34 P32 P31 P33 L31 L34 L32 L33 AG28 AF29 AG29 AF28 AD30 AD29 AC29 AD28 AJ29 AK29 AJ30 AK28 AM29 AM31 AN29 AM30 AN31 AN32 AP30 AP32 AM33 AL31 AK33 AK32 AD34 AD32 AC30 AD33 AF31 AG34 AG32 AG33 2 3 OF 17 SC10U6D3V3MX-GP FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 3 VGA1C 3/17 FBB SC4D7U6D3V3KX-GP 2 1 89 FBA_D[63..0] 4 (DA-05691-001_v03_p.4_Table 2) NC NC Pull down FB_CLAMP with a 10kΩ Pull down FB_CLAMP with a 10kΩ 1 E1 N13P-GL N13M_GE1 N13M-GS N13P-GS 2 OF 17 2 5 VGA1B 2/17 FBA A OPS R8517 <Core Design> Wistron Corporation 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title N13P_GPU (3/5): VRAM I/F Size A2 Date: 5 4 3 2 Document Number Rev SD LA48 Friday, January 06, 2012 1 Sheet 85 of 103 5 4 3D3V_VGA_S0 3 2 1 3D3V_VGA_S0 3 4 4 SMBC_Therm 27,28 84.2N702.A3F 2nd = 84.DM601.03F NV_VID1 NV_VID2 92 92 -VIDEO_THERM_OVERT -VIDEO_THERM_ALERT OPS (DG-05587-001_v03_p.177_Table 95) RN8607 2 22uF(X5R) M0805 ×1 L8602 BLM18PG181SN1D-GP OPS 4 3 92 SRN10KJ-5-GP NV_VID0 N13P_GPIO12_H7 1 1.05V ±30mV 90mA total 3D3V_VGA_S0 1 2 OPS 2 1 R8611 92 NV_VID5 1 2 1 2 SMBD_Therm 27,28 2N7002KDW-GP SMBD_Therm_NV 4.7uF(X5R) K0603 ×1 OPS C8604 100nF(X7R) K0402 ×2 OPS C8605 D PLLVDD_PWR 15 OF 17 VGA1O 11/17 XTAL_PLL OPS C8606 AD8 AE8 PLLVDD SP_PLLVDD AD7 NC VID_PLLVDD 10KR2J-3-GP GF117 GF108/GKx Near GPU GPIO Description (DG-05587-001_v03_p.82_Tale 98) Under GPU 3D3V_VGA_S0 VIDEO_CLK_XTAL_SS H1 PURE_HW_SHUTDOWN# N13P-GS-A1-GP -VIDEO_THERM_OVERT OPS-BOM CTRL GPU_VID4 GPU_VID3 LCD_BL_PWM LCD_VCC LCD_BLEN GPU_VID1 GPU_VID2 3D Vision OVERT ALERT MEM_VREF_CTL GPU_VID0 PWR_LEVEL GPU_VID5 HPD_AB HPD_C MEM_VDD_CTL HPD_D HPD_E HPD_F Reserved Reserved 27,28,36GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 S 2N7002K-2-GP 1st = 84.2N702.031 2ND = 84.2N702.J31 OPS Function Description O O O O O O O O I/O I/O O O I O I I O I I I GPU Core VDD VID4 GPU Core VDD VID3 Panel Backlught PWM Brightness Control Panel Power Enable panel Backlight Enale GPU Core VDD VID1 GPU Core VDD VID2 3D Vision Left/Right signal Active Low Thermal Catastrophic Over Temperature Active Low Thermal Alert Memory VREF Control GPU Core VDD VID0 AC Power Detect Input. High = AC, Low = Battery GPU Core VDD VID5 Hot Plog Detect for IFPAB Hot Plog Detect for IFPC Memory VDD VID Hot Plog Detect for IFPD Hot Plog Detect for IFPE Hot Plog Detect for IFPF R8601 10KR2J-3-GP H3 100nF 22uF X7R X7R Footprint XTAL_OUTBUFF Population Location 0402 0805 1 1 Under GPU Near GPU 0402 1 Near GPU XTAL_IN XTAL_OUT N12P_XTAL_OUTBUFF R8602 10KR2J-3-GP OPS OPS-BOM CTRL 20PF 5% 50V +/-0.25PF 0402 1 R8603 DY 2 1MR2F-GP R8604 0R2J-2-GP Bead Type X8601 XTAL-27MHZ-46-GP 30Ω(ESR=0.05) X7R J4 H2 N13P-GS-A1-GP OPS Capacitor Type XTAL_SSIN 1 PLL Power Rail Filter-PLL_VDD (DG-05587-001_v03_p.177_Table 96) 1 I/O PLL Power Rail Filter-SP_PLLVDD and VIDPLLVDD Combined (DG-05587-001_v03_p.178_Table 97) OPS X8601_GND 4 3 27MHZ_OUT_R 27MHZ_IN 1 2 X8601_GND (+/-15%、-55~125℃) 1 D 2 G 2 3V_VGA_S0_R 0R0402-PAD 2 Normal Function GPIO pin Name Q8602 1 R2813 2 92 92 2 5 3 1 6 2 C8607 SC12P50V2JN-3GP 82.30034.351 OPS 2 NV_VID4 NV_VID3 VGA_LBKLT_CTL VGA_LCDVDD_EN VGA_BLEN OPS 1 1 P6 M3 L6 P5 P7 L7 M7 N8 M1 M2 L1 M5 N3 M4 R8 P4 P1 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO16 GPIO20 GPIO21 10KR2J-3-GP R8636 0R2J-2-GP DY 2 R8623 2 C8608 SC15P50V2JN-2-GP OPS 1 Q8601 SMBC_Therm_NV DY 1 SCD1U10V2KX-5GP 4 3 SRN10KJ-5-GP 1 2 R8620 10KR2J-3-GP OPS OPS 1 2 JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST# 1 RN8603 THERMDP OPS C8602 2 OPS N13P_TCK AM10 N13P_TMS AP11 N13P_TDI AM11 N13P_TDO AP12 N13P_TRST AN11 2 1 D 2 DY 10KR2J-3-GP PLLVDD OPS C8601 SCD1U10V2KX-5GP 1 1 1 1 100nF(X7R) K0402 ×1 2 OPS RN8605 SRN4K7J-8-GP R8619 TP8603 TP8604 TP8605 22uF(X5R) M0805 ×1 ( L8601 BLM18KG300TN1D-GP SCD1U10V2KX-5GP K3 I2CB_SCL I2CB_SDA THERMDN 1 1 K4 1.05V ±30mV 60mA I2CA=>CRT, I2CC=>LVDS. 3 4 I2CC_SCL I2CC_SDA (DG-05587-001_v03_p.177_Table 95) 3D3V_VGA_S0 2 I2CB_SCL_G3 I2CB_SDA_G2 OPS SC4D7U6D3V3KX-GP R7 R6 RN8604 SRN2K2J-1-GP OPS 2 1 R2 R3 GPU_LVDS_CLK GPU_LVDS_DATA RN8606 SRN2K2J-1-GP 2 1 SMBC_Therm_NV SMBD_Therm_NV SC4D7U6D3V3KX-GP T4 T3 2 1 I2CS_SCL I2CS_SDA ( 3 4 1D05V_VGA_S0 17 OF 17 VGA1Q 10/19 MISC1 OPS R8636 is reserved for Metal Xtal Capacitor Type 100nF 4.7uF 22uF X7R X7R X7R Footprint Population SPEC. (DG-05587-001_v03_p.176) XTALOUTBUFF signal should be pull down using a 10kΩ resistor. XTALSSIN signal should be pull down using a 10kΩ resistor. REmember to place components as close ti the GPU as possible. Location 0402 0402 0805 2 1 1 Under GPU Near GPU Near GPU 0603 1 Near GPU Bead Type 180Ω(ESR=0.2) C X7R SPEC. (DG-05587-001_v03_p.162) Adding a pull down to the DACA_VDD with a 10kΩ resistor to GND. All other DAC I/O pins (including DACA_VREF, DACA_REST) can be left floating. 3D3V_VGA_S0 3D3V_VGA_S0 1 1 R4 R5 VGA_CRT_DDCCLK VGA_CRT_DDCDATA AM9 AN9 VGA_CRT_HSYNC VGA_CRT_VSYNC ROM_CS# TSEN_VREF DACA_RSET NC NC NC R8625 10KR2F-2-GP DACA_HSYNC DACA_VSYNC NC DACA_RED NC DACA_GREEN NC DACA_BLUE H6 STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 TP8611 TP8612 1 1 AK9 VGA_CRT_RED 1 TP8613 AL10 VGA_CRT_GREEN 1 TP8614 AL9 VGA_CRT_BLUE J2 J7 J6 J5 J3 STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 ROM_SI ROM_SO ROM_SCLK H5 H7 H4 ROM_SI_H5 ROM_SO_H7 ROM_SLK_H4 R8618 15KR2F-GP R8617 30KR2F-GP R8627 15KR2F-GP BUFRST# OPS-BOM CTRL GPU SKU Phase Count Target N13M-GE1 N13M-GS N13P-GL N13P-GS Single phase Two phase Two phase Two phase DY 1 I2CA_SCL I2CA_SDA OPS-BOM CTRL 2 DACA_VREF GF108/GKx 2 NC NC 2 2 GF117 NC Recommended NVVDD Voltage Regulator Phase Coount OPS-BOM CTRL 1 2 OPS R8626 15KR2F-GP OPS-BOM CTRL 29 x 29 PACKAGE V: N13P-GS/GL (25~30W) B: N13M-GS/GE (15~20W) 2 AP8 DY 1 AP9 1DACA_RSET R8624 2KR2F-3-GP 2 1DACA_VREF GF117 DACA_VDD 1 R8629 TP8620 10KR2J-3-GP TP8621 OPS AG10 16 OF 17 2 1 GF108/GKx DACA_VDD 1 3 4 The GB4-128 package is available in a 29 mm × 29mm footprint. 128-bit memory interfaces respectively. VGA1P 12/17 MISC2 RN8601 SRN2K2J-1-GP 14 OF 17 VGA1N 4/17 DACA C (+/-15%、-55~125℃) L2 1 N13P-GS-A1-GP RN8602 VGA_CRT_BLUE VGA_CRT_GREEN VGA_CRT_RED 1 2 3 4 MULTI_STRAP_REF2_GND J1 MULTI_STRAP_REF0_GND CEC L3 128Mx16: OPS 8 7 6 5 3D3V_VGA_S0 R8313 40K2R2F-GP R8628 CEC_L3 2 OPS-BOM CTRL 1 hynix - H5TQ2G63BFR-11C Samsung - K4W2G1646C-HC11 2 10KR2F-2-GP SRN75J-1-GP N13P-GS-A1-GP OPS SPEC. (DG-05587-001_v03_p.191_Table 102) CTRL Multi_Strap_Ref0_GND 40.2kΩ 1% toOPS-BOM GND B OPS-BOM CTRL L3 N13P-GL N13M_GE1 N13M-GS N13P-GS TABLE 900MHz ROM_SI PD R8627 30Kohm 64.30025.6DL R8631 2KR2F-3-GP B VIDEO MEMORY HYNIX 64Mx16 0010 Samsung 64Mx16 0011 HYNIX 128Mx16 0110 SAMSUNG 128Mx16 0111 72.52G63.A0U 72.42164.D0U 72.51G63.H0U 1-007155 1-007156 1-007157 1-007356 34.8Kohm 64.34825.6DL 45.3Kohm 64.45325.6DL 15Kohm 64.15025.6DL 20Kohm 64.20025.6DL 72.41164.Q0U 1 1 1 2 OPS-BOM CTRL R8314 45K3R2F-L-GP R8316 34K8R2F-1-GP DY DY 2 DY DY 1 DY OPS STRAP0 STRAP1 STRAP2 2 64.15025.6DL Hynix - H5TQ1G63DFR-11C Samsung - K4W1G1646G-BC11 3D3V_VGA_S0 1 64.45325.6DL 20100702_NV 64Mx16: STRAP3 STRAP4 DY R8633 34K8R2F-1-GP R8635 30KR2F-GP R8315 5K1R2F-2-GP R8317 20KR2F-L-GP OPS-BOM CTRL DY OPS-BOM CTRL OPS-BOM CTRL 2 R8635 DY R8634 45K3R2F-L-GP 2 R8634 15Kohm R8632 34K8R2F-1-GP 1 STRAP2 DY 45Kohm R8630 45K3R2F-L-GP 2 64.34825.6DL 1 35Kohm 64.34825.6DL 64.34825.6DL 2 35Kohm R8633 3D3V_VGA_S0 35Kohm 1 DY 2 DY 1 R8632 N12M-GE DEV ID: 0xA7A 1010 2 N12P-GV DEV ID: 0x0DF7(ES) 1 N12P-GE DEV ID: 0xDF5 0101 2 STRAP1 TABLE NVIDIA (DA-05691-001_v04_p.3_Table 2) 10kΩ pull-up to 3.3V NC NC NC A A <Core Design> Wistron Corporation 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title N13P_GPU (4/5): GPIO/STRAP Size A1 Document Number Date: Friday, January 06, 2012 Rev SD LA48 Sheet 86 of 103 DY C8722 OPS SC4D7U6D3V3KX-GP 2 1 SC4D7U6D3V3KX-GP 2 1 SC4D7U6D3V3KX-GP 2 1 SC4D7U6D3V3KX-GP 2 1 C8721 C8714 OPS C8708 OPS C8715 DY C8723 22uF(X5R) M0805 ×1 SC22U6D3V5MX-2GP 2 1 Under GPU OPS 47uF(X5R) M0805 ×1 C8724 4.7uF(X5R) K0805 ×5 B 2 6 OF 17 VGA1F 13/17 NVVDD AA12 AA14 AA16 AA19 AA21 AA23 AB13 AB15 AB17 AB18 AB20 AB22 AC12 AC14 AC16 AC19 AC21 AC23 M12 M14 M16 M19 M21 M23 N13 N15 N17 N18 N20 N22 P12 P14 P16 P19 P21 P23 R13 R15 R17 R18 R20 R22 T12 T14 T16 T19 T21 T23 U13 U15 U17 U18 U20 U22 V13 V15 V17 V18 V20 V22 W12 W14 W16 W19 W21 W23 Y13 Y15 Y17 Y18 Y20 Y22 OPS SCD1U10V2KX-5GP 2 1 OPS C8707 SC4D7U6D3V3KX-GP 2 1 C8720 C8713 OPS DY OPS SCD1U10V2KX-5GP 2 1 DY SC4D7U6D3V3KX-GP 2 1 SC4D7U6D3V3KX-GP 2 1 C8719 C8712 DY C8706 SC4D7U6D3V3KX-GP 2 1 C8718 OPS C8705 SCD1U10V2KX-5GP 2 1 C8717 C8711 OPS DY OPS SC4D7U6D3V3KX-GP 2 1 DY C8710 DY C8704 3 VGA_CORE SCD1U10V2KX-5GP 2 1 C C8716 C8709 C8703 SC4D7U6D3V3KX-GP 2 1 OPS 0.1uF(X7R) K0402 ×8 SCD1U10V2KX-5GP 2 1 SCD1U10V2KX-5GP 2 1 OPS OPS SCD1U10V2KX-5GP 2 1 C8702 SC4D7U6D3V3KX-GP 2 1 DY SC4D7U6D3V3KX-GP 2 1 SC4D7U6D3V3KX-GP 2 1 D C8701 SCD1U10V2KX-5GP 2 1 OPS 4.7uF(X5R) K0603 ×15 SC4D7U6D3V3KX-GP 2 1 4 SC4D7U6D3V3KX-GP 2 1 5 NVVDD Decoupling Requirement (DG-05587-001_v03_p.56_Table 7) 15/17 GND_1/2 GND_1 GND_71 GND_5 GND_72 GND_6 GND_73 GND_7 GND_74 GND_8 GND_75 GND_9 GND_76 GND_10 GND_77 GND_11 GND_78 GND_12 GND_79 GND_13 GND_80 GND_14 GND_81 GND_2 GND_82 GND_15 GND_83 GND_16 GND_84 GND_17 GND_85 GND_18 GND_86 GND_19 GND_87 GND_20 GND_88 GND_21 GND_89 GND_22 GND_90 GND_23 GND_91 GND_24 GND_92 GND_3 GND_93 GND_25 GND_94 GND_26 GND_95 GND_27 GND_96 GND_28 GND_97 GND_29 GND_98 GND_30 GND_99 GND_31 GND_100 GND_32 GND_101 GND_33 GND_102 GND_34 GND_103 GND_4 GND_104 GND_35 GND_105 GND_36 GND_106 GND_37 GND_107 GND_38 GND_108 GND_39 GND_109 GND_40 GND_110 GND_41 GND_111 GND_42 GND_112 GND_43 GND_113 GND_44 GND_114 GND_45 GND_115 GND_46 GND_116 GND_47 GND_117 GND_48 GND_118 GND_49 GND_119 GND_50 GND_120 GND_51 GND_121 GND_52 GND_122 GND_53 GND_123 GND_54 GND_124 GND_55 GND_125 GND_56 GND_126 GND_57 GND_127 GND_58 GND_128 GND_59 GND_129 GND_60 GND_130 GND_61 GND_131 GND_62 GND_132 GND_63 GND_133 GND_64 GND_134 GND_65 GND_135 GND_66 GND_136 GND_67 GND_137 GND_68 GND_138 GND_69 GND_139 GND_70 GND_140 A2 AA17 AA18 AA20 AA22 AB12 AB14 AB16 AB19 AB2 AB21 A33 AB23 AB28 AB30 AB32 AB5 AB7 AC13 AC15 AC17 AC18 AA13 AC20 AC22 AE2 AE28 AE30 AE32 AE33 AE5 AE7 AH10 AA15 AH13 AH16 AH19 AH2 AH22 AH24 AH28 AH29 AH30 AH32 AH33 AH5 AH7 AJ7 AK10 AK7 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 AL24 AL26 AL28 AL30 AL32 AL33 AL5 AM13 AM16 AM19 AM22 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 VDD_72 AM25 AN1 AN10 AN13 AN16 AN19 AN22 AN25 AN30 AN34 AN4 AN7 AP2 AP33 B1 B10 B22 B25 B28 B31 B34 B4 B7 C10 C13 C19 C22 C25 C28 C7 D2 D31 D33 E10 E22 E25 E5 E7 F28 F7 G10 G13 G16 G19 G2 G22 G25 G28 G3 G30 G32 G33 G5 G7 K2 K28 K30 K32 K33 K5 K7 M13 M15 M17 M18 M20 M22 N12 N14 N16 A AG11 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198 GND_F GND_H GND_OPT_1 GND_OPT_2 1uF(X5R) K0402 ×2 4.uF(X5R) K0603 ×2 7 OF 17 VGA1G 17/17 NC/VDD33 AC6 AJ28 AJ4 AJ5 AL11 C15 D19 D20 D23 D26 H31 T8 V32 NC#AC6 NC#AJ28 NC#AJ4 NC#AJ5 NC#AL11 NC#C15 NC#D19 NC#D20 NC#D23 NC#D26 NC#H31 NC#T8 NC#V32 VDD33_1 VDD33_2 VDD33_3 VDD33_4 J8 K8 L8 M8 OPS C8731 OPS C8732 Under GPU T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W13 W15 W17 W18 W20 W22 W28 Y12 Y14 Y16 Y19 Y21 Y23 CONFIGURABLE POWER CHANNELS AH11 C16 W32 Optional CMD GNDs (2) NC for 4-Lyr cards N13P-GS-A1-GP OPS-BOM CTRL XVDD_1 XVDD_2 XVDD_3 XVDD_4 XVDD_5 XVDD_6 XVDD_7 XVDD_8 U1 U2 U3 U4 U5 U6 U7 U8 XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15 XVDD_16 V1 V2 V3 V4 V5 V6 V7 V8 XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22 W2 W3 W4 W5 W7 W8 XVDD_23 XVDD_24 XVDD_25 XVDD_26 XVDD_27 XVDD_28 XVDD_29 XVDD_30 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 XVDD_31 XVDD_32 XVDD_33 XVDD_34 XVDD_35 XVDD_36 XVDD_37 XVDD_38 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 D C N13P-GS-A1-GP OPS-BOM CTRL B Capacitor Type 0.1uF(X7R) K0402 ×3 OPS C8733 OPS C8734 Near GPU OPS C8735 SC4D7U6D3V3KX-GP 2 1 Under GPU Under GPU Near GPU Near GPU Near GPU SC1U6D3V2KX-GP 2 1 10 4 1 1 5 N19 N2 N21 N23 N28 N30 N32 N33 N5 N7 P13 P15 P17 P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18 T2 T20 T22 5 OF 17 VDD33 Decoupling (DG-05587-001_v03_p.57_Table 8) SC1U6D3V2KX-GP 2 1 (+/-15%、-55~125℃) (+/-22%、-55~105℃) (+/-15%、-55~85℃) 15 8 1 1 5 SCD1U10V2KX-5GP 2 1 0603 0402 0805 0805 0805 16/17 GND_2/2 OPS-BOM CTRL Location SCD1U10V2KX-5GP 2 1 X7R X6S X5R X6S X7R X5R X5R X5R Population VGA1E 9/17 XVDD N13P-GS-A1-GP N13P-GS-A1-GP SCD1U10V2KX-5GP 2 1 4.7uF 0.1uF 47uF 22uF 4.7uF Footprint 8 OF 17 VGA1H OPS-BOM CTRL Capacitor Type 1 9 OF 17 VGA1I OPS C8736 Footprint Population Location 3D3V_VGA_S0 0.1uF 1uF 4.7uF X7R X5R 0402 0402 0603 X7R X5R X5R 3 2 1 Under GPU Near GPU Near GPU 3 2 1 (+/-15%、-55~125℃) (+/-15%、-55~85℃) A <Core Design> Wistron Corporation 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih, Taipei Hsien 221, Taiwan, R.O.C N13P-GS-A1-GP OPS-BOM CTRL Title N13P_GPU (5/5): PWR/GND Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA48 Sheet 87 of 103 A B C D E VIDEO FRAME BUFFER PORT A 1D5V_VGA_S0 1D5V_VGA_S0 VRAM1 FBA_D[63..0] A8 A1 C1 C9 D2 E9 F1 H9 H2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VRAM_CH_A_ZQ_1 H1 M8 L8 VREFDQ VREFCA ZQ 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 FBA_A0 FBA_A1 FBA_A2 FBA_A3 FBA_A4 FBA_A5 FBA_A6 FBA_A7 FBA_A8 FBA_A9 FBA_A10 FBA_A11 FBA_A12 FBA_A13 FBA_A15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 FB CMD mapping85,89 85,89 Mode D-N13x 85,89 FBA_BA0 FBA_BA1 FBA_BA2 M2 N8 M3 BA0 BA1 BA2 85 85 FBA_CLK0 FBA_CLK0# J7 K7 CK CK# 85 FBA_CKE0 K9 CKE FBA_DQM0 FBA_DQM1 D3 E7 DMU DML 85,89 FBA_W E# 85,89 FBA_CAS# 85,89 FBA_RAS# L3 K3 J3 WE# CAS# RAS# 4 243R2F-2-GP 2 1 FBA_VREF_0 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 FBA_D11 FBA_D13 FBA_D9 FBA_D12 FBA_D8 FBA_D15 FBA_D10 FBA_D14 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 FBA_D3 FBA_D5 FBA_D0 FBA_D6 FBA_D2 FBA_D7 FBA_D1 FBA_D4 DQSU DQSU# C7 B7 DQSL DQSL# F3 G3 ODT K1 OPS R8801 3 85 85 CS# RESET# L2 T2 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 VRAM2 FBA_DQS_W P0 85 FBA_DQS_RN0 85 FBA_VREF_0 FBA_DQS_W P1 85 FBA_DQS_RN1 85 FBA_ODT0 FBA_CS0# FBA_RST 243R2F-2-GP 1 VDD VDD VDD VDD VDD VDD VDD VDD VDD VRAM_CH_A_ZQ_2 K8 K2 N1 R9 B2 D9 G7 R1 N9 VDD VDD VDD VDD VDD VDD VDD VDD VDD A8 A1 C1 C9 D2 E9 F1 H9 H2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ H1 M8 L8 VREFDQ VREFCA ZQ OPS 85 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 85,89 FBA_A0 FBA_A1 FBA_A2 FBA_A3 FBA_A4 FBA_A5 FBA_A6 FBA_A7 FBA_A8 FBA_A9 FBA_A10 FBA_A11 FBA_A12 FBA_A13 FBA_A15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 FB CMD mapping85,89 85,89 Mode D-N13x 85,89 FBA_BA0 FBA_BA1 FBA_BA2 M2 N8 M3 BA0 BA1 BA2 85 85 FBA_CLK0 FBA_CLK0# J7 K7 CK CK# 85 FBA_CKE0 K9 CKE FBA_DQM3 FBA_DQM2 D3 E7 DMU DML 85,89 FBA_W E# 85,89 FBA_CAS# 85,89 FBA_RAS# L3 K3 J3 WE# CAS# RAS# 85 85,89 2 K8 K2 N1 R9 B2 D9 G7 R1 N9 85,89 R8802 85 85 FBA_D[63..0] DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 FBA_D23 FBA_D22 FBA_D21 FBA_D20 FBA_D16 FBA_D17 FBA_D18 FBA_D19 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 FBA_D26 FBA_D25 FBA_D31 FBA_D28 FBA_D29 FBA_D27 FBA_D30 FBA_D24 DQSU DQSU# C7 B7 FBA_DQS_W P3 85 FBA_DQS_RN3 85 DQSL DQSL# F3 G3 FBA_DQS_W P2 85 FBA_DQS_RN2 85 ODT K1 FBA_ODT0 85 CS# RESET# L2 T2 FBA_CS0# FBA_RST 85 85,89 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 85,89 128 X 16 72.52G63.A0U 72.42164.D0U IC VRAM K4W2G1646C-HC11 FBGA96 64 X 16 72.51G63.H0U 72.41646.Q0U IC VRAM H5TQ1G63DFR-11C FBGA 96BALLS IC VRAM K4W1G1646G-BC11 FBGA 96BALLS 4 3 128Mx16: H5TQ1G63BFR-12C-GP H5TQ1G63BFR-12C-GP BOM CTRL BOM CTRL hynix - H5TQ2G63BFR-11C Samsung - K4W2G1646C-HC11 64Mx16: Hynix - H5TQ1G63DFR-11C Samsung - K4W1G1646G-BC11 2 2 Combined Memory FBVDD/Q Decoupling DDR3×16 with Clamshell Layout (DG-05587-001_v03_p.87_Table 23) 1D5V_VGA_S0 OPS OPS C8802 C8803 SCD1U10V2KX-5GP 2 1 C8801 SCD1U10V2KX-5GP 2 1 OPS SCD1U10V2KX-5GP 2 1 SCD1U10V2KX-5GP 2 1 Capacitor Type 0.1uF 1uF OPS Footprint X7R X7R Population 4 8 0402 0603 Location Close to VRAM Close to VRAM 1D5V_VGA_S0 C8804 X7R (+/-15%、-55~125℃) *Per clamshell pair 1K33R2F-GP 1 0.1uF(X7R) K0402 ×4 OPS R8803 2 1.0uF(X7R) K0603 ×8 C8811 OPS OPS C8812 R8804 SCD01U50V2KX-1GP 2 1 C8810 1K33R2F-GP 1 C8809 OPS 2 C8808 OPS SC1U6D3V3KX-2GP 2 1 C8807 OPS SC1U6D3V3KX-2GP 2 1 C8806 OPS SC1U6D3V3KX-2GP 2 1 OPS SC1U6D3V3KX-2GP 2 1 OPS SC1U6D3V3KX-2GP 2 1 C8805 SC1U6D3V3KX-2GP 2 1 OPS SC1U6D3V3KX-2GP 2 1 1 SC1U6D3V3KX-2GP 2 1 FBA_VREF_0 <Core Design> OPS C8813 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CHANNEL-A_VRAM1,2 (1/4) Size A3 Close to VRAM(For VRAM1 & VRAM2) Date: A B C D Document Number LA48 Friday, January 06, 2012 Rev SD Sheet E 88 of 103 A B C D E VIDEO FRAME BUFFER PORT A 1D5V_VGA_S0 1D5V_VGA_S0 VRAM3 FBA_D[63..0] VDD VDD VDD VDD VDD VDD VDD VDD VDD A8 A1 C1 C9 D2 E9 F1 H9 H2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VRAM_CH_A_ZQ_3 H1 M8 L8 VREFDQ VREFCA ZQ 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 FBA_A0 FBA_A1 FBA_A2 FBA_A3 FBA_A4 FBA_A5 FBA_A6 FBA_A7 FBA_A8 FBA_A9 FBA_A10 FBA_A11 FBA_A12 FBA_A13 FBA_A15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 FB CMD mapping85,88 85,88 Mode D-N13x 85,88 FBA_BA0 FBA_BA1 FBA_BA2 M2 N8 M3 BA0 BA1 BA2 85 85 FBA_CLK1 FBA_CLK1# J7 K7 CK CK# 85 FBA_CKE1 K9 CKE FBA_DQM6 FBA_DQM4 D3 E7 DMU DML 85,88 FBA_W E# 85,88 FBA_CAS# 85,88 FBA_RAS# L3 K3 J3 WE# CAS# RAS# 4 243R2F-2-GP 1 FBA_VREF_1 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 FBA_D35 FBA_D38 FBA_D33 FBA_D34 FBA_D32 FBA_D37 FBA_D36 FBA_D39 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 FBA_D49 FBA_D54 FBA_D48 FBA_D55 FBA_D51 FBA_D53 FBA_D50 FBA_D52 DQSU DQSU# C7 B7 DQSL DQSL# F3 G3 ODT K1 OPS 3 85 85 CS# RESET# L2 T2 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 FBA_DQS_W P6 85 FBA_DQS_RN6 85 FBA_VREF_1 FBA_DQS_W P4 85 FBA_DQS_RN4 85 FBA_ODT1 FBA_CS1# FBA_RST VRAM_CH_A_ZQ_4 K8 K2 N1 R9 B2 D9 G7 R1 N9 VDD VDD VDD VDD VDD VDD VDD VDD VDD A8 A1 C1 C9 D2 E9 F1 H9 H2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ H1 M8 L8 VREFDQ VREFCA ZQ OPS 85 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 85,88 FBA_A0 FBA_A1 FBA_A2 FBA_A3 FBA_A4 FBA_A5 FBA_A6 FBA_A7 FBA_A8 FBA_A9 FBA_A10 FBA_A11 FBA_A12 FBA_A13 FBA_A15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 FB CMD mapping85,88 85,88 Mode D-N13x 85,88 FBA_BA0 FBA_BA1 FBA_BA2 M2 N8 M3 BA0 BA1 BA2 85 85 FBA_CLK1 FBA_CLK1# J7 K7 CK CK# 85 FBA_CKE1 K9 CKE FBA_DQM7 FBA_DQM5 D3 E7 DMU DML 85,88 FBA_W E# 85,88 FBA_CAS# 85,88 FBA_RAS# L3 K3 J3 WE# CAS# RAS# 85 85,88 R8902 2 2 R8901 VRAM4 243R2F-2-GP 1 K8 K2 N1 R9 B2 D9 G7 R1 N9 85,88 85 85 FBA_D[63..0] DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 FBA_D44 FBA_D43 FBA_D47 FBA_D45 FBA_D42 FBA_D40 FBA_D46 FBA_D41 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 FBA_D56 FBA_D62 FBA_D61 FBA_D60 FBA_D57 FBA_D59 FBA_D58 FBA_D63 DQSU DQSU# C7 B7 FBA_DQS_W P7 85 FBA_DQS_RN7 85 DQSL DQSL# F3 G3 FBA_DQS_W P5 85 FBA_DQS_RN5 85 ODT K1 FBA_ODT1 85 CS# RESET# L2 T2 FBA_CS1# FBA_RST 85 85,88 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 85,88 4 3 H5TQ1G63BFR-12C-GP H5TQ1G63BFR-12C-GP BOM CTRL BOM CTRL 2 2 Combined Memory FBVDD/Q Decoupling DDR3×16 with Clamshell Layout (DG-05587-001_v03_p.87_Table 23) 1D5V_VGA_S0 OPS OPS C8902 C8903 SCD1U10V2KX-5GP 2 1 C8901 SCD1U10V2KX-5GP 2 1 OPS SCD1U10V2KX-5GP 2 1 SCD1U10V2KX-5GP 2 1 Capacitor Type 0.1uF 1uF OPS Footprint X7R X7R Population 0402 0603 4 8 Location Close to VRAM Close to VRAM 1D5V_VGA_S0 C8904 X7R (+/-15%、-55~125℃) *Per clamshell pair 1K33R2F-GP 1 0.1uF(X7R) K0402 ×4 OPS R8903 2 1.0uF(X7R) K0603 ×8 C8911 OPS OPS C8912 R8904 SCD01U50V2KX-1GP 2 1 C8910 1K33R2F-GP 1 C8909 OPS 2 C8908 OPS SC1U6D3V3KX-2GP 2 1 C8907 OPS SC1U6D3V3KX-2GP 2 1 C8906 OPS SC1U6D3V3KX-2GP 2 1 OPS SC1U6D3V3KX-2GP 2 1 OPS SC1U6D3V3KX-2GP 2 1 C8905 SC1U6D3V3KX-2GP 2 1 OPS SC1U6D3V3KX-2GP 2 1 1 SC1U6D3V3KX-2GP 2 1 FBA_VREF_1 <Core Design> OPS C8913 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CHANNEL-A_VRAM3,4 (2/4) Size A3 Close to VRAM(For VRAM3 & VRAM4) Date: A B C D Document Number LA48 Friday, January 06, 2012 Rev SD Sheet E 89 of 103 A B C D VIDEO FRAME BUFFER PORT C VRAM5 VDD VDD VDD VDD VDD VDD VDD VDD VDD A8 A1 C1 C9 D2 E9 F1 H9 H2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 4 243R2F-2-GP 1 FBB_VREF_0 H1 M8 L8 VRAM_CH_C_ZQ_1 VREFDQ VREFCA ZQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 FBB_D1 FBB_D3 FBB_D0 FBB_D2 FBB_D5 FBB_D4 FBB_D7 FBB_D6 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 FBB_D13 FBB_D11 FBB_D14 FBB_D10 FBB_D12 FBB_D8 FBB_D15 FBB_D9 DQSU DQSU# C7 B7 DQSL DQSL# F3 G3 ODT K1 FBB_ODT0 85 CS# RESET# L2 T2 FBB_CS0# FBB_RST 85 85,91 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 OPS 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 FBB_A0 FBB_A1 FBB_A2 FBB_A3 FBB_A4 FBB_A5 FBB_A6 FBB_A7 FBB_A8 FBB_A9 FBB_A10 FBB_A11 FBB_A12 FBB_A13 FBB_A15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 FB CMD mapping85,91 85,91 Mode D-N13x 85,91 FBB_BA0 FBB_BA1 FBB_BA2 M2 N8 M3 BA0 BA1 BA2 85 85 FBB_CLK0 FBB_CLK0# J7 K7 CK CK# 85 FBB_CKE0 K9 2 R9001 3 CKE FBB_DQM1 FBB_DQM0 D3 E7 DMU DML 85,91 FBB_W E# 85,91 FBB_CAS# 85,91 FBB_RAS# L3 K3 J3 WE# CAS# RAS# 85 85 1D5V_VGA_S0 85,91 FBB_DQS_W P1 85 FBB_DQS_RN1 85 FBB_VREF_0 VRAM_CH_C_ZQ_2 FBB_DQS_W P0 85 FBB_DQS_RN0 85 243R2F-2-GP 1 K8 K2 N1 R9 B2 D9 G7 R1 N9 FBB_D[63..0] VRAM6 K8 K2 N1 R9 B2 D9 G7 R1 N9 VDD VDD VDD VDD VDD VDD VDD VDD VDD A8 A1 C1 C9 D2 E9 F1 H9 H2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ H1 M8 L8 VREFDQ VREFCA ZQ FBB_D[63..0] OPS 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 85,91 FBB_A0 FBB_A1 FBB_A2 FBB_A3 FBB_A4 FBB_A5 FBB_A6 FBB_A7 FBB_A8 FBB_A9 FBB_A10 FBB_A11 FBB_A12 FBB_A13 FBB_A15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 FB CMD mapping85,91 85,91 Mode D-N13x 85,91 FBB_BA0 FBB_BA1 FBB_BA2 M2 N8 M3 BA0 BA1 BA2 85 85 FBB_CLK0 FBB_CLK0# J7 K7 CK CK# 85 FBB_CKE0 K9 CKE 85 85 FBB_DQM2 FBB_DQM3 D3 E7 DMU DML 85,91 FBB_W E# 85,91 FBB_CAS# 85,91 FBB_RAS# L3 K3 J3 WE# CAS# RAS# R9002 2 1D5V_VGA_S0 E DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 FBB_D29 FBB_D31 FBB_D28 FBB_D24 FBB_D27 FBB_D30 FBB_D25 FBB_D26 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 FBB_D20 FBB_D17 FBB_D23 FBB_D18 FBB_D21 FBB_D16 FBB_D22 FBB_D19 DQSU DQSU# C7 B7 FBB_DQS_W P2 85 FBB_DQS_RN2 85 DQSL DQSL# F3 G3 FBB_DQS_W P3 85 FBB_DQS_RN3 85 ODT K1 FBB_ODT0 85 CS# RESET# L2 T2 FBB_CS0# FBB_RST 85 85,91 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 85,91 4 3 H5TQ1G63BFR-12C-GP H5TQ1G63BFR-12C-GP BOM CTRL BOM CTRL 2 2 Combined Memory FBVDD/Q Decoupling DDR3×16 with Clamshell Layout (DG-05587-001_v03_p.87_Table 23) 1D5V_VGA_S0 OPS OPS C9002 C9003 SCD1U10V2KX-5GP 2 1 C9001 SCD1U10V2KX-5GP 2 1 OPS SCD1U10V2KX-5GP 2 1 SCD1U10V2KX-5GP 2 1 Capacitor Type 0.1uF 1uF OPS Footprint X7R X7R Population 0402 0603 4 8 Location Close to VRAM Close to VRAM 1D5V_VGA_S0 C9004 X7R (+/-15%、-55~125℃) *Per clamshell pair 1K33R2F-GP 1 0.1uF(X7R) K0402 ×4 OPS R9003 2 1.0uF(X7R) K0603 ×8 C9011 OPS OPS C9012 R9004 SCD01U50V2KX-1GP 2 1 C9010 1K33R2F-GP 1 C9009 OPS 2 C9008 OPS SC1U6D3V3KX-2GP 2 1 C9007 OPS SC1U6D3V3KX-2GP 2 1 C9006 OPS SC1U6D3V3KX-2GP 2 1 OPS SC1U6D3V3KX-2GP 2 1 OPS SC1U6D3V3KX-2GP 2 1 C9005 SC1U6D3V3KX-2GP 2 1 OPS SC1U6D3V3KX-2GP 2 1 1 SC1U6D3V3KX-2GP 2 1 FBB_VREF_0 <Core Design> OPS C9013 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Close to VRAM(For VRAM5 & VRAM6) Date: A B C 1 D CHANNEL-C_VRAM5,6 (3/4) Document Number LA48 Friday, January 06, 2012 Rev SD Sheet E 90 of 103 B 1D5V_VGA_S0 VRAM7 K8 K2 N1 R9 B2 D9 G7 R1 N9 4 243R2F-2-GP 1 FBB_VREF_1 VRAM_CH_C_ZQ_3 FBB_D[63..0] DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 FBB_D35 FBB_D37 FBB_D32 FBB_D39 FBB_D36 FBB_D38 FBB_D33 FBB_D34 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 FBB_D51 FBB_D53 FBB_D48 FBB_D54 FBB_D49 FBB_D55 FBB_D50 FBB_D52 DQSU DQSU# C7 B7 FBB_DQS_W P6 85 FBB_DQS_RN6 85 DQSL DQSL# F3 G3 FBB_DQS_W P4 85 FBB_DQS_RN4 85 ODT K1 CS# RESET# L2 T2 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 VDD VDD VDD VDD VDD VDD VDD VDD VDD A8 A1 C1 C9 D2 E9 F1 H9 H2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ H1 M8 L8 VREFDQ VREFCA ZQ OPS 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 FBB_A0 FBB_A1 FBB_A2 FBB_A3 FBB_A4 FBB_A5 FBB_A6 FBB_A7 FBB_A8 FBB_A9 FBB_A10 FBB_A11 FBB_A12 FBB_A13 FBB_A15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 FB CMD mapping85,90 85,90 Mode D-N13x 85,90 FBB_BA0 FBB_BA1 FBB_BA2 M2 N8 M3 BA0 BA1 BA2 85 85 FBB_CLK1 FBB_CLK1# J7 K7 CK CK# 85 FBB_CKE1 K9 CKE 2 R9101 3 FBB_DQM6 FBB_DQM4 D3 E7 DMU DML 85,90 FBB_W E# 85,90 FBB_CAS# 85,90 FBB_RAS# L3 K3 J3 WE# CAS# RAS# 85 85 C D 1D5V_VGA_S0 85,90 FBB_ODT1 FBB_CS1# FBB_RST FBB_VREF_1 VRAM_CH_C_ZQ_4 85 FBB_D[63..0] VDD VDD VDD VDD VDD VDD VDD VDD VDD A8 A1 C1 C9 D2 E9 F1 H9 H2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ H1 M8 L8 VREFDQ VREFCA ZQ OPS 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 85,90 FBB_A0 FBB_A1 FBB_A2 FBB_A3 FBB_A4 FBB_A5 FBB_A6 FBB_A7 FBB_A8 FBB_A9 FBB_A10 FBB_A11 FBB_A12 FBB_A13 FBB_A15 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A15 FB CMD mapping85,90 85,90 Mode D-N13x 85,90 FBB_BA0 FBB_BA1 FBB_BA2 M2 N8 M3 BA0 BA1 BA2 85 85 FBB_CLK1 FBB_CLK1# J7 K7 CK CK# 85 FBB_CKE1 K9 CKE 85 85 FBB_DQM5 FBB_DQM7 D3 E7 DMU DML 85,90 FBB_W E# 85,90 FBB_CAS# 85,90 FBB_RAS# L3 K3 J3 WE# CAS# RAS# 85 85,90 R9102 E VRAM8 K8 K2 N1 R9 B2 D9 G7 R1 N9 VIDEO FRAME BUFFER PORT C 243R2F-2-GP 2 1 A DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 FBB_D60 FBB_D58 FBB_D62 FBB_D57 FBB_D63 FBB_D59 FBB_D61 FBB_D56 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 FBB_D40 FBB_D47 FBB_D41 FBB_D44 FBB_D42 FBB_D46 FBB_D43 FBB_D45 DQSU DQSU# C7 B7 FBB_DQS_W P5 85 FBB_DQS_RN5 85 DQSL DQSL# F3 G3 FBB_DQS_W P7 85 FBB_DQS_RN7 85 ODT K1 FBB_ODT1 85 CS# RESET# L2 T2 FBB_CS1# FBB_RST 85 85,90 NC#T7 NC#L9 NC#L1 NC#J9 NC#J1 T7 L9 L1 J9 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ G1 F9 E8 E2 D8 D1 B9 B1 G9 85,90 4 3 H5TQ1G63BFR-12C-GP H5TQ1G63BFR-12C-GP BOM CTRL BOM CTRL 2 2 Combined Memory FBVDD/Q Decoupling DDR3×16 with Clamshell Layout (DG-05587-001_v03_p.87_Table 23) 1D5V_VGA_S0 OPS OPS C9102 C9103 SCD1U10V2KX-5GP 2 1 C9101 SCD1U10V2KX-5GP 2 1 OPS SCD1U10V2KX-5GP 2 1 SCD1U10V2KX-5GP 2 1 Capacitor Type 0.1uF 1uF OPS Footprint X7R X7R Population 0402 0603 4 8 Location Close to VRAM Close to VRAM 1D5V_VGA_S0 C9104 X7R (+/-15%、-55~125℃) *Per clamshell pair 1K33R2F-GP 1 0.1uF(X7R) K0402 ×4 OPS R9103 2 1.0uF(X7R) K0603 ×8 C9111 OPS OPS C9112 R9104 SCD01U50V2KX-1GP 2 1 C9110 1K33R2F-GP 1 C9109 OPS 2 C9108 OPS SC1U6D3V3KX-2GP 2 1 C9107 OPS SC1U6D3V3KX-2GP 2 1 C9106 OPS SC1U6D3V3KX-2GP 2 1 OPS SC1U6D3V3KX-2GP 2 1 OPS SC1U6D3V3KX-2GP 2 1 C9105 SC1U6D3V3KX-2GP 2 1 OPS SC1U6D3V3KX-2GP 2 1 1 SC1U6D3V3KX-2GP 2 1 FBB_VREF_1 <Core Design> OPS C9113 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Close to VRAM(For VRAM7 & VRAM8) Date: A B C 1 D CHANNEL-C_VRAM7,8 (4/4) Document Number LA48 Friday, January 06, 2012 Rev SD Sheet E 91 of 103 5 4 3 2 1 SSID = PWR.Plane.Regulator_GFX PWR_DCBATOUT_VGA_CORE 2nd source 1 VGA_CSP1_R 1 2 PR9201 30K9R2F-GP PWR_VGA_CORE_PN1 OPS PR9204 NTC-150K-GP 2 3 4 10 9 PG9205 1 2 GAP-CLOSE-PWR-3-GP N13P-GL 71.0N13P.B0U N13M-GS 71.0N13M.E0U N13M-GE1 71.0N13M.C0U 7 6 5 8 2 N13P-GS 71.0N13P.00U FDMS3600-02-RJK0215-COLAY-GP 0.875V VID[6:0]0110010 84.03606.037 PWR_VGA_CORE_V5FILT 63.10334.1DL 63.10334.1DL 63.10334.1DL PR9233 DY 63.10334.1DL DY DY PR9208 DY 2 2 PR9210 0R2J-2-GP DY 1 0R0402-PAD PR9211 3D3V_VGA_S0 3D3V_VGA_S0 OPS-BOM CTRL 1 PWR_VGA_CORE_V5FILT 1 2 1 2 1 OPS 1 2 COIL-D36UH-5-GP GND GND 2 41 OPS 1 PR9244 2 OPS OPS PR9242 2D2R3J-2-GP OPS PWR_VGA_CORE_THRM_R 1 DY PWR_VGA_CORE_TER2 PC9216 SC470P50V2KX-3GP DY 2KR2F-3-GP PWR_VGA_CORE_AGND PT9203 OPS 2 PWR_VGA_CORE_VBST2 2 PC9215 SCD1U50V3KX-GP 2 25 TPS51728RHAR-GP 2VGA_VBST2_R 1 OPS 2D2R2J-GP 2 PR9225 1 1 PGND VGA_CORE PL9202 84.03606.037 B PWR_VGA_CORE_LGATE2 1 VGA_CSN2_R PWR_VGA_CORE_AGND OPS PC9220 SC3300P50V2KX-1GP 1 2 PR9250 30K9R2F-GP PWR_VGA_CORE_VREF OPS SCD012U25V2KX-GP OPS 1 PR9246 OPS VGA_VREF_L 2 2 1 1 PC9219 OPS OPS PWR_VGA_CORE_PN2 PR9247 1 42K2R2F-L-GP PWR_VGA_CORE_AGND PR9248 9K09R2F-GP 2 2 PR9254 0R0402-PAD PR9251 0R2J-2-GP 2 DY 1 OPS 1 PR9253 124KR2F-GP PWR_VGA_CORE_SLP 1 1 DYPR9252 0R2J-2-GP PC9218 2 1 PR9240 2 PWR_VGA_CORE_SLEW 2 DY SLP PCNT EN SLEW 1 DY PWR_VGA_CORE_THRM 7 6 5 2 2 PC9223 SC330P50V2KX-3GP PWR_VGA_CORE_CSP2 2 1 PC9222 SC330P50V2KX-3GP PWR_VGA_CORE_CSN1 2 1 DY 1 2 PR9249 0R0402-PAD 9 1 8 PWR_VGA_CORE_UGATE2 SC220P50V2KX-3GP DY 3D3V_VGA_S0 PU PWR_VGA_CORE_VREF PC9221 SC330P50V2KX-3GP PWR_VGA_CORE_CSP1 2 1 OPS PC9224 SC330P50V2KX-3GP PWR_VGA_CORE_CSN2 2 1 B PWR_VGA_CORE_LL1 PWR_VGA_CORE_LL2 9 22,93 PWR_VGA_CORE_DROOP NTC-150K-GP 1 OPS PC9225 SCD1U50V3KX-GP THRM GFB VFB 12 13 35 37 23 28 DGPU_PWROK 2 3 4 10 ST330U2VDM-4-GP PWR_VGA_CORE_VR_ON 2 10KR2J-3-GP PWR_VGA_CORE_AGND LL1 LL2 CSP2 CSN2 7 8 PWR_VGA_CORE_THAL# PWR_VGA_CORE_IMON PWR_VGA_CORE_OSRSEL OPS PC9212 FDMS3600-02-RJK0215-COLAY-GP CSP1 CSN1 3 4 10 11 32 33 34 39 1 1 PWR_VGA_CORE_CSP2 PWR_VGA_CORE_CSN2 2 0R0402-PAD PWR_VGA_CORE_GFB 2 0R0402-PAD PWR_VGA_CORE_VFB SC3300P50V2KX-1GP OPS2 OPS 2 11K8R2F-GP 6 5 THAL# IMON OSRSEL PGD PG# DROOP PU9206 30 27 OPS PC9211 GAP-CLOSE-PWR-3-GP PR9239 1 PR9241 1 PC9217 1 PR9243 1 VID0 VID1 VID2 VID3 VID4 VID5 VID6 PC9210 2 2 2 0R0402-PAD 2 0R0402-PAD 20 19 18 17 16 15 14 21 24 2 VGA_CSP2_R VGA_CSN2_R PR9236 1 PR9237 1 PWR_VGA_CORE_CSP1 PWR_VGA_CORE_CSN1 DRVH2 DRVL2 PR9238 2 0R0402-PAD 2 0R0402-PAD DRVH1 DRVL1 VREF OPS Q1: Id=11A, Qg=10~14nC, Rdson=7.5~9.8 mohm Q2: Id=23A, Qg=27~38nC, Rdson=1.7~2.1 mohm PWR_VGA_CORE_VREF NTC-150K-GP PR9226 1 PR9227 1 VBST1 VBST2 40 31 36 1 VGA_CSP1_R VGA_CSN1_R PWR_VGA_CORE_IMON PR9256 1 PWR_VGA_CORE_VID0 PWR_VGA_CORE_VID1 PWR_VGA_CORE_VID2 PWR_VGA_CORE_VID3 PWR_VGA_CORE_VID4 PWR_VGA_CORE_VID5 PWR_VGA_CORE_VID6 TRIPSEL TONSEL PG9211 OPS-BOM CTRL 83 NVGND_SENSE 83 NVVDD_SENSE 3D3V_VGA_S0 PWR_VGA_CORE_VREF PWR_VGA_CORE_PCNT OPS OPS-BOM CTRL PWR_DCBATOUT_VGA_CORE OPS V5IN V5FILT 2 DY PR9235 10KR2J-3-GP 2 1 PR9234 10KR2J-3-GP 2 1 OPS PR9233 10KR2J-3-GP 2 1 PR9232 10KR2J-3-GP 2 1 DY PR9231 10KR2J-3-GP 2 1 PR9229 10KR2J-3-GP 2 1 OPS 26 PWR_VGA_CORE_V5FILT 38 PWR_VGA_CORE_VBST1 22 PWR_VGA_CORE_VBST2 29 2 SCD22U10V2KX-1GP OPS PWR_VGA_CORE_AGND PR9230 10KR2J-3-GP 2 1 0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD 0R0402-PAD 2 2 2 2 2 2 PC9207 SC470P50V2KX-3GP 2 PR9220 10KR2J-3-GP 2 1 PR9219 10KR2J-3-GP 2 1 PR9218 10KR2J-3-GP 2 1 PR9217 10KR2J-3-GP 2 1 PR9216 10KR2J-3-GP 2 1 PR9215 10KR2J-3-GP 2 1 PR9214 10KR2J-3-GP 2 1 2 SC2D2U10V3KX-1GP 2 SC2D2U10V3KX-1GP OPS PC9214 1 1 1 1 1 1 1 PT9202 OPS DY PWR_VGA_CORE_LGATE1 SCD01U50V2KX-1GP PC9208 1 PC9209 1 OPS-BOM CTRL PR9221 PR9222 PR9223 PR9224 PR9257 PR9258 PT9201 OPS PR9213 56R2J-4-GP PU9201 OPS DY OPS NV_VID0 NV_VID1 NV_VID2 NV_VID3 NV_VID4 NV_VID5 DY PWR_VGA_CORE_TER1 SC10U25V5KX-GP OPS OPS Panasonic. 0.36uH 10*11.5*4 DCR=1.1mohm Idc=17A, Isat=24A SC10U25V5KX-GP DY OPS COIL-D36UH-5-GP PR9212 2D2R3J-2-GP 2 PC9206 SCD1U50V3KX-GP C PWR_VGA_CORE_TRIPSEL DY PR9209 2D2R2J-GP PWR_VGA_CORE_AGND 5V_S0 2 C 2 VGA_VBST1_R 1 1 1 0R0402-PAD PR9207 1 63.10334.1DL DY 2 1 DY 63.10334.1DL 2 63.10334.1DL PR9218 1 1 PR9232 1 NV_VID4 VGA_CORE PWR_VGA_CORE_UGATE1 1 DY 2 DY DY 2 63.10334.1DL 63.10334.1DL 0R2J-2-GP DY DY ST330U2VDM-4-GP 63.10334.1DL PR9217 ST330U2VDM-4-GP PR9230 PG9213 GAP-CLOSE-PWR-3-GP OPS PL9201 PWR_VGA_CORE_VBST1 63.10334.1DL 1 NV_VID3 DY 2 NV_VID1 63.10334.1DL 2 0.9V VID[6:0]=0110000 DY 2 0.975V VID[6:0]=0101010 1 0.9V VID[6:0]=0110000 PR9215 1 NVVDD Boot Voltage 76K8R2F-GP PG9206 1 2 GAP-CLOSE-PWR-3-GP 86 86 86 86 86 86 D VGA_CSN1_R 2 1 OPS 2 PU9202 BOM control SCD012U25V2KX-GP 2 PR9203 76K8R2F-GP OPS PG9204 1 2 GAP-CLOSE-PWR-3-GP PC9201 OPS PR9202 42K2R2F-L-GP 1 OPS 2 2 1 1 PG9203 1 2 GAP-CLOSE-PWR-3-GP OPS PC9204 1 84.03606.037 FDMS3606S-GP-U OPS PC9203 2 1 2 PU9206 PC9202 SC10U25V5KX-GP PG9202 1 2 GAP-CLOSE-PWR-3-GP OPS 84.03606.037 FDMS3606S-GP-U SC10U25V5KX-GP PU9202 SCD01U50V2KX-1GP D PWR_DCBATOUT_VGA_CORE PG9201 1 2 GAP-CLOSE-PWR-3-GP 1 Main source DCBATOUT VGA_CSP2_R OPS OPS PWR_VGA_CORE_AGND 2 1 PR9255 0R0402-PAD 3D3V_VGA_S0 PWR_VGA_CORE_AGND A 1 A 2 PR9228 10KR2J-3-GP <Core Design> DGPU_PWROK Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 5 4 3 2 TPS51728_VGA_CORE Size Document Number Date: Friday, January 06, 2012 Rev <Doc> SD Sheet 1 92 of 103 5 4 3 2 +3VS to 3.3V_DELAY Transfer 1 1 84.04494.037 2nd = 84.04168.037 OPS 2 DCBATOUT_RUN check layout 8 7 6 5 C9302 SCD1U16V2KX-3GP 1D05V_VGA_S0 3.6A U9302 S 1 S 2 S 3 G 4 D D D D D OPS AO4468-GP 84.04468.037 2nd = 84.08882.037 OPS R9317 C9308 SCD1U16V2KX-3GP OPS C9310 SCD1U50V3KX-GP 2 OPS 2 OPS D9301 MMPZ5239BPT-GP RUNON_R_2 1 2 R9314 30KR2F-GP 1 C9303 SCD1U50V3KX-GP 83.9R103.D3F OPS OPS 2 OPS 1 OPS R9307 5K1R2F-2-GP 2 1 1 2DIS_EN_1D5_RUN_R R9305 330KR2J-L1-GP R9306 OPS 100KR2J-1-GP 84.S0610.B31 2ND = 84.00610.C31 OPS K OPS RUNON_R 1 2 R9303 5K1R2F-2-GP 2 OPS DIS_EN_1D5_RUN OPS DY 22,92 DGPU_PW ROK 1 R9310 0R2J-2-GP C 84.2N702.J31 2ND = 84.2N702.J31 2N7002K-2-GP 84.2N702.J31 2ND = 84.2N702.J31 OPS 2 D Q9304 2N7002K-2-GP 10KR2J-3-GP S 1 DY R9313 0R2J-2-GP 2 PR9315 2 DGPU_PW ROK_R 1 OPS C9304 SCD1U10V2KX-4GP S 1 G 3D3V_VGA_S0 1D5V_VGA_S0 2 D DGPU_PWR_EN Q9305 G RUNON_R D Q9303 NDS0610-NL-GP S 10KR2J-3-GP 3.3V_RUN_VGA_1 OPS 2 RUN_ENABLE_1 1 A 2 1 1 R9316 0R2J-2-GP DY 1 2 R9308 30KR2F-GP RUNON_R_1 G 2 3 2 1 1 R9315 0R2J-2-GP OPS RUN_ENABLE OPS 84.2N702.A3F 2nd = 84.2N702.A3F OPS 18 DGPU_PW R_EN# TC9301 SE330U2D5VDM-1GP OPS AO4494L-GP 1 1 4 5 6 R9304 100R2J-2-GP Q9301 2N7002KDW -GP C 1 2 3 4 1D05V_VTT 3.3V_ALW _1 DCBATOUT 3D3V_S0 D D D D 2 G OPS 84.03419.031 2nd = 84.00048.031 3rd = 84.03334.031 OPS 2 C9301 SC10U6D3V3MX-GP Q9302 AO3419L-GP 1 1 R9302 100KR2J-1-GP 2 DY C9309 SCD1U16V2KX-3GP 1 D 8 7 6 5 2 S 1D5V_VGA_S0 U9301 S S S G 2 3D3V_VGA_S0 3D3V_S0 1D5V_S3 AO4468, SO-8 Id=11.6A, Qg=9~12nC Rdson=17.4~22m ohm 2 0R5J-5-GP OPS D 1.05V to 1.05V_VGA_S0 Transfer 1D5V_VGA_S0 DY 1 R9301 1 1 DY R9311 75R2F-2-GP 1D05V_VGA_S0 1 2 OPS 2 6 1 DGPU_PW ROK_R 2N7002KDW -GP 2 B DIS_1D05V_NV_L 5 4 DGPU_PW ROK# OPS 3 3 DGPU_PWROK# DIS_FBVDD_L 4 6 B Q9309 OPS R9312 75R2F-2-GP 5 2 R9318 10KR2J-3-GP 2 1 3D3V_S0 Q9308 2N7002KDW -GP OPS DGPU_PWROK# 1 OPS <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 5 4 3 2 DISCRETE VGA POWER Size A3 Document Number Date: Friday, January 06, 2012 Rev LA480 SD Sheet 1 93 of 103 5 4 3 2 1 D C D BLANK C B B <Core Design> Wistron Corporation A 21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title <Title> Size A4 Document Number LA480 Date: Friday, January 06, 2012 Rev SD Sheet 94 of 103 A 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Reserved Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 95 of 1 103 A 5 4 3 2 1 D D C C BLANK B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title TOUCH PANEL Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 96 of 1 103 A 3 1 1 1 2 2 2 1 2 2 1 1 1 1 1 1 DY SCD1U25V2KX-GP 1 DY SCD1U25V2KX-GP 1 DY EC9730 EC9731 EC9732 EC9733 SCD1U25V2KX-GP 34.4GD01.001 XDP_DBRESET# 5,19 H_CPUPW RGD 5,22 PLT_RST# 5,18,27,31,36,65,66,71,80,82,83 SC1KP50V2KX-1GP 34.4GD01.001 SCD1U25V2KX-GP D 1 1 EC9729 EC9727 EC9728 34.4B417.001 ZZ.SCREW.091 1 VCCSA SCD1U25V2KX-GP ZZ.SCREW.091 SCD1U25V2KX-GP ZZ.SCREW.091 DCBATOUT H1 H2 H21 H18 STF237R128H42-1-GPSTF237R128H42-1-GP STF237R128H42-1-GP STF256R89H178-GP H14 H15 H16 H17 HOLET157B276R134-GP HOLET157B276R134-GP HOLET157B276R134-GP HOLET157B276R134-GP ZZ.SCREW.091 MINI PCIE 2 VGA Std-Off CPU Plate 2 1 4 2 5 D 34.4GD01.001 14" Structure boss H7 H8 HOLE355X355R111-S1-GPHOLE335R115-GP H10 H11 H12 H13 H19 HOLE237R95-GP HOLE237R95-GP HOLE335R115-GP HOLE237R95-GP HOLE315R95-GP ZZ.00PAD.D11 ZZ.00PAD.581 ZZ.00PAD.571 ZZ.00PAD.921 ZZ.00PAD.921 ZZ.00PAD.D01 ZZ.00PAD.921 ZZ.00PAD.911 ZZ.00PAD.D01 1 1 1 1 1 1 3D3V_S0 5V_S0 1 1 1 1 1 ZZ.00PAD.D11 H5 HOLE315X315R91-S1-GP 1 H3 HOLE256R115-GP H4 HOLE256R115-GP R9704 100R2J-2-GP R9705 100R2J-2-GP 3D3V_VGA_S0 ODD_PW R_5V VCC_CORE 5V_S5 1 1 1 1 1 1 1 1 1 1 DY DY DY DY DY DY DY DY DY EC9724 PS_S3CNTRL DY PS_S3CNTRL G G S 2 2 2 EC9723 Q9705 2N7002A-7-GP DY SCD1U25V2KX-GP 2 EC9722 SCD1U25V2KX-GP 2 EC9721 2 EC9720 SCD1U25V2KX-GP 2 EC9719 SCD1U25V2KX-GP 2 EC9718 SCD1U25V2KX-GP 2 EC9717 SCD1U25V2KX-GP 2 EC9716 2 EC9715 SCD1U25V2KX-GP 2 1 1 1 DY EC9714 SCD1U25V2KX-GP 2 DY SCD1U25V2KX-GP 2 1 1 EC9713 SCD1U25V2KX-GP 2 EC9712 DY SCD1U25V2KX-GP 1 EC9711 SCD1U25V2KX-GP 2 EC9710 SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP 2 EC9709 SCD1U25V2KX-GP DY EC9708 SCD1U25V2KX-GP DY 2 EC9707 1 1 1 EC9706 DY SCD1U25V2KX-GP SCD1U25V2KX-GP 2 EC9705 2 1 Q9704 2N7002A-7-GP 5V_RUNPWR 3D3V_AUX_KBC D 3D3V_AUX_S5 S 3D3V_S0_CAMERA D DCBATOUT C 3D3V_RUNPWR C 2 DY 2 DY 1 1 5V_USB1_S3 1 1D05V_VTT 5V_USB2_S3 B PS_S3CNTRL G 19,27,46 PM_SLP_S4# 2 VTT_RUNPWR 2 1 1 D 2 DY 1D5V_RUNPWR Q9711 2N7002A-7-GP DY G Q9701 2N7002A-7-GP DY 2 DY G 36,37 PS_S3CNTRL PS_S3CNTRL <Core Design> A G Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. S S S S G S 1 2 1 2 1 2 R9711 100R2J-2-GP DY Q9710 2N7002A-7-GP DY PS_S3CNTRL R9710 100KR2J-1-GP PM_SLP_S4 D Q9702 2N7002A-7-GP DY S G 2 1 PS_S3CNTRL G DY 1D8V_RUNPWR 1D05V_RUNPWR 2 DY S PS_S3CNTRL Q9709 2N7002A-7-GP D 2 DY A D D Q9707 2N7002A-7-GP DY DY GFX_RUNPWR CORE_RUNPWR Q9706 2N7002A-7-GP 1 1 1 2 DY EC9704 SCD1U25V2KX-GP DY R9702 100R2J-2-GP R9709 100R2J-2-GP EC9703 SCD1U25V2KX-GP R9707 100R2J-2-GP SCD1U25V2KX-GP R9706 100R2J-2-GP 1D5V_S3 3D3V_S5 EC9702 DY D 1D8V_S0 VCCSA B R9701 100R2J-2-GP D AD+ VCC_GFXCORE VCC_CORE EC9726 SCD1U25V2KX-GP For Discharge SCD1U25V2KX-GP 2 EC9725 Title UNUSED PARTS/EMI Capacitors 5 4 3 2 Size A3 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 97 of 103 5 4 3 2 1 D D (Blanking) C C B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Change History Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 98 of 1 103 A 5 4 3 Intel-Power Sequence S0 Intel PCH Pin Name S5 VccSUS (5V/3V ) Wake Event D 3D3V_AUX_S5 PWRBTN# PM_PWRBTN# PM_PWRBTN# SLP_A# SLP_A# SLP_LAN# SLP_LAN# SLP_S5# PM_SLP_S5# SLP_S4# PM_SLP_S4# SLP_S3# PM_SLP_S3# VccASW/ VccSPI Vcc_WLAN VccASW/ VccSPI +3V_MINI_WLAN assertion = 16mS SLP_A# Te >0s ( SLP_A# to APWROK ) SLP_LAN# SLP_S5# (TEST POINT) SLP_S4# T09 >30us ( SLP_S5# t0 SLP_S4# ) Ta >30us ( SLP_S4# t0 SLP_S5# ) T10 >30us ( SLP_S4# t0 SLP_S3# ) SLP_S3# VccASW/ VccSPI Tb >30us ( SLP_S3# t0 SLP_S4# ) T29 >0s ( VccSUS to VccASW ) +3V_MINI_WLAN S0_PWR_GOOD T11 >1ms ( VccASW to APWROK ) CL_ RST#(TEST POINT) T12 >500Us ( APWROK to CL_RST# ) 1D8V_S0 1D5V_S0 VCCSA S3 SLP_A# SLP_S5# (TEST POINT) SLP_S4# S0_PWR_GOOD CL_ RST# CL_ RST# VccASW/ VccSPI VCCPLL 1D8V_S0 +3V_MINI_WLAN VDDQ 1D5V_S0 S0_PWR_GOOD T13 >5ms<650ms ( VCCPLL to UNCOREPWRGOOD ) 1D5V_S0 VCC_CORE VDDPWRGOOD T17 >2ms<650ms ( VDDQ to DRAMPWROK ) VccAXG VCC_GFXCORE IMVP_PWRGD SYS_PWROK SYS_PWROK PWROK S0_PWR_GOOD DRAMPWROK PM_DRAM_PWRGD Tf <500ms UNCOREPWRGOOD (SLP_3# to VCCCORE/VCCAWG) PLTRST# H_CPUPWRGD PLT_RST# IMVP_PWRGD Tc >40ns (APWROK# to VCCASW/VCCSPI) T12 >500Us ( APWROK to CL_RST# ) 1D8V_S0 D85V_PWRGD IMVP7_PWRGD T11 >1ms ( VccASW to APWROK ) CL_ RST#(TEST POINT) VccCore VCC_GFXCORE Te >0s ( SLP_A# to APWROK ) SLP_LAN# IMVP7_VR_EN VCC_CORE D PM_PWRBTN# T17 >2ms<650ms ( VCCPLL to DRAMPWROK ) D85V_PWRGD S3 3D3V_AUX_S5 T13 >5ms<650ms ( VCCPLL to UNCOREPWRGOOD ) T17 >2ms<650ms ( VCCSA to DRAMPWROK ) S0 Wake Event SLP_S3# PWROK/APWROK Tc >40ns VR_VDDQPWRGOOD VDDPWRGOOD (APWROK# to VCCASW/VCCSPI) VCCSA VCCSA VDDPWRGOOD C Main board PCH Pin Name 3D3V_AUX_S5 Minimum duration of PWRBTN# 1 (S3-to-S0-to-S3) (S5-to-S0-to-S5) S5 2 VCCSA D85V_PWRGD VCC_CORE C VCC_GFXCORE Tf <500ms (SLP_3# to VCCCORE/VCCAWG) IMVP_PWRGD SYS_PWROK SYS_PWROK S0_PWR_GOOD T12 >100ms ( APWROK to PLTRST# ) T20 >100ms ( PWROK to PM_DRAM_PWRGD S0_PWR_GOOD UNCOREPWRGOOD) T12 >100ms ( APWROK to PLTRST# ) T20 >100ms ( PWROK to UNCOREPWRGOOD) H_CPUPWRGD PM_DRAM_PWRGD T25 >1ms<100ms ( UNCOREPOWERGOOD to PLTRST# ) PLT_RST# T25 >1ms<100ms ( UNCOREPOWERGOOD to PLTRST# ) H_CPUPWRGD Tk >100ns (DRAMPWROK to Tn >30us (PLTRST# to UNCOREPOWERGOOD ) SLP_S4# ) Tn >30us (PLTRST# to UNCOREPOWERGOOD ) PLT_RST# B B A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Change History 5 4 3 2 Size A2 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 99 of 103 A B C D85V_PWRGD RUNPWROK D 3D3V_VGA_S0 E 1.05VTT_PWRGD PM_SLP_S4# 0D75V_EN -4 DCBATOUT Adapter 38 -3 AO4407A PU4201 TPS51640RSLR PU4501 TPS51219 42,43,44 Charger 4 VCC_CORE +PBATT Battery 45 92 6 BQ24707ARGRR 39 PU9201 TPS51728RHAR IMVP_PWRGD PU4601 RT8207MZQW PU4801 TPS51461RGER 48 46 4 VCC_GFXCORE 2 1D05V_VTT PWR_GFX_PWRGD 40 VGA_CORE 1.05VTT_PWRGD 0D85V_S0 DDR_VREF_S3 1D5V_S3 3 4 0D75V_S0 DGPU_PWROK VCCSA U9302 AO4494L(MOS) 0 2 U9301 AO4494L(MOS) D85V_PWRGD 5 93 1D05V_VGA_S0 1D5V_VGA_S0 R6516 RUNPWROK TPS51225RUKR 41 LAN_PWR_ON -2 -1 3 3D3V_AUX_S5 5V_AUX_S5 Q3103 AO3419L -1 5V_S5 3D3V_S5 U6102 UP7534BRA8 41 61 U3601 AO4468-GP 36 U3602 AO4468-GP PU4701 RT8068AZQW 36 -2 47 R6010 60 1 3D3V_AUX_KBC 5V_USB4_S3 5V_S0 3D3V_S0 1D8V_VGA_S0 3 LAN PM_SLP_S3# -1 R2707 3D3V_LAN_S5 3D3V_SPI R6512 WLAN R8202 Cardreader R6403 Fingerprint R6301 Bluetooth R4922 Camera RUNPWROK G5285T11U 49 2 Q9302 DMP2130L 93 LCDVDD 2 3D3V_VGA_S0 F4902 U4901 SY6288CAAC ODD R5607 CRT withuot HDMI F5101 FAN R2802 R5606 HDD TouchPad R6903 R2903 R2904 Audio_Codec 56 F4901 LCD F4903 R5603 R2913 <Core Design> 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: A B C D Power Block Diagram Document Number LA480 Friday, January 06, 2012 Rev SD Sheet E 100 of 103 5 4 3 PCH SMBus Block Diagram 3D3V_S5 3D3V_S0 ‧ ‧ 2 1 KBC SMBus Block Diagram 5V_S0 ‧ 3D3V_S0 SRN2K2J-1-GP SRN2K2J-1-GP ‧ D SMBCLK SMB_CLK SMBDATA SMB_DATA DIMM 1 ‧ ‧ ‧PCH_SMBCLK ‧ PCH_SMBDATA 3D3V_S5 SRN10KJ-5-GP D TouchPad Conn. SCL SRN33J-5-GP SDA SMBus Address:A0 GPIO35/PSDAT1 TPDATA GPIO37/PSCLK1 TPCLK ‧ ‧TPCLK TPDATA TPDATA TPCLK 2N7002KDW 3D3V_AUX_KBC ‧ DIMM 2 SRN2K2J-1-GP ‧PCH_SMBCLK ‧ PCH_SMBDATA ‧ SCL SDA SRN4K7J-8-GP SMBus Address:A4 SML0CLK SML0_CLK SML0DATA SML0_DATA 3D3V_S5 ‧PCH_SMBCLK ‧ PCH_SMBDATA ‧ Minicard WLAN Battery Conn. SRN33J-3-GP GPIO17/SCL1/N2TCK BAT_SCL BATA_SCL_1 I2C_CLK GPIO22/SDA1/N2TMS BAT_SDA BATA_SDA_1 I2C_DAT SMB_CLK SMB_DATA SRN2K2J-8-GP SML1CLK SML1_CLK SML1DATA SML1_DATA ‧ ‧ C PCH_SMBCLK PCH_SMBDATA 3D3V_S0 SMB_CLK BQ24707 KBC NPCE855 SCL SDA SMB_DATA ‧ ‧ ‧ PCH Minicard W-WAN 3D3V_S5 C GPIO73/SCL2 ‧ GPIO74/SDA2 SRN2K2J-1-GP SRN10K2J-1-GP 2N7002KDW Thermal IC LVDS_DDC_CLK_R LVDS_DDC_DATA_R ‧ ‧ CLK DATA ‧ ‧ LCD CONN 3D3V_S0 5V_S0 ‧ ‧ 3D3V_S0 ‧ SRN2K2J-1-GP CRT_DDC_DATA CRT_DDC_DATA ‧ ‧ CRT_DDCCLK_CON CRT_DDCDATA_CON SRN2K2J-1-GP SMBC_Therm_NV SMBD_Therm_NV PEG_RX0~15 PEG_RX#0~15 PEG_TX0~15 PEG_RT#0~15 SRN10KJ-6-GP ‧ PCH_HDMI_DATA ‧ 3D3V_VGA_S0 ‧ 2N7002DW-1-GP ‧ B ‧ 3D3V_S0 PCH_HDMI_CLK SMDATA PEG_RX#0~15 PEG_RX0~15 PEG_RT#0~15 PEG_TX0~15 5V_S0 ‧ SDVO_CTRLDATA I2CS_SCL I2CS_SDA GPU 3D3V_S0 SDVO_CTRLCLK SMCLK SMBD_THERM CRT CONN 2N7002DW-1-GP B SMBC_THERM SRN10KJ-6-GP ‧ CRT_DDC_CLK ‧ SRN4K7J-8-GP 3D3V_S0 CRT_DDC_CLK ‧ ‧ L_DDC_CLK L_DDC_DATA ‧ ‧ CRT_DDCCLK_CON CRT_DDCDATA_CON HDMI CONN PEG_RXP0~15 PEG_RXN0~15 PEG_TXP0~15 PEG_TXN0~15 CPU 2N7002DW-1-GP A A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title SMBUS Block Diagram 5 4 3 2 Size A2 Document Number Date: Friday, January 06, 2012 Rev SD LA480 Sheet 1 101 of 103 A B C D Thermal Block Diagram E Audio Block Diagram 1 1 SPKR_PORT_D_LPAGE28 DXP P2800_DXP SPEAKER SPKR_PORT_D_R+ MMBT3904-3-GP SC2200P50V2KX-2GP UMA Thermal P2800 DXN P2800_DXN Codec 92HD79B1 Place near CPU PWM CORE HP OUT HP1_PORT_B_L MMBT3904-3-GP PAGE27 GPIO5 KBC NPCE795P GPIO92 2 SYS_THRM TDR CPU_THRM TDL HP1_PORT_B_R T8 OTZ THERM_SYS_SHDN# 2N7002 PURE_HW_SHUTDOWN# IMVP_PWRGD G Put under CPU(T8 HW shutdown) GPIO4 GPIO94 GPIO56 VGA_THRM EN D S 2 VR TDR MIC IN HP0_PORT_A_L PAGE28 HP0_PORT_A_R P2800_VGA_DXP DXP THRMDA VREFOUT_A_OR_F FAN_TACH1 FAN1_DAC 3V/5V PGOD TACH FAN VGA Thermal P2800 SC2200P50V2KX-2GP SC2200P50V2KX-2GP VGA P2800_VGA_DXN THRMDC DXN Place near GPU(DISCRETE only). MMBT3904-3-GP Digital MIC DMIC_CLK/GPIO1 VIN 5V DMIC0/GPIO2 3 3 PH VIN OTZ VSET VOUT FAN CONTROL P2793 PORTC_L PAGE28 Analog MIC PORTC_R VREFOUT_C <Core Design> 4 4 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Thermal/Audio Block Diagram Size Custom Date: A B C D Document Number LA480 Friday, January 06, 2012 Rev SD Sheet E 102 of 103 5 4 3 2 1 D D C C (Blanking) B B <Core Design> Wistron Corporation A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Change History Size A4 Document Number LA480 Friday, January 06, 2012 Date: 5 4 3 2 Rev SD Sheet 103 1 of 103 A www.s-manuals.com </pre><hr>Source Exif Data: <br /><pre>File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Producer : Modify Date : 2015:10:25 20:50:22+02:00 Create Date : 2012:01:06 10:58:48+08:00 Creator Tool : Metadata Date : 2015:10:25 20:50:22+02:00 Document ID : ed0385cb-3a6d-11e1-0000-8413dd28405e Instance ID : uuid:3e67e89f-4c00-453d-bb3b-31eefce7198e Format : application/pdf Title : Wistron LA480 - Schematics. www.s-manuals.com. Creator : Description : Subject : Wistron LA480 - Schematics. www.s-manuals.com. Text 0020 Watermark : {1BB492FB-9723-446D-9965-8F106C72B29A} PXC Viewer Info : PDF-XChange Viewer;2.5.201.0;Jan 23 2012;21:08:47;D:20150412203029+04'00' Has XFA : No Page Count : 104 Keywords : Wistron, LA480, -, Schematics., www.s-manuals.com. Text Watermark : {1BB492FB-9723-446D-9965-8F106C72B29A} Warning : [Minor] Ignored duplicate Info dictionary </pre> <small>EXIF Metadata provided by <a href="https://exif.tools/">EXIF.tools</a></small> <div id="ezoic-pub-ad-placeholder-110"> <script async src="//pagead2.googlesyndication.com/pagead/js/adsbygoogle.js"></script> <!-- usermanual link ad --> <ins class="adsbygoogle" style="display:block" data-ad-client="ca-pub-0545639743190253" data-ad-slot="6172135303" data-ad-format="link"></ins> <script> (adsbygoogle = window.adsbygoogle || []).push({}); </script> </div> </div> <div id="catlinks" class="catlinks catlinks-allhidden" data-mw="interface"></div> <div class="visualClear"></div> </div> </div> <div id="mw-navigation"> <h2>Navigation menu</h2> <div id="mw-head"> <div id="p-personal" role="navigation" class="" aria-labelledby="p-personal-label"> <!-- <div id="p-search" role="search"> <form action="https://usermanual.wiki/search.php" id="searchform"> <div id="simpleSearch"> <input type="search" name="search" placeholder="Search UserManual.wiki" title="Search UserManual.wiki [ctrl-option-f]" accesskey="f" id="searchInput" tabindex="1" autocomplete="off"><input type="hidden" value="Special:Search" name="title"><input type="submit" name="go" value="Go" title="Find a User Manual" id="searchButton" class="searchButton"> </div> </form> </div>--> <ul> <li id="pt-mycontris"><a href="https://usermanual.wiki/upload" title="Upload User Manual" accesskey="y">Upload a User Manual</a></li> </ul> </div> <div id="left-navigation"> <div id="p-namespaces" role="navigation" class="vectorTabs" aria-labelledby="p-namespaces-label"> <h3 id="p-namespaces-label">Versions of this User Manual:</h3> <ul> <li id="ca-nstab-main"><span><a href="https://usermanual.wiki/Document/wistronla480rsdschematics.2053506075" title="User Manual Wiki" accesskey="c">Wiki Guide</a></span></li> <li id="ca-nstab-main"><span><a href="https://usermanual.wiki/Document/wistronla480rsdschematics.2053506075/html" title="HTML" accesskey="c">HTML</a></span></li> <li id="ca-nstab-main" class="selected" ><span><a href="https://usermanual.wiki/Document/wistronla480rsdschematics.2053506075/help" title="Discussion / FAQ / Help" accesskey="c">Download & Help</a></span></li> </ul> </div> </div> <div id="right-navigation"> <div id="p-views" role="navigation" class="vectorTabs" aria-labelledby="p-views-label"> <h3 id="p-views-label">Views</h3> <ul> <li id="ca-view"><span><a href="#">User Manual</a></span></li> <li class="selected" id="ca-edit"><span><a href="https://usermanual.wiki/Document/wistronla480rsdschematics.2053506075/help" title="Ask a question" accesskey="e">Discussion / Help</a></span></li> </ul> </div> </div> </div> <div id="mw-panel"> <div id="p-logo" role="banner"><a class="mw-wiki-logo" href="https://usermanual.wiki/Main_Page" title="Visit the main page"></a></div> <div class="portal" role="navigation" id="p-navigation" aria-labelledby="p-navigation-label"> <h3 id="p-navigation-label">Navigation</h3> </div> <div class="portal" role="navigation" id="p-tb" aria-labelledby="p-tb-label"> </div> </div> </div> <div id="footer" role="contentinfo"> <ul id="footer-info"> <li id="footer-info-lastmod">© 2024 UserManual.wiki</li> </ul> <ul id="footer-places"> <li id="footer-places-privacy"><a href="https://usermanual.wiki/ContactUs" title="UserManual.wiki:Contact Us">Contact Us</a></li> <li id="footer-places-about"><a href="https://usermanual.wiki/DMCA" title="UserManual.wiki:DMCA">DMCA</a></li> </ul> <ul id="footer-icons" class="noprint"> <li id="footer-poweredbyico"> </li> </ul> </div> </div></body></html> <script src="/cdn-cgi/scripts/7d0fa10a/cloudflare-static/rocket-loader.min.js" data-cf-settings="707f6e236c19e34b213dd3de-|49" defer></script>