Wistron Leopard2 Schematics. Www.s Manuals.com. R1.0 Schematics
User Manual: Motherboard Wistron Leopard2 - Schematics. Free.
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A CLK GEN B C D Leopard2 Block Diagram 3 ICS954206 E Project code: 91.4C701.001 PCB P/N : 48.4C701.011 REVISION : 05202 -1 4,5 Mobile CPU SYSTEM DC/DC 42 TPS5130 INPUTS OUTPUTS 1D8V_S3 5V_S3 DCBATOUT 3V_AUX Dothan 4 1394 Conn 4 31 11,12 DDRII*2 SYSTEM DC/DC 45 29 28 PCMCIA 1 SLOT 1D05V_S0 1D2V_VGA_S0 6,7,8,9,10 CARDBUS 1394 SD/MS/MMC/SM SD/MS 29 6 in 1 Card Slost OUTPUTS DCBATOUT PCI 7411 Power Switch TPS2220A INPUTS DDR-SDRAM16,17 HY5DS573222F-28 Host BUS 400/533MHz 27,28 MAX8743 LVDS 13,14,15 19 LCD VGA Alviso 18 ATI M26P PEG SVIDEO/COMP MAXIM CHARGER 40 TVOUT MAX8725 INPUTS RGB CRT DMI I/F 100MHz 3 34 Mini-PCI 802.11a/b/g OUTPUTS BT+ CRT DCBATOUT DAUGHTER BOARD 18V 4.0A 5V 100mA 3 BLUE THUMB 21,22,23,24 31 10/100 RTL8100C 41 PCI BUS P EIDE ICH6-M RJ11 CONN CPU DC/DC USB x 2 USB x 2 35 USB 2.0 30,31 RJ45 CONN HDD 26 MODEM MDC Card OUTPUTS VCC_CORE 35 31 MAX1907 INPUTS AC97-LINK S EIDE DCBATOUT DVD/ 26 CD-RW 0.844~1.3V 27A 26 2 PCI EXPRESS/ USB2.0 MIC IN18 EXPRESSCARD 31 AC'97 CODEC AD1981B LINE OUT OP AMP G1420B PCB LAYER LPC Bus 33 Docking 18 KBC NS97551 36 LPC 38 Debug Conn 26 Power Switch TPS2231 DAUGHTER BOARD 35 Comsumer IR 37 Touch Pad 1 37 Int. KB 25 Thermal & Fan G768D 38 FlashRom 4Mb (512kB) L1: Signal 1 L2: GND L3: Signal 2 L4: Signal 3 L5: VCC L6: Signal 4 L7: GND L8: Signal 51 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Block Diagram Size A3 Document Number Date: Monday, July 11, 2005 A B C D 2 Rev -1 Leopard2 Sheet E 1 of 47 A B ICH6-M Integrated Pull-up and Pull-down Resistors ICH6-M EDS 14308 0.8V1 D E Power name description 5V_S0= 5 Voltage power up on system work(S0 state) ACZ_BIT_CLK, DPRSLP#, EE_DIN, 5V_S3= 5 Voltage suspend to RAM(S3 state) EE_DOUT, EE_CS, GNT[5]#/GPO[17], ICH6 internal 20K pull-ups 4 C GNT[6]#/GPO[16], LDRQ[1]/GPI[41], 5V_S5= 5 Voltage soft off(S5 state) 4 3D3V_S0= 3.3 Voltage power up on system work(S0 state) LAD[3:0]#/FB[3:0]#, LDRQ[0], 3D3V_S3= 3.3 Voltage suspend to RAM(S3 state) PME#, PWRBTN#, TP[3] 3D3V_S5= 3.3 Voltage soft off(S5 state) LAN_RXD[2:0] ICH6 internal 10K pull-ups ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC, ICH6 internal 20K pull-downs LVDDR_2D8V= 2.8 Voltage power up on system work(S0 state) 1D8V_S3= 1.8 Voltage suspend to RAM(S3 state) 2D5V_S0= 2.5 Voltage power up on system work(S0 state) ACZ_SDOUT,ACZ_BITCLK, DPRSLPVR, SPKR VCC_CORE_S0= CPU VID Voltage power up on system work(S0 state) USB[7:0][P,N] ICH6 internal 15K pull-downs DD[7], SDDREQ ICH6 internal 11.5K pull-downs LAN_CLK ICH6 internal 100K pull-downs 1D5V_VCCA_S0= 1.5 Voltage power up on system work(S0 state) 1D5V_S0= 1.5 Voltage power up on system work(S0 state) 1D5V_S5= 1.5 Voltage soft off(S5 state) DDR_VREF= 0.9 Voltage power up on system work(S0 state) 1D2V_VGA_S0= 1.2 Voltage power up on system work(S0 state) for VGA VRAM_VDDQ= 1.8 Voltage power up on system work(S0 state) for VRAM 3 3 1D05V_S0= 1.05 Voltage power up on system work(S0 state) ICH6-M IDE Integrated Series Termination Resistors CORE_GMCH_S0= 1.05 Voltage power up on system work(S0 state) for ALVISO core power VCCP_GMCH_S0= 1.05 Voltage power up on system work(S0 state)for ALVISO BUSIO power DD[15:0], DIOW#, DIOR#, DREQ, approximately 33 ohm DDACK#, IORDY, DA[2:0], DCS1#, DCS3#, IDEIRQ PCI RESOURCE TABLE 2 DEVICE IDSEL PCI IRQ REQ# / GNT# Mini-PCI AD21 P_INTE# REQ0#/GNT0# Cardbus Controller TI7411 LAN Blue Thumb (CARBUS)P_INTG# (1394)P_INTF# AD22 (CARD READER)P_INTG# REQ1#/GNT1# AD23 REQ2#/GNT2# P_INTE# 2 AD24 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ITP Size A3 Document Number Date: Wednesday, July 06, 2005 A B C D Rev -1 Leopard2 Sheet E 2 of 47 A B D 1 3D3V_S0 C219 SCD1U16V 1 C218 SC4D7U10V5ZY 2 C524 SCD1U16V 2 C199 SC4D7U10V5ZY 1 1 1 2 2 3D3V_48MPWR_S0 4D7R3 1 R196 DY R200 10KR2 2 DY 3D3V_S0 DummyR200(up side),Mounting R221(down side) --SRC7 on ITP_EN 4 1 1 1 C518 SCD1U16V DY Mounting R200(up side),DummyR221(down side) --CPU2_ITP on DY DY 2 DY R221 10KR2 C539 SCD1U16V 2 C525 SCD1U16V 2 2 C543 SCD1U16V 2 C538 SCD1U16V 1 1 1 2 C523 SCD1U16V 2 C532 SCD1U16V 2 C519 SC10U10V6ZY-U 1 1 3D3V_CLKGEN_S0 2 L38 1 2 MLB-201209-11 1 4 E 3D3V_S0 L17 1 2 3D3V_APWR_S0 MLB-201209-11 2 3D3V_S0 C 3D3V_S0 25,41 CLK_PWRGD# 1 3D3V_APWR_S0 3D3V_48MPWR_S0 R590 10KR2 CLK_XOUT 3D3V_CLKGEN_S0 X7 CLK_XIN 2 2 SC22P 2 1 C544 H/L: 100/96MHz 22 CLK_PCIE_ICH# 22 CLK_PCIE_ICH SRN33-2-U2 RN19 4 1 3 2 20 23 25 27 30 32 CLK_SRCC3 CLK_SRCT3 19 22 24 26 31 33 CLK_SRCC5 CLK_SRCT5 SB SRN33-2-U2 TPAD30 TP31 TP_SRCC6 CLK_SRCT6 2 1 DY 0R2-0 TPAD30 TP30 TP_SRCT6 R584 2 CLK_SRCC6 1 R568 DY 0R2-0 CLK_REF14 26 PREQ2# 1 2 22 CLK_ICH14 22R2 R602 1 2 32 CLK_CODEC 22R2 R601 2 1 4,7 CPU_SEL0 2K2R2 R222 52 53 46 47 SRCCLKC1 SRCCLKC2 SRCCLKC3 SRCCLKC4_SATA SRCCLKC5 SRCCLKC6 GND GND GND GND GND GND GNDA RN21 CLK_SRCC2 CLK_SRCT2 1 2 51 45 29 13 6 2 38 4 3 VDDPCI VDDPCI 4 3 R591 10KR2 CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6 SRN33-2-U2 DY PM_STPCPU# 22,41 3 RN24 CPU_STOP# CPUCLKC0 CPUCLKC1 CPUCLKC2_ITP/SRCCLKC7 54 43 40 35 CLK_CPUC2 CLK_CPUT2 2 1 CPUCLKT0 CPUCLKT1 CPUCLKT2_ITP/SRCCLKT7 44 41 36 CLK_CPUT0 CLK_CPUC0 1 2 FSLA/USB_48MHZ FSLB/TEST_MODE 12 16 FS_A 96MHZ_SSC/SRCCLKC0 96MHZ_SST/SRCCLKT0 18 17 CLK_SRCC0 CLK_SRCT0 DOTC_96MHZ DOTT_96MHZ 15 14 DOT96C DOT96T 3 4 DY CLK_XDP_CPU# 4 CLK_XDP_CPU 4 SRN33-2-U2 RN25 4 3 SRN33-2-U2 R592 1 R593 1 2 10R2 2 33R2 SC RN23 1 2 DREFCLK CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4 4 3 CLK48_USB 22 CLK48_CARDBUS CPU_SEL1 4,7 DREFCLK# CLK_PCIE_NEW 27 CLK_PCIE_NEW# DREFSSCLK# 7 DREFSSCLK 7 CLK_XDP_CPU CLK_XDP_CPU# SRN33-2-U2 R199 2 133R2 R201 2 133R2 DREFCLK# 7 DREFCLK 7 CLK_CPU_BCLK CLK_CPU_BCLK# CLK_MCH_BCLK CLK_MCH_BCLK# ICS954206AG 1 R202 1 R198 1 R582 1 R580 1 R603 1 R594 1 R596 1 R595 1 R585 1 R586 2 49D9R2F 2 49D9R2F 2 49D9R2F 2 49D9R2F 2 DY 49D9R2F 2 DY 49D9R2F 2 49D9R2F 2 49D9R2F 2 49D9R2F 2 49D9R2F 1 R194 1 R195 1 R566 1 R567 1 R581 1 R583 1 R569 1 R570 2 49D9R2F 2 49D9R2F 2 49D9R2F 2 49D9R2F 2 49D9R2F 2 49D9R2F 2 49D9R2F 2 49D9R2F SRN33-2-U2 2 CLK_IREF 2 475R2F 36 PCLK_KBC 1 R589 2 SS_SEL 22R2 22 PM_STPPCI# 22 CLK_ICHPCI 1 R220 2 33R2 ITP_EN REQSEL CLK_PCI3 2 33R2 CLK_PCI4 2 33R2 CLK_PCI5 2 33R2 2 1 R181 1 1R600 1R218 R219 CLK_CPU_BCLK 1 CLK_CPU_BCLK# 3D3V_CLKGEN_S0 R606 10KR2 TP33 TPAD30 TP32 TPAD30 close to CPU FS_A 2 10KR2 2 1 R197 1 REQSEL 2 R605 DUMMY-R2 FS_C FS_B FS_A 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ICS954206AG Spread Spectrum Select PCLK_PCM 27 PCLK_LAN 30 PCLK_MINI 34 NEAR CLKGEN 3D3V_S0 1 1 42 37 11 48 7 1 REF0 REF1/FSLC/TEST_SEL SCLK SDATA 11,24 SMBC_ICH 11,24 SMBD_ICH 13 CLK_PCIE_PEG# 13 CLK_PCIE_PEG 34 28 21 SRCCLKT1 SRCCLKT2 SRCCLKT3 SRCCLKT4_SATA SRCCLKT5 SRCCLKT6 1 2 2 7 CLK_MCH_3GPLL# 7 CLK_MCH_3GPLL SRN33-2-U2 RN18 4 1 3 2 CLK_SRCC1 CLK_SRCT1 1 2 VDDCPU VDDA VDD48 VDDREF 4 3 RN22 CLK_CPUT1 CLK_CPUC1 SEL100_96MHZ#/PCICLK_F1 PCI/SRC_STOP# ITP_EN/PCICLK_F0 PCICLK5 PCICLK4 PCICLK3 PCICLK2 IREF 26 CLK_PCIE_NEW# 26 CLK_PCIE_NEW SS_SEL 9 55 8 5 4 3 56 39 3 VDDSRC VDDSRC VDDSRC RN20 VTT_PWRGD#/PD 49 50 X2 X1 1 1 C545 10 U72 X-14D31818M-17 2 SC22P DREFSSCLK DREFSSCLK# CLK_MCH_3GPLL CLK_MCH_3GPLL# SS3 SS2 SS1 SS0 Spread Amount% 0 0 0 0 -0.8 CLK_PCIE_PEG 0 0 0 1 -1.0 CLK_PCIE_PEG# 0 0 1 0 -1.25 CLK_PCIE_ICH 0 0 1 1 -1.5 CLK_PCIE_ICH# 0 1 0 0 -1.75 0 1 0 1 -2.0 0 1 1 0 -2.5 0 1 1 1 -3.0 1 0 0 0 +-0.3 1 0 0 1 +-0.4 1 0 1 0 +-0.5 Wistron Corporation 1 0 1 1 +-0.6 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 1 0 0 +-0.8 1 1 0 1 +-1.0 1 1 1 0 +-1.25 1 1 1 1 +-1.5 1 CPU 266M 133M 200M 166M 333M 100M 400M Reserved Title Clock Generator (ICS954206AG ) Size A3 Document Number Date: Monday, July 11, 2005 A B C D Rev -1 Leopard2 Sheet E 3 of 47 B U53A 62.10055.011 PZ47903 N4 H_BREQ#0 6 IERR# INIT# A4 B5 LOCK# J2 H_INIT# 21 H_LOCK# 6 H_CPURST# 6 H_RS#[2..0] 6 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_TRDY# 6 H_HIT# 6 H_HITM# 6 VCCP_GMCH_S0 BPM#0 BPM#1 BPM#2 BPM#3 PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# C8 B8 A9 C9 A10 B10 A13 C12 A12 C11 B13 A7 PROCHOT# THERMDA THERMDC B17 B18 A18 THERMTRIP# C17 A15 A16 B14 B15 ITP_CLK1 ITP_CLK0 BCLK1 BCLK0 R393 56R2J VCC_CORE_S0 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# DBR# R27 150R2 6 H_DSTBN#0 6 H_DSTBP#0 6 H_DINV#0 CPU_PROCHOT# THERMDP1 25 THERMDN 25 PM_THRMTRIP-A# 7,21 PM_THRMTRIP-I# 7,21 CLK_XDP_CPU# 3 CLK_XDP_CPU 3 CLK_CPU_BCLK# 3 CLK_CPU_BCLK 3 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 PM_THRMTRIP# should connect to ICH6 and Alviso without T-ing ( No stub) 6 H_DSTBN#1 6 H_DSTBP#1 6 H_DINV#1 2 TP2 TCK(PIN 5) 0R0402-PAD 2 2 0R0402-PAD R383 1 R385 1 3,7 CPU_SEL0 3,7 CPU_SEL1 PSI# CPU_SEL0_CPU CPU_SEL1_CPU A19 A25 A22 B21 A24 B26 A21 B20 C20 B24 D24 E24 C26 B23 E23 C25 C23 C22 D25 U53B PZ47903 62.10055.011 D0# D32# D1# D33# D2# D34# D3# D35# D4# D36# D5# D37# D6# D38# D7# D39# D8# D40# D9# D41# D10# D42# D11# D43# D12# D44# D13# D45# D14# D46# D15# D47# DSTBN0# DSTBN2# DSTBP0# DSTBP2# DINV0# DINV2# Y26 AA24 T25 U23 V23 R24 R26 R23 AA23 U26 V24 U25 V26 Y23 AA26 Y25 W25 W24 T24 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H23 G25 L23 M26 H24 F25 G24 J23 M23 J25 L26 N24 M25 H26 N25 K25 K24 L24 J26 D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# AB25 AC23 AB24 AC20 AC22 AC25 AD23 AE22 AF23 AD24 AF20 AE21 AD21 AF25 AF22 AF26 AE24 AE25 AD20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 E1 C16 C14 C3 AF7 AC1 E26 FBO(PIN 11) VCCP_GMCH_S0 R33 2KR2F 1 COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# G1 B7 C19 E4 A6 AD26 RSVD2 RSVD3 RSVD4 RSVD5 TEST1 TEST2 C5 F23 GTLREF0 Layout Note: 0.5" max length. COMP0 COMP1 COMP2 COMP3 1 1 1 1 2 2 2 2 27D4R2F 54D9R2F 27D4R2F 54D9R2F H_DPRSLP# 21 H_DPSLP# 21 H_DPWR# 6 2 VCCP_GMCH_S0 R395 200R2J H_PWRGD 21 H_CPUSLP# 6,21 TEST1 TEST2 R392 1KR2 DY BSEL[1:0] Freq.(MHz) LH 100 LL 133 Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" . R402 R403 R35 R36 R29 1KR2 2 1 54D9R2F 1 54D9R2F 1 56R2J 2 150R2 2 39D2R2F 2 680R2 2 27D4R2F 3 H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6 2 2 R391 2 R386 CPU_PROCHOT# 2 R384 XDP_TDI 1 R387 XDP_TMS 1 R389 XDP_TRST# 1 R388 XDP_TCK 1 R390 BSEL0 BSEL1 6 H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 1 VCCP_GMCH_S0 GTLREF 2 1KR2F 1 1 R34 H_CPURST# PSI# P25 P26 AB2 AB1 MISC TCK(PIN A13) XDP_TDO D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# H_D#[63..0] 1 H_RS#0 H_RS#1 H_RS#2 K3 K4 HIT# HITM# ITP Conn. CPU 1 2 B11 H1 K1 L2 M3 Place testpoint on H_IERR# with a GND 0.1" away H_IERR# 2 STPCLK# LINT0 LINT1 SMI# BR0# R396 56R2J 1 C6 D1 D4 B4 21 H_STPCLK# 21 H_INTR 21 H_NMI 21 H_SMI# A20M# FERR# IGNNE# H_DEFER# 6 H_DRDY# 6 H_DBSY# 6 DY 2 C2 D3 A3 L4 H2 M2 1 21 H_A20M# 21 H_FERR# 21 H_IGNNE# 3 A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# ADSTB#1 DEFER# DRDY# DBSY# 4 2 6 H_ADSTB#1 AF4 AC4 AC7 AC3 AD3 AE4 AD2 AB4 AC6 AD5 AE2 AD6 AF3 AE1 AF1 AE5 H_ADS# 6 H_BNR# 6 H_BPRI# 6 1 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 N2 L1 J3 RESET# RS0# RS1# RS2# TRDY# REQ0# REQ1# REQ2# REQ3# REQ4# E VCCP_GMCH_S0 ADS# BNR# BPRI# 2 H_REQ#0 R2 H_REQ#1 P3 H_REQ#2 T2 H_REQ#3 P1 H_REQ#4 T1 A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB#0 CONTROL 6 H_ADSTB#0 6 H_REQ#[4..0] P4 U4 V3 R3 V2 W1 T4 W2 Y4 Y1 U1 AA3 Y3 AA2 U3 ADDR GROUP 1 XTP/ITP SIGNALS 4 HCLK THERM H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 D DATA GRP 0 DATA GRP 2 6 H_A#[31..3] C DATA GRP 1 DATA GRP 3 ADDR GROUP 0 A 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU (1 of 2) Size A3 Document Number All place within 2" to CPU Date: Monday, July 11, 2005 A B C D Rev -1 Leopard2 Sheet E 4 of 47 B C U53D 1 1 2 2 G913C-U DY DY 150u *1 1 1 1 1 1 3 1 1 1 VCCP_GMCH_S0 1 0.1u *10 DY 2 DY R398 49K9R2F BC2 SC1U10V3ZY 2 2 BC85 SC1U10V3ZY 1 1 1 2 0R2-0 2 2 2 2 2 2 2 C20 C29 C30 C25 C16 C28 C31 C22 C32 TC1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 ST100U6D3VM-U 2 C21 VCC_CORE_S0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SC10U6D3V5MX 2 SC10U6D3V5MX 2 SC10U10V5ZY-L 2 SC10U6D3V5MX 2 SC10U10V5ZY-L 2 SC10U10V5ZY-L 2 SC10U10V5ZY-L 2 SC10U10V5ZY-L 2 SC10U10V5ZY-L 2 SC10U10V5ZY-L 2 SC10U10V5ZY-L 2 SC10U10V5ZY-L 2 2 SC10U6D3V5MX 2 C18 C19 C23 C24 C33 C35 C36 C42 C39 C40 DY C41 C50 C318 C319 C321 C322 C323 C325 C324 C326 DY DY DY DY DY DY DY DY DY SC10U10V5ZY-L Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line. 1 R28 SC10U6D3V5MX 2 VCCSENSE and VSSSENSE lines should be of equal length. DY 1D5V_VCCA_SET 1 Layout Note: OUT 4 DY 1 DY 2 2 2 5 SC10U6D3V5MX 2 R39 54D9R2F DY SET 1 R40 54D9R2F SHDN# GND IN SC10U6D3V5MX 2 TP_VSSSENSE 1 2 3 BC84 SC22P 1 TP_VCCSENSE U52 SC10U6D3V5MX 2 AE7 AF6 41 41 41 41 41 41 3D3V_S0 1D5V_S0 1 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 1D5V_VCCA_S0 R397 12K7R3F SC10U6D3V5MX 2 E2 F2 F3 G3 G4 H4 I max = 120 mA SC10U6D3V5MX 2 P23 W4 1D5V_VCCA_S0 2 VCCP_GMCH_S0 2 0R2-0 E 4 1 1 R394 C15 SC10U10V6ZY-U D13 D15 D17 D19 D21 D23 D26 E3 E6 E8 E10 E12 E14 E16 E18 E20 E22 E25 F1 F4 F5 F7 F9 F11 F13 F15 F17 F19 F21 F24 G2 G6 G22 G23 G26 H3 H5 H21 H25 J1 J4 J6 J22 J24 K2 K5 K21 K23 K26 L3 L6 L22 L25 M1 M4 M5 M21 M24 N3 N6 N22 N23 N26 P2 P5 P21 P24 R1 R4 R6 R22 R25 T3 T5 T21 T23 T26 U2 U6 U22 U24 V1 V4 V5 V21 V25 W3 W6 W22 W23 W26 Y2 Y5 Y21 Y24 2 D10 CPU_D10 D12 D14 D16 E11 E13 E15 F10 F12 F14 F16 K6 L21 L5 M22 M6 N21 N5 P22 P6 R21 R5 T22 T6 U21 TP1 TP3 TP20 2 C17 SCD01U16V2KX TP_VCCA1 TP_VCCA2 TP_VCCA3 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 1 F26 B1 N1 AC26 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 2 1 1 1D5V_VCCA_S0 A2 A5 A8 A11 A14 A17 A20 A23 A26 AA1 AA4 AA6 AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA25 AB3 AB5 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB26 AC2 AC5 AC8 AC10 AC12 AC14 AC16 AC18 AC21 AC24 AD1 AD4 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD22 AD25 AE3 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE23 AE26 AF2 AF5 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF24 B3 B6 B9 B12 B16 B19 B22 B25 C1 C4 C7 C10 C13 C15 C18 C21 C24 D2 D5 D7 D9 D11 1 G5 H22 H6 J21 J5 K22 U5 V22 V6 W21 W5 Y22 Y6 1 3 AA11 AA13 AA15 AA17 AA19 AA21 AA5 AA7 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AB6 AB8 AC11 AC13 AC15 AC17 AC19 AC9 AD10 AD12 AD14 AD16 AD18 AD8 AE11 AE13 AE15 AE17 AE19 AE9 AF10 AF12 AF14 AF16 AF18 AF8 D18 D20 D22 D6 D8 E17 E19 E21 E5 E7 E9 F18 F20 F22 F6 F8 G21 PZ47903 62.10055.011 VCC0 VCC59 VCC1 VCC60 VCC2 VCC61 VCC3 VCC62 VCC4 VCC63 VCC5 VCC64 VCC6 VCC65 VCC7 VCC66 VCC8 VCC67 VCC9 VCC68 VCC10 VCC69 VCC11 VCC70 VCC12 VCC71 VCC13 VCC14 VCCA0 VCC15 VCCA1 VCC16 VCCA2 VCC17 VCCA3 VCC18 VCC19 VCCP0 VCC20 VCCP1 VCC21 VCCP2 VCC22 VCCP3 VCC23 VCCP4 VCC24 VCCP5 VCC25 VCCP6 VCC26 VCCP7 VCC27 VCCP8 VCC28 VCCP9 VCC29 VCCP10 VCC30 VCCP11 VCC31 VCCP12 VCC32 VCCP13 VCC33 VCCP14 VCC34 VCCP15 VCC35 VCCP16 VCC36 VCCP17 VCC37 VCCP18 VCC38 VCCP19 VCC39 VCCP20 VCC40 VCCP21 VCC41 VCCP22 VCC42 VCCP23 VCC43 VCCP24 VCC44 VCC45 VCCQ0 VCC46 VCCQ1 VCC47 VCC48 VID0 VCC49 VID1 VCC50 VID2 VCC51 VID3 VCC52 VID4 VCC53 VID5 VCC54 VCC55 VCC56 VCCSENSE VCC57 VCC58 VSSSENSE 2 4 VCC_CORE_S0 U53C 1 VCC_CORE_S0 D PZ47903 62.10055.011 2 A 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU (2 of 2) Size A3 Document Number Date: Sunday, July 03, 2005 A B C D Rev SC Leopard2 Sheet E 5 of 47 A B C D E Trace 10 mil wide with 20 mil spacing 1 H_YRCOMP 1 H_XRCOMP 2 R118 24D9R2F 2 R97 24D9R2F 4 4 Power On Sequencing VCCP_GMCH_S0 U19A Alviso Strapping Signals REV.NO. 1.0 and Configuration REF. NO. 15577 Pin Name Strap Description CFG[2:0] FSB Frequency Select page 183 Configuration 001 = FSB533 101 = FSB400 others = Reversed CFG[4:3] Reserved CFG5 DMI x2 Select 2 CFG6 Reserved CFG7 CPU Strap CFG8 Reserved CFG9 PCI Express Graphics Lane Reversal CFG[11:10] Reserved CFG[13:12] XOR/ALL Z test straps CFG[15:14] Reversed CFG16 FSB Dynamic ODT 0 = DMI x2 1 = DMI x4 0 = DDR2 1 = DDR1 (Default) (Default) 0 = Reserved 1 = Dothan (Default) 0 = Reserve Lanes 1 = Normal (Default) 00 01 10 11 = = = = Reserved XOR mode enabled All Z mode enabled Normal Operation Reversed CFG18 GMCH core VCC Select 0 = 1.05V (Default) 1 = 1.5V CFG19 CPU VTT Select 0 = 1.05V (Default) 1 = 1.2V CFG20 Reversed SDVOCRTL _DATA SDVO Present C1 C2 D1 T1 L1 P1 HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWING 0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default) CFG17 1 (Default) H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING HADS# HADSTB#0 HADSTB#1 HVREF HBNR# HBPRI# HBREQ0# HCPURST# F8 B9 E13 J11 A5 D5 E7 H10 H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 HCLKINN HCLKINP AB1 AB2 CLK_MCH_BCLK# 3 CLK_MCH_BCLK 3 HDBSY# HDEFER# HDINV#0 HDINV#1 HDINV#2 HDINV#3 HDPWR# HDRDY# HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 HEDRDY# HHIT# HHITM# HLOCK# HPCREQ# HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HRS0# HRS1# HRS2# HCPUSLP# HTRDY# C6 E6 H8 K3 T7 U5 G6 F7 G4 K1 R3 V3 G5 K2 R2 W4 F6 D4 D6 B3 A11 A7 D7 B8 C7 A8 A4 C5 B4 G8 B5 H_DBSY# 4 H_DEFER# 4 Vccp Vcc_mch 10~30uS MCH_PWERGD 3 VCCP_GMCH_S0 3~10mS R457 100R2F H_BNR# 4 H_BPRI# 4 H_BREQ#0 4 H_CPURST# 4 CLK_ENABLE# VGATE TO ICH6 H_VREF C384 R458 200R2F SCD1U10V2KX H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 CORE_GMCH_S0 H_DINV#[3..0] 4 R519 0R2-0 DY H_DPWR# 4 H_DRDY# 4 H_DSTBN#[3..0] 4 H_DSTBP#[3..0] 4 H_REQ#[4..0] 4 H_DPWR# 2 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 H_CPUSLP#_GMCH H_RS#[2..0] H_TRDY# 4 1 R54 2 0R0402-PAD 4 H_CPUSLP# 4,21 ALVISO-GM 1 Wistron Corporation 0 = No SDVO device present (Default) 1= SDVO device present NOTE: All strap signals are sampled with respect to the leading edge of the Alviso GMCH PWORK In signal. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. ALVISO-GM:71.0GMCH.08U ALVISO-PM:71.0GMCH.0BU ALVISO-GML:71.0GMCH.0JU Title GMCH (1 of 5) Size A3 Document Number Date: Monday, July 11, 2005 A Vvid >100uS <10uS 1 Trace 10 mil wide with 20 mil spacing Vboot Vboot Vcc_core 1 2 1 C128 SCD1U16V 2 2 1 R117 100R2F C95 SCD1U16V VR_ON 2 H_YSWING 1 R95 100R2F 2 1 H_XSWING G9 C9 E9 B7 A10 F9 D8 B10 E10 G10 D9 E11 F10 G11 G13 C10 C11 D11 C12 B13 A12 F12 G12 E12 C13 B11 D13 A13 F13 1 R116 221R3F 2 2 R105 221R3F VID 4 >3mS H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# 2 1 VCCP_GMCH_S0 1 VCCP_GMCH_S0 HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# 1 H_YSCOMP E4 E1 F4 H7 E2 F1 E3 D3 K7 F2 J7 J8 H6 F3 K8 H5 H1 H2 K5 K6 J4 G3 H3 J1 L5 K4 J5 P7 L7 J3 P5 L3 U7 V6 R6 R5 P3 T8 R7 R8 U8 R4 T4 T5 R1 T3 V8 U6 W6 U3 V5 W8 W7 U2 U1 Y5 Y2 V4 Y7 W1 W3 Y3 Y6 W2 2 H_XSCOMP H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 HOST 1 R109 54D9R2F 1 R96 54D9R2F 3 H_A#[31..3] 2 2 4 H_D#[63..0] 2 VCCP_GMCH_S0 B C D Rev -1 Leopard2 Sheet E 6 of 47 A B C D E Alviso will provide SDVO_CTRLCLK and CTRLDATA pulldowns on-die DMITXN0 DMITXN1 DMITXN2 DMITXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 Y33 AA37 AB33 AC37 DMITXP0 DMITXP1 DMITXP2 DMITXP3 AM33 AL1 AE11 AJ34 AF6 AC10 SM_CK0 SM_CK1 SM_CK2 SM_CK3 SM_CK4 SM_CK5 AN33 AK1 AE10 AJ33 AF5 AD10 SM_CK0# SM_CK1# SM_CK2# SM_CK3# SM_CK4# SM_CK5# SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3 22 DMI_RXP[3..0] 11 M_CLK_DDR0 11 M_CLK_DDR1 11 M_CLK_DDR3 11 M_CLK_DDR4 11 M_CLK_DDR#0 11 M_CLK_DDR#1 11 M_CLK_DDR#3 11 M_CLK_DDR#4 11,12 11,12 11,12 11,12 M_CS#0 M_CS#1 M_CS#2 M_CS#3 AN16 AM14 AH15 AG16 SM_CS0# SM_CS1# SM_CS2# SM_CS3# AF22 AF16 SM_OCDCOMP0 SM_OCDCOMP1 AP14 AL15 AM11 AN10 SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3 AK10 AK11 AF37 AD1 AE27 AE28 AF9 AF10 SMRCOMPN SMRCOMPP SMVREF0 SMVREF1 SMXSLEWIN SMXSLEWOUT SMYSLEWIN SMYSLEWOUT M_OCDCOMP0 M_OCDCOMP1 R534 11,12 M_ODT0 40D2R2F 11,12 M_ODT1 11,12 M_ODT2 11,12 M_ODT3 DDR_VREF_S3 1 2 M_RCOMPN M_RCOMPP SMXSLEW 2 2 2 R535 40D2R2F C154 SMYSLEW SCD1U10V2MX-1 MUXING AP21 AM21 AH21 AK21 1 1 Layout Note: Route as short as possible M_CKE0 M_CKE1 M_CKE2 M_CKE3 BM_BUSY# EXT_TS0# EXT_TS1# THRMTRIP# PWROK RSTIN# R494 1 R495 1 DREF_CLKN DREF_CLKP DREF_SSCLKN DREF_SSCLKP NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 PM_BMBUSY# 22 PM_THRMTRIP-A# 4,21 PWROK 25 2 PLT_RST1# 13,24,26 100R2 DREFCLK# 3 DREFCLK 3 DREFSSCLK# 3 DREFSSCLK 3 Note: Intel design guide suggest(page 203) If the LVDS interface is not implementd, all signals associated with the interface can be left as no connects. AP37 AN37 AP36 AP2 AP1 AN1 B1 A2 B37 A36 A37 When Low 2.2K Ohm 1 R498 PM_EXTTS#0 2 10KR2 Ref ALVISO EDS-1 Page 115 VCCP_GMCH_S0 1 R471 PM_EXTTS#1 2 10KR2 R543 80D6R2F R420 1KR2 2 R437 10KR2 2 2 CFG2 CFG1 CFG0 R438 R419 4K7R2 4K7R2 CFG(2..1) FREQ.(MHz) 10 400 00 533 11 Reserved 2 2 DY DY 2 CPU_SEL0 3,4 CPU_SEL1 3,4 1 1 1 For Dothan-B M_RCOMPN M_RCOMPP 1 2 R533 80D6R2F 1 1 1 R465 10KR2 1 FOR DDR2 1D8V_S3 CFG2=0(R419):133MHZ CFG2=1(R420):100MHZ A B 1 R441 1 R440 1 R464 1 R469 1 R442 1 R461 1 R439 1 R468 1 R69 1 R466 1 R459 1 R467 1 R463 1 R460 1 R462 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 2K2R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 20R2-0 20R2-0 termination resistors close to GMCH ALVISO-GM 2D5V_S0 2 0R2-0 2 0R2-0 Intel design guide suggest Ref no.:14511 page 210 J23 J21 PM_EXTTS#0 H22 PM_EXTTS#1 F5 AD30 RST1# 1 AE29 R536 A24 A23 C37 D37 H24 H25 AB29 AC29 SDVOCTRL_DATA SDVOCTRL_CLK GCLKN GCLKP A15 C16 A17 J18 B15 B16 B17 TVDAC_A TVDAC_B TVDAC_C TV_REFSET TV_IRTNA TV_IRTNB TV_IRTNC E24 E23 E21 D21 C20 B20 A19 B19 H21 G21 J20 DDCCLK DDCDATA BLUE BLUE# GREEN GREEN# RED RED# VSYNC HSYNC REFSET E25 F25 C23 C22 F23 F22 F26 C33 C31 F28 F27 LBKLT_CRTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL B30 B29 C25 C24 LACLKN LACLKP LBCLKN LBCLKP B34 B33 B32 LADATAN0 LADATAN1 LADATAN2 CFG3 CFG4 A34 A33 B31 LADATAP0 LADATAP1 LADATAP2 C29 D28 C27 LBDATAN0 LBDATAN1 LBDATAN2 C28 D27 C26 LBDATAP0 LBDATAP1 LBDATAP2 EXP_COMPI EXP_ICOMPO EXP_RXN0 EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8 EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15 E30 F34 G30 H34 J30 K34 L30 M34 N30 P34 R30 T34 U30 V34 W30 Y34 PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 EXP_RXP0 EXP_RXP1 EXP_RXP2 EXP_RXP3 EXP_RXP4 EXP_RXP5 EXP_RXP6 EXP_RXP7 EXP_RXP8 EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15 D30 E34 F30 G34 H30 J34 K30 L34 M30 N34 P30 R34 T30 U34 V30 W34 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 EXP_TXN0 EXP_TXN1 EXP_TXN2 EXP_TXN3 EXP_TXN4 EXP_TXN5 EXP_TXN6 EXP_TXN7 EXP_TXN8 EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15 E32 F36 G32 H36 J32 K36 L32 M36 N32 P36 R32 T36 U32 V36 W32 Y36 TXN0 C372 1 TXN1 C1071 TXN2 C387 1 TXN3 C1081 TXN4 C386 1 TXN5 C1161 TXN6 C409 1 TXN7 C1181 TXN8 C410 1 TXN9 C1171 TXN10 C430 1 TXN11 C1311 TXN12 C429 1 TXN13 C1301 TXN14 C452 1 TXN15 C1421 2 EXP_TXP0 EXP_TXP1 EXP_TXP2 EXP_TXP3 EXP_TXP4 EXP_TXP5 EXP_TXP6 EXP_TXP7 EXP_TXP8 EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15 D32 E36 F32 G36 H32 J36 K32 L36 M32 N36 P32 R36 T32 U36 V32 W36 TXP0 C373 1 TXP1 C97 1 TXP2 C389 1 TXP3 C1061 TXP4 C388 1 TXP5 C1051 TXP6 C407 1 TXP7 C1191 TXP8 C408 1 TXP9 C1151 TXP10 C431 1 TXP11 C1291 TXP12 C432 1 TXP13 C1321 TXP14 C453 1 TXP15 C1431 2 CFG5 CFG6 CFG7 PEG_COMP 2 R473 D36 D34 CORE_GMCH_S0 Note: CRT_RED, CRT_GREEN, CRT_BLUE, are ground referenced. Place 150 Ohm 11,12 11,12 11,12 11,12 SDVO_DAT SDVO_CLK 3 CLK_MCH_3GPLL# 3 CLK_MCH_3GPLL R493 1 R492 1 DDR 3 TPAD30 TP22 TPAD30 TP23 1D5V_S0 U19G Intel suggest NC Due to votusly DVO CFG2 PCI-EXPRESS GRAPHICS AA33 AB37 AC33 AD37 2 1KR2 MISC DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 22 DMI_RXN[3..0] CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 1 R52 TV DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3 CFG0 CFG1 G16 H13 G14 F16 F15 G15 E16 D17 J16 D15 E15 D14 E14 H12 C14 H15 J15 H14 G22 G23 D23 G25 G24 J17 A31 A30 D26 D25 VGA Y31 AA35 AB31 AC35 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 LVDS DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 CFG/RSVD 22 DMI_TXP[3..0] PM DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3 CLK AA31 AB35 AC31 AD35 4 NC DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI U19B 22 DMI_TXN[3..0] 2D5V_S0 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG16 2 2 2 2 2 2 2 2 2 2 2 2 2 PEG_RXN[15..0] 13 PEG_RXP[15..0] 13 3 PEG_TXN0 PEG_TXN1 2SCD1U16V SCD1U16V PEG_TXN2 SCD1U16V 2 PEG_TXN3 SCD1U16V PEG_TXN4 PEG_TXN5 2SCD1U16V SCD1U16V PEG_TXN6 PEG_TXN7 2SCD1U16V SCD1U16V PEG_TXN8 PEG_TXN9 2SCD1U16V SCD1U16V PEG_TXN10 PEG_TXN11 2SCD1U16V SCD1U16V PEG_TXN12 PEG_TXN13 2SCD1U16V SCD1U16V PEG_TXN14 PEG_TXN15 2SCD1U16V SCD1U16V PEG_TXP0 SCD1U16V 2 PEG_TXP1 SCD1U16V PEG_TXP2 PEG_TXP3 2SCD1U16V SCD1U16V PEG_TXP4 SCD1U16V 2 PEG_TXP5 SCD1U16V PEG_TXP6 PEG_TXP7 2SCD1U16V SCD1U16V PEG_TXP8 SCD1U16V 2 PEG_TXP9 SCD1U16V PEG_TXP10 PEG_TXP11 2SCD1U16V SCD1U16V PEG_TXP12 SCD1U16V 2 PEG_TXP13 SCD1U16V PEG_TXP14 PEG_TXP15 2SCD1U16V SCD1U16V PEG_TXN[15..0] 13 PEG_TXP[15..0] 13 2 ALVISO-GM CFG8 CFG15 2 4 1 24D9R2F When High 1K Ohm 1 R470 1 R497 1 R496 CFG18 2 DUMMY-R2 2 DUMMY-R2 2 DUMMY-R2 CFG19 CFG20 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Strapping Title CFG17 CFG[17:3] have internal pullup resistors. CFG[19:18] have internal pulldown resistors C D GMCH (2 of 5) Size A3 Document Number Date: Thursday, July 07, 2005 Rev -1 Leopard2 Sheet E 7 of 47 A B C D E 4 4 U19C U19D 3 2 AG35 AH35 AL35 AL37 AH36 AJ35 AK37 AL34 AM36 AN35 AP32 AM31 AM34 AM35 AL32 AM32 AN31 AP31 AN28 AP28 AL30 AM30 AM28 AL28 AP27 AM27 AM23 AM22 AL23 AM24 AN22 AP22 AM9 AL9 AL6 AP7 AP11 AP10 AL7 AM7 AN5 AN6 AN3 AP3 AP6 AM6 AL4 AM3 AK2 AK3 AG2 AG1 AL3 AM2 AH3 AG3 AF3 AE3 AD6 AC4 AF2 AF1 AD4 AD5 SADQ0 SADQ1 SADQ2 SADQ3 SADQ4 SADQ5 SADQ6 SADQ7 SADQ8 SADQ9 SADQ10 SADQ11 SADQ12 SADQ13 SADQ14 SADQ15 SADQ16 SADQ17 SADQ18 SADQ19 SADQ20 SADQ21 SADQ22 SADQ23 SADQ24 SADQ25 SADQ26 SADQ27 SADQ28 SADQ29 SADQ30 SADQ31 SADQ32 SADQ33 SADQ34 SADQ35 SADQ36 SADQ37 SADQ38 SADQ39 SADQ40 SADQ41 SADQ42 SADQ43 SADQ44 SADQ45 SADQ46 SADQ47 SADQ48 SADQ49 SADQ50 SADQ51 SADQ52 SADQ53 SADQ54 SADQ55 SADQ56 SADQ57 SADQ58 SADQ59 SADQ60 SADQ61 SADQ62 SADQ63 SA_BS0# SA_BS1# SA_BS2# AK15 AK16 AL21 SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7 AJ37 AP35 AL29 AP24 AP9 AP4 AJ2 AD3 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 AK36 AP33 AN29 AP23 AM8 AM4 AJ1 AE5 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7# AK35 AP34 AN30 AN23 AN8 AM5 AH1 AE4 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 AL17 AP17 AP18 AM17 AN18 AM18 AL19 AP20 AM19 AL20 AM16 AN20 AM20 AM15 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 SA_CAS# SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE# AN15 AP16 AF29 AF28 AP15 GMCH_TP48 GMCH_TP49 M_A_BS#0 11,12 M_A_BS#1 11,12 M_A_BS#2 11,12 M_A_DM[7..0] 11 11 M_B_DQ[63..0] M_A_DQS[7..0] 11 M_A_DQS#[7..0] 11 M_A_A[13..0] 11,12 M_A_CAS# 11,12 M_A_RAS# 11,12 TP29 TPAD30 TP28 TPAD30 M_A_WE# 11,12 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 AE31 AE32 AG32 AG36 AE34 AE33 AF31 AF30 AH33 AH32 AK31 AG30 AG34 AG33 AH31 AJ31 AK30 AJ30 AH29 AH28 AK29 AH30 AH27 AG28 AF24 AG23 AJ22 AK22 AH24 AH23 AG22 AJ21 AG10 AG9 AG8 AH8 AH11 AH10 AJ9 AK9 AJ7 AK6 AJ4 AH5 AK8 AJ8 AJ5 AK4 AG5 AG4 AD8 AD9 AH4 AG6 AE8 AD7 AC5 AB8 AB6 AA8 AC8 AC7 AA4 AA5 SBDQ0 SBDQ1 SBDQ2 SBDQ3 SBDQ4 SBDQ5 SBDQ6 SBDQ7 SBDQ8 SBDQ9 SBDQ10 SBDQ11 SBDQ12 SBDQ13 SBDQ14 SBDQ15 SBDQ16 SBDQ17 SBDQ18 SBDQ19 SBDQ20 SBDQ21 SBDQ22 SBDQ23 SBDQ24 SBDQ25 SBDQ26 SBDQ27 SBDQ28 SBDQ29 SBDQ30 SBDQ31 SBDQ32 SBDQ33 SBDQ34 SBDQ35 SBDQ36 SBDQ37 SBDQ38 SBDQ39 SBDQ40 SBDQ41 SBDQ42 SBDQ43 SBDQ44 SBDQ45 SBDQ46 SBDQ47 SBDQ48 SBDQ49 SBDQ50 SBDQ51 SBDQ52 SBDQ53 SBDQ54 SBDQ55 SBDQ56 SBDQ57 SBDQ58 SBDQ59 SBDQ60 SBDQ61 SBDQ62 SBDQ63 SB_BS0# SB_BS1# SB_BS2# AJ15 AG17 AG21 SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7 AF32 AK34 AK27 AK24 AJ10 AK5 AE7 AB7 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 AF34 AK32 AJ28 AK23 AM10 AH6 AF8 AB4 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7# AF35 AK33 AK28 AJ23 AL10 AH7 AF7 AB5 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 AH17 AK17 AH18 AJ18 AK18 AJ19 AK19 AH19 AJ20 AH20 AJ16 AG18 AG20 AG15 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 SB_CAS# SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE# AH14 AK14 AF15 AF14 AH16 DDR SYSTEM MEMORY B M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 DDR SYSTEM MEMORY A 11 M_A_DQ[63..0] GMCH_TP50 GMCH_TP51 M_B_BS#0 11,12 M_B_BS#1 11,12 M_B_BS#2 11,12 M_B_DM[7..0] 11 M_B_DQS[7..0] 11 M_B_DQS#[7..0] 11 3 M_B_A[13..0] 11,12 M_B_CAS# 11,12 M_B_RAS# 11,12 TP27 TPAD30 TP26 TPAD30 2 M_B_WE# 11,12 ALVISO-GM ALVISO-GM 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title GMCH (3 of 5) Size A3 Document Number Date: Thursday, July 07, 2005 A B C D Rev -1 Leopard2 Sheet E 8 of 47 A B 2 IND-D1UH C370 SC10U6D3V5MX 2 IND-D1UH C139 SC10U6D3V5MX 2 IND-D1UH C153 SC10U6D3V5MX DY C141 SCD1U10V2MX-1 1D5V_MPLL_S0 C140 SCD1U10V2MX-1 C L2 2 1D5V_DPLLA_S0 C77 SCD1U10V2MX-1 1D5V_DPLLB_S0 2D5V_S0 D6 VCCP_GMCH_S0 1 R55 2 1 10R2 C371 SCD1U10V2MX-1 C103 C102 C114 SC10U10V6ZY-U SCD1U10V2MX-1 ST100U6D3VM-U DY Size A3 D F37 G37 2 1 1 2 DY VCCP_GMCH_S0 Date: Thursday, July 07, 2005 2 2 1 1 C385 C451 SC10U10V5ZY-L SC10U10V5ZY-L 2 1 1 2 2 1 1 2 2 1 2D5V_S0 2D5V_TXLVDS_S0 C82 SC4D7U10V5ZY SCD1U10V2MX-1 2D5V_TXLVDS_S0 C74 C73 SCD47U16V3ZY SCD47U16V3ZY C127 1 1D8V_S3 VCCA_3GBG VSSA_3GBG DY 2 C164 1 TC9 ST100U4VBM-U C159 SCD1U10V2MX-1 1 VCCP_GMCH_S0 2 2 1 1 G12 2 2 C83 SCD01U16V3KX SCD1U10V2MX-1 Y29 Y28 Y27 Note: All VCCSM pins shorted internally AE37 W37 U37 R37 N37 L37 J37 2 1 G13 2 1D5V_HMPLL_S0 2D5V_ALVDS_S0 VCCA_3GPLL0 VCCA_3GPLL1 VCCA_3GPLL2 Note: All VCCSM pins shorted internally VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6 FOR DDR2 AF20 AP19 AF19 AF18 C449 C447 SC10U10V5ZY-L SC10U10V5ZY-L C80 SC10U10V5ZY-L SCD1U10V2MX-1 2 CORE_GMCH_S0 GAP-CLOSE-PWR C81 VCCA_SM0 VCCA_SM1 VCCA_SM2 VCCA_SM3 1 VCCTX_LVDS0 VCCTX_LVDS1 VCCTX_LVDS2 1 2D5V_S0 1 2 GAP-CLOSE-PWR C84 B28 A28 A27 GAP-CLOSE-PWR C75 SC10U10V5ZY-L 1 1 2 2 4 1 GMCH_CORE_VCC 2 2 VCC_SYNC 1 1 C 2 C78 SC10U6D3V5MX 2 K13 VTT0 J13 VTT1 K12 VTT2 W11 VTT3 V11 VTT4 U11 VTT5 T11 VTT6 R11 VTT7 P11 VTT8 N11 VTT9 M11 VTT10 L11 VTT11 K11 VTT12 W10 VTT13 V10 VTT14 U10 VTT15 T10 VTT16 R10 VTT17 P10 VTT18 N10 VTT19 M10 VTT20 K10 VTT21 J10 VTT22 Y9 VTT23 W9 VTT24 U9 VTT25 R9 VTT26 P9 VTT27 N9 VTT28 M9 VTT29 L9 VTT30 J9 VTT31 N8 VTT32 M8 VTT33 N7 VTT34 M7 VTT35 N6 VTT36 M6 VTT37 A6 VTT38 1VCCP_GMCH_CAP1 N5 VTT39 M5 VTT40 N4 VTT41 M4 VTT42 1 N3 VTT43 M3 VTT44 N2 VTT45 M2 VTT46 VCCP_GMCH_CAP2 B2 VTT47 VCCP_GMCH_CAP3 V1 VTT48 N1 VTT49 M1 VTT50 VCCP_GMCH_CAP4 G1 VTT51 GAP-CLOSE-PWR C79 1 L13 2 C165 SCD1U10V2MX-1 H20 C161 SCD1U10V2MX-1 VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC G10 F19 E19 G19 C76 VCCH_MPLL1 VCCH_MPLL0 VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL 1D5V_S0 2 L11 1 2D5V_S0 1 1 SCD1U10V2MX-1 2 1 1 AC2 AC1 B23 C35 AA1 AA2 2 2D5V_TVDAC_S0 1 1 1 1 1 2 1 2 IND-D1UH 2 1 C160 SCD1U10V2MX-1 SCD1U10V2MX-1 V1.8_DDR_CAP1 2 AM37 V1.8_DDR_CAP2 2 AH37 1 AP29 V1.8_DDR_CAP5 AD28 AD27 AC27 AP26 AN26 AM26 AL26 AK26 AJ26 AH26 AG26 AF26 AE26 AP25 AN25 AM25 AL25 AK25 AJ25 AH25 AG25 AF25 AE25 AE24 AE23 AE22 2 1 AE21 AE20 AE19 AE18 2 1 AE17 AE16 AE15 AE14 AP13 AN13 AM13 AL13 AK13 AJ13 2 1 AH13 AG13 AF13 AE13 AP12 AN12 AM12 AL12 AK12 AJ12 AH12 AG12 AF12 AE12 AD11 AC11 AB11 AB10 AB9 AP8 V1.8_DDR_CAP6 V1.8_DDR_CAP4 AM1 2 V1.8_DDR_CAP3 AE1 2 1 B22 B21 A21 A35 B26 B25 A25 D19 H17 H18 G18 B 2 L31 1 2 1D5V_S0 2 GAP-CLOSE-PWR 1 G53 1 1 2 C406 C405 C428 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 1 VCCSM0 VCCSM1 VCCSM2 VCCSM3 VCCSM4 VCCSM5 VCCSM6 VCCSM7 VCCSM8 VCCSM9 VCCSM10 VCCSM11 VCCSM12 VCCSM13 VCCSM14 VCCSM15 VCCSM16 VCCSM17 VCCSM18 VCCSM19 VCCSM20 VCCSM21 VCCSM22 VCCSM23 VCCSM24 VCCSM25 VCCSM26 VCCSM27 VCCSM28 VCCSM29 VCCSM30 VCCSM31 VCCSM32 VCCSM33 VCCSM34 VCCSM35 VCCSM36 VCCSM37 VCCSM38 VCCSM39 VCCSM40 VCCSM41 VCCSM42 VCCSM43 VCCSM44 VCCSM45 VCCSM46 VCCSM47 VCCSM48 VCCSM49 VCCSM50 VCCSM51 VCCSM52 VCCSM53 VCCSM54 VCCSM55 VCCSM56 VCCSM57 VCCSM58 VCCSM59 VCCSM60 VCCSM61 VCCSM62 VCCSM63 VCCSM64 VCCHV0 VCCHV1 VCCHV2 VCCA_LVDS VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2 VCCD_TVDAC VCCDQ_TVDAC VCCA_TVBG VSSA_TVBG 2D5V_ALVDS_S0 2 1 1 C403 C404 SC10U10V5ZY-L SC10U10V5ZY-L F17 E17 D18 C18 F18 E18 3 1 2 C63 1 2 2 U59 VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1 U19E 1 VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 1 2D5V_S0 2 T29 R29 N29 M29 K29 J29 V28 U28 T28 R28 P28 N28 M28 L28 K28 J28 H28 G28 V27 U27 T27 R27 P27 N27 M27 L27 K27 J27 H27 K26 H26 K25 J25 K24 K23 K22 K21 W20 U20 T20 K20 V19 U19 K19 W18 V18 T18 K18 K17 APL5308-25AC-TR SCD1U10V2MX-1 1 1 2 2 C359 SC4D7U6D3V5KX 1D5V_DLVDS_S0 2 1 1 SC10U10V5ZY-L 2 2 C448 1 1 VOUT VIN GND 2 1 2 3 2 1 3D3V_S0 POWER 2 A 1D5V_DLVDS_S0 D E G11 2 1D5V_DDRDLL_S0 G15 2 1D5V_S0 C472 GAP-CLOSE-PWR C166 ST100U6D3VM-U SCD1U10V2MX-1 2 4 1D5V_PCIE_S0 1 G55 2 1D5V_S0 GAP-CLOSE-PWR TC22 ST100U6D3VM-U DY 1D5V_3GPLL_S0 1D5V_S0 G54 1 2 GAP-CLOSE-PWR C473 SC10U10V5ZY-L C450 SCD1U10V2MX-1 C158 SCD1U10V2MX-1 2D5V_3GBG_S0 1 G14 Sheet E 2 2D5V_S0 9 3 C96 GAP-CLOSE-PWR SCD1U10V2MX-1 2 C104 SCD22U16V3ZY SCD22U16V3ZY VCCP_GMCH_S0 C427 C426 SC4D7U10V5ZY SC4D7U10V5ZY DY SSM5818SL 1D5V_HPLL_S0 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Document Number GMCH (4 of 5) Leopard2 of Rev 47 -1 ALVISO-GM VCCP_GMCH_S0 A B VSS_NCTF68 VSS_NCTF67 VSS_NCTF66 VSS_NCTF65 VSS_NCTF64 VSS_NCTF63 VSS_NCTF62 VSS_NCTF61 VSS_NCTF60 VSS_NCTF59 VSS_NCTF58 VSS_NCTF57 VSS_NCTF56 VSS_NCTF55 VSS_NCTF54 VSS_NCTF53 VSS_NCTF52 VSS_NCTF51 VSS_NCTF50 VSS_NCTF49 VSS_NCTF48 VSS_NCTF47 VSS_NCTF46 VSS_NCTF45 VSS_NCTF44 VSS_NCTF43 VSS_NCTF42 VSS_NCTF41 VSS_NCTF40 VSS_NCTF39 VSS_NCTF38 VSS_NCTF37 VSS_NCTF36 VSS_NCTF35 VSS_NCTF34 VSS_NCTF33 VSS_NCTF32 VSS_NCTF31 VSS_NCTF30 VSS_NCTF29 VSS_NCTF28 VSS_NCTF27 VSS_NCTF26 VSS_NCTF25 VSS_NCTF24 VSS_NCTF23 VSS_NCTF22 VSS_NCTF21 VSS_NCTF20 VSS_NCTF19 VSS_NCTF18 VSS_NCTF17 VSS_NCTF16 VSS_NCTF15 VSS_NCTF14 VSS_NCTF13 VSS_NCTF12 VSS_NCTF11 VSS_NCTF10 VSS_NCTF9 VSS_NCTF8 VSS_NCTF7 VSS_NCTF6 VSS_NCTF5 VSS_NCTF4 VSS_NCTF3 VSS_NCTF2 VSS_NCTF1 VSS_NCTF0 U19H Y12 AA12 Y13 AA13 L14 M14 N14 P14 R14 T14 U14 V14 W14 Y14 AA14 AB14 L15 M15 N15 P15 R15 T15 U15 V15 W15 Y15 AA15 AB15 L16 M16 N16 P16 R16 T16 U16 V16 W16 Y16 AA16 AB16 R17 Y17 AA17 AB17 AA18 AB18 AA19 AB19 AA20 AB20 R21 Y21 AA21 AB21 Y22 AA22 AB22 Y23 AA23 AB23 Y24 AA24 AB24 Y25 AA25 AB25 Y26 AA26 AB26 VTT_NCTF17 VTT_NCTF16 VTT_NCTF15 VTT_NCTF14 VTT_NCTF13 VTT_NCTF12 VTT_NCTF11 VTT_NCTF10 VTT_NCTF9 VTT_NCTF8 VTT_NCTF7 VTT_NCTF6 VTT_NCTF5 VTT_NCTF4 VTT_NCTF3 VTT_NCTF2 VTT_NCTF1 VTT_NCTF0 VCC_NCTF78 VCC_NCTF77 VCC_NCTF76 VCC_NCTF75 VCC_NCTF74 VCC_NCTF73 VCC_NCTF72 VCC_NCTF71 VCC_NCTF70 VCC_NTTF69 VCC_NCTF68 VCC_NCTF67 VCC_NCTF66 VCC_NCTF65 VCC_NCTF64 VCC_NCTF63 VCC_NCTF62 VCC_NCTF61 VCC_NCTF60 VCC_NCTF59 VCC_NCTF58 VCC_NCTF57 VCC_NCTF56 VCC_NCTF55 VCC_NCTF54 VCC_NCTF53 VCC_NCTF52 VCC_NCTF51 VCC_NCTF50 VCC_NCTF49 VCC_NCTF48 VCC_NCTF47 VCC_NCTF46 VCC_NCTF45 VCC_NCTF44 VCC_NCTF43 VCC_NCTF42 VCC_NCTF41 VCC_NCTF40 VCC_NCTF39 VCC_NCTF38 VCC_NCTF37 VCC_NCTF36 VCC_NCTF35 VCC_NCTF34 VCC_NCTF33 VCC_NCTF32 VCC_NCTF31 VCC_NCTF30 VCC_NCTF29 VCC_NCTF28 VCC_NCTF27 VCC_NCTF26 VCC_NCTF25 VCC_NCTF24 VCC_NCTF23 VCC_NCTF22 VCC_NCTF21 VCC_NCTF20 VCC_NCTF19 VCC_NCTF18 VCC_NCTF17 VCC_NCTF16 VCC_NCTF15 VCC_NCTF14 VCC_NCTF13 VCC_NCTF12 VCC_NCTF11 VCC_NCTF10 VCC_NCTF9 VCC_NCTF8 VCC_NCTF7 VCC_NCTF6 VCC_NCTF5 VCC_NCTF4 VCC_NCTF3 VCC_NCTF2 VCC_NCTF1 VCC_NCTF0 L17 M17 N17 P17 T17 U17 V17 W17 L18 M18 N18 P18 R18 Y18 L19 M19 N19 P19 R19 Y19 L20 M20 N20 P20 R20 Y20 L21 M21 N21 P21 T21 U21 V21 W21 L22 M22 N22 P22 R22 T22 U22 V22 W22 L23 M23 N23 P23 R23 T23 U23 V23 W23 L24 M24 N24 P24 R24 T24 U24 V24 W24 L25 M25 N25 P25 R25 T25 U25 V25 W25 L26 M26 N26 P26 R26 T26 U26 V26 W26 AB12 AC12 AD12 AB13 AC13 AD13 AC14 AD14 AC15 AD15 AC16 AD16 AC17 AD17 AC18 AD18 AC19 AD19 AC20 AD20 AC21 AD21 AC22 AD22 AC23 AD23 AC24 AD24 AC25 AD25 AC26 AD26 1D8V_S3 L12 M12 N12 P12 R12 T12 U12 V12 W12 L13 M13 N13 P13 R13 T13 U13 V13 W13 2 VCCSM_NCTF31 VCCSM_NCTF30 VCCSM_NCTF29 VCCSM_NCTF28 VCCSM_NCTF27 VCCSM_NCTF26 VCCSM_NCTF25 VCCSM_NCTF24 VCCSM_NCTF23 VCCSM_NCTF22 VCCSM_NCTF21 VCCSM_NCTF20 VCCSM_NCTF19 VCCSM_NCTF18 VCCSM_NCTF17 VCCSM_NCTF16 VCCSM_NCTF15 VCCSM_NCTF14 VCCSM_NCTF13 VCCSM_NCTF12 VCCSM_NCTF11 VCCSM_NCTF10 VCCSM_NCTF9 VCCSM_NCTF8 VCCSM_NCTF7 VCCSM_NCTF6 VCCSM_NCTF5 VCCSM_NCTF4 VCCSM_NCTF3 VCCSM_NCTF2 VCCSM_NCTF1 VCCSM_NCTF0 ALVISO-GM VSS271 VSS270 VSS269 VSS268 VSS260 VSS259 VSS258 VSS257 VSS256 VSS255 VSS254 VSS253 VSS252 VSS251 VSS250 VSS249 VSS248 VSS247 VSS246 VSS245 VSS244 VSS243 VSS242 VSS241 VSS240 VSS239 VSS238 VSS237 VSS236 VSS235 VSS234 VSS233 VSS232 VSS231 VSS230 VSS229 VSS228 VSS227 VSS226 VSS225 VSS224 VSS223 VSS222 VSS221 VSS220 VSS219 VSS218 VSS217 VSS216 VSS215 VSS214 VSS213 VSS212 VSS211 VSS210 VSS209 VSS208 VSS207 VSS206 VSS205 VSS204 VSS203 VSS202 VSS201 VSS200 VSS199 VSS198 VSS197 VSS196 VSS195 VSS194 VSS193 VSS192 VSS191 VSS190 VSS189 VSS188 VSS187 VSS186 VSS185 VSS184 VSS183 VSS182 VSS181 VSS180 VSS179 VSS178 VSS177 VSS176 VSS175 VSS174 VSS173 VSS172 VSS171 VSS170 VSS169 VSS168 VSS167 VSS166 VSS165 VSS164 VSS163 VSS162 VSS161 VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS150 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131 VSS130 VSSALVDS VSS267 VSS266 VSS265 VSS264 VSS263 VSS262 VSS261 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100 VSS99 VSS98 VSS97 VSS96 VSS95 VSS94 VSS93 VSS92 VSS91 VSS90 VSS89 VSS88 VSS87 VSS86 VSS85 VSS84 VSS83 VSS82 VSS81 VSS80 VSS79 VSS78 VSS77 VSS76 VSS75 VSS74 VSS73 VSS72 VSS71 VSS70 VSS69 VSS68 VSS67 VSS66 VSS65 VSS64 VSS63 VSS62 VSS61 VSS60 VSS59 VSS58 VSS57 VSS56 VSS55 VSS54 VSS53 VSS52 VSS51 VSS50 VSS49 VSS48 VSS47 VSS46 VSS45 VSS44 VSS43 VSS42 VSS41 VSS40 VSS39 VSS38 VSS37 VSS36 VSS35 VSS34 VSS33 VSS32 VSS31 VSS30 VSS29 VSS28 VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VSS0 U19F Y1 D2 G2 J2 L2 P2 T2 V2 AD2 AE2 AH2 AL2 AN2 A3 C3 AA3 AB3 AC3 AJ3 C4 H4 L4 P4 U4 Y4 AF4 AN4 E5 W5 AL5 AP5 B6 J6 L6 P6 T6 AA6 AC6 AE6 AJ6 G7 V7 AA7 AG7 AK7 AN7 C8 E8 L8 P8 Y8 AL8 A9 H9 K9 T9 V9 AA9 AC9 AE9 AH9 AN9 D10 L10 Y10 AA10 F11 H11 Y11 AA11 AF11 AG11 AJ11 AL11 AN11 B12 D12 J12 A14 B14 F14 J14 K14 AG14 AJ14 AL14 AN14 C15 K15 A16 D16 H16 K16 AL16 C17 G17 AF17 AJ17 AN17 A18 B18 U18 AL18 C19 H19 J19 T19 W19 AG19 AN19 A20 D20 E20 F20 G20 V20 AK20 C21 F21 AF21 AN21 A22 D22 E22 J22 AH22 AL22 H23 AF23 B24 D24 F24 J24 AG24 AJ24 B36 AL24 AN24 A26 E26 G26 J26 B27 E27 G27 W27 AA27 AB27 AF27 AG27 AJ27 AL27 AN27 E28 W28 AA28 AB28 AC28 A29 D29 E29 F29 G29 H29 L29 P29 U29 V29 W29 AA29 AD29 AG29 AJ29 AM29 C30 Y30 AA30 AB30 AC30 AE30 AP30 D31 E31 F31 G31 H31 J31 K31 L31 M31 N31 P31 R31 T31 U31 V31 W31 AD31 AG31 AL31 A32 C32 Y32 AA32 AB32 AC32 AD32 AJ32 AN32 D33 E33 F33 G33 H33 J33 K33 L33 M33 N33 P33 R33 T33 U33 V33 W33 AD33 AF33 AL33 C34 AA34 AB34 AC34 AD34 AH34 AN34 B35 D35 E35 F35 G35 H35 J35 K35 L35 M35 N35 P35 R35 T35 U35 V35 W35 Y35 AE35 C36 AA36 AB36 AC36 AD36 AE36 AF36 AJ36 AL36 AN36 E37 H37 K37 M37 P37 T37 V37 Y37 AG37 A B C C D 1 D E 4 4 VSS 3 3 FOR DDR2 CORE_GMCH_S0 Size A3 Date: Thursday, July 07, 2005 2 NCTF 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Document Number GMCH (5 of 5) Leopard2 Sheet E 10 of Rev 47 -1 1 1 GND /DQS0 /DQS1 /DQS2 /DQS3 /DQS4 /DQS5 /DQS6 /DQS7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 13 31 51 70 131 148 169 188 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 114 119 ODT0 ODT1 1 2 M_CLK_DDR4 DY C231 SC10P50V2JN-1 M_CLK_DDR#4 M_CLK_DDR3 DY C244 SC10P50V2JN-1 M_CLK_DDR#3 8 M_A_DQS#[7..0] 8 M_A_DQS[7..0] 7,12 M_ODT0 7,12 M_ODT1 DDR_VREF_S3 SB High 9.2mm DDR2-200P-4 BC43 SCD1U16V C205 SC2D2U6D3V3MX-1 202 SDA SCL 195 197 VDDSPD 199 SA0 SA1 198 200 NC#50 NC#69 NC#83 NC#120 NC#163/TEST 50 69 83 120 163 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 81 82 87 88 95 96 103 104 111 112 117 118 VREF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 GND GND 201 SMBD_ICH SMBC_ICH 3D3V_S0 BC44 SCD1U16V R175 10KR2 1 11 29 49 68 129 146 167 186 Place near DM1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 M_CLK_DDR1 7 M_CLK_DDR#1 7 M_A_DM[7..0] 8 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 2 GND 201 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 1D8V_S3 164 166 10 26 52 67 130 147 170 185 1 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 DY R230 10KR2 CK1 /CK1 4 M_CLK_DDR0 7 M_CLK_DDR#0 7 2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C547 SC2D2U6D3V3MX-1 CK0 /CK0 C220 SC2D2U6D3V3MX-1 DY R176 10KR2 3 1D8V_S3 Place near DM2 M_CLK_DDR0 1 81 82 87 88 95 96 103 104 111 112 117 118 BC122 SCD1U16V M_CKE0 7,12 M_CKE1 7,12 30 32 DY 2 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 2 10KR2 3D3V_S0 79 80 C511 SC10P50V2JN-1 M_CLK_DDR#0 M_CLK_DDR1 1 50 69 83 120 163 3D3V_S0 1 R229 M_CS#0 7,12 M_CS#1 7,12 CKE0 CKE1 DY 2 NC#50 NC#69 NC#83 NC#120 NC#163/TEST DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 110 115 1 198 200 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 8 M_A_DQ[63..0] SMBD_ICH 3,24 SMBC_ICH 3,24 2 2 202 199 SA0 SA1 BA0 BA1 /CS0 /CS1 2 VREF VSS BC123 SCD1U16V C548 SC2D2U6D3V3MX-1 VDDSPD 107 106 M_A_RAS# 8,12 M_A_WE# 8,12 M_A_CAS# 8,12 1 1 2 DDR_VREF_S3 195 197 8,12 M_A_BS#0 8,12 M_A_BS#1 108 109 113 2 ODT0 ODT1 SDA SCL 8,12 M_A_BS#2 M_CLK_DDR4 7 M_CLK_DDR#4 7 M_B_DM[7..0] 8 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 /RAS /WE /CAS NORMAL TYPE 114 119 7,12 M_ODT2 7,12 M_ODT3 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 10 26 52 67 130 147 170 185 1 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 164 166 2 13 31 51 70 131 148 169 188 CK1 /CK1 M_CLK_DDR3 7 M_CLK_DDR#3 7 2 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 8 M_B_DQS[7..0] CK0 /CK0 30 32 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 1 /DQS0 /DQS1 /DQS2 /DQS3 /DQS4 /DQS5 /DQS6 /DQS7 8 M_B_DQS#[7..0] M_CKE2 7,12 M_CKE3 7,12 2 11 29 49 68 129 146 167 186 2 79 80 1 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 3 CKE0 CKE1 2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 M_CS#2 7,12 M_CS#3 7,12 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 1 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 110 115 2 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 8 M_B_DQ[63..0] /CS0 /CS1 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 1 BA0 BA1 M_B_RAS# 8,12 M_B_WE# 8,12 M_B_CAS# 8,12 2 107 106 108 109 113 E DM1 8,12 M_A_A[13..0] /RAS /WE /CAS 1 8,12 M_B_BS#0 8,12 M_B_BS#1 4 D 2 8,12 M_B_BS#2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 NORMAL TYPE M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 SB C DM2 8,12 M_B_A[13..0] 1 B 1 A C510 SC10P50V2JN-1 M_CLK_DDR#1 2 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DDR2-200P-5 DDR2 Socket Size Document Number Custom Low5.2 mm Hi 9.2 mm Date: Thursday, July 07, 2005 A B C D Rev Leopard2 Sheet E -1 11 of 47 A B C D PARALLEL TERMINATION E Decoupling Capacitor Put decap near power(0.9V) and pull-up resistor Put decap near power(0.9V) and pull-up resistor DDR_VREF DY DY DY DY 2 C498 SCD1U16V DY 1 C494 SCD1U16V C562 SCD1U16V 2 1 1 C497 SCD1U16V 2 C493 SCD1U16V 2 2 C555 SCD1U16V 1 1 1 C503 SCD1U16V 2 C551 SCD1U16V 2 C502 SCD1U16V 2 2 2 1 1 1 1 1 1 2 C501 SCD1U16V DY DY 2 C559 SCD1U16V 1 C560 SCD1U16V C561 SCD1U16V 2 1 1 C504 SCD1U16V 2 C496 SCD1U16V 2 C495 SCD1U16V 1 1 1 C552 SCD1U16V 2 C558 SCD1U16V 2 C557 SCD1U16V 2 C492 SCD1U16V 1 1 1 C556 SCD1U16V 2 C550 SCD1U16V 2 C553 SCD1U16V 2 M_B_BS#2 8,11 1 M_CS#1 7,11 M_CS#3 7,11 1 8 7 6 5 RN26 SRN56-1 1 2 M_B_A13 3 4 M_B_BS#1 8,11 C500 SCD1U16V 2 M_B_A0 M_B_A2 M_B_A7 C554 SCD1U16V 1 1 2 3 4 M_B_A1 C499 SCD1U16V 2 8 7 6 5 1SRN56-1 1 1 56R2J 1 56R2J 2 2 2 2 2 56R2J 56R2J M_A_A12 M_B_A3 R561 R608 R562 R609 M_B_A[13..0] 8,11 1 M_B_A10 M_B_A11 2 1 2 3 4 2 RN28 8 7 6 5 RN30 4 M_A_A[13..0] 8,11 DDR_VREF 1 4 DY M_ODT2 7,11 M_ODT3 7,11 M_CS#2 7,11 1D8V_S3 Place these Caps near DM1 SRN56-1 C203 SC2D2U6D3V3MX-1 1 C200 SC2D2U6D3V3MX-1 2 1 1 C204 SC2D2U6D3V3MX-1 2 C193 SC2D2U6D3V3MX-1 2 1 M_B_RAS# 8,11 M_B_CAS# 8,11 M_B_WE# 8,11 M_B_BS#0 8,11 2 1 2 3 4 2 8 7 6 5 3 1 RN27 C190 SC2D2U6D3V3MX-1 3 SRN56-1 RN31 DY 1D8V_S3 1 C192 SCD1U16V C202 SCD1U16V 2 C191 SCD1U16V 2 DY SRN56-1 1 M_B_A5 M_B_A8 M_B_A9 M_B_A12 RN29 8 7 6 5 C201 SCD1U16V M_CKE3 7,11 SRN56-1 2 1 2 3 4 M_CKE2 7,11 1 M_B_A4 M_B_A6 1 1 2 3 4 2 8 7 6 5 DY DY Place these Caps near DM2 2 C243 SC2D2U6D3V3MX-1 1 C232 SC2D2U6D3V3MX-1 2 1 1 C240 SC2D2U6D3V3MX-1 2 C236 SC2D2U6D3V3MX-1 2 SRN56-1 2 M_A_A8 M_A_A1 M_A_A4 M_A_A2 1 1 2 3 4 2 8 7 6 5 1 RN15 C234 SC2D2U6D3V3MX-1 2 RN13 RN14 8 7 6 5 1 2 3 4 M_A_A0 M_A_A3 1 2 3 4 M_A_A5 M_A_A11 M_A_A7 M_A_A6 1 2 3 4 M_A_A9 DY DY DY 1 1 C235 SCD1U16V C241 SCD1U16V 2 C233 SCD1U16V 2 2 SRN56-1 1 M_A_A13 M_A_A10 M_CS#0 7,11 M_ODT0 7,11 2 1 2 3 4 1 8 7 6 5 C242 SCD1U16V DY M_A_BS#1 8,11 M_A_RAS# 8,11 SRN56-1 RN16 8 7 6 5 SRN56-1 RN17 8 7 6 5 1 M_CKE0 7,11 M_A_BS#2 8,11 M_CKE1 7,11 1 SRN56-1 Wistron Corporation RN12 8 7 6 5 1 2 3 4 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. M_A_WE# 8,11 M_A_BS#0 8,11 M_A_CAS# 8,11 M_ODT1 7,11 Title DDR2 Termination Resistor SRN56-1 Size A3 Document Number Date: Thursday, July 07, 2005 A B C D Rev Leopard2 Sheet E -1 12 of 47 C D E U20A SB 1 OF 6 3D3V_S0 VGA_GPIO14 2 DDC3_CLK 19,25 DDC3_DATA 19,25 2 ATI suggest 0 ohm U62 1 R525 0R2-0 1 R524 0R2-0 22 M24_RST# 7,24,26 PLT_RST1# 1 1 1 3D3V_S0 DY 2 1 A 2 2 B 3 VCC GND Y 2R447 150R2F 2R520 100R2F 2R448 10KR2F-U 5 1 R98 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 10KR2 PERSTB NC7S08-U 1 R502 2 715R3 PEG_CALRP PEG_CALRN PEG_CALI 3D3V_S0 3D3V_S0 PCIE_TEST AE25 PERSTB PERSTB_MASK ATI_R2SET AH21 R2SET AK21 AJ22 AK22 Y_G C_R_PR COMP_B_PB AJ24 AK24 H2SYNC V2SYNC DDC3_CLK DDC3_DATA AG22 AG23 DDC3CLK DDC3DATA ATI_SSIN ATI_SSOUT AJ23 AH24 SSIN SSOUT XTALIN_M24 AH28 XTALIN AJ29 XTALOUT 2 2 R57 0R2-0 R70 1 1 R501 2 210KR2 10KR2 2 R446 4K7R2 2 2 2 1 1 1 0703 -1 R445 4K7R2 G 1 1 VGA_DDCDATA 2 Q37 3 2N7002 DDC_DATA G 1 D S 1 1 1 DDC_DATA 20 Q38 2 VGA_DDCCLK 2N7002 3 DDC_CLK 1KR2 2R99 2R537 1KR2 2R138 1KR2 TESTEN TEST_YCLK TEST_MCLK AH27 E8 B6 AF25 TESTEN TEST_YCLK TEST_MCLK PLLTEST STERE0SYNC AH25 STEREOSYNC DDC_CLK 20 D S M26-P-1 A B VREFG 2 1 00 CAL_OFF GPIO4 0 BYPASS_PLL GPIO5 0 ICOMP GPIO6 0 DEBUG_ACCESS GPIO8 0 2 0R2-0 ROMIDCFG(3:0) GPIO(9,13:11) 0000 MULTIFUNC(1:0) LCDDATA(17:16) 00 VIP_DEVICE LCDDATA(20) DWNGR0 LCDDATA(21) 0 (internal pull-down) 3D3V_S0 2R78 2R77 2R75 2R76 0R2-0 0R2-0 0R2-0 0R2-0 VGA_GPIO0 1 R82 C 2 10KR2 R508 100R2F 3D3V_S0 ATI_VREFG TXOUT_L0N TXOUT_L0P TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P TXOUT_L3N TXOUT_L3P TXCLK_LN TXCLK_LP TXOUT_U0N TXOUT_U0P TXOUT_U1N TXOUT_U1P TXOUT_U2N TXOUT_U2P TXOUT_U3N TXOUT_U3P TXCLK_UN TXCLK_UP AH15 AH16 AJ16 AJ17 AJ18 AK18 AJ20 AJ21 AK19 AJ19 AG16 AG17 AF16 AF17 AE18 AE19 AF19 AF20 AG19 AG20 TXAOUT0TXAOUT0+ TXAOUT1TXAOUT1+ TXAOUT2TXAOUT2+ DIGON BLON AE12 AG12 LCDVDD_ON BL_ON 36 TX0M TX0P TX1M TX1P TX2M TX2P TXCM TXCP AK13 AJ13 AJ14 AJ15 AK15 AK16 AJ12 AK12 DDC2CLK DDC2DATA AE13 AE14 19 19 19 19 19 19 C381 R509 DUMMY-R2 R507 100R2F SCD1U16V HPD1 AF12 R G B AK27 AJ27 AJ26 HSYNC VSYNC AJ25 AK25 VGA_GPIO2 1 DY R85 1 DY R516 1 DY R83 1 DY R100 1 DY R107 1 DY R510 1 DY R106 1 DY R87 1 DY R101 1 DY R517 1 DY R86 1 DY R511 1 DY R84 VGA_GPIO4 VGA_GPIO1 TXACLK- 19 TXACLK+ 19 TXBOUT0- 19 TXBOUT0+ 19 TXBOUT1- 19 TXBOUT1+ 19 TXBOUT2- 19 TXBOUT2+ 19 VGA_GPIO11 VGA_GPIO13 VGA_GPIO12 VGA_GPIO10 VGA_GPIO6 TXBCLK- 19 TXBCLK+ 19 VGA_GPIO9 VGA_GPIO5 19 VGA_GPIO7 R513 10KR2 VGA_GPIO8 VGA_GPIO3 R478 150R2 3 3D3V_S0 3D3V_S0 1 1 1 1 0 ATI Ref. Datasheets(page 3-32) DOC.NO.:CHS-216M24-03 GPIO[0..13] are internal pull-down. 20R2-0 EDID_DAT 20R2-0 EDID_CLK DY AJ10 DVPCNTL_0 AK10 DVPCNTL_1 AJ11 DVPCNTL_2 AH11 DVPCNTL_3 AG4 0 GPIO(3:2) 1 PCIE_CALRP PCIE_CALRN PCIE_CALI AD25 AD24 1 1 1 3D3V_S0 AC23 AB24 AB23 PEG_TESTIN DDC_CLK & DATA level shift R73 R74 150R2 150R2 PCIE_REFCLKP PCIE_REFCLKN PERSTB PWRGD_MASK 18 LUMA_VGA 18 CRMA_VGA 18 COMP_VGA R71 150R2 AF27 AE27 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCNTL_3 GPIO1 PCIE_MODE(1:0) 2 2 2 PLL_CAL_FORCE_EN VGA_PWRCNTL 45 1 2 2 3 CLK_PCIE_PEG 3 CLK_PCIE_PEG# 1D2V_VDDR_S0 2 2 2 ATI_MODE_0 15 SB DY DEFAULT 4 2 R480 0R2-0 R506 4K7R2 2 R505 4K7R2 1 R503 DUMMY-R2 1 PWRGD_MASK 2 1 STERE0SYNC 3D3V_S0 1 2 2 R504 10KR2 2 0 1 R481 DUMMY-R2 2 GPIO0 2 1 1 3D3V_S0 2 CAL_BG_BACKUP DVPDATA_0 15 DVPDATA_1 15 DVPDATA_2 15 R4351 R4341 NO USE DVPDATA PIN 1 EDID_CLK 19,25 EDID_DAT 19,25 3D3V_S0 2 DVOMODE=GND STRAPS 2 7 PEG_RXN[15..0] 2 2 DVOMODE=VSS 3.3V MODE DVOMODE=VDDC to 1.8V 1.8V MODE 2 10KR2 2 10KR2 2 10KR2 2 10KR2 2 10KR2 2 10KR2 2 10KR2 2 10KR2 2 10KR2 2 10KR2 2 10KR2 2 10KR2 2 10KR2 2 2 7 PEG_RXP[15..0] 2 2 PCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N PCIE_TX4P PCIE_TX4N PCIE_TX5P PCIE_TX5N PCIE_TX6P PCIE_TX6N PCIE_TX7P PCIE_TX7N PCIE_TX8P PCIE_TX8N PCIE_TX9P PCIE_TX9N PCIE_TX10P PCIE_TX10N PCIE_TX11P PCIE_TX11N PCIE_TX12P PCIE_TX12N PCIE_TX13P PCIE_TX13N PCIE_TX14P PCIE_TX14N PCIE_TX15P PCIE_TX15N ATI_MODE_0 1 R515 2 3 2 AF26 AE26 AC25 AB25 AC27 AB27 AC26 AB26 Y25 W25 Y27 W27 Y26 W26 U25 T25 U27 T27 U26 T26 P25 N25 P27 N27 P26 N26 L25 K25 L27 K27 L26 K26 DVOMODE VGA_ALERT# 25 R477 R479 150R2 150R2 1 7 PEG_TXN[15..0] 2 RXP0 RXN0 RXP1 RXN1 RXP2 RXN2 RXP3 RXN3 RXP4 RXN4 RXP5 RXN5 RXP6 RXN6 RXP7 RXN7 RXP8 RXN8 RXP9 RXN9 RXP10 RXN10 RXP11 RXN11 RXP12 RXN12 RXP13 RXN13 RXP14 RXN14 RXP15 RXN15 AH6 AJ6 AK6 AH7 AK7 AJ7 AH8 AJ8 AH9 AJ9 AK9 AH10 AE6 AG6 AF6 AE7 AF7 AE8 AG8 AF8 AE9 AF9 AG10 AF10 2 7 PEG_TXP[15..0] 2 AE10 2 0R2-0 R653 0R2-0 VGA_GPIO16 1 SCD1U16V PEG_RXP0 C110 1 PEG_RXN0 C109 1 PEG_RXP1 C391 1 PEG_RXN1 C392 1 PEG_RXP2 C111 1 PEG_RXN2 C112 1 PEG_RXP3 C393 1 PEG_RXN3 C390 1 PEG_RXP4 C120 1 PEG_RXN4 C121 1 PEG_RXP5 C412 1 PEG_RXN5 C414 1 PEG_RXP6 C123 1 PEG_RXN6 C122 1 PEG_RXP7 C413 1 PEG_RXN7 C411 1 PEG_RXP8 C137 1 PEG_RXN8 C134 1 PEG_RXP9 C435 1 PEG_RXN9 C436 1 PEG_RXP10C135 1 PEG_RXN10 C133 1 PEG_RXP11C433 1 PEG_RXN11 C434 1 PEG_RXP12C136 1 PEG_RXN12 C146 1 PEG_RXP13C455 1 PEG_RXN13 C456 1 PEG_RXP14C145 1 PEG_RXN14 C147 1 PEG_RXP15C454 1 PEG_RXN15 C457 1 DVOVMODE DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23 DY 1 R654 VGA_GPIO0 VGA_GPIO1 VGA_GPIO2 VGA_GPIO3 VGA_GPIO4 VGA_GPIO5 VGA_GPIO6 VGA_GPIO7 VGA_GPIO8 VGA_GPIO9 VGA_GPIO10 VGA_GPIO11 VGA_GPIO12 VGA_GPIO13 VGA_GPIO14 1 2 adjust SWING at 1.2v DVO / EXT TMDS / GPIO R474 105R3F AF3 AF2 PCI EXPRESS C64 SC270P50V 2 2 SCD1U16V3KX GPIO_PWRCNTL GPIO_MEMSSIN LVDS 1 1 XTALIN_M24 1 2 P2779A_LF 620R3F 1 R56 2 R444 182R3F DAC2 P2779A-08ST BC90 SC6P50V3DN C65 C360 SCD1U16V TMDS 3D3V_SS_S0 P2779A_REF VGA_GPIO16 1 8 7 6 5 1 2 4 VDD REF MODOUT VSS AJ5 AH5 AJ4 AK4 AH4 AF4 AJ3 AK3 AH3 AJ2 AH2 AH1 AG3 AG1 AG2 C6 SS 1 XTAL-27MHZ-3-U1 P2779A_XOUT XIN/CLKIN XOUT PD# LF 2 1 2 3 4 GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_17 DAC1 2 2 1 1 X5 R443 1MR2 2 BC95 SC22P U57 PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N PCIE_RX4P PCIE_RX4N PCIE_RX5P PCIE_RX5N PCIE_RX6P PCIE_RX6N PCIE_RX7P PCIE_RX7N PCIE_RX8P PCIE_RX8N PCIE_RX9P PCIE_RX9N PCIE_RX10P PCIE_RX10N PCIE_RX11P PCIE_RX11N PCIE_RX12P PCIE_RX12N PCIE_RX13P PCIE_RX13N PCIE_RX14P PCIE_RX14N PCIE_RX15P PCIE_RX15N THERM R472 0R5J-1 P2779A_XIN AH30 AG30 AG29 AF29 AE29 AE30 AD30 AD29 AC29 AB29 AB30 AA30 AA29 Y29 W29 W30 V30 V29 U29 T29 T30 R30 R29 P29 N29 N30 M30 M29 L29 K29 K30 J30 CLK 1 PEG_TXP0 PEG_TXN0 PEG_TXP1 PEG_TXN1 PEG_TXP2 PEG_TXN2 PEG_TXP3 PEG_TXN3 PEG_TXP4 PEG_TXN4 PEG_TXP5 PEG_TXN5 PEG_TXP6 PEG_TXN6 PEG_TXP7 PEG_TXN7 PEG_TXP8 PEG_TXN8 PEG_TXP9 PEG_TXN9 PEG_TXP10 PEG_TXN10 PEG_TXP11 PEG_TXN11 PEG_TXP12 PEG_TXN12 PEG_TXP13 PEG_TXN13 PEG_TXP14 PEG_TXN14 PEG_TXP15 PEG_TXN15 1 B 2 A HPD 1 R514 2 100KR2 VGA_RED 20 VGA_GREEN 20 VGA_BLUE 20 VGA_HSYNC VGA_VSYNC 20 ATI_RSET RSET AH26 DDC1DATA DDC1CLK AG25 AF24 VGA_DDCDATA VGA_DDCCLK GPIO_AUXWIN AG24 GPIO_AUXWIN DPLUS DMINUS AF11 AE11 1 R499 2 499R3F 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 R500 2 4K7R2 THERMDP_M24 25 THERMDN_M24 25 Title ATI(1 of 3) Size A3 Document Number Date: Monday, July 11, 2005 D Rev -1 Leopard2 Sheet E 13 of 47 A B C D E VRAM_VDDQ PVDD MPVDD PVSS MPVSS 1 1 SCD01U16V3KX C462 2 1 SCD01U16V3KX C459 2 C446 2 1 SCD01U16V3KX 1 SCD01U16V3KX C465 2 1 SCD01U16V3KX C442 2 1 C441 2 SCD01U16V3KX 1 SCD01U16V3KX C445 2 1 C421 2 2 1 SE220U2VDM-6 1 2 2 SCD01U16V3KX C382 2 1 SCD01U16V3KX C463 2 1 SCD01U16V3KX C443 2 1 1 2 2 1 SC1U10V3ZY 1 2 1 SCD1U16V3KX SCD1U16V3KX 2 1 1 2 SC1U10V3ZY 1 C460 2 SC1U10V3ZY 1 C417 2 SC1U10V3ZY 1 C420 2 SC1U10V3ZY 1 C466 2 T2 < 1mS T3 < 1mS 2D5_VDDR1 T4 < 1mS 1D2_VDDC 1D2V_VDDR_S0 VDD_15 T5 -- R126 1 2 T6 -- PCIE_PVDD_18 GAP-CLOSE-PWR PCIE_VDDR_12 /PCIE_PVDD_12 1D8V_VGA_S0 C439 2 1 L28 SCD01U16V3KX DY 3D3_VDDR4 1 2 MLB-201209-11 T5 time delay between full PCIE_PVDD_18 and 90% of PCIE_VDDR_12 T6 time delay between full PCIE_VDDR_12 and 90% of 1D2_VDDC 2 ADD ASIC DECOUPLING FOR ALL POWER AS REQUIRED PLACED CLOSE TO THE POWER/GND PINS WITH AS MANY AS POSSIBLE PLACED UNDER THE ASIC 1D8V_VGA_S0 U14 ADJ/GND VOUT VIN 3D3V_S0 AJ28 1 2 3 APL1087 A6 M26-P-1 1.8V C69 SC1U10V3ZY R48 110R3 R45 48D7R3F DY C478 SC1U10V3ZY C350 TC19 ST100U6D3VM-U 1 Imax=1A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Vo=1.25/110*(110+48.7)=1.803V Title SC10U10V6ZY-U ATI(2 of 3) 2 2 SC2D2U10V3ZY 1 SC10U10V6ZY-U C444 2 PCIE_PVDD_1D8V T1 < 1mS GAP-CLOSE-PWR SCD01U16V3KX AE24 AE21 PCIE_PVDD 2 3D3_VDDR3 1 1 VSS1DI VSS2DI 3 M26 Power UP Squence 1D2V_VDDR_S0 C416 2 AH22 DY R475 PCIE_VDDR SC1U10V3ZY AVSSN 1.8V SC22U10V6ZY-L1 2 1 C375 SC1U10V3ZY 2 1 C362 SC1U10V3ZY 2 1 C394 SCD01U16V3KX AF22 1.2V 1 1 1 C477 A7 VDD1DI VDD2DI A2VSSQ SC 2 AVDD AH20 AG21 GAP-CLOSE-PWR C619 SC1U10V3ZY 1 AH23 A2VSSN A2VSSN C423 1 APL5308-15AC-TR 1D5V_1_S0 2 A2VDDQ F19 M6 C66 SC10U10V6ZY-U DY 2 2 1 MPVDD_1D8V 2 1 1.8V SC10U10V6ZY-U AF23 VSSRH0 VSSRH1 1 2 VOUT VIN GND 3 R58 3D3V_VDDR4 SC10U10V5ZY-L 1 2 2 C476 SC1U10V3ZY 2 2 C481 1 1 VDDRH SC1U10V3ZY VRAM_VDDQ L37 1 2 MLB-201209-11 SC10U10V6ZY-U 1 A2VDD A2VDD VDD1DI_1D8VAE23 AE22 C395 AK28 SC10U10V6ZY-U 1D8V_VGA_S0 L36 1 2 MLB-201209-11 AF21 AE20 AG13 AG14 AH14 3.3V 1D5V_VGA_S0 SC U83 3D3V_S0 C98 SC47U6D3V0ZY C419 1 2.5V 1.8V 1.8V 1.8V VDDRH0 VDDRH1 TXVSSR TXVSSR TXVSSR TC21 SC22U10V6ZY-L1 2 1 2 1 2 1 PVDD_1D8V N6 AH18 AH12 GAP-CLOSE-PWR 3D3V_S0 1.2V 4 DIODE SUPPLIES POWER TO VDDC RAIL WHILE VDDC REGULATOR STABALIZES DURING POWER ON 3D3V_S0 1 1 2 MLB-201209-11 C86 TXVDDR TXVDDR LPVSS TPVSS 3D3V_S0 D7 SSM5818SL 2 1D8V_VGA_S0 L26 C85 AF13 AF14 1.8VF18 VDDRH AVDD_1D8V 1D8V_VGA_S0 C348 C353 L34 SC1U10V3ZY 1 2 SC10U10V6ZY-U MLB-201209-11 C374 1D8V_VGA_S0 L3 1 2 MLB-201209-11 LPVDD TPVDD DY 1D2V_VGA_S0 2 SC1U10V3ZY SC100P SC1U10V3ZY C398 2 1 1.8V AH19 AH13 AF18 AG15 AG18 AH17 1 APL1085_ADJ C396 SC1U10V3ZY SC10U10V6ZY-U 2 C347 1 1 2 2 1.8V C363 SC1U10V3ZY 1D8V_VGA_S0 L25 1 2 MLB-201209-11 A2VDDQ_1D8V 2 C364 SC10U10V6ZY-U LVDDR_1D8V SC1U10V3ZY A2VDD_2D5V 1 L32 1 2 MLB-201209-11 SC10U10V6ZY-U C354 2 1 C355 2 2D5V_S0 1 2 2 0R5J-1 1 1 R449 LVDDR_25 LVDDR_25 LVDDR_18 LVDDR_18 LVSSR LVSSR LVSSR LVSSR C68 R60 3D3V_VDDR3 SC1U10V3ZY C440 2 1 1D8V_VGA_S0 AE16 AE17 AE15 AF15 AD22 1D5V_S0 0R2-0 SC1U10V3ZY C438 2 1 2.8V AVSSQ 2 SCD1U10V2MX-1 C361 2 1 SC100P SC1U10V3ZY C378 2 1 SC1U10V3ZY C377 2 1 C376 2 1 C365 SC10U10V6ZY-U 2 1 LPVDD_1D8V D9 D13 D19 D25 E4 T4 AB4 R668 C437 1 1D8V_VGA_S0 L33 1 2 MLB-201209-11 SCD1U16V2KX-1 NC#D9 NC#D13 NC#D19 NC#D25 NC#E4 NC#T4 NC#AB4 1 3.3V 2 2 SC10U10V6ZY-U C397 2 C90 T23 U23 V23 W23 1D5V_VGA_S0C67 0R2-0 1 1 LVDDR_2D8V_S0 1 1 2 MLB-201209-11 PCIE_PVDD_18 PCIE_PVDD_18 PCIE_PVDD_18 PCIE_PVDD_18 R669 C415 2 L4 N23 N24 P23 2 SC22U10V6ZY-L1 LVDDR_2D8V PCIE_PVDD_12 PCIE_PVDD_12 PCIE_PVDD_12 DY EC119 2 1 2 G913C-U 3 AG26 AG27 AG28 AJ30 AK29 1 C144 2 1 4 OUT PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 PCIE_VDDR_12 SC D9 1 R418 100KR2F AC10 AC9 AD10 AD9 AG7 1.5V 2 LVDDR_2D8V 5 SET 2 C344 SC1U10V3ZY SHDN# GND IN VDDR4 VDDR4 VDDR4 VDDR4 VDDR4 DY 1D2V_VGA_S0 1 1 1 2 3 1 2D8V_SET U55 AC19 AC21 AC22 AC8 AD19 AD21 AD7 DY 1D5V_1_S0 1 2 2 C349 SC1U10V3ZY VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 VDDR3 DY 3D3V_S0 SSM5818SL 2 R417 124KR2F 2 C343 SC22P 3D3V_S0 1 1 1 LVDDR_2D8V AC11 AC20 H11 H20 M23 P8 Y23 Y8 2 DY VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 C418 2 1 C470 SC10U10V6ZY-U 2 2 2 DY C486 SC10U10V6ZY-U C461 SC1U10V3ZY DY 1 1 1 VRAM_VDDQ C422 SC1U10V3ZY 2 DY SC1U10V3ZY C467 2 1 VRAM_VDDQ AC15 AC17 AD13 AD15 1 4 VDDC VDDC VDDC VDDC VDDC SC1U10V3ZY DY VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 1.2V AC13 C399 2 A15 A21 A28 A3 A9 AA1 AA4 AA7 AA8 AD4 B1 B30 D11 D14 D17 D20 D23 D26 D5 D8 E27 F4 G10 G13 G15 G19 G22 G27 G7 H10 H13 H15 H17 H19 H22 J1 J4 J7 J8 K23 K24 L23 L8 M4 N4 N7 N8 R1 R4 T7 T8 V4 V7 V8 I/O POWER 1 U20D 4 OF 6 SCD01U16V3KX 1D2V_VGA_S0 SCD01U16V3KX C464 2 1 SCD01U16V3KX C469 2 1 SCD01U16V3KX C475 2 1 SCD01U16V3KX C468 2 C479 2 1 SCD01U16V3KX 1 SCD01U16V3KX C400 2 C424 2 1 SCD01U16V3KX 1 C458 2 SCD01U16V3KX 1.8V Size A3 Document Number Date: Thursday, July 07, 2005 A B C D Rev -1 Leopard2 Sheet E 14 of 47 B C E18 CASA# 16 WEA# E19 WEA# 16 CSA_0# E20 CSA#0 16 CSA_1# F20 CSA#1 16 CKEA B19 CKEA 16 B7 ATI_MVREFD MVREFS B8 ATI_MVREFS D30 DIMA_0 B13 DIMA_1 2 10KR2 VRAM_VDDQ 1 CLKA1 16 CLKA#1 16 R137 100R2 VRAM_VDDQ R136 100R2 TP5 TP6 C163 SCD1U16V 1 NC_DIMA_0 NC_DIMA_1 CLKA0 16 CLKA#0 16 1 R526 2 MVREFD 2 10R2 2 10R2 2 10R2 2 10R2 CKEB 1 CLKA1 CLKA1# B21 CLKA0_R 1 R128 1 C20 CLKA#0_R R129 C18 CLKA1_R 1 R131 1 A18 CLKA#1_R R132 2 10KR2 2 CLKA0 CLKA0# 1 R130 R2 RASB# 17 CASB# T5 CASB# 17 WEB# T6 WEB# 17 CSB_0# R5 CSB#0 17 CSB_1# R6 CSB#1 17 CKEB R3 CKEB 17 CLKB0 CLKB0# N1 N2 CLKB0_R CLKB#0_R CLKB1 CLKB1# T2 T3 CLKB1_R CLKB#1_R NC_DIMB_0 NC_DIMB_1 E3 AA3 DIMB_0 DIMB_1 TP4 TP25 ROMCS# AF5 ROMCS# TP24 C162 SCD1U16V 2 10R2 2 10R2 2 10R2 2 10R2 CLKB0 17 CLKB#0 17 CLKB1 17 CLKB#1 17 C7 MEMTEST C8 VDDCI VDDCI VDDCI VDDCI W16 M15 R19 T12 M26-P-1 1 2 L35 MLB-201209-11 VDDCI C380 C379 SC1U10V3ZY SC10U10V6ZY-U ATI_MODE_0 13 1 R544 2 DUMMY-R2 1 R539 2 DUMMY-R2 ATI suggest MEMTEST ATI_MODE_1 R538 DUMMY-R2 R135 240R2J MEMORY CHANNEL B 3 R545 10KR2 2 VDDR1 MEMVMODE_0 MEMVMODE_1 2 2 R134 100R2 1 1 MEMORY CHANNEL A 1 R120 1 R121 1 R122 1 R119 ATI_MODE_0 NC_MEMVMODE_1 2 As close to CHIP as possible QSB[7..0] 17 1D8V_VGA_S0 M26-P-1 2 M26-P-1 RASB# 1 R133 100R2 QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 1 CASA# CKEA F6 B3 K6 G1 V5 W1 AC5 AD1 VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC M16 N16 N15 P15 P16 R18 R17 R16 R15 R14 R13 R12 T13 T14 T15 W15 V16 V15 U15 U16 T19 T18 T17 T16 2 RASA# 16 QSB_0 QSB_1 QSB_2 QSB_3 QSB_4 QSB_5 QSB_6 QSB_7 DQMB#[7..0] 17 ARRAY A19 DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 4 U20F6 OF 6 P17 P18 P19 U12 U13 U14 U17 U18 U19 V19 V18 V17 V14 V13 V12 N18 N17 N14 W17 W18 W12 W13 W14 N13 N19 M19 M18 M12 N12 M13 M14 P12 P13 P14 M17 W19 CENTER RASA# QSA[7..0] 16 DQMB_0# DQMB_1# DQMB_2# DQMB_3# DQMB_4# DQMB_5# DQMB_6# DQMB_7# E6 B2 J5 G3 W6 W2 AC6 AD2 1D2V_VGA_S0 1 QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 2 J27 F30 F24 B27 E16 B16 B11 F10 MAB[13..0] 17 N5 M1 M3 L3 L2 M2 M5 P6 N3 K2 K3 J2 P5 P3 P2 MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8 MAB_9 MAB_10 MAB_11 MAB_12 MAB_13 MAB_14 1 QSA_0 QSA_1 QSA_2 QSA_3 QSA_4 QSA_5 QSA_6 QSA_7 DQMA#[7..0] 16 DQB_0 DQB_1 DQB_2 DQB_3 DQB_4 DQB_5 DQB_6 DQB_7 DQB_8 DQB_9 DQB_10 DQB_11 DQB_12 DQB_13 DQB_14 DQB_15 DQB_16 DQB_17 DQB_18 DQB_19 DQB_20 DQB_21 DQB_22 DQB_23 DQB_24 DQB_25 DQB_26 DQB_27 DQB_28 DQB_29 DQB_30 DQB_31 DQB_32 DQB_33 DQB_34 DQB_35 DQB_36 DQB_37 DQB_38 DQB_39 DQB_40 DQB_41 DQB_42 DQB_43 DQB_44 DQB_45 DQB_46 DQB_47 DQB_48 DQB_49 DQB_50 DQB_51 DQB_52 DQB_53 DQB_54 DQB_55 DQB_56 DQB_57 DQB_58 DQB_59 DQB_60 DQB_61 DQB_62 DQB_63 2 DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 D7 F7 E7 G6 G5 F5 E5 C4 B5 C5 A4 B4 C2 D3 D1 D2 G4 H6 H5 J6 K5 K4 L6 L5 G2 F3 H2 E2 F2 J3 F1 H3 U6 U5 U3 V6 W5 W4 Y6 Y5 U2 V2 V1 V3 W3 Y2 Y3 AA2 AA6 AA5 AB6 AB5 AD6 AD5 AE5 AE4 AB2 AB3 AC2 AC3 AD3 AE1 AE2 AE3 1 DQMA_0# DQMA_1# DQMA_2# DQMA_3# DQMA_4# DQMA_5# DQMA_6# DQMA_7# J25 F29 E25 A27 F15 C15 C11 E11 MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63 2 MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8 MAA_9 MAA_10 MAA_11 MAA_12 MAA_13 MAA_14 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 1 3 DQA_0 DQA_1 DQA_2 DQA_3 DQA_4 DQA_5 DQA_6 DQA_7 DQA_8 DQA_9 DQA_10 DQA_11 DQA_12 DQA_13 DQA_14 DQA_15 DQA_16 DQA_17 DQA_18 DQA_19 DQA_20 DQA_21 DQA_22 DQA_23 DQA_24 DQA_25 DQA_26 DQA_27 DQA_28 DQA_29 DQA_30 DQA_31 DQA_32 DQA_33 DQA_34 DQA_35 DQA_36 DQA_37 DQA_38 DQA_39 DQA_40 DQA_41 DQA_42 DQA_43 DQA_44 DQA_45 DQA_46 DQA_47 DQA_48 DQA_49 DQA_50 DQA_51 DQA_52 DQA_53 DQA_54 DQA_55 DQA_56 DQA_57 DQA_58 DQA_59 DQA_60 DQA_61 DQA_62 DQA_63 U20C3 OF 6 17 MDB[63..0] MAA[13..0] 16 E22 B22 B23 B24 C23 C22 F22 F21 C21 A24 C24 A25 E21 B20 C19 2 4 H28 H29 J28 J29 J26 H25 H26 G26 G30 D29 D28 E28 E29 G29 G28 F28 G25 F26 E26 F25 E24 F23 E23 D22 B29 C29 C25 C27 B28 B25 C26 B26 F17 E17 D16 F16 E15 F14 E14 F13 C17 B18 B17 B15 C13 B14 C14 C16 A13 A12 C12 B12 C10 C9 B9 B10 E13 E12 E10 F12 F11 E9 F9 F8 MEMORY INTERFACE A MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63 E 2 U20B 2 OF 6 16 MDA[63..0] D MEMORY INTERFACE B A 1.8V RESERVED 010 RESERVED 011 RESERVED 100 RESERVED 101 RESERVED 110 RESERVED 111 +VDDC_CT 2.8V +VDDC_CT GND 1 R79 2 DUMMY-R2 DVPDATA_0 13 1 R81 2 DUMMY-R2 DVPDATA_1 13 1 R80 2 DUMMY-R2 DVPDATA_2 13 R482 10KR2 +VDDC_CT 1 001 2.5V Samsng : 72.45532.M0U 1 000 SAMSUNG/128M +VDDC_CT R484 R483 10KR2 10KR2 1 2 R7 P4 M7 M8 L4 K1 K7 K8 R8 T1 AD12 AG5 AG9 AG11 F27 G9 G12 G16 G18 G21 G24 H27 H23 H21 H18 H16 H14 H12 H9 H8 H4 J23 J24 A2 A10 A16 A22 A29 C1 C3 C28 C30 D27 D24 D21 D18 D15 D12 D10 D6 D4 HYNIX/128M Hynix : 72.55732.B0U 2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CORE GND 1 SETTING DVPDATA_[2:0] VRAM_VDDQ 1 PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS Vendor/Size 2 K28 L28 M27 M26 M24 M25 M28 P28 N28 R25 R23 R24 R26 R27 R28 T28 T24 U28 V24 V26 V27 V25 V28 Y28 W24 W28 AA26 AA27 AA23 AA24 AA25 AA28 AB28 AC28 AD28 AD26 AD27 AE28 AF28 AH29 5 OF 6 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS U20E U4 U8 W7 W8 Y4 AB8 AB7 AB1 AC4 AC12 AC14 AD16 AC16 AC18 AD18 AK2 AJ1 VRAM Selection GND Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Hynix : HY5DS573222F(P)-28 (8Mx32) Samsung : K4D553235F-VC2A (8Mx32) Title ATI(3 of 3) Size A3 Document Number Date: Thursday, July 07, 2005 A B C D Rev -1 Leopard2 Sheet E 15 of 47 5 4 3 2 1 VRAM_VDDQ MCL/DSF H12 H13 DM1 DQS1 DQMA#6 QSA6 H12 H13 DM1 DQS1 2 2 60D4R2F 1 1 BC32 SCD1U16V HY5DS573222F-28 HY5DS573222F-28 4 of 5 U21D MDA6 MDA2 MDA0 MDA7 MDA1 MDA4 MDA5 MDA3 G3 K3 J3 F3 J2 G2 F2 K2 DQ18 DQ23 DQ20 DQ16 DQ21 DQ19 DQ17 DQ22 H3 H2 DM2 DQS2 4 of 5 U65D MDA37 MDA35 MDA34 MDA39 MDA33 MDA36 MDA38 MDA32 G3 K3 J3 F3 J2 G2 F2 K2 DQ18 DQ23 DQ20 DQ16 DQ21 DQ19 DQ17 DQ22 H3 H2 DM2 DQS2 F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9 M13 VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL MCL/DSF HY5DS573222F-28 N13 1 VREF 2 E5 E7 E8 E10 K6 K7 K8 K9 L5 L10 SC10U10V5ZY-L VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 1 2 DQ8 DQ12 DQ13 DQ10 DQ14 DQ9 DQ15 DQ11 1 SC10U10V5ZY-L DQ8 DQ12 DQ13 DQ10 DQ14 DQ9 DQ15 DQ11 K13 G13 G12 J13 F13 K12 F12 J12 2 1 1 DQMA#2 QSA2 K13 G13 G12 J13 F13 K12 F12 J12 MDA49 MDA53 MDA54 MDA50 MDA52 MDA48 MDA55 MDA51 R146 B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10 C VRAM_VDDQ 1 N13 MDA21 MDA18 MDA17 MDA22 MDA19 MDA23 MDA16 MDA20 R145 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ R549 1KR2F BC105 SCD1U16V 2 VREF 3 of 5 U65C 3 of 5 U21C CKE CLK CLK# BC106 DQMA#0 QSA0 DQMA#4 QSA4 HY5DS573222F-28 HY5DS573222F-28 U21E VRAM_VDDQ MDA26 MDA31 MDA30 MDA24 MDA27 MDA25 MDA29 MDA28 D12 D13 E13 C9 B10 B8 C13 B9 DQ26 DQ25 DQ24 DQ30 DQ28 DQ31 DQ27 DQ29 B12 B13 DM3 DQS3 BC104 SCD1U16V U65E 5 of 5 5 of 5 MDA58 MDA63 MDA61 MDA56 MDA59 MDA57 MDA62 MDA60 D12 D13 E13 C9 B10 B8 C13 B9 DQ26 DQ25 DQ24 DQ30 DQ28 DQ31 DQ27 DQ29 B12 B13 DM3 DQS3 B VDDR_VREF2 1 E5 E7 E8 E10 K6 K7 K8 K9 L5 L10 HY5DS573222F-28 BC42 N12 M11 M12 CKEA 15 CLKA1 15 CLKA#1 BC37 R550 1KR2F 2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DM0 DQS0 HY5DS573222F-28 BC28 BA0 BA1 NC#M10 D Layout trace 20 mil R141 1KR2F BC29 SCD1U16V DQMA#3 QSA3 DQMA#7 QSA7 2 HY5DS573222F-28 NC#C4 NC#C11 NC#H4 NC#H11 NC#L12 NC#L13 NC#M3 NC#N3 M13 VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL C4 C11 H4 H11 L12 L13 M3 N3 F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9 B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10 B3 B2 DQMA#5 QSA5 N4 M5 M10 MAA12 MAA13 C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11 1 60D4R2F 1 BC112 SCD1U16V 2 B VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ DQ3 DQ1 DQ2 DQ0 DQ6 DQ5 DQ4 DQ7 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VRAM_VDDQ 2 2 2 CKE CLK CLK# R553 60D4R2F 1 1 R554 BC107_1 CLOSE TO MEM !! N12 M11 M12 DM0 DQS0 B5 C6 B6 B7 D2 D3 C2 E2 NC#C4 NC#C11 NC#H4 NC#H11 NC#L12 NC#L13 NC#M3 NC#N3 CKEA BA0 BA1 NC#M10 B3 B2 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 NC#L9 2 of 5 U65B MDA45 MDA46 MDA43 MDA44 MDA42 MDA40 MDA47 MDA41 N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 L9 D7 D8 E4 E11 L4 L7 L8 L11 C4 C11 H4 H11 L12 L13 M3 N3 15 15 CLKA0 15 CLKA#0 N4 M5 M10 DQMA#1 QSA1 DQ3 DQ1 DQ2 DQ0 DQ6 DQ5 DQ4 DQ7 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 VDD VDD VDD VDD VDD VDD VDD VDD 1 MAA12 MAA13 C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11 2 C VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VRAM_VDDQ 2 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 NC#L9 D7 D8 E4 E11 L4 L7 L8 L11 SC10U10V5ZY-L MAA0 N5 MAA1 N6 MAA2 M6 MAA3 N7 MAA4 N8 MAA5 M9 MAA6 N9 MAA7 N10 MAA8 N11 MAA9 M8 MAA10 L6 MAA11 M7 L9 VDD VDD VDD VDD VDD VDD VDD VDD 1 RAS# CAS# WE# CS# NC#M4 B5 C6 B6 B7 D2 D3 C2 E2 RAS# CAS# WE# CS# NC#M4 BC108_1 M2 L2 L3 N2 M4 RASA# CASA# WEA# CSA#0 CSA#1 2 15 15 15 15 15 MDA12 MDA11 MDA9 MDA10 MDA13 MDA8 MDA15 MDA14 CLOSE TO MEM !! 2 of 5 U21B 1 of 5 U21A BC120 BC121 SC330P50V2KX SCD01U16V2KX 2 2 2 2 2 2 2 2 BC40 SCD01U16V2KX 1 1 1 1 1 1 1 1 1 1 BC113 BC36 BC34 BC38 BC41 BC33 BC39 BC111 SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX 2 2 1 D M2 L2 L3 N2 M4 2 15 QSA[0..7] RASA# CASA# WEA# CSA#0 CSA#1 SC10U10V5ZY-L BC35 SCD1U16V 60D4R2F 15 DQMA#[0..7] BC103 SCD1U16V 1 1 15 MAA[0..13] 2 BC110 SCD01U16V2KX 2 2 C485 SCD1U16V 1 1 1 C490 SCD1U16V 2 C487 SCD1U16V 2 2 C489 SCD1U16V 1 1 1 C172 SCD1U16V 2 C168 SCD1U16V 2 2 1 1 1 C484 SCD1U16V 2 1 2 C488 SCD1U16V 1 of 5 U65A 15 MDA[0..63] 2 VRAM_VDDQ All dampings in this page must near the VRAM. HY5DS573222F-28 BC31 SCD1U16V A R144 1KR2F Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2 CLOSE TO MEM 2 A HY5DS573222F-28 1 1 VDDR_VREF1 Title ATI VRAM (1/2) Layout trace 20 mil Size A3 Document Number Rev Date: Thursday, July 07, 2005 5 4 3 2 -1 Leopard2 Sheet 1 16 of 47 5 4 3 2 1 VRAM_VDDQ 1 of 5 U61A All dampings in this page must near the VRAM. MCL/DSF VREF DQ8 DQ12 DQ13 DQ10 DQ14 DQ9 DQ15 DQ11 H12 H13 DM1 DQS1 HY5DS573222F-28 DQMB#1 QSB1 G3 K3 J3 F3 J2 G2 F2 K2 H3 H2 U61D MDB43 MDB47 MDB45 MDB42 MDB44 MDB40 MDB41 MDB46 DQ18 DQ23 DQ20 DQ16 DQ21 DQ19 DQ17 DQ22 DQMB#5 QSB5 DM2 DQS2 G3 K3 J3 F3 J2 G2 F2 K2 H3 H2 2 2 R111 BC17 4 of 5 DQ18 DQ23 DQ20 DQ16 DQ21 DQ19 DQ17 DQ22 F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9 M13 VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL MCL/DSF E5 E7 E8 E10 K6 K7 K8 K9 L5 L10 VREF N13 C VRAM_VDDQ R522 1KR2F BC98 SCD1U16V HY5DS573222F-28 DM2 DQS2 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 2 B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10 SC10U10V5ZY-L VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ BC96 2 MDB14 MDB9 MDB11 MDB13 MDB10 MDB15 MDB12 MDB8 3 of 5 HY5DS573222F-28 4 of 5 CKE CLK CLK# BC97 1 DQMB#7 QSB7 K13 G13 G12 J13 F13 K12 F12 J12 R110 60D4R2F 1 1 DM1 DQS1 U61C MDB63 MDB59 MDB58 MDB60 MDB56 MDB62 MDB57 MDB61 N12 M11 M12 1 1 H12 H13 HY5DS573222F-28 3 of 5 BA0 BA1 NC#M10 1 2 DQMB#3 QSB3 DQ8 DQ12 DQ13 DQ10 DQ14 DQ9 DQ15 DQ11 N4 M5 M10 CKEB 2 DM0 DQS0 15 15 CLKB1 15 CLKB#1 CLOSE TO MEM !! B3 B2 MAB12 MAB13 D 2 2 1 1 2 2 DQ3 DQ1 DQ2 DQ0 DQ6 DQ5 DQ4 DQ7 2 of 5 SCD1U16V B VDDR_VREF4 DQMB#2 QSB2 D12 D13 E13 C9 B10 B8 C13 B9 DQ26 DQ25 DQ24 DQ30 DQ28 DQ31 DQ27 DQ29 B12 B13 DM3 DQS3 U61E MDB53 MDB54 MDB52 MDB51 MDB50 MDB49 MDB55 MDB48 DQMB#6 QSB6 5 of 5 CLOSE TO MEM D12 D13 E13 C9 B10 B8 C13 B9 DQ26 DQ25 DQ24 DQ30 DQ28 DQ31 DQ27 DQ29 B12 B13 DM3 DQS3 BC99 SCD1U16V R521 1KR2F 2 MDB20 MDB23 MDB22 MDB16 MDB19 MDB17 MDB21 MDB18 5 of 5 1 HY5DS573222F-28 1 HY5DS573222F-28 U64E 2 E5 E7 E8 E10 K6 K7 K8 K9 L5 L10 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQMB#4 QSB4 B5 C6 B6 B7 D2 D3 C2 E2 C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11 Layout trace 20 mil VRAM_VDDQ N13 HY5DS573222F-28 HY5DS573222F-28 R552 1KR2F BC108 SCD1U16V 2 HY5DS573222F-28 NC#C4 NC#C11 NC#H4 NC#H11 NC#L12 NC#L13 NC#M3 NC#N3 M13 VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL VSS_THERMAL BC102 K13 G13 G12 J13 F13 K12 F12 J12 U64D C4 C11 H4 H11 L12 L13 M3 N3 F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9 B4 B11 D4 D5 D6 D9 D10 D11 E6 E9 F5 F10 G5 G10 H5 H10 J5 J10 K5 K10 DM0 DQS0 U61B MDB32 MDB33 MDB34 MDB35 MDB36 MDB38 MDB37 MDB39 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VRAM_VDDQ C4 C11 H4 H11 L12 L13 M3 N3 60D4R2F 1 2 BC27 SCD1U16V VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B3 B2 2 of 5 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 NC#L9 1 2 2 R140 60D4R2F 1 1 R139 BC139_1 CLOSE TO MEM !! 15 CLKB0 15 CLKB#0 BC101 2 CKE CLK CLK# DQ3 DQ1 DQ2 DQ0 DQ6 DQ5 DQ4 DQ7 U64C MDB28 MDB29 MDB31 MDB25 MDB26 MDB27 MDB24 MDB30 SC10U10V5ZY-L N12 M11 M12 CKEB C3 C5 C7 C8 C10 C12 E3 E12 F4 F11 G4 G11 J4 J11 K4 K11 B5 C6 B6 B7 D2 D3 C2 E2 HY5DS573222F-28 VRAM_VDDQ 1 BA0 BA1 NC#M10 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQMB#0 QSB0 2 N4 M5 M10 MAB12 MAB13 D7 D8 E4 E11 L4 L7 L8 L11 SC10U10V5ZY-L A0 A1 A2 A3 A4 A5 A6 A7 A8/AP A9 A10 A11 NC#L9 VDD VDD VDD VDD VDD VDD VDD VDD 1 N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 L9 U64B MDB7 MDB6 MDB5 MDB4 MDB1 MDB0 MDB2 MDB3 2 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 RAS# CAS# WE# CS# NC#M4 15 QSB[0..7] BC140_1 M2 L2 L3 N2 M4 2 2 2 2 2 C RASB# CASB# WEB# CSB#0 CSB#1 15 DQMB#[0..7] BC25 BC107 SC330P50V2KX SCD01U16V2KX BC22 SCD01U16V2KX 1 of 5 U64A B 1 1 1 1 1 1 BC13 BC16 BC14 BC100 BC23 BC12 BC15 BC24 SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX 2 2 1 1 D N5 N6 M6 N7 N8 M9 N9 N10 N11 M8 L6 M7 L9 D7 D8 E4 E11 L4 L7 L8 L11 2 15 MAB[0..13] VDD VDD VDD VDD VDD VDD VDD VDD SC10U10V5ZY-L MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 15 MDB[0..63] RAS# CAS# WE# CS# NC#M4 NC#C4 NC#C11 NC#H4 NC#H11 NC#L12 NC#L13 NC#M3 NC#N3 BC26 SCD01U16V2KX M2 L2 L3 N2 M4 1 1 15 RASB# 15 CASB# 15 WEB# 15 CSB#0 15 CSB#1 BC19 SCD1U16V 60D4R2F 2 C474 SCD1U16V BC21 SCD1U16V 2 2 1 1 C157 SCD1U16V 2 C156 SCD1U16V 2 2 C124 SCD1U16V 1 1 1 C99 SCD1U16V 2 C155 SCD1U16V 2 2 C148 SCD1U16V 1 1 1 C401 SCD1U16V 2 2 1 1 VRAM_VDDQ A BC109 SCD1U16V Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. R551 1KR2F Title 2 2 CLOSE TO MEM A 1 1 VDDR_VREF3 ATI VRAM (2/2) Layout trace 20 mil Size A3 Document Number Date: Thursday, July 07, 2005 5 4 3 2 Rev Leopard2 Sheet 1 -1 17 of 47 A CN5 B C Digital Signal CONN 5V_S0 1 JVGA_HS 20 JVGA_VS 20 1 BC20 SC3P50V2CN SC3P50V2CN BAV99LT1 BAV99LT1 DY DY 31 31 31 31 DY DY RJ45-4 RJ45-5 RJ45-1 RJ45-2 MIC_PR AUD_AGND 33 DK_SPKR_R+ 33 DK_SPKR_L+ 36 VOL_UP_DK# Close to Docking CN CRT_B 20 USB_N_CON6 USB_P_CON6 LINE-OUT IR_OUT TPAD30 TP21 Analog Signal CONN USB_N_CON6 22 USB_PN7 CN6 EXT_MIC_1 32 EXT_MIC_2 32 USB_N_CON0 22 USB_PN1 HP_OUT_R 32 HP_OUT_L 32 R455 1 USB_P_CON6 22 USB_PP7 MIC_PR 36 VOL_DWN_DK# 5V_DOCK 1 MIC-IN DCBATOUT EARPHONE 33 LID_SW 19 R94 1KR2 55 2 1 RJ45-7 31 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 RJ45-8 31 RJ45-3 31 RJ45-6 31 JACK_DETECT# 33 58 57 4 AD+ SPDIF 5V_Dock_S0 1 2 0R2-0 R51 5V_S0 MUTE_LED 19,36 1394_TPA1P_PR 1394_TPA1N_PR 1394_TPB1P_PR 1394_TPB1N_PR 5V_DOCK DOCK_PRESENT AD+ MH2 USB_N_CON1 USB_P_CON1 59 2 USB_PN3 22 FOX-CONN58D-U3 USB_PP3 22 1 AUD_AGND 0R2-0 2 COMP_PR LUMA_PR CRMA_PR CIR_PR USB_P_CON0 22 USB_PP1 3D3V_S0 56 PR_PRESENT# CRT_G 20 MOLEX-CON10-1 MH1 C138 CRT_R 20 JST-CON20 CN12 1 60 CRMA 5V_S0 22 11 1 2 3 4 5 6 7 8 9 10 12 3 R124 R123 C149 150R2F 150R2F SC3P50V2CN SC3P50V2CN BC18 2 DDC_DATA_CON 20 DDC_CLK_CON 20 1 1 5V_S3 VOL_DWN_DK# 1 L12 2 BLM11B750S 1 CRMA_CN5 Docking Connector 2 VOL_UP_DK# 3 LUMA 2 USB_P_CON1 USB_N_CON1 CRMA_CN5 LUMA_CN5 L8 2 BLM11B750S 1 1 LUMA_CN5 2 5V_S3 1 USB_N_CON0 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 D30 2 2 USB_P_CON0 2 4 1 E 5V_S0 D5 21 3 D 31 31 31 31 JACK_DETECT# 1 MUTE_LED 1 AUD_AGND 1 MIC_PR 1 DK_SPKR_R+ 1 DK_SPKR_L+ 1 COMP_PR 1 VOL_UP_DK# 1 VOL_DWN_DK# 1 DOCK_PRESENT 1 PR_PRESENT# 1 BT_LED 1 3D3V_S3 R548 47KR2 63.47334.1D1 BT_LED 2 3 INPUT FUNCTION Place near the GMCH 1 BAV99LT1 ICH_PME# 22,30,34 1 R310 2 DUMMY-R2 PCI_AD24 22,27,30,34 LOW B0 HIGH B1 5V_S0 U16 5V_S3 AD+ 5V_S0 DCBATOUT LUMA 5V_S0 C425 SCD1U16V 1 LUMA_PR_1 2 IND-1D2UH C357 SC47P50V2JN C358 R456 SC47P50V2JN 150R2F R408 10KR2 1 2 1 C351 SC47P50V2JN 2 2 EC131 SCD1U16V 1 1 C62 SC470P25V2KN S VCC A PR_INSERT# 6 5 4 CRMA_VGA 13 2 NC7SB3157P6X-U 1 R72 2 C315 SC470P25V2KN COMP_PR 2 2 2 PR_PRESENT# 2 1 1 R104 2K2R2 SPDIF 2 BLM18PG600SN1 1 B1 GND B0 C369 SC47P50V2JN 1 SPDIF_OUT C356 SC47P50V2JN L27 1 2 IND-1D2UH 1 32 SPDIF_OUT 1 Q31 S2N3904-U3 1 2 L19 CRMA_PR_1 2 IND-1D2UH 2 3 2 47R2 LUMA_VGA 13 1 CRMA_PR 1 PR_INSERT# 36 2 1 R103 PR_INSERT# 6 5 4 NC7SB3157P6X-U 1 2 3 L29 PR_INSERT# DOCK_PRESENT S VCC A U15 CRMA 2 HP suggest B1 GND B0 2 2 C94 SCD1U25V3KX 2 2 1 1 1 C101 C617 SCD1U25V3KXSCD1U16V 2 C471 SCD1U16V 2 2 1 1 1 Please close to ICH6 5V_S0 1 2 3 L30 LUMA_PR 1 1 2 DUMMY-R2 2 BC0EX2 1 R624 1 31 2 19,31 2 LID_SW BC0EX1 3 D31 EARPHONE 31 2 EC14 SCD1U16V 2 EC19 SCD1U16V 2 EC104 SCD1U16V 2 EC106 SC1000P16V2KX 2 EC105 SC1000P16V2KX 2 EC110 SC1000P16V2KX 2 EC109 SC1000P16V2KX 2 EC111 SC1000P16V2KX 2 EC118 SC1000P16V2KX 2 EC30 SC1000P16V2KX 2 EC103 SC1000P16V2KX 2 EC28 SC1000P16V2KX 2 0R2-0 COMP_VGA 13 C352 SC47P50V2JN R491 150R2F R436 150R2F DY AUD_AGND Place near the DOCK 1 5V_S3 5V_DOCK F1 20 100 mil CIR_PR 2 C368 2 C367 SCD1U16V SC4D7U10V5ZY 1 R361 1 R512 CIR 1 FUSE-2A6V 1 1 2 2 1 2 0R2-0 2 0R2-0 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. CIR_KBC 36 Title TC6 ST47U6D3V-U1 Board to board conn/ Docking Size A3 CIR,CIR_PR,CIR_KBC are connect togather. default setting 12/12 DY Document Number Date: Monday, July 11, 2005 A B C D Rev -1 Leopard2 Sheet E 18 of 47 A B C D E INVERTER/LCD 3D3V_LCD_S0 3D3V_S0 SC 3D3V_LCD_S0 SI3865_R1C1 2 BC89 SC4700P50V3KX 1 3D3V_S0 DCBATOUT 2 LCDVDD_ON R1 2 IN R2 DTC114EUA-U1 Q10 ID_DET 1 R353 42 44 3 OUT R1 2 IN 36 NUM_LED LED8 LED7 NUM_LED# 37 R2 DTC114EUA-U1 5V_AUX 5V_AUX_PA Blue LED1 Amber LED2 Q21 2N7002 ID_DET#1 S R351 2N3906-2-U Q23 2 1 47KR2 3 2 D 2 100R2 1 7421_LED# NC 2 1K2R2J-1 LED7 1 5V_S0_PA NC 5V_AUX_PR 2 1K2R2J-1 1 CHG_LED# 1 R358 2 2 200R2J 2 7421_LED# Q28 2 IN 1 PWR_LED# 1 R355 CHG_LED# 1 GND R2 DTC114EUA-U1 36 PWR_LED 2 IN 3 OUT R1 PWR_LED# 37 1 GND R2 DTC114EUA-U1 LED10 IDE_LED# 1 Wistron Corporation LED9 1 CHG_LED# 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2 200R2J Title Inverter/LCD LED8 2 1 Size A3 PWR_LED# LED-B-54-U B 3 OUT R1 Q27 2 5V_S3_PA LED-O-11-U A CAPS_LED# 1 NC NC 2 1K2R2J-1 MUTE_LED# 37 1 GND R2 DTC114EUA-U1 LED-B-54-U LED5 CDROM_LED# 26 LED-B-54-U LED-O-11-U 5V_S3_PR 2 2 5V_AUX_PA LED6 2 2 200R2J NC 1 R359 1 1 R356 3 OUT R1 LED-B-53 1IDE_LED# 2 2 200R2J LED-O-11-U 1 R357 2 IN LED-B-53 LED3 1 R192 NC 2 LED-O-10 5V_S0_PR 1 R360 18,36 MUTE_LED LED1 1 5V_S0_PA R127 LED4 2 1 1K2R2J-1 Q32 36 CHG_LED LED-O-10 1 R180 2 3 3 HDD_LED# 26 IDE_LED# 5V_S0_PA 5V_S0_PR 2N3906-2-U Q22 2 1 47KR2 5V_AUX_PR LED2 CAPS_LED# 1 R346 2 5V_S0_PR 2 ID_DET# ID_DET 36,37 ID_DET change R from 100 to 200 ohm 2 1 1K2R2J-1 2N3906-2-U Q24 2 1 47KR2 2N3906-2-U Q20 1 R344 47KR2 LED2 Blue 1 R352 2 R350 10KR2 R345 100KR2 5V_S0_PR 1 7421 1 G 1 R125 2N3906-2-U Q26 2 1 47KR2 5V_S3_PR LED1 LED9 ID_DET 1 R354 1 GND 5V_AUX Amber U64 5V_S0_PA 2N3906-2-U Q25 2 1 47KR2 2 Blue BT_LED 18,31 2 LED6 Blue 1 5V_S3_PA R2 DTC114EUA-U1 1 LED5 Blue 802_ACT_LED 34 5V_S0 CAPS_LED# 1 GND MH2 3 LED4 PA Top U42 R2 DTC114EUA-U1 5V_S3 3 OUT R1 46 2 Amber Amber Amber 2 3 7421_LED# 1 GND 2 IN 36 CAPS_LED 2 PR Botton 802_BT_LED 2 IN R2 DTC114EUA-U1 IPEX-CON40-1-U1 CAPS IR R1 GND 1 S ID_DET# HDD Q33 OUT 3 37 802_BT_LED# 3 3 OUT R1 2 IN 27 7421_LED 2 CHR LID_SW 18 CH715F Q12 1 PWR LID_SW 2 100KR2 D26 D Q36 2N7002 1 G 1 GND 1 2 3 OUT 2 1 Q35 1 R547 C482 SC1000P50V 36 KBC_LID# R432 150R2 R430 10KR2 Q34 BC91 SCD1U 2 5V_S5 1 1 SCD1U16V 2 2 SCD1U16V 2 SC1000P16V2KX 2 2 C345 BC88 BC87 SC1000P16V2KX C346 1 1 1 5V_S0 R546 4K7R2 3D3V_LCD_S0 3 36 BRIGHTNESS 36 FPBACK 3D3V_S3 2 13,25 EDID_CLK 13,25 EDID_DAT R476 47KR2 SI3865DV-U 2 3 4 3 13 TXBCLK13 TXBCLK+ SI3865_R2 1 2 3 2 13 TXBOUT213 TXBOUT2+ R2 D2 D2 3 13 TXBOUT113 TXBOUT1+ R1/C1 ON/OFF S2 2 13 TXBOUT013 TXBOUT0+ BC93 SCD1U16V SC1U10V3ZY 3 13 TXACLK13 TXACLK+ 45 2 13 TXAOUT213 TXAOUT2+ BC92 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 13 TXAOUT113 TXAOUT1+ MH1 2 13 TXAOUT013 TXAOUT0+ 2 1KR2 1 1 1 R431 13 LCDVDD_ON 6 5 4 1 43 2 270KR2F 1 41 1 LCDVDD_ON_1 R433 2 2 2 4 BC94 SC10U10V6ZY-U 1 CN3 1 1 U58 BC8 SCD1U16V Document Number Date: Monday, July 11, 2005 C D Rev -1 Leopard2 Sheet E 19 of 47 A B C D E 4 4 CRT L9 2 DDC_CLK_CON BLM11B750S 1 2 DDC_DATA_CON L10 BLM11B750S 13 DDC_CLK 1 13 DDC_DATA 18 JVGA_HS JVGA_HS 18 JVGA_VS JVGA_VS 1 R115 1 R114 DDC_CLK_CON DDC_DATA_CON 2 33R2 2 33R2 VGA_HSYNC 18 18 13 VGA_VSYNC 13 L5 13 VGA_BLUE 1 13 VGA_GREEN 1 13 VGA_RED 1 L6 CRT_B 2 BLM11B750S 2 BLM11B750S CRT_B 18 CRT_G CRT_G 18 L7 3 CRT_R 1 CRT_R 18 C113 SC3P50V2CN 2 2 C125 SC3P50V2CN 2 C126 SC3P50V2CN 1 C89 SC15P50V2JN-1 2 1 C87 2 C88 SC15P50V2JN-1 2 2 2 2 R108 150R2F SC15P50V2JN-1 R112 150R2F 1 1 1 1 R113 150R2F 1 2 BLM11B750S 1 3 Close to CN5 Close to U19 (N/B) 010804 Modified on Astro ID request CIR FOR FF 5V_AUX 2 1 1 2 R363 100R2 2 2 R362 10KR2 U81 GND GND VS OUT 1 2 3 4 CIR 2 C316 SC4D7U10V5ZY CIR 18 1 IR-TSOP6236-U U50 GND GND VS OUT 1 1 2 3 4 IR-TSOP6236-U DY 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 CRT/ CIR Document Number Date: Thursday, July 07, 2005 A B C D Rev -1 Leopard2 Sheet E 20 of 47 A R319 10MR2J 2 LPC_LAD[3..0] LDRQ[0]# LDRQ[1]#/GPI[41] N6 P4 INTRUDER# INTVRMEN LFRAME#/FWH[4] P3 LPC_LFRAME# 36 A20GATE A20M# AF22 AF23 ICH_A20GATE 36 H_A20M# 4 CPUSLP# AE27 H_CPUSLP#_ICH DPRSLP# DPSLP# AE24 AD27 H_DPRSLP#_R H_DPSLP#_R FERR# AF24 H_FERR_R CPUPWRGD/GPO[49] AG25 H_PWRGD 4 IGNNE# INIT3_3V# INIT# INTR AG26 AE22 AF27 AG24 H_IGNNE# 4 RCIN# AD23 RCIN# 36 NMI SMI# AF25 AG27 H_NMI 4 H_SMI# 4 STPCLK# AE26 H_STPCLK# 4 THRMTRIP# AE23 RTC1 2 S 1 R270 ICH_TP5 F12 LAN_RSTSYNC 2 10KR2 DY 25,36,43 RSMRST# LAN_RSTSYNC E12 E11 C13 LANRXD[0] LANRXD[1] LANRXD[2] C12 C11 E13 LANTXD[0] LANTXD[1] LANTXD[2] AC97_SYNC_ICH C10 B9 ACZ_BIT_CLK ACZ_SYNC AC97_RST#_ICH A10 ACZ_RST# 3 32,35 AC97_BITCLK 32,35 AC97_SYNC 32,35 AC97_RST# 1 R269 1 R271 2 33R2 2 33R2 F11 F10 B10 32 AC97_DIN0 35 AC97_DIN1 32,35 AC97_DOUT 1 R623 AC97_DOUT_ICH 2 33R2 C9 AC19 1 R627 2 0R2-0 AE3 AD3 AG2 AF2 ACZ_SDIN[0] ACZ_SDIN[1] ACZ_SDIN[2] ACZ_SDO SATALED# SATA[2]RXN SATA[2]RXP SATA[2]TXN SATA[2]TXP AC2 AC1 SATA_CLKN SATA_CLKP Place within 500 mils of ICH6 ball 1 2 SATARBIAS# SATARBIAS R272 0R2-0 26 IDE_IORDY 26 IDE_IRQ14 26 IDE_DACK# 26 IDE_IOW# 26 IDE_IOR# AF16 AB16 AB15 AC14 AE16 IORDY IDEIRQ DDACK# DIOW# DIOR# 1 R53 R250 1 R245 1 LPC_LDRQ1# SB 2 DY 0R2-0 1 R252 20R2-0 20R2-0 1 R617 1 R629 2 10KR2 2 10KR2 R256 56R2J H_CPUSLP# 4,6 H_DPRSLP# 4 H_DPSLP# 4 2 56R2J H_FERR# 4 3 H_INIT# 4 H_INTR 4 VCCP_GMCH_S0 R257 75R2 R6V9 H_THERMTRIP_R 1 R258 2 56R2J R6V7 PM_THRMTRIP-I# 4,7 Layout Note: R6V7 needs to placed within 2" of ICH6, R6V9 must be placed within 2" of R6V7 w/o stub. AC16 AB17 AC17 IDE_A0 26 IDE_A1 26 IDE_A2 26 DCS1# DCS3# AD16 AE17 IDE_CS#0 26 IDE_CS#1 26 DD[0] DD[1] DD[2] DD[3] DD[4] DD[5] DD[6] DD[7] DD[8] DD[9] DD[10] DD[11] DD[12] DD[13] DD[14] DD[15] AD14 AF15 AF14 AD12 AE14 AC11 AD11 AB11 AE13 AF13 AB12 AB13 AC13 AE15 AG15 AD13 IDE_D0 IDE_D1 IDE_D2 IDE_D3 IDE_D4 IDE_D5 IDE_D6 IDE_D7 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15 DDREQ AB14 DA[0] DA[1] DA[2] SATA[0]RXN SATA[0]RXP SATA[0]TXN SATA[0]TXP AD7 AC7 AF6 AG6 SATA_RBIAS_PN AG11 AF11 2 LAN_CLK B11 CPU 3 TP42 D Q17 2N7002 1 G RCIN# VCCP_GMCH_S0 AC-97/AZALIA DY 2 The symbol use 2nd source The P/N is the main source Main source:20.D0152.103 2nd source:20.D0012.103 EE_CS EE_SHCLK EE_DOUT EE_DIN SATA IDE R333 10KR2 LAN D12 B12 D11 F13 1 ETY-CON3-S1 LPC_LDRQ1# 3D3V_S0 LPC_LDRQ0# 36 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 IDE_DREQ 26 2 VCCP_GMCH_S0 R246 56R2J VCCP_GMCH_S0 DY H_DPSLP# 1 3D3V_S0 RTCRST# 1 AA3 AA5 2 AA2 INTRUDER# P2 N3 N5 N4 1 RCT_RST# LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LAD[0]/FWH[0] LAD[1]/FWH[1] LAD[2]/FWH[2] LAD[3]/FWH[3] RTCX1 RTCX2 2 1 Y1 Y2 LPC RCT_X1 RCT_X2 GAP-OPEN 36 1 1 4 U42A 2 SC3D9P50V3CN RTC 1 C298 2 2 XTAL-32D768K-4P G70 SC1U10V3ZY 2 2 R633 1MR2 2 2 20KR2 C614 1 1 R632 BAT2 1 2 CH751H-40-U R334 1KR2 2 3 5 4 1 1 X4 RTC circuitry 1 1 E 2 SC4D7P50V3CN C300 SC1U10V3ZY D22 4 D 4 1 C299 3 CH751H-40-U 2 RTC_VCC C RTC_AUX_S5 2 1 3D3V_AUX D21 1 B R251 56R2J ICH6M 2 DY H_DPRSLP# 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ICH6-M (1 of 4) Size A3 Document Number Date: Thursday, July 07, 2005 A B C D Rev -1 Leopard2 Sheet E 21 of 47 A B C D E U42C U42B A3 E1 R2 C3 E3 C5 G5 J1 J2 PCI_IRDY# 27,30,34 PCI_PAR 27,30,34 ICH_PCIRST# 24 PCI_DEVSEL# 27,30,34 PCI_PERR# 27,30,34 PLTRST# PCICLK PME# R5 G6 P6 1 TP48 1 R287 TP46 PCI_LOCK# R318 32 ICH_SPKR 10KR2 2 10KR2 27,30,34 27,30,34 27,30,34 27,30,34 7 PM_BMBUSY# PIRQ[E]#/GPI[2] PIRQ[F]#/GPI[3] PIRQ[G]#/GPI[4] PIRQ[H]#/GPI[5] RESERVED RSVD[1] RSVD[2] RSVD[3] RSVD[4] RSVD[5] RSVD[6] RSVD[7] RSVD[8] TP[3] INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH# D9 C7 C6 M3 TP14 TPAD30 INT_PIRQE# 30,34 INT_PIRQF# 27 INT_PIRQG# 27 3D3V_S0 10 9 8 7 6 INT_PIRQD# INT_PIRQG# INT_PIRQF# INT_PIRQE# PCI_REQ#5 INT_PIRQA# INT_PIRQC# INT_PIRQB# 3D3V_S0 10 9 8 7 6 PCB_VER0 PCB_VER1 ICH_GPI7 1 R286 1 R264 1 R628 R332 10KR2 2 1 GPIO[25] GPIO[27] GPIO[28] CLKRUN# GPIO[33] GPIO[34] WAKE# THRM# 25 VRM_PWRGD AF21 VRMPWRGD 3 CLK_ICH14 E10 CLK14 3 CLK48_USB A27 CLK48 PM_SUS_CLK TP50 TPAD30 ICH_SLP_S5# 1 R618 2 100R2 PM_DPRSLPVR_R PM_BATLOW#_R 36 PM_PWRBTN# PLT_RST# R616 100KR2 SUSCLK T4 T5 T6 SLP_S3# SLP_S4# SLP_S5# AA1 25 ICH6_PWROK 41 PM_DPRSLPVR V6 36 RSMRST#_KBC AE20 PWROK DPRSLPVR V2 BATLOW# U1 PWRBTN# V5 LAN_RST# Y3 RSMRST# M25 M24 L27 L26 PERn[4] PERp[4] PETn[4] PETp[4] P24 P23 N27 N26 DMI[0]RXN DMI[0]RXP DMI[0]TXN DMI[0]TXP T25 T24 R27 R26 DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 7 7 7 7 DMI[1]RXN DMI[1]RXP DMI[1]TXN DMI[1]TXP V25 V24 U27 U26 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 7 7 7 7 DMI[2]RXN DMI[2]RXP DMI[2]TXN DMI[2]TXP Y25 Y24 W27 W26 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 7 7 7 7 DMI[3]RXN DMI[3]RXP DMI[3]TXN DMI[3]TXP AB24 AB23 AA27 AA26 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 7 7 7 7 DMI_CLKN DMI_CLKP AD25 AC25 CLK_PCIE_ICH# 3 CLK_PCIE_ICH 3 DMI_ZCOMP F24 F23 OC[4]#/GPI[9] OC[5]#/GPI[10] OC[6]#/GPI[14] OC[7]#/GPI[15] C23 D23 C25 C24 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 C27 B27 B26 C26 USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 OC[0]# OC[1]# OC[2]# OC[3]# USBP[0]N USBP[0]P USBP[1]N USBP[1]P USBP[2]N USBP[2]P USBP[3]N USBP[3]P USBP[4]N USBP[4]P USBP[5]N USBP[5]P USBP[6]N USBP[6]P USBP[7]N USBP[7]P USBRBIAS# USBRBIAS PCIE_TXN0 26 PCIE_TXP0 26 Layout Note: PCIE AC coupling caps need to be within 250 mils of the driver. 1D5V_S0 Place within 500 mils of ICH 3 R615 24D9R2F DMI_IRCOMP_R RP3 USB_OC#0 USB_OC#1 USB_OC#3 USB_OC#2 3D3V_S5 1 2 3 4 5 10 9 8 7 6 3D3V_S5 USB_OC#5 USB_OC#4 USB_OC#7 USB_OC#6 SRP10K C21 USB_PN0 D21 USB_PP0 A20 B20 D19 C19 A18 B18 E17 D17 B16 A16 C15 D15 A14 B14 A22 B22 TP12 TP13 USB_PN1 USB_PP1 USB_PN2 USB_PP2 USB_PN3 USB_PP3 USB_PN4 USB_PP4 USB_PN5 USB_PP5 USB_PN6 USB_PP6 USB_PN7 USB_PP7 USB_RBIAS_PN 18 18 31 31 18 18 35 35 35 35 26 26 18 18 1 R255 2 2 22D6R2F Intel 22.6 ohm 1% Place within 500 mils of ICH 3D3V_S5 R317 100KR2 Ver. SA SB SC -1 -2 PCB_VER0 PCB_VER1 PCB_VER2 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 R637 100KR2 R638 100KR2 D20 ECSMI# 6 1 ECSMI#_KBC 36 ECSCI# 5 2 ECSCI#_KBC 36 ECSWI# 4 3 ECSWI#_KBC 36 To avoide leakage current 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ICH6-M (2 of 4) Size A3 Document Number Date: Monday, July 11, 2005 B C D 1 Wistron Corporation CH731U-U A C250 2 SCD1U16V 2 C251 SCD1U16V 4 DMI_IRCOMP ICH6M 1 2 PCB_VER0 PCB_VER1 PCB_VER2 1 2 GPIO[24] SERIRQ R625 DUMMY-R2 R331 DUMMY-R2 R626 10KR2 2 V3 AB20 PUMA Board Version Setting R329 DUMMY-R2 GPO[21] GPO[23] AC20 TP51 TPAD30 2 10KR2 2 10KR2 2 10KR2 STP_CPU# AD20 AD21 25 PM_THRM# 3D3V_S0 PCI_REQ#1 AD22 27,34,36 PCI_SERIRQ 26,33,36,42,44,45,46 PM_SLP_S3# 26,36,42 PM_SLP_S4# SRN10K 1 2 5K6R2 R639 1 2 8K2R2 R630 1 2 R631DY 10KR2 GPO[19] U5 1 1 1 2 8 7 6 5 STP_PCI# AB21 P5 R3 T3 AF19 AF20 AC18 0706 -1 R330 10KR2 1 1 2 3 4 3D3V_S0 PCI_SERIRQ MCH_SYNC# PCI_REQ#0 PM_THRM# GPI12 3D3V_S0 2 PM_BATLOW#_R PM_SUS_STAT# SRP10K 1 PCIE_WAKE# 36 PM_SUS_STAT# 1 2 3 4 5 3D3V_S0 RN10 PM_RI# SMB_LINK_ALERT# SMLINK0 SMLINK1 INT_PIRQH# PCI_REQ#2 PCI_REQ#3 PM_CLKRUN# SRP10K RP2 ICH6_GPO21 ICH_GPO27 AC21 2 2 1 2 3 4 5 TP40 TPAD30 1 PCI_SERR# PCI_DEVSEL# PCI_PERR# PCI_LOCK# 3D3V_S5 3D3V_S0 SRP10K RP1 GPI[12] GPI[13] 2 3D3V_S0 10 9 8 7 6 SMBALERT#/GPI[11] M2 R6 26 PCIE_WAKE# ICH6 Pullups RP4 GPI[7] GPI[8] GPI12 ECSWI# 13 M24_RST# AD9 AF8 AG8 U3 BMBUSY# AE19 R1 W6 ICH6_GPO19 26 NEWCARD_RST# 31 BT_EN 34 WIRELESS_EN# 27,30,34,36 PM_CLKRUN# AD19 ECSCI# 3,41 PM_STPCPU# ICH6M 1 2 3 4 5 SYS_RESET# TP39 TPAD30 PERn[3] PERp[3] PETn[3] PETp[3] 1 1 1 AC5 AD5 AF4 AG4 AC9 PIRQ[A]# PIRQ[B]# PIRQ[C]# PIRQ[D]# SUS_STAT#/LPCPD# U2 ICH_GPI7 ECSMI# PERn[2] PERp[2] PETn[2] PETp[2] K25 K24 J27 J26 PCIE_TXN0_R PCIE_TXP0_R 2 3 N2 L2 M1 L3 W3 3 PM_STPPCI# PLT_RST# 24 CLK_ICHPCI 3 ICH_PME# 18,30,34 SMBCLK SMBDATA LINKALERT# SMLINK[0] SMLINK[1] MCH_SYNC# SPKR SYS_RESET# DY S1N4148-U2 PCI_SERR# 27,30,34 PCI_STOP# 27,30,34 PCI_TRDY# 27,30,34 Y4 W5 Y5 W4 U6 AG21 F8 PM_SUS_STAT# D15 1 3 26 CPPE# Interrupt I/F INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# SMB_LINK_ALERT# SMLINK0 SMLINK1 MCH_SYNC# 3D3V_S5 SATA[0]GP/GPI[26] SATA[1]GP/GPI[29] SATA[2]GP/GPI[30] SATA[3]GP/GPI[31] 1 FRAME# 3D3V_S0 TP49 PERn[1] PERp[1] PETn[1] PETp[1] RI# AF17 AE18 AF18 AG18 1 IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# SRN100K 24,26 SMB_CLK 24,26 SMB_DATA TP47 SATA0_R0 SATA0_R1 SATA0_R2 SATA0_R3 8 7 6 5 PCIE_RXN0 26 PCIE_RXP0 26 2 PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3 PCI_REQ#3 ICH_GNT3 PCB_VER2 ICH_GPO48 PCI_REQ#5 ICH_GPO17 ICH_GPI0_R ICH_GPO16 1 2 3 4 PCI-EXPRESS J6 H6 G4 G2 PCI_REQ#2 34 34 27 27 30 30 CLOCKS C/BE[0]# C/BE[1]# C/BE[2]# C/BE[3]# PCI_REQ#0 PCI_GNT#0 PCI_REQ#1 PCI_GNT#1 PCI_REQ#2 PCI_GNT#2 PCI_REQ#1 Direct Media Interface RN8 L5 C1 B5 B6 M5 F1 B8 C8 F7 E7 E8 F6 B7 D8 H25 H24 G27 G26 POWER MGT USB PCI_REQ#0 REQ[0]# GNT[0]# REQ[1]# GNT[1]# REQ[2]# GNT[2]# REQ[3]# GNT[3]# REQ[4]#/GPI[40] GNT[4]#/GPO[48] REQ[5]#/GPI[1] GNT[5]#/GPO[17] REQ[6]#/GPI[0] GNT[6]#/GPO[16] PCI 2 J3 27,30,34 PCI_FRAME# AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31] 2 4 E2 E5 C2 F5 F3 E9 F2 D6 E6 D3 A2 D2 D5 H3 B4 J5 K2 K5 D4 L6 G3 H4 H2 H5 B3 M6 B2 K6 K3 A5 L1 K4 T2 GPIO PM_RI# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCIE AC coupling caps need to be within 250 mils of the driver. 3D3V_S0 18,27,30,34 PCI_AD[31..0] Rev -1 Leopard2 Sheet E 22 of 47 A B C D E Intel dummy 1 1 1 2 1 2 1 1 2 1 2 SCD1U10V2MX-1 2 1 1 SCD1U10V2MX-1 2 2 SCD1U10V2MX-1 2 SCD1U10V2MX-1 2 1 1 1 1 12 2 1 VCCUSBPLL VCCSUS3_3 A25 A24 2 1 1 1 CH751H-40-U 2 1 1D5V_ICH_S0 1 1 C587 GAP-CLOSE-PWR SCD1U10V2MX-1 Layout Note: Place near AB18 Place within 100 mils of ICH C258 SCD01U16V3KX R660 0R2-0 DY ICH6_VCCLAN1D5V ICH6_VCCLAN1D5V SC R659 1 Place within 100 mils of ICH C259 SCD1U10V2MX-1 AB3 2 1D5V_S0 0R2-0 RTC_AUX_S5 Place within 100 mils of ICH pin G10 1 VCCP_GMCH_S0 G16 G15 F16 F15 E16 D16 C16 2 1D5V_S5 2 3D3V_S5 AG23 AD26 AB22 C549 SC1U10V3ZY 2 2D5V_S0 1 V5REF_S0 V5REF_S5 G11 G10 C566 SCD1U16V 2 V5REF_S5 1 2 2 C567 SCD1U10V2MX-1 Place both within 100 mils of ICH near D27 V2D5S_PCI_IDE Layout Note: Place near AB3 C609 C615 SCD1U10V2MX-1 SCD1U10V2MX-1 C569 SCD1U10V2MX-1 DY Layout Note: Place near AG23 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2 1 B 2 1 2 1 1 2 1 C565 R611 10R2 Intel 10 ohm Place within 100 mils of ICH pin A17 1 Title C572 C581 C571 C263 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 DY ICH6-M (3 of 4) Size A3 DY Document Number Date: Thursday, July 07, 2005 A 5V_S5 D35 ICH6M C595 SCD1U10V2MX-1 C280 SC1U10V3ZY 2 3D3V_S5 2 F21 C271 SCD1U16V C574 SCD1U10V2MX-1 2 V5REF_SUS 1 2 2 2 2 ICH_VCC1_5 1 AA18 A8 Intel 10 ohm 2 V5REF V5REF 3 1D5V_S0 1 CORE IDE PCI 2 C594 SCD1U10V2MX-1 SCD1U10V2MX-1 Layout Note: 1D5V_ICH_S5 Place near U7 3D3V_S5 Place within 100 mils of ICH pin V7 2 SCD1U10V2MX-1 C591 1 Place within 100 mils of ICH pin A13 3D3V_S5 VCC2_5 VCC2_5 VCCLAN3_3/VCCSUS3_3 VCCLAN3_3/VCCSUS3_3 VCCRTC VCCLAN3_3/VCCSUS3_3 VCCLAN3_3/VCCSUS3_3 VCCLAN1_5/VCCSUS1_5 VCCSUS3_3 VCCLAN1_5/VCCSUS1_5 VCCSUS3_3 VCCSUS3_3 V_CPU_IO VCCSUS3_3 V_CPU_IO VCCSUS3_3 V_CPU_IO VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 CH751H-40-U V5REF_S0 G69 AB18 P7 R285 100R2 D16 2 1 G8 CH751H-40-U 1D5V_S5 C296 C297 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 1D5V_ICH_S5 2 A17 B17 C17 F18 G17 G18 VCC1_5_A 1D5V_ICH_S5 C589 1 3D3V_S0 G20 F20 E24 E23 E22 E21 E20 D27 D26 D25 D24 *Within a given well, 5VREF needs to be up before the corresponding 3.3V rail D19 3D3V_S0 2 C272 SCD1U10V2MX-1 A11 U4 V1 V7 W2 Y7 VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A DY 3D3V_S0 1 A13 F14 G13 G14 ICH6_VCCLAN3D3V 2 1 Place within 100 mils of ICH pin AG10 VCCSATAPLL VCC3_3 2 GAP-CLOSE-PWR C610 SCD1U10V2MX-1 Place within 100 mils of ICH DY pin AE1 2 3D3V_S0 AE1 AG10 VCCSUS1_5 G19 C282 SCD1U10V2MX-1 5V_S0 Layout Note: Distribute in PCI section near pin A2-A6 near D1-H1 1 C586 1 SCD1U10V2MX-1 VCCDMIPLL VCC3_3 U7 R7 C590 DY ALL NO_STUFF Caps do not have layout requirements but if layout allows then place next to ICH6 3D3V_S0 2 1D5V_ICH_S0 G29 AC27 E26 VCCSUS1_5 VCCSUS1_5 C582 DY C267 C264 SCD1U10V2MX-1 SCD1U10V2MX-1 2 2 Place within 100 mils of ICH near E26, E27 1D5V_S0 1 1 3D3V_S0 C254 SCD01U16V3KX SC10U10V5ZY-L P1 M7 L7 L4 J7 H7 H1 E4 B1 A6 C583 DY 1 C253 VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 Place within 100 mils of ICH pin AG13, AG16 2 2 DY AA7 AA8 AA9 AB8 AC8 AD8 AE8 AE9 AF9 AG9 AA10 AG19 AG16 AG13 AD17 AC15 AA17 AA15 AA14 AA12 C593 DY SCD1U10V2MX-1 2 1 1 DY 1 1 GAP-CLOSE-PWR 2 Place within 100 mils of ICH DY 2 SCD1U10V2MX-1 G26 1 C604 C597 C273 SCD1U10V2MX-1 SCD1U10V2MX-1 2 1D5V_GPLL_ICH_S0 2 1D5V_S0 2 2 1 1D5V_S0 Place within 100 mils of ICH near pin AG9 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 4 C592 DY 2 DY VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A F9 U17 U16 U14 U12 U11 T17 T11 P17 P11 M17 M11 L17 L16 L14 L12 L11 AA21 AA20 AA19 1 1 2 DY AA6 AB4 AB5 AB6 AC4 AD4 AE4 AE5 AF5 AG5 VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A 2 DY SCD1U10V2MX-1 2 C281 C596 C598 SCD1U10V2MX-1 SCD1U10V2MX-1 2 Place within 100 mils of ICH near pin AG5 1 1 1D5V_S0 USB 2 3 C268 SC10U10V5ZY-L USB CORE 1 Layout Note: PCI decoupling 3D3V_S0 PCI/IDE REF 2 C295 SC10U10V5ZY-L VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B PCIE 1 Layout Note: IDE decoupling 3D3V_S0 AA22 AA23 AA24 AA25 AB25 AB26 AB27 F25 F26 F27 G22 G23 G24 G25 H21 H22 J21 J22 K21 K22 L21 L22 M21 M22 N21 N22 N23 N24 N25 P21 P25 P26 P27 R21 R22 T21 T22 U21 U22 V21 V22 W21 W22 Y21 Y22 SATA 1 2 2 2 2 SCD1U10V2MX-1 C252 C568 C576 SCD1U10V2MX-1 SCD1U10V2MX-1 TC12 ST220U10V-U 4 DY 1 1 1 1D5V_S0 1 2 C573 C575 C584 C577 C585 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 Layout Note: Place near pin AA19 2 U42E 1 1 Layout Note: Place above caps within 100 mils of ICH near F27, P27, AB27 1 1D5V_S0 C D Rev -1 Leopard2 Sheet E 23 of 47 A B C D E E27 Y6 Y27 Y26 Y23 W7 W25 W24 W23 W1 V4 V27 V26 V23 U25 U24 U23 U15 U13 T7 T27 T26 T23 T16 T15 T14 T13 T12 T1 R4 R25 R24 R23 R17 R16 R15 R14 R13 R12 R11 P22 P16 P15 P14 P13 P12 N7 N17 N16 N15 N14 N13 N12 N11 N1 M4 M27 M26 M23 M16 M15 M14 M13 M12 L25 L24 L23 L15 L13 K7 K27 K26 K23 K1 J4 J25 J24 J23 H27 H26 H23 G9 G7 G21 G12 G1 4 3 5V_S0 U78A 14 PLT_RST# 1 RSTDRV#_R 3 2 1 R644 2 33R2 RSTDRV#_5 26 7 TSAHCT32 PCIRST# 3V to 5V level shift for HDD & CDROM 2 SMBUS(ICH6 ---> SODIMM,CLKGEN) 3D3V_S0 14 3D3V_S0 U44B 4 6 PLT_RST#_R 5 22 PLT_RST# 1 2 7 3D3V_S0 TSLCX08-U RN4 SRN4D7KJ 3D3V_S5 1 R268 2 33R2 PLT_RST1# 7,13,26 ICH6 asserts PLTRST# to reset devices on the platform. VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS U42D VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS F4 F22 F19 F17 E25 E19 E18 E15 E14 D7 D22 D20 D18 D14 D13 D10 D1 C4 C22 C20 C18 C14 B25 B24 B23 B21 B19 B15 B13 AG7 AG3 AG22 AG20 AG17 AG14 AG12 AG1 AF7 AF3 AF26 AF12 AF10 AF1 AE7 AE6 AE25 AE21 AE2 AE12 AE11 AE10 AD6 AD24 AD2 AD18 AD15 AD10 AD1 AC6 AC3 AC26 AC24 AC23 AC22 AC12 AC10 AB9 AB7 AB2 AB19 AB10 AB1 AA4 AA16 AA13 AA11 A9 A7 A4 A26 A23 A21 A19 A15 A12 A1 4 3 2 ICH6M 1 SMB_ICH_CTL SRN10KJ U44C 9 U37 3 5 2 6 1 10 22 ICH_PCIRST# ICH_PCIRST#_R 1 R284 TSLCX08-U 2 33R2 PCIRST1# 27,28,30,34,36 Secondary PCI Bus reset signal. 22,26 SMB_CLK 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. SMBC_ICH 3,11 Title PCIRST# Buffer to enhance the driving strength 2N7002DW ICH6-M (4 of 4) Size A3 22,26 SMB_DATA Document Number Date: Thursday, July 07, 2005 A 1 Wistron Corporation 4 3 4 8 SMBD_ICH 3,11 7 RN5 1 2 14 4 3 3D3V_S0 B C D Rev -1 Leopard2 Sheet E 24 of 47 A B 5V_S0 4 1 GAP-CLOSE-PWR 1 2 1 1 E 5V_G768_S0 G9 4 D Reserve for G768B works at High Speed Close to G768D 5V_G768_S0 C 2 2 2 BC6 SCD1U16V SC1000P50V U12 EC20 BC5 SC10U10V6ZY-U DY VCC_FAN 4 THERMDP1 4 THERMDN 1 RUNPWROK 1 2 3 4 5 6 7 8 THERMDP2 1 2 G768_RST# 4K7R2 R46 R38 10KR2 FANVCC VCC DXP1 DXN DXP2 RESET# GND AGND TH_SHUT VCC SMBCLK NC SMBDATA ALERT# FG CLK 16 15 14 13 12 11 10 9 SMBC_G768D SMBD_G768D PM_THRM# 22 FAN_FB CLK32_G768 36 2 G768D R30:5K SET TO 120°C Must close to MAX6509 1 2 3 3,41 CLK_PWRGD# VCC 5 Y 4 3D3V_AUX VRM_PWRGD VCC 5 HYST 4 5V_S5 C34 SCD1U25V3KX 3 MAX6509HAUK-T-U 2 3 NC A GND SET GND OUT# 1 1 U63 Put these two Caps near the thermal diode. M6509_SET 1 2 3 R30 22KR3F 2 U4 3D3V_S0 NC7S14-U THERMDP1 R529 2 0R0402-PAD R530 2 0R0402-PAD 1 3 S5_ENABLE 1 A 2 B 3 GND VCC 5 DY Y 4 S5PWR_ENABLE 46 NC7S08-U 2 1 BC4 SC2K2P THERMDN 3D3V_S0 14 THERMDP1/DP2/THERMDN ON THE SAME LAYER W/S = 10/5 MIL, 12 MIL AWAY FROM OTHERS CAPS CLOSE TO G768B RUNPWROK U44D THERMDP_M24 12 11 13 7 42,44,45 VCCP_PWRGD ICH6_PWROK 22 2 G781 Close to VGA chip 2 BC7 SC2K2P TSLCX08-U THERMDN_M24 180 ms after VCC_G768 > 4.38v, p2, 7 1 1 2 36,42 BC10 SCD1U16V VRM_PWRGD 22 THERMDP2 THERMDN 2 BAT54-1 PWROK 7 3D3V_AUX U18 1 1 41 VGATE RSMRST# 21,36,43 DY 2 DY SYSTEM SENSOR THERMDP1 D8 R68 10KR2 1 BC1 SC470P50V3JN S2N3904-U3 Put under CPU Socket 2 2 DY THERMDN 1 Q9 1 BC11 SC470P50V3JN DY 2 3 THERMDP2 BC9 SC2K2P 3D3V_S0 1 3D3V_S0 5V_S0 R59 2K2R2 U13 1 2 3 4 1 2 1 2 5V_S0 RN1 13 THERMDP_M24 13 THERMDN_M24 R557 10KR2 FAN1 1 2 4 3 2 BC118 SCD1U16V 2 1 BC117 SC10U10V6ZY-U D33 S1N4148-U2 2 1 1 VCC_FAN C57 SCD1U16V G781 SMBCLK SMBDATA ALERT# GND 8 7 6 5 DDC3_CLK 13,19 DDC3_DATA 13,19 VGA_ALERT# 13 74.00781.0BD SMBD_G768D BC119 SCD1U16V 36 SMBD_KBC 1 1 ETY-CON3-S1 1 SRN10KJ 2 1 4 FAN_FB 3 5 3 2 VCC DXP DXN THERM# Wistron Corporation SMBC_G768D 36 SMBC_KBC The symbol use 2nd source The P/N is the main source Main source:20.D0152.103 2nd source:20.D0012.103 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title G768D Size A3 Document Number Date: Monday, July 11, 2005 A B C D Rev -1 Leopard2 Sheet E 25 of 47 A B C D E HDD Connector HDD1 2 5V_S0 IDE_IORDY 21 IDE_DACK# 21 IDE_IRQ14 21 2 0R0402-PAD IDE_A1 21 IDE_A0 21 IDE_CS#0 21 HDD_LED# R542 10KR2 HDD_LED# 19 IDE_DACK# BAY_ID0 DIAG IDE_A2 IDE_CS#1 TP18 R540 2K7R2J SYN-CONN44D-5 5V_S0 2 D32 SSM24L-U DY 2 1 2 SC10U10V5ZY-L C480 CD_AGND 32 RSTDRV#_5 IDE_D7 IDE_D6 IDE_D5 IDE_D4 IDE_D3 IDE_D2 IDE_D1 IDE_D0 IDE_IOW# IDE_IORDY IDE_IRQ14 IDE_A1 IDE_A0 IDE_CS#0 5V_S0 CDROM_LED# 19 R311 10KR2 5V_S0 CSEL CDROM_CSEL R288 DUMMY-R2 52 SYN-CONN50-4R3GP 1 1 1 2 SCD1U16V C483 2 C292 SCD1U16V 1 2 DY 5V_S0 3 4 CD_AUDL 32 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 1 R532 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 54 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15 IDE_DREQ IDE_IOR# 2 PBIDDACK# 1 1 1 DY R527 4K7R2 1 2 5V_S0 R541 4K7R2 R531 4K7R2 IDE_DREQ 21 IDE_IOW# 21 IDE_IOR# 21 53 2 32 CD_AUDR 1 DIAG 21 IDE_A2 21 IDE_CS#1 51 3D3V_S0 1 R528 470R2 CN16 5V_S0 3D3V_S0 1 1 HDDCSEL1 CDROM RSTDRV#_5 24 IDE_D7 IDE_D6 IDE_D5 IDE_D4 IDE_D3 IDE_D2 IDE_D1 IDE_D0 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 46 48 2 4 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 1 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15 BC69 SC10U10V6ZY-U 3 PIN 49,50 DON'T USE 2 47 45 1 2 2 21 IDE_D[15..0] The symbol use 2nd source The P/N is the main source Main source:20.10150.050 2nd source:20.B0040.050 3D3V_S0 NEWCARD Connector IDE_IRQ14 SKT3 Place them Near to Chip 3D3V_S5 1 2 3 4 1 R320 2 8K2R2 Place them Near to Connector 1D5V_S0 3D3V_NEW_S0 1D5V_NEW_S0 3D3V_NEW_LAN_S5 C261 SCD1U16V 2 C260 SC10U10V5ZY-L 1 1 1 C269 SCD1U16V 2 2 2 2 C270 SC10U10V5ZY-L 2 C257 DY SCD1U16VDY SCD1U16V 2 C256 1 1 1 1 CARD-SKT21-U2 For Newcard socket C265 SCD1U16V 2 2 CN14 3D3V_S5 22 PCIE_TXP0 22 PCIE_TXN0 RN7 2 1 U41 CPPE# CPUSB# 3 4 1.5VOUT 1.5VOUT 3D3V_S0 5 6 3.3VIN 3.3VIN 3D3V_NEW_S0 7 8 3.3VOUT 3.3VOUT TP15 TP-2 3D3V_S5 NEWCARD_OC# PERST# 3D3V_NEW_LAN_S5 23 21 9 20 NC#1 NC#10 NC#12 NC#13 NC#24 1 10 12 13 24 GND GND 11 25 OC# 3.3VAUX_IN PERST# AUX_OUT CPUSB# CPPE# 1 R267 Q16 1CONN_CLKREQ# G 2N7002 PERST# SC R488 10KR2 3D3V_NEW_LAN_S5 22 PCIE_WAKE# 1 A 2 B 3 3D3V_S5 DY VCC GND 5 CONN_WAKE# 1D5V_NEW_S0 22,24 SMB_DATA 22,24 SMB_CLK TP38 TP35 PREQ2# 3 U43 22 NEWCARD_RST# PLT_RST1# 7,13,24 D TPS2231 CONN_CLKREQ# 3D3V_NEW_S0 2 0R2-0 S PLT_RST1# 3 CLK_PCIE_NEW 3 CLK_PCIE_NEW# 22 CPPE# TP45 PM_SLP_S3# 22,33,36,42,44,45,46 PM_SLP_S4# 22,36,42 3D3V_S0 TPS2231_RST# 1 17 16 14 15 4 3 2 22 2 1D5V_NEW_S0 CPUTSB# CPPE# STBY# SHDN# SYSRST# RCLKEN 3 1.5VIN 1.5VIN 2 1 19 18 PCIE_RXP0_R PCIE_RXN0_R 22 PCIE_RXP0 22 PCIE_RXN0 SRN100KJ 1D5V_S0 22 USB_PP6 22 USB_PN6 SMB_DATA_C SMB_CLK_C CONN_TP2 CONN_TP3 CPUSB# 26 25 24 MH2 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 MH1 3 2 SMBUS(ICH6--NEWCARD,LAN) Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 1 HDD / CDROM/NEWCARD JAE-CON26-U Y 4 1 Size A3 TPS2231_RST# Document Number NC7SZ08-U Date: Monday, July 11, 2005 A B C D Rev -1 Leopard2 Sheet E 26 of 47 A B U47A VCCP VCCP U1-1 18,22,30,34 PCI_AD[31..0] CLK48_CARDBUS * All 1394 signals must be routed on top side only * Differential pairs of each ports should have equal trace length * Stubs must be keep as short as possible U15 1394_TPBIAS0 31 TPA0P TPA0N V15 W15 1394_TPA0P 31 1394_TPA0N 31 TPB0P TPB0N V14 W14 AGND AGND AGND R322 2 4K7R2 R335 2 4K7R2 X-24D576M-2 1 W17 T19 P12 3D3V_S0 L5 L2 K5 K3 K7 L1 L3 NC#W17 RSVD TEST0 RSVD RSVD RSVD RSVD RSVD RSVD RSVD 1 2 1 2 2 C275 SC10U10V5ZY-L 1 C276 SC1000P50V C274 SC1U10V3KX 2 U13 V13 2 C301 SC15P N12 U14 U16 U17 TPA1P TPA1N V18 W18 TPB1P TPB1N V16 W16 1394_TPBIAS1 3D3V_S0 1394_TPBIAS1 31 1394_TPB1P 1394_TPB1N C283 SCD1U16V 1394_TPB1P 1394_TPB1N R282 10KR2 1394_TPB1P 31 1394_TPB1N 31 MC_PWR_CTRL# SD_CD# MS_CD# SM_CD# MS_CLK/SD_CLK/SM_EL_WP# MS_BS/SD_CMD/SM_WE# E3 F5 F6 G5 F3 U1-5 MS_DATA3/SD_DAT3/SM_D3 MS_DATA2/SD_DAT2/SM_D2 MS_DATA1/SD_DAT1/SM_D1 H5 G3 G2 MS_D3 29 MS_D2 29 MS_D1 29 U1-6 MS_SDIO(DATA0)/SD_DAT0/SM_D0 SD_CLK/SM_RE# SD_CMD/SM_ALE G1 J5 J3 MS_SDIO 29 SM_RE# 29 SM_ALE 29 SD_DAT0/SM_D4 SD_DAT1/SM_D5 SD_DAT2/SM_D6 SD_DAT3/SM_D7 H3 J6 J1 J2 SM_D4 SM_D5 SM_D6 SM_D7 SD_WP/SM_CE SM_CLE SM_R/B# SM_PHYS_WP# H7 J7 K1 K2 SD_WP 29 SM_CLE 29 SM_R/B# 29 U1-9 1 1394_TPA1P 31 1394_TPA1N 31 2 0R2-0 2 SD MS/MS_pro SD_CD# 29 MS_CD# 29 SM_CD# 29 MS_CLK 29 MS_BS 29 3D3V_S0 U45 3D3V_S0 2N7002DW 1 1 R338 MC_PWR_CTRL# TP19 TPAD30 1 MC_PWR_CTRL-1 R281 100KR2 MS/MS_pro D17 XD SD_CD# 1 SM_CD# 2 R280 10KR2 2 SDA SCL 2 M2 M3 2 GAP-CLOSE-PWR F1 F2 U1-10 1 1 1 2 C294 SC12P 1 X2 MC_PWR_CTRL_0 MC_PWR_CTRL_1 U1-8 B_USB_EN# A_USB_EN# 3D3V_PLL_S0 6 R323 150R2 E1 E2 DY G28 2 B_USB_EN 2 210KR2 A_USB_EN 10KR2 1 R336 1 R337 C311 SCD1U16V 3 3D3V_S0 1 1394_XO 1394_XI 3D3V_PLL_S0 3D3V_S0 4 1 3D3V_S0 C310 SCD1U16V DY R12 PC[2:0]=000 TPBIAS1 SUSPEND# DATA CLOCK LATCH SPKROUT C314 SCD1U16V 2 PC0(TEST1) PC1(TEST2) PC2(TEST3) C313 SC1000P50V 1394_TPB0P 31 1394_TPB0N 31 1 R17 1394_PHYTEST M11 1394_CPS 1 P15 1394_CNA R19 R18 3D3V_S0 2 XO XI C289 SCD1U16V DY 1 TPBIAS0 PHY_TEST_MA CPS CNA C288 SCD1U16V 2 2 6K34R3F C287 SCD1U16V 1 1 R289 C312 SC1000P50V DY 2 U18 1394_R0 U19 1394_R1 2 C293 SCD1U16V 1 1 VDPLL_15 2 VDPLL_15 VSSPLL T18 T17 1 V19 VDPLL_33 P14 2 VDPLL_33 VSSPLL R0 R1 PAR FRAME# TRDY# IRDY# STOP# DEVSEL# IDSEL PERR# SERR# REQ# GNT# PCLK PRST# GRST# RI_OUT#/PME# 3D3V_S0 R13 R14 V17 1 AVDD AVDD AVDD U1-7 SD/SDIO 2 4 PCI7421 as possible 3D3V_PLL_S0 UNUSED TERMINALS 2 CS_SUSPEND# R2 10KR2 N1 L6 N2 L7 1 R312 Should be places as close to 3 3D3V_S0 28 CB_DATA 28 CB_CLOCK 28 CB_LATCH 32 PCI_SPKR Bypass/Decupoling Capacitors 7421_LED 19 PM_CLKRUN# 22,30,34,36 2 TPAD30 TP52 INT_PIRQG# CB_MFUNC5 2 22,30,34 PCI_PERR# 22,30,34 PCI_SERR# 22 PCI_REQ#1 22 PCI_GNT#1 3 PCLK_PCM 24,28,30,34,36 PCIRST1# 1 R300 P9 V7 R8 U7 W8 N8 CS_IDSEL W5 2 100R2 V8 U8 U1 T2 P5 R3 T1 7421_PME# T3 3D3V_S0 INT_PIRQF# 22 PCI_SERIRQ 22,34,36 3 22,30,34 PCI_PAR 22,30,34 PCI_FRAME# 22,30,34 PCI_TRDY# 22,30,34 PCI_IRDY# 22,30,34 PCI_STOP# 22,30,34 PCI_DEVSEL# PCI_AD22 INT_PIRQG# 22 2 0R2-0 2 C/BE0# C/BE1# C/BE2# C/BE3# M1 1 R324 5 PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3 CLK_48 PCM_INTB# 1 22,30,34 22,30,34 22,30,34 22,30,34 N3 M5 P1 P2 P3 N5 R1 E 1 W11 W9 W7 W4 3 D CARBUS 1 NONE 1394 CARD READER 2 AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 1394 4 U2 V1 V2 U3 W2 V3 U4 V4 V5 U5 R6 P6 W6 V6 U6 R7 V9 U9 R9 N9 V10 U10 R10 N10 V11 U11 R11 W12 V12 U12 N11 W13 CARD BUS PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 2 W3 W10 1 of 4 1 3D3V_S0 C INTA# INTB# INTC# INTD# MC_PWR_CTRL 29 3 7421_LED BAW56-1 29 29 29 29 SM PCI7411-1 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title TI SNC1Q21 (1 of 2) Size A3 Document Number Date: Monday, July 11, 2005 A B C D Rev -1 Leopard2 Sheet E 27 of 47 B G10 CBB_A13 29 C8 A8 B8 A9 C9 E10 CBB_A23 CBB_A22 CBB_A15 CBB_A20 CBB_A21 CBB_A19 A_CPERR#/A_A14 A_CSERR#/A_WAIT# F10 B3 CBB_A14 29 CBB_WAIT# 29 A_CREQ#/A_INPACK# A_CGNT#/A_WE# E7 B9 CBB_INPACK# 29 CBB_WE# 29 A_CSTSCHG/A_BVD1(STSCHG#/RI#) A_CCLKRUN#/A_WP(IOIS16#) A_CCLK/A_A16 B2 C3 E9 CBB_BVD1# 29 CBB_WP 29 CBB_A16 29 A_CINT#/A_READY(IREQ#) A_CRST#/A_RESET C4 A6 CBB_RDY 29 CBB_RESET 29 A_CAUDIO/A_BVD2(SPKR#) A2 CBB_BVD2# 29 A_CCD1#/A_CD1# A_CCD2#/A_CD2# A_CVS1/A_VS1# A_CVS2/A_VS2# C15 E5 A3 E8 CBB_CD1# CBB_CD2# CBB_VS1# CBB_VS2# A_RSVD/A_D14 A_RSVD/A_D2 A_RSVD/A_A18 B13 D2 C10 CBB_D14 29 CBB_D2 29 CBB_A18 29 2 29 29 29 29 29 29 29 29 29 29 E18 J15 RSVD RSVD RSVD F14 A18 H18 RSVD RSVD RSVD B19 F17 C17 RSVD RSVD RSVD RSVD N13 B17 C18 F19 RSVD RSVD RSVD N17 A15 K15 1 2 2 C607 SC150P50V2JN VCC_ASKT_S0 U77 27 CB_DATA 27 CB_CLOCK 27 CB_LATCH 24,27,30,34,36 PCIRST1# 1 2 10KR2 R635 5V_S0 3D3V_S0 PS_SHDN# 3 4 5 12 21 13 C608 SCD1U16V 5V_S0 C603 SC4D7U10V5ZY 1 DY RSVD RSVD 1 1 RSVD RSVD J18 B18 C602 SC4D7U10V5ZY 2 G19 H17 J13 J17 H19 J19 1 RSVD RSVD RSVD RSVD RSVD RSVD 2 K13 C605 SCD1U16V PCIRST1# DATA CLOCK LATCH RESET# SHDN# 3.3V 1 2 5V 5V 7 20 12V 12V 11 25 GND GND 1 RSVD R634 100KR2 C613 SCD1U16V C612 C611 SCD1U16V SC1U10V3ZY 2 F15 G18 K14 M18 VCC_ASKT_S0 AVCC AVCC 9 10 AVPP 8 OC# 15 NC NC NC NC NC NC NC NC NC 24 23 22 19 18 17 16 14 6 VPP_ASKT_S0 3 TSP2220A 3D3V_S0 U47D 4 PCI7411-1 PCI7411-1 H8 H9 H10 H11 H12 J8 M7 J12 M9 M10 M12 K8 K12 N7 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC G7 G8 G13 H13 J9 J10 J11 K9 K10 K11 L8 L9 L10 L11 L12 M8 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND of 4 VR_PORT VR_PORT VR_EN# M19 PT_PORT H1 VR_PORT 2 H2 C302 SCD1U16V 1 A_CPAR/A_A13 A_CFRAME#/A_A23 A_CTRDY#/A_A22 A_CIRDY#/A_A15 A_CSTOP#/A_A20 A_CDEVSEL#/A_A21 A_CBLOCK#/A_A19 RSVD RSVD RSVD RSVD VPP_ASKT_S0 2 CBB_REG# 29 CBB_A12 29 CBB_A8 29 CBB_CE1# 29 B15 A16 B16 A17 C16 D17 C19 D18 E17 E19 G15 F18 H14 H15 G17 K17 L13 K18 L15 L17 L18 L19 M17 M14 M15 N19 N18 N15 M13 P18 P17 P19 1 C5 F9 B10 G12 U1-3 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 4 2 A_CC/BE3#/A_REG# A_CC/BE2#/A_A12 A_CC/BE1#/A_A8 A_CC/BE0#/A_CE1# CBB_D10 29 CBB_D9 29 CBB_D1 29 CBB_D8 29 CBB_D0 29 CBB_A0 29 CBB_A1 29 CBB_A2 29 CBB_A3 29 CBB_A4 29 CBB_A5 29 CBB_A6 29 CBB_A25 29 CBB_A7 29 CBB_A24 29 CBB_A17 29 CBB_IOWR# 29 CBB_A9 29 CBB_IORD# 29 CBB_A11 29 CBB_OE# 29 CBB_CE2# 29 CBB_A10 29 CBB_D15 29 CBB_D7 29 CBB_D13 29 CBB_D6 29 CBB_D12 29 CBB_D5 29 CBB_D11 29 CBB_D4 29 CBB_D3 29 Power switch 2 D1 C1 D3 C2 B1 B4 A4 E6 B5 C6 B6 G9 C7 B7 A7 A10 E11 G11 C11 B11 C12 B12 A12 E12 C13 F12 A13 C14 E13 A14 B14 E14 D19 K19 POWER TERMINALS A_CAD31/A_D10 A_CAD30/A_D9 A_CAD29/A_D1 A_CAD28/A_D8 A_CAD27/A_D0 A_CAD26/A_A0 A_CAD25/A_A1 A_CAD24/A_A2 A_CAD23/A_A3 A_CAD22/A_A4 A_CAD21/A_A5 A_CAD20/A_A6 A_CAD19/A_A25 A_CAD18/A_A7 A_CAD17/A_A24 A_CAD16/A_A17 A_CAD15/A_IOWR# A_CAD14/A_A9 A_CAD13/A_IORD# A_CAD12/A_A11 A_CAD11/A_OE# A_CAD10/A_CE2# A_CAD9/A_A10 A_CAD8/A_D15 A_CAD7/A_D7 A_CAD6/A_D13 A_CAD5/A_D6 A_CAD4/A_D12 A_CAD3/A_D5 A_CAD2/A_D11 A_CAD1/A_D4 A_CAD0/A_D3 RSVD RSVD 1 CARDBUS A 3 A5 A11 of 4 2 U1-2 VCCA VCCA 3 E 1 4 U47C 2 C606 SCD01U16V2KX 2 1 CARDBUS B of 4 D 1 VCC_ASKT_S0 2 U47B C 2 A C309 SCD1U16V U1-4 1 1 PCI7411-1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title TI PCI7411 GHK (2 of 2) Size A3 Document Number Date: Monday, July 11, 2005 A B C D Rev -1 Leopard2 Sheet E 28 of 47 A B C D E Cardbus I/F PCMCIA Socket CBB_D[0..15] 28 CBB_A[0..25] 28 CBUS1 CBB_IORD# 28 CBB_IOWR# 28 CBB_OE# 28 CBB_WE# 28 CBB_REG# 28 CBB_RDY 28 CBB_WP 28 CBB_RESET 28 CBB_WAIT# 28 CBB_INPACK# 28 1 CBB_RESET CBB_A4 CBB_WAIT# CBB_A3 CBB_INPACK# CBB_REG# CBB_A1 Place close to pin 19. CBB_BVD2# C279 DUMMY-C2 CBB_A0 CBB_BVD1# CBB_D0 CBB_D8 CBB_D1 CBB_D9 CBB_D2 CBB_D10 2 2 1 1 1 1 2 2 1 2 MS_SDIO MS_D1 MS_D2 MS_D3 15 14 16 18 MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 MS_D1 MS_D2 MS_D3 33 32 31 21 22 23 24 S.M/XD-D1 S.M/XD-D2 S.M/XD-D3 S.M/XD-D4 S.M/XD-D5 S.M/XD-D6 S.M/XD-D7 DY 25 30 34 S.M-LVD S.M-CD# S.M-D0 3D3V_CR_S0 R558 2K2R2 R560 2K2R2 DY DY 27 27 27 27 SM_D4 SM_D5 SM_D6 SM_D7 SM_D4 SM_D5 SM_D6 SM_D7 MS-BS MS-INS MS-SCLK 13 17 19 MS_BS_1 MS_CD# MS_CLK_R1 R604 RSV#4 XD-CD 4 39 SM_CD# SD-CD-COM SD-CD-SW SD-WP-SW SD-CLK SD-CMD 41 42 5 8 10 S.M#/XD-CLE S.M#/XD-ALE S.M#/XD-WE S.M#/XD-CE S.M#/XD-RE S.M#/XD-R/B S.M/XD-WP-IN 38 37 36 28 27 26 35 GND GND GND GND 46 45 44 1 27 SM_ALE 3D3V_CR_S0 SM_CD# SM_CD# 1 R559 SM_CLE 2 MS_SDIO 0R2-0 MS_CD# 27 2 MS_CLK 33R2 MS_CLK 27 3 SD_CD# SD_CD# 27 SD_WP SD_WP 27 MS_CLK MS_BS 1 2 33R2 R599 SM_CLE SM_CLE 27 SM_ALE SM_ALE 27 MS_BS_1 1 2 SD_WP R215 22R2 SM_RE# SM_RE# 27 SM_R/B# SM_R/B# 27 MS_CLK_R0 1 R588 MS_BS 27 MS_CLK_R 2 330R2 3D3V_CR_S0 SKT-MEMO-9-U1 R579 2K2R2 R578 4K7R2 2 3D3V_S0 3D3V_CR_S0 U34 SM_R/B# SD_WP 1 2 3 R228 4K7R2 70 C230 SCD1U16V OUT GND SET IN 5 ON# 4 AAT46101GV-1 R239 15KR2 MC_PWR_CTRL 27 C239 SC1U10V3ZY 2 2 Clock AC termination 33MHz clock for 32-bit Cardbus card I/F CBB_WP CBB_CD2# 3D3V_CR_S0 MS_BS SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 2 1 2 CBB_A2 SM_RE# C290 SCD01U16V3KX SM_CD# MS_CLK_R0 1 CBB_A5 R283 DUMMY-R2 CBB_RESET MS_SDIO MS_D1 MS_D2 MS_D3 2 3 43 1 CBB_A16 27 27 27 27 7 6 12 11 1 CBB_VS2# 47K 2 33R2 2 33R2 2 33R2 2 33R2 1 C600 SCD1U16V R216 2K2R2 1 R214 1 R217 1 R213 1 R193 2 2 1 CBB_A16 CBB_A22 CBB_A15 CBB_A23 CBB_A12 CBB_A24 CBB_A7 CBB_A25 CBB_A6 R577 2K2R2 R301 DUMMY-R2 MS_SDIO MS_D1 MS_D2 MS_D3 1 CBB_A21 VPP_ASKT_S0 VCC_ASKT_S0 SM-CD-COM SM-CD-SW SM-WP-SW XD-VCC S.M-VCC MS-VCC SD-VCC 2 CBB_RDY 40 29 20 9 1 CBB_A20 C509 C537 C517 C531 SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SCD01U16V2KX SKT2 2 CBB_WE# 3 3D3V_CR_S0 2 2 C601 C599 SC1000P50VSCD1U16V CBB_A8 CBB_A17 CBB_A13 CBB_A18 CBB_A14 CBB_A19 3D3V_CR_S0 3D3V_CR_S0 1 1 1 C588 SC22U10V6ZY-U 2 2 1 CBB_IOWR# 2 CBB_IORD# CBB_A9 1 CBB_A11 2 VCC_ASKT_S0 1 CBB_CE2# CBB_OE# CBB_VS1# 2 CBB_A10 1 CBB_CE1# CBB_D15 6 in 1 Connector CBB_CE1# 28 CBB_CE2# 28 CBB_BVD1# 28 CBB_BVD2# 28 CBB_CD1# 28 CBB_CD2# 28 CBB_VS1# 28 CBB_VS2# 28 2 CBB_CD1# CBB_D4 CBB_D11 CBB_D5 CBB_D12 CBB_D6 CBB_D13 CBB_D7 CBB_D14 4 2 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 61 28 62 29 63 30 64 31 65 32 66 33 67 34 68 CBB_D3 1 1 4 2 69 CARDBUS68P-9 62.10024.491 3D3V_S0 SKT1 1 2 3 4 U75 CARDBUS-SKT45-U1 MS_CLK 1 A MS_CLK_R 2 B 3 GND VCC 5 SE 4 1 SD_CD# 1 NC7SZ66P5X Wistron Corporation DY 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title PCMCIA SLOT/ CARDBUS SKT Size A3 Document Number Date: Thursday, July 07, 2005 A B C D Rev -1 Leopard2 Sheet E 29 of 47 A B C D E 3D3V_LAN_S5 EECS_3 EESK EEDI EEDO R166 LAN_X2 2 DUMMY-R2 1 PCI_AD[0..31] 8 7 6 5 AVDD25 22,27,34 VDD25 18,22,27,34 C225 SCD1U16V 1 R152 2 0R3-U C176 SCD1U16V M93C46-W-3 2 1 PCI_C/BE#[0..3] 1 LAN_X1 1 2 3K6R3 R174 U27 1 CS VCC 2 SK DC 3 DI ORG 4 DO GND 2 Close to RTL8100C Pin121,Pin122 X6 1 4 2 4 1 1 XTAL-25MHZ-43 2 2 C186 SC12P50V2JN C185 SC12P50V2JN 2 R157 3D3V_LAN_S5 1 5K6R3F 3D3V_LAN_S5 1 C174 2 2 SCD1U16V C198 SCD1U16V 1 1 2 SCD1U16V 1 2 C216 SCD1U16V 1 C184 2 C215 SCD1U16V 1 2 2 2 2 C213 SCD1U16V 1 1 1 2 2 PCI_AD1 PCI_AD0 VDD25 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 1 C214 2 SCD1U16V C217 SCD1U16V 2 C188 2 2 SCD1U16V C173 C167 SC22U10V6ZY-U 1 1 1 1 VDD25 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 SCD1U16V 2 GAP-CLOSE-PWR 2 PCI_AD7 PCI_C/BE#0 3D3V_LAN_S5 1 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 L14 BLM11A601S AVDD33 PCI_PERR# PCI_STOP# PCI_DEVSEL# PCI_TRDY# 3D3V_S5 C175 SCD1U16V 1 C177 DY 2 C170 2 C178 PCI_PAR 22,27,34 PCI_SERR# 22,27,34 PCI_PERR# 22,27,34 PCI_STOP# 22,27,34 PCI_DEVSEL# 22,27,34 PCI_TRDY# 22,27,34 1 1 PCI_AD15 VDD25 PCI_C/BE#1 PCI_PAR PCI_SERR# 2 PCI_AD13 PCI_AD14 2 NC NC NC NC AVDDH VSSPST GND LED0 VDD18 LED1 LED2 LED3 GND EESK VDD18 EEDI EEDO VDD33 EECS LANWAKE PCIAD0 PCIAD1 NC GND NC XTAL1 XTAL2 VSS GND GND VSS 3 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 122 123 124 125 NC CTRL18 AVDD18 NC RTL8100CL-U PCI_AD2 2 3D3V_LAN_S5 PM_CLKRUN# 22,27,34,36 G23 1 2 GAP-CLOSE-PWR 1 3D3V_S0 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SCD1U16V 24,27,28,34,36 PCIRST1# 3 PCLK_LAN 22 PCI_GNT#2 22 PCI_REQ#2 18,22,34 ICH_PME# PCIAD2 VSSPST GND VDD25 VDD18 PCIAD3 PCIAD4 PCIAD5 PCIAD6 VDD33 PCIAD7 CBEB0 GND VSSPST PCIAD8 PCIAD9 NC M66EN PCIAD10 PCIAD11 PCIAD12 VDD33 PCIAD13 PCIAD14 GND VSSPST GND PCIAD15 VDD25 VDD18 CBEB1 PAR SERRB SERR# NC NC GND NC VDD33 PERRB PERR# STOPB STOP# DEVSELBDEVSEL# TRDYB TRDY# GND VSSPST CLKRUNBCLKRUN# GND 2 SCD1U16V 3D3V_LAN_S5 3 VDD25 G19 1 1 ISOLATE 22,34 INT_PIRQE# CHP69 Q11 2 LAN_PWR_CTRL 1 0R2-0 2 AVDD33 TX+ MDI0+ TXMDI0AVDD33 AVDDL GND VSS RX+ MDI1+ RXMDI1AVDD33 AVDDL CTRL25 NC VSS AVDDH NC HSDAC+ NC HSDAC- AVDD25 NC VSS NC MDI2+ NC MDI2NC AVDDL GND VSS NC MDI3+ NC MDI3AVDD33 AVDDL VSSPST GND NC GND ISOLATE# ISOLATEB NC VDD18 INTAB INTA# VDD33 PCIRST# PCIRSTB PCICLK GNTB GNT# REQB REQ# PMEB PME# VDD25 VDD18 PCIAD31 PCIAD30 GND PCIAD29 PCIAD28 VSSPST GND CTRL25 1 R151 SCD1U16V AVDD33 CTRL25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 PCIAD27 PCIAD26 VDD33 PCIAD25 PCIAD24 CBEB3 VDD18 NC IDSEL PCIAD23 NC GND PCIAD22 PCIAD21 GND VSSPST GND PCIAD20 VDD18 VDD25 PCIAD19 VDD33 PCIAD18 PCIAD17 PCIAD16 CBEB2 FRAME#FRAMEB NC GND IRDY# IRDYB VDD18 NC RX+ RX- 3D3V_LAN_S5 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 AVDD33 GND TX+ TX- 126 U24 C169 SCD1U16V VSS RSET 2 128 127 1 1 2 C171 SCD1U16V AVDD25 2 EECS_3 31 31 C189 3D3V_LAN_S5 3 31 31 EEDO EEDI R154 49D9R2F EESK R153 49D9R2F LAN_LED2 LAN_LED1 R155 49D9R2F LAN_LED0 R156 49D9R2F RX+ RX- LAN_X1 Close to LAN chip TX- LAN_X2 1 TX+ SCD1U16V 1 TP7 TP8 TP9 2 PCI_C/BE#2 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 VDD25 PCI_AD20 PCI_AD21 PCI_AD22 ISOLATE PCI_AD23 LAN_IDSEL 1 Wistron Corporation 2 1 3D3V_LAN_S5 R149 15KR2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. R165 100R2 2 PCI_IRDY# Title 22,27,34 LAN RTL8100C 1 1 PCI_C/BE#3 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 R150 1KR2 PCI_AD23 PCI_FRAME# 22,27,34 Size A3 Document Number Rev A B C D -1 Leopard2 Date: Thursday, July 07, 2005 Sheet E 30 of 47 A B C Place on bottom side From NEW! 1004-1 Blue thumb R453 1 1 R621 22 USB_PN2 1394 Connector 10 8 7 6 5 4 3 2 USB_N_CON2 USB_P_CON2 USB_P_CON2 22 USB_PP2 E CN4 2100R2 2 100R2 18 BC0EX2 18 BC0EX1 USB_N_CON2 18,19 BT_LED 34 BT_PRIOR 34 WLAN_ACT D 4 1 9 3D3V_BT_S0 1 R142 27 1394_TPA0P 2 0R0402-PAD 27 1394_TPA0N 1 R143 2 0R0402-PAD 27 1394_TPB0P 1 R147 2 0R0402-PAD 27 1394_TPB0N 1 R148 2 0R0402-PAD TPA0+ 1394_1 6 3 TPA0TPB0TPB0+ 4 1 5 1 1 R298 56R2F 1394_TPB0_T 1 1 27 1394_TPBIAS0 R297 56R2F 2 R295 56R2F 2 2 R296 56R2F 2 BC0EX2 connect to PCI_AD22 on main board. BC0EX1 connect to ICH_PME# on main board. 1 SKT-1394-4P-6-U1 1 JST-CON8-7 4 2 2 2 2 1 R67 2 0R0402-PAD 1394_TPB1N_PR 18 27 1394_TPB1N 1 R66 2 0R0402-PAD R294 56R2F 3 R292 56R2F 2 R290 56R2F 1394_TPB1_T 1 RJ45 PIN C284 TPS5130_1D8V_EN# 31 G TD+ --> TX+ RJ45-1 TD- --> TX- RJ45-2 RD+ --> RX+ RJ45-3 RD- --> RX- RJ45-6 C285 SC220P SC1U10V3KX R293 5K1R2 2 2 3 1 1 27 1394_TPB1P 1 1394_TPA1P_PR 18 1394_TPA1N_PR 18 1394_TPB1P_PR 18 1 2 0R0402-PAD R291 56R2F 10/100 LAN Transformer D QB2 2N7002 QB3 2N7002 S S 1 R50 2 BT_EN# D 27 1394_TPA1N 2 1 2 2 R454 11KR3F 2 0R0402-PAD 27 1394_TPBIAS1 2 3 2 R518 10KR2 C100 SCD1U16V 1 R65 2 2 1 5V_S3 SC4D7U10V5ZY 2 G913C-U 22 BT_EN Close to CN20 2 1 3D3V_BT_S0 R299 5K1R2 27 1394_TPA1P 1 4 1 OUT C383 1 G DY 1 SET EC117 SCD1U DY 1 SHDN# GND IN 3D3V_BT_SET 5 EC29 SCD1U DY C286 SC220P SC1U10V3KX 2 2 U60 1 2 3 EC27 SCD1U DY R490 18KR3F 3 BT_EN# 1 C366 SC20P I max = 150 mA 1 1 1 C402 SC1U10V3ZY EC116 SCD1U 2 3D3V_BT_S0 5V_S3 1 3D3V_BT_S0 2 MAX 150mA POWER SWITCH 2 C277 BC0EX2 BC0EX1 BT_LED These components near to chip side. 2 10/100M Lan Transformer U3 XFR_RDC 3 XFR_CMT 11 XFR_RXC 14 XFR_TDC 6 8 7 TDTD+ RXRX+ 15 16 RDRD+ 2 1 TXTX+ 9 10 RJ45-8 RJ45-7 RJ45-6 RJ45-5 RJ45-4 RJ45-3 RJ45-2 RJ45-1 RXRX+ RX- 30 RX+ 30 TXTX+ RJ45-8 RJ45-7 RJ45-6 RJ45-5 RJ45-4 RJ45-3 RJ45-2 RJ45-1 18 18 18 18 18 18 18 18 JK1 9 RJ45_END1 XFORM-187-U RJ45_END2 DY 1 C26 SCD1U16V 1 R401 75R2F XFR_CMT 1 R400 1 R399 2 75R2F 2 75R2F 2 XFR_RXC RJ45_END LAN_TERMINAL RJ45_1 RJ45-2 RJ45-3 RJ45-4 RJ45-5 RJ45-6 RJ45-7 RJ45-8 RJ45_2 RJ45_3 RJ45_4 RJ45_5 RJ45_6 RJ45_7 RJ45_8 TIP RING RJ11_1 RJ11_2 4 1 2 C320 SC1500P2KV8KX 1 RJ45-1 CN1 ETY-CON2-R1 L21 1 2 TIP_MDC RING_MDC 1 1 TIP RING 2 MLB160808 2 L20 MLB160808 1 Wistron Corporation 10 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. RJ45-74-U1 Title 3 1.route on bottom as differential pairs. 2.Tx+/Tx- are pairs. Rx+/Rx- are pairs. 3.No vias, No 90 degree bends. 4.pairs must be equal lengths. 5.6mil trace width,12mil separation. 6.36mil between pairs and any other trace. 7.Must not cross ground moat,except RJ-45 moat. R404 75R2F 2 2 C27 SCD1U16V 1 1 TXTX+ 2 30 30 CT CT CT CT LAN / 1394 Connector 20.D0151.102 Size A3 Document Number Date: Monday, July 11, 2005 A B C D Rev -1 Leopard2 Sheet E 31 of 47 A B C D E 2 BC134 SC1U10V3ZY 2 BC137 SCD1U16V 1 1 1 BC135 SCD1U16V 2 2 1 3D3V_S0 BC133 SCD1U16V 4 4 AUD_AGND 5V_AUDIO_S0 1 DY 2 33R2 2 1 R327 AC97_BITCLK 21,35 AC97_SYNC 21,35 AC97_RST# 21,35 SPDIF_OUT 18 SPDIF_OUT 2 BC71 SC22P DY 3 2XTALOUT_CODEC_R1 DUMMY-R2 BC72 2 DUMMY-C2 5V_S0 BC139 R646 SC22P 28K7R3F R342 4K7R2 AUX_L AUX_R 26 40 44 33 5V_AUDIO_S0 1 AC97_CBITCLK 1 R316 AC97_DIN0 21 AC97_DOUT 21,35 U80 1 SHDN# 2 GND 3 IN SET BC140 SC1U10V3ZY AD1981B-AS 5VA_SET 5 5V_AUDIO_S0 OUT R647 10KR3F 4 2 MAX8863-S BC138 SC10U10V6ZY-U For High limit --> H45 2 AUD_AGND EC160 2 HP_OUT_L HP_OUT_R 6 10 11 48 DY X-24D576MHZ-3-U1 1 SCD1U16V BIT_CLK SYNC RESET# SPDIF 1 DUMMY-C2 1 CD_L CD_R CD_GND_REF AC97_DIN0_CODEC 1 R315 CLK_CODEC 3 2 2 BC68 22R2 X3 2 29 30 31 32 27 28 VREF VREFOUT 1 9 DVDD1 DVDD2 AFILT1 AFILT2 AFILT3 AFILT4 SDATA_IN SDATA_OUT 8 5 2 BC78 SC22P 1 2 0R2-0 1 R309 150KR2J 2 3 2 R304 150KR2J 2 2 R307 150KR2J XTL_IN XTL_OUT 1 R343 XTALOUT_CODEC 1 1 BC60 HPSENSE 33 EAPD 33,36 2 CDAGND DY 1 1 BC59 1 2 22R2 1 1 R306 26 CD_AGND CDAUDR 17 16 47 1 2 22R2 HPSENSE_1 33 2 2K2R2 2 1 R305 CDAUD_L 18 2 SC1U25V5ZYCDAUD_R 20 CDAUD_GND 19 2 SC1U25V5ZY 39 41 2 SC1U25V5ZY AUD_PC_BEEP 14 15 1 BC61 3 S1N4148-U2 1 R636 1 26 CD_AUDR CDAUDL MONO_OUT PHONE_IN 12 42 2 22R2 AD1981_JS0 JS0 JS1 EAPD 46 45 1 R308 AUD_MDC_CODEC 37 AUD_PHONE_CODEC13 4 7 26 CD_AUDL 1 3 2 SCD1U16V 2 SCD1U16V LINE_IN_L LINE_OUT_L LINE_IN_R LINE_OUT_R 1 2 BC75 1 BC67 1 23 35 24 36 D18 U48 NC NC 33 AUD_LOR 35 AUD_MDC_OUT 35 AUD_PHONE MIC1 MIC2 ID1# ID0# 33 AUD_LOL 21 22 DVSS1 DVSS2 BC66 SC1U10V3ZY AVDD1 AVDD2 AVDD3 AVDD4 BC58 SC1U10V3ZY AUD_MICIN1 1 AUD_MICIN2 1 AVSS1 AVSS2 AVSS3 AVSS4 EXT_MIC_1 2 EXT_MIC_2 2 R302 10KR2 AUD_AGND 25 38 43 34 AUD_AGND 3D3V_S0 2 2 C307 SC270P50V3JN 1 2 C305 SC270P50V3JN 2 C308 SC270P50V3JN 1 2 C306 SC270P50V3JN 1 2 2 1 ADAF1 ADAF2 ADAF3 ADAF4 CODECVREF VREFOUT 1 1 1 BC128 BC74 BC77 BC76 SCD1U16V SCD1U16V SCD1U16V SCD1U16V 2 2 1 1 AUD_AGND 18 HP_OUT_L 18 HP_OUT_R AUD_AGND AUD_AGND G32 1 2 VREFOUT GAP-CLOSE 2 BC64 SC1U10V3ZY 2 DY 1 1 2 AUD_AGND 2 G31 R313 3KR2F 1 2 GAP-CLOSE AUD_AGND 18 EXT_MIC_2 AUD_AGND CLOSE TO CODEC 14 5V_AUDIO_S0 3 G30 2 1 GAP-CLOSE 2 GAP-CLOSE 14 AUD_BEEP2 GAP-CLOSE 7 2 AUD_BEEP 1 2 10KR2 AUD_PC_BEEP 2 C304 SCD1U16V DY TSAHCT86 C303 R325 1KR2 TSAHCT86 BC65 SC1U10V3ZY AUD_AGND SCD1U16V R314 3KR2F Wistron Corporation 2 1 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. CLOSE TO CODEC BC62 SC1000P50V3KX AUD_AGND AUD_AGND AUD_AGND MIC1 PREAMP Title AUDIO CODEC AD1981B Size A3 Document Number Date: Monday, July 11, 2005 B C AUD_AGND 18 EXT_MIC_1 AUD_AGND A GAP-CLOSE AUD_AGND 1 AUD_SYS_BEEP 1 R326 AUD_AGND R347 10KR2 2 2 8 5 10 1 VREFOUT 7 14 U49C 9 AUD_AGND G73 2 U49B 4 1 7 AUD_AGND G33 6 U39_PL 1 5V_AUDIO_S0 AUD_AGND 1 CUT MOAT G72 MIC2 PREAMP 1 5V_AUDIO_S0 36 KBC_BEEP UNDER CODEC SB-27-02 TSAHCT86 2 2 AUD_AGND AUD_BEEP1 1 22 ICH_SPKR U49A 1 1 2 27 PCI_SPKR BC63 SC1000P50V3KX D Rev -1 Leopard2 Sheet E 32 of 47 B C R650 2 15KR2 4 SPKR_L+ 2 20KR2 1 1 R649 1 R339 100KR2 BC80 SC220P SC 32 AUD_LOL 5V_S0 BC81 CSOUTL1 2 SCD1U16V3KX R349 1 2 L_LINE_IN 1 SPKR_L+ 1 2 18KR2J R348 15KR2 2 1 E 2 BC143 SC10P50V2JN-1 1 BC136 AUD_LOL 1 CSOUTL2 2 SC4D7U10V5ZY 4 D 2 TC15 DK_SPKR_L+ 18 SE100U16VGM-2 3 A SC U79 BC129 BC141 SCD1U16V3KX SCD1U16V3KX AUD_AGND R_BYPASS HP_R AUD_AGND 8 2 17 23 SHUTDOWN TJ HP-IN VOL 18 19 20 21 RVDD RBYPASS RHPIN RLINEIN AUD_AGND 3 LOUT+ LOUTSE/BTL# HP/LINE# MUTEIN MUTEOUT GND/HS GND/HS GND/HS GND/HS 14 16 11 9 1 12 13 24 ROUTROUT+ 15 22 G1421BF3U Q19 2N7002 1 G PM_SLP_S3# SPKR_L+ SPKR_L- 2 LLINEIN LHPIN LBYPASS LVDD GND 1 G1420_SHUTDOWN# 22,26,36,42,44,45,46 3 10 S HPSENSE_1 AUD_AGND AUD_MUTE R648 2 DY 10KR2 G1420_SHUTDOWN# 1 AUD_AGND SPKR_RSPKR_R+ AUD_AGND 3 SC 25 HP_L L_BYPASS 2 1 BC142 SC10U10V6ZY-U 2 1 2 5VA_OP_S0 4 5 6 7 G1420_SHUTDOWN# D AUD_AGND BC73 R340 CSOUTR1 1 1 2 SCD1U16V3KX 15KR2 32 AUD_LOR 2 R_LINE_IN 1 R341 SPKR_R+ 2 18KR2J 1 DK_SPKR_R+ 18 2 TC14 SE100U16VGM-2 BC70 SC220P 5VA_OP_S0 5V_S0 AUD_LOR 1 BC132 2 CSOUTR2 SC4D7U10V5ZY R642 1 G71 2 1 R643 SPKR_R+ 2 20KR2 15KR2 1 2 SC 1 GAP-CLOSE-PWR 2 BC131 SC10P50V2JN-1 5V_S0 1 R_BYPASS 1 2 2 5V_S0 1 HPSENSE_1 Q41 2N7002 2 1 18 EARPHONE 1 R303 S 2 22KR2J C616 SC1U10V3ZY 2 2 D EARPHONE_R AUD_AGND HPSENSE 32 1 3 2 AUD_AGND 1 G 2 BC130 SC4D7U10V5ZY HPSENSE_1 32 R640 100KR2 18 JACK_DETECT# BC79 SC4D7U10V5ZY 2 R641 100KR2 2 1 L_BYPASS C291 SC1U10V3ZY 5V_S0 36 KBC_MUTE 4 32,36 EAPD 5 14 6 AUD_MUTE_1 9 HPSENSE 10 U78C 8 TSAHCT32 AUD_MUTE SPKR_RSPKR_L+ SPKR_L- SPK1 6 4 3 2 1 1 5 TSAHCT32 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. ETY-CON4-11-U EC155 SC220P 2 R645 10KR2 7 1 1 Speaker SPKR_R+ U78B 7 14 5V_S0 EC158 SC220P EC161 SC220P EC159 SC220P 20.D0151.104 Title AUDIO Size A3 Document Number Date: Thursday, July 07, 2005 A B C D Rev -1 Leopard2 Sheet E 33 of 47 A B C D E MINI-PCI 4 4 PCI_C/BE#[3..0] 1 1 BC127 SCD1U16V 2 2 BC124 SCD1U16V 2 BC126 SC4D7U10V5ZY 18,22,27,30 2 PCI_AD[31..0] 1 1 3D3V_S0 BC125 SCD1U16V 22,27,30 3D3V_S5 3D3V_S0 2 CN13 1 TIP R612 DUMMY-R2 1 2 R328 10KR2 3 19 802_ACT_LED 1 G 22 WIRELESS_EN# 2 3 WIRELESS_EN D Q18 2N7002 S WIRELESS_EN INT_PIRQE# 3D3V_S0 MINI_PIN21 TP11 3 PCLK_MINI 22 PCI_REQ#0 PCI_AD31 PCI_AD29 PCI_AD27 PCI_AD25 31 WLAN_ACT 3D3V_S0 PCI_AD21 PCI_AD19 1 PCI_AD17 PCI_C/BE#2 R613 10KR2 2 PCI_C/BE#3 PCI_AD23 22,27,30 PCI_IRDY# 22,27,30,36 PM_CLKRUN# 22,27,30 PCI_SERR# 22,27,30 PCI_PERR# PCI_C/BE#1 PCI_AD14 PCI_AD12 PCI_AD10 2 PCI_AD8 PCI_AD7 PCI_AD5 PCI_AD3 5V_S0 PCI_AD1 1 125 2 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 123 124 126 RING 5V_S0 INT_PIRQE# 22,30 3 3D3V_S5 PCIRST1# 24,27,28,30,36 3D3V_S0 PCI_GNT#0 22 MINI_PME# 1 R619 2 DY 0R2-0 PCI_AD28 PCI_AD26 PCI_AD24 MOD_IDSEL 1 R620 PCI_AD22 PCI_AD20 ICH_PME# 18,22,30 BT_PRIOR 31 PCI_AD30 2 10R2 PCI_AD21 PCI_PAR 22,27,30 PCI_AD18 PCI_AD16 PCI_FRAME# 22,27,30 PCI_TRDY# 22,27,30 PCI_STOP# 22,27,30 PCI_DEVSEL# 22,27,30 PCI_AD15 PCI_AD13 PCI_AD11 2 PCI_AD9 PCI_C/BE#0 PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0 PCI_SERIRQ 22,27,36 3D3V_S5 PCIMODEM124A1U1 62.10032.001 1 1 The symbol use 2nd source The P/N is the main source Main source:62.10032.001 2nd source:62.10032.031 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title MINI-PCI Size A3 Document Number Rev A B C D -1 Leopard2 Date: Thursday, July 07, 2005 Sheet E 34 of 47 A B C D E USB POWER 5V_S3 5V_USB1_S3 F2 100 mil 2 2 4 C150 SCD1U16V SC4D7U10V5ZY 2 C152 1 SC C151 SC1000P50V 2 MINISMDC110-U 1 1 2 1 1 TC7 ST100U6D3VBM 4 USB_P_CON3 22 USB_PP4 USB_N_CON3 22 USB_PN4 5V_USB1_S3 USB1 11 9 1 USB_N_CON3 USB_P_CON3 3 5 2 3 4 10 12 USB_N_CON4 USB_P_CON4 6 7 8 3 SKT-USB-76-U USB_P_CON4 22 USB_PP5 USB_N_CON4 22 USB_PN5 2 2 MDC Connector 2 AUD_MDCIN DUMMY-R2 G68 2 2 GAP-CLOSE-PWR 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 33 34 1 32 C578 SCD1U16V SC4D7U10V5ZY AUD_PHONE 32 Check with Ambit ACSDATAIN1_A ACSDATAIN1_B 1 R266 AMP-CONN30A-1 20.F0099.030 2 22R2 1 R263 AC97_SYNC 21,32 AC97_DIN1 21 2 DY 22R2 1 AC97_BITCLK 21,32 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. C266 SC22P Title DY 2 DY C579 2 C580 SCD1U16V 1 1 21,32 AC97_DOUT 21,32 AC97_RST# 2 1 MDC_S3_1 31 1 R622 DUMMY-R2 CN9 35 1 1 3D3V_S0 36 3D3V_S3 2 1 R254 32 AUD_MDC_OUT USB / MDC CONN. Size A3 Document Number Date: Thursday, July 07, 2005 A B C D Rev -1 Leopard2 Sheet E 35 of 47 B C KBC_3D3V_AUX D RTC_AUX_S5 5 6 37 KROW[1..8] KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7 KROW8 10 MOLEX-CON8-2 37 KCOL[1..16] DY KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 4 3 2 1 3D3V_S0 5 6 7 8 RN6 SRN10K-2 1 2 2 BC48 SC3P50V2CN 1 R253 KBC_32KX1 KBC_32KX2 2 0R2-0 18 VOL_UP_DK# 18 VOL_DWN_DK# 40 CHG_I_SEL 40 CHG_I_PRE_SEL 40 CHG_ON# 13 BL_ON 19,37 ID_DET 19 FPBACK 25,42 S5_ENABLE 3D3V_S5 CHG_ON# VCC_+3VSB 22 RSMRST#_KBC 2 39 AD_OFF BC52 SC1U10V3ZY 38 KBCBIOS_CS# TPAD30 TP34 TPAD30 TP43 1 KBC_SEL1 KBC_CLK 49 50 51 52 53 56 57 58 59 60 61 64 65 66 67 68 105 106 107 108 109 KBSOUT0 KBSOUT1 KBSOUT2 KBSOUT3 KBSOUT4 KBSOUT5 KBSOUT6 PortC KBSOUT7 KBSOUT8 KBSOUT9 KBSOUT10 KBSOUT11 KBSOUT12 PortD-1 KBSOUT13 KBSOUT14 KBSOUT15/XOR_OUT PortE TINT# TCK JTAG Debug Port TDO TDI TMS 110 111 114 115 116 117 118 119 IOPF0/PSCLK1 IOPF1/PSDAT1 IOPF2/PSCLK2 IOPF3/PSDAT2 IOPF4/PSCLK3 IOPF5/PSDAT3 IOPF6/PSCLK4 IOPF7/PSDAT4 158 160 32KX1/32KCLKIN 32KX2 PortB IOPM0/D8 IOPM1/D9 IOPM2/D10 IOPM3/D11 IOPM4/D12 IOPM5/D13 IOPM6/D14 IOPM7/D15 173 174 47 SEL0# SEL12_SEL2# IOPQ3/CLK R262 DA_BRI 1 2 DY 0R2-0 CHG_ICTL CHG_VCTL BRIGHTNESS 19 PWM_BRI 1 R265 2 0R2-0 CDROM_BT# 37 CIR_KBC 18 AC_IN# 40 IOPE4/SWIN IOPE5/A20//EXWINT40 IOPE6/LPCPD#/EXWINT45 IOPE7/CLKRUN#/EXWINT46 2 44 24 25 KBC_PWRBTN# 37 KBC_LID# 19 138 139 140 141 144 145 146 147 PortJ-2 1 1 1 2 2 2 1 BT_SCL BT_SDA 2 C278 SCD1U16V3KX KBC_3D3V_AUX RN2 KBC_PME# PM_PWRBTN# KBC_3D3V_AUX DVD_BT# CDROM_BT# AC_IN# 1 R233 1 R261 1 R651 B 1 DUMMY-R2 RSMRST#_KBC 1 R247 2 100KR2 S5_ENABLE 1 R238 2 10KR2 SB KBC HARDWARE SETTING KBC_3D3V_AUX A0/ENV0 A1/ENV1 A2/BADDR0 1 R249 RN3 2 DUMMY-R2 2 1 2 3 4 SRN10KJ SB-31-02 A3/BADDR1 1 R248 150 151 SELIO# PortD-2 PortM IOPD4 IOPD5 IOPD6 IOPD7 41 42 54 55 PR_INSERT# 18 KBC_MUTE 33 ECSWI#_KBC 22 PortK A8 A9 A10 A11 A12 A13_BE0 A14_BE1 A15_CBRD 143 142 135 134 130 129 121 120 A8 38 A9 38 A10 38 A11 38 A12 38 A13 38 A14 38 A15 38 PortL A16 A17 A18 IOPL3/A19 IOPL4/WR1# 113 112 104 103 48 A16 38 A17 38 A18 38 C 2 R234 3 2 10KR2 2 10KR2 2 10KR2 A4/TRIS KBCBIOS_RD# 38 KBCBIOS_WE# 38 KBC_SEIO# TP10 TPAD30 WR1# IRE OBD DEV PROG 2 DUMMY-R2 1 R243 ENV0 0 0 1 1 2 DUMMY-R2 ENV1 0 1 0 1 TRIS 0 0 0 0 SHBM=1: Enable shared memory with host BIOS TRIS=1: While in IRE and OBD, float all the signals for clip-on ISE use I/O Address BADDR1-0 Index Data 0 0 2E 2F 0 1 4E 4F 1 0 (HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1 1 1 Reserved 1 Wistron Corporation TP36 TP44 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title KBC NS97551 C255 SCD1U16V Size Document Number Custom For NS97551 use only Date: Thursday, July 07, 2005 A 3 4 SRN10KJ 1 2 6K8R2F R232 1 2 6K8R2F R231 1 2 10KR2 R259 BT_SDA PM_CLKRUN# 22,27,30,34 152 KBC_PIN21 DY 2 1 BT_SCL A0/ENV0 38 A1/ENV1 38 A2/BADDR0 38 A3/BADDR1 38 A4/TRIS 38 A5/SHBM 38 A6 38 A7 38 KBC_D[0..7] 38 KBC_D0 KBC_D1 KBC_D2 KBC_D3 KBC_D4 KBC_D5 KBC_D6 KBC_D7 8 7 6 5 SRN10K SMBC_KBC SMBD_KBC DVD_BT# 37 PM_SLP_S4# 22,26,42 PM_SLP_S3# 22,26,33,42,44,45,46 CLK32_G768 25 KBC_PME# 1 2 0R2-0 R260 1 2 3 4 2 100KR3F CAPS_LED 19 NUM_LED 19 MUTE_LED 18,19 BT_SCL 39 BT_SDA 39 PCIRST1# 24,27,28,30,34 RD# WR0# AGND AD_IA 1 R275 MUTE_BTN# 37 802_BT_BTN# 37 BRIGHTNESS 26 29 30 D0 D1 D2 D3 D4 D5 D6 D7 RN9 VOL_UP_BTN# VOL_DWN_BTN# VOL_UP_DK# VOL_DWN_DK# KBC_BEEP 32 PWR_LED 19 CHG_LED 19 VOL_UP_BTN# 37 VOL_DWN_BTN# 37 IOPD0/RI1#/EXWINT20 IOPD1/RI2/EXWINT21 IOPD2/EXWINT24/RESET2# 124 125 126 127 128 131 132 133 BT_SENSE TP41 TP37 PM_PWRBTN# 22 SMBC_KBC 25 SMBD_KBC 25 A0/ENV0 A1/ENV1 A2/BADDR0 A3/BADDR1 A4/TRIS A5/SHBM A6 A7 3D3V_S0 R274 560KR3F TP17 TP16 168 169 170 171 172 175 176 1 PortJ-1 1 1 1 1 1 161 VBAT 32 33 36 37 38 39 40 43 THERMAL_DP THERMAL_DN IOPC0 IOPC1/SCL2 IOPC2/SDA2 IOPC3/TA1 IOPC4/TB1/EXWINT22 IOPC5/TA2 IOPC6/TB2/EXWINT23 IOPC7/CLKOUT PortP 96 PC97551-VPC-U 99 100 101 102 BT_TH 39,40 AIRLINE_VOLT 40 AD_IA 40 PM_SUS_STAT# 22 KBC_MATRIX1 37 KBC_MATRIX2 37 EAPD 32,33 153 154 162 163 164 165 PS2 Interface GND GND GND GND GND GND GND 10KR2 2 IOPA0/PWM0 IOPA1/PWM1 IOPA2/PWM2 IOPA3/PWM3 IOPA4/PWM4 IOPA5/PWM5 IOPA6/PWM6 IOPA7/PWM7 81 82 83 84 87 88 89 90 93 94 IOPB0/URXD1 IOPB1/UTXD1 IOPB2/USCLK1 IOPB3/SCL1 IOPB4/SDA1 IOPB7/RING#/PFAIL#/RESET2# PortH IOPJ2/BST0 IOPJ3/BST1 IOPJ4/BST2 IOPJ5/PFS IOPJ6/PLI IOPJ7/BRKL_RSTO# 148 149 155 156 3 4 27 28 A5/SHBM 95 Key Matrix Scan KBC_3D3V_AUX 1 R244 AVCC PWM or PortA KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7 62 63 69 70 75 76 CHG_I_SEL CHG_I_PRE_SEL 1 2 100KR2 PSDAT4 2 10KR2 DA0 DA1 DA2 DA3 DA Output 17 35 46 122 137 159 167 1 2 KBC_32KX2_1 1 R236 1 R242 PSCLK1 PSDAT1 PSCLK2 PSDAT2 R237 37 TCLK_5 X1 3D3V_S0 37 TDATA_5 X-32D768KHZ-12-U20MR3 3 BC50 SC3P50V2CN 4 2 1 1 TINT# TCK TDO TDI TMS Host Interface 71 72 73 74 77 78 79 80 BC57 SCD1U16V 4 AD0 AD1 AD2 AD3 IOPE0 IOPE1 IOPE2 IOPE3 NC#93 NC#94 AD input IOPB5/(GA20) IOPB6/KBRST# BC55 SCD1U16V 1 21 ICH_A20GATE 21 RCIN# BC54 SCD1U16V 2 IOPD3/ECSCI BC49 SCD1U16V 1 31 BC46 SCD1U16V BT+ 2 22 ECSCI#_KBC KBC_PWUREQ# BC51 SCD1U16V BT_SENSE NC#11 NC#12 NC#20 VCORF NC#85 NC#86 NC#91 NC#92 NC#97 NC#98 9 KBC_D0 TINT# TCK TDO TDI TMS BC47 SCD1U16V SCD1U16V 11 12 20 21 85 86 91 92 97 98 CN15 34 45 123 136 157 166 16 SERIRQ IOPQ0/LDRQ# LFRAME# LAD0 LAD1 LAD2 LAD3 LCLK RESET1# IOPQ1/SMI# IOPQ2/PWUREQ# LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 3 PCLK_KBC 21,25,43 RSMRST# 22 ECSMI#_KBC 2 DUMMY-R2 ECSWI#_KBC 1 R273 KBC_3D3V_AUX 2 VDD 2 7 8 9 15 14 13 10 18 19 22 23 22,27,34 PCI_SERIRQ 21 LPC_LDRQ0# 21 LPC_LFRAME# 3 U40 BC53 SCD1U16V VCC VCC VCC VCC VCC VCC 1 21 LPC_LAD[0..3] 4 1 2 3 4 5 6 7 8 BC56 2 GAP-CLOSE-PWR 2 1KR2 2 2 DY KBC_RTC_VCC1 R235 2 2 2 2 1 D13 BC45 SSM5818SL SCD1U16V 3D3V_S0 G27 1 2 BLM11P600S KBC_AVCC 1 1 KBC_3D3V_AUX E KBC_3D3V_AUX L18 3D3V_AUX 2 A D Rev Leopard2 Sheet E -1 36 of 47 A B C D E 3D3V_S0 1 INTERNAL KEYBOARD CONNECTOR 1 3D3V_S0 R406 10KR2 KCOL[1..16] R415 10KR2 36 2 4 802_BT_BTN# 5V_S3 LAUNCH Board MUTE_BTN# 1 C335 1 R407 10KR2 19,36 ID_DET 19 NUM_LED# 36 MUTE_BTN# 2 POWER BUTTON 1 R416 36 KBC_PWRBTN# 2 470R2 DY 1 SCD1U10V2MX-1 DVD_BT# CDROM_BT# 22 1 36 DVD_BT# 36 CDROM_BT# EC101 EC100 SC1000P16V2KX SC1000P16V2KX JST-CON20 2 2 KBC_MATRIX2,KBC_MATRIX1 PA 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5V_S0 1 26 2 C336 PWRBTN# the matrix table for PCB R277 10KR2 1 BC86 SCD1U16V KBC_3D3V_AUX R278 10KR2 2 SCD1U10V2MX-1 19 PWR_LED# 19 MUTE_LED# 19 802_BT_LED# 36 VOL_UP_BTN# 36 VOL_DWN_BTN# 36 802_BT_BTN# 3D3V_AUX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 KROW8 KROW7 KCOL10 KROW5 KROW6 KCOL1 KROW3 KROW4 KCOL6 KCOL2 KROW1 KCOL3 KCOL5 KCOL8 KCOL9 KCOL7 KCOL4 KCOL13 KCOL14 KCOL15 KCOL12 KCOL11 KCOL16 2 KROW2 2 2 3 PR 3D3V_S0 DY Discrete 00 01 UMA 10 11 1 1 ETY-CON24-1 20.K0170.001 2 2 2 EC98 SC1000P16V2KX 1 EC97 EC96 SC1000P16V2KX 2 D29 SC1000P16V2KX 3D3V_S0 EC95 2 EC94 EC99 SC1000P16V2KX 1 DY 1 1 1 BAV99LT1 1 VOL_DWN_BTN# VOL_UP_BTN# 802_BT_LED# MUTE_LED# PWR_LED# NUM_LED# 2 2 VOL_UP_BTN# 3 KBC_MATRIX2 36 KBC_MATRIX1 36 2 10KR2 1 1 10KR2 1 D28 R279 2 2 R276 SC1000P16V2KX 3 1 4 21 CN8 25 CN2 SC1000P16V2KX 36 2 KROW[1..8] VOL_DWN_BTN# 3 1 DY TouchPad Connector 1 2 2 R556 10KR2 2 R555 10KR2 KCOL16 KCOL11 KCOL12 KCOL15 1 KCOL14 KCOL13 KCOL4 KCOL7 2 KROW1 KCOL2 KCOL6 KROW4 1 KCOL9 KCOL8 KCOL5 KCOL3 5V_S3 1 BAV99LT1 CN7 9 8 7 6 5 4 3 2 for EMI KROW3 KCOL1 KROW6 KROW5 KCOL10 KROW7 KROW8 KROW2 DY 1 BC114 DY SCD1U16V DY BC30 2 BC116 SC1U10V3ZY 2 DY for EMI SC47P50V2JN 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 BC115 2 RC1 SRC100P50V-U 1 8 7 6 5 RC3 SRC100P50V-U 2 RC4 SRC100P50V-U SC47P50V2JN RC2 SRC100P50V-U 8 7 6 5 8 7 6 5 8 7 6 5 36 TDATA_5 36 TCLK_5 1 10 ETY-CON8-5 1 8 7 6 5 8 7 6 5 1 Wistron Corporation RC6 SRC100P50V-U 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 2 3 4 1 2 3 4 RC5 SRC100P50V-U Title KEYBOARD/TOUCH PAD/Launch key Size A3 Document Number for EMI Date: Thursday, July 07, 2005 A B C D Rev Leopard2 Sheet E -1 37 of 47 A B C D E 4 4 3 KBC_D[0..7] 3 36 FLASH ROM 2 2 512KB Flash U46 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 KBC_3D3V_AUX 36 36 A0/ENV0 A1/ENV1 A2/BADDR0 A3/BADDR1 A4/TRIS A5/SHBM A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A0/ENV0 A1/ENV1 A2/BADDR0 A3/BADDR1 A4/TRIS A5/SHBM A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 20 19 18 17 16 15 14 13 3 2 31 1 12 4 5 11 10 6 9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 8 VDD KBC_D0 KBC_D1 KBC_D2 KBC_D3 KBC_D4 KBC_D5 KBC_D6 KBC_D7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 21 22 23 25 26 27 28 29 CE# 30 KBCBIOS_CS# 36 WE# 7 KBCBIOS_WE# 36 OE# 32 KBCBIOS_RD# 36 VSS 24 PM39LV040-70VC 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title BIOS/GF Size A3 Document Number Date: Thursday, July 07, 2005 A B C D Rev Leopard2 Sheet E -1 38 of 47 A B C D E Adaptor in to generate DCBATOUT D23 3 Layout 200mil 1 AD+ MMBZ5252B DCIN1 4 AD_JK 3 1 2 3 4 AD+_2 8 7 6 5 2 2 C317 SCD1U50V5KX 2 1 R26 100KR2 2 B C Q3 2 IN 36 AD_OFF 1 Q5 PDTA124EU 1 E AD_OFF# 3 3 OUT R1 EC2 1 1 2 BC83 SCD1U50V3ZY 2 5 SKT-JACK-134-GP 4 D D D D AO4407 BC82 SC1000P50V R25 200KR2J 2 4 1 EC1 SCD1U50V3ZY 2 1 1 2 U2 S S S G SCD1U50V3ZY 1 1 GND R2 DTC114EUA-U1 3 3 3D3V_AUX 3D3V_AUX D24 D25 2 BT_SCL 3D3V_AUX D3 2 3 BT_SDA 1 3 2 BT_TH 1 BAV99LT1 BAV99LT1 3 1 BAV99LT1 BATTERY CONNECTOR 2 2 BT+ CN11 2 7 1 F3 FUSE-10A125V 1 G6 40 BT+SENSE 1 2 3 4 5 6 8 36 BT_SCL 36 BT_SDA 36,40 BT_TH SB 2 2 BCC1 SCD1U 2 1 SYN-CON6-2-U2 1 GAP-CLOSE BC3 SC1000P50V 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Adaptor/ Bettery conn. Size A3 Document Number Rev A B C D -1 Leopard2 Date: Thursday, July 07, 2005 Sheet E 39 of 47 2 C4 SCD1U D1 2 1 AD+ U51 S S S G AD+_TO_SYS 2 2 D01R2512F-1-GP R37 DUMMY-R3 C338 SC1U50V5ZY G35 1 GAP-CLOSE-PWR Close to MAX1909 pin 24 1 1 1 C331 SC10U25V6KX 2 1 C38 SCD1U 4 3 2 1 U5 SI4431BDY C330 SC10U25V6KX R410 33R2 MAX8725_GND 22 28 2 DLOV 21 DHI 23 MAX8725_DHI DLO 20 MAX8725_DLO PGND 19 2 DHIV PDL LDO 5 6 7 8 CSSN 1 1 2 25 26 CSSP SC1U10V3ZY 1 Near MAX8725 Pin 21 BT+ 1 2 2 1 VCTL ICTL MODE IINP 9 CLS 6 ACOK 2 CHG_PWR-3 1 IND-10UH-28 R409 R427 49K9R2F MAX8725_GND G5 5 29 CSIP 18 CSIN BATT GND 17 16 15 PKPRES 1 2 GAP-CLOSE-PWR MAX8725_GND 1 1 2 G37 1 C334 C332 C333 SC10U25V6KX SC10U25V0KX SC10U25V0KX 2 2 PKPRES# PGND 1 G S S S 2 31K6R3F 4 3 2 1 1 R426 1 MAX8725_LDO 2 U6 SI4800BDY PKPRES# R422 100KR2 2 D015R2512F-1 5 6 7 8 8 1 GAP-CLOSE-PWR 2 MAX8725_CLS ACIN CHG_PWR-2 2 2 MAX8725_IINP AC_IN 3 L22 D D D D R428 49K9R2F C342 SC1U10V3ZY 1 2 MAX8725_VCTL 11 MAX8725_ICTL 10 MAX8725_MODE 7 MAX8725_DLOV 2 2 1 2 D D D D 1 C55 1 S S S G MAX8725_PDS27 AD+_TO_SYS 24 PDS SRC MAX18725_DC_IN 1 DCIN MAX8725_LDO 1 Near MAX8725 Pin 2 C341 SCD1U MAX8725_DHIV U7 R411 100KR2 DCBATOUT 2 DUMMY-R3 MAX8725_LDO MAX8725_GND MAX8725_GND 4.2V/cell 1 C44 SCD1U25V3KX 1 2 1 2 C339 SCD1U25V3KX C54 SCD1U R429 100KR2F 1 0R2-0 AO4407 2 2 1 C340 SCD1U25V3KX MAX8725_GND 2 R421 1 R405 AD+_TO_SYS 2 MAX8725_LDO 36,39 BT_TH 8 7 6 5 SC CH521S-30 R423 68KR3F D D D D GAP-CLOSE-PWR D27 1 U54 S S S G DY G34 MAX8725_ACIN R425 19K1R2F AD+ 1 2 3 4 2 AO4407 2 AC_IN Threshold 2.089V Max. AC_IN > 2.089V --> AC DETECT 1 R364 1 1 2 3 4 2 R424 100KR2F D D D D 2 1 8 7 6 5 G36 HM1-SB AD<=17V, disable charger function BT+ DCBATOUT BAV99LT1 2 0707 -1 ISOURCE_MAX = (0.075/R364)*(VCLS/VREF) TOTAL_POWER : Adapter=90W,Total_Power=81W GAP-CLOSE-PWR 15K4R2F-GP 1 AIRLINE_VOLT 36 1 R17 2 100KR2F 3D3V_S5 3 2 2 2 1 R18 1 1 2 1 2 2 2 1 G 1 2 2 MAX8725_GND CHG_I_PRE_SEL D Q7 36 CHG_I_SEL S 2N7002 Q44 1 G 2N7002 3 L: Charge ON36 R205 20KR2F 2 is 2 CHG_PBATT R43 29K4R2F D SB S DY MAX8725_GND SB MAX8725_GND DY 3 2 H: Charge OFF Q43 S2N3904-U3 1 SC MAX8725_ICTL 1 1 3 Q8 2N7002 S AC_IN R414 68KR3F 2 1 1 2 is R44 2K2R2F D 1 G CHG_PBATT C56 SC1U10V3ZY R413 39KR2F R47 100KR2 36 CHG_ON# 3 MAX8725_REF MAX8725_GND 3D3V_AUX AC_IN# 36 MAX8725_CLS 1 2 GAP-CLOSE-PWR 2 1 R412 49K9R2F 1 2 G8 2 2 1 1 2 C53 SCD1U25V3KX 2 2 C51 SCD1U MAX8725_GND V_REF :4.2235V (<500uA) MAX8725_REF R42 20KR2F parallel to KBC GND is KBC's GND MAX8725ETI C43 SCD01U50V3KX C52 SCD01U50V3KX 1 0707 -1 BT+SENSE 39 From Battery Connector REF 1 GAP-CLOSE-PWR CCV CCI CCS 1 R41 10KR2 2 13 12 14 4 G7 1 36 AD_IA MAX8725_GND MAX8725_CCV MAX8725_CCI MAX8725_CCS 1 MAX8725_GND MAX8725_GND MAX8725_GND If Charger is MAX1909,dummy them. ICTL : 0A 0.3A 1.5A 2.5A CHG_ON# H L L L CHG_I_SEL L L H L CHG_I_PRE_SEL L H L L Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CHARGER MAX8725 Size Document Number Custom Rev -1 Leopard2 Date: Thursday, July 07, 2005 Sheet 40 of 47 A B C 5V_S5 D E 5V_S5 2 1 40 MAX1907_CC 12 2 C1 SC270P50V2JN 15 NEG 14 POS 13 GND NC 11 41 TIME 1 R16 1 2 S S 2 DUMMY-R3 1 2 C37 SCD47U10VKX G4 1 R13 MAX1907_NEG G3 2 130R3F 1 2 TC3 3 GAP-CLOSE-PWR 1907_CSP 1 R10 R382 1K18R3F 1 R371 TC4 GAP-CLOSE-PWR LS/IRFR3709Z/8.2mOhm/@4.5V MAX1907AETL-U TC2 SE220U2VDM-6 2 1 1 R31 1 1 1 2 Q4 IRFR3709Z G 2 C5 SC100P50V2JN-U 1 1 R381 2 DY 130R3F 2 698R2F G1 2 100KR2F 1 offset 1.2% R7 47KR3 2 GAP-CLOSE 2 1 2 0R2-0 2 1 1 2 SC4D7U25V6KX-L 1 2 SC4D7U25V6KX-L 1 2 SC4D7U25V6KX-L 1 2 SC4D7U25V6KX-L 1 2 SCD1U 4 3 1 TC17 GAP-CLOSE-PWR Q30 IRFR3709Z 2 110R2F 2 698R2F G2 D 2 39 20 PM_STPCPU# 2 R374 100KR2 4 1 R12 1 1 1 2 DDO# 3,22 PM_STPCPU# 22 PM_DPRSLPVR 1 R11 2 C6 SC470P50V2KX MAX1907_POS SUS ILIM 35 MAX1907_ILIM 9 27 R32 698R2F D 2 MAX1907_OAIN+ MAX1907_OAIN- 1 2 200R2F SE220U2VDM-6 17 16 2 C9 SC1000P50V 1 R22 SE220U2VDM-6 OAIN+ OAIN- 1 1 1907_CSP1 1907_CSN1 2 IND-D68UH-10 2 18 19 2 200R2F SE220U2VDM-6 CSP CSN 1 1 R23 2 PGND 1 29 28 FB VCC_CORE_S0 L1 G DPSLP# REF R373 150KR2F 2 C3 SC1U10V3KX 2 MAX1907_DL DL CC 8 MAX1907_REF HS/IRFR3707Z/12.5mOhm/@4.5V SHDN# TON 4 TC16 SE100U25VM-L1-GP MAX1907_LX 2 R372 DUMMY-R2 1 S MAX1907_DH VCC_CORE_S0_G92 Ton=NC, Freq.=300KHz G S C328 SCD1U 1 7 C11 2 2 1KR2 32 C13 1907_CSP_G 1 R5 LX C327 1 G 2 C10 SCD1U25V3KX 1 C329 1 42 CPU_SHDN# 3 33 2 0R3-0-U Q6 IRFR3707Z C14 2 B0 B1 B2 DH 1 R24 1 4 1 2 3 31 Q29 IRFR3707Z SSM5818SL 3 D0 D1 D2 D3 D4 D5 BST D 4 1 26 25 24 23 22 21 2 MAX1907_B0 R6 MAX1907_B1 100KR2 MAX1907_B2 S0 S1 S2 30 D D2 3 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 4 5 6 CLKEN# SYSPOK IMVPOK VDD C12 1 MAX1907_S0 MAX1907_S1 MAX1907_S2 DCBATOUT 3 2 38 36 37 SYSPOK 25 VGATE 5 5 5 5 5 5 V+ VCC 1 1 1 3,25 CLK_PWRGD# DCBATOUT 1 1 U1 34 R9 100KR2 10 R15 100KR2 SC4D7U10V5ZY 2 2 4 R8 2K2R2F R2 0R3-0-U DY 2 C2 SC4D7U10V5ZY 1 2 R4 0R3-0-U 2 C7 SCD1U25V3KX 1 2 3D3V_S0 1 DCBATOUT R3 10R3 2 MAX1907_VCC 1 1 CPU_CORE-MAX1907 5V_S0 1 R14 DUMMY-R2 3D3V_S0 3D3V_AUX 1 2 2 2 VCCP_GMCH_S0 1 R1 100KR2 DY SYSPOK 2 3 2 R21 4K7R2 2 R19 10KR2 1 OCP=30A, Vally current = 27.5A, Vilim=550mV(55mVp-p*10) 0 0 0 1.324 0 1 1 0 1 0 1.292 0 1 1 1 0 0 1.260 0 1 1 1 0 1 1.244 2 0 1 1 1 1 1 1.212 1 1 0 0 0 0 1 1.180 1 0 0 0 1 1 1.148 1 0 0 1 1 0 1.100 1 0 1 0 0 1 1.052 1 0 1 0 1 1 1.020 1 0 1 1 1 0 0.972 1 1 0 0 0 0 0.940 1 1 MAX1907_B2 2 1 R368 DUMMY-R2 R378 DUMMY-R2 R379 20KR2 3 Q2 S2N3904-U3 1 2 1 1 0 S C8 R20 22KR2J 2 1 1.340 SCD1U10V2MX-1 1 1 1 2 0 1 1 R380 20KR2 2 2 2 R376 20KR2 2 1 1 2 R377 20KR2 R375 DUMMY-R2 1 R369 DUMMY-R2 2 MAX1907_B1 V 0 5V_S0 1 MAX1907_B0 R370 DUMMY-R2 2 MAX1907_S2 1 5V_S0 1 1 5V_S0 R365 DUMMY-R2 2 MAX1907_S1 R366 DUMMY-R2 2 2 R367 DUMMY-R2 MAX1907_S0 5V_S0 1 5V_S0 1 5V_S0 VID5 VID4 VID3 VID2 VID1 VID0 2 Deeper Sleep Voltage : 0.748V , S0=L, S1=H, S2=Open, D Q1 2N7002 1 G Vcore VID Boot-up Voltage : 1.2V , B0=L, B1=L, B2=Open 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title IMVP IV-CPU POWER-MAX1907 Size A3 Document Number Date: Monday, July 11, 2005 A B C D Rev -1 Leopard2 Sheet E 41 of 47 5 4 2 C212 SC5600P25V2KX 2 1 150R2F 1 1 R190 For 5V SETTING=5.0915V 2 29K4R2F close to IC 2 1KR2F 1 R208 R209 1K8R2 C209 1 2 2 4K99R2F 5130_5V_LDO close to IC C208 1 2 2 5130_FB3 SCD1U16V2KX-2 1 2 R575 Vo=(R1*0.85)/R2+0.85 5130_OUT1U 5130_OUT1D close to IC 1 2 OCP 5.82A=>R182=10K close to IC 2 C520 5130_LL1 SCD1U16V2KX-2 1 11K5R2F DCBATOUT 1 R183 2 10KR3F 5130_TRIP2 BAW56-1 SC 1 R587 3K24R2F 5130_LL1 43 5V_OCP SC 5130_OUT1U 43 5130_OUT1D 43 DCBATOUT 1 R207 2 15KR3F 5130_TRIP3 5130_TRIP1 C528 5130_INV1 SC8200P25V2KX 5130_FB1 5130_TRIP2 C223 1 2 SB DCBATOUT SCD1U16V2KX-2 5130_FLT close to IC 5V_AUX 5130_3D3V_LDO 3 5 2 R185 150KR2J 3 OUT 1 GND 5130_REF 2 SC Q42 2 IN SB 1 2N7002DW 84.27002.03F PM_SLP_S3# PM_SLP_S4# 5130_FB1 5130_SS_STBY1 5130_INV2 5130_FB2 5130_SS_STBY2 5130_PWMSEL 5130_CT 6 31 TPS5130_1D8V_EN# 5130_SS_STBY1 1 2 TPS5130_1D8V_EN# 100KR2 4 R1 R2 DTC115EE-U DCBATOUT 1 R184 2 100KR2 STBY_REF 5130_STBY_LDO 1 2 3 4 5 6 7 8 9 10 11 12 5130_LL2 5V_AUX G59 2 C527 5130_LH2 1 2 INV1 FLT LH1 OUT1_U LL1 OUT1_D OUTGND1 TRIP1 VIN_SENSE12 TRIP2 OUTGND2 OUT2_D SC1000P50V2KX U71 C 5130_5V_LDO U73 1 GAP-CLOSE-PWR 5130_LL2 43 SCD1U16V2KX-2 DCBATOUT FB1 SS_STBY1 INV2 FB2 SS_STBY2 PWM_SEL CT GND REF STBY_VREF5 STBY_VREF3.3 STBY_LDO LL2 OUT2_U LH2 VIN VREF3.3 VREF5 REG5V_IN LDO_IN LDO_CUR LDO_GATE LDO_OUT INV_LDO TPS5130 36 35 34 33 32 31 30 29 28 27 26 25 close to IC 5130_OUT2U 5130_REGIN G67 5130_OUT2U 43 2 1 GAP-CLOSE-PWR 5130_5V_LDO 5130_3D3V_LDO 2 C207 SCD1U25V2ZY-U 1 5V_S3 SC4D7U10V5ZY 78.47593.411 1 2 OCP 8.88A=>R207=15K 5130_OUT2D 43 C533 2 T(soft)=1.736ms 5130_OUT2D 48 47 46 45 44 43 42 41 40 39 38 37 2 1 5130_FLT 5130_INV1 C521 SCD01U16V2KX C530 1 C 2 1 0703 -1 22,26,33,36,44,45,46 SC 5130_LH1 2 10KR2F-U D 3D3V_OCP D11 5130_INV3 1 2 C522 SC6800P25V2KX-N2 2 1 680R3F OCP 8.2A=>R186=13K close to IC 1 2 1 R576 C228 SC4700P50V2KX 2 1D8V_PWR DCBATOUT 1 R186 2 13KR3F 5130_TRIP1 SCD1U16V2KX-2 C211 5130_INV2 SC3300P50V2KX 5130_FB2 For 1.8V SETTING=1.82V 2 5V_PWR 1 1 2 2 1 R211 SC C210 2 1 2 330R2F SC4700P50V2KX 1 R210 R189 2K7R2J 1 R191 1D8V_OCP (1D8V=>CH1 , 3D3V=>CH2 , 5V =>CH3) 3 1 R187 1 R574 1 3D3V_PWR 2 10KR2F-U D 2 TI TPS5130 for 1D8V, 3D3V, 5V For 3.3V SETTING=3.349V 1 R188 3 C526 SCD1U25V2ZY-U 2 BL3# B 1 D36 SB PM_SLP_S4# 5130_CT 5V_AUX 1 0R2-0 R663 3 4 2 5 1 6 2 S5PWR_ENABLE 25 5130_REF 1 0R2-0 R662 PM_SLP_S4# 2 1 TPS5130_5V_EN# 2 100KR2 5130_SS_STBY3 DY 2 U74 1 R598 C535 SC47P50V2JN 78.47034.1F1 C536 SCD1U16V2KX-2 5130_SS_STBY3 5130_FB3 5130_INV3 C542 SC1000P25V 1 3D3V_S0 2 5130_OUT3D 43 5130_OUT3U 43 5130_LL3 43 PWM_SEL * Condition Voltage H : Auto PWM/SKIP 2.2V(Min)~ L : PWM fixed (300KHz) ~0.3V(Max) 1 5130_TRIP3 3D3V_S0 14 R523 10KR2 A U44A 1 2 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 25,44,45 VCCP_PWRGD PM_SLP_S3# 3 2 CPU_SHDN# 41 Title 7 2 2 5130_OUT3D 5130_LL3 5130_OUT3U 2 D34 BAT54-1 DCBATOUT 83.00054.L03 5130_SS_STBY2 C529 SC4700P50V2KX 2 GAP-CLOSE ZZ.CON2C.XX1 3 C534 SC4700P50V2KX 78.47224.2F1 1 R597 0R2-0 G60 1 1 2 5130_STBY_LDO TPS5130PT-U C541 SCD1U16V2KX-2 5130_5V_LDO 2N7002DW 84.27002.03F A B 5130_LH3 1 2 2 SC 13 14 15 16 15130_PG_DELAY 17 18 19 20 21 22 23 24 1 22,26,36 PM_SLP_S4# SS_STBY3 FB3 INV3 PGOUT PG_DELAY TRIP3 VIN_SENSE3 LH3 OUT3_U LL3 OUT3_D OUTGND3 CH521S-30 43 TSLCX08-U TPS5130 (3D3V/5V/1D8V) Size A3 HW Thermal Throttling Document Number Rev -1 Leopard2 Date: Thursday, July 07, 2005 Sheet 42 of 47 5 4 3 2 1 TI TPS5130 for 1D2V, 5V, 3D3V 1D8V_PWR (1D2V=>CH1 , 5V=>CH2 , 3D3V =>CH3) DCBATOUT 2 1D5V_S5 2 3 VOUT 2 GND 1 VIN Imax=9.3A Rdson=19.6~24mohm 5V_PWR D C262 SC2D2U10V3ZY 2 1 GAP-CLOSE-PWR G64 4 3 2 1 G S S S 2 G9131-15T73UF-GP 5V_S3 G65 1 3D3V_S5 1 GAP-CLOSE-PWR U39 C540 SC10U35V0ZY-U 1 GAP-CLOSE-PWR G58 SC 1 2 1 2 5 6 7 8 D D D D U28 AO4422 C206 SCD1U25V2ZY-U 1 GAP-CLOSE-PWR G56 1.5V_S5 (For ICH6) D 1D8V_S3 G57 2 1D8V_PWR L39 1 2 IND-4D7UH-66-GP Imax=A DCR=mOhm 2 TC23 SE220U2VDM-7 3D3V_PWR KEMET, NTD:7.6 (Q1) ESR=25mohm Iripple=2.2A 7.3*4.3*1.9 Imax=9.3A Rdson=19.6~24mohm 5130_OUT1D 1 C 1 GAP-CLOSE-PWR 5V_S0 DY C245 SC10U10V5ZY 78.10693.411 2 2 C247 SCD1U Vo(cal.)=0.90V 1 VIN VREF VCNTL 2 9 GND GND 1 1 3 6 4 NC NC NC 8 7 5 DDR_VREF TC13 ST100U4VBM-1 GAP-CLOSE-PWR C563 SC22U10V6ZY-U DY 2 C564 SCD1U16V2KX-2 VOUT 1 GAP-CLOSE-PWR G24 2 1 1 2 R614 1KR2F 2 TC25 ST220U6D3VDM-12 Imax=9.3A Rdson=19.6~24mohm APL5331_0D9V_VREF 2 0D9V_LDO U38 1 1 SB 2 Imax=4.5A DCR=60mOhm 7*7*3.0 R610 1KR2F 1 5V Iomax=5.4A OCP>10A 0D9V_S0 Iomax=2A G25 2 1 2 G S S S 4 3 2 1 5 6 7 8 SC10U10V5ZY-L 1D8V_S3 KEMET, NTD:8.0 (Q1) ESR=25mohm Iripple=1.65A 7.3*4.3*2.8 4 3 2 1 42 5130_OUT3D C246 Imax=9.3A Rdson=19.6~24mohm 1 2 IND-4D7UH-66-GP G S S S B 2 1 2 1 2 5 6 7 8 C238 SC10U35V0ZY-U L41 D D D D U33 AO4422 1 GAP-CLOSE-PWR G63 Trace Length=1cm (500mils) Trace Width=8mils Trace Resistance>25mohm D D D D C227 SCD1U25V2ZY-U 5V_PWR 5130_OUT3U 5130_LL3 1 2 1D8V_S3 42 5130_OUT3U 42 5130_LL3 3D3V_AUX G61 GAP-CLOSE-PWR G62 DCBATOUT U32 AO4422 1 2 2 G S S S 4 3 2 1 42 5130_OUT1D 2 GAP-CLOSE-PWR AO4422 C 1 1 D D D D U26 2 GAP-CLOSE-PWR G66 Imax=300mA 1 5130_OUT1U 5130_LL1 5 6 7 8 42 5130_OUT1U 42 5130_LL1 1D8V Iomax=5A OCP>10A 5130_OUT3D APL5331KAC-TR B KEMET 100uF / 4V / B2 Size / NTD:5.615 Iripple=1.1A / ESR=70mohm SO-8-P L3# circuit DCBATOUT 1 2 C226 SC10U35V0ZY-U DCBATOUT 1 C229 SCD1U25V2ZY-U 2 D D D D 4 3 2 1 G S S S 42 5130_OUT2D 5130_OUT2D Imax=9.3A Rdson=19.6~24mohm NEC, NTD:8.75 (Q1) ESR=55mohm Iripple=1.65A 7.3*4.3*2.8 HTH GND LTH VCC 5 RESET#/RESET 4 D12 L3# at 8.13V 1 RSMRST# 21,25,36 G680LT1 1 BAT54-1 R226 6K04R2F HTH 2 3 2 1 2 3 42 BL3# DY A 2 TC24 ST220U6D3VDM-6 HTH Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 Imax=4.5A DCR=60mOhm 7*7*3.0 2 U30 AO4422 3D3V Iomax=4A OCP>8A 1 L40 1 2 IND-6D8UH-31-GP D D D D A 3D3V_PWR R212 174KR2F Title TPS5130 (3D3V/5V/1D8V/0D9V) 2 G S S S 4 3 2 1 5130_OUT2U 5130_LL2 5 6 7 8 42 5130_OUT2U 42 5130_LL2 R227 1MR2F Imax=9.3A Rdson=19.6~24mohm C224 SCD1U10V2MX-1 U29 1 U31 AO4422 2 5 6 7 8 1 5V_AUX Size A3 Document Number Date: Monday, July 11, 2005 Rev -1 Leopard2 Sheet 43 of 47 Iocp=7.8 * 1.7 = 13.3A Rds,on=5.5*1.375=7.563m ohm Vcs1=Iocp*Rds,on=100mV VILIM=Vcs1/0.1=1V Iocp=4.3 * 1.7 = 7.3A Rds,on=20*1.375=27.5m ohm Vcs2=Iocp*Rds,on=201mV VILIM2=Vcs2/0.1=2.01V DCBATOUT 1 1 5V_S3 2 C508 SC1U25V5ZY 1 1 2 C513 SC1U10V3KX 2 2 C514 SCD01U50V3KX C507 SCD01U50V3KX 5V_S3 3 Close to pin4 2 Close to pin21 D10 1 1 2 R573 10R3 SB MAX8743_BST2 25 BST1 MAX8743_DH1 MAX8743_LX1 MAX8743_DL1 26 27 24 DH1 LX1 DL1 DH2 LX2 DL2 18 17 20 28 CS1 CS2 16 1 2 G20 L16 1D5V_PWR 1 2 IND-6D8UH-31-GP 2 U70 G21 2 14 ON2 12 5 10 TON REF PGOOD 7 8 SC R607 30K1R2F R658 100KR2 DY Rds-on,max = 20m ohm 7A@70 degree C 2 1 MAX8743_ON# R661 1 2 R179 10KR2F-U MAX8743_FB2 5V_S3 R563 DUMMY-R2 1 3D3V_S0 1 R172 2 100KR2 2 SC 5V_AUX 100KR2F U82 DUMMY-R2 2 1 100KR2 VCCP_PWRGD R564 DUMMY-R2 2 2 3 4 2 5 1 6 2 2 1 1 R657 R565 1 1 3D3V_S5 MAX8743_VREF MAX8743EEI 1 2 0703 -1 SKIP# OVP R178 5K1R2F 2 1 6 R162 10KR2F-U IRF7807Z 2 FB2 ON1 1 GAP-CLOSE-PWR 1 FB1 2 2 TC11 SE220U2VDM-7 DY C516 SC1U10V3KX 15 11 1 GAP-CLOSE-PWR 4 3 2 1 1 0R2-0 1 0R2-0 1 GAP-CLOSE-PWR MAX8743_DH2 MAX8743_LX2 MAX8743_DL2 2 1 2 3 4 MAX8743_VREF MAX8743_ON# 2 R170 2 R171 OUT2 MAX8743_FB1 MAX8743_VREF 2 5 6 7 8 D D D D 1 AO4422 4 3 2 1 OUT1 GND SE220U2VDM-6 2 1 1D05V ON/OFF control 2 1 G22 MAX8743_BST2R S S S G 1 19 1 Rds-on,max = 5.5m ohm 10A@70 degree C AO4422 G S S S R164 8K06R2F BST2 G S S S MAX8743_BST1R TC8 GAP-CLOSE-PWR 1 ILIM1 2 3 C197 SCD1U25V3KX 5 6 7 8 8 7 6 5 1 U66 13 1D5V_S0 U68 D D D D 1 GAP-CLOSE-PWR G17 2 L15 2 IND-4D7UH-16-GP D D D D 1 GAP-CLOSE-PWR G18 2 1 ILIM2 23 1D8V_VRAM_PWR 2 2 2 UVP 1 2 3 4 G16 1 1D5V / 4D3A R167 0R3-U 21 4 9 G S S S 0703 -1 2 2 C181 SCD1U25V3KX VDD V+ 2 AO4422 U69 22 R572 100KR2F 1 VRAM_VDDQ R163 86K6R2F 2 0R3-U VCC D D D D 1 R161 C506 SC10U25VMX-2-U SC 1 2 C515 SC1U10V3KX 1 8 7 6 5 U67 1D8V / 5.5A C512 SCD1U25V3KX 2 1 R571 402KR2F 1 1 R169 100KR2F 2 1 2 1 2 C491 SC10U25VMX-2-U MAX8743_BST1 C505 SCD1U25V3KX 1 BAW56-1 25,42,45 DY Ton Setting Side 1 Frequency(kHz) VCC 235 Float 345 VREF 485 AGND 620 Side 2 Frequency(kHz) 170 255 355 460 DY DY C618 SCD1U10V2MX-1 1 2 R656 10KR2 1 2 PM_SLP_S3# 22,26,33,36,42,45,46 R667 0R2-0 MAX8743_ON# 2N7002DW 44,45 DY Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title MAX8743 (1D8V_S0/1D5V_S0) Size A3 Document Number Date: Monday, July 11, 2005 Rev -1 Leopard2 Sheet 44 of 47 Iocp=7.8 * 1.7 = 13.3A Rds,on=5.5*1.375=7.563m ohm Vcs1=Iocp*Rds,on=100mV VILIM=Vcs1/0.1=1V Iocp=4.3 * 1.7 = 7.3A Rds,on=20*1.375=27.5m ohm Vcs2=Iocp*Rds,on=201mV VILIM2=Vcs2/0.1=2.01V DCBATOUT 1 1 5V_S3 2 C91 SC1U25V5ZY 1 1 2 C61 SC1U10V3KX 2 2 C60 SCD01U50V3KX C92 SCD01U50V3KX 5V_S3 3 Close to pin4 2 Close to pin21 D4 SB 1 1 2 R102 10R3 MAX8743A_BST2 BST1 MAX8743A_DH1 MAX8743A_LX1 MAX8743A_DL1 26 27 24 DH1 LX1 DL1 DH2 LX2 DL2 18 17 20 28 CS1 CS2 16 1 1 12 TON REF PGOOD 7 OVP 8 SKIP# C93 SC1U10V3KX M24/M26 POWER PLAY (VGA_PWRCNTL) high (3.3V) = set lower core voltage (VDDC = 1.0V) low (0V) = set higher core voltage (VDDC = 1.2V) 1 1 2 2 2 5 6 7 8 D D D D 1 GAP-CLOSE-PWR R63 510R2F R93 10KR2F-U MAX8743A_FB2 2 MAX8743A_VREF Rds-on,max = 20m ohm 7A@70 degree C 3D3V_S0 R90 1 1 2 R452 1 0R2-0 MAX8743_ON# 44 2 R489 2 100KR2 2 100KR2F 5V_S3 SB 2 R450 0R2-0 VCCP_PWRGD 25,42,44 1 R486 2 MAX8743A_VREF 1 1 DUMMY-R2 R485 DUMMY-R2 2 High(3.3V)=>Vo=1.0V Low(0V)=>Vo=1.2V TC18 IRF7807Z MAX8743EEI 1 3 2 2 Vo=Vref*(1+R1/R2) =1.0V*(1+2K/10K) =1.2V Vo=1.0V*(1+0/10K) =1*1=1.0V R451 10KR2 G42 2 1 ON2 R487 30K1R2F VGA_PWRCNTL 13 2 S U10 2 FB2 ON1 1 GAP-CLOSE-PWR 2 1 1 2 SC1000P25V D 2 1 1 0R2-0 1D2V_PWR 0706 -1 G43 L24 1D05V_PWR 1 2 IND-3D3UH-44-GP SE220U2VDM-7 MAX8743_ON# 2 R652 2 FB1 14 1 GAP-CLOSE-PWR 1 5 10 15 R655 3K3R2 Q39 2N7002 1 G 1 4 3 2 1 11 1D2V ON/OFF control OUT2 OUT1 MAX8743A_FB1 C71 2 MAX8743A_DH2 MAX8743A_LX2 MAX8743A_DL2 5 6 7 8 2 GAP-CLOSE-PWR R62 49K9R2F G41 AO4422 2 IRF7807Z 1 1 DY MAX8743A_BST2R 4 3 2 1 8 7 6 5 S S S G 1 2 3 4 IRF7807Z 1 S 2 S 3 S 4 G 2 19 G S S S 25 6 1 BST2 C72 SCD1U25V3KX 1 2 1 MAX8743A_BST1R MAX8743A_VREF GAP-CLOSE-PWR G48 13 23 2 ILIM2 2 ILIM1 Rds-on,max = 5.5m ohm 10A@70 degree C 2 GAP-CLOSE-PWR G47 21 4 3 GND R61 10KR2F-U 1 SE220U2VDM-6 1 G49 2 TC20 2 SE220U2VDM-6 2 GAP-CLOSE-PWR SCD1U25V3KX C70 1 U8 22 UVP 1D05V_S0 U11 S S S G 2 1 GAP-CLOSE-PWR G52 TC5 1 SB 1 D D D D U56 1 R64 0R3-U D D D D 2 D D D D GAP-CLOSE-PWR G51 8 7 6 5 L23 1 2 IND-D82UH-3-GP 1D2V_PWR 1 2 2 9 1 2 3 4 G50 2 VDD V+ 2 C58 SCD1U25V3KX G S S S AO4422 U17 C337 SC10U25VMX-2-U SC10U25VMX-2-U 1D05V / 6.8A R92 100KR2F 1 1D2V_VGA_S0 R88 100KR2F 2 0R3-U VCC D D D D 1 R49 SC 2 C59 SC1U10V3KX 1 2 8 7 6 5 U9 1D2V / 13A C46 2 1 SC C45 SCD1U25V3KX 1 1 1 R91 220KR2F 1 2 R89 243KR2F 2 1 1 C47 SCD1U25V3KX C48 SC10U25VMX-2-U 2 2 C49 SC10U25VMX-2-U MAX8743A_BST1 1 BAW56-1 Ton Setting Side 1 Frequency(kHz) VCC 235 Float 345 VREF 485 AGND 620 Side 2 Frequency(kHz) 170 255 355 460 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title MAX8743 (1D2V_VGA_S0/1D05V) Size A3 Document Number Rev -1 Leopard2 Date: Thursday, July 07, 2005 Sheet 45 of 47 A B C FOR GMCH Power D E 1D8V_S3 GAP-CLOSE-PWR 1 C195 SCD1U16V3KX R177 220R3F IN+ VSS ING1214 2 VDD 5 OUT 4 DDR_VREF_S3 4 DY 2 1 2 G39 2 U25 1 2 3 1D05V_S0 GAP-CLOSE-PWR G44 1 2 GAP-CLOSE-PWR GAP-CLOSE-PWR 1 R204 VREFOUT = 0.9V C221 SCD1U16V 2 VCCP_GMCH_S0 DDR_VREF_S3 need 10 mil and must neat NB and DIMM 2 C222 SCD1U16V 1 1 1D05V_S0 R182 220R3F 2 G38 2 GAP-CLOSE-PWR 4 C196 SCD1U16V3KX 1 G45 1 CORE_GMCH_S0 2 GAP-CLOSE-PWR 2 1 1 1 G40 2 1 5V_S3 G46 1 2 0R3-U FOR DDR2 Power 1 1D5V_S0 1D2V_VDDR_S0 / 3A R160 0R5J-1 3D3V_S5 1 1 3 C194 R159 249R2F SCD1U10V2MX-1 2 VOUT 8 7 5 NC NC NC VIN VREF VCNTL 1 3 6 U35 GND GND 2 9 APL533_VREF2 1V:R159=470R 1.2V:R159=250R 2 3 4 25 S5PWR_ENABLE GND NC ON/OFF# IN 5 OUT 1 AAT4250-U 2 2 Run Power 5V_S0 SCD1U16V 5V_S3 5V_AUX U36 PWR_S0_CTL 2 OUT 1 AAT4250-U C182 DY 5V_S5 2 R321 1 0R3-U 1 5 SCD1U16V C183 SCD1U16V Q40 1D8V_S3 SI3456DV-U1 6 4 5 2 1 G S 3 2 IN 2 1 SCD22U50V5KX 1 2 3 2 D GND NC ON/OFF# D 3 VRAM_VDDQ S D DY S 2 2 S5PWR_ENABLE 8 7 6 5 0703 -1 Q13 2N7002 1 G PM_SLP_S3# 2 3 4 AO4422 QB1 2N7002 1 G 3D3V_AUX 1 1 1 R224 1KR2 5V_S3 3D3V_S0 1 2 3 4 2 U22 U76 1 RB1 100R2 D14 MMGZ5242B G S S S 2 330KR2 0703 -1 AO4422 D D D D G 1 R225 2 C546 TP0610K-U 5V_S5 8 7 6 5 2 3 Q14 G S S S 2 D 2 10KR2 S 1 R223 1 2 3 4 D D D D DCBATOUT 22,26,33,36,42,44,45 1 0R3-U C248 SCD1U16V 2 C249 2 APL5331KAC-TR 3D3V_S5 2 R241 1 R158 1KR2F 1 C179 SC1U6D3V2KX 2 3D3V_S3 1 4 1 1 2 TC10 ST220U4VDM-1 3D3V_AUX 1D5V_S0 2 2 2 U23 5V_S0 DY SC10U10V5ZY-L 1D2V_VDDR_S0 3 1 2 Suspend Power C180 SC1U6D3V2KX 1 C187 DY 5V_S3 1 1 C237 SCD1U16V 2 1 3D3V_S3 C570 SCD1U16V 2 R203 100KR2 1 DY 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title PWRPLANE&RESETLOGIC Size A3 Document Number Date: Thursday, July 07, 2005 A B C D Rev -1 Leopard2 Sheet E 46 of 47 A B C D E AD+ 1 1 1 1 1 1 1 SCD1U25V3KX 2 SCD1U25V3KX 2 SCD1U25V3KX 2 SCD1U25V3KX 2 SCD1U25V3KX 2 1 1 2 SCD1U25V3KX 2 SCD1U25V3KX 2 EC123 1 EC9 1 1 1 EC51 EC107 EC31 2 1 EC39 SCD1U16V 2 SCD1U16V 2 SCD1U16V 2 SCD1U16V 2 SCD1U16V 2 SCD1U16V 2 SCD1U16V 2 3D3V_S0 EC126 SCD1U16V 2 EC127 3D3V_LAN_S5 1 EC122 1 EC34 1 EC35 SCD1U16V 2 SCD1U16V 2 SCD1U16V 2 SCD1U16V 2 SCD1U16V 2 SCD1U16V 2 SCD1U16V 1 EC38 1 EC48 SCD1U16V 2 SCD1U16V 2 2 SCD1U16V 2 1 1 1 EC172 EC176 EC177 SCD1U16V SCD1U16V SCD1U16V 2 EC178 SCD1U16V 2 1 EC175 SCD1U16V SC 2 1 EC174 SCD1U16V 2 1 EC173 SCD1U16V 2 1 2 EC108 SCD1U16V AUD_AGND 2 1 TSAHCT86 7 7 AUD_AGND 3D3V_S0 3D3V_S0 3D3V_S0 AUD_AGND DY DY DY DY DY DY 1 1 2 DY SCD1U16V EC148 SCD1U16V SCD1U16V 2 DY EC25 2 1 1 SCD1U16V SCD1U16V 2 1 2 SCD1U16V 2 1 SCD1U16V SCD1U16V 2 1 2 1 DY EC76 DY 1 2 EC56 SCD1U16V DY DY DY DY 1 1 EC55 SCD1U16V 2 EC45 SCD1U16V SCD1U16V 2 2 EC63 5V_S3 1 1 EC41 SCD1U16V EC78 SCD1U16V 2 2 1 1 1 1 2 1 DY DY 2 EC53 SCD1U16V DY DY DY DY DY DY DY 1 SCD1U16V EC75 2 1 EC81 SCD1U16V 2 DY SCD1U16V EC54 EC77 SCD1U16V 2 1 5V_S0 1 EC46 SCD1U16V 2 EC144 SCD1U16V 2 EC66 SCD1U16V 1 1 5V_S0 2 EC58 SCD1U16V 2 2 EC73 SCD1U16V 1 1 1 DY 2 EC69 SCD1U16V 2 SCD1U16V SCD1U16V 2 SCD1U16V 2 SCD1U25V3KX 2 2 DY 1 SCD1U16V EC136 2 1 2 EC141 SCD1U16V 1 2 EC128 SCD1U16V 1 EC152 2 EC149 SCD1U16V EC60 1 1 2 EC50 SCD1U16V 1 2 SCD1U16V EC151 SCD1U16V 1 EC163 2 1 2 EC37 SCD1U16V 1 2 1 EC23 SCD1U16V 34.40E37.001 EC129 SCD1U16V 34.40E37.001 H7 HOLE SCD1U16V H22 2 H25 HOLE 2 H9 EC146 1D5V_S0 1 1 H26 HOLE H27 HOLE EC138 H1 HOLE EC83 1 1 H3 HOLE 1 1 H2 HOLE 1 1 1 1 EC22 EC120 EC121 EC125 H6 HOLE 2 H24 HOLE DY 5V_S0 SCD1U16V 1 H20 HOLE SCD1U16V 2 2 DY EC52 SCD1U16V EC57 DY 1 1 H4 HOLE DY 2 1 H11 HOLE EC80 SCD1U16V 1 H10 HOLE DY EC44 CORE_GMCH_S0 1 1 H16 HOLE DY 1 1 H5 HOLE 1 1 DY EC72 SCD1U16V H13 HOLE DY EC133 5V_S3 SCD1U16V H17 HOLE SCD1U16V 1 1 1 2 DY 1 H19 HOLE SCD1U16V H15 HOLE 34.40E37.001 SCD1U16V H12 EC65 1 H14 HOLE 1 H8 HOLE 1 H18 HOLE 2 2 H21 HOLE 34.40E37.001 1 H23 EC150 SCD1U16V EC74 2 2 1 K6 GNDPAD 1 1 1 1 K7 GNDPAD EC145 2 DY EC71 SCD1U16V 2 2 1 1 1 2 DY EC79 5V_S3 K5 GNDPAD DY 2 DY DY SCD1U16V DY EC59 SCD1U16V K4 GNDPAD EC70 SCD1U16V K3 GNDPAD EC82 3D3V_S0 SCD1U16V K1 GNDPAD SCD1U16V 1 1 1 1 1 1 K2 GNDPAD 2 SPRING-4SPRING-4 EC115 SCD1U16V SPRING-4 2 SPRING-4 EC40 SCD1U16V SPRING-4 1 SPRING-4 2 SPR15 1 SPR14 1 SPR16 1 SPR12 1 1 1 EC62 SPR13 EC143 DY 5V_S3 SPR11 1 1 1 EC154 1 AUD_AGND EC140 2 1 1 1 1 1 1 1 1 1 1 SPRING-18-U SPRING-18-U SPRING-18-U SPRING-18-U SPRING-18-U SPRING-18-U SPRING-18-U SPRING-18-U SPRING-18-U SPRING-9 EC67 2 EC61 SCD1U16V 2 1 EC49 EC156 SCD1U16V SCD1U16V EC142 SCD1U16V 2 SPR3 SCD1U16V SPR7 2 SPR1 SCD1U16V SPR10 2 SPR4 SCD1U16V SPR6 2 SPR8 2 SPR2 1 1 SPR5 2 SPR9 1 3 1 3 1 Wistron Corporation 1 1 1 1 1 1 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 1 1 EC113 13 TSAHCT32 SCD1U25V3KX 2 2 1 1 1 SCD1U16V 2 SCD1U25V3KX 2 SCD1U25V3KX EC36 1 EC124 1 EC43 SC 1 1 2 SCD1U16V 2 EC26 1D8V_S3 1D2V_VGA_S0 11 13 SCD1U25V3KX 2 1 1 EC91 SCD1U16V 2 2 1D05V_S0 EC17 SCD1U16V EC24 SCD1U16V EC21 SCD1U16V 2 1 1 1 EC8 SCD1U16V EC3 2 SCD1U16V 2 SCD1U16V 1D05V_S0 1 1 1 2 2 SCD1U16V 2 1D05V_S0 EC93 EC68 EC112 EC86 EC90 EC64 EC11 1 1D05V_S0 12 11 EC84 SCD1U25V3KX 2 1 EC12 EC47 EC134 EC5 2 12 EC135 SCD1U16V 2 U49D 1 1 1 U78D 14 14 5V_S0 EC87 SCD1U16V EC15 4 BT+ 5V_S0 5V_AUDIO_S0 EC10 AUD_AGND 1 AUD_AGND EC7 VCCP_GMCH_S0 AUD_AGND AUD_AGND EC89 SCD1U25V3KX EC4 4 AUD_AGND 1 1 1 EC32 SC1000P50V 2 2 2 EC18 SCD1U25V3KX EC16 SCD1U25V3KX EC88 1 1 1 1 EC33 SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX 2 EC130 EC102 2 1 SCD1U25V3KX 2 EC114 SCD1U25V3KX 1 SCD1U25V3KX 2 EC13 DCBATOUT 1 1 2 2 SCD1U25V3KX 2 1 1 EC92 SCD1U25V3KX DY 2 SCD1U25V3KX 1 EC85 2 EC164 2 SCD1U16V 2 DY EC6 EC165 SCD1U25V3KX 1 DY DY EC153 SCD1U25V3KX 1 1 2 SCD1U16V 2 DY DY EC162 SCD1U16V 1 EC139 EC147 SCD1U16V 2 DY DY SCD1U16V 2 1 1 EC42 EC132 SCD1U16V 2 SCD1U16V 2 1 1 SCD1U16V 2 1 EC137 EC157 DCBATOUT 1 DCBATOUT SC Title MISC & EMI Size A3 Document Number Date: Thursday, July 07, 2005 A B C D Rev -1 Leopard2 Sheet E 47 of 47 www.s-manuals.com
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No XMP Toolkit : Adobe XMP Core 4.0-c316 44.253921, Sun Oct 01 2006 17:14:39 Producer : Acrobat Distiller 5.0 (Windows) Create Date : 2005:07:12 03:13:48Z Modify Date : 2014:04:12 17:16:07+03:00 Metadata Date : 2014:04:12 17:16:07+03:00 Format : application/pdf Title : Wistron Leopard2 - Schematics. www.s-manuals.com. Creator : Subject : Wistron Leopard2 - Schematics. www.s-manuals.com. Document ID : uuid:ff43cf04-19a1-4155-954e-4a4faed71bff Instance ID : uuid:75c49b3d-96b5-4e1e-91e2-c6ae1f169216 Page Count : 48 Keywords : Wistron, Leopard2, -, Schematics., www.s-manuals.com.EXIF Metadata provided by EXIF.tools