WT7525 Datasheet. Www.s Manuals.com. R0.40 Weltrend
User Manual: Datasheets WT7525, WT7525-N140, WT7525-N160, WT7525-N161, WT7525-N180, WT7525-N181, WT7525-S140, WT7525-S160, WT7525-S161, WT7525-S180, WT7525-S181.
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偉詮電子股份有限公司
Weltrend Semiconductor, Inc.
`
WT7525
PC POWER SUPPLY SUPERVISOR
Data Sheet
REV. 0.40 Preliminary release
February 21, 2005
The information in this document is subject to change without notice.
Weltrend Semiconductor, Inc. All Rights Reserved.
新竹市科學工業園區工業東九路24號2樓
2F, No. 24, Industry E. 9th RD., Science-Based Industrial Park, Hsin-Chu, Taiwan
TEL:886-3-5780241 FAX:886-3-5794278.5770419
Email:support@weltrend.com.tw
WT7525 Preliminary release
Rev. 0.40
GENERAL DESCRIPTION
The WT7525 provides protection circuits, power good output (PGO), fault protection latch (FPOB),
and a protection detector function (PSONB) control. It can minimize external components of switching
power supply systems in personal computer.
The Over / Under Voltage Detector (OVD / UVD) monitors V33, V5, V12A, V12B and V12C input
voltage level. The Over Current Detector (OCD) monitor IS33, IS5, IS12A, IS12B and IS12C input
current sense. When OVD or UVD or OCD detect the fault voltage level, the FPOB is latched HIGH and
PGO go low. The latch can be reset by PSONB go HIGH. There is 3.5 ms delay time for PSONB turn
off FPOB.
When OVD and UVD and OCD detect the right voltage level, the power good output (PGO) will be
issue.
FEATURES
• The Over/Under Voltage Detector (OVD / UVD) monitors V33, V5, V12A, V12B and V12C input
voltage.
• The Over Current Detector (OCD) monitors IS33, IS5, IS12A, IS12B and IS12C input current sense.
• Both of the power good output (PGO) and fault protection latch (FPOB) are Open Drain Output.
• 75 / 300 ms time delay for UVD.
• 300 ms time delay for PGO.
• 38 ms for PSONB input signal De–bounce.
• 73 us for PGI/OVD/UVD internal signal De–glitches.
• 1.2 ms for OCD internal signal De–glitches.
• 3.5 ms time delay for PSONB turn-off FPOB.
Weltrend Semiconductor, Inc.
Page 2
WT7525 Preliminary release
Rev. 0.40
PIN ASSIGNMENT AND PACKAGE TYPE
WT7525-140
WT7525-160
WT7525-161
PGI
1
14
PGO
PGI
1
16
PGO
PGI
1
16
PGO
GND
2
13
VCC
GND
2
15
VCC
GND
2
15
VCC
FPOB
3
12
V5
FPOB
3
14
V5
FPOB
3
14
V5
PSONB
4
11
V33
PSONB
4
13
V33
PSONB
4
13
V33
I12AB
5
10
V12A
I12A
5
12
V12A
I12A
5
12
NC
RI
6
9
I33
RI
6
11
I33
RI
6
11
V12A
V12B
7
8
I5
NC
7
10
I5
I5
7
10
I33
V12B
8
9
I12B
V12B
8
9
I12B
WT7525-180
1
PGO
PGI
1
18
PGO
17
VCC
GND
2
17
VCC
3
16
V5
FPOB
3
16
V5
PSONB
4
15
V33
PSONB
4
15
V33
I12A
5
14
V12A
I12A
5
14
NC
RI
6
13
I33
RI
6
13
V12A
NC
7
12
I5
I5
7
12
I33
V12B
8
11
I12B
V12B
8
11
I12B
I12C
V12C
9
10
I12C
PGI
GND
2
FPOB
V12C
9
ORDERING INFORMATION
PACKAGE
14–Pin Plastic DIP
WT7525–N140
Lead–Free（Pb）
WT7525–N140 Pb
PACKAGE
Lead–Free（Pb）
16–Pin Plastic DIP
WT7525–N160
WT7525–N161
WT7525–N160 Pb
WT7525–N161 Pb
18
WT7525-181
10
14–Pin Plastic SOP
WT7525–S140
WT7525–S140 Pb
16–Pin Plastic SOP
WT7525–S160
WT7525–S161
WT7525–S160 Pb
WT7525–S161 Pb
PACKAGE
18–Pin Plastic DIP
18–Pin Plastic SOP
WT7525–N180
WT7525–S180
WT7525–N181
WT7525–S181
WT7525–N180 Pb
WT7525–S180 Pb
Lead–Free（Pb）
WT7525–N181 Pb
WT7525–S181 Pb
※ The Top-Side Marking would be added a dot（●）in the right side for lead-free package.
Weltrend Semiconductor, Inc.
Page 3
WT7525 Preliminary release
Rev. 0.40
PIN DESCRIPTION
Pin Name
TYPE
PGI
I
GND
P
FPOB
O
PSONB
I
I12A
I
I12AB
I
RI
I
V12B
I
V12C
I
I12C
I
I12B
I
I5
I
I33
I
V12A
I
V33
I
V5
I
VCC
I
PGO
O
Description
Power good input signal pin
Ground
Fault protection output pin, open drain output
On/Off switch input
12VA over current protection sense input
12VA / 12VB over current protection sense input (only for 140)
Current sense adjust input
12VB over/under voltage input pin
12VC over/under voltage input pin
12VC over current protection sense input
12VB over current protection sense input
5V over current protection sense input
3.3V over current protection sense input
12VA over/under voltage input pin
3.3V over/under voltage input pin
5V over/under voltage input pin
Power supply
Power good output signal pin, open drain output
Weltrend Semiconductor, Inc.
Page 4
WT7525 Preliminary release
Rev. 0.40
BLOCK DIAGRAM
WT7525C-140 BLOCK DIAGRAM
WT7525-140
VCC
Power On Reset
PWR
PWR
VCCI
38ms
debounce
PSONB
clr
3.5ms
delay
clr
75ms / 300ms
delay
1.2V ~ 1.8V
VREF = 1.2V
V33
Bandgap
Reference
VREF = 1.2V
Internal
Power
VCCI = 3.6V
- UN
+
- OV
+
- UN
V5
+
PWR
- OV
+
OSC
- UN
V12A
CLK
+
- OV
+
- UN
V12B
clr
73us
debounce
+
- OV
+
R
clr
1.2ms
debounce
PGI
+
VREF = 1.2V
-
clr
73us
debounce
UN
S
FPOB
Q
PGO
clr
300ms
delay
V12A
I33
-
V12A
+
IREF * 8
V12A
VREF = 1.2V
V12A
I5
-
-
IREF=VREF / RI
RI
+
IREF * 8
V12A
I12AB
+
-
+
IREF * 8
V12A
-
+
Weltrend Semiconductor, Inc.
Page 5
WT7525 Preliminary release
Rev. 0.40
WT7525-160 / 161
WT7525C-160 BLOCK DIAGRAM
VCC
Power On Reset
PWR
PWR
VCCI
38ms
debounce
PSONB
clr
3.5ms
delay
clr
75ms / 300ms
delay
1.2V ~ 1.8V
VREF = 1.2V
V33
Bandgap
Reference
VREF = 1.2V
Internal
Power
VCCI = 3.6V
- UN
+
- OV
+
- UN
V5
+
PWR
- OV
+
OSC
- UN
V12A
CLK
+
- OV
+
- UN
V12B
clr
73us
debounce
+
- OV
+
R
clr
1.2ms
debounce
PGI
clr
73us
debounce
+
VREF = 1.2V
- UN
S
FPOB
Q
PGO
clr
300ms
delay
V12A
I33
-
V12A
+
IREF * 8
V12A
VREF = 1.2V
V12A
I5
-
V12A
-
+
IREF * 8
V12A
I12B
-
IREF=VREF / RI
RI
+
IREF * 8
I12A
+
-
+
IREF * 8
Weltrend Semiconductor, Inc.
Page 6
WT7525 Preliminary release
Rev. 0.40
WT7525-180 / 181
WT7525C-180 BLOCK DIAGRAM
VCC
Power On Reset
PWR
PWR
VCCI
38ms
debounce
PSONB
clr
3.5ms
delay
clr
75ms / 300ms
delay
1.2V ~ 1.8V
VREF = 1.2V
V33
Bandgap
Reference
VREF = 1.2V
Internal
Power
VCCI = 3.6V
- UN
+
- OV
+
- UN
V5
+
PWR
- OV
+
OSC
- UN
V12A
CLK
+
- OV
+
- UN
V12B
+
clr
73us
debounce
- OV
+
- UN
V12C
+
R
clr
1.2ms
debounce
- OV
+
PGI
+
VREF = 1.2V
-
clr
73us
debounce
UN
S
FPOB
Q
PGO
clr
300ms
delay
V12A
I33
-
+
V12A
IREF * 8
V12A
VREF = 1.2V
V12A
I5
-
V12A
-
+
IREF * 8
V12A
I12B
-
+
IREF * 8
V12A
I12C
-
IREF=VREF / RI
RI
+
IREF * 8
I12A
+
-
+
IREF * 8
Weltrend Semiconductor, Inc.
Page 7
WT7525 Preliminary release
Rev. 0.40
ABSOLUTE MAXIMUM RATINGS
Parameter
Min.
Max.
Supply voltage, VCC, V12A
–0.3
16
VCC + 0.3（Max. 7V）
PGI, PSONB
–0.3
V12A + 0.3（Max. 7V）
V5,
V33,
I5,
I33
–0.3
Input voltage
V12B, I12A, I12B, I12AB
V12A + 0.3（Max. 16V）
–0.3
V12C, I12C
PGO
–0.3
7
Output voltage
FPOB
–0.3
16
Operating temperature
-40
125
Storage temperature
-55
150
*Note: Stresses above those listed may cause permanent damage to the devices
Unit
V
V
V
V
V
V
℃
℃
RECOMMENDED OPERATING CONDITIONS
Parameter
Conditions
Supply voltage, VCC
Input voltage
Output voltage
Output sink current
PGI, PSONB, V5, V33
V12A, V12B, V12C
PGO
FPOB
FPOB
PGO
Min.
4
Typ.
12
0.3V
0.3V
Supply voltage rising time
Output current for RI
RI
1
10
Max.
15
7
15
7
15
10
10
65
Unit
V
V
V
V
V
mA
mA
ms
uA
ELECTRICAL CHARACTERISTICS, at Ta=25°C and VCC=5V.
Over Voltage Detection
Parameter
Condition
V33
Over voltage threshold
V5
V12ABC
ILEAKAGE Leakage current (FPOB)
VOL Low level output voltage (FPOB)
Min.
3.7
5.7
13.3
V(FPOB) = 5V
Isink =10mA
Typ.
3.9
6.1
13.8
5
Max.
4.1
6.2
14.3
0.3
Unit
V
V
V
uA
V
PGI and PGO
Parameter
Under voltage threshold
Condition
V33
V5
V12ABC
Input threshold voltage(PGI)
ILEAKAGE Leakage current(PGO)
VOL
Low level output voltage(PGO)
Offset Voltage of OCP comparators
Min.
2.55
4.1
9.5
1.16
PGO = 5V
Isink =10mA
Typ.
2.69
4.3
10
1.20
5
Max.
2.83
4.47
10.5
1.24
0.3
6
–6
Unit
V
V
V
V
uA
V
mV
PSONB
Parameter
Input pull-up current
High-level input voltage
Low-level input voltage
Condition
PSONB= 0V
Min.
Typ.
150
Max.
1.8
1.2
Weltrend Semiconductor, Inc.
Page 8
Unit
uA
V
V
WT7525 Preliminary release
Rev. 0.40
TOTAL DEVICE
Parameter
Icc Supply current
Vcc start-up voltage
Vcc stop voltage after start-up
Condition
PDON _N= 5V
Min.
Typ.
Max.
1
3.6
2.0
SWITCHING CHARACTERISTICS, Vcc=5V
Parameter
Condition
Min.
Typ.
Max.
tdb1
De-bounce time (PSONB)
24
38
52
tdelay1 Delay time (PGI to PGO)
200
300
400
tdb2
De-bounce time (PSONB)
24
38
52
tg1
De-glitch time for PGI
47
73
100
tg2
De-glitch time for OVD / UVD
47
73
100
tg3
De-glitch time for OCD
0.8
1.2
1.5
tdelay2 PSONB to FPOB delay time
tdb2+2.0 tdb2+3.5 tdb2+5.0
tdelay3 Internal UVD/OCD delay time
after FPOB go low &
49
75
100
PGI > 1.2V
300
400
after FPOB go low & 200
PGI < 1.2V
APPLICATION CIRCUIT
+5V
+5VSB
1K
PGI
+5VSB
10K
PGI
PGO
GND
VCC
FPOB
R4=100
PGO
+5VSB
VS
R5=300
PSONB
PSONB
V33
+3.3V
0.01uF
I12AB
V12A
22uF
30K, 1%
R2, 1%
RI
I33
V12B
I5
R3, 1%
R1, 1%
22uF
22uF
+12VB
+5V
22uF
+12VA
NOTE1：The series resistor R5 at PSONB can not be omitted. （R0 = 300Ω is suggested）
NOTE2：The series resistor R4 = 100Ω at PGO is suggested.
Weltrend Semiconductor, Inc.
Page 9
Unit
mA
V
V
Unit
mS
mS
mS
uS
uS
mS
mS
mS
mS
WT7525 Preliminary release
Rev. 0.40
APPLICATION NOTE
When the current cross inductor raised, inductor voltage raised.
And when inductor voltage exceeded resistor voltage, the OCP active.
We can setup OCP point by the following equation
Let VR = VL
R * IR = RL * IL
∵ IR = 8 * IREF
R * (8 * VREF / RI) = RL * IL
R = (RL * IL) / (8 * VREF / RI) ––––– (1)
And the capacitor C is used to avoide power on fail or dynamic load fail. We suggest C > 1uF.
EX：How to select the resistor of R? Assume RI=30KΩ, RL=5mΩ, OCP IL=20A。
Sol：R
= ( IL * RL ) / ( 8 * IREF )
= ( 20A * 5mΩ) / { 8 * ( 1.2V / 30KΩ)}
= 312.5Ω
Weltrend Semiconductor, Inc.
Page 10
WT7525 Preliminary release
Rev. 0.40
APPLICATION TIMMING
1.) PGI (UNDER_VOLTAGE)：
PSONB
tdelay2
FPOB
tdb1
tdelay1+tg1
tdelay1+tg1
PGO
tdb2
PGI
tg1
Weltrend Semiconductor, Inc.
Page 11
WT7525 Preliminary release
Rev. 0.40
2.) V33, V5, V12 (UNDER_VOLTAGE) or IS33，IS5，IS12 (OVER_CURRENT)：
PSONB
tdelay2
FPOB
tdb1
tdelay1+tg1
PGO
tdb2
V33/V5/V12
IS33/IS5/IS12
tdelay3=75mS
PSONB
tdelay3+tg2 / tg3
FPOB
tdb1
tdelay2
tdb1
tdelay1+tg1
PGO
tdb2
PGI
V33/V5/V12
IS33/IS5/IS12
tdelay3=300mS
PSONB
tdelay3+tg2/ tg3
FPOB
tdb1
tdelay2
tdb1
PGO
tdelay1+tg1
tdb2
PGI
V33/V5/V12
IS33/IS5/IS12
Weltrend Semiconductor, Inc.
Page 12
WT7525 Preliminary release
Rev. 0.40
3.) V33, V5, V12 (OVER_VOLTAGE)：
PSONB
tdelay2
FPOB
tdb1
tdelay1+tg1
PGO
tdb2
V33/V5/V12
PSONB
tg2
FPOB
tdb1
tdelay2
tdb1
PGO
tdelay1+tg1
tdb2
V33/V5/V12
Weltrend Semiconductor, Inc.
Page 13
WT7525 Preliminary release
Rev. 0.40
MECHANICAL INFORMATION
PLASTIC DUAL–IN–LINE 14 / 16 / 18 PACKAGE
NOTE 1：All linear dimensions are in inches（millimeters）.
NOTE 2：This drawing is subject to change without notice.
NOTE 3：Falls within JEDEC MS–001
Weltrend Semiconductor, Inc.
Page 14
WT7525 Preliminary release
Rev. 0.40
PLASTIC SMALL–OUTLINE 14 / 16 PACKAGE
NOTE 1：All linear dimensions are in inches（millimeters）.
NOTE 2：This drawing is subject to change without notice.
NOTE 3：Falls within JEDEC MS–012
Weltrend Semiconductor, Inc.
Page 15
WT7525 Preliminary release
Rev. 0.40
PLASTIC SMALL–OUTLINE 18 PACKAGE
NOTE 1：All linear dimensions are in inches（millimeters）.
NOTE 2：This drawing is subject to change without notice.
NOTE 3：Falls within JEDEC MS–013 AB
NOTE 4：Body length dimensions A does not include mold flash, protrusions or gate burrs. Mold flash,
protrusions and gate burrs shall not exceed 0.006in ( 0.15mm ) per side.
NOTE 5：Body width dimensions B does not include inter–lead flash or protrusions. Inter–lead flash and
protrusions shall not exceed 0.010in ( 0.25mm ) per side.
Weltrend Semiconductor, Inc.
Page 16
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