Freescale Semiconductor Mcf5480 Users Manual MCF5485 Reference

2015-02-09

• MCF548x Reference Manual
  • Table of Contents
  • About This Book
    • General Information
    • ColdFire Documentation
    • Register Conventions
  • Chapter 1 Overview
    • 1.1 MCF548x Family Overview
    • 1.2 MCF548x Block Diagram
    • 1.3 MCF548x Family Products
    • 1.4 MCF548x Family Features
      • 1.4.1 ColdFire V4e Core Overview
      • 1.4.2 Debug Module (BDM)
      • 1.4.3 JTAG
      • 1.4.4 On-Chip Memories
        • 1.4.4.1 Caches
        • 1.4.4.2 System SRAM
      • 1.4.5 PLL and Chip Clocking Options
      • 1.4.6 Communications I/O Subsystem
        • 1.4.6.1 DMA Controller
        • 1.4.6.2 10/100 Fast Ethernet Controller (FEC)
        • 1.4.6.3 USB 2.0 Device (Universal Serial Bus)
        • 1.4.6.4 Programmable Serial Controllers (PSCs)
        • 1.4.6.5 I2C (Inter-Integrated Circuit)
        • 1.4.6.6 DMA Serial Peripheral Interface (DSPI)
        • 1.4.6.7 Controller Area Network (CAN)
      • 1.4.7 DDR SDRAM Memory Controller
      • 1.4.8 Peripheral Component Interconnect (PCI)
      • 1.4.9 Flexible Local Bus (FlexBus)
      • 1.4.10 Security Encryption Controller (SEC)
      • 1.4.11 System Integration Unit (SIU)
        • 1.4.11.1 Timers
        • 1.4.11.2 Interrupt Controller
        • 1.4.11.3 General Purpose I/O
  • Chapter 2 Signal Descriptions
    • 2.1 Introduction
      • 2.1.1 Block Diagram
    • 2.2 MCF548x External Signals
      • 2.2.1 FlexBus Signals
        • 2.2.1.1 Address/Data Bus (AD[31:0])
        • 2.2.1.2 Chip Select (FBCS[5:0])
        • 2.2.1.3 Address Latch Enable (ALE)
        • 2.2.1.4 Read/Write (R/W)
        • 2.2.1.5 Transfer Burst (TBST)
        • 2.2.1.6 Transfer Size (TSIZ[1:0])
        • 2.2.1.7 Byte Selects (BE/BWE[3:0])
        • 2.2.1.8 Output Enable (OE)
        • 2.2.1.9 Transfer Acknowledge (TA)
      • 2.2.2 SDRAM Controller Signals
        • 2.2.2.1 SDRAM Data Bus (SDDATA[31:0])
        • 2.2.2.2 SDRAM Address Bus (SDADDR[12:0])
        • 2.2.2.3 SDRAM Bank Addresses (SDBA[1:0])
        • 2.2.2.4 SDRAM Row Address Strobe (RAS)
        • 2.2.2.5 SDRAM Column Address Strobe (CAS)
        • 2.2.2.6 SDRAM Chip Selects (SDCS[3:0])
        • 2.2.2.7 SDRAM Write Data Byte Mask (SDDM[3:0])
        • 2.2.2.8 SDRAM Data Strobe (SDDQS[3:0])
        • 2.2.2.9 SDRAM Clock (SDCLK[1:0])
        • 2.2.2.10 Inverted SDRAM Clock (SDCLK[1:0])
        • 2.2.2.11 SDRAM Write Enable (SDWE)
        • 2.2.2.12 SDRAM Clock Enable (SDCKE)
        • 2.2.2.13 SDR SDRAM Data Strobe (SDRDQS)
        • 2.2.2.14 SDRAM Reference Voltage (VREF)
      • 2.2.3 PCI Controller Signals
        • 2.2.3.1 PCI Address/Data Bus (PCIAD[31:0])
        • 2.2.3.2 Command/Byte Enables (PCICXBE[3:0])
        • 2.2.3.3 Device Select (PCIDEVSEL)
        • 2.2.3.4 Frame (PCIFRM)
        • 2.2.3.5 Initialization Device Select (PCIIDSEL)
        • 2.2.3.6 Initiator Ready (PCIIRDY)
        • 2.2.3.7 Parity (PCIPAR)
        • 2.2.3.8 Parity Error (PCIPERR)
        • 2.2.3.9 Reset (PCIRESET)
        • 2.2.3.10 System Error (PCISERR)
        • 2.2.3.11 Stop (PCISTOP)
        • 2.2.3.12 Target Ready (PCITRDY)
        • 2.2.3.13 External Bus Grant (PCIBG[4:1])
        • 2.2.3.14 External Bus Grant/Request Output (PCIBG0/PCIREQOUT)
        • 2.2.3.15 External Bus Request (PCIBR[4:0])
        • 2.2.3.16 External Request/Grant Input (PCIBR0/PCIGNTIN)
      • 2.2.4 Interrupt Control Signals
        • 2.2.4.1 Interrupt Request (IRQ[7:1])
      • 2.2.5 Clock and Reset Signals
        • 2.2.5.1 Reset In (RSTI)
        • 2.2.5.2 Reset Out (RSTO)
        • 2.2.5.3 Clock In (CLKIN)
      • 2.2.6 Reset Configuration Pins
        • 2.2.6.1 AD[12:8]-CLKIN to SDCLK Ratio (CLKCONFIG[4:0])
        • 2.2.6.2 AD5-FlexBus Size Configuration (FBSIZE)
        • 2.2.6.3 AD4-32-bit FlexBus Configuration (FBMODE)
        • 2.2.6.4 AD3-Byte Enable Configuration (BECONFIG)
        • 2.2.6.5 AD2-Auto Acknowledge Configuration (AACONFIG)
        • 2.2.6.6 AD[1:0]-Port Size Configuration (PSCONFIG)
      • 2.2.7 Ethernet Module Signals
        • 2.2.7.1 Management Data (E0MDIO, E1MDIO)
        • 2.2.7.2 Management Data Clock (E0MDC, E1MDC)
        • 2.2.7.3 Transmit Clock (E0TXCLK, E1TXCLK)
        • 2.2.7.4 Transmit Enable (E0TXEN, E1TXEN)
        • 2.2.7.5 Transmit Data 0 (E0TXD0, E1TXD0)
        • 2.2.7.6 Collision (E0COL, E1COL)
        • 2.2.7.7 Receive Clock (E0RXCLK, E1RXCLK)
        • 2.2.7.8 Receive Data Valid (E0RXDV, E1RXDV)
        • 2.2.7.9 Receive Data 0 (E0RXD0, E1RXD0)
        • 2.2.7.10 Carrier Receive Sense (E0CRS, E1CRS)
        • 2.2.7.11 Transmit Data 1-3 (E0TXD[3:1], E1TXD[3:1])
        • 2.2.7.12 Transmit Error (E0TXER, E1TXER)
        • 2.2.7.13 Receive Data 1-3 (E0RXD[3:1], E1RXD[3:1])
        • 2.2.7.14 Receive Error (E0RXER, E1RXER)
      • 2.2.8 Universal Serial Bus (USB)
        • 2.2.8.1 USB Differential Data (USBD+, USBD-)
        • 2.2.8.2 USBVBUS
        • 2.2.8.3 USBRBIAS
        • 2.2.8.4 USBCLKIN
        • 2.2.8.5 USBCLKOUT
      • 2.2.9 DMA Serial Peripheral Interface (DSPI) Signals
        • 2.2.9.1 DSPI Synchronous Serial Data Output (DSPISOUT)
        • 2.2.9.2 DSPI Synchronous Serial Data Input (DSPISIN)
        • 2.2.9.3 DSPI Serial Clock (DSPISCK)
        • 2.2.9.4 DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS)
        • 2.2.9.5 DSPI Chip Selects (DSPICS[2:3])
        • 2.2.9.6 DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS)
      • 2.2.10 FlexCAN Signals
        • 2.2.10.1 FlexCAN Transmit (CANTX0, CANTX1)
        • 2.2.10.2 FlexCAN Receive (CANRX0, CANRX1)
      • 2.2.11 I2C I/O Signals
        • 2.2.11.1 Serial Clock (SCL)
        • 2.2.11.2 Serial Data (SDA)
      • 2.2.12 PSC Module Signals
        • 2.2.12.1 Transmit Serial Data Output (PSC0TXD, PSC1TXD, PSC2TXD, PSC3TXD)
        • 2.2.12.2 Receive Serial Data Input (PSC0RXD, PSC1RXD, PSC2RXD, PSC3RXD)
        • 2.2.12.3 Clear-to-Send (PSCnCTS/PSCBCLK)
        • 2.2.12.4 Request-to-Send (PSCnRTS/PSCFSYNC)
      • 2.2.13 DMA Controller Module Signals
        • 2.2.13.1 DMA Request (DREQ[1:0])
        • 2.2.13.2 DMA Acknowledge (DACK[1:0])
      • 2.2.14 Timer Module Signals
        • 2.2.14.1 Timer Inputs (TIN[3:0])
        • 2.2.14.2 Timer Outputs (TOUT[3:0])
      • 2.2.15 Debug Support Signals
        • 2.2.15.1 Processor Clock Output (PSTCLK)
        • 2.2.15.2 Processor Status Debug Data (PSTDDATA[7:0])
        • 2.2.15.3 Development Serial Clock/Test Reset (DSCLK/TRST)
        • 2.2.15.4 Breakpoint/Test Mode Select (BKPT/TMS)
        • 2.2.15.5 Development Serial Input/Test Data Input (DSI/TDI)
        • 2.2.15.6 Development Serial Output/Test Data Output (DSO/TDO)
        • 2.2.15.7 Test Clock (TCK)
      • 2.2.16 Test Signals
        • 2.2.16.1 Test Mode (MTMOD[3:0])
      • 2.2.17 Power and Reference Pins
        • 2.2.17.1 Positive Pad Supply (EVDD)
        • 2.2.17.2 Positive Core Supply (IVDD)
        • 2.2.17.3 Ground (VSS)
        • 2.2.17.4 USB Power (USBVDD)
        • 2.2.17.5 USB Oscillator Power (USB_OSCVDD)
        • 2.2.17.6 USB PHY Power (USB_PHYVDD)
        • 2.2.17.7 USB Oscillator Analog Power (USB_OSCAVDD)
        • 2.2.17.8 USB PLL Analog Power (USB_PLLVDD)
        • 2.2.17.9 SDRAM Memory Supply (SDVDD)
        • 2.2.17.10 PLL Analog Power (PLLVDD)
        • 2.2.17.11 PLL Analog Ground (PLLVSS)
  • Part I Processor Core
    • Chapter 3 ColdFire Core
      • 3.1 Core Overview
      • 3.2 Features
        • 3.2.1 Enhanced Pipelines
          • 3.2.1.1 Instruction Fetch Pipeline (IFP)
            • 3.2.1.1.1 Branch Acceleration
          • 3.2.1.2 Operand Execution Pipeline (OEP)
            • 3.2.1.2.1 Illegal Opcode Handling
            • 3.2.1.2.2 Enhanced Multiply/Accumulate (EMAC) Unit
            • 3.2.1.2.3 Memory Management Unit (MMU)
            • 3.2.1.2.4 Floating Point Unit (FPU)
            • 3.2.1.2.5 Hardware Divide Unit
          • 3.2.1.3 Harvard Memory Architecture
        • 3.2.2 Debug Module Enhancements
      • 3.3 Programming Model
        • 3.3.1 User Programming Model
          • 3.3.1.1 Data Registers (D0-D7)
          • 3.3.1.2 Address Registers (A0-A6)
        • 3.3.2 User Stack Pointer (A7)
          • 3.3.2.1 Program Counter (PC)
          • 3.3.2.2 Condition Code Register (CCR)
        • 3.3.3 EMAC Programming Model
        • 3.3.4 FPU Programming Model
        • 3.3.5 Supervisor Programming Model
          • 3.3.5.1 Status Register (SR)
          • 3.3.5.2 Vector Base Register (VBR)
          • 3.3.5.3 Cache Control Register (CACR)
          • 3.3.5.4 Access Control Registers (ACR0-ACR3)
          • 3.3.5.5 RAM Base Address Registers (RAMBAR0 and RAMBAR1)
          • 3.3.5.6 Module Base Address Register (MBAR)
        • 3.3.6 Programming Model Table
      • 3.4 Data Format Summary
        • 3.4.1 Data Organization in Registers
          • 3.4.1.1 Integer Data Format Organization in Registers
          • 3.4.1.2 Integer Data Format Organization in Memory
        • 3.4.2 EMAC Data Representation
          • 3.4.2.1 Floating-Point Data Formats and Types
            • 3.4.2.1.1 Signed-Integer Data Formats
            • 3.4.2.1.2 Floating-Point Data Formats
      • 3.5 Addressing Mode Summary
      • 3.6 Instruction Set Summary
        • 3.6.1 Additions to the Instruction Set Architecture
        • 3.6.2 Instruction Set Summary
      • 3.7 Instruction Execution Timing
        • 3.7.1 MOVE Instruction Execution Timing
        • 3.7.2 One-Operand Instruction Execution Timing
        • 3.7.3 Two-Operand Instruction Execution Timing
        • 3.7.4 Miscellaneous Instruction Execution Timing
        • 3.7.5 Branch Instruction Execution Timing
        • 3.7.6 EMAC Instruction Execution Times
        • 3.7.7 FPU Instruction Execution Times
      • 3.8 Exception Processing Overview
        • 3.8.1 Exception Stack Frame Definition
        • 3.8.2 Processor Exceptions
      • 3.9 Precise Faults
    • Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC)
      • 4.1 Introduction
        • 4.1.1 MAC Overview
        • 4.1.2 General Operation
      • 4.2 Memory Map/Register Definition
        • 4.2.1 MAC Status Register (MACSR)
          • 4.2.1.1 Fractional Operation Mode
            • 4.2.1.1.1 Rounding
            • 4.2.1.1.2 Saving and Restoring the EMAC Programming Model
            • 4.2.1.1.3 MULS/MULU
            • 4.2.1.1.4 Scale Factor in MAC or MSAC Instructions
        • 4.2.2 Mask Register (MASK)
      • 4.3 EMAC Instruction Set Summary
        • 4.3.1 EMAC Instruction Execution Timing
        • 4.3.2 Data Representation
        • 4.3.3 EMAC Opcodes
    • Chapter 5 Memory Management Unit (MMU)
      • 5.1 Features
      • 5.2 Virtual Memory Management Architecture
        • 5.2.1 MMU Architecture Features
        • 5.2.2 MMU Architecture Location
        • 5.2.3 MMU Architecture Implementation
          • 5.2.3.1 Precise Faults
          • 5.2.3.2 MMU Access
          • 5.2.3.3 Virtual Mode
          • 5.2.3.4 Virtual Memory References
          • 5.2.3.5 Instruction and Data Cache Addresses
          • 5.2.3.6 Supervisor/User Stack Pointers
          • 5.2.3.7 Access Error Stack Frame
          • 5.2.3.8 Expanded Control Register Space
          • 5.2.3.9 Changes to ACRs and CACR
          • 5.2.3.10 ACR Address Improvements
          • 5.2.3.11 Supervisor Protection
      • 5.3 Debugging in a Virtual Environment
      • 5.4 Virtual Memory Architecture Processor Support
        • 5.4.1 Precise Faults
        • 5.4.2 Supervisor/User Stack Pointers
        • 5.4.3 Access Error Stack Frame Additions
      • 5.5 MMU Definition
        • 5.5.1 Effective Address Attribute Determination
        • 5.5.2 MMU Functionality
        • 5.5.3 MMU Organization
          • 5.5.3.1 MMU Base Address Register (MMUBAR)
          • 5.5.3.2 MMU Memory Map
          • 5.5.3.3 MMU Control Register (MMUCR)
          • 5.5.3.4 MMU Operation Register (MMUOR)
          • 5.5.3.5 MMU Status Register (MMUSR)
          • 5.5.3.6 MMU Fault, Test, or TLB Address Register (MMUAR)
          • 5.5.3.7 MMU Read/Write Tag and Data Entry Registers (MMUTR and MMUDR)
        • 5.5.4 MMU TLB
        • 5.5.5 MMU Operation
      • 5.6 MMU Implementation
        • 5.6.1 TLB Address Fields
        • 5.6.2 TLB Replacement Algorithm
        • 5.6.3 TLB Locked Entries
      • 5.7 MMU Instructions
    • Chapter 6 Floating-Point Unit (FPU)
      • 6.1 Introduction
        • 6.1.1 Overview
          • 6.1.1.1 Notational Conventions
      • 6.2 Operand Data Formats and Types
        • 6.2.1 Signed-Integer Data Formats
        • 6.2.2 Floating-Point Data Formats
        • 6.2.3 Floating-Point Data Types
          • 6.2.3.1 Normalized Numbers
          • 6.2.3.2 Zeros
          • 6.2.3.3 Infinities
          • 6.2.3.4 Not-A-Number
          • 6.2.3.5 Denormalized Numbers
      • 6.3 Register Definition
        • 6.3.1 Floating-Point Data Registers (FP0-FP7)
        • 6.3.2 Floating-Point Control Register (FPCR)
        • 6.3.3 Floating-Point Status Register (FPSR)
        • 6.3.4 Floating-Point Instruction Address Register (FPIAR)
      • 6.4 Floating-Point Computational Accuracy
        • 6.4.1 Intermediate Result
        • 6.4.2 Rounding the Result
      • 6.5 Floating-Point Post-Processing
        • 6.5.1 Underflow, Round, and Overflow
        • 6.5.2 Conditional Testing
      • 6.6 Floating-Point Exceptions
        • 6.6.1 Floating-Point Arithmetic Exceptions
          • 6.6.1.1 Branch/Set on Unordered (BSUN)
          • 6.6.1.2 Input Not-A-Number (INAN)
          • 6.6.1.3 Input Denormalized Number (IDE)
          • 6.6.1.4 Operand Error (OPERR)
          • 6.6.1.5 Overflow (OVFL)
          • 6.6.1.6 Underflow (UNFL)
          • 6.6.1.7 Divide-by-Zero (DZ)
          • 6.6.1.8 Inexact Result (INEX)
        • 6.6.2 Floating-Point State Frames
      • 6.7 Instructions
        • 6.7.1 Floating-Point Instruction Overview
        • 6.7.2 Floating-Point Instruction Execution Timing
        • 6.7.3 Key Differences between ColdFire and M68000 FPU Programming Models
    • Chapter 7 Local Memory
      • 7.1 Interactions between Local Memory Modules
      • 7.2 SRAM Overview
      • 7.3 SRAM Operation
      • 7.4 SRAM Register Definition
        • 7.4.1 SRAM Base Address Registers (RAMBAR0/RAMBAR1)
      • 7.5 SRAM Initialization
        • 7.5.1 SRAM Initialization Code
      • 7.6 Power Management
      • 7.7 Cache Overview
      • 7.8 Cache Organization
        • 7.8.1 Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified
        • 7.8.2 The Cache at Start-Up
      • 7.9 Cache Operation
        • 7.9.1 Caching Modes
          • 7.9.1.1 Cacheable Accesses
            • 7.9.1.1.1 Write-Through Mode (Data Cache Only)
            • 7.9.1.1.2 Copyback Mode (Data Cache Only)
          • 7.9.1.2 Cache-Inhibited Accesses
        • 7.9.2 Cache Protocol
          • 7.9.2.1 Read Miss
          • 7.9.2.2 Write Miss (Data Cache Only)
          • 7.9.2.3 Read Hit
          • 7.9.2.4 Write Hit (Data Cache Only)
        • 7.9.3 Cache Coherency (Data Cache Only)
        • 7.9.4 Memory Accesses for Cache Maintenance
          • 7.9.4.1 Cache Filling
          • 7.9.4.2 Cache Pushes
            • 7.9.4.2.1 Push and Store Buffers
            • 7.9.4.2.2 Push and Store Buffer Bus Operation
        • 7.9.5 Cache Locking
      • 7.10 Cache Register Definition
        • 7.10.1 Cache Control Register (CACR)
        • 7.10.2 Access Control Registers (ACR0-ACR3)
      • 7.11 Cache Management
      • 7.12 Cache Operation Summary
        • 7.12.1 Instruction Cache State Transitions
        • 7.12.2 Data Cache State Transitions
      • 7.13 Cache Initialization Code
    • Chapter 8 Debug Support
      • 8.1 Introduction
        • 8.1.1 Overview
      • 8.2 Signal Descriptions
        • 8.2.1 Processor Status/Debug Data (PSTDDATA[7:0])
      • 8.3 Real-Time Trace Support
        • 8.3.1 Begin Execution of Taken Branch (PST = 0x5)
        • 8.3.2 Processor Stopped or Breakpoint State Change (PST = 0xE)
        • 8.3.3 Processor Halted (PST = 0xF)
      • 8.4 Memory Map/Register Definition
        • 8.4.1 Revision A Shared Debug Resources
        • 8.4.2 Configuration/Status Register (CSR)
        • 8.4.3 PC Breakpoint ASID Control Register (PBAC)
        • 8.4.4 BDM Address Attribute Register (BAAR)
        • 8.4.5 Address Attribute Trigger Registers (AATR, AATR1)
        • 8.4.6 Trigger Definition Register (TDR)
        • 8.4.7 Program Counter Breakpoint and Mask Registers (PBRn, PBMR)
        • 8.4.8 Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1)
        • 8.4.9 Data Breakpoint and Mask Registers (DBR/DBR1, DBMR/DBMR1)
        • 8.4.10 PC Breakpoint ASID Register (PBASID)
        • 8.4.11 Extended Trigger Definition Register (XTDR)
          • 8.4.11.1 Resulting Set of Possible Trigger Combinations
      • 8.5 Background Debug Mode (BDM)
        • 8.5.1 CPU Halt
        • 8.5.2 BDM Serial Interface
          • 8.5.2.1 Receive Packet Format
          • 8.5.2.2 Transmit Packet Format
        • 8.5.3 BDM Command Set
          • 8.5.3.1 ColdFire BDM Command Format
            • 8.5.3.1.1 Extension Words as Required
          • 8.5.3.2 Command Sequence Diagrams
          • 8.5.3.3 Command Set Descriptions
            • 8.5.3.3.1 Read A/D Register (rareg/rdreg)
            • 8.5.3.3.2 Write A/D Register (wareg/wdreg)
            • 8.5.3.3.3 Read Memory Location (read)
            • 8.5.3.3.4 Write Memory Location (write)
            • 8.5.3.3.5 Dump Memory Block (dump)
            • 8.5.3.3.6 Fill Memory Block (fill)
            • 8.5.3.3.7 Resume Execution (go)
            • 8.5.3.3.8 No Operation (nop)
            • 8.5.3.3.9 Synchronize PC to the PSTDDATA Lines (sync_pc)
            • 8.5.3.3.10 Force Transfer Acknowledge (force_ta)
            • 8.5.3.3.11 Read Control Register (rcreg)
            • 8.5.3.3.12 BDM Accesses of the Stack Pointer Registers (A7: SSP and USP)
            • 8.5.3.3.13 BDM Accesses of the EMAC Registers
            • 8.5.3.3.14 BDM Accesses of Floating-Point Data Registers (FPn)
            • 8.5.3.3.15 Write Control Register (wcreg)
            • 8.5.3.3.16 Read Debug Module Register (rdmreg)
            • 8.5.3.3.17 Write Debug Module Register (wdmreg)
      • 8.6 Real-Time Debug Support
        • 8.6.1 Theory of Operation
          • 8.6.1.1 Emulator Mode
        • 8.6.2 Concurrent BDM and Processor Operation
      • 8.7 Debug C Definition of PSTDDATA Outputs
        • 8.7.1 User Instruction Set
        • 8.7.2 Supervisor Instruction Set
      • 8.8 ColdFire Debug History
        • 8.8.1 ColdFire Debug Classic: The Original Definition
        • 8.8.2 ColdFire Debug Revision B
        • 8.8.3 ColdFire Debug Revision C
          • 8.8.3.1 Debug Interrupts and Interrupt Requests (Emulator Mode)
      • 8.9 Freescale-Recommended BDM Pinout
  • Part II System Integration Unit
    • Chapter 9 System Integration Unit (SIU)
      • 9.1 Introduction
      • 9.2 Features
      • 9.3 Memory Map/Register Definition
        • 9.3.1 Module Base Address Register (MBAR)
          • 9.3.1.1 System Breakpoint Control Register (SBCR)
          • 9.3.1.2 SEC Sequential Access Control Register (SECSACR)
          • 9.3.1.3 Reset Status Register (RSR)
          • 9.3.1.4 JTAG Device Identification Number (JTAGID)
    • Chapter 10 Internal Clocks and Bus Architecture
      • 10.1 Introduction
        • 10.1.1 Block Diagram
        • 10.1.2 Clocking Overview
        • 10.1.3 Internal Bus Overview
        • 10.1.4 XL Bus Features
        • 10.1.5 Internal Bus Transaction Summaries
        • 10.1.6 XL Bus Interface Operations
          • 10.1.6.1 Basic Transfer Protocol
          • 10.1.6.2 Address Pipelines
      • 10.2 PLL
        • 10.2.1 PLL Memory Map/Register Descriptions
        • 10.2.2 System PLL Control Register (SPCR)
      • 10.3 XL Bus Arbiter
        • 10.3.1 Features
        • 10.3.2 Arbiter Functional Description
          • 10.3.2.1 Prioritization
          • 10.3.2.2 Bus Grant Mechanism
            • 10.3.2.2.1 Bus Grant
            • 10.3.2.2.2 Parking Modes
          • 10.3.2.3 Watchdog Functions
            • 10.3.2.3.1 Timer Functions
        • 10.3.3 XLB Arbiter Register Descriptions
          • 10.3.3.1 Arbiter Configuration Register (XARB_CFG)
          • 10.3.3.2 Arbiter Version Register (XARB_VER)
          • 10.3.3.3 Arbiter Status Register (XARB_SR)
          • 10.3.3.4 Arbiter Interrupt Mask Register (XARB_IMR)
          • 10.3.3.5 Arbiter Address Capture Register (XARB_ADRCAP)
          • 10.3.3.6 Arbiter Bus Signal Capture Register (XARB_SIGCAP)
          • 10.3.3.7 Arbiter Address Tenure Time Out Register (XARB_ADRTO)
          • 10.3.3.8 Arbiter Data Tenure Time Out Register (XARB_DATTO)
          • 10.3.3.9 Arbiter Bus Activity Time Out Register (XARB_BUSTO)
          • 10.3.3.10 Arbiter Master Priority Enable Register (XARB_PRIEN)
          • 10.3.3.11 Arbiter Master Priority Register (XARB_PRI)
    • Chapter 11 General Purpose Timers (GPT)
      • 11.1 Introduction
        • 11.1.1 Overview
        • 11.1.2 Modes of Operation
      • 11.2 External Signals
      • 11.3 Memory Map/Register Definition
        • 11.3.1 GPT Enable and Mode Select Register (GMSn)
        • 11.3.2 GPT Counter Input Register (GCIRn)
        • 11.3.3 GPT PWM Configuration Register (GPWMn)
        • 11.3.4 GPT Status Register (GSRn)
      • 11.4 Functional Description
        • 11.4.1 Timer Configuration Method
        • 11.4.2 Programming Notes
    • Chapter 12 Slice Timers (SLT)
      • 12.1 Introduction
        • 12.1.1 Overview
      • 12.2 Memory Map/Register Definition
        • 12.2.1 SLT Terminal Count Register (STCNTn)
        • 12.2.2 SLT Control Register (SCRn)
        • 12.2.3 SLT Timer Count Register (SCNTn)
        • 12.2.4 SLT Status Register (SSRn)
    • Chapter 13 Interrupt Controller
      • 13.1 Introduction
        • 13.1.1 68K/ColdFire Interrupt Architecture Overview
          • 13.1.1.1 Interrupt Controller Theory of Operation
            • 13.1.1.1.1 Interrupt Recognition
            • 13.1.1.1.2 Interrupt Prioritization
            • 13.1.1.1.3 Interrupt Vector Determination
      • 13.2 Memory Map/Register Descriptions
        • 13.2.1 Register Descriptions
          • 13.2.1.1 Interrupt Pending Registers (IPRH, IPRL)
          • 13.2.1.2 Interrupt Mask Register (IMRH, IMRL)
          • 13.2.1.3 Interrupt Force Registers (INTFRCH, INTFRCL)
          • 13.2.1.4 Interrupt Request Level Register (IRLR)
          • 13.2.1.5 Interrupt Acknowledge Level and Priority Register (IACKLPR)
          • 13.2.1.6 Interrupt Control Registers 1-63 (ICRn)
            • 13.2.1.6.1 Interrupt Sources
          • 13.2.1.7 Software and Level n IACK Registers (SWIACKR, L1IACK-L7IACK)
    • Chapter 14 Edge Port Module (EPORT)
      • 14.1 Introduction
      • 14.2 Interrupt/General-Purpose I/O Pin Descriptions
      • 14.3 Memory Map/Register Definition
        • 14.3.1 Memory Map
        • 14.3.2 Register Descriptions
          • 14.3.2.1 EPORT Pin Assignment Register (EPPAR)
          • 14.3.2.2 EPORT Data Direction Register (EPDDR)
          • 14.3.2.3 Edge Port Interrupt Enable Register (EPIER)
          • 14.3.2.4 Edge Port Data Register (EPDR)
          • 14.3.2.5 Edge Port Pin Data Register (EPPDR)
          • 14.3.2.6 Edge Port Flag Register (EPFR)
    • Chapter 15 GPIO
      • 15.1 Introduction
        • 15.1.1 Overview
        • 15.1.2 Features
      • 15.2 External Pin Description
      • 15.3 Memory Map/Register Definition
        • 15.3.1 Register Overview
        • 15.3.2 Register Descriptions
          • 15.3.2.1 Port x Output Data Registers (PODR_x)
            • 15.3.2.1.1 8-Bit PODR_x Registers
            • 15.3.2.1.2 7-Bit PODR_x Register
            • 15.3.2.1.3 5-Bit PODR_x Registers
            • 15.3.2.1.4 4-Bit PODR_x Registers
            • 15.3.2.1.5 FBCS Register (PODR_FBCS)
          • 15.3.2.2 Port x Data Direction Registers (PDDR_x)
            • 15.3.2.2.1 8-Bit PDDR_x Registers
            • 15.3.2.2.2 7-Bit PDDR_x Register
            • 15.3.2.2.3 5-Bit PDDR_x Registers
            • 15.3.2.2.4 4-Bit PDDR_x Registers
            • 15.3.2.2.5 FBCS Register (PDDR_FBCS)
          • 15.3.2.3 Port x Pin Data/Set Data Registers (PPDSDR_x)
            • 15.3.2.3.1 8-Bit PPDSDR_x Registers
            • 15.3.2.3.2 7-Bit PPDSDR_x Register
            • 15.3.2.3.3 5-Bit PPDSDR_x Registers
            • 15.3.2.3.4 4-Bit PPDSDR_x Registers
            • 15.3.2.3.5 FBCS Register (PPDSDR_FBCS)
          • 15.3.2.4 Port x Clear Output Data Registers (PCLRR_x)
            • 15.3.2.4.1 7-Bit PCLRR_x Register
            • 15.3.2.4.2 5-Bit PCLRR_x Registers
            • 15.3.2.4.3 4-Bit PCLRR_x Registers
            • 15.3.2.4.4 5-Bit PCLRR_FBCS Registers
          • 15.3.2.5 Port x Pin Assignment Registers (PAR_x)
            • 15.3.2.5.1 FlexBus Control Pin Assignment Register (PAR_FBCTL)
          • 15.3.2.6 FlexBus Chip Select Pin Assignment Register (PAR_FBCS)
          • 15.3.2.7 DMA Pin Assignment Register (PAR_DMA)
          • 15.3.2.8 FEC/I2C/IRQ Pin Assignment Register (PAR_FECI2CIRQ)
          • 15.3.2.9 PCI Grant Pin Assignment Register (PAR_PCIBG)
          • 15.3.2.10 PCI Request Pin Assignment Register (PAR_PCIBR)
          • 15.3.2.11 PSC3 Pin Assignment Register (PAR_PSC3)
          • 15.3.2.12 PSC2 Pin Assignment Register (PAR_PSC2)
          • 15.3.2.13 PSC1 Pin Assignment Register (PAR_PSC1)
          • 15.3.2.14 PSC0 Pin Assignment Register (PAR_PSC0)
          • 15.3.2.15 DSPI Pin Assignment Register (PAR_DSPI)
          • 15.3.2.16 General Purpose Timer Pin Assignment Register (PAR_TIMER)
      • 15.4 Functional Description
        • 15.4.1 Overview
  • Part III On-Chip Integration
    • Chapter 16 32-Kbyte System SRAM
      • 16.1 Introduction
        • 16.1.1 Block Diagram
        • 16.1.2 Features
        • 16.1.3 Overview
      • 16.2 Memory Map/Register Definition
        • 16.2.1 System SRAM Configuration Register (SSCR)
        • 16.2.2 Transfer Count Configuration Register (TCCR)
        • 16.2.3 Transfer Count Configuration Register-DMA Read Channel (TCCRDR)
        • 16.2.4 Transfer Count Configuration Register-DMA Write Channel (TCCRDW)
        • 16.2.5 Transfer Count Configuration Register-SEC (TCCRSEC)
      • 16.3 Functional Description
    • Chapter 17 FlexBus
      • 17.1 Introduction
        • 17.1.1 Overview
        • 17.1.2 Features
        • 17.1.3 Modes of Operation
      • 17.2 Byte Lanes
      • 17.3 Address Latch
      • 17.4 External Signals
        • 17.4.1 Chip-Select (FBCS[5:0])
        • 17.4.2 Address/Data Bus (AD[31:0])
        • 17.4.3 Address Latch Enable (ALE)
        • 17.4.4 Read/Write (R/W)
        • 17.4.5 Transfer Burst (TBST)
        • 17.4.6 Transfer Size (TSIZ[1:0])
        • 17.4.7 Byte Selects (BE/BWE[3:0])
        • 17.4.8 Output Enable (OE)
        • 17.4.9 Transfer Acknowledge (TA)
      • 17.5 Chip-Select Operation
        • 17.5.1 General Chip-Select Operation
          • 17.5.1.1 8-, 16-, and 32-Bit Port Sizing
          • 17.5.1.2 Global Chip-Select Operation
        • 17.5.2 Chip-Select Registers
          • 17.5.2.1 Chip-Select Address Registers (CSAR0-CSAR5)
          • 17.5.2.2 Chip-Select Mask Registers (CSMR0-CSMR5)
          • 17.5.2.3 Chip-Select Control Registers (CSCR0-CSCR5)
      • 17.6 Functional Description
        • 17.6.1 Data Transfer Operation
        • 17.6.2 Data Byte Alignment and Physical Connections
        • 17.6.3 Address/Data Bus Multiplexing
        • 17.6.4 Bus Cycle Execution
          • 17.6.4.1 Data Transfer Cycle States
        • 17.6.5 FlexBus Timing Examples
          • 17.6.5.1 Basic Read Bus Cycle
          • 17.6.5.2 Basic Write Bus Cycle
          • 17.6.5.3 Bus Cycle Multiplexing
          • 17.6.5.4 Timing Variations
            • 17.6.5.4.1 Wait States
            • 17.6.5.4.2 Address Setup and Hold
        • 17.6.6 Burst Cycles
        • 17.6.7 Misaligned Operands
        • 17.6.8 Bus Errors
    • Chapter 18 SDRAM Controller (SDRAMC)
      • 18.1 Introduction
      • 18.2 Overview
        • 18.2.1 Features
        • 18.2.2 Terminology
        • 18.2.3 Block Diagram
      • 18.3 External Signal Description
        • 18.3.1 SDRAM Data Bus (SDDATA[31:0])
        • 18.3.2 SDRAM Address Bus (SDADDR[12:0])
        • 18.3.3 SDRAM Bank Addresses (SDBA[1:0])
        • 18.3.4 SDRAM Row Address Strobe (RAS)
        • 18.3.5 SDRAM Column Address Strobe (CAS)
        • 18.3.6 SDRAM Chip Selects (SDCS[3:0])
        • 18.3.7 SDRAM Write Data Byte Mask (SDDM[3:0])
        • 18.3.8 SDRAM Data Strobe (SDDQS[3:0])
        • 18.3.9 SDRAM Clock (SDCLK[1:0])
        • 18.3.10 Inverted SDRAM Clock (SDCLK[1:0])
        • 18.3.11 SDRAM Write Enable (SDWE)
        • 18.3.12 SDRAM Clock Enable (SDCKE)
        • 18.3.13 SDR SDRAM Data Strobe (SDRDQS)
        • 18.3.14 SDRAM Memory Supply (SDVDD)
        • 18.3.15 SDRAM Reference Voltage (VREF)
      • 18.4 Interface Recommendations
        • 18.4.1 Supported Memory Configurations
        • 18.4.2 SDRAM SDR Connections
        • 18.4.3 SDRAM DDR Component Connections
        • 18.4.4 SDRAM DDR DIMM Connections
        • 18.4.5 DDR SDRAM Layout Considerations
          • 18.4.5.1 Termination Example
      • 18.5 SDRAM Overview
        • 18.5.1 SDRAM Commands
          • 18.5.1.1 Row and Bank Active Command (ACTV)
          • 18.5.1.2 Read Command (READ)
          • 18.5.1.3 Write Command (WRITE)
          • 18.5.1.4 Precharge All Banks Command (PALL)
          • 18.5.1.5 Load Mode/Extended Mode Register Command (LMR, LEMR)
            • 18.5.1.5.1 Mode Register Definition
            • 18.5.1.5.2 Extended Mode Register Definition
          • 18.5.1.6 Auto Refresh Command (REF)
          • 18.5.1.7 Self-Refresh (SREF) and Power-Down (PDWN) Commands
        • 18.5.2 Power-Up Initialization
          • 18.5.2.1 SDR Initialization
          • 18.5.2.2 DDR Initialization
      • 18.6 Functional Overview
        • 18.6.1 Page Management
        • 18.6.2 Transfer Size
      • 18.7 Memory Map/Register Definition
        • 18.7.1 SDRAM Drive Strength Register (SDRAMDS)
        • 18.7.2 SDRAM Chip Select Configuration Registers (CSnCFG)
        • 18.7.3 SDRAM Mode/Extended Mode Register (SDMR)
        • 18.7.4 SDRAM Control Register (SDCR)
        • 18.7.5 SDRAM Configuration Register 1 (SDCFG1)
        • 18.7.6 SDRAM Configuration Register 2 (SDCFG2)
      • 18.8 SDRAM Example
        • 18.8.1 SDRAM Signal Drive Strength Settings
        • 18.8.2 SDRAM Chip Select Settings
        • 18.8.3 SDRAM Configuration 1 Register Settings
        • 18.8.4 SDRAM Configuration 2 Register Settings
        • 18.8.5 SDRAM Control Register Settings and PALL command
        • 18.8.6 Set the Extended Mode Register
        • 18.8.7 Set the Mode Register and Reset DLL
        • 18.8.8 Issue a PALL command
        • 18.8.9 Perform Two Refresh Cycles
        • 18.8.10 Clear the Reset DLL Bit in the Mode Register
        • 18.8.11 Enable Automatic Refresh and Lock Mode Register
        • 18.8.12 Initialization Code
    • Chapter 19 PCI Bus Controller
      • 19.1 Introduction
        • 19.1.1 Block Diagram
        • 19.1.2 Overview
        • 19.1.3 Features
      • 19.2 External Signal Description
        • 19.2.1 Address/Data Bus (PCIAD[31:0])
        • 19.2.2 Command/Byte Enables (PCICXBE[3:0])
        • 19.2.3 Device Select (PCIDEVSEL)
        • 19.2.4 Frame (PCIFRAME)
        • 19.2.5 Initialization Device Select (PCIIDSEL)
        • 19.2.6 Initiator Ready (PCIIRDY)
        • 19.2.7 Parity (PCIPAR)
        • 19.2.8 PCI Clock (CLKIN)
        • 19.2.9 Parity Error (PCIPERR)
        • 19.2.10 Reset (PCIRESET)
        • 19.2.11 System Error (PCISERR)
        • 19.2.12 Stop (PCISTOP)
        • 19.2.13 Target Ready (PCITRDY)
      • 19.3 Memory Map/Register Definition
        • 19.3.1 PCI Type 0 Configuration Registers
          • 19.3.1.1 Device ID/Vendor ID Register (PCIIDR)-PCI Dword Addr 0
          • 19.3.1.2 PCI Status/Command Register (PCISCR)-PCI Dword Addr 1
          • 19.3.1.3 Revision ID/Class Code Register (PCICCRIR)-PCI Dword 3
          • 19.3.1.4 Configuration 1 Register (PCICR1)-PCI Dword 3
          • 19.3.1.5 Base Address Register 0 (PCIBAR0)-PCI Dword 4
          • 19.3.1.6 Base Address Register 1 (PCIBAR1)-PCI Dword 5
          • 19.3.1.7 CardBus CIS Pointer Register PCICCPR-PCI Dword A
          • 19.3.1.8 Subsystem ID/Subsystem Vendor ID Registers PCISID-PCI Dword B
          • 19.3.1.9 Expansion ROM Base Address PCIERBAR-PCI Dword C
          • 19.3.1.10 Capabilities Pointer (Cap_Ptr) PCICPR-PCI Dword D
          • 19.3.1.11 Configuration 2 Register (PCICR2)-PCI Dword F
        • 19.3.2 General Control/Status Registers
          • 19.3.2.1 Global Status/Control Register (PCIGSCR)
          • 19.3.2.2 Target Base Address Translation Register 0 (PCITBATR0)
          • 19.3.2.3 Target Base Address Translation Register 1 (PCITBATR1)
          • 19.3.2.4 Target Control Register (PCITCR)
          • 19.3.2.5 Initiator Window 0 Base/Translation Address Register (PCIIW0BTAR)
          • 19.3.2.6 Initiator Window 1 Base/Translation Address Register (PCIIW1BTAR)
          • 19.3.2.7 Initiator Window 2 Base/Translation Address Register (PCIIW2BTAR)
          • 19.3.2.8 Initiator Window Configuration Register (PCIIWCR)
          • 19.3.2.9 Initiator Control Register (PCIICR)
          • 19.3.2.10 Initiator Status Register (PCIISR)
          • 19.3.2.11 Configuration Address Register (PCICAR)
        • 19.3.3 Communication Subsystem Interface Registers
          • 19.3.3.1 Comm Bus FIFO Transmit Interface
            • 19.3.3.1.1 Tx Packet Size Register (PCITPSR)
            • 19.3.3.1.2 Tx Start Address Register (PCITSAR)
            • 19.3.3.1.3 Tx Transaction Control Register (PCITTCR)
            • 19.3.3.1.4 Tx Enables Register (PCITER)
            • 19.3.3.1.5 Tx Next Address Register (PCITNAR)
            • 19.3.3.1.6 Tx Last Word Register (PCITLWR)
            • 19.3.3.1.7 Tx Done Counts Register (PCITDCR)
            • 19.3.3.1.8 Tx Status Register (PCITSR)
            • 19.3.3.1.9 Tx FIFO Data Register (PCITFDR)
            • 19.3.3.1.10 Tx FIFO Status Register (PCITFSR)
            • 19.3.3.1.11 Tx FIFO Control Register (PCITFCR)
            • 19.3.3.1.12 Tx FIFO Alarm Register (PCITFAR)
            • 19.3.3.1.13 Tx FIFO Read Pointer Register (PCITFRPR)
            • 19.3.3.1.14 Tx FIFO Write Pointer Register (PCITFWPR)
          • 19.3.3.2 Comm Bus FIFO Receive Interface
            • 19.3.3.2.1 Rx Packet Size Register (PCIRPSR)
            • 19.3.3.2.2 Rx Start Address Register (PCIRSAR)
            • 19.3.3.2.3 Rx Transaction Control Register (PCIRTCR)
            • 19.3.3.2.4 Rx Enables Register (PCIRER)
            • 19.3.3.2.5 Rx Next Address Register (PCIRNAR)
            • 19.3.3.2.6 Rx Done Counts Register (PCIRDCR)
            • 19.3.3.2.7 Rx Status Register (PCIRSR)
            • 19.3.3.2.8 Rx FIFO Data Register (PCIRFDR)
            • 19.3.3.2.9 Rx FIFO Status Register (PCIRFSR)
            • 19.3.3.2.10 Rx FIFO Control Register (PCIRFCR)
            • 19.3.3.2.11 Rx FIFO Alarm Register (PCIRFAR)
            • 19.3.3.2.12 Rx FIFO Read Pointer Register (PCIRFRPR)
            • 19.3.3.2.13 Rx FIFO Write Pointer Register (PCIRFWPR)
      • 19.4 Functional Description
        • 19.4.1 PCI Bus Protocol
          • 19.4.1.1 PCI Bus Background
          • 19.4.1.2 Basic Transfer Control
          • 19.4.1.3 PCI Transactions
          • 19.4.1.4 PCI Bus Commands
          • 19.4.1.5 Addressing
            • 19.4.1.5.1 Memory Space Addressing
            • 19.4.1.5.2 I/O Space Addressing
            • 19.4.1.5.3 Configuration Space Addressing and Transactions
            • 19.4.1.5.4 Address Decoding
        • 19.4.2 Initiator Arbitration
          • 19.4.2.1 Priority Scheme
        • 19.4.3 Configuration Interface
        • 19.4.4 XL Bus Initiator Interface
          • 19.4.4.1 Endian Translation
          • 19.4.4.2 Configuration Mechanism
            • 19.4.4.2.1 Type 0 Configuration Translation
            • 19.4.4.2.2 Type 1 Configuration Translation
          • 19.4.4.3 Interrupt Acknowledge Transactions
          • 19.4.4.4 Special Cycle Transactions
          • 19.4.4.5 Transaction Termination
        • 19.4.5 XL Bus Target Interface
          • 19.4.5.1 Reads from Local Memory
          • 19.4.5.2 Local Memory Writes
          • 19.4.5.3 Data Translation
          • 19.4.5.4 Target Abort
          • 19.4.5.5 Latrule Disable
        • 19.4.6 Communication Subsystem Initiator Interface
          • 19.4.6.1 Access Width
          • 19.4.6.2 Addressing
          • 19.4.6.3 Data Translation
          • 19.4.6.4 Initialization
          • 19.4.6.5 Restart and Reset
          • 19.4.6.6 PCI Commands
          • 19.4.6.7 FIFO Considerations
          • 19.4.6.8 Alarms
          • 19.4.6.9 Bus Errors
        • 19.4.7 PCI Clock Scheme
        • 19.4.8 Interrupts
          • 19.4.8.1 PCI Bus Interrupts
          • 19.4.8.2 Internal Interrupt
      • 19.5 Application Information
        • 19.5.1 XL Bus-Initiated Transaction Mapping
        • 19.5.2 Address Maps
          • 19.5.2.1 Address Translation
            • 19.5.2.1.1 Inbound Address Translation
            • 19.5.2.1.2 Outbound Address Translation
            • 19.5.2.1.3 Base Address Register Overview
      • 19.6 XL Bus Arbitration Priority
    • Chapter 20 PCI Bus Arbiter Module
      • 20.1 Introduction
        • 20.1.1 Block Diagram
        • 20.1.2 Overview
        • 20.1.3 Features
      • 20.2 External Signal Description
        • 20.2.1 Frame (PCIFRM)
        • 20.2.2 Initiator Ready (PCIIRDY)
        • 20.2.3 PCI Clock (CLKIN)
        • 20.2.4 External Bus Grant (PCIBG[4:1])
        • 20.2.5 External Bus Grant/Request Output (PCIBG0/PCIREQOUT)
        • 20.2.6 External Bus Request (PCIBR[4:1])
        • 20.2.7 External Request/Grant Input (PCIBR0/PCIGNTIN)
      • 20.3 Register Definition
        • 20.3.1 PCI Arbiter Control Register (PACR)
        • 20.3.2 PCI Arbiter Status Register (PASR)
      • 20.4 Functional Description
        • 20.4.1 External PCI Requests
        • 20.4.2 Arbitration
          • 20.4.2.1 Hidden Bus Arbitration
          • 20.4.2.2 Arbitration Scheme
          • 20.4.2.3 Arbitration Latency
          • 20.4.2.4 Arbitration Examples
        • 20.4.3 Master Time-Out
      • 20.5 Reset
      • 20.6 Interrupts
    • Chapter 21 FlexCAN
      • 21.1 Introduction
        • 21.1.1 Block Diagram
        • 21.1.2 The CAN System
        • 21.1.3 Features
        • 21.1.4 Modes of Operation
          • 21.1.4.1 Normal Mode
          • 21.1.4.2 Freeze Mode
          • 21.1.4.3 Module Disabled Mode
          • 21.1.4.4 Loop-Back Mode
          • 21.1.4.5 Listen-Only Mode
      • 21.2 External Signals
        • 21.2.1 CANTX[1:0]
        • 21.2.2 CANRX[1:0]
      • 21.3 Memory Map/Register Definition
        • 21.3.1 FlexCAN Memory Map
        • 21.3.2 Register Descriptions
          • 21.3.2.1 FlexCAN Module Configuration Register (CANMCR)
          • 21.3.2.2 FlexCAN Control Register (CANCTRL)
          • 21.3.2.3 FlexCAN Timer Register (TIMER)
          • 21.3.2.4 Rx Mask Registers
            • 21.3.2.4.1 FlexCAN Rx Global Mask Register (RXGMASK)
            • 21.3.2.4.2 FlexCAN Rx 14 Mask Register (RX14MASK)
            • 21.3.2.4.3 FlexCAN Rx 15 Mask Register (RX15MASK)
          • 21.3.2.5 FlexCAN Error Counter Register (ERRCNT)
          • 21.3.2.6 FlexCAN Error and Status Register (ERRSTAT)
          • 21.3.2.7 Interrupt Mask Register (IMASK)
          • 21.3.2.8 Interrupt Flag Register (IFLAG)
      • 21.4 Functional Overview
        • 21.4.1 Message Buffer Structure
        • 21.4.2 Message Buffer Memory Map
        • 21.4.3 Transmit Process
        • 21.4.4 Arbitration Process
        • 21.4.5 Receive Process
          • 21.4.5.1 Self-Received Frames
        • 21.4.6 Message Buffer Handling
          • 21.4.6.1 Serial Message Buffers (SMBs)
          • 21.4.6.2 Transmit Message Buffer Deactivation
          • 21.4.6.3 Receive Message Buffer Deactivation
          • 21.4.6.4 Locking and Releasing Message Buffers
        • 21.4.7 CAN Protocol Related Frames
          • 21.4.7.1 Remote Frames
          • 21.4.7.2 Overload Frames
        • 21.4.8 Time Stamp
        • 21.4.9 Bit Timing
          • 21.4.9.1 Configuring the FlexCAN Bit Timing
        • 21.4.10 FlexCAN Error Counters
      • 21.5 FlexCAN Initialization Sequence
        • 21.5.1 Interrupts
    • Chapter 22 Integrated Security Engine (SEC)
      • 22.1 Features
      • 22.2 ColdFire Security Architecture
      • 22.3 Block Diagram
      • 22.4 Overview
        • 22.4.1 Bus Interface
        • 22.4.2 SEC Controller Unit
          • 22.4.2.1 Static EU Access
          • 22.4.2.2 Dynamic EU Access
        • 22.4.3 Crypto-Channels
        • 22.4.4 Execution Units (EUs)
          • 22.4.4.1 Data Encryption Standard Execution Unit (DEU)
          • 22.4.4.2 Arc Four Execution Unit (AFEU)
          • 22.4.4.3 Advanced Encryption Standard Execution Unit (AESU)
          • 22.4.4.4 Message Digest Execution Unit (MDEU)
          • 22.4.4.5 Random Number Generator (RNG)
      • 22.5 Memory Map/Register Definition
      • 22.6 Controller
        • 22.6.1 EU Access
        • 22.6.2 Multiple EU Assignment
        • 22.6.3 Multiple Channels
        • 22.6.4 Controller Registers
          • 22.6.4.1 EU Assignment Control Registers (EUACRH and EUACRL)
          • 22.6.4.2 EU Assignment Status Registers (EUASRH and EUASRL)
          • 22.6.4.3 SEC Interrupt Mask Registers (SIMRH and SIMRL)
          • 22.6.4.4 SEC Interrupt Status Registers (SISRH and SISRL)
          • 22.6.4.5 SEC Interrupt Control Registers (SICRH and SICRL)
          • 22.6.4.6 SEC ID Register (SIDR)
          • 22.6.4.7 SEC Master Control Register (SMCR)
          • 22.6.4.8 Master Error Address Register (MEAR)
      • 22.7 Channels
        • 22.7.1 Crypto-Channel Registers
          • 22.7.1.1 Crypto-Channel Configuration Registers (CCCRn)
          • 22.7.1.2 Crypto-Channel Pointer Status Registers (CCPSRHn and CCPSRLn)
          • 22.7.1.3 Crypto-Channel Current Descriptor Pointer Register (CDPRn)
          • 22.7.1.4 Fetch Register (FRn)
          • 22.7.1.5 Data Packet Descriptor Buffer (CDBUFn)
      • 22.8 ARC Four Execution Unit (AFEU)
        • 22.8.1 AFEU Register Map
        • 22.8.2 AFEU Reset Control Register (AFRCR)
        • 22.8.3 AFEU Status Register (AFSR)
        • 22.8.4 AFEU Interrupt Status Register (AFISR)
        • 22.8.5 AFEU Interrupt Mask Register (AFIMR)
      • 22.9 Data Encryption Standard Execution Units (DEU)
        • 22.9.1 DEU Register Map
        • 22.9.2 DEU Reset Control Register (DRCR)
        • 22.9.3 DEU Status Register (DSR)
        • 22.9.4 DEU Interrupt Status Register (DISR)
        • 22.9.5 DEU Interrupt Mask Register (DIMR)
      • 22.10 Message Digest Execution Unit (MDEU)
        • 22.10.1 MDEU Register Map
        • 22.10.2 MDEU Reset Control Register (MDRCR)
        • 22.10.3 MDEU Status Register (MDSR)
        • 22.10.4 MDEU Interrupt Status Register (MDISR)
        • 22.10.5 MDEU Interrupt Mask Register (MDIMR)
      • 22.11 RNG Execution Unit (RNG)
        • 22.11.1 RNG Register Map
        • 22.11.2 RNG Reset Control Register (RNGRCR)
        • 22.11.3 RNG Status Register (RNGSR)
        • 22.11.4 RNG Interrupt Status Register (RNGISR)
        • 22.11.5 RNG Interrupt Mask Register (RNGIMR)
      • 22.12 Advanced Encryption Standard Execution Units (AESU)
        • 22.12.1 AESU Register Map
        • 22.12.2 AESU Reset Control Register (AESRCR)
        • 22.12.3 AESU Status Register (AESSR)
        • 22.12.4 AESU Interrupt Status Register (AESISR)
        • 22.12.5 AESU Interrupt Mask Register (AESIMR)
      • 22.13 Descriptors
        • 22.13.1 Descriptor Structure
          • 22.13.1.1 Descriptor Header
          • 22.13.1.2 Descriptor Length and Pointer Fields
          • 22.13.1.3 Null Fields
          • 22.13.1.4 Next Descriptor Pointer
        • 22.13.2 Descriptor Chaining
        • 22.13.3 Descriptor Type Formats
        • 22.13.4 Descriptor Classes
          • 22.13.4.1 Dynamic Descriptors
          • 22.13.4.2 Static Descriptors
      • 22.14 EU Specific Data Packet Descriptors
        • 22.14.1 AFEU Mode Options and Data Packet Descriptors
          • 22.14.1.1 Dynamically Assigned AFEU
          • 22.14.1.2 Statically Assigned AFEU
        • 22.14.2 DEU Mode Options and Data Packet Descriptors
          • 22.14.2.1 Dynamically Assigned DEU
          • 22.14.2.2 Statically Assigned DEU
        • 22.14.3 MDEU Mode Options and Data Packet Descriptors
          • 22.14.3.1 Recommended Settings for MDEU Mode Register
          • 22.14.3.2 Dynamically Assigned MDEU
          • 22.14.3.3 Statically Assigned MDEU
        • 22.14.4 RNG Data Packet Descriptors
        • 22.14.5 AESU Mode Options and Data Packet Descriptors
          • 22.14.5.1 Dynamically Assigned AESU
          • 22.14.5.2 Statically Assigned AESU
          • 22.14.5.3 AESU-CCM Mode Descriptor
        • 22.14.6 Multi-Function Data Packet Descriptors
          • 22.14.6.1 Snooping
          • 22.14.6.2 Dynamic Multi-Function Descriptor Formats
          • 22.14.6.3 Static Multi-Function Descriptor Formats
          • 22.14.6.4 SSLv3.1/TLS 1.0 Processing Descriptors
            • 22.14.6.4.1 Outbound TLS Descriptors
            • 22.14.6.4.2 Inbound TLS Descriptors
    • Chapter 23 IEEE 1149.1 Test Access Port (JTAG)
      • 23.1 Introduction
        • 23.1.1 Block Diagram
        • 23.1.2 Features
        • 23.1.3 Modes of Operation
      • 23.2 External Signal Description
        • 23.2.1 Detailed Signal Description
          • 23.2.1.1 Test Mode 0 (MTMOD0)
          • 23.2.1.2 Test Clock Input (TCK)
          • 23.2.1.3 Test Mode Select/Breakpoint (TMS/BKPT)
          • 23.2.1.4 Test Data Input/Development Serial Input (TDI/DSI)
          • 23.2.1.5 Test Reset/Development Serial Clock (TRST/DSCLK)
          • 23.2.1.6 Test Data Output/Development Serial Output (TDO/DSO)
      • 23.3 Memory Map/Register Definition
        • 23.3.1 Memory Map
        • 23.3.2 Register Descriptions
          • 23.3.2.1 Instruction Shift Register (IR)
          • 23.3.2.2 IDCODE Register
          • 23.3.2.3 Bypass Register
          • 23.3.2.4 JTAG_CFM_CLKDIV Register
          • 23.3.2.5 TEST_CTRL Register
          • 23.3.2.6 Boundary Scan Register
      • 23.4 Functional Description
        • 23.4.1 JTAG Module
        • 23.4.2 TAP Controller
        • 23.4.3 JTAG Instructions
          • 23.4.3.1 External Test Instruction (EXTEST)
          • 23.4.3.2 IDCODE Instruction
          • 23.4.3.3 SAMPLE/PRELOAD Instruction
          • 23.4.3.4 ENABLE_TEST_CTRL Instruction
          • 23.4.3.5 HIGHZ Instruction
          • 23.4.3.6 CLAMP Instruction
          • 23.4.3.7 BYPASS Instruction
      • 23.5 Initialization/Application Information
        • 23.5.1 Restrictions
        • 23.5.2 Nonscan Chain Operation
  • Part IV Communications Subsystem
    • Chapter 24 Multichannel DMA
      • 24.1 Introduction
        • 24.1.1 Block Diagram
        • 24.1.2 Overview
          • 24.1.2.1 Master DMA Engine (MDE)
          • 24.1.2.2 Address and Data Sequencer (ADS)
          • 24.1.2.3 Priority-Task Decoder (PTD)
          • 24.1.2.4 Logic Unit with Redundancy Check (LURC)
          • 24.1.2.5 Debug Unit
        • 24.1.3 Features
      • 24.2 External Signals
        • 24.2.1 DREQ[1:0]
        • 24.2.2 DACK[1:0]
      • 24.3 Memory Map/Register Definitions
        • 24.3.1 DMA Task Memory
          • 24.3.1.1 Task Table
          • 24.3.1.2 Task Descriptor Table
          • 24.3.1.3 Variable Table
          • 24.3.1.4 Function Descriptor Table
          • 24.3.1.5 Context Save Space
        • 24.3.2 Memory Structure
        • 24.3.3 DMA Registers
          • 24.3.3.1 DMA Register Map
          • 24.3.3.2 Task Base Address Register (TaskBAR)
          • 24.3.3.3 Current Pointer (CP)
          • 24.3.3.4 End Pointer (EP)
          • 24.3.3.5 Variable Pointer (VP)
          • 24.3.3.6 PTD Control (PTD)
          • 24.3.3.7 DMA Interrupt Pending (DIPR)
          • 24.3.3.8 DMA Interrupt Mask Register (DIMR)
          • 24.3.3.9 Task Control Registers (TCRn)
          • 24.3.3.10 Priority Registers (PRIORn)
          • 24.3.3.11 Initiator Mux Control Register (IMCR)
          • 24.3.3.12 Task Size Registers (TSKSZ[0:1])
          • 24.3.3.13 Debug Comparator Registers (DBGCOMPn)
          • 24.3.3.14 Debug Control (DBGCTL)
          • 24.3.3.15 Debug Status (DBGSTAT)
          • 24.3.3.16 PTD Debug Registers
        • 24.3.4 External Request Module Registers
          • 24.3.4.1 External Request Module Register Map
          • 24.3.4.2 External Request Base Address Register (EREQBAR)
          • 24.3.4.3 External Request Address Mask Register (EREQMASK)
          • 24.3.4.4 External Request Control Register (EREQCTRL)
      • 24.4 Functional Description
        • 24.4.1 Tasks
        • 24.4.2 Descriptors
        • 24.4.3 Task Initialization
        • 24.4.4 Initiators
        • 24.4.5 Prioritization
        • 24.4.6 Context Switch
        • 24.4.7 Data Movement
        • 24.4.8 Data Manipulation
          • 24.4.8.1 LURC Features
        • 24.4.9 Line Buffers
          • 24.4.9.1 Combine Write Enable
          • 24.4.9.2 Read Line Enable
          • 24.4.9.3 Speculative Prefetch
        • 24.4.10 Termination of Loop
        • 24.4.11 Interrupts
        • 24.4.12 Debug Unit
      • 24.5 Programming Model
        • 24.5.1 Register Initialization
        • 24.5.2 Task Memory
          • 24.5.2.1 Task Table
      • 24.6 Timing Diagrams
        • 24.6.1 Level-Triggered Requests
        • 24.6.2 Edge-Triggered Requests
        • 24.6.3 Pipelined Requests
    • Chapter 25 Comm Timer Module (CTM)
      • 25.1 Introduction
        • 25.1.1 Block Diagrams
        • 25.1.2 Overview
        • 25.1.3 Comm Timer External Clock[7:0]
      • 25.2 Memory Map/Register Definition
        • 25.2.1 Timer Module Register Map
        • 25.2.2 Register Descriptions
          • 25.2.2.1 Comm Timer Configuration Register (CTCRn)-Fixed Timer Channel
          • 25.2.2.2 Comm Timer Configuration Register (CTCRn)-Variable Timer Channel
      • 25.3 Functional Description
        • 25.3.1 Variable Timer in Baud Clock Generator Mode
        • 25.3.2 Fixed Timer in Initiator Mode
          • 25.3.2.1 Fixed Timer in Initiator Mode Example
        • 25.3.3 Variable Timer in Initiator Mode
          • 25.3.3.1 Variable Timer in Initiator Mode Example
    • Chapter 26 Programmable Serial Controller (PSC)
      • 26.1 Introduction
        • 26.1.1 Block Diagram
        • 26.1.2 Overview
        • 26.1.3 Features
        • 26.1.4 Modes of Operation
      • 26.2 Signal Description
        • 26.2.1 PSCnCTS/PSCBCLK
        • 26.2.2 PScnrts/pscfsync
        • 26.2.3 PSCnrxd
        • 26.2.4 pscntxd
        • 26.2.5 Signal Properties in Each Mode
      • 26.3 Memory Map/Register Definition
        • 26.3.1 Overview
        • 26.3.2 Module Memory Map
        • 26.3.3 Register Descriptions
          • 26.3.3.1 Mode Register 1(PSCMR1n)
          • 26.3.3.2 Mode Register 2 (PSCMR2n)
          • 26.3.3.3 Status Register (PSCSRn)
          • 26.3.3.4 Clock Select Register (PSCCSRn)
          • 26.3.3.5 Command Register (PSCCRn)
          • 26.3.3.6 Receiver Buffer (PSCRBn) and Transmitter Buffer (PSCTBn)
          • 26.3.3.7 Input Port Change Register (PSCIPCRn)
          • 26.3.3.8 Auxiliary Control Register (PSCACRn)
          • 26.3.3.9 Interrupt Status Register (PSCISRn)
          • 26.3.3.10 Interrupt Mask Register (PSCIMRn)
          • 26.3.3.11 Counter Timer Registers (PSCCTURn, PSCCTLRn)
          • 26.3.3.12 Input Port (PSCIPn)
          • 26.3.3.13 Output Port Bit Set (PSCOPSETn)
          • 26.3.3.14 Output Port Bit Reset (PSCOPRESETn)
          • 26.3.3.15 PSC/IrDA Control Register (PSCSICRn)
          • 26.3.3.16 Infrared Control Register 1 (PSCIRCR1n)
          • 26.3.3.17 Infrared Control Register 2 (PSCIRCR2n)
          • 26.3.3.18 Infrared SIR Divide Register (PSCIRSDRn)
          • 26.3.3.19 Infrared MIR Divide Register (PSCIRMDRn)
          • 26.3.3.20 Infrared FIR Divide Register (PSCIRFDRn)
          • 26.3.3.21 Rx and Tx FIFO Counter Register (PSCRFCNTn, PSCTFCNTn)
          • 26.3.3.22 Rx and Tx FIFO Data Register (PSCRFDRn, PSCTFDRn)
          • 26.3.3.23 Rx and Tx FIFO Status Register (PSCRFSRn, PSCTFSRn)
          • 26.3.3.24 Rx and Tx FIFO Control Register (PSCRFCRn, PSCTFCRn)
          • 26.3.3.25 Rx and Tx FIFO Alarm Register (PSCRFARn, PSCTFARn)
          • 26.3.3.26 Rx and Tx FIFO Read Pointer (PSCRFRPn, PSCTFRPn)
          • 26.3.3.27 Rx and Tx FIFO Write Pointer (PSCRFWPn, PSCTFWPn)
          • 26.3.3.28 Rx and Tx FIFO Last Read Frame Pointer (PSCRLRFPn, PSCTLRFPn)
          • 26.3.3.29 Rx and Tx FIFO Last Write Frame Pointer (PSCRLWFPn, PSCTLWFPn)
      • 26.4 Functional Description
        • 26.4.1 UART Mode
        • 26.4.2 Multidrop Mode
        • 26.4.3 Modem8 Mode
        • 26.4.4 Modem16 Mode
        • 26.4.5 AC97 Mode
          • 26.4.5.1 Transmitter
          • 26.4.5.2 Receiver
          • 26.4.5.3 Low Power Mode
        • 26.4.6 SIR Mode
        • 26.4.7 MIR Mode
          • 26.4.7.1 Data Format
          • 26.4.7.2 Serial Interaction Pulse (SIP)
        • 26.4.8 FIR Mode
          • 26.4.8.1 Data Format
        • 26.4.9 PSC FIFO System
          • 26.4.9.1 RX FIFO
          • 26.4.9.2 TX FIFO
        • 26.4.10 Looping Modes
          • 26.4.10.1 Automatic Echo Mode
          • 26.4.10.2 Local Loopback Mode
          • 26.4.10.3 Remote Loopback Mode
      • 26.5 Resets
        • 26.5.1 General
        • 26.5.2 Description of Reset Operation
          • 26.5.2.1 Reset
          • 26.5.2.2 CRSRX
          • 26.5.2.3 CRSTX
          • 26.5.2.4 CRSES
      • 26.6 Interrupts
        • 26.6.1 Description of Interrupt Operation
          • 26.6.1.1 Processor Interrupt
      • 26.7 Software Environment
        • 26.7.1 General
        • 26.7.2 Configuration
          • 26.7.2.1 UART Mode
          • 26.7.2.2 Modem8 Mode
          • 26.7.2.3 Modem16 Mode
          • 26.7.2.4 AC97 Mode
          • 26.7.2.5 SIR Mode
          • 26.7.2.6 MIR Mode
          • 26.7.2.7 FIR Mode
        • 26.7.3 Programming
          • 26.7.3.1 MIR Mode
          • 26.7.3.2 FIR Mode
    • Chapter 27 DMA Serial Peripheral Interface (DSPI)
      • 27.1 Overview
      • 27.2 Features
      • 27.3 Block Diagram
      • 27.4 Modes of Operation
        • 27.4.1 Master Mode
        • 27.4.2 Slave Mode
      • 27.5 Signal Description
        • 27.5.1 Overview
        • 27.5.2 Detailed Signal Descriptions
          • 27.5.2.1 DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS)
          • 27.5.2.2 DSPI Peripheral Chip Selects 2-3 (DSPICS[2:3])
          • 27.5.2.3 DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS)
          • 27.5.2.4 DSPI Serial Input (DSPISIN)
          • 27.5.2.5 DSPI Serial Output (DSPISOUT)
          • 27.5.2.6 DSPI Serial Clock (DSPISCK)
      • 27.6 Memory Map and Registers
        • 27.6.1 DSPI Module Configuration Register (DMCR)
        • 27.6.2 DSPI Transfer Count Register (DTCR)
        • 27.6.3 DSPI Clock and Transfer Attributes Registers 0-7 (DCTARn)
        • 27.6.4 DSPI Status Register (DSR)
        • 27.6.5 DSPI DMA/Interrupt Request Select Register (DIRSR)
        • 27.6.6 DSPI Tx FIFO Register (DTFR)
        • 27.6.7 DSPI Rx FIFO Register (DRFR)
        • 27.6.8 DSPI Tx FIFO Debug Registers 0-3 (DTFDRn)
        • 27.6.9 DSPI Rx FIFO Debug Registers 0-3 (DRFDRn)
      • 27.7 Functional Description
        • 27.7.1 Start and Stop of DSPI Transfers
        • 27.7.2 Serial Peripheral Interface (SPI)
          • 27.7.2.1 Master Mode
          • 27.7.2.2 Slave Mode
          • 27.7.2.3 FIFO Disable Operation
          • 27.7.2.4 Tx FIFO Buffering Mechanism
            • 27.7.2.4.1 Filling the Tx FIFO
            • 27.7.2.4.2 Draining the Tx FIFO
          • 27.7.2.5 Rx FIFO Buffering Mechanism
            • 27.7.2.5.1 Filling the Rx FIFO
            • 27.7.2.5.2 Draining the Rx FIFO
        • 27.7.3 DSPI Baud Rate and Clock Delay Generation
          • 27.7.3.1 Baud Rate Generator
          • 27.7.3.2 CS to SCK Delay (tCSC)
          • 27.7.3.3 After DSPISCK Delay (tASC)
          • 27.7.3.4 Delay after Transfer (tDT)
          • 27.7.3.5 Peripheral Chip Select Strobe Enable (PCSS)
        • 27.7.4 Transfer Formats
          • 27.7.4.1 Classic SPI Transfer Format (CPHA = 0)
          • 27.7.4.2 Classic SPI Transfer Format (CPHA = 1)
          • 27.7.4.3 Modified SPI Transfer Format (MTFE = 1, CPHA = 0)
          • 27.7.4.4 Modified SPI Transfer Format (MTFE = 1, CPHA = 1)
          • 27.7.4.5 Continuous Selection Format
        • 27.7.5 Continuous Serial Communications Clock
        • 27.7.6 Interrupts/DMA Requests
          • 27.7.6.1 End of Queue Interrupt Request
          • 27.7.6.2 Transmit FIFO Fill Interrupt or DMA Request
          • 27.7.6.3 Transfer Complete Interrupt Request
          • 27.7.6.4 Transmit FIFO Underflow Interrupt Request
          • 27.7.6.5 Receive FIFO Drain Interrupt or DMA Request
          • 27.7.6.6 Receive FIFO Overflow Interrupt Request
      • 27.8 Initialization and Application Information
        • 27.8.1 How to Change Queues
        • 27.8.2 Baud Rate Settings
        • 27.8.3 Delay Settings
        • 27.8.4 Calculation of FIFO Pointer Addresses
          • 27.8.4.1 Address Calculation for the First-in Entry and Last-in Entry in the Tx FIFO
          • 27.8.4.2 Address Calculation for the First-in Entry and Last-in Entry in the Rx FIFO
    • Chapter 28 I2C Interface
      • 28.1 Introduction
        • 28.1.1 Block Diagram
        • 28.1.2 I2C Overview
        • 28.1.3 Features
      • 28.2 External Signals
      • 28.3 Memory Map/Register Definition
        • 28.3.1 I2C Register Map
        • 28.3.2 Register Descriptions
          • 28.3.2.1 I2C Address Register (I2ADR)
          • 28.3.2.2 I2C Frequency Divider Register (I2FDR)
          • 28.3.2.3 I2C Control Register (I2CR)
          • 28.3.2.4 I2C Status Register (I2SR)
          • 28.3.2.5 I2C Data I/O Register (I2DR)
          • 28.3.2.6 I2C Interrupt Control Register (I2ICR)
      • 28.4 Functional Description
        • 28.4.1 START Signal
        • 28.4.2 Slave Address Transmission
        • 28.4.3 STOP Signal
        • 28.4.4 Data Transfer
        • 28.4.5 Acknowledge
        • 28.4.6 Repeated Start
        • 28.4.7 Clock Synchronization and Arbitration
        • 28.4.8 Handshaking and Clock Stretching
      • 28.5 Initialization Sequence
        • 28.5.1 Transfer Initiation and Interrupt
        • 28.5.2 Post-Transfer Software Response
        • 28.5.3 Generation of STOP
        • 28.5.4 Generation of Repeated START
        • 28.5.5 Slave Mode
        • 28.5.6 Arbitration Lost
        • 28.5.7 Flow Control
    • Chapter 29 USB 2.0 Device Controller
      • 29.1 Introduction
        • 29.1.1 Overview
        • 29.1.2 Features
        • 29.1.3 Block Diagram
          • 29.1.3.1 Controller and Synchronization
          • 29.1.3.2 Descriptor RAM
          • 29.1.3.3 FIFO Controller
          • 29.1.3.4 FIFO RAM Manager
          • 29.1.3.5 Integrated USB 2.0 Transceiver
            • 29.1.3.5.1 USB Differential Data (USBD+, USBD-)
            • 29.1.3.5.2 USBVBUS
            • 29.1.3.5.3 USBRBIAS
            • 29.1.3.5.4 USBCLKIN
            • 29.1.3.5.5 USBCLKOUT
      • 29.2 Memory Map/Register Definition
        • 29.2.1 USB Memory Map
        • 29.2.2 USB Request, Control, and Status Registers
          • 29.2.2.1 USB Status Register (USBSR)
          • 29.2.2.2 USB Control Register (USBCR)
          • 29.2.2.3 USB Descriptor RAM Control Register (DRAMCR)
          • 29.2.2.4 USB Descriptor RAM Data Register (DRAMDR)
          • 29.2.2.5 USB Interrupt Status Register (USBISR)
          • 29.2.2.6 USB Interrupt Mask Register (USBIMR)
          • 29.2.2.7 USB Application Interrupt Status Register (USBAISR)
          • 29.2.2.8 USB Application Interrupt Mask Register (USBAIMR)
          • 29.2.2.9 Endpoint Info Register (EPINFO)
          • 29.2.2.10 USB Configuration Value Register (CFGR)
          • 29.2.2.11 USB Configuration Attribute Register (CFGAR)
          • 29.2.2.12 USB Device Speed Register (SPEEDR)
          • 29.2.2.13 USB Frame Number Register (FRMNUMR)
          • 29.2.2.14 USB Endpoint Transaction Number Register (EPTNR)
          • 29.2.2.15 USB Application Interface Update Register (IFUR)
          • 29.2.2.16 USB Configuration Interface Register (IFRn)
        • 29.2.3 USB Counter Registers
          • 29.2.3.1 USB Packet Passed Count Register (PPCNT)
          • 29.2.3.2 USB Dropped Packet Counter Register (DPCNT)
          • 29.2.3.3 USB CRC Error Counter Register (CRCECNT)
          • 29.2.3.4 USB Bitstuffing Error Counter Register (BSECNT)
          • 29.2.3.5 USB PID Error Counter Register (PIDECNT)
          • 29.2.3.6 USB Framing Error Counter Register (FRMECNT)
          • 29.2.3.7 USB Transmitted Packet Counter Register (TXPCNT)
          • 29.2.3.8 USB Counter Overflow Register (CNTOVR)
        • 29.2.4 Endpoint Context Registers
          • 29.2.4.1 Endpoint n Attribute Control Register (EP0ACR, EPnOUTACR, EPnINACR)
          • 29.2.4.2 Endpoint n Max Packet Size Register (EP0MPSR, EPnOUTMPSR, EPnINMPSR)
          • 29.2.4.3 Endpoint n Interface Number Register (EP0IFR, EPnOUTIFR, EPnINIFR)
          • 29.2.4.4 Endpoint n Status Register (EP0SR, EPnOUTSR, EPnINSR)
          • 29.2.4.5 bmRequest Type Register (BMRTR)
          • 29.2.4.6 bRequest Type Register (BRTR)
          • 29.2.4.7 wValue Register (WVALUER)
          • 29.2.4.8 wIndex Register (WINDEXR)
          • 29.2.4.9 wLength Register (WLENGTHR)
          • 29.2.4.10 Endpoint n Sync Frame Register (EPnOUTSFR, EPnINSFR)
        • 29.2.5 USB Endpoint FIFO Registers
          • 29.2.5.1 USB Endpoint n Status and Control Register (EPnSTAT)
          • 29.2.5.2 USB Endpoint n Interrupt Status Register (EPnISR)
          • 29.2.5.3 USB Endpoint n Interrupt Mask Register (EPnIMR)
          • 29.2.5.4 USB Endpoint n FIFO RAM Configuration Register (EPnFRCFGR)
          • 29.2.5.5 USB Endpoint n FIFO Data Register (EPnFDR)
          • 29.2.5.6 USB Endpoint n FIFO Status Register (EPnFSR)
          • 29.2.5.7 USB Endpoint n FIFO Control Register (EPnFCR)
          • 29.2.5.8 USB Endpoint n FIFO Alarm Register (EPnFAR)
          • 29.2.5.9 USB Endpoint n FIFO Read Pointer (EPnFRP)
          • 29.2.5.10 USB Endpoint n FIFO Write Pointer (EPnFWP)
          • 29.2.5.11 USB Endpoint n Last Read Frame Pointer (EPnLRFP)
          • 29.2.5.12 USB Endpoint n Last Write Frame Pointer (EPnLWFP)
      • 29.3 Functional Description
        • 29.3.1 Interrupts
      • 29.4 Software Interface
        • 29.4.1 Device Initialization
          • 29.4.1.1 USB Descriptor Download
          • 29.4.1.2 USB Interrupt Register
          • 29.4.1.3 Endpoint Registers
            • 29.4.1.3.1 USB Endpoint to FIFO Mapping
          • 29.4.1.4 FIFO Sizes
          • 29.4.1.5 Enable the Device
        • 29.4.2 Exception Handling
          • 29.4.2.1 Unable to Fill or Empty FIFO Due to Temporary Problem
          • 29.4.2.2 Catastrophic Error
        • 29.4.3 Data Transfer Operations
          • 29.4.3.1 USB Packets
            • 29.4.3.1.1 Handshakes
            • 29.4.3.1.2 Short Packets
          • 29.4.3.2 Sending Packets
          • 29.4.3.3 Receiving Packets
            • 29.4.3.3.1 Programming the FIFO Controller
          • 29.4.3.4 USB Transfers
            • 29.4.3.4.1 Data Transfers to the Host
            • 29.4.3.4.2 Data Transfers to the Device
          • 29.4.3.5 Control Transfers
            • 29.4.3.5.1 Default Control Pipe
            • 29.4.3.5.2 Device Requests
          • 29.4.3.6 Bulk Traffic
            • 29.4.3.6.1 Bulk OUT
            • 29.4.3.6.2 Bulk IN
          • 29.4.3.7 Interrupt Traffic
          • 29.4.3.8 Isochronous Operations
            • 29.4.3.8.1 Isochronous Transfer Summary
    • Chapter 30 Fast Ethernet Controller (FEC)
      • 30.1 Introduction
        • 30.1.1 MCF548x Family Products
        • 30.1.2 Block Diagram
        • 30.1.3 Overview
        • 30.1.4 Features
        • 30.1.5 Modes of Operation
          • 30.1.5.1 Full and Half Duplex Operation
          • 30.1.5.2 Interface Options
            • 30.1.5.2.1 10 Mbps and 100 Mbps MII Interface
            • 30.1.5.2.2 10 Mpbs 7-Wire Interface Operation
          • 30.1.5.3 Address Recognition Options
          • 30.1.5.4 Internal Loopback
      • 30.2 External Signals
        • 30.2.1 Transmit Clock (EnTXCLK)
        • 30.2.2 Receive Clock (EnRXCLK)
        • 30.2.3 Transmit Enable (EnTXEN)
        • 30.2.4 Transmit Data[3:0] (EnTXD[3:0])
        • 30.2.5 Transmit Error (EnTXER)
        • 30.2.6 Receive Data Valid (EnRXDV)
        • 30.2.7 Receive Data[3:0] (EnRXD[3:0])
        • 30.2.8 Receive Error (EnRXER)
        • 30.2.9 Carrier Sense (EnCRS)
        • 30.2.10 Collision (EnCOL)
        • 30.2.11 Management Data Clock (EnMDC)
        • 30.2.12 Management Data (EnMDIO)
      • 30.3 Memory Map/Register Definition
        • 30.3.1 Top Level Module Memory Map
        • 30.3.2 Detailed Memory Map (Control/Status Registers)
        • 30.3.3 MIB Block Counters Memory Map
          • 30.3.3.1 Ethernet Interrupt Event Register (EIR)
          • 30.3.3.2 Interrupt Mask Register (EIMR)
          • 30.3.3.3 Ethernet Control Register (ECR)
          • 30.3.3.4 MII Management Frame Register (MMFR)
            • 30.3.3.4.1 Generating a Write Frame
            • 30.3.3.4.2 Generating a Read Frame
          • 30.3.3.5 MII Speed Control Register (MSCR)
          • 30.3.3.6 MIB Control Register (MIBC)
          • 30.3.3.7 Receive Control Register (RCR)
          • 30.3.3.8 Receive Hash Register (RHR)
          • 30.3.3.9 Transmit Control Register (TCR)
          • 30.3.3.10 Physical Address Low Register (PALR)
          • 30.3.3.11 Physical Address High Register (PAHR)
          • 30.3.3.12 Opcode/Pause Duration Register (OPD)
          • 30.3.3.13 Individual Address Upper Register (IAUR)
          • 30.3.3.14 Individual Address Lower Register (IALR)
          • 30.3.3.15 Group Address Upper Register (GAUR)
          • 30.3.3.16 Group Address Lower Register (GALR)
          • 30.3.3.17 FEC Transmit FIFO Watermark Register (FECTFWR)
          • 30.3.3.18 FEC Receive FIFO Data Register (FECRFDR)
          • 30.3.3.19 FEC Receive FIFO Status Register (FECRFSR)
          • 30.3.3.20 FEC Receive FIFO Control Register (FECRFCR)
          • 30.3.3.21 FEC Receive FIFO Last Read Frame Pointer Register (FECRLRFP)
          • 30.3.3.22 FEC Receive FIFO Last Write Frame Pointer Register (FECRLWFP)
          • 30.3.3.23 FEC Receive FIFO Alarm Register (FECRFAR)
          • 30.3.3.24 FEC Receive FIFO Read Pointer Register (FECRFRP)
          • 30.3.3.25 FEC Receive FIFO Write Pointer Register (FECRFWP)
          • 30.3.3.26 FEC Transmit FIFO Data Register (FECTFDR)
          • 30.3.3.27 FEC Transmit FIFO Status Register (FECTFSR)
          • 30.3.3.28 FEC Transmit FIFO Control Register (FECTFCR)
          • 30.3.3.29 FEC Transmit FIFO Last Read Frame Pointer Register (FECTLRFP)
          • 30.3.3.30 FEC Transmit FIFO Last Write Frame Pointer Register (FECTLWFP)
          • 30.3.3.31 FEC Transmit FIFO Alarm Register (FECTFAR)
          • 30.3.3.32 FEC Transmit FIFO Read Pointer Register (FECTFRP)
          • 30.3.3.33 FEC Transmit FIFO Write Pointer Register (FECTFWP)
          • 30.3.3.34 FEC FIFO Reset Register (FECFRST)
          • 30.3.3.35 FEC CRC and Transmit Frame Control Word Register (FECCTCWR)
      • 30.4 Functional Description
        • 30.4.1 Initialization Sequence
          • 30.4.1.1 Hardware Controlled Initialization
          • 30.4.1.2 User Initialization (Prior to Asserting ECR[ETHER_EN])
        • 30.4.2 Frame Control/Status Words
          • 30.4.2.1 Receive Frame Status Word (RFSW)
          • 30.4.2.2 Transmit Frame Control Word (TFCW)
        • 30.4.3 Network Interface Options
        • 30.4.4 FEC Frame Transmission
        • 30.4.5 FEC Frame Reception
        • 30.4.6 Ethernet Address Recognition
        • 30.4.7 Hash Algorithm
        • 30.4.8 Full Duplex Flow Control
        • 30.4.9 Inter-Packet Gap (IPG) Time
        • 30.4.10 Collision Handling
        • 30.4.11 Internal and External Loopback
        • 30.4.12 Ethernet Error-Handling Procedure
          • 30.4.12.1 Transmission Errors
            • 30.4.12.1.1 Transmitter Underrun
            • 30.4.12.1.2 Retransmission Attempts Limit Expired
            • 30.4.12.1.3 Late Collision
            • 30.4.12.1.4 Heartbeat
          • 30.4.12.2 Reception Errors
            • 30.4.12.2.1 Overrun Error
            • 30.4.12.2.2 Non-Octet Error (Dribbling Bits)
            • 30.4.12.2.3 CRC Error
            • 30.4.12.2.4 Frame Length Violation
            • 30.4.12.2.5 Truncation
        • 30.4.13 MII Data Frame
        • 30.4.14 MII Management Frame Structure
  • Part V Mechanical
    • Chapter 31 Mechanical Data
      • 31.1 Package
      • 31.2 Pinout
      • 31.3 Mechanical Diagrams
        • 31.3.1 MCF5485/5484 Mechanical Diagram
        • 31.3.2 MCF5483/5482 Mechanical Diagram
      • 31.4 MCF5481/5480 Mechanical Diagram
      • 31.5 Mechanicals 388-pin PBGA Package Outline
      • 31.6 Case Drawing
    • Appendix A MCF548x Memory Map
      • A
      • B
      • C
      • D
      • E
      • F
      • G
      • H
      • I
      • J
      • L
      • M
      • P
      • R
      • S
      • T
      • U
  • Index